1991_Hitatchi_8_16_Bit_Microprocessor_Data_Book 1991 Hitatchi 8 16 Bit Microprocessor Data Book
User Manual: 1991_Hitatchi_8_16_Bit_Microprocessor_Data_Book
Open the PDF directly: View PDF 
.
Page Count: 1006
| Download | |
| Open PDF In Browser | View PDF |
8/16-BIT MICROPROCESSOR
DATA BOOK
~HITACHI®
M21T132
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without
notice.
2.
All rights are reserved: No one is permitted to reproduce or duplicate, in
any form, the whole or part of this document without Hitachi's permission.
3.
Hitachi will not be held responsible for aIiy damage to the user that may
result from accidents or any other reasons during operation of the user's
unit according to this document.
4.
Circuitry and other examples describe,d herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims
or other problems that may result from applications based on the examples
described herein.
5.
No license is granted by implication or otherwise under any patents or
other rights of any third party or Hitachi, Ltd.
6.
MEDICAL APPLICATIONS: Hitachi's products are not authorized for
use in MEDICAL APPLICATIONS without the written consent of the
appropriate officer of Hitachi's sales company. Such use includes, but is
not limited to, use in life support systems. Buyers of Hitachi's products are
requested to notify the relevant Hitachi sales offices when planning to use
the products in MEDICAL APPLICATIONS.
September 1991
@Copyright 1991, Hitachi America, Ltd.
Printed in U.S.A.
INDEX
8/16-Bit Microprocessor Data Book
General Information
DATA SHEETS
HD6300, HD6800 8-Bit Microcomputer Family
HD64180 8-Bit Microprocessor Family
HD68000 16-Bit Microprocessor Family
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
iii
CONTENTS
SECTION 1
•
GENERAL INFORMATION
• Quick Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ix
• Introduction of Packages ........................................................................ .
• Sockets for Evaluating Surface and Through-Hole Mount Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
• Device Packing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
• Reliability and Quality Assurance ................................................ . . . . . . . . . . . . . . . . .
23
• Reliability Test Data of Microcomputer ........................................................... "
29
• Program Development and Support System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
• Device Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
SECTION 2
•
DATA SHEETS
HD6303RI A03R/B03R
HD6303XI A03X/B03X
CMOS Microprocessing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS Microprocessing Unit .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
86
HD6303Y I A03Y IB03Y IC03Y
CMOS Microprocessing Unit ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 127
HD6305X21 A05X2/B05X2
CMOS Microcomputer Unit .................................... " '"
HD6305Y21 A05Y2/B05Y2
CMOS Microcomputer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 202
HD63B09/C09
CMOS Microprocessing Unit . ,....... , . , ............ , . . . . . . . . . . . . . . .. 232
HD63B09E/C09E
CMOS Microprocessing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 277
HD6802
Microprocessing with Clock and RAM ... , . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
HD6802W
Microprocessing with Clock and RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 327
HD6803/6803-1
Microprocessing Unit. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 340
171
314
HD68091 A09/B09
Microprocessing Unit. ................... , . . . . . . . . . . . . . . . . . . . . . . . . .. 367
HD6809EI A09E/B09E
Microproccesing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 400
SECTION 3
HD64180R/Z
Microprocessing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 435
HD64180S
Network Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 568
HD641180X/3180XI7180X
Microcontroller Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 697
HD648180W
Microcontroller Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 793
SECTION 4
HD68000/HCOOO
Microprocessor Unit ............................................... 907
• Hitachi Sales Offices ................................................. , . . . . . . . . . . . . . . . . . . . . . . . . . .. 992
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
v
8/16-BIT MICROPROCESSOR DATA BOOK
Section One
General Information
• Quick Reference Guide
• Introduction of Packages
• Sockets
• Device Packing
• Reliability and Ouality Assurance
• Reliability lest Data of Microcomputer
• Program Development and Support System
• Device Availability
•
HITACHI
QUICK REFERENCE GUIDE
• NMOS 8-BIT MICROPROCESSOR
Type No.
HD6809
HD68A09
HD68B09
HD6803
HD6803·1
HD6809E
HD68A09E
HD68B09E
HD6802
HD6802W
Clock Frequency (MHz)
1.0
1.0
1.0 (HD6803)
1.25 (HD680J.l)
1.0 (HD6809)
1.5 (HD68A09)
2.0 (HD68B09)
1.0 (HD6B09E)
1.5 (HD68A09E)
2D (HD68B09E)
Supply Voltage (V)
5.0
5.0
5.0
5.0
5.0
-20-+75
-20-+75
0-+70
-20-+75
-20-+75
RAM (byte)
128
256
128
-
-
Oscillator
Ves
Ves
Ves
Ves
-
DP-40
DP-40
DP-40
DP·40
DP-40
Operating Temperature'
(oC)
Package
01 nternal oscillator and RAM
added to the H D6800
032 byte RAM Battery backed
up possible
Features
Compatibility
MC6802
-
o Full software
o Upward instruc· o The highest
tion compatibil· version of the
compatibil ity
ity with the
with the
HMCS6800
family
HD6BOO
HD6809
oOn·chip SCI
o Powerful ad·
oBus employ·
and timer
dressing modes ment on time
o Easy relocat·
sharing basis
able/reentrant o External clock
programming
MC6809
MC68A09
MC68B09
MC6B03
MC6BOJ.l
MC6B09E
MC68A09E
MC6BB09E
• Wide Temperature Range 1-40-+8S"C) version is lVIil.ble.
~HITACHI
Hitachi America, Ltd.
0
Hitachi Plaza 0 2000 Sierra Point Pkwy.
0
Brisbane, CA 94005-1819 • (415) 589-8300
ix
Quick Reference Guide
• CMOS 8-BIT MICROPROCESSOR
Type No.
Clock Frequency (MHz)
HD6303R
HD63A03R
HD63B03R
HD6303X
HD63A03X
HD63B03X
1.0 (HD6303R)
1.5 (HD63A03R)
2.0 (HD63B03R)
1.0 (HD6303X)
1.5 (HD63A03X)
2.0 (HD63B03X)
HD6303Y
HD63A03Y
HD63B03Y
HD63C03Y
1.0 (HD6303Y)
1.5 (HD63A03Y)
2.0 (HD63B03Y)
3.0 (HD63C03Y)
5.0
5.0
5.0
0-+70
0-+70
0-+70
RAM (byte)
12B
192
256
External Memory Expansion (byte)
65k
6Sk
6Sk
DP-40, FP-54
CG-40, CP-52, CP-44
DP·64S, FP·BO,
CP·68
Dp·64S, FP-64,
CP-68
Supply Voltage (V)
Operating Temperature" (oC)
Package
• On-chip timer and synchronous/asynchronous SCI
• Upward instruction compatibility with the HD6BOO
Features
• Low power consumption modes (sleep and standby)
HD6305X2
HD63A05X2
HD63B05X2
HD6305Y2
HD63A05Y2
HD63B05Y2
HD63B09/E
HD63C09/E
HD64180R/Z
1.0 (HD6305X2)
1.5 (HD63A05X2)
2.0 (HD63B05X2)
1.0 (HD6305Y2)
1.5 (HD63A05Y2)
2.0 (HD63B05Y2)
2.0 (HD63B09/E)
3.0 (HD63C09/E)
6.0 (HD64180R/Z-6)
8.0 (HD64180R/Z-8)
10.0 (HD64180R/Z-l0)
5.0
5.0
5.0
5.0
0- +70
0- +70
-20- + 75
-20- +75
RAM (byte)
128
256
External Memory
Expansion (byte)
16k
16k
65k
512k11M'
DP-64S, FP-64
DP-64S, FP-64
DP-40
CP-44
DP-64S
CP-68
FP-80
• Software compatibility
with the HD6809/E
• Easy relocatable/
reentrant programming
• Flexible system
expansion capabilities
• Powerful addressing
mode
• On-chip MMU, DMAC,
synchronous/
asynchronous SCI and
timer
• Software compatibility
with Z80/8080
• R version-68/63, 80xx
interface
• Z version-Z80 interface
Type No.
Clock Frequency (MHz)
Supply Voltage (V)
Operating Temperature' (oG)
Package
Features
• On-chip timer and synchronous SCI
• Powerful bit manipulation instruction
• Low power consumption modes (wait,
stop and standby)
-
-
~HITACHI
x
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
Quick Reference Guide
HD641BOS
HD6411BOX
HD6431 BOX
HD6471BOX
B.O (HD641 BOSLP-B)
100 (HD641 BOSLP-10)
4.0 (HD6411BOX-4)
6 0 (HD6411BOX-6)
S.O (HD6411S0X-SL)
4 0 (HD6431 BOX-4)
60 (HD6431BOX-6)
SO (HD6431S0X-SL)
4.0 (HD6471 BOX-4)
6.0 (HD6471BOX-6)
B.O (HD6471 BOX-SL)
5.0
5.0
5.0
5.0
-20- + 75
-20- + 75
-20- + 75
-20- + 75
RAM (byte)
-
512
512
512
External Memory
Expansion (byte)
1M
1M
1M
1M
CP-84
CP-90S, FP-80B,
CP-84
DP-90S, FP-80G,
CP-84
DP-90S, FP-BOB,
CP-84, CG-84
Type No.
Clock Frequency (MHz)
Supply Voltage (V)
Operating Temperature' (0G)
Package
Features
• Software
compatibility with
HD64180R/Z
• 2-Channel Senal
Interface
• Software
compatibility with
HD64180R/Z
• No internal ROM
(Romless)
• Software compatibility
with HD64180R/Z
• 16K byte Mask ROM
• Software compatibility
with HD64180R/Z
• 16K byte PROM
·Wide Temperature Range (-40-+8SoC) version is available.
CP/M@isthe registered trade mark of Digitsl Research Inc,
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
xi
Quick Reference Guide
• NMOS 16-BIT MICROPROCESSOR
HDS8000Y8
HD68000Yl0
HD68000Y12
HDS8000-8
HDS8000-10
HD68000-12
Type No.
Clock Frequency (MHz)
HDS8000P8
S.O(HDS8000Y-8)
S.0(HDS8000·S)
10.0(HDS8000-10) 10.0(HDS8000Y-l0
12.5(HDS8000·12) 12.5(HDS8000Y-12
S.0(HDS80001!8) S.0(HDS8000PSS)
S.0(HDS8000C~)
0-+70
Operating Temperature tC)
0.9 (f = SMHz)
1.5 (f = SMHz, SMHz, 10MHz),
1.75 (f = 12.5 MHz)
PGA-SS
DC-64
Package
HDS8000CP8
5.0
Supply Voltage (V)
Power Dissipation (W)
HD68000PSB
CP-SS
DP-64S
DP-S4
High performance MPU featuring 32-bit data processing function
Feature
MCS8000LS
MCS8000LS
MCS8000LlO
MCS8000LI2
Compatibility
MCSSOOOFNS
MCS8000FNS
MCS8000PS
MCS8000PS
MCS8000RS
MCS8000RS
MCS8000Rl0
MCS8000RI2
• CMOS 16-BIT MICROPROCESSOR
Type No.
HDS8HCOOO-8
HDSSHCOOO-l0
HDSSHCOOO-12
HDSSHCOOOY-8
HDSSHCOOO't(.10
HDSSHCOOOY42
HD68HCOOO~
HDSSHCOOOP10
HDSSHCOOOP-12
HDSSHCOOOPS8
HD68HCOOOPS-l0
HDSSHCOOOPSl2
HDSSHCOOOCP-S
HDSSHCOOOCP-l0
HDS8HCOOOCItl2
Clock
S.O(HDSSHCOOO-S ) S.O(HDSSHCOOO¥8 ) S.O(HDSSHCOOOPS ) S.O(HDSSHCOOOP98 ) S.O(HDSSHCOOOCPS )
Frequency 10.0(HDSSHCOOO-l0) 10.0(HDSSHCOOOY10) 10.0(HDSSHCOOOP-10) 10.0(HDSSHCOOOPS'l0) 10.0(HDSSHCOOOCItl0)
(MHz) 12.5(HDSSHCOOO-12) 12.5(HDSSHCOOOYI2) 12.5(HDSSHCOOO~2) 12.5(HDSSHCOOOPS12) 12.5(HDSSHCOOO~ 2)
Supply
Voltage
(V)
5.0
Operating
Temperature (oC)
0-+70
Current
Dissipation (mA)
Package
25 (f = S MHz)
30 (f= 10 MHz)
35 (f = 12.5 MHz)
DC-S4
Feature
Compati·
bility
PGA-SS
DP-S4
DP-64S
CP-SS
High performance MPU featuring 32-bit data processing function
MCSSHCOOOLS
MCSSHCOOOLlO
MCSSHCOOOL 12
MCSSHCOOORS
MCSSHCOOOR10
MCSSHCOOOR12
MCSSHCOOOGS
MCSSHCOOOG10
MCSSHCOOOG 12
MCSSHCOOOFNS
MCSSHCOOOFN10
MCSSHCOOOFN 12
~HITACHI
xii
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
INTRODUCTION OF PACKAGES
Hitachi microcomputer devices include various types of
package which meet a lot of requirements such as ever smaller,
thinner and more versatile electric appliances. When selecting a
package suitable for the customers' use, please refer to the
following for Hitachi microcomputer packages.
multi· function types, applicable to each kind of mounting
method. Also, plastic and ceramic materials are offered ac·
cording to use.
Fig. I shows the package classification according to the
mounting types on the Printed Circuit Board (PCB) and the
materials.
1. Package Classification
There are pin insertion types, surface mounting types and
Standard Outline
Pin Insertion Type
PlastiC DIP
CaramtC DIP
Shrink Outline
Shrink Type PI ..tl~ DIP
Shrink Type Ceramic DIP
Package ClaSSification
Flat Package
Su rface Mounting Type
ChIP Carrier
EPROM on the Package
Multl·functlon Type
Type
DIP; DUAL IN LINE PACKAGE
S·DIP;SHRINK DUAL IN LINE PACKAGE
PGA PIN GRID ARRAY
FLAT·DIP; FLAT DUAL IN LINE PACKAGE
FLAT·QUIP. FLAT QUAD IN LINE PACKAGE
CC CHIP CARRIER
SOP;SMALL OUTLINE PACKAGE
FPP; FLAT PLASTIC PACKAGE
PLCC; PLASTIC LEADED CHIP CARRIER
LCC ; LEADLESS CHIP CARRIER
Fig. 1 Package Classification according to the Mounting Type on the Printed Circuit Board and the Materials.
2. Type No. and Package Code Indication
Type No. of Hitachi microprocessor is followed by package
material and outline specifications, as shown below. The package
type used for each device is identified by code as follows, illus-
trated in the data sheet of each device.
When ordering, please write the package code beside the type
number.
Type No. Indication
HDxxxx-P
(Note) The HD68000 with shrink type plastic DIP (DP-64S) has a different type No. from other devices.
TypeNo.
HD68000PS8
PackaA! Clanificatlon
No IndICation : Ceramic DIP
P
; PI ..tlc DIP
F
; FPP
CP
; PLCC
CG
; LCC
Y
; PGA U6·bit microcomputer device)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
Introduction of Packages
Package Code I ndication
I
DP-64S
2lUti!!J.
o ;DIP
'- M-.tL.er-i.-'s- -'I-N-um-be~r-Of-P-in"j
C;CC
F ; FLAT
1,oo. . . ., . j
P ; Plastic
G
S; S-DIP
; Glass Sealed
ceramic
C ;Ceramic
(Note)
PGA packages of 16-bit microcomputer devices have a different indication.
Package Code Indication;
PGA-6 8
Date Code Indication
Assembly lot date code_
OA3
;(ur
'tl!!!s.
0;1990
~
9;1999
1; 1st week
~
H;Aug.
5' 5th week
J;TPt.
M' Dec .
•
2
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300
Introduction of Packages
Table I according to the mounting method on the PCB.
3. PieD. Dimension.. Outline
Hitachi microprocessor employs the packages shown in
Table 1 Package List
Method of Mounting
Package Classification
Package Matenal
Package Code
Plastic
DP-40
DP-64
Ceramic
DC-64
S-DIP
Plastic
Dp·64S
Dp·90S
PGA
Glass Sealed Ceramic
PGA-68
FLAT-QUIP (FPP)
Plastic
FP·S4
FP-64
FP-80
FP80B
PLCC
Plastic
CP·44
CP-S2
CP·68
CP-84
Glass Sealed Ceramic
CG-40
CG-84
Standard Outline (DIP)
Pin Insertion Type
Shnnk Outline
Flat Package
Surface Mounting Type
Chip-Carrier
LCC
PluticDIP
•
Unit: mm(inch)
DP-40
528(2079)
54.0ml'. (2 126m...)
40
~~
21
~
.
;
~
20
(0047)
~a~!~
~
a~
2.54±02S
(OiOQ±OOIO)
048±01
(0019±0004)
5E
!
N
e
D'-IS'
D.t._
(D.DIDt'/;
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
3
Introduction of Packages
Unit: mm(inch)
•
DP-64
82.04 (3.Z30)
83.ZZmax.(J,Z76max.)
64
33
I
•
4
ZZ.86
HITACHI
Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589·8300
Introduction of Packages
I Ceramic DIP
Unit: mm(inch)
8 I 28
(3200)
eDC-64
33
64
~
i
o
0
IF"""'"
025~
(0010!8118l)
Shrink Type PI_tic DIP
Unit: mm(inch)
eDP-648
576(2268)
58.6max.(2.301mal(~)rot,
64
,"nnn~
0
~
(0039)
.wwwwwwwlz
_
5
•
_
~
"
19.05
(0.750)
~~i!lil~
'r----~~1
.nQ
I;
1.778±0.25
~±0010)
0.48±0 10 II
(0019±00r-
55 -
~~
0'-15'
O.2~!\"!il)
lOOIO!' '
S
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
5
Introduction of Packages
• DP-90S
r: : : : : : : : : ~ ~:~:~ ~ : : : : : : : : :I~I1~l!
II 1.00.03
( 9)
1
45
H
~
c
·E
~
~ ~
~4~t~l;-aA
22.86 (0.900) >
===== ~ ~ ~O""'~ (O.01~S81
_.!:.=:il-;;E
~
0.019_0.004)
E·E
00."
II
l
025. 0. 11 II
!:!'_~'!=I!.ll~*
.e
I
Pin Grid Array
Unit: mm(inch)
• PGA·68
2UUO.45
(0.900 ± 0.0187)
2642
(1.040)
.;s
0
0
.HITACHI
6
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
Introduction of Packages
IFlat Package
Unit: mm(inch)
• FP-54
015±005
(0006 ± 0 002)
• FP-64
• FP-80
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
7
Introduction of Packages
• FP·80A
17 2±0 3(0 677±0 012)
14.0(0.551)
41
[60
U
C>
-H
N
r-
0.dQ+O]l5
(0 .012±0.002)
c::
~
I
~"
C>
'"
-H
::::
'"
'"
M
'"
~
Jj
_=I-~IHIIIIIDIIIIIIIIIIIIIIIIIIIIIIIIIII 40
Ij
2.90(0.114)max
II
0.1 (0.004)
(STAND OFF)
'"
C>
II
20
1<$1 0.13(0.OOS)~
0.15±0.OS
(0.006 ± 0.002)
• FP·80B
\D
C;
d~
+1 ~
C)
~
'"
~
C)
~
de
'of
•
o
•
'of
~
+1
:
~HITACHI
8
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
Introduction of Packages
IPlastic Leaded Chip Carrier
Unit: mm(inch)
• CP-44
39
u;
0
0
0
28
40
+1
0
en
'"0
N
44
1
0
0
+1
PI
11'1
...:
6
'"o
II'I~
7
0.74(0.029)
-0
d
+1
+10
11'10
11'1-
'0
N~
15.50tO.50
0.610tO.020)
'-0"0"."10=0".0"'0-":4
• CP-52
20.07tO.12(0.790tO.005)
019.12 (00.753)
46
34
~ 47
33
0
0
+1
0
en
..., 52
~ 1
0
N
0
+1
.....
0
0
N
7
,
8
.......
_-- .__ ........
21
'"o
II'I~
_0
0.75(0.030)
0+1
+1 0
11'10
11'1"";
'0
N~
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
9
Introduction of Packages
Unit: mm(inch)
• CP-68
-.
-.
2515+012(099+0005)
024.20(00.953)
60
44
61
43
'"
o
~
o
+
en1 68
en
1
e
0
~
o
~
+1
~
~
'"
'"
","1
N
9
o
27
-0
26
10
N
0+1
GO
+10
•
~d
N~
og
.0
"'0
.. -
0+1
+1",
0
0.74(0.029)
....
~e
23.12±0.50
(0.910±0.020
00.10 0.004
• CP-84
-.
-.
3023+012(1 190+0005)
029.28(01.153)
74
54
53
75
II>
o
o
C>
1
+
o
en
• 84
N
0
1
~
o
+1
'"o
'"
N
'"o
~
",,,!
_ 0
c:i +1
+10
11
",0
12
32
"!:;i
N~
0.74(0.029)
10
• HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
Introduction of Packages
ILeadless Chip Carrier
Unit: mm(inch)
• CG·40
D12.19±O.3
(O.480±O.012)
Ib====d
Ii nnnnnnnnnn h
,1
~
NS
~
• CG·84
029.21 ±O.3S (01.1 SO±O.OlS)
0
.
)(
)(
0
.. E
Eo>
I"l'"
o~
..is.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
11
Introduction of Packages
4. Mounting Method on Board
Lead pins of the package have surface treatment, such as
solder coating or solder plating, to make them easy to mount
on the PCB. The lead pins are connected to the package by
eutectic solder. The following explains the common connecting
method ofleads and precautions.
4.1 Mounting Method of Pin Insertion Type Package
Insert lead. pins of the package into through·holes (usually
about 4>0.8mm) on the PCB. Soak the lead part of the package
in a wave solder tub.
Lead pins of the package are held by the through·holes.
Therefore, it is easy to handle the package through the process
up to soldering, and easy to automate the soldering process.
When soldering the lead part of the package in the wave solder
tub , be careful not to get the solder on the package, because
the wave solder will damage it.
4.2 Mounting Method of Surface Mounting Type Package
Apply the specified quantity of solder paste to the pattern
on any printed board by the screen printing method, and put a
package on it. The package is now temporarily fixed to the
printed board by the surface tension of the paste. The solder
paste melts when heated in a reflowing furnace, and the leads
of the package and the pattern of the printed board are fIXed
together by the surface tension of the melted solder and the
self alignment.
The size of the pattern where the leads are a~tached, partly
depending on paste material or furnace adjustment, should be
1.1 to 1.3 times the leads' width.
The temperature of the reflowing furnace depends on pack·
age material and also package types. Pig. 2 lists the adjustment
of the reflowing furnace for FPP. Pre-heat the furnace to 150°C.
The s~rface temperature of the resin should be kept at 235°C
max. for 10 minutes or less.
Ensure good heater or temperature controls because the
material of a plastic package is black epoxy-resin which damages
easily. When an infrared heater is used, if the temperature is
higher than the glass transition point of epoxy-resin (about
150°C), for a long time, the package may be damaged and the
reliability lowered. Equalize the temperature inside and outside
the packages by l~ssening the heat of the upper surface of the
packages.
Leads of PPP may be easily bent under shipment or during
handling and cannot be soldered onto the printed board. If
they are, heat the bent leads again with a soldering iron to reshape them.
Use a rosin flux when soldering. Don't use a chloric flux
because the chlorine in the flux tends to remain on the leads
and lower the reliability of the product.
Even if you use a rosin flux, remaining flux can cause the
leads to deteriorate. Wash away flux from packages with
alcohol, chlorothene or freon. But don't leave these solvents
on the packages for a long time because the marking may
disappear.
5. Marking
Hitachi trademark, product type No., etc. are printed on
packages. Case I and Case II give examples of marks and Nos.
Case I applies to products which have only a standard type No.
Case II applies to products which have an old type No. and a
standard type No.
(1) The temperature of the leads should be kept at 260°C
for 10 minutes or less.
(2) The temperature of the resin should be kept at 235°C
for 10 minutes or less.
(3) Below is shown the temperature profile when soldering a
package by the reflowing method.
t
!
~
!
Tlme---'
Figure 2 Reflowing Furnace Adjustment for FPP
~HITACHI
12
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
Introduction of Packages
Case I; Includes a standard type No.
'. 'mDB
(C)B DB809B
(d)
(]~ B~
ISJ
Case \I; Includes an old type No. and a standard type No.
(a)
(b)
'. mOG
(e)
B D ~ B800 DB
(d)
(c)
(]~B~ISJ
BDB800B
Mean ing of Each Mark
(al
(bl
(el
(dl
(el
Hitachi Trademark
Lot Code
Standard Type No.
Japan Mark
Old Type No.
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
13
SOCKETS FOR EVALUATING SURFACE AND
THROUGH-HOLE MOUNT PACKAGES
1. SOCKET LIST
Thble I lists the sockets available on the market for evaluating the characterislics of surface and through-hole package devices. For details, please
inquire directly to the socket manufacturer.
Table 1 IC Socket list
Package Type
Package Code
DIP (Plastic)
DIP (Plastic, Shrink)
Dip (Ceramic)
PGA (Glass Sealed Ceramic)
Manufacturer Name
ICS1-0S44-S17-2
Yamaichi Denkl
FP-64
ICS1-0644-472-2
FPQ-64-1.0-08A
Yamaichi Denki
Enplas
FP-64A
ICS1-0644-692-3
FPQ-64-0.8-01A
Yamaichi Denki
Enplas
FP-80
ICS1-0804-394-2
FPQ-80-0.8-11 A
Yamaichl Denki
Enplas
FP-80B
ICS1-0804-819-1
FPQ-80-0.8-11 A
FPQ-80-0.8-13A
Yamaichi Denkl Kogyo
Enplas
Enplas
QFP
PLCC
Socket Code
FP-S4
CP-44
ICS1-0444-400
Yamalchi Denkl Kogyo K.K.
CP-S2
ICS1-0S24-411
Yamaichi Denki Kogyo K.K.
CP-68
ICS1-0684-390
PLCC-68-1.27-02
Yamaichl Denkl Kogyo K.K.
Enplas
CP-84
PC 1-0840S0-003
ICS1-0844-401-1
Nepenthe
Yamaichi Denki Kogyo
DP-40
IC37NR-4006-G4
Yamaichl Denkl
DP-64
IC8620-6409-G4
IC86-6409
IC7620-6407S-G4
IC38-6407S-G4
Yamaichl Denkl Kogyo
DP-64S
Yamaichi Denki
Yamalchi Denki
DP-90S
IC121-9009-G4
Yamalchi Denki Kogyo
DC-64
IC8620-6409-G4
Yamaichi Denki Kogyo
AUGAT
PC-68
PPS68-AG2D
CG-40
240-S084-00-1102
TEXTOOL
CG-84
PC 1-0840S0-003
SHIM-0844-401-047
ICS1-0844-401-1
Nepenthe
Nepenthe
Yamalchi Denkl Kogyo
LCC (Glass Sealed Ceramic)
~HITACHI
14
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
DEVICE PACKING
1. SHIPPING CONTAINERS AND HANDLING
1.1 SHIPPING CONTAINER FORMS
Figures I and 2 illustrate the shipping container forms for
ordinary Ie devices. Within the outer corrugated cardboard carton
there are one or more inner cartons. These inner carton contain
magazines, trays, or tape reels, which the Ie devices are shipped in.
Plastic surface mount packages containing large chips can crack
if they absorb moisture and are mounted by retlow soldering. These
surface mount devices are packed with a moisture-proof material to
prevent the packages from absorbing moisture during shipping and
storage.
---"""";;;.,:;0..,
1
OUTER
j_+-"":::'" Carton tape (blue)
Packing
List
BOX
Label
K--"
~'
2
INNER
~_'
_ _ _ _ _ _ _\_\""_ _ _
BOX
\Magazine
Label
Cardboard
Carton
Tr............
3
R
MAGAZINE,
TRAY, &
MaS-PACK
Product
Tray
4
IC (LSI)
Figure 1.
Shipping Containers
_HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
15
Device Packing
1.2 NOTES ON HANDLING
(I) Handles the outer cardboard carton with care. Sudden drops or
shocks can cause damage to the enclosed products. Be sure not
to overstack the cartons.
(2) Prevent water leakage. Do not leave shipping contamers outside
or store them in high-temperature, high-humidity areas.
(3) Handle the inner cartons with care. Dropping a box may dislodge a magazine stopper, allowing devices to slide out in which
care their leads may be deformed. Dropping may also cause
damage to cerdmic packages and cause leaks to air-tight seals.
The surface of transparent vinyl-chlonde magazines are treated
with an antistatic coating to prevent static charge. Be aware of
the following notes concerning this coatmg:
• Water leakage WIll cause the anti-static material to peel off
and lose it effectiveness.
• The anti-static material may become sticky in hightemperature, high-humidity environments.
• The anti-static material may warp over time; avoid storage
beyond six months. Do not reuse the material.
• Note that the surface resistance of transparent magazines is
less than I x 10 10 Ohms, and the surface resistance of black
magazines is less than I x 1!J6 Ohms.
• Store vinyl-chloride tmys between -25°C and +40°C. Both
the shape and color may change in an environment above
55°C.
1.3 PARTIAL SHIPMENTS PACKING
~PinkFoam*
/
I
I
(Antistatic)
Inner Box or
MOS Pack
Packing List*
~HITACHI
Label (Bar Coded)*
DIMENSION IN MM
DIMENSION IN INCHES
WxHxL
WxHxL
250 x 250 x 500
10 x 10 x 20
250 x 225 x 550
10 x 9 x 22
175 x 150 x 550
7 x 6 x 22
* Materials or placement may vary.
Figure 2.
Partial Shipments
@HITACHI
16
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
Device Packing
2. MOISTURE-PROOF (DRY PACK) PACKING AND HANDLING
If a surface mount package is mounted with solder reflow after it
has absorbed moisture, then package cracks may occur. In order to
prevent moisture absorption during shipping or storage, the pack-
ages are encased m vacuum packed moisture-proof (dry pack) packing material as shown in figure 3 The following sections describe
how to handle this material.
DIP or PLCC
LSI
MagaZine
Stopper
Magazine
Band
"-..'-"7
~
D
Product
!
'-~
,/;'
<4 _ _ . /
=-_.--.t::. __ /
Tray
DeSiccant
Vapor-proof bag
(containing aluminum foil)
Carton
!
Water vapor-proof packing~~A~========7~~
Label
V
Inner case
Figure 3.
Vacuum Packed MOisture-Proof (Dry Pack) Packing
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
17
Device Packing
-----------~------
2.1 SlORAGE METHOD:
Stonng packed res under lOappropnate condItIOns can cause deterioratIOn m soldcrablhty and performance. HitachI recommends
that products III vacuum packed mOIsture-proof (dry pack) packmg
matenal be stored In tray boxed If thIs IS not possIble, packages
should be stored under the followmg condItIOns:
• Temperature- 5 to 30°C
• Hurmdlty less than 60 % RH
p..,rts stored In unopened vacuum packed mOIsture-proof (dry
pack) condllloll may r(mam solderable for three (3) to five (5) years.
2.2 HANDLING AFTER OPENING:
In order to prevent n.:-absorplIt.m alter openmg the mOIstureproof material. store under the conditions h~ted above and retlow
mount the poc kages wllhm onc week If thc packages mllst be placed
Into ~toragc ag~lin after openmg. then seal 10 a new (non-mOi~ture
cont:1mmatcd) SIlica gel (confIrm \'l/Jth blue-colored mdicator) and
~tore under the cnndltlons llstcd above Try to reseal In vacuum
pack('d 1l100'-.illff'-prnnf (Jry pack) packing matcnal
2.3 BAKING BEFORE SOLDER REFLOW:
Baking IS necessary If the mdicator of the sihca gel does not
appear blue-colored throughout; more than one week has elapsed
smce openrng (even stored under the conditlOns listed above); or the
affixed label mdlcates bakmg IS requIred.
2.4 RECOMMENDED BAKING CONDITIONS:
Bakmg should be performed under the following condItions:
• Temperature. l25"C
• DuratIon: 16 to 24 hours
The magazmes, trays, and tape reels normally used for shIpment
are not heat-proof. therefore contamers cannot be baked as shIpped.
DeVIces mu:;;t first be transferred into a heat-proof contamer Heatproof magazInes and trays are currently under development.
Tray labelled as heat-proof can be used, however do not bake with
the mOl sture-proof bag Sake on a level plane to prevent sliding.
3. PACKING SPECIFICATIONS FOR VARIOUS PACKAGES
3.1 PACKING SPECIFICATIONS for DIP Packages
---------r--------Package Code
(correspondIng
diagram)
DP-40
illustration
In
fIgure 4(b}
(A or B)
Quantity
'--------- --ICs/Magazrne IC/MOS Pack Magazlnes/lnner Box
9
-
20
-
Inner Box' DImenSions
W x H x LIn mm. and (inches)
112.5 x 59.4 x 500
(4'/:, x 2% x 20)
DP-64
-------
(DP·64S)
(C)
8
-
(D)
-
10
12
75 x 59.4 x 500
(3 x 2% x 20)
Dp·90S
DC-64
N/A
80 x 16 x 240
(3% x % x 9%)
FIgure 4(a). PackIng Specifications for DIP Packages '(see FIg 1, thIS section)
~HITACHI
18
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
Device Packing
lI.rdpoly""renemIIUln"
(bl.d)
Nnn millar.llon pla_urlz....!
'lojt,hluro<'lhyl",,' 8Io l'l"'r
Igray)
Nnoll'1'llr.l,onplnl,ruN
InftcMorOfthylentstllPper
(II rl "
Magazine board thickness: 0.8 ± 0.31111
Length: 500 ± 2...
Magazine board thlcknes:.: 1 O±O.31111
Length: 495 1.. 311\.
(500 t3ra.. )
17H.
~
~W
Dimensional tolerance. ±O.SlIIm
Illustration (A)
Illustration (6)
Clear
Nflh mllC"r~llon pIA~l1nl~d
fillftrhlorlM'lh)ll'nt&tnPLIt'r
(<55: I.O±O,alllll
Length: 495.± 311111
If"
Black Foam
(carbon treated)
Cardboard
(Ffaday)
~
16'~.'iiiiiiiiiiiiiiiiiiii_, : 4.0:mm
Pink' Foam
(anti-static)
Illustration (C)
Figure 4(b),
Cardtfoard
(Faraday)
1,01mm
Illustration (0)
Packing Materials for DIP Packages
•
HITACHI
Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
19
Device Packing
3.2 QFP AND LCC PACKING SPECIFICATION
Vmyl-Chlonde
(dntl-~Iatlt charge tr~ated)
lIIustralion (A)t
IllustratIon (B)t
illustration (c)t
IllustratIon (0)*
illustration (E);
twlthout holes
:twrth holes
.HITACHI
20
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 .' (415) 589-8300
Device Packing
Quantity
Package Code
Illustration in
Figure 5
IClTray
Trays/Inner Box
FP-54
(C or D)
50
10
FP-64
(C or D)
50
10
FP-64A
(B)
50
10
FP-80
(C or D)
50
10
FP-80B
D
50
10
CG-40
(A)
50
10
Inner Box' Dimensions
W x H x L in mm. (in.)
147 x 70 x 325
(5% x 2% x 13)
147 x 70 x 325
(5% x 2% x 13)
147 x 70 x 325
(5% x 2% x 13)
147 x 70 x 325
(5% x 2% x 13)
147 x 70 x 325
(5% x 2% x 13)
147 x 70 x 325
(5% x 2% x 13)
Figure 5. QFP and LCC Packing Specifications and Materials '(see Fig. 1, this secllOn)
3.3 PACKAGE PACK SPECIFICATIONS
PLCC PACKING SPECIFICATIONS
c~,,,
.......,bI. PC V<>1,,»
~ 0:0'
c~."".. ",,
Magazine board
thickness: 1.1 ± 0.3 mm
length: 495 ± 3 mm
Magazine board
thickness: 0.8 ± 0.3 mm
length: 495 ± 3 mm
20.1
13.~
~
13.~
h
h
*~I~1
h
r
ili~l
.r
u
IR.S
Magazine board
thickness: 0.8 ± 0.3 mm
length: 495 ± 3 mm
I"':
Dimensional tolerance: ± 0.5 mm
Illustration (B)
Quantity
ICs Magazine
Magazines/Inner Box
CP-44
(A)
26
30
23
CP-68
(C)
18
CP-84
(D)
15
lrir-:~
Dimensional tolerance: ± 0.5 mm
Illustration (C)
Illustration in
Figure 6
(B)
1I~1
26.25
Package Code
CP-52
r
'(
0":
21.1
Dimensional tolerance: ± 0.5 mm
Illustration (A)
2i.tI.!i
13.'
18
28
Inner Box' Dimensions
W x H x Lin mm. (in.)
113 x 56.3 x 493.8
(4% x 2% x 19%)
118.8 x 65.6 x 500
(4% x 2% x 20)
118.8 x 65.6 x 493.8
(4% x 2% x 20)
Figure 6. PLCC Packing Specifications and Materials '(see Fig. 1, this section)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300
21
Device Packing
4,0 PACKING LABELS
44444444444444444444
CUST PART
C
!ill!llililllll!1 I!IIII!I!I 1[111 11111 I!III 111!1 11111 II III 111!llillllll!II!!III!II!I!IIIIII!II!IIIIII!1 III!II!II IIII
~ALPART
IFRCW'l :
44444444444444444444
!i1lillililIi ;il'IIJlill!llll:li'I;li'II:I!"lil'llilill;lill:IIII:1Ii
; I Iii 'I ! I i ,I i r I !,' i' ; II lilli'ltlllll:":II'IIII'11,'I:lli
iii' ;iii ~ I ; i i iiilill'I!llllil,I'I!11
;1 i! i ,I i IIill'l
II!:
I, ,t
Ii!
Ii: i : 1'1/ II/
"""1.,,
1[, I
1,1"
QUANTITY
ill~
'I': ill, I'lill'!\:',I Ii'IIii'I 1:1',:!,
/ ~;I ' !I Ill: ,! II : i I :
if ill, I! :!I ' I! III 1.111: !! '
Q ;",I:
!11!11 1Ii' 1:1:1 1111111111,I ; I
;!
'I
'I..
'i-.
~~Cf~RGE LO,
,III:
i'l I, :, ; "11111/
" .' I' I'1.11
III
I
I, <, 'I
"
I , . · J II III
!,.
:~~TE CODE
'!'jll:!i.lillllilillililliltll:'i'I'l'i'lilillil:.'llilillilill:lrli'lillilil'llll!I'i'lij'ililli',iI'l:lill:liIIII!
::;111: :
!I:.!lill i i, '11 iii! ill! il i it: i 1 llh!! ill: 11 i
CUST
K
p,o,
44444444444444444444444444444
4444-1444444-14444444-144444444-1
":4444-14-1444444-14444444-1-1-1444-1
! 444-144444444444444444444-14444
44-14444-1444-1444-144444-14444444
444444444444444
iJ
~~~~~~~~~~~~~~:~~~:~~~~:~~::~
ij 44444444444444444444444444444
!:TO=
;,i
4444444 ER
iih:!n [:
I$HITACHI
444444
!!I i,II11,1111II :II,
!I"II!I 11:111111 I!I!IIIIIII lilll 1'111111111111i
I! "I ," I, ! II 'I ;
L,
!.I
I I
44444444444444444444
lsox mum
il l!I I~li~!li 1:~li~[il l!~liJlil l!~I I I ~l lil li~1 i I I !~ 14444444444
Illmlil:11
. , . ,I , I "I,
,. ,I .. "I '" "
". I,
,,' I, ,
I ,.,' , II "I . " ,,' ,. "I II ,
Figure 7.
Figures I and 2 on pages 13 and 14 show the outer box label
placement on the end and left adjacent side of the box, Placement is
within one-half inch ('12") of the box's corner. Figures I and 2 show
the inner box label placement is on the end of the inner box. A
packing list is alixed to the left adjacent side of the outer box's end
and next to the bar code label.
Outer Box Label
PIN: _ _ _ _ _ __
QTY: _ _ _ _ _ __
Date Code: - _ _ _ __
Figure 8.
Inner Box Label
@>HITACHI
22
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
RELIABILITY AND QUALITY
1. VIEWS ON QUALITY AND RELIABILITY
Basic views on quality in Hitachi are to meet individual
user's purchase purpose and quality required, and to be at the
satisfied quality level considering general marketability. Quality
required by users is specifically clear if the contract specifica·
tion is provided. If not, quality required is not always defmite.
In both cases, efforts are made to assure the reliability so that
semiconductor devices delivered can perform their ability in
actual operating circumstances. To realize such qUality in
manufacturing process, the key points should be to establish
quality control system in the process and to enhance morale
for quality.
In addition, quality required by users on semiconductor
devices is going toward higher level as performance of elec·
tronic system in the market is going toward higher one and is
expanding size and application fields. To cover the situation,
actual bases Hitachi is performing is as follows;
(1) Build the reliability in design at the stage of new product
development.
(2) Build the quality at the sources of manufacturing process.
(3) Execute the harder inspection and reliability confmnation
of fmal products.
(4) Make quality level higher with field data feed back.
(5) Cooperate with research laboratories for higher quality
and reliability.
With the views and methods mentioned above, utmost efforts
are made for users' requirements.
2. RELIABILITY DESIGN OF SEMICONDUCTOR
DEVICES
2.1 Reliability Targets
Reliability target is the important factor in manufacture
and sales as well as performance and price. It is not practical to
rate reliability target with failure rate at the certain common
test condition. The reliability target is determined correspond·
ing to character of equipments taking design, manufacture,
irmer process quality control, screening and test method, etc.
into consideration, and considering operating circumstances
of equipments the semiconductor device' used in, reliability
target of system, derating applied in design, operating condition,
maintenance, etc.
2.2 Reliability DeSign
To achieve the reliability required based on reliability targets,
timely sude and execution of design standardization, device
design (including process design, structure design), design
review, reliability test are essential.
(1) Design Standardization
Establishment of design rule, and standardization of parts,
material and process are necessary. As for design rule, critical
items on quality a1id reliability are always studied at circuit
design, device design, layout design, etc. Therefore, as long as
standardized process, material, etc. are used, reliability risk is
extremely small even in new development devices, only except
for in the case special requirements in function needed.
(2) Device Design
It is important for device design to consider total balance
of process design, structure design, circuit and layout design.
Especially in the case new process and new material are em·
ployed, technical study is deeply executed prior to device
ASSURANCE
development.
(3) Reliability Evaluation by Test Site
Test site is sometimes called Test Pattern. It is useful method
for design and process reliability evaluation of Ie and LSI which
have complicated functions.
I. Purposes of Test Site are as follows;
• Making clear about fundamental failure mode
• Analysis of relation between failure mode and manufac·
turing process condition
• Search for failure mechanism analysis
• Establishment of QC point in manufacturing
2. Effectiveness of evaluation by Test Site are as follows;
• Common fundamental failure mode and failure mecha·
nism in devices can be evaluated.
• Factors dominating failure mode can be picked up, and
comparison can be made with process having been experi·
enced in field.
• Able to analyze relation between failure causes and manufacturing factors.
• Easy to run tests.
etc.
2.3 Design Review
Design review is organized method to confmn that design
satisfies the performance required including users' and design
work follows the specified ways, and whether or not technical
improved items accumulated in test data of individual major
fields and field data are effectively built in. In addition, from
the standpoint of enhancement of competitive power of products, the major purpose of design review is to ensure quality
and reliability of the products. In Hitachi, design review is
performed from the planning stage for new products and even
for design changed products. Items discussed and determined
at design review are as follows;
(1) Description of the products based on specified design
documents.
(2) From the standpoint of specialty of individual participants,
design documents are studied, and if unclear matter is
found, sub-program of calculation, experiments, investigation, etc. will be carried out.
(3) Determine 'contents of reliability and methods, etc. based
on design document and drawing.
(4) Check process ability of manufactUring line to achieve
design goal.
(5) Discussion about preparation for production.
(6) Planning and execution of sub-programs for design change
proposed by individual specialist, and for tests, experiments
and calculation to confmn the design change.
(7) Reference of past failure experiences with similar devices,
confmnatlon of method to prevent them, and planning
and execution of test program for confmnation of them.
These studies and decision~ are made using check lists
made individually depending on the objects.
3. QUALITY ASSURANCE SYSTEM OF SEMICONDUCTOR
DEVICES
3.1 Activity of Quality Assurance
General views of overall quality assurance in Hitachi are as
follows;
(1) Problems in individual process should be solved in the
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
23
Reliability and Quality Assurance
process. Therefore, at final product stage, the. potential
failure factors have been already removed.
(2) Feedback of information should be made to ensure satisfied
level of process ability.
(3) To assure reliability required as an result of the things
mentioned above is the purpose of quality assurance.
The followings are regarding device design, quality approval
at mass production, inner process quality control, product
inspection and reliability tests.
3.2 Quality Approval
To ensure quality and reliability required, quality approval
is carried out at trial production stage of device design and
mass production stage based on reliability design described at
section 2.
The views on quality approval are as follows;
(I) The third party performs approval objectively from the
standpoint of customers.
(2) Fully consider past failure experiences and information
from field.
(3) Approval is needed for design change and work change.
(4) Intensive approval is executed on parts material and pro·
cess.
(5) Study process ability and fluctuation factor, and set up
control points at mass production stage.
Considering the views mentioned above, quality approval
shown in Fig. I is performed.
3.3 Quality and Reliability Control at Mass Production
For quality assurance of products in mass production,
quality control is executed with organic division of functions
Step
I
,Target
SpeCification
in manufacturing department, quality assurance department,
which are major, and other departments related. The total
function flow is shown in Fig. 2. The main I'oiots are described
below.
3.3.1 Quality Control of Pam and Material
As the performance and the reliability of semiconductor
devices are getting higher, importance is increasing in quality
control of material and parts, which are crystal, lead frame,
fine wire for wire bonding, package, to build products, and
materials needed in manufacturing process, which are mask
pattern and chemicals. Besides quality approval on parts and
matenals stated in section 3.2, the incoming inspection is,
also, key in quality control of parts and materials. The in·
coming inspection is performed based on incoming inspection
specification following purchase specification and drawing,
and sampling inspection is executed based on MIL·STD·' 050
mainly.
The other activities of quality assurance are as follows:
(I) Outside Vendor Technical Information Meeting
(2) Approval on outside vendors, and guidance of outside
vendors
(3) PhYSical chemical analysis and test
The typical check points of parts and materials are shown in
Table I.
3.3.2 Inner Process Quality Control
Inner process quality control is performing very important
function in quality assurance of semiconductor devices. The
following is description about control of semi·fmal products,
final products, manufacturing facilities, measuring equipments,
Contents
Purpose
I DeSign Re'flew
I
I
t
~;riaIS. P.;rt.]
loesi 9n
Tnal
Production
App~oval
llCharacteristics Approval
1~lty Appr~v.1
(1)
=r:---:1-
l~lity APJ>roval
Mas!i
(21
~
Characteristics of Matenal and
Parts
Appearance
Dimension
Heat ReSistance
Mechanical
Electrical
Others
Confirmation of
Charactenstics and
Reliability of Matenals
and Parts
Electrical
Characteristics
Function
Voltage
Current
Temperature
Others
Appearance, DimenSion
Confirmation of Target
Spec. Mainly about
Electrical Charactenstlcs
Reliability Test
life Test
Thermal Stress
Moisture ReSIstance
Mechanical Stress
Others
Confirmation of Quality
and Reliability In DeSign
Reliability Test
Process Check same a~
QualIty Approval (11
J
Confirmation of Quality
and Reliability
Production
In
Mass
Figure 1 Flow Chart of Quality Approval
~HITACHI
24
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589·8300
Reliability and Quality Assurance
circumstances and sub-materials. The quality control in the
manufacturing process is shown in Fig. 3 corresponding to
the manufacturing process.
(1) Quality Control of Semi-fmal Products and Final Products
Potential failure factors of semiconductor devices should be
removed preventively in manufacturing process. To achieve it,
check points are set-up in each process, and products which
have potential failure factor are not transfer to the next process.
Especially, for high reliability semiconductor devices, manufacturing line is rigidly selected, and the quality control in the
manufactUring process is tightly executed - rigid check in
each process and each lot, 100% inspection in appropriate ways
to remove failure factor caused by manufacturing fluctuation,
and execution of screening needed, such as high temperature
aging and temperature cycling. Contents of inner process
quality control are as follows;
• Condition control on individual equipments and workers,
and sampling check of semifmal products.
• Proposal and carrying-out improvement of work
• Education of workers
• Maintenance and improvement of yield
• Picking-up of quality problems, and execution of counter-
Process
measures
• Transmission of information about quality
(2) Quality Control of Manufacturing Facilities and Measuring
Equipment
Equipments for manufacturing semiconductor devices have
been developing extraordinarily with necessary high performance devices and improvement of production, and are important
factors to determine quality and reliability. In Hitachi, automatization of manufacturing equipments are promoted to improve manufacturing fluctuation, and controls are made to
maintain proper operation of high performance equipments
and perform the proper function. As for maintenance inspection
for quality control, there are daily inspection which is performed daily based on specification related, and periodical inspection
which is performed periodically. At the inspection, inspection
points listed in the specification are checked one by one not to
make any omission. As for adjustment and maintenance of
measuring equipments, maintenance number, specification are
checked one by one to maintain and improve quality.
(3) Quality Control of Manufacturing Circumstances and Submaterials
Quality and reliability of semiconductor device is highly
Quality Control
Inspection on Matenal and
Parts for Semiconductor
Lot Sampling,
Confirmation of
Devices
Quality Level
ManufactUring Equipment,
Environment, Sub·material,
Worker Control
I nner Process
Quality Control
l(){)1)i1i. Inspection on
Appearance and Electrical
Characteristl~
Products
Method
Sampling Inspection on
Appearance and Electrical
Confirmation of
Quality Level
Lot Sampling,
Confirmation of
Quality Level
Testing,
Inspection
Lot Sampl ing
Characteristics
Confirmation of
Reliability Test
Quality Level, Lot
Samplmg
Feedback of
r ---------------,
: Quality Information
I
I
Claim
:
I
field Experience
:
General Quality
Information
I
L _________________ .J
Information
Figure 2 Flow Chart of Quality Control in Manufacturing Process
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
25
Reliability and Quality Assurance
--~----------------.------------------------------------------
affected by manufacturing process. Therefore, the controls of
manufacturing circumstances - temperature, humidity, dust and the control of sub materials - gas, pure water - used in
manufacturing process are intensively executed. Dust control
is described in more detail below.
Dust control is essential to realize higher integration and
higher reliability of devices. In Hitachi, maintenance and improvement of cleanness in manufacturing site are executed
with paying intensive attention on buildings, facilities, airconditioning systems, materials delivered-in, clothes, work, etc.,
and periodical inspection on floating dust in room, falling dusts
and dirtiness of floor.
Table 1 Quality Control Check Points of Material and Parts
(Example)
Material.
Parts
Wafer
Mask
3.3_3 Final Product Inspection and Reliability Assurance
(I) Final Product Inspection
Lot inspection is done by quality assurance department for
products which were judged as good products in 100% test,
which is fmal process in manufacturing department. Though
100% of good products is expected, sampling inspection is
executed to prevent mixture of failed products by mistake of
work, etc. The inspection is executed not only to confIrm that
the products meet users' requirement, but to consider potential
factors. Lot inspection is executed based on MIL-STD-IOSD.
(2) Reliability Assurance Tests
To assure reliability of semiconductor devices, periodical
reliability tests and reliability tests on individual manufacturing
lot required by user are performed.
Fine
Wire for
Wire
Bonding
Frame
Ceramic
Package
Plastic
Important
Control Items
Appearance
Dimension
Sheet Resistance
Defect Density
Crystal Axis
Appearance
Dimension
Resistoration
Gradation
Appearance
Dimension
Purity
Elongation Ratio
Appearance
Dimension
Processing
Accuracy
Plating
Mounting
Characteristics
Appearance
Dimension
Leak Resistance
Plating
Mounting
Characteristics
Electrical
Characteristics
Mechanical
Strength
Composition
Electrical
Characteristics
Thermal
Characteristics
Molding
Performance
Mounting
Characteristics
Point for Check
Damage and Contamination on Surface
Flatness
Resistance
Defect Numbers
Defect Numbers. Scratch
Dimension Level
Uniformity of Gradation
Contamination. Scratch.
Bend, Twist
Purity Level
Mechanical Strength
Contamination, Scratch
Dimension Level
Bondability. Solderability
Heat Resistance
Contamination, Scratch
Dimension Level
Airtightness
Bondability. Solderability
Heat Resistance
Mechanical Strength
Characteristics of
Plastic Material
Molding Performance
Mounting Characteristics
$HITACHI
26
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
Reliability and Quality Assurance
Control Point
Purpose of Control
Purchase of Material
Wafer
Wafer,
t:
Surface Oxidation
Characteristics, Appearance
ScratCh. Removal of Crystal
Oefect Wafer
Assurance of Resistance
Appearance, Thtckness of
Pinhole, Scratch
Oxidation
I nspection on Surface
Oxide Film
Oxidation
Photo
Re.ist
Photo Resilt
I nspaction on Photo Resist
Dimension, Appearance
() Pac Level Chock
Diffusion
Dimension Level
Check of Photo Rosist
Diffusion
O.ffusion Depth. Sheet
Diffusion Status
Resistance
Inspection on Diffusion
() Pac Lowl Chock
Gate Width
Control of Basic Parameters
Characteristics of Oxide Film
(VTH. otc.l Cleanness of surface.
Prior Check of VIH
Breakdown Voltage Check
Breakdown Voltage
.:, Evaporat.on
EV8pora~
tion
Thickness of Vapor Film.
Scratch, Contamination
Wafer
Thickneu. VTH Characteris·
Assurance of Standard
Thickness
I nspection on Evaporation
o Pac Lowl Check
Wafer Inspection
tic.
Inspection on Chip
Electrical Characteristics
Chip
Prevention of Crack,
Quality Assurance of Scribe
Electrical Characteristics
Chip Scribo
Appearance of Ch ip
Inspection on Chip
Appearance
() Pac Lot Judgement
Frame
Assembling
Assembling
Appearance after Chip
Bonding
Appearance aft.r Wire
Bonding
Pull Strength. Compression
Width. Shear Strength
Appearance after Assembling
() PQC Level Check
, Inspection after
Quality Check of Chip
Bonding
Quality Check of Wire
Bonding
Prevention of Open and
Short
As_ling
() PQC Lot Judgement
Sealing
Sealing
() Pac Lewl Check
Final Electricallnlpection
Marking
o Failure Analysis
Appearance after Sealing
Guarantee of Appearance
Outline, Dimension
and Dimension
Marking Strength
Analysis of Failures, Failure
Mode. Mechanism
Feedback of AnalYSis Inf ••rmation
Appearance I nspaction
Sampling Inspection on
Products
Receiving
Shipment
Figure 3 Example of Inner Process Quality Control
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
27
Reliability and Quality Assurance
Failure Analysis
Countermeasure
Execution of
Countermeasure
Report
Quality Assurance Dept.
Follow-up and Confirmation
of Countermaasure Execution
Report
L ________________________________
Sales Engineering Dept.
Reply
Customer
Figure 4 Process Flow Chart of Field Failure
~HITACHI
28
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
~
RELIABILITY TEST DATA OF MICROCOMPUTER
2. PACKAGE AND CHIP STRUCTURE
2.1 Package
1. INTRODUCTION
Microcomputer is required to provide higher reliability and
quality with increasing function, enlarging scale and widening
application. To meet this demand, Hitachi is improving the
quality by evaluating reliability, building up quality in process,
strengthening inspection and analyzing field data etc ..
This chapter describes reliability and quality assurance data
for Hitachi g·bit and 16·bit multi·chip microcomputer based on
test and failure analysis results. More detail data and new infor.
mation will be reported in another reliability data sheet.
(1)
Ceramic DIP
o
The reliability of plastic molded type has been greatly im·
proved, recently their applications have been expanded to auto·
mobiles measuring and control systems, and computer terminal
equipment operated under relatively severe conditions and
production output and application of plastic molded type will
continue to increase.
To meet such requirements, Hitachi has considerably im.
proved moisture resistance, operation stability, and chip and
plastic manufacturing process.
Plastic and ceramic package type structure are shown in
Figure I and Table I.
(2) Plastic DIP
Lid
(3) Plastic Flat Package
Bonding wire
Chip
Bonding wire
L..d
Figure 1 Package Structure
Table 1 Package Material and Properties
Item
Plastic DIP
Ceramic DIP
Plastic Flat Package
Package
Alumina
Epoxy
Epoxy
Solder plating Alloy 42
Lead
Tin plating Brazed Alloy 42
Solder dipping Alloy 42 or Cu
Seal
Au·Sn Alloy
N.A
N.A
Die bond
Au·Si
Au·Si or Ag paste
Au·Si or Ag paste
Wire bond
Ultrasonic
Thermo compression
Thermo compression
Wire
AI
Au
Au
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300
29
Reliability Test Data of Microcomputer
2.2 Chip Structure
Hitachi microcomputers are produced in NMOS E/D tech·
nology or low power CMOS technology. Si·gate process is used
1----
in both types because of high reliability and high density.
Chip structure and basic circuit are shown in Figure 2.
~---------~-~-----------------
~~-Gata N-channel E/O
I
Si-Gate CMOS
AI
I
AI
\
I
Dram
Source
FETI
Drain
Sial
Source
Drain
Source
FET2
FET2
N-channel
OMOS
P-channel
EMOS
N-channel
EMOS
EMOS
N-channel
Figure 2 Chip Structure and Basic Circuit
3. QUALITY QUALIFICATION AND EVALUATION
3.1 Reliability Test Methods
Reliability test methods shown in Table 2 are used to qualify and evaluate the new products and new process.
Table 2 Reliability Test Methods
Test Items
Test Condition
MIL-STO-883B Method No.
Operating Life Test
125°C,l000hr
1005,2
High Temp, Storage
Low Temp, Storage
Steady State Humidity
Steady State Humidity Biased
Tstg max, l000hr
Tstg min, l000hr
65°C 95%RH, l000hr
85°C 85%RH, l000hr
1008,1
Temperature Cycling
Temperature Cycling
Thermal Shock
Soldering Heat
Mechanical Shock
Vibration Fatigue
Variable Frequency
Constant Acceleration
Lead Integrity
_55°C - 150°C, 10 cycles
_20° C - 125°C: 200 cycles
O°C - 100°C, 100 cycles
260°C, 10 sec
1500G 0.5 msec, 3 times/X, Y, Z
60Hz 200, 32hrs/X, Y, Z
2Q-2oo0Hz 200,4 min/X, Y, Z
20000G,1 min/X, Y, Z
225gr, 90° 3 times
1010,4
1011,3
2002,2
2005,1
2007,1
2001,2
2004,3
~HITACHI
30
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
Reliability Test Data of Microcomputer
------------------------------------------~------
Table 9. There is little difference according to device series, as
the design and production process, etc. are stlLndardized.
3.2 Reliability Test Result
Reliability test result of 8·bit microprocessors is shown in
Table 3 to Table 7, that of 16·bit microprocessors in Table 8,
Table 3 Dynamic Life Test (S·bit microprocessor)
Device Type
HD6800
HD6802
HD6809
Total
Sample Size
Component Hours
Failures
248 pes
452
85
248000
153712
85000
0
1*
0
785
486712
1
-----
* leakage current
Estimated Field Failure Rate
=0.Q1%/l000h".tTa: 75'C
(Activation Energy = O. 7.V, Confidence Level 60%)
Table 4 High Temperature, High Humidity Test (8·bit microprocessor) (Moisture Resistance Test)
(1) 85°C 85%RH Bias Test
Device Type
Vee Bias
168 hrs
500 hrs
1000 hrs
HD6800P
HD6802P
HD6809P
5.5V
5.5V
5.5V
0/45
0/38
0122
0/45
0/38
0/22
0/45
0/38
0/22
0/105
0/105
0/105
168 hrs
500 hrs
1000 hrs
0/22
0122
0/38
0/45
0122
0122
0/38
0/45
0/22
0/22
Total
(2) High Temperature-High Humidity Storage Life Test
Device Type
HD6800P
HD6802P
HD6802P
HD6809P
Condition
65°C
80°C
65°C
65°C
95%RH
90%RH
95%RH
95%RH
0/38
0/45
(3) Pressure Cooker Test
(Condition' 2atm 121°C)
Device Type
HD6800P
HD6802P
40 hrs
60 hrs
100 hrs
0/42
0122
0/42
0/42
0122
0122
(4) MI L-STD·883B Moisture Resistance Test
(Condition; 65°C - -10°C, over 9Q%RH, Vee = 5.5V)
Device Type
HD6800P
HD6802P
10 cycles
20 cycles
0/25
0125
0125
0125
40 cycles
0125
0/25
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
31
Reliability Test Data of Microcomputer
Table S Temperature Cycling Test (S-bit microprocessor) (-SSoC - 2SoC - 150°C)
Device Type
HD6800P
HD6802P
HD6809P
10 cycles
100 cycles
200 cycles
0/453
0/502
0/202
0/44
0177
0/45
0/44
0/77
0/45
Table 6 High Temperature, Low Temperature Storage Life Test (S-bit microprocessor)
Device
Temperature
168 hrs
500 hrs
1000 hrs
150°C
-55°C
0/88
0/76
0/88
0/76
0/88
0/76
MPU total
Table 7 Mechanical and Environmental Test (8-bit microprocessor)
Flat Plastic Package
Plastic DIP
Test Item
Condition
Sample Size
Failure
Sample Size
Failure
O°C - 100°C
10 cycles
110
0
100
0
Soldering Heat
260°C, 10 sec.
180
0
20
0
Salt Water Spray
35°C, NaCI 5%
24 hrs
110
0
20
0
Solderability
230° C, 5 sec.
Rosin flux
159
0
34
0
Drop Test
75cm, maple board
3 times
110
0
20
0
Mechanical Shock
1500G, 0.5 ms
3 times/X, Y, Z
110
0
20
0
Thermal Shock
Vibration Fatigue
r--so32 Hz,
20G
hrs/X, Y, Z
110
0
20
0
Vibration Variable Freq.
100 - 2000 Hz
20G,4 times/X, Y, Z
110
0
20
0
Lead Integrity
225 g, 90·
Bonding 3 times
110
0
20
0
@HITACHI
32
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
Reliability Test Data of Microcomputer
Tabl, 8 Dynamic Lif. Test (16-bit microproclnorl
Device Type
HD68000
Condition
168 hrs
500 hrs
1000 hrs
Ta
Vcc
125°C
5.5V
0/62
0/62
0/62
150·C
5.5V
0/52
0/52
0/52
Estlmltld Filid Filiure Rita
= 0.013%/1000 h""t TI = 7SoC
(Activltlon Energy 0.71V, Confidenoo Llvel8O%1
Tabl. 9 Mechanical .nd Envlronm.ntal Tin (IB-bit microprocessor 1
Device Type
Test Item
Condition
Sample Size
Failure
High Temperature
Storage
Ta = 295°C, 1000 hrs
42
0
Low Temperature Storage
Ta = -55·C, 1000 hrs
42
0
Temperature
Cycling (11
-55°C - 25·C - 150°C
10 cycles
189
0
Temperature
CYCling (21
_20°C - 25°C - 125°C
500 cycles
44
0
Thermal
Shock
-55·C - 125°C
15 cycles
44
0
Soldering heat
260°C, 10 sec
44
0
Solderability
230·C, 5 sec
44
0
Mechanical
Shock
1500G, 0.5 msec
3 times/X, Y, Z
44
0
Vibration
Variable Freq.
20 - 2000 Hz, 20G
3 times/X, Y, Z
44
0
Constant
Acceleration
20000G
1 miniX, Y, Z
44
0
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
33
Reliability Test Data of Microcomputer
4. PRECAUTION
4.1 Storage
It is preferable to store semiconductor devices in the follow·
ing ways to prevent detrioration in their electrical charac·
teristics, solderability, and appearance, or breakage.
(I) Store in an ambient temperature of 5 to 30°C, and in a
relative humidity of 40 to 60%.
(2) Store in a clean air environment, free from dust and active
gas.
(3) Store in a container which does not induce static electric·
ity.
(4) Store without any physical load.
(5) If semiconductor devices are stored for a long time, store
them in the unfabricated form. If their lead wires are
formed beforehand, bent parts may corrode during storage.
(6) If the chips are unsealed, store them in a cool, dry, dark,
and dustless place. Assemble them within 5 days after unpacking. Storage in nitrogen gas is desirable. They can be
stored for 20 days or less in dry nitrogen gas with a dew
point at _30°C or lower. Unpacked devices must not be
stored for over 3 months.
(7) Take care not to allow condensation during storage due to
rapid temperature changes.
4.2 Transportation
As with storage methods, general precautions for other
electronic component parts are applicable to the transportation of semiconductors, semiconductor-incorporating units
and other similar systems. In addition, the following considerations must be given, too:
(I) Use containers or jigs which will not induce static electricity as the result of vibration during transportation. It is
desirable to use an electrically conductive container or
aluminium foil.
(2) In order to prevent device breakage from clothes-induced
static electricity, workers should be properly grounded with
a resistor while handling devices. The resistor of about I M
ohm must be provided near the worker to protect from
electric shock.
(3) When transporting the printed circuit boards on which
semiconductor devices are mounted, 'suitable preventive
measures against static electricity induction must be taken;
for example, voltage built-up is prevented by shorting
terminal circuit. When a belt conveyor is used, prevent the
conveyor belt from being electrically charged by applying
some surface treatment.
(4) When transporting semiconductor devices or printed circuit
boards, minimize mechanical vibration and shock.
to apply surge voltage from the tester, to attach a clamping
circuit to the tester, or not to apply any abnonna1 voltage
through a bad contact from a current source.
During measurement, avoid miswiring and short-circuiting.
When inspecting a printed circuit board, make sure that no
soldering bridge or foreign matter exists before turning on the
power switch.
Since these precautions depend upon the types of semiconductor devices, contact Hitachi for further details.
4.4 Soldering
Semiconductor devices should not be left at high temperatures for a long time. Regardless of the soldering method,
soldering must be done in a short time and at the lowest possible temperature. Soldering work must meet soldering heat test
conditions, namely, 260°C for 10 seconds and 350°C for 3
seconds at a point I to 1.5 mm away from the end of the device
package.
Use of a strong alkali or acid flux may corrode the leads,
deteriorating device characteristics. The recommended soldering
iron is the type that is operated with a secondary voltage supplied by a transformer and grounded to protect from lead
current. Solder the leads at the farthest pOint from the device
package.
4.5 Removing Residual Flux
To ensure the reliability of electronic systems, residual flux
must be removed from circuit boards. Detergent or ultrasonic
cleaning is usually applied. If chloric detergent is used for the
plastic molded devices, package corrosion may occur. Since
cleaning over extended periods or at high temperatures will
cause swollen chip coating due to solvent permeation, select the
type of detergent and cleaning condition carefully. Lotus
Solvent and Dyfron Solvent are recommended as a detergent.
Do not use any trichloroethylene solvent. For ultrasonic cleaning, the following conditions are advisable:
• Frequency: 28 to 29 kHz (to avoid device resonation)
• Ultrasonic output: 15WI~
• Keep the devices out of direct contact with the power
generator.
• Cleaning time: Less than 30 seconds
4_3 Handling for Measurement
Avoid static electricity, noise and surge-voltage when semiconductor devices are measured. It is possible to prevent breakage by shorting their terminal circuits to equalize electrical
potential during transportation. However, when the devices are
to be measured or mounted, their terminals are left open to
provide the possibility that they may be accidentally touched
by a worker, measuring instrument, work bench, soldering iron,
belt conveyor, etc. The device will fail if it touches something
which leaks current or has a static charge. Take care not to·
allow curve tracers, synchroscopes, pulse generators, D.C.
stabilizing power supply units etc. to leak current through their
terminals or housings.
Especially, while the devices are being tested, take care not
~HITACHI
34
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
PROGRAM DEVELOPMENT AND SUPPORT SYSTEM
• PROGRAM DEVELOPMENT AND SUPPORT SYSTEM
OF B-BIT 116-BIT MICROPROCESSOR
H680S02oo loads a universal as, CP/M.68K® developed
jointly w~ Digital Research Inc. and operates with the exist·
ingCP/M .
H680SD200 is prepared as system development device to
develop software and hardware of various types of microcom·
puter system.
Fig. I shows the program development procedure using this
system development device.
'CP/M®and CP/M-68K®are registered trademarks of D,gita'
Research Inc.
Assembler
~.?~;~C~} \~~~~or)
C Complier for
630116303)
and 68000
Error
Software
~ebug
No
In Case of
H660SD200
~
,,", " '
"""
.
I"
", i
.
Fig. 1 Program Development Procedure
$
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
35
Program Development and Support System
Table 1 System Development Equipment SD200
MPU
-
-
16·bit
MPU
HD68000
8 bit
MPU/MCU
Product Name
Function
Product Code
Note
CP/M·68K
S680CPM3F
• Single user Operating System
• 68000 Assembler, C complier, Screen editor and
Linker are included
VAX-11
Interface Program
S680CLC3F
• Interface Program between the SD200 and theVAX·11.
• File transfer function.
Option
• VT52 Terminal Emulation.
DATA 1/0
EPROM Programmer
I nterface Program
S680CDl1F
• I nterface Program between the SD200 and the
DATA I/O EPROM Programmer model 22/29.
PKW·1000/7000
EPROM Programmer
I nterface Program
S680CPK2F
• Interface Program between the SD200 and the
PKW·100017000 EPROM Programmer (Aval Corp.
Japan)..
FORTRAN
S680CFR1 F
• FORTRAN Compiler. (Subset of FORTRAN77)
Option
Super PLIH
S680CPL 1 F
• Super PLIH Compiler.
Option
Symbol ic Debugger
S680CSD2F
• Symbolic Debugger for programs written in 68000
Assembler or Super PLIH.
Option
64180ASE
S180CAS1 F
• Realtime In·circuit Emulator for 64180.
Supplied with
H180AS01E
S35XAS6·F
• 6305Z/63L05/6805 Macro Assembler.
• Linkage editor is included.
OPtion
6301/6801/6800
Macro Assembler
S31XAS6·F
• 6301/6801/6800 Macro Assembler.
• Linkage editor is Included.
Option
6301
CCompiler
S31CCLN·F
• C Compiler for 6301 (63031.
Option
6305/63L05/6805
Macro Assembler
~HITACHI
36
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
Program Development and Support System
Tabl e 2 Cross System
MPU
Machine
Intel
MDS
OS
Product Name
Product Code
ISIS·II
6305/63L05/6805
Assembler
S35MDS1·F
6305/63L05/6805 Assembler.
Object code is absolute address format.
Conditional assemble function.
CP/M
6305/63L05/6805
Assembler
S35MDS2·F
6305/63L05/6805 Assembler.
Object code is absolute address format.
Conditional assemble function.
ISIS·II
6301 Assembler
S31MDS1·F
6301/6801 Assembler.
Object code is absolute address format.
Conditional Assemble function.
CP/M
6301 Assembler
S31MDS2·F
6301/6801 Assembler.
Object code is absolute address format.
Conditional Assemble function.
6301
Macro Assembler
S31IAS1·F*
630 1 Macro Assembl er.
Linkage Editor is included.
6305
Macro Assembler
S35IAS1·F*
6305 Macro Assembler.
Linkage Editor is included.
8·bit MCU
IBM·PC
Function
PC· DOS
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
37
Program Development and Support System
Table 3 Third Parties' Products
Assemblers for HITACHI's microcomputers are provided by
the other companies. Hitachi introduce some venders and their
Vender Name
products listed below. Please contact those venders directly if
you have questions or requests to purchase these products.
Product Name
OS/System
Product Code
ASM68
6301 Assembler
6305 Assembler
ASM05
6809 Assembler
ASM69
ASM68K
68000 Assembler
VAX11
MICROTEC
505W Olive, Suite 325
Sunnyvale, CA94086
(4081733·2919 U.S.A.
64180 Assembler
ASM180
64180 Simulator
INT180
64180 C
MCC180
64180 Pascal
PAS180
6301 Assembler
ASM68
ASM05
6305 Assembler
IBM·PC
64180 Assembler
ASM180
64180 C
MCC180
64180 Pascal
PAS180
6301 Assembler
CAMELOT
79 London Road
Knebworth Herts,
SG3 6HG,
England
Stevenage (04381812215
AVOCET SYSTEMS, INC.
804 South State St.
Dover, DE19901
(302) 734·0151
U.S.A.
MICROWARE SYSTEMS CORPORA·
TION
5835 Grand Avenue
Dos Moines, IA50312
(5121279·8844 U.S.A.
.
IBM·PC
6305 Assembler
6800/680116301
Assembler
CP/M
MS·DOS, CP/M.86
XASM·68
6805 Assembler
CP/M
MS·DOS, CP/M.86
XASM·05
6309/6809
Assembler
CP/M
MS·DOS, CP/M.86
XASM·09
64180 Assembler
CP/M
MS· DOS, CP/M.86
XASM·180
6309/6809
Assembler
68000/68HCOOO
Assembler
OS·9
OS·9
KCRS
·Under development
~HITACHI
38
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
Program Development and Support System
•
Development System for 4·Bit, 8-Bit, end l6·Bit
Microcomputers
The H680SD2oo is a development system for Hitachi 4.bit,
8.bit and l6·bit microcomputers. It is a desktop system in
which a l6·bit microprocessor H068000 is loaded as the CPU.
Its standard system configuration includes a CRT, a keyboard,
and two floppy disk drives. An assembler, compiler, and in·
circuit emulator (ASE) associated with the user's MCV are
available as options.
APPLICABLE DEVICES
• HMCS400 series
• HD6305U. HD6305V
• HD6301V, HD6301X, HD6301Y
• HD64180
• HD68000, HD68HCOOO
(Other 4-bit and 8-bit microcomputers will be supported in the
future)
HD64180 THIRD·PARTY DEVELOPMENT TOOLS
Product: Cross·Assemblers and Cross·Compllers
Company
Amellcan Automation
1714·731·1661)
Mlcrolec Research
1400·733·2919)
Avocet Systems
1000·440·0500)
2500AD Sollware
(303·369·5001)
BSO
1617-094·7000)
SumltrOnics
(408·737·7683)
SLR Systems
(800-033·306 I )
ASM
S/W SIM
C COMP
VII
VII
VII
PASCAL
VII
VII
VII
Vii
CII
CII
V
V
BASIC
CII
V
V
V
C
UmwarelSDS
V
(312·971·0170)
Soltalcl
(800·433·0812)
Allen Ashley
1818·793·5748)
C
II" IBM-PC. V =VAX. C = CPIMI
•
•
•
•
•
•
•
•
•
FEATURES
AdoptS general CP/M-68K® operating system
Two internal 8 inch floppy disk drives (double-sided, doubledensity) and a 40M byte hard disk (available as an option)
make it possible to provide substantial external memory.
Since CRT editor (screen editor) is included in the standard
system, efficient programming, editing, and debugging of
source programs are possible.
C compiler for HD68000 is included. FORTRAN and Super
PL/H for HD68000 and C Compiler for HD6301 (HD6303)
are available as options.
User prototype system can easily be debugged using incircuit
emulator (ASE) associated with the user's MCU.
With connection of VAX-11® to RS-232C interface,
H680SD2oo operates as VAX-11® (OS, VMS) work station.
When 2M byte memory board is connected, high-speed
operation can be realized.
Following interface are included
(1) EPROM programmer
(2) Printer (Centronics specification)
(3) Serial interface emulator for 4-bit and 8-bit single chip
microcomputers
·CP/w.®iS. register.d tr.de m.rk of Digital R....rch Inc.
.. V AX-"® is a registered tred. m.rk of Digital Equipm.nt Corp.
Product: Support Tools
Company
Product Description
Electronic Moldmg
1401 -769·3000)
Robinson Nugent
(012·945-0211 )
Yamalche/Nepenthe
(4 I 5·856·9332)
Methode ElectroRiCS
1312·392-3500)
TSI. Inc
(800-074·2280)
Mlcromlnt
1800·635·3355)
Shrink-DIP Adapter lor Breadboarding
PIN 20764·72-341
Shrink-DIP Socket
PIN TSS-6475-TNG
Shrink-DIP Socket PIN te 38-6407S·G4
S-O Test Socket PIN IC 76-64075-G4
PLCC Adapter for Hitachi's ASE
64180 IBM-PC Card With DSD80 Remote
Software Debugger
64180 Evaluallon Board
PIN SB180
Product: Operating Systems
Company
Echelon
(415-948,3020)
JMI Software
(215-620-0840)
Oecmallon
(400-900-1678)
Hunter & Readv
1415·326·2950)
lPI
(516·938-6600)
Type of Operating Sy••em
ZCPR3 (CP/M)
C ExecutlVe/80 Muill-Tasking Kernel
QUick-Task RealUme ExecutIVe
VRTX/80 Multi-Tasking Kernel (Z80)
MTOS/BO Multi-Tasking Kernel (ZeD)
HITACHI ORDERING INFORMATION
Part Number
Delerlpllon
H180ASE02
Adaptive System Evaluator, ASE-II
H680SMOIS
H180ABX
8 MHz Buffer Box tor ASE·I User,
256K Byte Emulation Memory Board (Option)
Includes V2.0 System Software
H100CP01
PLCC·68 MPU Adapt.r lor 1 Mby1.
AddreSSing (Option)
H680S0200
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
39
Device Availability
HD64180S
HDI80ABX02H(4)
HS180ABX05H(4)
ASE (Adaptive System Emulator)
HS180ASTOI H
HS180AST01H
User Cable
HS180ACUC1H
Emulator
H
HD6305X2
HD64180R
Description
HD6303R
HD6303X
HD6303Y
HS31 VEML04H(1)
HS31XEML02H(1)
HS31YEML03H(1)
HD35YEML05H(1)
(H31 MIX4j(2)
(H31 MIX2)(2)
(H31 MIX3)(2)
(H35MIX5)(2)
HD6305Y2
A
R
D
W
A
R
E
Emulation Memory
H84EMB02
Board up to 84K Byte
H64EMB02
H680SMOI S(6)
Emulalion Memory Board
H680SMOI S(6)
US180EVBOI H
Evaluation Board
HS31 YESS 11 H
Programming Socket Adapter
Programming Socket Adapter
Programming Socket Adapter
S35IBMPC(3)
Cross Assembler (IBM-PC)
S311BMPC(3)
S31IBMPC(3)
S31IBMPC(3)
C Complier (IBM-PC)
US31PCUISF
US31PCUISF
US31PCUISF
M21TOO6
M21T132
M21TOO6
M21TOO6
M21TOO6
M21T132
M21T132
M21T132
M21TOI9(5)
M21TOI9(5)
M21TOI9(5)
M21T020(5)
SOFTWARE
L
I
T
E
R
A
T
U
R
E
Data Sheet
f---Hand Book
M21T132
M21T132
Specification Sheet
M21TOll
M21T013
Hardware Manual
M21T053
M21T053
Product Bnef
M21T025
~HITACHI
40
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
Device Availability
HD641180X
HD643180X
HD647180X
H064180Z
HS180ABX04H(4)
HS180ABX03H(4)
HS180ASTOl H
H0648180W'
H06309"
H068HCOOO"
H068000"
H06802"
H06803
H06809"
HG1EVT2(1)
HS 180ASTOl H
HS180ACUCl M
H64EMBOI
H680SMOl S(6)
H660SMOl S(7)
HS18XESFOI H
HS18XESCOI H
HS18XESSOI H
HS18XESGOl H
M21T132
M21T132
M21T012
M21TOll
M21T113
M21T053
M21T026
M21T025
M21T132
M21T132
M21T132
M22TOO3
M21T132
M22TOO3
M21T132
M21TOO6
M21T132
M21T132
(Note) 1. Emulator Includes an RS-232 port for connecllon to IBM PC or PC compatible machines. Software not Included.
2. Same as footnote (1) above, but shipped with cross assembler (8" floppy disk) that operates with Hitachi's H68SD5 development system.
3. Developed by one of Hitachi's engineering subSidiaries Cross assembler Include software utility to downloadlupload code between PC host
and emulator.
4. Must be used with ASE station (PIN: HS180ASTOl H)
5. Includes user's manual, hardware and software application notes, and other relevant Information
6. 64K bytes user memory is provided in standard configuration. Can be expanded up to 512K bytes. Maximum of two 256K byte memory
boards can be Installed (optional) .
• Contact Marketing.
""Refers to third-party support tools.
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
41
Device Availability
C Compiler - - - -_ _ _ _ _ _ _ _ _ __
J
Cross _ _ _ __
Assembler
EPROM On-Package LSI - . . .
EPROM On-Ch,p LSI - - - - - ,
Emuidtor
Programming
Socket Adapter
Typical Support Tools for HD6303/05 Series
•
SINGLE-CHIP MICROCOMPUTER SUPPORf SYSTEMS
HItachi and Its engmcenng sub:'IJwnes make huu.I'Aare and ~oft
ware support tools to operat(' wIth mati\, popular h{)~t . :olllputer~ and
expedile the development of the mlcrocomputer-hased target system. The support system Include!' tn-clrcult nnulato[,'}, cro."'~ a~senl'
biers, passive socket adapters for easily plOgramnling EPROM onchip devices, and documentation.
In additIOn to hardware and sott"aIe suppon, Hitachi has Field
ApplIcation EnglOcers (FAE) to help IdenldY the most cost-effective
lCis) for your applIcatIOn and answer your technical questions
•
•
•
•
•
•
IN-CIRCUIT EMULATOR FUNCTIONS FOR HD6303/05 Series'
Senallllterface connectIOn (0 man) h'''1 compUlc" via RS-232C
pOri.
Executes user';.. program m lcai-tlfllc on ~om!.." ?mulator~. OJ
when loaded In emulator's memory starting lrorn a ~ck\~terl address. ExecutIOn is llltarupted when breakpOInts are detected, or
when RESET or ABORT IS switched
Single step tracing of user's prog,mn is possible. Data III register>
and data In memory are dISplayed alter every executIOn
BreakpOInts can be set In user's program by USIng the pro31am
counter address, data bus, or external Signal probes Breakpoint,
can be dISplayed and changeJ.
Data In internal registers of the subject nllcrocomputer can be
displayed or changed
I" sct
LIne as~eInblcr and dba~\cmhlcl on ~ome emulators
*FunctlOns listed In the overVIew HUY not eXdC't1y apply to all emulator~ Retei to the appllcabie emulator u~cr'i-I manual tor further
mfOrmatlofl
•
•
•
RC;tl-tUllC tracing !~ rO~~lbk on most emulator~, the emulator
stores and J"p!uys bus dat" and external Slgllal> lor up to lOll
machIne cycles on some emulators, 01 2035 machlllc cycle,., on
other crnulator~ bct()re and Jfter the addrc~s where a breakpomt
•
•
CROSS ASSEMBLER FUNCTIONS (PC-DOS)
The ,oftwale " diVIded mto '" main pari'.
Stru<:tured Reloeatahle Cross Mano Assemhler
The cross assembler IS designed to meet the specificatIOn outlIned
In HitachI's HD6303 and HD6305 assembler user's manual,
WhICh means that mnemOnIC, macro and directive compatibIlIty
IS mamtamed
The assembler also offers a structured code faCIlIty, similar to
that f(lUnd in some high level languages The mam structured
features are hsted hdow
IF.
THEN
. ELSE
. DO
WHILE.. REPEAT
UNTIL.
FOR.
TO
CAl.L (wIth pam met"" pa"ed on the stack)
Linker
The linker concatenates and locates all relocatable modules IIlto
~HITACHI
42
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
Device Availability
•
•
•
•
an executable object file (Motorola S-type /(lfmat). Start addrc"es of rclocatable program and data ,ect",", can be entered at
linkage tIme
Macro Librarian
Named libranes of useful macros can be built by the user, savIDg
time dunng generallon of source code. The macro IIbranan IS
searched during assembly lime for the appropriate macro dennltio", that do not appear ID the source file
Object Module Librarian
Named Iobrane, of useful object modules can be bUIlt by the user.
The hbraries called up at linkage time are searched by the linker
to sec tf unsatisfied external references can be resolved. Object
modules whIch satisfy the unresolved references are automatically included ID the executable object file (S-record format).
Emulator Interface Software
The IDterface software allow, connecllon between Hitachi's serially linked emulators and the IBM PC using an RS232 asynchronou~ mterface.
Commands from the PC keyboard are dtrected to the emulator
and responses are displayed on the screen. File upload and
download ID Motorola S-type format enables assembled and
linked program, to be run on the emulator. Real time trace facilities are available on all serial linked emulators.
EPROM Programmer Interface Software
The Interface software allows connection to most proprietary
EPROM Programmers for downloading (or uploading) executable ohJect modules in Motorola S-type* data format. The programmers can be run either In REMOTE CONTROL or LOCAL
mode.
In local mode, programmer commands can be entered on the
programmer keyboard and upload/download of object modules
can be actIvated USIng the IBM PC keyboard.
In remote control mode, all programmer command!>. are entered vIa the IBM PC keyboard
All programmer commands WIll be speCIfIc to the particular
programmer u,ed.
C COMPILER FUNCTIONS (PC-DOS)
The HD6303 and HD6305** compiler comprises three programs, a pre-processor, the main compiler and an optimiser. The
system also provides standard library files (which facilitates 110
and tloatmg point operations), the standard "include" files
which contam the necessary declarations for the usage of library
function, Runtime object files for integer and tloating point
arithmetic are included. Compatible with Hitachi and Microtec
Research*** assemblers.
• Compiler Options
The following tables indicate the options available dunng preprocessmg and compiling.
Table 1.
No.
Pre-processor Options
Opt\(m
Descnptlon
I
A
hsues error me~sagcs to the pre-processor
,ource program file
2
D
Define~
3
L
Table 2.
No.
a macro name
Inserts the origmal ,ource program Imes
mto the pre-proce;;ed ,ource program as
comments
Compiler Options
Option
Descnptlon
I
p
Generates object code whIch calls a
profiler routine (a routtne whIch profiles
the hIstory of the program executIon)
everyume a functIOn IS called (see
Note I).
3
L
check routme everytHne a function IS
Generates object code whIch calb a stack
called (,ee Note I)
Note 1: The profiler routine and the stack check routine
should be prepared in a separate module for your own target
system.
•
Limits in Compilatioll
(I) Length of an input line 512 characters
(2) Length of a character stnng. 510 characters
(3) Number of external names 156
(4) EffectIVe length of Idenufiers. 8 characters
(5) EffectIVe length of external IdentIfiers 6
(6) Nest of condlllonal compllcatton 32 level
(7) Nesting of file meluslOn. 14 level
(8) Number of macro parameter,. 32
(9) Length of a macro deflmllon. 512 characters
(10) Recursive expansion of a macro name: 32 times
•
Data Size
(I) Char type: 8 btl
(2) Short type, int type. 16 bIt
(3) Long type: 32 bit
(4) Float type: 32 bIt
(5) Double type: 64 bit
(6) Pointer type: 16 btl
No data alignment is done in allocatIOn of structured data
•
*Motorola S-type is a trademark of Motorola, Inc.
**Conforms to Kerninghan and RitchIe C programming
language standard rather than ANSI C programming language
,tandard.
***Microtec Research is a trademark of Microtec Research, Inc .
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
43
Device Availability
(3) Character Handling Library Functions
isalnum. Isalpha, issascii, iscntl, isdigit, islower, isprint.
ispunct, isspace, isupper, tolower, toupper.
(4) Character String Handling Library Functions
index, rindex, streat, strcmp, strcpy, strlen, strncat,
strncopy
(5) Data Conversion Library Function
atoi, atol
(6) Memory Allocation Library Functions (see Note 2)
malloc, calloc, free, cfree
(7) Miscellaneous Library Functions
NOTE 2: To use the 110 library functions and Memory
allocation library functions, low level routines must be
prepared by the user according to the target system
requirements.
IJ\lIPClII'i1
+-
<;lIIllMP('
I 6303 Standard Library
I
L _
_
_ ___. ..J 6303 Relocatable Object
Linker
I
• IN-CIRCUIT EMULATOR FOR HD64180 SERIES
Hltachl's hardware emulator consists of the Adaptive System Emulator (ASE) plus emulator box for the corresponding microprocessor.
The emulator supports hardware and software development when
connected to a Vax-II, IBM-PC, or PC compallble host machine.
• ASE FEATURES
• Seflal connectIOn to host computer, or console via RS-232C port
allows loadmg, saving, and verifymg of user programs.
• Object formats' Intel HEX; and Motorola S.
• Connects to centronics pnnter.
• Includes 3.5 Inch floppy disk drive.
• EMULATOR BOX FEATURES
• Executes program in realtime from 0.5 MHz to 8 MHz for all
emulators except HSI80 ABX05H which executes in realtime
from 0.5 MHz to 10 MHz.
• Memory:
-Includes 64-kbyte user memory
-Expandable to 512 kbytes with an optional memory board (up to
6 MHz without walt states)
• EMULATOR BOX FUNCTIONS
• Executes user's program loaded in emulator's memory:
-Realllme
-Smgle step
• Breaks on combmallon of specified number of the following
conditions:
-Program counter (logical or phYSical address)
-Access to specified memory area
-DMAC transfer request or completion
-Eight external probe signals
• Up to 255 software breakpoints on RAM area
• Multi-break function: In multi-MPU system using several ASEs,
an ASE break acts as a tflgger which causes other ASEs to break.
(HSI80ABX05H).
• Sequcnt131 break: Analyzes order m which up to 4 software breakpomts were passed (HSI80ABX04H/05H).
• Realtime tracing.
-Stores or displays bus mformation, external signal, or 110 signals for up to 2048 machme cycles
-Traces by bus cycle or 125 ns after user program execution stops
at breakpomt
-Trace startmg or extracting condillon can be specified
• Pseudo-II0 emulation funcllon (HS l80ABX04H/05H)
• Disassembler
• Line assembler
• Symbolic debugger
• Execution time measurement
• Displays, sets, changes, or transfers data In memory
~HITACHI
44
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
8/16-BIT MICROPROCESSOR DATA BOOK
I DATA SHEETS I
Section 1\vo
HD6300, HD6800
8-Bit
Microcomputer Family
~HITACHI
HD6303R,HD63A03R,--HD63B03R
CMOS MPU (Micro Processing Unit)
The HD6303R IS an 8·blt CMOS mIcro processtng umt
whIch has the completely compatIble tnstruchon set wIth the
HD6301VI 128 bytes RAM. Senal Communication Interface
(SCI). parallel I/O ports and multI functIon timer are mcorpora·
ted 10 the HD6303R It IS bus compatIble wIth HMCS6800 and
can be expanded up to 65k bytes LIke the HMCS6800 famtly.
I/O level IS TTL compatIble wIth +50V smgle power supply
As the HD6303R IS CMOS MPU. power dIssipation IS extremely
low And also HD6303R has Sleep Mode and Stand·by Mode
as lower power dlsslpahon mode. Therefore. flexIble low power
consumptIOn appltcatlOn IS possIble.
•
•
•
•
•
•
•
•
•
•
•
•
FEATURES
ObJect Code Upward CompatlbJe wIth the HD6800, HD6801.
H06802
MultIplexed 8us (00/A O -0 7 /A 7 A.-A" I, Non MultIplexed
8us (0 0-0 7 , Ao-A ls I
Abundant On·Chlp FunctIons CompatIble wIth the
H06301V1; 128 Bytes RAM, 13 Parallel I/O Lones, 16·blt
TImer, Senal CommunIcatIon Interface (SCI I
Low Power ConsumptIon Mode, Sleep Mode, Stand·By Mode
Mlnomum Instruction Execution TIme
1ps (f=1MHzl, 0.67ps (f=1 SMHzl, O.5ps (f=2.0MHzl
BIt Manopulatlon, BIt Test InstructIon
Error Detectong FunctIon, Address Trap, Op Code Trap
Up to 6Sk Bytes Address Space
Wide OperatIon Range
Vcc =3 to 6V (f = 0 1 - O.S MHzl
f = 0.1 to 2.0 MHz (V cc = SV ± 10%1
HD6303RP, H063A03RP,
H063B03RP
(OP·40)
H06303RF, H063A03RF,
HD63B03RF
(FP·S41
HD6303RCG,HD63A03RCG,
HD63B03RCG
•
TYPE OF PRODUCTS
Type No.
Bus Timing
H06303R
H063A03R
1.0 MHz
HD63B03R
2.0 MHz
(CG-40)
1.5 MHz
HD6303RCp, HD63A03RCP
HD63B03RCP
PROGRAM DEVELOPMENT SUPPORT TOOLS
• Cross assembler and C compiler software for IBM PCs and
compatibles
• In circuit emulator for use with IBM PCs and compatibles
(CP·52)
HD6303RL, HD63A03RL
HD63B03RL
(CP-44)
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
47
HD6303R, HD63A03R, HD63B03R
• PIN ARRANGEMENT
e H06303RF, H063A03RF,
H063B03RF
e H06303RP, H063A03RP,
H063B03RP
1- ,- ;;( ; (
ii~
AS
RIW
OoIAo
E~
~
>
"".f")N~
(NC>
w
e H08303RCG, H083A03RCG,
H063B03RCG
~ I~ i
::;:~:;;
L:SJ L;J L8J ~~J ~~J ~~..: L~J L~J L~j L~J
6
O,IA,
(NC>
02 /A 1
(NC>
.... '"
O~N
N N
.( .(
'"
..c-« -<
c[
(Top View)
(Top View)
(Top View)
• HD 6303RL, HD63A03RL
HD63B03RL
eH06303RCP, HD63A03 RCP,
HD63B03RCP
NC
11m
STBY
P20
p"
P"
P2J
P"
P 22
oi
P"
p,.
NC
P"
INC)
AO/Pl0
Al/PI1
Ao IP1Q
A2I'PI2
A 1 /Pll
NC
A2 /P12
U~;!~~::~~!!
4
u
ze;,~~'t~><<«ci..tz
<..:«..:(0(
(Top View)
(Top View)
~HITACHI
48
A1s
Hitachi Amenca, Ltd. • Hitachi Plaza • 2000 Sierra Pomt Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
As/PIS
HD6303R, HD63A03R, HD63B03R
-------------------------------------------------------•
BLOCK DIAGRAM
--'
--'<{
1~101~
>~~~~
> x W LU,Z
~Ia:
to.-.-i--+-- P,a
p"
--- P n
Address
to++-H-- P 23
Data
-
P24
Buffers
----- P,o/Ao
-_PIllA,
------P,2/A2
Address
--_.-..... PIJ fAJ
P14/A4
Buffers
~-PI5/A5
- . - - - - PIelA"
----P,7/A7
~HITACHI
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
49
HD6303R, HD63A03R, HD63B03R
• ABSOLUTE MAXIMUM RATINGS
Symbol
Item
Unit
Value
Supply Voltage
Vee
-0.3-+7.0
V
Input Voltage
Operating Temperature
V,"
Top"
-0.3 - Vee+0.3
0- +70
V
·C
Storage Temperature
Tstg
-55 -+150
·C
(NOTE)
This product has protection
CirCUits In
Input terminal from high static electricity voltage and high electflc field.
But be careful not to apply overvoltage more than maximum rat lOgs to these high Input Impedance protection
Circuits. To assure the normal oPeration, we recommend Vln. V out ' VSS :;; (V m or V out ) :;; Vee-
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee = 5.0V±10%, Vss = OV, Ta = O-+70·C, unless otherwise noted.)
Item
Symbol
Test Condi tion
min
typ
Input "Low" Voltage
All Inputs
V ,L
Input Leakage Current
NMI, I RO J , RES, STBY
II," I
V," =0.5-Vee -0.5V
-
-
Three State (off-state)
Leakage Cu rrent
0 0 -0 7 , A.-A"
IITSII
V," =0.5-Vee -0.5V
-
Output "High" Voltage
All Outputs
V OH
Output "Low" Voltage
All Outputs
VOL
10L = 1.6mA
-
C,"
V,"=OV, f= 1.0MHz,
Ta= 25·C
Icc
V,L (STBY) =0-0.6\1
V,H (~) = Vee
-0.5- V ee V
RES, STBY
Input "High" Voltage
Vee-0.5
V ,H
EXTAL
Vce xO.7
2.0
Other Inputs
Input Capacitance
Standby Current
PIO - PI7, P'O-P'4,
All Inputs
Non OperatIOn
max
Unit
Vee
+0.3
V
O.B
V
1.0
IJ.A
-
1.0
IJ.A
2.4
-
Vee- 0.7
-
-
V
-
0.55
V
-
-
12.5
pF
-
2.0
15.0
IJ.A
pperatmg(f-l MHz")
-
6.0
Sleeping (f=IMHz**)
-
1.0
10.0
2.0
mA
-0.3
10H = -2001J.A
10H = -101J.A
V
V ,L (RES) = 0 - 0.6V
Current DIssipation'
Icc
RAM Stand-By Voltage
V RAM
2.0
-
-
V
* V1H min = Vcc-1.OV, V 1L max'" O.SV
.. Current DISSipation of the operating or sleeping condition IS proportional to the operating frequency So the typo or max,
values about Current DIssipations at f = x MHz operation are decided according to the following formula,
typ value (f =xMHz) '" typo value (f:: lMHz) xx
max, value (f =xMHzl = max, value (f:: 1MHli x x
(both the sleepmg and operatmg)
~HITACHI
50
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303R, HD63A03R, HD63B03R
•
AC CHARACTERISTICS (Vee
=5.0V±10%, Vss = OV, Ta = O~+70°C, unless otherwise noted.)
BUS TIMING
Item
Symbol
Test
Can·
dltion
HD6303R
HD63A03R
HD63B03R
I-~~.~~.~.j...-~~--,-.~>-~.-.-~
min
1!
typ
max min typ
-
10 0666 -
-;2-~1---f-'-
max min typ
10 0.5
max
-
Unit
10
fJ.S
15-;;'t--... f--;; -:::=t~-_ -~~t-~
.~-,.~~
.....
__ __.. '~.~ .~iq~= -'-e---
~
60··
~.
'-__
1------
:--
~: -
-:+
-
40-
'-----1---.-
=- _ .2.Q _::-
-
-
-
20
-
-450 ---~-0-
-
.- -
20
20
20
-::
-
ns
-.- . - -
=- _
-
~
ns
ns
20
30(t:::I-=~~!- .-:= -.. ~~ .~
.~. ~~lio 7oFl'~ ':, .~:-"~\L
-
-.330
-
250
-
-
190
160
ns
-~-'H~~1jr~~it'-~1~0 ~~~ 1~ I-~~'
=- _~O _-.+.::- 50 __ ."S_~
o
_--=----t,.-ol-=.r-=
_ 200 ~~I--~
20 20' ns
80 _ -=-
Address Hold Time for Latch
Addrtss Hold Time
.~..!
--
.- ---t~-
---f----
~~ ~- ~-f-~I~-,
=~~~
---+--
Address Set·up Time for Latch' __ I ~SL._
.."-"--
tAH
f-----+--l--.. . 200 ..1..1 ~ --=-__
::ri:::al~::~-ffl;':~~;':I~:;d :::~C'~
i--=-
--
---f-------
60
650 395
f-----+----+~+-- - ~I--Access Time
I
•
_::-:-1-.
650 i =-._
395 _.~~~~~-L-M_ultiplexed Bus (tACCM)
20
-120
20Oscillator stabilization Time
tAC
Fig.8
200 Fig.9 200 f---1-=--T2oQ
Processor Control Set·up Time
tpcs
*These timings change in approximate proportion to tcyc. The figures in
(= In the highest speed operation)
thiS
~
f----
-
.~~--
- .. ~
ns
270
ns
270 ns
ms
---ns
characteristics represent those when tcyc
IS
minimum
PERIPHERAL PORT TIMING
Item
Symbol
Peripheral Data
Port I, 2
tposu
Set·up Time
Peripheral Data
Port 1,2
tpOH
Hold Time
Delay Time, Enable Nega./ Port 1
tive Transition to Peri·
2'
' t pwo
pheral Data Val id
Test
Can·
dition
HD63A03R
HD63B03R
HD6303R
.Unit
;;;in I typ max min typ max min typ max
Fig.3
200
-
-
200
-
Fig.3
200
- -
200
-
--
Fig.4
-
-
-
-
300
-~'-~-
300
-
200
.
200
-
-
ns
-
-
ns
-
-
300
ns
• Except P:1I
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
51
HD6303R, HD63A03R, HD63B03R
TIMER, SCI TIMING
Test
Symbol Con·
dition
min
typ
Timer Input Pulse Width
tpWT
2.0
-
Delay Time, Enable Positive
Transition to Timer Out
tTOD
-
-
400
-
0.6
Item
Fig. 5
HD63A03R
HD6303R
SCI Input Clock Cycle
tSeye
2.0
SCI Input Clock Pulse Width
tpWSCK
0.4
Test
Symbol Can·
dition
min typ
3
max min
-
typ
HD63B03R
max min
typ
max
Unit
2.0
-
-
2.0
-
-
tcye
-
-
400
-
-
400
ns
2.0
-
-
2.0
tCYC
0.4
-
-
0.6
0.6
tScye
0.4
MODE PROGRAMMING
Item
RES "Low" Pulse Width
PW RSTL
Mode Programming Set·up Time
t MPS
Mode Programming Hold Time
tMPH
Fig. 6
max min
-
-
3
2
-
2
150
-
-
150
typ
-
max min
-
~--------------------t~--------------------
Addr~ss
Strobe
HD63B03R
HD63A03R
HD6303R
3
2
150
typ
max
-
-
Unit
tCYC
tcYC
ns
___I
2.4V
lAS)
Enable
lEI
MPU Write
Oo-D"A o-A 1
MPU Rood
0.-0,. Ao-A.
_
NotVahd
Figure 1 Multiplexed Bus Timing
~HITACHI
52
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
HD6303R, HD63A03R, HD63B03R
leve
'E,
Address Val,d
MPUWme
0,-0,
MPU R••d
0.-0,
------~-------+----------~
------~--------~---------------------{I
A.-A, (Port n
24V
A.-A"
06V
I!ZI2 Not Valid
Figure 2 Non-Multiplexed Bus Timing
r
rMPUReld
E~
lOV
OBV
O.8V
'I.'.e -- '1'u
P
Inputs
_tpwo
2 v
oav
All Oat.
2 .•V Oatl V,tld
Port Outputl _____________J'rI.:::O!:BV:....___
Figure 3 Port Data Set-up and Hold Times
(MPU Read)
Timer
MPUWrlte
Counter _______.I '-__.,::::::.::=---'
Note) Port 2: Except Pu
Figure 4 Port Data Delay Times
(MPU Write)
'-______
P"
Ou1put
Figure 6 Mode Programming Timing
Figure 5 Timer Output Timing
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
53
HD6303R, HD63A03R, HD63B03R
Vee
RL = 2.2kfl
14.0kfl for E)
e=90pF for AS, R/W, D,/A, - D,/A" and AS
Test POint
IS1074
=30pF for P20 .... Pl. and Ao/P 1o - A, {P17
®
=40pF for E
or Equlv.
e
R= 12kQ
R
Figure 7 Bus Timing Test Loads (TTL Load)
Interrupl
Test
Internal
Address Bus
'NMI iRQ;
Internal
Data Bus
~~:~nal
--lI....+-~=-::!'~~~=,A...,s~p,..,.~s~p;"1,J\-;S;;;P-;2J\.C~X;:;;!'(;;;;~=x.
Op Code per and Irrelevant peo _ PCB
IXO
IXB
_ _ . ~ata
PC7
PClS
IX7
IX'5
----~~-~~/:=========================~\~-------
Internal
Write
Figure B Interrupt Sequence
-
)\»\\\\»\\\\\\\\\\\\\\
I~
..,
~~\\\\\\\\\\\\\\\\\\\\
'~>-----l>-I- - - - - -
RIW _
~\\\\\\\\\\\\\\\\\\\\~W
:;""." ~",
~:.
I~>----- (A, - Als )
~HITACHI
56
0
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303R, HD63A03R, HD63B03R
Vee
x......- - - - I P J O
y.
P,.
z.
-o+----+-+....-1I----Ix,
PH
V,
P"
-oj---+-+.....,i--;z,
Y
(PCOI
Pl. (PC11
......- - - - I P o (PC2)
Inh
HOl40538
Note
1) FIgure of Multlplexed Mode
21 RC",=Reset Constant
31 R,=10kH
Mod.
Control
SWItch
Figure 11
Recommended CirCUit for Mode Selection
Truth Table
Control Input
-- -
- - _ - - On SWI,ch
$elect
InhIbit i-C:T:."'A+H-=O 140538
~__ 0 0 i~ ~o~~
o
xoo-----------~~~~--~~,
Xl
0
0
1
Zo Yg X,
o
1
0
Z~
Y, Xo
~ ~~_~~~
--DX
1 0
0
X.!_
Z, Yo Xo
yoO------------------~~#_~--_,
1
0
1
2, Yo X,
y,o~----------------
1
1
0
Z, V, Xo
1
1
1
Z, V, X,
x
X X
Zoo-------------1::lIowlIIg sendl I/O functIOns
• Bauds rate
'data fonnat
• clock
SOlllCC
• Port 2 bit 2 feature
It IS 4-blt wnte-only regISter. cleared by R'ES. The 4 bits are
considered as a pair of 2·hi! Ilelds The lower 2 bits control the
bit rate of mternal clock whlie the uppel 2 bit; control the
format and the clock select logrc
BltOSSO)
Bit I SS I
Speed Select
These bits select the Baud rate for the mternal clock The
rates selectable are function of E clock frequency of the CPU.
Table 5 lists the available Baud Rates
Blt2 CCO
BIt 3 CCI
Clock Control/Format Select
1
They control the data format and the clock select logiC
Table 6 defines the bit fIeld
•
Internally Generated Clock
If the user wish to use externally an mternal clock of the
senal I/O, the foIlowl!1g requirements should be noted
'CCI, CCO must be set to "10"
• The maxnllum clock rate must be 1-:/16.
• The clock rate IS equal to the bIt rate
• The values of RE and TE have no effect
•
Externally Generated Clock
If the user wIsh to supplv an external clock to the Sertal
I/O, the followmg requirements should be noted
• The CC I, ceo must be set to "I I" (See Table 6).
• The external clock must be set to 8 tnlles of the demed
baud rate
-The maXilllum external dock freq\Jency l~ E/2 clock
• Senal Operations
The sertal I/O hardware mllst be tnltlaitLed by the softwale
before operallon 11,e sequence Will be normally as follows
'Wlltmg the desrred operatulll control hits of the Rate and
Mode Control RegISter
• Wrttmg the demed operallon control hIts of the TRCS
regIster
If Port 2 bIt 3,4 are used for sertall/O. TE. RE bits may be
kept set When TE, RE bit are cleared dUfing SCI operatIon,
and subsequently set agam, It should be noted that TE. RE
must be kept "0" for at teast one bit tnne of the current baud
rate If TE, RE are set agam Within one bIt tillIe, there may be
the case where the InitialIZing of lllternal function for transmitter and receiver does not take place correctly
• Transmit Operation
Data transmISSion IS enabled by the TE bit
III
the TRCS
register When >;et, the output llf tlte transmIt shift Jeglstel
I>; connected with Port 2 hit 4 winch IS lI11condltJ()l1ally con·
f1gmed as an output
After RT:'i, the user should tnltlahle both the RMC regISter
and the TRCS regISter for deSIred opeutlon Setttrlg the TE hit
call~es a tranSJllISSIUn of ten· bIt rJealllblc oj "} "s FoiiowlI1g the
plealllble, Intcrnal synchrol1l/a!lon I~ e:-.tahllshed and the tJans·
ll11ttel IS leady to operate Then citilci of tile followltlg states
cXlsb
(I) If the transnnt data leglstel IS empty (TDRL ~ I), the
consecutive "} "s are traJl:.,nlltled lIldlc.:ltlng an Idle
states
(e) If the data ha, heen loaded Into the Tlansllllt Data
RegIster (TORE ~ 0). It IS tra",ferred to the output
shift leglster and data transmiSSIon beglOs.
Durtng the data transfer, the stMt bit ("0") IS first trans~
fefled Next the 8·blt data (begtrlnlllg at bIt 0) and fiually the
stop bit ("1 ") When the contents of the Transllllt Data RegISter
IS transferred to the output shift reg"ter, the hardware sets the
TDRE flag bit If the CPU falls to respond to the flag wtthrn
the proper time, TDRE IS kept :-.et and thcn a COlltlllUOUS slflng
of I's IS sent unttl the data IS supphed to the data regISter
•
Receive Operation
The receive operation IS enabled by the R~~ bIt The sellal
Hlput IS connected With Port 2 bit 3. The receiver operation
IS deterrnll1ed by the contents of the TRCS and RMC regISter
The received bit .)trearn IS synchronllcd by the fnst "0" (start
hIt) DUling 10·hrt tune, the data IS strobed approxImately at
the center of each bIt If the tenth hit IS not "I" (stop bit).
the system aSSLlmes a frallllI1g error and the ORFE IS set
If the tenth hit IS "1", the data IS transferred to the receive
data register, and the RDRF flag IS set. If the tenth b!l of the
next data IS received and stili RDRF IS preserved set, then
ORFE IS set lndlcatmg th:.1t an overrun errOl has occurred
After the CPU read of tire status regIster as a respon" to
RDRF flag or ORFE flag, followed by the CPU read of the
lecelve data leglster, RDRF or ORFE wril he cleared.
•
RAM CONTROL REGISTER
Tire regISter aSSigned to the addre\S $0014 gIves a statos
JI1forrnation about standby RAM
RAM ContrOl Register
Bit 0 Not used.
Bit 1 Not used.
Bit 2 Not used.
~HITACHI
62
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy. • Bnsbane, CA 94005-1819 • (415) 589-8300
HD6303R, HD63A03R, HD63B03R
Bit 3 Not u..d.
Bit 4 Not used.
Bit 5 Not u..d.
Bit 6 RAM Enable (RAME).
Usmg tillS control bit. the user can dl>able the RAM RAM
Enable bit IS 'el on the positive edge 01 RES and RAM "
enabled. The program can wflte "I" or "0" If RAME IS
deared. the RAM address becomes external address and the
CPU may read the data from the outSide memory.
Bit 7 Standby Power Bit (STBY PWR)
Th" bit can be read 01 wfltten by the user program. It IS
deared when the Vee voltage IS removed. Normally tillS bit
I> sci by the program before gOll1g Into sland·by mode When
the CPU recovers from stalld·by mode. this bit should be
checked If It IS "I". the data "f the RAM IS retained dUflllg
stand·by and It IS valid.
• GENERAL DESCRIPTION OF INSTRUCTION SET
The HD6303R has an upward object code compaHble with
the 11))6801 to utlille all ""tructlon set> of the HMCS6800
The e"el,.'utlOn tllne uf the key m~tluctlOIl IS reduced to lIlcrease
the system through.pul In addition. the bit operation mstluc·
tmll. the exchange lIlstrllctlOl1 between the lIldex and the
accuillulator, the sleep lIlstrllctlOn ale added. 11l1s section
descflbes
• CPU programming model (See Fig. 20)
• Addressing modes
• Accumulator and memory manipulation instructions (See
Table 7)
• New instruchons
·Index register and stack marupulation mstructlOns (See
Table 8)
• Jump and branch instruclions (See Table 9)
• Condition code register manipulahon instructions (See
Table 10)
·Op-code map (See Table 11)
• Cycle-by-cyc1e operation (See Table 12)
• CPU Programming Model
The programming model for the HD6303 R is shown in Figure 20. The double accumulator is physically the same as the
accumulator A concatenated wllh the accumulator B, so that
the contents of A and B is changed with executmg operation of
an accumulator D.
r
A
t~- - - - -
-
-
-
°U
7
0 - -
8
-
- -
- -
-
~
8 Bit
AccumulCllor~ A and B
~ Or 16811 Double Accumul;llO' 0
I-IIs_ _ _ _ _-"-_ _ _ _---'ol Indl!~ Ae9,~,er
(XI
I-lls-"-_ _ _ _ _ _ _ _ _---'ol
StaCk POInle' (SP)
I-IIs'--_ _ _ _-'-PC"-_ _ _ _-l01
PrOlllam Caunle. IPCI
,
every Instrucllon is shown along with execution I1me given m
terms of machme cycles (Table 7 to II). When the clock
frequency is 4 MHz, the machine cycle will be microseconds.
Accumulator (ACCX) Addressing
Only the accumulator (A or B) is addressed. Either accumulator A or B is specified by one-byte mstructions.
Immediate Addressing
In thiS mode, the operand is stored m the second byte of the
instruction except that the operand m LOS and LOX, etc are
stored in the second and the third byte. These are two or
three-byte mstructions.
Direct Addrelsing
In this mode, the second byte of mstruction indicates the
address where the operand is stored. Direct addressing allows
the user to directly address the lowest 256 bytes in the machine;
locations zero through 255. Improved execu lion times are
achieved by storing data in these locations. For system
configuration, it is recommended that these localions should be
RAM and be utilized preferably for user's data realm. These are
two-byte instructions except the AIM, OlM, ElM and TIM
which have three-byte.
Extended Addressing
In this mode, the second byte indicates the upper 8 bit
addresses where the operand is stored, while the third byte
indicates the lower 8 bIts. This is an absolute address in
memory. These are three-byte instructions.
Indexed Addressing
In this mode, the contents of the second byte IS added to the
lower 8 bits in the Index Register. For each of AIM, OIM, ElM
and TIM instructions, the contents of the third byte are added
to the lower 8 bits m the Index Register. In addition, the resulting "carry" is added to the upper 8 bits tn the Index Register.
The result IS used for addressing memory. Because the modIfied
address is held in the Temporary Address Register, there is no
change to the Index Register. These are two-byte instructions
but AIM, OIM, ElM, TIM have three-byte.
Implied Addressing
In this mode, the instruction itself gives the address; stack
pointer, index register, etc. These are I-byte instructions.
Relative Addressing
In this mode, the contents of the second byte is added to the
lower 8 bits in the program counter. The resulting carry or
borrow is added to the upper 8 bits. This helps the user to
address the data within a range of -126 to +129 bytes of the
current execution mstructlOn. These are two-byte instructions.
0
I
~
H
I
N
1
II C
-
Cond,llon Corle Reg's!!'. leCRI
CarryiBorrow from MSB
Over/1o,",
Zero
Nega',I/!'
IlItt'rrupt
Hill! Carry IFrom 8,,31
Figure 20 CPU Programming Model
• CPU Addressing Modes
The HD6303R has seven address modes which depend on
both of the instructIOn type and the code. The address mode for
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
63
HD6303R, HD63A03R, HD63B03R
Table
7
Accumulator. Memory Manipulation Instructions
Condition Code
Addressing Mode.
OperMlom
Mnemontc
DIRECT
IMMEO
-
OP
-•
ADDA
88
2
ADD8
CB
_Doable
ADOD
C3
Add AccumulatOr.
A8A
Add With c.rry
AOCA
AND
ANOS
BI' Test
81T A
BIT B
CI••r
CLR
Compet.
Accumulators
Complement, 1',
Complement, 2',
-•
OP
-•
2 A8 4 2
2 2 08 3 2 E8 4 2
3 3 03 4 2 E3 5 2
2 98
3
IMPLIED
ArithmetiC Operetlon
OP
-•
88
4
3
A +M ..... A
F8
4
3
8+M .... S
F3
5
3
OP
-•
I
1 A + 8 .... A
2
2 99
3
ADC8
C9
2 2 09
3
2 E9
4
2 F9
4
3
A+M+C-A
8+M+C-B
ANOA
84
3
2
A4
4
2
84
4
3
A·M-A
C4
2 2 94
2 2 04
3
2 E4
4
2
F4
4
3
8·M- B
85
2
2 95
3
2
AS
4
2
85
4
3
A·M
C5
2
2 05
3
2 E5
4
2 F5
4
3
8·M
7F
5
3
00- M
2
A9
6F
4
2 89
5 2
4
3
eLAA
4F
1
1 00"'" A
elAS
SF
I
I
eMP"
81
CI
2 2 91
2 2 01
3 2
3
2
AI
El
4
2
81
4
3
4
2
Fl
4
3
8-M
63
6
2
73
6
3
11
CeA
COM
43
COM8
53
60
NEG
6
2
70
6
1 1 A -A
1 1 8 - 8
00- M ...... M
NEGA
40
NEG8
50
1 1 OO-A .... A
1 1 00-8-8
DeCimal Ad,urt. A
OAA
19
2 I
o.crement
DeC
4A
1
INegat.,
5A
OEC8
excluSlw OR
Increment
L_
Accumulator
EORA
88
2 2
98
3
2
AS
4
2
88
4
3
EOR8
C8
2
08
3
2
e8
6C
4
2
F8
4
3
6
2
7C
6
3
2
INC
4C
INCB
5C
86
2
2 96
3
2
,
A + 1 ..... A
1
1 1 8 + 1 .... B
M-A
2
3
M-B
2
FC
5
3
M + 1 ..... 8, M -.. A
2
e6
la.d Double
Aceumu"tor
LOO
CC
3 3
DC
•
2
ec
5
Multlplv Un",gn";
MUL
OR. 'ncluslve
ORAA
BA
ORAB
CA 2
7
2 AA
• 22 BA [-.- 3 ~
• 3i;~ ,._- --f-
eA 4
PSHA
1
FA
3
A
I(
B ...... A
B
A + M ...... A
B + M ...... B
A ..... Msp. SP - 1 ..... SP
B ..... Msp. SP - 1 ...... SP
PSHB
37
4
Pull Dill
PULA
32
33
3 1 SP .. '-SP.Msp-A
3 1 SP .. ' ...... SP.Msp .. 8
ROlli. L.ft
ROL
49
1
PUlB
69
6
2
7'
6
3
ROLA
1
59
1 1
RORA
46
1 1
AORB
56
1
ROL8
Rotet. Right
1
ROR
66
6
2
76
S.
3
Note) Condition Code Register will be explained In Note of Table 10
1
I
I
I
I
I
I
I
I
I
:
~l ~b7I
I I I I I
•
:J L?1 !
•
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
R
R
b1
I ! [ I I
I
I
I
I
I
I
I
I
I
I
I
I
I
R S
R S
R S
(j)~
(f) ~~
r(J
(2/
I I1J
I
I @ •
I @ •
I (,j) •
I R
I
I
R
I
I
I
I
I
@'
@.
@.
I
I
I
R
I
R
I
I
R
I
I
I
R
I
R
I
I (tl I
I @ I
I @ I
I @ I
I @ I
I
I
I
3
4
3
2
M + 1 ..... M
4
D6
8
~
B6
2
OA 3
M- 8
F6
2
2
0
2
C6
PUlh 0111
AG M-A
4
LOAS
3
A-1 .... "
1 B-1 .... 8
A6
4
2 2 9A
1
B
INCA
LOAA
1
-
2
··
· ··
··
·· ·· ··
·· ·· ··
·· ··
·· ··
·· ··
·· ··
·· ··
·· ··
·· ··
·· ··
·· · ··
·· ··
·· ·· ·
·· ·· ··
·· ·· · · · ·
·· ·· · · · ··
·· ·· ·· ·· ·· ··
·· ·· · · · ·
·· ··
riJ · ·
·· ··
I
I
I
Converts binary add of BCD
characters Into BCD format
M - 1 .... M
SA 6 2 7A 6 3
OeCA
C
3
R S R R
1 1 A-8
3
0
I N Z V
R S R R
M-M
COMA
I
H
I R
I R
R S R R
00- 8
A-M
4
I
M+ , .... A
8+M
A
18
5
I
89
CMPB
Comper.
OP
Regilt.,
EXTEND
INDEX
Bool ••nl
@
1,::1
GO
bO
I
I
I
I
I
~.,
(to be contmued)
~HITACHI
64
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303R, HD63A03R, HD63B03R
Table 7 Accumulator, Memory Manipulation Instruction,
Condltton Code
Addr.ulng Modes
Oper.tlons
Mn.monlc
IMMEO
D.
St-uft left
Anthmetlc
DIRECT
-•
0.
INDEX
Regllt.r
EXTEND
- • op - • 0 • - • op
68
ASL
6
2
78
6
Bool .. nl
Amhmetlc Oper.llOn
IMPLIED
-•
3
H
M
A j ~lllllIlt-o
~
ASlA
48
1 1
ASL8
5&
1 1
Double Shift
Left, Arithmetic
ASLO
05
1 1 ~
Shih R.ght
ASR
ArithmetIC
Shift Right
Loglelll
Double Shih
RIghi logical
LSAA
44
1
LSRS
54
1 1
LSRO
04
1 1 o.....{
LSR
64
A7
STAB
07
3
2 EI
Store Double
STD
DO 4
SUBA
80
2 2 90
SU88
CO
2 2
Double Subtfeet
SU8D
83
3 3 93
Subtreet
S8A
Trlnsf.,
Accumulltors
T"1 Z.ro or
Minus
110
Ace AI
4
4
2 ED 5
3 2
AO 4
DO 3 2 EO
4
6
2 A3
4
2 74
6
3
A_ M
2 F7
4
3
B_M
2 FD 5
A_ M
B ..... M+ 1
A -M .... A
2 FO
4
8 -M_8
A
2 92
3
2
A2
4
2 B2
4
S8C8
C2
2
2
02
3
2 E2
4
2 F2
4 3
B-M-C-8
16
TBA
17
70
M+' ..... A
A-M-C ..... A
3
TAB
2
B-M
1 1 A - S ..... A
1 1 A_B
1 1 B_A
M - 00
4 3
1 A -00
TSTA
40
1
50
1 1 B - 00
And Immediate
TSTB
AIM
71
6
3
61
7
3
MIMM---oM
OR Immediate
DIM
12
6
3 62
7
3
M+IMM-M
EOR Immediate
ElM
75
6 3 65
7
3
M(f)IMM ..... M
Test Immediate
TIM
78
4
3 68 5
3
MIMM
3 2
1 0
I N Z V
B
C
·· ··
····
·· ··
·· ··
·· ··
··
·· ·· ··
··· ··· ·
·· ·· , , , ,
··· ··· , , , ·,
···· , ·
·· ·· ,
I
I Ilt I
I (!)I
I
I
I
I@ I
I
I
I
I
I I
I
----+
3
2
bO
ACCAQAI .~CC~
4 3
82
16
IiIi I f"'9
2 BO
5 3
h-O
_
.,
3
I
•• o--cLLllllD-"'9
111
bO
4
5 2 B3
4
1
2 B7
SBCA
60
I
bT
Mj
3
10
TST
•
lee
"0 17
:Ien
ASRB
2
Subtr.et
6 3
1 1
1 1
3
With Carr ...
77
47
97
Acc:umu Iitors
2
57
STAA
Accumul.tor
6
ASRA
Store
Accumulttor
Subtract
...,7
A1
67
5 4
I
R I
R I 6
R IKi
R I
·
~I
R
I
I
I
I
I
R
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I R
I
•
••
••
••
I
I
I
I
I
I
I
I
I
I
I
R
R
I
R R
R R
R R
:
I
R
!
I
R
I
I
R
I
I
R
•
•
•
•
Note) Condition Code Register will be explained In Note of Table 10
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
65
HD6303R, HD63A03R, HD63B03R
TIM----(M)· (IMM)
Evaluates the AND of the immediate data and the
memory, changes the flag of associated condition code
register
Each instruction has three bytes; the flIst is op-code, the
second is immediate data, the third is address modifier_
XGDX--(ACCD)" (IX)
Exchanges the contents 01 accumulator and the mdex
register.
SLP- - - -The MPU is brought to the sleep mode. For sleep
mode, see the "sleep mode" section.
• New Instructions
In addition to the HD6801 Instruction Set, the HD6303R
has the following new instructions:
AIM----(M)· (IMM) .... (M)
Evaluates the AND of the immediate data and the
memory. places the result in the memory_
OIM----(M) + (IMM) .... (M)
Evaluates the OR of the immediate data and the
memory, places the result in the memory_
EIM-- --(M)(!) (IMM) .... (M)
Evaluates the EOR of the immediate data and the
memory, places the result In the memory.
Table 8
Index Register, Stack Manipulation Instructions
Condition Code
Addressing Modes
POlnlet' Operations
MnemonIC
COmp .... Indu Reg
CPX
Decrement Index Rtrg
OEX
DIRECT
IMMEO
OP
~
8C
3
•
3
OP
9C
~
•
•
2
EXTEND
INDEX
OP
~
AC 5
•2
DP
~
8C
5
•
IMPLIED
OP
09
PES
3.
Inctlment Ind.x Reg
INX
08
Increm.nt Steck Pntr
INS
31
Load Index Reg
LOX
CE
3
3 DE
Lotd Stick Pntr
LOS
8E
3
3 9E
Stor, Indel< Reo
STX
4
OF 4
Store Steck Pntr
STS
9F
TXS
'"deM Rev ... Steck Pnt,
Steck Pnlf ..... Indelil R·~ ~SX
~-----'=
-
•
•
2 EE
~
3
o.crement Steck Pntf
------
Register
Bool.enl
1
ArithmetiC OperattOn
•
-'-f-'-1 1 if+l-X
1 sP+1-5P
S
3
M- X H .IM+lI ..... XL
8E
S
3
M ..... $PH. (M+ll .... SP L
FF
S 3
X H "" M. Xl
8F
5
SPH- M,SPL-IM+1)
- ---- --
A8X
3
1 X-I - Sf'
1 SP+l-X
30
1
3A
1 1 8 +x- X
S 1 XL"" M IP . SP - 1 -+ SP
PSHX
3C
Pull O.t.
PUlX
J8
•
1
hch.nge
XGDX
18
2
1 ACCD··IX
In
(M + 11
1
Pusl'! Oet.
Note) Condition Code Register Will be explained
-0
35
--~--.
2 1 0
I N Z V C
I 1 I
X-MM+l
1 X -1 ..... X
S 2 FE
2 AE S 2
2 EF S 2
2 AF S 2
•3
·· ··· , · ·,
·· ·· ·· ·, ····
·· ·· · ·, ···
·· ·· ,, ··
··· ··· ···· ·····
·· ·· ·· ·· ·· ··
· · · · ··
••••••
H
SP-l-SP
1
5
XH .... M .. , SP - 1 .... SP
SP. 1 -. SP, M ...... XH
SP.1 .... SP.M IP -X L
<1.) I
R
(lJ
(lJ
(lJ
R
R
R
Note of Table 10.
~HITACHI
66
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303R, HD63A03R, HD63B03R
Table 9 Jump. Branch Instruction
Addressing Modes
()per.tlons
MnemoniC
RELATIVE
OP
Br.nch Always
DIRECT
BAA _ _ ~. ~ I-~f---
_ B_'"_n_ch_N_'~~_~~'-_---1-,2,-,'+:3,+2
Branch If Carry Ct.r
Bee
24 3 2
Br.nch If Carry Set,---+--...:B:.::C,:.S_-+-2-S
Branch If - Z.ro
BEQ
27
~.
2
-
"
~C~c,----------~.~.~.~.~.~.~
--~~,------+~~~f7~
--
N@V'O
z_+_ I'.-~-"-I-~..:O'--_t:_t:_t:_t:_t:_t:-
C+Z-O
Z-:;(N-@V.-~ 1
-r---
••••••
C+Z·'
1----- -
-
'----+-+c-+--+-H-:--
N@ V•
+-+-+-+----j---JH--t---t----t
-~-.-,---
3 i .---------t-----t--t--t--t--t-- - -- -- --
--SMI----t--2i
Z'O
l.ro
BNE
Br.nch To Subroutene
Jump
BSR
JMP
Jump To Subroutine
JSR
No Opert'lon
NOP
01
,,
Return From Interrupt
RTI
3B
'0 ,
RTS
39
5
WIll! for Intlrrupt·
Sleep
5.32'0
H I N Z V C
-+-+-+-+-+-+___
-- - -- -
-:.-'~-n"-chltl~;;;;o;----;~;- ---2~ -~- ~-
Rlturn From
Subroutlnl
Softwlrl Intlrrupt
Sr.nth Test
IMPLIED
OP -
4-~~-+-4_~N=on~., _______
None
---(;'--;0-- -----~F-~~~I_'__
__
- 1---- - 1-- -
---==----------------+-++--+Br.nch If < Z.ro
al T
20 3
Br.nc:h II Not Equal
.
EXTEND
______.____ _
---=B"""::.n"ch-'-'-:-'fC>
__'Z:.:O:..:'O'---_I----=B..::G..::E_-4-=2-=-CF 3 ~ ~~B"'~::.n"ch~l~f~>-'Z:.:":..:~'----e-~8GT
2E 3 2
- Br.nch If H"h.r
8HI _ _ 22 3 2 1 8r.nchlf Code Address + 3
-,-0
1
1
3
2
3
4
a pera
1
2
5
Jump Address (MSBI
Jump Address (LSBI
Next Op Code
Address of
ncf(M5B)
Address of Operand (LSBI
Operand Data
Next Op Code
Op Code Address + 2
Address of Operand
Op Code Address + 3
2
Op Code Address+2
4
3
Destination Address
Op Code Address + 3
4
-----t---+-"1-t-0~p-'C'Coc-:d"e-A·d:;-dress + 1
STO--Sl'S-- -_.
ASL
Op Code Address + 1
Op Code Address + 2
Jump Address
OpC')de-Addressn-····· --
- .. - _.-,-- -oi'- Code·Address+ 1 -----
5iA-
ADl'fD·-
2
1
1
1
o
o
1
1
1
1
o
1
1
1
1
o
1
i:Yestlnatlon Addre-ss"(MSBI
Destination Address (LSBI
Accumulator Data
Next Op Code
Addressof-aperai'-d(M5BI
Address of Operand (LSBI
Operand Data (MSBI
Operand Data (LSBI
Next Op Code
Destination-Address (MSS)Destination Address (LSBI
Register Data (MSB)
Register Data (LSB)
Next Op Code
Ju"mp--Atid-ress (MSS) -Jump Address (LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
-Address-o'"Operand-(MS-Sf
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
____
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
00
Next Op Code
- Continued -
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
71
HD6303R, HD63A03R, HD63B03R
Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
Instructions
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
LSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
LSR
ROL
NOP
SEC
SEV
TAP
TPA
TSX
I, Cycles
Address Bus
I
#
Data Bus
Op Code Address + 1
Next Op Code
1
2
--PULA
Cycle:
f- - Op
2
-pTn:s--- --
---,-
3
2
3
T
4
-
PULX
4
--.
Restart Address (LSB)
Data from Stack
-Nex-iOp
1
1
2
3
4
3
4
5
2
3
4
5
1
2
3
4
5
1
1
- RTS- ------- --- - --- - - - -- ,-
7
Next Op Code
Restart Address (LSB)
-NiiXt-OpCode-------------
FFFF
Stack POinter
Op Code Address + 1
-Or> Code Address
1
5
1
1
1
-Or; Code A(idress-~"l ----
2
3
4
2
5
CodeA"iidress +1 ---- --
FFFF
Op Code Address + 1
FFFF
Stack POinter + 1
~ I
o
+-, ------
FFFF
Stack POinter + 1
Stack POinter + 2
""Oc=.:p:.cC"'"o-'cdC=-e"'Ac=.:d"'d-re-=ss-+c-7"l
FFFF
Stack POinter
Stack POinter - 1
Op Code Address + 1
Op Code Address+ 1
FFFF
Stack Pointer + 1
Stack Pointer + 2
Return Address
Op Code Address+ 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
1
1
---+-,--1
0
0
1
-Cod-" ---------
Restart Address (LSB)
Accumulator Data
Next Op Code
N-""t- Op-Cod,,- - - - - Restart Address (LSB)
Data from Stack (MSB)
Data from Stack (LSB)
Next Op Co~---Restart Address (LSB)
Index Register (LSB)
Index Register (MSB)
Next Op C"ocd_,e_ _ _ __
Next Op Code
Restart Address (LSB)
Return Address (MSB)
Return Address (LSB)
First Op Code of Return Routine
Ned Op Code
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
Restart Address (LSB)
- Continued -
~HITACHI
72
Hitachi America, ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy_ • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303R, HD63A03R, HD63B03R
Table 12 Cycle·by·Cycie Operation (Continued)
Address Mode &
Instructions
Address Bus
IMPLIED
WAI
9
1
2
3
4
5
6
7
8
9
RTI
10
1
2
3
4
5
6
7
8
9
SWI
12
10
1
2
3
4
5
6
7
8
9
10
11
12
1
2
SLP
1
Op Code Address+ 1
FFFF
Stack Poonter
Stack Poonter - 1
Stack Poonter - 2
Stack Poonter - 3
Stack Poonter-4
Stack Poonter - 5
Stack Poonter-6
Op Code Address+ 1
FFFF
Stack Poonter + 1
Stack Poonter + 2
Stack Poonter + 3
Stack Poonter +4
Stack Poonter + 5
Stack Poonter +6
Stack Poonter + 7
Return Address
Op Code Address + 1
FFFF
Stack Poonter
Stack Poonter - 1
Stack Pointer - 2
Stack Poonter - 3
Stack Pointer - 4
Stack POinter - 5
Stack POinter - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address + 1
FFFF
FFFF
I
4
Sleep
j
3
4
I
FFFF
Op Code Address + 1
Data Bus
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator. A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (LSB)
Conditional Code Register
Accumulator B
Accumulator A
Index Register (MSB)
Index RegISter (LSB)
Return Address (MSB)
Return Address (LSB)
Forst Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routone (MSB)
Address of SWI Routone (LSB)
Forst Op Cpde of SWI Routine
Next Op Code
Restart Address (LSB)
High Impedance· Non MPX Mod
Address Bus ·MPX Mode
.
Restart Address (LSB)
Next Op Code
- Conllnued -
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819· (415) 589-8300
73
HD6303R, HD63A03R, HD63B03R
Table 12 Cycle-by-Cycle Operation (Continued)
Address Mode &
InstructIons
RELATIVE
BCC
BEQ
BGT
BLE
BLT
BNE
BRA
I Cycles IC
I
I yc e
I
#
BCS
BGE
BHI
BLS
BMT
BPL
BRN
3
,_~~~_Y.Y~~_
!
r-- --+1'
5
I
Address Bus
1
2
Op Code Address+ 1
FFFF
3
1Op Code Address +1
J Branch Address
3
4
5
• SleepMode
On execuhOn of SLP mstruction, the MPU IS brought to the
sleep mode. In the sleep mode, the CPU stops Its operation,
but the contents of the registers In the CPU are retained. In this
mode, the peripherals of CPU will remam actIve. So the operations such as transmit and receIve of the SCI data and counter
may keep In operatIon. In thIs mode, the power consumption
is reduced to about 1/6 the value ofa normal operation.
The escape from this mode can be done by interrupt, RES,
STBY. The RES resets the MPU and the SfBY brings it into the
standby mode (This will be mentioned later). When interrupt is
requested to the CPU and accepted, the sleep mode is released,
then the CPU is brought in the operation mode and jumps to
the interrupt routine. When the CPU has masked the interrupt,
after recovering from the sleep mode, the next instruction of
SLP starts to execute. However, 10 such a case that the IImer
interrupt is inhibited on the timer side, the sleep mode cannot
be released due to the absence of the interrupt request to the
CPU.
II
001
Return Address (LSB)
Return Address (MSB)
First Op Code of Subroutine
This sleep mode is available to reduce an average power
consumption in the applications of the HD6303R which may
not be always running .
• Standby Mode
Bringing "STBY "Low", the CPU becomes reset and all
clocks of the HD6303R become inactive. It goes into the
standby mode. This mode remarkably reduces the power consumptions of the HD6303R.
In the standby mode, if the HD6303R is continuously supplied with power, the contents of RAM is retained. The standby
mode should escape by the reset start. The following is the
typical application of this mode.
First, iiIYi routine stacks the CPU's internal information and
the contents of SP in RAM, disables RAME bit of RAM control
register, sets the standby bit, and then goes into the standby
mode. If the standby bit keeps set on reset start, it means that
the power has been kept during stand-by mode and the contents
of RAM is normally guaranteed. The system recovery may be
possible by returning SP and bringing into the condition before
the standby mode has started. The timing relation for each line
in this application is shown in Figure 2 I.
(~
'"'"\
$
'Test;" 1"
'Test;"O"
Stack POlOter
Stack POlOter-l
Branch Address
The HD6303R has two low power consumption modes; sleep
and standby mode.
HD6303R
Branch Offset
Restart Address (LSB)
First Op Code of Branch Routine
Next Op Code
-~--t-~t~O(fe-AdC-d'""re-s-s~+~l--~r--;~::t:~t A-dd-r:~~L~~-----
• LOW POWER CONSUMPTION MODE
NMI
Data Bus
Ir---f
ReS
m,
I
r+-
Jsm~~:
II
I
.
St"kr~I1'efl
, RAM COntrol
reglsterSoet
•
Osclllatorr
U~'llllng
time
~
t"lItH
Figure 21 Standby Mode TImIng
~HITACHI
74
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
HD6303R, HD63A03R, HD63B03R
• ERROR PROCESSING
When the HD6303R fetches an undefIned instruction or
fetches an instruction from unusable memory area, It generates
the highest priority internal interrupt, that may protect from
system upset due to noise or a program error.
• Op-Code Error
Fetching an undefmed op·code, the HD6303R will stack the
CPU register as in the case of a normal interrupt and vector to
the TRAP ($FFEE, $FFEF), that has a second highest pnority
(m is the highest).
• Addr. . Error
When an instruction is fetched from other than a reSident
RAM, or an external memory area, the CPU starts the same
interrupt as op·code error. In the case which the mstruction IS
fetched from external memory area and that area is not usable,
the address error can not be detected.
The address which cause address error are shown in Table
13.
This feature is applicable only to the instruction fetch, not to
normal read/Write of data accessing.
Transitions among the active mode, sleep mode, standby
mode and reset are shown in Figure 22.
Figures 23, 24 show a system configuration.
The system flow chart of HD6303R is shown in Figure 25.
Figure 22
TranSitions among Active Mode, Standby Mode,
Sleep Mode, and Reset
Table 13 Address Error
Address Error
$0000 - $001 F
HD6303R MPU
16
Address Bus
Oa'8 Bus
Figure 23 HD6303R MPU Multiplexed Mode
8
AddrftS BUI
Figure 24 HD6303R MPU Non·Multiplexed Mode
~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819· (415) 589·8300
75
HD6303R, HD63A03R, HD63B03R
A
FF •
PCl
~
MSP
PCH·4 MSP·'
IXl -. MSP·2
IXH
~
MSP·3
ACCA • MSP·4
Acea -. MSP·5
CCR • MSP·6
Figure 25 HD6303R System Flow Chart
~HITACHI
76
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD6303R, HD63A03R, HD63B03R
• PRECAUTION TO THE BOARD DESIGN OF OSCILLA·
TION CIRCUIT
As shown in Fig. 26, there IS a case that the cross talk dis·
turbs the normal oscillation if signal lines are put near the
oscillation CtrCUlt. When design 109 a board, pay attentton to
thiS. Crystal and CL must be put as near the HD6303R as
possible.
~
..-
Avoid signal hnes
In thiS area
~ ~
ro
g, g,
Vi, Vi
"i
CL
,fiH~-;""'()
40
XTAL
rlHH-;.....() EXTAL
meL
HD6303R
HD6303R
(DP·40)
Do not use thiS kind of prtnt board deSign
Figure 26
Precaution to the boad deSign
of oscillation CirCUit
(Top View)
Fig. 27 Example of Oscillation CirCUitS
In
Board DeSign
• PIN CONDITIONS AT SLEEP AND STANDBY STATE
• Sleep State
The conditIons of power supply pms, clock pms, mput pms
and E clock pm are the same as those of operatIOn. Refer to
Table 14 for the other pm conditIOns.
• Standby State
Only power supply pillS and .sTBV are aclIve. As for the
clock pm EXTAL, Its mput IS fixed Internally so the MPU is
not mfluenced by the pm conditIOns. XTAL IS m "I" output.
All the other pms are tn high Impedance.
Table 14 Pm Condition In Sleep State
______
Mode
Pin
-_______..
I
Non Multiplexed Mode
_.--,
~~ction __ __ ____
I/O P o r t _ . _______
Condition
Keep the condition just before sleep
Function
Address Bus (Ao -A 7)
Output "1"
I
Condition
- ' - " - ' - - . - - - - = - f . - - - - - - . - - -..----"----
P2. _ P24
A./PI. A7/P17
--
Multiplexed Mode
-----_.-
4______ .__~~~P_"r.r.... _____._ _
+--__________ ..=:-____
+---
____ __.
A. - At5 I--~~.:.ti()"--_
~d5!!"~ Bu,-(A. _- AI.s.1__
_ _ _ _-+_-'C:c0::,:n.c::dition f---- ,,____ .___ Outpu!.,,_1'_'_
Data Bus (Do -0 7 )
Function
Do/A. D1/A1
High Impedance
Condition
R/W
,,-
-L___~d.'!~:s.~~s_(:_.. "':. Atsl.. ____ _
,.
,
j
RIW Signal
!
Condition
Output "1"
!
.--
-- ----
E:
---
-
----
Address Bus (Ao -A 7 1. E: Data Bus
_~~_L_l~~t~~~i~=E fi'!lh~I~~anc:_':==-
Function
t---- -
I/O Port
Keep the condition just before sleep
~
AS
RIW Signal
Output AS
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300
77
HD6303R, HD63A03R, HD63B03R
Table 15 Pin Condition dUring RESET
J
~-
- Mode I
Non-Multiplexed Mode
Pin
~
i
-~ -------~~ ~-- ----------
r-
Multiplexed Mode
---- ---
~--------------
-.r-=- _=-__----~-.----- f--:'~~:~;:.o" ., --.'"~'"~""'~~---
~
,
Impedance
4------~_________+: __ High
___
-____________--li ____ -__________________________
_
~
.~~'~; A'~"_ ~-=-::::~~;:
-L!
Do/Ao - D,/A,
(Note)
--- ---
--
High Impedance
---r .
E
In the multlp!exed mode, the data bus IS set to "1" output state dUllng E
external memory Followmg 1 and 2 should be done to avoid the conflict,
(11
(2)
,1--
co
"1" and
It
1" O u t , ; ; ; ; - - - - - - 1 Output
,"0"
causes the conflict With the output of
Construct the system that disables the external memory dUring reset
Add 47 kfl pull-down resistance to the AS pin to make AS pm "0" level dUring E = "1"
data bus high Impedance state
ThiS operation makes the
•
RECEIVE MARGIN OF THE SCI
Receive margm of the SCI contamed 10 the HD6303R
shown m Table 17
Note SCI = Serial lOllllllullIcalion Interface
•
DIFFERENCE BETWEEN HD6303 AND HD6303R
The HD6303R is an upgraded version of the HD6303. The
difference between HD6303 and HD6303R is shown in Table
16.
Table 16 Difference between HD6303 and HD6303R
Table 17
Bit distortion
Item
HD6303R
HD6303
1Mode 2:
Operating
Mode
Multiplexed
: Mode
(EqUivalent to Mode 4)
Mode 2' Not defined
IS
HD6303R
Character
tolerance
distortion tolerance
(t-tollto
(T---To) ITo
±375%
+3.75%
-2.5%
----I-"'---~---------
EI
. I The electrical character:ctrl~a istics of 2M Hz versIOn
C/rac er- (B version) are not specIS ICS
Ifled.
Some characteristics
are Improved.
The 2MHz ve"ion IS
guaranteed.
f-----f-i-fas-probiem in-out-putcompare function.
Timer
(Can be avoided by soft·
ware.)
The problem IS solved.
6
4
START
8
STOP
Ideal Waveform
I
B" length /--t o
-1
I - - - - - - - - - - C h a r a c t e r length T o - - - - - - - - - - - i
Real Waveform
T_t-t-j_ _-----J.I
•
APPLICATION NOTE FOR HIGH SPEED SYSTEM
DESIGN USING THE HD6303R
This note describes the solutIOns of the potenllal problem
caused by noise generation In the system uSing the HD6303R.
The CMOS ICs and LSls featured by low power consumption
$
78
and high nOise Illlmulllty are generally considered to be enough
with simply deSigned power source and the GND hne.
But thIS docs not apply to the apphcatlons configured of
high speed system or of high speed parts Such high speed system may have a chance to work mcorrectly because of the nOise
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303R, HD63A03R, HD63B03R
by the tranSIent current generated dUring swltchmg One of
example IS a system 10 whIch the HD6303R directly accesses
hIgh speed memory such as the HM6264, The nOIse generatIOn
owmg to the over current (SometImes It may be several
hundreds rnA for peak level) dUring sWltehmg may cause data
wflte error
ThIs nOIse problem may be observed only at the Expanded
Mode (Mode I, 2,4, 5 and 6) of the HD6303R
I
0
I
\
f
X
A,-A IS
~
\
\
R/W
Do
I. Noise Occurrence
If the HD6303R IS connected to hIgh speed RAM, a write
error may occur As shown 10 FIg 28, the norse IS generated 10
address bus durrng write cycle and data IS written IOta an unexpected address from the HD6303R ThIS phenomenon causes
random faIlures 10 systems whose data bus load capacItance
exceeds the specIfIcatIon value (90 pF max,) and/or the Impedance of the GND hne IS hIgh
I
\
AS
Assummg the HD6303R IS used as CPU In a system
X
A~No,se
----A
<
7
';
Fig, 28 NOISe Occurrence m address bus durmg write cycle
If the data bus Do ~ D, changes from "FF" to "00", extremely large transIent current flows through the GND Ime
Then the nOIse IS genera ted on the LSI's Ys; pms proportlonrng
to the transIent current and to the Impedance [ZgJ of the GND
Ime,
FIg, 30 shows the dependency of the nOIse voltage on the each
parameter.
l~ l~~~
Vn
Fig 29 NOise Source
ThIS nOIse level, Y n - appears on all output pms on the LSI
mdudmg the address bus,
vee
Cd
Z9
N
NOise Voltage
29
GND Impedance
Cd
Data bus load capacitance
N
Number of data bus lines sWitching from H to L
Fig 30 Dependency of the nOise voltage on each parameter
II. NOIse Protection
To aVOId the nOIse on the address bus dUring the system
operatIon mentIOned before, there are two solutIons as follows
The one method IS to ISolate the HD6303R from peripheral
deVIces so that peripherals are not affected by the nOIse The
other IS to reduce nOIse level to the extent of not affecting peripherals usmg analog method,
~HITACHI
Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
79
HD6303R, HD63A03R, HD63B03R
1. Noi,e I,olation
Addresses should be latched at the negatIve edge of the
AS sIgnal or at the posItive edge of the E signal. The 74LS373
IS often used Ifl thIs case.
LS373
D,/A,- D,/A,I--~>---i
G
HD6303R
2. Noise Reduction
As the nOIse level depends on each parameter such Cd. Vee.
Zg, the noise level can be reduced to the allowable level by con·
trolling those analog parameters.
(a) Transient Current ReductIon
(I) Reduce the data bus load capacItance. If large load
capacitance IS expected. a bus buffer should be in·
serted.
(2) Lower the power supply voltage Vee withm specifi·
cation.
(3) Increase a lime constant at transIent state by insert·
109 a reSIStor (100 - 200n) to Data Buses in senes
to keep nOIse level down.
Table 18 shows the relatIOnshIp between a senes
resistor and nOIse level or a resistor and DC/AC
charactensties.
AS
*-__-' ' " Additional
L...._ _ _ _
R
D,~VV-----~------r--------r-----~
Latch
174LS373 for
nOise Isolation 1
HD6303R
----
Table 18.
ReSIStor
Item
No
lOOn
1.6mA
1.6mA
NOISe Voltage Level
------
See Fig. 31
DC Charactemtlcs
IOL
- - _..
f = 1 MHz
f=15MHz
tADL
t ACCM
190 ns
190 n,
210 n'
395 n,
395 ns
375 ns
tADL
160 ns
180 ns
200 ns
tAS L
20 ns
20 ns
o ns
tACCM
270 ns
250 n,
230 ns
f = 2 MHz
FIg 31 shows an example of the dependency of the nOIse
voltage on the load capacitance of the data bus.'
conditions
15
Vee = 5
Ta
29
ov
= 25'C
= 0
N =8
Cd=90~
~
1.0mA
No change
-.
AC
Charac·
tenstlcs
200n
MaXimum allowed )
load capacitance of
• Note
The value of senes resistor should be carefully selected because
It
heavily depends on each parameter of actual application
system
Fig. 32 shows the tYPical wave form of the noi,e.
the H D6303R
speCification
o
>
~10
E pm
"0
>
:Qt".,
~
o
205
ns
50
100
Flg.32
Data bus load capacItance Cd (pFJ
Flg.31
~HITACHI
80
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303R, HD63A03R, HD63B03R
(3) Insert a bypass capacitor between the Vee line and the
GND of the HD6303R. A tantalum capacitor (about
O.Ij.lF) is effective on the reduction.
(b) Reduction of GND line impedance
(I) Widen the GND line width on the PC board.
(2) Place the HD6303R close by power source.
r-~------r-------r------r--~~
Power
Source
~~~----~--------~------~--~~
(Recommended)
power
Source
Fig. 33 Layout of the HD6303R on the PC board
• WARNING CONCERNING POWER START-UP
• WRITE-ONLY REGISTER
RES must be held low for at least 20 ms when the power
starts up. In this case, the internal reset function is not effective
until the oscillation begins at power-on. The RES signal is input
to the LSI in synchronism with the internal clock t/> (shown in
Figure 34.)
Therefore, after power starts up, the LSI conditions such as
its 1/0 ports and operating mode, are unstable. Fix the level of
1/0 ports by means of an external circuit to determine the level
for system operation during the oscillator stabilization time.
When the CPU reads a write-only register, the read data is
always $FF, regardless of the value in the write-only register.
Therefore, be careful of the results of instructions which read a
write-only register and perform an arithmetic or logical operation on its contents, such as AIM, ADD, or ROL, is executed,
because the arithmetic or logical operatIOn is always done with
the data $FF. In particular, don't use the AIM, OIM or ElM
instruction to mampulate the DDR bit of PORT.
Internal reset
RES pin
signal
Figure 34 RES circuit
•
•
NOTICE ON HD6303R
The HD6303R is the same die as the HD630lVl. The on-chip
Mask ROM is disabled by mask option; therefore not all modes of
operation are available on the HD6303R. Please note that wherever
HD6301VI is referenced, the information also applies to the
HD6303R.
NOTICE ON HD6303R1
The HD6303R has been upgraded to HD6303Rl. Refer to the
following figures for differences between the devices. All other
characteristics remain the same.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
81
HD6303R, HD63A03R, HD63B03R
•
DIFFERENCES BETWEEN HD6301V1, HD6303R, HD6303R1, HD63P01M1, AND HD63701VO
Item
HD6301V
HD63701V0
RAM Size: 128·byte
Address: S0080-$OOFF
RAM Size: 192-by1e
Address: $OO4O-$OOFF
$OOOO~~Z~~
$0000 F-<==~~~
RAM
Operation Mode
$0040~~~~
$0080 ....".""7"~"7I
Mode 4: Expandad Multiplexed Mode = Mode 2
HD63701V0 does not have Mode 4
After providing supply valtege, output level is undefinad
(0 or 1) unless the contents of the Output Compare Register
matches with those of the Free Running Counter. The Out·
put Level Register is not inltializad by reset.
The Output Level Register is initialized to 0 by reset.
Timer
...""". ,,
.
,
~
_....
,-----
____ J
0uI~
1njj\J!
III' Eltto
I"0Il2 B112
Figure 20
Programmable Timer Block Diagram
HD6301Vl, HD6303R,
HD63P01Ml
When framing error occurs,
recalve date Is not transfer·
red from the Receive Shill
Register to Receive Data
Register (RDR).
HD6303Rl
Figure 20
Programmable Timer Block Diagram
Receive date is transferred from Receive Shift Register to
RDR even if framing error occurs.
Receive date Is transferred
from Receive Shift Register
to RDR even if framing error
occurs.
SCI
•
82
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD6303R, HD63A03R, HD63B03R
•
DIFFERENCES BETWEEN HD6301Vl, HD6303R, HD6303Rl, HD63P01Ml, AND HD63701VO (Continued)
HD6301V
HD63701V0
The DDR of port IS reset synchronously with E clock 110
state IS undefined from providing power supply till OSCillation
start (max 20ms)
The DDR of port IS reset asynchronously with E clock. CPU
enters Into high Impedance state (Input state) by bringing
RES Low
Reset release and MCU Internal reset IS performed synchronously With E clock
Item
Port Reset
I/O
Port ....
reset
!<
STBY signal IS latched synchronously With E clock
I-!-
-
I;:
0
w
I~ I~ ~ ~ I~ ~ c3
21t~~~-::!;:~~;::::R%S~~'a
p. . .
Pn
11
PIJ 12
PI.. 1
PH'
P,.'
'27 1
p.. '
Pit 1
P"
1
PM
21
p..
p.. 2
PIl 4
p.. 5
'.,
6
'.2 7
p..
p..
37
2
Au
A13
1\ NC
A,.
POI
p.. 31
Atl
~2~~1!;1I~1!~~~~~~~
p.. _'~_ _ _ _ _~Vtt
~
ll;l~ll.l. ~~J.i.i~ ~<
(Top View)
(Top View)
• HD6303XCP, HD63A03XCP, H D63B03XCP
P20 1
p"
p"
o
0,
D.
D.
P231
D.
D.
0,
P,.
p"
p"
P"
NC
NC
Ao
P,o
p"
p"
p"
•
P"
p"
p"
p"
A,
A,
A.
A.
A5
A.
A,
Vss
A.
(Top View)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
87
HD6303X, HD63A03X, HD63B03X
• BLOCK DIAGRAM
vcc---v••
v••
0""
P2o(TIn)
P2dToutl)
~o
... 0
IN""
P22(SClK)
:::0
00
fS:-
N
P23(Rx)
r01111 iI rII II
..J
~
)(
..J
~~ ~~~
~
)(
W
gl~I~""I~
___
""
CPU
'-t--
~:I:
~
£
P24(Tx)
~
A
P2s(Tout2)
P2s(Tout3)
P27(TclK)
~
-
I - - Do
--
-
L-.
'--
Oi
E
~
£:;,
.
CD
:;,
CD
.::
!!to
0
-
---------'!--____
~r'""
'::x=J.,>---I~--
'M
_l\\\\\\\\\\\\\\\\\\\\\\,
_11I14....'r-<-------~,:=:x=r~r
'"
_ll$»~\\\\\I\\'1\\~II\\\II!\\\lI'r-l'_vv_vt:JD_;~r-1- - - -
w,
_:\\\\\\\\\\~\\\\~\"\\f
!~~;;"I- - - - -
~::·.»\Il~mll\\ll\\\\\\1lmlll-mmlil.m.-----~(}-{}-{Y,
. . .>---1';..'- - - - ,»:
PCB
PCO- Firs!
PC7
PC15
Instruction
Figure 11 Reset Timing
•
FUNCTIONAL PIN DESCRIPTION
•
Vee, Vss
Vee and Vss provide power to the MPU With 5V± 10% supply. In the case of low speed operation (fmax = 500kHz), the
MPU can operate WIth three through SIX volts. Two Vss pms
should be tied to ground.
•
XTAL, EXTAL
These two pms mterface WIth an AT-cut parallel resonant
crystal Dlvlde-by-four clfcuit IS on ChIP, so If 4MHz crystal
OSCIllator IS used, the system clock IS I MHz for example.
AT Cut Parallel Resonant Crystal OSCillator
Co= 7pF max
Rs=60Q max
e l 1 =CL2
o
EXTALr--_-,
• STBY
ThIs pin makes the MPU standby mode. In "Low" level, the
OSCIllatIOn stops and the mternal clock IS stabilized to make
reset condition To retam the contents of RAM at standby
mode, "0" should be wntten mto RAM enable b,t (RAME).
RAME IS the b,t 6 of the RAM/port 5 control regISter at $0014.
RAM IS dISabled by this operatIOn and Its contents IS sustamed
Refer to "LOW POWER DISSIPATION MODE" for the
standby mode.
•
XTALr---~-----'
CJ
and EXTAL pillS. Any llIle must not cross the Ime between the
crystal OSCillator and XT AL. EXT AL.
,
OpF - 22pF . 20',
(32 - 8MHz)
-1CL21-CLI
Figure 12 Crystal Interface
EXTAL pin can be dnved by the external clock of 45 to
55% duty, and one fourth frequency of the external clock
is produced in the LSI. The external clock frequency should
be less than four times of the maximum operable frequency
When using the external clock, XT AL pm should be open
Fig. 12 shuws an example of the crystal interface The crystal
and CLl , CL2 should be mounted as close as pOSSIble to XT AL
Reset (RES)
This pm resets the MPU from power OFF state and pro·
vldes a startup procedure Dunng power-on, RES pm must
be held "Low" level for at least 20ms.
The CPU regISters (accumulator, mdex register, stack pointer,
cond,t,on code register except for interrupt mask bit), RAM
and the data regISter of a port are not inittalized during reset,
so their contents are unknown in this procedure.
To reset the MPU dUflng operation, RES should be held
"Low" for at least 3 system-clock cycles. At the 3rd cycle
durmg "Low" level, all the address buses become "High". When
RES remamS "Low", the address buses keep "High". If RES
becomes "HIgh", the MPU starts the next operation.
(l) Latch the value of the mode program pms; MPo and MP , .
(2) Inillalize each mternal register (Refer to Table 3)
(3) Set the mterrupt mask b,t. For the CPU to recognize the
maskable IOterrupts IRQ" IRQ, and IRQ3, thIS bit should
be cleared 10 advance.
(4) Put the contents (= start address) of the last two addresses
($FFFE, $FFFF) into the program counter and start the
program from thIS address (Refer to Table I).
*The MPU IS usable to accept a reset IOpUt until the clock
OHITACHI
Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
95
HD6303X, HD63A03X, HD63B03X
becomes nonnal oscillation after power on (max. 20ms). During
this transient time, the MPU and I/O pins are undefined. Please
be aware of this for system designing.
•
Enable (E)
This pin provides a TTL·compatible system clock to external
circuits. Its frequency IS one fourth that of the crystal oscillator
or external clock. This pin can drive one TTL load and 90pF
capacitance.
•
Non·Maskable Interrupt (NMI)
When the falling edge of the mput Signal IS detected at thiS
pin, the CPU begins non·maskable interrupt sequence mtemally.
As well as the IRQ menlloned below, the instruction being
executed at NMI signal detection will proceed to its completion.
The interrupt mask bit of the condition code register doesn't
affect non·maskable interrupt at all.
When starting the acknowledge to the !llM1, the contents of
the program counter, index register, accumulators and conditIOn
code register will be saved onto the stack. Upon completion
of this sequence, a vector IS fetched from $FFFC and $FFFD
to transfer their contents mto the program counter and branch
to the non·maskable mterrupt semce routme
(Note) After reset start, the stack pomter should be illitialized
on an appropreate memory area and then the fallmg edge
should be mput to NMI pm.
Interrupt Reque,t (IRO I • IRO-;)
These are level-sensItive pillS which request an mternal
mterrupt sequence to the CPU. At mterrupt request, the CPU
will complete the current mstruchon before its request acknowl·
edgement. Unless the mterrupt mask in the condition code
register is set, the CPU starts an mterrupt sequence; If set, the
interrupt request will be Ignored. When the sequence starts, the
contents of the program counter, index register, accumulators
and condition code register will be saved onto the stack, then
the CPU sets the lIlterrupt mask bit and will not acknowledge
the maskable request. Durmg the last cycle, the CPU fetches
vectors depicted in Table I and transfers theu contents to the
program counter and branches to the service routine.
The CPU uses the external mterrupt pms, IRQI and
also as port pms P 50 and PSI, so it provides an enable bit to
Bit 0 and I of the RAM port 5 control register at $0014 Refer
to "RAM/PORT 5 CONTROL REGISTER" for the detaus.
When one of the mternal mterrupts, ICI, OCI, TOl, CMI or
SIO is generated. the CPU produces mternal mterrupt Signal
(IRQ,) IRQ, functions just the same as IRQ; or fRQ, except
for its vector address. Fig 13 shows the block diagram of the
mterrupt CirCUit.
•
fRO; ,
Table 1 Interrupt Vector Memory Map
Priority
Highest
-
Vector
MSB
------------
FFFE
FFFF
FFEE
FFFC
FFEF
RES
TRAP
FFFD
NMI
FFFA
FFFB
FFF9
SWI (Software Interrupt)
IRQ I
FFF7
FFF5
FFF3
ICI
FFFB
FFF6
FFF4
FFF2
FFEC
FFEA
Lowest
Interrupt
LSB--
FFFO
FFED
FFEB
FFFI
._---.-
------------
(Timer 1 Input Capture)
OCI (Timer 1 Output Compare 1. 2)
TOI (Timer 1 Overflow)
CMI (Timer 2 Counter Match)
---------.
IRQ,
-----------------~-
SID (RDRF+ORFE+TDRE)
~HITACHI
96
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303X, HD63A03X, HD63B03X
Each RegIster s Intetrupt
Enable Flag
'" ", Enable, "0', DIsable
--0--1>-4----1
Cond,,,"n
Code
RegIster
fRCh
>-+----1
ICF
-+-o--O-+-~~-I''O' ,Enable
lei
I·MASK
"1",Dlsabl
OCEI
OCF2
Interrupt
Request
Signal
TOF
eMF
ADRF
OAFE
TORE ----.--
----------~.~~~
Sleep
Cancel
SIgnal
SWI
Figure 13 Interrupt CirCUit Block Diagram
Mode Program (MP". MP , )
10 Opcldte MPl:. MP o rill should he c,,"neeled to "High"
level and MP I sh()uld he l'()lmected to ··Lo-.\ level (Iefel to
•
I Ig I')
•
Read/Wrrte (R/W)
ThIS "gnal, usually be In read state ("H,gh"), shows whether
the CPU IS l!I read ("HIgh") or wrIte ("Low") state to the
perrpheral or memory devrces ThIS can drive one TTL load
and 301'1' capaCltallee
• RD.WFi
These SIgnab show active low outputs when the CPU "
readrng!wrrtrng to the penpherals or memones ThIS enables
the CPU easy to access the penpheral LSI WIth Ri:5 and WR
rnput 1"'" These pillS can dr've one TTL load and 30pF capaC!·
tance
•
Load InstructJon RegISter (LTR)
rhos Signal shows the mstructlOn ope code bemg on data
bus (active Jow) ThIS pm can dnve aIle TTl load and 30pF
capaCitance
Memory Ready (MR, P,,)
ThlS IS the lllput control Signal whIch stretches the system
clock's "H,gh" penod to access low· speed memones. Durmg
thiS signal IS m "HIgh", the system clock operates In normal
sequence But thIS Signal In "Low", the "lhgh" period of the
system clock Will be stretched dependmg on Its "Low" level
duratIon rn II1tegral mUltIples of the cycle tnIle TIllS allows the
CPL' to lIltl'tlalc With !o\\-speed lllcmorH:'..., (see rIg 2) Up to
'i iJS can be stretched
DUlmg lOternal addre~~ ,;pace acce~s t'f IH'llvalld memo!)
access, MR IS prohibited Internally to prevent decrease of operatIon speed Even In the halt state, MR can also stretch "HIgh"
penod of system clock to allow peripheral deVIces to access
low-speed memones. As thIS SIgnal is used also as P", an enable
b,t IS prOVIded at bIt 2 of the RAM/port 5 control register at
$0014. Refer to "RAM/PORT 5 CONTROL REGISTER" for
more details
•
Halt (HALf; P S3 )
ThIS IS an tnput control slgnal to stop lflstructton execution
and to release buses When thiS SIgnal SWItches to "Low", the
CPU stops to enter mto the halt state after having executed
the present InstructIOn When entermg mto the halt state, it
makes BA (P 74) "HIgh" and also an address bus, data bus, RD,
WR, R/W hIgh Impedance When an mterrupt IS generated
In the halt state, the CPU uses the Interrupt handler after the
halt IS cancelled
(Note) I Please don't SWItch the HALT SIgnal to "Low" when
the CPU executes the WAI InstructIOn and IS in the
lllterrupt watt state to aVOId the trouble of the CPU's
operatlOl1 aftel the halt IS callcelled.
2 When power IS supp\red WIth the condition that
HALT IS "low", MCU cannot sometImes release the
reset cond,tion. even If RESET becomes "HIgh".
HALT should be low before RESET nses up.
•
•
Bus Available (BA)
ThIS IS an output control SIgnal which is normally "Low"
but "HIgh" when the CPU accepts HALT and releases the buses.
fhe HD6800 and HD6802 make BA "HIgh" and release the
buses at WAI executIOn, whIle the HD6303X doesn't make
BA "H,gh" under the same conditIOn. But if the HALT becomes
~HITACHI
Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
97
HD6303X, HD63A03X, HD63B03X
"Low" when the CPU is in the interrupt wait state after having
executed the WAI, the CPU makes SA "High" and releases the
buses. And when the HALT becomes "High", the CPU returns
to the interrupt wait state.
• PORT
The HD6303X provides three I/O ports. Table 2 gives the
address of ports and the data direction reglster and Fig. 14
the block diagrams of each port.
bit 0 decides the I/O direction of P,o and bit I the I/O direction OfP'1 to P ("0" fOI input, "I" for output).
'7
Port 2 is also used as an I/O pin for the timers and the
SCI. When used as an I/O pin for the timers and the SCI, port
2 except P,o automatically becomes an input or an output
depending on their functions regardless of the data direction
register's value.
Port 2 Data Direction Register
Table 2 Port and Data Direction Register Address
Port
Port 2
Port 5
Port 6
I
Port Address
$0003
$0015
$0017
4
Data Direction Register
$0001
$0016
• Port 2
An 8-bit input/output port. The data direction register
(DDR) of port 2 controls the I/O state. It provides two bits;
A reset clears the DDR of port 2 and configures port 2 as an
input port. This port can drive one TTL and 30pF capacitance. In addition, it can produce I rnA current when V out =
1.5V to drive directly the base of Darlington transistors.
Port Write Signal
Data Bus
Timer 1.2.;--+_ _ _-..1
SCI Output
Port Read Signal
....L.
Port 2
Port Read Signal
...L
Data Bus _ _ _..r--"_.E
Figure 14 Port Block Diagram
• RAM/PORT 5 CONTROL REGISTER
The control register located at $0014 controls on-chip
RAM and port 5.
• Port 5
An S-bit port for input only. The lower four bits are also
usable as input pins for interrupt, MR and HALT.
RAM/Port 5 Control Register
• Port 6
An S-bit I/O port. This port provides an 8-bit DDR corresponding to each bit and can specify input or output by the
bit ("0" for input, "I" for output). This port can drive one
TTL load and 30pF capacitance. A reset clears the DDR of port
6. In addition, it can produce ImA current when V OUI = 1.5V
to drive directly the base of Darlington transistors.
4
1
0
• BUS
• 0 0 -0 7
These pms are data bus and can dllve one TTL load and
90pF capacitance respectively.
Bit 0, Bit 1 IROI,IRO, Enable Bit (/ROIE,IRO,E)
When using Pso and P 51 as interrupt pins, write "I" in
these bits. When "0", the CPU doesn't accept an external
interrupt or a sleep canceDation by the external mterrupt.
These bits become "0" during reset.
• Ao-A"
These pins are address bus and can drive one TTL load and
90pF capacitance respectively.
Bit 2 Memory Ready Enable Bit (MRE)
When ulling P 52 as an input for Memory Ready Signal, write
"I" in this bit. When "0". the memory ready function is pro-
•
98
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303X, HD63A03X, HD63B03X
hibited and P" can be used as I/O port This bit becomes
"I" during reset.
llIode and the oll·ch,p RAM data" valid
Bit 3 Hatt Enable bit (HLTE)
When u"ng P" a, an mput fOI Halt Signal, wnte "I" m tillS
bit. When "0", the halt function IS prohibited and PS3 can be
used as I/O port. ThiS bit becomes "I" dunng reset.
(Note) When using PS2 and PS3 as the Input ports In mode I
and 2, MRE and HLTE bit should be cleared just after
the reset.
Notice that memory ready and halt functIOn IS enable
till MRE and HLTE bit is cleared
[··------l
-
MPo
~
----E
-"- Rll
...r::::--'
--WR
=
L....
RES
STBYNMI-
Bit 4, Bit 5 Not Used.
PortLines
2
81/0
<::
-R/N
- ' - ClR
HD6303X
-----BA
MPU
Timer 1 2
SCI
Bit 6 RAM Enable (RAME)
On-chip RAM can be disabled by thiS control bit By reo
setting the MPU, "I" is set to this bit, and on-chlp RAM is
enabled. This bit can be written "I" or "0" by software. When
RAM is in disable condition (= logiC "0"), on-chip RAM IS
invalid and the CPU can read data from external memory.
This bit should be "0" before getting mto the standby mode to
protect on-chip RAM data.
8 Data Bus
Port 5
8~~ ~-wn;L16 Address
MR fiA[i
Port 6
8 I/O lines
Bus
Figure 15 Operation Mode
Bit 7 Standby Power Bit (STBY PWR)
When Vee is not provided m standby mode, this bit IS
cleared. This is a flag for both read/write by software. If this bit
is set before standby mode, and remains set even after returning
from standby mode, Vee voltage is provided during standby
• MEMORY MAP
The MPU can address up to 65k bytes Fig 16 gives memory
map of HD6303X. 32 IIIternalleglSters usc addresses frolll "00"
as shown III Tablc 3
Table 3 Internal Register
Address
Registers
00
-
01
0203
0405
060708
09
OA
OB
OC
00
OE
OF
10
11
12
Port 2 Data Direction Register
R/W* * *
-
Initialize at RESET
W
$FC
RIW
Undefmed
-
-
Port 2
-
-
-
-
-
-
-
-
-
Timer Control/Status Register 1
Free Running Counter ("High")
Free Running Counter ("Low")
Output Compare Register 1 ("High")
Output Compare Register 1 ("Low")
Input Capture Register ("High")
Input Capture Register ("Low")
Timer Control/Status Register 2
Rate, Mode Control Register
Tx/Rx Control Status Register
RIW
R/W
RIW
RIW
RIW
$00
$00
R
R
$00
$00
$FF
$FF
RIW
R/W
$00
$10
$00
RIW
R
$20
$00
13
Receive Data Register
Transmit Data Register
14
RAM/Port 5 Control Register
W
RIW
15
16
Port 5
Port 6 Data Direction Register
R
W
$00
$7C or $FC
-
$00
(contlllued)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
99
HD6303X, HD63A03X, HD63B03X
Table 3 Internal Register
Registers
Address
17
Port 6
RIW***
Initialize at RESET
RIW
Undefoned
-
18"
-
-
19
Output Compare Register 2 ("High")
RIW
$FF
lA
Output Compare Register 2 ("Low")
RIW
$FF
18
Timer ControllStatus Register 3
RIW
$20
lC
Time Constant Register
W
$FF
lD
lE
IF··
Timer 2 Up Counter
RIW
$00
-
Test Register
-
• External Address
•• Test Register Do not access to this register .
... R
W
: Read Only Register
: Write Only Register
R/W: Read/Write Regllter
and incremented by system clock. The counter value is readable
by software without affecting the counter. The counter is
cleared by reset.
When wnting to the upper byte ($09 J, the CPU writes the
preset value ($1'1'1'8) into the counter (address $09, $OA)
regardless of the write data value. But when wnting to the
lower byte ($OA) after the upper byte writing, the CPU writes
not only the lower byte data into lower 8 bit, but also the
upper byte data into higher 8 bit of the FRC.
The counter will be as follows when the CPU writes to it
by double store Instructions (STD, STX etc.).
HD6303X
Expanded Mode
Interna'Registers
External
Memory
Space
Internal
RAM
$09 Wnte
$OAWnte
External
Memory
Space
$FFF8
$5AF3
In the case of the CPU write (S5AF3) to the FRC
Figure 17 Counter Wnte Timing
$FFFF '--_ _--'
• Excludes the foll.:>wlng addresses
which may be used externally:
$02. $04. $06. $07. $1 B
Figure 16 HD6303X Memory Map
• TIMER 1
The HD6303X provides a 16-bit programmable timer which
can simultaneously measure an mput waveform and generate
two independent output waveforms. The pulse widths of both
input/output waveforms vary from microseconds to seconds.
Timer I is configurated as follows (refer to Fig. 18)
Control/Status Register I (8 bit)
Control/Status RegISter 2 (7 bit)
Free Running Counter (16 bit)
Output Compare Register I (16 bit)
Output Compare Register 2 (16 bit)
Input Capture Register (16 bit)
• Output Compare Register (OCR)
($0008. $OOOC; OCR1) ($0019, $OOlA ;OCR2)
The output compare register is a 16-bit read/write register
which can control an output waveform. The data of OCR is
always compared with the FRC.
When the data matches, output compare flag (OCF) in the
timer control/status register (TCSR) IS set. If an output enable
bit (OE) in the TCSR2 is "1", an output level bit (OLVL) in
the TCSR will be output to bit I (Tout I) and bit 5 (Tout 2)
of port 2. To control the output level again by the next compare, the value of OCR and OLVL should be changed. The
OCR IS set to $FFFF at reset. The compare function is inhibited
for a cycle just after a write to the OCR or to the upper byte
of the FRC. ThiS is to begm the comparison after seUmg the
16-bit value valid m the register and to inhibit the compare
function at this cycle, because the CPU wntes the upper byte
to the FRC, and at the next cycle the counter is set to SFFF8.
• For data write to the FRC or the OCR. 2·byte transfer
mstrucllon (such as STX etc) should he used.
•
•
FrH-Running Counter (FRC) ($0009 : OOOA)
The key timer element is a 16-bit free-running counter driven
•
100
Input Capture Register (lCR) ($OOOD : OOOE)
The input capture register IS a 16-blt read only register which
stores the FRC's value when external mput Signal transition
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303X, HD63A03X, HD63B03X
generates an input capture pulse. Such transitIOn is controlled
by mput edge bit (IEDG) m the TCSRI.
In order to input the external mput Signal to the edge
detecter, a bit of the DDR corresponding to bit 0 of port 2
should be cleared ("0"). When an mput capture pulse occurs
by the external mput Signal transition at the next cycle of CPU's
high-byte read of the ICR, the mput capture pulse wlll be delayed by one cycle. In order to ensure the input capture operatIOn, a CPU read of the ICR needs 2-byte transfer mstructlOn.
The mput pulse width should be at least 2 system cycles. ThiS
register is cleared ($0000) dunng reset
•
Timer Control/Status Register 1 (TCSR1) ($0008)
The timer control/status register I is an 8-bit register. All bits
are readable and the lower 5 bits are also writable. The upper 3
bits are read only which indicate the followmg timer status.
Bit 5 The counter value reached to $0000 as a result of
counting-up (TOF)
Bit 6 A match has occured between the FRC and the OCR I
(OCFI)
Bit 7 Defined transItion of the !lmer mput signal causes the
counter to transfer ItS data to the ICR (ICF).
The followings are each bIt descnphons.
Bit 7
to the OCRI ($OOOB or $OOOC) after the TCSRI or
TCSR2 read.
ICF
Input Capture Flag
This read-only bit is set when an input signal of
port 2, bit 0 makes a transition as defined by IEDG and
the FRC IS transferred to the ICR. Cleared when reading
the upper byte ($0000) of the ICR followmg the
TCSRI or TCSR2 read.
•
Timer Control/Status Register 2 (TCSR2) ($OOOF)
The timer control/status register 2 is a 7 -bit register. All bits
are readable and the lower 4 bits are also writable. But the
upper 3 bits are readI.IIC."yIF,om8"ll
Figure 23 CPU Programming Model
• CPU Addressing Mode
TIle HD6303X provldcs 7 addreSSing modes TI1C addreSSing
mode is deCided by an instructiOn type and code Tablc 10
through 14 show addressing modes of each instruction With
the executIOn times counted by the machine cycle.
When the clock frequency IS 4 MHz, the machll1e cycle time
~HITACHI
110
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy_ • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303X, HD63A03X, HD63B03X
becomes microseconds directly.
Accumulator (ACCX) Addressing
Only an accumulator IS addressed and the accumulator A or
B is selected. This is a one-byte instrucllon.
Immediate Addressing
This addre ..mg locates a data m the second byte of an
lt1>tluctllln However, LDS and LDX locate a data It1 the second
and tlurd byte exceptIOnally Th,s addressmg IS a ~ or 3-byte
It1structlon
Direct AddressIng
In this addressing mode, the second byte of an instructton shows the address where a data IS stored 256 bytes (SO
through $255) can be addressed directly. Execution tnnes
can be reduced by storing data in this area so it is recommended
to make it RAM for users' data area in configurating a system.
This is a 2-byte instruction, while 3-byte with regard to AIM,
OIM, ElM and TIM.
Extended AddreSSing
In this mode, the second byte shows the upper 8 bit of the
data stored address and the third byte the lower 8 bIt This
indicates the absolute address of 3-byte instruction in the
memory,
Indexed Addressi n9
The second byte of an instruction and the lower 8 bit of the
index register are added in this mode. As for AIM, OIM, ElM
and TIM, the third byte of an instruction and the lower 8 bits
of the index register are added_
This carry is added to the upper 8 bit of the index register
and the result is used for addreSSing the memory. The modified
address is retained in the temporary address register, so the contents of the index register doesn't change. This is a 2-byte
instruction except AIM, DIM, ElM and TIM (3-byte instruction).
Imphed Addressing
An instruction itself specifies the address. That is, the
instruction addresses a stack pointer, index register etc. This is a
one-byte instruction,
Relative Addressing
The second byte of an instruction and the lower 8 bits of
the program counter are added. The carry or borrow is added to
the upper 8 bit. So addressing from -126 to +129 byte of the
current instruction is enabled. This is a 2·byte instruction.
(Note) eLI, SEI Instructions and Interrupt Operation
When accepting the IRQ at a preset timing with eLI
and SEI instructions, more than 2 cycles are neces·
sary between the eLI and SEI instructions. For example,
the following program (a) (b) don't accept the IRQ but
(c) accepts it.
eLI
eLI
eLI
SEI
NOP
SEI
NOP
NOP
SEI
(a)
(b)
(c)
The same thing can be said to the TAP instruction
instead of the eLI and SEI instrUctions.
_HITACHI
Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
111
HD6303X, HD63A03X, HD63B03X
Table 10 Accumulator, Memorv Manipulation Instructions
Conc:htlon Code
Addressing Mode.
Operltlons
MnemoniC
IMMEO
OP -
Add
ADDA
ADD8
ADDD
ABA
Add With Carry
ADCA
89
ADC8
AND
ANDA
ANOS
C9
80
Compare
Compar.
Accumulators
Compl.",.."t. ,',
Compl.",."t, 2's
INepte,
DeCimal Ad,UI1. A
Decr.",."t
DP
-
oP -
#
C4
SITA
85
BIT B
C5
2 2 99
2 2 D9
2 2 90
2 2 D4
2 2 95
2 2 05
3
#
3
3
A+M+C-A
2 E9
AO
4
2 F9
4
3
4
2
4
3
B+M+c-a
A·M-A
2
2
E4
2
4
3
8·M- 8
3 2
A5
4
2
85
4
3
A·M
2 E5
4
2
F5
0
3
8'M
5
2
7F
5 3
3
CLR
6F
4
CLRA
OF
I
I
00 - A
CLR8
5F
1
I
eMPA
81
2 2 91
3 2
eMPS
Cl
2 2 01
3
AI
4
2 81
2 El
4
2 Fl
63
6
2 73
•
3
00 - 8
A-M
0
3
8-M
6
3
II
C8A
COM
43
53
1
1
NEG
60
6
2
70
6
I
A -A
I
B -8
oo-M-M
3
NEGA
NEG8
40
1 I
oo-A-A
50
1 I
oo-8-B
DAA
19
2 1 chlrleters Into BCD format
DEC
SA
6
2
7A
6
Converts bU\IIry add of BCD
M-l-M
3
DECA
OA
1
1 A -1 ..... A
DEC8
5A
1
1 8-1-B
EORS
C8
2 .2_ 08
3
2
Increment
INC
A8
4
2 B8
E8
4
2
6C
6
2 7C
F8
A(!lM-A
4 3
4 3
6
8 (!lM- B
, M+l-M
3
INCA
OC
INCB
5C
1
1<1
A+ l - A
86
2 2
A6
4
2 86
4
3
M-A
LOAS
C6
2
2 06 3 2 E6
4
2
F6
4 3
M-8
LOD
CC
3
3
EC
5
2
FC
5
M + 1- 8,M-A
3
DC 4
2
2
3
3D
Multlplv Unsigned
MUL
OR.lnclus",.
ORAA
8A
2
2 9A
3
2
AA •
2
SA 4
3
ORA8
CA
2
2 DA 3
2
EA 4
2
FA 0
3
7 1 A
II;
B ..... A
+- A+M-A
B +M ..... B
36
4
PSHB
37
4
1 A -- MIP, SP - 1 -- SP
I B ... Map. SP - 1 ... SP
PULA
32
3
1 SP .. 1- SP.MIP- A
33
3 1 SP .. 1'" SP. Map - B
'9
1
59
1 1
ROL
69
6
2
79
6
3
AOLA
RDL8
RDR
66
6
2
76
6
, :jl4[J4i r r r r r r n
I
R
• (7) 1 R
.(7)1 R
.(l)1 R
(Note) Condition Code Register Will be explalOed 10 Note of Table 13
.HITACHI
114
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303X, HD63A03X, HD63B03X
Table 12 Jump, Branch Instructions
Condition Code
Addressing Modes
Operations
MnemoniC
Branch Test
_.--~~~s~e:_.--543210
H
Branch Always
Branch Never
Branch If Carry Clear
Branch If Carry Set
Branch If " Zero
Branch If II< Zero
----------
BRA
BRN
Bee
BCS
BEQ
BGE
20
21
I
3
3
I
2'
2 '
, None
_~hwarelnterruo~ __ -.~S~W.~I----~--+-~~-4--~~~~I~~~~~33~FE~'9,2~,'_~
Walt for Interrupt·
eep
INote)
·.....
•
S ••
• ® ••
WAI
1A
SLP
4
1
'" WAI puts R/W high, Address Bus goes to FFFF, Data Bus goes to the three state
ConditIOn Code Register
I N Z V C
None
WIt!
be explained ,n Note of Table 13
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
115
HD6303X, HD63A03X, HD63B03X
Table 13 Cond,t,on Code Register Manipulation InstructIons
~ddresslngMod8!
OperatIOns
IMPLIED
MnemonIC
Condition Code Register
Boolean Operation
op
H
LEGEND
OP
H
I
Number of Program Bytes
Anthmetlc Plus
Anthmetlc Mmus
+
if>
M
32-~
0-
N
C
Z
V
CONDITION CODE SYMBOLS
Operation Code (Hexadecimal)
Number of MCU Cycles
MSp Contents of memory location pOinted to by Stack POinter
#
r--s,...---
Boolean AND
Boolean InclUSive OR
N
Z
Zero Ibvte)
V
Overflow, 2's complement
C
R
S
Carry/Borrow framlto bit 7
Reset Always
Set Always
Set ,f true after test or clear
Not Affected
t
Boolean ExclUSive OR
Complement of M
Transfer Into
Half
W
o
w
PC'
PC'
C"J
=.
?:
VECTORING
FFFE FFFF
l>
::r:
3
'":::l.
t:I
C"J
P'
0>
W
g
~
•
::r:
(Note)
1
S
C"J
=.
"lJ
p;;
2
N
Il)
•
~
0
0
0
"lJ
::r:
t:I
0')
w
o
~
(")
::;:
'"
""C::J• :I
:::l.
en
0-
Il)
:::>
.'"
C")
l>
CD
-l>0
~
~
CD
•
~
~
~
'P
co
w
g
w
?:
w
:><:
@
:I
"lJ
;a
Refe' to "FUNCTIONAL PIN DESCRIPTION" fo, mo,e
details of Interrupts
o
b:l
~~
Q.
The program sequence will come to the RES start from
any place of the flow dunng RES. When STBY=O. the
sequence will go Into the standby mode regardless of the CPU
condition.
Figure 25 HD6303X System Flow Chart
HD6303X, HD63A03X, HD63B03X
Table 16 Cycle-by-Cycle Operation
Address Mode &
,
IMMEDIATE
Aoe
AND
eMP
LOA
SBC
-ilOOD
LDD
LOX
DIRECT
ADe
AND
CMP
LOA
SBC
STA
ADO
BIT
EOR
ORA
SUB
CPX
LOS
SUBD
2
3
2
3
1
3
3
- AOI5D-CP5(
LDD
LOS
LOX
SUBD
--~
2
3
-,--2
3
-~
1
4
-STD-----sfS-----
..
- --4
--JSR-
2
3
4
1
---
2
3
4
- - - ---15
2
3
4
TIM
------- ----- -----4
-AIM--- ElM
OIM
I
!
1
--,
5
2
3
2
3
I
Op Code Address + 3
Op Code Address + 1
Address of Operand
Op Code Address + 2
,
0
0
I,
1
1
1
1
0
1
Operand Data
Next Op Code
I
I
I
Op Code Address + 1
Op Code Address + 2
0
0
0
I
1
1
1
I
i
I
1 -. -OperandDaii(MSB)---Operand Data (LSB)
1
Next Op Code
0
1
1
1
0
0
0
1
1
1
1
1
0
1
0
0
1
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
Address of Operand (LSB)
Oper a nd Da ta
Next Op Code
I
i
--01:> C-odeAddress + 1
Destination Address
I
Op Code Address + 2
QPCOdeAddress +-f- -
-r-t
Address of Operand
Address of Operand + 1
Op Code Address+ 2
--0" Code Address + 1
DestlOatlon Address
Destination Address + 1
Op Code Address + 2 ._-··-Op Co-deAddress:tl
1
1
0
0
,
Jump Address
Address of Operand
Op Code Address + 2
-
FFFF
5
6
Address of Oper and
Op Code Address+ 3
--,- -,-
1
1
1
1
0
0
1
-,-- ro--- -,-
-----
--j
Address of Operand
4
0
0
1
1
0
0
1
Stack POinter
Stack POinter - 1
Op Code Address + 1 Op Code Address + 2
I
--
~-
FFFF
4
Op Code Address + 3
- - - -;- b'p-CodeAddres"s--+-'
6
,
i
,
-
--~
- -
Op Code Address + 1
Op Code Address + 2
2
ADO
BIT
EOR
ORA
SUB
STX
Data Bus
Address Bus
Instructions
I
1
1
1
-,
0
0
0
0
-- 0--
1
1
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
0
-1
1
1
0
1
1
1
1
1
0
Destination -Address
--
.--.
Accumulator Data
Next Op Code
"-Acfdr"eSs ofOperancf"[SB)Operand Data (MSB)
Operand Data (lSB)
Next Op Code
Destination Address "(LseT"Register Data (MSB)
Register Data (lSB)
_____
~~~~E_~_~~
-jump Address (LSBI
Restart Address (LSB)
Return Address (lSB)
Return Address (MSB)
First Subroutme Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Next Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
Restart Address (lSBl
New Operand Data
Next Op Code
(Continued)
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
119
HD6303X, HD63A03X, HD63B03X
Address Mode &.
InstructIons
Address Bus
Data Bus
INDEXED
1
JMP
3
ADC
AND
CMP
LOA
SSC
TST
STA
ADD
SIT
EOR
ORA
SUS
2
3
1
4
2
3
4
1
4
2
3
4
ADDD
CPX
LOS
SUSD
1
LDD
LOX
5
2
3
4
5
STD
STX
STS
1
2
5
3
4
5
JSR
1
2
5
3
4
5
ASL
COM
INC
NEG
RDR
ASR
DEC
LSR
ROL
1
2
6
3
4
5
6
TIM
1
5
2
3
4
5
CLR
1
5
2
3
4
5
AIM
OIM
ElM
1
2
3
7
4
5
6
7
Op Code Address + 1
FFFF
Jump Address
1
1
1
1
0
1
1
1
0
1
0
0
1
1
1
1
1
1
0
1
1
0
Op Code Address + 1
FFFF
IX + Offset
Op Code Address+2
1
1
Op Code Address + 1
FFFF
IX + Offset
Op Code Address+ 2
Op Code Address + 1
FFFF
IX + Offset
IX+Offset+ 1
Op Code Address + 2
Op Code Address+ 1
FFFF
IX+Offset
IX+Offset+ 1
Op Code Address + 2
1
1
0
0
1
1
1
0
0
1
1
0
0
0
u
Op Code Address + 1
FFFF
Stack POinter
Stack POinter - 1
IX + Offset
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Offset
Op Code Address + 2
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
Op Code Address + 3
Op Code Address+ 1
FFFF
IX + Offset
IX + Offset
Op Code Address + 2
Op Code Address+ 1
Op Code Address + 2
FFFF
IX + Offset
FFFF
IX+Offset
Op Code Address + 3
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
1
0
I
II
I
1
1
1
0
I
I
I
0
0
1
I
I
1
0
1
1
0
!
1
1
0
Next Op Code
1
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSBJ
Operand Data (MS8)
1
1
1
1
Operand Data (lSB)
0
Next Op Code
Offset
Restart Address (LSB)
RegIster Data (MSB)
Register Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (lSB)
Return Address (MSB)
First Subroutine Op Code
Offset
Restart Address (lSB)
Operand Data
Restart Address (lSB)
New Operand Data
Next Qp Code
Immediate Data
Offset
Restart Address (lSB)
Operand Data
Next Op Code
Offset
Restart Address (lSB)
Operand Data
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
0
1
0
1
1
1
1
1
1
Operand Data
1
1
0
1
1
1
1
0
1
1
1
1
1
1
0
1
0
0
0
I
1
1
1
1
1
1
1
1
1
0
0
0
0
I
0
Offset
Restart Address (LSB)
F,rst Op Code of Jump Routine
Offset
Restart Address (LSB)
1
1
0
1
00
I
Next Op Code
Immediate Data
Offset
Restart Address (LSD)
Operand Data
Restart Address (LSB)
New Operand 'Data
Next Op Code
(Continued)
~HITACHI
120
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Pomt Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303X, HD63A03X, HD63B03X
Address Mode &
Instructions
Address Bus
Data Bus
EXTEND
JMP
3
1
2
3
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
4
ADDD
CPX
LOS
SUBD
STD
STX
LOD
LOX
5
Address of Operand
Op Code Address + 3
1
Op Code Address + 1
Qp Code Address+2
Destination Address
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address 01 Operand + 1
Op Code Address", 3
Op Code Address + ,
Cp Code Address + 2
Destination Address
Destination Address + 1
Op Code Address + 3
Op Code Address+ 1
Op Code Address+ 2
2
3
2
3
4
STS
---
JSR
-,5
2
3
4
.. 5
1
6
ASR
DEC
LSR
ROL
1-6
CLR
2
3
4
5
6
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
a
1
1
0
0
0
FFFF
1
0
0
2
3
Stack POinter
Stack POinter - ,
Jump Address
Op Code Address + ,
Op Code Address + 2
Address of Operand
1
0
0
0
0
4
FFFF
5
6
Address of Operand
Op Code Address+ 3
Op Code Address+ 1
Op Code Address+2
Address of Operand
Address of Operand
ap Code Address + 3
1
0
1
1
1
1
1
1
0
0
0
0
1
1
5
Op Code Address + 2
3
4
4
1
5
ASL
COM
INC
NEG
ROR
1
2
Qp Code Address + 1
Qp Code Address + 2
Jump Address
Qp Code Address + 1
2
3
4
5
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
I
0
1
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
0
1
0
Jump Address (MSB)
Jump Address (lSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
Next Qp Code
Destination Address (MSB)
Destination Address (lSB)
Accumulator Data
Neltt Op Code
Address of Operand (MSB)
Address of Operand (LSBl
Operand Data (MSBl
Operand Data (lSBl
Next Op Code
Destination Address (MSB)
Destination Address (lSB)
Regl!>ter Data (MSB)
Register Data (LSB)
Next Op Code
Jump Address (MSB)
Jump Address {LSB)
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
Restart Address {lSB)
New Operand Data
Next Qp Code
Address of Operand (MSB)
Address of Operand (LSB)
Operand Data
00
Next Op Code
(Continued)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
121
HD6303X, HD63A03X, HD63B03X
Address Mode &
Address Bus
InstructIons
Data Bus
IMPLIED
... BA
"'SL
"'SR
CLC
CLA
COM
DES
INC
INX
LSAD
AOA
SBA
SEI
T... S
Te ...
TST
TXS
D......
PUL ...
"'SX
"'SLO
ce ...
CLI
CLV
DEC
DEX
INS
LSR
R(I)L
NOP
SEC
SEV
T... P
TP...
TSX
XGDX
Op Code Address + 1
1
0
1
0
Next Op Code
1
2
1
Op Code Address + 1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
FFFF
1
2
PULS
3
PSH ...
1
PSHB
4
2
3
4
PSHX
5
1
2
FFFF
3
4
Stack Pomter
Op Code Address + 1
Op Code Address + 1
2
3
FFFF
Stack POinter + 1
4
1
Stack POinter + 2
Op Code Address + ,
2
3
FFFF
4
5
1
RTS
5
2
3
4
5
1
MUL
2
3
7
FFFF
Stack POinter + 1
Op Code Address + 1
,
PULX
Op Code Address + 1
4
5
6
7
Stack POinter
Stack Potnter ~ 1
Op Code Address + 1
Op Code Address + 1
FFFF
Stack Pomter + 1
Stack POInter + 2
Return Address
Op Code Address + 1
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
0
0
1
1
j
I
1
1
:I
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
II
I
i
i
I
ji
1
1
1
i
jI
1
Next Qp Code
Restart Address (LSB)
0
Next Op Code
1
1
1
1
Data from Stack
Next Op Code
Restart Address {lSBj
1
Restart Address (lSB)
Accumulator Data
0
0
Next Op Code
NeKt Op Code
1
1
1
1
1
1
1
Data from Stack (LSS)
Next Op Code
Aest.rt ...ddress (LSS)
0
1
1
1
1
0
u
1
1
1
1
1
1
Restart Address (lSB)
Data from Stack (MSB)
Index Register (lSB)
Index Register (MSB)
Next Op Code
Next Op Code
Restart Address (LSB)
Return Address (MSBI
Return Address (lSBI
FIrst Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
(Continued)
$
122
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303X, HD63A03X, HD63B03X
Address Mode &
Instructions
Data 8us
Address Bus
IMPLIED
WAI
I
2
3
9
4
5
6
7
B
9
ATI
I
2
3
10
4
5
6
7
B
9
10
SWI
I
2
3
12
4
5
6
7
B
9
10
II
12
SlP
I
2
4
Op Code Address + 1
FFFF
Stack POinter
Stark POinter - 1
Slack POinter - 2
Stack Pomter - 3
Stack Pomter - 4
Stack Pomter - 5
Stack POinter - 6
Op Code Address + 1
FFFF
Stack POinter + 1
Stack POinter + 2
Stack POinter
+3
Stack Pomter +4
Stack Pomter + 5
Stack Pomter + 6
Stack Pomter + 7
Return Address
Op Code Address + 1
FFFF
Stack POinter
Stack POlRter - 1
Stack POlRter - 2
Stack POlRter - 3
Stack POlRter - 4
Stack Pomter - 5
Stack POlRter - 6
Vector Address FHA
Vector Address FFFB
Address of SWI RoutlOe
Op Code Address + 1
FFFF
I
I
0
I
I
I
I
I
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0
0
0
0
0
0
0
I
I
I
I
I
I
Sleep
I
3
4
FFFF
Op Code Address + 1
1
0
0
0
0
0
0
0
0
0
I
I
I
I
I
I
I
I
0
0
0
0
I
0
0
0
0
0
0
0
I
I
I
I
I
I
I
I
j
1
1
I
0
1
I
I
1
0
I
I
0
I
I
0
I
I
I
I
I
I
0
I
0
I
I
0
I
I
I
Next Op Code
Restart Address (LSBI
Return Address (LSB)
Return Address (MSB)
Index Register (LSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Next Op Code
Restart Address (lSB)
Conditional Code Register
Accumulator 8
Accumulator A
Index Register (MSBI
Index Register (lSSI
Return Address (MSB)
Aeturn Address (LSB)
First Op Code of Return Routine
Next Op Code
Restart Address (LSB)
Return Address (lSB)
Return Address (MSB)
Index Register (lSB)
Index Register (MSB)
Accumulator A
Accumulator B
Conditional Code Register
Address of SWI Routine (MSB)
Address of SWI Routine (lSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (lSB)
I
Restart Address (lSB)
Next Op Code
RELATIVE
Bee
SEQ
BGT
BlE
BlT
BNE
BAA
BVe
BSA
Bes
BGE
BHI
BlS
BMT
BPl
BAN
BVS
I
3
2
3
I
5
2
3
4
5
Op Code Address + 1
FFFF
Test= 1
I Branch Address
I Op Code Address +1 Test:=o"O
Op Code Address + 1
FFFF
StaCk POinter
Stack Potnter - 1
Branch Address
0
0
I
I
I
0
0
I
I
1
I
I
0
I
0
Branch Offset
Restart Address (lSB)
First Op Code of Branch Routme
Next Op Code
Offset
Restart Address tlSB)
Return Address (LSB)
Return Address (MSB)
First Qp Code of Subroutll'l
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
123
HD6303X, HD63A03X, HD63B03X
• WARNING CONCERNING THE BOARD DESIGN OF
OSCILLATION CIRCUIT
When designing a board, note that crosstalk may disturb the
normal oscillation if signal lines are placed near the oscillation
circuit as shown in Figure 26. Place the crystal and CL as close
to the HD6303X as possible.
~
~
.§ .§
iii
a.
(ij
&
en en
CL
:
p~;
'pel I
,,
I
XTAL
EXTAL
HD6303X
I
I
HD6303X
IDP·64SI
Do not ... a this kind of printed-circuit board design.
Figure 26 Warning concerning board design
of oscillation circuit
(Top View)
Figure 27 Example of Oscillation Circuits in Board Design
•
RECEIVE MARGIN OF THE SCI
Receive margin of the SCI contained in the HD6303X is
shown in Table 17.
Note: SCI =Serial Communication Interface
HD6303X
START
3
Table 17
Bit distortion
tolerance
(t-to) Ito
Character
distortion tolerance
(T -To) ITo
±43.7%
±4.37%
6
4
8
STOP
Ideal Waveform
Real Waveform
1 + - - -_ _
• WARNING CONCERNING WAI INSTRUCTION
If the HALT signal is accepted by the MCU while the WAI in·
struction is executing, the CPU will not operate correctly after
HALT mode is canceled.
WAI is a instruction which waits for an interrupt. The cor·
responding interrupt routine is executed after an interrupt
occurs.
However, during the execution of the WAI instruction,
HALT inpu t makes the CPU malfunction and fetch an abnormal
interrupt vectoring address.
In HALT mode, the CPU operates correctly without the WAI
instruction, and WAI is executed correctly without HALT input.
Therefore, if HALT input is necessary, make interrupts wait
during the loop routine, as shown in Figure 28.
T_!-t-1_ _---l.1
1
it
I
WAI
~
1 - - - - - - - 1 waltong for
HALT onput
(
Interrupt
~
wrong vector address
(MSB)
wrong vector address
(LSB)
..
op-code fete h
,
Interrupt occurs
t
vector fetch for interrupt
~
t
Interrupt routine
I
Figure 28 MAC function during WAI
~HITACHI
124
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303X, HD63A03X, HD63B03X
• WARNING CONCERNING POWER START·UP
RES must be held low for at least 20 ms when the power
starts up. In this case, the internal reset function is not effective
until the oscillation begins at power·on. The RES signal is input
to the LSI in synchronism with the internal clock q, (shown in
Figure 30.)
Therefore, after power starts up, the LSI conditions such as
its 1/0 ports and operating mode, are unstable. Fix the level of
1/0 ports by means of an external circuit to determine the level
for system operation during the oscmator stabilization time.
•
Cli
CLi
WAI
1) MAL funct.on
LOOP
BRA
lOOP
··
·
iO Recommended method
Figure 29 Program to wait for interrupt
• WRITE-ONLY REGISTER
When the CPU reads a write-only register, the read data is
always $FF, regardless of the value in the write-only register.
Therefore, be careful of the results of instructions which read
write-only register and perform an arithmetic or logical operation on its contents, such as AIM, ADD, or ROL, is executed,
because the arithmetic or logical operation is always done with
the data $FF. In particulars, don't use the AIM, OIM or ElM
instruction to manipulate the DDR bit of PORT.
Internal reset
signal
Figure 30 RES circuit
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
125
H D6303V, H D63A03V,
H D63B03V, H D63C03Y
CMOS MPU (Micro Processing
The HD6303Y is a CMOS 8-bJI single-chip mIcroprocessing unit
which contains a CPU compatible with the CMOS 8-bit microcomputer HD6301 V, 256 bytes of RAM, 24 parallel I/O pins, Serial
Communication Interface (SCI) and two timers
•
•
•
•
•
•
•
Unit)
HD6303YP, HD63A03YP,
HD63B03YP, HD63C03YP
FEATURES
Instruction Set Compatible with the HD6301 V1
256 Bytes of RAM
24 Parallel 1/0 Pms
Parallel Handshake Interface (Port 6)
Darlington Transistor Drive (Port 2, 6)
16-B.t Programmable Timer
Input Capture Register x 1
Free Running Counter X 1
Output Compare Register x 2
• 8-Bit Reloadable Timer
External Event Counter
Square Wave Generation
• Serial Communication Interface (SCI)
Asynchronous Mode (8 Transmit Formats, Hardware Panty)
Clocked Synchronous Mode
• Memory Ready
3 Kinds of Memory Ready
• Halt
• Error Detection
(Address Error, Op-code Error)
• Intarrupt - External 3, Internal 7
• Maximum 85k Bytes Address Space
• Low Power DiSSIpation Mode
Sleep Mode
Standby Mode (Hardware Standby, Software Standby)
• Minimum Instruction Execution Time - 0 5lts (f = 2MHz)
• Wide Range of Operation
Vcc =3t05.5V (f=O.1 toO.5MHz)
f= O. 1 to 1.0MHz : HD6303Y }
Vcc=5V± 10% { f=O.1 to 1.5MHz. HD63A03Y
f=O.1 to 2.0MHz HD63B03Y
f=O.1 to 3.0MHz ; HD63C03Y
•
•
(DP-64S)
HD6303YF, H D63A03YF,
HD63B03YF, HD63C03YF
(FP-64)
HD6303YH,HD63A03YH
HD63B03YH,HD63C03YH
PROGRAM DEVELOPMENT SUPPORT TOOLS
Cross assembler and C compiler software for IBM PCs and
(FP-64A)
compatibles
•
In circuit emulator for use with IBM pes and compatibles
HD6303YCP,HD63A03YCP
HD63B03YCP,HD63C03YCP
(CP-68)
.HITACHI
126
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• PIN ARRANGEMENT
• HD6303YP, HD63A03Yp, HD63B03YP,
HD63C03YP
• HD6303YF, HD63A03YF, HD63B03YF,
HD63C03YF
iii)
EXTAl
WII
, RtW
MP.
MP.
IfB
STiY
Dli
•
8A
0,
0,
0,
0,
D.
D.
D.
m
P"
PI. 1
PJI 1
PH'
PJ:1
Ao
1
A,
Poo '
PII 1
Psz 1
A,
P.,
p..
p..
'"
A.
A.
,
PH
P"
V..
p..
PI!
A,
P"
p..
p..
p..
p..
p.,
:;;:N!::~~t:!~~~~g;:;:::;
A.
:t~~£~:t~J.JJJ~:
A,
(Top View)
A"
A ..
7
A"
A ..
,
Au
Vee
(Top View)
• HD6303YCP, HD63A03YCp, HD63B03YCP,
HD63C03YCP
• HD6303YH, HD63A03YH, HD63B03YH,
HD63C03YH
o
D,
D,
D.
D,
D,
D,
A,
A,
A,
A,
A,
P"
P"
A,
p ..
A,
P"
P"
A,
VS82
A.
~~
MM M~~~~~
~~~
~~~~~~~~~;1J~J~~;
(Top View)
(Top View)
~HITACHI
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
127
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• BLOCK DIAGRAM
Vcc_
Vss Vss P,o(T,n )
P2I(Tout,)
Pn(SClK)
P23(Rx
)
P,.(Tx
)
P,s(Tou!»
P,6(Tout3)
P,,(TClK)
...J
a:
N
~
a:
C
C
«
~
...J
~
OW
XMX
Rb
WR
CPU
~
R!W
('J]:f
0
CL
BA
...
~:I
..
III
:I
o.
!...
05
06
07
III
0
PSO(i1lC1, )
PSlmm, )
Ps,(MR )
PsJ(Rm)
)
Ps.(iS
P5S( O"S
PS6
P.,
Poo
p. ,
P 6,
P6J
P6.
P6S
P66
P67
,.
i
III
c
~
a:
0
CL
Do
0,
0,
03
Ao
A,
A,
AJ
A.
As
A.
A7
As
A.
Alo
All
A"
Al3
A,.
A15
<0
~
a:
0
CL
RAM
256Bytes
$HITACHI
128
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Unit
Value
Supply Voltage
Vee
-0.3-+7.0
V
Input Voltage
-0.3-V ee +0.3
V
Operating Temperature
V,"
Top<
-20- + 75
·C
Storege Temperature
T.tg
-55-+150
·C
(NOTE) This product has protection circuits in input terminal from high static electricity voltage and high electric f.eld
But be careful not to apply overvoltage more than maximum ratings to these high input Impedance protection circuits To allura the normal
operation, we recommend V in • Vout : Vss ~ (V.., orVout) ~ Vee·
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee = 5.0V '" 10%, VSS = OV, Ta = -20·C - + 75·C, unless otherwise noted.)
Item
Symbol
Test Condition
m,STBV
Input "High" Voltage
EXTAL
V,H
Input "Low" Voltage
All Inputs
Input Leakage Current
N;;M, m, STliY,
MPo,MP,
II," I
V",= 05-V ee -0.5V
~-A;lk 0 0 -0 7 , !w,
IITSII
V., = 0.5-Vee-0.5V
,R
Output "High" Voltage
All Outputs
-
V OH
IOH= -200jl.A
IoH = -10jl.A
max
Unit
Vee
+0.3
V
-
O.S···
V
1.0
jl.A
1.0
jl.A
-
Vcc- 0 .7
-
-0.3
V,L
,Ports 2,5,6
typ
Vee XO.7
2.0
Other Inputs
Three State
Leakage Currant
min
V ee -0.5
2.4
-
V
V
Output "Low" Voltage
All Outputs
VOL
IOL = 1.6mA
-
-
0.4
V
Darlington Drive
Current
Ports 2, 6
-I OH
V.u.=1.5V
1.0
-
10.0
mA
Input Capacitance
All Inputs
C,"
Von = OV,I = lMHz,
Ta = 25·C
12.5
pF
Non Operation
ISTB
-
-
Standby Current
3.0
15.0
jl.A
mA
Sleeping (1= 1MHz")
ISLP
Sleeping (1= 1.5MHz··)
Sleeping (f= 2MHz")"
Sleeping (1=3 MHz)
Current Dissipation'
Operating (f= 1MHz")
Operatmg (f= 1.5MHz")
Icc
-
1.5
3.0
2.3
4.5
mA
3.0
6.0
mA
4.5
9.0
mA
7.0
10.0
mA
10.5
15.0
mA
Operating (f= 2MHz")"
-
14.0
20.0
mA
Operating (1=3 MHz)
-
21.0
30.0
mA
2.0
-
-
V
VRAM
RAM Standby Voltage
-
=
V IH min
Vee - 1 ,QV. VIl max = 08V (All output terminals are at no load)
Current Dissipation of the operating or sleeping condition IS proportional to the operating frequency So the typ or max values about Current
Dissipations at X MHz operation are deCided according to the follOWing formula
typo value If
X MHz)
typo value (f
1MHz) x X
max value (f
X MHz)
max. value If
1MHz) x X
(both the sleeping and operating)
=
=
... SCLK
=
=
=
=
O.6V (-20·C-O·C)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
129
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• AC CHARACTERISTICS (Vee = 5.0V ± 10%, VSS = OV, T. = -20 - + 75°C, unless otherwise noted.)
BUS TIMING
Item
Symbol
HD6301YO
Test
Condition
typ
tHR
0
PWRW
450
t RWD
-
Cycle Time
tey<:
1
Enable Rise Time
tEr
Enable Fall Time
t E,
-
Enable Pulse Width "High" Level'
PW EH
450
Enable Pulse WIdth "Low" Level'
PW EL
450
Address, AIW Delay Time·
t DOW
-
t DSA
80
tAH1
80
tAD
I Write
I Read
Data Delay Time
Data Set-up Time
Address, RIW Hold Time"
I Write·
Data Hold Time
Fig 1
t HW1
80
RD, WR Address Hold Time'
tAH2
70
RD, WR Data Hold Time'
tHW2
70
I Read
Data Hold Time
RD,
WR Pulse Width'
RD,
WR Delay Time
RD, WR Hold Time
tHAW
LlR Delay Time
tOLA
-
LIR Hold Time
tHLA
10
-
Peripheral Read Access Time
tACC
-
MR Set·up Time'
ISLR
400
MR Hold Time'
tHMA
-
-
200
E Clock Pulse Width at MR
Fig
2
PW EMR
Processor Control Set-up Time
tpcs
Processor Control Alse Time
tpet
Processor Control Fall TIme
tpCf
SA Delay Time
teA
Fig. 3
-
OSCillator Stabilization Time
tRC
Fig. 14
20
Fig. 2, 3
PW RST
Reset Pulse W,dlh
-These timings change
Fig 3, 13, 14
In
HD63A01YO
HD63B01YO
HD63C01YO
Unit
min.
In
min
typ
max
min
typ
max
min
typ
-
10
0.666
05
0333
25
-
-
10
-
-
10
25
25
25
-
-
25
-
-
25
--
-
300
-
220
-
-
t40
220
-
-
140
250
-
-
190
-
-
160
120
70
-
60
-
50
-
40
-
50
-
40
-
40
-
20
-
160
-
-
230
70
-
9
-
-
200
100
-
200
40
20
200
300
50
50
0
300
-
-
-
-
280
100
9
-
-
-
200
-
100
-
100
250
-
-
3
approximate proportion to tcye The figures
max
10
160
-
-
20
3
40
40
0
-
-
190
-
-
10
-
20
3
thiS characteristics represent those when teye
IS
40
20
-
120
50
9
100
100
160
-
minimum (""
20
20- 20
- -20
0
140
5
180
-170
100
20
3
-
10
.s
20
ns
20
ns
-
ns
-
ns
120
ns
100
ns
-
ns
-
ns
40
ns
20
ns
80
ns
--
ns
50
-
-
220
100
-
-
max
In
ns
ns
ns
,...---ns
ns
ns
ns
25
ns
9
.s
-
ns
50
ns
50
ns
120
ns
-
ms
tcye
the highest speed operation)
Peripheral Port Timing
Item
Peripheral Data
Set Up T,me
Peripheral Data
Hold Time
Svmbol
Port 2,5,6
HD6303Y
Test
condition
tpDSU
HD63A03Y
Time
Input Oat. Set.lJp
Time
Port 2,5,6
tpDH
Port 2.5,6
tpWD
Fig. 6
tpWIS
Port 6
tlH
Port 6
tiS
Output Strobe Delav Time
min
tvP
max
min
tvP
max
min
tvP
max
200
-
-
200
-
-
200
-
-
200
-
200
-
-
200
-
-
200
-
-
200
-
-
-
-
300
-
-
300
-
-
300
-
-
300
tDSDl
IoSii2
Fig.l0
200
-
-
200
-
-
200
-
-
-
ns
-
-
150
-
--
ns
-
-
150
100
-
-
-
200
150
-
100
-
-
100
-
-
ns
Fig.ll
-
-
-
200
-
-
200
-
-
200
n.
$
130
Unit
max
Fig. 5
Input Strobe Pulse Width
Input Data Hold
HD63C03Y
tvP
Delay Time (From
Enable Fall Edge to
Peripheral Output)
HD63B03Y
min
200
150
100
-
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
ns
n.
n.
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
TIMER, SCI TIMING
Item
Symbol
Timer 1 Input Pulse Width
Delay Time (Enable Positive
TranSItion to Timer Output)
SCI Input Clock Cycle
II Mync Mode
Clock Sync
SCI Transmit Data Delay Time
(Clock Sync Mode)
HD63A03Y
HD63C03Y
HD63B03Y
Unit
min
typ
max
min
typ
max
min
typ
max
min
typ
max
tpWT
Fig 9
20
-
-
2.0
-
-
20
-
-
20
-
-
leye
tTOD
Fig 7,8
-
-
400
-
-
400
-
-
400
-
-
400
ns
Fig 9
10
-
-
-
-
-
tcye
20
-
10
20
-
10
20
-
10
Fig 4
20
-
-
teye
-
-
220
-
-
220
-
-
220
-
-
220
ns
260
-
-
260
-
-
260
--
-
260
-
-
ns
-
-
100
-
-
ns
06
tSeye
tSeye
trxD
SCI Receive Data Set-up Time
(Clock Sync Mode)
HD6303Y
Test
Condition
tSAX
Fig 4
SCI Receive Data Hold Time
(Clock Sync Mode)
tHRX
100
-
-
100
-
-
100
SCI Input Clock Pulse Width
tpWSCK
04
0.4
0.4
-
0.6
04
20
-
200
200
-
-
20
200
-
20
tpWTCK
-
-
06
20
-
0.6
1wye
200
-
Timer 2 Input Clock Cycle
Timer 2 Input Clock Pulse Width
Timer 1-2, SCllnpul
Fig 9
-
teye
ns
Clock Rise Time
leK<
-
-
100
-
-
100
-
-
100
-
-
50
ns
Timer 1-2, SCI Input Clock Fall Time
tCKf
-
-
100
-
-
100
-
-
100
-
-
50
ns
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
131
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
ICYC
v
2.4V
j
PWEL
E
1\
PWEH
7f-
t\a.8V
....
lAD
~
\-
r-
f-
.-tEr
tEl
tAHl
:?C
2.4V
a.8V
tAH2
PWRW
IRWO
'\,
RD,WR
~
tHRW
Jl
a.8V
2.4V
tHW2
IOOW
tHWl
~
IOSR
IACC
LlR
/
2.aV
~
a.8V
IOLR
--~
1,.
.",
2.4V
a.8V
~
7'
L>--
tHR
r----
,.
7~
Y-
~
tHLR
_
O.8V
_____
Figure 1 Bus Timing
E
MR
tPCr
Figure 2 Memory Ready and E Clock Timing
$
1 32
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Last Instruction
E
I ••
I-""II"::-:-:-:-",,...__...;I;;.;'C;;.'"':":""'..,l;;':::"_ _..,.
2 4V
BA
08V
Figure 3
HALT and SA Timing
Synchronous Clock
Transmit Data
Receive Dala
'2 OV
2.4V
Figure 4
IS
IS
high level when clock Input
high level when clock output
SCI Clocked Synchronous Timing
jMPUWrite
E
Figure 5 Port Data Set-up and Hold Times (MPU Read)
Figure 6 Port Data Delay Times (MPU Write)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
133
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
E
E
T2CNT
T,mer 1 - - - - . . . . r-..,.L::::'::;~~
FRC
r----
P'5-------'-~
"=r----
Outputs _ _ _ _ _ _ _.....J
~=---
P'"
P,.
Output
(TCONR=N)
Figure 7
••
T,mer 2 Output TIming
tCKI
'TImer 2 . tteye
SCI
. tSeye
F,gure 9
Figure 8
TImer 1 Output TIming
"T,mer 1 . tPWT
TImer 2. tPWTCK
SCI
. tPWSCK
PORT6
Data
(Input)
T,mer 1·2. SCI Input Clock TImIng
FIgure 10
Port 6 Input Latch TImIng
1rl
Vee
RL =22kQ
Test POint
MPU access of
PORT6
C
R
lS2074181
or EqUlv
C = 90pF for 0 0 -0,. A,,-A , •. E
= 30pF for Port 2. Port 5. Port 6. liD.
WIt RIW. BA. m
R = 12kO
FIgure 11
Figure 12
Output Strobe TIming
Bus TImIng Test Loads ITTL Load)
Interrupt
Test
Intarna'
Addr.ss Bus --"-+-~_-J'-_"-_-"_....J"-_J\.._....I',-......,,-_J\.._.J\~....J"-_.I\.._..A_...J'-_.II...
ector Vector
sp
Ne"
sP, $P·3 SP 4
SP·l
SP 6
MSB
lSB
PC
Address Addr.
Address
Interna'
D.t'~
_ _"-_~_-J'-_~_~_-J'-_"-_.J\__....J"-_.I\.._-"_...J'-__.I\..__~__....I'~__AIX8 IX 15
Internal
ReId
Intern,l
Wnte
\~
AceA
AceS
Vector Vector First Inst of
MSB
lS8
Interrupt R04JMe
eeR
____________________r-----------
------',
\
F,gure 13
Interrupt Sequence
.HITACHI
134
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
, _Bl..JU1..
--55~V~
________-+______~______________~
I!-="---IJIC ~.---'pes
on -----< ___________.....__-1
\~>------II....
r
_ _ __
w.. ~I_II• •I!bL........_______~:~~>-r
·,....i_..
____
---< ....-----:\\~....--.r-'.'
..
_a>I\1Mi~~W!\lM\,l1il1~w.r-'
...
_:~\\\\\\\\\\\\..
t:::TD;.-...r-41-J----------11::7"D'~I;.J- - - - -
"
• • •IW~----:;:O_O_O:JlI..."'----.:II-'- - - pee - pco -
~·.IA
First
PC 15
PC 1
Instruellon
Figure 14 Reset Timing
• FUNCTIONAL PIN DESCRIPTION
• Vee. Vas
Vee and Vss provide power to the MPU with 5V± 10% supply.
In the case of low speed operation (fmax=500kHz), the MPU can
operate with 3 to 5.5 volts. Two Vss pins should be tied to ground.
•
XTAL.EXTAL
These two pins interface with an AT-cut parallel resonant crystal.
Divide-by-four circuit is on chip, so if 4MHz crystal oscillator is
used, the system clock is IMHz for example.
EXTAL pin can be drived by the external clock with 45% to 55%
duty. The system clock which is one fourth frequency of the external clock is generated in the LSI. The external clock frequency
should be less than four times of the maximum operating frequency. When using the external clock, XTAL pin should be open. Fig.
15 shows examples of connection circuit. The crystal and CLI , CL2
should be mounted as close as possible to XTAL and EXTAL pins.
Any line must not cross the line between the crystal oscillator and
XTAL, EXTAL.
AT Cut Parallel Resonant Crystal Oscillator
Co=7pF max
Rs=60Q max
XTALr-~~---,
Cl
EXTALt--~~
CLI =Cu
= 1OpF - 22pF ± 20%
(3.2-BMHzl
• fiIV
This pin makes the MPU standby mode. In "Low" level, the os·
cillation stops and the internal clock is stabilized to make reset condition. To retain the contents of RAM at standby mode, "0"
should be written into RAM enable bit (RAME). RAME is the bit
6 of the RAM/port 5 control register at SOOI4. RAM is disabled by
this operation and its contents is sustained.
Refer to "LOW POWER DISSIPATION MODE" for the
standby mode.
R•••t IJiESI
This pin resets the MPU from power OFF state and provides a
pin must be held "Low"
startup procedure. During power-on,
level for at least 2Oms.
The CPU registers (accumulator, index register, stack pointer,
condition code register except for interrupt mask bit), RAM and
the data register of ports are not initialized during reset, so their
contents are undefined in this procedure.
To reset the MPU during operation, li:ES should be held "Low"
for at least 3 system-clock cycles. At the 3rd cycle during "Low"
level, all the address buses become "High". When RES remains
"Low", the address buses keep "High". IfRBbecomes "High",
the MPU starts the next operation.
(I)
Latch the value of the mode program pins; MP. and MP,.
(2) Initialize each internal register (Refer to Table 4).
(3) Set the interrupt mask bit. For the CPU to recognize the
maskable interrupts IRQ" IRQ, and IRQ., this bit should be
cleared in advance.
(4) Put the contents (=start address) of the last two addresses
(SFFFE, SFFFF) into the program counter and start the program from this address. (Refer to Table I).
•
m
• Enabl. lEI
This pin provides a TTlrcompatible system clock to external circuits. Its frequency is one fourth that of the crystal oscillator or external clock. This pin can drive one TTL load and 90pF capacitance.
• Non-Ma.kable Interrupt INMII
When the falling edge of the input signal is detected at this pin,
the CPU begins non-maskable interrupt sequence internally. As
Figure 1 5 Connection CirCUit
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
135
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
well as the mQ mentioned below, the instruction being executed at
Nm signal detection will proceed to its compeletion. The interrupt
the current instruction before the acceptance of the request. Unless
the interrupt mask in the condition code register is set, the CPU
starts an interrupt sequence; if set, the interrupt request will be ignored. When the sequence starts, the contents of the program
counter, index register, accumulators and condition code register
will be saved onto the stack, then the CPU sets the interrupt mask
bit and will not acknowledge the maskable request. During the last
cycle, the CPU fetches vectors depicted in Table 1 and transfers
their contents to the program counter and branches to the service
routine.
The CPU uses the external interrupt pins (IRQ, and IRQ,) also
as port pins P50 and P", sO it provides an enable bit to Bit 0 and 1 of
the RAM port 5 control register at $0014. Refer to "RAM/PORT 5
CONTROL REGISTER" for the details.
When one of the internal interrupts, ICI, OCI, TOI, CMI or SIO
is generated, the CPU produces internal interrupt signal (IRQ,).
IRQ, functions just the same as IRQ, or IRQ, except for its vector
address. Fig. 16 shows the block diagram of the interrupt circuit.
mask bit of the condition code register doesn't alTect non-maskable
interrupt at all.
In response to an NMI interrupt, the contents of the program
counter, index register, accumulators and condition code register
will be saved onto the stack. Upon completion of this sequence, a
vector is fetched from SFFFC and SFFFD to transfer their contents
into the program counter and branch to the non-maskable interrupt
service routine.
(Note) At reset start, the stack pointer should be initialized on
an appropriate memory area and then the falling edge
be input to lilMI pin.
mur,.
e Interrupt Reque.t
lmf,)
These are level-sensitive pins which request an internal interrupt
sequence to the CPU. At interrupt request, the CPU will complete
Each Status Registers Interrupt
Enable Flag
"1" ,Enable "0'" Disable
.....,.
ISF
ilmi
---..
imIl
---..
""-
ICF
OCFl
Q-
OCF2
--0-
--
TOF
IRQJ
CMF
RORF
-0ORFE
TORE
RJ;f1
-0-
1
ICI
....~
TOI
CondItIon
Code
Aeglster
I MASK
'0' Enable
. l' . Disable
~
CMI
~
~dge
1
E~tectlve
IrcUit
Addr,ss Error
Op Code Error
O,lee!",' Clrcu.t
~
Interrupt
Request
Signal
Sleep
Cancel
Signal
TRAP
SWI
Figure 16
Interrupt CirCUit Block D,agram
~HITACHI
136
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Priority
Highest
Lowest
Table 1 Interrupt Vector Memory Map
ries. Refer to "RAM/PORT 5 CONTROL REGISTER" for more
details.
Vector
MSB
LSB
FFFE
FFFF
FFEE
FFEF
FFFC
FFFD
• Halt IHALT; P n )
This .s an Input control signal to stop instruction execution and
to release buses. When this signal switches to "Low", the CPU
stops to enter IOta the halt state after having executed the present
instruction. When entering into the halt state, it makes BA "High"
and also an address bus, data bus, RD, WR, R/W high impedance.
When an interrupt is generated in the halt state, the CPU uses the
interrupt handler after the halt is cancelled. When halted during the
sleep state, the CPU keeps the sleep state, while BA is "High" and
releases the buses. Then the CPU returns to the previous sleep
state when the HALT signal becomes "High".
(Note) Please don't switch the HALT signal to "Low" when
the CPU executes the WAI instruction and is in the interrupt wait state to avoid the trouble of the CPU's operation after the halt is cancelled.
FFFA
FFFB
FFFB
FFF9
FFF6
FFF7
FFF4
FFF5
FFF2
FFF3
FFEC
FFED
FFEA
FFEB
FFFO
FFF1
Interrupt
l'IES
TRAP
Nm
SWI
(Software Interrupt)
llfQ,. ISF (port 6 Input Strobe)
ICI
IT .mer 1 Input Capture)
OCI
(T.mer 1 Output Compare 1.2)
TOI
(Timer 1 Overflow)
CMI
(T.mer 2 Counter Match)
llfQ2
SID
(RDRF+ ORFE+ TDRE+ PER)
• Mode Program (MP o• MP,)
Set MP, "High" and MP, "Low"
• Read/Write IR/W)
This signal, usually be in read state ("High"), shows whether
the CPU is in read ("High") or write ("Low") state to the peripheral or memory devices. This can drive one TTL load and 30pF capacitance.
• '1115. 'WA'
These signals show active low outputs when the CPU is reading/
writing to the peripherals or memories. This enables the CPU easy
to access the peripheral LSI with 'RTI and WR Input pins. These pins
can drive one TTL load and 30pF capacitance.
• Load Instruction Register (L1R)
This signal shows the instruction opecode being on data bus
(active low). This pin can drive one TTL load and 30pF capacitance.
• Memory Ready IMR; P n )
This is the input control signal which stretches the system
clock's "High" period to access low-speed memories. HD6303Y
can select three kinds of low-speed memory access method by
RAM/Port 5 Control Register's MRE bit and AMRE bit. In the
case that CPU accesses low-speed memories by the external MR
signal (MRE="I", AMRE="O"), the system clock operates in
normal sequence when this signal is in "High".
But this signal in "Low", the "High" period of the system clock
will be stretched depending on .ts "Low" level duration 10 mtegral
multiples of the cycle time. This allows the CPU to interface with
low-speed memories (See Fig. 2). Up to 91'-s can be stretched.
DUring internal address space access or non valid memory access, MR is prohibited internally to prevent decrease of operation
speed. Even in the halt state, MR can also stretch "High" period of
system clock to allow peripheral devices to access low-speed memo-
• Bus Available IBA)
This is an output control signal which is normally "Low" but
"High" when the CPU accepts HALT and releases the buses. The'
HD6800 and HD6802 make BA "High" and release the buses at
WAI execution, while the HD6303Y doesn't make BA "High"
under the same condition.
• PORT
The HD6303Y provides three 8-bit I/O ports. Each port provides Data Direction Register (DDR) which controls the I/O state
by the bit.
Table 2 Port and Data Dlfection Reg.ster Address
Port
Port 2
Port 5
Port 6
Port Address
$0003
$0015
$0017
Data Direct.on Register
$0001
$0020
$0016
• Port 2
An 8-bit I/O port. Port 2 DDR (P2DDR) controls the I/O state.
This port provides DDR corresponding to each bit and can define
input or output by the bit ("0" for input, "I" for output).
As Port 2 DDR is cleared during reset, it will be an input port.
Port 2 is also used as an I/O pin for timer I, Timer 2 and the SCI.
Pins for Timers and the SCI set or reset each DDR depending on
their functions and become I/O pins. When port 2 functions as an I/
o port after used as I/O pins of the timers or the SCI, the I/O direction of the pins remain as it is used as the I/O pin of timer and SCI.
Port 2 can drive one TTL load and 30pF capacitance. ThiS port
can produce )mA when V0"'= 1.5V to drive directly the base of
Darlington transistor.
P2o lTin)
P" is also used as an external input pin for the input-capture.
This pin IS an I/O port which is an input or output as defined by the
Data Direction Register (P"DDR) ("0" for an input and" 1" for
an output) Then either a signal to or from P" ("to" for an output
port, "from" for an input port) is always input to the Timer) input
capture.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
137
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
RES
R
"'
.------; 0
D 1----1~
P,o DDR
l!l
~
C
WP2D
1-----10
iO
E
~
D
P,o DATA
C
~
WP2D DDR Wnte Signal
WP2
Port Wnte Signal
RP2
Port Read Signal
WP2
Timer 1
Input Capture Input
>------------.
PZl (Tout 1). PZ4 (Tx). PZ6 (Tout 21. PZ6 (Tout 3)
These four pins can be also used as output pins for Timer I,
Timer 2 and a transmit output of the SCI. Timer I, and the SCI
S
have a register which enables output. By selling these registers,
they automatically will be output pins of timer or the SCI.
R
.------t--iO
D I---~ "'
P"DDR
~
C
WP2D
'-_..r
I"
-,
co
lii
0
iO
0
DI---~ E
P" DATA
c:
C
-"
,!'~~~ ~ ,_T~".:'~r}_ and SCI
I
I
WP2
~.r-f'+-------+--~-- Output Data
-------+-----r-- Output Enable Signal
L -......
~HITACHI
138
Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
ble as an I/O port when the SCI has no clock mput or output (as an
output port If P" DDR= I, as an mput port If P" DDR=O).
PuISCLK)
P" is also used as a clock I/O pm for the SCI. It IS selected as a
clock input or output pin by the operating mode of the SCI. It is usaAES
S A, A,
r---------~,Q
D~--+_~
p" DDA
C
'":J
'"~
WP2D
I
T
01---+-+ 0'"
~_J,,---,Q
p" DATA
_____--l--__U - - - . ilm'
MR
RArf
• Initializing value dunng reset;
IR01E= "0", IR02E= "O",MRE = "O",HLTE= "1"
P I4 (is)
_
p .. is also usable as the input strobe (IS) for port 6 handshake
interface. This pin, as is P", is always an I/O port. If P,. IS used as an
output port (set the DDR ofP.. to "I"), an output signal from P"
will be the input to IS:
RES
.-------iQ
R
01----1
P" DDR
'""
C
--=---------11---. Port
is
6 Control Status Register
~HITACHI
140
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
by setting the OS enable register (OSE) of the port 6 Control Status
Register (P6CSR).
P•• I(J§)
P" is also usable as the output strobe (OS) for port 6 handshake
interface. It will be an 1/0 port during reset, and an OS output pin
RES
'"
:>
'"~
0
P•• OOR
..
to
C
0
W 50
E
~
Q
0
P•• OATA
E
Port 6 Control/Status Register
C
r---------I
WP5
~rr'-+_----------~----+-OS
OSE
RP5
....l....-
(0'
OS output
)
OS output disable
Pl.' P&1
P56 and P" are 110 ports.
RES
R
Q
0
p," OOR
C
WP50
Q
0
p," DATA
C
'"
'"~"
..'"
0
c:
Q;
E
WP5
RP5
~
POAT5 DDA ($0020)
(Wrote only. SOO
L----IL-..-l_.J_-L_-L_....L._..L---l dUring reset)
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
141
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Port 6 controls parallel handshake onterface besides functions as
an I/O port. Therefore, it provides DDRs to control and IS LATCH
to latch the input data.
Port 6 can drive one TTL load and 30pF capacitance. It can drive
directly the base of Darlington transistor as port 2.
• Port 6
8-bit 110 port. Port 6 DDR controls I/O state. Each bit of port 6
has a DDR and designates input or output ("0" for input, "I" for
output). During reset, Port 6 DDR is cleared and port 6 becomes an
input port.
RES
R
'"
D
P., DDR
C
co"
WP6D
'E"
Q
~
'"
0
~
Q
D
P., DATA
C
RS
R
oS
WP6
RP6
WP6D DDR Write Signal
-L.
WP6
Port Write signal
Q
D
RP6
Port Read signal
IS LATCH
C
_ _ _ _ _ _ _ _ _ _ _ _ _ _ Port 6
Control Status Reg,ster
~
PORT6 DDR 1$00161
(Write onlv. $00
dUring reset)
PORT6 ($00171
(R/W. not InIttallzed dunng
reset)
• BUS
• Addre.. Bus (Ao - Au)
Address Bus (Ao - A,,) is used for addressing the memory and
peripheral LSI.
This bus can interface with the bus of HMCS 6800 and drive one
TTL load al,d 90pF capacitance.
P" are cleared and become IRQ, input pin and rn:Q, input pin.
When IRQ,E and IRQ,E are set, p.. and P" cannot be used as an
output ports. When "0", the CPU doesn't accept an external interrupt or a sleep cancellation by the external interrupt. These bits are
cleared during reset.
Bit 2 Memory Ready Enable Bit (MRE)
•
Data BUB (Do - D7)
8-bit parallel data bus for data transmit between the memory or
peripheral LSI. This bus can drive one TTL load and 90pF capacitance.
When using P" as an input pin of the "memory ready" signal,
write" 1" in this bit When set, P" DDR is automatically cleared
and becomes the MR input pin. The bit is cleared during reset.
Bit 3 Halt Enable Bit (HLTE)
• RAM/PORT 5 CONTROL REGISTER
The control register located at $0014 controls on-chip RAM and
port 5.
RAM/Port 5 Control Register (RP5CR)
When using P53 as an input pin of the HALt signal, write" 1" in
this bit. When this bit is set, P" DDR is automatically cleared and
becomes the Halt input pin. If the bit is "0", the Halt function is
inhibited and P" is used as an I/O port. The bit IS set to "1" during
reset.
Bit 4 Auto Memory Ready Enable Bit (AMRE)
$0014
Bit 0. Bit lli'Rf,.
fiI02 Enable Bit (lRO,E. IR02E)
When using P50 and PSI as interrupt pins, write "1" in these bits.
When the bit is set to "1 ", the DDRs corresponding to P" and
When the bit is set and the CPU accesses the external address,
"memory ready" operates automatically and stretches the E clock's
"High" duration for one system clock. When MRE bit of bit 2 is
cleared and when the CPU accesses the external address space, the
function operates. When MRE bit is set and then the CPU accesses
the external address space w,th P,,(MR) pin in "low", "memory
ready" operates automatically. This bit is set to "1" during reset.
~HITACHI
142
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Table 3 "Memory Ready" Function
MRE
AMRE
0
0
"Memory ready" inhibited.
0
1
When the CPU accesses the external address, "High" duration of E clock automatically becomes one-cycle
longer This state IS retained dUring reset
1
0
1
1
Function
"Memory ready" operates by P 52 (MR) pin The funcllon IS the same as that of the HD6301XO
When the CPU accesses the external address space with the P 52 (MR) pin in "low", the "auto memory
ready" operates This function IS effective If It has both "high-speed memory" and "slow memory"
outside Input CS signal of "slow memory" to MR pin
this bit is cleared (=loglc "0") on-chip RAM is invalid and the
CPU can read data from external memory. This bit should be "0"
before gettmg IOta the standby mode to protect on-chip RAM data,
Bit & Standby Flag (STBY FLAG)
By c1earmg thiS flag, HD6303Y gets IOta the standby mode by
software. This flag is set to "I" durmg reset, so the standby mode IS
canceled with 1rnS' pm in "low" The IfES pin should be in "low"
until oscillation becomes stable (mm 20ms.). If the STBY pin in IS
in "low", the standby mode can not be canceled wIth the RES pin
Bit 7 Standby Power Bit (STBY PWR)
When Vee is not provided m standby mode, this bit IS cleared
ThIS IS a flag for read/write and can be read by software. If this bit is
set before standyby mode, and remams set even after returnmg
from standby mode, Vee voltage is provided dunng standby mode
and the on-chip RAM data is vahd.
in "low",
Bit 6 RAM Enable (RAME)
On-chip RAM can be disabled by thIS control bit By resettmg
the MPU, "I" is set to this bit, and on-chip RAM IS enabled When
(a) MRE =0, AMRE = 1
,
,
, _---''
E
~-
Address
external
address
external address
Bus
Internal address
(b) MRE=I, AMRE=1
E
Address""'\ ,...-,==..--.. r-.,=-==--,.,----------..,-="..,.,..,,-....
external
Bus
address
,.--------~
external addres:i
MR
(CS pin of "slow memory")
(c) MRE= 1 ,AMRE=O (HD6301 XO Compatible Mode)
E
Address
Bus
,,--,,=::-::r--.r-.==--.r-+-----------!,
r-:::=c::r--. r-:::-=-:-"\
external address
MR
Figure 17
Memory Ready Timing
• Port 6 Control/Status Register
Ti'.is is the Control/Status RegISter for parallel handshake mterface using Port 6. The functions are as follows,
Il Latches input data to Port 6 at the IS (P,,) falhng edge
2) Outputs a strobe signal OS (P,) outward by reading or Writing to port 6.
3) When IS FLAG is set at the IS fallmg edge, an interrupt occurs.
The followmg show; Port 6 Control/Status Register (P6CSR),
$0021
.. Bit 7 IS Read ~Only bit
~HITACHI
Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
143
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Bit 0
Bit 1
Bit 2
strobe. When cleared, P" functions as an 110 port. When set, P"
functions as an US output pin. (P" DDR is set by OSE.) This bit is
cleared during reset.
Not used.
Bit 3: Latch Enable
This register controls the input latch for Port 6 (ISLATCH).
When this bit is set to "1", the input data to port 6 will be latched
inward at the"E (P.. ) falling edge. An input latch will be canceled by
reading Port 6, which enables to latch the next data. If cleared, the
input latch remains canceled and this bit functions as a usual input
port. This bit is cleared during reset.
Bit 6: IS IRQ, Enable Input Strobe Interrupt Enable
When set, an IRQ; interrupt to the CPU occurs by setting IS
FLAG of bit 7. When cleared, the interrupt does not occur. This bit
is cleared during reset.
Bit 7: IS Flag Input Strobe Flag
This flag is set at the IS (P.. ) falling edge. This flag is for readonly. When set, the flag is cleared by reading or writing to Port 6
after reading the Port 6 Control Status Register. This bit is cleared
during reset.
Bit 4: OSS Output Strobe Select
This register initiates an output strobe (OS) from P" by reading
or writing to port 6. When cleared, OS occurs by reading Port 6.
When set, N occurs by writing to Port 6. This bit is cleared during
reset.
•
MEMORY MAP
The MPU can address up to 65k bytes. Memory map is shown in
Fig. 20. 40 addresses (SOOOO - SOO27 except $00, S02, $04, $05,
S06, S07, $18) are the internal registers as shown in Table 4.
Bit &: OSE Output Strobe Enable
This register decides the enabling or disabling of the output
HD6303Y
Port 6 Control/Status Register
Figure 18
Input Strobe Interrupt block Diagram
I!li
WlI
"RrS"
R/W
lJR"
HD6303Y
SA
MPU
Data Bus
PORT 5
~·""l
,"'
"'''MlllT
Address Bus
PORT 6
Address Bus
Figure 19 HD6303Y Opsratlng Function
~HITACHI
144
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Table 4 Internal Reg.ster
Address
00·
01
02·
03
04·
05·
OS·
07·
08
09
OA
OB
OC
OD
OE
OF
10
11
12
13
14
15
1S
17
18
19
1A
18
1C
1D
1E
1F····
20
21
22
23
24
25
26
27
•
••
•••
....
Reg.ster
Abbrev.ation
Port 1 DDR (Data D"ection Reg.ster)
Port 2 DDR
Port 1
Port 2
Port 3 DDR
Port 4 DDR
Port 3
Port 4
T.mer Control/Status Reg.ster 1
Free Runn,ng Counter (MSB)
Free Runnong Counter (lSB)
Output Compare Reg.ster 1 (MSB)
Output Compare Register 1 (lSB)
Input Capture Reg.ster (MSB)
Input Capture Reg.ster (lSB)
P1DDR
P2DDR
PORT1
PORT2
P3DDR
P4DDR
PORT3
PORT4
TCSR1
FRCH
FRCl
OCR1H
OCR1l
ICRH
ICRl
TCSR2
RMCR
TRCSR1
RDR
TOR
RP5CR
PORT5
PSDDR
PORTS
PORT7
OCR2H
OCR2l
TCSR3
TCONR
T2CNT
TRCSR2
TSTREG
P5DDR
PSCSR
Timer Control/Status Register 2
Rate/Mode Control Register
Tx/Rx Control Status Reg.ster 1
ReceIVe Data Register
Transmit Data Register
RAM/Port 5 Control Reg.ster
Port 5
Port S DDR
Port S
Port 7
Output Compare Reg.ster 2 (MSB)
Output Compare Reg.ster 2 (lSB)
T,mer Control/Status Reg.ster 3
Time Constant Register
T.mer 2 Up Counter
Tx/Rx Control Status Reg.ster 2
Test Reg.ster·
PORT 5 DDR
PORT 6 Control/Status Reg.ster
-
--
Reserved
-
-
-
-
R/W··
W
W
R/W
R/W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R
W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
W
R/W
-
-
lnol.alized value
during reset···
$FE
$00
indef.note
Indefinite
$FE
$00
,ndefinote
'ndefinite
$00
$00
$00
$FF
$FF
$00
$00
$10
$CO
$20
$00
indefinite
$F8 or $78
Indefinite
$00
indefinite
indefinite
$FF
$FF
$20
$FF
$00
$28
$00
$07
-
External address
R Read-only register, W Wnte-only register, RIW Read/Wnte register
When empty bit IS In the register, It IS set to "1"
Register for test Don't access this register
~HITACHI
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
145
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• Output Compare Register (OCR)
($OOOB, $OOOC; OCR1) ($0019. $001A: OCR2)
The output compare register is a 16-bit read/write register which
can control an output waveform. The data of OCR is always compared with the FRC.
When the data matches, output compare flag (OCF) in the timer
control/status register (TCSR) is set. Ifan output enable bit (OE) in
the TCSR2 is "I", an output level bit(OLVL) in the TCSR will be
output to bit I (OCR I) and bit 5 (OCR 2) of port 2. To control the
output level again by the next compare, the value of OCR and
OL VL should be changed. The OCR is set to SFFFF at reset. The
compare function is inhibited for a cycle just after a write to the upper byte of the OCR or FRC. This is to set the 16-bit value valid in
the counter register for compare. In addition, it is because counter
is to set $FFF8 at the next cycle of the CPU's upper byte write to
the FRC.
• For data write to the FRC or the OCR, 2-byte transfer instruction (such as STX, etc.) should be used.
$0000
Internal·
$0027
RegIster
External Memory
$0040
Space
Internal RAM
256 Bytes
$013F
External
Memory
Space
• Input Capture Register nCR) ($0000 : OOOEI
The input capture register is a 16-bit read-only register which
stores the FRC's value when external input signal transition generates an input capture pulse. Such transition is controled by input
edge bit (IEDG) in the TCSRI.
In order to input the external input signal to the edge detector, a
bit of the DDR corresponding to bit 0 of port 2 should be cleared
("0"). When an input capture pulse occurs by external input signal
transition at the next cycle of CPU's high-byte read of the ICR, the
input capture pulse will be delayed by one cycle. In order to ensure
the input capture operation, a CPU read of the ICR needs 2-byte
transfer instruction. The input pulse width should be at least 2 system cycles. This register is cleared ($0000) during reset.
$FFFF
"This mode does not
include the addresses.
$00, $02, $04, $05,
$06, $07 or $18 which
can be used externally.
Figure 20 HD6303Y Memory Map
• TIMER 1
The HD6303Y provides a 16-bit programmable timer which can
simultaneously measure an input waveform and generate two independent output waveforms. The pulse widths of both input/output
waveforms vary from microseconds to seconds.
Timer I is configured as follows (refer to Fig. 22).
ControllStatus Register 1 (8 bit)
ControllStatus Register 2 (7 bit)
Free Running Counter (16 bit)
Output Compare Register 1 (16 bit)
Output Compare Register 2 06 bit)
Input Capture Register (16 bit)
• Free-Running Counter (FRCH$OOOg:OOOAI
The key timer element is a 16-bit free-running counter driven
and incremented by system clock The counter value is readable by
software without afTecting the counter. The counter is cleared during reset.
When writing to the upper byte ($09), the CPU writes the preset
value (SFFF8) into the counter (address S09, SOA) regardless of
the write data value. But when writing to the lower byte (SOA) after
the upper byte writing, the CPU writes not only lower byte data into
lower 8 bit, but also upper byte data into higher 8 bit of the FRe.
The counter will be as follows when the CPU writes to it by double store Instructions (STD, STX, etc.)
Counter value
$FFF8
:
Timer Control/Status RegIster 1
$0008
Bit 0
OLVL 1 Output Level 1
OLVLl is transferred to port 2, bit 1 when a match occurs between the counter and the OCR 1. If bit 0 of the TCSR2 (OEI).
is set to "1", OLVLl will appear at bit 1 of port 2.
Bit 1
IEOG Input Edge
This bit determines which edge, rising or falling, of input signal of bit 0 of port 2 will trigger data transfer from the counter to
the ICR For this function, the DDR corresponding to port 2, bit
o should be cleared beforehand.
IEDG= 0, triggered on a falling edge
("High" to "Low")
IEDG= 1, triggered on a rising edge
("Low" to "High")
$5AF3
In the case of the CPU write ($ 5AF3) to the FRC
Figure 21 Counter Write Timing
• Timer Control/Status Regiater 1 (TCSR1) ($0008)
The timer controllstatus register I is an 8-bit register. All bilS are
readable and the lower 5 bilS are also writable. The upper 3 bits are
read-only which indicate the following timer status.
Bit 5
The counter value reached to SOOOO as a result of couoting-up (TOP).
Bit 6
A match has occurred between the FRC and the OCR 1
(OCFO.
Bit 7
Defined transition of the timer input signal causes the
counter to transfer its data to the ICR (ICF).
The followings are the each bit descriptions.
Bit 2
ETOI Enable Timer Overflow Interrupt
When this bit is set, an internal interrupt (IRQ,) by TO! interrupt is enabled. When cleared, the interrupt is inhibited.
Bit 3
EOCI1 Enable Output Compar. Interrupt 1
~HITACHI
146
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
When this bit is set, an internal Interrupt (IRQ,) by OCII interrupt is enabled. When cleared, the interrupt is inhibited.
Bit 4
EICI Enable Input Capture Interrupt
When this bit is set, an internal interrupt (IRQ,) by ICI interrupt is enabled. When cleared, the Interrupt is inhibIted
Bit Ii
TOF Timer Overflow Flag
This read-only bit 'is set when the counter mcrements from
SFFFF by 1. Cleared when the counter's MSB byte (S0009) IS
read by the CPU after the TCSR I read at TOF= 1.
Bit 6
OCF1 Output Compare Flag 1
This read-only bit is set when a match occurs between the
OCRl and the FRC. Cleared when writing to the OCRl ($OOOB
or SOOOC) after the TCSR 1 or TCSR2 read at OCF= 1
Bit 7
ICF Input Capture Flag
This read-only bit .s set when an input signal of port 2, bit 0
makes a transition as defined by IEDG and the FRC is transferred to the ICR. Cleared when reading the upper byte (SOOOD) of
the ICR after the TCSR 1 or TCSR2 read at ICF= 1.
• Timar Control/StatuI Register 2 (TCSR2) ($OOOF)
The timer control/status register 2 is a 7-bit register. Ali bits are
readable and the lower 4 bits are also writable But the upper 3 bits
are read-only which indicate the foliowing timer status.
A match has occurred between the FRC and the OCR2
Bit 5
(OCF2).
Bit 6
Timer ControllStatus RegIster 2
6
5
432
1
0
Bit 7
The same status flag as the ICF flag of the TCSR I, b,t 7
The foliowlngs are the each bIt descnptlons
Bit 0
OE 1 Output Enable 1
This bIt enables the OLVLl to appear at port 2, bIt 1 when a
match has occurred between the counter and the output compare register 1 When this bit IS cleared, hll 1 of port 2 wIll be an
110 port When set, It WIll be an output ofOLVLl automatlcaliy
OE2 Output Enable 2
Bit 1
Th.s bIt enables the OLVL2 to appear at port 2, bll 5 when a
match has occurred between the counter and the output compare register 2 When this b,t IS cleared, port 2, bit 5 will be an II
o port. When set, it wili be an output of OLVL2 automatlcaliy.
Bit 2
OLVL2 Output Levet 2
OLVL2 IS transferred to port 2, b,t 5 when a match has occurred between the counter and the OCR2 If bll 5 of the TCSR2
(OE2), is set to "1", OLVL2 WIll appear at port 2, bit 5.
Bit 3
EOCI2 Enable Output Compare Interrupt 2
When this bit is set, an internal interrupt (IRQ,) by OCI2 interrupt is enabled. When cleared, the Interrupt is inh.bited
Bit 4
Not used
Bit Ii
OCF2 Output Compare Flag 2
ThIS read-only bIt is set when a match has occurred between
the counter and the OCR2 Cleared when writing to Ihe OCR2
($0019 or SOOI A) after the TCSR2 read at OCF2= I
Bit 6
OCF1 Output Compare Flag 1
ICF Input Capture Flag
Bit 7
OCFI and ICF are dual addressed If which regIster, TCSRI
or TCSR2, CPU reads, it can read OCFI and ICF to b,t 6 and bit
7.
Both the TCSRI and TCSR2 WIll be cleared during reset.
(Note) If OEI or OE2 is set to "I" before the first output compare match occurs after reset restart, bit I or bit 5 of port 2
will produce "0" respectively.
F,gure 22 T,mer 1 Block Diagram
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
147
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• TIMER 2
In addition to the timer I, the HD6303Y provides an 8-bit reloadable limer, which is capable of counting the external event. The
timer 2 contains a timer output, so the MPU can generate three independent waveforms. (Refer to Fig. 23.)
The timer 2 is configured as follows:
Control/Status Register 3 (7 blls)
• 8-bit Up Counter
. Time Constant Register (8 bits)
• Tim.r 2 Up Counter (T2CNTI ($001 DI
This is an 8-bit up counter which operates with the clock decided
by CKSO and CKSI of the TCSR3. The CPU can read the value of
the counter without affecting the counter. In addition, any value
can be written to the counter by software even during counting.
The counter is cleared when a match occurs between the counter
and the TCONR or during reset.
If the write operation is made by software to the counter at the
cycle of counter clear, it does not reset the counter but put the write
data to the counter.
• Time Constant Regioter (TCONRI ($001 CI
The time constant register is an 8-bit write only register. The
data of register is always compared with the counter.
When a match has occurred, the counter match flag (CMF) of
the timer control status register 3 (TCSR3) is set and the value
selected by TOSO and TOSI of the TCSR3 will appear at port 2, bit
6. When CMF is set, the counter will be cleared simultaneously and
then start counting from $00. This enables regular interrupts and
waveform outputs without any software support. The TCONR is set
to "$FF" during reset.
• Timer Control/Status Regiater 3 (TCSR31 ($001 BI
The timer control/status register 3 is a 7-bit register. All bits are
readable and 6 bits except for CMF can be written.
The followings are each pin descriptions.
Timer ControllStatus Register 3
765
432
1
0
Bit 0
Bit 1
CKSO Input Clock Select 0
CKS1 Input Clock Select 1
Input clock to the counter is selected as shown in Table 5 depending on these two bits. When an external clock is selected,
bit 7 of port 2 will be a clock input automatically. Timer 2 detects
the rising edge of the external clock and increments the counter.
The external clock is countable up to half the frequency of the
system clock.
, - - - - Timer' FRC
Port 2
Bit 7
Port 2
BII 6
IRQ3
Figure 23 Timer 2 Block Diagram
$
148
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Table 5 Input Clock Select
Input Clock to the Counter
CKSI
CKSO
0
0
0
1
E clock/B·
1
0
E clock/12B·
1
1
External clock
E clock
These clocks come from the FRC of the timer 1 If one of these clocks is
selected as an Input clock to the up countef. the CPU should not wnte to
the FRC of the timer 1
Bit 2
Bit 3
TOSO Timer Output Select 0
TOS 1 Timer Output Select 1
When a match occurs between the counter and the TCONR
timer 2 outputs shown in Table 6 will appear at port 2, bit 6 depending on these two bits. When both TOSO and TOS I are "0",
bit 6 of port 2 will be an 1/0 port.
Table 6 T,mer 2 Output Select
TOSI
TOSO
0
0
TImer Output
TImer Output Inhibited
0
1
Toggle Output·
1
0
Output "0"
1
1
Output "I"
When 8 match occurs between the counter and the TeONR, timer 2
output level IS reversed This leads to production of 8 square wave With
50% duty to the external wIthout any software support
Bit 4
T2E Timer 2 Enable Bit
When thIs bIt is cleared, a clock input to the up counter is
inhibited and the up counter stops When set to "I", a clock
selected by CKSI and CKSO (Table 5) IS input to the up counter.
(Note) P" outputs "0" when T2E bit cleared and timer 2 set in
output enable condition by TOSI or TOSO. It also outputs
"0" when T2E bit set" I " and timer 2 set in output enable condition before the first counter match occurs.
Bit 6
Not Used.
Bit 6
ECM I Enable Counter Match Interrupt
When this bit is set, an internal interrupt (IRQ,) by CMI is
enabled. When cleared, the interrupt is inhibited.
Bit 7
CM F Counter Match Flag
This read-only bit is set when a match occurs between the up
counter and the TCONR. Cleared by writing "0" at CMF= I by
software (unable to write" I" by software).
Each bit of the TCSR3 is cleared during reset.
• SERIAL COMMUNICATION INTERFACE (SCI)
The Serial Communication Interface (SCI) in the HD6303Y
contains the following two operating modes: asynchronous mode by
the NRZ format, and clocked synchronous mode which transfers
data synchronously with the clock. In the asynchronous mode, data
length, parity bits and number of stop bits can be selected, and eight
transfer formats are provided.
The SCI consists of the following registers as shown in Fig. 24
Block Diagram.
Transmit/Receive Control Status Register I (TRCSRI)
Rate/Mode Control Register (RMCR)
Transmit/Receive Control Status Register 2 (TRCSR2)
Receive Data Register (RDR)
Recevie Shift Register
Transmit Data Register (TD R)
Transmit Shift Register
To operate the SCI, initialize the RMCR and TRCSR2, after
selecting the desirable operating mode and transfer format. Next,
set the enable bit (TE or RE) of the TRCSR 1. Operating mode and
transfer format should be changed when the enable bit (TE, RE) is
cleared. When setting the TE or RE again after changing the operating mode or transfer format, interval of more than a I-bit cycle of
the baud rate or bit rate IS necessary. If a I-bit cycle or more is not
allowed, the SCI block may not be initialized.
P" ~----------------------------------------------~
F,gure 24 SCI Block DIagram
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
149
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• Asynchronous Mode
Asynchronous mode contains 8 transfer formats as shown in
Fig.25.
Data transmission is enabled by selling TE bit of the TRCSR 1,
then port 2, bit 4 will unconditionally become a serial output independently of the corresponding DOR
To transmit data, set the desirable transmit format with RMCR
and TRCSR2 When the TE bit is set. the data can be transmitted
after transmitting the one frame of preamble ("1 ").
The conditions at this stage are as follows.
I) If the TDR is empty (TDRE=I), consecutive I's are produced to indicate the Idle state.
2) If the TOR contains data (TDRE=O), data is sent to the
Transmit Shift Register and data transmit starts.
During data transmit, a start bit of "0" IS transmitted first. Then
7-bit or 8·bit data (starts from bit 0) is transmitted. With PEN= I,
the parity bit, even or odd, selected by EOP bit is added, lastly the
stop bit (1 bit or 2 bis) is sent.
When the TDR is "empty", hardware sets TDRE flag bit. If the
CPU doesn't respond to the flag in proper timing (the TDRE is in
set condition till the next normal data transfer starts from the transmit data register to the transmit sift register), "1" is transferred instead of the start bit "0" and continues to be transferred till data is
provided to the data regISter While the TDRE is "I", "0" is not
transferred.
Data receive IS posSIble by setting RE bit This makes port 2,
bit 3 a senal input. The operation mode of data receive is decided by
the contents of the TRCSR2 and RMCR at first, and set RE bit of
TRCSRI. The first "0" (space) synchronizes the receive bit flow.
Each bit of the following data will be strobed in the middle. If a stop
bit is not ")", a framing error assumed and ORFE is set
When a framing error occurs, receive data is transferred to the
Receive Data Register and the CPU can read the error-generating
data. This makes It posSIble to detect a line break.
When PEN bit is set, the parity check is done. If the parity bit
does not match the EOP bit, a parity error occurs and the PER bit is
set, not the RDRF bit. Also, when the parity error occurs the receive data can be read just like in the case of the framing error.
The RDRF flag is set when the data is received without a framing error and a parity error.
If RDRF is still set when receiving the stop bit of the next data,
ORFE is set to indicate the overrun generation. CPU can get the receive data by reading RDR. When 7 bit data format is selected, the
8th bit of RDR IS "0".
When the CPU read the receive Data Register as a response to
RDRF flag or ORFE flag after having read TRCSR, RDRF or
ORFE is cleared.
(Note) Clock Source in Asynchronous Mode
If CCI:CCO= 10, the internal bit rate clock IS provided at P"
regardless of the values for TE or RE. Maximum clock rate is
E+16.
If both CCI and CCO are set, an external TTL compatible clock
must be connected to P" at sixteen times (l6x) the desired bit
rate, but not greater than E.
(1)
ISTARTI
7BU Data
I STOP I
(2)
I STARTI
7Blt Data
(3) ISTART I
7Bu Data
I PARITY I STOP
(4)
I STARTI
7Blt Data
IPARITY I
(5)
I START I
881t Data
(6)
ISTARTI
BSlt Data
2 STOP
(7)
ISTARll
881t Data
IPARIT3 STOP I
(8)
I STARTj
SSlt Data
IPARITYI
2STOP
I
2 STOP
I STOP
I
2 STOP
Figure 25 Asynchronous Mode Transfer Format
• Clocked SynChronous Mode
In the clocked synchronous mode, data transmit IS synchronized
with the clock pulse. The HD6303Y SCI provides functionally independent transmitter and receiver which makes full duplex operation
pOSSIble In the asynchronous mode. But In the clocked synchronous
mode an SCI clock 1/0 pin is only P", so the Simultaneous receive
and transmit operation is not available. In this mode, TE and RE
should not be In set condition (" I") simultaneously. Fig 26 gives a
synchronous clock and a data format in the clocked synchronous
mode
1) Data transmit
Data transmit IS realized by selling TE bit In the TRCSRI Port
2, bit 4 becomes an output unconditIOnally Independent of the
value of Ihe corresponding DOR
Both the RMCR and TRCSR should be set In the desirable operatmg condition for data transmit.
•
150
When an external clock Input is selected and the TORE flag is
"0", data transmit is performed from port 2, bit 4, synchronizing
with 8 clock pulses input from external to port 2, bit 2.
Data is transmilled from bit 0 and the TORE is set when the
Transmit Shift Register (TSR) is "empty". More than 9th clock
pulse of external are ignored
When data transmit is selected to the clock output, the MPU
produces transmit data and synchronous clock at TORE flag clear.
2) Data receive
Data receive IS enabled by setting RE bit. Port 2, bit 3 will be a
serial input. The operating mode of data receive is decided by the
TRCSRI and the RMCR.
If the external clock input is selected, 8 external clock pulses and
the synchronized receive data are input to port 2, bit 2 and bit 3 respectively. The MPU put receive data into the receive data shift regISter by this clock and set the RDRF flag at the termination of 8 bit
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
data receive. More than 9th clock pulse of external mput are Ig·
nored. When RDRF IS cleared, the MPU starts recelvmg the next
data instantly. So, RDRF should be cleared With P" "High".
When data receive is selected with the clock output, 8 syn·
chronous clocks are output to the external by settmg RE bit So reo
celve data should be mput from external synchronously with this
clock When the first byte data IS received, the RDRF flag IS set.
After the second byte, receive operation IS performed by sending
the synchronous clock to the external after clearing the RDRF bit.
<=====:::J1 Transmit Direction
Synchronous
clock
Data
~i'JotValtd
• Transmit data
• Receive data
IS
IS
produced from a failing edge of a synchronous clock to the next failing edge
latched at the rising edge
Figure 26 Clocked Synchronous Mode Format
• Transmit/Receive Control Status Register (TRCSR1)
($0011)
The TRCSR I is composed of 8 bits which are all readable Bits 0
to 4 are also writable. This register IS iOlllahzed to $20 during reset.
Each bit functions are as follows.
Transmit/Receive Control Status Register
$0011
Bit 0
WU Wake·up
In a typical multi·processor configuratIOn, the software pro·
tocol prOVides the destmatlOn address at the first byte of the
message. In order to make unmterested MPU Ignore the reo
maining message, a wake·up functIOn IS available By this, unm·
terested MPU can inhibit all further receive processmg 1111 the
next message starts.
Then wake·up funcllon IS tnggered by consecutive I's With I
frame length The software protocol should prOVide the Idle lime
between messages.
By settmg this bit, the MPU stops data receive 1111 the next
message The receive of consecullve "I" With one frame length
wakes up and clears thiS bit by hardware and then the MPU reo
starts receive operation. However, the RE flag should be already
set before setting this bit. In the clocked synchronous mode WU
is not available, so this bit should not be set.
Bit 1
TE Transmit Enable
When this bit IS set, transmit data will appear at port 2, bit 4
after one frame preamble m asynchronous mode, while m
clocked synchronous mode it appears Immediately. ThiS IS ex·
ecuted regardless of the value of the corresponding DDR When
TE is cleared, the serial 1/0 doesn't atTect port 2, bit 4
Bit 2
TIE Transmit Interrupt Enable
When this bit is set, an internal interrupt (IRQ) is enabled
when TDRE (bit 5) IS set. When cleared, the mterrupt IS
inhibited.
Bit 3
RE Receive Enable
When set, a signal IS mput to the receiver from port 2, bit 3
regardless of the value of the DDR. When RE IS cleared, the
senal I/O doesn't aflTect port 2, bit 3.
Bit 4
RIE Receive Interrupt Enable
When this bit is set, an internal mterrupt (IRQ,) IS enabled
when RDRF (bit 7) or ORFE (bit 6) IS set When cleared, the
interrupt is inhibited.
Bit 5
TORE Transmit Data Register Empty
TDRE IS set by hardware when the TDR is transferred to the
Transmit Shift Register 10 the asynchronous mode, while in
clocked synchronous mode when the TDSR is "empty". This
bit IS cleared by readmg the TRCSR I or TRCSR2 and writing
new transmit data to the TDR when TDRE= I TDRE IS set to
"I" dunng reset.
Bit 6
ORFE Overrun Framing Error
ORFE IS set by hardware when an overrun or a framing error
IS generated (during data· receive only). An overrun error occurs
when new receive data is ready to be transferred to the RDR
dunng RDRF still bemg set. A framing error occurs when a stop
bit IS "0". But 10 clocked synchronous mode, thiS bit is not af·
fected. This bit IS cleared by readmg the TRCSR I or TRCSR2,
and the RDR, when RDRF= I ORFE is cleared during reset.
RDRF Receive Data Register Full
Bit 7
RDRF IS set by hardware when data IS received normally and
transferred from the Receive Shift Register (RSR) to the RDR
ThiS bit IS cleared by readmg TRCSR I or TRCSR2, and the
RDR, when RDRF= I. This bit is cleared during reset.
• Transmit Rate/Mode Control Register (RMCR)
The RMCR controls the follOWing senal 1/0
Baud Rate
Data Format
. Clock source
. Port 2, Bit 2 Function
. OperatIOn Mode
All bits are readable/wntable. Bit 0 to 5 of the RMCR are cleared
dunng reset.
Transfer Rate/Mode Control Register
6
5
4
3
2
1
o
550
Bit 0
Bit 1
Bit 5
SSO
551
SS2
$0010
1
Speed Select
These bits control the baud rate used for the SCI. Table 7 lists
the available baud rates The IImer I FRC (SS2=0) and the timer 2
up counter (SS2= J) provide the '"ternal clock to the SCI. When
select 109 the timer 2 as a baud rate clock source, it functions as a
baud rate generator The timer 2 generates the baud rate listed 10
Table 8 depending on the value of the TCONR.
(Note) When operatlDg the SCI with mternal clock, do not per·
form write operation to the timer/counter which IS the
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
1 51
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Table 7 SCI Bit Tomes and Transfer Rates
(1) Asynchronous Mode
552
0
55'
0
0
0
,
,
, ,
0
,
0
XTAL
2.4576MHz
40MHz
E
6144kHz
10MHz
550
_.
1.22BBMHz
0
E-'6
208)ls/4800Baud
128 u s/J8l2 5BdUd
104 2 !Is/9600Baud
0
E -, 024
1 67rns/SOOBaud
1 024ms/976 6Baud
E- 4096
667ms/150Baud
4 096rns/244 1Baud
8333,us/1200Baud
3333ms/300Baud
E~
-
• When SS2
4,9152MHz
IS
26 ,s/38400Baud
128
16f.1 s /62500Baud
.
-
.
I~
"1", Timer 2 provides SCI .:Io.:b file haud rate
Baud R.le
0
13J,sn6800Baud
f
32 (N+ l)
•
shown as follows with the TCONR as N
mput clock frequency to the)
timer :2 counter
N::: 0"'- 2)5
f
(
(2) Clocked Synchronous Mode *
XTAL
40 MHz
60 MHz
80 MHz
SS2
SSI
SSO
E
10MHz
15 MHz
20 MHz
30 MHz
0
0
0
0
1
a
E - 2
E - 16
E - 12B
E - 512
2 tis/bIt
0
1
1
0
1
0
1
133,us/blt
107 lis/bit
853 J.(s/blt
341 ",$/M
1 tis/bit
Bl'sfblt
64 ps/bIt
0667 !,s/blt
533 Jts/blt
-
-
16 Jis/blt
128,us/blt
..
427/Js/blt
17111s/blt
'
..
..
512 tts/blt
-
120 MHz
.
256 "sIbil
·Btf rates In the case of mternal clock operation In the case of external clock operation, the external clock tS operatable up to DC - 1/2
system clock
•• The bit rate
IS
shown as follows with the TCONR as N
Bot Rate (I's/bot)
0
4 (N+l)
--y-
(
f
mput clock frequency to the)
IImer ~ counter
N o O-255
Table 8 Baud Rate and Tome Constant Regoster Example
~~AL
Baud Rate (Saud
, 10
, 50
300
600
'200
2400
4800
9600
'9200
38400
• E/8 clock
IS
24576MHz
36864MHz
40MHz
49152MHz
2' '
, 27
32'
, 91
63
31
,5
95
35'
207
103
43'
255
, 27
5'
25
,2
63
31
,5
47
23
11
5
2
7
3
,
-
0
-
-
7
3
BOMHz
70'
5' '
207
'03
5,
25
,2
,
--
a
-
Port 2, BIt 3
I
-
Input to the tuner 2 up counter and E clock otherwise
Table 9 SCI Format and Clock Source Control
CC2
CCI
CCO
Format
Mode
Clock Source
Port 2,
0
a
0
8 bIt data
Clocked Synchronous
External
a
a
0
1
1
S·blt data
Asynchronous
Internal
Input
Not Used··
a
8·b.j data
Asynchronous
Internal
Output·
0
,
1
1
a·blt data
Asynchronous
External
Input
0
a
S·btt data
Clocked Synchronous
Internal
Output
,
a
1
7-btt data
Asynchronous
1
0
7-bn data
Asynchronous
Jnternal
Jnternal
Output·
1
1
1
7-blt data
Asynchronous
E)(ternal
Input
1
BIt
2
Port 2,
BIt
4
When the TRCSR1, RE bit IS "1",
bit 3 IS used as a senal input
Not Used··
When the TRCSR1, TE bIt IS "1",
4 IS used as a serial output
bIt
• Clock output fl'!!,udlc<" oj Ihl' TRCSRI, hll Rr dnd TI
.. Not u<;cd ror the SCI
~HITACHI
152
Hitachi America, Ltd, • Hitachi Plaza· 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
clock source of the SCI.
ceo
eCl
ee2
Bit 2
Bit 3
Bit 4
Ciock Control/Format Seiect"
These bits control the data format and the clock source (refer to
Table 9).
" CCO, CCI and CC2 are cleared during reset and the MPU
goes to the clocked synchronous mode of the external ciock
operation. Then the MPU automatically set port 2, bit 2 into
the clock input state. When using port 2, bit 2 as an output
port, the DDR of port 2 should be set to "I" and CCI and
CCO to "0" and "I" respectively.
Bit 6
Bit 7
Not Used
Not Used
• Transmit/Receive Control Status Register 2 (TRCSR2)
The TRCSR2 is a 7-bit register which can select a data format in
the asynchronous mode The upper 3 bits are the same address as
the TRCSR I. Therefore, the RDRF, ORFE and TDRE can be read
by either the TRCSRI or TRCSR2. B,ts 0 to 2 of the TRCSR2 are
used for read/write. Bits 4 to 7 are used only for read.
Transmot/Receove Control Status Regoster 2
7
6
5
4
3
2
1
If this bit is "0", the stop b,t is l-bit.lf"I", the stop bit is 2-bit.
This bit is cleared dUrIng reset.
Bit 1
EOP Even/Odd Parity
This bit selects the parity generated and checked when the
PEN is "I". If this bIt is "0", the parity is even. If"I", it os odd.
This bit is cleared during reset.
PEN Parity Enable
Bit 2
This bit decides whether the parity b,t should be generated
and checked in the asynchronous mode or not. If this bit is "0",
the parity bit is neither generated nor checked If "I", ot ,s generated and checked. This bit is cleared during reset
The 3 bits above do not affect the SCI opertoon in the clocked
synchronous mode.
Bit 3
Not Used
Bit 4
PER Parity Error
This bit os set when the PEN os "\ " and a parity error occurs.
It is cleared by reading the RDR after readmg the TRCSR2,
when PER=I
Bit &
TORE
Transmot Data Reg,ster Empty
Bit 6
ORFE
Overrun/Framong Error
Bit 7
RORF
Rece,ve Data Regoster Full
" Each flag of the TORE, ORFE, and RDRF can be read from
eother the TRCSR \ or TRCSR2
0
IRDRFIOAFEITDAEI PER 1 -I PEN 1 Eopi SBLI $OOlE
Bit 0
SBL Stop Bit Length
This bit selects the stop bit length on the asynchronous mode .
•
PRECAUTION 1
In the synchronous clocked receive operation w,th clock-output,
there are three cases for clock pulse liming after RDRF clear as
shown below.
Please consider above 10 designing system, since transmitting
receiving time is not uniform.
The clock-output of case I or case 2 ,s determmed by "\" or "0"
of SCI internal operation clock of RDRF clearing cycle. In addition,
10 the case oflow voltage operation (Vee < 4.5V), the clock-output
of case I may transfer to case 3.
RDR read cycle (RDRF clearl
I·
-I
E
bit a
bot 1
clock·output
case 1
.
case 2
bit a
to
J
t,
bot
case 3
a
-I
( note)
When bit rate is
E/2,
E/16,
E/128,
E/5l2,
to = E, and
t, = 8E,
t2 = 2E.
t, = l6E.
to = 64E,
t, = 256E,
t, = l28E.
t, = 5l2E.
Diagram for Precaution 1
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
153
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• PRECAUTION 2
When transmitting Ibrough ciock-synchronous serial communication interface, TE bit should not be cleared with TORE ofTRCSR
($11) is "0".
The TORE set and clear conditions of SCI are shown as follows.
TDRE
Set condition
Clear condition
1. TOR ~ transmit
shift register
(asynchronous)
2. Transmit shift
register is empty.
(clock-synchronous)
3. RES = 0
When writing to TOR
after TRSCR read,
with TORE = 1, TORE
is cleared.
If transmit data is written to TOR, and then TE bit is cleared wilb
TORE = 0 to stop transmitting, TORE remains "0".
In Ibis case, even ifTE bit is set and transmit data is written again,
Ibe TOR data is not transmitted.
Please note that TE bit must be cleared after the last data has been
transmitted.
(This caution is not applied to asynchronous serial communication interface.)
• TIMER, SCI STATUS FLAG
Table 10 shows Ihe sel and reset condilions of each Slalus flag in
the timer 1, timer 2 and SCI.
Table 10 Timer 1, Timer 2 and SCI Slalus Flag
Set Condition
P6CSR
Timer
IS FLAG
Falling edge input to P54 (is)
ICF
FRC - ICR by Rising or Falling edge input to
P20
(Selecting with the IEDG bit)
OCFl
OCRl = FRC
OCF2
OCR2 - FRC
TOF
FRC = $FFFF + 1 cycle
CMF
T2CNT - TCONR
Clear Condition
1
Read the P6CSR then read or write the
PORT6, when IS flAG = 1
2.
m=O
1
Read the TCSR 1 or TCSR2 then ICRH,
when ICF = 1
2
m=O
1
Read the TCSRl or TCSR2 then write to
the OCR1H orOCR1L, when OCFl = 1
2
RES = 0
1
Read the TCSR2 then write to the OCR2H
or OCR2L, when OCF2 = 1
1
Timer
2
2
RES = 0
1.
Read the TCSRl then FRCH, when
TOF= 1
2.
m=O
1.
Write "0" to CMF, when CMF = 1
2
RES =
1.
Read the TRCSR 1 or TRCSR2 then RDR,
when RDRF = 1
Receive Shift Register - RDR
2
RES= 0
ORFE
1
Framing Error (Asynchronous Mode)
Stop Bit = 0
1
Read the TRCSR 1 or TRCSR2 then RDR, when
ORFE = 1
2
Overrun Error (Asynchronous Mode)
Receive Shift Register - RDR when
RDRF= 1
2 .m=O
1
Asynchronous Mode
TOR - Transmit Shift Register
Read the TRCSR 1 or TRCSR2 then write to the
TOR, when TORE = 1
2
Clocked Synchronous Mode
Transmit Shift Register IS "empty"
3.
RES'= 0
SCI
TORE
PER
Parity when PEN= 1
1.
2.
(Note) -
. Transfer
= . equal
ICRH, Upper byte of ICR
OCRl H. Upper byte of OCRl
OCR2H. Upper byte of OCR2
•
154
0
RDRF
Read the TRCSR2 then RDR, when PER= 1
m=O
OCRl L. Lower byte of OCRl
OCR2L; Lower byte of OCR2
FRCH. Upper byte of FRC
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• LOW POWER DISSIPATION MODE
The HD6303Y provides two low power dissipation modes; sleep
and standby,
This sleep mode is effective to reduce the power dissipation for a
system with no need of the HD6303Y's consecutive operation,
e_ Standby Mode
e Sleep Mode
The MPU goes to the sleep mode by SLP instruction execution,
In the sleep mode, the CPU stops its operation, while the registers'
contents are retained, In this mode, the peripherals except the CPU
such as timers, SCI, etc, continue their functions, The power dissipation of sleep-condition is one fourth that of operating condition,
The MPU returns from this mode by an interrupt, RES or
S'i'BY; it goes to the reset state by RES' and the standby mode by
"'STI!V, When the CPU acknowledges an mterrupt request, it cancels
the sleep mode, returns to the operation mode and branches to the
interrupt routine, When the CPU masks this interrupt, it cancels
the sleep mode and executes the next instruction, However, for example, if the timer I or 2 prohibits a timer interrupt, the CPU
doesn't cancel the sleep mode because of no mterrupt request.
The MPU goes to the standby mode with the"ST1!Y "Low" or
by clearing the STBY nag, In this mode, the HD6303Y stops all the
clocks and goes to the reset state, In this mode, the power dissipation is reduced to several". A, During standby, all pins, except the
power supply (Vee, Vss), the S'FIIY, RES and XTAL (which outputs "0"), go to the high impedance state In this mode, power
(Vee) is supphed to the HD6303Y, and the contents of RAM is retained, The MPU returns from this mode during reset. When the
MPU goes to the standby mode with STBY "Low", it will restart at
the timing shown in Fig, 27(a), When the MPU goes to the standby
mode by clearing the STBY flag, it will restart only by keeping the
J(ES "Low" for longer than the oscillating stabilization time, (Fig,
27(b»
Vee
\~
INMII
,
NMI
HD6303Y
ffiY
• RES
I I I1
1\
I!""'-'IIIII_---I,~:
r:-
II
I
I
I
f4 '1"
-I"
Standby Mode
o Save R89lsters
o AAM/Port 5 Control Register Set
I
-I
o Oscillator!
Start
f----*
Restart
(a) Standby Mode by STBY
ILJ
HD6303Y
,,
,,
,
,,'..!
I
Standby Mode
OSTBY FLAG
Clear
Vss
,,
,,
,
.,
I
1
o OSCillator:
Start
~
Time
: Restart
vss
(b) Standby Mode by the STBY Flag
Figure 27 Standby Mode Timing
~HITACHI
Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
155
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• TRAP FUNCTION
The CPU generates an interrupt with the highest priority
(TRAP) when fetching an undefined instruction or an instruction
from non-memory space. The TRAP prevents the system-burst
caused by noise or a program error.
a Op Coda Error
When fetching an undefined op code, the CPU saves registers as
well as a normal interrupt and branches to the TRAP (SFFEE,
SFFEF). This has the priority next to reset.
F.
..
11- - - - -
- - -
GUS
3···
IAc _
s.
I"
I"
PC
,
.. IOI'I . . . . .
- tL Of 1.1., Double AcIr:_I" .. 0
·1
I"
, ..........,. Uti
01
St_kl"o,nI.. I$I'1
01
"""" .... c.........
IPCI
0
~ -,I
a Addre•• Error
H
I N Z V C
c.n"lI,onCotleR"I... ICCRI
C..yftor._', ... Mil
When an instruction fetch is made from the address of internal
register, the MPU generaters an interrupt as well as an op code
error. But on the system with no memory in its external memory
area, this function is not applicable if an instruction fetch is made
from the external non-memory area. Addresses where an address
error occurs are from $0000 to SOO27.
ThIs function is available only for an mstruction fetch and is not
applicable to the access of normal data read/Write.
(Note) The TRAP interrupt provIdes a retry functIon differently
from other interrupts This is a program flow return to the
address where the TRAP occurs when a sequence returns
to a main routine from the TRAP mterrupt routine by
RTI. The retry can prevent the system burst caused by
noise, etc.
However, if another TRAP occurs, the program repeats
the TRAP interrupt forever, so the consideration IS necessary in programming.
•
•
0 - - - - - - -
INSTRUCTION SET
The HD6303Y provides object code upward compatIble with the
HD6801 to utihze all mstruction set of the HMCS6800. It also reduces the execution times of key instructions for throughput improvement.
Bit manipulation mstruction, change instruction of the index
register and accumulator and sleep instruction are also added
The followings are explamed here.
CPU Programming Model (refer to Fig. 28)
Addressing Mode
Accumulator and Memory Mampulation Instruction (refer to
Table 11)
New InstructIOn
Index Register and Stack Mampulatlon Instruction (refer to
Table 12)
Jump and Branch Instruction (refer to Table 13)
Condition Code RegIster Manipulation (refer to Table 14)
Op Code Map (refer to Table 15)
a Programming Model
Fig 28 depicts the HD6303Y programmmg model The double
accumulator D consists of accumulator A and B, so when using the
accumulator D, the contents of A and B are destroyed.
0..-'1_
Z.,o
In'."",
"_UCar.yl",oml.lll
Figure 28 CPU Programming Model
the address where a data IS stored. 256 bytes ($0 through $255) can
be addressed directly. Execution times can be reduced by storing
data in this area so it is recommended to make It RAM for users'
data area in configurating a system. ThIS is a 2-byte instruction,
while 3 byte with regard to AIM, OIM, ElM and TIM.
Extended Addressing
In this mode, the second byte shows the upper 8 bit of the data
stored address and the third byte the lower 8 bit. This indicates the
absolute address of 3 byte instructIon in the memory.
Indexed Addre.slng
The second byte of an instruction and the lower 8 bit of the index register are added in this mode As for AIM, OIM, ElM and
TIM, the third byte of an instructIOn and the lower 8 bits of the 10dex register are added.
ThIS carry is added to the upper 8 bit of the mdex register and
the result is used for addressmg the memory. The modified address
is retained in the temporary address register, so the contents of the
index register doesn't change. This is a 2-byte instruction except
AIM, OIM, ElM and TIM (3-byte mstruction)
Implied Addressing
An instruction itself specifies the address ThIS IS, the instruction
addresses a stack pointer, index register, etc. ThIS is a one-byte instruction.
Relative Addrassing
The second byte of an instructIon and the lower 8 bits of the program counter are added. The carry or borrow IS added to the upper
8 bIt. So addressing from -126 to + 129 byte of the current instruction is enabled. This is a 2-byte mstruction
(Note) CLI, SEI Instructions and Interrupt Operation
When accepting the IRQ at a preset timing with CLI and
SEI instructions, more than 2 cycles are necessary between the CLI and SEI instructions. For example, the following program (a)(b) don't accept the IRQ but (c) accepts it
a CPU Addre.sing Mode
The HD6303Y provIdes 7 addressing modes. The addressing
mode is determined by an instruction type and code. Tables II
through 15 show addressing modes of each instructIon with the execution times counted by the machine cycle
When the clock frequency is 4MHz, the mach me cycle tIme becomes microseconds directly
CLI
SEI
CLI
NOP
SEI
CLI
NOP
NOP
SEI
(a)
(b)
(c)
Accumulator (ACCX) Addre•• ing
Only an accumulator IS addressed and the accumulator A or B is
selected. ThIS is a one-byte instructIon.
Immediate Addres.lng
This addressing locates a data in the second byte of an instruction. However, LDS and LDX locate a data in the second and third
byte exceptionally. This addressing IS a 2 or 3-byte instruction.
The same thing can be saId to the TAP mstruction instead
of the eLI and SEI mstructlons
Direct Addre.sing
In this addressing mode, the second byte of an instruction shows
_HITACHI
156
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Table 11
Accumulator, Memory Manipulation Instructions
Condition
Addressing Mode,
Oper.tlOns
MnemOniC
. -. .
INDEx
OIRECT
IMMEO
EXTEND
IMPLIED
OP
OP
0'
- • 0' - • 0' -
"DDA
a8
2
2
98
3
2
A8
4
2
88
4
ADD8
C8
2
2
Da
3
2
E8
4
2
F8
Add Double
ADDD
C3
3
3
03
4
2 E3
5 2
F3
•
Add Accumulator,
A8A
Add With Clrrv
AOCA
89
2
2
99
3
2
A9
4
2
ADC8
C9
2
2
09
3
2
E9
2
F9
ANOA
8'
C4
2
2
94
3
2
A4
•
89
4
2
80
2
2
D.
3
2
E4
4
2
F4
BiT A
85
2
2
95
3
2
A5
4
2
BIT 8
C5
2 2 05 3 2 E5
4
2
Add
AND
ANOB
81' Tett
Cle.r
Compere
ComPl're
Accumul.tor.
Complenwnt, 1',
3
A +M- A
3
S+M--B
A
18
ClR
6F
•
3
BtM.C .....
0
3
A·M-A
4
3
8·M ..... B
85
4
3
A·M
F5
4
3
8'M
5 2 7F
4
SF
CMPa
Cl
1
1 00 -- A
1
1 00 -- 8
91
3
2
AI
4
2
81
4
3
A-M
2
01
3
2
El
4
2
Fl
4
3
8 - M
63
COM
COMA
6
2
73
6
11
1
1
43
1
1
COM8
53
1
1
A-a
EORB
CB
2
2
08
3
2
E8
4
2
6C
6
2
F8
4
3
7C
6
3
INC8
5C
1
I
R
I
I
R
I
1 R
1
I
R
1
I
R
96
3
2
A6
4
2 86
4
3
M-A
06
3
2
E6
4
2
F6
4
3
M - 8
LCNtd Double
Accumulator
lDD
CC
3
3
DC
4
2
EC
5
2
FC
5
3
M +1
MultIPly Unsigned
MUl
OR,lnciull ....
ORAA
8A
2
2 9A
3
2
AA 4
2
8A
4
3
ORA8
CA
2
2
DA 3
2
EA
2
F"
4
3
---0
8, M - A
7 1 A. 8 - A 8
A+M- A
8 +M ..... 8
PSHA
36
4
1
A -- MIP, SP - 1 ..... SP
PSHe
PULA
37
4
1
Pull oal.
J2
3
1
B - MIP, SP - 1 ..... SP
SP + 1- SP.MIP ..... A
33
3
1
SP + 1 -- SP. Mil)"'" 8
49
1
1
:)4}0; I I I I I I It4I
79
6
3
ROlA
1
59
1
RORA
46
1 1
ROR8
56
1
ROlB
Rotlte R"hl
66
ROR
(Note) Condition Code RegISter will be explained
In
6
2
76
6
3
Note of Table 14
1
•
C
b1
~)I;[};i
•
I
I
R
I
I
R
1
I
.1
bO
1 (\' I
j, I
I
I
t it I
I '\ I
I
I
;Ii I
I
I
'6 1
I
I I I I J I I jJ
CbJ
,~'
(i)
:!J;
Push Oat.
2
I
",.
2
6
I
-$ •
2
69
I
Ziro
8rench If Highe,
I,anch If < Z.,.,
Ir,neh If Lowe' 0,
SOme
aranch If
< Z.ro
'reneh If Mlnu.
....nch If Not Equal
Zero
8,.nch If Owrflow
MntmOnK:
INDEX
•
.01'-
IRA
8RN
ICC
ICS
IEQ
8GE
IGT
IHI
IlE
RELATIVE DIRECT
OP - " OP ...
20 3 2
21 3 2
24 3 2
25 3 2
27 3 2
2C 3 2
2E 3 2
22 3 2
2' 3 2
8lS
23
IlT
IMI
20 3 2
21 3 2
8NE
26
EXTEND
OP -
•
Irlneh Tnt
IMPLIED
OP -
•
No...
Non.
Coo
C-I
Z-I
N@II-O
Z + IN@ III- 0
C+Z-O
Z+IN@YI-'
C + Z· 1
3 2
N@Y-.
N-.
ZoO
3 2
C_
IIiC
21 3 2
11-0
araneh If Overflow Set
8115
IPl
ISR
JMP
JSR
29 3 2
2A 3 2
80 5 2
11-'
N-O
....nett If Plul
arllneh To Subroutine
J_
JumP To Subroutine
6E 3 2 7E 3 3
90 5 2 AD 5 2 80 6 3
•
No 0".,..10.
NOP
O.
Return From IntefNpt
RTI
38 '0 •
"Itum From
RTS
39
$WI
WAI
SlP
3' 12'
3E 9
Subroutine
Softwere Interf.!
w... for 'ntlrrupt·
Sloop
1
5
'A 4
Adv.nCft P'OI Cntr
Only
•
•,
Condlt_" Code
R.......
5 4 3 2 I 0
H I N Z y C
·• ···· ••• ·•• ·••
···· ·• ·• • ·•
······ • ·· •
·• ·· ···•• ·•• ··
······ ····
············
· ·····
·· ·· ···· ····
··• ·····• ····
·······• ······ ··•
··········
·• • • ·• ••··
-@-
5 •
1) •
INotel • WAI PUb RJW high; Addr..1 BUlgoosto FFFF; O.ta BUlgoos to the th ... ltate.
Condition Coda Rlglster will be •• pllinod .n Note of Table 14
$
160
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y. HD63A03Y, HD63B03Y, HD63C03Y
Table 14 Condition Code Register Manipulation Instructions
ddr... .ngMode1
()perMtOnl
C...,
MnemonIC
c.r,V
Accumulator It. ...... CeA
ClC
Cli
ClV
SEC
SEI
SEV
T .. P
eeR . . . Accumul'tor A
TP"
Ctter Int.rrupt Milk
elMr Overftow
Set C.f'y
Set Interrupt Milk
5I.O..."low
Condition Code A.. ".e,
- •
1
1
OP
DC
OE
,
1
1
1
1
1
1
1
0"
00
OF
OB
06
01
1
R
S
···· ·
· ···
S
--- @ ---
• I•
CONDITION CODE SYMBOLS
H
Half~rry from bit 3 to bit 4
I
Interrupt mask
Number of Program By tes
Arithmetic Plus
Arithmetic Minus
N
Negative (sign bltl
Z
V
Zero (bylel
Overflow. 2's complement
•
Boolean AND
+
C
R
Carry/Borrow from Ito bit 7
Reset Always
800lean Inclusive OR
800lean Exclusive OR
S
Set Always
Set If true after test or clear
Not Affected
e
t
M
Complement of M
Transfer Into
OBit = Zero
00 Byte = Zero
(Note)
•
Condition Code Register Notes. (Bit set if test
(i)
(2)
(BII VI
(B;I
CI
@
@
(81t
(Bit
IBlt
(Bit
(Bit
C)
V)
V)
V)
N)
(5)
(6)
(i)
Test: Result
Tes,. Result
@
(9)
(AIIB'II
(iQ)
(,i)
(All B,II
(B,I
II
(B" CI
IS
0
C
S
A_ eCR
OP Operation Code (Hexadecimal!
Number of MCU Cvcles
MSp Contents of memory location pOinted by Stack POIOter
11
1
V
R
eeR -. A
LEGEND
2
Z
R
1- C
1-1
1 -V
1
1
1
3
N
·· · ·· ·· ·· ·
·· ·· ·· ·· · ·
· ····
O-C
0-1
O-V
,1
•I
5
H
Boole." Oper.hon
IMPLIED
true and cleared otherwise)
= 10000000'
~
00000000'
Test: 8CC Character of hlgh-order byte greater than 10' INot cleared If previously set)
Test: Operand = 10000000 PfiOr to execution'
Test. Operand = 01111111 prior to execution'
Test. Set equal to Ne C = 1 after the execution of instructions
Test Result less than zero' (BIt 15=1)
Load Condition Code Register from Stack
Set when Interrupt occurs If previously set, a Non·Maskable Interrupt IS required to eXit the walt state
Set according to the contents of Accumulator A
Result of Multiplication Bit 7:Q., IACCS)
Table 15 OP-Code Map
OP
CODE
~ /°"
0000
LO
0000
0001
0010
0011
0100
0101
0110
0111
1000
0
I
2
3
•
NOP
0001
1
SBA
C'"
00.0
2
BRA
BRN
BH'
/" /
/ " / " BLS
LSRO / " acc
ASLO
TAP
TPA
.NX
'001 9 OEX
1010 A CLV
1011 B SEV
1100 C CLC
I1Dl 0 SEC
I1ID E eLi
SEt
I
6
7
•
'm1 'F
0
BCS
/
BNE
T"B
BEQ
TBA
XGOX BVC
BVS
0,0."
SLP
BPL
BMI
.....
/
/"
/"
/"
I
UNDEFINED OP eOOE
BGE
BLT
8GT
8LE
2
0011
3
TSX
INS
PUL ..
PULB
DES
TXS
PSH ..
PSHB
PULX
RTS
.. BX
RT.
PSHX
MUL
w..,
a
INO
--
0110
l~
1
6
1
"CC
A
.. CC
0100
D'O'
I
•
0.11
•
AceA or SP
IMM
'000
I
I
AceB or X
OIR liND
I
EXT
IMM
100.
j
j
1100
9
l
1011
B
81
10'0
A
I
NEG
COM
LSR
I
SUBO
E'M
/-1
"SR
"SL
ROL
DEC
liD.
I
"'0
I
I
1111
F
E
0
EXT
0
I
2
ADDD
3
•
ST ..
I
6
STA
/1
7
•t
EOR
~J
"DC
ORA
ADO
TIM
INC
TST
A
B
CPX
~-JMP---
eLR
I
OIR liND
.. NO
BIT
LOA
ROR
• I
C
I
I
I
SUB
CMP
SBC
A.M
D.M
--I
SWI
3
O.R
6
I
7
~SR_i_
LOO
C
~D_ _ _ _
--L05---- ~L __LOX
E
JSR
STS
.--------!
8 I --'---.L.. A I
0
B
...------1
C I
STX
D
I
E
F
I
F
I2:':J
• Only each instructions of AIM, OIM, ElM, TIM
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
161
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
and port states.
• CPU OPERATION
• CPU Instruction Flow
When operating, the CPU fetches an instrution from a memory
and executes the required function. This sequence starts with RES
cancel and repeats itself limitlessly if not affected by a special instruction or a control signal. SWI, RTI, WAI and SLP instructions
change this operation, while NMI, IRQ., IRQ" IRQ" HALT and
STBY control it. Fig. 29 gives the CPU mode transition and Fig. 30
the CPU system flow chart. Table 16 shows CPU operating states
• Operation at Each Instruction Cycle
Table 17 shows the operation at each instruction cycle. By the
pipeline control of the HD6303Y, MULT, PUL, DAA and XGDX
instructions, etc. prefetch the next instruction. So attention is necessary to the counting of the instruction cycles because it is different
from the usual one - from op code fetch to the next instructIOn op
code.
FIgure 29 CPU Operation Mode Transition
Table 16 CPU OperatIon State and Port, Bus, Control SIgnal State
Reset
STBY'3
HALT
Sleep
H
T
T
T
T
Keep
H
Keep
°0-°7
T
T
T
T
As -A'6
Port 5
H
T
T
T
T
Keep
H
Keep
Port 6
T
T
Keep
Keep
Control SIgnal
'I
T
"
Port
Ao-A7
Port 2
"
'2
-3
E pin goes to high Impedance state
•
162
'I
lIIi, Wli, RtW, IiIf = H, BA = l
lID, Wli, RIW = T, UIf. BA = H
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
on
'--
::I:
s:<>
pc .•
PC-'
r VECTORING
:r.
»
3
CD
::::!.
<>
.?'
!::
?-
•
(Note) 1. The program sequence will come to the
;!;
;;;
<>
:r.
"tJ
i»
Refer to "FUNCTIONAL PIN DESCRIPTION" for more
details of interrupts
N
."
•
N
0
0
0
::r:
~~
t:J
en
~O
w
~
o
~ 1:
•
CD
w
::::!.
en
0-
~
."
:::l
5"
::r:
(")
»
t:J
en
co
9'
w
to
o
w
TN
c»
<0
•
t<
~
::r:
~
01
00
t:J
en
'P
00
w
0
0
t1
en
w
~
1:
"J]-
.".
0
0
::r:
o
w
~.
jiJ
RES start from
any place of the flow dUring RES. When STBY=O. the
sequence will go into the standby mode regardless of the CPU
condition.
w
Figure 30 HD6303Y System Flow Chart
()
o
t<
w
0>
W
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Table 17 Cycle-by-Cycle Operation
Address Mode &
InstructIons
Data Sus
Address Bus
IMMEDIATE
ADC
AND
CMP
LOA
SBC
ADDD
LDD
LOX
ADD
BIT
EOR
ORA
SUB
CPX
LOS
SUBD
1
2
Op Code Address + 1
Op Code Address + 2
1
1
0
0
1
1
1
0
Operand Data
Next Op Code
1
2
3
Op Code Address + 1
Op Code Address + 2
Op Code Address + 3
1
1
1
0
0
0
1
1
1
1
1
0
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
1
2
Op Code Address + 1
Address of Operand
Op Code Address+2
1
1
Address of Operand (LSB)
Operand Data
Next Op Code
2
3
DIRECT
ADC
AND
CMP
LOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
3
3
a
a
a
a
1
Op Code Address + 1
1
0
1
1
Destlnatoon Address
0
1
0
1
Accumulator Data
2
DestInatIon Address
Op Code Address + 2
1
a
1
0
Next Op Code
3
~A~D~D~D~~C~P~X~----- -----+--71~~O~p~C~0~d~e~A~dd~r~e~ss~+-71----4-~1--~~O~4-~1--+--1~~~A~d~d~re~s~s~oTf~O~p-e-ra-n"d~(~L~S~B).-
3
LDD
LOX
LOS
SUBD
--S~T~D---'S~T~S'-
I
2
43
4
Address of Operand
Address of Operand + 1
Op Code Address+2
1
l
1
a
a
1
1
1
1
1
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
---l---------~1~4-;O~P~C~0~d~e~A;d7d~r=es~s~+~1~---+--71~~~O.-+--71--~~1~4-~D~es~t~,n~a7tl~on~A~d~d~re~s~s-"(L~S"'B~)0
a
2
Destonatlon Address
a
1
a
1
RegIster Data (MSB)
a
1
a
1
RegIster Data (LSB)
3
Destonatlon Address + 1
____+-_-c4c--+ Op Code Address + 2
1
a
1
a
Next Op Code
JSR------ 1
-;O:<'p::--;:Cc:o-d::.=-e·A:.::d.::.d'cre.::s=-s7+..;:1----+---i1--+-~O--t-·1c-+-i-1-+-'JTu'=m::p~Aid:'-d7r:=:e:::ss:"-(L"S;;;B")---STX
4
5
I
2
3
4
5
2
3
FFFF
Stack POInter
Stack POInter - 1
Jump Address
Op Code Address+ 1
Op Code Address + 2
Address of Operand
2
3
4
5
6
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address + 3
----1"----,:
4
1
a
a
1
1
1
1
1
1
1
0
a
0
a
1
a
0
1
1
1
1
1
1
1
0
1
1
1
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Forst Subroutone Op Code
Immediate Data
Address of Operand (LSB)
Operand Data
1
1
1
1
Address of Operand (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
-.~.--,~c_--+----~il--_4~--+-O~P_~C~0::d~e~A~d~d~re~s::s~+~3~--_+~1~4-~0c_+__17_+_70--+-N;=e:=:x~t~O~P~C~0~de~-------AIM
ElM
I
1
Dp Code Address + 1
1
a
1
1
ImmedIate Data
OIM
6
1
1
1
a
1
a
a
1
1
a
1
1
1
a
1
a
(Contonued)
~HITACHI
164
Hitachi America, Ltd_ • Hitachi Plaza • 2000 Sierra Point Pkwy_ • Brisbane, CA 94005-1819. (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Address Bus
Data Bus
INDEXED
1
JMP
3
2
3
AOC
AND
CMP
LOA
SBC
TST
STA
ADO
BIT
EOR
ORA
SUB
1
2
4
1
4
1.000
CPX
LOS
SUBO
LDO
LOX
STD
STX
STS
5
3
4
1
2
3
4
5
2
3
4
5
1
JSR
5
ASR
DEC
LSR
ROL
2
3
4
5
1
6
2
3
4
5
6
1
TIM
5
2
3
4
5
1
CLR
5
AIM
OIM
2
1
5
ASL
COM
INC
NEG
ROR
3
4
2
3
4
5
1
2
ElM
7
3
4
5
6
7
Op Code Address + 1
FFFF
Jump Address
Op Code Address + 1
FFFF
IX + Offset
Op Code Address + 2
1
0
1
1
1
1
1
1
1
0
0
1
0
0
1
1
1
Op Code Address + 1
FFFF
IX + Offset
Op Code Address + 2
Op Code Address + 1
FFFF
IX + Offset
IX + Offset + 1
Op Code Address + 2
Op Code Address + 1
FFFF
IX+Offset
IX + Offset + 1
Op Code Address + 2
Op Code Address + 1
FFFF
Stack Pointer
Stack Poonter - 1
IX + Offset
Op Code Address + 1
FFFF
IX + Offset
FFFF
IX + Ollset
OP Code Address+ 2
Op Code Address + 1
Op Code Address + 2
FFFF
IX + Offset
Op Code Address + 3
Op Code Address + 1
FFFF
IX+OIIset
IX+OIIset
Op Code Address + 2
Op Code Address + 1
Op Code Address+2
FFFF
IX+OIIset
FFFF
IX + Ollset
Op Code Address + 3
1
1
0
1
1
•
1
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
0
0
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
0
0
0
1
1
0
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
Offset
Restart Address (LSB)
First Op Code 01 Jump RoutIne
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Accumulator Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data (MSB)
Operand Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
RegIster Data (MSB)
RegIster Data (LSB)
Next Op Code
Offset
Restart Address (LSB)
Return Address (LSB)
Return Address (MSB)
Forst Subroutone Op Code
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
ImmedIate Data
Offset
Restart Address (LSB)
Operand Data
Next Op Code
Offset
Restart Address (LSB)
Operand Data
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
1
00
1
0
0
0
1
1
1
0
1
1
1
1
1
0
1
0
1
1
0
1
0
Next Op Code
ImmedIate Data
Offset
Restart Address (LSB)
Operand Data
Restart Address (LSB)
New Operand Data
Next Op Code
(Contonued)
1
1
1
1
1
1
0
1
1
1
1
1
1
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
165
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Address Mode 80
Instructions
Address Bus
EXTEND
JMP
3
1
2
3
ADC
AND
CMP
lOA
SBC
STA
ADD
BIT
EOR
ORA
SUB
TST
4
4
ADDD
CPX
lOS
SUBD
lDD
lOX
5
1
2
3
4
1
2
3
4
1
2
3
4
5
STD
STX
STS
5
1
2
3
4
5
JSR
6
1
2
3
4
5
6
ASl
COM
INC
NEG
ROR
ASR
DEC
lSR
ROl
6
1
2
3
4
5
6
ClR
1
2
5
3
4
5
Op Code Address+ 1
Op Code Address+2
Jump Address
Op Code Address + 1
Op Code Address+ 2
Address of Operand
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Destination Address
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
Op Code Address+ 3
Op Code Address + 1
Op Code Address + 2
Destination Address
Destination Address + 1
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
FFFF
Stack POinter
Stack POinter - 1
Jump Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
FFFF
Address of Operand
Op Code Address + 3
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand
Op Code Address + 3
Data Bus
1
1
1
1
1
1
1
a
a
a
a
0
a
a
1
1
-0-
a
1
1
1
1
1
1
1
1
1
a
a
1
1
1
1
a
0
1
1
1
1
1
0
a
a
a
0
a
a
0
a
a
1
1
a
a
a
1
1
1
0
0
a
a
1
1
1
1
1
1
a
a
1
a
1
1
1
1
1
1
1
1
1
a
1
1
1
1
1
1
1
1
a
a
1
1
1
1
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
Jump Address (MSB)
Jump Address (lSB)
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
Next Op Code
1
1
a
1
1
1
a
1
1
1
a
1
1
1
1
a
1
1
1
1
a
1
1
1
1
1
a
1
1
1
1
1
0
1
1
1
1
a
i
Destination Address (MSB)
Destination Address (lSB)
Accumulator Data
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data (MSB)
Operand Data (lSB)
Next Op Code
Destination Address (MSB)
Destination Address (lSB)
Register Data (MSB)
Register Data (lSB)
Next Op Code
Jump Address (MSB)
Jump Address (lSB)
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
First Subroutine Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
Restart Address (lSB)
New Operand Data
Next Op Code
Address of Operand (MSB)
Address of Operand (lSB)
Operand Data
00
Next Op Code
(Continued)
~HITACHI
166
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Address Mode &
InstructIons
IMPLIED
ABA
ASL
ASR
CLC
CLR
COM
DES
INC
INX
lSRD
ROR
SBA
SEI
TAB
TBA
TST
TXS
ABX
ASLD
CBA
CLI
CLV
DEC
DEX
INS
lSR
ROl
NOP
SEC
SEV
TAP
TPA
TSX
011.11.
XGDX
PULA
Address Bus
1
Op Code Address + 1
1
0
1
0
Next Op Code
1
2
1
2
Op Code Address + 1
FFFF
Op Code Address + 1
FFFF
Stack POInter + 1
Op Code Address + 1
FFFF
Stack Poonter
Op Code Address + 1
Op Code Address + 1
FFFF
Stack POInter + 1
Stack POInter + 2
Op Code Address + 1
FFFF
Stack Poonter
Stack POInter - 1
Op Code Address + 1
Op Code Address + 1
FFFF
Stack Poonter + 1
Stack Poonter + 2
Return Address
Op Code Address + ,
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
Next Op Code
Restart Address (LSB)
Next Op Code
Restart Address (LSB)
Data from Stack
Next Op Code
Restart Address (LSB)
Accumulator Data
Next Op Code
Next Op Code
Restart Address (lSB)
Data from Stack (MSB)
Data from Stack (lSB)
Next Op Code
Restart Address (lSB)
Index RegIster (lSB)
Index RegIster (MSB)
Next Op Code
Next Op Code
Restart Address (lSB)
Return Address (MSB)
Return Address (lSB)
Forst op Code of Return RoutIne
Next Op Code
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
Restart Address (lSB)
1
2
PUlB
3
3
PSHA
Data Bus
PSHB
4
PUlX
4
1
2
3
4
1
2
3
4
,
PSHX
2
5
3
4
5
1
2
RTS
5
3
4
5
1
2
MUl
7
3
4
5
6
7
0
1
1
1
1
1
1
,
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
1
1
0
0
1
0
0
0
1
1
1
0
0
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
0
U
1
1
1
1
1
1
(Conttnued)
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
167
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
Address Mode &
Instructions
Date Bus
Address Bus
IMPLIED
WAI
1
2
Op Code Address + 1
FFFF
Stack POInter
Star.k POinter - 1
Stack POinter - 2
Stack POInter - 3
Stack POlnter-4
Stack POinter - 5
Stack POinter - 6
Op Code Address + 1
FFFF
Stack POinter + 1
Stack POInter + 2
Stack POinter + 3
Stack POinter + 4
3
4
9
5
6
7
8
9
RTI
1
2
3
4
5
6
10
7
Stack POinter + 5
Stack POInter + 6
Stack POinter + 7
Return Address
Op Code Address + 1
FFFF
Stack POInter
Stack POInter - 1
Stack POInter - 2
Stack POinter - 3
Stack POinter - 4
Stack POinter - 5
Stack POinter - 6
Vector Address FFFA
Vector Address FFFB
Address of SWI Routine
Op Code Address+ 1
FFFF
10
1
SWI
2
3
4
5
6
7
8
9
12
10
11
12
1
2
SlP
I
3
RELATIVE
BCC
BEO
BGT
BlE
BLI
BNE
BRA
BVC
BSR
BCS
BGE
BHI
BlS
BMT
BPl
BRN
BVS
1
2
3
Op Code Address + 1
FFFF
Test~' 1
J Branch Address
I Op Code Address +1 Test ~ '0
3
1
I
2
5
I
I
I
a
a
a
a
a
a
a
a
a
3
4
5
I
Op COdeAddress + 1
FFFF
Stack POinter
Stack POinter - 1
Branch Address
a
a
a
a
a
a
a
a
a
a
a
1
1
1
1
a
1
1
I a
I
i
I
I
I
1
1
1
1
1
1
1
1
1
1
1
1
1
a
1
1
1
1
1
1
1
1
1
1
1
a
1
1
1
1
!
I
j
J
1
1
1
1
1
1
1
1
I
a
1
1
---t
1
1
1
1
1
1
1
1
1
1
I
f------"
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
a
0
I I
FFFF
Op Code Address + 1
4
1
a
a
a
a
a
a
a
Sleep
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
4
1
1
1
1
0
0
0
0
0
0
0
8
9
1
1
0
1
1
!
1
1
a
1
1
1
1
1
a
1
Next Op Code
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
Index RegIster (lSB)
Index RegIster (MSB)
Accumulator A
Accumulator B
CondItIonal Code RegIster
Next Op Code
Restart Address (LSB)
CondItIonal Code RegIster
Accumulator B
Accumulator A
Index RegIster (MSB)
Index RegIster (lSB)
Return Address (MSB)
Return Address (lSB)
First Op Code of Return RoutIne
Next Op Code
Restart Address (lSB)
Return Address (lSB)
Return Address (MSB)
Index RegIster (lSB)
Index RegIster (MSB)
Accumulator A
Accumulator B
CondItIonal Code RegIster
Address of SWI Routine (MSB)
Address of SWI Routine (lSB)
First Op Code of SWI Routine
Next Op Code
Restart Address (lSB)
i
1
Restart Address (lSB)
Next Op Code
Branch Offset
Restart Address (lSB)
First Op Code of Branch RoutlOe
Next Op Code
-,~~
1
0
1
1
1
1
1
1
1
a
a
1
1
1
0
1
0
I aa
I
i 1
!
Offset
Restart Address (lSB)
Return Address (lSBI
Return Address (MSBI
First Op Code of Subroutine
,
~HITACHI
168
Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6303Y, HD63A03Y, HD63B03Y, HD63C03Y
• WARNING CONCERNING THE BOARD DESIGN OF
OSCILLATION CIRCUIT
When designing a board, note that crosstalk may disturb the
normal oscillation if signal lines are placed near the oscillation
circuit as shown in Figure 31. Place the crystal and C L as close
to the HD6303Y as possible.
Cl
J7i
1-1~-'-ll XTA l
r-ll-- (shown III Figure 35.)
Therefore, after power starts up, the LSI conditions such as its 1/
o ports and operating mode, are unstable. Fix the level of I/O ports
by means of an external cirCUIt to determine the level for system
operatIOn dunng the OSCIllator stablhzation hme.
in
Recommended method
Figure 34 Program to wait for interrupt
internal reset
signal
RES pin
Figure 35
RES circuit
~HITACHI
170
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
HD6305X2,HD63A05X2,HD63B05X2
CMOS MCU (Microcomputer Unit)
The HD6305X2 is memory expandable versions of the
HD6305XO, which is CMOS 8-bit single chip microcomputer. A
CPU, a clock generator, a 128-byte RAM, I/O terminals, two
timers and a serial communIcation interface (SCI) are built in the
HD6305X2.
The HD6305X2 has the same functions as the HD6305XO's
except for the number of I/O terminals. The HD6305X2 is a
microcomputer unit which includes no ROM and its memory
space is expandable to 16k bytes externally.
•
•
•
•
•
•
•
•
•
•
HARDWARE FEATURES
8-bit based MCU
128-bytes of RAM
A total of 31 terminals, Including 24 I/O's, 7 Inputs
Two timers
- 8-bit timer with a 7-bit prescaler (programmable prescaler,
event counter)
- 15-bit timer (commonly used with the SCI clock divider)
On-chip serial interlace circuit (synchronized with clock)
Six interrupts (two external, two timer, one serial and one
soltware)
Low power dissipation modes
- Wait ..... In this mode, the clock oscillator is on and the
CPU halts but the timer/serial/interrupt lunction is operable.
- Stop ..... In this mode, the clock stops but the RAM data,
I/O status and registers are held.
- Standby .. In this mode, the clock stops, the RAM data is
held, and the other internal condition IS reset.
Minimum instruction cycle time
-HD6305X2 ...1 I's (I = 1 MHz)
-HD63A05X2 ... 0.67 I's (I = 1.5 MHz)
-HD63B05X2 ... 0.5 I' (I = 2 MHz)
Wide operating range
Vcc = 3 to 6V (I = 0.1 to 0.5 MHz)
-HD6305X2 .. I =0.1 to 1 MHz (Vcc =5V ± 10%)
-HD63A05X2. 1= 0.1 to 1.5 MHz (Vcc=5V±10%)
-HD63B05X2. 1=0.1 to 2 MHz (Vcc=5V±10%)
HD6305X2P, HD63A05X2P,
HD63B05X2P
(DP-64S)
HD6305X2F, HD63A05X2F,
HD63B05X2F
(FP-64)
•
•
•
•
•
•
•
•
•
•
SOFTWARE FEATURES
Similar to HD6800
Byte efficient instruction set
Powerlul bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable lor all RAM bits and all I/O terminals)
A variety 01 Interrupt operations
Index addreSSing mode uselul lor table processing
A variety of conditional branch instructions
Ten powerlul addressing modes
All addreSSing modes adaptable to RAM, and I/O instructions
Three new instructions, STOP, WAIT and DAA, added to the
HD6805 lamily instruction set
• PROGRAM DEVELOPMENT SUPPORT TOOLS
• Cross assembler software lor use With IBM PCs and compatibles
• In circuit emUlator lor use with IBM PCs and compatibles
~HITACHI
Hitachi America, Ltd.' Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
171
HD6305X2, HD63A05X2, HD63B05X2
• PIN ARRANGEMENT
• HD6305X2p, HD63A05X2p, HD63B05X2P
a
• HD6305X2F, HD63A05X2F, HD63B05X2F
DATAo
DATA,
DATA,
DATA,
DATA.
DATA,
DATA.
DATA,
TIMER
:;:
.... .;..... .;....
o
o
0
E
R/W
ADR,)
A/W
ADA,)
ADR"
ADA'2
ADR!,
B,
B,
B,
Bo
ADRlo
ADA"
ADR,
ADR,
ADR,
ADR,
ADR.
ADR.
ADR,
ADR,
ADR,
ADRo
ADR,o
C,/Tx
0,
C./R.
C,/CK
C.
C,
C,
C,
Co
D./INT,
0,
0,
0,
0,
0,
ADA,
ADA,
ADA,
B,
ADA6
B.
ADA"
BJ
ADA.
B,
ADR)
B,
ADR2
ADAl
AOR o
C1 /Tx
0,
Vee
(Top Viewl
(Top Viewl
.HITACHI
172
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
•
BLOCK DIAGRAM
XTA.l Ex TAL
Rlii
TIMER
Accumulator
A
110
Stack
Pointer
Bo
e,
e,
e,
e.
Port B
-
~E
IZI~
..
110
Terminals
.
~s.
a.-
~
.
~
0:
.a:
:;
og
Otloo J
Control
Condition Code
Register
CC
A,
0,
CPU
Index
Register
Port A
0,
O.
0,
0,
0,
CPU
Port 0
Input
Terminals
$P
Program
Counter
"High" PCH
Program
'LU
.
';
Counter
"Low" pel
8,
CIl
;
IZI
C.
C,
C,
C,
Port C
110
Term,nals
Cola
c.
e.,tRIl
C,(T-
• No IOternal ROM In HD6305X2
DATA,
.:::
DATA,
.3'"
DATA,
DATA,
,
.
-
IZI·
Senal
Data
Register
DATA,
DATA.
DATAl
DATAo
Senal
Status
Register
~HITACHI
Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
173
HD6305X2, HD63A05X2, HD63B05X2
• ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 - +7.0
V
Input Voltage
V ,n
-0.3 - Vee + 0.3
V
Top,
0-+70
Item
Operating Temperature
T stg
Storage Temperature
[NOTE)
°c
--
~-
--~--------
°c
-55 - +150
These products have a protection Circuit 10 the,r Input terminals agamst high electrostatic voltage or high electriC fields
Notwithstanding,
be careful not to apply any voltage higher than the absolute maximum rating to these high Input Impedance CircUits To assure normal
operation, we recommended V in • Vout; Vss ~ (V in or V out ) ~ Vee
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee
= 5.0V±10%, Vss = GNO, Ta = 0 -
Item
Input "High" Voltage
--
EXTAL
min
typ
max
~5
Vee xO.7
-
V ec +0.3
Test Cond ition
Symbol
RES,STBY
+70°C, unless otherwISe noted. I
V IH
Other Inputs
Input "Low" Voltage
2.0
All Inputs
V IL
Output "High" Voltage All Outputs
-0.3
V OH
Output "Low" Voltage
All Outputs
TIMER,INT,
0, - O"STBY
illd
Three·state Current
Ao-A"Bo-B"
Co - C" ADRo - ADRI3",
OATAo- DATA 7 , E",R/W"
ilTSoi
VOL
0.8
V
V
c----V
-
-
1.0
JlA
-
-
1.0
JlA
Operating
-
5
10
mA
Wait
-
2
5
mA
-
2
10
JlA
2
10
-
-
12
JlA
pF
--
Stop
Vin
= 0.5'~ Vee-0.5
= lMHz"""
lec
f
Cin
f - lMHz, Vin
Standby
Input Capacitance
V
Vee+0 .3
~-~ f - - - -
2.4
IOH = -200JlA
f--C----------- -.
IOH = -10JlA
Vee- 0 .7
- - - - - c------ c----.
IOL = 1.6mA
0.55
Input Leakage Current
Current Dissipation""
Unit
All Terminals
= OV
.-
.. Only at standby
•• VIHmln= VCC-1 OV, VILmax ""'cav
... The value at f =xMHz IS given by uSing
Ice U=xMHzl = Icc (f= lMHzl xx
•
AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = GNO, T. = 0 ~ +70°C, unless otherwise noted.)
Item
Symbol
Cycle Time
t cvc
Enable Rise Time
Ie,
Enable Fall Time
tEl
Enable Pulse Width("High" Level)
PW EH
Enable Pulse Width("Low" Level)
PW EL
Address Delay Time
Address Hold Tome
Data Delay Time
tAD
tA~-
---_.
tow_
Data Hold Time (Write)
tHW
Data Set·up Time (Read)
tOSA
Data Hold Time (Read)
tHA
Test
Condition
HD6305X2
min
typ
min
typ
0.666
-
1
-
10
-
-
20
-
-
20
-
-
-
300
-
-,,-
f - - f - - - ----
f--:.,-450
450
Fig 1
-
f--
,,-- i----
--- f-----
-----
40
250
-._-
~
-- i - - -
- - - -=-+200
I 40
1--:;;-:--- -_.
80
f----
0
-
HD63B05X2
HD63A05X2
max
-
-"._---
---20
~--
30
60
0
~-
~-
-
mm
-~- ,Q~20
300
--__30
max
~---
--190
-
--
220
--220
-_._-
rio
160
-
-
20
I---
50
0
typ
max
---=- r.-1L
10
-_.-'-- _IJ.~
-
-
20
~
ns
ns
ns
c---- - - c--180
ns
ns
120
ns
. - - - ~ns
ns
-
~HITACHI
174
Unit
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
• PORT TIMING (Vee = 5.0V±10%, Vss = GND, Ta = 0 ~ +70°C, unless otherwise noted.)
Item
Symbol
Port Data Set·up Time
(Port A, B, C, D)
-
--
Port Data Hold Time
(Port A, B, C, D)
.--"--Port Data Delay Time
(Port A, B, C)
-----
•
--"."
200
tpos
-----_.-
-
HD6305X2
Test
Condition f----min
typ
max
_.-
- f-------- -
Fig. 2
c---
-------
1-------
200
tpOH
------
-----~-
tpow
Flg.3
-
----
-~--
-
-
-
300
min
HD63A05X2
typ
max
min
HD63B05X2 '
typ
max
200
200
----- - - - f----------- - - - - 1----200
200
-
-
-
300
-
-
-
--
Unit
ns
--_._--
-
ns
300
ns
CONTROL SIGNAL TIMING (Vee = 5,OV±10%, Vss = GND, Ta = 0 - +70°C, unless otherwise noted.)
Symb ol
Item
Test
Condition
HD~395X2
HD63A05X2
HD63B05X2
Il--min
typ-- -m-ax--+-m-In--'-ty--p-'--m-a-x--+--m-,--n---'--t-y-p-m-a-x
INTPulseWI~~~--------r---------- ~---Iteye
_
_
teye
D~~ ~ ~ :;~ - c--=-:~
--'-~~~~~"-W~dt~=~=-_-_-J :::~_
RES ~ulse ,:vv--'dth _ _ _ _ ~"-Control Set-up Time
~'tcs
teye
~--.
-
ns
r~
-,--
-
-
-
-
ns
5
__5__+-_-_+_ 5
250
- -- 250
250
ns
--~teye
t
tcyc
ns
Timer Pulse Width
, t TWL
+250
+c;~O
+200
- - - - - - - - - - - -------1----+----------- +-----t---j---'-""''-+---t----+-=-''-+
ms
- _-_+-_
20_i---_
F '_9_5._F_,g_2_0'+---:-::--+_-_t---2
Oscillation Start Time (Crystal)_ I_t,_o_sc_--+_
_t----:-c_t--_--+
_20
_+-----::-:--t
_O
Reset Delay Time
i tRHL
Fig. 19
80
80
ms
80
tcyc
Fig 5
-t-
• C L = 22pF ±20%, Rs = 60n max.
• SCI TIMING (Vee = 5.0V±10%, Vss= GND, Ta = 0 ~ +70°C, unless otherwise noted.)
Item
Clock Cycle
Data Output Delay Time
Data Set-up Time
Data Hold Time
Symbol
Test
Condition
1
tscyc
tTXD
tSRX
tHRX
min
Fig 6,
Flg.7
-
200
100
HD63A05X2
HD6305X2
typ
typ
max
max
min
21845
32768 0.67
250
250
-
-
-
-
200
100
-
-
min
0.5
-
200
100
HD63B05X2
typ
max
-
16384
250
-
-
-
Unit
j.lS
ns
ns
ns
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
175
HD6305X2, HD63A05X2, HD63B05X2
14-.---------tc.,.c---------~
E
\foo---PW"
-
tEr
24V
Ao - Al1
R(W
o 6V
MCU Write
DATAo - DATA,
MCU Read
DATA. - DATA,
Figure 1 Bus Timing
E
E
Port
AB,C,D
Port
A,B,C
24V
O.6V
Data
Valid
Figure 3 Port Data Delay Time (MCU Write)
Figure 2 Port Data Set·up and Hold Times
(MCU Read)
Interrupt
Test
Address
Bus
Op Code Op Code
INT I-NT
,2
____ L-_ _A_'-I"/PSS
'-
I FFF
Address
Address. 1
AddressAddress
PCoPC,
.
Data Bus
R/W
Qp
Operand I',elevant
Code
Op Code Oala
Vector Vector
~dsd~ess~~:ress
First Inst of
Interrupt Routine
,---------'/
Figure 4 I nterrupt Sequence
~HITACHI
176
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
~~ -tosc--~~----~~
Vee
~JVce-O 5V
vee-'"O 5V
'""L..o.-._ __
~.~.--------.~
Bus
Address
~~<--.J'----'L-J\.-----1L--J'---_---"--_-'
1FFF
1FFF 1FFF lFFF 1FFE 1FFF New PC
R/W
__
Data Bus
&.~r ---------->--{1/////$/i;}__
rrY~
.'. .
Flgure5 Reset Tlmmg
tscyc
Clock Output
Cs/C-K
\
o 6V
o 6V
~
Data Output
tTXO
I
o 6V
I----
,
)o
i
6V
I
t~~
Cs/RX
i
24V
C7/TX
Data Input
\
24V
------'c:
-
tHRX
::~~_----,:\--r,__
(
Flgure6 SCI Tlmmg (Internal Clock)
tscyC
20V
Clock Input
Cs/CK
---~
o 8V
o 8V
o 8V
tTXD
Data Output
24V
C7/TX
o 6V
tSRX
Data Input
20V
20V
Cs/RX
o 8V
o 8V
Flgure7 SCI Tlmmg(External Clock)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
177
HD6305X2, HD63A05X2, HD63B05X2
o Data Bus (OAT Ao ~ DATA 7)
ThiS TTL compatible three-state buffer can drive one TTL
load and 90pF.
Vcc
TTL Load
I OL
(Port)
Test poInt
terminal
=1
6mA
24kQ
o---......---..-,.==:::j;ji=~
90pF
o Address Bus (ADR o ~ ADR 13)
Each terminal IS TTL compatible and can drive one TTL
load and 90pF.
12kQ
o Input/Output Terminals (Ao ~ A7, Bo ~ B7, Co ~ C 7 )
These 24 terminals conSISt of three 8·blt I/O ports (A. B. C).
Each of theIll can be used as an ll1put or output terminal on
a bit through program control of the data direction register.
For detail" refer to "I/O PORTS."
[NOTES)
1. The load capacItance Includes stray capacitance caused
by the probe, etc
2. All diodes are 152074
®
Figure 8 Test Load
- DESCRIPTION OF TERMINAL FUNCTIONS
The input and output signals of the MCU are descnbed
here.
eVee, Vss
olnput Terminals (01 ~ 07)
These seven mput-only tenninals are TTL or CMOS COIllpatible. Of the port D's, D. IS also used as fNT,. If D. is
used as a port. the INT, interrupt mask bit of the miscellane·
ous regtster must be set to "1" to prevent an INT, IIlterrupt
from bemg accidentally accepted.
oSTBY
ThiS terminal is used to place the MCU mto the standby
mode. With STBY at "Low" level. the oscillation stops and
the mternal condition IS reset. For details, refer to "Standby Mode."
Voltage is applied to the MCU through these two terminals.
Vee IS 5.0V ± 10';1. while VSS IS grounded.
oINT,INT,
External interrupt request inputs to the MCl.!. For details.
refer to "INTERRUPT' The iN'f; tcrnllnal IS al,o used as
the port D. terminal
• XTAL, EXTAL
These terminals provide input to the on·chip clock circUIt.
A crystal oscillator (AT cut. 2.0 to 8.0 MHz) or ceramic
mter is connected to the terminal. Refer to "INTERNAL
OSCILLATOR" for using these input terminals.
• TIMER
This is an mput terminal for event counter.
"TIMER" for details.
The tennmals described m the following are I/O pins for
senal communication tnterface (SCI). They are also used as
ports C 5 , C. and C 7 • For details, refer to "SERIAL COMMUNICATION INTERFACE."
oCK (Cs)
Used to input or output clocks for serial operation .
o Rx (C.)
Used to receive serial data.
o Tx (C7)
Used to transmit serial data .
Refer to
o RES
Used to reset the MCU. Refer to "RESET" for details.
oNUM
This termmal is not for user apphcation. In case of the
HD6305XI. this terminal should be connected to Vee
through 10kfl resistance. In case of the HD6305X2. thiS
terminal should be connected to VS s.
o Enable (E)
This output tenninal supplies E clock. Output is a smgle·
phase, TTL compatible and 1/4 crystal oscillation frequency
or 1/4 external ciock frequency. It can dnve one TTL load
and a 90pF condenser.
-MEMORY MAP
The memory map of the MCU is shown in Fig. 9. $1000 $1 FFF of the HD6305X2 are external addresses. However,
care should be taken to assign vector addresses to $1 FF6 SI FFF. Durtng interrupt processing. the contents of the CPU
registers are saved tnto the stack in the sequence shown in
Fig. 10. This savmg begins with the lower byte (PCL) of the
program counter. Then the value of the stack pointer is
decremented and the lugher byte (PCH) of the program
counter. index register (X). accumulator (A) and condition
code register (CC) are stacked in that order. In a subroutine
call. only the contents of the program counter (PCH and PCL)
are stacked.
o Read/Write (R/W)
This TTL compatible output signal indicates to peripheral
and memory devices whether MCU IS m Read ("High"). or
m Write ("Low") The normal standby state IS Read ("High")
Its output can dnve one TTL load and a 90pr condenser.
•
178
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
or-------~I~~IO~OO~O~~O~P~R~T~A~$OO
I/O Ports
I~·
11-....;P:,;0:.;,R;,;,T..,;B;......j SO 1
PORT C
S02
2
3
PORT D $03"
4 PORT A DDR S04'
5 PORT BOOR S05'
6 PORT C DDR $06'
Not Used
8 T,mer Data Reg S08
9 T,mer CTRL Reg $09
1 0 Mlsc Reg $OA
Timer
121t-__S_C_I___B!S001F
128
RAM
~0080
(128Bytes) I~_
255
256
Stack
$80FF
$ 100
External
\
409E Memory Space $OFFF
409t
ROM'
-REGISTERS
There are five registers which the programmer can operate.
o
'-________....JI Accumulator
o
I
index
' -_ _ _ _ _ _ _ _--' Register
o
' -_ _ _ _ _ _ _ _ _ _ _ _ _ _
'3
6 5
0
1....0--,-10....10-,1_0.....
10....
10-,1_'...1.1_',1-1_ _S_p_~1 ~6~~~er
Not Used
$1000
~16
(4,096Bytes)
SCI CTRL Reg $10
11 SCI STS Reg $11
1 8 SCI Data Reg $12
8182 -~n;;r-r~~t-.- $1FF6
81 91
Veei;";;::;
S1 FFF
8192
$2000
~g~~~"
Zero
' - - - - Negative
'-----Interrupt
Mask
'-------Half
Carry
Not Used
311-_ _--I$1F
3? External
$20
121' Memory Space $1F
External
Memory Space
16383,~______-,
IProgram
~.Counter
$3FFF
Figure "
.. Write only register
... Read only register
• ROM area 1$1000 - $1 FFFI on the H06305X2
IS changed Into External Memory Space
Programming Model
• Accumulator (A)
ThIS accumulator is an ordinary 8-bit register which holds
operands or the result of arithmetic operation or data processing.
Figure 9 Memory Map of MCU
1 654 3 2 1 o
Condition
n-4 1 1 1
Code Register n+1
I
n-3
Accumulator
n+2
n-2
Index Register
n+3
n-1 0
01
n+4
n
PCW
PCl'
Pull
n+5
Push
.. In a subroutine call, only pel and PCH are stacked.
Figure 10 Sequence of Interrupt Stack Ing
• IndeK Register (X)
The mdex regIster IS an 8-bit regIster. and IS used for index
addressing mode. Each of the addresses contained in the
regIster consIsts of 8 bIts which, combined with an offset
value, provIdes an effective address.
In the case of a read/modIfy /wnte instructIon, the index
regIster can be used hke an accumulator to hold operation
data or the result of operatIOn.
If not used In the index addressing mode, the register can
be used to store data temporanly.
• Program Counter (PC)
The program counter IS a 14-blt register that contains the
address of the next instruction to be executed .
• Stack Pointer (SP)
The stack pointer is a 14-blt register that indicates the address of the next stacking space. Just after reset, the stack
pointer is set at address $OOFF. It is decremented when data
is pushed, and incremented when pulled. The upper 8 bits
of the stack pointer are fIXed to 00000011. During the MCV
being reset or during a reset stack pointer (RSP) instruction,
the pointer is set to address $OOFF. Since a subroutine or
interrupt can use space up to address $OOC I for stacking, the
subroutine can be used up to 31 levels and the interrupt up
to 12 levels .
• Condition Code Register (CC)
The condition code register is a S-bit register, each bit
indicating the result of the instruction just executed. The
bits can be individually tested by conditional branch instruc-
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
179
HD6305X2, HD63A05X2, HD63B05X2
tlOns. The CC bits are as follows.
Half Carry (H)' Used to indicate that a carry occurred between bits 3 and 4 during an arithmetic operation (ADD, ADC).
Interrupt (I):
Setting this bit causes all mterrupts, except
a software interrupt, to be masked. If an
interrupt occurs with the bit I set, It IS
latched. It will be processed the instant
the interrupt mask bit is reset. (More specifically, it will enter the interrupt processing
routine after the mstruction follOWing the
CLI has been executed.)
Negative (N): Used to indIcate that the result of the most
recent arithmetic operation, logical operation
or data processing is negative (bIt 7 IS logic
"I ").
Zero (Z)·
Used to indicate that the result of the most
recent arIthmetIc operation, logical operation
or data processing IS zero.
Carry /
Represents a carry or borrow that occurred
Borrow (C): m the most recent arithmetIc operatIOn This
bit IS also affected by the BIt Test and Branch
instruction and a Rotate instruction
-INTERRUPT
There~e si~ifferent types of mterrupt. external. interrupts (INT, INT,), mternal tImer interrupts (TIMER,
TIMER,), serial interrupt (SCI) and JOterrupt by an instruction (SWI).
Of these six interrupts, the INT, and TIMER or the SCI
and TIMER, generate the same vector address, respectively.
When an interrupt occurs, the program in progress stops
and the then CPU status IS saved onto the stack. And then,
the interrupt mask bit (I) of the condition code register is
set and the start address of the interrupt processing routine
IS obtained from a particular mterrupt vector address. Then
the mterrupt routine starts from the start address. System
can eXIt from the interrupt routine by an RTI instruction.
When thIS instruction IS executed, the CPU status before
the interrupt (saved onto the stack) IS pulled and the CPU
restarts the sequence with the JOstructIon next to the one at
whIch the interrupt occurred. Table I lists the priority of
mterrupts and their vector addresses.
Table 1
Interrupt
Priority of Interrupts
Priority
RES
SWI
2
Vector Address
_~___$__IFFE,
$IFFF
$lFFC,
$IFFD
----==------- _.- -------_._._----_.INT
3
$IFFA
$lFFB
TIMER/INT,
4
$IFF8
$IFF9
5
$1 FF6,
$1 FF7
- - - - - - - - - - f - - - - - - - - r----.---'----
SCI/TIMER,
1 - - - - - - - . - - - '- - - -
A flowchart of the JOterrupt sequence is shown in Fig. 12.
A block diagram of the interrupt request source IS shown in
fig. 13
". j'-,1
$FF ·.SP
"'TIMER
o ·DDR',
CLR INT LogiC
$FF
SCI
~TDR
$7F-.... Tlmer Prescaler
$50~TCR
$3F· ·SSR
$OO-·SCR
$ 7F·MR
F,gure 12 Interrupt Flow Chart
~HITACHI
180
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589·8300
HD6305X2, HD63A05X2, HD63B05X2
Bit 7 of this register is the iNTi interrupt request flag_
When the falling edge is detected at the INT. tenninal, "I"
is set m bit 7. Then the software in the mterrupt routine
(vector addresses: SIFF8, SIFF9) checks bit 7 to see if it
is INT. mterrupt. Bit 7 can be reset by software.
In the block diagram, both the external interrupts INT and
INn are edge trigger inputs. At the falling edge of each mput,
an interrupt request is generated and latched. The INT inter·
rupt request is automatically cleared if jumping is made to
the INT processing routine. Meanwhile, the INT. request is
cleared if "0" is written in bit 7 of the miscellaneous register.
For the external interrupts (INT, INT.), internal timer
interrupts (TIMER, TIMER.) and senal interrupt (SCI), each
interrupt request is held, but not processed, if the I bit of the
condition code regISter is set. Immediately after the I bit is
cleared, the correspondmg interrupt processing starts according to th~onty.
The INT. mterrupt can be masked by setting bit 6 of the
miscellaneous regIster; the TIMER interrupt by setting bit 6
of the timer control register; the SCI interrupt by settmg bit
5 of the serial status register; and the TIMER. interrupt by
setting bit 4 of the serial status register.
The status of the lNT terminal can be tested by a Bil or
BIH instruction. The INT falling edge detector CIrcuit and
its latching circuit are independent of testing by these instructions. This is also true with the status of the fiii'F2 termma!.
Miscellaneous Register (MR;$OOOA)
76543210
!
IMR71MRSL21ZIZ1ZIZIZ\
tL_ _ _ _ _ _ _ _ _ _ INT. Interrupt Mask
L _ _ _ _ _ _ _ _ _ _ _ INTl Interrupt Request Flag
Miscellaneous Register (MR; $OOOA)
Bit 6 is the INT. interrupt mask bit. If this bit is set to "I",
then the INT. interrupt is disabled. Both read and write are
pOSSible With bit 7 but" I" cannot be written in this bit by
software. This means that an interrupt request by software
is impossible .
When reset, bit 7 is cleared to "0" and bit 6 is set to "I"
• Miscellaneous Register (MR; $OOOA)
The interrupt vector address for the external interrupt
INT. is the same as that for the TIMER mterrupt, as shown
in Table I. For this reason, a special register called the miscellaneous register (MR; $OOOA) IS avaIlable to control the
INT. interrupts.
-TIMER
Figure 14 shows a MCV timer block diagram. The timer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data
Vectonng generated
$1FFA.$1FFB
BIH/BIL Test
Condition Code Register (eel
iliif Interrupt Latch
INT
\
Fallmg Edge Detector
I
'}---<>-t---- Vectoring generated
$1FFB. $1FF9
TIMER
Senal Status
RegISter (SSRI
SCI TIMER,
'}---+----
Vectoring generated
$1 FF6. $1 FF7
Figure 13 Interrupt Request Generation Circuitry
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
181
HD6305X2, HD63A05X2, HD63B05X2
register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the CPU saves its status into the stack
and fetches timer interrupt routine address from addresses
$1 FF8 and $1 FF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register. can also mask the timer
interrupt.
.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the input to the
timer Input terminal.
Once the timer count has reached "0", It starts counting
down with "$FF". The count can be mOnitored whenever
deSIred by reading the IImer data register. ThiS permits the
program to know the length of time having passed after the
occurrence of a timer Interrupt, without disturbing the con·
tents of the counter.
When the MCU is reset, both the prescaler and counter are
mitialized to logic "I ". The timer interrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) is set.
To clear t~e timer interrupt request bit (bit 7), it is necessary to write "0" in that bi!:
TCR7
Timer interrupt r~quest
o
Absent
• Timer Control Register (TCR; $ooOgl
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controUed
by the timer control register (TCR; $0009).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
Timer Control Register (TC R; $00091
' - - - - - - - - - - - Timer Interrupt mask
' - - - - - - - - - - - - - T t m e r mterrupt request
After reset, the TCR IS initialized to "E under timer terminal control" (bit 5 = 0, bit 4 = I). If the timer terminal is
"I ", the counter starts counting down with "$FF" immediately after reset.
When "I" IS written in bit 3, the prescaler IS mitialized.
This bit always shows "0" when read.
Table 2
TCR
Present
Clock Source Selection
Clock mput source
Bit 5
Bit 4
0
0
Internal clock E
TCRS
Timer interrupt mask
0
1
E under timer term mal control
o
Enabled
1
0
No clock input (countmg stoppedl
DISabled
1
1
Event input from timer terminal
{Internal
Clockl
E--+-1
Input
Terminal
' -_ _..,.-_ _ _...,.._ _---J Timer Interrupt
Write
Read
Figure 14 Timer Block Diagram
~HITACHI
182
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
A prescaler division ratio is selected by the combination of
three bits (bits 0, I and 2) of the timer control register (see
Table 3). There are eight different division ratios: +1, +2, +4,
+8, +16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
Table 3
Prescaler Division Ratio Selection
TCR
Prescaler division ratio
Bit 2
Bit 1
0
0
0
+1
0
0
1
+2
0
1
0
+4
0
1
1
+8
1
0
0
+16
Bit 0
1
0
1
+32
1
1
0
+64
1
1
1
+128
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "I". When a timer
interrupt occurs, "I" is set in the timer interrupt request bit.
This bit can be cleared by writing "0" 10 that bit.
-SERIAL COMMUNICATION INTERFACE (SCI)
This interface is used for serial transmission or reception
of 8-bit data. Sixteen transfer rates are available in the range
from 1 Jl.S to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one octal counter and
one prescaler. (See Fig. IS.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.
-SCI Control Register (SeR; $0010)
SCI Control Registers (SCR; 0010)
Transfer
Clock
L--.r--'---r-'
Generator
SCI Status Registers
(SSR :$0011)
SCI/TIMER2
Figure 15 SCI Block Diagram
o
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
183
HD6305X2, HD63A05X2, HD63B05X2
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completion of transmitting or receiving S-bit data_ It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS="I". The bit can also be
cleared by writing "0" in it.
C 7 terminal
SCR7
o
Used as I/O terminal (by DDR).
Serial data output (DDR output)
c. termonal
SCR6
o
Bit 6 (SSR6)
Bit 6 is the TIMER, interrupt request bit. TIMER, is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER,.)
Used as I/O terminal (by DDR).
Serial data input (DDR input)
SCR5 SCR4
0
Clock source
C, terminal
-
0
Used as 1/0 termonal (by
DDR).
0
1
-
1
0
Internal
Clock output (DDR output)
1
1
External
Clock Input (DDR Input)
BIt 5 (SSRS)
Bit S IS the SCI interrupt mask bit which can be set or
cleared by software. When it is "I", the SCI interrupt (SSR7)
IS masked When reset, it is set to "I".
------.--~----
------- f - - - - - - - - - - - . - - - - ....
Bit 7 (SCR7)
When this bit is set, the OOR correspondmg to the C,
becomes "I" and this termmal serves for output of SCI data.
After reset, the bIt is cleared to "0"
Bit 6 (SCR6)
When thIs bIt IS set, the DOR corresponding to the C.
becomes "0" and thIs termmal serves for input of SCI data.
After reset, the bit is cleared to "0".
BIt 4 (SSR4)
BIt 4 is the TIMER, tnterrupt mask bit which can be set
or cleared by software. When the bIt IS "I", the TIMER,
interrupt (SSR6) IS masked. When reset, it is set to "I".
BIt 3 (SSR3)
When "I" IS written in thIS bit, the prescaler of the transfer
clock generator is inttialized. When read, the bIt always is "0".
BIts 2 - 0
Not used.
SSR7
o
BIts 5 and 4 (SCR5, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0"
Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. After
reset, the bits are cleared to "0".
SCR3
0
SCR2
0
SCRl
0
SCRO
I
0
Transfer clock
rate
-_._-_._-_.. ----
f,------.
4.00 MHz
SSR6
o
0.95 11s
o
0
0
1
211s
1.9111s
0
0
1
0
411S
3.82115
0
0
1
1
811s
76411s
I
I
I
I
I
I
1
1
1
1
32768 115
1/325
-SCI Status Register (SSR; $0011)
76543210
TIMER, ,nterrupt request
Absent
SCI Interrupt mask
Enabled
DISabled
___S~S__R_4_ _ _f-____T_IM~E_R::.,. Interrupt mask
o
-SCI Data Register (SDR; $0012)
A senal-parallel conversion regrster that is used for transfer
of data.
----
Present
SSR5
0
Absent
Present
4.194 MHz
1 11'
SCI Interrupt request
Enabled
Disabled
• Data Transmission
By wntmg the desired control bIts into the SCI control
regrsters, a transfer rate and a source of transfer clock are
determmed and bIts 7 and 5 of port C are set at the 5erial
data output tenninal and the serial clock terminal, respectlvely. The transmit data should be stored from the accumulator or index regrster into the SCI data regISter. The data
wntten m the SCI data register IS output from the C,fTx
temllnal, starling with the LSB, synchronously with the
faIlIng edge of the serial clock. (See FIg. 16.) When 8 bIt of
~HITACHI
184
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the last
serial clock. This request can be masked by setting bit 5 of the
SCI status register. Once the data has been sent, the 8th bit
data (MSB) stays at the C7/Tx terminal. If an external clock
source has been selected, the transfer rate determined by
bits 0 - 3 of the SCI control register is Ignored, and the C5/
CK terminal is set as input. If the internal clock has been
selected, the Cs/CK terminal is set as output and clocks are
output at the transfer rate selected by bits 0 - 3 of the SCI
control register.
Figure 16 SCI Timing Chart
• Data Reception
By writing the desired control bits into the SCI control
register, a transfer rate and a source of transfer clock are de·
termined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock terminal, respectively.
Then dummy.writing or ·reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subsequent received data. It must be taken
after reset and after not reading subsequent received data.
The data from the C./Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When 8 bits of data have been reo
ceived, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bit 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 - 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the C,/CK terminal. If the internal
clock has been selected, the Cs /CK terminal is set as output
and clocks are output at the transfer rate selected by bits 0 3 of the SCI control register.
TIMER> is commonly used with the SCI transfer clock
generator. If wanting to use TIMER> independently of the
SCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
Writing the SDR causes the' prescaler of the transfer clock
generator to be initialized.
-I/O PORTS
There are 24 input/output terminals (ports A, B. C). Each
I/O terminal can be selected for either input or output by the
data direction register. More specifically, an I/O port will
be input if "0" is written in the data direction register, and
output if "I" is written in the data direction register. Port A,
B or C reads latched data if it has been programmed as output,
even with the output level being fluctuated by the output
load. (See Fig. 17.)
When reset, the data direction register and data register go
to "0" and all the input/output terminals are used as input.
Bit of data
register
Bit of
output
data
Status of
output
Input to
CPU
1
0
0
0
direction
1
1
1
0
X
3·stat.
Figure 17
-TIMER>
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 - 0 of the SCI control register
(4 jJ.S - approx. 32 ms (for oscillation at 4 MHz)) is input to
bit 6 of the SCI status register and the TIMER> interrupt
request bit is set at each failIng edge of the clock. Since interrupt requests occur periodically, TIMER> can be used as a
reload counter or clock.
---~1
~---'
:r:
:Transfer
clock generator IS reset and mask bit (bit 4
of SCI status register) IS clea red.
,nterrupt request
@.@ : TIMER2 Interrupt request bit cleared
ill. ® : TIMER>
•
1
Pin
Input/Output Port Diagram
Seven input-only terminals are available (port D). Writing
to an input terminal is invalid.
All input/output terminals and input tenninals are TTL
compatible and CMOS compatible in respect of both input and
output.
If I/O ports or mput ports are not used, they should be
connected to Vss via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
-RESET
The MCV can be reset either by external reset input (RES)
or power-on reset. (See Fig. 18.) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown m Fig. 19 .
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
185
HD6305X2, HD63A05X2, HD63B05X2
requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the specifications and typical arrangement of the crystal, respectively.
J
5V
Vee
4.5 V
O V - - - - - -J
~
/
Terminal
--
~::;.,
V,LRES
--------of"
tRHl
I---
c,
-----------'
AT Cut
Parallel
Resonance
Co=7pF max.
EXTAL f=2.0-80MHz
Rs=6OQ max
C:Y
L
Figure 18 Power On and Reset Timing
Rs
XTAL
Co
Figure 21
Parameters of Crystal
(a)
HD6305X
MCU
F'gure 19
Input Reset Delay CirCUit
-INTERNAL OSCILLATOR
The internal oscillator circuit
IS
designed to meet the
INOTE)
i
f----1~_IEXTAL
o-a: OMHZ=
XTAL
Figure 22
HD6305X
MCU
10-22pF±20%
Use as short wirings as pOSSIble for connection of the crystal
with the EXTAL and XTAL terminals. Do not allow these
wIrings to cross others.
Typical Crystal Arrangement
-LOW POWER DISSIPATION MODE
The HD6305X has three low power dissipation modes:
wait, stop and standby.
Crystal Oscillator
Cll
EXTAL
b"D
XTAL
HD6305X
MCU
Ceramic Oscillator
External
Clock
Input
EXTAL
NC
XTAL HD6305X
MCU
External Clock Drive
Figure 20
Internal Oscillator Circuit
.Wait Mode
When WAIT instruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication inter·
face - stay active. (NOTE: Once the system has entered the
wait mode, the serial communication interface can no longer
be retriggered.) In the wait mode, the registers, RAM and I/O
terminals hold their condition Just before entering into the
wait mode.
The escape from this mode can be done by mterrupt (INT,
TIMER/INT. or SCI/TIMER.), RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentioned later.)
When interrupt is requested to the CPU and accepted, the
wait mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit of the condition code register, after releasing from the wait mode the MCU executes the instruction
next to the WAIT. If an interrupt other than the INT (i.e.,
TIMER/INT. or SCI/TIMER.) is masked by the timer control
~HITACHI
186
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
register, miscellaneous register or serial status register, there
is no interrupt request to the CPU, so the wait mode cannot
be released.
Fig. 23 shows a flowchart for the wait function.
• Stop Mode
When STOP instruction being executed, MCU enters into
the stop mode. In this mode, the oscillator stops and the CPU
and peripheral functions become inactive but the RAM,
registers and I/O terminals hold their condition just before
entering into the stop mode.
The escape from this mode can be done by an external
interrupt (M or 1liIT2), RES or STBY. The RES resets the
MCU and the STBY brings into the standby mode.
When interrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the opera·
tion mode and vectors to the interrupt routine. If the interrupt is masked by the I bit of the condition code register,
after releasing from the stop mode, the MCU executes the
instruction next to the STOP. If the INT, interrupt is masked
by the miscellaneous register, there is no interrupt request to
the MCU, so the stop mode cannot be released.
Fig. 24 shows a flowchart for the stop function. Fig. 2S
shows a timing chart of return to the operation mode from
the stop mode.
For releasing from the stop mode by an interrupt, oscillation starts upon input of the interrupt and, after the internal
delay time for stabilized oscillation, the CPU becomes active .
For restarting by RES, oscillation starts when the RES goes
"0" and the CPU restarts when the RES goes "I". The duration of RES="O" must exceed tosc to assure stabilized oscillation.
• Standby Mode
The MCU enters into the standby mode when the STBY
terminal goes "Low". In this mode, all operations stop and
the internal condition is reset but the contents of the RAM are
hold. The I/O terminals turn to high-impedance state. The
standby mode should escape by bringing STBY "High". The
CPU must be restarted by reset. The timing of input signals
at the RES and STBY terminals is shown in Fig. 26.
Table 4 lists the status of each parts of the MCU in each
low power diSSipation modes. Transitions between each mode
are shown in Fig. 27.
(Note)
~en I bit .£!..£ondihon code register IS "I" and interrupt
(INT, TIMER/INT" SCI/TIMER,) IS held, MCU does not enter
WAIT mode by the execution of WAIT mstruction.
In that case, after the 4 dummy cycles MCU executes the
next mstructlOn.
In the same way, when external in terru pts (INT, INT 2) are
held at the bit I set, MeU does not enter STOP mode by the
executlOn of STOP Instruction. In that case, also, MCU executes
the next mstruchon after the 4 dummy cycles.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
187
HD6305X2, HD63A05X2, HD63B05X2
OscIllator Active
T,mer and Serial
Clock ActIve
All Other Clocks
Stop
Imtlallze
CPU, TIMER. SCI,
1/0 and All
Other FunctIons
No
No
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 23 Wait Mode Flow Chart
~HITACHI
188
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2 , HD63A05X2 , HD63B05X2
Stop OSCillator
and All Clocks
No
Turn on OSCillator
Walt for Time Delay
to StabIlize
Turn on OSCIllator
Walt for TIme Delay
to StabIlize
1=0
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
F,gure 24 Stop Mode Flow Chart
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
189
HD6305X2, HD63A05X2, HD63B05X2
OscIllator
E
""11111"""""111""11
M11111111111111111111111111111111111111111111111111111111111I
II
(
~'I-----+----'
T,me reqUired for oscil~ation to beco~~J-=>
I
Interrupt
STOP onstructlon
executed
stabIlized (built-in delay time)
r;-nstructlons
restart
(a) Restart by Interrupt
Oscillator 11111111111111111111111111111
TIme required for OSCIllatIon to become
------------St.ib;l Ized (t05C ) - - - - - - - -
STOP instructIon
executed
Reset
start
RES
(b) Restart by Reset
F,gure 25
Timong Chart of Releasing from Stop Mode
L----------\Il~_-.JI
iii
•
I
I
I
I
I
I
,
I
I
I
I
I
' - - " __L __ ~'
-L-----il------I--------'
IResta;t
tosc
F,gure 26
Table 4
Tlmong Chart of Releasong from Standby Mode
Status of Each Part of MCU on low Power DIssipation Modes
ConditIon
Mode
WAIT
-
Start
Software
STOP
Standby
WAIT onstructlon
STOP onstructlon
Hardware
STBY~"low"
Escape
Osclllator
CPU
TImer,
Se".1
RegIster
RAM
ActIve
Stop
ActIve
Keep
Keep
Keep
STBY, RES, INT, INT"
each interrupt request of
TIMER, TIMER" SCI
Stop
Stop
Stop
Keep
Keep
Keep
STBY, RES, INT, INT,
I/O
terminal
-Stop
Stop
Stop
Reset
Keep
HIgh Impedance
STBY~"Hlgh"
~HITACHI
190
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
Figure 27
TranSitions among Active Mode, Walt Mode,
Stop Mode, Standby Mode and Reset
-SIT MANIPULATION
The MCU can use a single instruction (BSET or BCLR) to
set or clear one bit of the RAM or an I/O port (except the
wnte·only registers such as the data direction regISter). Every
bit of memory or I/O Within page 0 ($00 - $FF) can be tested
by the BRSET or BRCLR instructIon,dependmg on the result
of the test, the program can branch to required destmatlOns
Smce bits m the RAM, or I/O can be manipulated, the user
may use a bit Within the RAM as a flag or handle a smgle I/O
bit as an mdependent I/O tennmaL Fig 28 shows an example
of bit manIpulation and the valIdity of test instructIOns In
the example, the program IS configured assunung that bit 0
of port A is connected to a zero cross detector circuit and
bit 1 of the same port to the tngger of a tnac
The program shown can activate the tnac withm a time of
1OI-'s from zero·crossing through the use of only 7 bytes on
the ROM. The on·chip IImer provides a reqUIred time of
delay and pulse width modulation of power is also pOSSible.
SE l F 1
Figure 28
BRClR 0, PORT A, SELF 1
BSET 1, PORT A
BClR 1, PORT A
Example of Sit Manipulation
-ADDRESSING MODES
Ten different addressing modes are avaIlable to the MCU
.Immediate
See Fig. 29. The immediate addressing mode provides
access to a constant which does not vary dunng execution of
the program.
ThIS access requIres an instruction length of 2 bytes. The
effective address (EA) IS PC and the operand is fetched from
the byte that follows the operatIOn code
• Direct
See Fig. 30. In the dIrect addressing mode, the address of
the operand IS con tamed In the 2nd byte of the mstructlOn
The user can gam direct access to memory up to the lower
255th address All RAM and I/O regISters are on page 0 of ad·
dress space so that the dIrect addressll1g mode may be utilIzed.
• Extended
See Fig. 31. The extended addressmg IS used for referenc·
Ing to all addresses of memory. The I:A IS the contents of
the 2 bytes that follow the operatIOn code An extended
addreSSing ,"struet"," reqUIres a length of 3 bytes
• Relative
See Fig. 32. The relative addrcssmg mode is used With
branch InstructIOns only. When a branch occurs, the program
counter IS loaded With the contents of the byte followmg the
operation code. EA = (PC) + 2 + ReI., where ReI. Indicates a
Signed 8·b,t data followmg the operatIOn code. If no branch
occurs, ReI = O. When a branch occurs, the program Jumps
to any byte In the range + 129 to -127. A branch Instruction
requIres a length of 2 bytes
• Indexed (No Offset)
See FIg 33 The indexed addreSSIng mode allows access
up to the lower 255th address of memory. In this mode, an
InstructIOn requires a length of one byte. The EA is the
contents of the Index regISter.
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
191
HD6305X2, HD63A05X2, HD63B05X2
• Indexed (S-bit Offset)
See Fig. 34. The EA is the contents of the byte following the operation code, plus the contents of the index register.
This mode allows access up to the lower 511 th address of
memory. Each instruction when used in the index addressing
mode (8-bit offset) requires a length of 2 bytes.
• Indexed (16-bit Offset!
See Fig. 35. The contents of the 2 bytes following the
operation code are added to content of the index register
to compute the value of EA. In thIs mode, the complete
memory can be accessed. When used in the indexed addressing mode (16-bit offset), an instruction must be 3 bytes long.
• Bit Set/Clear
See Fig. 36. This addressing mode is applied to the BSET
and BCLR instructions that can set or clear any bit on page
O. The lower 3 bits of the operation code specify the bit to
be set or cleared. The byte that follows the operation code
indicates an address within page o.
• Bit Test and Branch
See Fig. 37. This addressing mode is applied to the BRSET
and BRCLR instructions that can test any bit within page 0
and can be branched in the relative addressing mode. The
byte to be tested is addressed depending on the contents of
the byte following the operation code. IndiVIdual bits within
the byte to be tested are specified by the lower 3 bits of the
operation code. The 3rd byte represents a relative value which
will be added to the program counter when a branch condition
is established. Each of these instructions should be 3 bytes
long. The value of the test bit is written in the carry bit of the
condition code regIster.
• Implied
See Fig. 38. This mode involves no EA. All informatIOn
needed for execution of all instructIOn is contamed in the
operation code. Direct manipulation on the accumulator
and index register IS mcJuded in the impbed addressing mode.
Other instructions such as SWI and RTf are also used in this
mode. All mstructions used in the Impbed addressmg mode
should have a length of one byte.
i l:: i
j
A
I
Memory
I
--l
r----
A
F8
Indel( Reg
I
Stack Pomt
PROG LOA ;:$FB 05BEC~A~6=::l--_ _ _ _ _..J
05BF
Prog Count
Fe
OseQ
cc
FIgure 29
Example of Immediate AddreSSing
EA
Memorv
0048
CAT FeB 32 0048 t:::J:202:=t---+----OOOO
------t
20
["del( Reg
I
Stack POint
PROG lOA CAT ~:~~ ~::42;B:t::~
L
Prog Count
052F
cc
~
.,
Figure 30
Example of Direct Addressing
~HITACHI
192
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
EA
Memory.
~
A
40
Index Reg
I
Stack Pomt
I
Prop Count
CAT FCB
64 06E51"':__40_-;1
F'gure 31
040C
CC
Example of Extended AddreSSing
EA
Memory
,
i
PROG SEQ PROG2
'
~
04A7~'
27
04A8
•
18
L -_ _~_ _~
~
Figure 32
Example of Relative AddreSSing
EA
Memory
A
I
4C
Index Re
BB
Stack Poml
Prog Count
......__...;O::,::5"'F5,..=::J
CC
Figure 33
Example of Indexed (No Offset) AddreSSing
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
193
HD6305X2, HD63A05X2, HD63B05X2
EA
Memory
TABL
:~: ~:~ ~~::I-I-::~:~~::~
feB =08
FeB:;
CF
r--t----~~r;:::J
008Bt=~OBt::j,-----j--J
Doae
CF
IndexCF
Reg
03
PAOG LOA TABl X
Stack POInt
6~~~ t--'ii~!i;-~--I
I
Prog Count
0750
cc
~
.
.
Figure 34
Example of Index (B-bit Offset) Addressing
,
~
,
PAOG LOA TABl X
TABL
DB
Index Reg
02
~::~t::~~;~::~
Stack OInt
0694 tr=~7E=:f
Prog Count
~~: ~:: ~;;~,"~::~:~~::~
FeB:: DB 0780
FCB ~CF
-I
'
DB
I
0695
CC
J
________
078'~-=C;..F_-I
Figure 35
Example of Index (16-bit Offset) Addressing
. - - - - - - - - - - E'
Memorv
000'
PORT 8 EQu 1 0001 r--;;B:;"F-;....--,
lodell Reg
PAOG BeLA 6 PORT B 058F t::::J'~D=:}-----.:
0590..
01
I
.
Figure 36
Example of Bit Set/Clear Addressing
•
194
Stack POint
Prog Count
0591
CC
~
.
I
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
fA
Memorv
0002
PORT C EQU 2 0002 r--'-FO:.....~
PROG SRCLR 2 PORT C PROG 2
baunt
g~;:~::~~~;::~IT-
Prog
0594
0576 r-....;,10:""'--1, J--""'-""
FIgure 37
CC
Example of BIt Test and Branch Addressing
fA
Memory
A
f5
Index
e9
f5
Slack oml
Prog Count
0588
cc
F,gure 38
Example of ImplIed Addressing
-INSTRUCTION SET
There are 62 basic instructions available to the HD6305X
MeV. They can be classified into five categories: register/
memory, read/modify/write, branch, bit manipulation, and
control. The details of each instruction are described in
Tables 5 through II.
• Register/Memory Instructions
Most of these instructions use two operands. One operand
is either an accumulator or index register. The other is derived
from memory using one of the addressing modes used on the
HD6305X MeV. There is no register operand in the uncon·
ditional jump instruction (JMP) and the subroutine jump
instruction (JSR). See Table 5.
• Read/Modify!Write Instructions
These instructions read a memory or register, then modify
or test its contents, and write the modified value into the
memory or register. Zero test instruction (TST) does not
write data, and is handled as an exception in the read/modify/
write group. See Table 6.
• Branch Instructions
A branch instructIOn branches from the program sequence
in progress If a particular conditIOn is established. See Table 7.
• Bit Manipulation Instructions
These instructions can be used With any bit located up to
the lower 255th address of memory. Two groups are available;
one for setting or clearing and the other for bit testing and
branching. See Table 8.
• Control Instructions
The control instructions control the operation of the Mev
which is executing a program. See Table 9.
• List of Instructions in Alphabetical Order
Table 10 lists all the instructions used on the HD6305X
Mev in the alphabetical order.
• Operation Code Map
Table II shows the operation code map for the instructions
used on the MeV.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
1 95
HD6305X2, HD63A05X2, HD63B05X2
Table 5 Register/Memory Instructions
Addrelling Model
Indexed
Indexed
MnemoniC
Operations
•-
OP
Load A from Memory
LOA
A6 2
OP
•
Boot•• nl
Inde.ed
-
OP
2 B8 2
3 C8
•3 4
OP
F8
1
•
--
3 E6 2
4 06
•
--
OP
OP
•3 5
Condition
Cod.
Arithmetic::
Operation
Extended INo Offset) 18-Bot Offset) 116-1Irt0lfl0tl
Dl'ect
Immedllte
H
• •
• •
• •
••
•
M_A
Load X from Memory
LOX
AE 2
2 BE
2
3 CE 3
4
FE
1
3
EE
2
4 DE 3
5
M-X
Store A In Memory
STA
--
B7
2
3 C7 3
4
F7
1
4
E7
2
4 07 3
5
A_M
Store X In Memory
STX
- --- -
-
BF
2
3 CF
3
4
FF
1
4
EF 2
4 OF 3
5
X-M
Add Memory to A
ADD
AB 2
2
BB 2
3 CB 3
4
FB
1
3
E8 2
4 DB 3
5
A+M~.A
I
A
N
Z
A
A
A
A
C
•
•
•
A
A
A
I,
•
A
A
I
A
I
I
A
I
I.
Add Memory and Carry
AOC
A9 2
2 B9
2
3 C9 3
4
F9
1
3 E9 2
4 09 3
5 A+M+C· ..A
SUB
AD 2
2 BO 2
3 CO 3
4
FO
1
3
EO
2
4 DO 3
5 A-M ......A
A WIth Borrow
SBC
A2
2
2 B2
2
3 C2
3
4
F2
1
3
E2
2
4 02 3
5 A-M-C---A
AND Memory to A
AND
A4
2
2 B4
2
3 C4 3
4
F4
1
3
E4
2
4 04 3
5 A M-A
OR Memory With A
ORA
AA 2
2 8A 2
3 CA 3
4
FA
1
3
EA 2
4 OA 3
5
A+M-A
EOR
AB 2
2 BB 2
3 ca 3
4
Fa
1
3 <6 2
4 08 3
5
A\t>M-..A
CMP
AI
2 61
3 Cl
3
4
Fl
1
3
El
2
4 01
5 A-M
CPX
A3 2
2 B3 2
3 C3 3
4
F3
1
3
E3
2
4 03 3
A5 2
2 B5
2
3 C5 3
4
F5
1
3
E5
2
-...-
BC
2
2 CC 3
3 FC
1
2 EC
2
BO 2
5 CD 3
6 FO
1
5 ED 2 r s
to A
SUbtreet Memory
- - - --
•
• •
A
Subtrect Memory from
---
ExclUSive OR Memory
with A
f----------
Artthmetlc Compare A
With Memory
Amhmetlc Compare-X--
f--------- f---- -
With Memory
--------Bit Test Memory With
--~---
A (logical Comparel
BIT
Jump Unconditional
JMP
------Jump to Subroutme
--~
2
-
-
--
2
3
5
X-M
4 05 3
5
A
3 DC 3
4
Do '31-6
•
•
•
•
--
•
•
A
A
I
I.
I
•
•
•
• •
A
A
I
I
I
I
• •
A
I
•
•
I
• •
•
• • • • •
• • • • •
M
I
A
---------
Symbols Op" Operation
_ .. Number of bytes
-
'" Number of
cycles
Table 6 Read/Modify/Write Instructions
AddreSSing Modes
I MnemonIC
Operations
I
----Imphed(A)
,~-~--
-----1~lndelled-·
Implted(X)
~
Indexed-
(No Offset) (8 BIt Offset)
Direct
ConditIOn
01",;0---: t--Op',;T-::-ro,; ;;- ~- 01' -;= o--'f~T-
Rotate left Thru Carry
ROL
49
1
Rotate Righi Thru Carry
ROR
46
1
LSL
46
1
2
59
1
2 39
79
1
56
1
36
76
1
5B
1
38
2
5
78
1
5
C{}:ib'
69
66
2
6
AOIXorM
I III II I
SMt Right
ArithmetiC Shift Right
Artthmetlc Shift left
LSR
44
1
2 54
1
or Zero
-
1
5 68
5
.
0' I H3": .. I. KJ
c:r I 1-1+:..1 I 1--0
64
1
57
1
37
2
5
77
1
67
1
58
1
38
2
5 78
1
5 68 2
Equal to lSl
4 60
A-OO or X-OO or M-OO
40
1
50
1
3D 2
4 70 1
2
6
b'
1
t-
•
0
C
48
---~
"
•
47
---
"i~~~
•
Oo
ASR
TST
1/
74
•
•
C
C
-- --ASl
Test for Negative
Symbols Op
2 34
"iJ
•
C@1' I IAH§D5J
b,
D-l I ~~:'H I I 1- • •
b,
Loglca'
Code
Boolean/Arithmetic Operation
C
• •
•
• •
A
• •
A
·
0
A
A
OperatIon
'" Number of bytes
.. Number of cycles
Ie
@>HITACHI
196
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
•
HD6305X2, HD63A05X2, HD63B05X2
Table 7 Branch Instructions
Addressing Modes
Operations
Mnemonic
Branch Always
BRA
Relative
OP
#
-
20
2
3
None
None
H
Branch Never
BRN
21
2
3
Branch IF Higher
BHI
22
2
3
C+Z=O
Branch IF lower or Same
BlS
23
2
3
C+Z=1
Branch IF Carry Clear
BCC
24
2
3
C=O
(Branch IF Higher or Same)
(BHS)
24
2
3
C=O
BCS
25
2
3
C=1
(BlO)
25
2
3
C=1
BNE
26
2
3
z=o
Branch IF Carry Set
(Branch IF lower)
Branch IF Not Equal
Branch IF Equal
BEQ
27
2
3
Z=1
Branch IF Half Carry Clear
BHCC
28
2
H=O
Branch IF Half Carry Set
BHCS
29
2
3
3
Branch IF Plus
BPL
2A
2
3
N=O
Branch IF Minus
BMI
2B
2
3
N=1
BMC
2C
2
3
1=0
BMS
2D
2
I 3
1= 1
Bil
2E
2
3
H=1
Branch IF Interrupt Mask
Bit
IS
Clear
Branch IF Interrupt Mask
Bit
IS
Set
Branch IF Interrupt Line
IS
low
- - - -- -
INT=O
Branch IF Interrupt Line
IS
High
Branch to Subroutine
Condition Code
Branch Test
BIH
2F
2
3
INT=1
BSR
AD
2
5
-
I
N
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • •
• • • • •
• • • • •
Symbols. Op = OperatIon
# :: Number of bytes
- = Number of cycles
Table 8 Bit Manipulation Instructions
Operations
Mnemonic
Addressing Modes
Booleanl
Branch
Bit Set.' Clear
Bit Test and Branch Arithmetic
Test
Operation
OP
II
OP
Ii - 2·n
3 5
Mn=1
-- 01 +2·n 3 5
Mn=O
--- 1~Mn
10+2·n 2 5
O~Mn
11 +2·n 2 5
-
-
Branch IF Bit n
Branch IF Bit n
Set Bit n
Clear Bit n
Symbols Op
IS
IS
set
clear
BRSET n(n=O 7)
BRClR n(n=O, 7)
BSET n(n-O, 7)
BClR n(n=O,- 7)
#
== Operation
= Number of bytes
-
=
Condition Code
H
I
N
•
•
•
•
•
•
•
•
• •
Z
C
,~
• •
• • •
• • •
1\
Number of cycles
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
197
HD6305X2, HD63A05X2, HD63B05X2
Table 9 Control Instructions
Addressing Modes
~---
Operations
Mnemonic
-OP
Implied
11
Condition Code
Boolean Operation
-
H
N
Z
• • •
91'- 1 2
Transfer X to A
-• • •
---SEC
1
Set Carry Bit
99
1
--- • • •
1
Clear Carry BIt
CLC
9B
1
• •, •
-;-----------_._--SEI-- 98 r---i--- --2
Set Interrupt Mask BIt
•
•
---2
-,Clear Interrupt Mask Brt
CLI
9A
0-1
0 •
•
-,- W - - - - Software Interrupt
SWI
83
• 1 •
- - - - - - - - - - - --_._---1--:-,
581
Return from SubroutIne
RTS
• • •
---------------,-------Return from Interrupt
RTI
'SO , 8
?
?
97
TAX
Transfer A to X
I
A~X
2
1
~-
X~A
-------,~-------
'~C
O~C
'~I
~-----------------
..
Reset Stack POinter
No-Operation
,
-f:lSp-- 9C --- - - - - - - - - f-go.
NOP
-- - - - - 1
DAA
BD
-- ----STOP -8E
--- .- WAir- 8F -
-,-
WaIt
Symbols. Op"" Operation
?
?
f - : = - - c - - - - - - - - - - - - ---- --. --_.- -- r--'$FF-SP
- - - - - - - - - - - - - _.. _-------"-Advance Prog Cntr Only
• •
• •
• •
-Converts blnarv add of BCD charcters Into
BCD format
__________
A
4- c - - - - - - - - - - - - - - - - - - --• •
4
• •
A
Instruction Set (on Alphabetical Order)
---r---1
Mnemonic
Implied
ADC
-ADD
----
-~.-
Addressing Modes
Direct
Extended
X
X
-------X
X
X
X
x
X
X
ASL
X
ASR
X
BCLR
SCS-------
~--
------
BHI
----
(BHS)
(16-B't)
Clear
X
X
X
A
X
X
X
1\
X
X
X
X
------xX
- - - 1-----
1--
---,,-I-
X
X
--+
-
- - - c----
X
X
x
BIH
I
=t
X
~-
-X--
BIT
---
(BLO)
X
X
X
BLS
x
BMC
X
BMI
X
BMS
X
BNE
X
BPL
X
r---- x
BRA
Half Carry (From B,t 3)
Interrupt Mask
Negative (51gn B,t)
Z
Zero
•
•
•
•
•
•
•
X
X
•
•
•
•
•
•
•
•
•
I
Z
C
A
A
1\
1\
1\
f\
1\
1\
•
f\
f\
f\
f\
1\
1\
N
•
•
•
•
•
• •
••
• •
• •
• •
• •
• •
• •
• •
• •
•
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
• •
•
• •
• •
• •
• •
• •
• •
• •
• • • •
1\
1\
(to be continuedt
CondItion Code Symbols
H
I
N
H
•
X
X
Branch
•
•
- - t----
X
B't
Test Ilt
•
•
•
-X-1 - - -
X
X
--
Indexed
(8-B't)
X
--
__
_ _ _ _ c--_
~-=t=
----1
BHCS
Indexed
Relative (No Offset)
- - ---- .
BCC
Condition Code
B't
Set/
Indexed
Immediate
AND
C
t.
•
Carry/Borrow
Test and Set If True. Cleared OtherWise
Not Affected
load CC Register From Stack
~HITACHI
198
A*
"" Number of cycles
Table'O
BEQ
BHCC
-,
2
• Are BCD characters of upper byte 10 or more'} (They are not cleared if set in advance)
# .. Number of bytes
-
----
~--------
-,--, -2-
DecImal Adjust A
Stop
---~~-----
C
• •
• •,
• 0
• .-•
• •
• •
• ,•
• • •
• • •
• • •
• • •
Hitachi America, Ltd_ • Hitachi Plaza • 2000 Sierra Point Pkwy_ • Brisbane, CA 94005·1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
Instruction Set (In Alphabetical Order)
Table 10
Condition Code
Addressing Modes
Bit
Mnemonic
Implied
ImmedIate
Direct
Extended
BRN
Relative
Indexed
Indexed
Indexed
Set,
Test &
INo Ofhet)
(8·8It)
(16·Blt)
Clear
Branch
X
BRCLR
X
BRSEl
X
BSEl
X
BSR
CLC
X
X
CLI
X
CLR
X
X
CMP
COM
X
X
x
X
OAA
X
OEC
x
EOR
X
x
X
CPX
INC
-
X
x
x
X
x
JMP
x
x
X
X
X
X
X
X
X
X
x
X
X
x
x
x
X
X
x
x
X
x
x
x
x
X
x
X
x
X
x
x
x
x
LOX
X
x
x
X
X
X
LSL
x
x
X
X
LSR
X
X
x
X
NEG
x
X
X
X
NOP
X
x
ORA
X
X
x
X
X
X
ROR
X
x
x
x
RSP
x
RTI
X
RTS
x
X
SEC
x
SEI
x
STA
STOP
STX
SWI
x
X
x
x
x
X
x
x
x
x
X
x
X
x
x
X
X
X
x
x
X
x
x
x
SUB
x
X
x
TAX
X
TST
x
TXA
x
WAIT
x
I
N
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
x
SBC
X
H
•
•
LOA
JSR
ROL
Bit
x
?
•
0
f\
C
•
f\
"•
•
•
•
"
" 1
0
" "
""- "
"
"
"
"
"
" •
" ••
"• "• •
• • •
" ••
/\ /\
1\
/\
0
"
/\
/\
/\
/\
/\
• • "•
"
1\
/\
•
•
/\
•
•
/\
•
?
•
•1
•
•
• /\
•1 /\
•
• •
• 1\
• •
• • •
f\
•
/\
/\
/\
"• •
?
?
• •
/\ /\
• 1
• •
/\ •
• •
1\ •
/\ /\
• •
• •
1\ •
• •
• •
Condition Code Symbols
H
Half Carry (From Bit 3)
C
I
Interrupt Mask
/\
N
Z
Negative (Sign Bit)
Zero
•
Carry Borrow
Test and Set If True. Cleared Otherwise
Not Affected
Load CC RegIster From Stack
~HITACHI
Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
199
HD6305X2, HD63A05X2, HD63B05X2
Table 11
Bit Manipulation
0
1
2
3
4
Test &
Branch
Set/
Clear
0
BRSETO
BRCLRO
BRSETl
1
BRCLRl
BRSET2
BSETO
BCLRO
Branch
Operation Code Map
Read/Modify/Write
Rei
DIR
2
BRA
3
A
4
IMP IMM
X
,Xl
,XO
IMP
5
NEG
6
7
8
9
RTI'
-
A
DIR
EXT
,X2
,Xl
,XO
B
C
0
E
F
~H
--
BCLRl
BLS
COM
SWI'
-
CPX
3
BCC
BCS
LSR
-
-
AND
--
-
4
5
ROR
--
ASR
--
TAX'
RTS'
-
~
~-
-~
5
BRCLR2
6
BRSET3
BSET3
7
BRCLR3
BCLR3
BNE
BEQ
B
BRSET4
BSET4
BHCC
LSL/ASL
.-
CLC
9
BRCLR4
BCLR4
BHCS
ROL
-
SEC
A
BRSET5
BRCLR5
BSET5
B
C
-
BPL
BMI
DEC
BRSET6
BCLR5
BSET6
BMC
INC
0
BRCLR6
BCLR6
BMS
E
BRSET7
BSET7
F
BRCLR7
BCLR7
BIL
BIH
3/5
2/5
2/3
~
--
-
TSTHII
TST(-l)
TST
25
1 2
CLR
1/2
2(6
1
SBC
2
BIT
--
8
9
cu'
A
SEI'
RSP'
ADD
JMP(-l)
C
-
JSR(+2)
-
WAIT' TXA'
1/5 1;' 1;1 2/2
JSR(+l)
LOX
2;3
STX
3/4 3/5
L
o
W
6
STA(+ll 7
STA
EOR
ADC
ORA
DAA' NOP BSR'
STOP'
-~
CMP
LOA
~
IGH
0
SUB
BRN
BHI
BSETl
BSET2
BCLR2
(NOTES)
Register /Memory
Control
B
JSRi+21 0
E
STXI+1i F
2/4 1/3
"-" IS an undefined operation code
The lowermost numbers In each column represent a byte count and the number of cycles required (byte counUnumber of cycles)
The number of cycles for the mnemOniCs astensked (*) IS a follows
BSR = 5
RTI=8
DAA=2
TAX =2
RTS=5
STOP =4
RSP=2
eLi = 2
SWI = 10
WAIT = 4
SEI = 2
TXA = 2
3. The parenthesized numbers must be added to the cycle count of the particular instruction
• Additional Instructions
The following new instructions are used on the HD6305X.
DAA Converts the contents of the accumulator into BCD code.
WAIT Causes the MCV to enter the wait mode. For thIs mode,
see the topic, Walt Mode,
STOP Causes the MCV to enter the stop mode. For this mode,
see the topic, Stop Mode.
•
PRECAUTION l-BOARD DESIGN OF
OSCILLATION CIRCUIT
When connecting crystal and ceramIc resonator with the XTAL
and EXTAL pms to OSCIllate, observe the following m deSIgning
the board.
(I) Locate crystal, ceramIc resonator, and load capacity CI and C2
as near the LSI as possIble. (Induction of noise from outside to
the XTAL and EXTAL pins may cause trouble in oscIllation.)
(2) Wife the signal hnes to the nelghbounng XTAL and EXTAL
pins as far apart as possIble.
(3) Board design ofsituatmg signal hnes or power supply hnes near
the oscillator circuit as shown in Fig. 40, should not be used
because of trouble In oscillation in inductIOn. The resistor between the XTAL and EXTAL, and pms close to them should be
10M n or more.
•
PRECAUTION 2-PROGRAM OF WRITE ONLY REGISTER
Read/Modify /Wnte mstructions are unavailable for changing the
contents ofWnte Only Register (e.g. DDR; Data Direction Register
ofl/O port) of HD6305X, HD6305Y and HD63P05Y.
(I) Data cannot be read from wnte only register. (e.g. DDR of
I/O port)
While read/modify/write instructions are executed in the following sequence.
(i) Reads the contents from appointed address.
(Ii) Changes the data which has been read.
(iii) Turn the data back to the original address.
Thus, read/modify/write instructions cannot be applied to
write only register such as DDR.
(2) For the same reason, do not set DDRofl/O port using BSET and
BCLR instructIOns.
(3) Stored instructions (e.g. STA and STX, etc.) are available for
writing into the write only register.
•
PRECAUTION 3-SENDING/RECEIVING PROGRAM OF
SERIAL DATA
Be careful that malfunction may occur if SDR (SERIAL DATA
REGISTER: $0012) IS read or written during transmitting or receiving serial data.
•
PRECAUTION 4-WAIT/STOP INSTRUCTIONS PROGRAM
When I bit of condition code register is .. I" and an interrupt
(INT2, T1MER/INT2) is held, the MCV does not enter into WAID
mode by executing the WAIT instruction.
In that case, after the 4 dummy cycles, the MCV executes the next
mstruction.
In the same way, when external mterrupts (INT, INT2) are held at
the bit I set, the MCV does not enter into the STOP mode by executing STOP instruction. In that case the MCV executes the next instruction after the 4 dummy cycles.
~HITACHI
200
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305X2, HD63A05X2, HD63B05X2
•
PRECAUTION TO USE BSR
If there is 2nd BSR programmed on the address which is dtrected
by first BSR, 2nd BSR may not be executed correctly For this
reason, BSR should not be programmed on the address which is
directed by first BSR.
If necessary, please program as followmg.
(I) On the address which first BSR d,rected, NOP instruction
should be mserted before second BSR.
(2) On the address which first BSR directed, JSR instruction should
be programmed instead of 2nd BSR.
XTALC=~--,-~~~
EXTAL
C=~---=~I-'"
HD630SX
HD630SY
HD63POSY
BSR
I
I
Figure 39
I
LBL1
BSR
I
I
< .,
I
I
I
..........
~ ~
..
LBL1]
I
Design of Oscillation Circuit Board
I
LBL2 ___ .J_
OIl
... ...
LBL3
'", 'I'I
---r
LBL2 --;]
_J\
____ -.1
I
example of malfunction
XTAL
of 2nd BSR execution
EXTAL
BSR
I
I
I
I
HD630SX
HD6305Y
HD63POSY
LBL1
NOP
BSR
I
I
I
LBL2 - - - I
"]
:~~]
I
I
Figure 40
Example of Circuit Causing Trouble in Oscillation
• PRECAUTION WHEN USING BIL/BIH INSTRUCTION
(I) Execute Instruction after the INT Voltage level has stabilized
above V IH or below V IL .
(2) INT voltage level needs to be stabIlized whIle BILlBlH Instruction Execution.
There may be a malfunction by ghtch on control signal If
BILlBIH Instruction Execution has exercized m unstablized INT
signal level.
example of counter measure
(NOP IS mserted)
BSR
I
II
LBL1
JSR
I
I
I
I
I
LBL2 - - - -
I
I
I
VIH
VIL
example of counter measure
(JSR IS used instead of BSR)
-+,------\;-
A K~
A
ii
\
!
I
AVOid BIUBIH Instruction Execution
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
201
HD6305Y2,HD63A05Y2,HD63B05Y2
CMOS MCU (Microcomputer Unit)
The HD6305Y2 is a CMOS 8-bit single chip microcomputer. A
CPU, a clock generator, a 256 byte RAM, 110 terminals, two
timers and a serial communication interface (SCI) are built in the
HD6305Y2. Its memory space is expandable to 16k bytes externally.
The HD6305Y2 has the same function as the HD6305Y2's
except for the number of 110 terminals. The HD6305Y2 is a
microcomputer unit which includes no ROM and its memory
space is expandable to 16k bytes externally
•
•
•
•
•
•
•
•
•
•
HARDWARE FEATURES
8-bit based MCU
2S6-bytes of RAM
A total of 31 terminals, including 24 I/O's, 7 inputs
Two timers
- 8-bit timer with a 7-bit prescaler (programmable prescaler,
event counter)
- lS-bit timer (commonly used with the SCI clock divider)
On-chip serial Interface circuit (synchronized with clock)
Six interrupts (two external, two timer, one serial and one
software)
Low power dissipation modes
- Wait ..... In this mode, the clock oscillator is on and the
CPU halts but the timer/seriallinterrupt function is operable.
- Stop ..... In this mode, the clock stops but the RAM data,
I/O status and registers are held.
- Standby .. In this mode, the clock stops, the RAM data is
held, and the other internal condition is reset.
Minimum instruction cycle time
-HD6305Y2 ... 1 "s (f = 1 MHz)
-HD63AOSY2 ... 0.67"s (f= 1.S MHz)
-HD63BOSY2 ... O.S " (f = 2 MHz)
Wide operating range
Vce=3t06V(f=0.1 toO.SMHz)
-HD630SY2 .. f = 0.1 to 1 MHz (Vee = SV ± 10%)
-HD63AOSY2. f= 0.1 to 1.S MHz (Vcc=SV±10%)
-HD63BOSY2. f=O.lto 2 MHz (Vcc=SV±10%)
HD6305Y2p, HD63A05Y2P,
HD63B05Y2P
(DP-64S)
HD6305Y2F, HD63A05Y2F,
HD63B05Y2F
(FP-64)
•
•
•
•
SOFTWARE FEATURES
Similar to HD6800
Byte efficient instruction set
Powerful bit manipulation instructions (Bit Set, Bit Clear, and
Bit Test and Branch usable for 192 byte RAM bits within page
and I/O terminals)
A variety of interrupt operations
Index addressing mode useful for table processing
A variety of conditional branch instructions
Ten powerful addressing modes
All addressing modes adaptable to RAM, and I/O instructions
Three new instructions, STOP, WAIT and DAA, added to the
HD680S family instruction set
o
•
•
•
•
•
•
• PROGRAM DEVELOPMENT SUPPORT TOOLS
• Cross assembler software for use with IBM PCs and compatibles
• In circuit emulator for use with IBM PCs and compatibles
.HITACHI
202
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305Y2, HD63A05Y2, HD63B05Y2
• PIN ARRANGEMENT
• HD6305Y2F, HD63A05Y2F, HD63B05Y2F
• HD6305Y2P, HD63A05Y2P, HD63B05Y2P
~
....
DATAo
0
~<.J~
:J~~
DATA,
iNT
ffiY
DATA,
DATA. 3
XTAL
ZwX
..
..
...
0(<1(<<
~~~~!;(!cooO
DATA ..
DATAl
DATA.
DATA"
EXTAL
NUM
TlMEA
E
A/W
A,
A.
A.
A.
A,
A,
A,
A.
ADR'I
ADA 11
ADAII
ADA,o
AD'"
ADR.
ADR,
ADR,
I,
I.
I.
I.
I,
I,
I,
I,
AD'
"
ADR ..
ADRa
ADRa
ADA,
ADRo
e,/T.
D,
D,/J'A'I';
el/Ra
C,/eR
D.
D.
c.
c,
D,
c,
D,
c,
D,
c• ......_ _ _ _ _- J - V"
3307
I!: g ;;;
:::
~oouuu~60 add
~d
U
(TapV,ow)
(Top View)
• BLOCK DIAGRAM
"TAL El(TAl
RM
TIMER
Accumulator
A
Revl,t.,
Contr~
.x
0=
~i
Condition Coe»
R'glster
r ___
--'c:,:c'i
Stack
Point...
D,
CPU
Index
Port A
I/O
Terminals
La:
CPU
DJiNT,
D.
D.
0,
0,
0,
PortO
Input
Terminals
sp
Program
Counter
Por.8
"High" PCH
1/0
Program
Counter
"Low" peL
Termln",
"LU
.
.!!
CD
;
CD
!
!
Port C
110
T.rmiMis
• No Int.rn.1 ROM In H06305Y2
DATA,
DATAe
DATA,
DATA.
DATAl
DATA,
DATA,
DATAo
,e......
'oI
egiltlf'
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra POint Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
203
HD6305Y2, HD63A05Y2, HD63B05Y2
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 - +7.0
V
Input Voltage
V,n
-0.3 - Vee + 0.3
V
Operating Temperature
Topr
0-+70
·C
Storage Temperature
T stg
-55 - +150
·C
Thele products have 8 protection circuit in their Input termina's against high electrostatic voltage or high electric fields. Notwithstanding,
be careful not to apply any voltage higher than the ablolute maximum rating to these high input impedance circuits. To Illur, norm.1
(NOTE]
operation, we recommended V ln • V out ; Vss ~ (V ln or V aut ) ~
•
ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee
Vee-
= 5.0V±10%, Vss = GND, Ta = 0 -
Item
Symbol
+70°C, unless otherwise noted.)
Input "High" Voltage
EXTAL
Other Inputs
Input "Low" Voltage
V ,H
--
-----~-
t----
All Inputs
typ
max
~+0.3
Vee xO.7
2.0
-
Vee+0 .3
0.8
V OH
--~
Output "Low" Voltage
All Outputs
Input Leakage Current
TlMER,INT,
D, - D" STBY
Three·state Current
Ao - A 7 , Bo - B"
Co - C 7 , ADRo - ADR,,',
DATA o- DATA 7 ,E', R/W'
t----
-
2.4
-
IOH - -10JlA
V e e-°.7
-
-
-
-
0.55
V
-
-
1.0
JlA
-
-
1.0
JlA
-
5
10
mA
t---~-
2
= 1.6mA
II ILl
Operating
Vin
=0.5 -
-------
~--------
tf
lee
r-~
Stop
= lMHz'"
I--c---~----~-~~----
Standby
---Cin
f
-
Input Capacitance
All Terminals
V
V
Vee-0.5
II Ts ,!
Walt
V
Vee+0.3
-0.3
IOL
VOL
--
Unit
IOH - -200JlA
V ,L
Output "High" Voltage All Outputs
Current DissipatIon * *
min
Vee- O.S
Test Condition
RES, STB'?
'------'- - - --~--~~~--
= lMHz, Vin = OV
• Only at standby
** All output and RES terminal are open, and ponetrate current of Input are not Included.
••• The value at f =xMHz IS given by uSing
(VI H min
=
-2-
mA
5
- - - -1 - - JlA
10
-
2
-1()- j - JlA
-
-
12
pF
Vee - 1.0V, V I L max:;:: O.8V)
lee (I - xMHzi • lee II - lMHzi x x
•
AC CHARACTERISTICS (Vee = 5.0V±10%, Vss = GND. Ta = 0 - +70°C, unless otherwise noted.)
Item
Symbol
Cycle Time
t cvc
Enable Rise Time
tE, ~ __
Test
Condition
Data Set-up Time (Read)
Data Hold Time (Read)
-----,-
tHW
tOSR
- -t - - tHR
HD63A05Y2
typ
max
min
typ
max
-
10
0.5
JlS
20
ns
-
20
-
-
10
20
20
ns
-
-
220
-
-
ns
220
ns
-
-
20
50
-
-
190
0
-
-
10
0.666
20
-
20
-
-
300
300
-
-
250
-
-
-
30
-
200
-
-
30
-
0
-
t---r--:-:--450
FIg. 1
t----
-
f--;w-
40
80
f-- 0
60
160
-
-
20
180
ns
-
ns
120
ns
-
ns
-
ns
~HITACHI
204
Unit
min
-
t- 450
HD63B05Y2
max
1
e--
-~
Data Hold Time (Write)
typ
-
e---- -
Enable Fall Time
tEt
-----Enat,jePUIse Width("High" l;;~)
PW EH
Enable Pulse Width("Low" Level)
PW~
--Address Delay Time
tAD
-- ----Address Hold Time
tAH
-Data Delay Time
tow
HD6305Y2
min
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
ns
HD6305Y2 , HD63A05Y2 , HD63B05Y2
•
PORT TIMING (Vee = 5.0V±10%, Vss = GND, Ta
Item
Symbol
Port Data Set·up Time
(Port A, B, C, D)
tpos
--_.Port Data Hold Time
tpDH
(Port A, B, C, D)
- - - - - - - - - " - - - - - - 1-----Port Data Delay Time
tpDW
(Port A, B, C)
----.~-
•
+70·C, unless otherwise noted.)
--min
.
HD6305Y2
typ
~--
200
-
Flg.3
Unit
min
typ
max
min
typ
max
-
200
-
-
200
-
-
ns
-
-
200
-
-
200
-
-
ns
-
300
-
300
-
-
300
ns
-
200
Flg.2
HD63B05Y2
HD63A05Y2
max
--
r-
i
-
-
CONTROL SIGNAL TIMING (Vee = 5.0V ±10%, Vss = GND, Ta = 0 - +70·C, unless otherwise noted.)
Item
Symbol
INT Pulse Width
INT 2 Pulse Width
RES Pulse Width
tR\I\I"-tcs
Timer Pulse Width
tTWL
OSCillation Start Time (Crystal)
Reset Delay Time
= 22pF
±20%, R,
I
t-=-
:c
-250
tcyc
t lWL2
f----~-
Control Set-up Time
• CL
HD6305Y2
Test
Condition -;;;;;:'l-typ
max
t'WL
-=--------------~
•
=0 -
Test
Condition
tcyc
- +200
-f---- - tcyc
~2~ -
-iTsoi -
-F.;5
I 250 t ~
tcyc
+250
te. sc
Fig 5,Flg 20·
tRHL
Fig. 19
+200
80
-
HD63B05Y2
Unit
typ
max
min
typ
max
-
-
teye
+200
-
-
ns
tcyc
-
-
ns
-
-
+200
250
-
-
tcyc
+200
-
-
ns
-
20
ms
-
ms
5
-
250
-
-
-
teye
+200
-
-
20
-
-
-
20
-
80
-
80
typ
max
min
typ
max
-
21845
0.5
-
-
16384
250
250
ns
-
200
-
-
ns
-
100
-
-
ns
1--
! -
HD63A05Y2
min
5
tCyc
ns
=600 max.
SCI TIMING (Vee = 5.0V±10%, Vss= GND, Ta = 0 - +70·C, unless otherwise noted.)
Item
Symbol
Clock Cycle
tScyc
Data Output Delay Time
tTXD
Data Set-up Time
tSRX
Data Hold Time
tHRX
Test
Condition
Fig.6,
Flg.7
HD63A05Y2
HD6305Y2
min
typ
max
min
1
-
-
-
250
-
200
-
-
200
100
32768 0.67
100
HD63B05Y2
Unit
IJs
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
205
HD6305Y2, HD63A05Y2, HD63B05Y2
t-----------t,y,---------~
E
--PWEl---lI 1"'>----
24V
Ao-AI3
R/W
o 6V
tow
MCU Write
DATAo - DATA,
MCU Read
DATAo - DATA,
FIgure 1 Bus TImIng
E
24V
E
\=v
/
tpow
Port
Port
A.B.C.D
A.B.C
24V
06V
Data
Valid
Figure 3 Port Data Delav Time (MCU Write)
Figure 2 Port Data Set .... p and Hold Times
(MCU Read)
Interrupt
Test
Address
Bus
Data Bus
Op
Code
R/W
Operand Irr.levant
Op Code Data
Vector Vector
PC'3
~dSd~ess~~:ress
first Inst of
Interrupt Routine
\\-_ _ _ _ _---J!
Figure 4 Interrupt Sequence
$
206
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD6305Y2 , HD63A05Y2 , HD63B05Y2
==:=u-L
~~'
Vee
I
,_------.I
------._~-+----------------
Vee-O 5V
Address
Bus
':J-<-m&Il$
AiW
__
Data Bus
-:~,_,--------!~:~~;//p$j;j}__
FigureS Reset Timing
tscyC
Clock Output
Cs/CK
\
o 6V
Data Output
C1/TX
tTXD
06V
I
24V
I
o 6V
t---\
I
24V
)o
6V
I
~ I--Data Input
Cs/RX
\
I
tHRX
20V
20V
08V
o 8V
(
K
\
F'gure6 SCI Timing (Internal Clock)
20V
Clock Input
Cs/CK
o 8V
o 8V
Data Output
24V
C1/TX
o 6V
tSRX
Data Input
20V
20V
C6/RX
o 8V
o 8V
Figure 7 SCI Tlmlng(External Clock)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
207
HD6305Y2, HD63A05Y2, HD63B05Y2
• Data BuslDATAo -DATA,I
This TTL compatible three ..tate buffer can drive one TTL
load and 90pF.
Vee
TTL Load
24kQ
'Pard
~~~t O-----~-----1r---~r-_,
90pF
• Address Bus (ADRo - ADR131
Each terminal is TTL compatible and can drive one TTL
load and 90pF.
12kQ
• Input/Output Terminals lAo - A., Bo - B" Co - C,I
These 24 terminals consist of three 8·bit 110 ports (A, B, C).
Each of them can be used as an input or output terminal on
a bit through program control of the data direction register.
For details, refer to "1/0 PORTS."
[NOTES]
1. The load capacItance includes strav capacItance caused
by the probe. etc.
2. All diodes are 152014 interrupt by
setting bit 4 of the serial status register.
The status of the TNT terminal can be tested by a BIL or
BIH instruction. The TNT falling edge detector circuit and
its latching circuit are mdependent of testmg by these mstruc·
tions. This is also true with the status of the iNTl terminal.
• Miscellaneous Register (MR; $OOOAI
The interrupt vector address for the external mterrupt
INTl is the same as that for the TIMER mterrupt, as shown
in Table I. For this reason, a special register called the miscel·
laneous register (MR, SOOOA) IS available to control the
iNTl interrupts.
Bit 7 of this register is the INTl interrupt request flag.
When the falling edge is detected at the INTl terminal, "I"
is set in bit 7. Then the software in the interrupt routine
(vector addresses: SIFF8, SIFF9) checks bit 7 to see if it
is INTl interrupt. Bit 7 can be reset by software.
M,scellaneous Register (MR;$OOOAI
76543210
IMR~MR61Z1Z1Z1Z1Z1Z1
If
-INTl Interrupt Mask
tNTl Interrupt Request Flag
Bit 61s the INT> interrupt mask bit. If thiS bit is set to "I",
then the INT> interrupt IS disabled. Both read and write are
possible with bit 7 but "I" cannot be written m this bit by
software. ThiS means that an interrupt request by software
IS impossible.
When reset, bit 7 IS cleared to "0" and bit 6 IS set to "\" .
-TIMER
Figure 14 shows a MCU timer block diagram. The IImer
data register is loaded by software and, upon receipt of a
clock input, begins to count down. When the timer data
Vectoring generated
$1FFA. $1FFB
BIH/BIL Test
Condition Code Register (ee)
Minter·
rupt LatCh
INT
I
Falhng Edge Detector
I
}---<>-i----
Vectoring generated
$1 FF8. $1 FF9
TIMER
SCI TIMER,
}-----4>---
Vectoring generated
$1 FF6. $1 FF7
Figure 13 Interrupt Request GeneratIon Circuitry
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
211
HD6305Y2, HD63A05Y2, HD63B05Y2
register (TDR) becomes "0", the timer interrupt request
bit (bit 7) in the timer control register is set. In response to
the interrupt request, the CPU saves its status into 'the stack
and fetches timer interrupt routine address from addresses
$IFF8 and $IFF9 and execute the interrupt routine. The
timer interrupt can be masked by setting the timer interrupt
mask bit (bit 6) in the timer control register. The mask bit
(I) in the condition code register can also mask the timer
interrupt.
The source clock to the timer can be either an external
signal from the timer input terminal or the internal E signal
(the oscillator clock divided by 4). If the E signal is used as
the source, the clock input can be gated by the mput to the
timer input termmal.
Once the timer count has reached "0", It starts counting
down with "$FF". The count can be monitored whenever
desired by reading the limer data register. nus permits the
program to know the length of time having passed after the
occurrence of a timer interrupt, without disturbing the contents of the counter.
When the MCU is reset, both the prescaler and counter are
initialized to logic "I". The timer mterrupt request bit
(bit 7) then is cleared and the timer interrupt mask bit (bit
6) IS set.
To clear the timer interrupt request bit (bit 7), it is necessary to write "0" in that bit.
• Timer Control Register (TCR; $OOO9}
Selection of a clock source, selection of a prescaler frequency division ratio, and a timer interrupt can be controlled
by the timer control register (TCR; S0(09).
For the selection of a clock source, anyone of the four
modes (see Table 2) can be selected by bits 5 and 4 of the
timer control register (TCR).
T,mer Control Register (TCR; $0009}
L-.._ _ _ _ _ _ _ _ _ _ _
After reset, the TCR is initialized to HE under timer terminal control" (bit 5 = 0, bit 4 = I). If the IImer terminal is
"I", the counter starts counting down with "SFF" immediately after reset.
When "I" is written in bit 3, the prescaler is initialized.
This bit always shows "0" when read.
Table 2
TCR7
Timer Interrupt request
o
Absent
TCR
Present
Timer Interrupt mask
L - - - - - - - - - - - - - - T l m e r Interrupt request
Bit 5
Bit 4
0
0
Clock Source Selection
Clock input source
Internal clock E
TCR6
Timer Interrupt mask
0
1
E under timer terminal control
o
Enabled
1
0
No clock input (counting stopped}
D,sabled
1
1
Event input from timer terminal
(Internal
Clockl
E --t---LJ
[>'-"L./
TIMER
Input
Terminal
'---"'T'----..---....... Timer Interrupt
Wnte
Read
Figure 14 Timer Block Diagram
~HITACHI
212
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD6305Y2, HD63A05Y2, HD63B05Y2
A prescaler division ratio is selected by the combination of
three bits (bits 0, 1 and 2) of the timer control register (see
Table 3). There are eight different division ratios: +1, +2,.;.4,
+8, + 16, +32, +64 and +128. After reset, the TCR is set to the
+1 mode.
Table 3
A timer interrupt is enabled when the timer interrupt mask
bit is "0", and disabled when the bit is "1". When a timer
interrupt occurs, "I" IS set in the timer interrupt request bit.
This bit can be cleared by writing "0" in that bit.
-SERIAL COMMUNICATION INTERFACE (SCII
This mterface is used for serial transmission or reception
of 8 bit data. Sixteen transfer rates are available in the range
from 1 IlS to approx. 32 ms (for oscillation at 4 MHz).
The SCI consists of three registers, one octal counter and
one prescaler. (See Fig. IS.) SCI communicates with the CPU
via the data bus, and with the outside world through bits 5,
6 and 7 of port C. Described below are the operations of
each register and data transfer.
Prescaler Division Ratio Selection
0
TCR
Bit 2
Bit 1
Bit 0
Prescaler division ratio
0
0
0
+1
0
0
1
+2
0
1
0
+4
0
1
1
+8
1
0
0
+16
1
0
1
+32
1
1
0
+64
1
1
1
+128
-SCI Control Register (SCR; $00101
SCI Control Registers (SCR; $00101
Transfer
Clock
L-,..-"--r--' Generltor
In,tilli..
SCIITIMERz
Figure 16 SCI Block Diagram
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
213
HD6305Y2, HD63A05Y2, HD63B05Y2
SCR7
Bit 7 (SSR7)
Bit 7 is the SCI interrupt request bit which is set upon
completIOn of transmitting or receiving 8-bit data. It is
cleared when reset or data is written to or read from the
SCI data register with the SCRS="I". The bit can also be
cleared by writing "0" in it.
C, terminal
o
Used as 110 terminal (by DDR).
Serial data output (DDR output)
SCR6
C. terminal
o
Bit 6 (SSR6)
Bit 6 is the TIMER, interrupt request bit. TIMER, is used
commonly with the serial clock generator, and SSR6 is set
each time the internal transfer clock falls. When reset, the
bit is cleared. It also be cleared by writing "0" in it. (For
details, see TIMER,.)
Used as 110 terminal (by DDR).
Serial data input (DDR input)
SCR5 SCR4
0
Clock source
C, terminal
-
0
Used as I/O terminal (by
DDR).
0
1
-
1
0
Internal
Clock output ('DDR output)
1
1
External
Clock input (DDR input)
Bit 7 (SCR7)
When this bit is set, the DDR corresponding to the C,
becomes "I" and this terminal serves for output of SCI data.
After reset, the bit is cleared to "0".
Bit 6 (SCR6)
When this bit is set, the DDR corresponding to the C.
becomes "0" and this terminal serves for input of SCI data.
After reset, the bit is cleared to "0".
Bit 5 (SSRS)
Bit 5 is the SCI interrupt mask bit which can be set or
cleared by software. When it is "I", the SCI interrupt (SSR7)
is masked. When reset, it is set to "I"
Bit 4 (SSR4)
Bit 4 is the TIMER, interrupt mask bit which can be set
or cleared by software. When the bit is "I", the TIMER,
interrupt (SSR6) is masked. When reset, it is set to "I".
Bit 3 (SSR3)
When "I" is written in this bit, the prescaler of the transfer
clock generator is initialized. When read, the bit always is "0".
Bits 2 - 0
Not used.
SSR7
o
Bits 5 and 4 (SCRS, SCR4)
These bits are used to select a clock source. After reset,
the bits are cleared to "0" .
Bits 3 - 0 (SCR3 - SCRO)
These bits are used to select a transfer clock rate. After
reset, the bits are cleared to "0".
SCRI
SCRO
Transfer clock rate
4.00 MHz
4.194 MHz
SCI Interrupt request
Absent
Present
SSR6
o
TIMER, Interrupt request
Absent
Present
SCR3
SCR2
0
0
0
0
1 j.l1
0.95j.1s
0
0
0
1
2/1s
1.91
0
0
1
0
4/1s
3.82 j.lS
0
0
1
1
8j.1s
7.64/1s
SSR4
I
I
I
I
I
I
1
o
1
1
1
32768/1s
1/32 s
SSR5
o
SCI Interrupt mask
Enabled
Disabled
j.lS
TIMER, Interrupt mask
Enabled
DISabled
• Data Transmission
-SCI Data Reginer (SDR; $0012)
A serial-parallel conversion register that is used for transfer
of data.
-SCI Status Register (SSR; $0011)
76543210
By writing the desired control bits into the SCI control
registers, a transfer rate and a source of transfer clock are
determined and bits 7 and 5 of port C are set at the serial
data output terminal and the serial clock terminal, respectively. The transmit data should be stored from the accumulator or index register into the SCI data register. The data
written m the SCI data register is output from the C,/Tx
terminal, starting WIth the LSB, synchronously with the
falling edge of the serial clock. (See Fig. 16.) When 8 bit of
~HITACHI
214
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305Y2, HD63A05Y2, HD63B05Y2
data have been transmitted, the interrupt request bit is set in
bit 7 of the SCI status register with the rising edge of the last
serial clock. This request can be masked by setting bit 5 of the
SCI status register. Once the data has been sent, the 8th bit
data (MSB) stays at the C,/Tx terminal. If an external clock
source has been selected, the transfer rate determined by
bits 0 - 3 of the SCI control register is ignored, and the Cs/
CK terminal is set as input. If the internal clock has been.
selected, the Cs/CK terminal is set as output and clocks are
output at the transfer rate selected by bits 0 - 3 of the SCI
control register.
Figure 16 SCI Timing Chart
• Data Reception
By writing the desired control bits IOta the SCI control
register, a transfer rate and a source of transfer clock are de·
termined and bit 6 and 5 of port C are set at the serial data
input terminal and the serial clock tenninal, respectively.
Then dummy.writing or ·reading the SCI data register, the
system is ready for receiving data. (This procedure is not
needed after reading subsequent received data. It must be taken
after reset and after not reading subsequent received data.)
The data from the C6 /Rx terminal is input to the SCI
data register synchronously with the rising edge of the
serial clock (see Fig. 16). When 8 bits of data have been received, the interrupt request bit is set in bit 7 of the SCI
status register. This request can be masked by setting bIt 5
of the SCI status register. If an external clock source have been
selected, the transfer rate determined by bits 0 - 3 of the SCI
control register is ignored and the data is received synchronously with the clock from the CS /CK terminal. If the internal
cIock has been selected, the CS /CK terminal is set as output
and cIocks are output at the transfer rate selected by bits 03 of the SCI control register.
TIMER, is commonly used WIth the SCI transfer clock
generator. If wanting to use TIMER, !Odependently of the
SCI, specify "External" (SCRS = 1, SCR4 = 1) as the SCI
clock source.
If "Internal" is selected as the clock source, reading or
wntmg the SDR causes the prescaler of the transfer clock
generator to be mitialized.
-I/O PORTS
There are 24 input/output temunals (ports A, S, C). Each
I/O tenninal can be selected for either input or output by the
data direction register. More specifically, an I/O port will
be input if "0" is written ill the data direclton register, and
output if "1" is written 111 the data dueclton register. Port A,
S or C reads latched data if it has been programmed as output,
even with the output level being fluctuated by the output
load. (See FIg. 17.)
When reset, the data dIrection register and data regISter go
to "0" and all the illput/output termonals are used as input
Bit of data
direction
register
Bit of
output
data
Status of
output
Input to
CPU
1
0
0
0
1
1
1
1
0
X
Figure 17
.TIMER2
The SCI transfer clock generator can be used as a timer.
The clock selected by bits 3 - 0 of the SCI control register
(4 /.IS - approx. 32 ms (for oscillation at 4 MHz)) is input to
bit 6 of the SCI status register and the TlMER2 interrupt
request bit is set at each falling edge of the clock. Since interrupt requests occur periodically, TlMER2 can be used as a
reload counter or clock.
:Tranlfer clock generator it r,"t and muk bit (bit 4
of SCI stltU' regilter) it cl.ared.
(3),@ : TlMER2 interrupt requllt
@.@ : TIMERl Int.rrupt request bIt cl.ared
$
3-state
Pin
Input/Output Port Diagram
Seven input.only terminals are available (port D). Writing
to an input tenninal is invalid.
All input/output terminals and input terminals are TTL
compatible and CMOS compatible in respect of both input and
output.
If I/O ports or input ports are not used, they should be
connected to VSS via resistors. With none connected to these
terminals, there is the possibility of power being consumed
despite that they are not used.
-RESET
The MCU can be reset either by external reset input (RES)
or power-on reset. (See Fig. 18.) On power up, the reset
input must be held "Low" for at least tose to assure that the
internal oscillator is stabilized. A sufficient time of delay can
be obtained by connecting a capacitance to the RES input as
shown in Fig. 19.
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
215
HD6305Y2, HD63A05Y2, HD63B05Y2
45V·~----------------/
5V
Vcc
OV----------~
~::;;al
____________________
C,
--J
Figure 18
requirement for minimum external configurations. It can be
driven by connecting a crystal (AT cut 2.0 - 8.0MHz) or
ceramic oscillator between pins 5 and 6 depending on the required oscillation frequency stability.
Three different terminal connections are shown in Fig. 20.
Figs. 21 and 22 illustrate the speCifications and typical arrangement of the crystal, respectively.
~~
XTAL~0EXTAL
Power On and Reset Timing
Figure 21
AT Cut
Paraliel
Resonance
Co=7pF max
f=2 0-8 OMHz
Rs=6OQ max
Parameters of Crystal
100kU typ
la)
HD6305Y
MCU
Figure 19
Input Reset Delay CirCUit
-INTERNAL OSCILLATOR
The mternal oscillator ClfCUlt
IS
deSigned to meet the
I NOTE J
Use as short WIrings as poSSible for connection of the crystal
with the EXTAL and XTAl terminals 00 not allow these
wIrings to cross others
EXTAL
~t
20-80MHz=
XTAL
Figure 22
HD6305Y
MCU
10-22pF 120%
Typical Crystal Arrangement
-LOW POWER DISSIPATION MODE
The HD6.l05Y has three low power diSSipation modes:
wait, stop and standby.
Crystal Oscillator
CLi
~"D
EXTAL
XTAL
HD6305Y
MCU
Ceramic OSClliator
External
Clock
Input
EXTAL
NC
XTAL HD6305Y
MCU
External Clock Drive
Figure 20
Internal Oscillator CirCUit
• Wait Mode
When WAIT lOst ruction being executed, the MCU enters
into the wait mode. In this mode, the oscillator stays active
but the internal clock stops. The CPU stops but the peripheral
functions - the timer and the serial communication interface _. stay achve. (NOTE: Once the system has entered the
wait mode, the serial communication IOterface can no longer
be retriggered.) In the wait mode, the regISters, RAM and I/O
terminals hold their condition just before eptering into the
wait mode.
The escape from this mode can be done by interrupt (INT,
TIMER/INT> or SCI/TIMER», RES or STBY. The RES
resets the MCU and the STBY brings it into the standby
mode. (This will be mentIOned later.)
When mterrupt is requested to the CPU and accepted, the
W8Jt mode escapes, then the CPU is brought to the operation
mode and vectors to the interrupt routine. If the interrupt is
masked by the I bit ()f the condition code register, after releasmg from the wait mode the MCU executes the instruction
next to the WAIT. If an interrupt other than the INT (i.e.,
TIMER/INT> or SCI/TIMER» IS masked by the timer control
~HITACHI
216
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. 0 Brisbane, CA 94005-1819 0(415) 589-8300
HD6305Y2, HD63A05Y2, HD63B05Y2
regISter, miscellaneous register or senal status register, there
IS no mterrupt request to the CPU, so the walt mode cannot
be released
Fig. 23 shows a flowchart for the walt functIOn.
• Stop Mode
When STOP mstructlOn bemg executed, MCU enters mto
the stop mode. In tlus mode, the oscillator stops and the CPU
and penpheral functions become macllve but the RAM,
regISters and I/O termmals hold their condllton Just before
entenng mto the stop mode.
The escape from thIS mode can be done by an external
mterrupt (INT or INT2), RES or STBY. The RES resets the
MCU and the STBY bnngs mto the standby mode.
When mterrupt is requested to the CPU and accepted,
the stop mode escapes, then the CPU is brought to the operalion mode and vectors to the interrupt routine. If the mterrupt IS masked by the I bit of the condllton code register,
after releasmg from the stop mode, the MCU executes the
mstructlOn next to the STOP If the INT2 interrupt IS masked
by the mIScellaneous register, there IS no interrupt request to
the MCU, so the stop mode cannot be released
Fig. 24 shows a flowchart for the stop funchon. Fig. 2S
shows a timing chart of return to the operatIOn mode from
the stop mode
For releasmg from the stop mode by an mterrupt, oscillatIOn starts upon mput of the mterrupt and, after the mternal
delay time for stablllled OSCillation, the CPU becomes active .
For restartmg by RES, oSCIllalton starts when the RES goes
"0" and~ CPU restarts when the RES goes "I". The duration 01 RES="O" Ill",t exceed 30 '"' to J"Ure >tablilled ",clilatlOn
• Standby Mode
The MCU enters mto the standby mode when ".: STBY
termmal goes "Low" In tillS mode. all operations stop and
the mternal conditIOn IS reset but the contents of the RAM are
hold. The I/O termmals turn to high-Impedance state The
standby mode should escape by bnngmg STB'? "High" The
CPU mu>! be restarted hy reset The tlmmg of mput Signals
at the RES and SIBY terminals IS shown HI hg 2h
Table 4 lists the status of each parts of the MCU III each
low power diSSipatIOn moues 1 ranslhon~ between each mode
are shown In Fig 27
(Note)
When I bit of condition code regISter IS "I" and mterrupt
(INT, TlMER/INT 2, SCI/TiMER z ) IS held, MCU does not
enter WAIT mode by the execution of WAIT mstructlOn.
In that case, after the 4 dummy cycles MCU executes the next
instruction
In the same way, when external mterrupts (INT, INT 2 ) are
held at the bit I set, MCU does not enter STOP mode by the
executIOn of STOP mstructlOn In that case, also, MCU executes
the next mstructlOn after the 4 dummy cycles.
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
217
HD6305Y2, HD63A05Y2, HD63B05Y2
Oscillator Active
Timer and Senal
Clock Active
All Other Clocks
Stop
Initialize
CPU, TIMER, SCI,
I/O and All
Other Functions
No
No
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 23 Wait Mode Flow Chart
•
218
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305Y2, HD63A05Y2, HD63B05Y2
Stop Oscillator
and All Clocks
No
Turn on Oscillator
Walt for Time Delay
to Stabilize
Turn on Oscillator
Walt for Time Delay
to Stabilize
1=0
1=1
Load PC from
Interrupt Vector
Addresses
Fetch
Instruction
Figure 24 Stop Mode Flow Chart
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
219
HD6305Y2, HD63A05Y2, HD63B05Y2
o."~m'~:I--_~-I-/~_~
f
t.
STOP instruction
Interrupt
Time required for oscillation to become ~
-~tions
remn
stabilized (built-In delay time)
U~~
(a) Restart by Interrupt
Oscillator
E
11111111111111111111111111111
~~~~
Time required for OSCillation to become
stabll,zed (tos e )
STOP instruction
executed
.~
Reset
I start
(b) Restart by Reset
Figure 25
Timing Chart of Releasing from Stop Mode
\'-------lH~_~1
.,.
I
I
I
I
I
~-4--l-_-~.~---------4r---------~----------J
tose
Figure 26
Table 4
Restart
Timing Chart of ReleaSing from Standby Mode
Status of Each Part of MCU in Low Power DISsipation Modes
Condition
Mode
WAIT
---
Start
WAIT
Software
STOP
Standby
In-
struction
STOP instructlon
Hardware
STBY="Low"
Escape
Osclllator
CPU
Timer,
Sen.1
RegISter
RAM
Active
Stop
Active
Keep
Keep
Keep
STBY, RES,INT,INT.,
each interrupt request of
TIMER, TIMER., SCI
Stop
Stop
Stop
Keep
Keep
Keep
STBY, RES, INT, INT.
Stop
Stop
Stop
Reset
Keep
High impedance
I/O
terminal
STBY="Hlgh"
~HITACHI
220
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy_ • Brisbane, CA 94005-1819 • (415) 589-8300
HD6305Y2, HD63A05Y2, HD63B05Y2
Figure 27
TranSitions among Active Mode, Walt Mode,
Stop Mode, Standby Mode and Reset
-BIT MANIPULATION
The MCU can use a smgle instructIOn (BSET or BCLR) to
set or clear one bit of the RAM wlthm page 0 or an I/O port
(except the wflte-only regISters such as the data dlfectlOn
register) Every bit of memory or I/O wlthlll page 0 (SOO $FF) can be tested by the BRSET or BRCLR 111structlon,
dependmg on the result of the test, the program can branch to
re'lUlred dc>tlllattom Smce btts m the RAM on page 0, Ot I/O
can be mantpulated, the user may usc a bit wlthm the RAM on
page 0 as a flag or handle a smgle I/O bit as an mdependent
I/O tctmmal Fig 2R shows an example of bit mallipulatl
Read/W rite (R/W)
Two pins supply power to the part: Vss is ground
or 0 volts, while Vcc is +5.0 V ±10%.
This signal indicates the direction of data trans·
fer on the data bus. A low indicates that the MPU
is writing data onto the data bus. RIW is made high
impedance when BA is high. Refer to figures 25 and
26.
Address Bus (Ao - A1S)
Sixteen pins output address information from the
MPU onto the address bus. When the processor
does not require the bus for a data transfer, it will
output address FFFF16, R/W = high, and BS=low.
This is a "dummy access" or VMA cycle (see fig·
ures 25 and 26). All address bus drivers are made
high impedance when the bus available output (BA)
is high. Each pin will drive one Schottky TTL load
or four LS TTL loads, and typically 90 pF.
Reset (RES)
Data Bus (Do - D7 )
A low level on this Schmitt-trigger input for
greater thaf\ one bus cycle will reset the MPU, as
shown in fi~ure 3. The reset vectors are fetched
from locations FFFE16 and FFffi6 (table 2) when
interrupt aclmowledge is true, ( BA . BS = 1). During
initial power-on, the reset line should be held low
until the clock oscillator is fully operational. See
figure 4.
These eight pins provide communication with the
system bi-directional data bus. Each pin will drive
one Schottky TTL load or four LS TTL loads, and
typically 130 pF.
Because the HD6309 reset pin has a Schmitttrigger inpllt with a threshold voltage higher than
that of standard peripherals, a simple RIC network
may be used to reset the entire system. This higher
Table 1. Pin Description
Symbol
Pin No.
I/O
Function
Ground
Vss
NMI
2
Non maskable interrupt
IRQ
3
Interrupt request
FIRQ
4
Fast interrupt request
BS, BA
5, 6
Vcc
7
Ao -A'5
8-23
0
Address bus, bits 0-15
D7 -Do
24-31
I/O
Data bus, bits 0-7
RM
32
0
Read / Write output
DMA/BREQ
33
E, Q
34, 35
MRDY
36
Memory ready
RES
37
Reset input
EXTAL, XTAL
38, 39
Oscillator connection
HALT
40
Halt input
0
Bus status, Bus available
+ 5 V power supply
DMA
0
Bus request
Clock signal
~HITACHI
236
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
HD63B09, HD63C09
threshold voltage ensures that all peripherals are
out of the reset state before the processor.
Halt (HALT)
A low level on this input pin will cause the MPU
to stop running at the end of the present instruction
and remain halted indefinitely without loss of data.
When halted, the BA output is driven high indicating the buses are high impedance. BS is also high
which indicates the processor is in the halt or bus
grant state_ While halted, the MPU will not respond
to external realtime requests (FIRQ, IRQ) although
DMA/BREQ will always be accepted, and NMI or
RES will be latched for later response. During the
halt state, Q and E continue to run normally. If the
MPU is not running (RES), a halted state (BA . BS
= 1) can be achieved by pulling HALT low while
RES is still low. See figure 5.
Bus Available, Bus Status (BA, BS)
The BA output is an indication of an internal
control signal which makes the MOS buses of the
MPU high impedance. This signal does not imply
that the bus will be available for more than one
cycle. When BA goes low, an additional dead cycle
will elapse before the MPU acquires the bus.
The BS output signal, when decoded with BA,
represents the MPU state.
Table 2. Memory Map for Interrupt Vectors
Memory Map for
Vector Locations
MS
LS
Interrupt Vector
Description
FFFE
FFFC
FFFA
FFF8
FFF6
FFF4
FFF2
FFFO
FFFF
FFFD
FFFB
FFF9
FFF7
FFF5
FFF3
FFF1
RES
NMI
SWI
IRQ
FIRQ
SWI2
SWI3
Reserved
Interrupt Acknowledge is indicated during both
cycles of a hardware vector fetch (RES, NMI,
FIRQ, IRQ, SWI. SWI2, SWI3). This signal, plus
decoding of the lower four address lines, can provide the user with an indication of which interrupt
level is being serviced and allow vectoring by
device. See Table 2.
Sync Acknowledge is indicated while the MPU is
waiting for external synchronization on an interrupt line.
Halt/Bus Grant is true when the HD6309 is in a
halt or bus grant condition.
Non Maskable Interrupt (NMI)
A negative edge on NMI requests that a nonmask able interrupt sequence be generated. A nonmask able interrupt cannot be inhibited by the program, and also has a higher priority than FIRQ,
IRQ or software interrupts. During recognition of
an NMI. the entire machine state is saved on the
hardware stack. After reset, an NMI will not be
recognized until the first program load of the
hardware stack pointer (S). The pulse width of NMI
low must be at least one E cycle. If the !'IMI input
does not meet the minimum set up with respect to
Q, the interrupt will not be recognized until the next
cycle See figure 6.
Table 3.
BA
BS
0
0
0
1
1
0
1
1
MPU State Definition
MPU State
Normal (Running)
Interrupt or RESET Acknowledge
SYNC Acknowledge
HALT or Bus Grant
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
237
::r:
N
CAl
t::J
ex>
CJ)
w
tJj
::r:
o
s:
("">
(0
3
(1)
::r:
=»
t::J
::>.
(")
CJ)
.?'
w
~
(')
c.
o
•
(0
:;;
~
=-
-0
~
'"•
8""
E
~~
_
~-0 J:
2. ~
3.
»
Jf(')
~ J:
•
co
::>.
en
0-
w
::::l
(1)
C")
»
~~.~
40V
RES
I
08V
0 8V"'t'
U««((((((((~
~
O.8V I
'
~~
Add~: \\\\\\\\\~
R/W.\§\\\§ssf~
~~
'C
D.m~~~~~~~~~---V--~~--~--~~~V----V--~r---~---V~.--V---,,--~r---~---V--~r---~---V----V----V--~r---~--~
Bus ~~~~~~~~~~---n---J~--~--~N~mN~~P~C~N~mN--P~C~V~A~F~inrt--~---n~.~~--~---'~--~--~---J'---~--~New~~P~C~N~mN--~PC~V~M~A~F~i~-t-J'---~
BA \\\SS\\\~
...............
"S \\W\\\\\(~
(
HI Byte Lo Byte
I
\
Instruction
(I
HI Byte Lo Byte
r,
I
'R
o
~
~
<0
•
~
,£!
01
00
'P
00
w
g
Figure 3. RES Timing
Instruction
,'-_ _ _ __
HD63B09, HD63C09
1~4~.5~V----~'~-------------------VCC _ _- ,
E
-------+----f
RES
tRC
HD6309
V
C1n
C-
12 MHz
10~20 pF ± 20%
10~20
pF ±20%
8 MHz
1O~20
10~20
pF ±20%
pF ±20%
38
39
y
0
J;C~
Gn~
AT Cut Parallel Resonance Crystal
Co =7 pF max
Rs=60 n max
Figure 4. Crystal Connections and Oscillator Start Up
2nd To Last Last Cycle
Cvele of
of
Current
j !nst
.,
Current Dead
Inst Cycle
j.
Dead
j
In~=O~nstructlon
Deed
1ff--_ _ _.!.!H""alted=-_ _ _ _.+I•..:C;.:..vci:;,;e:...+-I_-I'.-,ex:::ec:::ute::;.+I_Cy.:..cIe-l.II• ...!.H~alted=-
Q
e
iiALi'
-----"":"I"
tPCS~~tPCf
tPCr
0.8 V
~~----------~,:,~----~~~
Address ---","'--~r---"
VIHI~.8 V
F~~~t-~-SH---------------------
>------4~---------------------,--y---"\----'---"--/
Bus
Fetch
Execute
Rm--~~r--y-->-----,~----------------~------BS _ _ _ _ _ _ _ _ _ _ _ _
Data
Bus
/
\\.,________--J/
r---~I~f---------------~\
BA
J
"
r---~--)_----~II----------------------~~-----
Opcode
Figure 5. HALT and Single Instruction Execution for System Debug
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300
239
HD63B09, HD63C09
Last Cycle
of Current
I"""""",,,
Instruction
..
'I-'"II,..--------------Interrupt Stacking
'1
and Vector Fetch Sequence
,.,,"
·1
Q
--~~~~~~~~~~~~~~~CA~~r
RIW"r::x=Y
Figure 6. IRQ and NMI Interrupt Timing
Last Cycle
of Current
Instruction
I..
m-2
Instruction
Fetch
Interrupt Stacking and Vector Fetch Sequence ------------I-----l
-II
m-l
"I"
III'"
Q
Add~~r_~~r---~.r_----\r--
___ r_--~r---~r---~r--__. r _ - -__ r_--~r_-~,,_----\r----'r----'r--
Bus
D.~
__~~__~,'_____A_____~____~____J~____J~____J~____J, ____J \ ____J \ _____',~___f~__~,'-_____
VMA
PCl
PCH
CC
New
New
PCH
PCl
''-___--'1
Figure 7. FIRQ Interrupt Timing
~HITACHI
240
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09, HD63C09
instruction they may not be recognized.
However, NMI is latched and need only
remain low for one cycle.
Fast Interrupt Request (FIRQ)
A low level on FIRQ input will initiate a fast
interrupt sequence provided its mask bit (F) in the
CC is clear. This sequence has priority over the
standard interrupt request (IRQ). It is fast in the
sense that it stacks only the contents of the condi·
tion code register and the program counter. The
interrupt service routine should clear the source of
the interrupt before doing an RTI. See figure 7.
Interrupt Request (IRQ)
A low level input on IRQ will initiate an interrupt
request sequence provided the mask bit (I) in the CC
is clear. Since IRQ stacks the entire machine state
it provides a slower response to interrupts than
FIRQ. IRQ also has a lower priority than FIRQ.
Again, the interrupt service routine should clear the
source of the interrupt before doing an RTI. See
figure 6.
Note: NMI, FIRQ, and IRQ requests are sampled on
the falling edge of Q. One cycle is required
for synchronization before these interrupts
are recognized. The pending interrupt(s) will
not be serviced until completion of the cur·
rent instruction unless a SYNC or CWAI
condition is present. IfIRQ and FIRQ do not
remain low until completion of the current
XTAL,EXTAL
These two pins are connected with parallel resonant fundamental crystal, AT cut. Alternately, the
pin EXTAL may be used as a TTL level input for
external timing with XTAL floating. The crystal or
external frequency is four times the bus frequency.
See figure 4. Proper RF layout techniques should be
observed in the layout of printed circuit boards.
Note for Board Design of the OsciUation Circuit: In designing the board, the following notes
should be taken when the crystal oscillator is used.
See figure 8.
1. Crystal oscillator and load capacity Cin, Cout
must be placed near the LSI as much as possible. (Normal oscillation may be disturbed
when external noise is induced to pin 38 and
39.)
2. Pin 38 and 39 signal line should be wired apart
from other signal line as much as possible.
Don't wire them in parallel with other lines.
(N ormal oscillation may be disturbed when E
or Q signal feeds back to pin 38 and 39.)
o
r-~~~'-__~IICO~
ch
HD6309
Figure 8. Board Design of the Oscillation Circuit
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
241
HD63B09, HD63C09
Designs to be A voided: A signal line or a
power source line must not cross or go near the
oscillation circuit line as shown in figure 9 to prevent induction from these lines. The resistance
between XT AL, EXT AL and other pins should be
over 10 MO.
bus accesses. MRDY may also be used to stretch
clocks (for slow memory) when bus control has
been transferred to an external device (through the
use of HALT and DMA/BREQ).
E,Q
DMA Bus Request (DMA/BREQ)
E is similar to the HD6800 bus timing signal <1>2: Q
is a quadrature clock signal which leads E. Q has no
parallel on the HD6800. Data is latched on the
falling edge of E. Timing for E and Q is shown in
figure 10.
The DMA/BREQ input provides a method of
suspending execution and acquiring the MPU bus
for another use, as shown in figure 12. Typical uses
include DMA and dynamic memory refresh.
MRDY also stretches E and Q during dead cycles.
Transition of DMA/BREQ should occur during
Q. A low level on this pin will stop instruction
execution at the end of the current cycle. The MPU
will acknowledge DMA/BREQ by setting BA and
BS to high level. The HD6309 does not perform the
auto-refresh executed in the HD6809. See figure 13.
Memory Ready (MRDY)
This input control signal allows stretching of E
and Q to extend data-access time. E and Q operate
normally while MRDY is high. When MRDY is low,
E and Q may be stretched in integral multiples of
half (1/2) bus cycles, thus allowing interface to slow
memories, as shown in figure 11. The maximum
stretch is 5 microseconds.
Typically, the DMA controller will request to use
the bus by asserting DMA/BREQ pin low on the
leading edge of E. When the MPU replies by setting
BA and BS to one, that cycle will be a dead cycle
used to transfer bus mastership to the DMA controller.
During nonvalid memory access (VMA cycles)
MRDY has no effect on stretching E and Q: this
inhibits slowing the processor during "don't care"
Must be avoided.
<1: IX!
ii "i
c: I:
'" iii'"
iii
o
I
I
1\
: '
------I---'-,--',------5ignal
C
Cout
39 --,XTAL
t---,
--' ::E!!;
.
m
38--'~'~-"~
~-~~
....... EXT~L
,
Cin
m
I
I
I
,
I
I
Example of Normal Oscillation may be Disturbed
•
242
I
I
,
I
HD6309
Figure 9.
,
I
I
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09, HD63C09
False memory accesses may be prevented during
dead cycles by developing a system DMA VMA
signal which is low in any cycle when BA has
changed.
high), another dead cycle will elapse before the
MPU accesses memory, to allow transfer of bus
mastership without contention.
The DMA/BREQ input should be tied high during
reset state.
When BA goes low (a result of DMA/BREQ--
End of Cycle (Latch Datal
Start of Cycle
I
I
I
,--_ _ _ _ _-...1
EX-O.8V
rr-
1
a
tAVS
1
/
't-O.8V
~~~~________~
:VCC-2.0V
\
11
_____.....1_ _ __
I
1
Figure 10. E/Q Relationship
\'---..J1
o
,
\
\
Vee - 2.0V
MRDY
Figure 11. MRDY Clock Stretching
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
243
HD63B09, HD63C09
MPU Operation
During normal operation, the MPU fetches an
instruction from memory and then executes the
requested function. This sequence begins at RES
and is repeated indefinitely unless altered by a
special instruction or hardware occurrence. Soft·
MPU
ware instructions that alter normal MPU operation
are: SWI, SWI2, SWI3, CWAI, RTI and SYNC. An
interrupt, HALT or DMA/BREQ can also alter the
normal execution of instructions. Figure 14 illus·
trates the flow chart for the HD6309.
DEAD
DMA
MPU
DEAD
Q
BA, BS
\~-------'/
ADDR
fMPUI
"-
____~)r-----------------~C
f~~~~1 ---------------------«~__________________________________J)~--------*DMAVMA is developed externally. but it is a system requirement for DMA.
Figure 12. Typical DMA Timing
10EAOI.
I
I I
OMACyc'..- - - - - - - - - - - - - - - - - - _
2
3
4
5
6
7
6
9
10
11
12
13
14
15
16
17
16
19
20
E
Q
DMA/BREQ
I
I
I
I
I
~~I~~
____________________________________________________________
I
B~BS ---fr~------------------------------------------------------------I
,
DMAVMA*~~----------------------------------------------------------*DMAVMA is developed externally, but it is a system requirement for DMA.
The HD6309 does not perform the auto-refresh executed in the HD6809.
Figure 13. DMA Timing
~HITACHI
244
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005·1819 • (415) 589·8300
::t:
~
2:
»
3
'"n
:::!.
!"
~
•
~
""C
[
•
§""
~.
~
:t
a~
~
""CO
.fJ:
·-
ttl
lii·
C"
~
'"
§;
~
~
HD6309 Interrupt Structure
•
Bus State
BA
BS
ttl
tJ
(J)
c.v
Running
o
o
o
co
~
..£!
~
Interrupt or Reset Acknowledge
g
Sync
Note: Asserting RES will result in entering the reset sequence from any point on the flow chart.
Halt/Bus Grant
N
~
C11
Figure 14. Flowchart for HD6309 Instruction
o
o
OJ
<.0
6
(J)
c.v
(')
o
<.0
HD63B09, HD63C09
Addressing Modes
The basic instructions of any computer are
greatly enhanced by the presence of powerful addressing modes. The HD6309 has the most complete
set of addressing modes available on any microcomputer today. For example, the HD6309 has 59
basic instructions, however, it recognizes 1464 different variations of instructions and addressing
modes. The addressing modes support modern programming techniques. The following addressing
modes are available on the HD6309:
•
•
•
•
•
•
•
•
•
•
extended instruction defines an absolute address
and is not position independent. Examples of
extended addressing include:
LDA
STX
LDD
CAT
MOUSE
$2000
Extended Indirect
As a special case of indexed addressing (discussed below), one level of indirection may be added to
extended addressing. In extended indirect, the two
bytes following the postbyte of an indexed instruction contain the address of the data.
Implied (includes accumulator)
Immediate
Extended
Extended indirect
Direct
Register
Indexed
- Zero-offset
-Constant offset
- Accumulator offset
- Auto increment/decrement
Indexed indirect
Relative
Program counter relative
LDA
LDX
STU
[CAT)
[$FFFE)
[DOG)
Direct Addressing
Implied (Includes Accumulator)
In this addressing mode, the opcode of the
instruction contains all the address information
necessary. Examples of implied addressing are:
ABX, DAA, SWI, ASRA, and CLRB.
Immediate Addressing
In immediate addressing, the effective address of
the data is the location immediately following the
opcode (i.e., the data to be used in the instruction
immediately follows the opcode of the instruction).
The HDS309 uses both 8-and IS-bit immediate
values depending on the size of the argument specified by the opcode. Examples of instructions with
immediate addressing are:
LDA #$20
LDX #$FOOO
LDY #CAT
Direct addressing is similar to extended addressing except that only one byte of address follows the
opcode. This byte specifies the lower 8 bits of the
address to be used. The upper 8 bits of the address
are supplied by the direct page register. Since only
one byte of address is required in direct addressing.
this mode requires less memory and executes faster
than extended addressing. Of course. only 256 locations (one page) can be accessed without redefining
the contents of the DP register. Since the DP register is set to $00 on reset, direct addressing on the
HD6309 is compatible with direct addressing on the
HD6800. Indirection is not allowed in direct addressing. Some examples of direct addressing are:
LDA
SETDP
LDB
LDD
$30
$10 (Assembler directive)
$1030
(temp)
calculate the EA; temp is a
holding register
perform autoincrement
do store operation
Indexed Indirect
The byte(s) following the branch opcode is (are)
treated as a signed offset which may be added to
the program counter. If the branch condition is true
then the calculated address (PC + signed offset) is
loaded into the program counter. Progtam execution continues at the new location as indicated by
the PC. Short (1 byte offset) and long (2 bytes offset)
relative addressing modes are available. All of
memory can be reached in long relative addressing
as an effective address is interpreted modulo 216.
Some examples of relative addressing are:
DOG
BEQ
BGT
LBEQ
LBGT
RAT
RABBIT
NOP
NOP
CAT
CAT
DOG
RAT
RABBIT
(short)
(short)
(long)
(long)
All of the indexing modes with the exception of
.HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
249
HD63B09, HD63C09
Program Counter Relative
tive to the program counter. Examples are:
The PC can be used as the pointer register with 8
-or 16-bit signed offsets. As in relative addressing,
the offset is added to the current PC to create the
effective address. The effective address is then used
as the address of the operand or data. Program
counter relative addressing is used for writing
position independent programs. Tables related to a
particular routine will maintain the same relation·
ship after the routine is moved, if referenced rela·
LDA
LEAX
CAT, PCR
TABLE, PCR
Since program counter relative is a type of indexing, an additional level of indirection is available.
LDA
LDU
(CAT, PCR]
[DOG, PCR]
HD6309 Instruction Set
The instruction set of the HD6309 is similar to
that of the HD6800 and is upward compatible at the
source code level. The number of opcodes has been
reduced from 72 to 59, but because of the expanded
architecture and additional addressing modes, the
number of available opcodes (with different addressing modes) has risen from 197 to 1464.
Some of the instructions and addressing modes
are described in detail below:
PSBU/PSBS
hardware stack (S) or user stack (U) any single
register, or set of registers with a single instruction.
PULU/PULS
The pull instructions have the same capability of
the push instruction, in reverse order. The byte
immediately following the push or pull opcode
determines which register or registers are to be
pushed or pulled. The actual PUSH/PULL
sequence is fixed: each bit defines a unique register
to push or pull, as shown in figure 16.
The push instructions can push onto either the
Push/Pull Postbyte
I I I I I I I I I
I~ AB
CC
DP
X
Y
stu
PC
..... Pull Order
Push Order-+
PC U Y X DP B A CC
FFFF··· ..... increasing memory address···OOOO
PC 5 Y X DP B A CC
Figure 16. Push and Pull Order
~HITACHI
250
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09, HD63C09
TFR/EXG
Within the HD6309, any register may be trans·
ferred to or exchanged with another of like-size: i.
e., 8-bit to 8-bit or 16-bit to 16-bit. Bits 4-7 of the
postbyte define the source register, while bits 0-3
represent the destination register (figure 17). They
are denoted as follows:
OOOO-D
0001-X
0010- Y
0101-PC
1000-A
1001-B
1010-CC
1011-DP
OOll-U
0100-S
Note: All other combinations are undefined and
invalid.
writing MSGl, PCR. the assembler computes the
distance between the present address and MSGl.
This result is placed as a constant into the LEAX
instruction which will be indexed from the PC value
at the time of execution. No matter where the code
is located, when it is executed, the computed offset
from the PC will put the absolute address of MSG 1
into the X pointer register. This code is totally
position independent.
The LEA instructions are very powerful and use
an internal holding register (temp). Care must be
exercised when using the LEA instructions with the
autOincrement and autodecrement addressing
modes due to the sequence of internal operations.
The LEA internal sequence is outlined as follows:
LEAa ,b+
LEAX/LEA Y/LEAU /LEAS
The LEA (load effective address) works by cal·
culating the effective address used in an indexed
instruction and stores that address value, rather
than the data at that address, in a pointer register.
This makes all the features of the internal address·
ing hardware available to the programmer. Some of
the implications of this instruction are illustrated in
table 5.
The LEA instruction also allows the user to
access data in a position independent manner. For
example:
LEAX MSGl, PCR
LBSR PDA T A(Print message routine)
MSGl FCC 'MESSAGE'
LEAa ,-b
1. b -1 .... temp
2. b -1 .... b
3. temp-a
(calculate EA with prede·
crement)
(modify b, predecrement)
(load a)
Autoincrement-by-two and autodecrement-bytwo instructions work similarly. Note that LEAX,
X + does not change X, however LEAX, - X does
decrement X. LEAX I, X should be used to incre·
ment X by one.
MUL
This sample program prints: 'MESSAGE'. By
Multiplies the unsigned binary numbers in the A
Table 5. LEA Examples
Transfer/Exchange Postbyte
:Soyrce:
1. b-temp
2. b + I-b
3. temp-+a
(any of the 16-bit pointer
registers X, Y, U, or S
may be substituted for a
and b)
(calculate the EA)
(modify b, postincrement)
(load a)
I D~sti~atiqn I
Innructlon
Operation Comment
LEAX 10. X
X+10-X
Adds 5-bit constant 10
to X
LEAX 500. X X+500-X Adds 1 6-bit constant
500 to X
LEAY A. Y
Y+A-Y
Adds 8-bit A accumulator to V
LEAY D. Y
Y+D-V
Adds 16-blt 0 accumulator to V
LEAU-10. U U-10-U
Subtracts 10 from U
LEA5-10.5 5-10-5
Used to reserve area on
stack
LEA510,5 5+10-5
Used to 'clean up' stack
LEAX 5,5
5+5-+X
Transfers as well as adds
Figure 17. TFR/EXG Format
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
251
HD63B09, HD63C09
and B accumulator and places the unsigned result
into the I6-bit D accumulator. This unsigned mul·
tiply also allows multiple-precision multiplications.
Long And Short Relative Branches
The HD6309 has the capability of program
counter relative branching throughout the entire
memory map. In this mode, if the branch is to be
taken, the 8-or I6-bit signed offset is added to the
value of the program counter to be used as the
effective address. This allows the program to
branch anywhere in the 64k memory map. Position
independent code can be easily generated through
the use of relative branching. Both short (8-bit) and
long (I6-bit) branches are available.
SYNC
After encountering a sync instruction, the MPU
enters a sync state, stops processing instructions,
and waits for an interrupt. If the pending interrupt
last Cycle
Software Interrupt
A software interrupt instruction will cause an
interrupt, and its associated vector fetch. These
software interrupts are useful in operating system
calls, software debugging, trace operations, memory mapping, and software development systems.
Three levels of SWI are available on this HD6309,
and are prioritized in the following order: SWI,
SWI2, SWI3.
Sync
last Cycle
of PrevIous Opcode
Instruction Fetch Execute
I
is non-maskable ( NMI) or mask able (FIRQ, IRQ)
with its mask bit (F or 1) clear, the processor will
clear the sync state and perform the normal interrupt stacking and service routine. Since FIRQ and
IRQ are not edge-triggered, a low level with a
minimum duration of three bus cycles is required to
assure that the interrupt will be taken. If the pending interrupt is maskable (FIRQ, IRQ) with its mask
bit (F or I) set, the processor will clear the sync
state and continue processing by executing the next
inline instruction. Figure 18 depicts sync timing.
I
I
I
of Sync
Instruction
Sync Acknowledge (Sleep model
'If
I
I
Q
Address=:JC=X!E:J:B~}---------1,r----f--------~§:2X=='I:.=X=::
DamX=::)c::=)C=::x==>---------1,r----r---------~==)C=::)c::=x:::
. . . . . . .---~-----....r------•
\
Riw~---'-----BA
::::::::>.._ _ _ _ _-J!
BS::::::::>..~
______________________~. . ------~------__--------------------~
-If;I
IRQ ----------------...J\,r----..v~
NMI
IH
FiAQ
0.8 V
I Ipe.
r
Note 2
tpe•
Notes: 1 If the associated mask b,t IS set when the interrupt is requested, this cycle will be an instruction fetch from
address locatIon PC + 1. However if the interrupt is accepted (NMI or an unmasked FIRQ or IRQ) mterrupt
processing continues with this cycle as (m) on fIgures 6 and 7 (interrupt timing).
2 .If mask bits are clear, IRQ and FIRQ must be held low for three cycles to guarantee that interrupt will be
taken, although only one cycle is necessary to bring the processor out of SYNC.
Figure 18. Sync Timing
~HITACHI
252
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD63B09, HD63C09
16-Bit Operation
Example 1: LBSR (Branch Taken)
The HD6309 has the capability of processing 16bit data. These instructions include loads, stores,
compares, adds, subtracts, transfers, exchanges,
pushes and pulls.
Before Execution SP = FOOO
Cycle-by-Cycle Operation
$8000
The address bus cycle-by-cycle performance
chart illustrates the memory-access sequence corresponding to each possible instruction and address
ing mode in the HD6309. Each instruction begins
with an opcode fetch. While that opcode is being
internally decoded, the next program byte is always
fetched. (Most instructions will use the next byte, so
this technique considerably speeds throughput.)
Next, the operation of each opcode will follow the
flow chart.VMA is an indication of FFFF16 on the
address bus, R/W = high and BS = low. The
following examples illustrate the use of the chart :
see figure 19.
LBSR
CAT
CAT
$AOOO
Cycle-by-Cycle Flow
Cycle # Address Data R/W Description
1
2
3
4
5
6
7
8
8000
8001
8002
FFFF
FFFF
FFFF
FFFF
EFFF
17 1
IF 1
FD 1
1
1
1
1
03 0
9
EFFE
80
*
*
*
*
0
Opcode Fetch
Offset High Byte
Offset Low Byte
VMA Cycle
VMA Cycle
VMA Cycle
VMA Cycle
Stack Low Order
Byte of Return
Address
Stack High Order
Byte of Return
Address
Example 2: DEC (Extended)
$8000
$AOOO
$AOOO
$80
DEC
FCB
Cycle-by-Cycle Flow
Cycle # Address Data R/W Description
1
2
3
4
5
6
7
*
Opcode Fetch
Operand Address,
High Byte
Operand Address,
00 1
8002
Low Byte
VMA Cycle
FFFF
1
Read the Data
AOOO
80 1
VMA Cycle
FFFF
1
Store the Decremented
7F 0
AOOO
Data
The data bus has the data at that particular
address.
8000
8001
7A
AO
1
1
*
*
_HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
253
HD63B09, HD63C09
()PC'"
NNNN
~
V..
1001'11
I
No
LBCC. LSCS
LBEQ.L BGE
LBGT. LBHI
LBHS.LBLE
LBLO.LBLS
LBLT. L BMI
LBNE. LBPL
LBRA.LBRN
LBSR.L BVC
LBVS
Re.--~
2nd_
NNNN+I
D,....
Imrnedllte
E.tended
BCC.BCS
BED.BGE
BGT.BHI
BHS.BlE
BlO.BlS
IlT,lMI
BNE.BPl
BRA.BRN
BSR.Bve
BV!
E--, "NDeC
ORCC
CWAI
"NDeC
ORCC
,
_H
NNNN+1C21
_Low
,
NNNN+1(21
_Low
Don't Care
FFFF
NNNN+2(31
0II0et
CWA'l
---
CCM....
NNNN+l
NNNN+l
Don't Cere
NNHN+2
Don t Cono
I (WI
NNNN+2
511'"
,
Don't C.re
FFFF
FFFF
I
I
OfIMtLow
PC LowIWI
NNNN+2(3J
SlICk
I
I
PC HoohlWl
Don't Ca...
FFFF
4
e
,
U !.owl..1
v..
No
I
Don't C.re
U HoghIWl
FFFF
SlICk
~
UlSR
No
r
V LowIWI
-,
V..
1
,
Don't Cere
FFFF
Y HoghlWl
--r
"IWI
s_
I
CCIWI
1--
Don't care
FFFF
~
'?v':
-,
_Ii","
FFFX
VICtor Low
FFFX+l
I
I
X LowIWl
Don't ea,.
FFFF
Don'Ie..
FFFF
S_
I
PC LowIWI
SlICk
I
PC HoghlWl
Stick
X HoghlWl
L--
1
NotBS: 1.
OPIWI
I
Don'Ie-,.
NNNN+1
r--l
0011
I
0fIMt Hog.
NNNN+1I21
"
!
A. InltructJOnl
B
~~: : : Shi"!!JO""ffse~t-'H"""i""h'----'
Address Bus NNNN + 1 2
2. Address NNNN is location of opcocle.
3. If opcode is two byte opcode subsequent addresses are in parenthesis ( ) .
4. Two-byte opcodes are highlighted.
Figure 19. Cycle-by-Cycle Performance
•
254
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09, HD63C09
'mplood
A
Aax
RTS
Dan't C.".
NNNN+l
Don't CI..
NNNN+l
Don't Core
FFFF
PC Hlllh
StIcI<
I
,
PC~
Stack
l
Don't Co..
FFFF
1
ASlA/B
ASRAla
CLRAlB
COMA/B
MUL
A
=~~
RTI
SYNC
SW13
Don't Co..
NNNN+l
OM
DECAIB
INCAla
LSwa
LSRAtB
NEGAtB
NOP
RDWB
RORAtB
SEX
TSTAtB
Don't Care
NNNN+1121
,
Don't Co..
NNNN+l
Don'tCore
FFFF
CC
StICk
I
,
Don't Clre
FFFF
I
Don't Clre
FFFF
,
,
Don't C...
FFFf
I Don't Core
NNNN+l
Don't Core
FFFF
PCI.owIWI
Stack
1
"
,
PC Hlllh!W1
Steck
U~IWI
I
VII
A
Stock
StICk
fFFF
,
,
U Hoghlwl
StIcI<
,
,
DP
Stock
VI.owIWI
StIcI<
X H",h
Stock
Don'tCore
FFFF
I
t
~
'Yv:
Don't Co..
3-S_
,
I
I
X~
J
I
,
I
X I.owIWl
Stock
Y High
Stack
Don't Core
FFFF
t
Don't Core
3-S_
I
Y Hogh!W1
StIcI<
Don't Core
FfFf
J
I
I
L Don'tC...J
Don't Co..
FFFF
1
~
a
Stock
t
I Don't Core
NNNN+l
Stack
I
X HlllhlWl
StIcI<
,
Y~
DPIWI
Stock
U Hiah
Stock
~
,
,
B !WI
Stock
AIWI
Steck
CC !WI
Steck
I
Don't Core
FFFF
J
,
,
Stack
U~
Stock
J--
PC High
Stack
I
PC~
Steck
..l
Don't Co..
Stock
V_High
FFFX
,
,
V_~
FFFX+l
Don't Core
FFFF
•
B
-
.(i)
Figure 19. Cycle-by-Cycle Performance (Cont.)
•
HITACHI
Hitachi America, ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
255
HD63B09, HD63C09
RegtSter
A,)-----------------------------~----------------------------------------__lA
TFR
Don't Care
FFFF
on', Care
FFFF
Don't Care
FFFF
Don·IC....
FFFF
Don't Care
FFFF
Don't Care
FFFF
Sl8c:k
PC Low
SlAIck
Y Htghtw)
Stac:k
Don·le....
SlIck
B
B
Figure 19_ Cycle-by-Cycle Performance (Cont.)
_HITACHI
256
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
:z:
~
=-
l
»
I
P- IYIO J
NNNN+1C21
3
1
CD
:::!,
n
.!"
R+58ft
r-
R+A
R+8
R+18BIt
R+8Bft
et
•
:z:
~
=-0
~
Don't Cere
NNNN+2131
Don',Can
Don't Care
Don',Can
NNNN+2131
•
NNNN+2t3"
Offset ' -
•
NNNN+2131
LDon', 0 ... I
lOon"•c...J
NNNN+3141
FFFF
NNNN+3141
NNNN+2131
•
•
LDon', Can I l Don', Can I
FFFF
I
,
FFFF
,
'"•
§
~~
Don't Care
FFFF
Don't Care
FFFF
Don't ClInt
FFFF
~
;;l
-0 :I
_
Don't Care
NNNN+2131
,Cere I
LDon',
~
FFFF
Don't Ce...
Inc/OtM::
by2
Inc/Dec
by1
DIfoot Hogh
DIfoot
NNNN+2~3)
R+D
,
PC+8BIt
Oor'l"l Care
NNNN+2131
,
,
I Don', eo.. I
FFFF
FFFF
Don',Can
Don't Care
FFFF
FFFF
-'-
1
Don't Care
FFFF
~
co
c:r
'"'"
_CD
~
'R
<:>
IDffeet ' - I
,
NNNN+3141
Don',Can
FFFF
Ex...-
1-
_ _ H;gh
,
,
-'NNNN+2131
NNNN+3141
Don't Cere
FFFF
t
Don't Cere
,
,
FFFF
FFFF
Don',Can
FFFF
1
~Y"
>
Don'te...
FFFF
FFFF
<0
§J
NNNN+2131
FFFF
1_'-
~
,
NNNN+213N
LDon"CanJ
9l
<»
,
I Offset High
Don',Can
"J?(')
.;§ :I
:::!,
DIfoot
l
Don',Can
~~
en
pC+ 188d
eo..
FFFF
,........... by 2
~'by2
:Fl5RWiCounter ReIabw
l8-Bit 0ff8et
to
<0
0,
::r::
W
g
N
(J1
-.J
to
::r:
I\.l
01
tJ
w
CXl
en
t::C
::J:
o
~
CO
::t>
~
::l.
£
JMP
g
•
::J:
~.
~~~~L
~
~
l
•
§
w..:t
~-c _
!"'I
)i
~(')
:I
·-
Data
EA
I
J
[ReglStarfW)
EA
J
RegISter HoghlW~
EA
Data Hogh
EA
I
,
l Data Low
I
EA+l
,
I I
<0
•
1i
~
~
JSR
It~
I
I
Don·, Care
FFFF
FFFF
I
I I
,
DltalW)
EA
18-Brt~'
BReglStar~'
l!l!!m!.
I
I
l
,
Data HIgh
EA
,
I
I
,
I Don·' Car. I
I FFFF I
J
Relative
1
Don·, Ca..
POinter RegtSter·
POinter RegISter·
POinter ReglSter- 1
Pomter Reglstar- 2
Program Counter+Offset Byte
Poogram Coonter +~, High Byte Offset Low Byte
IndIrect High Byte Indirect low Byte
0,_ Pogo RegISter
~
Address Hogh Byte Add.... Low Byte
!m!!l!!!!!!!..
NNNN+1(2)
Add.... Low Byte
* Pomter RegtSter IS Incremented following the Indexed access
Co
8
Figure 19. Cycle-by-Cycle Performance (Cont.)
FFFF
,
Don·, care I
EA
•
,
Don·, Ca..
FFFF
I
J
PC HoghlW) I
Stack
,
LEAY
I
l
I I
I I
tJ
w
()
o
en
LEAS
LEAU
LEAX
PC LowIW)
Stack
~
I
I
POinter ReglSter+A RegISter
POinter ReglSter+ B RegtSter
POInter RegtSter + 0 RegISter
l1m1.
I I
J l
Data Low
EA + 1
POinter ReglSter+Post Byte
PoInter RegISter + Offset Byte
POinter ReglSter+Offset High Byte Offset Low Byte
AcclllDulltgr Offwt
A RegISter Offset
18-Brt Offset
,
Data
EA
POinter Regmer
5-Brt Offset
B-Brt Offset
:T8ff2tunter
I
EIf"""""~IEA)
£:~
Auto Increment/Decrement
Incremen' by 1
Incremen' by 2
Docremen' by 1
Decremen, by 2
~
c»
EA+l
I
Don·, Ca..
"
~
§;
.1
CMPX.
,
lReglSter LowlW)/
o RegISter Offset
CD
ADDD._
SUBD
Data
EA
,
j
en
CT
TST
RDR
SUBAIB
-c
CD
::l.
ASL.ASR
CLR.CDM
DEC.INC
~~:
SBCAlB
2:
':<
LDD
STD
. . . .
LOU
STU
EDRAIB
1!l
a
STAIB
C~~~:
;::;:
2.
ADCAIB
ADDAIB
ANDAIB
::r:
I
CO
r---'.L--,
I
Don'
care I
FFFF
HD63B09, HD63C09
Sleep Mode
HD6309 Instruction set Tables
During the interrupt wait period in the SYNC
instruction (the sync state) and in the CWAI
instruction (the wait state), MPU operation is halt·
ed and goes to the sleep mode. However, the state
of I/O pins is the same as that of the HD6809 in this
mode.
The instructions of the HD6309 have been broken
down into five different categories. They are as
follows:
· 8-Bit operation (table 6)
• 16-Bit operation (table 7)
• Index register/stack pointer instructions (table 8)
• Relative branches (long or short) (table 9)
• Miscellaneous instructions (table 10)
HD6309 instruction set tables and Hexadecimal
Values of instructions are shown in table 11 and
table 12.
Table 6. 8-Bit"Aeeumuiator and Memory Instructions
Mnemonlc(.)
AOCA.ADCB
ADDA.ADOB
ANDA.ANDB
ASL. ASLA. ASLB
ASR.ASRA. ASRB
BITA. BITB
CLR. CLRA. CLRB
CMPA. CMPB
COM. COMA. COMB
DAA
DEC. DECA. OECB
EORA. EORB
EXG R1. R2
INC. INCA. INCB
LOA. LOB
LSL. LSLA. LSLB
LSR. LSRA. LSRB
MUL
NEG. NEGA. NEGB
ORA. ORB
ROL. ROLA. ROLB
ROR. RORA. RORB
SBCA. SBCB
STA. STB
SUBA.SUBB
TST. TSTA. TSTB
TFR R1. R2
Operation
Add memory to accumulator with carry
Add memory to accumulator
AND memory with accumulator
Arithmetic shift of accumulator or memory left
Arithmetic shift of accumulator or memory right
Bit test memory with accumulator
Clear accumulator or memory location
Compare memory from accumulator
Complement accumulator or memory location
Decimal adjust A accumulator
Decrement accumulator or memory location
Exclusive OR memory with accumulator
Exchange R1 with R2 (R1. R2=A. B. CC. OP)
Increment accumulator or memory location
Load accumulator from memory
Logical shift left accumulator or memory location
Logical shift right accumulator or memory location
UnSigned multiply (A x B..... D)
Negate accumulator or memory
OR memory with accumulator
Rotate accumulator or memory left
Rotate accumulator or memory right
Subtract memory from accumulator with borrow
Store accumulator to memory
Subtract memory from accumulator
Test accumulator or memory location
Transfer R1 or R2 (R1. R2=A. B. CC. DP)
Note: A. B. CC or DP may be pushed to Ipulled froml either stack WIth PSHS. PSHU (PULS. PULU) instructions .
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
259
HD63B09, HD63C09
Table 7. I6-Bit Accumulator and Memory Instructions
Mnemonic(s)
Operation
ADOO
Add memory to 0 accumulator
Compare memory from 0 accumulator
CMPO
0, R
EXG
Exchange 0 with X, Y, S, U or PC
LOO
Load 0 accumulator from memory
SEX
Sign Extend B accumulator into A accumulator
STD
Store 0 accumulator to memory
SUBO
Subtract memory from 0 accumulator
TFR
0, R
Transfer 0 to X, Y, S, U or PC
TFR
R, 0
Transfer X, Y, S, U or PC to 0
Note: D may be pushed (pulled) to eIther stack wIth PSHS, PSHU IPULS, PULU) instructIOns.
Table 8. Index Register/Stack Pointer Instructions
Mnemonic(s)
Operation
CMPS, CMPU
Compare memory from stack pointer
CMPX, CMPY
Compare memory from index register
EXG
Exchange 0, X, Y, S, U or PC with 0, X, Y, S, U or PC
R1, R2
LEAS, LEAU
Load effective address into stack pointer
LEAX, LEAY
Load effective address into index register
LOS, LOU
Load stack pointer from memory
LOX, LOY
Load index register from memory
PSHS
Push A, B, CC, OP, 0, X, Y, U or PC onto hardware stack
._---
PSHU
Push A, B, CC, OP, 0, X, Y, S or PC onto user stack
--------------------------------Pull A, B, CC, OP, 0,
PULS
Pull A, B,
PULU
ce,
X, Y, U or PC from hardware stack
DP, D, X, Y, S or PC from user stack
STS, STU
Store stack pOinter to memory
STX, STY
Store Index register to memory
TFR
ABX
-----------
R1, R2
Transfer 0, X, Y, S, U or PC to 0, X, Y, S, U or PC
Add B accumulator to X (unsigned)
~HITACHI
260
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09, HD63C09
Table 9. Branch In8truction8
Mnemonic(a'
Operation
Simple Branchea
BEQ, LBEQ
Branch if equal
BNE, LBNE
Branch if not equal
BMI, LBMI
Branch if minus
BPL, LBPL
Branch if plus
BCS, LBCS
Branch if carry set
BCC, LBCC
Branch if carry clear
BVS, LBVS
Branch if overflow set
BVC, LBVC
Branch if overflow clear
Signed Branchea
BGT, LBGT
Branch if greater (signed)
BGE, LBGE
Branch if greater than or equal (signed)
BEQ, LBEQ
Branch if equal
BLE, LBLE
Branch if less than or equal (signed)
BLT, LBLT
Branch if less than (signed)
Unsigned Branc....
BHI, LBHI
Branch if higher (unsigned)
BHS, LBHS
Branch if higher or same (unsigned)
BEQ, LBEQ
Branch if equal
BLS, LBLS
Branch if lower or same (unsigned)
BLO, LBLO
Branch if lower (unsigned)
Other Branch..
BSR, LBSR
Branch to subroutine
BRA, LBRA
Branch always
BRN,LBRN
Branch never
Table 10. MiscellaneoU8 In8truction8
Mnemonlc(a'
Operation
ANDCC
AND condition code register
CNAI
AND condition code register, then wait for interrupt
NOP
No operation
ORCC
OR condition code register
JMP
Jump
JSR
Jump to subroutine
RTI
Return from interrupt
RTS
Return from subroutine
SWI, SWl2, SWl3
Software interrupt (absolute indirect)
SYNC
Synchronize with interrupt line
_HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
261
HD63B09, HD63C09
Table 11. HD63091nstruction Set Table
IMP
INSTRUCTIONS!
FORMS
ABX
OP -
,
3A 3
1
ACCMREG
,
DIRECT
OP -
,
EXTND
OP -
,
IMMED
OP -
INDEXQ)
OP -
RELATIVE
I OP
B+X~X
(UnsIgned)
ADC
ADD
AND
ASL
ASR
BCC
ADCA
ADCB
ADDA
ADDB
ADDD
ANDA
ANDB
ANDCC
99
09
9B
DB
03
94
04
ASLA
ASLB
ASL
4B 2
58 2
ASRA
ASRB
ASR
47 2
57 2
4
4
4
4
6
4
4
2
2
2
2
2
2
2
B9
F9
BB
FB
F3
B4
F4
5
5
5
5
7
5
5
3
3
3
3
3
3
3
89
C9
8B
CB
C3
B4
C4
lC
2
2
2
2
4
2
2
3
2
2
2
2
3
2
2
2
A9 4+
E94+
AB 4+
EB 4+
E36+
A4 4+
E44+
A+M+C-~A
2+
2+
2+
2+
2+
2+
2+
08 6
2 78 7
3
A+M~A
B+M~B
D+M
07 6
2777
3
BI\M~B
CCI\IMM~CC
68 6+ 2+
~}
[}{]]]ll]}-- 0
67 6+ 2+
~}
r:miiITIHl
BCC
LBCC
24 3
2
10~(6) 4
24
BCS
8EQ
BGE
BGT
BCS
LBCS
25 3
25
27 3
27
2C 3
BHS
2
10~(6) 4
2C
2E 3
BGT
LBGT
BHS
2
10~(6) 4
BGE
LBGE
BHI
LBHI
2
2
10~(6) 4
2
10~(6) 4
22
24 3 2
BLE
BLO
BLO
LBLO
BLS
BLS
95 4
05 4
2 B6 6
2 F5 5
3 B5 2
3 C6 2
BLT
LBLT
BMI
BMI
18MI
2 A54+ 2+
2 E54+ 2+
2F 3
10~(6)
2F
25 3
10~(6)
25
23 3
LBLS
BLT
bOC
Branch C=O
Long Branch
C=O
Branch C=1
C=1
Branch Z=1
long Branch
Z=1
Branch NEllY = 0
long Branch
NE&V=O
Branch ZV(NE&V) =0
Long Branch
(NEllY) =0
Branch CVZ = 0
long Branch
CVZ=O
Branch C=O
10~(6) 4 long Branch
24
BITA
BITB
BLE
LBLE
b7
bO
zv
2E
22 3
LBHS
BIT
C b7
10~(6) 4 long Branch
BEQ
18EQ
BHI
.M+l~D
AI\M~A
1
1
10
23
20
10
20
2B
10
2B
2
4
2
4
2
C=O
BII Taol A (MI\A)
Bn Tesl B (MI\B)
Branch ZV (NE&V) = 1
Long Branch
ZV(NEllY) =1
Branch C=1
Long Branch
C=1
Branch CVZ= 1
(6) 4
Long Branch
3
Branch NE&V= 1
Long Branch
NEllV=1
Branch N=1
Long Branch
N=1
CVZ=1
2
(6) 4
3
2
(6) 4
6
5
4
3
2
1
0
F
H
I
N
Z
V
C
••••••••
•• •• ••
•• •• ••
•• •• •• ••
••
•0-• • •
•• •• ••
•• •
•• •• •• ••
•• • •
•• •• •• •• •• •• •• ••
I
I
I
I
B+M+C~B
1
1
7
E
DESCRIPTION
-15 I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
R
R
'-- f 7=1 FF-A
B<1)I:'·> f 7=0 O·~A
•• •• •• ••
••••
••••
•• •• •• ••
(r- I-
I
I
I
J
J
I
I
I
J
J
J
I
I
I
I
I
J
I
••
•
J
J
J
(]J
)
••••••••
•• •• ••
•••• ••
@
J
@
I
I
J
J
J
J
J
I
I
(Continued)
~HITACHI
264
Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09, HD63C09
INSTRUCTIONSI
FORMS
ST
IMP
ACCMREG
OP -
, -, -,
STA
STB
STO
STS
STU
STX
STY
SUBA
SUB
DIRECT
OP
97 4
07 4
DO 5
10 6
2 B7 5
2 F7 5
2 FO 6
3 10 7
OF
OF 5
9F 5
10 6
9F
FF
90 4
DO 4
SUBB
SUBO
93 6
SWI@
3F 19 1
SWl2@ 1020 2
3F
SWl3@ 11 20 2
SWI
EXTND
OP
2
2
3
FF 6
BF 6
10 7
,
IMMED
OP -
A7 4+
E74+
ED 5+
106+
EF
3
3
3
4
3
,
3 80 2
3 CO 2
3 83 4
i-@
DESCRIPTION
2+
A~M
2+
2+
3+
B~M
2 AO 4+ 2+
2 EO 4+ 2+
3 A36+ 2+
O~M
S~M
U~M
M+l
M+l
X~M
M+l
M+l
Y~M
M+l
TSTA
TSTB
IF 6
40 2
2
I
60 2
I
TST
3
606+ 2+
4
3
2
1
0
H
I
N
Z
V
C
I
I
I
I
I
I
I
I
R
R
I
I
I
I
I
I
R
R
I
I
I
I
I
I
I
t
I
I
t
I
I
I
t
R
R
•• •• •• ••
•• •• •• ••
•• •• •• ••
••••
S
M+l~O
RI~R2<2>
2 70 7
5
F
Software Interrupt 2
O-M
Synchronize to
00 6
6
Software Interrupt 1
B-M~B
Interrupt
RI,R2
TFR
TST
7
E
•• • ••
• •• •
A-M~A
Software Interrupt 3
3F
13 ;04 1
SYNC
,
RELATIVE
OP
EF 5+ 2+
AF 5+ 2+
106+ 3+
AF
3
4
BF
2 BO 5
2 FO 5
2 B3 7
INDEX
____ Vcc=4.5V
0.8 ----------------
8,
~
.~
z
0.5
0~--------------~5~0------------L-160·~(p~F~)-----
Address Bus load Capacitance Cd
Figure 23. Dependency of the Noise Voltage on the Load Capacitance of the Address Bus
•
270
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09, HD63C09
Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply Voltage
,
Vee
-0.3 to +7.0
V
Input Voltage
Von'
-0.3 to +7.0
V
Maximum Output Current
11012
5
mA
Maximum Total Output Current
1~lo 13
100
mA
Operating Temperature
Topr
-20to +75
·c
Storage Temperature
Tstg
-55 to + 150
·c
Notes
1 • With respect to Vss (system GNOI
2
Maximum output current
3
(Ao -A, 5'
DO -0 7 • BA. BS. Q. EI
Maximum total output current IS the total sum of output currents which can flow out simultaneously from output termmals and
4
I/O common terminals (AO -A'5'
DO -0 7 , BA. BS. Q. EI
Permanent LSI damage may occur If maximum ratings are exceeded
IS
the maximum currents which can flow out from one output terminal and I/O common terminal
RNV.
RNV.
Normal operation should be under recommended
operating conditions If these conditions are exceeded, It could affect reliability of LSI
Recommended Operating Conditions
Symbol
Item
Supply Voltage
Input Voltage
Min
Typ
Max
Unit
4.5
5.0
5.5
V
EXTAL
-0.3
0.6
V
Other Inputs
-0.3
0.8
V
Vee
V
Vee
V
Vee
V
75
·c
EXTAL
Other Inputs
Operating Temperature
Note' 1
2.0
-20
25
With respect to Vss (system GNO)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
271
HD63B09, HD63C09
Electrical Characteristics
DC Characteristics (Vcc=S.O V ± 10%, Vss=O V, Ta= -20 to +7S'C, unless otherwise noted.)
HD63C09
HD63B09
Symbol Min
Item
Input High Voltage
RES
V 1H
Typ Max Min
Typ Max Unit Teet Condition
V
Vee- 0 .5
Vee
Vee- 0 .5
Vee
EXTAL
Vee xO . 7
Vee
Vee xO . 7
Vee
Other Inputs
2.0
Vee
2.0
Vee
-0.3
0.6
-0.3
0.6
-0.3
0.8
-0.3
0.8
~n
-2.5
2.5
-2.5
2.5
pA
Vin =0 to Vee,
IrSI
-10
10
-10
10
pA
Vm=O.4 to Vee,
-10
10
-10
10
VOH
4.1
4.1
Vee- 0 .1
Vee- 0.1
~oAD:ii-10pA
4.1
4.1
~OAD=
-4001'A
Q, E
Vee- 0 .1
Vee- 0. 1
~OAD:>
-1 OpA
BA, BS
4.1
4.1
~OAD=
-400pA
Vee- 0 .1
Vee- 0 .1
ILOAD:> -1 OpA
-~--~~
Input Low Voltage
EXTAL
V 1L
Other Inputs
Input Leakage Current Except EXTAL,
V
XTAL
Vee=max
Three State (Off State) Do -D7
Input Current
Ao-A,s, R/W
Output High Voltage Do-D7
l
Ao-A,s, R/W,
~OAD= -4001'A
VOL
0.5
0.5
V
~OAD=2mA
G.n
15
15
pF
Vm=OV,
Except Do -D7
10
10
Ao -A,s, R/W, Cout
BA, BS
12
12
pF
24
36
mA
15
18
Output Low Voltage
Input Capacitance
Vee=max
V
Do-D7
T. =25'C,
Output Capacitance
Current Dissipation
lee
f=lMHz
Operating
Sleeping
.HITACHI
272
Hitachi Am~riGa, Ltd.
@
Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09, HD63C09
AC Characteristics (Vcc=5.0 V
±
10%, Vss=O V, Ta= -20 to +75°C, unless otherwise noted.)
Clock Timing
HD63B09
HD63C09
Item
Symbol
Min Typ Max Min
Frequency of Operation
(Crystal External Input)
fXTAL
2
8
Cycle Time
t"YC
500
2000333
Total Up Time
tuT
480
310
ns
Processor Clock High
fpwEH
220
5000 140
5000 ns
Processor Clock Low
fpwEL
210
1000 140
1000 ns
E Rise and Fall Time
te" tel
20
20
ns
100
ns
Etow to ~,gh Time
Q Clock High
2
12
MHz Figs. 25. 26
2000 ns
~vs
140
1000 140
5000 140
5000 ns
20
20
fpwOH
Q Clock Low
fpwOL
220
Q Rise and Fall Time
to,. tol
toE
70
Max Unit Test Condition
100
220
Otow to ELow Time
Typ
100
70
HD63B09
HD63C09
1000 ns
ns
ns
Bus Timing
Item
Symbol
Address Delay
tAD
Peripheral Read
Access Time
(tuT-~D-toSR = ~ccl
Data Set
(Read)
Up Time
Input Data Hold Time
Address Hold Time
Ta=O to +75°C
Time
Output Hold Time
110
~cc
330
toSR
40
40
ns
Ta=O to +75°C
ns
toHR
10
10
ns
~H
20
20
ns
10
toHW
Figs. 25. 26
10
110
toDW
Ta= -20 to O°C
110 ns
160
Ta= -20 to O°C
Data Delay
(Write)
Min Typ Max Min Typ Max Unit Test Condition
70
30
30
20
20
ns
ns
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
273
HD63B09, HD63C09
Processor Control Timing
HD63C09
HD63B09
Min Typ Max Min Typ Max Unit Test Condition
Item
Symbol
MROY Set Up Time
tpesM
110
70
ns
Figs. 3 - 7
MROY Set Up Time 2
tpesM2
240
160
ns
Figs. 11, 12
Interrupts Set Up Time
tpes
110
70
ns
HALT Set Up Time
tpesH
110
70
ns
RES Set Up Time
tpesR
110
110
ns
OMA/BREQ Set Up Time
tpeso
110
70
100
Processor Control Rise and Fall Timetper,
ns
100 ns
tpet
Crystal Oscillator Start Time
20
~e
20
ms
5.0V
Test Point
• C= 30pF (BA, BS)
130pF (0 0 -0 7 , E, Q)
90 pF (Ao -A,5, R/W)
• R= 10kO (D o -0 7 )
10kO (Ao -A'5' E, Q, R/W)
10kO (BA, BS)
0---.--.--....- 4
R
All diodes are lS2074.£) or equivalent.
C includes stray capacitance.
Figure 24. Bus Timing Test Load
$
274
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09, HD63C09
~------------------t~--------------------~
E Vee - 2.0V
Vee - 2.0V
O.BV
Vee - 2.0V
~-----tPWEH -.----~
O.BV
Vee - 2.0V
Q
ADDR Vee - 2.0V
BA. BS
O.BV
Data------------------------------------~~
~
NotValid
Figure 25.
Read Data from Memory or Peripherals
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
275
HD63B09, HD63C09
E
---i~It----tpwaH----..I
Q------~----~~
RIW
ADDR Vee - 2.0V
BA,BS
~O~.8~V~~~--~1-~+-
__________~______________;=~~
Data
Data Valid
~
Not Valid
Figure 26. Write Data to Memory or Peripherals
~HITACH.
276
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 .. (415) 589-8300
HD63B09E,HD63C09E--CMOS MPU (Micro Processing Unit)
The HD6309E is the highest 8-blt microprocessor of
HMCS6800 family, which is just compatible with the conventional HD6809E.
The HD6309E has hardware and software features which
make it an ideal processor for higher level language execution or
standard controller applications. External clock inputs are
provided to allow synchronization with peripherals, systems or
other MPUs.
The HD6309E is complete CMOS device and the power
diSSipation is extremely low. Moreover, the SYNC and CWAI
instruction makes low power application possible.
•
•
•
•
•
•
FEATURES
Hardware - Interface with All HMCS6800 Peripherals
Software - Object Code Compatible with the HD6809E
Low Power Consumption Mode (Sleep mode)
SYNC state of SYNC Instruction
WAIT state of CWAI Instruction
External Clock Inputs, E and 0, Allow Synchronization
Wide Operation Range
f = 0.5 to 3MHz (Vcc=5V±10%)
Type No.
HD63B09EP, HD63C09EP
(DP·40)
• PIN ARRANGEMENT
2.0MHz
HD63C09E
3.0MHz
TSC
LIC
RES
BS
Bus Timing
HD63B09E
HALT
AVMA
SA
Vce
a
E
A.
A,
BUSY
R/W
A,
A,
A.
,
HD6309E
A,
A.
D.
0,
0,
0,
D.
Os
D.
A,
0,
A"
A"
A I.
Au
(Top View)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
277
HD63B09E, HD63C09E
•
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply Voltage
Vcc*
-0.3-+7.0
V
Input Voltage
Yin *
-0.3-+7.0
V
110'**
5
mA
mA
Maximum Output Current
Maximum Total Output Current
':E10'***
100
Operating Temperature
Topr
-20-+75
°c
Storage Temperature
Tstg
-55 - +150
°c
* With respect to VSS (SYSTEM GND)
•• Maximum output current is the maximum currents which can flow out from one output terminal and 1/0 common terminal.
(A. - Au, AIW. D. - 0,. BA. BS. lIC. AVMA, BUSY)
••• Maximum tot81 output current is the total sum of output currents which can flow out simultaneously from output terminals and I/O common
terminal •. (A. - Au. AIW. Do - 0,. BA. BS. LIC. AVMA. BUSY)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions.
If these conditions are exceeded, it could affect reliability of LSI.
•
RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage
Logic, RES
Input Voltage
E,Q
Symbol
VCC *
min
typ
max
Unit
4.5
5.0
5.5
V
VIL
-0.3
0.8
V
..
.
VILC
Logic
E.Q
VIH
RES
Operating Temperature
Topr
-0.3
-
0.4
V
2.0
-
VCC
V
3.0
-
VCC
V
Vcc-0.5
-
Vee
V
-20
25
75
°c
* W'th respect to VSS (SYSTEM GNO)
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee=5.0V±IO%, Vss=OV, Ta=- 20 - +75°C, unless otherwise noted. I
Symbol
Item
Logic
Input "High" Voltage
E,a
J!f3'
Input "Low" Voltage
Input leakage Current
Logic, J!f3'
E,a
Logic. J!f3'
E
a.
VIH
VII·
VIHA
VIL
VILC
I,n
A. - Au. Am
VOH
VOL
Do - 0, , Logic
Frequencv of Operation
Input a, RES
E
AIW.
BA, BS, Lie,
AVMA,BUSY
E,a
Three-Stata (Off Stata)
Do"'" 0.,
Input Current
A.-A".A/W
Input Capacitance
A,,-,.. •.
Output Capacitance
Current Dissipation
Vee-rna.
ILOAO~-10,.A
BA, BS. LlC,
AVMA.BUSY
Output "Low" Voltage
Vin""O -.. VCC ....
ILOAO--400,.A
Do ...... 0,
Output "High" Voltage
Test Condition
I LOAO--400,.A
I LOAO:l:-tO,.A
I LOAO--400,.A
I LOAO:l:-l0,.A
I LOAO=2mA
Vm-OV,
Cin
Ta-25'C.
f-1MHz
V,n-OV.
Cout Ta-25'C.
f-1MHz
f
ITSI
ICC
Von-0.4- Vec.
Vcc-ma.
Operatmg
Sleeping
min
HD63B09E
typo
2.0
3.0
Vec-0.5
-0.3
-1>.3
-2.5
-10
4.1
Vce-0.1
4.1
Vee-0.1
4.1
Vec-O.1
-
-
-
-
max
Vee
Vee
Vee
0.8
0.4
2.5
10
-
min
H063C09E
typo
2.0
3.0
Vce-0.5
-0.3
-0.3
-2.5
-10
4.1
Vec-O.l
4.1
Vee-O· 1
4.1
-
-
-
mil)(
Unit
Vec
Vee
Vee
0.8
0.4
2.5
V
V
V
V
V
,.A
10
,.A
-
V
-
V
-
-
0.5
-
-
10
15
-
30
50
-
10
15
pF
-
3.0
10
10
30
MHz
,.A
,.A
-
Vec-O·l
-
10
15
-
0.5
-10
-10
-
2.0
10
10
20
0.5
-10
-10
-
-
10
-
-
-
-
0.5
V
10
15
pF
30
50
pF
V
mA
15
*T.-25'C. Vce-5V
.HITACHI
278
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
HD63B09E, HD63C09E
• AC CHARACTERISTICS (VCC"5.0V±10%. Vss=O. Ta=-20 - +75°C. unless otherwise noted.)
1. CLOCK TIMING
Symbol
Item
Test Condition
HD63C09E
min
HD63B09E
typ
max
min
typ
max
2000
ns
1000
ns
1000
ns
-
-
15
ns
140
-
1000
ns
-
-
15
ns
Cycle Time
teye
500
-
2000
333
E Clock "Low"
tpWEL
210
-
1000
140
E Clock "High" IMeasured at VIHI
tpWEH
220
-
1000
140
E Rise and Fan Time
tEr. tEl
-
-
20
a Clock "High"
tPWOH
220
1000
a Rile and Fan Time
tar, tal
-
Fig. 1.2
-
20
Unit
E "Low" to a Rising E "Lqw" -+Q"High"
tEal
100
-
-
a "High" to E Rising a "High"-+E "High"
tE02
100
tEQ3
100
a "Low" to E Falling a "Low"-+E "Low"
tEQ4
100
-
85
E "High" to a Falling E "High"-+Q"Low"
-
min
HD63B09E
typ
max
min
typ
max
110
ns
-
ns
85
85
85
-
-
ns
ns
ns
n.
2. BUS TIMING
Symbol
Item
Addrass Delay
Address Hold Time
IAddress, RIW, BA, BSI
I Ta- 0 -
Test Condition
-
tAD
75'C
I Ta - -20-0' C
Peripheral Read Accass Times
_1~j:-tEI-tAD-tDSR·tAccl
20
tAH
10
tACC
Fig. 1, 2
330
110
-
-
20
-
10
-
-
-
185
-
-
20
-
-
n.
20
-
-
n.
110
-
-
70
ns
-
-
ns
tDSR
40
Input Data Hold Time
tDHR
20
tDDW
-
-
30
-
Output Data Hold Time
l
Ta·0-75'C
tDHW
20
Ta- -20-0'C
Unit
-
Data Satup Time IReadl
Data Delay Time IWritel
HD63C09E
-
-
30
20
-
n.
3. PROCESSOR CONTROL TIMING
Item
Symbol
HD63C09E
HD83B09E
TlSt Condition
min
typ
max
min
typ
max
Unit
Control Delay IBUSY, LIC, AVMAI
tCD
-
-
200
-
-
130
ns
Intarrupts Set Up Time
tpcs
110
-
-
70
-
-
ns
70
-
-
ns
70
-
n.
120
ns
110
ns
80
n.
'RACT'Sat Up Time
tpcs
110
-
'A"Ef Sat Up Tim.
tpcs
110
-
TSC Satup. Time
tpcs
110
-
-
TSC Drive to Valid Logic Levels
tTSA
-
-
120
-
TSC Release MOS Buffers to High Impedance
tTSR
-
tTSD
-
110
TSC Th ree-5tata Delay
80
tpc~
100
-
TSC Input Delay
tPCT
-
-
Processor Control Rise/FaU
-
-
30
Fig. 1, 2,
7 - 10,
14 and 17
tPCI
30
70
ns
100
ns
-
ns
_HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
279
HD63B09E,HD63C09E
teye
-----------1
E
VILe
tE04
O--------r-----~~
RiW
-~:-;;~,.k,..__:::::J_-_+------------------_t+__lk
Addr.
BA,BS____~~~~~4-
__-+-__-----------------_+~~
O.ta-----------+---------~~
BUSY,
LlC, ______________
AVMA
VCC-2.0V
O.BV
~~~~
~NotValld
(NOTE)
Waveform measurements for all Inputs and outputs are specified at logiC "Hlgh":::: V IHmin and logiC "Low" ::: V ILmax unless otherwise specified
Figure 1 Read Data from Memory or Peripherals
E
VILC
O-------+------~~
RiW
Addr .• VCC-2.0V
O.8V
BA, BS
Data
Data Valid
BUSY,
LIC,
AVMA _ _ _ _ _ _ _ _ _ _ _
~~~~~
VCC·2.0V
O.BV
~NotValld
(NOTE)
Waveform measurements for all Inputs and outputs are specified at logIC "Hlgh"
= V IHmin and logic "Low" = V ILmax unless otherwise specified.
Figure 2 Write Data to Memory or Peripherals
~HITACHI
280
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300
HD63B09E, HD63C09E
+--Vcc
+--Vss
FiRQ
imi
l..-•
.,:::=-.:....-.. LlC
....---.AVMA
RiW
TSC
HALT
BA
BS
'----+BUSY
L..._ _ E
'-----0
Figure 3 HD6309E Expanded Block Diagram
5.0 V
• PROGRAMMING MODEL
As shown in Figure 5, the HD6309E adds three registers to
the set available in the HD6800. The added registers include a
Direct Page Register, the User Stack pointer and a second
Index Register.
RL = 1.8 k!1
Test Point 0-.-.......--l0iii1--1
• Accumulators IA. B. D)
The A and B registers are general purpose accumulators
which are used for arithmetic calculations and manipulation
of data.
Certain instructions concatenate the A and B registers to
form a single l6·bit accumulator. This is referred to as the D
Register, and is formed with the A Register as the most
significant byte.
C
C = 30 pF for BA. BS. LlC. AVMA. BUSY
130pF for O. -0,
90pF for A. -A IS • RiW
• Direct Page Register lOP)
R = 10 kOfor O. -0,
10 kOfor Au -A IS • RiW
10 kOfor BA. BS. LIC. AVMA. BUSY
The Direct Page Register of the HD6309E serves to enhance
the Direct Addressing Mode. The content of this register
appears at the higher address outputs (As - Au) during d~ct
addressing instruction execution. This anows the direct mode
to be used at any place in memory, under program control.
To ensure HD6800 compatibility, al1 bits of this register are
cleared during Processor Reset.
All diodes are 1S2074@ or equivalent.
C Includes stray capacitance.
Figure 4 Bus Timing Test Load
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
281
HD63B09E, HD63C09E
o
16
x-
Index RegIster
Y - Index RegISter
POinter Registers
U - User Stack POInter
S - Hardware Stack POinter
PC
A
\.
Program Counter
I
•D
B
Accumulators
I
o
' -_ _ _ _D_p_ _ _ _.jl
7
D"ect Page RegISter
0
IElF I H II I N I z I V I c I
cc -
ConditIon Code RaglSter
Figure 5 Programming Model of The MIcroprocessing Unit
• Index Registen IX, VI
The Index Registers are used in indexed mode of addressing.
The 16-bit address in this regisler takes part in the calculation
of effective addresses. This address may be used to point to
data directly or may be modified by an optional constant or
register offset. During some indexed modes, the contents of
the index register are incremented or decremented to point to
the next item of tabular type data. All four pointer registers
(X, Y, U, S) may be used as mdex registers.
• Stack Pointer IU, SI
The Hardware Stack Pointer (S) is used automalIcally by
the processor during subroutine calls and interrupts. The Vser
Stack Pointer (V) is con trolled exclusively by the programmer
thus allowing arguments to be passed to and from subroutines
with ease. The V-register is frequently used as a stack marker.
Both Stack Pointers have the same indexed mode addressing
capabilities as the X and Y registers, but also support Push and
Pun instructions. This allows the HD6309E to be used efficiently as a . stack processor, greatly enhancing its ability to
support higher level languages and modular programmmg.
(NOTE) The stack pointers of the HD6309E point to the top
of the stack, in contrast to the HD6800 stack pointer,
which pOinted to the next free location on stack.
• Program Counter IPCI
The Program Counter is used by the processor to point to
the address of the next instruction to be executed by the
processor. Relative Addressing is provided allowing the Program
Counter to be used like an index register in some situations.
• Condition Code Register ICCI
The Condition Code Register defines the state of the
processor at any given time. See Figure 6_
$
282
Carry
Overflow
L...---Zero
L -_ _ _ _ NegatIve
L..._ _ _ _ _ IRQ Mask
L..._ _ _ _ _ _ Half Carry
L . . . - - - - - - - - F I R Q Mask
' - - - - - - - - - - - Ent"e Flag
Figure 6 Condition Code Register Format
• CONDITION CODE REGISTER DESCRIPTION
• Bit 0 ICI
Bit 0 is the carry flag, and IS usually the carry from the
binary ALV. C is also used to represent a 'borrow' from
subtract like instructions (CMP, NEG, SVB, SBC) and IS the
complement of the carry from the binary ALV.
• Bit 1 IVI
Bit I is the overflow flag, and is set to a one by an operation
which causes a signed two's complement arithmetic overflow.
This overflow is detected in an operation in which the carry
from the MSB in the ALV does not match the carry from the
MSB-l.
• Bit 2 IZI
Bit 2 is the zero flag, and is set to a one if the result of the
previous operation was identically zero.
• Bit31NI
Bit 3 is the negative flag, which contains exactly the value
of the MSB of the result of the preceding operation. Thus, a
negative two's-complement result wi11leave N set to a one.
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09E, HD63C09E
• Bit4(J}
Bit 4 is the 'IRQ mask bit. The processor will not recognize
interrupts from the lruY line if this bit is set to a one. NMI,
FIRQ, IRQ, RES and SWI all set I to a one; SWI2 and SWI3
do not affect I.
This higher threshold voltage ensures that all peripherals are
out of the reset state before the Processor.
Table 1 Memory Map for Interrupt Vectors
Memory Map for Vector
Locations
• BitS (H)
Bit 5 is the half-carry bit, and is used to indicate a carry
from bit 3 in the ALU as a result of an S-bit addition only
(ADC or ADD). This bit is used by the DAA instruction to
perform a BCD decimal add adjust operation. The state of this
flag is undefined in all subtract-like instructions.
• Bit6(F)
Bit 6 is the FIRQ mask bit. The processor will not recognize
interrupts from the FIRQ line if this bit is a one. NMI, FIRQ,
SWI, and RES all set F to a one. iRQ, SWI2 and SWI3 do not
affect F.
• Bit 7 (E)
Bit 7 is the entire flag, and when set to a one indicates that
the complete machine state (all the registers) was stacked, as
opposed to the subset state (PC and CC). The E bit of the
stacked CC is used on a return from interrupt (RTI) to determine the extent of the unstacking. Therefore, the current E
left in the Condition Code Register represents past action.
• HD6309E MPU SIGNAL DESCRIPTION
• Power (Vss, Vee)
Two pins are used to supply powel to the part: Vss is
ground or 0 volts, while Vee is +5.0 V ±10%.
• Address Bus (Ao - A 1S )
Sixteen pins are used to output address information from
the MPU onto the Address Bus_ When the processor does not
require the bus for a data transfer, it will output address
FFFF I6 , R/W = "High", and BS = "Low"; this is a "dummy
access" or VMA cycle. All address bus drivers are made highimpedance when output Bus Available (BA) is "High" or when
TSC is asserted. Each pin will drive one Schottky TTL load or
four LS TTL loads, and 90 pF. Refer to Figures 1 and 2.
FFFE
FHC
FFFA
FFFB
FFF6
FFF4
FFF2
FFFO
FFFF
FFFD
FFFB
FFF9
FFF7
FFFS
FFF3
FFFl
Interrupt Vector
Description
RES
NMI
SWI
rna
FIRQ
SWI2
SWI3
Reserved
• Bu. Available, Bus Status (BA, BSI
The Bus Available output is an indication of an internal
control signal which makes the MOS buses of the MPU high
impedance. When BA goes "Low", a dead cycle will elapse before
the MPU acquires the bus. BA will not be asserted when TSC
is active, thus allowing dead cycle consistency.
The Bus Status output signal, when decoded with BA,
represents the MPU state (valid with leading edge of Q).
MPU State
• ReadlWrita (R/WI
This signal indicates the direction of data transfer on the
data bus_ A "Low" indicates that the MPU is writing data-Onto
the data bus. RlW is made high impedance when BA is "High"
or when TSC is asserted. Refer to Figures 1 and 2.
$
LS
• HALT
A "Low" level on this input pin will cause the MPU to stop
running at the end of the present instruction and remain halted
indefmitely without loss of data. When halted, the BA output
is driven "High" indicating the buses are high impedance. BS
is also "High" which indicates the processor is in the Halt state.
While halted, the MPU will not ~nd to external real-time
requests (FIRQ, IRQ) although NMI or RES will be latched
for later response. During the Halt state Q and E should
continue to run normally. A halted state (BA • BS = I) can be
achieved by pulling HALT "Low" while RES is still "Low". See
Figure S.
• Data Bus (Do - 0 7 )
These eight pins provide communication with the system
bi-directional data bus. Each pin will drive one Schottky TTL
load or four LS TTL loads, and 130 pF.
• RES
A "Low" level on this Schmitt-trigger input for greater tl;1an
one bus cycle will reset the MPU, as shown in Figure 7. The
Reset vectors are fetched from locations FFFEI6 and FFFFI6
(Table 1) when Interrupt Acknowledge is true, (BA • BS = I).
During initial power-on, the Reset line should be held "Low"
until the clock input signals are fully operational.
Because the HD6309E Reset pin has a Schmitt-trigger input
with a threshold voltage higher than that of standard peripherals,
a simple RIC network may be used to reset the entire system.
MS
MPU State Definition
BA
BS
o
o
0
Normal (Running)
1
Interrupt or RESET Acknowledge
o
SYNC Acknowledge
HALT Acknowledge
Interrupt Acknowled~ indicated durinAJl~th cycles of a
hardware-vector-fetch (RES, NMI, PTRQ, IRQ, SWI, SWI2,
SWI3). This signal, plus decoding of the lower four address
lines, can provide the user with an indication of which interrupt
level is being serviced and allow vectoring by device. See Table
1.
Sync Acknowledge is indicated while the MPU is waiting
for external synchronization on an interrupt line.
Halt Acknowledge is indicated when the HD6309E is in a
Halt condition.
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
283
6
I\.J
(Xl
"""
(j)
w
ttl
o
to
:::c
s:
n
tt:I
='»
3
6
ct)
:::0.
n
(j)
"'etr-"
E
w
o
o
'"
Q
tt:I
J;!
R3
•
~
n
to
='-
'"
'"•
N
1f.
""
0
0
0
-0
OJ
1:
_
!:!. :-I
;:?»
~O
~ 1:
Address
Data
AtW
~
BA
~
•
AVMA
BUSY
C"
New PCH New PCL
~
...
BS
en
0:>
:::0.
New PCH New PCL VMA 1st Opcode
",
:::I
_CD
L1C
C")
»
to
.j>.
0
0
'f'
c»
cD
•
-:;;;:
§J
01
00
~
(.oJ
0
0
(NOTE)
Waveform measurements for allmputs and outputs are specified at logic "High" = V 1Hmin afld logic "Low"
Figure 7
RES" Timi!lg
=
VILmax unless otherwise specified.
I7MA
~
>
3
C1>
Halted
Halted
:::>.
n
~
!i
•
Q
~
=.
"C
~
E
§
JOO:T
•
~.
~
_.
:t
~
a)i
"CO
Address
Bus
,i
·-
R/W
BS
I
Data
§;
Bus
Fetch
\
__________---',
\
\
"E
Instruction
Opcode
~
AVMA
\
/
LIe
/
\
.!:!!
i
I\.)
00
U1
,
jr-----
co
•
Execute
----~,r-----------~
~
~
~~
III
~
.fJ:
Di"
..
, ' -_ __
'---1
8
0')
Co)
t::Jj
o
<0
~
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High"" V1Hmin and logiC "Low..... VILma. unless otherwise specified.
Figure 8 HALT and Single Instruction Execution for System Debug
8
0')
Co)
(')
o
<0
tz:I
HD63B09E, HD63C09E
• Non Maskable Interrupt (NMU*
A negative transition on this input requests that a nonmaskable interrupt sequence be generated. A non-maskable
interrupt cannot be inhibited by the program, and also has a
higher priority than FIRQ, IRQ or software interrupts. During
recognition of an NMI, the entire machine state is saved on
the hardware stack. After reset, an lilMI will not be recognized
until the first program load of the Hardware Stack Pointer (S).
The pulse width of NMI low must be at least one E cycle. If
the NMI input does not meet the minimum set up with respect
to Q, the interrupt will not be recognized until the next cycle.
See Figure 9.
of a double-byte operation (e.g., LDX, STD, ADDD). Busy is
also "High" during the first byte of any indirect or other vector
fetch (e.g., jump extended, SWI indirect etc.).
In a multi-processor system, busy indicates the need to
defer the rearbitration of the next bus cycle to insure the
integrity of the above operations. This difference provides the
indivisible memory access required for a "test-and-set" primitive, using anyone of several read-modify-write instructions.
Busy does not become active during PSH or PUL operations.
A typical read-modify-write instruction (ASL) is shown in
Figure 12. Timing information is given in Figure 13. Busy is
valid tCD after the rising edge of Q.
•
Fast-Interrupt Request (FIRO)*
A "Low" level on this input pin will initiate a fast interrupt
sequence, provided its mask bit (F) in the CC is clear. This
sequence has priority over the standard Interrupt Request
(IRQ), and is fast in the sense that it stacks only the contents
of the condition code register and the program counter. The
interrupt service routine should clear the source of the interrupt
before doing an RTI. See Figure 10.
• AVMA
AVMA is the Advanced VMA signal and indicates that the
MPU will use the bus in the follOWing bus cycle. The predictive
nature of the AVMA signal allows efficient shared-bus multiprocessor systems. AVMA is "Low" when the MPU is in either a
HALT or SYNC state. AVMA is valid tCD after the riSing edge
ofQ.
• Interrupt Request (I R0) *
A "Low" level input on this pin will initiate an Interrupt
Request sequence provided the mask bit (I) in the CC is clear.
Since IRQ stacks the enUre machine state it provides a slower
response to interrupts than FIRQ. IRQ also has a lower priority
than FIRQ. Again, the interrupt service routine should clear
the source of the interrupt before doing an RTI. See Figure 9.
• L1C
LIC (Last Instruction Cycle) is "High" during the last cycle
of every instruction, and its transition from "High" to "Low"
will indicate that the first byte of an opcode will be latched at
the end of the present bus cycle. LIC will be "High" when the
MPU is Halted at the end of an instruction, (Le., not in CWAI or
RESET) in SYNC state or while stackillg during interrupts.
L1C is valid tCD after the rising edge of Q.
•
NMI. fTRQ, and fRO requests are ,ampled on the falhng edge of Q.
One l'yde IS reqUired for lIynchronlzatJOn before these Interrupts are
rcco~nu;ed. The pendmp: interrupUs) will not be serviced until
completion of the current instruction unlc'IlI a SYNC or CWAI
condition is present. If IRQ and FIRQ do not remam "Low" unlll
completIOn of the current instlUl'tlon they may not be recognized.
However. NMI is latl..'hcd and need only remam "Low" for one cycle.
• Clock Inputs E. 0
E and Q are the clock signals required by the HD6309E.
Q must lead E; that is, a transition on Q must be followeQ by a
similar transition on E after a minimum delay. Addresses will
be valid from the MPU, tAD after the falling edge of E, and
data will be latched from the bus by the falling edge of E.
While the Q input is fully TTL compatible, the E input directly
drives internal MOS circuitry and, thus, requires levels above
normal TTL levels. This approach minimizes clock skew
inherent with an internal buffer. Timing and waveforms for E
and Q are shown in Figures I and 2 while Figure II shows a
simple clock generator for the HD6309E.
• BUSY
Busy will be "High" for the read and modify cycles of a read·
modify-write instruction and during the access of the first byte
• TSC
TSC (Three-State Control) will cause MOS address, data,
and R/W buffers to assume a high-impedance state. The control
signals (BA, BS, BUSY, AVMA and L1C) will not go to the
high-impedance state. TSC is intended to allow a single bus to
be shared with other bus masters (processors or DMA controllers).
While E is "Low", TSC controls the address buffers and R/W
directly. The data bus buffers during a write operation are in a
high-impedance state until Q rises at which time, if TSC is
true, they will remain in a high-impedance state. If TSC is held
beyond the rising edge of E, then it will be internally latched,
keeping the bus drivers in a high-impedance state for the
remainder of the bus cycle. See Figure 14.
• MPU Operation
During normal operation, the MPU fetches an instruction
from memory and then executes the requested function. This
sequence begins after RES and is repeated indefinitely unless
altered by a special instruction or hardware occurrence. Software instructions that alter normal MPU operation are: SWI,
SWl2, SW13, CWAI, RTI and SYNC. An interrupt or HALT
input can also alter the normal execution of instructions.
Figure 15 illustrates the flow chart for the HD6309E.
~HITACHI
286
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
i
~
2:
»
~
:::>.
~
Last Cycle
of Current
Instruction
I' . I,
a
•
:::t:
i.
~
E
Q
•
§
~.
~
:t
a~
"0
~:t
•
D:I
:::>.
'"~
~
!"
§;
~
FFFD FFFF
{iiiQil
FFF9
iRUor
{TRtlI
NMi
Dem __~__- J ' -__~__~__-J~__~---n--~~--~---n~--~--~--~~--n---~---J'---~--~~~'---~---n~~~__~__~
V1iiIA PCl PCH
Ul
UH
YL
YH
Xl
XH
DP
B
A
CC
A New New V1iiIA
PCH
PCl
::x::::c:::J.===========------;::::::~-x: : c: :J.
RtW~
BA
,
I
I
BS - - v - - - - v - - - v - - "
::::>.
r-\
BUSY --A---A---J
AVMA
llC
,'------
I
E
1::
a>
(NOTE)
Waveform measurements for allmputs and outputs are specified at logic "High" = V IHmin and logic "Low"· VILmax unless otherwise specified.
E clock shown for reference only.
$
I
I\)
co
-..J
c=.
',-_ __
S
~
co
•
New New
PC PC + 1
Figure 9 IRQ and NMllnterrupt Timing
w
ttl
o
<.0
t:El
S
a>
w
o
o
<.0
t:El
::r::
N
00
00
tJ
(J')
Last Cycle
of Current
Instruction
I_
~
w
Instruction
-I·
-I-
Interrupt Stacking and Vector Fetch Sequence
Q)
Fetch
ttl
oCO
.. I
(")
=r.
m+9 _1_
»
n
-,-
3
CD
::!.
_L n+1
_I
1-
I
tJ
w
()
o
E
C"l
(J')
1"
r-
et
•
;;;
1!i
=r.
Q
Address
Bus
FIRQ
'"
8
w-~
Data
CO
r
VIL~~~~~
'~Cf
"0
~
•
VIH
PC
PC
FFFF
SP-l
SP-2
SP-3
$FFFF
$FFF6
$FFF7
$FFFF
New PC New PC+ 1
tpcs
VWi
_
~ :I
PCl
CC
PCH
VMA
New PCH
New PCl
VMA
"0
2. ~
;:;'l>
l'C)
;§ :I
•
RfiI~
(J>
Il>
BS
::::l
'"
§;
...o
I
\
BA~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
t:C
::!.
0-
~
/
\\-.._ _ _ _ _ _ _ __
AVMA
<0
~
BUSY
00
<0
0,
W
o
o
tr::I
::r::
(NOTE)
Waveform measurements for all Inputs and outputs are specified at logic "High"
E clock shown for reference only.
=
V IHmin and logiC "Low"
Figure 10 FIRQ Interrupt Timing
= V ILmax unless otherwise specified.
tr::I
HD63B09E, HD63C09E
I
I
I
I
I
IMRo
I
I
I
I
L ___ _
74LS04
E}
a
+5V
T o MPU and MPU System
74LS04
NOTE
4)( fo
If optional CirCUit IS not Included the CLR and PRE
Inputs of U2 and U3 must be tied high
a
MROY
~-------------------u
Figure 11
HD6309E Clock Generator
Memory
Memory
Location
Contents
PC -> $0200
S68
ASL Indexed Opcode
$0201
S9F
Extended Indirect Postbyte
$0202
S63
Indirect Address HI-Byte
$0203
SOO
$0204
------
--
Indirect Address La-Byte
Next Main Instruction
---.
~~(?J
$6301
Contents Descnptlon
S06
Effective Address HI-Byte
Effective Address La-Byte
Figure 12 Read Modify Write Instruction Example (ASL Extended Indirect)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
289
N
CD
::r:
Last Cycle of
Current Instr.
0
I
::J:
s:n
m-l
m
I
I
m+l
• •
I
m+2
•
m+3
•
I
m+4
•
I
I_
m+5
.1-
m+6
. 1m+7
..I
m+ 8
m+9
•I.
m+l0
.I
I
•
J::1:j
Q
»
3
6
A_
.
<">
0')
E"
..?-
c.v
oo
Data
•
(0
::r
;:;:
J::1:j
I»
BUSY
(')
:!:
31
'"
'"•
0'"
0
LIC
N
AVMA
==::::::' - \
I
E
0
~.
;;;
-0 :I
_
~~
~(')
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High" = V IHmin and logic "Low"
= V ILmax unless otherwise specified.
Figure 13 BUSY Timing (ASL Extended Indirect Instruction)
~ :I
•
m
::>.
tIl
o
(0
E
:!:
I
t:l
0')
c.v
-
en
t:T
'":::>
5D
n
»
~
0
~
($
<0
•
~
~
~
0
0
(NOTESI Data will be asserted by the MPU only durin9the interval while RlWis "Low" and E or Q is "High".
Waveform measurements for all inputS and outputs are specified at logic uHigh'" = V IHmin and logic "Low" = V ILmax unless otherwise specified.
Figure 14 TSC Timing
\
:J:
~
=r.
l>
3
CI)
fi·
'"
Ei
•
:J:
;::;:
n
'"=r.
"'0
~
•
8""
~.
;;;"'0 J:
_
Q.
~
a~
~(')
~ J:
•
o::J
::l.
en
C"
'"=>
CI)
C")
l>
':f
~
CWAI
~
<0
Co.)
HD6309E Interrupt Structure
•
~
Bus State
BA
BS
~
Running
0
0
~
Interrupt or Reset Acknowledge
0
1
1
1
0
1
i
o
Sync Acknowledge
(NOTES) 1. Asserting R'ES will result
Halt AcknowleC!9! _________
In
entering the reset
tIl
o
c.o
trl
::r::
tj
en
sequence from any point in the flow chart.
2. BUSY is "High·· during first vector fetch cycle.
Co.)
()
I\)
CO
8en
Figure 15 Flowchart for HD6309E Instruction
o
c.o
trl
HD63B09E, HD63C09E
• ADDRESSING MODES
The basic instructions of any computer are greatly enhanced
by the presence of powerful addressing modes. The 1I>6309E
has the most complete set of addressing modes aruable on
any microcomputer today. For example, the 1I>6309E has 59
basic instructions; however, it recognizes 1464 different varia·
tions of instructions and addressing modes. The addressing
modes support modem programming techniques. The following
addressing modes are available on the HD6309E:
(I) Implied (Includes Accumulator)
(2) Immediate
(3) Extended
(4) Extended Indirect
(5) Direct
(6) Register
(7) Indexed
Zero-Offset
Constant Offset
Accumulator Offset
Auto Increment/Decrement
(8) Indexed Indirect
(9) Relative
(10) Program Counter Relative
• Implied (lnclud.. Accumulator)
In this addressing mode, the opcode of the instruction
contains all the address information necessary. Examples of
Implied Addressing are: ABX, OAA, SWI, ASRA, and CLRB.
• Immediate AddNlling
In Immedia te Addressing, the effective address of the data
is the location immediately following the opcode (i.e., the data
to be used in the instruction immediately follows the opcode
of the instruction). The HD6309E uses both 8 and l6-bit
immediate values depending on the size of argument specified
by the opcode. Examples of instructions with Immediate
Addressing are:
LOA #$20
LOX #$FOOO
LOY #CAT
• DiNCt AddressIng
Direct addressing Is similar to extended addressing except
that only one byte of address follows the opcode. This byte
specifies the lower 8 bits of the address to be used. The upper
8 bits of the addres.; are supplied by the direct page register.
Since only one byte of address is required .in direct addressing,
this mode requires less memory and executes faster than
extended addressing. Of course, only 256 locations (one page)
can be accessed without redefining the contents of the OP
register. Since the OP register is set to 500 on Reset, direct
addressing on the HD6309E is compatible with direct addressing
on the HD6800. Indirection is not allowed in direct addressing.
Some examples of direct addressing are:
LOA
530
SETDP 510
(Assembler directive)
LOB
51030
»
3
<'D
~.
!"
Et
•
::t:
;:;:
'"
:
"t:J
;;;N
'"•
N
<:>
<:>
<:>
~~
;;;"t:J :I
_
~~
~O
~ :I
ASLA
ASLB
ASRA
ASRB
CLRA
CLRB
COMA
COMB
DAA
DECA
DECB
INCA
INCB
LSLA
LSLB
lSRA
LSRB
NEGA
NEGB
NOI'
ROLA
ROLB
RORA
RORB
SEX
TSTA
TSTB
ABX
RTS
TFR
EXG
MUL
SWI
SWl2
SWl3
PULU
PULS
PSHU
PSHS
WA
VMA
VMA
STACK (RI
STACK (RI
VMA
STACK (RI
AD DR
VMA
VMA
VMA
RTI
CWAI
VMA
VMA
VMA
VMA
VMA
VMA
=:
--
V!A
I
VMA
VMA
I
V~A
I}
VMA
VMA
VMA
1,2
VMA Stack (WI 0
VMA (Note 31
12
VMA
{Stack (RI} ,
(Note 31 0
I
I
I
STACK (WI
STACK (WI
STACK (WI
STACK (WI
STACK (WI
STACK (WI
STACK (WI
STACK (WI
STACK (WI
STACK (WI
ADDR~SP
•
I
STACK (WI STACK (WI
STACK (WI STACK (WI
AODR ~SP
VMA
I
VMA
I
STACK
STACK
STACK
STACK
STACK
STACK
STACK
STACK
STACK
STACK
VMA
I
(WI
(Wi
(WI
(WI
(WI
(WI
(WI
(WI
(WI
(WI
I
7;
00
VMA;
I
en
cr
'"
:0
:::J
(")
»
..,.
<:>
I
VMA
!
1
VMA
<.0
<:>
9'
00
.
(RI
(RI
(RI
(RI
(RI
(RI
STACK (RI
(RI
STACK (RI
(RI
~TACK (RI
STACK (RI
STACK (RI
0
AD DR ... SP
I
<0
•
~
9
CJl
00
~
w
<:>
<:>
(NOTESI
1. Stack !WI refeB to the foIlowil1!l_: 51' ~ 51' - 1. then ADDR ~ SP with RNi ~ "Low"
Stack (RI refeBto thefollowil19_: ADDR ~SP_ RNi~ "Hi""', then SP ~SP + 1.
PSHU, PULU instructions ... the ....... stack pointer h.e., 51' ~ UI and PSHS, PULS use the hardware stack pointer (•. e., SP = SI.
2. Vector refeB to the _ _ of an interrupt 0< reset _ _ (see T _ 1 I.
3. The number of stack accesses will vary aa:ordil1!l1D the
of by1es _ .
4. VilA cycles will occur until an intenupt occurs.
num_
STACK
STACK
STACK
STACK
STACK
STACK
STACK
STACK
(Not. 41
VECTOR (HI, VECTOR (HI,
BUSY ~1
BUSY ~1
VECTOR (LI, VECTOR (LI,
BUSY ... 0
BUSY ~O
a:I
:l.
_
::r:
tJ
en
w
to
o
to
~
::r:
tJ
en
w
()
N
CO
CO
Figure 18 Address 8us Cyde-by-Cyde Performance (Continued I
o
to
~
HD63B09E, HD63C09E
Non- Implied
AOCA
AOCS
AOOA
AOOB
ANOA
ANOB
BITA
BITB
CMPA
CMPB
EORA
EORS
LOA
LOB
ORA
ORB
SBCA
SBCB
STA
STB
SUBA
SUBB
LOO
LOS
LOU
LOX
LOY
ASL
ASR
CLR
COM
DEC
INC
LSL
LSR
NEG
ROL
ROR
ANOCC
ORCC
TST
STO
STS
STU
S'rX
STY
(NOTES)
1. Stack (W) refers to the fol!Q.wlng sequence: SP (- SP - 1,
then ADDR ...- SP with RIW = "Low"
Stack (R) refers to the following sequence: ADDR (- with
RtW = "High", then SP (- SP + 1
PSHU, PULU instructions use the user stack pointer (Le.,
SP = U) and PSHS, PULS use the hardware stack pointer
(ie,SP=S)
2. Vector refers to the address of an Interrupt or reset vector
(see Table 1).
3. The number of stack accesses will vary according to the
number of bytes saved.
4. VMA cycles will occur until an Interrupt occurs
VMA
STACK (WI
STACK (WI
VMA, BUSY <-1
AOOR +
BUSY <-0
AOOR +
imA"
ADOR +
JSR
AOOO
CMPO
CMPS
CMPU
CMPX
CMPY
SUBO
I
ADDR + (Wi
VMA
VMA
Figure 18 Address Bus Cycle-by-Cycle Performance (Continued)
Table 4 8-Bit Accumulator and Memory Instructions
Mnemonic(s)
Operation
ADCA,ADCB
Add memory to accumulator with carry
ADDA, AD DB
Add memory to accumulator
ANDA,ANDB
And memory with accumulator
------------------ -
ASL, AS LA, ASLB
Arithmetic shift of accumulator or memory left
ASR,ASRA,ASRB
Arithmetic shift of accumulator or memory right
BITA, BITB
B it test memory with accumulator
CLR, CLRA, CLRB
Clear accumulator or memory location
CMPA, CMPB
Compare memory from accumulator
COM, COMA, COMB
Complement accumultor or memory location
DAA
Decimal adjust A accumulator
DEC,DECA,DECB
DeCrement accumulator or memory location
EORA, EORB
Exclusive or memory With accumulator
EXG Rl, R2
Exchange Rl with 1'12 (I'll, R2 = A, B, CC, OP)
INC, INCA, INCB
InCrement accumulato. or memory location
LOA, LOB
Load accumulator from memory
LSL, LSLA, LSLB
Logical shift left aCcumulatOr Or memory location
LSR, LSRA, LSRB
Logical shift right accumulatOr or memory location
•
300
HITACHI
(Continued)
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09E, HD63C09E
Table 4 8·Bit Accumulator and Memory Instructions (Continued)
Mnemonictsl
MUL
NEG, NEGA, NEGB
ORA,ORB
ROL, ROLA, ROLB
ROR, RORA, RORB
SBCA,SBCB
STA,STB
SUBA,SUBB
TST, TSTA, TSTB
TFR R1, R2
Operation
Unsigned multiply (A x B -+ D)
Negate accumulator or memory
Or memory with accumula!_or______
Rotate accumulator or memory left
Rotate accumulator or memory right
Subtract memory from accumulator with borrow
Store accumulator to memory
Subtract memory from accumulator
Test accumulator or memory location
Transfer R1 to R2(R1, R2 =A, B, CC, OP)
{NOTE I A, B, CC or DP may be pushed '0 {pulled froml el.her Slack wl.h PSHS, PSHU
(PULS, PULUllnstruc'lons.
Table 5 16·Bit Accumulator and Memory Instructions
Mnemonic(s)
AOOO
CMPD
EXG 0, R
LOO
SEX
STO
SUBO
TFR 0, R
TFR R,O
Operation
Add memory to 0 accumulator
Compare memory from 0 accumulator
Exchange 0 with X, Y, S, U or PC
Load 0 accumulator from memory
Sign Extend B accumulator into A accumulator
Store 0 accumulator to memory
Subtract memory from 0 accumulator
Transfer 0 to X, Y, S, U or PC
Transfer X, Y, S, U or PC to 0
(NOTE) 0 may be pushed {pulledlto ei.her .... k WIth PSHS, PSHU (PULS, PULU)
Instructions.
Table 6 Index Register Stack Pointer Instructions
Mnemonic(s)
CMPS,CMPU
CMPX,CMPY
EXG R1, R2
LEAS,LEAU
LEAX, LEAY
LOS, LOU
LOX, LOY
PSHS
PSHU
PULS
PULU
STS, STU
STX,STY
TFR R1, R2
ABX
Operation
Compare memory from stack pointer
Compare memory from index register
Exchange 0, X, Y, S, U or PC with 0, X, Y, S,U or PC
Load effective address into stack pointer
Load effective address into index register
Load stack pointer from memory
Load index register from memory
Push A, B, CC, OP, 0, X, Y, U,or PC onto hardware stack
Push A, B, CC, OP, 0, X, Y, S, or PC onto user stack
Pull A, B, CC, OP, 0, X, Y, U or PC from hardware stack
Pull A, B, CC, OP, 0, X, Y, S or PC from user stack
Store stack pointer to memory
Store index register to memory
Transfer 0, X, Y, S, U or PC to 0, X, Y, S, U or PC
Add B accumulator to X (unsigned)
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589·8300
301
HD63B09E, HD63C09E
Table 7 Branch Instructions
Mnemontc(s)
---
Operation
SIMPLE BRANCHES
BEQ, LBEQ
Branch if equal
BNE, LBNE
Branch if not equal
BMI, LBMI
Branch If minus
BPL, LBPL
Branch If plus
BCS,LBCS
Branch If carry set
BCC,LBCC
Br anch If carry clear
BVS, LBVS
Branch If overflow set
BVC,LBVC
Branch If overflow clear
BGT, LBGT
Branch if greater (signed)
SIGNED BRANCHES
BGE, LBGE
Branch if g~eater than or equal (signed)
--------~B~E~Q~,~L~B~E~Q=----------t---~B~ra-n-c~h~i~f~eq~ual
-----------------------------------------------------------Branch if less than or equal (signed)
~
BLE, LBLE
----BLT,LBLT
-,
Branch if less than (signed)
UNSIGNED BRANCHES
BHI, LBHI
Branch if higher (unsigned)
BHS,LBHS
Branch if higher Or same (unsigned)
BEQ, LBEQ
Branch if equal
BLS, LBLS
Branch if lower or same (unsigned)
BLO,LBLO
Branch if lower (unsigned)
BSR, LBSR
Branch to subroutine
BRA, LBRA
Branch always
BRN, LBRN
Branch never
OTHER BRANCHES
Table B Miscellaneous Instructions
Operation
Mnemonic(s)
ANDCC
AND condition code register
CWAI
AND condition code register, then wait for interrupt
NOP
No operation
ORCC
OR condition code register
JMP
Jump
JSR
Jump to subroutine
RTI
Return from interrupt
RTS
Return from subroutine
SWI, SWI2, SWI3
Software interrupt (absolute indirect)
SYNC
Synchronize with interrupt line
~HITACHI
302
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09E, HD63C09E
Table 9. HD6309E Instruction Set Table
INSTRUCTIONS!
FORMS
ABX
AOC
ADD
AND
ASL
ASR
IMP
OP -
DIRECT
EXTND
IMMED
INDEX(j) RELATIVE
# OP - # OP - # OP
# OP - # OP -151 #
3A 3
1
ACCM REG
AOCA
AOCB
ADDA
ADDB
ADDD
ANDA
ANDB
ANOCC
B+X-X
(UNSIGNED)
99
D9
9B
DB
D3
4
4
4
•
6
9' 4
D4
•
ASLA
ASLB
ASL
48 2
58 2
ASRA
ASRB
ASR
47 2
57 2
2
2
2
2
2
2
2
B9
F9
BB
FB
F3
B.
F4
5
5
5
5
7
5
5
3
3
3
3
3
3
3
89
C9
8B
CB
C3
84
C4
1C
2
2
2
2
4
2
2
3
2
2
2
2
3
2
2
2
2+
A+M+C--A
2+
2+
2+
2+
A 4 4 + 2+
E 4 4 + 2+
8+M+C-S
A9 4 +
E9 4+
AS 4 +
EB 4 +
E3 6+
B+M-B
O+MM+ 1 ...... 0
Ai\M-A
Bi\M-B
CCi\IMM-CC
08 6
2 78 7
3
68 6 + 2+
MCb,.
67 6 + 2+
!
1
1
A}
07 6
2 77 7
3
BCC
LBCC
24 3
2
10 5(6) 4
24
BCS
BEQ
BGE
BGT
BCS
LBCS
25 3 2
lO 5i61 4
25
27 3 2
BEQ
LBEQ
BGE
LBGE
BGT
LBGT
_
BHI
LBHI
BHS
BHS
LBHS
BIT
BLE
BITA
BITB
BLE
LBLE
2 B5 5
2 F5 5
3 85 2
3 C5 2
2 AS 4 + 2 +
2 E5 4 + 2 +
. BLS
BLO
LBLO
BLS
LBLS
BLT
BMl
BLT
LBLT
BMI
LBMI
C~l
C~l
Branch
Z~ 1
Z~ 1
Branch
N0v~o
N0V~o
Branch ZV(NE!)v)~ 0
Long Branch
ZViN0V ,~ 0
Branch
Cv Z~O
Long Branch
Cv Z ~ 0
Branch
t.:=O
Long Branch
C~O
Bit Test A (MI\A I
Bit Test B (MAS)
2F 3 2
1 0 5i61 4
2F
BLO
Branch
Long Branch
Long Branch
1 0 5i61 4
24
95 4
D5 4
C~O
27
2C 3 2
10 5i61 4
2C
2E 3 2
22 3 2
1 0 5i61 4
22
24 3 2
C
Long Branch
Long Branch
2E
BHl
bo
C~O
1 0 5(6) 4
1 0 5(6) 4
1-0
b.
Q'IIIIIII~
Branch
Branch ZViN0vl~1
Long: Branch
ZViN0VI~l
C~l
25 3 2
1 0 5i61 4
25
23 3 2
Branch
1 0 5(6) 4
23
2D 3 2
lO 5i61 4
2D
28 3 2
Long Branch
10 5(6) 4
28
Long Branch
C~l
Branch
Cv Z ~ 1
CVZ~l
Branch
N(i)V~l
Lona Branch
N0V~1
Branch
N=l
Long Branch
N~l
5
H
4
I
3
N
2
Z
1
V
0
C
••••••••
••• ••• •••
•• •• • ••
••
•• r-•• r-•• ••
•• •• ••
•• •
•• •• • ••
• • •• •
•• •• •• •• •• •• •• ••
I
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
R
R
<7l
i
:}~Imr'l
1
1
6
F
1
1
I
1
A+M-A
b1
BCC
7
E
DESCRIPTION
I
1
I
I
I
1
I8l
I8l
I8l
I
I
I
I
I
I
I8l
I8l
I8l
1
I
1
I
I
I
I
I
I
I
I
I
I
I
I
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
••••••••
• •• • • •• •
•• •• •• ••
••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
••••••••
•• ••• • • •
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
I
I
I
I
R
R
(Continued)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
303
HD63B09E, HD63C09E
INSTRUCTIONSI
FORMS
KNE
Kl'l
KRA
KRN
KSR
(.;J:I~,.;(.
O~
-
#
DIRECT
EXTND
# O~ -
O~
#
IMMED
O~
-
#
INDEXCD RELATIVE
- # OP -@ #
DESCRIPTION
O~
KNt:
lKNE
26 3
2
10 516) ..
Branch
Z~O
Long Branch
Hi'L
26
2A 3
L1!I'l
10 5(6) 4
KRA
lKRA
KRN
lKRN
2A
20
16
2I
10
21
3
5
3
5
2
3
2
4
KSR
8D 7
2
Branch to
Z~O
2
Branch
N~O
Long Branch
N~O
Branch Always
Long Branch Always
Branch Never
Long Branch Never
Subroutme
lKSR
17 9
3
Long Branch to
KVe
lKve
28 3
2
Branch
Subroutine
KVe
8VS
8VS
l8VS
Long Branch
28
29 3
Branch
CMI'
ClRA
ClR8
ClR
4F 2
SF 2
I
I
OF
9I
DI
10
93
II
9C
II
93
9C
CM~A
CMPH
CMI'D
CMI'S
CMI'U
CMI'X
CMPY
COM
COMA
COMB
COM
6
4
4
7
7
7
6
10 7
9C
43 2
53 2
2 7F 7
2 8I 5
2 FI 5
3 10
83
3 II
BC
3 II
B3
2 BC 7
"
"
"
3 10
BC
"
3
3 • I 2
3 CI 2
4 10 5
.3
4 II 5
BC
4 II 5
.3
3 HC 4
4
EOR
EXG
INC
JMI'
JSR
10 5
HC
6 F 6 + 2+
2 A I 412 E I .. +
4 10 7 +
A3
4 117 ...
AC
4 117+
A3
3 AC 6 +
03 6
2 73
7
Compare M M + I
from S
3+
Compare M M + 1
2+
Compare M M + 1
19 2
4A 2
5A 2
IE H
4C 2
5C 2
2 7A 7
2 B8 5
2 F. 5
63 6-+ 2 +
3
3 88 2
3 C. 2
Compare M M + 1
from D
I
I
I
OA 6
98 4
D8 4
Compare M (rom
from
6A 6 + 2+
2 A 8 4-l- 2 +
2 E 8 .. + 2 +
2
I
I
U
from X
Compare M M + 1
from Y
A-A
ii-B
M-M
CC A IMM-cC
Walt (or Interrupt
Decimal Adjust A
A-I-A
B-I-B
M-I-M
A(i)M-A
B(i)M-B
RI-R2®
A+I-A
B+I-B
OC 6
OF. 3
9D 7
2 iC 7
2 7E 4
2 BD 8
3
3
3
6
F
5
H
4
I
3
N
6e 6 + 2+
6E 3+ 2+
M+ I-M
EA@-I'C
AD i + 2 +
Jump to Subroutme
A
B
2
Z
I
V
0
C
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
••••••••
••••••••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• ••
•• •• • ••
•• •• • ••
••••
••••
••••
••••
••• ••• ••• •••
R
R
3+
3C "20 2
DECA
DECK
DEC
EORA
EORK
RI. R2
INCA
INCK
INC
V~I
O-A
O-B
O-M
Compare M from
4 10 7 + 3 +
AC
3
V~I
Long Branch
2+
2+
3+
I
I
CWAI
DAA
DEC
V~O
2
10 5(6) 4
29
ClR
V~O
10 516) 4
7
E
@
@
S
R
R
R
R
R
S
S
S
I
I
I
I
I
I
I
I
I
I
I
I
I
I
!
!
R
R
I
I
I
I
!
I
I
I
I
I
I
I
I I R
I I R
I I R
It-- t-- (7)t-- t--
S
S
S
)
••• ••• ••• ••• : ••
••
••• ••• ••• •••
•
••
••• ••• ••• •••
•• •• •• •• •• •• •• •••
I
I
I
!
I
I
I
I
I
I
I
I
@
I
!
!
I
I
!
I
I
I
I
I
I
R
R
I l -t-- ®
)
(Continued)
~HITACHI
304
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09E, HD63C09E
INSTRUCTIONS!
FORMS
LD
EXTND
IMMED
INDEX.
Me
Return from
Return from
I
92 4
D2 4
ID 2
I
I
I
C
Push Registers on
U Stack
Pull Registers
from S Stack
09 6
SBCA
SBCB
0
C
I
I
Interrupt
SBC
I
V
No Operauon
2 AA 4 + 2 +
2 EA 4 + 2 +
2
3B~15 I
RTS
2
Z
•• •• •• ••
•••
•• •• •• ••
•
••
•• •• •• ••
••••
•
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• ••
! [}11111111 j.O •• •• •• ••
••••
0.,b,1111111b,HJ ••• ••• ••• ••• •••
••••• •
•• •• ••
ii+
•• •• • •• • • • •
•• •• •• ••
••
r••••••••
••••••••
C b,.---.bo
RTI
3
N
AXB-D
(UnsIgned)
I
ORA
ORB
ORCC
PSHS
6
F
M-A
M-B
MMtl-D
MM'I-S
A}
08 6
12 2
A6
E6
EC
10
EE
3 EE
3 AE
4 10
AE
32
33
30
31
2
2
3
4
7
E
DESCRIPTION
2 B2 5
2 F2 5
3 82 2
3 C2 2
2 A2 4 t 2 +
2 E2 4 + 2 +
I
Subroutll'le
A-M-C-A
B-M-C-B
Still Extend B mto A
IB"',," d 7=1 FF-A
8(1)1::"/~7=:.O
O-A
I
I
I
I
I
I
I
I
I
I
I
•••
I
I
I
I
I
I
I
I
I
( t - t- <:!J
I
)
••••••••
•• •• ••
•••• ••
C8l
C8l
I
I
I
I
I
I
I
I
I
I
(Contlnuea)
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
305
HD63B09E, HD63C09E
AC.;dr!tkHG
INSTRUCTIONS!
~ORMS
ST
OP -
STA
STB
STD
STS
97 4
D7 4
DO 5
10 6
OF
OF 5
STU
STX
STY
SUB
9F 5
10 6
SUBA
SUBB
SUBD
SWI
SW!$OOOO) addr... bu. load capacitance = 90pF
F,gure 22 Noise at address bus output changing
~HITACHI
312
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD63B09E, HD63C09E
Countermeasure: To prevent the noise on BUSY, LIC, AVMA
outputs from appearing, this signals must be
latched at the negative edge of E or Q clock as
shown in Figure 23. An example of counter·
measure circuit is shown in Figure 24.
E
Q
Ao -All
BUSY
LlC
AVMA
Figure 23 An example of countermeasure of the noise
74L S74
BUSY
LIC
AVMA
eor
cr
:
~:
•
°1
Figure 24 An example of countermeasure circuit
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300
31 3
HD6802---------------MPU
(Microprocessor with Clock and RAM)
The H06802 is a monolithic 8-bit microprocessor that contains all the registers and accumulators of the present H06800
plus an internal clock oscillator and driver on the same chip.
In addition, the H06802 has 128 bytes of RAM on the chip
located at hex addresses 0000 to 007F. The first 32 bytes of
RAM, at hex addresses 0000 to 001 F, may be retained in a low
power mode by utilizing V cc standby, thus facilitating memory
retention during a power-down situation.
The H06802 is completely software compatible with the
H06800 as weD as the entire HMCS6800 family of parts.
Hence, the H06802 is expandable to 65k words.
•
•
•
•
•
•
•
FEATURES
On-Chip Clock Circuit
128 x 8 Bit On-Chip RAM
32 8ytes of RAM are Retainable
Software-Compatible with the HD6800
Expandable to 65k words
Standard TTL-Compatible Inputs and Outputs
• PIN ARRANGEMENT
o
ReS
EXTAL
XTAL
E
RE
• 8 Bit Word Size
• 16 Bit Memory Addressing
• Interrupt Capability
• Compatible with MC6802
"ccStandbV
Rm
0,
0,
HD6802
•
A. 1
BLOCK DIAGRAM
D.
D.
A. 1
A.
Vce
Vce
Vee
4
D.
D,
A. 1
Vee
Standby Vee
A, 1
Au
A..
Au
Au
A, 1
A,1
A IO 1
Counterl {
Timor I/O
lm
Au _ _ _ _ _ _ _ _ _r- Vss
iRa 1---+.....--'1
cs,
D,
0,
-l
~V~M:.::A~_ _
(Top View)
P...lltl {
I/O
XTAll-......---,
CJ
Crystal
Control {
C,;,;
$
314
~C'
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6802
• ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
Symbol
Value
Vee·
Vee Stand by·
-0.3- +7.0
V
-0.3 - +7.0
Unit
Input Voltage
Vln •
Operating Temperature
Topr
-20 - +75
V
°c
Storage Temperature
T,,,,
-55 - +150
°c
• With 'espect to Vss (SYSTEM GNDI
(NOTE)
•
Permanent LSI damage may occur If maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions 8re exceeded, It could affect reliability of LSI.
RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage
Symbol
min
typ
max
Unit
Vee·
Vee Standby·
4.75
5.0
5.25
V
VIL
-0.3
-
O.S
V
Vee
V
25
Vee
75
V
°c
Input Voltage
L
VIH*
Operation Temperature
.
Except RES
2.0
RES
4.25
-20
I
Top,
-
• With ,espect to Vss (SYSTEM GND)
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc-6.OV±6%, Vee Standby-6.0V±6%, Vss-OV, T.--2G-+75°C, unle.. otherwise
Symbol
Item
Input "High" Voltage
Input "Low" Voltage
Except RES
VIH
RES
Exceptm
Output "Low" Voltage
Three State (Off Statellnput Current
Input Leakage Current
Power Dissipation
Input Capacitance
Output Capacitance
0 0 -0,.
Except Do -0,
....
Except 0 0 -0,
Ao-A IS , R/W, SA,
VMA,E
• In power·down mode, maximum power dissipation
•• T.-25" e, V -5V
IS
Vee
O.S
-
VOH
2.4
-
VOL
ITsl
I,n
IOH = -145jlA
IOH = -l00jlA
IOL = 1.6mA
Vln = 0.4-2.4 V
Vin = G-5.25V
-10
-2.5
-
-
Vee
O.S
-
Unit
V
V
-
V
0.4
V
jlA
jlA
10
2.5
-
0.6
10
1.2
12.5
C.n
V,n=OV, T.=25°C,
f=1.0MHz
-
6.5
10
c"ut
Vln=OV, T.=25°C,
f=1.0MHz
-
-
12
Po *
0 0 -0,
-
-0.3
2.4
2.4
IOH = -205jlA
Ao-A IS , RfR, VMA
SA
noted.1
typ*- max
-0.3
VIL
1m
min
2.0
4.25
...
00-0" E
Output "High" Voltage
Test Condition
W
pF
pF
less than 42mW .
••• As 'ft'n inpucrh•• hilt.rHis character, applied voltage up to 2.4V IS regarded 8S "Low" level when It goes up from
•••• Does not include EXTAL and XTAL. which are crystal inputs .
•
av .
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
315
HD6802
• AC CHARACTERISTICS (Vee-5.OV±5%. Vee Standby-5.0V±5%. Vss-oV. Te--20-+75°C. unles. otherwise noted.1
1. CLOCK TIMING CHARACTERISTICS
Item
Frequency of Operation
I Input Clock + 4
I Crystal Frequency
Cycle Time
PWt/>M
PWt/>L
Fig. 2. Fig. 3
at 2.4V (Fig. 2. Fig. 31
at 0.4V (Fig. 2. Fig. 31
t.p
O.4V - 2.4V(Fig.2.Fig.3)
feyC
I "H igh" Level
I "Low" Level
Clock Pulse Width
Clock Fall Time
Test Condition
Symbol
f
fXTAL
min
0.1
1.0
1.0
450
-
typ
-
Unit
max
1.0
4.0
10
MHz
4500
ns
25
ns
-
jlS
2. READIWRITE TIMING
Item
Address Delay
Peripheral Read Access Time
Data Setup Time (Read)
Input Data Hold Time
Output Data Hold Time
Address Hold Time (Address. RIW. VMA)
Data Delay Time (Write)
Bus Available Delay
Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
(Measured at 0.8V and 2.0V)
"Ta = 25°C. Vcc
Symbol
Test Condition
min
-
tAM
toow
tSA
Fig. 2. Fig. 3. Fig. 6
Fig. 2
Fig. 2
Fig. 2
Fig. 3
Fig. 2. Fig. 3
Fig. 3
Fig. 4. Fig. 5. Fig. 7. Fig. 8
tpcs
tpcr
tpCf
Fig. 4-Fig. 7. Fig. 12
200
Fig. 4-Fig. 7. Fig. 12.
Fig. 13. Fig. 16
-
tAD
tocc
tOSR
tM
tM
530
100
10
20
10
-
typo
max
Unit
-
270
-
-
-
-
-
225
250
ns
ns
ns
ns
ns
ns
ns
ns
-
ns
100
ns
-
-
=5V
3. POWER DOWN SEQUENCE TIMING, POWER UP RESET TIMING AND MEMORY READY TIMING
Item
RAM Enable Reset Time (11
RAM Enable Reset Time (21
Reset Release Time
RAM Enable Reset Time (31
Memory Ready Setup Time
Memory Ready Hold Time
Symbol
tREl
tRE2
tLRES
tRE3
tSMR
tMMR
Test Condition
Fig. 13
Fig. 13
Fig.
Fig.
Fig.
Fig.
12
12
16
16
typ
min
150
E-3 cycles 20"
0
300
0
-
-
max
-
ms
ns
ns
200
ns
-tRES • 20 msec min. for S type. 50 msec min. for R type.
~HITACHI
316
Unit
ns
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6802
5.0V
c= 130pF for 0,-0" E
= 90pF for A, -Au, R,w, and VMA
= 30pF for BA
R= llkOfor 0,-0" E
= 16kO for A, -Au ,R,w, and VMA
= 24kO for BA
C Includes stray Capacl!tnce.
All dIodes are 152074 Q:f or equIvalent
Figure 1 Bus Timing Test Load
E
R,w
Address
From MPU
VMA
Data
From Momory
or Peripheral.
~ Data Not Valid
Figure 2 Read Data from Memory or Peripherals
f---------- tCYC-----------1
E
2.4V
0.4V
Addra..
FromMPU
VMA
toow
2.4V
0018
From MPU
0.4V
Oa18 Not Vahd
Figure 3 Write Data in Memory or Peripherals
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
317
HD6802
The lall Instruction Cycle
I·
HALTCvcle
+
E
BA
Figure 4 Timing of HALT and BA
HAlTCyde
,
.
Instruction Cycle
La4V
2.0V
HALT
-,
IPc,
O.8V
IPcs
lIlA
\
BA
Figure 5 Timing of
o .v
HAIT and BA
MPU Restarl Sequence
MPUR...t
E
VMA
Figure 6
RES and MPU Restart Sequence
$
318
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6802
WAIT Cycle or
The Last Instruction Cycle
24V
Interrupt Sequence
'I'
\
IRQ. NMI
Figure 7 IRO and NMI Interrupt Timing
The last execution cycle of
+
WAI instruction (#9)
WAIT Cycle
2.4V
BA
Figure 8 WAI Instruction and BA Timing
• MPU REGISTERS
A general block diagram of the HD6802 is shown in Fig. 9.
As shown; the number and configuration of the registers are the
same as for the HD6800. The 128 x 8 bit RAM has been
added to the basic MPU. The first 32 bytes may be operated in a
low power mode via a Vee standby. These 32 bytes can be
retained during power-up and power-down conditions via the
RE signal.
The MPU has three l6-bit registers and three 8-bit registers
available for use by the programmer (Fig. 10).
• Program Counter (PC)
The program counter is a two byte (J6-bit) register that
points to the current program address.
• Stack Pointer (SP)
The stack pointer is a two byte (J6-bit) register that contains
the address of the next available location in an external
push-down/pop-up stack. This stack is normaily a random access
Read/Write memory that may have any location (address) that
is convenient. In those applications that require storage of
information in the stack when power is lost, the stack must be
non-volatile.
• Index Register (IX)
The index register is a two byte register that is used to store
data or a sixteen bit memory address for the Indexed mode of
memory addressing.
• Accumulators (ACCA, ACCB)
The MPU contains two 8-bit accumulators that are used to
hold operands and results from an arithmetic logic unit(ALU).
• Condition Code Register (CCR)
The condition code register indicates the results of an
Arithmetic Logic Unit operation: Negative(N), Zero(Z), Overflow(V), Carry from bit7(C), and half carry from bit3(H). These
bits of the Condition Code Register are used as testable
conditions for the conditional branch instructions. Bit 4 is the
interrupt mask bit(I). The used bits of the Condition Code
Register (B6 and B7) are ones.
Fig. 11 shows the order of saving the microprocessor status
within the stack.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
319
HD6802
MA 3
.37
moo
J;Q[ I
iiAL't 2
TIm.
E"TAL 31
)CTA,L 38
... 7
VMA 5
ARI 34
Vee"PI,. .,35
21 27 28 28 30 3' 32 33
0, D. 0, 0, 0, 0, 0, 0"
VIS· PiM1,21
Figure 9 Expanded Block Diagram
7
0
I
AceA
I
ACea
7
15
I
I.~
I"
IX
I
I
Accumul8tor A
0
Accumul.tor 8
0
Ilndtlt A~I'1et'
0
PC
I
Ptot',", Count.r
0
SP
I
Steck POinte'
Clrrv I F,om alt 71
Overflow
Z...
NeptlV,
IntefNpt mask
HlIf Ctrrv (From alt 31
Figure 10 Programming Model of The Microprocessing Unit
Figure 11 Saving The Status of The Microproceuot' in The Stack
~HITACHI
320
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6802
•
HD6802
MPU SIGNAL DESCRIPTION
Proper operation of the MPU reqUIres that certain control
and timing signals be provided to accomplish specific functions
and that other signal lines be monitored to determine the state
of the processor. These control and timing signals for the
H06802 are similar to those of the H06800 except that TSC,
DBE, 1/11 ,1/11 input, and two unused pins have been eliminated,
and the following signal and timing lines have been added.
RAM Enable (RE)
Crystal Connections EXT AL and XTAL
Memory Ready(MR)
Vee Standby
Enable 1/11 Output(E)
The following is a summary of the H06802 MPU signals:
• Address Bus (Ao - A ls )
Sixteen pins are used for the address bus. The outputs are
capable of driving one standard TTL load and 90pF.
•
Data Bus (Do - 0 7 )
Eight pins are used for the data bus. It is bidirectional,
transferring data to and from the memory and peripheral
devices. It also has three·state output buffers capable of driving
one standard TTL load and 130pF.
Data Bus will be in the output mode when the internal RAM
is accessed. This prohibits external data entering the MPU. It
should be noted that the internal RAM is fully decoded from
$0000 to $007F. External RAM at $0000 to $007F must be
disabled when internal RAM is accessed.
• HALT
When this input is in the "Low" state, all activity in the
machine will be halted: This input is level sensitive.
In the halt mode, the machine will stop at the end of an
instruction. Bus Available will be at a "High" state. Valid
Memory Address will be at a "Low" state. The address bus will
display the address of the next instruction.
To insure single instruction operation, transition of the
HALT line must not occur during the last 250ns of E and the
. HALT line must go "High" for one Clock cycle.
HALT should be tied "High" if not used. This is good
engineering design practice in general and necessary to insure
proper operation of the part.
• ReadIWrite (R/W)
This TTL compatible output signals the peripherals and
memory devices whether the MPU is in a Read ("High") or
Write ("Low") state. The normal standby state of this signal is
Read ("High"). When the processor is halted, it will be in the
logical one state ("High").
This output is capable of driving one standard TTL load and
9OpF.
• Valid Memory Address (VMA)
This output indicates to peripheral devices that there is a
valid address on the address bus. In normal operation, this Signal
should be utilized for enabling peripheral interfaces such as the
PIA and ACIA. This signal is not three-state. One standard TTL
load and 90pF may be directly driven by this active high signal.
• Bus Available (BA)
The Bus Available signal will normally be in the "Low" state.
When activated, it will go to the "High" state indicating that the
microprocessor has stopped and that the address bus is available
(but not in a three-state condition). This will occur if the HALT
line is in the "Low" state or the processor is in the wait state
as a result of the execution of a WAI instruction. At such time,
all three-state output drivers will go to their off state and other
outputs to their normally inactive level.
The processor is removed from the wait state by the
occurrence of a maskable (mask bit 1=0) or nonmaskable
interrupt. This output is capable of driving one standard TTL
load and 30pF.
• I nterrupt Request (I Ra)
This level sensitive input requests that an interrupt sequence
be generated within the machine. The processor will wait, until
it completes the current instruction that is being executed
before it recognizes the request. At that time, if the interrupt
mask bit in the Condition Code Register is not set, the machine
will begin an interrupt sequence. The index Register, Program
Counter, Accumulators, and Condition Code Register are stored
away on the stack. Next the MPU will respond to the interrupt
request by setting the interrupt mask bit high so that no further
interrupts may occur. At the end of the cycle, a 16-bit address
will be loaded that points to a vectoring address which is located
in memory locations FFF8 and FFF9. An address loaded at
these locations causes the MPU to branch to an interrupt
routine in memory.
The HALT line must be in the "High" state for interrupts to
be serviced. Interrupts will be latched internally while HALT is
"Low".
A 3kO external register to Vee should be used for wire-OR
and optimum control of interrupts.
•
Reset (RES)
This input is used to reset and start the MPU from a
power-down condition, resulting from a power failure or an
initial start-up of the processor. When this line is "Low", the
MPU is inactive and the information in the registers will be lost.
If a "High" level is detected on the input, this will Signal the
MPU to begin the restart sequence. This will sta.t execution of a
routine to initialize the processor from its reset condition. All
the higher order address lines will be forced "High". For the
restart, the last two(FFFE, FFFF) locations in memory will be
used to load the program that is addressed by the program
counter. During the restart routine, the interrupt mask bit is set
and must be reset before the MPU can be interrupted by IRQ .
Power-up and reset timing and power-down sequences are
shown in Fig. 12 and Fig. 13 respectively.
• Non-Maskable Interrupt (NMI)
A low-going edge on this input requests that a non-maskbe generated within the processor. As with
the IRQ signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effect on NMI.
The Index Register, Program Counter, Accumulators, and
Condition Code Register are stored away on the stack. At the
end of the cycle, a 16-bit address will be loaded that points to a
vectoring address which is located in memory locations FFFC
and FFFD. An address loaded at these locations causes the
MPU to branch to a non-maskable interrupt routine in memory.
A 3kO external resistor to Vee should be used for wire-OR
and optimum control of interrupts.
Inputs IRQ and 'Nm are hardware interrupt lines that are
sampled when E is "High" and will start the interrupt routine
on a "Low" E following the completion of an instruction. IRQ
and NMI should be tied "High" if not used. This is good engineering design practice in general and necessary to insure
proper operation of the part. Fig. 14 is a flowchart describing the
major decision paths and interrupt vectors of the microprocessor. Table I gives the memory map for interrupt vectors.
inter~ sequence
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
321
HD6802
Vcc
!--tpcs
>4.25V
.,..------~~-~=L+------------l---O.8V
RES ---1--"1
REs
RE
VMA
Option 1
(See Note below)
----.-"1,
Option 2
tt
O~.8~V~
__________
~
~2'OV~/~/-1
~~O~.8~V------------
See Figure 8 for
Power Down condition
tpcr
____--J/
(NOTE)
(I~---------------~,,~------------------
If option 1 is chosen, RES and RE pins can be tied together.
Figure 12 Power-up and Reset Timing
Vcc
E
RE
Figure 13 Power-down Sequence
Figure 14 MPU Flow Chart
•
322
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6802
Conditions for Crystal (4 MHz)
• AT Cut Parallel resonant
• Co =7 pF max.
• R, = 80n max.
Table 1 Memory Map for Interrupt Vectors
Vector
MS
FFFE
FFFC
FFFA
FFF8
LS
FFFF
FFFD
FFFB
FFF9
Description
Restart
Non-Maskable Interrupt
Software Interrupt
Interrupt Request
(RES)
(NMI)
(SWI)
(rna)
• RAM Enable (RE)
A TIL-compatible RAM enable input controls the on-chip
RAM of the H06802. When placed in the "High" state, the
on-chip memory is enabled to respond to the MPU controls. In
the "Low" state, RAM is disabled. This pin may also be utilized
to disable reading and writing the on-chip RAM during a
power-down situation. RAM enable must be "Low" three cycles
before Vee goes below 4.7SV during power-down.
RE should be tied to the correct "High" or "Low" state if
not used. This is good engineering design practice in general and
necessary to insure proper operation of the part .
• EXTAL 8nd XTAL
The 806802 has an internal oscillator that may be crystal
controlled. These connections are for a para11el resonant
fundamental crystal (AT cut). A divide-by-four circuit has been
added to the H06802 so that a 4MHz crystal may be used in
lieu of a I MHz crystal for a more cost-effective system. Pin39 of
the 806802 may be driven externa11y by a TTL input signal if
a separate clock is required. Pin38 is to be left open in this
mode.
An RC network is not directly usable as a frequency source
0/1 pins 38 and 39. An RC network type TIL or CMOS
oscillator will work well as long as the TIL or CMOS output
drives the 806802.
If an external clock is used, it may not be halted for more
than 4.5/-15. The H06802 is a dynamic part except for the
internal RAM, and requires the external clock to retain
information.
c,
Crystal Equivalent Circuit
Recommended Oscillator (4MHz)
39 pin [ } - - - - - - , - - - ,
HD6802
38 pm
0 - - - - -..........,
C,
C, • 22pF ± 20%
z
Figure 15 Crystal Oscillator
When using the crystal, see the note for Board Design of the
Oscillation Circuit in H06802.
• Memory Ready (MR)
MR is a TIL compatible input control signal which allows
stretching of E. When MR is "High", E will be in normal
operation. When MR is "Low", E may be stretched integral
multiples of half periods, thus allowing interface to slow
memories. Memory Ready timing is shown in Fig. 16.
MR should be tied "High" if not used. This is good
engineering design practice in general and necessary to insure
proper operation of the part. A maximum stretch is 4.5/-1s.
r-
2.4V.....k=------I·JI----~\
E
----'"
~O.4V
~tSMR
tHMR
tPCf
/
tPCr
MR
Figure 16 Memory Ready Control Function
• HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
323
HD6802
• EIIIbI. lEI
This pin supplies the clock. for the MPU and the rest of the
system. This is a single phase, TTL compatible clock. This clock.
may be conditioned by a Memory Ready Signal. This is
equivaJent to ~2 on the H06800.
• Vee SUndby
This pin supplies the dc voltage to the first 32 bytes of RAM
as weD as the RAM Enable (RE) control logic. Thus retention of
data in this portion of the RAM on a power up, power.down, or
standby condition is guaranteed at the range of 4.0 V to 5.25 V.
Maximum current drain at S.2SV is 8mA.
~
o
____
*
~
1=''''''''"'---1,
• MPU INSTRUCTION SET
The H06802 has a set of 72 different instructions. Included
are binary and decimal arithmetic, logical, shift, rotate, load,
store, conditional or unconditional branch, interrupt and stack.
manipulation instructions.
This instruction set is the same as that for the
6800MPU(HD6800 etc.) and is not explained again in this
data sheet.
• NOTE FOR BOARD DESIGN OF THE OSCILLATION
CIRCUIT IN HD6802
In designing the board, the following notes should be taken
when the crystal oscillator is used.
Crystal oscillator and load capacity CL must be placed near
the LSI as much as possible.
(Normal oscillation may be disturbed when external noise is]
induced to pin 38 and 39.
HD6802
Pin 38 signal line should be wired apart from pin 37 signal
line as much as possible. Don't wire them in paraJ1el, or normal
oscillation may be disturbed when E signal is feedback.ed to
XTAL.
The following deSign must be avoided.
Must be avoided
c(
!
:I
I
o
III
~
-f--......f--f------
Signal C
39
~-+-....,...--;~
38
1--+~-4---;~
A signal line or a power source line must not cross or go near
the oscillation circuit line as shown in the left figure to prevent
the induction from these lines and perform the correct
oscillation. The resistance among XTAL, EXTAL and other pins
should be over 10MO.
HD6802
Figure 17 Note for Board Design of the Oscillation Circuit
~HITACHI
324
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
HD6802
~Other
Ilgnal,ar8 not wired in thu. area .
. / E signal i, wired apart from 38 pin
'-----038
/
0=3:...7----, E
ond 39 pin.
HD6802
(Top View)
Figure 18
Example of Board Design Using the Crystal Oscillator
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
325
HD6802
• NOTE FOR THE RELATION BETWEEN WAI INSTRUCTION AND HALT OPERATION OF HD6802
When HALT input signal is asserted to "Low"
level, the MPU will be halted after the execution of
the current instruction except WAI instruction.
The "Halt" signal is not accepted after the fetch
cycle of the WAI instruction (See ® in Fig. 19). In the
case of the "WAI" instruction, the MPU enters the
"WAIT" cycle after stacking the internal registers and
outputs the "High" level on the BA line.
When an interrupt request signal is input to the
MPU, the MPU accepts the interrupt regardless the
"Halt" signal and releases the "WAIT" state and outputs the interrupt's vector address. If the "Halt" signal
is "Low" level, the MPU halts after the fetch of new
PC contents. The sequense is shown below.
WAI
Ins.ructlon
IFetch
I
E
VMA
tROor
NMr
BA
When the Interrupt occurs during the WAIT CYCLE, the MPU accepts the Interrupt even If
HAlT IS at "Low" aevel
Figure 19 HD6802 WAIT CYCLE & HALT Request
_HITACHI
326
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300
HD6802W------MPU (Microprocessor with Clock and RAM)
HD6802W is the enhanced version of HD6802 which contains MPU, clock and 256 bytes RAM. Internal RAM has been
extended from 128 to 256 bytes to increase the capacity of
system Jead/write memory for handling temporary data and
manipulating the stack.
The internal RAM is located at hex addresses ()()()() to OOFF.
The fint 32 bytes of RAM, at hex addresses ()()()() to 001 F, may
be retained in a low power mode by utilizing Vcc standby,
thus facWtating memory retention during a power-down situation_
The HD6802W is completely software compatible with the
HD6800 as well as the entire HMCS6800 family of parts. Hence,
the HD6802W is expandable to 65k words.
HD6802WP
(DP-40)
•
•
•
•
•
•
•
FEATURES
On-Chip Clock Circuit
256 x 8 Bit On-Chip RAM
32 Bytes. of RAM are Retainable
Software-Compatible with the HD6800. HD6802
Expandable to 6Sk words
Standard TTL-Compatible Inputs and Outputs
• 8 Bit Word Size
• 16 Bit Memory Addressing
• Interrupt Capability
• PIN ARRANGEMENT
V,,
RES
HALT
EXTAL
XTAL
MR
IRO
E
VMA
RE
NMI
Vee SttndbY
Rfli
8A
D,
Vee
'"
D.
D,
HD6802W
D,
• BLOCK DIAGRAM
D.
D,
D.
D,
Vcc
Vee
Vee
Au
A..
A..
Au
Vee
Standby Vee
..r-
A,,~_ _ _ _ _ _
Counterl {
Timor 1/0
1m
iRa I----t.....-~ nm
CS,
VMA
Vss
(Top View)
MR
VMA
t--"C~'OC::,k'--_ _-t E
RE
R/W
om
~~----4R~~Niij
Porollol
{
1/0
IMPUI
SA
0.-0,
XTALt--t---,
Control {
A.-A" EXTAL
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
327
HD6802W
A expanded block diagram of the HD6802W is shown in Fig.
1. As shown, the number and configuration of the registers are
the same as the HD6802 except that the internal RAM has been
extended to 256 bytes.
MR 3
E 37
~40
NMi 6
HALT 2
1mi 4
EXTAL 39
XTAL 38
8A 7
VMA 5
Rfii 34
Vee· Pins 8,35
Va· Pins 1,21
28 27
D, D.
28 29 30 31 32 33
D, D. D, D, D, D.
Figure 1 Expanded Block Diagram
Address Map of RAM is shown is Fig. 2.
The HD6802W has 256 bytes of RAM on the chip located
at hex addresses 0000 to ooFF. The first 32 bytes of RAM, at
hex addresses 0000 to 00 IF, may be retained in a low power
mode by utilizing Vee standby and setting RAM Enable Signal
"Low" level, thus facilitating memory retention during a
power·down situation.
: : _____________ } retention by Vee Standby
0020
~F~----------~
F 'gure 2 Address Map of H D6802W
~HITACHI
328
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589·8300
HD6802W
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Vcc·
Vcc Standby·
Yin·
Supply Voltage
Input Voltage
Value
Unit
-0.3-+7.0
V
V
·C
·C
Operating Temperature
Topr
-0.3-+7.0
-20-+75
Storage Temperature
TItg
-55 - +150
• With retpect to Vss (SYSTEM GNDI
(NOTEI
•
Perm_nt LSI damage may Occur if maximum ratings are exceeded. Normal operation should be under
recommended operating conditions. If these conditions are eKceeded. it could affect reliability of LSI.
RECOMMENDED OPERATING CONDITIONS
Item
Symbol
min
4.75
Vcc
V cc Standby·
V 1L
Supply Voltage
.
Input Voltage
V 1H
4.0
-0.3
2.0
• I Except R£S
Operation Temperature
I RES
Vce -0.75
-20
Topr
typ
max
Unit
5.0
5.25
V
O.B
V
25
Vce
V
Vee
75
·C
• With retpect to Vss (SYSTEM GNDI
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee-5.OV±5%. Vee Standby-5.0V±5%. VSS-oV. Ta--2G-+75·C. unless otherwise noted.1
Symbol
Item
Input "High" Voltage
Input "Low" Voltage
Except RES
V1H
..
RES
Except RES
Ao-A IS • R/W, VMA
BA
Output "Low" Voltage
Three State (Off Statel Input Current
Input Leakage Current
Power Dissipation
Input Capacitance
Output Capacitance
VOH
VOL
0 0 -0,.
ITSI
Except 0 0 -0 7
lin •••
min
2.0
typO
max
-
Vec
Vcc-O.75
-
-0.3
-
-0.3
2.4
-
Vee
O.B
O.B
-
-
2.4
-
-
IOH = -100jtA
2.4
-
IOL = 1.6mA
Yin = 0.4-2.4V
Vin - Q-5.25V
-10
-2.5
-
V1L
RES
00-0 7 , E
Output "High" Voltage
Test Condition
IOH = -205j.lA
IOH = -145jtA
-
Po ••• *
0 0 -0 7
Except 0 0 -0 7
Ao-A IS , R/W, BA,
VMA
Gn
Vin=OV, T.=25·C,
f=I.0MHz
c"u,
Vin=OV, T.=25·C.
f=I.0MHz
·T.~C, voc·5V
•• AI'FiEI input bas hllteresis character, applied voltage up to 2.4V is regarded as "Low" level when it goes up from
••• Does not includa EXTAL and XTAL, which are crystal inputs•
•••• In power-down mode, maximum pOwer diuipation is less than 42mW•
•
-
0.7
10
6.5
-
0.4
10
2.5
1.2
12.5
10
12
Unit
V
V
V
V
jtA
jtA
W
pF
pF
av.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
329
HD6802W
• AC CHARACTERISTICS (Vee=5.0V±5%, Vee Standby:'5.0V±5%, Vss=OV, Ta=-20-+75d C, unless otherwise noted.)
1. CLOCK TIMING CHARACTERISTICS
I Input Clock .;- 4
Frequency of Operation
Test Condition
Symbol
Item
f
l Crystal Frequency
Cycle Time
"Low" Level
typ
max
-
1.0
1.0
fXTA!:_ '---Fig. 4, Fig. 5
f---lcvc
at 2.4V(Fig. 4, Fig. 5)
l~~"Lev~= I---~H~_
Clock Pulse Width
min
0.1
1.0
10
-~-~
-
450
PWL
'atO.4V (Fig. 4, Fig. 5)
tq,
'D.4V - 2.4V(Fig.4,Fig.5)
-
MHz
IlS
j------
ns
4500
----
t-----
~-----"-
Clock Fall Time
4.0
Unit
ns
25
2. READ/WRITE TIMING
Item
min
typO
max
Unit
-
270
ns
-
ns
100
-
ns
Fig.4
10
-
-
ns
Flg.5
20
-
ns
-
-
-
ns
-
225
ns
-
-
250
ns
200
-
-
ns
100
ns
max
Unit
Symbol
Test Condition
Address Delay
tAD
Fig. 4, Fig. 5, Fig. 8
Peripheral Read Access Time
tace
Fig.4
530
Data Setup Time (Read)
tOSR
Fig.4
Input Data Hold Time
tH
Output Data Hold Time
tH
Address Hold Time (Address, R/W, VMA)
tAH
Fig. 4, Fig. 5
10
Data Oelev Time (Write)
toow
Fig. 5
-
Bus Available Delay
Processor Controls
Processor Control Satup Time
Processor Control Rise and Fall Time
(Measured at O.BV and 2.0V)
tSA
Fig. 6, Fig. 7, Fig. 9, Fig. 10
tpcs
Fig. 6 - Fig. 9, Fig. 11
tpcr,
Fig. 6 - Fig. 9, Fig. II, Fig. 12,
Fig. 14
tpCI
-
3. POWER DOWN SEQUENCE TIMING, POWER UP RESET TIMING AND MEMORY READY TIMING
Symbol
min
typ
RAM Enable Reset Time (1)
tRE'
Fig. 12
150
-
RAM Enable Reset Time (2)
tRE2
Fig. 12
E·3 cycles
-
Item
Reset Release Time
tLRES
RAM Enable Reset Time (3)
tRE3
Memory Ready Setup Time
tSMR
Test Condition
-
Fig. 11
20
Fig. 11
0
Fig. 14
300
~.------.--
Memory Ready Hold Time
tHMR
Fig. 14
0
-
~-
_-.
-
200
~HITACHI
330
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
ns
ms
ns
ns
ns
-
HD6802W
5.0V
R L • 2.4kll
Test POint o---f""-t~--foIIII--+
C· 130pF for D. -0,. E
• 90pF for A. -Au,
= 30pF for BA
c
RtW, and VMA
f{. 11 kll for O. -0"
E _
• 16kll for A. -A", R/W, and VMA
R
= 24kll for BA
C Includes stray Capac~nce.
All dIode. are 1S2074(tj)or equivalent.
Figure 3 Bus Timing Test Load
E
RtW
Address
FromMPU
VMA
Dat8
From Memory
or Peripherals
2.0V
O.BV
~ O.ta Not Valid
Figure 4 Read Data from Memory or Peripherals
~-------------------~vc--------------------~
E
RtW
Address
From MPU
VMA
D....
From MPU
~
O.... NotV.hd
Figure 5 Write Data in Memory or Peripherals
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
331
HD6802W
The Last Instruction Cycle
HALT Cycle
+
E
BA
Figure 6 Timing of HALT and BA
+
HALT Cycle
/
I nstruction Cycle
-'
04V
20V
HALT
-,
tpcr
OBV
Ipcs
IBA
\
BA
o 4V
Figure 7 Timing of HALT and BA
MPU Reslart Sequenca
MPU Resol
r------.i
E
VMA
2.4V
04V
2.4V
Figure B RES and MPU Restart Sequence
~HITACHI
332
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6802W
WAIT Cycle or
The Last Instruction Cycle
., ..
/
24V
1\
Interrupt Sequence
jf--
ri~V
OSV
IRQ, NM I
tpc,
I. tpcs
~
-- - - - -- - ------ -- -- -- - -- - - - - - - - IWhen WAIT Cycle)
--"\
SA
\
~O.4V
Figure 9 IRO and NMI Interrupt Timing
The last execution cycle of
""""'+
WAI instructIon ,.1#9_1_ _ _ _
WAIT Cycle
2.4V
SA
Figure 10 WAI Instruction and SA Timing
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
333
HD6802W
•
HD6802W MPU SIGNAL DESCRIPTION
•
Address Bus (Ao - A 15 I
Sixteen pins are used for the address bus. The outputs are
capable of driving one standard TTL load and 90pF.
• Data Bus (Do - 0 7 1
Eight pins are used for the data bus. It is bidirectional,
transferring data to and from the memory and peripheral
devices. It also has three-state ou tpu t buffers capable of driving
one standard TTL load and 130pF.
Data Bus will be in the output mode when the internal RAM
is accessed. This prohibits external data entering the MPU. It
should be noted that the internal RAM is fully decoded from
$0000 to $OOFF. External RAM at $0000 to SOOFF must be
disabled when internal RAM is accessed.
• HALT
When this input is in the "Low" state, all activity in the
machine will be halted: This input is level sensitive.
In the halt mode, the machine will stop at the end of an
instruction. Bus Available will be at a "High" state. Valid
Memory Address will be at a "Low" state. The address bus will
display the address of the next instruction.
To insure single instruction operation, transition of the
HALT line must not occur during the last tpcs of E and the
HALT line must go "High" for one Clock cycle.
HALT should be tied "High" if not used. This is good
engineering design practice in general and necessary to insure
proper operation of the part.
•
ReadlWrite (R/WI
This TTL compatible output signals the peripherals and
memory devices whether the MPU is in a Read ("High") or
Write ("Low") state. The normal standby state of this signal is
Read ("High"). When the processor is halted, it will be in the
logical one state ("High").
This output is capable of driving one standard TTL load and
9OpF.
•
Valid Memory Address (VMAI
This output indicates to peripheral devices that there is a
valid address on the address bus. In normal operation, this signal
should be utilized for enabling peripheral interfaces such as the
PIA and ACIA. This signal is not three-state. One standard TTL
load and 90pF may be directly driven by this active high signal.
•
Bus Available (BAI
The Bus Available signal will normally be in the "Low" state.
When activated, it will go to the "High" state indicating that the
microprocessor has stopped and that the address bus is available
(but not in a three-state condition). This will occur if the HALT
line is in the "Low" state or the processor is in the wait state
as a result of the execution of a WAI instruction. At such time,
all three-state output drivers will go to their off slate and other
outputs to their normally inactive level.
The processor is removed from the wait state by the
occurrence of a maskable (mask bit 1=0) or nonmaskable
interrupt. This output is capable of driving one standard TTL
load and 30pF.
•
I nterrupt Request (I Ral
This level sensitive input requests that an interrupt sequence
be generated within the machine. The processor will wait, until
it completes the current instruction that is being executed
before it recognizes the request. At that time, if the interrupt
mask bit in the Condition Code Register is not set, the machine
will begin an interrupt sequence. The index Register, Program
Counter, Accumulators, and Condition Code Register are stored
away on the stack. Next the MPU will respond to the interrupt
request by setting the interrupt mask bit high so that no further
interrupts may occur. At the end of the cycle, a 16-bit address
will be loaded that points to a vectoring address which is located
in memory locations FFF8 and FFF9. An address loaded at
these locations causes the MPU to branch to an interrupt
routine in memory.
The HALT line must be in the "High" state for interrupts to
be serviced. Interrupts will be latched internally while HALT is
"Low".
A 3H! external register to Vee should be used for wire-OR
and optimum control of interrupts.
•
Reset (RESI
This input is used to reset and start the MPU from a
power-down condition, resulting from a power failure or an
initial start-up of the processor. When this line is "Low", the
MPU is inactive and the information in the registers will be lost.
If a "High" level is detected on the input, this will signal the
MPU to begin the restart sequence. This will start execution of a
routine to initialize the processor from its reset condition. All
the higher order address lines will be forced "High". For the
restart, the last two(FFFE, FFFF) locations in memory will be
used to load the program that is addressed by the program
counter. During the reslart routine, the interrupt mask bit is set
and must be reset before the MPU can be interrupted by IRQ.
Power-up and reset timing and power-down sequences are
shown in Fig. II and Fig. 12 respectively.
• Non-Maskable Interrupt (NMn
A low-going edge on this input requests that a non-maskinter!':!£!.. sequence be generated within the processor. As with
the IRQ signal, the processor will complete the current
instruction that is being executed before it recognizes the NMI
signal. The interrupt mask bit in the Condition Code Register
has no effeet on NMI.
The Index Register, Program Counter, Accumulators, and
Condition Code Register are stored away on the stack. At the
end of the cycle, a 16-bit address will be loaded that points to a
vectoring address which is located in memory locations FFFC
and FFFD. An address loaded at these locations causes the
MPU to branch to a non-maskable interrupt routine in memory.
A 3kn external resistor to Vee should be used for wire-OR
and optimum control of interrupts.
Inputs IRQ and liIMI are hardware interrupt lines that are
sampled when E is "High" and will start the interrupt routine
on a "Low" E following the completion of an instruction. IRQ
and NMI should be tied "High" if not used. This is good engineering design practice in general and necessary to insure
proper operation of the part. Fig. 13 is a flowchart describing
the major decision paths and interrupt vectors of the microprocessor. Table I gives the memory map for interrupt vectors.
~HITACHI
334
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6802W
Vee
E
I--tpes
>Vcc-O·75V
l ___ _
....,..,_..,.-,=-"Ii!+ __ __________
r_t_L_A_ES
_ _ _ _ _ _ _ _ _ _-iI-_ _
OptIon 1
(See Note belowl
tLAES~__---------~f----------~~
OptIon 2
RE
VMA
R
See Figure 12 for
Power Down condition
2.0V
____________~Q~8~
tPCr
01--------..\
____-..J/
(NOTEI
'---------
If option 1 is chosen. RES and RE pins can be tied together.
figure 11 Power-up and Reset Timing
Vee
E
RE
figure 12 Power-down Sequence
figure 13 MPU flow Chart
$HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
335
HD6802W
Conditions for Crystal (4 MHz)
• AT Cu t Parallel resonant
• Co =7 pF max.
• R. = 80n max.
Table 1 Memory Map for Interrupt Vectors
Vector
MS
FFFE
FFFC
FFFA
FFFB
LS
FFFF
FFFD
FFFB
FFF9
Description
Restart
Non·Maskable Interrupt
Software Interrupt
Interrupt Request
(RES)
(N MI)
(SWI)
(iRQ)
• RAM Enable (RE)
A TTL·compatible RAM enable input controls the on-chip
RAM of the HD6802W. When placed in the "High" state, the
on.chip memory is enabled to respond to the MPU controls. In
the "Low" state, RAM is disabled. This pin may also be utilized
to disable reading and writing the on-chip RAM during a
power-down situation. RAM enable must be "Low" three cycles
before Vee goes below 4.75V during power-down.
RE should be tied to the correct "High" or "Low" state if
not used. This is good engineering design practice in general and
necessary to insure proper operation of the part .
• EXTAL and XTAL
The HD6802W has an internal oscillator that may be crystal
controlled. These connections are for a parallel resonant
fundamental crystal (AT cut). A divide-by· four circuit has been
added to the HD6802W so that a 4MHz crystal may be used in
lieu of a IMHz crystal for a more cost·effective system. Pin39 of
the HD6802W may be driven externally by a TTL input signal if
a separate clock is required. Pin38 is to be left open in this
mode.
An RC network is not directly usable as a frequency source
on pins 38 and 39. An RC network type TTL or CMOS
oscillator will work well as long as the TTL or CMOS output
drives the HD6802W.
If an external clock is used, it may not be halted for more
than 4.5/lS. The HD6802W is a dynamic part except for the
internal RAM, and requires the external clock to retain
information.
c.
Crystal Equivalent Circuit
Recommended Oscillator (4MHz)
39 pin
D--------t---,
HD6802W
38 pm
rl-----------.
c, " C, = 22pF ± 20%
When using the crystal, see the note for Board Design of the
Oscillation Circuit in HD6802W.
• Memory Ready (MRI
MR is a TTL compatible input control signal which allows
stretching of E. When MR is "High", E will be in normal
operation. When MR is "Low", E may be stretched integral
multiples of half periods, thus allowing interface to slow
memories. Memory Ready timing is shown in Fig. 14.
MR should be tied "High" if not used. This is good
engineering design practice in general and necessary to insure
proper operation of the part. A maximum stretch is 4.5I1 S•
~0.4V
2.4V
E
~tSMR
tpCf
I
tPCr
MR
Figure 14 Memory Ready Control Function
~HITACHI
336
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
HD6802W
•
• MPU INSTRUCTION SET
Enable (E)
This pin supplies the clock for the MPU and the rest of the
system. This is a single phase, TTL compatible clock. This clock
may be conditioned by a Memory Ready Signal. This is
equivalent to <1>2 on the HD6800 .
• Vee Standby
This pin supplies the dc voltage to the first 32 bytes of RAM
as well as the RAM Enable (RE) control logic. Thus retention of
data in this portion of the RAM on a power-up, power.down, or
standby condition is guaranteed at the range of 4.0 V to 5.25 V.
Maximum current drain at 5.25V is 8mA.
_______
o
~
~
39
F"-...----i,
7h
The HD6802W has a set of 72 different instructions.
Included are binary and decimal arithmetic, logical, shift, rotate,
load, store, conditional or unconditional branch, interrupt and
stack manipulation instructions.
This instruction set is the same as that for the
6800MPU (HD6800 etc.) and is not explained again in this
data sheet.
• NOTE FOR BOARD DESIGN OF THE OSCILLATION
CIRCUIT IN HD6802W
In designing the board, the following notes should be taken
when the crystal oscillator is used.
Crystal oscillator and load capacity CL must be placed near
the LSI as much as possible.
[Normal oscillation may be disturbed when external noise is]
induced to pin 38 and 39.
38
HD6802W
37
Pin 38 signal line should be wired apart from pin 37 signal
line as much as possible. Don't wire them in parallel, or normal
oscillation may be disturbed when E signal is feedbacked to
XTAL.
The following design must be avoided.
Must be aVOided
i~ 0\
o
-+---+-+----- Signal C
39
I---'--+-~--t~
38
r-+-<------I~
A signal line or a power source line must not cross or go near
the oscillation circuit line as shown in the left figure to prevent
the induction from these lines and perform the correct
oscillation. The resistance among XTAL, EXT AL and other pins
should be over 10Mn.
HD6802W
Figure 15 Note for Board Design of the Oscillation Circuit
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
337
HD6802W
~Other
signals are not wired in this area.
. / E signal is wired apart from 38 pin
/'
ond 39 pin.
Q-""----'e
HD6802W
(Top View)
Figure 16 Example of Board Design Using the Crvstal Oscillator
~HITACHI
338
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6802W
•
NOTE FOR THE RELATION BETWEEN WAI INSTRUCTION AND HALT OPERATION OF HD6802W
When HALT input signal is asserted to "Low"
level, the MPU will be halted after the execution of
the current instruction except WAI instruction.
The "Halt" signal is not accepted after the fetch
cycle of the WAI instruction (See
R;W
AS
A.
A.
I - - - - P..
A..
A..
Au
A..
A..
A..
~
P"
P..
P..
P..
P..
p ..
PH
•
TYPE OF PRODUCTS
Type No.
Bus Timing
HD6803
1.0MHz
H 06803· 1
1.25MHz
Vrx Standby
~HITACHI
340
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
HD6803, HD6803-1
• ABSOLUTE MAXIMUM RATINGS
Item
..
Symbol
Value
Supply Voltage
Input Voltage
Vee
Operating Temperature
Storage Temperature
T OI>r
-0.3-+7.0
-0.3-+7.0
0 -+70
-55-+150
•
Vi"
T...
Unit
V
V
C
·C
W,th respect to vSS ISYSTEM GNDI
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating
conditions. If these conditions are exceeded. it could affect reliabilitY of LSI.
•
ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vee -5.0V±5%. Vss - OV. Ta - D-+70·C. unl... oth.rwi. noted.)
Item
Input "High" Voh_ge
Symbol
m
Other Inputs'
V'H
Input "Low" Voltage
All Inputs'
Input Load Current
Input Leakage Current
Three State (Offset)
Leakage Current
EXTAL
V'L
Ilinl
Output "High" Voltage
NMI. IRQ. RES
P,O - P17 • Do/Au- D,/A,
P:w - P14
Do/Au - D,/A,
A., - ~IS. E. RIW. AS
Other Outputs
All Outputs
Output "Low" Voltage
Darlington Drive Current P,O
Power Dissipation
Input Capacitance
Vee Standby
Standby Current
-
P 17
Do/A. - D,/A,
Other Inputs
Powerdown
Operating
Powerdown
11",1
IITS'!
Test Condition
V,n = 0- Vee
Von = 0-5.25V
Vin = 0.5 - 2.4V
ILOAD = -205 p.A
VOH
VOL
-loH
Po
C'n
ILOAD
ILOAD
ILOAD
Vout =
= -145 p.A
= -100 p.A
= 1.6 mA
1.5V
V,n = OV. Ta = 25 C.
f= 1.0MHz
typ
4.0
2.0
-
-0.3
-
-
-
-
-
-
-
2.4
2.4
2.4
-
VSB
VSBB = 4.0V
max
Unit
Vee
Vee
V
OB
0.8
2.5
10
100
0.5
10.0
1200
V
mA
mW
-
-
-
12.5
10.0
5.25
-
5.25
8.0
-
-
p.A
V
-
-
p.A
-
-
-
V
mA
-
1.0
4.0
4.75
VSBB
ISBB
min
pF
V
mA
eEJCcept Mode Programming Levels.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
341
HD6803, HD6803-1
• AC CHARACTERISTICS
BUS TIMING (Vee· 5.0V :I: 5%, Vas· OV, T.· 0 - +70o C, unl... otherwise notedJ
Symbol
Item
Test
Condition
min
Cycle Time
t;,yc
Address Strobe Pulse Width "High" •
PWASH
Address Strobe Rise Time
tASr
5
Address Strobe Fall Time
Address Strobe Delay Time •
tAS!
tASO
60
Enable Rise Time
tEr
tEf
Enable Fall Time
Enable Pulse Width "High" Time •
1
Address Strobe to Enable Delay Time •
tASeo
tAD
tAOL
Data Set-up Read Time
I
I
Read
Write
Address Set-up Time for Latch •
Address Hold Time for Latch
Address Hold Time
Data Hold Time
Peripheral Read Access Time (Multiplexed Bus)'
Oscillator stabilization Time
Processor Control Set-up Time
5
450
450
PWEH
PWEL
Data Set-up Write Time
200
5
5
Enable Pulse Width "Low" Time •
Address Delay Time
Address Delay Time for Latch •
H06803
typ
max
Fig. 1
-
tosw
tOSR
tHR
tHW
tASL
tAHL
tAH
ItACCM)
tRC
tpcs
60
Fig. 8
-
10
-
min
0.8
150
-
5
350
-
30
-
50
50
-
-
50
-
50
-
-
-
-
-
260
270
5
30
5
5
340
-
225
80
10
20
-
60
20
20
-
-
-
-
-
-
(600)
-
-
100
-
200
100
Fig. 7,8 200
-
H06803-1
typ
max
115
70
10
20
50
20
20
-
10
-
-
50
50
50
-
-
/.IS
ns
ns
ns
ns
50
ns
ns
-
ns
-
-
ns
ns
260
260
ns
ns
-
ns
ns
ns
ns
ns
-
ns
ns
ms
-
ns
(420)
-
Unit
·The.. timings change in approximate proportion to tcyc. The figures in this characteristics represent those when tcyc is minimum
(- in the high..t speed ope ..tion).
PERIPHERAL PORT TIMING (Vee· B.OV :I: 5%, Vss· OV, T.· 0 - +70·C, unle.. otherwise rIOtedJ
Item
Peripheral Data Setup Time
Peripheral Data Hold Time
Oelav Time, Enable Negative
Transition to Peripheral Data
Valid
• Except P21
Symbol
Port 1,2
Port 1,2
tposu
tpOH
Port 1,2'
t pwo
min
typ
max
-
Fig. 2
200
200
-
-
Fig. 3
-
-
400
Test Condition
Fig.2
Unit
ns
ns
ns
eHITACHI
342
Hitachi America, Ltd. • Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6803 , HD6803-1
TIMER. SCI TIMING (Vee· s.ov
is"'. Vss· OV. TI· 0 -
Item
Timer Input Pulse Width
Symbol
Test Condition
tpWT
Delay Time. Enable Positive Transition to
Timer Out
MODE PROGRAMMING (Vee· S.OV
is"'. VSS· OV. T. -
RES "Low" Pulse Width
max
-
-
ns
-
600
ns
-
1
0.4
Unit
-
0.6
toye
tSeye
0 - +70·C. unl... otherwise noted.1
min
typ
miX
Unit
V MPL
-
1.7
V
VMPH
PW ASTL
4.0
3.0
-
-
V
teye
teye
Test Condition
Symbol
Item
Mode Programming Input "Low" Voltage
Mode Programming Input "High" Voltage
tvP
-
Fig.4
tSeve
tpWSCK
SCI Input Clock Pulse Width
min
2teve+200
tTOO
SCI Input Clock Cycle
Mode Programming Set·up Time
Mode Programming
Hold Time
+70·C. unless otherwise noted.!
FIg. 6
tMPS
2.0
tMPH
0
100
l An Rise Time~ lj.1s
I m Rise Time < l}1s
-
-
-
ns
leve
2.2V
Addr ... Strobe
!--PWASH-
IASI
V
-
oev
....
....
i--IAS.
tASO
1\
io-lASf
I-
l-
ASEC
!-
V'
En,ble
lEI
O.5~
--
I---tAO-
R/W
~
A,-A ..
Do/A" - D,/A,
IPutt 3)
- 1\
-
...
1- 1£.
Olf/Ao-D7/Ai
(Pori 31
I-tAH
- t 0 6 W - 1-
t-tHW
Addresa V,lId
oev
)
fo-
'-
~tAHL
22V
22V
Add,",
V,hd
~
-
/
to-I£f
I'"
I{
oev
,
0.,. V,ltd
j-tCSA-
22V
Address
V,lId
oev
I(
I\.
~
oev
i--tAOL-
MPU Rood
1\
22V
tASL ....
MPUW'lte
PWEH
1/
PWH
,
....
i-tHR
20V
o.t. V,hd
O.8V
If
ItACCMI-
Figure 1 Expanded Multiplexed Bus Timing
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
343
HD6803, HD6803-1
r
r-MPURead
Enable (E)
2,4V
MPUWro,.
Enable (E)
O,SV
O'SV't-:'PWOX'1.--"':2:":,Om
V .Jro--"""'!!il..L'r~---
p .. - P"
P,. - P,.
..;O:.;8~Vr.T~
9:.
AU 0 1 1 : 2 2V
Por' OU'PUII _ _ _ _ _ _ _ _
V Oa'a Valid
____~~=';;""_ _ _ __
• Not appl icable to P u
Figure 2 Data Set-up and Hold Times
(MPU Read)
Figure 3 Port Data Delay Timing
(MPU Write)
Enable (E)
'-___
Timer
Cou"'.r _ _ _ _..J
'-_~==...J
P"
Output
Figure 5 Mode Programming Timing
Figure 4 Timer Output Timing
m
Vee
RL ' 2 '2kO
Test POint
152014 i!:!'
or EQUI"
C
c
•
R ..
R
90 pF for ColAo -.. 07/A" As"" AlS, E. AS, RtrN
30 pF for PIO - P17. PlO - P14
12 kS'l for Do/Ao -.. D,/A'I. As -.. AIS. E. AS, RIW
24 kn for Pm"'" P17. PXl - P14
TTL Load
Figure 6 Bus Timing Test Load
•
344
HITACHI
Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6803, HD6803-1
l•• '''''''''''00.
--1
E.,.ble (EI
InMr,*
A~~8~~---+~--~~~~
__
-'~~~
__
~~
__
~~--~
__-J'-__ ____ __
~
~
-r~
__ __
~
-'~
__ ____
~
NI"'\/r---V--,,..---V----v----v----V--,,..---'V----v---,,--V----'V----,,,---'V----v--
Inl...
O•• e
.......J......,.......,JI.".--.I\.,.....-..J\p.......J\_-
au. -"'----"'----".,,""..,eo.=A,O-•. ,.CO-..~PCO_='~PC-I..7""'C8,..-"'PC,.,...!'-•.,..o--•.,. 7""."'8-..,X""5"....,.,
.. =J\-----~
~___________________________________- - J
In.er.... Rlii - - - - - - - - - - - - - - . ,
.~: ,Inte'nlllnt.rrupt
E.Ib','EI
Figure 7 Interrupt Sequence
$\~\\\\\\\\\\\\\\ ~\\\\~\\\\\\~ ~ ~ [1JlJ1S"
-5.25V
't-l------------11 ,
~ .
" ~
V~ ~~-.-.75-V---------__- - - -__--I~
~
lID -------------tl '"I- - - - - - - - - - - - - - - -.....,
~ ~
~•.bV '...
·,~~-O.I~v~...---------
Figure 8 Reset Timing
Nomin.1 Crvstll ',r.m.ter
• SIGNAL DESCRIPTIONS
•
rvltol
Vee and VSS
These tWQ pins are used to supply power and ground to the
chip. The voltage supplied will be +5 volts ±5%.
• XTAL and EXTAL
These connections are for a parallel resonant fundamental
crystal, AT cut. Devide·by4 circuitry is included with the
internal clock, so a 4 MHz crystal may be used to run the
system at I MHz. The devide·by4 circuitry allows for use of the
inexpensive 3.58 MHz Color TV crystal for non·time critical
applications. Two 22pF capacitors are needed from the two
crystal pins to ground to insure reliable operation. An example
of the crystal interface is shown in Fig. 9. EXT AL may be
driven by an external TTL compatible source with a 45% to
55% duty cycle. It will devided by 4 any frequency less than
or equal to 5 MHz. XTAL must be grounded if an external
clock is used.
Item
Co
4 MHz
5 MHz
7pF mi'. 4.7pF mi •.
80n mi'. 30n typo
XTALr---.------,
CJ
EXTAl
t--_.,
C Ll
•
C L2 ' 22pF .20%
~3.2
- 5 MHzl
(NOTEI AT cut plrollol
relonance perlmlt.rs
tL2~CLt
Figure 9 Crystal Interface
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
345
HD6803, HD6803-1
• vee Sundby
E following the completion of an instruction.
chip. The first 64 bytes of RAM will be maintained in the power
down mode with 8 rnA current max. The circuit of figure 13
can be utilized to assure that Vee Standby does not go below
VSBB during power down.
To retain information in the RAM during power down the
following procedure is necessary:
I) Write "0" into the RAM enable bit, RAME. RAME is bit
6 of the RAM Control Register at location $0014. This
disables the standby RAM, thereby protecting it at power
down.
2) Keep Vee Standby greater than VSBB.
•
This pin will supply +s volts ±S% to the standby RAM on the
Vee Standby
TPowerLin8
l
Figure 10 Battery Backup for Vee Standby
• R... IRESI
This input is used to reset and start the MPU from a power
down condition, resulting from a power failure or an initial
startup of the processor. On power up, the reset must be held
"Low" for at least 100 ms. When reset during operation, RES
must be held "Low" at least 3 clock cycles.
When a "High" level is detected, the CPU does the follow.
ing;
I) All the higher order address lines will be forced "High".
2) I/O Port 2 bits, 2, I, and 0 are latched into programmed
control bits PC2, PC I and PCO.
3) The last two ($FFFE, $FFFF) locations in memory will
be used to load the program addressed by the program
counter.
4) The interrupt mask bit is set. Clear before the CPU can
recognize maskable interrupts.
• Enable IE)
This supplies the external clock for the rest of the system
when the internal oscillator is used. It is a single phase, TTL
compatible clock, and will be the divide- by-4 result of the
crystal oscillator frequency. It will drive one TTL load and 90
pF capacitance.
•
Non-Maskeble Interrupt (NMI)
When the falling edge of the input signal is detected at this
pin, the CPU begins non-maskable interrupt sequence internally.
As with interrupt Request signal, the processor will complete
the current instruction that is being executed before it recognizes
the NMI signal. The interrupt mask bit in the Condition Code
Register has no effect on liIm.
In response to an NMI interrupt, the Index Register, Program
Counter, Accumulators, and Condition Code Register are stored
on the stack. At the end of the sequence, a 16-bit address will
be loaded that points to a vectoring address located in memory
locations $FFFC and $FFFD. An address loaded at these loca·
tions causes the CPU to branch to a non-maskable interrupt
service routine in memory.
A 3.3 kO external resistor to Vee should be used for
wire-OR and optimum control of interrupts.
Inputs lRQ, and NMI are hardware interrupt lines that are
sampled during E and will start the interrupt routine on the
Interrupt Request (IRQ,)
This level sensitive input requests that an interrupt sequence
be generated within the machine. The processor will complete
the current instruction before it recognizes the request. At
that time, if the interrupt mask bit in the Condition Code
Register is not set, the machine will begin an interrupt sequence. The Index Register, Program Counter, Accumulators,
and Condition Code Register are stored on the stack. Next the
CPU will respond to the interrupt request by setting the interrupt mask bit "High" so that no further maskable interrupts
may occur. At the end of the cycle, a 16-bit address will be
loaded that points to a vectoring address which is located
in memory locations $FFF8 and $FFF9. An address loaded
at these locations causes the CPU to branch to an interrupt
routine in memory.
The IRQ, requires a 3.3 kO external resistor to Vee which
should be used for wire-OR and optimum control of inte!!.!!pts.
Internal Interrupts will use an internal interrupt line (IRQ2)'
This interrupt will operate the same as IRQ, except that it will
use the vector address of $FFFO through $FFF7. i'RQ"; will
have priority to IRQ2 if both occur at the same time. iThe
Interrupt Mask Bit in the condition code register masks both
interrupts (See Table 1).
Table 1 Interrupt Vector Location
Highest
Priority
Lowest
Priority
Vector
MSB
LSB
FFFE
FFFF
FFFC
FFFD
FFFA
FFFB
FFF8
FFF9
FFF6
FFF7
FFF5
FFF4
FFF2
FFF3
FFFO
FFFI
Interrupt
m
NMI
Software Interrupt
(SWil
iRlr,
ICF (Input Capture I
OeF (Output Compare I
TOF (Timer Overflowl
SCI (RDRF + ORFE + TORE I
• Reld/Write (RMI
This TTL compatible output signals the peripherals and
memory devices whether the CPU is in a Read ("High") or a
Write ("Low") state. The normal standby state of this signal is
Read ("High"). This output can drive one TTL load and 90pF
capacitance.
• Address Strobe lAS I
In the expanded multiplexed mode of operation, address
strobe is output on this pin. This signal is used to latch the 8
LSB's of address which are multiplexed with data on Do / Ao
to 0 7/ A7. An 8-bit latch is utilized in conjunction with Address
Strobe, as shown in figure 11. So Do/Ao to D7/A7 can become
data bus during the E pulse. The timing for this signal is shown
in Figure I of Bus Timing. This signal is also used to disable the
address from the multiplexed blls allOwing a deselect time, tASD
before the data is enabled to the bus.
• PORTS
There are two I/O ports on the H06803 MPU; one 8-bit
port and one 5·bit port. Each port has an associated write
.HITACHI
346
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6803, HD6803-1
only Data Direction Register which allows each I/O line to be
progranuned to act as an input or an output'. A "I" in the
corresponding Data Direction Register bit will cause that I/O
line to be an output. A "0" in the corresponding Data Direction
Register bit will cause that I/O line to be an input. There are
two ports: Port I, Port 2. Their addresses and the addresses of
their Data Direction registers are given in Table 2.
* The only exceptIon
IS
state when used as an input. In order to be read properly, the
voltage on the input lines must be greater than 2.0 V for a
logic "I" and less than 0.8 V for a logic "0". As outputs, this
port has no internal pullup reSistors but will drive TTL inputs
directly. For driving CMOS inputs, external pullup resistors are
reqUired. After reset, the I/O lines are configured as inputs.
Three pins on Port 2 (pin 8, 9 and 10 of the chip) are requested
to set following values (Table 3) during reset. The values of
above three pins during reset are latched into the three MSBs
(Bit 5,6 and 7) of Port 2 which are read only.
Port 2 can be configured as I/O and provides access to the
Serial Communications Interface and the Timer. Bit I is the
only pin restricted to data input or Timer output.
bit 1 of Port 2. which can either be data
Input or Tuner output
Table 2 Port and Data Direction RegIster Addresses
Ports
Data Direction
Register Address
Port Address
I/O Port 1
I/O Port 2
$0002
$0003
$0000
Table 3 The Values of three pins
$0001
• I/O Port 1
This is an 8-bit port whose individual bits may be defined as
inputs or outputs by the corresponding bit in its data direction
register. The 8 output buffers have three-state capability,
allowing them to enter a high impedance state when the
peripheral data lines are used as inputs. In order to be read
properly, the voltage on the input lines must be greater than 2.0
V for a logIC "I'" and less than 0.8 V for a logic "0'". As outputs,
these lines are TTL compatible and may also be used as a source
of up to I rnA at 1.5 V to directly drive a Darlington base. After
reset, the I/O lines are configured as inputs.
[NOTES)
AS
.
.
.
9
H
,0
L
L
L; Logical ''0''
H; LogIcal •• ,"
• BUS
• Address Lines (As - A IS I
Each line is TTL compatible and can drive one TTL load and
90 pF. After reset, these pins become output for upper order
address lines (As to AlS).
•
INTERRUPT FLOWCHART
The In terrupt flowchart is depicted in Figure 16 and is common to every interrupt excluding reset.
-l
G OC
D,
Value
• Data/Address Lines (Do/Ao - D,/A,I
Since the data bus is multiplexed with the lower order
address bus in Data/ Address, latches are required to latch those
address bits. The 74LS373 Transparent Octal D-type latch can
be used with the H06803 to latch the least Significant address
byte. Figure II shows how to connect the latch to the H06803 .
The output control to the 74LS373 may be cOMected to
ground.
• I/O Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have
three-state capability, allowing them to enter a high impedance
GND
Pin Number
S
a,
}
74LS373
_~.A.-A,
Function Table
OutPUt
D,
a,
}
Enable
Output
Control
G
0
0
L
L
L
H
H
H
L
H
L
H
L
X
o.
X
X
Z
0". 0. -0,
..
F,gure 11 Latch Connection
$
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
347
HD6803, HD6803-1
• MEMORY MAP
The MPU can provide up to 65k byte address space. A
memory map is shown in Figure 12. The first 32 locations are
reserved for the MPU's internal register area, as shown in Table
4 with exceptions as indicated.
Table 4 Internal Register Area
Port
Port
Port
Port
1 Dlta
2 Data
1 Data
2 Oat.
Not
Not
Not
Not
Used
Used
Used
Used
Register
Direction Regilt .. - ..
Direction Register··
Register
Register
Addr...
00
01
02
03
04'
OS'
06'
07'
Timer Control and Status Register
Count.r tHigh Byte)
Counter t Low Byte)
Output Compere Register (High Byte)
08
09
Output Compere Register (Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Not Used
OC
00
OE
OF'
Rate and Mode Control RegISter
Transmit/Receive Control and Status Register
Receive Data Register
Transmit Data Register
10
11
12
13
RAM Control RegISter
Reserved
OA
OB
14
IS·1F
.. External Address
•• 1; OutpUt, 0; Input
Multiplexed/RAM
$0000
Internal Registers
s00IF
External Memory Space
$OOBO
Internal RAM
SOOFF
External Memory Space
• PROGRAMMABLE TIMER
The HD6803 contains an on-chip 16·bit programmable timer
which may be used to measure an input waveform while inde·
pendently generating an output waveform. Pulse widths for
both input and output signals may vary from a few microseconds to many seconds. The timer hardware consists of
an 8·bit control and status register,
• a 16-bit free running counter,
• a l6-bit output compare register,
• a 16-bit input capture register
A block diagram of the timer registers is shown in Figure 13.
• Fr" Running Counter ($0009:$OOOA1
The key element in the programmable timer is a 16·bit free
rUnning counter which is driven to increasing values by E (En.
able). The counter value may be read by the CPU software at
any time. The counter is cleared to zero by reset and may be
considered a read.only register with one exception. Any CPU
write to the counter's address ($09) will always result in preset
value of $FFF8 being loaded into the counter regardless of the
value involved in the write. This preset figure is intended for
testing operation of the part, but may be of value in some
applications.
• Output Compare Register (SOOOB:$OOOC1
The Output Compare Register is a 16·bit read/write register
which is used to control an output waveform. The contents of
this register are constantly compared with the current value of
the free running counter. When a match is found, a flag is set
(OCF) in the Timer Control and Status Register (TCSR) and the
current value of the Output Level bit (OLVL) in the TCSR is
clocked to the Output Level Register. Providing the Data
Direction Register for Port 2, Bit I contains a "I" (Output),
the output level register value will appear on the pin for Port 2
Bit 1. The values in the Output Compare Register and Output
Level bit may then be changed to control the output level on
the next compare value. The Output Compare Register is set to
$FFFF during reset. The Compare function is inhibited for
one cycle following a write to the high byte of the Output
Compare Register to insure a valid 16·bit value is in the register
before a compare is made.
• Input Capture Register (SOOOD:$OOOEI
The Input Capture Register is a 16·bit read·only register used
to store the current yalue of the free running counter when the
proper transition of an external input signal occurs. The input
transition change required to trigger the counter transfer is
controlled by the input Edge bit (IEOG) in the TCSR. The Data
Direction Register bit for Port 2 Bit 0, should' be clear (zero)
in order to gate in the external input signal to the edge detect
unit in the timer.
The input pulse width must be at least two E-cycles to
ensure an input capture under all conditions.
• With PorI 2 Bit 0 configured as an output and sel to ".", the
external inpul will still be seen by the edge delect unit.
$FFFO 1-----4
SFFFF '--_ _ _"
External Interrupt Vectors
(NOTE!
Excludes the follOWing addresses which may
be used externally. $04. $OS. $06. $07. and
$OF.
Figure 12 HD6803 Memory Map
~HITACHI
348
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
HD6803, HD6803-1
HD8803 Intornel
BUI
Output Input
L~I
Edit
Bit 1
Bit 0
Port:2
Port 2
Figure 13 Block Diagram of Programmable Timer
Timer Control and Status Register
7
6
lieF I OeF
S
4
3
2
1
TOF I Elel I EOel I ETOIIIEDG
• Tim... Controllnd Statui Regiltar (TCSR) ($0008)
The Timer Control and Status Register consists of an 8-bit
register of which all 8 bits are readable but only the low order 5
bits may be written. The upper three bits contain read-only
timer status information and indicate the followings:
• a proper transition has taken place on the input pin with a
'subsequent transfer of the current counter value to the
input capture register .
• a match has been found between the value in the free
running counter and the output compare register, and
when SOOOO is in the free rUMing counter.
Each of the flags may be enabled onlo the HD680J inlernal
bus (iRTO
DO 4
2
ED 5
2
FD 5
3
A_M
B _ M+l
Subtract
SUBA
2
2 90
3
2
AO
4
2
BO
4
3
A-M _A
SUB£>
2
2
DO
3
2
EO
4
2 FO
4
3
B -M_B
83
4
3 93
5
2
A3
6
2
6
3
Double Subtract
SUBD
SBA
Subtract
SBCA
82
SBCB
C2
With Carrv
Transfer
Accumulators
TAB
TBA
Telt Zero or
TST
Minus
AO 87
80
CO
Subtract
Arcumulators
2 92 3 2 A2 4 2 B2
2 2 02 3 2 E2 4 2 F2
2
60
6
2
TSTB
Are
4
3
4
3
70 6
a
~
eo
A.B-M:M+l-A: B
10
TSTA
The Condition Corte Refltst"»r notes
83
1.-0
iiQ
=)a r:r.,I IIIII L,~
Sra,B
Store Double
bO
AO 87
STAA
Store
AccumulatOr
-
Act AI aee I
A7
3
ASAA
ASAO
Sh,h Aight
Bool.onl
Arithmetic OperatIOn
2
1
A-B-A
A-M-C-A
B-M-C-B
16
2 1 A-B
17
2
1 B-A
40
2
1 A -00
50
2
1 B - 00
M -00
3
5
4
H
I N Z V C
•
•
•
•
•
•
•
•
•
•
••
••
3
2
1 0
I I @I
I I @"' I
I I ~I
I
I
~
I
I 6 I
I I KID I
I
I
I
6
I
••A
••R
• •R
I ~I
• •
• •
• •
••
• •
••
• •
• •
••
• •
• •
• •
••
• •
• •
I
A
I
I
KID
I
I K§l I
~
R
I
•
•
•
I
I
I
A
I
I
A
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I I I
I I I
I A
I R
I R A
I R A
I R A
I
I
I
I
I
I
•
•
listed after Table 10.
Direct I\ltdr."ing
In direct addrts~in!1.. the address of the operand is contained
in the second byte of the instruction. Direct addressing allows
the user \0 directly address the lowest 256 bytes in the machine
i.e., locations zero through 255. Enhanced execution times are
achieved by storing data in these locations. In most configurations. it should be a random access memory. These are two-byte
instructions.
E"t.nded Addressing
In extended addressill~. the address contained in the second
byte of !he instruction i; used as the hi2her S-bits of the address
the operand. The third byte of the ~nstruction is used as the
lower R-bits of the address for the operand. This IS an absolute
~ddress in memory. These 3re three-byte IIIstrucllons.
I nclexed Addressing
In indexed addressmg. the address contained III the second
\lyte of the instruction -is added 10 the index register's lowest
of
•
8-bits in the CPU. The carry is then added to the higher
order 8-blls of the index register. This result is then used to
address memory. The modified address is held in a temporary
address register so there is no change to the index register. These
are two-byte instructions.
Implied Addre..ing
In the implied addressing mode the instruction gives the
address (i.e., stack pointer, index register, etc.). These are
one-byte instructions.
Relative Addressing
In relative addressing, the address contained in the second
byte of the instruction is added to the program counter's lowest
S-bns plus two. The carry or borrow is then added to the high
8-bits. This allows the user to address data within a range of
-126 to +129 bytes of the present instruction. These are twobyte IIIstrucllons.
HITACHI
Hitachi America, Ltd .• Hitachi Plaza e 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
355
HD6803 , HD6803-1
• New Instructions
In addition to the existing 6800 Instruction Set, the followmg new mstructlons are
incorporated in the H06803 Microcomputer.
ABX
Adds the 8·bit unsigned accumulator B to the l6-bit X-Register taking mto account
the possible carry out of the low order byte of the X-Register.
AOOO Adds the double precision ACCO· to the double precIsion value M:M+l and places
the results in ACCO.
ASLO Shifts all bils of ACCO one place to the left. Sit 0 is loaded with zero. The C bit is
loaded from the most significant bit of ACCO.
LOO
Loads the contents of double precision memory location mto the double
accumulator A:B. The condition codes are set accordmg to the data.
LSRO Shifts all bits of ACCO one place to the right. Bit 15 is loaded with zero. The C bit
is loaded from the least significant bit to ACCO.
MUL
Multiplies the 8 bits in accumulator A with the 8 bits 10 accumulator 8 to obtam a
l6-bit unsigned number in A:B, ACCA contains MSB of result.
PSHX The contents of the index register IS pushed 011tO the stack at the address con tamed
in the stack pointer. The stack pomter IS decremented by 2.
PULX The index register is pulled from the stack beginnmg at the current address
contained in the stack pointer + 1. The stack pomter IS mcremented by 2 in total.
STO
Stores the contents of double accumulator A:B in memory. The contents of ACCD
remain unchanged.
SUBO Subtracts the contents of M:M + I from the contents of double accumulator AB
and places the result 10 ACCD.
BRN
Never branches. If effect, this instruction can be conSidered a two byte NOP (No
operation) requiring three cycles for execullon.
CPX
Internal processing modified to permit tis use With any conditional branch instruction.
-ACCD'ls the 16 bit register (A B) formed by concatenatmg the A and 8 accumulators The A·accumulator is the most significant byte.
Table 8 Index Register and Stack Manipulation Instructions
Condition Code
AddreSSing Modes
POinter Operations
Mnemonic
IMMED.
OP
Compare Index Reg
Decrement Index Reg
Decrement Stack Pntr
Incr.ment Index Reg
Increment Stack Pnt~
Load Index Reg
CPX
DEX
DES
Register
Boolean!
8C
-"
4
3
DIRECT
OP
9C
c- t---
- - - - - - -.- 1- c--- - INX
- - : = - - - f---
- "
5 2
INDEX
OP
-
AC 6
EXTND
"2
IMPLIED
OP
-
BC
6 3
"
r---
INS
OP
-
"
09
3
1
ArithmetiC OperattOn
H
X-M
M+ 1
X -1-X
34
3
1 SP-l-SP
08
3
1
X + 1- X
31
3
1
SP+l-SP
LOX
CE
3
3
DE
4
2
EE
5
2
FE
5
3
M- XH.IM+II- XL
LOS
8E
3
3 9E
4
2 AE
5
2
BE
5
3
M- SP H • IM+II-SP L
STX
OF
4
2
EF
5
2
FF
5
3
X H -M.XL-IM+ll
Store Stack Pntr
Index Reg ..... Stack Pntr
STS
9F
4
2 AF
5
2
BF
5
3
SP H - 'In. SP L -IM+ 11
TXS
35
Stack Pntr - Index Reg
TSX
Add
ABX
Push Data
Pull Data
Load Stack Pntr
Store Index Reg
5
X-l-SP
3
1
30
3
1 SP + 1 - X
3A
3
1 B +X- X
PSHX
3C
4
1
XL - MoP' SP - 1 - SP
PULX
38
5
1
XH - MoP' SP - 1 - SP
SP+l-SP.Msp -X H
SP + 1 - SP. MoP
~
XL
•
•
•
•
•
•
•
•
•
•
•
•
•
4
3
.,
I
2
I
I
C
I
·•• ··• • ·• ··
·
·•
•
•
• ·· • •
·• •• ·• ·• ·•
· · · ]~
• · • • ·1·
• •
I--
•
."e •I
I
• ,7
• '7
.(j)
7
I
R'.
I
R
I
R
I
R
The Condition Code Register notes are listed after Table 10
~HITACHI
356
1 0
I N Z V
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6803, HD6803-1
Table 9 Jump and Branch Instructions
Condition Code
Rillist.,
5 4 3 2 1 0
H I N Z V C
Addressing Model
Operations
Branch Always
Mnemonic
- .. - .. - . - .. - ..
RELATIVE DIRECT
OP
DP
INDEX
OP
EXTND
OP
Branch Telt
IMPLIED
OP
•
•
•
•
•
•
•
•
•
•
·
• •
• • •
•••
• • •
• • •
•
• • •
• • •
• • •
• • •
• • •
• • •
•• •
•• •
• • •
• • •
•• •
•• •
• • •
• • •
20
21
24
25
27
2C
2E
22
2F
3
3
3
3
3
3
3
3
3
BlS
23
3 2
C+Z-1
BlT
BMI
20
2B
3 2
3 2
N@V-l
N -I
BNE
26
3 2
ZoO
BVC
28
3 2
V-O
29
3 2
2A 3 2
80 6 2
V -I
Jump
BVS
BPl
8SR
JMP
Jump To Subroutine
JSR
No Operation
NOP
01
Return From Interrupt
RTI
3B 10 1
-@-
RTS
39
1
SWI
WAI
3F 12 1
3E 9 1
• • • • •
• S • • • •
• @. • • •
Branch If CarrV Clear
Branch If Carry Set
Branch If - Zero
Branch If :> Zero
> Zero
Branch If
Branch If Higher
Branch If __ Zero
Branch I f Lower Or
Sem.
Branch If
<
Zero
Branch If Minus
Branch If Not Equal
Zero
Branch If Overflow
Clear
Branch If Overflow Set
Branch If Plus
Branch To SubrOutine
Return From
Subroutine
Softwar. I "tlrrupt
Wait for Interrupt
2
2
2
2
2
2
2
2
2
None
Non.
CoO
C-l
Z-1
N@V-O
Z + (N@ VI - 0
c+z-o
Z + (N@ VI-I
• •
••
• •
• •
• •
•
• •
• •
••
• •
• •
• •
• •
• •
BRA
BRN
BCC
BCS
BEO
BGE
BGT
BHI
BlE
Branch Never
· ·•• · ·
N-O
90 5
6E 3 2 7E 3 3
2 AD 6 2 BD 6 3
2
5
1
•
Advances Prog. Cntt,
Only
•
•
•
•
•
•
•
•
•
•
•
•
• • •
• • •
·
Tablel0 Condition Code Register Manipulation Instructions
fo. dd,e..,n9 Mod..
Operatons
MnemonIC
IMPLIED
OP
Clear Carry
Clear Interrupt Mask
Clear Overflow
Set carry
Set Interrupt Mask
Set Overflow
Accumulator A - CCA
CCR - Accumulator A
ClC
Cli
ClV
SEC
SEI
SEV
TAP
TPA
OC
OE
OA
00
OF
OB
06
07
- ..
2
2
2
2
2
2
2
2
Condition Code Regllter
Boolean Operation
1
1
1
1
1
1
1
1
O~C
O~I
O~V
1
~
1~
C
I
,~V
A~
CCR
A
CCR~
5
H
•
•
•
•
•
•
4
I
3
N
• •
•
• •
• •
S •
• •
R
2
Z
1
V
0
C
R
• •
• • •
• R •
• • S
• • •
• S •
--~4>---
• • • • I • I·
CondItion Code Register Notes: (Bit set it test is true and cleared otherwise)
1 (Bit VI
(Bil CI
(BIt C)
(Bit V)
(Bit V)
(Bit V)
(Bit N)
(All)
(Bit I)
(All)
(llit CI
Test. Result - 10000000'
Te.. R.sult. 00000000'
Test Oecimal value of most Significant BCD Character greater than nine) (Not cleared If previously set)
Test. Operand· 10000000 prior to execution?
Test Operand" 01111111 prior to execution)
Test: Set equal to result of N@ C after shift has occurred.
Test· Result less than zero? (Bit 15::; 1)
Load Conditton Code Register from Stack. (See Special Operations)
Set when interrupt occurs. If previously SIt, a Non·Maskable Interrupt is re~ulred to eXit the wait state.
Set according to the contents of Accumulator A
Set equal to ,esult 01 Bit 7 IACCBI
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
357
HD6803, HD6803-1
Table 11
ACCX
ABA
ABX
ADC
ADD
ADDD
AND
ASl
ASlD
ASR
BCC
BCS
BEa
BGE
BGT
BHI
BIT
•
•
•
•
•
•
2
•
•
•
•
•
•
BlT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
•
•
•
•
•
•
•
•
•
•
•
•
2
•
•
DAA
DEC
2
DES
DEX
EOR
•
•
•
INC
2
INS
•
Dlrecl
1'~".rJ d~:ed
•
•
•
•
•
•
•
•
3
3
5
3
4
4
6
4
6
4
4
6
4
6
•
•
2
2
4
2
•
•
2
BlE
BlS
I;;;:.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6
6
•
•
•
•
•
•
•
•
3
4
4
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6
6
•
•
•
•
•
•
2
3
4
4
4
5
6
6
6
6
•
•
•
•
•
•
•
6
6
•
•
•
•
•
•
Instruction Execution Times in Machine Cvde
2
3
4
4
•
•
•
•
6
6
•
•
PI::·
2
3
•
•
•
•
•
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Rt·
..tlve
•
•
•
•
•
•
•
•
•
3
3
3
3
3
3
•
3
3
2
2
2
2
•
3
3
LDD
LOS
LOX
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
SBA
SBC
SEC
6
3
SEI
SEV
STA
STD
•
•
•
2
•
•
•
INX
JMP
JSR
LOA
RTS
•
•
ACCX
•
•
•
•
•
•
•
STS
STX
SUB
SUBD
•
•
•
•
•
2
•
•
2
•
•
3
•
4
•
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
3
3
3
TAB
TAP
TBA
TPA
TST
•
•
•
•
TSX
•
WAI
•
•
5
3
4
4
4
t.~~~ ~~~
•
•
3
6
4
5
3
6
5
5
5
5
4
5
1m·
Rt·
plied
I.'iva
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
3
•
•
•
•
•
•
•
•
•
•
2
3
4
4
•
•
•
•
•
•
•
•
•
•
•
•
3
4
4
4
5
5
5
4
6
5
5
5
•
•
•
•
•
12
•
2
2
2
•
•
•
•
•
•
•
•
•
•
2
4
•
•
•
2
•
•
Dlrtct
•
•
•
•
SWI
TXS
•
•
•
•
•
~";'.~:.
•
4
4
3
5
•
•
•
•
•
•
•
6
6
•
•
•
•
6
6
•
4
4
•
•
•
•
•
•
•
•
•
•
6
6
6
6
•
•
•
•
•
•
•
•
•
•
•
3
•
10
•
•
•
•
•
2
4
6
•
4
•
•
•
•
•
•
•
•
2
2
2
•
10
5
2
•
•
•
•
•
•
6
6
•
•
•
•
•
•
5
•
•
9
•
•
•
•
•
•
•
•
•
•
•
•
•
~HITACHI
358
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6803 , HD6803-1
• Summery of Cycle by Cycle Operation
Table 12 proVides a detailed descnpllon of the information
present on the Address Bus. Data Bus, and the Read/Write line
(R/\V) during each cycle for each instruction.
This information is useful in companng actual with expected
results during debug of both software and hardware as the
control program is executed. The information IS categorized in
groups according 10 addressmg mode and number of cycles per
instruclIon. (In general. Instructions with the same addressing
mode and number of cycles execute in the same manner: ex·
ceptions are mdicated in the table).
Table 12 Cycle by Cycle Operation
Address Mode &
Instructions
Address Bus
Data Bus
IMMEDIATE
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
LOS
LOX
LDD
3
1
2
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
CPX
SUBD
ADDD
4
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus F F F F
1
1
1
1
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
Op Code Address
Op Code Address + 1
DestinatIon Address
1
1
0
Op Code
DestinatIon Address
Data from Accumulator
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
1
1
1
1
OpCode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1
1
1
0
0
OpCode
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
1
OpCode
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Subroutine Address
Stack POInter
Stack Pointer + 1
1
1
1
0
0
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
3
1
2
3
4
DIRECT
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
3
1
2
3
STA
3
LOS
LOX
LDD
4
STS
STX
STD
4
CPX
SUBD
ADDD
5
JSR
5
1
2
3
1
2
3
4
1
2
3
4
1
2
3
4
5
1
2
3
4
5
(ContInued)
_HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300
369
HD6803 , HD6803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
INDEXED
JMP
3
1
2
3
ADC
ADD
AND
BIT
CMP
EOA
LOA
OAA
SBC
SUB
4
3
4
4
STA
1
2
1
2
3
4
LOS
LOX
LDD
LDD
5
STS
STX
STD
5
1
2
3
4
5
1
2
3
4
5
ASL
ASA
CLA
COM
DEC
INC
LSA
NEG
AOL
AOA
TST'
CPX
SUBD
ADDD
6
1
2
3
4
5
6
6
1
2
3
4
5
6
JSA
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Aegister Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Aestart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Aegister Plus Offset
1
1
1
0
Op Code
Offset
Low Byte of Aestart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Aeglster Plus Offset
Index Aeglster Plus Offset + 1
1
1
1
1
1
Op Code
Offset
Low Byte of Aestart Vector
Operand Data (HIgh Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Aeglster Plus Offset
Index Aegister Plus Offset + 1
1
1
1
0
0
Op Code
Offset
Low Byte of Aestart Vector
Operand Data (HIgh Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Aeglster Plus Offset
Address Bus FFFF
Index Aeglster Plus Offset
1
1
1
1
1
0
Op Code
Offset
Low Byte of Aestart Vector
Current Operand Data
Low Byte of Aestart Vector
New Operand Data
Op Code Add ress
Op Code Address + 1
Address Bus FFFF
Index Aegister + Offset
Index Aeglster + Offset + 1
Address Bus FFFF
1
1
1
1
1
1
Op Code
Offset
Low Byte of Aestart Vector
Operand Data (HIgh Order Byte)
Operand Data (Low Order Byte)
Low Byte of Aestart Vector
Op Code Address
Op Code Address + 1
Address Bus F F F F
Index Aeglster + Offset
Stack Pointer
Stack Po In ter - 1
• In the TST Instruction, R/W Ime of the Sixth cycle IS "'" level, and AS
1
1
1
1
a
a
Op Code
Offset
Low Byte of Aestart Vector
f----~
Op Code
Offset
Low Byte of Aestart Vector
F "51 Subroutine Op Code
Aeturn Address (Low Order Byte)
Aeturn Address (HIgh Order Byte)
= FFFF, DB = Low Byte of
Reset Vector.
(Continued)
~HITACHI
360
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6803, HD6803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
EXTENDED
JMP
3
1
2
3
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
4
1
2
3
4
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
1
1
1
1
Op Code
Address of Operand (High Order Byte)
Address of Operand (Low Order Byte)
Operand Data
4
1
2
3
4
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Destination Address
1
1
1
0
OpCode
Destination Address (High Order Byte)
Destination Address (Low Order Byte)
Data from Accumulator
LOS
LOX
LDD
5
1
2
3
4
5
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
1
1
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
STS
STX
STD
5
1
2
3
4
5
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address of Operand + 1
1
1
1
0
0
Op Code
Address of Operand
Address of Operand
Operand Data (High
Operand Data (Low
(High Order Byte)
(Low Order Byte)
Order Byte)
Order Byte)
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address of Operand
Address Bus FFFF
Address of Operand
1
1
1
1
1
0
Op Code
Address of Operand (H,gh Order Byte)
Address of Operand (Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
CPX
SUBD
ADDD
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
Operand Address
Operand Address + 1
Address Bus F F F F
1
1
1
1
1
1
Op Code
Operand Address (High Order Byte)
Operand Address (Low Order Byte)
Operand Data (High Order Byte)
Oper and Data (Low Order Byte)
Low Byte of Restart Vector
JSR
6
1
2
3
4
5
6
Op Code Address
Op Code Address + 1
Op Code Address + 2
Subroutine Starting Address
Stack Pointer
Stack Pointer - 1
1
1
1
1
0
0
Op Code
Address of Subroutine (High Order Byte)
Address of Subroutine (Low Order Byte)
Op Code of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
ADC
ADD
AND
BIT
CMP
EOR
LOA
ORA
SBC
SUB
STA
-----
ASL
ASR
CLR
COM
DEC
INC
LSR
NEG
ROL
ROR
TST'
• In the TST instruction, RIW line of the
SIxth
cycle
IS "'"
level, and AB
-
= FFFF, DB:: Low Byte of
Reset Vector
(Continued)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
361
HD6803, HD6803-1
Table 12 Cycle by Cycle Operation (Continued)
Address Mode &
Instructions
Address Bus
Data Bus
IMPLIED
ABA
ASL
ASR
CBA
CLC
CLI
CLR
CLV
COM
ABX
DAA
DEC
INC
LSR
NEG
NOP
ROL
ROR
SBA
SEC
SEI
SEV
TAB
TAP
TBA
TPA
TST
2
3
1
2
Op Code Address
Op Code Address + 1
1
1
1
2
Op Code Address
Op Code Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Previous Register Contents
Op Code Address
Op Code Address + 1
Address Bus F F F F
Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Stack Pointer
Op Code Address
Op Code Address + 1
Address Bus F F F F
1
1
1
1
1
3
ASLD
LSRD
3
DES
INS
3
INX
DEX
3
PSHA
PSHB
3
TSX
3
TXS
3
PULA
PULB
4
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
1
2
3
Stack Poonter + 2
1
1
2
Op Code Address
Op Code Address + 1
Stack POInter
Stack POInter - 1
1
1
3
5
4
1
2
3
4
5
RTS
WAI··
5
9
1
1
1
1
1
1
1
1
1
1
1
1
5
1
2
PULX
0
3
4
3
4
1
1
1
1
1
1
1
1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Op Code Address
Op Code Address + 1
Stack POInter
Stack Pointer - 1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer + 1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack POInter
Stack POInter + 1
1
2
4
PSHX
,
1
2
3
4
0
0
1
1
1
1
1
1
1
1
1
0
0
Op Code
Op Code of Next Instruction
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code
Irrelevant Data
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Accumulator Data
Op Code
Op Code of Next Instruction
Irrelevant Data
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack
Op Code
Irrelevant Data
Index Register (Low Order Byte)
Index Reglner (High Order Byte)
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Bvte)
Index Register (Low Order Byte)
OpCode
Irrelevant Data
Irrelevant Data
Address of Next Instruction
(High Order Byte)
Address of Next Instruction
(Low Order Byte)
OpCode
Op Code of Next Instruction
Return Address (Low Order Bvte)
Return Address (High Order Byte)
(ContInued)
•
362
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6803, HD6803-1
Table 12 Cycle by Cycle Operat,on (Continued)
Address Mode &
Instructions
WAI··
Cycles
Cycle
;:
5
6
7
8
9
MUL
10
SWI
10
12
Stack
Stack
Stack
Stack
Stack
POinter
Pointer
Pointer
POinter
POinter
-
2
3
4
5
6
Op Code Address
Op Code Address + 1
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus F F F F
Address Bus FFFF
Address Bus FFFF
Op Code Address
Op Code Address + 1
Stack POinter
Stack Pointer + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
Stack POinter + 2
1
6
Stack Pointer + 3
1
7
Stack Pointer + 4
1
8
Stack POinter + 5
1
9
Stack POinter + 6
1
10
Stack POinter + 7
1
10
11
Op Code Address
Op Code Address + 1
Stack POinter
Stack POinter - 1
Stack POinter - 2
Stack POinter - 3
Stack POinter - 4
Stack POinter - 5
Stack POinter - 6
Stack POinter - 7
Vector Address FFFA (Hex)
1
1
0
0
0
0
0
0
0
1
1
12
Vector Address FFFB
(He~)
1
1
2
3
4
5
6
7
8
9
RT!
RIW
Line
0
0
0
0
0
Address Bus
10
1
2
3
4
1
2
3
4
5
6
7
8
9
Data Bus
Index Register (Low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Op Code
Irrelevant Data
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
Low Byte of Restart Vector
OpCode
Irrelevant Data
Irrelevant Data
Contents of Cond. Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(Low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instructlon Address from
Stack (Low Order Byte)
OpCode
Irrelevant Data
Return Address (Low Order Byte)
Return Address (High Order Byte)
Index RegISter (Low Order Byte)
Index RegISter (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
(Continued)
•• WhIle the MPU IS In the "Wilt" st.te, Its bus state will appear as a SIrI'S of MPU reads of an address which IS seven lOCations less thin the
onglna' contents of the Stick POtnter. Contrary to the HD6800. none of the ports are draven to the high Impedance state by • WAI
,nstruClion.
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
363
HD6803, HD6803-1
Table 12 Cycle by Cycle Operation (Continued)
RELATIVE
Address Mode &
Instructions
BCC BHT BNE
BCS BlE BPl
BEQ BlS BRA
BGE BlT BVC
BGT BMT BVS
BRN
Cycle
#
1
Cycles
3
2
3
BSR
6
1
2
3
4
5
6
R/W
Line
1
Address Bus
Op Code Address
Op Code Address + 1
Address Bus FFFF
Data Bus
OpCode
Branch Offset
Low Byte of Restart Vector
t
1
Op Code Address
Op Code Address + 1
Address Bus FFFF
Su broutlne Starting Address
Stack POinter
Stack POinter - 1
Op Code
Br anch Offset
Low Byte of Restart Vector
Op Cllde of Next Instruction
Return Address (Low Order Byte)
Return Address (High Order Byte)
t
1
1
1
0
0
When the op codes (4E. SE) are used to execute. the MPU
continues to increase the program counter and it wjll not stop
until the Reset signal enters. These op codes are used to test the
LSI.
• Summary of Undefined Instruction Operations
The HD6803 has 36 underlined instructions. When these are
carried out, the contents of Register and Memory in MPU
change at random.
Table 13 Op codes Map
HD6B03 MICROPROCESSOR INSTRUCTIONS
OP
COOE
~
LO
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
6
OlIO
---0000
0
NOP
ACC
A
0001
1
0010
0011
2
3
SSA
BRA
TSX
CSA
BRN
INS
..------
...-
SHI
PULA 1+11
SLS
PULB 1+11
BCC
DES
BCS
TXS
TAB
SNE
PSHA
LSRO 1+11 ~
ASLO 1+11 ~
TAP
DIll
7
TPA
TBA
BEQ
PSHB
1000
8
lNX 1+11
..------
BVC
PULX 1+21
OAA
1001
9
OEX 1+11
1010
A
CLV
BVS
RTS 1+21
BPl
ABX
lal1
B
SEV
ABA
BMI
RTI 1+ 71
1100
C
CLC
-------~
BGE
PSHX 1+11
1101
0
SEC
/
BlT
MUll+7I
1110
E
Cli
~
BGT
WAI (+61
1111
F
SEI
~
BlE
SWII+91
1/2
1/2
2/3
113
BYTE/CYClE
(NOTES)
ACC INO
B
ACCA or SP
eXT
0100 0101 OlIO 0111
--------5
4
6
7
ACCS or X
IMMJ OIRJ INO 1 eXT
IMM 1 OIR J INOJ EXT
1000 1 1001110101 lOll
11001110111"011111
8
I
I
9
A
I
NEG
C
101
ElF
0
SUB
-COM
CMP
1
SSC
2
SUBO 1+21
·
AOOO 1+21
AND
BIT
5
ROR
LOA
6
~J
.~J
STA
STA
EOR
ASl
ROl
AOC
DEC
ORA
A
----
ADD
CPX 1+21
INC
~~4~1
TST
-- .. -
JMP 1-31
2/6
LOS 1+11
• I+it[
ClR
112
.
JSR 1+21
3/6
2/2
J
STS 1+11
1 2/4 J 3/4
2/3
B
·
·
LOO 1+11
5TO 1+11
• 1+111
lOX 1+11
• I+l}!
2/2
J
5TX 1+11
2/3
J
2/41 3/4
11 Undefined Opcode. are marked With ~.
4~
) Indicate that the number ,n parentheSIS must be added to the cycle count for that Instruction.
The instructions shown below Ire all 3 bytes Ind are marked with ......
Immechate addresslOg mode of SUeD. CPX. LOS. AODD. LDO and LOX IOstructlons, and undefined op codes
18F, CD. CFI.
The Op codes (4E, 5E) are 1 byte/- cvcles Instructions, and are marked With ......
•
364
7
8
9
2) (
3~
3
4
LSR
ASR
1/2
S
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
C
0
E
F
::c
S·
'"'~
:l>
3
~
n"
?'
r-
Et
•
;;
~
~
-c
~
'"•
§""
~~
-c
_
~ :I
~~
~C')
~ :I
•
OJ
ai'
C"
'"
:::l
'"
C")
:l>
'f
o
~
~
<0
•
'];:
~
..--L.,
~
I
'SCI • TIE·TORE + RIE·(RORF + ORFE)
IN
Y
,----<
Vector ... PC
NMI
TAP
SWI
IRQ,
ICF
DCF
TOF
SCI
~
c.n
~
Co
FFFC FFFO
FFFA FFFB
FFF8 FFF9
FFF6 FFF7
FFF4 FFF5
FFF2 FFF3
FFFO FFFl
v.>
o
o
A
Non-Maskable Interrupt
Software Interrupt
Maskable Interrupt Request 1
Input Capture Interrupt
Output Compare Interrupt
Timer Overflow Interrupt
SCI Interrupt (TORE + RORF + ORFE)
::r:
tJ
en
(Xl
o
w
::r:
tJ
en
(Xl
w
en
01
Figure 16 Interrupt Flowchart
o
W
I
~
HD6803, HD6803-1
Dati Bu.
Add .... Bu.
Figure 17 HD6803 MPU Expanded Multiplexed 8uI
• Ceutlon for the HD6803 Family SCI, TIMER Stetul FI..
The flags shown in Table 14 are cleared by reading/writing
(flag reset condition 2) the data register corresponding to each
flag after reading the status register (flag reset condition I).
Table 14
Status Flag
To clear the flag correctly. take the following procedure:
I. Read the status register.
2. Test the flag.
3. Read the data register.
StatuI Flag Reset Conditions
Flag Reset Condition 1
(Status Register)
Flag Reset Condition 2
(Dlte Regilter)
ICR/Read
ICF
When each flag is "1",
TIMER
OCF
TRCSR/Read
OCRIWrit.
TC/Read
TOF
RDRF
SCI
When each flag is "1",
RDR/Read
ORFE
TRCSR/Read
TDRIWrite
TORE
.HITACHI
366
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6809, HD68A09, HD68B09-
MPU
(Micro Processing Unit)
The HD6809 is a revolutionary high perfonnance 8-bit
microprocessor which supports modem programming techniques such as position independence, reentrancy, and modular
programming.
This third-generation addition to the HMCS6800 family has
major architectural improvements which include additional
Jegisters, instructions and addressing modes.
The basic instructions of any computer are greatly enhanced
by the presence of powerful addressing modes. The HD6809 has
the most complete set of addressing modes available on any
8-bit microprocessor today.
The HD6809 has hardware and software features which make
it an ideal processor for higher level language execution or
standard controller applications.
H D6809P, H D6BA09P, H D6BB09P
(DP-40)
• PIN ARRANGEMENT
HD6800 COMPATIBLE
• Hardware - Interfaces with All HMCS6800 Peripherals
• Software - Upward Source Code Compatible Instruction Set and Addressing Modes
•
•
•
•
ARCHITECTURAL FEATURES
Two 16-bit Inde)( Registers
Two 16-bit Inde)(able Stack Pointers
Two 8-bit Accumulators can be Concatenated to Form
One 16-Bit Accumulator
• Direct Page Register Allows Direct Addressing Throughout Memory
HArf
Vss 1 0
NMT
2
XTAl
il«j 3
EXTAL
i'iAil
"lfE"S
BS
MROY
BA
a
Vee
DMA78'REO
ANi
HD6809
0,
0,
0,
0,
D.
•
•
•
•
•
•
•
•
•
•
•
•
HARDWARE FEATURES
On Chip Oscillator
DMAIBREO Allows DMA Operation or Memory Refresh
Fast Interrupt Request Input Stacks Only Condition
Code Register and Program Counter
MRDY Input E)(tends Data Access Times for Use With
Slow Memory
Interrupt Acknowledge Output Allows Vectoring By
Devices
SYNC Acknowledge Output Allows for Synchronization
to External Event
Single Bus-Cycle RESET
Single 5-Volt Supply Operation
NMI Blocked After RESET Until After First Load of
Stack Pointer
Early Address Valid Allows Use With Slower Memories
Early Write-Data for Dynamic Memories
0,
0,
0,
A"
A ..
A,,-.._ _ _ _ _ _- - ' - A ..
(Top View)
• Compatible with MC6809, MC68A09 and MC68B09
• SOFTWARE FEATURES
• 10 Addressing Modes
HMCS6800 Upward Compatible AddreSSing Modes
Direct Addressing Anywhere in Memory Map
Long Relative Branches
Program Gaunter Relative
True Indirect Addressing
E)(panded Indexed AddreSSing:
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
367
HD6809, HD68A09, HD68B09
•
•
•
•
•
•
•
0, 5, 8, or 16-bit Constant Offsets
~, or 16-bit Accumulator Offsets
Auto-Increment/Decrement by 1 or 2
Improved Stack Manipulation
1464 Instructions with Unique Addressing Modes
8 x 8 Unsigned Multiply
16-bit Arithmetic
Transfer1'Exchange All Registers
Push/Pull Any Registers or Any Set of Registers
Load Effective Address
• BLOCK DIAGRAM
+--Vcc
+--vss
An
NMi
J!1'RQ
TRll
x
o{
OMA/BREQ
R/W
A
B
HALi'
BA
BS
XTAL
EXTAL
MROY
E
Q
.HITACHI
368
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6809, HD68A09, HD68B09
• ABSOLUTE MAXIMUM RATINGS
Item
Supply Voltage
.
Symbol
Value
Unit
Vee
-0.3-+7.0
V
Input Voltage
Operating Temperature
Vi" *
-0.3-+7.0
Top ...
-20 - +75
V
°c
Storage Temperature
THO
-55 - +150
°c
• With respect to Vss (SYSTEM GNDI
(NOTE)
Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under
recommended cperating conditions. If these conditions are exceeded.
It
could affect rehatMhty of LSI.
• RECOMMENDED OPERATING CONDITIONS
.
.
Item
Supply Voltage
Input Voltage
V ,H
Symbol
min
typ
max
Unit
Vee
V ,L
4.75
-0.3
5.0
5.25
0.8
V
.
Operating Temperature
Logie
(Ta = 0 - +75°C)
2.0
-
Logie
(Ta = -20 - DoC)
2.2
-
Vee
RES
4.0
-
Vee
-20
25
75
Topr
V
Vee
V
°c
"With respect to Vss (SYSTEM GNDI
• ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee =5V±5%, Vss = OV, Ta
Symbol
Item
Input "High" Voltage
=-2D-+75°C, unlen otherwise noted.l
Test Condition
Ta=0-+75°C
Except RES
V'H
Ta
= -20 -
O°C
Input "Low" Voltage
Three State (Off Statel
Input Current
V,L
Except EXTAL.
XTAL
°0- 0 7
A.-A",RtW
°0 ......
Output "High" Voltage
lin
I TS1
01
Ao-A IS • RIW.
Q.E
V OH
Input Capacitance
Output Capacitance
VOL
Po
0 0 -0 7
Except Do -07
Ao""'AI5. R IW.
SA.BS
Vin-0-5.25V.
,
Vcc=max
Vin=O.4-2.4V.
Vcc=max
'LOAO=-205"A.
VCc=min
I LOAO =-145"A.
Vcc==min
I LOAO=-100"A.
VCc=mln
SA.SS
Output "Low" Voltage
Power Dissipation
HD6809
tvo' max
Vee
Cin
Cout
' LOAO=2mA
Vin=OV,
Ta=25°e.
f=IMHz
•
min
2.0
2.2
HD68A09
tvo' max
Vee
Vee
-
Vee
-0.3
-
Vee
0.8
-0.3
-2.5
2.5
-2.5
2.4
-
2.4
2.4
2.2
4.0
RES
Input Leakage Current
min
2.0
-10
-100
-
-
-10
10
100 -100
-
HD68809
tvo" max
Vee
2.2
-
4.0
-
-
Vee
O.B
-0.3
2.5
-2.5
-
10
100
-10
-100
-
2.4
-
Vee
-
V
2.5
"A
10
100
"A
-
2.4
-
-
2.4
-
-
2.4
-
-
-
2.4
-
-
2.4
-
-
-
-
7
0.5
1.0
15
10
-
-
12
7
-
12
-
-
7
0.5
1.0
15
10
-
-
12
-
10
V
-
-
0.5
1.0
15
10
Unit
Vee
0.8
-
10
-
4.0
min
2.0
10
-
-
V
V
W
pF
pF
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
369
HD6809, HD68A09, HD68B09
•
AC CHARACTERISTICS (Vcc=5V±5%, Vss = OV, Ta = -20-+75°C, unless otherwise noted.}
1. CLOCK TIMING
HD6809
Item
Frequency of Operation
Symbol
HD68A09
HD68809
Test Condition
Unit
mIn
typ
max
mIn
typ
4
0.4
15500 280
-
5000
280
-
25
-
-
-
max
min
typ
6
0.4
(Crystal or External Input)
fXTAL
0.4
Cycle Time
teye
1000
Total Up Time
tUT
975
Processor Clock "High"
tpWEH
450
Processor Clock "Low"
tpwEL
430
E Rise and Fall Time
tEr, tEf
E Low to QHigh Time
tAVS
200
-
250
130
tpWQH
450
-
5000
280
tpwOL
450
-
15500
280
-
-
25
-
-
25
-
200
-
-
133
-
-
100
a Clock "High"
a Clock "Low"
a A,se and Fa" Time
tar. tOf
0Low to E Falling
tOE
FIg. 2, Fig. 3
-
10000 667
-
640
-
max
165
80
-
5000
220
-
5000
ns
15700 220
-
15700
ns
-
20
ns
-
ns
10000 500
-
480
15700 220
5000 210
25
-
8
MHz
10000
ns
-
ns
15700
ns
5000
ns
20
ns
125
ns
2. BUS TIMING
item
Symbol
Test Condition
min
Address Delay
Address Valid to 0High
Peripheral Read Access Time
ItUT-tAO-tOSA=tACC)
D.t. Set Up Time (Aead)
Input Data Hold Time
Address Hold Time
I
A, -A", AMi
Oata Delay Time (Write)
OutpUt Hold Time
-
tAO
tAO
tACC
'DDW
tOHW
-
Fig. 2, Fig. 3
Fig. 2, Fig. 3
Ta=e-+75·C
FIg. 2, Fig. 3
Ta=-20-0'C
Fig. 3
Fig.3
Ta=0-+7S·C
Fig.3
Ta=-20-0·C
min
min
HD68B09
typ max
- 110
440
60
10
-
20
-
10
-
-
-
-
200
-
-
140
-
30
-
-
30
-
-
30
-
20
-
-
20
-
-
20
-
695
200
-
80
10
-
-
20
-
10
-
HD68A09
typ max
140
-
-
50
tOSR
tOHR
tAH
HD6809
typ max
25
-
-
-
Unit
ns
ns
-
15
-
330
-
-
ns
40
10
-
-
-
-
ns
ns
20
-
-
ns
10
-
n.
110
n,
-
ns
-
ns
3. PROCESSOR CONTROL TIMING
Item
MADY Set Up Time
Interrupts Set Up Time
HALT Set Up Time
RES Set Up Time
DMA/BREO Sat Up Time
Processor Control Rise and Fall Time
Crystal Oscillator Start Time
Symbol
Test Condition
tPCSM
tpcs
t~CSH
tpCSR
tpCSO
tPCr,
tpCt
tRC
Fig. 6-Flg. 10
Fig. 14, FIg. 15
min
HD6809
typ max
125
200
200
200
125
-
-
-
-
-
HD6BA09
typ max
125
140
140
140
125
-
min
-
-
-
-
100
-
-
50
-
-
HD68B09
typ mex
n.
-
-
100
-
-
100
n.
30
-
-
30
ms
-
~HITACHI
370
Unit
110
110
110
110
110
-
-
min
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
ns
ns
n.
ns
HD6809, HD68A09, HD68B09
5.0V
• C = 30pF (BA. BSI
130pF (D. - 0,. E. 01
90pF (A, - All' R/WI
·R= llkn(D,-D,1
16kn (A, - All' E. O. R/WI
24kn (BA. BSI
Test POint o--~-~--",--+
R
All diodes are lS2074t9or equivalent.
C includes Stray Capacitance.
Figure 1 Bus Timing Test Load
RiW _ _ _..r
*Hold time for BA. 85 not specified.
Figure 2 Read Data from Memory or Peripherals
"Hold t,me for BA. BS not specified.
Figure 3 Write Data to Memory or Peripherals
• PROGRAMMING MODEL
As shown in Figure 4, the HD6809 adds three registers to the
set available in the H06800. The added registers include a
Direct Page Register, the User Stack pointer and a second Index
Register.
Accumulaton lA, B, 01
The A and B registers are general purpose accumulators
which are used for arithmetic calculations and manipulation of
data.
Certain instructions concatenate the A and B registers to
form a single l6-bit accumulator. This is referred to as the D
•
register, and is formed with the A register as the most significant
byte.
• Direct Page Regimr IDPI
The Direct Page Register of the H06809 serves to enhance
the Direct Addressing Mode. The content of this register appears
at the higher address outputs (As-AI 5) during Direct Addressing Instruction execution. This allows the direct mode to be
used at any place in memory, under program control. To ensure
HD6800 compatibility, all bits of this register are cleared during
Processor Reset.
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
371
HD6809, HD68A09, HD68B09
offset. During some indexed modes, the contents of the index
register are incremented or decremented to point to the next
item of tabular type data. All four pointer registers (X, Y, U, S)
may be used as index registers.
Index Registen IX, V)
The Index Registers are used in indexed mode of addressing.
The 16-bit address in this register takes part in the calculation of
effective addresses. This address may be used to point to data
directly or may be modified by an optional constant or register
•
o
15
x-
},,"~,~,-.
Index Reg Ister
Y - Index Register
...
U - User Stack POinter
S - Hardware Stack POinter
PC
Program Counter
1
A
"-
B
,
v
Accumulators
o
o
L-_ _ _ _D_p_ _ _ _..J1
7
Direct Page Register
0
IElF I II I Iz I Ic I
H
N
V
cc -
Condition Code Register
Figure 4 Programming Model of The Microprocessing Unit
• Stack Pointer IU, S)
The Hardware Stack Pointer (S) is used automatically by the
processor during subroutine calls and interrupts. The stack
pointers of the HD6809 point to the top of the stack, in
contrast to the HD6800 stack pointer, which pOinted to the
next free location on the stack. The User Stack Pointer (U) is
controlled exclusively by the programmer thus allowing arguments to be passed to and from subroutines with ease. Both
Stack Pointers have the same indexed mode addressing capabilities as the X and Y registers, but also support Push and Pull
instructions. This allows the HD6809 to be used efficiently as a
stack processor, greatly enhancing its ability to support higher
level languages and modular programming.
• Program Counter
The Program Counter is used by the processor to point to the
address of the next instruction to be executed by the processor.
Relative Addressing is provided allowing the Program Counter
to be used like an index register in some situations.
• CONDITION CODE REGISTER DESCRIPTION
Bit 0 IC)
Bit 0 is the carry flag, and is usually the carry from the
binary ALU. C is also used to represent a 'borrow' from subtract
like instructions (CMP, NEG, SUB, SBC) and is the complement
of the carry from the binary ALU.
•
Bit 1 (V)
Bit I is the overflow flag, and is set to a one by an operation
which causes a signed two's complement arithmetic overflow.
This overflow is detected in an operation in which the carry
from the MSB in the ALU does not match the carry from the
MSB·J.
•
• Bit 2 IZ)
Bit 2 is the zero flag, and is set to a one if the result of the
previous operation was identically zero.
Bit 3 IN)
Bit 3 is the negative flag, which contains exactly the value of
the MSB of the result of the preceding operation. Thus, a
negative two's--complement result will leave N set to a one.
•
• Condition Code Register
The Condition Code Register define~ the State of the
Processor at any given time. See Fig. 5.
•
Bit 4 (I)
Bit 4 is the 'iRU mask bit. The processor will not recognize
interrupts fro.!!!.Jhe m:Q line if this bit is set to a one. NMI,
FIRQ, M'O', RES, and SWI all are set I to a one; SWI2 and SW13
do not affect I.
Carry
Overflow
--Zero
~----
Negative
- - - - - - I R O Mask
- - - - - - Half Carry
' - - - - - - - - - FIRO Mask
' - - - - - - - - - - - - Entire Flag
• BitS IHI
Bit 5 is the half· carry bit, and is used to indicate a carry' from
bit 3 in the ALU as a result of an 8-bit addition only (ADC or
ADD). This bit is used by the DAA instruction to perform a
BCD decimal add adjust operation. The state of this flag is
Figure 5 Condition Code Register Format
•
372
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6809, HD68A09, HD68B09
undefmed in all subtract-like instructions.
Table 1 Memory Map for Interrupt Vectors
Memory Map For
Vector Locations
MS
LS
FFFE
FFFF
FFFC
FFFD
FFFA
FFFB
FFF8
FFF9
FFF6
FFF7
FFF4
FFF5
FFF2
FFF3
FFFO
FFFl
• Bit 6 (F)
Bit 6 is the FIRQ mask bit. The processor will not rec~nize
interrupts from the FIRQ line if this bit is a one. NMI, IRQ,
SWI, and RES aU set F to a one. tm:!, SWI2 and SWl3 do not
affect F.
• Bit 7 (E)
Bit 7 is the entire flag, and when set to a one indicates that
the complete machine state (all the registers) was stacked, as
opposed to the subset state (PC and CC). The E bit of the
stacked CC is used on a return from interrupt (RTI) to
determine the extent of the unstacking. Therefore, the current
E left in the Condition Code Register represents past action.
• SIGNAL DESCRIPTION
Power (Vss, Vee)
Two pins are used to supply power to the part: VSS is
ground or 0 volts, while VCC is +S.OV ±S%.
•
• AddreaBus(Ao-A 15 )
Sixteen pins are used to output address information from the
MPU onto the Address Bus. When the processor does not
require the bus for a data transfer, it will output address
FFFF t6 , R/W = "High", and BS = "Low"; this is a "dummy
access" or VMA cycle. Addresses are valid on the rising edge of
Q (see Figs. 2 and 3). AU address bus drivers are made high
impedance when output Bus Availalbe (BA) is "High". Each pin
will drive one Schottky TTL load or four LS TTL loads, and
typically 90 pF.
• Data Bul (Do -0 7 )
These eight pins provide communication with the system
bi-directional data bus. Each pin will drive one Schottky TTL
load or four LS TTL loads, and typically 130 pF.
• ReadlWrite (R/WI
This signal indicates the direction of data transfer on the data
bus. A "Low" indicates that the MPU is writing data onto the
data bus. R/W is made high impedance when BA is "High". R!W
is valid on the rising edge of Q. Refer to Figs. 2 and 3.
•
Interrupt Vector
Description
m
NMI
SWI
IRQ
FIRQ
SWI2
SWI3
Reserved
• HALT
A "Low" level on this input pin will cause the MPU to stop
running at the end of the present instruction and remain halted
indefinitely without loss of data. When halted, the BA output is
driven "High" indicating the buses are high impedance. BS is
also "High" which indicates the processor is in the Halt or Bus
Grant state. While halted, the MPU will not respond to external
real-time requests (FIRQ, IRQ) although DMA/BREQ will
always be accepted, and NMI or RES will be latched for later
response. During the Halt state Q and E continue to run
normally. If the MPU is not running (RES, DMA/BREQ). a
halted state (BA' BS=I) can be achieved by pulling HALT
"Low" while "RES' is still "Low".lfDAM/BREQ and HALT are
both pulled "Low", the processor will reach the last cycle of the
instruction (by reverse cycle stealing) where the machine will
then become halted. See Figs. 8 and 16.
•
BUI Available, Bul Status (BA, BSI
The BA output is an indication of an internal control signal
which makes the MOS buses of the MPU high impedance. This
signal does not imply that the bus will be available for more
than one cycle. When BA goes "Low", an additional dead cycle
will elapse before the MPU acquires the bus.
The BS output signal, when decoded with BA, represents the
MPU state (valid with leading edge of Q).
Table 2 MPU State Definition
Reset (m)
A "Low" level on this Schmitt· trigger input for greater than
one bus cycle will reset the MPU, as shown in Fig. 6. The Reset
wctors are fetched from locations FFFEt6 and FFFF 16 (Table
I) when Interrupt Acknowledge is true, (BA • BS= I). During
initial power-on, the Reset line should be held "Low" until the
clock oscillator is fully operational. See Fig. 7.
Because the H1>6809 Reset pin has a Schmitt-trigger input
with a threshold voltage higher than that of standard peripherals,
a simple RIC network may be used to reset the entire system.
This higher threshold voltage ensures that all peripherals are out
of the reset state before the Processor.
•
BA
0
0
1
1
BS
0
1
0
1
MPU State
Normal (Running)
Interrupt or RESET Acknowledge
SYNC Acknowledge
HALT or Bus Gtant
Interrupt Acknowledge is indicated durin~.E.?th cycles of a
hardware-vector-fetch (RES, NMI, FIRQ, IRQ, SWI, SWI2,
5W13). This signal, plus decoding of the lower four address lines,
can provide the user with an indication of which interrupt level
is being serviced and allow vectoring by device. See Table 1.
Sync: Acknowledge is indicated while the MPU is waiting for
external synchronization on an interrupt line.
Hait/Bul Grant is true when the H06809 is in a Halt or Bus
Grant condition .
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
373
w
E§
......
~
0')
CO
o
c.o
f.
~
CD
~.
!it
•
.
I
E§
.... I
0')
CO
~
c.o
"'C
",..\\\S\S\\~
~~
C
~SSSSSS~~~~SS~C:::)(:::JC:::)(:::J~__~~)(~~~~K:::J(:F;'.~.J(::::~:::~C:::)(:::>C:::)(:::JC:::)(:::JC:::)(;MM~~J(;__;;~;X::::K:;F,;m:)C:::)(
•
..
~2:
~
I\)
~~"I"!'"'t"4~
H,ay.
.. \§~
&\\\S%~
Loltyce
VIP:
H,,,.
I_IOn
r.
\
w..
I
Figure 6 RES Timing
~ l:
~
.I~
•
i~
c:I
4.75\7
Vcc
E
---+~
5"
~
-1~
RES
~
tRC
--=--I
<»
HD6809
cO
•
~
~
i
ImlructoCWl
U
I
8
a~
"'Co
LoB".
YI
8MHz
6MHz
4 MHz
Cin
Caut
38
18pF±20% 18pF ± 20%
22pF±20% 22pF ± 20%
22pF±20% 22 pF ± 20%
Gn;J;
Figure 7 Crystal Connections and Oscillator Start Up
V,
39
J;Cout
,'--_ _ _ __
::r::
t:l
0')
CO
ttl
o
c.o
HD6809, HD68A09, HD68B09
• Non Mllklble Interrupt (NMII*
A negative edge on this input requests that a non-maskable
interrupt sequence be generated. A non-maskable interrupt
cannot be inhibited~ the program. and also has a higher
priority than FIRQ. IRQ or software interrupts. During recognition of an NMi. the entire machine state is saved on the
2nd To L.t Last Cycle
CyeleOf
Of
Current
Current
Dead
•
'nit. • • 'nit. I • Cycle •
I
I
I
I
hardware stack. After reset. an NMI will not be recognized until
the first program load of the Hardware Stack Pointer (S). The
pulse width of NY! "Low" must be at least one E cycle. If the
mI input does not meet the minimum set up with respect to
Q. the interrupt will not be recognized until the next cycle. See
Fig. 9.
Halted
•
Halted
a
HAlT----~
<::X:::)
~n.----'r--~,r--~
Bu.
Fetch
aA _ _ _ _ _ _ _ _ _ _- J
I
If
I
If
as
Doto
~
I
\
\
I
<::X:::)~---
I
au.
Exeeute
InstructIOn
Opcode
Figure 8 HALT and Single Instruction Execution for System Debug
.... CycIo
of eu"....
Instruction
Fetch
hmructicMI
--IIf---------------------I.WNPI S_...... V . ., .. F.,.. _ _
,. "'
,m+', m+2 1m+3 1m+4 1",+S,m+1 I m+" m+8 1m+8,m+'O,m+llt+'2Im+'?lm+'4Im+'5Im+'8r+11 t+·BI n 1.+'.,
1-,
o
Figure 9
TIm and Jimllnterrupt Timing
.HITACHI
Hitachi America. Ltd. • Hitachi P'aza· 2000 Sierra Point Pkwy. * Brisbane. CA 94005-1819. (415) 589-8300
375
HD6809, HD68A09, HD68B09
LMt Cyde
of Current
In.truetlon
Ir'lltruc:tlon
Fetch
1 1 - - - ! - - - - - - - - l n 1 . r r u p t StKklng end VltCtor Fetc:h Sequene.
a
.. ~--~v---~--~.r---~--~__--v---~--~r---~--~----v----v--~~--~
~
Bu•
mm
.•:;,t' I
VIH
r
PC
tPCs
~O~8~V~
PC
FFFF
SF-I
SP-2
SP-3
FFFF
FFF6
FFF7
FFFF
NewPC NewPC+l
_______________________________________________________________
\I...---~/
Figure 10 FIRO Interrupt Timing
• Fast-Interrupt Request (FIROI*
A "Low" level on this input pin will initiate a fast interrupt
sequence provided its mask bit (F) in the CC is clear. This
se~ence has priority over the standard Interrupt Request
(IRQ), and is fast in the sense that it stacks only the contents of
the condition code register and the program counter. The
interrupt service routine should clear the source of the interrupt
before doing an RTI. See Fig. 10.
Interrupt Request (lRQI*
A "Low" level input on this pin will initiate an interrupt
Request sequence provided the mask bit (I) in the CC is clear.
Since IRQ stacks the entire machine state it provides a slower
response to interrupts than FIRQ. IRQ also has a lower priority
than FIRQ. Again, the interrupt service routine should clear the
source of the interrupt before doing an RTI. See Fig. 9.
•
*
near the LSI as much as possible.
[ Normal oscillation may be disturbed when external noise is)
induced to pin 38 and 39.
2) Pin 38 and 39 signal line should be wired apart from other
signal line as much as possible. Don't wire them in parallel.
[ Normal oscillation may be disturbed when E or Q signal is
feedbacked to pin 38 and 39.
o
40
39'-1r~~aa~--~IICO~
38
37L-J==__,
NMI, FIRQ, and IRQ requests are sampled on the falling
edge of Q. One cycle is required for synchronization before
these interrupts are recognized. The pending interrupt(s)
will not be serviced until completion of the current instruction unless a SYNC or CWAI condition is present. If IRQ and
FIRQ do not remain "Low" until completion of the current
instruction they may not be recognized. However, NMI is
latched and need only remain "Low" for one cycle.
• XTAL, EXTAL
These inputs are used to connect the on-chip oscillator to an
external parallel· resonant crystal. Alternately, the pin EXTAL
may be used as a TTL level input for external timing by
grounding XTAL. The crystal or external frequency is four
times the bus frequency. See Fig. 7. Proper RF layout
techniques should be observed in the layout of printed circuit
boards.
< NOTE FOR BOARD DESIGN OF THE OSCILLATION
CIRCUIT>
In designing the board, the following notes should be taken
when the crystal oscillator is used.
I) Crystal oscillator and load capacity Cin, Cout must be placed
J-......,
cin -rir
HD6809
Figure 11 Board Design of the Oscillation Circuit.
A signal line or a power source line must not cross or go near
the oscillation circuit line as shown in Fig. 12 to prevent the
induction from these lines and perform the correct oscillation.
The resistance among XT AL, EXT AL and other pins should be
over 10Ms).
~HITACHI
376
'1
J
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6809, HD68A09, HD68B09
•
MUlt be
elD
"i"i
i
a.
I
I
ill;;;
o
E,Q
E is similar to the H06800 bus timing signal '2; Q is a
quadrature clock signal which leads E. Q has no parallel on the
H06800. Addresses from the MPU will be valid with the leading edge of Q. Data is latched on the falling edge of E. Timing
for E and Q is shown in Fig. 13.
avoided.
1\
• MRDY
~~:~'---------~9MIC
This input control signal allows stretching of E and Q to
extend data-access time. E and Q operate normally while MRDY
is "High". When MRDY is "Low", E and Q may be stretched in
integral multiples of quarter (1/4) bus cycles, thus allowing
interface to slow memories, as shown in Fig. 14. A maximum
H06809
Figure 12 Example of Normal Oscillation may be Disturbed.
Stlrt o~ Cycle
End of Cycle! Latch Deta)
I
E
,..--_ _ _ _ _..., I
X:
--x_O~.5..;..V_ _ _ _ _..J/
!--t --L
AVS
a
I
I
I
li
O.5V
:
2. 4V
\
I
~.----~I-----
I
AddreSi Valid
Figure 13 EfQ Relationship
\I....----J/
2.4V"\
f~
!'------I
I
I
a
MROY
/
\"--_-.J/
oJ/
11;'"
(s--llo~':"'~V-H-----
\ ....-.,.:---fff-S_ _ _
.aj~
--------------"'I:~""I~""I~~~~~:""'~~~
Figure 14 MRDY Timing
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
377
HD6809, HD68A09, HD68B09
stretch is 10 microseconds. During non valid memory access
(WA cycles) MRDY has no effect on stretching E and Q; this.
inhibits slowing the processor during "don't care" bus accesses.
MRDY may also be used to stretch clocks (for slow memory)
when bus control has been transferred to an external device
(through the use of HALT and DMA/BREQ).
Also MRDY has effect on stretching E and Q during Dead Cycle.
•
DMA/BREQ
The DMA/BREQ input provides a method of suspending
execution and acquiring the MPU bus for another use, as shown
in Fig. 15. Typical uses include DMA and dynamic memory
refresh.
Transition of DMA/BREQ should occur during Q. A "Low"
level on this pin will step instruction execution at the end of the
current cycle. The MPU will acknowledge DMA/BREQ by
setting BA and BS to "High" level. The requesting device will
now have up to 15 bus cycles before the MPU retrieves the bus
for self-refresh. Self-refresh requires one bus cycle with a leadMPU
DEAD
ing and trailing dead cycle. See Fig. 16.
Typically, the DMA controller will request to use the bus by
asserting DMA/BREQ pin "Low" on the leading edge of E.
When the MPU replies by setting BA and BS to a one, that cycle
will be a dead cycle used to transfer bus mastership to the DMA
controller.
False memory accesses may be prevented during and dead
cycles by developing a system DMAVMA signal which is "Low"
in any cycle when BA has changed .
When BA goes "Low" (either as a result of DMA/BREQ"High" or MPU self-refresh), the DMA device should be taken
off the bus. Another dead cycle will elapse before the MPU
accesses memory, to allow transfer of bus mastership without
contention.
• MPU OPERATION
During normal operation, the MPU fetches an instruction
from memory and then executes the requested function. This
DMA
DEAD
MPU
E
Q
DMA/BREQ
BA, BS
DMAVMA' _ _ _- J/
\'--_____---J/
______---J)~----------------------~c
ADDR
(MPU)
ADDR
(DMAC)
----------~(~------------------~)~----
"DMAVMA is a signal which is developed externally, but is a system requirement for DMA.
Figure 15 Typical DMA Timing «14 Cycles)
~HITACHI
378
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6809, HD68A09, HD68B09
!oEADIf-...__
- - - - - - - - 1 . OMA CVc1.. --------.----JOEAOI
I
I
I
I
I
I
I
MPU
IOEA~OMAI
I
I
I
E
Q
I
DMA/BREQ
~ul--~---------------------------I
BA, BS
-1Ir-~------------------------------------------~~l ' - - I- ! - fvr~I---------I
I
DMAVMA'
__________________~_+--~I--_r----------I
I
I
I
I
_.~
*OMAVMA is a signal which
I
I
I
~'--_______
IS
developed externally. but
IS
a system requirement for DMA.
Figure 16 Auto - Refresh DMA Timing
(Reverse Cycle Stealing)
sequence begins at RES and is repeated indefinitely unless
altered by a special instruction or hardware occurrence. Soft·
ware instructions that alter nonnal MPU operation are: SWI,
SWI2, SWI3, CWAI, RTI and SYNC. An interrupt, HALT or
DMA/BREQ can also alter the nonnal execution of instructions.
Fig. 17 illustrates the flow chart for the H06809.
Immediate Addressing
In Immediate Addressing, the effective address of the data is
the location immediately following the opcode (Le., the data to
be used in the instruction immediately follows the opcode of
the instruction). The HD6809 uses both 8 and l6·bit immedir!e
values depending on the size of argument specified oy the
opcode. Examples of instructions with Immediate Addressing
•
are:
•
ADDRESSING MODES
The basic instructions of any computer are greatly enhanced
by the presence of powerful addressing modes. The H06809 has
the most complete set of addressing modes available on any
microcompu ter today. For example, the H06809 has 59 basic
instructions; however, it recognizes 1464 different variations of
instructions and addressing modes. The addressing modes
support modern programming techniques. The following ad·
dressing modes are available on the fl06809:
(I) Implied (Includes Accumulator)
(2) Immediate
(3) Extended
(4) Extended Indirect
(5) Direct
(6) Register
(7) Indexed
Zero·Offset
Constant Offset
Accumulator Offset
Auto Increment/Decrement
(8) Indexed Indirect
(9) Relative
(10) Program Counter Relative
•
LDA #$20
LOX #$FOOO
LOY #CAT
(NOTE) # signifies Immediate addressing, $ signifies hexa·
decimal value.
• Extended Addressing
In Extended Addressing, the contents of the two bytes
immediately following the opcode fully specify the l6·bit
effective address used by the instruction. Note that the address
generated by an extended instruction defines an absolute
address and is not position independent. Examples of Extended
Addressing include:
LOA
CAT
STX
MOUSE
LOD
$2000
Extended Indirect
As a special case of indexed addressing (discussed below),
"I" level of indirection may be added to Extended Addressing.
In Extended Indirect, the two bytes following the postbyte of
an Indexed instruction contain tire address of the data.
LOA
[CAT]
LOX
[$FFFE)
STU
[DOG)
•
Implied (Includes Accumulator)
In this addressing mode, the opcode of the instruction
contains all the address information necessary. Examples of
Implied Addressing are: ABX, DAA, SWI, ASRA, and CLRB.
•
•
Direct Addressing
Direct addressing is similar to extended addressing except
that only one byte of address follows the opcode. This byte
specifies the lower 8·bit of the address to be used. The upper
8·bit ofthe address are supplied by the direct page register. Since
only one byte of address is required in direct addreSSing, this
mode requires less memory and executes faster than extended
addressing. Of course, only 256 locations (one page) can be
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
379
::r:
CAl
(Xl
o
t1
-
1ilm.~
10)
co
0
(0
~
~
::r:
2:
t1
0)
»
3
'"n
co
!::
c.
(0
::l.
~
}>'
0
•
::r:
:I:
s:
t1
0)
n
2:
co
-0
tx:l
~
•
0
(0
8
w..
<:>
~ l:
_
-0
2. ~
3. )i
";?(')
~ :I
•
OJ
::l.
CJ)
c:r
'"
16
(")
»
§
'f'
c»
cO
H06809 I nterrupt Structure
•
E
Bus State
BA
BS
en
0>
en
0,
Running
0
o
Interrupt or Reset Acknowledge I
0
~
w
Sync
8
Halt/Bus Grant
(NOTE)
Asserting RES will result in entering the reset sequence from anv point in the flow chart.
Figure 17 Flowchart for 1:106809 Instruction
I
o
HD6809, HD68A09, HD68B09
accessed without redefining the contents of the OP register.
Since the OP register is set to $00 on Reset, direct addressing on
the H06809 is compatible with direct addressing on the
H06800. Indirection is not allowed in direct addressing. Some
examples of direct addressing are:
$30
LDA
SETOP
$10 (Assembler directive)
LOB
$1030
LDO
C!~~~----------------~r---------t--------------------(==~=>C===:JC:==:JC:===
Dot.
r.~c:x=r:J-----'r---T---------(=X=X::::=:X=
,
.•
Rm===x===Jr-----~\------------~,------~----------~--------------8A
=::A________...J!
-..IL
•
~~~------------------------~.------~------------------------------
~
-jf-}tpCf
~ ------------------------------------------~'r---~OV~~;=H~~~~il-----.-.------_________________________________
~
~~-
(NOTES)
• If the associated mask bit is set when the interrupt is reques~hls ~ will be an Instruction fetch from address location PC + 1.
However, if the interrupt is accepted (NMI or an unmasked FIRQor IRQ) interrupt processing contmues with this cycle as (m) on Figure 9
and 10 (Interrupt Timl!!.9L
•• If mask bits are clear, fRO and ~ must be held "Low" for three cycles to guarantee that mterrupt will be taken, although only one
cycle is necessary to bring the processor out of SYNC.
Figure 19 Sync Timing
~
Opcode (Fetch)
Long
Short
hnmedl.te
Brench
Branch
81
Inherent
OPCode +
Inde;l(ed
Opcode +
ACCAOffllt
ACC80fhei
Ff .. 5811
Ff" 8 81t
PC + 8 81t
vh
Auto
Auto
FI + 16·811
Inc/Dee Inc/Dec
8~'
8y2
"'0
PC + btendltd No Off .. t
16-811 'ndlrect
OpcOcie .. Opcocie .. Opcode .. Opc.ode +
Opcode .. Opced... Opcod. + Opcode +
vkvk.
vk vk
t
ADOR
I
i
StICk (Write)
StICk (Write)
(NOTE)
Write operation during store instruction.
Figure 20 Address Bus Cycle-by-Cycle Performance
$HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
385
HD6809, HD68A09, HD68B09
ImphedPISJIt
t~~--~--r---r---T---'---~---r--~--~----~---ff---ASLA
AIX
A5LS
RTS
EXG
TF"
MUL
PSHU
PSHS
ASRA
ASRI
elRA
PULU
PULS
OWl
twAI
RTI
SWl'
OWl3
eLAS
COMA
COMB
DAA
DECA
OEca
STACK
v
v
VIp-"
STACK'
INCA
{STACK,,,,
(Wmel 0
LSLB
LSRA
LSRI
NEG ...
NEGI
NOP
ROLA
I
12xSTACK
(Wntel
tDllmmyRHdI
INCB
LSLA
LI
VMA.
VECTOR
v~
YIn:
1.
ROLB
RORA
RDRB
.EX
TSTA
TSTS
(WI'"
2'l
(I) DMA/BREQ : "Low" for 6-13 cycles
(2) DMA/BREQ : "High" for 3 cycles
(#1)
HD6809 acknowledges the input signal level of
DMA/BREQ at the end of each cycle, then detennines
whether the next sequence is MPU or DMA. When
"Low" level is detected, HD6809 executes DMA
MPU
cycle
I 1---------'---------1
I
I
Dead
cycle
DMA cycle
I I
Deed
MPU cycle
Deed
cycl. f----..:...~--_i cycle
DMA cycl.
E
DMA/BREO
BA.BS
i~ri------------------~~
,,
,
:
• r
i·
3 cycle.
6-13 cycle.
Assertion of
BAdeley.
one clock
cycle
Figure 21 Exception of BA, BS Output
verce cycle steal. And it is only cleared ifDMA!BREQ is
inactive ("High") for 3 or more MPU cycles. So I or 2
inactive cycle(s) doesn't affect the self refresh counter.
(b) Exceptional Operations of DMA/BREQ, BA signals
(#2)
HD6809 includes a self refresh counter for the reo
E
11 cycle "H igh
"I
DMA/BREO
BA.BS
DMA
Self Refresh
counter
12 cycle. "Hi9h'j
DMA/BREO
BA.BS
I:
l:
~
,,...o-___'>-------,,''-,-+.'::--:-.., ,-------.~:
ef~ective (~5 cycl~')
r. ;2
~
l~"
~~
I
,I'
I
I
CYCle;
~
cYcle
!
Reverse
steal 1
: " :
_I I
,
\~.-I~----~lt~I----~----~--~--~-------
'r:r--~l~,
V,------
'------~
I
t
DMA
Self Refresh
counter
I-
effective 115 cycle.)
..j
Reverse .:vele st.el •
Figure 22 Exception of "O:";"M:'A",""B"'R"'E"'a
•
396
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD6809, HD68A09, HD68B09
(c)
How to avoid the.. exceptional operationl
It is necessary to provide 4 or more cycles for in-
DMAiBRE~,-
active DMA/BREQ level as shown in Fig. 23_
l'-----~~---i~~-=--=--=-_
l-i,. .
______
4 or mort cvcl..
----1
\
BA, BS
I
Figure 23 How to Avoid Exceptional ()perations
(a) An Example of the Syltam Configuration
This restriction is applied to the following system.
(I) DMA/BREQ is used for DMA request.
(2) "Halt Burst Mode" is used for DMA transfer
(2) Restriction for DMA Tranlfer
There is a restriction for the DMA transfer in the H06809
(MPU), H06844 (DMAC) system. Please take care of following.
r---DMAiBAEQ
DMA tranlfar
a
request
DAQH
0
C t--- E clock
"w4
HD6809
tMPUI
BA
HD6844
tDMACI
DGANT
DMA acknowledge
Figure 24 An Example of HD6809, HD6844 System
The restriction is also applied to the system which doesn't )
( use 7474 Flip-Flop. Fig. 24, Fig. 25 shows an example which
uses 7474 for synchronizing DMA request with E.
(b) Restriction
"The number of transfer Byte per one DMA Burst
transfer must be less than or equal to 14."
reverse cycle steals once in 14 DMA cycles by taking
back the bus control. In this case, however, the action
taken by MPU is a little bit different from the DMAC.
Halt burst DMA transfer should be less than or
equal to 14 cycles. In another word, the number
stored into DMA Byte count register should be 0-14.
As shown in Fig. 25, DMA controller can't stop
DMA transfer (@) by BA falling edge and excutes
an extra DMA cycle during H06809 dead cycle. So
MPU cycle is excuted right after DMA cycle, the Bus
confliction occurs at the beginning of MPU cycle.
• Please than care of the section [I)(b) if 2 or more
DMA channels are used for the DMA transfer.
(d)
(c) Incorrect operation of HD6809, H06844 system
"Incorrect Operation" will occur if the number of
DMA transfer Byte is more than 14 bytes. If i»IAT
BREQ is kept in "Low" level HD6809 performs
How to imp/iment Halt Bust DMA transfer
(> 14 cycles)
Please use HALT input of H06809 for the DMA
request instead of DMA/BREQ.
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
397
HD6809, HD68A09, HD68B09
1 - - - - - - - 1 4 cycles - - - - - - i
E
IHD6809 side I
HD6B09 reverse
cycle steal
DMAfBREQ
BA
HD6B09r---~-L-477.r.r-~---------------I-----------i??77.~~~~~----~D~M~A-C-YC~le-S--cycle
DMA eye es
MPU cycle is
extuted right
after DMA,
Bus confliction
occurs
IHD6B44 side I
)
i:i'FiQH
+-_-f
DGRNT _ _
(BAI
HD6B44
DMA cycles
DMAcycles
cycles
@)
(
MPU seU BA to inactive "Low" )
for reverse cycle steal, But
DMAC couldn't acknowledge
)
the request and performs
extra DMA during Dead cycle.
Figure 25 Comparison of HD6809, HD6844 DMA cycles
(3) Note for ClR Instruction
CycIe-by-cycle flow of CLR instruction (Direct, Extended, Indexed Addressing Mode) is shown below. In this
sequence the content of the memory location specified by
the operand is read before writing "00" into it. Note that
status Flags, such as IRQ Flag, will be cleared by this extra
data read operation when accessing the control/status
register (sharing the same address between read and write)
of peripheral devices.
Example: CLR (Extended)
S8000
SAOOO
CLR
FCB
$AOOO
S80
Cycle #
1
2
Address
Data
8000
7F
R/W
Description
Opcode Fetch
8001
AO
Operand Address,
High Byte
8002
3
00
Operand Address,
Low Byte
4
FFFF
1
VMACycle
5
AOOO
80
1
Read the Data
6
FFFF
1
VMACycle
7
AOOO
00
o
Store Fixed "00"
into Specified
Location
• The data bus has the data at that particular address .
1
I
•
•
•
398
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6809, HD68A09, HD68B09
MRDY signal, nonnally derived from the chip select decoding,
must meet the tpes timing. MRDY's positive transition must
occur with the rising edge of 4f.
[4] Note for MRDY
HD6809 require synchronization of the MRDY input with
the 4f clock. The synchronization necessitates an external oscillator as shown in Figure 26. The negative transition of the
XTAL
39
______________________________
EXTAL~3~8
~
__--,
Part of
HD6809
MRDy~36~--~~--------;---------~
MRDY
7~4
+5V
Active Low
Chip Select
For Slow
Memory or
P.ripheral
PR
SynchroniZltion
o
lk
14
R }
4 A2
74121
Valu••
Chosen
al Req'd
C
3 AI
5 B
7
MRDY Str.tch
L-_S;;t:;.:r.;;;tc;;;h_-....;O;;;.7~R;;;C:....___________ To Memory
Figure 26 MRDY Synchronization
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
399
HD6809E, HD68A09E,---HD68B09E
MPU(Micro Processing Unit)
The HD6809E is a revolutionary high performance 8-bit
microprocessor which supports modem programming techniques
such as position independence, reentrancy, and modular
programming_
This third-generation addition to the HMCS6800 family has
major architectural improvements which include additional
registers, instructions and addreSSing modes.
The basic instructions of any computer are greatly enhanced
by the presence of powerful addressing modes. The HD6809E
has the most complete set of addressing modes available on any
8-bit microprocessor today.
The HD6809E has hardware and software features which
make it an ideal processor for higher level language execution
or standard controller applications. External clock inputs are
provided to allow synchronization with peripherals, systems or
other MPUs.
HD6800 COMPATIBLE
• Hardware - Interfaces with All HMCS6800 Peripherals
• Software - Upward Source Code Compatible Instruction Set
and Addressing Modes
• ARCHITECTURAL FEATURES
• Two lS-bit Index Registers
• Two lS-bit Indexable Stack Pointers
• Two 6-bit Accumulators can be Concatenated to Form One
16-Bit Accumulator
• Direct Page Register Allows Direct Addressing Throughout
Memory
• HARDWARE FEATURES
• External Clock Inputs, E and Q, Allow Synchronization
• TSC Input Controls Internal Bus Buffers
• L1C Indicates Opcode Fetch
• AVMA Allows Efficient Use of Common Resources in A
Multiprocessor System
• BUSY is a Status line for Multiprocessing
• Fast Interrupt Request Input Stacks Only Condition Code
Register and Program Counter
• Interrupt Acknowledge Output Allows Vectoring By Devices
• SYNC Acknowledge Output Allows for Synchronization to
External Event
• Single Bus-Cycle RESET
• Single 5- Volt Supply Operation
• NMI Blocked After RESET Until After First load of Stack
Pointer
• Early Address Valid Allows Use With Slower Memories
• Early Write-Data for Dynamic Memories
• SOFTWARE FEATURES
• 10 Addressi ng Modes
HMCS6800 Upward Compatible Addressing Modes
Direct Addressing Anywhere in Memory Map
Long Relative Branches
Program Counter Relative
True Indirect Addressing
Expanded Indexed AddreSSing:
0, 5, 8, or 16-bit Constant Offsets
8, or IS-bit Accumulator Offsets
•
•
•
•
•
•
•
AutO'I ncrement/Decrement by 1 or 2
Improved Stack Manipulation
1464 Instruction with Unique Addressing Modes
8 x 8 Unsigned Multiply
16-bit Arithmetic
Transfer/Exchange All Registers
Push/Pull Any Registers or Any Set of Registers
load Effective Address
• PIN ARRAN;.G_E_M_E_N_T_ _ _--,_
HALf
TSC
lIC
~
AVMA
o
BUSY
RiW
HD6809E
0,
0,
0,
0,
D.
O.
0,
0,
A..
A..
A..
(Top Viewl
~HITACHI
400
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
HD6809E, HD68A09E, HD68B09E
• ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Value
Unit
Supply Voltage
Vcc·
-0.3 - +7.0
V
Input Voltage
Vin·
-0.3 - +7.0
Operating Temperature Range
Topr
-20 - +75
Storage Temperature Range
Tstg
-55 -+150
V
·c
·c
• With respect to Vss (SYSTEM GND)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended
operating conditions. If these conditions are exceeded, it could affect reliability of LSI.
• RECOMMENDED OPERATING CONDITIONS
Item
Supply Voltage
Logic,
RES
Q,
Logic
•
max
unit
5.0
5.25
V
VIL·
-0.2
-0.3
-
0.8
V
0.4
V
VIHC·
E
Operating Temperature
•
typ
4.75
-
2.2
VIH·
RES
.
min
Vcc·
VILC·
E
Input Voltage
Symbol
-
4.0
Vcc· -0.75
Topr
-20
Vcc'
V
Vcc·
V
Vcc· +0.3
V
·c
75
25
With respect to Vss (SYSTEM GND)
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS (Vee
=S.OV ±S", Vss =OV, Ta =-20 -
Input "High" Voltaoe
LogIc,Q
V,H
VIHR
E
VIHC
2.2
4.0
Vee
Logic,a,m
V,L
-0.2
V,Le
~.3
LogiC. C, RES
InplJt Leakage Current
Ion
00- 0 ,
Ao-Au.R/W
VOH
VOL
Power Dlllipation
Po
-0,. logiC
Input,a,rn
-2.5
-100
ILoad' -205jIA,
Con
Output Capacitance
FrequencV of Operation
Three-State (Off State)
Input Current
Cout
00- 0 ,
ITSI
Ao-Als. R/W
typ·
Vee 2.2
Vee 4.0
Vee
+0.3
-
~7E
mi' min
Vee 2.2
Vo< 4.0
Vee
~~76
-
+0.3
-
O.S -0.2
0.4 ~.3
2.5 -2.5
100 -100
0.8 -0.2
0.4 ~.3 2.5 -2.5 100 -100 -
mox
Vee
Vee
Vee
-
+0.3
-
O.S
0.4
2.5
100
-
Unit
V
V
V
V
V
,.,.
,.,.
2.4
2.4
2.4
V
Vee -mm
2.4
2.4
2.4
V
ILoad' -IOOjjA,
2.4
2.4
2.4
V
'Load
II
2mA.
Vee" min
Vin-OV,
Ta
II
2SOC.
f-1MHz
A.-A", RNI,
SA, as, LlC,
AVMA.aUSY
E,a
HD88B09E
typo
ILoad' -145jIA,
Vee" min
Output "Low" Voltage
00
Vin-O-S.25V.
Vee" max
HD68A09E
tvp· max
~.7
Vee "min
SA, as. LIC,
AVMA, aUSY
Input Capecltance
HD6809E
min
rn
Input "Low" Voltage
Output "High" Voltage
Tnt Condition
Symbol
Item
+75·C, unle•• otherwise noted.)
Vin-OV.
Ta" 25°C.
f-1MHz
Vln-O.4-2.4V.
Vee'" max
0,5
0.5
0.5
V
1,0
1.0
1.0
W
10
15
10
15
10
15
pf
30
50
30
50
30
50
pF
10
15
10
15
10
15
pF
1.0 0.1
10 -10
100 -100
-
1,5 0.1
10 -10 100 -100 -
0.1
-10 -100 -
-
2.0 MH,
10
100
,.,.
,.,.
• Ta· 2SoC. Vee - 5V
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
401
HD6809E, HD68A09E, HD68B09E
• AC CHARACTERISTICS (Vee
READ/wRITE TIMING
=5.0V ±5%, Vss =OV, Ta =-20 -
Item
+75°C, unless otherwise noted'!
Test
Condition
Symbol
HD68A09E
HD68809E
Unit
typ
'eyc
1000
-
'eyc - tEf - tAD - tDSA = tACC
tACC
695
-
-
440
-
-
330
-
-
ns
Data Set",! TIme IAead)
tDSA
80
60
-
10
10
-
30
30
-
20
-
-
20
-
20
-
10
-
10
-
-
ns
10
-
-
tDHA
-
40
Input Data Hold Time
-
-
-
-
140
120
ns
Cycle Time
Peripheral Read Access Times
Ta=0-+75'C
Output Data Hold Time
Ta = -20 - O'C
Address Hold Time
IAddress. A /W)
30
tDHW
20
Ta =0 - +75'C
Ta=-20-0·C
20
tAH
10
10000 500
-
200
-
-
9500
295
9500
210
9500
280
9500
220
-
25
-
-
130
140
-
210
-
-
150
200
-
140
120
-
-
85
300
-
250
300
100
-
-
10
-
E Clock "HIgh" IMeasured at VIH)
tpWEH
450
tEr, tEf
-
a Clock "HIgh"
tpWoH
450
o Rise and Fall Time
tar, tof
E "Low" to a AlSing
tEal
200
-
o "High" to E RISing
tEo2
200
-
E "High" to a Failing
tEo3
200
o "Low"
tEo4
200
-
Interrupts HALT, AES and TSC Setup TIme
tpcs
200
-
TSC Dnve to Valid LogiC Levels
tTSA
-
TSC Aelease MOS 8uffers to HIgh Impedance
tTSA
TSC Three·State Delay
tTSD
Control Delay 18USY, LIC)
tCD
-
Control Delay IAVMAO)
tCD
Processor Control Rise/Fall
tPCr, tPCf
-
TSC Input Delay
tPCT
10
AVMA drives a not-valid data before providing correct output, so spec teo max
min
-
tPWEL
to E Failing
20
-
max
-
tDDW
E Clock "Low"
Fall TIme
10000 667
typ
450
Data Delav Time (Write)
F!Js& and
min
-
tAD
Fig. 1.2,
7 -10,
14 and 17
max
-
Address Delay
E
*
HD6809E
min
200
25
9500
280
130
130
130
140
25
-
9500
220
25
-
-
100
100
100
100
110
100
-
-
10
270
typ
max
-
10000
-
ns
ns
ns
ns
ns
ns
110
ns
9500
ns
9500
ns
20
ns
9500
ns
20
ns
-
ns
120
ns
110
ns
ns
ns
ns
ns
80
ns
200
n.
240
n.
100
ns
-
ns
= 270 nsec
(H068A09E) and 240 nsec (HD68B09E) are applied to
this signal. When this delay time causes a problem in user's application, please use D-type latch to get stable output.
~HITACHI
402
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300
HD6809E, HD68A09E, HD68B09E
~-------~WEL--------~
E
VILe
VIH
Q
R/W
Add,.
BA.BS· ____
~~~~--~____~--------------------------~~~
0lt8
BUSY,
Lie,
AVMA
_NotValid
• Hold time for BA,
(NOTE)
as not opecified
Waveform measurements for all inputs and outputs ar. specified at logic "High" - V IHinin and logic "Low" - V fLmax unless otherwise specified.
Filure 1 Read Data from Memory or Peripherals
E
Q
R/'ll
Addr.
---~v:-~~~~"---I----------------li~
BA,BS. ___~~~~~"~__
~~
t-____________________________
D8t8
BUSY,
Lie,
AVMA
~NotValid
• Hold time for BA, BS not specified
(NOTE) Waveform measurements for ali inputs and outputs are specified at logic "High"· VIHmln and logic "Low"· VILmax unl... otherwillopeclfled.
Figure 2 Write Data to Memory or Peripherals
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
403
HD6809E, HD68A09E, HD68B09E
4 - - Vcc
4-Vss
AIm
11m
L--.r.=::::!..:....... L1C
....--..... AVMA
R/W
TSC
HALT
BA
BS
' - - -.... BUSY
'--_ _ E
'-----0
Figure 3 HD6809E Expanded Block Diagram
5.0 V
RL a 2.2 kll
Test POint
<>-'1-..--....-+
C
C a 30 pF lor BA, BS, LIC, AVMA, BUSY
130pF lor Do -0,
90 pF lor Ao -Au, RIW
R =11.7 kOlor Do -0,
16.5 kOlor Ao -Au, RIW
24 kOlor BA, BS, LIC, AVMA, BUSY
All diodes are 1S2074@ or equivalent.
C includes stray capacitance.
Figure 4 Bus Timing Test load
• PROGRAMMING MODEL
As shown in Figure S, the HD6809E adds three registers to
the set available in the H06800. The added registers include a
Direct Page Register, the User Stack pointer and a second
Index Register.
• Accumulators lA, B, D)
The A and B registers are general purpose accumulators
which are used for arithmetic calculations and manipulation
of data.
Certain instructions concatenate the A and B registers to
form a single 16-bit accumulator, This is referred to as the D
Register, and is formed with the A Register as the most
significant byte.
• Direct Page Register lOP)
The Direct Page Register of the H06809E serves to enhance
the Direct Addressing Mode. The content of this register
appears at the higher address outputs (As - A 15 ) during direct
addressing instruction execution. This allows the direct mode
to be used at any place in memory, under program control.
To ensure HD6800 compatibility, all bits of this register are
cleared during Processor Reset.
~HITACHI
404
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6809E, HD68A09E, HD68B09E
o
15
x-
Index Register
V - Index Register
Pointer Registers
U - User Stack POinter
S - Hardware Stack POinter
PC
A
\
.
I
Program Counter
B
,
Accumulators
o
7
0
L.I_ _ _ _ _
D_P_ _ _ _...JI
7
Direct Page RegISter
0
IElF IH II IN Iz I V Ic I
cc -
CondItion Code RegISter
Figure 5 Programming Model of The Microprocessing Unit
• Index Registen (X, Y)
The Index Registers are used in indexed mode of addressing.
The 16·bit address in this register takes part in the calculation
of effective addresses. This address may be used to point to
data directly or may be modified by an optional constant or
register offset. During some indexed modes, the contents of
the index register are incremented or decremented to point to
the next item of tabular type data. All four pointer registers
(X, Y, V, S) may be used as index registers.
• Stack Pointer (U, S)
The Hardware Stack Pointer (S) is used automatically by
the processor during subroutine calls and interrupts. The Vser
Stack Pointer (V) is con trolled exclusively by the programmer
thus allowing arguments to be passed to and from subroutines
with ease. The V·register is frequently used as a stack marker.
Both Stack Pointers have the same indexed mode addressing
capabilities as the X and Y registers, but also support Push and
Pull instructions. This allows the HD6809E to be used effi·
ciently as a stack processor, greatly enhancing its ability to
support higher level languages and modular programming.
(NOTE) The stack pointers of the HD6809E point to the top
of the stack, in contrast to the HD6800 stack pOinter,
which pointed to the next free location on stack.
• Program Counter (PC)
The Program Counter is used by the processor to point to
the address of the next instruction to be executed by the
processor. Relative AddreSSing is provided allowing the Program
Counter to be used like an index register in some situations.
• Condition Code Register (CC)
The Condition Code Register defines the state of the
processor at any given time. See Figure 6.
Carry
Overflow
~---Zero
' - - - - - - Negative
' - - - - - - - IRQ Mask
' - - - - - - - Half Carry
~-------- FIRQ Mask
' - - - - - - - - - - Entire Flag
Figure 6 Condition Code Register Format
• CONDITION CODE REGISTER DESCRIPTION
• Bit 0 (C)
Bit 0 is the carry flag, and is usually the carry from the
binary ALV. C is also used to represent a 'borrow' from
subtract like instructions (CMP, NEG, SVB, SBC) and is the
complement of the carry from the binary ALV.
• Bit 1 (V)
Bit I is the overflow flag, and is set to a one by an operation
which causes a signed two's complement arithmetic overflow.
This overflow is detected in an operation in which the carry
from the MSB in the ALV does not match the carry from the
MSB·1.
• Bit 2 (Z)
Bit 2 is the zero flag, and is set to a one if the result of the
previous operation was identically zero.
• Bit 3 (N)
Bit 3 is the negative flag, which contains exactly the value
of the MSB of the result of the preceding operation. Thus, a
negative two's·complement result will leave N set to a one.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
405
HD6809E, HD68A09E, HD68B09E
• Bit 4111
Bit 4 is the IRQ mask bit. The processor will not recognize
interrupts from the IRQ" line if this bit is set to a one. NMI,
FIRQ, IRQ, RES and SWI all set I to a one; SWI2 and SWI3
do not affect I.
This higher threshold voltage ensures that all peripherals are
out of the reset state before the Processor.
Table 1 Memory Map for Interrupt Vectors
Memory Map for Vector
Locations
• Bit 5(H)
Bit 5 is the half·carry bit, and is used to indicate a carry
from bit 3 in the ALU as a result of an 8·bit addition only
(AOC or ADD). This bit is used by the DAA instruction to
perform a BCD decimal add adjust operation. The state of this
flag is undefmed in all subtract-like instructions.
• Bit6(F)
Bit 6 is the FIRQ mask bit. The processor will not recognize
interrupts from the FIRQ line if this bit is a one. NMI, FIRQ,
SWI, and RES all set F to a one. IRQ, SWI2 and SWI3 do not
affect F.
• Bit 7(E)
Bit 7 is the entire flag, and when set to a one indicates that
the complete machine state (all the registers) was stacked, as
opposed to the subset state (PC and CC). The E bit of the
stacked CC is used on a return from interrupt (RTI) to determine the extent of the unstacking. Therefore, the current E
left in the Condition Code Register represents past action.
• HD6809E MPU SIGNAL DESCRIPTION
• Power (VSS, Vee)
Two pins are used to supply power to the part: Vss is
ground or 0 volts, while Vee is +5.0 V ±5%.
• Address Bill (Ao - Au)
Sixteen pins are used to output address information from
the MPU onto the Address Bus. When the processor does not
require the bus for a data transfer, it will output address
FFFF I6 , R/W = "High", and as = "Low"; this is a "dummy
access" or VMA cycle. All address bus drivers are made highimpedance when output Bus Available (BA) is "High" or when
TSC is asserted. Each pin will drive one Schottky TIL load or
four LS TIL loads, and 90 pF. Refer to Figures I and 2.
MS
LS
FFFE
FFFC
FFFA
FFF8
FFF6
FFF4
FFF2
FFFO
FFFF
FFFD
FFFB
FFF9
FFF7
FFF5
FFF3
FFFI
Interrupt Vector
Description
RES
NMI
SWI
iRa
FIRQ
SWI2
SWI3
R_rved
• HALT
A "Low" level on this input pin will cause the MPU to stop
running at the end of the present instruction and remain halted
indefmitely without loss of data. When halted, the BA output
is driven "High" indicating the buses are high impedance. BS
is also "High" which indicates the processor is in the Halt state.
While halted, the MPU will not ~nd to external real-time
requests (FIRQ, IRQ) although NMI or RES will be latched
for later response. During the Halt state Q and E should
continue to run normally. A halted state (BA • BS = I) can be
achieved by pulling HALT "Low" while RES is still "Low". See
Figure 8.
Bus Available, Bus Status (BA, BS)
The Bus Available output is an indication of an internal
control signal which makes the MOS buses of the MPU high
impedance. When BA goes "Low", a dead cycle will elapse before
the MPU acquires the bus. BA will not be asserted when TSC
is active, thus allowing dead cycle consistency.
•
The Bus Status output signal, when decoded with BA,
represents the MPU state (valid with leading edge of Q).
Data Bill (Do - 0 7 )
These eight pins provide communication with the system
bi-directional data bus. Each pin will drive one Schottky TIL
load or four LS TTL loads, and 130 pF.
•
MPU State
• ReadlWrite (R/W)
This signal indicates the direction of data transfer on the
data bus. A "Low" indicates that the MPU is writing data onto
the data bus. R/W is made high impedance when BA is "High"
or when TSC is asserted. Refer to Figures 1 and 2.
•
RES
A "Low" level on this Schmitt -trigger input for greater than
one bus cycle will reset the MPU, as shown in Figure 7. The
Reset vectors are fetched from locations FFFEI6 and FFFF ••
(Table 1) when Interrupt Acknowledge is true, (BA - BS = I).
During initial power-on, the Reset line should be held "Low"
until the clock input signals are fully operational.
Because the HD6809E Reset pin has a Schmitt-trigger input
with a threshold voltage higher than that of standard peripherals,
a simple RIC network may be used to reset the en tire system.
BA
BS
o
o
0
MPU State Definition
Normal (Running)
1
Interrupt or RESET Acknowledge
o
SYNC Acknowledge
HALT Acknowledge
Interrupt Acknow1ed~ indicated durin~th cycles of a
hardware-vector-fetch (RES, NMI, FIRQ, IRQ, SWI, SWl2,
SWI3). This signal, plus decoding of the lower four address
lines, can provide the user with an indication of which interrupt
level is being serviced and allow vectoring by device. See Table
1.
Sync Acknowledge is indicated while the MPU is waiting
for external synchronization on an interrupt line.
Halt Acknowledge is indicated when the HD6809E is in a
Halt condition.
~HITACHI
406
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
:z:
s=
n
:<.
»
3
'"n
:0.
!"
r-
Ei
•
E
:E
Sn
:<.
a
-c
~
R3
'"•
0'"
0
Address
0
~.
iil
-C
:I
_
Q.
~
Data
R/W
~
~
BA
\\\m\\\
$:I
BS
;:a
-CO
•
CO
New PCH New PCL \7MA 1st Opcode
.
~
New PCH New PCL I7liIIA
:r:
t1
AVMA
:0.
'"
'"
.'"n
c:r
CJ)
BUSY
CO
o(0
:::l
LIC
tt:l
»
CD
.I>-
0
0
9'
<»
<0
•
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High"
= V IHmin and logic "Low" =: V ILmax unless otherwise specified.
:r:
t1
CJ)
Figure 7
RES Timing
CO
:t>
~
o(0
(J1
tt:l
EJ
00
to>
:r:
0
CJ)
..j:>
o(0
'f'
00
0
t1
CO
tJj
0
-...J
tt:l
:r:
.p.
o
t1
OJ
0)
CO
o
~
CD
<;;
t:t:l
C">
:::r
:r:
:.3
ct>
"'.
Halted
Halted
C")
",
CO
:t:O
~
CL
•
::r:
CD
Q
:::+
'"='-
t:t:l
C">
E
:r:
HALT
CO
tJj
-0
~
•
<=>
<=>
a
~~
;;l
-0 J:
_
~ ~
":J?C)
•
co
"'.
en
0-
t1
0)
N
~
J:
o
CD
lTj
Address
Bus
Fetch
Execute
R/W
BA
BS
----------~/...
_ _ _ _ _ _ _~/...
\
/
\
jr-----
~
co
C":l
:.-
!)ata
BUI
Instruction
Opcode
~
<=>
~
~
AVMA
~'"
-.;;:
~
Lie
I'"
t1
0)
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High" -= V IHmin and logic "Low" - V I Lm8X unless otherwise specified.
Figure 8 HALT and Single Instruction Execution for System Debug
HD6809E, HD68A09E, HD68B09E
• Non Maskable Interrupt (NMIl*
A negative transition on this mput requests that a nonmaskable interrupt sequence be generated. A non-maskable
interrupt cannot be inhibited by the program, and also has a
higher priority than FIRQ, IRQ or software interrupts. During
recognition of an NMI, the entire machine state is saved on
the hardware stack. After reset, an ~ will not be recognized
until the first program load of the Hardware Stack Pointer (S).
The pulse width of NMI low must be at least one E cycle. If
the NMI mput does not meet the minimum set up with respect
to Q, the interrupt will not be recognized until the next cycle.
See Figure 9.
of a double-byte operation (e.g., LDX, STD, ADDD). Busy is
also "High" during the first byte of any indirect or other vector
fetch (e.g., jump extended, SWI indirect etc.).
In a multi-processor system, busy mdicates the need to
defer the rearbitration of the next bus cycle to insure the
integrity of the above operations. This difference provides the
indivisible memory access required for a "test-and-set" primitive, using anyone of several read-modify-write instructions.
Busy does not become active during PSH or PUL operations.
A typical read-modify-write instruction (ASL) is shown in
Figure 12. Timing information is given in Figure 13. Busy is
valid tCD after the rising edge of Q.
• Fast-Interrupt Request (FIRO)*
A "Low" level on this input pin will initiate a fast interrupt
sequence, provided its mask bit (F) in the CC is clear. This
sequence has priority over the standard Interrupt Request
(IRQ), and is fast in the sense that it stacks only the contents
of the condition code register and the program counter. The
interrupt service routine should clear the source of the interrupt
before dOIng an RTI. See Figure 10.
• AVMA
AVMA is the Advanced VMA signal and indicates that the
MPU will use the bus in the following bus cycle. The predictive
nature of the AVMA signal allows efficient shared-bus multiprocessor systems. AVMA is "Low" when the MPU is in either a
HALT or SYNC state. AVMA is valid tCD after the riSing edge
ofQ.
• Interrupt Request (lRO)*
A "Low" level input on this pin will initiate an Interrupt
Request sequence provided the mask bit (I) in the CC is clear.
Since IRQ stacks the entire machine state it provides a slower
response to interrupts than FIRQ. IRQ also has a lower priority
than FIRQ. Again, the interrupt service routine should clear
the source of the interrupt before doing an RTI. See Figure 9.
• LIC
LIC (Last Instruction Cycle) is "High" during the last cycle
of every instruction, and its transition from "High" to "Low"
will indicate that the frrst byte of an opcode will be latched at
the end of the present bus cycle. LIC will be "High" when the
MPU is Halted at the end of an instruction, (i.e., not in CWAI or
RESET) in SYNC state or while stacking during interrupts.
LIC is valid tCD after the rising edge of Q.
•
NMT, FIRQ, and IR<:l requests are sampled on the falhng edge of Q.
One cycle IS required for synchromzatton before these Interrupts are
recogmzed The pending interrupt(s) will not be serviced untIl
complehon of the current instructton unless a SYNC or CW AI
condition is present. If IRQ and FIRQ do not remain "Low" until
completlOn of the current instruCtion they may not be recognized.
However. NMI IS latched and need only rem am "Low" for one cycle.
• Clock Inputs E, a
E and Q are the clock signals required by the HD6809E.
Q must lead E; that is, a transition on Q must be followed by a
similar transition on E after a minimum delay. Addresses will
be valtd from the MPU, tAD after the falling edge of E, and
data will be latched from the bus by the falling edge of E.
While the Q mput is fully TTL compatible, the E input directly
drives internal MOS circuitry and, thus, requires levels above
normal TTL levels. This approach minimizes clock skew
inherent with an internal buffer. Timing and waveforms for E
and Q are shown in Figures I and 2 while Figure II shows a
simple clock generator for the HD6809E.
• BUSY
Busy will be "High" for the read and modify cycles of a readmodify-write instructton and during the access of the first byte
• TSC
TSC (Three-State Control) will cause MOS address, data,
and R/W buffers to assume a high-impedance state. The control
signals (BA, BS, BUSY, AVMA and LIC) will not go to the
high-impedance state_ TSC is intended to allow a single bus to
be shared with other bus masters (processors or DMA controllers).
While E is "Low", TSC controls the address buffers and R/W
directly. The data bus buffers during a write operation are in a
high-impedance state until Q rises at which time, if TSC is
true, they will remain in a high-impedance state. If TSC is held
beyond the rising edge of E, then it will be internally latched,
keeping the bus drivers in a high-impedance state for the
remainder of the bus cycle. See Figure 14.
• MPU Operation
During normal operation, tlte MPU fetches an instruction
from memory and then executes the requested function. This
sequence begins after RES and is repeated indefinitely unless
altered by a special instruction or hardware occurrence. Software instructions that alter normal MPU operation are: SWI,
SWI2, SWI3, CWAI, RTI and SYNC. An interrupt or HALT
input can also alter the normal execution of instructions.
Figure IS illustrates the flow chart for the HD6809E.
~HITACHI
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
409
o
::r:
o0'>
:c
o
.j:>.
(Xl
CD
~
;::;:
'"'2:"'
::r:
o0'>
:t>
:3
LastCycl.
~
n"
of Current
Instruction
Instruction
?'
Fetch
1- -I·
r-
8.
. m-2, m-l,
•
I'
~
m
I m+l
m+2
m+3
1
,1 .
I
m+5 m+6 1 m+7 m+8
1
,.
I
.
'1
m+4
m+9 m+l0,m+ll(+12 m+13 m+14 m+15 m+16m+17Im+18
I' I
'
,
(Xl
-I- -I
Interrupt Stacking and Vector Fetch Sequence
I
I
1"1
I"
-I"
n
"+1
I'
~
-I
E
'"
::.
C")
~
•
(Xl
IJj
N
<=>
<=>
<=>
W~
iil-0 :I
_
~~
;gC')
~ :I
•
co
o
iRCI or
NMI
D~
__~__-J~__A-__~__-J~__~__-A__~~__~__~~~~__~__~~__~__~__-'~-J~__/~__~~__-J~__J~__~,__~.~__~
UH
Xl
I7MA PCl PCH
UL
DP
R/W
-:r:::::::c::::
BA
:x:::::x::::J.
,
I
BS:x:::::x::::J.~------------------------------------------------I;====~'-----------
~
---..r---v--v--
Q)
:::l
(1)
~
2
25
AVMA
BUSY -A-..-JI.......
:::::).
LlC
r-\
I
E
'f'
0;
<:C
•
~
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High"
E clock shown for reference only.
= V1Hmin and logic "Low" = VILn'IIIx
~
t11
CD
'P
CD
w
25
CD
~
::r:
o
0'>
Q
-0
o
Figure 9 IRQ and Nm Interrupt Timing
unless otherwise specified.
c::.
, _ _ __
CD
~
last Cycle
of Current
Instruction
~
I·
~
2:
l. m - 2
»
3
'"::!.
~
c.
;:;:
C">
Address
Bus
&j
•
§
W~
m
1
m+1
1
1
m+2
m+3
1 m+4' 1 m+5' 1 m+6
1
m+7
I
m+B
1
m+9
1
n
1
n+1
~~~~~~r-----\.r-----\.~r-----\.
VIL~~~~~
t~Cf ~
""0
;;;
N
I.
_I
o
•
'"2:
Fetch
'1
E
$l
I
1 m-1
Instruction
Interrupt Stacking and Vector Fetch Sequence
FIRO
PC
PC
FFFF
SP-1
SP-2
$FFFF
SP-3
$FFF6
$FFF7
$FFFF
New PC New PC+ 1
'pcs
V1H
Data ---"-----J'-----"----I
@
""0 :I
_
PCl
PCH
CC
VMA
New PCH
New PCl
9. ~
~)i
s
""0(,,)
~
"'" :I
•
!:Ii'
en·
BA
0)
CO
o(0
0-
'"::>
BS
'"
I:%j
(")
»
AVMA
«>
c=...
.l>-
e
e
'{'
~
BUSY
cO
•
LlC
~
~
E
==:A
/\
~
\~_ __
8
CO
;J>
o(0
::r:
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High" - VIHmin and logic "Low" .. VILmax unless otherwise specified.
E clock shown for reference only.
Figure 10 FIRQ Interrupt Timing
~
0)
I:%j
(J1
co
'P
co
w
S
t:I
0)
CO
t::Jj
o
(0
I:%j
HD6809E, HD68A09E, HD68B09E
I
I
I
I
-------------------,
I
I
I
I
Optional
MRDY CirCUit
IMRD
I
I
I
I
I
I
I
_ _ _ JI
L ___ _
,---f---------= a to System and proceuor
If.!'~----"",,",,,,,,,,,,= E to System
6800
+5V
NOTE
4xfo
If optional circUit IS not Included the CLR and PRE
Inputs of U2 and U3 must be tied high.
a
MAOY
STRETCH - - - - - - - - - - . /
Figure 11 HD6809E Clock Generator
Memory
Memory
Location
Contents
PC ... $0200
$68
ASL Indexed Opcode
$0201
$9F
Extended Indirect Postbyte
$0202
$63
Indirect Address Hi-Byte
$0203
$00
--
Contents DesCription
Indirect Address Lo-Byte
Next Main Instruction
$0204
L---
---
$63oo~
$6301~
Effective Address Hi-Byte
Effective Address Lo-Byte
Figure 12 Read Modify Write Instruction Example (ASL Extended Indirect)
~HITACHI
412
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
Last Cycle of
Current Instr.
I• m-l
::c
;::+
m
m+2
I•
$0201
$0202
$0203
X
X
m+3
• I•
m+4
m+ 8
m+9
1
··
1m+l0
"I
m+5
m+6
m+7
$FFFF
$6300
$6301
$FFFF
$E3D6
$FFFF
$E3D6
X
X
X
X
X
X
X
·1·
I
n
E
'"2:
C>
a
>-
3
'"
'"
Address
::l,
C>
$0200
r-
X~--c::::J.
Data
et
•
;;!;
RiW
S
n
2:
BUSY
-u
~
•
LIC
$68
:::::x
$9F
$63
$00
VMA
$E3
$06
VMA
$5C
y
A
__~I
VMA
I
\
I
X~-$88
\
\
$0203
,""--\~==~
I
\~
__
__
AVMA _ _ _oJV
""
~~:I
~ _
-u
2,
~
I m+l
.
. I•
E
(NOTE)
Waveform measurements for all inputs and outputs are specified at logic "High"'" VIHmin and logic "Low" .. VILmax unless otherwise specified.
:-I
):Ii
~O
Figure 13 BUSY Timing (ASL Extended Indirect Instruction)
~ :I
::r::
•
""
en
t1
(j)
'"
'"
o
::l,
CO
<:T
::::l
CD
t:J::I
(")
>-
*
::r::
o
t1
'f'
(j)
~
CO
<0
~
o
~
CD
~
t:J::I
CJl
00
::r::
(L)
clo
w
t1
o
o
(j)
(NOTES) Data will be ....rted by the MPU only during the intarval while R/Wis "Low" and E or a is "High",
Waveform measurements for all inputs and outputs are specified at logic "High" • V IHmin and logic "Low" • V I Lmex unless otherwise specified.
.j:>.
tv
'figure 14 TSC Timing
CO
tIl
o
CD
t:J::I
::r:
.j:>.
o
en
rtml·,.
.j:>.
00
o
:J:
<0
g
t%j
n
;;;:
::r:
o
en
[t>-+[ji>R
l-F,I
:t>
3
:::!.
CD
l-RJIV
Clr flMr
~
DisarmWf
~k
£
a
00
~
o
•
:J:
<0
t%j
~.
::r:
;;;:
o
en
-0
~
•
00
tx:I
§'"
o
<0
~.
iil
t%j
J:
~
a;
~(")
.;§ J:
•
en
:::I.
et>
0"
.'"'"
:::I
c->
:t>
~
00
<0
•
HD6809E Interrupt Structure
~
EJ
~
Co
c.:>
o
o
Bus State
SA
BS
!
0
1
I
Interrupt or Reset Acknowledge
Sync Acknowledge
0
0
1
0
I
Halt Acknowledge
1
1.~
Running
01
(NOTES) 1. AssertIng RES will ,esull in ent.,ing the reset
sequence from any point in the flow chart.
2. BUSY is "High" during first vector fetch cycle.
Figure 15 Flowchart for HD6809E Instruction
I
HD6809E, HD68A09E, HD68B09E
• ADDRESSING MODES
•
The basic instructions of any computer are greatly enhanced
by the presence of powerful addreSSing modes. The HD6809E
has the most complete set of addressing modes available on
any microcomputer today. For example, the HD6809E has 59
basic instructions; however, it recognizes 1464 different varia·
tions of instructions and addressing modes. The addressing
modes support modern programming techniques. The following
addressing modes are available on the HD6809E:
(I) Implied (Includes Accumulator)
(2) Immediate
(3) Extended
(4) Extended Indirect
(5) Direct
(6) Register
(7) Indexed
Zero-Offset
Constant Offset
Accumulator Offset
Auto Increment/Decrement
(8) Indexed Indirect
(9) Relative
(10) Program Counter Relative
Direct addressing is similar to extended addressing except
that only one byte of address follows the opcode. This byte
specifies the lower 8 bits of the address to be used. The upper
8 bits of the addres. are supplied by the direct page register.
Since only one byte of address is required in direct addressing,
this mode requires less memory and executes faster than
extended addressing. Of course, only 256 locations (one page)
can be accessed without redefining the contents of the DP
register. Since the DP register is set to $00 on Reset, direct
addressing on the HD6809E is compatible with direct addressing
on the HD68oo. Indirection is not allowed in direct addressing.
Some examples of direct addressing are:
LOA
$30
(Assembler directive)
SETDP $10
LOB
$1030
LOD
.
N
o
en
00
o
CO
;;;
I:::r:j
~
::.
»
Last Cycle
Sync
of Previous Opcode
,Instruction, Fetch ,Execute
. . ,
•
3
'"2=i"
'"
a
•
S
en
Last Cvcle
of Sync
• ,lnstructiO!)
Sync Acknowledge
"
00
»
o
E
CO
I:::r:j
;;;
~
::.
Q
-0
~
Addreu
8o
Data
•
~~
;;l
-0
1:
_
~' ~
~o
~ J:
•
!:!i'
eC")
»
....o
to
o
Rm~
BA~
BS~
LIC
\
~
/
\
i
I:::r:j
\L__________________
~
I
\ . ,
.,'
"
..
~ --------------------------------~.
NMI
~
CO
I
".
AVMA~
:::>
'"
en
00
tx::t
--y--y
C:;;'
'"
:r:
tj
~1I-ftPCf
'{
See Note 1
Vm~~~il---=See~N=0=te~2--------------------------V 1L r~~
o
'f'
~
co
•
~
~
'P
0:>
W
o
o
(NOTES) 1, If the associated m.k bit is set when the interrupt is ~ested. LIC will go "Low" and this cycle will be an instruction fetch from address
location PC + 1. However, if the interrupt is accepted CNMT or an unmasked FT"R"Q or fRll) LIC will remain "High" and interrupt processing
will start with this cycle as fm) o~re 9 and 10 (Interrupt Timing).
2. If mask bits are clear, 1lRl and FIRQ must be held "Low" for three cycles to guarantee that interrupt will be taken, although only one cycle
is necessery to bring the processor out of SYNC,
3. Waveform measurements for all inputs and outputs are specified at logic "High". V1Hmin and logic "Low" = VeL-max unless otherwise
specified,
Figure 17 SYNC Timing
C!7)
Opcode (Fetch)
:::t:
~:
=r.
l>
3
co
::!.
co
1"
Short
Long
Branch
Branch
.--
r-
8:
Immediate and
Implied
Indexed
•
:::t:
~
=r.
-0
~
•
N
Auto
Auto
Opcode +
Inc/Oec Inc/Dec
R + 16 Bits
R+0
byl
by2
I
Opcode +
;:::;:
lIMA
O~r+
_I
VMA
VMA
g
Offset
ACCA
ACCB
R + 5 Bit
R + 8 Bit
PC+8Bit
Opcode + Opcode +
VMA
W~
~
-0 :I
_
~~
I
VMA
VMA
VMA
I
VMA
VMA
I
VMA
VMA
VMA
VMA
I
lIMA
I
I
I
lIMA
I
~(')
g'
en-
N
cco
VMA
V~A
VMA
CO
CD
tlj
I
(")
l>
::r:
Stack Write
I
Stack Write
'oE.
o
t1
(j)
'f'
CO
~
:x>
o
<0
•
CD
~
£!
tlj
VMA
en
00
<0
N
O~Iode +
o
VMA
I
::::>
.p.
V¥A
VMA
No
Offset
(j)
D>
o
o
jode +
lIMA
.
Extended
Indirect
t1
•
W
,
::r:
~ :I
Co
PC +
16 Bits
::r:
t1
(NOTE)
(j)
1. Busy"" "High" during access of first byte of double byte immediate load.
2. Write operation during store instruction. Busy = "High" during first two cycles of a double-byte access and the first cycle of read-modify;ovrite access.
CO
3
o
AVMA
15
asserted on the cycle before a VNlA cvcle.
Figure 18 Address 8us Cycle-by.cycle Performance
tx:l
CD
tlj
::r:
~
I\.)
I\.)
t:l
0)
ex>
o
::z::
s:
CD
Implied Page
~
C")
~
»
3
CD
=>.
C")
}"
r-
a
•
;;;
or
C")
~
"tl
~
'"•
0
""
0
w..
0
"tl J:
_
~
2. :-I
;a
»
"tlC')
~J:
•
C::J
=>.
U>
C"
'"
:::l
-'"
n
»
co
.j>.
0
0
'f'
~
<0
•
ASLA
ASLB
ASRA
ASRB
CLRA
CLRB
COMA
COMB
DAA
DECA
DECB
INCA
INCB
LSLA
LSLB
LSRA
LSRB
NEGA
NEGB
NOP
ROLA
ROLB
RORA
RORB
SEX
TSTA
TSTB
ABX
RTSI
TFR
EXG
MUL
PSHU
PSHS
SWI
SW12·
SWl3
PULU
PULS
::r:
RTI
CWAI
t:l
0)
ex>
VMA
VMA
WA
iiMA
VMA
STACK (RI
STACK (RI
VMA
ADDR
WAA
VMA
VMA
WAA
WA
i7filA
WA
WA
VMA
VMA
VMA
WAA
i7filA
WA
VMA
i7filA
WA
WA
I
vk
vrk
I
STACK (WI
ADDR +-SP
STACK (WI
STACK (WI
STACK (WI
{Stack (WI)',2
STACK (WI
0
STACK (WI
(Note 31
STACK(WI
{StOCk (RI) ',2 STACK (WI
(Note 31 0 STACK (WI
STACK(WI
STACK (WI
STACK (WI
t
I
I
I
I
ADOR +- SP
~
I
::r:
STACK (WI
STACK (WI
STACK (WI
STACK (WI
STACK (WI
STACK (WI
STACK(WI
STACK (WI
STACK (WI
STACK(WI
STACK (WI
STACK (WI
WA
I
I
I
t:l
0)
E~
?
o
STACK (R)
STACK (R)
00
VMA ;
(Not. 41
VECTOR (HI, VECTOR (HI,
BUSY +-1
BUSY +-1
VECTOR (LI, VECTOR (LI,
BUSY+- 0
BUSY +-0
VJ.1A
I
i7MA
!
!
ADDR+-SP
I
~
CJ1
00
w
0
0
CD
i7QA
~
co
co
~
STACKIRI
(NOTESI
1. Stack (WI refers to the following sequence: SP +- SP - 1, then AD DR +- SP with Riw - "Low"
Stack (RI refers to the following sequence: ADDR +- SP with R/W ~ "High", then SP +-SP + 1.
PSHU, PULU instructions use the user stack pointer (i.e., SP = UI and PSHS, PULS use the hardwere stack pointer (i.e., SP
2. Vector refen to the address of an interrupt or reset vector (see Table 1).
3. The number of stack accesses will vary according to the number of bytes saved.
4. VMA cycles will occur until an interrupt occurs.
Figure 18 Address Bus Cycle-by.cycle Performance (Continued)
=SI.
STACK (RI
STACK (RI
STACK (RI
STACK IRI
STACK (RI
STACK (RI
STACK {RI
STACK(RI
STACKIRI
STACK (RI
STACK (RI
ex>
t:d
I~
HD6809E, HD68A09E, HD68B09E
Non- Implied
AOCA
AoCB
AooA
AooB
ANoA
ANoB
BITA
BITB
CMPA
CMPB
EORA
EORB
LOA
LOB
ORA
ORB
SBCA
SBCB
STA
STB
SUBA
SUBB
LOO
LOS
LOU
LOX
LOY
ASL
ASR
CLR
COM
DEC
INC
LSL
LSR
NEG
ROL
ROR
ANoCC
ORCC
AD DO
CMPo
CMPS
CMPU
CMPX
CMPY
SUBo
TST
(NOTESI
1 Slack (W) refers to Ihe following sequence SP <-- SP - 1,
then ADDR <-- SP with R/Vi = "Low"
St~k (R) refers to the following sequence ADDR <-- with
RIW = "High", then SP <-- SP + 1
PSHU, PULU Instructions use the user stack pointer (I.e.,
SP = U) and PSHS, PULS use the hardware stack pOinter
(I.e., SP = S)
2. Vector refers to the address of an Interrupt or reset vector
(see Tabte 1)
3 The number of stack accesses will vary according to the
number of bytes saved.
4 VMA cycles will occur until an Interrupt occurs.
VMA
STACK (WI
STACK (WI
VMA.BUSY.-,
AOoR+
BUSY'-O
AooR+
STo
STS
STU
STX
STY
JSR
AD OR +
VIR
VMA
I
VIR
AooR + (WI
Figure 18 Address Bus Cycle-by-Cycle Performance (Continued)
Table 4 8-Bit Accumulator and Memory Instructions
Mnemonic(s)
AOCA,AOCB
AOOA,AOOB
ANOA,ANOB
ASL,ASLA,ASLB
ASR, ASRA, ASRB
BITA,BITB
CLR,CLRA,CLRB
CMPA,CMPB
COM, COMA, COMB
OM
OEC,OECA,OECB
EORA,EORB
EXG R1, R2
INC, INCA, INCB
LOA, LOB
LSL, LSLA, LSLB
Operation
Add memory to accumulator with carry
Add memory to accumulator
And memory with accumulator
Arithmetic shift of accumulator or memory left
Arithmetic shift of accumuletor or memory right
Bit test memory with accumuletor
Clear accumulator cw memory location
Compere memory from accumulator
Complement accumultor or memory location
Decimal adjust A accumulator
Decrement accumulator or memory location
Exclusive or memory with accumulator
Exchange R1 with R2 (R1. R2 =A, B, ce, OPI
Increment accumulator or memory location
Load accumulator from memory
Logical shift left accumulator or memory location
(Continued)
$
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
423
HD6809E, HD68A09E, HD68B09E
Table 4 8·8it Accumulator and Memory Instructions (Continued)
Operation
Mnemonic(s)
LSR, LSRA, LSRB
MUL
NEG, NEGA, NEGB
ORA,ORB
Logical shift right accumulator or memory location
Unsigned multiply (A x 8 ..... O)
Negate accumulator or memory
ROL, ROLA, ROLB
ROR, RORA, RORB
Or memory with accumulator
Rotate accumulator or memory left
Rotate accumulator or memory right
SaCA, SBCB
STA,STB
SUBA, SUBB
TST, TSTA, TSTB
TFR R1, R2
Subtract memory from accumulator with borrow
Store accumulator to memory
Subtract memory from accumulator
Test accumulator or memory location
Transfer R1 to R2 (R1, R2 =A, B, CC, OP)
---~
.
-
INOTEI A, B, CC or OP may be pushed to Ipulled froml either stack with PSHS, PSHU
IPULS, PULUI,nstructlons.
Table 5 16·Bit Accumulator and Memory Instructions
Mnemonich}
AD DO
CMPO
EXG 0, R
LOO
SEX
STD
SUBO
TFR 0, R
TFR R,O
Operation
Add memory to 0 accumulator
Compere memory from 0 accumulator
Exchange 0 with X, Y, S, U or PC
Load 0 accumulator from memory
Sign Extend a accumulator into A accumulator
Store 0 accumulator to memory
Subtract memory from 0 accumulator
Transfer 0 to X, Y, S, U or PC
Transfer X, Y, S, U or PC to 0
-----
(NOTE) 0 may be pushed lputledl to either stack with PSHS, PSHU (PULS, PULUI
instructions.
Table 6 Index Register Stack Pointer Instructions
Mnemonic(s)
CMPS,CMPU
CMPX,CMPY
EXG R1, R2
LEAS, LEAU
LEAX,LEAY
LOS, LOU
LOX, LOY
PSHS
PSHU
PULS
PULU
STS,STU
STX,STY
,
TFR Rl, R2
ABX
Operation
Compare memory from stack pointer
..
Compare memory from index register
Exchange 0, X, Y, S, U or PC with 0, X, Y, S, U or PC
Load effective address into stack pointer
Load effective address into index register
Load stack pointer from memory
Load index register from memory
Push A, B, CC, OP, D, X, Y, U, or PC onto hardware stack
---Push A, B, CC, DP, 0, X, Y, S, or PC onto user stack
-,_. ..- - - _ . _ - - Pull A, B, CC, OP, 0, X, Y, U or PC from hardware stack
Pull A, B, CC, OP, 0, X, Y, S or PC from user stack
Store stack pointer to memory
Store index register to memory
Transfer D, X, Y, S, U or PC to 0, X, Y, S, U or PC
Add B accumulator to X (unsigned)
~HITACHI
424
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300
HD6809E, HD68A09E, HD68B09E
Table 7 Branch Instructions
Mnemonic(s)
BEQ, LBEQ
BNE, LBNE
BMI, LBMI
BPL,LBPL
BCS,LBCS
BCC, LBCC
BVS, LBVS
BVC, LBVC
BGT, LBGT
BGE, LBGE
BEQ, LBEQ
Operation
SIMPLE BRANCHES
Branch if equal
Branch if not equal
Branch if minus
Branch if plus
Bra nch if carry set
Branch if carry clear
Branch if overflow set
Branch if overflow clear
SIGNED BRANCHES
Branch if greater (signed)
Branch if greater than or equal (signed)
BLT,LBLT
Branch if equal
Branch if less than or equal (signed)
Branch if less than (signed)
BHI, LBHI
UNSIGNED BRANCHES
Branch if higher (unsigned)
BLE,LBLE
BLS, LBLS
Branch if higher or same (unsigned)
Branch if equal
Branch if lower or same (unsigned)
BLO,LBLO
Branch if lower (unsigned)
BSR,LBSR
BRA, LBRA
OTHER BRANCHES
Branch to subroutine
Branch always
BRN, LBRN
Branch never
BHS,LBHS
BEQ,LBEQ
Table 8 Miscellaneous Instructions
Operation
Mnemonic(s)
ANDCC
CWAI
NOP
ORCC
JMP
JSR
RTI
RTS
SWI, SW12, SWl3
SYNC
AND condition code register
AND condition code register, then wait for interrupt
No operation
OR condition code register
Jump
Jump to subroutine
Return from interrupt
Return from subroutine
Software interrupt (absolute indirect)
Synchronize with interrupt line
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
425
HD6809E, HD68A09E, HD68B09E
Table 9. HD6309E Instruction Set Table
INSTRUCTIONS/
FORMS
ABX
ADC
ADD
AND
ASL
ASR
IMP
ACCM REG
OP -
#
3A 3
I
ADCA
ADCB
ADDA
ADDB
ADDD
ANOA
ANDB
ANDCC
DIRECT
OP -
48 2
58 2
ASRA
ASRB
ASR
47 2
57 2
EXTND
OP
#
IMMED
OP -
#
INDEX(j) RELATIVE
OP -
#
4
4
4
4
6
4
4
2
2
2
2
2
2
2
89
F9
B8
FB
F3
84
F4
5
5
5
5
7
5
5
3
3
3
3
3
3
3
89
C9
88
CB
C3
84
C4
IC
2 A9 4 +
2 E9 4+
2 A8 4 +
2 EB 4 +
3 E3 6+
2 A4 4 +
2 E4 4+
2
2
2
2
4
2
2
3
8+M+C---B
2+
2+
A+M ...... A
B+M-B
2+
2+
2+
BEQ
BGE
BGT
BHS
CCAIMM~CC
I
I
08 6
2 78
7
68 6 + 2+
3
M
I
I
C
b,
A}
07 6
2 77
7
67 6 + 2+
3
BCC
LBCC
24 3
2
10 516! 4
BCS
LBCS
25 3
2
25
27 3
BW
• BLS
2
10 5(6) 4
27
2C 3
BGE
LBGE
2
10 5(6) 4
2C
2E 3
BGT
LBGT
BHI
LBHI
2
.
b,
_
10 516! 4
I~:
4
4
2 B5 5
2 F5 5
8MI
BLS
BLT
LBLT
"'----
1
C~
I
Z~ I
Branch
Long Branch
Z~ I
Branch
N(i)V~O
Long Branch
Branch
ZV(NElN) - 0
Long Branch
0
CvZ~O
Branch
Long Branch
CVZ~O
Branch
C~O
Long Branch
Branch
ZVIN!BV)o I
Long Branch
Co I
Branch
10 5(6) 4
Long Branch
25
23 3
Branch
C:oI
2
Cv Z ~ I
10 5(6) 4
Long Branch
23
20 3
Branch
20
28 3
I
Branch
Long Branch
ZV(N(i)V)~1
2
Cv Z
2
10 5(6) 4
BMI
LBMI
I
I
2
10 5(6) 4
2B
I
I
I
I
I
I
I
I
I
I
R
R
I
I
I
I
I
)
I8l
I8l
I8l
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
C~O
Bit Test B (MAB)
2F
25 3
I
I
0
C
Long Branch
Bit Test A (MI\A)
2F 3 2
10 5(6) 4
BW
LBW
Branch
C
CoO
2 A 5 -4 + 2 +
2 E 5 4 + 2+
3 85 2
3 C5 2
bet
ZVIN(i)V)~
22 3 2
10 516) 4
22
24 3 2
BHS
I
I
I
I
I
I
I
I8l
I8l
I8l
N(i)V~O
10 516! 4
LBLS
BLT
I
V
I
C~I
24
BLE
2
Z
C~O
10 5(6) 4
BEQ
LBEQ
BITA
BITB
BLE
LBLE
3
N
I
8AM~8
2
LBHS
BIT
4
I
I
I
I
AAM~A
n
BHI
5
H
O+MM+l--+D
24
BCS
6
F
••••••••
•• •• ••
•• •• ••
•• •• •• ••
••
• r-• -IJJ
••
••
: } ~ I fDTlll-o •• •
•
•• •
•• • •
! Q'IIIIIII~ •• •• •• ••
•• •• •• •• •• •• •• ••
(UNSIGNED>
A+M+C ...... A
2+
2+
br
BCC
7
E
DESCRIPTION
OP -@ #
B+X-X
99
D9
9B
DB
03
94
04
ASLA
ASLB
ASL
#
I
N(.)V
Long Branch
N8)V ~ I
0
Branch
N'I
Long Branch
No 1
0
I
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
••••••••
••••••••
•• •• •• ••
••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
••••••••
••••••••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
I
I
I
I
R
R
(Continued)
~HITACHI
426
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD6809E, HD68A09E, HD68B09E
INSTRUCTIONSI
FORMS
BNt:
BI'L
BNA
BNN
II.~N
Al.U::
op -
~ ..;(. DIMF£T
#
lop -
#
EXTND
op -
#
IMMED
op -
INDEXeD RELATIVE
# OP -@ #
DESCRIPTION
# OP -
BNt:
LBNE
26 3..12
10 5161 4
26
2A 3
BI'L
LBI'L
Branch
Z ,- 0
Long Branch
Z-O
2
10 5(6) 4
Branch
N-O
Long Branch
BNA
LBNA
BMN
LIIHN
2A
20
16
21
10
21
3
5
3
S
2
3
2
4
Branch Always
Long Branch Always
Branch Never
Long Branch Never
85M
80 7
2
Branch to
L85N
17 9
3
Long Branch to
IIVC
LIIVC
28
10
28
29
10
29
N~O
Subroutine
Subroutine
IIVC
BVS
CLM
eMI'
IIVS
LIIVS
CLNA
CLMII
CLN
CMPA
CMI'II
CMPD
4F 2
SF 2
OF
9I
III
10
93
II
9C
II
93
9C
CMI'U
CMI'X
CMI'V
COMA
COMB
COM
6
4
4
7
7
7
6
10 7
9C
43 2
53 2
2
2
2
3
7F 7
7
6F 6+
2 AI 4 +
2 EI 4+
4 10 7 +
A3
4 I 1 7+
AC
4 11 7+
A3
3 AC 6 +
3 10 8
BC
4 10 5
HC
4 10 7 + 3 +
AC
5
5
8
8
8
EON
EXG
INC
IMI'
ISH
2+
2 73 7
63 6 + 2+
3
~2
2
I
I
I
OA 6
98 4
08 4
IE 8
4C 2
SC 2
3+
Branch
V~I
Long Branch
V~I
O-A
O-B
O-M
Compare M from A
Compare M from B
Compare M M+ 1
from D
Compare M M + 1
from S
Compare M M + 1
from U
Compare M M t 1
from X
Compare M M + 1
from V
ii-s
03 6
19 2
4A 2
SA 2
3+
I
I
3C
DECA
DECS
DEC
EONA
EOHB
HI. H2
INCA
INCB
INC
V~O
Long Branch
X-A
CWAI
DAA
DEC
2+
2+
2+
3+
3
3 8I 2
3 CI 2
4 10 5
83
4 II 5
8C
4 II 5
83
3 HC 4
III
FI
10
113
3 II
IIC
3 II
113
2 BC
Branch
V~O
3 2
5161 4
I
I
CMI'S
COM
3 2
5161 4
2 lA 7
2 118 5
2 FH 5
3
3 88 2
3 C8 2
6A 6 + 2+
2 A8 4 + 2 +
2 E 8 4 + 2+
2
I
I
OC 6
OE 3
90 7
2 iC 1
2 j E 4
2 BO 8
6C 6 + 2+
6 E 3 + 2+
AD i + 2 +
3
3
3
M-M
CC /\ IMM-CC
Walt for Interrupt
Decimal AdJust A
A-I-A
B-I-B
M-I-M
A(i)M-A
B(i)M-B
RI-R2@
A+ I-A
B+ I-B
M+I-M
EA<3l-PC
Jump to Subroutine
7
E
6
F
5
H
4
I
3
N
2
Z
I
V
0
C
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
••••••••
••••••••
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• •• ••
•• •• •• ••
•• •• • ••
•• •• • ••
••••
••••
••••
••••
•• •• •• ••
••••
R
R
R
R
R
R
I
I
I
S
S
S
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
R
R
R
S
R
R
R
IBl
IBl
S
1 -r-
i7Jr- r-
S
S
I
•• •• •• ••
•• •• •• •• : •••
•• •• •• ••
••
Ii•
•• •• •• ••
•• •• •• •• • • • •••
••••••••
I
I
I
I
I
I
I
I
I
I
I
I
IBl I
I
I
I
I
I
I
I
I
I
I
I
R
R
-@
I
(Continued)
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
427
HD6809E, HD68A09E, HD68B09E
'"INSTRUCTIONSI
FORMS
lO
MP
AL(:M Rf.X.
OP -
#
lOA
lOB
lOD
lOS
lOU
lOX
LSL
IMMED
LSLA
LSRA
LSRB
LSR
INDEX(J) RELATIVE
or -
#
or -
# OP -
96
D6
DC
10
DE
2
2
2
3
B6
F6
FC
10
3
3
3
4
86
C6
CC
10
2 A6 4 + 2 +
2 E6 4+ 2+
3 EC 5 + 2 +
4 10 6 + 3 +
4
4
5
6
5
5
6
7
FE
2 FE 6
2 BE 6
3 10 7
BE
2
2
3
4
CE
3 C EI 3
3 8E 3
4 10 4
8E
LEAS
LEAU
LEAX
LEAY
LSLB
LSL
LSR
EXTND
#
DE 5
9E 5
10 6
9E
lOY
LEA
DIRECT
or -
#
or
EE
3 EE 5 + 2 +
3 AE 5 + 2 +
4 I {) 6 + 3 ~
AE
32 4 + 2 +
33 4 + 2 +
30 4 + 2 +
3 I 4+ 2+
48 2
58 2
1
1
54
2
2
2 78 7
3
68 6 + 2 +
1
1
1
04 6
3D 1I
I5
I fI
4
I
2 74
7
64 6 + 2 +
3
3
N
I
I
M M+ 1-0
I
V
MM+ 1--5
MM-"I"""'U
MM-t J---X
MM+ l--Y
I
I
I
I
I
I
R
R
R
R
I
I
I
I
I
I
R
R
0
C
R
EA(lJ~S
EA(lJ~U
EA(lJ~x
I
I
EA(lJ~Y
M
C b1
-
bo
b,
I
I
I
I
I
I
R
R
R
I
I
I
I
I
I
I
I
I
I
I
I
I
@
C
AXB-oD
1
2
Z
•• .!.
•
••
•• ••• ••• •••
••
•• •• •• ••
••
••••
•
•• •• •• •• •• •• •• ••
•• •• •• •• •• •• ••
A}
_
••••
[}U[[~O • • • •
••••
•• • •
~} o-{[[J]JI]-o{] •• •• ••• •• ••
••••• •
•• •• •
B
M+
•• •
•• •• •• ••• • • • ••
••••
•
••••••••
••••••••
M~A
M-'B
b,
MUL
6
F
B
08 6
44
7
E
DESCRIPTION
-is! #
(Unsigned)
NEG
NEGA
NEGB
40 2
50 2
1
1
NEG
NOP
OR
PSH
PUL
12
2
3 4 J~
r
2
PSHU
36"+1
2
35 ',.
2
37 "!
2
PULU
2 70
9A 4
DA 4
2 BA 5
2 FA 5
7
60 6
3
t-
2+
A + I-A
@
+ 1-8
I--M
@
I
I
@
I
I
I
I
I
I
I
I
R
R
I
I
I
No Operation
1
ORA
ORB
ORCC
PSHS
PULS
00 6
3 SA 2
3 CA 2
1A 3
2 AA 4 + 2 +
2 EA 4 + 2 +
AvM~A
I
I
BvM~B
CCV IMM-cC
Push Registers on
S Stack
Push RegIsters on
2
I
1 - -!J)
U Stack
Pull Registers
from S Stack
Pull Registers
I
1-
-®
I
1-
-®
)
from U Stack
ROL
ROR
ROLA
ROLS
ROL
49 2
59 2
RORA
46 2
56 2
RORS
ROR
1
1
09 6
2
79 7
69 61- 2 +
3
1
1
06 6
2 76
7
66 6 + 2 +
3
!}ttWIIIIIIID ••• ••• ••• •••
b,~bo
C
!} CamT11l riJ ••• ••• ••• •••
I
I
I
I
I
I
I
I
I
I
I
I
C b,--.b o
RTI
3B 115 1
Return from
RTS
39 5
Return from
(-
Interrupt
I
Subroutme
SBC
SEX
SBCA
SBeS
92 4
D2 4
)D 2
2 B2 5
2 F2 5
3 S2 2
3 C2 2
2 A 2 .. + 2 +
2 E 2 .. + 2 +
I
B"'~ ,f 7 ~ I
FF_A
B(1)l::/~7=O
O-A
••
•
I
I
I
)
••••••••
•• •• ••
•••• ••
@
Sign Extend B mto A
)
t
I
I
-iJJ
@
A-M-e-A
S-M-C-B
I
I
I
I
I
I
I
I
I
I
I
I
I
(Continued)
.HITACHI
428
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589,8300
HD6809E, HD68A09E, HD68B09E
INSTRUCTIONS!
FORMS
ST
EXTND
IMMED
A(;d~kEG DIRECT
• OP OP OP -
•
OP -
STA
97
STO
STD
07
4
4
00 5
10 6
OF
OF 5
9F 5
10 6
STS
STU
STX
STY
9F
SUB
SWI
•
2 07
5
3
2 F7 5
2 FO 6
3
3
3 10 7
4
FF
2 FF 6
2 OF 6
3
3
4
10 7
•
INDEX(\) RELATIVE
• OP -(\)
OP -
DESCRIPTION
•
A7 4 + 2 +
E7 4+ 2 +
A~M
ED 5 + 2 +
10 6 + 3 +
O ..... MM+ 1
S~MM+ I
B~M
EF
EF 5 + 2 +
AF 5 + 2+
10 6 + 3+
3
U---.MMt I
X ...... MM+ 1
Y--M M+ 1
AF
OF
2 AO 4 + 2 +
2 EO 4 + 2 +
A-M~A
3 A3 6 + 2 +
O-MM+ 1-"'0
SUBA
90
SUBB
DO
4
4
SUBD
SWI@
93
6
3 F 19
I
Software mterrupt 1
SWI2@
10 20
2
Software mterrupt 2
I I 20
2
Software Interrupt 3
3F
13
I
Synchrontze to
2 00 5
2 FO 5
2 03 7
3 80 2
3 CO 2
3 83 4
B~M~B
3F
SWI3@
SYNC
~4
mterrupt
TFR
RI. R2
IF 6
2
RI
TST
TSTA
TSTB
4D 2
50 2
I
TestA
I
Test B
TestM
TST
00 6
2 70 7
6D 6
3
t
2+
~
R21%l
7
6
E
F
5
H
4
I
•• •• •• ••
•• •• •• ••
••• ••• ••• •••
3
2
N
Z V C
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
R
R
R
R
R
R
R
0
••
••
••
•
•• •• ••
• • •• • • • • •
•••••••
•••••••
••••••••
•• •• •• ••
••
•
•• •
•
®
®
S
S
I
I
I
I
I
I
I
I
I
I
I
I
I
R
R
I
I
R
I
I
I
S
S
S
I
If-- f--®
(NOTES)
Spacial Case - Carry set if b7 is SET.
9t Condition Code. set 8.a direct result of the instruction if CC il tP8Cified. and not affected otharwise.
LEGEND:
Z.ro (byta)
OP
Opar.tion Coda (H.xedecimal)
Overflow, 2's complement
V
Number of MPU Cycles
CarrV from bit 7
Number of Progr.m Bytes
C
#
Test .nd set if trua, cl_ed otherwise
Arithmetic Plu.
+
Not Affected
Arithmetic Minul
x
Multiplv
CC Condition Coda Register
g
Concatenation
Complement of M
logiealor
V
Transfer Into
logieal.nd
A
H.lf .... rv (from bit 3)
H
logiclll Exclulive or
Naptive (sign bid
N
@
z
•*
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
429
HD6809E, HD68A09E, HD68B09E
Table 10 Hexadecimal Values of Machine Codes
OP
Mnem
Mode
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
NEG
Direct
#
OP
Mnem
Mode
6
2
6
6
2
2
ROR
6
6
6
2
2
LEAX
LEAY
LEAS
LEAU
PSHS
PULS
PSHU
PULU
Indexed
COM
LSR
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
ASR
ASL,LSL
ROl
OEC
INC
TST
JMP
CLR
Direct
10
11
12
13
14
15
16
17
18
19
lA
lB
lC
10
IE
1F
} See
Next Page
NOP
SYNC
20
21
22
23
24
25
26
27
28
29
2A
28
2C
2D
2E
2F
Implied
Implied
6
2
2
6
2
6
6
3
6
2
2
2
2
~4
LBRA
LBSR
Relative
Relative
5
9
3
3
OAA
ORCC
Implied
Immed
2
3
1
2
ANOCC
SEX
EXG
TFR
Immed
Implied
;
Implied
3
2
8
6
2
1
BRA
BRN
BHI
BLS
BHS, BCC
BlO, BCS
BNE
BEQ
BVC
BVS
BPl
BMI
BGE
BLT
BGT
BLE
Relat've
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Rela'ive
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
40
41
42
43
44
45
46
41
48
49
4A
4B
4C
40
4E
4F
l
Indexed
Implied
I
RTS
ABX
RTI
CWAI
MUl
Implied
OP
Mnem
Mode
60
61
62
63
NEG
Indexed
2
2
64
65
66
67
68
69
6A
6B
6C
60
6E
6F
1
1
Immed
Implied
~20
2
SWI
Implied
19
NEGA
Implied
2
70
71
COMA
LSRA
2
2
RORA
ASRA
AS LA, LSLA
ROlA
OECA
2
2
2
2
2
INCA
TSTA
2
2
13
74
75
76
17
78
79
7A
7B
7C
11
2+
COM
LSR
6+
6+
2+
2+
ROR
ASR
ASl,LSl
ROL
DEC
6+
6+
6+
6+
6+
2+
2+
2+
2+
2+
INC
TST
JMP
CLR
2+
2+
Indexed
6+
6+
3+
6+
2+
NEG
Extended
7
3
3
Implied
2
50
51
52
53
54
55
NEGB
Implied
2
56
RORB
ASRB
ASLB, l.SLB
ROLB
OECB
COMB
LSRB
2
2
2
2
2
2
2
80
81
82
83
84
85
66
87
88
89
8A
8B
ac
INCB
TSTB
CLR8
7D
7E
7F
80
8E
Implied
Number of MPU cyciM (less possible push pull or mdexed-mode cycles)
2
COM
LSR
ROR
ASR
ASL,LSL
ROL
DEC
2+
INC
TST
JMP
ClR
SUBA
CMPA
SBCA
SUBD
ANOA
BITA
LOA
EORA
AOCA
ORA
AOOA
CMPX
BSR
LOX
3
3
3
3
3
4
Extendpd
Immed
Immed
Relative
Immed
2
2
2
4
3
3
3
3
2
2
3
2
2
2
2
2
2
2
2
4
7
3
2
2
2
2
3
2
3
2
SF
(to be continued)
# N umber of program bytes
Denotes unused opcode
~HITACHI
430
#
6+
72
CLRA
57
58
59
5A
58
5C
50
5E
5F
#
2+
2+
2+
2+
2
2
5
3
6,15
LEGEND:
-..
4+
4+
4+
4+
5+
5+
5+
5+
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD6809E, HD68A09E, HD68B09E
OP
Mnem
90
SUBA
CMPA
SBCA
SUBO
ANOA
BITA
LOA
STA
EORA
AOCA
ORA
AOOA
CMPX
JSR
LOX
STX
91
92
93
94
95
96
97
98
99
9A
9B
9C
90
9E
9F
AO
AI
A2
A3
A4
A5
A6
A7
AS
A9
AA
AB
AC
AD
AE
AF
BO
Bl
B2
83
B4
B5
B6
B7
B8
B9
BA
BB
BC
BO
BE
BF
co
Cl
C2
C3
C4
C5
SUBA
CMPA
SBCA
SUBO
ANOA
BITA
LOA
STA
EORA
AOCA
ORA
AOOA
CMPX
JSR
LOX
STX
SUBA
CMPA
SBCA
SUBO
ANOA
BITA
LOA
STA
EORA
AOCA
ORA
AOOA
CMPX
JSR
LOX
STX
SUBB
CMPB
SBCB
AOOO
ANOB
BITB
#
OP
Mnem
Mode
4
4
4
6
4
4
4
4
4
4
4
4
6
7
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C6
C7
LOB
Immed
C9
C9
CA
CB
CC
CO
CE
CF
EORB
AOCB
ORB
AOOB
LOO
00
01
02
03
04
05
4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
6+
7+
5+
5+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
07
08
09
OA
DB
DC
00
DE
OF
SUBB
CMPB
SBCB
AOOO
ANOB
BITB
LOB
STB
EORB
AOCB
ORB
AOOB
LOO
STO
LOU
STU
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
SUBB
CMPB
SBCB
AOOO
ANOB
BITB
LOB
STB
EORB
AOCB
ORB
AOOB
LOO
STO
LOU
STU
Extended
5
5
5
7
5
5
5
5
5
5
5
!i
7
8
6
6
EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
EO
EE
EF
Immed
2
2
2
4
2
2
2
2
2
3
2
2
FO
Fl
F2
F3
F4
F5
F6
F7
FB
F9
FA
FB
SUBB
CMPB
SBCB
AOOO
ANOB
BITB
LOB
STB
EORB
AOCB
ORB
AOOB
Mode
Direct
Indexed
Indexed
Extended
r
LOU
06
1
Immed
Direct
r
j
Direct
Indexed
Indexed
Extended
E)Ctended
#
OP
Mnem
2
2
2
2
2
2
2
FC
FD
FE
FF
LOD
STO
LOU
STU
2
3
2
2
3
3
3
4
4
4
6
4
4
4
4
4
4
4
4
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4+
4+
4+
6+
4+
4+
4+
4+
4+
4+
4+
4+
5+
5+
5+
5+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
2+
5
5
5
3
3
3
7
3
5
5
5
5
5
5
5
5
3
3
3
3
3
3
3
3
Mode
Ext1nded
Extended
#
6
6
6
6
3
3
3
3
5
4
4
4
2 Byte.Opcode
1021
1022
1023
1024
1025
1026
1027
1028
1029
102A
102B
102C
1020
102E
102F
103F
1083
108C
lOBE
1093
I09C
I09E
I09F
10A3
10AC
10AE
lOAF
10B3
10BC
lOBE
10BF
10CE
lODE
100F
10EE
10EF
10FE
10FF
113F
1183
118C
1193
119C
l1A3
l1AC
l1B3
llBC
LBRN
Relative
LBHI
LBLS
LBHS, LBCC
LBCS, LBLO
LBNE
LBEQ
LBVC
LBVS
LBPL
LBMI
LBGE
LBLT
LBGT
LBLE
Relative
Implied
SWI2
CMPO
Immed
CMPY
LOY
Immed
CMPO
CMPY
LOY
STY
Direct
CMPO
Indied
CMPY
LOY
STY
Indexed
CMPO
CMPY
LOY
STY
Immed
LOS
LOS
STS
Direct
LOS
Indexed
STS
Indexed
LOS
Extended
STS
Extended
SWl3
Implied
CMPU
Immed
Immed
CMPS
CMPU
Direct
CMPS
Direct
CMPU
Indexed
CMPS
Indexed
CMPU
Extended
CMPS
Extended
~
Oi'J
5(6)
5(6)
5(61
5(61
5(61
5(61
5(61
5(6l
5(6)
5(61
5(61
5(61
5(61
4
4
4
4
4
4
4
4
4
4
5(61
20
5
5
4
4
4
2
4
4
4
7
7
3
3
6
6
3
3
7+
7+
6+
6+
8
3+
3+
3+
3+
4
8
4
7
7
4
6
6
6+
6+
7
4
4
4
3
3
3+
3+
4
7
4
20
2
5
5
4
4
7
7
3
3
7+
7+
3+
3+
8
8
4
4
(NOTE): All unused opcodeo a'" both undefined and illegal
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
431
HD6809E, HD68A09E, HD68B09E
•
NOTE FOR USE
Execution Sequence of ClR Instruction
Cycl:-by-cycle flow of CLR instruction (Direct, Extended,
Indexed· Addressing Mode) is shown below. In this sequence
the content of the memory location specified by the operand
is read before writing "00" into it. Note that status Flags, such
as IRQ Flag, will be cleared by this extra data read operation
when accessing the control/status register (sharing the same
address between read and write) of peripheral devices.
Example: CI.R (Extended)
S8000
SAOOO
CLR
FCB
SAOOO
$80
Cycle #
I
Address
8000
Data
R/W
7F
I
Description
Opcode Fetch
'2
8001
AO
Operand Address,
1
High Byte
3
8002
00
Operand Address,
Low Byte
4
FFFF
1
VMACycle
5
AOOO
80
1
Read the Data
6
FFFF
1
VMACycle
7
AOOO
00
o
Store Fixed "00"
into Specified
Location
• The data bus has the data at that particular address.
•
•
~HITACHI
432
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
8/16-BIT MICROPROCESSOR DATA BOOK
Section Three
HD641808-Bit
Microprocessor Family
~HITACHI
HD64180R/Z
8-BIT CMOS
(Micro Processing Unit)
Based on a Imcrocoded execution UllIt and advanced CMOS manufac-
turmg technology, the HD64180 IS an 8-bIl MPU which provides the
benefits of high performance, reduced system cost and low power operatIOn while maIntamIng compatibilIty WIth the large base of mdustry
standard 8-blt software
Performance IS Improved by VIrtue of high operatIng frequency, plpeIming, enhanced mstruction set and an mtegrated Memory Management
UnIt (MMU) with 1M or SI2k bytes memory phYSical addIess space
System cost IS reduced by mcorporatmg key system functions on-chip
Ineludmg the MMU, two channel refresh, two channel Asynchronous
Senal CommunicatIOn Interface (ASCI), Clocked Serial 110 Port
(CSIIO), two channel 16-blt Programmable Reload Timer (PRT), Versatile 12 source Interrupt controller and a 'dual' (68 X x, 80x X) bus
interface.
HD64180RP
HD64180ZP
Low power consumptIOn dUlmg normal CPU operatIOn IS supple-
mented by two specific software controlled low power operatIOn modes.
The HD64180, when combmed with CMOS VLSI memOrIes and
penpherals, IS useful m system applIcatIOns requmng high perform·
ance, battery power operatIOn and standard software compatibility.
The HD64180Z IS fully compatible with Z80180 (ZI80) which IS
marketed by Zllog Inc
(DP-64S)
HD64180RCP
HD64180ZCP
• Software Features
• Enhanced standard 8-bIt software architecture'
Upward compatible with CP/M-80'"
• Hardware Features
• On-chip MMU supporting 1M byte memory (Provided 512K byte
for DP-64S.
• Two channel DMAC with memory-memory, memory-I/O and
memory-memory mapped I/O transfer capabilities
• Two channel, full duplex asynchronous serial commUnication
Interface (ASC) with programmable baud rate generator and
modem control handshake Signals
• One channel clocked senal I/O port with serial/parallel shift
register
• Two channel 16-bIt programmable reload timer for output waveform generation
• Four external and eight Internal Interrupts
• Dual bus interface compatible With Motorola 68 family and With
Intel 80 family
• On-chip clock generator
• Operating Frequency up to 10 MHz
• Low power dissipation: 50 mW at 4 MHz Operation (typ.)
• R = Interface with 63/68, 80xx peripherals
• Z = Interface with Z80 peripherals
(CP-68)
HD64180RF
HD64180ZF
(FP-80B)
~HITACHI
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
435
HD64180R/Z
Pin Function Differences in the HD64180 Series
Package
Type
*
CP-68
FP-80B
Pin
No.
HD64180R1
HD64180Z
18
Vss
Vss
35
A19
A19
52
NC
TESt
12
Vss
Vss
33
A19
A19
53
NC
TEST
*"J" after package designation indicates industrial temperature parts.
HD64180R
Part No.
HD64180RP-6
Clock Frequency
(MHz)
Package
Type
Address
Space
DP-64S
512 K Byte
FP-80
I MByte
CP-68
I MByte
Package
Type
Address
Space
DP-64S
512 K Byte
FP-80
1 M Byte
CP-68
I MByte
6
HD64180RP-8
8
HD64180RP-10
10
HD64180RF-6X
6
HD64180RF-8X
8
HD64180RF-IOX
10
HD64180RCP-6X
6
HD64180RCP-8X
8
HD64180RCP-10X
10
HD64180Z
Part No.
HD64180ZP-6
Clock Frequency
(MHz)
6
HD64180ZP-8
8
HD64180ZP-1O
10
HD64180ZF-6X
6
HD64180ZF-8X
8
HD64180ZF-I0X
10
HD64180ZCP-6X
6
HD64180ZCP-8X
8
HD64180ZCP-10X
10
~HITACHI
436
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
• PIN ASSIGNMENT
• HD64180R
Vas
1
0
XTAI.
E
m
1M
lIEF
HID
rmo;
rnn-,
CKS
CKA,,'rEI'Ill.
RXA,
TXA,
CKAo/tmRiO
RXAo
TXAo
0Cll0
~
:::~~l!e$!:1O!;;'::i:::"~:J.::;~~!i
..i.iJ~~~~~~;ooo8oo
~
..
D,
0.
Vee '-;L...._ _ _ _ _ _-J'- VIS
(FP-80B)
(DP-64S)
I~ri~c~
i~~j<~~~~
~
Ww
b~=m~wx».~~!w~~~
b-llaoll"II00IIW'tIl"IIMIiNII-
ifJTO~
"'..0
~II:O
HALT
mil),
0
lNr. 11
iilim;
INT21
ST 1
CKS
6 RXS/C'fS;
TXS
""1
A,1
A,1
A,1
Vss 18
A.
A,
AI',
A,
A,
A.
A"
An
~ CKA1/TENDo
~ RXA,
52 NC
51 TXA!
CKAo/lJREQ;;
RXAo
;
•
••
21
2
TXAo
0Cll0
~CfSo
2
I$ilfi'So
.. " 07
~rr~n~
M -
N
M
~II~II~
M
...,
::;II~II~
NC: Not connected.
Please leave the
NC pins open.
(CP-68)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
437
HD64180R/Z
• PIN ASSIGNMENT
• HD64180Z
o
WAif
iflJSACl<
4
5
E
BOSRro
6
!nI':
, [fA
~T
5
tiMl
,
Au
2'
mr
AU'
HALi
mill
5
TrnJr,
DAEQ,
CKS
Ao
A,
5
CKA'/T-ENDO
RXAI
TXA,
CKAolDREOo
4
TXAo
DCOo
A,
~
A"
m;;
D.
~~~~~~~~~~~~~~~f/
37 OJ
~JJJ~~5~~;dC;oodo
0,
~
0,
J
Do
.(
_ _-r- Vss
(FP-80B)
(DP-64S)
INTO
iNTi
HALi
0
iNr. II
5 ffmf,
I5IiEa.
I
ST
CKS
RXS/e'TS;
TXS
Ao
A, I
«
Aol
• CKA,ITENllO
RXA,
TEST
51 TXA,
A, I
V..
A.
CKAO/~
RXAo
TXAo
A.
As 21
0l:"00
eT&
~~~gMN
~~~~~~
••••
~~~~:~~~~~dCOOdQd
~
..
Please leave the TEST
pin open.
(CP-68)
~HITACHI
438
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
• HD64180 BLOCK DIAGRAM
1I
r
'1
r 'If r 1TI Ti r T T 'l 1
-
1T0UT~c-
1-- .....
"E
16-bit
Programmable
Reload Timers
I--DREQ,
rD
I
~
DMACs
I---+TEND,
(2)
~~
~
III
"
al
~
J9
£!l~
«
f-----"
"
III
RX s/CiS",- ~
)
~
(2)
III
TXS .... -
Interrupt
CPU
al
CKS·
I
Bus State Control
Timing
Generator
I~ I~ I~I~
w
I
Clocked
Seliail/O
Port
"tl
"tl
-TXAo
.1. CKAo/DREQo
Asynchronous
SCI
(channel 0)
f.
L->
-RXAo
-RTSo
-CTSo
-DCDo
'--MMU
-D-----Address
Buffer
-U
I
I
Data
Buffer
0
,---....,
'-----'
I
-TXA,
Asynchronous
SCI
(channel 1)
!..... CKA ,/TENDo
I-- RXA,
~
-Vcc
-Vss
(Ao- A'9: HD64180R1, HD64180Z; FP-80, CP-68)
.HITACHI
Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
439
HD64180R/Z
• ABSOLUTE MAXIMUM RATINGS
Value
Unit
-0.3- +7.0
V
-0.3- Vcc+ 0.3
V
Symbol
Item
Supply Voltage
Input Voltage
Operating Temperature
Topr
Storage Temperature
Tstg
-20- + 75'
°C
-40- +85"
-55- +150
°C
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions. If
these conditions are exceeded, it could affect reliability of LSI
• Standard Temp.
'" '" Industrial Temp .
• ELECTRICAL CHARACTERISTICS
• DC CHARACTERISTICS (Vcc=SV ±10%, Vss=OV, ta=-20- +7S o C, Industrial Temp
Ta=-40 - +8S o C, unless otherwise noted.)
max.
Unit
Vee-0.6
Vee+ 0.3
V
V,H2
2.0
Vee+ 0.3
V
Input 'T' Voltage
RESET, EXTAL, NMI
VIL1
-0.3
0.6
V
Input 'T' Voltage
Except RESET, EXTAL, NMI
V,L2
-0.3
0.8
V
Output "H" Voltage
All Outputs
VOH
Output "t.:' Voltage
All Outputs
VOL
Item
Symbol
Input "H" Voltage
RESET, EXTAL, NMI
V,H1
Input "H" Voltage
Except RESET, EXTAL, NMI
Condition
min.
IOH=-2OOIlA
2.4
IOH=-2OI'A
Vee-1.2
typo
V
IOL=2.2mA
0.45
V
Input Leakage
Current All Inputs
ExceptXTAL, EXTAL
I,L
Vin = 0.5 - Vee-0.5
1.0
I'A
Three State Leakage
Current
ITL
V,n = 0.5 - Vee-0.5
1.0
I'A
Power Dissipation
(Normal Operation)
Icc'
Power Dissipation
(SYSTEM STOP mode)
Pin Capacitance
Cp
f=4MHz
10
20
f=6MHz
15
30
f=8HMz
20
40
f= 10MHz
25
50
f=4HMz
2.5
5.0
f=6MHz
3.3
7.5
f=8HMz
5.0
10.0
f= 10MHz
6.3
12.5
Vin =OV, f= 1HMz
Ta = 25°C
12
'V'H min. = Vee-1.OV, V,L max. =0.8V (all output terminal are at no load)
~HITACHI
440
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
mA
pF
HD64180R/Z
• DC CHARACTERISTICS (V cc=5V ± 10%, Vss=OV, ta=-20 - +75°C, Industrial Temp
Ta=-40- +85°C, unless otherwise noted.)
HD64180R/Z-4
HD64180R/Z-6
HD64180R/Z-8
Symbol
min.
max.
min.
max.
min.
max.
min.
max.
unit
teye
250
2000
162
2000
125
2000
100
2000
ns
Clock "H" Pulse Width
ICHW
110
65
50
40
ns
Clock 'T' Pulse Width
tCLW
110
65
50
40
ns
Item
Clock Cycle Time
Clock Fall Time
15
tel
15
HD64180R/Z-10
15
10
ns
f----
Clock Rise Time
ter
15
tAo
110
15
15
10
ns
80
70
ns
70
ns
-----
Address Delay Time
Address Set-up Time
(ME or IOE t)
ME Delay Time 1
90
50
tAS
tME01
20
30
-
85
60
45
ns
10
IOC=1
RD Delay Time 1 - - - - tROO1
IOC=O
85
60
45
50
85
65
60
55
LlR Delay Time 1
tL01
100
80
70'
60
Address Hold Time 1
(ME, IOE, RD or WR i )
tAH
ns
80
35
20
10
ns
ns
ME Delay Time 2
tMEO 2
85
60
45
50
ns
RD Delay Time 2
tROO2
85
60
45
50
ns
LlR Delay Time 2
tL02
100
80
70'
60
ns
Data Read Set-up Time
Data Read Hold Time
----
tORS
50
tORH
0
- - -' - - - -
40
30
25
ns
0
0
0
ns
---
ST Delay Time 1
tS101
110
90
70
60
ns
ST Delay Time 2
ISTD2
110
90
70
60
ns
WAIT Set-up Time
tws
80
WAIT Hold Time
tWH
70
40
40
40
40
30
ns
30
ns
--
Write Data Floating
Delay Time
100
tWDZ
WR Delay Time 1
tWR01
90
Write Data Delay Time
twoo
110
60
ns
65
60
50
ns
90
80
60
ns
--
- -- - - - - - - -
Write Data Set-up Time
(WRt)
twos
WR Delay Time 2
tWR02
WR Pulse Width
tWRP
-
95
70
-40
60
--- - -
--
280
15
ns
------
90
-
20
80
170
60
130
50
-1-----110
ns
ns
'For a loading capacitance of less than or equal to 40 picofarads and operating temperature from 0 to 50 degrees, subtract 10
nanoseconds from the value given in the maximum columns_
~HITACHI
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
441
HD64180R/Z
HD64180R/Z·4
HD64180R/Z·6
HD64180R/Z·8
HD64180R/Z·10
Symbol
min.
min.
min.
min.
Write Data Hold Time
(WR t)
twoH
60
IOE Delay Time 1
tl001
Item
max.
max.
40
max.
15
max.
10
unit
ns
85
60
45
50
ns
85
65
60
55
ns
85
60
45
50
ns
IOE Delay Time 2
tl002
iOE" Delay Time 2
tl003
540
340
250
200
ns
tiNTS
80
40
40
30
ns
tlNTH
70
40
40
30
ns
NMI Pulse Width
tNMIW
120
120
100
80
ns
BUSREQ Set-up Time
tBRS
80
40
40
30
ns
BUSREQ Hold Time
tBRH
70
40
40
30
ns
BUSACK Delay Time 1
tBA01
100
BUSACK Delay Time 2
(LiR ~ )
lNi Set-up Time
(cid )
INT Hold Time
(cjd)
( ~ )
95
70
60
ns
tBA02
100
95
70
60
ns
Bus Floating Delay Time
tBzo
130
125
90
70
ns
ME Pulse Width (HIGH)
tMEWH
200
110
90
70
ns
210
125
100
80
ns
ME Pulse Width (LOW)
tMEwL
REF Delay Time 1
tRF01
110
90
80
60
ns
REF Delay Time 2
tRF02
110
90
80
60
ns
HALT Delay Time 1
tHA01
110
90
80
50
ns
HALT Delay Time 2
tHA02
110
90
80
50
ns
tORQS
80
40
40
30
ns
tORQH
70
40
40
30
ns
DREQ i Set-up Time
DREQ i Hold Time
TEND i Delay Time 1
tTE01
TEND i Delay Time 2
Enable Delay Time 1
85
70
60
50
tTE02
85
70
60
50
ns
tE01
100
95
70
60
ns
Enable Delay Time 2
tE02
100
95
70
60
ns
E Pulse Width (HIGH)
PWEH
150
75
65
55
ns
PWEL
300
180
130
110
ns
E Pulse Width (LOW)
~HITACHI
442
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
ns
HD64180R/Z
Item
Symbol
HD64180R/Z-4
HD64180R/Z-6
HD64180R/Z-8
HD64180R/Z-10
min.
min.
min.
min.
max.
max.
max.
max.
unit
Enable Rise Time
tEr
25
20
20
20
ns
Enable Fall Time
tEl
25
20
20
20
ns
tTOo
300
300
200
150
ns
CSI/O Transmit Data
Delay Time
(Internal Clock
Operation)
tSTDI
200
200
200
150
ns
CSI/O Transmit Data
Delay Time
(External Clock
Operation)
tSTOE
7.5tcyc
+300
7.5tcyc
+300
7.5tcyc
+200
7.5tcyc
+150
ns
CSI/O Receive Data
Set-up Time
(Internal Clock
Operation)
tSRSI
1
1
1
1
tcyc
CSI/O Receive Data
Hold Time
(Internal Clock
Operation)
tSRHI
1
1
1
1
tcyc
CSI/O Receive Data
Set-upTime
(External Clock
Operation)
tSRSE
1
1
1
1
tcyc
CSI/O Receive Data
tSRHE
1
1
1
1
tcyc
RESET Set-up Time
tRES
120
120
100
80
ns
RESET Hold Time
tREH
80
80
70
60
ns
Oscillator Stabilization
Time
tose
20
20
20
40
ms
tEXr
25
25
25
25
ns
External Clock Fall Time
(EXTAL)
tEXI
25
25
25
25
ns
RESET Rise Time
tRr
50
50
50
50
ms
Timer Output Delay
Time
External Clock Rise
Time
(EXTAL)
RESET Fall Time
tRI
50
50
50
50
ms
Input Rise Time
(except EXTAL, -RESET)
tlr
10
100
100
100
ns
Input Fall Time
(except EXTAL,RESET)
til
100
100
100
100
ns
$HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
443
HD64180R/Z
~--~~------------~~~----~
RD--+--++"""\
WR--1--H--------------rt--1t----1--~~----t~W~R~P--~~
ST----++"""\
tSTD
Data ----I+--~~~~KI
IN
Data ----++---------------------------~
OUT
RESET~
f
t-H------
'1
3C
'1 Output buffer is off at this point
FIgure 1 CPU TIming (1)
•
444
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589-8300
HD64180R/Z
1003
Data
IN "1
~EWH
BUSREQ
BUSACK
ADDRESS ______________~,
DATA
'Mr.
'RI)
WR".1M
~--------------~
"' during tNT 0 acknowledge cycle
*2 during refresh cycle
.
.
"3 Output buffer is off at thIS POint
Figure 1 CPU Timing (2)
$HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
445
HD64180R/Z
CPU or DMA ReadIWnte Cycle (Only DMA Write Cycle for TINliiI
Ta
-T-,--------T-,----"-----,=;;------
nmr.
(at level sense)
nmr.
(at edge sense)
"4
·ST02
*3 tSTOl
ST
., tOROS and tORaH are speclfted for the nSlng edge of clock foltowed by T:3
*2 tORoS and tORaH are speclfred for the nSlng edge of clock
"3 DMA cycle starts
·4 CPU cycle starts
FIgure 2 DMA Control Signals
Tw
T,
TW
E
(Memory ReadiWntel
E
U/O Readl
E
U/OWrrtel
tORS
DO-D,~~----------------------------~~rt
'Cli.!-,----' t - - - - - - - - - - ' I
Figure 3 E Clock Timing (1)
E
( BUS RELEASE mode)
SLEEP mode
----'---
F,gure 3 E Clock Timong (2)
~HITACHI
446
Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180RlZ
Timer Data
Reg.=OOOOH
trOD
Figure 4 Timer Output Timing
SLP .._ _
Next op-code fetch
RIi
---------+------11""\
1
Figure 5 SLP Execution Cycle
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra POint Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
447
HD64180R/Z
CSI/O Clock
tSTDI
Transmit data
(Internal Clock)
--------f--J r------------t--'
1'-_ _ _ _ _ _ _ _ _ __
tSTDE
tSTDE
Transmit data
(External Clock) _ _ _ _ _ _ _ _.j-_~ 1\.-_ _ __
Receive data
(Intemal Clock)
Receive data
(Extemal Clock)
Figure 6 CSIIO Receive/Transmit Timing
-Y20V
1Fi
RL =2.2kfl
Test Point
C
C= 90pF
R
20VV-
---.I\...=;0.;.;:.8,-,-V_ _ _
0_.8_V~
Vee
152074
Reference Level (Input)
tG\
\!JI
or Equiv.
R= 12kfl
=X
2 .4V
2.4VX=
0.8V
0.8V
-------
Reference Level (Output)
EXTAL
VILl
EXTAL Rise time and Fall time
Inputs, other than EXTAL, Rise time and Fall time
Figure 7 Bus Timing Test load (TTL Load)
~HITACHI
448
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
piaces the address bus, data bus, RD, WR, ME and
1 PIN DESCRIPTION
XTAL liN)
Crystal oscillator connection. Should be left open if an external
TTL clock is used. It is noted this input is not a TTL level input. See
Table D.C. characteristics.
EXTAL liN)
JOE in the high
impedance state.
BUSACK - Bus Acknowledge (OUT)
When the CPU completes bus release (in response to BUSREQ
LOW), it will assert BUSACK LOW. This acknowledges that the
bus is free for use by the requesting device
Crystal oscillator connection. An external TTL clock can be
input on this line. This input is schmitt triggered.
HALT - Halt/Sleep Status (OUT)
'" lOUT)
Asserted LOW after execution of the HALT or SLP instructions. Used with LIR and ST output pins to encode CPU status.
System Clock. The frequency is equal to one-half of crystal oscillator.
RESET - CPU Reset liN)
When LOW, initializes the HD64I80 CPU. All output signals
are held inactive during RESET.
LlR - Load Instruction Register lOUT)
Asserted LOW when the current cycle is an op-code fetch cycle.
Used with HAI"T and ST output pins to encode CPU status.
ST - Status (OUT)
Used with the HALT and LIR output pins to encode CPU
status.
Ao-A17 - Address Bus lOUT, 3-STATE)
A18/TOUT
19-bit address bus provides physical memory addresses of up to
512k bytes. The address bus enters the high impedance state during
RESET and when another device acquires the bus as indicated by
BUSREQ and BUSACK LOW. AI, is multiplexed with the TOUT
output from PRT channell. During RESET, the address bus function is selected. TOUT function can be selected under software control.
Table 1 Status Summary
HALT
L1R
0
1
0
CPU operation
(1st op-code fetch)
1
1
0
CPU operation
(2nd op-code and
3rd op-code fetch)
1
1
1
CPU operation
(MC except for op-code fetch)
0 0 -0 1 - Data Bus (IN/OUT, 3-STATE)
Bidirectional 8-bit data bus. The data bus enters the high impedance state dunng RESET and when another device acquires the
bus as indicated by BUSREQ and BUSACK LOW.
RD -
Read (OUT, 3-STATE)
Used during a CPU read cycle to enable transfer from the external memory or 110 device to the CPU data bus.
WR -
Write lOUT, 3-STATE)
Used during a CPU write cycle to enable transfer from the CPU
data bus to the external memory or 110 device.
0
X
1
DMA operation
0
0
0
HALT mode
1
0
1
SLEEP mode (including
SYSTEM STOP mode)
NOTE)
-.!ndicates memory read or write operation. The HD64180 asserts
ME LOW in the following cases.
(a) When fetching instructions and operands.
(b) When reading or writing memory data.
(c) During memory access cycles of DMA.
(d) During dynamic RAM refresh cycles.
10E - I/O Enable (OUT, 3-STATE)
Indicates 110 read or write operation. The HD64180 asserts !OE
LOW in the followmg cases.
(a) When reading or writing I/O data.
(b) During I/O access cycles of DMA.
(c) During INTo acknowledge cycle
WAIT - Bus Cycle Wait (IN)
Introduces wait states to extend memory and 110 cycles. If LOW
at the falling edge ofT" a wait state (Tw) is inserted. Wait states will
continue to be inserted until the WAIT input is sampled HIGH at
the falling edge of Tw, at which time the bus cycle will proceed to
completion.
Machine cycle
When LOW, indicates the CPU is in the dynamic RAM refresh
cycle and the low-order 8 bits (Ao-A,) of the address bus contain
the refresh address.
NMI - Non-Maskable Interrupt UN)
When edge transition from HIGH to LOW is detected, forces
the CPU to save certain state information and vector to an interrupt
service routine at address 0066H. The saved state information is restored by executing the RETN (Return from Non-Maskable Interrupt) instruction.
INTO - Maskable Interrupt Level 0 (IN)
When LOW, requests a CPU interrupt (unless masked) and
saves certain state information unless masked by software. INTo requests service using one of three software programmable interrupt
modes.
Mode
Synchronous clock for connection to HD63 x x series and other
6800/6500 series compatible penpheral LSIs.
Bus Request UN)
device may request use of the bus by asserting
BUSREQ LOW. The CPU will stop executing Instructions and
Operation
0
Instruction fetched and executed from data bus.
1
Instruction fetched and executed from address
0038H.
2
Vector System - Low-order 8 bits vector table
address fetched from data bus.
E - Enable (OUT)
BUSREQ -
X: Don't car.
Me.
REF - Refresh (OUT)
ME - Memory Enable (OUT, 3-STATE)
~..t!:ter
Operation
ST
In all modes, the saved state mformation is restored by executing RET! (Return from Interrupt) instruction.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
449
HD64180R/Z
INT"
!NT; -
RXA, - Asynchronous Receive Data - Channel 1 (IN)
Maskable Interrupt levell, 2 (IN)
When LOW, requests a CPU interrupt (unless masked) and
saves~tain state information unless masked by software. INT,
and INT, (and internally generated interrupts) re~ interrupt
service using a vector system similar to Mode 2 of INTo.
DREQO - DMA Request - Channel 0 (IN)
When LOW (programmable edge or level sensitive), requests
DMA transfer service from channel 0 of the HD64180 DMAC.
DREQo is used for Channel 0 memory ~ I/O and memory
~ memory mapped I/O transfers. DREQo is not used for
memory ~ memory transfers. This pin is multiplexed with
CKAo·
Asynchronous receive data to channel I of the ASCI.
CKA, - Asynchronous Clock .- Channel 1 (IN/OUT)
Clock mputloutput for channel I of the ASCI. This pin is
multiplexed (software selectable) with TENDo.
cfs, - Clear to Send -
Channel 1 (IN)
Modem control input signal for channell of the ASCI. This pin
is multiplexed (software selectable) with RXS.
TXS - Clocked Serial Transmit Data (OUT)
Clocked serial transmit data from the Clocked Serial I/O Port
(CSI/O).
TENDo - Transfer End - Channel 0 (OUTI
Asserted LOW synchronous with the last wnte cycle of channel
oDMA transfer to indicate DMA completion to an external device.
ThIs pm is multiplexed with CKA,.
RXS - Clocked Serial Receive Data (IN)
Clocked serial receive data to the CSI/O. This pin is multiplexed
(software selectable) WIth ASCI channel I CTS, modem control
input.
DREQ, - DMA Request - Channell (IN)
When LOW (programmable edge or level sense), requests
DMA transfer service from channel I of the HD64180 DMAC.
Channel I supports Memory - Purpose
Registers
R Counter
R
Index Register
IX
Index Register
IV
Stack Pointer
SP
Program Counter PC
Register Set GR'
Accumulator
A'
Flag Register
F'
B'Register
C'Register
D'Register
E'Register
H'Register
L'Register
General
Purpose
Registers
Figure 8 CPU Register Configuration
2,1 Register Description
incremented for each CPU op-code fetch cycles (each LlR cycles).
(1) Accumulator (A, A')
The Accumulator (A) serves as the primary register used for
many arithmetic, logical and I/O instructions.
(6) Index Regiaters (IX, end IV)
The Index Registers are used for both address and data operations. For addressing, the contents of a displacement specified in
the instruction are added to or subtracted from the Index Register
to determine an effective operand address.
(2) Fleg Registers (F, F')
The flag register stores various status bits (described in the next
section) which reflect the results of instruction execution.
(3) General Purpose Registers (BC, BC', DE, DE', HL, HL')
The General Purpose Registers are used for both address and
data operation. Depending on instruction, each half (8 bits) of these
registers (B, C, D, E, H, and L) may also be used.
Interrupt Vector Register III
For interrupts which !e~ a vector table address to be calculated (INT. Mode 2, INT" INT, and internal interrupts), the Interrupt Vector Register (I) provides the most significant byte of the
vector table address.
(4)
(7) Steck Pointer (SP)
The Stack Pointer (SP) contains the memory address based
LIFO stack.
(8) Program Counter (PC)
The Program Counter (PC) contains the address of the instruction to be executed and is automatically updated after each instruction fetch.
(9) Flag Register (F)
The Flag Register stores the logical state reflecting the results of
instruction execution. The contents of the Flag Register are used to
control program flow and instruction operation.
R Counter (R)
The least significant seven bits of the R Counter (R) serve to
count the number of instructions executed by the HD64180. R is
(&)
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
451
HD64180R/Z
instruction was an addition operation (ADD, INC, etc.).
43210
bot
I
s
Iz
- I
H
I - I PN I~
Flag ReglSler(FI
C: Carry (bit 0)
S: Si9ro (bit 7)
C is set to 1 when a carry (addition) or borrow (subtraction)
from the most significant bit of the result occurs. C is also affected
by Accumulator logic operations such as shifts and rotates.
S stores the state of the most significant bit (bit 7) of the result.
This is useful for operations with signed numbers in which values
with bit 7 = I are interpreted as negative.
3 ADDRESSING MODES
Z: Zero (bit 6)
Z is set to I when instruction execution results containing O.
Otherwise, Z is reset to O.
H: Half Carry (bit 4)
H is used by the DAA (Decimal Adjust Accumulator) instruction to reflect borrow or carry from the least significant 4 bits and
thereby adjust the results of BCD addition and subtraction.
PlY: ParitylOverflow (bit 2)
PlY serves a dual purpose. For logical operations PlY is set to 1
if the number of 1 bit in the result is even and PlY is reset to 0 if the
number of 1 bit in the result is odd. For two complement
arithmetic, PlY is set to 1 if the operation produces a result which is
outside the allowable range (+ 127 to -128 for 8-bit operations,
+ 32767 to - 32768 for 16-bit operations).
N: Negative (bit 1)
N is set to 1 if the last arithmetic instruction was a subtract operation (SUB, DEC, CP, etc.) and N is reset to 0 if the last arithmetic
The HD64180 instruction set includes eight addressing modes.
Implied Register
Register Direct
Register Indirect
Indexed
Extended
Immediate
Relative
10
(1) Implied Register liMP)
Certain op-codes automatically imply register usage, such as the
arithmetic operations which inherently reference the Accumulator,
Index Registers, Stack Pointer and General Purpose Registers.
(2) Register Direct (REG)
Many op-codes contain bit fields specifying registers to be used
for the operation. The exact bit field definition vary depending on
instruction as follows.
8-bit Register
g or g' field
Register
ww field
Register
0
0 0
B
0
0
0
0
1
C
0
1
DE
0
1
0
D
1
0
HL
1
1
SP
0
1
1
E
1
0
0
H
1
0
1
L
1
1
0
-
1
1
1
A
xx field
BC
Register
0
0
BC
0
1
DE
1
0
IX
1
1
SP
1 6-bit Register
Register
zz field
Register
0 0
0 1
BC
0
0
BC
DE
HL
0 1
1 0
DE
1 0
1
AF
1
SP
1
yy field
1
IV
Suffixed Hand L to wW,xx,yy,zz (ex. wwH,lXLI indicate upper and lower a-bit of the 16-bit
register respectively.
~HITACHI
452
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
(3) Register Indirect (REG)
(6) Immedlete (lMMED)
The memory operand address is contained in one of the 16-bit
General Purpose Registers (BC, DE and HL).
The memory operands are contained within one or two bytes of
the instruction.
(7) Rel,tlv, (RELI
(4) Indexed (lNDX)
The memory operand address is calculated using the contents of
an Index Register (IX or lY) and an S-bit signed displacement specified in the instruction.
I
1
ISign extended
op-code ,
I
op-code2
I
displacement (eI)
~
IX or IV
Relative addressing mode is only used by the conditional and
unconditional branch instructions. The branch displacement (relative to the cpntents of the program counter) is contained in the instruction.
~r----d~-op-code~~-t(~j)--~~nextended
r-
r
Operand
Program Counter (PC)
I
T
Memory
(8) 10110)
(6) Extended (EXT)
The memory operand address is specified by two bytes contained
in the instruction.
I
I
I •
f
I
f
1
op-code
l
n
m
mf
]
n
r-
r-
10 addressing mode is used only by I/O instructions. This mode
specifies 110 address (iOE = 0) and outputs them as follows.
(I) An operand is output to A,-A,. The Contents of Accumulator
is output to A,-A".
(2) The Contents of Register B is output to A,-A,. The Contents
of Register C is output to A,-Al5'
(3) An operand is output to A,-A,. OOH is output to A,-At ••
(useful for internal I/O register access)
(4) The CQptents of Register C is output to A,-A,. OOH is output
to A.-Al5'
(useful for internal I/O register access)
Operand
Memory
$HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
453
HD64180R/Z
• CPU BUS TIMING
MHz, 250 nsec). For interfacing to slow memory or peripherals,
optional wait states (Tw) may be inserted !:>etween T, and T•.
This section explains the HD64180 CPU timing for the following
operations.
(I) Instruction (op-code) fetch timing.
(2) Operand and data read/write timing.
(3) I/O read/write timing.
(4) Basic instruction (fetch and execute) timing.
• Instruction (op-code) Fetch Timing I
Fig. 9 shows the instruction (op-code) fetch timing with no wait
states.
__
An op-code fetch cycle is externally indicated when the LIR
(Load Instruction Register) output pin is LOW.
In the first half ofT" the address bus (Ao-A I ,) is driven with the
contents of the Program Counter (PC). Note that this is the translated address output of the HD64180 on-chip MMU.
__
In the second half of TI , the ME (Memory Enable) and RD
(Read) signals are asserted LOW, enabling the memory.
The op-code on the data bus is latched at the rising edge of T3
and the bus cycle terminates at the end of T3'
(5)~i~
(6) BUSREQ/BUSACK bus exchange timing.
The basic CPU operation consists of one or more "machtne cycles" (Me). A machine cycle consists of three system clocks, TI , T,
and T. while accessing memory or I/O, or it consists of one system
clock, Ti while the CPU internal operation. The system clock (I/» is
half frequency of crystal oscillation (Ex. 8 MHz crystal~ I/> of 4
I"
Op-code Fetch Timing
Tl
T2
,
Ao-AIB
===x
I
I
I
i PC!
T2
X
PC
+1
: <~p-code)>------I
LlR
Tl
I
I
00-07
WAIT
"I
T3
I
=:::::=:::~~~~~~~::::::~:~:
~
I
,
I
I
:
:1
i
--
\ :I
ME
RO
•
I
I
I
I
•
I
\:
I
I
~
\\..._ _ __
1
I
I
\
'-----
Figure 9 Op-Code Fetch T.ming
Fig. 10 illustrates the insertion of wait states (Tw) into the opcode fetch cycle. Wait states (Tw) are controlled by the external
WAIT' input combined with an on-chip programmable wait state
generator.
__
At the falling edge ofT, the combined WAIT input is sampled. If
WAIT inpu~sserted LO~a wait state (Tw) is inserted. The address bus, MEl RD and LIR are held stable during wait states.
When the WAIT is sampled inactive HIGH at the falling edge of
Tw, the bus cycle enters Ta and completes at the end of Ta.
Op-code fetch cycle
T2
Ao-A.s ===xr------~----~----~--~--~x:=:=.
_____
I
00-07
I
-----------~------~-----+~~~------------I
I
I
~~::::~:==:==:J_L:=::\~/~-----:rt\:,r-~---:~~--------~-----------_-:.:~:=
I
I
I
I
I
I
I
I
I
Ir
I
I
I
I
I
\L.__~'______~I____-+I__~I__~I
I
I
I
I
I
I
I
I
\L._ __
,---,
\L---~I-----+-----TI
- - 'r--~I
I
I
I
I
\~_____
Figure 10 Op-Code Fetch Timmg (with walt state)
.HITACHI
454
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
• Operand and Data Read/Write Timing
The instruction operand and data read/write timing differs from
op-code fetch timing in two ways. First. the L1R output is held inactive. Second, the read cycle timing is relaxed by one-half clock cycle
since data is latched at the falling edge of T ,.
Instruction operands include immediate data, displacement and
extended addresses and have the same timing as memory data
reads.
During memory write cycles the ME signal goes active in the
second half ofT,. At the end ofT,. the data bus is driven with the
write data.
At the start of .!J.....the WR signal is asserted LOW enabling the
memory. ME and WR go inactive in the second halfofT, followed
by deactivation of the write data on the data bus.
Wait states (Tw) are inserted as previously described for op-code
fetch cycles.
Fig. 11 illustrates the read/write timing without wait states (Tw),
while Fig. 12 illustrates read/write timing with wait states (Tw).
Read cycle
Ao-AI8
00-07
Write cycle
1
I
1
I
I
1
==x Memo~ !
------t-I-~ead ~at€>
X
address
+
Memo7 address
1
I
1
I
I
I
I
I
I
\
I
1
1
1
I
1
I
I /
I
I
1
1
1
1
1 \
1
/
I '---.,.1----'
I
I
\
iI
:I /
I
(,.-....I~-rit-·e-d-ata-----)>--I
-----------~-----T------r----~--------------__________ J 1 \.. ____ 1- _____ .1____
I
---------------
1
I
1
1
1
I
1
!:
I
I
\:
/
'--7-,- - - -....
,
Figure 11 Memory ReadlWrite Timing (without wait state)
Write cycle
Read cycle
T3
Ao-A,8===x~_____T_----_r----~--~X~~----~------+:------00-07 - - - - - - - -__:~----_+I-«Ieadda~
I
I
I
:
1
I
<
Write datS
I
;
----------"\
:r---~------:-------~----"'\: r--7i\.----------------""-T"----J
------\
\
I
I
I
i
1 \.-----T-------r-----~--:
I
I
:
1
I
I
I
I /
I \~__-+-I- - - - l - - - . . . J1
I
I
I
I
I
1
I
1
I
I /r--~I----~Ir-----~-------I
I.
1
I
1
I
I
i l l
,
I
1I
I
I
I
I
\
I
1
/
\...-+1
1I
1I
I -----1.-----'.
I I !
Figure 12 Memory Read/Write Timing (with weit state)
•
HITACHI
Hitachi America. Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
455
HD64180R/Z
4.3 I/O Read/Write Timing
110 instructions cause data read/wrIte transfer which differs
from memory data transfer in the following three ways. The IOE (II
o Enable) signal is asserted LOW instead of the ME signal. The 16bit 110 address is not translated by the MMU and A16-A18 are held
==X~
1/0 write cycle
1/0 read cycle
I-
Ao-AIB
LOW. At least one wait state (Tw) is always inserted for I/O read
and write cycles (except internal 110 cycles).
Fig. 13 shows 110 read/write timing with the automatically inserted wait state (Tw).
~I
Ta
_____I/_o_a,drd~re_s_s__~______~~X~~I______~I~/o~a~dd~r~e~ss~________
I
I
I
00-07
:(
-----~:-----r,-(~
I
I
I
Write data
>
' - - - - "----------~
--------,-----~----~-----+-----~---~--------..1: \. ___ ~------~-----:---J
'-______ _
_________ ..1 ____
~.
I
I
I
I
I
I
= 0 for
II 'I
I
I
I
I
I
I
i
I
I
ilo
I
I
/
I
I
I\\
I _____~I------------~,-I
I
r----+-------~I----------------I
I
:
\
I
I
NOTE: Als-A18
II
I
I
I
I
I
--r-----------------J./
~.
I
cycles
Figure 13 110 Read/Write Timing
4.4 Basic Instruction Timing
An instructIon may consist of a number of machme cycles mcluding op-code fetch, operand fetch and data read/wrIte cycles. An
instruction may also include cycles for internal processing in which
case the bus is idle.
The example in Fig. 14 illustrates the bus tIming for the data
transfer instruction LD (IX + d) ,g. This instruction moves the contents of a CPU register (g) to the memory location with address
computed by adding an sIgned 8-bit displacement (d) to the contents of an index register (IX).
The instruction cycle starts with the two machine cycles to read
the two bytes instruction op-code as indicated by LIR LOW. Next,
the instruction operand (d) is fetched.
The external bus is idle while the CPU computes the effective
address. Finally, the computed memory location is written with the
contents of the CPU register (g).
~HITACHI
56
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
CPU tntemal
.
I
.r
1 st op-code
2nd op-code
fetch cycle
fetch cycle
. .I.TT.I.
..I
DISplacement
read cycle
operation
Memory
.I.
wnte cyckt
Next Instructton
fetch cycle
Ao-A18
](
PC
IDDHI
X
PC+l
X
PC+2
X
lX+d
(7OH-77HI
~
9
00-01
l]if
ME
RD
WR
Machme Cycle
MCI
MC2
MC7
MC3
NOTE d = displacement
g = regISter contents
Figure 14 LD (IX + d). g Instruction Timing
nated and the HD64180 restarts execution from (logical and physical) address OOOOOH.
4.6 RESET Timing
Fig. IS shows the HD64180 hardware RESET timing. If the RESET pin is LOW for at least six clock cycles, processing is term i-
I
RESET
RESET Start
: OP-code fetch cycle
T.
T2
I
:
I
6 or more than 6 clocks
RESET
I
\.....,-----+----1::=;:
I
I
I
I
I
"-
•
High impedance
'v:Restart address(OOOOOH)
--"---'-------'<:"
Ao - A.8 _ _ _ _ _ _ _ _ _ _- - J:r--'I-I
,
I
Figure 15 RESET Timing
4.6 BUSREQ/BUSACK Bus Exchange Timing
The HD64180 can coordinate the exchange of control, address
and data bus ownership with another bus master. The alternate bus
master can request the bus release by asserting the BUSREQ (Bus
Request) input LOW. After the HD64180 releases the bus, it relinquishes control to the alternate bus master by asserting the
IroSACR (Bus Acknowledge) output LOW.
The bus may be released by the HD64180 at the end of each machine cycle. In this context a machine cycle consists of a minimum
of 3 clock cycles (more if wait states are mserted) for op-code fetch,
memory read/write and I/O read/write cycles. Except for these
cases, a machine cycle corresponds to one clock cycle.
When the bus is released, the address (Ao-Aos), data (Do-D7)
and control (ME, IOE, RD, and WR) signals are placed in the high
impedance state.
Note that dynamic RAM refresh is not performed when the
HD64180 has released the bus. The alternate bus master must provide dynamic memory refreshing if the bus is released for long periods of time.
Fig. 16 illustrates BUSREQ/BUSACK bus exchange during a
memory read cycle. Fig. 17 illustrates bus exchange when the bus
release is requested during an HD64180 CPU internal operation.
BUSREQ is sampled at the falling edge of the system clock prior to
T3 , Ti and Tx (BUS RELEASE state). If BUSREQ is asserted LOW
at the falling edge of the clock state prior to Tx, another Tx is executed.
@HITACHI
Hitachi America. Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
457
HD64180R/Z
r
+
CPU memory read cycle
T1
T2
Tw
T3
Bus release cycle
Tx
Tx
",,"CPU cycle
Tx
T1
cf>
Ao-Ata
=x
I
0
00-07
I
I
I
I
I
I
I
I
I
I
I
I
I
ME,IOE
lm.WR
!c=
~
I
:c=
I
~
:=
BUSREO
I
\
I
I
I
/
BUSACK
I
I
i\
I
I
I
/
I
I
Figure 16 Bus Exchange Timing (1)
CPU intemal operation
+
I-
Ti
Ti
Tx
Ti
Ti
Bus release cycle
Tx
Tx
cf>
Ao-A18
I
i>
I
I
I
I
I
00-07
I
I
I
ME,IOE
I
!>
I
I
I
I
I
I
I
I
I
I
I
I
I
I
/1
I
I
I
\
I
I
\1
I
I
I
I
I
I
BUSACK
c=
I
I
I
I
I
I
I
I
I
I
I
I
BUS REO
T1
I
I
I
RO.WR
.I.CPU cycle
I
I
I
I
I
I C=
I
I
I
I
I
I
I
I
I
1/
I
I
I
I
I
Figure 17 Bus Exchange Timing (2)
~HITACHI
458
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
& HALT AND LOW POWER OPERATION MODES
The HD64180 can operate in 4 different modes. HALT mode,
10STOP mode and two low power operation modes - SLEEP and
SYSTEM STOP. Note that in all operating modes, the basic CPU
clock (XT AL, EXT AU must remam active.
&. 1 HALT Mode
HALT mode is entered by executIOn of the HALT mstruction
(op-code = 76H) and has the followmg characteristics.
(I) The in ternal CPU clock remains active.
(2) All internal and~ternal interrupts can be received.
(3) Bus exchange (BUSREQ and BUSACK) can occur.
(4) Dynamic RAM refresh cycle (REF) insertion continues at the
programmed interval.
(5) I/O operations (ASCI, CSI/O and PRT) continue.
(6) The DMAC can operate.
(7) The HALT output pm IS asserted LOW.
(8) The external bus activity consists of repeated 'dummy' fetches
of the op-code following the HALT instruction.
HALT op-code fetch cycle
.1'
Essentially, the HD64180 operates normally in HALT mode,
except that instruction execution is stopped.
HALT mode can be exited in the following two ways.
RESET Exit from HALT Mode
If the RESET input 's asserted LOW for at least six clock cycles,
HALT mode is exited and the normal RESET sequence (restart at
address OOOOOH) 's mitiated.
Interrupt Exit from HALT Mode
When an internal or external mterrupt is generated, HALT
mode is exited and the normal interrupt response sequence is initiated.
If the interrupt source is masked (individually by enable bit, or
globally by.J!:!', state), the HD64180 remainsJJLJ:IALT mode.
However, NMI interrupt will inItiate the normal NMI interrupt response sequence independent of the state of IEF,.
HALT timing is shown in Fig. 18
.1.
HALT mode
Interrupt
acknowledge cycle
I
I
\LI
,
I
Ao-A!B
HALT op-code address I
HALT op-code address
+
I
I
I
V
------------~~
, L-_________________________,
--------~~,
~~------------,
~
---------~
r ----------
~
:
I
_________r:--\
~--------
~~
_____
Figure 18 HALT TimIng
&.2 SLEEP Mode
Interrupt Exit from SLEEP Mode
SLEEP mode is entered by execution of the 2 byte SLP instruction. SLEEP mode has the following characteristics
(I) The internal CPU clock stops, reducing power consumption.
(2) The internal crystal oscillator does not stop.
(3) Internal and external interrupt inputs can be received.
(4) DRAM refresh cycles stop.
(5) 1/0 operations using on-chip peripherals continue.
(6) The internal DMAC stop.
(7) BUSREQ can be received and acknowledged.
(8) Address outputs go HIGH and all other control signal output
become inactive HIGH.
(9) Data Bus, 3-state.
SLEEP mode is exited in one of two ways as shown below.
The SLEEP mode is eXited by detection of an external (NMI,
INTo, INT" INTJ..Q!.internal (ASCI, CSI/O, PRT) interrupt.
In the case of NMI, SLEEP Mode is exited and the CPU begins
the normal NMI interrupt response sequence.
In the case of all other interrupts, the interrupt response depends on the state of the global interrupt enable flag (lEF,) and the
individual interrupt source enable bit.
If the individual interrupt condition is disabled by the corresponding enable bit, occurrence of that interrupt is ignored and the
CPU remains in the SLEEP state.
Assuming the individual interrupt condition is enabled, the response to that interrupt depends on the global interrupt enable flag
(IEF,). If interrupts are globally enabled (lEF,= 1) and an individually enabled interrupt occurs, SLEEP mode is exited and the
appropriate normal interrupt response sequence is executed.
If interrupts are globally disabled (IEF, = 0) and an individualIy
enabled interrupt occurs, SLEEP mode is exited and instruction execution begins with the instruction following the SLP instruction.
Note that this provides a technique for synchronization with high
speed external events without incurring the latency imposed by an
interrupt response sequence.
Fig. 19 shows SLEEP timing.
RESET Exit from SLEEP Mode
If the RESET input is held LOW for at least six clock cycles, the
HD64180 will exit SLEEP mode and begin the normal RESET sequence with execution starting at address (logical and physical)
00000H.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
459
HD64180R/Z
6.3 IOSTOP Mode
6.4 SYSTEM STOP Mode
IOSTOP mode is entered by setting the IOSTP bit of the I/O
Control Register (ICR) to I. In this case, on-chip I/O (ASCI, CSI/
0, PRT) stops operating. However, the CPU continues to operate.
Recovery from IOSTOP mode is by clearing the IOSTP bit in ICR
to O.
SYSTEM STOP mode is the combination of SLEEP and
10STOP modes. SYSTEM STOP mode is entered by setting the
IOSTP bit in ICR to 1 followed by execution of the SLP instruction.
In this mode, on-chip I/O and CPU stop operating, reducing power
consumption. Recovery from SYSTEM STOP mode is the same as
recovery from SLEEP mode, noting that internal I/O sources (disabled by lOS TOP) cannot generate a recovery interrupt.
SLP 2nd op-code
fetch cycle
Ao-A1B
SLEEP mode
SLP 2nd OP-Cod? address
X
7FFFFH
I
I
I
Op-code fetch or interrupt
acknowledge cycle
iX~---
I
I
I
---~
I
I
II
\~----------~~I
\'-----Figure 19 SLEEP Timing
~HITACHI
460
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
6 INTERRUPTS
The HD64180 CPU has twelve interrupt sources, four external
and eigh t in ternal, with fixed priority.
This section explains the CPU registers associated with interrupt
Priority
Higher
1
Priority
2
3
4
5
6
7
8
9
10
11
12
Lower
Priority
processing, the TRAP mterrupt, mterrupt response modes and the
external interrupts. The detailed discussion of internal interrupt
generation (except TRAP) is presented in the appropriate hardware
section (i.e. PRT, DMAC, ASCI and CSI/O).
Interrupt
TRAP (Undefined Op-code Trap)
iiiMf (Non Maskable Interrupt)
INT 0 (Maskable Interrupt Level 0)
TIiIT1 (Maskable Interrupt Level 1)
INT 2 (Maskable Interrupt Level 2)
Timer 0
Timer 1
DMA channel 0
DMA channel 1
Clocked Serial 1/0 Port
Asynchronous SCI channel 0
Asynchronous SCI channel 1
Internal Interrupt
)
External Interrupt
Internal Interrupt
Figure 20 Interrupt Sources
6.1 Interrupt Control Registers and Flags
The HD64180 contains three registers and two flags which are
associated with interrupt processing.
Register and
Flag Name
Access Method
Function
This register determines the most sigOlficant three bits of the
low-order byte of the interrupt vector table address for external interrupts INT, and INT2 and all mternal interrupts (except TRAP).
The five least significant bits are fixed for each specific interrupt
source. By programming IL the vector table can be relocaled on 32
bytes boundaries
IL is initialized to OOH during RESET
I
ContaIns upper 8-bit
of interrupt vector
LD A,I and
LD I, A Instructions
(3) INT /TRAP Control Re.gister UTC)
IL
Contains lower 8-bit
of Interrupt vector
I/O instruction
(addr = 33H)
bot
ITC
Interrupt/Trap control
I/O instruction
(addr= 34H)
INTfTRAP Control Reg,ster UTC
TRAP
A/W
EI. DI,
LD A. I. and
LD A, R Instructions
Enable/disable
mterrupt
IEF"IEF 2
1/0 Address
= 34H)
6
I I
UFO
I I I
R
ITE2
ITEI
ITEO
RfW
RfW
R/W
!TC is used to handle TRAP mterrupts and to enable or disable
the external maskable interrupt mputs iN'f,;, INT" and INT2.
TRAP (bit 7)
(1) Interrupt Vector Register (I)
Mode 2 for INTo external interrupt, INT, and INT, external 10terrupts and all internal interrupts (except TRAP) use a programmable vectored technique to determme the address at which interrupt processing starts. In response to the interrupt a 16-bit address
is generated. This address accesses a vector table in memory to obtain the address at which execution restarts.
While the method for generation of the least significant byte of
the table address ditTers, all vectored interrupts use the contents of I
as the most significant byte of the table address. By programming
the contents ofi, vector tables can be relocated on 256 bytes boundaries throughout the 64k bytes logical address space.
Note that I is read/written with the LD A, I and LD I, A instructions rather than 1/0 (IN, OUT) instructions.
I is initialized to OOH during RESET.
Il7
R/W
I
1..6
5
I
RIW
4
Interrupt Source Dependent Code
IEF, controls the overall enabling and disabling of all internal
and external maskable interrupts (j e all mterrupts except NMI and
1/0 Address
3
IL5
• Interrupt Enable Flag 1,2 (lEF I , IEF2 )
RIW
'----v--------'
Programmable
ITE2,1,O: Interrupt Enable 2,1,0 (bits 2-0)
!TEl...!:!E~d !TEO enable and disable the external mterrupt
mputs INT" INT" and INTo respectIvely. If cleared 10 0, the interrupt IS masked. During RESET, !TEO is initialized to I while ITEI
and ITE2 are initialized to 0
Intenupt Vector Low RegISter UL
6
UFO: Undefined Fetch Object (bit 61
When a TRAP mterrupt occurs (TRAP bit is set to 1), the contents of UFO allow determmation of the startmg address of the
undefined instruction. This is necessary smce the TRAP may occur
on either the second or third byte of the op-code. UFO allows the
stacked PC value (stacked 10 response to TR AP) to be correctly adjusted. If UFO = 0, the first op-code should be mterpreted as the
stacked PC-\. If UFO = I, the first op-code address is stacked
PC- 2. UFO is read-only
= 33H)
(2) Interrupt Vector Low Register (lL)
bit
This bit is set to I when an undefined op-code IS fetched TRAP
can be reset under program control by wntmg it with 0, however it
cannot be written with I under program control. TRAP IS cleared to
o durmg RESET.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
461
HD64180R/Z
TRAP).
IfIEF, = 0, all maskable interrupts are disabled. IEF, can be reset to 0 by the DI (Disable Interrupts) instruction and set to I by
the EI (Enable Interrupts) instruction.
--Ihe purpose of IEF, is to correctly manage the occurrence of
NMI. During NMI, the prior interrupt reception state is saved and
all maskable interrupts are automatically disabled (IEF, copied to
IEF, and thell IEF, cleared to 0). At the end of the NMI interrupt
service routine, execution of the RETN (Return from Non-maskable Interrupt) will automatically restore the interrupt receiving state
(by copying IEF2 to IEF,) prior to the occurrence of NMI.
IEF, state can be reflected in the PlY bit of the CPU Status register by executing LD A, I or LD A, R instructions.
Table 2 shows the state of IEF, and IEF,.
Table 2 State of IEF, and IEF,
CPU Operation
RESET
NMI
RETN
Interrupt except
miMandTRAP
IEF,
IEF,
0
0
REMARKS
Inhibits the interrupt except NMI and TRAP.
0
IEF,
II:F,
not affected
Copies the contents of IEF , to IEF ,.
Returns from the NMI service routine.
Inhibits the interrupt except NMI and TRAP
0
0
RETI
not affected
not affected
TRAP
not affected
not affected
EI
1
1
01
0
0
LOA,I
not affected
not affected
Transfers the contents of IEF, to P/v flag
LOA. R
not affected
not affected
Transfers the contents of IEF, to P/v flag.
8.2 TRAP Interrupt
The HD64180 generates a non-maskable (not affected by the
state of IEF,) TRAP interrupt when an undefined op-code fetch occurs. This feature can be used to increase software reliability, implement an 'extended' instruction set, or both. TRAP may occur during op-code fetch cycles and also if an undefined op-code is fetched
during the interrupt acknowledge cycle for INT. when Mode 0 is
used.
When a TRAP interrupt occurs the HD64180 operates as follows.
(1) The TRAP bit in the Interrupt TRAP/Control (ITC) register is
set to I.
(2) The current PC (Program Counter) value, reflecting the location of the undefined op-code, is saved on the stack.
(3) The HD64180 vectors to logical address O. Note that iflogical
address OOOOH is mapped to physical address OOOOOH, the vector is the same as for RESET. In this case, testing the TRAP bit
in ITC will reveal whether the restart at physical address
OOOOOH was caused by RESET or TRAP.
The state of the UFO (Undefined Fetch Object) bit in ITC
allows TRAP manipulation software to correctly 'adjust' the stacked
PC depending on whether the second or third byte of the op-code
generated the TRAP. If UFO
0, the starting address of the invalid instruction is equal to the stacked PC- I. If UFO = I, the
starting address of the invalid instruction is equal to the stacked
PC-2. Fig. 21 shows TRAP Timing.
Note that Bus Release cycle, Refresh cycle, DMA cycle and
WAIT cycle can't be inserted just after TTP state which is inserted
for TRAP interrupt sequence.
=
~HITACHI
462
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
Restart from OOOOH
2nd op-code
~Ch cycle
Op-code
fetch cycle
IT1---T1TP
Ao-A18
00-07
TIFf
~~----------~----
W
m5
~ ---r--------~--------------~--~
Figure 21 (a) TRAP Timing - 2nd Op-code Undefined
Restart from OOOOH
Ao-Al.
IX
PC
SP-1
IX+d,IY+d
r-\
00-07
PC
'--/
1H
H
OOOOH
PC-1L
Undefined
op-code
-
- h
-
SP-2
h
~ tt-
I
I
rh
rh
j
l
rn
rn
r t-
l
r t-
I
L.JIL---1
Figure 21 (b) TRAP Timing - 2nd Op-code Undefined
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy • Brisbane, CA 94005-1819. (415) 589-8300
463
HD64180R/Z
-------------------------------------------------------------
8.3 External Interrupts
(5) Execution commences ~cal address 0066H.
The last instruction of an NMI service routine should be RETN
(Return from Non-maskable Interrupt). This restores the stacked
PC, allowing the interrupted program to continue. Furthermore,
RETN causes IEF, to be copied to IE~storing the interrupt reception state that existed prior to the NMI.
Note that NMI, since it can be accepted during HD64180 onchip DMAC o~ion, can be used to externally interrupt DMA
transfer. The NMI service routine can reactivate or abort the
DMAC ~ation as required by the application.
For NMI, special care must be taken to insure that interrupt
inputs do not 'overrun' the NMI service routine. Unlimited NMI
inputs without a corresponding number of RETN instructions will
eventually cause stack overflow.
Fig. 22 shows the use of ~ and RETN while Fig. 23 details
NMI r~se timing. NMI is edge sensitive and the internally
latched NMI falling edge is held until it is sampled. If the falling
edge of NMI is latched before the falling edge of clock state ~ to
T, or Ti in the last machine cycle, the internally latched NMI is
sampled at the falling e~ofthe clock state prior to Ta or Ti in the
last machine cycle and NMI acknowledge cycle begins at the end of
the current machine cycle.
The HD64180 has four external hardware interrupt inputs.
(I) NMI - Non-maskable Interrupt
(2) Q!1 - Maskable Interrupt Level 0
(3) INT, - Maskable Interrupt Levell
(4) iiiiT.-=...Maskable Interrupt Level 2
__
NMI, INT, and INT, have fixed interrupt response modes. INT.
has three different software programmable interrupt response modes - Mode 0, Mode 1 and Mode 2.
8.4
IiiMI -
Non-Maskable Interrupt
The NMI interru£!..!!!.put is edge sensitive and cannot be masked
by software. When NMI is detected, the HD64180 operates as follows.
(I) DMAC operation is suspended by clearing the DME (DMA
Main Enable) bit in DCNTL.
(2) The PC is pushed onto the stack.
(3) The contents of IEF, are copied to IEF2 • This saves the interrupt reception state that existed prior to NMI.
(4) IEF, is cleared to O. This disables all external and internal
maskable interrupts (i.e. all interrupts except NMI and
TRAP).
main
program~
IEF, -IEF2
-IEF,
PCH -(SP-1)
PCl -(SP-2)
0
NMI
Interrupt service
program
NMI--
TI
IEF,
PCl -(SP)
PCH -(SP+ 1)
RETN
F,gure 22 NMI Sequence
last MC
NMI acknowledge cycle
PC is pushed onto stack
_ _-'x'-_--'P...:C'--_~
X
SP-l
Restart from 0066H
Op-code fetch
X SP-2 X 0066H
x==
Instruction
00-07
(
PCH
)-(
PCl
>----0
\---1
Figure 23 NMI Timing
~HITACHI
464
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
6.& INTo - Maskable Intarrupt Level 0
--Ihe next highest priority external interrupt after NMI is INTo.
INTo is sampled at the fallini!.!!ge of the clock state prior to T 3 or Ti
in the last machine cycle. If INTo is asserted LOW at the falli~ge
of the clock state prior to T, or Ti in the last machine cycle, INTo is
accepted. The interrupt is masked if either the IEF, flag or the ITEO
(Interrupt Enable 0) bit in ITC are cleared to O. Note that after RESET the state is as follows.
0) IEF, is 0, so I~ is masked.
(2) ITEO is I, so INTo is enabled by execution of the EI (Enable
Interrupts) instruction.
The INTo interrupt is unique in that three programmable mterrupt response modes are available - Mode 0, Mode I, and Mode 2.
The specific mode is selected wIth the 1M 0, 1M I and 1M 2 (Set Interrupt Mode) instructions. During RESET, the HD64180 is
initialized to use Mode 0 for INTo.
Last MC
The three
T,
RST instruction execution
"·11
T2 Tw' Tw' T3
response modes for INTo are ...
INTo Mode 0
During the interrupt acknowledge cycle, an instruction is fetched
from the data bus (00 -07 ) at the nsing edge of T,. Often, this instruction is one of the eight single byte RST (REST ART) instructions which stack the PC and restart execution at a fixed logical address. However, multibyte instructions can be processed if the interrupt acknowledging device can provide a multi byte response.
Unlike all other interrupts, the PC IS not automatically stacked.
Note that TRAP interrupt will occur if an invalid instruction is
fetched during INTo Mode 0 interrupt acknowledge.
Fig. 24 shows INI. Mode 0 Timing.
liNT 0 acknowledge cyclel
......
10 terrupt
0) Mode 0 - Instruction fetch from data bus.
(2) Mode I - Restart at logical address 0038H.
(3) Mode 2 - Low byte vector table address fetch from data bus.
Ti
r
Ti
T,
PC is pushed onto stack
T2
T3
T,
T2
T3
WID
_:\~/~__________
Ao-A,.
____~X~______~PC~____~X~~S~P-~1~~
\'-___---'1
RST instruction
00-07
------------~c=)~-----{(~PC~Hc=~
MC: Machine Cycle
• Two wait states are automatically inserted.
Figure 24 INT ~ Mode 0 Timing IRST InstructIon on the Data Bus)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
465
HD64180R/Z
instruction followed by the RET! (Return from Interrupt) instruction, so that the interrupts are reenabled. Fig. 25 shows the use of
INT. (Mode 1) and RET!.
Fig. 26 shows INTo Mode 1 timing.
INTO ModU
When INT. is received, the PC is stacked and instruction execution restarts at logical address 0038H. Both IEF, and IEF, flags are
reset to 0, disabling all maskable interrupts. The interrupt service
routine should normally terminate with the EI (Enable Interrupts)
o
PCH
pel
-IEF.,IEf2
-(SP-l)
-(SP-2)
INTo (Mode 1)
In1errupt service
program
EI
(1 -
IEh IEF,)
RETI
Figure 25 flilT;Mode 1 Interrupt Sequence
me; acknowledge cycle
last MC
Op-code fetch cycle
PC is pushed onto stack
Ao-A1B _ _~"X,-
___P_C:.-.___X
SP-1
X
SP-2
X 0038H C
''-___-'1
~
00-07
ST
---------<
PCH
X
PCl
>---CJ--
\'-___-'1
• Two wait states are automatically inserted.
Figure 26 INT oMode 1 Timing
.HITACHI
466
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
and CPU acquires the 16-bit vector.
Next, the PC is stacked. Finally, the 16-bit restart address is
fetched from the vector table and execution commences at that address.
Note that external vector acquisition is indicated by L1R and
IOE both LOW. Two wait states (Tw) are automatically inserted for
external vector fetch cycles
During RESET the Interrupt Vector Register (I) is initialized to
OOH and, if necessary, should be set to a different value prior to the
occurrence of a TNT;, Mode 2 interrupt. Fig. 28 shows INTo Mode 2
interrupt Timing.
INTO Mode 2
This method determines the restart address by reading the contents of a table residing in memory. The vector table consists of up
to 128 two-byte restart addresses stored in low byte, high byte
order.
The vector table address is located on 256 bytes boundaries in
the 64k bytes logical address space as programmed in the 8-bit Interrupt Vector Register (I). Fig. 27 shows the INTo Mode 2 Vector
acquisition.
During INTo Mode 2 acknowledge cycle, first, the low-order 8
bits of vector is fetched from the data bus at the rising edge of T,
Memory
16-bit Vector
Interrupt Vector
Register I
a-bit on
Data Bus
+
1
High-order a bits
of starting address
Vector
Low-order a bits
of starting address
Vector
256 Bytes
Vector
Table
Offset
-
Figure 27 tNT 0 Mode 2 Vector Acquisition
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
467
HD64180RlZ
Last MC
OP-code
fetch cycle
INTo acknowledge cycle
Vector lower
address read
J PC is pushed onto stacklInterrupt manipulation
cycle
I
I
I
T1 T2 Tw"Tw"T3 Ti T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
Starting add res':.
Ao-A18
=:::J(I-__';"'PC",--_~X
SP-l
X
SP-2
X Vector
'f,Yr"-ec-to-r-:"+-"',X
)C
~
00-07
ST
Starting address Starting address
Lower vector
(lower address) (upper address)
>---~Jp~C~H[) r-~PC~L~
,'-----'/
• Two wait states are automatically inserted.
Figure 28 INTo Mode 2 Timing
6.6 INT 1 .INTz
_
__
The operation o( external interrupts INT, and I.!f!..is a vector
mode similar to INT. Mode 2. The difference is that INT, and INT,
generate the low-order byte of vector table address using the I~ (Interrupt Vector Low) register rather than fetching it from the data
bus. This is also the interrupt response sequence used for all internal interrupts (except TRAP).
As shown in Fig. 29 the low-order byte of vector table address is
comprised of the most significant three bits of the software programmable IL register and the least significant five bits which are a
unique fixed value for each interrupt (I"iij'I';", INT, and internal)
source.
INT, and INT, are globally masked by JEF, = O. Each is also individually maskable by respecllvely clearing the !TEl and ITE2
(bits 1,2) of the INT/TRAP control register to O.
During RESET, IEF" !TEl and ITE2 bits are initIalized to O.
6.7 Internal Interrupts
Internal interrupts (except TRAP) use the same vectored response mode as INT, and INT,' (Fig 29). Internal interrupts are
globally masked by IEF, = O. Individual internal interrupts are
enabled/disabled by programming each individual I/O (PRT,
DMAC, CSI/O, ASCI) control register. The lower vector of INT, ,
INT" and internal interrupt are summarized in Table 3.
~HITACHI
468
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
Memory
H
16-bit Vector
II.
I
I
Fixed Code
" (5 bits)
"
Vector
+
1
High-order 8 bits
of starting eddress
32 Bytes
Vector
L -____________
Low-order 8 bits
Vector
~·l_~
table
Figure 29 INT ,. INT 2 and Internal Interrupts Vector Acquisition
Table 3 Interrupt Source and Lower Vector
Interrupt Source
Priority
Highest
INT,
iN'!':
PRT channel 0
PRT channel 1
DMA channel 0
DMA channel 1
CSI/O
ASCI channel 0
ASCI channell
Lowest
• Programmable
•
IL
b7
b.
·
· ·
·
· ·
· ·
· ·
· ·
· ·
· ·
Fixed Code
b.
·
·
·
·
·
·
·
·
b.
b3
b2
b,
bo
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
469
HD64180R/Z
Interrupt Acknowledge Cycle Timing
ed~ clock
Fig. 30 shows int~t acknowle~~ycle timing for internal interrupts, INT" and INT,. INT, and INT, are sampled at the falling
Last MC -
r
TI
state prior to T3 or Ti in the last machine cycle. If INT,
or INT, is asserted LOW at the falling edge of clock state prior to T,
or Ti in the last machine cycle, the interrupt request is accepted.
Op-code
fetch Cy~
IN'fi. INT,. Intemallnterrupt acknowledge cycle
-~----'--~------'--
__P~C~S~ta~c_k_in~g_ _ _~____v_ac_t_o_r_T_a_b~_R_e_ed_ _'-i
T,
Tw· Tw·
Ta
ITI
rT'
T,
Ta
ITI
T,
T3
ITI
T,
Ta
T,
T,
T3
I
Starting
address
Ao-A16
SP-1
PC
SP-2
Vactor
Vactor+ 1
Do-D7~------+----------------+--1-~==~~~
ST
MC' Machine
• Two wait states are automatically inserted.
Cyc~.
Figure 30 INT I' INT, and Internal Interrupts Timing
6.8 Interrupt Sources and Reset
(4) ITC Register
(1) Interrupt Vector Register Ul
All bits are reset to O.
Since I = 0 locates the vector tables starting at logical address
OOOOH, vectored interrupts (INTo Mode 2, INT" INT, and internal
interrupts) will overlap with fixed restart interrupts like RESET (0),
NMI (0066H), INTo Mode I (0038H) and RST (OOOOH - 0038H).
The vector table (s) can be built elsewhere in memory and located
on 256 bytes boundaries by reprogramming I with the LO I, A instruction.
(2)
IL Register
Bits 7 - 5 are reset to O.
The IL Register can be programmed to locate the vector table for
INT" INT, and internal interrupts on 32 bytes sub-boundaries
within the 256 bytes area specified by I.
(3) IEF,. IEF2 Flags
Reset to O.
Interrupts other than NMI and TRAP are disabled.
•
470
ITEO are set to I. ITEI and ITE2 are reset to O.
INTo can be enabled by the EI instruction, which sets IEF, = I.
To enable INT, and INT, also requires that the ITEI and ITE2 bits
be respectively set = I by writing to ITC.
(S) 1/0 Control Registers
Interrupt enable bits reset to O.
All H064180 on-chip 110 (PRT, OMAC, CSIIO, ASCI) interrupts are disabled and can be individually enabled by writing to each
1/0 control register interrupt enable bit.
6.9 Difference between INTo interrupt and the other interrupts UN'i';. INT2 and internal interrupts) in the interrupt
acknowledge cycles
As shown in Fig. ~Fig. 26, Fig. 28 and Fig. 30, the interrupt
acknowledge ~ofI~ is different from those of the other interrupts, that is, INT" INT, and internal interrupts concerning the
state of control signals. The state of the control signals in each interrupt acknowledge cycle are shown below.
INTo interrupt acknowledge cycle: LIR = 0, IOE = OdT = 0
INT" INT" and internal interrupt acknowledge cycle: LIR = I,
IOE = I, ST = 0
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300
HD64180R/Z
7 MEMORY MANAGEMENT UNIT IMMUI
The "D64180 contains an on-chip MMU which performs the
translation of the CPU 64k bytes 06-bit addresses- OOOOH to
FFFFH) logical memory address space into a 512k bytes 09-bit addresses- OOOOOH to 7FFFFH) physical memory address space. Address translation occurs internally in parallel with other CPU operation.
Common Area 1
Common Area 1
7.1 Logical Address Spaces
The 64k bytes CPU logical address space is interpreted by the
MMU as consisting of up to three separate logical address areas,
Common Area 0, Bank Area and Common Area I.
As shown in Fig. 31 a variety of logical memory configurations
are possible. The boundaries between the Common and Bank
Areas can be programmed with 4k bytes resolution.
Common Area 1
Common Area 1
Bank Area
Bank Area
Common Area 0
Common Area 0
Figure 31 Logical Address Mapping Examples
7.2 Logical to Physical Address Translation
Fig. 32 shows an example in which the three logical address
space portions are mapped into a 512k bytes physical address space.
The important points to note are that Common and Bank Areas can
overlap and that Common Area 1 and Bank Area can be freely relocated (on 4k bytes physical address boundaries). Common Area 0
(if it exists) is always based at physical address OOOOOH.
, - - - - - - - , 7FFFFH
FFFFH . . . - - - - - - - ,
Common Area 1
Bank Area
y
Common Area 0
ooooH
Logical Address Space
x ____
L-_.L~
~OOOOOH
Physical Address Space
Figure 32 Logical - Physical Memory Mapping Example
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
471
HD64180R/Z
7.3 MMU Block Diagram
The MMU block diagram is shown in Fig. 33. The MMU translates internal 16-bit logical addresses to external 19-bit physical addresses.
Internal Address/Data Bus
Memory
anagement Unit
MMU Common Base
Register; CBR (7)
MMU Bank Base
Register; BBR (7)
LA: Logical Address
PA: Physical Address
Figure 33 MMU Block Diagram
Whether address translation takes place depends on the type of
CPU cycle as follows.
(I) Memory Cycles
Address Translation occurs for all memory access cycles including instruction and operand fetches, memory data reads and writes,
hardware interrupt vector fetch and software interrupt restarts.
(2) I/O Cycles
The MMU is logically bypassed for I/O cycles. The 16-bit logical
1/0 address space corresponds directly with the 16-bit physical 110
address space. The upper three bits (A" -A,,) of the physical address are always 0 during 110 cycles.
LA15
"000"
PAlS
PA16
LAo
p~o
~A"
Logical Address
Physical Address
Figure 34 1/0 Address Translation
(3) DMA Cycles
When the HD64180 on-chip DMAC is using the external bus,
the MMU is physically bypassed. The 19-bit source and destination
registers in the DMAC are directly output on the physical address
bus (A.-A.,).
~HITACHI
472
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
HD64180R/Z
7.4 MMU Registers
Three MMU registers are used to program a specific configuration of logical and physical memory.
(J) MMU Common/Bank Area Register (CBAR)
(2) MMU Common Base Register (CBR)
(3) MMU Bank Base Register (BBR)
CBAR is used to define the logical memory organization, while
CBR and BBR are used to relocate logical areas within the 512k
bytes physical address space. The resolution for both setting boundaries within the logical space and relocation within the physical
2
Common Area 1
space is 4k bytes.
The CAR field of CBAR determines the start address of Common Area I (Upper Common) and by default, the end address of
the Bank Area. The BAR field determines the start address of the
Bank Area and by default, the enc\ address of Common Area 0
(Lower Common).
The CA and BA fields of CBAR may be freely programmed subject only to the restriction that CA may never be less than BA. Fig.
35 and Fig. 36 shows example of logical memory organizations associated with different values of CA and BA.
3
Common Area 1
4
Common Area 1
Common Area 1
Bank Area
Common Area 0
Bank Area
Common Area 0
Common Area 1
Lower limit address
Common Area 1
Lower limit address
Common Area 1
Lower limit address
=
=
Bank Area
Lower limit address
Bank Area
Lower limit address
>
>
Bank Area
Lower limit address
>
OOOOH
Bank Area
Lower limit address
Common Area 1
Lower limit address
=
=
>
OOOOH
OOOOH
OOOOH
(RESET condition)
Figure 35 Logical Memory Organization
FFFFH
MMU Common/Bank Area Register
11 111 0 11 I
0
Common Area 1
--~~~~.~~ ~-----i
07 060504
Bank Area
MMU Common/Bank Area Register
10 11 10 10]
4 --_
.. ~,~,~,~~
~-----i
OOOOH
L -_ _ _---A
03020100
Common Area 0
Figure 36 Logical Space Configuration (Example)
~HITACHI
Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
473
HD64180R/Z
MMU Common Base Register (CBR . 1/0 Address = 38H)
7.6 MMU Register Description
M'r-~-.~~.-~-,~~,-~3-.__=--r~__r-~O-'
(11 MMU Common/Bank Area Register (CBARI
CBAR specifies boundaries within the HD64180 64k bytes logical address space for up to three areas, Common Area 0, Bank
Area, and Common Area l.
=
MMU Common/Bank Area Register (CBAR . 1/0 Address
bit
7
6
BA3
BA2
BA'
BAO
RiW
RIW
RIW
RIW
CB5
C84
CB3
CB2
CB'
RIW
RIW
RIW
RIW
RIW
C80
RIW
(31 MMU Bank Base Register (BBRI
3AH)
BBR specifies the base address (on 4k bytes boundaries) used to
generate a 19-bit physical address for Bank Area accesses. All bits of
BBR are initialized to 0 during RESET.
5
gCA21
CA'
1CAO
RiW
RiW
RiW
RiW
CB6
RIW
MMU Bank Ba.. Register (BBR . VO Address = 39H)
brt
CA3-CAO: CA (bits 7-41
CA specifies the start (low) address (on 4k bytes boundaries) for
the Common Area l. This also determines the last address of the
Bank Area. All bits of CA are initialized to I during RESET
6
5
RIW
RIW
3
:"""'~886--"-=-885..,-,884-=--"-":'88~3'---=:882----'-:--88'-'-------=---:880
'.--'1
RIW
RIW
RIW
RIW
RIW
7.6 Phvsical Address Translation
BA3-BAO: BA /bits 3-01
BA specifies the start (low) ad1ress (on 4k bytes boundaries) for
the Bank Area. This also determmes the last address of the Common Area O. All bits of BA are initialized to 0 during RESET.
(21 MMU Common Base Register (CBRI
CBR specifies the base address (on 4k bytes boundaries) used to
generate a 19-bit physical address for Common Area I accesses. All
bits of CBR are initialized to 0 during RESET.
Fig. 37 shows the way in which physical addresses are generated
based on the contents ofCBAR, CBR and BBR. MMU comparators classify an access by logical area as defined by CBAR. Depending on which of the three potential logical areas (Common Area I,
Bank Area or Common Area 0) is being accessed, the appropnate
7-bit base address is added to the upper 4 bits of the logical address,
yielding a 19-bit physical address. CBR is associated with Common
Area I accesses. Common Area 0 accesses use a (non-accessible,
internal) base register which contains O. Thus, Common Area 0, if
defined, is always based at physical address OOOOOH.
15
o
1211
r-----------~--------------------------_,log~al
Address
L----,r-_.1-_ _ _ _ _ _ _--,_ _ _--l (64k)
4
MMU Common Ba.. Reg
4
18
12 11
o
Physical
Address
(512k)
Figure 37 Physical Address Generation
~HITACHI
474
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
7.7 MMU and RESET
8 DYNAMIC RAM REFRESH CONTROL
During RESET, all bits of the CA field of CBAR are set to I
while all bits of the BA field of CBAR, CBR, and BBR are cleared to
O. The logical 64k bytes address space corresponds directly with the
first 64k bytes (OOOOH to FFFFH) of the 512k bytes (OOOOOH to
7FFFFH) physical address space. Thus, after RESET, the
HD64180 will begin execution at logical and physical address O.
The HD64180 incorporates a dYnamic RAM refresh control circuit Including 8-bit refresh address generation and programmable
refresh lIming. This CIrcuit generates asynchronous refresh cycles
inserted at the programmable interval independent of CPU program execution. For systems which don't use dynamic RAM, the
refresh function can be disabled.
When the internal refresh controller determines that a refresh
cycle should occur, the current instruclIon is interrupted at the first
breakpoint between machine cycles. The refresh cycle is inserted by
plaCing the refresh address on Ao- A7 and the REF output is driven
LOW.
Refresh cycles may be programmed to be either two or three
clock cycles in duration by programming the REFW (Refresh Wait)
bit in Refresh Control Register (RCR). Note that the external
WAlT input and the internal wait state generator are not effective
during refresh
Fig. 38 shows the lIming of a refresh cycle with a refresh wait
(TRW) cycle.
7.8 MMU Register Access Timing
When data is written into CBAR, CBR, or BBR, the value will
be effective from the cycle immediately following the 1/0 write cycle
which updates these registers.
Care must be taken during MMU programming to insure that
CPU program execution is not disrupted. Observe that the next cycle following MM U register programming will normally be an opcode fetch from the newly translated address. One simple technique
is to localize all MMU programming routines in a Common Area
that is always enabled.
MCi+1
Refresh cycle
MCi
TRW'
Refresh signal ~
(Internal signal)
T R2
\\.._ _ _ _ _ __
X
Refresh address
AD - A 7
X'-_____
\10-_____-11
NOTE: • If three refresh cycles are specified, TRW, is inserted.
Otherwise, TRW is not inserted.
MC: Machine Cycle
Figure 38 Refresh Timing
8.1 Refresh Control Register (RCRI
REFW: Refresh Wait (bit 61
RCR specifies the interval and length of refresh cycles, as well as
enabling or disabling the refresh function.
REFW = 0 causes the refresh cycle to be two clocks in duration.
REFW = I causes the refresh cycle to be three clocks in duration
by adding a refresh wait cycle (TRW)' REFW is set to I during RESET.
Refresh Control Ragister (RCA. 1/0 Address
=
36H)
o
eye1
CYCO
RIW
RIW
CYC 1, 0: Cycle Interval (bits 1-01
REFE: Refresh Enable (bit 71
REFE = 0 disables the refresh controller while REFE = I enables refresh cycle insertion. REFE is set to I during RESET.
•
CYCI and CYCO specify the interval (in clock cycles) between
refresh cycles.
In the case of dynamic RAMs requiring 128 refresh cycles every
2 ms (or 256 cycles every 4 ms), the required refresh interval is less
than or equal to 15.625I-'s. Thus, the underlined values indicate the
best refresh interval depending on CPU clock frequency. CYCO and
CYCl are cleared to 0 during RESET .
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
475
HD64180R/Z
Table 4 Refresh Interval
Time interval
CYC1
CYCO
Insertion
interval
: 10MHz
8 MHz
6MHz
4MHz
2.5 MHz
0
0
1
1
0
1
0
1
10 states
20 states
40 states
80 states
(1.0/-,s)"
(2.0/-,s)"
(4.0/-,s)"
(8.0/Ls)"
(1.25/-,s)"
(25/-,s)"
(5.0/-,s)"
(100/Ls)"
1.66/-,s
3.3/-,s
6.6/-,s
133/Ls
2.5/-,s
5.0/-,s
10.0/Ls
20.0/-,$
16.0/-,s
32.0/-,$
4.0/-,s
~
" calculated interval
8.2 Refresh control end reset
After RESET, based on the initialized value of RCR, refresh cycles will occur with an interval of 10 clock cycles and be 3 clock cycles in duration.
8.3 Dynamic RAM refresh operation notes
(I) Refresh cycle insertion is stopped when the CPU is in the fol-
lowing states.
(a) During RESET
_ __
(b) When the bus is released in response to BUSREQ
(c) During SLEEP mode
(d) During WAlT states
(2) Refresh cycles are suppressed when the bus is released in response to BUSREQ. However, the refresh timer continues to
operate. Thus, the time at which the first refresh cycle occurs
after the HD64180 re-acquires the bus depends on the refresh
timer, and has no timing relationship with the bus exchange.
(3) Refresh cycles are suppressed during SLEEP mode. If a refresh
cycle is requested during SLEEP mode, the refresh cycle request is internally 'latched' (until replaced with the next refresh request). The 'latched' refresh cycle is inserted at the end
of the first machine cycle after SLEEP mode is eXited. After
this initial cycle, the time at which the next refresh cycle will
occur depending on the refresh time, and has no timing relationship with the exit from SLEEP mode.
(4) Regarding (2) and (3), the refresh address is incremented by I
for each successful refresh cycle, not for each refresh request.
Thus, independent of the number of 'missed' refresh requests,
each refresh bus cycle will use a refresh address incremented
by I from that of the previous refresh bus cycles.
9 WAIT STATE GENERATOR
9.1 Wait State Timing
To ease interfacing with slow memory and I/O devices, the
HD64180 uses wait states (Tw) to extend bus cycle timing. A wait
state(s) is inserted based on the combined (logical OR) state of the
external WAlT input and an internal programmable wait state (Tw)
generator. Wait states (Tw) can be inserted in both CPU execution
and DMA transfer cycles.
9.2 WAIT Input
When the external WAlT input is asserted LOW, wait state
(Tw) are inserted between T, and T, to extend the bus cycle duration. The WAlT input is sampled at the falling edge of the system
clock in T, or Tw. If the WAlT input is asserted LOW at the falling
edge of the system clock in Tw, another Tw is inserted into the bus
cycle. Note that WAlT input transitions must meet specified set-up
and hold times. This can easily be accomplished by externally synchronizing WAlT input transitions with the rising edge of the system clock.
Dynamic RAM refresh is not performed during wait states (Tw)
and thus systems designs which uses the automatic refresh function
must consider the affects of the occurrence and duration of wait
states (Tw).
Fig. 39 shows WAlT tim mg.
I
,
,I
I
I
\ C\i, / Ii \
_ _ _ _ _ _~..L---->-;_...<'---
I
\..----------
Figure 39 WAIT Timing
@HITACHI
476
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
9.3 Programmable Wait State Insertion
In addition to the WAIT input, wait states (Tw) can also be programmably inserted using the HD64180 on-chip wait state generator. Wait state (Tw) timing applies for both CPU execution and
on-chip DMAC cycles.
By programming the 4 significant bits of the DMA/W AIT Control Register (DCNTL), the number of wait states (Tw) automatically inserted in memory and I/O cycles can be separately specified.
Bits 4-5 specify the number of wait states (Tw) inserted for I/O access and bits 6-7 specify the number of wait states (Tw) inserted for
memory access.
number automatically generated by the on-chip wait state generator.
MWI1, MWIO: Memory Wait Insertion (bits 7-6)
For CPU and DMAC cycles which access memory (including
memory mapped I/O), 0 to 3 wait states may be automatically inserted depending on the programmed value in MWIl and MWIO.
RIW
I ~~ I ~, I :~ I :
RIW
RIW
MWIO
The number of wait states
0
0
0
,
,
,
,
0
2
0
DMAIWAIT Control Register
(DCNTL VO Address = 32H)
b''r M:11
MWll
,
3
IWI1, IWIO: I/O Wait Insertion (bits 5-4)
For CPU and DMA cycles which access external I/O (and interrupt acknowledge cycles), I to 6 wait states (Tw) may be automatIcally inserted depending on the programmed value in IWIl and
IWIO.
RfW
The number of wait states (Tw) inserted in a specific cycle is the
maximum of the number requested by the WAIT input, and the
The number of wait states
For external 110
registers accesses
IWI'
0
IWIO
0
,
,
,
1
2
,
3
0
NOTE.
0
For internal 110
registers accesses
For INT 0 interrupt
acknowledge cycles when LlR is
lOW
For INT l ' INT, and
internal interrupts
acknowledge cycles
(Note (2»
For NMI interrupt
acknowledge cycles when LlR is
lOW
(Note (2))
2
0
(Note (1»
4
4
5
2
0
6
(1) For HD64' 80 Internal I/O register access 11/0 addresses 0000H-003FHI. IWI, and IWIO do not determine wait state ITw) timing For ASCI. CSI/
and PRT Data Register accesses, 0 to 4 walt states (Tw) Will be generated Walt states Inserted during access to these registers IS a function
o
of Internal synchronization requirements and CPU state
All other on-chip I/O register accesses he MMU. DMAC, ASCI Control Registers, etc) have 0 wait states IOserted and thus require only three
clock cycles
(2) For Interrupt acknowledge cycles 10 which UR IS HIGH, such as mterrupt vector table read and PC stacking cycle, memory access timing apphes.
9.4 WAIT Input and RESET
During RESET, MWIl, MWIO, IWIl and IWIO are all set to I,
selecting the maximum number of wait states (Tw) (3 for memory
accesses, 4 for external I/O accesses).
Also, note that the WAIT input is ignored during RESET. For
example, if RESET is detected while the HD64180 IS in a wait state
(Tw), the wait stated cycle In progress will be aborted, and the RESET sequence initiated. Thus, RESET has higher priority than
WAIT.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
477
HD64180R/Z
Channel 0
· Memory _ _ memory, memory _ _ 110, memory _ _
memory mapped I/O transfers
· Memory address increment, decrement, no-change
- Burst or cycle steal memory _ _ memory transfers
· DMA to and from both ASCI channels
· Higher priority than DMAC channell
10 DMA CONTROLLER (DMAC)
The H064180 contains a two channel OMA (Direct Memory
Access) controller which supports high speed data transfer. Both
channels (channel 0 and channel J) have the following capabilities.
Memory Address Space
Memory source and destination addresses can be directly specified anywhere within the S12k bytes physical address space using
19-bit source and destination memory addresses. In addition,
memory transfers can arbitrarily cross 64k bytes physical address
boundaries without CPU intervention.
Channell
· Memory _ _ I/O transfer
· Memory address increment, decrement
I/O Address Space
I/O source and destination addresses can be directly specified
anywhere within the 64k bytes I/O address space 06-bit source and
destination 110 addresses).
DMAC Registers
Each channel of the DMAC (channel 0, J) has three registers
specifically associated with that channel.
Transfer Length
Up to 64k bytes can be transferred based on a 16-bit byte count
register.
Channel 0
SARO
DARO
BCRO
Source Address Register
Destination Address Register
Byte Count Register
DREQ Input
Level and edge sense OREQ input detection are selectable.
TEND Output
Used to indicate DMA completion to external devices.
Cllllnnill
Transfer Rate
Each byte transfer can occur every six clock cycles. Wait states
can be inserted in DMA cycles for slow memory or 110 devices. At
the system clock (t/» = 6 MHz, the DMA transfer rate is as high as
1.0 megabytes/second (no wait states).
Additional feature disk for DMA interrupt request by DMA
END.
Each channel has the following additional specific capabilities.
The two channels share the following three additional registers
in common.
DSTAT
DMA Status Register
DMODE - DMA Mode Register
DCNTL - DMA Control Register
MARl
IARI
BCRI
Memory Address Register
I/O Address Register
Byte Count Register
10.1 DMAC Block Diagram
Fig. 40 shows the HD64180 DMAC Block Diagram.
Internal Address/Data Bus
~}
B
DMA Source Address
Register chO : SARO (19)
DMA Status
Register : DSTAT (8)
DMA Destination Address
Register chO : DARO (19)
DMA Mode
RegIster : DMODE (8)
DMA Byte Count
Register chO : BCRO (16)
DMAlWAlT Control
Register : DCNTL (8)
DMA Memory Address
Register ch1 : MAR1 (19)
DMA Control
-
DREaD
-
DREa,
I
I
DMA VO Address
Register ch 1 : IAR 1 (16)
DMA Byte Count
Register chl : BCRl (16)
Priority 8<
Request
Control
r--
Bus & CPU
Control
IL_~JI1911 l~1E,t._
Figure 40 DMAC Block Diagr$m
f>HlTACHI
478
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
HD64180R/Z
10.2 DMAC Register Description
(1) DMA Source Address Register Channel 0 (SARO: I/O Address = 20H to 22H)
Specifies the physIcal source address for channel 0 transfers. The
regIster contaInS 19 bIts and may specify up to SI2k bytes memory
addresses or up to 64k bytes I/O addresses. Channel 0 source can
be memory, I/O or memory mapped I/O
(2) DMA Destination Address Register Channel 0 (DARO: I/O
Address = 23H to 25H)
Specifies the physical destination address for channel 0 transfers.
The register contains 19 bits and may specify up to SI2k bytes
memory addresses or up to 64k bytes I/O addresses. Channel 0 destmation can be memory, I/O or memory mapped I/O.
(3) DMA Byte Count Register Channel 0 (BCRO: I/O Address
= 26H to 27H)
Specifies the number of bytes to be transferred. This register
contains 16 bits and may specify up to 64k bytes transfers. When
one byte IS transferred, the register is decremented by one. If "n"
bytes should be transferred, "n" must be stored before the DMA
operation.
(4) DMA Memory Address Register Channel 1 (MAR1: I/O
Address = 28H to 2AH)
Specifies the physical memory address for channel I transfers.
This may be destination or source memory address.
This regIster contams 19 bIts and may specify up to S12k bytes
memory addresses.
(5) DMA I/O Address Register Channel 1 (tAR1: I/O Address
= 2BH to 2CH)
Specifies the I/O address for channel I transfers. This may be
destination or source I/O address. This register contains 16 bits and
may specify up to 64k bytes I/O addresses.
(6) DMA Byte Count Register Channel 1 (BCR 1: I/O Address
= 2EH to 2FH)
Specifies the number of bytes to be transferred. This register
contains 16 bits and may specify up to 64k bytes transfers. When
one byte is transferred, the register is decremented by one.
DMA Status Register (DSTAT)
DST A T is used to enable and disable DMA transfer and DMA
termination mterrupts. DST AT also allows determining the status
of a DMA transfer i.e. completed or in progress.
(DIEO = I), a DMA interrupt request is made to the CPU.
To perform a software write to OEO, DWEO should be written
with 0 during the same register wnte access. Writing DEO to 0 disables channel 0 DMA. Writing OEO to I enables channel 0 DMA
and automattcally sets OME (OM A Main Enable) to 1. DEO is
cleared to 0 during RESET.
DWE1: DE1 Bit Write Enable (bit 5)
~
When performing any software write to DEI, OWEI should be
written with 0 during the same access. OWEI write value of 0 is not
held and DWEI is always read as I.
OWED: OED Bit Write Enable (bit 4)
When performmg any software write to OEO, DWEo should be
written with 0 during the same access. DWEO write value of 0 is not
held and DWEO is always read as I.
DIE 1: DMA Interrupt Enable Channel 1 (bit 3)
When DIEI is set to I, the termination of channell DMA transfer (jndlcated when OEI = 0) causes a CPU interrupt request to be
generated. When DIEI = 0, the channell DMA termination interrupt is disabled. DIE! IS cleared to 0 during RESET.
DIED: DMA Interrupt Enable Channel 0 (bit 2)
When DIEO is set to I, the termination channel 0 of DMA transfer (jndicated when OEO = 0) causes a CPU interrupt request to be
generated. When DIEO = 0, the channel 0 DMA termination interrupt is disabled. DIEO is cleared to 0 during RESET.
DME: DMA Main Enable (bit 0)
A DMA operation is only enabled when its DE bit (DEO for
channel O...QgI for channel I) and the DME bit are set to 1.
When NMI occurs, DME is reset to 0, thus disabling DMA activity during the NMI interrupt service routine. To restart DMA,
OEO and/or DEI should be written with I (even if the contents are
already I). This automatically sets DME to I, allowing DMA operations to continue. Note that DME cannot be directly written. It is
cleared to 0 by NMI or indirectly set to I by setting DEO and/or
DEI to I. DME is cleared to 0 during RESET.
(8) DMA Mode Register (OM ODE)
DMODE is used to set the addressing and transfer mode for
channelO.
(7)
DMA Status Register (OST AT
OMA Mode Register (OMODE
VO Address = 31 H)
~tr-~-.--~-r~--~~-'r-~-r~~'-~--r-~-'
VO Address = 30H)
OM'
oMO
SM,
SMO
RIW
RIW
RIW
RIW
I
MMOo
I
RIW
4
bot
DE'
oEO
OWE1
OWEO
RIW
RIW
W
W
I
DIE1
OlEO
RIW
RIW
oME
DE1: DMA Enable Channel 1 (bit 7)
When DEI = I and DME = I, channel I DMA is enabled.
When a DMA transfer terminates (BCRI = 0), DEI is reset to 0
by the DMAC. When DEI = 0 and the DMA interrupt is enabled
(DIEI = I), a DMA interrupt request is made to the CPU.
To perform a software write to DEI, DWEI should be written
with 0 during the same register write access. Writing DEI to 0 dIsables channel I DMA, but DMA is restartable. Writing OEI to I
enables channel I OMA and automatically sets DME (OMA Main
Enable) to 1. DEI is cleared to 0 during RESET.
DM1, DMO: Destination Mode Channel 0 (bits 5, 4)
Specifies whether the destination for channel 0 transfers is
memory, I/O or memory mapped 110 and the corresponding address modifier. DM I and OMO are cleared to 0 during RESET.
Table 5 Destination
DMI
DMO
Memory/I/O
Address
Increment/Decrement
0
0
0
1
0
Memory
Memory
Memory
110
+1
-1
fixed
fixed
1
1
1
OED: DMA Enable Channel 0 (bit 6)
When DEO
I and DME
I, channel 0 DMA is enabled.
When a DMA transfer terminates (BCRO 0), DEO is cleared to 0
by the DMAC. When OEO
0 and the DMA interrupt is enabled
=
=
=
=
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
479
HD64180R/Z
SM1. SMO: Source Mode Channel 0 (bits 3. 21
Specifies whether the source for channel 0 transfers is memory,
I/O or memory mapped I/O and the corresponding address
modifier. SM I and SMO are cleared to 0 during RESET.
Table 7 shows all DMA transfer mode combinations of DMO,
DMI, SMO, SM!. Since 1/0 ~ 1/0 transfers are not implemented, twelve combinations are available.
Table 6 Source
SMI
SMO
Memory/I/O
Address
Increment/Decrement
0
0
1
1
0
1
0
1
Memory
Memory
Memory
I/O
+1
-1
fixed
fixed
Table 7 Combination of Transfer Mode
DMI
DMO
SMI
SMO
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
Address
Increment/Decrement
Transfer Mode
Memory-Memory
Memory-Memory
Memory"-Memory
I/O-Memory
Memory-Memory
Memory-Memory
Memory"-Memory
I/O-Memory
Memory-Memory"
Memory-Memory"
1
0
1
0
1
0
1
0
SARO+ 1, DARO+ 1
SARO- 1, DARO+ 1
SARO fixed, DARO+ 1
SARO fixed, DARO+ 1
SARO+ " DARO-1
SARO-1. DARO-l
SARO fixed, DARO-l
SARO fixed, DARO- 1
SARO+ 1. DARO fixed
SARO- 1, DARO fixed
reserved
reserved
Memory-I/O
Memory-I/O
1
0
1
SARO+ " DARO fixed
SARO- 1, DARO fixed
reserved
0
1
reserved
" : includes memory mapped I/O
MMOD: Memory Mode Channel 0 (bit 11
When channel 0 is configured for memory ~ memory
transfers, the external DREQo input is not used to control the transfer timing. Instead, two automatic transfer timing modes are selectable - burst (MMOD = 1) and cycle steal (MMOD = 0). For
burst memory ~ memory transfers, the DMAC will sieze control of the bus continuously until the DMA transfer completes (as
shown by the byte count register = 0). In cycle steal mode, the
CPU is given a cycle for each DMA byte transfer cycle U1ltil the
transfer is completed.
_ __
For channel 0 DMA with I/O source or destination, the DREQo
input times the transfer and thus MMOD is ignored. MMOD is
cleared to 0 during RESET.
DMA/WAIT Control Registe. (DCNTLI
DCNTL controls the insertion of wait states into DMAC (and
CPU) accesses of memory or I/O. Also, the DMA request mode for
each DREQ (DREQo and DREQ,) input is defined as level or edge
sense. DCNTL also sets the DMA transfer mode for channel I,
which is limited to memory ~ I/O transfers.
DMAIWAIT Control Reg,ster (DCNTL
bot
7
GWI1
R/W
6
I
MWM)
R/W
5
4
IIWI1 IIWIO I
A/W
RIW
110 Addres. =
32HI
o
3
OMS1
DMSO
AIW
RIW
I
DIM1
O1MO
AIW
RIW
MWI1. MWIO: Memory Wait Insertion (bits 7-61
Specifies the number of wait states introduced into CPU or
DMAC memory access cycles. MWIl and MWIO are set to I during
RESET. See section of Wait State Control for details.
IWI1. IWIO: I/O Wait 'nsertion (bits 6-41
Specifies the num ber of wait states introduced into CPU or
DMAC I/O access cycles. IWIl and IWIO are set to I during RESET. See section of Wait State Control for details.
DMS1. DMSO: DMA Request Sense (bits 3-21
DMSI and DMSO specify the DMA request sense for channel 0
(DREQo) and channel I (DREQ,) respectively. When reset to 0,
the input is level sense. When set to I, the input is edge sense.
DMSI and DMSO are cleared to 0 during RESET.
DIM 1, DIMO: DMA Channel 1 I/O and Memory Mode (bits 1-01
Specifies the source/destination and address modifier for channell memory ~ I/O transfer modes. IMI and IMO are cleared
to 0 during RESET.
Table 8 Channell Transfer Mode
DIMI
DIMO
0
0
I
0
1
0
1
1
Transfer Mode
Memory-I/O
Memory-I/O
I/O-Memory
I/O-Memory
Address
Increment/Decrement
MARl + " IARI fixed
MAR1-1.IARl fixed
IARI fixed, MARl + 1
IAR1 fixed, MARl-I
10.3 DMA Operation
This section discusses the three DMA operation modes for
channel 0, memory ~ memory, memory ~ 110 and
memory ~ memory mapped I/O.h addition, the operation of
channel 0 DMA with the on-chip ASCI (Asynchronous Serial
Communication Interface) as well as Channel I DMA are described.
~HITACHI
480
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
(1) Memory ~ Memory - Channel 0
__
For memory ~ memory transfers, the external DREQo
input is not used for DMA transfer timing. Rather, the DMA operation is timed in one of two programmable modes - burst or cycle
steal. In both modes, the DMA operation will automatically proceed until termination as shown by byte count (BCRO) = O.
In burst mode, the DMA operation will proceed until termmation. In this case, the CPU cannot perform any program execution
~~~ioUS
Ie
cyc
-I-
until the D MA operation is completed.
In cycle steal mode, the DMA and CPU operation are alternated
after each DMA byte transfer until the DMA is completed. The sequence ...
( I CPU Machine Cycle~
DMA Byte Transfer )
. is repeated until DMA is completed. Fig. 41 shows cycle steal
mode DMA limmg.
CPU cycle DMA cycle (transfer 1 byte) CPU cycle
-I-
lD 9,m
op-code address
'I"","
Source
memory address
DMA cycle
Destination
LO g,m
memory address operand address
-.JX'-___X'-__--'X'-___X'-___
Address==::)(____
LD g.m
Read data
Wnte data
m
DATA
Figure 41 Cycle Steal Mode DMA Timing
To initiate memory ~ memory DMA transfer for channel
0, perform the following operations.
CD Load the memory source and destination addresses into SARO
and DARO.
(2) Specify memory +160
320
640
1280
2560
5120
10240
1
1
-
Ic: 16
64
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
+1
2
4
8
16
32
64
<1>+640
1280
2560
5120
10240
20480
40960
1
1
1
16
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
: 1
2
4
8
16
32
64
<1>: 480
960
1920
3840
7680
15360
30720
1
I
I
-
Ic : 16
0
: I
I
2
4
8
16
32
64
<1>+1920
3840
7680
15360
30720
61440
122880
-
<1>+30
I
: 1
2
4
8
16
32
64
1
<1>+10
1
D,v,de
Ratio
General
DivIde
Ratio
64
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1
I
1
Ic: 64
11.3 MODEM Control ~al_s__
__
ASCI channel 0 has CTSo, OCDo,~_RTSo external modem
control signals. ASCI channell has a CTS, modem control signal
which IS multiplexed with RXS pin (Clocked Serial Receive Data).
(1) CTS o : Clear to Send 0 (input)
The CTS o input allows external control (start/stop) of ASCI
channel 0 transmit operations. When CTS o is HIGH, channel 0
TORE bit is held at 0 regardless of whether the TDRO (Transmit
Data Register) is full or empty. When CTS o is LOW, TORE will reflect the state of TDRO. Note that the actual transmit operation is
not disabled by CTS o HIGH, only TORE is inhibited.
(2) DCDQ: Data Carrier Detect 0 (input}
The OCDo input allows external control (start/stop) of ASCI
channel 0 receive operations. When DCD o is HIGH, channel 0
RDRF bit is held at 0 regardless of whether the RDRO (Receive
Data Register) is full or empty. The error flags (PE, FE and OVRN
bits) are also held at O. Even after the DCDo input goes LOW, these
Baud Rate (Example)
(BPS)
<1>-6.144 -4.60B <1>=3.072
MHz
MHz
38400
19200
9600
4800
2400
1200
600
-
19200
9600
4800
2400
1200
600
300
-
9600
4800
2400
1200
600
300
150
-
MHz
4800
2400
1200
600
300
150
75
-
-
9600
4800
2400
1200
600
300
150
-
-
-
2400
1200
600
300
150
75
375
Ic: 64
CKA
I/O
Clock
Frequency
0
I
Ic
0
<1>+10
20
40
80
160
320
640
I
Ic
0
<1>+30
60
120
240
480
960
1920
I
Ic
0
<1>+30
60
120
240
480
960
1920
I
Ic
bits will not resume normal operation until the status register
(STA TO) is read. Note that this first read of STATO, while enabling
normal operation, will still indicate the DC Do input is HIGH
(OCOO bit = 1) even though it has gone LOW. Thus, the STATO
register should be read twice to insure the DC DO bit is cleared to O.
(3) RTS o : Request to Send 0 (output)
RTSo allows the ASCI to control (start/stop) another communication devices transmission (for example, by connection to that devices CTS input). RTS o is essentially a I bit output port, havlOg no
side effects on other ASCI registers or flags.
(4) CTS,: Clear to Send 1 (input}
Channell CTS, input is m..!!illPlexed with the RXS pin (Clocked
Serial Receive Data). The CTS, function is selected when the
CTS IE bit in ST~Il is set to I. When enabled, the CTS, operation
IS equivalent to CTS o'
Modem control signalhmlOg is shown in Fig. 48 (a) and Fig. 48(b).
@HITACHI
488
<1>+10
20
40
80
160
320
640
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
DCDo Pin
Status Register _ _ _ _ _ _ _ _ _ _---'
L...._ _ _ _ _ _ _ _ _ _ __
Read
Figure 48 (s) ~ Timing
110 instruction
I/O write cycle
-I
""
\--------'/
xl....._______
lITSOFlag _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
RTSoPin _________________________~)(~_ _ _ _ __
Figure 48 (b)
m's;; Timing
11.4 ASCI Interrupts
Fig. 49 shows the ASCI interrupt request generation circuit.
DCDO
RDRFO
IEF1
- - - ' r -......
OVRNO
ASCIO Interrupt
Request
PEO
FEO
RDRF1
OVRN1
PE1
ASCI1 Interrupt
Request
FE1
Figure 49 ASCI Interrupt Request Circuit Diagram
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
489
HD64180R/Z
11.5 ASCI ~ DMAC operation
Operation of the ASCI with the on-chip DMAC channel 0 requires the DMAC be correctly configured to utilize the ASCI /lags
as DMA request signals.
11.6 ASCI and RESET
During RESET, the ASCI status and control registers are
initialized as defined in the individual register descriptions.
Intemal Clock
Receive and Transmit operations are stopped dunng RESET.
However, the contents of the transmit and receive data registers
(TDR and RDR) are not changed by RESET
11.7 ASCI Clock
In external clock input mode, the external clock is dIrectly input
to the sampling rate (+ 16/+ 64) as shown in Fig. 50.
Baud Rate Selection
Prescaler
0_/_+_3_0_~~
I
¢-1
___
1_t_0_+_6_4_H
_ _+_1
E>
m
>
00 110 110
<
LD OX+dt.m
.'
S
.....
SID
01.
<
LDHJ,m
m
••
00..-"
D
01000 111
LO"",
7
ec...-..
>
>
m
"-
11011
101
OX+dtt,-gr
1JY+dt,..-vr
m-1HUoo
D
I.
m-OX+dtM
I.
m-(JY+dJM
00 "0 110
<
LD OV+d1,m
>
m
11111
101
00 110 110
<
>
>
m
LO W ..
01110 II
LD GX+dI.g
11011
101
D
,.
....... 1HUoo
'.
.......av+"'"
gr-OX+dlM
01110 IJ
<
LD OY+dl.Q
11111
101
01 110 g
<
•
>
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
517
HD64180R/Z
-
16·Bit Load
......
L_
"...
Flag
..-oNlC5
"""'-'no
Of'-code
lMMEo
LD
¥Nt,
mn
00 WWO 001
<
<
ON
LD IX, mn
m
"
>
>
11011
101
EXT
5
!NO
REG
Bytes
REG!
M'
LO IV,
mn
"
m
11111
O"",bon
AEL
3
0
•
7
6
4
2
1
0
5
Z
H
'N
N
C
mn-WWA
5
0
•
12
mo-IXo
5
0
•
12
mn-IV,.
00 100 001
<
<
5 .....
>
>
101
00100 001
<
<
"
m
>
>
LD sp, Hl
11111
001
SID
1
4
H~-SPA
LO SP.IX
11011
101
SID
2
7
tx.:t-SPR
LD SP,lV
11111
SID
2
7
IV,,-SPA
4
18
11 III 001
101
11111 001
LD _, (mn)
11 101
101
5
0
01 _ , OIl
<
<
LD Hllmn)
11011
101
010
11 111
101
010
"
m
11 101
3
15
(m!1JM-lr
S
0
4
18
LO ImnI.HL
S
0
4
18
"
m
11011
0
S
4
I.
LD 1mi'll. IV
"
m
11111
<
"
m
11M
>
>
0
S
3
0
S
4
16
>
>
101
Hr--/mn+ 1ltv.
Lr-n,ro,..
"
1XHr-(mn+ 11M
IXLr--1rntWw.
>
>
101
0
S
00 100 010
<
wwHr-lmn+
wwu--Im....
00 100 010
<
<
Imn+ llM-IVHr
ImnIM-lylt
>
>
101
00 100 010
<
<
LD 1mrV, IX
"
m
(mn+ H",,-IXHr
(mnlM-IXLr
01 wwO all
<
<
(mn-f 'ltv.-Hr
>
>
00 101
<
<
LDImn)._
"
m
0
S
>
>
00 101
<
<
LO IV, ImnI
"
m
(mlVM-wwlr
>
>
00 101 010
<
<
LO IX, Imnl
"
m
(mn+ 'lM-wwHr
4
I.
IYHr--(mn+
'1M
IYLr-(m~
>
>
(to be continued)
~HITACHI
518
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589·8300
HD64180R/Z
Block Transfer
ao-.-
......
T_
MNEMOfOCS
OP......
IMMEO
..,..
CPO
"-"
11101
101
EXT
N>
-REG
...GO
S
....
.....
....
s_
ao-.-
•
AEl
S
2
7
"'-O
(j)
I I s
I
PN=O ~-l=O
PIY= 1 BCtt-l:;:O
2=1 h=...".
Ar:;:tI..lw
z=o
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
519
HD64180R/Z
0_
Stack and Exchange
"""'"
PUSH
..........
OP·oode
MNEMONICS
.....0
PUSH zz
11 zzO
101
EXT
!NO
REG
8
......
REG
",P
5_
0_
REl
0
1
11
zzLr-ISP-2lM
2
,.
SP,,-2-SP,.
Flog
7
6
•
1
0
5
Z
H PN N
C
2
zzHr-ISP-t,,-,
PUSH IX
" all
"
101
SID
100 101
IXLt-ISP- 21..1
IXHr-(SP-l)".
SP"-2--SP,,
PUSH IV
11111
101
SID
2
11 100 101
"
IYlr-(SP- 21M
IYHr-ISP-l1r.t
SP"-2-SP,,
POP
POP "
11 zzO
001
0
5
1
•
(5P+ llr.t-zzHr
(SPiM-zzlr
SP"+2-SP,,
pop IX
11011
101
SID
2
12
11 100 001
(SP+l1t,..-IXHr
(SPIM-IXlr
SP"+2-SP,,
POPIY
11 111
101
SID
2
12
11 100 001
(SP+1)M-IYHr
(SPIr.t-IYlr
SP,,+ 2-SP"
'''''-
EX AF,AF'
00 001 000
SID
1
EX OE.HL
"
011
SID
1
EXX
11011 001
SID
1
EX ISP),Hl
11 100 011
SID
1
EX (SP),IX
1101'
101
810
2
SID
2
101
•
AF,,-AF,,'
3
DE.i-HlR
3
BCR-BC,,'
o,,-Dfo'
H.. - ...•
16
Hr-(SP+llt.t
lr-ISP,,",
11 100 011
EX ISPI,IY
11111
101
"
I.
IXH..-!SP+ 11M
1Xlr-ISPiM
fYH.---ISP+ 11M
IYLr-ISPiM
11 100 all
~HITACHI
520
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
Program Control Instruction.
"'*""""
......
00_
MOSOONCS
IMMEl)
tal
CAU....,
11001
<
<
CAU. f. mn
11.
<
<
Jump
OJNZ ,
n
m
101
m
Nl
REG
I1EGI
..
,2
REl
0
3
18
....
1
8
•
1
0
S
Z
H PN N
C
2
PCHr-ISP- 1lu
PCLr-ISP- 2lM
0
3
>
>
Off
18ff
00 010 000
<
- s_
>
>
100
n
EXT
--
0
>
....
2
91Br"01
2
7 1Br=0I
""""'!'Co
SP,,-2-SPtt
continut I ......
CAllmnf_"",
Br-1-Br
JPf,mn
11.
<
<
010
n
m
0
3
>
>
3
0.-...,
conIIrU 8r= 0
PCt!+rPCtl~O
U
mn-PC,..f."'"
conIInUe f •
.l'mn
11000 all
<
<
.l'tfU
.l'1XI
n
m
0
3
9
""""'!'Co
t-.
>
>
11101 001
0
1
3
....-!'Co
101
0
2
8
'''''-!'Co
0
2
8
IV.-!'Co
0
2
•
Pc..+r-P«<
0
2
8
continue
11011
11101 001
.I'M
11 111 101
JR,
00011 000
JRC,
00 111 000
11 101 001
< ,2
< ,2
JR NC,
,2
,2
0
>
2
2
0
>
2
2
00 100 000
< ,2
.....
2
00 101 000
<
JRNz"
>
00 110 000
<
JR Z,
>
0
>
2
2
•
•
•
•
•
•
•
C=O
PCt!+rPCt. C=l
cont1nue
c=,
PCt!+rF'Ctt C=O
~Z=O
PCt!+r~PGt
Z=1
contnII Z= 1
PC,.+rPC.! Z=O
RET
11001
001
0
1
RET.
11.
000
0
1
51. faINt
~f."'"
1
100 ....
RET I. true
2
12
1SPIor"'"
9
ISP1u-PCLr
ISP+ 'la,.-PCHr
SPrt+2-SP"
RET1
11101
101
01001
101
0
tsP+ lhrPCHr
SPtt+2-SPR
fIETN
11101
101
0
2
12
_PC"
CSP+ lJr.,r-PCHr
01000 101
SP,,+2-SP.t
EF,-EF,
(to be cont,nued)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
521
HD64180R/Z
-.........
_s
...........
00.....
IMMED
RSTv
EXT
IND
REG
REG!
"V ",
IMP
R£l
0
-,
"
flog
0 ......
,••, ,
0
H PN N
C
l
S
PCHr-ISP-H..
PCLr-ISP-21M
o-PCHr
~PC"
SPR-2-Sp,.
1/0 Instructions
"'"'"
N'UT
_S
.......
IMMEO
EXT
IND
REG
REG
m
11101
0' •
...
0
11011 0"
<
IN g,lCl
...........
OO-
'0'
000
S
0
,
•
flog
0 ......
, • , ,
4
0
C
S
l
H PN N
I
I
R
P
R
I
I
R
P
R
1Am1rA<
m-Ao-A,
Al-A.-A'5
9
1IC1r..
.......
.......
g= 110 Only the
Cr-Ao-A,
Br-Ae-A,~
mO.'"
11 101
00.
<
'0'
0
S
3
000
m
"
>
((l()mI,--...
9=110 0nIv1ht
........
......
'
m...... Ao-A,
IND
11101
'0'
0
s
,
10101 010
@
OO-A,-A'5
"
@)
x I x x I x
1IC~-(HL)y
H4f-l ...... HLt!
Br-1-Br
Cr-AG-A,
@)
a..--.Ae-A'5
INDR
"
101
10111
'0'
0
S
2
14&:iJt:(>*
12&=0)
0'0
x s x x I x
[8Or-~
a Hl«-1-.....
_0 . .
8r- t-Br
&=0
Cr-oAo-A,
Br--A,-A.s
N
11101
'0'
0
S
,
@
12
10 100 010
@)
x I x x I x
1ICIrtru..
HLtt+ l-1-iLR
Br-l-Br
...
Cr-Ao-A,
11 101
'0'
0
s
10 ,,0 010
,
@)
.......... '-A.5
141Br*0)
12(&=0)
x s x x I x
[18C1r~
H41+l-"""
_0 . .
Q
Br-1-Br
_0
Cr-Ao-At
.".... ....-A ..
(to be continued)
@
z=, "'-'=0
z=o '-'''0
@) N=' MS8ofom='
N== 0 MSB of o.tI= 0
~HITACHI
522
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180RlZ
--
0_
CUTPUr
_D
OUT~.A
DUTO PI..
"
m
INC
I1EG
FIEtI
101
10
S
D
-2
10
11101
101
00.
001
....
0_
......"""',
1
e
1
0
•
•
2
H PN N
C
2
m-Ao-Ar
101
001
m
....
>
01.
<
OTOM
EXT
" 010 011
<
OUTIC'I,Q
- ....
""......
MNEMONIC.
>
Ar-A.-A.,
•
D
•
D
10001 011
10
...... 1IICIo
Cr-Ao-Ar
Br-A.-Au
3
13
...... 1OOmIo
m-Ao-A,
•
11101 101
2
@
OO-A,-Al,
D
2
"
I
IHllM-IOOClo
I
@
I
p
I
I
"",-1-"",
Cr- l-Cr
81'-1-Br
Cr-Ao-Ar
@
OO-",-A ••
0""-
•
11101 101
10011 011
D
2
1611AtCM
141Br=e»
o [~1OOClo
""'-1-"",
••••I •
_0-
Cr-l-Cr
Br-1-Br
_0
Cr-Ao-A,
OO-A.-AI5
OTDR
11101
•
101
10111 011
D
2
14"'0
12111'=0)
_0.-1-.. .
o
["-1IICIo
HL.,a-l-+l.t1
•s ••
@
I
X
_0
Cr-Ao-Ar
Br-A.-Aul
oun
•
11101 101
10100 011
D
2
12
@
"-1IICIo
@
I
•
X
I
X
X
X
s
X
X
I
I
• ••
..... +1--.....
Br-1-Rr
Cr-Ao-Ar
OTII
11101
•
101
10110 all
@
Br-A,-A.,
D
2
14tf1A1'-QI
12_01
o [~1IICIo
"",+1-"",
I
X
-Q-
Br-l-Br
Br=O
C.....Ao-Ar
T$11O m
11101
101
01110 100
<
m
•
......A.-A"
•
>
3
12
IOOClo
m
Cr-Ao-Ar
p
OO-A.-A'5
Ito be continued)
@2=1 1Ir-l=0
Z=Q Br-l=Jf11:0
@ .... , MSB 01-= 1
N=O MSBofDatll=Q
.HITAOHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005·1819 • (415) 689.8300
623
HD64180R/Z
-.....
OUT1'UT
..-...cs
or......
.-0
OTM
11101
EXT
IND
- - - -REG
I1EGI
OM'
S
101
10
0
2
,.
10000 011
ttU,,-toOC~
....
1
••
S
2
1
0
H PN N
C
2
Q)
@
I
I
I
P
A
S
A
S
X
I
2
I
I
~+1-1«.t!
Cr+l-Cr
Br-1-Br
Cr-Ao-A1
@
OO-A.-A15
0 .....
11101
0
S
101
2
18111ir*0)
14.=0)
10010 011
Q
[~-
I
A
Hl«+1-I««
Cr+l-C,
.-1-Br
""*,
Q
until
.=0
Cr-Ao-A7
OO-A'-"15
OUTD
11101
S
101
0
2
12
10101 011
Q)
1HUu-1IIC~
"",-1-"",
@
X
I
X
X
1
•
4
1
0
S
2
H PN N
C
Br-1-Br
Cr-Ao-A1
Br-A.-A,.
Special Control Instructions
-
-
~
or.....
.-0
OM
00100 111
c...,
CC,
00 111 111
~
SCF
.
00 110 111
B
11 111 011
HAlT
01110 110
EXT
IND
REG
REG!
OM'
REl
SIO
"-
CPU
ContooI
-
@
2=1 "'-1=0
Z=O Br-l=FO
@
N= 1 MSB of Data= 1
N=O MSB of Data= 0
o.......,
s_
""""'"
......
....
P
AocumuIo""
"0
"",
1-,
---
l-Efl,1-Ef2@
101
m odeO
101
'"
01010 110
.. 2
11101
101
01011
110
HOP
SU'
m ode 1
mode 2
...s....
00 000 000
11101
S
CPU_
0.000 110
11 101
I
A
o-IEf"o-IEF2@
l' 110 011
11101
A
101
01 110 110
@ Interrupts are not sampled at the end of 01 or EI.
~HITACHI
524
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
20 INSTRUCTION SUMMARY IN ALPHABETICAL ORDER
MNEMONCS
Bytes
Machine Cycles
States
ADCA.m
2
2
6
ACe A.g
1
2
4
ADC A. (HU
1
2
6
ADC A. OX+d)
3
6
14
ACe A. OY+d)
3
6
14
ADD A.m
2
2
6
ADD A.g
1
2
4
ADD A. CHU
1
2
6
ADD A. OX+d)
3
6
14
ADD A. OY+d)
3
6
14
ADC HL.-
2
6
10
ADDHL._
1
5
7
ADDlX.xx
2
6
10
ADD fY.yv
2
6
10
ANDm
2
2
6
ANDg
1
2
4
AND CHU
1
2
6
AND OX+d)
3
6
14
AND OY+d)
3
6
14
BITb.(HU
2
3
9
BIT b. OX+d)
4
5
15
BIT b. OY+d)
4
5
15
BIT b.g
2
2
6
CALL f.mn
3
2
6
(If condition is false)
3
6
16
(If condition is true)
(to be contInued)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
525
HD64180R/Z
MNEMONICS
Bytes
States
Machine Cycles
CALL mn
3
6
16
CCF
1
1
3
CPO
2
6
12
CPDR
2
8
14
2
6
(If
BCR*O and Ar*(HUMl
12
(If BC R= 0 or Ar= (HUMl
CP (HU
1
2
6
CPI
2
6
12
CPIR
2
8
14
(If BCR*O and Ar*(HUMl
2
6
12
(If BCR= 0 or Ar= (HUMl
CP (IX+d)
3
6
14
CP OY+d)
3
6
14
CPt.
1
1
3
CPm
2
2
6
CPg
1
2
4
OM
1
2
4
DEC (HU
1
4
10
DEC IX
2
3
7
DEC IV
2
3
7
DEC (IX+d)
3
8
18
DEC OY+d)
3
8
18
DEC 9
1
2
4
DECww
1
2
4
DI
1
1
3
(to be continued)
~HITACHI
526
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
MNEMONICS
OJNZ j
Bytes
Machine Cycles
States
2
5
9 (If Br*O)
2
3
7 (If Br=O)
EI
1
1
3
EX AF,AF'
1
2
4
EX OE,HL
1
1
3
EX (SPI.HL
1
6
16
EX (SP),IX
2
7
19
EX (SP),IV
2
7
19
EXX
1
1
3
HALT
1
1
3
IMO
2
2
6
1M1
2
2
6
1M2
2
2
6
INC 9
1
2
4
INC (HU
1
4
10
INC OX+d)
3
8
18
INC OV+d)
3
8
18
INCww
1
2
4
INC IX
2
3
7
INC IV
2
3
7
IN A,(m)
2
3
9
IN g,(C)
2
3
9
INI
2
4
12
INIR
2
6
14 (If Br::FO)
2
4
12 (If Br=O)
INO
2
4
12
INOR
2
6
14 (If Br*O)
(to be continued)
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
527
HD64180R/Z
MNEMONICS
Bytes
Machine Cycles
States
INOR
2
4
12 Of Br=O)
INO g.(m)
3
4
12
JP f.mn
3
2
6
(If
3
3
f is false)
9
Of f is true)
(HU
1
1
3
JP (IX)
2
2
6
JP OY)
2
2
6
JP mn
3
3
9
JR j
2
4
8
2
2
6
JP
JR
C.;
Of condition is false)
2
4
8
Of condition is true)
JR NC.j
2
2
6
Of condition is false)
2
4
8
Of condition is true)
JR Z.j
2
2
6
Of condition is false)
2
4
8
Of condition is true)
JR NZ.j
2
2
6
Of condition is false)
2
4
8
(If condition is true)
(to be continued)
.HITACHI
528
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
Bytes
Machine Cycles
States
LD A. (BCI
1
2
6
LD A. (DEI
1
2
6
LDA.I
2
2
6
LD A. (mnl
3
4
12
LD A.R
2
2
6
LD (BCI.A
1
3
7
LDD
2
4
12
LD (DEI.A
1
3
7
LD ww.mn
3
3
9
LD ww.lmnl
4
6
18
LDDR
2
6
14 (If BCR*O)
2
4
1 2 (If BCR= 0)
LD (HU.m
2
3
9
LD HL.lmn)
3
5
15
LO (HU.g
1
3
7
LDI
2
4
12
LD I.A
2
2
6
LDIR
2
6
14
2
4
1 2 (If BCR= 0)
LD lX,mn
4
4
12
LO IX.(mn)
4
6
18
LD (lX+d).m
4
5
15
LD OX+d).g
3
7
15
LO IY.mn
4
4
12
LO 1Y.lmnl
4
6
18
LD (lY+d).m
4
5
15
LD OY+dl.g
3
7
15
MNEMONICS
Of BCR*O)
(to be continued)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
529
HD64180R/Z
MNEMONICS
Bytes
Machine Cycles
States
LD (mn),A
3
5
13
LD (mn),ww
4
7
19
LD (mn),HL
3
6
16
LD (mn),1X
4
7
19
LD (mn),IY
4
7
19
LD R,A
2
2
6
LD g,(HU
1
2
6
LD g,(lX+d)
3
6
14
LD g,(lY+d)
3
6
14
LD g,m
2
2
6
LD g,g'
1
2
4
LD SP,HL
1
2
4
LD SP,IX
2
3
7
LD SP,IY
2
3
7
MLTww
2
13
17
NEG
2
2
6
NOP
1
1
3
OR (HU
1
2
6
OR (lX+d)
3
6
14
OR (lY+d)
3
6
14
ORm
2
2
6
ORg
1
2
4
OTOM
2
6
14
OTOMR
2
8
16 (If Br:;!:O)
2
6
14 (If Br=O)
2
6
14 (If Br:;!: 0)
2
4
12 (If Br=O)
OTOR
(to be continued I
~HITACHI
530
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
Bytes
Machine Cycles
OTIM
2
6
14
OTIMR
2
8
16 Of B,,*O)
2
6
14
Of Br=O)
2
6
14
Of Br=FO)
MNEMONICS
OTIR
States
2
4
12 (If Br=O)
OUTO
2
4
12
OUTI
2
4
12
OUT (m).A
2
4
10
OUT (C).g
2
4
10
OUTO (m).g
3
5
13
POP IX
2
4
12
POP IV
2
4
12
POP zz
1
3
9
PUSH IX
2
6
14
PUSH IV
2
6
14
PUSH zz
1
5
11
RES b.1HU
2
5
13
RES b.OX+d)
4
7
19
RES b.lIY+d)
4
7
19
RES b.g
2
3
7
RET
1
3
9
RET f
1
3
5
Of condition is false)
1
4
10
Of condition is true)
RETI
2
4
12
RETN
2
4
12
(to be continued)
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589·8300
531
HD64180R/Z
Bytes
Machine Cvcles
States
RLA
1
1
3
RLCA
1
1
3
RLC (HU
2
5
13
RLC (lX+d)
4
7
19
RLC (IY+d)
4
7
19
RLC 9
2
3
7
RLD
2
8
16
RL (HU
2
5
13
RL (lX+d)
4
7
19
RL (lY+d)
4
7
19
RL 9
2
3
7
RRA
1
1
3
RRCA
1
1
3
RRC(HU
2
5
13
RRC (IX+d)
4
7
19
RRC (IY+d)
4
7
19
RRC 9
2
3
7
RRD
2
8
16
RR(HU
2
5
13
RR (lX+d)
4
7
19
RR (IY+d)
4
7
19
RR 9
2
3
7
RST v
1
5
11
SBC A.(HU
1
2
6
SBC A.OX+d)
3
6
14
SBC A.(lY+d)
3
6
14
SBC A.m
2
2
6
MNEMONICS
(to be continued}
•
532
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
Bytes
Machine Cycles
States
SBC A,g
1
2
4
SBC HL,ww
2
6
10
SCF
1
1
3
SET b.(HU
2
5
13
SET b.OX+d)
4
7
19
SET b.(IY+ d)
4
7
19
SET b.g
2
3
7
SLA (HU
2
5
13
SLA OX+dl
4
7
19
SLA OY+d)
4
7
19
SLA 9
2
3
7
SLP
2
2
8
SRA(HU
2
5
13
SRA QX+d)
4
7
19
SRA OY+d)
4
7
19
SRAg
2
3
7
SRL (HU
2
5
13
SRL (lX+d)
4
7
19
SRL (lY+d)
4
7
19
SRLg
2
3
7
SUB (HU
1
2
6
SUB (IX+d)
3
6
14
SUB (lY+d)
3
6
14
SUBm
2
2
6
SUBg
1
2
4
TSTIO m
3
4
12
TST 9
2
3
7
MNEMONICS
Ito be continued)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
533
HD64180R/Z
Bytes
Machine Cycles
States
TSTm
3
3
9
TST (HU
2
4
10
XOR(HU
1
2
6
XOR (IX+d)
3
6
14
XOR (IY+d)
3
6
14
XORm
2
2
6
XOR 9
1
2
4
MNEMONICS
.HITACHI
534
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.
10
Brisbane, CA 94005-1819 • (415) 589-8300
21 OP-CODE MAP
ode map
Ion format : XX
Table 18 1
:J:
~>
~
:::!.
B
C
D
n
!"
a
•
~
2:
""C
[
•
§
w..
~ l:
CY_.
~
a".
10J:
·-
':<
m
,
A
E
H
L
.(HL)
A
1011
1100
1101
1110
1111
B
C
D
E
F
0
rn
~
~
•
~
~
i
UI
W
UI
1
2
0
•
CD
~
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
E
H
:J L
;l (HL)
A
~ B
Di"
<0
LO
~
0000 0
3
4
!I
6
7
8
9
_(LO-ALL)
LO""0-7
BC
HL
AF
DE
BOIDEIHLISPI
zzl
(LO=0-7
NZ
NC
P
PO
f I
H (HL)
B
B
0
o I H (HL)
OOH lOH 20H 30H
v I
0000 0001 0010 0011 0100 010110110 0111 1000 1001 1010 1011 1100 1101 1110 1111
7
1
4
A
B
C
0
F
0
2
3
8
9
E
5 I 6
,
RET f
NOP MZi .II HZ.- .II NO.i
0
popzz
LD _,1M
: NOTE II
1
,
LO (_), A LD(Im) LD(Im)
,,
JP f,mII
2
,HI..
,A
3
JP rm aJT~ I EX(Sl) ! 01
,,,
INC_
,A ,HI..
LO g.s
/100 ASUB s AND s OR s
,
,,
,NOTEII
,8
OALL f,mII
4
INC II
DEO ,
,NOTEll
PUSH zz
!I
NOTE21 NOTE21 NOTE21 NOTE21 AIXlA,_ISlS mlANl ml OR m 6
LD g. m
, NOTElI
RST v
7
RLOAI RLA I OAA I SOF
RET f
8
EXAF,AF'I JR i IJR Z. i IJR OJ
RET EXX iii (ILl LD sP, 9
ADD HL._
LO A. (_) LD HI.. LD A.
HI..
(1m) (rm)
JP f,rm
A
DEC_
LO g.s
ADO A S80A XOR s CPs T_21"A,(Iw)IEXIE,IlI EI
B
,8
,8
OALL f,mII
C
INC II
CALl. ml NOTE311 Table31 NOTE31 0
DEC II
------- ---NOTE21
NOTE21 NOTE21 NOTE21 NOTE21 AIlCA,_ISllCA,IIIDI mlCP m E
LO "m
F
RROAIRRA CPL I CCF
RST v
A
B
9
8
o I 1
2 I 3
4 I 5 I 6 I 7
C I 0 I ElF
L j A
f j
C I E
ZICIPEIM
OIEILjA
II(LO-8-F)
OSH I 18H I 28H I 38H
v I
LO=8-F
=====~~T~2~===~
-------------------------------
---
-
NOTE11 CHU repll_ g.
21 CHU replle.. s.
31 If DDH i. supplementeda. lit op-eocla for the instructions which have HL or (HU as an operend in Table 18. the,n.tructions are executed
replacing HL with IX _ CHU with OX+dl.
ex.
22H: LD Imnl. HL
DDH 22H: LD Imnl.IX
If FDH is ._lemented .. lit op-cocle for the instructions which have HL or CHU as an operand in Table 18. tha instructions are executed
replacing HL with IV and (tIU with lIY+dl.
ax.
34H: INC CHU
FDH 34H: INC lIY + dl
How_. JP CHU and EX DE. HL are e.captlon Ind note the foHowings.
If DDH i••_IemantecI .. 1st op-eocla for JP CHU. OX! replaces CHLl I I _ _ _ JP OXI i. axecuted.
If FDH is supplemented .. 1.t op-oocle for JP CHLl. (00 repla_ CHU I I operend and JP OYl ilexecuted.
Even If DOH or FDH i. supplemented .. lit op-code for EX DE. HL. HL is nOt repIeced and the instruction is reglrded I I illegal instruction.
-
- -- - -
-
--
-
---
:r:
tJ
0'>
~
......
CO
~
N
01
W
0>
::t
t1
0")
~
~
.......
'"
(X)
(")
=-
):>
3
C1>
"'.
o
Table 19 2nd op-code map
Instruction format: CB XX
(")
r-
et
•
::I:
;::;:
'"
(")
="~
•
'"
g
W~
~ :t
" ~~
~O
.;§ J:
•
c:I
"'.
~
~
C1>
§;
*
o
'f'
cD
<0
•
~
.2!
~
'f'
co
w
o
o
~
b (LO-O-7)
1"
B
C
LO
~
0000 0
0001
0 0010
E 0011
H 0100
:J L 0101
--l
<{ (HL) 0110
II
A 0111
~ B 1000
C 1001
0 1010
bO
E 1011
H 1100
L 1101
(HL) 1110
A 1111
4
6
0
2
4
6
0
2
0
2
4
6
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
4
5
A
F
1
2
3
6
7
8
9
B
C
0
0
E
0
r--,
1
r--y-
2
3
4
5
6
7
r--a
~
r--r
---------------- ---------------- ---------------- r--a
---------------- ---------------- ---------------- I----]
RLC g RL g SlA g
--- ---- ---NOTE1) NOTE1)
--- ---- ----
NOTEll
BIT b,g
RES b,g
SET b,g
NOTEl)
NOTEl)
NOTEl)
8
8
9
A
B
C
0
E
F
rg~
r-s
BIT b,g
RES b,g
SET b,g
r--c
RRC g RR g SRA g SRLg
r--o
--- ---- ---- ---- ---------------- ---------------- --------------- r-yNOTE 11
NOTEn
NOTEl)
NOTEll
NOTE1)
NOTE 1)
NOTEll
0
1
2
3
---------------- ---------------- ---------------- r--y4
1
5
3
6
5
7
7
8
1
9
3
A
5
B
C
7
1
0
3
b (LO=8-F)
NOTE1) If DOH is supplemented as 1 5t op-code for the instructions which have (HL) as operand in Table 19, the instructions are executed replacing
(HL) with (lX+d).
If FDH is supplemented as 1st op-code for the instructions which have (Hl) as operand In Table 19, the Instructions are executed replacing (HL)
wIth (IY+d).
E
F
5
7
i¥
~
:!:
»
Table 20 2nd op-code map
Instruction format : ~
3
'"fi"
.?'
a
•
LO
~
~
~
:!:
"'0
~
•
""go
~~
iil
"'0
:I
_
Si. ~
;;l. )Ii
~o
~ :I
•
•
~
~
~ex>
w
g
01
tv
-...J
0000 0
0001
1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 A
1011 8
11"00 C
1101 -0
1110 E
1111 F
ww (LO-ALL)
DE
HL
SP
8C
g (LO-O-7)
H
8
0
H
8
0
0000 0001 0010 0011 0100 0101 0110 0111 100011001
4
6
0
1
2
3
5
7
819
IN g. (C)
INO g. (m)
OUT (C).g
OUTO (m).g
S8C HL,ww
LO (mn).ww
onMloT~
TST(H..) NEG
TST m TSTKlm
TST g
RETN
fS[Pl
1M 0 1M 1
LD ~A LDA,I RRO
INO g. (m)
IN g. (C)
OUT (C).g
OUTO (m).g
AOC HL.ww
LD ww. (rm)
OTOMIOTI:J.fl
TST g
MLT WW
RET!
1010
A
LOI
CPI
INI
OUTI
1011 1100111011111011111
8
C 1 DIE 1 F
LOIR
CPIR
INIR
OTIR
-----s----=r
S-
LDO LDDR
CPO CPDR
INO INOR
~
--A
----ee-
OUTD OTOR
-0
---r--F
LDR,A LDA,R RLO
1
E
- - - - _.. _-
2
3
4
5
6
7
L
A
C
E
L
A
819
-r
-----a~
~
1M 2
0
C
0
---r-
A
8
I C I DIE I F
__....L(b.Q=!- F)
::r:
tJ
en
~
CXl
o'"""
~
N
HD64180R/Z
22 BUS AND CONTROL SIGNAL CONDITION IN EACH MACHINE CYCLE
• IADDRESSI : invald
Z tDATAI
InstIUctian
ADDHl._
Machine
Me.
ADD A.m
ADCA.m
SUBm
sac A.m
ANDm
ORm
XORm
CPm
ADD A. tHU
AOC A. (HI.)
SUB tHU
sac A.IHU
ANa IHU
OR (HI.)
XOR tHU
CPtHU
ADD A. fD<+cO
ADD A. OY+CO
AOC A. fD<+ ell
ADC A. lY+dI
SUB fD<+cO
SUB lY+cO
sac A.1X+dI
1
0
1
0
1
0
z
1
1
1
1
1
1
1
181 ap-code
181
T,T.T.
Address
ap-code
0
1
0
1
0
1
0
2nd
T,T.T.
2nd ap-code
Address
0
1
0
1
0
1
1
·
ap-code
Z
1
1
1
1
1
1
1
181 ap-code
lot
T,T.T.
Address
ap-code
0
1
0
1
0
1
0
2nd
T,T.T.
2nd ap-code
Address
op-c:ode
0
1
0
1
0
1
1
z
1
1
1
1
1
1
1
1st ap-code
181
Address
ap-code
0
1
0
1
0
1
0
z
1
1
1
1
1
1
1
·
T,T.T.
MC.
n
MC,
T,T.T.
181 ap-code
Add....
ap-code
0
1
0
1
0
1
0
Me.
T,T.T.
181 operand
Add....
m
0
1
0
1
1
1
1
181 op-code
1st
Me,
T,T.T.
Address
ap-code
0
1
0
1
0
1
0
MC.
T,T.T.
HI.
DATA
0
1
0
1
1
1
1
1st ap-code
Me,
T,T.T.
Address
181
op-code
0
1
0
1
0
1
0
MC.
T,T.T.
2nd ap-code
Address
0
1
0
1
0
1
1
·
$
538
ST
Me,
ORa
XORII
CPII
Uii iiALi'
0
MC.
-MC. TiTiTm
ADDA.g
ADC A.g
SUB II
sac A.g
AND II
iOE
ap-code
TiTiTm
MC,
WR Me
Address
T,T.T.
Me.
-Me. TiTiTiTi
ADCHL._
sacHl._
iiD
181
Me.
-Me.
Me.
DATA
ADDRESS
1st ap-code
MC,
Me,
ADD DC.>uc
ADD W.yy
S_
Cycle
: high Impadanca.
1st
2nd
ap-code
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
instructIOn
SBC A. (lV+d)
AND (lX+d)
AND (lV+d)
OR (lX+d)
OR (lV+d)
XOR (lX+d)
XOR (lV+d)
CP (lX+d)
CP (lV+d)
Machine
Cycle
States
MC3
T,12T3'
MC.
-MC,
MC,
MC,
BIT b.g
MC,
MC,
DATA
ADDRESS
1st operand
Address
d
Z
TITI
WR
ME
IOE
UR
HALT
ST
0
1
0
1
1
1
1
1
1
1
1
1
1
1
T,12T3
lX+d
IV+d
DATA
0
1
0
1
1
1
1
T1T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
2nd op-code
0
1
0
1
0
1
1
0
1
0
1
0
1
0
T,T2T3
Address
2nd
op-code
T,T2T3
1st op-code
Address
1st
op-code
2nd op-code
2nd
BIT b. (Hl)
MC,
T,T2T3
Address
op-code
0
1
0
1
0
1
1
MC3
T,T2T3
Hl
DATA
0
1
0
1
1
1
1
T1T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
2nd op-code
2nd
op-code
0
1
0
1
0
1
1
MC,
T,T2T3
Address
T,T2T3
1st operand
Address
d
0
1
0
1
1
1
1
1,12T3
3rd op-code
Address
3rd
op-code
0
1
0
1
0
1
1
T1T2T3
IX+d
IV+d
DATA
0
1
0
1
1
1
1
T1T2T3
1st op-cocle
Address
op-code
0
1
0
1
0
1
0
T,T2T3
1st operand
Address
n
0
1
0
1
1
1
1
MC3
T1T2T3
2nd operand
Address
m
0
1
0
1
1
1
1
MC,
T.
1
1
1
1
1
1
1
MC,
T1T2T3
SP-l
PCH
1
0
0
1
1
1
1
MC,
Tl12T3
SP-2
PCl
1
0
0
1
1
1
1
1st
T1T2T3
1st op-code
Address
op-code
0
1
0
1
0
1
0
T,T2T3
1st operand
Address
n
0
1
0
1
1
1
1
MC,
BIT b. (lX+d)
BIT b. (IV + d)
RD
Mea
MC.
MC,
MC,
MC,
1st
CAll mn
CAllI.mn
(If conditIOn
.s false)
MC,
MC,
Z
(to be continued)
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
539
HD64180R/Z
....truction
Machine
Cycle
MC,
MC,
States
DATA
ADDRESS
RD
WR
ME
iCe
-UR
HALT
ST
T,T2T3
1st op-code
Add.....
1st
op-code
0
1
0
1
0
1
0
T,T2T3
1st operand
Add.....
n
0
1
0
1
1
1
1
2nd operand
Add.....
m
0
1
0
1
1
1
1
1
1
1
1
1
1
1
CALLf.mn
MC,
T,T2T3
Of condition
is truel
MC.
T,
MC,
T,T213
SP-1
PCH
1
0
0
1
1
1
1
MC.
T,1213
SP-2
PCl
1
0
0
1
1
1
1
T,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC,
T,T2T3
Hl
DATA
0
1
0
1
1
1
1
Z
1
1
1
1
1
1
1
T,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,12T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC,
T,12T3
Hl
DATA
0
1
0
1
1
1
1
Z
1
1
1
1
1
1
1
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
2ndop-c~
0
1
0
1
0
1
1
0
1
0
1
1
1
1
CCF
MC,
MC,
CPI
CPO
MC.
-MC.
MC,
CPIR
CPOR
Of BC.*O end
Ar*(HU")
MC.
-MC,
MC,
CPR
CPDR
Of BC.=O or
Ar=(HU,.)
TiTiTi
TiTiTiTiTi
T,12T3
MC,
T,12T3
Address
2nd
op-code
MC,
T,12T3
Hl
DATA
MC.
-MC.
CPl
Z
.
Z
1
1
1
1
1
1
1
T,12T3
1st op-code
Add .....
1st
op-code
0
1
0
1
0
1
0
MC,
T,12T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,
Z
1
1
1
1
1
1
1
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
TiTiTi
OM
01
MC,
TIT2T3
Ito be COOIInued)
~HITACHI
540
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
Instruction
DJNZ)
(ffBr*O)
Machine
Cycle
States
MC,
T,T2T3
MC,
T,·1
MC,
MC.
-MC,
T,T2T3
1st op-code
Address
1st operand
Address
MC,
T,T2T3
MC,
T,·1
MC,
EI
EX DE. HL
EXX
WR
ME
JOE
lIR
HALT
ST
1st
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
0
1
0
1
1
1
1
)-2
1
1
1
1
1
1
1
1st
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
Z
TITI
1st op-code
DJNZ)
(ff Br=O)
AD
DATA
ADDRESS
T1T2T3
Address
1st operand
Address
)-2
0
1
0
1
1
1
1
T,T2T3
Address
1st
op-code
0
1
0
1
0
1
0
T1T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T1T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
TI
Z
1
1
1
1
1
1
1
1st
op-code
0
1
0
1
0
1
0
1st
MC,
MC,
op~code
EX AF. AF'
MC,
T,T2T3
1st op-code
Address
MC,
T,T2T3
SP
DATA
0
1
0
1
1
1
1
MC,
T,T2T3
SP+1
DATA
0
1
0
1
1
1
1
MC.
Ti
1
1
1
1
1
1
1
MC,
T,T2T3
SP+1
H
1
0
0
1
1
1
1
MC.
T,T2T3
SP
L
1
0
0
1
1
1
1
MC,
T,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC,
T1T2T3
SP
DATA
0
1
0
1
1
1
1
MC.
T,T2T3
SP+1
DATA
0
1
0
1
1
1
1
MC.
TI
1
1
1
1
1
1
1
EX (SP). HL
EX (SP),IX
EX (SPUY
Z
Z
·1 DMA. REFRESH. or BUS RELEASE cannot be executed after thIS state (Request is Ignored)
(to be continued)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
541
HD64180R/Z
Inslruction
EX (SP),IX
EX (SP),IY
Machine
Cycle
MC.
MC,
MC.
HALT
IMO
1M1
M2
INC (HU
DEC (HU
INC (lX+d)
INC OY+dl
OEC (IX+d)
DEC (lY+d)
ADDRESS
ME
iCE
lJlf
HALT'
ST
1
0
0
1
1
1
1
T,T2T3
SP
1
0
0
1
1
1
1
T1T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
Next op-code
Address
Next
0
1
0
1
0
0
0
0
1
0
1
0
1
0
0
1
0
1
0
1
1
op-code
0
1
0
1
0
1
0
---
T,T,13
MC.
T lT213
1st op-code
Address
MC,
To
MC.
T,T2T3
1st op-code
Address
MC,
T1T2T3
HL
MC,
Ti
MC.
T,T2T3
op-code
1st
op-code
2nd
op-code
1st
Z
1
1
1
1
1
1
1
op-code
0
1
0
1
0
1
0
DATA
0
1
0
1
1
1
1
1
1
1
1
i
1
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1st
Z
HL
DATA
1st
MC. . T,12T3
1st op-code
Address
MC,
T,T2T3
2nd op-code
Address
op-code
0
1
0
1
0
1
1
T,T2T3
1st operand
Address
d
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
DATA
1
0
0
1
1
1
1
Address
1st
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
T ,T213
1st op-code
Address
1st
op-dode
0
1
0
1
0
1
0
2nd
MC,
T,T2T3
2nd op-code
Address
op-code
0
1
0
1
0
1
1
MC,
Ti
Z
1
1
1
1
1
1
1
MC,
MC.
-MC.
MC.
T ,T213
MC,
n
T ,T213
MC.
T1T2T3
MC,
Ti
MC.
op-code
2nd
Z
TiTi
lX+d
lY+d
DATA
Z
lX+d
lY+d
1st op-code
INC IX
INC IY
DEC IX
DEC IY
WR
IXL
IYL
2nd op-code
Address
MC.
INCww
DECww
1iD
IXH
IYH
T,T2T3
MC.
DATA
SP+l
T,T2T3
1st op-code
Address
MC,
INCg
DEC g
States
(to be continued)
~HITACHI
542
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 569.6300
HD64180RlZ
Instrucl10n
Machine
Cycle
MC,
IN A.1m)
MC,
States
ADDRESS
DATA
RD
WR
ME
IOE
UR
HALT
ST
T,T,T,
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
1,1213
1st operand
Address
m
0
1
0
1
1
1
1
mtoAo-A1
T,12T3
A to A8-A'5
DATA
0
1
1
0
1
1
1
1,1213
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
2nd
MC,
1,1213
2nd op-code
Address
op-code
0
1
0
1
0
1
1
MC,
T,1213
BC
DATA
0
1
1
0
1
1
1
1st
T,12T3
1st op-code
Address
op-code
0
1
0
1
0
1
0
T,T,T,
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
1,12T3
1st operand
Address
m
0
1
0
1
1
1
1
1,1213
mtoAo-A,
OOH to A.-A"
DATA
0
1
1
0
1
1
1
1,T213
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
2nd
MC,
1,T2T3
2nd op-code
Address
op-code
0
1
0
1
0
1
1
MC,
T,T,T,
Be
DATA
0
1
1
0
1
1
1
MC.
1,12T3
HL
DATA
1
0
0
1
1
1
1
T,T2T3
1st op-code
Add....s
1st
op-code
0
1
0
1
0
1
0
2nd
MC,
T,T,T,
2nd op-code
Address
op-code
0
1
0
1
0
1
1
MC,
T,T,T,
Be
DATA
0
1
1
0
1
1
1
MC.
1,T213
HL
DATA
1
0
0
1
1
1
1
Z
1
1
1
1
1
1
1
op-code
0
1
0
1
0
1
0
MC,
MC,
INg.IC)
MC,
INOg.lm)
MC,
MC,
MC.
MC,
IN!
IND
MC,
INIR
INDR
IIf B,*O)
MC.
-MC.
1,T2T3
1st op-code
Address
MC,
1,T213
2nd op-code
Address
op-code
0
1
0
1
0
1
1
MC,
1,1213
BC
DATA
D
1
1
0
1
1
1
MC.
T,T,T,
HL
DATA
1
0
0
1
1
1
1
MC,
INIR
INDR
1IfBr=0)
.
ToTi
1st
2nd
_HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
543
HD64180R/Z
Machine
Instruction
Me,
JP mn
MC,
MC,
JP I,mn
(W I is lalsel
MC,
MC,
MC,
JP I,mn
(W I is true)
MC,
MC,
JP(HU
JP (lXI
JP UYI
MC,
MC,
MC,
MC,
JRj
MC,
MC,
-MC.
JR C,j JR NCj
JR Z,j JR NZ,j
states
Cycle
MC,
Me,
JR C,j JR NCj
JR Zj JR NZj
MC,
Of condition
MC,
IS
true)
DATA
-RD -WR
-ME
-JOE -UR -HALT
ST
T,12T3
1st op-<:ode
Address
1st
op-code
0
1
0
1
0
1
0
T ,T213
1st operand
Address
n
0
1
0
1
1
1
1
T,T213
2nd operand
Address
m
0
1
0
1
1
1
1
T,12T3
1st op-code
Address
lst
op-code
0
1
0
1
0
1
0
T1T2T3
1st operand
Address
n
0
1
0
1
1
1
1
T,1213
lsi op-code
Address
lsi
op-code
0
1
0
1
0
1
0
T,T2T3
1st operand
Address
n
0
1
0
1
1
1
1
11T2T3
2nd operand
Address
m
0
1
0
1
1
1
1
1,T213
lsi op-code
Add....s
1st
op-code
0
1
0
1
0
1
0
Tl12T3
lsi op-code
Add....s
1st
op-code
0
1
0
1
0
1
0
1,T213
2nd op-code
Addrass
2nd
op-code
0
1
0
1
0
1
1
T,T2T3
1st op-code
Address
lsi
op-code
0
1
0
1
0
1
0
T,T 2 T3
lsi operand
Addrass
)-2
0
1
0
1
1
1
1
Z
1
1
1
1
1
1
1
T,T2T3
lsi op-code
Addrass
1st
op-code
0
1
0
1
0
1
0
T,12T3
lsi operand
Address
j-2
0
1
0
1
1
1
1
T1T213
1st op-codj!
Addrass
1st
op-code
0
1
0
1
0
1
0
1112T3
lsi operand
Address
J-2
0
1
0
1
1
1
1
Z
1
1
1
1
1
1
1
lSl0p-code
Addrass
1st
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
T,T213
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T,
lSI operand
Address
m
0
1
0
1
1
1
1
nn
Of condition
is falsel
ADDRESS
MC,
-Me.
TiTi
MC,
T,T2T3
MC,
Ti
LD g,g'
MC,
LD g,m
Me,
Ito be contJnuedl
~HITACHI
544
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
Instructoon
Mach,ne
Cycle
Slates
iii5
WR
ME
m-
1lR
HALT
ST
1st
op-code
0
1
0
1
0
1
0
DATA
ADDRESS
Me,
T,T2T3
1st op-code
Address
MC,
T,12T3
HL
DATA
0
1
0
1
1
1
1
T,12T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
1,T213
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
1,1213
1st operand
Address
d
0
1
0
1
1
1
1
1
1
1
1
1
1
1
LD g. IHL)
MC,
MC,
LD g. (lX+d)
LD g. (lY+d)
MC,
MC.
-MC.
111213
DATA
0
1
0
1
1
1
1
MC,
T112T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,
Z
1
1
1
1
1
1
1
MC,
1,1213
HL
9
1
0
0
1
1
1
1
1,1213
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,12T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
1,T213
1st operand
Address
d
0
1
0
1
1
1
1
1
1
1
1
1
1
1
MC,
MC,
LD IIX+d).g
LD (lY+d).g
MC,
MC.
-MC.
Z
9
1
0
0
1
1
1
1
1,12T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,12T3
1st operand
Address
m
0
1
0
1
1
1
1
MC.
1,1213
HL
DATA
1
0
0
1
1
1
1
1st op-code
1st
T,12T3
Address
op-code
0
1
0
1
0
1
0
1,1213
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T,T2T3
1st openond
Address
d
0
1
0
1
1
1
1
1,1213
2nd operand
Address
m
0
1
0
1
1
1
1
T,12T3
lX+d
lY+d
DATA
1
0
0
1
1
1
1
T1T2T3
1st op-code
Address
0
1
0
1
0
1
0
MC,
MC,
MC.
MC.
MC.
LD A. (BC)
LD A. (DEI
T,T,T,
1,12T3
MC,
LD (lX+dl.m
LD (lY+dl.m
.
IX+d
lY+d
MC,
LD IHU.m
Z
lX+d
IY+d
MC.
LD IHU.g
T,T,
MC,
1st
op-code
!to be contonuedl
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
545
HD64180R/Z
Instruction
Machine
Cycle
States
Rli
Wii
ME
mE
lJIi
"RAi:T
ST
DATA
0
1
0
1
1
1
1
1st
op-code
0
1
0
1
0
1
0
T1T2T3
1st operand
Address
n
0
1
0
1
1
1
1
Me,
TIT2T3
2nd operand
Address
m
0
1
0
1
1
1
1
Me.
T1T2T3
mn
DATA
0
1
0
1
1
1
1
MC,
T1T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
TI
Z
1
1
1
1
1
1
1
LD A. (BC)
lD A. IDE)
MC,
MC,
MC,
lD A.lmn)
LD (BC).A
LD IDE).A
A
1
0
0
1
1
1
1
T1T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T1T213
1st operand
Address
n
0
1
0
1
1
1
1
MC,
T1T2T3
2nd operand
Address
m
0
1
0
1
1
1
1
MC.
TI
1
1
1
1
1
1
1
MC,
TIT2T3
mn
A
1
0
0
1
1
1
1
Tl12T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
TI12T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T2T3
1st operand
Address
n
0
1
0
1
1
1
1
Tl12T3
2nd operand
Address
m
0
1
0
1
1
1
1
T1T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
Tl12T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
Tl12T3
1st operand
Address
n
0
1
0
1
1
1
1
T1T2T3
2nd operand
Address
m
0
1
0
1
1
1
1
Tl12T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T2T3
1st operand
Address
n
0
1
0
1
1
MC,
A.I
A.R
I.A
R.A
MC,
MC,
MC,
lD ww, mn
MC,
MC,
MC,
lD IX.mn
LD lY.mn
T1T2T3
1st op-code
Address
T,T2T3
MC,
LD
lD
LD
lD
Tl12T3
DATA
Be
DE
MC,
LD Imn).A
ADDRESS
BC
DE
MC,
MC,
MC.
MC,
LD Hl. (mn)
MC,
Z
1
1
(to be
conbnuedl
~HITACHI
546
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
Machine
Instruction
LD Hl., (mn)
DATA
lII5
WI!
W
N
llf
RID"
ST
T1T213
2nd operand
Address
m
0
1
0
1
1
1
1
MC.
T1T213
mn
DATA
0
1
0
1
1
1
1
MC,
T,T2T3
mn+l
DATA
0
1
0
1
1
1
1
T,T213
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T1T2T3
1st operand
Address
n
0
1
0
1
1
1
1
MC.
T lT2T3
2nd operand
Address
m
0
1
0
1
1
1
1
MC,
T lT2T3
mn
DATA
0
1
0
1
1
1
1
MC.
T,T213
mn+l
DATA
0
1
0
1
1
1
1
T,T2T3
1st op-code
Address
l.t
op-code
0
1
0
1
0
1
0
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T,T213
1st operand
Address
n
0
1
0
1
1
1
1
MC.
T,T213
2nd operand
Address
m
0
1
0
1
1
1
1
MC,
T1T2T3
mn
DATA
0
1
0
1
1
1
1
MC.
T,T2T3
mn+l
DATA
0
1
0
1
1
1
1
T,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T2T3
1st operand
Address
n
0
1
0
1
1
1
1
MC,
11T2T3
2nd operand
Address
m
0
1
0
1
1
1
1
MC.
Ti
1
1
1
1
1
1
1
Me.
T,T2T3
mn
L
1
0
0
1
1
1
1
MC,
T lT2T3
mn+l
H
1
0
0
1
1
1
1
MC,
MC,
LDww.(mn)
MC,
MC,
MC,
MC,
MC,
LD (mn).HL
ADDRESS
MC,
MC,
LD IX.lmn)
LD IY.(mn)
States
Cycle
Z
$
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
547
HD64180R/Z
Machine
Instruction
States
Cycle
Me, T,T2T3
Me, T,T2T3
ADDRESS
DATA
Ri5
WR
ME
iOE
IiR
HALT
ST
0
1
0
1
0
1
0
1st
1st op-code
Address
op-code
2nd op-code
2nd
Address
op-code
0
1
0
1
0
1
1
n
0
1
0
1
1
1
1
m
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1st operand
Me, T,T2Ta
lD (mnl.ww
Address
2nd operand
Me.
TtT2T3
Me,
To
Me.
T1T2T3
Me, T,T2T3
Me,
T1T2T3
Address
Z
mn
wwl
1
0
0
1
1
1
1-
mn+l
wwH
1
0
0
1
1
1
1
1st op-code
1st
op-code
0
1
0
1
0
1
0
0
1
0
1
0
1
1
Address
2nd op-code
Me,
Me,
LD (mnl.1X
LD (mn).lY
T,T2T3
Address
2nd
op-oode
T,T2T3
1st operand
Address
n
0
1
0
1
1
1
1
m
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
1
1
1
2nd operand
Me.
T1T2T3
Me,
To
Address
Z
IXL
Me.
T,T2T3
mn
IYl
IXH
Me,
T,T2T3
mn+l
IYH
1st op-code
1st
Address
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
1st op-oode
1st
T,T2T3
Address
op-code
0
1
0
1
0
1
0
Me,
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
Me,
To
1
1
1
1
1
1
1
1st op-code
1st
Address
op-code
0
1
0
1
0
1
0
2nd op-code
0
1
0
1
0
1
1
1
1
1
1
Me, T,T2T3
LD SP. HL
Me,
Me,
lD SP.IX
LD SP.IY
To
Me, T,T2T3
lDI
Z
Me,
T1T2T3
Address
2nd
op-code
Me,
T,T2T3
HL
DATA
0
1
0
1
1
Me. T,T2T3
DE
DATA
1
0
0
1
1
LDD
Ito be contlnued)
~HITACHI
548
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180RlZ
Instruction
MIIc:hine
Cycle
S_
0
1
0
mE'
1J(
'R'MT
ST
,
0
,
1
2nd op-<>Ode
2nd
Address
op-<>Ode
0
T,T2T3
HL
DATA
0
,
,
Me. T,12T3
DE
DATA
1
0
0
Z
1
1
1
1
1
1
1
op-<>Ode
0
1
0
1
0
1
0
Address
2nd
op-<>Ode
0
1
0
1
0
1
1
Me. T,T,T.
HL
DATA
0
1
0
1
1
1
T,12T3
DE
DATA
1
0
0
1
1
1
1st
T,T,T.
1st op-<>Ode
Address
op-<>Ode
0
1
0
1
0
2nd
op-<>Ode
0
1
0
1
0
,
,
z
1
1
1
1
1
1
,
1st op-<>Ode
Address
1st
op-code
0
1
0
1
0
1
0
2nd op-code
2nd
op-<>Ode
0
1
0
1
0
0
1
0
1
0
Me.
Me,
T,T.T.
1&t op-<>Ode
Address
2nd op-<>Ode
Me,
Me.
Me,
T,T2T3
2nd op-<>Ode
Me, T,TfT3
1&t
.
-Me. TiTi
Address
Me,
NEG
T,T2T3
0
0
0
0
1
, ,
, ,
1st
TiTiTiTI
Me. TiTiTiT,
-Me13 TiTiT.
,
,
0
1
T1T2T3
Address
T112T3
1&t op-<>Ode
Address
T,12T3
1st op-<>Ode
Address
op-<>Ode
0
1
0
1
0
,
,
,
Me, T,T2T3
1st operand
Address
m
0
1
0
1
1
1
1
,
1
1
1
1
1
1
1
0
1
0
1
1
1
Me,
NOP
Dr
,
,
, ,
,
Me.
MLTww
WR
op-<>Ode
T,T213
Me. T,T.T.
LOll
LODR
01 ac.==O)
111)
1st op-<>Ode
Address
Me,
LOll
LDDR
01 ac.*O)
DATA
ADDRESS
Me,
Me,
OUT (m),A
MC.
T,
Me. T,T,T.
1st
op-<>Ode
1st
.
mto Ao-A7
AtoA.-A ..
•
Z
A
1
0
0
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
549
HD64180R/Z
Instruction
Machine
ADDRESS
Slates
Cvcle
DATA
AD
WR
ME
IOE
ilR
HALT
ST
1st
T,T2T3
1st op-code
Address
op~code
0
1
0
1
0
1
0
MC,
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC,
T,
Z
1
1
1
1
1
1
1
MC.
T,T2T3
BC
g
1
0
1
0
1
1
1
T,T2TJ
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC,
T,T2TJ
1st operand
Address
m
0
1
0
1
1
1
1
MC.
T,
1
1
1
1
1
1
1
MC,
OUT (CI.g
MC,
MC,
OUTO (ml.g
T,T2T3
9
1
0
1
0
1
1
1
T,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC,
T,
Z
1
1
1
1
1
1
1
MC.
T,T2T3
DATA
0
1
0
1
1
1
1
OOH to A,,,-A,S
DATA
1
0
1
0
1
1
1
Z
1
1
1
1
1
1
1
T,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
Me,
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
Me,
Ti
z
1
1
1
1
1
1
1
MC.
T,T2T3
HL
DATA
0
1
0
1
1
1
1
T,T2T3
C to Ao-A7
OOH to Ad-Ats
DATA
1
0
1
0
1
1
1
1
1
1
1
1
1
1
MC,
MC,
OTIM
OTOM
Z
m to Ao--Ar
DOH to Ad-A!s
HL
C to Ao
MC,
T,T2T3
MC.
Ti
Me,
OTIMR
OTOMR
(JIBr*OI
MC,
A7
Me.
-MC"
TiTlT,
Z
(to be contmuedl
~HITACHI
550
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
Instruction
Machine
T,T2T3
MC,
T,T2T3
2nd op-code
Address
MC,
T,
MC.
T,T2T3
HL
MC,
T,T2T3
C to Ao A1
OOH to A'ii-A'5
MC.
TI
j()f
1st
op-codo
0
1
0
1
0
1
0
2nd
op-code
0
1
0
1
0
1
1
Z
1
1
1
1
1
1
1
DATA
0
1
0
1
1
1
1
DATA
1
0
1
0
1
1
1
tIIf HA[T
ST
Z
1
1
1
1
1
1
1
Addl8Ss
0
1
0
1
0
1
0
MC,
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC,
T,T2T3
HL
DATA
0
1
0
1
1
1
1
MC.
T,T2T3
BC
DATA
1
0
1
0
1
1
1
1st
T,T2T3
1st op-code
Address
op-code
0
1
0
1
0
1
0
MC,
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC,
T,T2T3
HL
DATA
0
1
0
1
1
1
1
MC.
T1T2T3
BC
DATA
1
0
1
0
1
1
1
Z
1
1
1
1
1
1
1
1st
T,T2T3
1st op-code
Address
op-code
0
1
0
1
0
1
0
MC,
T,T2T3
2nd op-code
Address
op-code
0
1
0
1
0
1
1
MC,
T,T2T3
HL
DATA
0
1
0
1
1
1
1
MC.
T,T2T3
BC
DATA
1
0
1
0
1
1
1
MC,
T ,T2T3
1st op-code
Address
1st
op-codo
0
1
0
1
0
1
0
MC,
T ,T2T3
SP
DATA
0
1
0
1
1
1
1
MC,
T,T2T3
SP+1
DATA
0
1
0
1
1
1
1
1st
T ,T2T3
1st op-code
Address
0
1
0
1
0
1
0
MC,
MC,
-MC.
MC,
OTIR
OTDR
(W B,=O)
ME
T,T2T3
MC,
OTIR
OTDR
(W B,*O)
Wli
DATA
1st
op-code
1st op-code
OUTI
OUTD
IIfj
ADDRESS
1st op-code
Address
MC,
OTIMR
OTOMR
(W Br=O)
States
Cvcle
TITI
2nd
POP zz
POP IX
POPIY
MC,
op-code
(to be continued)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
551
HD64180R/Z
Instruct",n
Machine
Cycle
States
2nd op-code
POP IX
POP IY
DATA
ADDRESS
i'iD
WR
ME
IOE
DR
HAi:T
ST
.
MC,
T1T2T3
Address
2nd
op-code
0
1
0
1
0
1
1
MC,
T,T2T3
SP
DATA
0
1
0
1
1
1
1
MC,
T,T2T3
SP+l
DATA
0
1
0
1
1
1
1
T,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
MC,
MC,
-MC,
TITI
PUSH zz
MC,
T1T2T3
SP-l
zzH
1
0
0
1
1
1
1
MC,
T1T2T3
SP-2
zzL
1
0
0
1
1
1
1
T,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
Z
1
1
1
1
1
1
1
SP-l
IXH
IYH
1
0
0
1
1
1
1
SP- 2
IXL
IYL
1
0
0
1
1
1
1
0
1
0
1
0
1
0
MC,
MC,
PUSH IX
PUSH IY
MC,
-MC4
MC,
MC.
TITI
T,T2T3
T,T2T3
MC,
T,T2T3
Address
1st
op-code
MC,
T,T2T3
SP
DATA
0
1
0
1
1
1
1
MC,
T,T2T3
SP+l
OATA
0
1
0
1
1
1
1
T,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
1st op-code
RET
RET f
Ilf condmon
IS falsel
r-------RET f
(If conditIOn
MC,
MC,
-MC,
TITI
MC,
T,T2T3
MC,
T,
MC,
T,T2T3
SP
DATA
0
1
0
1
1
1
1
MC,
T,T2T3
SP+l
DATA
0
1
0
1
1
1
1
T ,T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T2T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
IS true)
1--RETI
RETN
MC,
MC,
(to be continued)
~HITACHI
552
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180RlZ
InstNclion
RE11
MacIme
S_
~
ADDRESS
DATA
RI5
"WI{
W
N
111
'mT
ST
MC.
T,12Ta
SP
DATA
0
1
0
1
1
1
1
MC.
T,T.T.
SP+l
DATA
0
1
0
1
1
1
1
1 st op-c:ode
1st
MC,
T,T.T.
Addnoss
op-c:ode
0
1
0
1
0
1
0
1st op-c:ode
MC,
T,T.T.
Addraos
1st
op-c:ode
0
1
0
1
0
1
0
2nd
op-c:ode
0
I
0
1
0
1
1
RETN
RLCA
RLA
AReA
RRA
ALCg
ALg
RRCg
RRg
SLAg
SRAg
SALg
2nd op-c:ode
MC.
T,12T3
MC.
n
Addnoss
·
1 st op-c:ode
MC,
ALC (HlJ
RL tHU
ARC (HU
RR tHU
SLA tHU
SRA tHU
SAL tHU
ALC ax+d)
ALC GY+dl
RL ax+dl
AL GY+dl
ARC QX+d)
RACGY+dl
RR QX+dl
RR oY+dl
SLA OX+dl
SLA oY+dl
SRA OX+dI
SRA oY+dl
SAL OX+dl
SAL oY+dl
Addraos
2nd op-c:ode
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
MC.
T,12T3
Addraos
2nd
op-c:ode
MC.
T,T.T.
HI.
DATA
MC.
n
MC.
T,T2Ta
·
z
HL
DATA
1
0
0
1
1
1
1
l.t op-c:ode
T,12T3
Addnoss
1st
op-c:ode
0
1
0
1
0
1
0
T,T.T.
2nd op-c:ode
Addraos
2nd
op-c:ode
0
1
0
1
0
1
1
T,T.T.
1st operand
Address
d
0
1
0
1
1
1
1
T,T.T3
3rd op-c:ode
Addnoss
op-code
0
1
0
1
0
1
1
MC.
T,12T3
lX+d
lY+d
DATA
0
1
0
1
1
1
1
MC.
Ti
1
1
1
1
1
1
1
MC,
Me.
MC.
MC.
MC,
MC,
RLD
RRD
T,12T3
z
1st
op-c:ode
3rd
·
Z
T112Ta
lX+d
lY+d
DATA
1
0
0
1
1
1
1
T,12T3
1st op-c:ode
Address
1st
op-c:ode
0
1
0
1
0
1
0
2nd op-c:ode
2nd
MC.
T,T2T3
Addraos
op-c:ode
0
1
0
1
0
1
1
MC.
T,12Ta
HL
DATA
0
1
0
1
1
1
1
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
553
HD64180R/Z
Instruction
RlD
RRD
Machine
Cycle
States
ADDRESS
DATA
liD
WR
ME
IOE
m
HA[i'
ST
Z
1
1
1
1
1
1
1
MC.
-MC,
TiTiTiTi
MC.
T,T2T3
Hl
DATA
1
0
0
1
1
1
1
Tl12T3
1st op-code
Address
lst
op-code
0
1
0
1
0
1
0
1
1
1
1
1
1
1
MC,
MC,
-MC.
Z
TiTi
RSTv
SCF
MC.
T1T213
SP-l
PCH
1
0
0
1
1
1
1
MC.
T,12T3
SP-2
PCl
1
0
0
1
1
1
1
T,T213
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T213
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,T213
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC.
Ti
Z
1
1
1
1
1
1
1
T,T213
1st op-code
Address
lst
op-code
0
1
0
1
0
1
0
MC,
T,T213
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC.
1,T2T3
Hl
DATA
0
1
0
1
1
1
1
MC.
Ti
1
1
1
1
1
1
1
MC.
T,T213
Hl
DATA
1
0
0
1
1
1
1
T1T2T3
1st op-code
Address
lst
op-code
0
1
0
1
0
1
0
T,T213
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
Tl1213
lst operand
Address
d
0
1
0
1
1
1
1
T,T 2T3
31d op-code
Address
31d
op-code
0
1
0
1
0
1
1
MC.
T,T213
lX+d
lY+d
DATA
0
1
0
1
1
1
1
MC.
Ti
1
1
1
1
1
1
1
1
0
0
1
1
1
1
MC,
MC,
SET b.g
RES b.g
MC,
SET b. IHU
RES b. IHU
MC,
MC,
SET
SET
RES
RES
b.
b.
b.
b.
CIX+dl
oY+dl
IIX +
N
Q)
•
o
""
DMA cycle
beglllS at the
end of MC
~~
;; :I
-
"~~
BUSREG
~ :I
Interrupt
;?(')
•
OJ
Bus IS released
at the end of
MC
INTo,
INT,
m.,
",.
Accepted after
executing the
current
Instruction
U>
ct>
Intemal
(")
110
..,.
o
Interrupt
CD
Ar.r.p.ntahle
!
!
ex;
!
•
!
~
NOTE)
I
MC
Cl
Cl
-..J
Z
~
o"II
Not acceptable
m
:II
~
Z
Gl
~
o
om
!
!
!
I
Acceptable
Return from
SYSTEM STOP
mode to normal
operation
::r:
t1
CD
W
!
Not acceptable Acceptable
Interrupt
DMA cycle
acknowledge
stops
cycle precedes
NMI IS accepted
after executing
struction
g::
o
o
!
!
the next In-
.2J
00
til
Not acceptable
!
'f'
<0
Not acceptable
• After BUS
RELEASE cycle,
DMA cycle
begIns at the
end of one
MC
executing the
current
Instruction
NMI
o
m
m
Q)
»
~
J:
cr
:::l
m
»
z
(')
not acceptable when DMA Request IS In level sense
same as the above
Machine Cycle
en
~
~
CXl
o
~
N
HD64180R/Z
Type 1, Type 2, and Type 3 requests priority is shown as follows.
hillhest priority Type I > Type 2 > Type 3 lowest priority
Each request priority in Type 2 is shown as follows.
hiahest priority Bus Req. > Refresh Req. > OMA Req. lowest
priority
2.. RIQUIST PRIORITY
The H064180 has the followina three types of requests.
Type 1.
To be accepted in specified state ........... WAIT
Type 2.
To be accepted in each machine cycle ...... Refresh Req.
OMA Req.
Bus Req.
Type 3.
(NOTE) If Bus Req. and Refresh Req. occurs simultaneously, Bus
Req. is accepted but Refresh Req. is cleared.
Refer to "2.7 Interrupts" for each request priority in Type 3.
To be accepted in each instruction ......... Interrupt Req.
21 OPERATION MODE TRANSITION
NOTEl
'1 NORMAl' CPU executes ,nstructions normally In NOlIMAL mode.
'2 OMA request· DMA is requested in the folowing e....
mmr.
(1) 15lIEOO.
= 0 ("""""'" ~ (memory mapped)
(2) OEO
1 (memory ~ memory DMA tran.!erl
=
'3
VO OMA tran.fer)
OMA end: OMA end. in the tollowing coses.
(1) 15lIEOO. llREQ;
1 (mamory ~ (memory mapped) VO DMA trans!erl
(2) BCRO. BCRl = OOOOH (all OMA tran.t....)
Othor _lion mode tranaltion.
The folloWing OperatIOn mode transitions 8re also possible.
1.
HALT
:;;::::::::
=
(3) ~
=
0
fall
~~~ESH
IOSTOP
DMA transfers)
;MA
}
REFRESH
BUS RELEASE
1
l;us RELEASEJ
2
SLEEP
:;:::::::::
BUS RELEASE
SYSTEM STOP ;;::: BUS RELEASE
~HITACHI
558
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300
HD64180R/Z
26 STATUS SIGNALS
The followmg table shows pm outputs m each operating mode.
Mode
CPU
operatIon
LlR
ME
lOE
RD
WR
REF
Op-code Fetch
(1st op-code)
0
0
1
0
1
1
1
Op-code Fetch
(except 1st
op-code)
0
0
1
0
1
1
1
ST
Address
BUS
Data
BUS
1
0
A
IN
1
1
A
IN
HALT BUSACK
Memory Read
1
0
1
0
1
1
1
1
1
A
IN
Memory Write
1
0
1
1
0
1
1
1
1
A
OUT
VO Read
VO Write
1
1
0
0
1
1
1
1
1
A
IN
1
1
0
1
0
1
1
1
1
A
OUT
1
1
1
1
1
1
1
1
1
A
IN
Internal
Operation
Refresh
nterrupt
NMI
~cknowledg
INTo
eVcle
(15t machIne INT" INT. &
Internal Interrupts
cle)
"v
1
0
1
1
1
0
1
1
.
A
IN
0
0
1
0
1
1
1
1
0
A
IN
0
1
0
1
1
1
1
1
0
A
IN
1
1
1
1
1
1
1
1
0
A
IN
IN
1
Z
Z
Z
Z
1
1
0
.
Z
HALT
0
0
1
0
1
1
0
1
0
A
IN
SLEEP
1
1
1
1
1
1
0
1
1
1
IN
Memory Read
1
0
1
0
1
1
1
1
0
A
IN
Memory Write
1
0
1
1
0
1
1
1
0
A
OUT
BUS RELEASE
Internal
DMA
1/0 Read
1
1
0
0
1
1
1
1
0
A
IN
110 Write
1
1
0
1
0
1
1
1
0
A
OUT
1
1
1
1
1
1
1
1
1
Z
IN
RESET
NOTE) 1
HIGH
LOW
A
Programmable
Z
High Impedance
IN
: Input
OUT. Output
. invalid
o
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
559
HD64180R/Z
17 PIN STATUS DURING RESET AND LOW POWER OPERATION MODES
Pin No.
Symbol
4
WAlT'
II
II
7
IBlJs"CK
IBUBflfU
8
Im:.f
e
10
11
12
13-30
31
-
l~
-
lINT.
lINT,
1m;
ST
A.-A"
A,.tlTOUT
34-41 0.-0,
42
RTSo
43 ICTS"
44
iD<:Do
45
TXA.
RXA.
47
CKAoiOREO.
TXA,
RXA,
CKA,lTENOo
51
TXS
52
RXS/CTS,
53
CKS
RESET
SLEEP
IOSTOP
SYSTEM STOP
IN(N)
IN IN)
IN lA)
IN IN)
1
OUT
IN IN)
OUT
IN IAl
IN lA)
OUT
IN lA)
0
IN IAl
IN lA)
IN IA)
IN IN)
IN lA)
IN lA)
IN IN)
IN lA)
IN lA)
INiAl
INIAl
INiAl
IN lA)
IN lA)
IN lA)
IN lA)
IN lA)
IN IN)
1
,
Z
1
IN IN)
OUT
A
1
1
AI,\
Z
1
A
1
TOUT
Z
OUT
H
H
-
Z
Z
A
Z
-
1
H
OUT
H
IN IN)
IN lA)
IN IAl
IN IN)
IN IN)
IN IN)
1
OUT
H
H
-
IN IN)
IN lA)
CKA.
!internal clock mode)
z
OUT
IN IN)
Z
IN IN)
Z
CKA.
lextemal clock model
Z
IN lA)
IN IN)
IN IN)
DREOo
z
IN IN)
IN lA)
IN IN)
-
1
OUT
H
H
IN IN)
IN IAl
IN IN)
IN IN)
CKA,
Ilnternal clock mode)
Z
OUT
Z
Z
CKA,
(external clock mode)
Z
IN lA)
IN IN)
IN INI
TENDo
Z
1
OUT
1
-
1
OUT
H
H
RXS
Cf5,
IN IN)
INIAl
IN IA)
IN IN)
IN INI
IN IN)
IN IN)
CKS
(Internal clock mode)
Z
OUT
1
1
CKS
(external clock model
Z
IN lAl
Z
Z
IN IN)
IN IN)
-
45
48
49
50
Pin ltatul In nch opntlon mod,
Pin funotlon
IN IN)
IN IN)
54
OREO,
-
IN INI
IN INI
INIAl
55
TEND,
1
1
OUT
1
56
HAlT
-
1
0
OUT
0
57
REF
1
OUT
1
IOE
1
1
OUT
1
59
m-
-
1
58
-
1
1
OUT
60
61
82
E
-
0
E clock output
DR
-
1
1
-
OUT
-
WR
-
1
1
OUT
1
1
1
'" clock output
-
OUT
-
-
83
64
-
RD
'"
1: HIGH
0: LOW
N 1Al: input iAcIIve)
-
1
1
1
A: Programmable
Z: Hogh Impedanca
N (N). input (Not active)
OUT: Output
H. Holds the previous state
-: .ame as the left
~HITACHI
560
Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
28 INTERNAL I/O REGISTERS
By programming lOA 7 and IOA6 in the 110 control register, m-
REGISTER
I MNEMONICS
ASCI CQntrol RegISIer A Channel 0
CNTLAO
ternal 110 register addresses are relocatable within ranges from
OOOOH to OOFFH in the 110 address space.
ADDRESS
o
REMARKS
0
MPE
bit
RE
TE
li'm
MPBRI
EfR MOD2 MODI MODO
dumg RESET
0
0
0
1
invalid
0
0
0
RIW
RIW
RMI
RIW
RIW
RIW
RIW
RIW
RIW
t
L
MODE SelectIon
Multi Processor Bit RecoiwI
EnorFlag~
Request To Send
Enable
~ Transmrt
~ Recatve Enable
'-- Multi Procassor Enable
ASCI Control Regosler A Channel 1
CNTLAI
o
1
MPE
bit
RE
TE
CKAID MPBRI MOD2 MODI MODO
EFR
during RESET
0
0
0
1
onvalld
0
0
0
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
II
LMODE SelectIon
Multi Proces.... BIt Recetve/
EITDI' Flag Reset
~CKAI DIsable
~ Transmrt Enable
~ Recatve Enable
~ Multi Processor Enable
MOD2.1.0
000
001
0' 0
0' 1
'00
'0'
1 10
,,,
IAscl Control Regosler B Channel 0
CNTLBO
o
2
Start
Start
Start
Start
Start
Start
Start
Start
+ 7 bit Data + 1 Stop
+ 7 bd Data + 2 Stop
+ 7 bit Data + Panty + , Stop
+ 7 bit Data + parrty + 2 Stop
+ 8 bit Data + , Stop
+ 8 bit Data + 2 Stop
+ 8 bit Data + Panty + , Stop
+ 8 bit Data + parrty + 2 Stop
bd
MPBT
MP
dumg RESET
l,.aIod
0
RIW
RIW
RIW
C1'S1
PS
RIW
PEO
DR
SS2
SSt
0
0
1
1
1
RIW
RIW
RIW
RIW
RIW
L
SSO
L
Clock Source and
Speed Select
Divide Ratoo
'-Parity Even or Odd
~ Clear To Send/Prescale
~ Multi Proces....
Multi Procassor BIt Transmrt
• CTS . Dependong on the conditoon of CTS Pon .
PS . Cleared to 0
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
561
HD64180R/Z
REGISTER
I MNEMONICS
ASCI Control RegISter B Channel 1
. CNTlBl
ADDRESS
o
REMARKS
3
brt
MPBT
MP
CTS/
PS
PEO
DR
SS2
551
during RESET
Invalid
0
0
0
0
1
1
1
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
SSO
L
II
Clock Source and
Speed Select
Divide Ratio
~ Panty Even or Odd
L.... Clear To Send/Prescale
'- Muttl Processor
'-MullJ Processor Brt Transmrt
General
dIVide ratio
o
4
PS=l
(divide ratio= 30)
DR-O (X 16)
DR-l (X64) DR-O (X 16) DR-l (X64)
000
001
010
011
100
101
110
+
+
+
+ 640
+ 1280
111
External clock (frequency
bit
552.1.0
ASCI Status ReglStar Channel 0
STATO
PS=O
(dIVide ratio= 10)
+
+
+
+
160
320
640
1280
2560
5120
10240
+
2560
+ 5120
+ 10240
+20480
+40960
<
:
+
480
960
+ 1920
+ 3840
+ 7680
+ 15360
+30720
+
+
+
+
+
+
+
1920
3840
7680
15360
30720
61440
122880
+40)
RDRF
OVRN
PE
FE
RIE
during RESET
0
0
0
0
0
RIW
R
R
R
R
RIW
DCDO TORE
R
..
TIE
R
RIW
0
T~smrt
Interrupt
Enable
Data
Register Empty
Data Camer Datect
'-- Receiv.lnterrupt Enable
'-- Framing Error
'-Parity Error
•• C'fSo Pinl TORE
L.... Over Run Error
l
1
' - Receive Data Registar Full
H
0
: Dapending on the condition of I5CDo Pin.
Transm~
.~
IASCI Status Register Channel 1
: STAn
o
5
I
bit
RDRF
OVRN
PE
FE
RIE
during RESET
0
0
0
0
0
0
1
0
RIW
R
R
R
R
RIW
RIW
R
RIW
CTS1E TORE
TIE
rtansmit
Interrupt
Enable
Tran.m~ Data
RegISter Empty
'- ffi1 Enable
'- Receive Intenupt Enable
.... FramingError
'-Parity Error
'- Over Run Error
Reooive Data Register Full
Ito bs continUecIl
~HITACHI
562
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
REGISTER
I MNEMON)CS
ASCI T ransm~ Data Regislilt' Channel
o
ADDRESS
REMARKS
0 6
: TORO
ASCI Transmrt Data Regislilt' Channel
0 7
1
TOR1
ASCI Receive Data RegISter Channel
o
0 8
TSRO
ASCI Receove Data RegISlilt' Channel
0 9
1
. TSR1
CSVO Control RegISter
. CNTR
o
A
bit
EF
EIE
RE
TE
-
552
S51
during RESET
0
0
0
0
1
1
1
1
RIW
R
RIW
RfW
RIW
RfW
RIW
RIW
l, l
550
LSpeed Select
TransmHnabie
Receive Enable
L- End Interrupt Enable
End Flag
S52,1,O
Baud Rate
o
CSVD TransmrtlReceove Data
RegISter
552,1,0
t/>+ 20
000
001
010
011
Baud Rate
t/>+ 320
100
101
110
11 1
+40
+80
+160
+ 640
+1280
Extemal
(frequency < + 20)
B
TRDR
T,,"or Data RegISter Channel OL
. TMDROL
0 C
Timer Data Regislilt' Channel OH
. TMDROH
0 0
Timor Reload Regislilt' Channel OL
. RLDROL
0 E
Timer Reload RegiSlilt' Channel OH
. RLDROH
0 F
Timor Control Regislilt'
1 0
bit
. TCR
~T~F-11_TFO~-+_T~IE_l-+_TlE70-1~T~OC~1+-TO~C~0-+T_D7E_1-rTOE~0~
::-+:
1:-:07:-t-::-0:::-;-+::-:0::-l~D::-:-t-::70::-1
0
during RESET 1--=-0-t--:0:--f-=7.
RIW
R
R
RIW
RIW
RIW
RIW
RIW
RIW
~~=*~==~~~~==~
L
LTinerDown
Count Enable 1,0
Timer Output Control 1,0
Timer Interrupt Enable 1,0 I
Timer Interrupt Flag 1,0
TOC1,O
00
01
10
Inhibited
11
1
Toggle
o
110 be continued)
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
563
HD64180RlZ
REGISTER
I
MNEMONICS
ADDRESS
Timer Data Register Channel I L
· TMORIL
I
4
Timer Data Register Channel I H
: TMORIH
I
5
Timer Reload Register Channel I L
: RLDRIL
I
6
Timer Reload Ilegister Channel I H
· RLDRIH
I
7
Free Runmog Counter
I
8
REMARKS
reed only
FRC
DMA Source Address Register
Channel OL
SAROL
2 0
OMA Source Address Register
ChannelOH
· SAROH
2
DMA Source Address Regis1ar
Channel OB
SAROB
2 2
DMA Destination Address Register
Channel OL
: OAROL
2 3
DMA Destination Address Register
ChannelOH
·OAROH
2
DMA Oest.,atlon Address Register
Channel OB
: OAROB
2 5
DMA Byte Count Register Channel
I
Bits 0-2 _
used for SAROB
A,e. AH. A ••
X
X
X
X
0
0
I
I
0
I
0
I
OMA Transfer Request
DREGo lex1arnall
RORO (ASCIO)
RORI (ASCI!)
Not Used
4
Bits 0-2 are used for OAROB.
A,e, An, A ••
2 6
X
X
X
X
0
0
I
I
0
I
0
I
OMA Transfer Request
DREao Ie,ternan
TORO (ASCIO)
TORI (ASCII)
Not Used
OL
· BCROL
DMA Byte Count Register Channel
OH
: BCROH
2 7
DMA Memory Address Register
ChanneltL
: MARIL
2 B
DMA Memory Address Register
ChannellH
: MARtH
2 9
DMA Memory Address Register
ChannellB
: MARIB
2 A
DMA
IL
VO Address Register Channel
Bits 0-2 are used for MAR I B
2 B
: IAR1L
DMA VO Address Register Channel
IH
IARIH
2 C
Ito be continued)
~HITACHI
564
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180RlZ
REGISTER
I MNEMONICS
OMA Byto Count Regiotllr Channel
REMARKS
ADDRESS
2 E
lL
: BCRIL
OMA Byto Counl Regiotllr ChInneI
2 F
lH
: BCRIH
3 0
OMA S18tuS Regiotllr
: DSTAT
bit
DEI
DEO
during RESET
0
RIW
0
RIW
RIW
OWEI OWEO
1
1
W
W
DEI
0
DEO
0
RIW
RIW
-
DME
1
0
R
=-
Enable
'[)MA ntllrnlpl E _ 1,0
-OMA E _ Bit Write E _ 1,0
-OMA Enable ch 1,0
3 1
OMA Mode Rogiol8r
bit
-
-
OMI
DMO
during RESET
1
1
0
0
RIW
: DMODE
RIW
RIW
SMI
0
SMO
0
RIW
RIW
~
-
0
RIW
1
LMemory
MOOE
Select
-
L-
OMI, 0 Destln8Don
00
M
01
M
10
M
1 1
VO
MMooi
0
1
I
AddnIso
DARO+l
DARO-l
DARO fi.ed
DARO fbead
Ch 0 Source
Mode 1,0
Ch 0 Destination
Mode 1,0
SM1,O Souroe
M
00
o1 M
M
1 0
VO
1 1
AddnIso
SARO+l
SARO-l
SARO fixed
SARa fixed
Mode
Cycle Steal Mode
Bursl Mode
(to be continued)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
565
HD64180R/Z
REGISTER
I
MNEMONICS
DMAIWAIT Control Register
AODRESS
3 2
. DCNTl
REMARKS
bit
MWlI
MWIO
MIll
!WID
during RESET
1
1
1
1
0
0
0
0
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
OMSI OMSO OIMI
OIMO
LaMA Ch 1
1'0 Memory
Mode Select
-I5ftml'SeIect. i = 1.0
'-1'0 Wa~ Insertion
L-
Memory
Wa~
Insertion
The number of
wa~slal8S
MWlI.0
00
01
10
11
I
OMSi
0
1
2
3
Sense
Edge sense
sensa
o
DIM 1.0
3 3
Addl88s Increment/Decrement
Transfer Mode
MARl + 1
MAR1-l
fARl fixed
fARl fixed
M-VO
M-VO
00
01
10
11
:11.
0
2
3
4
00
01
10
11
I level
1
Interrupt Vector low Register
The number of
wa~ slalas
MIIl.0
VD-M
VD-M
fARl fixed
IARI fixed
MAR1+l
MAR1-1
bit
1.7
1.6
1.5
-
-
-
-
-
during RESET
0
0
0
0
0
0
0
0
RIW
RIW
RIW
RIW
ITEO
Llnterrupt Vector low
NT!TRAP Control Register
3 4
.ITC
bit
TRAP
UFO
-
-
-
ITE2
ITEI
during RESET
0
0
1
1
1
0
0
1
RIW
RIW
R
RIW
RIW
RIW
l. l
U_ed FoWh
TRAP
Refl88h Control Register
3 6
. RCR
o~
LiNT' Enable 2.1.0
bit
REFE
REFW
-
-
-
-
CYCI
during RESET
1
1
1
1
1
1
0
0
RIW
RIW
RIW
RIW
RIW
II
.~h
Refraoh Enable
CYC1.0
CYCO
ICvele Select
WM Slala
Interval of Refraoh Cycle
00
01
10
11
10 Slalas
20
40
80
(to be
contmuodl
@HITACHI
566
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Poin! Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180R/Z
REGISTER
I
MNEMONICS
MMU Common Base Regislllr
REMARKS
ADDRESS
3 8
. CBR
bit
-
during RESET
0
RIW
RIW
C86
C85
C84
CB3
CB2
CBl
CBO
0
0
RIW
0
0
RIW
0
0
RIW
R/W
RIW
RIW
RIW
0
LMMU Common Base Regislllr
MMU Bank Base Regislllr
3 9
: BBR
bit
-
BB6
BB5
B84
883
BB2
BBl
BBO
during RESET
0
RIW
0
RIW
0
RIW
0
RIW
0
RIW
0
0
RIW
R/W
0
RIW
RIW
L- MMU Bank Base Regislllr
MMU CommonlBank AI88 Ragislllr
: CBAR
3 A
bit
CA3
CA2
CAl
CAO
SA3
SA2
SAl
BAD
during RESET
1
1
1
1
0
RIW
RIW
RIW
RIW
RIW
0
RIW
0
RIW
0
RIW
RIW
L MMU Bank
AI88 Regislllr
LMMUCommon
AI88 Ragislllr
VO Control Regislllr
3 F
ICR
bit
IOA7
IOA6
IOSTP
-
-
-
-
-
during RESET
0
RIW
0
0
RIW
1
1
1
1
1
RIW
RIW
L,
Lvo
Stop
VO AddRlSS
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
567
HD64180S
NPU (Network Processing Unit)
• DESCRIPTION
The HD64IS0S, network processing unit (NPU), provides multipurpose
hIgh-speed communication control functions on a single LSI chip. The
HD64IS0S offers high performance communication protocol processing, as well as user system application processing, at a low cost.
Built-in features, such as an S-bit CPU, 2 serial 110 channels, and a
direct memory access controller (DMAC, support hIgh-speed data
transfer by reducing communications overheads.
The HD64IS0S has a variety of applications. It can be used as a
communication subsystem processor or as a controller in a distributed
control system for industrial robots.
In addition, the HD64IS0S is designed to interface with existing
communication chips and to be compatible with existing communication software. It can be used with virtually any kind of communication
system.
This manual deSCrIbes HD64IS0S hardware. For details about programming instructions refer to the HD64IS0 Programming Manual
(M21T038).
(CP-S4)
• Overview
The HD64IS0S network processing UOIt (NPU) contains a 2-channel
serial interface, S-bit CPU, 2-channel direct memory access controller
(DMAC) with a proprIetary chained-block transfer function, tImers,
etc., all integrated on a single LSI chIp. The HD64IS0S is thus well
suited to multiprotocol commUnIcatIons processlOg.
The multiprotocol serial communicatIOns interface (MSCI) and the
asynchronous serial communications interface/clocked serial 110 port
(ASCIICSIO) allow high speed data transfer using various communications protocols.
In particular, the MSCI IS capable of handling asynchronous, byte
synchronous, and bit synchronous communications protocols. Since the
MSCI is connected to the on-chip DMAC, It is possible to reahze high
speed single-address DMA transfer (chained-block transfer) in frame
units during bit synchronous communications. Furthermore, the flexible processing capability ofthe HD64IS0S's CPU ensures compatibility
with a wide range of communications protocols.
(FP-SOA)
• FEATURES
CPU
·Software-Compatible with HD64IS0Z
• SO type bus interface
• On-chip MMU (I Mbyte physical address
space)
DMAC
• 2 channels
• DMA transfer between memory and memory,
memory and 110 (memory-mapped 110), and
memory and MSCI
• Chained-block transfer between memory and
MSCI
• Internal interrupt requests available
Multiprotocol serial • Full duplex channel
• Asynchronous, byte synchronous (mono-, bi-,
interface (MSCI)
or external synchronous), or bit synchronous
(HDLC or loop) selectable
• Transmit/receive control using modem control
signals (RTSM, CTSM, and DCDM)
• Internal Advanced Digital PLL (ADPLL)
clock extraction
receive data and/or receive clock nOIse
suppression
• On-chip baud rate generator
• Internal interrupt requests available
• Maximum transfer rate 7.1 Mbps (with 10
MHz clock)
communications
Asynchronous serial • Full duplex channel
communicatIOns
• Asynchronous clocked serial mode
interface/clocked
(selectable)
• Transmit/receive control using modem control
serial I/O port
(ASCIICSIO)
signals (RTSA, CTSA, and DCDA)
• On-chip baud rate generator
• Internal interrupt requests available
Timers
• 2 channels
• S-bit reloadable up-counter
• Output waveform generator and external event
count func\ions
• Internal interrupt requests available
Interrupt controller • Four external interrupt lines (NMI, INTo,
INT I, and INT2)
• Fifteen internal interrupt sources
Memory access
Internal refresh controller
support function
• Internal wait state controller
• Internal chip-select controller
Other functions
• On-chip clock oscillator circuit
• Low power dissipation modes (sleep and
system stop)
~HITACHI
568
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• TYPE OF PRODUCTS
Product Name
Max. Operating Frequency
HD64IS0SCP6
6.17 MHz
HD64ISOSCPS
S MHz
HD64IS0SCPI0
10 MHz
HD64IS0SH6
6.17 MHz
HD64IS0SHS
SMHz
HD64IS0SH 10
10 MHz
Package
CP-S4 (S4-pin PLCC)
FP-SOA (SO-pin QFP)
• PIN ASSIGNMENT
...
WAIT
oeDA
INT.
RlSA
M-
....,
TXDM
RESET
.XeM
BUSREO
RXIlIA
Vuo
CTSM
BUSACK
DCDM
ST
llR
Ai-8M
SYNC
ROF
v"
"AlT
RD
D,
TXCM
Do
'"
'"
0.
D,
0.
WAif
N"MI
1N'Fo
INTi
fNi2
miff
IlUSRnQ
S'I
OR
REF
n=
RIl
WI!
Mil
IDE
AU
AI
A2
Top View
(CP-S4)
Top View
(FP-SOA)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
569
HD64180S
t-
C.
ILU
~ I~ I~I~ I~I~ I~ I~I~
CPU
TINo
TINl
TOUTo
TOUTl
DREQo
Timers
with 8-bit
reloadable
up-counter
(2 channels)
DMAC
with chained
block transfer
function
(2 channels)
til
:B
0
!:£.
Ul
.c
.c
co
iii
f!:!
'0
'0
SYNC
:is
Ul
::l
TENDo
TENDl
(j)
£:!.
Ul
Ul
DREQl
TXDM
RXDM
::l
0
MSCI
(1 channel)
TXCM
RXCM
«
RTSM
DCDM
CTSM
TXDA
RXDA
TXCA
ASCI/CSIO
(1 channel)
RXCA
RTSA
- DCDA
CTSA
Ao-A19
* CS 2 is not output in FP-80A
Do-D7
-E--
Vee
~
Vss
Figure 1. Block Diagram of the HD64180S
~HITACHI
570
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, GA 94005-1819 • (415) 589-8300
HD64180S
• Applications
• Position in Product Line
The HD64180S's on-chip CPU (software-compatible with the HD64180Z) is capable of processing
both communications protocols and user application programs. If the on-chip CPU is programmed for
use mainly as a communications processor, application processing can be carried out by another CPU.
Figure 2 illustrates this concept.
100%
::J
Q.
HD64180S
On-chip CPU
processing capability
o
c.
:co
C:
Communications protocol processing
o
O%L---------------------------------~
CPU oriented to application processing
CPU oriented to communications
protocol processing
Figure 2. Allocating CPU Processing Capability
For example, the HD64180S's CPU can be used mainly for communications protocol processing to
provide various communications functions for a host CPU. This is suitable in situations requiring
high-speed data transfer and/or complicated protocol processing. In this case, a flexible interface can
be configured with the host CPU by selecting appropriate software and I/O devices.
On the other hand, the HD64180S's CPU can be used for application processing (i.e., when data
transfer occurs infrequently and/or at low speeds). In this case, the MSCI, ASCI/CSIO, and DMAC in
the HD64180S can process the communications data so as to reduce CPU overhead.
Thus the HD64180S can be used in a wide range of applications-from small-scale configurations
containing two or three chips to large-scale configurations containing mass memory and numerous I/O
devices.
•
HITACHI
Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300
571
HD64180S
• Examples of System Configuration
(1) Data communications system
Figure 3 shows a system configured with a data communications subsystem. This system can be used for
communications between computers in a public network or in an office automation (OA) system.
system.
Local 1/0
Communication lines
~
~
Host CPU
Main memory
1/0 subsystem
Data
communications
subsystem
(with HD64180S)
1
I
I
I
System bus
Figure 3. Example Configured with a Data Communications Subsystem
Figure 4 shows a minimum configuration example for the data communications subsystem
shown in figure 3. In this configuration, the host CPU loads the HD64180S control program
from main memory into the dual port RAM (DPRAM). The DPRAM has a transmit buffer,
receive buffer, and communications data status area for interfacing between the host CPU and the
HD64180S. Since the memory area allocated to this subsystem's communications program and
transmit/receive buffers is relatively small, the subsystem is well suited for low-speed, simple
communications protocols.
_HITACHI
572
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD64180S
1
Communication lines
Memory map
1
1Mb~er---------------.
Data communications
, . - - - - - - t ; " . - - - - - - - , subsystem
r-----~L-----~
1
kb~e I - - - - - - - - - - - l
Communication data status
Transmit buffer
Receive buffer
Communication control
program and data
~Do
OL----------_--l
Host CPU interface
Figure 4. Example of Data Communications Subsystem
(minimum configuration)
Figure 5 shows an extended communications subsystem for complex protocol processing and highspeed data transfer. This subsystem incorporates external memory and two stages of transmit/receive
buffers. The HD641S0S control program is loaded into external memory. This subsystem is easily
realized because the HD64180S can directly access up to 1 Mbyte of memory using its 20-bit address
bus.
Communication lines
Data communications subsystem
l'
~
I
1
Mb
Memory map
yte
\
Communications control
program and data
Extemal memory
(SRAM or DRAM)
HD64180S
I
Externa!
memory
r
J
[2 kby1e-1 Mbyte)
Communication data status
Transmit/Receive buffer
1 khyte
Communications data status
DPRAM (1 kbyte)
---
I-- -- ------1--------------------I
Transmit buffer
--
DPRAM
Host CPU interface
Receive buffer
0
Figure 5. Example of Data Communications Subsystem
(extended configuration)
.HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
573
HD64180S
(2) Distributed control system
Figure 6 shows an example in which the HD64180S is used as a distributed control device. This
configuration can be used for controlling industrial machinery or for communicating between control
devices of automobiles, OA systems, point-of-sales (POS) terminals, etc.
Communications network
for control devices
Data processing
and I/O processing
Data processing
and I/O processing
Data processing
and I/O processing
Figure 6. The HD64180S in a Distributed Control System
Figure 7 shows the internal configuration of the distributed control devices shown in figure 6. In
this configuration, the HD64180S is directly connected to an I/O device, and the external memory
(EPROM and RAM) contains the HD64180S control program and application programs. This simple
system also allows high-speed data processing by providing direct access to up to 1 Mbyte of memory
space including the data/stack and transmit/receive buffer areas .
•
574
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589-8300
HD64180S
Communications network
1-~80S
Distributed control device
External memory
(EPROM and RAM)
Memory map
1 Mbyte
Data/Stack area
:::2:
[4 kbyte-1 Mbyte]
~
",.
TransmiVReceive buffer
Dedicated 110 device
Communication
control program
l'
-lLocal 110 function
Application processing
program
:::2:
0
II:
0..
w
0
Figure 7. Internal Configuration of a Distributed Control Device Using the HD64180S
In the two configuration examples given above, the HD64180S is used either as a part of a data
communications subsystem or as a distributed control device. In addition, the HD64180S can be used
with various kinds of communications equipment.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
575
HD64180S
• Signal Descriptions
• Power Supply
Pin
Number
Input/
Symbol
CP-S4
}'P-SOA
Output
Vee
1,19,29,
8,41,71
Input
43,54
Vss
Remarks
+5V power supply: All Vee pins must be
connected to the
4,36,
24,29, 35,
41,48,
60, 74
Input
+ 5V system power supply.
Ground: All V ss pins must be connected to the
system ground.
63, 74
Note:
To minimize potential difference in the chip, use the shortest possible lead length to the Vee and Vss pins.
• Clock
Pin
Number
Inputl
Symbol
CP-S4
FP-SOA
Output
Remarks
XTAL
2
72
Input
Crystal resonator input: The input frequency must be
double that of the !II clock.
When the EXTAL pin is connected to an external
clock, the XTAL pin should be left floating.
EXTAL
3
73
Input
Crystal resonator or external clock input: The input
frequency must be double that of the !II clock. Figures
8 and 9 show crystal resonator and external clock
connection diagrams, respectively.
84
70
Output
System clock: Supplies the !II clock to peripheral
devices.
~HITACHI
576
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819· (415) 589·8300
HD64180S
EXTAL
XTAL
Figure 8. Example of Crystal Resonator Connection
EXTAL
XTAL
C~--- ~
'----!~.
~ .- -
External clock input
FI oat'Ing
Figure 9. Example of External Clock Configuration
• Reset Line
Pin
Number
Input/
Symbol
CP-S4
FP-SOA
Output
Remarks
RESET
17
6
Input
Reset: When this line is driven active low for 6 or more
clock cycles, the HD64180S enters the reset mode and
all functions are reset.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
577
HD64180S
• Address Lines
Pin
Symbol
Number
CP-B4
FP-BOA
Ao-AI9
30-35,
18-23,
37-40,
42,
44-47,
25-28,
30-34,
36-40
Input!
Output
Output
(Three
State)
49-53
Remarks
Address bus: This 20-bit address bus supports
1Mbyte of memory and a 64kbyte (l6-bit address
width) I/O space. The address bus goes to high
impedance during:
• Reset mode
• Passing control of the bus to another device (the
HD64180S is placed in the bus release mode when the
BUSREQ line is asserted).
• Data Lines
Pin
Number
Symbol
Input!
CP-B4
FP-BOA
Output
Remarks
55-62
42-49
Input!
Data bus: The 8-bit handles bi-directional
data passing (input and output of data.)
Output
(Three
State)
• Memory and I!O Interface Lines
Pin
Number
Symbol
Input/
Remarks
CP-S4
FP-SOA
Output
25
14
Output
Read: This line is asserted during read cycles.
(Three
When this line is driven active low, the data lines are
State)
used as inputs.
Output
Write: This line is asserted during write cycles.
(Three
When this line is driven active low, the data lines
State)
are used as outputs.
26
15
~HITACHI
578
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD64180S
Pin
Number
Input/
Symbol CP-S4
FP-SOA
Output
Remarks
ME
16
Output
Memory enable: This line is used to indicate a
(Three
memory read or write operation. It is asserted in the
State)
following cases:
27
Instruction fetch, operand read, and memory
o
read/write instructions
28
17
o
Memory access during DMA cycles
o
Refresh cycles
Output
I/O enable: This line is used to indicate an I/O
(Three
read/write operation. It is asserted in the following
State)
cases:
o
I/O read/write instructions
01/0 access during DMA cycles
o
WAIT
12
Input
INTo acknowledge cycles
Wait: This line is used to extend either memory or I/O
read/write cycles. If this line is low at the falling edge
of a T2 state, a Tw state is inserted. If the line is still
low at the falling edge of the inserted Tw state, an
additional Tw state is inserted. This process is
repeated until the signal level on this line is high at the
falling edge.
9
79
Output
Chip select: These lines are used to access one of the
CSl
10
80
Output
three physical address areas: PAL, PAM, and PAR.
CS2
11
Output
The partition of the physical address space is the same
as that of wait controllers.
1
Physical address
Signal
area accessed
asserted
PAL area
CSo
(lower physical address area)
2
PAM area
CSl
(middle physical address area)
3
PAR area
CS2
(upper physical address area)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
579
HD64180S
• System Control Lines
Pin
Number
Symbol
CP-S4
BUSREQ 18
Input!
FP-SOA Output
Remarks
7
Bus request: This line is asserted by an external device
Input
to request control of the bus. When this line is driven
active low, the internal bus master waits until the end of
the current machine cycle, then places the address lines,
the data lines, and some of the memory I/O interface
---
--
lines (RD, WR, ME, and IOE) into the high impedance
state.
BUSACK 20
9
Output
Bus acknowledge: This line is used by the internal bus
master to notify an external device by sending a
BUSACK signal that a BUSREQ signal has been
received and the bus has been released.
HALT
24
13
Output
HALT: This line is asserted whenever a HALT or SLP
instruction is executed. It indicates that the HD64180S
is in the halt, sleep, or system stop mode. This line is
also used in conjunction with the LlR and ST lines to
indicate the status of the CPU and internal DMAC.
LIR
22
11
Output
Load instruction register: This line is asserted during
opcode fetch cycles. This line can also be used to
output the Z80 peripheral LSI interface signal.
ST
21
10
Output
Status: This line is used, together with LlR and HALT,
to indicate the internal status of the HD64180S (see
table).
HALT
(1)
LlR
ST
Status
0*1
0
CPU active (first byte
of an opcode fetch)
*1
The upper value shows the LIR pin status when the LIRE bit of the operation mode control register is 1, and the lower
value shows tl.e LIR pin status when the LIRE bit is O.
~HITACHI
580
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
Pin
Number
Symbol
CP-84
FP-80A
Input/
Output
Remarks
(2)
1
0. 2
1
CPU active (second or
third byte of an opcode
fetch)
1
(3) X· 1
1
(4)
1
0
DMAC operation
Normal operating mode
(other than (1), (2),
or (3»
Reset mode
(5) 0
0. 2
0
Opcode fetch during
halt mode (no
instructions are
executed)
1
(6)
0
1
Halt mode (other than
(3) or (5»
Sleep mode (other than
(3»
System stop mode
REF
23
12
Output
Refresh: This line is asserted during the DRAM refresh
cycle. During this cycle, the refresh address is output
on the 12 low-order lines (Ao - All) of the address bus.
*1 X: Don't care
*2 The upper value shows the LIR pin status when the LIRE bit of the operation mode control register is I, and the lower
value shows the LIR pin status when the LIRE bit is O.
• Interrupt Lines
Pin
Number
Input/
Symbol CP-84
FP-80A
Output
NMI
2
Input
13
Remarks
Non-maskable interrupt: This line is used to request a
non-maskable interrupt.
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
581
HD64180S
Pin
Number
Input/
Symbol
CP-S4
FP-SOA Output
INTo
14
3
Input
Remarks
Interrupt 0: This line is used to request a level-O
maskable interrupt. There are three different modes for
level-O interrupts (see table).
Mode
Function
0
Executing the instruction on the data
bus
1
Executing the instruction at address
0038H
2
INTI
15
4
Input
Vector mode
Interrupt 1 and 2: These lines are used respectively
to request level-l and level-2 maskable
INT2
16
5
Input
interrupts (vector mode).
• DMA Lines
Pin
Number
Input/
Symbol
CI"-S4
FP-SOA Output
DREQo
80
66
Input
Remarks
DMA request for channel 0: This line is used to
request a DMA transfer using internal DMAC
channelO.
DREQI
81
67
Input
DMA request for channel I: This line is used to
request a DMA transfer using internal DMAC
channell.
TENDo
82
68
Output
Transfer end for channel 0: This line is used to indicate
the end of a DMA transfer using internal DMAC
channel O. It is asserted synchronously with the read
cycle upon the last data transfer.
TEND I
83
69
Output
Transfer end for channell: This line is used to indicate
the end of a DMA transfer using internal DMAC
channel 1. It is asserted synchronously with the read
cycle upon the last data transfer.
~HITACHI
582
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Serial 1/0 (MSCI) Lines
Pin
Number
Input/
Symbol
CP-S4
FP-SOA
Output
Remarks
TXDM
71
57
Output
Transmit data from the MSCI: This line is used to
output transmit data from the MSCI.
RXDM
68
54
Input
Receive data to the MSCI: This line is used to input
receive data to the MSCI.
TXCM
70
56
Input!
Transmit clock for the MSCI: This line is used to
Output
input/output the MSCI transmit clock.
Three programmable modes:
Input:
• External transmit clock
Output: • Transmit clock from the on-chip baud rate
generator
• Receive clock (used as the transmit clock)
RXCM
69
55
Input/
Receive clock for the MSCI: This line is used to
Output
input/output the MSCI receive clock. This line can also
be used to input the ADPLL operating clock.
Four programmable modes:
Input:
• External receive clock
• ADPLL operating clock
Output: • Receive clock extracted by the ADPLL
(when the on-chip baud rate generator is used
as the ADPLL operating clock)
• Receive clock from the on-chip baud rate
generator
RTSM
65
51
Output
Request to send for the MSCI: Indicates that the
HD64180S has data to be output to a communications
device such as modem. The output level can be
automatically controlled by MSCI operation (autoenable function). This line can also be used as a
general purpose output port.
DCDM
66
52
Input
Data carrier detect for the MSCI: Indicates that a
communications device such as modem is receiving
valid data from the communications line. MSCI receive
operation can be automatically controlled by this input
(auto-enable function). This line can also be used as a
general purpose input port.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
583
HD64180S
Pin
Number
Input/
Symbol
CP-S4
FP-SOA Output
CTSM
67
53
Input
Remarks
Clear to send for the MSCI: Indicates that a
communications device such as modem is ready to send
data to the communications line. MSCI transmit
operation can be automatically controlled by this input
(auto-enable function). This line can also be used as a
general purpose input port.
SYNC
64
50
Input/
Synchronization for the MSCI: This line is used
Output
as an input in the external byte synchronous mode.
Synchronization is established at the falling edge of
SYNC. This line is used as an output in the byte sync
(mono- or bi-) or HDLC mode. It indicates the inverse
of the SYNCD/FLGD bit in MSCI status register 1
(MSTl)*. In the asynchronous mode, this line is used
as an input. The input value does not affect operation.
*For details concerning MSCI status register I (MSTl), see "MSCI Status Register I."
• Serial 1/0 (ASCI/CSIO) Lines
Pin
Number
Input/
Symbol CP-S4
FP-SOA
Output
Remarks
TXDA
65
Output
Transmit data from the ASCI/CSIO: This line is used
79
to output transmit data from the ASCI/CSIO.
RXDA
76
62
Input
Receive data to the ASCI/CSIO: This line is used to
input receive data to the ASCI/CSIO.
TXCA
78
64
Input/
Output
Transmit clock for the ASCI/CSIO: This line is used
to input/output the ASCI/CSIO transmit clock.
Two programmable modes:
Input:
• External transmit clock
Output • Transmit clock from the on-chip baud rate generator
RXCA
77
63
Input/
Receive clock for the ASCI/CSIO: This line is
Output
used to input/output the ASCI/CSIO receive clock.
Two programmable modes:
Input:
• External receive clock
•
Output • Receive clock from the on-chip baud rate generator
~HITACHI
584
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
Pin
Number
Input!
Symbol
CP-84
FP-80A Output
Remarks
RTSA
72
58
Request to send for ASCI/CSIO: Indicates that the
Output
HD64180S has data to be output to a communications
device such as a modem. The output level can be
automatically controlled by the ASCI/CSIO operation
(auto-enable function). This line can also be used as a
general purpose output port.
DCDA
73
59
Input
Data carrier detect for ASCI/CSIO: Indicates that a
communications device such as a modem is receiving
valid signals from the communications line.
ASCI/CSIO receive operation can be automatically
controlled by this input (auto-enable function). This
line can also be used as a general purpose input port.
CTSA
61
75
Input
Clear to send for ASCI/CSIO: Indicates that a
communications device such as modem is ready to send
data to the communications line. ASCI/CSIO transmit
operation can be controlled automatically by this input
(auto-enable function). This line can also be used as a
general purpose input port.
• Timer Lines
Pin
l'iumber
Input/
Symbol
CP-S4
FP-SOA Output
TINo
5
75
Remarks
Timer inputs for channels 0 and 1: Event counter
Input
signals are input via these lines.
TINI
6
76
Input
TOUTo
7
77
Output
TOUTl
8
78
Output
Timer outputs for channels 0 and 1: Timer signals are
output via these lines.
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
585
HD64180S
• Absolute Maximum Ratings
Item
Symbol
Rating
Unit
Supply voltage
Vee
-0.3 to +7.0
V
Input voltage
Yin
-0.3 to Vcc + 0.3
Operating temperature
Topr
-20 to +75
V
'C
Storage temperature
Tstg
-55 to +150
'C
Caution: Permanent damage to the HD64180S may result if it is subjected to conditions that
exceed the absolute maximum ratings. To assure normal operation, the following conditions should
be satisfied:
Vss ~ Yin
~
Vee
• Electrical Characteristics
• DC Characteristics (Vcc=5V ± 10%, Vss=OV, Ta=-20 to +75°C unless otherwise specified)
Item
Symbol
min
Input high level voltage at
V IHI
typ
max
Unit
Vcc-O.6
Vcc+O.3
V
VIH2
2.2
Vcc+O.3
V
Vn..l
-0.3
0.6
V
Vn..2
-0.3
0.8
V
Conditions
RESET, EXTAL, and NMI
Input high level voltage at
lines other than RESET,
EXTAL, and NMI
Input low level voltage at
RESET, EXTAL, and NMI
Input low level voltage at
lines other than RESET,
EXTAL, and NMI
Output high level voltage
at all output lines
Output low level voltage
VOH
2.4
V
Vcc-1.2
0.45
VOL
V
IOH = -200 IlA
IOH=-20 IlA
IOL=2.2mA
at all output lines
~HITACHI
586
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
DC Characteristics (cont.) (Vcc=5V:!: 10%, Vss=OV, Ta=-20 to +75°C unless otherwise specified)
Item
Symbol
Input leakage current
IlL
typ
min
max
Unit
1.0
JlA
Yin =0.5 to
Vcc-O.5
at all input lines other than
XTAL and EXTAL
Three state leakage current
Conditions
ITL
1.0
V in =0.5 to
JlA
Vcc-O.5
Current dissipation·
96
60
120
Current dissipation·
6
12
(system stop mode)
8
16
(normal operation)
Icc
rnA
f=8MHz
f= 10 MHz
f=6MHz
rnA
f=8MHz
pF
Vin=OV,f=1
20
10
Pin capacitance
f=6MHz
72
36
48
f= 10 MHz
20
Cp
MHz, Ta =25"C
• Input signal
RESET, EXTAL, NMI: VIHm,n = Vc;c..(J.6V, VILma, =
O.6V the others: VIHm,n = Vcc-1.OV, VILmax = O.8V
• AC Characteristics (Vcc=5V:!: 10%, Vss=OV, Ta=-20 to +75°C unless otherwise specified)
Note that the specifications related to C~ pin is specified only in CP-84 package version.
Bus Timing
Table .3-3. Bus Timing
Item
Symbol
Oock cycle time
be
Oock high-level
tcHw
HD64180SCP6 HD64180SCPS HD64180SCPI0
max min typ max min typ max Unit Timing
min typ
162
2000 125
65
2000 100
50
38
-
2000 ns
-
ns
10, 11,
12, and 13.
Eulsewidth
Oock low-level
See figures
tCLw
65
50
38
-
ns
pulse width
Oock fall time
tcf
15
15
12 ns
Oock rise time
ta-
15
15
12
ns
Address delay
tAD
90
80
55
ns
time
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300
587
HD64180S
Bus Timing (cont.)
Item
Address set-up
time (vis-a-vis
falling edge of
ME,IOE,or
CS2-CSO)
ME delay time 1
RD delay time 1
LIR delay time 1
Address hold
time (vis-a-vis
rising edge of
ME,IOE,RD,
WRor
CS2-CSO)
ME delay time 2
RD dela~ time 2
RD delay time 3
LIR delay time 2
Data read set-up
time
Data read hold
time*
ST delay time 1
ST delay time 2
WAIT set-up
time
Symbol
lAs
HD64180SCP6 HD64180SCPS HD64180SCPI0
min typ max min typ max min typ max Unit Timing
20
15
- os See figures
15
10, 11,
12, and 13.
60
60
80
tMEo!
IRDDl
lID!
tAlI
20
35
IRoo2
60
60
1RDD3
65
IID2
80
tMED2
50
50
70
10
50 os
50
50
60
70
50 os
toRS
40
30
30
toRI!
0
0
0
tsm!
90
tsTo2
90
tws
40
70
70
40
50 os
os
55 os
- os
50
30
55 os
55 os
- os
-
os
60 os
60 os
- os
... Defmed against the flfSt signal to go high level of ME, RD and CS2 - CSo
~HITACHI
588
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
Bus Timing (cont.)
HD64180SCP6 HD64180SCPS HD6418OSCPI0
Item
Symbol
WAIT hold time
Write data
floating delay
time
WR delay time 1
Write data delay
time
Write data set-up
time (vis-a-vis
falling edge of
WR)
WR delay time 2
WR pulse width
Write data hold
time (vis-a-vis
rising edge of
WR)
IOE delal:: time 1
IOE delal:: time 2
IOE delay time
3 (from falling
twH
min typ
max min typ
max min typ max Unit Timing
40
40
95
twoz
30
70
- ns
60 ns
See figures
10, 11,
12, and 13.
twRDl
65
twDD
90
twDs
twDH
-
130
15
60
60
nODI
nOD2
nOD3
60
80
170
40
340
-
50 ns
60 ns
15
20
40
twRm
twRP
60
80
250
-
110
10
-
ns
55
ns
-
ns
ns
-
50
50
- 200
50 ns
50 ns
- ns
60
55
ed~e
ofLIR)
IOE delal:: time 4
!NT set-up time
(vis-a-vis
falling edge of
tINrs
40
40
30
-
ns
ns
IINrn
40
40
30
-
ns
65
nOO4
fII)
!NT hold time
(vis-a-vis
falling edge of
1'1)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
589
HD64180S
Bus Timing (cont.)
Item
Symbol
NMI pulse width INM1w
BUSREQ set-up
mas
HD64180SCP6 HD64180SCPS HD64l8OSCPI0
min typ max min typ max min typ max Unit Timing
-
120
40
100
80
-
ns
See figures
40
30
-
us
10, 11,
time (vis-a-vis
12, and 13.
falling edge of
S'l)
BUSREQhold
tBRH
40
40
-
30
-
ns
time (vis-a-vis
falling edge of
S'l)
BUSACK delay
tBAD!
95
70
60 ns
tBAD2
95
70
60 ns
tBzo
125
90
80
ns
70
-
ns
80
-
ns
time 1
BUSACK delay
time 2
Bus floating
dela~
time
ME high-level
tMEwH
110
90
tMEwL
125
- 100
-
pulse width
ME low-level
pulse width
REF delay time 1 tRFol
REF delay time 2 tRFD2
HALT delay
80
tBADl
90
90
90
80
60 ns
60 ns
50 ns
tHAD2
90
80
50
ns
80
time 1
HALT delay
time 2
RESET set-up
tREs
120
- 100
80
-
ns
tRBH
80
80
80
-
ns
time
RESET hold
time
Oscillator
tose
-
20
20
40
ms
stabilize time
~HITACHI
590
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
Bus Timing (cont.)
Symbol
Item
RESET rise time tRr
RESET fall time IRf
CS delay time 1 tcSDl
CS delay time 2 tcsnz
HD64180SCP6 HD64180SCPS HD64180SCPI0
min tyP max min typ max min tyP max
50
50
50
50
50
50
50
60
55
60
55
50
Unit
ms
ms
ns
ns
Timing
See figures
10, 11,
12, and 13.
MSCI Timing
Symbol
Item
TXCM cycle time trcYCM
(lXCM input)
TXCM rise time trcrM
(lXCM input)
TXCM fall time traM
(lXCM input)
TXCM high-level trCHWM
pulse width
(lXCM input)
TXCM low-level trcLWM
pulse width
(lXCM input)
1XDM delay time tmDlM
(IXCM input)
1XDM delay tim: tmDlM
(IXCMootput)
RXCM cycle time IRCYCM
*
HD64180SCP6 HD64180SCPS HD64180SCPI0
min t~~ max min t~~ max min t~~ max Unit Timing
1.4* 1.4* 1.4* - tcYc
See figures
14, 15,
15
20
10 ns
16, 17,
18, 19,
15
20
10 ns
20,21
and 22.
0.55 0.55 0.55 - tcYc
0.55 -
-
0.55 -
0.55 -
-
130
1.4* -
80
100
80
65
1.4* -
-
tcYc
ns
50 ns
1.4* -
-
tcYc
In asynchronous mode, loop mode, trcvCM, 1RCVCM =2.5 tcvc (min).
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
591
HD64180S
MSCI Timing (cont.) (Vcc=5V ± 10%, Vss=OV, Ta=-20 to +75°C unless otherwise specified)
HD64180SCP6 HD64180SCPS HD64180SCPI0
max min typ max Unit Timing
15
10 os
See figures
15
10 os
14, IS,
0.55 - tCYc 16, 17,
18, 19,
0.55 - tCYc 20,21
and 22.
30
- os
Item
Symbol min typ max min typ
RXCM rise time tRCIM
20
RXCM fall time tRaM
20
RXCM high-level tRCHWM
0.55 0.55 pulse width
RXCM low-level tRCLWM
0.55 0.55 pulse width
RXDM-RXCM
IRDstM
50
40
set-uptime
(RXCM input)
RXCM-RXDM 1RDHIM
40
30
hold time (RXCM
input)
RXDM-RXCM 1RDs2M
130
- 100
set-uptime
(RXCM output)
RXCM-RXDM tRDH2M
40
30
hold time (RXCM
output)
ADPLL operating 1PLcYM
120
80
clock cycle time
ADPLL operating tI>L:M
15
clock rise time
15
ADPLL operating IPuM
clock fall time
ADPLL operating iPuIwM
25
15
clock high-level
pulse width
15
ADPLL operating IPLLWM
25
clock low-level
pulse width
tBGDM
150
~BRG* output
delay time
20
-
os
80
-
os
20
-
ns
57
-
os
10
8 ns
10
8 ns
120
10
-
ns
10
-
os
95
os
.. fBRa ~ fl'l (fBRG is the baud rate generator output frequency; fl'l is the CPU operating clock frequency) .
•
592
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
MSCI Timing (cont.) (Vee=5V ± 10%, Vss =OV, Ta=-20 to + 75°C unless otherwise specified)
Item
TXCMlRXCM
oU!Eut rise time
TXCMlRXCM
oU!Eut fall time
RXCM-SYNC
S!!!,!bol
tBoMr
tBGMr
HD64180SCP6 HD64180SCPS HD64180SCPI0
min t;,]! max min tm max min tm max Unit Timing
50
30 ns
40
See figures
14, 15,
30 ns
50
40 16, 17,
18, 19,
tsYSU
2.5
-
-
2.5
-
-
tcYe
2.5 -
2.5
-
-
tcYe
2.5
set-u~time
RXCM-SYNC
tsYlID
hold time
crSM high-level tcrsHwM
2.5
2.0
-
2.0
-
2.0 -
-
tcYe
2.0
-
2.0 -
2.0 -
-
tcYe
2.0
-
2.0 -
2.0
-
-
tcYe
2.0
-
2.0 -
2.0 -
-
tcYe
-
70 ns
20,21
and 22.
~ulsewidth
crSM low-level tcTSJ..WM
pulse width
DCDM high-level tDcoHWM
pulse width
DCDM low-level tDcoLWM
pulse width
f<}-RTSMdelay
tRTSDM
100
85
time
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
593
HD64180S
ASCI/CSIO Timing (Vcc=5V ± 10%, Vss=OV, Ta=-20 to +75°C unless otherwise specified)
Item
TXCAinput
Symbol
1:rCYe
HD64180SCP6 HD64180SCPS HD64180SCPlO
min typ max min typ max min typ max Unit Timing
2.5
2.5
2.5
-
tcYe
0.55 -
0.55 -
-
tcYe
cycle time
TXCAinput
See figures
23,24,
trcaw
0.55
-
high-level pulse
25,26,
27,28
width
and 29.
TXCAinput
trcLw
0.55
-
0.55 -
0.55 -
-
tcYe
ns
low-level pulse
width
TXCA input rise trcr
30
20
10
30
20
10 ns
time
TXCA input fall
trcr
time
TXDAdelay
troDI
1.5
3.0 1.5
3.0 1.5
3.0 tcYe
time 1
TXDAdelay
50
trooz
30 ns
40
time 2
RXCAinput
tRcye
2.5
tRCIIW
0.55
tRCLW
0.55
2.5
2.5
-
tcYe
-
0.55 -
0.55 -
-
tcYe
-
0.55 -
0.55 -
-
tcYe
cycle time
RXCAinput
high-level pulse
width
RXCAinput
low-level pulse
width
RXCA input rise tRer
30
20
10
ns
30
20
10
ns
time
RXCA input fall
tRer
time
$HITACHI
594
Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
ASCI/CSIO Timing (cont.) (Vcc=5V ± 10%, Vss=OV, Ta=-20 to +75°C unless otherwise specified)
HD64180SCP6
Item
RXDA set-up
Snnbol
1RDs1
min
50
ty~
HD64180SCPS
max min ty~
40
HD64180SCPI0
max min typ max Unit Timing
30
- ns See figures
time 1
23,24,
RXDA hold time tRmn
1
-
20
30
40
ns
27,28
IRDS2
130
- 100
80
-
ns
RXDA hold time IRDH2
2
40
30
20
-
ns
RXDA set-up
25,26,
and 29.
time 2
~-BRG
output
tBGDA
80
70
ro
ns
1BaAr
50
40
30
ns
IBGM
50
40
30
ns
delay time
TXCA/RXCA
output rise time
TXCA/RXCA
oU!Eut fall time
crSA high-level tcrsHw
2.0
-
2.0 -
2.0 -
-
tCYc
Eulse width
low-level
tcrsLw
2.0 -
2.0 -
2.0
-
-
tCYc
too>Hw
2.0
-
2.0 -
2.0
-
-
tCYc
DCDA low-level 1Da>Lw
Eulse width
2.0
-
2.0
2.0 -
-
tCYc
crsx
:Qulse width
DCDAhighlevel pulse width
RTSAdelay
tRTSD
-
100
85
70 ns
time
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
595
HD64180S
DMAC Timing (Vcc=5V ± 10%, Vss=OV, Ta=-20 to +75°C unless otherwise specified)
Item
DREQset-up
time
DREQ hold time
TEND delay
time 1
TEND delay
time 2
ST delax time 1
ST delax time 2
1DRBQs
HD64180SCP6 HD64180SCPS HD6418OSCPI0
min typ max min typ max min typ max Unit Timing
40
40
30
See figure
- os
\DRIlQH
40
SI!!!bol
30.
30
-
trEol
70
60
os
50 os
trED2
70
60
50 os
tm>1
90
90
70
70
60 os
60 os
1m>2
40
Timer Timing (Vcc=5V ± 10%, Vss=OV, Th=-20 to +75°C unless otherwise specified)
Item
Symbol
Timer input
1PwT
pulse width
Timer input set- 1PDsu
up time
Timer input hold fl>DH
time
Timer output
troD
delay time
HD64180SCP6 HD64180SCPS HD6418OSCPI0
min typ max min typ max min typ max Unit Timing
20 2.0 2.0 - tcYc See figure
31.
40
40
30
-
os
40
40
30
-
os
100
•
596
85
70 os
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
EXTAL Input Clock Signal Timing (Vcc=5V ± 10%, Vss=OV, Ta=-20 to +75°C unless
otherwise specified)
HD64180SCP6 HD64180SCPS HD64180SCPI0
Item
External clock
Symbol
min typ max min typ
81
1000 62
max min typ max Unit Timing
1000 50
1000 ns
See figure
IJ:.cHw
20
15
10
-
ns
IEcLw
20
15
10
-
ns
cycle time
External clock
32.
high-level pulse
width
External clock
low-level pulse
width
External clock
25
25
15
ns
25
25
15
ns
fall time
External clock
rise time
Miscellaneous
Rise and Fall Times of Input Signals with No Characteristics Specified
(Vee = 5V ± 10%, vss
= OV, Ta =-20 to +75°C unless otherwise specified)
HD64180SCP6 HD64180SCPS HD6418OSCPI0
Item
Input line rise
Symbol
min typ
max min typ
max min typ max Unit Timing
100
100
100 ns
100
100
100 ns
time (no
See figure
33.
characteristics
specified)
Input line fall
time (no
characteristics
specified)
$
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
597
HQ64180S
Bus Timing
,J bF'Lr
nJ'>Jf\J\f >Jr\-
>-
I" f+-.
::=~
c
~~ 10• Ii
IO'1~ I07~
10.
WAIT
1.'1= I"
-,1. s
""~If
HE
t:~o,
10E
~H
f..I
I. s
If
M \l~
I
I
I,oo,~ ~
tROD;
t.I
Jl
'x
RD
tfOOC
t ROO
t:OO'
II
'x film,
I
1
I
!
~
I
I
Fx1tWRD
WR
1
I ••
l+-
+
t WRP
1\
i--
V
t"Ut 1p2
i
t I. 0 2
tLO!~
~
I
H
I
I
~STr
I
ST
t:rOt
Do - 0, (I HI
~.l
~;J
~J rnp
to It H
lr- ~
~
~I'-
t-t
~
tw~os
00 -0, (DUn
I
RESET' ,
~
-I..
1--1.,
hI ..
.oj
t D It"
tCSD2
I ••
~
>--
t RES -1
I".
IYnCSylf. 6V
II
f+---< t WOH
.'k
t1tE5~
I
I
I
l-
M
1.--: I<-
I+- L.,
t Iti M
\VOcS9·6V
it. ,
k--
1--1.tcso 1
*1
Output buffer inactivation timing.
*2
A low-level signal should be input to the RESET pin such that it is sampled at low level for at least six successive iii
clock falling edges. After the reset mode is entered, it may require up to 10 clock cycles before all of the output lines
are set to their initialize conditions.
See" Reset Mode," for details.
Figure 10. Bus Timing (1)
~HITACHI
5913
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
m"
m"
Do-D,(IN)"
A.-A ..
D. - D,
HE,~,~,~--------------~
., During INTo acknowledge cycle
·2 During refresh cycle
·3
Output buffer inactivation timing
Figure 11. Bus Timing (2)
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
599
HD64180S
Second opcode fetch cycle
for SLP instruction
T,
T.
Opcode fetch or interrupt
acknowledge cycle
Sleep or system stop mode
T.
Ts
Ts
Ts
T,
T.
I NT •• I NT ,.
INT.
00
O. 6V
tNMIW
tAD
tAD
A.-A,.
r
t HA ••
tHAD1
Ll
HALT
ME.RO.m
II
L /
\ \
Figure 12. Bus Timing (3) (sleep or system stop mode)
--5.5V
I
Vee
.:Jf- 4. 5V
more than maximum value of tose
----111-1_ _ _ _ _ _ _ _il-_ _yO . 6V
Figure 13. Bus Timing (4)
•
600
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
MSClTiming
(1) Transmit timing (TXCM input)
t TcrM
TXCM
(input)
TXOM
(output)
* Defines in the FM type codes.
Figure 14. Transmit Timing (TXCM input)
(2) Transmit timing (TXCM output)
TXCM'1
~
(output)
J
jo----o
I<---t
tTOD2M •2
tTOD2M
TXOM
(output)
)
)
*1 For details ofthe TXCM waveform, see figure 13-10.
*2 Defines in the FM type codes.
Figure 15. Transmit Timing (TXCM output)
(3) Receive Timing (RXCM input)
-0
RHCM
(input)
~crM
--t
tRCLWM
tRCHWM
tRCYCM
tRos1M
<-4
RHOM
(input)
F-
==>
t. OH1 ..
K
Figure 16. Receive Timing (RXCM input)
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
601
HD64180S
(4) Receive Timing (RXCM output)
RKCH"
(output)
tROS2M
RHOH
(input)
tRDH2M
K
)
"For details of the RXCA waveform, see figure 19.
Figure 17. Receive Timing (RXCM output)
(5) ADPLL Operating Clock •...iming
J
y-
RKCH
(input)
1'------'1
Figure 18. ADPLL Operating Clock Timing
(6) Baud Rate Generator Output Timing
t aGOM
t. GDM
TKCH/RKCH
(output)
Figure 19. Baud Rate Generator Output Timing (fBRG=f
I+-t TCf
-<
- t Tcr
'--
).
TXDA
fo---.
tTDDI
Figure 23. Transmit Timing (TXCA input)
(2) Transmit Timing (TXCA output)
TXCA'
(output)
~
I'-_ _ _~
tTDD2
..........
TXDA
----~)~-----------------
• For details of the TXCA waveform, see figure 3-18.
Figure 24. Transmit Timing (TXCA output)
(3) Receive Timing (RXCA input)
RXCA
(input)
RXDA
Figure 25. Receive Timing (RXCA input)
~HITACHI
604
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
(4) Receive Timing (RXCA output)
RXCA"
(output)
RXDA
'For details of the RXCA waveform, see figure 27.
Figure 26. Receive Timing (RXCA output)
(5) Baud Rate Generator Timing
t aGOA
TXCA/RXCA
(output)
tSGAf
Figure 27. Baud Rate Generator Timing
(6) CTSA and DCDA Timing
CTSA
DCDA
-i
-i
tCTSLW
tOCOLW
U
tCTSHW
U
tOCDHW
~
~
Figure 28. CTSA and DCDA Timing
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
605
HD64180S
(7) RTSA Timing
1/1
\
~D
)(
RTSA
Figure 29. RTSA Timing
•
606
HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589·8300
HD64180S
DMACTiming
DMA readlwrite cycle *3
DREQo. ,
(level sensitive
mode)
DREQo. ,
(edge sensitive
mode)
ST
·1
Defines the rising edge of the clock immediately preceding Ta In single-block transfer mode (dual address type) in
write cycle
·2 Defines the rising adge of the clock
·s Defines a read cycle in single-block transfer mode (dual address type)
·4
Defines the clock alter Ts of write cycle In single-block transfer mode (dual address type)
·5 Defines the rising edge of the clock at the beginning of a DMA cycle
*8
Defines the rising edge of the clock at the beginning of a CPU cycle
Note: The timing for ME. JOE. RD. WR. 00-07. and Ao-A19 during readlwrite operations is the same during CPU
operation.
Figure 30. DMAC Timing
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819. (415) 589-8300
607
HD64180S
loner TIming
TI No. ,
TOUT D.
,
Figure 31. Timer Timing
EXTAL Input Clock Signal Timing
t ECye
tecHW
i r - - - - - - - , I Vc c-D. 6V
D. 6V
tEe.
Figure 32. EXTAL Input Clock Signal Timing
•
608
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
HD64180S
Miscellaneous
(1) Rise and Fall Times of Input Signals with No Characteristics Specified
-
--
t ,f
t'r
,---
--10-
Figure 33. Rise and Fall Times of Input Signals with No Characteristics Specified
(2) Reference Levels (when not otherwise specified)
=:x.i·.&;:U_---'~:o.l:
.
I~DC
Z.4V~
=:XZ.4'
O. BY
O. BY
Output signal reference level
Input signal reference level
Figure 34. Reference Levels
(3) Bus Timing Load (TIL load)
Vee
RL
Test point
Diode·
c
rRL=1.6KQ
l
• IS2074H or equivalent.
1
c = 90pF
I
R = 12KQ
J
Figure 35. Bus Timing Load
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
609
HD64180S
• Instruction Set
~
the instruction set, the following conventions are used:
(1) Register specification
g, g' represents a 8-bit register, while ww, xx, YY, or zz represents a pair of 8-bit registers. The
corresponding registers are listed below.
s.s' Resister
000
001
010
011
100
101
111
B
C
D
E
ww Resister
xx'
Resister
n:
Resister
zz
Resister
00
01
10
11
00
01
10
11
BC
DE
BC
DE
IY
00
01
10
DE
IX
00
01
10
SP
11
SP
11
AF
BC
DE
HL
SP
BC
HL
H
L
A
Note: ww, xx, yy, or xx plus H or L (eg, wwH, IXL) indicates the high or low order byte of a 16-bit
register.
(2) Bit specification.
'b' indicates the bit number of the bit operand in a bit manipulation instruction. The
corresponding bits are listed below.
B
Bit
000
0
1
001
010
011
100
101
110
111
2
3
4
5
6
7
•
610
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
(3) Condition specification
'f indicates the condition for executing an instruction, based on the arithmetic result. The
corresponding conditions are listed below.
f
Condition
000
NZ
non zero
001
010
011
100
101
110
111
Z
zero
NC
non c!!!!l:
C
c!!!!l:
PO
Earit~odd
PE
P
Eari~even
M
sian Elus
sian minus
(4) Restart address
'v' indicates the restart address of a restart instruction. The corresponding addresses are listed
below.
v
Address
000
OOH
OSH
IOH
ISH
20H
28H
30H
38H
001
010
011
100
101
110
111
(5) Flag
Flag changes are indicated by the following symbols:
.: The flag is not changed by the instruction.
X: Flag change by this instruction is undefined.
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
611
HD64180S
t:
The flag is changed according to the arithmetic result of the instruction.
S: The flag is set to 1 by the instruction.
R: The flag is reset to 0 by the instruction.
P: The flag is changed as a parity flag by the instruction.
V: The flag is changed as an overflow flag by the instruction.
(6) Others
Indicates the memory at the address indicated in parentheses.
( )1:
Indicates the I/O at the address indicated in parentheses.
m or n: g-bit value
mn:
16-bit value
Subscript r indicates a g-bit register.
r:
R:
Subscript R indicates a 16-bit register.
b·( )M: Indicates the memory bit specified by b at the address indicated in parentheses.
Indicates the register bit specified by b in the register specified by gr.
b·gr:
dorj: Signed g-bit displacement
Source addressing mode
S:
Destination addressing mode
D:
AND
OR
+:
EB:
Exclusive OR
()M:
•
612
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300
HD64180S
• Data Manipulation Instructions
(1) Arithmetic and logic instructions (8bits)
OperatlDII
!1liiie
ADD
MNEMONICS
8ytea
Stateo
OperatIon
IMMEl EXT IND REG REGI IMP REI.
ADDA.I
ADDA,\IIL)
ADDA.m
10000,
10000110
II 000 110
(
ADD A,UX +d)
ADD A,UY +d)
ADC
AddreooI",
OP code
ADCA.I
ADC A,(HL)
ADCA.m
AOC A.nX Idl
.
7
FI..
4 2
Z H PIV
I I V
I I V
I I V
6
1
N
R
R
R
C
I
I
I
0
2
4
6
6
Ar+ ....Ar
Art (HL).~Ar
Art ..~Ar
S
I
I
I
D
3
14
Ar
10101 g
10101110
11 101110
( m )
11 011 101
10 101 110
( d )
11111101
10 101 110
( d )
Operation
Bytes
'States
2
17
wwHrxwwLr-owwI
S/O
2
6
0
0
0
1
4
I
S
S
OP code
INO
REG REGI IMP
S/O
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
REL
A~(HL)."Ar
I
--
~HITACHI
614
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
(2) Rotate/shift instructions
Operation
name
Rotate
and
Shilt
Data
MNEMONICS
Addressing
OPcode
IMME
RLA
RLI
RL !HLI
RL (lX+dl
RL (lY+d)
RLCA
RLCI
RLC (HL)
RLC UX+d)
RLC (lY+d)
RLD
RRA
RRI
RR (HL)
RR UX+d)
RR (lY+d)
RReA
RRCg
RRe (HL)
RRe UX+d)
RRe UHd)
00 010 111
11 001 011
00 010 1
11 001 011
00 010 110
11 011 101
11 001 011
( d )
00 010 110
11 111101
11 001 011
( d )
00 DID 110
00 000 111
11 001 011
000001
II 001 011
00 000 110
II 011 101
II 001 011
( d )
00 000 110
II 111101
II 001 011
( d )
00 000 110
II 101 101
01 101 111
00 011 \11
II 001 011
00 011 g
II 001 011
00 011110
11 011 101
II 001 011
( d )
00 011 110
II 111101
11 001 011
( d )
00 011 110
00 001 111
II 001 011
00 001 1
II 001 011
00 001 110
II 011 101
II 001 011
( d )
00 001 110
11111 101
11 001 011
( d )
00 001 110
EXT
INO
REG
REGI
Bytes
IMP
REL
SID
SID
I
2
S
6
Z
1
1
FIlii
4 Z
H P/V
R
R P
7
Operation
States
3
7
C .,...--110
1 0
N e
R 1
R 1
2
13
1
I
R
P
R
1
SID
4
19
1
1
R
P
R
1
SID
4
19
1
1
R
P R
1
1
2
3
7
1
R
R
R
I
P R
1
1
2
13
I
I
R
P
R
I
SID
4
19
1
1
R
P
R
1
SID
4
19
I
1
R
P R
1
1
1
R
P
1
1
R
R
P R
1
1
SID
SID
SID
S/O
oJtllllllQJ
C"J~
...!!.
SID
2
16
&11 ' - - - - - '
..
till
As
(HLlN
~IIIIIIIf-O-I
.,--"" e
R
R
I
2
3
7
2
13
1
1
R
P
R
1
SID
4
19
1
1
R
P
R
1
SID
4
19
1
1
R
P
R
I
1
2
3
7
1
1
R
R
P
R
R
1
1
SID
SID
SID
SID
SID
'1, ---.J-4i
2
13
1
1
R
P
R
1
SID
4
19
I
1
R
P R
1
SID
4
19
1
1
R
P R
I
SID
(Contmued)
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
615
HD64180S
Operation
name
Rotate
aad
Shift
Data
MNEMONICS
Addressing
OP code
IMME
RRD
SLAg
SLA (Hl)
EXT
IND
11101101
01 100 1I1
11 001 011
00 100 g
11 001 011
REG REGI IMP
SID
Bytes
States
2
16
REt
=N
Operation
..
..
iHUt.
Flag
7
S
1
6 4 2 1 0
Z H PlY N C
I
R
P
R
1
1
R
P
R
1
1
1
R
P
R
1
2
7
2
13
S/O
4
19
I
I
K
P
R
I
SID
•
19
I
I
R
P
R
1
2
7
I
I
R
P
R
1
2
13
1
1
R
P
R
1
SID
4
19
1
1
R
P
R
1
SID
t
19
1
1
R
P
R
1
2
7
1
1
R
P
R
1
2
3
1
I
R
P
R
1
SID
4
19
1
1
R
P
R
1
SID
4
19
1
1
R
P
R
1
SID
SID
..7
c ..
110
UO IIMI 1111
SLA IIXtd)
SlA (IYtd)
SRAg
SRA (Hl)
SRA (lXtd)
SRA (IYtd)
SRlg
SRL (Hl)
SRl (IXtd)
SRL (IYtd)
11 011101
11 001 011
( d >
00 100 110
11 111101
11 001 011
( d >
00 100 110
11 001 011
00 101 g
11 001 011
00 101110
11 011101
11 001 011
( d >
00 101 110
11111101
11 001 011
( d >
00 101110
11 001 011
00 III g
11 001 011
00 111110
11 011 101
11 001 011
( d >
00 1I1 110
11 1I1101
11 001 011
( d >
00 111110
SID
SID
SID
SID
1:(1111111
HJ
..
.. c
..
·-/1111111..HJc
I
.HITACHI
616
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
(3) Bit manipulation instructions
Operation
DIIIIO
BIt Set
MNEMONICS
IIOII!I EXT
SETb,i
SETb,(III.)
SETb,UX+dl
SETb,(lY+dl
BIt Reoet
RESb,i
RESb,(HL)
RESb,UX+dl
RES b,(IY+dl
Bit Test
AIIcI...mc
0' .....
BlTb,i
BlTb,(HL)
BlTb,(IX+d)
BIT b,UY+dl
UOIIOll
IU
11101 Oll
lib 110
11011101
11101011
( d )
lib III
l1111ltl
111111 011
( d )
lib 110
11011011
lib
11101011
10 b 110
11111101
11 GOI 011
SID
2
SID
7
l-o\1'~
2
13
SID
4
It
1-o\Io(lX+dl.
SID
4
I.
1-+(IY+d).
2
7
""".~
2
13
0-+(111.).
SID
4
It
0-+(1X+d).
SID
4
It
"""·(lY+dl.
2
,
SID
SID
S
PIq
2
Z H
S
• • 'IV
7
X
I
S
f.'Iiii:l;~.
b·.....
1 0
N C
X R
2
,
X
1
5 X R
5
4
15
b·UX+dl~.
X
I
5 X R
5
4
15
bo(lY+d).~
X
I
5 X R
•
( d )
O1b 110
11 III 101
11101011
( d )
01 b 110
0pendI0n
1-+(111.).
•
11101011
II b
11101011
01 b 110
11 011111
11101011
SIateo
IND RIG RIIIlI IMP IlL
•
( d )
10 b no
l1111ltl
111111 Oil
( d )
lOb 110
BrIM
5
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
617
HD64180S
(4) Arithmetic instructions (16 bits)
......
Operation
ADD
MNEMONICS
Addreosing
OP code
IIIMEt EXT
ADDH!._
ADDIX,xx
ADDIY;yy
110_11101
II 011101
110 ",,11101
11111101
110 yy11101
IND
REG REGI IMP
S
D
S
D
D
2
10
HL,+ww.+ ....HL,
1
2
4
7
..,-1"'••,
SID
SID
2
7
ly.-1 ....1Y.
1
4
SID
2
7
ww.+ l-ww.
1X..+I"'IX.
SID
2
7
IY.+I-IY.
IJ
2
10
ilL,- w... • ,··IIL.
DI!C ww
110_1011
11011101
110 101 011
11111101
110 101 011
SID
IIOWWOOII
II 011101
110 100 011
11111101
110 100 011
SID
11101101
01 WWOOIO
S
SOC
sac IIL...w
•
618
X
lY.+yy....IY.
DEC
INCIY
HL,+...,.~HL,
IX,+ ...~IX.
10
S
INC...,
INC IX
7
10
REI.
2
11101101
01_1010
INC
I
2
PI..
4 2
Z H P/V
X
X
Operation
D
ADC HJ.ww
DEC1Y
Stales
S
ADC
DEC IX
Byles
7
S
6
I 0
N C
R I
R I
R
I
1
I
X V R
I
I
I
X V
I
1X.-l"'IX.
S
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589·8300
HD64180S
• Data Transfer Instructions
(1) 8-bit transfer instructions
Operation
name
MNEMONICS
Load
Ioblt Data
LDA.I
II!M!!
LDA.R
LDA.(lIC)
LDA.(IlE)
LDA.Im)
FIaa
AcId......lng
OP COJIe
11101101
01010 m
11101101
OIOl1m
00 001010
00 011 010
00 m 010
EXT
IND
Bytes
States
2
6
I,....Ar
SID
2
6
a.....Ar
D
D
D
I
I
(BCl.~Ar
3
6
6
12
SID
2
6
_Ir
SID
2
6
_Rr
S
S
S
1
I
3
7
Ar~(BCl.
7
13
Ar~(IIIDl.
1
I
2
I
g(~gr
6
6
m~
RliG RliGI IMP
SID
S
S
S
Operation
BEL
.,
..
•
7
S
I
6
Z
I
2 1 0
H P/v N C
R 1EF. R
I
I
R 1EF. R
(1lE).~Ar
(mo).~Ar
( n )
( m )
1.01'"
LDU
1.0 (Be)'"
1.0 (DEl'"
LD(Dltl.A
11101101
91000 1II
11101101
01001111
00 000 010
00 010 010
00 110 010
D
D
D
Ar~(IlE).
..
( n )
( m )
1.0 ....
LDg,(HL)
LDg,m
011 t
011 110
001 110
SID
D
D
S
S
(HL).~gr
( m )
LDg,(IX+d)
LDg,UY+d)
1.0 (HLl..,
11 011101
011 110
( d )
11 III 101
Oil 110
( d )
00 110 110
S
D
3
II
(1X+d)~
S
D
3
11
UY+d).~gr
2
9
m~(HL).
D
S
( m )
1.0 (lX+d)..,
1.0 UY+dl.m
1.0 (HL)"
1.0 UXtd)"
1.0 UY+d)"
11 011101
00 110 110
( d )
( m )
l1llll01
00 110 110
( d )
( m )
011101
11 011101
01110 I
( d )
11 III 101
01110 I
( d )
S
D
t
15
m~UXtd).
S
D
I
15
DI~UYtdl.
1
3
7
15
r(HL).
3
15
rUYtd).
D
S
S
D
S
D
gr~(lXtd).
*1 No interrupts are sampled at the end of LD A,I or LD A,R instruction .
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
619
HD64180S
(2) 16-bit transfer instructions
Operation
name
MNEMONICS
Addressing
OP code
IMME[ EXT
LD wW,mn
Load
16·bit Data
LD IX,mn
LDIY.mn
LUSI',IIL
LDSP,IX
LDSP,IY
LDww,{mn)
LD HL,(mn)
LD IX,(mn)
LD IY,(mn)
OOwwOOOI
( n )
( m )
II 011 101
00 100 001
( n )
( m )
II III 101
00 100 001
( n )
( m )
II III 001
II 011 101
II III 001
II III 101
II III 001
II 101 101
01 wwlOIl
( n )
( m )
00 101 010
( n )
( m )
II 011101
00 101 OlD
( n )
( m )
II III 101
00 101 010
(
LD (mn),ww
LD (mn),HL
LD (mnJ,IX
II
S
IND
REG
D
REGI
IMP
Bytes
States
Operation
3
9
mn..... ww.
REL
S
S
D
4
12
mn-IX.
S
D
4
12
mn .....IY.
S/I>
I
2
(
III... ·S!'.
SID
7
IX ...... SP.
SID
2
7
JY.-SP.
4
18
(mn+I).-wwHr
S
D
7
Flag
6 4 2 I 0
Z H P/V N C
(mn)N-wwLr
S
D
3
15
(lIIutl)",-lIr
S
D
4
IK
(mn+ 1I.-IXllr
(mn)~-Lr
(nul)II- IXLr
D
S
4
18
(mn+II.-IYHr
(mn) ..... IYLr
)
( m )
II 101 101
01 wwOOIl
( n )
( m )
00 100 010
( n )
( m )
II 011101
00 100 010
( n )
D
S
4
19
wwHr-(mn+l)/II
wwLr..... (mn)III
D
S
3
16
Hr-(mn+lI.
Lr-(mn).
D
5
4
19
IXHr-(mn+!l.
IXLr.... (mn)"
D
5
4
19
( m )
LD (mn),IY
II III 101
00 100 010
( n )
( m >
IYHr-(mn+!I.
IYLr-fmn) ..
.HITACHI
620
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
(3) Block transfer instructions
Operaticm
name
Block
Transfer
Search
Data
MNEMONICS
Addressing
OPcocle
IMMEl EXT
CPO
IND
REG
Bytes
REGI IMP
11101101
10101001
S
11101101
10 III 001
S
Operation
States
REt
S
2
12
Ar-(HL).
7
S
I
BC,-I~BC,
S'
2
14
12
BC,*O Ar*(HL).
BC,=O or Ar= (HL).
[A'-(HL ).
Q BC,-I~BC,
CPJ
11101101
10100 001
S
11101101
10110001
S
S
2
12
S
2
14
12
BC.*O Art:. (HLl ..
DC.=O or At= (ULl ..
Q
I
I
I
.
.
I
I
I
I
I
2
12
I
S
I
S
.,
I
S
rAr-(HL).
BC,-I~BC,
.,
A,=(HL), or BC.=O
SID
11101101
10 101 000
S
.,
111.. 11 ..... 111..
Ht,l.'al (J until
LDD
I
.,
I
HLo+I~HLo
CPJR
0
.,
.,
I
BC,-I~BC,
I
Z H P/V N C
I
HLo-I~HLo
a.peuQlllliI
Ar= (HL), or sc.=o
Ar-(HL).
Flag
4 Z
.,
HLo-I~HLo
CPOR
6
(HL).~(DE).
R
I
If
BC,-I~BC.
I)F4-I~DE,
HLo-l~HL,
lJ)DR
SID
11101101
10 III 000
2
[ (HL).~(DE).
14 (BC,*O)
12 (BC.=O)
R R R
oc.-I~BC,
Q
DE,-I~DE,
HL,-I~HL.
a.peuQ l1li11
BC,=O
LIlI
SID
11101101
10 100 000
2
12
(HL).~(DE).
R
.
I
R
BC,-I~BC,
DE.+I~DE.
HL,+l~HL.
LIlIR
11101101
10110000
SID
2
14 (BC,'O)
12 (BC,=O)
[ (HL).~(DE).
R R R
BC,-I~BC,
Q DE.+I~DE.
HLo+l~HL,
a.peu Q unb1
BC,=O
*2 P/V = 0 : DCa - I = 0
P/V=l: DCa-loOO
*3 Z =1 : Ar =(HL)y
Z =0 : AroO (HL)y
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
621
HD64180S
(4) Stack/exchange instructions
Operation
name
MNEMONICS
Addressing
OP cnde
IMMED EXT
PUSH
PUSH"
IND
II ,,0101
REG REGI
S
IMP
D
Bytes
States
I
II
7
S
Operation
REL
6
Z
Flag
2 1 0
H P/V N C
4
"Lr-ISP-21.
zzHr..... (SP-l)M
SP.-2-SP.
II 011 101
II 100 101
SID
PUSH IY
11111101
II 100 101
SID
2
14
POP ..
II ..0 001
S
I
9
PUSH IX
2
14
IXLr~ISP-21.
IXHr-ISP-I).
SP.-2-SP.
IYLr-ISP-21.
IYHr-ISP-I).
SP.-2.....SP.
POP
D
(SPt 1).-uHr
ISPI.~uLr
..
SP.+2~SP.
POP IX
11011101
II 100 001
SID
2
12
POP IY
II III 101
II 100 001
SID
2
12
(SPtl).-IXHr
ISPI.-IXLr
SP.t2~SP.
ISPt J).~IYHr
ISPI.~IYLr
SP.+2.....SP.
Exclml1gc
F.x AF.AF'
110 IMII 000
EX DE,HL
EXX
II 101 011
II on 001
S/ll
SID
SID
I
I
J
3
•
AF.·.. AF.'
DE.-HL.
BC,-BC'
DE,-DE'
EX ISPI.HL
II 100 011
SID
I
16
EX (SPI.IX
II on 101
II 100 011
II III 101
II 100011
SID
2
19
SID
2
19
Hr-(SPtl).
Lr-ISPI.
IXHr-(SPtl).
IXLr-(SPI.
IYHr- ISPt I).
IYLr-(SPI.
I
111.··111."
EX (SPI.IY
*4
POP AF writes the stack contents to the flag.
~HITACHI
622
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Program Control Instructions
Operation
name
Call
MNEMONICS
CALL mn
Addressmg
OP code
II 001 101
( n
(
,
m ,
IMMED EXT
D
IND
REG
REGI
IMP
Bytes
States
3
16
Operation
REL
7
S
6
Z
Flag
2 1 0
H P!V N C
4
PCHr-lSP-Ii.
PCLr-ISP-21.
mn-PCN
SP~-2-SP.
CALL f,mn
IIf
(
(
Jump
D1NZj
100
n
m
3
D
)
61f falsel contmue f IS false
16 If true) CALL mn f IS true
)
00 010 OIJII
00 101 OIJII
s
2
9
Operation
7
5
Flag
6 4 2 I II
Z H P/V N C
I
I
M
I'
M
I
I
R P
R
X
"!
X X
X
5
X
X
X
(Am),~Ar
m....A.-A,
A~A.-AII
IN R,(C)
11101101
01.
D
S
2
9
(1lC)'~RI'
R= 110 : Only lhe
IlOO
nags will
change,
C~A.-A,
Dr-At-All
INOg,(m)
11101101
OIlg 0IIIl
5
0
3
12
( m )
11101101
10101 010
INO
D
S
2
12
(OOm),~gr
g=1I0 Only lhe
nags will
change.
m-A.-A,
OO.... A.-A"
(1lC),~(HL).
.,
I
X
HL,-I~HL,
8r-I~Br
Cr~A.-A,
INOR
11101101
10 III 010
0
5
2
Br....A,-A"
[ (BC),~(HL).
14(BrOO)
12(Br=0) Q
.,
I
X
HL.-I~HL.
8r-I~Br
Repeal Q tmtil
8r=0
Cr~A.-A,
8r-tA,-A15
.,
'5
INI
11101101
10 100 010
D
S
2
12
(BC),~(HL).
X
I
X
X
5
X X
I
X
HL,+l~HL,
Br-l ..... Br
~A.-A,
.,
Dr-AI-All
INIR
11101101
10110010
0
5
2
14(8rOO)
12(8r=0)
[ (BC),~(HL).
Q
I
X
HL,+I~HL,
8r-I~Br
Repeat Q until
8r=0
~A.-A,
Dr-A.-A"
"5 Z = 1 .: Br - 1 = 0
Z=O
*6 N = 1
N=O
(Continued)
Br - 1 .. 0
MSB of Data = 1
MSB of Data = 0
$
624
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
Operation
MNEMONICS
name
OUTPUT
Addressing
OP code
IMME[ EXT
OW Im).A
OUT ICI.g
REG
REGI
11 010 011
< m >
IMP
S
States
I/O
D
2
10
S
D
2
10
S
D
3
13
D
2
14
001
11 101101
1101
( m >
11 101 101
101101011
IIOg
OTDM
Operation
7
6
S
Z
Flag
4 2 I
H P/V N
0
C
Ar-IAm) ,
m..... A.-AT
Ar-A.-A ll
11 101 101
OIg
OUTO Iml"
IND
Bytes
gr-IBCI,
Cr ..... A,-A,
Bf-A.-AII
gr-IOOm),
m-A.-A,
OO..... A,-A 1,
S
IHLI.-IOOCI,
HL,-I-HL,
C,-I-C,
Br-I-8,
.s
.7
1
I
P
R S
R
S
S
X
X
I
1
I
Cr-A.-AI
.s
OO-A.-A II
OTDMR
S
11 101 101
10011 011
D
2
1616,'01
1418,"01
[ IHLI.-IOOCI,
HI.,-I-HI.,
Q Cr-l-Cr
1
R
Sr-I-Sr
OTDR
S
11 101 101
10111011
S
11 101 lIll
10 100 011
OUTI
D
D
2
2
14IB"OI
121B,"01
12
Repeat Q until
B,"O
C,-A.-A,
OO..... A.-A 11
[ IHLI.-(BCI,
X
S
11 101101
10110011
D
2
1418,<01
12IB,"0)
1
X
Q HLl-I-HL.
B,-I-B,
Repeat Q until
B,"O
Cr-A.-A,
Sr-A.-A ll
IHL) .-IBCI,
HL,+I-HI.,
Sf-I-Sr
.s
'7
X
1
X X
X
S
X
X
I
I
S
P
Cr-A.-Al
Sf-A,-All
OTlR
.
[ IHL).-IBC),
Q I;lL,+i-HL,
B,-I-B,
Repeat Q until
B,"O
I
.
X
I
X
R
R
Cr-A.-A,
Ur .... A.-Au
TSTIOm
OTIM
11 101 101
01 110 1110
( m >
11 101 101
10 000 011
S
S
S
D
3
2
12
(OOC}I' m
14
Cr ..... A.-A T
OO-A.-A ll
IHL).-IOOC),
HL,+I-HI.,
C,+i-Cr
.,
1
*'1
1
P
1
1
R
S
R
S
"I
R
X
X
Sr-I-Bf
C,-A.-A,
OO-A.-A"
OTlMR
11 101 101
10010011
S
D
2
1616,,01
14IB,"O)
[ IHLi.-IOOCI,
Q HI.,+l-HI.,
C,+i-C,
B,-I-B,
Repeat Q until
8,"0
Cr-A.-A I
OO---A,-A "
OUTD
11 101 101
10 101 011
S
D
2
12
IHLI.-IBCl,
HL,-I-HI.,
Sf-l-Sr
Cr-Ao-AI
'7
X I
"
I
X
Br .....A.-AL,
*7 Z = 1
Z=O
*8 N = 1
N=O
Br - 1 '" 0
Br - 1 .. 0
MSB of Data = 1
MSB of Data = 0
~HITAOHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
625
HD64180S
• Special Control Instructions
Operation
name
MNEMONICS
Addressing
OP code
IMMED EXT
IND
REG
REGI
IMP
SID
States
I
4
Decimal
Adjust
Accumulator
REL
S
Special
Function
DAA
00 100 111
Carry
CCF
SCF
00 111 111
00 110 111
I
I
3
3
C~C
DI
EI
HALT
IMO
11 110011
11 111 011
01 110 110
11 101 101
01 000 110
11 101101
01 010 110
11 101 101
01 011 110
00 000 000
11101101
01 110110
I
I
1
2
3
3
3
6
O-+IEFh O.... IEFs
2
6
2
6
I
2
3
No operation
8
Sleep
Control
CPU
Control
IMI
1M2
NOP
SLP
7
{)pt!:ration
Bytes
I~
1~IEFh I~IEF.
CPU halted
Interrupt
mode 0
Interrupt
mode I
Interrupt
mode 2
I
..••
Flag
6 4 2 1 0
Z H PlY N C
I I P
I
R
R
R
R
• 9 No interrupts are sampled at the end of a DI or EI instruction .
•
626
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
I
S
HD64180S
• Alphabetical List of Instructions
MNEMONICS
ADC A. m
ADC A. It
Bytes
Machine Cycles
States
2
1
2
2
6
4
ADC A. (HL)
1
2
6
ADC A. (IX+d)
3
6
14
ADC A. (Iy +d)
3
6
14
ADD A. m
2
2
6
ADD A. g
1
ADDA. (HL)
1
2
2
6
ADD A. (IX +d)
3
6
14
ADD A. (IY+d)
3
6
14
ADC HL. ww
2
6
10
4
ADD HL. ww
1
5
7
ADD IX. xx
2
6
10
ADD IY. yy
2
6
10
ANDm
2
2
6
ANDg
2
4
AND (HL)
1
1
6
AND (IX+d)
3
AND (IY+d)
3
2
6
6
BIT b. (HL)
2
3
9
BIT b. (IX+d)
4
5
15
BIT b. (IY + d)
4
5
15
BIT b. g
2
2
6
CALL f. mn
3
2
6
3
6
14
14
(If condition is false)
16
(If condition is true)
16
CALL mn
3
6
CCF
1
1
3
CPD
2
6
12
CPDR
2
8
14
(If BC.*O and Ar* (HL)M)
12
2
6
CP(HL)
1
2
6
CPI
2
6
12
CPIR
2
8
(If BC.=O or Ar= (HL)M)
14
(If BC.*O and Ar* (HL)M)
•
HITACHI
(Continued)
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
627
HD64180S
MNEMONICS
CPIR
Bytes
Machine Cycles
2
6
States
12
(If BC.=O or Ar= (HL).,)
3
6
14
CP (IY+d)
3
6
14
CP (IX+d)
CPL
1
1
3
CPm
2
2
6
CP g
1
2
4
DAA
1
2
4
DEC (HL)
1
4
10
DEC IX
2
3
7
DECIY
2
3
7
DEC (IX+d)
3
8
18
DEC (IY+d)
3
8
18
DECg
1
2
4
DECww
1
2
4
DI
1
1
3
DJNZ j
2
!i
9(lf Ik1'O)
2
3
7(If Br=O)
EI
1
1
3
EXAF, AF'
1
2
4
EX DE, HL
1
1
3
EX (SP), HL
1
6
16
EX (SP), IX
2
7
19
EX (SP), IY
2
7
19
EXX
1
1
3
HALT'
1
1
3
1M 0
2
2
(j
1M 1
2
2
6
1M 2
2
2
6
INC g
1
2
4
INC (HL)
1
4
10
INC (IX+d)
3
8
18
INC (IY+d)
3
8
18
INCww
1
2
4
INC IX
2
3
7
INC IY
2
3
7
IN A, (m)
2
3
9
IN g, (C)
2
3
9
INI
2
4
12
INIR
2
Ii
I""f I1r
•
628
HITACHI
I ())
(Continued)
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
MNEMONICS
INIR
Bytes
Machine Cycles
Stares
2
4
12(If Br=O)
12
IND
2
4
INDR
2
6
14 (If Br*O)
2
4
12 (If Br=O)
INO g, (m)
3
4
12
JP f, mn
3
2
6
(If f is false)
3
3
9
(If f is true)
JP (HL)
1
1
3
JP (IX)
2
2
6
JP OY)
2
2
6
JP mn
3
3
9
8
JR j
2
4
JR C, j
2
2
6
(If condition is false)
2
4
8
(If condition is true)
JR NC, j
2
2
2
4
6
(If condition is false)
8
(If condition is true)
JR Z, j
2
2
2
4
6
(If condition is false)
8
(If condition is true)
JR NZ, j
2
2
6
(If condition is false)
2
4
lO A, (BC)
1
2
6
lO A, (DE)
1
2
lO A, I
2
2
6
6
LD A, (mn)
3
4
12
lOA, R
2
2
6
8
(If condition is true)
lO (BC), A
1
3
7
lOD
lO (DE), A
2
4
12
1
3
7
LD
WW,
mn
3
3
9
LD
WW,
(mn)
4
6
18
~HITACHI
(Continued)
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
629
HD64180S
MNEMONICS
LDDR
Bytes
Machine Cycles
2
6
14 (If BC.=1=O)
2
4
12(If BC.=O)
LD (HL). m
2
3
9
LD HL. (mn)
3
5
15
LD (HL). g
1
3
7
LDI
2
4
12
LD I. A
2
2
LDIR
2
6
14(If BC.=1=O)
2
4
12(If BC.=O)
6
LD IX. mn
4
4
12
LD IX. (mn)
4
6
18
LD (IX+d). m
4
5
15
LD (IX+d). g
3
7
15
LD IY. mn
4
4
12
LD IY,
~
6
18
LD (IY+d), m
4
5
15
LD (IY+d). g
3
7
15
LD (mn). A
3
5
13
LD (mn). ww
4
7
19
LD (mn), HL
3
6
16
LD (mn), IX
4
7
19
LD (mn). IY
4
7
19
LDR. A
LD g. (HL)
LD g. (IX+d)
LD g. (IY+d)
2
2
6
1
2
6
3
6
14
3
6
14
LDg. m
2
2
6
LD g. g'
1
2
4
LD SP. HL
LD SP. IX
1
2
4
2
3
7
LD SP. IY
2
3
7
MLTww
2
13
17
NEG
2
2
6
NOP
1
1
3
OR (HL)
1
2
6
OR (IX+d)
3
6
14
OR (IY+d)
3
6
14
ORm
2
2
6
(111n)
ORg
1
2
4
OTDM
2
6
14
•
630
States
HITACHI
(Continued)
Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
MNEMONICS
OTDMR
OTDR
Bytes
Machine Cycles
States
2
8
16(If Br*O)
2
6
14 (If Br=O)
2
6
14 (If Br*O)
2
4
12 (If Br=O)
OTIM
2
6
14
OTIMR
2
8
16 (If Br*O)
6
14(If B,=O)
2
OTIR
I
2
2
6
14(If Br*O)
4
12(If Br=O)
OUTD
2
4
12
OUTI
2
4
12
OUT (m), A
2
4
10
OUT (C), g
2
4
10
OUTO (m), g
3
5
13
POP IX
2
4
12
POPIY
2
4
12
POP zz
1
3
9
PUSH IX
2
6
14
PUSHIY
2
6
14
PUSH zz
1
5
11
RES b, (HL)
2
5
13
RES b, (IX+d)
4
7
19
RES b, (IY·+d)
4
7
19
RES b, g
2
3
7
RET
1
3
9
RET f
1
3
5
(If condition is false)
4
1
10
(If condition is true)
RETI
2
10
22
RETN
2
4
12
RLA
1
1
3
RLCA
1
1
3
RLC (HL)
2
5
13
RLC (IX+d)
4
7
19
RLC (IY +d)
4
7
19
RLCg
2
3
7
RLD
2
8
16
RL (HL)
2
5
13
•
HITACHI
(Continued)
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
631
HD64180S
MNEMONICS
Bytes
Machine Cycles
RL (IX +d)
4
7
RL (Iy +d)
4
7
19
19
RL g
2
3
7
RRA
1
1
3
RRCA
1
1
3
RRC (HL)
2
5
13
RRC (IX+d)
4
7
19
RRC (IY+d)
4
7
19
RRC g
2
3
7
RRD
2
8
16
RR (HL)
2
5
13
RR (IX+d)
4
7
19
RR (IY+d)
4
7
19
RRg
2
3
7
RST v
1
5
11
SBC A. (HL)
1
2
6
SBC A. (IX+d)
3
6
14
SBCA. (IY+d)
3
6
14
SBCA. m
SBCA. g
2
6
1
2
2
SSC HL. ww
2
6
10
SCF
1
1
3
SET b. (HL)
2
5
13
SET b. (IX +d)
4
7
19
SET b. (IY+d)
4
7
19
SET b. g
2
2
4
4
2
2
3
7
5
13
SLA (HL)
SLA (IX+d)
SLA (IY+d)
SLAg
SLP
SJ{A (ilL)
4
7
19
7
19
3
7
2
8
~
:,
1:1
SRA (IX+d)
4
7
19
SRA (IY+d)
4
2
7
3
19
SRA g
SRL (HL)
5
13
7
19
7
19
SRL g
2
4
4
2
3
7
SUB (HL)
1
2
6
SRL (IX+d)
SRL (IY+d)
-----~
•
632
States
HITACHI
7
.
(Continued)
Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300
HD64180S
MNEMONICS
Bytes
Machine Cycles
StiIte§
SUB (IX+d)
3
6
14
SUB (IY+d)
3
6
14
SUBm
2
2
6
SUB g
1
2
4
TSTIO m
3
4
12
7
TST g
2
3
TSTm
TST (HL)
3
3
9
2
4
10
XOR (HL)
1
2
6
XOR (IX+d)
3
6
14
XOR'IY+d)
3
6
14
XORm
2
2
6
XORg
1
2
4
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
633
• Opcode Maps
0>
W
"""
::r:
t1
Table 1. Opcode Map (1)
0)
~
::r
~
s:
co
00
o
=.
First opcode
3
Instruction fonnat: XX
»
'""'.
co
rn
.?'
r-
c:
•
~
~
=.
"
~
•
B
0
§'"
~~
iil
"
:I
-
2. ~
:=l. )i
JfO
~ J:
•
CXJ
"'.
en
C"
'":::>
5"
~
*
~
00
<0
•
E
~
~
~
:5
ww(LO=ALL)
LO=0-7
DE
HL
SP
BC
DE
HL
AF
g (LO=0-7)
PO
P
NZ
NC
(HL)
B
(HL)
0
H
B
0
H
OOH 10H 20H 30H
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1
4
F
5
6
7
9
A
B
2
3
0
8
0
0
E
I
NOP DJNZj JR NZ.j JRNO,j
RET f
I
:
.1
LO ww,mn
POP zz.
I
LO(ww)' A LD(rm) LD(mn)
JP f, mn
I
I
,HL
,A
JP mn
:secona opcooe
Instruction fonnat: CB XX
B
LO
~
0000 0
0001
D 0010
E 0011
H 0100
---..
...J
0101
L
...J
« (HL) 0110
II
A 0111
:c
'-'
1000
B
C 1001
D 1010
be
1011
E
H 1100
1101
L
(HL) 1110
A 1111
C
b (LO=0-7)
4
0
6
2
4
2
0
6
0
2
4
6
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1
2
3
0
4
5
6
7
9
A
B
C
D
E
F
8
3
RLC g RL g SLA g
5
6
--- ---- ------ ---- ----
7
8
9
. . .
BIT b,g
RES b,g
.
.
SET b,g
.
---------------- ---------------- ------------------------------- ---------------- ----------------
E
F
r-----e
~
8
~
'E3
B
D
~
~
rg--
A
C
en
0
-,-~
a-
1
2
4
o
RRC g RR g SRA g SRLg
BIT b,g
RES b,g
r-o
SET b,g
--- ---- ---- ---- ----------------------------------------------r-o
r-y.
.
. . . .
--- ---- ---- ----
0
1
3
2
.
---------------- ---------------- ---------------- ~
4
1
5
3
6
5
7
7
8
1
9
A
3
5
B
7
C
1
D
3
E
5
F
7
b (LO=8-F)
*
In the instruction to be executed. DDH can be added to the beginning of the opcode and (HL) is replaced by (IX + d) in
opcode DD CB d XX. In the same way. FDH can be added to the beginning of the opcode. In the instruction to be
executed. (HL) is replaced by (IY+ d) in opcode FD CB d XX.
:J:
~
Table 3. Opcode Map (3)
2:
:<>
3
~.
Second opcode
Instruction fonnat: ED XX
.?'
li
•
:J:
;::;:
'"2:
("")
"1J
~0
~
'"•
§""
~.
iil
"1J
2.
:I
_
!""I
;a )i
ifC')
~ :I
•
'"c-
CD
:::!.
'"
:::J
CD
§;
..,.
o
<0
~
~
CD
•
~
~
01
00
CD
Co
w
o
o
Q)
W
'-J
LO
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
ww (LO=ALL)
BC
DE
HL
SP
g (LO=0-7)
B
0
H
B
H
0
0000 0001 0010 0011 0100 0101 0110 0111 1000 11001
4
1
2
3
5
6
7
0
819
IN g, (C)
INO g, (m)
OUT (C),g
OUTO (m),g
SBC HL,ww
LO (mn),ww
OTIMIOTIMR
TST(HL) NEG
TST m TSTKlm
TST g
RETN
SLP
1M 0 1M 1
LDI,A LD A,I RRO
IN g, (C)
INO g, (m)
OUT (C),g
OUTO (m),g
AOC HL,ww
LO ww, (mn)
OTOMIOTDMR
MLT ww
TST g
RETI
1M 2
LD R,A LD A,R RLO
0
4
1
2
3
5
6
7
8 I 9
A
A
C
E
L
C
E
L
g (LO=8-F)
1010
A
LOI
CPI
INI
OUTI
1011 1100111011111011111
B
C 1 DIE 1 F
LOIR
CPIR
INIR
OTIR
-0,
-y-
-a
~
-g-
LOO
CPO
INO
OUTO
---e
~
-a
-g
LOOR
CPOR
INOR
OTOR
-;::-S
-0
[)
E-
-r
A
B
C 1 DIE
1 F
::r:
tJ
en
~
~
ex:>
o
til
HD64180S
• Bus Cycle States
••• in the ADDRESS column indicates that the address output is undefmed and 'z' in the DATA
column indicates that the data pin is in the high-impedance state. The LIR pin output value is
obtained when the LIRE bit in the operation mode control register is 1.
hl"lruerk)11
Machine
Cvcle
MC.
ADD HL.ww
T.T,T.
ADDA.m
ADCA.m
SUB m
SBC Am
ANDm
ORm
XORm
Mr
lOr
un
IIAI.T
ST
1st
op-code
0
1
0
1
0
1
0
*
Z
1
1
1
1
1
1
1
T,T,T.
0
1
0
1
0
1
0
MC,
T,T,T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC.
-MC.
TiTiTiTi
*
Z
1
1
1
1
1
1
1
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T ,T,T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC.
-MC.
TiTiTiTi
Z
1
1
1
1
1
1
1
MC,
T,T,T.
1st
op-code
0
1
0
1
0
1
0
MC,
Ti
Z
1
1
1
1
1
1
1
MC,
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,T,T.
1st operand
Address
m
0
1
0
1
1
1
1
MC,
T,T,T.
1st op-code
Addrass
1st
op-code
0
1
0
1
0
1
0
MC,
T,T,T.
HL
DATA
0
1
0
1
1
1
1
MC,
T,T,T.
1st op-code
Addrass
1st
op-code
0
1
0
1
0
1
0
MC,
T,T,T3
2nd op-code
Address
op-cod8
0
1
0
1
0
1
'1
MC,
ADD A.g
ADC A.g
SUB 9
SBC A.g
ANDg
OR 9
XORg
CP 9
wn
1st
op-code
MC,
ADC HL.ww
SBC HL.ww
no
1st op-code
Address
TiTiTiTi
ADD lX.xx
rY.vv
1st op-code
Address
DATA
MC,
-MC"
ADD
AoonrSS
Slnlnn
*
1st op-code
Address
*
CPm
ADD A IHU
ADC A. (HU·.
SUB IHL)
SBC A IHU
AND IHU
OR (HU
XOR (HL)
CP IHU
ADD
ADD
ACC
ADC
SUB
SUB
A (1X+d)
A. (IY+ d)
A (IX + d)
A, (IY+d)
IIX+d)
(IY+d)
2nd
SBC A. IIX+d)
•
638
HITACHI
(Continued)
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
Instruction
SBC A. (IV+d)
AND (1X+d)
AND (lV+d)
OR (lX+d)
OR (lY+d)
XOR (lX+d)
XOR (lV+d)
CP (1X+d)
CP (lY+d)
Machine
Cycle
MC3
MC.
-MC.
MC.
MC,
States
T,T,T3
MC,
Z
UR
HALT
ST
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1X+d
IV+d
DATA
0
1
0
1
1
1
1
T,T,T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T,T,T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
2nd op-code
2nd
T,T,T3
Address
op-code
0
1
0
1
0
1
1
MC3
T,T,T3
HL
DATA
0
1
0
1
1
1
1
T,T,T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T3
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T,T,T3
1st operand
Address
d
0
1
0
1
1
1
1
T,T,T3
3rd op-code
Address
3rd
op-code
0
1
0
1
0
1
1
T,T,T3
1X+d
lY+d
DATA
0
1
0
1
1
1
1
T,T,T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T3
1st operand
Address
n
0
1
0
1
1
1
1
MC3
T,T,T3
2nd operand
Address
m
0
1
0
1
1
1
1
MC.
Ti
1
1
1
1
1
1
1
MC.
T,T,T3
SP-l
PCH
1
0
0
1
1
1
1
MC.
T,T,T3
SP-2
PCL
1
0
0
1
1
1
1
T,T,T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T3
1st operand
Address
n
0
1
0
1
1
1
1
MC,
MC3
MC.
MC.
MC,
MC,
CALL t.mn
(If condition
is false)
*
IOE
MC,
MC,
CALL mn
d
-RD -WR -ME
T,T,T3
BIT b. (HL)
BIT b. (1X+d)
BIT b. (IV + d)
1st operand
Address
TiTi
BIT b.g
MC,
DATA
ADDRESS
MC,
MC,
Z
*
(Contmued)
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
639
HD64180S
Instruction
Machine
Cycle
HALT
ST
1
0
1
0
T,T,Ta
n
0
1
0
1
1
1
1
MCa
T ,T,Ta
2nd operand
Address
m
0
1
0
1
1
1
1
MC.
Ti
1
1
1
1
1
1
1
MC.
T,T,Ta
SP-l
PCH
1
0
0
1
1
1
1
MC.
T ,T,Ta
SP-2
PCL
1
0
0
1
1
1
1
T,T,Ta
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,T,Ta
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MCa
T,T.Ta
HL
DATA
0
1
0
1
1
1
1
*
Z
*
Z
1
1
1
1
1
1
1
T,T,Ta
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC.
T,T,Ta
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MCa
T,T,T3
HL
DATA
0
1
0
1
1
1
1
TiTiTi
*
1
1
1
1
1
1
1
T,T.Ta
1st
op-code
0
1
0
1
0
1
0
MC.
T,T.Ta
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MCa
T,T,Ta
HL
DATA
0
1
0
1
1
1
1
MC.
-MC.
TiTiTiTiTi
Z
1st op-code
Address
MC,
*
Z
1
1
1
1
1
1
1
T,T.Ta
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,T.T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC.
Ti
Z
1
1
1
1
1
1
1
0
1
0
1
0
1
0
MC,
TiTiTi
OM
*1
--
0
MC.
-MC.
01 *1
-LlR
1
MC,
CPL
IOE
0
MC.
-MC.
CPIR
CPDR
(If BCR=O or
Ar=(HU..l
-ME
1st operand
Address
MC,
CPIR
CPDR
(If BCR'l"O and
Ar'l"(HL)..l
-WR
lst
op-code
MC,
CPI
CPO
RD
1st op-code
Address
MC,
CCF
DATA
ADDRESS
T,T,Ta
MC.
CAli f.mn
(If condition
is true)
States
MC,
T,T.T3
*
1st op-code
Address
1st
op-code
No interrupts are sampled at the end of a 01 instruction.
(Continued)
~HITACHI
640
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD64180S
Instruction
DJNZj
(If 8r*0)
Machine
Cycle
MC,
T,T,T.
MC,
Ti
MC.
MC.
-MC.
DJNZj
(ij 8r=0)
*3
1st op-code
Address
MC,
Ti
WR
ME
iOE
LIR
HALT
ST
1st
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
0
1
0
1
1
1
1
*
1st operend
Address
*
TiTi
T,T,T.
1st op-code
Address
.2
j-2
Z
1
1
1
1
1
1
1
1st
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
T,T,T.
1st operand
Address
j-2
0
1
0
1
1
1
1
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T ,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
Ti
MC,
EX DE, HL
EXX
T,T,T.
RD
DATA
ADDRESS
*2
MC,
MC.
EI
States
MC,
*
EX AF, AF'
EX (SP), HL
EX (SP),IX
EX (SP),IY
*2
*
Z
1
1
1
1
1
1
1
1st
op-code
0
1
0
1
0
1
0
MC,
T ,T,T.
1st op-code
Address
MC,
T,T,T.
SP
DATA
0
1
0
1
1
1
1
MC.
T ,T,T.
SP+l
DATA
0
1
0
1
1
1
1
MC.
Ti
1
1
-1
1
1
1
1
Z
*
MC.
T,T,T.
SP+l
H
1
0
0
1
1
1
1
MC.
T,T.T.
SP
L
1
0
0
1
1
1
1
MC,
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC,
T,T,T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC.
T,T,T.
SP
DATA
0
1
0
1
1
1
1
MC.
T,T,T.
SP+l
DATA
0
1
0
1
1
1
MC.
Ti
1
1
1
1
1
*
Z
,
,
1
(Continued)
DMA, refresh, and bus release cannot be executed immediately after this state (their requests are ignored).
*3 No interrupts are sampled at the end of an EI instruction .
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
641
HD64180S
InstruCtion
EX (SP), IX
EX (SP),IY
Machine
Cycle
States
1
1
1
T.T.T.
SP
1
0
0
1
1
1
1
T.T.T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
---
Next op-code
Address
Next
op-code
0
1
0
1
0
0
0
T.T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T.T.T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC.
T1T2T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC.
Ti
*
1
1
1
1
1
1
1
0
1
0
1
0
1
0
DATA
0
1
0
1
1
1
1
1
1
1
1
1
1
1
Me.
T.T.T3
MC.
T.T.T.
HL
MC.
Ti
MC.
T.T2T.
HL
DATA
1
0
0
1
1
1
1
T.T2T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T .T2T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T.T2T.
1st operand
Address
d
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
DATA
1
0
0
1
1
1
1
lst
op-code
0
1
0
1
0
1
0
MC2
Me.
MC.
-MC.
T.T2T.
MC7
Ti
Z
*
TiTi
Me.
lX+d
IY+d
Z
*
DATA
Z
*
T.T2T.
lX+d
IY+d
Me.
T .T2T.
lst op-code
Address
Me2
Ti
MC.
Z
*
1
1
1
1
1
1
1
T.T2T.
1st op-code
Address
1st
op-dode
0
1
0
1
0
1
0
Me2
T .T2T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC.
Ti
Z
1
1
1
1
1
1
1
MC.
*
(Continued)
•
642
Z
1st
op-code
1st op-code
Address
MC.
INC IX
INC IV
DEe IX
DEC IY
ST
1
MC.
INCww
DEe ww
HALT
0
1M2
DEC (lX+d)
DEC (lV+d)
tiR
0
MC.
INe (lX+d)
INe(lY+d)
iCE
1
-
INC (HU
DEC (HL)
ME
IXL
IVL
MC.
INCg
DEC g
WR
IXH
IYH
T.T.T.
HALT
IMI
RD
SP+l
MC.
MC7
IMO
DATA
ADDRESS
HITACHI
Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
Instruction
Machine
Cycle
HALT
ST
0
1
0
1
0
T,T.T.
m
0
1
0
1
1
1
1
T,T.T.
mtoAo-Ar
A to A.-A ..
DATA
0
1
1
0
1
1
1
T,T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC.
T,T.T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC.
T,T.T.
BC
DATA
0
1
1
0
1
1
1
T,T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T.T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T,T.T.
1st operand
Address
m
0
1
0
1
1
1
1
T,T.T.
mtoAo-Ar
OOHto A.-A ..
DATA
0
1
1
0
1
1
1
T,T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
2nd
MC.
T,T.T.
2nd op-cocle
Address
op-code
0
1
0
1
0
1
1
MC.
T,T.T.
BC
DATA
0
1
1
0
1
1
1
MC.
T,T.T.
HL
DATA
1
0
0
1
1
1
1
T,T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC.
T,T.T.
2nd op-code
Addrass
2nd
op-code
0
1
0
1
0
1
1
MC.
T,T.T.
BC
DATA
0
1
1
0
1
1
1
MC.
T,T.T.
HL
DATA
1
0
0
1
1
1
1
MC.
MC.
MC,
Me,
MC.
-MC.
Z
1
1
1
1
1
1
1
T,T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC.
T,T.T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
MC.
T,T.T.
BC
DATA
0
1
1
0
1
1
1
MC.
T,T,T.
HL
DATA
1
0
0
1
1
1
1
MC,
INIR
UR
1
MC.
INDR
(IfBr=O)
IOE
0
MC.
INIR
INDR
(If B,*O)
-ME
1st operand
Address
MC,
1111
1110
WR
1st
op-code
MC,
INOg.(m)
-RD
1st op-code
Address
MC.
IN g.(C)
DATA
ADDRESS
T,T.T.
MC,
IN A.1m!
States
TiTi
*
(Continued)
•
HITACHI
Hitachi America. Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
643
HD64180S
Machine
Instiuction
MC,
JP mn
MC,
MC.
JP
(If
t,mn
t is false)
MC,
MC,
MC,
JP I,mn
(If f is tNe)
MC,
MC.
JP (HL)
MC,
MC,
JP (IX)
JP (IY)
MC,
MC,
JR j
MC,
MC.
-MC.
JR C,j JR NC,j
JR ZJ JR NZ,j
(If condition
is false)
JR C,j JR NC,j
JR Z,j JR NZ,j
(If cond~ion
is INe)
States
Cvcle
MC,
MC,
MC,
MC,
MC.
-MC.
DATA
ADDRESS
-LIR
-HALT
ST
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T.
1st operand
Address
n
0
1
0
1
1
1
1
T,T,T.
2nd operand
Address
m
0
1
0
1
1
1
1
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T.
1st operand
Address
n
0
1
0
1
1
1
1
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T.
lst operand
Address
n
0
1
0
1
1
1
1
T,T,T.
2nd operand
Address
m
0
1
0
1
1
1
1
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T.
1st op-code
Address
lsI
op-code
0
1
0
1
0
1
0
T,T,T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T.
1st operand
Address
j-2
0
1
0
1
1
1
1
Z
1
1
1
1
1
1
1
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T.
1st operand
Address
)-2
0
1
0
1
1
1
1
T,T,T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,T.
1st operand
Address
j-2
0
1
0
1
1
1
1
TiTi
TiTi
MC,
T,T,T.
MC,
Ti
*
*
1st op-code
Address
Z
1
1
1
1
1
1
1
1st
op-code
0
1
0
1
0
1
0
LD g,g'
MC,
-RD -WR -ME -IOE
Z
1
1
1
1
1
1
1
T,T,To
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T,To
1st operand
Address
m
0
1
0
1
1
1
1
*
LDg,m
MC,
(Continued)
~HITACHI
644
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
instruction
Machine
Cycle
S_s
m
HArT'
ST
1
0
1
0
1
0
MC.
T,T.To
HL
DATA
0
1
0
1
1
1
1
T,T.To
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T.To
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T,T.To
1st operand
Address
d
0
1
0
1
1
1
1
1
1
1
1
1
1
1
DATA
0
1
0
1
1
1
1
1st
op-code
0
1
0
1
0
1
0
Z
1
1
1
1
1
1
1
MCo
TiTi
Z
*
T,T.To
lX+d
IY+d
Me,
T,T.To
1st op-code
Address
Me.
Ti
Meo
T,T.To
HL
9
1
0
0
1
1
1
1
T,T.To
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T.To
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T,T.To
1st operand
Address
d
0
1
0
1
1
1
1
1
1
1
1
1
1
1
MC,
MC.
MCo
MC.
-Me.
*
TiTiTi
Z
*
T,T:zT3
lX+d
IY+d
9
1
0
0
1
1
1
1
T,T.To
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
MC.
T,T.To
1st operand
Address
m
0
1
0
1
1
1
1
Meo
T,T.To
HL
DATA
1
0
0
1
1
1
1
T,T,To
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T.To
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T,T,To
1st operand
Address
d
0
1
0
1
1
1
1
T,T,To
2nd operand
Address
m
0
1
0
1
1
1
1
T,T,To
lX+d
lY+d
DATA
1
0
0
1
1
1
1
T,T,To
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
Me,
MC,
Me,
Me,
MCo
Me.
Me.
LO A. (Be)
LD A. (DE)
i6E
0
MC.
LO OX+dl.m
LO oY+d).m
ME
1st
op-code
MC.
-MC.
LD (HU.m
WR
1st op-code
Address
MC.
LO OX+d).g
LD oY+d).g
Ri5
T,T.To
MC,
LD (HU.g
DATA
MC,
LO g. (HU
LO g. OX+d)
LD g. (lY+d)
ADDRESS
Me,
(Continued)
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
645
HD64180S
Machine
Instruction
States
eycle
LD A. (Bel
I:D A IDE)
0
1
1
1
1
T,T.T.
0
1
0
1
0
1
0
T,T.T.
1st operand
Address
n
0
1
0
1
1
1
1
Me.
T,T.T.
2nd operand
Address
m
0
1
0
1
1
1
1
Me.
T,T,T.
mn
DATA
0
1
0
1
1
1
1
Me.
T.T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
Me.
Ti
Z
1
1
1
1
1
1
1
*
T,T.T.
Be
DE
A
1
0
0
1
1
1
1
T,T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T.T.
1st operand
Address
n
0
1
0
1
1
1
1
Me.
T,T.T.
2nd operand
Address
m
0
1
0
1
1
1
1
Me.
Ti
1
1
1
1
1
1
1
Me.
T,T.T.
mn
A
1
0
0
1
1
1
1
T.T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T.T.T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T,T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T.T.T.
1st operand
Address
n
0
1
0
1
1
1
1
T.T.T3
2nd operand
Address
m
0
1
0
1
1
1
1
T.T.T.
1st op-code
Addres!
1st
op-code
0
1
0
1
0
1
0
T .T,T.
2nd op-code
Address
2nd
op-code
0
1
0
1
0
1
1
T.T.T.
1st operand
Address
n
0
1
0
1
1
1
1
T,T.T.
2nd operand
Address
m
0
1
0
1
1
1
1
T.T,T3
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T.T.T.
1st operand
Address
n
0
1
0
1
1
1
1
Me,
Me,
Me.
Me.
Me.
Me,
Me.
Me.
MC.
MC,
*4
Z
*
No Interrupts are sampled at the end of a LD A. I or LD A. R instruction .
•
646
ST
1
Me.
LD HL. (mn)
1M llAt"I'
0
Me.
LD lX.mn
LD IY.mn
iOE
1st
op-code
Me,
LD _.mn
'AilE"
DATA
Me.
o.
o,
WIf
1st op-code
Address
Me.
LD AI
LD A.R
LD ~A
LDR.A
AD
Be
DE
LD Almnl
LD ImnlA
DATA
T,T.T.
Me.
Me,
LD (BelA
1.0 (DEl.A
ADDRESS
(Continued)
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300
HD64180S
hUltnlcliol\
LD Hl, (mnl
Machine
Cycle
Wii
ME
W
TIIf
RArT
ST
2nd operand
Address
m
0
1
0
1
1
1
1
MC.
T,T.T.
mn
DATA
0
1
0
1
1
1
1
MC.
TIT.T.
mn+l
DATA
0
1
0
1
1
1
1
T,T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
2nd
op-code
0
1
0
1
0
1
1
MC.
T,T.T.
MC.
T,T.T.
2nd op-code
Address
1st operand
Address
n
0
1
0
1
1
1
1
MC.
T,T.T.
2nd operand
Address
m
0
1
0
1
1
1
1
MC.
T,T.T.
mn
DATA
0
1
0
1
1
1
1
MC.
T,T.T.
mn+l
DATA
0
1
0
1
1
1
1
T,T.T.
1st op-code
Address
1st
op-code
0
1
0
1
0
1
0
T,T.T.
2nd op-co
® > ® (Low)
Type ® requests are prioritized as follows:
(High) BUSREQ> Refresh request > DMA request (Low)
For the priority of type ® requests, see section 3.6 "Interrupts"
_HITACHI
662
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
HD64180S
• State Transition Diagrams
(1) Chip operation mode transition diagram
(2) Bus control transition
BUSREO= 0
_____
B_U_SREO = 1 and refresh request issued
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
663
S
CJ)
CJ)
.j::>
• Status Signals
m
~
~
::J:
i.
l>
3
CD
::!.
ex>
o
Status signals are listed below.
Chip
operation
mode
rn
"
Operation cycle
ill
C")
!"
[CPU
r-
8:
•
::J:
1
1
1
0
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
i I
,
1 , 1
0
0
1
1
1
1
0
1
0
1
1
1
1
1
I
1
1
1
1
1
~~
i I/O write
Internal operation
I
NNI
lIclmowl- I
edge(rust
1NT.
i machine
cycle)
I INTI, INT., and internal interrupts
i
Intema1
BUSACK
1
J/Oread
~
""0 :I
_
HALT
0
""0
Interrupt
REF
1
1
Nonnal
operation
mode
Wi!
0
1
•
§
~~
Ril
0
Memory write
N
IOE
Second and third opcode fetch
Memory read
~
liE
F1lSt opcode fetch
~
=r.
I
0
:
I
1
0
I
I
I
I
I
I
I
!
I
ST
CS._ 2
A.-A ..
0.-0,
0
OCT (Al
OU1' (Al
J::'\
1
OCT (Al
OUT (Al
J::'\
1
OCT (Al
OUT (Al
1
OCT (Al
OUT (Al
1
1
OUT (Al
1
1
OUT (Al
I
1
OUT (Al
Z
0
I
1
0
I
I
1
I
0
1
i
0
1
1
1
I
1
I
I
I
1
1
I
1
I
0
0
:
0
,
0
OUT (Al
J ::'\
OUT (Al
J ::'\
1
OUT (Al
Z
Memory read
I
,
0
1
0
1
I
I
1
0
OCT (Al
OUT (Al
1
1
0
1
1
0
I
I
1
0
OCT (Al
OUT (Al
CD
J/Oread
1
I
I
0
0
1
1
1
1
g}
I/O write
'"::;,
1
i 1
0
1
0
I
I
1
CD
Internal operation
1
1
1
1
1
1
1
1
§;Z
Rdresh
1
0
1
1
1
0
1
1
!
Bus release mode
1
z
z
z
Z
1
1
0
I
~ :I
DMA
•
::!.
~
~C;;
cD
•
~
e
CJ1
00
CD
0::.
Col
g
------
~
...
--
i
I
!
j
I
;
I
1
OUT (Al
0
1
OUT (Al
0
1
OUT (Al
I
1
OUT (Al
1
1
0
J::'\
OUT (Al
1
OCT (Al
I
Memory write
~()
J::'\
OUT (Al
Z
I:
0:
OUT (A):
IN:
Z:
,
1::,\
OUT (Al
J::'\
OUT (Al
Z
Z
Z
High level output
Low level output
Any output
Input
,
High impedance
i
~
• Status Signals (cont.)
~
»=-
Chip
opert'i""
3
o·
~
ill
ME
fOE
RO
i\R
REF
Memotyread
1
0
1
0
1
Memory write
1
0
1
1
Operation cycle
HALT
BUSACK
Sf
CS._.
Ao ---A I9
1
0
1
0
OUT (A)
OUT (A)
0
1
0
1
0
OUT (A)
OUT (A)
I
mcde
P'
!::
Co
Halt
Internal
mode
DMA
!
•
:J:
I/O read
1
1
0
0
1
1
0
1
0
1
OUT (A)
=-
I/O write
1
1
0
1
0
1
0
1
0
1
OUT (A)
Internal operation
1
1
1
1
1
1
0
1
0
1
OUT (A)
Refresh
1
I
0
1
1
1
0
0
1
1
1
OUT (A)
1
i z I z
z
Z
1
0
0
1
1
i 0
i 0
~
-0
,
~
•
w.
I\.)
Bus release mode
8
;;J
-0 :I
_
Q.
~
Halt mode other than above
•
OUT (A)
I
I :\
OUT (A)
OUT (A)
i
I :\
1
OUT (A)
OUT (A)
! OUT
I
,I
0
1
OUT (A)
i
I
1
i
I 1
I 0
0 I 1
0
1
I
1
0
1
: I/O write
1
C")
~
OUT (A)
0
1
»
~
0
1
Memory write
0-
CO
1
0
I/Oread
:::>
~
0
1
i
'"
.cD
'2.
1
1
I
!
System
stop
mode
,
I
I
1
1
I
I
!
1
0
1
0
1
0
1
0
1
OUT (A)
0
I
1
0
1
0
1
OUT (A)
1
I
1
0
1
0
1
,OUT (A)
I
1
OUT (A)
I
I
z
z
Refresh
1
0
I
1
1
1
0
0
1
1
1
Z
I z
z
Z
1
0
0
1
1
Z
Z
Sleep mode other than above
1
1
1
1
1
1
0
1
1
1
1
Z
Bus release mode
1
Z
Z
Z
Z
1
0
0
1
1
Z
Z
System stop mode other than above
1
1
1
1
1
1
0
1
1
1
1
Z
---
I
1
1
I
I
1
1
1
1
Z
Z
Ij
j
(Al
1:\
Bus release mode
Reset
mode
Z
1
DMA
C::J
I
0
mode
ffi-
z
z
0
1
1
I
1
! Memoty read
Internal operation
I i\
OUT (A)
1
Internal
~3:
•
Z
I i\
OUT (A)
I
I
Sleep
:a>
-00
;a
0
I
I
0.-0,
$
U1
1:
High level output
CO
0:
Low level output
<:::>
<:::>
OUT (A):
IN:
Z:
Any output
Input
High impedance
ex>
~
::r:
tJ
(J)
~
~
OJ
OJ
C11
ex>
o
en
HD64180S
• Pin States in Reset and Low Power Dissipation Modes
Pin name
TIN •. TIN,
TOUT •. TOUT',
CS •. CS,. CS.
WAIT
NMI
I NT o. I NT ,. INT.
RESET
BUSREQ
BUSACK
ST
LIR
REF
HALT
RO
WR
----.:::-ME
IOE
OUT (A)
HOLD
OUT (A)
OUT (H)
(A)
I N (N)
I N (A)
I N (A)
IN (A)
IN (A)
OUT (H)
OUT (A)
OUT (A)
IN
IN
IN
IN
IN
(N)
(N)
(N)
IN
IN
IN
IN
IN
(A)
(N)
(A)
(A)
(A)
(A)
(I-I)
OUT (A)
OUT (H)
OUT (H)
OUT (H)
OUT (H)
OUT (H)
OUT ( A)
OUT (H)
OUT (H)
OUT ( L )
OUT ( L )
OUT (H)
OUT (A)
OUT (H)
OUT (H)
OUT (A)
OUT (H)
(I-I)
OUT (A)
OUT (H)
OUT (H)
OUT (A)
OUT (H)
OUT (A)
OUT (H)
OUT
---~---
OUT
Z
I N
(A) •
OUT (A) •
I N (N)
IN
z
(A)
Z
I N (N)
--
OUT (A)
HOLD
OUT (H)
OUT (A)
HOLD
IN (N)
IN (N)
IN (N)
IN
IN
IN
IN (A):
IN (N):
OUT (H):
OUT (L):
OUT (A):
Z:
HOLD:
•
666
I N (N)
OUT (H)
0.- 0 7
RTSM
OCDM
CTSM
RXDM
System stop mode
OUT ( L )
z
100tput selected
Sleep mode
IN (A)
Reset mode
I N (N)
A.-A,.
__ IInput selected
SYNC
Pin state
(A)
(A)
(A)
IN ( N )
IN (N)
I N (N)
Input (active)
Input (inactive)
Output (fixed to high level)
Output (fixed to low level)
Output (active) - High or low level output
High impedance
Holding the previous state
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Pin States in Reset and Low Power Dissipation Modes (cont.)
Pin name
Input selected
RXCM
TXCM
TXCA
Reset mode
Sleep mode
I N (N)
IN ( /\ )
I N (N)
OUT (A)
OUT (A)
( A)
IN (N)
OUT (A)
OUT (A)
Output selected
--
Input selected
I N (N)
Output selected
--
TXDM
RTSA
DCDA
CTSA
RXDA
RXCA
Pin state
IN
--
System stop mode
---~~
OUT (H)
OUT (A)
OUT (II)
OUT (H)
OUT
(A)
110 L D
I N ( N)
IN
(A)
I N (N)
IN (N)
IN (A)
IN (N)
I N (N)
I N (A)
I N (N)
I N (A)
IN (N)
OUT (A)
OUT (H)
IN (A)
IN (N)
OUT (H)
HOLD
Input selected
I N (N)
Output selected
--
Input selected
I N (N)
Output selected
--
OUT (A)
OUT (H)
OUT (A)
IN (N)
IN (A)
IN (N)
OUT (H)
OUT (A)
OUT (H)
oclock output
oclock output
oclock output
TXDA
DREa., OREa,
TEND.,TEND,
q,
IN (A):
IN (N):
OUT (H):
OUT (L):
OUT (A):
Z:
HOLD:
Input (active)
Input (inactive)
Output (fixed to high level)
Output (fixed to low level)
Output (active) - High or low level output
High impedance
Holding the previous state
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
667
HD64180S
• Built-in Registers
CPU
Register
Interrupt control register (ICR)
Address
OOOOH
Remarks
__
-. -
-~I~_~~_~ I~-~
~v.....
o
0
__~I_-~I__-~I_-~_-~
-- IF_~~
TRAP
&1
...
OOOlH
t:ilfo..tIiICI
0: s.aond bWltof ~ undIfIMd
1:
MMU common base register
(CBR)
1
rMr"
.......
0: TRAPirMrnIpI
I.TRAP_
-I
•
0
n.w~ofopoodtUftdlflMd
- -- - - --...
... ...
...
- - - - -- -- ... ...
...
- - - - - -_.,. .-. .J. .-. --I
coo
C87
ClIO
CII4
181
B84
881
OAI
ColO
BAI
CO2
CBI
ceo
CIt
-.
Inltla! Valu.
MMU bank base register (BBR) 0002H
-~I
887
mlllaIVaI",.
MMU common/bank area
register (CBAR)
0003H
-~I
CA3
CO2
..... v....
I
Fouthlghorderbbcltfle
1ower . . . . . lmlforCClll'lllNN'l . . . '
Operation mode control register 0004H
(OMCR)
.,.,..."...Wlortftlbw* .....
- ~L~M_._
--.
BIINarn·1
LIl7E
Llle
..... v....
I
IOC
-
I
-
I
-
I-
W
Rlllld.Writ.
1
1
0
0
0
~
ilIIe.-
0: The i:MOUIpUlillow
onlvduringtM~
t.IctIcyda2oflht
AETI_'"
... IirItM...Int~
wah that of the zeo.butd ~ LSII.
1: Norm.. operation
oftheifll'Olnterrupl
" NormaIopetaIIon
... _ _
Lii'T!fftF!OF!I'YEn
..._ _ _ 0 _ _
O. When the LIRE bit 110, theIiJiOUflM illowonirlor
totneiJil'(bIt,
1:Norm"~
~HITACHI
668
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Built-in Registers (cont.)
CPU
Register
Address
I/O control register (IOCR)
0005H
Remarks
-1-1-1-1-1-...
RiW
Intu.lv..,.
0
J..
...... ..-ISLP _ _ _1
1 IplIm IIIOp mode (8LP InIINction 1tdCUtion)
Unused
Unused
0006H
0007H
Wait Control
Register
Physical address boundary
register 0 (PABRO)
Address
0008H
Remarks
.. _I
-.
7
71 P",
P...
P8D4
RiW
fW/
RiW
p. .
RiW
P8D3
RiW
P8D2
P8D11
RiW
RoW
PlOD
RoW
•
I
IndialVu.
PALIPAN Bounclaly "'*- (I hIglMIIdefblll)
Physical address boundary
register 1 (PABRl)
_
0009H
811 ....
...
,
7
1 P8171
PIli
PIli
PI"
RiW
RiW
RoW
RiW
PI,.
fW/
PI"
pe1'
RiW
RoW
I
PI'.
RoW
InltlalVIIue
PAMofI'AH Boundary Add,... (8 hlgh-o«:ltr bill)
Wait control register L (WCRL) OOOAR
PALWl
0
0
PALWI
0
0
0
0
•
PALWO
0
Number 01 Wilt Stat..
0
1
0
I
0
I
0
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
669
HD64180S
• Built-in Registers (cont.)
Wait Control
Register
.
Remarks
Address
Wait control register M (WCRM)OOOBH
,
.
--I - 1 - 1 - 1 - 1 - 1-I ---I .- 1
--PAMWl
0
0
0
0
MIl
....
PAMWI
0
0
PAMWO
0
Num..... otWII11 Stotts
0
_-
MIl
0
I
0
0
0
1
0
Wait control register H (WCRH) OOOCH
.7
--_.....
t
PA11W2
PAHWI
b
0
0
0
0
Number otWIl1 Sloies
I
0
OOOOH
BIN....
(lOWeR)
PAHWO
0
b
I
0
0
-...
_Vol..
I-I
10M2
.,."
IOHD
MIl
MIl
MIl
,
I
I-
I'OHIg'
10HZ
0
0
0
0
lOLl
0
10HI
0
0
10HO
0
101.2
IOL,
IOLD
MIl
MIl
MIl
,
I
I'OLaw
Number 01 Wall Stoles
0
1
0
0
0
0
lOLl
10LO
0
1
Number otWII11 Stales
0
0
1
0
0
4
.HITACHI
670
0
MIl
0
I/O wait control register
2
__
·-~I_-~_-~I_-~I -~I_-~I_p~~I_·~~I~p_~~1
Hitachi America, ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300
HD64180S
• Built-in Registers (cont.)
Wait Control
Register
Interrupt wait control register
(lN1WR)
Remarks
Address
OOOEH
Il_
-...
I-I-I-I- I-I
_w.
InIUllYIlu.
INTWI
INTW2
0
0
0
0
Refresh wait control register
(RWCR)
OOOFH
... I ..-... I """"... I
tI1WI
Number 01_ SIll.
Z
INTWO
0
0
,
4
1
0
0
1
0
-
.. -I
_v_
-I......
RoW
RIII,..hW.t
IIEI'W2
REFWI
0
0
0
0
0
Number 01 Wall S.....
REFWO
0
0
1
0
1
0
0
0
0
Interrupt Control
Register
Address
Interrupt status register 0 (lSRO) OOlOH
Remarks
---
7
5
3
2
R
•
R
•
I
tSc'J'B?1¥8W
1. _ _
0--...1'lII,,-
R
x
•
I
,,-JIIDlIIIL..
O:"'rdllMd
I
JII:1JlIBIL
1' _ _
0:.,.....l'1li.....
__I
ExterMII _ _ iNTi
,,
0: ..............
1'__ 1'__ 1.__ 1.__
""""BYP'Y
O:RlqulMnd:1IUd
•
J8l8DIL..
O:RIq&IIIInalllud
lIIlBIIIlf...
tt .......... 1Iud
E!ttrM! """"'"iffi
O: . . . IIi .....
HITACHI
Hitachi America, ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
671
HD64180S
• Built-in Registers (cont.)
Interrupt Control
Register
Address
Interrupt status register 1 (ISRl) OOl1H
Remarks
BIt NetM
I
T1IRQ
..........
TOIRQ
OM.'
DMlAt
R
R
R
InitiaJyak.te
I
DMAlnterrupCB
~
O"R«luHlnocil,1HId
t:R.qutlllnuM
1
MQltCSIO Txta
I
O:Requntnol"
1: R«tUUt _ _
.ygrqpRXINT
Interrupt enable register 0
(JERO)
OO12H
e
..........
'"""v....
""""VIE
1:Rec!Udtia.
5
"'-
TX""'"
..
3
2
AX""'"
1H11E
a
•
~
~
O:DiIII:Md
1: EnabItd
l:Enllbled
ASCIfCSIO RXRDV
E_
ge
0: DiMbItd
0: DIMbIed
l:EMbIed
MSaRXfIT
1. EI\DIed
0013H
1:ReqUHtbl,*,
1 1 1 1_1_1
~,.,..,'!1!!lDY
Interrupt enable register I
(JERI)
0: ReqUMI nDllnuecl
0: AaQuMt not!lewd ,. A.qUtlIt Inued
- - - - - - -I -
BIt ...... IllCRDY1E
'\
0: AlqIMll no! IMued
---
T11RQE
..........
InIiIIVaIw
TOIRQE
CM181E
~1l!R!!V
iffi_
1: Enabled
lE_
"'- "'-
........ E_
r.1-
0: DINbIId
1: EntbItd
l:EnIIbIed
OMIA1E
DMIBOE
DMIAOE
ANI
ANI
ANI
Trffi_
~
0: IlINf*d
•
........ 1 1 1 1
1NT1E
1
•
TXlNT1E
AXINT1E
ANI
ANI
1 1 1
•
0
I
ASCJ:.IO
TImer Channel 1
~Enllbl'
AXINTEnlble
0: DIMtMd
~
1: Enabl4lcl
1: Enlbied
Interrupt vector low register (IL) OO14H
BltMI.rN
I
IL8
IL7
~~--~--~--~--~~~--~--~
I
Fixlldccd.
I
Low ord.r byt. of veetor Iddreu
$
672
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Built-in Registers (cont.)
Interrupt Control
Register
Address
Unused
OO15H
OO16H
Unused
0017H
Unused
RemarJ(s
Refresh Control
Register
Address
Refresh control register (RCR)
OO18H
Remarks
•• _1
1- I - I - I -
FEFE
cvca
C"f'CO
CYC1
Inlbal Valu.
~
o· Ratr..h cvcIIl not In•• rted
9l!!!!.!!!!!!!
·InMl'llotllnteNal
000:3211:_
001:14"....
010: . . . . . .
,- R.fr••h cycles In.arted
011:128 .....
100"10". . .
101. 192stldu
110:224 . ..
111: 258 . . .t
Unused
Unused
Unused
OO19H
OOIAH
OOlBH
Bus Control
Register
Address
DMA priority control register
(PCR)
OOICH
Remarks
•
SlngIHloc:lcTrMIfw
Mode (duallddrMI)
-
SIrIg"'bIoekTran.fat
Mode (alngle IIddreelI
.....
-.
-
-
-
-
•
1
-
-
•
...,
ChalnItd·bIodt TfW\Ster
lnitiaiVaIu,
~
0: ChMMIO huprlolMy CWM'char'IMI 1
1: ChIMtl' hu priorty _ChaMtI 0
DMA master enable register
OOlDH
Single-block Transfer
Mod. (dual address)
(DMER)
Single-block Transfer
Mod. (Single address)
DME
Chained-block Transfer
Mod.
RaadM'rHe
RIW
Inl\lal Value
I
OMA Master·Enable
~
0 Disable
1
'$'HITACHI eoo.'.
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
673
HD64180S
• Built-in Registers (cont.)
Bus Control
Register
Unused
Unused
Address
OOlEH
OOlFH
Remarks
MSCI
Register
MSCI TX/RX buffer register
Address
0020H
Remarks
(MTRB)
initial Value
I
VallIt written to, or read '10m, the trtln,",lU~
MSCI status register 0 (MSTO)
buff.,
0021H
'~J'
~
TXINTlnlirrupt
0: Tr..... mllbutf.rfuU
o Nolnterrupt
1 Interrupt
" Tr.,amlt buffer
.mptylnOlfull
~
~
O' No race"'- data
O' Nolntlrrupt
1 InltrrupC
MSCI status register 1 (MSTl)
1: ReoerwdMII
0022H
fWI/
PIW
R/W
FVN
°_ 2 . o_~
\F1!o_
WW
°
• f¥Mo.ynchlo,.,..moa
~
o1. No
......._
n~
P.uem
_ lid
ONDI~
1 CMrqed
I
~
• Aayncl'll'Ol'lOl.llrnode
o SreMMqUlH'lCllencfnoldttected
1 Brnk ~nce end delact«l
• BIt .ynchronDUl moeN
O' Notltlgd.wotecl
'''''''-
Tr,nan"llhr. Statu.
~
:t
ldle
IdIe$Carto.tlldlon
·an~mocM
~lntlty!!
0,: ~
--ow-
o
Idle Hquenc, ••rt no!
~
1 kIM .....nc. . ." detect.d
BrHkDelK1lon
~modII
O· ..... ~ lltarlallOt",*=l*i
" Break ...~"'" d-.oted
AbcMt OetctlonoGA p.ftettl o.t.cdon
·8It.ync~modII
0:
-
AOCMt....-.MaI'I/OA~m
""-
••1t
I AboItNqL/el'lC4lul1lGA-.,.,..,.
~HITACHI
674
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD64180S
• Built-in Registers (cont.)
MSCI
Register
Address
MSCI status register 2 (MST2)
0023H
Remarks
Initial Valua
0
~~ I'~--
r-'
End of ReoIfw F,.me
• BllI)'ndvollCMlS mod.
0: .-.IWfrItlMMCI
._""-.
1 End of
0: Noframlng amw
0 No CAe emwdM«Hd
1 CRC.rn:w~
dMIc:Ud
Nell"'" frame
1: FIWnIng-.or
~Errot
dItIIcHd
_
~~
~: =:.enw~1Cted
Parity..,. Bk
• Alyncl'lronoul mode
o· p.tyorMPbM:"O"
1 PllrlYotMPbI:","
O'NormIIItltldd
"",F_
1: FralMvdhreelduebltll
.-
.... .
·iii.,..,..
.... ..0: NannIIenddhmf
1: ShortframedNctld
MSCI status register 3 (MST3)
_
0024H
...
R
lnll'-lVu..
~~"""'L,..I. . .
--
~.~::,=:;::, o.
1: TranlmllsMSCldIIta
•
1:
~1l.
I
~
0: Diubit
CiiMbwllYti
1. En'"
CTSMhIgh ......
I
AXE..0;0
___
synchronout mod.
O. AOPLL nonn.t mode
1 Enabll
1 ADPLLaNfd'trnode
5C"iitlnpytLm.St.us
0: DCDM bwllvtl
1 '6Ci5Mhighlwel
MSCI frame status register
0025H
(MFST)
ftudIWrlte
InltialVPie
•
AM'
AM'
!WI
RM
MY
PIN
---------,,----------
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589·8300
675
HD64180S
• Built-in Registers (cont.)
MSCI
Register
Address
Remarks
MSCI interrupt enable register 0 0026H
(MIEO)
Inilial Valu.
o
0
0
0
,--J
~
E"....
D.O....
TXINTlnt.rrupl
~
,.-lJ
,E_
00_
1 Enable
""AD
'"',.."
Enable
0ll0_
1 Enable
MSCI interrupt enable register 1 0027H
-
Atync
(MIEl)
-
IDLE
UDAE
HJI.C
: SV1CDE
......
fWI
fWI
-
CDCDE
CCTSE
-
ABTOE!
GAPDE
RGOE
-"'"
_EE
BRIQJE
Byt. Sync
fWI
IOLOE
fWI
InItIalV.lu.
0
~
IDllnte!!!!2! En!!!l!!
QgTS InhI!!l!e! Enable
BRKO Interrupt Enable
O;DlaabI.
o.OIuble
,E_
o Dltable
1'Enab\II
• Asynchronous modo
1 Enable
UDRNlnI!rrUp!EnetlM
• BylelBlt I)'nchronou. mod.
O:Dllabi'
, E......
SYNCDlnI!mIpIEnabi'
ASTOIGAPD Interrupt
Enlble
• 811synchronoul mod.
O.DII~
"Enab18
• ByI. aynchronow mod.
0:0....
1:En.tJle
coco lnt.rrupC Enable
BAKE Interrupt Enable
FlGD Int.rnml Enab'"
0: Draable
1. Enable
• Asyt\chronoua mod.
o Dltable
, E.....
• BII • .,nchrotlOUI mod.
O:OIIab1e
fDLD Interryp! Enabl.
1 Enable
• Bllayncflronoul mod.
O.OIubl.
'I'Enable
MSCI interrupt enable register 2 0028H
(MIE2)
At,..
-
PMPE
PEE
fIlM..
-
-
-
EOME
SHATE
ABTE
RBITE
0
0
8)'f11 Sync
Bit Sync
~
OYANE
CReEE
fWI
InIllalV"
-~-I
-
I
I
CReE Inletrufll Enabi.
• BytftJbJt synchronous mod•
• B' .''''''....... mod.
o.~
0: DIubIe
1: Enable
1: En""
CVAN Interrupt Enable
PMP Interrupl Enabkt
O:Drtable
" Enable
• AsynchronoU8 mod.
0'''''''''''
1. Enable
SHRT Interrupt Enlble
• BII aynchronoul mode
0: DiNbIt
"Enable
FAME Interrupt Enable
PE Interrupt Enable
• Asynctuormus mode
• Asynchronoul mode
O'DIsabIe
1, Enable
RBIT Interru~ Enable
AST Interrupt Enable
• 811 synchronous mOde
$HITACHI
676
-
o Ollabtt
0, DiNbr.
l' Enablt
• BlIsynchronoul mode
o Disable
" Enable
" Enable
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Built-in Registers (cont.)
MSCI
Register
MSCI frame intelTUpt enable
register (MFlE)
Address
0029H
Remarks
_v_
•
I
EOMF 1Rte;rrup! En8tN
·8Ill:yflChroncKllmocM
0: DIMb/III
1: EMbII
MSCI command register
(MCMO)
002AH
• T.....,..IlCornmMdl
000001: TXmIt
000010: TX ......
000011: TX dubIe
000100: TXCACInItIaIIudon
000101: ElDCkItbnfromlX
CAC_
000110: Endof~
000111: Abort tranemlulon
001000' . . tilton
001001: TXbuflerdNr
0Ih1l'l: ,....,.
.-~
010001:
AX,....
010010. AX""
010011: R)(dlalble
010100: RXCRCInIlildullon
0101Dl·~r.lect
010110: SearctlMPbIt
• OIhosync rnoa.
010 Byte-.ync,
....,""..-
01 ,. Byte'lync. Extlrnal
synct\n:lnoul!TICMHI
100 81l·IYnc, H01.e mod,
101 BIl"ync, Loop mode
HD R, ••rved
,,, R•••rved '
CRe Ca/cUlalon Coda
• By1elBlt synchronous
..o DISable
t,
EnabNI
0
I
~A'lve:!;r:'!!, mode
n,,,
00
01 15blta
10 2bltl
11 Reserved
CACCllIculatlOfl_
Expr"'ion and
!m!!!L.Y!!!!L
• ByteJBrt synchronous mod.
OX CAe·'S
IX: CRC-CCITT
XO Inl1181 value. atl 0$
Xl Inettalvalua .. a1I,.
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
677
HD64180S
• Built-in Registers (cont.)
MSCI
Register
Address
MSCI mode register 1 (MMDl) 002CH
Remarks
r-=r-
Initial Value
0
0
0
0
0
0
0
-l;L.AA!
=.0)...•" ]
.B!1..BIlt
0
• Asynchronous mode
• Asynchronous mode
00 '" ctOCll. rate
01 1116 clock rate
00 8 bIIsJcharacler
01 7 bltslcharacler
10 6bllsfcharactaf
• Asynel'lronous mOde
00 No parrtylMP bit
01 MP bit apptndld
(byoommand)
10 1132clOckr.t.
I' 5b1ts/character
10 Evenpantyappendedand
,,
eh«:ked
11 Odd panty appended and
checked
1164 clock r.,.
Ad4rM!l Flak! CbtcI\
Receive Character
• Bit synchronous mode
l:!.ns!h
10: SIl~I. address 2'
01
: ::::~:s~~~:;~-Check
~oAs~n~:;~:~:::rd.
11 Oua' addr.*,
7 brtslcharactar
10 6 bltslcharaClar
11
5 brtslci'laractaf
MSCI mode register. 2 (MMD2) 002DH
FVvV
ReadlWrlte
'oil",
AIW
FVvV
RIW
AIN
R,W
AIN
v":~"~lg~ s,'., 0 I 0 ~o0 0 ;;'~:':'d':;;'''''"
.-
synchronous
TransmISsIOn Coda
mode!1.e!
o NRZ
communicatIOns
01 Aulo echo
• BytelBll syncnronous
mode
1 FM
10 Reserved
11
Local loop back
00 NRZ
~~ =~Ved
ADen Optrllhng ClgcMN Ratt
11 Aeserved
o FM
00 Manchester
01 FMl
10 FMC
"
Reserved
MSCI control register (MCTL)
• Byte/BII synchronous mode
00 lIS
01 )(16
10 x32
1 I Aeserved
002EH
ReacIJWrlte
RIN
Initial Value
0
Pm
PIN
ANI
RIW
~
TXR!adyStateCont!gl
o
TXADY bII goet 10 1
wMnth.'rMlll'lftbuffel'II
""'"
1. TXADY bit goes to 1 when
the tranlll'lil bullar II not lun
~
• Aaynchronolll
modo
o· Off
" On (break lencl)
RIW
PIN
o
,
~~
o Ffi'SMllneal
low_
1 BTSMllna-'
high level
IdleS!ateConlrol
• ByteJBlt synchronous mode
O. Tranamitla milk
Go Actlye on Po.
, Transmltlan Idle pattern
O' 0iI1bIe
• BlltYftChronoul
"""modo
'0_
Unclamm Stete Comrol
SYNCttaractar
• Byte I}'11ChI'Of'lOUI mode
o En'.,.. Idle stllte immediately
1 Entars Idle stat. after CAe .,ansmitaion
• Bit synchronoul mod.
0' Enters Idle Ilata att.r aborting transmISSion
1 Enters KlI.ltat. after FCS and flag transmilllOll
~
• Byte Iync mode
o· Disable
" Entbla
~HITACHI
678
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane! CA 94005-1819 • (415) 589-8300
HD64180S
• Built-in Registers (cont.)
MSCI
Register
MSCI synchronous/address
register 0 (MSAO)
Address
Remarks
002FH
Initial Valu.
• ByI. synchronous modtl
SYN attam for ree.
BI-Iync
•
B~
SYN anar" for Ir'lIIImililon and
'Ynchronoul mode
Addr ••,lialel
HOt.C
mod.
....,
not enllCkeel
UnuMd
511'1D1. addr... 1
BIIa 7...(1 of 1h. HOOMarv station ..sur...
Single eddr... 2
UnuHd
Dual addr...
BIt, 7-0 01 thl MCOndary atatlon MSdr...
Addr.,.lIalel not ch.ckMi
UnlolMd
Singia addr... 1
Blta 7-0 01 tha MCDl'Idaty
4·blt Ilddr...
Bits 7-"' 01 1M secondary alation Mdr...
Dual_dl...
Bits 1-0 of In. NCOndary atatlon Mklr...
mod.
MSCI synchronous/address
register 1 (MSAl)
Ion bIt,7-o
It." addr...
0030H
InftlalValua
SYN Pansrn for Tr'nlm"llOnlAddr... Field Chec:k
• Byte synchronous mods
Mono·sync
SYN
BI·sync
SYN attarnlortranamilsion.ndrec
.rn br Ifananulsion
• BII II)'nchronous mod.
Add..... "aid no! checktd
HCLC
mod.
....,
mod.
MSCI idle pattern register
Stngleaddrnal
ion
11115-8
U,_
U,_
Single ackIr... 2
Bit_ 15-8 of 1M MCOnd.ry It.ion addr...
DY&laddr•••
Itt. 15-8 of tha a.candaty .lIttOn IIddr...
Add..... II.1eI not cntdctd
Unualld
SIngle addr••, 1
U,_
4-bltaddrn,
UnuMd
Duat add .....
arts ,5-a 01 the! ucondary ltatlOn add,."
0031H
(MIDL)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
679
HD64180S
• Built-in Registers (cont.)
MSCI
Register
MSCI time constant register
Remarks
Address
0032H
(MTMC)
MSCI RX clock source register 0033H
(MRXS)
• •
_.!IOdC ......
.... .......
.,.".
file.,..,.,
010: RXCM ".Input(noIII tuppNlllon)
100 _
IntemallMud
(lAG)
autput
_ "'ADf'U _
_
11O:ADPLL~
~a.udR!t!
·CIDdc...,.,.uo
0000.111
0001 1/2
0010.114
OOt1' 118
't1.ADPU.~
(RI(CII .......... - . . _ _
Otht,.: ........
0100.1118
0101 1132
0110' 1184
0111 111.
1000:111.
1001 '"12
01. .: AIMfved
MSCI TX clock source register 0034H
(MTXS)
_v_
r,,·mt8ew!_
• ClDdcdlvillonrlllo
ooao: 111
0001 1/2
0010 114
OD11: til
0100.1118
0101: , .
0110 ,.0111: 11128
1000: 11lS8
1001' '1112
0Ihe0a,
_
Unused
Unused
Unused
003SH
0036H
0037H
•
680
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Built-in Registers (cont.)
ASCIICSIO
Register
ASCI TX/RX buffer register
Address
0038H
(TRB)
Remarks
_
""'"
1::.... 1~lna I
_..... "'"
"'"
"'"
.....
"""" I~
fWI
I>W
"'"
I>W
x
I
T'.n.."ItIFI~IV. buffer
ASCI status register 0
I"""
TFIIO
I>W
value
0039H
(STO)
-
o
InltiaiValue~
~
It TXitUm.lpl.not
R..'"~
I
AXINT 'nt!!!!l!
.!!l!.-.
0: RXlnlerruplnotreqUltlted
1 AX inlerrupl Nqu_td
O· R«lelvedUdoeinot
1: TXIntarrupI
ASCI status register 1
" Rec»W dItII uittl
"'-
~
0: TranIft'IlbuIfer
1. Tranamltbuff.,
......
003AH
....,
1 c= I
(STl)
R
Inillal Value
0
0
~
Trantmllterklkt&tte
o TXnocldle
fWI
fWI
"'"
.~~ irk.~~
1. arNk tnd detected
l' U". !Iv.! changad
1: TXId..
fWI
oc:oA LIne LweI Chanp!
o lint lwei not changed
1 Line!tnl changed
0!I!cl!0n
....................
o. ar_swtnotdtt.ct41d
Break StIl1
1 arellkttartct.tected
ASCI status register 2
003BH
1-1~_.,_nc_
.._....--tl -
(ST2)
InlllalYaIue
PMP
"'"
PE
fWI
AIW
fWI
I O~OlJl
I!ooIIiIIIUi
partylMP bit value
o· ParltyIMP bit value 0
1. ParltylMP bit value 1
0
~
0
0 No owrrun efl'Of delllCt«l
1 OYert'un error delec:ted
Framing Error
O. No Iramu'lg fN'ror d8hld1d
1 FratlurIg errordetllCted
~
o No p&nly errcr deteG1ed
" Pertty.rrord.tecttd
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
681
HD64180S
• Built-in Registers (cont.)
ASCI!CSIO
Register
ASCI status register 3
Address
Remarks
003CH
ClS
(STI)
x
-
o
I
I
CTSA Inpulloine Level
o. Ci'SA Ilna low level
1
TX Enable
~
em liM high t.ve'
, Enable
DCi5A Input une Le""
RX Enable
~
0: ~~rMllowlevei
1 OCDA I.,. high r.veI
Unused
1 Enable
003DH
ASCI interrupt enable register 0 003EH
(lEO)
7
~A_'Y_"'_ _-II
~Iock.d Serial.
•
TX'NTE
I ~'NTE I
_
R!N
'M'., V.,,,
•
R!N
AIW
0
~
I
TXINT Interrupt Enable
o Disable
1 Enable
R!N
~o
TXROY Interrupt Enable
o Disable
, Enable
RXINT Interrupt Enable
o
D~abl.
1 Enable
RXRDY Inhlrrupt Enable
Disable
IE_
o
ASCI interrupt enable register I 003FH
(lEI)
I
A.yn,
Clocked Set/a!
3
1•
RudJWrlle
R!N
R!N
o
Inilla! Value
lOt. Interrupt Enable
0, DlUbt.
, Enable
0
~
eeTS
Enable
ODlUble
1. Enable
2
1
r
R!N
R!N
0
0
0
AIW
In,,!,,"
BAKO
Enable
• Asynchrol'lOUI
ITIOdI
o Dt,ablt!
, Enable
00_
COCO Interrupt Enable
1:
En..
BRKe Interrupt Enable
• Alyncl'lronoul
..-
o oiallb1e
1. Enlble
.HITACHI
682
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Built-in Registers (cont.)
ASCIICSIO
Register
Address
ASCI intelTUpt enable register 2 0040H
Remarks
(IE2)
InllilllYaIue
PMP lnItn'upt EntbI!
0: DINbIt
OVRNInt!f!UFll;E....
O. """'"
,'e.-
t:En'"
PElnI!rNpIE!!I!tH
0''''1: Enable
Unused
OO41H
ASCI command register
0042H
(CMD)
w
w
w
w
....!.....
·Tl'II'IVftlcornm'"
• ReceNeOOlM'lMClI
000001. TX,.-
010001: AX,...
001)010' 1)( . . . .
010010. AX ......
000011. TXdilable
010011' RXdIMbIe
001000' MPbM:on
010110: Search MP til
w
w
."""'...........
t::hMMI .....
100001:
000000' No ....1IiCNI
0IhM: AMervect
001001: TXbuhrdHr
ASCI mode register 0
0043H
(MOO)
-r
!I!!e..!!!.!.!!
• Alynchronou, modi
000: AsyncfwonouI moct.
110: aodIed..talmodt
OttMrv.luel . . ....erv.d
ASCI mode register 1
00: 1M
10: 2'*
• aocMd .....
........
0044H
~
(MOl)
_
_
RIW
IW/
_
IW/
I!..!!!!!
• AtynchI'OnCM modi!
00: 1notcbd!.rllle
01: 1/18ofclock,...
10: 1lJ2ofdockrat.
."""'""_ .....
1,:1I14ofclDck ....
TheM bIIt ItIouIdbe .. 1O 00•
•
HITACHI
Hitachi America, Ltd, • Hitachi PlllZa • 2000 Sierra Point Pkwy. , Brisbane, CA 94005-1819 • (415) 589-8300
683
HD64180S
• Built-in Registers (cont.)
ASCI/CSIO
Register
ASCI mode register 2
Address
0045H
(M02)
Remarks
_
I=--... I - I -
1
I-
I-
1 -
I~I~I
..,. ..,.
""""v_
0
0
T
~!!~!2!!
00' FulidupItx
01: AI.rto«:ho
10: RenrvecI
11:L.ocaI~
ASCI control register
0046H
(CTL)
I=-- I
-
-...
In/WVaJu.
-
I-
-
I-..,. - I I..,.
-
_....I
0
· _. . . modo
O' 011 (NcItJMI oper*lon)
l' On (B........nd)
• Clocked HriaI mode
SIIthltbictoO
Unused
Unused
Unused
RIS
~
O:miAlDw",",
.""""
I, IIT§A""" .....
output
0047H
0048H
0049H
.HITACHI
684
Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Built-in Registers (cont.)
ASCIICSIO
Register
Address
ASCI time constant register
004AH
Remarks
(TMC)
InltialVaJua
RIlla:! Tlmar Vliua (I -251)
ASCI RX clock source register
004BH
(RXS)
_
I::.... ,~
•
1
-
,
•
1AXCS21 AXCS' 1 AXCOO 1
RNI
initial Value
RNI
1
-
-
1-
RNI
0
I
R.celve Clook Soum.
AX MutarlSlwe Mode Stled
CIoc:kedMrllllmodli
• "*ynchrol1CH.lI mod.
o
000 RXCAUnelnput
000 SlaWmocMI
100 Inlamsl baud
fa gln.rmor
100 MalhlfmocM
(BAGl_
OlheN'
R~
Otha" Ae..rved
ASCI TX clock source register
004CH
(TXS)
•
•
I~cs21 ~cs, mso I~e
I::.s..._... I
"'" "'"
-
5
1
RNI
RNI
3
,
2
1 ~-I =-,
RNI
I I
0
nBRO
RNI
RIW
lnillalVa"'"
C~
Transmll
SoUraI
• Asynduoooul mode
000 TXCA1Inelnpu1
100: tntamalbaudrate
_IBAG)
.......
Othars Renrved
Unused
004DH
Unused
004EH
Unused
004FH
I
I
TX MasterlSlave Mod. S.lecc
• CIoc:kodu".,1 mode
000 Siavamoct.
100 Mutar mod.
Others. R...rved
eaudRate
• Clock dlYlSionratD
0000 111 0101 1.132
0001 1/2 OlIO 1/64
0010 1/4 0111 11128
0011 118 1000 11256
01001116 1001
'1512
OtMr. ReMlVeci
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
685
HD64180S
• Built-in Registers (cont.)
Timer (channel 0)
Register
TImer up-counter channel 0
(TCNT channel 0)
Address
Remarks
0050H
ReIdWrItI
ANI
FVN
MY
MY
MY
MY
MY
MY
W
W
W
W
W
W
W
W
COIF
EOMI
-
TME
rOS1
TOSO
""'"
CKSO
MY
RIN
AIW
AIW
RIN
0
0
•
tnilla/Value
TImer constant register
channel 0 (TCONR channel 0)
0051H
RudIW...
InlllalVaJul
TImer controVstatus register
channel 0 (TCSR channel 0)
0052H
IMN_I
-".
I
MY
Inlllt;IValu.
I~
~
1:Countltaft
o. TCNTMdTCXlNR
....
..""
noI~ual
1 TCNT and TOONR
.,.
CMFlnt.rruptEnabie
0053H
....... 1 ..pl-
aurtllgNII
ThMr Output Se'-d
10' OUtput 0
II' OutpUll
I-
I-
ECKS2
AIW
EnableExp!tldPrllCa1er
00 8C
01; 8CIe
10:BClI28
11: External event
00' OUtploC tlx~ to 0
01. Toggled output
O' DlMbIe
I:EMIM
TImer expand prescale register
channel 0 (TEPR channel 0)
I
Input ClodtS.lect
TIrn"'E~
9:s!me!re Match FlIlJ
*
O. CIi:x:K "Mlected by the CKSl-o
in TCSR
1: Clock " MIecUd bV the ECKS2-0 bit. In TEPR
I
ECKSI
I
AMI
I
AMI
expand Clock Input Select
OOO.8C
00I'BC/2
Ola'BC!"
O",BC18
100:80116
101 8Cl32
110: BCI64
111'001128
~HITACHI
686
ECKSO
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Built-in Registers (cont.)
Timer (channell)
Register
Timer up-counter channel 1
(TCNT channell)
Address
Remarks
0054H
Raad/Wrlte
RIN
PIN
w
w
QIF
EC,",I
Inlll,IV,Iua
Timer constant register
channell (TCONR channell)
0055H
ReadlWrlt.
w
w
w
w
w
ThE
lOS1
TOSO
OKS,
Cl<$0
PIN
FWI
FVW
AIW
w
Inlll.IV.~
Timer controVstatus register
channell (TCSR channell)
0056H
Bit HaIM
I
ReadlWriI.
I -
FVW
Inlll'IValua
compare Mtteh F1!p
o TeNT andTCONR
.ra not equal
, TCNT andTCONR
:ml=TO
InputCIoc;t(S4IIec:t
0
OOBC
0, 8CII
1 Countaten
10.8Cf128
11' Extemal IlIlnt
counlslgnal
.,.equal
CMF Intarrupt Enlbla
o Dlaabkl
1 Enabte
Timer expand prescale register
channell (TEPR channell)
0057H
Tlm.r Output Seltel.
00 OUtput Ilxed to 0
01 T.ledoutput
10 OUtput 0
11 Output 1
h~m·IL-E_EP~I__-__~__~____~__-L_E_C~
__2LI_E_~_S_'LI__EC_~_oJI
ReadlWnte
RIW
RIN
PIW
PIW
InltlalValul
Enable Expand PI.seaIer
e.pand Clock Input Select
o Clock IS ..!ectad by the CK$I·0 tlda In TCSA
1 Clock IS ..Iected by the ECKS2..o bits In TEPR
000 BC
00, BCJ2
0108CJ4
011 BCJ8
100 BCI1e
101 BCl32
110 BCf64
111 BCl128
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
687
HD64180S
• Built-in Registers (cont.)
DMAC (channel 0)
Register
Destination address register
Address
0058H
Remarks
nn BIIII T1111111
H TIIIIlI@
23
L channel O/buffer address
register L channel 0
(DARL channel 0/
BARL channel 0)
:
8 7
:
:
SIngIHIIock Ir_t" mod,
(dwII-'dMiI
Single-block Irantl., mode
U""...
~
u......
B_
(........._>
--
Chalned-bb:k trlnIf.r
Destination address register
115 15
0059H
.....
.....
0
:
0AAl
BAAl
H channel O/buffer address
register H channel 0
(DARH channel 0/
BARH channel 0)
Destination address register
005AH
B channel O/buffer address
register B channel 0
(DARB channel 0/
BARB channel 0)
Source address register
nn"IIII IIIIIII TII IIl~
005BH
23
L channel 0 (SARL channel 0)
16 15
8 7
:
Source address register
005CH
: :
Singla-block tran,'er mode
(dual address)
Slngle·block Ir.nsfar mode
H channel 0 (SARH channel 0)
Source address register
0
H
(Single
Unused
SARB
SARH
Unused
CPS
Unused
.....
add,.ss)
Charned-block I,ans'.r
mode
UnuMd
005DH
B channel O/chain pointer base
channel 0 (SARB channel 0/
CPB channel 0)
~HITACHI
688
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD64180S
• Built-in Registers (cont.)
DMAC (channel 0)
Register
Current descriptor address
register L channel 0
(COAL channel 0)
Address
Remarks
oo5EH
6J]H fill TIIIILITa
15
•
7
0
:
:
:
UnuHd
CUlTent descriptor address
register H channel 0
(COAH channel 0)
U",'"
oo5FH
FmH .. Lm4
Error descriptor address register OO6OH
1
L channel 0 (EDAL channel 0)
-----
Error descriptor address register oo61H
H channel 0 (EDAH channel 0)
8 7
:
I--l
oo62H
Receive buffer length H
channel 0 (BFLH channel 0)
oo63H
:
U......
UnulNd
EDAM
EDAL
I_-l
Chalned-bkd1r.....,
mod.
Receive buffer length L
channel 0 (BFLL channel 0)
0
IIII IIII
H T LITa
6TI
~IIII'IIII~
16
8
:
7
0
:
:
SIng..-bIock lfanlftr mode
Cd... .,..)
~tran_mocI.
........-
u""",,
U......
U......
Un....
IlfLL
I.............l
.. MOeI
IWIIfer mode MSCI tD memory
IlFLH
Byte count register L channel 0 oo64H
(BCRL channel 0)
SII'IQItI-bIoc:k "enll" mode
Byte count register H channel 0 oo65H
(BCRH channel 0)
Unused
Unused
!
(ml add,..,)
Slngl,·bIock InlnIfer mod,
(Single add,..,)
Ch..ne6-blocktrantl.,
-
oo66H
oo67H
•
IICA<
;
--
HITACHI
Hltaohl America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
689
HD64180S
• Built-in Registers (cont.)
DMAC (channel 0)
Register
DMA status register channel 0
(DSR channel 0)
Address
0068H
Remarks
S~HIbdlIrMlf"
-
-
-
EOM
80F
ss
register L channell
(CDAL channell)
0076H
1615
8
7
0
:
'
:
Slngle-blocktransf.rmode
Source address register
0074H
H channell (SARH channell)
Source address register
B channel 1Ichain pointer base
channel 1 (SARB channel 11
CPB channell)
l
T "
Lern
~IIII~IIIIIII,IIII~
23
Unused
s_
SARH
SARL
Unused
CPS
Unused
U",...
Ern"
T LTI1J
~IIII;IIII~
a
15
7
0
Single-block translar mode
(dualaddrass)
Current descriptor address
register H channel I
(CDAH channell)
Single-block ,rans'., mod.
0077H
Chained·bIockt,an,'.r
mod.
•
692
Unuhd
U,.....
COAH
COAL
(slngl••ddress)
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
HD64180S
• Built-in Registers (cont.)
DMAC (channell)
Address
Register
Error descriptor address register 0078H
L channell (EDAL channell)
Remarks
Fm"IIIIl IIIILm4
15
•
1
7
0
i
•
Error descriptor address register 0079H
H channell (EDAH channell)
u......
eOAL
Receive buffer length L
channell (BFlL channell)
007AH
Receive buffer length
H channell (BFLH channell)
007BH
Ern"
T LI@
~IIII:IIII~
15
• 7
0
Single-bloc:k translet moM
..
""...........
Idual.tdr"'l
,.....
UnuHd
U.....
.. MSCt
trMlf.rmodl MSCltomernctIY
U._
8f1.H
u.....
SlngIHlock transfer I'I'IOdt
." )
Byte count register L channell 007CH
(BCRL channell)
BFU.
Ern" 1111 TIIIILI@
1$
II
Unused
Unused
007EH
007FH
DMA status register channell
(DSR channell)
0080H
Slngle-block "Inlf.t mod.
(duI' address)
:
!
SIngI.·bIock Iran.... mod.
(• .,tVltacld,...)
""'"
--
Chalned·bIock Iransf.r
Slngla-blocktrans'.f
mode (dual.cldfMI'
SlnQla-bJocll. 1rMsf.,
mode (alngll ..tdreu'
0
:
:
Byte count register H channell 007DH
(BCRH channell)
7
-
-
-
EOM
BClf
rot'
EaT
--
Chalned·bIodc If.net'r
BCR.
-
-
DE
DINE
_
o
0
Initlalv.lue
~
I
~
O'T,.".,.,notczmpletecl
1: Tranal., CDmPIeted
W
o
I
~
·CNil*l-blocklrlnlfer
~
0:01....
0: Error notdetected
1: EnorcltltcUd
1:EMbIe
Butr" CMrrlowNndeffIow
DE BIIWfMe En!bl!
• ChUMd block treMf...
O' Error not deICed
1:Elftlfdettct.d
O'EneIM
1:DIIaIMe
End of Fram. TraMler
• Chalntd-blocktranef.,
u.n""
o Frame
not compll1ed
1: Frame trMtI., compIIted
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
693
HD64180S
• Built-in Registers (cont.)
DMAC (channell)
Register
Address
DMA mode register A channell 0081H
Remarks
SJngI.-bIock Irantl.r
mod. (dull add,..,)
(DMRA channell)
Slngle-blocktt,nlfer
fI'IOd.(llngllllddml)
-
-
RSEll
....LO
N.IOD
r---
-
RT
I--
Th clock)
• Low power operation
• Four operatIon modes (HD643l80X and HD647l80X)
-Mode 0: single-chIp mode
-Mode 1: expanded mode (Internal ROM disabled)
-Mode 2: expanded mode (mternal ROM enabled)
-Mode 3: PROM programmIOg mode (HD647l80X only)
• Internal ROM data protect functIOn (HD647180X only)
• Packages
-SO-pm quad flat package
-84-pin plastIC leaded ChIP carner
-90-pm dual inime package
• BLOCK DIAGRAM
The HD647l80X combmes a hIgh-performance CPU core WIth
many of the systems and 110 resources reqUIred by a broad
range of applIcatIOn, (figure 2).
The CPU core conSIsts of fIve functIOnal blocks
• Clock generator
• Bus state controller
• Interrupt controller
• Memory management umt (MMU)
• Central processIOg umt (CPU)
The Integrated 110 resources compnse the remaInIng four
functIonal blocb.
• DMA controller (DMAC two channels)
• Asynchronous senal commUnIcation Interface (ASCI: two
channels)
• Clocked ;enalllO port (CSIIO. one channel)
• Programmable reload tImer (PRT. two channels)
• Programmable tImer 2 (PT2· one channel)
• Analog comparator (SIX channels)
• 110 ports
The memory conSIsts of:
• RAM (512 bytes)
• PROM (16 kbyte). HD647180X
• Mask ROM (16 kbyte): HD643180X
~HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra Pomt Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
697
HD641180X, HD643180X, HD647180X
698
(FP-SOB)
(CP-84)
(DP-90S)
(CG-84)
• HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
•
Pin Assignment
Figure 1 shows a top view of the HD641180X, HD643180X and HD647180X packages. Table 1
shows the pin functions in the four modes.
~
S'.,'"
~"''''
~
"'N -
TNT
PE,
PCo
>C
"
PC,
>C,
V"
PC.
>C,
NC
PCe
PC,
"
PDo
;:;;;)~;;:il
:!'~~::!;':!:
;:F~'/PA'
o
!NT;
5RR'i1!PAs
CKS/PA,
10
.9
{;e
'fl
21
n
..
15
PD,
POl
PD.
PD~
66
.4
65
IC
",
",
TOUT2
CKAoi~
AXAo
TXAo
'0
PO
RXS/~/PA.
TXSiPAJ
CKA, tTrm5O/PA,
AXA,/PA,
TXA,iPAo
i'
'"
~a
Is
29
]0
"
'"
NC
~
CTSO
RTSO
ICP-84)
~=~ ~ 0
EXTAL
Vee
3
.
PBo
90
MP,
Vss
811
PB,
6
85
7
80'
P82
PBJ
1.'
'fENEi-,,'PA,
'"
!5RE1'f,/ PA 6
PE,
PEa
PEs
88
87
.
REm
•
83
PB.
NMI
INTo
9
82
PBs
PB,
CKS/PA,
:g~~6
10
~~~ ;~
79
NC
13
14
PB7
V"
11
lENCl/PA7
PE4
15
79
1Ji;fEQ'1/PA6
eo,
PCo
PC,
16
75
17
14
18
19
73
72
CKS/PAs
RXS/CTS,/PA4
TXS/PA3
CKA,iTENl:folPA2
70
69
RXA,/PA,
TXA,/PAo
Ie
INT,
INT2
pe2
pe3
vss
20
PC.
21
PCs
n
78
:g~~~T3
~~:~
::
25
66
TOUT2
PDo
85
CKAo/DAEOo
PO,
26
27
M
RXAo
P02
PC7
28
63
P03
29
82
TXAo
DCDo
PD4
30
POs
31
60
CfSo
RTSO
P06
32
59
ANs/PGs
P07
33
58
PEo
39
PEl
PE2
31
39
55
M
NC
AN3/PG3
AN2/PG2
53
AN,/PG,
TOUn
Vee
PEl
39
52
ANoIPGo
40
51
vss
41
50
VSS
42
49
PFo
PF,
43
48
..
41
PF4
PF2
45
48
PFJ
PC4
o
10
NC
II
PC.
n
PDo
25
PO
PD5
••
,S
.,
06
'"
64
63
"
60
30
PO,
RXS/m-;IPA4
TXSiPAJ
CKA"iENl5O/PA1
AXA,:PA,
TXA,;PAo
IC
NC
TOUn
TOUT2
CKAo.'iJi'ITQl,
RXAo
TXAo
'>8
DC1'fo
=0
'0
I"iiSo
"
PG,iAN,
~.
PG4IAN4
i~~~~~1i~f~£t£ii1~~~~
~
~~~~
ICG-84)
~~~~4/PG4
~~~ :
PF7
PFa
PFs
(DP-90S)
Note) NC: Not connected. Please leave the NC pins open.
Note) CG-84: HD647180X only
Figure 1. Pin Assignment
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra POint Pkwy. Brisbane, CA 94005-1819 • (415) 589-8300
699
HD641180X , HD643180X, HD647180X
-'
-'>-x
XW
Timing
Generator
I
IInterrupt I
Bus State Control
'I---:
I"---.
I
en
<0
I
J
I
TOUT2
IC
TOUT3
-.l
~(ChanneI1)1
ITWo
PAo/TXA,
~f'Jt~lfoA'
PA,/RXA,
lJ
~r:::-
L
)\
)j
Clocked
Serial 1/0
Port
I
l
l
PA3/TXS
~XS
PA5/CKS
P P
o 0
r r
t t
.QA
Figure 3. Block Diagram (HD641180X)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra POint Pkwy • Brisbane, CA 94005-1819 • (415) 589-8300
701
HD641180X, HD643180X, HD647180X
Table 1 Pin Function (HD643180X, HD647180X)
Pin No.
FP-SOS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
CG-84
DP-90S
CP-S4
10
11
12
13
14
15
16
17
18
19
20
21
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
44
45
46
47
48
49
50
51
52
9
10
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Operating
Model
Operating
Mode 0
NMI
INTo
INT,
INT,
-
-
PE.
ST
PCo
PC,
Ao
A,
PC,
A,
PC,
A,
Vss
PC.
-
A.
Operating
Mode 2
-
----
Operating
Mode 3
(HD6471 SOX
onlyl
A.
-
----
PC,
A,
PC,
As
PC,
A,
POD
AB
PO,
A9
A9/PO,
-
PO,
AlO
AlO/PO,
A,o
PO,
A"
A12
A ,,/PO,
All
PO.
A '2/PO.
A,2
PO,
A13
A ,3/PO,
A13
POs
A,.
A ,./PO s
A,.
PO,
A15
A,.IPO,
OE
PEo
A16
A ,./PEo
CE
PE,
A"
A,,/PE,
-
PE2
A'B
A,e/PE2
-
A,9
A,9/PE3
TOUT1
Vee
PE3
Vss
PFo
-
00
PF,
0,
PF2
O2
PF3
0,
PF.
O.
PF,
0
PF.
O.
PF,
07
Vss
PGoIANo
PG,/AN,
PG2/AN,
5
---
Ae/POo
--
----
As
--
00
0,
02
03
O.
0,
O.
0,
--
Notes: - Same as prevIous column
- No function
For the HD641180X pin function, please refer to table heading Operation Mode 1.
~HITACHI
702
Hitachi Amenca, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Table 1 Pin Function (HD643180X, HD647180X) (cont.)
Pin No.
-
Operating
Mode 1
Operating
Mode 0
FP-SOB CG-S4
CP-S4 DP-9OS
42
53
55
PGalAN3
43
54
PG.JAN.
58
44
59
55
PG&'ANs
45
60
RTSo
56
46
57
61
CTSo
47
62
OeOo
58
48
59
63
TXAo
49
64
RXAo
60
CKAalOREQo
50
61
65
51
TOUT2
62
66
52
67
TOUT3
63
53
69
IC
65
TXA,/PAo
54
66
70
RXA,/PA,
55
67
71
CKA,/TENOalPA2
56
68
72
57
TXS/PA3
73
69
RXS/CTS,/PA.
58
70
74
CKS/PAs
59
71
75
OREQ,/PAe
60
72
76
TENO,/PAr
61
73
77
62
74
78
PBr
63
75
81
PBe
64
76
82
PBs
77
83
PB.
65
PB3
78
84
66
67
79
85
PB2
PB,
68
80
86
81
87
PBo
69
70
82
88
Vss
71
83
89
cf>
MP,
84
72
90
1
73
2
MPo
2
XTAL
74
3
4
EXTAL
75
3
4
76
5
Vee
PEr
77
6
5
78
7
6
PEs
79
7
PEs
8
RESET
80
9
8
23
Vss
68
Vss
-
Operating
Mode 2
Operating
Mode 3
(HD6471 SOX
only)
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
--
HALT
REF
IOE
ME
E
LlR
WR
RO
+-
++++++++-
--
+-
-
-
-
-
-
+-
+-
+-
-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
+-
.....
+-
.....
.....
.....
.....
.....
.....
+-
+-
WAIT
BUSACK
BUS REO
+-
-
-
Vpp
++-
~HITACHI
Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
703
HD641180X, HD643180X, HD647180X
• CPU Architecture
The five CPU core functional blocks are described in this section.
Clock Generator
The clock generator generates the system clock (ep) from an external crystal or external clock input. Also, the system clock is programmably pre scaled to generate
timing for the on-chip I/O and system support devices.
Bus State Controller
The bus state controller performs all status/control bus activity. This includes external bus cycle wait state timing, RESET, DRAM refresh, and master DMA bus exchange. Generates 'dual-bus' control signals for compatibility with peripheral devices.
Interrupt Controller
The interrupts controller monitors and prioritizes the four external and eight internal
interrupt sources. A variety of interrupt response modes are programmable.
Memory Management Unit (MMU)
Maps the CPU 64-kbyte logical memory address space into a I-Mbyte physical
memory address space. The MMU organization preserves software object code compatibility while providing extended memory access and uses an efficient 'common
area- bank area' scheme. I/O accesses (64-kbyte I/O address space) bypass the
MMU.
Central Processing Unit (CPU)
The CPU is microcoded to implement an upward-compatible superset of the 8-bit
standard software instruction set. Many instructions require fewer clock cycles for
execution and seven new instructions are added.
Mode Selection
Mode program pins, MPo and MPI determine the operation mode of the LSI (table
4) .
• I/O Resources
DMA Controller (DMAC)
The two channel DMAC provides high speed memory to/from memory, memory
~HITACHI
704
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
to/from I/O, and memory to/from memory-mapped I/O transfers. The DMAC features edge or level sense request input, address increment/decrement/no-change
and (for memory to/from memory transfers) programmable burst or cycle steal
transfer. In addition, the DMAC can directly access the full I-Mbyte of physical
memory address space (the MMU is bypassed during DMA) and transfers (up to
64-kbyte in length) can cross 64-kbyte boundaries.
Asynchronous Serial Communication Interface (ASCI)
The ASCI provides two separate full-duplex U ARTs and includes a programmable
baud rate generator, modem control signals, and a multiprocessor communication
format. The ASCI can use the DMAC for high-speed serial data transfer, reducing
CPU overhead.
Clocked Serial 1/0 Port (CSI/O)
The CSI/O half-duplex clocked serial transmitter and receiver can be used for simple, high-speed connection to another microprocessor or microcomputer.
Programmable Reload Timer ( PRT)
The PRT contains two separate channels, each consisting of 16-bit timer data and
16-bit timer reload registers. The time base is the system clock divided by 20 (fixed)
and PRT channel I has an optional output allowing waveform generation.
Programmable Timer 2 (PT2)
The PT2 16-bit programmable timer can measure an input waveform and generate
two independent output waveforms. The pulse widths of both input/output waveforms vary from microseconds to seconds.
Analog Comparator
The HD641180X/HD643180X/HD647180X provides an analog comparator with 6
channels. Each channel can be programmed as a reference voltage (Vrer) input pin
or a compared voltage (Vin) input pin.
Input Output Port (1/0 Port)
The HD643180X/HD647180X provides seven I/O ports. (port A-G). Each port
consists of a data direction register (DDR) to determine the directions of the individual pins, an output data register (ODR) to hold output data and an input data
register (IDR) to latch input date. However, Port G does not have a DDR or ODR since it is an
input-only port.
@HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra POint Pkwy. Brisbane, CA 94005-1819 • (415) 589-8300
705
HD641180X, HD643180X, HD647180X
•
Pins Signal Description
XTAL, EXTAL: Crystal (Input)
XT AL and EXT AL are the crystal oscillator connections. An external TTL clock
can be input on EXT AL. XT AL should be left open if an external TTL clock is
used. Note that XTAL. XTAL is schmitt triggered. See DC characteristics.
(OUT)
¢l is the system clock output. Its frequency is equal to one-half of the crystal oscilla-
tor's.
RESET: CPU Reset (Input)
When RESET is low, it initializes the HD641180X/HD643180X/HD647180X CPU.
All output signals are held inactive during reset.
Ao-A19: Address Bus (Output, Three-State)
The address bus enters the high-impedance state during reset and when another device acquires the bus as indicated by BUSREQ and BUSACK low. During reset, the
address function is selected.
Do-D7: Data Bus (Input/Output, Three-State)
The bidirectional 8-bit data bus enters the high-impedance state during reset and
when another device acquires the bus as indicated by BUSREQ and BUSACK low.
RD: Read (Output, Three-State)
During a CPU read cycle, RD enables transfer from the externql memory or I/O
device to the CPU data bus.
WR: Write (Output, Three-State)
During a CPU write cycle, WR enables transfer from the CPU data bus to the external memory or 1/0 device.
ME: Memory Enable (Output, Three-State)
ME indicates memory read or write operations. The HD641180X/HD643180X/
HD647180X asserts ME low in the following cases.
~HITACHI
706
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra POint Pkwy' Brisbane. CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
When fetching instructions and operands
When reading or writing memory data
During DMA memory access cycles
During dynamic RAM refresh cycles
10E: I/O Enable (Output, Three-State)
10E indicates I/O read or write operations. The HD641180X/HD643180X/
HD647180X asserts 10E low in the following cases:
When reading or writing I/O data
During DMA I/O access cycles
During INTo acknowledge cycle
WAIT: Bus Cycle Wait (Input)
WAIT introduces wait states to extend memory and I/O cycles. If low at the falling
edge of T2, a wait state (Tw) is inserted. Wait states will continue to be inserted
until the WAIT input is sampled high at the falling edge of Tw, at which time the
bus cycle will proceed to completion.
E: Enable (Output)
E is a synchronous clock for connection to HD63 x x series and other 6800/6500
series compatible peripheral LSls.
BUSREQ: Bus Request (Input)
Another device may request use of the bus by asserting BUSREQ low. The CPU
will stop executing instructions and place the address bus, data bus, RD, WR, ME,
and 10E in the high-impedance state.
BUSACK: Bus Acknowledge (Output)
When the CPU completes bus release (in response to BUSREQ low), it will assert
BUSACK low. This acknowledges that the bus is free for use by the requesting device.
HALT: Halt/Sleep Status (Output)
HALT is asserted low after execution of the HALT or SLP instructions. Used with
LIR and ST output pins to encode CPU status (table 2).
LIR: Load Instruction Register (Output)
LIR is asserted low when the current cycle is an opcode fetch cycle. Used with
HAL T and ST output pins to encode CPU status (table 2).
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
707
HD641180X, HD643180X, HD647180X
ST: Status (Output)
ST is used with the HALT and
LIR output pins to encode CPU status (table 2).
Table 2 Status Summary
ST
HALT
0
LlR
0
Operation
0
CPU operation
(2nd opcode and
3rd opcode fetch)
CPU operation
(1 st opcode fetch)
CPU operation
(MC except for opcode fetch)
0
0
Note
X
1
DMA operation
0
0
0
Halt mode
Sleep mode (including
System stop mode)
X: Don't care
MC: Machine cycle
REF: Refresh (Output)
When low, REF indicates that the CPU is in a dynamic RAM refresh cycle and the
low-order 8 bits (Ao-A7) of the address bus contain the refresh address.
NMI: Non-Maskable Interrupt (Input)
When high to low is detected, it forces the CPU to save certain state information
and vector to an interrupt service routine at address 0066H. The saved state information is restored by executing the RETN (return from non-maskable interrupt) instruction.
INTo: Maskable Interrupt Level 0 (Input)
When low, INTo requests a CPU interrupt (unless masked) and saves certain state
information unless masked by software. INTo requests service using one of three
software programmable interrupt modes (table 3).
~HITACHI
708
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1619 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Table 3 Interrupt Modes
Mode
Operation
o
Instruction fetched and executed from data bus
2
Vector system: Low-order 8 bits of vector table address fetched from data bus
Instruction fetched and executed from address 0038H
In all modes, the saved state information is restored by executing the RETI (return
from ·interrupt) instruction.
INT 1, INT2 : Maskable Interrupt Levels 1, 2 (Input)
When low, INTI and INT2 request a CPU interrupt (unless masked) and save certain state information unless masked by software. INTI and INT2 (and internally
generated interrupts) request interrupt service using a vector system similar to mode
2 of INTo.
DREQo DMA Request-Channel 0 (Input)
DREQo low (programmable edge or level sense) requests DMA transfer service
from channel 0 of the HD641180X/HD643180X/HD647180X DMAC. DREQo is
used for channel 0 memory to/from 110 and memory to/from memory-mapped I/O
transfers. DREQo is not used for memory to/from memory transfers. This pin is
multiplexed with CKAo.
TENDo: Transfer End-Channel 0 (Output)
TENDo is asserted low synchronous with the last write cycle of channel 0 DMA
transfer to indicate DMA completion to an external device. This pin is multiplexed
with CKAL
DREQ1: DMA Request-Channel 1 (Input)
DREQI low (programmable edge or level sense) requests DMA transfer service
from channell of the HD641180X/HD643180X/HD647180X DMAC. Channell
supports memory to/from 110 transfers.
TEND 1: Transfer End- Channel 1 (Output)
TENDI is asserted low synchronous with the last write cycle of channel 1 DMA
transfer to indicate DMA completion to an external device.
@HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy. Brisbane, CA 94005·1819· (415) 589-8300
709
HD641180X, HD643180X, HD647180X
TXAo: Asynchronous Transmit Data-Channel 0 (Output)
TXAo is the asynchronous transmit data from channel 0 of the asynchronous serial
communication interface (ASCI).
RXAo: Asynchronous Receive Data-Channel 0 (Input)
RXAo is the asynchronous receive data to channel 0 of the ASCI.
CKAo: Asynchronous Clock-Channel 0 (Input/Output)
CKAo is the clock input/output for channel 0 of the ASCI. This pin is multiplexed
(software selectable) with DREQo.
RTS o: Request to Send-Channel 0 (Output)
R TSo is the programmable modem control output signal for channel 0 of the ASCI.
CTS o: Clear to Send-Channel 0 (Output)
CTSo is the modem control input signal for channel 0 of the ASCI.
DCDo: Data Carrier Detect-Channel 0 (Output)
DCDo is the modem control input signal for channel 0 of the ASCI.
TXA 1 : Asynchronous Transmit Data-Channel 1 (Output)
TXAI is the asynchronous transmit data from channel 1 of the ASCI.
RXA 1 : Asynchronous Receive Data-Channel 1 (Input)
RXAI is the asynchronous receive data to channel 1 of the ASCI.
CKA1 : Asynchronous Clock-Channel 1 (Input/Output)
CKAI is the clock input/output for channel 1 of the ASCI. This pin is multiplexed
(software selectable) with TENDo.
CTS 1 : Clear to Send-Channel 1 (Input)
CTSI is the modem control input signal for channel 1 of the ASCI. This pin is
multiplexed (software selectable) with RXS.
~HITACHI
710
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
TXS: Clocked Serial Transmit Data (Output)
Clocked serial transmit data from the Clocked SerialllO Port (CSIIO).
RXS: Clocked Serial Receive Data (Input)
Clocked serial receive data to the CSIIO. This pin is multiplexed (software selectable) with ASCI channel 1 CTSI modem control input.
CKS: Serial Clock (Input/Output)
Input or output clock for the CSIIO.
TOUT1 : Timer Output (Output)
Pulse output from Programmable Reload Timer channell.
ANo·AN s: Comparator (Input)
ANo-ANs input data to the analog comparator. Select two of these pins and apply
the reference voltage (Vref) and the voltage to be compared (Vin) to them.
PAo·PAn PBo·PB7, PCo·PCn POO-P0 7, PEo, PE7, PFo·PF7 : Parallel Ports A·F
(Input/Output)
Ports A-F are 8-bit 1/0 ports. Each pin of each port can be individually configured
as an input or output depending on the port data direction register. At reset, each
port is initialized as an input port.
PGo·PG s : Parallel Port G (Input)
Port G is a 6-bit input port.
IC: Input Capture (Input)
IC inputs the input capture signal for timer 2.
TOUT2, TOUT3: Timer Output 2, 3 (Output)
TOUT2 and TOUT3 are timer 2's outputs.
MPo, MP1 : Mode Program 0, 1 (Input)
The mode program pins, MPo and MP1, determine the operation mode of the MPU
as shown in table 4.
@HITACHI
Hitachi Amenca, Ltd .• Hitachi Plaza. 2000 Sierra Pomt Pkwy· Brisbane, CA 94005-1819 • (415) 589-8300
711
HD641180X, HD643180X, HD647180X
Table 4. Operating Mode Selection
MP,
MPo
o
o
o
ROM
RAM
E
o
I: Internal
E: External
Select mode 1 (MP, ~ 0, MP2
~
In
Operating Mode
Applicable Wide-Range
0; Single chip mode
HD6431 BOX
HD6471 BOX
1; Expanded mode 1
HD6431 BOX
HD6471 BOX
HD6411BOX
2; Expanded mode 2
HD6431 BOX
HD6471 BOX
3; PROM programming mode
(HD6471 BOX only)
HD6471 BOX
1) for the HD641180X.
Vee, Vss: Power
Vee is power supply. Vss is the ground .
• Multiplexed Pins
PAo/TXA1, PA1/RXA1, PA3/TXS, PA5/CKS, PA6/0REQ1, PA7/TENOl
At reset, PAo/TXAl, PAdRXAI, PA3/TXS, PAs/CKS, PAs/DREQI, and PA7ITENDI
are configured as port A input. They can be used as TXAI, RXAI, TXS, CKS, DREQI,
and TENDI by setting the corresponding bit in the port A disable register to 1.
PA2/CKA1/TENOo
At reset, PA~/CKAdTENDo is configured as a port A input. The function of this
pin depends on the combination of bit 2 in the port A disable register (DERA2)
and the CKAID bit in the ASCI control register channell (table 5).
Table 5. PA2ICKA1/TENOo State
DERA2
CKA1D
°1
0, 1
°1
Pin Function
TENDo
~HITACHI
712
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
PA4/RXS/CTS1
At reset, PA4/RXS/CTS, is configured as a port A input. The function ofthis pin depends
on the combination of bit 4 in the port A disable register (DERA4) and the CTSIE bit in
the ASCI status register channell (table 6).
Table 6. PA4/RXS/CTS1 State
DERA4
CTS1E
°
0, 1
°1
Pin Function
RXS
CTSI
CKAo/DREQo
CKAo/DREQo is configured as the CKAo at reset. When either the DMI or SMI bit of
the DMA mode registers 1, this bit is forcibly configured as the DREQo input, even ifit
has been configured as an output pin.
PGo/ANo, PG1/AN1, PG2/AN2, PG3/AN3, PG4IAN4, PGs/ANs
These pins cannot be configured as parallel port input pins (TTL-level input pins) alternate with analog comparator input pins. When using these pins as a TTL input
port, read the port G input data register (IDRG).
When using these pins as an analog comparator's channel input, read the comparator control/status register (CCSR).
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
713
HD641180X, HD643180X, HD647180X
• Absolute Maximum Ratings
Item
Symbol
Value
Unit
Supply Voltage
Vee
-0.3 to +7.0
V
Input Voltage
- 0.3 to V ee + 0.3
V
Operating Temperature
- 20 to + 75
Storage Temperature
- 55 to + 150
°C
°C
Note: Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should
be under recommended operating conditions. If these conditions are exceeded, it could effect
reliability of LSI.
Storage Temperature of the HD647180X is Tstg ~ -55 - +125'C .
• ELECTRICAL CHARACTERISTICS
• DC Characteristics (Vee = 5V ± 10%, Vss = OV, Ta = -20 to + 75°C, unless
otherwise noted)
Typ
Symbol
Item
Min
Max
Unit
V,H1
Input High Voltage
RESET, EXTAL, NMI
Vee- 0 .6
Vee+ 0 .3
V
V,H2
Input High Voltage
Except RESET, EXTAL, NMI
2.0
Vee+ 03
V
V,L1
Input Low Voltage
RESET, EXTAL, NMI
-0.3
0.6
V
V Il2
Input Low Voltage
Except RESET, EXTAL, NMI
-0.3
0.8
V
V OH
Output High Voltage
All outputs
2.4
Vec
Condition
V
IQH = -200jJ.A
20jJ.A
IOH -
12
VOL
Output Low Voltage
All Outputs
0.45
V
IOl = 2.2 mA
I'l
Input Leakage
Current All Inputs
Except XT AL, EXTAL, RESET
10
jJ.A
Vln= 0.5 to Vee - 0.5 V
frl
Three State Leakage
Curref,lt
1.0
jJ.A
VIn= 0.5 to Vee - 0.5 V
Icc
(Note)
Power DissipatIOn
(Norm·al Operation)
20
25
30
40
50
60
mA
f = 4 MHz
f - 6 MHz
f - 8 MHz
Power Dissipation
(System Stop Mode)
5
6.3
7.5
10
12.5
15
mA
f= 4 MHz
f - 6 MHz
f - 8 MHz
pF
Vin= OV, f= 1 MHz
Cp
Pin
RESET
120
Capacitance
Except
RESET
20
Ta=25°C
Note. V,Hm,n = Vee - 1.0 V, V,lmax = 0.8 V (All input pins except RESET, EXTAL NMI)
V,Hm,n = Vee - 0.6 V, V,lmax = 0.6 V (RESET, EXTAL, NMI)
(all output terminals are at no load.)
~HITACHI
714
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Symbol
Item
Min
Max
Unit
V1HP
Input
High-Level
Voltage
20
Vee + 0.3
V
V1LP
Input
Low-Level
Voltage
-0.3
OS
V
VOHP
Output
High-Level
Voltage
2.4
VOLP
Output
Low-Level
Voltage
V,n
Analog
Comparator
Input Level
Voltage
Input Leak
Current
V,ef
IILP
Note.
Typ
V
Vee -12
V
1.0
*IOL=2.2 mA
**IOL =10 mA
V
V,ef+ 01
Low level
VTH
IOH=-200 J.LA
ioH-- 20 /LA
0.45
High level
Condition
Vref-O 1
0
Vee XO.S
V
1.0
/LA
V,n-0.5 to
Vee - 0.5
Port A-F
Port F on!y
~HITACHI
Hitachi America, Ltd • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
71 5
HD641180X, HD643180X, HD647180X
• AC Characteristics (Vss = OV, Ta = -20 to + 75°C, unless otherwise noted)
HD641180X-4
HD641180X-6
HD641180X-8l
HD643180X-4
HD643180X-6
HD643180X-8l
HD647180X-4
HD647180X-6
HD647180X-8l
min
max
min
max
min
max
unit
Vee
Power Supply
45
55
45
55
475
525
V
teye
Clock Cycle TIme
250
2000
162
250
125
250
ns
tCHW
Clock HIgh Pulse W,dth
110
65
50
tCLW
Clock Low Pulse W,dth
110
65
50
tel
Clock Fall T,me
15
15
15
ns
ter
Clock RIse Tome
15
15
ns
tECYc
External Clock Cycle T,me
125
15
125
125
ns
tEXHW
External Clock
High Pulse W,dth
50
30
25
ns
tEXLW
Extemal Clock
Low Pulse W,dth
50
30
25
ns
tEXr
(Note 1)
Extemal Clock
RIse T,me
25
25
25
ns
tEXt
(Note 1)
Extemal Clock
Fall tIme
25
25
25
ns
65
ns
Symbol
Item
tAD
Address Delay TIme
tAs
Address Set-up TIme
(ME or iO£ j)
tMEDl
ME Delay T,me 1
~DDl
RD Delay TIme 1
tLDl
LlR Delay Time 1
1000
81
100
50
625
75
30
ns
ns
20
ns
75
45
45
ns
IOC=l
75
45
45
ns
IOC=O
80
50
45
100
80
70
ns
(Note 2)
Address Hold TIme 1
(ME, N, RD or WR fl
tAH
80
20
35
ns
tMED2
ME Delay T,me 2
75
45
45
ns
tRDD2
RD Delay TIme 2
75
45
45
ns
tLD2
LlR Delay TIme 2
100
80
70
ns
(Note 2)
tDRS
Data Read Set-up T,me
60
55
45
tDRH
Data Read Hold TIme
0
0
0
tSTD1
ST Delay TIme 1
110
90
70
ns
tSTD2
ST Delay T,me 2
110
90
70
ns
tws
WAIT Set-up TIme
80
40
40
ns
tWH
WAIT Hold TIme
70
40
40
ns
tWDZ
Wrote Data FloatIng
Delay TIme
100
95
70
ns
tWRDl
WR Delay T,me 1
80
50
45
ns
tWDD
Wrote Data Delay TIme
110
90
80
ns
tWDS
Wrote Data Set-up TIme
60
40
ns
ns
20
ns
(INA jl
Note 1 External clock rlse/faU time (\:xr' ~Xf) may be shortened for satisfYing external dock pulse Width (\:XHW' l£xLw)
Note 2 For a loading capacitance of less than or equal to 40 picofarads and operating temperature from 0 to 50 degrees, subs tract 10 nanoseconds
from the value given In the maximum columns
~HITACHI
716
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Symbol
Item
HD6411BOX-4
HD6411BOX-6
HD6411BOX-BL
HD6431 BOX-4
HD6431 BOX-6
HD6431 BOX-BL
HD6471 BOX-4
HD6471 BOX-6
HD6471 BOX-BL
min
min
min
max
max
max
unit
45
ns
tWRD2
WR Delay Time 2
tWRP
WR Pulse Width
280
170
130
ns
tWDH
Write Data Hold Time
(WR!l
60
40
15
ns
t'ODl
IOE Delay Time 1
BO
50
IOC=l
75
45
45
IOC=O
80
50
45
45
~OD2
IOE Delay Time 2
~OD3
IOE Delay Time 3
(LiR J)
540
340
250
ns
~NTS
INT Set-up Time
( Jl
80
50
40
ns
~NTH
INT Hold Time
( Jl
70
40
40
ns
~MIW
NMI Pulse Width
120
120
100
ns
taRS
BUSREQ Set-up Time
( Jl
80
50
40
ns
taRH
8USREQ Hold Time
( J)
70
40
40
ns
tBADl
BUSACK Delay Time 1
100
95
70
ns
taAD2
BUSACK Delay Time 2
100
95
70
ns
taZD
Bus Floating Delay Time
130
125
90
ns
tMEWH
ME Pulse Width (HIGH)
200
110
90
ns
~EWL
~FDl
ME Pulse Width (LOW)
210
125
100
REF Delay Time 1
110
90
80
ns
ns
~FD2
REF Delay Time 2
110
90
80
ns
tHADl
HALT Delay Time 1
110
90
80
ns
~AD2
HALT Delay Time 2
110
90
80
ns
toROS
DREQI Set-up Time
80
50
40
toRaH
DREQi Hold Time
70
40
40
tTEDl
TENDi Delay Time 1
85
70
60
ns
tTED2
TENDI Delay Time 2
85
70
60
ns
~Dl
Enable Delay Time 1
100
95
70
ns
~D2
Enable Delay Time 2
100
95
70
PWEH
E Pulse Width (HIGH)
150
75
65
ns
PWEL
E Pulse Width (LOW)
300
180
130
ns
75
45
ns
ns
ns
ns
ns
<@fHITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra POint Pkwy' Brisbane, CA 94005-1819 • (415) 589-8300
717
HD641180X, HD643180X, HD647180X
Symbol
ter
Item
HD641180X·4
HD641180X·6
HD641180X·8L
HD643180X·4
HD643180X·6
HD643180X·8L
HD647180X·4
HD647180X·6
HD647180X·8L
min
min
min
Enable Rise Time
max
25
max
max
unit
20
20
ns
tef
Enable Fall Time
25
20
20
ns
tTOO
Timer Output Delay Time
300
300
200
ns
tsTOI
CSI/O Transmit Data Delay Time
200
200
200
ns
7.5tcyc
+300
7.5tcyc
+300
7.5teyc
+200
ns
(lntemal Clock Operation)
tSTOE
CSVO Transmit Data Delay Time
(External Clock Operation)
tSRSI
CSI/O Receive Data Set·up Time
tcyc
(lntemal Clock Operation)
tSRHI
CSI/O Receive Data Hold Time
tcyc
(lntemal Clock Operation)
tSRSE
CSVO Receive Data Set·up Time
tcyc
(External Clock Operation)
tSRHE
CSI/O Receive Data Hold Time
tcyc
(External Clock Operation)
lflES
RESET Set-up Time
120
120
100
lflEH
RESET Hold Time
80
80
70
ns
tesc
Oscillator Stabilization Time
20
20
20
ms
teXr
Extemal Clock Rise Time (EXTAL.)
25
25
25
ns
texf
Extemal Clock Fall Time (EXTAL.)
25
25
25
ns
lflr
RESET Rise Time
50
50
50
ms
tm
RESET Fall Time
50
50
50
ms
ttr
Input Rise Time
(except EXTAL. RESET)
100
100
100
ns
!tt
Input Fall Time
(except EXTAL. RESET)
100
100
100
ns
!Jwo
Port Data Output Delay
Time
110
90
80
ns
tposu
Port Data Input Setup
Time
80
50
50
ns
tpOH
Port Data Input Hold
Time
60
40
40
ns
ns
The H0643180X differs from H064 7180X In chip design and manufactunng process Be careful when uSing the H0647180X system for the H0643180X
smce characteristics values are not exactJy the same though guaranteed values are Identical
~HITACHI
718
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
HD641180X, HD643180X, HD647180X
Opcode Fetch Cycle
~ __4--HtJ~~__~lt~A_S
__________
110 Write Cycle
~_t_M~E~
_ --I__++-tM_E_D_1_________-++__+-__
10E
+---+~_JA.S
ItAH
~
~D2
tlomD2tAH,
\ , - t lQQ.1jI'+--------------+.jI
1--'
I
\'+----1-1--1£ ~H
~RDl
~WRD2
WR--1--n-------------1t--tr----t--~~~I~----~tW~RP~--t1~~
~
!
LlR-~,
tL~D~ll,++_------------_.jI
r
ST----.......""
tST~
~TD2
if
Data
IN
"' Output buffer is off at this point.
Figure 4. CPU Timing (Opcode Fetch Cycle)
1/0 Write Cycle (1/0 Read Cycle)
When 10C = 1
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
719
HD641180X, HD643180X, HD647180X
T,
~2:
en
oj:>.
T3
00
'"
»
TW
T2
o
.?<
teOl
3
~
....w
00
'"::>.
Fl
a
E
en
oj:>.
(Memory ReadlWrite)
•
tED 1
::t:
~
-0
~
o
.?<
E
(VO Read)
•
te02
""
§
w..
;;l
-0 :I
_
-..J
....
00
E
tORS
0/0 Write)
2. ~
;a )Ii
~(')
~ :I
•
::>.
'"
.'"'"
g
~
en
oj:>.
Figure 9. E Clock Timing (Bus Release Mode,
Sleep Mode,
System Stop Mode)
o
:xl
HD641180X, HD643180X, HD647180X
E
Example
( VO Read
-
Opcode fetch
E
(110 Write)
Figure 9A. E Clock Timing (Minimum Timing Example
of PWEL and PWEH)
Timer Data
Reg. = OOOOH
TOUT 1
TOUT2
TOUT3
tTOD
Figure 10. Timer Output Timing
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
725
HD641180X, HD643180X, HD647180X
.:
.s::
0
.!
Q)
"0
0
&
0
)(
Q)
z
..:
Q)
(j
>c
(,)
j!:
~
0
::;,
~
u
~
(IJ
j
W
Q.
...I
C/)
.,.:
,..
~
::;,
10)
u::
I~
726
I~
e?
<1:
I
o
<1:
• HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, GA 94005-1819. (415) 589-8300
:r
""
1!i
:<.
»
CSI/O Clock
3
CD
tSTDI
::J.
n
!"
g
•
:r
Transmit data
(Internal Clock)
s=
n
:<.
tSTDE
tSTDE
"
~
Transmit data
(External Clock)
•
§
f
,
I'~_ _ _ _ _ _ _ _ __
w..
@ :I
"=- )Ii
Q.
~
"J?(')
~ :I
::r:
oen
Receive data
(Internal Clock)
C:J
::J.
~
:if
:::>
co
~
~
en
?
§;
~cO
o
Receive data
(External Clock)
..><:
S
en
~
w
co
<0
~
•
J;::
~
~
g
Figure 12. CSI/O Receive/Transmit Timing
~
S
en
~
-...J
~
-..j
I\)
-..j
co
~
HD641180X, HD643180X, HD647180X
T2
Port
output
------'
tPDSU
tPDH
Input
Figure 13. Port Input and Output Timing
-
EXTAL \/ill
t ECYC
-
~tEXr
V,Hl
VIHl
tEXHW
I--tEXf
VILl
V-
tEXLW
Figure 14. External Clock Rise Time
and Fall Time
Figure 15. Input Rise Time and Fall
Time
(Except EXTAL, RESET
~HITACHI
728
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra POint Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Vee
Test Point
18
C
R
152074
RL
or Equiv.
®
C = 90 pF. R = 12 kO
RL = 1.6 kH
Figure 16. Bus Timing Test Load (TTL Load)
---Y20V
---yw
20VY-
.-!\...;;;0.;.;;.8_V'--_ _0_.8;....V_~
Wy-
.-!\...;.0...;;;.8_V_ _ _O;.....8.=--v!L
Figure 17. Reference Level (Input)
Figure 18. Reference Level (Output)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
729
HD641180X, HD643180X, HD647180X
• INSTRUCTION SET
Register
g, g', ww, xx, yy, and zz specify a register to be used. g and g' specify an 8-bit register. ww, xx, yy, and zz specify a 16-bit pair of 8-bit registers. TableI shows the
correspondence between symbols and registers.
Table 7 Register Specification
g,g'
Reg.
000
001
010
011
100
101
111
B
C
ww Reg.
00 BC
xx
00
01
10
11
Reg.
yy
Reg.
zz
Reg.
BC
00
01
10
11
BC
00
01
10
11
BC
D
E
01
10
11
H
L
A
Note: Hand L suffixed to wW,xx,yy,zz (ex. wwH, IXL) indicate upper
and lower 8 bits of the 16-bit register, respectively.
DE
HL
SP
DE
IX
SP
DE
IV
SP
DE
HL
AF
Bit
b specifies a bit to be manipulated in the bit manipulation instruction. Table 8 shows
the correspondence between b and bits.
Table 8 Bit Specification
b
Bit
000
001
010
011
100
101
110
111
a
1
2
3
4
5
6
7
Condition
f specifies the condition in program control instructions. Table 9 shows the
correspondence between f and conditions .
•
730
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Table 9 Condition Specification
f
000
001
010
011
100
101
110
111
Condition
NZ non zero
Z zero
NC non carry
C carry
PO parity odd
PE parity even
P sign plus
M sign minus
Restart Address
v specifies a restart address. Table A-4 shows the correspondence between v and restart addresses.
Table 10 Restart Address Specification
v
Address
000
001
010
011
100
101
110
111
OOH
08H
10H
18H
20H
28H
30H
38H
Flag
The following symbols show the flag conditions:
. : not affected
1 : affected
x : undefined
S : set to 1
R : reset to 0
P : parity
V: overflow
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
731
HD641180X, HD643180X, HD647180X
Miscellaneous
(
(
)M : Data in the memory address
h : Data in the 110 address
m or n : 8-bit data
mn : 16-bit data
r : 8-bit register
R : 16-bit register
b·(
)M : Contents of bit b in the memory address
b·gr : Contents of bit b in the register gr
d or j : 8-bit signed displacement
S : Source addressing mode
D : Destination addressing mode
. : AND operation
+ : OR operation
+ : EXCLUSIVE OR operation
** : Added new instructions to Z80
~HITACHI
732
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra POint Pkwy· Brisbane, CA 94005-1819· (415) 589-8300
HD641180X, HD643180X, HD647180X
Instruction Summary
Data Manipulation Instructions
Table 11 Arithmetic and Logical Instructions (8 Bit)
Addressing
Op.rltion
Name
Mnemonics
Opcode
ADD
ADD A"
ADD A,IHL)
ADD A,m
10000,
10000110
11000110
IMM£D EXT
IND
REG REGI IMP
5
0
S
REL
Byt••
I
D
I
D
2
States
Operation
Flag
764210
S Z H PlY N C
Ar+gr-+Ar
Ar+(HLl ....... Ar
Ar+m ..... Ar
I
I
I
I
:
I
I
I
I
V
V
V
R
R
R
I
I
I
I.
Art (IX +d)III ..... Ar
I
I
I
V
R
I
I.
Ar+{IYtdllll......Ar
I
V
R
I
I
I
I
V
V
V
R
R
R
I
:
I
( m )
ADD A,(IX+d)
11 011 101
10000110
( d )
ADD A,IIYtd)
11 III 101
10000110
( d )
ADC
AOC A,m
!(
ADC A,i1X+d)
AOC A,!{Y +d',
AND
!
10001 g
10001110
llOOlllD
ADC A"
ADC A,(HL\
10 100 ,
10 lOOllO
lllOOllfl
AND HV
ANDm
1
I
Ar+m+c ....Ar
I
Art (IX +d) .. +c ..... Ar
I
I
V
R
I
I A,+IIYTd),+c-A, iII
I
V
R
I
I
I
I
5
S
5
P
P
P
R
R
R
R
R
R
I.
I
5
P
R
R
14
I
5
P
R
R
m )
I.
111011101
10001110
d )
11 III 101
10 001 110
( d )
AND,
Ar+gr+c-+Ar
Art (HUIl+c..... Ar
5
14
i
5
I
I s
I
I
0
I
0
I
I
D
2
•
I A"gr-M
! Ar":HLi"' .... Ar
i Ar'm----Ar
I
i
m )
AND'IX-dl
11011101
10100110
I ' d )
AND iIY +di
Compare
11 III WI
10100110
d
CP,
10 III ,
10 III 110
1l1ll1lO
CPm
!
I 0
I
I
I 0
I
I
5
5
!
I
I
I
I
D
SID
! D
, m
I.
CP [IY +dl
i S
I
11111101
10 III 110
, d
I
)
DEC
DEC ,
DEC iHLI
DEC lIX+dl
DEC (lY+d)
V
5
I
:
V
I
\'
5
5
I
I
I
I
V
5
I
I
:
V
S
I
00, 101
00110101
I Ar- ;IX +dl M
I'
I
II
i Ar- dY +diM
S
!
SID
SID
I SiD
I
:
111011101
I
I
I
I
00101111
ment
D
I
r
Comple-
I
I
!
i 0
i(d
'1
I
HL<,
i Ar-m
I
11611101
10111110
)
CP dXi'dl
I A,-gr
I A,-
S
: !
•
gr-I-",
I
I
V
S
3
18
(IX+dllll-l .....
1
1
1
1
V
V
5
S
I
I
V
5
I
I
I
I
1
I
V
V
V
R
R
R
;IX+d\ ..
~ :~:
I :::
I 00110101
SID
18
(IY+dlM-j---
lIY·dl,
( d )
INC
INC,
INC iHLI
INC ilX+dl
SID
::
11011101
1
00 110 100
1 : :10
( rl
SID
4
gr+l-gr
10
18
{HUIII+ l-(HL)",
(IX+d)"'+l ......
I {lX+d)",
)
~HITACHI
Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
733
HD641180X, HD643180X, HD647180X
Table 11 Arithmetic and Logical Instructions (8 Bit) (cont)
Flag
Addressing
Operation
Neme
Mnemonic.
MULT
MLT ww ••
Negate
NEG
11101101
010lI0100
OR
ORg
OR lULl
ORm
10110 g
10110110
II 110110
( m >
II 011 101
10 110 110
( d >
11111101
10110110
( d >
OR IIX+dl
OR IIY+dl
SUB
SUBg
SUB (HLI
SUBm
SUB IIX+dl
SUB (IY+dl
SUBC
SseA~
sse A,IULI
sse A.m
sse A,IIX+dl
sse A,(IY +dl
Test
TST g ••
TST (HU"'·
TST
m··
Opcode
II 101101
01 wwllOO
10 010 g
10 010 110
II 010 110
( m >
11011101
10010110
( d ) ,
11111101
10 010 110
( d )
10011 g
10011 110
II 011 110
( m >
II 011 101
10 011 110
( d )
11111101
10011110
( d )
II 101 101
OOg 100
11101101
00 110 100
II 101 101
01100 100
IMMED EXT
IND
S
6 4 2 1 0
Z H PlY N C
7
REG REGI IMP REL Bytes
2
SID
States
Operation
11
wwHrxwwLr..."".
SID
2
6
O-Ar-Ar
I
I
I
V
S
I
D
D
D
1
I
•
Ar+gr-Ar
Ar+(HLI.-Ar
2
6
6
Ar+m-Ar
I
I
I
I
I
I
R
R
R
P
P
P
R
R
R
R
R
R
S
D
3
I.
Ar+ (IX td).-Ar
I
I
R
P
R
R
S
D
3
I.
Ar+ IIY +d).-Ar
I
I
R
P
R
R
0
0
0
I
I
S
D
S
S
S
S
•
Ar-gr--Ar
2
6
6
Ar- (HL11I-Ar
Ar-m-Ar
I
I
I
I
I
I
I
I
I
V
V
V
5
S
S
I
I
I
3
I.
Ar- (IX +dl .. -Ar
I
I
I
V
S
I
0
3
14
Ar- IIY +dl.-Ar
I
I
I
V
S
I
0
D
I
I
•
0
2
6
6
Ar-gr-c-Ar
Ar- (HU ... -c..... Ar
Ar-m-c-Ar
I
I
I
I
I
I
I
I
I
V
V
V
S
S
S
I
I
I
S
0
3
I.
Ar-(IX+dllll-c-Ar
I
I
I
V
S
I
S
D
3
I.
Ar-(IY+dJII-c-Ar
I
I
I
V
S
I
2
1
Ar·gr
I
I
S
P
R
R
2
10
Ar'IULI.
I
I
S
P
R
R
3
9
Ar·m
I
I
S
P
R
R
4
S
S
5
S
S
S
S
S
S
( m )
XOR
XOR g
XOR lULl
XORm
10101 g
10 101 110
11101 110
( m )
S
:
I
I
D
2
6
6
MBgr-Ar
Art[lIHLI.-Ar
ArtBm-Ar
I
I
I
I
I
I
R P
R P
R P
R
R
R
R
D
D
S
S
XOR (IX+dl
II 011 101
S
D
3
14
Ar€tl(fX+dlll.... Ar
I
I
R
P
R
R
XOR IIY+dl
10 101 110
( d )
11111 101
10 101 110
( d )
S
D
3
14
~(IY+d)"'-Ar
I
I
R
P
R
R
flHITACHI
734
R
R
Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819. (415) 589-8300
HD641180X, HD643180X, HD647180X
Table 12 Rotate and Shift Instructions
Operation
S
Flag
4 2 1 0
Z H PlV N C
~''''''---1iO
I
I
R
R
P
R
R
I
I
Add ....lng
Optrotl..
Name
Rotate
sod
Shift
Dsta
Mnemonic.
RLA
RLI
RL IHLI
RL IIX+dl
RL IIY+dl
RLCA
RLCg
RLC IHLI
RLC I1X+dl
RLC IIY+dl
RLD
RRA
RRa
RR IHLI
RR lIX+dl
RR lIY+dl
RRCA
RRCI
RRC IHLI
RRC IIX+dl
RRC lIY+dl
Opeode
00 010111
11001011
00 010 I
11001011
00 010110
11 011101
11001011
( d )
00 010110
11111101
1100101l
( d )
00010110
00Il00111
11 001 011
00 IlOO a
11001011
00Il00110
11011101
11001011
( d )
001lOO1I0
11111101
11001011
( d )
00 IlOO 110
11101101
01101111
00011111
11001011
00 011 g
II 001 011
00011110
1I011101
11 001 Oll
( d )
0001l1l0
1I 1I1 101
1I 001 Oll
( d )
0001l1l0
00001111
1I001011
00 001 a
1I001011
00 001110
11011101
11001011
( d )
00 001 110
11111101
11 001 Oll
( d )
00001110
_0
EXT
7
INO REG REGI IMP
SID
SID
REL Byte.
Stilt••
1
2
3
7
'-fl.
C
8
2
13
I
1
R
P
R
1
SID
I
19
1
1
R
P
R
1
SID
I
19
1
1
R
P
R
1
I
2
3
7
1
1
R
R
P
R
R
1
I
SID
SID
SID
o1fITIIIIIJJ
C.7~W
2
13
I
I
R
P
R
I
SID
4
19
I
1
R
P
R
I
SID
4
19
I
I
R
P
R
I
ttLlM
!
1
R
P
R
[jb'--"e.o
1111111 KJ..1
c
I
I
R
R
P
R
R
I
1
SID
~
~
SID
.
AI
2
16
I
2
3
7
2
13
I
1
R
P
R
1
SID
I
19
1
1
R
P
R
1
SID
4
19
I
I
R
P
R
I
1
2
3
7
I
I
R
R
P
R
R
1
1
2
13
I
1
R
P
R
1
SID
4
19
1
1
R
P
R
1
SID
4
19
1
I
R
P
R
1
SID
SID
SID
SID
SID
SID
1:11 L.-.....J bel
q 1111111 i10
.7~1ID
C
(continued)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
735
HD641180X, HD643180X, HD647180X
Table 12 Rotate and Shift Instructions (cont)
Optrotion
Name
Mnemonics
Opcocle
Rotate
RRD
11101101
01100 III
11 001 011
00 100 g
11 001 011
00 100 110
11 011101
11 001 011
( d )
00 100 110
11 III 101
11 001 011
( d )
00 100 110
11 001 011
00 101 g
11 001 011
00 101 110
11 011101
11 001 011
( d )
00 101110
11111101
11 001 011
( d )
00 101 110
11 001 011
OOlllg
11 001 011
00 111 110
11 011101
11 001 011
( d >
00 1ll1l0
11 III 101
11 001 011
( d )
00 1ll1l0
and
Shift
Data
SLAg
SLA (BL)
SLA (IXtd)
SLA (JYtd)
SHAg
SRA (BL)
SRA (IXtd)
SRA (JYtd)
SRLg
SRL {BLI
SRL (lXtd)
SRL IIYtdl
-
EXT IND
illiG IlliGI IMP REL Byte.
SID
2
Stot..
16
•
..
"i'ttu.
0
I
I
R
P
R
I
I
R
P
R
I
19
I
I
R P R
I
4
19
I
I
R P R I
2
7
I
I
R
P
R
I
I
I
R
P
R
I
13
SID
4
SID
SID
.,
1
I
7
2
SID
Flog
4 2
Z H PlY N C
I R P R
S
~
•
I
2
SID
7
Operation
OJ
~
b1
CCIIIiTi 1HJ
"
.. e
2
13
SID
4
19
I
I
R
P
R
I
SID
4
19
I
I
R
P
R
I
2
7
I
I
R
P
R
I
SID
SID
.--IIIIIIIIHJ
.. c
"
2
3
I
I
R
P
R
I
SID
4
19
I
I
R P
R
I
SID
4
19
I
I
R
R
I
SID
•
736
I
Addreulng
P
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD641180X, HD643180X, HD647180X
Table 13 Bit Manipulation Instructions
---------
I
Operation
Name
Bit Set
Mnemonics
Opcode
SET b,g
11001011
lib
11001011
lib 110
11011101
11001011
( d )
lib 110
11111101
11001011
( d )
lib 110
SET b,(HLI
SET b,IIX+dl
SET b,IIY +dl
RES b"
Bit Reset
RES b,(HLI
RES b,iIX+dl
RES b,OY +d'i
I
i
Bit Test
I BIT b,g
BIT b,(HLi
BITb.(IX+dl
BIT b,iIY+dl
IMMED EXT
IND
REG
,
REGI
!
I
Addressing
I
IMP
REL
I
I
I
!
Bytes States
I
SID
SID
SID
7
Operation
2
7
I~b'gr
2
13
l~b·(HLI.
19
l~b'(IX+dl.
4
19
l~b·IIY+dl.
2
7
O..... b·gr
4
S
6
Z
Flag
4 2 1
H P/V N
0
C
I
I SID
I
I
,
11001011
lOb
11001011
10 b 110
11011101
11001011
( d )
10 b 110
11111101
11001011
( d )
10 b 110
SID
I
2
13
O.....b·(HL)iI!
SID
4
19
O-h·i1X+d}lII
SID
4
19
O..... b·Oy..l.d)'"
SID
I
I
I
11001011
Olb g
11001011
Olb 110
11011101
11001011
( d )
01 b 110
11111101
S
2
S
S
S
I: 00;
O~I
I
Olb
110
i
i
I
6
b·gr .... z
IX
I
:
S
X
R
2
9
b·(HLlw ..... z
X
I
S
X
R
4
15
b·(IX+d),,!"·... z
X
:
S
X
R
4
15
b·(IY+dl"c"z
X
I
S
X
R
I
~HITACHI
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Pomt Pkwy. Brisbane, CA 94005-1819· (415) 589-8300
737
HD641180X, HD643180X, HD647180X
Table 14 Arithmetic Instructions (16 Bit)
Flag
Addressing
7
Operation
Name
Mnemonics
ADD
ADDHL,....
ADD IX""
ADD lV,yy
Opcode
l1li ....1l1li1
11 011101
00 xxi 001
11111101
l1li yyllllli
IMMED EXT IND
REG REGI IMP
S
D
S
D
2
10
IY.+yy.... IY.
D
2
10
HL.+ww.+c-HL.
SID
I
2
4
7
ww.-I-ww.
IX.-I-IX.
SID
2
7
IY.-I-IY.
I
11101 101
01 wwl 010
S
DEC
DECww
DEC IX
IIIIwwlOIl
11 011 101
l1li101 011
11 III 101
l1li101011
SID
011 wwO 011
II 011 101
0111011 011
11111101
0111011011
SID
11101101
OlwwOOIO
S
INCww
INC IX
INCIY
SBe
SOC HL,ww
I
2
Stat••
Operation
H1..+ .........HL.
7
10
lX.+xx.... IX.
D
AOC HL,ww
INC
Bytes
S
ADC
DECIY
REL
SID
2
4
7
ww.+l-ww.
IX.+l .... IX.
SID
2
7
IYR+I-IY.
D
2
10
HL.-ww.-c-HL.
S
4 2 1
Z H PlV N
6
X
X
R
R
I
I
X
R
I
I
I
X
V
R
I
I
I
X
V
S
I
~HITACHI
738
0
C
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Data Transfer Instructions
Table 15 a-Bit Load
Addr.sslng
Oper.tlon
Name
Load
8-8]t Data
Mnemonic.
LDA,I
LDA,R
LOA,IBCI
LDA,IOEI
LDA,lmnl
Opcodo
II 101101
01 DID 111
11101101
01011 111
00 001 010
00 011 010
00 111 010
(
LDI,A
LO R,A
LD IBCI.A
LD IDEI,A
LD Imnl,A
LDg,m
LDg"IXtdl
LD g,llY+dl
LD IHLl.m
LD lIX+dl,m
LD IIY+dl,m
LD IHLI,g
LD IIX+dl,g
LD IIY+dlg
n
IND
S
S
6
1
0
S
C
2
State.
6
Ir-Ar
I
Z H PlY N
I R IEF. R
SID
2
6
Rr-Ar
I
I
0
D
0
I
I
3
6
6
12
IBCI.-Ar (Note I)
IOEI.-Ar
SID
2
6
Ar-.lr
SID
2
6
Ar-Rr
S
S
S
I
I
3
7
7
13
Ar-IBCI.
Ar-IOEI.
Ar-Imnl.
I
I
2
I
6
gt-gr
6
m-gr
REG REGI IMP
SID
S
REL Byt••
Operation
R W. R
(mn)II~Ar
)
( m )
11101 101
91Il00 111
II 101 101
Ot 001 III
00 IlOO 010
00 010 010
00 110 010
(
LDgg
LD g,IHLI
n
IMMEl! EXT
Flog
4 2
7
D
0
0
)
( m )
01 g It
01 g 110
OOg 110
( m )
11011101
01 g 110
( d )
11111101
01 g 110
( d )
00 110 110
( m )
II 011101
00110110
( d )
( m )
11111101
00 110 110
(
d )
( m )
01 110 g
II 011101
01 110 g
(
d )
II III 101
01 110 g
(
d )
SID
0
D
S
S
(HL1.-+gr
S
D
3
14
(lX+dlll-+gr
S
D
3
II
lIY+dl.-gr
2
9
m-+(HLl ll
S
D
S
D
4
IS
m-IIX+dl.
S
D
I
IS
m"""{IY+dl"
I
3
7
IS
gr-IHLI.
gr-IIX+dl.
3
IS
gr-lIY+dl.
D
S
S
D
S
D
Note: 1 Interrupts are not sampled at the end of LD A, I or LD A, R,
@HITACHI
Hitachi America, Ltd, • Hitachi Plaza' 2000 Sierra Point Pkwy, • Brisbane, CA 94005·1819 • (415) 589·8300
739
HD641180X, HD643180X, HD647180X
Table 16 16-81t Load
Operllton
.
Name
Mnemonic.
Opood.
Load
LDww....
OIIwwOOIII
(
>
( m >
11 011101
01110110111
(
>
( m >
1I111101
01110110111
(
>
( m >
1I1110ll1
11 011 101
1I1110ll1
11 III 101
11 III 0111
11101101
16-Blt Data
LDIX..,.
LDIY..,
LDSP,HL
LDSP,IX
LDSP,IY
LD .....,lmn)
.
.
-
Addr....n'
7
REL
Operation
S1et..
mn-+ww.
9
S
REG REG! IMP
D
S
D
4
12
mn-IX.
S
D
4
12
mn-IY.
SID
SID
I
2
I
HI.,-SP.
1
IX......SP.
SID
2
1
IY.-SP.
I
18
(mnt lJ .....wwHr
EXT IND
S
Byles
D
3
(
LDHL,lmn)
LD 1X,lmo)
LDIY,lm)
LD IPII),,",
LD Imn),HL
LD Imn)Jl(
2 1 0
Z H PNN C
•
m >
)
.
·
·
.
011101010
(
>
( m >
11 011101
011101010
(
>
( m >
1I111101
011101010
(
>
( m >
11101101
01 wwOOIl
(
FII,
4
(mn)lIII-+ wwLr
01 wwl 011
(
S
•
S
D
3
IS
(mn+l} .... Hr
(mn),,-Lr
S
D
I
18
(mn+1) .... IXHr
(mn).-IXLr
S
D
I
18
(mn+lJ .... IYHr
{mo).-IYLr
D
S
I
19
wwHr-(mn+ll.
wwLr-(mn).
3
16
Hr--(mn+1) ..
)
( m >
0111011 010
( n >
( m >
11 011101
0111011 010
D
S
Lr-Imn).
D
S
I
19
IXHr.... (mn+ 1).
IXLr-Imn).
(
LD lmolJY
• >
( m
>
11 III 101
0111011 010
(
>
( m >
.
D
S
I
19
IYH,-Imntl).
JyLr.... (mn).
~HITACHI
740
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Table 17 Block Transfer
Flog
Addressing
Operation
Neme
Block
Transfer
Search
Data
Mnemonics
Opcode
CPD
11101101
101011101
IMMEO EXT
IND
REG REGI IMP
REL Bytes
State.
Operation
7
6
S
Z
4 2 1
H PIV N
2
3
S
S
2
12
Ar- IHLI.
I
I
I
S
BC,-I~BC.
HL.-I~HL.
CPDR
I
0
C
S
11101101
101111101
S
2
14
12
BC,.O A.. IHLI.
BC,=O or Ar= IHLI.
2
3
I
I
I
I
S
[Ar-IHLI.
Q
BC,-I~BC.
HL.-I-HL.
Repeat Q ...i1
Ar:(HL).or &,"'0
CPI
11101101
1011101101
S
11101101
101101101
S
S
2
12
Ar- IHLI.
I
I
S
I
BC,-I~BC,
HL.+I~HL.
CPIR
"
3
I
S
2
14
12
BC.*OAr*(HL).
BC,,=O or Ar=(HLl.
2
3
I
!
I
I
R
I
S
[Ar-IHLI.
Q
BC,-I~BC.
HL.+l~HL.
Repeat Q until
Ar= lHLlfill or BC.::::~
LDD
SID
11101101
10101Il00
2
12
IHLI.~IDEI.
2
R
BC.-I~BC,
DE,-I~DE,
HL.-1 ..... HL.
LDD••
SID
11101101
10 III IlOO
2
14IBC"01 [ IHLI,~IDEI.
12 IBC.=OI Q BC,-I~BC.
R R R
DE,-I~DE,
HL.-I~HL.
Repeat Q until
BC.=O
LDI
SID
11101101
101110Il00
2
12
IHLI.~IDEI.
2
R
1
R
R
R
R
OCM-I .... SC.
DE,+I~DE.
HL.+l ..... HL.
LDIR
11101101
10110Il00
[ SID
2
14IBC.'01 [ IHLI.~IDEI.
l2IBC.=OI Q BC,-I~BC,
DE,,+l-DE.
I
Note:
P/V
P/V
Z =
Z =
HL.+1 .... HL.
Repeat Q unul
BC.=O
= O. BCR-I = 0
= I' BCR-I
0
I' Ar = (HL)M
*'
O' Ar
*'
(HL)M
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
741
HD641180X, HD643180X, HD647180X
Table 18 Stack and Exchange
Addressing
7
Operation
Name
Mnemonics
Opcode
PUSH
PUSHn
II zzO 101
IMMED EXT
REG REGI IMP
D
S
IND
REL Bytes
I
States
11
5
Operation
Flag
2 1 0
Z H PIV N C
6
4
zzLr~(SP-2).
zzHr..... (SP-l) ..
SPR-Z.....SPR
PUSH IX
SID
111011101
11 100101
2
14
lXLr~(SP-2).
IXHr~ (SP-li.
SPR-Z.....SPR
PUSH IY
11 1ll10l
11 100 101
SID
2
14
IYLr~(SP-2).
IYHr~(SP-li.
SP~-2-SP.
pop zz
POP
D
II zzO 001
S
I
9
ISPtl)"' .....zzHr
4
(SP) "' .....zzLr
POP IX
11 011 101
11 100001
SID
2
12
POP IY
11111101
11100001
SID
2
12
SPR+2 .....SPR
(SPt I)"' ..... rXHr
(SP1"' ..... rXLr
SPA+2..... SP.
(SP+ll",-+IYHr
(SP) ",--IYLr
SP.+Z.....SPR
Exchange
EX AF.AF'
EX DE,HL
EXX
SID
SID
SID
1
I
1
4
AFR-AFR'
3
3
DER .... HL A
BCI-SCI '
100011
SID
I
16
HLI .... HLI '
Hr.... (SP+ll lII
Lr-ISPI.
11 011 101
II 100011
11111101
II 100 011
SID
2
19
IXHr- (5P+ 1)",
2
19
IXLr-(SP)",
IYHr-(SP+l)1II
IYLr-ISPI.
000010lI0
11 101 011
11011001
I
DEM-DE A'
I
EX {SPI,HL
EX (SP)'!X
EX ISPI,lY
III
I
SID
I
I
I
Note 4 In the case of pop AF, Flag is written a current contents of the stack.
~HITACHI
742
Hitachi America, Ltd, • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD641180X, HD643180X, HD647180X
Program Control Instructions
Table 19 Program Control
Fleg
Addre ••ing
Oplrltion
Name
Mnemonics
Opcode
IMMED EXT
call
CALLmn
11 001101
( n >
( m >
D
3
CALL f,mp
Ilf
D
3
(
(
JIDIlP
DJNZJ
100
n >
m>
IND
REG REGI IMP
REL Byte.
D
00010000
2
2
Stet..
16
Operation
7
6
S
Z
4 2 1
H PlY N
0
C
PCH,-ISP-I).
PCLr-ISP-21.
",,-PC,
SP.-2......SP.
6 If fabel continue fiafal8e
16Wtruel CALL ... fiatrue
918,>01
71B,=01
B,-I-Br
continue. Br=O
pc'tj-PC•. Br*O
JPf...
llf
010
n >
m>
D
II 000 011
( n >
( m >
lllOIOOI
II Oll 101
II 101 001
II III 101
ll101001
00 Oll 000
00111000
D
(
(
JPmn
JP IHL)
JP IlX)
JP IlY)
JRJ
JRCj
3
3
6 If fabel
91f true)
3
9
D
D
I
2
3
HL.-pc'
6
IX.-PC.
D
2
6
IY.....PC.
JR NZj
00 110000
{J·2>
00101000
(J·2>
00100000
RET
11001001
RETf
Ilf
RETI
11101101
01001101
JR Zj
f IS false
"",-PC,
2
8
pc'+J-pc'
D
!
2
2
2
2
2
!
2
6
8
continue C=O
PC,+j-pC, C=I
6
continue. C=1
1
D
D
D
0)
1218,=0)
2
Br..... A,-A]$
[ IBC),~IHL).
Q
HL,-I~HL.
Br-I ..... Sr
RepeatQ1Dlhl
Br=O
Cr..... A.-A1
Br..... A.-A,s
6
5
INI
INIR
11101101
10100010
D
11101101
10110010
D
S
12
2
S
1418,>0)
1218,=0)
2
I
Note
z = 1.
=
Br-I
0
Z = O· Br-i
0
N
i MSB of Data
=
'*
:BC),~IHL).
X
I
X X
X S
X X
HLM+l ..... HL.
Br-l ..... Sr
Cr..... A.-AI
Br..... A,-AlI
[ IBC),~IHL).
Q HLRtl ..... HLR
Br-I .... Sr
Repeat Q until
8r=0
X
6
I
X
Cr..... Ao-Al
Br.... A,-Au
(continued)
=i
N = 0 MSB of Data = 0
~HITACHI
744
1
Hitachi Amenca, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy· Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Table 20 I/O (cont)
Flog
Addressing
7
Operation
Name
Mnemonics
Ope.d.
Output
OUT Im).A
11010011
( m )
IMMEO EXT
IND
REG REGI IMP
S
110 Byt••
D
2
State.
10
Operation
6
4
2
1
0
S Z H PlY N C
Ar-IAm),
m-A.-A,
AJ-.A.-An
OUT Ie).
11101101
01 g 1101
S
D
2
10
OUTO (m),g"·
11101101
IIOg 1101
S
D
3
13
OTOM"·
11101101
101101011
D
2
14
( m )
S
RI'-IBC)'
Ct-A.-A,
Dr-At-All
rlllOm),
m-Ao-A,
OO-A,-A"
IHL).-IOOC),
HI.,-I-HI.,
er-l-Ct
6
1
5
1
1
P
R
S
R
S
1
R
X
S
X
X
6
1
X
X
5
1
X
X
X
S
X
X
1
X
1
1
S
P
R
R
1
5
1
1
P
6
I
1
R
S
R
S
X
5
1
X
X
1
1
Br-l .... Sr
er-A.-A,
OO-A.-AII
OTDMR"·
11101101
10011011
S
D
2
16IB,'0)
14IB,=0)
[ IHL).-IOOC),
Q
6
~;~;~~rHI.,
Sf-I-Dr
Repeat Q until
8r=0
Cr-Ao-A,
OO-As-Au
OTDR
S
I1lGl101
10m 011
D
2
14(8r*0)
I iHLI.-IBC),
121B,=01
Q HI.,-I-HI.,
Sr-I-Sf
RepeatQuntli
8r=0
OUTI
S
11101101
10100011
D
2
12
Cr.... Ao-A,
Sr-A.-ALl
IHL).-IBCI,
HL.+l-HI.,
6
1
X
Sr-I .... Sf
Cr-A.-A,
Sr-A,-Au
OTIR
11101101
10110011
S
D
2
14(8r*0)
121B,=0I
IIHLI.-IBCI,
6
Q Hl.,tl-HL.
Sf-} ..... Sf
Repeat Quntil
8r=0
TST1Om"·
11101101
011101110
S
S
3
12
( m )
OTlM ••
11101101
10000011
S
D
2
14
2
16IB<*0)
141B,=0)
Cr ..... A.-A,
Sr-A.-A ll
(OOC1,'m
Cr-A.-A,
OO-A,-A u
IHLI.-IOOC),
HL.+l-HI.,
Cr+l-Cr
Sf-I-Sr
Cr-A,-A,
OO-A,-A ll
OTlMR ••
11101101
10010011
S
D
[ IHL).-IOOC),
6
1
R
Q HI., + l-HL.
Cr+l ....er
Sr-I-Dr
Repeat Q until
&=0
Cr-A.-A,
OUTO
11101101
10101011
S
D
2
12
OO ..... A.-A ,1
IHL).-IBC),
HL.-I-HI.,
Br-l-Br
Cr.... A.-A,
6
1
X
Sr-AI-A LI
= 1. Br- 1 = 0
O. Br-I *' 0
= I: MSBofData = 1
= 0: MSBofData = 0
Note: 5 Z
Z=
N
N
@HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819. (415) 589·8300
745
HD641180X, HD643180X, HD647180X
Special Control Instructions
Table 21 Special Control
-_._Operation
Name
i
Addressing
Mnemonics
Opcode
Special
Function
DAA
001001ll
Carry
CCF
SCF
OOllOlll
Control
CPU
Control
DI
El
HALT
IMO
IMI
1M2
NQP
SLP"'·
IMMEO EXT
IND
REG REGI IMP
SID
REL
i
Bytes! States
00 III III
11110011
1I111011
01110110
11101101
01000110
11101101
01010110
II 101 IOI
01011110
00 000 000
1I10lI01
01110110
Operation
I
4
Decimal
Adjust
Accumulator
I
I
3
3
C-C
I-C
I
I
I
2
3
3
3
6
O--'IEFu O....IEF1
2
6
2
6
I
2
8
3
l .....IEF" I..... JEFI
Z
Flag
4 2 1
H P/v N
C
I
I
I
7
6
S
I
P
R
R
7
7
CPU halted
Interrupt
mode 0
Interrupt
mode I
Interrupt
mode 2
No operation
Sleep
Note 7 Interrupts are not sampled at the end of DJ or EI.
~HITACHI
746
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
0
R I
R S
HD641180X, HD643180X, HD647180X
• INSTRUCTION SUMMARY IN ALPHABETICAL ORDER
MNEMONICS
Bytes
Machine Cycles
States
ADC A,m
2
2
6
ADC A,g
1
2
4
ADC A, (HL)
1
2
6
ADC A, (lX+d)
3
6
14
ADC A, (lY+d)
3
6
14
ADD A,m
2
2
6
ADD A,g
1
2
4
ADD A, (HL)
1
2
6
ADD A, (lX+d)
3
6
14
ADD A, (lY+d)
3
6
14
ADC HL,ww
2
6
10
ADD HL,ww
1
5
7
ADD IX,xx
2
6
10
ADD IY,yy
2
6
10
AND m
2
2
6
AND 9
1
2
4
AND(HL)
1
2
6
AND (IX+d)
3
6
14
AND (lY+d)
3
6
14
BIT b, (HL)
2
3
9
BIT b, (lX+d)
4
5
15
BIT b, (lY+d)
4
5
15
BIT b,g
2
2
6
CALL f,mn
3
2
6
(If condition is false)
3
6
16
(If condition is true)
(continued)
Note •• : New instructions added to Z80
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005· 1819 • (415) 589·8300
747
HD641180X, HD643180X, HD647180X
MNEMONICS
Bytes
Machine Cycles
States
CALL mn
3
6
16
CCF
1
1
3
CPD
2
6
12
CPDR
2
8
14
(If BCR*O and Ar*(HU M)
2
6
12
(If BC R= 0 or Ar= (HUM)
CP (HL)
1
2
6
CPI
2
6
12
CPIR
2
8
14
2
6
(If BCR*O and Ar* (HUM)
12
(If BC R= 0 or Ar= (HL)M)
CP (IX + d)
3
6
14
CP (lY+d)
3
6
14
CPL
1
1
3
CPm
2
2
6
CP 9
1
2
4
DAA
1
2
4
DEC (HL)
1
4
10
DEC IX
2
3
7
DECIY
2
3
7
DEC (lX+d)
3
8
18
DEC (lY+d)
3
8
18
DEC 9
1
2
4
DEC ww
1
2
4
DI
1
1
3
(continued)
.HITACHI
748
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
MNEMONICS
Bytes
Machine Cycles
States
2
5
9 (If Br*'O)
2
3
7 (If Br=O)
EI
1
1
3
EX AF,AF'
1
2
4
EX OE,HL
1
1
3
EX (SP),HL
1
6
16
EX (SPl.IX
2
7
19
EX (SPl.IY
2
7
19
EXX
1
1
3
HALT
1
1
3
1M 0
2
2
6
1M 1
2
2
6
1M 2
2
2
6
INC 9
1
2
4
INC (HL)
1
4
10
INC (lX+d)
3
8
18
INC (lY+d)
3
8
18
INCww
1
2
4
INC IX
2
3
7
INC IY
2
3
7
INA,(m)
2
3
9
IN g,(C)
2
3
9
INI
2
4
12
INIR
2
6
14 (If Br*'O)
2
4
12 (If Br=O)
INO
2
4
12
INOR
2
6
14 (If Br*'O)
OJNZj
(continued)
@HITACHI
Hitachi Amenca, Ltd • Hitachi Plaza' 2000 Sierra Pomt Pkwy, • Bnsbane, CA 94005-1819 • (415) 589-8300
749
HD641180X, HD643180X, HD647180X
MNEMONICS
Bytes
Machine Cycles
States
INOR
2
4
12 (If Br=O)
INO g,(m)**
3
4
12
JP f,mn
3
2
6
(If f is false)
3
3
9
(If f is true)
JP (HL)
1
1
3
JP (IX)
2
2
6
JP (ly)
2
2
6
JP mn
3
3
9
JR j
2
4
8
JR C,j
2
2
6
(If condition is false)
2
4
8
(If condition is true)
JR NC,j
2
2
6
(If condition is false)
2
4
8
(If condition is true)
JR Z,j
2
2
6
(If condition is false)
2
4
8
(If condition is true)
JR NZ,j
2
2
6
(If condition is false)
2
4
8
(If condition is true)
(continued)
~HITACHI
750
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD641180X, HD643180X, HD647180X
MNEMONICS
Bytes
Machine Cycles
States
LD A, (BC)
1
2
6
LD A, (DE)
1
2
6
LD A,I
2
2
6
LD A, (mn)
3
4
12
LD A,R
2
2
6
LD (BC),A
1
3
7
LDD
2
4
12
LD (DE),A
1
3
7
LD wW,mn
3
3
9
LD wW,(mn)
4
6
18
LDDR
2
6
14 (If BCR'*O)
2
4
12 (If BCR=O)
LD (HU,m
2
3
9
LD HL,(mn)
3
5
15
LD (HU,Q
1
3
7
LDI
2
4
12
LD I,A
2
2
6
LDIR
2
6
14 (If BCR'*O)
2
4
12 (If BCR=O)
LD IX,mn
4
4
12
LD IX,(mn)
4
6
18
LD (lX+d),m
4
5
15
LD OX+d),Q
3
7
15
LD IY,mn
4
4
12
LD IY,(mn)
4
6
18
LD (lY+d),m
4
5
15
LD (lY+d),Q
3
7
15
(continued)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Pomt Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
751
HD641180X, HD643180X, HD647180X
MNEMONICS
Machine Cycles
Bytes
States
LD (mn),A
3
5
13
LD (mn),ww
4
7
19
LD (mn),HL
3
6
16
LD (mn),1X
4
7
19
LD (mn),IY
4
7
19
LOR,A
2
2
6
LD g,(HL)
1
2
6
LO g,(IX+d)
3
6
14
LD g,(IY+d)
3
6
14
LOg,m
2
2
6
LOg,g'
1
2
4
LD SP,HL
1
2
4
LD SP,IX
2
3
7
LD SP,IY
2
3
7
MLTww"
2
13
17
NEG
2
2
6
NOP
1
1
3
OR(HU
1
2
6
OR (lX+d)
3
6
14
OR (lY+d)
3
6
14
ORm
2
2
6
OR 9
1
2
4
OTDM"
2
6
14
OTDMR"
2
8
16 (If Br*'O)
2
6
14 (If Br=O)
2
6
14 (If Br*'O)
2
4
12 (If Br=O)
OTDR
(continued)
•
752
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
HD641180X, HD643180X, HD647180X
States
Bytes
Machine Cycles
OTIM"
2
6
14
OTIMR"
2
8
16 (If Br*O)
2
6
14 (If Br=O)
2
6
14 (If Br*O)
2
4
12 (If Br=O)
OUTO
2
4
12
OUTI
2
4
12
OUT (ml.A
2
4
10
2
4
10
3
5
13
POP IX
2
4
12
POP IV
2
4
12
POP zz
1
3
9
PUSH IX
2
6
14
PUSH IV
2
6
14
PUSH zz
1
5
11
RES b,(HL)
2
5
13
RES b,(lX+d)
4
7
19
RES b,(lV+d)
4
7
19
RES b,g
2
3
7
RET
1
3
9
RET f
1
3
5
MNEMONICS
OTIR
OUT (Cl.g
OUTO (m),g
..
(If condition is false)
1
4
10
(If condition is true)
RETI
2
10
22
RETN
2
4
12
(continued)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819· (415) 589-8300
753
HD641180X, HD643180X, HD647180X
Bytes
Machine Cycles
States
RLA
1
1
3
RlCA
1
1
3
RlC (Hl)
2
5
13
RlC (lX+d)
4
7
19
RlC (lY+d)
4
7
19
RlC 9
2
3
7
RlD
2
8
16
Rl (HL)
2
5
13
Rl (lX+d)
4
7
19
Rl (lY+d)
4
7
19
Rl 9
2
3
7
RRA
1
1
3
RRCA
1
1
3
RRC (Hl)
2
5
13
RRC (lX+d)
4
7
19
RRC (lY+d)
4
7
19
RRC 9
2
3
7
RRD
2
8
16
RR (HL)
2
5
13
RR (lX+d)
4
7
19
RR (lY+d)
4
7
19
RR 9
2
3
7
RST v
1
5
11
SBe A,(HL)
1
2
6
SBC A,(lX+d)
3
6
14
SBe A,(lY+d)
3
6
14
2
2
6
MNEMONICS
SBe A,m
(contmued)
o
754
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300
HD641180X, HD643180X, HD647180X
Bytes
Machine Cycles
SBC A,g
1
2
4
SBC HL,ww
2
6
10
SCF
1
1
3
SET b,(HL)
2
5
13
SET b,(lX+d)
4
7
19
SET b,(lY+d)
4
7
19
SET b,g
2
3
7
SLA (HL)
2
5
13
SLA (lX+d)
4
7
19
SLA (lY+d)
4
7
19
SLA 9
2
3
7
SLp··
2
2
8
SRA(HU
2
5
13
SRA (lX+d)
4
7
19
SRA (lY+d)
4
7
19
SRA 9
2
3
7
SRL (HL)
2
5
13
SRL (lX+d)
4
7
19
SRL (lY+d)
4
7
19
SRL 9
2
3
7
SUB (HU
1
2
6
SUB (lX+d)
3
6
14
SUB (lY+d)
3
6
14
SUB m
2
2
6
SUB 9
1
2
4
··TSTIO m
3
4
12
··TST 9
2
3
7
MNEMONICS
States
(continued)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300
755
HD641180X, HD643180X, HD647180X
Bytes
Machine Cycles
States
TST m··
3
3
9
TST (HL)**
2
4
10
XOR (HL)
1
2
6
XOR (lX+d)
3
6
14
XOR (lY+d)
3
6
14
XOR m
2
2
6
XOR 9
1
2
4
MNEMONICS
~HITACHI
756
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
.OPCODEMAP
Table 22 First Opcode Map
Instruction format: XX
eo
wwlLo
AIQ
DE
HL
Lo
SP
BC
NZ
1Lo-0-7)
B
C
0
~
II
~
II>
E
H
L
HL
A
B
C
0
E
H
L
I (HL)
A
LO
~
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
0
H : (HL) B 1 0 i H i(HL)
B
0000 0001 0010 0011 0100 0101 0110 0111
1
7
4
5
0
2
3
6
NOP OJNZ JR NZ.I JRNC.)
LO _.mn
:1Note 1
LO (_). A LO(om) LO(nn)
,,
,
,
H..
A
INC_
,,,
LO g..
INC g
,,
14Note 11
DEC g
,!Note 11
LO g. m
,INola 11
RLCAI RLA I oAA I SCF
WF.AF] JR I IJR Z.II JR c.
ADD HL._
Lo A. (_) LD tt-. LO A.'
(om) (m)
DEC_
LO g.s
INC g
DEC g
Lo g.m
RRCA RRA I CPL I CCF
o J 1 I 2 I 3 41 51 6i 7
C
E.lLJA
C1 Ei Li A
glLo-8-A
AF
P
30H
RET I
NDA
SUB. AND • OR.
zz
I
v
0
1
popzz
JP I. 1M
JP mllJT(JnI. EXIIPi 01
2
3
H..
A
CALL I. 1M
PUSH zz
m;2i ~~ ~~ _21 AlIDA._ SUBm AND "'lOR m
RST v
RET I
RET EXX JP (HL) LD 51'.
s
4
5
6
7
8
9
HI.
JP I.IM
NlC A SBCA XOR • CPs T_2 NA.jllJjOOE.It.
•
•
CAll.~
======~)I= ==== =
31\T- 3 _
_21 ~21 _21 _21 ADC~~sacA.~XM
8
9
EI
CALL I.IM
A
B
~
"'lCP m
RST v
CioiEi F
z C PE M
08H ISH 28H 38H
Lo
Notes:
7
HL
PO
20H
OOH
1000 1001 1010 1011 1100 1101 1110 1111
A
F
B
8
9
C
0
E
.
====~)I ====~
0
DE
NC
IOH
8
A
B
C
0
E
F
I
v
F
1. (HU replaces g.
2. (HU replaces s.
3. If DDH is added as first opcode for the instructions which have HL or (HU as an operand
d).
in table 1. the instructions are executed replacing HL with IX and (HU with (IX
+
ex:
22H: LD (mn). HL
DDH 22H: LD (mn). IX
If FDH is added as first opcode for the instructions which have HL or (HU as an operand
in table 1. the instructions are executed replacing HL with IV and (HU with (IV
d).
+
ex:
34H: INC (HU
FDH 34H: INC (IV
+
d)
However. JP (HU and EX DE. HL are exceptions. Note the followings:
If DDH is added as first opcode for JP (HU. (IX) replaces (HU as operand and JP (IX) is
executed.
If FDH is added as first opcode for JP (HU. (IV) replaces (HL) as operand and JP (IV) is
executed.
Even if DDH or FDH is added as first opcode for EX DE. HL. HL is not replaced and the
instruction is regarded as illegal.
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
757
HD641180X, HD643180X, HD647180X
Table 23 Second Opcode Map
Instruction format: CB XX
b (Lo -
o
B
0
0
E
H
L
=
;;: (HL)
A
II
! B
0
0
E
H
L
(HL)
A
.
LO
~
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
0
0
E
F
0 -
7)
o
o
I 2 I 4 I 6
I 2 I 4 I 6
I 2 I 4 I 6
0000 0001 0010 0011 0100/0101/0110/0111 l000L1001 J 101011011 1100111011111011111
1
0
2
3
8 I 9 I A I B
I 0 I E I F
4 I 5 I 6 I 7
o
0
-r
2-
--3
RLC g RL g SLA g
BIT b.g
4""'
SET b.g
RES b.g
-r
---------------- ---------------- ---------------- e-
---1) ----- -(Note ,) (Note 1)
-(Note
--- --- - - ---
- - - - - -(Note -;)- - - - - - -- - -
--iN~t~
1)- - - -- -
- - - - - iNot. 11 - - - --
--r
-49
~
8
RRC g RR g SRAg SRLg
BIT b.g
SET b.g
RES b.g
--c
0
-------------------------------1)--(Note 1)
(Note 1)
------- -------- ---------------- ---------------- E
--(N~t~
(Note 1) (Note 1) (Note 1) (Note 1)
0
1
2
3
4 I 5
1 / 3
I 6
/ 5
I 7
/ 7
8 I 9
1 I 3
I A I B
I 5 I 7
b (Lo -
8
o
I
o
1
/
3
-r
I E I F
/ 5 / 7
nF)
table 2. the Instructlons are executed replacing (HLl with (IX
+
If FDH IS added as first ope ode for the Instructions which have (HU as operand In table 2. the Instructions are executed replacing (HL) with (lY
d)
+
Note 1 If DDH IS added as 111'St ope ode for the Instructions which have (HLl as operand
d)
In
Table 24 Second Opcode Map
Instruction format: ED XX
ww (Lo -
BO
Lo
~
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
0
0
E
F
L DE
All)
J HL / SP
g (Lo-O-71
B
BID I H /
o / H /
OOOOj00011 001 OJ 0011 0100 0101/011010111 1000/1001
4
5 I 6 I 7
8 I 9
o I 1 I 2 I 3
IN g. (0)
INO g. (m)
OUT (O).g
OUTO (m).g I
I
SBO HL.'MN
I
LO (mn). 'MN
OTIMIOTIMR
TST g
TST mI TSTIO m
ITST (HL) NEG
RETN
1M 0 1M 1
LD I.A LD A,I RRDJ
INO g. (m)
IN g. (0)
aUTO (m).g
aUT (O).g
ADO HL.'MN
LO 'MN. (mn)
aTOMloTOMR
TST g
MLT'MN
RETI
1M 2
LD R.A LD A,R RLOI
4
0 / 1 I 2 / 3
5
8 I 9
6 / 7
0 I E I L I A
0
E
L I A
g (Lo-8-F)
1010
A
LOI
OPI
INI
OUTI
1011 1100/1101/1110/1111
B
o I 0 I ElF
LOIR
OPIR
INIR
OTIR
f-3
~
f-T
r--e
~
rsiJ5l
LOO
OPO
INO
auTO
r-a
LOOR
OPOR
INOR
OTOR
r--g
I---A
~
f--T
r--o
f--'E
~
A
B
o
/
0
/ ElF
~HITAOHI
758
0
r--y-f-2
Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
• BUS AND CONTROL SIGNAL CONDITION IN EACH MACHINE CYCLE
Machine
WR
lna1rUction
Cvcie
Stat.
Address
Data
RD
ADDHl.,ww
MC,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
0
MC,-
TiTiTiTi
0
ME
IDE
LlR
HALT ST
Z
MC.
MC,
T,T,T3
lstopcode
Address
1st
opcode
0
0
0
MC,
T,T,T3
2ndopcode
Address
2nd
opcode
0
0
0
MC3MC.
TiTiTiTi
MC,
T,T,T3
lstopcode
Address
1st
opcode
0
0
0
MC,
T,T,T3
2ndopcode
Address
2nd
opcode
0
0
0
MC3MC.
TiTiTiTi
AODA.g
AOCA.g
SUBg
SBCA.g
ANDg
ORg
XORg
CPg
MC,
T,T,T3
0
0
0
0
MC,
Ti
ADDA.m
ADCA.m
SUBm
SBCA.m
ANDm
ORm
XORm
CPm
MC,
T,T,T3
lstopcode
Address
1st
opcode
0
0
0
0
MC,
T,T,T3
1st operand
Address
m
0
0
ADDA.(HU
ADCA. (HU
SUB(HU
SBCA. (HU
AND(HU
OR(HU
XOR(HU
CP(HU
MC,
T,T,T3
lstopcode
Address
1st
opcode
0
0
0
0
MC,
T,T,T.
HL
Data
0
0
ADDA. (IX + d)
ADD A. (IY+ d)
ADCA. (lX+d)
ADCA. (iY+d)
SUB (lX+d)
SUB (lY+d)
SBC A. (iX+d)
MC,
T,T,T.
lstopcode
Address
1st
opcode
0
0
0
0
MC,
T,T,T3
2ndopcode
Address
2nd
opcode
0
0
0
ADDiX.xx
ADDiY.VV
ADCHl.,ww
SBCHl.,ww
Z
0
Z
lstopcode
Address
1st
opcode
Z
(continued)
Note: • (Address): invalid
Z (Data): High impedance.
•• : New instructions added to ZBO
•
HITACHI
Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
759
HD641180X, HD643180X, HD647180X
Machine
Cycle
States
Instruction
SBC A. (lY+d)
AND (lX+d)
AND (lY+d)
OR (IX+d)
OR (lY+d)
XOR (lX+d)
XOR (lY+d)
CP (IX+d)
CP (lY+d)
BIT b.g
BIT b. (HL)
CALL mn
&,.,,:
CAll f.mn
RD
d
0
0
Data
0
0
1st opcode
Address
1st
opcode
0
0
0
2nd opcode
Address
2nd
opcode
0
0
0
1st opcode
1st
0
0
0
Address
opcode
0
0
0
MC,MC,
TiT!
MC.
T,T,T3
IX+d
IY+d
MC,
T1T2T3
MC,
T,T,T 3
MC,
T1T2T3
T,T,T3
WR
ME
IOE
LIR
2nd opcode
2nd
Address
opcode
MC3
T,T,T3
Hl
Data
0
0
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
MC3
T,T,T3
1st operand
Address
d
0
0
MC,
T,T2T3
3rd opcode
Address
3rd
0
0
T,T,T3
IX+d
IY+d
Data
0
0
MC,
T,T,T3
1st opcode
Address
1st
opcode
0
0
MC,
T1T2T3
1st operand
Address
0
0
MC,
T,T2T3
2nd operand
Address
0
0
m
MC,
TI
MC,
T1T2T3
SP-l
PCH
0
MC.
T,T,T3
SP-2
PCl
0
MC,
T,T2T3
1st opcode
1st
opcode
0
0
0
0
0
0
0
Z
Address
T,T,T3
0
opcode
MC,
MC,
HALT ST
Z
MC,
(If cond~lon
IS false)
Data
1st operand
Address
T,T,T3
MC,
BIT b, (lX+d)
BIT b. (lY+d)
Address
MC,
1st operand
Address
0
0
0
0
0
0
(continued)
.HITACHI
760
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Machines
States
Cycle
Instruction
CALL I,mn
01 condilton
is true)
Address
Dats
RD
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
MC,
T ,T ,T,
1st operand
Address
n
0
0
MC,
T ,T ,T,
2nd operand
Address
m
0
0
WR
ME
IDE
LlR
HALT ST
0
0
MC.
Ti
MC5
T ,T ,T,
SP-1
PCH
0
0
MC.
T ,T ,T,
SP-2
PCl
0
0
CCF
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
0
0
CPI
CPO
MC,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
0
MC,
T,T;>T 3
2nd opcode
Address
2nd
opcode
0
0
0
Hl
Data
0
0
CPIR
CPDR
(H Bc,.*O and
Ar*(HLl,,)
CPIR
CPDR
(H Bc,.=O or
Ar=(HLl,,)
Z
MC3
T ,T ,T 3
MC.MC.
TiT.T.
MC,
T 1T2T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T ,T ,T 3
2nd opcode
Address
2nd
opcode
0
0
0
MC3
T,T,T,
Hl
Data
0
0
MC.MC.
TiT.T.T.T.
MC,
T1T2T3
1si opcode
Address
1st
opcode
0
0
0
MC,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
Hl
Data
0
0
Z
0
Z
0
MC,
T ,T ,T 3
MC.MC.
TiT.Ti
CPl
MC,
T ,T,T3
1st opcode
Address
1st
opcode
0
0
0
0
DAA
MC,
T ,T,T3
1st opcode
Address
1st
opcode
0
0
0
0
0
0
0
0
01 (Note 1)
MC,
T.
MC,
T,T,T,
Z
Z
1st opcode
Address
1st
opcode
(continued)
Note' 1 Interrupt request .s not sampled
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
761
HD641180X, HD643180X, HD647180X
Machine
Instruction
Cycle
States
Address
Data
RD
DJNZ I
(If 8r*0)
MC,
T,T,T3
1st opccde
Address
1st
opcode
0
0
1st operand
Address
)-2
0
0
0
0
DJNZ)
(If 8r=0)
MC,
TI (Note 2)
MC3
T,T,T3
MC,MC,
T,T,
MC,
T,T,T3
WR
ME
IOE
LIR
HALT ST
0
0
0
0
Z
Z
1st opcode
Address
1st
opcode
MC,
TI (Note 1)
MC3
T,T 2T 3
1st operand
Address
)-2
0
0
EI (Note 3)
MC,
T 1T 2T 3
1st opcode
Address
1st
opcode
0
0
0
0
EX DE. HL
MC,
T ,T ,T 3
1st opcode
Address
1st
opcode
0
0
0
0
EX AF. AF'
MC,
T ,T ,T 3
1st opcode
Address
1st
opcode
0
0
0
0
MC,
TI
EX (SP). HL
MC,
T,T 2 T 3
0
0
0
EXX
EX (SP).IX
Z
Z
1st opcode
Address
1st
opcode
0
0
MC,
T,T,T3
SP
Data
0
0
MC3
T,T,T3
SP+l
Data
0
0
MC,
TI
MC,
T,T,T 3
SP+ 1
H
0
0
MC,
T,T,T3
SP
L
0
0
MC,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
EX (SPI.lY
Z
MC3
T,T,T3
SP
Data
0
0
MC,
T,T2T3
SP+l
Data
0
0
MC,
TI
Z
Note 2 DMA. refresh. or bus release cannot be executed after this state (Request IS Ignored)
3 Interrupt request
IS
(contInued)
not sampled
~HITACHI
762
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Instruction
EX (SP).IX
EX (SPl.IV
HALT
Machine
St_
Cycle
Address
Data
WR
ME
MC.
T,T,T,
SP+l
IXH
IVH
RD
0
0
MC,
T,T,T,
SP
IXL
IVL
0
0
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
0
Next opcode
Address
Next
opcode
0
0
0
IOE
UR
HALf
ST
0
0
0
!MO
1M 1
1M2
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T,T,
2nd opcode
Address
2nd
opcode
0
0
0
INC 9
DEC 9
MC,
T ,T,T,
lst opcode
Address
lst
opcode
0
0
0
0
MC,
Ti
INC (HL)
DEC (HU
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
0
0
HL
Date
0
0
0
INC (IX + d)
INC (lV+d)
DEC (lX+d)
DEC (lV+d)
INCww
DEC ww
INC IX
INC IV
DEC IX
DEC IV
0
Z
MC,
T,T,T,
MC,
Ti
MC.
T ,T ,T,
HL
Date
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
0
MC,
T ,T ,T,
2nd opcode
Address
2nd
opcode
0
0
0
MC,
T ,T,T,
1st operand
Address
d
0
0
MC.MC,
TiTi
MC.
T,T,T,
0
0
Z
0
0
Z
IX+d
IV+d
Data
Z
MC,
Ti
MC.
T,T,T,
IX+d
IV+d
Data
MC,
T,T,T,
1st opcode
Address
1st
opcode
MC,
Ti
Me,
T,T,T,
lstopcode
Address
MC,
T ,T,T,
2nd opcode
Address
MC,
Ti
0
0
0
0
0
0
1st
opcode
0
0
0
0
2nd
opcode
0
0
0
Z
Z
(conMued)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1B19 • (415) 589-8300
763
HD641180X, HD643180X, HD647180X
Machine
Instruction
Cycle
States
Address
Data
RD
IN A,(m)
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
MC,
T,T,T,
1st operand
Address
m
0
0
MC,
T1T2T3
m to Ao-A7
Data
0
WR
ME
IOE
LlR
HALT
ST
0
0
0
0
A toAe-A"
IN g,(C)
INO g,(m)"
INI
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T2T3
2nd opcode
Address
2nd
opcode
0
0
0
MC,
T,T2T3
BC
Data
0
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
0
MC,
T1T2T3
2nd opcode
Address
2nd
opcode
0
0
0
MC,
T,T,T,
1st operand
Address
m
0
0
MC,
T1T2T3
m to AD-A,
OOH to Ae-A15
Data
0
MC,
T1T2T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T,T,
2nd opcode
Address
2nd
opcode
0
0
0
0
IND
INIR
MC,
T,T,T,
BC
Data
T,T,T,
HL
Data
MC,
T1T2T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T1T2T3
2nd opcode
Address
2nd
opcode
0
0
0
0
INIR
INDR
(If 8r=0)
MC,
T,T,T,
BC
Data
MC,
T1T2T3
HL
Data
MCsMC,
TITI
MC,
T ,T ,T,
0
0
MC,
INDR
(If Br*O)
0
0
0
0
0
0
0
0
0
Z
1st opcode
1st
opcode
0
0
0
Address
a
0
MC,
T1T2T3
2nd opcode
Address
2nd
opcode
0
MC,
T,T2T3
BC
Data
a
MC,
T,T,T,
HL
Data
0
a
a
a
(continued)
~HITACHI
764
Hitachi Amenca, Ltd .• Hitachi Plaza· 2000 Sierra POint Pkwy· Bnsbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Machine
Instruction
Cycle
States
Address
Data
AD
JP mn
MC,
T,T,T3
1st opcode
1st
0
0
Address
opcode
0
0
m
0
0
1 st
0
0
0
0
0
0
0
0
m
0
0
1st opcode
1st
0
Address
opcode
0
MC,
T,T,T 3
1st operand
WR
ME
IOE
DR
HALT
ST
0
0
0
0
0
0
0
0
0
0
0
0
Address
MC3
T 1T 2T 3
2nd operand
Address
JP f,mn
IIf f IS false)
MC,
MC,
T,T,T3
T ,T2T 3
1st opcode
Address
opcode
1st operand
Address
MC,
JP f,mn
T ,T2T3
IIf f IS true)
MC,
T,T;:>T3
MC3
T,T,T 3
1st opcode
1 st
Address
opcode
1st operand
Address
2nd operand
Address
MC,
JP (HLI
MC,
JP IIX)
JP (IY)
JR I
T,T2T 3
T,T,T3
MC,
T,T 2 T3
MC,
T,T 2 T3
MC,
T,T,T3
1st opcode
1st
Address
opcode
2nd opcode
2nd
Address
opcode
1st opcode
1st
Address
opcode
1st operand
1-2
---------------._--0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address
JR C,I JR NC,I
JR Z,I JR NZ,I
(If condition
MC3MC,
TITI
MC,
T,T,T3
MC,
T,T,T3
IS false)
MC,
T,T,T,
JR Z,I JR NZ,I
(If condition
MC,
T1T..,T3
true)
LD g,g'
LD g,m
1st opcode
1st
Address
opcode
1st operand
1-2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address
JR C,I JR NC,I
IS
Z
1st opcode
1st
Address
opcode
1st operand
1-2
Address
MC3Me',
TITI
MC,
T,T,T3
MC,
TI
MC,
T 1T 2 T3
MC,
T1T2T3
Z
1st opcode
1st
Address
opcode
Z
1st opcode
1 st
Address
opcode
1st operand
m
Address
(continued)
~HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819' (415) 589-8300
765
HD641180X, HD643180X, HD647180X
Machine
Instruction
LD g. (HU
LD g. (lX+d)
LD g. (lV+d)
LD (HU.g
LD (lX+d).g
LD (lV+d).g
LD (HU.m
LD (lX+d).m
LD (IV+d).m
LD A. (Be)
LD A. (DE)
Cycle
Me,
States
Address
Data
RD
T ,T ,T,
1st opcode
Address
1st
opcode
0
Viii
0
MC,
Me,
T,T,T,
HL
Data
0
0
T,T,T,
1st opcode
Address
1st
opcode
0
Me,
T,T,T,
2nd opcode
Address
2nd
opcode
Me,
T,T 2 T,
1st operand
Address
d
Me.Me.
Me.
TiTi
T ,T,T,
IX+d
IV+d
Me,
T,T,T,
Me,
Me,
Me,
ME
IOE
OR
HALT ST
0
0
0
0
0
0
0
0
0
0
Data
0
0
1st opcode
Address
1st
opcode
0
0
T,T,T,
HL
9
T,T,T,
1st opcode
Address
1st
opcode
0
Me,
T,T,T,
2nd opcode
Address
2nd
opcode
Me,
T ,T ,T,
1st operand
Address
d
Me.Me.
Me,
TiTiTi
T,T,T,
lX+d
IV+d
9
Me,
T,T,T,
1st opcode
Address
1st
opcode
0
0
Me,
T,T,T,
1st operand
Address
m
0
0
Me,
Me,
T,T 2 T,
HL
Date
T,T,T,
1st opcode
Address
1st
opcode
0
Me,
T,T 2T,
2nd opcode
Address
2nd
opcode
MO,
T,T,T,
1st operand
Address
Me.
T,T 2 T,
Me.
Me,
z
0
0
0
0
0
0
0
0
0
0
z
Ti
0
0
z
0
0
0
0
0
0
0
0
0
0
d
0
0
2nd operand
Address
m
0
0
T,T,T,
lX+d
IV+d
Date
T,T,T,
1st opcode
Address
1st
opcode
0
0
0
0
0
0
0
0
(continued)
•
766
HITACHI
Hitachi America. Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• arisbane. CA 94005·1819 • (415) 589·8300
HD641180X, HD643180X, HD647180X
Machine
Instruction
Cycle
States
Address
Deta
RD
LD A, (Be)
Me,
T,T2T 3
Be
Data
0
0
Me,
T,T,T,
1st opcode
Address
1st
opcode
0
0
Me,
T,T,T,
1st operand
Address
n
0
0
Me,
T ,T ,T,
2nd operand
m
0
0
LD A, (DE)
WR
ME
IOE
LIR
HALT
ST
DE
LD A,(mn)
0
0
0
0
0
0
0
Address
LD (Be),A
Me.
T,T,T,
mri
Data
0
0
Me,
T ,T ,T,
1st opcode
Address
1st
opcode
0
0
Be
DE
A
1st opcode
1st
opcode
LD (DE),A
LD (mn).A
Me,
TI
Me,
T,T2T3
Me,
T,T,T 3
z
Address
Me,
T,T,T,
Me,
T,T,T,
1st operand
Address
2nd operand
m
0
0
0
0
0
0
0
0
Address
(Note 4)
LDA,I
LD A,R
LD I,A
TI
Me,
T,T 2T 3
mn
A
Me,
T,T,T 3
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T,T,
2nd opcode
Address
2nd
0
0
0
opcode
1st
opcode
0
0
0
0
0
0
m
0
0
1st opcode
1st
0
0
0
0
Address
opcode
0
0
0
LD R.A
LD
WW,
mn
z
Me.
Me,
T,T 2T 3
1st opcode
Address
Me,
T ,T ,T,
1st operand
Address
Me,
T,T2T 3
2nd operand
0
0
Address
Me,
LD IX,mn
T,T,T,
LD IY,mn
Me,
T,T,T,
Me,
T,T,T,
Me.
T,T,T,
2nd opcode
2nd
Address
opcode
1st operand
Address
n
0
0
2nd operand
m
0
0
1 st
opcode
0
0
Address
1st operand
n
0
0
Address
LD HL, (mn)
Me,
Me,
T,T,T,
T ,T ,T,
1st opcode
0
0
Address
(continued)
Note 4 Interrupt request is not sampled
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
767
HD641180X, HD643180X, HD647180X
Machine
WR
ME
Instruction
Cycle
States
Addre..
Date
RD
LD HL, (mnl
Me,
T,T,T.
2nd operand
Address
m
0
0
T,T,T,
mn
Data
0
0
T,T,T.
mn+l
Data
0
0
LDww.(mnl
Me.
Me.
Me,
T,T,T,
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T,T,
2nd opcode
Address
2nd
opcode
0
0
0
Me,
T,T,T,
1st operand
Address
n
0
0
Me.
T ,T,T,
2nd operand
Address
m
0
0
Me.
Me6
Me,
T,T,T,
mn
Data
0
0
T,T,T,
mn+l
Data
0
0
T,T,T,
1st opcode
Address
1st
0
0
0
opcode
0
LD 1X,(mnl
LD IY.(mnl
LD (mnl.HL
Me,
T,T,T.
2nd opcode
Address
2nd
opcode
0
0
Me,
T,T,T,
1st operand
Address
n
0
0
Me.
T,T,T,
2nd operand
Address
m
0
0
Me.
Me6
Me,
T,T,T,
mn
Data
0
0
T,T,T,
mn+l
Data
0
0
T,T,T,
1st opcode
Address
1st
opcode
0
0
Me,
T,T,T,
1st operand
Address
n
0
0
Me,
T,T,T,
2nd operand
Address
m
0
0
Me.
Me.
Me.
T,T,T3
mn
L
0
0
T,T,T.
mn+l
H
0
0
IOE
LlR
HAi:'f
ST
0
0
0
0
z
T.
(continuedl
eHITACHI
768
Hitachi America. Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane. CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Machine
Instruction
Cycle
States
Address
Data
lID
LD (mnl.ww
Me,
T 1T 2T 3
1st opcode
1st
0
0
0
Address
opcode
0
WR
ME
Me,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
Me3
T,T,T3
1st operand
Address
n
0
0
Me,
T,T 2 T3
2nd operand
m
0
0
IOE
LlR
HALT
ST
0
Address
LD (mn),IX
LD (mn),IY
z
Me,
TI
Me,
T1T2T3
mn
wwL
0
Me,
T1T2T3
mn+l
wwH
0
Me,
T,T2T3
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T,T3
2nd opcode
2nd
opcode
0
0
0
Address
1st operand
n
0
0
2nd operand
Address
m
0
0
Me3
T,T 2T3
0
0
0
Address
Me,
T1T2T3
z
Me,
TI
Me,
T,T2T3
mn
IXL
IYL
0
0
Me,
T,T2T3
mn+l
IXH
0
0
IYH
LD SP, HL
LD SP,IX
Me,
T ,T2T 3
Me,
TI
Me,
T,T2T 3
LD SP,IY
Me,
T,T,T3
1st opcode
1st
Address
opcode
0
0
0
0
0
0
0
0
0
0
z
1st opcode
1 st
Address
opcode
2nd opcode
2nd
opcode
Address
LDI
0
Me3
TI
Me,
T1T2T3
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T2T3
2nd opcode
Address
2nd
opcode
0
0
0
Me 3
T,T 2T 3
HL
Data
0
Me,
T,T,T3
DE
Data
LDD
Z
0
0
0
0
(continued)
~HITACHI
Hitachi America, Ltd • Hitachi Plaza· 2000 Sierra POint Pkwy· Brisbane, CA 94005-1819 • (415) 589-8300
769
HD641180X, HD643180X, HD647180X
Instruction
LDIR
LDDR
Of Bc,,*O)
LDIR
LDDR
Ilf Bc,,=o)
Machine
Cycle
States
WR
Address
Data
RD
Me,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
0
ME
IOE
LlR
HALT ST
0
0
Me3
T,T,T3
HL
Data
Me.
T,T,T3
DE
Data
Me.Me.
TiTi
Me,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
0
0
0
z
0
0
Me3
T,T,T3
HL
Data
Me.
T,T,T3
DE
Data
Me,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T,T,
2nd opcode
Address
2nd
opcode
0
0
0
MC3Me"
TiTlTiTi
TiTiTiTi
TiTiTi
Me,
T,T,T,
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
NOP
Me,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
0
OUT (m).A
Me,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
0
Me,
T,T,T3
1st operand
Address
m
0
0
Me3
Ti
Me.
T,T,T3
m to Ao-A,
A to A.-A ..
A
MLTww··
NEG
0
0
0
Z
0
z
0
0
(continued)
~HITACHI
770
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
HD641180X, HD643180X, HD647180X
Instruction
Machine
Cycle
States
Address
Data
RD
OUT (C),g
MC,
T1T2T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
OUTO (m),g··
OTIM··
OTOM··
OTIMW·
OTOMW·
Uf Br*O)
OTIMW·
OTDMR··
(If Br=O)
WR
ME
IOE
LlR
MC3
T,
MC,
T ,T,T3
BC
g
MC,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
MC3
T ,T,T 3
1st operand
Address
m
0
0
MC,
T,
MC,
T,T,T3
m to Ao-A,
DOH to A.-A"
g
MC,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T ,T,T,
2nd opcode
Address
2nd
opcode
0
0
0
HALT
ST
0
Z
0
0
0
Z
0
0
MC3
T,
MC,
T,T,T3
HL
Data
MC,
T,T,T3
C to Ao-A,
DOH to A.-A"
Data
MC.
T,
MC,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
0
Z
0
0
0
0
Z
MC3
T,
MC,
T,T,T3
HL
Data
MC,
T,T,T3
C to Ao-A,
OOH to A.-A"
Data
MC.MC.
TiTiTi
MC,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
0
Z
0
0
0
0
Z
MC,
Ti
Me,
T,T,T3
HL
Data
MC.
T,T,T3
C to Ao-A,
OOH to A.-A"
Data
MC.
Ti
0
Z
0
0
0
0
Z
(conllnued)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Bnsbane, CA 94005-1819 • (415) 589-8300
771
HD641180X, HD643180X, HD647180X
Imnrvctlon
OUTI
OUTO
OTIR
OTDR
/IfBr*O)
OTf!
OTDR
(If
111=0)
POP zz
POP IX
POPIY
Machine
Cycle
Stat..
WR
ME
IOE
Addre..
Date
RD
Me,
T,T,T3
1st opcode
Address
lst
opcode
0
0
0
Me,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
0
LlR
HALT ST
0
Me3
T,T,T3
HL
Data
Me.
T,T,T3
BC
Data
1
1
Me,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
0
Me,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
Me3
T,T,T3
HL
Data
0
MC.
T,T,T3
Be
Data
Me.Me.
TiTi
Me,
T ,T,T3
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
Me3
T,T,T3
HL
Data
0
Me.
T,T,T3
Be
Data
Me,
T,T,T3
lstopcode
Address
1st
opcode
0
0
Me,
T,T,T3
SP
Data
0
0
Me.
T,T,T.
SP+l
Data
0
0
Me,
T,T,T.
1st opcode
Address
1st
opcode
0
0
0
0
0
0
0
0
Z
0
0
0
0
1
0
0
0
0
(continued)
•
772
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Instruction
POP IX
POPIY
PUSH zz
PUSH IX
PUSH IY
RET
Machine
Cycle
States
Address
Data
RD
2nd opcode
Address
2nd
opcode
0
0
T,T,T,
SP
Data
0
0
MC.
T ,T ,T,
SP+l
Data
0
0
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
MC,MC,
TiTi
MC.
T,T,T,
SP-l
zzH
0
MC.
T,T,T,
SP-2
zzL
0
MC,
T ,T ,T,
1st opcode
Address
1st
opcode
0
MC,
T,T,T,
2nd opcode
Address
2nd
opcode
0
MC,MC.
TiTi
MC.
T ,T ,T,
SP-l
IXH
IYH
0
0
MC.
T ,T ,T,
SP-2
IXL
IYL
0
0
MC,
T ,T ,T,
1st opcode
Address
1st
opcode
0
0
0
MC,
T ,T ,T,
MC,
WR
ME
IDE
LlR
HALT ST
0
0
0
0
0
0
0
0
Z
0
0
Z
0
0
MC,
T,T,T,
SP
Data
0
MC,
T IT ~T 3
SP+l
Data
0
0
RET f
(If condition
is false)
MC,
T ,T ,T,
1st opcode
Address
1st
opcode
0
0
0
0
MC,MC,
TiTi
RET f
Uf condition
IS true)
MC,
T,T,T,
0
0
0
0
Z
1st opcode
Address
1st
opcode
Z
MC,
Ti
MC,
T,T,T,
SP
Data
0
0
MC.
T ,T ,T,
SP+l
Data
0
0
(continued)
$
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
773
HD641180X, HD643180X, HD647180X
Instruction
Machine
Cycle
States
Address
Data
RD
RETI
MC,
1st opcode
0
Address
1st
opcode
2nd opcode
Address
2nd
0
opcode
1
Z
1 ,
MC,
T1T2T3
T1T2T3
MC3MC,
TITITI
MC,
T,T,T3
MC,
TI
MCa
T1T2T3
2nd opcode
Address
opcode
MCg
T,T,T3
SP
MC"
T ,T ,T 3
MC,
MC,
WR
ME
0
IOE
LIR
HALT ST
0,
0
1
0
0,
1
1st
1st opcode
Address
0
0
0,
opcode
0
Z
1 ,
1
RLCA
0
0
0,
Data
0
0
1,
SP+ 1
Data
0
0
1,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
0
T ,T,T3
1 st opcode
Address
1st
0
0
0
0
opcode
0
0
0
0
0
0
0
0
0
0
0
RLA
RRCA
RRA
RLC 9
RL 9
RRC 9
MC,
T1T2T3
RR 9
SLA 9
SRA 9
MC3
TI
MC,
T,T,T3
2nd
2nd opcode
2nd
Address
opcode
1
Z
SRL 9
RLC (HL)
RL (HL)
RRC (HL)
MC,
T,T,T3
RR (HL)
SLA (HL)
SRA (HL)
MC3
T,T,T3
SRL (HL)
MC4
TI
MC,
T 1T 2T 3
1st opcode
1st
Address
opcode
2nd opcode
2nd
Address
opcode
HL
Data
Z
HL
Data
Note 5 The upper and lower data show the state of L1R when LIRE
0
0
= 1 and LIRE = 0 respectively
~HITACHI
774
0
Hitachi Amenca, Ltd • Hitachi Plaza. 2000 Sierra Pomt Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
(cont,nued)
HD641180X, HD643180X, HD647180X
Machine
Cycle
Stat..
Instruction
RLC (IX + d)
RLC (IV + d)
RL(lX+d)
RL (IV + d)
RRC (IX + d)
RRC (IV + d)
RR(lX+d)
RR(lY+d)
SLA (IX + d)
SLA (IV + d)
SRA (IX + d)
SRA (IV + d)
SRL (IX + d)
SRL (IV + d)
RLD
RRD
WR
ME
WE
Address
Date
RD
MC,
T,T,T,
1st opcode
Address
1st
opcode
0
0
LlR
0
MC,
T,T,T,
2nd opcode
Address
2nd
opcode
0
0
0
MC,
T,T ,T,
1st operand
Address
d
0
0
MC,
T,T,T,
3rd opcode
Address
3rd
opcode
0
0
Me,
T,T,T,
lX+d
lV+d
Data
0
0
HALT ST
0
0
Z
MC.
Ti
MC,
T,T,T,
IX+d
IY+d
Data
MC,
T,T ,T,
1st opcode
Address
1st
opcode
0
0
0
MC,
T,T ,T,
2nd opcode
Address
2nd
opcode
0
0
0
MC,
T,T ,T,
HL
Data
0
0
Me,-
TiTiTiT,
0
0
0
Z
MC,
0
0
MC.
T,T ,T,
HL
Data
MC,
T,T,T,
1st opcode
Address
1st
opcode
MC,MC,
TiTi
MC,
T,T,T,
SP-l
PCH
0
0
MC,
T,T,T,
SP-2
PCL
0
0
SCF
MC,
T,T ,T,
1st opcode
Address
1st
opcode
0
SET b.g
RES b.g
MC,
T,T ,T,
1st opcode
Address
1st
opcode
MC,
T,T,T,
2nd opcode
Address
2nd
opcode
MC,
Ti
MC,
T,T,T,
1st opcode
Address
MC,
T,T ,T,
MC,
T,T,T,
MC,
Ti
MC,
T,T,T,
RST
V
SET b. (HU
RES b. (HL)
0
0
0
0
0
0
0
0
0
0
0
0
0
1st
opcode
0
0
0
2nd opcode
Address
2nd
opcode
0
0
0
HL
Data
0
0
0
Z
Z
0
Z
HL
Data
0
0
(continued)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
775
HD641180X, HD643180X, HD647180X
Instruction
SET
SET
RES
RES
b, (lX+d)
b, (lY+d)
b, (lX+d)
b, (lY+d)
SLP"
TSTIO m""
Machine
Cycle
States
Address
Data
RD
Me,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T2T3
2nd opcode
Address
2nd
opcode
0
0
0
Me3
T1T2T3
1st operand
Address
d
0
0
Me,
T,T2T3
3rd opcode
Address
3rd
opcode
0
0
Me,
T,T 2 T3
IX+d
IY+d
Data
0
0
IX+d
IY+d
Data
1st opcode
1st
opcode
0
0
0
Address
2nd opcode
Address
2nd
opcode
0
0
0
Me,
TI
Me,
T,T 2 T3
Me,
T,T,T3
WR
ME
10E
LIR
z
0
0
T,T:.>T3
FFFFFH
Z
Me,
T,T2T3
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T,T3
2nd opcode
opcode
2nd
0
0
0
1st operand
m
0
0
Data
0
Me3
T,T,T3
0
0
Me,
Address
HALT ST
0
0
0
Address
Me,
T1T2T3
e to Ao-A,
0
OOH to As-A"
TST g""
TSTm""
TST (HU""
Me,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
Me,
T1T2T3
2nd opcode
Address
2nd
opcode
0
0
0
Me3
TI
Me,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T,T3
2nd opcode
Address
2nd
opcode
0
0
0
Me3
T,T,T3
1st operand
Address
m
0
0
Me,
T,T,T3
1st opcode
Address
1st
opcode
0
0
0
Me,
T,T,T3
2nd opcode
2nd
opcode
0
0
0
Address
HL
Data
0
0
Me3
TI
Me,
T,T,T,
0
Z
0
0
z
(continued)
@HITACHI
776
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
INTERRUPT
Instruction
Machine
Cycle
States
NMI
Me,
T,T.T.
Me.Me.
TiTi
MC.
T,T.T.
SP-l
PCH
0
0
MC.
T,T.T.
SP-2
PCl
0
0
Me,
T,T.Tw
TwT•
Next opcode
Address (PC)
1st
opcode
Me.-
TiTi
INTo Mode 0
(RST Inserted)
Address
Data
iii)
Next opcode
Address (PC)
Z
0
WR
ME
iOE
0
UR
HALT ST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Z
Z
MC.
Me.
T,T.T.
SP-I
PCH
0
0
MC.
T,T.T.
SP-2
PCl
0
0
INTo Mode 0
(CALL
Me,
T,T.Tw
TwT•
Next opcode
Address (PC)
1st
opcode
Inserted)
MC.
T,T.T.
PC
n
0
0
MC.
T,T.T.
PC+I
m
0
0
MC.
Ti
MC.
T,T.T.
SP-l
PC+2(H)
0
0
MC.
T,T.T.
SP-2
PC+2OJ
0
0
MC,
T,T.Tw
TwT•
Next opcode
Address (PC)
Z
MC.
T,T.T.
SP-I
PCH
0
0
MC.
T,T.T.
SP-2
PCl
0
0
MC,
T,T.Tw
TwT3
Next opcode
Address (PC)
Vector
PCH
INTo Mode I
INTo Mode 2
INT,
INT.
Internal
Interrupts
Z
Me.
Ti
Me.
T,T.T.
SP-I
Me.
T,T.T.
SP-2
PCl
MC.
T,T.T.
I, Vector
Oats
0
0
Me.
T,T.T.
~
Data
0
0
MC,
T,T.Tw
TwT•
Next opcode
Address (PC)
Z
Z
Vec1Or+ I
I
0
0
0
0
0
Z
MC.
T.
MC.
T,T.T.
SP-l
PCH
0
0
MC.
T,T.T.
SP-2
PCl
0
0
MC.
T,T.T.
I, Vector
Dets
0
0
Me.
T,T.T.
~
Data
0
0
Vec1Or+ 1
•
HITACHI
Hitachi America. Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane. CA 940Q5.1819 • (415) 589-8300
777
~
~
~
co
~
.a
C
en
~
!!L
~
C
~
~
~
~
~
~
Normal Operation
(CPU mode)
(I/O Stop mode)
.a
§i
Request
Refresh Cycle
Interrupt
Acknowledge
Cycle
i'5'
WAIT
Accepted
Accepted
Not accepted
Accepted
Accepted
Not accepted
Not accepted
Not accepted
Refresh cycle
begIns at
the end of MC
Not accepted
Not accepted
Refresh cycle
begIns at
the end of
MC
Refresh cycle
begIns at
the end of
MC
Not accepted
Not accepted
Not accepted
:;J;:
Refresh Request
(Request of
Refresh by the on-chIp
Refresh Controller)
S
~
DREQo
DREQ 1
DMA cycle
begIns at the
end of MC
DMA cycle
begIns at the
end of MC
Accepted
If refresh
cycle precedes
DMA cycle
begIns at the
end of one
MC
Accepted
DMA cycle
beginS at the
end of MC
Accepted
Refer to
Secllon 10
"DMA
Controller"
for details
Accepted
" After bus
frelease
cycle, DMA
cycle begIns
at the end of
oneMC
Not accepted
Not accepted
Bus IS released
at the end of
MC
Bus is released
at the end of
MC
ContInue bus
release
mode.
Accepted
Not accepted
Not accepted
Not accepted
Not accepted
Accepted
Return from
sleep mode
to normal
operation
Accepted
Return from
system stop
mode to normal
operation
Not accepted
Not accepted
Not accepted
Not accepted
Accepted
Return from
sleep mode
to normal
operation
Not accepted
~~~:~:Pted
~:;P~~~le
Not accepted
:<.
!"
Et
3!
~
Wait State
'::
~
<=>
<=>
W- J$.
=l
BUSREQ
'II;V
~ 1:
o §:
:::!
"
~
~ .. "
':<
;
Interrupt
INT 0, INT 1,
INT 2
:I
~.
Internal
.:c
Interrupt
§
va
C")
~
...
~
00
to
NMI
Bus IS released
at the end of
MC
Not accepted
Accepted after
executIng the
current
Accepted after
executIng the
current
Instruction.
Instruction
Accepted after
executing the
current
instruction
Accepted after
executing the
current
instruCtion
~::~:~ ~~:er
~.'':;~:~~ ~~:er
current
instruction.
current
instruction
~
g:
g
acknowledge
stops
cycle precedes
NMI is accepted
after executing
the next In-
~
~
Not accepted
struction
Notes '. not acceptable when DMA Request is In level sense
MC: MachIne Cycle
DMA Cycle
Bus Release
Mode
Sleep mode
System Stop
Mode
g:
»
~
•
0
~
"a
0)
,j:>.
~
~
n
'3!.
5
~
03:
'::r
:><:
0
~
.
::G
t:1
~
.....:J
CQ
......
i5=
Q,
~
~~~e~t~~~~
m
!a
:5'
system stop
mode to normal
operation.
~
w
......
~
~
~~~ue~t~~om
.....
me
"
sleep mode
to normal
operation
0
......
t:1
Z
~
~
...
.:><:
C)
!!
t:1
-
III
'3!.
Accepted
~
-
~:5'
Not accepted
m
::G
00
0
:><:
HD641180X, HD643180X, HD647180X
Request Priority
The HD643180X/HD647180X has the following three types of requests.
Type 1: To be accepted in specified state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. WAIT
Type 2: To be accepted in each machine cycle ..................... Refresh Req.
DMA Req.
Bus Req.
Type 3: To be accepted in each instruction ....................... Interrupt Req.
Type 1, type 2, and type 3 request priority is as follows:
Highest priority Type 1
>
Type 2
>
Type 3 Lowest priority
Type 2 request priority is as follows:
Highest priority Bus Req.
>
Refresh Req.
>
DMA Req. Lowest priority
Note: If Bus Req. and Refresh Req. occurs simultaneously, Bus Req. is accepted.
Refer to "Section 8, Interrupts" for type 3 request priority.
Type 4: To be accepted in last machine cycle
Highest priority Bus Req. from Bus masters> Interrupt Req.
•
HITACHI
Hitachi America, Ltd .• Hitachi Piau' 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819' (415) 569·8300
779
HD641180X, HD643180X, HD647180X
Operation Mode Transition
Figure 19. Operation Mode Transitions
~HITACHI
780
Hitachi America, Ltd • Hitachi Plaza. 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Notes:
1
2.
3.
Normal. CPU executes instructions normally in normal mode.
DMA request: DMA IS requested in the following cases.
(1) DREQo, DREQ, = 0 (memory to/from (memory-mapped) 110 DMA transfer)
(2) DEO = 1 (memory to/from memory DMA transfer)
DMA end: DMA ends in the following cases.
(1) DREQo, DREQ, = 1 (memory to/from (memory-mapped) 110 DMA transfer)
(2) BCRO, BCR 1 = OOOOH (all DMA transfers)
(3) NMI = 0 (all DMA transfers)
I
I
The following operation mode transitions are also possible
Halt
•
110 Stop ..._ __
(DMA
Refresh
Bus Release
DMA
( Refresh
Bus Release
Sleep
Bus Release
System Stop
Bus Release
@HITACHI
Hitachi America, Ltd • Hitachi Plaza' 2000 Sierra POint Pkwy. Brisbane, CA 94005-1819 • (415) 589-8300
781
HD641180X, HD643180X, HD647180X
Status Signals
Table 26. shows pin outputs in each operating mode.
Table 26 Pin Outputs
Mode
CPU
operation
LlR
ME
IOE
RD
Opcode Fetch
(1 st opcode)
0
0
0
Opcode Fetch
(except 1st
opcode)
0
0
0
Memory Read
0
1
0
Memory Write
0
1
1
1/0 Read
0
0
110 Write
0
WR
REF HALT BU5ACK
5T
0
0
0
Internal
Operation
Refresh
Interrupt
Acknowledge Cycle
(1st
machine
cycle)
NMI
0
INTo
0
0
1
0
0
0
0
INT1, INT2 &
Internal Interrupts
Bus Release
Z
Halt
0
Z
0
Z
Z
0
Sleep
Internal
DMA
A
In
A
In
A
In
A
Out
A
In
A
Out
A
In
A
In
0
A
In
0
A
In
0
A
In
Z
In
0
A
In
0
A
IN
Out
0
0
Address Data
Bus
Bus
In
0
Memory Read
0
Memory Write
0
0
0
1/0 Read
0
1/0 Write
0
Reset
0
0
0
A
0
A
In
0
A
Out
Z
In
Note 1 : High
0: Low
A : Programmable
Z : High Impedaoce
In : Input
Out: Output
* : Invalid
$
782
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
• INTERNAL 1/0 REGISTERS
By programming lOA 7 in the 110 control register, internal 110 register addresses are
relocatable within ranges from OOOOH to OOFFH in the 110 address space.
Register
1
Mnemonic
ASCI Control Register A Channel 0
(CNTLAO)
Address
o
Remarks
0
bit
Dunng reset
RIW
MPE
RE
TE
RTSO
MPBRI
EFR MOD2 MOD1 MODO
0
0
0
1
Invalid
0
0
0
RIW
RIW
RIW
R/W
R/W
R/W
RIW
RIW
II '---[
Mode selectlo;
Multi Processor Bit Receivel
Error Flag Reset
Request To Send
Transmn Enable
' - Receive Enable
' - MU~I Processor Enable
ASCI Control Register A Channel 1
(CNTLA1)
0
1
bit
Dunng reset
RIW
MPE
RE
TE
CKA1D
MPBRI
MOD2 MODl MODO
EFR
0
0
0
1
Invalid
0
0
0
RIW
RIW
RIW
R/W
R/W
RIW
RIW
RIW
L
L..
MOD2. 1.0
000
001
01 0
1 1
100
1
1
1 1 0
1 1 1
o
o
IAscl Control Register 8 Channel 0
(CNTLBO)
o
2
Start
Start
Start
Start
Start
Start
Start
Start
II
Mode SelecMn
Multi Processor Bit Recelvel
Error Flag Reset
~ CKA 1 Disable
' -Transmrt Enable
'- Receive Enable
Multi Processor Enable
+
+
+
+
+
+
+
+
7
7
7
7
8
8
8
8
bit
brt
bit
bit
brt
bit
bit
bit
bit
MPBT
DUring reset
Invalid
0
RIW
RIW
RIW
MP
Data
Data
Data
Data
Data
Data
Data
Data
+
+
+
+
+
+
+
+
C'fS1
PS
RIW
1 Stop
2 Stop
Panty
Panty
1 Stop
2 Stop
Panty
Panty
+
+
1 Stop
2 Stop
+
+
1 Stop
2 Stop
PEa
DR
0
0
R/W
R/W
SS2
SSO
1
1
1
R/W
R/W
RIW
L
I
SS1
LClock Source and
Speed Select
DIVide RatiO
Even or Odd
I... Clear To Send/Prescale
l..- Multi Processor
Mulb Processor Bit Transmit
~Panty
• CTS Depends on the condition of CTS Pin
PS Cleared to 0
(continued)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
783
HD641180X, HD643180X, HD647180X
Register
I
Mnemonic
ASCI Control Register B Channel 1
(CNTLB1)
Rema",s
Address
o
3
MPBT
bit
During reset invalid
RIW
RIW
MP
cr§'1
PEO
DR
SS2
SSI
0
0
0
0
1
1
1
RIW
RIW
RIW
RIW
RIW
RIW
RIW
PS
L
SSO
Clock Source and
Speed Select
L- Divide Ratio
'-Parity Even or Odd
'-- Clear To SendlPrescale
'-- Multi Processor
-Multi Processor Bit Transmit
General
divide ratio
SS2.1.0
IAscl Status Register Channel 0
(STATO)
o
4
=0
= 10)
O(X 16} DR = 1 (x64) DR PS
(divide ratio
DR -
t/>+ 640
+ 1260
+ 2560
+ 5120
+10240
+20460
+40960
000
001
010
011
100
101
110
160
t/>+
+
320
+
640
+ 1260
+ 2560
+ 5120
+ 10240
11 1
External clock (frequency
bit
RDRF
OVRN
PE
FE
RIE
During reset
0
0
0
0
0
R
R
R
R
RIW
RIW
<
=1
= 30)
O(X 16} DR = lIx64}
PS
(divide ratio
t/>+ 480
+
960
+ 1920
+ 3840
+ 7660
+ 15360
+30720
d>+
1920
+
3B4O
+
7680
+ 15360
+ 30720
+ 61440
+ 122880
t/> +4O)
15m) TDRE
. ..
R
R
TIE
0
RIW
I
• r>a>o :
ASCI Status Register Channel 1
(STAn)
o
5
Transmit
Interrupt
Enable
Transmit Data
Register Empty
'- Data CInier Detect
L-- Receive Interrupt Enable
- Framing Error
I-Parity Error
•• CTS. Pin I TORE
'- Over Run Error
l
1
' - Receive Data Register FuR
H
0
Depends on the condition of
Pin.
bit
During reset
RIW
I
r>a>o
RDRF OVRN
PE
FE
RIE
CTSIE TORE
TIE
0
0
0
0
0
0
1
0
R
R
R
R
RIW
RIW
R
RIW
J .
Transmit
Interrupt
Enable
Transmit Data
-.!!..egister Empty
'-- CTS 1 Enable
L Receive Interrupt Enable
L- Framing Error
L-Parity Error
'- Over Run Error
Receive Data Register Ful
(continued)
784
• HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD641180X, HD643180X, HD647180X
Register
I
Mnemonic
ASCI Transmit Data Register Channel
o
Address
Remarks
0 6
(TDRO)
ASCI Transmit Data Register Channel
0 7
1
(TOR1)
ASCI ReceIVe Data Register Channel
o
0 8
(TSRO)
ASCI Receive Data Register Channel
0 9
1
(TSR1)
o
CSI/O Control Register
A
(CNTR)
brt
EF
EIE
RE
TE
-
SS2
SS1
Dunng reset
0
0
0
0
1
1
1
1
RIW
R
RIW
RIW
RIW
RIW
RIW
RIW
l
SSO
LSpeed Select
Transmrt Enable
Receive Enable
End Interrupt Enable
End Flag
SS2,1,0
Baud Rate
q,+
000
001
010
011
o
B
Timer Data RegISter Channel OL
(TMDROL)
o
C
Timer Data Register Channel OH
(TMDROH)
o
0
Timer Reload Register Channel OL
(RLDROLl
o
E
Timer Reload Register Channel OH
(RLDROH)
0
F
Timer Control Register
1 0
CSVO TransmrtlRecelve Data
Register
SS2,1,0
20
100
101
110
111
+
40
80
+160
Baud Rate
q,+
320
+ 640
+ 1280
Extemal
(frequency < + 20)
(TRDR)
(TCR)
brt
TIF1
TIFO
TIE 1
TIEO
TOC1
TaCO
TDE1
DUring reset
0
0
0
0
0
0
0
0
RIW
R
R
RIW
RIW
RIW
RIW
RIW
RIW
l.
TOEO
L
Timer Down
Count Enable 1,0
Timer Output Control 1 ,0
Timer Interrupt Enable 1,0
Timer Interrupt Flag 1,0
TOC1,0
TOUT1
00
01
10
11
1
Toggle
0
1
(continued)
@>HITACHI
Hitachi America, Ltd, • Hitachi Plaza' 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819. (415) 589-8300
785
HD641180X, HD643180X, HD647180X
Register
I
Mnemonic
Address
Timer Data Register Channel 1L
(TMDR1U
1 4
Timer Data Registar Channel 1H
(TMDR1H)
1 5
Timer Reload Register Channel II
(RLDR1U
1 6
Timer Reload Register Channel 1H
(RLDR1H)
1 7
Free Running Countar
1 S
Remarks
Read only
(FRC)
DMA Source Address Register
Channel OL
(SAROU
2 0
DMA Source Address Registar
Channel OH
(SAROH)
2 1
DMA Source Address Registar
Channel OB
(SAROB)
2 2
[oMA Destination Address Register
Channel OL
(DAROU
2 3
DMA Destination Address Register
ChannalOH
(DAROH)
2 4
iDMA Destination Address Registar
ChannalOB
(DAROB)
2 5
DMA Byte Count Register Channal
OL
(BCROU
2 6
DMA Byte Count Registar Channel
iOH
(BCROH)
2 7
DMA Memory Address Register
ChannellL
(MARlU
2 8
DMA Memory Address Registar
Channel lH
(MARl H)
2 9
DMA Memory Address Registar
ChannellB
(MARl B)
2 A
DMA
lL
va Address Registar Channel
DMA
lH
va Address Registar Channal
Sits 0-3 are used for SAROB.
A,9. A,s. AH. A,.
X
X
0
0
1
X
X
0
X
X
1
0
1
1
X
X
DMA Transfer ReQuest
DREQo (external)
RDRO (ASCIO)
RDRI (ASCIl)
Not Used
Bits 0-3 are used for DAROB.
A'9. Ala. AH, A,.
X
X
0
0
X
X
1
0
X
X
1
0
X
X
1
1
DMA Trensfer ReQuest
i5REOo (external)
TDRO (ASCIO)
TORI (ASCI1)
Not Used
Bits 0-3 are used for MAR 1B.
2 B
(IARlU
2 C
(IAR1H)
( continued)
786
• HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD641180X, HD643180X, HD647180X
Register
I
Mnemonic
Address
DMA Byte Count Register Channel
lL
(BCR1U
2 E
DMA Byte Count Register Channel
lH
(BCR1H)
2 F
DMA Stetus Register
3 0
Remarks
b~
DEI
DEO
DIEI
OlEO
-
Dunng reset
0
0
1
1
0
0
1
RIW
RIW
RIW
W
W
RIW
RIW
(DSTAT)
DWEI DWEO
DME
0
R
lnMA
Master
Enable
.qMA Interrupt Enable 1,0
-DMA Enable B~ Write Enable 1,0
'--DMA Enable ch 1,0
3 1
DMA Mode Register
(DMODE)
bit
-
-
DMI
DMO
SMI
Dunng reset
1
1
0
0
0
0
0
RIW
RIW
RIW
RIW
RIW
RIW
-
SMO MMOD
-
1
LMemorv
Mode
Select
Ch 0 Source
Mode 1,0
' - Ch 0 Destlnabon
Mode 1,0
DM1, 0 Destination
00
01
10
1 1
MMOD
0
1
M
M
M
VO
Address
DARO+ 1
DARO-l
DARO fixed
DARO fixed
SM1,0 Source
M
00
o1 M
M
1 0
VO
1 1
Address
SARO+ 1
SARO-l
SARO f,xed
SARO fixed
Mode
Cycle Steal Mode
Burst Mode
(continued)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819· (415) 589·8300
787
HD641180X, HD643180X, HD647180X
Register
I
Mnemonic
DMAlWait Cootrol Resiter
Address
Rema.i
"., ~
)I tmer (TM1 )
f-i
rr-
TI
,-
P1 0 (TXO)
P11 (RXO)
P1;, (SCKO)
P13 (TX1)
P1,(RX1)
P1s (SCK1)
P16 (TOUT1 )
P 7 (TOUT2 )
rr(2 channels)
~
l!!
"
Cl
Port 1
:>
.0
~
~
..
r~
~
2
l;
.£
n
po,
po,
Port 3
r---'
r-~
POo
P0 2
P0 3
j;
r-
SCI
Port 0
J
~AlD converte
~
Q
--:l
PO s
5
t+
"'::I
~
P0 6
PO,
(B·botx
4·channel)
Port 4
AVec
AVss
P4 0 (ANo)
P4, (AN,)
P4 2 (AN 2)
P43 ( AN 3)
Figure 2 HD648180W Block Diagram
~HITACHI
796
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
• Pin Descriptions
• Pin Arrangement
Figure 3 shows the pin arrangement of the HD648180W in the FP-80A package. Figure 4 shows
the pin arrangement in the CP-84 package.
,
M~~~~~~~~~~G~Q~~«a~~
~
~
~
HALT
38
P11TX 1
PtVRX 1
P1&' SCK1
~
~
P1sfTOUT 1
~
38
~
~
REF/P2 S
32
P1/TOUT1
P33/0RE01 fflN 1
P32/TEN01 /TOUT4
P31/0REOo
P30/TENOo/TOUT 3
Ao
~
Vss
A1
A2
30
29
28
P0 7
A.
As
As
V
PO.
~
P03
P02
P0 1
UR
~
~
M
A3
~
POs
P05
A7
M
As
~
POo
Ag
~
07
21
Os
7
A 10
80 pin
12345678
/'
1 pin
~ ~ ~ J~ ~ ~ ;
J ~1@1131~
'68 r5 8 8 b tS
~~3:>
O~NM
~~~~
- -'"
iiliil
....
NN
a. a.
Figure 3 Pin Arrangement (FP-80A)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
797
HD648180W
~
Iw
~
I~~~~~
(/ll~~
~002
~~
~~~~g~~~~~o~&f~~~~~~~
~>w
><1:~~~~Z
~~z~~~
Mnnnm~~~~~M~U~M~~~Y~~
~
ST
HALT
IOE
ME
lIR
WR
RO
REF/P2 S
Ao
NC
A1
A2
A3
A4
As
As
A7
As
Ag
AlO
75
76
53
52
51
50
77
78
79
80
81
82
83
84
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
0
4
5
8
9
10
11
p1:/rx 1
PV RX 1
PySCK1
P\/TOUT 1
P 7ITOUT2
P3:J Il5REOi!TIN 1
P~ITEN01ITOUT 4
P31/QRffio
P30ITE NOolTOUT 3
VSS
NC
P~
POe
POS
P04
PO:J
PO:1
POl
POo
07
Os
12 13 14 15 16 17 18 19 20 21 22232425 26 27 28 29 30 31 32
Figure 4 Pin Arrangement (CP-S4)
~HITACHI
798
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819, (415) 589·8300
HD648180W
• Pin Functions
Table 2 Pin Functions
Pin Number
FP-80A PC-84
1/0
Name and Pin Function
Power supply Vee
GND
14,56 26, 70
Input
Power Supply: Connect all Vee pins to
system power supply (+5 V).
Vss
10,31, 21,44
59
73
57
71
Input
Ground: Connect all Vss pins to system
power supply (0 V).
Input
Connect to crystal oscillator with twice
system clock (<1» frequency.
Type
Signal
XTAL
XTAL
clock
When inputting external clock at EXTAL,
leave XTAL open.
58
EXTAL
Input
72
Connect to crystal oscillator or external
clock. External clock frequency should
be 2 times system clock.
CL,
JlJlJL External clock
EXTAL
EXTAL
input
XTAL
o
XTAL
Open
~
CL~
Oscillator circuit examples
Reset
RESET
Address bus
Ao to A'9
61
75
Output
System Clock: Supplies system clock to
peripheral devices.
60
74
Input
Reset: Chip is reset when this pin is
dropped low.
1 to 9,
1 to
Output
Address Bus: For memory access.
(Tri-state) These lines go to high impedance only in
the following cases.
70 to 80 20, 84
a. During reset
b. When bus control is granted to
another device (when BUSACK
drops low because of low input at
BUSREQ).
$HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
799
HD648180W
Table 2 Pin Functions (cont)
Pin Number
Type
Signal
FP·80A PC-84
I/O
Name and Pin Function
Data bus
Do to D7
15 to
22
27 to
34
Input/
Output
Data Bus: 8-bit, bidirectional data bus
Memory 110
interface
signal
RD
68
82
Output
Read: Indicates chip is in read cycle.
(Tri-state) At this time, data bus is in input mode.
WR
67
81
Output
Write: Indicates chip is in write cycle.
(Tri-state) At this time, data bus is in output mode.
ME
65
79
Output
Memory Enable: Indicates memory
(Tri-state) read/write is being performed. Goes low
in the following cases:
a.
Instruction fetch and operand read
b. Data read/write by memory reference
instruction
c.
Memory access during DMA cycle
d. Refresh cycle
10E
64
Output
110 Enable: Indicates I/O read/write is
(Tri-state) being performed. Goes low in the
following cases:
78
a. Data read/write by 110 instruction
execution
b. I/O access during DMA cycle
c.
13
25
Input
Wait: Used to extend memory and 110
read/write cycles. If low at the falling
clock edge in a T 2 or Tw state, a Tw
state is inserted next.
BUSREQ 11
23
Input
Bus Request: Used by another device
to issue a bus request. When this pin
goes low, CPU terminates instruction
execution and sets address bus, data
bus, and some memory interface signals
(RD, WR, ME, 10E) to high impedance .
WAIT
System
control
signals
•
800
INTo acknowledge cycle
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Table 2 Pin Functions (cont)
Pin Number
Type
Signal
System
control
signals
BUSACK 12
HALT
ST
FP-80A PC-84
1/0
Name and Pin Function
24
Output
Bus Acknowledge: Indicates receipt of
BUSREO signal by CPU and release of
bus. Notifies device that output
BUSREO signal that bus is under its
control.
63
77
Output
HALT: Goes low when CPU executes
HALT or SLP instruction to indicate that
CPU is in halt or sleep mode. Used
together with ST and LlR signals
(described below) to indicate operational
status of internal DMA and CPU mode.
66
80
Output
Load Instruction Register: Indicates
ongoing cycle is op code fetch cycle.
62
76
Output
Status: Indicates operational status. Do
not connect pull-down resistance to this
pin.
ST HALT
LlR Operation Mode
0
0
CPU operation
(1 st op-code fetch
cycle)
0
CPU operation
(2nd, 3rd op-code
fetch cycle)
CPU operation
(machine cycles
other than opcode fetch cycles)
0
Undefined
0
0
0
DMA
0
Halt mode
Sleep mode
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
801
HD648180W
Table 2 Pin Functions (cont)
Pin Number
Type
Signal
FP-SOA PC-S4
I/O
Name and Pin Function
System
control
signals
REF
69
83
Output
Refresh: Low level indicates CPU is in
DRAM refresh cycle. Refresh address is
output on lower 8 bits of address bus
(Ao through A7). Refresh cycle interval
can be programmed to 10, 20, 40, or 80
states.
Interrupt
signals
NMI
44
57
Input
Non-Maskable Interrupt: Non-maskable
interrupt request pin.
INTo
45
58
Input
Interrupt 0: Maskable interrupt level
request pin. Level 0 has 3 modes.
°
Mode
Meaning
°
Execute instruction on data
bus
Execute instructions starting
from address 0038H
2
INTl
48
61
Input
INT2
46
59
Input
33
46
Input
DMAsignals DREQo
Vectored
Interrupt 1, 2: Maskable interrupt Level 1
and 2 request pins. Vectored.
DMA Request for Channel 0: Asks
internal DMAC to perform transfer on
channel o. Enables internal DMAC to
synchronize with external I/O device.
Internal DMAC channel 0 supports the
following transfers.
a. Memory
H
Memory
b. Memory
H
I/O
Memory
H
Memory-mapped I/O
c.
~HITACHI
802
Hitachi America, ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Table 2 Pin Functions (cont)
Pin Number
Signal
Type
FP-80A PC-84
1/0
Name and Pin Function
DMAsignals TENDo
32
45
Output
Transfer End for Channel 0: Internal
DMAC channel 0 transfer end signal.
This signal goes low at write cycle of final
data transfer.
DREQ 1
35
48
Input
DMA Request for Channel 1: Asks
internal DMAC to perform transfer on
channel 1. Channel 1 supports
Memory +-+ 1/0 transfers only.
TEND1
34
47
Output
Transfer End for Channel 1: Internal
DMAC channel 1 transfer end signal.
This signal goes low at write cycle of final
data transfer.
TXo
43
56
Output
Transmit Data for SCI Channel 0: SCI
channel 0 transmit data pin.
RXo
42
55
Input
Receive Data for SCI Channel 0: SCI
channel 0 receive data pin.
SCKo
41
54
Input!
Output
Serial Clock for SCI Channel 0: SCI
channel 0 clock input/output pin.
TX 1
40
53
Output
Transmit Data for SCI Channel
channel 1 transmit data pin.
RX 1
39
52
Input
Receive Data for SCI Channel 1 : SCI
channel 1 receive data pin.
SCK 1
38
51
Input/
Output
Serial Clock for SCI Channel 1: SCI
channel 1 clock input/output pin.
Serial
communications
$
1: SCI
HITACHI
Hitachi America, ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
803
HD648180W
Thble 2 Pin Functions (cont)
Pin Number
Type
Signal
FP-SOA PC-S4
1/0
Name and Pin Function
Timers
TINl
35
48
Input
Timer Input for Channel 1: Input signal
pin for timer 1 input capture. Signal
transitions at this pin transfer freerunning counter value to input capture
register.
TOUT 1
37
50
Output
Timer Output for Channel 1: Timer 1
waveform output pin. When output
compare register and free-running
counter match, value of OLVL bit of timer
control/status register 1 is output from
this pin.
TOUT2
36
49
Output
Timer Output for Channel 2: Timer 2
waveform output pin. When timer 2 time
constant register and timer 2 up-counter
match, value selected by bit 2 and bit 3
of timer control/status register 2 is output
from this pin.
TOUT3
32
45
Output
Timer Output for Channel 3: Timer 3
waveform output pin. When timer 3 time
constant register and timer 3 up-counter
match, value selected by bit 2 and bit 3
of timer control/status register 2 is output
from this pin.
TOUT4
34
47
Output
Timer Output for Channel 4: Timer 4
waveform output pin. When timer 4 time
constant register and timer 4 up-counter
match, value selected by bit 2 and bit 3
of timer control/status register 4 is output
from this pin.
~HITACHI
804
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Table 2 Pin Functions (cont)
Pin Number
Type
Signal
FP-80A PC-84
I/O
Name and Pin Function
AID
converter
AVss
55
69
Input
Analog Ground: AID converter power
supply (ground)
AVec
50
63
Input
Analog Power Supply: AID converter
power supply (+5 V). Connect to system
power supply (Vee).
65 to
68
Input
Analog Input: AID converter input signal
pins
ANo to AN3 51 to
54
ADT
48
61
Input
AID Trigger: External trigger input pin to
start AID converter
Vpp
49
62
Output
Test pin. Do not connect.
Parallel 110 POo to P07 23 to
30
35 to
42
Input!
Output
Port 0: 8-bit parallel 110 port. Switched
between input and output by data
direction register 0 (DORO).
P1 o toP1 7 36 to
49 to
56
Input!
Output
Port 1: 8-bit parallel 110 port. Switched
between input and output by data
direction register 1 (DOR1).
17 to
P20 to P2s 6 to 9
11, 12, 20
23,24,
69
83
Inputl
Output
Port 2: 7-bit parallel 110 port. Switched
between input and output by data
direction register 2 (DOR2).
P26 is output only.
P30 to P37 32 to
35
45 to
48
45 to
48
58 to
61
Input!
Output
Port 3: 8-bit parallel 110 port. Switched
between input and output by data
direction register 3 (DOR3).
P40 to P43 51 to
54
65 to
68
Input
Port 4: 4-bit input-only port.
EEPROM
43
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
805
HD648180W
• Basic CPU Architecture
The HD648180W has an advanced, high-speed, eight-bit CPU. Its instruction set is
upward-compatible with the HD64180Z.
• Features
The HD648180W CPU has the following features.
CPU architecture based on the Z-80
Expanded instruction set with instructions for:
-
Input from on-chip I/O
Output to on-chip 1/0
Block transfer between memory and on-chip I/O
8-bit x 8-bit multiplication
AND operations on on-chip 110
AND operations on accumulator A
Transition to sleep mode
Eight addressing modes
-
Implied
Register direct
Register indirect
Indexed
Extended
Immediate
Relative
I/O
Maximum operating speed: 6.144 MHz
Special CPU operating modes
-
-
Low-power modes (standby modes)
Software standby mode
Hardware standby mode
Sleep mode
Halt mode
Bus-release mode
~HITACHI
806
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005· 1819. (415) 589·8300
HD648180W
• Address Space
The HD648180W CPU has a 64-kbyte logical address space and 64-kbyte 110 address space.
The 64-kbyte logical address space is mapped into a I-Mbyte physical address space by the memory
management unit (MMU). For details, see Memory Management Unit (MMU).
The 64-kbyte 110 address space is assigned to on-chip and off-chip 110. For details, see On-Chip 110
Address Space Map.
• Register Configuration
The CPU includes two general register sets (GR and GR '), and a single special-purpose register
set. Register sets GR and GR' each include an accumulator, a flag register, and six generalpurpose registers. The special-purpose register set consists of an interrupt vector register, an R
counter, two 16-bit index registers, a stack pointer, and a program counter.
Register set GR
Special-purpose registers
Accumulator Flag register
A
F
B register
C register
D register
E register
H register
L register
1
General-purpose
register set
Interrupt
vector
R counter
register
R
I
Index register IX
Index register IV
Stack pointer SP
Program counter PC
I
Register set GR'
Accumulator Flag register
F'
A'
B'register
C'register
D'register
E'register
H'register
L'register
1
General-purpose
register set
Figure 5 CPU Register Configuration
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
807
HD648180W
• Register Descriptions
The following table describes the function of each register. Unless otherwise specified, register
content is undefined following a reset.
Register Name
Symbol
Function
Accumulators
A, N
Accumulators are registers in which 8-bit arithmetic
operations, logical operations, and shifts are performed.
Accumulator N is used in place of accumulator A following
execution of the instruction EX AF, AF'.
Flag registers
F, F'
Flag registers store the status of operations. Flag register F'
is used in place of flag register F following execution of the
instruction EX AF, AF'.
General-purpose
registers
B,C
D,E
The registers in register set GR can be used as 8-bit
registers (B, C, D, E, H, L) or 16-bit registers (BC, DE, HL).
They can be used to execute operations or store
addresses.
H,L
B',C'
D', E'
H', L'
The registers in register set GR' supplement the GR
registers. The two register sets can be swapped using the
EXX instruction.
This 8-bit register stores the upper 8 bits of the 16-bit vector
produced by an interrupt. Vectors are used for INTo mode 2,
INT" INT2 , and internal interrupts (7 sources).
A reset initializes this register to OOH.
Interrupt vector
register
R counter
R
This 8-bit register counts the number of op-code fetch cycles
performed. The content of this counter is unrelated to the
refresh address, which is generated by another on-chip
counter that cannot be accessed by the user. A reset
initializes this register to OOH.
Index registers
IX, IY
These 16-bit registers are used for indexed addressing and
16-bit operations. In indexed addressing, the base address
is stored in the index registers. A signed 8-bit displacement
is added to the base address to generate the operand's
effective address. In 16-bit operations that involve the index
registers, a general-purpose register (except HL), the index
registers, or the stack pointer can be used for the other
operand.
Stack pointer
SP
This 16-bit register stores the top address of the stack area.
A reset initializes this register to OOH.
Program counter
PC
This 16-bit register stores the logical address of the next
instruction to be executed. This register is normally
incremented by 1 each time a 1-byte instruction code is
accessed, but execution of a jump instruction causes the
address of the jump destination to replace the current content
of the program counter. A reset initializes this register to
OOOOH .
•
808
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
HD648180W
Flag Register
The flag register (F) contains individual flags that are set and reset to represent the status of the
result of an 8-bit or 16-bit operation. This register is referenced by extended arithmetic
instructions and conditional jump instructions.
~Iag register
I
7
6
S
Z
5
4
H
3
2
PIV
N
o
c
Flag Name
Symbol
Function
Sign
S
Bit 7 is set when an operation produces a negative result
(MSB - 1) and reset by a positive result (MSB - 0).
Zero
Z
Bit 6 is set when an instruction execution produces a zero
result, and reset by any other result.
Half-carry
H
Bit 5 is set when an operation results in a carry or borrow from
the 4th bit. The half-carry flag is reset when neither a carry nor
borrow is generated. This flag is referenced for adjustment of
decimal operations (DAA instruction).
Parity/overflow
PN
Bit 2 can be used as either a parity or an overflow flag.
The parity flag indicates the parity of the data stored in the
accumulator following execution of a logical operation. An even
number of 1s in the accumulator value sets the parity flag, while
an odd number of 1s resets it.
The overflow flag is set when the result of a signed arithmetic
operation exceeds the range of + 127 through -128 for an 8-bit
operation, or the range of +32767 through -32768 for a 16-bit
operation. Results within these ranges reset the overflow flag.
Negate
N
Bit 1 is set by execution of a subtraction instruction (examples:
SUB, DEC, CP) and reset by an addition instruction (examples:
ADD, INC).
Carry
C
Bit 0 is set when an operation results in a carry or borrow from
the most significant bit. Any other result resets this flag. The
following lists the various types of carries and borrows.
• Carry produced by an addition result
• Borrow produced by a subtraction result
• Carry produced by a shift or rotate
.HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300
809
HD648180W
Addressing Modes
The CPU instruction set has eight addressing modes.
I.
Implied Addressing (IMP)
This addressing mode is based on data included within op codes. It is used by instructions
that manipulate bit positions specified by the accumulator (A), index registers (IX, IY), stack
pointer (SP), HI... general-purpose register, or op codes.
2.
Register Direct Addressing (REG)
In this addressing mode, 8-bit and 16-bit registers are specified by op code fields g, g', ww,
xx, yy, and zz. The following tables show the relationships between field codes and registers.
8-Bit Register Specification
g or g' Field
Specified Register
000
B
001
C
010
0
011
E
100
H
101
L
110
111
A
~HITACHI
810
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
16-blt Register Specification
ww Field
Specified Register
xx Field
Specified Register
00
00
01
Be
DE
01
Be
DE
10
HL
10
IX
11
SP
11
SP
yy Field
Specified Register
zz Field
Specified Register
00
00
01
Be
DE
01
Be
DE
10
IV
10
HL
11
SP
11
AF
3.
Register Indirect Addressing (REG!)
In this addressing mode, general-purpose registers are used as 16-bit address registers for
specification of operands in memory.
~
Be
DE
HL
--------~
~r-'
r-'
Operand
Memory
l...-
~ ~
.HITAOHI
Hitachi Amerlcll, LIlt. Hitachi Pi~a • 2000 Sierra Point Pkwy. , Brlllblll1e, CA 94006·1819 , (415) p8~·8300
a, 1
HD648180W
4.
Indexed Addressing (INDX)
In this addressing mode. effective addresses are generated by adding a displacement
(d: signed 8-bit value) to the index registers (IX. IY).
Op code 1
Sign extension
Op code 2
~r-'
~~
Displacement (d)
Operand
I
I
IX or IV
Memory
~c....
~~
5.
Extended Addressing (EX])
With this addressing mode, 2 bytes (m, n) following the op code are used as a 16-bit address
for direct specification of an operand in memory.
Op code
n
~~
~r-'
m
m
J
n
I
Operand
Memory
~'-'
~'--'
~HITACHI
81 2
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
6.
Immediate Addressing (IMMED)
With this addressing mode, 1 byte (m) or 2 bytes (m, n) following the op code are used as a
direct operand.
~
~} 8-bit operand
7.
~
~}
'6-h" operand
Relative Addressing (REL)
This addressing mode can be used with branching instructions only. A displacement (j:
signed 8-bit value) is added to the program counter (PC) to generate a branch address. In the
case of a conditional branch, the branch is taken only when a condition is satisfied.
Op code
Sign extension
Displacement U)
Program counter (PC)
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
813
HD648180W
8.
I/O Addressing
This addressing mode can be used with I/O instructions only. The specified address is an I/O
address (JOE = 0). One of the following addresses is output by this addressing mode.
• An address formed by the content of the operand, which is output to Ao through A7 , and
the content of accumulator A, which is output to As through A 15 .
• An address formed by the content of register C, which is output to Ao through A7, and the
content of register B, which is output to As through A 15 .
• An address formed by the content of the operand, which is output to Ao through A7 , and
OOH, which is output to As through A 15 • This is convenient for accessing on-chip I/O
registers.
• An address formed by the content of register C, which is output to Ao through A7, and
OOH, which is output to As through A 15 . This is convenient for accessing on-chip I/O
registers.
•
814
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Instruction Set Overview
The CPU instruction set for this chip can be broken down as follows.
Operation instructions
Load instructions
Program control instructions
I/O instructions
Special control instructions
These instructions consist of 1 to 4 bytes. Typical examples are shown below.
7
1-byte instruction
2-byte instruction
6
5
0
4
3
2
g'
9
7
6
0
0
5
0
4
3
2
LDg, g'
0
0
9
m
3-byte instruction
Immediate data
0
7
6
5
4
3
2
1
1
0
'1
1
1
0
1
0
1
I1
1
0
I
LDg, m
9
LD g, (IX + d)
Displacement
d
7654320
4-byte instruction
1
1
0
1
1
1
0
1
0
0
1
1
0
1
1
0
LD (IX + d), m
d
Displacement
m
Immediate data
See Instruction Set Lists for further details .
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
81 5
HD648180W
Conditional Jump and Conditional Call Instruction Precautions
The following illustrates operation when the conditional jump instruction JP f, mn is executed.
Note the difference in operation when the condition tests true and when it tests false.
Example
When the instruction JP NZ, 6000H is at address 5000H (MMU sets base register to OOH).
~
~r-'
5000H
JP NZ. (C2H)
5001H
OOH
5002H
60H
5003H
SLP (EDH)
76H
~w
~
~r-'
6000H
LD (32H)
6001H
00
r-'
w
r-'
70
-
~w
T1
T2
T3
~
T1
T2
T3
X
5001H
T1
T2
T3
X
5002H
T1
T2
X
6000H
T3
T1
T2
/3 = 2.048 MHz
when = 6.144 MHz
0
Number of inputs
Absolute precision
Unit
8
Resolution
Input hold time
(conversion time)
Max
Ta" 25°C, Vee
=5.0 V
IJ.s
4
Channel
2.0
LSB
Note: AVee must equal Vee.
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
819
HD648180W
AC Characteristics (Vee = S V ±to %, Vss = 0 V, T a = -20 to +7SoC unless
otherwise noted)
HD648180W-4
Test Conditions
Min
HD648180W-6
Typ Max Min Typ Max Unit
Item
Symbol
Clock cycle time
tc~c
Clock high pulse
duration
tcHW
110
65
ns
Clock low pulse
duration
tcLW
110
65
ns
Clock fall time
tcf
15
15
ns
Clock rise time
tcr
15
15
ns
External clock cycle
time
tECYC
External clock high
pulse duration
Figure 6
250
333
162
333
ns
125
81
ns
tExHW
50
32
ns
External clock low
pulse duration
tEXLW
50
32
ns
External clock rise time
tEXr*l
External clock fall time
tEXtl
Address delay time
tAD
Address setup time
(measured from ME
or IDE falling edge)
tAS
ME delay time 1
tMEDl
Figure 6,7,
85
60
ns
tRDDl
Figure 6
85
60
ns
Figure 8
85
65
ns
Figure 6
100
80*2 ns
RD
(when IOC = 1)
delay
(when IOC = 0)
time 1
LlR delay time 1
tLDl
Figure 18
Figure 18
Figure 6
25
25
ns
25
25
ns
110
90
ns
50
Address hold time
tAH
(measured from ME, IDE,
RD, or WR rising edge)
30
80
ns
35
ns
ME delay time 2
tMED2
Figure 6,7
85
60
ns
AD delay time 2
tRDD2
Figure 6
85
60
ns
LlR delay time 2
tLD2
100
80*2 ns
Notes: 1. If external clock pulse duration specifications (tExHW' tExLW) are not satisfied, adjust
tEXr and tEXt·
2. tLDl (tLD2) = 60 ns when bus timing test load capacitance C = 40 pF.
~HITACHI
820
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
AC Characteristics (Vee =5 V
otherwise noted) (cont)
±to %, V ss =0 V, T a =-20 to +75°C unless
Item
Symbol
Data read setup time
tORS
Data read hold time
tORH
ST delay time 1
tSTD1
ST delay time 2
tSTD2
WAIT setup time
tws
WAIT hold time
tWH
Write data floating
delay time
twoz
WR delay time 1
Test Conditions
Figure 6,7
HD648180W-4
HD648180W-6
Min Typ Max
Min Typ Max Unit
50
40
ns
0
0
ns
Figure 6
Figure 10
Figure 6
110
90
ns
110
90
ns
80
40
ns
70
40
ns
100
95
ns
tWR01
90
65
ns
Write data delay time
twoo
110
90
ns
Write data setup time
(measured from WR
falling edge)
twos
WR delay time 2
tWR02
WR pulse duration
tWRP
Write data hold time
(measured from WR
rising edge)
t WOH
IDE
(when IOC = 1)
delay
(when IOC = 0)
time 1
tlOO1
IOE delay time 2
IOE delay time 3
(measured from LlR
falling edge)
Figure 6
40
60
90
ns
80
ns
280
170
ns
60
40
ns
Figure 6
85
60
ns
Figure 8
85
65
ns
tlOO2
Figure 6
85
60
ns
tlOO3
Figure 7
•
540
340
ns
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
821
HD648180W
AC Characteristics (Vee = 5 V ±10%, Vss = 0 V, T. = -20 to +75°C unless
otherwise noted) (cont)
HD648180W-4
HD648180W-6
Symbol T8st Conditions Min Typ Max Min Typ Max Unit
Item
80
40
ns
INT hold time
tlNTH
(measured from ell falling edge)
70
40
ns
NMI pulse duration
120
120
ns
80
40
ns
70
40
ns
INT setup time
tIN~S
(measured from ell falling edge)
Figure 7
Figure 13
tNMIW
BUSREQ setup time
tBRS
(measured from ell falling edge)
Figure
7
BUSREQ hold time
tBRH
(measured from ell falling edge)
BUSACK delay time
1
tBAD1
100
95
ns
BUSACK delay time
2
tBAD2
100
95
ns
Bus floating delay time
tBZD
130
125 ns
ME pulse duration (high)
tMEWH
200
110
ns
ME pulse duration (low)
tMEWL
210
125
ns
Port data output
delay time
tpWD
Figure
13
Port data input
setup time
t pDs
Figure
13
180
150
ns
Port data input
hold time
tpDH
Figure
13
60
40
ns
Figure 7
REF delay time
1
tRFD1
REF delay time
2
tRFD2
HALT delay time
1
tHAD1
Figure 7
HALT delay time
2
tHAD2
Figure
12
tDRQS
Figure
10
DREQi setup time
DREQi hold time
1
1
tDRQH
110
90
ns
110
90
ns
110
90
ns
110
90
ns
110
90
ns
80
40
ns
70
40
ns
TENDi delay time
1
tTED1
85
70
ns
TENDi delay time
2
tTED2
85
70
ns
_HITACHI
822
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
HD648180W
AC Characteristics (Vee
otherwise noted) (cont)
=5 V ±10%, V ss =0 V, Ta =-20 to +75°C unless
Test Conditions
HD648180W-4
HD648180W-6
Min Typ Max
Min Typ Max
Item
Symbol
Timer output delay time
tTOD
Figure 11
SCI input clock cycle
(clocked synchronous
mode)
tscyc
Figure 17
SCI transmit data delay
time (clocked synchronous mode)
tTXD
SCI receive data setup
time (clocked synchronous mode)
tSRX
SCI receive data hold
time (clocked synchronous mode)
tHRX
SCI input clock pulse
duration
tpWSCXH
tpWSCXL
Figure 14
0.4"1-
Timer 1 input clock
pulse duration
tpWTH
tpWTL
Figure 15
8
8
tcyc
RESET setup time
tRES
Figure 15
120
120
ns
RESET hold time
tREH
80
80
300
40
40
200
Figure 17
300
-
Unit
ns
tcyc
200
ns
260 -
260 -
ns
100 -
100 -
ns
0.6"1 0.4"1-
0.6.1 tscyc
ns
tRr
50*2
50.2
ms
RESET fall time
tRI
50*2
50"2
ms
Input pin rise time
(other than RESET)
tlr
100"2 -
100.2 ns
Input pin fall time
(other than RESET)
til
100.2 -
100. 2 ns
ADT input pulse
duration
tpWADH
tpwADL
Figure 15
8
8
tcyc
STBY input delay
duration
tSTBYD
Figure 6
0
0
ns
Oscillation stabilization
time
losc
Figure 9
RESET rise time
Figure 19
20
20
ms
Notes: 1. Set so: (tpWSCXH) + (tpwscxd + (tIR) + (tIF) = tSCYC'
2. If these rise and fall times are satisfied, but other specifications are not satisfied, adjust
these rise and fall times to satisfy the other specifications .
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
823
HD648180W
opocode fetch cyce
I
h,
T2
-.J ~BF. .,; I-tcf t cr
tcye
Address
-I
~o
-
tw~
10
. cycle (/
10 read cycle)
/ write
Tw
T,
T3
T,
T3
1,.--
i'----'
(
rtws-l
rt H
/ If ~
tME~~
s
!r-
~
tMEO'
f0o-
.
tAH
~
t~002
"\
tAS
tl002 tAH
t!
t-4!;.:: +--
tl~
II
J
~RDl
WR
tLD2
~
¥~r
\
tRoD,
-
Tw
'J nW r\U~U
1
RD
T2
tWR02
f---.
tWRP
r'\
t
If
J
~STD2
tLOl
'x
ST
If
tSTDl
F
7/ A
'\.'\. '\../"k
Data in
to~~
tORH
=t//",-
~~s
/7"-.
t?RH
tWDZ
II- r-
'-Y "-
-
/ 7
r-t WQi;j ~
"-
twoof
Data out
~
"'-
~~t"'"
tRI
~
tRES~
Io.-t Rr
Note: Output buffer off point.
Note
r- tREH
tRi~Jb.
RI
Op-Code Fetch Cycle and I/O Write Cycle
(I/O Read Cycle) when 10C = 1
Figure 6 CPU Timing (1)
~HITACHI
824
t
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
INTi
Data in· 1
ME ·2
tBAH
BUSREQ
tBADl
tBAD2
BUSACK
Address
Data
ME,RD
WR,IOE
t BZD
t·3
tHADl
HALT
tSTBYD
Notes: 1. For INTo acknowledge cycle
2. For refresh cycle
3. Output buffer off point
INT 0 Acknowledge Cycle, Refresh Cycle, Bus Release Mode,
Halt Mode, sleep Mode, and System Stop Mode
Figure 7 CPU Timing (2)
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
825
HD648180W
~
Q)
(j
~
.~
~
ca:
8
~
g
3:
~
Q)
(j
>-
0
~
""0
cu
r5
~
Q
g
r5
Cl
a:
~
I~
Figure 8 CPU Timing (3)
~HITACHI
826
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
-5.5V
I~~~------------~~~~-------------------
Vee
tose maximum value
RESET _____--\~~~ _ _ _ _ _ _ _ _...... \-_-J" 0.6 V
Figure 9 CPU Timing (4)
_ _CPU or DMA read/write cycle
(TEND j applicable in DMA write cycle only)
DREQj
(level input)
tDRQS
DREQj
(edge input) ---------------- ------ --
------------------------------- ------
t~~~2·-4·
tTED1
tSTD1*3
ST
Notes: 1. Prescribed for clock rising edge immediately before T 3
2. Prescribed for each clock rising edge
3. T1 of DMA cycle start
4. T1 of CPU cycle start
Figure 10 DMA Control Signals
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
827
HD648180W
Timer data
register = OOOOH
troD
Figure
n
Timer Output
Next op-~etch
SLP instruction fetch
Address
ME, LlR,
RD
----i
~------------II
Figure 12 SLP Execution Cycle
~HITACHI
828
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Port
output
Input
Figure 13 Port 1/0 Timing
t scyc
tpWSCXH
\
II
II
SCKO,
SCK1
1\
J
tpWSCXL
Figure 14 SCI Clock Input Timing
tpWTH
II
-\
TIN1
J
1\
tpWTL
Figure 15 Timer 1 Input Pulse Duration
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
829
HD648180W
tpWADH
II
\
ADT
1\
I
tpWADL
Figure 16 ADT Input Pulse Duration
seye
\
-Transmit
data
\
I - tTXD
}.
tSRx
tHRx
/
Receive
'\
data
Figure 17 SCI Clocked Synchronous Timing (direct phase)
EXTAL
V ll1
...,v
-
I-- tEXr
V1H1
V1H1
I-- tEXt
/
\
V 1L1
t EXHW
t EXLW
Figure 18 Rise and Fall TImes for External Clock Input Signal
•
830
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819. (415) 589·8300
HD648180W
Figure 19 Rise and Fall Times for Input Signals (except EXTAL AND RESET)
Vee
Test point ~
1
R....
152074(8)
or equivalent
TT
C = 90 pf
TT
R = 12 kn
RL = 1.Skn
Figure 20 Bus Timing Test Load (TTL load)
=X
2 .0V 2 . 0 V X =
0.8 V 0.8 V
Input signal reference levels
=X
2 .4V 2. 4V X =
0.8 V 0.8 V
Output signal reference levels
Figure 21 Reference Levels
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
831
HD648180W
• Instruction Set Lists
The following explains the symbols used throughout the instruction set lists contained in this
appendix.
1. Register Specification
The register specification symbols are: g, g', ww, xx, yy, and zz. The symbols g and g'
represent 8-bit registers, while ww, xx, yy, and zz represent 16-bit registers, as shown below.
g,g'
Reg.
ww
Reg.
xx
Reg.
yy
Reg.
zz
Reg.
000
B
00
BC
00
BC
00
BC
00
BC
001
C
01
DE
o1
DE
01
DE
01
DE
010
10
HL
10
IX
10
IV
10
HL
01 1
D
E
11
SP
11
SP
11
SP
11
AF
100
H
1 01
L
111
A
Note: The letters "H" (high) and "L· (low) are appended to the 16·bit register symbols to indicate
the upper 8 bits and lower 8 bits. For example: wwH, IXL.
2.
Bit Specification
The symbol b in the bit operand of a bit manipulation instruction, specifies the bit location as
shown below.
b
Bit
000
0
001
1
010
2
o1 1
3
1 00
4
1 01
5
110
6
111
7
832
• HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
HD648180W
3.
Condition Specification
The symbol f specifies the condition against which the result of an operation is compared to
determine the next instruction to be executed, as shown below.
Condition
000
NZ
non zero
a 01
a1a
a11
1 aa
Z
zero
NC
non carry
C
carry
parity odd
101
PO
PE
110
P
sign plus
111
M
sign minus
4.
parity even
Restart Address
The symbol v specifies the restart address for a restart instruction, as shown below.
v
Address
000
OOH
001
08H
01 0
10H
011
18H
1 00
20H
1 01
28H
110
30H
111
38H
5.
Flags
The following symbols are used to denote changes in flags.
Flag not affected
x: Flag change undefined
t: Flag affected according to operation result
S: Flag set to 1
R: Flag reset to 0
P: Flag changes as a parity flag
V: Flag changes as an overflow flag
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
833
HD648180W
6.
Other Symbols
( )M: Parentheses contain memory address
( )1: Parentheses contain I/O address
m or n: 8-bit value
mn: 16-bit value
r: r suffix indicates 8-bit register
R: R suffix indicates 16-bit register
b • ( )M: b-th bit of memory address in parentheses
b • gr: b-th bit of general register gr
d or j: Signed 8-bit displacement
S: Source addressing mode
D: Destination addressing mode
.: AND operation
+: OR operation
EB: XOR operation
•
834
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
• Data Manipulation Instructions
1.
Arithmetic and Logical Instructions (8-bit)
Flag
Addressing
0
Operation
Name
Mnemonics
ADD
ADC
AND
ADD A. 9
~Code
w
2 ~
;;i1 w
><
0
~
10000g
a
(!)
-'
w w a.. w
a: a: :iii a: Bytes Slates
1
0
6
S
Z H PN N C
t t V R t
t
t t t V R t
D
1
4
Ar+gr ..... Ar
S D
1
6
Ar + (HLlt.i ..... Ar
D
2
6
Ar+m ..... Ar
S
4
2
7
~eration
ADD A. (HL)
10000 110
ADD A. m
11000110
ADD A. (IX+ d)
11011101
10000110
S
D
3
14
Ar+ (IX +d}M ..... Ar
t t t V R t
ADD A, (IY + d)
11111101
10000110
S
D
3
14
Ar+ (IY + dIM ..... Ar
t t t V R t
ADC A. 9
10001 9
D
1
4
Ar+gr+c ..... Ar
ADCA,(HL)
10001110
D
1
6
Ar+ (HLh.1 + c ..... Ar
ADCA. m
11001110
D
2
6
Ar+m+c ..... Ar
t t t V R t
t t t V R t
t t t V R t
ADC A, (IX + d)
11011101
10001110
S
D
3
14
Ar + (IX + dIM + C ..... Ar
t t t V R t
ADC A, (IY + d)
11111101
10001110
S
D
3
14
Ar + (IY + dIM +C ..... Ar
t t t V R t
ANDg
10100g
AND (HL)
10100 110
P
ANDm
11100110
AND (IX + d)
11011101
10100 110
AND (IY + d)
11111101
10100 110
Compare CPg
S
S
s
S
10111110
CPm
11111110
1
4
Ar·gr ..... At
1
6
Ar·(HL}M ..... Ar
D
2
6
Ar'm ..... Ar
t t s
t t s
t t S
S
D
3
14
M(IX+ d}M ..... Ar
t t S
P R R
S
D
3
14
Ar·(IY + dIM ..... Ar
t t S
P R R
S
P R R
D
1
4
Ar-gr
t t t V
1
6
Ar- (Hl)M
t
D
2
6
Ar-m
t t t V
S
$
t
t
R R
P R R
S D
S
10111 9
CP (HL)
D
S D
S
S
V S
S
t
t
t
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
835
HD648180W
1. Arithmetic and Logical Instructions (8·bit) (cont)
Flag
Addressing
7
0
Operation
Mnemonics
Name
w
~Code
~
0 Ci
!;< ~ w
w
iii:
4
2
1
0
...J
0.. w
a: a: ;;I a: Bytes States
;;I w
6
~eration
S Z H PN N C
CP (IX +d)
11011101
10111110
S
D
3
14
Ar-(IX+ dIM
t t t
V S
CP (IV +d)
11111101
10111110
S
D
3
14
Ar-(IY +d)M
t t t
V
s t
Complement
CPL
00 101111
SID
1
3
Ar-+ Ar
- -
-
S
-
DEC
DECg
OOg 101
1
4
gr-l-+gr
V S
-
DEC (HL)
00 110 101
1
10
(HL)M - 1 -+ (HL)M
DEC (IX+ d)
11011101
00110101
SID
3
18
(IX+d)M-l-+
(IX+d)M
t t t
t t t
t t t
DEC (IY + d)
11111101
00 110 101
SID
3
18
(IY + dIM -1 -+
(IV + dIM
t
t
t
t
t
t
Compare
INC
INCg
OOg 100
INC (HL)
00 110 100
INC (IX+d)
11011101
00 110 100
INC (IV +d)
11111101
00 110 100
MULT
MLTww
11101101
01 wwll00
NEGATE
NEG
11101101
01000100
OR
SID
SID
V S
-
V S
-
t
V S
t
t
t
V R
V R
-
-
1
4
gr+l-+gr
1
10
(HL)M + 1 -+ (HL)M
SID
3
18
(IX+d)M+l -+
(IX + d)M
t
t t
V R
SID
3
18
(IY + dIM + 1 -+
(IV + dIM
t
t
V R -
2
17
wwHr x wwLr -+ ww
- - - -
SID
2
6
O-Ar-+Ar
t t t
D
1
4
Ar+gr-+Ar
R P R R
1
6
Ar + (HL)M -+ Ar
t
t
t
D
t
R P R R
D
2
6
Ar+m-+Ar
t
t R
SID
SID
SID
S
t
-
-
V S
t
ORg
10110g
OR (HL)
10110110
ORm
11110110
OR (IX+d)
11 011101
10110110
S
D
3
14
Ar + (IX + dIM -+ Ar
t t
R P R R
OR (IY +d)
11111101
10110110
S
D
3
14
Ar + (IV + dIM -+ Ar
t
R P R R
S
S
$
836
S
t
t
P
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
R R
HD648180W
1.
Arithmetic and Logical Instructions (8-bit) (cont)
Flag
Addressing
0
L.U
Operation
Mnemonics
Name
OpCode
SUB
SUBg
10010 9
SUB (HL)
to 010 110
SUBm
t1 010110
SUB (IX td)
t1011101
to 010 110
SUB(IY +d)
11111101
10010110
SBCA, 9
10011 9
SBCA, (HL)
10011110
SBCA, m
11 011 110
SBC A, (IX + d)
11 011 101
10011110
SBC A, (IV +
TSTg
11101101
00 9 100
TST (Hl)
11101101
00 110 100
TSTm
11101101
01100 100
XORg
10101 9
SUBC
TEST
XOR
::;;
XOR (HL)
10101110
XORm
11101110
XOR (IX+d)
11011101
10101110
XOR (IY +d)
11111101
10101110
;1!l
a
><
(!)
-'
0
L.U L.U "- L.U
~ il::
a: a: ;1!l a: Bytes States
L.U
4
2
1
0
7
6
Operation
S
Z H PN N C
D
t
4
Ar-gr~Ar
t
1
6
Ar - (HL)M ~ Ar
t t t
t t t
V S
D
V S
t
D
2
6
Ar-m~Ar
t
t
t
V S
t
S
D
3
14
Ar- (IX + dIM ~ Ar
t
t t
V S
t
S
D
3
14
Ar- (IY + dIM ~ Ar
t t t
V S
t
D
1
4
Ar-gr-c~Ar
1
6
Ar- (HL)M - c -> Ar
D
2
6
Ar-m-c~Ar
t t t
t t t
t t t
V S
D
V S
t
t
t
S
D
3
14
Ar - (IX + dIM - c -> Ar
t t t
V S
t
S
D
3
14
Ar- (IY + d)M-c ~ Ar
t t t
V S
t
2
7
Ar-gr
t t
S
P R R
2
10
Ar·(HL)M
t t
S
P
R R
3
9
Ar·m
t
t s
P
R R
1
4
Ar$gr~
S
S
S
S
S
S
S
S
S
V S
D
1
6
Ar $ (HL)M -> Ar
D
2
6
Ar$m~Ar
t t
1 t
t t
S
D
3
14
Ar$ (IX + dIM -> Ar
1 t
R
P
R
S
D
3
14
Ar$(IY + dIM
t
R
P
R R
D
S
S
S
Ar
~
Ar
t
R
P
R R
R
P
R R
R
P
R
R
R
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
837
HD648180W
2.
Rotate and Shift Instructions
Flag
Addressing
Operation
Mnemonics
Name
RLA
Rotale
and
RLg
shift data
Cl
UJ
:::;;
OpCode
~
~
UJ
x
Cl
~
UJ
CI
@ c..
IX
IX
~
SID
00010111
SID
11001011
00 010 9
7
--'
UJ
IX
6
4
2
Operation
lcJ..i1111111~
0
t
t
R P R
t
t
13
t
t
R P
R
t
t
R P
R
t
1
3
2
7
2
C
b7-bO
R
R
RL (HL)
11001011
00010110
RL(IX+el)
11011101
11001011
00010110
SID
4
19
t
RL (IV +ell
11111101
11001011
00 010 110
SID
4
19
t t
R P R t
RLCA
00 000 111
1
3
- -
R
-
R t
t t
R P
R t
RLC 9
11001011
00 OOOg
RLC (HL)
11 001 011
00000110
RLC (IX + d)
11011101
11001011
00 000110
RLC (IV + d)
11111101
11001011
00 000110
RLD
11101 101
01101111
RRA
00011111
RR 9
11001011
00011 9
RR(HL)
11001011
00011110
RR (IX + d)
11011101
11001011
00011110
RR (IV + d)
11111101
11001011
00011110
RRCA
00001111
RRCg
11001011
00001 9
SID
SID
041111111~
C
.7
bO
2
7
2
13
t
t
R P R t
SID
4
19
t
t
R P R t
SID
4
19
t
t
R P
R t
t
t
R P
R
SID
SID
a
b7
SID
SID
2
16
R
R P
13
t
R P R t
4
19
t t
R P
R t
4
19
t
R P
R t
1
3
2
7
7
2
SID
SID
SID
SID
Yllllillro-J
b7_bO
C
Y.7IIIIIIIbOkJC
t
t
-
-
t t
3
SID
(Hl)M
bD
- -
1
2
SID
Ar
R t
R
- -
R
-
R
t t
R P
R
~HITACHI
838
1
S Z H PN N C
Bytes States
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
t
t
t
HD648180W
2. Rotate and Shift Instructions (cont)
Flag
Addreiling
Operation
Mnemonics
Name
RRC (HL)
Rotate
and
shift data RRC (IX+ d)
C4'lCode
i~i
~ ~ II ~
S1)
II 001 011
00 001110
e
2
13
2 I 0
S Z H PN N C
t t R P R t
7
Bytel Statn
C4'leratlon
4
11011101
11 001 011
00 001110
S1)
4
19
t t
R P R
l
RRC (IV + d)
11111101
11001011
00001110
S1)
4
19
t
t
R P R
t
RRD
11101101
01100 111
2
16
t
t
R P R
-
t
t
R P R
t
t t
R P R
t
SLAg
11001011
00 100 9
SLA (HL)
11001011
00 100 110
SLA (IX +d)
11011101
11001011
00 100 110
SLA (IV +d)
11111101
11001011
00 100 110
SRAg
11001011
001101 9
SRA(HL)
11001011
00 101110
SRA(IX+d}
11011101
11001011
00 101110
SRA(IY +d}
11111101
11001011
00 101110
SRLg
11001011
00 111 9
SRL (HL)
11001011
00 111110
SRL (IX + d)
11 011101
11001011
00 111110
SRL (IV + d)
11111101
11 001 011
00 111110
SID
=}
.7
..
.7
..
(HU ..
2
7
2
13
SID
4
19
t t
R P R
t
SID
4
19
t t
R P R
t
2
7
[[1111111
t-{] t t
.7
.. C
R P R
t
2
13
t t
R P R
t
SID
4
19
t t
R P R
t
SID
4
19
t t
R P R
t
2
7
R P R
t
2
3
SID
4
19
t
t
R P R t
SID
4
19
t
t
R P R
SID
SID
SID
SID
SID
SID
•
-
..
D-!
I I I I I I I 1-.
C .7
--.-1 I I I I I I I..Klc t t
"'
t t
R P R t
t
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
839
HD648180W
3.
Bit Manipulation Instructions
Flag
Addressing
Cl
Operation
Mnemonics
Name
Bttset
Btt reset
Bitlesl
Op Code
SETb, 9
11 001 011
l1b 9
SETb, (HL)
11 001 011
11 b 110
SET b, (IX + d)
11 011101
11 001 011
l1b 110
SET b, (IV + d)
11111101
11 001 011
l1b 110
RES b, 9
11 001 011
lab 9
RES b, (HL)
11 001 011
lab 110
RES b, (IX + d)
11 011101
11 001 011
lab 110
RES b, (IV + d)
11111101
11 001 011
lab 110
BIT b, 9
11 001 011
01 b 9
BIT b, (HL)
11 001 011
01 b 110
BIT b, (IX + d)
11 011 101
11 001 011
01 b 110
BIT b, (IV + d)
11111 101
11001011
01 b 110
a
LU
x C!l
:::;; !;( Cl
-'
a.. UJ
UJ W
;!l w ;;:; a: a: ;!l a: Bytes States
1
a
6
Z H PN N C
4
Operation
S
2
7
1 -+b-gr
- - - - - -
2
13
1 -+b-(HL)M
------
SID
4
19
1 -+ b-(IX + d)M
------
SID
4
19
1 -+ b-(IV + d)M
------
2
7
a -+b-gr
------
2
13
a -+b-(HL)M
------
SID
4
19
a -+ b-(IX + d)M
------
SID
4
19
0-+ b-(IV + d)M
------
2
6
b-gr -+ z
X
t
S
X
R
-
2
9
b-(HL)M -+z
X
t
S
X
R
-
S
4
15
b-(IX + d)M -+ Z
X
t
S
X
R
-
S
4
15
b-(IV + dh.t -+ Z
X
t
S
X
R
-
SID
SID
SID
SIO
S
S
~HITACHI
840
2
7
Hitachi America, Ltd_ • Hitachi Plaza. 2000 Sierra Point Pkwy_ • Brisbane, CA 94005-1819. (415) 589-8300
HD648180W
4. Arithmetic Instructions (16·bit)
FIIf
Addr.lling
Operation
Mnemonic.
Name
Op Code
ADO
ADDHL. ww
OOwwlOOI
ADO IX. xx
11011101
00 xxI 001
ADO IY. Y'f
ADe
DEC
INC
SBC
I SI i
i
Ii i
SVIti
aa,..
Op.ratlon
0
1
7
HI.R +ww" ... HI.R
0
2
10
IX" + ~(II ... 1)("
S
0
2
10
IYR + yy" ... IY"
11101101
01 wwl 010
S
0
2
10
HLR +WWR + C ... HLR
DECww
OOwwl0ll
SIO
1
4
wwR-l ... wwR
DEC IX
11011101
00 101011
SIO
2
7
IXR-l ... IXR
DECIY
II III 101
00 101011
SIO
2
7
IYR-l-+IYR
INCww
00 WWO 011
I
4
WWR + I -+WWR
INC IX
11011101
00 100 OIl
SIO
2
7
INCIY
II III 101
00 100 OIl
SIO
2
SBCHL.ww
11101101
01 WW0010
D
2
S
S
11111101
OOyylOOl
ADCHL. ww
SIO
S
2
•
S Z
-- -- -- -
0
H PN N C
7
l
~
4
1
)(
)(
R ~
R ~
)(
R ~
X V R
t
- - - - -
IX R+ 1-+ IXR
- - - - - - -- -- - - - - - -
7
lyR+l ...... IYR
- - - -
- -
10
HLR - wwR - c ...... HLR
t t X
- -
V S
t
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
841
HD648180W
• Data Transfer Instructions
1.
8-Bit Load
Addressing
0
UJ
><
a
Flag
6
Ir ..... Ar
t
t
R IEF2 R
-
2
6
Rr ..... Ar
t
t
R IEF2 R
-
- - - - - - - - - - - - - - - -
LDA, I
11101101
01010 111
SID
2
LDA, R
11101101
01011111
SID
~
UJ
0
~
Cl
UJ
UJ
a: a:
0..
~
4
....J
UJ
a: Bytes States
LDA, (BC)
00 001010
S
D
1
6
(BC)M ..... AnNale)
LDA, (DE)
00 011 010
S
D
1
6
(DE)M ..... Ar
LDA, (mn)
00 111010
D
3
12
(mn)M ..... Ar
LDI,A
11101101
01 000111
SID
2
6
Ar ..... lr
- - -
LDR, A
11101101
01 001111
SID
2
6
Ar ..... Rr
- - -
S
-
- -
- - - - - - -
LD (BC), A
00 000 010
D S
1
7
Ar ..... (BC)M
-
LD(DE), A
00010010
D S
1
7
Ar ..... (DE)M
LD (mn), A
00 110 010
S
3
13
Ar ..... (mn)M
- - - - - - - - - - -
LDg, g'
01 g g'
1
4
gr' ..... gr
LD g, (HL)
01 g 110
1
6
(HL)M ..... gr
LDg, m
OOg 110
D
2
6
m ..... gr
LDg, (IX+d)
11 011101
01 9 110
S D
3
14
(IX + d)M ..... gr
- - -
LD g, (IV + d)
11111101
01 9 110
S D
3
14
(IV + d)M ..... gr
------
LD (HL), m
00110110
S
2
9
m ..... (HL)M
- - - - - -
LD (IX+ d), m
11 011101
00 110 110
S
D
4
15
m ..... (IX +d)M
- - - - -
LD (IV + d), m
11111 101
00 110 110
S
D
4
15
m ..... (IV +d)M
- -- - - -
D
00
D
S
S
D
- - - - - - - - - - - - - - - -
Note: Interrupts are not detected at the end of the LD A, I and LD A, R instructions.
•
842
0
Z H PN N C
Load
8-bit data
~
1
6
S
Q>Code
::;;
2
7
Q>eration
Operation
Name
Mnemonics
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
- -
-
HD648180W
1.
8-Bit Load (cont)
Flag
Addressing
Cl
Operation
Mnemonics
Name
LD (HL), 9
Load
8-bit data
LD (IX + d), 9
LD (IV + d), 9
2.
~Code
a
w
>< (!)
:;; !;< Cl
w w
~
w
~
a: a:
--'
a.. w
~ a: Bytes States
4
2
1
0
7
6
~eration
S
Z H PN N C
1
7
gr~(HL)M
11 011101
01110g
0
S
3
15
gr~(IX+d)M
- - - - - - - - - - -
11111101
01110g
0
S
3
15
gr~(IV+d)M
------
S
01110 9
0
16-Bit Load
Addressing
Cl
Operation
Mnemonics
Name
Load
LDww, mn
16-bit data
~Code
w
x
:;; !;< Cl
~
00 WWO 001
S
LD IX, mn
11011101
00 100 001
S
LD IV, mn
11 111 101
00 100 001
S
LU
~
(!)
LU
a
LU
a: a:
Flag
--'
a.. w
~ a: Bytes States
2
1
0
7
6
~eration
S
Z H PN N C
- -
4
- - -
3
9
mn~wwR
-
D
4
12
mn -> IXA
- - - - - -
0
4
12
mn -> IVA
-
D
-
- - - -
LDSP, HL
11 111 001
SiD
1
4
HLR ~SPR
LDSP, IX
11 011 101
11 111 001
SiD
2
7
IXR ~SPA
- - - - - - - - - - -
LDSP, IV
11 111 101
11 111 001
SiD
2
7
IVA -> SPA
- -
LDww, (mn)
11101101
01 wwl 011
S
4
18
(mn+ I)M ~wwHr
- - -
LD HL, (mn)
00 101 010
S
3
15
(mn+l)M~Hr
- - - - - -
0
D
- - - -
- -
(mn)M~Lr
.HITAOHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589-8300
843
HD648180W
2.
16-Bit Load (cont)
Flag
Addressing
Cl
Operation
Mnemonics
Name
w
~
>< <.!l (3
..J
~ Cl w w a. w
w ;;:; a: a: ~ a: Bytes States
7
6
4
2
1
0
Operation
S
Z H PN N C
LD IX, (mn)
Load
16-bit data
11011101
00 101 010
S
0
4
18
(mn + I)M -+ IXHr
(mn)M -+ IXLr
-
- -
LD IY, (mn)
11111101
00 101010
S
0
4
18
(mn + I)M -+ IYHr
(mn)M -+ IYLr
------
LD(mn),ww
11101101
01 wwOOll
D
4
19
wwHr-+(mn+l)M
wwLr -+ (mn)M
------
LD (mn), HL
00 100010
D
S
3
16
Hr -+ (mn + I)M
Lr -+ (mn)M
------
LD (mn),IX
11011101
00 100 010
0
S
4
19
IXHr -+ (mn + I)M
IXLr -+ (mn)M
------
LD (mn),IY
11111101
00 100010
D
S
4
19
IYHr -+ (mn + I)M
IYLr -+ (mn)M
------
OpCode
~
S
-
~HITACHI
844
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
- -
HD648180W
3.
Block Transfer
Addressing
Flag
0
Operation
Mnemonics
Name
Block
transfer
search
data
Op Code
LU
::;; !;( 0x
~
LU
~
c:5
Q.
..J
a: a:
~
a: Bytes States
Cl
LU
LU
w
4
2 1
0
7
6
Operation
S
Z H PN N C
'2
'1
-
CPD
t110tl0l
10101001
S S
2
12
Ar-(HL)M
BCA-l ..... BCA
HLA -1 ..... HLR
t t t t
CPDR
11101101
10111001
S
2
14
12
BCA .. 0 Ar .. (HL)M
BCA = 0 or Ar = (HL)M
[ Ar- (HL)A
Q BCA-l ..... BC A
HLA -1 ..... HLA
Repeat Q until
Ar = (HL)M or BC A = 0
t t t t s -
S
'2
S
'I
'2
'I
t t t t S t t t t s -
CPI
11101101
10100 001
S
S
2
12
Ar- (HL)M
BCA-l ..... BCA
HLA + 1 ..... HLA
CPfR
11101101
10110001
S
S
2
14
12
BCA .. 0 Ar .. (HL)M
BCA = 0 or Ar = (HL)M
[ Ar- (HL)M
Q BCA-l ..... BCA
HLA + 1 ..... HLR
Repeat Q until
Ar = (HL)M or BCA = 0
t t t t
LDD
11101101
10101 000
SiD
2
12
(HL)M ..... (DE)M
BCA-l ..... BCR
DER -1 ..... DER
HLA -1 ..... HLR
- -
R
t
LDDR
11101101
10111000
SiD
2
14 (BC R.. 0) [ IHl), ~ IDEI,
12 (BC R= 0) Q BCA-l ..... BCR
DEA -1 ..... DER
HLA -1 ..... HLA
Repeat Q until
BCA = 0
-
-
R
LDI
11101101
10100 000
SiD
2
12
- -
R
t
R
-
LDIR
11101101
10110000
SiD
2
14 (BC A.. 0) [ IHl), ~ 10O,
12 (BC A= 0) Q BCA-l ..... BC R
DEA + 1 ..... DEA
HLR + 1 ..... HLR
Repeat Q until
BCA =0
- -
R
R
R
-
(HL)M ..... (DE)M
BC A-1 ..... BC A
DER + 1 ..... DEA
HLR + 1 ..... HLA
'2
'I
S
-
R
-
R R
-
'I
'1
Notes 1 PN = 0: BCA - 1 = 0
PN = l' BC A- 1 .. 0
2. Z = l' Ar = (HL)M
Z=O: Ar .. (HL)M
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
845
HD648180W
4.
Stack and Exchange
Flag
Addressing
0
LU
Opera1ion
Mnemonics
Name
~Code
PUSH
PUSH zz
11 zzO 101
PUSH IX
POP
~
!;< ;s:;
Cl
a
4
2
0
6
Z H PN N C
a. -'
w
~ a: Bytes Stales
S
D
1
11
zzLr .... (SP - 2}M
zzHr .... (SP -l}M
SPR-2 .... SPR
- - -
11011101
11100 101
SID
2
14
IXLr .... (SP - 2}M
IXHr .... (SP-l}M
SPA-2 .... SPA
------
PUSHIY
11111101
11100 101
SID
2
14
IYLr .... (SP - 2}M
IYHr .... (SP -l}M
SPA-2 .... SPA
------
POPzz
11 zzO 001
S
1
9
(SP + l}M .... zzH~Not.)
(SP}M .... zzLr
SPA+2 .... SPA
-
POP IX
11011101
11100001
SID
2
12
(SP+ I}M .... IXHr
(SP}M .... IXr
SPA+2 .... SP A
------
POPIY
11111101
11100001
SID
2
12
(SP + I}M .... IYHr
(SP}M .... IYLr
SPA+2 .... SPA
------
00001000
SID
1
4
AFA .... AF A'
3
DEA- HLA
- - - - - - - - - - - - - - - - - - - -
Exchange EXAF, AF'
w
LU
D
W
~eration
-
-
-
-
-
- - -
-
EX DE, HL
11101 011
SID
1
EXX
11011001
SID
1
3
BCA-BCA'
DEA- DEA'
HLA - HLA'
EX (SP), HL
11100 011
SID
1
16
Hr-(SP+ I}M
Lr-(Sp}M
-
- - -
- -
EX (SP), IX
11011101
11100 011
SID
2
19
IXHr- (SP + I}M
IXLr-(SP}M
-
- - -
-
EX (SP), IY
11111101
11100 011
SID
2
19
IYHr- (SP + I}M
IYLr-(SP}M
- - - - - -
Note: POP AF writes stack contents to flag.
~HITACHI
846
1
7
S
a: a:
:::I!
~
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
-
HD648180W
• Program Control Instructions
I
Addressing
Operation
Name
Mnemonics
Call
Jump
~Code
~
~
Flag
)(
c;
c Cl
w w a.. -'
w
~ i!;
~
Bytes States
w
a:: a::
a::
7
6
4
~eration
S
Z
H PN N C
2
1
0
-
- - - -
CAllmn
11001101
D'
3
16
PCHr -> (SP - 1hA
PClr -> (SP - 2}M
mn-> PC R
SPR - 2 -> SPR
-
CAllI, mn
111 100
<0>
0
3
6(1: lalse)
16 (I: true)
continue: I is lalse
CAll mn: I is true
- -
DJNZj
00010000
9 (Br .. O)
7(Br= O}
Br-l->Br
continue: Br = 0
PCR + j -> PCR: Br .. 0
-
- -
2
- - - - -
0 2
- -
- -
- - -
JPI, mn
111 010
<0>
0
3
3
6(1: lalse}
9(1: true}
mn -> PC R: I is true
continue. I is lalse
-
JPmn
11 000011
<0>
0
3
9
mn --+ PC R
- - - - - -
JP(Hl}
11101001
0
1
3
HlR -> PCR
JP(IX}
11011101
11101 001
D
2
6
IXR --+ PCR
- - - - - - - - - - -
JP(IY}
11111101
11101001
0
2
6
IY R -> PCR
-
JRj
00 011 000
0 2
8
PCR + j --+ PCv
- - - - - -
JRC,j
00 111000
D 2
2
6
8
continue' C = 0
PCR + j -> PCR: C = 1
- -
-
- - -
JRNC,j
00 110 000
0 2
6
- - -
8
continue' C = 1
PCR + j -> PC R: C = 0
- - -
2
00 101000
D 2
6
8
continue' Z = 0
PC R+ j -> PC R: Z = 1
- - - - - -
00100000
0 2
6
8
continue: Z = 1
PCR + j -> PCR: Z = 0
- - -
2
1
9
(SPlt.1 -> PClr
(SP + I}M --+ PCHr
SPR + 2 -> SPR
-
5(1: lalse)
10 (I: true)
continue: I is lalse
RET: I is true
- - - - - -
22 (Z)
12 (Rl)
(SP}M --+ PCLr
(SP + I}M -> PCHr
SPR + 2 --+ SPR
- - - - - -
JR Z,j
JR NZ,j
Return
cw
RET
11001001
RETI
111 000
2
0
0 1
1
RETI
11101101
01001101
0
•
2
- -
-
- -
- -
-
- - - - -
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
847
HD648180W
• Program Control Instructions (cont)
Flag
Addressing
Operation
Name
Mnemonics
c
w
::E
QlCode
~
~
~
~
Sl
~
cr cr
Q.
...J
~
cr Bytes States
W
4
1
7
6
Qleration
S
Z H PN N C
2
0
Return
RETN
11101101
01000101
D
2
12
(SP)M --+ PCLr
(SP + 1)1.1 --+ PCHr
SPR + 2 --+ SPR
IEF2 --+ IEFl
- - - - - -
Restart
RSTv
11 v 111
D
1
11
PCHr --+ (SP-l)M
PCLr --+ (SP - 2)M
0--+ PCHr
v --+ PClr
SPR- 2 --+ SPR
------
• 1/0 Instructions
Flag
Addressing
Operation
Name
Mnemonics
Input
cw
QlCode
::E
~
Ii<
w
~
~
Sl
~
cr cr
INA. (m)
11011011
lNg, (C)
11101101
01 g 000
D
INOg. (m)
11101101
OOg 000
D
IND
11101101
10101010
Notes: 1. Z=I:
Z=O:
2. N=I:
N = 0:
7
D
...J
~
cr Bytes States
W
4
Qleration
S Z
D S 2
9
(Am),--+Ar
m --+ Aoto A7
Ar --+ As to A1S
- - -
S 2
9
(BClt --+ gr
g = 110: only the
flags will change.
Cr --+ Ao to A7
Br --+ As to A1S
2
1
0
H PN N C
-- -
t
t
R P R -
t
R P
S 3
12
(OOm), --+ gr
9 = 110: only the
flags will
change.
m -+Ao IOA7
00 -> As to A1S
t
'1
'2
S 2
12
(BC), -> (Hl)M
HlR - 1 --+ HlR
Br-l->Br
Cr --+Ao toA7
Br -> As to Ats
X t
X X t
Br-l =0
Br-l .. 0
MSBofdata=l
MSB of data =0
•
848
Q.
6
HITACHI
Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
R
'2
-
X
HD648180W
• 1/0 Instructions (cont)
Flag
Addressing
0
Operation
Mnemonics
Name
Input
INOR
U.J
~
OpCode
;;!i
c;
><
o Cl
U.J U.J a. -'
U.J
!><
U.J ;;!; cc: cc: ;;!i cc: Bytes States
0
11101101
10111010
S 2
14 (Br .. O)
t2 (Br=O)
2
1
0
7
6
4
Operation
S
Z
H PN N C
( (BC)I ~ (HLlt.4
HLR-l ~HLR
Br-l ~Br
Repeat Q until
Br=O
X S
X X
t
X
Q
Cr~AotoA7
Br~AstoA15
'2
'I
0
11101101
10100 010
INI
S 2
12
(BC)I ~ (HLlt.4
HLR+l ~HLR
Br-l ~Br
X
t
X X
t
X
Cr~AotoA7
'2
Br~AstoA'5
0
11101101
10110010
INIR
S 2
14(Br .. 0)
12 (Br =0)
( (BC)I ~ (HL)M
Q HLR +1 ~HLR
Br-l ~Br
Repeat Q until
Br= 0
X S X X
t
X
Cr~AotoA7
Br~AstoA'5
OUT (m),A
Output
S
11010011
0 2
10
Ar~(Amh
------
m~AotoA7
Ar~AstoA'5
OUT (C), 9
11101101
01 9 001
S
11101101
00 9 001
S
0 2
10
gr~(BC)1
------
Cr~AotoA7
Br~AstoA15
OUTO (m), 9
11101101
10001011
OTOM
0 3
13
gr~(OOm)1
-
- - - - -
m~AotoA7
00~AstoA15
S
0 2
14
(HL)M ~ (OOC)I
HLR -1 ~ HLR
Cr-l ~Cr
Br-l --> Br
'2
'I
t t t P t t
Cr~AotoA7
00 ~Asto A'5
OTDMR
Notes: 1.
2.
Z= 1:
Z = 0:
N=I:
N = 0:
11101101
10011011
S
0 2
16 (Br .. O)
14(Br=0)
[ I"W, ~ IOOCI,
'2
R S
R S
HLR-l ~HLR
Cr -1 --> Cr
Br-l --> Br
Repeat Q until
Br= a
Cr --> Ao to A7
00 --> ~ to A'5
t
R
Q
'2
Br-l =0
Br-l .. 0
MSBofdata=1
MSB of data = a
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
849
HD648180W
• 1/0 Instructions (cont)
Flag
Addressing
Operation
Name
Mnemonics
Output
2.
OpCode
::;; !;(
;l w
x
c
~
~
aW
0.. -'
W
S 3
12
(OOC)rm
Cr -+1.oto A7
00 -+ I\; to A1S
t t
(HL)M -+ (OOCIi
HLR + 1 -+ HLR
Cr+l-+Cr
Br-l-+Br
Cr -+1.oto A7
00 -+ I\; to A1S
t t t P t t
S
OTIM
11101101
10000011
S
D 2
14
OTIMR
11101101
10010011
S
D 2
16 (Br .. O)
14(Br=0)
11101101
10101011
S
Z=I:
Z=O:
N=I:
N=O:
D 2
12
[ IHLl. ~ ."l,
S
X
P R R
'I
'2
'2
R S
Q HLR + 1 -+ HLR
Cr+l -+Cr
Br-l-+Br
Repeat Q until
Br=O
Cr -+ 1.0 to A7
00 -+ I\; to A1S
(HL)M -+ (Bell
HLR-l -+ HLR
Br-l -+Br
Cr -+ 1.0 to A7
Br -+ I\; to A,s
X
'2
R S
'I
X
t
R
'2
t X X t X
Br-l =0
Br-l .. 0
MSB of data: 1
MSB of data=O
~HITACHI
850
1
OTDR
OUTD
Notes: 1.
cw
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
• Special Control Instructions
Addressing
0
Operation
Name
Mnemonics
w
~Code
~
~
;;; w
><
0
~
(!)
Flag
4
2
1
0
6
~eration
S
Z H PN N C
a
-'
w 0.. w
a: a: ;;; a: Bytes States
w
7
1
4
Decimal
adjust
accumulator
t t t
00 111111
1
3
C-+C
SCF
00 110 111
1
3
I-+C
01
11110011
1
3
0-+ lEFt, 0 -+ IEF 2(NoIe
- - R - R t
- - R - R S
- - - - - - - - - - - - - - - - - - - - -
Special
function
OM
00100 111
Carry
control
CCF
CPU
control
Si1)
EI
11111011
1
3
1 -+ lEFt, 1 -+ IEF2(NoIe
HALT
01110110
1
3
CPU halted
IMO
11101101
01000110
2
6
(nterrupt
mode 0
IMI
11101101
01010110
2
6
Interrupt
mode 1
-
1M2
11101101
01011110
2
6
Interrupt
mode 2
- - -
NOP
00 000000
1
3
No ope ration
SLP
11101101
01110110
2
8
Sleep
P
-
t
- - - - -
-
- -
- - - - - - - -
-
-
Note: InterrLpts are not detected at the end of the 01 or EI instruction.
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
851
HD648180W
• Alphabetical Instruction List
Mnemonics
Bytes
Machine Cycles
States
ADCA, m
2
2
6
2
4
ADCA,g
ADCA, (HL)
2
6
ADC A, (IX + d)
3
6
14
ADC A, (IY + d)
3
6
14
2
6
10
2
2
6
ADDA,g
2
4
ADD A, (HL)
2
6
ww
ADCHL,
ADD A, m
ADD A, (IX + d)
3
6
14
ADD A, (IY + d)
3
6
14
1
5
7
ADD IX, xx
2
6
10
ADD IY, yy
2
6
10
ANDm
2
2
6
ANDg
2
4
AND (HL)
2
6
ADD HL,
ww
AND (IX + d)
3
6
14
AND (IY + d)
3
6
14
BIT b, (HL)
2
3
9
BIT b, (IX + d)
4
5
15
BIT b, (IY + d)
4
5
15
BITb,g
2
2
6
CALL f, mn
3
3
2
6
6 (If condition is false)
16 (If condition is true)
CALL mn
3
6
16
1
3
CCF
CPD
2
6
12
CPDR
2
2
8
14 (If BC R 0 and Ar (HL)M)
12 (If BC R = 0 or Ar = (HL)M)
*
6
*
~HITACHI
852
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
HD648180W
Mnemonics
Bytes
Machine Cycles
States
CP (HL)
1
2
6
CPI
2
6
12
CPIR
2
2
8
14 (If BCR 0 and Ar (HL)~,d
12 (If BCR - 0 or Ar .. (HL)~,d
CP (IX + d)
3
6
14
CP (IV + d)
3
6
14
CPL
1
1
3
CPm
2
2
6
CPg
2
4
DAA
2
4
DEC (HL)
4
10
'*
6
DEC IX
2
3
7
DEC IV
2
3
7
DEC (IX + d)
3
8
18
DEC (IV + d)
3
8
18
DECg
2
4
DECww
2
4
DI
1
DJNZj
2
2
'*
3
'*
5
3
9 (If Br 0)
7 (If Br = 0)
EI
1.
3
EX AF. AF'
2
4
EX DE. HL
3
EX (SP). HL
6
16
EX (SP). IX
2
7
19
EX (SP). IV
2
7
19
EXX
3
HALT·
1
1
3
IMO
2
2
6
1M 1
2
2
6
1M2
2
2
6
•
HITACHI
Hitachi America. Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
853
HD648180W
Mnemonics
Bytes
Machine Cycles
States
INCg
1
2
4
4
10
INC (HL)
INC (IX + d)
3
8
18
INC (IV + d)
3
8
18
2
4
INCww
INC IX
2
3
7
INCIV
2
3
7
IN A, (m)
2
3
9
IN g. (C)
2
3
9
INI
2
4
12
INIR
2
6
14 (If Br ~ 0)
INIR
2
4
12 (If Br
IND
2
4
12
INDR
2
2
6
4
14 (If Br ~ 0)
12 (If Br = 0)
INO g, (m)
3
4
12
JP f, mn
3
3
2
3
6 (If f is false)
9 (If f is true)
1
3
JP (HL)
= 0)
JP (IX)
2
2
6
JP (IV)
2
2
6
JPmm
3
3
9
JRj
2
4
8
JRC,j
2
2
2
4
6 (If condition is false)
8 (If condition is true)
JR NC,j
2
2
2
4
6 (If condition is false)
8 (If condition is true)
JRZ,j
2
2
2
4
6 (If condition is false)
8 (If condition is true)
JRNZ,j
2
2
2
4
6 (If condition is false)
8 (If condition is true)
LD A, (BC)
2
6
LD A, (DE)
2
6
~HITACHI
854
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Mnemonics
Bytes
Machine Cycles
States
LDA,I
2
2
6
LD A, (mm)
3
4
12
LDA,R
2
2
6
LD (BC), A
1
3
7
LDD
2
4
12
3
7
LD (DE), A
LDww, mn
3
3
9
LD ww, (mn)
4
6
18
LDDR
2
2
6
4
14 (If SCR 0)
12 (If SC R = 0)
LD (HL), m
2
3
9
LD HL, (mn)
3
5
15
LD (HL), 9
1
3
7
LDI
2
4
12
LDI,A
2
2
6
LDIR
2
2
6
4
14 (If BCR 0)
12 (If BCR .. 0)
LDIX,mn
4
4
12
LD IX, (mn)
4
6
18
LD (IX + d), m
4
5
15
LD (IX + d), 9
3
7
15
LD IV. mn
4
4
12
LD IV. (mn)
4
6
18
LD (IY +d), m
4
5
15
LD (IY + d), 9
3
7
15
LD (mn), A
3
5
13
LD (mn), ww
4
7
19
LD (mn), HL
3
6
16
LD (mn), IX
4
7
19
LD (mn), IY
4
7
19
LOR, A
2
2
6
2
6
LD g, (HL)
*
*
_HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
.-
----
855
HD648180W
Mnemonics
Bytes
Machine Cycles
States
LD g, (IX + d)
3
6
14
LD g, (IV + d)
3
6
14
LDg,m
2
2
6
LD g,g'
2
4
LD SP, HL
2
4
LD SP,IX
2
3
7
LD SP,IV
2
3
7
MLTww
2
13
17
NEG
2
2
6
3
NOP
2
6
3
6
14
OR (IV + d)
3
6
14
ORm
2
2
6
2
4
OR (HL)
1
OR(IX+ d)
ORg
OTDM
2
6
14
OTDMR
2
2
8
6
16 (If Br * 0)
14(lfBr=0)
OTDR
2
2
6
4
14 (If Br * 0)
12(lfBr=0)
OTIM
2
6
14
OTIMR
2
2
8
6
16 (If Br* 0)
14 (If Br = 0)
OTIR
2
2
6
4
14(lfBr*0)
12 (If Br = 0)
OUTD
2
4
12
OUTI
2
4
12
OUT (m), A
2
4
10
OUT (C), 9
2
4
10
OUTO (m), 9
3
5
13
POP IX
2
4
12
POP IV
2
4
12
•
856
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Mnemonics
Bytes
Machine Cycles
States
POPzz
1
3
9
PUSH IX
2
6
14
PUSHIY
2
6
14
5
11
PUSH zz
RES b, (HL)
2
5
13
RES b, (IX + d)
4
7
19
RES b, (IY + d)
4
7
19
RES b, 9
2
3
7
RET
3
9
RETf
3
4
5 (If condition is false)
10 (If condition is true)
RETI
2
10 (Z)
4 (R1)
22 (Z)
12 (R1)
RETN
2
4
12
RLA
3
RLCA
3
RLC (HL)
2
5
13
RLC (IX+ d)
4
7
19
RLC (IY + d)
4
7
19
RLCg
2
3
7
RLD
2
8
16
RL (HL)
2
5
13
RL (IX + d)
4
7
19
RL (IY + d)
4
7
19
RLg
2
3
7
RRA
3
RRCA
3
RRC (HL)
2
5
13
RRC (IX + d)
4
7
19
RRC (IY + d)
4
7
19
RRCg
2
3
7
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
857
HD648180W
Mnemonics
Bytes
Machine Cycles
States
RRD
2
8
16
RR (HL)
2
5
13
RR (IX + d)
4
7
19
RR (IV + d)
4
7
19
RRg
2
3
7
RSTv
sac A, (HL)
sac A, (IX + d)
sac A, (IV + d)
sac A, m
sac A, 9
sac HL, ww
3
5
11
2
6
6
14
3
6
14
2
2
6
2
4
6
10
2
3
SCF
1
SET b, (HL)
2
5
13
SET b, (IX + d)
4
7
19
SET b, (IV + d)
4
7
19
SET b, 9
2
3
7
SLA (HL)
2
5
13
SLA (IX + d)
4
7
19
SLA (IV + d)
4
7
19
SLAg
2
3
7
SLP
2
2
8
SRA (HL)
2
5
13
SRA (IX+ d)
4
7
19
SRA (IV + d)
4
7
19
SRAg
2
3
7
SRL (HL)
2
5
13
SRL (IX + d)
4
7
19
SRL (IV + d)
4
7
19
SRLg
2
3
7
2
6
SUB (HL)
~HITACHI
858
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Mnemonics
Bytes
Machine Cycles
States
SUB (IX + d)
3
6
14
SUB (IV + d)
3
6
14
SUB m
2
2
6
2
4
SUBg
TSTIOm
3
4
12
TSTg
2
3
7
TSTm
3
3
9
TST (HL)
2
4
10
XOR (HL)
1
2
6
XOR (IX + d)
3
6
14
XOR (IV + d)
3
6
14
XORm
2
2
6
2
4
XORg
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
859
ex>
~
• Op Code Map
0>
o
0>
~
2:
o
»
First op code
CD
Instruction fonnat: XX
3
:::!.
g
~
r-
s:
•
:J:
BC
~.
2:
..,~"
•
o
g
B
~.
C
~ l:
D
"
-
~~
•
..,
'"
III
:::!.
en
C"
CD
:!:
::r«
M
~
§;
~
cO
<0
•
"E
9
!
g
~
LO
0000
0001
0010
0
1
2
3
(HL)
A
B
C
D
0011
0100
0101
0110
0111
1000
1001
1010
6
7
8
9
A
E
H
L
(HL)
A
1011
1100
1101
1110
1111
B
C
D
E
F
E
~O
~
~
co
......
co
Table 3 Op Code Map (1)
:J:
H
L
4
5
ww(LO=ALL
DE
HL
SP
g (LO= Oto 7)
(HLl
D
H (HLl
B
H
B
D
0000 0001 0010 0011 0100 0101 0110 0111
4
5
6
7
3
1
2
0
;
NOP OJNZ' JRNZ, .JRNC,
LOww,mn
*1
LO(ww),A LO (mn LO(mn
,HL
,A
,
INCww
LOg,s
:
INCg
: *1
OECg
: *1
LOg,m
: * 1 ------Note2------~~H}iLir
-----1----c 1------ ----RLCA RLA OM SCF
EXAF,N'i JR i JR Z, i JR C, i
AOOHL ww
LOA,(ww) LOHL, LOA,
(mn) (mnJ
DECww
LOg,s
INCg
DECo
--------------------.--LDg,m
----------~-~----------RRCA RRA CPL CCF
4
5
6
7
0
1
2
3
L
A
E
A
C
E
C
L
a(LO=8toFl
I
I
I
1000 1001
8
9
1010
A
1011
B
ADD A SUBs ANDs ORs
,s
*2
*2
*2
*2
ADCA SBCA XORs CP s
,5
,5
-----
-----
__~t_
-----
8
9
A
B
-~-~- __*_t
-~-~-
LO = 0 to 7
DE
AF
HL
NC
PO
P
10H 20H 30H
1101 1110 1111
D
E
F
RET!
POPzz
JP!, mn
JPmn OUT(m EX(SP 01
,A
,HL
CALL I, mn
PUSH zz
AOOA,~ SUB m AND m OR m
RSTv
RET I
RET EXX JP (HL LO SP,
HL
JPI, mn
Table 2 IN A, (mIExocHJ EI
CALL I,mn
CALLrm * 3 Table 3 *3
AOCA,~8CA,~XORm CPm
RSTv
C
D
E
F
C
PE
M
Z
08H 18H 28H 38H
. _ J_P......8toF
BC
NZ
OOH
1100
C
zz
I
v
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
v
I
;;!;
~
='~
3CD
Notes: 1. g is replaced by (HL).
::0.
2. s is replaced by (HL).
c:
3. Appending DD to the beginning of an op code (DD XX) in an instruction that has HL or (HL) in its operand produces the
same operation as the original format with the following replacements:
n
.?'
r-
•
HL replaced by IX
~='-
(HL) replaced by (IX + d)
~
Example:
8'"
o
22H ; LD (mn). HL ~ DDH 22H ; LD (mn), IX
-0
•
~.
Similarly. appending FD to the beginning of an op code (FD XX) in an instruction that has HL or (HL) in its operand
produces the same operation as the original format with the following replacements:
~~
HL replaced by IV
~-0 :I
_
~(')
(HL) replaced by (IV + d)
•
Example:
g}
34H ; INC (HL) ~ FDH 34H ; INC (IV + d)
~ ::I
CXl
::0.
~
CD
§;
....
~
CD
An exception is the JP (HL) instruction (E9H). Appending DDH or FDH to the beginning replaces (HL) with (IX) or (IV).
If DDH or FDH is appended to the EX DE, HL instruction (EBH). an undefined instruction results. without replacement of
HL.
~
.
~
::I:
g
=»
00
.....
Second op code
Instruction fonnat: CB XX
00
~
~
:::>.
n
b (lO=O to 7)
4
~
~
•
::I:
~
B
::2
C
=-
&l
•
§
0
E
N
w..:r:
~
a~
~
l":r:
~
~
""tic)
•
!XI
:::>.
~
~
!D
~
~~
co
•
~
s
I
H
H
L
(HL)
A
B
C
0
C)
E
H
L
.(HL)
A
lO
~
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000 0001
0
1
0010
2
0011
3
0
2
0100 0101
4
5
4
6
0110 0111
6
7
0
2
1000 1001
a
9
1010
A
6
1011
B
0
2
1100 1101
C
0
4
6
1110 1111
E
F
0
1
---?-
---t-
~
2
3
4 RlCg Rlg SLAg
5
6 * 1 * 1 -;'T
BlTb,g
7
a
9
RESb,g
r-L-
SETb,g
r--45
----------------------------------·1----------- -----------------------*1
*1
I 6
------------------------ ----------------------------------------------7
.
a
I
!
r-g---
~
~
A
B
C RRCg RRg SRAg SRlg
0
E -Not8- -NO~- Note- Note-
F
0
1
2
3
BITb,g
RESb,g
+
~
SETb,g
----------Note---------- ----------~---------- ----------tiOte---------- ~
------------------------ ------------------------ ------------------------ ~
F
4
1
5
3
6
5
7
7
a
1
9
A
3
5
b(lO.ato A
B
7
C
0
E
F
1
3
5
7
-------
- - -
Note: H DOH is appended to the beginning of the op code, the instruction is executed by the op code DO CB d XX, replacing (HL)
with (IX + d). Similarly, if FDH is appended to the beginning of the op code, the instruction is executed by the op code FD CB
d XX, replacing (HL) with (IY + d).
Table 5 Op Code Map (3)
::z::
;:::;:
~
:r.
Second op code
Instruction fonnat: ED XX
»
3
~
o·
!"
!:
•
~
So
:r.
"""C
~
'"•
§
~~
~ :t
N
"""C
_
~~
"""c(')
~:!:
•
0:>
::l.
W
o
o
(lO=All)
DE
Hl
SP
WW
?-
lO
~
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
B
0
H
0000
0
0001
1
0010
2
3
4
5
6
7
8
9
A
B
C
0
E
F
0
C
0011
0100
0
0101
5
H
0110 0111
1000 11001
7
8 T 9
6
INo,IC)
OUT(C),g
SBCHl,ww
lO(mn),ww
OTIMToTIMR
TSTg
lSf(Hl] NEG
TSTMhsrorr
RETN
IMO 1M 1
ISLPl
LDI,A lOA, I RRO
INOg,(m)
INg,(C)
OUTO(m),g
OUT Cl,o
AOCHl,ww
LDww,lmn}
OTDMIOTDMA
TSTg
MlTww
RETI
1M2
lOR,A LDA,R RlO
1
8
9
2
7
3
5
6
4
E
l
A
C
E
l
A
9 (lO=810 F)
2
INOg,(m)
OUTO(m),g
0
1
BC
g (LO=Oto 7)
B
3
4
T
1010
1011
A
B
lOI lOIR
CPI CPIR
INI
INIR
OUTI OTIR
1100 11101 11110 11111
C[ DIE 1 F
~
1
~
~I
~
~
6
i---'--
lOO
CPO
INO
QUTO
'--71
8
9!
lOOR
CPOR
INOR
OTDR
!
~
~
Ih
~
--4-,
A
B
cTOIEIF
-f-1
::r:
tJ
(j)
~
(Xl
~
(Xl
00
O"l
W
o
~
HD648180W
• Bus Cycle Conditions
A hyphen in the Address column indicates that address output is undefined. A "z" in the Data
column indicates that the data pin is at high impedance.
Instruction
Machine
Cycle
States
ADDHL, ww
MC1
T1T2T3
MC2 to
MC3
lililili
MC1
T1T2T3
1st op-code
address
MC2
T1T2T3
MC3 to
MCa
liliTiTi
MC1
T1T2T3
1st op-code
address
MC2
T1T2T3
MC3 to
MCa
lililiTi
MC1
T1T2 T3
MC2
li
MC 1
T1T2 T3
1st op-code
address
MC2
T1T2 T3
ADDIX,ww
ADD IY, yy
ADCHL,
SBCHL,
ww
ww
ADDA, 9
ADCA, 9
SUBg
SBCA, 9
ANDg
ORg
XORg
CPg
ADD A, m
ADCA, m
SUBm
SBCA, m
ANDm
ORm
XORm
CPm
Address
Data
RD WR ME IOE LlR HALT ST
1st op-code
address
1st
op-code
0
0
0
0
1st
op-code
0
0
0
0
2nd op-code 2nd
address
op-code
0
0
0
1st
op-code
0
0
0
2nd op-code 2nd
address
op-code
0
0
0
0
0
0
0
1st
op-code
0
0
0
0
2nd operand 2nd
address
op-code
0
0
Z
Z
Z
1st op-code
address
1st
op-code
Z
$
864
0
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Instruction
Machine
States
Cycle
Address
Data
RD WR ME IOE L1R HALT ST
ADD A, (HL)
ADC A, (Hl)
SUB (HL)
SBC A, (HL)
AND (HL)
OR (HL)
XOR (HL)
CP (HL)
MC,
T,T2T3
1st op-code
address
1st
op-code
0
0
MC2
T,T2T3
HL
Data
0
0
ADD A, (IX + d)
ADD A, (IV + d)
ADC A, (IX + d)
ADC A, (IV + d)
SUB (IX + d)
SUB (IV + d)
SBC A, (IX + d)
SBC A, (IV + d)
AND (IX + d)
AND (IV + d)
OR (IX + d)
OR (IV + d)
XOR (IX + d)
XOR (IV + d)
CP (IX + d)
CP (IV + d)
MC,
T,T2T3
1st op-code
address
1st
op-code
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
MC3
T1T2T3
1st operand
address
MC4 to
MCs
lili
MC6
T,T2T3
IX+d
IV+d
MC,
T1T2T3
1st op-code
address
MC2
BITb,g
BIT b, (HL)
0
0
0
0
0
0
0
0
0
0
Data
0
0
1st
op-code
0
0
0
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC,
T,T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T,T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T,T2T3
HL
0
0
d
Z
Data
•
0
0
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
865
HD648180W
Instruction
Machine
Cycle
States
Address
Data
RD WR ME IOE LlR HALT ST
MC l
T1T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T 3
1st operand
address
d
0
0
MC4
T1T2T3
3rd op-code
address
3rd
op-code
0
0
MCs
T1T2T3
IX+d
IV+d
Data
0
0
MC l
T1T2T3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T3
1st operand
address
n
0
0
MC3
T1T2T3
2nd operand m
address
0
0
MC4
Ti
MCs
T1T2 T3
SP-1
PCH
MC6
T1T2 T3
SP-2
PCl
CAll f. mn
(H condition
is false)
MC l
T1T2T3
1st op-code
address
MC2
T1T2T3
CAll f. mn
(H condition
is false)
MC l
BIT b. (IX + d)
BIT b. (IV + d)
CAll mn
0
0
0
0
0
0
0
Z
0
0
1
0
0
1st
op-code
0
1
0
1st operand
address
n
0
0
T1T2T3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T3
1st operand
address
n
0
0
MC3
T1T2T3
2nd operand m
address
0
0
MC4
Ti
MCs
T1T2T3
SP-1
PCH
0
0
MC6
T1T2T3
SP-2
PCl
0
0
Z
•
866
0
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Instruction
Machine
Cycle
States
CCF
MC1
CPI
CPO
Address
Data
RD WR ME IOE L1R HALT ST
T1T2 T3
1st op-code
address
1st
op-code
0
0
0
0
MC 1
T1T2T 3
1st op-code
address
1st
op-code
0
0
0
0
MC2
T1T2T 3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T 3
HL
Data
0
0
MC4 to
MC6
TiTiTi
Z
1
1
MC1
T1T2T 3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2 T 3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T 3
HL
Data
0
0
MC4 to
MCa
TiTiTiTiTi -
Z
1
MC 1
T1T2T 3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T 3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T 3
HL
0
0
MC4 to
MC6
TiTiTiTiTi -
CPL
MC 1
T1T2 T3
1st op-code
address
1st
op-code
0
0
0
0
DAA
MC 1
T1T2 T3
1st op-code
address
1st
op-code
0
0
0
0
MC2
Ti
MC 1
T1T2T 3
0
0
0
0
CPIR
CPDR
(If BCR *- 0 and
Ar*- (HLlMl
CPIR
CPDR
(If BCR = 0 or
Ar = (HLlMl
DINole
Data
0
0
Z
Z
1st op-code
address
1st
op-code
Note: Interrupts are not detected at the end of the 01 instruction.
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
867
HD648180W
Instruction
DJNZj
(If Br"* 0)
Machine
Cycle
States
Address
Data
RD WR ME IOE LlR HALT ST
1st op-code
address
1st
op-code
0
0
0
0
0
0
MC l
T1T2Ta
MC2
li*l
MCa
T1T2Ta
MC4 to
MCs
lili
MC l
T1T2Ta
MC2
li'l
MCa
T1T2Ta
1st operand
address
j-2
0
0
EI*2
MC l
T1T2Ta
1st op-code
address
1st
op-code
0
EX DE, HL
EXX
MC l
T1T2Ta
1st op-code
address
1st
op-code
EX AF, AF'
MC l
T1T2Ta
1st op-code
address
1st
op-code
MC2
li
MC l
T1T2Ta
1st op-code
address
MC2
T1T2Ta
MCa
T1T2 Ta
MC4
li
MCs
T1T2Ta
SP + 1
H
0
0
MCs
T1T2Ta
SP
L
0
0
DJNZj
(If Br = 0)
EX (SP), HL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1st
op-code
0
0
0
0
SP
Data
0
0
SP + 1
Data
0
0
Z
1st operand
address
j-2
Z
1st op-code
address
1st
op-code
Z
Z
Z
Notes: 1. Immediately after this state, DMA, refresh, and bus release cannot be executed. Any
such requests are ignored.
2. Interrupts are not detected at the end of the EI instruction.
$
868
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Instruction
EX (SP), IX
EX (SP), IY
HALT
Machine
Cycle
States
Address
Data
RD WR ME IOE L1R HALT ST
MC,
T,T2T 3
1st op-code
address
1st
op-code
0
0
0
MC2
T,T2T 3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T,T2 T3
SP
Data
0
0
MC 4
T,T 2T 3
SP + 1
Data
0
0
MCs
Ti
MC6
T1T2 T3
SP + 1
IXH
IYH
0
0
MC7
T1T2 T3
SP
IXL
IYL
0
0
MC,
T,T2 T 3
1st op-code
address
1st
op-code
0
0
0
Next op-code Next
address
op-code
0
0
0
0
Z
0
0
0
IMO
1M 1
1M2
MC,
T,T 2T 3
1st op-code
address
1st
op-code
0
0
0
MC2
T,T2T 3
2nd op-code 2nd
address
op-code
0
0
0
INCg
DECg
MC,
T1T2 T3
1st op-code
address
0
0
0
0
MC 2
Ti
MC,
T1T2 T 3
1st op-code
address
1st
op-code
0
0
0
0
MC 2
T,T2T 3
HL
Data
0
0
MC3
Ti
Data
0
INC (HL)
DEC (HL)
INC (IX + d)
INC (IV + d)
DEC (IX + d)
DEC (IV + d)
1st
op-code
0
Z
Z
MC 4
T1T2 T 3
HL
MC,
T,T 2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T,T2 T 3
2nd op-code 2nd
address
op-code
0
0
0
MC3
Ti
1st operand
address
0
0
d
@HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
869
HD648180W
Instruction
INC (IX + d)
INC (IV + d)
DEC (IX + d)
DEC (IV + d)
INCww
DECww
INC IX
INC IV
DEC IX
INCIV
IN A, (m)
IN g, (C)
INO g, (m)
Machine
Cycle
States
Address
Data
RD WR ME IOE LlR HALT ST
Z
MC4 to
MC5
TiTi
MC6
T1T2T3
MC7
Ti
MCa
T1T2T3
IX+d
IV+d
Data
MC1
T1T2T3
1st op-code
address
1st
op-code
MC2
Ti
MC 1
T1T2T3
1st op-code
address
MC2
T1T2T3
MC3
Ti
MC 1
T1T2T3
1st op-code
address
MC2
T1T2T3
MC3
IX+d
IV+ d
Data
0
0
Z
0
0
0
0
0
0
1st
op-code
0
0
0
0
2nd op-code 2nd
address
op-code
0
0
0
1st
op-code
0
0
0
0
1st operand
address
m
0
0
T1T2T3
m to Ao-A7
Ato Aa-A15
Data
0
MC1
T1T2T3
1st op-code
address
1st
op-code
0
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
BC
Data
0
MC 1
T1T2T3
T1T2T3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
MC3
T1T2T3
1st operand
address
m
0
0
MC4
T1T2T3
m to Ao-A7
OOH to
Data
0
Z
Z
0
0
1
0
0
0
Aa-A15
~HITACHI
870
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
0
HD648180W
Instruction
INI
IND
Machine
Cycle
States
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T3 BC
T1T2T3 HL
T1T2T3 1st op-code
MC1
0
Data
0
0
0
0
0
2nd op-code 2nd
op-code
address
0
0
0
T1T2T3
MC3
T1T2T3 BC
T1T2T3 HL
Data
0
Data
1
MCs to
MC6
lili
Z
MC 1
T1T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
op-code
address
0
0
0
MC3
T1T2T3 BC
T1T2T3 HL
T1T2T3 1st op-code
address
Data
0
0
0
0
0
Data
0
0
MC2
MC1
JP f, mn
(If f is false)
Data
1st
op-code
address
MC4
JP mn
RD WR ME IOE LlR HALT ST
T1T2T3
MC4
INIR
INDR
(lfBr=O)
Data
MC1
MC4
INIR
INDR
(If Br* 0)
Address
1
0
0
0
0
1st
op-code
0
0
MC2
T1T2T3
1st operand
address
n
0
0
MC3
T1T2T3
2nd operand m
address
0
0
MC 1
T1T2T3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T3
1st operand
address
n
0
0
0
0
0
0
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
871
HD648180W
Instruction
Machine
States
Cycle
Address
Data
RD WR ME IOE LlR HALT ST
0
0
0
0
0
0
0
0
0
2nd op-code 2nd
op-code
address
0
0
0
T1T2T3
1st op-code
address
1st
op-code
0
0
0
0
MC2
T1T2 T3
1st operand
address
j-2
0
0
MC3 to
MC4
TiTi
0
0
0
0
0
0
MC1
T1T2T3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T3
1st operand
address
n
0
0
MC3
T1T2 T3
2nd operand m
address
0
JP (HL)
MC1
T1T2T 3
1st op-code
address
1st
op-code
0
JP (IX)
JP (IY)
MC 1
T1T2T 3
1st op-code
address
1st
op-code
MC2
T1T2T 3
MC1
JP f, mn
(If is true)
JRj
JR C, j JR NC, j MC 1
JR Z, j JR NZ, j
(If condition
MC2
is false)
JR C, j JR NC, j MC 1
JR Z, j JR NZ, j
(If condition
MC2
is true)
LD g,g'
LDg,m
LD g, (HL)
Z
T1T2T 3
1st op-code
address
1st
op-code
0
0
T1T2T 3
1st operand
address
j-2
0
0
T1T2T3
1st op-code
address
1st
op-code
0
0
T1T2T 3
1st operand
address
j-2
0
0
0
0
MC3 to
MC4
TiTi
MC 1
T1T2 T3
MC2
Ti
MC 1
T1T2 T3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T 3
1st operand
address
m
0
0
MC 1
T1T2T 3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T 3
HL
Data
0
0
Z
1st op-code
address
1st
op-code
1
Z
0
0
0
0
.HITACHI
872
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Machine
Cycle
States
Instruction
LD g. (IX + d)
LD g. (IV + d)
LD (HL). 9
LD (HL).
m
m
m
LD (IX + d).
LD (IV + d).
Data
RD WR ME IOE LlR HALT ST
MC,
T,T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T,T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T,T2T3
1st operand
address
0
0
MC4 to
MCs
lili
MCs
T,T2T3
IX+d
IV+d
Data
0
0
MC,
T,T2T3
1st op-code
address
1st
op-code
0
0
MC2
MC,
li
T,T2T3
T,T2T3
MC2
MC3
LD (IX + d). 9
LD (IV + d). 9
Address
d
0
Z
0
0
0
Z
0
0
HL
9
1st op-code
address
1st
op-code
0
0
0
T,T2T3
2nd op-code 2nd
op-code
address
0
0
0
MC3
T,T2T3
1st operand
address
0
0
MC4 to
MC6
liliTi
MC7
T,T2T3
IX+d
IV +d
9
MC,
T,T2T3
1st op-code
address
1st
op-code
0
0
MC2
T,T2T3
1st operand
address
m
0
0
MC3
HL
Data
MC,
T,T2T3
T,T2T3
1st op-code
address
1st
op-code
0
MC2
T,T2T3
2nd op-code 2nd
address
op-code
MC3
T,T2T3
1st operand
address
MC4
T,T2T3
MCs
T,T2T3
d
Z
0
0
0
0
0
0
0
1
0
0
0
0
0
d
0
0
2nd operand
address
m
0
0
IX+d
IV+d
Data
0
0
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
----
~
-~
873
HD648180W
Instruction
Machine
Cycle
States
LD A, (Be)
LD A, (DE)
T1T2T3
Address
Data
1st op-code
address
1st
op-code
o
0
o
o
o
o
o
o
o
o
o
o
LD A, (mn)
T 1T2T31st op-code
address
1st
op-code
0
o
T 1T2T31st operand
address
n
o
o
o
o
0
o
T1T2T3
2ndoperand m
address
Data
1st op-code
address
LD (Be), A
LD (DE), A
z
li
Me3
LD (mn), A
Me3
1st
op-code
o
A
T 1T2T31st op-code
address
1st
op-code
0
o
T 1T2T31st operand
address
n
o
o
T1 T2T3
m
o
o
2nd op-code
address
z
li
o
A
LD
LD
LD
LD
A. INote
A, RNote
I,A
T1T2T3
LD WW, mn
Me3
0
1st
op-code
0
o
o
2ndop-code 2nd
address
op-code
0
o
o
o
T 1T2T31st op-code
address
R,A
0
T 1T2T31st op-code
address
1st
op-code
0
o
T 1T2T31st operand
address
n
o
o
2ndop-code m
address
o
o
T1T2T3
Note: Interrutps are not detected at the end of the LD A, lor LD A, R instruction .
•
874
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
o
HD648180W
Machine
Cycle
States
Instruction
LDIX,mn
LD IY, mn
LD HL, (mn)
RD WR ME IOE LlR HALT ST
1st
op-code
0
0
0
0
T1T2T3
1st op-code
address
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
MC3
T1T2T3
1st operand
address
n
0
0
MC4
T1T2T3
2nd operand m
address
0
0
MC1
T1T2T3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T3
1st operand
address
n
0
0
MC3
T1T2T3
2nd operand m
address
0
0
MC4
mn
Data
0
0
mn+1
Data
0
0
MC 1
T1T2T3
T1T2T3
T1T2T3
1st op-code
address
1st
op-code
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
MC3
T1T2T3
1st operand
address
MC4
MCs
0
0
0
0
0
0
0
n
0
0
T1T2T3
2nd operand m
address
0
0
mn
Data
0
0
mn+1
Data
0
0
MC 1
T1T2T3
T1T2T3
T1T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T3
1st operand
address
n
0
0
MC4
T1T2T3
2nd operand m
address
0
0
MCs
T1T2T3
T1T2T3
mn
Data
0
0
mn+1
Data
0
0
MC6
•
------
0
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
-- - -
0
0
MC6
LD IX, (mn)
LD IY, (mn)
Data
MC 1
MC s
LD WW, (mn)
Address
875
HD648180W
Instruction
Machine
Cycle
States
LD (mn), HL
MC 1
LD (mn), ww
LD (mn), IX
LD (mn), IY
Address
Data
RD WR ME IOE LlR HALT ST
T1T2T3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T3
1st operand
address
n
0
0
MC3
T1T2T3
2nd operand m
address
0
0
MC4
MCs
MCs
MC 1
Ti
T1T2T3
T1T2T3
T1T2T3
MC2
0
0
0
Z
mn
L
0
0
mn+1
H
0
0
1st op-code
address
1st
op-code
0
0
0
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T3
1st operand
address
n
0
0
MC 4
T1T2T3
2nd operand m
address
0
0
MCs
MCs
MC7
MC1
Ti
T1T2T3
T1T2T3
T1T2T3
MC2
Z
mn
wwL
0
0
mn+1
wwH
0
0
1st op-code
address
1st
op-code
0
1
0
0
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T3
1st operand
address
n
0
0
MC 4
T1T2T3
2nd operand m
address
0
0
MCs
MCs
Ti
T1T2T3
mn
IXL
IYL
0
0
MC 7
T1T2T3
mn+1
IXH
IYH
0
0
Z
@HITACHI
876
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
0
HD648180W
Instruction
Machine
Cycle
States
LD SP, HL
MC 1
T1T2T 3
MC2
li
MC1
T1T2 T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T 3
2nd op-code 2nd
address
op-code
0
0
0
MC3
li
MC1
T1T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T 3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2 T3
HL
Data
0
0
MC4
T1T2T3
DE
Data
1
MC1
T1T2T 3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T 3
HL
Data
0
0
MC4
T1T2 T 3
DE
Data
0
MCsto
MC6
lili
Z
1
MC 1
T1T2 T 3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T 3
HL
Data
0
0
MC4
T1T2 T 3
DE
Data
MC 1
T1T2T 3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2 T3
2nd op-code 2nd
address
op-code
0
0
0
MC3 to
MC 13
liliTiTi
liliTiTi
liliTi
LD SP,IX
LD SP,IY
LDI
LDD
LDIR
LDDR
(If SCR
'* 0)
LDIR
LDDR
(If SCR = 0)
MLTww
Address
Data
RD WR ME IOE L1R HALT ST
1st op-code
address
1st
op-code
0
0
Z
0
0
0
0
Z
0
0
0
0
0
0
0
0
0
Z
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
877
HD648180W
Instruction
Machine
Cycle
States
NEG
MC 1
Address
Data
RD WR ME IOE LlR HALT ST
Tj T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
Nap
MC1
T1T2T3
1st op-code
address
1st
op-code
0
0
0
0
OUT (m). A
MC1
T1T2T3
1st op-code
address
1st
op-code
0
0
0
0
MC2
T1T2T3
1st operand
address
m
0
0
MC3
li
MC4
T1T2T3
A
m to Ao-A7
Ato Aa-A15
MC1
T1T2T3
1st op-code
address
1st
op-code
0
0
0
0
MC2
T1T2T3
2nd op-code 2nd
op-code
address
0
0
0
MC3
li
MC4
MC 1
T1T2T3
T1T2T3
MC2
OUT (C). 9
aUTO (m). 9
Z
0
0
Z
BC
9
1st op-code
address
1st
op-code
0
T1T2T3
2nd op-code 2nd
address
op-code
MC3
T1T2T3
1st operand
address
MC4
li
MC5
T1T2T3
m
0
1
0
0
0
0
0
0
0
0
Z
Ao-A7
OOH to
Aa-A15
m to
9
0
0
OHITACHI
878
0
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
0
HD648180W
Instruction
OTiM
OTOM
OTiMR
OTOMR
(lfBr*O)
OTIMR
OTOMR
(lfBr=O)
Machine
Cycle
States
Address
Data
RD WR ME IOE LlR HALT ST
MC1
T1T2 T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
Ti
MC4
T1T2T3
HL
Data
0
0
MCs
T1T2T3
C to Ao-A7
OOH to
Aa-A 1s
Data
MCs
Ti
MC 1
T1T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
op-code
address
0
0
0
MC3
Ti
MC4
T1T2 T3
HL
Data
0
0
MCs
T1T2T3
Cto Ao-A7
OOH to
Aa-A1s
Data
MCs to
MCa
TiTiTi
MC1
T1T2 T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2 T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
Ti
0
0
MC4
0
Z
0
0
Z
0
Z
0
0
Z
0
Z
T1T2 T3
HL
Data
MCs
T1T2T3
C to Ao-A7
OOH to
Aa-A1s
Data
MCsto
Ti
0
0
Z
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
879
HD648180W
Instruction
OUTI
OUTD
OTIR
OTDR
(If Br*O)
OTIR
OTDR
(If Br = 0)
POPzz
POP IX
POPIY
Machine
Cycle
States
Address
Data
RD WR ME IOE LlR HALT ST
MC1
T1T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T 3
2nd op-code 2nd
address
op-code
0
0
0
MC3
0
T1T2T 3
HL
Data
0
MC4
T1T2T 3
BC
Data
1
MC1
T1T2T3
1st op-code
address
1st
op-code
MC2
T1T2T3
MC3
1
1
0
0
0
1
2nd op-code 2nd
address
op-code
0
0
T1T2T3
HL
Data
0
0
MC4
T1T2T3
BC
Data
1
MCsto
MC6
TiTi
MC1
T1T2 T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T3
HL
Data
0
0
MC4
T1T2T3
BC
Data
MC l
T1T2 T3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T3
SP
Data
0
0
MCa
T1T2T3
SP + 1
Data
0
0
MC 1
T1T2T3
1st op-code
address
1st
op-code
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
Me3
T1T2T3
SP
MC4
T1T2 T3
SP + 1
Z
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Data
0
0
Data
0
0
~HITACHI
880
0
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Instruction
Machine
Cycle
States
PUSH zz
MC 1
T1T2T 3
MC2 to
MC3
TiTi
MC4
T1T2T 3
SP-1
zzH
0
0
T1T2T 3
SP-1
zzL
0
0
1
MC 1
T1T2T 3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2 T 3
2nd op-code 2nd
address
op-code
0
0
0
MC3 to
MC4
TiTi
MCs
T1T2 T 3
SP -1
IXH
IYH
0
0
MCa
T1T2T 3
SP-2
IXL
IYL
0
0
MC 1
T1T2T 3
1st op-code
address
1st
op-code
0
0
MC2
T1T2T 3
SP
Data
0
0
MC3
MCs
PUSH IX
PUSHIY
RET
Address
Data
RD WR ME IOE L1R HALT ST
1st op-code
address
1st
op-code
0
0
0
0
Z
0
Z
0
0
T1T2 T 3
SP + 2
Data
0
0
RETf
(If condition
is false)
MC1
T1T2 T3
1st op-code
address
1st
op-code
0
0
0
0
MC2 to
MC3
TiTi
RETf
(If condition
is true)
MC 1
T1T2T 3
0
0
0
0
MC2
Ti
MC3
T1T2T 3
SP
Data
0
0
MC4
T1T2T 3
SP + 1
Data
0
0
Z
1st op-code
address
1st
op-code
Z
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
881
HD648180W
Instruction
RETI (R1)
RETN
Machine
Cycle
States
MC1
Address
T1T2T3 1st op-code
address
MC2
MC4
RETI (Z)
MC1
T1T2T3 SP
T1T2T3 SP+ 1
T1T2T3 1st op-code
0
0
0
0
0
0
Data
0
0
Data
0
0
1st
op-code
0
0
0
0
1
1
1Note
1
1
MC3 to
MCs
TiTiTi
MCs
T1T2T3
0
oNote
1
op-code
Z
1st op-code
address
1st
op-code
MC7
Ti
MCa
T1T2T3 2nd op-code 2nd
op-code
0
1
1
ONote
0
0
0
1
1Note
1
1
Z
address
1
oNote
T1T2T3 2nd op-code 2nd
address
ONote
0
0
0
1
MCg
T1T2T3 SP
Data
0
0
1Note
1
1
MC10
T1T2T3 SP+ 1
T1T2T3 1st op-code
Data
0
0
1Note
1
1
1st
op-code
0
0
0
0
1st
op-code
0
0
0
0
0
0
RLCA
RLA
RRCA
RRA
MC1
RLCg
RLg
RRCg
RRg
SLAg
SRAg
SRLg
MC1
address
T1T2T3 1st op-code
address
MC2
T1T2T3 2nd op-code 2nd
address
MC3
Ti
1
0
op-code
Z
Note: Upper value is LlR status when LIRE
•
882
1st
op-code
op-code
address
MC2
RD WR ME IOE LlR HALT ST
T1T2T3 2nd op-code 2nd
address
MC3
Data
= 1.
Lower value is LlR status when LIRE - O•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Instruction
RLC (HL)
RL (HL)
RRC (HL)
RR (HL)
SLA (HL)
SRA (HL)
SRL (HL)
Machine
Cycle
States
RLD
RRD
Data
RD WR ME IOE LlR HALT ST
MC l
T1T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
HL
Data
0
0
Z
1
1
MC l
T1T2T3
li
T1T2T3
T1T2T3
MC2
MC4
MCs
RLC (IX + d)
RLC (IV + d)
RL (IX + d)
RL (IV + d)
RRC (IX + d)
RRC (IV + d)
RR (IX + d)
RR (IV + d)
SLA (IX + d)
SLA (IV + d)
SRA (IX + d)
SRA (IV + d)
SRL (IX + d)
SRL (IV + d)
Address
HL
Data
1st op-code
address
1st
op-code
0
0
0
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T3
1st operand
address
d
0
0
MC4
T1T2T3
3rd op-code
address
3rd
op-code
0
0
MCs
T1T2T3
IX+d
IV + d
Data
0
0
MC6
MC7
li
T1T2T3
MC l
0
0
Z
Data
T1T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T3
liliTiTi
HL
0
0
T1T2T3
HL
MCa
0
0
IX+d
IV +d
MC4 to
MC7
0
Data
0
0
0
Z
Data
0
0
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
883
HD648180W
Instruction
Machine
States
Cycle
RSTv
MC1
T1T2T3
MC2 to
MC3
TiTi
MC4
T1T2T3
SP-1
PCH
0
0
MCs
T1T2T3
SP-2
PCl
0
0
SCF
MC1
T1T2T3
1st op-code
address
1st
op-code
0
SET b, 9
RES b, 9
MC1
T1T2T3
1st op-code
address
1st
op-code
MC2
T1T2 T3
2nd op-code 2nd
address
op-code
MC3
Ti
MC1
T1T2T3
1st op-code
address
MC2
SET b, (Hl)
RES b, (Hl)
SET b, (IX + d)
SET b, (IV + d)
RES b, (IX + d)
RES b, (IV + d)
Address
Data
RD WR ME IOE L1R HALT ST
1st op-code
address
1st
op-code
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1st
op-code
0
0
0
T1T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T3
Hl
0
0
MC4
Ti
MCs
T1T2T3
Hl
Data
MC1
T1T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T1T2T 3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T1T2T3
1st operand
address
d
0
0
MC4
T1T2T3
3rd op-code
address
3rd
op-code
0
0
MCs
T1T2T3
IX+d
IV+d
Data
0
0
MC6
Ti
MC7
T1T2T3
Z
Z
Data
Z
0
0
0
Z
IX+d
IV+d
Data
0
0
~HITACHI
884
0
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
0
HD648180W
Instruction
Machine
Cycle
States
SLP
MC,
MC2
TSTIOm
Address
Data
RD WR ME IOE LIR HALT ST
T,T2T3
1st op-code
address
1st
op-code
0
0
0
T,T2T3
2nd op-code 2nd
address
op-code
0
0
0
FFFFFH
Z
0
0
MC,
T,T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T,T2T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
T,T2T3
1st operand
address
m
0
0
MC4
T,T2T3
C to Ao-A7
OOH to
Data
0
0
Aa-A15
T5Tg
TSTm
TST (HL)
MC,
T,T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T,T2 T3
2nd op-code 2nd
address
op-code
0
0
0
MC3
Ti
MC,
T,T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T,T2T3
2nd op-code 2nd
address.
op-code
0
0
0
MC3
T,T2T3
1st operand
address
m
MC,
T,T2T3
1st op-code
address
1st
op-code
0
0
0
MC2
T,T2T3
2nd op-code 2nd
op-code
address
0
0
0
MC3
Ti
MC4
T,T2T3
0
0
0
Z
0
0
Z
HL
Data
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
885
HD648180W
Instruction
Machine
Cycle
States
NMI
MC1
T1T2T3
MC2 to
MC3
TiTi
MC4
T1T2T3
SP-1
PCH
0
0
MCs
T1T2T3
SP-2
PCl
0
0
MC1
T1T2T W Next op-code 1st
address (PC) op-code
TWT3
MC2 to
MC3
TiTi
MC4
T1T2T3
SP-1
PCH
0
0
MCs
T1T2T3
SP-2
PCl
0
0
T1T2Tw
TWT3
Next op-code 1st
address (PC) op-code
1
1
MC2
T1T2 T3
PC
n
0
0
MC3
T1T2T3
PC+ 1
m
0
0
MC4
Ti
Z
1
MCs
T1T2T3
SP-1
PC + 2 (H) 1
0
0
MCs
T1T2T3
SP-2
PC + 2 (L) 1
0
0
MC 1
T1T2 T W Next op-code
address (PC)
TWT3
1
1
MC2
T1T2T3
SP- 1
PCH
0
0
MC3
T1T2T3
SP + 2
PCl
0
0
MC 1
T1T2Tw
TWT3
Next op-code vector
address (PC)
MC2
Ti
MC3
T1T2T3
SP-1
PCH
0
0
MC4
T1T2T3
SP-2
PCl
0
0
MCs
T1T2T3
I, vector
Data
0
0
MCs
T1T2T 3
I, vector + 1
Data
0
0
iNTO mode 0
(RST inserted)
INTo mode 0
MC 1
(CALL inserted)
INTo mode 1
INTo mode 2
Address
RD WR ME IOE LlR HALT ST
0
Next op-code
address (PC)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Z
1
Z
Z
•
886
Data
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Instruction
INT1•
INT2•
internal
interrupts
Machine
States
Cycle
Address
Data
RD WR ME IOE L1R HALT ST
MC l
T1T2TW Next op-code
address (PC)
TWT3
MC2
1i
MC3
T1 T2T3.
SP-1
PCH
T1T2T3
SP-2
PCl
T1T2T3
I. vector
Data
0
I. vector + 1
Data
0
MC4
MCs
MC6
T1T2T3
0
Z
0
0
0
0
1
0
0
_HITACHI
Hitachi America, Ltd .• Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
887
HD648180W
• Acceptable Requests in Each Mode
Current Status
Action
Request
Normal Mode
(CPU Mode)
Walt
(IOSTOP Mode) State
WAIT
Accepted
Accepted Not
accepted
Accepted
Accepted Not
accepted
Not
Not
accepted accepted
Refresh
request
(request
for
insertion
of refresh
cycle by
on-chip
refresh
circuit)
Refresh cycle
inserted at
machine cycle
break
Not
Not
accepted accepted
Refresh
cycle
inserted at
machine
cycle break
Refresh
Not
cycle
accepted
inserted at
machine
cycle break
Not
Not
accepted accepted
lJI1EQQ
DMAcycle
inserted at
machine cycle
break
Accepted, Accepted
DMA cycle
but OMA * Followinserted at
cycle not
ing
machine
inserted
completion cycle break
until
of refresh
machine
cycle, 1
cycle
machine
break
cycle is
executed
and then
OMAcycie
is inserted.
Accepted Accepted
Not
Not
(Consult * Following accepted accepted
completion
this
manual
of bus
for full
release
details.)
cycle, 1
machine
cycle is
executed
and then
OMAcycie
is inserted.
Not
Not
accepted accepted
Bus
Bus
release
release
mode
mode
entered at continues
machine
cycle break
0Rrn1
SOSREQ Bus
release
mode entered
at machine
cycle break
Note:
*
Refresh
Cycle
Interrupt
AcknowlDMA
edge Cycle Cycle
Bus
release
mode
entered at
machine
cycle break
Bus
Release
Mode
Sleep
Mode
Standby
Mode
Accepted Accepted
Not accepted when DREQo and OREQ1 are set for level detection.
~HITACHI
888
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819· (415) 589-8300
HD648180W
Current Status
Normal Mode
Walt
Action
(CPU Mode)
Request (IOSTOP Mode) State
aINTo,
Refresh
Cycle
Interrupt
Acknowl· DMA
edge Cycle Cycle
Bus
Release
Mode
Sleep
Mode
Standby
Mode
Accepted in
final machine
cycle of
instruction
Accepted
in final
machine
cycle of
instruction
Not
accepted
Not
accepted
Not
accepted
Not
accepted
Accepted, Not
sleep
accepted
mode
exited
and
normal
status
recovered
InternalllO
interrupt
request
Accepted in
final machine
cycle of
instruction
Accepted
in final
machine
cycle of
instruction
Not
accepted
Not
accepted
Not
accepted
Not
accepted
Accepted, Not
sleep
accepted
mode
exited
and
normal
status
recovered
NMI
Accepted in
final machine
cycle of
instruction
Accepted
in final
machine
cycle of
instruction
Not
accepted
Not
Accepted, Not
accepted
DMA
accepted
**Accepted suspendin final
ed
machine
cycle of
instruction
following
completion
of acknowledge cycle.
EINT"
~ INT2
Note:
Accepted,
sleep
mode
exited
and
normal
status
recovered
Accepted,
standby
mode
exited
and
normal
status
recovered.
Note
that
10STOP
bit
remains
selto 1.
** Accepted when INTo is being used in mode o. The NMI acknowledge cycle begins following
execution of the instruction placed on the bus .
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
889
HD648180W
• Request Priority Sequence
Three types of requests can be input to the CPU.
1.
Requests that can be accepted and executed at the end of a state (WAIn
2.
Requests that can be accepted and executed at the end of a machine cycle (refresh requests,
DMA requests, BUSREQ)
3. Requests that can be accepted and executed at the end of an instruction (all interrupts)
Basically, the priority sequence gives 1 the highest priority, and 3 the lowest.
Within group 2 above, the descending priority sequence is:
BUSREQ
Refresh request
DMArequest
If a BUSREQ and refresh request are input simultaneously, the BUSREQ is given priority.
For the priority sequence of the interrupts in group 3 above, see the section of this manual
that details interrupt operations.
4.
Among requests that are accepted and executed in the final machine cycle of an instruction,
the descending priority sequence is:
Bus requests (BUSREQ, refresh request, DMA request)
Interrupt
•
890
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
• Mode Transitions
NMI =0
STBY =0
1-
/STBY=O
DMA request '2
Notes: 1. Normal: Normal CPU instruction execution mode
2. DMA request: DREOo or DREO l = 0 (for memory H (memory-mapped) 110
transfers)
DEO = 1 (for Memory H Memory transfers)
3. DMA end: URE:fo or ~ = 1 (for memory H (memory-mapped) 110 transfers)
BCRO and BCR1 = OOOOH (for all transfer modes)
NMI = 0 (for all transfer modes)
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
891
HD648180W
In addition to the above, the following mode transitions are also possible.
1.
From halt to DMA, refresh, or bus release, and vice versa.
2.
From sleep to bus release, and vice versa.
$
892
HITACHI
Hitachi America, Ltd, • Hitachi Plaza • 2000 Sierra Point Pkwy, • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
• Status Signal List
The following list shows the status signal output for each mode.
Address Data
Bus
LlR ME IOE RD WR REF HALT BUSACK ST Bus
Mode
0
0
0
0
0
Memory
read
0
Memory
write
0
CPU
1st op code
operation fetch
Other op
code fetch
0
A
In
0
A
In
0
A
In
A
Out
A
In
A
Out
A
In
*
A
In
0
0
A
In
1
0
A
In
0
A
In
0
*
Z
In
1
0
A
In
0
I/O read
0
I/O write
0
0
0
Internal
operation
0
Refresh
Interrupt
acknowledge (1 st
machine
cycle)
NMI
0
INTo
0
0
0
0
INT1 , INT2 ,
and
internal
interrupts
Z
Bus release
Halt
0
Z
0
Z
Z
0
0
0
Sleep
Internal
DMA
Memory
read
0
Memory
write
0
0
0
I/O read
0
I/O write
0
In
*
0
A
In
*
0
A
Out
*
0
A
In
0
A
Out
Z
In
0
0
Reset
1 = high level; 0 = low level; * = undefined; A = any value; Z = high impedance; IN = input; OUT =
output
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
893
HD648180W
• Internal I/O Register Reference
The upper 8 bits of the I/O register address are all O. The most significant bit of the lower 8 bits
can be set using the lOA7 bit of the 10 control register. The table below shows the addresses
when IOA7 = O.
Register
Address
DMA source address
register
channel a L: SARaL
2a
DMA source address
register
channel a H: SARaH
21
DMA source address
register
channel a B: SARaB
22
Remarks
Only bits a, 1, 2, and 3 are used
A 19, A 18 ,
DMA destination
address register
channel a L: DARaL
23
DMA destination
address register
channel a H: DARaH
24
DMA destination
address register
channel a B: DARaB
25
An,
A 16
DMA Transfer Request
x
x
a
a
DREao (external)
x
x
a
1
Not used
x
x
1
a
Not used
x
x
1
1
Not used
Only bits a, 1, 2, and 3 are used
A 19, A 18,
An,
A 16
DMA Transfer Request
x
x
a
a
UREOO (external)
x
x
a
1
Not used
x
x
1
a
Not used
x
x
1
1
Not used
DMA byte count register 26
channel a L: BCRaL
DMA byte count register 27
channel a H: BCRaH
•
894
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Register
Address
DMA memory address
register
channel 1 L: MAR1 L
28
DMA memory address
register
channel 1 H: MAR1 H
29
DMA memory address
register
channel 1 B: MAR1 B
2A
DMA I/O address
register
channel 1 L: IAR1 L
2B
DMA 1/0 address
register
channel 1 H: IAR1 H
2C
Remarks
Only bits 0, 1, 2, and 3 are used
DMA byte count register 2E
channel 1 L: BCR1 L
DMA byte count register 2F
channel 1 H: BCR1 H
DMA status
register: DSTAT
30
Bit
7
Imtlalvalue
I
31
Bit
7
I -
32
Bit
lrutlal value
33
5
0
DWE1
1
RlW
W
I
4
DWED
1
I
3
DIE1
0
OlEO
0
6
5
4
3
2
DM1
DMO
SM1
SMO
I
I
I
I
I
1
D
I
-
RlW
FWI
W
1
2
I
-
1
I MMOD
DME
0
I
0
-
0
0
0
0
0
1
ANI
RlW
ANI
ANI
-
7
6
5
3
2
1
0
FWI
IL7
0
FWI
5
6
I
IL6
0
I
FWI
RlW
4
I
115
0
FWI
IWIO
1
0
0
0
0
RIW
RlW
RIW
RIW
RlW
1
-
I
IDMS1 I DMSO I DIM1 I DIMO
4
I
3
I
-
I
2
1
0
-
I -
I -
-
-
1
1
-
-
1
I
Fixed code
I
R
RIW
1
I
Arbitrary values
$
I
-
7
R•• dlWnte
I
-
RlW
Bit
Initial value
DED
I MWI1 I MWIO I IWI1
1
1
1
Read/Write
Interrupt vector low
register: IL
I
1
Irntlslvalue
ReadlWnte
DMAIWAIT control
register: DCNTL
0
6
I
FWI
ReadlWnte
DMA mode
register: DMODE
DE1
1
I
I
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
895
HD648180W
Register
INTfTRAP control
register: ITC
Address
34
Remarks
Bit
7
Initiafvalue
Re.dIW",e
Refresh control
register: RCR
MMU common base
register: CBR
36
Bit
Bit
Initial value
ReadlWnte
MMU bank base
register: BBR
MMU commonlbank
area register: CBAR
39
3A
Bit
3F
6
,
I
ITEI
,
0
ITEO
I
0
0
-
AIW
AIW
I
AIW
I
0
0
AIW
0
AlW
I
CBI
0
0
, CBO
5
4
3
-
I -I I
-
-
-
-
AIW
AIW
AIW
AIW
AIW
AIW
AIW
5
4
3
2
I
0
1
6
CA2
I
RIW
AIW
7
Li§Q
Initial value
1
ReadlWrite
RIW
,
I
-
4
2
, CB4
, CB33 I CB2
,
0
0
0
,
0
0
0
AIW
AIW
AIW
AIW
5
CAl
I
5
6
LlRTE'
I
W
ICC
AIW
I
BAI
0
0
0
AIW
AIW
AIW
3
, -2
I
I
-
-
-
AIW
,
I
AIW
4
-
,
-
I
I
-
-
7
I IOAR ,
6
5
4
-
-
0
I
AlW
-
'IOSTOpl
0
AIW
,
3
-
I
I
-
-
2
I
I
-
,
0
4
3
2
I CAOI I SA3 I BA2 ,
AIW
,
0
I BBS I BB4 I BB3 I BB2 I BSI0 I SBO
0
I
I CYCI I CYCO I
AIW
-
I
2
I
0
7
I CA3 ,
I
2
, ITE2
0
AIW
Inlttalvalue
-
-
5
CBS
0
6
AIW
BII
I
I
CB6
ReedlWrite
•
-
-
7
I CB7 ,
Initial value
Bit
I
3
4
I
I
AIW
6
Bit
5
-
I
AlW
BB6
0
Read/WrIte
896
7
7
ReadIW"te
110 control
register: IOCR
R
I BB7a I
Initlafvalue
Operating mode control 3E
register: OMCR
AIW
I REFE I REFW I
Initial value
Read/Write
38
6
I TRAP I UFO I
0
0
I
I
AIW
,
0
BAO
0
AIW
,
, -0
I
I
I
I -I ,
-
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
0
I
-
,
HD648180W
Register
Free-running
counter H: FRCH
Free-running
counter l: FRCl
Timer control/status
register 1: TCSR1
Output compare
register 1 H: OCR1H
Output compare
register 1 l: OCR1 l
Address
40
Remarks
Bit
Intial value
ReadIWrite
41
Bit
Bit
I
Bit
I
0
I FRce I
0
RlW
0
0
0
0
0
RIW
RIW
RIW
RIW
RIW
7
ICF
0
R
S
4
3
2
6
I
0
I FRC6 I FRCS I FRC4 I FRC3 I FRC2 I FRCI I FRCO I
0
0
0
0
0
0
0
RlW
RIW
RIW
RIW
RIW
RIW
RIW
I
S
6
OCF
TOF
I
0
0
R
R
4
EICI
I
0
RIW
3
2
I
0
EOCI
ETOI
IEDG I OLVl I
I
I
I
0
0
0
0
RIW
RIW
RIW
RIW
7
6
S
4
3
2
I
0
I
RIW
I
RlW
I
RIW
I
RIW
I
RIW
I
RIW
I
RIW
I
RIW
6
S
4
3
I
RlW
I
RIW
I
RIW
I
RIW
IOCRIS I OCRI41 OCRI31 OCRI21 OCRII IOCRIO I OCRe I OCRa I
Bit
7
I OCR7
I
RIW
Imtial value
45
2
0
0
ReadiWrile
Input capture
register H: ICRHNote
3
RIW
RIW
Initial value
ReadlWrile
44
4
0
7
Initial value
ReadlWrite
43
S
RIW
I FRC7
Initial value
ReadlWrite
42
6
7
I FRCIS I FRCI41 FRCI31 FRCI21 FRCII I FRCIO I FRce
Bit
I OCR6 I OCAS I OCR4 I OCR3
I
2
0
I OCR2 I OCRI IOCROI
I
I
I
RIW
RIW
RIW
7
4
5
I
6
3
2
0
IICRI5 I ICRI411CRI3 IICRI2 IICRII IICRIO I ICR9 I ICRB I
Initial value
. . . . . . . .
ReadIWnte
R
R
R
R
R
R
R
R
• Undefined
Input capture
register l: ICRlNote
46
7
Bit
I nital value
6
5
I ICR?
. I ICR6. I ICAS.
ReadIWnte
R
R
R
I
4
ICR4
.
R
3
2
I
0
I ICR3
. I ICR2. I ICRI. I ICRO.
R
R
R
I
R
• Undefmed
Note: ICRH and ICRl are not initialized by reset.
•
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
897
HD648180W
Register
Address
Transmit/receive
control/status register
AO: TRCSRAO
47
Transmit/receive
control/status register
B 0: TRCSRBO
48
Rate/mode control
register 0: RMCRO
49
Remarks
Bit
7
I RDRFO
4B
Serial port control
register: SCIPCR
4C
0
1
0
R
RIW
5
4
B~
7
I RDRFO
0
40
Initial value
1
ReadlWrile
-
7
6
Bit
RlW
7
Initial value
Bit
I
R
R
5
4
REO
0
RIW
2
I
3
1
3
ceol
1
I
TEO
0
WUO
I
0
0
0
RIW
RIW
RIW
2
1
0
I
I PENO I EOPO I SBLO I
0
0
0
-
SS02 I CC02 I
TIEO
RIW
RIW
RlW
2
1
0
I ccoo I SSOI I SSOO I
0
0
0
0
0
0
RIW
RlW
RIW
RlW
RIW
RIW
5
4
3
2
1
0
ISCKHLOlsOUTMOI SINMO I SCKMO ISCKHUIsou™11 SINMI I SCKMll
0
0
0
0
0
0
0
0
Btt
1
-
RIW
RIW
6
5
I - I-
7
Initial value
I ADEF I
0
ReadIWrite
R
•
898
I
I
TDREO I PERO I
1
0
6
1
-
-
I
R
7
I
4E
6
ORFEO
0
R
Bit
ReadIWrite
AID control/status
register: AOCSR
I
3
4
RIEO
R
l!'lItial value
register: AOCR
I
0
ReadIWrite
AID control
5
TDREO
R
I
Transmit data
register 0: TORO
I
Initial value
Initial value
4A
6
ORFEO
ReadIWrite
ReadJWrite
Receive data
register 0: RORO
I
1
RIW
4
I
1
-
-
6
5
1
-
RlW
RIW
3
2
1
I- I- I
4
I
0
1
1
0
-
-
RIW
RlW
1
0
3
2
CH2
0
0
0
RIW
RIW
RIW
RIW
I
ANE
RIW
AVREF
0
ADS I EADEI I
0
0
RIW
RIW
CHI
I
CHO
I ACSI I ACSO
0
0
RIW
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
RIW
I
I
HD648180W
Register
Address
AID result register:
ADRR
4F
Remarks
BIt
Initial vaue
Re.dlWnt.
Transmit/receive
control/status register
A 1: TRCSRA1
50
Transmit/receive
control/status register
B 1: TRCSRB1
51
Rate/mode control
register 1: RMCR1
52
Bit
Re.dlWr~.
BIt
R.adlWr~.
Bit
IMia! value
54
Timer 2 up-counter
H: T2CNTH
55
Timer 2 up-counter
L: T2CNTL
56
4
3
2
t
R
R
R
R
R
R
R
7
6
5
BIt
0
R
0
R
I
R
7
6
5
4
3
RIEl
REt
I
0
0
RIW
RIW
4
0
R
I -I
I
R
0
R
6
I
1
-
-
7
6
I
0
R
3
I
1
-
5
4
3
0
RIW
I T2C15 I T2C14 I T2C13 I T2C12 I T2CII
0
0
0
0
ReadlWr~.
RIW
RIW
RIW
RIW
Bit
2
[ TIEl
0
RIW
I
R
• Undefined
1
0
TEt
WUt
I
I
0
0
RIW
RIW
I
2
0
I PEN 1 I EOPI I SBLt I
0
0
0
RIW
RIW
RIW
5
4
3
2
1
0
5512 I CC12 I CCll I CCIO
5510
5511
I
I
I
0
0
0
0
0
0
RIW
RIW
RIW
RIW
RIW
RIW
Initial value
2
I
0
I T2Cl0 I T2C9 I T2C8 I
0
0
0
RIW
RIW
RIW
7
Initial value
AeadlWnte
•
0
. . . . . . . .
7
R.adlWr~.
Transmit data
register 1: TDR1
5
IRORFI I ORFEI I TOREI I PERI
lortlal value
53
6
IRORFI I ORFEI I TOREt I
Indlal value
Receive data
register 1: RDR1
7
IADRR71 ADRR61 AORRSI AORR41 AORR31 AORR21 AORRI IAORRO I
6
5
4
3
2
I
0
T2C5
T2C4 I T2C3 I T2C2
T2CI
T2CO
I T2C6 I
I
I
I
I
0
0
0
0
0
0
0
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
I T2C7
0
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
899
HD648180W
Register
Timer 2 time constant
register H: t2CONRH
Address
57
Remarks
Bit
Initial value
R.adlWrile
Timer 2 time constant
register L: T2CONRL
58
Bit
Initial value
59
Bot
Initial value
5A
Bot
Initial value
ReadlWrite
Timer 3 up-counter
L: T3CNTL
58
Bit
Initial value
ReadIWnte
Timer 3 time constant
register H: T3CONRH
5C
Bll
Initial value
ReadIWnte
Timer 3 time constant
register L: T3CONRL
50
Bot
Initial value
5E
4
3
2
1
0
1
W
1
W
1
W
1
W
1
W
1
W
1
W
w
7
6
5
4
3
2
1
0
t
1
W
1
W
1
W
1
W
t
1
W
w
3
2
1
0
1
1
W
W
7
0
RIW
6
I ECM21 I
0
RIW
5
1
-
4
I
I
-
I T20S1 I T20s0 I CK2S1 I CK2S0 I
0
0
0
0
RIW
RtW
RIW
RIW
7
6
4
5
3
2
1
0
I T3C15 I T3C14 I T3C13 I T3C12 I T3CI1 I T3Cl0 I T3C9 I T3CS I
0
0
0
0
0
0
0
0
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
4
7
6
5
3
2
1
0
I T3C7 I T3C6 I T3C5 I T3C4 I T3C3 I T3C2 I T3C1 I 13CO I
0
0
0
0
0
0
0
0
RtW
RIW
RtW
RIW
RtW
RIW
RIW
RIW
7
6
5
4
3
2
1
0
IT3CN1SIT3CN14I13CN131T3CN12IT3CN11IT3CN101 T3CN91 T3CNa]
1
I
1
1
1
1
I
1
W
W
W
W
W
W
W
W
7
6
5
4
3
2
1
0
1
W
1
W
1
W
1
W
1
W
1
W
1
W
1
W
7
6
3
2
l~wl~~I~~I~~I13~I~~IT3~I~~1
ReadIWrite
Timer control/status
register 3: TCSR3
5
~MF2
ReadlWrite
Timer 3 up-counter
H: T3CNTH
6
l~wl~~I~~I~~I~ml~~lu~I~~1
Re.dlWnle
Timer control/status
register 2: TCSR2
7
IT2CN15I T2CN141 T2CN13 I T2CN12I T2CN11 I T2CN10 I T2CN91 T2CNSI
Bit
Initial value
ReadIWrite
I CMF3 I ECM31 I
0
0
RtW
RtW
5
4
1
-
-
I
1
-
I 130S 1 I T30s0 I
0
0
RtW
RIW
0
1
-
I
1
-
~HITACHI
900
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
1
-
I
HD648180W
Register
Address
Remarks
Timer 4 up-counter
H: T4CNTH
SF
Bit
InitiaiValU8
RIW
ReadlWrite
Timer 4 up-counter
L: T4CNTL
Timer 4 time constant
register H: T4CONRH
60
Bit
7
I
61
1
RIW
RIW
RIW
RIW
RIW
RIW
6
5
4
3
2
1
T4C4
T4C3 I T4C2
T4C1
HC6
T4CS
I
I
I
I
0
0
0
0
0
0
I
0
T4CSI
0
RIW
0
I
T4CO
RIW
RIW
RIW
RIW
RIW
RIW
7
6
5
4
3
2
1
0
Bit
value
Btt
Btt
Initial value
64
I
2
T4C10 I T4CQ
0
0
RIW
AeadlWnte
Output data
register 0: OORO
T4C7
I
0
Initial value
63
3
RIW
ReadlWrite
Timer control/status
register 4: TCSR4
4
ReadlWnte
In~laI
62
5
Inllialvalue
ReadlWnte
Timer 4 time constant
register L: T4CONRL
6
7
I T4C15 I T4C14 I HC13 I T4C12 I T4C11
0
0
0
0
0
Bit
Initial value
Read,wnte
I
0
IT4CN15IT4CN14IT4CN13IT4CN12IHCN11IT4CN101 T4CN91 T4CNSI
1
1
1
1
1
1
1
1
W
W
W
W
W
W
W
W
7
6
5
4
3
2
1
0
I T4CN71 T4CN61 T4CNSI T4CN4 I T4CN3 I T4CN2 I HCN1 I T4CNO I
1
1
1
1
1
1
1
1
W
W
7
6
I CMF4 I ECM41 I
0
0
W
W
5
-
4
I
-
W
W
W
W
3
2
1
0
I T4051 I T40S0 I CK451 I CK450 I
1
1
0
0
0
0
RIW
RIW
-
-
RIW
RIW
RIW
RIW
7
6
5
4
3
2
1
0
I OOR07 I OORo.1 OORO. I OORO, I OORO, I OOR02 I ODRO, I OORO. I
0
0
0
0
0
0
0
0
RIW
RIW
RIW
RIW
RIW
RIW
RIW
RIW
Note Reading obtains mput port values
Output data
register 1: OOR1
65
Bit
IllItiaivalue
ReadIWnte
6
7
S
4
3
2
1
0
I OOR17 I OOR1.1 OOR1·IOOR1,IOOR1,I OOR1 2I OOR1, I OOR1. I
0
0
0
0
0
0
0
0
RlW
RIW
RlW
RIW
RIW
RIW
RIW
RIW
Note Reading obtams Input port values
Output data
register 2: OOR2
66
Btt
7
I -
Initial value
1
ReadlWnte
-
6
S
4
3
2
1
0
I 00R2.1 OOR2s I OOR2, I OOR2, I 00R2 2 1 OOR2, I OOR2. I
0
0
0
0
0
0
0
RIW
RIW
RIW
RIW
RIW
RIW
RIW
Note Reading obtBlns mput port values
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
901
HD648180W
Register
Output data
register 3: ODR3
Address
67
68
Port 0 data direction
register: DDRO
69
Port 2 data direction
register: DDR2
7
~S7j
Inrtialvalue
ReadlWnte
Port 4: PORT4
Port 1 data direction
register: DDR1
Remarks
Bit
6A
68
BIt
1/0 port control
register 2: IOPCR2
0
0
RN>/
RN>/
7
6
5
4
0
W
0
0
0
0
0
W
W
W
W
w
l!'IItisl value
0
0
W
W
0
S
2
1
0
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
w
5
4
3
2
1
0
Brt
7
Bit
-
6
j
BIt
-
j DDR2sj DDR2.j DDR2.1 DDR22j DDR2, I DDR20 I
0
0
0
0
0
0
w
w
w
w
w
w
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
w
6
5
7
4
S
2
1
0
jDREQoEI TENDoEI P2,E I BUSE j AOUTE JTOUT ,E I SCK ,E I SCKoE I
IMiai value
Readmnte
Bit
Initial value
•
-
-
7
6
5
4
S
2
1
0
I DDRS71 DDRS.j DDRssj DDRS.j DDR3.1 DDR32j DDRS, j DDR30 I
Initial value
6E
0
Readmnt.
Initial value
6D
0
Initial value
I
6C
0
RN>/
RN>/
RN>/
RN>/
Note Reading obtains Input port values
7
6
5
0
2
1
4
3
j DDR17 I DDR1.1 DDR1sj DDR1.1 DDR1.1 DDR12j DDR1, j DORIo I
Bit
Readmrite
902
0
RN>/
ReadIWnte
ReadlWnte
1/0 port control
register 1: IOPCR1
0
Rm
IDDR07j DDRO.j DDROsj DDRO.j DDRO.j DDR02j DDRO, j DDROo j
Re.dmrit.
Port 3 data direction
register: DDR3
1
6
5
4
S
2
0
ODRS.j ODRSsj ODRS.j ODRS.j ODRs2j ODRS, j CORSo I
0
0
0
0
0
0
0
0
Rm
RN>/
RN>/
RN>/
RN>/
RN>/
RN>/
RN>/
7
6
5
4
S
0
0
0
0
0
0
-
RN>/
RN>/
RN>/
RN>/
RN>/
RN>/
RN>/
I -1 I P307C1 I P3 7CO jlNT2E jlNToE
2
1
0
j PS.C1 j P3.CO ITEND,EI
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD648180W
Register
EEPROM control
register 1: EEC1
Address
70
Remarks
7
Bit
Initlalvaiu8
ReadlWnte
EEPROM control
register 2: EEC2
71
7
I!4t
Initial value
A •• dlWnt.
Memory relocate
register: MRR
System control
register: SYSCR
72
7F
I
PW
0
1
-
-
3
2
1
-
-
5
4
3
2
1
0
RIW
RIW
RlW
RIW
RIW
RIW
3
2
1
0
6
AMR2
0
0
RIW
7
6
1
I
1
,
0
I -1 I -1
-
-
W
RlW
•
-
5
ReadlWnte
A ••dlWnt.
1
2
I
-
Il'lItialvalue
Initial value
4
3
-
6
I AMA31
Bit
4
I -1 I
7
I!4t
5
6
I BUSY I m~ I PEAM I - I
0
1
0
0
A
RIW
RIW
-
1
0
I -1 I -1 I -1 I -1 I
-
I AMR1 I AMRO I EPR3 I EPR2 I EPA1 I EPRO I
0
0
0
0
0
0
5
4
ISTBYE I CKC2 I CKC1 I CKCO I
I AAME I - I - I
0
1
1
1
0
0
0
0
-
-
RlW
RIW
RIW
RlW
RlW
-
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
903
@HITACHI
904
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
8/16-BIT MICROPROCESSOR DATA BOOK
Section Four
HD68000 16-Bit
Microprocessor Family
~HITACHI
~HITACHI
906
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD68000/HD68HCOOO---
MPU (Micro Processing Unit)
-HD68000The HD68000 is the first in a family of advanced micropro·
cessors from Hitachi. Utilizing VLSI technology, the H068000
is a fully·implemented l6·bit microprocessor with 32·bit
registers, a rich basic instruction set, and versatile addressing
modes.
The H068000 possesses an asynchronous bus structure with
a 24·bit address bus and a 16·bit data bus.
FEATURES
• 32·Bit Data and Address Registers
• 16 Megabyte Direct Addressing Range
• 56 Powerful Instruction Types
• Operations of Five Main Data Types
• Memory Mapped, 110
• 14 Addressing Modes
HD68000·S, HD6S000·10, HD6S000-12
HD6SHCOOO-S, HD6SHCOOO·l0, HD6SHCOOO-12
(DC-64)
HD6S000Y·S, HD6S000Y·l0, HD6S000Y·12
HD6SHCOOOY-S, HD6SHCOOOY-l0, HD6SHCOOOY·12
- HD68HCOOO -
The H068HCOOO is a 16-bit microprocessor of H068000
family, which is exactly compatible with the conventional
H0680oo.
The H068HCOOO is a complete CMOS device and the power
dissipation is extremely low.
FEATURES
• Instruction Compatible with NMOS HD68000
• Pin Compatible with NMOS HD68000
• AC Timing Compatible with NMOS HD68000
• Low Power Dissipation (Icc typ = 20 mA, Icc max =35 mA
atf= 12.5 MHz)
HD6S000P·S
HD6SHCOOOP-s, HD6SHCOOOP-l0, HD6SHCOOOP-12
HD6S000PS-S
HD6SHCOOOPS-S, HD68HCOOOPS-l0, HD68HCOOOPS·12
(Dp·64S)
HD6S000CP-S
HD6SHCOOOCP-S, HD6SHCOOOCP-l0, HD6SHCOOOCP-12
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589·8300
907
HD68000/HD68HCOOO
• TYPE OF PRODUCTS
Type No.
HD68000-8
HD6BOOO-10
HD68000-12
HD68000Y-8
HD68000Y-10
HD68000Y-12
Process
NMOS
HD68000~
HD68000PS8
HD68000CIlS
HD6BHCOOO-8
H D6BH COOO-1 0
HD6BHCOOO-12
HD6BHCOOO¥B
HD6BHCOOOY-10
H D6BHCOOOY-12
HD6BHCOOOflB
HD6BHCOOOP-10
HD6BHCOOOR-12
HD6BHCOOOPSS
H D68HCOOOP5-1 0
HD68HCOOOP5-12
HD68HCOOOC~
HD68HCOOOCP-10
HD6BHCOOOCP-12
CMOS
Clock Frequency
(MHz)
8.0
10.0
12.5
B.O
10.0
12.5
B.O
8.0
B.O
8.0
10.0
12.5
B.O
10.0
12.5
8.0
10.0
12.5
B.O
10.0
12.5
8.0
10.0
12.5
Package
DC-64
PGA-68
DP-64
DP-64S
CP-68
DC-64
PGA-68
DP-64
DP-64S
CP-68
(Note) HD68000 refers to the NMOS version 68000. and HD68HCOOO
refers to the CMOS version 68000. 68000 stands for NMOS and
CMOS version.
~HITACHI
908
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD62000/HD68HCOOO
• PIN ARRANGEMENT
• DC-64, OP-64, OP-64S
• PGA-68
1 PIN
0
D.
06
07
02
0,
Do
AS
"ODS
013
0,.
OTACK 1
BR 1
Vee 1
ClK 1
Vss 1
HALT 1
RES 1
VMAI
E
~o@
~ 0
Pin No
,
Function
Pin No
NIC
2
3
4
'8
OTACK
~
'8
20
III
5
a
eLK
HALT
7
VIlA
2'
22
23
24
B
8
iEiiii
'0
A'6
A,.
"'2
'3
'4
'5
It
A'2
A11
17
E
NIC
Fe,
FCo
",
A,
......
A,
"
0
ft
41.,
@Jg)J@:
~@~t0~®lJ~®
oooo@o@o@@
(Bottom View)
FuncttOn
A,
N/e
....
....
A"
A"
PinNa
36
38
37
38
J1j
40
FunctIOn
Pin No
Function
0,
52
53
....
50
55
56
A"
Vee
V.
Au
AS
LOS
BG
Vee
V.
57
A"
""
RES
58
0 ..
A"
An
VPA
IPl.
58
80
27
0 ..
44
'PLo
8'
0"
0,
0,
:HI
0"
0 ..
0,
0,
0,
0,
0,
45
29
30
3'
32
33
JoI
,
.7
~
4'
42
43
25
:HI
0
@;;.
0053
o
@oo,
0
,
(Top View)
A2'
Vee
A20
A'9
A'8
A17
IPl2
IPl,
IPlo 5
FC2
FC,
FCo
A,
A2
h" "@I@"
D
010
011
012
"I:
oo.w~~;
@
45
Fe,
NIC
47
A,
4B
48
50
5'
'"
.......
""
82
0,
83
Do
84
85
88
UDS
RIW
IPL.
87
....
8B
Du
• CP-68
(Top View)
(Top View)
•
HITACHI
Hitachi America, ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
909
HD68000/HD68HCOOO
• ABSOLUTE MAXIMUM RATINGS
Item
HD68000
HD6BHCOOO
Value
Value
-0.3- +7.0
-0.3- +7.0
0-+70
-55- +150
-0.3- +6.5
-0.3- +6.5
0-+70
-55 - +150
Symbol
..
Supply Voltage
Vee
Input Voltage
Vin
Operating Temperature Range
Topr
Storage Temperature
T,tg
Unit
V
V
·C
·C
'With respect to VSS (SYSTEM GNO)
(NOTE) Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions.
If these conditions are exceeded, it could affect reliability of LSI.
Since the HD68HCOOO is II
C~MOS
deVice, users are expected to be cautious on
"Iatch~up"
problem clused by voltage fracturations .
• RECOMMENDED OPERATING CONDITIONS
Item
Symbol
Supply Voltage
Input Voltage
Other Inputs
All Inputs
Operating Temperature
•
.
.
.
Vee
ClK
HD68HCOOO
HD68000
min
tYP
max
min
typ
max
4.75
5.0
5.25
4.75
2.8
2.0
-0.3
0
5.0
5.25
-
Vee
-
Vee
VIH
2.0
-
Vee
VIL
-0.3
0
25
0.8
70
Topr
25
0.8
70
With respect to VSS (SYSTEM GNO)
.HITACHI
910
Hitachi America, Ltd. • Hitachi Plaza· 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819. (415) 589-8300
Unit
V
V
V
·c
HD68000/HD68HCOOO
• ELECTRICAL CHARACTERISTICS
•
DC CHARACTERISTICS (Vee -IIV ± 11%, Vss - OV, T. - 0 - +70o C, Fig. 1, un I••• oth.rwl.. noted.)
Item
Input "High" Voltage
Svmbol
Test Condition
H088000
min
max
CLK
I
Dt
I
her nputs
Input "Low" Voltage
HD88HCOOO
min
max
2.8
VIH
2.0
Vee
VIL
Vss-0.3
0.8
Vss -0.3
Vee
Vee
0.8
-
2.5
~fI, ~C~fI, OlACK,
2.0
Unit
V
V
IPL o - IPL" VPA, CLK
HALT, RES
lin
@5.25V
-
2.5
-
20
-
20
AS, A I - Au, Do - DIS,
FC o - FC" LOS, R/W, UOS,
VMA
ITSI
@2.4V/0.4V
-
20
-
20
p.A
AS, AI - A,~, ~ -:..Qu,
Output "High" Voltage FC o - FC" LOS, R ,UoS,
VMA,E
E*
VOH
IOH = -400p.t
2.4
-
Vee-OJ5
-
V
Input Leakage Current
Th ree·State (Off State)
Input Current
Output "Low" Voltage
Vee-OJ5
-
HALT
IOL -1.6 mA
-
0.5
-
0.5
AI -A'3, BG, FCo - FC,
RES
IOL =3.2 mA
0.5
0.5
-
0.5
IOL =5.0mA
-
AS, Do - DIS, LOS, R/W, E,
UOS, VMA
IOL =5.3 rnA
-
0.5
-
0.5
CERAMIC PACKAGE
f = 6 MHz
f - 8 MHz
f - 10 MHz
-
1.5
f=12.5MHz
-
1.75
-
-
f=8MHz,
Vee = 5V,
Ta = 25°C
-
0.9
-
-
-
30
-
20.0
-
20.0
Power Dissipation
VOL
Po
PLASTIC PACKAGE
f = 8 MHz
Current Dissipation
10*·
f= 10 MHz
f = 12.5 MHz
Capacitance (Package Type Dependent)
·With external pull up resistor of 1.1
··Without load.
Cin
Vin = OV,
Ta = 25°C,
f = 1 MHz
p.A
0.5
V
W
25
mA
35
pF
kn.
+5 V
lS2074@
or
EQUivalent
Figure 1 Test Loads
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
911
HD68000/HD68HCOOO
• AC CHARACTERISTICS (VCC = 5V ± 5%, Vss = OV, Ta = 0- +70°C, unless otherwise noted.)
CLOCK TIMING
Item
Frequency of Operation
Cycle Time
Symbol
8 MHz
10 MHz
12.5 MHz
Unit
min
max
min
max
min
max
f
4.0
4.0
100
45
45
10.0
250
125
125
4.0
80
MHz
125
55
55
8.0
250
125
125
12.5
teye
250
ns
35
35
125
125
ns
-
10
10
-
10
10
-
5
5
ns
tCl
Clock Pulse Width
Test Condition
Fig. 2
tCH
tCr
Rise and Fall Times
tCt
ns
ns
j 4 - - - - - - - - teye -------<~
(NOTE)
Timing measurements are referenced to and from a low voltage of 0.8 volt and high a voltage of 2.0 volts, unless otherwise noted.
The voltage sWing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 volt and
2.0 volts.
Figure 2 Clock Input Timing
•
912
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD68000/HD68HCOOO
READ AND WRITE CYCLES
Item
Num.
Test
Svmbol Condition
8MHz
10 MHz
12.5 MHz
min max min mex min max
Unit
1
Clock Period
toyc
125 250
100 250
80
250
ns
2
Clock Width Low
tCL
55
125
45
125
35
125
ns
3
Clock Width High
tCH
55
125
45
125
35
125
ns
4
Clock Fall Time
tCI
-
10
10
5
ns
5
Clock Rise Time
tCr
-
10
-
5
ns
S
Clock Low to Address Valid
70
55·
ns
55
ns
ns
-
10
-
SA
Clock High to FC Valid
tCHFCV
-
7
Clock High to Address, Data Bus
High Impedance (Maximum)
tCHADZ
-
SO
-
70
-
60
8
Clock High to Address, FC Invalid (Minimum)
tcHAFI
0
-
0
-
0
-
ns
9'
Clock High to AS, OS Low
tCHSL
0
60
0
55
0
55
ns
Address Valid to AS, OS Low (Read)/
AS Low (Write)
tAVSL
30
-
20
-
0
-
ns
112
llA2
tCLAV
FC Valid to AS, OS Low (Read)/
AS Low (Write)
tFCVSL
12'
132
Clock Low to AS, OS High
tCLSH
AS, OS High to Address/FC Invalid
tSHAFI
142
AS, OS Width Low (Read)/AS Low (Write)
14A2
OS Width
Low (Write)
Fig. 3,
Fig.4
70
60
80
-
60
-
50
-
40
-
ns
-
70
-
55
-
50
ns
30
-
20
-
10
-
ns
195
160
-
ns
95
-
80
ns
105
-
65
-
tsL
240
tDSL
115
tSH
150
152
AS, OS Width High
16
Clock High to Control Bus High Impedance
tCHCZ
-
60
-
70
-
60
ns
172
AS, OS High to R/W High (Read)
tSHAH
40
-
20
-
10
-
ns
lSI
Clock High to R/W High
tcHAH
0
70
0
60
0
60
ns
Clock High to R/W Low (Write)
tcHAL
70
-
60
ns
tASAV
-
60
AS Low to R/W Valid (Write)
-
20
ns
0
0
30
-
ns
50
-
ns
20'
20A6
20
20
ns
212
Address Valid to R/W Low (Write)
tAVAL
20
21A2
FC Valid to R/W Low (Write)
tFCVRL
60
222
R/W Low to OS Low (Write)
'tALSL
80
-
23
Clock Low to Data Out Valid (Write)
tCLDO
-
70
-
55
-
55
252
AS, OS High to Data Out Invalid (Write)
tsHDOI
30
-
20
-
15
ns
262
Data Out Valid to OS Low (Write)
tDOSL
30
-
20
15
-
ns
27 5
2S2
-
-
AS, OS High to OTACK High
0
150
ns
-
ns
ns
29
30
31 2• 5
Data In to Clock Low (Setup Time on Read)
tOlCl.
15
-
50
10
30
10
tSHDAH
0
245
0
AS, OS High to Data In Invalid
(Hold Time on Read)
tsHDII
0
-
0
tSHBEH
0
-
0
OS High to BIDfR High
0
-
0
AS,
190
ns
ns
ns
ns
OTACK Low to Data In (Setup Time)
tDALDI
-
90
-
65
-
50
32
HALT and RESET Input Transition Time
tAHr, I
0
200
0
200
0
200
ns
33
Clock High to'BG Low
tCHGL
-
70
-
60
50
ns
34
Clock High to BG High
tcHGH
-
70
-
-
50
ns
35
BR Low to BG Low
tBALGL
90
ns
1.5
+3.5
60
80
1.5
ns
+3.5
70
ns
1.5
+3.5
Clk.
Per .
• 57 lor HD6BHCOOO
~HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
913
HD68000/HD68HCOOO
READ AND WRITE CYCLES (CONTINUED)
Item
Num.
Test
Symbol Condition
SMHz
10MHz
12.5 MHz
Unit
min
max
min
max
min
max
367
BR High to BG High
tBRHGH
1.5
90ns
+3.5
1.5
SOns
+3.5
1.5
70ns
Clk.Per.
+3.5
37
BGACK Low to BG High
tGALGH
1.5
OOns
+3.5
1.5
SOns
+3.5
1.5
70ns
+3.5 Clk.Per.
37A8
BGACK Low to BR High
toALBRH
20
1.5
Clock!
20
1.5
Clocks
20
1.5
Clocks
ns
3S
BG Low to Control, Address, Data Bus
High Impedance (AS High)
tGLZ
-
SO
-
70
-
60
39
BG Width High
tGH
1.5
-
1.5
-
1.5
-
tcLVML
-
70
ns
55
-
70
70
-
70
45
ns
tEr, f
-
25
-
25
-
25
ns
200
-
150
-
90
-
ns
0
120
0
90
0
70
ns
-
ns
Clk.Per.
40
Clock Low to VMA Low
41
Clock Low to E Transition
42
E Output Rise and Fall Time
43
VMA Low to E High
tVMLEH
44
AS, DS High to VPA High
IsHVPH
45
E Low to Control, Address Bus Invalid
(Address Hold Time)
lELCAI
30
-
10
-
10
46
BGACK Width Low
tGAL
1.5
-
1.5
-
1.5
tASI
20
-
20
-
ns
20
-
20
-
20
teELOAL
20
-
ns
tCLET
Fig.3,
Fig.4
ns
Clk.Per.
47 5
Asynchronous Input Setup Time
4S3
BERR Low to DTACK Low
499
AS, DS High to E Low
tsHEL
-70
70
-55
55
-45
45
ns
50
E Width High
tEH
450
-
350
-
2S0
-
ns
51
E Width Low
tEL
700
-
550
-
440
-
ns
53
Clock High to Data Out Invalid
tcHOOI
0
0
-
ns
E Low to Data Out Invalid
tELoOI
30
20
-
0
54
-
15
-
ns
55
R/W to Data Bus Driven
tRLOBO
30
-
20
-
10
-
ns
564
HALT/RESET Pulse Width
tHRPW
10
1.5
1.5
1.5
-
Clk.Per.
tGABO
5S7
BG High to Control Bus Driven
tGHBO
1.5
-
1.5
-
10
BGACK High to Control Bus Driven
-
10
57
1.5
-
Clk.Per.
Clk.Per.
NOTES:
1,
For a loading capacitance of less than or equal to 50 picoferads, substract 5 nanoseconds trom the value given in the maximum columns.
2.
Actuel value depends on clock period.
3. If *47 is satisfied for both OTACK and BEAR. *48 may be 0 nanoseconds.
4.
For power up, the MPU must be held in RES state for 100 rns to allow stabilization of on~hip circuitry. After the system is powered up,
#56 refers to the minimum pulse width required to reset the system,
5. If the asynchronous setup time (647) requirements are satisfied, the DTACK low~to-data setup time (11'31) requirement can be ignored.
The data must only satisfy the date-in clock-low setup time (127) for the following cycle.
6. When AS and R/W are equally loaded (i20%), subtreet 10 nanoseconds from the values given in these columns.
7. The processor will negate 8G and begin driving the bus again if external arbitration logic negates
8. The minimum value must be met to guarantee proper operation. If the maximum value
9. The falling edge of 56 triggers both the negation of the strobes
IS
m before asserting B'G'ACK.
exceeded, BG may be reasserted.
(As and xOS) and the falling edge of E. Either of these events can occur
first, depending upon the loading on each signal. Specification #49 indicates the absolute maximum skew that will occur between the
rising edge of the strobes and the fall ing edge of the E clock .
•
914
HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD68000/HD68HCOOO
These waveforms should only be referenced in regard to the
edge·to-edge measurement of the timing specifications. They
are not intended as a functional description of the input and
output signals. Refer to other functional descriptions and
their related diagrams for device operation.
Data In
BERR/8R
(Note 2)
Asynchronous _ _ _ _ _ _ _ _ _ __
Input
(Note 1) - - - - - - - - - - -
NOTES:
1. Setup time for the synchronous inputs BGACK. IPL O_2 and VPA guarantees their recognition at the next falling edge of the clock.
2. BR need fall at this time only in order to insure being recognized at the end of this bus cycle.
3. Timing measurements are referenced to and from
II
low voltage of 0.8 volt and a high voltage 2.0 volts. unle" otherwise noted.
The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between
0.8 volt and 2.0 volts.
Figure 3. Read Cycle Timing
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300
91 5
HD68000/HD68HCOOO
These waveforms should only be referenced in regard to the
edge-ta-edge measurement of the timing specifications. They are
not intended as a functional description of the input and output
signals. Refer to other functional descriptions and their related
diagrams for device operation.
elK
R/Vii
Ooto Out
BERA/BR
(Note 2)
Asynchronous - - - - - - - - - - - - .
r--------
Inputs
(Note 1)
NOTES:
1. Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted.
The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between
O.B volt ond 2.0 volts.
2. Because of loading variations, R/W may be valid after
A! even though
both are initiated bV the rising edge of S2 (Specification 2OA).
Figure 4. Write Cycle Timing
•
916
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD68000/HD68HCOOO
•
HMCS6800 TIMING
Test
Symbol
Item
Num.
6MHz
8MHz
10 MHz
12.5 MHz
Condition min max min max min max min max
Unit
12
Clock Low to
tcLSH
-
80
-
70
-
55
-
50
n5
18
Clock High to R/W High
tcHRH
0
80
0
70
0
80
0
80
n5
20
Clock High to R/W Low (Write)
tcHRL
-
80
-
70
n5
23
tcLDO
55
-
60
Clock Low to Data Out Valid (Write)
-
55
n5
27
Data In to Clock Low (Setup Time on Read)
tDICL
10
-
10
-
n5
29
AS, ~ High to Data In Invalid
-
n5
40
Clock Low to VMA Low
70
n5
41
Clock Low to E Transition
tcLET
42
ter I
43
E Output Rise and Fall Time
~ Low to E High
-
tvMLEH
240
-
200
-
150
-
90
-
ns
44
~, ~ High to VPA High
tsHVPH
0
160
0
120
0
90
0
70
ns
45
E Low to Control, Address 8us Invalid
teLCAI
35
-
ns
45
-
ns
AS, DS High
(Hold Time on Read)
-
80
-
70
25
-
15
-
0
-
0
-
0
70
-
70
-
tsHDIl
Fig.5,
0
-
tcLVML
Fig. 6
-
80
35
25
(Address Hold TIme)
47
Asynchronous Input Setup Time
49 1
AS, DS High to E Low
tASI
25
tsHEL
-80
50
E Width High
teH
800
51
E Width Low
E Low to Data Out Invalid
teL
900
teLDOI
40
54
60
-
-
-
-
-
70
25
55
25
30
-
10
-
10
20
-
20
-
20
-70
450
700
30
70 -55
55 -45
-
-
-
350
550
20
280
440
15
45
ns
25
ns
-
ns
ns
ns
ns
NOTE:
1. The falling edge 01 S6 triggers both the ft8IIIItion 01 the strobel (AJ end xDSlend the IllIIng edge 01 E. Either 01 these ovents cen occur first,
depending upon the loading on eoch Ilgnal. Specification 11'49 Indlcatel the eboolute maximum Ikew that will occur between the rising edge 01
the strobes Ind the falling edge of the E clock.
~~~~~wwwwwwwwwwww~~~~
NOTE: Thll timing diagram II Included for th_ who wish to design their own circuit to generate VQA. It shows the best case possiblV attainable.
Figure 5. HD6800 Timing-Best Case
• HITACHI
Hitachi America, Ltd .• Hitachi Plaza' 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819' (415) 589-8300
917
HD68000IHD68HCOOO
~~~~Mwwwwwwwwwwwwwwwwwwwwwwwwwwwwe.~~
NOTE: This timing diagram illncludod for thooo who wish to design thoir own circuit to genorateVMA. It shOWI tho worst c_ possibly ett.lnoble.
Figure 6. HD6800 Timing-Worst Case
BUS ARBITRATION
Test
Item
Num.
7
Symbol
Clock High to Address, Data Bus
High Impedance
8MHz
10 MHz
12.5MHz
Condition min max min max min max
Unit
16
Clock High to Control Bus High Impedance
tcHCZ
33
Clock High to BG Low
tcHGL
34
Clock High to BG High
tcHGH
-
35
BR Low to BG Low
tBALGL
1.5
BOns
70ns
90ns
1.5
1.5
Clk.Per.
+3.5
+3.5
+3.6
36'
BR High to BG High
tBRHGH
1.6
90ns
BOns
1.6
1.5 70,!! Clk.Per.
+3.6
+3.5
+3.6
37
BGACK Low to BG High
!GALGH
1.5
BOns
90ns
70ns
1.6
1.5
CIk.Per.
+3.5
+3.5
+3.5
37A2
BGACK Low to BR High
!GALBAH
38
tcHADZ
Fig.7Fig. 9
80
80
70
70
-
70
70
60
60
1.5
1.5
20 Clock, 20
",lock
BG Low to Control, Address, Data
Bus High Impedance (AS High)
tGLZ
-
tGH
1.6
!GAL
1.5
39
BG" Width High
46
BGACK Width Low
47
Asynchronous Input Setup Time
IAsl
20
57
BGACK High to Control Bus Driven
!GABD
1.6
58'
BG High to Control Bus Driven
!GHBD
1.5
BO
-
-
1.6
1.5
20
1.5
1.5
70
-
-
-
60
ns
60
ns
50
ns
50
ns
1.6
20 Clock
ns
-
60
ns
-
Ek.Per.
1.5
1.5
20
1.6
1.5
-
Ok.Per.
ns
CIk.Per.
CIk.Per.
NOTES:
1. The prOCOllor will negotolfG and bogln driving tho bus again if external .rbitretion logic negote, iR before ....rt'ng BGACK.
2. The minimum value must be met to gUlrante. proper operation. If the maximum value is exceeded. R may be re....rtect.
•
918
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD68000/HD68HCOOO
Figures 7, 8, and 9 depict the three bus arbitration cases that
can arise. Figure 7 shows the timing where AS is negated when
the processor ~rts DC (Idle Bus Case). Figure 8 shows the
timing where AS is asserted when the processor asserts DC
(Active Bus Case). Figure 9 shows the timing where more than
one bus master are requesting the bus. Refer to Bus Arbitration
for a complete discussion of bus arbitration.
The waveforms shown in Figures 7, 8, and 9 should only be
referenced in regard to the edge-to-edge measurement of the
timing specifications. They are not intended as a functional
description of the input and output signals. Refer to other func·
tional deSCriptions and their related diagrams for device opera·
tion.
ClK
R/W
FCO-FC2
AI-~
00- 0 15
~
1-
Figure 7. Bus Arbitration Timing Diagram - Idle Bus Case
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589·8300
919
HD68000/HD68HCOOO
57
ClK
lOS/ODS _ _ _..../
RiW
F~-FC. =========t==*--------+----~c:====
Do-DIS
Figure 8. Bus Arbitration Timing Diagram - Active Bus Case
ClK
@
t--
19-
I-
Ir-l.r--
V-V-l.r--
~
Figure 9. Bus Arbitration Timing Diagram - Multiple Bus Requesu
•
920
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589-8300
HD68000/HD68HCOOO
•
INTRODUCTION
Programming Model
As shown in the programming model, the 68000 offers seven·
teen 32·bit registers in addition to the 32·bit program counter
and a I6·bit status register. The first eight registers (DO - 07)
are used as data registers for byte (8·bit), word (16·bit), and
long word (32·bit) data operations. The second set of seven
registers (AO - A6) and the system stack pointer may be used
as software stack pointers and base address registers. In addi·
tion, these registers may be used for word and long word
address operations. All 17 registers may be used as index regis·
ters.
The status register contains the interrupt mask (eight levels
available) as well as the condition codes; extend (X), negative
(N), zero (Z), overflow (V), and carry (C). Additional status
bits indicate that the processor is in a trace (T) mode and/or
in a supervisor (S) state.
Status Register
System Byte
r---~/\."------.
31
1615
87
r-
I
I
I
I
I
I
I
I
I
l-
r-r--
I
I
l-
I
I
I
I
I
I
31
1615
l-
r--
D
-
-
I
-
I
I
I
0
_ AD
AI
A2 Seven
Address
Registers
- A3
A4
- A5
II-
-
I-
...
r
User Byte
(Condition A.'-_
Code Register)
,.-_____
_-,
4
3
-
- A6
r------u;;;a;kPo7n;r-------~A
Supervisor Stack POinter
~---------------------~
31
24 23
D
~:::::~:;
Interrupt
Mask
DO
01
02
03 Eight
oota
04 Register,
05
06
07
15
87
ISystem Byte:
Zero
Overflow
Table 1
7Two Stack
POinters
I 6~~~:=
I Status
Revll,e,
D
User Byte
Addressing Modes
Carry
Unused, read as zero.
•
DATA TYPES AND ADDRESSING MODES
Five basic data types are supported. These data types are:
(1) Bits
(2) BCD Digits (4 bits)
(3) Bytes (8 bits)
(4) Word (16 bits)
(5) Long Words (32 bits)
In addition, operations on other data types such as memory
address, status word data, etc., are provided for in the instruc·
tion set.
The 14 addressing modes, shown in Table I, includes six
basic types:
(1) Register Direct
(2) Register Indirect
(3) Absolute
(4) Immediate
(5) Program Counter Relative
(6) Implied
Included in the register indirect addressing modes is the capa·
bility to do post incrementing, predecrementing, offsetting and
indexing. Program counter relative mode can also be modified
via indexing and offsetting.
$
Register Direct Addreuing
Data Regilter oiredt
Address Register Direct
Absolute Date Addreuing
Absolute Short
Absolute
Progrem Counter Relative Addr.uing
Relalive with Offset
Relative with Index and Offset
Register Indirect Addreuing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
I mmediote Dota Add,euing
Immediate
Quick Immediate
Implied Add,auing
Implied Register
(NOTES)
EA = Effective Addre..
An Address Register
On = Data Register
Xn = Addre.. or Data Register used
tiS Index Register
SR = Status Register
PC = Program Counter
( ) = Contents of
d. = Elght-bit Offset
(displacement)
Q
EA = On
EA = An
EA
EA
= (Nexl Word)
= (Next Two Words)
EA = (PC) + d ..
EA = (PC) + (Xn) + d.
EA = (An)
EA = (AN). An <-An + N
An <-An - N, EA = (Ani
EA = (An) + d ..
EA = (An) + (Xn) + d.
DATA = Next Word(s)
Inherent Data
EA = SR, USP, SP, PC
dl6 = Sixteen..IJit Offset
(dISplacement)
N = 1 for Byte, 2 for
Words and 4 for long
Words. If An IS the stack
polMter and the operand
si ze is byte, N =2 to keep
the stack pointer on 8
word boundary.
-+- = Replaces
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589·8300
921
HD68000/HD68HCOOO
instructions can use any of the 14 addressing modes. Combining
instruction types, data types, and addressing modes, over 1000
useful instructions are provided. These instructions include
signed and unsigned multiply and divide, "quick" arithmetic
operations, BCD arithmetic and expanded operations (through
traps).
• INSTRUCTION SET OVERVIEW
The 68000 instruction set is shown in Table 2. Some additional instructions are variations, or subsets, of these and they
appear in Table 3. Special emphasis has been given to the instruction set's support of structured high-level languages to facilitate ease of programming. Each instruction, with few exceptions, operates 'on bytes, words, and long words and most
Table 2
Mnemonic
Description
ABCD
ADD
AND
ASL
ASR
Add Dec:imal with Extand
Add
Logical And
Arithmetic Shift Left
BCC
BCHG
BCLR
BRA
BSET
BSR
BTST
Branch Conditionallv
Mnemonic
Arithmetic Shift Right
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and· Set
Branch to Subroutine
Bit Test
CHK
CLR
CMP
Check Register Again,' Bounds
CI..r Operand
DBee
Test Condition, Decrement and
DIVS
DIVU
Brench
Signed Divide
Unligned Divide
Compare
Tvpe
ADD
AND
Vanatlon
ADD
ADDA
ADDQ
ADDI
ADDX
AND
ANDI
ANDI toCCR
ANDI to SR
CMP
EOR
Exclusive Or
E )(change Registers
Sign E.tend
JMP
JSR
Jump
LEA
LINK
LSL
LSR
Loed Effective Addre..
Link Stack
Logical Shift Left
Logical Shift Right
MOVE
MOVEM
MOVEP
MULS
MULU
Move
Mnemonic
Jump to Subroutine
Move Multiple Registers
Move Peripheral Data
Signed Multiply
Unsigned Multiply
Push Effective Addrtll
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left With Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine
SBCD
Sec
STOP
SUB
SWAP
Subtract Decimal with Extend
Set Conditional
No Operation
One's Complement
TAS
TRAP
TRAPV
TST
OR
Logical Or
UNLK
Negate Decimal with Extend
Negate
Description
PEA
NBCD
NEG
NOP
NOT
Stop
Subtract
Swap Data Register Halves
Test and Set Operand
Trap
Trap on Overflow
TOIt
Unlink
Variations of Instruction Types
Instruction
Description
Type
MOVE
Add
Add Addre ..
Add QUIck
Add Immediate
Add with Extend
Logical And
And Immediate
And Immediate to
Condition Codes
And Immediate to
Status Register
CMP
CMPA
CMPM
CMPI
Compare
Compare Address
Compare Memory
Compare Immediate
EOR
EORI
EORI to CCR
E xciuslve Or
EORI to SR
Description
EOR
EXG
EXT
Table 3
Instruction
Instruction Set
Vanatlon
MOVE
MOVEA
MOVEQ
MOVE fromSR
MOVE to SR
MOVE to CCR
MOVE USP
NEG
NEG
NEGX
OR
OR
ORI
ORI toCCR
ORI to SR
SUB
Exclusive Or Immediate
ExclUSive Or Immediate
to Condition Codes
Exclusive Or Immediate
to Status Register
SUB
SUBA
SUBI
SUBQ
SUBX
Description
Move
Move Address
Move
Move
Move
Move
Move
Quick
from Status Register
to Status Aegister
to Condition Codes
User Stack Pointer
Negate
Negate With Extend
Logical Or
Or Immediate
Or Immediate to
Condition Codes
Or Immediate to
Status Register
Subtract
Subtract
Subtract
Subtract
Subtract
Address
I mmediata
Quick
with E xtand
$HITACHI
922
Hitachi America, Ltd. • Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005-1819 • (415) 589·8300
HD68000/HD68HCOOO
• REGISTER DESCRIPTION AND DATA ORGANIZATION
ADDRESS REGISTERS
The following paragraphs describe the registers and data
organization of the 68000.
Each address register and the stack pointer is 32 bits wide
and holds a full 32 bit address. Address registers do not support
byte sil.ed operands. Therefore. when an address register is used
as a source operand. either the low order word or the entire
long word operand IS used depending upon the opera lion size.
When an address register IS used as the destinatIOn operand, the
entue register is affected regardless of the operation size. If the
operation size IS word. any other operands are sign extended
to 32 bits before the operatIOn IS performed.
• OPERAND SIZE
Operand sizes are defined as follows: a byte equals 8 bits,
a word equals 16 bits, and a long word equals 32 bits. The
operand size for each instruction is either explicitly encoded
in the instruction or implicitly defined by the instruction
operation. Implict instructions support some subset of all three
sizes.
• DATA ORGANIZATION IN MEMORY
Bytes are individually addressable with the high order byte
having an even address the same as the word. as shown in
Figure 10. The low order byte has an odd address that is one
count higher than the word address. Instructions and multibyte
data are accessed only on word (even byte) boundaries. If a
long word datum is located at address n (n even), then the
second word of that datum is located at address n + 2.
The data types supported by the 68000 are: bit data, integer
data of 8, 16, or 32 bits, 32·bit addresses and binary coded
decimal data. Each of these data types is put in memory, as
shown in Figure II. The numbers indicate the order in which
the data would be accessed from the processor.
• DATA ORGANIZATION IN REGISTERS
The eight data registers support data operands of 1,8, 16,
or 32 bits. The seven address' registers together with the active
stack pointer support address operands of 32 bits.
DATA REGISTERS
Each data register is 32 bits wide. Byte operands occupy
the low order 8 bits. word operands the low order 16 bits. and
long word operands the entire 32 bits. The least significant bit
is addressed as bit lero. the most significant bit is addressed
as bit 31.
When a data register is used as either a source or destination
operand. only the appropriate low-order portion is changed:
the remaining high-order portion is neither used nor changed.
15
14
13
12
11
Byte 00000o
Byte 000002
Byte FFFFFE
10
9
8
7
6
Word.OOOOOO
Word.000002
WordtFFFFE
5
4
3
2
0
Byte 000001
Byte 000003
4
Byte FFFFFF
Figure 10 Word Organization in Memory
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005·1819 • (415) 589-8300
923
HD68000/HD68HCOOO
Bit Data
6
1 Byte = 8 Bots
4
5
3
2
10
1 Byte = 8 Bots
9
8
7
6
o
I nteger Data
15
14
13
12
11
5
4
3
2
0
Byte 1
Byte 0
n IMSB
n+2
I
LSBI
Byte 3
Byte 2
n+l
n+3
1 Word"" 16 Bits
15
14
"'l~
13
12
11
10
9
6
8
5
4
3
2
Word 0
Word 1
Word 2
n+4
0
~'I
n+l
n+3
n+5
1 Long Word = 32 Bits
15 14
MSB
n+2
13
12
11
10
9
8
7
4
6
2
0
n+l
High Order
- - Long Word 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LSB
Low Order
n+3
n+5
n+4
___ Long Word 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
n+7
n+6
n+9
- - "'LongWord 2 ... - - - - - - - - - - - - - - - - - - - - - - - - - - - 0+10
~--------------------------------------~
n+ll
Addresses
1 Address = 32 Bots
4
o
15
14
13
12
11
10
9
8
7
6
3
2
5
MSB
Hogh Order
--AddressO-- - _ - - ______________________
_
n+2
Low Order
LSB
n+l
n+3
n+5
n+4
- - Address 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0+6
n+8
n+l0
r---------------------------------~
__ .Address 2. __ __________________________ _
~M-SB-=-M-os-tS-og-no~foc-an-t-Bo-t----------------------------~
lSB
= Least Significant Bit
n
n+2
MSD
14
13
12
11
n+9
n+ll
Decimal Data
2 Binary Coded Decimal DIgits == 1 Byte
15
0+7
10
9
BCDO
BCDI
BCD4
BCD5
8
7
5
4
LSD
3
2
o
BCD3
n+l
BCD7
n+3
MSD = Most Significant DigIt
LSD:: Least Significant Digit
Figure 11 Data Organization in Memory
•
924
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
HD68000/HD68HCOOO
• ADDRESSING
Instructions for the 68000 contain two kinds of information:
the type of function to be performed, and the location of the
operand(s) on which to perform that function. The methods
used to locate (address) the operand(s) are explained in the
following paragraphs.
Instructions specify an operand location in one of three
ways:
Register Specification - the number of the register is given
in the register field of the instruction.
Effective Address - use of the different effective address
modes.
Implicit Reference - the defmition of certain instructions
implies the use of specific registers.
• INSTRUCTION FORMAT
Instructions are from one to five words in length, as shown
in Figure 12. The length of the instruction and the operation
to be performed is specified by the first word of the instruction
which is called the operation word. The remaining words
further specify the operands. These words are either immediate
operands or extensions to the effective address mode specified
in the operation word.
• PROGRAMVDATA REFERENCES
The 68000 separates memory references into two classes:
program references, and data references. Program references, as
the name implies, are references to that section of memory that
15
14
13
12
11
contains the program being executed. Data references refer to
that section of memory that contains data. Operand reads are
from the data space except in the case of the program counter
relative addressing mode. All operand writes are to the data
space.
• REGISTER SPECIFICATION
The register field within an instruction specifies the register
to be used. Other fields within the instruction specify whether
the register selected is an address or data register and how the
register is to be used.
• EFFECTIVE ADDRESS
Most instructions specify the location of an operand by using
the effective address field in the operation word. For example,
Figure 13 shows the general format of the single effective address
instruction 'operation word. The effective address is composed
of two 3·bit fields: the mode field, and the register field. The
value in the mode field selects the different address modes. The
register field contains the number of a register.
The effective address field may require additional informa·
tion to fully specify the operand. This additional information,
called the effective address extension, is contained in the
following word or words and is considered part of the instruction, as shown in Figure 12. The effective address modes are
grouped into three categories: register direct, memory addressing, and special.
g
10
8
6
5
4
7
Operation Word
IFirst Word Specifi.. Operation and Modesl
Immediate Operand
IIf Any. Ona or Two Word,1
Source Effective Add .... Extension
IIf Any. Ona or Two Wordsl
Oestinatlon Effective Address Extension
Itf Anv. Ona or Two Wordsl
3
2
1
0
Figure 12 Instruction Format
Figure 13 Single-Effective-Address Instruction Operation Word General Format
•
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
925
HD68000/HD68HCOOO
REGISTER DIRECT MODES
These effective addressing modes specify that the operand
is in one of the 16 multifunction registers.
Data Register Direct
The operand is in the data register specified by the effective
address register field.
COMMENTS
MEMORY
MPU
$001 Foo r---'''';;;;':C::---i
• EA = On
• Machine level Coding
MOVE DO.$IFoo
10OOOABcoi DO
;!;II
0011
Word
0001
1100
0000
LReg #0
Absolute
Short
Data
Register
OWL
MOVE DO. $1 Foo
Direct
31CO
OWL+2r--~'F~00=---i
Address Register Direct
The operand is in the address register specified by the effec·
tive address register field.
MEMORY
MPU
1000012341 A4
COMMENTS
• EA = An
• Machine Level Coding
MOVE A4. $201000
I I I~
'OO
Word Absolute
Long
Addres.
MOVE A4.$201000
OWL 1-_.=33:..:C:,;:C;"""--j
OWL + 2
0020
OWL+4r--'='000~----j
•
926
Register
Direct
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
HD68000/HD68HCOOO
EXAMPLE
MPU
COMMENTS
MEMORY
eEA· An
• Address Register Sign Extended
• Machine Level Coding
MOVE $201000. A4
1000012341 A4
0011
1000
0111
1001
~
I~Absol ute
Move
Word
og#4
Long
Address
Register
Direct
OWL
MOVE $201000. A4
OWL+2
0020
OWL+4
1000
MEMORY ADDRESS MODES
These effective addressing modes specify that the operand
is in memory and provide the specific address of the operand.
Address Register Indirect
The address of the operand is in the address register specified
by the register field. The reference is classified as a data reference with the exception of the jump and jump to subroutine
instructions.
COMMENTS
MPU
MEMORY
• EA
= (AnI
• Machine Level Coding
MOVE (AOI. DO
~li~£I~
oats-
1000010001 AD
Word
OWL 1-_...:30=10::"-_-1
Register
Direct
Reg #0
ARI
(Address
Register
MOVE (AOI. DO
Indirect)
.HITACHI
Hitachi America, Ltd .• Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
927
HD68000/HD68HCOOO
Address Register Indirect With Postincrement
The address of the operand is in the address register specified
by the register field. After the operand address is used, it is
incremented by one, two, or four depending upon whether
the size of the operand is byte, word, or long word. If the
address register is the stack pointer and the operand size is
byte, the address is incremented by two rather than one to
keep the stack pointer on a word boundary. The reference is
classified as a data reference.
EXAMPLE
MPU
MEMORY
00000100 A4
COMMENTS
• EA ~ (An); An + M-An
Where An .... Address Register
M -I,2,or4
ID_nding Whether
Byte, Word, or
Long Word)
• Machine Level Coding
MOVE (A4) +, $2000
00000102
0011
~
$2000
0001
AbsL.
Short
MOVE (A41 +,$2000
OWL
310C
OWL+2
2000
Addre .. Register Indirect With Predecrement
The address of the operand is in the address register specified
by the register field. Before the operand address is used, it is
decremented by one, two, or four depending upon whether
the operand size is byte, word, or long word. If the address
MPU
MEMORY
OOOOOOFE
#4
ARI with
Increment
COMMENTS
• An - M_An; EA ~ (An)
Where An ....... Address Register
M _I,2,or4
(Oepending Whether
Byte, Word, or
Long Word)
• Machine Level Coding
.I
MOVE - (A31, $4000
Mow
Word
0001
OWL ~_,,"3_1E_3_ _-I
OWL+2
4000
$
11~11
~~~~l
-L
Absolute
Short
928
1100
register is the stack pointer and the operand size is byte, the
address is decremented by two rather than one to keep the
stack pointer on a word boundary. The reference is classified
as a data reference.
00000100 A3
MOVE - (A3I,S4ooo
I ;r
1101
Predic·
rement
Reg #3
HITACHI
Hitachi America, Ltd .• Hitachi Plaza. 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
HD68000/HD68HCOOO
Add,... Register Indirect With Displ_ment
This address mode requires one word of extension. The address of the operand is the sum of the address in the address
register and the sign-extended l6-bit displacement integer in
the extension word. The reference is classified as a data reference with the exception of the jump to subroutine instructions.
COMMENTS
MPU
MEMORY
• EA'" An + d l6
Where An ------- Pointer Register
d l6 --.......16-8It Displacement
• d l6 Displacement is Sign Extended
• Machme Level Coding
MOVE $100tAO).$3000
100001 000 I AO
I
0001
1110
1000
Abs!luteI:': #0
Short
ARI
with
Move
Word
DISplacement
MOVE $100tAO).$3000
ADDRESS
CALCULATION:
AO - 00001000
dl6 - 00000100
00001100
OWL t-_..;;3..;.1;:.E8:.-_.,
OWL + 2
0100
OWL+4t--~3~000~---i
Add,... Register IndirlCt With Index
This address mode requires one word of extension. The
address of the operand is the sum of the address in the address
register. the sign-extended displacement integer in the low order
eight bits of the extension word. and the contents of the index
register. The reference is classified as a data reference with the
exception of the jump and jump to subroutine instructions.
COMMENTS
MPU
MEMORY
• EA = An + Rx
Where
+ d ll
An ~ Pointer Register
Rx - - Designated Index Register,
(Either Address Register or
Data Register)
d ll -----. 8-Blt Displacement
• Ax & d. are Sign Extended
IOOOO2BDCI 00
• Ax may be Word or Long Word
Long Word may be DeSignated With Rx.L
• Machine Level Coding
~AO
MOVE $04tAO, DO), $1000
0011
.......r-
Move
Word
MOVE $04tAO, DO),
$1000
ADDRESS
CALCULATION:
AO - 00002000
DO - oooo2BDC
0001
Absolute
Short
OWL+2~--0004~--~
OWL+4t-__1~000~_--i
0000
Reg #0
ARI
with
Index
31FO
OWL
1111
-==r=-II:.......
0000
0000
0000
0100
orf[
vl-a1anstant ~
#0
Zeros
Reg
d - 00000OO4
00004BEO
$
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
929
HD68000/HD68HCOOO
SPECIAL ADDRESS MODE
The special address modes use the effective address register
field to specify the special addressing mode instead of a register
number.
Absolute Short Address
This address mode requires one word of extension. The ad·
dress of the operand is the extension word. The 16-bit address
is sign extended before it is used. The reference is classified
as a data reference with the exception of the jump and jump
to subroutine instructions.
MEMORY
MPU
COMMENTS
• EA = (Next Word)
• 16·811 Word is Sign Extended
• Machine Level Coding
NOT.L$2000
$2000
$2002
FFFF --0000
0000 __ FFFF
0100
0110
t
1011
Not Instruction
NOT.L $2000
1000
t.w~
=:0::-1.,-::-=::Absolute
Short
OWL 1-_...;4..;:.6;:.8S:-_o1
OWL + 21-__2_ooo
_ _--l
COMMENTS
• EA = (Next Word)
EXAMPLE
MEMORY
MPU
$1000
• 16-Bit Word is Sign Extended
• Machine Level Coing
MOVE $1000. $2000
0011
$2000
~
Move
Word
0001
1111
1000
I~
Short
Absolute
Short
MOVE $1000. $2000
31FS
OWL
OWL+2
1000
OWL+4
2000
•
930
HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy.• Brisbane, CA 94005·1819 • (415) 589·8300
HD68000/HD68HCOOO
Absolute Long Address
TIlls address mode requires two words of extension. The
address of the operand is developed by the concatenation of
the extension words. The high-order part of the address is the
MPU
first extension word; the low-order part of the address is the
second extension word. The reference is classified as a data
reference with the exception of the jump and jump to sub·
routine instructions.
MEMORY
COMMENTS
• EA = INext Two Words)
• Machine Level Codmg
NEG $014000
0100
0100
0111
1001
~f.z.--=:C
NEG
Absolute
Instruction
OWL
Long
4479
OWL+2r-__~000~~I__~
OWL +4
4000
NEG $014000
Program Counter With Displacemant
TIlls address mode requires one word of extension. The
address of the operand is the sum of the address in the program
counter and the sign-extended 16·bit displacement integer in
MPU
the extension word. The value in the program counter is the ad·
dress of the extension word. The reference is classified as a pro·
gram reference.
MEMORY
COMMENTS
• EA "" (PC) + d 16
• dl 6 IS Sign Extended
• Machine Level Codmg
MOVE (LABEll. DO
IXXXXABCDI DO
0011
0000
0011
1010
I T--:J:th
~~:~
~:~ster
Displacement
Direct
MOVE (LABEL). 00
ADDRESS
CALCULATION:
PC • 0000B002
d -00001000
00009002
< LABEL> $9002
ABCD
r---------4
~HITACHI
Hitachi America, Ltd. • Hitachi Plaza • 2000 Sierra Point Pkwy. • Brisbane, CA 94005-1819 • (415) 589-8300
931
HD68000/HD68HCOOO
Program Counter With Index
This address mode requires one word of extension. This
address is the sum of the address in the program counter, the
sign·extended displacement integer in the lower eight bits of
the extension word, and the contents of the index register.
The value in the program counter is the address of the extension
word. This reference is classified as a program reference.
EA = (PC I + (R.I + d,
(NOTE)
PC Value
I-------i
Extension Word
Beginning
Address of
1PC +
d~
D/A
Data
DeSIred Data
Location
In
Table
l PC + d
: Data Register' O. Address Register' 1
Register I ndex Register Number
W/L
: Sign~xtented. low order Word integer
in Index Register = 0
Long Word in Index Register"" 1
Data Table
Table
+ Rx
1\
MEMORY
MPU
COMMENTS
• EA = (PCI + (Rx) +d.
Where
PC ___ Current Program Counter
$8000~
IXXXX34561DO
$8002~
100001010 IAO
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:10:23 19:55:17-08:00 Modify Date : 2013:10:24 01:24:53-07:00 Metadata Date : 2013:10:24 01:24:53-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:7e9a1b8b-104b-400b-b197-68985cf858e0 Instance ID : uuid:ac6d4024-71b2-4120-98c6-36de59bcd344 Page Layout : SinglePage Page Mode : UseNone Page Count : 1006EXIF Metadata provided by EXIF.tools