1991_IDT_Databook_Update_1 1991 IDT Databook Update 1

User Manual: 1991_IDT_Databook_Update_1

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Integrated Device Technology, Inc.

1991
DATA BOOK UPDATE 1

2975 Stender Way, Santa Clara, California 95054
Telephone: (408) 727-6116 • FAX: (408) 492-8674
Printed in U.S.A.
©1991 Integrated Device Technology

GENERAL INFORMATION

CONTENTS OVERVIEW

Historically, Integrated Device Technology has presented its product offerings entirely under one cover.
In an effort to simplify this information for our customers, it has been divided into four separate data books
- Logic, Specialized Memory, RISC and Static RAM.
This 1991 Update offers new and revised information from each of the four 1991 Data Books. Also
included is a current, complete packaging section for alilDT product groups. This section will be updated
in each subsequent data book.
The Table of Contents contains a listing of the products in the Update. All data sheets are designated
by their corresponding Data Book (A = Logic, B = Specialized Memories, C = RISC, and D = Static RAM)
and page numbered individually. For example, Updated 1 C, centered at the bottom of the page, refers
to the 1991 RISC Data Book. The corresponding page number is shown in the lower right corner. New
data sheets and application notes follow the partial and complete data sheets in the section with the data
book that they will appear in when next published.
A header bar atthe top of each change to a partial or complete data sheet indicates which 1990-91 data
book the original data sheet can be found in. The reference is organized by data book, section and page
number.
IDT, a recognized leader in high-speed CMOS technology, produces a broad line of products. This
enables us to provide a complete CMOS solution to designers of high performance digital systems. Not
only do our product lines include industry standard devices, they also feature products with faster speed,
lower power, and package and/or architectural benefits that allow the designer to achieve significantly
improved system performance.
To find ordering information: Start with the Ordering Information chart at the back of each new data
sheet. Updated data sheets - for which only the updated information has been included - should be
used in reference with the complete data sheet in the appropriate 1991 Data Book.
To find product data: Start with the Table of Contents, organized by data book (data books are
organized with partially updated data sheets at the front, followed by updated full data sheets, then new
data sheets) or with the numeric Table of Contents organized across all product lines. These indexes will
direct you to the pagels) of the partial, full or new data sheet. Included in the update sections is a header
bar above the change which has a reference for locating the complete data sheet in the appropriate 1991
Data Book. Data sheets may be of the following type:
ADVANCE INFORMATION - contain initial descriptions, subject to change, for products that are in
development, including features and block diagrams.
PRELIMINARY - contain descriptions for products soon to be, or recently, released to production,
including features, pinouts and block diagrams. Timing data are based on simulation or initial characterization and are subject to change upon full characterization.
FINAL - contain minimum and maximum limits specified over the complete supply and temperature
range for full production devices.
New products, product performance enhancements, additional package types and new product
families are being introduced frequently. Although this update is published in an effort to keep our
customers informed of new and changing data, ~ is impossible for itto remain current. Please contact your
10caiiDT sales representative to determine the latest device specifications, package types and product
availability.

UPDATE 1 1.1

LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components In life support devices or systems
unless a specific written agreement pertaining to such Intended use is executed between the manufacturer and an officer of lOT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support
or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component Is any component of a life support device or system whose failure to perform can be reasonably expected
to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Note: Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve
design or performance and to supply the best possible product. IDT does not assume any responsibility foruse of any circuitry describedotherthan the circuitry
embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device
Technology, Inc.

The IDT logo is a registered trademark, BUSMUX, Flexi-pak, BiCEMOS, Cache RAM, CEMOS, Flow-thru EDC, IDT/ux, MacStation, REAL8, RISC
SubSystem, RISController, RISCore, SmartLogic, SyncFIFO, TargetSystem, and R3051 are trademarks of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Corporation.
Intel and i486 are trademarks of Intel Corporation.

UPDATE 1 1.1

2

1991 DATA BOOK UPDATE 1
TABLE OF CONTENTS
PAGE

GENERAL INFORMATION
Contents Overview ........................................................................ '" ......... ............. ..................... .............. ... ........
Table of Contents ....... .......... .......... ..................... ... ....... ......... ........ .... ..... ... .......................... .............. ... ... ............
Numeric Table of Contents ................. ................... ....... ................. ... ....... ......... ........................... .............. ... ........

1.1
1.2
1.3

CAPABILITIES.....................................................................................

2

QUALITY AND RELIABILITY .................................................................................................

3

TECHNOLOGY AND

PACKAGE DIAGRAM OUTLINES
Package Diagram Outline Index ..... ........ ....... .... ... ..... ..................... .............. ...... .................. ................. ...............
Monolithic Package Diagram Outlines ..... ..... ......... ..... ....... ...... ........... ..... ..... .............. ... .......... ...... ..... ............ ......
Module Package Diagram Outlines ..................................................... '" ..... .............. .......... .... ..... ... .... ....... ..........

LAST BK.

4.2
4.3
4.4

UPDATEPG.

1990/91 LOGIC DATA BOOK UPDATES
PARTIALLY UPDATED DATA SHEETS
IDT54/74FCT240T
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT241T
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT244T
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT540T
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT541T
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT299T
8-lnput Universal Shift Register w/Common ParalielllO Pins ............
IDT54/74FCT399T
Quad Dual-Port Register .....................................................................
IDT54/74FCT543T
Non-inverting Octal Latched Transceiver. ...........................................
IDT49FCT804
High-Speed Tri-Port Bus Multiplexer ..................................................
IDT54/74FCT240
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT241
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT244
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT540
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT541
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT299
8-lnput Universal Shift Register w/Common ParalielllO Pins ............
IDT54/74FCT399
Quad Dual-Port Register. ....................................................................
IDT54/74FCT543
Non-inverting Octal Latched Transceiver ............................................

A6.10 ....... ;...
A6.10 ...........
A6.10 ...........
A6.10 ...........
A6.10 ...........
A6.13...........
A6.17...........
A6.19...........
A6.29...........
A6.40 ...........
A6.40 ...........
A6.40 ...........
A6.40 ...........
A6.40 ...........
A6.43 ...........
A6.47...........
A6.49...........

A-2
A-2
A-2
A-2
A-2
A-3
A-5
A-5
A-6
A-8
A-8
A-8
A-8
A-8
A-8
A - 10
A - 11

UPDATED FULL DATA SHEETS
IDT73210
Fast Octal RegisterTransceiverw/Parity ............................................
IDT73211
Fast Octal Register Transceiver w/Parity ............................................
IDT49C466
64-BitCMOSFlow-ThruEDCUnit... ....................................................
IDT49FCT805A
Buffer/Clock Driver w/Guaranteed Skew ............................................
IDT49FCT805
Buffer/Clocl< Driver w/Guaranteed SlI~

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UPDATE1 4.4

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UPDATE1 4.4

10

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UPDATE 1 4.4

14

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UPDATE 1 4.4

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UPDATE 1 4.4

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UPDATE1 4.4

20

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UPDATE1 4.4

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22

PACKAGE DIAGRAM OUTUNES

QUAD IN-LINE PACKAGES (Continued)
104·Pln FR·4 Plastic QIP - M3S

r:~;g
Ir-----

:1

~:~~~ ----1~~1

••••••••••••••••••••••••••
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DD

DDD:~g

..........................
1
t
••••••••••••••••••••••••••
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PIN 1

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§

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§
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1.990
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2.210

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0.025

SIDE VIEW

••••••••••••••••••••••••••
••••••••••••••••••••••••••
BOTTOM VIEW

UPDATE1 4.4

23

PACKAGE DIAGRAM OUTUNES

QUAD IN-LINE PACKAGES (Continued)
12o-Pin FR-4 PlastIc QIP - M39

000000000000000000000000000000
000000000000000000000000000000

I...., .....

DD~DD~DD
DD~DD~DD

2.890

0- 0.016
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1.l
f

0.100
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2.990

DD~DD~DD3F1O

2.920

QggQggtggQg~~ggQgg~ 1

0.230

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I

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0.250

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9i1 ilfrffi Irm 1M nmffi fir

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~1!

0.100 TYP.

000000000000000000000000000000
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coooooooooooooooooooooooooooo~

3.040
3.060

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BOTTOM VIEW

UPDATE1 4.4

24

PACKAGE DIAGRAM OUTUNES

QUAD IN-LINE PACKAGES (Continued)
12o-Pln FR-4 Plastic QIP - M40

1

000000000000000000000000000000
000000000000000000000000000000

OO~OD~DD
OD~OD~DD
OO~DD~OD
DO~DD~OO

f

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0.230
0.350

000000000000000000000000000000
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., T
2.690

_'.890 '.790

II

0.125
0.250

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000000000000000000000000000000

o.oooo.oo~.oooo.ooooooooo.ooo

D~DDDD~D

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2.920

l

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2.990
3.010

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cooooooooooooooooooooooooooooo
3.040
3.060
BonOMVIEW

UPDATE1 4.4

25

PACKAGE DIAGRAM OUTUNES

QUAD IN·LlNE PACKAGES (Continued)
128-Pln FR·4 Plastic QIP - M41

ei =

+

00000000000000000000000000000000
00000000000000000000000000000000

II

I

I~ I

II

I~I

0.016
0.025

I

DD~DD~D

DD~DD~D

I

II

I~DI

I~I

2.290
2.310

I

00000000000000000000000000000000

cooooooooooooooooooooooooooooooo

+

0.240

TOP VIEW

Pin 1

I~

0.290
3.740
3.760

~I

11
I
j.-

0.120
0.170

SIDE VIEW

BOTTOM VIEW

UPDATE1 4.4

26

PACKAGE DIAGRAM OUTUNES

QUAD IN-LINE PACKAGES (Continued)
128-Pln FR-4 Plastic QIP - M42

L...

i

~

~

3.465
3.495

~

·····
..... ..... ........ .... .........
...•............................

I

T

~:~;g ~:~;g D~D~D~D~ ~~~;
! + ,......
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1

0.430

MAX.

1

,

TOP VIEW

Pin 1

0.100
TYP .

.j 1+

••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••

0000000.0000.8 • • • • • • • • • • • • • • • • • •

••••••••••••••••••••••••••••••••
BOTTOM VIEW

UPDATE1 4.4

27

PACKAGE DIAGRAM OUTUNES

QUAD IN-LINE PACKAGES (Continued)
128-Pln FR-4 Plastic QIP - M43

00000000000000000000000000000000

DooooooIDD~D

+

1

0.016
0.025

OB[lDD[lD ::;:
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C::H::J~ DD~D
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•
Pin 1

I'"

2.290

li

2.310

TOP VIEW

0.350·~... ~
MAX.

3.740

3.760"

l8Igggg ggggg ggggg ggggg ggggg ggggg gg

~I

0.120
0.170

SIDE VIEW

l""

D~DD~DD

D~DD~DD2_

Dcc:::JCJcCJD

ooooo~oooooooogo~oQog J
2.410

00000000000000000000000000000000

--.J '--0.100
I r TYP.

BOTTOM VIEW

UPDATE 1 4.4

28

PACKAGE DIAGRAM OUTUNES

QUAD IN-LINE PACKAGES (Continued)
132-Pln FR-4 Plastic QIP - M44

3.280
3.320

~I

.................................
•••••••••••••••••••••••••••••••••

D~DDDDD~D
o
0
D~DDDDD~D ~:

D~DDDDD~D
.................................
•••••••••••••••••••••••••••••••••

,
Pin 1

TOP VIEW

0.368

n
112.080
2.120

2.280
2.320

MAX.

--'~1ffi1Hffil=r=rtmf=fllfflffl==RffH=Hif'~
0.100 -./
TYP.

SIDE VIEW

.J.. o.~

j4-

0.025

0.125
0.175

•••••••••••••••••••••••••••••••••
•••••••••••••••••••••••••••••••••

DD~D~D~DD

DD~D~D~DD
DD~D~D~DD
•••••••••••••••••••••••••••••••••

•••••••••••••••••••••••••••••••••
BOTTOM VIEW

UPDATE1 4.4

29

PACKAGE DIAGRAM OUTUNES

QUAD IN-LINE PACKAGES (Continued)
132-Pln FR-4 Plastic QIP - M45

L
3.490
~~~------------3.510--------------~~~1

..... ............................
'

~

i

t

0.100

TYP.

IIJJ
a:Il ,.
a:Il
IIJJ
IIJJ
" ,1
••••••••••••••••••••••••••'••••••• -I..',

•••••••••••••••••••••••••••••••••

,t

TOP VIEW

' 0.320
MAX.

Pin 1 " , ."

SIDE VIEW

0.015
0.025

•••••••••••••••••••••••••••••••••
•••••••••••••••••••••••••••••••••

DD>[JD
.......
.........................
•••••••••••••••••••••••••••••••••
~

BOTTOM VIEW

30

PACKAGE DIAGRAM OUTUNES

QUAD IN-LINE PACKAGES (Continued)
132·Pln FR·4 Plastic QIP - M46

I~~'--------------3.510--------------~~
................................. =fl
[ l] 'O[[l].
O[[l] ~:~~~

..................................
1
T
3.490

1.590
1.610

1

00=
D [ .l] . '.

i

T
0.100
lYP.

O[ l]
.................................
--'-.
•••••••••••••••••••••••••••••••••
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t

a:o

II]]

TOP VIEW

290
1
11
1.310

0.195 ......
MAX.

Pin 1

SIDE VIEW

0.015
0.025

•••••••••••••••••••••••••••••••••
•••••••••••••••••••••••••••••••••

•••••••••••••••••••••••••••••••••
•••••••••••••••••••••••••••••••••
BOTTOM VIEW

UPDATE1 4.4

31

PACKAGE DIAGRAM OUTUNES

QUAD IN-LINE PACKAGES (Continued)
164-Pln FR-4 Plastic QIP - M47

·
·
'
·
T
-r
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4.090
4.110

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..

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1.890
1.920

ttl

0.100

TOP VIEW

0016
0.026

TYP.

COOOOOOOOOOOOOOOOOOOOOOOOOOODOOOOO
0000000000000000000000000000000000

0000000

ICJIICJIICJIICJIICJIICJIICJIICJIICJIICJIICJIICJIICJIII:JI

0000000,

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BOTTOM VIEW

UPDATE1 4.4

32

PACKAGE DIAGRAM OUTUNES

HEX IN-LINE PACKAGES
66-Pln Ceramic Sidebraze HIP - M48

....~_ _ _ 1.090 - - - - 1... 1
1
MAX.

0.170
0.190

DT

-..1

~

rfl:::==::i--.t.

1.090

MAX.

~_l
t
TOP VIEW

Pin 1

+

--"II'--~~

r--------~~~

•••••••••••
•••••••••••
•••••••••••

0.015
0.025

+
0245

I

MAX.--.J

I_ T

SIDE VIEW

-t
0.590
0.610

•••••••••••
•••••••••••
•••••••••••

--L

BOTTOM VIEW

UPDATE1 4.4

33

PACKAGE DIAGRAM OUTUNES

HEX IN-LINE PACKAGES (Continued)
66-Pln Ceramic Sidebraze HIP - M49

PIN1

~
,r·

1.355.-...1
1.385 .

-I

~:~~~ ~ j....rf1

,,Io""J10··
lc=J
~

1.385

IIlI .

PIN1

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•

•

••

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•

•

:It
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•••
••••
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mt··o.o~~025

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0.100~ '--TYP.-----. . -

ft·
••
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•••
•••
•••
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r- 0.100
TYP.

. 0.200
MAX.

.-;j

MAX.

0.250
MAX .

I..0;590
. ~I
0;610
0.990
1.010

UPDATE14A

34

PACKAGE DIAGRAM OUTUNES

HEX IN-LINE PACKAGES (Continued)
66-Pln Ceramic Sidebraze HIP - MOO

PIN1

L

'" r

1.355
1.385

-..I
- I

1r.D~~D'
lc=J
,.. ....-.
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1.385

0.125
0.135

[I]]

0.100

TYP.--.j ~

tI:
••
•••
•••
•••

PIN1 - . .

.eli)

0.250

MAX.

,..•• .....
•••
••
•••••
••
•••
• e(!)

~:

-

.~

0.990
1.010

UPDATE1 4.4

35

PACKAGE DIAGRAM OUTUNES

HEX IN-LINE PACKAGES (Continued)
66-Pln Ceramic Sidebraze HIP - M51

.
PIN1 --.

'--1.365~
I~
1.395
~I

I 0

0.100
TYP.

100

0.050
MAX.

TOP VIEW

....••• .•...••

....-_ _ _-=:..++..:., 0.100

···1···.,.

••

..t'i)

•••

IIJI • • •
IIJI

:11
III

PIN1

--+

~..

IIJI

(!le.

TYP.

0.245
MAX.
SIDE VIEW

II.
III

••

~'.59r~
0.610

0.990
1.010

BOTIOMVIEW

UPDATE14.4

36

PACKAGE DIAGRAM OUTUNES

PIN GRID ARRAY PACKAGES
121-Pln Ceramic Sidebraze PGA - M52

I.

1.325
00II-'- 1 .355

~

I

T

bI

1.325
1.355

o::n

!CD

!

~
TOP VIEW

~ 1.200 ---+j

I

I

BSe

0000000000000
0000000000000
0000000000000
000
000

888

ggg

0.235 .

MAX.~

--.j

T

0.016
0.020

~ 0.040
c-r
0.060

1j4-""

II

~0.175

MAX.

SIDE VIEW

8881.200

ggg

000
000
0000
000
0000000000000
0000000000000
10000000000000

T

t

j

Bse

..

.

BOTTOM VIEW

Pin A1

UPDATE14.4

37

PACKAGE DIAGRAM OUTUNES

PIN GRID ARRAY PACKAGES (Continued)
121-Pln Ceramic Sidebraze PGA - M53

0.125
0.1.75

-1rrr ~:~:~

jO.100
Bse

..I.
1

0.Q16

0.020
0.280
MAX ..
TOP VIEW

L

r--

1.200--1
BSe ---"I

0000000000000
0000000000000
0000000000000
000
000

ggg
ggg

ggg
ggg

T

SIDE VIEW

1.200
BSe

000
ooo~
0000
000
0000000000000
~oooooooooooo

..,000000000000

T

BOTTOM VIEW

PINA1

UPDATE1 4.4

38

PACKAGE DIAGRAM OUTLINES

SINGLE IN-LINE PACKAGES
3D-Pin Ceramic Sidebraze SIP - M54

0.330
0.360

'Pin1

I_

~0.175
I·~
MAX.

0.007+
0.013

FRONT VIEW

2.970
3.030

II

1
0.420
MAX.

0.010
MAX.

0.015
0.022

UPDATE1 4.4

0.125
0.175

39

PACKAGE DIAGRAM OUTUNES

SINGLE IN-LINE PACKAGES (CONTINUED)
3D-Pin FR·4 Plastic SIP - M55

3.615
3.645

----------~~~I

0.625
0.675
---t-

~ ~01~
trllY1.

0. 495

0.180

0.525

Pin 1

0.125
0.175
0.025
0.055

0.035
0.055

_.1-4--

QJl.QZ.
0.013

SIDE VIEW

TTTTTTTTTTTTTTTTTTTTTTTTTTTTTT
BACK VIEW

UPDATE14.4

40

PACKAGE DIAGRAM OUTUNES

SINGLE IN-LINE PACKAGES (Continued)
36-Pln FR-4 Plastic SIP - M56

L.

I
Pin 1

0.040
0.075

I

4.760

,-

~ ~IIIIII

~

~,

4.780

I,
I

~J.0.100

FRONTVIEW.

TYP.

1_

r-

MAX.

.725

]

0.018

.....~ 0.026

0.305

--.1.-.

. -1-

MAX.

0.007
0.013

SIDE VIEW

DDDDDD~~~
0.040
0.070

BACK VIEW

UPDATE1 4.4

~

41

II

PACKAGE DIAGRAM OUTUNES

SINGLE IN-LINE PACKAGES (Continued)
36-Pln FR·4 Plastic SIP - M57

I

L..
3.590
i'IIr=f------3.61O

Il

I

§

D

0.185

§

11t

I

I

475

TTTTTT.,TTplTTTTTTTTTTTTTTTTTTTTTTTTTTT 0.495
0.035 -+/ \40.015 .1..
---.I j.-0.100
0.070
0.025
TYP
FRONT VIEW

II
§

I

.

_I

MAX. ~

•.

.

L

~

rTIl
~.~~; ~
.
SIDE VIEW

I§ 1£

0.040

l

0.060

iiTiTTiTTTiiTT TiiTT iiiTT TiiTTiiiTTiiLWBACK VIEW
~
0.120
0.175
4O-Pln FR·4 Plastic SIP - M58

I'"

D~
t
Pin 1

.• 1

4.005
4.035

ElD~D~

~~

0.035
0.075

-1 h

0.100
TYP.

-0.650
0.710

i.

-h

0.015
0.022

rn

0.180...-1
0.220 I

0.025
0.055

0.125
0.175

0.495
0.525

1.-...

r-

~

gg~~ .~
SIDE VIEW

FRONT VIEW

UPDATE1 4.4

42

PACKAGE DIAGRAM OUTUNES

SINGLE IN-LINE PACKAGES (Continued)
4O-Pln FR-4 Plastic SIP - M59

I"

::~~~ ---~~I

ii========r~-;===D===;-!;l-;::=::::;D:--;===§D====;---r===§D====;i - 0 . 6 5 0
1'n::n::n::;;:;;:;;:;=;::hn';;:i'i"Fii'iJii""i'i:i'i:l-u~~'iFi"i'iFi~..ri:n:n:n::n::n::r;:;;'l .i. 0.710

Pin 1

~ '--l
II II

0.035
0.075

--'Ih

-II.-,
~II

-I

0.100
TYP.

0.015
0.022

0.025
0.055

0.125
0.175

~:~~~ ~ ~
0.495
0.525

[I]

~

0.007
I
0.013 . .14-

SIDE VIEW

FRONT VIEW

II

45-Pin FR-4 Plastic SIP - M60

SIDE VIEW

BACK VIEW

UPDATEl 4.4

43

PACKAGE DIAGRAM OUTUNES

SINGLE IN-LINE PACKAGES (Continued)
45·Pln FR·4 Plastic SIP - M61

BACK VIEW

UPDATE 1 4.4

44

PACKAGE DIAGRAM OUTUNES

DUAL SINGLE IN-LINE PACKAGES
2S·Pln FR·4 Plastic DSIP - M62

~ 1.390

r-- 1.410

---.I
------.

0.70~DD·
MAX~

./' ~14- ¥

Pin 1

0.100
TYP.

0.015
0.025

l-

0.285-+/
MAX.

1
LO.125
0.175

j.-

0.100
TYP ....

SIDE VIEW

FRONT VIEW

BACK VIEW

36·Pln Ceramic Sidebraze DSIP - M63
0.230

'1rr71i

1.780

rJ

1.'ii2O

----r~~=

0.100 ____
TYP.

0.007
'D.irl]

0.060

FRONT VIEW

UPDATE1 4.4

45

PACKAGE DIAGRAM OUTLINES

DUAL SINGLE IN-LINE PACKAGES (Continued)
aa-Pin Ceramic Sidebraze DSIP - M64

I~

«~
MAX.

~I

M~
MAX.

p~~lL-.L.'I.-r

0.075
MAX.

I III

~

0.035
0.055

~

r-JI- ~-'- - 4~~;

0.100
TYP.

0.015
0.025

FRONT VIEW

0010
_.0.040

----.I I.- 0.270
- I I - MAX.

"1

H

0 360
.
MAX

+I ~0.100
~TYP.
0.007
0.013
SIDE VIEW

UPDATE1 4.4

46

PACKAGE DIAGRAM OUTUNES

ZIG-ZAG IN-LINE PACKAGES
42-Pln FR-4 Plastic ZIP - M65

r

~I

2.630
2.650

~oI I~~~,~IL.-/"'...j ~ --I" -.jj4-

Pin 1

0.100
TYP.

0.015
0.025

LO.125
0.190

0.050
TYP.

~

1+-0.350

I~li'

A

MAX.

0.100
TYP.

FRONT VIEW

BACK VIEW

52-Pin FR-4 Plastic ZIP - M66

3.040

14----3.060'----~

Pin 1

TYP.

~

0.050 ,0.015
TYP.O.025
TOP VIEW

'------- 0.345

1C~

0.640
0.660

-.114-

------I

0.125
0.190

BOTIOMVIEW

UPDATE1 4.4

47

PACKAGE DIAGRAM OUTUNES

ZIG·ZAG IN·LlNE PACKAGES (Continued)
64·Pln FR·4 Plastic ZIP - M67

I"
~::~
"I
DflDflDflDy~
--I~"'-=-r
FRONT VIEW

0.100

0.050

TYP.

TYP.

0.125
0.190

SIDE VIEW

64·Pin FR·4 Plastic ZIP - M68

I"
~::~
"I
DflDflDflqJ~.
--i~"'-=-r
FRONT VIEW

0.100

0.050

TYP.

TYP.

UPDATE1 4.4

0.125
0.190

~.

'-----0.350

~I~IMAX.

...... ...-0.100
TYP.
SIDE VIEW

48

PACKAGE DIAGRAM OUTUNES

ZIG-ZAG IN-LINE PACKAGES (Continued)
75-Pin FR-4 Plastic ZIP - M69

I..

2.640

~I

2.660

D~D~D~D~. I~::
PIN1

+-0.015

~I--o.orr

0.023
TOP VIEW

TYP 0.090
0.120

~
BACK VIEW

UPDATE 1 . 4.4

--..j

1..-

-io::
0 .180

TYP

SIDE VIEW

II

PIN1

49

PACKAGE DIAGRAM OUTLINES

SINGLE IN-LINE MEMORY MODULES
64·Pln FR·4 Plastic SIMM - M70

Module Dimensions for Package M70 are not yet finalized.
Please consult the factory for furth~r details.

64·Pln FR·4 Plastic SIMM - M71

3.840
3.860
~___________________ 3.580
3.588

0.260

0~280.

I

.350
-+I 1+0MAX.

0.510
0.530

0.390
0.410
'"f1......................................................~
..I~I4-L.....-... """-

0.045
0.055

0.050
Pin 1

FRONT VIEW

TYP.

BACK VIEW

UPDATE.1 -4.4

50

PACKAGE DIAGRAM OUTUNES

SINGLE IN-LINE MEMORY MODULES (Continued)
64-Pln FR-4 Plastic SIMM - M72

3.840
3.860
3.580

14-----------3 .588 :....---------~

0.360

0~380.

Jl

-.j

0.610
0.630

0.390
0.410

~0.330

~"""..LLLLLLJ~"""".&&.aJLLLlcu.JI~-""...JL-

MAX.

0.045
0.055

0.050
FRONT VIEW

Pin 1

!

TYP.

1~[=::J[lCJ~[=:J

."'. "" , '" "

'" "

' " " • ' " " r'\1I1! "

'" " '" "

" "

" '" "

III I!

BACK VIEW

72-Pln FR-4 Plastic SIMM - M73

4.240
~~'------------4.260---------~

I

~

3.974----------~~

:~ I.; CJ~ [<--__-'T
0.245
0.255

I'

PIN 1

~

94

---l, ,'-------'

L - ,_ _

FRONT VIEW

I I , , " ' " I I ' " 11111"'" 11111.11" I I

("")

:!i:

~LlllJWUW1l.LIUIII.U.ll.UULI~~--' - -

11"".-"""

t~:

0.055

SIDE VIEW

,

II'" '"'' '"" III,,' II

BACK VIEW

PIN 1

UPDATE 14.4

51

PACKAGE DIAGRAM OUTLINES

SINGLE IN-LINE MEMORY MODULES (Continued)
ao-Pin FR-4 Plastic SIMM - M74

0.390
0.410

FRONT VIEW

I,~"D",D""D",D""D",D""D,:)

SIDE VIEW

~

BACK VIEW

PIN 1

aO-Pin FR-4 Plastic SIMM - M75

I.
~:~~~~r~~1I I~I :r~ I~l lci~ill
4.640

~I

4.660

0390

0.240
0.260

i

11111111111111111111111111111111111111" 11111111111111111111111111111111111111
0.250
~
--.ji4-0.050

PIN 1

1-- TYP

TYP

FRONT VIEW

r~

-+\

0 .210

MAX

0.41 0
-+11---0.045
0.055
SIDE VIEW

~t
0

IOUIlIUIIIUIllIIUUIIIUIIIIIIIIIIII

A

110111111111001118111111011111

BACK VIEW

PIN 1

UPDATE 1 4.4

52

PACKAGE DIAGRAM OUTUNES

SINGLE IN-LINE MEMORY MODULES (Continued)
8O-Pln FR-4 Plastic SIMM - M76

4.640
~--------4.660 --------~

~--------4.3~--------~~
4.394

-+I

,

0.550
0.570

0 .350
1+MAX.

-----I '---

0.045

~r- 0.055

0.240
0.260

SIDE VIEW

!

!

II

lo~!
I
I~I
I
I~o~
I.URI.RmlmIUUm.I." .. ~ 1IIIIIIIIIIInnljRIDRIIIDIIUIII
BACK VIEW

t

PIN 1

UPDATE1 4.4

53

1990/1991 LOGIC DATA BOOK

1991 DATA BOOK UPDATE 1
TABLE OF CONTENTS
LAST BK.

UPDATE PG.

1990/91 LOGIC DATA BOOK UPDATES
PARTIALLY UPDATED DATA SHEETS
IDT54/74FCT240T
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT241T
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT244T
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT540T
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT541T
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT299T
8-lnput Universal Shift Register w/Common Parallel I/O Pins ............
IDT54/74FCT399T
Quad Dual-Port Register. ....................................................................
IDT54/74FCT543T
Non-inverting Octal Latched Transceiver. ...........................................
IDT49FCT804
High-Speed Tri-Port Bus Multiplexer ..................................................
IDT54/74FCT240
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT241
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT244
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT540
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT541
Inverting Octal Buffer/Line Driver ........................................................
IDT54/74FCT299
8-lnput Universal Shift Register w/Common Parallel I/O Pins. ...... .....
IDT54/74FCT399
Quad Dual-Port Register. ....................................................................
IDT54/74FCT543
Non-inverting Octal Latched Transceiver........ ..... ...... ..... ..... ..... ..... .....

A6.10 ...........
A6.10 ...........
A6.10 ...........
A6.10 ...........
A6.10 ...........
A6.13...........
A6.17...........
A6.19...........
A6.29...........
A6.40 ...........
A6.40 ...........
A6.40 ...........
A6.40 ...........
A6.40 ...........
A6.43... ........
A6.47...........
A6.49... ..... ...

A-2
A-2
A-2
A-2
A-2
A-3
A-5
A-5
A-6
A-8
A-8
A-8
A-8
A-8
A-8
A - 10
A - 11

UPDATED FULL DATA SHEETS
IDT73210
Fast Octal Register Transceiver w/Parity ............................................
IDT73211
Fast Octal Register Transceiver w/Parity .............................................
IDT49C466
64-Bit CMOS Flow-ThruEDC Unit... ....................................................
lOT49FCT805A
Buffer/Clock Driver w/Guaranteed Skew....... ...... ......... ..... .... .............
IDT49FCT805
Buffer/Clock Driver w/Guaranteed Skew............................................
lOT49FCT806A
Buffer/Clock Driver w/Guaranteed Skew... ..... ..... ...... ...... ...... ..... ..... ...
IDT49FCT806
Buffer/Clock Driver w/Guaranteed Skew ............................................
IDT54/74FBT2240A
Inverting Octal Buffer/Line Driver w/25Q Series Resistor ...................
IDT54/74FBT2240
Inverting Octal Buffer/Line Driver w/25Q Series Resistor ...................
IDT54/74FBT2244A
Inverting Octal Buffer/Line Driver w/25Q Series Resistor ...................
IDT54/74FBT2244
Inverting Octal Buffer/Line Driver w/25Q Series Resistor ...................
IDT54/74FBT2373A
Octal Transparent Latch w/3-State and 25Q Series Resistor .............
IDT54/74FBT2373
Octal Transparent Latch w/3-State and 25Q Series Resistor .............
IDT54/74FBT2841A
10-Bit Memory Latch w/25Q Series Resistor ......................................
IDT54/74FBT2841
10-Bit Memory Latch w/25Q Series Resistor ......................................

A5.9.............
A5.9.............
A5.13 ...........
A6.30 ..... ......
A6.30 ...........
A6.30..... ......
A6.30 ...........
A6.67...........
A6.67...........
A6.68...........
A6.68 ...........
A6.69...........
A6.69...........
A6.71 ...........
A6.71 ...........

A - 14A - 14
A-3D
A-54
A-54
A-54
A-54
A - 61
A - 61
A - 67
A - 67
A - 73
A - 73
A - 80
A - 80

NEW DATA SHEETS AND APPLICATION NOTES
IDT54/74FCT826T
8-Bit Inverting Register w/Multiple Enable .................................................................. A - 88
AN-82
Clock Distribution Simplified wilDT Guaranteed Skew Clock Drivers ........................ A - 95
AN-84
IDT49FCT804 Tri-Port Bus Multiplexer ....... :.............................................................. A - 106

1991 LOGIC DATA BOOK

Partial Changes to Data Sheets

The following section contains partial data sheets that appeared in the 1991 LOGIC Data Book. These data sheets
had changes to less than 50% of the overall contents. Re.fer to the bars above changes to see where that section
can be found in the 1991 LOGIC Data Book.

UPDATE1 A

IDT54/74FCT240T/AT/CT,IDT54/74FCT241T/AT/CT
IDT54/74FCT244T/AT/CT, IDT54/74FCT540T/AT/CT
IDT54/74FCT541T/AT/CT

Data Book A, Section 6.10, Page 2

PIN CONFIGURATIONS
IDT54174FCT240T

IDT54174FCT241T/244T

Vee

OEA

OEB

DAo
OBo
DA1

16

OAo
DBo
OA1

iliililll ::
13

9
10

OEA
DAo
OBo
DA1

2
3
4

OB1

5

DA2
OB2

7

DA3
OB3
GND

18

6

P20·1
020·1

8

E20-1

17

OEB"

Do

OAo
DBo

01
02

OA1
DB1

03
04

18

4

P20·1
020·1

17
16

5

DB1

DA2

OA2

OB2

6x§9?Q;f, 15
7 )$.2gP.$.l 14

DB2

DA3

8

12

OA3

11

DB3

OB3
GND

OM

05

13

DB2

06

9

12

OA3

07

10

11

DB3

GND

&
E20-1

DIP/SOldliiwCERPACK
TOP VIEW

IDT54/74FCT240T/AT/CT, IDT54/74FCT241T/AT/CT
IDT54/74FCT244T/AT/CT,IDT54174FCT540T/AT/CT
IDT54174FCT541T/AT/CT

Vee

OEA

Vee
2
3

OB1

DIP/50Ic#w.lVlcERPACK
TOP VIEW

•

IDT54174FCT540T/541T

2
3

OEB
18

17
P20·1
020·1 16
6 5020·2 15
:§~; 14
7
&
8 E20-1 13
12
9

00"

4

01"

5

02*
03"

10

11

04"
Os"
06"

Ot'

DIP/SOIOI.EmiicERPACK
.
iofi\iiEW

Data Book A, Section 6.10, Page 6

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT240T

tPLH
tPHL

!PHZ
!PLZ

Propagation Delay
ON to ON

RL =5000

Output Enable Time

1.5

10.0

1.5

10.5

1.5

6.2

1.5

6.5

Output Disable Time

1.5

9.5

1.5

10.0

1.5

5.6

1.5

5.9

IDT54174FCT240T/AT/CT,IDT54174FCT241T/AT/CT
IDT54174FCT244T/AT/CT,IDT54174FCT540T/AT/CT
IDT54174FCT541T/AT/CT

Data Book A, Section 6.10, Page 8

ORDERING INFORMATION

x
Package

P
D
1...-------1 SO
L

,S",

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

exI:ij]lII
UPDATE1 A

2

IDT54/74FCT299T/AT/CT

Data Book A, Section 6.13, Page 1

. DESCRIPTION:

FEATURES:
• IOT54/74FCT299T equivalent to FAS"fI"M speed
• IOT54174FCT299AT'250/0 faster than FAS"fI"M

.1fIB••~111fililrlijfft.IEJ

The IOT54/74FCT299T and IOT54/74FCT299Ar.. are
built using advanced CEMOSTM. a dual-metal CMOS technology.

IDT54/74FCT299T/AT/CT

Data Book A, Section 6.13, Page 2

PIN CONFIGURATIONS
So
OEl
OE2
1/06
1/04
1/02
1/00
00

MR
GND

Vee

Sl

2

P20-1
020-1

3
4
5

,,,,§P2Bi1,,.

6
7

E20-1

8

OS7
07
1/07
1/05
1/03
1/01

9

CP

10

DSo

~1fitJt!Q.l

&

DIP/soldliliii~ERPACK
TOP VIEW

UPDATEl A

3

IDT54/74FCT299T/AT/CT

Data Book A, Section 6.13, Page 5

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

tPLH
tPHL

Propagation Delay
CP 10 000r07

tPLH
tPHL

Propagation Delay
CPto liOn

2.0

12.0

2.0

12.0

2.0

7.2

2.0

tPHL

Propagation Delay
MR to 00 or 07

2.0

10.0

2.0

10.5

2.0

7.2

2.0

tPHL

Propagation Delay
MRto lIOn

2.0

15.0

2.0

15.0

2.0

8.7

2.0

tPZH
tPZL

Output Enable Time
OEnto liOn

1.5

11.0

1.5

15.0

1.5

6.5

1.5

tPHZ
tPLZ

Output Disable Time
OEnto liOn

1.5

7.0

1.5

9.0

tsu

Set· up Time HIGH
or LOW
So or Sl to CP

7.5

7.5

tsu

Set· up Time HIGH
or LOW liOn,
DSo or DS7 to CP

5.5

5.5

4.0

4.5

tH

Hold Time HIGH
or LOW
So or Sl to CP

1.0

1.0

1.0

1.0

tH

Hold Time HIGH
or LOW liOn,
DSo or DS7 to CP

1.5

1.5

1.5

1.5

tw

CP Pulse Width
HIGH or LOW

7.0

7.0

5.0

6.0

7.0

7.0

5.0

6.0

7.0

7.0

5.0

6.0

tw

Width

tREM

Recovery Time
MRto liOn

IDT54/74FCT299T/AT/CT

Data Book A, Section 6.13, Page 7

ORDERING INFORMATION
x
X
Device Type

Package

P
D
' - - - - - - - - - - l SO
L
E

J1KI

UPDATEl A

Plastic DIP
CERDIP
Small Outline IC
Leadless C hip Carrier
CERPACK

::~ltiM

4

Data Book A, Section 6.17, Page 2

IDT54/74FCT399T/AT/CT

PIN CONFIGURATION
S

Vcc

OA

00

lOA

100

hA
he

110
he
loe

lOB
OB
GND

Oe
CP

DIP/SOI4./IDlPERPACK
TOP VIEW

Data Book A, Section 6.17, Page 7

IDT54/74FCT399T/AT/CT

ORDERING INFORMATION

x
Package

Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC

K

Data Book A, Section 6.19, Page 1

IDT54/74FCT543T/AT/CT

FEATURES: .

UPDATE1 A

5

Data Book A, Section 6.19, Page 2

IDT54/74FCT543T/AT/CT

PIN CONFIGURATIONS
Vee
CEBA
Bo
B1
B2
B3
B4
Bs
Bs
B7

LEBA
OEBA
Ao
A1
A2
A3
A4
As
As
A7
CEAB
GND

LEAB

OEAB

DIP/SOIC/CERPAcK{EfAJ
TOP ViEW·'·'·,·,·,·,·,·,·,·,··. . ·

Data Book A, Section 6.19, Page 5

IDT54/74FCT543T/AT/CT

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

tPHL
tPLH
tPHL

Ci. = SOpF

Propagation Delay
Transparent Mode
An 'to Bn or Bn to An
I

RL = soon
8.0

2.5

9.0

2.0

Bn

tPZH
tPZL

Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn

tPHZ
tPLZ

Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn

tsu

Set·up Time, HIGH or LOW
An or Bn to LEBA or LEAB

3.0

3.0

2.0

2.0

tH

Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB

2.0

2.0

2.0

2.0

5.0

5.0

5.0

5.0

tw

Pulse Width
LOW

IDT49FCT804/A/C

Data Book A, Section 6.29, Page 1

FEATURES:

UPDATE1 A

6

IDT49FCT804/A/C

Data Book A, Section 6.29, Page 2

I

PIN CONFIGURATION
GND

C7

C8
C9
RAMrn=
S1
So
Po

C6
C5

ITc

crs

rEA
BI
Be
137

A1

~

Po
M

Bs

Vee

Vee

Bs

GND

GND

Ib
81
B2
Bl
El4
DAB
DeB
DeA

P9
flB

A7
P6'

P6
DEc

DEB
DEA
C4

Co

C1

C3

C2

GND
DIP
TOP VIEW

IDT49FCT804/A/C

Data Book A, Section 6.29, Page 6

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

CL=SOpF
RL = soon
.1.5

14.4

12.0

1.5

13.2

11.0

1.5

14.4

12.0

1.S

10.8

9.0

1.5

13.0

11.S

8.0

1.5

10.0

9.0

7.7

UPDATE1 A

7

IDT49FCT804/A/C

Data Book A, Section 6.29, Page 8

ORDERING INFORMATION

x
Package

P
'---------1J

Plastic DIP
Plastic Leaded Chip Carrier

.;~@iMllMMsm!Erl~]l!l,~l:t
IOT54/7 4FCT2401 A/C, IDT54/7 4FCT241 lAIC
IDT54/7 4FCT2441 A/C, IDT54/7 4FCT5401 A/C
IOT54/74FCT541 lAIC

Data Book A, Section 6.40, Page 6

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT240{l,-=)

tPlH
tPHl

Propagation Delay
ONto ON
Output Enable Time
Output Disable Time

Data Book A, Section 6.43, Page 1

IOT54/74FCT299/A/C

FEATURES:
• IDT54/74FCT299 equivalent to FAS"fTM speed
• IDT54/74FCT299A 25% faster than FASTTM

~m:J~T.iE• •'''JilI$iir:lbiij:Jii.$J!llWtmlI

DESCRIPTION:

The IDT54/74FCT299 and IDT54/74FCT299~§@are built
using advanced CEMOSTM, a dual-metal CMO§..\echnology.
The IDT54!74FCT299 and IDT54/74FCT299"::are 8-input
universal shift/storage registers with 3-state outputs.

UPDATEl A

8

IDT54174FCT299/A/C

Data Book A, Section 6.43, Page 5

NG CHARACTERISTICS OVER OPERATING RANGE

tPLH
tPHL

Parameter
Propagation Delay
CPtoQoor07

tPLH
tPHL·

Propagation Delay
CPto liOn

2.0

12.0

2.0

12.0

2.0

7.2

2.0

tPHL

~agation

Delay
MRto 00 orQ7

2.0

10.0

2.0

10.5

2.0

7.2

2.0

tPHL

Propagation Delay
MRto liOn

2.0

15.0

2.0

15.0

2.0

8.7

2.0

tpZH
tPZL

Output Enable TIme
OEnto liOn

1.5

11.0

1.5

15.0

1.5

6.5

1.5

tPHZ
tPLZ

Output Disable Time
OEnto lIOn

1.5

7.0

1.5

9.0

tsu

Set·up Time HIGH
or LOW
SoorS, to CP

7.5

7.5

tH

Hold Time HIGH
or LOW
SoorS, to CP

1.0

1.0

1.0

1.0

tsu

Set·up Time HIGH
or LOW lIOn, DSo
or DS7to CP

5.5

5.5

4.0

4.5

tH

Hold Time HIGH
or LOW lIOn, DSo
or DS7 to CP

1.5

1.5

1.5

1.5

7.0

7.0

5.0

6.0

7.0

7.0

5.0

6.0

7.0

7.0

5.0

6.0

CL=50pF
At =5000

tw
tw
tREM

Width
Recovery Time
MRtoCP

IDT54174FCT299/A/C

II

Data Book A, Section 6.43, Page 7

ORDERING INFORMATION

x
Device Type

299

' - - - - - - - - - - - - 1 299A

S·lnput Universal Shift Register
FastS·lnput Universal Shift Register

i,itMi¥W~al111~1~tmn~~1I~tlwl\.~~
UPDATE 1 A

9

Data Book A, Section 6.47, Page 1

IDT54/74FCT399/A/C
FEATURES:

DESCRIPTION:

• IDT54/74FCT399 equivalent to FASTTM speed
• IDT54174FCT399A 30% faster than FASTTM

. The IDT54174FCT3991J\lm!arehigh-speed quad dual-port
registers.

:~1iin'-X.{\~It_e1Dffl'.~f:jlll!i~'~A$imjI t:?

Data Book A, Section 6.47, Page 5

IDT54/74FCT399/A/C

tPHL

Propagation
CPto an

tsu

Set-up Time
HIGH or LOW
Into CP

tH

Hold Time
HIGH or LOW
Into CP

tsu

Set-upTime
HIGH or LOW
Sto CP

9.0

tH

Hold Time
HIGH or LOW
StoCP

0

9.5

8.5

9.0

0

0

0

tw

Data Book A, Section 6.47, Page 7

IDT54174FCT399/A/C
ORDERING INFORMATION

xxxx
Device
Type

UPDATE1 A

10

Data Book A, Section 6.49, Page 1

IDT54/74FCT543/A/C

FEATURES:

DESCRIPTION:

• IDT54/74FCT543 equivalent to FAST"M speed
• IDT54n4FCT543A 25% faster than FAST"M

The IDT54174FCT543/.qgjis a non-inverting octal transceiver built using advanced CEMOSTM, a dual metal CMOS
technology.

!B:lfiiiQ'fD.lIiiblk'VIlW;lliiib.Ieii.$I!BItI

Data Book A, Section 6.49, Page 2

IDT54/74FCT543/A/C

PIN CONFIGURATIONS

LEBA
OE8A
Ao
A1

A2
A3
A4
As
A6
A7

CEAB
GND

2
3
4
5
6
7

16
15

Vee
CE8A
80
81
82
83
84
85
86
87

13

OEAB

P24-1,

B
9

10
11
12

m:s

DIP/SOIc/CERPAC~
TOP VIEW
c

Data Book A, Section 6.49, Page 3

IDT54/74FCT543/A/C

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLe = 0.2V, VHe = Vee - 0.2V
Commercial: TA = DoC to
Vee = 5.0V ±
Military: TA = -55°C to +125°C Vee = 5.0V± 10%
Output HIGH Voltage
VIN = VIH or VIL

UPDATE1 A

11

IDT54/74FCT543/A/C

Data Book A, Section 6.49, Page 5

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

tPHL

Propagation Delay
Transparent Mode

Q=50pF
RL = soon

An to Bn or Bn to An
tPLH
tPHL

Propagation Delay
LEBA to An, LEAB to Bn

8.0

2.5

tPZH
tPZL

Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to Anor Bn

9.0

2.0

tPHZ
tPLZ

Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn

tsu

Set-up Time, HIGH or LOW
An or Bn to LEBA or LEAB

3.0

3.0

2.0

2.0

tH

Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB

2.0

2.0

2.0

2.0

5.0

5.0

5.0

5.0

tw

Pulse Width
LOW

IDT54174FCT543/A/C

,

Data Book A, Section 6.49, Page 7

ORDERING INFORMATION

xxxx

X

x

Device
Type

Package

Process

Commercial
MIL-STD-883, Class B
Plastic DIP
CERDIP
Leadless Chip Carrier
Small Outline IC
CERPACK
Chip Carrier

UPDATE1 A

12

1991LOGIC DATA BOOK

Changes to Full Data Sheets

The following section contains full data sheets that appeared in the 1991 LOGIC Data Book. These data
sheets had changes to 50% or more of the overall contents and are now considered new. Refer to the bar at
the top of each page to see where that page can be
found in the 1991 LOGIC Data Book.

UPDATE1 A

13

IDT73210A/11A

Data Book A, Section 5.9, Page 1

~ ~@

PRELIMINARY
IDT73210/A
IDT73211/A

FAST CMOS OCTAL
REGISTER TRANSCEIVER
WITH PARITY

IntegJateci DevIce Tedmolo&),. IDe.

FEATURES

• Even parity generation from Port B to Port A
• Parity polarity control
• High output drive capability: 64/48mA (commerciall
military)
• Available in 32-pin sidebraze DIP and surface mount
32-pin SOJ packages
• High-speed, low-power, CEMOSTM process technology
• Military product compliant to MIL-STD-883, Class B

• Two bidirectional interfacing ports
• Single-level pipeline register for one port and one-level
(73211) or two-level (73210) pipeline register for the
other port
• 8-bit wide interface ports plus parity bit
• Even parity checking in both directions
• Even/odd parity generation from Port A to Port B

IDT73210 FUNCTIONAL BLOCK DIAGRAM
Ao-a

PERRB

t
AEN

CP

-rL

Vee GND2--1l

I

t

1 }3

POWER
SUPPLY

REGZ

REG X
QXo-a

9

I

9
POLARITY

MUX

9

1

I

Even/Odd
IEven Parity
Parity
Check
Generation

Icom~le.ment
anty

9

MUX

Even Parity
Check

9

Even Parity
Check

Even ,I
Parity
Generation

9

9

Wo-a

QYo-a

I

LATCH

L REGY ~
r

wI

j

LE

I?
PERRA

BnF

I

;
Bo-a

1

DX

SEL

0

f
2594 drw la

CEMOS Is a 1rademark of IntO\lratad Device Technology Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

APRIL 1991
DSC-tI035I.

C>1991 Integratad Device TechnologY,lnc.

UPDATE1 A

14

IDT73210A/11A

Data Book A, Section 5.9, Page 2

10173211 FUNCTIONAL BLOCK DIAGRAM
A0-8

AEN

PERRB

Vee GND2-o

--r-'----,

CP-'--~

L ......_I--~I-----BEN
aX0-8
9

POLARITY

-:----+--.----,
9

Even Parity Even/Odd
Check
Parity
Generation

Even Parity
Check
9

9

9

( 4 - -........+-LE

~-------~~.SEL

L..-----,r------'

2594 drw lb

PERRA

BOE

B0-8

UPDATE1 A

15

IDT7321 OA/11 A

Data Book A, Section 5.9, Page 3

low~to-high CP transition. The output data bus is Ao-a and is
enabled when AOE is low. When SEL is high, there is only a
one clock cycle latency.
When SEL is low, the incoming data is latched into Register
Y on the low-to-high CP transition, when BEN is low. Even
parit~ of the registered data is checked. If PERRB goes high,
FUNCTIONAL DESCRIPTION
The IDT73210/1 Octal Register Transceivers are high- a panty error has occurred. Even parity (OYs) is generated on
speed, low-power data interface with data integrity checking the contents in RegisterY. When BEN is low, the contents of
register Yare transferred to Register Z on the low-to-high CP
capability.
transition.
When BOE is low, the content of RegisterZ is made
They are designed for high-performance systems requiring
bidirectional data transfer between two buses and maintain- available at output Port A. When SEL is low, there is a two
clock cycle latency.
ing error checking via parity.
pon 8 to pon A Path (IDT73211) is comprised of latch
In any RISC or CISC microprocessor system, the
(W),latch
(Y), register (Z), an even parity generator/checker
IDT7321 0/1 can be used to interface cache memory with main
memory. Data integrity is ensured through parity checking. and a parity bit latch complementor. The input data bus is on
Control features allow dynamic reconfiguration of the Bo-s lines.
When SEL is high, the incoming data is latched into Latch
check/generate and odd/even parity options.
W. When LE is high, Latch W is transparent; when LE is low,
Latch W is closed. The parity bit, Bs, can be complemented
DETAILED FUNCTIONAL DESCRIPTION
pon A to pon 8 Path (IDT73210 and IDT73211) is by the POLARITY pin. If POLARITY is low, the parity sense
comprised of a register (X), an even/odd parity generator and remains the same. If POLARITY is high, the parity sense is
an even parity checker. The input data is on the AO-8 lines. complemented. Parity is not generated in this path. Even
When AEN is low, Ao-s is latched into Register X on the low- parity of latched data is checked; If PERRB goes high, a parity
to-high CP transition. Even parity of the latched data is . error has occurred. When BEN is low, Wo-a is latched into
checked. If PERRA goes high, a parity error has occurred. A Register Z on the low-to-high CP transition. The previous
new parity bit, Bs, is generated. The output data bus is Bo:s contents are held in Register Z if BEN is high or if there is no
low-to-high CP transition. The output data bus is Ao-s and is
and is enabled when BOE is low.
pon 8to pon A Path (IDT73210) is comprised of a latch enabled when AOE is low. When SEL is high, there is only a
(W), two registers (Y and Z), an even parity generator/checker one clock cycle latency.
When SEL is low, the incoming data is latched into Latch Y
and a parity bit latch complementor. The input data bus is on
when
LE is high. Latch Y is closed when LE is low. Even parity
the Bo-s lines.
When SEL is high, the incoming data is latched into Latch of latched data is checked. If PERRB goes high, a parity error
W. When LE is high, Latch W is transparent; when LE is low, has occurred. Even parity (Ys) is generated on the contents
Latch W is closed. The parity bit, Bs, can be complemented in Latch Y. When BEN is low, the contents of Latch Yare
by th~ POLARITY pin. If POLARITY is low, the parity sense transferred to Register Z on the low-to-high CP transition.
remains the same. If POLARITY is high, the parity sense is When BOE is low, the content of Register Z is made available
complemented. Parity is not generated in this path. Even at output Port A. When SEL is low, there is a one clock cycle
parityofiatched data is checked. If PERRB goes high, a parity latency.
The power pins are Vcc and GNDo-2. GNDo is internal quiet
error has occurred. When BEN is low, Woos is latched into
Register Z on the low-to-high CP transition. The previous ground, GNDl is Port B ground and GND2 is Port A ground.
contents are held in Register Z if BEN is high or if there is no

APPLICATIONS

• Cache memory bus interface
• Read and write buffers for RISC microprocessor system
• Registered transceiver with parity

UPDATE1 A

16

IOT7321 OA/11 A

Data Book A, Section 5.9, Page 4

PIN CONFIGURATIONS(1)
BEN
BOE
Bo
Bl
B2
B3
B4
GNDo
GNDI
B5

B8
PERRB
LE
CP

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

31

SEL
AOE
Ao
Al

A2
A3
P32-2.
C32-2

25
24
23
22
21

&

8032-2

19
18
17

A4
Vee
GND2

As
A6

A7
As
PERRA
AEN
POLARITY
2594 drw02

DIP/SOJ
TOP VIEW
NOTE:

1. GNDo is internal quiet ground
GND1 is B Port ground
GND2 is A Port ground

II

PIN DESCRIPTIONS
Pin Nama

110

A0-8

110

AEN
AOE

I

B0-8
BEN
BOE
LE

1/0
I
I
I

SEL

I

POLARITY

I

PERRA
PERRB
CP
Vee
GND0-2

I

0
0
I

Description
Data Port A.
Clock enable (active low) for the register X.
3-state output enable.for Port A.
Data Port B.
Clock enable (active low) for the registers Y and Z.
3-state output enable for Port B.
Latch enable inpulfor Latch Y/Latch Wof Pori B. The Latch YlLatch W is open when LE is high. Data is latched
on the high-to-low transition of LE.
Input selection for Port B.
SEL = 0 Register Y (73210); 8EL = 1 Latch W
SEL = 0 Latch Y (73211 );
Polarity selection input.
Polarity
A to B Diraction
0
EVEN
1
ODD

B to A Direction
Pass Parity
Complement Parity

Parity output error for Pori A.
Parity output error for Pori B.
Input clock.
+5 volts.
Ground.
259411>101

UPDATE.1 A

17

IDT7321 OA/11 A

Data Book A, Section 5.9, Page 5

OPERATING MODES SUMMARY
IDT73210/1 A TO B DIRECTION
Output
Input
A0-8

Reg. X

PERRA

A0-8 ~QX0-8 Result of even
(CP = La to Hi) parity check
(AEN = 0)

(Ba)

B0-8

Even/odd parity bit
Bs = POLARITY XOR
Even parity generate
from QX0-7

QX0-8~

B0-8
(BOE = 0)

25941b102

IDT73210/1 B TO A DIRECTION WHEN SEL = 1
Reg.Z
Input
B0-8

Latch W
B0-8 ~ W0-8
(LE = 1)

PERRB
Result 01 even
parity check

(QZa)
Bit complemented
by POLARITY
(Even/odd parity
translation)

IDT73210 B TO A DIRECTION WHEN SEL

Output
QZ0-8

(Aa)

A0-8

W0-8 ~QZ0-8
(CP = La to Hi)
(BEN = 0)

As = POLARITY XOR
Ws

QZ0-8 ~A0-8
(AOE = 0)

25941b103

=0
Reg.Z

Input
B0-8

Reg. Y

PERRB

B0-8 ~QY0-8 Result of even
(CP = La to Hi) parity check
(BEN = 0)

Output

(QZa)

QZ0-8

(Aa)

A0-8

Even parity generated
bit

QY0-8 ~ QZ0-8
(CP = La to Hi)
(BEN = 0)

As = Even parity
generated from QY0-7

QZ0-8 ~A0-8
(BOE = 0)

25941b104

IDT73211 B TO A DIRECTION WHEN SEL = 0
Reg.Z
Input
B0-8

Latch Y
B0-8 ~ Y0-8
(LE = 1)

PERRB
Resu~

of even
parity check

Output

(QZa)

QZ0-8

(Aa)

Even parity generated
bit

Y0-8 ~QZ0-8
(CP = La to Hi)
(BEN = 0)

As = Even parity
generated from Y0-7

A0-8
. QZ0-8 ~ A0-8
(BOE = 0)
25941b105

UPDATE1 A

18

IDT7321 OA/11 A

Data Book A, Section 5.9, Page 6

CACHE
MEMORY

R3000

t---

34

36

4 x (74FCT823)

I I 5 x (29FCT52) J
32

4

4x (280)

Address + Acc Type (0, 1)
Data Bus Chip Count

I

Data

=9

Pin Count

=176

CACHE
MEMORY

R3000

34

4

36

x (74FCT823)

I I

4

x 73210

I

32

Address + Acc Type (0, 1)

Data

=

Data Bus Chip Count 4 Pin Count
Saves 10ns In the Critical Data Path

=128

Figure 1.. R3000 System with No Parity Support In Main Memory

UPDATE1 A

2594 drw04

19

1DT73210A/11A

Data Book A, Section 5.9, Page 7

CACHE
MEMORY

R,3000

34

36

4 x (74FCT823ll

l 5 x (29FCT52) I
32

4

4 x (280)

Parity
Error

36
Address + Acc Type (0, 1)
Data Bus Chip Count

=9

Data + Parity
Pin Count = 176

CACHE
'MEMORY

R3000

34

36

4 x (74FCT823),

"

4 x 73210

Parity
Error

36

Address + Acc Type (0, 1)
Data Bus Chip Count

=4

Data + Parity
Pin Count

=128

Figure 2. R3000 System with Parity Support in Main Memory

UPDATEl A

2594 drwOS

20

10T7321 OA/11 A

Data Book A, Section 5.9, Page 8

32+4

FPU

OSC

(4)

CPU

,-Reset - +

Inll
PAL
Inlt Options - + Slate
Match
Intr 5-0 - +

!C r..' - - rr-

(4)

Tag

~

I - -+

r-"T1

.-. Q
!:l
~

20+ 1 +3

f

I Cache
x 60 Bits

""-

18

AddrLo

:>

"T1

Q

--- ~ ---

Dala

c ~

r--

---

o Cache

x 60 Bits

~

1+---+

'--

(1)

FCT240A

u
oc:

I

Mem
Rd&Wr
PAL State Machine

Buffered
Sys Clock

,..

BIHl

BIHl

- CP
Vcc...... LE
Busy
Rd&Wr

il

ll

BIHl

73210
AIHl

73210
AIHl

1

1

II:
f---~

BIHl

CP
LE
73210
AIHl

73210
AIHl

1

1

t

1

1

1

AIHl

AIHl

AIHl

CP
73210
... AOE

73210

73210

BIHl

BIHl.

BIHl

BIHl

1

1

1

1

. AIHl

---

Address

73210
jERRAiB

t

Dala + Parity

Figure 3. Read and Wrlle Buffers Using Elghl IDT7321 011

UPDATEI A

21

IDT73210A/11A

Data Book A, Section 5.9, Page 9

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Com'l.

Mil.

Unit

-{l.5 to
Vee + 0.5

-{l.5 to
Vec+ 0.5

V

Rating

VTERM

Terminal Voltage
with Respect
to Ground

Vee

Power Supply
Voltage

·0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125 -65 to +135

°C

TSTG

Storage
Temperature

-55 to +125 -65 to + 150

°C

Parameter(')

Conditions

Typ.

Unit

CIN

Input
Capacitance

VIN= OV

5

pF

COUT

Output
Capacitance

VOUT= OV

7

pF

Cuo

Input - Outpu,t
Capacitance

VOUT= OV

7

pF

Symbol

NOTE:
1. This parameter is sampled and not 100% tested.

PT

Power Dissipation

1.2

1.5

W

lOUT

Total Output
Current

200

250

mA

25941b107

NOTE:
25941b106
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
, RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated ,in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
The following conditions apply unless otherwise specified:
Commercial: TA = O°C to +70°C, vcc = 5.0V ± 5%; Military: TA
Symbol

= -55°C to +125°C, Vcc

Test Condltions(')

Parameter

Min.

5.0V± 10%
Typ.(2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

-

0.8

V

IIH

Input HIGH Current

Vee = Max.

Except I/O

-

-

10

~A

IlL

Input LOW Current

VI = 2.7V
Vee

= Max.

VI = 0.5V

V

110 pins

-

Except I/O

-

-

-10

110 pins

-

-

-20

-

-0.7

-1.2

V

PERRA,PERRB

-30

-

-150

mA

20
~A

VIK

Clamp Diode Vo~age

Vee = Min., IN = -18mA

los

Short Circuit Current

Vee = Max.(3l , Vo = GND

AD-s, Bo-s

-20

-

-75

VOH

Output HIGH Voltage

Vee = Min.

10H = -12mA MIL.

2.4

3.3

-

V

VIN = VIH or VIL

10H = -15mA COM'L.

-

0.3

0.5

V

-

200

-

VOL

VH

Output LOW Voltage

Input Hysteresis for CP only

Vee = Min.

ArH3

10L = 48mA MIL.

VIN = VIH or VIL

BrH3

10L = 64mA COM'L.

Vee = Min.

PERRA

10L = 20mA MIL.

VIN = VIH or VIL

PERRB

10L = 24m A COM'L.

Vee=5V

NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°e ambient, not production tested.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed 100 millisecond.

UPDATE1 A

mV
25941b109

22

IDT7321 OA/11 A

Data Book A, Section 5.9, Page 10

POWER SUPPLY CHARACTERISTICS
Commercial: TA = O°C to +70°C, Vcc = 5 OV+ 5%·, Military· TA = -55°C to +125°C , Vcc =5.0V + 10%
Typ.(2) Max.
Test Condltlons(1)
Symbol
Parameter
Min.

-

-

ICCDI

Dynamic Power Supply
Current(4)

Vcc= Max.·
Outputs Disabled
fcp =10MHz
SO% Duty Cycle
fi=SMHz

VIN = Vccor GND

-

ICCD2

Dynamic Power Supply
Current(4)

Vec= Max.
Outputs Disabled
fcp =40MHz
SO% Duty Cycle
fl =20MHz

VIN = Vccor.GND

-

Iccoc

Quiescent Power Supply Current

Vee = Max., VIN = GND or Vee

.ICCQT

Quiescent Power Supply Current

Vcc= Max.
VIN = 3.4(3)

COM'L

TTL Inputs HIGH

MIL

2.0

rnA

0.3

1.0

mAl

0.3

1.S

Input

6.0

1S

rnA

24

60

rnA

NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading, not production tested.
3. This parameter is not direcUy testable but is derived for use in the total power supply calculation.
, 4. Ic = IQUIESCENT + IINPUTS t IDYNAMIC
Ic = leeoc + IceoT DHNT + IceD
leeoc = Quiescent Current
IceoT = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TIL Inputs at DH
lceo =Dynamic Current caused by an Input Transition Pair (HLH or LHL)
All currents are in milliamps and all frequencies are in megahertz.

UPDATE1 A

UnR

0.001

259411>108

23

IDT7321 OA/11 A

Data Book A, Section 5.9, Page 11

IDT73210A,IDT73211A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Commercial Range Performance) TA = DoC to +70°C; VCC= 5V± 5%
CL =50pF', RL -- 500n
. . ..
Parameter

Description

. Typ,<1)

Max.
7.2

Unit
. ns

-

9.0

ns

-

-

9.0

Propagation Delay
POLARllY to Be

-

-

8.5"

ns

IPHL
tPLH

Propagation Delay
Ba-a 10 PERRB
LE= High

-

-

9

ns

Is

Sel-upTime
Aa-a, Ba-a (R,eg Y-73210 only),
POLARllY, SEL to CP

. 3.0

-

-

ns

IH

Hold Time
10CP

1.0
1.5
3.0

-

-

ns
ns

-

.'i_

ns

IPHL
IPLH

Propagation Delay
Clock to Aa-a (AOE = Low)

tPHL
IPLH

PropagaliOn Delay
Clock to Ba-a (BOE

tPHL
IPLH

Propagation Delay
CP to PERRA, PERRB

IPHL
tPLH

'

:.',

,

-

= Low)

I AO-a, Ba-a (Reg Y-7321 0 only)
I

Min.

POLARllY, SEL

,

ns

ts

Sel-upTime
AEN, BEN 10 CP

IH

Hold Time
AEN, BEN 10 CP

1.5

-

-

ns

ts

Sel-upTime
Ba-alo LE

3,0

-

-

ns

IH

Hold Time
Ba-alo LE

1.5

-

-

ns

IS

Sel-upTime
Ba-a 10 CP (Reg Z); LE

3.5

-

-

ns

=High

IH

Hold Time
Ba-a to CP (Reg Z); LE = High

1.5

-

-

ns

IpZH
tPZL

Oulpul Enable Time
AOE to Aa-a, BOE 10 Ba-a

-

-

7.0

ns

IPHZ
IPLZ

OutpUI Disable Time
AOE 10 Aa-a, BOE 10 Ba-a

-

-

6.0

ns

IPWH

Clock Pulse Widlh High

7.0

5.0

Clock Pulse Widlh Low

7.0

5.0

-

ns

IPWL

NOTE:
1. Typical values are at Vee = 5.0V and +25°C ambient, not production tested.

UPDATE 1 A

ns
259411>110

24

IDT73210A/11A

Data Book A, Section 5.9, Page 12

IDT73210A,IDT73211A AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) TA = -55°C to +125°C; Vee = 5V ± 10%
CL - 50pF', RL - soon
Typ.(1)

Max.

Unit

tPHL
tPLH

Propagation Delay
Clock to A0-8 (AOE = Low)

-

-

9

ns

tPHL
tPLH

Propagation Delay
Clock to B0-8 (BOE = Low)

-

-

10.5

ns

tPHL
tPLH

Propagation Delay
CP to PERRA, PERRB

-

-

10.5

ns

tPHL
tPLH

Propagation Delay
POLARITY to Ba

-

-

9.5

ns

tPHL
tPLH

Propagation Delay
B0-8 to PERRB
LE= High

-

-

10

ns

ts

Set· up Time
A0-8, Bo-a (Reg Y-73210 only),
POLARITY, SEL to CP

3.5

-

-

ns

tH

Hold Time
toCP

1.5
2.0
3.5

-

-

ns
ns

-

-

Parameter

Description

Min.

I A0-8, B0-8 (Reg Y-7321 0 only)
I POLARITY, SEL

ns

ts

Set-up Time
AEN, BEN to CP

tH

Hold Time
AEN, BEN to CP

1.5

-

-

ns

ts

Set-up Time
B0-8 to LE

3.5

-

-

ns

tH

Hold Time
B0-8 to LE

1.5

-

-

ns

ts

Set-up Time
B0-8 to CP (Reg Z); LE = High

4.5

-

-

ns

tH

Hold Time
60-8 to CP (Reg Z); LE = High

2.5

-

-

ns

tPZH
tPZL

Output Enable Time
AOEtoA0-8,BOEtoB0-8

-

-

8.0

ns

tPHZ
tPLZ

Output Disable Time
AOEtoA0-8,BOEtoB0-8

-

-

7.5

ns

-

ns

tPWH

Clock Puls.e Width High

8

6

tPWL

Clock Pulse Width Low

8

6

NOTE:

ns
259411>111

1. Typical values are a1 Vee = 5.0V and +25°e ambient, not production tested.

UPDATEl A

25

IDT73210A/11A

Data Book A, Section 5.9, Page 13

IDT73210, IDT73211 AC ELECTRICAL CHARAcTERISTICS
(Guaranteed Commercial Range Performance) TA
CL = 50pF· RL = 5000

.

= O°C to +70°C;

Vee

= 5V ±5%

. Min.

Typ.(1)

Max•

Unit

-

-

9

ns

-

-

10.5

ns

Propagation Delay
CP to PERRA. PERRB

-

-

10.5

ns

tPHL
tPLH

Propagation Delay
POLARITY to B8

-

-

9.5

ns

tPHL
tPLH

Propagation Delay
BO-fJ to PERRB
LE = High

-

-

10

ns

ts

Set-up Time
AO-fJ. BO-f3 (Reg Y·73210 only).
POLARITY. SEL to CP

3.5

-

-

ns

tH

Hold Time
toCP

I

1.0
1.5

-

ns
ns

ts

Set·up Time
AEN, BEN to CP

3.5

-

-

tH

Hold Time
AEN. BEN to CP

1.5

-

-

ns

ts

Set-up Time
BO-fJto LE

3.5

-

-

ns

tH

Hold Time
BO-fJ to LE

1.5

-

-

ns

ts

Set-up Time
BO-fJ to CP (Reg Z); LE

4.5

-

-

ns

Parameter

Description

tPHL
tPLH

Propagation Delay
Clock to AO-fJ (AOE

= Low)

tPHL
tPLH

Propagation Delay
Clock to BO-fJ (BOE

= Low)

tPHL
tPLH

AO-fJ. BO-fJ (Reg Y-7321 0 only)
I POLARITY, SEL

= High

ns

IH

Hold Time
BO-fJ to cP (Reg Z); LE = High

1.5

-

-

ns

tPZH
tPZL

Output Enable Time
AOEtoAO-fJ.BOEtoBO-fJ

-

-

8.0

ns

tPHZ
tPLZ

Output Disable Time
AOE to AO-fJ, BOE to BO-fJ

-

-

7.5

ns

tPWH

Clock Pulse Width High

7.0

5.0

-

ns

tPWL

Clock Pulse Width Low

7.0

5.0

-

NOTE:

ns
259411>112

1. Typical values are at Vee = 5.0V and +25°e ambient, not production tested.

UPDATE1 A

26

IDT7321 OA/11 A

Data Book A, Section 5.9, Page 14

10173210, 10173211 AC ELECTRICAL CHARACTERISTICS
(Guaranteed Military Range Performance) TA = -55°C to +125°C; Vee = 5V ± 10%
CL = 50pF; RL = 500n
Min.

Typ.(1)

Max.

Unit

tPHL
tPLH

Propagation Delay
Clock to A0-8 (AOE = Low)

-

-

11

ns

tPHL
tPLH

Propagation Delay
Clock to B0-8.(BOE = Low)

-

-

12

ns

tPHL
tPLH

Propagation Delay
CP to PERRA. PERRB

-

-

12

ns

tPHL
tPLH

Propagation Delay
POLARITY to Ba

-

-

11

ns

tPHL
tPLH

. Propagation Delay
B0-8 to PERRB
LE= High

-

-

11.5

ns

3.5

-

-

ns

1.5
2.0
3.5

-

-

ns
ns

-

-

2

-

-

ns

3.5

-

-

ns

Parameter

Description

ts

Set-upTIme
A0-8. 80-8 (Reg Y-73210 only).
POLARITY. SEL to CP

tH

Hold TIme
to CP

LA0-8. B0-8 (Reg Y-73210 only)
I POLARITY. SEL

-

ns

ts

Set-upTime
AEN. BEN to CP

tH

Hold TIme
AEN. BEN to CP

ts

Set-upTIme
B0-8to LE

tH

Hold TIme
B0-8to LE

2

-

-

ns

ts

Set-up Time.
B0-8 to CP (Reg Z); LE = High

5

-

-

ns

tH

Hold TIme
B0-8 to CP (Reg Z); LE = High

3

-

-

ns

tPZH
tPZL

Output Enable Time
AOE to A0-8. BOEtoB0-8

-

-

10

ns

tPHZ
tPLZ

Output Disable Time
AOE to A0-8. BOEtoB0-8

-

-

9

ns

tPWH

Clock Pulse Width High

8

6

-

ns

tPWL

Clock Pulse Width Low

8

6

-

NOTE:

ns
259411>113

1. Typical values are at Vee = 5.0V and +25°C ambient, not production tested.

UPDATE1 A

27

IDT7321 OA!11 A

Data Book A, Section 5.9, Page 15
Vee

INPUTS 0 - - - - -........--1

OUTPUTS

.~

IlL

2594 drw07
2594 drw 08

Figure 4. ·Inputlnterface Circuit
Figure 5. Output Interface Circuit

+ 7.0V

Vee

o---e

DEFINITIONS:
CL =. Load capacitance: .includes jig and probe capacitance
RL = tennination resistance: should be equal to lour of the Pulse Generator
Figure 6. AC Test load Circuit

AC TEST CONDITIONS
Input Pulse levels

GNDto3.0V

Test·

SWitch

Input RiselFall Times

1V/ns

Closed

Inpul Timing Reference levels

1.5V

Open Drain
Disable low
Enable low
All other Tests

Output Reference levels
Output load

1.5V
See Figure 6

Open
25941b113

25941b112

UPDATE 1 A

28

IDT73210A/11A

Data Book A, Section 5.9, Page 16

ORDERING INFORMATION
IDT

xxxxx

XX

x

x

Device
Type

Speed

Package

Process!
Temperature
Range
I-

-

-I

Blank

~B
.Y
'---------'-----j

TC

' - - - - - - - - - - - - , , - - - - - 1 Blank

A

Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Compliant to MIL-STD-883, Class B

32-pin Small Outline IC (J·Bend)
32-pin Thin Sidebraze DIp (300mil wide)
Standard Speed
High Speed

'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _--/ 73210 -8-bit Orie Single, One Double Pipeline Registers
73211 8-bit Two Single Pipeline Registers
2594 drw 10

UPDATE_1 A

29

IDT49C466

Data Book A, Section 5.13, Page 1

64-BIT FLOW-THRU
ERROR DETECTION
AND CORRECTION UNIT

PRELIMINARY
IDT49C466

Integrated Device Technology, Inc.

FEATURES:
• 64-bit wide Flow-thruEDCTM
• Separate System and Memory Data Input/Output Buses
• - Error Detect Time: 15ns
- Error Correct Time: 20ns
• Corrects all single bit errors; Detects all double bit errors
and some multiple bit errors
• Configurable 16-deep system bus read/write buffer with
flag indicators
• Simultaneous check bit generation and data correction of
memory data
• Supports partial word writes on byte boundaries
• Low noise output
.
• Sophisticated error diagnostics and error logging
• Parity generation on system data bus
• 208-pin Pin Grid Array and Plastic Quad Flatpack

DESCRIPTION:
The IDT49C466 64-bit Flow-thruEDCTM is a high-speed
error detection and correction unit to ensure data integrity in

high reliability memory systems. The flow-thru architecture,
with separate system and memory data buses, is ideally
suited for pipe lined memory systems.
Implementing a Hamming code in the a-bit wide check bit
bus, the I DT49C466 corrects all single bit hard and soft errors,
and detects all double bit errors. The read/write buffers can
store up to sixteen 64/72-bit words until the system bus is
ready (during reads) oruntil the system bus is released (during
writes). Full and empty flags indicate whether additional data
can be written to the EDC.
The simultaneous check bit generation and data correction
of memory data eliminates the separate correction and
generation rnodes found on other EDC units. Check bit
generation for partial word writes on byte boundaries is
supported on the IDT49C466.
Diagnostics features include a syndrome latch from which
the error bit can be located, a four bit error counter which logs
up to 15 errors, and an error data latch which stores the
complete error. data word. Parity can be generated and
checked on the system bus by the IDT49C466.

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

SD
LATCH

OUT
SD
CHK-BIT
LATCH

CBSYNo-7

P0-7
2617drw01

Flow-thruEDC Is a trademark of Integrated Device Technology Inc.

JUNE 1991

COMMERCIAL TEMPERATURE RANGE
e1991 Integrated DevIce Technology, Inc.

UPDATE1 A

DSC-a0371t

30

ERR

1~:~~:;:m::~1~~:~:~-;:~:~~

.

w;':;

PSEL (BIt 5, Made R-a)

I

t

II·· 1111~ ...··_~

I

CBSYN 0.'

'-----4_ _ _ _ _ _ _ _---,_ _ _ _ _ _ _ _

~

WBSEl

P ...

PERR ~----------------~

MEN

SYNClK

.1

~

~

.

ERROR

...

MIl to SO Path

_

SO to MO Path

I

POWER
SUPPLY

~vcc
17

n,,,.

==::j:::)- INTERNAL
SYNCLK

Olagnollio path

49C466 64-Bit Flow-ThruEDCTM

~

~

II

GNO

IDT49C466

Data Book A, Section 5.13, Page 3

PIN CONFIGURATION

A

B

C

E

F

G

H

J

K

M

N

P

R

T

u

7

MO_l0

MO_B

MO_2

MO_l

MERR

CBL6

CBLl

RBEN

RBSEl

RsHF

SO_2

SO_3

BEO

SO_9

SO_10

SO_12

SO_15

17

6

MO_13

MO_9

MO_6

MO_3

ERR

CBL3

CBL2

RBREN

RBEF

RBFF

SO_l

SO_4

SO_6

SO_B

SO_13 SO_16

SO_17

16

5

MO_17

MO_12

MO_ll

MO_5

MO_4

CBIJ

CBL4

CBLo

GNO

so_o

PO

sOJ

Pl

BEl

SO_14 SO_19

SO_21

15

4

MO_1B MO_19

MO_15

GNO

MOJ

MO_O

CBL5,

GNO

Vee

SO_5

SO_ll

GNO

GNO

P2

SO_2O

14

3

MO_23

MO_2O MO_14

Vee

SO_lB

SO_22

SO_24 SO_25

13

2

MO_25

MO_22

MO_21

MO_16

SO_23

SO_26

SO_26

SO_27

12

1

MO_27

MO_28

MO_24

GNO

P3

BE3

SO_30

SO_29

11

0

MO_31

MO_30

MO_29

MO_26

SO_31

SOE

SOllE

SClK

10

9

SOOlE

MOE

MDilE

GNO

IMOOlE

GNO

MEN

RS_O

9

MO_3

MO_35

GNO

SO_33

MClK

RS_1

8

SO_37

SO_34

SO_32

PERR

7

SO_38

P4

SO_35

6

P5

BE4

8

MO_33 MO_32

°

GNO

l

G208·1

7

MO_37

6

MO_41 MO_38 MO_42

MO_45

SO_42

5

MO_43 M034

MO_46

MO_52

GNO

4

MO_48

MO_SO

GNO

MO_36

MO_49

MO_39 MO_40

GNO

MO_61 pBSYN4

Vee

GNO

SO_61

GNO

SO_54

SO_49

BE2

SO_38

5

4

VCC

SO_43

SO_39 SO_40

SO.:..51

SO_45

SO_44

SO_41

SO_47

BE5

",

3

MO_47 MO_51

2

MO_53

MO_54 MO_57

BSYN7

BSYN5 pBSYN2 pBSYNO lWaREN

1

MO_55

MO_58

MO_63

BSYN3 CBSYN1 WBSEl CBSEl

A

B

MO_56 MO_60

WBEN

MO_5:!
C

°

MO·59 pBSYN6

E

F

GNO

G

GNO

H

SO_62

SO_59

~YNClK WBEF SO_60
WBFF

SO_63

J

K

P7
l

SO_57 SO_53

BE7

SO_55

BE6

SO_SO

SO_51

SO_56

P6

'SO_52

P

R

M

N

2

SO_48 SO_46

T

U

Pin 1 reference
2617 drw03

208-pln PGA Package

Top View

UPDATE1 A

32

IDT49C466

Data Book A, Section 5.13, Page 4

PIN CONFIGURATION

GNO
M054
M053
M052
M051
MOSO
M049
M048
M047
MD46
M045
MD44
M043
M042
M041
M040
M039
M038
M037
M036
M035
M034 ,
M033
M032
SOOLE
MOE
MOlLE
M031
GNO
M030
M029
M028
M027
M026
M025
M024
M023
M022
M021
M020
GNO
M019
M018
MOH
M016
M015
M014
M013
M012
M011
M010

GNO
S046
S045
S044
BE5
P5
S043
S042
5041
5040
5039
5038
5~37

5036
BE4
GNO
P4
5035 '
S034
S033
S032
PEAR
MCU<
MOOLE
RS1
MEN
GNO
RS_O
SOILE
SCLK

SOE
S031
5030
S029
S028
BE3
P3
5027
5026
5025
5024
S023
5022
S021
S020
BE2
P2
5019
S018
SOH
S016
GNO

vee

104

PQFP

Top View
2617drw04

UPDATE1 A

33

II

IDT49C466

Data Book A, Section 5.13, Page 5

PIN DESCRIPTION
Pin Name

110

Description

Data Buses
500-63

110

System Data Bus: is a bidirectional 64·bit bus interfacing tothe system or cpu. When System Output
Enable, SOE, is high or Byte Enable, BE0-7, is low, data is input. The data is latched into the system
data (SO) latch when the System Oata Input Latch Enable (SOILE) is low. The System Oata Bus
outputs corrected memory data during a read operation. Corrected data can come from the memory
data (MO) output latch or the content of the read buffer. When the Read Buffer Select (RBSEL) pin
is low, the MO latch is selected. When RBSEL is high, the read buffer content is selected. When
System Output Enable, SOE, is low and Byte Enable, BEo·7, is high, the SO bus output drivers are
enabled.

MOO-63

I/O

Memory Data Bus: is a bidirectional 64-bit bus interfacing to the memory. Ouring a read cycle,
memory data is input for error detection and correction. Oata is latched in the memory data (MO) input
latch when Memory Oata Input Latch Enable (MOlLE) is low. Ouring a memory write cycle, data from
the SO output latch (WBSEL=O)or the write buffer (WBSEL=1)is output on the Memory Oata Bus.

CBl0-7

I

Check Bit Inputs: interface to the check bit memory.

CBSYN0-7

0

Check Bit or Syndrome Output:. When CBSEL is low and MOE is low the generated check b~s are
selected. When CBSEL is high and MOE is high, the syndrome bits are selected.

P0-7

I/O

Parity Input/output for bytes 0 to 7: These pins are parity inputs when the corresponding Byte
Enable (BE) is low, and are used to generate the par~y error signal (PERR). These pins are outputs
when the corresponding Byte Enable (BE) is high. The internal parity select bit (PSEL) of the mode
register selects odd or even parity.

SOE

I

System Output Enable: enables system data output drivers if the corresponding Byte Enable
(BE0-7) is high.

BE0-7

I

Byte Enable: is used along with SOE, to enable the System Oata outputs for a particular byte. For
example, if BEl is high, the System data outputs for byte 1 (S08.15) are enabled. The BE0-7 pins also
control the data byte mux. If a particular BE is high during a memory read cycle, data is fed back to
the memory data bus and used for check bit generation of that byte. This is used during partial word
wr~e operations and rewr~ing corrected data to the memory. H a particular BE is low, data from the
system data latch and wr~e buffer is directed tothe memory data bus and used for check bit generation
of that byte, used in writing new data during a partial word wr~e operation. BE is buffered with the data
in the wr~e buffer.

MOE

I

Memory Output Enable: when low, enables the output buffers of the memory data bus (MO). It also
controls the check bit output buffer enable.

MOlLE

I

Memory Data Input Latch Enable: on the high to low trans~ion latches data at the MO inputs and
the checkbits at the CBI inputs. The latch is transparent when MOlLE is high.

MOOLE

I

Memory Data Output Latch Enable: latches data into the MO output latch during the low to high
.
transition of MOOLE. When MOOLE is low, the MO output latch is transparent.

SOOLE

I

System Data Output Latch Enable: latches data in the SO output latch and the SO checkbit latch
on the low to high transition of SOOLE. The latch is transparent when SOOLE is low.

SOILE

I

System Data Input Latch Enable: latches in the SO input latch on the high to low transition. When
SOILE is high, the SO input latch is transparent.

WBSEL

I

Write Buffer Select: when high, the output of the wr~e buffer is selected. When the WBSEL is low,
output from the SO input latch is selected.

WBEN

I

Write Buffer Enable: allows system data (SO) input to be written tothe write buffer on the SCLK rising
edge.

WBREN

I

Write Buffer Read Enable: when low, allows data to be read from the the write buffer on MCLK rising
edge.

RSO-l

I

Reset and Select pins (read and write buffer FIFOs)
RSl
RSo
Function
0
0
Reset 16-deep FIFO or first 8-deep FIFO
0
Reset second 8-deep FIFO
1
Select 16-deep FIFO or first 8-deep FIFO
1
0
Select second 8-deep FIFO
1
1

Control Inputs

2617tbiOl

upDATE1 A

34

IDT49C466

Data Book A, Section 5.13, Page 6

PIN DESCRIPTION (Continued)
110

Pin Name

Description

RBSEL

I

Read Buffer Select: when high the output of the read buffer is selected. When low, data from the
MD output latch is selected.

RBEN

I

Read Buffer Enable: when low allows data to be written into the read buffer on the low to high
transition of the memory clock.

RBREN

I

Read Buffer Enable: when low, allows data to be read from the read buffer on the low-to-high
transition of SCLK

CBSEL

I

Checkblt Select: when high, selects the syndrome bits at the CBSYN()'7 output. When CBSEL is low,
the checkbits are selected.

MEN

I

Mode Enable Input: When low, data on the SO bus is loaded into the EDC mode register on the lowto-high transition of the SCLK. The mode register is used to determine the modes of the EDC.

MCLK

I

Memory Clock: On the low to high transition of MCLK, memory data is written to the read buffer when
RBEN is low. Data is read from the write buffer when WBREN is Iowan the low to high transition of
MCLK.

SCLK

I

System Clock: On the low to high transition of the SYSCLK, data is read from the read buffer when
RBREN is low. Data on the system data bus is written into the write buffer when WBEN is Iowan the
low to high transition of SCLK.

SYNCLK

I

SYNdrome. CLocK: HERR is high, and the Error Counter indicates zero errors, syndrome bits are
clocked into the Syndrome Register and data from the outputs of the Memory Data input latch are
clocked into the Error-Data Register on the low-to-high edge of SYNCLK. If ERR is low, the Error
Counter will increment on the low-to-high edge of SYNCLK, unless the Error Counter indicates fifteen
errors.

WBEF

0

Write Buffer Empty Flag: when low, indicates that the last data word in the write buffer has just been
output. Further read operations are then inhibited. At reset, the WBEF is low.

WBFF

0

Write Buffer Full Flag: when low, inhibits further write operations to the buffer and indicates that the
write buffer is full. After a reset, WBFF goes high.

0

Read Buffer Empty Flag: when low, indicates that the last data word in the read buffer has just been
output. Further read operations are then inhibited. At reset, the RBEF is low.

RBHF

0

Read Buffer Half-full Flag: when low, indicates that there are eight or more data words (in the 16deep configuration) or four or more data words (in the dualS-deep configuration) in the read buffer.
The flag will return high when less than eight (or four) data words are in the buffer.

RBFF

0

Read Buffer Full Flag: when low, inhibits further write operations to the buffer and indicates that the
..
read buffer is full. After a reset, RBFF goes high.

ERR

0

Error Flag: In normal mode (Mode 3), when ERR is low, a data error is indicated. The ERR is not
latched internally.

MERR

0

Multiple Error Flag: In normal mode (Mode 3), when MERR is low, a multiple data error is indicated.
The MERR is not latched internally.

PERR

0

Parity Error Flag: when low, indicates a parity error on the system data bus input.

Clock Inputs

Status Outputs

RBEF
..

Power Supply .
Vee

P

Power Supply Voltage, +5 volts.

GND

P

Ground.
2617tbi 02

UPDATE1 A

35

IDT49C466

Data Book A, Section 5.13, Page 7

DETAILED DESCRIPTION -

,
Ji4-BIT M~DIFIED HAMMING CO DE - CHECKBIT ENCODING CHAR -r<1 2)
Generated

Participating Data Bits

Checkblts

Parity

CBO
CBl
CB2
CB3
CB4
CB5
CB6
CB7

Even (XOR)

0

Even (XOR)

X

Odd (XNOR)

X

Odd (XNOR)

X

1

2

3

X

X

X

X

X

4
X

7

X

X

8

9

X

X

X

X
X

X

X
X

6

X

X

Even (XOR)

5

X

X

X

X

X

X

Even (XOR)
Even (XOR)

X

X

X

X

X

X

X

X

Even (XOR)

X

X

X

X

X

X

X

X

11

X

12

13

X

15

X

X

X

14

X

X
X

X

10

X
X

X

X

X

X

X

X
X

X

X

X

26171bi 03

Generated

Participating Data Bits

Checkblts

Parity

CBO
CBl
CB2
CB3
CB4
CB5
CB6
CB7

Even (XOR)

16

Even (XOR)

X

Odd (X NOR)

X

Odd (X NOR)

X

17
X
X

18

19

X

X

20

X

X

23

X

X

X
X

22

X

X

Even (XOR)

21

X

X

24

25

X

X

X
X

X

X

X

X

X

X

26

27

X
X

28

29

X

31

X
X

X

X

X
X

X

X

X

X

X

Even (XOR)

X

X

Even (XOR)

X

X

X

X

X

Even (XOR)

X

X

X

X

X

X

30

X

X

X

X

X

X

X

X

X

X
2617tbi04

Generated

Participating Data Bits

Checkbits

Parity

32

CBO
CBl
CB2
CB3
CB4
CBS
CBS
CB7

Even (XOR)

X

Even (XOR)

X

Odd (X NOR)

X

Odd (X NOR)

X

33
X

34

35

X
X

38

39

X

X

X

X

X

36

X

X

Even (XOR)

X

X

37

X

X

X

X

X

X

X
X

X

X

X

X

X

X

. X

41

X

Even (XOR)
Even (XOR)

40

X

42

44

45

X

43

X

X

X

X

X
X

X

X
X

X

X

46

47

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Even (XOR)

~
26171bi05

Generated

Participating Data Bits

Checkbits

Parity

48

CBO
CBl
CB2
CB3
CB4
CBS
CBS
CB7

Even (XOR)

X

Even (XOR)

X

Odd (XNOR)

X

Odd (X NOR)

X

49
X

50

51

X
X

52

54

55

X

X

X

X

·X

X

X

X

X

X

X

X

X

X

Even (XOR)

X

X

X

X

X

X

X

57

X

Even (XOR)
Even (XOR)

56

X

X

X

Even (XOR)

53

X

58

59

60

61

X

X IX

X

X

X

62

X
X

X
X

X

X

63

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

NOTES:
2617tbi06
1. The table indicates the data bits participating in the checkbit generation. For example. checkbit CBO is the Exclusive-OR function of the 64 data input bits
mar1 Path A
=> Path B

MDBUS

SD

L-_______________ WBSEL
Figure 1. Byte Merge
2617 drw 05

Memory Read
During a memory read, data and the corresponding input
checkbits are read from the MD bus and CBlo-? respectively.
The memory data and CBI may both be latched as they come
in (MD Latch In and MD Checkbit latch) by the MOlLE signal.
Memory data is sent to the MD checkbit generator (where
checkbits corresponding to the input data are generated) and
to the error correct circuitry. The generated checkbits are XORed with the input checkbits to produce the syndrome word.
. This is sent to the error correction circuitry which generates
the corrected data (normal mode). The corrected data is
output to the SO bus via either of two data paths. If the user
chooses not to use the read buffer (RBSEL low). data flows
through MD Latch Out. AssertingMDOLE latches this data.
The output buffer is enabled by asserting SOE and BEo-? In
order to also write this corrected data back to memory. the
output buffer needs to be disabled by pulling SOE high. followed by the usual write procedure ..
If the read buffer is selected (RBSEL high), data is clocked
into the buffer (Read-Buffer Write) when RBEN is low, on the
rising edge of MCLK. Data is clocked out of the buffer
(Read_Buffer Read) when RBREN is low on the rising edge of
SCLK. An appropriate skew between,the buffer read and write
clocks (MCLK and SCLK) is essential to avoid any flag
contention on read/write boundaries (simultaneous read and
write when buffer is either empty or full).
Partial Word Write/Byte Merge
Writing a word shorter than 64 bits to memory is treated
as a special case. The checkbits generated for a data word

shorterthan 64 bits and written to a particular memory location
differ from the checkbit word that would be generated by the
entire 64-bit data word at the same location. Hence, the byte
merge operation is required to carry out the following tasks:
read the contents of the memory location to be written to,
merge the byte/bytes being written (from SO side) with the
other component bytes previously at that memory location
(from MD side), generate a checkbit word for this composite
word and write both the generated checkbits and the composite data word to memory. The BEn bits supplied by the user
determine the bytes that come from SO and those that come
from MD, as illustrated in Figure 1.
EDCModes
The lOT49C466 has 5 modes of operation (very similar to
those of the IDT49C465 32-bit Flow-Thru EDC) which are
described' in the Operating Mode section. The Error Data
Output mode is useful for memory initialization. On issuing a
clear, the Error Data register becomes an 'all-zero-data'
source, All diagnostic registers can be cleared in this
manner. In Checkbit Injection mode, the MD Checkbit Latch
is loaded with data from the System Bus. This serves to verify
the functioning of the EDC. Any discrepancy between the
injected checkbits and generated checkbits should result in
assertion of the ERR or MERRsignals. These modes, and
certain other features such as clear, buffer configuration, etc.,
can be controlled by appropriately. loading the Mode
Register. The Mode Register can be written to by asserting
MEN. Then SOO-15 is clocked into the register on the rising
edge of SCLK.

UPDATE1 A

38

/

IDT49C466

Data Book A, Section 5.13, Page 10

Diagnostics
The diagnostic ability of the 466 rests on a set of 6 registers
that provide error logging information. They include the checkbit register, error count register, error type register, 2 syndrome registers and the error data register. Data is clocked
into each of these registers on the rising edge of SYNCLK. The
checkbit register, error count register, error type register and
one of the syndrome registers are reloaded only in the case of
an error. The other syndrome register and the error data
register are reloaded on every new read cycle. The contents
ofthe Error Data register can be read only in Error Data mode.
The contents of the other diagnostic registers can be read in
Diagnostic mode.

OPERATING MODE CHARTS
15

7

UNUSED

6

I

RMODE

4

5

I

PSEL

I

RWBD

EDCM2 EDCM1 EDCMO

0
0
0
0
1

Parity
The 466 provides a parity check & generation facility. On a
memory read the EDC generates parity bits for each data word .
and outputs the parity byte on the parity bus, POol. During a
memory write, parity is checked by comparing the parity bits
input on POol and the parity bits generated from the input data
word. A discrepancy between these two would cause the
PERR pin to be asserted.

0

0
1
1

X

0
1

0
1

X

RWBD

2

CLEAR

I

I

EDCMO-2

ERRO-DATA OUTPUT MODE
DIAGNOSTIC-OUTPUT MODE
GENERATE-DETECT MODE
NORMAL MODE (DEFAULT)
CHECKBIT-INJECTION MODE

OPERATION
NOP
READ MODE REGISTER ON SD BUS

OPERATION

0

DUAL BUFFERS (8), DEFAULT

1

SINGLE BUFFER (16)

CLEAR

o

OPERATION

RMODE
0
1

3

OPERATION
NORMAL

0

1

CLEAR ALL DIAG. REGISTERS

PSEL

OPERATION
EVEN
ODD

0
1

2617drw06
DIAGNOSTIC OUTPUT DATA FORMAT
TOSDBUS

~
37136135134133132131130 29128 27126125124 23122121120119118117116 151141131121111101918 716151413121110
Syndrome
(on error only)

•

Error
Type

Error
Count

Syndrome
(on every Read)

Checkblt
(on error only)

Checkbit
(from checkblt latch)

i

FROM DIAGNOSTIC REGISTERS
2617drw07

UPDATEl A

39

IDT49C466

Data Book A, Section 5.13, Page 11

OPERATING MODE DESCRIPTION
MODE

DESCRIPTION

MODE 0

Error-Data Output Mode: This mode allows the uncorrected data captured from an error event by the Error-Data
Register to be read by the system for diagnostic purposes. The Error-Data Register is cleared by setting the mode
register 'clear-bit'.

MODE 1

Diagnostic-Output Mode: In this mode, one external source and four internal registers are read by the system bus for
diagnostic and error logging purpose. Internal data paths allow output from the CBI()'7 LATCH to be read directly by the
system bus for diagnostic purpose. The contents of the internal diagnostic checkb~ register, syndrome register, error
count register and error-type register are also output on the SD bus.

MODE 2

Generate·Detect Mode: (Detect-Only) The EDC performs
error detection only during memory reads.

MODE 3

Normal Mode: The EDC performs checkbit generation during memory writes and error detection and correction during
memory reads.

MODE 4

Checkbit·lnjeclion Mode: In this mode, the checkbit latch is loaded with a desired S-bit data from the SD bus when
MDILE is strobed. By inserting various checkbit values, correct functioning of the EDC can be verified "on-board". The
rest of the operation is similar to regular memory read. The EDC compares the injected checkbits against the intern~
generated checkbits. Any discrepancy in the injected checkbit and the internally generated checkbit will cause the ERR
or MERR to go low.

checkb~

generation during a memory write, and performs

2617 tbl 08

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Com'l.

CAPACITANCE
Unit

Vee

Power Supply Voltage

-0.5 to +7.0

V

VTERM

Terminal Voltage with
Respect to Ground

-0.5 to
VCC+0.5

V

TA

Operating Temperature

Oto+70

°C

TSIAS

Temperature Under Bias

-55 to +125

°C

TSTG

Storage Temperature

-55 to +125

°C

lOUT

DC Output Current

30

rnA

Symbol
CIN

(TA = +25°C , f = 1.0 MHz)

Parameter1)
Input
Capacitance

COUT

Output
Capacitance

Typ.

Unit

PGA

5

pF

PQFP

-

Conditions
VIN = OV
VOUT= OV

PGA
PQFP

NOTE:
1. This parameter is sampled and not 100% tested.

7

pF

2617 tbll0

NOTE:
2617tb109
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a slress
rating only, and functional operation of Ihe device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Ratings for
extended periods of time may affect reliability.

UPDATE1 A

40

IDT49C466

Data Book A, Section 5.13, Page 12

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
The following conditions apply unless otherwise specified:
Commercial: TA = O°C to +70°C, VCC = 5.0V ± 5%;
Min.

Typ.(2)

Max.

Unit

VIH

Input Hillh Level(4)

Guaranteed Lallie Hillh Level

2.0

-

V

VIL

Input Low Level(4)

Guaranteed Logic Low Level

-

-

O.S

V

IIH

Input High Current

Vcc = Max., VIN = 2.7V

-

0.1

5.0

J.LA

·0.1

-5.0

/LA

-

·0.1

-10

/LA

Va = Vee (Max.)

-

0.1

10

-

-

mA

IOH=-2mA

2.4

-

-

V

10L= SmA

-

0.3

0.5

V

-

200

-

Symbol

Test Condltlons(1)

Parameter

IlL

Input Low Current

Vcc = Max., VIN = 0.5V

Ioz

Off State (Hi·Z)

Vcc= Max.

IVo=ov

Output Current
los

Short Circuit Current

Vcc = Max.(3), VOUT= OV

VOH

Output HIGH Voltage

VCCm Min.,
VIN - VIH or VIL

VOL

Output LOW Voltage

Vee = Min.
VIN = VIH or VIL

VH

Input Hysteresis on input control lines

NOTES:
1. For conditions shown as min. or max., use appropriate value specified above for the applicable device type.
'2. Typical values are at Vee = 5.0V, +25"C ambient temperature and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. These input levels provide zero noise immunity and should only be static tested in a noise-free environment

mV
2617tbill

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Con't)
The following conditions apply unless otherwise specified:
Commercial: TA = O°C to +70°C, Vee =5.0V ± 5%
Min.

Typ.(2)

Max.

Un"

leeoc

Quiescent Power Supply Current

VIN = Vcc, or VIN = GND
Vcc= Max.

-

3.0

5

mA

ICooT

Quiescent Power Supply Current
TTL Input Levels

VIN= 3.4V
Vcc= Max.

-

0.3

1

mAl
Input

ICCD

Dynamic Power Supply Current

VIN = Vcc, or VIN = GND
Vcc = Max. f = 10MHz Correct Mode

-

-

Symbol

Parameter

Test Condltlons(1)

NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified above for the applicable device type.
2. Typical values
at Vee = 5.0V, +25"C ambient temperature, and maximum loading.

-

mA
2617tbi12

are

UPDATEI A

41

ID,;>T49C466

Data Book A, Section 5.13, Page 13

AC PARAMETERS
PROPAGATION DELAY TIMES (PRELIMINARY)
Description
Number

Parameter

From Input

To Output

Max.

Unit

20
20

ns

Refer to·
Timing Diagram
Figure

GENERATE (WRITE) PARAMETERS
Without Write Buffer:

1
2
3
4
5
6

tBC

BEn

CBSYN (chkbit)

tBM

BEn

MDOUT

tPPE

Pxin

PERR

9

ns

tsc

SDin

CBSYN (chkbit)

. ns

tSM

SDin

MDaut

tSPE

SDin

PERR

15
15
13
25
20
17

ns

ns

ns
ns

With Write Buffer:

7
8

tMCb

MCLK (La-Hi)

CBSYN (chkbit)

tMMD

MCLK (La-Hi)

MDaut

9

tWBSEL

WBSEL

MDaut

ns
ns

DETECT (READ) PARAMETERS
Without Read Buffer:

10

tWYc

SYNCLK (La-Hi)

CBSYN(syndr)

11

tME

MDin

ERR

12
13
14

tMME

MDin

MERR

tCE

CBI

ERR

tCME

CBI

MERR

15 .
15
20
15
20

ns
ns
ns
ns
ns

With Read Buffer:

15
16

tSSD

SCLK (La-Hi)

SDout

tRBSEL

RBSEL

SDout

22
10

ns

ns

ns

ns

CORRECT (READ) PARAMETERS
Without Read Buffer:

17
18

tcs

CBI

SDout

tMP

MDin

Pxout

19

tMS

MDin

SDout

20
24
23

SCLK (Lo-Hi)

Pxout

25

ns
ns

With Read Buffer:

20

tSPb

NOTES:
1. Bold indica1es critical system parameters.
2. (Lo-Hi) indicates Low-to-High transition and vice versa.

2617.blt3

UPDATE1 A

42

IDT49C466

Data Book A, Section 5.13, Page 14

PROPAGATION DELAY TIMES
FROM LATCH ENABLES (PRELIMINARy)
Refer to
Timing Diagram

Description
Number

Parameter

From Input

21

tMLE

MOlLE (Lo·Hi)

Max.

Unit

ERR

To Output

18

ns

22

tMLME

MOlLE (La·Hi)

MERR

21

ns

23

tMLP

MOlLE (La·Hi)

Px

25

ns

24

tMLS

MOlLE (La·Hi)

SOout

22

ns

25

tOOLS

MOOLE (Hi-Lo)

SOout

15

ns

26

tOOLP

MOOLE (Hi-Lo)

Px

18

ns

27

tSLC

SOILE (Lo-Hi)

CBSYN (chkbit)

20

ns

28

tSLM

SOILE (Lo·Hi)

MOout

16

ns

29

tSOLC

SOOLE (Hi-Lo)

CBSYN (chkbit)

12

ns

30

" tSOLM

SOOLE (Hi-Lo)

MOout

12

ns

Figure

NOTE:

26171bi14

1. (Lo:.Hi) indicates Low-to~High transition and vice versa.

RIW BUFFER TIMES (PRELIMINARY)
Refer to
Timing Diagram

Description
Number

Parameter

From Input

To Output

Min.

Max.

Unit·

Figure

31

tRSF

RS1 (Hi-Lo)

EF (Hi-La)/FF (Lo-Hi)

-

15

ns

7

32

tSKEWl

RCLK (Lo-Hi)
(SCLK or MCLK) -

WCLK (Lo-Hi)
(SCLK or MCLK)

20

-

ns

3,5

33

tSKEW2

WCLK (Lo-Hi)
(SCLK or MCLK)

RCLK (Lo-Hi)
(SCLK or MCLK)

20

-

ns

4,6

34

tEF

RlWCLK (Lo-Hi)
(SCLK or MCLK)

EF

-

16

ns

4,6

35

IFF

RlWCLK (Lo-Hi)
(SCLK or MCLK)

FF

-

16

ns

3,5

NOTE:
1. (Lo-Hi) indicates Low-to-High transition and vice versa.

26171bi15

UPDATE1 A"

43

IDT49C466

Data Book A, Section 5.13, Page 15

BYTE MERGE TIMES (PRELIMINARY)
Refer to
Timing Diagram

Description
Number

36
37
38
39
40

Parameter
tSCM

From

To

SCLK (Lo·Hi)

MDout

tMDM

MDOLE (Hi·Lo)

MDout

tRBM

RBSEL

MDout

tSDM

SDiLE (Lo·Hi»

MDout

tSOE

MDin

SOE (Hi·Lo)

Max.

Unit

22
18
18
16

ns

TBD

ns

Figure

ns
ns
ns
26171b116

NOTES:
1. (La-Hi) indicates Low-to-High transition and vice versa.

ENABLE AND DISABLE TIMES (PRELIMINARY)
Refer to
Timing Diagram

Description
Number

41
42
43
44
45
46
47
48
49
50

Parameter
tBESZx

From Input
BEN =

tBESxZ
tBEPZx

BEN =
MOE =

tSESxZ

Pout

Low

CBSYN

High
MOE =

tMEMXZ
tSESZx

High
Low

tCECXZ
tMEMZx

To Output
SDout

Low

tBEPxZ
tCEClx

High

Low

MDout

High
SOE=

Low
High

SDout

·
·

Min.

-

Hi-Z

-

Hi·Z

-

Hi-Z

-

·
·
·

-

Hi-Z

-

Hi-Z

-

NOTES:
1. (Z) indicates high impedence.
2. (La-Hi) indicates Low-to-High transition and vice versa.
3 ..• indicates delay to both edges.

Max.

Unit

Figure

15
15
15
15
15
15
18

ns

6

ns

6

ns

4

ns

4,9

ns

6

18

15
15

26171bl 17

UPDATE1 A

44

IDT49C466

Data Book A, Section 5_13, Page 16

SET-UP AND HOLD TIMES (PRELIMINARY)
Description

Refer to
Timing Diagram
Figure

To Input

(edge)

Min_

51

tCMLS

CBI Set-up

before MDILE =

Hi-Lo

2

ns

5

52

tCMLH

CBI Hold

afterMDILE=

Hi-Lo

6

ns

5

53

tMMLS

MDINSet-up

before MDILE =

Hi-Lo

2

ns

5

54

tMMLH

MDINHold

afterMDILE =

Hi-Lo

6

ns

5

55

tCMOlS

CBISet-up

before MDOLE =

Lo-Hi

10

ns

56

tCMOLH .

CBI Hold

afterMDOLE=

Lo-Hi

2

ns

57

tMMOLS

MDIN Set-up

before MDOLE =

Lo-Hi

10

ns.

58

tMMOI.H

MDIN Hold

afterMDOLE =

Lo-Hi

2

ns

59

tMMCS

MDIN Set-up

before MCLK =

Lo-Hi

6

ns

60

tMMCH

MDIN Hold

after MCLK=

Lo-Hi

6

ns

61

tsSLS

SDIN Set-up

before SDILE =

Hi-Lo

4

ns

62

tSSLH

SDINHold

afterSDILE=

Hi-lo

4

ns

63

tSSCS

SDIN Set-up

before SClK

lo-Hi

4

ns

64

tsSCH

SDIN Hold

afterSClK

lo-Hi

4

ns

65

tsOOl.E

MClK (lo-Hi)

before SDOlE =

lo-Hi

8

ns

66

lENS

RIW Buffer Enable Set-up

before SIM ClK =

lo-Hi

4

ns

3,4,5,6

67

tENH

RIW Buffer Enable Hold

after S/M ClK =

lo-Hi

4

ns

3,4,5,6

68

tos

RIW Buffer Data In Set-up

before SIM ClK =

lo-Hi

2

ns

3

69

tOH

RIW Buffer Data In Hold

after S/M CLK =

lo-Hi

6

ns

3

70

tRSS

RS1 (Hi-lo)

RlWBEN=

Hi-lo

12

ns

7

71

tMOOS

Mode DataSet-up

before SClK =

lo-Hi

5

ns

8

72

tMOOH

Mode Data Hold

afterSClK=

lo-Hi

1

ns

8

73

tMENS

Mode Enable Set-up

before SClK =

Lo-Hi

2

ns

8

74

tMENH

Mode Enable Hold

afterSClK =

lo-Hi

6

ns

8

before SYNCLK =

High

Number

Parameter

From Input

Unit

DIAGNOSTIC SET-UP AND HOLD TIMES
75

tCSCS

CBISet-up

25

ns

76

tMSCS

MDIN Set-up

25

ns

77

tMLSCS

MDllE Set-up = High

25

ns
26171b118

NOTES:
1. (Lo-Hi) indicates lOw-to-=High transition and vice sersa.

MINIMUM PULSE WIDTH (PRELIMINARY)
Refer to
Timing Diagram

Description
Number

Parameter

Condition

From Input

-

Min_

Unit

6

ns

tRS

Min_ RS1 low time

79

tMLE

Min. MDllE high time

to strobe new data

MD, CBI = Valid

6

ns

80

tMOOLE

Min. MDOlE low time

to strobe new data

SD= Valid

6

ns
ns

78

to reset buffers

81

tSLE

Min. SDllE high time

to strobe new data

SD = Valid

6

82

!eLK

Min. S/MClK high time

to clock in new data

EN signal low

6

ns

83

tsVNCLK

Min. SYNClK high time

to clock in new data

-

6

ns

Figure

26171b119

UPDATE1 A

45

IDT49C466
Input Pulse Levels

Data Book A, Section 5.13, Page 17
GND t03.0V

Input Rise/FaU Times

1V/ns

Input Timing Reference Levels

1.SV
1.SV

Output Reference Levels
Out Load

See Figure 13 .
2617.bi2.

arameter
Name

Propagation Delay
To
From

Min.!

Max.

CBI Set-up to SYNCLK = High
MD Bus

MDILE

t
MDIN Set-up to SYNCLK = High

min.

tMlSCS

MDILE= HighSet:up to SYNCLK
= High

min.

tSYNClK

SYNCLK Pulse Width

min.

I

SYNCLK@
tSYNClK_

SD Bus

r

1991 Integrated Device Technology. Inc.

UPDATEl A

54

IDT49FCT805/806/A

Data Book A, Section 6.30, Page 2

PIN CONFIGURATIONS
IDT49FCT805
VCCA
2
3

19

081

18

082

Ok!
GNDA

4

OA4
OAs

6

P20-1 17
D20·1 16
5020·2 15

7

14

084
085

GNDa

8

13

MON

OEA

9

12

OEa

10

11

INa

INA

INDEX

VCCB

OAl
0A2

5

&

E20-1

I

II

3

083

OA3

GNDB

GNDA

:1 4
:1 5

OA4
OAs

:16

GNDa

U

2

,

"

II

....... ...... I

I '-'I I--'

2019
1
18[:
17[-

L20·2

:17
8

:1

082
083

16[

GNDa

15L

084
085

14[:
9 10111213

r-r,....,
I

II

r""""1I I
I

~,....,

II

II

I~ ~ ~~ ~

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

2574 drw01

2574drw02

IDT49FCT806
VCCA
OAl
0A2
OA3
GNDA'

P20-1
D20·1
5020-2
&
E20-1

19

'OBl

18

OB2

17
16

OB3
GNDa

15

084

OA4
OAs

7

14

OBs

GNDa

8

13

OE"A,

9

12

MON
UEa

10

11

INa

INA

INDEX

Vcca

6

~ I~

<

111.11
...... ....... I

3

'Ok
GNDA

2

ms
GNDa

U
1

:1
:1 5

4

OM :]6

a

1 02

2574tbiOl
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may
exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals.
3. Output and I/O terminals.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V
Commercial' TA = O°C to +70°C' VCC = 5 OV -+ 5% , Military' TA = -55°C to +125°C', VCC= 5 OV +
- 10%
Min.

Typ.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

VIL

Input LOW Level

Guaranteed Logic LOW Level

-

0.8

V

IIiH

Input HIGH Current

Vcc= Max.

-

5

J.lA

IlL

Input LOW Current

10ZH

Off State (HIGH Z)

10ZL

Output Current

VIK

Clamp Diode Voltage

Vcc = Min., IIN= -18mA

los

Short Circuit Current

Vcc = Max,(3), Vo = GND

VOH

Output HIGH Voltage

Symbol

VOL

Test Condltlons(1)

Parameter

Output LOW Voltage

Max.

Unit

V

VI = Vcc

-

Vcc = Max.

VI =GND

-

-

-5

J.lA

Vcc = Max.

Vo =Vcc

-

-

10

J.lA

-10

J.lA

-

-0.7

-1.2

V

-60

-120

-250

rnA

Vo =GND

VHC

Vcc

VHC(4)

Vcc

10H = -12mA MIL.
10H = -15mA COM'L.

3.6

4.3

-

10H = -24mA MIL.
10H = -24mA COM'L.

2.4

3.8

-

Vcc = 3V, VIN = VLC or VHC, 10L= 300fLA

-

GND

VLC

VCC = Min.

10L= 300J.lA

GND

VLC(4)

VIN = VIH or VIL

10L = 48mA MIL.

-

0.3

0.55

-

200

Vcc = 3V, VIN = VLC or VHc,loH = -321!A

Vcc = Min.

10H = -3OOI!A

VIN = VIH or VIL

V

V

10L = 64mA COM'L.
VH

-

Input Hysteresis for all inputs

-

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vec = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.

UPDATE1 A

mV
2574 Ibl 03

56

,

Data Book A, Section 6.30, Page 4

IDT49FCT805/806/A

POWER SUPPLY CHARACTERISTICS
Symbol
Icc

Parameter
Quiescent Power Supply Current

ICCD

Quiescent Power Supply Current
TTL Inouts HIGH
Dynamic Power Supply Current(4)

Ic

Total Power Supply Current(S)

L\lee

Typ.!2)

Max.

Unit

-

0.2

1.5

rnA

-

1.0

2.5

rnA

VIN= Vee
VIN=GND

-

0.15

0.25

mAl
MHz

VIN= Vee
VIN=GND

-

1.7

4.0

rnA

VIN =3.4V
VIN =GND

-

2.2

5.3

VIN = Vee
VIN= GND

-

4.3

8.4(5)

VIN =3.4V
VIN =GND

-

5.3

10.9(5)

Test Condltlons(1)
Vee = Max.
VIN = GND or Vee
Vce= Max.
VIN=3.4\f(3)
Vee = Max.
Outputs Open
OEA = OEB = GND
Per Output Toggling
50% Dutv Cvcle
Vee = Max.
Outputs Open
Ii = 10MHz
50% Duty Cycle
OEA = OEB = GND
Mon. Out out Tooolino
Vee = Max.
Outputs Open
Ii =2.5MHz
50% Duty Cycle
OEA = OEB = GND
Eleven Outputs
Tooalina

Min.

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient.
3. Per TIL driven input (VIN =3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ll.lee DHNT + loco (fCPI2 + fiND)
Icc = Quiescent Current
ll.lcc = Power Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TIL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
No = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.

UPDATE1 A

2574tbl04

57

Data Book A, Section 6.30, Page S

IDT49FCTSOS/S06/A

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT49FCT80S/806

Symbol
tPLH
tPHL

Parameter
Propagation Delay
INA to OAn, INB to OBn

tPZL
tPZH

Output Enable Time
OEA to OAn,
OEBtoOBn

tPLZ
tPHZ

Output Disable Time
OEA toOAn,
OEBto OBn

tSK(0)(3)
tSK(p) (3)
tSK(t)(3)

Condltlon(1)
CL=50pF
RL=

soon

Mln.l2)

Max.

IDT49FCT80SAl806A

Mil.

Com'l.

Mln.l 2)

Mil.

Com'l.

Max.

Min.(2)

1.S

Max.

Mln.l 2)

Max.

Unit

S.8

1.S

6.8

ns

1.5

6.5

1.5

7.5

1.5

8.0

1.S

8.S

1.S

8.0

1.5

8.5

ns

1.S

7.0

1.5

7.S

1.5

7.0

1.S

7.S

ns

-

0.7

-

0.9

-

0.7

-

0.9

ns

-

1.0

-

1.1

-

1.0

-

1.1

ns

-

1.S

-

1.5

-

1.S

-

1.5

ns

Skew between two outputs of
same~ackage-'same transition)
Skew between opposite transitions
I(tPHL -tPLH) of same output
Skew between two outputs of
different package at same power
supply voltage and temperature
I(same transition)

NOTES:
2574tbt07
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew guaranteed across temperature range but measured at maximum temperature only. Skew parameters apply to propagation delays only.

UPDATE.1 A

58

IDT49FCT805/806/A

Data Book A, Section 6.30, Page 6

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vcc

SWITCH POSITION
0--.

7.0V

soon

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFtNITIONS:
2574 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

zxt

PULSE WIDTH

-= ~~V

l

-

OV

tsu-toj+--..j

'~"~~&~~=t- ~'"

=l====~-_ 3V
~gV

TIMING - - - - - - , ....
INPUT
"
ASYNCHRONOUS CONTROL

-....
PRESET
CLEA
R
: -~-I=:::t====:.....=ETC.
SYNCHRONOUS CONTROL
CLOCK
J
""-~......~ ETC.

:~~~~~ vvir
~tsu

PROPAGATION DELAY

HIGH-LOW-HIGH
PULSE

3V
1.SV
OV

tw

_ _ 1.SV

3V
1.SV
OV

ENABLE AND DISABLE TIMES
ENABLE

DISABLE

,.----3V
,---""\. - - - - 3V

---I.SV
+----OV

CONTROLk
INPUT

SAME PHASE
INPUT TRANSITION

tPZL

OUTPUT SWITCH
NORMt~~ CLOSED

OUTPUT

-...J

tPZH

OUTPUT SWITCH

NORM~~~ OPEN

OPPOSITE PHASE
INPUT TRANSITION
'----'-----OV

3.SV
I.SV

"""'-+--'1

3.SV
VOL
VOH
OV

NOTES
2574 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate,; 1.0 MHz; Zo,; son; tF'; 2.Sns;
tR'; 2.5ns.

UPDATE1 A

59

Data Book A, Section 6.30, Page 7

IDT49FCT80S/806/A

ORDERING INFORMATION
IDT49FCT ...",..,..,X;.::X;.:;X~_
Device Type

xx
Package

x
Process/
Temperature
Range
Y:lank

P
D
~----------~E

L
SO
SOS
S06
L - - - - - - - - - - - - - I SOSA
S06A

Commercial
Military (-SSOC to +12S0C) Compliant to
MIL-STO-SS3, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Non·lnverting Buffer/Clock Driver
Inverting Buffer/Clock Driver
Fast Non·lnverting Buffer/Clock Driver
Fast Inverting Buffer/Clock Driver
2574 drw07

UPDATE1 A

60

IDT54174FBT2240/2240A

G

Data Book A, Section 6.67, Page 1
ADVANCE
INFORMATION
IDT54174FBT2240
IDT54174FBT2240A

HIGH-SPEED BiCMOS
MEMORY DRIVERS

Integrated Device Technology, Inc:.

FEATURES:

DESCRIPTION:

• IDT54/74FBT2240 equivalent to the 54/74BCT2240
• IDT54/74FBT2240A 25% faster than the 2240
• 250 output resistors reduce overshoot and undershoot
when driving MOS RAMs
Significant reduction in ground bounce from standard
CMOS devices
TTL compatible input and output levels
• Higherstatic VOH for improved noise immunity and
reduced system power dissipation
• ±10% power supply for both military and commercial
grades
JEDEC standard pinout for DIP, SOIC and LCC packages
• Military product compliant to MIL-STD-883, Class B

The FBT series of BiCMOS Memory Drivers is built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54/74FBT2240 series are octal buffers/line drivers
where each output is terminated with a 250 series resistor.
The FBT series of bus interface devices are ideal for use in
designs needing to drive large capacitive loads with low static
(DC) current loading. All data inputs have a 200mV typical
input hysteresis for improved noise rejection. The output
buffers are designed to guarantee a static VOH of 2.7V. This
higher output level in the high state results in a significant
reduction in overall system power diSSipation and improved
noise immunity when driving DRAMS and SRAMS.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

OEs
DAo

OAo

OBo

DBa

DA1

OA1

OB1

DB1

DA2

OA2

OB2

DB2

DA3

OA3

OB3

Vce

OEA
DAo
OBo
DA1
OB1
DA2
OB2
DA3
OB3
GND

2

3
4
5
6
7
8
9
10

P20·1
D20-1
8020·2
&
E20·1

19
18
17
16
15
14
13
12
11

OEs
OAo
DBo
OA1
DB1
OA2
DB2
OA3
DB3

DIP/SOIC/CERPACK
TOP VIEW

8 CB
1om 1
0

INDEX

L....J L..J

DA1
OB1
DA2
OB2
DA3

DB3

2642 drw 01

]
]
]
]
]

4
5
6
7
8

,.
r

I LJ L..J

3 2 : : 20 19
18
17
L20·2
16
15
14
9 10 11 1213

[
[
[
[
[

OAo
DBa
OA1
DB1
OA2

tB ~ ~I:( cO
IO(!jClOCl
BiCEMOS is a trademark of Integrated Device Technology, Inc.

LCC
TOP VIEW

MILITARY AND COMMERCIAL TEMPERATURE RANGES
e1991 Integrated Device Technology, Inc.

UPDATE1 A

2642 dM 02

MAY 1991
DSC1f1l1

IDT54/74FBT2240/2240A

Data Book A, Section 6.67, Page 2
FUNCTION TABLE(1)

PIN DESCRIPTION

In~uts

Pin Names

Description

OEA,OEB

3-State Output Enable Inputs (Active LOW)

Dxx
Oxx

Output

OEA,OEB

Dxx

Oxx

Inputs

L

L

H

Outputs

L

H

L

H

X

Z

2642 tbl 01

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Commercial

Military

Unit

VTERM(2) Terminal Vofiage
w~h Respect
toGND

-0.5 to +7.0

-0.5 to +7.0

V

VTERM(3) Terminal Voltage
with Respect
toGND

-0.5 to Vcc

CAPACITANCE
Symbol

-0.5 to Vcc

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

NOTE:

2642 tbl 02

(TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions Type Max. Unit

CIN

Input Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT= OV

8

12

pF

NOTE:
2642 tbl 04
1. This parameter is measured at characterization but not tested.

2642 tbl 03

1. Stressesgreaterthan those IistedunderABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.

UPDATE1 A

62

-

IDT54/74FBT2240/~240A

Data Book A, Section 6.67, Page 3

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vee = 5.0V ± 10%; Military: TA = -55°C to +125°C, Vcc = 5.0V ± 10%
Typ.(2)
Symbol
Test CondltlonS<')
Parameter
Min.

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

-

V

Vil

Input LOW Level

Guaranteed Logic LOW Level

-

-

O.B

V

IIH

Input HIGH Current

Vee = Max., VI = 2.7V

-

10

itA

III

Input LOW Current

Vee = Max., VI = 0.5V

itA

High Impedance

Vee = Max.

50

itA

10Zl

Output Current

-

-10

10ZH
II

Input HIGH Current

Vee = Max., Vee (Max.)

-

VIK

Clamp Diode Voltage

Vee = Min., IN = -lBmA

-

Vo=2.7V
Vo=0.5V

-0.7

-50
100
-1.2

itA
V

100H

Output Drive Current

Vee = Min., Va = 2.25V

-35

-

-

mA

100l

Output Drive Current

50

-

-

mA

los

Short

Vee = Min., Va = 2.25V
Vee = Max., Vo = GND(3)

-75

-

-225

mA

VOH

Output HIGH Voltage

-

V

VOL

Circu~

Current

Vee = Min.

10H=-lmA

2.7

3.B

VIN = VIH or Vil

10H= -BmA

2.4

3.3

Output LOW Voltage

VH

Input Hysteresis

Vee=5V

leeH
leez
leel

Quiescent Power
Supply Current

Vec= Max.
VIN = GND or Vee

10H = -12mA

2.0

3.2

-

IOl= 1mA

-

0.1

0.5

10l= 12mA

-

0.35

O:B

200

-

mV

-

0.2

1.5

mA

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

UPDATEl A

V

2642tb105

63

IDT54174FBT2240/2240A

Data Book A, Section 6.67, Page 4'

POWER SUPPLY CHARACTERISTICS
Symbol
lilcc

Parameter
Quiescent Power Supply
Current (Inputs TIL HIGH)

Test Conditions(ll

Min.

Vcc= Max.
VIN = 3.4V(3)

Typ.\~)

-

0.5

Max.
2.0

Unit
mA

ICCD

Dynamic Power Supply
Current(4)

Vcc = Max., Outputs Open
OEA = OEB = GND
One Input Toggling
50% Duty Cycle

VIN= Vcc
VIN=GND

-

0.3

0.40

mAl
MHz

Ic

Total Power Supply
Current(6)

Vcc = Max., Outputs Open
fi = 1OMHz, 50% Duty Cycle

VIN = Vcc
VIN=GND

-

3.2

5.5

mA

OEA = OEB .; GND
One Bit Toggling

VIN =3.4V
VIN=GND

-

3.5

6.5

Vcc = Max., Outputs Open
Ii = 2.5MHz, 50% Duty Cycle

VIN = Vcc
VIN=GND

-

6.2

9.5(5)

OEA = OEB = GND
Eight Bits Toggling

VIN = 3.4V
VIN= GND

-

8.2

17.5(5)

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25'C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vee or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
S. Ic = 10UIESCENT + !iNPUTS + IDYNAMIC
Ic = Icc + 0

.,

32: :2019
DA1
OB1
DM
OB2
DAa

DB3

]
]
]
]
]

4
5
6
7
8

18
17
L20-2 16
15
14
9 1011 12 1a

[
[
[
[
[

OAo
DBo
OA1
DB1
OA2

250
2641 drw 01

2641 drw02

LCC
TOP VIEW

BiCEMOS is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MAY 1991
DSC-601211

<01991 Integrated Device TechnologY,lnc.

UPDATE1 A

67

FUNCTION TABlE(1)

PIN DESCRIPTION
Pin Names

In~

Description

OEA,OEB

3-State Output Enable Inputs

Dxx

Inputs

Oxx

Outputs

Ou~uts

uts

Oxx

OEA,OEB

Dxx

L
L

L

L

H

H

X

H
Z

2641 tbl 01

NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

2641 tbl02

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Commercial

Military

Unit

VTERM(2) Terminal Voltage
with Respect
toGND

-0.5 to +7.0

-0.5 to +7.0

V

VTERM(3) Terminal Voltage
with Respect
toGND

-0.5 to Vee

-0.5 to Vee

V

Parameter(l)

Conditions Type Max.

Unit

CIN

Input Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT = OV

8

12

pF

Symbol

NOTE:
2641
1. This parameter is measured at chamcterization but not tested.

TA

Operating
Temperature

Oto+70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to + 150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

tbl 04

NOTES:
2641 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal
voltage may exceed Vee by +O.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 1/0 terminals only.

UPDATE1 A

68

IDT54/74FBT2244/A

Data Book A, Section 6.68, Page 3

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc= 5.0V + 10%', Military' TA = -55°C to +125°C, Vcc = 5.0V ± 10%

-

Min.

Typ.!2)

Max.

Unit

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

-

V

Vil

Input LOW Level

Guaranteed Logic LOW Level

IIH

Input HIGH Current

Vee = Max., VI = 2.7V

III

Input LOW Current

Vee = Max., VI = 0.5V

-

10ZH

High Impedance

Vee = Max.

10Zl

Output Current

-

Symbol

Test Condltlons(1)

Parameter

Vo=2.7V

-

Vo=0.5V

II

Input HIGH Current

Vee = Max., Vee (Max.)

VIK

Clamp Diode Voltage

Vee = Min., IN = -1SmA

-

10DH

Output Drive Current

Vee = Min., Vo = 2.25V

-35

10Dl

Output Drive Current

50

los

Short Circuit Current

Vee = Min., Vo = 2.25V
Vee = Max., Vo = GND(3)

VOH

Output HIGH Voltage

Vee = Min.
VIN= VIH or Vil

VOL

Output LOW Voltage
Input Hysteresis

Vee = 5V

leeH
leez
leel

Quiescent Power
Supply Current

Vee = Max.
VIN = GND or Vee

V

10

!LA

-10

!LA

50
-50

!LA

100
-1.2

!LA
V

-

mA

-

mA

-225

mA
V

V

-75

-

10H = -1mA

2.7

3.S

10H = -SmA

2.4

3.3

IOH=-12mA

2.0

3.2

-

10l= 1mA

-

0.1

0.5

0.35

O.S

200

-

mV

-

0.2

1.5

mA

10l= 12mA
VH

-0.7

O.S

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

UPDATE1 A

26411bI05.

69

IDT54174FBT2244/A

Data Book A, Section 6.68, Page 4

POWER SUPPLY CHARACTERISTICS
Symbol

Typ.(2)

Max.

Unit

-

0.5

2.0

mA

-

0.3

0.40

mAl
MHz

VIN = Vcc
VIN=GND

-

3.2

5.5

mA

OEA = OEs = GND
One Bit Toggling

VIN =3.4V
VIN=GND

-

3.5

6.5

Vcc = Max., Outputs Open
Ii = 2.5MHz, 50% Duty Cycle

VIN = Vcc
VIN =GND

-

6.2

9.5(5)

OEA = OEs = GND
Eight Bits Toggling

VIN =3.4V
VIN =GND

-

8.2

17.5(5)

Test Condltions(1)

Parameter

Min.

Alcc

Quiescent Power Supply
Current (Inputs TTL HIGH)

Vcc = Max.
VIN = 3.4V(3)

ICCD

Dynamic Power Supply
Current(4)

Vcc = Max., Outputs Open
OEA = OEs = GND
One Input Toggling
50% Duty Cycle

VIN="VCC
VIN= GND

Ic

Total Power Supply
Current(6)

Vcc = Max., Outputs Open
Ii = 1OMHz, 50% Duty Cycle

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
,2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TIL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
'5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + !.Icc DHNT + ICCD' (fcp/2 + t. Ni)
Icc = Quiescent Current
!.Icc = PoWer Supply Current for a TIL High Input (VIN = 3.4V)
DH = Duty Cycle for TIL Inputs High
NT = Number of TIL inputs at DH
IcCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
II = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

2641 tbl 06

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FBT2244
Com'l.
Symbol

Parameter

Condltlon(1)

IDT54/74FBT2244A
Com'l.

Mil.

Mil.

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

1.5

6.5

1.5

7.0

1.5

4.8

1.5

5.1

ns

Max.

Unit

tPLH
tPHL

Propagation Delay
DxxtoOxx

tPZH
tPZL

Output Enable Time

1.5

8.0

1.5

8.5

1.5

6.2

1.5

6.5

ns

tPHZ
tPLZ

Output Disable Time

1.5

7.0

1.5

7.5

1.5

5.6

1.5

5.9

ns

CL = 50pF
RL=

soon

NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

UPDATE1 A

2641 tbl07

70

IDT54/74FBT2244/A

Data Book A, Section 6.68, Page 5

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
Vee

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

O-e7.0V

soon

DEFINITIONS:
.
26411b10B
Cl = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT

Z&t

PULSE WIDTH

=t

-=_ OV
~~V

I
tsu --0
L...JL...JIIL...JL....I

3

01
01
02
02
03

]
]
]
]
]

4
5
6
7
8

2 : : 20 19

18
17
L20·2 16
15
14
9 1011 1213

'1

"

r1 "

[
[
[
[
[

07
06
Os
05
05

r1 ,-,

~ClUJv~

OZ-,OO

2640 drw02

Cl

DIP/SOIC/CERPACK
TOP VIEW

LCC
TOP VIEW

BiCEMOS is a trademark 01 Integrated Device Technology. Inc.

MAY 1991

MILITARY AND COMMERCIAL TEMPERATURE RANGES
e199' Integrated Device Technology. Inc.

UPDATE1 A

Data Book A, Section 6.69, Page 2

IDT54/74FBT2373/A

FUNCTION TABLE(1)

PIN DESCRIPTION
Pin Names

j

Description

outputs

Inputs

Do-D7

Data Inputs

Dn

LE

OE

On

LE

Latch Enables Input (Active HIGH)

H

H

L

H

OE

Output Enables Input (Active LOW)

L

H

L

L

00-07

3·State Latch Outputs

X

L

L

NC

X

X

H

Z

2640tb105

NOTE:
t. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High Impedance
NC = No Change

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

VTERM(2) Terminal Vo~age
with Respect
toGND
VTERM(3) Terminal Voltage

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

Symbol

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

PT

Power Dissipation

lOUT

DC Output Current

0.5
120

0.5
120

mA

(TA = +25°C, f = 1.0MHz)

Parameter(1)

Conditions Type Max.

Unit

CIN

Input Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT = OV

8

12

pF

NOTE:
2640 tbl 02
1. This parameter is measured at characterization but not tested.

wHh Respect
toGND
TA

2640tbl06

W

NOTES:
2640 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. No terminal voltage may
exceed Vcc by +O.5V unless otherwise noted.
2. Inputs and Vce terminals only.
3. Outputs and 1/0 terminals only.

UPDATE 1 A

74

IDT54/74FBT2373/A

Data Book A, Section 6.69, Page 3

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vee = 5.0V + 10%; Military: TA = -55°C to +125°C, VCC = 5.0V ± 10%
Typ.<2)
Test Condltlons(1)
Min.
Symbol
Parameter
2.0
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
Input LOW Level
Vil
Guaranteed Logic LOW Level
IIH
Input HIGH Current
Vee = Max., VI = 2.7V
III
Input LOW Current
Vee = Max., VI = 0.5V
-

-

Max.

-

10ZH
10Zl
II
VIK
100H
100l
los
VOH

High Impedance
Output Current
Input HIGH Current
Clamp Diode Voltage
Output Drive Current
Output Drive Current
Short Circuit Current
Output HIGH Voltage

VOL

Output LOW Voltage

VH
leeH
leez
leel

Vee = Max.

Vo=2.7V
Vo=0.5V

Vee = Max., Vee (Max.)
Vee = Min.,IN = -1SmA
Vee = Min., Vo = 2.25V
Vee = Min., Vo =2.25V
Vee = M81(., Vo =GND(3)
Vee = Min.
VIN = VIH or Vil

Input Hysteresis
Quiescent Power
Supply Current

10H = -1mA
10H= - SmA
10H = -12mA
IOl= 1mA
10l= 12mA

Vee = 5V
Vee = Max.
VIN = GND or Vee

-

-

-

-

-0.7

-35
50
-75
2.7
2.4
2.0

-

-

O.S
10
-10
50
-50
100
-1.2

-

-

-

3.S
3.3
3.2
0.1
0.35
200
0.2

-225

NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vee = 5.0V. +25 C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

0.5
O.S

1.5

Unit
V
V
I1A
I1A

ItA.
I1A
V
rnA
rnA
rnA
V

V
mV
rnA

26401b103

D

UPDATE1 A

75

IDT54/74FBT2373/A

Data Book A, Section 6.69, Page 4

POWER SUPPLY CHARACTERISTICS
Symbol
61ee

Parameter
Quiescent Power Supply
Current (Inputs TTL HIGH)

leeD

Dynamic Power Supply
Current(4)

Ie

Total Power Supply
Current(6)

Test Condltlons(1)

Min.

Vee = Max.
VIN =3.4V(3)

Typ.(2)

-

0.5

Max.
2.0

0.3

0.4

Vee = Max., Outputs Open
OE = GND, LE = Vee
One Input Toggling
50% Duty Cycle

VIN = Vee
VIN=GND

-

Vee = Max., Outputs Open

VIN= Vee
VIN=GND

-

3.2

5.5

Ii =1 OMHz, 50% Duty Cycle
OE = GND, LE = Vee
One Bit Toggling

VIN= 3.4V
VIN=GND

-

3.5

6.5

VIN = Vee
VIN=GND

-

6.2

9.5(5)

Ii = 2.5MHz, 50% Duty Cycle
OE = GND, LE = Vee
Eight Bits Toggling

VIN =3.4V
VIN=GND

-

8.2

17.5(5)

Vee

= Max., Outputs Open

rnA
mAl
MHz

NOTES.
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = laulEscENT + IINPUTS + IDYNAMIC
Ic = Icc + ,.,Icc DHNT + ICCD (fcp/2 + fl NI)
Icc = Quiescent Current
,.,Icc = Power Supply Current for a TTL High Input (VIN =3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL! inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
NI = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

UPDATE1 A

Unit

rnA

2640 tbl 04

76

IDT54/74FBT2373/A

Data Book A, Section 6.69, Page 5

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDTS4/74FBT2373
Symbol

Parameter

Condltlon(1)

IDTS4/74FBT2373A

Mil.

Com'l.
Mln.(2)

Max.

Mln.(2)

1.5

8.0

Mil.

Com'l.

IIIax.

IIIln.(2)

Max.

Mln.(2)

Max.

Unit

1.5

8.5

1.5

5.2

1.S

5.6

ns

tPLH
tPHL

Propagation Delay On to On

tPLH
tPHL

Propagation Delay LE to On

2.0

9.3

2.0

10.1

2.0

8.5

2.0

9.8

ns

tPZH
tPZL

Output Enable Time

1.5

12.0

1.S

12.S

1.5

6.5

1.5

7.5

ns

tPHZ
tPLZ

Output Disable Time

1.5

7.4

1.5

8.1

1.5

5.5

1.5

6.5

ns

tsu

Set· up Time HIGH or LOW
Onto LE
Hold Time HIGH or LOW
Onto LE
LE Pulse Width HIGH or
LOW

2.0

-

2.0

-

2.0

-

2.0

-

ns

1.5

-

1.5

-

1.5

-

1.5

-

ns

6.0

-

6.0

-

5.0

-

6.0

-

ns

tH
tw

CL = SOpF
RL= soon

NOTES:

2640tb107

1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.

UPDATEl A

77

IDT54/74FBT2373/A

Data Book A, Section 6.69, Page 6

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

e--. 7.0V

Vcc

500n

DEFINITIONS:
264011>108
CL = Load capacitance: includes jig and probe capacitance.
RT = Tennination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
~~

zzt

PULSE WIDTH

-=-w~~V
-============-*=:i=====-=J

tsu ---<>f4----I

INPUT _
TIMING
ASYNCHRONOUS CONTROL

'OW-",G~"~~=t- ~'"
t~

_ 6JV
3V

PRESET - - - - , ~-+--+---­ - 3V
CLEAR
- - + - - - - - 1.SV
ETC. - - - - '
1 - - - - - OV
SYNCHRONOUS CONTROL

HIGH-LOW-HIGH
PULSE

'--+-___

CLOCK

:~~it~ vvJr
J
~su
ETC.

- 3V
-1.5V
"'"........."..~ - OV

t

PROPAGATION DELAY

ENABLE AND DISABLE TIMES
ENABLE

SAME PHASE
INPUT TRANSITION

DISABLE

) - - . - t - - - - OV
OV
3.SV

_-..:........-.J-OUTPUT

--1.5V

VOH
-1.5V

VOL

VOL
OUTPUT SWITCH

3V

OPPOSITE PHASE
INPUT TRANSITION
' - _ _J - - - -

NORM~~~ OPEN

OV

OV

NOTES

2640 drw 04

1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate S 1.0 MHz; Zo S 50n; tF S 2.5ns;
tRS 2.5ns.

UPDATEl A

78

IDT54/74FBT2373/A

Data Book A, Section 6.69, Page 7

ORDERING INFORMATION
IDT

XX

FBT

Temperature
Range

XXXXX

X

x

Device Type

Package

Process

~~I,"k
L -_ _ _ _ _ _ _-j

1

P
D
SO
L
E

Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK

2373

Octal Transparent Latch Driver
High·Speed Octal Transparent Latch Driver

54

-55°C to +125°C

' - - - - - - - - - - - - - - 11 2373A

'-________________--11

Commercial
MIL·STD·883, Class B

I 740°C to +70°C
2640drw 03

UPDATEl A

79

IDT54/74FBT2841A/2841 B

t;;"

Data Book A, Section 6.71, Page 1

IDT54/74FBT2841A
IDT54/74FBT2841B

HIGH-SPEED BiCMOS
10-BIT MEMORY
LATCHES

Integrated De~ce Technology, Inc.

FEATURES:

DESCRIPTION:

• 250 output resistors reduce overshoot and undershoot
when driving MaS RAMs
• Significant reduction in ground bounce from standard
CMOS devices
• TIL compatible input and output levels
• Low power in all three states
• ± 10% power supply for both military and commercial
grades
• JEDEC standard pinout for DIP, SOIC and LCC
packages
• Military product compliant to MIL-STD·883, Class B

The FBT series of BiCMOS Memory Drivers are built using
advanced BiCEMOSTM, a dual metal BiCMOS technology.
This technology is designed to supply the highest device
speeds while maintaining CMOS power levels.
The IDT54/74FBT2841 series are 3-state, 10-bit latches
where each output is terminated with a 250 series resistor.
The FBT series of memory line drivers are ideal for use in
designs needed to drive large capacitive loads with low static
(DC) current loading. They are also designed for rail-to-rail
output switching. This higher output level in the high state will
result in a significant reduction in overall system power
dissipation.

FUNCTIONAL BLOCK DIAGRAM

250

Yo

Y,

Y2

Y3

V4

V8

Ve

PIN CONFIGURATIONS

2599 drw 01

INOEX
DE

Vee

00
01
D2
03
04
05
06
07
Da
09

Vo
V,
V2
V3
V4
Vs
V6
V7
Va
V9

GNO

LE

ILU () 8
ClClOZ>
-

0

0

-

>->-

LJL..JLJIILJL......JL.J

02
03
04
NC

05
06
07

432,,282726
LJ
2S[
Js
1
]6
24[
23[
J7
L28-1
22[
Ja
21 [
J9
20[
J 10
19[
J11
12 13 14 15 16 17 1a

V2
V3
V4
NC

Vs
V6
V7

1"""'1'--'1"""'1"-'''''''1'''''''1

coc»oow

cnco

ClClZZ...J>->-

2599 drw02

(!)

LCC
TOP VIEW

DIP/SOIC/CERPACK
TOP VIEW
BiCEMQS is a trademark of Integrated Device Techology. Inc,

MILITARY AND COMMERCIAL TEMPERATURE RANGES
@1991 Integrated Device Technology Inc.

APRIL 1991
DSC-001412

I

UPDATE1 A

80

FUNCTION TABLE(1)

PIN DESCRIPTION
Name

I/O

00-09

I

The latch data inputs.

LE

I

The latch enable input. The latches are transparent when LE is HIGH. Input data is latched
on the HIGH-to-LOW transition.

0

YO-Y9
OE

I

Description

The 3-state latch outputs.
The output enable control. When OE is LOW,
the outputs are enabled. When OE is high, the
outputs YI are in the high-impedance (off)
state.

Outputs

LE

01

QI

VI

H

X

X

X

Z

Function
High Z

H

H

L

L

Z

High Z

H

H

H

H

Z

HighZ

H

L

X

NC

Z

Latched (High Z)

L

H

L

L

L

Transparent

L

H

H

H

H

Transparent

L

L

X

NC

NC

2599 tbl 05

Latched

NOTE:
2599 tbl 06
1. H = HIGH, L = LOW, X = Don'tCare, NC = No Change, Z = High
Impedance

LOGIC SYMBOL
D

Internal

Inputs
OE

D
LE
LE---'-----'
OE----------~
2599 drw 03

ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
VTERM(2) Terminal Voltage
with Respect
toGND
VTERM(3) Terminal Voltage

CAPACITANCE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

with Respect
toGND
TA

Operating
Temperature

o to +70

-55 to +125

°C

TSIAS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TSTG

Storage
Temperature

-55 to + 125

-65 to +150

°C

PT

Power Dissipation

0.5

0.5

W

lOUT

DC Output Current

120

120

mA

Symbol

(TA = +25°C f = 1.0MHz)

Parameter(1)

Conditions

Typ.

Max. Unit

CIN

Input Capacitance

VIN = OV

6

10

pF

COUT

Output Capacitance

VOUT= OV

8

12

pF

NOTE:
2599tbl
1. This parameter is measured at characterization but not tested.

NOTES:
2599 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute ma:=
.'
c3~ 2

Inputs

v

0E2---.(lJ
OE3

2522 drw04

PIN DESCRIPTION
Names
UO

VI
EN

OEn

0
I

I

W

2522 drw03

LCC
TOP VIEW

OE1

I

Vs

nnnnnnn

CP
EN _ _ _-'
CLR _ _ _ _---'

CP

V1
V2
V3
NC
V4
Vs

FUNCTION TABlES(1)

D

I

III1III

~ '3' '2' L..I1 28 2-i 26
:]5
25[:
:]6
24[:
:]7
23[:
:]8
L28-1
22[:
:]9
21[:
05 :]10
20[:
Os :]11
19[:
12131415161718

lOGIC SYMBOL

CLR

II

01
D2
D3
NC
D4

DIP/SOIC/CERPACK
TOP VIEW

I

CO)

0

IIIII

2522 drw02

DI

U

C'\I.....

WIWO uW
al 002>10>-

Description .
The D flip-flop data inputs.'

When the clear input is LOW and OE is
LOW, the 01 outputs are LOW.. When
the clear input is HIGH, data can be
,
entered into the register.
Clock Pulse for the Register; enters
data into the register on the LOW-toHIGH transition.
The register three-state outputs.

Internall
Out uts
QI
VI

OE(2)

CLR

EN

01

CP

L
L

H
H

L
L

L
H

i
i

H
L

Z
Z

L
H
L
H
L
L
H
H

L
L
H
H
H
H
H
H

X
X
H
H
L
L
L
L

X
X
X
X
L
H
L
H

X
X
X
X

L
L
NC
NC
H
L
H

Z
L
Z
NC
Z
Z
H
L

i
i
i
i

L

Function
High Z
Clear
Hold
. Load

2522tbi 05

NOTE:
,
. 1. H=HIGH
L=LOW
X=Don't Care
NC= No change
i = LOW-to-HIGH Transition
Z = High Impedance
2, 'oE is an Active-High internal signal produced as follows:

Clock Enable. When the clock enable is
LOW, data on the 01 input is transferred
to the 01 output on the LOW~to-HIGH
clocl< transition. When the clocl< enable
is HIGH, the 01 outputs do not change
state, regardless of the data or clock.
input transitions.
Output c.ontrol. When any OEn input is
HIGH, the VI outputs are in the high
impedance staie. When all OEn inputs
are LOW, the TRUE register data. is
present at the VI outputs.

OE1

OE2

OE3

OE

H

X

X

L

X

H

X

L

X

X

H

L

L

L

L

H
25221b105.

2522 tbl 04

Ui>DATE1 A

89

IDT54n4FCT826AT/BT/CT
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)
Svmbol
RatinQ
VTERM(2) Terminal Vonage
with Respect to
GND
VTERM(3) Terminal Vonage
with Respect to
GND
TA
TBIAS
TSTG
PT
lOUT

Operating
Temperature
Temperature
Under Bias
Storage
Temperature
Power Dissipatior

CAPACITANCE

CommercIal
-0.5 to +7.0

Military

Unit

-0.5 to +7.0

V

-0.5 to Vee

-0.5 to Vee

V

Oto+70

-55 to +125

°C

-55 to +125

-6510+135

°C

-55 to +125

-65to+150

°C

DC Output
Current

0.5

0.5

W

120

120

mA

(TA = +25°C,

f = 1.0MHz)

Conditions

T~

Max.

Unit

CIN

Input
Capacitance

VIN = OV

6

10

pF

COUT

Output
Capacitance

VOUT= OV

S

12

pF

Parameter!!)

Symbol

2522tbl02
NOTE:
1. This parameter is measured at characterization, but is not production
tested.

NOTE:
25221blOt
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed Vcc by +0.5V unless otherwise noted.
2. Input and Vee terminals only.
3. Outputs and 110 terminals only.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = O°C to +70°C, Vcc = 5.0V ± 5%; Military: TA = ·55°C to +125°C, Vcc = 5.0V ± 10%
Min.

Tvp.(2)

VIH

Input HIGH Level

Guaranteed Logic HIGH Level

2.0

Vil

input LOW Level

Guaranteed Logic LOW Level

IIH

input HIGH Current

Vee = Max.

VI = 2.7V

III

Input LOW Current

Vee = Max.

VI = 0.5V

-

-

10ZH

High Impedance Output Current

Vee = Max.

Vo= 2.7V

-

VO= 0.5V

-

-0.7

-1.2

V

-60

-120

-225

mA

10H = -6mA MIL.
10H = -SmA COM'L.

2.4

3.3

-

V

10H = -12mA MIL.
10H = -15mA COM'L.

2.0

3.0

-

V

10l = 32m A MIL.
10l = 4SmA COM'L.

-

0.3

0.5

V

-

200

-

mV

0.2

1.5

mA

Svmbol

Test Conditions!!)

Parameter

10Zl
II

Input HIGH Current

Vee = Max., VI = Vee (Max.)

VIK

Clamp Diode Voltage

Vee = Min.,IN=-ISmA

los

Short Circuit Current

Vee = Max.(3), Vo= GND

VOH

Output HIGH Voltage

Vee = Min.
VIN = VIH or Vil

Val

Output LOW Voltage

VH

Input Hysteresis

Icc

Quiescent Power Supply Current

Vee = Min.
VIN = VIH or Vil

Vee = Max.
VIN = GND or Vee

-

NOTES:
1. For conditions shown as Max. or Min. use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25'C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.

UPDATE1 A

Max.

Unit

-

V

O.S

V

5

JlA

-5

JlA

10

JlA

-10
20

JlA

25221bl03

90

IDT54174FCT826AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS
Symbol

Test Condltlons(1)

Parameter

.<1lcc

Quiescent Power Supply Current
TTL Inputs HIGH

Vcc= Max .
VIN = 3.4V(3)

ICCD

Dynamic Power Supply Curren~4)

Vcc= Max.
Outputs Open
OE=EN=.GND

Min.

Typ.(2)

Max.

Unit

-

0.5

2.0

rnA

0.15

0.25

mAl
MHz

-

1.7

4.0

rnA

VIN =3.4V
VIN =GND

-

2.2

6.0

VIN = Vcc
VIN =GND

-

4.0

7.8(5)

VIN= 3.4V
VIN=GND

-

6.2

16.8(5)

VIN = Vcc
VIN=GND

One Input Toggling
50% Dutv Cvcle
Total Power Supply Curren~6)

Ic

Vcc= Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
OE = EN=GND
One Bit Toggling
atfi=5MHz
50% Dutv Cvcle
Vcc= Max.
Outputs Open
fcp= 10MHz
50% Duty Cycle
OE = EN=GND
Eight Bits Toggling
at fi = 2.5MHz
50% Dutv Cvcle

VIN = Vcc
VIN =GND

NOTES:
1. For conditions shown as Max. or Min., use appropriale value specified under Electrical Characteristics ·for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at Vec or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ic = 10UIESCENT + hNPUTS + IDYNAMIC
Ic = Ice + dlcc DHNT + IceD (fcp/2 + flNI)
Ice = Quiescent Current·
.
dlcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
IceD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
ft = Input Frequency
NI = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.

2522tbl 06

=

UPDATE1 A

91

IDT54174FCT826AT/BT/CT
HIGH·PERFORMANCE CMOS BUS INTERFACE REGISTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT826AT

Symbol
tPLH
tPHL

Parameter
Propagation Delay
CP to V I (OE = LOW)

Conditlons(1) Mln,<2)
CL= 50pF
RL = 500n
CL = 300pF(3)
RL= 500n
CL= 50pF
RL = 500n

Mil.

Com'l.

Test

IDT54/74FCT826BT

Max. Mln.(2) Max. Mln,<2

IDT54/74FCT826CT
Com'l.

Mil.

Com'l.

Max. MlnP

Max. Min.(2

Mil.

Max. Mln.(2 Max.

Unit
ns

-

10.0

-

11.5

-

7.5

-

8.5

-

6.0

-

7.0

-

20.0

-

20.0

-

15.0

-

16.0

-

12.5

-

13.5

tsu

Set-up Time HIGH or LOW
DltoCP

4.0

-

4.0

-

3.0

-

3.0

-

3.0

-

3.0

-

ns

tH

Hold Time HIGH or LOW
DltoCP

2.0

-

2.0

-

1.5

-

1.5

-

1.5

-

1.5

-

ns

tsu

Set-up Time HIGH or LOW
EN toCP

4.0

-

4.0

-

3.0

-

3.0

-

3.0

-

3.0

-

ns

tH

Hold Time HIGH or LOW
ENtoCP

2.0

-

2.0

-

0

-

0

-

0

-

0

-

ns

-

14.0

-

15.0

-

9.0

-

9.5

-

8.0

-

8.5

ns

6.0

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns

7.0

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns

6.0

-

7.0

-

6.0

-

6.0

-

6.0

-

6.0

-

ns

-

12.0

-

13.0

-

8.0

-

9.0

-

7.0

-

8.0

ns

-

23.0

-

25.0

-

15.0

-

16.0

-

12.5

-

13.5

-

7.0

-

8.0

-

6.5

-

7.0

-

6.0

-

6.0

-

8.0

-

9.0

-

7.5

-

8.0

-

7.0

-

7.0

tPHL

Propagation Delay, CLR to

tREM

VI
Recovery Time CLR to CP

tw
tw

Clock Pulse Width
HIGH or LOW
CLR Pulse Width

tPZH

LOW
Output Enable Time OE

tPZL

to VI

tPHZ
tPLZ

CL = 50pF
RL = 500n
CL = 300pF(3)

Output Disable Time OE

RL = 500n
CL = 5pF(3)

to VI

RL = 500n
CL= 50pF
RL - 500n

NOTES:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.

UPDATE1 A

ns

2522 tbl 07

92

IDT54174FCT826AT/BT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS

SWITCH POSITION
-7.0V

Vcc

soon

soon

~

.1::::=

OV

3V

LOW-HIGH-LOW
PULSE

3V
I.SV

HIGH-LOW-HIGH
PULSE

tREM

XI

OV

xxtts~-

Open

- 3V
-

I.SV
OV

PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.

All Other Outputs

PULSE WIDTH

TIMING
INPUT
ASYNCHRONOUS CONTROL

Closed

. x : X X - I.SV
tH

xxtt:u

Switch

DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT

Test
Open Drain
Disable Low
Enable Low

.,.

.

4-tH

- 3VI.SV
-

XXX-

PROPAGATION DELAY

OV

ENABLE AND DISABLE TIMES
ENABLE

DISABLE
~--3V

~--,-:----3V

CONTROL
INPUT

.
SAME PHASE
INPUT TRANSITION

OUTPUT _
NORMALLY
LOW

OUTPUT

---I.SV
'--~~-'·+------OV
....-.,>-1

are connected to A and C ports, respectively. The B port is
connected to the system data bus.
Under the control of the path selection input 80 (81 =
LOW) and the direction control signals, DAB and DCB, data
is transferred between the processor data bu!) and the two
memory banks. Thisimplementation uses less components
and control logic than a discrete implementation using
transceivers.

.....----<>1 B

C

~~N~ 1
SELECT

4A

4B
Figure 4. Interleaved Memory Data Path Application

UPDATE1 A

108

IDT49FCT804 TRI-PORT BUS MULTIPLEXER

APPLICATION NOTE AN-84

MULTIPROCESSOR SYSTEM DATA
COMMUNICATION APPLICATION
Figure SA shows the block diagram of a multiprocessor
(P1, P2 and P3) system coupled through the BUSMUX. The
scheme is explained in detail in Figure 5B. The three processors are operating in parallel. There is a central host
processor which divides the problem into parallel segments
and allocates the code and data among the three processors.
Eventually, the three processors need to communicate with
each other to pass and update the results. The BUSM UX is
used as the communication channel.

The host processor controls the arbitration between the
three processor requests and achieves transfer of the data
by applying the proper signals to the BUSMUX. The key
advantages of this scheme are reduced component count
leading to a compact layout and fast operation.

CONCLUSION
The IDT49FCT804 three-port BUSMUX is ideally suited
for applications involving inter-bus communication. The key
benefits of using the BUSMUX are simplified system design,
ease of control, savings in space and power dissipation and
an overall improvement in the system performance.

CONTROL
PROC
DIR_CTL
PATH_CTL
OE
49FCT804
PROC1

B

PROC2

C

DBUS

D BUS
A
DBUS

PROC3

5A

5B
Figure 5. Multiprocessor System Application

UPDATEl A

109

1990/1991 SPECIALIZED MEMORIES DATA BOOK

II

1991 DATA BOOK UPDATE 1
TABLE OF CONTENTS

LAST BK.

UPDATE PG.

1990/91 SPECIALIZED MEMORIES DATA BOOK UPDATES
PARTIALLY UPDATED DATA SHEETS
IDT10484
4K x 4 ECl 10K SRAM (Corner Power) ............... ......... ....... ...... ........ 85.1. ............
4K x 4 ECl 100K SRAM (Corner Power) ................... ... .......... ....... .... 85.1 ... ....... ...
IDT100484
IDT101484
4K x 4 ECl 101K SRAM (Corner Power) ........................................... 85.1 .............
IDT10A484
4K x 4 ECl 10K SRAM (Corner Power) .......... ......... ........ ....... ....... .... 85.2... ..........
IDT100A484
4K x 4 ECl 100K SRAM (Corner Power) ........................................... 85.2.............
IDT101A484
4K x 4 ECl 101 K SRAM (Corner Power) ........................................... 85.2 .............
64K x 1 ECl 10K SRAM ................. ........ ...... ..... ............... ....... ....... .... 85.3 .............
IDT10490
64K x 1 ECl 100K SRAM ................................................................... 85.3 .............
IDT100490
IDT101490
64K x 1 ECl 101K SRAM ................................................................... 85.3 .............
IDT10496RL
16K x 4 Self-Timed Reg Input, latch Output ........... ,.......................... 85.6.............
IDT100496Rl
16K x 4 Self-Timed Reg Input, latch Output ...................................... 85.6.............
IDT101496Rl
16K x 4 Self-Timed Reg Input, latch Output ...................................... 85.6.............
IDT10506Rl
64K x 4 Self-Timed Reg Input, latch Output... ..... .... ....... ...... ....... ...... 85.11. ..........
64K x 4 Self-Timed Reg Input, latch Output ...................................... 85.11 ...........
IDT100506Rl
IDT101506Rl
64K x 4 Self-Timed Reg Input, latch Output ...................................... 85.11 ...........
IDT7251
512x18-8it-1Kx9-8it8iFIFO ....................................................... 86.19 ...........
IDT72510
512x18-8it-1Kx9-8it8iFIFO ....................................................... 86.19 ...........
IDT7252
512x18-8it-1Kx9-8it8iFIFO ....................................................... 86.19 ...........
512x18-8it-1Kx9-8it8iFIFO ....................................................... 86.19 ...........
IDT72520
IDT72511
512 x 18-8it 8iFIFO ............................................................................ 86.20...........
IDT72521
512 x 18-8it 8iFIFO ............................................................................ 86.20 ...........
IDT7030
8K (1 K x 8) Dual-Port RAM (MASTER) .............................................. 87.2 .............
IDT7040
8K (1 K x 8) Dual-Port RAM (SLAVE) .................................... ;............. 87.2.............
IDT7010
9K (1 K x 9) Dual-Port RAM (MASTER) .............................................. 87.3 .............
IDT70104
9K(1 K x 9) Dual-Port RAM (SLAVE) ................. ;................................ 87.3.............
IDT7M81006
64K x 16 Dual-Port Static RAM Module ............ ........ ..... ........... .......... 88.7... .... ......
IDT7M81008
32K x 16 Dual-Port Static RAM Module .............................................. 88.7.............
IDT7M1002
16K x 32 Dual-Port Stalic RAM Module .............................................. 88.9 .............
IDT7MP4034
256K x 8 CMOS Stalic RAM Module ............................................... ;.. 88.22...........
IDT7M84040
256K x 9 CMOS Static RAM Module .................................................. 88.26...........
IDT7MC4032
16K x 32 CMOS Static RAM Module w/Separate Data 110 ................. 88.35 ...........
IDT7MP4031
16K x 32 CMOS Stalic RAM Module. ......... ..... ..... ........... ...... ...... ....... 88.36 ........ ...
IDT7MP4036
64K x 32 CMOS Stalic RAM Module. ........... ..... ....... ....... ...... ....... ...... 88.39. .... ... ...
IDT7MP4045
256K x 32 CMOS Static RAM Module ................................................ 88.40 ...........

8-2
8-2
8-2
8-2
8-2
8-2
8-2
8-2
8-2
8 -3
8 -3
8 -3
8 -3
8-3
8 -3
8-3
8-3
8-3
8-3
8-6
8-6
8 -8
8 -8
8 -9
8 -9
8 - 10
8 - 10
8 - 15
8 - 17
8 - 18
8 -18
8 - 20
8 - 21
8 - 22

UPDATED FULL DATA SHEETS
16K x 4 ECl 10K SRAM .....................................................................
IDT10494
IDT100494
16K x 4 ECl 100K SRAM ...................................................................
IDT101494
16K x 4 ECl 101K SRAM ...................................................................
IDT7Ml001
128K x 8 Dual-Port Static RAM Module ..............................................
IDT7Ml003
64K x 8 Dual-Port Stalic RAM Module ................................................
IDT7MP4047
512K x 16 CMOS Stalic RAM Module ................................................

8 - 26
8 - 26
8 - 26
8 - 35
8 - 35
B - 50

85.4 .............
85.4 .............
85.4.............
88.4 .............
88.4 .............
88.34...........

NEW DATA SHEETS AND APPLICATION NOTES
lKx4ECll0KSRAM ............................................................................................... 8-58
IDT10474
lOTI 00474
1K x 4 ECl lOOK SRAM ............................................................................................. 8 - 58
IDT101474
lKx4ECll01KSRAM ............................................................................................. 8-58
IDT10A474
1K x 4 ECl 10K SRAM............................................................................................... 8 - 67

LAST BK.

UPDATE PG.

1990/91 SPECIALIZED MEMORIES DATA BOOK UPDATES (Continued)
NEW DATA SHEETS AND APPLICATION NOTES (ContInued)
IDT100A474
1K x 4 ECl 100K SRAM.............................................................................................
IDT101 A474
1Kx4ECl101KSRAM .............................................................................................
IDT10480
16K x 1 ECl 10K SRAM.............................................................................................
IDT100480
16Kx1 ECl10KSRAM .............................................................................................
IDT101480
16K x 1 ECl 10K SRAM.............................................................................................
IDT10514
256Kx4ECl10KSRAM ...........................................................................................
IDT100514
256K x 4 ECl 10K SRAM ...........................................................................................
IDT101514
256Kx4ECl10KSRAM ...........................................................................................
IDT10596RR
32K x 9 ECl 10K SRAM.............................................................................................
IDT100596RR
32K x 9 ECl 10K SRAM .............................................................................................
IDT101596RR
32K x 9 ECl 10K SRAM.............................................................................................
IDT7099
36K (4K x 9-Bit) Synchronous Dual-Port RAM ...........................................................
Subsystems Custom Module Capabilities ........ ..... ...... ........ ....... ..................... ............. ....... ....... ... ...... ... ....... ..... ...
IDT71 M024
128K x 8 CMOS Static RAM Module ..........................................................................
IDT7M1011
1K x 36 CMOS Dual-Port Static RAM Module............................................................
IDT7M1012
2K x 36 CMOS Dual-Port Static RAM Module............................................................
IDT7M4048
512 x 8 CMOS Static RAM Module - Military ...........................................................
IDT7M4048
512 x 8 CMOS Static RAM Module - Commercial ...................................................
IDT7MB4048
512 x 8 CMOS Static RAM Module - Commercial ...................................................
IDT7M4068
256K x 8 CMOS Static RAM Module - Military .........................................................
IDT7M4068
256K x 8 CMOS Static RAM Module - Commercial .................................................
IDT7MB4068
256K x 8 CMOS Static RAM Module - Commercial .................................................
IDT7M4077
256K x 32 BiCMOS/CMOS Static RAM Module .........................................................
IDT7M7004
32K x 32 CMOS EEPROM Module ............................................................................
IDT7M7005
32K x 16 SMOS SRAM/EEPROM Module .................................................................
IDT7MB4064
64K x 16 BiCMOS Static RAM Module.......................................................................
IDT7MB4065
256K x 20 BiCMOS/CMOS Static RAM Module .........................................................
IDT7MB4066
256K x 16 BiCMOS/CMOS Static RAM Module .........................................................
IDT7MB4067
256K x 32 CMOS Static RAM Module ........................................................................
IDT7MB6139
Dual (16K x 60) Data/Instruction Cache Module for IDT79R3000 CPU .....................
IDT7MP1021
128K x 8 CMOS Dual-Port Static RAM Module..........................................................
IDT7MP1023
64K x 8 CMOS Dual-Port Static RAM Module............................................................
IDT7MP4046
256K x 16 CMOS Static RAM Module ........................................................................
IDT7MP6074
256K IDT79R4000 Secondary Cache Module Block Family......................................
IDT7MP6084
1MB IDT79R4000 Secondary Cache Module Block Family.......................................
IDT7MP6094
4MB IDT79R4000 Secondary Cache Module Block Family.......................................
IDT7MP6085
128K Byte CMOS Secondary Cache Module for the Intel™ i486™ ...........................
IDT7MP6087
256K Byte CMOS Secondary Cache Module for the Intel™ i486™ ...........................
IDT7MP6086
128K Byte CMOS Secondary Cache Module for the Intel™ i486™ ...........................
IDT7MP9244AT
Fast CMOS 32-Bit Buffer/Line Driver and Bidirectional Transceiver Modules ...........
IDT7MP9244CTZ
Fast CMOS 32-Bit Buffer/Line Driver and Bidirectional Transceiver Modules ...........
IDT7MP9244T
Fast CMOS 32-Bit Buffer/Line Driver and Bidirectional Transceiver Modules ...........
IDT7MP9245AT
Fast CMOS 32-Bit Buffer/Line Driver and Bidirectional Transceiver Modules ...........
IDT7MP9245CTZ
Fast CMOS 32-Bit Buffer/Line Driver and Bidirectional Transceiver Modules ...........
IDT7MP9245T
Fast CMOS 32-Bit Buffer/Line Driver and Bidirectional Transceiver Modules ...........
The Subsystem's "FlexiPak™" CMOS Module Family ..........................................................................................
AN-83
Width Expansion of SyncFIFOsTM (Clocked FIFOs) ...................................................

B - 67
B-67
B -76
B-76
B -76
B-85
B - 85
B-85
B - 94
B - 94
B - 94
B - 104
B - 113
B - 114
B - 122
B - 122
B - 130
B - 139
B - 139
B - 148
B - 157
B - 157
B - 166
B - 174
B - 180
B - 191
B - 198
B - 205
B - 212
B - 218
B - 226
B - 226
B - 227
B - 234
B - 234
B - 234
B - 239
B - 239
B - 247
B - 256
B - 256
B - 256
B - 256
B - 256
B - 256
B - 263
B - 264

iii
.-

1991 SPECIALIZED MEMORIES DATA BOOK

Partial Changes to Data Sheets

The following section contains partial data sheets that appeared in the 1991 SPECIALIZED MEMORIES Data
Book. These data sheets had changes to less than 50%
of the overall contents. Refer to the bars above changes
to see where that section can be found in the 1991 SPECIALIZED MEMORIES Data Book. '

UPDATE1 B

-

,

IDT10/1 00/1 01484

Data Book B, Section 5.1, Page 8

AC ELECTRICAL CHARACTERISTICS

Parameter(l)

.

"

.

,'.

"--~.,--.~

IDT10/100/101A484

Data
,

Book~,

Section 5.2, Page 7

I'

AC ELECTRICAL CHARACTERISTICS

Parameter(l)

-""

~

~~.

~ ~

--,.

p

+

IDT10/1 00/1 01 A484

~

••

"'

'

-

'<;1

,

~

."

~,

Data Book B, Section 5.2, Page 8

AC ELECTRICAL CHARACTERISTICS

Parameter(l)

. . -~.

"...

~

."""~

.. ~-"',..~,,.

"''''';~-'''''-''''{''N

IDT10/100/101490

' ,'_'

AC ELECTRICAL CHARACTERISTICS

Parameter(l)

D~ta

Book B, Section 5.3, Page 8

(Over the AC Operating Range)

10490512
100490512
101490512

Test
Condition

UPDATE1 B

10490515
100490515
101490515

2

IDT10/100/101496RL .

Data Book B, Section 5.6, Page 8

AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)
10496RL12
100496RL12
101496RL12

Test
Parameter(1)

10496RL15
100496RL15
101496RL15
Unit

Condition

IDT10/100/101496RL

Data Book B, Section 5.6, Page 9

AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)
Test
Parameterl1)

10496RL10
100496RL1 0
101496RL10

10496RL12
100496RL12
101496RL12

10496RL15
100496RL15
101496RL15
Unit

Condition

IDT10/100/101506RL

Data Book B, Section 5.11, Page 8

AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)
Test
Parameter(1)

Condition

IDT7251 /725217251 0/72520

Data Book B, Section 6.19, Page 15

DC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = SV ± 10%, TA = O°C to +70°C; Military: Vee = SV ± 10%, TA = ·SsoC to +12S°C)
-------I~D17~2-51~L------,----,

ID17252L
ID172510L
ID172520L
Military

1. Measuremenls with 0.4V:;; VIN :;; Vee, DSA = DSB . is LOW a!!Q RIWA is HIGH,
data is read from Port A on the falling edge of OS>.. When CS>. is LOW and RtWA is LOW, data
is written into Port A on themR'!edge of OS\.

Data Book B, Section 6.20, Page 13

1DT72511/21

DC ELECTRICAL CHARACTERISTICS
(Commercial: Vcc = 5V ± 10%, TA = O°C to +70°C; Military: Vec = 5V ± 10%, TA =-55°C to +125°C)

I0T72511L
IDT72521L
tA

Commercial
80ns

=

I0T72511L
IDT72521L
tA

Military
80ns

=

Parameter
Standby Current

(AB = We = OS>. =

NOTES:
3. Measurements are made with outputs opentt~*11:~~¥:#!g9:.;

IDT72511/21

Data Book B, Section 6.20, Page 14

AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5V ± 10%, TA = O°C to + 70°C; Military: Vee = 5V ± 10%, TA = -55°C to + 125°C)

1. The minimum data hold time is 5ns (IOns for the Bans speed grade) when writing to the~W;f~oo.l~kgiIMf~w!l\WR!2!tfi;;

IDT72511/21

Data Book B, Section 6.20, Page 15

AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5V ± 10%, T A = O°C to + 70°C; Military: Vee = 5V ± 10%, TA = -55°C to + 125°C)

UPDATEI'B

6

IDT72511/21

Data Book B, Section 6.20, Page 16

AC ELECTRICAL CHARACTERISTICS
(Commercial: Vee = 5V ± 10%, TA = O°C to + 70°C; Military: Vee

= 5V ± 10%, TA = -55°C to + 125°C)

35

45

60

ns

14,15.20.22

tWEF

35

45

60

ns

14,15,20,22

tRFF

35

45

60

ns

14,15.21,23

tWFF

35

45

60

ns

14,15,21,23

tRAEF

Read clock edge to
Almost·Empty Flag
asserted

50

60

75

ns

20,22

tWAEF

Wr~e clock edge to

50

60

75

ns

20,22

LI

Almost-Empty Flag not
asserted
tRAFF

Read clock edge to
Almost-Full Flag not
asserted

50

60

75

ns

21,23

tWAFF

Write clock edge to
Almost-Full Flag
asserted

50

60

75

ns

21,23

IDT72511/21

Data Book B, Section 6.20, Page 27

ORDERING INFORMATION

xx
Speed

im
>5(f~

80

Commercial onlY}

.
Acces~ Time

(tA)

In ns

UPDATE1 B

7

IDT7030SA/LA/7040SA/LA

Data Book B, Section 7.2, Page 2

PIN CONFIGURATIONS

DIP
TOP VIEW

2690 drw02

IDT7030SA/LA/7040SA/LA

Data Book B, Section 7.2, Page 3

DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (Vee = 5.0V ± 10%)
7030x35
7040x35

7030 x 45(3)
7040 x 45(3)

Max. Typ. Max. Typ. Max.

Typ. Max.

7030 x 20(2)
7040 x 20(2)
Symbol

Parameter

1584

Full Standby Current
(One Port -.AII
CMOS Level Inputs,

f=

0(5)

Test Condition
One Port CEl or
CER ~ Vee - 0.2V
VIN ~ Vee - 0.2V or
Y,N ~ 0.2V Active Port

Version
SA
LA
Com'l. SA
LA

Typ.

Mil.

50
46

160
125

7030 x 25
7040 x 25
50
46
50
46

170
135
150
115

45
42
45
42

150
115
135
105

40
35

140
105

Unit
rnA

iQi1.*'Qpijwf#'.!f:t~:;;
1DT7030SA/LA/7040SA/LA

Data Book B, Section 7.2, Page 6

TIMING WAVEFORM OF READ CYCLE NO.2, EITHER SIDE(1,:U

DATAOUT

----T-------~s.....s..-S.~--I-~~~~-~

UPDATE1 B

8

IDT7030SA/LA/7040SA/LA

Data Book B, Section 7.2, Page 9

AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(8)
7030x25
7040 x 25
Min. Max.

7030 x 35
7040 x 35
Min. Max.

7030 x
7040 x 45(2)
Min. Max.

IDT7030SA/LA/7040SA/LA

Data Book B, Section 7.2, Page 15

1DT7010S/L/70104S/L

Data Book B, Section 7.3, Page 2

Unit

PIN CONFIGURATIONS

2651 drw02

UPDATE1 B

9

IDT7MB1 006/1 OOB
PIN CONFIGURATION
1 • • 67 GNO
2 • • S6GND
a • • S9Vcc

4 • • 70 LJNf
5 •• 71 L_A(I)
L_A(3)
L_A(5)
GND
L_A(7)
L_A(9)
L_BUSY(l)
L_A(II)
L_A(13)
L_A(15)
L_Dli
16 • • 82 L_BUSY(5)

8
9
10
11
12
13
14
15

• •
• •
••
••
••
.,.
••
••
••
••

72
73
74
75
76
77
78
79
80
81

17': .. 83

GND

18 • • 84 Vee
19 • • 85 L~SEM
20 • • 86

L35t'

21
22
23
24
25

L_VO(I)
L_VO(3)
L_BUSY(3)
L-'/0(5)
L-'/0(7)

••
••
••
••
• •

87
88
89
90
91

26 • • 92 GNO

27 • •
28 • •
29 • •
30. •
31 • •
32 • •
33 • •

93
94
95
96
97
98
99

L_VO(9)
L_1I0(11)
L_VO(13)
LjO(15)
Vee
GNO
GND

Data Book B, Section B.7, Page 1
(1,2)
GND 132_ .66
GND 131 • • 65
Vee
R_BUSY(O)
R_A(O)
R_A(2)
R_A(4)

130_ .64
129_ .63
128_ .62

127_ .61
126 • • SO

GND 125_ .59
R_A(6)
R_A(8)
R_BUSY(4)
R_A(10)
R_A(12)
R_A(14)
R_Iii

124_ .58
123 • • 57
122 • •
121 • •
120 • •
119 • •

56
55
54
53

118 • • 52

R_BUSY(2) 117 • • 51
GND 116 • • 50
Vee 115 • • 49
R~CS 114 • • 48
R_RIW 113 • • 47
R_IIO(O) 112 • • 46
R_IIO(2) 111 •• 45
R_BUSY(6) 110 • • 44
R_IIO(4) 109 • • 43
R_VO(6) 108 • • 42
GND 107 • • 41
R_IIO(8) 106 • • 40
R_VO(10) 105 • • 39
R_VO(12) 104 • • 38
R_VO(I') 103 • • 37
Vee 102 • • 36
R_BUSY(7) 101. .35
GND 100 • • 34

IDT7M1006/100B

Data Book B, Section 8.7, Page 4

DC ELECTRICAL CHARACTERISTICS
± 10%, TA = O°C to +70°C)

(Vcc=5.0V

IDT7MB1006

IDT7MB1008

Min.

UPDATE1 B

10

Data Book B, Section B.7, Page 5

IDT7M1006/100B
I

AC ELECTRICAL CHARACTERISTICS
(Vee = S.OV ± 10%, TA = O°C to +70°C)
-40

UPDATE1 B

11

IDT7M1 006/1 ooB

,

UPDATE1 B

Data Book B, Section B.7, Page 6

12

IDT7M1 006/1 008

Data Book B, Section 8.7, Page 7

UPDATE1 B

13

IDT7MB1 00S/1 008

Data Book B, Section 8.7, Page 8

UPDATE1 B

14

Data Book B, Section 8.9, Page 1

IDT7M1002

IDT7M1002
~

~.~

-"

~

--- ""..

~.,..,

-

~.

"'''

"~,

Data Book B, Section 8.9, Page 4
........ --- --- -- .~ ~ ~

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to + 125°C or DoC to +70°C)

UPDATE1 B

15

IDT7M1002

Data Book B, Section 8.9, Page 5

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA =55°C io + 125°C or O°C to +70°C)

Unit

IDT7M1002

0

Data Book B, Section 8.9, Page 7

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = 55°C to +125°C or O°C to +70°C)

UPDATE1 B

16

Data Book B, Section 8.22, Page 1

IDT7MP4034
DESCRIPTION:

Data Book B, Section 8.22, Page 3

IDT7MP4034
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels

GND to 3.0V
Sns
1.SV

Ilo~u~tp~u~t~R~ef~er_en_c_e_L_ev_e_ls_.J• •!I1.ffi11.5.V :;:
~,• •

L Output Load

2745!bI 06

Data Book B, Section 8.22, Page 3

IDT7MP4034
AC ELECTRICAL CHARACTERISTICS(2)

UPDATE1 B

17

IDT7MB4040

Data Book B, Section 8.26" Page 4

AC ELECTRICAL CHARACTERISTICS(2)

Parameters

This parameter is guaranteed by design, but not tested.
2. 15ns, 17ns are preliminary specifications.

IDT7MC4032

Data Book B, Section 8.35, Page 2

PIN CONFIGURATION(l)

UPDATE1B

18

IDT7MC4032

Data Book B, Section 8.35, Page 5

AC ELECTRICAL CHARACTERISTICS (Continued)
(Vee = 5.0V ± 10%, TA = O°C to +70°C and -55°C to + 125°C)
Parameters

UPDATE1 B

19

IDT7MP4031

Data Book B, Section 8.36, Page 3

8

DATAoUT

lOf--'-----l-,l
Zo = son

-

-

&TM
(Typical, ns)

son

5

4

1,5V
2

drwCl

20

40

60

80

100 120 140 160 180 200

CAPACITANCE (pF)

IDT7MP4031

Data Book B, Section 8.36, Page 5

AC ELECTRICAL CHARACTERISTICS
TA = O°C TO +70°C)

UPDATEl B

20

IDT7MP4036

Data Book B, Section 8.39, Page 3

8

DATAoUT ~I'--------rn

Zo = 50n

-

~ 50n

6
tJ.TAA

(Typical, ns)

5

4
3

1.5V

2

20

40

60

80

100 120 140 160 180 200

CAPACITANCE (pF)

IDT7MP4036

Data Book B, Section 8.39, Page 4

AC ELECTRICAL CHARACTERISTICS
= 5V ±10%, TA = O°C TO +70°C)

UPDATE1 B

21

IDT7MP4036

Data Book B, Section 8.39, Page 3

8
7

1::1"-------.-=0

DATAoUT

Zo = 50Q

-

ATAA
(Typical, ns)

1

5

50Q
3

1,5V

2
drwC1

20

40

60

80

100

120 140

160 180

200

CAPACITANCE (pF)

IDT7MP4045

-

Data Book B, Section 8.40, Page 4

AC ELECTRICAL CHARACTERISTICS

NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only ..

2703 tbl 09

UPDATE1 B

22

IDT7MP4045

DATAoUT

'

Data Book B, Section 8.40, Page 3

~'f---------'~-l50r\
Zo=50Q

I1TAA

(Typical. ns)

••

5

1.5V
drwCl

20

40

60

80

100 120 140 160 180 200

CAPACITANCE (pF)

IDT7MP4045

Data Book B, Section 8.40, Page 5

AC ELECTRICAL CHARACTERISTICS

NOTES:

2703tbi09

1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.

UPDATEl B

23

UPDATE1 B

24

1991 SPECIALIZED MEMORIES DATA BOOK

Changes to Full Data Sheets

The following section contains full data sheets that appeared in the 1991 SPECIALIZED MEMORIES Data
Book. These data sheets had changes to 500/0 or more of
the overall contents and are now considered new. Refer
to the bar at the top of each page to see where that page
can be found in the 1991 SPECIALIZED MEMORIES
Data Book.

UPDATE1 B

25

I DT1 0/1 00/1 01494

Data Book B, Section 5.4, Page 1

G"

IDT10494
IDT100494
IDT101494

HIGH-SPEED BiCMOS
ECl STATIC RAM
64K (16K x 4-BIT) SRAM

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

16,384·words X 4-bit organization
Address access lime: 5/6/7/8/10/15
low power dissipation: 700mW (typ.)
Guaranteed Output Hold time
Fully compatible with ECl logic levels
Separate data input and output
JEDEC standard through-hole and surface mount
packages

The IDT10494, IDT100494 and 101494 are 65,536-bit
high-speed BiCEMOSTM ECl static random access memories organized as 16K x 4, with separate data inputs and
outputs. All 1I0s are fully compatible with ECl levels.
These devices are part of a family of asynchronous fourbit-wide ECl SRAMs. The devices have been configured to
follow the standard ECl SRAM JEDEC pinout. Becausethey
are manufactured in BiCEMOSTM technology, however, power
dissipation is greatly reduced over equivalent bipolar devices.
The asynchronous SRAMs are the most straightforward to
use because no additional clocks or controls are required:
DataouT is available an access time after the last change of
address. To write data into the device requires the creation of
a Write Pulse, and the write cycle disables the output pins in
conventional fashion.
The fast access time and guaranteed Output Hold time
allow greater margin for system timing variation. DatalN setup
time specified with respect to the trailing edge of Write Pulse
eases write timing allowing balanced Read and Write cycle
times.

FUNCTIONAL BLOCK DIAGRAM
Ao

-

•
•

•

DECODER

•
•

A13

G5,53G-BIT
MEMORY ARRAY

---------

VCC
VEE

•

•

f--

~~

01

02
03

WE

•
•
•

Do

CS

•
•

J }

I. • • • • 1
SENSE AMPS
AND READ/WRITE
CONTROL

§
1"

Qo

01

02
03

v

h

2764 drw 01

BiCEMOS is a trademark of Integrated Device Technology. Inc.

COMMERCIAL TEMPERATURE RANGE

MAY 1991
DSC-000213

If> 1991 Integrated Device Technology, Inc.

UPDATE1 B

26

IDT1 0/1 00/101494

Data Book B, Section 5.4, Page 2

PIN CONFIGURATION

300-Mil-Wide
PLASTIC SOJ PACKAGE
Y28

400-Mi/-Wide
CERAMIC PACKAGE
C28

2764 drw 02

DIP/SOJ
TOP VIEW

PIN DESCRIPTIONS

LOGIC SYMBOL

Symbol

Pin Name

Ao through A13

Address Inputs

Do through 03

Data Inputs

00 through 03

Data Outputs

Ao
A1

WE

Write Enable Input

A2

CS

Chip Select Input (Internal pull down)

VEE

More Negative Supply Voltage

Vee

Less Negative Supply Voltage

A3

A4
As

00
01
02
03

A6
2764 tbl

A7
As

01

A9
A10
A11
A12
A13

AC OPERATING RANGES(1)
I/O

VEE

Temperature

10K -S.2V±S%

o TO 7SoC. air flow exceeding 2 m/sec

100K -4.SV±S%

o TO 8SoC. air flow exceeding 2 m/see
o TO 75°C. air flow exceeding 2 m/sec

101 K -4.75V to -5.46V

2764 drw 05

16Kx4
SRAM

2764 tbl 02

NOTE:

1. Referenced 10 Vcc

TRUTH TABLE(1)

CAPACITANCE (TA=+25°C. f=1.0MHz)

cs

WE

DataouT

Typ.

Max.

Typ.

Max.

Unit

H

X

L

Input
Capacitance

4

-

3

-

pF

L

H

RAM Data

Read

L

L

L

Write

Output
Capacitance

6

DIP
Symbol
CIN

GoUT

Parameter

SOJ

-

3

-

pF

NOTE:

Function
Deselected

2764lb104

1. H=High. L=Low. X=Don'l Care
2764 tbl 03

UPDATE1 B

27

Data Book B, Section 5.4, Page 3

IDT10/100/101494

ECL-10K ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Ratln\l

Value

Unit

+0.5 to -7.0

V

o to +75

°C

-55 to +125

°C

VTERM

Terminal Voltage
With Respect to GND

TA

Operating Temperature

TBIAS

Temperature Under Bias

TSTG

Storage
Temperature

-65 to +150
-55 to +125

°C

I

Ceramic
Plastic

PT

Power Dissipation

1.5

W

lOUT

DC Output Current (Output
High)

-50

mA

NOTE:
27641b1 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This.is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

ECL-10K DC ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, RL =500 to -2.0V, TA = 0 to +75°C, air flow exceeding 2
Symbol
VOH

VOL

Parameter

mIse c)

Test Conditions

Output HIGH Voltage

V IN = V IHA or V ILB

Output LOW Voltage

VIN = VIHA or VILB

Typ.(1)

Max. (A)

Unit

TA

-1000
-960
-900

rnV

-885

-840
-810
-720

O°C
25°C
75°C

-1870
-1850
-1830

-1665
-1650
-1625

rnV

-

O°C
25°C
75°C

-1020
-980
-920

rnV

-

-

O°C
25°C
75°C

-

-1645
-1630
-1605

rnV

-

O°C
25°C
75°C

Min_ (8)

VOHC

Output Threshold HIGH Voltage

V IN = V IHB or VILA

VOLC

Output Threshold LOW Voltage

V IN = V IHB or V ILA

VIH

Input HIGH Voltage

Guaranteed Input Voltage
High for All Inputs

-1145
-1105
-1045

-840
-810
-720

rnV

-

O°C
25°C
75°C

Guaranteed Input Voltage
Low for All Inputs

-1870
-1850
-1830

-1490
-1475
'1450

rnV

-

O°C
25°C
75°C

VIL

IIH

Input LOW Voltage

Input HiGH Current

VIN = VIHA

CS

IlL

lEE

Input LOW Current

Supply Current

NOTE:
1. Typical parameters are specified at VEE

-

-

220

~A

110

~A

170

~A
~A

-

rnA

-

CS

0.5

-

Others

-50

-

90

All Inputs and Outputs
Open

-190

-130·

-

Others
VIN=VILB

27641b106

=-5.2V, TA =+25°C and maximum loading.

UPDATEl B

28

Data Book B, Section 5.4, Page 4

IDT10/100/101494

ECL-100K ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Value

Unit

+0.5 to -7.0

V

Oto +85

°C

-55 to +125

°C

VTERM

Terminal Voltage
With Respect to GND

TA

Operating Temperature

TBIAS

Temperature Under Bias

TSTG

Storage
Temperature

-65 to +150
-55 to +125

°C

PT

Power Dissipation

lOUT

DC Out mput Current (Output
High)

I

Ceramic
Plastic

1.5
-50

W
mA

27621b107
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any olher conditions
above Ihose indicated in the operational sections oflhis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

ECL-100K DC ELECTRICAL CHARACTERISTICS

.

.

-

.

(VEE = -4 5V RL =500 to -2 OV TA - 0 to +85°C air flow exceeding 2 mlsec)
. Symbol

Min. (B)

Typ.(1)

Max. (A)

Unit

VOH

Output HIGH Voltage

V IN = V IHA or V ILB

-1025

·955

-880

mV

VOL

Output LOW Voltage

V IN = V IHA or V ILB

·1810

·1715

-1620

mV

VOHC

Output Threshold HIGH Voltage

V IN = V IHB or V ILA

·1035

mV

VOLe

Output Threshold LOW Voltage

V IN = V IHB or V ILA

-

-

·1610

mV

VIH

Input HIGH Vo~age

Guaranteed Inpuf Voltage
High for All Inputs

-1165

-

-880

mV

VIL

Input LOW Voltage

Guaranteed Input Voltage
Low for All Inputs

-1810

-

-1475

mV

IIH

Input HIGH Current

VIN=VIHA

CS

-

-

220

!LA

Others

-

110

-

IlL

lEE

Parameter

Input LOW Current

Supply Current

Test Conditions

VIN=VILB

CS

0.5

Others

-50

-

-170

-110

All Inputs and Outputs
Open

NOTE:
1. Typical parameters are specified at VEE = -4.5V, TA = +25°C and maximumloading.

UPDATE1 B

170

!LA

90
rnA
27621b108

29

IDT10/1 00/1 01494

Data Book B, Section 5.4, Page 5

ECL-101K ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Value

Unit

+0.5 to -7.0

V

o to +75

°C

VTERM

Terminal Voltage
With Respect to GND

TA

Operating Temperature

TBIAS

Temperature Under Bias

-55 to +125

°C

TSTG

Storage
Temperature

-65 to +150
-55 to +125

°C

I

Ceramic
Plastic

PT

Power Dissipation

1.5

W

lOUT

DC Out mput Current (Output
High)

-50

mA

NOTE:
2763 till 09
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

ECL-101 K DC ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, RL=50Q to -2.0V, TA = 0 to +75°C, air flow exceeding 2

m/sec)
Min. (8)

Typ. Vee 0.2V or < 0.2V
L_SEM and R_SEM <: Vee. -0.2V

NOTES:
1. For IDT7Ml001 (128K x 8) version only.
2. For IDT7Ml003 (64K x 8) version only.

2803 Ibl 06

UPDATE1 B

37

IDT7M1001/3

Data Book B, Section 8.4, Page 4

DC ELECTRICAL CHARACTERISTICS
(Vcc=5.0V ± 10%, TA = -55°C to + 125°C and O°C to +70°C)
Symbol

Parameter

IDT7M1001
Min.
Max.

Test Conditions

IDT7M1003
Min.
Max.

Unit

IILlI

Input Leakage
(Address, Data & Other Controls)

Vee = Max.
VIN = GND to Vee

-

80

-

40

flA

IILlI

Input Leakage
(CSand SEM)

Vee = Max.
VIN = GND to Vee

-

10

-

10

flA

IILol

Output Leakage
(Data)

Vee = Max.
CS ~ VIH. VOUT = GND to Vee

-

80

-

40

flA

VOL

Output Low Voltage

Vee = Min.

IOL= 4mA

-

0.4

-

0.4

V

VOH

Output High Voltage

Vee = Min.

IOH = -4mA

2.4

-

2.4

-

V
2803 tbl 07

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2803 tbl 08

+5V

+5V

DATAOUT~

480Q
DATA OUT - - - . - - - 1
255Q

30 pF'

255Q

Figure 1. Output Load

Y

480Q
5pF'

Figure 2. Output Load
(for tcLZ, tCHz, tOLZ. tOHZ, tWHZ, tow)
'Including scope and jig.

UPDATE1 B

2803 drw 04

38

IDT7M1001/;3

Data Book B, Section 8.4, Page 5

AC ELECTRICAL CHARACTERISTICS
(Vcc = 5.0V ± 10%, TA = -55°C to +125°C and O°C to +70°C)
IDT7M1001Sxx IIDT7M1003Sxx
_30(5)
_35(5)

_25(5)

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

-40

Min.

Max.

Unit

Read Cycle
tRC

Read Cycle Time

25

-

30

-

35

-

40

-

ns

IAA

Address Access Time

-

25

-

30

-

35

-

40

ns

IAcs(2)

Chip Select Access Time

-

25

-

30

-

35

-

40

ns

IOE

Output Enable Access Time

-

13

-

15

-

20

-

25

ns

IOH

Output Hold From Address Change

3

-

3

-

3

3

-

ns

3

-

3

-

3

-

ns

-

18

-

20

-

20

-

20

ns

3

-

3

-

3

-

3

-

ns
ns

telZ(')

Chip Select to Output in

teHZ(')

Chip Deselect 10 Output in High

IOLl(')

Output Enable to Output in Low Z

IOHZ(')

Output Disable to Output in High

-

18

-

20

-

20

-

20

!pu(')

Chip Select 10 Power Up Time

0

-

0

-

0

-

0

-

ns

!po(')

Chip Disable to Power Down Time

-

50

-

50

-

50

-

50

ns

ISOP

sa;; Flag Update Pulse (OE or SEM)

12

-

12

-

15

-

15

-

ns

30

35

-

40

-

ns

30

35

-

ns

25

-

30

-

35

-

ns

5

-

5

5

-

ns

0

-

0

25

-

30

0
20

-

0

Low Z

3

Z
Z

WrlleCycle
twc

Write CyCle Time

25

teW(2)

Chip Select to End of Write

20

-

lAW

Address Valid to End of Write

20

-

lAS. (3)

Address Set-up to Write Pulse Time

1AS2

Address Set-up to

twp

Write Pulse Width

twR(4)

Write Recovery Time

0

tow

Data Valid to End of Write

15

toH(4)

Data Hold Time

0

-

tOHZ(')

Output Disable

-

18

twHZ(')

Write Enable to Output in High

-

18

tow(··4)

Output Active from End of Write

0

ISWRO

SEM Flag Write to Read Time

10

ISPS

SEM Flag Contention Window

10

-

13

50
35

CS Time

5
0
20

10 Output in High Z
Z

25

0

-

ns

35

-

ns

0

-

ns

25

-

30

-

ns

-

0

-

0

-

ns

-

20

-

20

-

20

ns

-

20

-

20

-

20

ns

0

ns

15

.-

15

-

ns

-

65

ns

50

ns

0

-

15
15

-

-

55

-

60

-

40

-

45

0
13

0

ns

Port·lo-Porl Delay Timing
twoo(S)

Write Pulse

1000(6)

Write Data Valid to Read Data Valid

10 Data Delay

-

NOTES:
1. This parameter is quaranteed by design but not tested.
2. To access RAM CSs Vil and SEM -

~
2754 drw OB

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2,3,5)
twc

ADDRESS

~,

)K
tAW

CS
_tAS

"1-

/"
tWR

tcw

DATAIN __________________________

-(~

tDW

~14

tDH

DATA VALID
2754 drw 09

NOTES:
1. W!; or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CSand a low W!;.
3. twR is measured from the earlier of CS or ~ going High to the end of write cycle.
4. During this period, 1/0 pins are in the output state and inputs si~s must not be applied.
5. If the CS Low transition occurs simultaneously with or after the W!; Low transitions, the outputs remain in a high impedance state.
S. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig) .. This parameter is graranteed by design, but not tested.
7. During a WE controlled writ.!.9'cle, write pulse «twp) > twHZ + tow) to allow the 1/0 drivers to turn off and data to be placed on the bus for the required
twD. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP.

UPDATE1 B

55

IDT7MP4047

Data Book B, Section 8.34, Page 7

ORDERING INFORMATION
lOT XXXX
Device
Type

x

XX

X

X

Power

Sp ed

Package

Process/
Temperature
Range

Comm~rcial
'--------------------~S

'--_ _ _ _ _ _ _ _ _ _ _ _ _

1

70

~85

1

(O°C to +70°C)

FR·4 SIP (Single In·line vertical Package)

100
120

L-------------------------------~L

}

Speed in Nanoseconds

Low Power

' - - - - - - - - - - - - - - - - - - - - - - , 7MP4047 512K x 16 CMOS Static RAM Module
2754 drw 10

UPDATE1 B

56

1991 SPECIALIZED MEMORIES DATA BOOK

New Data Sheets and App. Notes

The following section contains important new data sheets
and application notes that were not included in the 1991
SPECIALIZED MEMORIES Data Book.

UPDATE1 B

57

t;)"
lnt'eJpated Device Technology. Inc.

HIGH-SPEED BiCMOS
ECl STATIC RAM
4K (1 K X 4-BIT) SRAM

PRELIMINARY
IDT10474
IDT100474
IDT101474

FEATURES:

DESCRIPTION:

•
•
•
•
•
•
•
•

The IDT10474, IDT100474 and 101474 are 4,096-bit highspeed BiCEMOSTM ECl static random access memories
organized as 1Kx4, with separate data inputs and outputs. All
I/Os are fully compatible with ECl levels.
These devices are part of a family of asynchronous four-bitwide ECl SRAMs. This device have been configured to follow
the traditional corner-power pinout. Because they are manufactured in BiCEMOSTM technology, however, powerdissipation is greatly reduced over equivalent bipolar devices.
The asynchronous SRAMs are the most straightforward to
use because no 'additional clocks or controls are required:
DataOUT is available an access time after the last change of
address. To write data into the device requires the creation of
a Write Pulse, and the write cycle disables the output pins in
conventional fashion.
The fast access time and guaranteed Output Hold time allow
greater margin for system timing variation. DatalN setup time
specified with respect to the trailing edge of Write Pulse eases
write timing allowing balanced Read and Write cycle times.

1024-words x 4-bit organization
Address access time: 7/8/10/15 ns
low power dissipation: 600mW (typ.)
Guaranteed Output Hold time
Fully compatible with ECl logic levels
Separate data input and output
Traditional corner-power pinout
Standard through-hole and surface mount packages

FUCNTIONAL BLOCK DIAGRAM
Ao

•

•
•

•

•

DECODER

•
•

•

A9

•

•
•
•

4,096-BIT
MEMORY
ARRAY

-.- vcc
- . - VEE

••• ••
SENSE AMPS
AND READIWRITE
CONTROL

WE
CS

---+__

---+__

2758drwOl
BiCEMOS Is a trademark of Integrated Device Technology, Inc.

MAY 1991

COMMERCIAL TEMPERATURE RANGE

~.

C19911n1egrated Device Technology. Inc.

UPDATE1 B

58

IDT10474, IDT100474, IDT101474
HIGH SPEED BICMOS ECLSTATIC RAM 4K (lK

x 4-BI1)

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION
VeeA
02
Q3

Vee
01
00

Ao
A1

Os
D2

A2

D1

A3

Do

A4
As

CS
WE

NC
As
VEE

A9
AB
A7
400-Mil-Wide
CERDIP PACKAGE
024

275Bdrw 02

TOP VIEW

PIN DESCRIPTIONS
Symbol

LOGIC SYMBOL
Pin Name

AO through A9

Address Inputs

DO through D3

Data Inputs

00 through 03

Data Outputs

WE

Write Enable

CS

Chip Select Input (Internal pull down)

Ao
AI
A2
A3

VEE

More Negative Supply Voltage

A4

Vee

Less Negative Supply Voltage

1Kx4

As SRAM
As

00
01
02
03

A7

2758lbiOl

As

A9

AC OPERATING RANGES(1)
110

Temperature

VEE

10K

-S.2V ± S%

oto 7SoC, air flow exceeding 2 m/sed

lOOK

-4.SV ± 5%

a to 85°C, air flow exceeding 2 m/sed

101K

-4.7SV ± -S.46V

oto 7SoC, air flow exceeding 2 m/sed

NOTE:

2857 drw 03

2758lbl02

1. Referenced 10 Vcc.

TRUTH TABLE(1)

CAPACITANCE (TA=+25°C, f=1.0MHz)
Symbol

Parameter

DATAOUT

FUNCTION

CS

WE

Typ.

Max.

Unit

X

L

Deselected

-

H

pF

L

H

RAM Data

Read

L

L

L

Write

DIP
CIN

Input Capacitance

4

COUT

Output Capacitance

6

pF
2758 lbl 03

NOTE:
1. H=High, L=Low, X=Don'l Care

UPDATEl B

2758lblO4

59

IOT10474, IOT100474, 10T101474
HIGH SPEED BICMOS ECl STATIC RAM 4K (lK x 4-BI1)

COMMERCIAL TEMPERATURE RANGE

ECl-10K ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Value

Unit

+0.5 to -7.0

V

o to +75

°C

-55 to +125

°C

VTERM

Terminal Voltage
With Respect to GND

TA

Operating Temperature

TBIAS

Temperature Under Bias

TSTG

Storage
Temperature

-65 to +150
-55 to +125

°C

PT

Power Dissipation

1.5

W

lOUT

DC Output Current
(Output High)

-50

mA

I

Ceramic
Plastic

27581b105
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

ECl-10K DC ELECTRICAL CHARACTERISTICS
(VEE = -S.2V, RL=SOQ to -2.0V, TA = 0 to +7SoC, air flow exceeding 2 m/sec)
Symbol
VOH

Test Conditions

Parameter
Output HIGH Voltage

V IN = V IHA or V ILB

TypJl)

Max. (A)

Unit

TA

-1000
-960
-900

mV

-885

-840
-810
-720

O°C
25'C
75°C

mV

O'C
25'C
75°C

mV

O°C
25'C
75'C

Min. (B)

-1665
-1650 .
-1625

VOL

Output LOW Voltage

V IN = V IHA or V ILB

-1870
-1850
-1830

-

VOHC

Output Threshold HIGH Voltage

V IN = V IHB or VILA

-1020
-980
-920

-

-

VOLC

Output Threshold LOW Voltage

V IN = V IHB or VILA

-

-1645
-1630
-1605

mV

-

O°C
25'C
75°C

27581b105

VIH

Input HIGH Voltage

Guaranteed Input Voltage
High for All Inputs

-1145
-1105
-1045

-840
-810
-720

mV

-

O'C
25'C
75'C

VIL

Input LOW Voltage

Guaranteed Input Voltage
Low for All Inputs

-1870
-1850
-1830

-1490
-1475
-1450

mV

-

O'C
25°C
75°C

IIH

I IL

lEE

Input HIGH Current

Input LOW Current

Supply Current

NOTE:
1. Typical parameters are specified at VEE

VIN=VIHA

V IN = V ILB

CS

-

Others

-

CS

0.5

Others

-50

-

-190

-130

All Inputs and Outputs Open

220

flA

-

110

flA

-

170

flA

-

90

flA

-

-

rnA

2758 tbl 06

=-5.2V, TA =+25°C and maximum loading.

UPOATEl B

60

IOT10474, IOT100474, IOT101474
HIGH SPEEO BICMOS ECl STATIC RAM 4K (lK

x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

ECL-100K ABSOLUTE MAXIMUM RATINGS(1)
Svmbol
VTERM

Ratlna
Terminal Voltage
With Respect to GND

TA

Operating Temperature

TBIAS

Temperature Under Bias

TSTG

Storage
Temperature

-65 to +150
-55 to +125

·C

PT

Power Dissipation

1.5

W

lOUT

DC Output Current
(Output High)

-50

mA

I

Ceramic
Plastic

Value
+0.5 to -7.0

Unit
V

Oto +85

·C

-55 to +125

·C

NOTE:

2758tbl07

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

ECL-100K DC ELECTRICAL CHARACTERISTICS
(VEE

= -4.5V, Rl = son to -2.0V,

Symbol

TA

= 0 to +85°C, air flow exceeding 2 mlsec)
Min. (8)

Typ.101

Symbol

Parameter

Typ.

Max.

Typ.

Max.

Unit

-

TBD

-

pF

-

TBD

-

pF

CIN

Input
Capacitance

4

GoUT

Output
Capacitance

6

275711>103

TRUTH TABLE(1)

AC OPERATING RANGES(1)
110

VEE

10K -S.2V ±S%
lOOK -4.SV ±50/0
101K -4.7SV to -S.4SV
NOTE:

1. Referenced to Vcc

Temperature

275711>102

WE

H

X

L

L

H

RAM Data

Read

L

L

L

Wr~e

NOTE:

Data

Function

CS

oTO 7S DC, air flow exceeding 2 mlsed
o TO 85°C, airflow exceeding 2 mlsed
o TO 7S o C, air flow exceeding 2 mlsed

OUT

Deselected

275711>104

1. H=High, L=Low; X=Don'! Care

UPDATE1 B

77

IOT10480, IOT100480, IOT101480
HIGH SPEED BiCMOS ECl STATIC RAM 64K (16K x 1-BIT)

COMMERCIAL TEMPERATURE RANGE

ECL-10K ABSOLUTE MAXIMUM RATINGS(1)
Svmbol

Rating

Value

Unit

+0.5 to -7.0

V

Oto +75

·C

-55 to +125

·C

\/TERM

Terminal Voltage
With Respect to GND

TA

Operating Temperature

TBIAS

Temperature Under Bias

TSTG

Storage
Temperature

-65 to +150
-55 to +125

·C

PT

Power Dissipation

1.5

W

lOUT

DC Output Current
(Output High)

-50

mA

I

Ceramic
Plastic'

275711>105
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

ECl-10K DC ELECTRICAL CHARACTERISTICS
(VEE

= -S.2V, Rl =soo to -2.0V,

Symbol
VOH

VOL

VOHC

TA

= 0 to +7SoC , airflow exceeding 2 m/sec)

Parameter
Output HIGH VoHage

Output LOWVoltage

Output Threshold HIGH Voltage

Test Conditions
V IN = V IHA or V ILB

V IN = V IHA or V ILB

VIN=VIHBor VILA

TypJl)

Max. (A)

Unit

TA

-1000
-960
-900

mV

-885

-840
-810
-720

O·C
25°C
75°C

-1870
-1850
-1830

-1665.
-1650
-1625

mV

-

O·C
25·C
75·C

-1020
-980
-920

mV

-

-

o·e
25·C
75·C

-

-

-1645
-1630
-1605

mV

O·C
25·e
75·C

Min. (8)

VOLC

Output Threshold LOW Voltage

V IN = V IHB or VILA

VIH

Input HIGH VoHage

Guaranteed Input Voltage
High for All Inputs

-1145
-1105
-1045

-840
-810
-720

mV

-

O·C
25·e
75·C

Guaranteed Input VoHage
Low for All Inputs

-1870
-1850
-1830

-1490
-1475
-1450

mV

-

o·e
25·e
75°C

-

.220

-50

-

-170

-80

VIL

IIH

Input LOW Voltage

Input HIGH Current

VIN=VIHA

CS
.Others

IlL

Input LOW Current

VIN = VILl3

lEE

Supply Currerit

All Inputs and Outputs
Open

CS
Others

NOTE:
1. Typical parameters are specified at VEE = -5.2V, TA = +25°C and maximum loading.

UPOATE1 B

0.5

~A

-

110

~

-

170

~A

...

90

~A

-

rnA

275711>106

78

IDT10480, IDT100480, IDT101480
HIGH SPEED BICMOS ECL STATIC RAM 64K (16K

X

COMMERCIAL TEMPERATURE RANGE

1-BIT)

ECL-100K ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

VTERM

Terminal Voltage
With Respect to GND

Value

Unit

+0.5 to -7.0

V

TA

Operating Temperature

o to +85

°C

TBIAS

Temperature Under Bias

-55 to +125

°C

TSTG

Storage
Temperature

-65 to +150
-55 to +125

°C

,-ceramic
Plastic

PI

Power Dissipation

1.5

W

lOUT

DC Out mput Current (Output
High)

-50

mA

NOTE:

2757 tbl 07

1. Stresses greater than those listed under ABSOLUTE MAXI MU M
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

ECL-100K DC ELECTRICAL CHARACTERISTICS
(VEE = -4.5V, RL=50Q to -2.0V, TA = 0 to +85°C, air flow exceeding 2 m/sec)
Symbol

Min. (8)

Typ.<1)

Max. (A)

VIN=VIHAor VllB

-1025

-955

-880

mV

V IN = V IHA or V IlB

-1810

-1620

mV

Output Threshold HIGH Voltage

V IN = V IHB or V ILA

-1035

Output Threshold LOW Voltage

V IN = V IHB or V ILA

-

Input HIGH Voltage

Guaranteed Input Voltage

-1165

-1715
-

-1810

-

-

CS

0.5

Others

Parameter

VOH

Output HIGH Voltage

Val

Output LOW Vo~age

VOHC
Vale
VIH

Test Conditions

Unit

-

mV

-1610

mV

-880

mV

-1475

mV

-

220

(.LA

-

170

-50
-150

-70

-

High for All Inputs
Vll

Input LOW Voltage

Guaranteed Input Voltage

,

Low for All Inputs
IIH

Input HIGH Current

VIN = VIHA

CS
Others

III

lEE

Input LOW Current

Supply Current

VIN = VllB

All Inputs and Outputs Open

(.LA

90
mA
2757 tbl 08

NOTE:

1. Typical parameters are specified at VEE

110

= -4.5V, TA = +25°C and maximum loading.

UPDATE1 B

79

IOT10480, IOT100480, IOT101480
HIGH SPEED. BICMOS ECl STATIC RAM 64K (16K x 1-BIT)

COMMERCIAL TEMPERATURE RANGE

ECL-101K ABSOLUTE MAXIMUMRATINGS(1)
Symbol

Rating

Value

Unit

+0.5 to -7.0

V

Operating Temperature

Oto +75

·C

Temperature Under Bias

-55 to +125

·C

Storage
Temperature

-65 to +150
-55 to +125

·C

VTERM

Terminal Voltage
Wnh Respect to GND

TA
TBIAS
TSTG

PT

Power Dissipation

lOUT

DC Out mput Current
(Output High)

I

Ceramic
Plastic

1.0
-50

W
mA

NOTE:
27571b109
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS'
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

ECL-101 K DC ELECTRICAL CHARACTERISTICS
(VEE = -5 2V , Rl =500 to -2 OV, TA - 0 to +75°C , air fl6w exceeding 2 mtsec)

..

Min. (8)

Typ.(1)

Max. (A)

Unit

VOH

OutputHIGH Voltage

VIN = VU-iA or VILB

-1025

-955

-880

mV

VOL

Output LOW Voltage

V IN = V IHI\ orVILB

-1810

"1715

-1620

mV

VOHC

Output Threshold HIGH Voltage

V IN = V IHB or VILA

-1035

-

mV

VOlC

Output Threshold LOW Voltage

VIN=VIHBor VILA

-

-

-1610

illV

VIH

Input HIGH Voltage

Guaranteed Input Voltage
High for All Inputs

-1165

-

~880

mV

VIL

Input LOW Voltage

Guaranteed Input Voltage
Low for All Inputs

-1810

-

-1475

mV

IIH

Input HIGH Current

VIN;,VIHA

-

220

/lA

Symbol

Parameter

Test Conditions

CS

0.5

-

Others

-so

-

90

Allinpuis and OiJIP~ls
Open

-170

-80

-

CS
Others

IlL

lEE

Input lOW Current

Supply Current

NOTE:
1. Typical parameters are specified at Vee

VIN=VILB

',. '

110
170

!!A
rnA
27571bll0

= -5,2V. TA = +25·C and maximum loading.

UPOATE1 B

80

IOT10480, IOT100480, 10T101480
HIGH SPEED BICMOS ECL STATIC RAM 64K (16K x 1-BIT)

COMMERCIAL TEMPERATURE RANGE

AC TEST LOAD CONDITION

AC TEST IN.PUT PULSE

VCC(GND)

J2

DATAouT

50n

0.011l F

.I.

VEE

r

.

30PF

yO%

tF
tR =tF =2.0ns typo
Note: All timing measurements are
referenced to 50% input levels.
tR

*

-2.0V
*Includes ~robe and
jig capacitance

2757 drwOB

2757 drw07

RISE/FALL TIME
Symbol

Parameter

tR

Output Rise Time

tF

Output Fall Time

Test Condition

-

Min.

Typ.

Max.

Unit

-

2

ns

-

2

-

ns
2757tblll

FUNCTIONAL DESCRIPTION
The IDT10480, IDT100480 and IDT101480 BiCMOS ECl
static RAMs (SRAM) provide high speed with low power
dissipation typical of BiCMOS ECL. These devices foliow the
conventional pinout and functionality for 16Kx1 SRAMs. The
ECl -101K meets electrical specifications that combine the
ECl-100K temperature and voltage compensated output
levels with the high-speed of ECl-10K VEE compatibility
(-S.2V).

READ TIMING
The read timing on these asynchronous devices is straightforward. DataouT is held low until the device is selected by
Chip Select (CS). Then Address (ADDR) settles and data
appears on the output aftertime 1M. Note that DataouT is held
for a short time (tOH) afterthe address begins to change for the
next access, then ambiguous data is on the bus until a new
timetAA.

WRITE TIMING
To write data to the device, a Write Pulse need be formed
on the Write Enable· input (WE) to control the write to the
SRAM array. While CS and ADDR must be set-up when WE
goes low, DatalN can settle afterthe falling edge of WE, giving
the data path extra margin. Data is written to the memory celi
at the end of the Write Pulse, and addresses and Chip Select
must be held after the rising edge of the Write Pulse to ensure
_
satisfactory completion of the cycle.
DataouT is disabled (held low) during the Write Cycle. If CS
is held low (active) and addresses remain unchanged, the
DataouT pins will output the written data after "Write Recovery
Time" (tWR).
Because of the very short Write Pulse requirement, ·these
devices can be cycled as quickly for Writes as for Reads.
Balanced cycles mean simpler timing in cache applications.

UPOATE1 B

81

III-

IDT10480, IDT100480, IDT101480
HIGH SPEED BiCMOS ECl STATIC RAM 64K (16K xl-BIT)

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)
Test
Parameter(1)

5ymbol

1048058
10048058
10148058

10480510
100480510
101480510

10480512
100480512
101480512

Max.

Min.

Max.

Min.

Max.

Unit

5

Condition

Min.

Max.

Min.

10480515
100480515
101480515

Read Cycle
tAcS

Chip Select Access Time

-

-

3

-

5

-

-

3

-

5

5

-

ns

Chip Select Recovery Time

-

5

tRCS

5

ns

fAA

Address Access Time

-

-

8

-

10

-

12

-

15

ns

lOH

Data Hold from Address

-

3

-

3.5

-

3.5

-

3.5

-

ns

Change
27571b112

NOTES:
1. Input and Output reference level is 50% point of waveform.

READ CYCLE GATED BY CHIP SELECT

DATAoUT
2757 drw09

READ CYCLE GATED BY ADDRESS

ADDR

DATAoUT
2757 drw 10

UPDATE1 B

82

IDT10480, IDT100480, IDT101480
HIGH SPEED BiCMOS ECL STATIC RAM 64K (16K

x 1-BIT)

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (Over the AC Operating

Symbol

Parameter(1)

1048058
10048058
10148058

Range)

10480510
100480510
101480510

10480512
100480512
101480512

10480515
100480515
101480515

Test
Condition

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

-

9

-

10

-

10

-

2

-

5

-

5

0

-

2

-

0

-

2

2

-

3

-

ns

0

5

-

10

ns

18

ns

Wrhe Cycle

WI

Write Pulse Width

WlSA= minimum

7

WlSO

Data Set-up Time

0

WlSO:a<2)

Data Set-up Time to WE High

-

5

WlSA

Address 5et-up Time

WlSA= minimum

0

WlSCS

Chip Select 5et-up Time

0

IWHo

Data Hold Time

-

IWHA

Address Hold Time

-

1

WlHCS

Chip Select Hold Time

-

1

WlS

Write Disable Time

WlR<3)

Write Recovery Time

-

-

1

5
10

0

5
0
0
1
1
1

-

5
12

2
2

-

14

3
3

ns
ns
ns
ns
ns
ns
ns

2757tbl13
NOTES:
1. Input and Output relerence level is 50% point of waveform.
2. twSD is specified with respect to the falling edge of WE for compatibility with bipolar part specifications, but this device actually only requires tWSD2 with
respect to rising edge of WE .
3. twR=twHA + 1M and thus can include a full access time if addresses change while Chip Select is still low.

WRITE CYCLE TIMING DIAGRAM

AD DR

DATAIN
~-----tWS02~-----+I

i------tw------i
DATAoUT

~,-----tw------,'=1xxxxxxx
Z157 drw 11

UPDATE1 B

83

IDT10480, IDT100480, IDT101480
HIGH SPEED BiCMOS ECl STATIC RAM 64K (16K

x 1-BIT)

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
lOT

XXX

X

XX

X

X

Device Type

Arch itectu re

Speed

Package

Processl
Temp. Range

-----------

Commercial

L-------I--------l: :"'k
8
10

CERDIP

Speed in Nanoseconds

12
15

L-________________________ S
~I

I

Standard Architecture

10480

16K (16K x 1-bit) SiCMOS ECl-10K
Static RAM

100480

16K (16Kx Hit) SiCMOS ECl-100K
Static RAM

101480

16K (16K x 1-bit)BiCMOS ECl-1 01 K
Static RAM
2757 drw 12

UPDATE1 B

84

G"

HIGH-SPEED BiCMOS
ECl STATIC RAM
1M (256K x 4-BIT) SRAM

Integrated Device Technology, Inc.

PRELIMINARY
ID110514
IDT100514
IDT101514

FEATURES:

DESCRIPTION:

262,144-words X 4-bit organization
• Address access time: 10/12/15
low power dissipation: 900mW (typ.)
Guaranteed Output Hold time
• Fully compatible with ECl logic levels
• Separate data input and output
JEDEC standard through-hole and surface mount
packages

The IDT10514, IDT1 00514and IDT101514are 1,048,576bit high-speed BiCEMOSTM ECl static random access memories organized as 256Kx4, with separate data inputs and
outputs. All II0s are fully compatible with ECl levels.
These devices are part of a family of asynchronous fourbit-wide ECl SRAMs. The devices have been configured to
follow the standard ECl SRAM family pinout. Because they
are manufactured in BiCEMOSTM technology, however, power
dissipation is greatly reduced over equivalent bipolardevices.
The asynchronous SRAMs are the most straightforward to
use because no additional clocks or controls are required:
DataouT is available an access time after the last change of
address. To write data into the device requires the creation of
a Write Pulse, and the write cycle disables the output pins in
conventional fashion.
The fast access time and guaranteed Output Hold time
allow greater margin for system timing variation. DatalN setup
time specified with respect to the trailing edge of Write Pulse
eases write timing allowing balanced Read and Write cycle
times.

FUNCTIONAL BLOCK DIAGRAM
AD

r--

•

•

•

•

•

•

DECODER

•

0

•
•

A17

1,04B,576-BIT
MEMORY ARRAY

VCC

~

VEE

•
•

r--

~

Do
01
02

t=

03

I· •

••

·1

SENSE AMPS
AND READIWRITE
CONTROL

~!::l

- "'

Vn-

.K

~

.I

~

00
01

02

. . b>- 03

"-

2780 drwOl

BiCEMOS is a trademark of Integrated Device Technology, Inc.

MAy 1991

COMMERCIAL TEMpERATI/RE RANGE

DSC-8024'-

e 1991 Integrated Device Technology. Inc.

UPDATE1 B

85

IOT10514, IOT100514, IOT101514
HIGH SPEEO BICMOS ECl STATIC RAM 1M (256K

x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION
AI4
AI5
AIS
AI7

AI3
AI2
All
Alo

CS

A9

Do
CO

D3
03

Vee

VEE

Vee

VEE

01
01

02
D2
As

WE
Ao
AI
A2
A3

A7

As

400-Mil-Wide
CERAMIC PACKAGE
C32

A5

A4
2786 drw02

400-Mil-Wide
PLASTIC SOJ PACKAGE
Y32

TOP VIEW

LOGIC SYMBOL

PIN DESCRIPTION
Symbol

Pin Name

r--:!::o:-!:::-!::::~...,

Aothrough A17

Address Inputs

Dothrough 03
00 through 03

Data Inputs
Data Outputs

Ao
AI
A2
A3

WE

Write Enable Input

A4

CS

Chip Select Input (Internal pull
down)

VEE

More Negative Supply Voltage

Vee

Less Negative Supply VoHage

NC

No Connect (Not Internally
Connected

AC OPERATING RANGES(1)
VEE

Temperature

10K -5.2V ±5%

o TO 75°C, air flow exceeding 2 mlsec

lOOK -4.5V ±5%

.0 TO 85°C, air flow exceeding 2 mlsec

101K -4.75V to -5.46V

o TO 75°C, air flow exceeding 2 mlsec

DIP

CoUT

03

01

02

2786 drw 05

256Kx4
SRAM

TRUTH TABLE(1)

CAPACITANCE (TA=+25°C, f=1.0MHz)

CIN

As
A9

2786 Ibl 02

NOTE:
I. Referenced to Vee

Symbol

00

AlO
All
AI2
AI3
AI2
AI3
AI4
AI5
AIS
AI7

2786IbIOl

1/0

A5
As
A7

SOJ

CS

WE

Typ.

Max_

Typ.

Max.

Unit

X

L

Input
Capacitance

4

-

H

3

-

pF

L

H

RAM Data

Read
Write

6

L

L

Output
Capacitance

L

Parameter

-

3

-

pF

NOTE:
7861bl03

DATAoUT

Function
Deselected

27861b104

I. H=High. L=Low. X=Don·t Care

UPOATE1 B

86

IDT10514, IDT100514, IDT101514
HIGH SPEED BICMOS ECl STATIC RAM 1M (256K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

ECl-10K ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Value

Unit

+0.5 to -7.0

V

Oto +75

°C

-55 to +125

°C

VTERM

Terminal Voltage
W~h Respect to GND

TA

Operating Temperature

TBIAS

Temperature Under Bias

TSTG

Storage
Temperature

-65 to +150
-55 to +125

°C

I

Ceramic
Plastic

PT

Power Dissipation

1.5

W

lOUT

DC Output Current
(Output High)

-50

mA

NOTE:
2786 till 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Expcsureto absolute maximum rating conditions
for extended periods may affect reliability.

ECl-10K DC ELECTRICAL CHARACTERISTICS
(VEE = -5 2V RL=50Q to -2 OV , TA = 0 to +75°C airflow exceeding 2 m/sec)
Symbol
VOH

Parameter
Output HiGH Vo~age

Test Conditions
V IN = V IHA or V ILB

Typ.<1)

Max. (A)

Unit

TA

-1000
-960
-900

mV

-885

-840
-810
-720

O°C
25°C
75°C

mV

O°C
25°C
75°C

mV

O°C
25°C
75°C

Min. (8)

VOL

Output LOW Vo~age

VIN=VIHAor VILB

-1870
-1850
-1830

-

-1665
,-1650
-1625

VOHC

Output Threshold HIGH Voltage

V IN = V IHB or V ILA

-1020
-980
-920

-

-

VOLC

Output Threshold LOW Voltage

V IN = V IHB or VILA

-

-

-1645
-1630
-1605

mV

O°C
25°C
75°C

VIH

Input HIGH Voltage

Guaranteed Input Voltage
High for All Inputs

-1145
-1105
-1045

-

-840
-810
-720

mV

O°C
25°C
75°C

VIL

Input LOW Vo~age

Guaranteed Input Vo~age
Low for All Inputs

-1870
-1850
-1830

-

-1490
-1475
-1450

mV

O°C
25°C
75°C

IIH

Input HIGH Current

VIN=VIHA

-

-

220

).lA

-

-

110

).lA

-

CS

0.5

-

170

IlA

-

Others

-50

-

90

IlA

-

-260

-180

-

mA

CS
Others

I IL

lEE

Input LOW Current

Supply Current

VIN=VILB

All Inputs and Outputs Open

NOTE:
1. Typical parameters are specified at VEE = -5.2V, TA = +25°C and maximum loading.

UPDATE1 B

2786 till 06

87

IDT10514, IOT100514, IDT101514
HIGH SPEED BICMOS ECl STATIC RAM 1M (256K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

ECL-100K ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Value

Unit

+0.5 to -7.0

V

o to +85

·C

-55 to +125

·C

VTERM

Terminal Voltage With
Respect 10 GND

TA

Operating Temperature

TBIAS

Temperature Under Bias

TSTG

Storage
Temperature

-65 to +150

·C

PT

Power Dissipation

1.5

W

lOUT

DC Output Current
(Output High)

-50

mA

I

Ceramic

NOTE:
2786 tbl 07
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

ECL-100K DC ELECTRICAL CHARACTERISTICS
(VEE = -4.5V, RL=50Q to -2.0V, TA = 0 to +85°C, air flow exceeding 2 m/sec)
Symbol

Parameter

Min. (8)

Typ.<1)

Max. (A)

Unit

VOH

Output HIGH Voltage

V IN ~ V IHA or V ILB

-1025

-955

-880

mV

VOL

Output LOW Voltage

V IN ~ V IHA or V ILB

-1810

-1715

-1620

mV

VOHC

Output Threshold HIGH Voltage

V IN ~ V IHB or VILA

-1035

-

-

mV

VOLe

Output Threshold LOW Voltage

V IN ~ V IHB or V ILA

-

mV

Input HIGH Voltage

Guaranteed I nput Voltage

-1165

-

-1610

VIH

-880

mV

VIL

Input LOW Voltage

Guaranteed Input Voltage

-1810

-

-1475

mV

-

-

220

~A

-

110

Test Conditions

High for All Inputs
Low for All Inputs
IIH

VIN~VIHA

Input HIGH Current

CS
Others

IlL

lEE

VIN~VILB

Input LOW Current

Supply Current

NOTES:
1. Typical parameters are specified at VEE

CS

0.5
-50

-

170

Others

-240

-160

-

All Inputs and Outputs Open

~A

gO
mA
2786tbl08

~

-4.5V, TA

~

+25°C and maximum loading.

UPDATE1 B

88

IDT10514, IDT100514, IDT101514
HIGH SPEED BiCMOS ECl STATIC RAM 1M (256K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

ECL-101K ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Value

Unit

+0.5 to -7.0

V

a to +75

°C

VTERM

Terminal Voltage
With Respect to GND

TA

Operating Temperature

TalAS

Temperature Under Bias

-55 to + 125

°C

TSTG

Storage
Temperature

-65to +150
-55 to +125

°C

PT

Power Dissipation

1.5

W

lOUT

DC Out mput Current
(Output High)

-50

mA

I

Ceramic
Plastic

NOTE:

2786 tbl 09

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

ECL-101K DC ELECTRICAL CHARACTERISTICS
(VEE = -5 2V , RL=50Q to -2 OV, TA = 0 to +75°C , air flow exceeding 2 rn/sec)
Symbol

Parameter

Min_ (8)

Typ.(l)

Max_ (A)

Unit

V ILB

-1025

-955

-880

mV

VILB

-1810

-1715

-1620

mV

VILA

-1035

-

mV

V lLA

-

-1610

mV

-880

mV

Test Condition

= V IHA or
V IN = VIHA or
V IN = V IHB or
V IN = V IHB or

VOH

Output HIGH Voltage

VOL

Output LOW Voltage

VOHC

Output Threshold HIGH Voltage

VOLC

Output Threshold LOW Voltage

VIH

Input HIGH Voltage

Guaranteed Input Voltage
High for AI/Inputs

-1165

-

VIL

Input LOW Voltage

Guaranteed Input Voltage
Low for AI/Inputs

-1810

-

-1475

mV

IIH

Input HIGH Current

VIN

CS

-

-

220

itA

Others

-

110

-

IlL

lEE

Input LOW Current

Supply Current

V IN

VIN

= VIHA
= VILB

CS

0.5

Others

-50

-

-260

-180

AI/Inputs and Outputs Open

NOTES:
1. Typical parameters are specified at VEE = -S.2V. TA = +2SoC and maximum loading.

UPDATE1 B

170

itA

90
rnA
27B6tbl10

89

IDT10514, IDT100514, IDT101514
HIGH SPEED BICMOS ECl STATIC RAM 1M (256K

x 4-Bln

COMMERCIAL TEMPERATURE RANGE

AC TEST LOAD CONDITION

AC TEST INPUT PULSE

::::---UJ[

Vee (GND)

DATAoUT

50n

r

J€

20%

tF
tR = tF = 2.0ns typo
Note: All timing measurements are
referenced to 50% input levels.
tR

30PF

'

2786 drw 07

-2.0V
'Includes probe and
jig capacitance
2786 drw06

RISE/FALL TIME
Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

-

ns

tR

Output Rise Time

-

-

2

tF

Output Fall Time

-

-

2

ns
2786 !bIll

FUNCTIONAL DESCRIPTION
The IDT10S14,IDT100S14 and IDT101S14 BiCMOS ECl
static RAMs (SRAM) provide high speed with low power
dissipation typical of BiCMOS ECL. These devices follow the
JEDEC standard revolutionary pinout. The ECl-1 01 K meets
electrical specifications that combine the ECl -1 OOK temperature and voltage compensated output levels with the highspeed of ECl-10K VEE compatibility (-S.2V).
READ TIMING
The read timing on these asynchronous devices is straightforward. DataOUT is held low until the device is selected by
Chip Select (CS). Then Address (ADDR) settles and data
appears on the output alter time tAA. Note that DataOUT is
held for a short time (tOH) alter the address begins to change
for the next access, then ambiguous data is on the bus until a
new time tAA.

WRITE TIMING
To write data to the device, a Write Pulse need be formed
on the Write Enable input (WE) to control the write to the
SRAM array. While CS and ADDR must be set-up when WE
goes low, DatalN can settle after the falling edge of WE, giving
the data path extra margin. Data is written to the memory cell
at the end of the Write Pulse, and addresses and Chip Select
must be held after the rising edge of the Write Pulse to ensure
satisfactory completion of the cycle.
DataOUT is disabled (held low) during the Write Cycle. If
CS is held low (active) and addresses remain unchanged, the
DataOUT pins will output the written data after "Write Recovery Time" (tWR).
Because of the very short Write Pulse requirement, these
devices can be cycled as quickly for Writes as for Reads.
Balanced cycles mean simpler timing in cache applications.

UPDATE1 B

90

IDT10514, IDT100514, IDT101514
HIGH SPEED BiCMOS ECl STATIC RAM 1M (256K

x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (Over the

Test
Parameter(1)

Symbol

Condition

AC Operating Range)

10514510
100514510
101514510

10514512
100514512
101514512

Min_

Max.

Min.

10514515
100514515
101514515

Max.

Min.

Max.

Unit

Read Cycle

lAcs

Chip Select Access Time

-

-

5

-

5

-

5

ns

tRCS

Chip Select Recovery Time

-

5

-

5

-

5

ns

IAA

Address Access Time

-

-

10

-

12

-

15

ns

tOH

Data Hold from Address Change

-

3

-

3

-

3

-

NOTE:
1. Input and Output reference level is 50% point of waveform.

ns
2786tbl12

READ CYCLE GATED BY CHIP SELECT

DATAoUT
2786 drw 08

READ CYCLE GATED BY ADDRESS
ADDR

DATAoUT
2786 drw 09

UPDATE 1 B

91

IDT10514, IDT100514, IDT101514
HIGH SPEED BICMOS ECl STATIC RAM 1M (256K x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)

Test
Parameter<1)

Symbol

10514510
100514510
101514510

10514512
100514512
101514512

10514515
100514515
101514515

Condition

Min.

Max.

Min.

Max.

Min.

Max.

Unit

10

-

10

-

ns

2

ns

2

-

8

-

8

0

-

1
2

2

-

-

5

-

5

-

5

-

5

Write Cycle
tw

Write Pulse Width

twSA= min.

8

twSD

Data Set·up Time

-

0
6

-

tWSA= min.

0

-

-

twS02(2)

Data Set·up Time to WE High

twSA

Address Set·up Time

twscs

Chip Select Set-up Time

-

0

tWHO

Data Hold Time

2

tWHA

Address Hold Time

-

tWHCS

Chip Select Hold Time

-

2

tWHS

Write Disable Time

twR(3)

Write Recovery Time

-

-

2

5

0

0
2
2

1
2

ns
ns
ns
ns
ns
ns
ns

ns
NOTES:
2786 tbt 13
1. Input and OU!put reference level is 50% point of waveform.
2. twSD is specifted with res,Q!l!;t to the falling edge of WE for compatibility with bipolar part specifications, but this device actually only requires twSD2 with
respect to rising edge of WE .
3. tWA is defined as the time to reflect the newly written data on the Data Outputs (00 to 03) when no new Address Transition occurs.

5

WRITE CYCLE TIMING DIAGRAM

ADDR

DATA IN
~---------tWS02--------~

WE
~--------- tw--------~

DATAoUT
2786 drw 10

UPDATE1 B

92

IDT10514, IDT100514, IDT101514
HIG.H SPEED BICMOS ECl STATIC RAM 1M (256K

x 4-BIT)

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
lOT

XXX
::---:--::--Device Type

X

XX

X

x

Architecture

Speed

Package

Processl
Temp. Range

1__--l: ;"'k

L...-_ _ _

L-____________________

~

Sidebraze DIP
PlasticSOJ

10
12
15

' - - - - - - - - - - - - - - - - 11 S

I

'----------------------------------------~

Commercial

Speed in Nanoseconds

Standard Architecture

10514

1M (256K x 4-bits) SiCMOS ECl-10K
Static RAM

100514

1M (256K x 4-bits) SiCMOS ECl-100K
Static RAM

101514

1M (256K x 4-bits) SiCMOS ECl-101K
Static RAM
2786drw 11

UPDATE1 B

93

G"

Integrated Device Technology, Inc.

ADVANCE
INFORMATION
IDT10596RR
IDT100596RR
IDT101596RR

SELF-TIMED BiCMOS
ECl STATIC RAM
256K (32K x 9-BIT) SRAM

FEATURES:
• 32,768-words X 9-bit organization
Self-Timed Write, with registers on inputs and outputs
• Balanced Read/Write cycle time: 10/12/15 ns
Wide word for reduced address loading
• Differential clock input
• Fully compatible with ECl logic levels
• Separate data input and output
• JEDEC standard pinouts

DESCRIPTION:
The IDT10596RR, IDT100596RR, and IDT101596RR are
294,912-bit high-speed BiCEMOSTM ECl self-timed static
random access memories (STRAM) organized as 32Kx9, with
inputs and outputs fully compatible with ECl levels. Clocked
registers on inputs and outputs, and the self-timed write
operation, provide enhanced system performance over con-

ventional RAMs, providing easier design and improved system level cycle times.
These devices are part of a family of nine-bit-wide ECl
SRAMs. The devices have been configured to follow the
proposed ECl SRAM JEDEC pinout. Because they are
manufactured in BiCEMOSTM technology, however, power
dissipation is similar to CMOS devices of equivalent density.
Inputs are captured and outputs gated by the rising edge of
an externally supplied differential clock. The small input valid
window required means more margin for system skews.
logic-to-memory propagation delay is included in device
cycle time calculation, allowing this device to deliver better
system performance than asynchronous SRAMs and glue
logic.
Write timing is controlled internally based on the clock. Write
Enable has no special requirements. The device allows
balanced read and write cycle times, and reads and writes can
be inserted in any order.

FUNCTIONAL BLOCK DIAGRAM

294,912-BIT
MEMORY ARRAY

~

Vee

~

VEE

00
SENSE AMPS
AND READIWRITE
CONTROL

A

08
MUX

•
•

•

B

AI

2787drw 01

BiCEMOS Is a trademark of Integrated Device Technology. Inc.

COMMERCIAL TEMPERATURE RANGES
e

MAY 1991
DSC-80251-

1991 Integrated Device Technology, Inc.

UPDATE1 B

94

IDT10596RR, IDT100596RR, IDT10l596RR
HIGH SPEED BICMOS ECl SELF-TIMED STATIC RAM 256K (32K x 9-BIT)

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION
(A1S) NC
A4
AI2
Ala
AI4
CS
D7
OS
a7
Vce
as
Vce
VEE
as
Vcc
a4

r--T""""T"""-'

All
AIO
A9
WE
Ds
Da
D2
as
aa
Vcc
a2
VEE
Vec
al
Vce
ao
DI

os
D4

300-Mil-Wide
Plastic SSOP Package
48

DO

Ao
AI
A2

ClK
ClK
As
As
A7
(AIS) NC
As
NC -..._ _ _ _- As

LOGIC SYMBOL
2787drw 02

Ao
AI
A2
Aa

TOP VIEW

PIN DESCRIPTIONS
Symbol

ao
al
a2
aa
a4
as

A4

DO through D8

Data Inputs

As
As
A7
As

ao through a8

Data Outputs

A9

CS

Chip Seleel Input (Internal pull down)

WE

Write 'Enable Input

ClK,ClK

Differential Clock Imputs

Pin Name

AD through A14

Address Inputs

VEE

More Negative Supply Voltage

Vee

less Negative Supply Vollage

as

a7
as

AlO
All
AI2
Ala
AI4

2787drw04

VeeA

less Negative Supply VoRage lor Output

NC

No Connect (Not internally bonded)

32Kx9
SRAM

27871bIOl

AC OPERATING RANGES(1)
110

VEE

TRUTH TABLE(1)

Temperature

CS

WE

ClK

10K -S.2V±5%

o TO 75 DC, air flow exceeding 2 mlsec

H

X

lOOK ·4.5V±5%

o TO 85 DC, air flow exceeding 2 mlsec

l

H

l

l

i
i
i

101K -4.75V to ·5.46V o TO 75°C, air flow exceeding 2 m/sec
NOTE:
I, Referenced to Vee

CAPACITANCE (TA=+25°C

27871b102

DATAoUT(2)

Function

l

Deseleeled

RAM Data

Read

WRITE Data

Write

NOTES:
I. H=High. l=Low. X=Don't Care.
2. DATAoUT initiated by next rising CLK.

27871b104

1=1 OMHz)
SSOP

Symbol

Parameter

Typ.

Max.

Unit

CIN

Input Capacitance

TBD

-

pF

CoUT

Output Capacitance

TBD

-

pF
2787tb1 03

UPDATE1 B

95

IDT10596RR, 1DT100596RR, IDT101596RR
HIGH SPEED BICMOS ECl SELF-TIMED STATIC RAM 256K (32K x 9-Bln

COMMERCIAL TEMPERATURE RANGE

Eel-10K ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Value

Unit

+0.5 to -7.0

V

Oto +75

°C

-55 to +125

°C

VTERM

Terminal Voltage
With Respect to GND

TA

Operating Temperature

TBIAS

Temperature Under Bias

TSTG

Storage
Temperature

-65 to +150

°C

PT

Power Dissipation

2.0

W

lOUT

DC Output Current (Output
High)

-50

mA

I

Ceramic

27871b105
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this

ECl-10K DC ELECTRICAL CHARACTERISTICS
(VEE = -5 2V , RL =
Symbol
VOH

VOL

VOHC

son to -2 OV , TA = 0 to +75°C , air flow exceeding 2 m/sec)
Parameter

Output HIGH Voltage

Test Conditions
V IN = V )HA or V ILB

Output LOW Voltage

V IN = V IHA or V ILB

Output Threshold HIGH Voltage

V IN = V IHB or V ILA

TypJl)

Max. (A)

Unit

TA

-1000
-960
-900

mV

-885

-840
-810
-720

O°C
25°C
75°C

-1870
-1850
-1830

-1665
-1650
-1625

mV

-

O°C
25°C
75°C

-1020
-980
-920

-

mV

-

O°C
25°C
75°C

-

-

-1645
-1630
-1605

mV

O°C
25°C
75°C

Min. (B)

VOLe

Output Threshold LOW Voltage

V IN = V IHB or V ILA

VIH

Input HIGH VoHage

Guaranteed Input Voltage
High for All Inputs

-1145
-1105
-1045

-840
-810
-720

mV

-

O°C
25°C
75°C

-1870
-1850
-1830

-

-1490
-1475
-1450

mV

O°C
25°C
75°C

CS

-

-

220

Il A

-

Others

-

-

110

Il A

-

0.5

170

J.lA

-50

-

90

Il A

-

-280

-220

-

mA

VIL

Input LOW Voltage

Guaranteed Input Voltage
Low for All Inputs

IIH

Input HIGH Current

VIN=VIHA

IlL

Input LOW Current

VIN = VILB

CS

lEE

Supply Current

All Inputs and Outputs Open

Others
NOTE:
1. Typical parameters are specified at VEE

27871b106

=-S.2V. TA =+2S'C and maximum loading.

UPDATE1 B

96

IDT10596RR, IDT10OS96RR, IDT101596RR
HIGH SPEED BICMOS ECl SELF-TIMED STATIC RAM 256K (32K x 9-BI1)

COMMERCIAL TEMPERATURE RANGE

ECL-100K ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM

Rating
Terminal Voltage
With Respect to GND

Value

Unit

+0.5 to -7.0

V

TA

Operating Temperature

Oto +85

·C

TBIAS

Temperature Under Bias

-55 to +125

·C

TSTG

Storage
Temperature

-65 to +150

·C

Pr

Power Dissipation

2.0

W

lOUT

DC Output Current
(Output High)

-50

mA

I

Ceramic

278711>107
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposureto absolute maximum rating conditions
for extended periods may affect reliability.

ECL-100K DC ELECTRICAL CHARACTERISTICS
(VEE = -4.5V, RL=

son to -2 OV, TA = 0 to +85°C , airflow exceeding 2 rn/sec)
Min. (B)

Typ.(l)

Max.(Al

Unit

VOH

Output HIGH Voltage

V IN = VIHA or VILB

-1025

-955

-880

mV

VOL

Output LOW Voltage

VIN = VIHAOr VILB

-1810

-1715

-1620

mV

VOHC

Output Threshold HIGH Voltage

VIN=VIHBor VILA

-1035

-

mV

VOLe

Output Threshold LOW Voltage

VIN=VIHBor VILA

-

-1610

mV

VIH

Input i'IIGH Voltage

Guaranteed Input Voltage

-1165

-

-880

mV

-1810

-

-1475

mV

CS

-

-

220

jLA

Others

-

-

110

CS

0.5

-

170

Others

-50

-

90

-260

-200

-

Symbol

Parameter

Test Conditions

High for All Inputs
VIL

Input LOW Voltage

Guaranteed Input Voltage
Low for All Inputs

IIH

IlL

lEE

Input HIGH Current

Input LOW Current

Supply Current

NOTE:
1. Typical parameters are specified at VEE

VIN=VIHA

VIN=VILB

All Inputs and Outputs Open

J.LA

mA
278711>108

=-4.5V, TA =+25·C and maximum loading.

UPDATE1 B

97

1DT10596RR, IDT100596RR, IDT101596RR
HIGH SPEED 81CMOS ECl SELF-TIMED STATIC RAM 256K (32K x 9-81T)

COMMERCIAL TEMPERATURE RANGE

ECL-101K ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Value

Unit

+0.5 to -7.0

V

o to +75

°C

VTERM

Terminal Voltage
W~h Respect to GND

TA

Operating Temperature

TBIAS

Temperature Under Bias

-55 to +125

°C

TSTG

Storage
Temperature

-65 to +150

°C

PT

Power Dissipation

2.0

W

lOUT

DC Output Current (Output
High)

-50

mA

J

Ceramic

2787 tbl 09
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXI MUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this speCification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

ECL-101 K DC ELECTRICAL CHARACTERISTICS
= -S.2V, Rl = son to -2.0V, TA = 0 to +7S o C, air flOW exceeding 2 m/sec)

(VEE

Min. (8)

Typ.(l)

Max. (A)

Unit

VOH

Output HIGH Voltage

V IN = V IHA or V ILB

-1025

-955

-880

mV

VOL

Output LOW Voltage

V IN = V IHA or V ILB

-1810

-1715

-1620

mV

VOHC

Output Threshold HIGH Voltage

V IN = V IHB or V ILA

-1035

-

-

mV

VOLC

Output Threshold LOW Voltage

V IN = V IHB or VILA

-

mV

Input HIGH Voltage

Guaranteed Input Voltage
High for All Inputs

-1165

-

-1610

VIH

-880

mV

VIL

Input LOW Voltage

Guaranteed Input Voltage
Low for All Inputs

-1810

-

-1475

mV

IIH

Input HIGH Current

VIN=VIHA

flA

Symbol

IlL

lEE

Parameter

Input LOW Current

Supply Current

Test Condition

VIN=VILB

CS

-

-

220

Others

-

-

110

CS

0.5
-50

-

170

Others

-280

-220

-

All Inputs and Outputs Open

NOTE:
1. Typical parameters are specified at VEE ~ -S.2V, TA ~ +2SoC and maximum loading.

UPDATEl B

flA

90
mA
2787 tbl 10

98

IDT10596RR, IDT100596RR, IDT101596RR
HIGH SPEED BICMOS ECl SELF-TIMED STATIC RAM 256K (32K

x 9-BI1)

AC TEST LOAD CONDITION

COMMERCIAL TEMPERATURE RANGE

AC TEST INPUT PULSE

Vee (GND)

~

20%

DATAoUT

tF
tR = IF = 2.0ns typo
Note: All timing measurements are
referenced to 50% input levels.

IR

r30PFO

2787 drw06

-2.0V
°1.!1c1udes erobe and
Jig capacitance
2787 drw05

RISE/FALL TIME
Symbol

Parameter

tR

Output Rise Time

tF

Output Fall Time

Test Condition

-

Mh

Typ.

Max.

Unit

-

2

-

ns

2

-

ns
27871blll

FUNCTIONAL DESCRIPTION
The IDT10596RR, IDT1 00596RR, and IDT1 01596RR SelfTimed BiCMOS ECl static RAMs (STRAM) provide high
speed with low power dissipation typical of BiCMOS ECL.
On-chip logic additionally helps improve system performance.
As can be seen in the Functional Block Diagram on the title
page, this device contains clocked input registers to sample
and hold addresses, input data, and control status. Inputs are
sampled on the rising edge of the clock (ClK) input (falling
edge of ClK). In the case of a write cycle, the memory cell is
written by an internal timer initiated by the rising edge of ClK,
and write data conducted to the outputs. Output data is
clocked out the output register and is held through the next
cycle.

READ TIMING

In a typical read cycle, the read address is captured by the
rising edge of clock, as at 0 below. Then, after access occurs
internally, the read data for the read address clocked in at 0
is clocked through the output register to the output pins by the
next rising edge of clock (for this example, at @). There is a
short delay from rising clock to output ready, called tOR (see
Read Cycle Timing).
The output register takes some time to change state for the
next output, but this time is very short. Therefore, data hold
lime from clock lJigh (tDH) is specified as zero minimum hold
lime.

FUNCTIONAL DESCRIPTION TIMING EXAMPLE

UPDATE1 B

99

IDT10596RR, IDT100596RR, IDT101596RR
HIGH SPEED BICMOS ECl SELF-TIMED STATIC RAM 256K (32K x 9-BIT)

COMMERCIAL TEMPERATURE RANGE

DESELECT TIMING
Because the outputs are registered, they will continue to
drive the output pins until a disable state is clocked through the
device. The deselected state is achieved by de-asserting chip
select (CS high) at rising edge of clock. This case occurs at
@ below. Outputs then attain the disable state (low) after the
next rising clock edge. Status of other inputs do not effect the
disabling of the device when chip select is de-asserted with
the proper relation to clock.
WRITE TIMING
Write cycles are identical to read cycles, except that write
enable and write data need also be supplied, with the appropriate setup and hold timing. The device has on-chip timing
that handles all aspects of writing data into the addressed
RAM cell without the need for external write-pulse generation.
The timing logic uses an internal timer as the write pulse, and
thus only one edge of clock need be determined (de-skewed)
exactly.
In addition to writing to the RAM cell, the write data is fed to
the output register by a multiplexer, so that write data is
available on the output pins in the appropriate time slot (Le.
afler the next clock high edge). This function is sometimes
called "Transparent Write," and is useful for write-through
cache applications. Thus the input data sampled at CD is available on the output in the next cycle.
There are no restrictions on the order of read cycles and
write cycles.

UPDATE1 B

100

IDT10596RR, IDT100596RR, IDT101596RR
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 256K (32K

x 9·BIT)

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)

Test
Symbol

Parameter(1)

10596RR1 0

10596RR12

100596RR10
101596RR10

100596RR12
101596RR12

10596RR15
100596RR15
101596RR15

Max.

Unit

Condition

Min.

Max.

Min.

Max.

Min.

10
4
4
1

-

12
5
5

-

15

-

ns

6

-

ns

-

ns

4

ns

READ CYCLE

teye

Cycle Time

tWL

Clock Low Pulse Width

-

twH

Clock High Pulse Width

-

tses

Setup Time for Chip Select

tSA

Setup Time for Address

tHes

Hold Time for Chip Select

tHA

Hold Time for Address

-

tDH

Data Hold from Clock High

tDR

Data Ready from Clock High

-

1
2
2

¥ ...":-::--

&c::::
§~ 3
-::::.1
.:%-.

~::"t

0
0

NOTE:
1. Input and Output reference level is 50% point of waveform.

4

.-::'V~r-

.~hl: -

1

1
2
2
0
0

;-;.i:

.,

y •••

.;-:-."}

":"::;

.

-

4

6

£:~

1
1

2
2
0
0

.:

¥-.:
.~:~.

!:';:yo
».~

..........
.~)

'-:q::'

ns
ns
ns
ns
ns
27B71b112

READ CYCLE TIMING DIAGRAM
~-------------k~------------~

ClK

ADDR

DATAour

UPDATE1 B

101

IDT10596RR, IDT100596RR, I.DT101596RR
HIGH SPEED 61CMOS ECl SELF-TIMED STATIC RAM 256K (32K

x 9-61T)

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)

Test
Symbol

Parameter1 )

10596RR1 0
100596RR1 0
101596RR10

Condition

Min.

-

1

.:;

1

i~

2

,i?

10596RR12
100596RR12
101596RR12

Max.

Min.

-

1

Max.

10596RR15
100596RR15
101596RR15
Min.

Max.

Unit

ns

WRITE CYCLE
tSWE

Setup Time for Write Enable

tSD

Setup Time for Data In

tHWE

Hold TIme for Write Enable

tHD

Hold TIme for Data In

....:-:
'::.:.':
~:.

r

2,:t~:;

NOTES •.

-

-

1

1

-

1

2);:
2 ,:?

-

2jP'

-

-

2;:::;:

-

:.:~::.

::;

;~

i;I'
/';1'

ns
ns
ns
27871b112

1. Input and Output reference level is 50% point of waveform.
2. All Setup. Hold. and access timing is the same as the Read Cycle with the addition of the above requirements. Write Data appears on the output pins after
the next rising edge of ClK.

WRITE CYCLE TIMING DIAGRAM
t--------tCYC------~

elK

ADDR

DATAIN

DATAour

2787 drw 08

UPDATE1 6

102

IDT10596RR, IDT100596RR, IDT101596RR
HIGH SPEED 6iCMOS ECl SELF-TIMED STATIC RAM 256K (32K x 9-61T)

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
IDT

~-,nn_n_n__
n_

aa

nn

a

a

Device Type

Architecture

Speed

Package

Process/
Temp. Range

----1: :"ok

'--'--_ _I

10
12
15

~--------------------------~II RR

Commercial

SSOP

Speed in Nanoseconds

Registered Inputs, Registered Outputs

10596

256K (32K x 9-bits) SiCMOS
ECl-10K Self-Timed Static RAM

100596

256K (32K x 9-bits) SiC MaS
ECl-1 OOK Self-Timed Static RAM

101596

256K (32K x 9-bits) SiCMOS
ECl-1 01 K Self-Timed Static RAM
2787 drw09

UPDATE1 B

103

t;)"

ADVANCE
INFORMATION
IDT7099S

HIGH-SPEED 36K (4K x 9-BIT)
SYNCHRONOUS
DUAL-PORT RAM

Integrated Device Technology,lnc:.

FEATURES:

DESCRIPTION:

• High-speed clock-to-data output times
Military: 20/25/30ns (max.)
Commercial: 15/20/25ns (max.)
• Low-power operation
IDT7099S
Active: 900 mW (typ.)
Standby: 50 mW (typ.)
• 4K X9 bits
• Architecture based on dual-port RAM cells
Allows full simultaneous access from both ports
Independent bit/byte read and write inputs for control
functions
• IDT's BiCEMOSTM process technology
• Synchronous operation
4ns setup to clock, 1ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 15ns clock to data out
Self-timed write allows fast write cycle
20ns cycle times, 50MHz operation
• Clock enable feature
• Guaranteed data output hold times
• Available in 68-pin PGA and PLCC
• Military product compliant to MIL-STD-883, Class B

The I DT7099 is a high-speed 4K X 9 bit synchronous dualport RAM. The memory array is based on dual-port memory
cells to allow simultaneous access from both ports. Registers on control, data and address inputs provide low set-up
and hold times. The timing latitude provided by this
approach allow systems to be designed with very short
realized cycle times. With an input data register, this device
has been optimized for applications having unidirectional data
flow or bi-directional data flow in bursts. Changing data
direction from reading to writing normally requires one dead
cycle.
Fabricated using IDT's BiCEMOSTM high-performance
technology, these dual-ports typically operate on only
900mW of power at maximum high-speed clock-to-data output times as fast as 15ns. An automatic power down
feature, controlled by CE, permits the on-chip circuitry of each
port to enter a very low standby power mode.
The IDT7099 is packaged in a 68-pin PGA or 68-pin
PLCC. Military grade product is manufactured in compliance
with the latest revision of MIL-STD-883, Method 5004.

FUNCTIONAL BLOCK DIAGRAM
-I

IIOBl~~_ _

WRITE
LOGIC

IlOol·7l

It-++--H++-I

I-_...,....~ IIOaR

WRITE
LOGIC

MEMORY
ARRAY

IlOoR·7R

SENSE
SENSE
AMPS DECODER DECODER AMPS 1-++-1-1--+-+---"1

BITOER

BIT OEl
BYTE OEl - - - I - '
CLKl --+-T-H-+---+-+tt--+-_....I

'--+-- BYTE OER
L--+-~r+--~+-~----CLKR

CLKENl---+-~+---4~~+-----'

BIT RIWl

L---~~~--~~~----CLKENR

ST

ST
WT
GEN(I)

1-+-1-+--<0-1 WT

GEN(I)

BITRiWR
BYTE RiWR

BYTE RiWl
ADDR

ADDR

CER
3007 drw01A

NOTE:
1. Self-timed write generator.
BiCEMOS Is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MAY 1991
DSC·l097/·

©1991In1egrated OeviceTechnoJogy,lnc.

UPDATE1 B

104

IDT7099S HIGH-SPEED 36K (4K x 9-BIT)
SYNCHRONOUS DUAL-PORT RAM

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS
51

50

ASL
52

53

55

49
A6L

A7L

48

47
A3L

40

CLKL pLKENA

AOL
45

AlL

42

44

46

A2L .

A4L

39

41

43

CiJ C\J ..-

..J~..J
0

<><><*~-----~.-~
VALID

ICQV@_ _V_A_LI_O_
3007 drw OGA

NOTES:
1. CEl = CER = L, CLKENl = CLKENR = L

2. OE = Lfor the reading port.

UPDATEl B

109

IDT7099S HIGH-SPEED 3SK (4K x 9·BIT)
SYNCHRONOUS DUAl·PORT RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO.1, CE HIGH (1)
1----

teLK

teLK

ClK
ClKEN

-----+--------~-------_+---------------

BYTE RAN ,,~~,--~,,~~~~
or BIT RAN

ADDRESS

DATAIN --~---+--------_t_--_<

DATAoUT

------+-----{.
3007 drw07A

NOTE:
1. OE low throughout.

_

(1,2)

TIMING WAVEFORM OF READ-TO-WRITE CYCLE NO.1, CE LOW
1--_ _

teLK

ClK
ClKEN -----+--------~------~-------------

BYTE
or BIT

RfW
RfW

...----:...-."..-r----t-'<'""""'...-~.,....."""

ADDRESS

DATAIN

DATAoUT - - - - - - - t - - - - - (
3007 drw OBA

NOTES:
1. During dead cycle, if CE is low, data will be written into array.
2. OE low throughout.

UPDATEI B

110

ID17099S HIGH-SPEED 36K 14K x 9-8IT)
SYNCHRONOUS DUAL-PORT RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

introducing clock skew for very fast interleaved memory
applications.
The data inputs are gated to control on-chip noise in bussed
applications. The user must guarantee that the BYTE R/W
and BIT RIW pins are low for at least one clock cycle before
any write is attempted. A high on the CE input for one clock
cycle will power down the internal circuitry to reduce static
power consumption.
The device has independent bit write, byte write, bit enable,
and byte enable pins to allow for independent control.

FUNCTIONAL DESCRIPTION
The IDT7099 provides a true synchronous dual-port static
RAM interface. Registered inputs provide very short set-up
and hold times on address, data, and all critical control inputs.
All internal registers are clocked on the rising edge of the clock
Signal. An asynchronous output enable is provided to ease
asynchronous bus interfacing.
The internal write pulse width is independent of the high
and low periods ofthe clock. This allows the shortest possible
realized cycle times. Clock enable inputs are provided to stall
the operation of the address and data input registers without

CAPACITANCE (TA = +25°C, f = 1.0MHz)
Parameter(1)

Symbol

Condition

Max. Unit

CIN

Input Capacitance

VIN= OV

11 ;

COUT

Output Capacitance

VOUT= OV

11

pF
pF
3007tbi 07

TRUTH TABLES
TRUTH TABLE I: READ/WRITE CONTROL(1)
Inputs
Synchronous

Asynchronous

Clk

CE

Byte RIW

/'
/'
/'
/'
/'
/'
/'
/'
/'

h

h

h

h

I

h

h

h

I

h

I

I

I

/'

I

/'
/'

I

/'

Bit RIW ByteOE

Outputs

BitOE

1100-7

1I0a

Mode

X
X
X
X

Hi-Z

Hi-Z

Deselected, Power Down, Data 110 Disabled

DATAIN

Hi-Z

Deselected, Power Down, Byte Data Input Enabled

Hi-Z

DATAIN

I

X
X
X
X

DATAIN

DATAIN

I

h

X

L

I

I

h

X

H

I

h

I

L

X

I

h

I

H

X

I

I

X

X

h

h

L

L

h

h

H

L

Hi-Z

DATAoUT

I

h

h

L

H

DATAoUT

Hi-Z

Read Byte Only

I

h

h

H

H

Hi-Z

Hi-Z

Data 110 Disabled

Deselected, Power Down, Bit Data Input Enabled
Deselected, Power Down, Data Input Enabled

DATAIN DATAoUT

Write Byte, Read Bit

DATAIN

Write Byte Only

Hi-Z

DATAoUT DATAIN

Read Byte, Write Bit

Hi-Z

DATAIN

Write Bit Only

DATAIN

DATAIN

Write Byte, Write Bit

DATAoUT DATAoUT

Read Byte, Read Bit
Read Bit Only

3007tb10B

TRUTH TABLE II:
CLOCK ENABLE FUNCTION TABLE (1)
Register Outputs

Register Inputs

Inputs
Operating Mode

Clk

CLKEN

AD DR

DATAIN

ADDR

DATAIN

Load "1"

/'
/'
/'

I

h

h

H

H

I

I

I

L

L

h

X

H

X

N/C
N/C

N/C

X

X
X

Load "0"
Hold (do nothing)

N/C

NOTE:
3007tbi 09
1. H = High voltage level steady state. h = High voltage level one set-up time prior to the low-ta-high clock transition. L = Low voltage level steady state
I = Low voltage level one set-up time prior to the low-to-high clock transition, X = Don1 care, N/C = No change
'

UPDATE1 8

111

ID17099S HIGH-SPEED 36K (4K x 9-BIT)
SYNCHRONOUS DUAL-PORT RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XXXX

A

999

A

A

Device
Type

Power

Speed

Package

Process!
Temperature
Range

y:''"'
'--______________-1

J
G

15
-1 2o

L -____________________

25
30

L---------------------------1S
~------------------------------------__I7099

Commercial (O°C to +70°C)
Military f-55°C to + 125°C)
Comp iant to MIL-STD-883, Class B
Plastic Leaded Chip Carrier
Ceramic Pin Grid Array
Commercial Only }
Speed in Nanoseconds
Mil~ary

Only

Standard Power
36K (4K x 9-Bit) Synchronous Dual-Port RAM
3007 drw09

UPDATE1 B

112

~

lOT SUBSYSTEMS CUSTOM
MODULE CAPABILITIES

Integrated Device Tec:hnology, Inc:.

INTRODUCTION
lOT Subsystems is available for design and manufacturing of a
wide range of custom products. From dense memory modules to
sophisticated mu~i-processor subsystems, we are the leading supplier of custom modules to commercial and military customers. This
experience provides the basis of our professional approach to meet
your needs. Custom module solutions can provide significant benefits to you:

• Application Specific
Encompassing all of your design criteria (electrical, mechanical,
environmental), a custom solution is specially tailored to perform in
your application.

• Faster Time to Market
Acting as an extension of your design team, we can provide the
resources you need to bring your product out in time to
meet your window of opportunity.

CUSTOM PRODUCT
DEVELOPMENT OVERVIEW
Customer requirements gathered
and understood to prepare
proposal which fits electrical,
mechanical, and business needs.
Custom development proposal
written and presented to customer
for evaluation and feedback.
Changes are made as required to
ensure customer will receive
desired end product.

add~ional

• Manufacturing Ease/Guaranteed Performance
100% of lOT Subsystem products are tested over guardbanded
temperature and supply voltage to ensure datasheet conformance.
This guaranteed performance reduces time-consuming debugging
and provides you with confidence that your system will perform well
at your customer's installation.

• Density
More capability into smaller space is what it takes to stay
competitive. lOT Subsystems can help you using the packaging
technology appropriate for your needs. Double-sided surface
mounted components on FR-4 substrates offer quick-turn solutions.
TAB mounted die and other approaches on a wide variety of
substrates can offer substantial density advantages, especially for
high pincount devices such as processors and ASICs. We can help
you evaluate and compare alternatives to make the best selection for
your application.

Subsystems' Engineering begins
design. This process often
involves communication with
customer engineering group.

CUSTOM MODULE DEVELOPMENT FLOW
Figure 1 illustrates our custom module development flow, from
initial concept through manufacturing and delivery. The initial concept is the starting point for discussions with the customer and
Subsystems Engineering. Specifications, mechanical requirements,
and other needs are reviewed and discussed to select the best
components and assembly technology for the application.
Allspecifications are reviewed with you priorto substrate fabrication
to ensure adherence to your requirements.

PACKAGING FLEXIBILITY
Packaging options provide you with the flexibility to fit your
function within the available space. Military and hostile environments
typically require the use of ceramic substrates while FR-4 is most
often used in commercial and industrial temperature applications.
Newer die packaging technologies such as TAB, flip-chip and others
offer density and performance advantages not attainable by conventional through-hole or surface mount assemblies.
lOT Subsystems can provide you with the technology to fit your
needs through prototypeibeta testing, pilot production, and volume
manufacturing. Contact the factory for more details.

SPECIFICATION:
ACiDC PARAMETERS
SCHEMATIC
MECHANICAL
MARKING
OTHER (AS REO'o)

Subsystems' Engineering finshes
design, and obtains approval
within Subsystems' Marketing,
Production, Assembly, and Test
groups.

Complete custom specification
delivered to customer for review
and approval prior to ordering
motherboard fabrication.

No

Approved?
Yes

Custom module approval
received; motherboard and other
parts ordered for assembly kitting.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

(

SUBSYSTEMS' MANUFACTURING)

JUNE 1991
DSC·7089-

101991 Integrated Device Technology,lnc.

UPDATE1 B

113

t;)"

128K x 8
CMOS STATIC RAM

PRELIMINARY
IDT71 M024
IDT71 M025

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• High density 1 megabit (128K x 8) static RAM
• Dual Chip Select Version (IDT71 M024)
Single Chip Select Version (IDT71 M025)
• Fast access time:
- commercial: 55ns (max.)
- military: 60ns (max.)
• Low power consumption
- active: 100mA (max.)
- CMOS standby: 2mA (max.)
• Very low power version
- data retention: 501lA (max.) vcc = 3V
- CMOS standby: 1001lA (max.)
• 32-pin ceramic sidebrazed DIP or ceramic leadless chip
carrier (LCC)
• Single 5V (±10%) power supply
• Inputs/outputs directly TIL compatible

The IDT71 M024/71 M025 is a 1 megabit (128K x 8) static
RAM packaged in a sidebrazed ceramic dual in-line package
(DIP) and a ceramic leadless chip carrier (LCC). The
IDT71 M024/71 M025 is available with access times as fast
as 55ns. For battery backup applications, a very low power
version is available, offering a commercial temperature data
retention current of 501lA with Vee = 3V.
The IDT71 M024/71 M025 is packaged in a 400 mil and a
600 mil 32-pin ceramic DIP as well as a 400 mil by 820 mil
LCC. The 600 mil DIP conforms to the JEDEC standard,
while the 400 mil DIP offers the same solution in 30% less
space. For surface mount applications, the proposed JEDEC
standard 400 mil by 820 mil LCC is ideal.
All inputs and outputs of the IDT71 M024/71 M025 are
TIL compatible and operate from a single 5V supply. Fully
asynchronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease
of use. All IDT military semiconductor components are
manufactured in compliance to the latest revision of MILSTD-883 Class B, making them ideally suited for applications
demanding the highest level of performance and reliability.

FUNCTIONAL BLOCK DlAGRAM(1)

CSl
CS2

PIN CONFIGURATION(1,

128K x 8

RAM

110

NC
A16
A14
A12
A7
As
As
A4
A3
A2
Al
Ao
1100

2B20dlW02

NOTE:
I. Forthe IDT?1 M024 version Pin 30;CS2. For the IDT?I M025 version Pin
30;N.C.

PIN NAMES
1100·7

Data InputslOutputs

AO'lS
CS1, CS2

Addresses

WE

Write Enable

OE

Output Enable

2)

Vcc
A1S
CS2
WE
A13
As
Ag
All
OE
Al0
CSl
1107
1106
1105
1104
1103

1/01

1102
GND

Chip Selects

N.C.

No Connect

Vee

Power

GND

Ground

2820drwOl

DIP, LCC
TOP VIEW
NOTES:
I. For package dimensions, please refer to the drawings in the packaging
section.
2. For the IDT?I M024 version Pin 30;eS2. For the IDT?1 M025 version Pin
30;N.e.
2820 tbl 01

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MAY 1991
DSC·7091J.

<01991 Integrated Device Technology, Inc.

UPDATE1 B

114

10171 M024171 M025
1 MEGABIT (128K x 8) CMOS STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(1)

TRUTH TABLE
Mode

CSl CS2

Standby

H

X

Standby

X

Read
Read
Wr~e

OE WE

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

Operating
Temperature

o to +70

-55 to +125

°C

TBIAS

Temperature
Under Bias

-55 to +125

-65 to + 135

°C

TSTG

Storage
Temperature

-55 to + 125

-65 to +150

°C

lOUT

DC Output Current

50

50

mA

Output

Power

Symbol
VTERM

Terminal Voltage
with Respect
toGND

TA

X

High-Z

Standby

L

X
X

X

High-Z

Standby

L

H

L

H

DOUT

Active

L

H

L

H

High-Z

Active

L

H

X

L

DIN

Active
tblOg

CAPACITANCE(1)
Symbol

(TA

= +25°C f = 1.0MHz

Parameter

CIN

Input Capacitance

COUT

Output Capacitance

Conditions

Typ-

Unit

VIN= OV

6

pF

VOUT= OV

8

NOTE:
1. This parameter is guaranteed by design, but not tested.

pF
2820 fur 10

RECOMMENDED DC OPERATING CONDITIONS
Symbol
Vee
GND

Parameter
Supply Voltage
Supply Voltage

Min.

Typ.

Max.

Unit

4.5

5

5.5

V

0

0

0

NOTE:
2820 fur 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT1NGs may cause permanent damage to the device. This is a stress rating
only and functional operation 01 the device at these or any otherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Input High Voltage

2.2

-

6

V

VIL

Input Low Voltage

'0;5(1)

-

0.8

V

Ambient
Temperature

GND

Vee

O°Cto +70°C

OV

5V± 10%

-55°C to + 125°C

OV

5V±10%

Grade

V

VIH

Rating

Commercial
Military

2820 tbl 04

NOTE:
1. VrL = -3.0V for pulse width less than 20ns.

2820tbl03

DC ELECTRICAL CHARACTERISTICS
Vee

= 5V ± 10%, TA = DoC to +70°C and -55°C to + 125°C)
Military

Commercial
Symbol

Parameter

Test Conditions

Max.

Min.

Max.

Unit

-

2.5

-

5

).LA

2.5

-

5

).LA

Min.

IILlI

Input Leakaqe

Vee = Max., VIN = GND to Vee

IILol

Output Leakage

Vee = Max., CS1 = VIH and CS2= VIL,
VOUT = GND to Vee

VOL

Output Low Voltaqe

Vee - Min. 10L - 2mA

-

0.4

-

0.4

V

VOH

Output High Voltage

Vee = Min., 10H = -1 mA,

2.4

-

2.4

-

V

lee

Dynamic Operating Current

Vee = Max., CS 1"; VIL and CS2 ~ VIH ,
f = fMAX, Outputs Open

-

100

-

100

mA

ISB

Standby Supply Current
(TTL Levels)

CS1 ~ VIH and CS2"; VIL, Vee = Max.,
f = fMAX, Outputs Open

-

2.5

-

2.5

mA

iSB1

Full Standby Supply Current
(CMOS Levels)

CSl ~ Vee - 0.2V and CS2"; 0.2V
VIN > Vee - 0.2V or < 0.2V
Very Low Power Version(l)

-

2

-

2

mA

-

100

-

350

NOTE:
1. For data retention version, please specify L power when ordering.

).LA
2820 tbl05

UPDATE1 B

115

10T71 M024171 M025
1 MEGABIT (128K x 8) CMOS STATIC RAM

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS
Input Pulse Levels

GNDt03.0V

Input RiselFall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figures 1 and 2
2820tbl 07

+5V

+5V
4800
4800
DATAoUT-~--+

DATAOUT -""f---;
2550
2550
2820drw 10

Figure 1. Output Load
• Including scope and jig

Figure 2. Output Load
(for tOLZ, tCHZ, tOHZ, twHZ, tow and teu)

DATA RETENTION CHARACTERISTICS(1)
(TA = DOC to +7DoC and -55°C to +125°C)
Symbol

Parameter

Test Condition

-

Min.

-

V

-

V

0.8

0.8

V

VOR< 4.5V

-

0.2

0.2

V

Vee = 3.0V, CS2 S 0.2V or

-

50

300

~A

-

50

200

~

-

-

ns

Vee for Data Retention

\/ITS,

CS1 Input Voltage

VOR;:,,2.2V

2.2

Ves2

CS2 Input Voltage

VOR;:,,4.5V

Data Retention Current

Unit

-

VOR

leeDR1

Comm.1 Military
Max.

2.0

CS1, CS2;:" Vee - 0.2V,
VIN s Vce - 0.2V or VIN ;:" 0.2V
leeDR2

Data Retention Current

Vee = 2.0V, CS2 S 0.2V or
CS1, CSn Vee - 0.2V,
VIN

tPDS(~)

Power Down Set Up Time

tPOR(2)

Power Down Recovery Time

s Vee - 0.2V or VIN ;:" 0.2V
0
tRe(3)

-

NOTES:
1. This option is only offered when ordering L power version.
2 .. This parameter is guaranteed by design, but not tested.
3. tRC = Read Cycle Time.

ns
2820 tbl 09

DATA RETENTION WAVEFORM
DATA
RETENTION MODE
Vee
VDR ;:,,2V
CS1

CS2
2820 drw 03

UPOATE1 B

116

10171 M024171M025
1 MEGABIT (128K x 8) CMOS STATIC RAM

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
Vcc

= 5V + 10%

TA = O°C to +70°C and -55°C to +125°C
71 M024 or 71 M025
_65(2)
-60(2)

_55(2,3)
Symbol
Parameter
Read Cycle

Min.

Max.

Min.

Max.

ns
ns "

-

70
70
70
35
25

-

5
5

-

ns

25

-

25

ns

-

10
0

-

ns

-

5
5
10,
0

-

ns

65

-

70

-

70

ns

-

-

70 '

-

ns

55
0

-

ns

-

70
55
0
65
65
65
30
0
0

-

25

0

-

-

20

-

-

Chip Select to Power·Up Time
Chip Deselect to Power·Down Time

-

60

10
0
-

25
-

-

-

-

65
50
0
60
60
60
30
0
0

20

-

tOE
tOHZ(l)

Output Enable to Output Valid

tOLZ(l)

Output Enable to Output in Low Z

tCLZ1,2(1)

Chip Select to Output in Low Z

tCHZ1,2(1)

Chip Deselect to Output in High Z

tOH
tPU(l)

Output Hold from Address Change

!PO(l)

Output Disable to Output in High Z

-

-

Unit

-

3
5

Chip Select (CS2) Access Time

-70
I Max.

70

-

tACS2

-

Min.

-

3
5
10
0

Chip Select (CS1) Access Time

I

-

60
60
65
30
25

tACSl

Max.

65
65
70
35
25

-

60
-

I

70

65

Read Cycle Time
Address Access Time

Min.

-

55
55
60
25
20

tRC
1M

I

-

-

-

ns
ns
ns
ns
lis

Write Cycle

tAW

Address Valid to End of Write

tCWl

Chip Select (CS1) to End of Write

tCW2

Chip Select (CS2) to End of Write

tow

Data to Write Time Overlap

tDH

Data Hold Time

tWR
tWHZ(l)

Write Recovery Time

60
45
0
55
55
55
25
0
0

Write Enable to Output in High Z

-

toW(l)

Output Active from End of Write

!Wc

Write Cycle Time

twp

Write Pulse Width

tAS

Address Set·up Time

0

NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specification only.
3 Commercial temperature only.

-

-

-

-

-

-

-

ns

-

ns

-

ns

-

ns

-

ns

-

65
65
65
30
0
0

-

25

-

25

ns

0

-

0

-

ns

-

-

ns
ns

2820tbl06

UPDATEI B

117

IDT71M024171M025
1 MEGABIT (128K x 8) CMOS STATIC RAM

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
Vee = 5V + 10% TA = DoC to +70°C and -55°C to +125°C)
71 M024 or 71 M025
-85
Max.
Min.

Symbol
Parameter
Read Cycle

Min.

-100
Max.

-120
Min. Max.

Unit

tRC

Read Cycle Time

85

-

100

-

120

-

ns

1M

Address Access Time
Chip Select (CS1) Access Time

-

Chip Select (CS2) Access Time

-

-

120
120
120

tOE
tOHZ(1)

Output Enable to Oulput Valid

-

-

-

45
35

ns

Output Disable to Output in High

100
100
100
45
35

-

IACS2

85
85
85
40
30

ns

IACS1

-

tOlZ(1)

Output Enable to Output in Low

5

-

5

-

5

ns

tClZ1,2(1)

Chip Select to Output in Low

5

-

5

-

5

-

tCHZ1,2(1)

Chip Deselect to Output in High

-

30

-

35

-

35

ns

tOH
tPU(1)

Output Hold from Address Change

10

-

10

-

10

a

-

a

-

a

-

ns

Chip Select to Power-Up Time

tPO(1)

Chip Deselect to Power-Down Time

-

85

-

100

-

120

ns

Z
Z

Z
Z

-

ns
ns
ns

ns

ns

Write Cycle
twc

Write Cycle Time

-

100
65

-

120
65

-

ns

Write Pulse Width

85
60

-

twp
lAS

Address Set-up Time

a

-

a

-

a

-

ns

lAW

Address Valid to End of Write

-

ns

-

ns

tCW2

Chip Select (CS2) to End of Write

75
75
75

-

Chip Select (CS1) to End of Write

75
75
75

-

tCW1

70
70
70

ns

tow

Data to Write Time Overlap

35

40

tOH

Data Hold Time

a

ns

Write Recovery Time

0

-

ns

tWHZ(1)

Write Enable to Output in High

-

30

-

35

a
a
-

-

tWR

-

35

ns

toW(1)

Output Active from End of Write

a

-

a

-

0

-

Z

NOTE:

-

-

a
a

-

-

40

ns

ns

ns
2820 tbl 06

1. This parameter is guaranteed by design, but not tested.

UPDATEl B

118

10T71 M024171 M025
1 MEGABIT (128K x 8) CMOS STATIC RAM

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

~--------------tRC--------------~
----~

,------------

ADDRESS

CS2

DATAoUT

L-L..../1--------------------------------i(
2820 drw 04

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
~----------------- tRc----------------~

ADDRESS

i--------------tAA-------------J
~-------

DATAoUT

tOH --------i

--------------------~~~~~~

2820drw05

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

DATA OUT

NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS1 = VIL, CS2 = VIH .
3. Address valid prior to or coincident with CS1 transition low, CS2 transition high.
4. OE=VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.

UPOATE1 B

119

IDT71M024f71M025
1 MEGABIT (128K x 8) CMOS STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
IWC
ADDRESS

=:)K

),
,/

/

lAW

~~
CS2

,/~
~

--/'

tWp(7)

i--tAS

tWR-

"

,/

-tWHZ(6)..IOHZ(6)
DATAoUT

(4)

_ _ toHZ(6)_
tow (6)

~

'\.
/

tDWDATAIN

I"

~

DATA VALID

I'

)

(4)

)2820 drw 07

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS1, CS2 CONTROLLED TIMING)(1, 2, 3, 5)
twc
ADDRESS

=:)(

)K
tAW

CS2
-tAS

DATAIN

~,

/ ~

7~

~K.
tWR

tcw

---------------«E

tDW

.. hI

tDH

DATA VALID

2820 drw 08

NOTES:
1. WI: or CSl must be high, or CS2 must be low during all address transitions.
2. A write occurs during the overlap (twp) of a low CS1, high CS2, and a low WE.
3. twR is measured from the earlier of CSl or WE going high or CS2 going low to the end of the write cycle.
4. During this period, 1/0 pins are in the output state, and input signals must not be applied.
5. If the CS1 low transition, CS2 high transition occur simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. During a WE controlled write cycle, twp must be greater than tWHZ+ tow to allow the 110 drivers to turn off and data to be placed on the bus for the required
tow. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP.

UPDATE1 B

120

IDT71M024n1M025
1 MEGABIT (128K x 8) CMOS STATIC RAM

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

XXXX
A
-- -A- -999- - - - -A- Device Power
Type

Speed

Package

Process!
Temperature
Range

~~~k
L---------------l1fC

IL

Commercial (O°C to +70°C)
Military (-55°C to +125°C)
MIL-STD-883 compliant
600 Mil Sidebrazed Ceramic DIP
400 Mil Sidebrazed Ceramic DIP
400 Mil x 820 Mil LCC

55 (Commercial onlY)}
60
65
Speed in Nanoseconds
L - - - - - - - - - - - - - - - l 7o
85
100
120

~--------------------___lls
IL

171 M024

~------------------------------~171M025

Standard Power
Low Power (data retention)
128Kx8 CMOS Static RAM (Dual Chip Select)
128Kx8 CMOS Static RAM (Single Chip Select)
2820 drw 09

UPDATE1 B

121

1;)"
Integrated DevIce Technology, Inc.

1K x36
2Kx36
CMOS DUAL-PORT
STATIC RAM MODULE

PRELIMINARY
IDT7M1011
IDT7M1012

FEATURES

DESCRIPTION

High density 1K/2K x 36 CMOS Dual-Port Static RAM
modules
Fast access times
Commercial: 25, 30, 40, 50, 60ns
Military: 30, 40, 50, 60, 70ns
• Fully asynchronous readlwrite operation from either port
• Surface mounted LCC packages allow through-hole
module to fit on a 121-pin PGA footprint
Single 5V (±10%) power supply
• Multiple GND pins and decoupling capacitors for maximum noise immunity
Inputs/outputs directly TTL compatible

The IDT7M1 011/1012 are 1K/2K x 36 high speed CMOS
Dual-Port static RAM modules constructed on a co-fired
ceramic substrate using 4 IDT701 (1 K x 9) Dual-Port RAMs
or41DT7012 (2Kx9) Dual-Port RAMs. The IDT7M1 011/1012
modules are designed to be used as stand alone 36-bit dualport RAM.
This module provides two independent ports with separate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory.
The IDT7M1011/1 012 modules are packaged in a 121-pin
ceramic PGA (Pin Grid Array), resulting in package dimensions of only 1.36" x 1.36" x 0.28". Maximum access times as
fast as 25ns/30ns are available over the commercial/military
temperature range.
AIiIDT military modules are constructed with semiconductor components manufactured in compliance with the latest
revision of MIL-STD-883, Class B making them ideally suited
to applications demanding the highest level of performance
and reliability.

°

PIN CONFIGURATION(1, 2)
2
A
B

e
D

E
F
G
H

K

L

M

N

GND

3

4

S

S

L_R!W(3) R_R!W(3) R_I/O(20) R_IIO(22) R_'/O(2S)

L_'/O(IS) R_IIO(IS) R_I/O(19) R_I/O(21)
L_I/O(23)

R_I/O(23) R_'/O(24)

L_A(10)

S

9

10

11

L_'/O(2?)

L-'/O(2S)

L_I/O(30)

L_I/O(32)

L_R!W(4)

R-'/O(2S)

U/O(29)

L_I/O(31)

L_'/O(33)

vee

L_I/O(34)

GND

R_A(10)

R_A(9)

R_A(O)

GND

L_'/O(3S) R_IIO(33)

R_A(I)

R_I/O(2?) R_I/O(32)

12

13

R_AiW(4) R_I/O(3S)
R_I/O(34)

vee

L_A(O)

L_I/O(20) L_I/O(24)

L_A(I)

GND

L_IIO(21)

L_I/O(2S)

L_A(2)

R_A(2)

R_I/O(2S) R_I/O(31)

L_I/O(22)

L_I/O(2S)

L_A(3)

R_A(3)

R_'/O(29)

R-'/O(30)

GND

L_es

GND

GND

R_CS

GND

UWJ(I)

L_OE

R_R!W(I)

L_R!W(2)

R_OE

R_R!W(2)

L-'/O(O)

R-'/O(3)

L_A(4)

R_A(4)

L-'/O(IS)

R_'/O(I?)

L-'/O(I)

R-'/O(2)

L_A(S)

R_A(5)

L_'/O(IS)

R_'/O(IS)
R_I/O(IS)

L_'/O(19)

L_A(9)

?

PGA
Top View

-

-

R_I/O(I)

GND

L_A(S)

L_A(?)

L_A(S)

GND

R_A(S)

R_A(?)

R_A(S)

vee

GND

L_I/O(3)

R_I/O(O)

vee

R_'/O(4)

R_'/O(S)

R_'/O(?)

R_'/O(S)

L_'/O(II)

L_I/O(12)

L_I/O(13)

L_'/O(14)

L_'/O(I?)

R_I/O(14)

L_'/O(4)

L_I/O(S)

L_I/O(S)

L_I/O(?)

L_'/O(8)

R_I/O(S)

L_I/O(9)

L_'/O(10)

R_'/O(9)

R_'/O(10)

R_I/O(II)

R_'/O(12)

R_I/O(13)

L_I/O(2)

2

3

4

S

S

?

S

9

10

11

12

A
B

e
D
E

F
G

H

K

L
M

N

13

NOTES:
1. For module dimensions, please refer to the module drawings in the packaging section.
2. For the IDT7Ml011 (1 K x 36 version). Pins C6 and C8 (L_A(10) and R_A(10) respectively) must be connected to VCC for proper operation of the
module.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1991 Integrated Device Technology,lnc.

MAY 1991
OSC·70731·

UPDATEI B

122

IDT7M1011nDT7M1012 (1K12K x 36)
CMOS DUAL-PORT STATIC RAM MODULES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL BLOCK DIAGRAMS
7M1011
L_A(0-9)

-

-

L_IIO(O-8)
L CS
L::::OE

R_A(0-9)
R_IIO(O-B)
R CS
R::::OE

IDT7010
1Kx9

L_RlW(o)

R_RlW(O)

L_I/O(9-17)

R_IIO(9-17)
IDT7010
1Kx9

L_RlW(1)

R_RlW(1)

L_I/O(1B-26)

R_I/O(18-26)
IDT7010
1Kx9

L_RlW(2)

R_RiW(2)

L_I/O(27-35)

R_I/O(27-35)
~

IDT7010
1Kx 9

-

L_RlW(3)
2821 drw 02

7M1012
L_A(0-10)

-

-

L_IIO(~

L CS

R_I/O(O-B)
R CS
R::::OE

IDT7012
2Kx9

L:::OE

R_A(0-10)

R_RlW(O)
R_I/O(9-17)
IDT7012
2Kx9
L_RlW(1)

R_RIW(1)

L_I/O(18-26)

R_I/O(1B-26)
IDT7012
2Kx 9

L_RlW(2)

R_RlW(2)

L_IIO(27-35)

R_I/O(27-35)
'---

IDT7012
2Kx9

~

UtW(3)
2821 drw 03

UPDATE1 B

123

IDT7M1011/IDT7M1012 (lK/2K x 36)
CMOS DUAL-PORT STATIC RAM MODULES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN NAMES
Left Port

Right Port

Names

L_CS

R_CS

Chip Selects

L_RlW(1-4)

R_RlW(1-4)

ReadIWrite Enables

L_OE

R_OE

Output Enables

L_A (0-10)

R_A (0-10)

Address Inputs

L_I/O (0-35)

R_I/O (0-35)

Data Input/Outputs

Vee

Power

GND

Ground

NOTE:
2821 tbl 01
1. On the IDT7M1011 (1 Kx 36 version), Pins C6 and C8 (L_AlOand R_AlO
respectively) need to be connected to VCC for proper operation of the
module.

CAPACITANCE TABLE (TA = +25°C, f = 1.0MHz)
Symbol

Parameter

C_IN(1)

Input Capacitance (Address, CS, OE)

C IN(2)

Input Capacitance (Data, R/W)

COUT

Output Capacitance (Data)

IDT7M1011
Max.

IDT7M1012
Max.

V_IN

50

50

pF

V

15

15

pF

15

15

pF

Conditions

= OV
IN = OV

V_OUT = OV

Unit

2821 tbl 05

NOTE:
1. This parameter is guaranteed by design but not tested.

ABSOLUTE MAXIMUM RATINGS(1)
Symbol

Rating

Commercial

Military

Unit

VTERM

Terminal Voltage
w~h Respect to
GND

-0.5 to +7.0

-0.5 to +7.0

V

TA
TBIAS

Operating
Temperature
Temperature
Under Bias

TSTG

Storage
Temperature

lOUT

DC Output
Current

o to +70
-55 to +125

-'-55 to +125
-65 to +135

°C
°C

-55 to +125

-65 to +150

°C

50

50

rnA

2821 tbl02
NOTE:
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliabilty.

RECOMMENDED DC
OPERATING CONDITIONS
Min.

Typ.

Max.

Unit

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

-

6.0

V

Input Low Voltage

-0.5(1)

-

0.8

Symbol

VIL

Parameter

V
2821 tbl 03

NOTE:
1. V1L '" -3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade

Ambient
Temperature

GND

Vec

Military

-55°C to + 125°C

OV

5.0V± 10%

O°C to +70°C

OV

5.0V± 10%

Commercial

2821 tbl 04

UPDATE1 B

124

IDT7M1011/IDT7M1012 (lK/2K x 36)
CMOS DUAL-PORT STATIC RAM MODULES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = -55°C to + 125°C or O°C to +70°C)
IDT7M1012

IDT7M1011

Max.

Unit

IILlI

Input Leakage

Vee = Max.
VIN = GND to Vee

-

40

-

40

Il A

IILOI

Output Leakage

Vee = Max.
CS ~ VIH, VOUT

-

40

-

40

IlA

VOL

Output Low Voltage

Vee

-

0.4

-

0.4

V

VOH

Output High Voltage

Vee

2.4

-

2.4

-

V

Parameter

Symbol

Test Conditions

= Min.
= Min.

Max.

Min.

= GND to Vee
IOl = 4mA
IOH = -4mA

Min.

2921 tbl 06

. DC ELECTRICAL CHARACTERISTICS
(Vee

=5V ± 10%, TA =-55°C to + 125°C or O°C to +70°C)
IDT7M1012

IDT7M1011
Test Conditions

Min. Max.ll ) Max.I') Min. Max.ll ) Max.I') Unit

Symbol

Parameter

Icc

Dynamic Operating
Current (Both Ports Active)

Vee = Max., CS ~ VIl,
Outputs Open, f = fMAX

-

1040

1240

-

1040

1240

mA

ISB

Standby Supply
Current (Both Ports Inactive)

Vee = Max., CS_L and CS_R ~ VIH
Outputs Open, f = fMAX

-

260

320

-

260

320

mA

ISB1

Standby Supply
Current (One Port Inactive)

Vee = Max., CS_L a CS ~ VIH
Outputs Open, f = fMAX

-

700

800

-

700

800

mA

ISB2

Full Standby Supply
Current (Both Ports Inactive)

CS_L and CS_R ~ Vee -O.2V
VIN > Vee 0.2V or < 0.2V

-

60

120

-

60

120

mA

NOTES:
1. For commercial grade (O°C to +70°C) versions only.
2. For military grade (-55°C to + 125°C) versions only.'

2821 tbl 07

AC TEST CONDITIONS
Input Pulse Levels

GND t03.0V

Input Rise/Fall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels
Output Load

1.5V
See Figures 1 & 2
2821 tbl 08

+5V

4800

DATA OUT---I)-----"

DATA oUT---9"---1
2550

2550

2821 drw 04

~

5pF'

2.21drwOS

'Including scope and jig.
Figure 1. Output Load

Figure 2. Output Load (For tCHZ, tCLZ, tOHZ,
tOLZ, tWHZ, tOW)

UPDATE1 B

125

IDT7M1011I1DT7M1012 (1K/2K x 36)
CMOS DUAL-PORT STATIC RAM MODULES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
Vee = 5V ± 10%, TA = -55·C to + 125·C or O·C to +70·C)
7Ml0llSxx or7Ml012Sxx
-25(9)
Symbol .Parameter

-40

-30
Max.

Min.

Max.

Min.

25

-

30

-

25

-

30

25

-

30

~O

-50

-70

I Min. . Max.

Min.

Max.

Min.

40

-

50

-

40

-

50

40

-

50

-

25

-

30

-

35

0

-

0

Max.

Min.

Max.

Unit

Read Cycle

IRe

Read Cycle Time

1M

Address Access Time

lACS 121 Chip Select Access Time

-

toE'

Output Enable Access Time

-

12

-

15

-

toH

Output Hold from Address Change

0

-

0

-

0

tcul "

Chip Select to Output in Low Z

0

-

0

-

tcHZl"

Chip Deselect to Output in High Z

-

10

-

12

toLZ II, Output Enable to Output in Low Z

0

-

0

-

toHzII, Output Disable to Output in High Z

-

10

-

12

IPUII,

Chip Select to Power Up Time

0

-

0

IP[JI"

Chip Deselect to Power Down Time

-

50

-

25
. 20

-

60

-

70

-

ns

60

-

70

ns

70

ns

40

ns

0

-

ns

-

0

-

ns

60

-

0

-

0

-

-

15

-

20

-

30

-

35

ns

0

-

.0

-

0

-

0

-

ns

-

15

-

20

-

30

.-

35

ris

-

0

-

0

-

0

-

0

-

ns

50

-

50 .

50

-

50

50

ns

-

0

-

-

Write Cycle'
30

-

40

.-

50

-

60

25

-

30

-

35

-

40

30

-

35

25

-

0

-

0

15

-

20

-

0

-

0

-

12

-

12

-

!we

Write Cycle Time

tcwI 2I

Chip Select to End of Write

lAW

Address Valid to End of Write

20

-

25

lAS

Address Set-Up Time

0

-

0

twP

Write Pulse Width

20

-

twR

Write Recovery Time

0

-

tow

Data Valid to End of Write

12

-

tDH

Data Hold Time

toHzII,

Output Disable to Output in High Z

-

10

twHZ'"

Write Enable to Output in High Z

-

10

tow I,

Output Active from End of Write

0

0

-

0

NOTES:
1. This parameter is guaranteed by design but not tested.
2. To access RAM array, CS!> V'L
3. Master mode is not available on this module.
4. The module is always in the Slave Mode.
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
6. To ensure that the earlier of the two ports wins.
7. To ensure that the write cycle is inhibited during contention.
S. To ensure that a write cycle is completed after contention.
9. Preliminary specification only.

UPDATE1 B

0

-

20

-

-

0

....:.

15

-

20

-

15

-

20

-

0

-

0

-

0

0
30

-

0
35

40
0
40

70

-

ns

-

50

-

ns

-

ns

0

-

50

-

ns

ns

50

ns

20

-

0

-

0

-

30

-

35

ns

30

-

35

ns

-

0

-.

0

0
30

ns

ns

ns
2821 1bI09

126

IDT7M1011nDT7M1012 (lK/2K x 36)
CMOS DUAL-PORT STATIC RAM MODULES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO.1 (EITHER SIDE) (1,2,4)

ADDRESS

j4---t-

tOH

DATA OUT
2821 drw 06

TIMING WAVEFORM OF READ CYCLE NO.2 (EITHER SIDE) (1,3,5)

DATAOUT

CURRENT

lsa _ _ _ _ _.1

%
2821 drw 07

NOTES:
1. RIW is high for Read Cycles
2. Device is continuously enabled, ~ =L. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low
4. OE= L
5. To access RAM, CS = L.
6. This parameter is guaranteed by design but not tested.

UPDATE1 B

127

IDT7M1011/1DT7M1012 (1K/2K x 36)
CMOS DUAL·PORTSTATIC RAM MODULES

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1 (RIW CONTROLLED TIMING) (1, 3, 5, 8)
~--------------

___ twc __________________~.

ADDRESS

~-------------tAW --------------~~

~----------tWP(2) -----------4~

R/W

DATA OUT

DATAIN __________________________________(

2821 drw 08

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1, 3, 5, 8)
~--------------

___ twc ________________~.~

tAW

~-----'----

twp (2)

_____- ' -__~

R/W

DATA IN __________________________________

~

2821 drw 09

NOTES:
1. RiW must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low RlWfor memory array writing cycle.
3. twR is measured from the earlier of CS or RiW going high to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the RiW low transition, the outputs remain in the high impedance slate.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If
is low during a RiW controlled write cycle, the write pulse width must be the larger of twp or (IWZ + tow) to allow the I/O drivers to turn
off and data to be placed on the bus for the required lOW. If OEis high during an RiW controlled write cycle, this requirement does not apply.
and the write pulse can be as short as the specified twP.
9. This parameter is guaranteed by design but not tested.

rn:

UPDATE1 B

128

IDT7M1011nDT7M1012 (1K12K x 36)
CMOS DUAL-PORT STATIC RAM MODULES

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT

xxxx

A

999

A

A

Device
Type

Power

Speed

Package

Process!
Temperature
Range
Commercial (O°C to +70°C)
Military (-65°C to + 125°C) Semiconductor
Components compliant to MIL-STD883, Class B
Ceramic PGA (Pin Grid Array)
25
30

'-------------1

40
50
60
70

~-----------il S
I
17Ml0ll
~------------------~17Ml012

UPDATE1 B

speed. in Nanoseconds
}
(Military Only)
Standard Power
1K x 36 CMOS Dual-Port static RAM Module
2K x 36 CMOS Dual-Port static RAM Module

129

~.

512K x 8
CMOS STATIC RAM MODULE

PRELIMINARY
IDT7M4048

Integrated DevIce Technology, Inc.

FEATURES:

DESCRIPTION:

• High density 4 megabit CMOS static RAM module
• Equivalent to the JEDEC standard for future monolithic
S12K x 8 static RAMs
• Fast access time: 17ns (max.)
• Low power consumption (L version)
- Active: 110mA (max.)
- CMOS Standby: l.4mA (max.)
- Data Retention: 800~ (max.) Vcc = 2V
• Surface mounted LCCs (Ieadless chip carriers) on a 32pin, 600 mil ceramic DIP substrate
• Single SV (±10%) power supply
• Inputs/outputs directly TTL compatible

The IDT7M4048 is a 4 megabit (S12K x 8) CMOS static
RAM module constructed on a co-fired ceramic substrate
using four 1 Megabit static RAMs and a decoder. The
IDT7M4048 is available with access times as fast as 17ns.
For low power applications, the IDT7M4048 version offers a
data retention current of 800~ and a standby current of
1.4mA.
The IDT7M4048 is packaged in a 32-pin ceramic DIP.
This results in a package 1.7 inches long and 0.6 inches
wide, packing 4 megabits into the JEDEC DIP footprint.
All inputs and outputs of the IDT7M4048 are TTL compatible and operate from a single SV supply. Fully asynchronous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
All IDT military module semiconductor components are
manufactured in compliance with the latest revision of MILSTD-883, Class B, making them ideally suited to applications demanding .the highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

ADDRESS
CS

512K x 8

RAM

WE
OE

1/0

2B22drw02

CEMOS Is a trademark of Integrated Device Technology Inc.

MAY 1991

MILITARY TEMPERATURE RANGE

DSC-7074/-

e1991 Integrated DeviceTechnology,lnc.

UPDATE1 B

130

IDT7M4048
512K,x 8 CMOS STATIC RAM MODULE

MILITARY TEMPERATURE RANGE

PIN NAMES

PIN CONFIGURATION(l)
'~18
A16
A14
A12

Vee
A15
A17
WE
A13
A8

A7
A6

A9
A11

As
A4

A3

1100·7

Data Inputs/Outputs

AO·18

Addresses

CS

Chip Select

WE

Write Enable

OE

Output Enable

Vcc

Power

GND

Ground
29221blOl

OE
Al0
CS

A2

Al
Ao

1107

1100

IIOs
l/Os

1/01

1102

1104
1103

GND

2822 drw 01

DIP
TOP VIEW
NOTE:
1, For module dimensions, please refer to the module drawings in the
packaging section,

ABSOLUTE MAXIMUM RATINGS(1)

TRUTH TABLE
Mode
~
OE

WE

Output

Power

Symbol

Military

Unit

VTERM

Terminal Voltage
with Respect
toGND

-0.5 to +7.0

V

TA

Operating
Temperature

-55 to +125

°C

TBIAS

Temperature
Under Bias

-65 to +135

,0C

TSTG

Storage
Temperature

-65 to +160

°C

lOUT

DC Output Current

50

mA

Standby

H

X

X

High-Z

Standby

Read

L

L

H

DOUT

Active

Read

L

H

H

High-Z

Active

Write

L

X

L

DIN

Active
2822tb1 09

CAPACITANCE(1)
Symbol

(TA --

+25°C , f - 1 OMHz)

Parameter

Conditions

Typ.

Unit

CIN

Input Capacitance

VIN = OV

50

pF

CIN(C)

Input Capacitance (CS)

VIN= OV

10

pF

GoUT

Output Capacitance

VOUT= OV

40

NOTE:
1, This parameter is guaranteed by design, but not tested.

pF
2922tbll0

RECOMMENDED DC OPERATING CONDITIONS
Symbol

Parameter

Min.

Typ.

Max.

Unit

Vee

Supply Voltage

4:5

5

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

VIL

Input Low Voltage

-0.5(1)

NOTE:
1. VIL = -2.0V for pulse widlh less than IOns.

-

6

V

0.8

V

Rating

NOTE:
29221bl02
1, Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to Ihe device. This is a stress rating
only and functional operation of the device at Ihese or any otherconditions
above those indicated in Ihe operational sections of this specification is
not implied, Exposure to absolute maximum rating conditions for extended periods may affect reliability,

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military

Ambient
Temperature

GND

Vee

-55°C to + 125·C

OV

5V± 10%
2B221b104

2922tb103

UPDATE1 B

131

IDT7M4048
512K x 8 CMOS STATIC RAM MODULE

MILITARY TEMPERATURE RANGE

DC· ELECTRICAL CHARACTERISTICS
(VCC

= SV± 10%, TA = -SSOCto +12S°C)
7M4048SxxCB 7M4048LxxCB

Symbol

Parameter

Test Conditions

17ns-55ns

60ns-120ns

Min.

Max.

Min.

Max.

Unit

Ilul

Input Leakage

Vee = Max., VIN = GND to Vee

-

20

-

20

IlA

IILOI

Output Leakage

Vee = Max., CS = VIH,
VOUT = GND to Vee

-

20

-

20

IlA

VOL

Output Low Voltage

Vee = Min., IOL = 2mA(1),
IOL - 8mA(2)

-

0.4

-

0.4

V

VOH

Output High Voltage

Vee = Min., IOH = -lmA(1),
IOH = -4mA(2)

2.4

-

2.4

-

V

lee

Dynamic Operating Current

Vee = Max., CS ~ VIL; I = IMAX,
Outputs Open

-

240

-

110

mA

ISB

Standby Supply Current
(TIL Levels)

CS ~ VIH, Vee = Max., I = lMAX,
Outputs Open

-

120

-

12

mA

ISB1

Full Standby Supply Current
(CMOS Levels)

CS ~ Vee - 0.2V, VIN ~ Vee - 0.2V
or~ 0.2V

-

60

-

4

mA

Very Low Power Version(3)

-

60

-

1.4

NOTES:
1. For 60ns·120ns versions only.
2. For 17ns-55ns versions only.
3. L version only.

mA
2822tbi 05

DATA RETENTION CHARACTERISTICS(5)
(TA = -SSOC to +12S°C)
Symbol

Parameter

Test Condition

-

VOR

Vee lor Data Retention

ieeoR

Data Retention Current

CS ~ Vee - 0.2V

teOR(3)

ChiD Deselect to Data Retention Time

VIN ~ Vee - 0.2V or

1R(3)

Operation Recoverv Time

VIN> 0.2V

Min.

Max.
Vee@2.0V

Unit

2.0

-

-

2(4)

mA

-

ns

-

ns

0
tRe(2)

V

NOTES:
1. Vee = 2V, TA = +25°C.
2. tRC = Read Cycle Time.
3.. This parameter is guaranteed by design, but not tested.
4. For 60ns-120ns versions. ICCDR=800f!A.
5. L version only.

28221bl09

DATA RETENTION WAVEFORM
DATA
RETENTION MODE
VOR~

2V

VOR
2B22 drw03

UPDATE1 B

132

IDT7M4048
512K x 8 CMOS STATIC RAM MODULE

MILITARY TEMPERATURE RANGE

AC TEST CONDITIONS
Input Pulse Levels

GNDto 3.0V

Input RiselFall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figures 1 and 2:
2822tbi 07

+5V

+5V

480n

480n
DATAoUT-...,...--+

DATAoUT -~--;

255n

2SSn
2822drw10

Figure 2. Output Load
(for tOLZ, ICHZ, 10HZ, IWHz, lOW and ICU)

Figure 1. OUlpUI Load

• Including scope and jig

AC ELECTRICAL CHARACTERISTICS

.

(Vee = 5V +
- 10% TA = O°C to +70°C)
. 7M4041iSxxCB, 7M4048i..xxCB
_17l~1

Symbol
Read Cycle

Parameter

Min.

_20l~1

I

I Max. I

Min.

I

Max.

Min.

-25
I Max.

I

I

-30
Min.
Max.

I

-35

I Min. I Max.

Unit

tRC

Read Cycle Time

17

-

20

-

25

-

30

-

35

-

ns

1M

Address Access Time

17

20

ns

8

-

10

-

12

-

15

-

35

25

-

30

20

-

25

17

-

8

-

12

-

12

0

-

0

0

5

-

5

-

lAcs

Chip Seleel Access Time

-

tOE
tOHZ(l)

Output Enable to Output Valid

-

Output Disable to Output in High Z

-

7

tou(')

Output Enable to Output in Low Z

0

tcul')

Chip Seleel to Output in Low Z

5

-

5

tCHZ(')

Chip Deseleel to Output in High Z

-

12

-

13

-

14

-

tOH
tPU(l)

Output Hold from Address Change

1

-

3

-

3

-

3

Chip Seleel to Power-Up Time

0

-

0

-

0

-

tpo(')

Chip Deselect to Power-Down Time

-

17

-

20

-

20

-

15

-

30

35

ns

15

ns

-

15

ns

0

-

ns

5

-

ns

16

-

20

ns

3
0

-

ns

0

-

25

-

30

-

35

ns

25

-

30

-

35

-

ns

17

-

20

-

25

-

ns

-

0

-

0

-

ns

25

-

30

-

ns

25

-

30

-

ns

17

20

ns
ns

ns

Write Cycle
twc

Write Cycle Time

17

twp
IAS(2)

Write Pulse Width

14

-

Address Set-up Time

lAW

Address Valid to End of Write

tcw

3

-

3

-

3

17(4)

-

18

20

Chip Select to End of Write

17

18

tow
tOH(2)

Data to Write Time Overlap

10

12

-

15

Data Hold Time

0

0

-

0

tWR(2)

Write Recovery Time

0

-

-

0

-

0

-

0

-

0

-

tWHZ(l)

Write Enable to Output in High Z

-

10

-

13

-

15

-

15

-

15

tow(')

Output Active from End of Write

2

-

2

-

2

-

5

-

5

-

NOTES:

1.
2.
3.
4.

20

0

0

ns
ns
ns
2B22tbl 06

This parameter is guaranteed by design. but not tested.
IAS=Ons for CS controlled write cycles. IDH. twR= 3ns for WE controlled write cycles.
Preliminary specifications only.
IAW=14ns for CS controlled write cycles.
UPDATE1 B

133

IDT7M4048
512K x 8 CMOS STATIC RAM MODULE

MILITARY TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
(VCC

= 5V ± 10%, TA = -55°C to +125°C )
7M4048SxxCB, 7M4048LxxCB

Parameter

Min.

I Max.

Min.

I

-60\~/

I

-55

-45

Symbol

·65\~/

I

I

Max.

Min.

Max.

Min.

Max.

-70

Min.

Max. Unit

Read Cycle
tRC

Read Cycle Time

45

-

55

-

65

-

65

-

70

-

ns

1M

Address Access Time

45

-

55

-

60

-

65

-

70

ns

lACS

Chip Select Access Time

-

45

-

60

-

65

-

70

ns

Output Enable to Output Valid

-

25

30

-

30

-

35

-

45

ns

Z
Output Enable to Output in Low Z
Chip Select to Output in Low Z
Chip Deselect to Output in High Z

-

20

-

55

tOE
tOHZ(I)

20

-

25

-

25

-

30

ns

5

-

5

3

-

5

5

5

-

5

5

-

ns

-

-

0

5

-

-

20

-

20

-

25

-

25

-

40

ns

tOH
tPU(I)

Output Hold from Address Change

5

-

5

10

-

-

10

ns

0

-

0

-

10

Chip Select to Power·Up Time

-

0

-

0

-

ns

tPO(I)

Chip Deselect to Power-Down Time

-

45

-

55

-

65

-

65

-

70

ns

65

-

70

-

ns

55

ns

65

-

tOlZ(I)
tCLZ(1)
tCHZ(I)

Output Disable to Output in High

0

ns

Write Cycle
twc

Write Cycle nme

45

-

55

-

65

twp

Write Pulse Width

35

45

-

50

lAs

Address Set-up Time

-

5

-

0

lAW

Address Valid to End of Write

40

50

Chip Select to End of Write

40

-

60

tcw

-

-

60

-

65

tDW

Data to Write Time Overlap

-

-

30

-

5

50

tOH

Data Hold Time

20
0(2)

-

20
0(2)

-

0

tWR

Write Recovery Time

0(2)

-

0(2)

-

0

tWHZ(I)

Write Enable to Output in High

-

15

-

20

toW(I)

Output Active from End of Write

5

-

Z

5

-

NOTES:

0

55
0
65

-

0

ns

ns

65

-

ns

30

-

35

-

ns,

-

0

-

0

-

ns

0

-

0

-

ns

25

-

25

-

30

ns

-

0

-

-

0

ns
28221bi 06

1, This parameter is guaranteed by design. but not tested.
2. IAS=Ons for CS controlled write cycles. tOH. twR= 5ns for WE controlled write cyeles.
3. Preliminary specifications only.

UPDATE1 B

134

IDT7M4048
512K x 8 CMOS STATIC RAM MODULE

MILITARY TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V +
- 10% TA = -55°C to +125°C)

.

7M4048SxxCB, 7M4048LxxCB
-85
Symbol
Read Cycle

Parameter

Min.

I

Max.

I

Min.

-100
I Max.

I

-120
Min. I Max.

Unit

tRC

Read Cycle Time

85

-

100

-

120

-

ns

fAA

Address Access Time

-

85

-

100

-

120

ns

tACS

Chip Select Access Time

-

85

-

100

-

120

ns

tOE

Output Enable to Output Valid

-

48

50

ns

Output Disable to Output in High Z

-

33

-

60

tOHZ(1)

-

40

ns

tOLZ(1)

Output Enable to Output in Low Z

0

ns

tCLZ(1)

Chip Select to Output in Low Z

5

tCHZ(1)

Chip Deselect to Output in High Z

ns

tOH

-

-

Output Hold from Address Change

tPU(1)

Chip Select to Power-Up Time

tPD(1)

Chip Deselect to Power-Down Time

35

5

-

5

-

43

-

45

-

50

10

-

10

-

10

-

ns

0

-

0

-

0

-

ns

-

85

-

100

-

120

ns

0

0

ns

WrfteCycfe
twc

Write Cycle Time

85

-

100

-

120

-

ns

twP

Write Pulse Width

65

-

75

-

90

-

ns

tAS

Address Set-up Time

2

5

-

ns

Address Valid to End of Write

82

100

-

ns

tcw

Chip Select to End of Write

80

100

tow

Data to Write Time Overlap

38

-

ns

0

-

5

tAW

-

0

-

33

-

35

-

0

-

tDH

Data Hold Time

0

tWR
twHZ(1)

Write Recovery Time

0

toW(1)

Output Active from End of Write

Write Enable to Output in High Z

0

-

90
85
40

45
0
0

0

ns

-

ns

40

ns

-

ns

ns

NOTE:
1. This parameter is guaranteed by design, but not tested.

UPDATE1 B

135

IDT7M4048
512K x 8 CMOS STATIC RAM MODULE

MIUTARY TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

~--------------tRC--------------~
ADDRESS

DATAouT

_ _of

--------------------------~
2822 drw 04

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

~----------------IRC----------------~
ADDRESS
~-----------

lAA

------------~

~---IOH---~

DATA OUT

' -____________~~~

~~dM05

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

DATAo~i,.II4-:-:=--=:_-=:~-I-C-L:Z-(-5)-=--tA=C=S===~~-g----·'------'t'oo"'12822 drw06

NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.

UPDATE1B

136

IDT7M4048
512K x 8 CMOS STATIC RAM MODULE

MILITARY TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING){1, 2, 3, 7)
Iwe

ADDRESS

)K

==>K

/
tAW

~~

)'~
Iwpl7)

i-- IAS

IWR-40

~K
I----- I WHZ 16)___

/~
tOHZ I6)
tow (6 )

IOHZ I6 )

DATA OUT

14)

"

/

IDH

tDW~~
1/

DATA IN

~

DATA VALID

l/1'\

14)

)-

)

2822 drw 07

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING){1, 2, 3, 5)
Iwe

ADDRESS

==> K
k-tAS

)K
tAW

1

/v
lew

tWR

WE
DATAIN __________________________

~~

tDW

~I.

tDH

DATA VALID

2822 drw 08

NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twA is measured from the earlier of CS or WE going high to the end of write cycle.
4. Durin[.!l1is period, 1/0 pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. During a WE controlled write cycle, write pulse «twp) > tWHZ + tow) to allow the 1/0 drivers to turn off and data to be placed on the bus for the required
tDW. If OE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP.

UPDATE1 B

137

IDT7M4048
512K x 8 CMOS STATIC RAM MODULE

MIUTARY TEMPERATURE RANGE

ORDERING INFORMATION
IDT

A
-XXXX
- - -A- -999- - - - -A- Device
Type

Power Speed Package

Process/
Temperature
Range

----ll

,----I

B

'-----------jC
17
20
25
30
35
45
' - - - - - - - - - - - - - - - 1 55
60
65
70
85
100
120
'-----------------lL
S
'--------------------l7M4048

Military (-55°C to +125°C)
Semiconductor component compliant
to MIL-STD-883, Class B
Sidebrazed DIP (Dual In-line Package)

Speed in Nanoseconds

Low Power
Standard Power
512K x 8 CMOS Static RAM Module
2822 drw 09

UPDATEl B

138

t;;"

PRELIMINARY
IDT7M4048
IDT7MB4048

512K x8
CMOS STATIC RAM
MODULE

Integrated Device Technology. Inc.

FEATURES:

DESCRIPTION:

• High density 4 megabit (512K x 8) static RAM module
• Equivalent to the JEDEC standard for future monolithic
512K x 8 static RAMs
• Fast access time: 17ns (max.)
• Low power consumption (L version)
- Active: 110mA (max.)
- CMOS Standby: 400jJA (max.)
- Data Retention: 200jJA (max.) Vee =2V
• Surface mounted plastic packages on a 32-pin, 600 mil
ceramic or FR-4 DIP substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible

The IDT7M4048/7MB4048 is a 4 megabit (512K x 8)
static RAM module constructed on a co-fired ceramic or
muHilayer epoxy laminate (FR-4) substrate using four 1
megabit static RAMs and a decoder. The IDT7MB4048 is
available with access times as fast as 17ns. For low power
applications, the IDT7M4048 version offers a data retention
current of 200jJA and a standby current of 400jJA.
The IDT7M4048 is packaged in a 32-pin ceramic DIP.
This resuHs in a package 1.7 inches long and 0.6 inches
wide, packing 4 megabits into the JEDEC DIP footprint. The
IDT7MB4048 likewise is packaged in a 32-pin FR-4 DIP
resulting in the same JEDEC footprint in a package 1.6
inches long and 0.6 inches wide.
All inputs and outputs of the IDT7M4048 and 7MB4048
are TTL compatible and operate from a single 5V supply.
Fully asynchronous circuitry requires no clocks or refresh for
operation and provides equal access and cycle times for
ease of use.

FUNCTIONAL BLOCK DIAGRAM

ADDRESS
CS

512Kx8

RAM

WE
OE

8

110

2675 drw02

CEMOS Is a traden'1ark of Integrated Device Technology Inc.

MAY 1991

COMMERCIAL TEMPERATURE RANGE
Cl19911nlegraled DevIce Technology. Inc.

DSC-4047/1

UPDATEl B

139

IDT7M4048, IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION(1)

PIN NAMES
v~

A18
A16
A14
A12
A7
As
As
A4
A3
A2
AI
Ao

AIS
A17
WE
A13
A8
A9
All
OE
Al0
CS

1100-7

Data Inputs/Outputs

Ao-IS

Addresses

CS

Chip Select

WE

Write Enable

OE

Output Enable

Vcc

Power

GND

Ground
2675tbi 01

1/07
1106
1/05

1/00
1/01
1/02

1/04
I/O:!

GND

2675drw 01

DIP
TOP VIEW
NOTE:
1. For module dimensions, please refer to the module drawings in the
packaging section.

ABSOLUTE MAXIMUM RATINGS(1)

TRUTH TABLE
Mode
CS OE

WE

Output

Power

Symbol
VTERM

Terminal Voltage
wnh Respect
toGND

TA

Standby

H

X

X

High-Z

Standby

Read

L

L

H

DOUT

Active

Read

L

H

H

High-Z

Active

Wrne

L

X

L

DIN

Active
2675tbi 09

CAPACITANCE(1)
Symbol

(TA

= +25°C , f -1
-

Parameter

OM Hz)

Conditions

Typ.

Unit

CIN

Input Capacitance

VIN= OV

35

pF

CIN(C)

Input Capacitance (CS)

VIN = OV

8

pF

COUT

Output Capacitance

VOUT= OV

35

pF
2675 tbl to

NOTE:
1. This parameter is guaranteed by design, but not tested.

RECOMMENDED DC OPERATING CONDITIONS
Symbol

Parameter

Min.

Typ.

Max.

Unit

Vee

Supply Vo~age

4.5

5

5.5

V

GND

Supply Vo~age

0

0

0

V

VIH

Input High Voltage

2.2

-

6

V

VIL

Input Low Voltage

-0.5(1)

-

0.8

V

NOTE:
1. VIL = -2.0V for pulse width less than IOns.

Rating

Commercial

Unit

-0.5 to +7.0

V

Operating
Temperature

oto +70

°C

TBIAS

Temperature
Under Bias

-10to+85

°C

TSTG

Storage
Temperature

-55 to +125

°C

lOUT

DC Output Current

50

mA

NOTE:
2675tb102
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RA TINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device atthese or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial

Ambient
Temperature

GND

O°Cto +70°C

OV

Vee
5V± 10%
2675 tbI 04

2675tb1 03

UPDATE1 B

140

IDT7M4D48, IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS
(Vcc

= 5V ± 1D%, TA =DOC to +7D°C)

Symbol

Parameter

Test Conditions

7M4048LxxN

7MB4048SxxP

Min.

Max.

Min.

Max.

Unit

-

4

-

8

J.lA

4

-

8

J.lA

IILlI

Input Leakage

Vee = Max., VIN = GND to Vee

IILol

Output Leakage

Vee = Max., CS = VIH,
VOUT = GND to Vee

VOL

Output Low Vo~age

Vee = Min'i!IOL = 2mA(1),
IOL= 8mA( )

-

0.4

-

0.4

V

VOH

Output High Voltage

Vee = Min., IOH = -1 mA(l),
IOH = -4mA(2)

2.4

-

2.4

-

V

lee

Dynamic Operating Current

Vee = Max., CS ~ VIL; f = fMAX,
Outputs Open

-

110

-

480

mA

ISB

Standby Supply Current
(TTL Levels)

CS:?: VIH, Vee = Max., f = fMAX,
Outputs Open

-

12

-

250

mA

ISBl

Full Standby Supply 'Current
(CMOS Levels)

CS:?: Vee - 0.2V, VIN :?: Vee - 0.2V
or ~ 0.2V

-

0.4

-

50

mA

NOTES.
1. For 7M4048L.xxN version only.
2. For 7MB404BSxxP version only.

2675 tbl 05

DATA RETENTION CHARACTERISTICS(l, 4)
(TA =

DOC to +7DOC)

Symbol

Parameter

Test Condition

-

Min.

Max.
Vee@2.0V

-

Unit

VOR

Vee for Data Retention

leeOR
teoR(3)

Data Retention Current

CS:?: Vee - 0.2V

-

Chip Deselect to Data Retention Time

yiN ~ Vee - 0.2V or

0

-

ns

tR(~)

Operation Recovery Time

VIN:?: 0.2V

IRd2 )

-

ns

2.0

V

200

J.lA

NOTES:
1. Vcc = 2V, TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by design, butnot tested.

2675tbl 09

4. For 7M404BL.xxN version only,

DATA RETENTION WAVEFORM
DATA
RETENTION MODE
4.SV

4.5V
VOR:?: 2V

2675 drw 03

UPDATE1B

141

IDT1M4048, IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
Input Pulse Levels

GNDto 3.0V

Input Rise/Fall Times

5ns

Input nming Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figures 1 and 2
2675 tbl 07

+5V

+5V

480n

480n

DATAOlJT-....---+
255n

DATAouT-....---+
30pF'

255n
2675drw 10

Figure 1. Output Load

Figure 2. Output Load
(for tOLZ, tCHZ, tOHZ, tWHZ, tow and tCLl)

AC ELECTRICAL CHARACTERISTICS
= 5V ± 10%, TA = DoC to

NOTES:
1. This parameter is guaranteed by design. but not tested.
2. tAS=Ons for CS controlled write cycles. tDH. twR= 3ns for WE controlled write cycles.
3. Preliminary specifications only.
4. tAW=14ns for CS controlled write cycles.

UPDATE1 B

26751bl06

142

IDT7M4048,IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = O°C to +70°C)
7M4048LxxN

7MB4048SxxP

I
I Max. I

-45
Symbol
Read Cycle

Parameter

Min.

-60(3)

-55
Min.

I

Max.

Min.

I

Max.

I
I

_65(3)
Min.

I

Max.

I
I

-70
Min. I Max. Unit

tRC

Read Cycle Time

45

-

55

-

65

-

65

-

70

-

ns

1M

Address Access Time

45

-

55

-

65

-

70

ns

Chip Select Access Time

45

-

55

60

-

65

ns

Output Enable to Output Valid

-

25

30

30

45

ns

20

-

25

-

35

20

-

-

70

tOE
tOHZ(1)

-

60

lACs

-

25

-

30

ns

tOLZ(1)

Output Enable to Output in Low Z

5

-

5
5

5

5

5

-

ns

-

-

0

5

-

5

Chip Select to Output in Low Z

-

3

tCLZ(1)
tCHZ(1)

Chip Deselect to Output in High Z

-

20

-

20

-

25

-

25

tOH
IPU(1)

Output Hold from Address Change

5

5
0

0

-

10

0

-

10

Chip Select to Power·Up Time

-

0

-

tPD(1)

Chip Deselect to Power-Down TIme

-

45

-

55

-

65

-

65

-

65

-

65

50

55

-

0

Output Disable to Output in High Z

-

ns

40

ns

10

ns

0

-

ns

-

70

ns

70

-

ns

55

-

ns

-

ns

ns

0

-

0

-

ns
ns

WrHe Cycle
twc

Write Cycle Time

45

Write Pulse Width

35

-

55

twp
lAS

Address Set-up Time

5

-

5

lAw

Address Valid to End of Write

40

tcw

Chip Select to End of Write

40

tDW

Data to Write Time Overlap

tDH

Data Hold Time

20
0(2)

tWR
tWHZ(1)

Write Recovery Time

0(2)

-

Write Enable to Output in High Z

-

toW(1)

Output Active from End of Write

5

45
50

-

60

50

-

60

20
0(2)

-

30

0(2)

-

0

-

15

-

20

-

25

-

5

-

NOTES:
1. This parameter is guaranteed by design, but not tested.
2. IAS=Ons for es controlled write cycles. tDH, IWR= 5ns for WE controlled write cycles.
3. Preliminary specifications only.

UPDATE1 B

0

0

0

-

0

-

-

25

-

30

-

0

-

0
65
65
30
0

0

65
65
35

ns
ns
ns

ns
26751b106

143

1:1

IDT7M4048, IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
(Vcc - 5V + 10% TA - DoC to +70°C)
7M4048LxxN

I

·85

~ymbol

Parameter

Min.

Max.

Min.

·100
Max.

I

·120
Min.
Max.

Unit

Read Cycle
tRC

Read Cycle Time

85

-

100

-

120

-

ns

1M

Address Access Time

tOE

Output Enable to Output Valid

tOHZ(1)

Output Disable to Output in High Z

-

100
100
50
35

-

120
120
60
40

ns

Chip Select Access Time

85
85
48
33

-

lACS

-

tOLZ(1)

Output Enable to Output in Low Z

0

0

-

0

Chip Select to Output in Low Z

5.

5

-

5

-

ns

tCLZ(1)

-

tCHZ(1)

Chip Deselect to Output in High Z

-

43

-

45

-

50

ns

tOH
tPU(1)

Output Hold from Address Change

10

-

10

10

0

-

0

0

-

ns

Chip Select to Power· Up Time

-

tPD(1)

Chip Deselect to Power·Down Time

-

85

-

100

-

120

ns

85
65
2
82

-

100
75
5
90
85
40
0

-

120
90
5
100

-

ns

-

ns

-

ns

-

ns
ns
ns

ns

ns

Write Cycle
twc

Write Cycle Time

twp

Write Pulse Width

lAS

Address Set-up Time

lAW

Address Valid to End of Write

tcw

Chip Select to End of Write

tDW

Data to Write Time Overlap

tDH

Data Hold Time

tWR

Write Recovery Time

tWHZ(1)

Write Enable to Output in High Z

0
0
-

tow(1)

Output Active from End of Write

0

80
38

NOTE:

0

-

33

-

35

-

40

ns

-

0

-

0

-

ns

-

-

ns

100
45

-

ns

-

ns

0

-

ns

0

-

ns

2675 tbl 08

1. This parameter is guaranteed by design, but not tested.

UPDATE1 B

144

IDT7M4048, ID17MB4048
512K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

~-------------tRC------------~
ADDRESS

DATA~------------------------[

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

~---------------t~--------------~

ADDRESS
~-----------tAA------------~
/4-----tOH ----~

DATA OUT

'_____________....c...po._

2675 d/W05

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

D'T.:i: : : '~= - ~=- ~=t-C-LZ=-(-5):_-_tA~C~S~ ~ .-bO l<-.----'
- t. . .12675drw06

NOTES:
1. ~ is High for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. ~=VIL.
'.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
UPDATE1 B

145

IDT7M4048, IDT7MB4048
512K

x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3, 7)

ADDRESS

Iwe

=>

)

OE

./
lAW

~

/
I wp (7)

-lAS

IWR4

~i\..

WE

/
IOHZ (6)

~IWHZ(6) ....

IOHZ IS)

DATA OUT

(4)

IOwIS)

"

c[;,
(4)

/

'"

...!Q!:L..
IDW-

V

DATArN

I"

DATA VALID

)-

)

2675 drw 07

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2, 3, 5)

ADDRESS

Iwe

=>

)V
lAW

CS
-lAS

"1

)V
lew

IWR

WE
DATArN __________________________

~~

IDW

.,14

IDH

DATA VALID

2675 drw08

NOTES:
1. ~ or ~ must be high during all address transitions.
2. A write occurs during the overlap (twP) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. Durin9lhis period, 110 pins are in the output state, and input signals must not be applied.
5. If the ~ low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. During a WE controlled write cycle, write pulse ((twp) > tWHZ + tow) to allow the 110 drivers to tum off and data to be placed on the bus for the required
tDW. If DE is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP.

UPDATE1 B

146

IDT7M4048, ID17MB4048
512K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
lOT

XXXX
A
A
-----999- - - - -A- Device Power Speed Package
Process!
Type

Temperature
Range

I

I

' - - - - - - - - - - f Blank

L - - - - - - - -4

P
N

Commercial (O·C to +70·C)
SOs mounted on an FR-4 DIP
SOs mounted on a Side brazed DIP

17
20

25
30
35
45

'-----~--------455

Speed in Nanoseconds

60
65
70

85
100
120

'---______~~-----~L
S
'---_-'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _--17M4048
7MB4048

Low Power
Standard Power

512K x 8 Static RAM Module (ceramic substrate)
512K x 8 Static RAM Module (FR-4 substrate)
2675 drw09

UPDATE1 B

147

t;).

256K x 8
CMOS STATIC RAM MODULE

PRELIMINARY
IDT7M4068

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• High density 2 megabit CMOS static RAM module
• Equivalent to the JEDEC standard for future monolithic
256K x 8 static RAMs
• Fast access time: 17ns (max.)
• Low power consumption (L version)
- Active: 110mA (max.)
- CMOS Standby: 700J.IA (max.)
- Data Retention: 400J.IA (max.) Vcc = 2V
• Surface mounted LCCs (Ieadless chip carriers) on a 32pin, 600 mil ceramic DIP substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible

The IDT7M4068 is a 2 megabit (256K x 8) CMOS static
RAM module constructed on a co-fired ceramic substrate
using two 1 Megabit static RAMs and a decoder. The
IDT7M4068 is available with access times as fast as 17ns.
For low power applications, the IDT7M4068 version offers a
data retention current of 400!lA and a standby current of
700!lA.
The IDT7M4068 is packaged in a 32-pin ceramic DIP.
This results in a package 1.7 inches long and 0.6 inches
wide, packing 2 megabits into the JEDEC DIP footprint.
All inputs and outputs of thelDT7M4068 are TTL compatible and operate from a single 5V supply. Fully asynChronous circuitry requires no clocks or refresh for operation and
provides equal access and cycle times for ease of use.
All IDT military module semiconduCtor components are
manufactured in compliance with the latest revision of MILSTD-883, Class B, making them ideally suited to applications demanding the highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

ADDRESS
CS

18

256K

x8

RAM

WE
OE
drw02

8

I/O

CEMOS is a trademark of Integrated Device Technology Inc.

MAY 1991

MILITARY TEMPERATURE RANGE
@1991 Integrated Device Technology. Inc.

UPDATEt B

DSC-70761-

148

IDT7M4068
256K x 8 CMOS STATIC RAM MODULE

MIUTARY TEMPERATURE RANGE
PIN NAMES

PIN CONFIGURATION(1)

NOTE 2
A16
A14
A12

Vex:
A1S
A17
WE
A13
As
A9
All
OE
Al0
CS

A7
A6
As
A4
A3
A2
Al
Ao
1/00
1/01
1/02
GND

1100-7

Data InputslOutputs

AO-17

Addresses

CS

Chip Select

WE

Write Enable

OE

Output Enable

Vce

Power

GND

Ground
2675tbl 01

1107
1/06
1/05
1/04
1/03

drw01

DIP
TOP VIEW
NOTE:
1. For module dimensions, please refer 10 the module drawings in the
packaging section.
2. For proper operation of the module, Pin 1 must be connected to GND.

ABSOLUTE MAXIMUM RATINGS(1)

TRUTH TABLE

CS

at:

Standby

H

Read

Output

Power

Symbol

Military

Unit

X

WE
X

High-Z

Standby

VTERM

.,.0.5 to +7.0

V

L

L

H

DOUT

Active

Terminal Voltage
with Respect
toGND

Read

L

H

H

High-Z

Active

TA

X

°C

L

L

DIN

Active

Operating
Temperature

-55 to +125

Write

TBIAS

Temperature
Under Bias

-65 to +135

°C

TSTG

Storage
Temperature

-65 to +160

°C

lOUT

DC Output Current

50

rnA

Mode

2675tb111
CAPACITANCE(1) (TA = +25°C , f =
Symbol

Parameter

1 OMHz)

Conditions

Typ.

Unit

CIN

Input Capacitance

VIN = OV

25

pF

CIN(C)

Input Capacitance (CS)

VIN = OV

10

pF

COUT

Output Capacitance

VOUT= OV

25

pF
2675 tbll0

NOTE:
1. This parameter is guaranteed by design, but not tested.

RECOMMENIDEID IDC OPERATING CONDITIONS
Symbol

Parameter

Min.

Typ.

Max.

Unit

Vce

Supply Voltage

4.5

5

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Input High Voltage

2.2

VIL

Input Low Voltage

-0.5(1)

NOTE:
1. VIL = -2.0V for pulse width less than IOns.

-

6

V

0.8

V

Rating

NOTE:
2675 tbl 02
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device attheseor any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Military

Ambient
Temperature

GND

-55°C to + 125°C

OV

Vee
5V± 10%
2675tb1 04

26751b1 03

UPDATE1 B

149

IDT7M4068
256K x 8 CMOS STATIC RAM MODULE

MILITARY TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS
(Vec = SV ± 10%, TA= -SS°.c to +12S°C)
,

7M4068SxxCB 7M4068LxxCB
Symbol

Parameter

IILlI

input Leakage

IILol

Output Leakage

VOL

Output Low Voltage

VOH

Output High Voltage

lee

Dynamic Operating Current

17ns-55ns

Test Conditions

= Max., VIN = GND to Vee
Vee = Max., CS = VIH,
Vour = GND to Vee
Vee = Min.210L = 2mA(I),
IOL = BmA()
Vee = Min., IOH = -lmA(1),
IOH = -4mA(2)
Vee = Max., CS ~ VIL; f = fMAX,
Vee

60ns-120ns

,Min.

Max.

Max.

Unit

-

10

-

10

IlA

10

-

10

IlA

-

0.4

-

0.4

V

2.4

-

2.4

-

V

-

110

mA

-

240

Min.

Outouts Ooen
158

Standby Supply Current
(TTL Levels)

CS 2: VIH, Vee = Max., f = fMAX,
Outputs Open

-

60

-'

6

mA

1581

Full Standby Supply Current
(CMOS Levels)

CS 2: Vee - 0.2V, VIN 2: Vee - 0.2V
0.2V

-

30

-

2

mA

or~

Very Low Power Version(3)

-

30

-

0.7

NOTES:

mA
2675 tbl 05

1. For 60ns·120ns versions only.
2. For 17ns·55ns versions only.
3. L version only.

DATA RETENTION CHARACTERISTICS(5)
(TA

= -SSOC to +12S°C)

Symbol

Parameter

Test Condition

-

VOR

Vee for Data Retention

leeoR

Data Retention Cumint

CS 2: Vee - 0.2V

teDR(3)

ChiD Deselect to Data Retention Time

VIN ~ Vee - 0.2V or

tR(3)

Operation Recovery Time

VIN> 0.2V

Min.

Max;
Vee@2.0V

2.0

-

V

-

1(4)

rnA

-

ns

-

ns

0
tRe(2)

NOTES:
1. Vcc=2V,TA=+25°C.

2.
3.
4.
5.

Unit

2675tbl 09

tRC = Read Cycle Time.
This parameter is guaranteed by design, but not tested.
For60ns-120ns versions, ICCDR=4001!A.
'
L version only.

DATA RETENTION WAVEFORM
DATA
RETENTION MODE

VOR2: 2V
VOR
_-"~-""-_"""'_ 2675 drw 03

UPDATE1 B

150

IDT7M4D68
256K x 8 CMOS STATIC RAM MODULE

MILITARY TEMPERATURE RANGE

AC TEST CONDITIONS
Input Pulse Levels

GNDto 3.0V

Input RiselFaH Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figures 1 and 2
2675 tbl 07

+5V
480n

480n

DATA OUT -....--~
255n

DATAouT - _ -...
30pF"

. 255n
2675drw 10

Figure 1. Oulpul Load

. Flgure:l: OUlpUI Load
(for IOU, ICHZ, 10HZ, IWHZ, low and ICU)

" Including scope and jig

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V +
- 10%, TA = O°C to +70°C)
7M4068SxxCB; 7M4068LxxCB

.17(a,
Symbol

Parameter

.20(a,

Min.

Max.

Min.

I

Max.

Min.

·25
Max.

·30
Min.
Max.

I

·35
Min. Max. Unit

Read Cycle
tRC

Read Cycle Time

17

-

20

-

25

-

30

-

35

-

1M

Address Access Time

-

17

-

20

25

ns

-

17

-

20

-

35

Chip Select Access Time

-

30

tACS

-

35

ns

tOE

Output Enable to Output Valid

-

8

-

12

-

15

-

15

ns

Z
Output Enable to Output in Low Z
Chip Select to Output in Low Z
Chip Deselect to Output in High Z

-

7

-

10

tOHZ(I)

8

-

12

-

12

-

15

ns

0

0

-

0

-

0

-

0

-

ns

5

-

5

-

5

-

5

-

5

-

ns

-

12

-

13

-

14

-

16

-

20

ns

tOH
tPU(I)

Output Hold from Address Change

1

-

3

-

3

-

3

-

3

-

ns

0

-

0

tPO(I)

Chip Deselect to Power·Down Time

tOLZ(1)
tCLZ(I)
tCHZ(I)

Output Disable to Output in High

Chip Select to Power-Up Time

25

-

0

-

20

-

25

20

-

25

15

-

17

-

17

-

0

30

-

0

ns

-

ns

35

ns

-

30

-

-

30

35

-

ns

-

20

25

ns

Write Cycle
twc

Write Cycle Time

17

twp

Write Pulse Width

14

-

tAS(2)

Address Set-up Time

-

3

-

0

Address Valid to End of Write

-

3

tAW

3
17(4)

-

18

-

20

-

25

-

30

tcw

Chip Select to End of Write

17

-

18

-

25

10

12

15

0

0

0

tWR(2)

Write Recovery Time

0

-

0

-

0

-

17

Data Hold Time

-

-

30

Data to Write Time Overlap

-

20

tow
tOH(2)

0

-

0

-

twHZ(I)

Write Enable to Output in High

-

10

-

13

-

15

-

15

-

15

ns

toW(I)

Output Active from End of Write

2

-

2

-

2

-

5

-

5

-

ns

Z

0

NOTES:
1. This parameter is guaranteed by design, but not tested.
2. tAS=Ons for es controlled write cycles. IDH, tWR= 3ns for WE controlled write cycles.
3. Preliminary specifications only.
4. IAW=14ns foreScontrolied write cycles.
UPDATE1 B

0

20
0

ns
ns
ns
ns
ns
ns

26751bi 06

151

1DT7M4068
256K x 8 CMOS STATIC RAM MODULE

MIUTARY TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
(Vee

= 5V ± 10%, TA = -55°C to +125°C)
7M4068SxxCB, 7M4068LxxCB

I

-45
Symbol
Read Cycle

Parameter

Min.

I Max. I

-60\~1

-55
Min.

I

Max.

I Min.

Max.

-65\~1

I

Min.

I

Max.

-70
Min. I Max. Unit

tRC

Read Cycle TIme

45

-

55

-

65

-

65

-

70

-

ns

1M

Address Access TIme
Output Enable to Output Valid

-

-

Output Disable to Output in High Z

-

-

-

65
65
35
25

-

70
70
45
30

ns

-

60
60
30
25

-

tOE
tOHZ(l)

55
55
30
20

-

Chip Select Access Time

45
45
25
20

-

lACS

-

tOLZ(l)

Output Enable to Output in Low Z
Chip Select to Output in Low Z

-

5
5

-

3
5

-

5
5

-

0
5

-

ns

tCLZ(l)

5
5

tCHZ(l)

Chip Deselect to Output in High Z

20

-

20

-

25

25

-

Output Hold from Address Change

-

10
0

-

-

-

10
0

40
10

ns

tOH
tPU(l)

-

-

0

-

ns

tPO(l)

65

-

70

ns

-

-

ns

-

ns

-

ns

-

70
55
0
65
65
35
0
0

-

ns

-

ns

-

ns
ns

-

-

-

-

Chip Select to Power-Up Time

5
0

-

5
0

Chip Deselect to Power-Down TIme

-

45

-

55

-

65

-

-

-

-

65
50
0
60
60
30
0
0

-

-

55
45
5
50
50
20
0(2)
0(2)

-

65
55
0
65
65
30
0
0

ns
ns
ns
ns
ns

Write Cycle
twc

Wrne Cycle Time

twp

Wrne Pulse Width

lAS

Address Set-up Time

lAW

Address Valid to End of Write

tew

Chip Select to End of Wrne

tow

Data to Write Time Overlap

tOH

Data Hold Time

twR
twHZ(l)

Wrne Recovery Time

45
35
5
40
40
20
0(2)
0(2)

Wrne Enable to Output in High Z

-

15

-

20

-

25

-

25

-

30

toW(l)

Output Active from End of Write

5

-

5

-

0

-

0

-

0

-

-

-

-

-

NOTES:
1. This parameter is guaranteed by design, but not tested.
2. IAS=Ons for ~ controlled write cycles. tDH, twR= 5ns for WI: controlled write cycles.
3. Preliminary specifications only.

UPDATEI B

-

-

-

ns
ns

ns
2675tbl12

152

IDT7M4068
256K x 8 CMOS STATIC RAM MODULE

MIUTARY TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
(Vee - 5V ± 10% TA - -55°C to +125°C)

.

7M4068SxxCB, 7M4068LxxCB
-120 ;
-100
MaX. I Min. I Max. I Min. I MaX.

-85

Symbol
Read Cycle

Parameter

Min.

.-

tAC

Read Cycle Time

85

-

100

1M

Address Access Time
Chip Select Access Time

tOE
tOHZ(l)

Output Enable to Output Valid

48

Output Disable to Output in High Z

-

-

100

lACS

-

85

tOLZ(l)

Output Enable to Output in Low Z

0

0

tcLZ(l)

Chip Select to Output in Low Z

tCHzl 1)

85
33

120

"'-

Unit
ns

120

ns

120

ns

50

-

60

ns

.35

-

40

ns

0

ns

5

-

100

5

-

5

-

Chip Deselect to Output in High Z

-

43

-

45

-

50

ns

tOH
tPU(l)

Output Hold from Address Change

10

10
0

0

-

ns

0

tPO(l)

Chip Deselect to Power-Down Time

-

-

10

Chip Select to Power-Up Time

85

-

100

-

120

ns

100

-

120

-

ns.

90

ns

ns

WrHeCycle
twc

Write Cycle Time

85

twP

Write Pulse Width

65

lAs

Address Set-up Time

2

lAw

Address Valid to End of Write

82

tew

Chip Select to End of Write

80

tow

Data to Write Time Overlap

38

toH

Data Hold Time

0

twR

Write Recovery Time

0

1WHZ(1)

Write Enable to Output in High Z

-

Output Active from End of Write

0

tow

1)

.-

75

-

ns

5

-

5

-

ns

90

100

_.

0

-

0

-

ns

0

-

33

-

35

-

40

ns

-

0

-

0

-

ns

85
40

100

45
0

ns
ns
ns
ns

NOTE:
1. This parameter is guaranteed by design. but not tested.

UPDATE1 B

153

IDT7M4068
256K x 8 CMOS STATIC RAM MODULE

MIUTARY TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 1(1)
~--------__----IRC--------------~

ADDRESS

DATAouT

----<

--~----------------__

2675 drw 04

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

1"----------------- t RC

--------------~

ADDRESS
f4------------- 1M

------------~

f4---------tOH--------~

DATA OUT

2675 drw05

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

~i~c=--==--=-=_- 'C=LZ=(5=)_-_'A~C-S_-_-_-~·-D- - ·!-~t"~I.~
DATAOUT--------------------------~~

~

2675 drw 06

NOTES:
1. M is High for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. ~=VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
UPDATE 1. B

154

IDT7M4068
256K x 8 CMOS STATIC RAM MODULE

MIUTARY TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2, 3, 7)
twe

ADDRESS

=:)K

DE

,

.,

)

"

I\..

./"
tAW

~I"i.

./
twp(7)

i--tAS

tWR--

~

WE

./"

~tWHZ(6) ....

tOHZ(6)

'tOHZ(6)

DATA OUT

(4)

,tOW(6)

'I.,

"-

/

..,!Q!:!....
low--..

DATA IN

I'

DATA VALID

')

"

(4)

)2675 drw07

':,'

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1, 2,3,5)

twe

ADDRESS

=::)'

)
lAW

i--tAS ' }

"

/'
lew

IWR

WE

DATAIN __________________________

~~

tow

~14

tOH

DATA VALID

2675 drwOB

NOTES:

1,
2,
3.
4,
5.
6.
7.

~ or C§ must be high during all address transitions,

A write occurs during the overlap (twp) of a low C§ and a low WE.
twR is measured from the earlier of C§ or ~ going high to the end of write cycle.
During.!i:1is period, I/O pins are in the output state, and input si~ls must not be applied,
"the C§ low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
During a ~ controlled wril!!.9'cle, write pulse «IWP) > IWHZ + tow) to allow the I/O drivers to tum off and data to be placed on the bus for ,the required
tow. If ~ is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified IWP.

UPDATE1 B

155

IDT7M4068
256K x 8 CMOS STATIC RAM MODULE

MIUTARY TEMPERATURE RANGE

ORDERING INFORMATION
IDT

A
-XXXX
- - -A- -999- - - - - - -A' - - Device
Type

Power Speed

Package

Process/
Temperature
Range

----lIB

,--I

'-------------lC
17
20
25
30
35
45
'----------------155
60
65
70
85
100
120
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _--!L
S
'---------------------l7M4068

UPDATE 1 B

Military (-55°C to + 125°C)
Semiconductor component compliant
to MIL-STD-883, Class B
Sidebrazed DIP (Dual In-line Package)

Speed in Nanoseconds

Low Power
Standard Power
256K x 8 CMOS Static RAM Module

156

256K x 8
CMOS STATIC RAM MODULE

PRELIMINARY'
IDT7M4068
IDT7MB4068

Intesrated DevIce Tedmology, Inc.

FEATURES:

DESCRIPTION:

• High density 2 megabit CMOS static RAM module
• Equivalent to the JEDEC standard for future monolithic
256K x 8 static RAMs
• Fast access time: 17ns (max.)
• Low power consumption (L version)
- Active: 110mA (max.)
- CMOS Standby: 200j.IA (max.)
- Data Retention: 100j.IA (max.) Vce = 2V
• Surface mounted plastic packages on a 32-pin, 600 mil
ceramic or FR-4 DIP (Dual In-line Package) substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible

The IDT7M4068/7MB4068 is a 2 megabit (256K x 8)
static RAM module constructed on a co-fired ceramic or
multilayer epoxy laminate (FR-4) substrate using two 1
Megabit static RAMs and a decoder. The IDT7MB4068 is
available with access times as fast as 17ns. For low power
applications, the IDT7M4068 version offers a data retention
current of 100j.IA and a standby current of 200j.IA.
The IDT7M4068 is packaged in a 32-pin ceramic DIP.
This results in a package 1.7 inches long and 0.6 inches
wide, packing 2 megabits into the JEDEC DIP footprint. The
IDT7MB4068 likewise is packaged in a 32-pin FR-4 DIP
resulting in the same JEDEC footprint in a package 1.6
inches long and 0.6 inches wide.
All inputs and outputs of the IDT7M4068 and 7MB4068
are TTL compatible and operate from a single 5V supply.
Fully asynchronous circuitry requires no clocks or refresh for
operation and provides equal access and cycle times for
ease of use.

FUNCTIONAL BLOCK DIAGRAM

ADDRESS
CS

256Kx 8

RAM

WE
DE

110

2823 dow 02

CEMOS is a trademark of Integrated Device Technology Inc.

MAY 1991

COMMERCIAL TEMPERATURE RANGE
4:11991 Integrated Device Technology,lnc.

DSC·7075/-

UPDATE1 B

157

IDT7M4068,IDT7MB4068
256K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION(1)

PIN NAMES

A14

Vee
AIS
A17

A12

WE

A7

A4

A13
As
A9
A11

A3

DE

A2

AID

NOTE 2

AIS

As
As

AI

CS

AD

1/07
1/06
1105
1/04
1/03

1100
1/01
1/02
GND

1100·7

Data Inputs/Outputs

AD-17

Addresses

CS

Chip Select

WE

Wr~e

OE

Output Enable

Enable

Vcc

Power

GND

Ground
28231b10t

2823 drw 01

DIP
TOP VIEW
NOTES:
1.' For module dimensions, please refer to the module drawings in the
packaging section.
2. Forproperoperation olthe 7M4068LxxN module, Pin 1 must be connected
to GND. For 7MB4068xxP module, Pin 1 is a no connect.

ABSOLUTE MAXIMUM RATINGS(1)

TRUTH TABLE
Mode

~

DE

WE

Output

Power

Symbol
VTERM

Terminal VoHage
w~h Respect
toGND

TA

Standby

H

X

X

High-Z

Standby

Read

L

L

H

DOUT

Active

Read

L

H

H

High-Z

Active

Wr~e

L

X

L

DIN

Active
2823 tbi 09

CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
Symbol

Parameter

Conditions

Typ.

Unit

CIN

Input Capacitance

VIN= OV

25

pF

CIN(C)

Input Capacitance (CS)

VIN = OV

8

pF

COUT

Output Capacitance

VOUT= OV

25

pF
2823 tbil0

NOTE:
1. This parameter is guaranteed by design, but not tested.

RECOMMENDED DC OPERATING CONDITIONS
Symbol

Parameter

Min.

Typ.

Max.

Unit

Vcc

Supply Voltage

4.5

5

5.5

V

GND

Supply Vo~age

0

0

0

V

VIH

Input High Voltage

VIL

Input Low Voltage

2.2
-0.5(1)

NOTE:
1. VIL = -2.0V for pulse width less than 10ns.

-

6

V

0.8

V

Rating

Commercial

Unit

-0.5 to +7.0

V

Operating
Temperature

o to +70

·C

TSIAS

Temperature
Under Bias

-10 to +85

·C

TSTG

Storage
Temperature

-55 to +125

·C

lOUT

DC Output Current

50

rnA

NOTE:
282311>102
1. Stresses greaterthan those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device atthese or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial

Ambient
Temperature

GND

Vee

O·Cto +70·C

OV

5V ± 10%
28231b1 04

28231b1 03

UPDATE1 B

158

IDT7M4068,IDT7MB4068
256K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ± 10%, TA = O°C to +70°C)
Symbol

Parameter

Test Conditions

IILlI

Input Leakage

Illol

Output Leakage

VOL

Output Low Vo~age

VOH

Output High Voltage

7MB4068SxxP

7M4068LxxN
Max.

Min.

Max.

Unit

-

2

-

10

J.1A

-

2

-

10

J.1A

-

0.4

-

0.4

V

2.4

-

2.4

-

V

Min.

= Max., VIN = GND to Vee
Vee = Max., CS = VIH,
VOUT = GND to Vee
Vee = Min .• IOl = 2mA(I),
IOl = 8mA(2)
Vee = Min.,loH = -1 mA(I),
Vee

IOH = -4mA(2)
Icc

Dynamic Operating Current

Vee = Max., CS';; Vll; I = IMAX,
Outputs Open

-

110

-

300

mA

ISB

Standby Supply Current
(TTL Levels)

CS ~ VIH, Vee = Max., I = fMAX,
Outputs Open

-

6

-

120

mA

ISBI

Full Standby Supply Current
(CMOS Levels)

CS ~ Vee - 0.2V, VIN ~ Vee - 0.2V
or,;; 0.2V

-

0.2

-

20

mA

NOTES:
1. For 7M4068LxxN version only.
2. For 7MB4068SxxP version only.

2823 tbl 05

DATA RETENTION CHARACTERISTICS(1, 4)
(TA - O°C to +70°C)
Symbol

Parameter

..

Test Condition

-

VOR

Vee lor Data Retention

leeoR
teoR(3)

Data Retention Current

CS ~ Vee - 0.2V

Chip Deselect to Data Retention Time

VIN ,;; Vee· 0.2V or

tR(3)

Operation Recovery Time

VIN ~ 0.2V

Min.

Max.
Vce@2;OV

Unit

2.0

-

-

100

J.1A

0

-

ns

tRcC 2)

V

ns

NOTES:
1. Vcc = 2V, TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by design, but not tested.
4. For 7M4068LxxN version only.

2823 tbl 09

DATA RETENTION WAVEFORM
DATA
RETENTION MODE
VOR~

2V

VOR
2823 drw03

UPDATEI B

159

IDT7M4068, IDT7MB4068
256K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
Input Pulse Levels

GNDto 3.0V

Input RiselFall Times

5ns

Input Timing Reference Levels

1.5V

. Output Reference Levels

1.5V

Output Load

See Figures 1.and 2
2823tb1 07

+5V

+5V

4800

4800
DATAour -...---i

DATAour -..,--..;

2550

2550

2823drw 10

Figure 2. Output Load
(for tOll, tCHZ, toHZ, tWHZ, tow and tcu)

Figure 1. Output Load

• Including scope and jig

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V +
- 10%, TA = O°C to +70°C)
7MB4068SxxP

I

-IT<)

Symbol
Read Cycle

Parameter

Min.

Max.

-20\<)

Min.

J

-25

Max.

Min.

Max.

I

-30

Min.

I

Max.

-35

I Min. I Max.

Unit

Read Cycle Time

17

-

20

-

25

-

30

-

35

-

1M

Address Access Time

17

-

20

-

35

ns

17

25

30

ns

Output Enable to Output Valid

12

-

15

15

ns

Output Disable to Output in High Z

-

12

-

-

35

tOE
tOHZ(1)

-

20

-

30

Chip Select Access Time

-

25

lACs

-

12

-

15

ns

tOlZ(1)

Output Enable to Output in Low Z

0

0

-

5

-

5

5

5

-

ns

2

-

0

Chip Select to Output in Low Z

-

0

tClZ(1)

-

tCHZ(1)

Chip Deselect to Output in High

-

10

-

10

-

14

-

16

-

20

ns

tOH
tPU(1)

Output Hold from Address Change

5

5

-

5

-

lis

0

-

0

0

-

5

0

-

5

Chip Select to Power-Up Time

-

0

-

ns

tPO(1)

Chip Deselect to Power-Down Time

-

12

-

12

-

25

-

30

-

35

ns

20

25

-

30
20

0

-

ns

25

30

-

ns

15

-

20

-

-

35

17

16

-

25

-

30

ns

12

-

15

17

0

0

-

20

0

0

-

ns

0

-

-

0

-

0

-

ns
ns

.IRC

Z

8
7

10
10

0

ns

ns

Write Cycle
twc

Write Cycle Time

17

IWP

Wr~e

14

lAS

Address Set-up Time

0

lAW

Address Valid to End of Wr~e

14

tcw

Chip Select to End of Write

14

tow

Data to Write Time Overlap

10

tOH

Data Hold Time

0

-

IWR

Write Recovery Time

0

-

0

-

IWHt 1)

Wr~e Enable to Output in High

-

10

-

13

-

15

-

18

-

20

tOW(1)

Output Active from End of Write

0

-

0

-

0

-

0

-

0

-

Pulse Width

Z

15
0

NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.

0
20

0

25

ns
ns

ns

ns
2823 tbl 06

UPDATE1 B

160

IDT7M4068,IDT7MB4068
256K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA = DoC to +70°C)
7MB4068SxxP
-45

Symbol
Read Cycle

Parameter

Min.

7M406BLxxN
-60(2)

-55

I Max. I

Min.

I

Max.

Min.

I

Max.

I
I

I

_65(2)

Min.

-70

Max. I Min.

I Max.

Unit

tRC

Read Cycle Time

45

-

55

-

65

-

65

-

70

-

ns

1M

Address Access Time

-

45

-

55

60

-

65

-

70

ns

lACS

Chip Select Access Time

45

-

55

60

-

65

-

70

ns

tOE
tOHZ(!)

Output Enable to Output Valid

-

-

25

-

30

-

30

35

-

45

ns

Output Disable to Output in High Z

-

20

-

20

-

25

-

25

-

30

ns

tOlZ(!)

Output Enable to Output in Low Z

0

-

3

-

0

-

ns

5

5

-

5

-

5

Chip Select to Output in Low Z

-

0

tCll(!)

5

-

5

-

ns

tCHZ(1)

Chip Deselect to Output in High Z

-

20

-

25

-

25

-

25

40

ns

tOH
tpu(1)

Output Hold from Address Change

5

5

ns

0

0

-

10

0

-

10

0

-

10

Chip Select to Power-Up Time

-

0

-

ns

tPO(1)

Chip Deselect to Power-Down Time

-

45

-

55

-

65

-

65

-

70

ns

-

55

-

65

-

65

-

70

-

ns

45

50

-

55

-

55

0

0

-

0

0

60

-

65

60

65

65

30

-

-

-

ns

-

-

30

-

35

-

ns

0

-

0

-

0

-

ns

Write Cycle
twc

Wrtte Cycle Time

45

twp

Write Pulse Width

35

lAS

Address Set-up Time

lAw

Address Valid to End of Write

40

tcw

Chip Select to End of Write

40

tow

Data to Write Time Overlap

25

IDH

Data Hold Time

tWR
tWHZ(1)
toW(1)

0

50
50

65

ns
ns
ns

25

0

-

0

-

Write Recovery Time

0

-

0

-

0

-

0

-

0

-

ns

Write Enable to Output in High Z

-

25

25

-

25

-

25

-

30

ns

Output Active from End of Write

0

-

-

0

-

0

-

0

-

ns

0

NOTES:
1. This parameter is guaranteed by design. but nollesled.
2. Preliminary specifications only.

UPDATE1 B

161

IDT7M4068, IDT7MB4068
256K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V+
- 10% , TA = O°C to +70°C)
7M4068LxxN
-85

~ymbol

Parameter

Min.

I

Max.

I

Min.

-100
I MaX.

-120
Min. I Max.

Unit

Read Cycle
tRC

Read Cycle Time

1M

Address Access Time

lACS

Chip Select Access Time

tOE

Output Enable to Output Valid

tOHZ(1)

Z
Output Enable to Output in Low Z
Chip Select to Output in Low Z
Chip Deselect to Output in High Z

tOlZ(I)
tCLZ(I)
tCHZ(I)

Output Disable to Output in High

tOH
tPU(I)

Output Hold from Address Change
Chip Select to Power-Up Time

tPO(I)

Chip Deselect to Power-Down Time

85
0
5
10
0
-

-

100

-

120

-

ns

85
85
48
33

-

100
100
50
35

-

120
120
60
40

ns

-

0
5

-

-

ns

-

ns

43

-

45

50

ns

-

10
0

-

0
5
10
0

-

ns

-

120

ns

85

-

100

-

-

ns
ns
ns

ns

Write Cycle
twc

Wr~e

Cycle Time

IWP

Wr~e

Pulse Width

lAS

Address Set-up Time

lAW

Address Valid to End of Write

tcw

Chip Select to End of Write

tow

Data to Write Time Overlap

tOH

Data Hold Time

tWR
tWHZ(I)

Write Recovery Time

tow(1)

Output Active from End of Write

Write Enable to Output in High

85
65
2
82
80
38
0
0

Z

-

-

-

100
75
5
90
85
40
0
0

-

33

-

35

0

-

0

-

NOTE:
1. This parameter is guaranteed by design, but not tested.

-

-

120
90
5
100
100
45
0
0
0

-

ns

-

ns

-

ns

-

ns

40

ns

-

ns

ns
ns
ns

ns

2823 tbl 08

UPDATE1 B

162

IDT7M4068, IDT7MB4068
256K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO.

1(1)

~--------------tRC--------------~

ADDRESS

DATAarr -------------------------(
2823 drw 04

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

~-----------------IRC----------------~

ADDRESS
J------------ lAA

------------~

~-------IOH--------~

DATA OUT

2823 drw 05

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

CSi:=-C--=--=--~-,-CL-Z-(5-)-,-A-CS-=-~-.p--.-,~t"~,,,~
DATAOUT-----------------------------~

~

2823 drw 06

NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected, ~ = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE=VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.

UPDATE1 B

163

IDT7M4068, IDT7MB4068
256K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2, 3;7)
twe

ADDRESS

)K

==>K

/

~

tAW

~~

/~
I wp(7)

~IAS

tWR."..-

/'t:

\..

IOHZ(6)

_IWHZ(S1....
tOHZ(S)

DATA OUT

(4)

IOW(S)

"

/

low ____

V

DATA IN

I'"

~

DATA VALID

Y

'"

(4)

)-

)

2823 dlW 07

TIMING WAVEFORM OF WRITE CYCLE NO. 2(CS CONTROLLED TIMING)(1, 2,3,5)
twe ..

ADDRESS

==> K

~IAS 1-

) I'

"

lAW

/1'
lew

DATAIN __________________________

~~

IWR

low

.. I ..

IOH

DATA VALID

2823 drw 08

NOTES:
1.
2.
3.
4.
5.
S.
7.

WE or CS must be high during all address transitions.
A write occurs during the overlap (twP) of a low CS and a low WE.
twR is measured from the earlier of CS or WE going high ·to the end of write cycle.
DUrin9Jhis period, 110 pins are in the output state, and input sil1!'!!ls must not be applied.
If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
During a WE controlled write cycle, write pulse «twp) > tWHZ + tow) to allow the 1/0 drivers to turn off and data to be placed on the bus for the required
tow. If ~ is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP.

UPDATE1 B

164

IDT7M4D68, IDT7MB4068
256K x 8 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

IDT

XXXX

A

999

A

A

Device
Type

Power

Speed

Package

Processl
Temperature
Range

'----------11

Blank

'------------1 ~

Commercial (O'C to +70'C)
SOs on an FR-4 DIP (Dual In-line Package)
SOs on a Sidebrazed DIP (Dual In-line Package)

17
20
25

30
35

45

L - - - - - - - - - - - - - - 1 55

Speed in Nanoseconds

60
65
70
85
100
120

L-__________________________

~L

S

Low Power
Standard Power

L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--I7M4068

256K x 8 Static RAM Module (ceramic substrate)
7MB4068 256K x 8 Static RAM Module (FR-4 substrate)
dIW09

UPDATE1 B

165

(;)
Integrated DevIce Technology, Inc.

256K x 32
BiCMOS/CMOS STATIC RAM
MODULE

PRELIMINARY
IDT7M4077

FEATURES:

DESCRIPTION:

• High density 8 megabit static RAM module

The I DT7M4077 is a 256K x 32 static RAM module constructed on an a multilayer ceramic substrate using 8 1
megabit static RAMs in leadless chip carrier (LCC) packages.
Availabilityoffourwrite enable lines (one foreachgroupoftwo
RAMs) provides byte write capability. The IDT7M4077 is
available with access time as fast as 15ns with minimal power
consumption.
The IDT7M4077 is packaged in a 64 pin sidebraze DIP
(Dual In-line Package). The DIP configuration allows 64 pins
to be placed on a package 3.2 inches long, 0.6 inches wide
and 0.31 inches tall.
All inputs and outputs of the IDT7M4077 are TTL compatible and operate from a single 5V supply. Full asynchronous
circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.
All IDT military modules are constructed with semiconductor components manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making them ideally suited
to applications demanding the highest level of performance
and reliability.

• Low profile 64 pin sidebraze DIP (Dual In-line Package)
Very fast access time: 15ns (max.)
Surface mounted lead less chip carrier (LCC) components
on an multilayer ceramic substrate
• Single 5V (±10%) power supply
Inputs/outputs directly TTL compatible
• Multiple GND pins and decoupling capacitors for maximum noise immunity

PIN CONFIGURATlON(1)
Vee
1100
1101
1102
1103
WEo
GND
1104
1105
1106
1107
Ao
A1
A2
A3
OE
GND
A4
A5
A6
A7
A8
11016
11017
11018
11019
WE2
11020
11021
11022
11023
GND

GND
1108
1/09
11010
110"
WE1
11012
11013
11014
11015
A9
A10
A11
A12
A13
GND

FUNCTIONAL BLOCK DIAGRAM

AO·17

cs-OE __

CS
A14
A15
A16
A17
11024
11025
11026
11027
GND
WE3
11028
1/029
11030
1/031
Vee

256Kx 32

RAM

1100·7 1108·15 11016·23 11024·31
2814 drw 01

PIN NAMES

2814 drw 02

DIP
TOP VIEW

NOTES:
1. For module dimensions, please refer to module drawing in the packaging
section.

1100-31

Data Inputs/Outputs

A0-17

Addresses

CS

Chip Select

WE0-3
OE

Write Enables
Output Enable

Vec

Power

GND

Ground
28141b101

BICEMOS and CEMOS are trademarks of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1991 Integrated Device Technology, Inc.

MAY 1991
05C·7071/-

UPDATEl B

166

IDT7M4D77 256K x 32
BiCMOS/CMOS STATIC RAM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS(l)
Symbol
VTERM

Rating
Terminal Voltage
with Respect
to GND

Commercial

Military

Unit

-0.5 to +7.0

-0.5 to +7.0

V

TA

Operating
Temperature

o to +70

-55 to +125

°C

T81AS

Temperature
Under Bias

-10 to +S5

-65 to +135

°C

TSTG

Storage
Temperature

-55 to +125

-65 to +150

°C

TRUTH TABLE
Mode
CS
Standby

H

OE

WE

Output

Power

X

X

High Z

Standby
Active

Read

L

L

H

DATAoUT

Write

L

X

L

DATAIN

Active

Read

L

H

H

High-Z

Active
6 41b1 02
21

lOUT

CAPACITANCE

DC Output
Current

50

50

RECOMMENDED DC OPERATING
CONDITIONS
Symbol

Parameter

Conditions

Max.

Unit

CliO

1/0 Capacitance
(Data)

V(IN) = OV

15

pF

CINI

Input Capacitance
(Address & Control)

V(IN) = OV

90

pF

CIN2

Input Capacitance
(WE)

V(IN) = OV

35

pF

mA

NOTES:
2614 It> 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in. the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

Min.

Typ.

Max.

Unit

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Vo~age

0

0

0

V

VIH

Input High Voltage

2.2

-

6.0

V

VIL

Input Low Voltage

-0.5(1)

-

O.S

V

NOTE:
1. VIL(min) = -1.5V for pulse width less than IOns.

(TA = +25°C, F = 1.0MHz)

Parameter(1)

Symbol

NOTE:
1. This parameter is guaranteed by design but not tested.

2814 tbl 04

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature

GND

-55°C to + 125°C

OV

5.0V ± 10%

O°Cto +70°C

OV

5.0V

Grade
Military
Commercial

Vee
± 10%
2614 tbl 06

2614 It> 05

DC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V ±10%, TA = -55°C to +125°C and O°C to +70°C)
Symbol

Parameter

Test Conditions
Min.

Ilul

Input Leakage
(Address and Control)

Vee = Max.; VIN = GND to Vee

-

Military
Max.

Comm.
Max.

Unit

120

SO

IlA

Ilul

Input Leakage (Data)

Vee = Max.; VIN = GND to Vee

-

15

10

!LA

Ilul

Input Leakage (WE)

Vee = Max.; VIN = GND to Vee

-

30

20

!LA

IILol

Output Leakage

Vee = Max.; CS = VIH, VOUT = GND to Vee

-

15

10

!LA

VOL

Output Low

Vee = Min., IOL = SmA

-

0.4

0.4

V

VOH

Output High

Vee = Min., IOH = -4mA

2.4

-

-

V

7M4077B(1)
Symbol

Parameter

Test Conditions

lee

Dynamic Operating
Current

f = fMAX; CS = VIL
Vee = Max.; Output Open

158

Standby Supply
Current

CS:2: VIH. Vee = Max.
Outputs Open, f = fMAX

1581

Full Standby
Supply Current

CS:2: Vee - 0.2V; f = 0
VIN> Vee - 0.2V or < 0.2V

NOTE:
1. Preliminary specifications only.

Max.

7M4077S(1)
Military
Max.

7M4077S
Comm.
Max.

Unit

1600

1540

1200

mA

-

SOO

4S0

mA

-

640

SO

mA
26141b1 09

UPDATE1 B

167

IDT7M4077 256K x 32
BICMOS/CMOS STATIC RAM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS
Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

Sns

Input Timing Reference Levels

1.SV

Output Reference Levels

1.SV

Output Load

See Figures 1-4
2814 tbl 08

+S V

+S V

480Q

480Q

DATAouT----------,---------;

DATAouT-----------r--------~

2SSQ

2550 ySPF"

30 pF'

2814 drw03

Figure 1. Output Load

Figure 2. Output Load
(for tolZ, toHZ, lCH Z, lClZ, lWHZ, toW)
• Includes scope and jig.

8

7
6
ATAA
(Typical, ns)

S
4

3

DATAoUT

...[Y-----------,"n
Zo = SOQ

-=

f

2
SOQ

1.SV

20 40 60 80 100120140 160180200
CAPACITANCE (pF)

2814 drw 11

Figure 4. BiCMOS Lumped Capacitive Load;
Typical Derating

Figure 3. BiCMOS Output Load

UPDATE1 B

168

IDT7M4077 256K x 32
BICMOSICMOS STATIC RAM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ±10%, TA

= -55°C to +125°C and O°C to +70°C)
7M4077Bxx
_17(2)

_15(2)

Symbol Parameter
Read Cycla

Min.

Max.

Min.

_20(2)

Max.

Min.

Max.

Unit

tRC

Read Cycle Time

15

-

17

-

20

-

ns

1M

Address Access Time

,15

Chip Select Access Time

-

17
9

-

20
20

ns

lACS
tCLZ(1)

-

Chip Select to Output in Low Z

2

-

2

-

5

-

ns

tOE
tOLZ(1)

Output Enable to Output Valid

-

6

-

8

-

10

ns

Output Enable to Output in Low Z

2

-

2

-'

0

-

ns

tCHZ(1)

, Chip Deselect to Output in High Z

8

-

10
6

-

10
10

ns

5

'-

5

-

ns

-

-

20
15
16
0
15
0

8

tOHZ(1)

Output Disable to Output in High Z

-

5

tOH

Output Hold from Address Change

5

-

ns

ns

Write Cycle

-

Write Recovery Time

15
9
10
0
10
0

-'
-

17 ,
10
12
0
12
0

Write Enable to Output in High Z

-

6

-

7

tow

Data to Write Time Overlap

8

Data Hold from Write Time

toW(1)

Output Active from, End of Write

6
0
2

-

toH

-

0
2

-

twc

Write Cycle Time

tcw

Chip Select to End of Write

lAW

Address Valid to End of Write

lAS

Address Set-up Time

twp

Write Pulse Width

twR
twHZ(1)

-

-

-

-

ns

-

ns

-

ns

-

13

ns

12
0
0

-

ns

-

ns

-

ns

ns
ns
ns,

2814~09

NOTES:
t. This parameter is guaranteed by design, but 'not tested.
,2. I'reliminary specifications only.

UPDATE1 B

169

iii

IDT7M4077 256K x 32
BiCMOS/CMOS STATIC RAM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS
(vee = 5 OV -+10% , TA = -55°C to + 125°C and O°C to +70°C)
7M4077Sxx
-25
Symbol Parameter
Read Cycle

Min.

-30
Max.

Min.

-45

-35
Max.

Min.

Max.

Min.

-55
Max.

Min.

Max.

Unit

tRC

Read Cycle Time

25

-

30

-

35

-

45

-

55

-

ns

!AA

Address Access Time

25

-

30

-

45

-

55

ns

Chip Select Access Time

25

-

30

-

35

tAcs
tClZ(1)

-

35

-

45

-

55

ns

Chip Select to Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

tOE

Output Enable to Output Valid

-

12

-

15

-

18

-

23

-

25

ns

tOlZ(1)

Output Enable to Output in Low Z

0

-

0

-

-

0

-

-

ns

tCHZ(1)

Chip Deselect to Output in High Z

-

18

-

20

-

25

-

25

ns

Output Disable to Output in High Z

-

15

tOHZ(1)

10

-

10

-

10

-

10

-

10

ns

tOH
tPU(1)

Output Hold from Address Change

5

-

5

-

5

0

0

-

0

-

ns

-

-

5

0

-

5

Chip Select to Power-Up Time

tPO(1)

Chip Deselect to Power-Down Time

-

25

-

30

-

35

-

45

-

55

ns

0

0

0

ns

Write Cycle
twc

Write Cycle Time

25

-

30

-

35

-

55

-

ns

Chip Select to End of Write

20

-

25

-

30

-

45

tcw

40

50

Address Valid to End of Write

20

25

-

40

Address Set-up Time

0

25

30

35

40

-

ns

20

tWR
tWHZ(I)

Write Recovery Time

0

-

0

-

0

-

0

-

0

Write Pulse Width

-

0

twp

-

30

tAs

-

-

ns

tAW

-

0

-

ns

Write Enable to Output in High Z

-

15

-

18

-

20

-

23

-

25

ns

tow

Data to Write Time Overlap

15

-

17

20

-

25

30

-

ns

tOH

Data Hold from Write Time

0

-

0

0

-

0

-

0

-

ns

tow(1)

Output Active from End of Write

0

-

0

-

0

-

0

-

0

-

0

0

NOTES:

50

ns
ns

ns
2814 tbl 09

1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.

UPDATE1 B

170

IDT7M4077 256K x 32
BICMOSICIIOS STATIC RAilIiODULE

IIIUTARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

ADDRESS

DATAOUT - - - - - - - - - - - - - - ( .
2814 drw 04

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

AD R~ :~:~ _~- ~- ~- ~- ~- ~- ~tO~-H~ ~ ~ =t-.-A~A=~-t~-~ -I=- ~=- ~:- ~:- ~:- ~·- I-~-tO-H---~~~
..

DATA OUT

PREVIOUS DATA VALID

DATA VALID
2814 drw 05

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

2814 drw 06

NOTES:

1.

WE is High for Read Cycle.

2. Device is continuously selecllld. ~ = VIL.

cs

3. Address valid prior to or coincident with
transition low.
4. l:5I:=VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested..

UPDATE1 B

171

IDT7M4077 256K x 32
BICMOSICMOS STATIC RAM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1(1,2,3,7)
twc

ADDRESS

~
) I\..

=>K:

/~
tAW

~K

/~
tw~~

twp(7)

i4-tAS·

/~

\.

~tWHZ(6).
tOHZ(6)
.

DATA OUT

(4)

tOHZ(6)
tOW(6)

,

L.-

/

~
tDWV

DATA IN

"

)-

(4)

I'.
..

DATA VALID· )

2814 drw 07

TIMING WAVEFORM OF WRITE CYCLE NO. 2(1,2,3,5)

ADDRESS

twc

=>K:
-tAS

)K:
tAW

1

/v
(3)

tWR

tcw

WE
DATAIN ________________________

--i~

tDW

..,1 ...

tDH

DATA VALID

2814 drw 08

NOTES:
1. WE or~ must be high during all address transitions.
2. A write occurs during the overlap of a low ~ and a low ~
3. twR is measured from the earlier of ~ or WE going high to the end of write cycle.
4. Durin9-'his period, 110 pins are in the output state, and input si~ls must not be applied.
5. If the ~ low transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. During a WE controlled write cycle, the write pulse width must be the larger of twp or twHZ + tow to allow the 110 drivers to turn off and data to be placed
on the bus for the required tow. If ~ is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified twP.

UPDATE1B

172

IDT7M40n 256K x 32
BICMOSICMOS STATIC RAM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
IDT

XXXXX

x

x

x

X

Device
Type

Power

Speed

Package

Process!
Temperature
Range

I'------II ~Iank
IC
15

17
20
25

'----------------------~30

35

Commercial (O°C to +70°C)
Military (-55°C to +125°C)
Semiconductor components compliant
to MIL-STD 883, Class B
Sidebrazed DIP (Dual In-line Package)

}s_;, N~,="',

45

55
L -_ _ _ _

------------------~IS

IB

1------------------------'------------1 7M4077

Standard Power
BiCEMOS Power
256K x 32 Static RAM Module
2814drw 10

UPDATE1 B

173

G"

..

SUBSYSTEMS "FLEXI-PAKTM" FAMILY

32K X 32
CMOS EEPROM MODULE

PRELIMINARY
IDT7M7004

Integrated DevIce Technology, Inc.

FEATURES:
•

•

•

•

DESCRIPTION:

High-density 1 megabit CMOS EEPROM modules
Member of the Subsystems "Flexi-Pak" Family of
interchangeable modules, with equivalent pin-outs,
supporting a wide range of applications.
Footprint compatible module upgrades to the next higher
density with relative ease
Fast access time:
- 75ns (max.) 7M7004 commercial
- 95ns (max.) 7M7004 military
Surface mounted LCC components mounted on a co-fired
ceramic substrate
Offered in a 66-pin HIP (Hex In-line Package), occupying
only 1 sq. inch of board space
Single 5V (±10%) power supply
Multiple GND pins and decoupling capacitors for maximum
noise immunity
Inputs and outputs directly TTL-compatible
Please consult the factory regarding the number of Erasel
Write Cycles per Byte Minimum available on the module

The IDT7M7004 is a high-speed, high-density 1 megabit
CMOS EEPROM module constructed on a multi-layer, cofired ceramic substrate using 432K x 8 EEPROM components
in leadlesss chip carriers.
This module is part of the IDT Subsystems "Flexi-Pak"
Family. This family of SRAM/EEPROM/EPROM memory
modules support applications requiring stand alone static or
programmmable memory or those applications needing a
combination of both. All of these module configurations have
equivalent pin-outs, making these "plug-in compatible" (i.e.
inter-changeable), suitable for a wide range. of applications.
The IDT7M7004 is available with access times as fast as
75ns over the commercial temperature range and 95ns over
the military temperature range.
This family of IDT modules are offered in a 66-pin, ceramic
HIP (Hex In-line Package). This HIP package is similar to a
PGA and fits 1 megabit of memory into 1 sq. inch of board
space.
All military IDT modules are assembled with semiconductor
components compliant with the latest revision of MIL-STD883 Class B, making them ideally suited to applications
demanding the highest level of performance and reliability.

FUNCTIONAL BLOCK DIAGRAM

1100-1107

1108-11015

11016-11023

11024-1/031

Ao·A16
OE

2825 drwOl

Fiexi-Pak is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MAY 1991
DSC.7078/·

Cl1991 Integrated Device Technology,lnc.

UPDATE1B

174

IDT7M7004 (32K x 32)
CMOS EEPROM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN NAMES
Name

Description

/100-31

Data Inputs/Outputs

Ao-16

Address Inputs

WE 0-3

Write Enables

CSO-3

Chip Selects

OE

Output Enable

VCC

Power Supply

GND

Ground
TbIOl

PIN CONFIGURATIONS (1,2)

1/08 WEI I/O 15
1/09 eSl 1/014
1/010 GND 1/013
A13 1/011 I/O 12
A14

Ala

A15

All GND
A12 WEo

A16

GND
1/00
1/01
1/02

Vee

OE

GND

1/07
1/06
1/05

1/03

I/O 4

eso

1/024 Vee
1/025 CS3
1/026 WE3
A6
1/027

• 1

.12 .23

34.45.56 •

• 2
.3

.13 .24
• 14 .25

• 4
• 5

.15 .26
.16 .27

35.46.57 •
36.47.58 •
37.48.59 •
38.49.60 •

A7

A3

Ao

.6
.7

• 17 .28
• 18 .29

39.50.61 •
40.51.62 •

GND

A4

Al

A8

A5

A2

.8
• 9

• 19 .30
.20 .31

41.52.63 •
42.53.64 •

A9

WE2
CS2

1/023
1/022

• 10.21 .32
• 11 .22 .33

43.54.65 •
44.55.66 •

GND

1/021

1/019

1/020

HIP
TOP VIEW

1/016
1/017
1/018

1/031

1/030
1/029
1/028

II

Drw02

NOTES:
1. For module dimensions, please refer to the module drawings in the packaging section.
2. For the IDT7M7004 (32K x 32 version), pins 6 and 7 are no connects.

UPDATEl B

175

IDT7M7004 (32K x 32)
CMOS EEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

ABSOLUTE MAXIMUM RATINGS (1)
Symbol

Rating

Com'l.

Mil.

Unit

VTERM

Terminal Vottage
with Respect
to Ground

-0.5 to +7.0

-0.5 to +7.0

V

TA
TBIAS

o to +70

Operating
Temperature

-55 to +125

-10to +85

TSTG

Storage
Temperature

-55 to +125

-65 to +150

·C

lour

DC Output Current

50

50

rnA

·C

Min.

Typ.

Max.

Unit

4.5

5.0

5.5

V

0

0

0

V

Input High Voltage

2.2

6.0

V

Input Low Vottage

-0.5(1)

-

0.8

V

Vee

Supply Vottage

GND

Ground

VIH
VIL

TbI05

TbI04

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.

TRUTH TABLE (1)
Mode
CS

Parameter

Symbol

·C

Temperature
Under Bias

-65 to +135

RECOMMENDED DC OPERATING
CONDITIONS

NOTE:
1. VIL (min.) = -3.0V for pulse width less than 20ns.

CAPACITANCE

(TA = +25°C, f = 1.0MHz)

Parameter(l)

Conditions

Max.

Unit

CIN(I)

Input Capacitance
(Data, CS, WE)

VIN = OV

12

pF

CIN(2)

Input Capacitance
(Address, OE)

VIN = OV

50

pF

Gour

Output Capacitance

Vour= OV

15

pF

Symbol

TbI03

OJ:

WE

Output

Power

Standby

H

X

X

HighZ

Standby

Read

L

L

H

DOUT

Active

Write

L

H

L

DIN

Active

Read

L

H

H

HighZ

Active

NOTE:
1. This parameter is guaranteed by design but not tested.

RECOMMENDED OPERATING
TEMPERATURE AND VOLTAGE SUPPLY

TbI02

NOTE:
1. For the proper' operation of the module,
Cycles.

DE: must be High for all Write

Grade

Ambient Temperature

GND

Commercial

O·Cto +70·C

OV

5.0V

Vee

Military

-55·C to + 125·C

OV

5.0V ± 100/.

± 100/.
TbI06

DC ELECTRICAL CHARACTERISTICS
(Vcc = 5V ± 10%, TA =-55°C to +125°C or O°C to +70°C)
Symbol

Parameter

Test Conditions

Min.

Max.

Unit

= GND to Vee

-

40

~A

= Max., VIN = GND to Vee

-

10

~A

-

10

~A

Vee

-

0.45

V

Vee

2.4

Ilul

Input Leakage Current
(Address, OE)

Vee = Max., VIN

Ilul

Input Leakage
(Data, WE, CS)

Vee

IILol

Output Leakage

Vee = Max.
CS = VIH, Vour = GND to Vee

= Min., IOL = 6mA
= Min., IOH = -4mA
f = 5 MHz, lOUT = 0 rnA
Vee = Max.

VOL

Output Low Voltage

VOH

Output High Voltage

lee

Dynamic Operating Current

ISB

Standby Supply Current
(TTL)

CS ~ 2V to Vee + 1V

-

V

-

320

rnA

-

12

rnA
Tbl07

UPDATE1B

176

IDT7M7004 (32K x 32)
CMOS EEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS
In Pulse Levels
Input RiselFall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

+5V

+5V
GNDto 3.0V
IOns
1.5V
1.5V
See Figures 1 and 2

4800

4800
DATAour

-t__--+

DATAoUT
30pF*

2550

-t__--+

2550

5pF *

lbl08

Drw03

Figure 1. Output Load

Figure 2. Output Load
(for tcHZ)

• Including scope and jig

AC ELECTRICAL CHARACTERISTICS
Vee = 5V ± 10% TA = -55°C to +125°C or O°C to +70°Cl
7M7004SxxCH or 7M7004SxxCHB

Symbol

Parameters

-75
-95
Min. Max •. Min. Max.

-125
Min. Max.

-150
Min. Max.

-200
Min. Max.

Unit

READ CYCLE
tAC

Read Cycle Time

75

-

95

-

125

-

150

-

IAA

Address Access Time

75

-

95

-

125

150

-

200

ns

lACS

Chip Select Access Time

75

--:

95

150

200

ns

Output Enable to Output Valid

40

-

-

tOE

-

70

-

80

ns

tCHZ(l)

Chip Select to Output in High Z

0

40

tOH.

Output Hold.from Address Change

0

200

-

ns

125

50

-

55

-

0

50

0

55

0

55

0

60

ns

-

0

-

0

-

0

-

0

'-

ns

WRITE CYCLE
twc

Write Cycle Time

0.4

10

0.4

10

0.4

10

0.4

10

0.4

10

ms

IAH

Address Hold Time

50

50

-

50

-

ns

2

2

-

ns

Write Pulse Width

-

2

twp
tcs

CS Set-up Time

0

ns

tCH

CSHoidTime

0

tDS·

Data Set·up Time

55

-

50

Address Setup Time

tDH

Data Hold Time

-

50

lAS

-

0

105

55
0

-

2
105
0
0
55
0

2
105
0
0

105

105

ns

0

0

-

55

-

55

-

-

0

-

0

,-

ns

0

0

ns
ns

PAGE MODE WRITE CYCLE
twc

Write Cycle Time

0.4

10

0.4

10

0.4

10

0.4

10

0.4

10

ms

IAH

Address Hold Time

50

-

50

-

50

50

-

ns

Address Setup Time

2

-

2

-

2

-

50

lAS

-

2

tDS

Data Set·up Time

55

-

55

55

55

ns

-

105

105

-

ns

105

-

55

0

-

105

-

-

0.2

200

0.2

200

I1S
ns

tDH

Data Hold Time

twP

Write Pulse Width

105 '

IBLC

Byte Load Cycle Time

0.2

200

0.2

200

0.2

tWPH

Write Pulse Width High

0

0

200

2
0

0

ns

ns

55

-

55

-

55

-

55

-

55

-

DATA POLLING CYCLE
tDH(l)
Data Hold Time

0

-

0

0

0

-

0

-

ms

0

-

0

0,

-

0

Output Enable Hold Time

-

0

tOEH(l)
tOE (1)

Output Enable to Output Delay

-

100

-

100

-

100

-

100

-

100

ns

twA (1)

Write Recovery Time

2

-

2

-

2

-

2

-

2

-

ns

ns

lbl09

NOTE:

1. This parameter is guaranteed by design but not tested.

UPDATEI B

177

IDT7M7004 (32K x 32)
CMOS EEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF READ CYCLE(1)

tRC-~b

ADDRESS

""
DE

IOH _ _

~

1M

" ~" " "'--""II::

I

'\.'\.'\.'\.'\.'\."I.-

///

L

-////////

///'"

////////

///'"

Ics

I CHZ(1)

IOE

I
DATA OUT

NOTES:
I. This parameter is guaranteed by design but not tested.

j
Drw04

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)
twc

ADDRESS
tAH

'\.'\.'\.'\.'\.'\.'\.'\.,,'\.'\.'\.

"'////

I

~////////////////////

"""" ""
tAS_

tCH

l-

.....,'"

I

DATA OUT

ft·Wp

tDS

<*

DATA IN

H
~

tDH==i

DATA VALID

XXXX
OrwOS

TIMING WAVEFORM OF PAGE MODEWRITE CYCLE (1)
DE

/ ,-----------------------------

---------------

---

CS
ISLC

II~/I---

WE

AO-5 --~~~~~~------~~----~,-------II----~xr----~-II--.---'T..........,..=.:..;=f~~;1;~;,:::~-:-"....,..,.-----1I
..
II ---

DATA IN ----~~~~~~~~--~--~J~----~,----II-------~/I-------""""""'"'-'..;..;;;;"--"'1"'------'1---" ....----11 SYTE62
"----""-11--SYTE63
Drw06

NOTES:
I. A6through AI4 must specify the page address during each High to Low transitions of WE (orCS).

UPDATE1 B

DE must be High only when WEand CSare both Low.

178

IDT7M7004 (32K x 32)
CMOS EEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF DATA POLLING CYCLE

~--------------------------------II--------------II--/I

1/07

,------11------'-__/

AO-14
Drw07

NOTES:
1. This parameter is guaranteed by design but not tested.
.
2. AS through A 14 must specify the page address during each High to Low transitions of WE (or ~). ~ must be High only when WE and CS are both Low.

ORDERING INFORMATION
lOT

XXXX

xx

XXX

X

x

Device
Type

Power

Speed

Package

Process!
Temperature
Range
Y:lank

'---------~II

CH

Commercial (ODC to +70DC)
Military (-55DC to +125DC)
Semiconductor components compliant to
MIL-STD-883, Class B
Sidebrazed HIP (Hex In-line Package)

75

95

'-------------~ 125

150
200

~--------------------------~~S
I

'-----------------------1: 7M7004

} Spe"" '"

N""~~"d,

Standard Power
32K x 32 CMOS EEPROM Module
2825dlW 08

UPDATE1 B

179

SUBSYSTEMS "FLEXI-PAKTM" FAMILY

1;)"
IDtesrated DevIce Technology. 1Dc:.

. PRELIMINARY
IDT7M7005

32K X 16/32K X 16
CMOS SRAM/EEPROM
MODULE

FEATURES:

DESCRIPTION:

• High-density CMOS module with SRAM and EEPROM
memory on-board
• Member of the Subsystems "Flexi-Pak" Family of
interchangeable modules, with equivalent pin-outs,
supporting a wide range of applications.
• Footprint compatible module upgrades to the next higher
density with relative ease
• Fast access times:
- 25ns (max.) commercial SRAM
- 30ns (max.) military SRAM
- 75ns (max.) commercial EEPROM
- 95ns (max.) military EEPROM
• Low power CMOS operation
• Surface mounted LCC components mounted on a co-fired
ceramic substrate
• Offered in a 66-pin HIP (Hex In-line Package), occupying
only 1 sq. inch of board space
• Single 5V (±10%) power supply
• Multiple ground pins for maximum noise immunity
• Inputs and outputs directly TTL-compatible
• Please consult the factory regarding the number of Erase/
Write Cycles per Byte Minimum available on the module

The I0T7M7005 is a high-speed, high-density CMOS
module with both SRAM & EEPROM memory on-board. It is
constructed on a multi-layer, co-fired ceramic substrate using
32K x 8 SRAM or EEPROM components in leadlesss chip
carriers.
These modules are part of the lOT Subsystems "Flexi-Pak"
Family. This family of SRAM/EEPROM/EPROM memory
modules support applications requiring stand alone static or
programmmable memory or those applications needing a
combination of both. All of these module configurations have
equivalent pin-outs, making them "plug-in compatible" with
each other, suitable for a wide range of applications.
The I0T7M7005 is available with SRAM access times as
fast as 25nsoverthe commercial temperature range and 30ns
over the military temperature range and EEPROM access
times as fast as 75ns overthe commercial temperature range
and 95ns over the military temperature range.
These modules are offered in a 66-pin, ceramic HIP (Hex
In-line Package). This HIP package is similar toa PGA and
fits the SRAM/EEPROM memory into 1 sq. inch of board
space.
All military lOT military modules are assembled with
semiconductor components compliant with the latest revision
of MIL-STO-883 Class B, making them ideally suited to
applications demanding the highest level of performance and
reliability.

FUNCTIONAL BLOCK DIAGRAM
1/00-1/07

1/08-1/015

32Kx8

32K x 8

32K x 8

32K x 8

SRAM

SRAM

EEPROM

EEPROM

1/016-1/023

1/024-1/031

Ao-A16
OE

2826 drw 01

Flexl-Pak Is a Trademark of Inlegrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
CI991 Integrated DevIce Technology,lnc.

MAY 1991
DSC-70781-

UPDATEl B

180

IDT7M700S (32K x 16/32K x 16)
CMOS SRAM/EEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONSI1,2)
1I0s
1/09
1/010
·A13
'A14
A15
A16
GND
1/00
1/01
1/02

WE, 1/015
CS1 .11014
GND 'j/013
1/011. 1/012
Ala OE
Al1.GND
A12 WEo
Vr£ 1/07
CSo 1106
GND 1/05
1/03 1/04

el
e2
e3
e4
e5
e6
e7
e8
e9
elo
ell

e12
e13
e14
e15
e16
e17
elS
e19
e20
e21
e22

e23
e24
e25
e28
e27
e2S
e29
e30
e31
e32
e33

34.e.45~. 56e
35e 48e:57e
38e 47e 58e
37e 48e 5ge
38e 4ge 60e
3ge50e61e
40e 51e 62e
41e 52e 63e
42e 53e 64e
43e 54e 65e
44e55e66e

1/024
1/025
11028
As
A7
GND
As
A9
1/016
1/017
1/018

Vr£
CS3
WE3
1/027
A3
A4
. As
WE2
CS2
GND
1/019

1/031
1/030
1/029
1/028
Ao
AI
A2
1/023
1/022
1/021
1/020

2826 drw 02

HIP
TOP VIEW
NOTES:
1. For module dimensions, please refer to the module drawings in the packaging section.
2. For the IDT7M7005 (32Kx t6/32K x 16) version, pins 6 and 7 are no connects.
.

PIN NAMES
Name

RECOMMENDED OPERATING
TEMPERATURE AND VOLTAGE SUPPLY

Description

1/00-31

Data Inputs/Outputs

A 0-16

Address. Inputs

\NEO-l

RAM Wr~e Enables

WE 2·3

EEPROM Wr~e Enables

.'

CSO-l

RAM Chip Selects

CS2.3

EEPROM Chip Selects

OE

Output Enable

vee

Power Supply

GND

Ground

..

Grade'

Ambient Temperature

GND

Vee

Commercial

O·Cto +70·C

OV

5.0V± 100/.

Military

-55·C to +125·C

OV

5.0V± 100/.

2B2S1IlI01

TRUTH TABLE II)'
Mode

~

Standby

H

Re~d

L
L
L

Wr~e

Read

CAPACITANCE (TA = +25°C, f ;" 1.0MHz)

rn:

WE

Output

Power

Symbol

Conditions

Max.

UnH

X

HighZ

Standby

CINll)

VIN=OV

12

pF

L
note ..L

H

DOUT

Active

Input Capacitance
(Data, CS, WE)

L

DIN

Active

CIN(2)

50

pF

H

HighZ

Active

Input Capacitance
(Address, OE)

VIN=OV

H

COUT

Output Capacitance

VOUT= OV

15

pF

, X

2826111102

NOTE:
t For the SRAM array OE = X (don't care); however, for the EEPROM array
= H (high).

m:

Parameterl1)

NOTE:
1. This parameter is guaranteed by design but not te~ted.

UPDATEl B.

181

IDT7M700S (32K x 16/32K x 16)
CMOS SRAMlEEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED DC OPERATING
CONDITIONS
Symbol

Parameter

Vee

Supply Vokage

GND

Ground

VIH

Input High Voltage

VIL

Input Low Vokage

ABSOLUTE MAXIMUM RATINGS (1)

Min.

Typ.

Max.

Unit

4.5

5.0

5.5

V

0

0

0

V

2.2
-0.5(1)

-

6.0

V

O.S

Com'l.

Symbol

Rating

VTERM

Terminal Vokage
wnh Respect
to Ground

TA

Operating
Temperature

TBIAS

V

Unit
V

-55 to +125

'c

Temperature
Under Bias

-55 to +125 -65 to +135

'C

TSTG

Storage
Temperature

-55 to +125 -65 to +150

'C

lOUT

DC Output Current

2826tbl 05

NOTE:

1. VIL (min.) = -3.0V for pulse width less than 2Ons.

Mil.

-0.5 to +7.0 -0.5 to +7.0

Oto +70

50

50

mA
28261b1 04

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This Is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS (EEPROM)
(Vee

.

=5V +- 10%

Symbol

TA =-55°C to + 125°C or O°C to +70°C)
Min.

Max.

Unit

Ilul

Input Leakage Current
(Address, OE)

Vee = Max., VIN

= GND to Vee

-

20

!JA

Ilul

Input Leakage
(Data, CS, WE)

Vee = Max., VIN

= GND to Vee

-

10

/LA

IILOI

Output Leakage

Vee = Max.
CS = VIH, VOUT = GND to Vee

-

10

/LA

lee

Dynamic Operating Current

f = 5 MHz, lOUT = 0 mA
Vee = Max.

-

160

mA

ISB

Standby Supply Current
(TTL)

CS

~

-

6

mA

VOL

Output Low Vokage

Vee

= Min., IOL = 6mA

-

0.45

V

VOH

Output High Voltage

Vee = Min., 10H = -4mA

2.4

-

V

Parameter

Test Conditions

2V to Vee + 1V

2826 tbl 07

DC ELECTRICAL CHARACTERISTICS (SRAM)
Svmbol

Parameter

Min.

Max.1t)

MaxP)

Unh

= GND to Vee

-

5

10

/LA

= Max., VIN = GND to Vee

-

10

20

!JA

Test Conditions

IILlI

Input Leakage Current
(Address, OE)

Vee = Max., VIN

Ilul

Input Leakage Current
(Data, CS, wE)

Vee

IILol

Output Leakage Current

Vee = Max.
CS = VIH, VOUT = GND to Vee

-

5

10

/LA

lee

Dynamie Operating Current

Vee = Max., CS ~ VIL
f = fMAX, Output Open

-

400

440

mA

ISB

Standby Supply Curenl

Vee = Max., CS ~ VIH
f = fMAX, Output Open

-

40

140

mA

ISB1

Full Standby Supply Current

CS ~ Vee -0.2V
VIN > Vee -0.2V or < 0.2V

-

40

40

mA

VOL

Output Low Vokage

Vee

= Min., 10L = SmA

-

0.4

0.4

V .

Vee

= Min., IOH = -4mA

2.4

-

-

V

VOH

Output High Voltage

NOTES:

2826 tbl 06

1. For TA = o'e to +70'e versions only.
2. For TA = -55'e 10 +125'e versions only.

UPDATEl B

182

IDT7M700S (32K x 16/32K x 16)
CMOS SRAMlEEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS (EEPROM)
In Pulse Levels
Input RiselFall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

+5V

+5V

GNDto 3.0V
10ns
1.5V
1.5V
See Figures 1 and 2

480(1
DATAoUT

-t---+

255(1

-t---+

DATAoUT
30pF·

255(1

5pF·

28261b1 08

2826 drw03

Figure 2. Output Load

Figure 1. Output Load

(for tcHZ)

• Ineluding scope and jig

AC ELECTRICAL CHARACTERISTICS (EEPROM)
+125°C or O°C to +70°C)

(Vce = 5V ± 10%, TA = -55°C to

Symbol

Parameters

-75
Min. Max.

7M7005SxxlxxCH
7M7005SxxlxxCHB
-125
-150
-95
Min. Max. Min. Max. Min. Max.

-200
Min. Max.

Unit

READ CYCLE
200

-

ns

200

ns

200

ns

70

-

80

ns

0

55

0

60

ns

-

0

-

0

-

ns

tRC

Read Cycle Time

75

-

95

-

125

-

150

-

1M

Address Access Time

75

-

95

75

-

95

125

-

150

Chip Select Access Time

-

125

lACS
tOE

Output Enable to Output Valid

-

40

~

50

-

55

-

tcHZ (1)

Chip Select to Output in High Z

0

40

0

50

0

55

tOH

Output Hold from Address Change

0

-

0

-

0

150

WRITE CYCLE
twc

Write CyeleTime

0.4

10

0.4

10

0.4

10

0.4

10

0.4

10

ms

IAH

Address Hold Time

50

50

-

50

-

ns

2

2

-

2

2

-

ns

twp

Write Pulse Width

105

-

105

-

50

Address Setup Time

-

50

lAS

-

105

-

ns

tcs

CS Set-up Time

0

...,.

0

-

0

-

0

0

0

-

0

0

Data Set·up Time

55

55

55

-

55

-

0

tDS

-

-

ns

CSHoldTime

-

0

tCH

55

ns

tDH

Data Hold Time

0

-

0

0

-

0

-

0

-

105

-

2
105

ns

ns

PAGE MODE WRITE CYCLE
twc

Write Cycle Time

0.4

10

0.4

10

0.4

10

0.4

10

0.4

10

ms

IAH

Address Hold Time

50

-

50

50

-

50

2

2

2

-

2

2

tDS

Data Set-up Time

55

55

55

55

tDH

Data Hold Time

0

0

-

ns

twp

Writ'e Pulse Width

105

105

-

105

-

-

-

ns

Address Setup Time

-

-

50

lAS

-

105

-

105

-

tBlC

Byte Load Cycle Time

0.2

200

0.2

200

0.2

200

0.2

0.2

200

Writ,e Pulse Width High

55

-

55

-

55

-

55

-

55

-

ns

0

0

0

0

0

ms

ns

'.

twPH

55
0

0

0

200

ns
ns
ns
~s

DATA POLLING CYCLE
tOEH( 1)

Output Enable Hold Time

0

-

0

-

0

-

0

-

0

-

tOE (1 )

Output Enable to Output Delay

-

100

-

100

-

100

-

' 100

-

100

tWR(1)

Write Recovery Time

2

-

2

-

2

-

2

-

2

-

tDH(1)

Data Hold Time

ns

ns
28261b1 09

NOTE:

1. This parameter is guaranteed by design but not tested.

UPDATE1 B

183

IDT7M7005 (32K x 16/32K x 16)
CMOS SRAM/EEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC TEST CONDITIONS (SRAM)
In Pulse Levels
Input RiselFali Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDt03.0V
IOns
1.5V
1.5V
See Figures I' and 2
2S26tb1 08

+5V

+5V
480n

480n

DATAoUT
255n

DATAoUT-""---+
30pF*

5pP

255n

2826 drw03

Figure 1. Output Load

Figure 2. Output Load
(for tCLZ, tOLZ, ICHl, tOHZ, tow, twHZ)

"Including scope and jig

AC ELECTRICAL CHARACTERISTICS (SRAM)
(Vee = 5.0V+
- 10%, TA = -55°C to +125°C and O°C to +70°C)

Symbol

Parameters

-25
Min. Max.

7M7005SxxlxxCH
7M7005SxxlxxCHB
-30
-35
-40
I
I
Min. Max. I Min. Max. Min. Max.

I

-45
'Min. Max.

Unit

READ CYCLE
tRC

Read Cycle Time

25

-

30

-

35

-

40

-

45

ns

Address Access Time

25

-

35

-

40

-

45

ns

Chip Select Access Time

25"

-

30

lACS
tCLl(l)

-

-

fAA

30

-

35

-

40

-

45

ns

Chip Select to Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

tOE
tOLl(l)

Output Enable to Output Valid

-

12

20

-

25

ns

Output Enable to Output in Low Z

2

-

5

-

ns

2

13

-

15

-

-

2

-

5

-

-

tCHZ(l)

Chip Select to Output in High Z

-

12

-

15

ns

-

12

-

13

15

-

20

Output Disable to Output in High Z ,.

-

17

tOHZP)

20'

-

20

ns

tOH

Output Hold from Address Change

3

-

3

-

5

-

5

-

5

-

ns

25

-

30

-

35

40

-

45

-

ns

40

-

ns

30

-

40,

ns

2

-

35

-

ns

-'

ns

13

-

17

-

20

-

20

ns

-

16

-

16

20

-

ns

-

3

-

5

-

ns

20

WRITE CYCLE
twc

Wr~e

tcw

Chip Select to End of Write

20

lAW

Address Valid to End of Write

20

Cycle Time

-

25

0

-

0

20

-

23

0

-

lAS

Address Set-up Time

twP

Wr~e

Pulse Width

twR
twHZ(l)

Wr~e

Recovery Time

tow

Data to Write Time Overlap

13

tDH

Data Hold from Wr~e Time

3

towll ),

Output Active from End of Write

5

Wr~eEnable

to Ouput in High Z

25

-

12

-

0

15

-

30
0
25
0

3

-

3

5

-

5

NOTE:
1. This parameter is guaranteed by design, but not tested.

35
35
2
30
0'

,5

-

0

5

n's

ns
2S26tb1 08

UPDATE1 B"

184

IDT7M700S (32K x 16/32K x 16)
CMOS SRAMlEEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS (SRAM CONTINUED)
(Vee = 5.0V± 10%. TA =-55°C to +125°C and O°C to +70°C)

Symbol

-50
Min. Max.

Parameters

I

7M7005Sxx/xxCH
7M7005Sxx/xxCHB
-60
-70
-85
I
I
Min. Max. Min. Max. Min. Max.

I

-100
Min. Max.

Unit

READ CYCLE
tRC

Read Cycle Time

50

-

60

-

70

-

85

-

100

-

ns

1M

Address Access Time

50

-

100

ns

60

70

-

85

50

-

70

Chip Select Access Time

-

60

tACS
tCLZ(1)

-

85

-

100

ns

Chip Select to Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

tOE
tOLZ(1)

Output Enable to Output Valid

-

30

-

30

-

35

45

ns

Output Enable to Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

tCHZ(1)

Chip Select to Output in High Z

20

-

25

-

30

35

-

40

ns

Output Disable to Output in High Z

20

-

25

-

-

tOHZ(1)

-

30

-

35

-

40

ns

tOH

Output Hold from Address Change

5

5

-

5

-

5

-

5

-

ns

60

-

70

-

100

-

ns

65

80

-

90

ns

80

90

45

-

45

-

50

55

-

ns

5

-

-

2

-

-

85

55

0

-

-

-

40

-

WRITE CYCLE
twc

Write Cycle Time

50

tcw

Chip Select to End of Write

45

tAW

Address Valid to End of Write

45

tAS

Address Set·up Time

twP

Write Pulse Width

twR
twHZ(1)

Write Recovery Time

0

-

Write Enable to Ouput in High Z

-

20

tow

Data to Write Time Overlap

25

tDH
toW(1)

Data Hold from Write Time

5

-

Output Active from End of Write

5

-

2
40

55

65

5

5

ns
ns

0

-

-

0

-

ns

-

25

-

30

-

35

-

40

ns

. 30

-

30

35

-

ns

5

-

5

-

ns

5

-

40

5

-

5
5

0

5

5

ns

NOTE:
1. This parameter is guaranteed by design. but not tested.

EEPROM TIMING WAVEFORMS
TIMING WAVEFORM OF READ CYCLE(1)
tRC---~~
ADDRESS

..!

tM

"""",,"k
OE

~~~~~~

.....

I

tOH-<-////////

////

////////

////

tcs

I

///

tCHZ(1)

tOE

DATA OUT

=1
2826 drw04

NOTES:
1. This parameter is guaranteed by design but not tested.

UPDATE1 B

185

IDT7M700S (32K x 16/32K x 16)
CMOS SRAM/EEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)

Iwc

ADDRESS
IAH

,-""""",'

'////

I

""""" " ""---'-,

~////////////////////

ICH

r"1.:",

IAS-

WE

I

DATA OUT

----..J

Iwp
IDS

<==>e 1
/--

II

DATA IN
BYTE 0

BYTE 1

BYTE 2

BYTE3

1/

1/-1/--

X
BYTE 62

BYTE 63
2826 drw 06

NOTES:
1. A6through A14 must specify the page address during each High to Low transitions of WE (or CS). OE must be High only when WE and CSare both Low.

UPDATE1B

186

IDT7M700S (32K x 16/32K x 16)
CMOS SRAMlEEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF DATA POLLING CYCLE

1,---------------------------------//--------------//---

1107

r------//------~__~

Ao-14 _ _ _ _ _ _ _ _ _ _ _---'A;::.n'----'X

An

~~ ~

_-'A"'n'--_ _ '_---'''''-_JI''
2826 dow 07

NOTES:
1. This parameter is guaranteed by design but not tested.
2. AS through A14 must specify the page address during each High to Low transitions olM (or CS).

UPDATEl B

OE must be High only when WE and CS are both Low.

187

IDT7M7005 (32K x 16/32K x 16)
CMOS SRAM/EEPROM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

SRAM TIMING WAVEFORMS
TIMING WAVEFORM OF READ CYCLE NO.

1(1)

ADDRESS

DATAouT--------------------~
2826 drw04

=i___t_RC=-=--=--=-~1=

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

ADDRESS

I:

______
tOH~tAA

__
*"'

tOH~

DATA OUT ____________.L..t-"'X-""X<........>o =====D=A=T=A=V=A=L=ID==4==:==
2826 drw 05

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

CS~~_r

l"~.--i:?

DATAOUT------------~~

L,,",'.'~

~
2826 drw06

NOTES:
1. WE is high for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. OE=VIL.
5. Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.

UPDATEl B

188

IDT7M7005 (32K x 16/32K x 16)
CMOS SRAM/EEPROM MODULE

MIUTARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED)(1, 2,3,7)
twe

ADDRESS

=:),

)K:
/
tAW

~r\.

/'1'
t wp(7)

i4-tAS

tWR_

/V'

r'\.

tOHZ(6)

I+--tWHZ(6)_
10HZ (6)

DATA OUT

(4)

~tOW(6)~

"

(4)

f'.

/

1/

DATA IN

J

tow

"

DATA VALID

)-

tDH

/I
2826 drw 07

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED)(1, 2, 3, 5)
twe

ADDRESS

=:)K

),
tAW

/'.t'
i+-tAS )

tew

DATAIN---------------------------K~

tWR

tDW

.1-

tDH

DATA VALID
2826 drw 08

NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twP) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WI: going High to the end of write cycle.
4. Durina.!tlis period, I/O pins are in the output state, input signals~st not be applied.
5. If the CS Low transition occurs simultaneously with or after the WE Low transition, the outputs remain in a high impedance state.
S. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. During a WE controlled write cycle, write pulse (twP > tWHZ+ tDW) to allow the I/O drivers to turn off data and to be placed on the bus for the required tow.
If Ql; is high during an WI: controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP .

UPDATEl B

189

IDT7M7005 (32K x 16/32K x 16)
CMOSSRAM/EEPROM MODULE

MILITARY AND COMMERCIAL TEMPERATURE RANGES

ORDERING INFORMATION
lOT XXXX
Device
Type

xx

XXX/XXX

X

Power SRAM EEPROM Package
Speed Speed

X
Processl
Temperature
Range

I
I Blank
"---1 B

Commercial (O°C to +70°C)
Military (-55°C to + 125°C)
Semiconductor components compliant to
MIL-STD-883, Class B

CH

Sidebrazed HIP (Hex In-line Package)

75
95
125
150
200

}
Speed in Nanoseconds

25
30
35

40

45

50
60
70
85
100

~------------------------~II S

Speed in Nanoseconds

Standard Power

I 7M7005 32K x16/32K x 16 CMOS SRAM/EEPROM Module
I
2826 drw08

UPDATE1 B

190

~

PRELIMINARY
IDT7MB4064

64Kx 16
BiCMOS STATIC RAM MODULE

Intesrated DevIce Technology. Inc;

FEATURES:

DESCRIPTION:

•
•
•
•

High density 1 megabit BiCMOS static RAM module
Low profile 40-pln DIP (Dual In-line Package)
UHra fast access time: 10ns (max.)
Surface mounted plastic components on an epoxy
. laminate (FR-4) substrate
• Single 5V (±1oak) power supply
• Inputs/outputs directly TTL compatible
• MuHiple GND pins for maximum noise immunity

The IDT7MB4064 is a 64K x 16 BiCMOS static RAM
module constructed on an epoxy laminate (FR-4) substrate
using 4 64K x 4 static RAMs in plastic SOJ packages.
Availability of two chip select lines (one for each group of two
RAMs) provides byte access. Extremely fast speeds can be
achieved due to the use of 256K static RAMs fabricated in
IDT's high performance, high reliability BiCEMOSTM technology. The IDT7MB4064 is available with access time as fast
as 1Ons with minimal power consumption.
The IDT7MB4064 is packaged in a40 pin FR-4 DIP (Dual
Incline Package). The DIP configuration allows 40 pins to be
placed on a package 2.0 inches long and 0.60 inches wide and
0.36 inches tall.
All inputs and outputs of the IDT7MB4064 are TTL
compatible and operate from a single 5V supply. Full
asynchronous Circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of
use.

PIN CONFIGURATION(1)

FUNCTIONAL BLOCK DIAGRAM
CSL
csu
Vee

A15
GND

WE

ADDRESS

CSU
CSL
A14
A13
A12
All
AID
As
GND
As
A17
As
As
A4
A3
A2
AI
AD

11013
1/012
1/011
1/010
1/09
·I/Os

GND
1/07
1/06
1/05
li04
1/03
1/02
1/01
1100
OE
DIP TOP
VIEW

OE -

64KX 16
RAM

8
1100·7

1/08-15
2827 dlW 0,

PIN NAMES

2827 drw02

NOTE:
1. For module dimensions, please refer to the module drawings in the

packaging section.

___-01

1100-15

Data InputslOutputs

A!>-15

Addresses

CSL, CSU

Chip Selects Lower, Upper

WE

Write Enable

OE

Output Enable

Vcc

Power

GND

Ground
2B271b10,

BICEMOS Is trad_of Integrated DevIce Technology. Inc.

MAY 1991

COMMERCIAL TEMPERATURE RANGE
CI'991In1egraled DevIce TocI1nology.lnc.

DSC-7080/-

UPDATE1 B

191

IDT7MB4064 64K x 16
BICMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TRUTH TABLE
Mode
CS OE WE

RECOMMENDED DC OPERATING
CONDITIONS
Symbol

Parameter
Vo~age

Power

Typ.

Max.

Unit

Read

L

L

H

DATAoUT

Active

4.5

5.0

5.5

V

Write

L

X

L

DATAIN

Active

Read

L

H

H

High-Z

Active

Vee

Supply

GND

Supply Vo~age

0

0

0

V

VIH

Input High Voltage

2.2

6.0

V

Input Low Voltage

-0.5(1)

-

Vil

Output

Min.

O.S

NOTE:

2827 tbl 02

V
2827 1Il105

ABSOLUTE MAXIMUM RATINGS(1)

1. VIL (min) = -l.SV for pulse width less than 10ns.

Symbol

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade

Ambient
Temperature

GND

Commerical

O°Cto +70°C

OV

VTERM

Vee
5.0V ± 10%
2827 tbl 06

Rating
Terminal Voltage with
Respect to GND

Value

Unit

-0.5 to +7.0

V

TA

Operating Temperature

o to +70

°C

TBIAS

Temperature Under Bias

-10 to +S5

°C

TSTG

Storage Temperature

-55 to +125

°C

lOUT

DC Output Current

50

mA

NOTE:

CAPACITANCE
Symbol

(TA = +25°C, F = 1.0MHz)

Parameter(1)

Conditions

Max.

Unit

CIN(D)

Input Capacitance
(Data)

V(lN) = OV

10

pF

CIN(A)

Input Capacitance
(Address & Control)

V(IN) = OV

40

pF

GoUT

Output Capacitance

V(OUT) = OV

14

NOTE:

2827 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. . Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

pF
2827 tbl 04

1. This parameter is guaranteed by design but not tested.

DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V +10% TA = O°C to +70°C
Symbol
Ilul

Parameter
Input Leakage
(Address and Control)

Max.

Unit

Vee = Max.;VIN

Test Conditions

= GND to Vee

Min.

-

40

flA

= GND to

-

10

-

10

flA
flA
V

Ilul

Input Leakage (Data)

Vee = Max.; VIN

Illol

Output Leakage

Vee = Max.; CS = VIH, VOUT = GND to Vee

VOL

Output Low

Vee = Min., IOl = SmA

-

0.4

VOH

Output High

Vee = Min., IOH = -4mA

2.4

-

V

lee

Operating Current

Vee = Max,CS " Vll; f = fMAX, Outputs Open

-

720

mA

Vee

2827 tbl 07

UPDATE1 B

192

IDT7MB4064 64K x 16
BICMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/FaU Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V
5ns
1.SV
1.5V
See Figures 1-4
2827 11>108

+5V

+5V

4800

4800

DATAoUT ________~~----~

DATAOUT~~

255n

____~------~
5pP

30 pF*

• includes sCope and jig. .

2827 drw 03

Figure 1. Output Load

Figure 2•. · OutpulLoad
(for tou, 10HZ, ICHZ, tCLZ, twHZ,lOW)

8
7
6

dTAA
(Typical, ns) 5

4
3
2

DATAO~Jt~_----------~~~
Zo.50Q

-=

1

50'1

1.5V

20

2827 drw04

40

60

80

100 120 140 160 180 200

CAPACITANCE (PF)
Figure 4. Lumped Capacitive Load,
Typical Derating

Figure 3. BICMOS Output Load

UPDATE1 B

193

IDT7MB4064 64K x 16
BICMOSSTATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
Vee

= 5V±10%, TA = O°C to +70°C)
7MB4064BxxP
_10(2)

Symbol
Parameter
Read Cycle

-12(2)

Min.

Max.

Min.

-15 .
Max.

-17

Min.

Max.

Min.

Max.

Unit

tAC

Read Cycle Time

10

-

12

-

15

-

17

-

ns

1M

Address Access Time

-

10

-

12

15

-

17

ns

lACS
tClZ(1)

Chip Select Access Time

-

4

-

7

ns

2

-

6
-

-

Chip Select to Output in Low Z

tOE

Output Enable to Output Valid

6

-

-

4

2

-

5

-

-

2

5

-

-

2

toLzl1)

Output Enable to Output in Low Z

2

-

2

-

2

tCHZ(1)

Chip Deselect to Output in High Z

6

-

7

tOHZ(1)

Output Disable to Output in High Z

-

3

-

4

-

5

-

tOH

Output Hold from Address Change

5

-

5

-

5

-

8

2

-

ns

7

ns

-

ns

9

ns

6

ns

5

-

ns
ns

Write Cycle
twc

Write Cycle Time

10

-

12

-

15

-

17

-

tcw

Chip Select to End of Write

7

-

8

-

9

10

-

ns

lAW

Address Valid to End of Write

8

-

9

-

10

-

11

-

ns

-

ns

lAS

Address Set·up Time

0

-

0

-

0

-

0

twp

Write Pulse Width

8

-

9

-

10

11

tWA

Write Recovery Time

0

-

0

-

0

-

tWHZ(1)

Wr~e Enable to Output in High

4

-

5

tDW

Data to Write Time Overlap

4

-

5

-

6

-

8

tDH

Data Hold from Write Time

0

-

0

-

0

tow(1)

Output Active from End of Write

2

-

2

-

2

-

2

Z

NOTES:

-

6

0

0

ns
ns

7

ns

-

ns

-

ns
ns
2827 tbl 09

1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.

UPDATE1 B

194

IDT7MB408464K 1116
BICMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

ADDRESS

DATAour - - - - - - - - - - - - - - - ( .
2827 drw 05

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
~~~-------tRC---------~~~

ADDRESS
DATA our

t::--==--==--=~_~t-O~H~~~~--t-AA~~:~-.~-,:::::::::~.-,-~ C-tO-H---PREVIOUS DATA VALID

DATA VALID
2827 drw06

II

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

~~

...•...
DATA OUT .. .

..-

'"
tCLl

t~

1

2827 drw07

NOTES:

1.
2.
3.
4.
5.

,

WE is High lor Read Cycle..

Devies is continuously selected. ~ =VIL.
Address valid prior to or coincident with ~ transition low.
tiE =VIL.
Transition is measured ±2OOmV from steady state. This parameter is guaranteed by design. but not tested.

UPDATE1 B

195

IDT7MB4064 64K x 16
BICMOSSTATIC RAM MODULE

COMMERCIAL-TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1(1)
~~----~----~---lwC----------------~

ADDRESS

~--~--~Icw--------~

14----
 Wp(2)------I~
DATAouT~~~~~--~-*----------------------~-----------------

I--IDW--....+I.._-IDH=%
DATA IN

--------------------------------<~

XX
2827drw 08

TIMING WAVEFORM OF WRITE CYCLE NO.

2(1,6)

~------------~---lwC--------------~~

ADDRESS
~--------I

cw --------~

~------------------tAW------------~

---+--.-1-........--...---..

14----IWp(2)-----II~/-+------

WE

IWHZ(4,9)
DATAOUT~~~~~--~~~~~~r-----------~------~----~

_ ____

DATA IN

~---------------------(r:---tD~W----~-1-4---ID-H-~--~~(B)~~~
"--

2827 drw09

NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.

~

WI: or CS must be high during all address transitions.

A write occurs during the overlap (~ of a low CS.
IWP is measured from the earlier of CS or WE going high to the end of the write cycle.
,
DuringJhis period, 1/0 pins are in the output state so that the input signals of opposite.2f1ase to the outputs must not be applied.
If the CS low transition occurs simultaneously with the WI: low transitions or after the WE transition, outputs remain in ahigh'impedance state.
~ is continuously low (~ = VIL).
"
"
DOUT is the same phase of write data of this write cycle.
,"
'
",
',,
IfCS is low during this period, 1/0 pins are in the output state, Then the data input signals of opposite phase to the outputs must not be applied totllem.
Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested,

UPDATE1 B

196

IDT7MB4064 64K x 16
BICMOS STAllC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
IDT

XXXXX

x

x

x

X

Device
Type

Power

Speed

Package

Process!
Temperature
Range

IL...----II Blank
~-------------4

~

P

10
__________________~ 12
15
17

Commercial (O°C to +70°C)
FR-4 DIP (Dual In-line Package)

} Speed in Nanoseconds

BiCEMOS Power
~-----------------4

7MB4064 64K x 16 BiCMOS Static RAM Module

2827drw 11

UPDATE1 B

197

®

PRELIMINARY
IDT7MB4065

256K x 20
BiCMOS/CMOS STATIC RAM
MODULE

Intesrated DevIce Technology, Inc.

FEATURES:

DESCRIPTION:

• High density 256K x 20 BiCMOS/CMOS static RAM
module

The IDT7MB4065 is a 256K x 20 BiCMOS/CMOS static
RAM module constructed on an epoxy laminate (FR-4) substrate using 5 256K x 4 static RAMs in plasticSOJ packages.
The IDT7MB4065 is available with access time as fast as 12ns
with minimal power consumption.
The IDT7MB4065 is packaged in a 48 pin FR-4 DIP (Dual
In-line Package). The dual row configuration allows 48 pins to
be placed on a package 2.4 inches long, 600 mils wide and
0.35 inches tall.
All inputs and outputs of the IDT7MB4065 are TTLcompatible and operate from a single 5V supply. Full asynchronous
circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.

• Low profile 48-pin FR-4 DIP (Dual In-line Package)
• Fast access time: 12ns (max.)
• Surface mounted plastic components on an epoxy
laminate (FR-4) substrate
• Single 5V (±10%) power supply
• Inputs/outputs directly TTL compatible
• Multiple GND pins for maximum noise immunity

PIN CONFIGURATION(1)
GND
1/019

1I01S
11017
I/OIS
11015
1/014

11013
11012
11011
11010
GND
DE
1109
liDs
1107
liDs
liDs
1104
1103
1102
1101
1100

Vec

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

FUNCTIONAL BLOCK DIAGRAM
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

CSL

Vce

CSU

A17
A16
A1S
A14
A13

ADDRESS
DE ----'01

A12
All
Al0
A9
CSU
CSL
GND

256KX 20
RAM

WE-__-OI

12
1/00·7

1108·19
2828 drw02

WE
As
A7
As
As

PIN NAMES

A4
A3

1100·19

Data InputslOutputs

A2

AO·17

Address

Al

CSL

Chip Selects· Lower Byte

Ao
GND

CSU

Chip Selects - Upper Byte

2828 drw 01

DIP
TOP VIEW

WE

Write Enable

DE

Output Enable

Vee

Power

GND

Ground

NOTE:

28281t> 01

1. For module packaging dimensions, please refer to the module
drawings in the packaging section.

MAY

COMMERCIAL TEMPERATURE RANGE

1991

OSC·70811·

C1991 Integrated OevIceTechnology.lnc.

UPDATE1 B

198

IDT7MB4065 256K x 20

BICMOS/CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS
Symbol
VrERM

Rating

Comm.

Unit

Terminal Voltage with
Respect to GND

·0.5 to +7.0

V

RECOMMENDED DC OPERATING
CONDITIONS
Min.

Typ.

Max.

Unit

Vee

Supply Voltage

Parameter

4.5

5

5.5

V

0

0

0

V

-

6

V

Symbol

TA

Operating Temperature

Oto+70

·C

GND

Supply Voltage

TBIAS

Temperature Under Bias

·10 to +S5

·C

VIH

Input High Voltage

TSTG

Storage Temperature

·55 to +125

·C

lOUT

DC Output Current

50

mA

NOTE:
28281b1 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of thEi device attilese or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

Input Low Voltage
VIL
NOTE.
1. VIL = ·2.0V for pulse width less than IOns.

OE

WE

Output

Standby

H

X

X

Hi-Z

Standby

Read

L

L

H

Dout

Active

Read

L
L

V
282811J1 03

Grade

Ambient
Temperature

GND

Vee

Commercial

0·Cto+70·C

OV

5.0V± 10%
2828 .bI 04

CS

Write

O.S

RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE

TRUTH TABLE
Mode

2.2
·0.5(1)

X
H

L
H

Power

Din
Hi·Z

CAPACITANCE
(TA

= +25°C, F = 1.0MHz)

Active

Symbol

Parameter(1)

CondRlons

Max.

Unit

Active

CIN(D)
CIN(A)

Input Capacitance
Input Capacitance
(Address and Control)

VIN= OV
VIN= OV

12
42

pF
pF

COUT

Output Capacitance

VOUT= OV

12

pF

282811J1 08

NOTE:
1. This parameter is guaranteed by design but not tested.
2828 tbI 09

DC ELECTRICAL CHARACTERISTICS
(Vee = 5.0V ±100/0, TA = O°C to +70°C)
Symbol

Parameter
Input Leakage
(Address and Control)

Vee = Max.; VIN = GND to Vee

-

IILlI

Input Leakage (Data)

Vee = Max.; VIN = GND to Vee

IILOI

Output Leakage

Vcc = Max.; CS = VIH, VOUT =GND to Vee

VOL

Output Low

VOH

Output High

IILlI

Symbol

Test Conditions

Max.
50

Unit

-

10

I1A

10

I1A

Vee = Min., IOL = SmA

-

0.4

V

Vee = Min., IOH =-4mA

2.4

-

V

Parameter

Test Conditions

= VIL

Dymanic Operating
Current

f = fMAX(2); CS

ISB

Standby Supply
Current

CS ~ VIH. Vee = Max.
Outputs Open, f = fMAX(2)

ISB1

Full Standby'
Supply Current

CS ~ Vee -0.2V; F =0
VIN > Vee - 0.2V or < 0.2V

Icc

Min.

7MB4065B(1) 7MB4065S
Max.
Max.
1000

I1A

Unit

750

mA

-

300

rnA

-

10

mA

Vee = Max.' Output Open

NOTES:
I. Preliminary specifications only.
2. fMAX =l/tRC

2828 11>109

UPDATE.l B

199

IDT7MB4085 2581( x 20
BICMOSICMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
Input Pulse Levels
Input RiselFall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDt03.0V
5ns
1.5V
1.5V
See Figures 1-4
2828.bi 06

+5V

+5V

48011

48011

DATAoUT-'---'---.-----I
25511

DATAoUT----'--.-----I
2550

30 pF*

5pF*

• includes scope and jig.

Figure 2. Output Load
(for tOlZ, tOHZ, tCHZ, tCLZ, tWill, tow)

Figure 1. Output Load

282~~

AC ELECTRICAL CHARACTERISTICS .
(Vee

=5V +1
- 0%, TA = O°C to +70°C)
7MB4065BxxP
_15(2)

_12(2)
Symbol Parameter
Read Cycle

Min.

Max.

Min.

_17<2)

Max.

Min.

Max.

Unit

tRC

Read Cycle Time

12

-

15

-

17

-

ns

1M

Address Access Time

12

ns

7

8

-

17

Chip Select Access Time

-

15

lACS
tCLZ(1)

-

9

ns

Chip Select to Output in Low Z

2

-

2

-

2

,-

ns

tOE
tOLZ(1)

Output Enable to Output Valid

-

5

-

6

-

8

ns

Output Enable to Output in Low Z

2

2

-

2

-

ns

tCHZ(1)

Chip Deselect to Output in High Z

-

-

8

ns

Output Disable to Output in High Z

-

4

tOH

Output Hold from Address Change

5

-

5

-

-

10

tOHz!1)

-

-

15

9

7

6

ns

5

-

ns

-

17

-

ns

-

10

-

ns

-

ns

5

Write Cycle
twc

Write Cycle Time.

12

tcw

Chip Select to End of Write

lAW

Address Valid to End of Write

8
9

lAS

Address Set-up Time

0

twP

Write Pulse Width

9

twR
twHZ(1)

Write Recovery Time

0

Write Enable to Output in High Z

-

5

--,.

7

ns

Data to Write Time Overlap

5

6

8

-

ns

tOH .
toW(1)

Data Hold from Write Time

0

0

-

0

-

ns

Output Active from End of Write

2

-

6
-

-

tow

2

-

2

-

NOTES:
1. This parameter is guaranteed by design, but not tested.
2. Preliminary specifications only.

10
0
10
0

12
0
12
0

,

ns
ns
ns

ns
2828 lb. 09

UPDATE1 B

200

IDT7MB4065 256K x 20
BICMOs/CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

ATM

(TlP~al, 115)

DATA OUT

5

J!:Y-_-----.....,n
Zo=50n

-=-

1

50n

1.5V
20

40

60

80

100 120 140 160 180 200

2828 drw 04

CAPACITANCE (PF)
Figure 4. BiCMOS Lumped Capacitive Load,
Typical Derating

Figure 3. BICMOS Output Load

AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%, TA = O°C to +70°C)
7MB4065SxxP
·2()t~

Symbol

Parameters

Min.

I

·25

Max.

Min.

·35

·30

I Max.

Min.

I Max.

Min.

·45

I Max.

Min.

I Max.

Unit

Read Cycle
tRC

Read Cycle TIme

20

-

25

-

30

-

35

-

45

-

ns

1M

Address Access Time

-

20

-

25

-

30

35

-

45

ns

lACS

Chip Select Access Time

-

20

-

25

-

30

-

35

-

45

ns

leLZ(1)

Chip Select Ie Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

toE

Output Enable to Output Valid

-

10

-

12

-

15

-

18

-

23

ns

toL.Z<')

Output Enable to Output in Low Z

0

-

0

-

0

-

0

-

0

-

ns

tCHZ(I)

Chip Deselect to Output in High Z

-

to

-

12

-

15

-

18

-

20

ns

toHZ(')

Output Disable to Output in High Z

-

10

-

10

-

10

-

10

-

10

ns

toH

Output Hold from Address Change

3

-

3

-

3

-

5

-

5

-

ns

!pu(')

Chip Select to Power Up Time

0

-

0

-

0

-

0

-

0

-

ns

!po(')

Chip Deselect to Power Down TIme

-

20

-

25

-

30

-

35

-

45

ns

IWe

Write Cycle TIme

20

-

25

-

30

-

35

-

45

-

ns

leW

Chip Selection to End of Write

15

-

20

-

25

-

30

-

40

ns

lAW

Address Valid to End of Write

15

-

20

-

25

-

30

-

40

lAS

Address Set-up TIme

0

0

-

0

-

0

-

0

IWP

Write Pulse Width

15

-

-

20

25

-

30

-

ns

Write RecoverY TIme

0

-

0

0

-

0

-

35

IWR

-

0

-

ns

IWHZ(')

Write Enable to Output in High Z

-

13

-

15

-

18

-

20

-

23

ns

lOw

Data to Write TIme Overlap

12

15

..,.

25

'-

ns

0

0

0

-

20

Data Hold from Write Time

-

17

IOH

-

0

-

0

-

ns

tow(')

Output Active from End of Write

0

-

0

-

0

-

0

-

0

-

Write Cycle

ns
ns

ns
2828 tbl 07

NOTES:
1. This parameter is guaranteed by design but not tested.
2. PreliminarY specifications only,

UPDATE1 B

201

IDT7MB4065 256K x 20
BICMOSICMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO.1

(1)

tRC--------------__~
ADDRESS

~~------~-t CLZ(5)tACS-----;---;~
________
~

DATAo~

______________________________

~

2828 drw05

TIMING WAVEFORM OF READ CYCLE NO.2 (1,2,4)
t RC ____________.....
*=~
ADDRESS

t

~:

M - - - - - - - -. .

DATAouT

L-t

-OH---------

DATA VALID

PREVIOUS DATA VALID

2828 drw06

TIMING WAVEFORM OF READ CYCLE NO.2 (1,3,4)

cs ___

~

DATAo~

2828 drw 07

NOTES:
1. Mis High for Read Cycle.
2. Device is continuously selected. CS = VIL.
3. Address valid prior to CS transition low.
4.01:= VIL.
5. Transition is measured ±200 mV from steady state .. This parameter is guaranteed by design, but not tested.

UPDATEl B

202

IDT7MB4065 256K x 20
BICMOS/CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CYCLE)(1)

....1--------- t

we--------~

ADDRESS

~~-

______

tew----------~--

__~

~I-------- t AW --------------~
~~--twP------

__~

-----------r----~~--~

I,~-----------------

t OHZ (4,9) t--__------t~

to

(9)

DATAoUT

DATAIN

--------------l1991 Integrated Device Technology, Inc.

DSC·70821·

UPDATE1 B

205

IDT7MB4066
256K x 16 BICMOSICMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

RECOMMENDED DC OPERATING
CONDITIONS

ABSOLUTE MAXIMUM RATINGS
Symbol
\/TERM

Rating

Comm.

Unit

Terminal Vokage with
Respect to GND

-0.5 to +7.0

V

Symbol

Min.

Typ.

Max.

Unit

Vee

Supply Vokage

Parameter

4.5

5

5.5

V

0

0

0

V

-

6

V

TA

Operating Temperature

o to +70

·C

GND

Supply Voltage

TBIAS

Temperature Under Bias

-10to+B5

·C

VIH

Input High Voltage

2.2

TSTG

Storage Temperature

-55 to +125

·C

VIL

Input Low Vokage

-0.5(1)

lOUT

DC Output Current

50

mA

NOTE:
2829 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

-

O.B

NOTE.
1. VIL = -2.0V for pulse width less than 10ns.

V
2829tbl 03

RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade

Ambient
Temperature

GND

Vee

Commercial

0·Cto+70·C

OV

5.OV ± 10%
2829 tbl 04

CAPACITANCE

TRUTH TABLE
Mode
Standby
Read

~

OE

WE

Output

H

X

X

Hi-Z

L

L

Write

L

X

Read

L

H

H

(TA = +2S·C, F = 1.0MHz)

Power
Standby

Dout

Active

L

Din

Active

H

Hi-Z

Active

Parameter(l)

Conditions

Max.

Unit

CIN(D)
CIN(A)

Input Capacitance
Input Capacitance
(Address and Control)

VIN = OV
VIN = OV

12

36

pF
pF

COUT

Output Capacitance

VOUT= OV

12

Symbol

2829 tbl 08

pF
2829tbl 09

DC ELECTRICAL CHARACTERISTICS
=S OV +10%
, TA = O·C to +70·C)
-

(Vee

Symbol

Max.

Unit

Input Leakage
(Address and Control)

Vee = Max.; VIN = GND to Vee

-

40

I1A

Ilul

Input Leakage (Data)

Vee = Max.; VIN = GND to Vee

I1A

Output Leakage

Vee = Max.; CS = VIH, VOUT = GND to Vee

10

I1A

VOL

Output Low

Vee = Min., 10L = BmA

-

10

IILol

0.4

V

VOH

Output High

Vee = Min., 10H = -4mA

2.4

-

V

Ilul

Symbol

Parameter

Parameter

Test Conditions

Test Conditions

Dymanic Operating
Current

f = fMAX(2); CS = VIL

ISB

Standby Supply
Current

ISBl

Full Standby
SupplV Current

Icc

Min.

7MB4066B(1) 7MB4066S
Max.
Max.

Unit

BOO

600

rnA

CS ~ VIH, Vee = Max.
Outputs Open, f = fMAX(2)

-

240

mA

CS ~ Vee - 0.2V; F = 0
VIN > Vee - 0.2V or < 0.2V

-

8

mA

Vee = Max.' Output Open

NOTES:
1. Preliminary specifications only.
2. fMAX = l1tRC

2829 11>109

UPDATE1 B

206

IDT7MB4D66
256K x 16 BICMOS/CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
Input Pulse Levels
Input RiselFall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1-4
28291b1 06

+5V

+5 V

480n

480n
DATAoUT---------r------~

255n

DATAoUT---------r------~

255n

30 pF*

5pF*

• includes scope and jig.

Figure 1. Output Load

Figure 2. Output Load

282' dON 03

(for tOLZ, tOHZ, tCHZ, tCLz, tWHZ, tow)

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V ±10%, TA = O°C to +70°C)
7MB4066BxxP
_12(2)

Symbol Parameter
Read Cycle

Min.

_1~2)

_15(2)

Max.

Min.

Max.

Min.

Max.

Unit

,

tRC

Read Cycle Time

12

-

15

-

17

-

ns

1M

Address Access Time

12

-

15

ns

Chip Select Access Time

7

-

8

-

17

lAcs
tCLZ(1)

-

9

ns

Chip Select to Output in Low Z

2

-

2

2

-

tOE
tOLZ(1)

Output Enable to Output Valid

-

5

-

Output Enable to Output in Low Z

2

-

tCHZ(1)

Chip Deselect to Output in High Z

7

-

tOHZ(1)

Output Disable to Output in High Z

-

4

tOH

Output Hold from Address Change

5

-

ns

-

8

ns

2

-

ns

8

-

10

ns

-

5

-

6

ns

-

5

-

5

-

ns

15

-

17

-

10

-

ns

9
10

-

12

-

ns

-

ns

2

6

-

Write Cycle
twc

Write Cycle Time

12

tcw

Chip Select to End of Write

8

lAw

Address Valid to End of Write

9

-

lAs

Address Set-up Time

0

-

0

-

0

IWP

Write Pulse Width

9

-

10

-

12

tWR
tWHZ(1)

Wr~e

0

-

0

-

0

Write Enable to Output in High Z

-

6

tow

Data to Write Time Overlap

5

-

6

-

toH
toW(1)

Data Hold from Write Time

0

0

Output Active from End of Write

2

-

-

Recovery Time

-

NOTES:
1. This parameter is guaranteed by design, but not tested.
2. PreliminarY specifications only.

5

2

-

ns

ns
ns

7

ns

8

-

ns

0

-

ns

2

ns
2829 !b109

UPDATE1 B

207

IDT7MB4066
256K X.16 BICMOSfCMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

ATM

(Tl1'IcaI.ns)

DATA OUT

J::.-Y------:::L...,l
=

ZO= 50n

5

50n

1.5V
20

40

60

2829 drw04

80

100 120 140 180 180 200

CAPACITANCE (PF)
Figure 4. BICMOS Lumped Capacitive Load,
Typical Derating

Figure 3. BICMOS Output Load

AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%, TA = O°C to +70°C)
7MB4066SxxP
-2O<~

Symbol

Parameters

Min.

I

-30

-25

Max.

Min.

I Max.

-45

-35

Min.

I Max.

Min.

I Max.

Min.

I Max.

Unit

30

-

35

30

-

25

-

-

45

-

ns

35

-

45

30

-

35

ns

-

45

-

5

ns

-

ns

Read Cycle
tRC

Read Cycle Time

20

-

1M

Address Access Time

-

20

lAcs

Chip Select Access Time

-

20

-

tCLZ(1)

Chip Select to Output in Low Z

5

-

5

toE

Output Enable to Output Valid

-

10

-

12

toLZ1991 Integrated OevIc. Technology. Inc.

DSC-70831-

UPDATEI B

212

IDT7MB4067
256K x 32 CMOS STATIC RAM MODULE

CAPACITANCE

(TA

=+25°C, F = 1.0MHz)

Parameterl1 )

Symbol
Data

CIN(W)

Input Capacitance
(WE)

TRUTH TABLE

CondHlons

Max.

UnH

V(lN)=OV

15

pF

V(IN) = OV

35

pF

va Capacitance

Cvo

CIN(e)

COMMERCIAL TEMPERATURE RANGE

V(lN) = OV

Input Capacitance

1S

pF

Mode

CS

WE

Output

Power

Standby

H

X

Hi·Z

Standby

Read

L

H

Dout

Active

Write

L

L.

Din

Active
2830tbi 02

(OS)
CIN(A)

Input Capacitance
(Address)

V(IN) = OV

SO

pF
2S30tbi 04

RECOMMENDED DC OPERATING
CONDITIONS
Parameter

Min.

Typ.

Max.

Unit

Vee

Supply Voltage

4.5

5.0

5.5

V

GND

Supply Voltage

0

0

0

V

VIH

Inpul High Vollage

S.O

V

Vil

Inpul Low Voltage

NOTE:
1. VIL (min)

Value

Unit

-0.510 +7.0

V

Operating Temperature

010+70

·C

Temperature Under Bias

-1010+S5

·C

Symbol

NOTE:
1. This parameter is guaranteed by design but not tested.

Symbol

ABSOLUTE MAXIMUM RATINGS(1)

-

2.2
-0.5(1)

V

O.S

2S30tbi 05

=-1.5V for pulse wid!h less !han 10ns.

Rating

'lTERM

Terminal Voltage with
Respect to GND

TA
T81AS
TSTG

Storage Temperature

lOUT

DC Output Current

-5510+125

·C

50

mA

NOTES:
2B30tbi03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause pennanent damage to !he device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in lIle operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade

Ambient
Temperature

GND

Commercial

0·Cto+70·C

OV

Vee
5.0V ± 10%
283011>106

DC ELECTRICAL CHARACTERISTICS
(Vee

=5.0V ±1 0%, TA = O°C to +70°C)
7MB40S7

Symbol
Ilul

Max.

Unit

Input Leakage
(Address and Control)

Vee = Max.; VIN

=GND to Vee

-

so

!LA

-

10

!LA
!LA

0.4

V

2.4

-

V

Parameter

Test Conditions

Ilul

Input Leakage (Data)

Vee = Max.; VIN = GND to Vee

Illol

Output Leakage

Vee = Max.; CS = VIH, Vour = GND to Vee

VOL

Output Low

Vee = Min., IOl = SmA

VOH

Output High

Vee

= Min., IOH = -4mA

Min.

10

.'

Svmbol

Parameter

Toot Condltlono

Min.

7MB4067
Me:!.

Unit

Icc

Dynamic Operating
Current

f = fMAX; CS = Vil
Vee = Max.; Output Open

-

1200

mA

158

Standby Supply
Current

CS 2: VIH, Vee = Max.
Outputs Open, f =fMAX

-

480

mA

1581

Full Standby
Supply Current

CS2: Vee- 0.2V; f =0
VIN > Vee - 0.2V or < 0.2V

-

SO

mA
2830 11>1 07

UPDATE1 B

213

IDT7MB4067
256K x 32 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

AC TEST CONDITIONS
Input Pulse Levels

GNDto 3.0V

Input RiselFall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 1 & 2
2830 tbl 08

+5V

+5V

4800

4800

DATA OUT - - - - , - - - - - - l

DATAoUT - - - - . , . . - - - - 1

25snLi 30 ,F'

5 pF*
2830 drw03

Figure 2. Output Load

Figure 1. Output Load

(for teH z. teLZ. IWHZ. tOW)

* Includes scope and jig.

AC ELECTRICAL CHARACTERISTICS
(Vee = 5V -+10% , TA = O°C to +70°C)
7MB4067SxxP
-20(2)
Symbol Parameter
Read Cycle

-25

Min.

Max.

-30

Min.

Max.

Min.

-45

-35
Max.

Min.

Max.

Min.

Max.

Unit

tRC

Read Cycle Time

20

-

25

-

30

-

35

-

45

-

ns

tAA

Address Access Time

-

20

-

25

-

30

-

35

-

45

ns

lACs

Chip Select Access Time

-

20

-

25

-

30

-

35

-

45

ns

tCLZ(')

Chip Select to Output in Low Z

5

-

5

-

5

-

5

-

5

-

ns

tCHZ(')

Chip Deselect to Output in High Z

-

10

-

12

-

15

-

18

-

20

ns

tOH

Output Hold from Address Change

3

-

3

-

3

5

0

-

0

-

0

0

0

-

ns

Chip Select to Power-Up Time

-

5

tpu(')

-

tpo(')

Chip Deselect to Power-Down Time

-

20

-

25

-

30

-

35

-

45

ns

-

35

-

·45
40

-

ns

30
30

-

40

-

ns

0

0

ns

35

-

0

-

0

-

ns

ns

Write Cycle
twc

Write Cycle Time

20

-

25

-

30

tcw

Chip Select to End of Write

15

-

20

-

25

lAw

Address Valid to End of Write

15

20

-

25

lAS

Address Set-up Time

0

0

-

0

twP

Write Pulse Width

15

20

-

25

tWR

Write Recovery Time

0

-

0

-

0

tWHZ(')

Write Enable to Output in High Z

-

13

-

15

-

18

-

20

-

23

ns

tow

Data to Write Time Overlap

12

15

-

17

-

25

0

0

-

0

0

-

0

-

ns

Data Hold from Write Time

-

20

tOH

-

tow(')

Output Active from End of Write

0

-

0

-

0

-

0

-

0

-

NOTES:

30

ns

ns

ns
ns
2830 tbl 09

1. This parameter is guaranteed by design. but not tested.
2. Preliminary specifications only.

UPDATE1 B

214

IDT7MB4067
256K x 32 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO.1

(1)

~""_-----tRC---""----"

ADDRESS

~~~_ _ _ _ _ _ _ _ _ _ ____

_

""'7"~----:*""""'7""-"""'7-

CS
J-.---

tCLZ(S)

DATAoUT-----------------<
2830dM04

TIMING WAVEFORM OF READ CYCLE NO.2 (1, 2,4)

ADDRESS

-Y

I~-.,--"~

---'~~--:~~~=·-tO-H----------------------'~-tO-H-----

DATAoUT

PREVIOUS DATA VALID

DATA VALID
2830 drw05

TIMING WAVEFORM OF READ CYCLE NO.3 (1,3,4)

CS

DATA OUT

i-

~_-=kIDkA-CS
-.-,_ ----,------,r
'--I",.'
L,OH'~
--------

_

2B30drw06

NOTES:

1.
2.
3.
4.
S.

WE is high for read cycle.

Device is continuously selected. CS = VIL.
Address valid prior to or coincident with
transition loVi.

~=VIL.

cs

Transition is measured ±200mV from steady state. This parameter is ·guaranteed by design, but not tested.

UPDATE1 B

215

IDT7MB4067
256K x 32 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING) (1, 2,3,7)

•

twc
ADDRESS .~

,,/

~

/

•

lAw

~ I:-

I-

7 tAS~

~

DATAoUT

(4)

•

twp(7)

..

tWR

7~

f;;:"

,

tWHZ(6)

tOW(6
V

/

(4)

I"
rDW'-'gtDH

DATAIN

V DATA VALID'

I'

/'1
2830 drw07

TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING) (1,2,3,5)
~-------------twc------------~··I

ADDRESS
~----------tAW----------~

;~i~--------tcw -------4~I~~. .rtwR

r;tDW'-'

DH~I

DATAIN ---------------i(~ DATA VALID

)1>1-----2B30 drw 08

NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CS and a low WE.
3. twR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition transition occurs simultaneously with or after the WE low transition, the outputs remain in a high impedance state.
6. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by
design but not tested.
7. During a WE controlled write cycle, the write pulse width must be the larger of twP or (twHz + tDW) to allow the 110 drivers to turn off and data to be placed
on the bus for the required lOW.

UPDATE1 B

216

IDT7MB4067
256K x 32 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
IDT

XXXXX

x

x

X

x

Device
Type

Power

Speed

Package

Process!
Temperature
Range
,YBlank

L--------li P
I

Commercial (O°C to +70°C)

FR-4 DIP (Dual In-line Package)

20
25

L..-------------------l30

35

45

L..-----'------------l-l S
" Standard Power'
L..-______________------1~ 7MB4067 256K x 32 Static RAM Module
2830 drw010

UPDATE1 B

217

t;)"

DUAL (16K x 60)
DATA/INSTRUCTION CACHE
MODULE FOR IDT79R3000 CPU

PRELIMINARY
IDT7MB6139

Integrated DevIce Teclmolol)'. Inc.

FEATURES:

DESCRIPTION:

• High-speed CMOS static RAM module constructed to
support the IDT79R3000 RISC CPU as a complete data
and instruction cache
• Operating frequencies to support 12MHz, 16.7MHz,
20M Hz, 25MHz and 33MHz IDT79R3000
• Available in high-density, low profile 128-pin QIP (Quad
In-line Package) with special stand-off
• Surface mounted SO components on a multi-layer epoxy
substrate (FR-4)
• Multiple GND pins and decoupling capacitors for
maximum noise immunity
• On-board address latches for direct interface to the
IDT79R3000 CPU
• TTL compatible II0s
• Single 5V (± 10%) power supply

The IDT7MP6139 is a 240K-byte high-speed CMOS static
RAM cache module constructed on a multilayer epoxy substrate (FR-4) using 28 (16K X 4) SRAMs, 8 IDT74FCT373
latches, and a IDT74FCTT244 buffer.
The construction and specifications of this module have
been optimized to support its use as a complete 16K deep
Instruction and Data cache for the IDT79R3000 MIPsTM
microprocessor.
The IDT7MB6139 is organized as two separate banks of
16K x 60 with the IDT74FCT373s being used as address
latches.The two banks of RAM with their associated address
latches share a common 14-bit ADDRESS bus and a common
60-bit DATA bus. The chip select, write enable, RAM output
enable and latch enable controls forthe two banks are brought
out separately to support interleaving access to the two banks
of RAM. Each bank of address latches reduces the capacitance loading on the outpuits of the latches; thereby, enhancing CPU performance.
All inputs and outputs ofthe IDT7MB6139 are TTL-compatible and operate from a single 5V supply. Fully asynchronous
circuitry is used, requiring no clocks or refreshing for operation.

PIN CONFIGURATION
GNO
00
02
04
Os
08
~1
CS11
CS15
~
011
013
Ao

65
66
67
68
69
70
71
72
73
74
75
76

GNO
01
03
05
07
09
rn:1
GNO
010
~
012

77

A2
A4

78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95

A1
A3
A5
GNO
LEl
LE3
016

014
GNO
GNO
015
017
018
020

WE2

~2
~s

wts

023
025
027
029
031

Vee

Vee

Vee
019
021
~
GNO
022

0Es

Vee 12~1) (1)64

N.C.
N.C.
058
056
GNO

Wbt
054
053

WEB
051
GNO
A12
A10

As
As
LE2
LE4
GNO
047
045
043
WE7
GNO
042
~

Vee
N.C.
N.C.
059
057
055

12 (1) (1)63
126
62
125
61
124
60
123
59
122
58
121
57
120
56
119
55
118
54
117
53
116
52
115
51
114
50
113
49
112
48
111
47
110
46
109
45
108
44
107
43
106
42
105
41
104
40
103
39
102
38
101
37
100
36
99
35
98
34

OS!

~4
~8

0Es

052
050
A13
A11
A9
A7
GNO
GNO
049
048
046
044
rn:7
~7
~3
~
041
039
039
036
034
GNO

PIN NAMES
Do - 059

Data Inputs/Outputs

Ao -A13

Address Inputs
Lateh Enables
RAM Selec1s
Write Enables
Outout Enables
Ground
Power Supplv
No connec1ion (1)

LEl - LE4
CS1l-CS1a
WEl-WEs
OE1-0Es
GND

Vce
N_C.

2BOO Ibl 01

2600 drw 01
NOTES:
1. Pins 62, 63, 126, and 127 must be connected to GNO for proper

operation of this module.
2. For module dimensions, please refer to module drawings in the
packaging section.

MAY 1991

COMMERCIAL TEMPERATURE RANGE

DSC-7084I-

...1991 Integrated DevIce Tochnology.lnc.

UPOATEI B

218

IDT7MB6139 (2 x 16K x 60) DATAilNSTRUCTlON
CACHE MODULE FOR IDT79R3000 CPU

COMMERCIAL TEMPERATURE RANGE

CACHE - BANK "A"

I

A()"6

I
I

..

FCT
373

AC()"6

~

LATCH

00-15

619B

~

16K X 4

~~

-

LE3

I

I

I

WE5 OE5

..

CS15

I

-"
A 7-13

~

I

FCT
373

I

~

AC7-13

...016-31 ..

LATCH
619B

..

~

16K X 4
L-..

I

I

I
CS16

WE6 OE6

I

I

---.

FCT
373

~

LATCH

.

16K X 4

-.l

WE7

-.l

OE7

,
FCT
373

--.L

o 4S-59

........

619B
16K X 4

I
WEs

UPDATE1B

I

FCT
244
BUFFER

.2 36-39 ..

.....

...

I

~

LATCH

....

CS17

I

A07-13

..

'p 4O -47 ..

.....

'-

~

...
V

........0 32-35....,.

619B

AO()"6

..
r

I

OEs CS1s

2800 drw02

219

IDT7MB8139 (2 x 18K x 80) DATA/INSTRUCTION
CACHE MODULEFORIDT79R3000 CPU

COMMERQALTEMPERATURERANGE

CACHE· BANK "B"
I
I
Ao-e

L

.....

FCT
373

Mo-e

~

LATCH
,'"

,

~

.....

....

16K X 4

-

'-

LE1

~ ~

WEl

r

C811

I
I

FCr
373

..

~

OEl

~r

A 7-13

00-15

6.198'

~

. M7-13

i

LATCH

,.016-31

6198

.....

161$ X 4

.

r

'-

--.!
WE2

~

~

OE2

C812

I
I
FCT
373 ..

~.

ABo-s
.,.

LATCH

..

- ~D32-35...

..-.'

6198·
16K X 4

~

~

.

-.l

~,~

---1

WE7 OE7

r

.....

--L

..

FCT

244
BUFFER

C817

.2_ ...

-

.

I

,
FCT
373

-

~4Q-47 ...

--;

.I

AB7-13 .....

~
6198

LATCH

,.048-59 ..

16K X 4
L....

I
WE4

I

I

OE4 C814

2BOO drw 03

:'!,

UPDATE1 B

220

IDT7MB6139 (2 x 16K x 60) DATA/INSTRUCTION
CACHE MODULE FOR IDT79R3000 CPU

COMMERCIAL TEMPERATURE RANGE

RECOMMENDED DC OPERATING
CONDITIONS

ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM

Rating

Comm.

Unit

Terminal Voltage with
Respect to GND

-0.5 to +7.0

V

Min.

Typ.

Max.

Unit

Vee

Supply Voltage

4.5

5

5.5

V

a

a

a

V
V

Symbol

Parameter

TA

Operating Temperature

a to +70

°C

GND

Supply Voltage

T81AS

Temperature Under Bias

-10 to +85

°C

VIH

Input High Voltage

2.2

-

6

TSTG

Storage Temperture

-55 to + 125

°C

VIL

Input Low Voltage

-0.5 (')

-

0.8

lOUT

DC Output Current

50

rnA

NOTE.
1. VIL (min.)

2BOO Ibl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

V
2800 tbl 03

~

-3.0V for pulse width less than 20ns.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

TRUTH TABLE

Grade

Ambient
Temperature

GND

Vee

Commercial

O°Cto +70°C

OV

5.0V ± 10%
2800 tbl 04

OE

WE

Output

Power

X
X

X
X

High Z

Standby

H

HighZ

Standby

CS1

CS2

Standby

H

X

Standby

X

Mode

CAPACITANCE

(1)

(TA

=+25°C, F =1.0 MHz)

Read

L

L

L

H

Dout

Active

Symbol

Parameter

Conditions

Typ.

Unit

Read

L

L

H

H

High Z

Active

CIN

Input Capacitance

VIN = OV

30

pF

Wr~e

L

L

X

L

DIN

Active

COUT

Output Capacitance

VOUT = OV

18

pF
2800 tbl 08

NOTE:
1. This parameter is guaranteed by design but not tested.

2BOO Ibl 07

DC ELECTRICAL CHARACTERISTICS
(Vcc=5.0V ± 10%, TA = O°C to +70°C)
Symbol

12MHz

16.7 MHz

20 MHz

25 MHz

Min. Max.

Min. Max.

Min. Max.

Min. Max.

33 MHz

20

-20

20

·20

20

-20

20

-20

20

itA

10

-10

10

-10

10

-10

10

-10

10

itA

-

3000

-

3000

-

3500

-

3750

rnA

3750

-

3750

-

4050

-

4500

-

4750

rnA

-

450

-

450

-

450

-

600

-

750

rnA

-

1500

-

1500

-

1650

-

1800

-

2000

rnA

Parameter

Test Conditions

III

Input Leakage
Current

Vee = Max.,
VIN = GND to Vee

-20

ILO

Output Leakage
Current

Vee = Max., CS = VIH,
VOUT = GND to Vee

-10

ICC1

Operating
Current

CS = VII, Vee = Max.
Outputs Open, f = a

-

3000

lee2

Dynamic Operating
Current

Vee = Max., CS = VII,
f = fMAX, Outputs Open

-

IS81

Full Standby
Operating Current

CS ~ Vee - 0.2V, VIN>
Vee - 0.2V or <·0.2V

IS8

Standby Power
Supply Current

CS ~ VIH, Vec = Max.,
Outputs Open, f = fMAX

VOH

Output High
Voltage

Vee = Min.,
IOH=4mA

2.4

-

2.4

-

2.4

-

2.4

-

2.4

-

Output Low
Voltage

Vee = Min.
IOL= 8mA

-

0.4

-

0.4

-

0.4

-

0.4

-

0.4

VOL

Min. Max. Unit

V
V

2BOO Ibl 05

UPDATE1 B

221

'
.
.
COMMERCIAL TEMPERATURE RANGE

IDT7MB6139 (2 x 16K x 60) DATA/INSTRUCTION
CACHE MODULE FO~ IDT79R3000 CPU

AC TEST CONDITIONS
Input Pulse Levels
Input RiselFall Times .
Input Timing Reference. Levels
Output Reference Levels
Output Load

GNDto 3.0V
5ns
1.5V
1.5V
See Figores 1 and 2
2800 tbl 06

.

~+5V480n

DATA out .

DATA out

".

255n

~

. . +5V480n

.

30pF*

.'

255n

. 5pF*
2BOOdrw04

* Including scope and jig.

Figure 1. Output Load

Figure 2. Output load
(for tOLZ, toHZ)

AC ELECTRICAL CHARACTERISTICS

(vee = s.ov ±10%, TA = O°C to +70°C)

12MHz
Symbol

Parameters

Min.

Read Cycle
tLE
Latch Enable Width

Max.

lAs

Address Setup Time to LE

4

-.
-

IAH

Address Hold Time from LE

3

-

1AA(2)

Address Access Time

lACS

Chip Select Time

tOE

Output Enable Time

tOHt l )

Output Disable to. Output in High Z

2

tOHt l )

Output Disable to Output in Low Z

WrHeCycie

8

-

45

16.7 MHz
Min.

Max.

20 MHz
Min.

Max.

25
Min.

-

6

2

1.5

-

1.5

-

3.5

-

35

-

30

6
2

6

4

MHz
Max.

-

33 MHz
Min.

Max. Unit

6

-

ns

4

-

ns

3.5

25

-

20

ns

20

15

ns

,5

ns

6

ns

25

17

-

13

-

8

-

14

2

10

2

8

2

5

-

5

-

5

-

5

-

ns

6

-

6

6

-

6

-

4

-

ns

·4

1.5

-

25

-

23

20

: 18

-

15

20

-

17

-

12

13

-

11

8

0

-

0

-

40

-

22

-

16

2

5

-

.2

30

ns

..

tLE

Latch Enable Width

8

lAS

Address Setup Time to LE

4

IAH

Address Hold Time from LE

3

-

lAw

Address Valid to End of Wrke

40

-

30

tcw.

Chip Select to End of Wrke

35

-

25

twp

Wrke Pulse Width

30

-

25

tow

Data Valid to End of Wrke

20

13

tOH

Data Hold Time

-

-

0

-

0

1.5

2

3.5

-

3.5
20

0

-

ns
ns
ns
ns
ns
ns
ns
2800 tbl 07

NOTES:

1. This parameter is guaranteed by design but not tested.
2. LE already asserted.

UPDATE1 B

222

IDT7MB6139 (2 x 16K x 60) DATA/INSTRUCTION
CACHE MODULE FOR IDT79R3000 CPU

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE(1)

ADDR

ADDR VALID

tAS

LE

tAH

tLE

tOE

DE

tOLZ (2)
DATAoUT---------------------------;----~

DATA VALID

tACS

2800 drw 05

NOTES:
1. WE and CS must be High for all address transitions.
2. This parameter is guaranteed by design but not tested.

UPDATE1 B

223

IDT7MB6139 (2 x 16K x 60) DATA/INSTRUCTION
CACH.E MODULE FOR IDT79R3000 CPU

COMMERaALTEMPERATURERANGE

TIMING WAVEFORM OF WRITE CYCLE(1)
....,

)(

ADDR

tAS

LE

-./'

)(

ADDRVALID

V-

tAH

"\..

."
",

tLE

)

DATA IN

"-

tAW
tWP

.

./

'"

~H

tDW

V'

"

V

[)/

DATA VALID

tcw

/'

28OOdlW06

NOTE:
1. A write occurs (IWP) during the overlap of a Low CS and WE and a High LE.

UPDATE1 B

224

IDT7MB6139 (2 x 16K x 60) DATA/INSTRUCTION
CACHE MODULE FOR IDT79R3000 CPU

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
lOT

XXXX
Device
type

999
Speed

A

PrOCeSS!
Temperature
range

BLANK Commercial (O°C to +70°C)

K

12
16
~----------------------~ 20
25
33

~~--------------------------~ S

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-j

UPDATE1 B

FR:4 QIP (Quad In-line Package)

12MHz }
16.7 MHz
2. a MHz.
25 MHz
33 MHz

. Speed in Megahertz

Standard Power

7MB6139 (2x 16Kx 60) Data/Instruction Cache Module

225

128K x 8
64Kx8
CMOS DUAL-PORT
STATIC RAM MODULE

ADVANCE
INFORMATION
IDT7MP1021
IDT7MP1023

FEATURES

DESCRIPTION:

• High density 1M/512K CMOS dual-port static RAM
module
• Fast access times:
- 25,30,35,40,50, 65ns
• Fully asynchronous reacllwrite operation from either port
• On-board semaphore. (SEM) controls
.
• Surface mounted plastic components on a 64-pin FR-4
SIMM (Single In-line Memory Module)
• MuHiple .GND pins and decoupling capacitors for maximum noise immunity
• Single 5V (±10%) power supply
• Input/outputs directly TTL compatible

The IDT7MP1 021/1DT7MP1023 is a 128Kx8/64Kx8 highspeed CMOS dual-port static RAM module constructed on a
muHilayer glass epoxy laminate (FR-4) substrate using eight
IDT7006 (16K x 8) dual-port RAMs and two IDT 74FCT138
decoders or depopulated using only four IDT7006s and two
decoders.This module provides two independent ports with
separate control, address, and I/O pins that permit independent and asynchronous access for reads or writes to any
location in memory. TheSEM controls can be used to facilitate
port-to-port communication via "handshake" signaling. The
SEM controls are logic latches which are part of the IDT7006
but independent of the dual-port RAM memory array. This
control allows the signalling of information to easily pass
through the dual-port module.
The IDT7MP1021/1023 module is packaged on a multilayer glass expoxy laminate (FR-4) 64-pin SIMM (Single Inline Memory Module) with dimensions of only 3.85" x 0.305"
x 1.12". Maximum access times as fast as 25ns over the
commercial temperature range are available.
All inputs and outputs of the IDT7MP1021/1023 are TTL
compatible and operate from a single 5V supply. Fully
asynchronous circuitry is used, requiring no clocks or refreshing for operation of the module.

PIN CONFIGURATION
vee

1

L3il:
L_RIW

3

L_~

7

L_~

9

2
4
6
8

5

L_I/O(O)
L_I/O(l)

GND

11
13
15

L_I/O(2)

17

L_I/O(3)

19

L_I/O(4)
L_I/O(5)
L_I/O(6)

21

L_I/O(7)

27

L_A(O)

29

L_A(l)
L_A(2)
L_A(3)

31

23
25

33
35

L_A(4)
L_A(5)

37
39

L_A(6)

41

L_A(7)
L_A(8)

43
45
47

L_A(9)
L_A(10)

49
51

L_A(11)
L_A(12)
L_A(13)

53

L_A(14)
L_A(15)

57
59

L_A(16)

61

GND

63

55

GND
R351:
R_RIW
R_8m"
R_~

10
12

R_I/O(O)

14

R_I/O(1)

16

R_I/O(2)

18

R_I/O(3)

20
22

R_I/O(4)

24
26

R_1I0(5)
R_I/O(6)
R_I/O(7)

28

R_A(O)

30

R_A(1)
R_A(2)

32
36
38

R_A(3)
R_A(4)
R_A(5)

40

R_A(6)

42
44

R_A(7)

46
48

GND

50
52

R_A(10)
R_A(11)

54

R_A(12)

56
58

R_A(13)
R_A(14)

60

R_A(15)

34

PIN NAMES
Left Port

LA (0-16)
L VO (0-7)
L RIW
LCS
L OE
L SEM

Right Port
R A (0-16)
R VO(0-7)
R RIW
R CS
ROE
R SEM

Vcc
GND

Description
Address Inputs
Data InputslOutputs
ReadlWrite Enables
Chip Select
Ou~ut Enable
Semaphore Control
Power
Ground

R_A(8)
R_A(9)

62

R_A(16)

64

vee

SIMM

TOP VIEW
CEMOS Is a lrademark of Inlogra1ed Device Technology. Inc.

JUNE 1991

COMMERCIAL TEMPERATURE RANGE

DSC-711851·

01991 Inlogra1ed DevIce Technology. Inc.

UPDATE1 B

226

G·

256K x 16
CMOS. STATIC RAM MODULE

IDT7MP4046

Integrated. DevIce Tedmolo&y; Inc.

FEATURES:

DESCRIPTION:

• High-speed 4 megabit CMOS static RAM module
• Fast access time: 70ns (max.)
• Low power consumption .
- Active: 220mA max.
- CMOS Standby: 4501JA max.
- Data retention: 2501JA max. (Vcc= 2V)
• Surface mounted small outline plastic packages on a 45
pin FR-4 SIP (Single In-line Package)
• Single 5V (±1 0%) power supply
• MuHiple GND pins and decoupling capacitors lor maximum noise immunity
• Inputs/outputs directly TTL compatible

The IDT7M P4046 is a 256K x 16 CMOS static RAM modu Ie
constructed on a muHilayer epoxy laminate (FR-4) substrate
using 4128K x 8 static RAMs in small oulline plastic packages
and a one-ol-four decoder. Availability of two Write Enables
and two Output Enables provides byte access and output
control flexibility. The IDT7MP4046 is available with access
times as fast as 70ns with a maximum operating current 01
220mA. For battery backup applications, there is a very low
data retention current.
The IDT7MP4046 is packaged in a45 pin FR-4 SIP (Single
In-line Package). This results is a package 4.5 inches in
length and 0.14 inches in thickness.
All inputs and outputs olthe IDT7MP4046 are TTL compatible and operate from a single 5V supply. Full asynchronous
circuitry requires no clocks or refresh lor operation and provides equal access and cycle times for ease 01 use.

FUNCTIONAL BLOCK DIAGRAM

WEo OEo

AO-17

WEl OEl

18

256Kx 16

RAM

cs-

1/00-7

1/08-15
2832 drwOl

CEMOS Is a trademark oIlnteg'Bled Device Technology. Inc.

MAY 1991

COMMERCIAL TEMPERATURE RANGE
CI991 Integrated Devlco Technology. Inc.

DSC-7086/-

UPDATEi B

227

IDT7MP4046
256K x 16 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION(1, 2)

PIN NAMES

r----...,----,
GND

Vee
WEl
OEl
1/015

1100-11015

Data Inputs/Outputs

Ao-A17

Addresses

CS

"Chip Select

WEo-l
OEo-l

11014
11013
11012

11011

Write Enables
Output Enables

Vcc

Power

GND

Ground
28321b1 01

1/010
I/Os

I/0s'
AD

ABSOLUTE MAXIMUM RATINGS(1)

Al

A2

Symbol

A3
A4

\/TERM

As
A6
A7
A17

OS"
GND

Rating

Commercial

Terminal Vokage with
Respect to GND

Unit

-0.5 to +7.0
,

V

.

TA

Operating Temperature

Oto+70

·C

TBIAS

Temperature Under Bias

-10to+85

·C

TSTG

Storage Temperature

-55 to +125

·C

lOUT

DC Output Current

50

mA

NOTE:
28321b103
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause pennanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification Is not Implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

A17
A16

A15
A14
A13

A12
All
AID

As
As
1/07
1/06
1/05
1/04
1/03
1/02
1/01
1/00
OEO

CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
Symbol

Conditions

Typ.

Unit

CIN(A)

Input Capacitance
(Address)

Parameter

VIN=OV

30

pF

CIN(D)

Input Capacitance
(Data, WE, OE)

VIN=OV

15

pF

VIN = OV

8

pF

VOUT= OV

20

CIN(C)

Input Capacitance(CS)

COUT

Output Capacitance

NOTE:
1. This parameter is guaranteed by design, but not tested.

WEo
Vee

pF
2832 11>104

GND
SIP
2832 drw 02
FRONT VIEW

NOTES:
1. For module dimensions, please refer to the module drawings in the
packaging section.
2. Pins 21 and 24 must be tied together.

RECOMMENDED DC OPERATING
CONDITIONS
Symbol

Parameter

Min.

Typ.

Vcc

Supply Vokage

4.5

5

5.5

V

GND

Supply Vokage

0

0

0

V

VIH

Input High Voltage

6

V

VIL

Input Low Vokage

-

2.2
-0.5(1)

NOTE:
1. VIL = ·3.0V for pulse width less than 20ns.

UPDATE1 B

Max. Unit

0.8

V
2832 11>105

228

IDT7MP4046
256K x 16 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TRUTH TABLE
Mode

~

WE

Output

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE

Power

Standby

H

X

HighZ

Standby

Read

L

H

DATAour

Active

Write

L

L

HighZ

Active

Grade

Ambient
Temperature

GND

Vee

Commercial

O·Cto +70·C

OV

5.0V± 10"10
2832!b1 06

2B32!b1 02

DC ELECTRICAL CHARACTERISTICS
(VCC =5.0V ± 10%, TA =O°C to +70°C)
Parameter
Symbol

Test Conditions
Vee = Max., VIN

=GND to Vee

Unit

-

Max.
4
4

V

Min.

Ilul

Input Leakage

IILol

Output Leakage

Vee = Max.
CS = VIH, Vour = GND to Vee

VOL

Output Low Vo~age

Vee = Min., IOL =2mA

-

0.4

VOH

Output High Voltage

Vee = Min., IOH = -lmA

2.4

-

V

Icc

Dynamic Operating Current

Vee = Max., CS = VIL,
I =lMAX, Output Open

-

220

rnA

IS9

Standby Supply Current
(TTL Levels)

CS 2: VIH, Vee = Max.,
I =lMAX, Ouput Open

-

12

rnA

IS91

Full Standby Supply Current
(CMOS Levels)

CS 2: VHe, VIN 2: VHe or ~ VLe
Vee = Max., Output Open

-

450

J.lA

'"

J.LA
J.lA

28321b1 07

DATA RETENTION CHARACTERISTICS (1)

.

(TA = O°C to +70°C)
Symbol

' Parameter

Test Condition

Mln_

Max_
cc@2.0V

-

2.0

-

V

-

250

J.lA
ns

VOR

Vee lor Data Retention

ICCOR

Data.Retention.Current

CS 2: Vee - 0.2V

teoR(~)

Chip Deselect to Data Retention Time

VIN ~ Vee - 0.2V

tR(~)

Operation Recovery Time

VIN 2: - O.2V

0
tRe'''! .

NOTES:

-

Unit

ns
2B32!b110

1. Vcc =2V, TA = +25·C.
2. tRC = Read Cycle TIme.
3. This parameter is guaranteed by design, but not tested.

DATA RETENTION WAVEFORM

DATA
RETENTION
MODE
VOR2:2V
VOR
2832drw 04

UPDATE18

229

IDT7MP4D46
256K x 16 CMOS STATIC RAM MODULE

COMMERQAL TEMPERATURE RANGE

AC·TEST CONDITIONS
Input Pulse Levels

GNDto 3.0V

Input RiselFall Times

5ns

InpUt Timing Reference Lev.els

1.5V

OutpUt Reference Levels.
Output Load

1.5V
See Figures 1 and 2
2832 IbI 08

5V

5V

480n

480n
DATAoUT-~-~

DATAoUT-.......- - i
255n

30pP

5pP

255n

2832drw03

Figure 1. Output Load

Figure 2. Output !.qad
(for tCLl, tOll, ICHl, tOHZ, tow, and twHZ)

"Including scope and jig

AC ELECTRICAL CHARACTE~ISTIC$
(Vee - 5 OV ± 10%,TA - O°C to +70°C)

-

Symbol

Parameters

Min.

7MP4046LxxS
-85
-100
I

I

-70

Max.

1

I

-120

Max. 1 Min.

Min.

Max.

Min.

-

85

-

100

-

70

-

85

-

100

-

48

-

33

-

Max.

Unit

READ CYCLE
tRC

tAA

Read Cycle Time
. Address Access Time

70

-

tACS

Chip .Select Access Time

-

.70

tOE

Oulput Enable to Output Valid

-

·45

toHil)

Output Disable to Output in High Z

-

30

..

85

100
50
35

120

-

-

ns

120

ns

120

ns

60

ns

40

.ns

tOll(l)

Output Enable to Output in Low Z

0

-

-

0

-

ns

Chip Select to Output in LowZ

5

-

5:

-

0

tCtz twHZ + tow) to allow the I/O drivers to !Urn off and dala to be placed on the bus for the required
two. If ~ is high during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twP.

UPDATE1B

232

IDT7MP4046
256K x 16 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
lOT

xxxx

x

xx

X

x

Device
Type

Power

Speed

Package

Process/
Temperature
Range

Commercial (O°C to +70°C)
L----------~S

L-_______________

1 70

~85

FR-4 SIP (Single !n-line vertical Package)

}

Speed in Nanoseconds

100
1 120
L-----------------------------~L

Low Power

' - - - - - - - - ' - - - - - - - - - - - - - - - - - - - j 7MP4046 256K x 16 CMOS Static RAM Module
2832drw 10

UPDATE1 B

233

e;;"

256KB/1MB/4MB
IDT79R4000 SECONDARY CACHE
MODULE BLOCK FAMILY

PRELIMINARY
IDT7MP6074
IDT7MP6084
IDT7MP6094

IDtepa1ed DevIce Tecbnolol)'. Inc:.

FEATURES:

DESCRIPTION:

• High-speed BiCEMOSTM/CEMOSTM secondary cache
module block constructed to support the IDT79R4000
CPU
• Available as a pin compatible family to build 256 kilobyte, 1 megabyte and 4 megabyte secondary caches
• Zero wait-state operation
• Four word line size
• Operating frequencies to support 50MHz and 75MHz
IDT79R4000
• Available as a set of four identical high density 80 lead
(gold-plated fingers) SIMMs (Single In-Line Memory
Modules)
• Surface mounted plastic components on a multilayer
epoxy laminate (FR~4) substrate
• Multiple ground pins and decoupling capacitors for
maximum noise immunity
• TIL compatible II0s
• Single 5V (±10%) power supply

The IDT7MP6074 is a 256 kilobyte IDT79R4000 secondary cache module, block constructed on a multilayer epoxy
laminate substrate (FR-4), using 11 16K x 4 static RAMs and
2 IDT74FBT2827 di'ivers. The IDT7MP6084 is a 1 megabyte
1DT79R4000 secondary cache module block using 11 64K x
4 static RAMs, and the IDT7MP6094 is a 4 megabyte
IDT79R4000 secondary cache module block using 11 256K x
4 static RAMs. The IDT74FBT2827 has intemal250 series
resistors and BiCEMOSTM II0s resulting in the fastest propagation times with minimal overshoot and ringing. Four identical cache module blocks comprise a full secondary cache.
The IDT7MP6074/84/94 support use in an IDT79R4000based system at speeds of 50MHz and 75M Hz with zero waitstate operation. Module supports a four word line size. For
other line sizes, please consult factory.
All inputs and outputs of the IDT7MP6074/84/94 are TTLcompatible and operate from a single 5V supply. Fully
asynchronous circuitry is used, requiring no clocks or refresh
for operation.

FUNCTIONAL BLOCK DIAGRAM

Al·17
OE
TCS

,

17.1'

..
..
~

74FBT2827
x2

DCS

-

~

hJ

WE

..
~

Al·17
OE

256Kx36
DATA

CS
hJ

WE

......
.

...
~

AH7
OE
CS

256Kx8
TAG

kJ

WE
j

36

~

II

1/00-35

,

811
1

To-7

drwOl

BICEMOS and CEMOS are trademarks of Integrated Oevice Technology Inc.

MAY 1991

COMMERCIAL TEMPERATURE RANGE
01991 ln1egrated Oevk:e Technology. Inc.

DSC-7087/-

UPDATE1 B

234

IDT7MP6074184194 (256KBJ1MB/4MB)
IDT79R4000 SECONDARY CACHE MODULE BLOCK

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION(1,2)
GND

1/00
1/02
1/04
1/06
1/07
I/0e
1/011
1/013
GND

11016
1/018
1/020
1/022
Vee

11024
1/026
1/028
GND

11031
1/033
1/035

WE
A1

A3
As
GND
DCS

A7
Ae
A11

A12
A14
A1S
TCS
GND
T2
T4
Ts
Vee

1
3
5
7
9
11
13
15

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75

77
79

PIN NAMES

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80

Vee

1/01
1/03
1/05
GND

1/08
1/010

1100-35

Data InputslOutputs

To-7

Tag Inputs/Outputs

Ao-17

Address Inputs

DCS

Data Chip Select

TCS

Tag Chip Select

WE

Write Enable

11012

OE

Output Enable

1/014
1/015
1/017
1/019
1/021

Vee

Power Supply

GND

Ground
IblOl

GND

1/023
1/025
1/027
1/029
1/030
1/032

CAPACITANCE
Symbol

1/034
GND
Ao
A2
A4
As
Vee

Parameter 1)

Conditions

Max.

Unit

CIN(O)

Input Capacitance (Data)

VIN = OV

10

pF

CIN(A)

Input Capacitance
(A1-1S, OE, TCS, DCS)

VIN = OV

10

pF

CIN(B)

Input Capacitance
(Ao, WE)

VIN= OV

100

pF

GoUT

Output Capacitance

VOUT=OV

10

pF

NOlI::
1. This parameter is guaranteed by design. but not tested.

Ibl03

DE
RECOMMENDED DC OPERATING CONDITIONS

As
A10
GND
A13
A1s

Symbol

A17
To
T1
T3
Ts
T7
GND

Min.

Typ.

Max.

Unit

Vee

Supply Voltage

Parameter

4.5

5

5.5

V

GND

Supply Vo~age

0

0

0

V

VIH

Input High Voltage

2.2

-

6

V

Vil

Input Low Vo~age

-0.5(1)

-

0.8

V

NOTE:
1. VIL = -1.5V for pulse width less than 10ns.

Ibl04

dlW02

SIMM
TOP VIEW

ABSOLUTE MAXIMUM RATINGS

NOTES:
1. For the IDT7MP6084 (1 MB version). pins 67 and 68 are no connects for
proper operation of the module.. For the IDT7MP6074 (256KB version).
pins 65. 66. 67 and 68 are no connects for proper operation of the module.
2: For package dimensions, please refer to the module drawings in the
packaging section.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial

Ambient
Temperature

GND

Vce

0·Cto+70·C

OV

5V±1O%

Rating(1)

Value

Unit

VTERM

Terminal Vokage with Respect
toGND

-0.5 to +7.0

V

TA

Operating Temperature

TBIAS

Temperature Under Bias

Symbol

TSTG

Storage Temperature

loUT

DC Output Current

.0 to +70

·C

-10 to +85

·C

-55 to +125

·C

50

mA

NOTE:
tbl02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

!bIOS

UPDATE1 B

235

IDT7MP6074/84194 (256KB/1 MB/4MB)
IDT79R4000 SECONDARY CACHE MODULE BLOCK

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS
(Vee = 5V ± 10%, TA =

O°C to +70°C)
50MHz

. Symbol

Parameter

Ilull

Input leakage (except Ao, WE)

IIu21

Input Leakage (AD, WE)

IILOI

Output Leakage

lee

Operating Current

VOH

Output High Voltage

VOL

Output Low VoHage

=GND to Vee
Vee = Max., VIN =GND to Vee
Vee = Max., CS =VIH, VOUT =GND to Vee
CS = VIL; Vee = Max., Outputs Open
Vee = Min., IOH = -4mA
Vee = Min., IOL = 8mA
Vee c Max., VIN

AC TEST CONDITIONS

75MHz

Max.

Min.

Max.

Unit

-

10

-

10

-

110

110

-

10

-

10

I1A
I1A
I1A

2200

-

TBD

rnA

Min.

Test Conditions

2.4

-

2.4

-

V

-

0.4

-

0.4

V

+5V

+5V

Input Pulse Levels

GNDt03.0V

Input RiselFall Times

5ns

Input Timing Reference Levels

1.5V

Output Reference Levels

480n
DATA OUT

1.5V

Output Load

See Figures 1 and 2

480n
DATAOUT-.......-

30pF*

255n

...

255n

!bIOS

Figure 1. Output Load

Rgure 2. Output Load
(for tOll and tOHZ)

* Including scope and jig.

AC ELECTRICAL CHARACTERISTICS
(Vee =5V + 10%, TA =O°C to +70°C)
7MP6074S50
7MP6084S50
7MP6094S50
Symbol

Min.

Parameter

7MP6074S75
7MP6084S75
7MP6094S75

Max.

Min.

Max.

Unit

25

-

15

ns

15

ns

13

ns

READ CYCLE

1M

Address Access Time

tOE

Output Enable to Output Valid

tOHt 1)

Output Disable to Output in High Z

tou,l)

Output Enable to Output in Low Z

0'

25

-

20

-

-

0

-

ns
ns

WRITE CYCLE

tAW

Address Valid to.End

25

-

15

-

twp

Write Pulse Width

20

10

-

ns

tow

Data Valid to End of Write

17

-

8

ns

Data Hold Time

0

-

o.

-

. tOH

Of Write

NOTE: ...
1. This parameter is guaranteed by design but not tested.

ns
tbiOS

UPDATE1 B

236

IDT7MP6074184194 (256KBl1 MB/4MB)
IDT79R4000 SECONDARY CACHE MODULE BLOCK

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE(1)

ADDRVALID

ADDR _ _ _ _,

14-------tAA----~

DATAOUT - - - - - - - - - - - - " - - - ( :

dlW04

NOTES:
1. This parameter is· guaranteed by design. but not tested.

TIMING WAVEFORM OF WRITE CYCLE

ADDR

)~

•
WE

DATA IN

AD DR VALID
"tAW

'"

twp

/

I,.
I'

UPDATE1 B

tow

..ItOH

DATA VALID
drw05

237

IDT7MP6074184194 (256KB/1 MB/4MB)
IDT79R4000 SECONDARY CACHE MODULE BLOCK

COMMERCIAL TEMPERATURE RANGE
drw07

ORDERING INFORMATION
lOT XXXX
Device
Type

X

XXX

X

x

Power

Speed

Package

Processl
Temperature
Range
.

.

-----ll

1-1

~------------~

Blank

Commercial (O°C to +70°C)

M

FR-4 SIMM (Single In-line Memory Module)

~________~______~150

175

~--------------------------~

~

________________________________

50MHz }
75MHz

Speed in MegaHertz

S

Standard Power

7MP6074

256KB IDT79R4000 Secondary Cache
Module Block
1MB IDT79R4000 Secondary Cache
Module Block
4MB IDT79R4000 Secondary Cache
Module Block

~7MP60~

7MP6094

drwOO

UPDATE1 B

238

PRELIMINARY
IDT7MP6085
IDT7MP6087

1281

WEI
11610
11012
11014
11016
GND
CS2
0E2
AI
A3
A5
A7

GND
Vee
ClK

As
All
.A13
Vee
CS3
OEl
110 IS
11020
11022
11024
11026
GND
11027
11029
11031
1/033
11035
GND

1
3
5
7
9
11
13
15
17

19
21
23
25
27
29
31
33
35
37
39
41
43
45
47.
49
51
53
55
51"
59
61
63
65
67
69
71
73
75
77
79

ABSOLUTE MAXIMUM RATINGS
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

GND
1100
1/02
1104.
li06
IlOs
GND
1109
11011
It013
11016
11017
CSo

,\2

GND
As
Ala
A12
A14
CSI
OEI
GND
11019
11021
11023
11025
WE2
WE:!
11028
11030
11032
11034
Vee
GND

44
46
48
50
52
54

56
58
60
62
64
66
68
70
72
74
76
78
80

Symbol
VTERM
TA
TSIAS
TSTG
lOUT

Rating
Terminal Voltage with Respect
toGND
Operating Temperature
Temperature Under Bias
Storage Temperature

Value
-0.5 to +7.0

Unit
V

o to +7'0
-10to+85
-55 to +125

DC
DC
DC

50

rnA

DC Output Current

NOTE:
28341b103
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification' is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliabilty.

CEo
AD

A2
A4
As

ADS
Vee

SIMM
TOP VIEW

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient Temperature
28341b104

RECOMMENDED DC
OPERATING CONDITIONS
Symbol
Vee
GND
2834

drwD2

NOTES:
1. For the IDT7MP6085 (128K byte) version, pins'27, 29,53,55 are no
connects.
2. For module dimensions, please refer to the module drawings in the
packaging section.

VIH
VIL

Parameter
Supply VoHage
Supply Voltage
Input High Votage
Input low Voltage

Min.
4.5
0
2.2
-0.5(')

Typ.
5.0
0

-

Max.
5.5
0.0
6.0
0.8

NOTE:
1. VIL = -3.0V for pu,lse width less than 5ns.

Unit
V
V
V
V
2834 tbl 05

CAPACITANCE(1)
(TA = +25°C, f = 1.0 MHz)
Symbol

PIN NAMES

CIN

Ao-A14
1100-11035
CSa-3

Address Inputs
Data Input/Output
Word Chip Select/Count Enable

WEo-3
OEo-3
ADS
ClK
GND

Byte Write Enables
Word Output Enables
Address Status
System Clock
Ground
Power

Vee

CIN
CVO

Max.

Unit

Input Capacitance
(CS,OE,VVE)
Input Capacitance
(Address, ClK, ADS

Parameter')

VIN = OV

20

pF

VIN = OV

70(2)

pF

110 Capacitance

VOUT= OV

20(3)

pF

Condition

NOTE:
28341b109
. 1, This parameter is determined by device characterization but is not production tested and applies to both the IDT7MP6085 and IDT7MP6067 unless
otherwise noted.
2. Specification for.IDT7MP6065 is 42 pF.
3. Specification for IDT7MP6085 is 13pF.
28341bIOl

UPDATE1 B

240

IDT7MP6085J IDT7MP6087 (128K1256K BYTE)
CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

COMME;RCIAL TEMPERATURE RANGE

TRUTH TABLE(1)
ClK

Prevlous~

l'
l'
l'
l'
l'
l'
l'

H

-

-

l'
l'

-

X
L
X

~
L
H

-

X
H

L

X

X

H

L

Address
Valid Input

-

-

X

.H

L

X

-

-

-

~

X

X

-

-

-

H
H

-

-

-

L
L

H
L
L
L

OE

-

-

-

-

X

-

WE

L
L
L

I/O

Function
Preset Address Counter
Ignore External Address Pins

-

-

-

-

H
L
H
H
L

Hi-Z
DATAoUT
DATAIN
DATAIN

-

Ignore External Address Pins
Sequence Address Counter
Sequence Address Counter
Suspend Address Sequencing
Suspend Address Sequencing
Outputs Disabled
Read
Write
Write
Not Allowed

NOTE:
1. H = HIGH, L = LOW, X = Don't Care, "-" = Unrelated, Hi-Z = High Impedance.

283411>111

DC ELECTRICAL CHARAcTERISTICS
=S.OV ± 10%, TA = O°C to 70°C)

(VCC

Symbol

Test Condition
Vee = 5.5V, VIN = OV to Vee

Min.

MaX.!I,

Unit

-

SOI2I

!LA

Vee = 5.5V, VIN = OV to Vee

-

20

!LA

Vee =5.5V, VIN

-

20(3)

!LA

-

20(3)

-

!LA

0.4

V
V

Illol
VOL

Parameter
Input Leakage Current
(Address, CLK, ADS)
Input Leakage Current
(CS,OE)
Input Leakage Current
(Data, WE)
Output Leakage Current
Output Low Voltage

CS =VIH, VOUT = OV to Vee. Vee
Iol = SmA, Vee = Min.

VOH

Output High Voltage

IoH

IILII
Ilul
Ilul

= OV to Vee
= Max.

=-4mA, Vee = Min.

-

2.4

NOTES:
1. Specifications apply to both the IDT7MP6085 and IDT7MP6087 unless otherwise noted.
2. Specification for IDT7MP6085 is 4OflA.
3. Specification for IDT7MP6085 is 10flA.

DC ELECTRICAL CHARACTERISTICS(1)
(Vee = S.OV ± 10%, TA = O°C to 70°C)

Symbol

Parameter

Test Condition

Iccl

Operating Power
Supply Current

CSSVIL
Outputs Open
Vee = Max., f =0(2)

1cc2

Dynamic Operating
Current

C~S VIL
Outputs Open
Vee = Max., f =IMAXI2l

IDT7MP6085
50MHzI1 1 25,33,40MHz

1050

520

960

IDT7MP6087
50MHzI 11 25,33,40MHz Unit

-

1040

rnA

2100

1920

rnA

NOTES:
I.Preliminal}' specification only.
2. All =!MAX, address and data inputs are cycling at the maximum frequency of read cycles of 1ItRC. f =0 means no inpullines change.

UPDATE1 B

283411>1111

241

IDT7MP6085/IDT7MP6087 (128K1256K BYTE)
CMOS SECONDARYCACH.E MODULE FOR THE INTEL 1486

COMMERCIAL TEMPERATURE RANGE

·0'

FUNCTIONAL DESCRIPTION
The IDT7MP6085 and the IDT7MP6087 are based on the
IDT71589 CacheRAM with internal edge-triggered registers
dedicated to support the Intel i486 CPU. These registers
support the fastest system designs and allow a 128K byte or
larger cache to be designed to consume the smallest number
of chips, the lowest power and board space, and allow the
designer to avoid the Lise of expensive high-speed cache-tag
RAMs and PLDs.
The internal registers are designed to support two high
speed functions: Burst read cycles and a late-abort self-timed
write cycle.
Burst read. cycles are accomplished through the assertion
of the ADS signal with a valid address input during the rising
edge ofthe clock input. This address will be used to access the
data in the Cache RAM module during the next clock cycle,
and data will be output during the following three cycles in
accordance with the i486's burst refill sequence (Le., during
the next cycle the address LSB is inverted, then the second
LSB is inverted as the LSB is restored to its original value,
etc.). Since the Cache RAM contains this counter internally,
the critical clock-to-data time of even the fastest CPU speeds
can be met by using a slower RAM module speed grade
without resorting to chip-intensive interleaving schemes.
Should the ADS signal be sampled as valid after having been
sampled as inv~lid; any bursting in process will be reinitialized
to the new address, and a new burst cycle will be started. The

burst counter wraps around at the end the sequence and
continues to count until stopped by the ADS or CS inputs. A
fast copy-back scheme can harness this capability by reading,
then writing the four burst addresses within a single bllrst
cycle.
The self-timed write cycle significantly eases the timing of
the address and data inputs during a write cycle, and allows
the write/don't write decision to be postponed until the very
end of the second cycle of a write cycle. During a write cycle,
the address will be strobed into the address registerduririg the
first rising edge of the clock after the ADS input becomes valid.
Data is sampled into the data input register during the next
cycle's riSing edge, as is the write enable input. If a write has
been enabled the data will be written from the address and
input data registers into the Cache RAM module during the
second (low) phase of the clock of that cycle.
A chip select pin is provided to give control over interruption
of write cycles and burst read cycles. When the CS input is
used to interrupt a burst cycle, it operates as a synchronous
input to the burst counter. A low level must be present on the
chip select input and must satisfy data set-up and hold times
in orderforthe counterto progress to its next state. To stop the
counter at its cu rrent state, the chip select input must be taken
high, and must stay high long enough to satisfy the CacheRAM
module's data set-up and hold times. The CS pin also is used
as an auxiliary to the WE inputs. Writes can only be
accomplished if both CS and WE are simultaneously sampled
active.
.

AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V
5ns.

1.5V
1.5V
See Figures 1& 2
2834tbi 08

+5V

+5V

480n

480n

DATAOUT --+---4
255n

DATAOUT --+--...
50pF'

255n

5pF'

2834 drw03

Figure 1. Output Load

2834 drw04

Figure 1. Output Load
(for tOHZ, tcHZ, tOLZ and tell)

'including scope and jig

UPDATE1 B

242

IDT7MP60851IDT7MP6087 (128K1 256K BYTE)
CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS
(Vcc =5 OV + 10%, TA

-

= 0° to +70°C)
50MHz(1)

Symbol

Name

Min.

Max.

-

40MHz

33MHz

Min.

Max.

Min.

25

-

30

10

-

11

25MHz

Max.

5

-

1

-

1
2

3

-

3

-

14

-

19

-

24

3

-

4

4

-

7

-

-

-

tOll

Output Enable to Output Valid
Output Enable to Output in la·Z(2,3)

8

2

-

2

tOHZ

Output Disable to Output in Hi-lt2,3)

-

8

-

tCYC

Clock Cycle TIme

20

tCH

Clock Pulse High

tCl

Clock Pulse Low

8
8

t51

Set·up Time (ADS, WE, CS)

4

t52

Set·up Time (Address, Input Data)

5

tH1

Hold TIme (CS.!. Input Data)

1

tH2

Hold TIme (Cst, WE, Address)

2

-

IAD5H

Hold TIme (ADS)

:3

-

tCD

Clock to Data Valid

-

toe

Data Valid After Clock

tOE

2

7

10
4

2

-

11
4
5

9

9

Min. Max.
40
14
14
5

6
1
2

-

-

Unit
ns
ns
ns
ns
ns
ns
ns

-

ns

34

ns

-

ns

10

ns

2

-

ns

-

10

3

5

-

NOTES:

ns
283411>110

1. Preliminary specifications only.
2. Transition is measured ±200mV from low or high impedance voltage with load (See AC Test Conditions, Fjgure 2).
3. This parameter is guaranteed by design but not tested.

TIMING WAVEFORM OF BURST READ CYCLE

CLK

ADDRESS

----------I
~--~'I~------+---------+---------+---------+---------

WE ______________+_-----JI

CS ______________+_-----J

DATA----------------~~'y)(y
NOTES:

m

1. If
goes low during a burst cycle, a new address will be loaded and another burst cycle will be started.
2. If CS is taken inactive during a burst read cycle, the burst counter will discontinue counting until CS input again goes active. The timing of the CS input
for this control of the burst counter must satisfy setup and hold parameters IS and IH.
3. A·Data from input address
B-Data from input address except Ao is now AD.
C·Data from input address except A1 is now A1.
D-Data from input address except AD and A1 are now AD and A1.
UPDATE1 B

243

IDT7MP6085/ IDT7MP6087 (128K1256K BYTE)
CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE
t--

elK

ICYC--

--.J~

\IS--IH~
.

.

1.

__ IS

\

...
-to

IH

r.:.

I----.X

ADDRESS

LJ~~~rL
.... Is ~
IH ,...

....

I-

I'-"

(2)

~U

~

DATAIN

'I
IOHZ(l)

DATAoUT

'(
~
~

HIGH-Z

IOLZ

r.:.
'I
1\
2B34 drw 06

NOTES:
1. DE Must be taken inactive at least as long as 10HZ + ts before Ihe second rising clock edge of write cycle.
2. ~ timing is Ihe same as any synchronous signal when used to block writes or to stop the burst count sequence.

UPDATE1 B

244

IDT7MP6085/IDT7MP6087 (128K1 256K BYTE)
CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF BURST WRITE CYCLE

elK

ADDRESS

DATAIN - - - - - - - - - - - - { ,

HIGH-Z

DATAOUT ___________~

2834 drw07

NOTES:
1. ~ Must be taken inactive at least as long as tOHZ + ts before the second rising clock edge of write cycle.
2. A-Data to be written to original input address.
B-Data to be written to original input address except Ao is now Ao.
C-Data to be written to original input address except A1 is now A1.
D-Data to be written to original input address except Ao and A1 are now Ao and A1.
3. If Al5S goes low during a burst cycle, a new address will be loaded, and another burst cycle will be started.
4. Ifes is taken inactive during a burst write cycle the burst counter will discontinue counting until the CS input again goes active. The timing of the CS input
for this control of the burst counter must satisfy setup and hold parameters ts and tHo CS timing is the same as any synchronous signal when used to block
writes or to stop the burst count sequence.

UPDATE1 B

245

III
:

IDT7MP60851IDT7MP6087 (128K1256K BYTE)
CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

COMMERCiAL TEMPERATURE RANGE

ORDERING INFORMATION
lOT

XXXXX

A

999

A

A

Device
Type

'Power

Speed

Package

Process!
Temperature

.Rarge

I

~Blank

Commercial (cl·C to +70·C)

FR-4 SIMM (Single In-Line Memory Module)

M
25
'---'-----'----'--'-'----1

'--.,....,..,..,.---~---.,-~--~---_l

'---------------------1

33
40
50
S "

}

7MP6085
7MP6087

Speed In Megahertz
Standard Power
128K Byte 1486 Cache Module
256K Byte i486 Cache Module

2834 drw 11

UPDATE1 B

246

t;J

128K BYTE CMOS
SECONDARY CACHE MODULE
FOR THE INTELTM i486™

PRELIMINARY
IDT7MP6086

Integrated DevIce Technology. Inc.

FEATURES:
• 128K byte direct mapped secondary cache module
• Uses the 1DT71589 32K x 9 CacheRAMTM with burst
counter and self-timed write
• Matches all timing and Signals of the i486 processor
• Operates with i486 speeds of up to 50MHz
• 72 lead FR-4 SIMM (Single-in-Line Memory Module)
• Single 5V (±100/0) power supply
• Multiple GNO pins and decoupling capacitors for maximum noise immunity
• Inputs/outputs directly TTL compatible

DESCRIPTION:
The I0T7MP6086, a 128K byte direct mapped secondary
cache module, uses 4 IOT71589 32K x 9 CacheRAMs in
plastic surface mount packages mounted on ,a multilayer
epoxy laminate (FR-4) substrate with gold-plated leads. Extremely high speeds are achieved using lOT's high performance, high reliability CEMOSTM technology. This module is
designed to facilitate the implementation of the

highest performance secondary caches for the i486 architecture while using low speed logic devices and consuming the
minimum board space.
The IOT7M P6086 data RAMs contain a full set of write data
and address registers. These registers are combined with the
internal write abort logic to allow the processor to generate a
self-timed write based upon a decision which can be left until
the end of the write cycle.
,
An internal burst address counter accepts the first cycle
address from the processor and then cycles through the
adjacent four locations using the i486's burst refill sequence
on appropriate rising edges of the system clock.
Three program identification pins are provided so that the
system can uniquely identify the I0T7MP6086.
Note that individual parity bits are grouped with their
respective bytes, not all at the end.
The SIMM package configuration allows 72 leads to be
placed on a package 4.25 inches long, 0.55 inches tall and
0.25 inches thick. The I0T7MP6086 is available to interface
with a 50M Hz i486. All inputs and outputs of the IOT7M P6086
are TTL compatible and operate from a single 5V power
supply.

FUNCTIONAL BLOCK DIAGRAM
A14

ADDRESS
REGISTER
lSB
BURST
CONTROL

Ao

1/00-1/03

WE
OE
CS
ClK
ADS

32K x 36
MEMORY
ARRAY

36

BURST &
WRITE
TIMING
CONTROL
36

dIW01

CEMOS and CacheRAM are trademarks of Integrated Device Technology, Inc.
Intel and 1486 are trademarks of Intel Corp.

MAY 1991

COMMERCIAL TEMPERATURE RANGE
C1991 Integrated OeviceTechnology. Inc.

DSC·7D89/·

UPDATE1 B

247

IDT7MP6086
128K BYTE CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

PIN CONFIGURATION(I,2)
GNO
1/00
1/02
1104
110s
II0a
WEl
1/010
GNO
1/013
1/015
1/017
Al
A3
As
A7
ADS
Vee

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36

CS
A9
Al1
A13
1/018
1/020
1/022
11024
1/026

38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

WE2
1/027
1/029
1/031
1/033
1/035
POl
Vee
GND

COMMERCIAL TEMPERATURE RANGE

CAPACITANCE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35

GNO

37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

GND
OE
Al0
A12
A14
1/019
1/021'
1/023
1/025
GND
WE3
1/028
1/030
1/032
1/034
PDO
P02
GNO

(TA = +25°C, f =1.0 MHz)

Vee
1101
1/03
1/05
1/07
WEO
1/09
1/011
1/012
1/014
11016
Ao
A2
A4
A6
Aa
ClK

Symbol
CIN
CIN
cvo

Parameter')
Condition
Input Capacitance VIN = OV
(Data)
Input Capacitance VIN = OV
(Address & Control)
Output Capacitance Vour= OV

Max.
13

Unit
pF

42

pF

13

pF

NOTE:

tbl09

1. This parameter is guaranteed by design but not tested.

ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM
TA
TSIAS
TSTG,
,lOUT

Rating
Terminal Voltage with Respect
toGND
Operating Temperature
Temperature Under Bias
Storage Temperature
DC Output Current

"

Value
-0.5 to +7.0

Unit
V

Oto+70,
-:-10 to +85
55 to +125
50

·C
·C
·C
mA

NOTE.

tbl03

Stresses greater than ,those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device atthese or any other conditions above those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliabilty.

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient Temperature
O·Cto +70·C
,bl04

drw02

SIMM
TOP VIEW

NOTE:
1. For module dimensions, please referto the module drawings in the
packaging section.
2. Please consult the factory regarding program identification pins.

Symbol
Vee
GNO
VIH
VIL

PIN NAMES
Ao-A14
1/00-1/035
CS
WEO-3
OE
ADS
ClK
POO-2
GNO
Vcc

RECOMMENDED DC
OPERATING CONDITIONS

Address Inputs
Data Input/Output
Chip SelectlCount Enable
Byte Write Enables
Output Enable
Address Status
System Clock
Program Identification
Ground
Power

Parameter
Supply Vo~age
Supply Voltage
Input High Votage
Input Low Voltage

Min.
4.5
0
2.2
-0.5(')

NOTE:

Typ.
5.0
0

-

-

Max.
5.5
0.0
6.0
0.8

Unit
V
V
V
V
,biOS

1. VIL = --{3.0V for pulse width less than 5ns.

,blO'

OPDATE1 B

248

IDT7MP6086
128K BYTE CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

DC ELECTRICAL CHARACTERISTICS
Symbol
Ilul
Illll
Illol
VOL
VOH

Parameter
Input Leakage Current
(Address & Contol)
Input Leakage Current
(Data)
Output Leakage Current
Output Low Vo~age
Output High Voltage

COMMERCIAL TEMPERATURE RANGE

=5.0V ± 10%,TA =OOe TO + 70 e)

(VCC

0

Test Condition
Vee

Min.

Max.

Unit

-

40

(.LA

-

10
10
0.4

2.4

-

(.LA
(.LA
V
V

= 5.5V, V,N = ov to Vcc

Vcc = 5.5V, V,N = OV to Vee
CS = VIH, VOUT = OV to Vee. Vee = Max.
10l = smA, Vee = Min.
10H = -4mA, Vee = Min.

,biOS

DC ELECTRICAL CHARACTERISTICS

(Vee

= 5.0V ± 10%, TA = OOe to +70

0

e)

7MP6086xxM
(1)

Symbol
Parameter
lee,
Operating Power
Supply Current
lee2

50 MHz

Test Condition
CS= VIL
Outputs Open
Vee = Max., f = O('}

Dynamic Operating
Current

-

CS=VIL
OUlputs Open
Vee = Max., f = fMAX('}

1150

40 MHz

33 MHz

25 MHz

520

520

520

960

880

800

NOTES:

Un"

rnA

rnA
tbl07

1.Preliminary specification only.
2. At 1= fMAX, address and data inputs are cycling at the maximum Irequency 01 read cycles 01 1/tRC. 1= 0 means no input lines change.

AC TEST CONDITIONS
Input Pulse Levels
Input RiselFall Times
Input Timing Reference Levels
Output Reference Levels
Output Load

GNDto 3.0V
5ns
1.5V
1.5V
See Figures 1 & 2
TbI08

+5V

+5V
4800

4800
DATAouT-_-""
2550

DATAOUT-_-""
50pF'

2550

5pF'

drw04

drw03

Figure 1. Output Load
(for tOHZ, tCHZ, tOlZ and tCLl)

Figure 1. Output Load

'including scope and jig

UPDATE1 B

249

IDT7MP6086
128K BYTE CMOS SECONDARY CACHE MODULE FOR THE INTEL i486

COMMERCIAL TEMPERATURE RANGE

The IDT7MP6086 is an extremely fast 128K byte CMOS
static Cache RAM module with internal edge-triggered registers dedicated to the support of the Intel i486 CPU. These
registers support the fastest systems and allow a 128K byte
or larger cache to be designed to consume the smallest
number of chips, the lowest power and board space, and allow
the designerto avoid the use of expensive high-speed cachetag RAMs and PLDs.
The internal registers are designed to support two high
speed functions: Burst read cycles, and a late-abort self-timed
write cycle.
Burst read cycles are accomplished through the assertion
of the ADS signal with a valid address input during the rising
edge ofthe clock input. This address will be used to access the
data in the Cache RAM module during the next clock cycle,
and data will be output during the following three cycles in
accordance with the i486's burst refill sequence (i.e., during
the next cycle the address' LSB is inverted, then the second
LSB is inverted as the LSB is restored to its original value,
etc.). Since the Cache RAM contains this counter internally,
the critical clock-to-data time of even the fastest CPU speeds
can be met by using a slower RAM module speed grade
without resorting to chip-intensive interleaving schemes.
Should the ADS signal be sampled as valid after having been
sampled as invalid, any bursting in process will be reinitialized
to the new address, and a new burst cycle will be started. The

burst counter wraps around at the end of the sequence and
continues to count until stopped by the ADS or CS inputs. A
fast copy-back scheme can harness this capability by reading,
then writing the four burst addresses within a single burst
~d~.
.
The self-timed write cycle significantly eases the timing of
the address and data inputs during a write cycle,and allows
the write/don't write decision to be postponed until the very
end of the second cycle of a write cycle. During a write cycle,
the address will be strobed into the address register during the
first rising edge of the clock after the ADS input becomes valid.
Data is sampled into the data input register during the next
cycle's rising edge, as is the write enable input. If a write has
been enabled the data will be written from the address and
input data registers into the Cache RAM module during the
second (low) phase of the clock of that cycle.
A chip select pin is provided to give control over interruption
of write cycles and burst read cycles. When the CS input is
used to interrupt a burst cycle, it operates as a synchronous
input to the burstcounter. A low level must be presenton the
chip select input and must satisfy data set-up and hold times
in orderforthe counterto progress to its next state. To stop the
counter at its current state, the chip select input must be taken
high, and must stay high long enough to satisfy the CacheRAM
module's data set-up and hold times. The CSpin also is used
as an auxiliary to the WE inputs. Writes can only be
accomplished if both CS and WE are simultaneously sampled
active.

AC ELECTRICAL CHARACTERISTICS (Vee

± 10%, TA

FUNCTIONAL DESCRIPTION

= S.OV

= 0° to +70°C)

7MP6086xxM
Symbol
tCYC
tCH
tCl
tSI
tS2
tHI
tH2
IADSH
tCD
tDe
tOE
tOlZ
tOHZ

Name
Clock Cycle Time
Clock Pulse High
Clock Pulse Low
Set-up Time (ADS, WE, CS )
Set-up Time (Address, Input Data)
Hold Time (CSJ. Input Data)
Hold Time (Cst, WE, Address)
Hold Time (ADS)
Clock to Data Valid
Data Valid After Clock
Output Enable to Output Valid
Output Enable to Output in Lo-Z('·3)
Output Disable to Output in Hi-z<'·3)

50 MHzl')
Min. Max.
20
8
8

-

4
5
1
2
3

-

-

14

-

3

-

-

7

2

-

-

7

NOTES:
1. Preliminary specifications only.

40 MHz
Min. Max.
25
10
10
4
5
1
2
3
19
4

-

8

2
-

8

33 MHz
Min. Max.
30
11
11
4
5
1
2
3
24
4
9
2
9

25 MHz
Min. Max.
40
14
14
5
6

1
2
3

34

5

-

2

-

10

-

10

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tbl10

2. Transition is measured ±200mV from low or high impedance voltage with load (Figure 2).
3. This parameter is guaranteed, but not tested.

UPDATE1 B

250

IDT7MP6086
128K BYTE CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF BURST READ CYCLE

ClK

ADDRESS

CS ______________+-____- J

DATA------------~---r'~y'y~
drw05

NOTES:
1, If i'iDS goes low during a burst cyi::le. a new address will be loaded and another burst cycle will be started.
2. If ~ is taken inactive during a burst read cycle. the burst counter will discontinue counting until ~ input again goes active. The timing of the CS input
for this control of the burst counter must satisfy setup and hold parameters ts and tH.
3, A-Data from input address
B-Data from input address except Ao is now Ao,
C-Data from input address except A1 is now A1.
D-Data from input address except Ao and A1 are now Ao and A1.

UPDATEl B

251

IDT7MP6086
128K BYTE CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE
14----

elK

tCYC~

--1ftCHttCL~I~~~~nits~tJf--

rr

... ts
ADDRESS

\

I~

... ...tH

... ts

j4-

-(2)

-~

DATA IN

'{
tOHZ(1)
HIGH-Z

DATAoUT

J]

tOLZ

r::.
'I
1\
drw06

NOTES:
1. OE Must be taken inactive at least as long as tOHZ + ts before the second rising clock edge of write cycle.
2. CS timing is the same as any synchronous signal when used to block writes or to stop the burst count sequence.

UPDATE1 B

252

IDT7MP6086
128K BYTE CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF BURST WRITE CYCLE

elK

ADDRESS

DATA IN - - - - - - - - - - - - - { ,

tOHZ(1)

-l+-~J~

HIGH-Z

DATAOUT _ _ _ _ _ _ _----'~

drw07

NOTES:

1. DE Must be taken inactive at least as long as tOHZ + IS before the second rising clock edge of write cycle.
2. A-Data to be written to original input address.
B-Data to be written to original input address except AD is now AD.
CoData to be written to original input address except A1 is now AI.
D-Data to be written to original input address except AD and A1 are now Ao and A1.
3. If Ami goes low during a burst cycle, a new address will be loaded, and another burst cycle will be started.
4. IfCSis taken inactive during a burst write cycle the burst counter will discontinue counting until the CS input again goes active. The timing of the CS input
for this control olthe burst counter must satisfy setup and hold parameters IS and IH. CS timing is the same as any synchronous signal when used to block
writes or to stop the burst count sequence.

UPDATE1 B

253

EI
:

IDT7MP6086
128K BYTE CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

COMMERCIAL TEMPERATURE RANGE

TRUTH TABLE
ClK

Previous ADS

Af)S

i
i
i
i
i
i
i

H

L

X

H

L

X

X

H

L

X

X

H

L

X

-

-

-

X

H

L

X

-

-

i
i

-

-

Address
Valid Input

-

-

WE
X

CS
X

at
-

-

-

-

-

-

-

L
L

-

H
H

-

-

-

H

Hi-Z

H

-

L

DATAoUT

L
L
L

L
L
L

H
H

DATA IN

L

-

NOTE:

H
L

-

1/0

-

DATAIN

Function
Preset Address Counter
Ignore External Address Pins
Ignore External Address Pins
Sequence Address Counter
Sequence Address Counter
Suspend Address Sequencing
Suspend Address Sequencing
Outputs Disabled
Read
Write
Write
Not Allowed
Iblll

= HIGH
=LOW

= Don'l Care
= Unrelated
Hi-Z = High Impedance

X

UPDATE1 B

254

IDT7MP6086 .
128K BYTE CMOS SECONDARY CACHE MODULE FOR THE INTEL 1486

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

lOT

xxxxx

A

999

A

A

Device

Power

Speed

Package

Process!
Temperature

Type

Rarge

I

~Blank

Commercial (O°C to +70°C)

' - - - - - - - - - 11 M

FR-4 SIMM (Single In-Une Memory Module)

1

25
~----------~33

40

} ..... "M""h""

50
~------------------~----~S

' - - - - - - - ' - - - - - - - - - - - - - - - 1 7MP6086

Standard Power
128K Byte i486 Cache Module
drwOB

UPDATE1 B

255

4LJ

PRELIMINARY
FAST CMOS 32-BIT BUFFER/LINE
IDT7MP9244T/AT/CTZ
DRIVER AND BIDIRECTIONAL
IDT7MP9245T/AT/CTZ
TRANSCEIVER MODULES

Integrated Device TecbnoloBY. Inc.

FEATURES:

DESCRIPTION:

• High density 32-bit FCT Logic modules
Equivalent to FAST'M speed and drive
Low profile module 75-pin ZIP (Zig-zag In-line vertical
Package)
• Uses 70 mil pitch leads for maximum density
Surface mount components on a multilayer epoxy laminate
(FR-4) substrate
• True TTL input and output compatible
- VOH = 3.3V (typ.)
- VOL = 0.3V (typ.)
-loL=64mA
• CMOS power levels (1 OmW typo static)
• Single 5V (±5%) power supply
• Multiple GND pins and decoupling capacitors for maximum
noise immunity

The IDT7MP9244T/AT/CTand IDT7MP9245T/AT/CTlogic
modules are designed to be employed as 32-bit memory and
address drivers, clock drivers and bus-oriented transmitterl
receivers which require maximum board packing density. The
IDT FCT logic components are built using advanced CEMOSTM ,
a dual metal CMOS technology.
The IDT7MP9244T/AT/CT has byte output enable control
and the IDT7MP9245T/AT/CT has word output enable and
transmiVreceive control.
The IDT7MP9244T/AT/CT and IDT7MP9245T/AT/CTare
packaged in a 75 pin ZIP (Zig-zag In-line vertical Package)
module offering the optimum in packing density. The dual row
(70 mil lead pitch) vertical configuration allows 75 pins to be
placed on a package 2.65 inches long, 510 mils tall and only
180 mils thick, resulting in a three-fold density improvement
over an equivalent monolithic though-hole implementation.

FUNCTIONAL BLOCK DIAGRAMS

Ob·7
OEl

OB·15
0102

0116-23
01:3

D124·31

061

,

:1
,
:1
,
:1
,
:1

IDT7MP9245

IDT7MP9244

,8

10T74FCT244 - T

, .-

'!I 8

DOH

8

I/OoA·7A
08

IDT74FCT245 - T

TIR1

,8

10T74FCT244 • T

'!I.8

10T74FCT244 • T

'!I.8

IDT74FCT244 - T

, .-

'!I 8

, .-

'!I 8

, .-

,8

DOI-15

8

"

11008-78

8

IlOaA·15A

-

IDT74FCT245 • T

8

...

1l0a8-158

0016-23

1I016A-23A
0102

~8

...
IDT74FCT245 - T

~8

"-

110168-238

TIR1
0024-31

8

1/024A-31A

2836 drw 01.

IDT74FCT245 - T

8

...

110248-318

2836 drwOlb

CEMOS is a trademark of Integrated Device Technology, Inc.
FAST is a trademark of Natlonaf Semicondudor Co.

MAY 1991

COMMERCIAL TEMPERATURE RANGE
«:11991 Integrated Device Technology,lnc.

DSC·7090/-

UPDATE1 B

256

IDT7MP9244T/AT/CT, IDT7MP9245T/AT/CT
FAST CMOS 32-BIT BUFFER/UNE DRIVER/BIDIRECTIONAL TRANSCEIVER MODULES

COMMERCIAL TEMPERATURE RANGE

PIN CONFIGURATION(1)
IDT7MP9244
Dlo
Dil
DI2
DI3
DI4
Dis
Dis
DI7
GND
01:2
Dis
DI9
Dilo
Dill
DIl2
DIl3
DIl4
Dils

Vee
Dils
DI17
Dils
DIl9
DI20
DI21
DI22
DI23
GND
OE4
DI24
DI25
DI26
DI27
DI2s
DI29
DI30
DI31
NC

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

45

47
49
51
53
55
57
59
61
63
65
67
69
71
73
75

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74

IDT7MP9245
I/OOA
I/OIA
1/02A
1/03A
1/04A
1/0 SA
110 SA
1/07A
GND
OEI
110 SA
1/09A
1/0 lOA
I/O"A
1I012A
1/013A
1/011 06
1. For conditions shown as Max. or Min .• use appropriate value specified under Electrical Characteristics for the applicable device type,
2. Typical values are at VCC = 5,.OV, +25°C ambient.
3. Per TIL driven input (VIN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
S. Ic = 10UIESCENT + hNPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + IccQ (!cP/2 + fiNi)
Icc = Quiescent Current
Alcc = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
t, = Input Frequency
NI = Number of Inputs at fl
All currents are in milliamps and all frequencies are in megahertz.
7. Gross functional testing is performed on the IDT modules; power supply characteristics of the IDT modules are guaranteed by design but not tested.

UPDATE1 B

259

III
_.

IDT7MP9244T/AT/CT, IDT7MP9245T/AT/CT
FAST CMOS 32·BIT BUFFER/UNE DRIVER/BIDIRECTIONAL TRANSCEIVER MODULES

COMMERCIAL TEMPERATURE RANGE

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR IDT7MP9244(1)
7MP9244T
Symbol

Parameter

Condlllon(2)

7MP9244AT

7MP9244CT

Mln.!3)

Max.

Mln.(3)

Max.

Mln.(3)

Max.

Unit

1.S

6.S

1.S

4.8

1.S

4.1

ns

tPlH
tPHl

Propagation Delay
DNtoON

tPZH
tPZl

Output Enable Time

1.S

8.0

1.S

6.2

1.5

5.8

ns

tPHZ
tPlZ

Output Disable Time

1.5

7.0

1.5

S.6

1.5

5.2

ns

Cl= SOpF
Rl= soon

NOTES:
28361b107
1. Specifications are for the IDT74FCT244-T components used on the IDT7MP9244. Gross functional testing is perfonned on the IDT modules; switching
characteristics of the IDT modules are guaranteed by design but not tested.
2. See test circuit and wave forms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
2836 Ibl 07

SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR IDT7MP9245(1)
7MP9245T
Parameter

Condltlon(2)

tPlH
tPHl

Propagation Delay
IIOA to I/0s, I/0s to IIOA

Cl = SOpF

tPZH
tPZl

Symbol

7MP9245AT

7MP9245CT

Mln.!3)

Max.

Mln.l3)

Max.

Mln.!3)

Max.

Unit

1.5

7.0

1.5

4.6

1.5

4.1

ns

Output Enable Time
OE to IIOA or I/0s

1.5

9.5

1.5

6.2

1.5

5.8

ns

tPZH
tPZl

Output Disable Time
OE to IIOA or I/0s

1.5

7.5

1.5

5.0

1.5

4.8

ns

tPZH

Output Enable Time
TtR to IIOA or I/0s

1.5

9.5

1.5

6.2

1.5

5.8

ns

tPZl

Rl= 500n

tPHZ
Output Disable Time
1.5
1.5
7.5
1.5
5.0
4.8
ns
tPlZ
TlR to IIOA or IlOs
NOTES:
2836 Ibl os
1. Specifications are for the IDT74FCT24S-T components used on the IDT7MP924S. Gross functional testing is performed on the IDT modules; switching
characteristics of the IDT modules are guaranteed by design but not tested.
2. See test circuit and wave fonns.
3. Minimum limits are guaranteed but not tested on Propagation Delays.

UPDATE1 B

260

IDT7MP9244T/AT/CT, IDT7MP924ST/AT/CT
FAST CMOS 32-BIT BUFFER/UNE DRIVER/BIDIRECTIONAL TRANSCEIVER MODULES

COMMERCIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS (FOR ALL OUTPUTS)
SWITCH POSITION
Vee

Test

Switch

Open Drain
Disable Low
Enable Low

Closed

All Other Outputs

Open

DEFINITIONS:
2836 tbl 09
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.

SET-UP, HOLD AND RELEASE TIMES
DATA

~~

xxt

PULSE WIDTH

-=-wnV

j
tsu .....'I4----I

~~V
-::::::~~=E====--=-_ 3V

INPUT _
TIMING

ASYNCHRONOUS CONTROL
CLEAR
PRESET

ETC.

tREM

I.SV
=::::*:!~=t====~-- 3V
OV

SYNCHRONOUS CONTROL

CLOCK:~~~
vvY j
ETC. ~SU

:""'"I~'-;,.;aj~

t

3V

-1.SV

PROPAGATION DELAY

-OV

ENABLE AND DISABLE TIMES
ENABLE

~-------,.-----3V

---1.SV

SAME PHASE
INPUT TRANSITION

-~--7~--'+~---OV
OUTPUT -...L........rlNORMALLY
LOW

OUTPUT

opposrrE PHASE
INPUT TRANSITION

DISABLE
r-------3V

---.1----

OUTPUT
NORMALLY
HIGH ____......c..

3.SV
VOL
VOH

OV

OV
NOTES
2B36drw 10
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate!'> 1.0 MHz; Zo $ SOQ; IF $ 2.Sns;
IR $2.5ns.

UPDATE1 B

261

IDT7MP9244T1AT/CT, IDT7MP9245T/AT/CT
FAST CMOS 32-BIT BUFFER/UNE DRIVER/BIDIRECTIONAL TRANSCEIVER MODULES

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION
IDT

XXXXX
--Device
Type

A

999

Power

Speed

A
-Package

A
Process/
Temperature
Range

I'------II

Blank

Commercial (O°C to +70°C)

Z

FR-4 ZIP (Zig-zag vertical In-line Package)

IT
CT

} Speed Grade

'------------------{ S

'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1 7MP9244
7MP9245

Standard Power
32-Bit Buffer/Line Driver Module
32-Bit Bidirectional Transceiver Module
2836 drw 11

UPDATE1 B

262

(;)"
Integrated Device Technology. Inc.

THE SUBSYSTEM'S "FLEXI-PAKTM"
CMOS MODULE FAMILY

GENERAL
INFORMATION

SRAM, EPROM, & EEPROM MODULES

FEATURES:

DESCRIPTION:

High·density modules using high-speed CMOS SRAM,
EPROM, and EEPROM components.
Inter-changeable modules, with equivalent footprints,
support a wide range of applications
Fast access times:
<····· • · .·• ·.· ·••·• ···. ···~~+¥:$9~~(iriMJEmillt~rY.·

•. • . •. . . •.
.... . ·•..•· . ·...>ii
~?ijs(m~x;)~f°inmer(;ial .
EEPfl(jr~1: ~$i1S (iriax;) -milltarY . •.•. . . .
··iii. ?Sijs(iri~x:) 790M~erci~I.·.
EPROM: ~9n~ (m?X}~rDllit<3ry . •. •. •.

..........••. i~9ri~@<3)(;)C(;oriiQ1erCial

Low power CMOS operation
Surface mounted LCC components on a co-fired ceramic
substrate
Offered in a 66-pin, ceramic HIP (Hex In-line Package)
occupying only 1 sq. inch of board space
Single 5V (± 10%) power supply
Multiple ground pins for maximum noise immunity
Inputs and outputs directly TIL-compatible

The Flexi-Pak family of modules are high-speed, highdensity CMOS memory modules constructed on a multilayer
co-fired ceramic substrate using either SRAM, EPROM, or
EEPROM components in lead less chip carriers.
This family of IDT modules supports applications requiring
stand alone static or programmable memory or those applications needing a combination of both. All module configurations
in this family have equivalent footprints, allowing "plug-in
compatibility" with each other (Le. interchangeable), ideal for
a wide range of prototype and debugging applications.
The Flexi-Pak family utilizes the fastest commercial grade
and MIL-STD-BB3 Class S military grade components, giving
you the highest performance available anywhere. CMOS
technology offers a low-cost, low-power alternative to bipolar
and fast NMOS memories.
All versions of the Flexi-Pak Module Family are offered in
a66-pin, ceramic HIP (Hex In-line Package). This HIP package
is similarto a PGA and allows the designer to fit into 1 sq. inch
of board space.
Alii DT military modules are assembled with semiconductor
components compliant with the latest revision of MIL-STDBB3 Class S, making them ideally suited to applications
demanding the highest level of performance and reliability.

ORGANIZATIONS
SRAM:

IDT7M4003 - 12BK x 8, 64K x 16, 32K x 32
IDT7M4013 - 512K x 8, 256K x 16, 12BK x 32

SRAM / EEPROM:

IDT7M7005 - 64K x B / 64K x B
64K x 8 / 32K x 16
32K x 16 / 64K x B
32K x 16/ 32K x 16
IDT7M7025* -64K x B / 256K x B
64K x 8 / 12BK x 16
32K x 16 / 256K x 8
32K x 16/ 128K x 16
IDT7M7035* -256K x B / 256K x B
256K x B / 128K x 16
12BK x 16/ 256K x B
128K x 16 / 128K x 16
IDT7!Vl7045* -256K x 8 / 64K x B
256K x 8 / 32K x 16
128K x 16 / 64K x B
128K x 16 / 32 K x 16

'Pll3ase coosuJtth.e

EEPROM: IDT7M7004 -12BK x B, 64K x 16, 32K x 32
IDT7M7014*- 512K x B, 256K x 16, 128K x 32
SRAM / EPROM:

IDT7M7012 - 64K x 8 / 64K x B
64K x B / 32K x 16
32K x 16/ 64K x B
32K x 16/ 32K x 16
IDT7M7002 - 64K x B / 256K x B
64K x B / 128K x 16
32K x 16 / 256K x 8
32K x 16 / 12BK x 16
IDT7M7022* -256K x 8 / 256K x 8
256K x 8 / 128K x 16
128K x 16/ 256K x 8
128K x 16 / 128K x 16
IDT7M7032* -2561<)( 8 / 641<)( 8
256K x 8 / 32K x 16
128K x 16/ 64K x 8
128K x 16/ 32K x 16

facto~fciravaila~iljty ofihese versions ..

Flexi-Pak is a Trademark of Integrated Device Technology. Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES
C1991 Integrated Device Technology. Inc.

UPDATE1 B

MAY 1991
263

t;).

WIDTH EXPANSION OF SyncFIFOsTM
(CLOCKED FIFOS)

APPLICATION
NOTE
AN-83

Integrated Device Technology, Inc.
by Rob De Voto

INTRODUCTION
The performance requirements of today's systems are
continually reaching to new heights. In response to needs for
higher performance, IDT has introduced a family of First-InFirst-Out (FIFO) buffers which are ideally suited for system
speeds of 25MHz or greater. The synchronous interface of
this family of Clocked FIFOs offers several advantages over
the traditionallDT720X Series of FIFOs:
a) speed (data transfer rates of up to 67MHz);
b) free running clock control simplifies system design.
The Clocked FIFO family includes xS-bit, x9-bit, and x1Sbit parts in a wide range of densities. To accommodate
system requirements beyond this product family, the FIFOs
can be easily expanded in width and depth. The purpose of
this Application Note is to discuss design considerations and

~-------

recommendations when designing with SyncFIFOs (Clocked
FIFOs) in Width Expansion.

SKEW TIMING
The inherent advantage of FIFO buffers is the ability to
buffer data between two mismatched systems or subsystems. Inherent to an interface between two asynchronous
systems is the issue of synchronizing events on one side with
respect to events on the other.
For the Clocked FIFOs, internal logic is used to synchronize the status flags to either the Write Clock (WCLK) or the
Read Clock (RCLK). A skew time is specified which determines if sufficient time has been allowed for the flag to be
updated in the current clock cycle. If the skew timing is not
met, an extra cycle is required to update the flag.

tCLK----------__~

WCLK

DO - D7

NO OPERATION
~~--tWFF----~

tSKEW1(1)

RCLK

-----~/
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If
the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next'
WCLKedge.
Figure 1. Skew Timing

SyncFIFO Is a trademark of Integrated Device Technology. Inc.
6191

©1991 Integrated Device Technology, Inc.

UPDATE1 B

264

WIDTH EXPANSION OF SYNCHORNOUS FIFOS
(CLOCKED FIFOS)

APPLICATION NOTE AN-S3

WIDTH EXPANSION
When using the Clocked FIFOs in Width Expansion, the
control signals of all parallel FIFOs should be connected

DATA IN (D)

/2x

/

~

RESET (RS)

RESET (AS)

~

~

/
/
WRITE CLOCK (WCLK)

WRITE ENABLE

(WEN)

together to maintain concurrent operations on all devices.
The recommended flag output circuitry is shown in the
following section.

y.:.
~

--------------

--

--

READ CLOCK (RCLK)

--------

READ ENABLE (FiEN)

--------

OUTPUT ENABLE (OE)

-------

lOT
Clocked
FIFO

lOT
Clocked
FIFO

m

IX

DATA OUT (0)

I

I

1 2x

.

I

Figure 2. Block Diagram Showing the Control Signals of a SyncFIFO (Clocked FIFO) in a Width Expansion Configuration

DESIGN CONSIDERATIONS
Inherent to all Clocked FIFOs is the concept of skew timing.
In reality, the skew timing of individual devices may vary by a
small amount. For example, the tSKEW, minimum spec forthe
20 ns speed grade of the IDT72211 (512 x 9-Bit) equals 8ns.
For two devices in width expansion, the actual tSKEW, of
FIFO#1 may equal7.2ns and the actualtsKEw, of FIFO#2 may
equal 7 Ans.
This small variation in the actual timing of the devices may
cause the flags of the parallel devices to be de-asserted in

different cycles. For example, if the tSKEW, timing of the
system happens to be 7.3ns on the edge which is de-asserting
the EF, then the EF of the two FIFOs will be de-asserted on
different clock cycles.
In this situation. if REN is asserted to begin read operations
when the EF of FIFO#1 is de-asserted but the EF of FIFO#2
is not de-asserted, then data on the outputs (0) of the two
devices will not be aligned. In other words, data from FIFO#2
will have a one location lag behind data from FIFO#1.

UPDATE1 B

265

WIDTH EXPANSION OF SYNCHRONOUS FIFOS
(CLOCKED FIFOS)

APPLICATION NOTE AN-S3

WCLK

Data Inputs (D)

WEN

RCLK

EF

REN
1A

Data Ouputs (0)

DO
tOLZ

_ _ _ _ _ _ _ _ _ _ _ _--.... joooIIf---- tOE

D1

..

OE

Figure 3_ Skew Timing for FIFO#1

UPDATE1 B

266

WIDTH EXPANSION OF SYNCHORNOUS FIFOS
(CLOCKED .FIFOS)

APPLICATION NOTE AN·S3

WCLK

Data Inputs (D)

WEN

RCLK

EF

REN

Data Outputs (0)

DO
toLZ

________________________________________

~~~--------toE

OE

Figure 4. Skew Timing for FIFO#2

UPDATE1 B

267

WIDTH EXPANSION OF SYNCHRONOUS FIFOS
(CLOCKED FIFOS)

APPLICATION NOTE AN-83

SOLUTION AND RECOMMENDATION
There are three solutions to the situation described.
1. Composite Flag. Monitorthe EFfrom all FIFOs in Width
Expansio~ A read operation (REN = low) can begin only
when the EF from all devices have been de-asserted. This is
the recommended solution.
2. WaH two clock cycles after EF de-assertion of anyone
device to begin a read operation. A read operation can begin
(REN = low) once two cycles of the RCLK have occurred after
de-assertion of the EF of anyone of the parallel FI FOs. This
will ensure that the EF on all devices has been de-asserted.

DATA IN (D)

/2x
/

/!,

RESET (RS)

""r""

~
Lf-J...

I

WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)

FULL FLAG (FF) #1

r

In a system where the Enable signals are generated by
logic based on the state ofthe FI FO flags, the occurence oftwo
clock cycles after EF de-assertion is already designed into the
system.
3. Use the Almost Empty Flag (AE) to begin read operations. De-assertion of AE may exhibit the same skew affect
as the EF (see next section), however, using AE does not
jeopardize data integrity.

FULL FLAG (FF) #2

-------------

READ CLOCK (RCLK)

-------

READ ENABLE (REN)

-------

OUTPUT ENABLE (OE)

-------

lOT
Clocked
FIFO #1

EMPTY FLAG (EF) #1

-------

-------

4

x

...

... D-DATAOUT(Q) /2X _

EMPTY FLAG (EF) #2

lOT
Clocked
FIFO #2

/

/

I

Figure 5. Recommended Block Diagram of Width Expansion using Composite Flags

UPDATE1 B

268

WIDTH EXPANSION OF SYNCHORNOUS FIFOS
(CLOCKED FIFOS)

APPUCATION NOTE AN-83

WCLK

Data Inputs (D)

WEN

RCLK

EF

tENS

REN

DO

Data Outputs (a)

toLZ
______________________________________,

~---------toE

OE

Figure 6. Waiting Two Clock Cycles after Flag Assertion

OTHER FLAGS

EXCEPTION

This skew affect also applies to the Full Flags (FF) of all the
Clocked FIFOs (x8, x9 and x18 SyncFIFOs), the AlmostEmpty Flag (AE) and Almost-Full Flag (AF) for the IDT72XXO
family (x8 SyncFIFOs), and the Programmable Almost-Empty
Flag (PAE) and Programmable Almost-Full Flag (PAF) forthe
IDT72XX1 family (x9 SyncFIFOs). The solution for these
flags is identical to those outlined above. In summary:
1. Composite Flag. Monitor the flags from all devices.
2. Wait two clock cycles after de-assertion of the flag of
anyone device.

The exception to the skew affect is the Programmable
Almost-Empty Flag (PAE), the Programmable Almost-Full
Flag (PAF), and the Half-Full Flag (HF) on the IDT722X5
family (x18 SyncFIFOs). These flags are not synchronized
with respect to anyone clock. In other words, they are
asserted and de-asserted with respect to different clocks. In
this case, there is no skew timing (tSKEW1). The monitoring of
only one device in Width Expansion is adequate for these
flags.

UPDATE1 B

269

WIDTH EXPANSION OF SYNCHRONOUS FIFOS
(CLOCKED FIFOS)

APPLICATION NOTE AN·S3

WCLK

PAE

n words in FIFO

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- f

RCLK
tENS

1'1

REN------------------------~~

Figure 7. Programmable Flag Timing for the 1DT722X5 Family (x1S SyncFIFOs)

UPDATE1 B

270

E

1991 Rise DATA BOOK

1991 DATA BOOK UPDATE 1
TABLE OF CONTENTS
LAST BK.

UPDATE PG.

1991 Rise DATA BOOK UPDATES
PARTIALLY UPDATED DATA SHEETS
IDT79R3000A
RISC CPU Processor............... ....... ........................... .............. .... ....... CS.1 ... .......... C - 2
IDT79R3000AE
RISC CPU Processor.......................................................................... CS.1 ............. C - 2
IDT79R3010A
RISC Floating Point Accelerator (FPA) ............................................... CS.3............. C - 4
IDT79R3010AE
RISC Floating Point Accelerator (FPA) ............................................... CS.3............. C - 4
IDT7RS107
R3000 CPU Modules for High Performance and
MultiProcessor Systems... ....... ......... ...... ......... .......... ......... ..... ... ........ C7.S ....... ...... C - S
IDT7RS108
R3000 CPU Modules with 2S6K Cache .............................................. C7.6............. C - B
IDT7RS110
Plug Compatible Family of R3000 CPU Modules ............................... C7.B ............. C - 11
UPDATED FULL DATA SHEETS
IDT79R30S1
IDT79R30S1 Family of Integrated RISControilers™ ...........................
IDT79R30S2
IDT79R30S1 Family of Integrated RISControilers™ ...........................
IDT7RS109
R3000 CPU Modules with 2S6K Cache ..............................................
IDT7RS901
IDT/sim System Integration Manager ROM able Debugging Kemal ...
IDT7RS903
IDT/c Multi-Host C-Compiler System ..................................................
IDT7RS90S
IDT/fp Floating Point Library for Use with R3000 Compilers ..............

CS.S .............
CS.S .............
C7.7.............
CB.9.............
C8.10 ...........
CB.12...........

NEW APPLICATION NOTES
AN-8S
SRAM Timing Parameters for 40MHz R3000A Cache Design ...................................
AN-86
IDT79R30S1™ System Design Example .......................................................... :........
IDT79R3000/R3001 System Performance Analysis ...................................................
AN-87
AN-8B
DMA Techniques with IDT's R3000/R3001 RISC CPU ..............................................
AN-89
R30S1™ Family Performance in Embedded Applications ..........................................

C -16
C -16
C - 42
C - SO
C - S6
C - 62

C - 66
C -71
C - 102
C - 110
C -124

1991 RISC DATA BOOK

Partial Changes to Data Sheets

The following section contains partial data sheets that appeared in the 1991 RiSe Data Book. These data sheets
had changes to less than 50 0/0 of the overall contents. Refer to the bars above changes to see where that section
can be found in the 1991 RiSe Data Book.

UPDATE1 C

UPDATE1 C
2

IDT79R3000A/AE

.

-

UPDATE1 C

Data Book C, Section 5.1, Page 30

3

Data Book C, Section 5.3, Page 9

IDT79R3010A/AE

UPDATE1 C

4

IDT79R3010A/AE

'

Data Book C, Section 5.3,. Page 24

IDT7RS107

Data Book C, Section 7.5, Page 2

External R3000 Condition Code Pin
.T99i§,exe)l?'9IY~§5RiIlon the module.
Q!l1w.§:~§:g:Q.QhQ~lM Code test pin,
sothe R3000 can do a Tesiaiid Branciiiii asiiiglecycle based

on its state,

UPDATE1 C

5

UPDATE1 C

6

IDT7RS107,

Data Book C, Section 7.5, Page 7

UPDATE1 C

7

IDT7RS107

Data Book C, Section 7.5, Page 8

IDT7RS108

Data Book C, Section 7.6, Page 1

R300a MODULE FOR HIGH PERFORMANCE
CPUS:
is constructed using surface mount devices on
board, and is connected to the
u~e'r's system via ::"\
located in two pin row regions on
the board.
'
:. ,

IDT7RS108

Data Book C, Section 7.6, Page 4

SIGNALS PROVIDED ON MODULE PINS

UPDATE1 C

8

IDT7RS108

Data Book C, Section 7.6, Page 6

UPDATE1 C

9

IDT7RS108

Data Book C, Section 7.6, Page 7

UPDATE1 C

10

IDT?RS10S

.

Data Book C, Section 7.6, Page S

,
IDT7RS110

Data Book C, Section 7.S, Page 1

IDT7RS110

Data Book C, Section 7.S, Page 4

SIGNALS PROVIDED ON MODULE PINS

UPDATE1 C

11

IDT7RS110

Data Book C, Section 7.8, Page 6

UPDATE1 C

12

IDT7RS110

Data Book C, Section 7.8, Page 7

IDT7RS110

Data Book C, Section 7.8, Page 8

UPDATE1 C

13

UPDATE1 C

14

1991 RISC DATA BOOK

Changes to Full Data Sheets

The following section contains full data sheets that appeared in the 1991 RiSe Data Book. These data sheets
had changes to 50% or more of the overall contents and
are now considered new. Refer to the bar at the top of
each page to see where that page can be found in the
1991 RiSe Data Book.

UPDATE1 C

15

IDT79R3051/3051 E/3052/3052E

1;).
IntepaRd bevlce TecbnoloKY. Inc.

Data Book C, Section 5.5, Page 1
PRELIMINARY
lOT 79R3051™, 79R3051 E
lOT 79R3052™, 79R3052E

IDT79R3051 FAMILY OF
INTEGRATED
RISControliers™

FEATURES:
• Instruction set compatible with IDT79R3000A and
IDT79R3001 MIPS RISC CPUs
•. High level of integration minimizes system cost, power
consumption
79R3000A 179R3001 RISC Integer CPU
R3051 features 4kB of Instruction Cache
R3052 features 8kB of Instruction Cache
All devices feature 2kB of Data Cache
"E" Versions (Extended Architecture) feature fIJIl
function Memory Management Unit, including 64entry Translation Lookaside Buffer (TLB)
.
4-deep write buffer eliminate!! memory write stalls
4-deep read buffer supports burst· refill from slow
memory devices

•
•
•
•
•
•
•

On-chip DMA arbiter
Bus Interface Minimizes Design Complexity
Single clock input with 40%-60% duty cycle
Direct interface to R3720/21/22 RISChipset™
35 MIPS, over 64,000 Dhrystones at 40 MHz
Low cost 84-pin PLCC packaging with optional thermal
slug
Flexible bus interface allows simple, low cost designs
20, 25, 33, and 40 MHz. operation
Complete software support
Optimizing compilers
Real.-time operating systems
Monitors/debuggers
Floating Point Software
Page Description Languages
'BrCond(3:O)

CI.k2xln

System Control
Coprocessor

Exception/Control
Registers

General Registers
(32 x 32)

32

Address!
Data

DMA
Ctrt

RdlWr ~
Ctrt

Figure 1. R3D51 Family Block Diagram
RISControner, R305x, R3051, R3052 are trademarks of Integrated Device Technology, Inc.

JUNE 1991

COMMERCIAL TEMPERATURE RANGE
1:>1991 Integrated DevIce Technology,lnc.

OSC-3000/1

UPDATE1.C

16

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 2

INTRODUCTION
The lOT R3051 Family is a series of high-performance 32bit microprocessors featuring a high level of integration, and
targeted to high-performance but cost sensitive embedded
processing applications. The R3051 family is designed to
bring the high-performance inherent in the MIPS RISC architecture into low-cost, simplified, power sensitive applications.
Functional units were integrated onto the CPU core in order
to reduce the total system cost, without significantly degrading
system performance. Thus, the R3051 family is able to offer
35 MIPS of integer performance at 40 MHz without requiring
external SRAM or caches.
Further, the R3051 family brings dramatic power reduction
to these embedded applications, allowing the use of low-cost
packaging for devices up to 25 MHz. The R3051 family allows
customer applications to bring maximum performance at
minimum cost.
Figure 1 shows a block level representation ofthe functional
units within the R3051 family. The R3051 family could be
viewed as the embodiment of a discrete solution built around
the lOT 79R3000A or 79R3001. However, by integrating this
functionality on a single chip, dramatic cost and power reductions are achieved.
Currently, there are four members of the R3051 family
family. All devices are pin ,and softw~re compatible: the
differences lie in the amount of instruction cache, and in the
memory management capabilities of the processor:
; .The R3052"E" incorPorates 8kB of Instruction Cache, and
features full function memory management unit (MMU)
including a 64-entry fully-associative Translation
Lookaside Buffer (TLB). This is the same memory
management unit incorporated in the lOT 79R3000A and
79R3001.

a

• The R3052 also incorporates 8kB of Instruction Cache.
However, the memory management unit is a much
simpler subset of the capabilities of the enhanced versions of the architecture, and in fact does not use a TLB.
• The R3051 "E" incorporates 4kB of Instruction Cache.
Additionally, this device features the same full function
MMU (including TLB file) as theR3052"E", and R3000A.
• The R3051 incorporates 4kB of Instruction Cache, and
uses the simpler memory management model of the
R3052.
An overview of the functional blocks incorporated in these
devices follows.
CPU Core
The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close to single cycle execution
rate. The CPU core contains a five stage pipeline, and 32
orthogonal 32-bi! registers. The R3051 family implements the
MIPS ISA. In fact, the execution:engine of the R3051 family
is the same as the. execution engine of the R3000A (and
R3001). Thus, the R3051 family is binary compatible with
those CPU engines.

The execution engine ofthe R3051 family uses a five-stage
pipeline to achieve close to single cycle execution. A new
instruction can be started in every clock cycle; the execution
engine actually processes five instructions concurrently (in
various pipeline stages). Figure 2 shows the concurrency
achieved by the R3051 family pipeline.

1#1

'----'---'---'---t.."""'""j

Current
CPU
Cycle
Figure 2. R3051 Family 5-Stage Pipeline

System Control Co-Processor
The R3051 family also integrates on-chip the System
Control Co-processor, CPO. CPO manages both,the exception handling capability of the R3051 family, as well as the
virtual to physical mapping of the R3051 family.
There are two versions of the R3051 family architecture:
the ExtendedArchitecture Versions (the R3051 Eand R3052E)
contain a fully associative 64-entry TLB which maps 4kB
virtual pages into the physical address space. The virtual to
physical mapping thus includes kernel segments which are
hard mapped to physical addresses. and kernel and user
segments which are mapped on a page basis by the TLB into
anywhere within the 4GB physical address space. In this TLB.
8 page translations can be "locked" by the kernel to insure
deterministic response in real-time applications. These versions thus use the same MMU structure as that found in the
..101' 79R3000A and 79R3001. Figure 3 shows the virtual to
physical address mapping found in the Extended Architecture
versions of the processor family.
The Extended Architecture devices allow the system designer to implement kernel software to dynamically manage
User task utilization of memory resources, and also allow the
Kernel to effectively "protect" certain resources from user
tasks. These capabilities are important in a number of
embedded applications, from process control (where resource
protection may be extremely important) to X-Window display
systems (where virtual memory management is extremely
important). and can also be used to simplify system
. debugging.

UPDATEl C

17

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 3
VIRTUAL

PHYSICAL

Oxffffffff
Kernel Mapped
(kseg2)

$

OxcOOOOOOO
Kernel Uncached
(kseg1)

-

Kernel Cached
(ksegO)

-

Physical
Memory

OxaOOOOOOO

Ox80000000
User Mapped
Cacheable
(kuseg)

1.

OxOOOOOOOO

Memory

3548 MB

r

512 MB

·Flgure 3. Virtual to Physical Mapping of Extended Architecture Versions

The base versions of the architecture (the R3051 and
R3052) remove the TLB and institute a fixed address mapping
for the various segments of the virtual address space. The
base processors support distinct kernel and user mode operation without requiring page management software, leading
to a simpler software model. The memory mapping used by
these devices is illustrated in figure 4. Note that the reserved
address spaces shown are for compatibility with future family
members; in t~e current family members, references to these
addresses are translated in the same fashion as their respective segments, with no traps or ex~eptions taken.

When using the base versions of the architecture, the
system designer can implement a. distinction between the
user tasks and the kernel tasks, without having to execute
page management software. This distinction can take the
formof physical memory protection, accomplished by address
decoding, or in other forms. In systems which do notwish to
implement memory protection, and wish to have the kernel
and user tasks operate out of a single unified me·mory space,
upper address lines can be ignored by the address decoder,
and thus all referenceswill be seen inthe lower gigabyte of the
. .
physical address space.

VIRTUAL

PHYSICAL

Oxffffffff
Kernel Cached
(kseg2)

Kernel Cacheable
Tasks

1024 MB

OxcOOOOOOO
Kernel Uncached
(kseg1)
OxaODOOOOO
Kernel Cached
(ksegO)

User
Cached
(kuseg)

Kernel/User
Cacheable
Tasks

Inaccessible

2048 MB

512 MB
512 MB

OxOOOOOOOO

Figure 4. Virtual to Physical Mapping of Base Architecture Versions

UPDATE1 C

18

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 4

Clock Generation Unit

Bus Interface Unit

The R3051 family is driven from a single input clock,
capable of operating in a range of 40%·60% duty cycle. On·
chip, the clock generator unit is responsible for managing the
interaction of the CPU core, caches, and bus interface. The
clock generator unit replaces the external delay line required
in R3000A and R3001 based applications.

The R3051 family uses its large internal caches to provide
the majority of the bandwidth requirements of the execution
engine, and thus can utilize a simple bus interface connected
to slow memory devices.
The R3051 family bus interface utilizes a 32-bit address
and data bus multiplexed onto a single set of pins. The bus
interface unit also provides an ALE signal to de-multiplex the
ND bus, and simple handshake Signals to process processor
read and write requests. In addition to the read and write
interface, the R3051 family incorporates a DMAarbiter, to
allow an external master to control the external bus.
The R3051 family incorporates a 4-deep write buffer to
decouple the speed of the execution engine from the speed of
the memory system. The write buffers capture and FIFO
processor address and data information in store operations,
and presents it to the bus interface as write transactions at the
rate the memory system can accommodate.
The R3051/52 read interface performs both single word
reads and quad word reads. Single word reads work with a
simple handshake, and quad word reads can either utilize the
simple handshake (in lower performance, simple systems) or
utilize a tighter timing mode when the memory system can
burst data at the processor clock rate. Thus, the system
designer can choose to utilize page or nibble mode DRAMs
(and possibly use interleaving), if desired, in high-performance
systems, or use simpler techniques to reduce complexity.
In order to accommodate slower quad word reads, the
R3051 family incorporates a 4-deep read buffer FIFO, so that
the external interface can queue up data within the processor
before releasing it to perform a burst fill of the internal caches.
Depending on the cost vs. performance tradeoffs appropriate
to a given application, the system design engineer could
include true burst support from the DRAM to provide for highperformance cache miss processing, or utilize the read buffer
to process quad word reads from slower memory systems.

Instruction Cache
The current family includes two different instruction cache
sizes: the R3051 family (the R3051 and R3051 E) feature 4kB
of instruction cache, and the R3052 and R3052E each incor·
porate 8kB of Instruction Cache. For all four devices, the
instruction cache is organized as a line size of 16 bytes (four
words). This relatively large cache achieves a hit rate well in
excess of 95% in most applications, and substantially con·
tributes to the performance inherent in the R3051 family. The
cache is implemented as a direct mapped cache, and is
capable of caching instructions from anywhere within the 4GB
physical address space. The cache is implemented using
physical addresses (rather than virtual addresses), and .thus
does not require flushing on context switch.
Data Cache
All four devices incorporate anon-chip data cache of 2kB,
organized as a line size of 4 bytes (one word). This relatively
large data cache achieves hit rates well in excess of 90% in
most applications, and contributes substantially to the performance inherent in the R3051 family. As with the instruction
cache, the data cache is implemented as a direct mapped
physical address cache. The cache is capable of mapping any
word within the 4GB physical address space.
The data cache is implemented as a write through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance.

UPDATE1 C

19

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 5

SYSTEM USAGE
~he lOT R3051 family,has been specifically designed to

easily connect to. low-cost memory systems. Typicallowccost
memory systems utilize slow EPHOMs, DRAMs, and application specific peripherals. These systems may also typically
con!ain large, slow static RAMs,although the lOT R3051
family has been designed to not specifically require the use of
external SRAMs.'
Figure 5 shows a typical system block diagram. Transparent latches are used to de-multiplex the R3051/52 address
and data busses from the AID bus. The data paths between

the memory system elements and the R3051 family AID bus
is managed by simple octal devices. A small set of simple
PALs can be used to control the various data path elements,
and tocontr61 the handshake between the memory devices
.
.. .
.,
.
and the CPU. .
Alternately, the memory interface can be constructed using
the lOT R3051 family RISc;hipset, which includes DRAM
control, data path control for interleaved memories,and other
general memory and system interface control functions. ThesEl
~~vices are described in separate data sheets. Figure 6
IlIu~tratesa simple system constructed using the R3051
RISChipset.
'.

CIk2xln
Int(5:0)

lOT R3051 Family
, ..RISControlier

BrCond(3:0)
BusReq
BusGnt
AD(31:0)

ALE

Addr(3:2)

. SysClk

Rd

Memory and Interface
Control PALs

t--+---------..!

Address
Decode
PAL

EPROM

1/0 Devicesl 1 4 - - -....
Peripherals
System VO

Figure 5. Typical R3051 Family Based System

UPDATE1 C

20

-

IDT79R3051 13051 E/3052/3052E

Data Book C, Section 5.5, Page 6

Clk2xln
ID179R3D51 Family
RISControlier

Addressl
Data

Control

R3051 Family
Local Bus

""

I>

ID179R3722
Integrated
110 Controller

PROM

110

ID179R3721
'--

DRAM
Controller

110

DRAM

DRAM

ID179R3720
Bus Exchanger
(2)

.-

!

"'"

Figure 6. R3051 Family Chip Set Based System

UPDATE1 C

21

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 7

DEVELOPMENT SUPPORT
The lOT R3051 family is supported by a rich set of development tools, ranging from system simulation tools through
prom monitor support, logic analysis tools, and sUb-system
modules.
Figure 7 is an overview of the system development process
typically used when developing R3051 family-based applications. The R3051 family is supported by powerful tools
through all phases of project development. These tools allow
timely, parallel development of hardware and software for
R3051/52 based applications, and include tools such as:
o A program, Cache-3051, which allows the performance of
an R3051 family based system to be modeled and
understood without requiring actual hardware.
o Sable, an instruction set simulator.
Optimizing compilers from MIPS, the acknowledged
..
leader in optimizing compiler technology;
o lOT Cross development tools, available in a variety of
development environments.

System
Architecture
Evaluation

• The high-performance lOT floating point library software,
which has been integrated into the compiler toolchain to
allow software floating point to replace hardware floating
point without modifying the original source code.
o The lOT Evaluation Board, which includes RAM,
EPROM, 1/0, and the lOT Prom Monitor.
o The lOT Laser Printer System board, which directly
drives a low-cost print engine, and runs Microsoft
Truelmage™ Page Description Language on top of
PeerlessPage™ Advanced Printer Controller BIOS.
o Adobe PostScript™ Page Description Language, ported
to the R3000 instruction set, runs on the IDT R3051
family.
o The IDT Prom Monitor, which implements a full prom
monitor (diagnostics, remote debug support, peek/poke,
etc.).
o An In-Circuit Emulator, developed and sold by Embedded
Performance, Inc.

System
Development
Phase

---

System
Integration
and Verification

SABLE Simulator
DBG Debugger
PIXIE Profiler
MIPS Compiler Suile

Stand-Alone Libraries

Floating Point Library
Cross Development Tools
Adobe PostScript™ POL
MicroSoft Truelmage™ POL
Ada

Cache·R305x
Hardware Models
General CAD Tools
RISC Sub.systems '
Evaluation Board
Laser Printer System

Figure 7. R30S1 Family Development Toolchaln

UPDATE1 C

22

-

-

""'..

~

~

~

~

~~~

,

¥~

"'"

IDT79R3051 13051 E/3052/3052E

•

_

.

?

~'""

~

Data Book C, Section 5.5, Page 8

PERFORMANCE OVERVIEW
The R3051 family achieves a very high-level of performance. This performance is based on:
• An efficient execution engine. The CPU performs ALU
operations and store operations at a single cycle rate,
and has an effective load time of 1.3 cycles, and branch
execution rate of 1.5 cycles (based on the ability of the
compilers to avoid software interlocks). Thus, the
execution engine achieves over 35 MIPS performance
when operating out of cache.
• Large on-chip caches. The R3051 family contains
caches which are substantially larger than those on the
majority of today's embedded microprocessors. These
large caches minimize the number of bus transactions
required, and allow the R3051 family to achieve actual
sustained performance very close to its peak execution
rate.
Autonomous multiply and divide operations. The
R3051 family features an on-chip integer multiplier/divide
unit which is separate from the other ALU. This allows
the R3051 family to perform multiply or divide operations
in parallel with other integer operations, using a single
multiply or divide instruction rather than "step" operations.
• Integrated write buffer. The R3051 family features a
four deep write buffer, which captures store target
addresses and data at the processor execution rate and
retires it to main memory at the slower main memory
access rate. Use of on-chip write buffers eliminates the
need for the processor to stall when performing store
operations.
• Burst read support. The R3051 family enables the
system deSigner to utilize page mode or nibble mode
RAMs when performing read operations to minimize the
main memory read penalty and increase the effective
cache hit rates.
These techniques combine to allow the processorto achieve
35 MIPS integer performance, and over 64,000 dhrystones at
40 MHz without the use of external caches or zero wait-state
memory devices.

SELECTABLE FEATURES
The R3051 family allows the system designer to configure
some aspects of operation. These aspects are established
when the device is reset, and include:
• BigEndian vs. LittleEndian operation: The part can be
configured to operate with either byte ordering convention, and in fact may also be dynamically switched
between the two conventions. This facilitates the porting
of applications from other proc;essor architectures, and
also permits inter-communications between various types
of processors and databases.
• Data cache refill of one or four words: The memory
system must be capable of performing 4 word transfers
to satisfy cache misses. This option allows the system
designer to choose between one and four word refill on

data cache misses, depending on the performance each
option brings to his application.

THERMAL CONSIDERATIONS
The R3051 family utilizes special packaging techniques to
improve the thermal properties of high-speed processors.
Thus, all versions of the R3051 family are packaged in cavity
down packaging.
The lowest cost members of the family use a standard
cavity down, injection molded PLCC package (the "J" package). This package, coupled with the power reduction techniques employed in the design of the R3051 family, allows
operation at speeds to 25M Hz. However, at higher speeds,
additional thermal care must be taken.
Thus, the R3051 family is also available in the "PH" package, which is basically a cavity down PLCC with an embedded
exposed thermal slug. The thermal slug makes direct contact
with the back of the die, allowing efficient thermal transfer
between the die and the case of the part. Even nominal
amounts of airflow will dramatically reduce the junction temperature of the die, resulting in cooler operation. The PH
package is available at all frequencies, and is pin and form
compatible with the PLCC package. Thus, designers can
choose to utilize this package without changing their PCB.
Finally, the R3051 family is also available in a cavity down
PGA with integral thermal slug. As with the PH package, this
package is highly thermally effiCient, and is appropriate for use
in more extreme temperature conditions, such as military
applications.
The members of the R3051 family are guaranteed in a case
temperature range of O°C to +85°C. The type of package,
speed (power) of the device, and airflow conditions, affect the
equivalent ambient conditions which meet this specification.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(0CA) of the given package. The following equation relates
ambient and case temperature:
TA = Tc - P * 0CA
where P is the maximum power consumption at hot temperature, calculated by using the maximum Icc specification
forthe device.
Typical values for 0CA at various airflows are shown in
Table 1 for the various packages.
Airflow (lt/mln)

0CA
"J" Package

0

200

400

600

800

1000

29

26

21

18

16

15

"PH" Packaqe*

22

8

3

2

1.5

1

PGA Package

22

8

3

2

1.5

1

UPDATE1 C

Table 1. Thermal Resistance (0CA) at Various Airflows
(*estimated: final values tbd)

23

I

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 9

PIN DESCRIPTION
PIN NAME

110

AID(31:0)

1/0

DESCRIPTION
Address/Data: A 32-bit time multiplexed bus which indicates the desired address for a bus transaction
in one phase, and which is used to transmit data between the CPU and external memory resources during
the rest of the transfer.
Bus transactions on this bus are logically separated into two phases: during the first phase, information
about the transfer is presented to the memory system to be captured using the ALE output. This
information consists of:
, Address(31 :4):
BE(3:0):

The high-order address for the transfer is presented on AlD(31 :4).
These strobes indicate which bytes of the 32-bit bus will be involved in
the transfer, and are presented on AlD(3:0).

During write cycles, the bus contains the data to be stored and is driven from the internal write buffer.
On read cycles, the bus receives the data from the external resource, in either a single data
transaction or in a burst of four words, and places it into the on-chip read buffer.
Addr(3:2)

0

Low Address (3:2) A 2-bit bus which indicates which word is currently expected by the processor.
Specifically, this two bit bus presents either the address bits for the single word to be transferred (writes
or single datum reads) or functions as a two bit counter starting at '00' for burst read operations.

Diag(1)

0

Diagnostic Pin 1. This output indicates whether the current bus read transaction is due to an onchip cache miss, and also presents part of the miss address. The value output on this pin is time
multiplexed:

Diag(O)

0

Cached:

During the phase in which the AID bus presents address information, this
pin is an active high output which indicates whether the current read is
a result of a cache miss. The value of this pin at this time in other than
read cycles is undefined:

Miss Address (3):

During the remainder of the read operation, this output presents
address bit (3) of the address the processor was attempting to
reference when the cache miss occurred. Regardless of whether a
cache miss is being processed, this pin reports the transfer address
during this time.

Diagnostic Pin O. This output distinguishes cache misses due to instruction references from those
due to datil references, and presents the remaining bit of the miss addr'ess. The value output on this
pin is also time multiplexed:

..

110:

Hthe "Cached" Pin indicates a cache miss, then a high on this pin atthis
time indicates an instruction reference, and a low indicates a data
reference. If the read is not due to a cache miss but rather an uncached
reference, then this pin is undefined during this phase.

Miss Address (2):

During the remainder of the read operation, this output presents
address bit (2) of the address the processor was attempting to
reference when the cache miss occurred. Regardless of whether a
cache miss is being processed, this pin reports the transfer address
.
during this time.

ALE

0

Address Latch Enable: Used to indicate that the AID bus contains valid address information for
the bus transaction. This signal is used by external logic to capturethe address for the transfer, typically
using transparent latches.

DataEn

0

External Data Enable: This signal indicates that the AID bus is no longer being driven by the processor
during read cycles, and thus the external memory system may enable the' drivers of the memory
system onto this bus without having a bus conflicl'occur. During write cycles, or when no bus
transaction is occurring, this signal is negated, thus disabling the external memory drivers

UPDATE1 C

24

~

~

•

_

~

IDT79R3051 13051 E/3052/3052E

~

,_

~w"

~

Data Book C, Section, 5.5, Page 10

PIN DESCRIPTION (Continued):
PIN NAME
Burst!
WrNear

1/0

0

DESCRIPTION
Burst TransferIWrite Near: On read transactions, the Burst signal indicates that the current bus read
is requesting a block of four contiguous words from memory. This signal is asserted only in read cycles
due to cache misses; it is asserted for alii-Cache miss read cycles, and for D-Cache miss read cycles
if selected at device reset time.
On write transactions, the WrNear output tells the external memory system that the bus interface unit
performing back-to-back write transactions to an address within the same 256 word page as the prior
write transaction. This signal is useful in memory systems which employ page mode or static column
DRAMs, and allows near writes to be retired quickly.

is

Rd

0

Read: An output which indicates that the current bus transaction is a read.

Wr

0

Write: An output which indicates that the current bus transaction is a write.

Ack

I

Acknowledge: An input which indicates to the device that the memory system has sufficiently
processed the bus transaction, and that the CPU may either terminate the write cycle or
process the read data from this read transfer.

RdCEn

I

Read Buffer Clock Enable: An input which indicates to the device that the memory system has
placed valid data on the AID bus, and that the processor may move the data into the on-chip Read
Buffer.

SysClk

0

System Reference Clock: An output from the CPU which reflects the timing of the internal
processor "Sys" clock. This clock is used to control state transitions in the read buffer, write buffer,
memory controller, and bus interface unit.

BusReq

I

DMA Arbiter Bus Request: An input to the device which requests that the CPU tri-state its bus
interface signals so that they may be driven by an external master.

BusGnt

0

DMA Arbiter Bus Grant. An output from the CPU used to acknowledge that a BusReq has been
detected, and that the bus is relinquished to the external master.

SBrCond(3:2)
BrCond(l :0)

I

Branch Condition Port: These external signals are internally connected to the CPU signals
CpCond(3:0). These signals can be used by the branch on co-processor condition instructions as input
ports. There are two types of Branch Condition inputs: the SBrCond inputs have special internal
logic to synchronize the inputs, and thus may be driven by asynchronous agents. The direct Branch
Condition inputs must be driven synchronously.

BErr

I

Bus Error: Input to the bus interface unit to terminate a bus transaction due to an external bus error.
This signal is only sampled during read and write operations. If the bus transaction is a read operation,
then the CPU will take a bus error exception.

Int(5:3)
Slnt(2:0)

I

Processor Interrupt: During normal operation, these signals are logically the same as the Int(5:0)
signals of the R3000. During processor reset, these signals perform mode initialization of the CPU, but
in a different (simpler) fashion than the interrupt signals of the R3000.
There are two types of interrupt inputs: the Sint inputs are internally synchronized by the processor,
and may be driven by an asynchronous external agent. The direct interrupt inputs are not internally
synchronized, and thus must be externally synchronized to the CPU. The direct interrupt inputs have
one cycle lower latency than the synchronized interrupts.

Clk2xln

I

Master Clock Input: This is a double frequency input used to control the timing of the CPU.

Reset

I

Master Processor Reset: This signal initializes the CPU. Mode selection is performed during
the last cycle of Reset.

Rsvd(4:0)

1/0

Reserved: These five signal pins are reserved for testing and for future revisions of this device.
Users must not connect these pins.

UPDATE1 C

25

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 11

ABSOLUTE MAXIMUM RATINGS(1, 3)
Symbol
Rating
VTERM Terminal Vo~age
with Respect
toGND
Te
Operating Case
Temperature
TBIAS
Temperature
Under Bias
TSTG
Storage
Temperature
VIN
Input Vo~age

Military
Commercial
Unit
-0.5 to +7.0 -0.5 to +7.0 V

RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Temperature
GND
Grade
Vee
Military

Oto+85

-55 to +125

·C

-55 to +125

~5to+135

·C

-55 to +125

-65 to +155

·C

-0.5 to +7.0

-0.5 to +7.0

V

Commercial

AC TEST CONDITIONS
Parameter

5.0±10%

0·Cto+85·C
(Case)

OV

5.0±5%

To Device
Under Test

2860drw 16

Min.

Max.

Unit

VIH

Input HIGH Vo~age

3.0

-

VIL

Input LOW Voltage

-

0.4

V

VIHS

Input HIGH

3.5

-

V

VILS

Input LOW Voltage

-

0.4

Vo~age

OV

OUTPUT LOADING FOR AC TESTING

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VIN minimum = -3.0V for pulse width less than 15ns.
VIN should not exceed Vee +0.5 Volts.
3. Not more than one output should be shorted ata time. Duration olthe short
should not exceed 30 seconds.

Symbol

-55·C to + 125·C
(Case)

V

V
2860 tbl 08

UPDATE1 C

26

·

"

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 12

DC ELECTRICAL CHARACTERISTICS- (Te = DOC to +85°C, Vee =+5.DV ±5%)
25M Hz

20MHz

33.33MHz

40MHz

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

VOH

Output HIGH Voltage

Vee = Min., IOH = -4mA

3.5

-

3.5

-

3.5

-

3.5

-

V

VOL

Output LOW Voltage

Vee = Min., IOL = 4mA

-

0.4

-

0.4

-

0.4

-

0.4

V

-

2.0

-

2.0

-

V
V

Unit

VIH

input HIGH Voltage(3)

-

2.0

Input LOW Voltage(1)

-

2.0

VIL

-

0.8

-

0.8

-

0.8

-

0.8

VIHS

Input HIGH Voltage(2,3)

-

3.0

-

3.0

-

3.0

-

3.0

-

V

VILS

Input LOW Voltage(1.2)

-

-

0.4

-

0.4

0.4

V

Input Gapaeitanee(4)

-

-

10

-

10

10

pF

GOUT

Output Capaeitanee(4)

-

-

10

10

-

10

10

pF

lee

Operating Current

Vee = 5V, TA = 70°C

-

350

400

-

500

600

mA

-

100

-

-

0.4

CIN

-

100

-

100

flA

IIH

Input HIGH Leakage

VIH= VCG

IlL

Input LOW Leakage

VIL = GND

-100

-

-100

-

-100

-

-100

-

flA

loz

Output Tri-state Leakage

VOH = 2.4V, VOL = 0.5V

-100

100

-100

100

-100

100

-100

100

flA

NOTES:
1.
2.
3.
4.

10

100

2860 tbl 10

VIL Min. = -3.0V for pulse width less than 15ns. VIL should not fall below -0.5 Volts for larger periods.
VIHS and VILS apply to elk2xln and Reset.
VIH should not be held above Vee + 0.5 volts.
Guaranteed by design.

UPDATE1 C

27

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 13

AC ELECTRICAL CHARACTERISTICS (1, 2, 3)_ (Tc = O°C to +85°C , Vcc = +5 OV -+5%)
20MHz
Symbol

Signals

Min.

Msx.

25MHz

33.33MHz

40MHz
Max.

Unit

'BiiSRii(j, AcTi, BusError, Siiit, Sel-up 10 §jSCIkrising
RaCEii, !iii, BrCond, SBrCond

6

-

5

-

4

-

3

-

ns

l1a

AID

Sel-Up 10 §jSCIkfalling

7

-

6

-

5

-

4

-

ns

12

'BiiSRii(j, AcTi, BusError, Slnl,

Hold from ~rising

4

-

4

-

3

-

3

-

ns

1

-

1

-

11

Description

Min.

Msx.

Min.

Max.

Min.

RaCEii,rrrt, BrCond,SBrCond
12a

AID

Hold from §jSCIkfalling'

2

-

2

-

13

AID, Addr, Dia~LE, Wr
'BUrStiWriiIiiSr,
, DataEn

Tri-stale from syscIk rising

-

10

-

10

-

10

-

10

ns

14

AID, Addr, DiaM'LE, Wr
13uiStiWriiIiiSr,
, DataEn

Driven from syscIk falling

-

10

-

10

-

10

-

10

ns

-

8

-

7

-

5

ns

-

7

-

6

8

6

5

ns

5

5

3

ns

4

-

2

ns

2

ns

t5

BusGnl

Asserted from §iSCIk rising

IS

BusGnl

Negated from sysClk falling

17

Wr, Rd, 'BUrStiWrNear, AID

Valid from sysClk rising

IS

ALE

Asserted from SysClk rising

-

t9

ALE

Negaled from SYsClk falling

-

4

110

AID

Hold from ALE negated(4)

2

111

DataEn

Asserted from syscIk falling

112

DataEn

114

AID

115

Wr,

4

-

3

-

4

-

3

-

-

2

-

1.5

-

1.5

-

ns

-

15

-

15

-

13

-

12

ns

Asserted from AID Iri-state(4)

0

0

-

0

-

ns

0

-

0

Driven from sysG1I( rising(4)

-

0

-

ns

4

ns

0

0

4

-

6

-

6

-

5

-

4

ns

117

ReI, DataEn, BursilWrN9ar Negaled from SYSClk falling
Addr(3:2)
Valid from syscIk
Diag
Valid from 8YSCIk

7

-

7

-

6

-

5

ns

118

AID

Tri-stale from sYSCiii falling

-

10

-

10

-

9

-

8

ns

119

AID

~ falling to data oul

-

10

-

10

-

9

-

8

ns

120

Clk2xln

Pulse Width High

10

-

8

-

6.5

-

5

-

ns

121

Clk2xln

Pulse Width Low

10

8

25

20

15

12.5

123

~

Pulse Width from Vcc valid

200

-

200

-

-

ns

Clock Period

-

5

Clk2xln

-

6.5

122

-

200

-

200

-

liS

124

Resel

Minimum Pulse Widlh

32

32

-

32

Sel-up 10 SYSClk falling

6

5

-

4

3

126

Inl

Mode sel-up 10 Resel rising

6

-

-

Isys

RiiSiii

-

32

125

-

5

-

4

-

3

-

ns

127

rrrt

Mode hold from ~ rising

2

-

2

1

-

ns

Sel-up 108YSClk falling

6

3

ns

Hold from sYSCiii falling

2

-

130

rrrt, BrCond

Sel-up 10 §iSCIk falling

6

-

5

129

SIiii, SBrCond
SIiii, SBrCond

-

1

128

-

ns

131

rrrt,BrCond

Hold from sysG1I( falling

1

-

tsys

sysClk

Pulse Width

2*122

2*122

132

8YSCIk
8YSCIk

Clock High Time

122-2 122+2 122-2 122+2 122 -1

133

Clock Low Time

122-2 122+2 122-2 122+2 122-1 122 + 1 122 -1 122 + 1

!derate

All oUlputs

Timing deralion for loading
over 25pt<4, 5)

116

7

6

2
5

2

-

2

2*122

2*122

2*122

-

0.5

-

2*122

0.5

5

4
1

-

1

4

-

3

1
2*122

-

2*122

122 + 1 122-1 122 + 1
0.5

-

0,5

ns

ns

ns
ns
ns
ns
nsJ
25pF

NOTES:
1. Alilimings referenced to 1.5 Volts.
2. All oulputs tesled with 25 pF loading.
3. The AC values lisled here reierenceliming diagrams contained in the R3051 Family Hardware User's Manual.
4. Guaranteed by design.
5. This parameler is used 10 derale the AC timings according to the loading of the system. This parameler provides a deration for loads over Ihe specified
tesl condition; that is, the deration factor is applied for each 25 pF over the specified test load condition.

UPDATEl C

28

IDT79R3051 13051 E/3052/3052E

Data Book C, Section 5.5, Page 14

PIN CONFIGURATIONS
0- m 00 r:::i2 c£1 c~ c~ c~
~  ~  

8

>

I~

1ii

C

w 0I~ I~ ...J
« g;

g;

is

is

~

Il)
II)

>

AlD(O)

8 §: M iiiCD
-0
~ z
""0
« ~

>

~

:::J

al

84·Pln PLCC with or without Integral Thermal Slug
Top View

Note:
Reserved Pins must not be connected.

UPDATE1 C

29

IDT79R3051 13051 E/3052/3052E

Data Book C, Section 5.5, Page 15

PIN CONFIGURATIONS (CONTINUED)

M

Vss

Clk2xln

Rsvd
(4)

Rsvd
(2)

Rsvd
(0)

L

AID
(28)

AID
(30)

Vee

Rsvd
(3)

Rsvd
(1 )

K

AID
(27)

AID
(29)

AID
(31)

J

Vee

Vss

H

AID
(25)

AID
(26)

G

AID
(23)

AID
(24)

F

AID
(21)

AID
(22)

E

Vee

o

Vss,

Tnt

Tnt

(4)

(3)

Tnt

Vee

Sint
(2)

(5)

Sint

S
S
BrCond
BrCond BrCond
(0)
(3)
(2)

Sint
(0)

BrCond
(1 )

Vss

RdCEn

Vee

BusReq

Ack

Bus
Error

Reset

m

BusGnt SysClk

Vee

Vss

Wr

DataEn

Vss

ALE

Rd

AID
(20)

AID
(19)

Diag
(1 )

Diag
(0)

C

AID
(18)

AID
(16)

Vss

BursV
WrNear

Addr
(2)

Vss

B

AID
(17)

Vee

AID
(14)

AID
(11 )

AID
(9)

AID
(8)

AID
(6)

AID
(4)

Vss

AID
(1)

Addr
(3)

Vee

A

AID
(15)

AID
(13)

AID
(12)

AID
(10)

Vee

Vss

AID
(7)

AID
(5)

AID
(3)

Vee

AID
(2)

AID
(0)

2

3

4

5

6

7

8

9

10

11

12

R3051
84·Pin Ceramic Pin Grid Array
(Cavity Down)

Bottom View

84·Pin PGA with Integral Thermal Slug
BotlomView

Note:
Reserved Pins must not be connected.

UPDATE1C

30

IDT79R3051/3051E/3052/3052E

Data Book C, Section 5.5, Page 16

t22

Clk2xln

{

t20

~

SysClk

J

t21

;y
~

t32

"

/
t33

tsys

"
r

Figure 8. R3051 Family Clocking

Vee

----------------i

Clk2xln

Reset·

t23
------------------~~------~----~
Figure 9. Power-On Reset Sequence

Reset

--1-

t24

-~ _ _ _ _~ _ _~r~r-------)",.

:r

____.

Figure 10. Warm Reset Sequence

Reset

---------------------------'1
Figure 11. Mode Selection and Negation of Reset

UPDATE1 C

31

IDT79R3051/3051 E/3052/3052E
Runl
Fixufll
Sta I

Stall

Stall

Data Book C, Section 5.5, Page 17
Stall

Stall

Stall

Fixup

PhiClk

SysClk

Rd

AlD(31:0)

Addr(3:2)

ALE

DataEn

Burst

RdCEn

Ack

Diag(1 )

Diag(O)
Start
Read

Turn
Bus

Ack?

Ack?

Ackl Sample
RdCen Data

End
Read

Figure 12. Single Datum Read in R3051 Family

UPDATE1 C

32

IDT79R3051/3051 E/3052/3052E

Runl
Fixupl
Stall
PhiClk

Stall

Stall

Stall

1.--..

Refilll

Refilll

Streaml

Streaml

Fixup

Fixup
Word 1

Word 2

Word 3

~

~

I

~.tla

,--L--I

'----J

..

19

\

1\

I

'00'

14

i1,tla •
Word 2 11
"
11
1\
t2a'j..
t2a'j..

V Word 1 "

~ 12a'j.

11S. .ll0

,"

~tla

14

V
Word 0 "
1\
11

.. h •
I
.. Ir
{
.. ...

'01'

tl~~

~

11,

l1a •

.. I

'10'

tt

~ :;rdl~

1

.I

..

'11'

tlSL;'"

tlSL;'"

..

t12

-

r
115 -

Ill\.

.. 11

14

~tl ~r
-r
..
..
...
--111

V- K t l

.

..

~J

-l-

BE

17

Fixup

.. t15"

.. t18.
Addr
'

tr

11\

.

1'------'

V
1,..-----,.

~

~

~

~

Fixup

f4

t7

114 ..

ALE

Refilll
Streaml

"'-V l\- f l\- f l\-V

.

Addr(3:2)

Refilll
Streaml

Word 0

~

AlD(31:0)

Data Book C, Section 5,5, Page 18

12

12

f-

t..

t2

l-

I

t-

t2

'-- f---I
t17~.!!?_

Diag(1)

~ached~

!:I

Miss Address(3)

Diag(O)

VD

Miss Address(2)

Start
, Read

I

Turn
Bus

I

Ackl
RdCen

I

I

I

I

I

I

I

I

Sample RdCEn Sample RdCEn Sample RdCEn Sample
New
Data
Data
Dala
Data Transaction

Figure 13. R3051 Family Bursl Read

UPDATE1 C

33

Data Book C, Section 5.5, Page 19

IDT79R3051/3051 E/3052/3052E
Stall

Stall

Stall

Stall

PhiClk

AlD(31 :0)

Addr(3:2)

ALE

RdCEn

Sample RdCEn Sample RdCEn Sample
D~a

D~a

D~a

Figure 14 (a). Start of Throttled Quad Read

UPDATE 1 C

34

IDT79R3051 13051 E/3052/3052E

Data Book C, Section 5.5, Page 20

Stall

Refill!
Stream!
-Fixup

Refill!
Stream!
Fixup

Refill!
Stream!
Fixup

Refill!
Stream!
Fixup

-Word 0

Word 1

Word 2

Word 3

PhiClk

AlD(31:0)

Addr(3:2)

ALE

Ack

RdCEn Sample
Data

RdCEn Sample
New
Data Transaction

Figure 14 (b). -End of Throttled Quad Read

UPDATE1 C

35

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 21

AlD(31 :0)

....- - r - - - - ; '-_ _ _ _ _ __

Addr(3:2) --'---+-'.~-r..--..-----.------

ALE _ _ _...,--+-JI

Start
Write

Data
Out

Ack?

Negarte
New
W
Transfer

Ack?

. Figure 15. R3051 Family Write Cycle

/'{

'!II\..

/'{

~.
~
t1t-

I

G
t3

AlD(31 :0)

-

Addr(3:2)

-

Diag(1 :0)

-

/

'!I-

/

'!I-

ALE

/-

/

'!I-

Figure 16. Request and Relinquish of R3051 Family Bus to External Master

UPDATE1 C

36

IDT79R3051 13051 E/3052/3052E

Data Book C, Section 5.5, Page 22
/~

~~

"'.l~

~~

~
16.jf
14

AlD(31:0)

<
<
<

It'

'"

Addr(3:2)

It'

Diag(1:0)

V

I'\.

I'\.

"

ALE,

'"
1/

"
"

/

Figure 17. R3051 Family Regaining Bus Mastership

UPDATE1 C

37

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 23
Run Cycle

Exception Vector

Phi

t28

t29
4000 drw31

Figure 18. Synchronized Interrupt Input Timing

Run Cycle

Exception Vector

Phi

t30

t31
4000 drw 32

Figure 19. Direct Interrupt Input Timing

Run Cycle
Phi

~

"-

V

"/

Capture BrCond

"-

/

"-

/

/

"

./

BCzT/F Instruction

V

"./

"-

r

'-

I

SBrCond(n)

JX
t28

t29

4000drw 33

Figure 20. Synchronized Branch Condition Input Timing

Run Cycle
Phi

"~

BrCond(n)

"/

"-

Capture BrCond

/

/

"-

"/

"-

r

I

~

r--"'"
130

BCzTIF Instruction

"-

"-

~
t31

4000 drw34

Figure 21. Direct Branch Condition Input Timing

UPDATE1 C

38

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 24

84-PIN PGA (CAVITY DOWN)
1

2

3

4

5

S

7

8

g

10 11

12

E1

~~--------D1----------~

E

NOTES

~------------D------------~

SEATING PLANE

NOTES:
1. All dimensions are in inches. unless otherwise noted.
2. SSC-Basic lead Spacing between Centers
3. Symbol "M" represents the PGA matrix size.
4. Symbol"N" represents the number of pins.
5. Chamfered comers are lOT's option.
S. Shaded area indicates integral metallic heat sink.

Drawing #

2874drwOl

G84-4

Symbol

Min

Max

A

.077

.145

"B

.016

.020

"B1

.OSO

.080

"B2

.040

.060

DIE

1.180

1.235

D11E1

1.100 BSe

e
L

.100 BSe

M

12
84

N

Q1

.. 140

.120

.025

.060

UPDATEl C.

39

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 25

84 LEAD PLCC (SQUARE)

45° x .045

--++-----+ ----++

E1

E

~l1J

B

SEATING PLANE
2874 drw 02

NOTES:
1. All dimensions are in inches, unless otherwise noted.
2. BSC-Basic lead Spacing between Centers.
3. 0 & E do not include mold flash or protutions.
4. Formed leads shall be planar with respect to one another and within .004" at the seating plane.
5. NO & NE represent the number of leads in the D & E directions respectively.
6. 01 & El should be measured from the bOllom of the package.

DWG#

J84-1

#of Leads

84

Symbol

Min.

Max.

A

165

.180

A1

.095

.115

B

.026

.032

b1

.013

.021

e

.020

.040

el

.008

.012

0

1.185

1.195

01

1.150

1.156

02/E2

1.090

1.130

03/E3

1.000 REF

E

1.185

1.195

E1

1.150

1.156

e

.050 BSe

NO/NE

21

UPDATEl C

40

IDT79R3051/3051 E/3052/3052E

Data Book C, Section 5.5, Page 26

ORDERING INFORMATION

xxxxx

lOT - - -

Device Type

xx

x

x

Speed Package

y..

Process!
Temp. Range

L..-_ _ _ _ _...,

Blank
'B'
'M'

Commercial Temperature Range
Compliant to MIL-STD-883, Class B
Military Temperature Range Only

'J'
'PH'
'G'

84-Pin PLCC
84-Pin PLCC with Integral Thermal Slug
84-Pin PGA with Integral Thermal Slug

'20'
'25'
' - - - ' - - - - - - - - - - 1 '33'
'40'

L

-------'--------i

79R3051
79R3051 E

79R3052
79R3052E

20.0 MHz
25.0 MHz
33.33 MHz
40.0 MHz
4kB
4kB
8kB
8kB

Instruction
Instruction
Instruction
Instruction

Cache,
Cache,
Cache,
Cache,

No TLB
With TLB
No TLB
With TLB

VALID COMBINATIONS
lOT 79R3051 - 20, 25
79R3051 E - 20, 25
79R3052 - 20, 25
79R3052E - 20, 25
79R3051 - 33, 40
79R3051 E - 33,40
79R3052 - 33, 40
79R3052E - 33, 40

All
All
All
All

packages
packages
packages
packages

PGA,
PGA,
PGA,
PGA,

PH
PH
PH
PH

Packages
Packages
Packages
Packages

Only
Only
Only
Only

UPDATE 1. C

41

IDT7RS109

~.

Data Book C, Section 7.7, Page 1

R3000 CPU MODULES

IDT7RS1D9

Integrated Device Technology, Inc.

FEATURES:
• Cache Size: 64K Instruction, 64K Data

R3DDD MODULE FOR HIGH PERFORMANCE
CPUs AND MULTIPROCESSOR SYSTEMS:

• Processor Speeds up to 33 MHz
• Includes R3010 Floating Point Accelerator
• 1-word Read Buffer; 4-word Write Buffer
• Supports R3000 Multiprocessor Features
• On-Board Parity Check and Generate
• Four or Eight-word block refills
• On-board oscillator, delay line, and reset
circuitry
• 100% burn-in and functional test at rated speed

The IDT7RS109 is a complete reduced instruction set
computer (RISC) CPU, based on the MIPS R3000 RISC
processor, and supplied on a small fully-tested high-density
plug-in module. The module includes the R3000 CPU, the
R3010 Floating Point Accelerator, 64 Kbytes each of data
and instruction cache memory, a single word read buffer and
a four-word write buffer. Clock generation, reset, control,
parity, and interrupt functions are included on the module to
simplify the remainder of the system design.
The 109 module includes a latch to hold an external
address for snooping in the D-cache and is designed to
support the R3000's multiprocessor features.
The module is constructed using surface mount devices
on a 5.2" by 5.2" epoxy laminate board, and is connected to
the user's system via 192 pins located in two pin row regions
on the board.

7RS109 Module. Actual Size 5.2" x 5.2"

MAY 1991

RSD PB109/B
©1991 Integrated Device Technology, Inc.

DSC-9056/1

UPDATE1 C

42

IDT7RS109

Data Book C, Section 7.7, Page 2

ARCHITECTURAL HIGHLIGHTS
Uses R3020 Write Buffers
R3020 chips are used on the module to provide a "smart"
four-deep write buffer between the CPU and external
memory. These devices store data and addresses for up to
four write requests to main memory, and handle the handshaking with the memory controller. The R3020s support
features such as byte gathering (combining multiple byte
writes to the same address in the buffer into a single write)
and address matching (a read orwrite to an address already
in the write buffer will be detected so the user software can
take appropriate action). The R3020's Match signals are
OR'edon the module to produce a single output, labeled
CONFLICT.
Four or Eight-Word Block Refill
The module refills both the instruction and data caches
from memory in either four or eight-word blocks. The block
refill size is set by a jumper on the module. Following a
cache miss, the processor will request a memory read atthe
missed address and wait for a data ready acknowledgement.
When an acknowledge is received, the processor will load
four or eight words into cache on four or eight successive
clock cycles. The memory interface must supply the correct
four or eight words (address A4A3A2 = 0 to 7) at the
processor's speed, 40 ns intervals for a 25 MHz system.
Interleaved memory is usually the best way to support this
requirement. The processor's CPCO pin, available as a pin
on the module, can be used to over-ride the block refill. The
processor performs instruction streaming during the refill.

Five User Interrupt Lines
Five pins on the module are used for user interrupt inputs.
The user interrupts are synchronized in registers on the
module before being sent to the R3000. Interrupt 2 is used
for the Floating Point Accelerator, if present.
External R3000 Condition Code Pin
The R3000 input CPCO is available as a pin on the
module. During run cycles, this pin acts as a Condition
Code test pin, so the R3000 can do a Test and Branch in a
single cycle based on its state. During read stalls, the pin
determines whether a single word or 8 words will be read.
Reads into the instruction cache must always be block
refills.
Internal Parity Check and Generate
The 7RS109 u.ses lOT 73211 registers for the data read
buffer. This device provides the ability to generate parity on
incoming data, if it is not already present, or to check parity
on outgoing data to detect parity errors occuring on the
module.

TYPICAL APPLICATIONS
The 7RS1 09 module is designed for applications that run
complex operating systems, such as UNIXTM, or that need
the maximum possible performance. The module contains
the maximum possible cache sizes (64K each) that can be
supported by the R3000 in Multiprocessor configurations.

On-board Oscillator and Delay Line
All the clock generation circuitry required by the R3000
system is on the module. A jumper can be used to select
between the on-board crystal oscillator or an external oscillator input. A delay line on the module is used to set the
timing for register strobes and other critical signals relative
to the R3000 clock. The R3000 clock output "SYSOUT" is
made available to the user system through eight pins on the
module, each independently buffered.
R3000 Reset and Initialization Logic
The initialization logic forthe R3000 CPU is contained on
the module. A "Cold Reset" pin on the module starts the
required 15 ms reset signal to the CPU, and then provides
the initialization vectors during the last few cycles. A second
reset pin is provided to reinitialize the CPU without repeating
the 15 ms delay. The R3000 is initialized to "Big-Endian"
operation.

UPDATE1 C

43

IDT7RS109

Data Book C, Section 7.7, Page 3

FUNCTIONAL BLOCK DIAGRAM

R3000 and R3010

Address Bus

UPDATEl C

44

,

.

IDT7RS109

Data Book C, Section 7.7, Page 4

SIGNALS PROVIDED ON MODULE PINS
Signal Name

Type

MAO ... MA31

1/0

32-bit address from the module to external memory. This is an output from the 3020 Write Buffer
except during the MP Invalidate function, when it is the input to the MP cache address latch.

Description

MDO ... MD31

1/0

32-bit data bus between the module and external memory. Driven from the 3020 Write Buffer during
writes; input to the Read Data Buffer during reads.

BACTO,1,2

a

The three R3000 AccType status signals, driven from the 3020 Write Buffer during writes and from
a latch during reads.

MDPO ... MDP3

1/0

The four parity bits for the MD data. Output during writes and input during reads.

CP_CpCondO, 2, 3

I

The three flag inputs to the R3000 CPU. CPCO is used during read stalls to control block refill of the
data cache. (The instruction cache must always be block refilled.) CPC2 and CPC3 are the MP stall
and invalidate controls.

ALOE

I

Data Cache Address Latch Output Enable When LOW, enables the output of the latch holding the
data cache address supplied by the R3000. It should be LOW at all times except when the MP Latch
is being used to invalidate a cache address.

BSYSOUT2 ... 9
UINTO,1,3,4,5
BRESET
WB WbFull

a
I

a
a

Eight buffered inverted copies of the R3000 signal "SYSOUT" for use in the user's system.
Interrupt inputs to the R3000. These signals are synchronized to SYSOUT on the module. R3000
interrupt 2 is used for the Floating Point Accelerator.
Buffered copy of the reset signal created on the module to reset the CPU. LOW during Reset.
Write Busy. Status signal created by the R3020 write buffer. Goes LOW to indicate the buffer is full.

CPU_BusError

I

Input to the R3000 indicating a bus error has occurred.

RESETC

I

Cold Heset to the module. The module creates a 15 ms long reset to the R3000 and executes the
R3000 initialization sequence when this pin goes LOW.

a

This signal can be used to detect the presence of an FPA on the module. To be used, it must be
connected to a 4.7K pull up resistor. The pin will be LOW if the FPA is present.

FP_FpPresent
WB_OutEn
WB_Request
WB_Acknowledge
CONFLICT
RABOE
RDBCE

I

a
I

Write Buffer Output Enable. When LOW, turns on the outputs of the R3020 write buffers.
Output from the R3020 to indicate that there is data in the buffer to be written to memory. Active LOW
Input to the R3020 to indicate data has been written into memory.

a

The OR of all the R3020 Match signals; indicates the address on the R3020 inputs matches one of
the addresses currently in the write buffer.

I

Read Address Buffer Output Enable. When LOW, turns on outputs of the buffers containing the read
address.

I

READ

a

Read Data Buffer Clock Enable. When LOW. enables the clock (SYSOUT) to the Read Data Buffers.
Status signal output. LOW during reads.

RABLE

I

WB LatchErrAddr

I

Latch Error Address input to the R3020.

WB EnErrAddr

I

Enable Error Address input to R3020.

Read Address Buffer Latch Enable. When HIGH, enables the Read Address Buffer latches.

CP MemRd

a

CP RdBusy

I

Read Busy. Input to the R3000 to indicate acknowledgment oj the MEMRD request.

EXTOSC

I

Optional Input from External Oscillator

R3000 output signal. When LOW, there is a request for a read from external memory.

UPDATE1 C

45

IDT7RS109

Data Book C, Section 7.7, Page 5

RELATED PRODUCTS
Prototyplng System
The 7RS109 module can be placed into immediate service using our flexible 7RS309 Prototyping Platform. The
system includes two boards: a general purpose CPU board,
and a personality card that interfaces the module to the CPU
board.
The CPU board contains 1Mb of main memory, 256K of
EPROM, two RS232 serial ports, an 8254 counter/timer,
and an 8-bit parallel port accessible through a dual port
RAM. Four 50-pin connectors provide access to all the
address, data, and control signals for external connection to
additional hardware on, for example, a wire-wrap board.

The system includes lOT's Software Integration Manager, which provides facilities for downloading code,
examining memory, and stepping through programs.
The personality card is on a separate board, and provides
a bed for the module, necessary control signals, and connectors for an HP 16500 Logic Analyzer.
Code for the R3000 can be created on a MIPS development system, on lOT's MacStation™ system, orusing lOT's
PC-based cross assembler and compiler products. Assembled code can be downloaded into the Prototyping
System for execution and debug.

A Module Prototyping Platform.
The card on the left is the personality card with a module; the card on the right is the general purpose CPU.

UPDATE1 C

46

IDT7RS109

Data Book C, Section 7.7, Page 6

SPECIFICATIONS
CPU
R3000

User Selectable Options via jumpers:
4 word or 8 word block refill
Big or Little Endian
Streaming/No Streaming
Store Partial On/Off

Floating POint
R3010 optional in either configuration. If present,
connected to INT2.
Cache Ram
64 KB I-cache (16K words)
64 KB D-cache (16K words)
Cacheable Address Space
4 GBytes
MP Support
Cache invalidate supported
Block Refill
4 or 8 word (or single word)
Endianess
User programmable via module pin.
Read/Write Buffers
1 - Word Read Buffer
4 - Word Write Buffer
Interrupts
6 User Interrupts, synchronized with SYSOUTA:D
in an on-board register.
I/O characteristics
TTL levels from FCT logic devices, PALs and R3000
Power Supply
4.5 amps (typical) at 5.0 V, 25°C, at 33MHz.
Environmental Conditions
Ambient temperature DoC to +50°C.
Relative Humidity 5% to 95%
Clock Frequencies
20, 25 and 33 MHz
Interconnection
192 18-mil round pins on 100-mil centers
Mating connector: Samtec SS-1 series socket strips
or equivalent.

UPDATE1 C

47

IDT7RS109

Data Book C, Section 7.7, Page 7

MECHANICAL OUTLINE
7RS109 TOP VIEW
I

'I~~-"--~-------------~::~~~""~~~i
,______
___________
I

'1

·19~

4:t..218o~5~

~~1

.095

_tl~

______~4.~79~5~_ _ _ _ _ _ _ _ _ _ _ _~~~_

II
II
II

I I
II
II

:6

l-.tO

.- E-;. A 3 2 - - - - - - - - - - - - - - - - - - -C32f.-;-;

I

• •

• ••

······
·
········
·
·
·····

··· ·
··· ··
··
···
··
··
··
··
··
·· · P1
··
·
··

0

·

E
F

0

~

1

~~

-.-

-t-

A

D

I

···
··
·
P2 ····

··, ·····
·····

·

····
t-- This command will continue execution

asm  This command allows the user to examine and
change memory interactively using standard assembler
mnemonics.

brklb [addressllst] This command will display all of the
currently set breakpoints if no address list is supplied. If an
address list is supplied, breakpoints are set at each of the
addresses in the list.

cacheflushlcf [-II-eI}

This command will flush both the icache and the d-cache if no option is specified. If the user
wants to just flush one or the other, the optional argument
may be entered.

caillca 
 [arg1 arg2 •.• arg8} This command invokes a subprocedure under the monitor environment. It
will do a jump and link to address passing any arguments,
up to 8, while still in monitor mode.

checksumlcs [starcaddr num_bytes}

Display the

checksums for each of the 'eproms'.

comparelcp [-wl-bl-h}   Compare
the block of memory specified by RANGE to the block of
memory that starts at destination.
contlc

This command continues execution of the client
process from where it last halted execution.

dbglntldi [<-el-d DEV>} Debug interrupt enable/disable -

from the current value of the test program register. The
program will stop execution just prior to the execution of the
instruction pointed to by address.

helpl? [command/ist] This command will print out a list of the
commands available in the monitor. If a command list is
supplied, only the syntax for the commands in the list is
displayed.

hlstory/h This command will display the last 16 commands
entered with identifying numbers so the user may reexecute the command by entering !#. This is a circular list
such that at anyone time the latest 16 commands are
available.

Inltll Initialize prom monitor (warm reset)
loadll [options} DEV This command will input from the
device specified by _DEVrecords of the format specified by
options.

movelm[-wl-bl-h}   Movetheblock
of memory specified by RANGE to the address specified by
destination.
nextln [count] This command is like the 'step' command
except that when a jal or bal instruction is encountered, all
of the instructions of the subprocedure are executed until
the subprocedure returns to the instruction following the
jump or branch and link.

rad [-ol-dl-h} Set the default radix to the requested base.

allows 'break key' to gen extr. int.

debugldb [DEV] Enter remote debug mode.

rc [oil [-wl-bl-h]  Addresses are automatically set

dis 

Disassemble the contents of memory
specified by range. If RANGE consists only of a beginning
address, enough locations following the beginning address
are disassembled to fill one page.

d/sptaglclt [-I] RANGE This command displays the in-

to KseqO and the caches are isolated. Read cache memory
specified by RANGE.

regsellrs [-cl-h} Select either the compiler names or the
hardware names for registers.

struction or data cache contents and the tag values if the
cache location is valid.

 [mask} This
command will search the area of memory specified by
RANGE for the value specified by value.

dr [reg#lnamelregJlTOup] This command will print out the

seg [-OI-11-21-u} Set the default segment to the requested k-

current contents of register(s).

segment.

dumpld [-wl-h}  Dump the memory specified by
RANGE to the display.
fllllf [-wl-hl-bl-II-r}  [value_list} Fills memory
specified by range with value_list..
fr [-sl-d}  Put  into the register
specified by .

golg [-n1 
 This command will begin execution at
address 
.

searchlsr [-wl-bl-h] 

setbaudlsb DEV This command allows the userto select the
baud rate for the device specified by DEV. DEV may be
either ttyO or ttyt.
stepls [count] This command will execute a single step or
if  is supplied then 'count' number of single steps will
be executed.

sub [-wl-hl-bl-II-r] 
 This command allows the
user to examine and change memory interactively.

UPDATE1 C

53

IDT7RS901

Data Book C, Section 8.9, Page 5

te [DEV] This command puts IDT/sim in a transparent mode
and connects the console port straight through to an outer
serial port.
tlbdump/td [RANGE] This command dumps the contents of
the translation buffer. If a range is specified, just the range
is dumped, otherwise the entire buffer is dumped.
tlbflush/tf [RANGE]
This command flushes the contents
ofthe translation buffer. If a range is specified, justthe range
is flushed, otherwise the entire buffer is flushed.
tlbmap/tm [-I index] [-ndgv]   This
command establishes a virtual to physical mapping in the
translation buffer.

tlbptov/tp  This command searches the translation buffer looking for translations which map to
. Any translations found, valid or invalid, are
displayed. The default segment is not applied to .
unbrk/ub  This command will unset all of the
breakpoints listed in . These are the ordinal
numbers of the breakpoints and can be obtained by doing
a 'brk' command.
we [-i] [-w/-b/-h]  [value_list] Addresses are
automatically setto KseqO and the selected cache is isolated.
This command will fill the selected cache memory specified
by RANGE with the pattern specified by value_list.

tlbpid/tl [pid] This command, without arguments, displays
the current process identifier in the system co-processor
register 'tlbhi'. If an argument is supplied then the current
process identifier in 'tlbhi' is set to < pid >.

LIST OF RUN TIME SUPPORT ENTRY POINTS
reset

gets

strlen

restart

puts

strcpy

reinit

printf

strcat

open

_exit

cli

read

flush_cache

get_range

write

clear_cache

tokenize

ioctl

setjmp

geCmem_conf

close

longjmp

secmem-conf

getchar

exc_utlb_code

install_command

putchar

atob

instalLnew_dev

showcar

strcmp

install_immediate_int
Install_normaUnt

UPDATE1 C

54

IDT7RS901

Data Book C, Section 8.9, Page 6

ORDERING INFORMATION
To order EPROMs to upgrade an lOT board level product, see the order codes below. To order 10T/sim in source code,
order the Developmental Use License AND orderthe software on the appropriate source media. The license will be shipped
to you for signature; on return the software will be shipped. You may also order binary distribution rights for the run-time
version of the monitor. Ask your lOT sales office for information.

Licenses
Developmental Use License ••••••..............••.........•..........•........••.......•......••..............•....•.....• 7RS901 SLY
Permits purchase of up to six copies of source code (any media combination) and use of source code
to develop run-time binaries on up to six machines at a time, but does not permit inclusion of the run
time code in ari end product.'

BinarY Distribution Rights ...•.•........•........••..............•.....•........................•...........:........... 7RS901 BLP-L
Extension to Developmental Use License to permit inclusion of binary, code into end product. Development Use License must be referenced on order or ordered simultaneously. This license permits up to
100 copies to be distributed royalty-free. Additional copies are subject to the royalty below, or a onetime buyout.

Binary Distribution Sublicense ...........................................•.......••...............•.....•..••.....••7RS901 BLC-L
Per Copy Royalty or orie-time buyout for distribution of run-times developed using the System Integration Manager beyond the first 100.

Maintenance Agreement .......................••..•..••..........•........................................•.................7RS901 SSY
One year free updates. We supply a direct telephone contact for support.

'

Source Media
10T/sim source code can be compiled with either the MIPSC compiler or with I OT/c Version 3.5 or
later. Earlier versions of 10T/c cannot compile this code. 10T/sim cannot be compiled on the 286
versions of 10T/c due to insufficient memory. The products listed below are media only and must be
purchased with license 7RS901SLV above.
'
Source for 386, MS-DOS ................•..........•..................................................................... 7RS901SBF-L
Compile with IDTlc C-Compiler. Shipped with both 1.2 MB 5.25" and 1.44 MB 3.5" diskettes.
Source for 386 PC, SCQ Xenlx ..................................:..................................................... 7RS901 SXX-L
Use with IDTlc C-Compiler.

Source for lOT MacStatlon, on Mac Disc ............................•.............................•........... 7RS901SMD-L
Use with MIPS C Compiler supplied with MacStation or with /DTlc.

, Source for MIPS machine, QIC-24 TAR Tape ................................................................7RS901 SUU-L
Use with MIPS C Compiler or with IDTlc.

Source for SUN SparcStation, QIC-24 TAR Tape ......................................................... 7RS901SWU-L
Use with IDTlc.

EPROM Versions
The following versions of 10T/sim are supplied in EPROMs for the indicated hardware. These versions are for updating the hardware to the latest version of the monitor.
For Any 7RS30x Prototyping System ...........................•...................................................7RS901 BAP
For the MacStation 1 (7RS501) .......................................................................................... 7RS901 BBP
or the MacStation 2 (7RS502) ...•...............................................................................•........7RS901 BCP
For 7RS382 Evaluation Board ••................•.................................•.......................................7RS901 BOP
For 7RS383 Evaluation board ............•...........•............•......................•.............•.................7RS901 BEP
For 7RS388 Real8™ Laser Printer Controller ...... ~ ....•.........••.•..............•.........•................. 7RS901 BFP

UPDATE1 C

55

IDT7RS903

(;)"

Data Book C, Section 8.10, Page 1

New! Version 3.5

IOT/c
Multi-Host C-Compiler System

IDT7RS903

Intepated DevIce Technology, Inc.

FEATURES:
• Includes C~oinpller, Optimizing Scheduler,
Assembler, Linker, Librarian, and ANSI Libraries
• Optional Floating Point Emulation Software
• Meets Plum Hall 2.00 ANSI C v~Udation suite
• Runs on 80286 and 80386 machines under MSOOSTM or XENIXTM, on MIPS machines and
MacStatlon under,RISC/os, and on Sun
SparcStation
• Supports entire lOT family of MIPS ISA Processors: R3000, R3001, R3051 , and R3052
• Supports Blg- and Little-End Ian Compilations
• Provides control over multiple memory segments
• Produces disassembled link listings to simplify
debug
"

OPTIMIZING C·COMPILER SYSTEM:
IDT/c consistsof a set of software products that run on a
variety of platforms, and which together produce highly
efficient code for R3000 CPUs and derivatives. The compiled code can be downloaded in several formats to a target
machine for execution. On the target machine, the code can
be controlled with IDT's System Integration Manager (IDTI
sim). The compiler is based on the popular GNU C compiler,
and is fully compliant with ANSI.C.
New features in release 3.5 of; IDT/cinclude a library
archiving program, ANSI C libraries, and a utility for moving
initialized variables into EPROM space.
The IDT/c package is available for execution on 286 or
386 machines under MS-DOS or XENIX, as well as the
MIPS and SUN workstations, and lOT's MacStation single
user workstation.
For any platform, IDT/c can be ordered with or without a
software floating point library., A switch in the compiler
determines if floating point instructions will result in R3010
instructions in the object code orwhether calls to the floating
point library will be made instead.

DD~~

DO

IJIU IJIIJIIJIIJI
IJIIJIIJIIJIIJIIJI

DiDiDiDI
HDiDiDi
; RsOOOISA
Target Machine

IOTlc System Flow

MAY 1991

704-00903-00110
C1991 Integrated DevIce Technology. Inc.

DSC-8061/-

UPDATE1 C

56

IDT7RS903

Data Book C, Section 8.10, Page 2

DESCRIPTION
The IOTlc C-Compiler System is a complete development package for CPUs based on the R3DDD architecture.
It contains an optimizing cross compiler, optimizing scheduler, assembler, linker, and a downloader. The 'C' compiler
is compliant with ANSI 'C' standard and performs the optimizations available in state-o-the-art 'C' compilers. The
assembler supports the R3DDD machine instructions and
architecture described in the book by Gerry Kane, "MIPS
RISC Architecture", including both native and synthetic
instructions. The complete IOTIc package runs on a variety
of host machines and operating systems and is part of lOT's
cross development system tools which include other packages such as debug monitors and libraries.
Complier
The C pre-processor is GNU cpp and the compiler itself
is based on GNU C. All C-preprocessing features are
supported. The combination of the compiler and assembler
included in IOTlc has been tested for compliance to the
ANSI 'C' standard using the Plum Hall test suite and is
compliant. Some compiler syntax and directives are different than those in the MIPS C-compiler, but it is possible to
write C programs which may be compiled using either
compiler.
The C compiler performs extensive optimization in mUltiple passes through the code. Each ofthe many optimization
techniques can. be individually switched on or off with
compiler directives.
Optimizing Scheduler and Assembler
The lOT cross assembler input is compatible with source
code written for the MIPS assembler. It implements the
R3DDD native instruction set as well as the augmented
synthetic instructions defined in the "MIPS RISC ARCHITECTURE" book by Gerry Kane. There are some extensions in the lOT cross assembler that provide the programmer with more control over code generation, such as 'Iaiu'load address upper and 'oria' -load address lower, enabling
direct programming in pure assembly language. The assembler produces .0 files which are later linked together with
other files to produce an executable file.
The scheduler first expands the synthetic instructions
into the native instruction set. It then rearranges code to
allow for and take advantage of R3DDD pipeline architecture.
At the same time the scheduler analyzes loads of static
constants and makes use of previously loaded constants
that are close in value.
Memory description file
The memory description file is used to instruct the linker
where to place object modules in the R3DDD memory map.
It tells the .linker what address classes are legal, what
addresses exist within those classes, and what addresses
should be written to output files. The file consists of a

sequence of class specifications (CODE, DATA, etc.) and
associated address ranges.
Linker
The linker combines separately assembled program files
into one object module. Command line switches may be
used to override the memory description file.
The format of object code produced by the assembler in
IOTlc is not compatible with the format produced by the
MIPS assembler, so modules compiled by the MIPS software cannot be linked directly with modules compiled by
IOTIc. Recompilation under IOTlc is required. Files produced by IOTIc can be run and debugged under the IOTlsim
monitor.
There are three types of output file formats supported: SRecords, hex, and binary image. The S-Record files are
useful in down-loading to target boards. The hex format file
is useful for EPROM programming because the code can be
divided into multiple files under this format.
The linker output can be disassembled back into a listing
file and map that includes all object modules at their correct
finallocations..in memory.
Endianess
IOTIc includes a switch so that code may be compiled in
either Big-endian,Or Little-endian format.
Floating Point Library
IOTlc may be ordered with a floating point library. A
switch in the compiler is set at compile time to determine
how the compiler should handle floating point instructions.
In the normal mode, it will produce R3D1D Floating Point
Accelerator instructions in the object code. If the switch is
set the other way, the compiler will insert calls to the floating
point library instead, and the floating point library must be
available at link time. Because the compiler knows about
the library during compile time, it can perform optimizations
not otherwise possible and keep the execution penalty for
using software instead of hardware to about a factor of 4 in
very floating point intensive code.
Librarian and Archiver
IOTIc supports object code library files. Many compiled
routines may stored in a single library file by using the
Archiver utility. At link time, the linker extracts only the
routines actually used. This technique reduces the number
of files that must be dealt with explicitly during program
development.
PROM-C
PROM-C is a utility included with IOTlc that permits
variables initialized by the program to be moved from their
normal locations in the object code into designated memory
space destined for EPROM. The user program can execute
a simple routine at start-up to move the variables from
EPROM back into RAM space at the appropriate locations.

UPDATE1 C

57

BI

I

IDT7RS903

Data Book C, Section 8.10, Page 3

r~~t~;-------------

--------------------.

:

GNU Complier

,

'",I

~
~

!,
~
~

!,

:,
:,

:~ .......~................................. ~ ... :;. ................................. ..".
I
:. _________ ...:~_:.. __ .. __ ..... .................................. _......... 1

S-records

.sre

PROMC
EPROM

formatter

.to Download

,IDT/cFlow

UPDATE1 C

58

IDT7RS903

Data Book C, Section 8.10, Page 4

OPTIMIZATION PASSES

PERFORMANCE COMPARISONS

Multiple optimization passes are performed by the GCC
compiler. Below is a brief description of what takes place on
each pass. Note that switches can be used in the compiler
to turn individual optimization choices off or on, providing
the programmer with a great deal of control over how the
compiler modifies the code .
.Jump optimization
Simplifies jumps to the following instruction, jumps across
jumps, and jumps to jumps. Oeleties un referenced labels
.
and unreachable code.

Execution
To obtain a measure of the efficiency of the IOT/c compiler, a set of benchmark programs was compiled under
both IOTIc and the MIPS compiler, and the size and execution
time of the resulting binaries were compared.
Execution Time Comparison
Code Size
Exec. Time
1.0
1.0
Complied with MIPS C
1.20
1.19
Complied with IOT/c

Register Scan and common subexpression elimination
Finds first and last use of each register for purposes of
subexpression elimination while performing constant propagation.

Loop optimization and strength reduction
Moves constant expression code outside of dynamic
·Ioop.

Data flow analysis
Oivides the program into basic blocks and identifies the
life of values in registers. Code producing unused results
and unreachable loops are eliminated.

Local. register allocation
Allocates registers to be used inside each basic block.

Global register allocation

Compile Time
The time required to compile a program under IOT/c
depends on the machine speed, type, and configuration.
For comparative purposes, the Stanford benchmark was
compiled under a variety of hosts and the results are shown
below. For reference, the same program was also compiled
using the. MIPS compiler.
Compile Time Comparisons
' Compile Time
Host
24 sec.
MIPS C on MIPS Machine
IOTIc on MIPS Machine
25 sec.
695 sec.
IOTIc on 10 MHz 286, MS-DOS
IOTIc on 25 MHz 386, Xenix
70 sec.

Assigns' registers for values which live across basic block
boundaries.

Final Pass
The final pass is to generate assembler code. At this
point, peephole optimizations are performed as' well as
generation and optimization of the function entry arid exit
code sequences.

UPDATE1C

59

IDT7RS903

Data Book C, Section 8.10, Page 5

COMMAND LINE SWITCHES
-E:

Pre-process only..S file is expected. Preprocessed file is written to the standard
output.

-0 : .

Optimize (GNU cc -0 option).

-01:

Optimize even more (GNU cc options: fstrength-reduce -fforce-addr -fforce-mem
-fcombine-regs -finline-functions).

-c:

Assemble only, do not link. 'Expected are
filenames with .s or .S suffixes. OutpLilfiles
(in absence of -0) will have .0 suffix.
Produce assembly listing.

-0 xxx:

Name output file. The default output name
is 'out.sre'.

-Fxxx.xxx:

Included for MIPS asm compatibility but ign o r e d . : ) .'

.extern name

Import symbol 'name' that refers to n bytes of
storage. (included forMIPS asm compatibility and ignored). .
. .

.globl name

Export defined symbol.

.half arg

Assemble arguments into consecutive
halfwords.

.set argument

Argument can be :

at - error flag every use of $1.
noat - disable errors due to user's usage of $1 (at).

-ZA:

-ZL:

.ent name

. reorder - enable scheduling to resolve pipeline conflicts.
.
noreorder - disable scheduling:

Produce link map.
Use xxx.xxx as memory layout description
file. In absence. of -F option the default is to
use file idt.mem in defauH library directory.

-ZThhhhhhhh: Specify text loading address; hhhhhhhh is
address in hex, up to a.hex digits. This will
. override .mem file definitions.

.spacen

Skip next n bytes, advancing location counter
by n.

•text

Store following into text section .

.word arg
SEGMENT

Assemble arguments into consecutive words.

-ZDhhhhhhhh: Specify data loading address; hhhhhhhh is
address in hex, up to a hex digits. This will
override .mem file definitions.
-e name:

Use global 'name' as program start address.

-noenv:

Do not include default library modules which
define the order of program sections and
global symbols that point to beginning and
end of text, data and bss.

-nostdlib:

Do not include library for linking with I DT/sim
monitor.

The SEGM ENT directive selects the address
.segmentwherethefollowingcodeordatawill
be stored. It is used to implement '.text',
'.data' and '.bss'which'are MIPS compatible
segments. Using this directive the user can
create other custom segments..

FLOATING POINT EMUL~TION
The floating point emulation library provides routines to
perform the functions listed below.
Single and Double Precision Add
Single and Double Precision Subtract
Single and Double Precision Multiply
Single and Double PreCision Divide

ASSEMBLER DIRECTIVES

Single and Double Precision Compare

.allgn n

Single and Double Precision Float to Integer Conversion
Integer to Single and Double Precision Float Conversion

Align so that n least significant bits of address
are O.

.ascll "string" Assemble string.

Single to Double Precision Conversion

.bss

Double to Single Precision Conversion
ASCII to Single and Double Precision Binary

Store following into bss section.

.byte arg, ... ,argAssemble arguments into consecutive bytes.
.data

Store following into data section .

.end name

Included for MIPS asm compatibility but
ignored.

Single and Double Precision Binary to ASCII

UPDATE.1 C

60

IDT7RS903

Data Book C, Section 8.10, Page 6

ORDERING INFORMATION
The IOT/c C·CompiJer is an efficient R3DDD C-compiJer system based on the popular GNU C and hosted on a variety
of computers. The IOT/c system includes the compiler, assembler, scheduler and linker. All PC versions of the software
are shipped with both 1.2 MB floppy discs and 1.44MB 3.5" diskettes. A "boxtop" single user license is included with the
product. Contact your lOT sales office for multiple user licensing.

Media, without Floating Point
The software listed below does not include the floating point library.
For 286 machine, MS· DOS ........................................................................................................7RS903BAF-N
Not recommended for large, complex programs. At least 2MB RAM recommended. Requires DOS version
3.3 or greater.
For 386 machine, MS-DOS ........................................................................................................7RS903BBF-N
This product uses extended memory space on the 386. 4 MB recommended.
For 286 machine, SCO Xenix ....................................................................................................7RS9D3BYX-N
For 386 machine, SCO Xenix ............... ;....................................................................................7RS903BXX-N
For MIPS machine RISC/os, on QIC-24 TAR Tape .................................................................7RS903BUU-N
. For MacStation, on Macintosh Disc ........................................................................................7RS903BMD-N
Runs on MacStation R3000 board under IDTlux.
For SUN Sparcstation, on QIC-24 TAR tape ........................................................................... 7RS903BWU-N

Media, with Floating Point Library
The software listed below includes the floating point library.
For 286 machine,. MS-DOS ......................................................................................................7RS903FBAF-N
Not recommended for large, complex programs. At least 2MB RAM recommended. RequiresDOS version
3.3 or greater.
For 386 machine, MS-DOS ......................................................................................................7RS903FBBF-N
This product uses extended memory space on the 386. 4 MB recommended.
For 286 machine, SCO Xenix ..................................................................................................7RS903FBYX-N
For 386 machine, SCQ Xenix ..................................................................................................7RS903FBXX-N
. For MIPS machine RISC/os, on QIC-24 TAR Tape ...............................................................7RS903FBUU-N
For MacStation, on Macintosh Disc ......................................................................................7RS903FBMD-N
Runs on MacStation R3000 board under IDTlux.
For SUN Sparcstation, on QIC-24 TAR tape ......................................................................... 7RS903FBWU-N

Floating Point Upgrade
The version of the compiler without floating point may be upgraded to the version with the floating point library. To upgrade,
contact your lOT sales office and give them the order code and serial number of your original software.

Maintenance
Maintenance ..................................................................................................................................7RS903BSY
Includes free upgrades for one year and direct telephone contact for support

UPDATE1C

61

IDT7RS905

Q.
~

Data Book C, Section 8.12, Page 1

IDT/fp
FLOATING POINT LIBRARY
For use with MIPS C-Compiler

IDT7RS905

IDtegrated DevIce Technology. Inc.

FEATURES:

DESCRIPTION:

• Allows use of floating point operations
without requiring a floating point chip in
system
• Requires no changes to C source code
• Floating point code can be linked to application or OS; does not require UNIXTM
• License includes binary distribution rights
• Conforms to IEEE 754 format

Object Code
from
MIPS

c-compller

The IDT7RS905 product is an IEEE-754 compliant float.ing point arithmetic library for use with the MI PS C-compiler.
It is used as a substitute for instructions normally requiring
the presence of a floating point accelerator (FPA), and
eliminates the need for that device. The software consists
of a pre-processor called Post Float, and a library which
contains software to duplicate the FPA's floating point
instruction set using only integer arithmetic. The Post Float
pre-processor reads object code from the MIPS C-compiler,
and substitutes calls to the library for each FPA instruction
encountered. The library is then linked with the modified
object code to produce an executable file that does not
require an FPA.
The library includes the basic single and double precision
arithmetic functions (add, subtract, multiply and divide) as
well as conversion routines between different precisions,
integer and ascii formats. The IEEE~754 single precision
floating pointformat represents numbers rangingfrom±1.2E38 to ±3.4E+38 with 24-bit mantissa precision. The double
precision format offers a range of±2.2D-308 to ±1.8D308
with a 53 bit mantissa. The accuracy of the floating point
library is within one least significant bit. The IEEE floating
point format defines special representations for underflow
(result = zero), overflow (result = + INF or -IN F), and invalid
operation (result = Not a Number, NaN). The floating point
library adheres to the IEEE~754 error handling procedure in
all applicable cases.

POST FLOAT

Filters R3010
Instructions;
substitutes calls

IDT/fp
MAY 1991

704-00905-001/8
e1991 Integrated Device Technology. Inc.

1JSC.«l44I.

UPDATE1 C

62

IDT7RS905

Data Book C, Section 8.12, Page 2

SUPPORTED OPERATIONS
Addition

FPADD(a,b) & DPADD(a,b)

FP to Integer

FPINT(sp) & DPINT(dp)

Subtraction

FPSUB(a,b) & DPSUB(a,b)

DPto SP

DPTOSP(dp)

Muttiplication

FPMUL(a,b) & DPMUL(a,b)

SPto DP

SPTODP(sp)

Division

FPDIV(a,b) & DPDIV(a,b)

ACSlIto FP

FASCBINO & DASCBINO

Comparision

FPCMP(a,b) & DPCMP(a,b)

FPtoASCIl

FBINASCO & DBINASCO

Integer to FP

FPFLT(int) & DPFLT(int)

ORDERING INFORMATION:
The IDT/fp package consists of the Post Float filter for the MIPS C-compiler and the floating point library. The product
is shipped with a single-user license which permits unlimited distribution of binary applications which have been linked with
the floating point library.

For use with MIPS C·compiler ................................................................................ 7RS905BUU-N
Maintenance ......•..........................................................................................................7RS905BSY

One year free updates

UPDATE1 C

63

UPDATE1 C

64

1991 Rise DATA BOOK

New Data Sheets and App. Notes

The following section contains important new data sheets
and application notes that were not included the 1991

RiSe Data Book.

UPDATE1 C

65

4(;)"

APPLICATION
NOTE
AN-8S

SRAM TIMING
PARAMETERS FOR 40 MHz
R3000A CACHE DESIGN

Integrated Device Technology, Inc.

by Satyanarayana Simha
The IDT79R3000Ais a RISC microprocessor which is used
in a variety of applications ranging from low-end embedded
controllers to high-end workstations. Currently, the R3000A
operates at a frequency of up to 40 MHz. This technical note
specifies the timing parameters for SRAMs to function as
cache for a 40 MHz R300.
Figure 1 shows a block level diagram of the R3000A with its
four clock inputs coming from a delay line. Table 1 shows a
summary of the delay line settings to be used for a 40 MHz
R3000A. Please note carefully that Clk2xSys is taken as
the zero time reference and comes from the first tap of the
delay line. The other 2x clocks lag Clk2xSys in time and
follow it with respect to delay line taps.
The design of the cache subsystem for the R3000A is
straightforward. Industry standard static RAMs function as
cache. The timing equations derived take into account the
effect of capacitive loading on the bus. The derating factors
are calculated based on certain assumptions. The deratings
due to the capacitive loading on the address, data and control
signals are assumed to be 2 ns each. Figure 2 shows a typical
R3000A based system. The cache comprises of fast 16 K X
4 static RAMs i.e., the IDT7198. The AdrLo busofthe R3000A
goes through a latch: the FCT373C.

IDT79R3000A
Clk2xSys
Clk2xSmp

Clk2xPhi

Figure 1. Four-phase clock input to the R300DA

40 MHz

Parameter

Clk2xSys

0

Clk2xSmp

4

Clk2xRd

4

Clk2xPhi

8

Table 1. Delay line settings for a 4D MHz R3DDDA

Data
Cache

Instruction
Cache

Adrlo

1...- - - - - 1 IClk

15 X

OE f - - - - - - - I IRdl
WE
iWr1

DClk 1 - - - - - ' " 1

DRd11------tOE
DWrl
15X

IDT79R3000A
Processor

IDT7198
(16KX4)

WE

IDT7198
(16K X 4)

FCT240

SysClk

Figure 2. Block level diagram of a cache subsystem with the R3DDDA using IDT7198 16K X 4 to function as cache.
(The R3D1D is not shown in this Figure)
101991 Integrated Device Technology,lnc.

UPDATE1 C

66

APPLICATION NOTE AN-8S

SRAM TIMING PARAMETERS FOR 40 MHz R3000A CACHE DESIGN

Figure 3 show the timing diagrams of the R3000A when
performing a data store followed by an instruction fetch. This
is the worst case example and is chosen to determine the
SRAM parameter requirements. The encircled numbers represent the equations presented in section 4.4. The timing
diagram in conjunction with the equations are used to determine the timing requirements.
The following equations are used to determine the timing
parameters for the static RAM so that they can function as
cache for a 40 MHz R3000A. The numbers at the left
correspond to the encircled numbers in the timing diagrams.
Equations 9 and 10 are not shown in the timing diagram but
are included for completeness. The equations also use some
R3000A parameters. These are listed in Table 2. The SRAM
specifications are given in Table 3.

The cache format of the R3000A is comprised of 60 bits: 32
bits of data, 4 bits of data parity, 20 bits of tag, a valid bit, and
three bits of parity to cover the tag and the valid bit. With this
requirement, it is clear that for the instruction cache, 15
IDT7198s (16K X4 SRAMs) are needed. The same number
is also required forthe data cache. This means that there are
a total of 30 SRAM devices forthe cache.

Timing equations for cache design
This section deals with the timing equations that enable us
to determine the critical timing requirements of the static RAM
that will be used as cache. These equations are based on the
use of static RAMs (without built-in latches) as cache RAMs.
The superscript 'd' in the following equations denote the
de ratings to be taken into account. The static RAM chosen for
illustration here is a 16K X 4 IDT7198. The board is assumed
to be surface mount for the 40 MHz R3000A. All calculations
are based on the 40 MHz R3000A specifications.

25ns Cycle Timing
phi
AdrLa

phi

STORE (h
p ase 2)

~

phi

FETCH (h
p ase 1)

IADR

I

DADR

~

2

4.7

8+2

d

4

CD

AdrLa d+ 373 PO + RAM AA + os

RAMau!

KXZ)

samp

3.5

1

samp

20.7 (21)

READ:

CD

3.5(4)

 teyG12 - tsys-smp - tOVaI - tovaP - twP

This equation is used to determine the Address Access
time parameter requirements of the static RAM. From the
timing diagram of Figure 4.9, it is easily calculated .. As an
example, let us calculate the address access time for a 33
MHz R3000A. The total cycle time for a 33 MHz R3000A is 30
ns. Ifthe processor's sample time requirement is met the time
remaining in the cycle is 24 ns in which the data has to be
presented to the processor. The processor requires a data
setup time of 4 ns. There is also a propagation delay through
the latch for the address bus. For the 33 MHz part, a fast
FCT373C is used because it has a maximum propagation
delay of 4.2 ns. The derating factors due to the capacitance
and the trace length have also to be taken into account. Using
all these factors, the equation is
tRAMAA:!> teye - tsmp - tos - t373PO - tAdrLod - tRAMAAd

40 MHz R3000A: tRAMAA:!> 25 - 4 - 4 - 4.2 - 2 - 2
tRAMAA:!> 8.8

Cache Enable to Sample
This equation is used to determine the system output
enable(toEs) requirements of the cache RAM. This should
meet the processor's setup specification. The output enable
time (tOE) specifications for the RAM is tested for a voltage.
change of 200 mV (a fall from 1.732 V to 1.532 V for IDT
RAMs). For a system, however, the voltage falls from approximately 3.3 V to 1.5 V. This fall time is usually a nanosecond.
Therefore, the RAM specifications should take this system factor Into consideration and specify the output
enable time at least one nanosecond lower than the
calculated. timings.
tOES:!> teyG12 - tRod - tos - tsys-smp + tsys-rd - tOESd
40 MHz R3000A: tOES:!> 12.5 - 2 - 4 - 4 + 4 - 2
tOES:!> 4.5

Minimum Read Pulse Width
This timing requirement guarantees that the read pulsewidth generated by the processor is at least as long as the
cache RAM output-enable time.
.
tOES:!> teyG12 - tsys-rd - tOEsd

40 MHz R3000A: tRAMOS:!> 12.5 - 4 - 2 - 2 - (-1)
tRAMOS:!> 5.5

Data Hold from End of Write
This parameter requirement guarantees that the data hold
from end of write of the cache RAM is met when the processor
or the read buffer is writing to the RAMs.
tRAMHO:!> fsmp-rd + tRAMLZ
40 MHz R3000A: tRAMHO :!> 0 + 2
tRAMHO:!> 2

Data SetUp to SysClk
This timing parameter ensures that the setup time into an
external register (for the main memory interface) is sufficient
enough forthe case when the processor is doing a store. The
data is clocked in the register on the rising edge ofthe buffered
SysOut* (through an inverting FCT240A). In this equation,
tsys(min)d is used to insure worst case calculations.
tsetupSys:!> teyG12 - tsys - tOVal - tovaP + tsy~ + t240POmin
40 MHz R3000A: tSetUpSys:!> 12.5 - 8 - 2 - 2 + 1 + 1.5
tSetUpSys:!> 3

Data Hold from SysClk
This timing parameter is to guarantee that the hold time
specification for an external register is met on a processor
store. In this equation the minimum value of tRod is taken to
insure worst case numbers.
tHoldSys:!> fsys-rd - tsysd - t240POmax + tRAMLZ + tR~
40 MHz R3000A: tHoldSys:!> 4 - 1 - 4.8 + 2 + 1
tHoldSys :!> 1.2

Address SetUp to End of Write
This equation enables us to determine the timing requirement for the RAM so that the address set up time is sufficient
before the trailing edge of the write pulse.
tRAMAW:!> teye - tsmp-sys - tAdrLrJi- t373PO + twP
16 MHz R3000A: tRAMAW:!> 25 - 4 - 2 - 4.2 + 1
tRAMAW:!> 15.8

Write Hold Pulse Width

40 MHz R3000A: tOES:!> 12.5 - 4 - 2
tOES:!> 6.5

This requirement guarantees thatthe cache RAMs minimum
write pulse width specification is met.

Read-Write I-Cache Data Bus Contention

tRAMPW:!> teyG12 - twrDIy

This timing requirement ensures that the RAM output is
tnstated soon enough after the instruction read signal goes
high. In the worst case, when the processor performs a store
operation, no data contention occurs.
tRAMHZ:!> tsys - tR~ + OEn
40 MHz R3000A: tRAMHZ:!> 8 - 2 + (-1)
tRAM HZ :!> 5

16 MHz R3000A: tRAMPW:!> 12.5 - 2
tRAMPW:!> 10.5

UPDATE1 C

68

APPLICATION NOTE AN-a5

SRAM TIMING PARAMETERS FOR 40 MHz R3000A CACHE DESIGN

40 MHz
Symbol

Parameter

Min

Max

Unit

Clock
TCkHigh

Input Clock High

5

TCkLow

Input Clock Low

5

TCkP

Input Clock Period

ns
ns

12.5

500

ns

Clk2xSys to Clk2xSmp

0

tcyc/4

ns

Clk2xSys to Clk2xRd

0

tcyc/4

ns

Clk2xSys to Clk2xPhi

3

tcyc/4

ns

-1.0
-0.5

ns

ns

Run Operation
TDen

Data Enable

TDDis

Data Disable

-

TDVal

Data Valid

-

1.5

ns

TWrDly

Write Delay

-

1.5

ns

TDS

Data Set-Up

4

ns
ns

ns

TDH

Data Hold

-2

TCBS

CpBusy Set-Up

6

ns

TCBH

CpBusy Hold

-1.5

ns

TAcTy

Access Type[l :0]

TAT2

Access Type[2]

TMWr

7.5

ns

Memory Write

-

9

ns

TExe

Exception

-

3

ns

TSAVal

Address Valid

-

12.5

ns

3

ns

Stall Operation

TSAcTy

Access Type Valid

TMRdl

Memory Read Initiate

TMRdT

Memory Read Terminate

TSd

Run Terminate

TRun

Run Initiate

TSMWr

Memory Write

TSEx

Exception Valid

ns

9

ns

9

ns

5

ns

1.5

7

ns

-

2.5

ns

9

ns

7.5

ns

TckP

ns/25pF

Reset Initialization

TrstPLL

Reset Timing, PLL on

3000

Trstcp

Reset Timing, PLL off

128

-

0.5

1

TRST

Reset Pulse Width

6

TckP
TckP

Capacitive Load Derating
CLD

Load Derate

Table 2. R3000A AC Specifications.*PLL: Phase Locked Loops

UPDATE1 C

69

SRAM TIMING PARAMETERS FOR 40 MHz R3000A CACHE DESIGN

READ CYCLE TIMING SPECIFICATIONS

APPLICATION NOTE AN·aS

WRITE CYCLE TIMING SPECIFICATIONS
40 MHz

40 MHz

Parameter
tRC

Min

8

Parameter

Max

-

Min

Max

twc

10

-

tCW1

10

-

-

lAw

10

-

tcLZ

2

-

lAS

0

-

tOES

-

4

twp

10

-

tOLZ

2

-

tWRl

0

-

-

4

tWR2

0

-

3.9

tWHZ

-

tow

5

1M
lAcs

tCHZ
tOHZ
tOH

8

-

tpu

0

-

tDH

0

tPD

-

15

tow

5

4

-

Table 3. Static RAM Read and Write Timings to work as cache with the R3000A.
(1) This assumes that an FCT373C with a TPD
legend:
tRAMAA tRAMOE tRAMHZ tRAMLZ tRAMHD tDS -

= 4.2 ns is used.

RAM Access Time
RAM Output Enable Time
RAM OutPut Low impedance to Output in High impedance
RAM Output in High impedance to output in Low impedance
RAM Data Hold TIme

R3000A Data Setup Time
Phase Difference between Clk2xSys and Clk2xPhi
Phase Difference between Clk2xPhi and Clk2xRd
tsmp Phase Difference between Clk2xPhi and Clk2xSmp
Icye Cycle time 01 the R3000A
tsmp·rd = tsmp - ltd
1240PD Propagation delay from Clk to Output of FCT240A
tsys -

ltd -

References:
1) lOT RISC R3000A Family Hardware User Manual, October 1988
2) lOT RISC R3000A Family Data Sheets, 1988
3) lOT RISC Data Book, 1991
4) lOT Data Book Supplement, 1989

UPDATE1 C

70

t;)

APPLICATION
NOTE
AN-8S

IDT79R305FM SYSTEM
DESIGN EXAMPLE

Integrated DevIce Technology. Inc.

by AndrewNg

INTRODUCTION
This application note describes a memory evaluation board
that is an example of many of the design considerations for
systems based on an IDT79R30S1™ RISControlierTM family
CPU.
The memory board, illustrated in Figure 1, consists of:
• An R30S1 CPU
• Reset circuitry
An address de-multiplexer
• A data transceiver
• Wait-state and memory control logic
• 128K bytes of SRAM
• 128K bytes o.f EPROM
• A dual channel UART
• A real time counter
• An interrupt controller
In addition, an expansion connector supplies all the CPU
signals for the addition of external modules such as DRAM
memory systems or other application specific 1/0 systems.
The memory and 1/0 system on the example board are
compatible with the IDT7RS382 R3000 Evaluation Board.
Thus 7RS382 software such as the IDTlsim PROM Debug
Monitor can run on the example board. The board is typical
of an embedded controller core such as for LAN adapters,
laser printers, facsimiles, and avionics applications. The
differences would appear in which peripherals are used and
memory type, size, and speed requirements.
The board was designed as a generic example of the
construction of a system using the IDT79R30S1 RISControlier
with both low parts count and cost sensitive requirements.
However, since many generalities were taken into consideration, many systems can reduce both parts count and cost

I-R3051 Family
RISControlier
CPU

rl

I
Address
Latches

Y

even further. Although the board is not populated with parts
that have the highest performance achievable, its deSign can
be easily modified to do so. In addition, PALTM support for
further experiments with optimizations and trade-offs can be
done to accommodate different kinds and speeds of memory
and 1/0. While the board is designed with SRAM for the
simplicity of a design example, the extension to a DRAM
system with CAS before RAS refresh is only slightly more
complex.

THE R3051 RISCONTROLLER CPU
The 1DT79 R30S1 family is a series of high-performance 32bit microprocessor RISControliers designed to bring the highperformance inherent in the MIPS~ RISC architecture into low
cost, simplified, and power sensitive applications.
The instruction set is compatible with the 79R3000A and
79R3001 RISC CPUs. Features of the R30S1 family include:
4kB (R30S1) to 8kB (R30S2) of Instruction Cache on-chip
2kB of Data Cache on-chip
Clocked from a single, double-frequency clock input
• On-chip 4 deep read and write buffer
On-chip DMA arbiter
• Flexible bursUsimple block bus interface
• Multiplexed address and data bus for low cost packaging,
simplicity of use
• Base versions use fixed address translation to simplify
software
Extended architecture versions use 64-entry, fully associative Translation Lookaside Buffer (TLB) to support page
mapping and virtual memory
The R30S1 RISControlier combines a similarly featured
R3000A CPU system consisting of over SO LSI/MSI parts into
a single integrated chip.
128K
RAM

I I

128K
EPROM

J
.-

JI

c:~

Data
Buffers

-1{Memory
Contra

00

I

·in

J

1il

~E

~8

JI

I

UART

I ICo~nter/J

~

Timer

Figure 1. System Block Diagram
The IDT Logo. R3051, and RISController are trademarks of i~tegrated Device Technology, Inc.
MIPS and R3000 are trademarks of MIPS ColT1Juter Systems, Inc. PAL Is a trademark of AMD.

4191

4:11991 Integrated Device Technology,lnc.

UPDATE1 C

71

IDT79R3051"" SYSTEM DESIGN EXAMPLE

APPUCATION NOTE AN-8S

DETAILED DESIGN REVIEW

Tri-State (Slnt(1)) is active during the reset vector, it is helpful
to an ATE programmer to be able to tri-state the inverter.

The following sections give a detailed review of how each
functional block relates specifically to designing with the
R3051 RISControlier. Particular attention is focused on
alternative design strategies that could reduce parts count
and improve performance as well as on a description of the
original design. The subsystem block designs include:
Analog reset logic
A PAL-based memory controller (3x PALs)
Address de-multiplexer (4x IDT74FCT373T)
• Data transceiver (4x IDT74FCT623T)
• 128kB of SRAM (4x IDT71256 32kx8 45ns SRAM)
• 128kB of EPROM (4x 27256 32kx8 125ns EPROM)
• 68681 DUART
8254 Timer
Interrupt controller (1 x PAL)
• Off-card connector
Reset, Reset Vector, and Clock Buffer Circuitry
The Reset signal is based on a linear integrated circuit, a TI
TL7705A supply voltage supervisor with a Power-On Reset
Generator. A 1 IlF capacitor is used to program the reset
generator for a 13 ms Reset period.
Note that because the R3051 synchronizes the Reset input
signal internally, an RC circuit can be used instead. An
example is to pull Reset high with a resistor of about 10K
Ohms, tie Reset to a 221lF capacitor which is tied to ground,
and tie Resetto a push button switch that is tied to ground. The
example board can be reprogrammed and populated to experiment with Reset.
Certain configuration options (the reset vector) are selected in the R3051 by using the interrupt pins at the rising
edge of Reset. On the example board, the interrupt pins are
simply pulled up (or down) since Slnt(2:0) are not used in this
system (software can permanently mask these interrupt inputs
in the Status Register). However, if they are used (via the
expansion connector) they would need to be multiplexed with
the reset function. There are a number of techniques to
perform this multiplexing:forexample, if the interrupting agent
is not capable of tri-stating its interrupt during Reset, an external multiplexer such as an IDT74FCT257T can be used,
with the enable always tied active and the select tied to Reset.
If the interrupting agent tri-states its interrupt during Reset,
then using simple pull-ups or pull-downs will still operate
properly.
The clocks on the board are buffered by an
IDT74FCT240C(T) inverting tri-state buffer. This buffer was
selected partially to provide a board testability path for injecting a test clock, as well as to bufferthe signals to increase their
drive. The primary reason forthe buffer, however, is to invert
SysClk to form SysClk, the signal that is used to clock the state
machines on this board. Buffer output pins closest to the
ground pin (pins with the lowest pin inductance) were used
first to help lessen potential noise and ground bounce problems. The Clk2xln oscillator is socketed, so that the board
may be populated with different speed parts.
In this deSign, the FCT240C(T) enables are pulled down to
be active all of the time. Since SysClk does not tri-state when

Memory Controller
The example board's Memory Controller consists of three
22V10 PALs. The first PAL is used for address decoding, the
second for wait state and cycle counting, and the third for byte
enables. The PALs are functionally described in the following
paragraphs. The PAL equations are included in the appendices. The PALs are all placed in sockets, and thus can easily
be reprogrammed for various experiments.
Address Decoder
The Address Decoder PAL, MEMDEC.JED, uses Address(31 :17) to generate chip selects. The chip selects are
decoded according to the 7RS382 address map as described
in the 7RS382 Hardware User's Guide. Three spare I/O pins
are provided, which could be used to decode additional chip
selects. These spare outputs are in place of the 'USER
CS1 X" chip selects provided for on the 7RS382 board, but not
explicitly supplied by this example board.
The address decoder does not wait for ALE to begin
generating the chip-select outputs. It does this so that
maximum performance may be achieved, since the Chip
Select outputs will be generated earlier in the transfer. However,
as a result, the CS outputs may tend to "glitch" as a valid
address is driven. Thus, the Read Enable and Write Enable
seen in the memory system must be synchronized so thatthey
are valid only within the time that the CPU is attempting a read
or write transfer. This combination allows maximum performance: address and chip enables are seen early in the
transfer, but the Read and Write signals are generated synchronously to insure proper system operation.
One of the extra I/O pins can be used as a test enable input
to tri-state the outputs for board level ATE. Some systems will
not need to decode as many address bits or may have a fixed
map, and thus may able to use FCT138's or 16V8's to do the
address decoding instead of the relatively expensive 22V1 0
part.
Memory Cycle Controller
The purpose of the Memory Cycle Controller is to provide
a wait-state generator which stalls the R3051 's Bus Interface
Unit, so that various types and speeds of memory can be
used. The Memory Cycle Controller is implemented with a
22V10 PAL called MEMCONT.JED. Note that this PAL was
selected in order to make the PAL equations more readable.
A lower cost solution may implement the state machine in two
16R8 PALs.
The Memory Cycle Controller allows various speeds of
memory devices to be used, by using the throttled read
supported by the R3051 bus interface. Other kinds of transactions are treated as simplified cases of the throttled read.
The basic state machine looks forthe start of a read orwrite
transaction by looking for an asserting edge of Rd orWr. When
a transaction is begun, the state machine starts a 5-bit binary
up counter, C(4:0). C(4:0) then increments on each SysClk
rising edge. C(4:0) is used as the basic timing master for all

UPDATEl C

72

APPLICATION NOTE AN-86

IDT79R3051"" SYSTEM DESIGN EXAMPLE

disable time is long relative to the system clock frequency.
Other outputs from the. Memory Cycle Controller PAL
include the R3051 transfertermination inputs RdCEn, Ack, and
BusError. On a read transfer, Burst and one of the Chip Enable inputs from the Address Decoder are used to determine
the timing and quantity of RdCEn signals to be assertedforthis
transfer (according to the requested transfer size and the
memory device speed).
Ack is asserted at the end of a write cycle to indicate
completion of the transfer, and optionally towards the end of
a Quad Word (Burst) read cycle. A description of the various
kinds and options of read and write cycles is thoroughly
explained in the R3051 Family Hardware User's Guide. The
number of cycles before and between the assertion of Ack and
RdCEn is programmable, allowing flexibility for various types
of memories. =--=_
Finally, the Bus Error output is used to end an undecoded
memory cycle. In the R3051 , Ad is negated one-half cycle
after the Bus Error input is asserted.

of the other control signals generated in the state machine.
In the memory scheme used here, rather than search for
the negating edge of Rd or Wr at the end of the transaction, a
CycEnd synchronous decoder is used to tell the C counter
when the end of the memory cycle occurs. This type of
strategy is used because the de-asserting edges of Rd and Wr
occur within the setup and hold times of a buffered/inverted
(FCT240C(T)) SysClk. Typically, the de-asserting edge of Rd,
Wr, and Burst should not be used to control a SysClk based
state machine. Similarly, the rapid negation of ALE by the
processor makes it difficult to synchronously sample ALE
when using a state machine driven by a buffered clock.
CycEnd serves to synchronously reset the state machine
when a de-asserting Rd or Wr edge is expected, whether or
not the Rd or Wr de-asserting edge meets the setup and hold
times of the state machine. Another output, EnStart is used to
start the byte enables by waiting a number of cycles before
asserting. The amount of time the transfer waits is used to
allow drivers used in the previous transfer to tri-state, and may
be necessary in systems which employ devices whose output

SysClk

C(4:0)

/

\

Wr

X

0

X

X

2

Ack

EnStart

X
\

3

X

0

/
/

\
\

CycEnd

/

Figure 2. Timing of CycEnd

Other ~pproaches
Of course, alternative methods and techniques to memory
interfacing with an R3051 family CPU exist. Four approaches
easily implemented in discrete components include:
• using a SysClk based CycEnd counter (as used in this
example)
• using asynchronously resettable registers for the counter
• using interlocking SysClk and SysClk registers
• using an unbuffered SysClk
All of these methods can be used to design forthe clocking
scheme of the R3051 Family, which uses both the rising and
falling edges to control its outputs. The use of both edges of
the clock allows the R3051 to mitigate the 1 clock intertransaction latency that is associated with most other CPUs
that need the extra clock to fixup and start new memory cycles.
However,because the R3051 Family asserts and de-asserts

its edges the same way on both Rd and Wr cycles, specific
methods can be employed so that the memory system is
always clocked from one edge of SysClk. An example of this
is the CycEnd method used on this board, which ignores the
edges that are not synchronized with the state machine.
Although traditional high-performance CPUs require complex
state machines to operate efficiently, the beauty of the R3051
family is the simplicity of its interface. Memory control state
machines for the R3051 family are really only minor variations
on traditional wait-state machines, and can also easily take
advantage of the 1/2 clock inter-transaction savings provided
by the CPU interface.
Each of the four approaches has advantages as well as
drawbacks relative to each other. The following paragraphs
will give a brief description of each technique. Each of the
methods could be used by themselves or combined with one

UPDATE1 C

73

IDT79R3051'M SYSTEM DESIGN EXAMPLE

APPUCATION NOTE AN-06

or more of the other methods, to achieve the optimal price/
performance/parts count for a given application. Systems
employing dedicated interface chips (such as the IDT R372x
family, orcustomer specific ASIC or Gate Array devices), may
choose to make different trade-offs than those using discrete
component based solutions.
Using SysClk and generating a Cycle End Indicator
The SysClk based CycEnd approach as described above
is straightforward because of its similarity to traditional waitstate machines. As mentioned above, it does not require the
terminating edge of Rd or Wr to complete a transaction.
The system implemented in this design example is limited
in speed by:

o hold time on the

registers as well as a 2 nsec minimum
propagation delay time to meetthe R3051 timing requirements
(note that using a buffered SysClk instead of the unbuffered
version would require negative hold time on the registers).
Despite these restrictions, some PALs can be found that meet
all of these requirements. This approach leads to a one cycle
latency in reacting to R3051 output assertions. An asserting
Rd or Wrwould be seen a clock too late to bring RdCEn or Ack
low during their first possible sampling clock. Using an
unbuffered SysClk has a speed advantage over the other
techniques:
tclk >= tpalco + t3051 setup + tcap + !wire
tclkl2 >= t3051 prop + tpalsetup + tcap + !wire

tclkl2 >= t240 + tpalco + t3051 setup + tcap + twire
which works out to 28 MHz for a 10 nsec 16V8, over 40 MHz
fora5 nsec 16R8 PAL, and 33 MHz for a 10 nsec 22V10 PAL.
Using Asynchronous Reset to terminate the Cycle
Counter
The second potential method, which uses an asynchronous reset to terminate the cycle, requires AND'ing together
Rd and Wr into the the reset line of the counter C(4:0) and can
be demonstrated by reprogramming the PAL on the example
board. The reset-to-valid output, reset width, and the reset
recovery time to clock are among the speed limiting paths in
this approach when implemented in PALs. Unfortunately, the
reset-to-output delay of a PAL is usually less optimized and
relatively slow.
tasyncreset <= tclkl2 - trdn - tcap - twire
For example, a 20 MHz system would require a reset-tooutput delay of 17ns, which can be found in a 10 nsec 22V1 0
PAL (with a 15 nsec reset to valid output data time).
Using interlocking PALs clocked on opposite edges
The third potential approach uses a SysClk based register
to detect asserting edges and a SysClk based registerto detect
de-asserting edges. The outputs of each of the PALs interlock
by controlling the outputs of the other PALs. This allows the
flexibility of seeing all edges and being able to control outputs
optimally by using any 1/2 clock edge (such as output enables).
Such an approach obviously requires more PALs, and is
somewhat speed limited by:
tclkl2 >= t240 + tpalco + tpalsetup + tcap + twire
which works out to 20 MHz for a 10 nsec 16V8 PAL.
In systems using chips designed specifically to interface to
the R3051 family (such as the IDT R3721 DRAM controller),
this approach is simpler to implement and leads to the highest
levels of performance.
Using an unbuffered SysClk
__
The fourth potential approach uses an unbuffered SysClk
based state machine. This leads to the requirement of having

which can support designs of 35 MHz for a 10 nsec 16V8 PAL
and well over 40 MHz with a 7.5 nsec 16R8 PAL.
An additional consideration relative to using an unbuffered
SysClk is the amount of loading placed on the clock, and the
impact of additional loading on R3051 AC parameters. Of
course, when using a single chip memory controller such as
the IDT R3721 or a customer designed ASIC, these loading
considerations are minimal.
In summary, the R3051 Family uses both edges ofthe clock
to assert control signals in order to reduce inter-transaction
delay between external bus cycles. However, by using one or
a combination of the above techniques in a design, a traditional wait-state machine can still be used with the addition of
only minor variations.
Read and Write Enables
The Read and Write Enables PAL, MEMEN.JED, uses
EnStart and CycEnd to control the initiation and length of the
output enable and write enable assertions. Ad andWrare used
to select between read and write cycles. Note that it would
have been possible to combine individual bank selects with
the address decoder PAL, rather than use a distinct PAL to
control the timing of the assertion of Write and Read Byte
Strobes.
On read cycles, RaEii is asserted as the system's primary
output enable signal. Ad DataEn is used to enable the FCT623T
data transceiver bank. RdDataEn in most systems would
simply be 'DataEn' as supplied straight from the processor.
This system provides RdDataEn in case other transceiver
banks are added to the system.
The byte enables are used to support partial word writes
which are used during byte, halfword, and tri-byte operatio~.
Write cycles combine the byte enables, BE(3:0), with Wr,
EnStart, and CycEnd to form the write enable outputs
WrEn(D:A) which are attached to the byte banks within the
memory system. Whether or not the system is Little or Big
Endian, WrEn(A) is alwaysattachedtothe LSB. WrEn(D:A) can
also be implemented· using an FCT257T multiplexer.
WrDataEn is used to control the FCT623T data transceiver
bank and must be held extra long to provide memory data hold
time.

UPDATE1 C

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IDT79R3051 Th1 SYSTEM DESIGN EXAMPLE

APPUCATION NOTE AN-86

Finally, the Byte Enable PAL also has a synchronized
PowReset output called ReSet and a "guarded" GUARTCS. The
guarded chip select, GUARTCS is an example of interfacing
R3051 signals to a Motorola-type 110 Device as opposed to an
Intel-type 110 Device.
Motorola-type devices multiplex their read/write input pin
and expect a data strobe pin to validate the data out orto latch

\

Rd

C(4:0)

the data in, while Intel-type devices have separate read and
write strobes. Since the MC68681 DUART is a Motorola
device, the data strobe must start late and end early, so that
readlwrite is held throughout that period. Additionally, the
MC68681 uses its chip select pin as a data strobe. As a data
strobe, it is important not to have decoder glitches on the chip
select since reads in 110 devices are often used to update

X

0

/

X

X

X
\

2

RdCEn

X

3

/

/

\

EnStart

0

\
\
\

CycEnd

RdEn

RdDataEn

/

/

/

Figure 3. Timing Diagram of RdEn

SysClk

\

Wr

C(4:0)

X

0

/ \

X

X

2

\

Ack

En Start

X

\
\

CycEnd

\
/

WrEn (A)

WrDataEn

3

X
/
/
/

0

X

x

/
\

Figure 4. Timing Diagram of WrEn(A)

UPDATE1 C

75

APPLICATION NOTE AN-86

IDT79R305F" SYSTEM DESIGN EXAMPLE

Wr

C(4:0)

\~--------------------------~----X'--_O_-IX'-__---'X'-__2_-IX'-__3_-IX'-__4 _...JX,-_5__
\~----------------------

GUARTCS

\~----------------------------\~----------------Figure 5_ Timing Diagram of Start of GUARTCS

Wr

C(4:0)

X'--_6_---JX

1 \
X

7
0
L _ _ _...J L _ _ _ __

\'---'-----'/
1
1
GUARTCS

----------~----~;------------'1
Figure 6. Timing Diagram of End of GUARTCS

UPDATE1 C

76

IDT79R3051'" SYSTEM DESIGN EXAMPLE

APPLICATION NOTE AN·U6

FIFO pointers. Thus, the guarded GUARTCS uses EnStart
and CycEnd to shorten up UARTCS. Finally, WrEn is provided to extend Wr to allow additional data hold time at the end
of the write cycle. WrEn could easily be inserted with another
OR term into WrEn(A).
Address Latch and Transceiver De-multiplexer
. The address latch bank consists of four FCT373T 8-bit
transparent latches. ALE is used for the latch enable on the
FCT373T's. The transparent phase allows extra address
decoding time during the time that ALE is high; the outputs of
the latches are fed directly to the address decode PAL and to
the memory devices. In order to insure that address hold time
to the latches are met, it is important to take care with the use
of the ALE signal. The number and length of the ALE traces
is critical and should be kept to a minimum.
Rather than use FCT373's, DRAM systems may want to
use FCTB21's or FCT823's, which are wider latches. RAS/
CAS address multiplexing can be performed by sequencing
the output enables of the latches and having the outputs of the
latches tied together and driving the DRAM address bus.
The data transceiver bank on the example board uses four
FCT623T 8-bit transceivers. FCT623T's were chosen over
the similar 10-bit FCTB61's and 9-bit FCT863's simply to
reduce pin count. The FCT861/3's provide a more conventional interface, since both output enables are active low,
instead of one enable active high, and the other active low as
in the FCT623T's. However, since this system uses PALs to
control the transceivers, the use of FCT623's poses no
additional complexity to the design.
.
FCT623T's were selected instead of FCT245's because of
the ease of interfacing to dual output enable pins instead of a
direction and enable pins as in the FCT245. Interfacing with
FCT245 controls would ideally require that the direction control only be changed when the output enable is disabled. This
requires extending a combined (latched) Ad and Wr ba~ed
signal for an extra cycle at the end of a memory transaction,
which may be the beginning of the next memory cycle. Unless
the direction pin is controlled with a SysClk based state machine, a signal like EnStart would be necessary to keep the
enable pin de-asserted in the subsequent cycle until the
direction pin control becomes valid. Some systems with high
noise tolerance, e.g., IBM-PC adapter boards, forgo the extra
cycle ideal and simply bus contend for avery short time (a few
ns) into its memory system by having the read strobe directly
control the direction. DataEn, output from the CPU, can be
used in such systems to simplify control signal generation.
When there are no pending DMA, read, or write requests,
the R3051 tri-states the ND(31 :0) bus during these non-bus
clock cycles to reduce power consumption. One can optionally
add external pullupor pulldown resistors so thatthe ND(31 :0)
bus is always defined for board level ATE and so that the input
pins of the latches and transceivers are stabilized.
Finally, systems that can output disable (oe to Z-state) all
memory readable devices within:
tdisable < tclkl2 - t3051 dataenn + taddr - tcap - twire

EPROM and Static RAM Memory
The memory on the example board is populated with 125
nsec Erasable PROMs (EPROMs) and 45 nsec Static RAMs
(SRAMs). Four 27C256 32KxB EPROMs are used to form
12BK bytes of ROM. The EPROMs are placed in sockets and
thus can easily be removed for reprogramming or replacement;
alternative designs may wish to add circuitry to allow in-board
programming of the EPROMs (e.g. Flash Era~e EP~OMS).
The EPROMs have a relatively long output disable time (oe
to z-state), typical of ROMs and thus require data b~ffers to
prevent contention on the multiplexed AD(31 :0) bus, smcethe
following equation is not met:
tclkl2 >= tdisablecontrol + tdisable - taddr + tcap + twire
In addition, the disable time for these EPROMs is long
enough that, except for relatively slow systems (under 20
MHz), extra clocks need to be added to the next bus cyc~e ~o
prevent bus contention with other memory banks. ThiS IS
determined by:
tclk >= tdisablecontrol + tdisable - tdata + tcap + twire
The SRAM bank is formed using four IDT71256 32Kx8
SRAMsfor a total of 128K bytes. The RAM chips have
common data I/O pins, separate read and write strobes, and
chip selects. RAMs without a separate read strobe (output
enable pin) may require more complex address decoding
when used in a muHiple bank configuration.
DUART, Timer, and Interrupt Controller
An MC68681 DUART and an MAX235 RS232 transceiver are
used to form two RS232 serial communication links. The DUART
control registers are word addressed, but only D(7:0) are used. The
MC68681 isanexampleofaMotorola-IypeVOinterfaceasexplained
above.
An iP8254 timer/counter chip is used for a real-time clock
or timer. The iPB254 is an example of an Intel-type I/O
interface. The iPB254's need for separate read and write
strobes matches up well with the R3051.
Software control of these chips is best described by their
respective data sheets. Typically, most software programs for
the 7RS382 have used the DUART in a polling mode and the
timer in a square wave mode. Interrupts Int(5:3) are controlled
by UARTlntOC, Timer OutB, and Timer OutA respective~y
from MSB to L$B. The 16RB PAL, called MEMINT.JED, IS
used to control these interrupts latches in the assertion
transition of the Original interrupt lines.
The controller holds the interrupt line to the processor for
Timer A and Timer B until they are acknowledged (as required
by the R3051). Acknowledgement is indicated by reading the
interrupt controller at Virtual Address BF80001 0 and BF800014
(Physical Address 1F800010 and 1F800014) respecti~ely.
This action incidentally reads extraneous data from the Timer
chip itself on D(7:0). The DUART interru~t must be acknowledged by using the DUART control registers.

might not require the transceiver bank and thus could reduce
the parts count by 4.
UPDATE1 C

77

APPLICATION NOTE AN-S6

IDT79R3051"" SYSTEM DESIGN EXAMPLE

The output disable to data in z-state time for these I/O
peripherals is relatively long, as is typical for I/O devices. This
forms the criticaitiming path forthe placement of EnStart in the
Memory Controller and Memory Enable PALs.

BusReq and BusGnt pins are not presently used on this board.
If DMA is to be used, the R3051 control outputs Rd, Wr, Burst,
DataEn, and ALE are pulled high or low so that they remain
inactive when tri-stated ..

Expansion Connector

SCHEMATICS AND PAL EQUATIONS

Two 50-pin connectors are provided which bring out the
R3051 RISControlier pins to allow off-board expansion. The

Appendices include the System Design Example Board
Schematics and the PAL equations.

R3051
PLCC-84

Ul..
1JL

RSVD(O)
RSVD(1)
RSVD(2)
~ RSVD(3)
1..§. RSVD(4)

g.

,..---.

~

~
~
~

,...--..

~

F=<

SINTNIOl
SINTN(1)
SINTN(21
INTN(3)
INTN(41
INTN(5)

BRCOND(O)
BRCOND(1)
SBRCOND(2)
SBRCONDr3\

~

~
~

0

27
26
25
24
23
20

SINTN(O)
SINTN(1)
SINTN(2)
INTN(3)
INTN(4)
INTN(5)

33 BRCOND(O)
30 BRCOND(1)
29 SBRCOND(2)
28 SBRCOND(3)

ACKN
RDCENN
BUSERRORN
BUSREON

36
35
37
34

RESETN
CLK2XIN

38 RESETN
14 CLK2XIN

ACKN
RDCENN
BUSERRORN
BUSREON

AD(O)
AD(1)
AD(2)
AD(3)
AD(4)
AD(5)
AD(6)
AD(7)
AD(8)
AD(9)
AD(10)
AD(11)
AD(12)
AD(13)
AD(14)
AD(15)
AD(16)
AD(17)
AD(18)
AD(19)
AD(20)
AD(21)
AD(22)
AD(23)
AD(24)
AD(25)
AD(26)
AD(27)
AD(28)
AD(29)
AD(30)
AD(31)

54
55

56
59
60
61
62
63
64
67
68
69
70
71
72
75
76
77
78

79
80
83
84
1
2
3
4
7
8
9
10
11

51
ADDR(2)
52
ADDR(3)
45
RDN
44
WRN
BUSGNTN 39
46
ALE
43
DATAENN
53
BURSTNIWRNEARN
47
DIAG(O)
48
DIAG(1)
40
SYSCLKN

ADIOl.,__
AQ(1)>=
AD(2IF
AD(3IF
AD(41)=
AD151>==
AD6 >=
AD 7 >=
AD 8 >==
AD 9 >==
AD 10 >==
AD(111.>=

AD(121~

AD(131.
AD114\ >==
AD(15). >==
AD(J6). >==
AD(171. >==
AD(181 >==
AD 19 >=
AD 20 >==
AD(211. >==
AD(221)==
AD(231)=
AD(24)
AD(25)
AD(26)
AD(27) >==
AD 28 >=
AD(29). >==
AD(30) >==
AD(31)

~

ADDI30~

ADDR(3)
RDN ,,-WRN >==
BUSGNTN >==
ALE >==
DATAENN >==
BURSTNF

DIAG(O)~

DIAG(1)
SYSCLKN

Figure 7. R3051 RISControlier

UPDATE1 C

78

IDT79R3051'" SYSTEM DESIGN EXAMPLE

APPUCATION NOTE AN-S6

+5V

+5V

TL7705A
7
8
SENSE
VCC
2 RESIN

RESET 6

3

RESET 5

CT

4

4.7K
SINTN(O)
SINTN 1
SINTN 2

POWRESETN
8RCOND O r 8RCOND 1 ;:=
SBRCOND 2
SBRCOND 3 ;:=

REF

REF 1

GND U32

16

16
4.7K

TO.

>==

1UF

~

4.7K

4.7K

16

Figure S. Reset Logic

> 4.7K
16

4.7K
16

~16
--'-

+5V

16
4.7K

BUSREON

Figure 9. Unused Inputs

TESTEN(4)
TESTEN(O)
+5V

.

3.6864 MHZ
OSC

r

GND

~

FCT240
VCC ~

1

~
~
~6

OEB
DAO
DAI
DA2
8
DA3
~ DBO
~ DBl
DB2
11
DB3

IOOSC

0 8

SYSCLKN
OSC

t---!

GND

VCC J.L

0 8

..t!

OSC2XIN

OAO

~

c:iAf ~
14
c:iA2 12

QA3
aBO
OBl
~

=
>=
>=

'--

~(C3)

+5V

MEMCONT.JED

4.7K

16
16
4.7K

+5V

6.

16

-±

16
4.7K

22V10

r7~~~~~--------------------lYClK

°

>-":'==="-:,..::.,:;='--________________...._1~3 IN 1
>-=~'=='~---------------------+-'lC!.jl IN9
10 INS

L_~~~----------------------+_~9 IN7
~~~~----------------------+_~S IN6
~~~~---------------------+~7 INS

~~~~~-------------------+~6 IN4
~~~~~-------------------+~5 IN3
~~~--------------__-------+~44IN2
~~~~~-------------------+~3 INl

1/091-'2"'3'--____- -...----------:-'-'R~E=S""ET!.!N>....<,
1/08 1-'2"'2~______+_---------W!..!.!..!R!:.EN"'N"'A"_<
1/071-'2 1________+---------:W
7'::!:R=EN"'N"'B:-<
1/061-'2"'0'--______+_---------:W'=':R=EN:-::N:-;:C=_.:
1/05 fJl~9~______+--------...:W'_'P.R=EN'='N"'D~:-l
1/04 f-'1"'8<--__-'-__+_-------..,.,.=-:W'-"::::R""EN"'N"-(
1/031-'1:::7________+-------"W!.!..R'-"Dc.;:;A';!;:TA;::E~N:7_<
1/02 f-'1"'6'--______+_------____'='R"'-D"'EN"'N"-(
1/01 f-'1"'5'--______+_------..!.R"'D"'D:'i'A".TA<;E~N;!,lN:7_<
1/00 r1L:!4<--______+--------=G:..::Uo.;A::.;Rc;..TC;::.S=.;N..:....,:

c:

~~~~~-------------------+~21INO

MEMEN.JED

4.7K

+ 22UF

T

16

Figure 11_ Memory Controller

UPDATE1 C

80

IDT79R3051'" SYSTEM DESIGN EXAMPLE
...--..

YVNUA'A""

~

0(31:0)

;:::::
~

AO(31:0)

~

TESTEN(2)
ALE,

~

74FCT373
3 00
00 12
401
01 15
02
8 03
""
13 04
n,
14 05
06
Q6
18 07
....

AU
'AU

'AU

4.7K

'AU

16
~

APPLICATION NOTE AN·86

'AU

'AU
'AU

'I\IJ

,

~ I~

.~4FCT623T

19 I'::.
BEN(O)

1>""1
BEN(2)'
"I:N{3,.

AD
'AC
'AC

2

Bl

! I~~

"0

8

'R

B3
B4
B5
B6

9

'D

~~

5

A{4)

61 A5

A{5)'
AIO)

A(;

0

18
16
15
14
13
12

' __t I~ ?!FCT623T
AI
'AI

3
4

74FCT373
0012
01
02
03
04
05
Q6
07

13

'AC

18

...1.1.

~
ICe

'12
15
16
19

AD e1
'AC
'AC

l"

GBA

2 AI
3 A2
4 A3
5 A4
6 A5
7AS
8 A7
g A8

Bl
B2
B3
B4
B5
B6
B7
B8

0(8

18
16
15
14
13
12

l"
~

'0:

0---1 1&

G;:FCT623T

AD 16
'AC
'AC

3

'~

8
13
14
17
Ie

'AC
AC
'A[
'AC

74FCT373
00
00
01
01
02
02
Q3
D3
Q4
04
05
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DB
Q6
07
07

~ GBA
2
5
6
'9
12
15

A 16

AO:16
'AC
'AC
AC
'AC
'AC
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19

;=t I~

:2~

3 DO
4

13
14
18

n7

...1.1.

,0:

~

OE"

00
01
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u'
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u,

u'
u

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12
15
116
19

18

:

--'tl~~

--=::li

74FCT373

A

2
3
4
5

In
A8

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B2 17
B3 16
B4 15
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BEN(3:0)

4,7K

A(31:4)

:'6

~

""
Figure 12. Address Latch Data Transceiver Demultiplexer

UPDATE1 C

81

APPUCATION NOTE AN-86

IDT79R3051'" SYSTEM DESIGN EXAMPLE

L.J

0(31·0)

..--.. AOOR(2)
!=( AUUH(3)

~

A(16:4)

L....)

71256

71256
A(4)
V.A(S)
VAtS)

V.A(7)

V A{8
VA(9)
VA(10)
VJ\lll)
V.A(12)
VA(13)
VA(14)
VA(1S)
/A(lS)

10
9
8
7
S
5
4
3
25
24
21
23
2
2S
1

/

AO
Al
A2
A3
A4
AS
AS
A7
A8
A9
Al0
All
A12
A13
A14

+sv

J

vee
GNO

r--"'

~
i===(
i===(

~
~

---1.g.
A(4)
/A(S)
/A(S)
/A(7)
'A{tl)
/A(9)
'A(lU)
/A(ll)
/A(12)
/A(13)
'A(14)
/A(lS)
'A(lS)

9
8
7
S
S
4
3
25
24
21
23
2
2S
1

/

~

20 "C"S"

---E WE
...li

0(0)
0(1)
U(2)
0(3)"0(4)'\
O(S)"u(S)
0(7)"-

11
12
13
15
16
17
18
19

000
001
002
0Q3
004
DOS
DOS
007

AO
Al
A2
A3
A4
AS
AS
A7
A8
A9
Al0
All
A12
A13
A14

000
001
002
003
004
DOS
DOS
007

'\

+5V

vee
GNO

20 "C"S"

~ WE
~ DE:

~

0(8
091"0101"0111"0121"0131'\
0141'\
0151'\

11
12
13
lS
lS
17
18
19

J

~

RAMeSN
WRENNA
WRENNB
WRENNe
WRENNO
ROENN

'---'

r

27256
A(4)
/A(5)
VAtS)
/A{)
/A(8)
/A(9)
/A(10)
/A(ll)
VA(12)
/A(13)
/A(14)
/A(lS)
V.A(lS)

10
9
8
7
S
5
4
3
25
24
21
23
2
26
27

V

AO
Al
A2
A3
A4
AS
AS
A7
A8
A9
Al0
All
A12
A13
A14

[(es
.n.

OE

27256
DO
01
02
03
04
05
OS
07

0(0)
0(1)"0(2)"0(3),\
0(4)'\
u(5)
U(S)
0(7)

11
12
13
lS
lS
17
18
19

"+5V
L~

vpp 1
vee ~
GNO

~

L...-..!!?-9 AO
A(4)
/A(5)
/A(S)
'A{f,
I'A{tl)
I'A(9)
/A(10)
/A(ll)
/A(12)
'A(l,,)
I'A(14)
/A(IS)
/A(lS)

/

8
7
S
5
4
3
25
24
21
23
2
2S
27

Al
A2
A3

A4
A5
AS
A7
A8
A9
Al0
All
A12
Al3
Al4

~ es
~ C5l:

DO
01
02
03
04
05
OS
07

0(8)
U(9),,0(10) '\
0(11)'\
0(12) '\
0(13),
u(14)
U(15)_,,-

11
12
13
lS
lS
17
18
19

'\
+SV
,,~

VPP 1
vee ~
GNO

)

EPROMeSN

NOTE: BANK A - - LlTILE ENOIAN LSB BYTE 0
- - BIG EN DIAN LSB BYTE 3
Figure 13. ROM and Slatic RAM Memory

UPOATE1 C

82

APPUCATION NOTE AN-86

10T79R3051™ SYSTEM DESIGN EXAMPLE

0(31·0)
'---J

71256

~ AO
A(4)
/A(5)
/A(6)
'A(7)
/A(8)
/A(9)
/A(lO)
'AI
/A(12)
/All<1)
'A(14
/A(15)
/A(16)

9
8
7
6
5
4
3
25
24
21
23
2
26
1

/

71256
OQO
001
002
0Q3
004
005
OOS
007

Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14

O(lS)

11
12
13
15
16
17
18
19

D(17),
D(18),

t,

0(19
U(20),\
U(21) '\
U(22) '\
0(23) '\

,

+5V

vee
GNO

20 ~

WE
---¥
,..A

~

11-

L..-..1.Q.
9
A(4)
8
V A(5)
7
/A(6)
6
VA(7)
5
VA(8)
4
VA(9)
3
VA(10)
25
VA(ll)
24
VA(12)
21
VA(13)
23
VA(14)
2
VA(15)
26
VA(16)
1
V

V

00
01
02
03
04
05
OS
07

~ OJ:

0(16)
0(17),
U(18),\
D(19),
0(20),

11
12
13
15
16
17
18
19

D(21),
D(22) ,

0(23),
'\
+5V
L~

vpp 1
vee ~
GNO

r--.l2 ~

D(25) ,
D(26) ,
D(27) ,

0(28),
0(29"
-0(30/'\
18
19 0(31)"'\
17

,

20 "CS"

J

11-

rn:

27256

27256
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14

vee
GNO

,..A

0(24)

11
12
13
15
16

+5V

~ WE

OE

---1Q.
9
(4)
8
/A(:l)
7
/A(6)
6
/A(7)
5
/A(8)
4
/A(9)
3
/AI10
25
/A(ll)
24
/A(12)
21
/A(13)
23
VA(14)
2
VA(15)
26
VA(lt>,
27

OQO
001
002
003
004
005
OOS
007

AO
Al
A2
A3
A4
A5
A6
A7
AS
A9
Al0
All
A12
A13
A14

r

c..........1.Q. AO

9
(4)
B Al
VA(5)
7 A2
VA(6)
6 A3
VA(7)
5 A4
VA(8)
4 A5
VA(9)
3 A6
VAllO) 25 A7
A8
VAl
24
VA(12) 21 A9
VA(13) 23 Al0
V A(14)
2 All
VA(15) 26 A12
VII(fS) 27 A13
A14

V

If.

00
01
02
03
04
05
06
07

0(24)
0(25)
0(26),
U(27)
0(28)

11
12
13
15
16
17
18
19

D(29)

D(30)
0(31)

,

+5V

4>-

~
vee f14
VPP

GNO

I"l-

22 OE

os

NOTE: BANKO - - LITTLE ENOIAN MSB BYTE 3
- - BIG ENOIAN MSB BYTE 0

Figure 13. ROM and Slatic RAM Memory

UPOATEl C

83

APPLICATION NOTE AN-86

10T79R3051'" SYSTEM DESIGN EXAMPLE
+5V
<~

68681

~ lACK
07
06
V05
V04
V03
VD(2)
V Dill
VD(Q)_

0(7:0)
~

C
C

AOOR(3:2)

19
22
18
23
17
24
16
25

V
A(5)
A(4)

A(5:4)

/

D'fi\CK ~

07
06
05
04
03
02
01
00

OPO
TXOA
RXOA
IPO
OPl
TXOB
RXOB
IPl
OP2
IP2

6
RS4
5
RS3
3
RS2
1
RSl

AOOR(3)
/AOOR(2)

/
GUARTCSN
WRENN
RESETN

IRQ 21

+5V

OP(O)
TXOA
RXOA
IP 0
OP(l)
TXDB
RXOB
IP 1
OP 2
IP(2)
UARTINTOC
TESTEN(3)

35
CS
8
11W
34
l=iES
2
IP3
IP4
~ IP5
~ ClK
~ X2

OP3 ~
OP4 ~
OP5
OP6 ~
OP7 ~

'39
IOClK

29
30
31
7
12
11
10
4
28
36

r11

L;>'

-=-

I ) SYSCLK
~

AOOR(2)
/AOOR3

/
0(0)
V O(l)
VO(2)
VO(3)
VO(4)
VO(5)
VD(6)
VO(7)
V

C

WRENNA

19
AO
20
Al
8254
8
7
6
5
4
3
2
1

00
01
02
03
04
05
06
07

OUTO

A(4)
OUTl

13 OUT(l)

V

AOOR(2)

/r--

21
CS
22
RO
23 WI'f

~
~

10 DUTrO)

OUT2

17 OUT(2)

GATEO
ClKO
GATEl
~ ClKl
,-r-1§. GATE2
18
ClK2

...-rll

B

TIMERCSN
ROENN

c=>~~IN~T~E~N~N

___________________________________________________________

Figure 14. InpUI/Output Devices

UPOATE1 C

84

APPUCATION NOTE AN-86

IDT79R3051'M SYSTEM DESIGN EXAMPLE

+5V

~

-;>-

16
MAX235
VCC

\4.7K
8
7
9
6
15
16
23
17
22
14

-

Til
n2
ROI
R02
TI3
TI4
R03
R04
TI5
R05

TOI
T02
Rll
RI2
T03
T04
RI3
RI4
T05
RI5

r1L
3
4
10
5
2
1
24
18
19
13

RTSN(O)
TXD(O)
RXD(O)
CTSN(O)
RTSN(1
TXD 1
RXD 1
CTSN 1
DTRN 1
DSRN 1

'7 ~g:
~

;-'- I-= 1) AND CYCENDN

{ PURPOSE: CYCLE END GOES LOW (SYNCHRONOUSLY) DURING THE LAST RDCENN ON
READS AND DURING ACKN ON WRITES.
IT RETURNS HIGH
SYNCHRONOUSLY BY INTERLOCKING ON THE COUNTER OUTPUTS
WHICH COUNT ONE GREATER THAN THE ASKED FOR VALUE BEFORE
RESETTING BACK TO ZERO (VIA CYCENDN). THUS CYCENDN WILL
DEASSERT ON THE SAME CLOCK AS THE RDN, WRN, OR BURS TN RISING
EDGES REGARDLESS OF WHETHER OR NOT THOSE RISING EDGES MEET
THE REGISTER'S SETUP AND HOLD TIMES.
{ NOTE:
TO FIT CYCENDN INTO A 16VS, TWO OUTPUTS MAY BE NEEDED.
CYCENDNEN
CYCENDN NOT

!TESTEN ;
RESETN AND CYCENDN AND
( !RAMCSN
AND (C
OR ( !RAMCSN
AND (C
OR ( !RAMCSN
AND (C
OR ( !EPROMCSN AND (C
OR (!EPROMCSN AND (C
OR ( !UARTCSN AND (C
OR (!TIMERCSN AND (C
OR ( { ! BUSERRORN} (C

(

02H)
OSH)
03H)
03H)
OCH)
06H)
06H)
1FH)

AND
AND
AND
AND
AND
AND
AND

!RDN
!RDN
!WRN
!RDN
!RDN

AND BURSTN)
AND !BURSTN)
)

AND BURSTN)
AND !BURSTN)
BURS TN)
BURSTN)
)

) ;

{ NOTE: IN THIS EXPERIMENT MEMSPAREO IS PULLED LOW AND CAN BE
USED TO DISABLE THIS CONTROLLER'S RDCENN, ACKN, AND BUSERRORN.
SINCE MEMSPAREO IS ATTACHED TO THE MEMDEC.LPLC PAL, THE
MEMDEC PAL COULD COMBINE THE CSN'S SO THAT THESE SIGNALS
ARE ONLY DRIVEN WHEN NEEDED.
{ NOTE: ANOTHER POSSIBILITY IS TO USE MEMSPAREO AS AN EXTRA CHIP
SELECT.

PURPOSE: READ BUFFER CLOCK ENABLE IS USED BY THE R305X TO STROBE
DATA INTO ITS INTERNAL READ BUFFERS.
NOTE:
IT IS ASSUMED THAT THE UART AND TIMER ARE
IN UNCACHABLE MEMORY SPACE AND WILL NOT BE BURST READ.
IF THEY ARE BURST READ, THE STATE MACHINE LOOPS 4 TIMES.

UPDATE1 C

93

IDT79R3051'" SYSTEM DESIGN EXAMPLE

RDCENNEN
RDCENN NOT

APPLICATION NOTE AN-86

!MEMSPAREO ;
RESETN AND CYCENDN AND (
( !RAMCSN AND !RDN
AND (
OR ( !BURSTN AND
OR ( !BURSTN AND
OR ( !BURSTN AND

(C
(C
(C
(C

02H)
04H) )
06H) )
08H) )

OR ( !EPROMCSN AND !RDN
AND (
(C
OR ( !BURSTN AND (C
OR ( !BURSTN AND (C
OR ( !BURSTN AND (C

03H)
06H) )
09H) )
OCH) )

OR (! UARTCSN AND ! RDN
AND (

(C

06H)

(C

06H)

)

OR (! TIMERCSN AND ! RDN
AND (
)

) ;

{ PURPOSE: ACKNOWLEDGE IS PRIMARILY USED TO END WRITE CYCLES. IT
SHOULD BE PULSED ONE (HALF) CLOCK CYCLE BEFORE THE WRITE
STROBE IS NEEDED. ON READ CYCLES, ACKNOWLEDGE WILL
IMPLICITLY BE GENERATED BY THE R30SX, HOWEVER, IF OPTIMAL
TIMING IS DESIRED, ACK SHOULD BE DRIVEN NO SOONER THAN 1
CLOCK BEFORE THE END OF A SINGLE READ AND FOR BURSTS NO
SOONER THAN 4 CLOCKS BEFORE THE END OF THE LAST READ.
ACKNEN
ACKN NOT

!MEMSPAREO ;
RESETN AND CYCENDN AND (
( ! RAMCSN AND ! WRN
AND (

{ WRITE CYCLE }
(C

03H)

)

OR (!RAMCSN AND !RDN AND !BURSTN
AND (
(C == OSH)

{READ

CYCLE}

{READ

CYCLE}

)

OR (!EPROMCSN AND !RDN AND !BURSTN
AND (
(C == 09H)
)

OR (!UARTCSN AND !WRN AND BURSTN
AND (
(C == 06H)

{ WRITE CYCLE }

)

UPDATE1 C

94

APPUCATION NOTE AN·as

IDT79R3051"'" SYSTEM DESIGN EXAMPLE

OR (! TIMERCSN AND ! WRN
AND (

WRITE CYCLE I

(C

06H)

)
) ;

{ PURPOSE: BUSERRORN SIMPLY ENDS A WAYWARD UNDECODED BUS CYCLE. ON
READS IT CAUSES AN EXCEPTION. ON WRITES IT DOES NOT CAUSE
AN EXCEPTION CONDITION FOR THE PROCESSOR. TO DO THAT, LATCH
BUSERRORN AND FEED IT TO AN INTERRUPT PIN OR A BRANCH
CONDITION PIN.
BUSERRORNEN
!MEMSPAREO
BUSERRORN NOT := RESETN AND CYCENDN AND
(C

IFH)

END
END UPAL2.

UPDATE1 C

95

IDT79R305F" SYSTEM DESIGN EXAMPLE

{ TITLE

PURPOSE
LANG
AUTHOR
UPDATES

APPLICATION NOTE AN-8S

MEMEN.LPLC
UPAL3 MEMORY READ AND WRITE ENABLE PAL FOR THE R30sX BEHAVIORAL BUS
EMULATOR MEMORY EVALUATION BOARD
GENERATES READ AND WRITE ENABLES FOR MEMORY CONTROLS.
LPLC - TM OF CAP lLANO COMPUTING SYSTEMS
ANDY NG, IDT INC.
C7C4F 03-1S-91 AP NOTE FIRST RELEASE

MODULE UPAL3
TITLE UPAL3
TYPE
AMD 22V10
INPUTS
DEMULTIPLEXED MEMORY ADDRESS LINES
SYSCLK
NODE [PIN1]
POWRESETN
NODE [PIN2]
RDN
NODE [PIN3]
WRN
NODE [PIN4]
ENSTARTN
NODE [PINS]
CYCENDN
NODE [PIN6]
BENO
NODE [PIN7]
BEN1
NODE [PINS]
BEN2
NODE [PIN9]
BEN3
NODE[PIN10]
UARTCSN
NODE [PINll]
MEMSPARE2
NODE [PIN13]

}

INVERTED SYSCLKN
POWER UP RESET
READ LINE
WRITE LINE
ENABLE START
CYCLE END
BYTE ENABLE 0
BYTE ENABLE 1
BYTE ENABLE 2
BYTE ENABLE 3
UART CHIP SELECT
SPARE INPUT

{ OUTPUT FEEDBACK NODES (NEEDED FOR LPLC'ISM)
RESETN
NODE [PIN23]
WRENN
NODE [PIN1S]
WRDATAEN
NODE [PIN17]
OUTPUTS

}

{ ATTRIBUTES C - COMBINATIONAL, R - REGISTERED, H -

HIGH, L - LOW }

WRITE ENABLES
WRENNA
WRENNB
WRENNC
WRENND
WRENN
WRDATAEN

NODE [PIN22]
NODE [PIN21]
NODE [PIN20]
NODE [PIN19]
NODE [PIN18]
NODE [PIN17]

{ READ ENABLES
RDENN
RDDATAENN

NODE [PIN16] ATTR[RL]
NODE [PIN1s] ATTR[RL]

READ OUTPUT ENABLE (FOR WORDS) }
READ DATA XCEIVER ENABLE
}

{ MISCELLANEOUS CONTROLS }
RESETN
NODE [PIN23] ATTR[RL]
GUARTCSN
NODE[PIN14] ATTR[RL]

SYNCHRONIZED RESET
GATED/GUARDED UART CHIP SELECT}

I/O PINS USED AS INPUTS
NONE }

ATTR[RL]
ATTR[RL]
ATTR[RL]
ATTR[RL]
ATTR[RL]
ATTR[RL]

WRITE
WRITE
WRITE
WRITE
WRITE
WRITE

ENABLE FOR BYTE 0
ENABLE FOR BYTE 1
ENABLE FOR BYTE 2
ENABLE FOR BYTE 3
ENABLE MOTO-TYPE I/O
DATA XCEIVER ENABLE

}

OUTPUT ENABLES }
WRENNAEN
NODE [PIN22EN]
WRENNBEN
NODE [PIN21EN]

UPDATE1 C

96

IDT79R30S1 Th1 SYSTEM DESIGN EXAMPLE

WRENNCEN
WRENNDEN
WRENNEN
WRDATAENEN
RDENNEN
RDDATAENNEN
RESETNEN
GUARTCSNEN

APPUCATION NOTEAN-86

NODE [PIN20ENj
NODE [PIN19ENj
NODE [PIN18ENj
NODE [PIN17ENj
NODE [PIN16ENj
NODE [PIN15ENj
NODE [PIN23ENj
NODE [PIN14ENj

{ ASYNCHRONOUS RESET AND SYNCHRONOUS PRESET NODES }
RESETEN
NODE [RESETj
NODE [PRESETj
PRESETEN
TABLE
{ RESET AND PRESET ARE NOT USED IN THIS PAL. }
0
RESETEN
PRESETEN = 0 ;

{ PURPOSE: WRITE BYTE ENABLES AND WRITE WORD ENABLE ALLOW
SUFFICIENT TIME FOR THE ADDRESS TO DECODE AND
FOR A VALID CHIP SELECT BEFORE ENABLING THE
WRITE STROBE FOR A SPECIFIC BYTE BANK.
NOTE:
BANK A IS THE BIG ENDIAN'S LSB BYTE3 OR THE LITTLE
ENDIAN'S LSB BYTEO.
IT ALWAYS HOLDS D(7:0).
BANK D IS THE BIG ENDIAN'S MSB BYTEO OR THE BIG
ENDIAN'S MSB BYTE3.
IT ALWAYS HOLDS D(31:23) .

WRENNAEN
WRENNA

!MEMSPARE2 ;
RESETN AND (
! WRN AND ! BENO AND ! ENSTARTN AND CYCENDN

NOT

.=

NOT

.= RESETN AND

) ;

WRENNBEN
WRENNB

!MEMSPARE2 ;
(

!WRN AND !BENl AND !ENSTARTN AND CYCENDN
) ;

WRENNCEN
WRENNC

NOT

!MEMSPARE2 ;
RESETN AND (
!WRN AND !BEN2 AND !ENSTARTN AND CYCENDN

NOT

!MEMSPARE2 ;
RESETN AND (
!WRN AND !BEN3 AND !ENSTARTN AND CYCENDN

) ;

WRENNDEN
WRENND
) ;

{ PURPOSE: WRENN IS USED TO PROVIDE A WRITE LINE THAT HOLDS
LOW FOR AN EXTRA CYCLE, SO THAT IT CAN BE USED FOR
MOTOROLA-TYPE I/O DEVICES ON THEIR MULTIPLEXED
READ/WRITE LINE.
WRENNEN
WRENN

NOT

.=

!MEMSPARE2
RESETN AND

UPDATE1 C

1DT79R3051 TN SYSTEM DESIGN EXAMPLE

APPUCATION NOTE AN·86

(!WRN AND CYCENDN)
OR (!WRENN AND !CYCENDN)
) ;

{ PURPOSE: WRDATAEN AND RDDATAENN DRIVE THE OUTPUT ENABLE
CONTROLS ON A FCT623T TRANSCEIVER BANK FOR THE
DATA BUS. THE CONTROLS CAN BE USED FOR ANY
DUAL-OUTPUT ENABLE TRANSCEIVER (1 FOR EACH
DIRECTION. OUTPUT ENABLE/DIRECTION CONTROLLED
TRANSCEIVERS (FCT245) REQUIRE MORE INTERFACING
IF OUTPUT CONTENTION IS TO BE AVOIDED BY
ONLY CHANGING THE DIRECTION WHEN THE OUTPUTS ARE
DISABLED.
{ NOTE:

NOTE:

NOTES:

WRITE DATA ENABLE DEASSERTS ONE CLOCK AFTER
WRN DOES TO PROVIDE SUFFICIENT HOLD TIME FOR THE
WRITE DATA INTO THE MEMORY (SEE UPAL2 QWRNFOR A
MORE DETAILED EXPLANATION) .
WRDATAEN IS ACTIVE HIGH FOR THE FCT623T OUTPUT ENABLE
CONTROL. FOR THE FCT861 OUTPUT ENABLES, USE ACTIVE
LOW.
THE FIRST OR-TERM ASSERTS WRDATAEN WHILE THE SECOND
OR-TERM DEASSERTS WRDATAEN.

WRDATAENEN
WRDATAEN

!MEMSPARE2 ;
RESE'fN AND (
(!WRN AND !ENSTARTN)
OR (WRDATAEN AND (!ENSTARTN OR !CYCENDN))

) ;

RDENNEN
RDENN

NOT

!MEMSPARE2 ;
RESETN AND (
!RDN AND !ENSTARTN AND CYCENDN

) ;

{ PURPOSE: RDDATAENN IS CONNECTED TO THE MEMORY BOARD'S
DATA TRANSCEIVER OUTPUT ENABLE (FCT623T OR FCT861)
AND ONLY ENABLES FOR THIS BOARD'S CHIP SELECTS.
IF THE MEMORY CONTROLLER IS USED FOR ANOTHER
BOARD'S MEMORY, THEN THE TRANSCEIVER OUTPUT ENABLE
SHOULD BE DISABLED FOR THOSE CHIP SELECTS (VIA
MEMSPARE2.
{ NOTE:

IN MOST SYSTEMS, R305X'S DATAENN OUTPUT CAN BE
CONNECTED DIRECTLY TO THE TRANSCEIVER ENABLE PIN
INSTEAD OF USING A SYNTHESIZED RDDATAENN.

RDDATAENNEN
RDDATAENN
NOT

!MEMSPARE2
RESETN AND
!RDN AND !ENSTARTN AND CYCENDN

) ;

{ PURPOSE: RESET SYNCHRONIZES THE POWER UP RESET FOR THE
MEMORY CONTROLLER STATE MACHINES AND FOR THE R305X.
RESETNEN
RESETN

!MEMSPARE2
NOT .= !POWRESETN

UPDATE1 C

98

IDT79R30S1'" SYSTEM DESIGN EXAMPLE

APPLICATION NOTE AN·as

{ PURPOSE: GUARDED/GATED UART CHIP SELECT, GUARTCSN GATES
UARTCSN BECAUSE THE UART BEING USED HAS A MOTOROLATYPE I/O DEVICE INTERFACE WHICH MULTIPLEXES ITS
READ/WRITE INPUT PIN SUCH THAT THE CHIP SELECT MUST
STROBE IN OR OUT DATA. THIS IS IN CONTRAST TO AN
INTEL-TYPE I/O DEVICE INTERFACE WHICH WOULD HAVE A
SEPARATE READ STROBE AND WRITE STROBE AS WELL AS A
CHIP SELECT.
IT IS IMPORTANT NOT TO HAVE A
GLITCH (FROM ADDRESS DECODING THE CHIP SELECT) ON
READS IN ORDER TO ALLOW THE I/O DEVICE TO UPDATE
FIFO POINTERS, ETC. THUS GUARTCSN STARTS LATE AND
ENDS EARLY, SO THAT READ/WRITE IS HELD VALID
THROUGHOUT THE CHIP SELECT.
GUARTCSNEN
GUARTCSN

!MEMSPARE2 ;
NOT:= RESETN AND (
!UARTCSN AND !ENSTARTN AND CYCENDN

) ;

END;
END UPAL3.

UPDATE1 C

99

APPLICATION NOTE AN·aS

IDT79R3051'" SYSTEM DESIGN EXAMPLE

{ TITLE

MEMINT.LPLC
UPAL4 MEMORY I/O INTERRUPT CONTROLLER PAL FOR THE R305X BEHAVIORAL
BUS EMULATOR MEMORY EVALUATION BOARD
PURPOSE: REPLICATES THE TIMER/UART INTERRUPT CONTROLLER ON THE 7RS382 BOARD.
ADDITIONAL FUSE BITS ADDED FOR 16V8 COMPATIBILITY.
LANG
LPLC - TM OF CAP lLANO COMPUTING SYSTEMS
AUTHOR
IDT INC.
UPDATES: C3F98 01-04-91 16V8 PCB VERSION FIRST RELEASE A.N.

{ U24A_382 INTERRUPT PAL}
{ 1-2-90,12-14-89 }
{JEDEC file's CHECKSUM = 379E } { NOTE: 01-04-91 - NOT APPLICABLE TO 16V8 }
CONTROL PAL FOR 8254 TIMER'S AND UART INTERRUPT
USED FOR EVALUATION BOARD 382 }
MODULE U24A_382;
TITLE U24A_382;
TYPE MMI 16R8;
{ FUSE BITS FOR
FUSE 2048 .. 2079
FUSE 2080 .. 2111
FUSE 2112 .. 2143
FUSE 2144 .. 2175
FUSE 2176 .. 2193

16v8 FAMILY ATTRIBUTES USED AS A 16R8
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000001111111111111111
11111111111111111111111111111111
111111111111111101

INPUTS;
MRES/
UARTINT/
PMRD/
CSTIM/
EA02
EA04
OUT1
OUTO

NODE[PIN2];
NODE[PIN3];
NODE[PIN4];
NODE[PIN5];
NODE[PIN6];
NODE [PIN7] ;
NODE[PIN8]; {input from Timer output OUT1}
NODE[PIN9]; {input from Timer output OUTO}

DTOA/
DTOB/
TOINT/

NODE[PIN14];
NODE[PIN15];
NODE[PIN16];

{feedback}
{feedback}
{feedback}

DT1A/
DT1B/
TlINT/

NODE[PIN17];
NODE[PIN18];
NODE[PIN19];

{feedback}
{feedback}
{feedbac~}

OUTPUTS;
UINT5/
DTOA/
DTOB/
TOINT/

NODE[PIN13];
NODE[PIN14];
NODE[PIN15];
NODE[PIN16];

{ goes to R3000's UINT3}

DT1A/
DT1B/
TlINT/

NODE[PIN17];
NODE[PIN18];
NODE[PIN19];

{ goes to R3000's UINT4}

UPDATE1 C

100

APPUCATION NOTE AN-a6

IDT79R3D51 1ld SYSTEM DESIGN EXAMPLE

TABLE;
{
8254 TIMER generates 2 square-wave outputs aUTO and OUT1.
When aUTO goes from high to low, this PAL asserts interrupt
TOINT/, which will interrupt R3000 through UINT3.
'Same scheme applies to OUT1, T1INT/ and UINT4.
Reading physical addresses 1F80 0010 and 1F80 0014 (which are
virtual addresses BF80 0010 and BF80 0014 in this 382 board)
will clear interrupt UINT3 and UINT4, respectively.
This PAL also synchronizes UART interrupt signal }

DTOA/
DTOB/
TOINT/ NOT

.=

DT1A/
DT1B/
TlINT/ NOT

UINT5/

aUTO;
DTOA/;
MRES/ AND
«NOT DTOA/
(NOT TOINT/

{delay TIMER's aUTO through a register}
(delay again)
AND DTOB/) OR
AND (NOT EA04 OR EA02 OR CSTIM/ OR PMRD/)));

OUT1;
DT1A/;
MRES/ AND
«NOT DT1A/ AND DT1B/) OR
(NOT TlINT/ AND (NOT EA04 OR NOT EA02 OR CSTIM/ OR PMRD/)));

:=

UARTINT/ OR NOT MRES/
{put UART's interrupt through a register to synchronize
it with R3000 clock }

END;
END U24A_382.

UPDATE1 C

101

t;;0

APPLICATION
NOTE
AN-87

IDT79R3000/R3001 SYSTEM
PERFORMANCE ANALYSIS

Integrated DevIce Technology. Inc.

By Dean M. Smith

INTRODUCTION
Pixstats and cache2000 are MIPS Computer Systems,
Inc. software tools that allow you to evaluate all possible·
79R3000 and 79R3001 system designs to determine the
optimum price/performance solution. These same tools play
a large a role in processor selection. The statistics generated
by pixstats and cache2000 allow you to esdtablish the exact
performance on various 79R3000/3001-based systems for
comparison to other candidate microprocessor systems.
Pixstats projects the number of 79R3000/1 integer unit
and 79R3010 floating-point unit pipeline interlock cycles.
Cache2000 models the 79R3000/1 memory subsystem
detailed in Figure 1, thereby projecting the penalties incurred
for accesses to asynchronous main memory. Cache size,
asynchronous-memory access penalties, write-buffer size,
cache burst-refill size, TLB miss penalties, cache flushing,
and other parameters can be varied and the exact performance impact acertained Pixstats and cache2000 together
provide complete analysis of 79 R3000/1 compiler and targetsystem performance.

79R3010

79R3000

Floating·polnt

Integer

Unit

Unit

(optional)

i
.I

i

r':::

~'}

~~~.

:Hi

.s)

(:t:

~f?

INTERPRETATION OF STATISTICS

~(;~l~!

~~~~!

"-

'Synchronous' System
The large allowable cache size for the 79R3000 (512Kb
max) and the 79R3001 (32Mb max) permit entire applications
to be housed in synchronous memory. Or, if needed, the
time-critical portion of a larger task or kernel can be locked in
cache segment. The performance of these 79R3000/1 'synchronous' solutions is determined from pixstats.
Since pixstats assumes a 100% cache hit-rate, the performance statistics generated are those for a 'synchronous'
system design. Asynchronous main memory access penalties are not simulated by pixstats. Pixstats assumes that
the application is operating in KSEGO and KSEG1 virtual
address segments. Thus, TLB and uTLB miss penaHies are
not simulated. Any additional run-time cycles incurred are a
resuH of the 79R3000 integer multiply/divide busy interlock
cycles and the 79R3010 floating-point busy interlock cycles.
The 79R3000/1 has a separate multiply and divide unit
that takes 12 and 35 cycles, respectively, for integer multiply
and divide. Attempts to prematurely read the result of a
multiply or divide cause the pipeline to stall (ie. interlock) until
the operation has been completed. Also, a new multiply or
divide operation can not begin before a previously issued
one completes. Such resource conflicts also cause the
pipeline to stall. The 79R3010 has separate add, multiply,
and divide units and will similarly stall its own pipeline when
conflicts occur. The optimizing compiler reduces the number
of pipeline stalls by re-scheduling the 79R3000/1 and the
79R3010 pipelines to eliminate as many data and resource
1:>1991 Integrated DevIce Technology. Inc.

)

Figure 1. 79R3000/1 Memory Subsystem

conflicts as possible. In the example pixstats output in
Figure 2, the total number of run-time cycles calculated is
10211. The difference between this number and the 8795
instructions executed is equal to the total number of 79R3000/
1 and 79R3010 interlock cycles.
All 79R3000/1 cache accesses are on word boundaries.
Consequently, Partial Word Store, Store Word Left, and
Store Word Right instructions are implemented as two cycle
read-modify-write operations. However, pixstats was originally written to model the 79R2000, the first implementation
of the MIPS architecture. The 79R2000 implemented these
special instructions as one-cycle operations, simultaneously
updating main memory and invalidating the corresponding
cache entry. This is the only shortcoming of pixstats in
modeling the 79R3000/1 and the 79R3010. Thus, the total

number of run-time cycles for a 'synchronous' system operating out of virtual address segments KSEGO or KSEG1 is
equal to the number of run-time cycles calculated by pixstats
plus the number of two cycle store instructions (sb, sh, swl,
swr). The number of two cycle store instructions is obtainable

UPDATE1.C

102

IDT79R30DO/R3001 SYSTEM PERFORMANCE ANALYSIS

APPLICATION NOTE AN-87

from the opcode distribution section of the pixstats output. For
the example in Figure 2 there are 127 sb instructions and
102 sh instructions accounting for a total run-time of 10340
cycles (ie. 129 two cycle stores + 10211 cycles calculated by
PIXSTATS).

'Cached' System
A 'cached' 79R3000/1 system is one in which a smaller
synchronous memory behaves as a cache to a larger and
slower asynchronous memory. Such a target system does
not have enough synchronous memory to house the entire
application.

(18634 cycles) x (40 nS) = 745.36 j.LS, @ 25MHz
(18634 cycles) x (30 nS) = 559.02 j.LS, @ 33MHz
(18634 cycles) x (25 nS) = 465.85 j.LS, @ 40MHz
cache2000:
Thu May 31 15:29:291990
17218 cycles (1.958), O.Os @ 20.0MHz
8795 instructions (O.OM)
cache flushes (Infinityms)

o

l-cache size =4096 words, direct-mapped, 4 word refill
D-cache size = 4096 words, direct-mapped, 4 word refill,
write-through
Write buffer =1 deep
TLB size = 56 entries, associative, random replacement,
page size,;, 1024 words

Example:
10211 (1.161) cycles (0.000408s @ 25.0MHz)
8795 (1.000) instructions

0(0.000) multiply/divide interlock cycles (12/35 cycles)
- these are due to R3000/1 Data and Resource
Conflicts.
604 (0.069) flops (1.48 mflop/s @ 25.0MHz)
112 (0.013) floating pOint data interlock cycles
- these are due to R3010 Data Conflicts
336 (0.038) floating point add unit interlock cycles
- these are due to R3010 Resource Conflicts
o (0.000) floating point multiply unit interlock cycles
- these are due to R3010 Resource Conflicts
o (0.000) floating point divide unit interlock cycles
-these are due to R3010 Resource Conflicts
968 (0.110) other floating point interlock cycles
- these are due to R3010 ?
112 (0.013) 1 cycle interlocks (2 cycle stalls - not
counted)
o (0.000) overlapped floating point cycles
492 (0.056) interlock cycles due to basic block boundary

Opcode distribution:
spec 1700 19.33%
bnop 215
2.44%

Iwc1
sb
jnop
xori
fcvtw
mff
Ibu
sh

50
127
117
112
112
112
110
102

1.71%
1.44%
1.33%
1.27%
1.27%
1.27%
1.25%
1.16%

"uTLB misses:
I-TLB misses:
D-TLB misses:
I-cache misses:
D-cache misses:
Idle writes:

Per
Instr
9
3
3
486
119
684

Per Cycle/Per Other
(0.10%/ 0.05%)
(0.03%/0.02%)

(0.03%10.02%/0.12%)
(5.53%/ 2.84%)
(1.35%/0.69%/14.27%)

(7.78%/3.99%/43.4%)
(2 memory cycles)

Page "mode writes:
Non-page writes:
Total writes:
I-stream branch:
I-stream d-miss:
I-stream write:
I-stream block:
I-stream words:

882

(2 mel'1Jory cycles)
(0.11%/0.06%/ 0.6%)
(2 memory cycles)
1576 (17.92%/9.20%)
45 (0.51%/0.26%1 9.3%)
(0.09%/ 0.05%/ 1.6%)
8
241 (2.74%/1.41%/49.6%)
192 (2.18%/ 1.12%/39.5%)
0.1/1.6/2.3
10

uTLB miss cycles:
9
I-TLB miss cycles:
39
0- TLB miss cycles:
39
I-cache miss cycles: 2916
·771
l-cache streaming:
D-cache miss cycles: 714
2-cycle SB/SH/SWU
SWR:
229
Write buffer full cycles: 3469
Write wait cycles:

(10.03%/5.15%/56.0%)

(0.00%/ 0.00%) (penalty 1)
(0.00%1 0.00%) (penalty 13)
(0.00%/ 0.00%) (penalty 13)
(33.16%/17.02%) (penalty 6)
(-8.77%/ -4.50%)
(8.12%/ 4.17%) (penalty 6)
(2.60%/ 1.34%) (penalty 1)

(39.44%/20.25%)

(average 2.2 per write)
1779 (20.23%/10.38%)
(average 2.9 per miss)

Figure 3. Excerpt From A cache2000 Output

Figure 2. Excerpt From a PIXSTATS Output

UPDATE1 C

103

•

APPLICATION NOTE AN-87

IDT79R3000/R3001 SYSTEM PERFORMANCE ANALYSIS

Cache2000 must be used to generate the performance
statistics of a 'cached' system. Main memory access penalties, uTLBfTLB miss penalties, and two-cycle store penalties
are simulated. However, cache2000 does not simulate
79R3000/1 and 79R3010 interlock cycles. Thus, the total
number of run-time cycles for a 'cached' system is equal to the
number of run-time cycles calculated by cache2000 plus the
total number of interlock cycles calculated by pixstats. For the
cache2000 example in Figure 3, the total number of run time
cycles for the target cached system is 18634 (ie. 17218 cycles
from cache2000 + 1416 interlock cycles from the corresponding pixstats output in Figure 2). Cache2000 assumes that the
cache is initially void of the benchmark. Initial cache misses
are incurred as code gets loaded into the cache for the first
time. All run times projected by cache2000 include these initial
cache misses. Note that the number of instructions executed
is the same for both the cache2000 output and the corresponding pixstats output. These instructions include the jump/
branch and load delay slot nops not replaced with useful
instructions by the optimizing compiler.
The statistics generated by pixstats and cache2000 can
be used to scale target system performance by using a faster
(or slower) 79R3000/1 matched with the corresponding speed
grades of synchronous and asynchronous memory. For
instance, the run times for the example application detailed
in Figures 2 & 3 with 25, 33, and 40MHz clocks are:

Size Of Executable
The size of the executable is useful in determining the
appropriate amount of target system cache. The executable
size also dictates the minimum amount of synchronous
memory required for a 'synchronous' target system. The
RISC/os UNIX utility size prints the size of the instruction and
data sections of the executable.

Dummy routines have been written and compiled to determine the the entry/exit code size for all languages supported
by MIPS. These dummy routines are detailed in Figure 5.
The corresponding static code sizes are summarized in Table
I. The entry/exit code size must be subtracted from the
application size to determine the stand-alone application
size. For the C application in Figure 4, the stand-alone
application code size consists of 7280 bytes of instruction(11360 - 4080) and 2256 bytes of data(7376 - 5120).

Language

I size (bytes)

D size(bytes)

C

4080

5120

ADA

30064

23552

'synchronous'
Performance

FORTRAN
PASCAL
COBOL
PU1
assembly
NOTE: compiler optimization level 4 used
Table 1. Entry/Exit Code

There is additional overhead when running the entry/exit
code. Table 1 summarizes the additional cycles incurred for
a 'synchronous' system, as measured by pixstats. Unknown, however, is the exact performance degradation for
'cached' systems. Since some of the cache is consumed by
the entry/exit code and data, the number of additional cache
misses' and other penalties associated with the resultant
increase in main memory traffic is not known.

Floating-Point Alternatives

Size of example:18736

Section

Size

Physical
Address

Virtual
Address

.text

11360

4194672

4194672

.in~

32

4206032

4206032

.dala

16

268435456

268435456

.li18

144

268435472

268435472

.sdala

2032

268435616

268435616

.sbss

432

268437648

268437648

.bss

4720

268438080

268438080

Figure 4. Output From Unix size Utility

The static instruction size of the example executable in
Figure 4 is 11360 bytes. The static data size of the example
executable is 7376 bytes (ie. 18736 total - 11360 code).
Each MIPS RISComputer generated executable has entry/
exit code inserted at compile time by RISC/os to transfer
control to and from the benchmark.

The 79R301 0 is optional in 79R3000/1 system design and
is used in applications that have floating-point requirements.
Floating-point emulation handled in software by the 79R3000/
1 integer unit offers a less expensive and space saving
alternative to the 79R3010. The performance of available
emulation routines is often adequate for limited floating-point
applications.
MIPS' compilers always assume the presence of the
79R3010 and thus generate 79R3010 instructions. If the
Cu1 (79R3010 usability) bit in the 79R3000/1 status register
is not set, then a Coprocessor Unusable Exception occurs
when a 79R3010 instruction is decoded. The 79R3000/1
jumps to the general exception vector where the exception
type is then decoded. Execution then jumps to the floatingpoint emulation service routine. The service routine initiates
the corresponding 79R3010 instruction emulation routine
started. To measure the performance of such systems, you
must omit the number of 79R301 0 interlock cycles calculated
by pixstatsfrom the total cycle count. The 79R301 0 dynamic
opcode distribution listed in the pixstats output is used to
calculate the emulation overhead. The following are the run

UPDATE1 C

104

.IDT79R3000/R3001 SYSTEM PERFORMANCE ANALYSIS

APPLICATION NOTE AN-87

cycle counts for the 79R3010 emulation package available
from lOT:

C dummy routine
mainO

{
}
Single Precision

Double Precision

ADD

40 cycles

66 cycles

SUB

52 cycles

90 cycles

MUL

50 cycles

97 cycles

DIV

160 cycles

236 cycles

Ada dummy routine
procedu re TEST is
begin
null;
end TEST;

NOTE: assuming emulation routines present in cache

Fortran dummy routine

Higher floating-point emulation can be achieved by using
lOT's PostFloat fiHer to eliminate exception handling overhead. A source program is first compiled at the assembly
level. The PostFloat filter is then used to strip away 79R3010
instructions, replacing them with direct calls to the emulation
routines. Even higher performance floating-point emulation
is achieved with lOT's cross compilers. lOT's multi-hosted
compilers inline floating-point emulation routines which then
benefit from global optimizations. Details of the lOT Post Float
filter and the IDT7RS903 Multi-Host C-compiler System are
available from lOT. Note that these alternatives eliminate
floating-point machine code in the executable. There are no
79R3010 pipeline interlock cycles to subtract out from the
statistics generated by pixstats.

Pascal dummy routine
Cobol dummy routine
PUI dummy routine
MIPS assembly dummy routine
Figure 5. Dummy Routines

without the -jmpopt compiler option
Jump
Inst

PERFORMANCE ANALYSIS STEPS

I

Creating The EXECUTable
At compilation, the MIPS compiler system allows you to
choose from various options that affect the nature and efficiency of the executable. These compiler options can be
turned on or off as appropriate. You can refer to the "lOT
R3000 FAMILY LANGUAGE PROGRAMMERS GUIDE" for
a complete description of the MIPS compiler system. A few
of the compiler system options, as related to performance
analysis, are discussed here.

ALU

10

l-cache

Delay

I

Slot

I-cache

O-cache

WB

J

-\

I-Iargel

I I~

(nap)

ALU

~

Targetl
Inst

F

R
D

ALU

I-cache

I

110

ALU

ME
M

WB

Compiler Optimization Levels:
There are several levels of optimization for the MIPS
compilers:

with the -jmpopt compiler option
Jump

Level

Optimizations

WB

Inst

0

none

1

default pipeline scheduling, local optimizations

2

adds global optimizations, register allocation

3

adds inter-procedural register allocation

4

adds procedure merging
10

Although optimization level 04 typically generates the
most efficient code, the target-system performance may not
be optimum. Procedure merging (ie. in lining) is an optimization technique intended to increase performance by
eliminating jumplbranch instructions. However, inlining of

UPDATE1 C

ALU

WB

Figure 6. The -jmpopt Lnker Option

105

IDT79R3000/R3001 SYSTEM PERFORMANCE ANALYSIS

APPUCATION NOTE AN-87

subroutines also tends to increase the static code size which
can have an adverse effect on cache hit-rate. It is advisable
to experiment with all compiler optimization levels to determine
which results in the highest target performance.
FIlling Unconditional Jump Delay Slots:
79R3000/1 jump instructions have a delay of one cycle
while they calculate the target address where execution is
resumed (refer to Figure 6). The instruction that immediately
follows in the pipeline is called the 'delay slot' instruction
which the 79R3000/1 always
executes. The compiler is responsible for re-scheduling the
pipeline by filling the delay slot with an instruction that is
independent of the jump. In this manner the pipeline con~in­
ues to flow and performance is not degraded. If the compiler
can not find a useful instruction, a nop is inserted that results
in a 1 cycle performance penalty.
The -jmpopt linker option fills any jump delay-slot with the
target of the jump and increments the target address to the
next instruction. Unlike the compiler, the linker has unlimited
scope and can refill the delay slot regardless of where target
instruction is.located.

Reducing cache Conflicts:·
'.
Every main memory location maps to exactly one 79R3000/
1 cache location. Different sections of code located a mUltiple of the cache size away from one another compete for
the same cache space. The 793000/1 first checks cache for
a needed piece of code. If not there, the code is then loaded
into cache from main memory - overwriting code previously
resident in the corresponding cache locations. Such cache
conflicts significantly degrade performance if newly loaded
code replaces other code that will be needed right away. A
classic example of this activity (known as to 'thrash in cac~e')
is a loop in which a subroutine is called that is located In a
muHiple of the cache size.
.
Major cache conflicts can be avoided by using the -cord
compiler option that uses statistics gener~ted by the p.rogram profiling tools pixie and prof (refer to Figure .7). The first
version of the executable is generated by invoking the corresponding driverwith the desired compiler options. Pixie is then
used to partition the executable into basic blocks. Each
basic block has exactly one entry point (ie. target address of
a jump/branch instruction) and exactly one exit point (ie. the
address of the first jump/branch instruction encountered).

CREATE THE EXECUTABLE
cc -app.c -0 app I-options]

PIXIFIFY THE EXECUTABLE
pixie app -0 app.pixie

RUN THE PIXIFIED EXECUTABLE
app.pixie

PROFILE THE EXECUTABLE
prof app -feedback feedfile

RE-CREATE THE EXECUTABLE
TO REDUCE CACHE CONFLICTS
cc app.c-o app -feedback feedfile -cordI-options]

app
OPTIMUM EXECUTABLE
Figure 7: Reducing Cache Conflicts

UPDATE1 C

106

IDT79R3000/R3001 SYSTEM PERFORMANCE ANALYSIS

APPLICATION NOTE AN-87

Additional counting code is inserted by pixie at the end of each
basic block. The pixified executable generates a file containing the basic block counts (.counts extension). This raw data
is used by prof to generate profile data for the different procedures within the application. This profile data is stored in a
feedback file in a format usable by the compiler. The application is then re-compiled with the -cord option. The
-cord option places the most frequently used loops in main
memory locations that do not conflict with one anotherforthe
same cache location.
Single or Double-Precision Floating-point:
A significant performance gain can be realized by both the
79R3010 and the floating-point emulation software by doing
single-precision arithmetic, vs double-precision. Single-precision often provides adequate dynamic range for an
application's floating-point requirements. To ensure that all
floating-point operations are done in single-precision, the
compiler option -float should be used. Even if all floatingpoint variables are declared as single-precision in the source,
the -float compiler option is necessary to ensure that intermediate operations are done in Single-precision.
Other Concerns:
The most efficient code is not appropriate for all applicationS/benchmarks. Compiler optimizations can alter the
intended nature of a benchmark. This is the case for realtime code in which the precise timing of operations is more
important than the execution speed. Loop optimizations that

app
executable

pixie
L -_ _ _..J

app.plxie
pixified
executable

L -_ _ _..J

app.pixle
pixified
executable
app.Addrs
basic blocks
address file

app.Counts
pixified

move loop invariant code outside loops so that it is only
executed once is one compiler optimization technique that
can create havoc with real-time code. The real-time portion
of an application should be written in MIPS assembly language
and assembled with the -noreorderoption to prevent pipeline
scheduling from altering the execution sequence of instructions . The resultant object code can then be linked with the
object code of other compiled modules.
Interprocedural register allocation and procedure merging
may not be desired if subroutine calls in a benchmark are
intended to simulate interrupts. Also, field serviceability
requirements may dictate the use of lower optimization levels.
Although compiler optimizations do not alter the flow of
control within a program, the sequence of object code may
be altered thereby making source-level debug difficult or
impossible. It is often useful to look at the dis-assembly of
the compiled code to decide on the appropriate optimization
level.· The RiSe/os utility dis generates the dis-assembly with
source listings i~terspersed.

Using pixstats
(refer· to. Figure 8)
Pixie is used to partition the executable into basic blocks.
Each basic block has only one entry point (ie. target address
of a jumplbranch instruction) and only one exit point (ie. the
address of the first jump/branch instruction encountered).
Additional counting code is inserted by pixie at the end of each
basic block. Also generated is' a file containing the basic

PIXIFY THE EXECUTABLE

pixie app -0 app.trace

RUN THE PIXIFIED EXECUTABLE

app.pixie

app

e

app.pxst
synch mem
subsystem
performance
statistics

GENERATE PERFORMANCE
STATISTICS FOR A
SYNCH R3000/R300l
MEMORY SUBSYSTEM

pixstats app > app.pxst

Figure 8. Using pixstats
UPDATE1C

107

APPLICATION NOTE AN-87

IDT79R3000/R3001 SYSTEM PERFORMANCE ANALYSIS

block addresses (.Addrs file). The pixified executable generates a file containing the basic block counts (.counts
extension). Pixstats uses the .Addrs and .Counts files to
generate detailed statistics on pipeline interlocks, opcode
frequency, and mini-profile data.

app

app.slze

executable

size of
executable

Using cache2000

(refer to Figure 9)

The size of the executable is useful in determining the
appropriate sizes of instructioll and data cache to simulate.
Pixifying the executable with the -idtrace option enables
tracing of instruction and data memory references for use by
cache2000. To model the target system, cache2000.c can be
modified asshown in Figure 10. Any optimization level may

DETERMINE SIZE OF EXECUTABLE
size app > app.size

app.trace
pixified
executable

app
executable

pixie

PIXIFY THE EXECUTABLE
I-Idtrace option)

app.Addrs
pixie -idtraceapp -0 app.trace

basic blocks
address file

MODIFY cache2000.c

cache2000.c .---------, cache2000.c
original
source

TO MODEL TARGET

simulated
R3000/R3001
mem subsystem

MEMORY SUBSYSTEM

L -_ _ _- - '

C~EA~E

cache2000.c .---------, cache2000.sys
mode
R3000JR3001 ' - - - - - - '
mem subsystem

app.trace
pixified
executable

cache2000 EXECUTABLE

executable

cc -04 cache2000.c -0 cache2000.sys -1m

execute

GENERATE PERFORMANCE STATISTICS FOR THE
TARGET R300011 SYSTEM

'I'
make pipe 19 app.trace

::1
cache2000.sys

app.sys

'I' 0

cache2000.sys > app.sys &

target me m
-su syste m
performance
statistics

Figure 9: Using cache2000

UPDATE1 C

108

APPLICATION NOTE AN-a7

IDT79R3000/R3001 SYSTEM PERFORMANCE ANALYSIS

be used to generate the cache2000 executable. II many
simulations are planned, it is advisable to experiment with all
01 the optimization levels to determine the best tradeoff
between cache2000 compilation and run times. Trace.h is an
include Iile that must be resident in the same working directory as cache2000.c at the time 01 compilation. The RISC/os
utility makepipe is used to run the pixilied executable and
output the results into the cache2000 standard input file
descriptor 19. Cache2000 generates the performance statistics for the 'cached' target system
A TLB miss penalty 01 13 cycles is assumed lor a random
page replacement algorithm. The TLB size is defined as 56
since the lower 8 TLB entries are not accessible by the

random register. A non-random replacement algorithm can
be simulated by delining the TLB size to be 64. The TLB
miss penalty can be changed to the appropriate value.
Embedded applications often do not implement a demand
paged virtual memory. Typically, these applications bypass
the TLB by running out 01 virtual address segments KSEGO
and/or KSEG1. This can be simulated with cache2000 by
setting the uTLB and TLB miss penalties to O. The ability to
bypass the TLB is important lor real-time applications that
can not tolerate the non-determinism caused by cache misses.
* A detailed description 01 setting up the main memory

read and write latencies lor simulation will be given here.
A lew examples are shown.

define

read_conflict_cbeckO

#endif

1* cache parameters

*/

1* instruction streaming */

/* instruction refill size, in words
#ifndef i_refill_log
•
define i_refill_log2
#endif

/* instruction cache size, in words
iifndef i_size_log
:#
define i_size_log 12
#endif
#define i size (1«i_size_log)

1* data refill size,

in words

#ifndef istreaming
:#
define istrearning 1
#endif

*/

1* memory parameters */
private unsigned wbsize =1;
private unsigned read latency ~;
private unsigned idle=write_tirne ~;
private unsigned page_write_time
2;
private unsigned nonpage_write_time a;
private unsigned byte_extra_wr~te_tirne

*/

#defin~

imiss_penalty
i_refill_size)
#define dmiss_penalty
d_refill size)

*/

#ifndef d_refill_log
#
define d_refill_1og2
#endif

(read_latency

+

(read_latency

+

&;

1* random parameters *1
1* data cache size,
#ifndef d size log
#

define

#ifndef

*/

in words

#

#endif
#ifndef

d_size_log 12

#endif

1*

TLB

#ifndef
:#

#

*1
tlbsize
define 'tlbsize 56

#endif

1* byte gathering *1
#ifndef
#

byte_gathering
define. byte_gathering 0

#endif

1* read conflict checking in write buffer */
#ifndef

utlbrniss penalty
define utlbmiss-penaltyO
tlbrniss_penalty
define tlbmiss-penaltyO

#endi f
hfndef page_log
#
define page log 10
#endif.
private char ·*comment = NULL;
private boolean random flush = false;
private unsigned print interval
2000000000000000;
private unsigned flush interval
2000000000000001l
private double random_flush_parameter;
private double cycletime =50e-9;

read_conflict_check
Figure 10. Cache2000.cModifiable Parameters

UPDATEl C

109

G"

APPLICATION
NOTE
AN-SS

DMA TECHNIQUES WITH
lOT'S R3000/R3001 RISC CPU

Integrated DevIce Technology, Inc:.

By Brent Bush

INTRODUCTION
There. are many cost sensitive applications today that
require high bandwidth data-transfer as well as high compute
power. With its efficient pipeline architecture and tightlycoupled flexible memory-controller, the R3000/3001 CPU's
from lOT prove to be an extremely effective solution. This
application note reveals various OMA (direct memory access)
techniques utilized in high bandwidth R3K deSigns. A general
review of the R3K CPU architecture and performance is given
and is followed by a detailed description of the R3K system
memory-hierarchy and its flexibility. Also, a detailed description of various tightly-coupled OMA approaches is presented.
The MIPS compilers & the R3000 CPU architecture are
based on over 35 staff years of research & development; its
foundation established with compiler optimizing research at
Standford University in the early 1980's. Benchmark comparisons of competitive solutions conducted by lOT customers
have shown that the MIPS solution is clearly the best price/
performance solution in most applications. As a MIPS semiconductor partner, lOT has produced the R3000 since 1988.and
the enhanced version R3000A since 1990.. lOT's agreement
with MIPS includes the right to design and sell derivatives of
the R3000 architecture. The R3001 RISControlier™ is lOT's
first derivative. Improvements were made to reduce chipcount and increase design flexibility. Bus control and timing is
identical to the R3000. The same R3000 (R3K) CPU core is
used in all lOT derivative CPU's, guaranteeing binary compatibility and reducing your time-to-market.

Figure 1 shows the functions found in the R3K core. There
are two tightly coupled processing units. The first is a full 32bit integerthat executes the MIPS RISC (Reduced Instruction
Set Computer) instruction set at 1 cycle per instruction.
Integer multiply and divides are included and are mUlti-cycle
operations that execute in an autonomous unit, allowing other
instructions to execute in parallel. There are dedicated adders
for instruction and data address calculations, eliminating any
possible pipeline stalls due to certain instruction sequences.
The second processor, Coprocessor 0 (CPO) contains a 64entry fully associative Translation Lookaside Buffer (TLB) with
control registers to support a virtual memory system with dual
(instruction & data) caches at full bandwidth. The TLB is part
of the Memory Management Unit (MMU). The MMU provides
adequate address mapping when the use of the TLB functions
is undesirable. Figure 2 shows the Kernel & User as well as
cacheable & uncacheable (I/O) memory segments provided.
Mapped segments require use of the TLB. Kernel segments
o & 1 (KsegO/Kseg1) provide .5 Gbytes of cacheable and
uncacheable memory (each) that is "hardwired .. tothe lower.5
Gbyte of the 4 GB physical address space. All status and
exception registers associated with maintaining User and
Kernel state and precise exception handling are in CPO.

CPO

CONTROL

CPU

(SYSTEM CONTROL
COPROCESSOR)

ARCHITECTURE OVERVIEW
Both The R3000 and R3001 are available at 16MHz to
40MHz in a 175-pin PGA package. There are also plastic &
ceramic surface mount packages available. All common instructions execute in 1 cycle, regardless of instruction
sequence. Two exceptions are Loads & Branches. All pipeline CPU architectures potentially incur latency on these
instructions. The R3K has a "potential" one-cycle latency.
This latency is minimized by always executing, rather than
stalling during the cycle following the Load or Branch (the
"delay" slot). The compiler's instruction rescheduler is highly
successful in filling this delay slot with another instruction,
bringing Load's and Branch's close to one cycle.
A dedicated autonomous unit inside the R3K performs
multi-cycle integer multiply and divide operations. This unit
has dedicated result registers and executes in parallel with
other non-multiply/divide instructions. A hardware interlock
occurs if the result registers are required priorto completion of
the multiply or divide.

4:11991 Integrated Device Technology,lnc.

GENERAL REGISTERS
(32 x 32)

EXCEPTION/CONTROL
REGISTERS
MEMORY
MANAGEMENT
UNIT REGISTERS

LOCAL
CONTROL
LOGIC

ALU
SHIFTER
MULTIPLLlERIDIVIDER

TRANSLATION
LOOKASIDE
BUFFER
(64 ENTRIES)

ADORES ADDER
PC
INCREMENTIMUX

TAG (20+4)

UPDATE1 C

DATA (32+4)
ADDRESS (16)

Figure 1. R3000/R3001 Functional Block Diagram

110

DMA TECHNIQUES WITH IDrs R3000/R3001 RISC CPU

APPUCATION NOTE AN-SS

MMU Address Translation
Virtual - - - - - - - - - - - - _ Physical
Address h'ffffffff
Kenrel Mapped
Cache able
(kseg2)

1024MB {
(TLB)

512MB - (
(hardwired)
512MB
(hardwired)

-r
\

~Any
~

Kernel Uncached
(kseg1)

Physical
Memory

Kernel Cached
(ksegO)

/
2048MB
(TLB)

I- 3548 MB

;j'

User Mapped
Cacheable
(kuseg)

'"a

~Any
~

:e

~.

0"

~

Address h'OOOOOOOO

Ij

512 MB

Figure 2. R3000/3001 Memory Mapping

COMPANION CHIPS
lOT provides many companion chips for R3K designs. The
R3010 is an optional 84-pin floating point accelerator. The
interface to this unit is "seamless". The FPA has it's own
register set & can perform Load and Store operations .
Therefore floating-point operands, opcodes, and results do
not have to be passed tolirom the CPU. A high degree of
parallelism exists in this 2-chip solution. Integer instructions &
multiple floating point instructions can execute simultaneously.
The R3020 is a 4-deep write buffer used to decouple the high
bandwidth CPU from the slower system bus. This is an
effective performance enhancer in data intensive applications. lOT has 7 and 8-deep buffers (IDT73200/201) that
provide deep, efficient read and write buffers. lOT's product
portfOliO includes high-speed logic devices, FI FO's(first in-first
out memories), dual-port static RAMs, and generic static
RAMs at the speeds required for the highest performance
R3K design.

THE R3DDD MEMORY HIERARCHY
(SYNCHRONOUS VERSUS ASYNCHRONOUS)
Figure 3 shows a typical R3000/R3001 system. The CPU's
Synchronous Bus consists of a 24-bit address bus (18-bit for
R3000) and a 32-bit data bus coupled to two banks of generic
static RAMs, one for Instructions and one for Data. It is impdrtant
to realize that the SRAMS provide single cycle access (address
and data) and can be used as a "Cache" or as a "Local" memory.
This bus is decoupled from the slower (multi-cycle) System Bus
resources with a registered interface.

A Cache is nothing more than a mirror image of some
larger, slower memory, used to hold the most recently acquired data. Properly sized caches will contain ~ 95% of the
instruction and data accesses required. When the required
instruction or data is not in the Cache the CPU invokes a multicycle access to the slower, larger "main" memory residing on
the System Bus. Caches are a cost effective way to greatly
increase performance.
When used as a local memory all accesses to the synchronous (cacheable) address space result in accessing the
SRAM's on the Synchronous Bus. There is no slower, larger
memory that maintains the same data.
It is important to define some terminology at this point:
"Synchronous"

Used when referring to the CPU's tightly
coupled, single cycle access bus,
independent of SRAM usage; "Cache" or
"Local" (Abbreviated "sync.")

"Asynchronous"

Used when referring to the multi-cycle
access System Bus. (Abbreviated
'-79R301 OAE-33G.")

Local Memory

Used when the Synchronous SRAM's
are used as a local memory; not as a
Cache in a Cache hierarchy.

Cache

Used when the Synchronous SRAM's
are used as a Cache in a Cache hierarchy system or when referring to the
CPU's internal control features for the
synchronous bus. (To conform to other
documentation.)

UPDATE1 C

111

DMA TECHNIQUES WITH lOTS RSOOO/R3001 RISC CPU

APPUCATION NOTE AN-SS

r---------------------,

I
I

CPU SUBSYSTEM

.---

I-Cache
D-Cache
IDT79R3000/1
Ctrl
Ctrl
Data

(G eneric
S RAM's)

Address

-

200MBYTES/SEC
BUS @ 25Mhz CPU

MemCtrl
(Generic
SRAM's)
Ctrl

Ctrl
Data

Data
AdrLa Bus

Addr

100MBYTES/SEC
CACHES (each)
@25MhzCPU

Addr
DATA
CACHE

INSTRUCTION
CACHE
j

SYNCHRONOUS BUS
(Asynchro naus
Handshake)
READIWRITE
CONTROL LOGIC
(2-4 PALS)

L __

READIWRITE BUFFER
(4 X 29FCT52's)

ADDRESS
REGISTERS

---

J14-

J

(3-4 X 74FCT823)

------1-------

Address

1 - - _...I

}Sy

STEM BUS
(ASYNCHRONOUS)

Data

Cantral

(camm.)

DRAMISRAM
(data/instruction)

(kseg1 )

(ksegO/2 or kuseg)

1/0

EPROM
(Boot code)

(kseg1)

Figure 3. R3000/R3001 System Hierarchy

• Please note that most R3000 documentation uses
"Cache" terminology exclusively when referring to the
synchronous address space.
A key element integrated into the CPU is the Cache
controller. It provides all control lines required to interface to
generic static RAMs for instruction fetching and data Loads
and Stores on the sync bus. No additional logic is required.
. Despite the single address and data busses there is no bus
conflict between instruction fetching and data loads or stores.
The controller "lime multiplexes" the address and data busses, providing a true Harvard Architecture in a small package.
Figure 4 shows the bus usage for each half-cycle phase. The
address and data are acquired during the same cycle. At
25MHz a full 200Mbytes/second is realized regardless of
.
instruction sequence.

During a synchronous read cycle the Cache controller
determines if the required data (or instruction) is in the SRAM.
If required, on the following cycle, a simple read/read busr
handshake is invoked by the controller to perform a multlcycle (asynchronous) access on the System Bus. The CP~
pipeline is "stalled" until data from the asynchronous space IS
available.
Synchronous Store instructions are always single-cycle
events. fullword (32-bit) Stores always update the sync
memory regardless of the hit/miss status of that location.
Partial word (byte/halfword) Stores are 2-cycle readlwrite
events. The sync memory is read to determine if the address
is in the Cache. If a "hit" occurs the new byte/halfword is
merged with the old cached data and then written into the sync
memory. When a Store updates the synchronous data memory

UPDATE1 C

112

DMA TECHNIQUES WITH IDrs R3000/R3001 RISC CPU

APPLICATION NOTE AN"OO

Instruction

Processor

Data
Cache

Cache
(Generic SRAM)

(Generic SRAM)

IWr

WE"
OE*

IRd

DWr
DRd

PHASE 1 TRANSACTION

Addrlo

2

WE"
OE*

PHASE 2 TRANSACTION

1
(Instruction Read)

(Data Read)

1
(Instruction Read)

(Data Store)

Data Addr

Instr. Addr

Data Addr

Instr. Addr

2

-11

DClk

'---+ _ _ _

,\.....-+--

IClk

,~-

IRd

DRd
DWr

I
---J~
I

1
Data and

____

TAG Busses

CPU Data Pins
Figure 4. Harvard Architecture of the R3000/R3001 Synchronous Bus
UPDATE1 C

113

DMA TECHNIQUES WITH

IDrs R3000/R3001

RISC CPU

APPUCATION NOTE AN-88

a write request is always "posted" to the System Bus. The
data, 32-bit address, and access type controls (Le. byte,
halfword, fullword) are supplied for one cycle and must be held
in registers to accommodate the muHi-cycle store operation
on the System Bus. The CPU continues to execute until the
System Bus is required for another access. If the previous
Store is not completed, then the CPU will stall until the write
buffer can accept the request.
In local memory applications these write requests to the
sync space are ignored by the asynchronous handshake logic
to avoid undesired bus stalls. Unlike Cache deSigns there is
no larger memory to update in parallel.

The main memory to Cache size ratio is 2000:1. Therefore,
11 SRAM Tag bits are required. All unneeded Tag bits are
disabled (masked from the address comparison) at Reset with
the R3001. A 4K ohm pulldown resistor is required for each
disabled Tag. The R3000 does not have this feature so simple
buffers are used to supply the addresses required. The buffer's
input value is determined by the system memory mapping.
When a local memory is implemented with the R3001, no
Tag bits are required since all accesses in the synchronous
area are always valid. Therefore all Tag bits and the Valid Bit
are disabled (as described above). This eliminates the 4
SRAM's in Figure 5 supporting Tag25:15 and Valid.

THE SYNCHRONOUS MEMORY CACHE OR LOCAL MEMORY?

INCREASED DMA BANDWIDTH USING THE
CACHE BLOCK REFILL MECHANISM

A ''tag check" is done on all synchronous accesses. (The
Since the synchronous SRAM is accessed in one cycle it
internal Cache controller has no way to determine that a local can be viewed as an extension to the CPU's register stack.
memory has been implemented.) "Tag" bits are required (in Once data resides here there is no access latency and
a Cache hierarchy) to determine whether the requested data routines operating on this data will run very close to 1 cycle per
resides in the Cache. They are an extension to the SRAM instruction. The R3K, with its internal Cache controller has
banks. The number of required Tag bits depends on the size efficient means to bring data into the synchronous SRAM. It
of the cacheable memory residing on the System Bus. A provides support for block refilling of the synchronous SRAM's.
''Valid'' bit is required to indicate that the addressed location in Setting the data block size to a large value can greatly improve
Cache contains a valid entry. Figure 5 is an R3001 example , data throughput. The block size for Instruction and Data is
with 32KB caches supporting a 64MB cacheable main memory. independently configured at Reset, providing 4, 8 16, or 32
word refills per Load instruction.
4Kohm Resistors
(for disable)

~

TAG31 :26,14:13

To System Bus
Address Register

To System Bus
ReadlWrite Buffer

AddrLo
14:2

I:=l

Latch (2x FCT573)
Data Cache
Data Cache
Tags
Data
2x1DT7174
4xlDT7174

/

(4

unus~ bits)

Tag25:15
Valid

R3001

Data

-DWr
DClk

IRd
IWr

DRd

IClk

J,Jj I

f-LE
I" WE

DE

LE---

~
OE

Latcn (2x FC 1573)
Instruction
Cache-Data
4x1DT7174

1

~

Instruction
Cache-Tags
2xlDT7174

(4UnUSe~

Figure 5. R3001 Cache, Design Example

UPDATE1 C

114

DMA TECHNIQUES WITH lOTS R3000/R3001 RISCCPU

APPUCATION NOTE AN-88

Figure 6 illustrates the timing associated with a 4-word
block refill. All signals shown, except RdBusy and CpCondO,
are supplied by the CPU. Refilling occurs when an attempt to
access data in the synchronous address space results in a
"miss". ("0#" means Tag bits did not match or Valid Bit is not
set). This decision takes place during the synchronous access
cycle (Run). During the first Stall cycle the controller invokes
a read protocol (MemRd) to the asynchronous space. The
CPU requires that the data be available one word per cycle
once the refill starts. This is accommodated by various
means; fast memory, dual-banked memory, read pipeline
registers, FIFO's, etc. When the data can be delivered at a one
word per cycle rate the System Bus state machine releases
RdBusy ("read busy") and the internal controller writes the
data into the sync memory. (Called "Refill" cycles). The
"Fixup" cycle is a repeat of the failed Run cycle and is required
to resume the pipeline execution. The address increment
cycle

Run

1 Stall
2

phase

1 2 1

Data:

1 #D 1 II 1

Tag:

1 #D 1 II

AdrLo(23:k):

AccTyp(2)

1

Stall

1 2 1

1

RdAddr(31 :16)

Refill

1 Refill

1

Refill

Refill

1

1 Fixup

1

Run

1 2 1

2

Z 1 D31

1 D21

1 D 1

I~I~I~I~I~I~I~I~I

1 D21

1

1 2 1

HighZ

1 21

1 21

1 2 1 1 1 2 1

Z 1 DO 1 Z 1 D1 1 Z 1 D21

ReadAddress(23:4)

1 D21

1 D21

D

1

1 01

ReadAddress(3:0)

AdrLo(k-l :0):
AccTyp(l :0):

Stall

required for the sync SRAM is supplied by the CPU. Address
increment, if required by the System Bus resource, must be
supplied by its state machine.
The block refill can be disabled to accommodate 1 word
refills by de-asserting the input CpCondO during the last RdBusy
(read busy) cycle. This is a key attribute when other cacheable
resources are accessed in a non-sequential manner.
The block refill mechanism can be utilized in a local
memory design as well as a Cache hierarchy. In a local
memory design the Valid Bit (and all Tag Bits) are disabled. To
facilitate a block refill the Valid Bit is not disabled but is sourced
by an I/O mapped register or high order address to force a
Cache miss. (More on this later.)
The realized bandwidth when utilizing the block refill mechanism can be easily computed. To follow is an example of
generic code used for moving a large block of data and the
associated bandwidth with different block refill sizes.

DataCacheMiss

DAcTy

_____I

(Cacheable Access)

DAcTy 1 DAcTy

\'------

CpCond(O)
RdBusy

-v
Run

JV
/

\r
\

Figure 6. Data Block Refill Timing Sequence (Block of Four Words)
UPDATE1 C

115

DMA TECHNIQUES WITH IDrs R3000/R3001 RISC CPU

DMAloop: Load
Add
Branch

APPUCATION NOTE AN-SS

; for synch_ memory block refill
; (destination = null)
; increment base register by block size.
; to DMAloop if base register not equal to
; maximum value.

This simple loop contributes just 2 cycles of latency per
block refill. ' Due to the Branch's delay slot, the Add & Branch
must be reversed to avoid an additional cycle. Total cycle
count for the loop is:

Careful control of address mapping can maximize the
usage of the sync memory. It could be partitioned into mu Itiple
DMA blocks plus a general usage area. No hardware or
software overhead is required to resolve the "stale data"
problem.

·1 (instr.) + 2 (Stalls min) + N (Refill size) + 1
(Fixup); N = number of words
Branch = 1 (instr.)
Add = 1 (instr.)
Load =

The following table shows the maximum bandwidth achieved
in a 25M Hz system.,
Block
Refill Size

Cycle
Count

4(words)

10(cycles)

40.0 (Mbytes/sec)

40(%)

8

14

57.1

"

57

"

16

22

72.7

"

73

"

32

38

84.2

"

84

"

Bandwidth

• Execute "Odd" DMA block transfer: Starting address =
b..... x1 xx.xxxx.xxxx.xxOO
• Non-DMA code: Data now in sync memory for algorithms. sorting. etc.
• Execute "Even" DMA block transfer: Starting address =
b..... xOxx.xxxx.xxxx;xxOO
Previous data no longer required. Cache miss is
guaranteed due to different address range. (Tags don't
match.) Starting address is "modulo" Cache site!

(%of max_)

The latency, incurred will vary based on the code loop
required and the speed of the asynchronous resource supplying the data. As seen in the figures above, this latency is
greatly minimized by using the larger block refill size.

DMA OBSTACLES IN A CACHE HIERARCHY
Using the Cache controller's block refill capability for DMA
type activity is an efficient way to increase bandwidth but does
raise a key question. In order to invoke the System Bus
protocol for block refilling the sync memory, a'Cache "miss"
must occur. How can the required miss occur if the Cache
already has a valid entry from a previous DMA transfer?
Furthermore. problems occur in cache hierarchy systems
when other bus masters update the cacheable system bus
memory~ In both scenarios. the data residing in Cache has
become "stale". The following are details of various methods
to resolve these issues and a discussion of the tradeoffs of
each method.
1. Explicit address mapping using two (or more) different
address spaces to perform DMA transfers.
Under program control. a subsequent DMA move can
use a different address space to insure the "miss'
required to bring the new data into the sync memory.
(An "Odd" and "Even" DMA address range could be
established.) Data block size can be;;:: Cache size. For
clarification. an example flow of events follows. (A
16KByte data Cache is assumed.)

2. Explicit software Cache invalidation - The R3K caches
need to be flushed (Valid Bit set to 0) at Power-up. This
is done with a simple software routine. Internal status
bits provide means to isolate sync SRAM accesses from
the System space. Executing Store Byte instructions at
this time sets the Valid Bit to 0 (invalid entry). Since the
R3K's Cache line size is 1 word a Store Byte instruction
is required for each word to be cleared. This mechanism
can be used to resolve stale data problems only when
the program has knowledge of the conflicting events and
the associated addresses. The program has control and
will clear only the required area of Cache. leaving usable
data intact. No additional hardware is required to support
this mechanism. (See Appendix-D in MIPS' "System
Programmers Guide for details.)
,3. Explicit hardware Cache invalidation - Some applications cannot accommodate the explicit address control of
methods 1 & 2 or the significant software overhead
associated with method 2."Described below are several
hardware supported methods to control status of the
Valid Bit when dealing with the "stale data" obstacles.
The tradeoffs of each method is briefly discussed.
3a. A resettable SRAM supplying the Valid Bit. An I/O
mapped register can provide a Reset signal that
clears the entire SRAM in 2 cycles. (The 8K x 8
SRAM - IDT7165 is an example.) The other 7 bits of
the SRAM would supply Tag Bits if required. One
Store' instruction plus a fraction of a PAL (programmable logic device) provides a completely cleared
Cache. One potential disadvantage is that good data.
along with the stale is lost.
3b. A Valid Bit "disable switch" to force a miss. An I/O
mapped register is used to set the CPU's Valid Bit
input to O. When the I/O register is set. all sync Loads
result in a miss and subsequent refill. regardless of
the Cache status. The SRAM supplying the Valid Bit
is not cleared and is updated during the refill. The
update is required if the Valid Bit could be previously
o (due to a real "miss"). This requires minimal hardware and software support. does not delete needed

UPDATE1C

116

DMA TECHNIQUES WITH IDrs R3000/R3001 RISC CPU

APPUCATION NOTE AN-aa

SRAM
(Data)

DATA

R30D1

OE

CS

Y

~II

TAG

SRAM
(Tag)

VALID
(to SRAM)

OE

AdrLo

CS

v-ValidCS = RUN or DISSW
BUFFER
(74FCT541)
'-l-

-

OEA

?

Drd

II

-OEB

(NC

en 3:
in ()
()
en

:2 en
1ii
en~ >
5

(Memctrl)

I

SwCS = RUN and DISSW

I
I

Async. Interface

I (ctlr.)

I

ck PAL

QI

AA

III

~

Jl

c:

o ;:;
s.

Figure 7. Valid Bit Diaable Switch (Using 1/0 Mapped Register)

data, and does not require the CPU's knowledge of
the sync memory's content. The Valid Bit must be
connected through a device that satisfies the strict
turn-on!turn-off times of the sync bus; hence the use
of an FCT buffer. Figure 7 shows this feature implemented with an R3001 in a Cache hierarchy and
gives an example of generic code to execute the
operation. (Instruction SRAM is omitted for simplicity.)
Generic Code: Store. ; to 1/0 mapped register, disabling
the Valid
NOP's ; cycle count = cycles to retire 1/0
Store. (Can be any non- data
Cache instruction!)
Load ; Miss forced, block refill occurs.
(Beginning of DMA , etc.)
; Loop for data block moved into
Cache.
Store

; to 1/0 mapped register, restoring
Valid Bit to normal. (End of DMA,
etc.)
NOP's ; cycle count = cycles to retire 1/0
Store. (Can be any non- data
Cache instruction!)
; Resume normal code. DMA data
now in Cache

An alternate method to control this "miss switch" is to simply
use a high-order address bit that is beyond the cache able
address range. This implies that for all normal sync accesses
this address bit is not set. The user program, requiring the
forced miss, sets this bit in the index or in the base address
registerusedforthe block-refill Loads. This requires even less
hardware support and offers more code flexibility. When using
the 1/0 mapped register method, (Figure 7), synchronous
Stores cannot occur because the Valid Bit SRAM is not
enabled during Run cycles. This limitation does not exist when
using an address bit for the disable mechanism. Figure 8
illustrates the needed control. (Instruction SRAM is omitted for
simplicity.)
In a local memory design (no Cache hierarchy) this circuit is
further simplified. Normally, in an R3001 local memory design
the Valid Bit (and all Tag Bits) are disabled at Reset and need
not be driven. To facilitate a block refill (for DMA, etc.) the Valid
Bit is not disabled but is sourced by a register to force the miss.
This Valid Bit source must still be output enabled by the CPU
controls "lrD" and "Drd" because it is driven during sync Stores
and Load Refills by the CPU. The strict timing therefore applies.
See Figure 9 for an example implementation.

UPDATE1 C

117

a

DMA TECHNIQUES WITH lOT'S R3000/R3001 RISC CPU

APPUCATION NOTE AN-88

SRAM
(Data)

DATA

-

R3001

OE

CS

Y

~Ii

TAG

SRAM
(Tag)

VALID

AdrLo

r---

~

'---

T

Dclk

'1

(to SRAM)

LE ~

CS

OE

,-:r:
AdrL023

BUFFER
(74FCT541)
OEA

OEB

y

Drd

~

/4

"MISS
. when low"
Figure S. Valid Bit Disable Switch (Using AddrLo bit)

SRAM
(Data)

DATA

DE

R3001

CS

YII

TAG l(Notused)

(Needed to insure
"Hit" on Instructions)

VALID

I

r-

:r:
AdrLo -

()

5

(toSRAM)

~

LE I--Dclk

»
a.

-

i"0

OEA

""

y

I\)

Drd

"logic1
BUFFER Br--(74FCT244)
"Miss when low"
- A IOEB

y

/

Ird

Figure 9. Valid Bit Disable Switch in a Local Memory Design

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OMA TECHNIQUES WITH lOT'S R3000/R3001 RISC CPU

APPLICATION NOTE AN-88

I

Tag

Latch

Data
AddrLo

'573

f---

DATA CACHE

r-- ,....-

-

ID179R3000A

1

Cache Ctrl

MP
Invalidate

MPstall

i

1
Invalidate

l-

Stall

AddrLo

Bus Monitor
• Monitor other Master's Writes
• Latch System Address
• Stall CPU
• Drive AdrLo bus with contention address
• Assert Invalidate (CPU writes Valid Bit = 0)

Async.I/F

Address, Control

I

SYSTEM BUS

I

Figure 10. R3000 Multiprocessor Cache Invalidate

Tag

1

Data
AddrLo

r-Latch
('573's)

-

T

Cache Ctrl
IDT79R3001
RISControlier

Latch
('573's)

Sychronous
Data
Memory

t

,-L

-

DMAStall

r---

1

-

-

1
l

Sychronous
Instruction
Memory

Il -I--

t
Req.

AddrLo Cache
Ctrl

I

Tag
DMA
Controller

Async IIF

Async.I/F

I

Ctrl
Memory
or 1/0

Main Mem Clrl

J

Figure 11. R3001 OMA Interface

UPOATEl C

119

APPLICATION NOTE AN-SS

OMA TECHNIQUES WITH lOT'S R3000/R3001 RISC CPU

3c. Using the R3000's multiprocessor hooks for Cache
invalidation. Solutions to the "stale data" problem
discussed require CPU participation. They do not
provide support in a Cache hierarchy where an
autonomous System Bus master updates the
cacheable System memory. (The CPU is unaware of
the transaction.) The R3000 has a 2-signal protocol
(MPStall,MPlnvalidate) to invalidate entries in the
data Cache. An independent state machine monitors
the System bus for cacheable writes by another bus
master. When detected, the address is stored in a
register and the MPStall is asserted. The R3000 tristates its address bus and this System Bus "snooper"
supplies the Cache address. When MPlnvalidate is
asserted, the R3000 clears the Valid Bit at that entry.
Figure 10 is a simple block diagram showing the
hardware to support this feature.
This example does not compare the cache's tags to the
address of the System Bus write. This means that the data in
the Cache may have been from a different address (modulo
Cache size) and invalidating that location was not required.
Invalidating without address comparison may result in reduced Cache hit-rates and loss of performance. The Tag Bits
can be read for comparison during MPStall cycles prior to

invalidates. This isdonewith 1 ormore Octal comparators (i.e.
IDT74FCT521). This extra step will omit anyunneededCacheentry invalidation.

THE R3001 DMA FEATURE
lOT added hooks to the R3001 providing access to the
synchronous memory by an autonomous controller. While the
"DMAStall" input is asserted the R3001 stalls and tri-states its
outputs allowing complete control by the external master. This
is a valuable feature when data transfer under program control
is prohibitive or undesirable. Figure 11 illustrates the system
connection of an external DMA master to an R3001 system.
In this example the CPU's asynchronous interface is utilized
to access resources. During DMAStall sourcing the Tag Bus
is required to update the Cache tags if a Cache hierarchy
exists or to supply high-order address lines during an asynchronous access.
The DMA Controller's bandwidth can exceed the CPU's
bandwidth. A 25MHz R3K has a 100MBytes/second data
bandwidth and requires 20 nanosecond SRAM. These SRAM's
can support cycle times of 20 nanoseconds. Therefore, a
carefully designed DMA controller could approach a
200Mbytes/second data bandwidth when using a separate
clock source.

DATA BUS

DWr'
DRd'

128KB
Sync. SRAM
WE (4 x IDT71256)
OE

Add
Ol

.

:u

"0
"0

cD <:'!
00

« «

"0

AdrLo23,16:9

AdrLo23,8:2
DClk

-

CS

.

'" '"

C\J
"0
"0

C\J
"0
"0

« «

D
00 0 0
LE 1 x FCT841T
LE 1 x FCT533T
D

f--c
I---<

LEAB
OEBA
CEBA
LEBA CEAB

Latched Transceivers
(4 x FCT543's)
PORT-B

OEAB

1

-1

-b
-

FIFO DATA

r--LA23 ,

~ CSA PORT-A
Add5:2 '

LA5:2 '
~:n
or- ~
-0

-

:::. LDWr'

~

OEA

EiilA <= LDWr' or LDRd '
RIWA
~ A2:0
Bidirectional
Synchronous FIFO
(2 x IDT72615's)
PAEba
.r"'

LDWr'~

-'~

«oc

Il..~

LDRd'

(to insure hold time)/[

-

0

M

~LL
-x

(Latch)

DWr'
DRd'

SysOut'

PORT-A

r--

Of-CK

1

1
SysReset'

, R3 001 '
Inte rface

Run'
To CPU Interru pts )

CLKA RS

PORT-8

I
(TO 110, 2nd CPU, etc)
(Controls nat shown

Figure 12. lOT Bidirectional FIFO's on the Synchronous Bus
UPOATE1 C

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DMA TECHNIQUES WITH IDrs R3DDD/R3DD1 RISC CPU

APPUCATION NOTE AN-SS

Another use of the DMAStall feature is preloading the
Instruction memory. This might be useful at power-up to bring
code from I/O space to local memory or to Cache (to "lock"
portions of speed critical code). This preloading is normally
done by swapping the data and instruction memories (Le.
special internal control bits) and executing a Load (from I/O
space) Store (to sync memory) routine.

"ZERO LATENCY" DMA USING IDT'S
72605/615 BIDIRECTIONAL FIFO
Most R3K design examples show the synchronous bus
with one memory bank to supply data. Because of the split
cycle timing required to "ping -pong" between instruction and
data resources, timing restrictions apply. However, by using
the CPU's control lines and unused sync address lines additional data resources can reside on the synchronous bus. A
second data path can be mapped into the synchronous space,
providing DMA transfers at the full CPU bandwidth (100
MBytes/sec @ 25M Hz) without latency.

AddrLo23

AddrLo22:7

AddrLoS

AddrLo4:2

0

x

x

x

Figure 12 illustrates 2 of IDT's 512 x 18 bidirectional
synchronous (clocked) FIFO's interfaced to the synchronous
bus. This device contains separate ('A to B' and 'B to A') FIFO
banks providing a 200MByte/sec. duplex bandwidth in a
25MHz system. The ports are registered and allow freerunning clocks. Flags provide buffer depth information that
can interface to the CPU's interrupt or status inputs. (Formore
details on this device refer to Section 6.21 in lDT's '.'1990/91
Specialized Memories" Databook.)
This example details the described technique in a "Local
Memory" approach with the R3001. 32Kx 8 SRAM's are used
for 128KB of local data and instruction memory each. A highorder address bit beyond the range of the local memory is
used to "bank select" between. the data SRAM and FIFO
operation. (See Figure 13 for a function address map for this
example.)

Function

Comments

implement SRAM or 1/0

0

x

x

x

implement SRAM or 1/0

1

x

x

0

Fifo data write during Store's

1

x

x

001

Fifo bypass write during Store's

1

x

x

1xx

Fifo offset reg. write during Store's

1

x

x

0

1

x

x

001

Fifo bypass read during Load's

1

x

0

1xx

Fifo offset reg. read

normal offset reads

1

x

1

11x

Fifo offset reg. read

FIFO now drives Bus

1

x

1

10x

Fifo offset reg. read

543 now drives Bus

1

x

1

01x

Reset PAL interrupt

(R3001 requirement)

Fifo data read during Load's

NOTE: ·x- = don't care

Figure 13. Function Address Map

Address mapping of resources on the asynchronous bus
must have Address23 = 0 to avoid erroneous FIFO reads.
(The control signal "Drd", always goes active during the first
("Run") cycle of any async. access.)
The FIFO's can't connect directly to the sync bus due to
strict output enable/disable timing requirements. "Drd" must
connect directly to the bus device. Therefore, a "gated" outputenable is required to perform the bank switch. This is
accomplished by using the SRAM's chip select (normally tied
active) and FCT543's forthe FIFO path. The 74FCT543T is a
bidirectional transceiver with separate latch and output enables that are gated with a chip select.
A transparent latch (74FCT573) is used to hold the CPU's
sync control signals for an additional half cycle. To ease timing
at high speeds, the FIFO operation occurs during phase 1 of
the following cycle.

FIFO READS
Because of the registered output of the FIFO, a one-cycle
latency is incurred for the first word. This occurs only when the
buffer status goes from "Empty" to "Not Empty". This design
example assumes that the data block sizes are known;
therefore, once FI FO reads begin, Empty status will not occur
until the last word of the block is read. If,Empty was reached
before the last word is read the program will load incorrect data
into the Load's destination register.
When Empty status is completely deterministic, the 1-cycle
latency is always handled by the execution of an initial
"dummy" read from the FIFO. If this is undesirable the control
PAL could initiate the dummy FIFO read upon deassertion of
the EMPTY flag, thereby eliminating the latency.

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121

APPUCATION NOTE AN-SS

DMA TECHNIQUES WITH IDT'S R3000/R3001 RISC CPU

The PAE (Programmable Almost Empty) output from the
FIFO is used to invoke an interrupt, alerting the CPU to
present data in the FIFO (when it de-asserts). The offset
(from) can be set to any value and can be changed in between
transfers to accommodate different block sizes and/or transfer rates. It is set to a value that guarantees Empty will not be
reached before the entire data block is read by the CPU. This
value can be ''fine tuned" to minimize the CPU response time
when the data source's rate is known.
The R3001 has inputs (called CpCond3:0) which are used
by special conditional branch opcodes. This is an alternate
(and faster) way to respond to the FIFO status. If the CPU is
waiting for data from the FIFO, it can sit in a 2-instruction loop
and branch immediately upon the receipt of the FIFO's flag.
Figure 14 shows example generic code to read a small
block of FIFO data into the CPU's general registers to be used
for computation.

FIFOread: Load

;from FIFO, destination = null (1 st
word pipeline latency)
Load
;1 st word into general register
Load's ; Additional loads equal to number of
available registers

Compute:

100% of the maximum bandwidth (100 Mbytes/second at
25MHz) is realized. Obviously, the limitation is based on the
number of registers available (maximum of 32). A Load/Store
(from FIFO/to local SRAM) routine can accommodate any
block size at 50% of the maximum bandwidth. Recall that
Loads & Stores execute in 1 cycle on the Synchronous Bus.
The local SRAM can be viewed as an extension to the CPU's
register stack. Figure 15 illustrates the timing for FI FO reads
(including the initial "dummy read").

FIFO WRITES
Bandwidth capability for CP U writes to the FI FO is identical
to FIFO reads. Unlike Reads, there is no latency associated
with Writing the first word into the FIFO. However, to simplify
timing on the FIFO bus, a "dummy" read is done to the FIFO's
internal offset register to turn the (FIFO to '543's) bus around.
Address bit 5 invokes the operation and Address bit 4 is used
to determine direction. (See address function table, Figure 13)
The Output Enables of the 543's and the FIFO's are sourced
by a registered PAL. Skew between the two outputs represent
minimal driving contention at a time the data is not used. No
damage to the parts will occur.
Figure 16 shows example generic code to write a small
block of data into the FI FO. Timing for the firsttwo FI FO writes
is also illustrated.

Add,Sub, etc. ; OR Store to sync data SRAM's

Figure 14. Example Synchronous FIFO Read Routine

Phase 1

Phase 2

(Instruction Read)

(CPU Data Read)

Phase 1
(Instruction Read
& FIFO Read)

Tsys

Phase 2
(CPU Data Read)

Phase 1
(Instruction Read
& FIFO Read)

Phase 2
(CPU Data Read)

PhiOul O
SysOul

O

--HI--.JI

AddrLo

DClk
DRd

!

(SysOul O)t

FIFO DATA

DATA BUS

Word 2

--+----{
Instr. RAM

Figure 15. Synchronous FIFO Read Timing

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DMA TECHNIQUES WITH lOT'S R3000/R3001 RISC CPU

FIFOwrite: Load
Store's

APPLICATION NOTE AN-88

; Special to turn FIFO bus around.
(543's now driving Bus)
; Number of Stores equal to number of
available registers

Figure 16. Example Synchronous FIFO Write Routine

This FIFO deSign can be used in both Cache hierarchy and
local memory designs. However, when using the data memory
as a Cache (a portion of) the TAG inputs are supplied by
SRAM. These Tag inputs must be supplied by a second
device (i.e. 541 buffer) to insure the "hit" when the FIFO is
read. The 541 inputs are "hardwired" to the address range of
the FIFO. The 110 resources, cacheable async. memory, must
be mapped so Address23 = 0 to prevent erroneous FIFO
reads.
Connecting a second data resource onto the sync bus is a
simple way to greatly improve latency and bandwidth in an
R3K system. Logic parts like the FCT543T and FCT541 T
provide the gated output enable necessary to satisfy the bus
timing, providing single cycle access to other system
resources.

SUMMARY
This article explores various ways to improve data throughput in an R3000/3001 design. Other detailed references
(listed below) are available for further study. When the R3K
architecture was introduced, it gain immediate popularity as a
workstation CPU .. Since introduction, however, lOT has
realized many designs in other application areas, such as in
embedded systems, that exploit the true potential of the
architecture. With the internal cache controller, true Harvard
Architecture, simple System Bus protocols, flexibility, speed,
and small footprint, the R3000/R3001 fit the needs for a wide
variety of systems designs.

REFERENCES
• MIPS RISC Architecture by Gerry Kane
• lOT RISC Oatabook, 1991
lOT R3000/3001 Designer's Guide, 1990
lOT RISC R3001 RISControlier Handbook, 1990
lOT Specialized Memories Oatabook, 1990/91
• lOT Logic Oatabook, 1990/91
lOT RISC R3000 Family Language Programmer's Guide
lOT RISC R3000 Family Assembly Programmer's Guide
• lOT RISC R3000 Family System Programmer's Guide

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t;)"

R3051™ FAMILY PERFORMANCE
IN EMBEDDED APPLICATIONS

APPLICATION
NOTE
AN-89

Integrated Device Technology, Inc.

By V. S. Ramaprasad

INTRODUCTION
The IDTR3051"M is a family of RISC controllers specially
suited for embedded applications. Instruction and data caches
are integrated on the chip to yield cache hit rates of over 90%
for a wide range of typical embedded applications. These
RISC controllers also provide the designer with a simple
interface to the rest of the system through built in readlwrite
buffers, a multiplexed address/data bus and a small set of
control signals. This simple interface enables the designer to
select an optimal price/performance memory and I/O system.
In this application note the performance of a 33 MHz R3051
based system is presented. Standard integer benchmarks are
run on the software model ofthe R3051 DRAM based sytem,
and the results obtained are compared with the published
results for 33 MHz i960 and 33 MHz 29K RISC processor
based systems. The performance of R3051 based systems
can be attributed to the raw horse power of R3000A core
coupled with the highly desired optimal integration provided
on the chip.

SYSTEM DESCRIPTION
The 33 MHz R3051 based system modelled is made up of
80ns DRAMS with a page mode access time of 50ns. The refill
sizes for both the caches is four. The processors burst mode
of access is utilized for refilling both the caches on cache
misses. This implies that after the initial latency cycles the
2-way interleaved main memory is capable of supplying the
subsequent instructions or data at the processor speed. The
instructions are streamed into the processor along with the on
chip cache refill.
The 33 MHz R3051 system is modelled with a software
simulation tool called Cache305x. This software is based on
the Cache2000, which is part of the Systems Programmers
Package developed by MIPS Computer Systems. Cache2000
is used to model R3000/R3001 based systems with more than
98% accuracy of simulation.
To accurately model R3051 based systems, the existing
Cache2000 is modified. Besides setting the cache sizes, the
block refill sizes, the write buffer depth etc, sections are added
to the Cache2000 program to simulate the bus priority scheme
adopted by the R3051 family for processing the main memory
transactions, and to implement the read/write protocols.
Memory transactions are listed here with descending order of
priorities. DMA activity is assumed not to be present in these
simulations.
1. Current transaction completes without preemption.
2. Instruction cache misses are processed.
3. Data residing in the four deep write buffer is retired to
the main memory.
4. Data cache misses are carried out next.
e1991 Integrated Device Technology, Inc,

The read/write operations follow the priority scheme. The
initiation of either of these transactions depends on the
pending memory transaction requests. The built-in bus a~bi­
tration logic resolves the conflict forthe memory bus following
the above mentioned priority scheme. The arbitratio~ unit
operates in parallel with the execution core. The core could be
executing instructions from the caches, while the bus arbitration unit is retiring the writes currently residing in the write
buffer.
For instruction cache misses, in the best case where there
is no write in progress, a read signal to the external memory
is initiated one cycle after the core missed in the instruction
cache. This extra cycle is forthe arbitration unitto generate the
read signal request. On top of this arbitration cycle, if a write
is currently in progress, the processor stalls till the write
operation is terminated. In this case, after write operation a
DRAM based system needs to be pre-charged before the read
operation. The first instruction is read into the processor after
the initial read latency of the memory system. The remaining
three instructions are read in three consecutive cycles. After
the reads, the DRAM pre-charge cycles are added to the total
.
cycle count.
Fordata cache misses, there is an extra penalty of flushing
the contents of the write buffer besides the extra one cycle for
the arbitration. The number of cycles it takes to flush the write
buffer depends on the number of words that are resident and
also whether they could be retired as idle writes,. or page
writes, or non page writes. In the current system tha~ is
modelled, four words of data is brought in on a cache miss.
The first word is read into the processor after the initial read
latency of the memory system. The remaining three words are
read in the following three consecutive cycles. Afterthe reads,
the DRAM pre-charge cycles are added to the total cycle
count.
The write buffer interface decouples the core processor
from the external slow memory system. Writes are retired in
parallel with the processor executing out of t~e cache~. In ~his
state of execution, write operations always Win the arbitration,
and continuously retires the writes. This parallel mode of
operation gets terminated only when the write buffer is full and
a store is pending or when the processor can no longer
execute out the caches. Keeping in mind that our interest in
these simulations is the total cycle count for the complete
execution of the program, write operations contribute to the
total cycle count only when the processor needs to read from
the external memory or when the processor can not proce~d
with the execution of a store instruction because the write
buffer is currently full.
The penalty cycles due to writes delaying the pro?essor
external reads on cache misses are accounted for dUring the
read transactions. When the write buffer is full and the

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124

APPLICATION NOTE AN-89

R3051'" FAMILY PERFORMANCE IN EMBEDDED APPUCATIONS

processor is executing a store instruction, penalty cycles that
would vacate a single entry in the write buffer is added. This
is not the same as retiring a single write, but it is equivalent to
four cycles. This is due to the availability of an extra data
register that captures the data being vacated from the write
buffer. If another store follows in this situation where the four
entries of the write buffer are full and the extra data buffer that
drives the bus is loaded, the penalty is that of retiring a write
to the memory.

DRAM PARAMETERS
The memory system considered in this R3051 design is
made up of SOns DRAMs with page mode access time of 50ns.
The other parameters ofthe DRAM that affect the access time
in different modes of DRAM are the initial read latency cycles,
numberof cycles to perform a write operation when the DRAM
is in idle mode, number of cycles to perform a readiwrite
operation when the DRAM is in page mode, number of cycles
to perform a write operation when the DRAM is not in page
mode. The parameters are set to fixed values to model a
DRAM system that works with R3051 running at 33 MHz.
The initial read latency cycles at 33 MHz is the summation
of the cycles to win the intemal arbitration (1 cycle), cycles for
the DRAM controller to generate RAS/CAS signals and perform a random read from the DRAM (6 cycles). The first word
of instruction/data is read in the fixup cycle (1 cycle) . The
remaining words are read in the three following cycles. It
should be noted that the DRAM pre-charge cycles are part of
the 6 cycle random read latency mentioned above.
The idle write latency is the number of cycles to retire a write
when the DRAM is in idle mode. Using SOns DRAMS this can
be accomplished in 6 cycles. The page mode read or write
operations can be completed in 3 cycles, while the non page
writes can be carried out in 6 cycles. In the current system that
is modelled with Cache305x, DRAM RAS pre-charge cycles
are added when a read follows a write operation.
DRAM Parameters @ 33 MHz
Read Latency

7 Cycles

RAS pre-charge

3 Cycles

Idle write

6 Cycles

Page write

3 Cycles

Non page write

6 Cycles

COMPETITION
In this application note two other RISC systems, namely the
i960 and the 29K, are compared with the R3051 DRAM system.
The Intel i960CA system is the ASV960CA board running
at 33MHz with 0 wait state memory for instructions and 3 wait
state memory for the data. The memory is implemented with
15ns SRAM. Internally the i960CA has 1 KB of instruction
cache memory. The benchmarks are compiled with 1.35
GCC/960 (results obtained from Intel).
The 29K system is the YARCs card running at 33 MHz
using RevD AM29000. It has a 2 MBytes of instruction
memory, and a 512 KBytes of data memory. The memories

are implemented with 35ns Static RAMs (results obtained
fromAMD).

STANDARD INTEGER BENCHMARKS
Several standard integer benchmarks are run on the 33
MHz R3051 based system using the Cache305x. They are
Quicksort, Bubblesort, Pi500, Anneal, Matmult, and
Dhrystonel.1. (0) The suite was selected by Intel, these
benchmarks are selected because of (1) the availability of
results for two other RISC procesors, namely the i960 and the
29K, and (2) though being small, they still provide an insight
into the capability of the processor in embedded
environments.
Quicksort performs sorting of 5000 elements of an integer
array using a recursive algorithm.
Bubblesort manipulates and sorts an array of 500 elements
after reading a file.
Pi500 computes the value of the mathematical constant 'Pi'
upto 500 decimal points. This program does not use any
floating point math, but more than 50% of the cycles are spent
in integer multiplications and integer divisions.
Anneal program solves the travelling-salesman problem by
the method of simulated annealing.
Matmult is a program that loops for 100 times, and in each
loop it performs the multiplication of two SxS integer arrays.
The .result is stored in another 8x8 array.
Dhrystone 1.1 benchmark demonstrates the integer numbercrunching powerofthe processor, although it is susceptible
to compiler optimizations. Dhrystone 1.1 is reported here for
the R3051 system instead of Dhrystone 2.0 for lack of data for
the i960 and the 29K.
All the above mentioned integer benchmarks are Compiled
with a C compiler version 2.0 on an M/120 system running
RISC/os 4.0. Except for Dhrystone benchmark, all the other
benchmarks are compiled with the highest level of optimization 04. This includes optimization techniques such as global
register allocation, optimal calling sequences, common subexpression elimination, procedure merging/inlining etc. For
Dhrystone, 03 level of optimization is used. This level of
optimization does not include procedure merging as it is
against the spirit of Dhrystone benchmarking.
The results for R3051 are listed below along with the results
published for 33 MHz i960 and 29K. The execution times for
above mentioned programs are shown in the table (smaller
values are better except for Dhrystone 1.1).
BENCHMARK

lOT R3051-33

1960CA-33

QUICKSORT(ms)

36

50

29K-33
46

BUBBLESORT(ms)

41

85

59

PI-500(ms)

1,023

1,624

1,282
7,205

ANNEAL(ms)

5,056

8,388

MATMULT(us)

19,148

26,898

44,578

DHRYSTONE 1.1

55,236

41,030

50,301

• R3051 system is SOns DRAM based system.
• i960CA-33 system is ASV960CA with 0 ws for code and 3 ws for data.
• 29K-33 system is YARC card with 35ns SRAMs.

UPDATE1C

125

a

R3051™ FAMILY PERFORMANCE IN EMBEDDED APPLICATIONS

APPLICATION NOTE AN-89

lOT R3051 vs Intel i960CA vs AMD29K
2.0

1.5

Relative to 1.0
3051-33

•
•

R3051-33
i960CA-33

m!

29K-33

0.5

0.0
Quick

Bubble Pi-500

Anneal Matmul Dhry1.1

CONCLUSIONS
The standard integer benchmarks, even though they do not
represent any real applications, provide an insight into the
inherent performance of a processor when running typical
embedded applications. The R3051 system considered here
is a DRAM based system, and still delivers more performance
comparedtothefastest i960CAand 29K based designs. It can
easily be deduced from the above data that the i960CA 33
MHz system is actually equivalent to a21.2 MHz R3051 based
system, and the 29K 33MHz system is equivalent to a 23.1
MHz R3051 based system. Still faster R305x systems are
feasible when designed with Static RAMs and it is reasonable
to expect further gains in performance.

UPDATE1 C

126

1991 SRAM DATA BOOK

1991 DATA BOOK UPDATE 1
TABLE OF CONTENTS
LAST BK.

UPDATE PG.

1991 SRAM DATA BOOK UPDATES
PARTIALLY UPDATED DATA SHEETS
IDT6116
2K x 8 with Power-Down .....................................................................
IDT61298
64K x 4 with Output Enable and Power-Down ....................................
IDT71256
32K x 8 with Power-Down ...................................................................
IDT7164
8K x 8 with Power-Down .....................................................................
IDT61 B298
64K x 4 BiCEMOS with Output Enable ...............................................
IDT61 B98
16K x 4 BiCEMOS with Output Enable ...............................................
IDT71 B256
32K x 8 BiCEMOS ..............................................................................
IDT71 B258
64K x 4 BiCEMOS ..............................................................................

D5.1 .............
D5.2.............
D5.10 ...........
D5.17...........
D6.1 .............
D6.2.............
D6.8.............
D6.9.............

UPDATED FULL DATA SHEETS
IDT71589
32K x 9 Burst Mode with Power-Down ............................................... D5.16...........
IDT71B229
16K x 9 x 2 BiCEMOS Cache RAM .................................................... D6.7.............

D-2
D-3
D-3
D- 5
D-5
D-6
D-7
D-8

D - 12
D - 20

1991 SRAM DATA BOOK

Partial Changes to Data Sheets

The following section contains partial data sheets that appeared in the 1991 SRAM Data Book. These data sheets
had changes to less than 50% of the overall contents. Refer to the bars above changes to see where that section
can be found in the 1991 SRAM Data Book.

UPDATE1 0

IOT6116

Data Book 0, Section 5.1, Page 2

PIN CONFIGURATIONS

INDEX

.:l

~

0

.!f.li: ~.f .if

A7

A6

As

k3

5

A2

6
7
8
9

A4
A3

NC
NC

A2
A1
Ao

A1
Ao

1/00

L28-1

10
11

1/00

1101
1/02
GND
2954 drw05

28·PIN LCC
TOP VIEW

2954 drw01

DIP/SOIC/CERPACKISOJ
TOP VIEW

IN

:1:!!!l: ~ ~ ~

INDEX

Ag
A4
A3

As

]4
]5

NC

A2 ]6
A1
Ao

1/00
1/01

L24-1

]7
]8

] 9
] 10
11 12131415
..................................
..... CI C\I C") v

,........,

'"

II

I,

"

•

Qz9QQ
-(!}--2954 drw 04

2954 drw03

24-PIN Lce
TOP VIEW

32·PIN Lee
TOP VIEW

IDT6116

Data Book 0, Section 5.1, Page 3

IgijELECTRICAL CHARACTERISTICS

(1)

vcc = 5.0V ± 10%, VLC = 0.2V, VHC = Vcc - 0.2V

Parameter

Unit

Operating Power Supply
Current, CS = VIL,
Outputs Open,

mA

IDT6116

Data Book 0, Section 5.1, Page 6

AC ELECTRICAL CHARACTERISTICS

Unit

Parameter
tOH

ns

Output Hold from
Address Change

UPDATE1 D

2

IDT61298

Data Book D, Section 5.2, Page 2

PIN CONFIGURATION
INDEX
. , ' . . . . I, .

32LJ2a27
:1
:1
A4 :1
A5 :1
A6 :1
A7 :1
As :1
A9 :1
CS :1
A2

4

26 [

A15

A3

5

1

25 [

A14

6

24 [

A13

7
8

23 [
22 [

A12
An

9
10

21 [
20 [

A10

11

19 [

L28·2

12
18 [
13 14 15 16 17

......

1/04
1/03
1/02

.

r-1,......,,.......,......," ,.-,

,

11I1~~I~~

2971 drw 02a

LCC
TOP VIEW

IDT61298

Data Book D, Section 5.2, Page 3

DC ELECTRICAL CHARACTERISTICS(1)
(Vcc

= 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
61298520
61298L20

Symbol
ISB1

Parameter

61298525
61298L25

61298S35
61298L35

61298545
61298L45

Mil.

Unit

35

35

rnA

4.5

4.5

Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l.

Power

Com'l.

Full Standby Power
Supply Current (CMOS Level)

S

30

30

35

30

35

30

;iiatlli$Y~iw'~:I~$lrt fi ~!IItJr~~~r

L

1.5

1.5

4.5

1.5

4.5

1.5

IDT61298

61298555
61298L55

.

Data ·Book D, Section 5.2, Page 4

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
VHC = VCC - 0.2V ••..••....••••.. ='--_ _ _-.-_ _ _.--_ _ _-;:-;-_ _, -_ _ _ _ _ _,-_-,

Unit

Parameter
Chip Deselect to Data
Retention Time

ns

IDT71256

Data Book D, Section 5.10, Page 3

DC ELECTRICAL CHARACTERISTICS(1, 2)

= 5.0V ± 10%, VLC = 0.2V

VHC

= VCC -

Parameter
Dynamic Operating Current
CS ~ VIL, Outputs Open
Vce = Max., f =fMAX(3)

I----t""
ISB1

UPDATE1 D

3

IDT71256

Data Book D, Section 5.10, Page 3 (con't.)

Unit

Parameter

rnA

Dynamic Operating Current
CS S VIL, Outputs Open

Vcc = Max., f = fMAX(3)
rnA

1DT71256

Data Book D, Section 5.10, Page 5

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
VLC

= O.2V, VHC = vcc - O.2V

IDT71256

. - -- - -

Data 'Book D, Section 5.10, Page 6

AC ELECTRICAL CHARACTERISTICS
71256545

IDT71256

'

'"

Data Book D, Section 5.10, Page 7

AC ELECTRICAL CHARACTERISTICS

Symbol

Parameter
2968 tbl t t

UPDATE1 0

4

IDT7164

Data Book D, Section 5.17, Page 3

DC ELECTRICAL CHARACTERISTICS(l)
(Vcc

= 5.0V ± 10%, VLC = 0.2V, VHC = Vcc - 0.2V)
7164515
7164L15

7164520(4)
7164L20(4)

7164525(4)
7164L25(4)

7164530
7164L30

Unit
mA

Unit

Parameter

mA

Standby Power Supply Current
(TTL Level), CS, ~ VI~~g~:!CS2:5 VIL
VCC = Max., Outputs Open, f = fMAX(3)

5
20
L

mA

0.2

IDT7164

Data Book D, Section 5.17, Page 4

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V

Unit

Parameter

ns

Chip Deselect to Data
Retention Time

IDT61 B298

Data Book D, Section 6.1, Page 2

ABSOLUTE MAXIMUM RATINGS(l)

RECOMMENDED DC OPERATING
CONDITIONS

NOTES:
gi:!!itgR!!mm~tMl~~§§m.E'4~tl!gj§'WH:L:::::::::;,

IDT61 B298

Data Book D, Section 6.1, Page 3

DC ELECTRiCAL CHARACTERiSTiCS(l)

Parameter
lee

Dynamic Operating Current
CS = VIL, Outputs Open, Vee = Max .. f = fMAX(2)

UPDATE1 D

5

IDT618298

Data Book 0, Section 6.1, Page 4

AC ELECTRICAL CHARACTERISTICS (Vee = 5.0V ± 10%, All Temperature Ranges)
Parameter

IDT61898

Data Book D, Section 6.2, Page 1

FEATURES:

IDT61898

Data Book 0, Section 6.2, Page 2
RECOMMENDED DC OPERATING
CONDITIONS

DC ELECTRICAL CHARACTERISTICS
Vee = 5.0V ± 10%)11.11!11~1111
IDT61 B~8

~

Data Book D, Section 6.2, Page 3

DC ELECTRICAL CHARACTERISTICS(1)
(Vee = 5.0V ± 10%):!t§J.fIB::¥§§:lil:Ii.~:~t~&ll
Parameter
NOTES:

W:tY,%iM'j¥m:EmIB~'*,*)*::_r

IOT61 B98

Data Book D, Section 6.2, Page 4

AC ELECTRICAL CHARACTERISTICS

3000tbi DB

UPDATE1 0

6

ORDERING INFORMATION

XXX

x

Speed

Process!
Temperature

R'y8."k~

L - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

IDT71 B256
__ "",.•= ,

_~"'~.

~~~""...".'",

,)o<~Z'''<

~

~8

Speed in Nanoseconds

"''1i'~<-'"'''''i~_'''''''''_''''''''~'''

ABSOLUTE MAXIMUM RATINGS(l)
Symbol

~¥Ii~I~1

Rating

Com'l.

Mil.

Unit

Terminal Voltage
with Respect
teGNO

·0.5 to +7.0

·0.5 to +7.0

V

~_""""""-

,_~

Data
Book D,__ Section
6.8, Page 2
• __ .._
_
_
~

RECOMMENDED DC OPERATING
CONDITIONS
Parameter

Input High Voltage

NOTE:

DC ELECTRICAL CHARACTERISTICS(l)

Parameter

Dynamic Operating Current
CS = VIL, Outputs Open, Vee = Max., f = fMAX(2}

UPDATE1 D

7

c

IDT71 B256

Data Book D, Section 6.8, Page 4

AC ELECTRICAL CHARACTERISTICS (Vee = 5.0V ± 10%, All Temperature Ranges)

TIMING WAVEFORM OF READ CYCLE(1,2)
Address

1 4 - - - - tAA --~

Data Out - - - - -

1DT71 B258

Data Book D, Section 6.9, Page 2

RECOMMENDED DC OPERATING
CONDITIONS

ABSOLUTE MAXIMUM RATINGS(1)

DC ELECTRICAL CHARACTERISTICS(1)

Symbol
Icc

Dynamic
CS = VIL,

= Max., f = fMAX(2)

IDT71 B258

Data Book D, Section 6.9, Page 3

UPDATE1 D

8

IDT71 B258

Data Book D, Section 6.9, Page 3 (con't.)

AC ELECTRICAL CHARACTERISTICS (Vee = 5.0V ± 10%, All Temperature Ranges)

IDT71B258.

.

Data Book D, Section 6.9, Pa.ge.4

TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1, 2,3,5,6)
~--------------twc--------------~

Address

cs

UPDATE1 D

9

UPDATE1 0

10

1991 SRAM DATA BOOK

Changes to Full Data Sheets

The following section contains full data sheets that appeared in the 1991 SRAM Data Book. These data sheets
had changes to 50% or more of the overall contents and
are now considered new. Refer to the bar at the top of
each page to see where that page can be found in the
1991 SRAM Data Book.

UPDATE1 D

11

IDT71589

Data Book D, Section 5.17, Page 1

CMOS CacheRAMTM
32K X 9-BIT (288K-BIT)
BURST COUNTER &
SELF-TIMED WRITE

~

Integrated Device Technology, Inc:.

FEATURES:

IDT71589

DESCRIPTION:

High density 32K x 9 architecture
Internal write registers (address, data, and control)
Self-timed write cycle
Internal burst read and write address counter
Clock to data times: 14, 19,24, 34ns
Chip select for depth expansion
Matches all timing and signals of Intel™ 486™
processors up to 50MHz
Packaged in plastic or hermetic 300 mil 32-pin DIP, and
plastic 300 mil 32-pin SOJ
Military product 100% screened to MIL-STD-883, Class B

The IDT71589 is an extremely high-speed 32K x 9-bit static
RAM with full on-chip hardware support of the Intel i486 CPU
interface. This part is designed to facilitate the implementation
of the highest-performance secondary caches for the i486
architecture while using low-speed cache-tag RAMs and
PALs and consuming the minimum possible board space.
The IDT71589 CacheRAM contains a full set of write data
and address registers. Internal logic allows the processor to
generate a self-timed write based upon a decision which can
be left until.the extreme end of the write cycle.
An internal burst address counter accepts the first cycle
address from the processor, then cycles through the adjacent
four locations using the i486's burst refill sequence on appropriate rising edges of the system clock.
Fabricated using IDT's CEMOSTM high-performance technology, this device operates at a very low power consumption
and offers· a maximum clock to data access time as fast as
14ns.
The IDT71589 CacheRAMs are packaged in a 32-pin
plastic or hermetic DIP, or a plasticJ-bend small-outline (SOJ)
package. Military grade devices are available 100% processed in compliance to the test methods of MIL-STD-883,
Class B, Method 5004.

FUNCTIONAL BLOCK DIAGRAM
A14

ADDRESS
REGISTER

•
•
•

LSB
BURST
CONTROL

Ao

1101-1/09

WE
OE
CS

ClK

•

294,912-BIT
MEMORY
ARRAY

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