1991_Intel_16 Bit_Embedded_Controller_Handbook 1991 Intel 16 Bit Embedded Controller Handbook

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Intel Corporation is a leading supplier of microcomputer components,
modules and systems. When Intel invented the microprocessor in 1971, it
created the era of the microcomputer. Today, Intel architectures are considered
world standards. Whether used in embedded applications such as automobiles,
printers and microwave ovens, or as the CPU in personal computers, client
servers or supercomputers, Intel delivers leading-edge technology.

16-BIT
EMBEDDED CONTROLLER
HANDBOOK

1991

About Our Cover.·
Thinkers. inventors, and artists throughout history have breathed
life into theN: ideas by converting them into rough working sketches, models,
and products. This series of covers shows a few of these creations, along
. with the applications and products created by Intel customers.

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear in this document nor does it make a commitment to ufildate the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel products:
287, 376, 386, 387, 486, 4-SITE, Above, ACE51 , ACE96, ACE186, ACE196, ACE960,
ActionMedia, BITBUS, COMMputer, CREDIT, Data Pipeline, DVI, ETOX, FaxBACK,
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Identifier, inteligent Programming, Intellec, Intellink, iOSP, iPAT, iPDS, iPSC, iRMK, iRMX,
iSBC, iSBX, iSDM, iSXM, Library Manager, MAPNET, MCS, Megachassis,
MICROMAINFRAME,
MULTICHANNEL,
MULTIMODULE,
MultiSERVER,
ONCE,
OpenNET, OTP, Pr0750, PROMPT, Promware, QUEST, QueX, Quick-Erase, Quick-Pulse
Programming, READY LAN, RMX/80, RUPI, Seamless, SLD, SugarCube, SX, TooITALK,
UPI, VAPI, Visual Edge, VLSiCEL, and ZapCode, and the combination of ICE, iCS, iRMX,
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Data Sciences Corporation.
CHMOS and HMOS are patented processes of Intel Corp.
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Additional copies of this manual or other Intel literature may be obtained from:
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Literature Sales
P.O., Box 7641
Mt. Prospect, IL 60056-7641
©INTELCORPORATION 1990

"rW_l®
III'V' .

CUSTOMER SUPPORT
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requires an international support organization and a breadth of programs to meet a variety of customer needs.
As you might expect, Intel's customer support is extensive. It can start with assistance during your development
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MCS® .. 968X9X
Architectural Overview
MCS® .. 96 8X9X Hardware
Design Information and
Data Sheets
MCS® .. 96 Instruction Set
80C196KB User's Guide
and Data Sheets
80C196KC User's Guide
and Data Sheets
~MCS® .. 96

Development
Support Tools

Memories Data SJ:1eet

Table of Contents
Alphanumeric Index ........................ ' .. '.............................

MCS®·96 FAMILY
Chapter 1
MCS-96 8X9X Architectural (Jverview . . .. . . . . . .. . . . . . . . . . . . . . . .. . . . .. . . . . . . . .

1-1

Chapter 2
8X9X Hardware Design Information..........................................
2-1
MCS®-96 DATA SHEETS
MCS-96 809XBH, 839XBH, 879XBH Advanced 16-Bit Microcontroller with 8- or '
16-Bit External Bus .................. ; ..................... : . . . . . . . . . . . . . 2-58
MCS-96 809XBH/839XBH/879XBH Express ............................... , . 2-80
MCS-96 809XJF, 839XJF, 879XJF Advanced 16-Bit Microcontroller with 8- or
16-Bit External Bus ............................................. '. . .... . . . . 2-83
MCS-96 809XJF/839XJF/879XJF Express................................... 2-102
EV8097BH Evaluation Board Fact Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-107

Chapter 3

MCS-96 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .

Chapter 4

3-1

80C196KB User's Guide ........................... :.......................
DATA SHEETS
87C196KB/83C196KB/80C196KB 1S-Bit High Performance CHMOS
,
Microcontroller . '............... : '................................... '. . . . .
87C196KB1616-Bit High Performance CHMOSMicrocontroller .................
83C198/80C198, 83C194/80C194 16-Bit CHMOS Microcontroller ..............
87C198/87C194 16-Bit CHMOS Microcontroller ..............................
8XC196K13 Express .............................. '.........................
EV80C196KB Evaluation Board Fact Sheet. . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . ..

4-1
4-98
4-126
4-153
4-173
4-194
4-211

Chapter 5
80C196KC User's Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
DATA SHEETS
8XC196KC 16-Bit High Performance CHMOS Microcontroller ................... 5-104
, 8XC196KC 16-Bit Microcontroller Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-130
EV80C196KC Evaluation Board Fact Sheet................................... 5-132

Chapter 6
MCS®-96 DEVELOPMENT SUPPORT TOOLS
ACE 196TM Software . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8096/196 Software Development Packages......... .........................
VLSiCE-96 In-Circuit Emulator ..............................................
Real-Time Transparent 80C196 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICE-196KB/HX In-Circuit Emulator..........................................

6-1
6-2
6-5
6-10
6-13

Chapter 7
MEMORIES
87C257 256K (32K x 8) CHMOS EPROM.....................................

7-1

Alphanumeric Index
8096/196 Software Development Packages ................................... , . . . ..
80C196KB User's Guide ........................................................ '. .
80C196KC User's Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83C198/80C198, 83C194/80C194 16-Bit CHMOS Microcontroller . . . . . . . . . . . . . . . . . . . ..
. 87C196KB/83C196KB/80C196KB 16-Bit High Performance CHMOS Microcontroller. . . . .
87C196KB16 16-Bit High Performance CHMOS Microcontroller. . . . . . . . . . . . . . . . . . . . . . ..
87C198/87C194 16-Bit CHMOS Microcontroller .................................... ,
87C257 256K (32K x 8) CHMOS EPROM...........................................
8X9X Hardware Design Information ................................................
8XC196KB Express .............................. : .................... : ..........
8XC196KC 16-Bit High Performance CHMOS Microcontroller .......................'...
8XC196KC 16-Bit MicroControlier Express ..........................................
ACE196™ Software .... :........................................................
EV8097BH Evaluation Board Fact Sheet. ....... : ............................. : ......
EV80C196KB Evaluation Board Fact Sheet ..................................... ;...
EV80C196KC Evaluation Board Fact Sheet .........................................
ICE-196KB/HX In-Circuit Emulator ................................................. ·
MCS-96 809XBH/839XBH/879XBH Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCS-96 809XBH, 839XBH, 879XBH Advanced 16-Bit Microcontroller with 8- or 16-Bit
External Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCS-96 809XJF/839XJF/879XJF Express. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . ..
. MCS-96 809XJF, 839XJF, 879XJF Advanced 16-Bit Microcontroller with 8- or 16-Bit
External Bus ..................................................................
MCS-96 8X9X Architectural Overview .....,.........................................
MCS"96 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Transparent 80C196 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .
VLSiCE-96 In-Circuit Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .

6-2
4-1
5-1
4-153
4-98
4-126
4-173
7-1
2-1
4-194
5-104
5-130
'. 6-1
2-107
4-211
5-132
6-13
2-80
2-58
2-102
2-83
1-1
3-1
6-10
6-5

MCS®-968X9X
" Architectural Overview

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October 1990

MCS®-96

8X9X

Architectural Overview

Order Number: 270250·005

1·1

MCS®-96
CONTENTS

8X9X ARCHITECTURAL OVE'RVIEW
CONTENTS

PAGE

7.0 HIGH SPEED OUTPUTS ........ ~ ... 1-34

1.0 CPU OPERATION .................... 1-3

1.1 CPU Buses ........................ 1-3

7.1 HSO CAM ........................ 1-34

1.2 CPU Register File .................. 1~4

7.2 HSO Status ....................... 1-35

1.3 RALU Control ...................... 1-4
1.4 RALU ............................. 1-4

7.3 Clearing the HSO ................. 1-35
7.4 Using Timer 2 with the HSO ....... 1-35

1.5 Internal Timing ..................... 1-5

7.5 Software Timers .................. 1-36

2.0 MEMORY SPACE .................... 1-6

8.0 ANALOG INTERFACE ..............

1-36

2.1 Register File ....................... 1-6
2.2 Special Function Registers ......... 1-7

8.1 Analog Inputs ...................... 1-36
8.2 A/D Commands .................. 1-37

2.3 Power Down ....................... 1-7

8.3 AID Results ......... , ............ 1-37

2.4 Reserved Memory Spaces ......... 1-9

8.4 Pulse Width Modulation Output
(D/A) .............................. 1-38

2.5 Internal ROM and EPROM ......... 1-9
2.6 Internal Executable RAM
(XRAM)-8X9XJF Only ............. 1-10

8.5 PWM Using the HSO ............. 1-39

9.0 SERIAL PORT ...................... 1-39

2.7 Memory Controller ................ 1-10
2.8 System Bus ...................... 1-10

9.1 Serial Port Modes ................. 1-39

3.0 SOFTWARE OVERViEW ............ 1-17

9.2 Controlling the Serial Port ......... 1-40
9.3 Determining Baud Rates .......... 1-41

3.1 Operand Types ................... 1-17

9.4 Multiprocessor Communications .. 1-42

3.2 Operand Addressing .............. 1-18

10.0110 PORTS ........................ 1-42

3.3 Program Status Word ............. 1-20

10.1 Input Ports ...................... 1-42
10.2 Quasi-Bidirectional Ports ........ 1-43

3.4 Instruction Set ..... ',' ............. 1-21
3.5 Software Standards and
Conventions ....................... 1-25

10.3 Output Ports .................... 1-43
10.4 Ports 3 and 4/ ADO-15 .......... 1-43

4.0 INTERRUPT STRUCTURE .......... 1-26

11.0 STATUS AND CONTROL

4.1 Interrupt Control .................. 1-28
4.2 Interrupt Priorities ................. 1-28

REGISTERS .......................... 1-44
11.1 I/O Control Register 0 (lOCO) .... 1-44

/ 4.3 Critical Regions ................... 1-29
4.4

Interrup~

11.2 I/O Control Register 1 (IOC1) .... 1-45

Timing ................... 1-30

11.3 I/O Status Register 0 (IOSO) ..... 1-45

5.0 TIMERS .. ........................... 1-31

11.4 I/O Status Register 1 (IOS1) .... :, 1-45

5.1 Timer 1 .......-.................... 1-31
5.2 Timer 2 ........................... 1-31

12.0 WATCHDOG TIMER . ~ ............. 1-46

5.3 Timer Interrupts .................. 1-31

12.1 SoftWare Protection Hints . ; ...... 1-46

5.4 Timer Related Sections ........... 1-32

12.2 Disabling the Watchdog ......... 1-46

6.0 HIGH SPEED INPUTS .. ............. 1-32

13.0 RESET .......... ," .. ,............... 1-46

6.1 HSI Modes ....................... 1-33

13.1 Reset Signal .................... 1-46

6.2 HSI FIFO ........ ; ............... : 1-33

13.2 Reset Status .................... 1-47

6.3 HSllnterrupts .................... 1-33

13.3 Reset Sync Mode ............... 1-47

6.4 HSI Status ........................ 1-33
1-,2

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

This overview is written about the 8X9XBH, 8X9XJF,
and 8X98 devices. These devic~ are generically referred to as the gX9X. All information in this overview
refers to the 8X9XBH, the 8X9XJF, and the 8X98 unless otherwise noted.

1.0 CPU OPERATION
The, major components of the CPU on the 8X9X are
the Register File and the RALU. Communication with
the outside world is done through either the Special
Function Registers (SFRs) or the Memory Controller.
The RALU (Register/Arithmetic Logic Unit) does not
use an accumulator, it operates directly on the 256-byte
register space made up of the Register File and the
SFRs. Efficient I/O operations are possible by directly
controlling the I/O through the SFRs. The main benefits of this structure are the ability to quickly change
context, the absence of accumulator bottie!leck, and
fast throughput and I/O times.

The 8X9X can be separated into several secti~ns for the
purpose of describing its operation. There is a l6-bit
CPU, a programmable High Speed I/O Unit, an analog
to digital converter, a seriaf port, artd a Pulse Width
Modulated (PWM) output for digital to analog conversion. In addition to ihese functional units, there are
some sections which support overall operation of the
chip such as the clock generator. The CPU and the
programmable I/O. make the 8X9X very different from
any other microcontroller. Let us first examine the
CPU.

1.1 CPU Buses
A "Control Unit" and two buses connect the Register
File ahd RALU. Figure 1 shows the CPU with its

VRE~

POWER
DOWN

ANGND

FREQUENCY
REFERENCE

······t······~···· ~::~~···l
CLOCK
tEN

A- BUS

ON-CHIP
EPROM 879 X BH

.....-r----,r-...

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CONTROL
SIGNALS

ADDR
] DATA
BUS

: PORT 4
HIGH
SPEED
I/O

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PORT 0

PORT 1

PORT 2
ALT FUNCTIONS

HSI

HSO
270250-1

Figure 1. Block Diagram

1-3

intJ

MCS®~96 8X9X ARCHITECTURAL OVERVIEW

major bus connections. The two buses are the "A-Bus"
which is 8,bits wide, and the "D-Bus" which is 16-bits
wide. The D-Bus transfers data only between the
RALUandthe Register File or Special Function Registers (SFRs). The A-Bus is used as the address bus for
the above transfers or' as' a multiplexed address/data
bus connecting to the "Memory Controller". Any accesses of either the internal ROM or external memory
are done through the -Memory Controller. '

the Register File is reserve,d for use as the stack pOinter
so it can not be used for data when stack manipubitions
are taking place. Addresses for accessing the Register
File and· SFRs are temporarily stored in two 8-bit address registers by the CPU hardware.

1.3 RALU Control
Instructions to the RALU are taken from the A-Bus
and stored temporarily in the instruction register. The
Control Unit decodes the instructions and generates the
correct sequence of signals to have the RALU perform
the desired function. Figure I shows, the instruction
register and the control unit.

Within the memory controller is a slave program counter (Slave PC) which keeps track of the PC in the CPU.
By having most program fetches from memory referenced to the slave PC, the processor saves time as addresses seldom have to be sent to the memory controller. If the address jumps sequence then the slave PC is
loaded with a new value and processing continues.
Data fetches from memory are also done through the
memory controller, but the slave PC is bypassed for
this operation.

1.4 RALU
Most calculations performed by the 8X9X take place in
the RALU. The RALU, shown in Figure 2, contains a
l7-bit ALU, the Program Status Word (PSW), the Program Counter (PC), a loop counter, and three temporary registers. All of the registers are 16-bits or
17-bits (16 + sign extension) wide. Some of the registers have the ability to perform simple operations to offload the ALU.

1.2 CPU Register File
The Register File contains 232 bytes of RAM' which
can be accessed as bytes, words, or double-words. Since
each of these locations can be used by the RALU, there
are essentially 232 "accumulator,s". The' first word in

6-BIT
A-BUS

UPPER WORD REGISTER/SHIFTER

LOWER WORD REGISTER/SHIFTER

~_ _ _ _-..,~16'--_ _ _-t-. . TEMPORA~Y REGISTER 14---,,=6--i

LOWER

270250-2

Figure 2. RALU Block Diagram

1-4

intJ

MCS@·96 aX9X ARCHITECTURAL OVERVIEW

A separate incrementor is used for the PC; however,'
jumps must, be handled through the ALU. Two of the
temporary registers have their own:' shift logic. These
registers are used for the operations which require logical shifts, including Normalize, Multiply, and Divide.
The "Lower Word" register is used only when doubleword quantities are being shifted, the "Upper Word"
register is used whenever a shift is performed or as a
temporary register for many instructions. Repetitive
shifts are counted by the 5.bit "Loop Counter".

The crystal or external oscillator frequency is divided
by 3 to genc:rate the three internal timing phases as
shown in Figure 4. Each of the internal phases repeat
every 3 oscillator periods: 3 oscillator periods are referred to as one "state time", the basic time measurement for 8X9X operations. Most internal operations
are synchronized to either Phase A, B or C, each of
which have a 33% duty cycle. Phase A is represented
externally by CLKOUT, a signal available on the
68-pin device. Phases Band C are not available externally. The relationships of XTALl, CLKOUT, and
Phases A, B, and C are shown in Figure 4. It should be
noted that propagation delays have not, been taken into
account in this diagram. Details on these and other timing relationships can be found In the Hardware Design
chapter.
.

A temporary register is used to store the second operand of two operand instructions. This includes the multiplier during multiplications and the divisor during
divisions. To perform subtractions, the output of this
register can be complemented before being placed into
the "B" input of the ALU.
The DELAY shown in Figure 2 is used to convert the
.16-bit bus into an 8-bit bus. This is required as all addresses and instructions are carried on the 8-bit A-Bus.
Several constants, such as 0, I and 2 are stored in the
RALU for use in speeding up certain calculations.
These come in'handy when the RALU needs to make a
2's complement number or perform an increment or
decrement instruction.

INTERNAL
CIRCUITRY

1.5 Internal Timing
The 8X9X requires an input clock frequency of between 6.0 MHz and 12 MHz to function. This frequency can be applied directly to XTALI. Alternatively,
since XTAL 1 and XTAL2 are inputs and outputs of an
inverter, it is also possible to 'use a crystal to genera~e
the clock. A block diagram of the oscillator section is
shown in Figure 3, Details of the circuit and suggestions for its use can be found in Section I of the Hardware Design chapter.

270250-3

Figure 3. Block Diagram of Oscillator
The RESET line can be used to start the 8X9X at an

exact time to provide for synchronization of test equipment and multiple chip systems. Use of this feature is
fully explained under RESET, Section 13 ..

XTAL 1

PHASE A
(CLOCKOUT)

PHASE B

PHASE C

_....'

....--,

''--~'

,'-----'

-,rl...__-,rl,-__

-'~_ _

270250-4

Figure 4. Internal Timings Relative to XTAL 1

1-5

MCS®·96 8X9XARCHITECTURAL OVERVIEW

2.0 MEMORY SPACE

2.1 Register File

The addressable memory space on the'8X9X consists of
64K bytes, most of which is available to the I;lser for
program or data memory, Locations which have special
purposes are OOOOH through OOFFH, OlOOH through
OlFFH (8X9XJF only), and IFFEH through 2080H.
All other locations can be used for either program or
data storage or for memory mapped peripherals. A
memory map is shown in Figure 5.

Locations OOH difough OFFH contain the Register File
and Special Function Registers, (SFRs). No code, can
be executed from this internal RAM section. If an attempt to execute instructions from locations OOOH
through OFFH is made; the instructions will be fetched
from external memory. This section of external memory is reserved fot use by Intel development tools. Execution of a nonmaskable interrupt (NMI) will force a

FFFFH
OFFH

255,

EXTERNAL MEMORY
OR I/O

POWER-DOWN
OFOH
OEFH

RA~

240

1--------------1 239
INTERNAL
REGISTER FILE

EXTERNAL MEMORY OR I/o
(8X9XBH)

(RA~)

IAH 1-_ _ _....._ _....._ _ _ _ _--1

INTERNAL PROGRAM STORAGE
RO~/EPROM OR EXTERNAL
MEIIORY' (8X9XJF)

BOOOH
5FFFH

4000H
3FFFH

19H

S'T ACK POINTER

STACK POINTER

l.8H

15H

10Sl
10SO

PWILCONtROL

10Cl

lOCO

14H
13H

INTERNAL PROGRAM
STORAGE ROM/EPROM
OR
EXTERNAL MEMORY

17H
16H

2080H

21
20

RESERVED

12H

19
18

llH

SP_STAT

SP_CON

10H

10 PORT 2

OFH

10 PORT 1

OEH

10 PORT 0

BAUD_RATE

ODH

TIMER2 (HI)

OCH

TI~ER2

OBH

TIMERl (HI)

(LO)

2072H - 207FH

SIGNATURE WORD

2070H - 2071H

RESERVED

2030H - 20BFH

SECURITY KEY

2020H - 202FH

RESERVED

201CH - 201FH

SELF JU~P OPCODE (27H FEH)

201AH-201BH

'RESERVED

2019H

CHIP CONFIGURATION eYTE

2018H

RESERVED

2012H - 2017H

INTERRUPT VECTORS

OAH

TIMERl (LO)

WATCHDOG

09H

INT_PENDING

08H

INLMASK

07H

SBUF (RX)

SBUF (TX)

06H

HSI_STATUS

HSO,COMMAND

6
5

2000H

05H

HSI31ME (HI)

HSO_ TIME (HI)

04H

HSUIME (LO)

HSO_ TIME (LO)

03H

AD_RESULT (HI)

HSLMODE

02H

AD_RESULT (LO)

AD_COMMAND

01H

RO (HI)

OOH

RO (LO)

(WHEN READ)

RESERVED

PORT 4

lFFFH

PORT 3

lFFEH

EXTERNA~

MEMORY
OR I/o

01FFH

EXTERNAL MEMORY OR I/O (8X9XBH)
INTERNAL EXECUTABLE RAM
(XRAM) (8X9XJF)

L-,

0100H
INTERNAL RAM \

OOFFH

OOOOH

(WHEN WRITTEN)

270250-5

Figure 5. Memory 'Map'

intJ

MCS®-96 8X9X ARCHITECTURAL OVERVIEW

call to external location OOOOH, therefore, the NMI and
TRAP interrupt are also reserved for Intel development
tools.

2.3 Power Down
The upper 16 RAM locations (OFOH through OFFH)
receive their power from the VPD pin. If it is desired to
keep the memory in these locations alive during a power down situation, one need only keep voltage on the
VPD pin. The current required to keep the RAM alive
is approximately 1 milliamp (refer to the data sheet for
the exact specification). Both Vee and VPD must have
power applied for normal operation. If VpD is not applied the power down RAM will not function properly,
even if Vee is applied.
.

The RALU can operate on any of the 256 internal register locations. Locations OOH through 17H are l,Ised to
access the SFRs. Locations 18H and 19H contain the
stack pointer. These are not SFRs, al).d may be used as
standard RAM if stack operations are not being performed. The stack pointer must be initialized by the
user program and can point anywhere in the 64K memory space. The stack builds down. There are no restrictions on the use of the remaining 230 locations except
that code cannot be executed from them.

To place the 8X9X into a power down mode, the
RESET pin is pulled low. Two state times later the
device will be in reset. This is necessary to prevent the
device from writing into RAM as the power goes down.
The power may now be removed from the Vee pin, the
VPD pin must remain within specifications. The 8X9X
can remain in this state for any amount of time and the
16 RAM bytes will retain their values.

2.2 Special Function Registers
All of the 110 on the 8X9X is controlled through the
SFRs. Many of these registers serve two functions; one
if they are read from, the other if they are written to.
Figure 5 shows the locations and names of these registers. A summary of the capabilities of each of these
registers is shown in Figure 6, with complete descriptions reserved for later sections)

To bring the 8X9X out of power down, RESET is held
low while Vee is applied. Two state times after the
oscillator has stabilized, the RESET pin c!m be pulled
high. The 8X9X will begin to execute code at location
02080H 10 state times after RESET is pulled high. Figure 7 shows a timing diagram of the power down sequence. To ensure that the 2 state time minimum reset
time (synchronous with CLKOUT) is met, it is recommended that 10 XT AL I cycles be used. Suggestions for
actual hardware connections are given in the Hardware
Design Chapter. Reset is discussed in Section 13.

There are several restrictions on using special function
registers.
Neither the source or destination addresses of the Multiply and Divide instructions can be a writable special
function register.
These registers may not be used as base or index registers for indirect or indexed instructions.

To determine if a reset is a return from power down or
a complete cold start a "key" can be written into power-down RAM while the device is running. This key
can be checked on reset to determine which type of
reset has occurred. In this way the validity of the power-down RAM can be verified. The length of this key
determines the probability that this procedure will
work, however, there is always a statistical chance that
the RAM will power up with a replica of the key.

.These registers can only be accessed as bytes unless
otherwise specified in Figure 6. Note that some of these
registers can only be aCcessed as words, and not as
bytes.
Within the SFR space are several registers labeled
"RESERVED". These registers are reserved for future
expansion and test purposes. Operations should not be
performed with theSe registers as reads from them and
writes to them may produce unexpected results. For
example, in some versions of the 8X9X writing to location OCH will set both timers to OFFFXH. This may
not be the case in future products, so it should not be
used as a feature.

Under most circumstances, the power-fail indicator
which is used to initiate a power-down condition must
come from the unfiltered, unregulated seetion of the
power supply. The power supply must have sufficient
storage capacity to operate the 8X9X until it has completed its reset operation.

1-7

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Description

Section

Zero Register - Always reads as a zero, useful for a base when
indexing and as a constant for calculations and compares.

AD_RESULT

AID Result Hi/Low - Low and high order Results of the A/D
converter (byte read only)

AD_COMMAND

AID Command Register - Controls the A/D

HSI_MODE

HSI Mode Register - Sets the mode of the High Speed Input unit.

HSLTlME

HSI Time Hi/Lo - Contains the time at which the High Speed
Input unit was 1riggered. (word read only)

HSO_TIME

HSO Time Hi/Lo - Sets the time or count·for the High Speed
Output to execute the command in the Command Register. (word
write only)

HSO_COMMAND

HSO Command Register - Determines what will happen at the
time loaded into the HSO Time registers.

HSI_STATUS

HSI Status Registers - Indicates which HSI pins were detected at
the time in the HSI Time registers and the current state of the pins.

SBUF (TX)

Transmit buffer for the serial port, holds contents to be outputted.

9
9

SBUF (RX)

Receive buffer for the serial port, holds the byte just received by
, the serial port.
Enables qr disables the individual

INT_MASK

Interrupt Mask Register interrupts.

INT_PENDING

Interrupt Pending Register - Indicates tliat an interrupt signal has
occurred on one of the sources and has not been serviced.

WATCHDOG

Watchdog Timer Register - Written to periodically to hold off
automatic reset every 64K state times.

TIMER1

Timer 1 HilLo -

TIMER2

Timer 2 HilLo - Timer 2 high and low bytes. (word read only)

5
5

10PORTO

Port 0 Register -

BAUD_RATE

Timer 1 high and low bytes. (word read only)
Levels on pins of port O.

IOPORT1

Port 1 Register - Used to read or write to Port 1.

IOPORT2

Port 2 Register -

SP_STAT

Serial Port Status -

SP_CON

Serial Port Control -

10SO

I/O Status Register 0 - Contains information on the HSO status

IOS1

I/O Status Register 1 - Contains information on the status of the
timers and of the HSI.

lOCO

I/O Control Register 0 - Controls alternate functions of HSI pins,
Timer 2 reset sources and Timer 2 clock sources.

10Cl

I/O Gontrol Register 1 --- Controls alternate functions of Port 2
pins, timer interrupts and HSI interrupts.

PWM_CONTROL

Pulse Width Modulation Control Register the PWM pulse.

Used to read or write to Port 2.
Indicates the status of the serial port.
Used to set the mode of the serial port.

Figure 6. SFR Summary

1-8

Sets the duration of

9
9

inter

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

YCC----------------------~

POWER DOWN

YPD---------------------+------~~------;_----------------a

5:1:.5V

RESET - - - - - - " \

XTALl

IflJIIIJLJ1JlfulI1IU1
10 XTALl CYCLES

CLOCK NOT NECESSARY

10 XTALl CYCLES
AFTER CLOCK IS STABLE

270250-6

Figure 7. Power Down Timing

2.4 Reserved Memory Spaces

OOOOH0018H1FFEH2000H2012H2018H
2019H
201AH201CH2020H2030H2080H

A listing of locations with special significance is shown
in Figure 8. The locations marked "Reserved" are reserved by Intel for use in testing or future products. All
reserved locations except 2019H must be filled with
Hex value OFFH to insure compatibility with future
devices. Location 2019H must be filled with 20H.
Locations lFFEH and IFFFH are reserved for Ports 3
and 4 respectively. This is to allow easy reconstruction
of these ports if external memory is used in the system.
An example of reconstructing the I/O ports is given in
section 7 of the Hardware Design chapter. If ports 3
and 4 are not going to be reconstructed, these locations
can be treated as any other external memory location.

0017H Register Mapped I/O (SFRs)
0019H Stack Pointer
1FFFH Ports 3 and 4
2011H Interrupt Vectors
2017H Reserved
Chip Configuration Byte
Reserved
201BH "Jump to Self" Opcode (27H FEH)
201FH Reserved
202FH Security Key
207FH Reserved
Reset Location

Figure 8. Registers with Special Significance

The 9 interrupt vectors are stored in locations 2000H
through 2011H. The 9th vector is used by Intel development systems, as explained in Section 4.

2.5 Internal ROM and EPROM
When a ROM device is ordered, or an EPROM device
is programmed, the internal memory locations 2080H
through 3FFFH on the 8X9XBH and 8X98 and locations 2080H through 5FFFH on the 8X9XJF are user
specified, as are the interrupt vectors, Chip Configuration Register and Security Key in locations 2000H
through 202FH.

Locations 20l2H through 201 7» are reserved for future use. Location 2018H is the Chip Configuration
byte which will be discussed in the next section. The
Jump~To-Seif opcodes at locations 201AH and 20lBH
are provided for EPROM programming as detailed in
the Hardware Design chapter. Locations 2020H
through 202FH are the security key used with the
ROM Lock feature which will be discussed in the next
section. All unspecified addresses in locations 2000H
through 207FH, including those marked Reserved,
should be considered reserved for use by Intel.

Instruction and data fetches from the internal ROM or
EPROM occur only if the device has a ROM or
EPROM, EA is tied high, and the address is between
2000H and 3FFFH on the 8X9XBH and 8X98 and
between 2000H and 5FFFH on the 8X9XJF. At all
other times data is accessed from either the internal
RAM space or external· memory and instructions are
fetched from external memory. The EA pin is latched
on RESET rising. Information on programming
EPROMs can be found in Section 10 of the Hardware
Design chapter.

Resetting the 8X9X causes instructions to be fetched
starting from location 2080H. This location was chosen
to allow a system to have up to 8K of RAM continuous
with the register file. Further information on reset can
be found in Section 13.

Do not execute code out of the last three locations of
internal ROM/EPROM.

1-9

MCS®·968X9X ARCHITECTURAL OVERVIEW
In addition to holding ~ slave PC, the memory controller contains a 4 byte queue to help speed execution.
This queue is transparent to the RALU and to the user
unless wait states are forced during external bus cycles.'
The instruction execution times shown in Section 14.8
show the normal execution times' with no wait states
added and the t"6-bit bus selected. Reldading the slave
PC and fetching the first byte of the new instruction
stream takes 4 state times. This is reflected in the jump
taken/not-taken times shown in the table.

2.6 Internal Executable RAM
(XRAM)-&X9XJF only
Locations OIOOH through OlFFH (8X9XJF only) contain the internal executable RAM (XRAM) space. Instruction fetches will be performed in this region if the
program counter points to the addresses OlOOH
through OIFFH. Data accesses can also be performed
from this region.
The XRAM is accessed and executed from as if it ~ere
external RAM that is contained on chip. No external
bus signals will be generated when accessing the
XRAM.

2.& System Bus
There are several operating modes on the 8X9X. The
standard bus mode uses a 16-bit multiplexed address/
data bus. Other bus modes include an 8-bit mode and a
mode in which the bus size can dynamically be
switched between 8-bits and l6-bits. In addition, there
, are several options available on the type of control signals used by the bus.

The XRAM is not part of the Register File. 8-bit direct
addressing can not be used on this address space.

2.7 Memory Controller
The RALU talks to the memory (except for the locations in the register file and SFR space) through the
memory controller which is connected to the RALU by
the A-Bus and several control lines. Since the A-Bus is
eight bits wide, the memory controller uses a Slave Program Counter to avoid having to always get the instruction location from the RALU. This slave PC is incremented after each fetch. When a jump or call occurs,
the slave PC must be loaded from the A-Bus before
instruction fetches can continue.

In the standard mode, external memory is addressed
through lines ADO through AD15 which form a 16-bit
multiplexed (address/data) data bus. These lines share
pins with I/O Ports 3 and 4. The falling edge of the
Address Latch Enable (ALE) line is used to provide a
clock to a transparent latch (74LS373) in order to de-

PHASE A
(CLKOUT)
PHASE B

PHASE C

REAllY

\\\\~\\\\\\\

ALE

-f''--____

\\-._ _---JI

---.<;BIT"'-;;;BU"'S)

WRITE STROBE MODE SELECT
(WR AND BHE/WRL AND WRJi)
ADDRESS VALID STROBE SELECT
(ALE/ ADV)
(IRCO) } INTERNAL READY
(IRC1) CONTROL MODE
(LOCO) } PROGRAM LOCK
(LOCI) MOD~
270250-8

Figure 10. Chip Configuration Register

During 16-bit bus cycles, Ports 3 and 4 contain the
address multiplexed with data using ALE to latch the
address. In 8-bit bus cycles, Port 3 is multiplexed address/data while Port 4 is address bits 8 through IS.
The address bits on Port 4 are valid throughout an 8-bit
bus cycle. Figure II shows the two options.
The bus width can be changed each bus cycle on the
8X9XBH and the 8X9XJF and is controlled using bit I
of the CCR with the BUSWIDTH pin. If either CCR.I
or BUSWIDTH is a 0, external accesses will be over a
16-bit address/8-bit data bus. If both CCR.I and BUSWIDTH are Is, external accesses will be over a 16:bit
address/16-bit data bus. Internal accesses are always
16-bits wide. The BUSWIDTH pin is not available on
the 8X98. CCR.I must be a on the 8X98.

The bus width can be changed every external bus cycle
if a I was loaded into CCR bit I at reset. If this is the
case, changing the value of the BUSWIDTH pin at runtime will dynamically select the bus width. For example, the user could feed the INST line into the BUSWIDTH pin, thus causing instruction accesses to be
word wide from EPROMs while data accesses are byte
wide to and from RAMs. A second example would be
to place an inverted version of Address bit 15 on the
BUSWIDTH pin. This would make half of external
memory w.ord wide, while half is byte wide.
Since BUSWIDTH is sampled after address decoding
has had time to occur, even more complex memory
maps could be constructed. See the timing specifications ·for an exact description of BUSWIDTH timings.
The bus width will be determined by bit 1 of the CCR
alone on 48-pin devices since they do not have a BUSWIDTH pin.

The CCR is ,loaded on reset with the Chip Configuration Byte, located at address 20l8H. The CCR register
is. a non-memory mapped location that can only be
written to during the reset sequence; once it is loaded it
cannot be changed until the next reset occurs. The
8X9X will correctly read this location in every bus
mode.

When using an 8-bit bus, some performance degradation is to be expected. On the 8X9X , instruction execution times with an 8-bit bus will slow down if any of
three conditions occur. First, word writes to external
memory will cause the executing instruction to take
two extra state times to complete. Second, word reads
from external memory will cause a one state time extension of instruction execution time. Finally, if the prefetch queue is empty when an instruction fetch is requested, instruction execution is lengthened by one
state time for each byte that must be externally ac"'
quired (worst case is the number of bytes in the instruction minus one.)

If the EA pin is set to a logical 0, the access to 2018H
comes from external memory. If EA is a logical I, the

access comes from internal ROM/EPROM. If EA is
+ 12.75V, the CCR is loaded with a byte from a separate non-memory-mapped location called PCCB (Programming CCB). The Programming mode is described
in Section 10 of the Hardware Design chapter.
BUS WIDTH

The 8X9XBH and 8X9XJF external bus width can be
run-time configured to operate as a standard 16-bit
multiplexed address/data bus, or as an 8051 style 16-bit

1-13

MCS®-96 8X9X ARCHITECTURAL OVERVIEW

BUS CONTROL

8X9X

8-BIT
LATCHED

PORT 4

PORT 4
PORT 3

PORT 3

270250-10

270250-9

16-Bit Bus

a·Bit Bus
Figure 11. Bus Width Options

BUS CONTROL

Using the CCR, the 8X9X can be made to provicJe bus
control signals of several types. Three.controllines have
dual functioJls designed to reduce external hardware.
Bits 2 and 3 of the CCR specify the functions per·
formed by these control lines. Figures 12~ 15 show the
sigllals which can be modified by changing bits in the
CCR, all other lines will operate as shown in Figure ~.

ALE

Standard Bus Control
If CCR bits 2 and 3 are Is, then the standard 8X9X
control ~Is WR, BHE and ALE are provided (Figure 12). WR will come out for every write. BHE will be
valid throughout the bus cycle and can be combined
with WR and address line 0 to form WRL and WRH.
ALE will rise as the address starts to come out, and will
fall to provide the signal to externally latch the address.

ALE

BHE

ADO-15

ADO -7

VALID

ADDR

DATA OUT

ADS-15

~ADDR LOwl
~

DATA OUT

ADDRESS HIGH

'270'250-11

~
~
270250-12

a-Bit Bus Cycle

16·Bit Bus Cycle
Figure 12. Standard Bus Control

1-14

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Write Strobe Mode

Address Valid Strobe Mode

The Write Strobe Mode eliminates the necessity to externally decode for odd or even byte writes. If CCR bit
2 is a 0, and the bus is in a 16-bit cycle, WRL and
WRH signals are provided in place of WR and BHE
(Figure 13). WRL will go low for all byte writes to an
even address and all word writes. WRH will go low for
all byte writes to an odd address and all word writes.

If CCR bit 3 is a 0, then an Address Valid strobe is
provided in the place of ALE (Figure 14). When the
address valid mode is selected, ADV will go low after
an external address is set up. It will stay low until the
end of the bus cycle, where it will go inactive high. This
can be used by ROM devices to provide a chip select for a
single external RAM device in a minimum chip count
system.

Write Strobe Mode is particularly well suited to memory systems latching data on the falling edge of WRITE.

Address Valid with Write Strobe

WRL is provided for all 8-bit bus write cycles.

ALE

-.n

WRL

VALID

WRH

VALID

ADO -15

--I

If both CCR bits 2 and 3 are Os, both the Address Valid
strobe and the Write Strobes will be provided for bus
control. Figure 15 shows these signals.

DATA OUT

ADDR

ALE

WRL

ADO -7 -1ADDR LOW

I-

AD8 -15

DATA OUT

ADDRESS HIGH

-1

II-

270250-14

270250-13

a·Blt Bus Cycle

16·Blt Bus Cycle
\

Figure 13. Write Strobe Mode

ADV

SHE

ADO -15

ADV

[
~

--1

VALID

ADDRI

ADO:" 7 .

DATA OUT

I-

AD8-15

--1

ADDR LOwl

DATA OUT

ADDRESS OUT HIGH

I.1270250-16

270250-15

a·Blt Bus Cycle

16·Blt Bus Cycle
Figure 14. Address Valid Strobe Mode

1-15

inter

MCS®·96 8X9X ARCHITECT,URAL OVERVIEW

WRL

WRH

ADO -15

--i

ADDR

VALID

WRL

VALID

ADO -7

J---

DATA OUT

ADS -15

-1

AD DR LOW

DATA OUT

-1. . __

J--J---

A_D_D_RE_S_S_H_IG_H_ _.....

270250-17

270250-18

16·Bit Bus Cycle

8·Bit Bus Cycle

Figure 15. Write Strobe with Address Valid Strobe
READY CONTROL

To simplify ready control, four modes of internal ready
control logic have been provided. The modes are chosen by properly configuring bits 4 and 5 of the CCR.
The internal ready control logic can be used to limit the
number of wait states that slow devices can insert into
the bus cycle. When the READY pin is pulled low,
wait states will be inserted into the bus cycle until the
READY pin goes high, or the number of wait states
equals the number specified by CCR bits 4 and 5,
whichever comes first. Table 1 shows the number of
wait states that can be selected. Internal Ready control
can be disabled by loading 11 into bits 4 and 5 of the
CCR.

executing from external memory. The modes are shown
in Table 2. Internal ROM/EPROM addresses 2020H
through 3FFFH on the 8X9XBH and the 8X98 and
addresses 2020H through 5FFFH on the 8X9XJF are
protected from reads. 2000H through 3FFFH on the
8X9XBH and the 8X98 and 2000H through 5FFFH on
the 8X9XJF are protected from writes, as set by the
CCR.
Table 2. Program Lock Modes
LOC1

LOCO

Protection

0
0

Read and Write Protected
Read Protected
Write Protected
No Protection

Table 1. Internal Ready Control
IRC1

IRCO

Description

o
o

Limit to 1 Wait State
Limit to 2 Wait States
Limit to 3 Wait States
Disable Internal Ready Control

1
1

This feature provides for simple ready control. For example, every slow memory chip select line could be
ORed together and be connected to the READY pin
with CCR bits 4 and 5 programmed to give the desired
'
number of wait states to the slow devices.

Only code executing from internal memory can read
protected internal memory, while a write protected
memory can not be written to, even from internal execution. As a result of 8X9X prefetching of instructions,
however, accesses to protected memory are not allowed
for instructions located above 3FFAH on the 8X9XBH
and the 8X98 and above 5FFAH on the 8X9X)F, This
is becaus~the lock protection mechanism is gated off of
the Memory Controller's slave program counter and
not the CPU program counter. If the bus controller
receives a request to perform a read of protected memory, the read sequence occurs with, indeterminate data
being returned to the CPU. Note that the interrupt vectors and the CCR are not protected .

. ROM IE PROM LOCK
Four modes of program memory lock are available on
the 8X9X devices. CCR bits 6 and 7 (LOCO, LOCI)
select whether· internal· program memory can' be read '
(or written in EPROM devices) by a program

, 1-16

To provide verification and testing when the program
lock feature is enabled, the 8X9X verifies the security
key before, programming or test modes are allowed to
read from protected memory. Before protect,ed memory
can be read, the chip reads external memory locations
4020H through 402FH and compares the values

MCS®~96 8X9X ARCHITECTURAL OVERVIEW

found to tlje internal security key located from 2020H
through 202FH. Only when the values exactly match
will accesses to protected memory be allowed. The details of ROM/EPROM accessing are discussed in Section 10 of the Hardware Design chapter.

result must be interpreted in modulo 256 arithmetic.
Logical operations on BYTES are applied bitwise. Bits
within BYTES are labeled from 0 to 7, with 0 being the
least significant bit. There are no alignment restrictions
for BYTES, so they may be placed anywhere in the
MCS-96 address space.

3.Q SOFTWARE OVERVIEW
This section provides information on writing programs
to execute in the 8X9X. Additional information can be
found in the following documents:
MCS®-96 M;ACRO ASSEMBLER USER'S GUIDE
Order Number 186 ASM 96 (Intel Systems)
Order Number 086 ASM 96NL (DOS Systems)
C-96 USER'S GUIDE
'Order Number 086 C96NL (DOS Systems)
PL/M·96 USER'S GUIDE
Order Number 186 PLM 96 (Intel Systems)
Order Number 086 PLM 96NL (DOS Systems)

WORDS
WORDS are unsigned 16-bit variables which can take
on the values between 0 and 65535. Arithmetic and
relational operators can be applied to WORD operands
but the result must be interpreted modulo 65536. Logical operations on WORDS are applied bitwise. Bits
within words are labeled from 0 to 15 with 0 being the
least significant bit. WORDS must be aligned at even
byte boundaries in the MCS~96 address space. The least
significant byte of the WORD is in the even byte address and the most significant byte is in the next higher
(odd) address. The address of a word is the address of
its least significant byte. Word operations to odd addresses are' not guaranteed to operate in a consistent
manner.

Throughout this section, short sections of code are used
to illustrate the operation of the device. For these sections it has been assumed that a set of temporary registers have been predeclared. The names of these registers
have been chosen as follows:
AX, BX, CX, and OX are 16-bit registers.
AL is the low byte of AX, AH is the high byte.
BL is the low byte of BX
CL is the low byte of CX
DL is the low byte of OX

SHORT-INTEGERS
SHORT-INTEGERS are 8-bit signed variables which
can take on the values betweep -128 and + 127.
Arithmetic operations which generate results outside of
the range ofa SHORT-INTEGER will set the overflow
indicators in the program status word. The actual numeric result returned will be the same as the equivalent
operation on BYTE variables. There are no alignment
restrictions on SHORT-INTEGERS so they may be
placed anywhere in the MCS_96 address space.

These are the same as the names for the general data
registers used in the 8086 (80186). It is important to
note, however, that in the 8X9X, these are not dedicated registers but merely the symbolic names assigned by
the programmer to an eight byte region within the onboard register file.

INTEGERS
INTEGERS are 16-bit signed variables which can take
on the values between -32,768 and 32,767. Arithmetic
operations which generate results outside of the range
of an INTEGER will set the overflow indicators in the
program status word. The actual numeric result returned will be the same as the equivalent operation on
WORD variables. INTEGERS conform to the same
alignment and addressing rules as do WORDS.

3.1 Operand Types
The MCS®-96 architecture provides support 'for a variety of data types which are likely to be useful in a control application. In the discussion of these operand
types that follows, the names adopted by the PLM-96
programming language will be used where appropriate.
To avoid confusion, the name of an operand type will
be capitalized. A "BYTE" is an unsigned eight bit variable; a "byte" is an eight bit unit of data of any type.

BITS
BITS are single-bit operands which can take on the
Boolean values of true and false. In addition to the normal support for bits as components of BYTE and
WORD operands, the 8X9X provides for the direct
testing of any bit in the internal register file. The MCS96 architecture requires that bits be addressed as components of BYTES or WORDS, it does not support the
direct addressing of bits that can occur in the MCS-51
architecture.

BYTES
BYTES are unsigned 8-bit variables which can take on
the values between 0 and 255. Arithmetic and relational
operators can be applied to BYTE operands but the

1-17

inter

MCS %LSB
Figure 17. Rounding Alternatives

V. The V (overflow) flag is set to indicate that the operation generated a result which is outside the range that
can be expressed in the destination data type. For the
SHL, SHLB and SHLL instructions, the V flag will be
set if the most significant bit of the operand changes at
any time during the shift.
VT. The VT (oVerflow Trap) flag is set whenever the V
flag is set but can only be cleared by an instruction
which explicitly operates on it such as the CLRVT or
JVT instructions. The operation of the VT flag allows
for the testing for a possible overflow condition at the
end of a sequence of related arithmetic operations. This
is normally more efficient than testing the V flag after
each instruction.

AX,CL,DL
AX.#4

MULUB
SHR

Imprecise rounding can be a major source of error in a
numerical calculation; use of the ST flag improves the
options available to the progranimer.

3.4 Instruction Set

1-21

The MCS-96 instruction set contains a full set of arithmetic and logical operations for the 8-bit data types
BYTE and SHORT INTEGER and for the 16-bit data
types WORD and INTEGER. The DOUBLE-WORD
and LONG data types (32 bits) are supported for the
products of 16 by 16 multiplies and the dividends of 32

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

by 16 divides and for shift operations. The remaining
operations on '32-bit variables can be implemented by
combinations of 16-bit operations. As an example the
sequence:

ADD
ADDe

AX,ex
BX,DX

performs a 32-bit addition, and the sequence

SUB
SUBe

AX,ex
BX,DX

performs a 32-bit subtraction. Operations on REAL
(i.e. floating point) variables are not supported directly
by the hardware but are supported by the floating point
library for the 8X9X (FPAL-96) which implements a
single precision subset of the proposed IEEE standard
for floating point operations. The performance of this
software is significantly improved by the 8X9X
NORMl- instruction which normalizes a 32-bit variable and by the existence of the ST flag in the PSW.
In addition to the operations on the various data ,types,
the 8X9X supports conversions between these types.

LDBZE (load byte zero extended) converts a BYTE to
a WORD and LDBSE (load byte sign extended) converts a SHORT-INTEGER into an INTEGER.
WORDS can be converted to DOUBLE-WORDS by
simply clearing the upper WORD of the DOUBLEWORD (CLR) and INTEGERS can be converted to
LONGS with the EXT (sign extend) instruction.
The MC~-96 instructions for addition, subtraction, and
compalison do not distinguish between unsigned words
and signed integers. Conditional jumps are provided to
allow the user to treat the results of these operations as
either signed or unsigned quantities. As an example, the
CMPB (compare'byte) instruction is used to compare
both signed and unsigned eight bit quantities. A JH
(jump if higher) could be used following the compare if
unsigned operands were involved or a JGT (jump if
greater-than) if signed operands were involved.
Table 3 summarizes the operation of each of the instructions. Complete descriptions of each instruction
and its timings can be found in the Instruction Set
chapter. A summary of instruction opcodes and timing
is included in the quick reference section at the end of
this chapter.

1-22

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Table 3. Instruction Summary
Mnemonic

Oper·
ands

Flags

Operation (Note 1)

Notes.

D - O+A
B+A
D D-'D+A+C
D - D-A

N
I"

C
I"
I"

I"
I"

ADDC/ADDCB

SUB/SUBB

B-A
D D_D-A+C-i

SUBC/SUBCB

CMP/CMPB

D-A

i
i
i
i
i
i
i
-

i
i
i
i

ADD/ADDB

ADD/AD DB

MUL/MULU

D,D

D' A

MULIMULU

Q, D + 2 -

B*A

MULB/MULUB

D,D + 1 -

D' A

remainder

MULB/MULUB

DIVU

OIVUB

D,D + 1 B' A
o - (0, 0 + 2)/ A, D + 2
0 _ (0,0 + i)/A, 0 + 1

DIV

0 - BandA

OR/ORB

0 - DorA

XOR/XORB

LDBSE

LDBZE

D-A;D+1 SIGN(A)
D-A;D+i - 0

PUSH

SP -

SP + 2

SP - 2; (SP) -

POP

A -

PUSHF

SP - SP - 2; (SP) PSW - OOOOH

POPF

SJMP

LJMP

(SP); SP -

PSW;

BR (indirect)

PC -

S~ -

3,4

1- 0

PSW (SP); SP SP + 2;
PC PC + it-bit olfset
PC +- PC + i6-biroflset

SCALL

0 - DandA

A-O

ANO/ANOB

remainder

LD/LDB

0 - (0,0 + i)/A,D + 1

ST/STB

0 - (0:0 + 2)/A,D + 2

2
2

0 (excL or) A
O-A

OIVB
AND/ANOB

PC -

(A)
SP - 2; (SP) PC;
PC + i1-bit offset
SP - 2; (SP) PC;
PC + i6-bit offset

LCALL

SP PC -

RET
J (conditional)

0
;

PC (SP);SP SP + 2
PC - , PC + a-bit offset (il taken)

JumpilC

JNC

JumpilC

=1
=0

JumpilZ

I-I"

5
5

5
5
5

NOTES:

1. II the mnemonic ends in "B", a byte operation is performed, otherwise a word operation is done. Operands 0, S, and A
must conform to the alignment rules for the required operand type. 0 and B are locations in the register file; A can be
located anywhere in memory.
2. D, D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D, D. + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to a word.
5. Offset is a 2's complement number.

1·23

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Table 3. Instruction Summary (Continued)
Operands

M(lemonlc

Flags

Operation (Note 1)

= 0
= 0
Jump if N = 1
Jump if N = 0 and Z = 0
Jump if N = 1 or Z = 1
JumpifC = 1 andZ= 0
Jump if C = 0 or Z = 1

JNE

Jump if Z

JGE

JumpifN

JLT

JGT

JLE

JNH

JNV

JVT

JNVT

JST

=1
=0
Jump if VT = 1; Clear VT
Jump if VT = 0; Clear VT
Jump if ST = 1
Jump ifST = 0
Jump if Specified Bit = 1
Jump if Specified Bit = 0
Jump if V

Jump if V

JBC

DJNZ

D ~ D - 1; if D "" 0 then
PC ~ PC + 8-bit offset

DEC/DECB

0-1

O-D

NEG/NEGB

INC/INCB

D ~ 0+ 1

EXT

D ~ 0; D + 2 -

EXTB

O-D;O+l

Sign(D)

NOT/NOTB

D ~ Logical Not (D)

CLR/CLRB

D~O

SHLlSHLB/SHLL

SHRISHRB/SHRL

SHRAISHRAB/SHRAL

msb -+ msb-----Isb -+'C

SETC

C~l

msb-----Isb

msb-----Isb ~ C

,;,

'" '"
'" '" '"
'" '"0 '"0
'" 0 0
'"
'"1 '"0 00 00
'" ?? '" '"0
'"
'" 0
-'" -'" '"1 -

'"
'"
'"
'"
'"

Sign (D)

JBS

JNST

0
0

-t
t
t

t
-

5
5
5
5
5
5
5
5
5
5
5
5
5
5,6
5,6
5

Notes

'"
'"

7
7
7

Enable All Interrupts (I ~ 1)

PC ~ PC+ 1

SKIP

PC~PC+2

NORML

Left shift till msb

SP ~ ,SP - 2; (SP)
PC ~ (2010H)

TRAP

C~O

CLRVT

RST

PC ~ 2080H

Disable All Interrupts (I

EI
Nap

CLRC

0
~

1; D ~ shift count
~

NOTES:
1. If the mne,monicends in "B", a byte operation is performed, otherwise a word operation is done. Operands D, B and A
must conform to the alignment rules for the required operand type. D and B are locations in the register file; A ,can be
"
located anywhere in memory.
5. Offset is a2's complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates,double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re~initialize ali the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.

1-24

inter

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

3.5 Software Standards and
Conventions
For a software project of any size it is a good idea to
modularize the program and to establish standards .
which control the communication between these modules. The nature of these standards will vary with the
needs of the final application. A common component of
all of these standards, however, must be the mechanism
for passing parameters to procedures and returning results from procedures. In tlie absence of some overriding consideration which prevents their use, it is suggested that the user conform to the conventions adopted by
the PLM-96 programming language for procedure linkage. It is a very usable standard for both the assembly
language and PLM-96 environment and it offers compatibility between these environments. Another advantage is that it allows the user access to the same floating
pointarithmetics library that PLM-96 uses to operate
on REAL variables.

byte undefined. Thirty-two bit parameters (LONGINTEGERS, DOUBLE-WORDS, and REALS) are
pushed into the stack as two 16-bit values; the most
significant half of the parameter is pushed into the
stack first.
As an example, consider the following PLM-96 procedure:
example_procedure: PROCEDURE
(paraml,param2,param3);
DECLARE paraml BYTE,
param2 DWORD,
param3 WORD;
When this procedure is entered at run time the stack
will contain the parameters in the following order:
?????? : param1
high word of param2
,-

low word of param2

param3

The MCS-96 architecture provides a 256 byte register
file. Some of these registers are used to control registermapped I/O devices and for other special functions
such as the ZERO register and the stack pointer. The
remaining bytes in the register file, some 230 of them,
are available for allocation by the programmer. If these
registers are to be used effectively, some overall strategy
for their allocation must be adopted. PLM-96 adopts
the simple and effective strategy of allocating the eight
bytes between addresses lCH and 23H as temporary ,
storage. The starting address of; this region is called
PLMREG. The remaining area in the register file is
treated as a segment of memory which is allocated as
required.

return address

SUBROUTINE LINKAGE

Stack_pointer

Figure 18. Stack Image

ADDRESSING 32-B11 OPERANDS

These operands are formed from two adjacent 16-bit
words in memory. The least significant wdrd of the
double word is always in lower address, even when the
data is in the stack (which means that the most sig- '
nificant word must be pushed into the stack first). A
double word is addressed by the address of its least
significant byte. Note that the hardware supports some
operations on double words (e.g. normalize and divide).
For these operations the double word must be in the
internal register file and must have an address which is
evenly divisible by four.
'

PLM-96 allows the definition of INTERRUPT procedures which are executed when a predefineQ interrupt
{lCcurs. These procedures do not conform to the rules of
a normal procedure. Parameters cannot be pas,sed t6
these procedures and they cannot return results. Since
they can execute essentially at any time (hence the term
interrupt), these procedures must save the PSW and ,
PLMREG when they are entered and restore these values before they exit.

1-25

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

4.0 INTERRUPT STRUCTURE'
There are 21 sources of interrupts on the 8X9X. These
sources are gathered into 8 interrupt types as indicated
in Figure 19. The 110 control registers which coritrol
some of the sources are indicated in the figure. Each of
the eight types of interrupts has its own interrupt vectbr
as listed in Figure 20. In addition to the 8 standard
interrupts, there is a TRAP instruction which acts as a
software generated interrupt. This instruction is not
currently supported by the MCS-96 Assembler and is
reserved for use in Intel development systems.
The programmer must initialize the interrupt vector table with the starting address of the appropriate interrupt service routine. It is suggested that any unused
interrupts be vectored to an error handling routine. The
error routine should contain recovery code that will not
further corrupt an already erroneous situation. In a debug environment; it may be desirable to have the routine lock into a jump to self loop which would be easily
traceable with emulation tools. More sophisticated routines may be appropriate for production code recoveries.

. PSW which contain.s a global disablebi.t. A block diagram of the system is shown in Figure 21.· The transition detector looks for OJo I transitions' on any of the
sources. External sources have a maximum transition
. speed of om;" edge every state time. If this is exceeded
the. interrupt may not be detected.
Vector Location
Vector

(Hjgh
(Low
Byte) . Byte)

Priority

Software Trap
Extint
Serial Port
Software
Timers
HSI.O
High Speed
Outputs
HSI Data
Available
AID Conversion
Complete
Timer Overflow

2011H ·2010H
200FH 200EH
200DH 200CH
200SH 200AH

Not Applicable
7 (Highest)
6
5

Three registers control the operation of the interrupt
system: Interrupt Pending,. Interrupt Mask, and the

2009H
2007H

2008H
2006H

4
3

2005H

2004H

2003H

2002H

2001H

2000H

o(Lowest)

Figure 20. Interrupt Vecto.r Locations

SOURCE

r---

IOC1.l
..._ _ _ _ _ _ _ EXTINT
EXTINT ~

---<>

ACH.7
n FLAG
RI FLAG

,...--y---------.l r---

SERIAL PORT

HSO_COMMAND.4

O~~

SOFTWARE TIMER

SOFTWARE TIMER
SOFTWARE TIMER 1
SOFTWARE TIMER Z
SOFTWARE TIMER 3
. RESEt TIMER Z'

START AID CONVERSION'
HSI.O,----------HSI.O
,.:--- HSa..cOMMAND.4

ANY tISO OPERATION - - 0

FIFOISFULL~

,
HOLDING REGISTER LOADED _

HIGH SPEED OUTPUTS

".
HSI DATA AVAILABLE

AID CONVERSION COMPLETE - - - - - - - - - - AID CONVERSION COMPLETE

.
nMERl OVERFLOW _
nMER2 OVERFLOW ~

~---IOC1.2

_----r--

TIMER OVERFLOW

•
--IOC1.3

270250-20

NOTE:
'Only when initiated by the HSO unit.

Figure 19, All Possible Interrupt Sources

1-26.

intJ

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

SOFTWARE
EXTINT

TIMERS,

SERIAL PORT

HSI.O

HSO

HSI

ADCONV.

TIMER
OVERFLOW

TRANSITION
DETECTOR

INTERRUPT MASt< REG

PRIORITY ENCODER

I bit
(PSW.9)
GLOBAL DISABLE

INTERRUPT
GENERATOR

D.BUS

_NMI

CONTROL
UNIT

270250-21

Figure 21. Block Diagram of Interrupt System

1-27

intJ

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

4.1 Interrupt Control
Interrupt Pending Register

When the hardware detects one of the eight interrupts
it sets the corresponding bit in the pending interrupt
register (INT_PENDING-09H). When the interrupt
vector is taken, the pending bit is cleared. This register,
the format of which is shown in Figure 22, can be read
or modified as a byte register. It can be read to determine which of the interrupts are pending at any given
time or modified to either clear pending interrupts or
generate interrupts under software control. Any soft~
ware which modifies the INT_PENDING register
should ensure that the entire operation is .indivisible.
The easiest way to do this is to use the logical.instructions in the two or three operand format, for example:

ANDB
ORB

INT_PENDING,#llllllOlB
; Clears the AID Interrupt
INT_PENDING,#OOOOOOlOB
.
; Sets the AID Interrupt

Caution must be used when writing to the pending register to clear interrupts. If the interrupt has already
been acknowledged when the bit is cleared, a 4 state
time "partial" interrupt cycle will occur. This is because the 8X9X will have to fetch the next instruction
of the normal instruction flow, instead of proceeding
with the interrupt processing as it was going to. The
effect on the program will be essen,tially that of an extra
NOP. This can be prevented by clearing the bits using a
2 operand immediate logical, as the 8X9X holds off
acknowledging interrupts during these "read!modify!
write" instructions.

(LOCATION 09H)

16 151413121 1 101

III

I I .~ ~:i:~~£~"

L -_ _ _ _ _' - -_ _
L -_ _ _ _ _ _ _ _ _

HSO EVENT
HSI BIT 0
SOFTWARE TIMERS
SERIAL I/O
EXTERNAL INTERRUPT

The INT_MASK register can be read or written as
byte register. A one in any bit position will enable the
corresponding interrupt source and a zero will disable
the source. The hardware will save any interrupts that"
occur by setting bits in the pending register, even if the
interrupt mask bit is cleared. The INT_MASK register also can 1)e accessed as the lower eight bits of the
psw so the PUSHF and POPF instructions save and
restore the INT_MASK register as well as the global
interrupt lockout and the arithmetic flags.
GLOBAL DiSABLE

The processing of all interrupts can be disabled by
clearing the I bit in the PSW. Setting the I bit will
enable interrupts that have mask register bits which are
set. The I bit is controlled by the EI (Enable Interrupts)
and 01 (Disable Interrupts) instructions. Note that the
I bit only controls the actual servicing of interrupts.
Interrupts that occur during periods of lockout will be
held in the pending register and serviced on a prioritized basis when the lockout period ends.

4.2 Interrupt Priorities
The priority encoder looks at all of the interrupts which
are both pending and enabled, and selects the one with
the highest priority. The priorities are shown in Figure
20 (7 is highest, 0 is lowest). The interrupt generator
then forces a call to the location in the indicated vector
location. This location would be the starting location of
the Interrupt Service Routine (ISR).
This priority selection controls the order in which
pending interrupts are passed to the software via interrupt calls. The software can then implement its own
priority structure by controlling the- mask register
(INT_MASK). To see how this is done, consider the
case ofa serial I/O service routine which must run at a
priority level which is lower than the HSI data available interrupt but hight;r than any other source. The
"preamble" and exit code for this interrupt service routine would look like this:

serial_io_isr:
PUSHF

270250-19

LDB
EI

Save the PSW
(Includes INT_MASK)
INT_MASK,#00000100B
Enable interrupts again

Figure 22. Interrupt Pending Register
Interrupt Mask Register,

Individual interrupts can be enabled or disabled by setting or clearing bits in the interrupt mask register
(INT_MASK-08H). The format of this register is the
same as that of the Interrupt Pending Register shown
in Figure 22.

POPF
RET
1-28.

S.rvi.. tho int.rrupt

Restore the PSW

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Note that location 200CH: in the interrupt vector table
would have to be loaded with the value of the label
serial_io_isr and the interrupt be enabled for this
routine to execute.
There is an interesting chain of instruction side-effects
which makes this (or any other) 8X9X interrupt service
routine execute properly: '
a) After the hardware decides to process an interrupt, it
generates and executes a special interrupt-call instruction, which pushes the current program counter
onto the stack and then loads the program counter
with the contents of the vector table entry ~orre
sponding to the interrupt. The hardware will not allow another interrupt to be serviced immediately following the interrupt-call. This guarantees that once
the interrupt-call starts, the first instruction of the
interrupt service routine will execute.
b) The PUSHF instruction, which is now guaranteed to
execute, saves the PSW in the stack and then clears
the PSW. The PSW contains, in addition to the
arithmetic flags, the INT_MASK register and the
global disable flag (I). The hardwarewiIl not allow
an interrupt following a PUSHF instruction and, by
the time the LD instruction starts, all of the interrupt enable flags will be cleared. Now there is guaranteed execution of the LD INT_MASK instruction.
c) The LD INT~MASK instruction enables those interrupts that the programmer chooses to allow to
interrupt the serial I/O interrupt service rO,lltine. In
this example only ll1e HSI data available interrupt
will be allowed to do this but any interrupt or combination of interrupts could ,be enabled at this point,
even the serial interrupt. It is the loading of the
INT_MASK register which allows the software to
establish its own priorities for interrupt servicing independently from those that the hardware enforces.
d) The EI instruction reenables the processing of interrupts.
e) The actual interrupt service routine executes within
the priority structure established by the software.
t) A:t the end of the service routine the POPF instruction restores the PSW to its state when the interruptcall occurred. The hardware will not allow interrupts
to be processed following a,POPF instruction s6the
execution of the last instruction (RET) is guaranteed
before further interrupts can occur. The reason that
this RET instruction must be prote;cted in this fashion is that it is quite likely that the i>OPF instruction
will reenable an interrupt which is already pending.
If this interrupt were serviced before the RET instruction, then the return address to the code that
was executing when the original interrupt occurred
, would be left on the stack. While this does not present a problem to the program flow, it could result in
a sta,ck overflow if interrupts are occurring at a high
frequency. TliePOPF instruction also pops the

INT_MASK register (part of the PSW), so any
changes made to this register during a routine which
ends with a POPF will be lost.
Notice that the "preamble" and exit code for the interrupt service routine does not include any code for saving or restoring registers. This is because it has been
assumed that the interrupt service routine has been allocated its own private set of registers from the onboard register file. The availa15ility of some 230 bytes of
register storage makes this quite practical.

4.3 Critical Regions
Interrupt service routines must share some data with
other routines. Whenever the programmer is coding
those sections of code which access these shared pieces
of data, great care must be taken to ensure that the
integrity of the data is maintained. Consider clearing a
bit in the interrupt pending register as part of a non-in•
terrupt routine:

LDB
ANDB
STB

AL,INT_PENDING
AL,#biLmask
AL,INT_PENDING

This code works if no other routines are operating concurrently, but will cause occasional but serious problems' if used in a concurrent envin:mment. (All programs which make use of interrupts must be considered
to be part of a concurrent environment.) To demonstrate this problem, assume that the INT_PENDING
register contains OOoollllB and bit 3 (HSO event interrupt pending) is to be reset. The code does work for
this data pattern but what happens if an HSI interrupt
occurs somewhere between the LOB and the STB instructions? Before the LOB instruction INT_PENDING contains oooo1111B and after the LOB instruction so does AL. If the HSI interrupt service routine
executes at this point then INT_PENDING will
change to 0000101 lB. The ANDB changes At to
, OOOOOll,IB and the STB ,changes INT_PENDING to
00000 III B. It should be 000000 lIB. This code sequence has manged to generate a false HSI interrupt
The same basic process can generate an amazing assortment of problems and headaches. These problems can
be avoided by assuring mutual exclusion which basically means that if more than one routine can change a
variable, then the programmer must ensure exclusive
access to the variable during the entire operation on the
variable.
In many cases the instruction set of the 8X9X allows
the variable to be modified with a single instruction.
The code in the above example can be implemented
with a single instruction.

ANDB

1-29

inter

MCS®-96 8XgXARCHITECTVRAL OVERVIEW.

Instructions are indivisible so mutual exclusion is ensured in this case. Changes to the INT,-PENDING ..
register must be made·as a single instruction, since bits
can be changed in this register even if interrupts are
disabled. Depending on system configurations, several
other SFRs might also need to be' changed in a single
instruction for the same reason.
When variables must be modified without interruption,
and a single instruction can not be used, the programmer must create what is termed a critical region in
which it is safe to modify the variable. One way to do
this is to simply disable interrupts with a D I instruction, perform the modification, and then re-enable interrupts with an EI instruction. The problem with this
approach is that it leaves the interrupts enabled even if
they were not enabled at the start. A better solution is
to enter the critical region with a PUSHF instruction
which saves the PSW and also clears the. interrupt enable flags. The region can then be terminated with a
POPF instruction which. returns the interrupt enable to
the state it was in before the code sequence. It should be
noted that some system configurations might require
more protection to form a critical region. An example
is a system in which more than one processor has access to a common resource such as memory or external
I/O devices.

4.4 Interrupt Timing
Interrupts are not always acknowledged immediately.
If the interrupt signal does not occur prior to 4 statetimes before the end of an instruction, the interrupt will
not be acknowledged until after the next instruction has
been executed. This is because an instruction is fetched
and prepared for execution a few state times before it is
actually executed.

STATE TIMES
EXECUTION

432 1
(
ENDING
) INSTRUCTION

EXTINT~
PENDING
BIT
RESPONSE TIME

'({

There are 6 instructiorts whiph always inhibit interrupts
from I?eing acknowledged until after th~ next instru~
tion has been executed. These instructions are:
~ Enable and Disable Interrupts .'
EI, DI
POPF, PUSHF-;- Pop and Push Flags
SIGND
...,... Prefix tQ' perform signed multiply
and divide (Note that Jhisis not an
ASM-96 Mnemonic,but is used for
signed multiply and divide)
SOFTWARE
TRAP
- Software interrupt
When an interrupt is acknowledged, the interrupt
pending bit is cleared, and a call is forced to the location indicated by the specified interrupt vector. This
call occurs after the completion of the instruction in
process, except as noted above. The procedure of getting the vector and forcing the call requires- 21 state
times. If the stack is in external RAM an additional 3
state times are required.
The maximum n).l)l1ber of state times required from the
time an interrupt is generated (not acknowledged) until
the 8X9X begins executing code at the desired location
is the time of the longest instruction, NORML (Normalize - 42 state times), plus the. 4 'state times prior to
the end of the previous instruction, plus the response
time (21 to 24 state times). Therefore, the maximum
response time is 70 (42 + 4 + 24) state times. This
does. not include the 12 state times required for PUSHF
if it is used as the first instruction in the interrupt routine' or additional latency caused by having the interrupt masked or disabled. Refer to Figure 22A, Interrupt Response Time, to visualize an example of a worst
case scenario.

END
CALL IS
'NORML)",}_'_N_OR_M_L_'~.....
F_OR_C_E_D.,./)

IF STACK
EXTERNAL

INTERRUPT ROUTINE

..J"S~E~T-----------;lcLEARED
•

114'~-------70 STATE TIMES-------"o....,..---I
270250-60

Figure 22A. Interrupt Response Time

1-30

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

Interrupt latency time can be reduced by careful selec,tion of instructions in areas of code where interrupts
are expected. Using. 'El' followed immediately by a
long instruction (e.g. MUL, NORML, etc.) will increase the maximum latency by 4 state. times, as an
interrupt cannot occur between EI and the instruction
following in. The "DI", "PUSHF", "POPF" and
:'TRAP" instructions will also cause the same situation. Typically the PUSHF, POPF and TRAP instructions would only effect latency when one interrupt
routine is already in process, as these instructions are
seldom used at other times.

5.0 TIMERS
Two l6-bit timers are available for use on the 8096. The
first is designated "Timer I", the second, "Timer 2".
Timer I is used to synchronize events to real time,
while Timer 2 can be clocked externally and synchronizes events to external occurrences.

5.1 Timer 1
Timer 1 is clocked once every eight state times and can
be cleared only by executing a reset. The only other
way to change its value is by writing to OooCH but this
is a test mode which sets both timers to OFFFXH and
should not be used in programs.

5.2 Timer 2
Timer 2 can be incremented by transitions (one count
each transition, rising and falling) on either T2CLK or
HSI.1. T2CLK is not available on the 8X98. The mul-

tiple functionality of the timer is determined by the
state of 1/0 Control Register 0, bit 7 (IOCO.7). To ensure that all CAM entries are chec\<.ed each count of
Timer 2, the maximum transition speed is limited to
once per eight state times. Timer 2 can be cleared by~
executing a reset, by setting lOCO. I, by triggering HSO
channel OEH, or by pulling T2RST or HSI.O high. The
HSO and CAM are described in Section 7 and 8.
IOCO.3 and ICOO.S control the resetting of Timer 2.
Figure 23 shows the different ways of manipulating
Timer 2. It is recommended that the lOCO register only
be used once during power on reset to initialize the
timers and pins, fohowed by an HSO command 14 to
clear Timer 2 internally; or externally cleared by the
T2RST or HSI.O pins. T2RST is not available on the
8X98. Some 8X9XBH devices have errata associated
with Timer 2. See the data sheets for more information.

5.3 Timer Interrupts
Both Timer I and Timer 2 can be used to trigger a
timer oyerflow interrupt and set a flag in the 1/0 Status
Register I (lOS 1). The interrupts are controlled by
IOC1.2 and IOC1.3 respectively. The flags are set in
IOS1.S and 1081.4, respectively.
Caution must be used when examining the flags, as any
access (including Compare and Jump on Bit) of 10SI
clears bits 0 through S including the software timer
flags. It is, therefore, recommended to write the byte to
a temporary register before testing bits. The general enabling and disabling of the timer iriterrupts are controlled by the Interrupt Mask Register bit O. In all cas- .
. eg., setting a bit enables a function, while clearing a bit
disables it.

IOCO.S

270250-22

Figure 23. Timer 2 Clock and Reset Options

1-31.

MCS®·96 8X~X ARCHITECTURAL OVERVIEW

5.4 Timer Related Sections,

6.0 HIGH SPEED INPUTS

The High Speed I/O unit is coupled to the timers in
that the HSI records the value on Timer 1 when transitions occur and the HSO causes transitiOlis to occur
based on values of either Timer 1 or Timer 2. The baud
rate generator can use the T2CLK pin as input to its
counter. a complete listing of the functions of 10Sl,
lOCO, and lOCI are in Section 11.

The High Speed Input Unit (HSI), can be used to record the time at which an event occurs with respect to
Timer 1: There are 4 lines (HSI.O through HSI.3)
which clm be used in this mode' and up to a total of 8
events can be recorded. HSI.2 and HSI.3 are bidirectional 'pins which can also be used as HSO.4 and
HSO.S. The I/O Control Registers (lOCO and IOCt)
are used to determine the functibns of these pins. A
block diagram of the HSI unit is shown in Figure 24:

FIfO
INTERRUPT
&;

CONTROL LOGIC

8x20 BIT

FIFO

+iSI PINS
~LO

~OHI

--'Hi(,R LoL-

t
t
.IlJ'1.I'lJ1.I1
EVERY EIGHTH POSITIVE
TRANSITION
270250-23

Figure 24. High Speed Input Unit

.1-32

intJ

MCS®·96 8X9X ARCHITECTURAL OVERVIEW

events. It can take up to 8 state times for this information to reach the holding register. For this reason, 8
state times must be allowed between consecutive reads
of HSI_TIME. When the FIFO is full, for a total of 8
events, were be stored by considering the holding register part of the FIFO. If the FIFO and holding register
are full, any additional events will cause an overflow
condition. Any eight consecutive events will overflow
on the ninth event if the program does not clear all
e.ntries in the FIFO before the ninth event occurs. Some
versions of the 8X9X have errata associated with the
HSI unit. See the data sheets for more infor.mation.

6.1 HSI Modes
There are 4 possible modes of operation for each of the
HSI pins. The HSI mode register is used to control
which pins will look for what type of events. The 8-bit
register is set up as shown in Figure 25.
High and low levels each need to be held for at least 1
. state time to ensure proper operation. The maximum
input speed is I event every 8 state times except when
the 8 transition mode is used, in which case it is I
transition per state' time. The divide by eight counter
can only be zeroed in mid-count 'by performing a hardware reset on the 8X9X.

6.3 HSI Interrupts
Interrupts can be generated by the HSI unit in three
ways; two FIFO related interrupts and 0 to I transitions on the HSLO pin. The HS10 pin can generate
interrupts even if it is not enabled to the HSI FIFO.
Interrupts generated by this pin cause a vector through
location 2008H. The FIFO related interrupts are controlled by bit 7 ofI/O Control Register I, (IOCI.7). If
the bit is a 0, then an interrupt will be generated every
time a value is Iqaded into the holding register. If it is a
I, an interrupt will only be generated when the FIFO,
(independent of the holding register), has six entries in
it. Since all interrupts are rising edge triggered, if
IOCI.7 = I, the processor will not be re-interrupted
until the FIFO first contains 5 or less records, then
contains six or more.

HSI_Mode (03H)

171 6 I 5

I 3 2111 0 I

HSI.O

~ODE

HSI.l·

~ODE

HSI.2

~ODE

HSI.3 MODE
WHERE EACH 2 - BIT MODE CONTROL FIELD
DEFINES ONE OF 4· POSSIBLE MODES:

00
01
10
11

8 POSITIVE TRANSITIONS
EACH POSITIVE TRANSITION
EACH NEGATIVE TRANSiTION
EVERY TRANSITION
(POSITIVE AND NEGATIVE)

270250-24

Figure 25. HSI Mode Register Diagram

6.4 HSI Status

The HSI lines can be individually enabled and disabled
using bits in lOCO, at location OOI5H. Figure 26 shows
the bit locations which control the HSI pins. If the pin
is disabled, transitions will not be entered in the FIl2'O.

Bits 6 and 7 of the I/O Status register I (lOS I) indicate
the status of the HSI FIFO. If bit 6 is a I, the FIFO
contains at least six entries. If bit 7 is a 1, the FIFO
contains at least 1 entry and the HSI holding register
has data available to be read. The FIFO may be read
after verifying that it contains valid data. Caution must
be used when reading or testing bits in IOS1, as this
action clears bits 0-5, including the softwah; and hardware timer overflow flags. It is best to store the byte
and then test the stored value. See Section 11.

T2RST~5

HSI.O

Y,lO-,---:-- T2 RESET
"-·IOCO.3

;--IOCO.O

:i""-o_-..,..---- HSI
• _. IOCO.2

~'-o---"---- HSI

HSI.l ~
T2CLK ~ : _. IOCO.7
HSI,2

r-- IOCO.4
~""'-oo------

TIMER2
CLOCK

Reading the HSI is done in two steps. First, the HSI
Status register is read to obtain the current state of the
HSI pins and which pins had changed at the recorded
time. The format of the HSI_STATUS Register is
shown in Figure 27. Second, the HSI Time register is
read. Reading the Time register unloads one level of the
FIFO, so if the Time.register is read before the Status
register, the event information in the Status register will
be lost. The HSI Status register is at location 06H and
the HSI Time registers are in locations 04H and 05H:

HSI .

; _. IOCO.6
HSI.3

~""'-o_-----

HSI

270250-25

Figure 26. lOCO Control Of HSI Pin Functions

6.2 HSI FIFO

If the HSI_TIME register is read without the holding
register being loaded, the returned value will be indeterminate. Under the same conditions, the four bits in

When an HSI event occurs, a 9x20 FIFO stores the 16
bits of Timer I and the 4 bits indicating which pins had

1-33

MCS®~96

8X9X ARCHITECTURAL OVERVIEW

HSI_STATUS indicating which events have occurred
will also be indeterminate. The four, HSI_STATUS
bits which indicate the current state of the pins will
always return the correct value.
It should be noted that many of the Status register conditions are changed by a reset, see Section 13. A complete listing of the functions of IOS0, lOS 1, and IOC 1
can be found in Section 11.

7.0 HIGH SPEED OUTPUTS

7;1 HSO CAM
A block diagram of the HSO .unit is shown in Figure
28. The Content Addressable Memory (CAM) file is
the center of. control. One CAM register is compared
with the timer values every state time, taking 8 state
times to compare all CAM registers with the timers.
This defines the time resolution of the HSO to be 8
state times (2.0 microseconds at an oscillator frequency·
of 12 MHz).

,-----------------,
HSI Status,.Register (HSI....;Status)

The High Speed Output unit, (HSO), is used to trigger
events at specific times with minimal CPU overhead.
These events include: starting an A to D conversion,
resetting Timer 2, setting 4 software flags, and switching 6 output lines (HSO.O through HSO.5). Up to eight
events can be pending at one time and interrupts can be
generated whenever any. of these events are triggered.
HSO.,4 and HSO.5 are bidirectional pins which can also
be used as HSI.2 and HSI.3 respectively. Bits 4 and 6 of
I/O Control Register 1, (IOCI.4, IOC1.6), enable
HSO.4
..:..
VB1A:L

To perform the actual analog-to-digital conversion the
8X9X implements a successive approximation algorithm. The converter hardware consists of a 256-resistor ladder, a comparator, coupling capacitors 'and a
IO-bit successive approximation register (SAR) with
'Iogic that guides the process. The resistor ladder pro·
vides 20 mV steps (VREF = 5.12V), while capacitive
coupling is used'to create 5 mV steps within the 20 mV
ladder voltages. Therefore, 1024 internal reference voltages are available for comparison against the analog
input to generate a IO-bit conversion result.

270246-14

Figure '13. Idealized AID Sampling Circuitry

External circuits with source impedances of 1 KO or
less will be able to maintain an input voltage within a
tolerance of about to.61 LSB (1.0 KO x 3.0 J.l.A
= 3.0 mY) given the D.C. leakage. Source impedances
above 2 KO can result in an external error of at least
one LSB due to the voltage drop caused by the 1 J.l.A
leakage. In addition, source impedances above 25 KO
may degrade converter accuracy as a result of the intern~1 sample capacitor not being fully charged during the
1 J.l.s (12 MHz clock) sample window.

A successive approximation conversion is performed by
comparing a sequence of reference voltages, to the analog input, in a binary search for the reference voltage
that most closely matches the input. The '/. full scale
reference voltage is the first tested. This corresponds to
a 10·bit result where the most significant bit is zero,
and all other bits are ones (011 U 111.11 b). If the ana·
log input was less than the test vbltage, bit 10 of the
SAR is left a zero, and a new test voltage of '/. full scale
(00 11.1111.11 b) is tried. If this test voltage was lower
than the analog input, bit 9 of the SAR is set and bit 8
is cleared for the next test (0101.1111.11b). This binary
search continues until 10 tests have occurred, at which
time the valid IO-bit conversion result resides in the
SAR where it can be read by software.

If large source impedances degrade converter accuracy
because the sample capacitor is not charged during the
sample time, an external capacitor connected to the pin
will compensate for this degradation. Since the sample
capacitor is 2 pF, a 0.005 J.l.F capacitor will charge the
sample capacitor to an accurate input voltage of to.S
LSB(2048 X 2 pF). An external capacitor does not
compensate for the voltage drop across the source resistance, but charges the sample capacitor fully during
the sample time.

2-13

8X9X HARDWARE DESIGN INFORMATION

Placing an external capacitor on each analog input will
also reduce the sensitivity to noise, as the capacitor
combines with series resistance in the external circuit to
form a low-pass filter. In practice, one should include a
small series resistance prior to the external capacitor on
the analog input pin and choos~ the largest capacitor
value practical, given the frequency of the signal being
converted. This provides -a low-pass filter on the input,
while the resistor will also limit input current during
over-voltage conditions.

Note that if only ratiometric information is desired,
VREF can be connected to V. In addition, VREF and
ANGND must be connected even if the AID converter
is not being used. Remember that Port 0 receives its
power from the VREF and ANGND pins even when it
is used as digital 1/0.

3.4 The AID Transfer Function
The conversion result is a lO-bit ratiometric representation of the input voltage, so the numerical value obtained from the conversion will be:

Figure 14 shows a simple analog interface circuit based
upon the discussion above. The circuit in the figure also
provides limited protection against over-voltage conditions on the analog input. Should the input voltage inappropriately drop significantly below ground, diode
D2 will forward bias at about 0.8 VDC. Since the specification of the pin has an absolute maximum low voltage of -0.3V, this will leave about 0.5V across the
270n transistor, or about ~ mA of current. This should
limit the current to a safe amount. However, before any

INT [1023

- ANGND)/(VREF - ANGND)].

This produces a stair-stepped transfer function when
the output code is plotted versus input voltage (see Figure 15). The resulting digital" codes can be taken as
simple ratiometric information, or they can be used to
provide information abou't absolute voltages or relative
voltage changes on the inputs. The more demanding
the application is on the AID converter, the more important it is to fully understand the converter's operation. For simple applications, knowing the absolute error of the converter is sufficient. However, closing a
servo-loop with analog inputs ll,ecessitates a detailed
understanding of an AID converter's operation and errors.

circuit is used in an actual application, it should be thoroughly analyzed for applicability to the specific problem
at hand.

VREF
01
FROM USER

x (VIN

CIRCUIT ::>--....---'WIr-_.rlI ANALOG
INPUT PIN

The errors inherent in an analog-to-4igital conversion
process are many: quantizing error; zero offset; fullscale error; differential non-linearity; and non-linearity.
These are "transfer function" errors related to the AID
converter. In addition, cOhverter temperature drift,
. Vee rejection, sample-hold feedthrough, multiplexer
off-isolation, channel-to-channel matching and random
noise should be considered,. Foitunately, one "Absolute
!?rror" specification is available which describes the
sum total of all deviations between the actual conversion process and an ideal converter. However, the various sub-componenfs of error are important in many
applications. These error components are described in
Section 3.5 and in the text below where ideal and actual
converters are compared.
o

ANGNO
270246-15

Figur, 14. Suggested AID Input Circuit

3.3 Analog. References
Reference supply levels strongly influence the absolute
accuracy of the conversion. For this reason, it is recommended that the ANGND pin be tied to the two Vss
pins as close to the chip as possible with minimum trace
length.' Bypass capacitors should also be used between
VREF and ANGND. ANGND should be within about
a tenth of a volt Vss. VREF should be well regulated
and used only for the AID converter. The VREF supply
can be between 4.5V and 5.5V and needs to be able to
source around 5 mAo Figure 6 shows all of these cdnnections.

An unavoidable error simply results from the conversion of a continuous voltage to an integer digital representation. This error is called quantizing error, and is
always ± 0.5 LSB. Quantizing err~r is the only error
seen in a perfect AID converter, and is obviously present in actual converters. Figure 15 sho~s the transfer
function for an ideal 3-bit AID converter (i.e. the Ideal
Characteristic).

2-14

inter

8X9X HARDWARE DESIGN INFORMATION

Note that in Figure 15 the Ideal Characteristic possesses unique qualities: it's first code transition occurs when
the input voltage is 0.5 LSB; it's full-scale code transition occurs when the input voltage equals the fullscale reference minus 1.5 LSB; and it's code widths are
all exactly one LSB. These qualities result in a digitization without offset, full-scale or linearity errors. In other words, a perfect conversion.
Figure 16 shows an Actual Characteristic of a hypothetical 3-bit converter, which is not perfect. When the
Ideal Characteristic is overlaid with the imperfect characteristic, the actual converter is seen to exhibit errors
in the location of the first and final code transitions and
code widths. The deviation of the first code transition
from ideal is called "zero offset", and the deviation of
the final code transition from ideal is "full-scale error".
The deviation of the code widths from ideal causes two
types of errors. Differential Non-Linearity and NonLinearity. Differential Non-Linearity is a local linearity
error measurement, whereas Non-Linearity is an overall linearity error measure.

only. A converter is monotonic if every subsequent
code change represents an input voltage change in the
same direction.
Differential Non-Linearity and Non-Linearity are
quantified by measuring the Terminal Based Linearity
Errors. A Terminal Based Characteristic results when
an Actual Characteristic is shifted and rotated to eliminate zero offset and full-scale error (see Figure 17). The
Terminal Based Characteristic is similar to the Actual
. Characteristic that would be seen ifzero offset and full. scale error were externally trimmed away. In practice,
this is done by using input circuits which include gain
and offset trimming. In addition, VREF on the 8X9X
could also be closely regulated and trimmed within the
specified range to affect full-scale error.
Other factors that affect a real AID Converter system
include sensitivity to temperature, failure to completely
reject all unwanted signals, multiplexer channel dissimilarities and random noise. Fortunately these effects are
small.
Temperature sensitivities are described by the rate at
which typical specifications change with a change in
temperature.

Differential Non-Linearity is the degree to which actual
code widths differ from the ideal one LSB width. Differential Non-Linearity gives the user a measure of how
much the input voltage may have changed in order to
produce a one count change in the conversion result.
Non-Linearity is the worst case deviation of code transitions from the corresponding code transitions of the
Ideal . Characteristic. Non-Linearity describes how
much Differential Non-Linearities COUld add up to produce an overall maximum departure from a linear characteristic. If the Differential Non-Linearity errors are
too large, it is possible for an AID converter to miss
codes or exhibit non-monotonicity. Neither behavior is
desireable in a closed-loop system. A converter has no
missed codes if there exists for each output code a
unique input voltage range that produces that code

Undesired signals come from three main sources. First,
noise on Vee-Vee Rejection. Second" input signal
changes on the channel being converted after the sample window has closed-Feedthrough. Third, signals
applied to channels not selected by the multiplexerOff-Isolation.
Finally, multiplexer on-channel resistances differ slightly from one channel to the next causing Channel-toChannel Matching errors, and random noise in general '
results in Repeatability errors,

2-15

-71

I It

FINAL CODE TRANSITION OCCURS
WHEN THE APPLIED VOLTAGE IS
EQUAL TO (Vref - 1 1/2 (LSB».
6

I
II

5-1

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US'

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ACTUAL CHARACTERISTIC OF
AN IDEAL A/D CONVERTER

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....
c

m
m
en
is

THE VOLTAGE CHANGE
BETWEEN ADJACENT CODE
TRANSITIONS (THE "CODE
WIDTH") IS
1 LSB,

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-...

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"TI

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s:
>
~
0Z

('j'

I
FIRST CODE TRANSITION OCCURS
WHEN THE APPLIED VOLTAGE IS
EQUAL TO 1/2 LSB,

0 1
1/2

INPUT VOLTAGE (LSBs)

61/2

270246-16

--1

ER~

fULL SCALE ERROR

I CHARACTERISTIC
IDEAL
I

ABSOLUTE ERROR

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~ CHARACTERISTIC
ACTUAL
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~ ZERO OFFSET I
1/2

INPUT VOLTAGE (LSBs)

270246-17

(

7
IDEAL FULL-SCALE CODE
TRANSITION

ACTUAL
FULL-SCALE CODE
TRANSITION

ACTUAL
CHARACTERISTIC

..,

r '"

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oV
1/2

INPUT VOLTAGE (LSBs)

61/2

270246-18

8X9X HARDWARE DESIGN INFORMATION

3.5 AID Glossary of Terms

D.C. INPUT LEAKAGE-Leakage current to ground
from an analog input pin.

Figures 15,16 and 17 display many of these terms.
ABSOLUTE ERROR---':The maximum difference between corresponding actual and ideal code transitions.
Absolute Error accounts for all deviations of an actual
converter from an ideal converter.
ACfUAL CHARACfERISTlC-The characteristic of
an actual converter. The characteristic of a given converter may vary over temperature, supply voltage, and
frequency conditions. An Actual Characteristic rarely
has ideal first and last transition locations or ideal code
widths. It may even vary over multiple conversion under the same conditions.
BREAK-BEFORE-MAKE-The property of a multiplexer which guarantees that a previously selected
channel will be deselected before a new channel isselected. (e.g. the converter will not short inputs
together.)

DIFFERENTIAL NON-LINEARITY-The difference between the ideal and actual code widths of the
terminal based charaCteristic of a converter.
FEEDTHROUGH-Attenuation of a voltage applied
on the selected channel of the AID converter after the
sample window closes.
FULL SCALE ERROR-The difference between the
expected and actual input voltage corresPonding to the
full scale code transition.
IDEAL CHARACTERISTlC-'-A characteristic with
its first code transition at VIN = 0.5 LSB, its last code
transition at VIN = (VREF - 1.5 LSB) and all code
widths equal to one LSB.
INPUT RESISTANCE-The effective series resistance
from the analog input pin to the sample capacitor.
LSB-LEAST SIGNIFICANT BIT: The voltage value
corresponding to the full scaie voltage'divideC! 'by 2n,
where n is the number of bits of resolution of the converter. For a lO-bit converter with a reference voltage
of 5.12 volts, one LSB is 5.0 mV. Note 'that ihis is
different than digital LSBs, since an uncertainty of two
LSB, when referring to an AID converter, equals
10 mY. (This has been confused with an uncertainty of
two digital bits, which would mean four counts, or

CHANNEL-TO-CHANNEL MATCHING-The difference between corresponding code transitions of actual characteristics taken from different channels under
the same temperature, voltage and frequency conditions.
CHARACfERISTlC-A graph of input voltage versus the resultant output code for an AID converter. It
describes the transfer function of the AID converter.

20 mV.)

CODE-The digital value output by the converter.
MONOTONIC-The property of successive approximation converters which guarantees that increasing input voltages produce adjacent codes of increasing value,
and that decreasing input voltages produce adjacent
codes of decreasing value.

CODE CENTER-The voltage corresponding to the
midpoint between two adjacent code transitions.
CODE TRANSITION-The point at which the converter changes from an output code of Q, to a code of
Q+ 1. The input voltage corresponding to a code transition is defined to be that voltage which is equally likely to produce either of two adjacent codes.

NO MISSED CODES-For each and every output
code, there exists a unique input voltage range which
produces that code only.
NON-LINEARITY -The maximum deviation of code
transitions of the terminal based characteristic from the
corresponding code transitions of the ideal characteristics.

CODE WIDTH-The voltage corresponding to the
difference between two adjacent code transitions.
CROSSTALK-See "Off-Isolation".

2-19

8X9X HARDWARE DESIGN INFORMATION

OFF.~SOLATlON-':Attenuation of a voltage applied
on /l deselected channel of the AID converter. (Also
referred to as Crosstalk.)

TERMINAL BASED CHARACTERISTIC-An Actual Characteristic which as been rotated and translated to .remove zero offset and full-scale error.

REPEATABILITY-The difference between corresponding code transitions from different actual characteristics takim from the same converter on the same
channel at the same temperature, voltage and frequency
conditions.

VCC REJECTION-Attenuation of noise on the Vee
line to the AID converter.
ZERO OFFSET-The difference between the expected
and actual input voltage corresponding to the first code
transition.

RESOLUTION-The number of input voltage levels
that the converter cap unambiguously disting~ish 'between. Also d¢fines the number of useful bits of information which the converter can return.

4.0 ANALOG OUTPUTS
Analog outputs can be generated by two methods, either by using the PWM output or the HSO. Either
device will generate a rectangular pulse train that varies
in duty cycle and/ (for the HSO only) period. If a
smooth analog signal is desired as an output, the rectangular waveform must be filtered.

SAMPLE DELAY-The delay from receiving the start
conversion signal .to when the sample window opens.
SAMPLE DELAY UNCERTAINTY-The variation
in the Sample Delay.

In most cases this filtering is best done after the signal
is buffered to make it swing from 0 to 5 volts since both
of the outputs are guaranteed only to TTL levels. A
block diagram of the type of circuit needed is shown in
Figure 18. By proper selection of components, accounting for temperature and power supply drift, a highly
accurate 8-bit D,to A converter can be made using either the HSO or the PWM output. Figure 19 shows two
typical circuits. If the HSO is used the accuracy could
be theoretically extended to 16-bits, however the temperature and noise related problems wouid be extremely hard to handle.

SAMPLE tIME-The time that the sample window is
open.
S~PLE TIME UNCERTAINty-The variation in
tlte sample time:

SAMPLE WINDOW-Begins when the sample capacitor is attached to a selected channel and ends when the
sample capaCitor is disconnected from the selected
channel.
SUCCESSIVE APPROXIMATION-An AID conversion method which uses a binary search to arrive at
the best digital representation of an analog input.

When driving some circuits it may be desirable to use
unfiltered Pulse Width Modulation. This is particularly
true for motor drive circuits. The PWM output can be
used to generate these waveforms if a fixed period on
the order of 64 J.ts is acceptable. If this .is not the case
then the HSO unit can be used. The HSO can generate
a variable waveform with a duty cycle variable in up to
65536 steps and a period of up to 131 milliseconds.
Both of these outputs produce TTL levels.

TEMPERATURE COEFFICIENTS-Change in the
stat~ variable per degree centigrade temperature
change. Temperature coefficients are added to the typical values of a specification to see the effect of temperature drift.

8X9X
HSO
OR
PWM

BUFFER
TO MAKE
OUTPUT
SWING
RAIL
TO
RAIL

FILTER
(PASSIVE
OR
ACTIVE)

POWER
AMP
(OPTIONAL)

(OPTIONAL)

ANALOG
OUTPUT

270246-21

Figure 18. D/A Buffer Block Diagram

. 2-20

inter

8X9X HARDWARE DESIGN INFORMATION

Vcc

* 1/2 VQ3001P
6

5.1~

270'
PWM----~VV~----

.-____~~__--~.-----ANALOG
OUT
8

9
270246-22
'This resistor limits rise time to. reduce
spikes & high frequency noise.

8X9X
HSO
PWM

HIGH

,OR ~---I

~~----~~----~r-------~ IMPEDANCE

AMP

ANALOG
OUTPUT

. CD4049

Rand C are chosen for best
filtering at the user's frequency

270246-23

Figure 19. Buffer Circuits for 01 A

5.0 1/0 TIMINGS
The lIO pins on the 8X9X are sampled and changed at
specific times within ll-n instruction cycle. The changes
occur relative to the internal phases sjJ.own in Figure 4.
Note that the delayrrom XTALI to the internal clocks
range from about 30 ns to lOP ns over process and
temperature. Signals generated by internal phases are
further delayed by 5 ns to is ns. The timings shown in
this section are idealized; no propagation delay factors
have been taken into account. Designing a system that
depends on an I/O pin to change within a window of
less than SO ns using the information in this section is
not recommended.

5,,1 HSO Outputs
Changes in the HSO lines are synchronized to Timer 1.
All of the external HSO lines due to change at a certain
value of a timer will change just pior to the incrementing of Timer 1. This corresponds to an internal change

during Phase B every eight state times. From an exter;
nal perspective the' HSO pin should change just prior to
the rising edge of CLKOUT arid be stable by its falliI'lg
. edge. Information from the HSO can be latched on the
CLKOUT falling edge. Internal events can occur anytime during the 8 state time window.
Timer 2 is synchronized to increment no faster than
Timer I, so there will always be'at least one incrementing of Timer I, while Timer 2 is at a specific value.

5.2 HSI Input Sampling.
The HSI pins are sampled internaUy once each state
time. Any value on these pins must remain stable for at
least 1 full state time to guarantee that it is recognized.
The actual sample occurs at the end of Phase A, which,
. due to propagation delay, ,is just after the rising edge of
CLKOUT. Therefore, 'if information is to be synchronized to the HSI it should be latched-in on CLKOUT

2-21

intJ

8XQX,HARDWARE DESIGN INFORMATION

falling. The time restriction applies even if t\le divide by
eight mode is being used. If two events occur on the
same pin within the same 8 state time wil).dow, only one
of the events will be recorded. If the events occur on
different pins they will always be 'reco~ded, regardless
of the time difference. The 8 state time window, (Le. the
amount of time during which Timer 1 remains, constant), is stable to within about 20, ns. The window
starts roughly around the rising edge of CLKOUT,
however this timing is very approximate due to the
amount of internal circuitry involved.

5.3 Standard I/O Port Pins
Port 0 is different from the other digital ports in that it
is actually part of the A/D converter. The port is sampled once every state time, however, sampling is not
synchronized to Timer 1. If this port is used, the input
signal on the pin must be stable one state time before
the reading of the SFR.

the rest of the 8X9X so that information can be passed
back and forth.
The baud rate generator is clocked by either XTALI or
T2CLK. Because T2CLK needs to be synchronized to
the XTALl signal its speed must be limited to '/'6 that
of XTAL I. The serial port will not function during the
time between the consecutive writes to the baud rate
register. Section 11.4 of the 8X9X Architecture chapter
discusses programming the baud rate generator.

6.1 Mode 0
Mode 0 is the shift register mode. The TXD pin sends
out a clock train, while the RXD pin transmits or receives the data. Figure 20 shows the waveforms and
timing. Note that the port starts functioning when a '1'
is written to the REN (Receiver Enable) bit in the serial
port control register. If REN is already high, clearing
the RI flag will start a reception.

Port 1 and Port 2 have quasi-bidirectional I/O pins.
When used as inputs the data on these pins must be
stable one state time prior to reading the SFR. This
timing is also valid for the input-only pins of Port 2 and
is similar to the HSI in that the sample occurs just after
the rising edge of CLKOUT. When used as outputs, the
quasi-bidirectional pins will change state shortly after
CLKOUT falls. If the change was from '0' to a '1' the
low impedance pullup will remain on for one state time
after the change.
'

In this mode the serial port can be used to expand the
I/O capability of the 8X9X by simply adding shift registers. A schematic of a typical circuit is shown in Figure 21. This circuit inverts the data coming in, so it
must be reinverted in software. The enable and latch
connections to the shift registers can be driven by decoders, rather than directly from the low speed I/O
ports, if the software and hardware are properly designed.'
,

Ports 3 and 4 are addressed as off-chip memorymapped I/O. The port pins will change state shortly
after the rising edge ofCLKOUT. When these pins are
used as Ports 3 and 4 they are open drains, their structure is different when they, are used as part of the bus.
See Section 10.4 of the 8X9X Architecture chapter. Additional information on port reconstruction is available
in Section 7.7 of this chapter.

6.2 Mode 1 Timings
Mode 1 operation of the serial port makes use of lO-bit
data packages, a start bit, 8 data bits and a stop bit. The
transmit and receive functions are controlled by separate shift clocks. The transmit shift clock starts when
the baud rate generator is initialized, the receive shift
clock is reset when a 'I to 0' transition (start bit) is
received. The transmit clock may therefore not be in
sync with the receive clock, although they will both be
at the same frequency.
'

6.0 SERIAL PORT TIMINGS
The serial port on the 8X9X was'designed to be compatiblewith the 8051 serial port. Since the 8051 uses a
divide by 2 clock and the 8i\9X uses,a divide by 3, the
serial port on the 8X9X had to be provided with its
own clock circuit to maximize its compatibility with
the 8051 at high baud rates. This means that the serial
port itself does not krlow about state times. There is
circuitry whiCh is synchronized to the serial port and to

The TI (Transmit Interrupt) and RI (Receive Interrupt) flags are set to indicate when operations are complete. TI is set when the last data bit of the message has
been sent, not when the stop bit is sent. If an, attempt to
send another byte is made before the stop bit is sent the
port will hold off transmission until the stop bit is complete. RI is set when 8 data bits are received, not when
the stop bit is received. Note that when the serial port
status register is read both TI and RI are cleared.

2-22

inter

8X9X HARDWARE DESIGN INFORMATION

TXD

RXD(OUTj

'04

'DO

D7
D7

AXD(INI
EXPANDED:

XTAL1~~

~~;---.

TXD

AXD(OUT) - - - - - (

DO
DO

AXD(INI

D1
01

-t:::J----!~
270246-24

Figure 20. Serial Port Timings in Mode 0

CLOCK INHIBIT

---=------jpx.x
15K

DATA

>O-t"-------1

RXD

'--__t--__...,.......:C.:;cLO:..:C.:.;,K, TXD
INPUTS ..
OUTPUTS

ENABLE

1:>-----1 PX.X
270246-25

Figure 21. Mode 0 Serial Port Example

Caution should be used when using the serial port to
connect more than two devices in half-duplex, (i.e. one
wire for transmit and receive). If the receiving processor does not wait for one bit time after .Rris set before
starting to transmit, the stop bit on the link could be
squashed. This could cause a problem,Jor other devices
listening on the link..
.

7.0 BUS TIMING AND MEMORY
INTERFACE
7.1 Bus Functionality
The 8X9X has a multiplexed (address/data) bus which
can be dynamically configured to have an 8-bit or 16bit data width. There are control lines to demultiplex
the bus (ALE or ADV), indicate reads (RD), indicate
writes (WRL and WRH, or WR with BHE and ADO),
and a signal to indicate accesses that are for an instruction fetch (INST). Section 3.5 of the 8X9X Architecture chapter contains an overview of the bus operation.

6.3 Mode 2 and 3 Timings
Modes 2 and 3 operate in a manner similar to that of
Mode I, The only difference is that the data is now
made up of 9 bits, so II-bit packages are transmitted
and received. This means that TI and RI will be set on
the 9th data bit rather than the 8th. The 9th bit can be
used for parity or multiple processor communications
(see Section 11 of the 8X9X Architecture chapter).

2-23

8X9X HARDWAREDESIG,N INFORMATION

number of inserted wait states is equal to the limit set in
the Chip Configutatidn Register (see Section 2 of the
MCS-96 Architecture chapter). There is a maximum'
time that the READY line can be held low without
risking a processor malfunction due to dynamic nodes
that have not been refreshed during the wait states.
This time is shown ~s TYLYH in the data sheet.

7.2 Timing Specifications
Figure 22 shows the timing of the bus signals and data
lines. Please refer to the latest data sheet for the exact
device you are using to ensure that your system is designed to the proper specifications. The major timing
specifications are described in Figure 23.

In most cases the READY line is brought low after the'
address is decoded and it is determined that a wait state
is needed, It is very likely that some addresses, such as
those addressing memory mapped peripherals, would
need wait states, and others would not. The READY
line must be stable within the TLLYV specification after ALE falls or the processor could lock-up. There is

7.3 READY Line Usage
When the processor has to address a memory location
that cannot respond within the standard specifications,
it is necessary to use the READY line to generate wait
states. When the READY line is held low, the processor waits in a loop for the line to come high or until the

XTAL1

CLOCKOUT

READY

-- ...,--------.,
----------_.,
'----------

BHE,INST

V_AL_I_D_____:-_-f ... ________ ____ ••

1-_ _,-_....,~__
4TAVLL ·1

,",,1.---TwLWH~

AD8-15 -~(~lL)____~::::::::::::::~VA~L~ID~::::::::::::~~~~-~-~-~-~-~-~-~-~'~-=
~.~.~.'---_ .... _--_.....
270246-26

.NOTES:
1.
2.
3.
4.

8-bit bus only.
8-bit or 16-bit bus and write strobe mode selected.
When ADV selected.
8-bit or 16-bit bus and no write strobe mode selected.

Figure 22. Bus Signal Timings

2-24

8X9X HARDWARE DESIGN INFORMATION

no requirement as to when READY may go high, as
Ions- as the maximum READY low time (TYLYH) is
not violated. To ensure that only one wait state is inserted it is necessary to provide external circuitry which
brings READY high TLLYH after the falling edge of
ALE!ADV, or program the Chip Configuration Register to select a Ready Control limit of one.

If a wait state is inserted, READY is internally latched
on the next rising edge of Phase A. If a 1 is found the
bus cycle resumes with the net impact being the insertiQn of one wait state. If a 0 is seen, a second wait state
is inserted.
'

The READY pin is again latched on the next rising
edge of CLOCKOUT if two wait states were inserted.
If the chip Sees a I, the bus cycle is resumed with the
result being an insertion of two wait states. If another 0
is seen, a third wait state is inserted in the bus cycle and
the READY pin is again latched on the following rising
edge of CLOCKOUT. If internal Ready Control is not
used, the READY line must at this point be a I to
ensure proper operation.
-

Internally, the chip latches READY on the first falling
edge of Phase A after ALE/ADV falls. Phase A is buffered and brought out externally as CLOCKOUT, so
CLOCKOUT is a delayed Phase A., If a i 'is seen, the
, bus cycle proceeds uninterrupted with no wait state insertions. If a 0 is seen, one wait state (3 Tosc) is inserted.
Tosc-Oscillator Period, one cycle time on XTALI.

TLLGV-ALE/ADV low to BUSWIDTH valid:
Maximum time after ALE/ADV is low until BU- SWIDTH must be valid. If this time is exceeded the
part could malfunction necessitating a chip reset.
Nominally less than 1 Tosc,

Timings the Memory System Must
Meet
TLLYH-ALE/ADV low to READY high: Maxi, mum time after ALE/ADV falls until READY is
brought high to ensure no more wait states. If this
time is <;xceeded unexpected wait states may reSult.
Nominally I Tosc + 3 Tosc X number of wait states
desired.
-

TLLGX-BUSWIDTH hold after ALE/ADV low:
Minimum time that BUSWIDTH must be valid at'tCr
ALE/ADV is low Nominally 1 TOse.
TRLDV-READ low to DATA valid: Maximum
time that the memory has to output data after READ
goes low. Nominally, a maximum of 3 Tosc periods.

TLLYV-ALE/ADV low to READY low: Maximum time after ALE/ADV falls until READY'must
be valid. If this time is exceeded the device could malfunction necessitating a chip reset. Nominally '2 TOsc
periods.

TRHD~READ high to DATA float: Time after

READ is high until the memory must float the bus.
The memory signal can be removed as soon as READ
is not low, and must be removed within the speci~ed
maximum time from when READ is high. Nominally
a maximum of I Tosc period.

TCLYX":'READY hold after CLOCKOUT low:
Minimu~ time that the value on the READY pin
must be valid after CLOCKOUT falls. The minimum
hold time is always zero nanoseconds.

TRHDX-DATA hold after READ goes high: Miltimum time that memory must hold input DATA valid
after RD is high., The hold time minimum is always
zero nanqseconds.

TYLYH-READY low to READY high: Maximum
time the part can be in the not-ready state. If it is
exceeded, the 8X9X dynamic nodes which hold the
current instruction may 'forget' how to finish the instruction.
'

TRLAZ-READ low to ADDRESS float: This is the
bus control specifying the time from an active-low
READ signal until the 8X9X ADDRESS drivers for
the cy~le are off the bus. This is specified in order fdr
data to be returned from the memory system without
bus contention. TypicallY,this is 0 ns for no bus,contention, However, up to 10 ns is acceptable in systems.

TAVDV-ADDRESS valid to DATA valid: Maximum time that the memory has to output valid data
after the 8X9X outputs a valid address. Nominally, a
maximum of 5 Tosc periods.
TAVGV-ADDRESS valid to BUSWIDTH valid:
Maximum time after ADDRESS becomes valid until
BUSWIDTH must be valid. Nominally less than 2
Tosc periods.
- '

Figure 23. Timing Specification Explanations

2-25

intJ

8X9X HARDWARE DESIGN INFORMATION

that proper memory decoding takes place before it is
output enabled. Nominally 2 Tosc periods.

Timings the 8096 Will Provide
T0HCH-XTALl high to CLOCKOUT high: Delay
from the rising edge of Xl'ALl to the resultant rising
edge on CLOCKOUT. Needed in systems where the
signal driving Xl' ALl is also used as a clock for external devices. Typically 50 to 100 nanoseconds.
TCHCH-CLKOUT high to CLKOUT high: The
period of CLKOUT and the duration of one state
time. Always 3 Tosc average, but individual periods
could vary by a few nanoseconds.
TCHCL-CLKOUT high to CLKOUl' low: Nominally I Tosc period.
TCLLH-CLKOUT low to ALE high: A help in d!lriving other timings. Typically plus or minus 5 ns to
10 ns.
TCLVL-CLOCKOUT low to ALE/ADV low: A
help in deriving other timings. Nominally I Tosc.
TLLCH-ALE/ADV low to CLKOUT high: Used
to derive other timings, nominally 1 Tosc period.
TLHLL-ALE/ADV high to ALE/ADV low:
ALE/ADV high time. Useful in determining ALE/
ADV rising edge to ADDRESS valid time. Nominally 1 Tosc period for ALE and 1 Tosc for ADY: with
back-to-back bus cycles.

TRLRH-READ low to READ high: RD pulse
width, nominally I Tosc period.
TRHLH-READ high to ALE/ADV high: Time between RD going inactive and next ALE/ADV, also
used to calculate time between RD inactive and next
ADDRESS, valid. Nominally I Tosc period.
TRHBX--':REAQ high to INST, BHE, ADS-IS Inactive: Minimum time that the INST ·and BHE lines
will be valid after RD goes high. Also the minimum .
time that the upper eight address lines (S-bit bus
mode) will remain valid after RD goes high. Nominally 1 Tosc.
TWHBX-WRITE high to INST, BHE, ADS-15
Inactive: Minimum time that the INST and BHE
lines will be valid after WR goes high. Also the minimum time that the upper eight address lines (S-bit bus
mode) will remain valid after WR goes high. Nomi- '
nally I Tosc.
TWLWH-WRITE low to WRITE high: Write
pulse width, nominally 3 Tosc periods.
THLHH-WRL, WRH low to WRL, WRH high:
Write strobe signal pulse width. Nominally 2 Tosc
periods.

TA VLL-ADDRESS valid to . ALE/ADY low:
Length of time ADDRESS is valid before ALE/ADV
falls. Important timing for address latch circuitry.
Nominally I Tosc period.

TQVHL-,OUTPUT valid to WRL, WRH low: Minimum time that OUTPUT data is valid prior to write
stro1;>es becoming active. Needed for interfacing to
memories that read data on the falling edge of write.
Nominally I Tosc.

TLLAX-ALE/ADV low to ADDRESS invalid:
Length of time ADDRESS is valid after ALE/ADV
falls. Important timing' for address latch circuitry.
Nominally I Tosc period.

TQVWH-OUTPUT valid to WRITE J!!Ih: Time
that the. OUTPUT data is valid before WR is high.
Nominally 3 Tosc periods.
TWHQX-WRITE high to OUTPUT not valid:
Time that the OUTPUT data is valid after WR is
high. Nominally I Tosc period.

TLLRL-ALE/ADV low to READ or WRITE low:
Length of time after ALE/ADV falls before RD or
WR fall. Could be needed to ensure that proper memory decoding takes place before it is.output enabled.
Nominally I Tosc period.
I

TWHLH-WRITE high to ALE/ADV high: Tune
between write high and next ALE/ADV, also used to
calculate the time between WR high and next ADDRESS valid. Nominally 2 Tosc periods.

TLLHL-ALE/ADV low to WRL, WRH low: Minimum time after ALE/ADV is low that the write
strobe signals will go low. Could be needed to ensure

Figure 23. Timing Specification Explanations (Continued)

)

2-26

8X9X HARDWARE DESIGN INFORMATION

bus mode, or one 74LS373 for an 8X9X in 8-bit bus
mode. As explained in Section 3.5 of the 8X9X Architecture chapter, the latched address signals will be referred to as MAO through MAl5 (Memory Address),
and the data lines will be called MOO through MDl5
(Memory Data).

7.41NST Line Usage
The INST (Instruction) line is high during bus cycles
that are for an instruction fetch and low for any other
bus cycle. The INST signal (not present on 48-pin versions) can be used with a logic analyzer to debug a
system. In this way it is possible to determine if a fetch
was for instructions or data, making the task of tracing
the program much easier.
.

Since the 8X9X can make accesses to memory for ei-.
ther bytes or words, it is necessary to have a way of
determining the type of access desired when the bus is
l6-bits wide. For write cycles, the signals Write Low
(WRL) and Write High (WRH) are provided. WRL
will go low during all word writes and during all byte
writes to an even location. Similarly, WRH will go low
. during all word writes and during all byte writes to an
odd loc~tion. During read cycles, an 8X9X in l6-bit
bus mode will always do a word read of an even location. If only one byte of the word is needed, the chip
discards the byte it does not need.

7.5' BUSWIDTH Pin. Usage
The BUSWIDTH pin is a control input which' determines the width of the bus access in progress.
BUSWIDTH is sampled after the rising edge of the first
CLOCKOUT after ALE!ADV goes low. If a one is
seen, the bus access progresses as a l6-bit cycle. If a
zero is seen, the bus access progresses as an 8-bit cycle.
The BUSWIDTH setup and hold timing requirements
appear in the data sheet.

Since 8X9X memory accesses over an 8-bit wide bus
are always bytes, only one write strobe is needed for
write cycles. For this purpose the WRL signal was
made to go low for all write cycles during 8-bit bus
accesses. When a word operation is requested, the bus
controller performs two byte-wide bus cycles.

The BUSWIDTH pin can be overridden by causing the
BUS WIDTH SELECT bit in the Chip Configuration
Register (CCR) to be zero. This will permanently select
an 8-bit bus width. However, if the BUS WIDTH SELECT bit in the CCR is a one, the BUSWIDTH pin
determines the bus width. See Section 3.5 of the 8X9X
Architecture chapter. Since the BUSWIDTH pin is not
available on 48-pin or 64-pin devices, the BUS WIDTH
SELECT bit in the CCR determines bus width.
.

In many cases it may be desirable to have a write signal
with a longer pulse width than WRL/WRH. The Write
(WR) line of the 8X9X is an alternate control signal
that shares a pin with WRL and is only available in
l6-bit bus mode. WR is nominally one Tosc longer
than the WRL/w,RH signals, 'hut goes low for any
write cycle. Therefore it is necessary to decode for the
type o'1:.vvrite (byte or word) desired.

7.6 Address Decoding
The multiplexed bus of the 8X9X must be demultiplexed before it can be used. This can be done with two
74LS373 transparent latches for an 8X9X in l6-bit

The Byte High Enable (BHE) signal and MAO can be
used for this purpose. BHE is an alternate control

Vee

BHE--------------~

WRITE HIGH
ALE - - - - I ~~--D

-cr"""

WR - - - - - - - - - - - - -.....

WRITE LOW

270246-27

Figure 24. Decoding WR and SHE to Generate WriteLow and Write High

2-27

8X9X HARDWARE DESIGN INFORMATION

signal that shares a pin with WRH. When.BHE is low,
the high byte of the 16-bit bus is enabled. When MAO is
low,- the lower byte is enabled. When MAO is low and
BHE is low, both bytes are enabled. Figure 24 shows
how to use WR, BHE and MAO to decode bus accesses.
It's important to note that this decoding inserts a delay
in the write signal which must be considered in a system timing analysis.

External memory systems for the ,8X9X can be set up
in many ways. Figures 25 through 28 show block diagrams of memory systems using an 8-bit bus with a
single EPROM, using an 8-bit bus with RAM and
EPROM, using a 16-bit bus with two external
EPROMs and using a 16-bit bus in a RAM and ROM
system. (The timings for the systems shown are optimized for 10 MHz operation.)

RD
ADS-IS

8X9X
ADO-7

HIGH ADDRESS

DATA
~

EPROM

74LS
3'73

LOW ADDRESS

""r-~

ADV

OPTIONAL IF
LATCHED EPROM
IS USED

270246-28

Figure 25. An 8-Bit Bus with EPROM Only

ADIS
CS
ADS-IS

HIGH ADDRESS
DATA

8X9X

EPROM

ADO-7

LOW ADDRESS

ADV

RD
WR

270246-29

Figure 26. An 8-Bit Bus with EPROM and RAM

2-28

inter

8X9)( HARDWARE DESIGN INFORMATION

270246-30

Figure 27. A 16-Blt Bus with EPROM Only

BUSWIDTH
AD8-1S

EPROM
ADV

ADO-7

RAM

r~;;~::JDATA
LOW ADDRESS

8X9X

270246-31

Figure 28. Memory System with Dynamic Bus Width

2-29

8X9X HAfU)WAflE,DESIGN INFORMATION
.I

It is also recommended that unused areas of code be

7.7 I/O Port Reconstructlpn
When a single-chip system' is being designed using 'a
multiple chip system as a prototype, it may be neces- ,
sary to reconstruct 1/0 Ports j and 4 !'ising a: memorymapped 1/0 technique. The circuit shown in Figure 30 '
provides this function. It can be attached to a 8X9X
system which has the required address decoding and
bus demultiplexing.
The output circuitry is basically just a latch that operates when IFFEH or IFFFH are placed on the MA
lines. The inverters surrounding the latch create an
open-collector output tQ' emulate the open-drain output
found on the 8X9X. The 'reset' line is, used to set the,
ports to all l's when the 8X9X is reset. It should be
noted that the voltage and current characteristics of the
port will differ from those of the 8X9X, but the basic
functionality will be the same.
The input circuitFY is just a bus transceiver that is addressed at lFFEH or IFFFH. If the ports are going to
be used for either input or output, but not both, some of
the circuitry can be eliminated.

8.0 NOISE PROTECTION TIPS
Designing controllers differs ffom designing-other computer equipment in the area of noise protection. A microcontroller circuit under the h~ of a car, in a photocopier, CRT terminal, or a 'high speed printer is subject to many :~ypes of electrical noise. Noise can get to
the processor-directly through the power supply, or it
can be induced onto the board by electromagnetic
fields. It is also possible for, the PC board to find itself
in the path of. electrostatic discharges. Glitches and
noise on the PC board can' cause the processor to act
unpredictably, usually by changing either the memory
-locations or the program counter.
There are both hardware and software solutions to
noise problems, but the best solution -is good design
practice and a few ounces of prevention. The 8X9X has
a Watchdog Timer which will reset the device if it fails
to execute the software properly. The software should
be set up to take advantage of this feature.

filled with NOPs and periodic jumps to an error routine
or RST (reset chip) instructions. This is particularly
important in the code around lookup tables, since if
lookup tables ,are executed all sorts of bad things can
happen. Wherever space allows, each table should be
surrounded by 7 NOPs (the longest 8X9X instruction
has 7 bytes) and a RST or jump to error routine instruotion. This will help to ensure a speedy recovery ,
should the proceSsor have a glitch in the program flow.
Many hardw~e' ,solutions exist for keeping PC board
noise to a plinimum. Ground planes, gridded ground
and Vee structures, bypass papacitors, transient absorbers and power busses with built·in capacitors can
, all be,of great help.,It is mucll easier to design a board
with these' features than to try to retrofit them later.
Proper PC board layout is probably the single most
important and, unfortunately, least understood aspect
of project design. Minimizing loop areas and inductance, as well as providing clean grounds are very important. More information on protecting against noise
can be found in the Application Note AP-125, "Designing Microcontroller Systems for Noisy Environments".

9.0 PACKAGING
The MCS-96 family o( prcidu~ts is offered in many versions. They are lj.v~ilable in 48~pin or 68-pin packages,
with or without on-chip ROM/EPROM and with or
without an AID converter. A summary of the available
options is shown'in Figure 31.
The 48-pin versions are a~ailable in ceramic and plastic
48-pin Dual-In-Line package (DIP). The ceramic versions have order numbers with the prefix '~C". The
plastic versions' have the prefix "P".
The 68-pin versions are available in a ceramic pin grid
array (PGA), a plastic leaded chip carrier (PLCC) and
a Type B leadless 'chip carrier (LCC). PGA devices
, have part numbers with the prefix "0'. PLCC devices
have the prefix "N". LCC devices have the_prefix "R".
SHRINK,-DIP is offered in 64-pin packages with a
package designator of "U".

2-30

8X9X HARDWARE DESIGN INFORMATION

MOO-MD7

WRH

MD8-MD15

74LS
04
(Xl\.'l)

74LS
273

CLR
RESET

INPUT

ADDR = P3, P4

8
ADO-AD7

ADa-AD15

270246-33

Figure 29. 1/0 Port Reconstruction
Factory
Masked
ROM
68-Pln

ANALOG

64-Pln

User Programmable

CPU

EPROM
48-Pin

68-Pln

64-Pin

48-Pin

8397BH 8397BH 8395BH 8097BH 8097BH 8095BH 8797BH
8397JF 8397JF 8398 8097JF 8097JF 8098

NO ANALOG 8396BH

OTP

68-Pin 64-Pin 48-Pin

68-Pln

64-Pin 48-Pin

8795BH 8797BH 8797JF
8798
8798 8797JF 8797BH

8X9X

Figure 30. HMOS MCS®96 Packaging
o48-Pin devices have four Analog Input pins.
oFor ROM/OTP /EPROM devices, 8X9XBH and 8X98 = 8 Kbytes,
8X9XJF = 16 Kbytes
o54-Pin devices have all "48-Pin device features plus the following:
Four additional Analog Input channels
One additional Quasi-Bidirectional 8 Bit Parallel Port
Four additional Port 2 pins with multiplexed features
Timer 2 Clock Source Pin
Timer 2 Reset pin
Two additional quasi-bidirectional port pins

o68-Pin devices have all 48- and 64-pin features plus the following:
Dynamic Buswidth sizing (8 or 16 bil"bus)
Dedicated System Clock Output (CLKOUT)
INST pin for memory expansion
Non-Maskable Interrupt for debugging
oPackage Designators:
N = PLCC
C = Ceramic DIP
A = Ceramic Pin Grid Array
P = Plastic DIP .
R = Ceramic LCC
U = Shrink DIP

2-31

inter

8X9X HARDWARE DESIGN INFORMATION

10.0 USING THE EPROM
This section refers to the 879XBH,' 8798, and 879XJF
devices. These devices are generically referred to as the
879X. All information in this section refers to all three
devices unless otherwise noted.

When an 879X EPROM device is not being erased, the
window must be covered with an opaque label. This
prevents functional degradation and data loss from the
array.

10.1 Power-Up and Power-Down
879XBH and the 8798 contain 8 Kbytes of ultraviolet
Erasable and electrically Programmable Read Only
Memory (EPROM). The 879XJF contains 16 Kbytes
of EPROM. When EA is a TTL high, the EPROM is
located at memory locations 2000H through 3FFFfl on
the 879XBH and the 8798. It is at locations 2000H
through SFFFH on the 879XJF.
Applying + 12.7SV to EA when the chip is reset places
the 879X device in the EPROM Programming Mode:
The Programming Mode supports EPROM programming and verification. The following is a brief description of each of the programming modes:
The Auto Configuration Byte Programming Mode
programs the Programming Chip Configuration Byte
and the Chip Configuration Byte.
The Auto Programming Mode enables an 879X to
program itself and up to IS other .879X·s.
The Slave Programming Mode provides a standard
interface to program any number of 879X's by a master device such as an EPROM programmer or another 879X.
The Run-Time Programming Mode allows individual EPROM locations to be programmed at run-time
under complete software control. (Run-Time Programming is done with EA = 5V.)
Some I/O pins have new functions for programming.
These pins 'determine the programming function, provide programming control signals and slave ID numbers, and pass error information. Figure 32 shows how
the pins are renamed. Figure 33 describes each new pin
function. PMODE selects the function to be performed
(see Figure 31).

PMODE

Programming Mode

To avoid damaging devices during programming, follow these rules:
RULE #l-Vpp must be within IV of Vee while
Vee is below 4.SV.
RULE #2- Vpp can not be higher than S.OV until
Vee is above 4.SV.
RULE #3- Vpp must not have a low impedance path
to ground when Vee is above 4.SV.
RULE #4--EA must be brought to 12.7SV before
Vpp is brought to 12.7SV (not needed for
run-time programming).
RULE #S-The PMODE and SID pins must be in
.
their desired state before RESET rises.
RULE #6- All voltages must be within tolerance and
the oscillator stable before RESET rises.
RULE # 7- The supplies to Vee, Vpp, EA and
RESET must be well regulated and free
of glitches and spikes.
To adhere to these rules you can use the following power-up and power-down sequences:

POWER UP
RESET
Vee

Vpp

CLOCK on (if using an external clock instead of the
internal oscillator)
PALE

PROG

PORn, 4

VIH(1)

SID and PMODE valid
EA == 12.7SV(2)

0-4

Reserved

Vpp

Slave Progr~mming Mode

WAIT (wait for supplies and clock to settle)

ROM Dump Mode

7-0BH

Reserved

OCH

Auto Programming Mode

WAIT Tshll (see data sheet)

ODH

Program Configuration. Byte

BEGIN

OEH-OFH

Reserved

Figure 31. Programming Function PMODE Values

12.75V(3)

RESET = 5\1,

8X9X HARDWARE DESIGN INFORMATION

NOTES:

POWER DOWN
RESET

1. VIH = logical 'I' (2.4V minimum)

= OV

2. The same power sl!El!ly can be used for EA and
Vpp. However, the EA pin must be powered up before Vpp is powered up. Also, EA should be protected from noise to prevent damage to EA.

Vpp = 5V
EA = 5V

3. Exceeding the maximum limit on Vpp for any
amount of time could damage the device permanently. The Vpp source"must be well regulated and free
of glitches and spikes.

PALE = PROG = SID = PMODE =:PORT3, 4 =
OV
Vee = Vpp = EA = OV

10.2 Reserved Locations

CLQCKOFF

Fill all Intel Reserved locations except address 2019H,
when mapped internally or externally, with OFFH to
ensure compatibility with future devices. Fill address
2019H with 20H.

~gg:~~~~

~~~-----------,

PROGRAIIIIING
VOLTAGE
8797BH

270246-34

Figure 32. Programming Mode Pin Function

2-33

8X9)( HARDWARE DESIGN INFORMATION

Name

Function

General

Mode

PMODE
(PO-.4, .5, .6, .7)

PROGRAMMING MODE SELECT: Determines the EPROM programming
algorithm that is performed. PMODE is sampled after a chip reset and
should be static while the device is operating.

Auto
Programming
Mode

PACT
(HSO.O)

PROGRAMMING ACTIVE: Used in the Auto-Programming Mode.
Indicates when programming activity is complete.

PVAL
(Ports 3 and 4)

PROGRAM VALID: These signals indicate the success or failure of
programming in the Auto Programming Mode and when using this mode
for gang programming. For the Auto Programming Mode this signal is
asserted at Port 3.0. When using this mode for gang programming, all bits
of Port 3 and Port 4 are. asserted to indicate programming validity of the
various slaves. A zero indicates successful programming on PVAL.O. A
zero on PVAL.1 through PVAL.15 indicates a fail.
'

SALE
(P2.0)

SLAVE ALE: Output signal from an 879X in the Auto Programming Mode.
A falling edge on SALE indicates that Ports 3 and 4 contain valid address/
command information for slave 879XBHs that may be attached to the
master.

SPROG
(P2.5)

SLAVE PROGRAMMING PULSE: Output from an 879X in the Auto
Programming Mode. A falling edge on SPROG indicates that Ports 3 and 4
contain valid data for programming into slave 879XBHs that may be
attached to the master.
.

Ports 3 and 4

ADDRESS/COMMAND/DATA BUS: Used by devices in the Auto
Programming Mode to pass command, addresses and data to slaves.
Also used in the Auto Programming Mode as a regular system bus to
access .external memory. Each line should be pulled up to VCC through a
resistor. Also used as PVAL (see above).

SID
(HSI-O, .1, .2, .3)

SLAVE ID NUMBER: Used to assign a pin of Port 3 or 4 to each slave to
pass programming verification acknowledgement. For example, if gang
programming in the Slave Programming Mode, the slave with SID = 0001
will use Port 3.1 to signal correct or incorrect program verification.

PALE
(P2.1)

PROGRAMMING ALE INPUT: Accepted by an 879X that is in the Slave
Programming Mode. Indicates that Ports 3 and 4 contain a command/
address.

pROG
(P2.2)

PROGRAMMING PULSE: Accepted by 879X that is in the Slave
Programming Mode. Used to indicate th'lt Ports 3 and 4 contain the data
to be programmed. A falling edge on PROG signifies data valid and starts
the programming cycle. A rising edge on PROG will halt programming in
the slaves.

PVER
(P2.0)

PROGRAM VERIFIED: A signal output after a'programming operation by
devices in the Slave Programming Mode. This signal is on Port 2.0 and is
asserted as a logic 1 if the bytes program correctly.

PD~

PROGRAMMING DURATION OVERFLOWED: A signal output by devices
in the Slave Programming Mode. Used to signify that the PROG pulse
applied for a programming operation was I,onger than allowed.

Slave
Programming
Mode

(P2.5)

AutoPCCB
Programming
Mode.

Ports 3 and 4

ADDRESS/COMMAND/DATA BUS: Used to pass commands,
addresses and data to and from slave mode 879X's.

PVER
(P2.0)

PROGRAM VERIFIED: A signal output after programming in the Auto
Configuration Byte Programming Mode. The signal is on Port 2.0 and is
asserted as a logic 1 if the bytes program correctly.

PALE
(2.1)

PROGRAMMING ALE INPUT: Used by a device in the Auto Program
Configuration Byte Mode to indicate that Port 3 contains the data to be
programmed into the PCCB and CCB.
Figure 33. Programming Mode Pin Definitions

inter

8X9X HARDWARE DESIGN INFORMATION

they did not. Programming takes approximately
250 ms. Figure 34 shows a minimum configuration for
Auto Configuration Byte Programming.

10.3 Auto Configuration Byte
Programming Mode
The Programming Chip Configuration Byte (PCCB)is
a'non-memory mapped EPROM location. It gets loaded into the CCR during reset fo~ auto and slave programming. The Auto Configuration Byte Programming
Mode programs the PCCB.

Once the CCB and PCCB are programmed, all programming activities and bus operations use the selected
bus width, READY control, bus controls, and READ/
WRITE protection until you erase the device. You
must be careful when programming the READ and
WRITE lock bits in the CCB and PCCB. If you enable
the,READ and WRITE lock bits in'the CCB or the
PCCB and then reset the device, the array may no longer be programmed or verified (see Figure 41 in Section
"10.7.1). Therefore, you should program the buswidth,
READY control, and bus controls using the Auto Configuration Byte Programming Mode. You should program the READ and WRITE lock bits when all programming is complete.

The Chip Configuration Byte (CCB) is at location
2018H and can be programmed like any other EPROM
location using auto, slave arid run-time programming.
However, you can also use the Auto Configuration
Byte Programming to program the CCB when no other
locations need to be programmed. The CCB' is programmed with the same value as the PCCB.
The Auto Configuration Byte Programming Mode is
entered by following the power-up sequence described
in Section 10.1 with PMODE = ODH, Port 4 =
OFFH, and Port 3 = the data to be programmed into
the PCCB and CCB. When a 0 is placed on PALE, the
CCB and PCCB are automatically programmed with
the data on Port 3. After programming, PVER is driven high if the bytes programmed correctly and low if

Vee
PO'

u '

If tb,e PCCB is not programmed, the CCR will be loaded with OFFFI:I when the device is in the Programming
Mode.
Specific requirements for CCB and PCCB programming are included in the Auto, Slave, and Run-time
Programming sections.

BINARY
SWITCH

PO.S PMOOE = ODH
PO.S

POA

P2.2

vpo
r----+-IRESET
..--~~-INMI

47 p.F

ANGNO

Vss l

vREF 1--....- - - -...
SVoe
Vee

1+-'---.

Vss2 XTALl
XTAL2 Pi.l Ho-+-+----+PALE
...........;.;.;r:;.;-....;.;.;:r;;:;.._...1

~PUSH TO
fVPROGRAM

270246-39

NOTES:
1. Tie Port 3 to the value desired to be programmed into CCS, and PCCS.
2. Make all necessary minimum connections for power, ground and clock.

Figure 34. The Auto CCR Programming Mode
2-35

8X9X HARDWARE DESIGN INFORMATION

10.4 Auto Programming Mode
The Auto Programming Mode 'provides the ability to
program the 879X EPROM without using an EPROM
programmer. For this mode follow the power-up sequence described in Section lO.1 with PMODE =
OCH. When RESET rises, the 879XBH and 8798 devices automatically program themselves with the' data
found' at external locations 4000H through 5FFFH.
The 879XJF programs itself with tile data found at externallocations 4000H through 7FFF. Figure 35 shows
a minimum configuration for using an 8K x 8 EPROM
to program one 879X in the Auto Programming Mode.
The 879X reads a word from external memory, then
the Modified Quick-Pulse Programming™ Algorithm
(described later) is used to program the appropriate
EPROM location. Since the erased state of a byte is
OFFH, the Auto Programming Mode will skip locations where,the data to be programmed is OFFH. When
all 8K of the 879XBH and 8798 and all 16K of the
879XJF has been programmed, PACT goes high and
the devices outputs a 0 on Port 3.0 (PV AL) if it programmed correctly and a I if it failed.

10.4.1. AUTO PROGRAMMING MODE AND THE

eeB/peeB

In the Auto Programming Mode the CCR is loaded
with the PCCB. The PCCB must correspond to the
memory system of the programming setup, including
the READY and bus control selections. You can program the PC9B using the Auto c<;mfiguration Byte
Programming Mode (see Section lO.3).

Auto Programming must be done ill 8·bir bus mode. For 68L devices you must tie the BUSWIDTH pin to
ground. You do not need to program the/buswidth selection bit in the PCCB (PCCB.1).For '48L and 64L
devices there is no BUSWIDTH pin. You must program PCCB.I using the Auto ,Configuration Byte Programming Mode before programming the array.
The data in the PCCB takes effect upon reset. If you
enable either the READ or WRITE lock bits during
Auto Programming but do not reset the device, Auto
, Programming will continue. If you enable either the
READ or WRITE lock bits and then reset the device,
the device will no longer program or verify. You should
program these bits when, no more programming will be
done.
10.4.2 GANG PROGRAMMING WITH THE AUTO
PROGRAMMING MODE

An 879X in the Auto Programming Mode can also be
used as a programmer for up to 15 other 879XBHs that
are configured in the Slave Programming Mode.
The 879K acts as the master .. The master programs the
slaves witjl the same data the master is programming
itself with. The master outputs the necessary slave command/data pairs on Ports 3 and 4. It also provides the
Slave ALE (SALE) and Slave PROG (SPROG) signals
to demultiplex the commands from the data. Figure 36
is a block diagram of a gang programming system using
one 879XBH in the Auto Programming Mode. The
Slave Programming Mode is described in the next section.

ADDRESS 15

Intel
ADDRESS 8" '15

2764A"2

PORT.

PO'~
po.s PNODE =OCH

PO.S

po••

AlE 1--_1--1

+5V

8797BH
lOOK

...........--+--1 RESET

NOTES:
':'
'Ports 3 and 4 should have pullups to vee.
,
1. Allow RESET to rise after the voltages to Vee, EA, and Vpp are stable.

Figure 35. The Auto Programming Mode
2-36

270246-35

intJ

8X9X HARDWARE DESIGN INFORMATION

commands b~ing given to the slaves after each programming pulse.

The master 879X reads a word from the external memory controlled by ALE, RD and. WR. It then drives
Ports 3 and 4 with a Data Program command using the
appropriate address and alerts the slaves with a falling
edge on SALE. Next, the data to be programmed is
driven onto Ports 3 and 4 and slave programming begins with.a falling edge on SPROG. At the same time,
the master begins to program its own EPROM location
with the data read in. Intel's Modified 'Quick-Pulse
Programming™ Algorithm is used, with DataYerify

When programming is complete PACT goes high and
Ports 3 and 4 are driven with all Is if all devices programmed correctly. Individual bits of Port 3 and 4 will
be driven to 0 if the slave with that bit number as an
SID did not program correctly. The 879X used as the
master assigns itself an SID' of O.

r-----------.,
_1I
_________ ., I

I
I

I
I
I
i '_ ..I

HSLSID = 270246-38

Figure 38. Data Verify Command Signals

DATA VERIFY COMMAND-When the Data Verify
Command is sent, the slaves indicate correct or incorrect verification of the previous Data Program by driving one bit of Ports 3 and 4. A 1 indiclltes correct verification, while a 0 indicates incorrect verification. The
SID (Slave ID Number) of each slave determines which
bit of Ports 3 and 4 is driven. PROG from the programmer governs when the slaves drive the bus. Figure 38
shows the relationship of Ports 3 and 4 to PALE and
PROG.

giving each chip being programmed a unique SID. The
master programmer can then issue a data verify command after the data program command. When a verify
command is seen by the slaves, each will drive one pin
of Port 3 or 4 with a 1 if the programming verified
correctly or a 0 if programming failed. The SID of each
slave determines which Port 3, 4 bit it is assigned. An
879X in the Auto Programming Mode could be the
master programmer if 15 or fewer slaves need to be
programmed (see Gang Programming with the Auto
Programming Mode).

The data verify command is always preceded by a Data
Program Command in a programming system with as
many as 16 slaves. Howev~r, a Data Verify Command
does not have to follow every Data Program Command.
.

10.5.3 SLAVE PROGRAMMING MODE AND THE
CCB/PCCB

Devices in the Slave Programmng Mode use Ports 3
and 4 as the command/data path. The data bus is not
used. Therefore, you do not need to program either the
CCB or the PCCB before starting slave programming.

. WORD DUMP COMMAND-When the Word
Dump Command is issued, the 879X being programmed adds 2000H to the address field of the command and places the value found at the new address on
Ports 3 and 4. For example, when the slave receives the
command#0100H, it will place the word found at location 2100H on Ports 3 and 4. PROG from the programmer governs when the slave drives the bus. The
signals are the same as shown in Figure 22.

You can program the CCB during slave mode programming like any other location. Data programmed
into the CCB takes effect upon reset. If you enable either the READ or WRITE lock bits in the CCB and do
not reset the device, slave programming will continue.
If you enable either the READ or WRITE lock bitsand do reset the device, the device will no longer program or verify. You should program the READ and
WRITE lock bits using slave programming when the
array is fully programmed and verified.

Note that this command only works when a single slave
is attached to the bus, and that there is no restriction on
commands that precede or follow it Word Dump Command.

10.6 Run-Time Programming
10.5.2 GANG PROGRAMMING WITH THE
SLAVE PROGRAMMING MODE

Using Run-Time programming, the 879X can program
itself under software control. One byte or word can be
programmed instead of the whole array. The only additional requirements are that you apply a programming
voltage to Vpp and have the ambient temperature at
25°C. Run-time programming is done with EAat a
TTL high (internal memory enabled).

Gang programming of 879Xs can be done using the
Slave Programming Mode. There is no.879X based limit on the number of chips that may be hooked to the
same Port 31P0rt 4 data path for gang programming.
If more than 16 chips are being gang programmed, the
PVER and PDO outputs of each chip can be used for
verification. The master programmer can ·issue a' data
program command and then either watch every chip's
. error signals, or AND all the signals together to get a
system PVER and PDO.

If 16 or fewer 879Xs are to be gang programmed at
once, a more flexible form of verification is available by
2-39

To run-time program the user writes a byte or word to.
the location to be programmed. The 879X will continually program that location until another data read or
data write to the EPROM occurs. The user must control the duration of the programming pulse by implementing the Modified Quick-Pulse Programming Algorithm (see Section 10.8) in software.

intJ

8X9X HARDWARE DESIGN INFORMATION

Figure 39 is an example of code for programming an
EPROM location while the device is executing internally. Upon entering the PROGRAM routine, the device
retrieves the address and data from the STACK. A
software 'timer is set to expire after one programming
pulse. The 879X starts programming a location by writing to it. The device then goes into a "Jump to SelF'
loop while the location is programmed. ("Jump to SelF'
is a two byte instruction which can be CALVed from
address 20IAH.) When the software timer interrupt occurs, the device escapes from the "Jump to SelF' loop,
ending the programming pulse. The minimum interrupt
service routine would remove the 20lAH return address from the STACK and' return.

EPROM. If the program is executing from external
memory no, program fetches or pre-fetches ,will occur
from internal memory.

. Once you start programming a location, you should not
perform any program fetches or pre-fetches from the
EPROM. The fetches will be done but programming
will stop. Using the "Jump to SelF' prevents this from
, . \ happening because addtess 20lAH is n~t part of the

The CCB can ~lso be programmed during Run-Time
Programming like any other EPROM iocation.

10.6.1 RUN-TIME PROGRAMMING AND THE
CCB/PCCB

For run-time programming, the CCR is loaded with the
CCB. Run-time programming is done with EA equal to
a TTL-high (internal execution) so the internal CCB
must correspond to the memory system of the application setup. You can use Auto Configuration Byte Programming or a generic programmer, to program the
CCB before using run-.time programming.

PROGRAM:
POP

temp

;take parameters from the
STACK

POP address_temp
POP data_temp
PUSH temp
PUSHF
LDB int_mask, #enable_swt_only
LDB HSO_COMMAND, #SWTO_ovf
ADD HSO_TIME,TIMER1, #program_pulse

;save ourrent status
;enable only swt interrups
;load swt oommand to interrupt
;when program pulse time
:has elapsed

EI
ST

:start programming

data-temp, [address_temp)

:nJump to Self" until
:the program pulse time
:has expired

CALL 201AH

POPF
RET

EiwtO_expired:
POP 0
RET
Figure 39. Programming the EP,ROM from Internal Memory Execu~lon

2-40

inter

8X9X HARDWARE DESIGN INFORMATION

Dllta programmed into the CCB hikes effect upon reset.

on the 879XBH and the 8798 and locations 2000HSFFFH on the 879XJF) from inadvertant or unauthorized programming. It also prevents writes to the
EPROM from upsetting program execution. If write
protection is not enabled, a data write to an internal
EPROM location will begin programming that location, and continue programming the location until a
data access of the internal EPROM is executed. While
programming, instruction fetches from internal
EPROM will not be successful and programming will
stop.

If the WRITE lock bit of the CCB is enabled the array

can no longer be programmed. You should only prognim the WRITE lock bit when no further programming will be done to the array. If the READ lock bit is
enabled the array can still be programmed using runtime programming 1>ut data accesses will only be performed when the program co.unter is between 2000H
and 3FFFH on the 879XBH and the 8798 and between
2000H and SFFFH on the 879XJF.

10.7 ROM/EPROM Program Lock

READ protection is selected by causing the LOCI bit
in the CCR to take the value O. When READ protection is enabled, the bus controller will only perform a
data read from the address range 2020H-3FFFH ifthe
slave program counter is' in the range 2000H-3FFFH
on the 879XBH and the 8798. The bus controller will
only perform a data read from the address range
2020H-SFFFH if the slave program counter is in the
range 2000H-SFFAH on 879XJF. Note that since the
slave PC can be many bytes ahead of the CPU program
counter, an instruction that is located after address
3FFAH may not be allowed to access protected memory, even though the instruction is itself protected.

Protection mechanisms have been provided on the
ROM and EPROM versions of the 8X9X to inhibit
unauthorized accesses of internal program memory.
However, there must always be ,a way to allow authorized program memory dumps for testing purposes.
The following describes 8X9X lock features and the
mode provided for authorized memory dumps.
10.7.1 LOCK FEATURES

Write protection is provided for EPROM devices while
READ protection is provided for both ROM and
EPROM devices.
'

If the bus controller receives a request to perform a
READ of protected memory, the READ sequence occurs with indeterminant data being returned to the
CPU.

Write protection is enabled by causing the LOCO bit in
the CCR to take the value O. When WRITE protection
is selected, the bus controller will cycle through the
write sequence, but will not actually drive data to the
EPROM and will not enable Vpp to the EPROM. This
protects the enti,re EPROM (locations 2000H-3FFFH

Figure 41. shows the effects of enabling the READ and
WRITE lock bits.

CCB.1

CCB.O

PCCB.1

PCCB.O

Lock

Array is unprotected. ROM Dump Mode and all programming modes
are allowed.

Array is read protected. ,Run7time programming and ROM Dump Mode
(with security key verification) are allow,ed. Auto, slave, and auto pees
programming are not allowed.

Same as above.

Array is write protected. ROM dump mode (with security key
verification) is allowed. Auto, slave, auto pees, and run-time
programming are not allowed.,

Protection

Same as above.

Array is read and write protected. ROM dump mode (with security key
verification) is allowed. Auto, slave, auto pees, and run-time
programming are not allowed.

Same as above.
Figure 41

2-41

8X9X HARDWARE DESIGN IN'FORMATION

Other enhancements were also made. to the 8X9X for
program protection. For example, the value of EA :is
latched on reset so that the device cannot be switched
from external to internal execution mode .at run-time.
In addition, if READ protection is selected, an NMI
event will cause the device to switch to 'external ol)ly
execution mode. Internal execution can only resume by
resCltting the chip.

Table 2. 8X9XBH Signature Words
. Device
879XBH
839XBH
809XBH
879XJF
839XJF
809XJF

Signature Word
896FH
896EH
Undefined
896BH
896AH
Undefined

10.7.2 ROM DUMP MODE

You can use the security key and ROM dump mode to
. dump the internal ROM/EPROM for testing purposes.
The security key is a 16-byte number. The internal
ROM/EPROM must contain the security key at locations 2020H-202FH. The user must place the same
secljrity key at external atldress 4020H -402FH. Before
doing ROM dump, the device checks that the keys
match.
The ROM dump mode is entered by following the
power-up sequence described in Section. 10.1 with
PMODE = 06H. The device first verifies the security
keys. If the security keys do not match, the device puts
itself into an endless loop of internal execution. If the
keys match, the device dumps data to external locations
4OOOH-5FFFH and 9000H-91FFH on the 879XBH
and the 8798 and to exte~nallocations 4000H - 7FFFH
and 9OO0H-937FH on the 879XJF. The data starting
at location 9000H will be indeterminate. The data starting at location 4oo0H will contain the internal
ROM/EPROM, beginning with internal address
2oooH.

10.10 Erasing the EPROM
Initially, and alter each erasure, all bits of the 879X are
in the "1" statel Data is introduced by selectively programming "Os" into the desired bit locations. Although .
only "Os': will be programmed, both "Is" and "Os" can
be present in the data w9rd. The only way to change a
"0" to a "1" is by ultraviolet light erasure.
Erasing begins UpOI) exposure to light with wavelepgths
shorter than approximately 4000 Angstroms (A). It
should be noted that sunlight and certain types of flu~
rescent lamps have wavelengths in the 3000-4000 A
range. Constant exposure to room level fluorescent
lighting could erase the typical 879X in approximately
3 years, while it would take approximately 1 week to
cause erasure when exposed to direct sunlight. If the
879X is to be exposed to light for extended periods of
time, opaque labels must be placed over the EPROM's
window to prevent unintentional erasure.

The Modified Quick-Pulse Programming Algorithm
calls for each EPROM location to receive 25 separate
100 /Jos (±5 /Jos) program cycles. Verification of correct
programming is done after the 25 pulses. If the location
verifies correctly, the next location is programmed. If
the location fails to verify, the location has failed.

The recommended erasure procedure for the 879X is
exposure to shortwave ultraviolet light which has a
wavelength of 2537A. The integrated dose (i.e., UV intensity X exposure time) for erasure should be a minimum of 15 Wsec/cm 2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 /JoW/cm2 power rating. The
879X should be placed within 1 inch of the lamp tubes
during erasure. The maximum integrated dose an 879X
can be exposed to without damage is 7258 Wsec/cm2 (1
week @ 12000 /JoW/cm2). Exposure of.the 879X to high
intensity UV light for long periOds may cause permanent damage.

Once all locations are programmed and verified, the
entire EPROM is again verified.

11.0 QUICK REFERENCE

Programming of 879X devices is done with Vpp 12.75V ±0.25V and Vee = 5.0V ±0.5V.

11.1 Pin Description

10.9 Signature Word

On the 48-pin devices the following pins are not bonded
out: Portl, PortO (Analog In) bits 0-3, T2CLK (P2.3),
T2RST (P2.4), P2.6, P2.7, CLKOUT, INST, NMI,
BUSWIDTH. S-DIP packages do not have INST,
CLKOUT, BUSWIDTH or NMI.

10.8 Modified Quick-Pulse
Programming™Algorithm

The' 8X9X contains a signature word at location
2070H. The word can be accessed in the slave mode by
. executing a word dump command (see Table 2).

2-42

inter

8X9X HARDWARE DESIGN INFORMATION

PIN DESCRIPTIONS
Symbol
Vee

Name and Function
Main supply voltage (SV).

Vss

Digital circuit ground (OV). Two pins.

VPD

RAM standby supply voltage (5V). This voltage must be present during normal operation. In
a Power Down condition (i.e. Vee drops to zero), if RESET is activated before Vee drops
below spec and VPD continues to be held within spec., the top 16 bytes in the Register File
will retain their contents. RESET must be held low during the Power Down and should not
be brought high until Vee is within spec and the oscillator has stabilized. See Section 2.3.

VREF

Reference vOltage for the AID converter (5V). VREF is also·the supply voltage to the analog
portion of the AID converter and the logic used to read Port O. See Section 8.

ANGND

Reference ground for the AID converter. Should be held at nominally the same potential as
Vss. See Section 8.

Vpp

Programming voltage for the EPROM devices. It should be +12.75V when programming
and will float to SV otherwise. The pin should not be above Vee on ROM or GPU devices..
This pin must flo"at in the application circuit on EPROM devices.

XTAL1

Input of the oscillator inverter and of the internal clock generator. See Section 1.S.

XT~L2

Output of the.oscillator inverter. See Section 1.5.

GLKOUT

Output of the internal clock generator. The frequency bf GLKOUT is
frequency. It has a.33% duty cycle. See Section 1.S

RESET

Reset input to the chip. Input low for at least 10XTAL1 cycles to reset the chip. The
subsequent low-te-high transition re-synchronizes GLKOUT and commences a 10-statetime sequence in which the PSW is cleared, a byte read from 2018H loads GGR, and a jump
to location 2080H is executed. Input high for normal operation. RESET has an internal
pullup. See Section 13. '.

BUSWIDTH

Input for buswidth selection. If GGR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an
8-bit cycle occurs. If GGR bit 1 is a 0, the bus is always an 8-bit bus. If this pin is left
unconnected, itwillrise to Vee. See Sectron 2.7.

NMI

A positive transition causes a vector to external memory location OOOOH. External memory
from OOH through OFFH is re$9rved for Intel development systems.

INST

Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle.

% the oscillator

Input for memory select (External Access). EA equal to a TTL-high caus~s memory
_
~ccesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA
~al
EA =

to a TTL-low causes accesses to these locations to be directed ,to off-chip memory.
+ 12.SV causes execution to begin in the Programming mode on EPROM devices.
EA has an internal pulldown, so it goes to 0 unless driven otherwise.

ALE/ADV

Address Latch Enable or Address Valid output, as selected by GGA. Both pin options __
provide a latch to demultiplex the address from the address/data bus. When the pin is ADV,
it goes inactive high at the end of the bus cycle. ADV can be used as a chip select for
external memory. ALE/ ADV is activated only during external memory accesses. See
Section 2.7.

Read signal output to external memory. RD is activated only during external memory reads.

2-43

8X9XHARDWARE DESIGN INFORMATION

PIN DESCRIPTIONS (Continued)
~

Symbol
WR/WRI

SHE/WRH

Name and Function
Write and Write Low output to external memory, as selected by the CCA. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL i~ activated only during external memory writes. See Section 2.7.
Sus High Enable or Write High output to external memory, as selected by the CCR.

o selects the bank of memory that is connected to the high byte of the data bus. AO

aRE =

!= 0
selects the bank of memory that is connected to the low byte of the data bus. Thus
accesses to a 16-bit wide memory can be to the low byte only (AO = 0, SHE = 1), to the
high byte only (AO = 1, 'SHE # = 0), or both bytes (AO = 0, SHE = 0). If the WRH function
is selected, the pin will go low if the bus cycle is writing to an odd memory location. See
Section 2.7.

READY

Ready input to lengthen external memory cycles, for interfacing to slow ,or dynamic memory,
or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin
is low prior to the falling edge of CLKOUT, the Memory Controller goes into a wait mode
until the next positive transition in CLKOUT occurs with READY high. The bus cycle can be
lengthened by up to 1 ,""S. When the external memory is not. being used, READY has no
effect. Internal control of the number of wait states inserted into a bus cycle held not ready
is available through configuration of CCR. READY has a weak internal pullup, so it goes to 1
unless externally pulled low. See Section 2.7.

HSI

Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1 , HSI.2, and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are also used as
ihputs by EPROM devices in Programming mode. See Section 6.

HSO

Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
See Section 7.

Port 0

8-bit high impedance input-only port. These pins car be used as digital inputs and/or as
analog inputs to the on-chip AID converter: These pins are also a mqde input to EPROM
devices in the Programming mode. See Section 10.

Port 1

8-bit quasi-bidirectional 110 port. See Section 10.

Port 2

8-bit mUlti-functional port. Six of its pins are shared with other functions in the 8X9X, the
remaining 2 are quasi-bidirectional. These pins are also used to input and output control
signals on EPROM devices in Programming Mode. See Section 10.

Ports 3 and 4

8-bit bidirectional I/O ports with open drain outputs" These pins are shared with the
multiplexed address/ data bus which has strong internal pullups. Ports 3 and 4 are also u~ed
as a command, address and data path by EPROM devices operating in the programming
.
mode. See Sections 2.7 and 1 0 . '

2-44

inter

8X9X HARDWARE DESIGN INFORMATION

11.2 Pin List

Name

The following is !l list of pins in alphabetical order.
Where a pin has two names it has been listed under
both names, except for the system bus pins, ADOADlS, which are listed under Port 3 and Port 4.
Name
ACHO/PO.O
ACH1/PO.1
ACH2/PO.2
ACH3/PO.3
ACH4/PO.4/MOD.0
ACH5/PO.5/MOD.1
ACH6/PO.6/MOD.2
Ad, 7 IPO.7 IMOD.3
ALE/ADV
ANGND
SHE/WRH
SUSWIDTH
CLKOUT
EA I
EXTINTIP2.2/PROG
HSI.O
HSL1
HSI.2/HSO.4
HSI.3/HSO.5
HSO.O
HSO.1
HSO.2
HSO.3
HSO.4/HSI.2
HSO.5/HSI.3
INST
NMI
PWM/P2.5/PDO
PALE/P2.1/RXD
PROG/P2.2/EXTNT
PVER/P2.0/TXD
PO.O/ACHO
PO.1/ACH1
PO.2/ACH2
PO.3/ACH3
PO.41 ACH4/MOD.0
PO.51 ACH5/MOD.1
PO.61 ACH6/MOD.2
PO.7 I ACH7 IMOD.3
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5

P1.6
31
P1.7
3,2
P2.0/TXD/PVER
18
P2.1/RXD/PALE
17
P2.2/EXTINT
15
P2.3/T2CLK
44
P2.4/T2RST
42
P2.5/PWM/PDO
39
P2.6
33
P2.7
38
P3.0/ADO PVAL
60
P3.1/AD1 PVAL
59
P3.21 AD2 PVAL
58
P3.3/AD3 PVAL
57
P3.4/AD4 PVAL
56
P3.51 AD5 PVAL
55
P3.61 AD6 PVAL
54
P3.7/AD7 PVAL
53
P4.0/AD8 PVAL
52
P4.1/AD9 PVAL
51
P4.2/AD10 PVAL
50
P4.31 AD11 PVAL
49
P4.4/AD12 PVAL
48
P4.5/AD13 PVAL
47
P4.6/AD14 PVAL
·46
P4.7/AD15 PVAL
45
RD
61
READY
43
RESET
16
RXD/P2.1
17
SALE/PVER/P2.0
18
SPROG/POO/P2.5
39
TXD/P2.0/SALE
18
T2CLK/P2.3
44
T2RST/P2.4
42
Vpp
37
1
Vee
14
VPD
13
VREF
68
Vss
36
Vss
WR/WRL
40
WRH/SHE
41
XTAL1
67
XTAL2
66

68-PIn 68-PIn 48-Pi n 64-Pin
PLCC PGA DIP SDIP
6
5
7
4
11
10
8
9
62
12
41
64
65
2
15
24
25
26
27
28
29
34
35
26
27
63
3
39
17
15
18
6
5
7
4
11
10
8
9
19
20
21
22
23
30

4
5
3
6
67
68
2
1
16
66
37
14
13
8
63
54
53
52
5'1
50
49
44
43
52
51
15
7
39
61
63
60
4
5
3
6
67
68
2
1
59
58
57
56
55
48

43
42
40
41
34
44
15

4
3
5
2
9
8
6
7
60
10
39

39
47
3
4
5
6
7
8
9
10
5
6

1
13
22
23
24
25
26
27
32
33
24
25

13
1
47
2

37
15
13
16
4
3
5
2
9
8
6
7
17
18
19
20
21
28

43
42
40
41

68-Pln 68-Pln 48-Pln 64-Pln
PLCC PGA
DIP SDIP
47
46
60
61
63
34
36
39
45
40
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
17
35
62
61
60
39
60
34
36
41
9
64
65
10
42
38
37
11
12

2
1
47

13
-

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
33
16
48
1
2
13
2

12
38
46
45
11
37
14
15
36
35

29
30
16
15
13
42
40
37
31
36
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
59
41
14
15
16
37
16
42
40
35
64
12
11
34
63
38
39
62
61

The following pins are not bonded out in the 48-pin
package:
PI.O through Pl.7, PO.O through PO.3, P2.3, P2.4, P2.6,
P2.7 CLKOUT, INST, NMI, TEST, T2CLK (P2.:3),
T2RST (P2.4).
2-45

8X9X HARDWARE DESIGN INFORMATION

1'1.3 Packaging
The.MCS-96 products are available in 48-pin, 64-pin and 68-pin packages, with and without AID, and with and
without on-chip ROM or EPROM. The MCS-96 numbering system shown below this section shows the pinouts for
the 48- and 68-pin packages. The 48-pin version is offered in a Dual-In-Line package while the 68-pin versions come
in a Plastic Leaded Chip Carrier (PLCC), a Pin Grid Array (PGA) or a Type uB" Leadless Chip Carrier.
The MCS®·96 Family Nomenclature
User Programmable

Factory
Masked
ROM

CPU

68·Pin 64·Pin 48·Pin 68-Pln
ANALOG

64~Pln

48·Pin 68-Pin 64-Pin 48-Pi.n 68-Pin 64-Pin 48-Pin

8397BH 8397BH 8395BH 8097BH 8097BH 8095BH 8797BH
8397JF 8397JF 8398 8097JF 8097JF 8098

NO ANALOG 8396BH

8795BH 8797BH 8797JF
8798
8798 8797JF 8797BH

8X9X

MTBF Calculations·

Transistor Count
Device Type

OTP

EPROM

#MOSGates

8X9XBH

3.8 x 107 Device Hours

SS·C

70·C

55°C

839XBH/879XBH

120,000

8X9XBH

1.7 x 107 Device Hours

809XBH

50,000

8X9XJF

S.2 X 106 Device Hours

839XJF/879XJF

203,00

809XJF

72,000

• MTBF data was obtaIned thrOugh calculatIons based upon the actual average junction temperatures under stress at 55"C and 70"C
ambient.

. Thermal Characteristics (same for 8X9XBH, 8X9XJF and 8X98)
Package Type

8Ja

8Jc

PGA

35°C/W

10°C/W

PLCC

37"C/W

13°C/W

LCC

28°C/W

Plastic DIP

38°C/W

19°C/W

Ceramic DIP

26°C/W

6.5°C/W

2-46

8X9X HARDWARE DESIGN INFORMATION

11.4 Package Diagrams
":
RXO/P2.1

RESET

TXO/P2.0

EXTINT/P2.2
VpD

HSII

VREr

HSI2/HS04

ci ci ci ci ci

~~~~~~
~

HSIO

'"~

'" '"

::i ~

~ ~ ~
1;:1 > > x

~ ~

III

1&1

ANGNO

HSI3/HS05

ACH4/PO.4

ACH5Il'O.5

ADO/P3.0

HSOO

ACH5/PO.5

ACH4/PO.4

AD1/P3.1

HSOI

ACH7/PO.7

ANGND

AD2/P3.:!

HS02

ACH6/PD.$

VREr

HS03

VPO

Vee

Vpp
PWM/P2.5

Vss
XTALI

WRL;WR

XTAL2

RffiT

ALE/ADV

READY

ADI5/P4.7

ADO/P3.0

ADI4/P4.6

AD1/P3.1

ADI3/P4.5

AD2/P3.2

ADI2/P4.4

AD3/P3.3

ADI1/P4.3

RXD/P2.1

TXD/P2.0

AD4/P3.4

MCS-96
68 PIN
PLCC

EXTINT/~2.2

Vss

WRH/SHE

AD3/P3.3
14

AD5/P3.5
AD6/P3.6
AD7/P3.7
AD8/P4.0

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD

P1.0
~1.1

AD9/P4.1
AD10/P4.2

P1.2

ADI1/P4.3

P1.3

ADI2/P4.4

P1.4

ADI3/P4.5

AD4/P3.4

HSIO

ADI4/P4.6

AD10/P4.2

AD5/P3.5

HSII

AD9/P4.1

AD6/P3.6

HSI2/HS04

AD8/P4.0

AD7/P3.7

ADI5/P4.7
T2CLK/P2.3

270246-45

48-Pin Package
270246-46

Pins Facing Down
7

18 19 16 14 12 10 8

17 15 13 11

S8-Pin Package (PLCC - Top View)
1

2 68
6766

2021
MCS-96
68 PIN
GRID ARRAY

9 1011 121314151617

6564

6362

67.

61 60

5958

5756

5554

34 36 38 40 42 44 46 48 50 53 52

35 37 39 41 43 45 47 49 51

2223
2425
2627
2829
3031
3233

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
or PC BOARD

270246-47

MCS-96
68 PIN
LEADLESS CHIP CARRIER
TYPE "S"
(EPROM ONLY)

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD

S8-Pin Package
(Pin Grid Array - Top View)

22
23
24
25
26
27
28

M
51 50 49 48 47 46 45 4443 42 41 40 39 38 37 36 35

270246-48

S8-Pin Package (LCC - Top View)

2-47

inter

8X9X HARDWARE DESIGN INFORMATION

270246-65

Shrink-DIP Package

2-48

intJ

8X9X HARDWARE DESIGN INFORMATION

) 11.5 Memory Map
OFFH ....- - - - - - - - - - - - - , 25 5
POWER-DOWN
OFOH
OEFH

lAH

19H

RAM

1-----------,
INTERNAL
REGISTER FILE
(RAM)

L..._ _ _ _ _ _ _ _ _ _ _.....
STACK POINTER

STACK POINTER

18H

2 40

39
FFFFH

PWM_CONTROL

16H

10Sl

10Cl

15H

10SO

lOCO

RESERVED

6 OooH
EXTERNAL MEMORY OR I/O
(8X9XBH. 8X98)

SP_STAT

SP_CON

INTERNAL PROGRAM STORAGE
ROM/EPROM OR EXTERNAL
MEMORY OR I/O (8X9XJF)

14H

12H
llH

17H

13H

EXTERNAL MEMORY
OR I/o

10H

10 PORT 2

10 PORT 1

OEH

10 PORT· 0

B"'UD_RATE

ODH

TlMER2 (HI)

OCH

TlMER2 (LO)

OBH

TIMERl (HI)

OAH

TIMERl (LO)

WATCHDOG

09H

INLPENDING

OSH

INT_MASK

INLMASK

07 H

SBUF (RX)

SBUF (TX)

06 H

HSLSTATUS

HSO_COMMAND

HSLTIME (HI)

HSO_TIME (HI)

04 H

HSLTIME (LO)

HSO_TIME (LO)

03 H

AD_RESULT (HI)

HSLMODE

02 H

AD_RESULT (LO)

AD_COMMAND

01 H

RO (HI)

00 H

RO (LO)

RESERVED

2030H-207FH

SECURITY KEY

2020H- 202FH

RESERVED

201CH- 201FH

SELF JUMP OPCOPE (27H FEH)

201AH- 2018H

RESERVED
CHIP CONFIGURATION BYTE

05 H

(WHEN READ)

2080H

13
RESERVED

4OOOH
3FFFH

INTERNAL PROGRAM
STORAGE ROM/EPROM
OR
EXTERNAL MEMORY

OFH

5 FFFH

RESERVED

2019H
2018H
2012H-2017H

INTERRUPT VECTORS
2000H

PORT 4

lFFFH

PORT 3

lFFEH

EXTERNAL MEMORY OR I/O (8X9XBH. 8X98)
XRAM (8X9XJF)

0100H

INTERNAL RAM
REGISTER FILE
STACK POINTER
SPECIAL FUNCTION REGISTERS
(WHEN ACCESSED AS DATA MEMORY)

OOFFH

OOOOH

(WHEN WRITTEN)

270246-49

2-49

inter

8X9X HA~DWARE DESIGN IfI.IFORMATION

11.6 Instruction Summary
Mnemonic
AOO/ADDB
ADD/AODB
ADDC/ADbcB
SUB/SUBS
SUB/SUBB
SUBC/SUBCB
CMP/CMPB
MULIMULU
MULIMULU
MULB/MULUB
MULB/MULUB
DIVU
DIVUB
DIV
DIVB
AND/ANDB
AND/ANDB
OR/ORB
XOR/XORB
LD/LDB
ST/STB
LDBSE
LDBZE
PUSH
POP
PUSHF

Operands

Operation (Note 1)

0 - D+A

D,- B + A·
D-D+A+C

2
2

3
2
2
2

3
2

3
2
2
2
2
2

3
2
2
2
2
2
2
1
1
0

POPF
SJMP
WMP
BR [indirect)
SCALL

0
1
1
1
1

LCALL
RET
J (conditional)
JC
JNC
JE

...
...
...!
...
...t

D -

D-A
0 - B-A
0 - D-A+C-1
D-A
D, D + 2 +-'- D ° A .
D, D + 2 BOA'
D,D + 1 ~ bOA
D, D + 1 BOA
(0, D + 2)/ A,
D (D, D + 1)/A,
D D (D,.D + 2)/ A,
(D, D + 1)/A,
D .-

D+
D. +
D+
D+

2
1
2
1

remainder
remainder
remainder
remainder

DandA
D D BandA
DorA
D D D (excl. or) A
O-A
A-O
O-A;D+1 SIGN(A)
O-A;D+1-0
SP SP - 2; (SP) A
(SP); SP SP + 2
A SP SP - 2; (SP) PSW;
PSW OOOOH
PSW (SP);SP SP + 2;
,
PC +- PC + 11·bit offset
PC -

PC + t6·bit offset

PC SP PC -

(A)
SP - 2; (SP) PC;
PC + 11-bit offset

SP PC -

SP - 2; (SP) PC;
PC + 16-bit offset

0
1
1

PC (SP);SP SP + 2
PC PC + ~·bit offset (if taken)
JumpifC = l'

1
1

JumpifC
JumpifZ

=0
=1

...
...
...
...
...
...
...

....

....
...
...
...
...
...

- - - - - - - - - - - - - - - ...

......
...
...

,1-0
1 - ...

Flags
C V

-- ...

- -

...
...
...
...

0
0
0

?
?

0
0
0
0

t
t
t
t
t
t
t

t
t
t
t

- - -

?
?
?
?

2
2

... ... ...

...

- - - - - - - - - - - - - - - - - - - - - - - - - - .......
- - - - - - - - - - - - -

3
3

- - - - - - - - - -

Notes

3,4
3,4

;

5
5
5
5

, NOTES;
1. If the mnemonic ends in "B", a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment ~es for the required operand type. D and B are locations in the Register, File; A can be
located anywhere in memory.
.
'
_
2. 0, D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D, D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to a word.
5. Offset is a 2's complement number.

2-50

8X9X HARDWARE DESIGN INFORMATION

Operands

Mnemonic
JNE
JGE
JlT
JGT
JLE
JH
JNH
JV
JNV
JVT
JNVT
JST
JNST
JBS
JBC
OJNZ
OEC/OECB
NE-G/NEGB
INC/INCB
EXT
EXTB
NOT/NOTB
CLR/CLRB
SHL/SHLB/SHLL
SHR/SHRB/SHRL,
SHRAISHRAB/SHRAL
SETC
CLRC
CLRVT,
RST
01
EI
NOP
SKIP
NORML
TRAP

Operation (Note 1)

1
1
1
1
1
1
1
1
1
1
1
1
1

JumpifZ = 0
Jump if N = 0
JumpifN = 1
Jump if N = OandZ = 0
Jump If N = 1 or Z = 1
JumpifC = 1 andZ = 0
JumpifC = OorZ = 1
Jump if V = 1
Jump if V = 0
Jump if VT = 1; Clear VT
Jump if VT = 0; Clear VT
JumpifST = 1
JumpifST = 0

Jun:tP'if Specified Bit = 1
Jump if Specified Bit = 0
0 - 0 --1;ifO*Othen
PC PC + 8-bit offset
0-0-1
0-0-0

3
1

1
1
1,
1
1
1

1
2
2
2
0

9
0
0
0
0
0
0
2
0

Flags
C V

- - ..... - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 - - - - 0 - - - - - '- - - - - '- - - - - - - - - "

- - - ..... ~

t
t
t

0 - 0+ 1
0 - p;O + 2 Sign (0)
0 - 0;0 -Ir 1 Sig'n(O)
o ,- Logical Not (0)
0-0

0
0
0
0

---

C -

?
?

0
0

msb-----Isb 0
0 ' - msb-----Isb - C
msb msb--""':-":"'Isb ""'"+ C
C-1
C-O
VT 0
~ 2080H
disable All Interrupts (I Enable All Interrupts (I PC-PC+1
PC-PC+2
Le~ shift till msb

SP PC -

= 1; 0

SP - 2; (SP) (2010H)

0)
1)

Note.
ST

shift count
PC

~
~

- - - - - - - - ?
0 - - - - -

- - - - ~

- - 1 - - - -' 0 - - - - - - 0
~

5
5
5
5
5
5
5
5
5
5
5
5
5
5,6
5,6

7
7
7

7
9,

NOTES:
,
1. If the mnemonic' ends in "8", a, byte operation is performed, 'otherwise a word operation is done. Operands 0, ,9 and A
must conform to the alignment rules for the required operand type. 0 and 8 are locations in the Register File; A, can be
located anywhere In memory.
5. Offset is a 2's complement number.
6. Specified bit is one of the 2048 bits in the register file.'
7. The "L" (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with 'code starting at
2080H.
9. The assembler will not accept this mnemonic.

2-51

, '

8X9X HARDWARE DESIGN INFORMATION

'I'

, 11.7 Opcode ,and State Time Listing
DIRECT

INDEXED~

INDIRECT@
NORMAL
AUTO-fNC.

IMMEDIATE

SHORT

LONG

I
.::,~. ",

III

ADD
,
ADD
i\DDB
ADDB
ADOO
ADDeB
SUB,

2
3
2
3
2
2
2

SUB
SUBB
SUBB
SUBC
SUBCB
CMP
CMPB

" .,;"\','

MULU
MULU
MULUB
MULUB
MUL
MUL
MULB
MUJ.B
D1VU'
D1VUB
DIV
DIVB

2
3
2
2
2
2

III

3
44 4
74 3
54 4
..\4 3
B4 3
68 3
48, 4
,78 3
58 4
A8 3
:B~ 3
88 3
98 3'
64

2 6C
3 4C
2 7C
3 5C
2 ~
3 ~
2 ~
3
~
2 '8C
2 9C
2 ~

3
4
3
4
4
5
4
5
3
3
4
4

III
Q

III

~I g5
4
5
4
5
4
4
4
5
4
5
4'
4
4
4

~fa
... lI
U)):

~ ~

III

aU)

I!: III

III

aU)

~):

ARITHMETIC INSTRUcnONS
65 4
5
66 3 6111
~ ,7112
45 5
6
46 4
71\2 4 Sit 3
75 3
4
76 3 6111
3 71\2
55 4
56 4 71\2 4 8113
5
AS 4
Ai> 3 6111
3 71\2
5
B5 3
4
B6 3 6111
3 71\2
69
5
6A 3 6111
3 7112
49 '5
6
4A 4 7112 4 8/13
79 j
4
7A 3 '6111
3 7/12
59 4
5
SA 4 7/12 4 81\3
A9 4
5 AA 3 6111 3 7/12
4
B9 3
BA 3 6111
3 1112.
89 4
5
8A 3 6111
3 7112
99 3
4
9A 3 6111 '3 '\7112

25
26
17
18
29
30
21
22
25
17
29

60
40
70
SO

, 21

~
~
~
~

80
90
~

4
5
3
4
5
6
4
5
4
3
5
4

26
27
i7
18
30
31
21
. 22
26
17
30

6E
4E
7E
5E

~
~

8E
9E
~

3
4
3
4
4
5
4
5

3
3
4
4

27132
28/33
19/24
20/25
31/36
32137
23/28
24/29
28/32
'20/24
32/36
24/28

3
4
3
4
4
5
4
5
3
3
4
4

28/33
29/34
20;25
21126
32/37
33/38
24/29
25/30
29/33
21i25
33/37
25/29

111
Q

67
47
77

57
A7
'B7
6B
4B
7B
5B
AB
BB
8B
9B
6F
4F
7F
SF
~
~

~
~

8F
9F
~
~

a@
~; fa ~;
_5 ~): 5 ~I=
U)

!ell

4
5
4
5
4
4
4
5
4
5

6111

5
6
6111 ' 5
7/12 6
6111 5
6111 ' 5
6111 5
71\2 6
6111 5
71\2 6
4 6111 5
4: 6111
5
4 6111
5
4 6/11
5

7112
81\3
7/12
81\3
7/12
71\2
7112
81\3
71\2
81\3
7/12
71\2
7112
7112

4
5
4
5
5
6
5
6
4
4
5
5

27132
28/33
19/24
20125
31136
32137
23/28
24/29
28/32
20124
32136
24/28

28/33
29/34
20/25
21126
32137
33/38
24/29
25/30
29/33
21/25
33/37
25/29

71\2

5
6
5
6
6
7
6
7
5
5
6
6

270246-63

NOTES:

·Long indexed and ,Indirect + instructions have identical opcodes with Short indexed and Indirect modes, respectively. The
second byte of instructions using any Incjirect or indexed addressing mode )lpecifies the exact mode used. If the second
byte is even, use Indirect or Short indexed. If it is odd, use Indirect + or Long indexed. In all cases the second byte of the
instruction always specifies an even (word) location for the 'address referenced.
(l) Nilimber of state times shown 'for internal/external operands.
,
@ The 'opcodes for signed multiply and divide are the opcodes for the unsigned functions with an "FE" appended as a
prefix,
@ State times shown for 16-bit bus.

inter

8X9X HARDWARE DESIGN INFORMATION .

·z

M
z
:I

.~
II:
III

~~
0

AND
AND
AN DB
ANDB
OR
ORB
XOR
XORB

2
3
,2
3
2
2
2
2

LD
LOB
ST
STB
LOBSE
LOBZE

2
2
2
2
2
2

AO
BO
CO
C4
BC
AC

3
3
3
3

PUSH
POP
PUSHF
POPF

I
1
0
0

C8
CC
F2
F3

2
2
1
I

60
40

70
50
80
90

84
94

~re
Ii)~

3
4
3
4
3
3
3
3

4
5
4
5
4
4
4
4

'4
4
4
4
4
4

8
12

PUSHF
POPF

I
1
0
0

2
1
I

F2
F3

~re
Ii)~

ere

~:I m ~:I
m
III 1i)F= III 1i)F=

LOGICAL INSTRUCTIONS
61 4
5
62 3 6111
3 7112.·
41 . 5 . 6
42 4 7112 4 8/13
71 3
4
3 7/12
72 3 6111
51 ,4
5
52 4 7/12 4 8/13
81 4
3 7/12
82 3 6111
5
91 3
4
92 3 6111
3 7/12
85 4
86 3 6111
3 7/12
5
4
95 3
96 3 6111
3 7/12
DATA TRANSFER INSTRUCTIONS
AI 4
5
3 7/12
A2 3 6111
BI 3
4
B2 3 6/11
3 7/12
- - . ' - C2 3 7111 3 8/12
C6 3 7/11
3 8/12
- - 4
BD 3
BE 3 6111
3 7112
AD 3
4
AE 3 ~II
3 7/12
STACK OPERATIONS (Internal stack)

SHORT

m
III e~

63
43
73
53
83
93
87
97

4
5
4
5
4
4
4
4

6111
7112
6111

~I
~~
7112

7/12

5
6
5
·6

6111
6111
6111
6111

5
5
5
5

A3
B3
C3
C7
BF
AF

4 ·6111
4 6111
4 7/11
4 7111
4 6111
4 6111

5
5

7112

CB
CF

3
3

11i15

12116

14/18

\4118

STACK OPERATIONS (external stack)
3
12
CA 2 15119 2 16120
CE 2 16120 2 16120
- -

CB
CF

3
3

15/19

4
4

16120
16120

- -

CA 2
CE 2

11115
14/18

2
2

12116

8/13
7/12

8113
7/12
7/12
7/12
7/12

7112

7/12
8/12

81-12

S 7112

PUSH
. POP

ere

III

INDEXED@)
LONG

INDIRECT@)
AUTo-INC.
NORMAL

IMMEDIATE

DIRECT'

12
14
12 '

16120

JUMPS AND CALLS
MNEMONIC OPCODE
UMP
E7
20:27@
SJMP
E3
BRII

BYTES
3'
2
2

STATES
8
8
8

MNEMONIC
LCALL
SCALL
RET
TRAPQ)

OPCODE
EF
28-2F@
FO
F7

BYTES
3
2
1
1

STATES
13/1(4)
13/1(4)

1211(4)
21/24
270246-64

NOTES:
'0------- HSI
•• - IOCO.2

roO""'-0-'---- HSI

HSI.1 ~
T2CLK - 0 :. - IOCO.7

(High
Byte)

TIMER2
CLOCK

;.- IOCO.4

""-0-------- HSI

HSI.2 - 0

;. - IOCO.6

'-'0------- HSI

HSI.3 - 0

270246-57

(Low
Byte)

Priority

2010H Not Applicable
200EH 7 (Highest)
200CH
6
200AH
5
2008H
2006H

4
3

2004H

2002H

2000H

o (Lowest)

10SO (15H)
IOS1 (16H)
HSO.O CURRENT STATE
HSO.1 CURRENT STATE

SOFTWARE TIMER ,0 EXPIRED

HSO.2 CURRENT STATE

SOFTWARE TIMER 1 EXPIRED

HSO.3 CURRENT STATE

SOFTWARE TIMER 2 EXPIRED

HSO.4 CURRENT STATE

SOFTWARfTIMER 3 EXPIRED

HSO.5 CURRENT STATE
CAM

TIMER 2 HAS OVERFLOW

HOLOING REGISTER IS FULL

TIMER 1 HAS OVERFLOW

HSO HOLDING REGISTER IS FULL

HSI FIFO IS FULL

270246-58

HSI HOLDING REGISTER DATA AVAILABLE
270246-60

2-56

8X9X HARDWARE DESIGN INFORMATION

Slave Programming Mode Commands

Chip Configuration

'1 7 1sI511 ~ 21 ~ ~

Cf.lIP CONFIGURATION REGISTER

L RESERVED (Set to

1 for
compatibility with future

parts) .
~

BUS WIDTH SELECT
(16 - BIT BUS / ><""8--:-;B""ITr;B"'U"'s)

P4.7

P4.6

Action

0
0
1
1

0
1

Word Dump
Dilta Verify
Data Program
Reserved

0
1

8X9XBH Signature Word

WRITE STROBE MODE SELECT
.
(WR AND BHE/WRL AND WRH)
ADDRESS VALID STROBE SELECT
(ALE/ ADV)
(iRCO) } INTERNAL READY
(iRC1) CONTROL MODE

Device

Signature Word

879XBH
839XBH
809XBH

896FH
896EH
Undefined

Port 2 Pin Functions

(LOCO) } PROGRAM LOCK
(LOCI) MODE

Port

Function

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5

Output
Input
Input
Input
Input
Output

Alternate Function

270246-61

Internal Ready Control
IRC1

IRCO

Description

Limit to 1 Wait State
Limit to 2 Wait States
Limit to 3 Wait States
Disable Internal Ready Control

Interrupt Pending Register
(LOCATION 09H)

Program Lock Modes
LOC1

LOCO

Protection

0
0

Read and Write Protected
Read Protected'
Write Protected
No Protection

0
1

17161514131211101

Reserved

Slave Programming

6-0BH

Reserved

OCH

Auto Programming Mode

ODH

Program Configuration Byte

OEH-OFH

Reserved

t 1.

~~:,~~E,,,

HSO EVENT
HSI BIT 0
SOFTWARE TIMERS
" - - - - - - - - - - - SERIAL I/O
~-------- EXTERNAL INTERRUPT
270246-62

Programming Function PMODE Values
PM ODE
Programming Mode
0-4

TXD (Serial Port Transmit)
RXD (SE!rial Port Receive)
EXTINT (External Interrupt)
T2CLK (Timer 2 Clock)
T2RST (Timer 2 Reset)
PWM (Pulse Width Modulation)

2-57

MCS®-96
809XBH, 839XBH, 879XBH
ADVANCED 16-BIT MICROCONTROLLER
. WITH 8- .OR 16-BIT EXTERNAL BUS
• 879XBH: an 809XBH with 8 Kbytes of On-Chip EPROM
• 839XBH: an 809XBH with 8 Kbytes of On-Chip ROM

•
•
•
•
•
•
•
•

232 Byte Register File
Register-to~Register

Architecture

10-Bit A/D Converter with S/H
Five 8-Bit I/O Ports
20 Interrupt Sources
Pulse-Width Modulated Output
ROM/EPROM Lock
Run-Time Programmable EPROM

•
•
•
•
•
•
•
•

High Speed 110 Subsystem
Full Duplex Serial Port
Dedicated Baud Rate Generator
6.25 J-ts ~6 x 16 Multiply
6.25 J-ts 32/16 Divide
16-Bit Watchdog Timer
Four 16-Bit Software Timers
Two 16-Bit Counter/Timers

The MCS-96 family of 16-bit microcontrollers consists of many members, all of which are designed for highspeed control functions. The MCS-96 family members produced using Intel's HMOS-III process are described
in this data sheet.
The CPU supports bit, byte, and word operations. Thirty-two bit double-words are supported for a subset of the
instruction set. With a 12 MHz input frequency the 8096BH can do a 16-bit addition in 1.0 p.s and a 16 x 16-bit
multiply or 32/16 divide in 6.25 p.s. Instruction execution times average 1 to 2 p.s in typical applications.
Four high-speed trigger inputs are provided to record the times at which external events occur. Six high-speed
pulse generator outputs are provided to trigger external events at preset times. The high-speed output unit can
s,imultaneously perform software timer functions. Up to four 16-bit software timers can be in operation at once.
The on-chip AID conver~er includes a Sample and Hold, and converts up to 8 multiplexed analog input
channels to 10-bit digital values. With a 12 MHz crystal, each conversion takes 22 p.s. This feature is only
available on the 8X95BHs and 8X97BHs, with the 8X95BHs having 4 multiplexed analog inputs.
Also provided on-chip are a serial port, a Watchdog Timer, and a pulse-width modulated output signal.

PORTO PORT 1

PORT2
AL T FUNCTIONS

HSI HSO

270090-50

Figure 1. MCS®-96 Block Diagram

2-58

October 1990
Order Number: 270090-007

inter

~OO~!bDrMlD~~OOW

8X9XBH

OFfH

255,
POWER-DOWN
RAM

OFOH
OEFH

INTERNAL
REGISTER FILE
(RAM)

240
239

FFFFH
1AH
19H

STACK POINTER

1SH

25
4000H

17H

PWM_CONTROL

16H

IOS1

10Cl

15H

10SO

lOCO

14H
13H

EXTERNAL MEMORY
OR I/O

,INT£RNAL PROGRAM
STORAGE ROM/EPROM
OR
EXTERNAL MEMORY
I

20
RESERVED

RESERVED

12H

19
1S

11H

SP_STAT

SP_CON

10H

10 PORT 2

OFH

10 PORT 1

OEH

10 PORT 0

BAUD_RATE

ODH

TIMER2 (HI)

OCH

TIMER2 (LO)

OBH

TIMERl (HI)

OAH

TIMER1 (LO)

WATCHDOG

09H

INLPENDING

INT_PENDING

13
RESERVED

2072H - 297FH

SIGNATURE WORD

2070H- 2071H

RESERVED

2030H - 206FH

SECURITY KEY

2020H - 202FH

~ESERVED

201CH-201FH

SELF JUMP OPCODE (27H FEH)

201AH- 201BH

RESERVED

2019H

CHIP CONFIGURATION BYTE

201SH

RESERVED

11
10

OSH

INLMASK

07H

SBUF (RX)

SBUF (TX)

06H

HSLSTATUS

OSH

20S0H

RESERVED

2012H - 2017H

INTERRUPT VECTORS
2000H
PORT 4

1FFfH

HSO_COMMAND

PORT 3

1fFEH

HSLTIME (HI)

HSO_TlME (HI)

04H

HSLTIME (LO)

HSO_TIME (LO)

EXTERNAL MEMORY
OR I/O

03H

AD_RESULT (HI)

HSLMODE

02H

AD_RESULT (LO)

AD_COMMAND

01H

RO (HI)

OOH

RO (LO)
(WHEN READ)

RO (LO)

INTERNAL RAM
REGISTER FILE
STACK POINTER
SPECIAL fUNCTION REGISTERS
(WHEN ACCESSED AS DATA MEMORY)

0100H
OOfFH

OOOOH

, (WHEN WRITTEN)
270090-6

Figure 2. Memory Map

2-59

8X9XBH

PACKAGING
The 80968H is available in 48-pin, 64-pin, and 68-pin packages, with and without AID, and with arid without
on-chip ROM or EPROM. The 80968H numbering system is shown in Figure 3. Figures 4-9 show the pinouts
for the 48-, 64- and 68-pin packages. The 48-pin version is offered in a Dual-In-Line package while the 68-pin
versions come in a Plastic Leaded Chip Carrier (PLCC), a Pin Grid Array (PGA) or a Type "8" Leadless Chip
Carrier.
Factory Masked
ROM
68-Pin
ANALOG

64-Pin

User Programmable

CPU

EPROM

48-Pin

68-Pin

64-Pin

48-Pin

68-Pin

48-Pin

68-pin

64-Pin

48-Pin

8795BH 8197BH 8797BH

8397BH 8397BH 8395BH 8097BH 8097BH 8095BH 8797BH

NO ANALOG 8396BH

OTP

64-Pin

8096BH

Figure 3. MCS®96 Packaging-8X9XBH
NOTES:
1. 48·pin devic!ls have four Analog Input pins.
2. 64-pin devices have all 48-pin device features plus the
following:
Four additional Analog Input channels
One additional Quasi-Bidirectional 8-bit Parallel Port
Four additional Port 2 pins with multiplexed features
. Timer 2 Clock Source pin
Timer 2 Reset pin
Two additional quasi-bidirectional port pins

PGAI
lCC

PlCC

Description

PGAI
PlCC
lCC

3. 68-pin devices have 48 and 64-pin features plus the following:
Dynamic Buswidth sizing (8 or 16-bit bus)
Dedicated System Clock Output (CLKOWT)
INST pin for memory expansion
Non-Maskable Interrupt for debugging
4. Package Designators:
N=PLCC
C=Ceramic DIP
A = Ceramic Pin Grid Array
P = Plastic DIP
R = Ceramic LCC
U = Shrink DIP

Description

PGAI
lCC

PlCC

Description

ACH7/PO.7/PMOD.3

AD6/P3.6

P1.6

ACH6/PO.6/PMOD.2

AD7/P3.7

P1.5

ACH2/PO.2

AD8/P4.0

HSO.1

ACHO/PO.O

AD9/P4.1

HSO.O

ACH1/PO.1

AD10/P4.2

HSO.5/HSI.3

ACH3/PO.3

AD11/P4.3

HSO.4/HSI.2

NMI

AD12/P4.4

HSl.l

AD13/P4.5

HSI.O

VCC

AD14/P4.6

Pl.4

VSS

AD15/P4.7

Pl.3

XTAL1

T2CLK/P2.3

Pl.2

XTAL2

READY

Pl.l

CLKOUT

T2RST/P2.4

Pl.0

BUSWIDTH

BHE/WRH

TXD/P2.0/PVERISALE

INST

WR/WRL

RXD/P2.1/PALE

ALE/ADV

PWM/P2.5/PDO/SPROG

RESET

P2.7

EXTINT IP2.2/PROG

ADO/P3.0

VPP

VPD

59
\ 58

AD1/P3.1

VSS

VREF

AD2fP3.2

HSO.3

ANGND

AD3/P3.3

HSO.2

ACH4/PO.4/PMOD.0

AD4/P3.4

P2.6

ACH5/PO.5/PMOD.l

AD5/P3.5

Pl.7

Figure 4a. PGA, PLCC and LCC Function Pinouts
2-60

8X9XBH

Description
1

2
3
4
5

6
7
8
9
10
11
1213
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

EA
ACH3/PO.3
ACH1/PO.1
ACHO/PO.O
ACH2/PO.2
ACH6/PO.6/PMOD.2
ACH7 IPO. 7 IPMOD.3
ACH5/PO.5/PMOD.1
ACH4/PO.4/PMOD.0
ANGND
VREF
VPD
. EXINTIP2.2/PROG
RESET
RXD/P2.1/PALE
TXD/P2.01
PVERISALE
P1.0
P1.1
P1.2
P1.3
P1.4
HSI.O
HSI.1
HSO.4/HSI.2
HSO.5/HSI.3
. HSO.O
HSO.1
P1.5
P1.6
P1.7
P2.6
HSO.2

Description
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

HSO.3
VSS
Vpp
P2.7
PWM/P2.51
PDO/SPROG
WR/WRL
SHE/WRH
T2RST/P2.4
READY
T2CLK/P2.3
AD15/P4.7
AD14/P4.6
AD13/P4.5
AD12/P4.4
AD11/P4.3
AD10/P4.2
AD9/P4.1
AD8/P4.0
AD7/P3.7
AD6/P3.6
AD5/P3.5
AD4/P3.4
AD3/P3.3
AD2/P3.2
AD1/P3.1
ADO/P3.0
RD
ALE/ADV
XTAL2
XTAL1
Vss
Vee

270090-56

Figure 5. Shrink-DIP Package

Figure 4b. Shrink-DIP Function Pinouts

2-61

inter

8X9XBH

/1
68
...eHS/PO.S

ADO/P3.0

ACH.4/PO.4

AOt/P!.1

ANGHD

AD2/Pl.2

VREf
VpD

13
,.

E)clINT/P2.2

RESEr

RXDjf>2.1

TXO/P2.D

MCS®-96
68 PIN
PLCC

AD8/P4.0
51

PI.!

Pt."
HSIO

ADS/P... ,

ACID/P"".2

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD

A011/P4.3
AOI2/P ... "
ADI3/p4.5
AD14/P4.6

HSII

AOI5/P4.7
44

HSI2/HS04

A04/P3.4

A05/P3.5
A06/p3.6

f1.0

ACl/P3.!

A07/P!.7

Plot

9 1011 121314 15 16 17 L
18
19

65
64

T2CLK/P2.3

VU~~Mll~U~~D~~~~gg

3 4 5'6 7

21
22

MCS®-96
68 PIN
LEADLESS CHIP CARRIER
TYPE "B"
(EPRO~ ONLY) .

62
61
60
59

23
24
25
26
27

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD.

58
57
56

28
29
30

55
54

31
32

~~~.~Q~~«gQ~~~~n~~r

270090-5
270090-3

Figure 8. 68-Pin Package (LCC - Top View)

Figure 6. 68-Pln Package (PLCC - Top View)

Pins Facing Down
7

18 19 16 14 12 10 8

17 15 13 11

1'-,

2 68

2021
2223
2425

6766
MCS-96
68 PIN
GRID ARRAY

2627
2829
3031
3233

6564
6362
61 60

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD

5958
5756
5554

34 36 38 40 42 44 46 48 50 53 52
35 37 39 41 43 45 47 49 51

270090-4

Figure 7. 68-Pin Package
(Pin Grid Array - Top View)

RXD/P2.1

RESET

TXD/P2.0

EXTINT/P2.2

HSIO
HSII
. HSI2/HS04

VPD
VREF ·
ANGND'

HSI3/HS05

ACH4/PO.4

HSOO

ACH5/PO.5

HSOI

ACH7/PO.7

HS02

ACH6/PO.6

HS03

vss

EA
Vce

vpp

Vss

PWM/P2.5

XTAL1

WRL/WR

XTAL2

WRH/BHE
READY

ALE/ADV

ADI5/P4.7

ADO/P3.0

ADI4/P4.6

AD1/P3.1

ADI3/P4.5

AD2/P3.2

ADI2/P4.4

AD3/P3.3

AD11/P4.3

AD4/P3.4

AD10/P4.2

AD5/P3.5

AD9/P4.1

AD6/P3.6

AD8/P4.0

AD7/P3.7

270090-2

Figure 9. 48-Pin Package

8X9XBH

PIN DESCRIPTIONS
Name and Function

Symbol
Vcc

Main supply voltage (5V).

Vss

Digital circuit ground (OV). There are two Vss pins, both of which must be connected.

VPD

RAM standby supply voltage (5V). This voltage must be present during normal operation. In a Power
Down condition (i.e. Vee drops to zero), if RESET is activated before Vee drops below spec and VPD
continues to be held within spec., the top 16 bytes in the Register File will retain their contents. RESET
must be held low during the Power Down and should not be brought high until Vee is within spec and
the oscillator has stabilized.

VREF

Reference voltage for the AID converter (5\1). VREF is also the supply voltage to the analog portion of '
the AID converter. and the logic used to read Port O.

ANGND

Reference ground for the AID converter. Must be held at nominally the same potential as Vss.

VPP

Programming voltage for the EPROM devices. It should be + 12. 75V for programming and will float to
5V otherwise. The pin should not be above Vee for ROM and CPU devices. This pin must be left
floating in the application circuit for EPROM devices.

XTAL1

Input of the oscillator inverter and of the internal clock generator.

XTAL2

Output of the oscillator inverter:

. CLKOUT*t

Output of the internal clock generator. The frequency of CLKOUT is
33% duty cycle.

Ya the oscillator frequency. It has a

RESET

Reset input to the chip. Input low for a minimum 10 XTAL 1 cycles to reset the chip. The subsequent
low-to-high transition re-synchronizes CLKOUr and commences a 10-state-time sequence in which the
PSW is cleared, a byte read from 2018H loads CCR, and a jump to location 2080H is executed. Input
high/or normal operation. RESET has an internal pullup.

BUSWIDTH*t

Input for bus width selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in
progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bitcycle occurs. If
CCR bit 1 is a 0, the bus is always an 8-bit bus. If this pin is left unconnected, it will rise to Vee.

NMI*t

A positive transition causes a vector to external memory location 0000f:t. I:xternal memory from OOH
through OFFH is reserved for Intel development systems.

INST*t

Output high during an external memory read indicates the read is an instruction fetch. INST is valid
throughout the bus cycle.

ALE/ADV

Input for memory select (External Access). EA equal to a TTL-high causes memory accesses to
locations 2000H through 3FFFH to be directed to on-Chip ROM/EPROM. EA equal to a TTL-low caUses
accesses to these locations to be directed to off-chip memory. EA = + 12.75V causes execution to
, begin in the Programming Mode. EA has an internal pulldown, so it goes to 0 unless driven otherwise.
Address Latch Enable or Address Valid output, as selected by CCA. Both pin options provide a latch to
demultiplex the address from the address/data bus. When the pin is ADV, it goes inactive high at the
end of the bus cycle. ADV can be used as a chip select for a single external RAM memory. ALE/ ADV is
activated only during external memory accesses.

Read signal output to external memory. RD is aqtivated only during external memory reads.

WR/WRI

Write and Write Low output to external memory, as selected by the CCR. WR will go low for every
external write, while WRL will go low only for external writes where an even byte is being written.
,
WR/WRL is activated only during external memory writes.

BHE/WRH

Bus High Enable or Write High output to external memory, as selected by the CCA. BHE = 0 selects
the bank of memory thatis connected to the high byte of the data bus. AO = 0 selects the bank of
memory that is connected to the low byte of the data bus. Thus accesses to a 16-bit wide memory can
be to the low byte only (AO = 0, BHE ~ 1), to the high byte only (AO = 1, BHE = 0), or both bytes
(AO = 0, BHE = 0). If the WRH function is selected, the pin will go low if the bus cycle is writing to an
odd memory location.

"Not available on Shrink· DIP package
tNot available on 48·pin device

2·63

intJ

8X9XBH

PIN DESCRIPTIONS (Continued)
Symbol
READY

Name and Function
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or
" for bus sharing. If the pin is high, CPU operation continues in a normal manner. ,If the pin is low
prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until the next
positive transition in CLKOUr occurs with READY high. The bus cycle can be lengthened by up
to 1 ",s. When the external memory is not being used, READY has no effect. Internal control of
the number of wait states inserted into a bus cycle held not ready is available through
configuration of CCR. READY has a weak internal pullup, so it goes to 1 unless externally pulled
low.

HSI

Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2, and HSI.3. Two
of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are also used as inputs by
EPROM devices in Programming Mode.

HSO

Outputs from High Speed Output Unit. Six HSO"pins are available: HSO.O, HSO.1, HSO.2, HSO.3,
HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.

Port 0:1:

8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog
inputs to the on-chip AID converter. These pins are also a mode input to EPROM devices in the
Programming Mode.

Port 1t

8-bit quasi-bidirectional I/O port.

Port2t

8-bit multi-functional port. Six of its pins are shared with other functions in the 8096BH, the
remaining 2 are quasi-bidirectional. These pins are also used to input and output control signals,
on EPROM devices in Programming Mode.

Ports 3 and 4

8-bit bi-directionall/O ports with open drain outputs. These pins are shared with the multiplexed
address/data bus which has strong internal pullups. Ports 3 and 4 are also used as a command,
address and data path by EPROM devices operating in the Programming Mode. When used as
ports, pull ups to Vee may be needed,
tNot available on 48-pin device
:rPort 0.0.1.2.3 not available on 48-pin device

2-64

8X9XBH

AID Result LO (02H) .

~ 1 ,"~"a ""~'"

./0

r; I-I-3

SlATUS:
0 = AID CURRENTLY 10LE
x
1 = CONVERSION IN PROCESS

CHANNEL

# SELECTS WHICH OF THE 8

ANALOG INPUT CHANNELS IS TO BE

CONVERTED TO DIGITAL FORM.
GO INDICATES WHEN THE CONVERSION IS TO
BE INITIATED (GO = 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).

~r-x

"6}
.2.

AID Command (02H)

270090-24

AID RESULT:
LEAST SIGNIFICANT 2 BITS

SPCON/SPSTAT (11H)

270090-21

O'}

W
R
I 2 -

BIT!. BITO SPECIFY THE MODE
00 = MODE 0
IO=MODE 2
01 = MODE 1 11 = MODE 3
PEN ENABLE THE PARITY FUNCTION

REN

.2.

HSLMode (03H)

I 7 61 s 41 3 21' 10 1

HSI.O

~ODE

HSI.3

~ODE

ENABLES THE RECEIVE FUNCTION

4 -TB8

PROGRAMS THE 9TH DATA BIT

5 -TI

IS THE TRANSMIT INTERRUPT FLAG

S-RI
"7 -RBB

HSI.l ~ODE
HSI.2

3 -

RPE

IS THE RECEIVE INTERRUPT FLAG
IS THE 9TH DATA RECEIVED
(IF NOT PARITY)
IS THE PARITY ERROR INDICATOR
(IF PARITY ACTIVE)

WHERE EACH 2 - BIT MODE CONTROL FIELD
DEFINES ONE OF 4 POSSIBLE MODES:
00
01
10
II

270090-26

8 POSITIVE TRANSITIONS
EACH POSITIVE TRANSITION
EACH NEGATIVE TRANSITION
EVERY TRANSITION
(POSITIVE AND NEGATIVE)

Baud Rate Calculations
UBlng XTAL 1:
Mod 0: 8aud ~ XTAL 1 frequency. 8 ,. 0

270090-22

Oth

Rate

4"(8

+ 1)

•

. Baud ~ XTAL IIrequency
erB. Rate
64" (8 + 1)

UBlng T2CLK:

M do O' 8aud ~ T2CLK frequency. 8 " 0
o
• Rate
B
'

HSO Command (06H)
CHANNEL:
o-s HSO.O - HSO.S
. BIT:

0]6
7
8-B
2
E
3

HSO.O AND HSO.l
HSO.2 AND HSO.3
SOFTWARE TI~ERS
R£SET TIMER2

• Baud _ T2CLK froquoncy . 8
hera. Rat~ 16.8
,"* 0

Note that 8 cannot equal 0, except when u81ng XTAL 1 In other
than Mode O.

START AID CONVERSION
INTERRUPT I NO INTERRUPT

Chip Configuration

SET I CLEAR

O. CHIP CONFIGURATION REGISTER

"'r'T"""'r'T"T'T"'r'

moiER 2/TIMER 1

RESERVED (Set to 1 for
compatibility with futUre

port.)

'270090-23

BUS WIDTH SELECT •
(16-BIT BUS/8-BIT BUS)
WRITE STROBE MODE 'SELECT
(WI! AND
1m AND WI!R)
ADDRESS VALID STROBE SELECT
(ALE/ ADV)

HSI_Status (06H)

17 61 5 413 211 101

(IRCO) }'NTERNAL READY CONTROL
'-----(IRC1) MODE

L,HSI.O STATUS

(LOCO) )
L - - - - - - ( L O C 1 ) PROGRAM 1.0CK MODE

HSI.I STATUS
HSI.2 STATUS

270090'-32

HSI.3 STATUS
WHERE FOR EACH 2-111T STATUS FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.

270090-25

2-65

inter

8X9XBH

Interrupt Pending/Mask Register
(LOCATION 08H, 09H)
17161514131211101

1 .

~::,;~::~2E"

c--_ _ _ _ _ _ _ _

HSO EVENT
HSI BIT 0
SOFTWARE TIMERS
SERIAL I/O

' - - - - - - - - - - - EXTERNAL INTERRUPT

270090-55

PSW Register

lOCO (15H)*

IOSO (15H)

HSI.O INPUT ENABLE / DISABLE

HSO,O CURRENT STATE

TIMER 2 RESET EACH WRITE

HSO.1 CURRENT STATE

HSI.1 INPUT ENABLE / DISABLE

HSO.2 CURRENT STATE

TIMER 2 EXTERNAL RESET ENABLE / DISABLE

HSO.3 CURRENT STATE

HSI.2 INPUT ENABLE / DISABLE

HSO.4 CURRENT STATE

TIMER 2 RESET SOURCE HSI.O / T2RST

HSO.5 CURRENT STATE

HSI.3 INPUT ENABLE / DISABLE

CAM QB HOLDING REGISTER IS FULL

HSO HOLDING REGISTER IS FULL

TIMER 2 CLOCK SOURCE: HSI.1 / f2ciJ(
270090-30

270090-27

lOCO (15H)*

IOC1 (16H)

T2RST - - 0 • - - IOCO.5

~~'-----T2

SELECT PWM / SELECT P2.5
RESET

EXTERNAL INTERRUPT ACH7 / EXTINT

• - - IOCO.3
• - - IOCO.O

TIMER 1 OVERFLOW INTERRUPt ENABLE / DISABLE

~_------- HSI

HSI.O
.

TIMER 2 OVERFLOW INTERRUPT ENABLE / DISABLE

• - - IOCO.2

HSO.4 OUTPUT ENABLE / DISABLE

~)-------- HSI

HSI.1
T2CLK - - 0 :--IOCO.7

SELECT TXD / SELECT P2.0

TIMER2
CLOCK

HSO.5 OUTPUT ENABLE / DISABLE
HSI INTERRUPT
FIFO FU LL /uHO;-'L:O:D"'INU'G"R"'E"GI;<'ST"'E'iiR'L"O;;:;AD"'E'liD

• - - IOCO.4

""'-0_-----'---..... HSI
• -- IOCO.6
HSI.3 - - 0
""'-0--------- HSI

HSI.2 - - 0

270090-31

270090-29

"See Errata section

2-66

8X9XBH

Vector Location
Vector

(High
Byte)

(Low
Byte)

1051 (16H)
Priority
SOFTWARE .TlMER 0 EXPIRED
SOFTWARE TIMER 1 EXPIRED

Software Trap
2011H
Extint
·200FH
Serial Port
200DH
Software
200BH
Timers
HSI.O
2009H
High Speed
2007H
Outputs
2005H
HSI Data
Available
AID Conversion 2003H
Complete
Timer Overflow 2q01H

2010H Not Applicable
200EH 7 (Highest)
200CH
6
200AH
5
2008H
2006H

4
3

2004H

2002H

2000H

o (Lowest)

SOFTWARE TIMER 2 EXPIRED
SOFTWARE TIMER :5 EXPIRED
TIMER 2 HAS OVERFLOW
TIMER 1 HAS OVERFLOW
HSI FIFO IS FULL
HSI HOLDING REGISTER DATA AVAILABLE
270090-28

2-67

8X9XBH

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*

+70°C

Ambient Temperature Under Bias .... O°C to
Storage Temperature .......... - 40°C to

NOTICE: This data sheet contains' preliminary information on new products in production. The specifications are subject to change without notice.

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

+ 150°C

Voltage from EA or Vpp
to VSS or ANGND ........•.... ~O.3V to +13.0V
Voltage from Any Other Pin to
VSS or ANGND .............. - O.3V to

+ 7.0V·

Average Output Current fro.m Any Pin ....... 10 mA
Power Dissipation .......................... 1.5W
'This includes Vpp on ROM and CPU only devices.

OPERATING CONDITIONS
(All characteristics in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol

Parameter

Min

Max

Units

Ambient Temperature Under Bias

+70

°C

Vee

Digital Supply Voltage

4.50

5.50

VREF

Analog Supply Voltage

4.50

5.50

lose

Oscillator Frequency

6.0

MHz

Vpo

Power-Down Supply Voltage

4.50

5.50

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. CHARACTERISTICS
Symbol

Max

Units

Icc

Vee Supply Current (O'C ,;; TA ,;; 70'C)

Parameter

240

185

lee1

Vee Supply Current (TA = 70'C)

Ipo

VPD Supply Current

Min

Test Conditions
All Outputs
Disconnected.
Normal operation
and Power· Down.

-0.3

+0.8

Input High Voltage (Except RESET, NMI, XTAL 1)

2.0

Vee +0.5

VIH1

Input High Voltage, RESET Rising

2.4

Vee +0.5

VIH2

Input High Voltage, RESET Falling (Hysteresis)

2.1

Vee +0.5

VIH3

Input High Voltage, NMI, XTAL 1

2.2

Vee +0.5

III

Input Leakage Current to each pin 01 HSI, P3, P4, and to P2.1.

±10

p.A

Vin =

Ill1

D.C. Input Leakage Current to each pin 01 PO

p.A

Yin =

IREF

VREF Supply Current

Vil

Input Low Voltage

VIH

IIH

Input High Current to EA

IlL

Input Low Current to each pin 01 P1,
and to P2.6, P2.7.

100

p.A

VIH = 2.4V

-125

p.A

Vil = 0.45V

IIL1

Input Low Current to RESET

-2

Vil = 0.45V

IIL2

Input Low Current P2.2, P2.3, P2.4, READY, BUSWIDTH

-50

p.A

Vil = 0.45V

VOL

Output Low Voltage on Quasi·Bidirectional
port pins and P3, P4 when used as ports

0.45

1m = 0.8mA
(Note 1)

VOL1

Output Low Voltage on Quasi·Bidirectional
port pins and P3, P4 when used as ports

0.75

IOl = 2.0 mA
(Notes 1, 2, 3)

0.45

IOl = 2.0mA
(Notes 1, 2, 3)

VOl2

-0.25

oto Vee
oto Vee

Output Low Voltage on Standard Output
pins, RESET and Bus/Control Pins

2-68

intJ

8X9XBH

D.C. CHARACTERISTICS (Continued)
Parameter

Min

VOH

Symbol

Output High Voltage on Quasi-Bidirectional
pins

2.4

Max

Units
V

IOH = -20 p.A
(Note 1)

VOH1

Output High Voltage on Standard Output
pins and Bus/Control pins

2.4

IOH = - 200 p.A
(Note 1)

IOH3

Output High Current on RESET

-50

Pin Capacitance (Any Pin to Vss)

Test Conditions

p.A

VOH = 2.4V

fTEST = 1.0 MHz

NOTES:
1. Quasi-bidirectional pins include those on P1, for P2.6 and P2.7. Standard Output Pins include TXD, RXD (Mode 0 only),
PWM, and HSO pins. Bus/Control pins include CLKOUT, ALE, BHE, RD, WR, INSTand ADO-15.
2. Maximum curtent per pin must be externally limited to the following values if VOL is held above 0.45V.
IOl on quasi-bidirectional pins and Ports 3 and 4 when used as ports: 4.0 mA
IOl on standard output pins and RESET: 8.0 mA
IOL on Bus/Control pins: 2.0 mA
3. During normal (non-transient) operation the following limits apply:
Total. IOL on Port 1 must not exceed 8.0 mAo
TotaiiOL on P2.0, P2.6, RESET and all HSO pins must not exceed 15 mA
Total IOl on Port 3 must not exceed 10 mAo
Total IOL on P2.5, P2.7, and Port 4 must not exceed 20 mAo

A.C. CHARACTERISTICS

(Test Conditions: Load Capacitance on Output Pins = 80 pF)

TIMING REQUIREMENTS (Other system components must meet these specs.)
Symbol

Parameter

Min

TCLYX(2,3)

READY Hold after CLKOUT Edge

hLYV

End of ALE/ ADV to READY Valid

hLYH

End of ALEI fS...DV to READY High

2Tosc+40

Address Valid to Input Data Valid

RD Active to Input Data Valid

--c-.

- -1---..e--

TRHDX

Data Hold after AD Inactive

TRHDZ

AD Inactive to Input Data Float

TAVGV(2,4)

Address Valid to BUSWIDTH Valid

TLLGX(2,3)
--=-=,

2Tosc-70

4Tosc-80

1000

--1 - - . _ - - - -1 - - - - - - - - - - -

Non-Ready Time

TYLYH

TRLDV

.- f - - - _ . _ . - - - - - - - - -1------

_TAVDV(4)
.

Units

Max

0(1)

BUSWIDTH Hold after ALE/ ADV Low
ALE/ ADV Low to BUSWIDTH Valid

TRLPV

Reset Low to Ports Valid

3Tosc - 100(5)

0
0

TLLGV(2,3)

- -r - ' - - -

5Tosc-120(5)

Tosc-25

2Tosc -125

.-1-------.---..---

Tosc +40

ns
Tosc -75

10Tosc

NOTES:
1. If the 48-pin or 64-pin device is being used then this timing can be generated by assuming that the CLKOUT falling edge
has occurred at 2Tosc+55 (TLLCH(max) + TCHCL(max)) after the falling edge of ALE.
2. Pins not bonded out on 64-pin devices
3. Pins not bonded out on 48-pin devices.
4. The term "Address Valid" applies to ADO-15, BHE and INST.
5. If wait states are used, add 3Tosc * N where N = number of wait states.

2-69

8X9XBH

TIMING RESPONSES (MCS-96 devices meet these specs)
Symbol

Parameter

Min

Max

Units

FXTAL

Oscillator Frequency

6.0

12.0

MHz

Tosc

Oscillator Period

166

0(4)

120(4)

TOHCH

XTAL 1 Rising Edge to Clockout Rising Edge

TCHCH(1,4)

CLKOUT Period(3)

3Tos0(3)

3Tosc(3)

TCHCL(1,4)

CLKOUT High Time

Tosc-35

Tosc+ 10

TCLLH(1,4)

CLKOUT Low to ALE High

-30

+15

TLLCH(4)

ALEI ADV Low to CLKOUT High(1)

Tosc-25

Tosc+45

hHLL
TAVLL(6)

ALEI ADV High Time

Tosc-30

Tos6+35(5)

Address Setup to End of ALEI ADV

Tosc-50

TRLAZ(7)

RD or WR Low to Address Float

Typ.

End of ALEI ADV to RD or WR Active

Tosc-40

hLRL
TLLAX(7)

Address Hold after End of ALEI ADV

Tosc-40

ns
ns

TWLWH

WR Pulse Width

3Tosc-35(2)

TOVWH

Output Data Valid to End of WR/WRL/WRH

3Tosc-60(2)

TWHOX

Output Data Hold after WR/WRL/WRH

Tosc-50

TWHLH

End of WR/WRL/WRH to ALE/ADv High

Tosc-75

TRLRH

RD Pulse Width

3Tosc-30(2)

TRHLH

End of RD to ALEI ADV High

Tosc-45

TCLLL(4)

CLOCKOUT Low(1) to ALEI ADV Low

Tosc-40

TRHBX(4)

RD High to INST(1), SHE, AD8-15 Inactive

TWHBX(4)

WR High to INST(1), SHE, AD8-15 Inactive

THLHH

WRL, WRH Low to WRL, WRH High

TLLHL

ALEI ADV Lowto WRL, WRH Low

TOVHL

Output Data Valid to WRL, WRH Low

Tosc-60

ns
Tosc+35

Tosc-25

Tosc+30

Tosc-50

Tosc+ 100

2Tosc-35

2Tosc+40

2Tosc-30

2Tosc+55

ns
ns

NOTES:
1. Pins not bonded out on 64-pin devices.
2. If more than' one wait state is desired, add 3Tosc for each additional wait state.
3. CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3Tosc ± 10 ns if Tosc is constant and
the rise and fall times on XTAL 1 are less than 10 ns.'
4. CLKOUT, INST, and BHE pins not bonded out on 4S-pin and 64-pin devices.
5. Max spec applies only to ALE. Min spec applies to both ALE and ADV.
6. The term "Address Valid" applies to ADO-15, BRE and INST.
7. The term" Address" in this definition applies to ADO-7 for S-bit cycles, and ADO-15 for 16-bit cycles.
'/

2-70

an+_r
' III-e-

8X9XBH

WAVEFORM

XTALI
CLOCKOUT
READY

.'. -_ .. -. --_.
AD --------------_(~D~AT~A~IN~-------270090-35

*Buswidth is not bonded out on 48- and 64-pin devices.

2-71

8X9XBH

__ Power Supply Rise Time

r - 5 •5V OC
i - - 4 •5V OC

Vce

.......
XTAL

9m'iw'~"~'i";m,m'~'~ii"ii'~~i~,~;~,m,,m;,~' ,~
0 ••" .

RESET

-I-

-I

Externol to Internal
Release Time

HSO.O-'HSO.3.
P2.0. P2.5
10 STATE TIMES

IADDRESS~

PORT3&4
WITH PULLUPS

2018H
cce
FIRST BUS FETCH CYCLE

TRLPV
10 XTAL CYCLES
External RESET Low to
Port Valid Time

RESET (UNCTION REGISTERS

ADDRESS I
2080H
PROGRAM
START

TOTAL 8X9X RESET TIME
270090-57

A.C. CHARACTERISTICS-SERIAL PORT--SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Test Conditions: Load Capacitance = BO pF

Symbol
TXLXL

Min

Parameter
Serial Port Clock Period
Serial Port Clock Falling Edge to Rising Edge

TOVXH

Output Data Setup to Clock Rising Edge

TXHOX

Output Data Hold After Clock Rising Edge

TXHOV

Next Output Data Valid After Clock Rising Edge

4Tose - 50

Input Data Setup to Clock Rising Edge

2Tose +200
0

ns
ns
ns
ns
5Tose

2-72

ns
ns

2Tose +50

. Input Data Hold After Clock Rising Edge
_.<-

+ 50

2Tose - 70

TXHDX

Last Clock Rising to Output Float

4Tose

3Tose

TDVXH

Units
ns

BTose

TXLXH

TXHQZ

Max

8X9XBH

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE

RXD--"',~~J--",J~~J--",J~~J--"~~,--"~"--'r~"--'r~'r--\r~\r

(IN)

270090-36

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TOlOl

Oscillator Frequency

MHz

TOHOX

High Time

TOlOX

Low Time

TOlOH

Rise Time

TOHOl

Fall Time

EXTERNAL CLOCK DRIVE WAVEFORMS

270090-4B

Ar) external oscillator may encounter as much as a 100 pF load at XTAl 1 when it starts up. This is due to interaction
between the amplifier and its feedback capacitance. Once the external signal meets the VIL and VIH specifications the
capacitance will not exceed 20 pF.
'

A.C. TESTING INPUT, OUTPUT WAVEFORM

FLOAT WAVEFORM
VlOAO +O.20 V

2.1.~ 2.0> TEST POINTS
0 . 4 5 ' - - / \ 0.8

v LOAD

2.0:

VLOAO -O.20 V

0.8 " - -

VOH -O.20

>TI~IN~~~isRENCE<
VOL +O.20·V

270090-51
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs, and Begins to Float
when a 200 mV change from the Loaded VOHIVOL Level occurs
IOLIiOH ;;, ± 15 mAo

270090-49
A.C. Testing inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logie "1" and O.BV for a Logie "0".

2-73

inter

8X9XBH

Minimum Hardware Configuration Circuits

47 p,r

270090-52

270090-53

2-74

8X9XBH

AID CONVERTER SPECIFICATIONS
AID Converter operation is verified only on the 8097BH, 8397BH, 809SBH, 839SBH, 8797BH, 879SBH.
The absolute conversion accuracy is dependent on the accuracy of VREF.
Test Conditions: VREF = S.12V, AGND = Vss = OV

Parameter

Typical"

Resolution

Minimum

Maximum

Units··

1024
1,0

1024
10

Levels
Bits

±4

LSBs

Absolute Error
Full Scale Error
Zero Offset Error

-O.S ±O.S

LSBs·

±O.S

LSBs
0

±4

LSBs

> -1

LSBs

±1

LSBs

Non-Linearity
Differential Non-Linearity
Channel-to-Channel Matching
Repeatability

±0.2S

LSBs

Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity

0.009
0.009
0.009

LSBI"C
LSBI"C
LSBrC
-60

Notes

1,3

Feedthrough

-60

Vcc Power Supply Rejection

-60

Off Isolation

3.0

fJ-A

Sample Delay

3Tosc - SO

3Tosc + SO

Sample Time

12Tosc - SO

12Tosc + 50

Input Resistance
D.C. Input Leakage

Sampling Capacitor

NOTES:
• These values are expected for most devices at 25'C.
•• An "LSB", as used here, is defined in the glossary which follows and has a value of approximately 5 mY.
1. DC to 100 KHz.
2. For starting the AID with an HSO Command.
3. Multiplexer Break-Before-Make Guaranteed.

2-75

•

inter

8X9XBH

EPROM SPECIFICATIONS
A.C. EPROM PROGRAMMING CHARACTERIST·ICS
Auto. Slave Mode Operating Conditions: Load Capacitance = 150 pF. TA = 25°C ±5°C. Vee. VPD. VREF
5.0V ± 0.5V. Vss, AGND = OV. Vpp = 12.75V ± 0.25V. EA = 11V ± 2.0V. fose = 6.0 MHz

Run-time Programming Operating Conditions: Fose = 6.0 MHz to 12.0 MHz. Vee. VPD. VREF = 5V ± 0.5V.
TA = 25°C to ±5°C and Vpp = 12.75V ± 0.25V. For run-time prpgramming over a full operating range.
contact the factory.

Symbol

Parameter

Min

Max

Units

TAVLL

ADDRESS/COMMAND Valid to PALE Low

TLLAX

ADDRESS/COMMAND Hold After PALE Low

TDVPL

Output Data Setup Before PROG Low

Tose

TpLDX

Data Hold After PROG Falling

Tose

TLLLH

Tose

180

' PALE Pulse Width

Tose '
100).LS +
144 Tose

TpLPH

PROG Pulse Width

TLHPL

PALE High to PROG Low

250

Tose

TpHLL

PROG High to Next PALE Low

600

Tose

TpHDX·

Data Hold After PROG High

Tose

TpHVV

PROG High to PVER/PDO Valid

500

Tose

250 Tose

TLLVH

PALE Low to PVER/PDO High

100

Tose

TpLDV

PROG Low to VERIFICATION/DUMP Data Valid

100

Tose

TSHLL

RESET High to First PALE Low (not shown)

2000

Tose

D.C. EPROM PROGRAMMING CHARACTERISTICS
Symbol

Parameter

Min

Ipp

Vpp Supply Current (Whenever Programming)

Vpp

Programming Supply Voltage

VEA

EA Programming Voltage

Max

Units

100

12.75 ±0.25

11 ±2.0

NOTE:

Vpp must be within tV of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground or Vss while
Vee> 4.5V.
/

2-76

8X9XBH

WAVEFORM-EPROM PROGRAMMING
r,..vLL
PORTS 3,4
PALE--_

PVER

PDO

VALID

----'

270090-43

Allowing more than seven FIFO entries to occur be·
tween cleared conditions will result in incorrect
status information for either the eighth or ninth con·
secutive entry. This effectively limits the total nUl\"
ber of records to seven.

8X9XBH ERRATA
Devices covered by this data sheet (see Revision
History) have the following errata.
1. INDEXED, 3 OPERAND MULTIPLY

There is one exception that will allow the FIFO to
correctly record eight events. If the first two ,events
of a cleared FIFO are separated by greater than 16
state times, the overflow conditions will always
cause the ninth event to be recorded with incorrect
status information. This is true even if- the event fol·
lowing the first two were only separated by eight
states.

The displacement portion of an indexed, three oper·
and (byte or word) multiply, may not be in the range
of 200H thru 17FFH inclusive. If you must use these
displacements, execute an indexed, two operand
multiply and a move if necessary.

2. HIGH SPEED INPUT FIFO OPERATION
3. RESET AND THE QUASI BIDIRECTIONAL
PORTS

To ensure proper operation (no overflow) of the High
Speed Input FIFO, it is imperative that any seven
consecutive FIFO entries be completely cleared be·
fore further events occur at the pins. To clear the
FIFO, some repetitive variation of the following in·
structions may be used ...
READ.HSI.TASK:

: NO INTERRUPTS

RELOAD.HREG:

JBC IOSI,7,RELOAD.HREG

:, WAIT FOR

Because RESET is asynchronous, it is possible to
apply RESET during writes to the quasi·bidirectional
port pins. If this occurs, the low impedance pullup
may not turn on, and only the high impedance pullup
is turned on. This causes the quasi·bidirectional pins
to go to their RESET state (logical one) but will not
do so before expiration of TRLPV max.

: HOLDING
: REGISTER TO
: LOAD
STB HSI.STAT, [PTR)
ST HSI.TIME, [PTR)

4. SOFTWARE RESET TIMING

: READ THE
: STATUS
: 'READ TIME TAG

The RESET pin will pull down for at least one state
time. if a software reset instruction executes or the
watchdog timer overflows. Earlier documentation in·
dicated two state times.

2·77

8X9XBH
5. USING T2CLK AS THE SOURCE FOR TIMER2
TIMER2 has two selectable clock sources, the
T2CLK or HSI.1 pins, selectable by bit IOCO.3. When
using T2CLK as the clock for TIMER2, writing to
lOCO may cause TIMER2 to ,increment. The user
should only write to lOCO once during ir;litializ~tion,
and then immediately clear TIMER2 using the HSO
. command OEH. Effectively, the customer cannot reset TIMER2 with bit IOCO.1, and can only use the
external reset sources or the HSO command when
using T2CLK as the clock source.
If the HSI.1 pin is the source for TIMER2, only the
first write to lOCO may cause TIMER2 to increment,
further writes will not increment TIMER2.

6. RESERVED LOCATION 2019H
The 1990 Architectural Overview recommendeq that
address 2019H be loaded with OFFH. The recommendation is now 20H.

DATA SHEET REVISION REVIEW
This data sheet (270090-007) is valid for devices
marked with a "D" at the end of the topside tracking
number: Data sheets are changed as new device
information becomes available. Verify with your local
Intel sales office that you have the latest version
before finalizing a design or ordering devices.
The following differences exist between this data
sheet and the previous version (-006).

1. T CCLH changed from Min = - 20 ns, Max =
'+25 ns to Min = -30 ns, Max = + 15 ns.
2. TXHQX changed from Min = 2Tosc - 50 ns to
Min = 2Tosc - 70 ns.
3. TOLOX changed from Min = 25 ns to Min =
30 ns,
4. An errata was added changing the recommendatipn for address 2019H from OFFH to 20H.
5. The power supply sequencing section has been
deleted. The information is in the Hardware Design Information.
6. The method of identifying the clirrent change indicator was added to the differences between the
~005 and -004 data sheets.
7. A bug was not documented in the -004 data
, sheet and was fixed before the -005 data. sheet.
Information on the bug was added to the difference between the -005 and -004 data sheets:

Dif,ferences ,between -006 and -005 data sheets.
1. All EPROM programming mode information has
been deleted and moved to the 16-Bit Handbook,
Hardware Design Information chapter.
, 2. Shrink-DIP package information has been added.
, 3. A new RESET timing specification has been added for olarity.
4. Software Reset pin timing information has been
added.
5. HSO IOl specifications have been improved so
that all HSO pins have the same drive capability.
6. Port 3 and Port 4 pin descriptions were clarified,
indicating the necessity of pullup if the pins are
used as ports.
7. HSI FIFO overflow description added.
Differences between the -005 and the -004 data
sheets.
1. The -005 data sheet corresponds to devices
marked with a "0" at the end of the topside
tracking number. The -004 data sheet corresponded to devices which are not marked with a
"0".
2. Much of the description of device functionality
has been deleted. All of this information is already in the Embedded controller handbooks in
the MCS-96 8096BH Architectural Overview
Chapter.
3. The A/D converter specification for Differential
Non-linearity has been changed to be a minimum
of > -1 Isbs to a maximum of +'2 LSBs.
4. 8X9XBH errata Section. The JBS and JBC on
Port 0 errata has been fixed on the latest device
stepping.
-5. 8X9XBH errata Section. The errata for the 48-pin
devices has been fixed on the latest device stepping.This errata caused the upper 8 bits on the
Address/Data bus to be latched when resetting
into an, 8-bit external memory system.
6. 8X9XBH errata section. An errata existed which
caused the device to be held in RESET for extended periods of time with the internal RESET
pin pulled down internally. The condition occurred when the XTAL inputs were driven before
Vcc was stable and within the data sheet specification. The condition was worse at cold. This errata was not documented in the -004 data sheet.
It has been fixed on the latest device stepping.
7. 8X9XBH errata Section. Errata, 3 and 4 have
been added to the errata list. These errata exist
for all steppings of the device.

2·78

8X9XBH

Differences between the -004 and the -003 data
"
sheets.

8. The EPROM programming section figures were
corrected to indicate the correct interface to a
2764A-2. A reset circuit was added to these figures and the signal PVAL (Port 3.X and Port 4.X)
is now identified as the valid signal for program
verification in the Auto Programming Mode. Text
was added to this section to reference the requirement of using the Auto CQnfiguration Byte
Programming Mode for 48-lead devices. Figure
22A was edited for corrections to the text, and
now indicates PVER (Port 2.0). The EPROM circuits were cQrrected to show 6 MHz operation
for programming devices from internal micro"
code.

1. The bus control figures and bus timing diagrams
were modified to more accurately describe their
operation. In particular the 8-bit bus modes now
reflect the use of Write Strobe Mode.
2. Additional text was added to the Analog/Digital
description of the conversion process to clarify
its operation and usefulness.
3. Text was added to the interrupt description section to indicate the maximum transition speed of
the input signal relative to the CPU's state timing. A figure was included to graphically demonstrate the interrupt response timing.
4. The pin descriptions were modified to indicate
that Vpp must normally float in the application.
5. The input low voltage specification (VIU) was
deleted and is covered by the VIL specification.
6. A suggested minimum configuration circuit was
added to the material.
7. The AID Converter Specifications for Differential Non-Linearity has been corrected to be a
maximum of + 2 LSB's.

9. The protected memory section was edited to indicate that the CPU will enter a "JUMP ON
SELF" condition when ROM/EPROM dump
mode is complete.
10. An 8X9XBH ERRATA section was added.
11. This REVISION REVIEW was added.

2-79

MCS®-96
809XBH/839XBH/879XBH
EXPRESS
•

Extended Temperature Range
( ~. 40°C to + 85°C)

•

Burn-In

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-96 family of
microcontroliers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes the commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.
With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of O°C to + 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of -40°C to + 85°C.
The optionaL burn-in is dynamic, for a minimum time of 160 hours at 125°C with Vee 0= 5.5V
guidelines in MIL-STD-883, Method 1015.

± 0.5V, following

Package types and EXPRESS versions are identified by a one- or two-letter prefix to the device number. The
prefixes are list~d in Table 1.
This data sheet specifies the parameters which deviate from the commercial temperature range option. The
.
commercial temperature range data sheets are applicable otherwise.

2-80

October 1990
Order Number: 270433-003

8X9XBH EXPRESS

OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Units

Ambient Temperature Under Bias

-40

+85

°C

D.C. CHARACTERISTICS
Symbol

Parameter

Min

Icc

Vcc Supply Current ( - 40°C S; T A S;

ICC1

Vcc Supply Current (TA

IREF

VREF Supply Current

IlL

Input Low Current to each pin of P1 ,
and to P2.6, P2.7.

+ 85°C)

=. + 85°C)

Max

Units

270

185

-150

p.A

Test Conditions
All Outputs
Disconnected.

VIL

0.45V

A.C. CHARACTERISTICS
Parameter

Max

Units

AD or WR Low to Address Float

Symbol

PACKAGING
Factory Masked
ROM-

68 Pin
ANALOG

64 Pin

48 Pin

User Programmable

CPU

68 Pin

64 Pin

48 Pin

68 Pin 64 Pin 48 Pin

8397BH 8397BH 8395BH B097BH 8097BH 8095BH 8797BH

NO ANALOG 8396BH

OTP

EPROM

8096BH

48,pln deVIces have four Analog Input pIns.
64-pin devices have all 48'pin device featur!,s plus the following:
Four additional Analog input channels
One additional quasi·bidirectional 8-bit parallel port
Four additional port 2 pins with multiplexed features
Timer 2 clock source pIn
Timer 2 reset pin
Two additional quasi·bidirectional port pins
68,pln devices have all 48-' and 64-pin features plus the following:
Oynamic buswidth sizing (8. or t 6-bit bus)
Dedicated System Clock Output (CLKOUT)
INST pin for memory expansion
Non·Maskable interrupt for debugging
Package DeSIgnators:
N=PLCC
C = CeramIc DIP
A=Ceramlc Pin Grid Array
P = Plastic DIP
R = Ceramic LCC
U = Shrink DIP
Prefix Designators:
•
T = Extended temperature
L = Extended temperature with 160 hours burn·in

2·81

68 Pin

64 Pin 48 Pin

8795BH 8797BH 8797BH

irltef

8X9XBH EXPRESS

DATA SHEET REVISION REVIEW
This data sheet (270433-003) is valid for de.vices
with a "D" at the end .of the topside tracking number. Data sheets are changed as new device information becomes available: Verify with your local
Intel sales office that you have the latest version
before finalizing a design or ordering devices.
The· following differences exist between this data
sheet and the previous version (-002).
1. All information except differences between the
standard and Express data sheets has been removed.
2. Prefix designators for Express products were
added to the packaging section.
Differences between the -002 and the -001 data
sheets.
1, TRLPv-Reset low to ports valid specification
added for clarity.

2-82

MCS®-96
809XJF,839XJF,879XJF
ADVANCED 16-BIT MICROCONTROLLER·
.WITH 8- OR 16-BIT EXTERNAL BUS
• 879XJF: an 809XJF with 16 Kbytes of On-Chip EPROM
• 839XJF: an 809XJF with 16 Kbytes of On-Chip ROM

•
•
•
•
•
•
•

232 Byte Register File
256 Bytes XRAM for Code
10-Blt A/D Converter with S/H
Five 8-Bit 110 Ports
20 Interrupt Sources
Pulse-Width Modulated Output
ROM/EPROM Lock

• Run-Time Programmable EPROM (OTP)

•
•
•
•
•
•
•
•

High Speed I/O Subsystem
Full Duplex Serial Port
Dedicated, Baud Rate Generator
6.25 J.Ls 16 x 16 Multiply
6.25 J.Ls 32/16 Divide
16-Bit Watchdog Timer
Four 16-Bit Software Timers
Two 16-Bit Counter ITimers

The MCS-96 family of 16-bit microcontroliers consists of many members, all of which are designed for highspeed cO,ntrol functions. The MCS-96 family members produced using Intel's HMOS-III process are described
in this data sheet.
The CPU supports bit, byte, and word operations. Thirty-two bit double-words are supported for a subset of the,
instruction set. With a 12 MHz input frequency the 8097 JF can do a i6-bit addition in 1.0 p.s and a16 x 16-bit
multiply or 32/16 divide in 6.25 p.s. Instruction execution times average 1 to 2 p.s in typical applications.
Four high-speed trigger inputs are provi,ded to record the times at which external events occur. Six high-speed
pulse generator outputs are provided to trigger external events at preset times. The high-speed output unit can
simultaneously perform software timer functions. Up to four 16-bit software timers can be in operation at once.
The on-chip AID converter includes a Sample and Hold, and converts up to 8 multiplexed analog input
channels to 10-bit digital values. With a 12 MHz crystal, each conversion takes 22 p.s.
Also provided on-chip are a serial port, a Watchdog Timer, and a pulse-width modulated output Signal.
POWER
VREF ANGND

•.-- -- --------- .
CONTROL
SIGNALS

l ~~~:
BUS

,~-~/

: PORT 4
I
I

,
•

PORT'O PORT 1

PORT2
AL T FUNCTIONS

HSI

HSO

Figure 1. MCS®·96 Bloc~ Diagram

2-83

270795-1

November 1990
Order Number. 270795-003

8X9XJF

OFFH

255,
POWER-DOWN
RAt.!

OFOH
OEFH

INTERNAL
REGISTER rilE
(RAM)

lAH

240
239

FFFFH
EXTERNAL MEMORY
OR I/o

19H

6000H

25
STACK POINTER

INTERNAL PROGRAM
STORAGE ROM/EPROM
OR
EXTERNAL MEMORY

STACK POINTER

18H

17H

PWM_CONTROL

5FFFH

2080H
ISH

1051

lOCI

ISH

1050

lOCO

14H
13H

2Q
RESERVED

RESERVED

12H

19
18

llH

SP_STAT

SP_CON

10H

10 PORT 2

OFH

, 10 PORT 1

10 PORT 1

BAUD_RATE

14'

OEH

10 PORT 0

ODH

TlMER2 (HI)

OCH

TlMER2, (LO)

OBH

TIMER 1 (HI)

2072H - 207FH

SIGNATURE WORD

2070H - 2071H

RESERVED

2030H - 20SFH

SECURITY KEY

2020H - 202FH

RESERVED

201CH - 201FH

SELF JUMP OPCODE (27H FEH)

201AH - 201BH

RESERVED

2019H

CHIP CONFIGURATION BYTE

2018H

RESERVED

2012H - 2017H

13
RESERVED

INTERRUPT VECTORS

OAH

TIMERI (LO)

WATCHDOG

09H

INLPENDING

INT_PENDING

08H

INT_MASK

07H

SBUF (RX)

SBUF (TX)

OSH

HSLSTATUS

HSO_COMMAND

05H

HSLTlME (HI)

HSO_ TIME (HI)

04H

HSLTlME (lO)

HSO_TIME (LO)

03H

AD_RESULT (HI)

HSLMODE

02H

AD_RESULT (lO)

AD_COMMAND

01H

RO (HI)

OOH

RO (lO)

(WHEN READ)

RE~ERVED

2000H

10
PORT 4

lFFFH

PORT 3

lFFEH

EXTERNAL MEMORY
OR I/O

01FFH

EXECUTABLE
INTERNAL RAM
(XRAM)

L-

0100H
INTERNAL RAM
REGISTER rilE
STACK POINTER
SPECIAL FUNCTION REGISTERS
(WHEN ACCESSED AS DATA MEMORY)

OOFFH

OOOOH

(WHEN WRITTEN)

270795-2

Figure 2. Memory Map

2-84

inter

8X9XJF

PACKAGING
The 8097JF is available in 64·pin and 68·pin packages, with and without on·chip ROM or EPROM. The 8097JF
numbering system is shown in Figure 3. Figures 4-6 show the pinouts for the 64· and 68·pin packages. The
64·pin version is offered in a Shrink·DIP package while the 68·pin versions come in a Plastic Leaded Chip
Carrier (PLCC).

MCS96 PACKAGING 8X9XJF
Factory
Masked ROM

I 64·Pin I 48·Pin
8397JF I 8397JF I
68·Pin

User Programmable

CPU

EPROM'
68·Pin

I 64·Pin I48·Pin

8097JF 18097JF

OTP

I64·Pin I48·Pin

68·Pin

I 64·Pin I48·Pin
8797JF18797JF I
68·Pin

Package Designators:
N = PLeC
C = Ceramic DIP
A = Ceramic Pin Grid Array
P = Plastic DIP
R = Ceramic LCC
U = Shrink DIP

Figure 3. The 809XJF Family Nomenclature
PLCC

PLCC

Description

PLCC

ACH7 IPO.7 IPMOD.3

AD6/P3.6

Description

Description
P1.6

ACH6/PO.6/PMOD.2

AD7/P3.7

P1.5

ACH2/PO.2

AD8/P4.0

HSO.1

: HSO.O

ACHO/PO.O

AD9/P4.1

ACH1/PO.1

AD10/P4.2

HSO.5/HSI.3

ACH3/PO.3

AD11/P4.3

HSO,4/HSI.2

NMI

AD12/P4,4

HSI.1

AD13/P4.5

HSI.O

VCC

AD14/P4.6

P1,4

VSS

AD15/P4.7

P1.3

XTAL1

T2CLK/P2.3

P1.2

XTAL2

READY

P1.1

CLKOUT

T2RST/P2,4

P1.0

SUSWIDTH

SHE/WRH

TXD/P2.0/PVERISALE

WR/WRL

INST

RXD/P2.1/PALE

ALE/ADV

.
PWM/P2.5/Pi50/SPROG

RESET

P2.7

EXTINTIP2.2/PROG

ADO/P3.0

VPD

AD1/P3.1

VSS

VREF

AD2/p3.2

HSO.3

ANGND

AD3/P3.3

HSO.2

AD4/P3,4

P2.6

AD5/P3.5

P1.7

r----'
--'--.

VPP
-_._-_.

----Figure 4. PLCC Function Pinout

2·85

ACH4/PO,4/PMOD.O
ACH5/PO.5/PMOD.1

8X9XJF

SDIP

Description

SDIP

1
2
3
4
S
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

EA
ACH3/PO.3
ACH1/PO.1
ACHO/PO.O
ACH2/PO.2
ACH6/PO.6/PMOD.2
ACH7/PO.7/PMOD.3
ACHS/PO.5/PMOD.1
ACH4/PO.4/PMOD.0
ANGND
VREF
VPD
EXINTIP2.2/PROG
RESET
RXD/P2.1/PALE
TXD/P2.0/PVERISALE
P1.0
P1.1
P1.2
P1.3
P1.4
HSI,O

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Description
HSI.1
HSO.4/HSI.2
HSO.5/HSI.3
HSO.O
HSO.1
P1.5
P1.6
P1.7
P2.6
HSO.2
HSO.3
Vss
Vpp
P2.7
PWM/P2.5/PDO/SP~OG

WR/WRL
BHE/WRH
T2RST/P2.4
READY
T2CLK/P2.3
AD15/P4.7
AD14/P4.6

SDIP

Description

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

AD13/P4.5
AD12/P4.4
AD11/P4.3
AD10/P4.2
AD9/P4.1
AD8/P4.0
AD7/P3.7
AD6/P3.6
AD5/P3.5
AD4/P3.4
AD3/P3.3
AD2/P3.2
AD1/P3.1
ADO/P3.0
RD
ALE/ADV
XTAL2
XTAL1
Vss
Vee

Figure 5. SDIP 8X97JF Pin Out

987.5.32
ACHS/PO 5

ACH4/PO.4

ANGND

VREF'

Vpo

EXTINT/PZ 2

RESET

RXD/P2,'
TXO/P2.0

l~D~~M~~~

--------(_

ADl/P3.!

MCS®-96
68 PIN
PLCC

AD4/P! "
A05/P3.5

ADS/Pl.e

52
51

HSI2/HS04

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD

Pl.!

ADO/P! 0

AD7/P;S.7
AOS/P4.0
A09/P4,1
A010/P4.2

AOI3/P4.S

T2CLK/P2 '.5

A014/P4.6

27 28 29 30 31 3Z 33 343536 37 38 39 40 41 4243

270795-3

Figure 6.. 68-Pin Package (PLCC - Top View)

270795-4

Figure 7. Shrink-DIP Package

2-86

inter

8X9XJF

PIN DESCRIPTtONS
Symbol

Name and Function

Vee

Main supply voltage' (5V).

Vss

DiQital circuit ground (OV). There are two Vss pins, both of which must be connected.

VPD

RAM standby supply voltage (5V). This voltage must be present during normal operation.
In a Power Down condition (i.e. Vee drops to zero), if RESET is activate,d before Vee drops
below spec and V PD continues to be held within spec., the top 16 bytes in the Register File
will retain their contents. RESET must be held low during the Power Down and should not
be brought high until Vee is within spec and the oscillator has stabilized.

VREF

Reference vQltage for' the A/D converter (5V). VREF is also the supply voltage to the
analog portion of the AID converter and the logic used to re~d Port O.

ANGND

Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·

Vpp

, Programming voltage for the EPROM pevices. It should be + 12. 75V for programming and
will float to 5V otherwise. It should not be above Vee for ROM or CPU devices. This pin
must be left floating in the application circuit for EPROM devices.

XTAL1

Input of .the oscillator inverter and of the internal clock generator.

XTAL2

Output of the oscillator inverter.

CLKOUT*

Output of. the internal clock generator. The frequency of CLKOUT is % the oscillator
frequency. It has a 33% duty cycle.

RESET

Reset inPut to the chip. Input low for a minimum of 10 XTAL 1 cycles to reset the chip. The
subsequent low-to-high transition re-synchronizes CLKOUT and commences a 10-statetime sequence in which the PSW is cleared, a byte read from 2018H .Ioads CCR, and a
jump to location 20BOH is executed. Input high for normal operati.on. RESET has an
internal pull up.

BUSWIDTH*

Input for bus width selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8bit cycle occurs. If CCR bit 1 is a 0, the bus is always an B-bit bus. If this pin is left
unconnected, it will rise to Vee.

NMI*

A positive transition causes a vector to external memory location OOOOH. External memory
from OOH through OFFH is reserved for Intel development systems.

INST*

Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle.

ALE/ADV

Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 5FFF to be directed to on-chip ROM/EPROM. EA .
equal to a TTL-low causes accesses to these locations to be directed to off-chip memory.
EA == + 12.75V causes execution to begin in the Programming Mode. EA has an internal
. pulldown, so it goes to 0 unless driven otherwise.
.
,
Address Latch Enable or Address Valid output, as selected by CCA. Both pin options
provide latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ADV can be used as a chip select for
a single external RAM memory. ALE/ ADV is activated only during external memory
accesses.

'Not avaIlable on Shrink-DIP package

2-B7

8X9XJF

PIN DESCRIPTIONS (Continued)
Symbol

Name and Function

Read signal output to external memory. RD is activated only during external memory
reads.

WR/WRL

Write and Write Low output to external memory, as selected by theCCR. WR will go
low for every external write, while WRL will go low only for external writes where an
even byte is being written. WR/WRL is activated only during external memory writes.

SHE/WRH

Sus High Enable or Write High output to external memory, as selected by the CCR.
SHE = 0 selects the bank of memory that is connected to the high byte of the data
bus. AO = 0 selects the bank of memory that is connected to the low byte of the
data bus. Thus accesses to a 16-bit wide memory can be to the low byte only tAO =
0, SHE = 1), to the high byte only (AO = 1, SHE = 0), or both bytes (AO = 0, SHE
= 0). If the WRH function is selected, the pin will go low if the bus cycle is writing to
an odd memory location.

READY

Ready input to lengt~en external melT)ory cycles, for interfacing to slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller
goes into a wait mode until the next positive transition in CLKOUT occurs with
READY high. The bus cycle can be lengthened by up to 1 JLs. When the external
memory is not being used, READY has no effect. Internal control of the number of
wait states inserted into a bus cycle held not ready is available through configuration
of CCA. READY has a weak internal pullup, so it goes to 1 unless externally pulled
low.

HSI

Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2, and
HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are
also used as inputs by EPROM devices in Programming Mode.

HSO

Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1,
HSO.2, HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with
theHSI Unit.

PortO

8-bit high impedance input-only port. These pins can be used as digital inputs and/or
as analog inputs to the on-chip A/D converter. These pins are also a mode input to
EPROM devices in the Programming Mode.

Port 1

8-bit ql,lasi-bidirectionall/O port.

Port 2

8-bit multi-functional port. Six of its pins are shared with other fl,lnctions in the
8096JF, the remaining 2 are quasi-bidirectional, These pins are also used to input
and output control signals on EPROM devices in Programming Mode.

Ports 3 and 4

8-bit bi-directionalllO ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups. Ports 3 and 4 are
also used as a command, a,ddress and data path by EPROM devices operating in the
Programming Mode. When used as ports, pullups to Vee may be needed.

2-88

8X9XJF

AID Result LO (02H)

-: 1

AID

AID Command (02H)

11
1

CHANNEL NUMBER

+::
-

STATUS:
0 = A/O CURRENTLY IDLE
1 = CONVERSION IN PROCESS

3 -

CHANNEL SELECTS WHICH Of THE 8
ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL roRM.
GO INDICATES WHEN THE CONVERSION IS TO
BE INITIATED(GO = 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).

270795-9
-_6 }
7

A/O RESULT:
LEAST SIGNIFICANT 2 BITS

SPCON/SPSTAT(11H)

270795-5

';}
W
R
I 2 -

. HSI_Mode (03H)

I 5 41 3

1'1 0 1

HSI.O MODE
HSI.l MODE
HSI.2 MODE

REN

4 -

TBB

PROGRAMS THE 9TH DATA BIT

5 -

! rs -

IS THE TRANSMIT INTERRUPT FLAG

IS THE RECEIVE INTERRUPT FLAG

f-;" -

RBS

......

HSI.3 MODE
/

WHERE EACH 2 - BIT MODE CONTROL FIELD
DEFINES ONE OF 4 POSSIBLE MODES:
00
01
10
11

IS THE 9TH DATA RECEIVED
(IF NOT PARITY)
RPE IS THE PARITY ERROR INDICATOR
. (If PARITY ACTIVE)

Baud Rate Calculations
Using XTAL 1:

Mod

o·

e .

Baud ~ XTAL !frequency • B '" 0
Rate
4'(8 + 1)
•

Othe . Baud
rs. Rate

HSO Command (06H)

XTAL 1 frequency
64* (B + 1)

Using T2CLK:
- T2CLK frequency. B
ModeO.• Baud
Rate B
•

CHANNEL:
0-5 HSO.O - HSO.5
0]6
7
8-B
E
F

ENABLES THE RECEIVE FUNCTION

270795-10

8 POSITIVE TRANSITIONS
EACH POSITIVE TRANSITION
EACH NEGATIVE TRANSITION.
EVERY TRANSITION
(POSITIVE AND NEGATIVE)

270795-6

BIT:

BIT1, BITO SPECIFY THE NODE
OO=MODEO
10=MODE2
01 = MODE 1 11 = MODE 3
PEN ENABLE THE PARITY FUNCTION

r2-

Baud

Others: Rate

HSO.O AND HSO.l
HSO.2 AND HSO.3
SOFTWARE TIMERS
RESET TlMER2
START A / 0 CONVERSION

'* 0

T2CLK frequency
=

16'8

=1=

Note that B cannot equal 0, except when using XTAL 1 In other

than Modo O.

INTERRUPT / NO INTERRUPT

SET /CLEAR

TIMER 2/TIMER 1

Chip Configuration
1.rl1.r-l""'~""''''..t.,.I0 CHIP CONfiGURATION REGISTER

RESERVED (Set to 1 for
compatibility with future

. 270795-7

ports)
BUS WIDTH SELECT
(16-BIT Bus/s-BIT BUS)
WRITE STROBE MODE SELECT
(ViR AND
I
AND Wlrn)

HSLStatus (06H)

am: m

ADDRESS VALID STROBE SELECT
(ALEi ADV)
(IRCO) }INTERNAL READY CONTROL

HSI.O STATUS

'------(IRC1). MODE

'----HSI.l STATUS

(LOCO) )
' - - - - - - - ( L O C 1 ) PROGRAM LOCK MODE

' - - - - - - - H S I . 2 STATUS
' - - - - - - - - - H S I . 3 STATUS

270795-11

WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCUR EO ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.

270795-8

2-89

intJ

8X9XJF
Interrupt Pending/Mask Register
(LOCATION 98H, 09H)

17161514131211101

II i

~:Z!~~::S~:E"

L -_ _ _ _ _ _ _

HSO EVEN;
HSI BIT 0
SOFTWARE TIMERS
SERIAL I/O

' - - - - - - - - - - - EXTERNAL INTERRUPT

270795-12

P5W Register

1050 (15H)

lOCO (15H)
HSI.O INPUT ENABLE /DISABLE

HSO.O CURRENT STATE

TIMER 2 RESET EACH WRITE

HSO.l CURRENT STATE

HSI.l INPUT ENABLE / DISABLE

HSO.2 CURRENT STATE

TIMER 2 EXTERNAL RESET ENABLE / DISABLE

HSO.3 CURRENT STATE

HSI.2 INPUT ENABLE / DISABLE

HSO.4 CURRENT STATE

TIMER 2 RESET SOURCE HSI.O / T2RST

HSO.5 CURRENT STATE

HSI.3 INPUT ENABLE / DISABLE

CAM Q.!! HOLDING REGISTER IS FULL

TIMER 2 CLOCK SOURCE HSl.l /T2CLK

HSO HOLDING REGISTER IS FULL

270795-13

270795-15

lOCO (15H)

IOC1 (16H)

T2RST - - 0 • - . IOCO.5
.
HSI.O

~~---- T2

SELECT PWM / SELECT P2.5
RESET

EXTERNAL INTERRUPT ACH7 / EXTINT

• -.10. CO.3
; _. 10CO.O

TIMER 1 OVERFLOW INTERRUPT ENABLE / DISABLE

~------- HSI

TIMER 2 OVERFLOW INTERRUPT ENABLE / DISABLE

• _. IOCO.2

HSO.4 OUTPUT ENABLE / DISABLE

..c~------- HSI

HSI.l
~
T2CLK - - 0 . -. IOCO.7

SELECT TXO / SELECT P2.0

m.4ER2
CLOCK

HSO.5 OUTPUT ENABLE / DISABLE

• _. 10COA

~------- HSI

HSI.2 - - 0

• -. IOCO.6

~-------- HSI

HSI;3 - - 0

270795-14

2-90

HSI INTERRUPT
FIFO FULL / "'HO"'L""O"'"IN""G'""'R"'E""GI""ST""E""R-;L""'O";";AO""'E"'O
270795-16

inter

8X9XJF

Vector Location
Vector

Software Trap
Extint
Serial Port
Software
Timers
HSI,O
High Speed
Outputs
HSI Data
Available
, AID Conversion
Complete
Timer Overflow

IOS1'(16H)

Priority

(High
Byte)

(Low
Byte)

2011H
200FH
200DH
200BH

2010H Not Applicable
200EH 7 (Highest)
200CH
6
5
200AH

SOFTWARE TIMER 1 EXPIRED

2009H
2007H

2008H
2006H

4
3

TIMER 1 HAS OVERFLOW

2005H

2004H

2003H

2002H

2001H

2000H

o (Lowest)

SOFTWARE TIMER 0 EXPIRED

SOFTWARE

TI~ER

2 EXPIRED

SOFTWARE TIMER 3 EXPIRED
TIMER 2 HAS OVERFLOW

HSI FIFO IS FULL
HSI HOLDING, REGISTER DATA AVAILABLE
270795-17

2-91

inter

8X9XJF

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature .......... -40°C to

+ 70°C
+ 150°C

Voltage from EA or Vpp
to VSS or ANGND ............ -O.3Vto

+ 13.0V

Voltage from Any Other Pin to
VSS or ANGND .............. -O.3V to

+ 7.0V·

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. It is valid for the devices indicated in
the revision history. The specifications are subject to
change without notice.
.

Ambient Temperature Under Bias .... O°C to

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond 'the
"Operating Conditions~' is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Average Output Current from Any Pin ....... 10 mA
Power Dissipation .......................... 1.5W
'This includes Vpp on ROM and CPU only devices.

OPERATING CONDITIONS
(All characteristics specified in this data sheet apply to these operating conditions unless otherwise noted.)
Symbol

Parameter

Min

Max

Units

Ambient Temperature Under Bias

+70

Vee

Digital Supply Voltage

4.50

5.50

VREF

Analog Supply Voltage

4.50

5.50

lose

Oscillator Frequency

6.0

MHz

VPD

Power-Down Supply Voltage

4.50

5.50

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. CHARACTERISTICS
Symbol

Parameter

lee

Vee Supply Current (O'C ,,; TA ,,; 70'C)

lecl

Vee Supply Current (TA

IpD

VPD Supply Current

IREF

VREF Supply Current

VIL

Input Low Voltage

VIH

Min

= 70'C)

Max

Units

300

245

Test Conditions
All Outputs
Disconnected.
Normal operation
and Power-Down.

-0.3

+0.8

Input High Voltage (Except RESET, NMI, XTAL 1)

2.0

Vee +0.5

VIHl

Input High Voltage, RESET Rising

2.4

Vee +0.5

VIH2

Input High Voltage, RESET Falling (Hysteresis)

2.1

Vee +0.5

VIH3

Input High Voltage, NMI(4), XTAL 1

2.2

Vee +0.5

Input Leakage Current to each pin 01 HSI, P3, P4, and to P2.1.

±10

p.A

Yin

IUl

D.C. Input Leakage Current to each pin 01 PO

p.A

Yin

IIH

Input High Current to EA

IlL

Input Low Current to each pin 01 P1,
and to P2.6, P2.7.

100

p.A

-125

p.A

= OtoVec
= OtoVee
VIH = 2.4V
VIL = 0.45V

IILl

Input Low Current to RESET

-2

Vil

IIl2

Input Low Current P2.2, P2.3, P2.4, READY, BUSWIDTH

-50

p.A

Vil

VOL o '

Output Low Voltage on Quasi-Bidirectional
port pins and P3, P4 when used as ports

0.45

IOL = 0.8 mA
(Note 1)

.vOll

Output Low Voltage on Quasi-Bidirectional
port pins and P3, P4 when used as ports

0.75

IOL = 2.0 mA
(Notes 1, 2, 3)

Output Low Voltage on Standard Output
pins, RESET and Bus/Control Pins

0.45

IOL'= 2.0 mA
(Notes 1, 2, 3)

VOL2

-0.25

2-92

= 0.45V
= 0.45V

8X9XJF

D.C. CHARACTERISTICS (Continued)
Symbol

Parameter

Min

VOH

Output High Voltage on Quasi-Bidirectional
pins

2.4

IOH = -20,...A
(Note 1)

VOH1

Output High Voltage on Standard Output
pins and Bus/Control pins
.

2.4

IOH = -200,...A
(Note 1)

IOH3

Output High Current on RESET

-50

Pin Capacitance (Any Pin to Vss)

Max

Units

Test Conditions

,...A

VOH = 2.4V

fTEST = 1.0 MHz

NOTES:
1. Quasi-bidirectional pins include those on P1, for P2.6 and P2.7. Standard Output Pins include TXD, RXD (Mode 0 only),
PWM, and HSO pins. Bus/Control pins include CLKOUT, ALE, BHE, RD, WR, INST and ADO-15.
2. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V.
IOL on quasi-bidirectional pins and Ports 3 and 4 when used as ports: 4.0 mA
IOL on standard output pins and RESET: 8.0 mA
IOL 6n Bus/Control pins: 2.0 mA
3.During normal (non-transient) operation the following limits apply:
TOlaiioL on Port 1 must not exceed 8.0 mAo
Total IOL on P2.0, P2.6, RESET and all HSO pins must not exceed 15 mAo
TotalloL on Port 3 must not exceed 10 mA.
TotaiiOL on P2.5, P2.7, and Port 4 must not exceed 20 mA.

A.C. CHARACTERISTICS
Test Conditions: Load Capacitance on Output Pins = 80 pF

TIMING REQUIREMENTS (Other system components must meet these specs)

Symbol

Parameter

TCLYX(3)

READY Hold after CLKOUT Edge

TLLYV

End of ALE/ ADV to READY Valid

TLLYH

End of ALE/ ADV to READY High

TYLYH

Non-Ready Time

TAVDV(2)
TRLDV

M'jn

Max

0(1)

Units
ns

2Tosc-70

4Tosc-80

1000

Address Valid to Input Data Valid

5Tosc -120(4)

RD Active to Input Data Valid

3Tosc -1 00(4)

2Tosc+40

TRHDX

Data Hold after RD Inactive

TRHDZ

RD Inactive to Input Data Float

TAVGV(2,3)

Address Valid to BUSWIDTH Valid

TLLGX(3)

BUSWIDTH Hold after ALE/ ADV Low

TLLGv(3)

ALE/ ADV Low to BUSWIDTH Valid

TRLPV

Reset Low to Ports Valid

ns
Tosc-25
2Tosc -125

Tosc +40

ns
ns
ns

Tosc -100

10Tosc

NOTES:
1. If the 64-pin device is being used then this timing can be generated by assuming that the CLKOUT falling edge has
occurred at 2Tosc+55 (TLLCH(max) + TCHCL(max)) after the falling edge of ALE.
2. The term "Address Valid" applies to ADO-15, BHE and INST.
3. Pins not bonded out on 64-pin devices.
4. If wait states are used, add 3Tosc • N where N = number of wait states.

inter

8X9XJF

TIMING RESPONSES (MCS·96 devices meet these specs.)

Parameter

Symbol
FXTAL

' Oscillator Frequency

Min

Max

Units

6.0

12.0

MHz

166

120

Tosc

Oscillator Period

TOHCH(3)

XT AL 1 Rising Edge to Clockout Rising Edge

TCHCH(3)

CLKOUT Period

3Tosc(2)

3Tosb(2)

TCHCL(3)

CLKOUT High Time

Tosc-35

Tosc+ 10

TCLLH(3)

CLKOUT Low to ALE High

-30

+ 15

TLLCH(3)

ALE/ ADV Low to CLKOUT High

Tosc-25

Tosc+45

hHLL

ALE/ ADV High Time

Tosc-30

Tosc+35(4)

TAVLL(5)

Address Setup to End of ALE/ ADV

Tosc-50

TRLAZ(6)

RD or WR Low to Address Float

Typ.

TLLRL

End of ALE/ ADV to RD or WR Active

Tosc-40

ns'
10

TLLAX(6)

Address Hold after End of ALE/ ADV

Tosc-40

TWLWH

WR Pulse Width

3Tosc-35(1)

TaVWH

Output Data Valid to End of WR/WRLlWRH

3Tosc-60(1)

TWHax

Output Data Hold after WR/WRL/WRH .

Tosc-' 50

TWHLH

End of WR/WRL/WRH to ALE/ ADV High

Tosc-75

TRLRH

RD Pulse Width

3Tosc-30(1)

TRHLH

End of RD to ALE/ ADV High

Tosc-45

TCLLL(3)

CLOCKOUT Low to ALE/ ADV Low

Tosc-40

Tosc+35

TRHSX(3)

RD High to INST, SHE, AD8·15 Inactive

Tosc-25

Tosc+30

TWHSX(3)

WR High to INST, SHE, AD8·15 Inactive

Tosc-50

Tosc+ 100

THLHH

WRL, WRH Low to WRL, WRH High

2Tosc-35

2Tosc+40

hLHL

ALE/ ADVlow to WRL, WRH Low

2Tosc-30

2Tosc+ 55

TaVHL

Output Data Valid to WRL, WRH Low

Tosc-60

NOTES:

1.lf more than one wait state is desired, add 3Tosc for each additional wait state.
,
2. CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3Tosc ± 10 ns if Tosc is constant and
the rise and fall times on XTAL 1 are less tnan 10 ns.
3. CLKOUT, INST, and SHE pins not bonded out on 64·lead package.
4. Max spec applies only to ALE. Min spec applies to both ALE and ADV.
5. The term "Address Valid" applies to ADO-15, SHE and INST.
6. The term" Address" in this specification applies to ADO-7 for a·bit cycles, and ADO-15 for 16·bit cycles.

2·94

inter

8X9XJF

WAVEFORM

XTAL1
CLOCKOUT·
READY
,
'.. _--------

'~-.

BHE. INST·

~----~--~~----~----------~--~~----------.--.
TAVLL.J ~I.---TWLWH ~

AD8-15 ~(~1L)----d

TXLXH

Serial Port Clock Falling Edge to Rising Edge

TOVXH

Output Data Setup to Clock Rising Edge

TXHOX

Output Data Hold After Clock Rising Edge

TXHOV'

Next Output Data Valid After Clock Rising Edge

TOVXH

Input Data Setup to Clock Rising Edge

TXHDX

Input Data Hold After Clock Rising Edge

TXHQZ

Last Clock Rising to Output Float

Units

Max
.

8Tose
4Tosc - 50

4Tose + 50

3Tosc

2Tose - 70

...

2Tose +50

2Tose +200

ns
ns

5Tose
----_.

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-5HIFT REGISTER MODE
r-------------~------------~----------------------------------.

r-TXLXl.-j'

TXD - -

-U- .. -U- ---U- _··U ---U- _. -U- _. -U- _.-U-

TQVXH-j

1-..

TXLXH..J

(O~;)-<~x:::r=x

r' ,
X

I- -I
-".c,-:--:::",r---"",:-:--::", .

TOVXH-j

TXHOV

r-TXHOX

..J r-TXHOX

TXHQZ..J

I
>-

RXD --""CCC-.-:::"T-- ----,.rc: -.C"'.I -----'L": .-.(IN) ~_--''\.::.=.:'''' _ _~'''-:. :.C:__'-"'L __ --' "~_:C':::I"" ___ ~'''''--~·''-- ... _---''.~:=CI'- __ ~. 'L:.==r ...__-"c=CI .... ---.J·'L.::::.::I ...~ __
270795-21

2-96

8X9XJF

EXTERNAL CLOCK DRIVE
Symbol

Par~meter

Min

Max

Units

1/TOLOL

Oscillator Frequency

MHz

TOHOX

High Time

25
30

TOLOX

Low Time

TOLOH

Rise Time

ns
ns

TOHOL

Fall Time

EXTERNAL CLOCK DRIVE WAVEFORMS

270795-22

.An external oscillator may encounter. as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.

A.C. TESTING INPUT, OUTPUT WAVEFORM

2 . 4 V 2.0> TEST POINTS
0.45

~~8

FLOAT WAVEFORM

< O~.x=.
2.0

270795-24
For Timing Purposes a Port Pin IS no Longer Floating when a
200 mV change from Load Voltage Occurs, and Begins to Float
when a 200 mV change from the Loaded VOHIVOL Level occurs
IOLlloH;;' ± 15 mA.

270795-23
A.G. Testing Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".

Minimum Hardware Configuration Circuits

270795-26

270795-25

2-97

8X9XJF

AID CONVERTER SPECIFICATIONS
The absolute conversion accuracy is dependent on the accuracy of VREF.
Test Conditions: VREF

5.12V, AGND

Parameter

Vss

Typical'

Resolution

OV
Minimum

Maximum

Units"

1024
10

Levels
Bits

±4

LSBs

Absolute Error
Full Scale Error
Zero Offset Error

-0.5 ±0.5

LSBs

±0.5

LSBs
0

±4

LSBs

> -1

LSBs

±1

LSBs

Non-Linearity
Differential Non-Linearity
Channel-to-Channel Matching
Repeatability

±0.25

LSBs

Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity

0.009
0.009
0.009

LSBrC
LSBrC
LSBrC
--60

Off Isolation
Feedthrough

-60

Vee Power Supply Rejection

-60

Notes

Input Resistance

1,3

3.0

Sample Delay

3Tosc

3Tosc + 50

Sample Time

12Tosc - 50

12Tosc + 50

D.C. Input Leakage

Sampling Capacitor

NOTES:
• These values are expected for most devices at 25°C.
•• An "LSB", as used here, is defined in the glossary which follows and has a value of approximately 5 mV.
1. DC to 100 KHz.
2. For starting the AID with an HSO Command.
3. Multiplexer Break-Belore-Make Guaranteed.

2-98

intJ

8X9XJF

OTP EPROM SPECIFICATIONS
A.C. EPROM PROGRAMMING CHARACTERISTICS
Auto, Slave Mode Operating Conditions: Load Capacitance = 150 pF, T A = ?5°C ± 5°C, Vee, Vpo, VREF =
5.0V ± 0.5V, Vss, AGND = OV, Vpp = 12.75V ± 0.25V, EA = 11V ± 2.0V, fose = 6.0 MHz
Run-time Operating Conditions: Fose = 6.0 MHz to 12.0 MHz, Vee, Vpo, VREF = 5V ± 0.5V, TA = 25°C to
± 5°C and Vpp = 12.75V ± 0.25V. For run·time programming over a full operating range, contact the factory.

Symbol

Parameter

Min

Max

Units

TAVLL

ADDRESS/COMMAND Valid to PALE Low.

Tose

TLLAX

ADDRESS/COMMAND Hold After PALE Low

Tose

TOVPL

Output Data Setup Before PROG Low

Tose

TpLOX

Data Hold After PROG Falling

Tose

TLLLH

PALE PulseWid,th

180

TpLPH

PROG Pulse Width

250 T08e

Tose
100}-tS +
144 Tose

TLHPL

PALE High to 'P'ROO Low

250

TpHLL

PROG High to Next PALE Low

600

TpHOX

Data Hold After PROG High

Tose

TpHVV

PROG High to PVER/PDO Valid

500

Tose

TLLVH

PAtE Ldwto PVER/PDO High

100

Tose

TpLOY

PROG Low to VERIFICATION/DUMP Data Valid

100

Tose

TSHLL

RESET High to First PALE Low (not shown)

2000

Tose

Tose
Tose

D.C. EPROM PROGRAMMING CHARACTERISTICS
Symbol

Parameter

Min

lpp

Vpp Supply Current (Whenever Programming)

Vpp

Programming Supply Voltage

VEA

EA Programming Voltage

I
I

Max
100 .

Units
mA

12.75 ±0.25

11 ±2.0

NOTE:
Vpp must b~ within.1V of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground (or Vss) while
Vee> 4,5V.

2-99

8X9X.:JF

WAVEFORM-EPROM PROGRAMMING (OTP)

PORTS 3,4

PALE--_
PROG ---+---..;;;.;;.;..~

PVER

__
_..I
VALID

VALID

PDO

__
_..I
VALID

VALID
270795-27

REVISION HISTORY

FUNCTIONAL DEVIATIONS

This data sheet (270795-003) is valid for devices
with an "A" at the end of the topside tracking number. Data sheets are changed as new device information becomes available. Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices.

Devices covered by this data sheet (see ReviSion
History) have the following errata.
1. INDEXED, 30PERANp.MUlTIPlY
The displacement portion of an indexed, three operand (byte or word) multiply may not be in the
. range of 200H thru 17FFH inclusive. If you must
use these displacements, execute an indexed,
two operand multiply and a move if necessary.
2. 8X9XJF HIGH SPEED INPUTS
The High Speed Input (HSI) peripheral on the
"JF" devices contain three deviations' from the
original 8X9XBH specification. The first changes
'the resolution description. The second deviation
describes skipped time tag recording. The third
modifies theeventl entry loading algorithm.
NOTE:
"Events" are defined as one or more pin transitions. "Entries" are defined as the recording of
one or more events. The FIFO is defined as empty even if there is an entry in the Holding Register.

The following differences exist between this data
sheet and the previous version (-002).
1. The reserved location section and th.e power supply sequencing section has been deleted. This
information is in the Hardware Design Informa~
tion ..
2. The Software Reset Timing bug was removed
from the Functional DeViations. The RESET pin
will pull down for at least 2 states if a software
reset or watchdog timer overflow occurs.
Differences between the -002 and -001 data sheets.
1. The TllGV spec has been changed from Max ±
Tose - 75 ns to Max = Tose = 100 ns.
2. The TCllH spec has been changed from Min =
-20 ns and Max = +25 ns to Min = -30 ns
and Max = + 15 ns.
.
3. The TXHQX spec has been changed from Min =
2 Tose - 50nsto 2Tose - 70 ns.
4, The TOlOX spec has been changed from Min =
25 ns to Min = 30 ns.
5. Added "20" recommendation for reserved address 2019H to EPROM specification.
6. Added functional deviations.

2·100

inter

8X9XJF

A. The eight state HSI resolution changes to nine
states. Events occurring on the same pin more
frequently than once every nine state times
may be lost. Selecting the Eight Positive Transition Mode limits the resolution to no more
than eight positive transitions per sixteen state
times. Transitions may n6t occur more quickly
than once per state time. This means transitions in one state time must stabilize and
hold a logic level for at least one state time
before any further transitions occur.
B. A mismatch between the nine state HSI resolution and the eight state hardware timer causes one time-tag value to be skipped every nine
timer counts. The effect on FIFO entries is to
receive l:! time tag one count later than expected every nine counts.

C. The HSI pins. are sampled during an internal
timing phase. This phase, after some propagation time, appears externally as CLKOUT. If
the first event to be recorded into an empty
FIFO occurs during this CLKOUT period, and
the second event' occurs after that period, the
events will be entered separately with timetags at least one count apart. If the second
event enters the FIFO coincident with the
"skipped" time-tag situation (see item 2
above) the time-tags will be at least two
counts apart. If both events occur within the
period of this internal phase, there will be only
one entry recording both events on one timetag.
3. RESERVED LOCATION 2019H
The 1990 Architectural Overview recommends
that reserved location 2019H be filled with hex
value FFH. The recommendation is now to fill
2019H with hElx value 20H.

2-101

infel®
MCS®-96
809XJF/839XJF1879XJF
Express
•

Extended Temperature Range

•

Burn-In

(-40°C.to +8$OC)
The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®-96 family of
microcontrollers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includesthe commercial standard temperature range with burn-in, and an extended
temperature range with or without burn-in.
With the commercial standard temperature range operational 9haracteristics are guaranteed over the temperature range of O°C to +70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to· + 85°C.
The optional burn-in is dynamic, for a minimum time of 160 hours at 125°C with Vee
guidelines in MIL-STD-883, Method 1015 ..

5.5V

± 0.5V, following

Package types and EXPRESS versi9ns are identified by a one- or two-letter prefix to the device number. The
prefixes are listed in Table 1.
This data sheet specifies the parameters for the extended temperature rangEl option. The commercial temperature range data sheets are applicable otherwise.

POWER
VREF ANGND

CONTROL
SIGNALS

-----16

.. --PORTO PORT 1

PORT 2
ALT FUNCTIONS

HSI

HSO
270796-1

MCS®-96 Block Diagram

2-102

October 1989
Order Number: 270796-001

8X9XJF EXPRESS

ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature .•.....•.. - 40·C to

+ 85·C
+ 150·C

Voltage from Vpp or EA
to Vss or.ANGND ......••.•.. -O.3V to

+ 13.0V

Voltage from Any Other Pin to
Vss or ANGND .............. -O.3V to

+ 7.0V·

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.

Ambient Temperature Under Bias. - 40·C to

Average Output Current from Any Pin ...•... 10 rnA
Power Dissipation .......•..............•... 1.5W
"This includes Vpp on ROM and CPU devices.

OPERATING CONDITIONS
Parameter

Min

. Max

Units

Symbol

Ambient Temperature Under Bias

-40

+85

°C

Vee

Digital Supply Voltage

4.50

5.50

VREF

Analog Supply Voltage

4.50

5.50

fose

Oscillator Frequeno;;y

6.0

MHz

VPO

Power-Down Supply Voltage

4.50

5.50

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. CHARACTERISTICS (Under listed operating conditions)
".
Symbol

Max

Units

lee

Vee Supply Current( - 40°C,,; TA ,,; + 85°C)

Parameter

Min

330

leel

Vee Supply Current(TA = + 85°C)

245

Ipo

VPO Supply Current

IREF

VREF Supply Current

Test Conditions
All Outputs
Disconnected.
Normal operation
and Power-Down.

VIL

Input Low Voltage (Except RESET)

-0.3

+0.8

VILl

Input Low Voltage, RESET

-0.3

+0.7

VIH

Input High Voltage (Except RESET, NMI, XTAL 1)

2.0

Vee +0.5

VIHl

Input High Voltage, RESET Rising

2.4

Vee +0.5

VIH2

Input High Voltage, RESET Falling Hysteresis

2.1

. Vee +0.5

VIH3

Input High Voltage, NMI, XTAL 1

2.3

Vee +0.5

III

Input Leakage C\lrrent to each pin of HSI, P3, P4, and to P2.1.

±10

",A

Yin = OtoVcc

ILil

D.C. Input Leakage Current to each pin of PO

",A

Itin = Oto Vee'

IIH

Input High Current to EA

IlL

Input Low Current to each pin of P1,
and to P2.6, P2.7.

IILl

Input Low Current to RESET

100
-150
-0.25

-2

",A
. ",A

Viti =2.4V
VIL = 0.45V

VIL = 0.45V

. -50

",A

VIL= 0.45V

IIL2

Input Low Current P2.2, P2.3, P2.4, READY, BUSWIDTH

VOL

Output Low Voltage on Quasi-Bidirectional
port pins and P3, P4 when used as ports

0.45

IOL = 0.8mA
(Note 1)

VOL1

Output Low Voltage on Quasi-Bidirectional
port pins and P3, P4 when used as ports

0.75

IOL = 2.0mA
(Notes 1, 2, 3)

VOL2

Output Low Voltage on Standard Output
pins, RESET and Bus/Control Pins

0.45

IOL = 2.0mA
(Notes 1, 2, 3)

2-103

intJ

8X9XJF EXPRESS

D.C. CHARACTERISTICS (Continued)
Symbol

'Parameter

Min
'2A

VOH

Output High Voltage on Quasi-Bidirectional
pins

VOH1

Output High Voltage on Standara Output
pins and Bus/Control pins

IOH3

Output High Current on RESET

-50

Pin Capacitance (Any Pin to Vss)

Max

Units

Test Conditions'

IOH = -20 ",A
(Note 1)

tOH = -200 ",A
(Note 1)

",A

VOH = 2AV

!TEST = 1.0 MHz

NOTES:
1. Quasi-bidirectional pins include ,those on P1, for P2.6 and P2. 7. Standard Output Pins include TXD, RXD (Mode 0 only),
PWM, and HSO pins. Bus/Control pins include CLKOUT, ALE, BHE, RD, WR, INST and ADO-15.
2. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V.
IOl on quasi-bidirectional pins and Ports 3 and 4 when used as ports: 4.0 mA
IOl on standard output pins and RESET: 8.0 mA
.
tOl on Bus/Control pins: 2.0 mA
3.During normal (non-transient) operation the following limits apply:
Total IOl on Port 1 must not exceed 8.0.rnA.
TotallOl on P2.0, P2.6, RESET and allHSO pins must not exceed 15 mA.
Total IOl on Port 3 must not exceed 10 mA.
.
Total IOl on P2.5, P27, and Port 4 must not exceed 20 mA.

A.C. CHARACTERISTICS (Under listed operating conditions)
Test Conditions: Load Capacitance on Output Pins = 80 pF
'
Oscillator Frequency = 10 MHz
TIMING REQUIREMENTS (Other system components must meet these specs)
Symbol

Parameter

Min

TCLYX(3)

READY Hold after CLKOUT Edge·

TLLYV

End of ALE/ ADV to READY Valid
End of ALE/ ADV to RJ:ADY High

TLLYH
TYLYH

. Units

Max

0(1)

2Tosc+40

Non-Ready Time

ns
2Tosc~70

4Tosc-80

1000

TAVDV(2)

Address Valid to Input Data Valid

5Tosc-120

TRLDV

RD Active to Input Data Valid

3Tosc-100

TRHDX

Dat1!- Hold after RD Inactive

TRHDZ

RD Inactive to Input Data Float

TAVGV(2,3)

Address Valid to BUSWIDTH Valid

TLLGX(3)

BUSWIDTH Hold after ALE/ ADV Low

TLLGV(3)

ALE/ ADV Low to BUSWIDTH Valid

ns
Tosc-::-25
2 Tosc -125

ns
ns
ns

Tosc +40
Tosc -:-75

NOTES:,
.,
.
1, If the 48-pin device is being used then this timing can be generated by assuming that the CLKOUT falling edge has
occurred at 2Tosc+55 (TLLCH(max) + TCHCL(max)) after the falling edge of ALE.
2. The term "Address Valid" applies to ADO-15, BHE and IN~n.
3. Pins not bonded out on 64-pin devices.

2-104

8X9XJF EXPRESS

A.C. CHARACTERISTICS (Continued)
TIMING RESPONSES (MCS-96 devices meet these specs)
Symbol

Parameter

Min

Max

Units

FXTAL

Oscillator Frequency

6.0

12.0

MHz

Tosc

Oscillii\tor Period

166

0(4)

120(4)

TCHCH(3)

CLKOUT Period(3)

3Tosc(2)

Tosc-35

Tosc+ 10

-20

+25

.. TOHCH

XTAL 1 Rising Edge to Clockout Rising Edge

TCHCL(3)

CLKOUT High Time

TCLLH(3)

CLKOUT Low to ALE High

TLLCH(3)

ALEI ADV Low to CLKOUT High

Tosc-25

Tosc+45

TLHLL

ALEI ADV High Time

Tosc-30

Tosc+35(4)

TAVLL(5)

Address Setup to End of ALEI ADV

Tosc-50

TRLAZ(6)

RD or WR Low to Address Float

ns
25

TLLRL

End of ALEI ADV to RD or WR Active

Tosc-40

TLLAX(6)

Address Hold after End of ALEI ADV

Tosc-40

TWLWH

WR Pulse Width

3Tosc-35

TaVWH

Output Data Valid to End of WR/WRL/WRH

3Tosc-60

TWHax

Output Data Hold after WR/WRL/WRH

Tosc-50

TWHLH

End of WR/WRLlWRH to ALEI ADV High

Tosc-75

TRLRH

RD Pulse Width

3Tosc-30

TRHLH

End of RD to ALEI ADV High

Tosc-45

TCLLL(3)

CLOCKOUT Low to ALEI ADV Low

Tosc-40

Tosc+35

TRHBX(3)

RD High to INST, BHE, AD8-15 Inactive

Tosc-25

Tosc+30

TWHBX(3)

WR High to INST, BHE, AD8-15 Inactive

TosC-50

Tosc+ 100

THLHH

WRL, WRH Low to WRL, WRH High

2Tosc-35

2Tosc+40

TLLHL

ALEI ADV Low to WRL, WRH Low

2Tosc-30

2Tosc+55

TaVHL

Output Data Valid to WRL, WRH Low

Tosc-60

NOTES:

1. If more than one wait state is desired, add 3Tosc for each additional wait state.
2. CLKOUT is directly generated as a divide by 3 of the oscillator. The period will be 3Tosc ± 10 ns if Tosc is constant and
the rise and fall times on XTAL 1 are less than 10 ns.
3. Pins not bonded out on 48-pin devices.
4. Max spec applies only to ALE. Min spec applies to both ALE and ADV.
5. The term "Address Valid" applies to ADO-15, BHE and INST.
6. The term" Address" in this definition applies to ADO- 7 for 8-bit cycles, and ADO-15 for 16-bit cycles.

2-105

·SX9XJF EXPRESS

Table 1. MCS®·96 Packaging-8X9XJF
Factory
Masked
ROM
68 Pin
Analog

EPROM

64 Pin 48 Pin 68 Pin

8397JF 8397JF

User
Programmable

CPU

64 Pin 48 Pin 68 Pin 64 Pin 48 Pin 68 Pin

8097JF 8097JF

No Analog
PACKAGE DESIGNATORS:

N
C
A
P
R
U

OTP

= PLCC
= Ceramic DIP
=;Ceramic Pin Grid Array
= Plastic DIP
= Ceramic LCC
= Shrink DIP

REVISION HISTORY
This is the first data sheet for the 8X9XJF Express devices.

2-106

64 Pin 48 Pin

8797JF 8797JF

EV8097BH fEATURES
• Zero Wait-State 12 MHz Execution Speed
• 24K Bytes of ROMsim

• Flexible Wait-State, Buswidth, Chip-Select Controller
• Concurrent Interrogation of Memory and Registers
• Sixteen Software Breakpoints
.'Two Single-Step Modes
• High-Level Language Support
• Symbolic Debug
• RS-232-C Communication Link

EVALUATION TOOL
Intel's EV8097BH evaluation board provides a hardware environment for code execution and
software debugging at a relatively low cost. The board features the 8097BH 16-bit microcontroller
from the industry standard MCS®-96 family, The board allows you to
take full advantage of the power of the MCS-96, The EV8097BH provides zero wait-state, 12 MHz
execution of a user's code. Plus, its memory (ROMsim) can be reconfigured to match your planned
memory system, allowing for exact analysis of code execution speeds in a particular application.
**IBM pc, XT, AT and DOS are regIstered trademarks of Interndtional Busmess CorporatIOn.

-n+_I®

111'e'-_Intel CorporatIon assumes no respopslblhty for the use of any circUitry other than CIrcUItry embodIed In an Intel product. No other ClfCUIt patent
lIcenses are ImplIed InformatlOn con tamed herem supercedes prevlOusly published specifIcations on these deVIces from Intel.
MARCH 1989
© Intel Corporation 1989
Order number: 270739-001

2-107

Popular features such as'a symb~lic d~bug, sin~le-line assembier, disassembler, single-step program
execution, and sixteen software breakpoints are standard on the EV8097BH. Intel provides a
complete code development environment using assembler (ASM-96) as well as high-level languages
such as Intel's iC;96 or PL/M-96 to accelerate development schedules.
The evaluation board is hosted on an IBM PC~ or BrOS-compatible clone, already a standard
development solution in most of today's engineering environments. The source code for the onboard monitor (written in ASM-96)is public domain. The program is about lK, and can be\!asily
modified to be included in your t'lrget hardware. In this way, the provided PC ho!\t software can be
used throughout the development phase.

FULL SPEED EXECUTION
The EV8097BH executes your code from on-board ROMsim at 12 MHz with zero wait-states. By
changing crystals on the 8097BH, arty slower execution speed can be evaluated. The boards host
interface timing is not affected by this crystal change,

24K BYTES OF ROMSIM
The board comes with 24K bytes of SRAM to be used as ROMsim for your application code and as
data memory if needeCi. 16K bytes, of this memory are configured as sixteen bits wide and 8K bytes
are configured as eight bits wide. You can therefore evaluate the speed of the part executing from
.
either buswidth.

FLEXIBLE MEMORY DECODING
By changing the Programable Logic Device (PLD) on the board, the'memory On the board can be
made to look like the memory system planned for your hardware application. The PLD controls the
buswidth of the 8097BH and the chip-select inputs on the board. It also cO,ntrols the number of wait
states (zero to four) generated by the 8097BH during a memory cycle. These features can all be
selected with 256 byte boundaries of resolution.

CONCURRENT INTERROGATION OF MEMORY AND REGISTERS
The monitor for the EV8097BH allows you to read and modify internal registers and external
memory while your code is running in the board,

SIXTEEN SOFTWARE BREAKPOINTS
There are sixteen breakpoints available which automatically substitute a TRAP instruction for your
instruction at the breakpoint location. The substitution occurs when execution is started. If the code
is halted or a breakpoint is reached, your code is restored in the ROMsim.

TWO STEP MODES
There are two single-step modes available, The first stepping mode locks out all interrupts which
might occur during the step. The second mode enable's interrupts, and treats subroutine calls-and
interrupt routine~ as indivisible instructions.

2-108

HIGH LEVEL LANGUAGE SUPPORT
The host software for the EV8097BH board is able to load absolute object code generated by ASM-96,
iC-96, PL/M-96 or RL-96, all of which are available from Intel.

SYMBOLIC DEBUG
The host has a Single-Line Assembler, and a Disassmbler that recognize symbolics generated by
Intel software tools.

RS-232-C COMMUNICATION LINK
The EV8097BH communicates with the host using an Intel 82510 UART provided on board. This
frees the on-chip UART of the 8097BH for your application.

POWER REQUIREMENTS
The EV8097BH board requirs 5 volts at 450 rnA. If the on-board LED's are disabled, the current
drops to 300 rnA. The board also requires + / - 12 volts at 25 rnA.
.

PERSONAL COMPUTER REQUIREMENTS
TJ:.le EV8097BH Evaluation Board is hosted on an IBM PC*, XT*, AT* or BIOS-compatible clone. The
PC must meet the following minimum requirements:
•
•
•
•
•
•

512K Bytes of Memory
One 360K Byte Floppy Disk Drive
PC-DOS* 3.1 or Later
A Serial Port (COMI or COM2) at 9600 Baud
ASM-96, iC-96 or PL/M-96 .
An ASCII text editor such as AEDIT

.
RS-232
BUFFERS
CPU

CHIP SELECT
BUSWlDTH
READY
LOGIC

Txd
P2

ANALOG INPUT
ANALOG
DIGITAL
DIGITAL 110

110

Rxd

ADDRESS

PortO

DATA

Port 1,2
HSO,HSI

810321<
x16
RAM6'ROM

810321<
x8

RAM£PROM

CONTROL

Block Diagram of the EV8097BH Board

Pnnted in U.s A /389/l0K/RR SM

82510
UART

'---

MCS®..,96 Instruction Set

MCS®·96
INSTRUCTION SET
breg. A byte register in the internal register file. When
confusion could exist as to whether this field refers to a
source or a destination register it will be prefixed with

OVERVIEW
This chapter of the manual gives a description of each
instruction recognized by the MCS®-96 architecture.
The instructions are sorted alphabetically by the assembly language mnemonic.

an "S" or a "D",

baop. A byte operand which is addressed by any of the
address modes.

Additional information including instruction execution
times and a description of the different addressing
modes can be found in the following documents:

bitno. A thr~e bit field within an instruction op-code
which selects one of the eight bits in a byte.

MCS·96 MACRO ASSEMBLER USER'S GUIDE
Order Number 122048 (Intel systems)
Order Number 122351 (DOS systems)

wreg. A word register in the internal register file. When
confusion could exist as to whether this field refers to a
source register or a ~estination register it will be prefixed with an "S" or a "0".

MCS·96 UTILITIES USER'S GUIDE
Order Number 122049 (Intel systems)
Order Number 122356 (DOS systems)

waop. A word operand which is addressed by any of the
address modes.
Lreg. A 32-bit register in the internal register file.

PL/M·96 USER'S GUIDE
Order Number 122134 (Intel systems)
Order Number 122361 (DOS systems)

caddo An address in the program code.
Flag Settings. The modification to the flag setting is
shown for each instruction. A checkmark (,..,) means
that the flag is set or cleared as appropriate. A hyphen
means that the flag is not modified. A one or zero (1) or
(0) indicates that the flag wiJI be in that stat!! after the
instruction. An up arrow (t) indicates that the instruction may set' the flag if it is appropriate but wiJI
not clear the flag. A down arrow ( J, ) indicates that the
flag can be cleared but not set by the instruction. A
question mark (?) indicates that the flag will be left in
an indeterminant state after the operation.

C·96 USER'S GUIDE
Order Number 167632
80C196KC USER'S GUIDE
Order Number 270704
80C196KB USER'S GUIDE
Order Number 270651
MCS·96 ARCHITECTURAL OVERVIEW
Order Number 270250

Generic Jumps and Calls. The assembler for the
MCS-96 family provides for generic jumps and calls.
For all of the conditional jump instructions a "B" can
be substituted for the "J" and the assembler wiJI generate a code sequence which is logically equivalent but
can reach anywhere in the memory. A JH can only
jump about 128 locations from the current program
counter; a BH can jump anywhere in memory. In a like
manner a BR will cause a SJMP or LJMP to be generated as appropriate and a CALL wiJI cause a SCALL
or LCALL to be generated. The assembler user's guide
should be consulted for the algorithms used by the assembler to convert these generic instructions into actual
machine instructions.

The instruction set descriptions in the following sections do not always show the effect on the program
counter (PC). Unless -otherwise specified, all instructions increment the PC by the number of bytes in the
instruction.
A set of acronyms are used to make the instruction set
descriptions easier to read, their definitions are listed
below:
aa. A two bit field within an opcode which selects the
basic addressing mode user. This field is only present in
those opcodes which allow address mode options. The
encoding of the field is as follows:

Indirect Shifts. The indirect shift operations use registers 24 through 255 (l8H-OFFH), since 0-15 are direct operators and registers 16 through 23 are Special
Function Registers. Note that indirect shifts through
SFRs are illegal operations.

Addressing mode

Immediate

Indirect

Indexed

The maximum shift count is 31 (IFH). Count values
above this wiJI be truncated to the 5 least significant
bits.
3-1

MCS®-96 INSTRUCTION SET

1. ADD (Two Operands) - ADD. WORDS
Operation: The sum of the two word operands is stored into the destination' (leftmost)
operand.

(DESTj" -

DST
wreg,

Assembly Language Format: .
ADD
Object cOde Format: [

(DESn

(SRC)

SRC
waop

011001aa

waop

1 Iwreg 1

Flags Affected

""'1"'" 1""'1""'1 i 1 -

2. ADD (Three Operands) - ADD WORDS
Operation: The Sum of the second and third word operands is stored into the destination
(leftmost) operand.

(DEST) Assembly Language Format:
. ADD
Object Code Format: [

(SRC1)

(SRC2)

DST
SRC1
D,wreg, Swreg,

0.10001 aa

waop

SRC2
waop

1I
ST

3-2

Swreg

Dwreg

Mcs/fij..gs INSTRuctiON SEt
.

3. ADDB (Two Operands) - ADD BYTES

:','

,.,,.

""I,

',',

Operation: Thesum"of the two byte 'operands is stored into the 'destination (leftmost)
operand.
.
(DEST) +- (DES'F) + (SRC)
Assembly Language Format:
ADDB

DST
breg.

SRC
baop'

Object Code Format: [ 011101 aa ] [ baop' ] [. br!ilg']

1-, :;,' ~: ' ...

. ",

4. ADDB (Three Operands) ""'7 ADD BYTES

Operation: The sum of tilesebond and'third byte operands is stored into the destination
,
(leftmost) operand,'
(DEST) +- (SRC1) + (SRC2),
Assembly Language Format:
ADDB

DST
Dbreg.

Object Code Format: [ 010101aa

SRC1
Sbreg.

SRC2
baop

baop ] [ Sbreg

3-3

Dbreg

inter

MCS~.$6 INST~UCTION,SET

5. ADDC - ADD WORDS WITH CARRY
Operation: The sum of the two word operands and the carry flag (0 or 1) is stored into the
destination (leftmost) operand.
(DEST) -

Assembly Language Format:

DST
wreg,

ADDC

Object Code Format: [

(DEST)

101001 aa

+ (SAC) + C

SAC
waop
waop

wreg

]

Flags Affected

INlclvlvrlsT

J.1 .... j ....

I .... l t l -

6. ADDCB - ADD BYTES WITH CARRY
Operation: The sum .of the two byte operands and the carry flag (0 or 1) is stored into the
destination (leftmost) operand.
(DEST) -

Assembly Language Format:
ADDCB

Object Code Format: [

(DEST)
DST
breg,

101101 aa

(SAC)

SAC
baop
baop

breg

Flags Affected.
Z

NlclvlvTlsT

.... 1 .... 1 .... 1

1 -

]

inter

MCS®·96 INSTRUCTION SET

7. AND (Two Operands) - LOGICAL AND WORDS
Operation: . The two word operands are ANDed,. the result having a 1 only in those bit
positions where both operands had a 1, with zeroes in all other bit positions.
The result is stored into the destination (leftmost) operand.

(DEST) Assembly Language Format:

AND
Object Code Format: [

(DEST) AND (SRC)
DST
wreg,

011000aa

J. [

SRC
waop
waop

'wreg

8. AND (Three Operands) - LOGICAL AND WORDS
Operation: The second and third word operands are ANDed, the result having a 1 only in
those bit positions where both operands had a 1, with zeroes in all other bit
positions. The result is stored into the destination (leftmost) operand.

(DEST) Assembly Language Format:

AND
Object Code Format: [

(SRC1) AND (SRC2)
DST
SRC1
Dwreg, Swreg;

010000aa

waop

SRC2
waop

3-5

SWreg

Dwreg

MCS®~96INSTRUCTION

9. AN DB (Two Operands) -

SET

LOGICAL AND BYTES

Operation: The two byte operands are ANDed, the result having a 1 only in those bit
positions where both operands had a 1, with zeroes in all other bit positions.
The result is stored into the destination (leftmost) operand.

(DEST) ..... (DEST) AND (SRC)
Assembly Language Format:

AN DB
Object Code Format: [

DST
breg,

011100aa·

SRC
baop

J [ baop J [ breg J

10. ANDB (Thre~ Operands) -

LOGICAL AND BYTES

Operation: The second and third byte operands are ANDed, the result having a 1 only in
those bit positions where both operands had a 1, with zeroes in all other bit
positions. The result is stored into the destination (leftmost) operand.
(DEST) ..... (SRC1) AND (SRC2)
Assembly Language Format:

AN DB
Object Code Format: [

DST
Dbreg,

010100aa

SRC1
Sbreg,

SRC2
baop

J [ baop J [ Sbreg J [ Dbreg J

Flags Affected

z 1 N 1C 1V I
~ 1~ 10 10

1 ST
1 -I VT

3-6 •

inter
11. BMOV -

MCS®·96 INSTRUCTION SET

BLOCK MOVE (80C196KB and 80C196KC only)
Operation:' This instruction is used to move a block of word data from one location in
memory to another. The source and destination addresses are calculated
using the indirect with auto-increment addressing modes. A long register addresses the source and destination pointers which are stored in adjacent word
registers. The number Of transfers Is specified by a word register. The blocks
of data can reside anywhere'in memory, but should not overlap.

(CNTREG)
COUNT LOOP; SRCPTR (PTRS)
DSTPTR (PTRS + 2)
(DSTPTR) (SACPTR)
(PTRS) SRCPTR + 2
(PTRS) + 2) DSTPTR + 2
COUNT COUNT - 1
if COUNT < > 0 then go to LOOP
PTRSCNTREG
Assembly Language Format: BMOV Lreg, wreg
Object Code Format: [11000001

1 [ wreg 1 [ Lreg 1

NOTES:

1. CNTREG does not get decremented during the instruction.
2. It is easy to unintentionally create a very long un-interruptable operation
with this instruction ..
To provide an interruptable version of the BMOV for large blocks, the BMOV
instruction can be used with the DJNZ instruction. This is possible because
the pointers are modified, but CNTREG is not. Consider the example:
LD
LD
LD
LD
Move: BMOV
DJNZ

PTRS, SRC
PTRS+2, DST
CNTREG, #COUNT
CNTSET, #SETS

;Pointer to base of sources table
;Pointer to base of destination table
;Number of bytes to move per set
;Number of sets to move

PTRS,CNTREG
CNTSET, MOVE

;Move one set
;Decrement set counters and move again

3-7 .

MCS@·96 INSTRUCTION SET

12. BMOVI -

INTERRUPTABLE BLOCK MOVE (80Ct96KC only)
Operation: This instruction is used to move a block of word :data from one location in
memory to another and is interruptable. The source and destination addresses
are calculated using the indirect with auto-increment addressing modes. A
long register addresses the source and destination pointers which are stored
in adjacent word registers. The number of transfers is specified by a word
register. The blocks of data can reside a,)ywhere in memory, but should not
overlap.
COUNT .-- (CNTREG)
LOOP: SRCPTR .-- (PTRS)
DSTPTR .-- (PTRS + 2)
(DSTPTR) .-- (SRCPTR)
(PTRS) .-- SRCPTR + 2
(PTRS) + 2) .-- DSTPTR + 2
COUNT .-- COUNT - 1
if COUNT < > 0 then go to LOOP
PTRSCNTREG

Assembly Language Format: BMOVI Lreg, wreg
Object Code Format: [10101101

1 [wreg 1 [ Lreg 1

NOTES:
1. CNTREG does not get decremented during the instruction. However, if the
BMOVi is interrupted, CNTREG will be updated. Therefore, CNTREG must
be reloaded before starting a BMOVi.

inter

MCS®·96 INSTRUCTION SET

13. BR (Indirect) - BRANCH INDIRECT
Operation: The execution continues at the address specified in the operand word register.
PC .-- (DEST)
Assembly Language Format: SR

[

wreg

Object Code Format: [ 11100011

wreg

Flags Affected
zlNlcl,vlvTlsT

-1-1-1-1-114. CLR - CLEAR WORD
Operation: The value of the word operand is set to zero.
(DEST) .-- 0
Assembly Language Format: CLR

wreg

Object Code Format: [ 00000001

wreg

3-9

MCS®'·96' INStfRI:JCTION SET

15. CLRB - CLEAR BYTE
Operation: The value of the byte operand is set to zero.

(DEST) +- 0
Assembly Language Format: CLRB
Object Code Format: [

breg

00010001

breg

Flags Affected

Z /. N / C
1

I V I"\IT I ST

I 0 I 01

I -,- I -

16. CLRC - CLEAR CARRY FLAG
Operation: The value of the carry flag is set to zero.

C+-O
Assembly Language Format: CLRC
Object Code Format: [. 11111000
Flags Affected

I N I C I vi VT r st
- I - I .0 ·1 - I - I Z

3-10

inter

MCS®·96 INSTRUCTION SET

17. CLRVT - CLEAR OVERFLOW TRAP
Operation: The value of the overflow-trap flag is set to zero.

VT +- 0
Assembly Language format: CLRVT
Object Code Format: [

11111100

18. CMP-COMPARE WORDS
Operation: The source (rightmost) word operand is subtracted from' the destination (Ieft~
most) word operand. The flags are altered but the operands remain unaffected. The carry flag is set as complement of borrow.
. (DEST) - (SRC)
Assembly Language format:

CMP
Object Code format: [

DST
wreg,

10001 Oaa

SRC
waop
waop

wreg

3-11

MCS®·961NSTRUCTION SET

19. CMPB - COMPARE BYTES
Operation: The source (rightmost) byte operand is subtracted from the destination (left·
most) byte operand. The flags are altered but the operands remain unaffected.
"The carry flag is set as complement of borrow.
(DEST) -

(SRC)

CMPB

DST
breg,

Assembly Language Format:

Object Code Format: [

10011'Oaa

SRC
baop
baop

breg

Flags Affected
zlNICIVIVTIST

",1"'1"'1"'1
20. CftjlPL -

COMPARE LONG (80C196KB and 80C196KC only)
Operation: This instruction is used to compare the magnitudes of two double word (long)
operands. The operands are specified using the direct addressing mode. Five
PSW flags are set following this operation, but the operands are not affected.
DST·SRC
DST SRC

Assembly Language Format: CMPL Lreg, Lreg
Object Code Format: [11000101

1 [ src Lreg 1 [ dst# Lreg 1

3·12

MCS®·96 INSTRUCTION SET.

21. DEC - DECREMENT WORD
Operation: The value of the word operand is decremented by one.
(OEST) +- (OEST) -

Assembly Language Format: OECwreg
Object Code Format: [ 00000101

wreg

Flags Affected

ZINlclvlvTlsT
"'.1 "'l"'I"'1 t 122. DECB - DECREMENT BYTE
-96 INSTRUCTION SET

26. DIVU - DIVIDE WORDS
Operation: This instruction divides the content of the destination DOUBLE-WOAD operand by the contents of the source WOAD operand, using unsigned arithmetic.
The low order word will contain the quotient; the high,order WOAD will contain
the remainder.
(low word DEST) (DEST) / (SAC)
(high word DEST) (DEST) MOD (SAC)
The above two statements are performed concurrently.
(

Assembly Language Format:
DIVU

DST
Ireg,

Object Code Format: [ 100011 aa

SAC
waop
waop

27. DIVUB -

Ireq

DIVIDE BYTES
Operation: This instruction' divides the contents of the destination WOAD operand by ·the
contents of the source BYTE operand, using unsigned arithmetic. The low
order byte of the destination, (Le., the byte with the lower address) will contain
the quotient; the high order byte will contain the remainder.
(lOW byte DEST) (DEST) I (SAC)
(high byte DEST) (DEST) MOD (SRC)
The above two statements are performed concurrently.

Assembly Language Format:
DIVUB

Object Code Format:

DST
wreg,

100111aa

SRC
baop
baop

wreg

3-15

MCS®·96INSTRUCTION.SET
\

28. DJNZ -

DECREMENT AND JUMP IF NOT ZERO

1',

Operation: The value of the .byte operand is decremented by 1.lf the result is not equal to
0, the distance ,from the end of this instruction to the target label is added to
. the program counter, effecting the jump. The offset from the end of this instruction to the target label must be in the range of - 128 to + 127. If the
result of the decrement is zero then c(;mtrol passes to the next sequential
instruction.
(COUNT) ~ (COUNT) ~ 1
if (COUNT) < > 0 then
PC ~ PC + disp (sign-extended to 16 bits)

end_if
Assembly·Language Format: DJNZ
Object Code Format: (

breg,cadd

111 00000

breg

disp

Flags Affected
Z 1 N 1 C 1 V 1VT 1ST
-1-1-1-1-1-

29. DJNZW - DECREMENT AND JUMP IF NOT ZERO WORD (80C196KB and
80C196KC only)
Operation: This instruction is the same as the DJNZ except that the count is a word
operand.: A counter word is decremented; if the result is not zero the jump is
taken. The range of the jump is -128 to + 127.

COUNT ~ COUNT ~ - 1
if COUNT < > 0 then
PC ~ PC + disp (sign extended)
Assembly Language Format: DJNZW wreg,cadd
Object Code Format: [11100001

1 [ wreg 1 [disp 1

3-16

MCS@·96 INSTRUCTION SET

30. OPTS - OISPOSABLEPERIPHERAL 'TRANSACTION SERVER
(PTS":'" 80C196KC only)
Operation: The PiS is disabled following the execution of this instruction.
PTS.Disable (PSW.10) +- 0
'"

Assembly Language Format: OPTS

,~.

Object Code Format: [ 11101100,]

31. EI- ENABLE INTERRUPTS
OperaJlon: 'Interrupts are erlsbled following the execution of'the next statement. Interruptcalls cannot occur immediately folloWing this ,instruction.
Interrupt Enable (PSW.9) +- 1

Assembly Language Format: EI
Object Code Format: [ 11111011]

-3-17

inter

MCS~·96INSTRUCT:ION.SE:r

32. EPTS - ENABLEPERtPHERAL' TRANSACTION -SERVER" ,;.
(PTS - 80C196KC o n l y ) '
". '
. ,Operation: The PTS is enabled following the execution of this. instruction.
PTS Enable (PSW.19) +-. 1 ,
Assembly Language Format: EPTS
Object Code Format: [ 11101101

"\,

),.',,:

33. EXT - SIGN EXTEND INTEGER INTO 'LONG·I~TEGER
Op~ratlon:

," ,

The lo~; Qrder wQrd of the operand is sign-extended throughout the high order
worQ ophe operand.
" ,
, ."
if (low word DEST) < BOOOH then
(high word DEST) +- 0
else
(high word DEST) .,...: OFFFFH
enc:Lif

Assembly Language Format: EXT

\ Ireg
,

Object Code Format: [ 00000110

Ireg

Flags Affected

ZINlclvlVTlsT
~

1~ 10 10 1- I -

MCS®·96 INSTRUCTION SET

34. EXTB - SIGN EXTEND SHORT-INTEGER INTO INTEGER
Operation: The low order byte of the operand is sign-extended throughout the high order"
byte of the operand.
if (low byte DEST) < SOH then
(high byte DEST) +- 0
else
(high byte DEST) +- OFFH
end_if

Assembly Language Format: EXTB
Object Code Format: [

wreg

00010110

wreg

Flags Affected
zlNlclVIVTIST

,;1,;1010"1-135. INC -INCREMENT WORD
Operation: The value of the word operand is incremented by 1.

(DEST) +- (DEST)

Assembly Language Format: INC
Object Code Format: [

wreg

00000111

wreg

FI,gs Affected
z

I" c

1V 1VT 1ST
i 1-

,,;J,;I,;I,;I

3-19

MCS®-96 INSTRUCTION SET

36. INCB -INCREMENT BYTE
Operation: The value of the byte operand is incremented by 1.
(DEST) (DEST) + 1
Assembly Language Format: INCB

breg

Object Code Format: [ 00010111

1 [ breg

37. IDLPD -

IDLE/POWERDOWN (80C196KB and 80C196KC only)
powe~down modes. Selecting IDLE or POWER DOWN is done using the key operand .. If the operand is
not a legal key, the part executes a reset sequence. The bus controller will
complete any prefetch cycle in progress before the CPU stops or resets.

Operation: This instruction is used for entry into the idle and

if KEY = 1 then enter IDLE
else if KEY 2 then enter
POWERDOWN
else execute reset.

Assembly Language Format: IDLPD #key (key is a-bit value)
Object Code Format: [111101101 [ key 1
Flags Affected

- - -

-0

X
X

Z
Legal Key:
Illegal Key:

( - = Unchanged)

3-20

inter
38. JBC -

MCS®·96 INStRUCTION SET

JUMP IF BIT CLEAR
Operation: The specified bit is tested. If it is clear (Le., 0), the distance from the end of this
instruction to the target label is added to the program counter, effecting,the
jump. The offset from the end of this instruction to the target label must be in
the range of -128 to + 127. If the bit is set (Le., 1), control passes to the next
sequential instruction.
if (specified bit) = 0 then
PC +- PC + disp (sign-extened to 16 bits)

Assembly Language Format: JE;lC

breg,bitno,cadd

1 [ breg 1 [ disp 1
where bbb is the bit number within the specified register.

Object Code Format: [ 0011 Obbb

3-21

MC$®-.96 INSTRUCTION SET

39.~ JBS -

JUMP IF BIT SET
Operation: The specified bit is tested. If it is set (i.e., 1),Jhe distance from the end of this
instruction to the target label is added to the program counter, effecting the
jump. The offset from the end of this instruction to the target I.abel must be in
the range of -128 to + 127. If the bit is clear (i.e., 0), control passes to the
next sequential instruction.
if (specified bit) = 1 then
PC +- PC +disp (sign-extended to 16 bits)

Assembly Language Format: JBS

breg,bitno,cadd

I [ disp I
where bbb is the bit number within the specified register.

Object Code Format: [ 00111 bbb )[ breg

40. JC - JUMP IF CARRY FLAG IS SET
Operation: If the carry flag is set (i.e., 1), the distance from the end of this instruction to
the target label is added to the program counter, effecting the jump. The offset
from the end of this instruction to the target label must be in the range of
-128 to + 127. If the carry flag is clear (i.e., 0), control passes to the next
sequential instruction.
if C

= 1 then
PC +- PC + disp (sign-extended to 16 bits)

Assembly Language Format: JC

cadd

, Object Code Format: [ 11011011

disp

3-22

MCS®·96 INSTRUCTION SET

41. JE-JUMP IF EQUAL
Operation: If the zero flag is set (i.e., 1), the distance from the' end of this instruction to the
target label is added to the program counter, effecting the Jump. The offset
from the end of this instruction to the target label must be in the range of
-128 to + 127. If the zero flag is clear (i.e., 0), control passes to the next
,sequential instruction.
ifZ=1then
PC +- PC + qisp (sign-extended to 16 bits)

Assembly Language Format: JE
Object Code Format:

cadd
11011111] [

disp

]

42. JGE-JUMP IF SIGNED GREATER THAN OR EQUAL
Operation: If the negative flag is clear (i.e., 0), the distance from the end of this instruction
,

to the target label is added to the program counter, effecting the jump. The
offset from the end of this instruction to the target label must be in the range
of --:,128 to + 127. If the negative flag is set (Le., 1), control passes to the next
. sequential instruction.
ifN =
then
PC +- PC
disp (sign-extended to 16 bits)

Assembly Language Format: JGE

cadd

Object Code Format: [ 11010110 ] [ disp

3·23

MCS®·96 INSTRUCTION:SET

43. JGT-JUMP IF. SIGNED GREATER THAN
Operation: If both the negative flag and the zero flag are clear (Le., 0), the distarice from
the end of this instruction to the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to the target
label must be in the range of - 128 to + 127. If either the negative flag or the
zero flag are set (Le., 1,) control passes to the next sequential instruction.
if N

=
PC

Assembly Language Format: JGT

0 AND Z
~ PC

0 then

+ disp (sign-extended to 16 bits)

cadd

Object Code Format: [ 11010010

disp

44. JH - JUMP IF HIGHER (UNSIGNED)
Operation: If the carry flag is set (Le., 1), but the zero flag is not, the distance from the end
of this instruction to the target label is added to the program counter, effecting
the jump. The offset from the end of this instruction to the target label must be
in the range of -128 to + 127. If either the carry flag is clear or the zero flag is
set, control passes to the next sequential instruction.
if C = 1 AND Z = 0 then
PC ~ PC + disp (sign-extended to 16 bits)

Assembly Language Format: JH

cadd

Object Code Format: [ 11011001

disp

3-24

MCS®·96 INSTRUCTION SET

4,5. JLE - JUMP IF SIGNED LESS THAN OR EQUAL
Operation: If either the negative flag or the zero flag are set (Le., 1), the distance from the
end of this instruction to' the target label is added to the program counter,
effecting the jump. The offset from the end of this instruction to the target
label must be in the range of - 128 to + 127. If both the negative flag and the
zero flag are clear (Le., 0), control passes to the next sequential instruction.
if N = 1 OR Z = 1 then
PC +,- PC + disp (sign-extended to 16 bits)
Assembly Language Format: JLE
Object Code Format: [

cadd

11011010

disp

Flags Affected

1N 1C 1V VT 1ST
-1-1-1- -1-

, Z·

46. JLT - JUMP IF SIGNED LESS THAN
Operation: If the negative flag is set (Le.; 1), the distance from the end of this instruction
to the target label is added to th.e program counter, effecting the jump. The
offset from the end of this instruction to the target label must be in the range
of -128 to+ 127. If the nl'lgative flag is clear (Le., 0), control passes to the
next sequential instruction.
ifN=1then
PC -- PC + disp (sign-extended to 16 bits)
Assembly Language Format: JLT
Object Code Format: [

cadd

11011110

disp

Flags Affected
zlNICIVIVTIST

-1-1'-1-1-1-

3-25

MCS®·96 INSTRUCTION SET

47. JNC-JUMP IF CARRY FLAG IS CLEAR
Operation: If the carry flag is clear (i.e., 0), the distance from the end of this instruction to
the target label is added to the program counter, effecting the jump. The offset
from the end of this instruction to the target label must be in the range of
-128 to + 127. If the carry flag is set (Le., 1), control passes to the next
sequential instructiQn.
.
if C = 0 then
PC PC

Assembly Language Format: JNC

disp (sign-extended to 16 bits)

cadd

Object Code Format: [ 11010011

disp

Flags Affected
zlNICIVIVTIST

-1-1-1-1-148. JNE - JUMP IF NOT EQUAL
Operation: If the zero flag is clear (i.e., 0), the distance from the end of this instruction to
the target label is added to the program counter, effecting the jump. The offset
from the end of this instruction to the target label must be in the range of
-128 to + 127. If tbe zero flag is set (Le., 1), control passes to the next
sequential instruction.
if Z = 0 then
PC PC

Assembly Language Format: JNE

disp (sign-extended to 16 bits)

cadd

Object Code Format: [ 11010111

[disp

? .

1
ST

3-26

inter

MCS®-96 INSTRUCTION SET

49. JNH - JUMP iF NOT HIGHER (UNSIGNED)
Operation: If either the carry flag is clear (i.e., 0), or the zero flag is set (Le., 1), the
distance from the end of this instruction to the target label is added to program
counter, effecting the jump. The offset from the end of this instruction to the
target label must be in the range of - 128 to + 127. If the carry flag is set (Le.,
1) and the zero flag is not, control passes to the next sequential instruction.
if C

= 0 OR Z = 1 then
PC +- PC

Assembly Language Format: JNH
-

Object Code Format: [

+ disp(sign-extended to 16 bits)

cadd

11010001

disp

50. JNST - JUMP IF STICKY BIT IS CLEAR
Operation: If the sticky bit flag is clear (Le., 0), the distance from the end of this instruction
to the target label is added to the program counter, effecting the jump. The
offset from the end of this instruction to the target label must be in the range
of -128 to + 127. If the sticky bit flag is set (Le., 1), control passes to the next
sequential instruction.
if ST = 0 then
PC +- PC
Assembly Language Format: JNST
Object Code Format: [

disp (sign-extended to 16 bits)

cadd

11010000

disp

3-27

MCS®·96 INSTRUCTION SET

51. JNV -

JUMP IF OVERFLOW FLAG IS CLEAR·
Operation: If the overflow flag is clear (Le., 0), the distance from the end of this instruction
to the target label is added to the program counter, effecting the jump. The
offset from the end of this instruction to the target label must be in the range
of -128 to +127. If the overflow flag is set (Le., 1), control passes to next
sequential instruction.
ifV=Othen
PC -- PC

Assembly Language Format: JNV

+ disp (sign-extended to 16 bits)

c~dd

ObjectCodeFormat: [/11010101

] [ disp ]

Flags Affected
zlNlclvlVTlsT

-1-1-1-1-152. JNVT -

JUMP IF OVERFLOW TRAP IS CLEAR
Operation: If the overflow trap flag is clear (Le., 0), the distance from the end of this
instruction to the target label is added to the program counter, effecting the
jump. The offset from the end of this instruction to the.target label must be in
the range of -128 to +127. if the overflow trap flag is set (Le., 1), control
passes to the next sequential instruction. The VT flag is cleared.
if VT = 0 then
PC -- PC

Assembly Language Format: JNVT
Object Code Format: [

disp (sign-extended to 16 bits)

cadd

11010100

disp

3-26

MCS®·96 INSTRUCTION SE.T

53. JST - JUMP IF STICKY BIT IS SET
Operation: If the sticky bit flag is set (Le., 1), the distance from the end of this instruction
to the target label is added to the program counter, effecting the jump. The
offset from the erid of this instruction to the target label must be in the range
of -128 to + 127. If the sticky bit flag is clear (i,e., 0), control passes to the
next sequential instruction.

if ST= 1 then
PC +- PC
Assembly Language Format: JST

disp (sign-extended to 16 bits)

cadd

11011000

Object Code Format: [

disp

54. JV - JUMP IF OVERFLOW FLAG IS SET
Operation: If the overflow is set (Le., 1), the distance from the end of this instruction to the
target label is added to the. program counter, effecting the jump. The offset
from the end of this instruction to the target label must be in the range of
-128 to + 127. If the overflow flag is clear (Le., 0), control passes to the next
sequential instruction.

if V = 1 then
PC +- PC
Assembly Language Format: JV
Object Code Format: [

disp (sign-extended to. 16 bits)

cadd

11011101

disp

3-29

MCS®~96 INStRUCtiON SET

55. JVT - JUMP IF OVERFLOW TRAP IS SET
Operation: If the overflow trap flag is set (Le., 1), the distance from the end of this instruction to the target label is added to the program counter, effecting the jump.
The offset from the end of this instruction to the target label must be in the
range of -128 to + 127. If the overflow trap flag is clear (Le., 0), control
passes to the next sequential instruction. The VT flag is cleared.
if VT = 1 then
PC PC + disp (sign-extended to 16 bits)
Assembly Language Format: JVT

cadd

11011100

Object Code Format: [

disp

Flags Affected

ZINlclvlvTlsT
-1~1-1-lol-

56. LCALL -

LONG CALL
Operation: The contents of the program counter (the return address) is pushed onto the
stack. Then the distance from the end of this instruction to the target label is
added to the program counter, effecting the call. The operand may be any
address in the entire address space.

SP SP - 2
(SP) PC
Pc. PC + disp
Assembly Language Format: LCALL
Object Code Format:

cadd

11101111

disp-Iow

Flags Affected

z I NI C I V I vrl ST
-\-\-I,-I-J-'

3-30

disp-hi

MCS®-96 INSTRUCTION SET

57. LD-LOAD WORD
Operation: The value of the source (rightmost) word operand is stored into the destination
(leftmost) operand.
(OEST) (SRC)
Assembly Language Format:

OST
wreg,

LO
ObjeC~1COde Format:

101000aa

SRC
waop
waop

wreg

58. LDB - LOAD BYTE
Operation: The value of the source (rightmost) byte operand is stored into the destination
(leftmost) operand.
(OEST) (SRC)
Assembly Language Format:

LOB

OST
breg,

Object Code Format: [ 1011 OOaa

SRC
baop
baop

breg

Flags Affected
zlNICIVIVTIST

-1-1-1-1-1-

3·31

MCS®-96 INSTRUCTIONS!:T

59. LDBSE --LoAD INTEGER WITH SHORT-INTEGER
Operation: The value of the source (rightmost) byte operand is sign-extended and stored
into the destination (leftmost) word operand.
(low byte DEST) +- (SAC)
if (SAC) < 80H then
(high byte DEST) +- 0
else
(high byte DEST) +- OFFH
end_if
Assembly Language Format:
LDBSE
Object Code Format: [

DST
wreg.

101111 aa

SAC
baop
baop

wreg

Flags Affected

1N 1c 1V 1VT 1ST
-1-1-1-1-1Z

60. LDBZE - LOAD WOAD WITH BYTE
Operation: The value of the source (rightmost) byte operand is zero-exte,nded and stored
into the destination (leftmost) word operand.
(low byte DEST) +- (SAC)
(high byte DEST) +- 0
Assembly Language Format:
LDBZE

Object Code Format: [

DST
wreg.'

SAC
baop

baop

101011aa

wreg

Flags Affected

zlNlclvlVTlsT

-1-1-1-1-1-

3-32

MCS®-96 INSTRUCTION SET

&1. LJMP - LONG JUMP
Operation: The distance from the end of this instruction to the target label is added to the
program counter, effecting the jump. The operand may be any address in the
.entire address space.
PC::: -

PC+ disp

Assembly Language Format: LJMP
Object Code Format: [

cadd

11100111

disp-Iow

disp-hi

62.· MUL (Two Operands) - MULTIPLY INTEGERS
Operation: The two INTEGER operands are multiplied using signed arithmetic and the 32bit result is stored into the destin/!,tion (leftmost) LONG·INTEGER operand.
The sticky bit flag is undefined after the instruction is executed.
(DEST) Assembly Language Format:
MUL
Object Code Format:

(DEST)· (SRC)
DST
Ireg,

11111110

SRC
waop

011011 aa

3-33

waop

Ireg

inter

MCS®·96 INSTRUCTION SET

63. MUL (Three Operands) -

MULTIPLY INTEGERS

Operation: The second and third INTEGERoperands are multiplied. using Signed arithmetic and the 32-bit result is stored into the destination (leftmost) LONG INTEGER operand. The sticky bit flag is undefined after the instruction is executed.
(DEST) -

Assembly Language Format:
MUL

Object Code Format: [

(SRC1) • (SRC2)
DST
Ireg,

11111110

SRC1
wreg,

SRC2
waop

010011aa

waop

wreg

Ireg

64. MULB (Two Operands) - MULTIPLY SHORT-INTEGERS
Operation: The two SHORT-INTEGER operands are multiplied using signed arithmetic
and the 16-bit result is stored into the destination (leftmost) INTEGER operand. The sticky bit flag is undefined after the instruction is executed.
(DEST) (DEST)' (SRC)
Assembly Language Format:
MULB

Object Code Format: [

DST
wreg,

11111110

1 ['

SRC
baop

011111aa,

ST
?

3-34

baop

] [

wreg

inter

MCS®·96 INSTRUCTION SET

65. MULB (Three Operands) -

MULTIPLV' SHORT·INTEGERS

Operation: The second and third SHORT-INTEGER operands are multiplied using signed
arithmetic and the 16-bit result is stored into the destination (leftmost) INTEGER operand. The sticky bit flag is undefined after the instruction is executed.
(DEST) +- (SRC1)· (SRC2)
Assembly Language Format:
MULB
Object Code Format: [

DST
wreg,

11111110

SRC1
breg

SRC2
baop

010111aa

baop

breg

wreg

66. MULU (Two Operands) -..: Ml,!LTIPLV WORDS
Operation: The two WORD operands are multiplied using unsigned arithmetic and the 32bit result is stored into the destination (leftmost) DOUBLE-WORD operand.
The sticky bit flag is undefined after the instruction is executed.
(DEST) +- (DEST)' (SRC)
Assembly Language Format:
MULU
Object Code Format: [

DST
Ireg,

011011 aa

SRC
waop
waop

Flags Affected

z 1N 1C 1v·1 VT 1ST
-1-1-1-1-1 ?

Ireg

inter

MCS\ID~96

IN.STRUCTION seT

67. MULU (Three Operands) -:- MULTIPLY WORDS
Operation: The second and third WOAD operands are multiplied using unsigned arithmetic and the 32-bit result is stored into the destination (leftmost) DOUBLEWOAD operand. The sticky bit flag is undefined after the instruction is executed.

(DEST)
Assembly Language Format:

MULU
Object Code Format: [

(SAC1) • (SAC2)

DST
Ireg,

010011 aa

SAC1
wreg,
waop

SRC2
waop

wreg

Ireg

Flags Affected

zlNlclvlVTIST

-1-1-1-1-1

68. MULUB (Two Operands) - MULTIPLY BYTES
Operation: The two BYTE operands are multiplied using unsigned arithmetic and the
. WORD result is stored into the destination (leftmost) operand. The sticky bit
flag is undefined after the instruction is executed.

(DEST)
Assembly Language Format:

MULUB
Object Code Format: [

(DEST)' (SAC)

DST
wreg,

011111 aa

SRC
baop
baop

wreg

3-36

inter

MCS®-96 INSTRUCTION SET

69. MULUB (Three Operands) - MULTIPLY BYTES'
Operation: The second and third BYTE operands are multiplied using unsigned arithmetic
and the WORD result is stored into the destination (leftmost) operand. The
sticky bit flag is undefined after the instruction is executed.

(DEST) +- (SRC1)' (SRC2)
DST
wreg,

Assembly Language Format:

MULUB
Object Code Format: [

010111 aa

SRC1
breg,
baop

SRC2
baop

breg

wreg

70. NEG - NEGATE INTEGER
Operation: The value of the INTEGER operand is negated.
(DEST) +- - (DEST)
Assembly Language Format: NEG
Object Code Format: [

. wreg

00000011

1 [wreg 1,

Flags Affected

I N I C I V I VT I ST
,...1,...1,...1,...1 i 1z

3·37
,

MCS®·96 INSTRUCTION SET

71. NEGB - NEGATE SHORT-INTEGER.
Operation: Thevalue·of the SHORT·INTEGER operand is negated.

(OEST) . - - (OEST)
Assembly Language Format: NEGB
Object Code Format: [

breg

00010011

1 [ breg

72. NOP - NO OPERATION
Operation: Nothing is done. Control passes to the next sequential instruction.
Assembly Language Format: NOP

Object Code Format: [

11111101

inter

MCS@·96 INSTRUCTION SET

73. NORML - NORMALIZE LONG-INTEGER
. Operation: The LONG-INTEGER operand is normalized; i.e., it is shifted to the left until its
most significant bit is 1. If the most significant bit is still 0 after 31 shifts, the
process stops and the zero flag is set. The number of shifts actually performed
is stored in the second operand.
(COUNT) +- 0
do while (MSB(DEST) = 0) AND ((COUNT)
(DEST) +- (DEST) • 2
(COUNT) +- (COUNT) + 1
end_while

Assembly Language Format: NORML

< 31)

Ireg,breg .

Object Code Format: [ 00001111

breg

Ireg

Flags Affected

1N 1C 1V 1VT 1ST
"-17101-1-1z

74. NOT - COMPLEMENT WORD
Operation: The value of the WORD operand is complemented: each 1 is replaced with a
0, and each 0 with a 1.
(DEST) +- NOT (DEST)
Assembly Language Format: NOT

wreg

Object Code Format: [ 00?00010

wr.eg

3-39

Mc:S@-96 INSTRUCr.ON SET

7S~· NOTS - COMPLEMENT BYTE

Operation: The vaule of the BYTE operand is complemented:

~ach

,,'

1 is replaced with a 0,

and each 0 with a 1.
. (DEST) ..- .NOT (DEST)

Assembly Language Format: NOTB

breg

Object Code Format: [ 00010010

breg

76. OR ~ LOGI~AL OR WORDS
Operation: The sc;>urce (rightmost) WORD is ORed with the destination (leftmost) WORD
operand. Each bit is set to 1 if the corresponding bit in either the source
operand or the destination operand is 1. The result replaces the original destination operand.
(DJ:ST) ..- (DEST) OR (SRC)

Assembly Language Format:
OR

DST'
wi-eg,

SRC
waop

Object Code Format: [ 100000aa I [waop I [ wreg I

3-40

inter
77. ORB -

MCS®-96 INSTRUCTION SET

LOGICAL OR BYTES
Operation: The source (rightmost) BYTE operand is ORed with the destination (leftmost)
BYTE operand. Each bit is set to 1 if the corresponding bit in either the source
operand or the destination operand was 1. The result replaces the original
destination operand.
(DEST) -

Assembly Language Format: ORB

(DEST) OR (SRC)

breg,baop

Object Code Format: [ 1001 OOaa

baop

breg

Flags Affected

ZINlclvlvTlsT

"'1"'10101-178. POP - POP WORD
Operatlo~:

The word on top of the stack is popped and placed at the destination operand.
(DEST) (SP)
SP SP + 2

Assembly Language Format: POP

waop

Object Code Format: [ 110011 aa

waop

3-41

intJ
79.POPA -

MCS®-96 INSTRUCTION SET

POP ALL (80C196KB and 80C196KC only)
Operation: This instruction is used instead of POPF to support the 8 additional interrupts.
It is similar to POPF, but pops two words instead of one. The first word is
popped into the INT...,.MASK1/WSR register pair, while the second word is
popped into the PSW/INT_MASK register pair. As a result of this instruction
the SP is incremented by 4. Interrupts cannot occur between this instruction
. and the one following it.
INT_MASK1 IWSR +- (SP)
SP +- SP + 2
PSW/INT_MASK +- (SP)
SP +- SP + 2

Assembly Language Format: POPA
Object Code Format: [11110101

(", = changed)

80. POPF - POP F.LAGS
Operation: The word on top of the stack is popped and placed in the PSW. Interrupt calls
cannot occur immediately following this instrl,lction.
(PSW) +- (SP)
SP +- SP + 2
Assembly Language Format: POPF
Object Code Format: [

11110011
Flags Affected

z I N I c I V I VT I ST
", I ", I ", I ", I ", I ",

3-42

MCS®·9E$ INSTRUCTION SET

81. PUSH - PUSH WORD
Operation: The specified operand is pushed onto the stack.
SP +- SP - 2
(SP) +- (DEST)

Assembly Language Format: PUSH

waop

Object Code Format: [ 11001 Oaa

waop

82. PUSHA -

PUSH ALL (80C196KB, 80C196KC and 80C196KR only)
Operation: This instruction is used instead of PUSHF to support the 8 additional inter.rupts. It is similar to PUSHF, but pushes two words instead of one. The first
word pushed is the same as for the PUSHF instruction, PSW/INT_MASK.
The second word pushed is formed by the INT_MASK1/WSR register pair.
As a result of this instruction the PSW, INT_MASK, and INT_MASK1 registers are cleared, and the SP is decremented by 4. Interrupts are disabled in
two ways by this instruction since both PSW.9 and the interrupt masks are
cleared. Interrupts cannot occur between this instruction and the one following
it.
SP +- SP - 2
(SP) +- PSW/INT_MASK
PSW/INT_MASK +- 0
SP +- SP - 2
(SP) +- INT_MASK1/WSR
INT_MASK1 +- 0

Assembly Language Format: PUSHA
Object Code Format: [11110100

3-43

inter

MCS®·96 INSTRUCTION SET

83. PUSHF - PUSH FLAGS
Operation: The PSW is pushed on top of the stack, and then set to aU zeroes. This implies

that all interrupts are disabled. Interrupt-calls cannot occur immediately following this instruction.
SP ~ SP - 2
(SP) ~ PSW
PSW ~ 0
Assembly Language Format: PUSHF
Object Code Format: [

84. RET -

11110010

RETURN FROM SUBROUTINE
Operation: The PC is popped off the top of the stack.

PC
SP

(SP)
SP + 2

Assembly Language Format: RET
Object Code Format: [

11110000

3-44

inter

MCS®-96 INSTRUCTION SET

85. RST - RESET SYSTEM
Operation: The PSW is initialized to zero, and the PC is initialized to 2080H. The 1/0
registers are set to their initial value. Executing this i,nstruction will cause a
pulse to appear on the reset pin.
PSW +- 0
PC' +- 2080H
Assembly Language Format:

RST

Object Code Format: [ 11111111

Flags Affected

z I N I C I V I VT I ST
01010101010

86. SCALL -

SHORT CALL
Operation: The contents of the program counter (the return address) is pushed onto the
stack. Then the distance from the end of this instruction to the target label is
added to the program counter, effecting the call. The offset from .the end of
this instruction to the target label must be in the range of -1024 to + 1023
inclusive.
SP +- SP - 2
(SP) +- PC
PC +- PC + disp (sign-extended to 16 bits)

Assembly Language Format: SCALL

cadd

Object Code Format: [ 00101xxx I [ disp-Iow I
where xxx holds the three high-order bits of displacement.

3-45

inter

MC~®·96 I~STRUqT'ON

SET

87. SETC-SET CARRY FLAG
Opera~ion:

The carry flag is set.
C-1

Assembly Language Format: SETC

11111001

Object Code Format:

88. SHL - SHIFT WORD LEFT
Operation: The destination (leftmost) word operand is shifted left as many times as specified by the count (rightmost) operand. The count may be specified either as an
immediate value in the range of 0 to 15 (OFH) inclusive, or as the content of
any register above 15H. Details on indirect shifts can be found in the Overview. The right bits of the result are filled with zeroes. The last bit shifted out is
saved in the carry flag.'
Temp _ (COUNT)
do while Temp < > 0
C High order bit of (DEST)
(DEST) (DEST) • 2
. Temp Temp-1
end_while
Assembly Language Format:

SHL

wreg,#count

SHL

wreg,breg

Object Code Format: [

00001001

cntlbreg

Flags Affected

ZINlclvlVTIST
,..., I ? I,..., I ,..., I

3-46

wreg

inter

MCS®-96 INSTRUCTION SET

89.. SHLB - SHIFT BYTE LEFT
Operation: The destination (leftmost) byte operand is shifted left as many times as specified by the count (rightmost) operand. The count may be specified either as an
immediate value in the range of 0 to 15 (OFH) inclusive, or as the content of
any register above 15H. Details on indirect shifts can be found in the Overview. The right bits of the result are filled with zeroes. The last bit shifted out is
saved in the carry flag.
Temp +- (COUNT)
do while Temp < > 0
C +- High order bit of (DESn
(DEST) +- (DEST) • 2
TEMP +- Temp - 1
end_while

Assembly Language Format:

SHLB

breg, # count

SHLB

br~g,breg

Object Code Format: [ 00011001

cnt/breg

1[
ST

3-47

brag

MC$@~96 fNSTRUCTION SET

90. SHLL -

SHIFT DOUBLE..'WORD LEFT
Operation: The destination (leftmost) double-word' operand is Shifted left as many times
as specified by the count (rightmost) operand. The count may be specified
either as an immediate value in the range of 0 to 15 (OFH) inclusive, or as the
content of any register above 15H. Details on indirect shifts can be found in
the Overview. The right bits of the result are filled with zeroes. The last bit
shifted out is saved in the carry flag.
Temp (COUNT)
do while Temp < > 0
High order bit of (DEST)
C (DEST) (DEST)' ,2
Temp Temp - 1
end_while

Assembly Language Format:

SHLL

Ireg, # count

SHLL

Ireg, breg

or
Object Code Format: [ 00001101

] [ cnt/breg

1[
ST

;3-48

Ireg

]

MCS®·96 INSTRUCTION SET

91. SHR - LOGICAL RIGHT SHIFT WORD
Operation: The destination (leftmost) word operand is shifted right as many times as
specified by the count (rightmost) operand. The count may be specified either
as an immediate value in the range of 0 to 15 (OFH) inclusive, or as the
content of any register above 15H. Details on indirect shifts can be found in
the OVerview. The left bits of the result are filled with zeroes. The last bit
shifted out is saved to the carry. The sticky bit flag is cleared at the beginning
of the instruction, and set if at any time during the shift a 1 is shifted first into
the carry flag, and a further shift cycle occurs.

Temp (COUNT)
do while Temp < > 0
C Low order bit of (DEST)
(DEST) / 2 where / is unsigned division
(DEST) Temp Temp - l'
end_while
Assembly Language Format:

SHR

wreg, # count

SHR

wreg,breg

Object Code Format: [

00001000

cnt/breg

3-49

wreg

,. " v
MCS~-96

INSTRUCTION SET

92. SHRA - ARITHMETIC RIGHT SHIFT WORD
Operation: The destination (leftmost) word operand is shifted right as many times as
.

specified by the count (rightmost) operand. The count may be specified either
as an immediate value' in the range ·of o· to 15 (OFH) inclusive, or as the
content of any register above 15H. Details on indirect shifts can be found in
the Overview: If the original high order bit value was 0, zeroes are shifted in. If
the value was 1, ones are shifted in. The last bit shifted out is saved in the
carry. The sticky bit flag is cleared at the beginning of the instruction, and set if
at any time during the shift a 1 is shifted first into the carry flag, and a further
shift cycle occurs.
Temp ..- (COUNT)
do while Temp < > 0
C ..- Low order bit of (DEST)
(DEST) ..- (DEST) / 2 where / is signed division
Temp ..- Temp - 1
end_while

Assembly Language Format:

SHRA

wreg, #count

SHRA

wreg,breg

Object Code Format: [ 00001010

cntlbreg

3-50

wreg

intJ

MCS®·96 INSTRUCTION SET

93. SHRAB - ARITHMETIC RIGHT SHIFT BYTE
Operation: The destination (leftmost) byte operand is shifted right as many times as specified by the count (rightmost) operand. The count may be specified either as
an immerliate vdlue in the range of 0 to 15 (OFH) inclusive, or as the content of
any register above 15H. Details on indirect shifts can be found in the Over. view. If the original high order bit value was 0, zeroes are shifted in. If that
value was 1, ones are shifted in. The last bit shifted out is saved in the carry.
The sticky bit flag is cleared at the beginning of the instruction, and set if at
anytime during the shift a 1 is shifted first into the carry flag, and a further shift
cycle occurs.
(COUNT)
Temp do while Temp < > 0
C, = Low order bit of (DEST)
(DEST) / 2 where / is signed division
(DEST) Temp - 1
Temp end_while

Assembly Language Format:

SHRAB

breg, #count

SHRAB

breg,breg

Object Code Format: [ 00011010

cntlbreg

3-51

breg

MCS®·96 INSTRUCTION SET

94. SHRAJ,. -

ARITHMETIC RIGHT SHIFT DOUBLE-WORD
Operation: The destination (leftmost) double-word operand is shifted right as many times
as specified by the count (rightmost) operand. The count may be specified
either as an immediate value in the range of 0 to 15 (OFH) inclusive, or as the
content of any register above 15H. Details on indirect shifts can be found in
the Overview. If the original high order bit value was 0, zeroes are shifted in. If
the value was 1, ones are shifted in. The sticky bit is cleared at the beginning
of the instruction, and set if at any time during the shift a 1 is shifted first into
the carry flag, and a further shift cycle occurs.
Temp+- (COUNT)
do while Temp < > 0
C +- Low order bit of (DEST)
(DEST) +- (DEST) I 2 where I is signed division
Temp +- Temp - 1
end_while

Assembly Language Format:

SHRAL

Ireg,#count

SHRAL

Ireg,breg

Object Code Format: [ 00001110

cntlbreg

3-52

ireg

inter
95. SHRB -

MCS®·96 INSTRUCTION SET

LOGICAL RIGHT SHIFT'BYTE
Operation: . The destination (leftmost) byte operand is shifted right as many times as specified by the count (rightmost) operand, The count may be specified either as
an immediate value 'in the range of 0 to 15 (OFH) inclusive, or as the content of
any register above 15H. Details on indirect shifts can be found in the Overview. The left bits of the result are filled with zeroes. The last bit shifted out is
saved in the carry. The sticky bit flag is cleared at the beginning of the instruction, and set if at any time during the shift a 1 is shifted first into the carry flag,
and a further shift cycle occurs.
Temp +- (COUNT)
do while Temp < >
C +- Low order bit of (DEST)
(DEST) +- (DEST) / 2 where / is unsigned division
Temp +- Temp - 1
end_while

Assembly Language Format:

SHRB

breg, #count

SHRB

breg,breg

Object Code Format:

00011000

cntlbreg

Flags Affected
ZINlclvlvTlsT

~101~101-1~

3-53

breg

inter
96. SHRL -

MCS®·96 INSTRUCTION SET

LOGICAL RIGHT SHIFT DOUBLE.:WORD
Operation: The destination (leftmost) double-word operand is shifted right as many times
as specified by the count (rightmost) operand .. The count may be specified
either. as an immediate value lin the range of 0 to 15 (OFH) inclusive, or as the
content.of any register above 15H. Details on indirect shifts can be found in
the Overview. The .left· ;bits of the, result are filled with zeroes. The last bit
shifted out is saved in the c<\rry. The sticky bit flag is cleared at the beginning
of the instruction, and set if at any time during the shift a 1 is shifted first into
the carry flag, and a .further shift cycle occurs.
.
Temp . - (COUNT)
do while Temp < > 0
C . - Low order bit of (DEST)
(DSET) . - (DEST) I 2 where I is unsigned division
Temp . - Temp - 1
end_while

Assembly Language Format:

SHRL

Ireg,#count

SHRL

Ireg,breg

Object Code Format: [ 00001100 J [ cnt/breg J [ Ireg· J
Flags Affected
zlNlclvlvTIST

..-101..-101-1..-

3-54

intJ

MCS®·96 INSTRUCTION SET

97. SJMP-SHORT JUMP
Operation: The distance from the end of this instruction to the target label is added to the
program counter, effecting the jump. The offset from the end of this instruction
to the label must be in the range of -1024 to + 1023 inclusive.
PC

Assembly Language Format: SJMP

disp (sign-extended to 16 bits)

cadd

1 [ disp-Iow 1
where xxx holds the three high order bits of the displacement.

Object Code Format: [ 00100xxx

Flags Affected

z 1 N 1 C 1 V 1VT 1ST

-1-1-1-1-198. SKIP - TWO BYTE NO·OPERATION
Operation: Nothing is done. This is actually a two-byte NOP where the second byte can
b~

any value, and is simply ignored. Control passes to the next sequential
instruction.

Assembly Language Format: SKIP

breg

Object Code Format: [ 00000000

breg

3-55

MCS®~96

INSTRUCTION SET

99. ST - STORE WORD
Operation: The value of the leftmost word operand is stored into the rightmost operand.

(DEST) Assembly Language Format:

(SRC)
SAC

DST

wreg,

waop

Object Code Format: [ 110000aa

waop

wreg

100. STB - STORE BYTE
Operation: The value of the leftmost byte operand is stored into the rightmost operand.

(DEST) Assembly Language Format:

STB

(SRC)
SRC

DST

breg,

baop

Object Code Format: [ 110001 aa

baop

breg

3·56

1
MCS®·96 INSTRUCTION SET

101. SUB (Two Operands) - SUBTRACT WORDS
Operation: The source (rightmost) word operand is subtracted from the destination (leftmost) wOrd operand, and the result is stored in the destination. The carry flag
is set as complement of borrow.

(DEST) Assembly Language Format:
SUB
Object Code Format: [

(DEST) DST
wreg,

01101 Oaa

] [

(SRC)

SRC
waop
waop

] [

wreg

]

102. SUB (Three Operands)....;. SUBTRACT WORDS
Operation: The source (rightmost) word operand is subtracted from the second word
operand, and the result is stored in the destination (the leftmost operand). The
carry flag is set as complement of borrow.

(DEST) Assembly Language Format:
SUB
Object Code Format: [

(SRC1) DST
wreg,

010010aa

] [

(SRC2)

SRC1
wreg,
waop

SRC2,
waop
] [

3-57

Sweg] [

Dwreg

]

inter

MCS®·96 INSTRUCTION SET

103. SUBB (Two Operands) - SUBTRACT BYTES
Operation: The source (rightmost) byte is subtracted from the destination (leftmost) byte
operand, and the result is stored in the destination. The carry flag is set as
complement of borrow.
(DEST) +- (DEST) - (SRC)

Assembly Language Format:
SUSS

DST
breg.

Object Code Format: [ 011110aa

SRC
baop
baop

breg

Flags Affected
ZINICIVIVTIST

,...1,...1,...1,...1 t 1 -

104. SUBB (Three Operands) - SUBTRACT BYTES
Operation: The source (rightmost) byte operand.is subtracted from the second byte operand. and the result is stored in the destination (the leftmost operand). The
carry flag is set as complement of borrow.
(DEST) +- (SRC1) - (SRC2)

Assembly Language Format:
SUSS

Object Code Format: [

DST
breg.

010110aa

SRC1
Sbreg
baop

SRC2
baop

Sbreg

3-58

Dbreg

inter

MCS®-96 INSTRUCTION SET

105. SUBC - SUBTRACT WORDS WITH BORROW
Operation: 'The source (rightmost) word operand is subtracted from the destination (Ieft, most) word operand. If the carry flag was clear, 1 is subtracted from the above
result. The result replaces the orignal destination operand. The carry flag is
set as complement of borrow.
(DEST) +- (DEST) -

Assembly Language Format:
SUBC

DST
wreg,

Object Code Format: [ 101010aa

(SRC) -

(1-C)

SRC
waop
waop

wreg

Flags Affected

1 N 1 C 1 V 1 VT 1 ST

i 1,...1,...1,...1 t 1 -

106. SUBCB - SUBTRACT BYTES WITH BORROW
Operation: The source (rightmost) byte operand is subtracted from the destination (leftmost) byte operand. If the carry flag was clear, 1 is subtracted from the above
result. The result replaces the original destination operand. The carry flag is
set as complement of borrow.
(DEST) +- (DEST) -

Assembly Language Format:
SUBCB

DST
breg,

Object Code Format: [ 10111 Oaa

(SRC) -

(1-C)

SRC
baop
baop

breg

3-59

inter

MCS®·96 INSTRUCTION SET

107. TIJMP - TABLE INDIRECT JUMP (80C196KC and 80C196KRonly)
Operation: The execution continues at an address selected· out of a table of addresses.
TBASE .is a word register which contains the 1S-bit address of the beginning
of the table. INDEX is a word register containing the 1S-bit address of a byte
which contains the index into the table. INDEX-MASK is ANDed with the
index. The index must be between 0 and 128.
ADDRESS CALCULATION

= OFFSET

[INDEX] AND INDEX_MASK

(2 • OFFSET) + [TBASE]

Assembly Language Format:

TBASE [lNDEX1.#INDEX-MASK
TIJMP wreg, wreg
# byte
[INDEX]

Object Code Format: [ 11100010 1 [ wreg 1 [

# byte

3-S0

= DEST

[TBASE]

1 [ wreg

X-

intJ
108. TRAP -

MCS®·96 INSTRUCTION SET

SOFTWARE TRAP
Operation: This instruction causes an interrupt-call which is vectored through location
2010H. The operation of this instruction is not effected by the state of the
interrupt enable flag in the PSW (I). Interrupt-calls cannot occur immediately
following this instruction. This instruction is intended for use by Intel provided
development tools. These tools will not support user-application of this instruction ..

SP +- SP - 2
(SP) +- PC
PC +- (2010H)
Assembly Language Format: This instruction is not supported by revision 1.2 of the 8096 assembly language.
Object Code Format: [

11110111

109. XOR -

LOGICAL EXCLUSIVE·OR WORDS
Operation: The source (rightmost) word operand is XORed with the destination (leftmost)
word operand. Each bit is set to 1 if the corresponding bit. in either the source
operand or the destination operand was 1, but not both. The result replaces
the original destination operand.
(OEST) +- (OEST) XOR (SRC)

Assembly Language Format:

XOR
Object Code Format: [

OST
wreg,

100001aa

SRC
waop

1 [ waop 1 [ wreg 1

Flags Affected

ZINlclvlvTlsT
"]"[0[01-1-

3-61

inter
110. XCH -

MCS®·96 INSTRUCTION SET

EXCHANGE WORD (80C196KC only)
Operation: The value of the source (rightmost) word operand is exchanged with the desti'nation (leftmost) operand.
(DEST) -

(SRC)

Assembly Language Format:

DST
wreg,

XCH

Object Code Format: [ 00000100
[

00001011

I ,

1[
1

SRC
waop
waop

Flags Affected

'wreg

I~I:I~I~I:I:I
111. XCHB -

EXCHANGE BYTE (80C196KC only)
Operation: The value of the source (rightmost) byte operand is exchanged with the destination (leftmost) operand.
(DEST) -

Assembly Language Format:
XCHB

Object Code Format:

(SRC)
DST
breg,

00010100
00011011

1[
1

SRC
baop
baop

breg

Flags Affected

I N J C J V 1VT 1ST

-1-1-1-1-1-

3-62

intJ
112. XORB -

MCS®·96 INSTRUCTION SET

LOGICAL EXCLUSIVE·OR BYTES
Operation: The source (rightmost) byte operand is XORed with the destination (leftmost)
byte operand. Each bit is set to 1 if the corresponding bit in either the source
operand or the destination operand was 1, but not both. The result replaces
the original destination operand.

(DEST)
Assembly Language Format:

XORB
Object Code Format: [

(DEST) XOR (SRC)

DST
breg,

100101aa

SRC
baop
baop

breg

3·63

80C196KB User's Guide
and Data Sheets

November 1990

80C196KB
User's Guide

Order Number: 270651-003
4-1

80C196KB USER'S GUIDE

CONTENTS

PAGE

'6.0 Pulse Width Modulation Output

1.0 CPU OPERATION .................... 4-4
1.1 Memory Controller ................. 4-5
1.2 CPU Control ....................... 4-5

(D/A) ................................. 4-36
6.1 Analog Outputs ................... 4-38

1.3 InternalTiming ..................... 4-5
2.0 MEMORY SPACE .................... 4-7

7.0 TIMERS . ............................ 4-39
7.1 Timer1 ........................... 4-39

2.1 Register File ....................... 4-7

7.2 Timer2 ........................... 4-39

2.2 Special Function Registers ......... 4-7

7.3 Sampling on External Timer
Pins ............................... 4-39

2.3 Reserved Memory Spaces ........ 4-11
2.4 Internal ROM and EPROM ........ 4-11

7.4 Timer Interrupts .................. 4-40

2.5 System Bus ...................... 4-12

8.0 HIGH SPEED INPUTS., ............. 4-41
8.1 HSI Modes ....................... 4-42

3.0 SOFTWARE OVERViEW ............ 4-12

8.2 HSI Status ........................ 4-42

3.1 Operand Types ................... 4-12

8.3 HSI Interrupts ..................... 4-43

3.2 Operand Addressing .............. 4-13

8.4 HSllnput Sampling ............... 4-43

3.3 Program Status Word ............. 4-15

8.5 Initializing the HSI ................. 4-43

3.4 Instruction Set .................... 4-17
3.5 80C196KB Instruction Set
Additions and Differences .......... 4-25
3.6 Software Standards and
Conventions ....................... 4~25

9.0 HIGH SPEED OUTPUTS ............ 4-43

3.7 Software Protection Hints ......... 4-26

9.3 HSO Status ....................... 4-46

4.0 PERIPHERAL OVERVIEW .......... 4-26
4.1 Pulse Width Modulation Output
(D/A) .............................. 4-27

9.4 Clearing the HSO and Locked
Entries ............................. 4-46

9.1 HSO Interrupts and Software
Timers ............................. 4-44
9.2 HSO CAM ........................ 4-45

4.2 Timers ........................... 4-27

9.5 HSO Precautions ....... " ........ 4-47
9.6 PWM USing the HSO, ............. 4-47

4.3 High Speed Inputs (HSI) .......... 4-27

9.7 HSO Output Timing ............... 4-48

4.4 High Speed Outputs (HSO) ....... 4-27

10.0 SERIAL PORT ..................... 4-48

4.5 Serial Port ........................ 4-27

10.1 Serial Port Status and Control ... 4-50

4.6 AID Converter .................... 4-29

10.2 Serial Port Interrupts ............. 4-52

4.7110 Ports ......................... 4-29

10.3 Serial Port Modes ............... 4-52

4.8 Watchdog Timer .................. 4-29

10.4 Multiprocessor
Communications ................... 4-54

5.0 INTERRUPTS ....................... 4-30
5.1 Interrupt Control .................. 4-32
5.2 Interrupt Priorities ................. 4-32 ,
5.3 Critical Regions ................... 4-34
5.4 Interrupt Timing ................... 4-34
5.5 Interrupt Summary ....... , ........ 4-35

4-2

11.0 AID CONVERTER .................
11.1 AID Conversion Process ........
11.2 AID Interface Suggestions ......
11.3 The AID Transfer Function ......
11.4 AID Glossary of Terms ..........

4-54
4-56
4-56
4-57
4-61

80C196KB USER'S GUIDE
CONTENTS

CONTENT~

PAGE

12.0110 PORTS ........................ 4-63
12.,1 Input Ports ...... : ................4-63
12.2 Quasi-Bidirectional Ports ........ 4-63
12.3 Output Por~s ............' ......... 4-65
12.4 Ports 3 and 4/ ADG-15 .......... 4-66

PAGE

15.0 EXTERNAL MEMORY
INTERFACING ....................... 4-74
15.1 Bus Operation ................... 4-74 ,
15.2 Chip Configuration Register ...... 4-75
" 15.3 Bus Width ................... , .. , 4-78
15.4 HOLD/HLDA Protocol ....... ,., .4-79

13.0 MINIMUM HARDWARE

15.5 AC Timing Explanations ..... ·.... 4-81

CONSiDERATIONS ...... , ............ 4-67
13.1 Power Supply ................... 4-67

15.6 Memory System Examples ...... 4-86
15.7 I/O Port Reconstruction ......... 4-88

13.2 Noise Protection Tips ............ 4-67

16.0 USING THE EPROM ... , ........... 4-88

13.3 Oscillator and Internal Timings ... 4-67
13.4 Reset and Reset Status ......... 4-68

16.1 Power-Up and Power-Down ..... 4-88

13.5 Minimum Hardware
Connections ....................... 4-71

16.2 Reserved Locations ............. 4-89
16.3 Programming Pulse Width
Register (PPW) ..........' ...... , ... 4-90

14.0 SPECIAL MODES OF

16.4 Auto Configuration Byte
Programming Mode ................ 4-91

OPERATION ..... , ................... 4-72
14.1 Idle Mode ....................... 4-72

16.5 Auto Progr.amming Mode ........ 4-91

14.2 Powerdown Mode .... ~ .......... 4-72
14.3 ONCE and Test Modes .......... 4-73

16.6 Slave Programming Mode ....... 4-93
16.7 Run-Time Programming ......... 4-95
16.8 ROM/EPROM Memory Protection
Options ............................ 4-96
16.9 Algorithms ..................... , 4-97

4-3

80C196KB USER'S GUIDE

The 80C196KB family is a CHMOS branch of the
MCS@-96 family. Other members of the MCS~96 family. incljlde the 8096BH and 8098. All of.. the MCS-96
components share a common instruction set and ~rchi
tecture. However the CHMOS components have enhancements to provide higher performance at lower
power consumptions. To further decrease power usage,
these parts can be placed into idle and powerdown
I!loi;les.

, There ,are many members of the 80C196KB family, so
, to provide easier reading this manual will refer to the
80C196KB family generically as the 8OC196KB.
Where information applies only to specific components
it will be clearly indicated.
The 80CI96KB can be separated into four sections for
the, purpose of des~ribing its oper~tion. A block diagram is shown in Figure I-I. There is the CPU and
architecture, the instruction set, the peripherals and the
bus unit. Each of the sections will be sub-divided as the
discussion progresses. Let us first examine the CPU.

MCS-96 family members are all high-performance microcontrollers with a 16-bit CPU and at least 230 bytes
of on-chip RAM. They are register-to-register machines, so no accumulator is needed, and most operations can be quickly performed from or to any of the
registers. In addition, the register operations can control the many peripherals which are available on the'
chips. These peripherals include a serial port, A/D converter, PWM output, up to 48 I/O lines and a HighSpeed I/O subsystem which has 2 16·bit timer/counters, an 8-level input capture FIFO and an 8-entry programmable output generator.

1.0 CPU OPERATION
The major components of the CPU on the 80C196KB
are the Register File and the Register/Arithmetic Logic Unit (RALU). Communication with the outside
world is done through either the Special Function Registers (SFRs) or the Memory Controller. The RALU
does not use an accumulator. Instead, it operates directly on the 256-byte register space made up of the
Register File and the SFRs. Efficient 110 operations
are possible by directly controlling the I/O through the
SFRs. The main benefits of this structure are the ability
to quickly change context, absence of accumulator bottleneck, and fast throughput and I/O times.

Typical applications for MCS-96 products are closedloop control and mid-range digital signal processing.
Mc;S-96 products are being ,used in moderns, motor
controls, printers, engine controls, photocopiers, antilock brakes, air conditioner temperature controls, disk
drives, and medical instrumentation.

v EF

ANGND

_-_

.--------------------.

r-~--~~ :CrPU______•

.....

,
... ,:,
,,,
,

CONTROL
SIGNALS

PORT 3

~f~:
l
....
BUS

'---

PORT 4

1+---1--

AID

ALTERNATE
FUNCTIONS

HSO

270651-1

Figure 1-1. 80C196KB Block Diagram
4-4

80C196KB USER'S GUIDE

The CPU on the 80C196KB is 16 bits wide and connects to the interrupt controller and the memory controller by a 16-bit bus. In addition, there is an 8-bit bus
which transfers instruction bytes from the memory con.troller to the CPU. An extension of the 16-bit bus connects the CPU to the peripheral devices.

REGISTERI ALU (RALU)

Most calculations performed by the 80C196KB take
place in the RALU. The RALU, shown in Figure 1-2,
contains a 17-bit ALU, the Program Status Word
(PSW), the Program Counter (PC), a loop counter, and
three temporary registers. All of the registers are 16bits or 17-bits (16+ sign extension) wide. Some of the
registers have the ability to perform simple operations
to off-load the ALU.
.

1.1 Memory Controller
The RALU talks to the memory, except for the locations in the register file and SFR space, throug1). the
memory controller. Within the memory controller is a
bus controller, a four byte queue and a Slave Program
Counter (Slave PC). Both the internal ROMIEPROM
bus and the external·memory bus are driven by the bus
controller. Memory access requests to the bus controller can come from either the RALU or the· queue, with
queue accesses having priority. Requests from the
queue are always for instruction at the address in the
slave PC.

A separate incrementor is used for the Program Counter (PC) as it accesses operands. However, PC changes
due to jump,s, calls, returns and inrerrupts must be handled through the ALU. Two of the temporary registers
have their own shift logic. These registers are used for
the operations which require logical shifts, including
Normalize, Multiply, and Divide. The "Lower Word"
and "Upper Word" are used together for the 32-bit
instructions and as temporary registers for many instructions. Repetitive shifts are counted by the 6-bit
"Loop Counter".

By having program fetches from memory referenced to
the slave PC, the processor saves time as addresses seldom have to be sent to the memory controller. If the
address sequence changes because of a jump, interrupt,
call or return, the slave PC is loaded with a new value,
the queue· is flushed, and· processing continues.

A third temporary register stores the second operand of
two operand instructions. This includes the multiplier
during multiplications and the divisor during divisions.
To perform subtractions, the outp~t of this register can
be complemented before being placed into the "B" input of the ALU.

Execution speed is increased by using a queue since it
usually keeps the next instruction byte available. The
instruction execution times shown in Section 3 show
the normal execution times with no wait states added
and the 16-bit bus selected. Reloading the slave PC and
fetching the first byte of the new instruction stream
takes 4 state times. This is reflected in the jump taken!
not-taken times shown in the table.

Several constants, such as 0, 1 and 2 are stored in the
RALU to speed. up certain calculations. (e.g. making a
2's complement number or performing an increment or
decrement instruction.) In addition, single bit masks for
bit test instructions ate generated in the constant register based on the 3-bit Bit Select register.

When debugging code using a logic analyzer, one must
be aware of the queue. It is not possible to determine
when an instruction will begin executing by simply
watching when it is fetched, since the queue is filled in
advance of instruction execution.

1.3 Internal Timing
The 80C196KB requires an input clock on XTALI to
function. Since XTALI and XTAL2 are the input and
output of an inverter a crystal can be used to generate
the clock. Details of the circuit and suggestions for its
use can be found in Section 13:

1.2 CPU Control
Internal operation of the 80C196KB is based on the
crystal or external oscillator frequency divided by 2.
Every 2 oscillator periods is referred to as one "state
time", the basic time measurement for all 80C196KB
operations. With a 12 MHz oscillator, a state time is
167 nanoseconds. With an 8 MHz oscillator, a state
time is 250 nanoseconds, the same as an 8096BH running with a 12 MHz oscillator. Since the 80C196KB
will be run at many frequencies, the times given
throughout this chapter will be in state times or
"states", unless otherwise specified. A clock out

A microcode engine controls the CPU, allowing it to
perform operations with any byte, word or double word
in the 256 byte register space. Instructions to the CPU
are taken from the queue and stored temporarily in the
instruction register. The microcode engine decodes the
instructions .and generates the correct sequence of
events to have the RALU p~rform the desired function.
Figure 1-2 shows the memory controller, RALU, instruction register and the control unit.

4-5

l
Memory
Bus

"TI

;1
!"

:::I

i:
CD

.j>.

m -<0
0
0

:::J

::::

i'
CD

H
H
IH

Upper word
register
w/shifter
Lower word
register
w/shifter

...o
i;:IIi;

Processor
Status
Word

Special
Function
Registers

::D

cii

M
ALU

c;)
CPU

E
o

~ Control

and Status
Signals

iii"

CD
DI

CPU BUSES

270651-2

inter

80C196KB USER'S GUIDE

(CLKOUT) signal, shown in Figure 1-3, is provided as
an indication of the internal machine state. Details on
timing relationships can be found in Section 13.

2.1 Register File
Locations OOH through OFFH contain the Register File
and Special Function Registers, (SFRs). The RALU
can operate on any of these 256 internal register locations, but code can not be executed from them. If an
attempt to execute instructions from locations OOOH
through OFFH is made, the instructions will be fetched
from external memory. This section of external memory is reserved for use by Intel development tools

PHASE1~
,

PHASE2~
,

The internal RAM from location OlSH (24 decimal) to
OFFH is the Register File. It contains 232 bytes of
RAM which can be accessed as bytes (8 bits), words
(16 bits), or double-words (32 bits). Since each of these
locations can be used by the RALU, there are essentially 232 "accumulators". This memory region, as well as
the status of the majority of the chip, is kept intact
while the chip is in the Powerdown Mode. Details on
Powerdown Mode are discussed in Section 14.

CLKOUT~
270651-3,

Figure 1·3. Internal Clock Waveforms

2.0 MEMORY SPACE
The addressable memory space on the 80C196KB consists of 64K bytes, most of which is available to the user
for program or data memory. Locations which have
special purposes are OOOOH through OOFFH and
1FFEH through 2080H. All other locations can be
used for either program or data storage or for memory
mapped peripherals. A memory map is shown in Figure

Locations 18H and 19H contain the stack pointer.
These are not SFRs and may be used as standard RAM
if stack operations are not being performed. Since the
stack pointer is in this area, the RALU can easily operate on it. The stack pointer must be initialized by the
user program and can point anywhere in the 64K memory space. Operations to the stack cause it to build
down, so the stack pointer should be initialized to 2
bytes' above the highest stack location, and must be
word aligned.

2-1.

OFFFFH
EXTERNAL MEMORY OR I/O
4000H
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY'

2.2 Special Function Registers
2080H

Locations OOH through 17H are the 1/0 control registers or SFRs. All of the peripheral devices on the
80C196KB (except Ports 3 and 4) are controlled
through these registers. As shown in Figure 2-2, three
SFR windows are provided on the 80C196KB.

RESERVED
2040H
UPPER 8 INTERRUPT VECTORS
(NEW ON 80C196KB)
2030H
ROM/EPROM SECURITY KEY
2020H

Switching between the -windows is done using the Window Select Register (WSR) at location 14H in all of the
windows. The PUSHA and POPA instructions push
and pop the WSR so it is easy to change between windows. Only three values may be written to the WSR, 0,
14 and 15. Other values are reserved for use in future
parts, and will cause unpredictable operation.

RESERVED
2019H
CHIP CONFIGURATION BYTE
2018H
RESERVED
2014H

LOWER INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
2000H

Window 0, the register window selected with WSR = 0,
is a superset of the one used on the 8096BH. As depict·
ed in Figure 2-3, it has 24 registers, some of which have
different functions when read than when written. Registers which are new to the 80Cl96KB or have changed
functions from the 8096 are indicated in the figure.

PORT 3 AND PORT 4
1FFEH
EXTERNAL MEMORY OR I/O
0100H
INTERNAL DATA MEMORY· REGISTER FILE
(STACK POINTER. RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY

OOOOH

Figure 2·1. 80C196KB Memory Map

4-7

80C196KB USER'S GUIDE

Listed registers
are present in
all three windows
16H

16H

WSR

14H
12H

INT MASKlIPENDl

16H

WSR

14H

INT MASK1/PENDl

12H

10H

OEH

TIMER2

OCH
OAH
08H

OCH

OAH

INT MASK/PEND

06H

INT MASK/PEND

08H

04H

02H

ZERO REG

INT MASK/PEND

06H

04H

02H

T2CAPTURE

OAH

06H

04H

OOH

T2CAPTURE

OCH

WSR
INT MASK1/PENDl

02H

ZERO REG

OOH

READ/WRITE
,WSR ~ 0

OOH

PROGRAMMING
WSR ~ 14

ZERO REG
WRITE/READ
WSR ~ 15

Figure 2-2. Multiple Register Windows

19H

STACK POINTER

18H

STACK POINTER

17H

'IOS2

17H

PWM_CONTROL

16H

10Sl

16H

10Cl

15H

10SO

15H

lOCO

14H

'WSR

14H

'WSR

13H

'INT

MASK 1

13H

'INT

MASK 1

12H

'INT

PEND 1

12H

'INT

PEND 1

'SP_CON

llH

'SP_STAT

llH

10H

PORT2

10H

PORT2

10H

RESERVED"

OFH

PORTl

OFH

PORn

OFH

RESERVED"

OEH

PORTO

OEH

BAUD RATE

OEH

RESERVED"

ODH

TIMER2 (HI)

ODH

TIMER2(HI)

ODH

'T2 CAPTURE (HI)

OCH

TIMER2 (LO)

OCH

TIMER2 (LO)

OCH

'T2 CAPTURE (LO)

OBH

TIMERl (HI)

OBH

'IOC2

OAH

TIMERl (LO)

OAH

WATCHDOG

09H

INT_PEND

09H

INT_PEND

08H

INT

OSH

INT

07H

SBUF(RX)

07H

SBUF(TX)

06H

HSI

STATUS

06H

HSO

COMMAND

05H

HSI

TIME (HI)

05H

HSO

TIME (HI)

04H

HSI_TIME (LO)

04H

HSO

TIME (LO)

03H

AD_RESULT (HI)

03H

HSI_MODE

02H

AD_RESULT (LO)

02H

AD_COMMAND

01H

ZERO REG (HI)

01H

ZERO REG (HI)

OOH

ZERO REG (LO)

,OOH

ZERO REG (LO)

MASK

WHEN READ

WSR

WSR ~ 15

MASK

WHEN WRITTEN

OTHER SFRS IN WSR 15 BECOME
READABLE IF THEY WERE WRITABLE
IN WSR ~ 0, AND WRITABLE IF THEY
WERE READABLE IN WSR ~ 0

04H

'NEW OR CHANG~D REGISTER
FUNCTION FROM S096BH
"RESERVED REGISTERS SHOULD NOT
BE WRITTEN OR READ

Figure 2-3. Special Function Registers

4-8

PPW
WSR ~ 14

inter

80C196KB USER'S GUIDE

Description

Zero Register - Always ~eads as a zero, useful for a base when indexing and as a
constant for calculations and compares.

AD_RESULT

AID Result Hi/low - low and high order results of the AID converter

AD_COMMAND

AID Command Register - Controls the AID

HSI_MODE

HSI Mode Register - Sets the mode of the High Speed Input unit.

HSI TIME
HSO_TIME

HSI Time Hillo - Contains the time at which the High Speed Input unit was triggered.
HSO Time Hi/lo - Sets the time or count for the High Speed Output to execute the
command in the Command Register.

HSO_COMMAND

HSO Command Register - Determines what will happen at the. time loaded into the
HSO Time registers.
'

HSI_STATUS

HSI Status Registers - Indicates which HSI pins were detected at the time in the HSI
Time registers and the current state of the pins. In Window 15 - Writes to pin
detected bits, but not current state bits.

SBUF(TX)

Transmit buffer for the serial port, holds contents to be outputted. last written value
is readable in Window 15.

SBUF(RX)

Receive buffer for the serial port, holds the byte just received by the serial port.
Writable in Window 15.

INT_MASK

Interrupt Mask Register - Enables or disables the individual interrupts.

INT_PEND

Interrupt Pending Register - Indicates that an interrupt signal has occurred on one of
the sources and has not been serviced. (also INT_PENDING)

WATCHDOG

Watchdog Ti,mer Register - Written periodically to hold off automatic reset every 64K
state times. Returns upper byte of WDT counter in Window 15.

TIMER1

Timer 1 Hi/lo - Timer1 high arid low bytes.

TIMER2

Timer 2 Hillo - Timer2 high and low bytes.

10PORTO

Port 0 Register - levels on pins of Port O. Reserved in Window 15.

BAUD_RATE

IOPORT1

Port 1 Register - Used to read or write to Port 1. Reserved in Window 15

IOPORT2

Port 2 Register - Used to read or write to Port 2. Reserved in Window 15

SP_STAT

Serial Port Status - Indicates the status of the serial port.

SP_CON

Serial Port Control - Used to set the mode of the serial port.

10SO

1/0 Status Register 0 - Contains information on the HSO status. Writes to HSO pins
in Window ,15.

IOS1

1/0 Status Register 1 - Contains information on the status of the timers and of the'
HSI.

lOCO

I/O Control Register 0 - Controls alternate functions of HSI pins, Timer 2 reset
sources and Timer 2 clock sources.

IOC1

1/0 Control Register 1 - Controls alternate functions of Port 2 pins, timer interrupts
and HSI interrupts.

PWM

CONTROL

INT_PEND1
INT
IOC2

MASK1

Pulse Width Modulation Control Register - Sets the duration of the PWM pulse.
Interrupt Pending register for the 8 new interrupt vectors (also INT_PENDING1)
Interrupt Mask register for the 8 new interrupt vectors
1/0 Control Register 2 - Controls new 80C196KB features

IOS2

I/O Status Register 2 - Contains information on HSO events

WSR

Window Select Register - Selects register window
Figure 2-4. Special Function Register Description

4-9

inter

80C196KB USER'S GUIDE

Programming control and test operations are done in
Window 14. Registers in this window that are not labeled should be considered reserved and should not be
either read or written.
In register Window IS (WSR= IS), the operation of
the SFRs is changed, so that those which were readonly in Window 0 space are write-only and vice versa.
The only major exception to this is that Timer2 is read/
write in Window 0, and T2 Capture is read/write
AD_COMMAND (02H) ,
AD_RESULT (02H, 03H)
HSI_MODE (03H)
HSI_TIME (04H, OSH)
HSO_TIME (04H, 05H)
HSI_STATUS (06H)
HSO_COMMAND (06H)
SBUF(RX) (07H)
SBUF(TX) (07H)
WATCHDOG (OAH)
TIMER I (OAH, OBH)
TIMER2 (OCH, ODH)
IOC2 (OBH)
BAUD_RATE (OEH)
PORTO (OEH)
SP_STAT(llH)
SP_CON (IIH)
IOS0 (ISH)
lOCO (ISH)
IOS1 (l6H)
lOCI (16H)
IOS2 (17H)
'PWM_CONTROL (17H)

in Window IS. (Timer2 was read-only on the 8096.)
Registers which can be read and written in Window 0
can also be read and written in Window IS.
Figure 2-4 contains brief descriptions of the SFR registers. Detailed descriptions are contained in the section
which discusses the peripheral controlled by the register. Figure 2-5 contain.s a description of the alternate
function in Window IS.

- Read the last written command
- Write a value into the result register
~ Read the value in HSI_MODE
- Write to FIFO Holding register
- Read the last value placed in the holding register
- Write to status bits but not to HSI pin bits. (Pin bits are I, 3, 5, 7)
- Read the last value placed in the holding register
- Write a value into the recc:;ive buffer
- Read the last value written to the transmit buffer
- Read the value in the upper byte of the WDT
- Write a value to Timerl
- ReadIWrite the Timer2 capture register.
(Timer2 read/write is done with WSR = 0)
- Last written value is readable, except bit 7 (Note I)
- No function, cannot be read
- No function, no output drivers on the pins
- Set the status bits, TI and RI can be set, but it will not cause an interrupt
- Read the current control byte
- Writing to this register controls the HSO pins. Bits 6 and 7 are inactive for
writes.
- Last writtc:n value is readable, except bit I (Note I)
- Writing to this register will set the status bits, but not cause interrupts. Bits
6 and 7 are not functional.
- Last written value is readable
- Writing to this register will set the status bits, but not cause interrupts.
- Read the duty cycle value writtc:n to PWM_CONTROL

NOTE:
1. IOC2.7 (CAM CLEAR) and IOCO.1 (T2RST) are not latched and will read as a 1 (precharged bus).

Figure 2-5. Alternate SFR .Function In Window 15

4-10

80C196KBUSER'S GUIDE

change the contents of this location. Refer to Section
15.2 for more information about bus contention during
CCB fetch.

Within the SFR space are several registers and bit locations labeled "RESERVED". These locations should
never be written or read. A reserved bit location should
always be written with 0 to maintain compatibility with
future parts. Values read from these locations may
change from part to part or over temperature and voltage. Registers and bits which are not labeled should be
treated as reserved registers and bits. Note that the default state of internal registers is 0, while that for external memory is 1. This is because SFR functions are
typically disabled with a zero, while external memory is
typically erased to all Is.

FFFFH
EXTERNAL MEMORY
ORIIO
4000H

Caution must be taken when using the SFRs as sources
of operations or as base or index registers for indirect or
indexed operations. It is possible to get undesired results, since external events can change SFRs and some
SFRs clear when read. The potential for an SFR to
~hange value must be taken into account when operatmg on these registers. This is particularly important
when high level languages are used as they may not
always make allowances for SFR-type registers. SFRs
can be operated on as bytes or words unless otherwise
specified.

INTERNAL PROGRAM
STORAGE ROMIEPROM
OR
EXTERNAL MEMORY

20BOH

RESERVED

2074H-207FH

VOLTAGE LEVELS

2072H-2073H

SIGNATURE WORD

2070H-2071H

RESERVED

2040H-206FH

INTERRUPT VECTORS

2030H-203FH

SECURITY KEY

2020H-202FH

RESERVED

2019H-201 FH

CHIP CONFIGURATION BYTE

201BH

RESERVED

2015H-2017H

PPW

2014H

INTERRUPT VECTORS

2000H-2013H

Figure 2·6. Reserved Memory Spaces

2.3 Reserved Memory Spaces

Resetting the 80CI96KB causes instructions to be
fetched starting from location 2080H. This location was
chosen to allow a system to have up to 8K of RAM
continuous with the register file. Further information
on reset can be found in Section 13.

Locations IFFEH and IFFFH are used for Ports 3 and
4 respectively, allowing easy reconstruction of these
ports if external memory is used. Ari example of reconstructing the I/O ports is given in Section 15. If ports 3
and 4 are not going to be reconstructed and internal
ROM/EPROM is not used, these locations can be
treated as any other external memory location.

2.4 Internal ROM and EPROM
When a ROM part is ordered, or an EPROM part is
programmed, the internal memory locations 2080H
through 3FFFH are user specified, as are the interrupt
vectors, Chip Configuration Register and Security Key
in locations 2000H through 207FH. Location 2014H
contains the PPW (Programming Pulse Width) register. The PPW is used solely to program 87CI96KB
EPROM devices and is a reserved location on ROM
and ROMless devices.

Many reserved and special locations are in the memory
area between 2000H and 2080H. In this area the 18
interrupt vectors, chip configuration byte, and security
key are located. Figure 2-6 shows the locations and
functions of these registers. The interrupts, chip configuration, and security key registers are discussed in Sections 5: 16, and 17 respectively. With one exception, all
unspecified addresses in locations 2000H through
207FH, including those marked "Reserved" are reserved by Intel for use in testing or future products.
They must be filled with the Hex value FFH to insure
compatibility with future devices. Location 2019H
should contain 20H to prevent possible bus contention
during the CCB fetch cycle. NOTE: 1. This exception
applies only to systems with a 16-bit bus and external
program memory. 2. Previously designed systems
which do not experience bus contention don't need to

Instruction and data fetches from the internal ROM or
EPROM occur only if the part has ROM or EPROM
EA is tied high, and the address is between 2000H and
3FFFH. At all other times data is accessed from either
the internal RAM space or external memory and instructions are fetched from external memory. The EA
pin is latched on RESET rising. Information on programming EPROMs can be found in Section 16.

4-11

80C196KB USER'S GUIDE

The 80CI96KB provides a ROM/EPROM lopk feature
to allow the program to be locked against reading
and/or writing the internal program memory. In order
to maintain security, code can not be executed out of
the last three locations of internal ROM/EPROM if
the lock is enabled. Details on this feature are in Section 17.

2.5 System Bus
There are several modes of system bus operation on the
80C196KB. The standard bus mode uses a 16-bit multiplexed address/data bus. Other bus modes include an
8-bit mode and a mode in which the bus size can dy-.
namically be switched between 8-bits and 16-bits.
Hold/Hold Acknowledge (HOLD/HLDA) and Ready
signals are available to create a variety of memory systems. The READY line extends the width of the RD
(read) and WR (write) pulses to allow access of slow
memories. Multiple processor systems with shared
memory can be designed using HOLD/HLDA to keep
the 80CI96KB off the bus. Details on the System Bus
are in Section 15.

3.0 SOFTWARE OVERVIEW
This section provides information on writing programs
to execute in the 80C196KB. Additional information
can be found in the following documents:
MCS®-96 MACRO ASSEMBLER USER'S GUIDE
Order Number 122048 (Intel Systems)
Order Number 122351 (DOS Systems)
MCS®-96 UTILITIES USER'S GUIDE
Order Number 122049 (Intel Systems)
Order Number 122356 (DOS Systems)
PL/M-96 USER'S GUIDE
Order Number 122134 (Intel Systems)
Order Number 122361 (DOS Systems)

These are the same as the names for the general. data
registers used in the 8086. It is important to note that in.
the 80C 196KB these are not dedicated registers but
merely the symbolic names assigned by the programmer to an eight byte region within the on-board register
file.

3.1 Operand Types
The MCS-96 architecture supports a variety of data
types likely to be uS,eful in a control application. To
avoid confusion, the name of an operand type is capitalized. A "BYTE" is an unsigned eight bit variable; a
"byte" is an eight bit unit of data of any type.
BYTES

BYTES are unsigned 8-bit variables which can take on
the values between 0 and 255. Arithmetic and relational
operators can be applied to BYTE operands but the
result must· be interpreted in modulo 256 arithmetic.
Logical operations on BYTES are applied bitwise. Bits
within BYTES are labeled from 0 to 7, with 0 being the
least significant bit.
WORDS

,WORDS are unsigned 16-bit variables which can take
on the values between 0 and 65535 .. Arithmetic al).d
relational operators can be applied to WORD operands
but the result must be interpreted modulo 65536. Logical operations on WORDS are applied bitwise.. Bits
within wor,ds are labeled from 0 to 15 with 0 being the
least significant bit. WORDS must be aligned at even
byte boundaries in the MCS-96 address space. The least
significant byte of the WORD is in the even byte address and the most significant byte is in the next higher
(odd) address. The address of a word is the address of
its least significant byte. Word operations to odd addresses are not guaranteed to operate in a consistent
manner.
SHORT-INTEGERS

C-96 USER'S GUIDE
Order Number 167632 (DOS Systems)

SHORT-INTEGERS are 8-bit signed variables which
can' take on the, values' between -128 and + 127,
Arithmetic operations which generate results outside of
the range of a SHORT-INTEGER will set the overflow
indicators in the program status word. The actual numeric result returned will be the same as the equivalent
operation on BYTE variables.

Throughout this chapter short sections of code are used
to illustrate the operation of the device. For these sections it is assumed that the following set of temporary
registers has· been declared:
AX, 13X, CX, and DX are 16-bit registers.
AL is the low byte of AX, AH is the high byte.
BL is the low byte of BX
CL is the low byte of CX
DL is the low byte of DX

4-12

inter

8OC196KB USER'S GUIDE

LONG-INTEGERS can also be normalized. For these
operations a LONG-INTEGER variable must reside in
the onboard register file of the 80Cl96KB and be
aligned at an address which is evenly divisible by 4. A
LONG-INTEGER is addressed by the address of its
least significant byte.

INTEGERS

INTEGERS are 16-bit signed variables which can take
on the values. between -32,768 and +32,767. Arithmetic operations which generate results outside of the
range of an.INTEGERwill set the overflow indioators
in the program status word. The actual numeric result
returned will be the same as the equivalent operation on
WORD variables. INTEGERS conform to the same
alignment and addressing rules as do WORDS.

LONG-INTEGER operations which are not directly
supported can be easily implemented with two INTEGER operations. For consistency with Intel provided
software, the user should adopt the conventions for ad- .
dressing LONG operands which are discussed in Section 3.6.
.

BITS

BITS are single-bit operands which can take on the
Boolean'values of true and false. In addition to the normal support for bits as components of BYTE and
WORD operands, the 80Cl96KB provides for the direct testing of any bit in the intemal register file. The
MCS-96 architecture requires that bits be addressed as
components of BYTES or WORDS, it does not support
the direct addressing of bits that can occur in the MCS51 architecture.

DOUBLE-WORDS are unsigned 32-bit variables
which can take on the values between 0 and
4,294,967,295. The MCS-96 architecture provides direct support for this operand type for shifts, as the dividend in a 32-by-16 divide and the product of a 16-by-16
multiply, and for double-word comparisons; For these
operations a DOUBLE-WORD variable must reside in
the on-board register file of the 80C196KB and be
aligned at an address which is evenly divisible by 4. A
DOUBLE-WORD operand is addressed by the address
of its least significant byte. DOUBLE-WORD operations .which are not directly supported can be easily
implemented with two WORD operations. For consistency with Intel provided software the user should adopt
the conventions for addressing DOUBLE-WORD operands which are discussed in Section 3.5.

3.2 Operand Addressing

Operands are accessed within the address space of the
8OC196KB with one of six basic addressing modes.
Some of the details of how these addressing modes
work are hidden by the assembly language. If the programmer is to take full advantage of the architecture, it
is important that these details be understood. This section will describe the addressing modes as they are handled by the hardware. At the end of this section the
addressing modes will be described as they are seen
through the assembly language. The six basic address
modes which will be described are termed register-direct, indirect, indirect with auto-increment, immediate,
short-indexed, and long-indexed. Several other useful
addressing operations can be achieved by combining
these basic addressing modes with specific registers
such as the ZERO register or the stack pointer.
REGISTER-DIRECT REFERENCES

The register-direct mode is used to directly access a
register from the 256 byte on-board register file. The
register is selected by an 8-bit field within the instruction and the register address must conform to the operand type's alignment rules. Depending on the instruction, up to three registers .can take part in the calculation.

LONG-INTEGERS

LONG-INTEGERS are 32-bit signed variables which
can take on the values between -2,147,483,648 and
+ 2,147,483,647. The MCS-96 architecture provides direct support for this data type for shifts, as the dividend
in a 32-by-16 divide and the product of a 16-by-16 multiply, and for double-word comparisons.

Examples

ADD
MUL
INCB

AX,BX,CX
AX,BX
CL

AX:=BX+CX.
AX:=AX*BX
CL:=CL+l

inter

80C196KBUSER'S'GUIDE

INDIRECT REFERENCES

The indirect mode is used to access an operand by placing its address in a WORD variable in the register file.
The calculated address must conform to the alignment
rules for the operand type. Note that the indirect address can refer to an operand anywhere within the address space of the 80C196KB, including the register

file. The register which contains the indirect address is
selected by an eightbiffield within the instruction. An
instruction can contain only one indirect reference and
the remainil!g operands of the instruction (if any) must
be register-direct ,references.

Examples

LD
ADDB
POP

AX, [AX]
AL,BL, [CX]
[AX]

AX:=MEM_WORD(AX)
AL:=BL+MEM_BYTE(CX)
MEM_WORD(AX) :=MEM_WORD(SP) ; SP:=SP+2

INDIRECT WITH AUTO-INCREMENT REFERENCES

This addressing mode is the same as the indirect mode
except that the WORD variable which contains the Indirect address is incremented after it is used to address
the operand. If the instruction oper~tes, on BYTES or

SHORT-INTEGERS the indirect address variable will
be incremented by one'. If the instruction operates on

WORDS or INTEGERS the indirect address ,variable
will be incremented by two.

Examples

LD
AX, [BX]+
ADDB AL,BL,[CX]+
PUSH [AX]+

AX:=MEM_WORD(BX) ; BX:=BX+2
AL:=BL+MEM_BYTE(CX) ; CX:=CX+1.
SP:=SP-2 ;
MEM_WORD(SP) :=MEM~WORD(AX)
AX:=AX+2

IMMEDIATE REFERENCES

INTEGER operands the field is 16 bits wide. An instruction can contain only one immediate 'reference and
the remaining operand(s) must be register-direct references.

This addressing mode allows an operand to be taken
directly from ,a field in the instruction. For operations
on BYTE or SHORT-INTEGER operands this field is
eight bits wide. For operations on WORD or
Examples

ADD AX,#340
PUSH #1234H
DIVB AX,#lO

AX:=AX+340
SP:=SP-2; MEM_WORD(SP) :=1234H
AL:=AX/10; AH:=AX MOD 10

SHORT-INDEXED REFERENCES

Sil1.ce the eight bit field ~ign-extended,theeffective
address can be up to 128 bytes before the address in the
WORD variable and up to 127 bytes after it. An instruction can contain only one short-indexed reference
and the remaining operand(s) must be register-direct
references.

In this addressing mode an eight bit field in the instruction selects a WORD variable in the register file which
contains an address. A second eight bit field in the instruction stream is sign-extended and summed with the
WORD variable to form the address of the operand
which will take part in the calculation.
Examples

LD
MULB

AX,12[BX]
AX,BL,3[CX]

AX:=MEM_WORD(BX+12)
AX:=BL*MEM_BYTE(CX+3)
4-14

80C196KB USER'S GUIDE

LONG-INDEXED REFERENCES

This addressing mode is like the short-indexed mode
except that a 16-bit field is taken from the instruction
and added to the WORD variable to form the address
of the operand. No sign extension is necessary. An in-

struction can contain only one long-indexed reference
and the remaining operand(s) must be register-direct
references.

Examples

AND AX,BX,TABLE[CX]
ST
AX, TABLE [BX]
ADDB AL,BL,LOOKUP[CX]

AX:=BX AND MEM_WORD(TABLE+CX)
MEM_WORD(TABLE+BX) :=AX
AL:=BL+MEM_BYTE(LOOKUP+CX)

ZERO REGISTER ADDRESSING

The first two bytes in the register file are fixed at zero
by the 80CI96KB hardware. In addition to providing a
fixed source of the constant zero for calculations and
comparisons, this register can be used as the WORD

variable in a long-indexed reference. This combination
of register selection and address mode allows any location in memory to be addressed directly.

Examples

ADD
POP

AX,1234[0]
5678[0]

AX:=AX+MEM_WORD(1234)
MEM_WORD(5678) :=MEM_WORD(SP)
SP:=SP+2

STACK POINTER REGISTER ADDRESSING

The system stack pointer in the 80CI96KB is accessed
as register 18H of the internal register file. In addition
to providing for convenient manipulation of the stack
pointer, this also facilitates the accessing of operands in
the stack. The top of the stack, for example, can be

accessed by using the stack pointer as the WORD variable in an indirect reference. In a similar fashion, the
stack pointer can be used in the short-indexed mode to
access data wi thin the stack.

Examples

PUSH
LD

[SP]
AX,2!SP]

DUPLICATE TOP_OF_STACK
AX:=NEXT_TO_TOP

ASSEMBLY LANGUAGE ADDRESSING MODES

These features of the assembly language simplify the
programming task and should be used wherever possible.

The MCS-96 assembly language simplifies the choice of
addressing modes to be used in several respects:
Direct Addressing. The assembly language will choose
between register-direct addressing and long-indexed
with the ZERO register depending on where the operand is in memory. The user can simply refer to an operand by its symboliq name: if the operand is in the register file, a register-direct reference will be used, if the
operand is elsewhere in memory, a long-indexed reference will be generated.

3.3 Program Status Word
The program status word (PSW) is a collection of Boolean flags which retain information concerning the state
of the user's program. There are two bytes in the PSW;
the actual status word and the low byte of the interrupt
mask. Figure 3-1 shows the status bits of the PSW. The
P8W can be saved in the system stack with a single
operation (PUSHF) .and restored in a like manner
(POPF). Only the interrupt section of the PSW can be
accessed directly. There is no SFR for the PSW status
bits.

Indexed Addressing. The assembly language will
choose between short and long indexing depending on
the value of the index expression. If the value can be
expressed in eight bits then short indexing will be used,
if it cannot be expressed in eight bits then long indexing
will be used.

4-15

intJ

80C196KB USER'S GUIDE

CONDITION FLAGS

The PSW bits on the 80CI96KB are set as follows:

Figure 3·1. PSW Register
The Z (Zero) flag is set to indicate that the operation generated a result equal to zero. For the addwith-carry (ADDC) and subtract-with-borrow
(SUBC) operations the Z flag is cleared if the result is non-zero but is never set. These two instructions are normally used in conjunction with
the ADD and SUB instructions to perform multiple precision arithmetic. The operation of the Z
flag for these instructions leaves it indicating the
proper result for the entire multiple precision calculation.
The Negative flag is set to indicate that the operation generated a negative result. Note that the N
flag will be in the algebraically correct state even
if an overflow occurs. For shift operations, including the normalize operation and all three forms
(SHL, SHR, SHRA) of byte, word and double
word shifts, the N flag will be set to the same
value as the most significant bit of the result. This
will be true even if the shift count is O.
The oVerflow flag is set to indicate that the operation generated a result which is outside the range
for the destination data type. For the SHL, SHLB
and SHLL instructions, the V flag will be set if the
most significant bit of the operand changes at any
time during the shift. For divide operations, the
following conditions are used to determine if the V flag is set:
For the
V is set if Quotient is:
operation:

VT: The oVerflow Trap (lag is set when the V flag is
set, but it is only cleared by the CLRVT, JVT and
JNVT instructions. The operation of the VT flag
allows for the testing for a possible overflow condition at the end of a sequence of related arithmetic operations. This is normally more efficient
than testing the V flag after each instruction.
C: The Carry flag is set to indicate the state of the
arithmetic carry from the most significant bit of
the ALU for an arithmetic operation, or the state
of the last bit shifted out of an operand for a shift.
Arithmetic Borrow after a subtract operation is
the complement of the C flag (i.e. if the operation
generated a borrow then C=O.)
X: Reserved. Should always be cleared when writing
to the PSW for compatibility with future products.
I:
The global Interrupt disable bit disables all interrupts when cleared except NMI, TRAP, and unimplemented opcode.
ST: The ST (STicky bit) flag is set to indicate that
during a right .shift a 1 has been shifted first into
the C flag and then. been shifted out. The ST flag
is undefined after a multiply operation. The ST
flag can be used along with the C flag to control
rounding after a right shift. Consider multiplying
two eight bit quantities and then scaling the result
down to 12 bits:

UNSIGNED
BYTE DIVIDE> 255 (OFFH)
UNSIGNED
WORD DIVIDE> 65535 (OFFFFH)
SIGNED
BYTE
DIVIDE
SIGNED
WORD
DIVIDE

-l27(8lH)

or
> l27(7FH)

< -32767 (800lH)
or
> 32767 (7FFFH)

MULUB
SHR

AX,CL,DL
AX,#4

;AX:=CL*DL

;Shift right 4

places
If the C flag is set after the shift, it indicates that the
bits shifted off the end of the operand were greater-than
or equal-to one half the least significant bit (LSB) of the
result. If the C flag is clear after the shift, it indicates
that the bits shifted off the end of the operand were less
than half the LSB of the result. Without the ST flag,
the rounding decision must be made on the basis of the
C flag alone. (Normally the result would be rounded up
if the C flag is set.) The ST flag allows a finer resolution
in the rounding decision:
.
C

Value of the Bits Shifted Off

Value = 0

o < Value < % LSB

Value = %LSB

Value> %LSB

Figure 3·2. Rounding Alternatives

Imprecise rounding can be a major source of error in a
numerical calculation; use of the ST flag improves the
options available to the programmer.

4-16

inter

80C196KB USER'S GUIDE

WORDS can be converted to DOUBLE-WORDS by
simply clearing the upper WORD of the DOUBLEWORD (CLR) and INTEGERS can be converted to
LONGS with the EXT (sign extend) instruction.

INTERRUPT FLAGS

The, lower eight bits of the PSW individually mask the
lowest 8 sources of interrupt to the 80C196KB. These
mask bits can be accessed as an eight bit byte (INT_
MASK-address 8) in the on-board register file. A separate register (INT_MASKI-address 13Hj contains
the control bits for the higher 8 interrupts. A logical 'I'
in these bit positions enables the servicing of the corresponding interrupt. Bit 9 in the PSW is the global interrupt disable. If this bit is cleared then interrupts will be
locked out. Note that the interrupts are collected in the
INT_PEND -registers even if they are locked out. Execution of the corresponding service routines will proceed according to their priority when they become enabled. Further information on the interrupt structure of
the 80C196KB can be found in Section 5.

The MCS-96 instructions for addition, subtraction, and
comparison do not distinguish between unsigned words
and signed integers. Conditional jumps are provided to
allow the user to treat the results of these operations as
either signed or unsigned quantities. As-an example, the
CMPB (compare byte) instruction is used to compare
both signed and unsigned eight bit quantities. A JH
(jump if higher) could be used following th~ compare if
unsigned operands were involved or a JGT (jump if
greater-than) if signed operands were involved.
Tables 3-1 and 3-2 summarize the operation of each of
the instructions. Complete descriptions of each instruction and its timings can be found in the MCS-96 family
Instruction Set chapter.

3.4 Instruction Set
The MCS-96 instruction set contains a full set of arithmetic and logical operations for the 8-bit data types
BYTE and SHORT INTEGER and for the 16-bit data
types WORD and INTEGER. The DOUBLE-WORD
and LONG data types (32 bits) are supported for the
products of 16-by-16 multiplies and the dividends of
32-by~ 16 divides, for shift operations, and for 32-bit
compares. The remaining operations on 32-bit variables
can be implemented by combinations of 16-bit operations .. As an example the sequence:

ADD
ADDC

AX,CX
BX,DX

performs a 32-bit addition, and the sequence

SUB
SUBC

The execution times for the instruction set are given in
Figure 3-3. These times are given for a 16-bit bus with
no wait states. On-chip EPROM/ROM space is a 16bit, zero wait state bus. When executing from an 8-bit
external memory system or adding wait states, the CPU
becomes bus limited and must solt)etimes wait for the
prefetch queue. The performance penalty for an 8-bit
external bus is difficult to measure, but has shown to be
between 10 and 30 percent based on the instruction
mix. The best way to measure code performance is to
actually benchmark the code and time it using an emulator or with TIMER!.

AX,CX
BX,DX

performs a 32-bit subtraction. Operations on REAL
(i.e. floating point) variables are not supported directly
by the hardware but are supported by the floating point
library for the 80Cl96KB (FPAL-96) which implements a single precision subset of draft 10 of the IEEE
standard for floating point arithmetic. The performance
of this software is significantly improved by the
80CI96KB NORML instruction which normalizes a
32-bit variable and by the existence of the ST flag in the
PSW.

The indirect and indexed instruction timings are given
for two memory spaces: SFR/Internal RAM space (0OFFH), and a memory controller reference (IOOHOFFFFH). Any instruction that uses an operand that is
referenced through the memory controller (ex. Add
rl,5000H(01) takes 2-3 states longer than if the operand was in the SFRIInternal RAM space. Any data
access to on-chip ROM/EPROM is considered to be a
memory _controller reference.
Flag Settings. The modification to the flag setting is
shown for each instruction. A checkmark (,....) means
that the flag is set or cleared as appropriate. A hyphen
means that the flag is not modified. A one or zero (I) or
(0) indicates'that the flag will be in that state after the
instruction. An up arrow (t) indicates that the instruction may set the flag if it is appropriate but will
not clear the flag. A down arrow ( ,J, ) indicates that the
flag can be cleared but not set by the instruction. A
question mark (?) indicates that the flag will be left in
an indeterminant state after the operation.

In addition to the operations on the various data types,
the 80CI96KB supports conversions between these
types. LDBZE (load byte zero extended) converts a
BYTE to a WORD and LDBSE (load byte sign extended) converts a SHORT-INTEGER into an INTEGER.

4-17

80C196KB USER'S GUIDE

Table 3-1A.lnstruction Summary
Mnemonic

Flags

Operation (Note 1)

Operands

ADD lAD DB

D -

ADD/ADDB

AODC/AOOCB

D B+A
O-O+A+C

D+A

Notes
VT ST

i
i
i
i
i
i
i

SUB/SUBB

0 - O-A

-",

SUB/SUBB

0 - B-A

SUBC/SUBCB

0-0-'-A+C-1

",-

(0,0 + 2) I A,O + 2 - , remainder

remainder

(0,0 + 2) I A,O + 2 -

remainder

i
i
i
i

(0,0 + 1) IA,O + 1 -

O-A

MUL/MULU

0,0 + 2 -

MUL/MULU

0,0 + 2 -

MULB/MULUB

0,0 + 1 -

MULB/MULUB

0,0 + 1 -

OIVU

CMP/CMPB

xA
BxA
0 xA
BxA

OIV

DIVB

oooo-

ANO/ANOB

D -

OANOA

ANO/ANOB

o +-

BANDA

OR/ORB

0 - DORA

XOR/XORB

OIVUB

(O,D + 1) IA,O + 1 -

D (ecx!. or) A

LD/LOB

O-A

ST/STB

A-O

3,4

LOBSE

0-A;0+1 -

LOBZE

0-A;0+1 - 0

PUSH

SP -

POP

A -

PUSHF

SP SP - 2; (SP) PSW;
PSW OOOOH; I 0

0, 0

POPF

PSW -

SJMP

PC +- PC + 11-bit offset

LJMP

BR [indirect]

PC -

SCALL

LCALL

SIGN(A)

(A)

SP SP - 2;
(SP) PC; PC -

PC -

SP PC -

SP ....: 2; (SP) -

(SP); SP + 2

(SP); SP -

SP + 2; I+-",

16·bit offset

",
'

PC + 11-bit offset

SP - 2; (SP) PC;
PC + 16-bit offset

4-18

intJ

80C196KB USER'S GUIDE

Table 3-16. Instruction Summary
Mnemonic

Operands

Flags

Operation (Note 1)

RET

PC -

(SP); SP -

J (conditional)

PC -

Jump ifC

a-bit offset (if taken)

Notes

Z N C V VT ST
- - - -

JNC

jump ifC

JNE

=1
Jump if Z = 0

JGE

Jump if N = 0

jump if Z

JLT

Jump if N

JGT

Jump if N = 0 and Z = 0

Jump if N = 1 or Z = 1

JLE

Jump if C = 1 and Z = 0

JNH

Jump if C = 0 or Z = 1

Jump if V = 1

JNV

Jump if V = 0

JVT

Jump if VT = 1; Clear VT

JNVT

Jump if VT = 0; Clear VT

JST

Jump if ST = 1

JNST

Jump ifST = 0

JBS

Jump if Specified Bit = 1

5,6

JBC

Jump if Specified Bit = 0

5,6

DJNZI
DJNZW

P -

DEC/DECB

D -

D-1

NEGINEGB

D -

O-D

INC/INCB

D -

EXT

D -

D; D

If D

D -1;

* 0 then PC +

+ a-bit offset

EXTB

D -

+
D; D +

NOTINOTB

D -

Logical Not (D)

CLR/CLRB

D-O

SHL/SHLB/SHLL

C -

msb - - - - - Isb -

SHRISHRB/SHRL

msb - - - - - Isb -

SHRA/SHRAB/SHRAL

msb -

2 1 -

Sign (D)
Sign (D)

msb - - - - - Isb -

,..
,..
,..
,..
,..
,..

,.. ,.. ,..
,.. ,.. ,..
,.. ,.. ,..
,.. 0 0
,.. 0 0
,.. 0 0

SETC

C-1

CLRC

C-O

4-19

,.. ,.. ,.. ,..
,.. ,.. ,.. 0
,.. ,.. ,.. 0
-

5
10

i
i
i

,..
,..

7
7
7

80C196KB USER'S GUIDE

Table 3-1C.lnstruc;:tion Summary
Mnemonic

Operands

"Flags

Operation (Note 1),

,Notes
VT

Z
-

2080H

CLRVT

RST

PC -

Disable All Interupts (I -

VT -

Nap

Enable All Interupts (I PC-PC+1

SKIP

PC-PC+2

NORML

TRAP

D-A

[PTR_HI] + [PTR_LOW] + ;
UNTIL COUNT = 0

shift count

(2010H)

paPA

IMASK1/WSR (SP); SP PSW (SP); SP SP+2

IDLPD

IDLE MODE IF KEY = 1;
POWER DOWN MODE IF KEY
CHIP RESET OTHERWISE

1; D -

SP SP-2; (SP) PSW;
OOOOH; SP SP-2;
PSW (SP) IMASK1/WSR; IMASK1 -

BMOV

Left shift till msb

SP- SP - 2;
, (SP) PC; PC -

PUSHA

CMPL

OOH

SP+2

= 2;

NOTES: '
1. If the mnemonic ends in "B" a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment rules for the required operand type. D and B are locations in the Register File; A can be
located arlywhere in memory.
2. D,D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D,D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to word.
5. Offset is a 2's complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates double-word operation.
.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.
10. The DJNZW instruction is not guaranteed to work. See Functional Deviations section.

4-20

intJ

80C196KB USER'S GUIDE

Table 3-2A. Instruction Length (in Bytes)/Opcode
MNEMONIC

DIRECT

IMMED

INDIRECT

INDEXED

NORMAL*(1)

A-INC'(1)

SHQRT*(1)

LONG*(1)

4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/AB
4/56
4/5A
3176
317A
3/B6
3/BA
3/9A

4/46
4/4A
3/66
3/6A
3/A6
3/AA
3/AB
4/56
4/5A
3176
3/7A
3/B6
3/BA
3/f)A

5/47
5/4B
4/67
4/6B
4/A7
4/AB
4/8B
5/57
5/5B
4/77

6/47
6/4B
5/67
5/6B
5/A7
5/AB
5/8B
6/57
6/5B
5/77

ADD (3-ap)
SUB (3-ap)
ADD (2-ap)
SUB (2-ap)
ADDC
SUBC
CMP
ADDB (3-ap)
SUBB (3-ap)
ADDB (2-ap)
SUBB (2-ap) .
ADDCB
SUBCB
CMPB

4/44
4/48
3/64
3/68
3/A4
3/A8
3/88
4/54
4/58
3174
3178
3/B4
3/B8
3/98

5/45
5/49
4/65
4/69
4/A5
4/A9
4/89

MUL (3-ap)
MULU (3-ap)
MUL (2-ap)
MULU (2-ap)
DIV
DIVU
MULB (3-ap)
MULUB (3-ap)
MULB (2-ap)
MULUB (2-ap)
DIVB
DIVUB

5/(2)
4/4C
4/(2)

6/(2)
5/4D
5/(2)

5/(2)

6/(2)

7/(2)

4/4E
4/(2)

5/4F
5/(2)

6/4F
6/(2)

3/6C
4/(2)

4/6D
5/(2)

3/6E
4/(2)

4/6F
5/(2)

5/6F
6/(2)

3/8C
5/(2)

4/8D
5/(2)

3/8E
5/(2)

4/8F
6/(2)

5/8F
7/(2)

4/5C
4/(2)

4/5D
4/(2)

4/5E
4/(2)

5/5F
5/(2)

6/5F
6/(2)

3/7C
4/(2)

317D
4/(2)

317E

3/7E
4/(2)

4/7F
5/,(2)

517F

4/(2)

3/9C

3/9D

3/9E

4/9F '

4/40
3/60
3/80

5/41
4/61

4/42
3/62

5/43
4/63

4/81

3/84

3/90
3/94

4/85
4/51
3/71
3/91
3/95

3/82
3/86
4/52

4/42
3/62
3/82
3/86
4/52
3172
3/92

2/C8

3/C9

2/CC

AND (3-ap)
AND (2-ap)
OR (2-ap)
XOR
. ANDB (3-ap)
ANDB (2-ap)
ORB (2-ap)
XORB
PUSH
POP

4/50

3/70

4/55
4/59
3175
3179
3/B5
3/B9
3/99

3172

3/92
3/96
2/CA
2/CE

(

417B

517B

4/B7

5/B7

4/BB

5/BB

4/9B

5/9B

4/83
4/87
5/53
4173
4/93

6/(2)
5/9F'
6/43

5/63
5/83
5/87

5/53
4173
5/93

3/96

4/97

5/97

2/CA
2/CE

3/CB
3/CF

4/CB
4/CF

NOTES:
1. Indirect and indirect + share the same opcodes, as do short and long indexed opcodes. If the second byte is even, use
indirect or short indexed. If odd, use indirect or long indexed.
2. The opcodes for signed multiply and divide are the unsigned opcode with an "FE" prefix.

4-21

inter

80C196KB USER'S GUIDE

Table 3-28. Instruction Length (in Bytes)/Opcode
MNEMONIC

LO
LOB
ST
STB
LOBSE
LBSZE

DIRECT

INDIRECT

IMMED

INDEXEr;>

NORMAL

A-INC

SHORT

LONG

3/AO

4/A1

3/A2

4/A3

5/A3

3/BO

3/B1

3/B2

4/B3

5/B3

3/CO

3/C2

4/C3

5/C3

3/C4

3/C6

4/C7

5/C7

3/BE

·3/BE

4/BF

5/BF

3/AE

4/AF

5/AF

3/BC
3/AC

3/BO
3/AO

Mnemonic

Length/Opcode

Mnemonic

Length/Opcode

PUSHF
POPF
PUSHA
POPA

1/F2
1/F3
1/F4
1/F5

3/EO
3/E1(4)
3/0F
3/0C

TRAP
LCALL
SCALL
RET
LJMP
SJMP
BR[)

1/F7

OJNZ
OJNZW
NORML '
SHRL
SHLL
SHRAL
SHR
SHRB
SHL
SHLB
SHRA
SHRAB

JNST
JST
JNH
JH
JGT
JLE
JNC
JC
JNVT
JVT
JNV
JV
JGE
JLT
JNE
JE
JBC
JBS

3/EF
2/2S-2F(3)
1/FO
3/E7
2/20-27(3)
2/E3

1/00
1/0S
1/01
1/09
1/02
1/0A

CLRC
SETC
01
EI
CLRVT
NOP
RST
SKIP
10LPO
BMOV

1/B3

1/0S
1/04
1/0C
1/05
1/00
1/06
1/0E
1/07
1/0F

3/00
3/0E
3/0S
3/1S
3/09
3/19
3/0A
3/1A

1/FS
1/F9
1/FA

1/FB
1/FC

1/FO
1/FF
2/00
1/F6
3/c'1

3/30-37

3/3S-3F

NOTES:
3, The 3 least significant bits of the opcode are concatenated with the 8 bits to form an 11·bit, 2's complement offset.
4, The DJNZW instruction is not guaranteed to work. See Functional Deviations section.

4·22

80C196KB USER'S GUIDE

Table 3.3A. Instruction Execution State Times (1)
MNEMONIC

DIRECT

ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
ADDC
SUBC
CMP
ADDB (3·op)
SUBB (3-op)
ADDB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB

NORMAL'

A-INC'

SHORT'

LONG'

7/10
7/10
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8

8/11
8/11
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9

7/10
7/10
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8

8/11
8/11
7/9
7/9.
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9

18/21
16/19
18/21
16/19
28/31
26/29
14/17
12/15
14/17
12/15
20/23
18/21

19/22
17/19
19/22
17/19
29/32
27/30
13/15
12/16
15/18
13/15
21/24
19/22

19/22
17/20
19/22
17/20
29/32
27/30
15/18
12/16
15/18
12/16
21/24
19/22

20/23
18/21
20/23
18/21
30/33
28/31
16/19
14/17
16/19
14/17
22/25
20/23

4
4
4
4
5
5
4
4
4
4
4

6
6
5
5
5
5
5
5
5
4
4
4
4
4

MUL (3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3·op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB

16
14
16
14
26
24
12
10
12
10
18
16

17
1.5
17
15
27
25
12
10
12
10
18
16

AND (3-op)
AND (2-op)
OR (2·op)
XOR
AN DB (3-op)
AN DB (2-op)
ORB (2-op)
XORB

5
4
4
4
5
4
4
4

6
5
5
5
5
4
4
4

7/10
6/8
6/8
6/8
7/10
6/8
6/8
6/8

8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9

7/10
6/8
6/8
6/8
7/10
6/8
6/8
6/8

8/11
7/9
7/9
7/9
8/1t
7/9
7/9

4,4
4,4
4
4

5,4
4
4

5/8
5/8
5/8
5/8

6/8
6/9
6/8
6/8

6/9
6/9
6/9
6/9

7/10
7/10
7/10
7/10

10/13
11/13
12/15
14/16

11/14
12/14
13/16
15/17

LD, LOB
ST,STB
LDBSE
LDBZE

5
5

INDEXED

INDIRECT

IMMED

BMOV

PUSH (int stack)
POP (int stack)
PUSH (ext stack)
POP (ext stack)

719

internal/internal: 6 + 8 per word
external/internal: 6 + 11 per word
external/external: 6+ 14 per word
6
8
8
11

7
9
-

9/12
10/12
11/14
13/15

10/13
11/13
12/15
14/16

"Times for operands as: SFRs and Internal RAM (0-1 FFH)/memory controller (200H-OFFFFH)

NOTE:
1. Execution times for memory controller references may be one to two states higher depending on the number of bytes in
the prefetch queue. Internal stack is 200H-1FFH and external stack is 200H-OFFFFH.

4-23

80C196KB.USER'S GUIDE

Table 3.3B. Instruction Execution State Times
MNEMONIC
PUSHF (int stack)
POPF (int stack)
PUSHA (int stack)
POPA (int stack)
TRAP (int stack)
LCALL (int stack)
SCALL (int stack)
RET (int stack)

MNEMONIC

6
12
12

PUSHF (ext stack)
POPF (ext stack)
PUSHA (ext stack)
POPA (ext stack)

8·
10
18
18

16
11
11
11

TRAP (ext stack)
LCALL (ext stack)
SCALL (ext stack)
RET (ext stack)

18
13
13
14

OEC/OECB
EXT/EXTB
INC/INCB

3
4
3

CMPL
CLR/CLRB
NOT/NOTB
NEG/NEGB

3
3
3

LJMP
SJMP
BR [indirect]
JNST,JST
JNH,JH
JGT,JLE
JNC, JC
JNVT, JVT
JNV, JV
JGE, JLT
JNE, JE
JBC,JBS

4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
5/9 jump not taken/jump taken

OJNZ
OJNZW (Note 1)

5/9 jump not tak~n/jump taken
5/9 jump not taken/jump taken

. NORML
SHRL
SHLL
SHRAL
SHR/SHRB
SHL/SHLB
SHR,A./SHRAB
CLRC
SETC
01
EI
CLRVT
NOP
RST
SKIP
10LPO

7
7
7

+ 1 per shift (9 for 0 shift)
7 + 1 per shift (8 for 0 shift)
7 + 1 per shift (8 for 0 shift)
7 + 1 per shift (8 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)

2
2
2
2
2
2
15 (includes fetch of configuration byte)
3
8/25 (proper key/improper key)

NOTE:
1. The DJNZW instruction is not guaranteed to work. See Functional Deviations section.

4-24

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80C196KB USER'S GUIDE

3.5 80C196KB Instruction Set
Addl~ions and Differences
For users already familiar with the 8096BH, there are
six instructions added to the standard MCS-96 instruction set to form the 80C 196KB instruction set. All of
the former instructions perform the same function, except as indicated in the next section. The new instructions and their descriptions are listed below:
PUSHA - PUSHes the PSW,
INT_MASK,
IMASK1, and WSR
POPA - POPs the PSW, INT_MASK, IMASK1,
and WSR
IDLPD - Sets the part into IDLE or Powerdown
mode
CMPL , - Compare 2 long direct values
BMOV - Block move using 2 auto-incrementing
pointers and a counter
DJNZW - Decrement Jump Not Zero using a Word
counter (Not functional on current stepping.)·

language and PLM-96 environment and it offers compatibility between these environments. Another advantage is that it allows the user access to the same floating
point arithmetics library that PLM-96 uses to operate
on REAL variables.
REGISTER UTILIZATION

The MCS-96 architecture provides a 256 byte register
file. Some of these registers are used to control registermapped I/O devices and for other special functions
such as the ZERO register and the stack pointer. The
remaining bytes in the register file, some 230 of them,
are available for allocation by the programmer. If these
registers are to be used effectively, some overall strategy
for their aUocation must be adopted. PLM-96 adopts
the simple and effective strategy of allocating the eight
bytes between addresses lCH and 23H as temporary
storage. The starting address of this region is caUed
PLMREG. The remaining area in the register file is
treated as a segment of memory which is allocated as
required.
ADDRESSING 32-BIT OPERANDS

INSTRUCTION DIFFERENCES

These operands are formed from two adjacent 16-bit
words in memory. The least significant word of the
double word is always in lower address, even when the
data is in the stack (which means that the most significant word must be pushed into the stack first). A dou;
ble word is addressed by the address onts least significant byte. Note that the hardware supports some operations on double words. For these operations the double
word must be in the internal register file and must have
an address which is evenly divisible by four.
.

Instruction times on the 80C 196KB are shorter than
those on the 8096 for many instructions. For example a
16X 16 unsigned multiply has been reduced from 25 to
'14 states. In addition, many zero and one operand instructions and most instructions using external data
take one or two fewer state times.
Indexed and indirect operations relative.to the stack
pointer (SP) work differently on the 80Cl96KBthan
on the 8096BH. On the 8096BH, the address is calculated based on the un-updated version of the stack
pointer. The 80CI96KB use~ the updated version. The
offset for POP[SP] and POP nn[SP] instructions may
need to be changed by a count of 2.

SUBROUTINE LINKAGE

Parameters are passed to subroutines in the stack. Parameters are pushed into the stack in the order that
they are encountered in the scanning of the source text.
Eight-bit parameters (BYTES 01: SHORT-INTEGERS) are pushed into the stack with the high order
byte undefined. Thirty-two bit parameters (LONG-INTEGERS, DOUBLE-WORDS, and REALS) are
pushed onto the stack as two 16-bit values; the most
significant half of the parameter is pushed into the
stack first.

3.6 Software Standards and
Conventions
For a software project of any size it is a good idea to
modularize the program and to establish' standards
which control the communication between these modules. The nature of these standards will vary with the
needs of the final application. A common component of
aU of these standards, however, must be the mechanism
for passing parameters to procedures and returning results from procedures. In the absence of some overriding consideration which prevents their use, it is suggested that the user conform to the conventions adopted by
the PLM-96 programming language for procedure linkage. It is a very usable standard for both the assembly

As an .example, consider the following, PLM-96 procedure:
example_procedure: PROCEDURE
(param I ,param2,param3);
DECLARE paraml BYTE,
param2 DWORD,
param3 WORD;

4-25

inter

80C196KB USER'S GUIDE

When this procedure is entered at run time the stack
will contain the parameters. in. the following order:
?????? : param1
high word of param2
low word of param2
param3
return address

+- Staci<.::...pointer

Figure 3-5. Stack Image

If a procedure returns a value to the calling code (as
opposed to modifying more global variables) then the
result is returned in the variable PLMREG. PLMREG
is viewed as either an 8-, 16- or 32-bit variable depending on the type of the procedure.
The standard calling convention adopted by PLM-96
has several key features:
a) Procedures can always assume that the eight bytes of
register file memory starting at PLMREG can be
used as temporaries within the body of the procedure.
b) Code which calls a procedure must assume that the
eight bytes of register file memory starting at
PLMREG are modified by the procedure.
.c) The Program Status Word (PSW-see Section 3.3) is
not saved and restored by procedures so the calling
code must assume that the condition flags (Z, N, V,
VT, C, and ST) are modified by the procedure.
d) Function results from procedures are always re:
turned in the variable PLMREG.
PLM-96 allows the definition of INTERRUPT procedures which are executed when a predefined interrupt
occurs. These procedures do not conform to the rules of
a normal procedure. Parameters cannot be passed to
these procedures and they cannot return results. Since
they can execute essentially at any time (hence the term
interrupt), these procedures must save the PSW and
PLMREG when they are entered and restore these values before they exit.

It is recommended that unused areas. of code be filled
with NOPs and periodiC jumpst!J an error routine or
RST (reset chip) instructions. This is particularly important in the code around lookup tables, since if lookup tables are executed uncj.esired results will occur.
Wherever space allows, el;lch table should be surrounded by 7 NOPs (the longest 80Cl96KB instruction has 7
bytes) and a RST or jump to error routine instruction.
Since RST is a one-byte instruction, the NOPs are not
needed if RSTs are used instead of jumps to an error
routine. This will help to ensure a speedy recovery
should the processor have a glitch in the program flow.

The Watchdog Timer (WDT) further protects against
software and hardware errors. W:hen using the WDT to
protect software it is desirable to reset it from only one
place in code, lessening the chance of an undesired
WDT reset. The section of code that resets the WDT
should monitor the other code sections for proper operation. This can be done by checking variables to make
sure they are within reasonable values. Simpl'y using a
software timer to reset the WDT every 10 milliseconds
, will provide protection only for catastrophic failures.

4.0 PERIPHERAL OVERVIEW
There are five major peripherals on the 80C196KB: the
pulse-width-modulated output· (PWM), Timer! and
Timer2, High Speed I/O Unit, Serial Port and A/D
Converter. With the exception of the high speed I/O
unit (HSIO), each of the peripherals is a single unit that
can be discussed without further separation.
Four individual sections make up the HSIOand work
together to form a very flexible' timer/counter based
I/O system. Included in the HSIO are a 16-bit timer
(Timer!), a 16-bit up/down counter (Timer2), a programmable high speed input unit (HSI), and a programmable high speed output unit (HSO). With very
little CPU overhead the HSIO can measure pulse
widths, generate waveforms, and create periodic interrupts. Depending on the application, it can perform the
work of up to 18· timer/counters and capture/compare
registers.
A brief'description of the peripheral functions and interractions is included in this section. It provides overview information prior to the detailed discussions in the
following sections. All of the details on control bits and
precautions are in the individual sections for each peripheral starting with Section 5.

3.7 Software Protection Hints
Several features to assist in recovery from hardware
and software errors are available on the 80C196KB.
Protection is also provided against executing unimplemented opcodes by the unimplemented opcode interrupt. In addition, the hardware reset instruction (RST)
can cause a reset if the program counter goes out of
bounds. This instruction· has an opcode of OFFH, so if
the processor reads in bus lines which have been pulled
high it will reset itself.

4-26

inter

80C196KB USER'S GUIDE

HSI_TIME register. When the time register is read
the next FIFO location is loaded into the holding register.

4.1 Pulse Width Modulation Output
(D/A)
,
Digital to analog conversion can be done with the Pulse
Width Modulation output. The output waveform is a
variable duty cycle pulse which repeats every 256 state
times or 512 state times if the prescaler is enabled.
Changes in the duty cycle are made by writing to the
PWM register. There are several types of motors which
require a PWM waveform for most efficient operation.
Additionally, if this waveform is integrated it will produce a DC level which can' be changed in 256 steps by
varying the duty cycle. Details on the PWM are in Section 6.

Three forms of HSI interrupts can be generated: when a
value moves from the FIFO into the holding register;
when the FIFO (independent of the holding register)
has 4 or more events stored; and when the FIFO has 6
or more events stored. This flexibility allows optimization of the HSI for the' expected frequency of interrupts.
Independent of the HSI operation, the state of the HSI
pins is indicated by 4 bits of the HSI_STATUS register. Also independent of the HSI operation is the HSI.O
pin interrupt, which can be used as an extra external
interrupt even if the pin is not enabled to the HSI unit.

4.2 Timers
4.4 High Speed Outputs (HSO)

Two 16-bit timers are available for use on the
80C 196KB. The first is designated "Timer!", the second "Timer2". Timer! is used to synchronize events to
real time, while Timer2 is clocked externally and synchronizes events to external occurrences. The timers
are the time bases for the High Speed Input (HSI) and
High Speed Output (HSO) units and can be considered
an integral part of the HSI/O. Details on the timers are
in Section 7.

The High Speed Output (HSO) unit can generate events
at specified times or counts based on Timer! or Timer2
with minimal CPU overhead. A block diagram of the
HSO unit is shown in Figure 4-4. Up to 8 pending
events can be stored in the CAM (Content Addressable
Memory) of the HSO unit at one time. Commands are
placed into the HSO unit by first writing to HSO_
COMMAND with the event to occur, and then to
HSO_TIME with the timer match value.

Timer! is a free-running timer 'which is incremented
every eight state times, just as it is on the 8096BH.
Timer! can cause an interrupt when it overflows.

Fourteen different types of events can be triggered by
the HSO: 8 external and 6 internal. There are two interrupt vectors associated with the HSO, one for external
events, and one for internal events. External events con:
sist of switching one or more of the 6 HSO pins
(HSO.O-HSO.5). Internal events include setting up 4
Software Timers, resetting Timer2, and starting an A/
D conversion. The software timers are flags that can be
set by the HSO and optionally cause interrupts. Details
on the HSO Unit are in Section 9.

Timer2 counts transitions, both positive and negative,
on its input which can be either the T2CLK pin or the
HSI.I pin. Timer2 can be read and written and can be
reset by hardware, software or the HSO unit. It can be
used as an up/down counter based on Port 2.6 and it's
value can be captured into the T2CAPture register. Interrupts can be generated on capture events and if
Timer2 crosses the OFFFFH/OOOOH boundary or the
7FFFH/8000H boundary in either direction.

4.5 Serial Port
4.3 High Speed Inputs (HSI)

The serial port on the 80CI96KB is functionally co~
patible with the serial port on the MCS-51 and MCS-96
families of microcontrollers. One synchronous and
three asynchronous modes are available. The asynchronous modes are full duplex, meaning they can transmit
and receive at the same time. Double buffering is provided for the receiver so that a second byte can be received before the first byte has been read. The transmitter is also double buffered, allowing bytes to be written
while transmission is still in progress.

The High Speed Input (HSI) unit can capture the value
of Timer! when an event takes place on one of four
input pins (HSI.O-HSI.3). Four types of events can trigger a capture: rising edges only, falling edges only, rising or falling edges, or every eighth rising edge. A block
diagram of this unit is shown in Figure 4-3. Details on
, the HSI unit are in Section 8.
When events occur, the Timer! value gets stored in the
FIFO along with 4 status bits which indicate the input
line(s) that caused the event. The next event ready to be
unloaded from the FIFO is placed in the HSI Holding
Register, so a total of 8 pieces of data can be stored in
the FIFO. Data is taken off the FIFO by reading the
HSI_ST ATUS register, followed by reading the

The Serial Port STATus (SP_STAT) register contains
bits to indicate receive overrun, parity, and framing errors, and transmit and receive interrupts. Details on the
Serial Port are in Section 10.

4-27

inter

80C196KB USER'S GUIDE

HSI Trigger Options
FIFO
INTERRUPT
CONTROL
Be LOGIC

~ HITO~O

-r-

11 6l

LOTOHI

TI ER

7x20 BIT
FIFO

-IH'iOR."LOl-

J1I1J1.I1.IUUUU
EVERY EIGHTH POSITIVE
TRANSITION

270651 ~18
270651-19

Figure 4·3. HSI Block Diagram

16-BIT

16-BIT
• T2RST
(P2.4)

XTAL1/16
CONTROL
LOGIC

~----~--24--------~

8
-..------16 - - - . I
16

HIGH SPEED OUTPUT CONTROLS
6 PINS
4 SOFTWARE TIMERS
2 INTERRUPTS
INITIATE AID CONVERSION
RESET TIMER2

BUS

270651-8

Figure 4·4. HSO Block Diagram

4·28

inter

80C196KB USER'S GUIDE

MODES OF OPERATION

Mode 0 is a synchronous mode which is commonly
used for shift register based 1/0 expansion. Sets of 8
bits are shifted in or out of the 80C 196KB with a data
signal and a cIock signal.
Mode I is the standard asynchronous communications
mode: the data frame used in this mode consists of 10
bits: a start bit (0).8 data bits (LSB first), and a stop bit
(1). Parity can be enabled to send an even parity bit
instead of the 8th data bit and to check parity on'reception.
Modes 2 and 3 are 9-bit modes commonly used for
multi-processor communications. The data frame used
in these modes consist of a start bit (0). 9 data bits (LSB
first), and a stop bit (1). When transmitting, the 9th
data bit can be set to a one to indicate an address or
other global transmission. Devices in Mode 2 will be
interrupted only if this bit is set. Devices in Mode 3 will
be interrupted upon any reception. This provides an
easy way to have selective reception on a data link.
Mode 3 can also be used to send and receive 8 bits of
data plus even parity.

input at a time using successive approximation with a
result equal to the ratio of the input voltage divided by
the analog supply voltage. If the ratio is 1.00, then the
result will be all ones. A conversion can be started by
writing to the AID_Command register or by an HSO
Command. Details on the AID converter are in Section
II.

4.7 I/O Ports
There are five 8-bit 1/0 ports on the 80CI96KB. Some
of these ports are input only, some are output only,
some are bidirectional and some have multiple functions. In addition to these ports, the HSI/O pins can be
used as standard 1/0 pins if their timer related features
are not needed.
Port 0 is an input port which is also the analog input
for the AID converter. Port 1 is a quasi-bidirectional
port and the 3MSBs of Port I are multiplexed with the
HOLD/HLDA functions. Port 2 contains three types
of port lines: quasi-bidirectional, input and output. Its
input and o,utput· lines are shared with other functions
such as serial- port receive and transmit and Timer2
clock and reset. Ports 3 and 4 are open-drain bidirectional ports which share their pins with the addressl
data bus.

BAUD RATES

Baud rates are generated in" an independent 15-bit
counter based on either the T2CLK pin or XTAL 1 pin.
Common baud rates can be easily generated with standard crystal frequencies. A maximum baud rate of 750
Kbaud is available in the asynchronous modes with
12MHz on XTALI. The synchronous mode has a maximum rate of 3.0 Mbaud with a 12 MHz clock.

Quasi-bidirectional pins can be used as input and output pins without the need for a data direction register.
They output a strong low value and a weak high value.
The weak high value can be externally pulled low providing an input function. A detailed explanation of
these ports' can be found in Section 12.

4.8 Watchdog Timer

4.6 A/D Converter

The Watchdog Timer (WDT) provides a means to recover gracefully from a software upset. When the
watchdog is enabled it will initiate a hardware reset
unless the software clears it every 64K state times.
Hardware resets on the 80CI96KB cause the RESET
input pin to be pulled low, pro~iding a reset signal to
other components on the board. The WDT is independent of the other timers on the 80C196KB.

The 80CI96KB's Analog interface consists of a sampleand-hold, an 8-channel multiplexer, and a 10-bit successive approximation analog-to-digital converter.
Analog signals can be sampled by any of the 8 analog
input pins (ACHO through ACH7) which are shared
with Port O. An AID conversion is performed on one

4-29

inter

80C196KBUSER'S GUI~E

5.0 INTERRUPTS

Special Interrupts

Twenty-eight (28) sources 'of interrupts are available on
the 80C196KB. These sources are gathered into 15 vectors plus special vectors for NMI, the TRAP instruction, and Unimplemented Opcodes. Figure 5-1 shows
the routing of the interrupt sources into their vectors as
well as the control bits which enable some of the
sources.

Three special interrupts are available on the
80C196KB: NMI, TRAP and Unimplemented opcode.
The external NMI pin generates an unmaskable interrupt for implementation of critical interrupt routines.
The TRAP instruction is useful in the development of
custom software debuggers or generation of software
interrupts. The unimplemented opcode interrupt generates an interrupt when unimplemented opcodes are exe-

SOURCES

VECTORS

NON - MASKABLE INTERRUPT - - - - - - - - - NMI
TIMER 2 CAPTURE

TIMER 2 CAPTURE

4TH FIFO ENTRY - - - - - - - - - HSI FIFO 4
UNIMPLEMENTED OPCODE - - - - - - - - - UNIMPLEMENTED OPCODE
TRAP INSTRUCTION
EXTINT (P2.2)
PORT 0.7

SOFTWARE TRAP

---_e~IOC1.1
-

EXTINT1
EXTINT

TJ FLAG
.........
TI FLAG (NEW)
/'~------ SERIAL PORT
RI FLAG - - - . . : ; ; . ; . . . - - - - RI FLAG (NEW)

------r--- SOFTWARE TIMER

SWTO - 3
RESET TIMER 2 - - - - - - 1
START AID -----~

HSI.O PIN - - - - - - - - - HSI.O PIN
HSO PINS 0 - 5 - - - - - - - - - HIGH SPEED OUTPUT
HSI FIFO IS FULL - - - - . . . , . . - - - - HSI FIFO FULL (NEW)
HSI HOLDING REGISTER LOADED

---_e~IOC1.7
-

AID CONVERSION COMPLETE

HSI DATA AVAILABLE

AID CONVERSION COMPLETE

TIMER 2 OVERFLOW - - - . . . . , . - -____L.:w-fIOC1.3
TIMER 1 OVERFLOW
IOC1.2

---=r-r--. . . ._--

TIMER 2 OVERFLOW (NEW)
TIMER OVERFLOW

Figure 5-1. 80C196KB Interrupt Sources

4-30

270651-9

inter

80C196KB USER'S GUIDE

cuted. This provides software recovery from random
execution during hardware and software failures. Although available for customer use, these interrupts may
be used in Intel development tools or evaluation boards.
NMI

NMI, the external Non-Maskable Interrupt, is the
highest priority interrupt. It vectors indirectly through
location 203EH. For design symmetry, a mask bit exists in INT_MASKI for the NM[ To prevent accidental masking of an NMI, the bit does not function
arid will not stop an NMI from occurring. For future
compatibility, the NMI mask bit must be set to zero.

The programmer must initialize the interrupt vector table with the starting addresses of the appropriate interrupt service routines. It is suggested that any unused
interrupts be vectored to an error handling routine. In a
debug environment, it may be desirable to have the routine lock into a jump to self loop which would be easily
traceable with emulation tools. More sophisticated routines may be appropriate for production code recoveries.
"

INTERRUPT SOURCES

NMI on the 8096 vectored directly to location {)()()()H,
so for the 80Cl96KB to be compatible with 8096 software, which uses the NMI, location 203EH must be
loaded with OOOOH. The NMI interrupt vector and interrupt vector location is used by some Intel development tools. For example, the EV8OCl96KB evaluation
board uses the NMI to process serial communication
interrupts' from' the host. The NMI interrupt routine
executes monitor commands passed from the host.

80C196KB
28 Sources

The NMI interrupt is sampled during PHI or
CLKOUT low and is latched internally. If the pin is
held high, multiple interrupts will not occur.

TRAP

18 Vectors

VECTOR STATUS

Opcode OF7H, the TRAP instruction, causes an indirect vector through location 201OH. The TRAP instruction provides a single instruction interrupt useful
in designing software debuggers. The TRAP instruction prevents the acknowledgement of interrupts until
after execution of the next instruction.
Unimplemented Opcode

Opcodes which are not implemented on the 80Cl96KB
will cause an indirect vector through location 2012H.
User code or hardware which may have failed and run
into an unimplemented opcode can software recover
through this interrupt. The DJNZW instruction is not
supported on the 80Cl96KB but remains a valid opcode, therefore, no interrupt will occur.

.4-31

270651-10

Figure 5-2. 80C196KB Interrupt Structure
Block Diagram

Five registers control the operation of the interrupt system: INT_PEND, INT_PENDI, INT_MASK and
INT_MASKl and the PSW which contains a global
disable bit. A block diagram of the system is shown in
Figure 5-2. The transition detector looks for 0 to 1 transitions on any of the sources. External sources have, a
maximum transition speed of one edge every state time.
Sampling will be guaranteed if the level on the interrupt
line is held for at least one state time. If the interrupt
line is not held for at least one state time, the interrupt
may not be detecled.

80C196KB USER'S GUIDE

5.1 Interrupt Control

format of these registers-is the same as that of the Interrupt Pending Register shown in Figure 5-3;'

Interrupt Pending Register

The INT_MASKand INT--,MASKI registers can be
read or written as byte registers. A one in any bit position will enable the corresponding interrupt source and
a zero will disable the source. The hardware will save
any interrupts that occur by setting bits in the pending'
register, even if t,he interrupt mask bit is cleared. The
INT-,-MASK register is the lower eight hits of the
PSW so the PUSHF and POPF instructions save and
restore the INT_MASK register as well as the global
interrupt lockout and .the, arithmetic flags. Both the
INT_MASK and INT_MASKI registers can be
saved with the PUSHA and POPA Instructions.

When the hardware detects one of the sixteen interrupts it sets the corresp~mding bit in one o( two pending
interrupt registers (INT_PEND-09H and INT_
PENDl-12H). When the interrupt vector is taken, the
pending bit is cleared. These registers, the formats of
which are shown in Figure 5-3, can be read or modified
as byte registers. They can ,be read to determine which
of the interrupts are pending at any given time or modified to either clear pending interrupts or generate interrupts under software control. Any software which
modifies the INT_PEND registers should ensure that
the entire operation is inseparable. The easiest way to
do this is to use the logical instructions in the two or
three operand format, for example:

ANDB
ORB

Global Disable

The processing of all interrupts except the NMI, TRAP
and unimplemented opcode interrupts can be disabled
by clearing the I bit in the PSW. Setting the I bit will
enable interrupts that have mask register bits which are
set. The I bit is controlled by the EI (Enable Interrupts)
and DI (Disable Interrupts) instructions. Note that the
I bit only controls the actual servicing of interrupts.
Interrupts that occur during periods of lockout will be
held in the pending register and serviced on a: prioritized basis when the lockout period ends.

INT_PEND,#llllllOlB
; Clears the AID Interrupt
INT_PEND,#OOOOOOlOB
; Sets the AID Interrupt

Caution must be used when writing to the pending register to' clear interrupts. If the interrupt has 'already
been acknowledged when the bit is cleared, a 5 state
time "partial" interrupt cycle will occur. This is because the 80CI96KB will have to fetch the next instruction of the normal instructionflQw, instead of proceeding with the interrupt processing. The effect on the program will be essentially that of an extra two NOP~
This can be prevented by clearing the bits using a 2
operand immediate logical, as the SOC196KB holds off
acknowledging interrupts during these "read/modify/
write" instructions.

5.2 Interrupt Priorities
The priority encoder looks at all of the interrupts which
are both pending and enabled, and selects the one with
the highest priority. The priorities are shown in Figure
5-4 (IS is highest, 0 is lowest). The interrupt generator
then forces a call to the location in the indicated vector
location. This location would be the starting location of
the Interrupt Service Routine (ISR).

Interrupt Mask Register

Individual interrupts can be enabled or disabled by setting or clearing bits in the interrupt mask registers
(INT_MASK-OSH and INT_MASKl-I3H). The

12H
13H

09H
08H

IPEND1:
IMASK1:

IPEND:
IMASK:

NMI

FIFO
FULL

EXT
INT1

T2
OVF

T2
CAP

HSI4

EXT
INT

SER SOFT HSI.O
PORT TIMER PIN

HSO
PIN

HSI
AID TIMER
DATA DONE OVF

Figure 5-3. Interrupt Mask and Pending Registers

4-32

inter

80C196KB USER'S GUIDE

Number

Source

Note that location 200CH in the interrupt vector table
would have to be loaded with the label serial_io_isr
and the interrupt be enabled for this routine to execute.

Vector
Priority
Location

INT15

NMI

203EH

INT14

HSI FIFO Full

203CH

INn3

EXTINT1

203AH

13'

INT12

TIMER2 Overflow

2038H

INT11

TIMER? Capture

2036H

11
10

INT10

4th Entry into HSI FIFO

2034H

INT09

2032H

INT08

2030H

SPECIAL Unimplemented Opcode

2012H

N/A

SPECIAL Trap

2010H

N/A

INT07

EXTINT

200EH

INT06

Serial Port

200CH

INT05

Software Timer

200AH

INT04

HSI.O Pin

2008H

INT03

High Speed Outputs

2006H

INT02

HSI Data Available

2004H

INT01

AID Conversion Complete

2002H

INTOO

Timer Overflow

2000H

Figure 5·4. 80C196KB Interrupt Priorities

This priority selection controls the order in which
pending interrupts are passed to the software via interrupt calls. The software can then implement its own
priority structure by controlling the mask registers
(INT_MASK and INT_MASKI). To see how this is
done, consider the case of a serial 1/0 service routine
which must run at a priority level which is lower than
the HSI data available interrupt but higher than any
other source. The "preamble" and exit code for this
interrupt service routine would look like this:

There is an interesting chain of instruction side-effects
which makes this (or any other) 80Cl96KB interrupt
service routine execute properly:
A) After the interrupt controller decides to process an
interrupt, it executes a "CALL", using the location
from the corresponding interrupt vector table entry
as the destination. The return address is pushed
onto the stack. Another interrupt cannQt be serviced
until after the first instruction following the interrupt call is executed.
B) The PUSHA instruction, which is now guaranteed to execute, saves the PSW, INT_MASK,
INT_MASKI, and the WSR on the stack as two
words, and clears them. An interrupt cannot be
serviced immediately following a PUSHA instruction. (If INT_MASKI and the WSR register are
not used, or 8096BH code is being executed,
PUSHF, which saves only the PSW and
INT_MASK, can be used in place of PUSHA).
C) LD INT_MASK, which is guaranteed to execute,
enables those interrupts that are allowed to interrupt this ISR. This allows the software to establish
its own priorities independent of the hardware.
D) The ~I instruction reenllbles the processing of interrupts'with the new priorities.
E) At the end of the ISR, the POPA instruction restores the PSW, INT_MASK, INT_MASKI, and
WSR to their original state when the interrupt occurred. Interrupts cannot occur immediately following a POPA instruction so the RET instruction is
guaranteed to execute. This prevents the stack from
overflowing if interrupts are ocq.lrring at high frequency. (If INT_MASKI and the WSR are not
being used, or 8096BH code is being executed,
POPF, which restores only the PSW and
INT_MASK, can be used in place of POPA.)

serial_io_isr:
'PUSHA
; Save the PSW, INT_MASK
; INT_MASKl,' and WSR
LDB
INT_MASK,#OOOOOIOOB
EI
; Enable interrupts again

POPA
RET

S,rvi"

th,int,rrupt

Restore

4-33

80C196KB' USER,'S GUIDE

Notice that the "preamble" and exit code for the interrupt service routine does not include any code for saving or restoring registers. This is because it has been
assumed that the interrupt service routine has been allocated its own private set of registers from the onboard register file. The availability of some 230 bytes of
register storage makes this quite practical.

5.3 Critical Regions
Interrupt service routines must sometimes share data
with other routines. Whenever the programmer is coding those sections of code which access these shared
pieces of data, great care must be taken to ensure that
the integrity of the data is maintained. Consider clearing a bit in the interrupt pending register as part of a
non-interrupt routine:
LDB
ANDB
STB

AL, INT _PEND

AL,#blLmask
AL,INT_PEND

This code works if no other routines are operating concurrently, but will cause occasional but serious problems if used in, a concurrent environment. (All programs which make use of interrupts must be considered
to be part of a concurrent environment.) To demonstrate this problem, assume that the INT_PEND register contains OOOOlll1B and bit 3 (HSO event interrupt pending) is to be reset. The code does work for this
data pattern but what happens if an HSI interrupt occurs somewhere between the LDB and the STB instructions? Before the LDB instruction INT_PEND contains 00001111B and after the LDB instruction so does
AL. If the HSI interrupt service routine executes at this
point then INT_PEND will change to OOOOIOI1B.
The ANDB changes AL to 00OO0l11B and the STB
changes INT_PEND to OOOOOIIIB. It should be
OOOOOOIIB. This code sequence has managed to generate a false HSI interrupt The same basic process can
generate an amazing assortment of problems and headaches. These problems can be avoided by assuring mutual exclusion which basically means that if more than
one routine can change a variable, then the programmer must ensure exclusive access to the variable during
the entire operation on the variable.

if interrupts are disabled. Depending on system configurations, several other SFRs might also need to be
changed in a! single instruction for the same reason.
When variables must be modified without interruption"
and a single instruction can not be used, the programmer must create what is termed a critical region in
which it is safe to modify the variable. One way to do
this is to simply disable interrupts with a D I instruc'
tion, perform the modification, and then re-enable interrupts with an EI instruction. The problem with this
approach is that it leaves the interrupts enabled even if
they were not enabled at the start. A better solution is
to enter the critical region with a PUSHF instruction
which saves the PSW and also clears the interrupt enable flags. The region can then be terminated with a
POPF instruction whic\I returns the interrupt enable to
the state it was in before the code sequence. It should be
noted that some system configurations might require
more protection to form a critical region. An example
is a system in which more than one processor has access to a common resource such as memory or external
I/O devices.

5.4 Interrupt Timing
The 80Cl96KB can be interrupted from four different
external sources; NMI, P2.2, HSI.O an!i PO.7. All external interrupts are sampled during PHI or CLKOUT
low and are latched internally. Holding levels on external interrupts for at least one state, time will ensure
recognition of the interrupts.
The external interrupts on the 80C196KB, although
sampled during PHI, are edge triggered interrupts as
opposed to level triggered. Edge triggered interrupts
will generate only one interrupt if the input is held
high. On the other hand, level triggered interrupts will
generate multiple interrupts when held high.'
Interrupts are not always acknowledged immediately.
If the interrupt signal does not, occur prior to 4 statetimes before the end of an instruction, the interrupt
may not be acknowledged until after the next instruc.
tionhas been executed. This.is because an instruction is
fetched and prepared for execlltion a few state times
before it is actually executed.

In many cases the instruction set of the 80Cl96KB allows the variable to be modified with a single instruction. The code in the above example can be implemented with a single instruction.

There are 6 instructions which always inhibit interrupts
from being acknowledged until after the next instruction has been executed. These instructions are:
EI, DI - Enabkand disable all interrupts by toggling the global disable bit (PSW.9).
PUSHF - PUSH Flags pushes the PSW/IN:r_
MASK pair then clears it, leaving both
INT_MASK and PSW.9 clear.

ANDB

Instructions are indivisible so mutual exclusion is ensured in this case. Changes to the INT_PEND or
INT_PENDI register must be made as a single instruction, since bits can be changed in'this register even

4-34

inter
POPF

80C196KB USER'S GUIDE

PUSHA ,
POPA -

POP Flags pops the PSW lINT_MASK
pair off the stack
PUSH All does a PUSHF, then pushes
the INT_MASK l/WSR pair and clears'
INT_MASKl
POP All pops the INT_MASKl/WSR
pair and then does a POPF

5.5 Interrupt Summary

Interrupts can also not occur immediately after execution of:
Unimplemented Opcodes
TRAP - The software trap instruction
SIGND - The signed prefix for multiply and divide
instructions

Many of the interrupt vectors on the 8096BH were
shared by multiple interrupts. The interrupts which
were shared on the 8096BH are: Transmit Interrupt,
Receive Interrupt, HSI FIFO Full, Timer2 Overflow
and EXTINT. On the 80C196KB, each of these interrupts have their own interrupt vectors. The source of
the interrupt vectors are typically programmed through
control registers. These registers can be read in Window 15 to determine the source of any interrupt. Interrupt sources with two possible interrupt vectors, serial
receive interrupt sharing serial port and receive interrupt vectors for example, should be configured for only
one interrupt vector.

Interrupts with separate vectors include: NMI, TRAP,
Unimplemented Opcode, Timer2 Capture, 4th Entry
into HSI FIFO, Software timer, HSI.O Pin, High Speed
Outputs, and AID conversion Complete. The NMI,
TRAP and Unimplemented Opcode interrupts were
covered in section 5.0.

The maximum number of state times required from the
time an interrupt is generated (not acknowledged) until
the 80CI96KB begins executing code at the desired location is the time of the longest instruction, NORML
(Normalize - 39 state times), plus the 4 state times
prior to the end of the previous instruction, plus the
response time (16(internal stack) or 18(external stack)
state tillles). Therefore, the maximum response time is
61 (39 + 4 + 18) state times. This does not include the
10 state times' required for PUSHF if it is used as the
first instruction in the interrupt routine or additional
latency caused by having the interrupt masked or disabled. Refer to Figure 5-5, Interrupt Response Time, to
visualize an example of worst case scenario.

EXTINT and PO.7

The 80CI96KB has two external interrupt vectors;
EXTINT (200EH) and EXTINTI (203AH). The
EXTINT vector has two alternate sources selectable by
IOCI.I, the external interrupt pin (Port 2.2) and Port
0.7, The external interrupt pin is the only source for the
EXTINTI interrupt vector. The external interrupt pin
should not be programmed to interrupt through both
vectors. Both external interrupt sources are rising edge
triggered,

Interrupt latency time can be reduced by careful selection of instructions in areas of code where interrupts
are expected. Using 'El'followed immediately by a
long instruction (e.g. MUL, NORML, etc.) will increase the maximum latency by 4 state times, as an
interrupt cannot occur between EI and the instruction

STATE TIMES

following EI. The 01, PUSHF, POPF, PUSHA, POPA
and TRAP instructions will also cause the same situation. Typically these instructions would only effect latency when one interrupt routine is already in process"
as these instructions are seldom used at other times.

3 9 - - - - ·- 1 6 - - - . . - - 2 - - - . . . . - 6--.

432

EXECUTION

'PUSHF'

INTERRUPT ROUTINE

EXTINT~
PENDING
BIT
RESPONSE TIME

..J SET
f-I.--------270651-11

Figure 5-5. Interrupt Response Time

4-35

80C196KB USER'S GUIDE

Serial Port Interrupts
The serial port generates one of three possible interrupts: Transmit interrupt TI(2030H), Receive Interrupt
RI(2032H) and SERIAL(200CH). Refer to section 10
for information on the serial port interrupts. The
8096BH shared the TI and RI interrupts on the SERIAL interrupt vector. On the 80C196KB, these interrupts share both the serial interrupt vector and have
their own interrupt vectors. Ideally, the transmit and
receive interrupts should be programmed as separate
interrUpt vectors while disabling the SERIAL interrupt. For 8096BH compatibility, the interrupts can still
use the SERIAL interrupt vector.

are individually enabled by setting bits 2 and 3 oflOC1:
bit 2 for Timer!, and bit 3 for Timer2. Which timer
actually caused the interrupt can be determined by bits
4 and 5 of 10SI: bit 4 for Timer2 and 5 for Timer!. On
the 80CI96KB Timer2 overflow(OH or 8000H) has a
separate interrupt vector through location 2038H.
Timer2 Capture
The 80CI96KB can generate an interrupt in response
to a Timer2 capture triggered by a rising edge on P2.7.
Timer2 Capture vectors through location 2036H.
High Speed Outputs

HSI FIFO FULL and HSI DATA AVAILABLE
HSI FIFO FULL and HSI DATA AVAILABLE interrupts shared the HSI DATA AVAILABLE interrupt vector on the 8096BH. The source of the HS,I
DATA AVAILABLE interrupt is controlled by the
setting of 1/0 Control Register I ,(IOC 1.7). Setting
IOC1.7 to zero will generate an interrupt when a time
value is loaded into the holding register. Setting the bit
to one generates an interrupt when the FIFO, independent of the holding register, has six entries in it.
On the 80C196KB, separate interrupt vectors are available for the HSI FIFO FULL(203CH) and HSI DATA
AV AILABLE(2004H) interrupts. The interrupts
should be programmed for separate interrupt vector locations. Refer to Section 8 for more information on the
High Speed Inputs.

The HSI FIFO can generate an interrupt when the HSI
has four or more entries in the FIFO. The HSI FIFO_
4 interrupt vectors through location 2034H.· Refer to
Section 8 for more information on the High Speed Inputs.

The High Speed Outputs interrupt can be generated in
response to a programmed HSO command which causes an external event. HSO commands which set or clear
the High Speed Output pins are considered external
events. Status Register IOS2 indicates which HSO
events have occured and can be used to arbitrate which
HSO command caused the interrupt. The High Speed
Output 'interrupt vectors indirectly through location
2006H. For more information on High Speed Outputs,
refer to Section 9.
Software Timers
HSO commands which create internal events can interrupt through the Software Timer interrupt vector. Internal events include triggering an AID conversion, resetting Timer2 and software timers. Status registers
IOS2 and 10SI can be used to determine which internal
HSO event has occured. Location 200AH is the interrupt vector for the Software Timer interrupt. Refer to
Section 9 for more information on software timers and
the HSO.

AID Conversion Complete
The AID Conversion Complete interrupt can generate
an interrupt in response to a completed AID conversion. The interrupt vectors indirectly through location
2002H. Refer to section II for more information on the
AID Converter.

HSI.O External Interrupt
The rising edge on HSI.O pin can be used as an external
interrupt. The HSI.O pin is sampled during PHI or
CLKOUT low. Sampling is guaranteed if the pin is
held for at least one state time. The interrupt vectors
through location 2008H. The pin does not need to be
enabled to the HSI FIFO in order to generate the interrupt.

6.0 Pulse Width Modulation Output
(D/A)
Digital to analog conversion can be done with the Pulse
Width Modulation output; a block diagram of the circuit is shown in Figure 6-1. The 8-bih:ounter is incremented every state time. When it equals 0, the PWM
output is set to a one. When the counter matches the
value in the PWM register, the output is switch!!d low.
When the counter overflows, the output is once again
switched high. A typical output waveform is shown in

Timer2 and Timer1 overflow
Timer2 and Timer! can interrupt on overflow. These
interrupts shared the same interrupt vector TIMER
OVERFLOW(2000H) on the 8096BH. The interrupts

4-36

intJ

80C196KB USER'S GUIDE

Figure 6-2. Note that when the PWM register equals
00, the output is always low. Additionally, the PWM
register will only be reloaded from the temporary latch
when the counter overflows. This means the compare
circuit will not recognize a new value' until the counter
has expired preventing missed PWM edges.
The 80C196KB PWM unit has a prescaler bit (divide
by 2) which is enabled by setting IOC2.2 = 1. The
PWM frequencies are shown in Figure 6-3. The output
waveform is a variable duty cycle pulse which 'repeats
every 256 or 512 state times (42.75 J-Ls or 85.5 J-Ls at
12 MHz). Changes in the duty cycle are made by writing to the PWM register at location 17H. The value
programmed into the PWM register can be read in
Window 15 (WSR = 15). There are several types of motors which require a PWM waveform for more efficient
operation. Additionally, if this waveform is integrated
it will produce a DC level which can be changed in 256
steps by varying the duty cycle. as described in the next
section.
XTAL1 =

8MHz

10MHz

12 MHz

IOC2.2 = 0
IOC2.2 = 1

15.6 KHz
7.8 KHz

19.6 KHz
9.8 KHz

23.6 KHz
11.8 KHz

PWM
OUTPUT

STATE TIME CLOCK
F(XTAL1 )/2

270651-12

• Duty Cycle Programmable

256 Steps

Figure 6-1. PWM Block Diagram

Figure 6-3. PWM Frequencies

The PWM output shares a pin with Port 2, pin 5 so
that these two features cannot be used at the same time.
IOCI.O equal to 1 selects the PWM function instead of
the standard port function.

DUTY
CYCLE

PWM CONTROL
REGISTER VALUE

OUTPUT WAVEFORM

HI
LO

10%

~~Jl~____~n~____~n~_____

50%

128

HI
LO

90%

230

HI
LO

99.6%

255

HI
LO

-1

u
270651-13

Figure 6-2. Typical PWM Outputs

4-37

80C196KB USER~S GUIDE

drift, a highly accurate 8-bit 0 to A converter can be
made using either the HSO or the PWM output. Figure
6-5 shows two typical circuits. If the HSO is used the
accuracy could be theoretically extended to l6-bits,
however the temperature and noise .related problems
would be extremely hard to handle.

6.1 Analog Outputs
Analog outputs can be generated by two methods, either by using the PWM output or the HSO. See Section ,
9.7 for information on generating a PWM with the
High Speed Output Unit. Either device will generate a
rectangular pulse train that varies in duty cycle and
period. If a smooth analog signal is desired as an output, the rectangular waveform must be filtered.
In most cases this filtering is best done after the signal
is buffered to make it swing from 0 to 5 volts since both
of the outputs are guaranteed only to low current levels. A block diagram of the type of circuit nee,!led is
shown in Figure 6-4. By proper selection of components, accounting for temperature and power supply

'80C196KB
HSO
OR
PWM

BUFFER
TO MAKE
OUTPUT
SWING
RAIL
TO
RAIL

When driving some circuits it may be desirable to use
unfiltered Pulse Width Modulation. This is particularly
true for motor drive circuits. The PWM output can
generate these waveforms if a fixed period on the order
of 64 f-ts is acceptable. If this is not the case then the
HSO unit can be used. The HSO can generate a vari. able waveform with a duty cycle variable in up to 65536
steps and a period of up to 87.5 milliseconds. Both of
these outputs produce CHMOS levels.

FILTER
(PASSIVE
OR
ACnVE)

POWER
AMP

I---- ANALOG
OUTPUT

(OpnONAL)

(OPnONAL)

270651-14

Figure 6-4. 01 A Buffer Block Diagram

Vcc

* 1/2 VQ3001 P
6

270'
PWM----~VV~----

S.1K

. .____~~__--~t-----ANALOG

OUT

9
270651-15

80C196KB

HSO
OR

HIGH

ANALOG

~_----"'Nw----_----_IIMPEDANCE .....- - - OUTPUT

PWM

AMP

270651-16

Figure 6-5. Buffer Circuits for 01 A

4-38

80C196KB USER'S GUIDE

7.0 TIMERS
7.1 Timer1
Timer! is a 16-bit free-running timer which is incremented every eight state times. An interrupt can be
generated in response to an overflow. It is read through
location OAH in Window 0 and written in Window 15.
Figure 7-1 shows a block diagram of the timers.

Capture Register

The value in Timer2 can be captured into the
T2CAPture register by a rising edge on P2. 7. The edge
must be held for at least one state time as discussed in
the next section. T2CAP is located at OCH in Window
15. The interrupt generated by a capture vectors
through location 2036H.
Fast Increment Mode

Care must be taken when writing to it if the High Speed
I/O (HSIO) Subsystem is being used. HSO time entries
in the CAM depend on exact matches with Timer!.
Writes to Timer! should be taken into account in software to ensure events in the HSO CAM are not missed
or occur in an order which may be unexpected. Changing Timer! with incoming events on the High Speed
Input lines may corrupt relative references between
captured inputs. Further information on the High
Speed Outputs and High Speed Inputs can be found in
Sections 8 and 9 respectively.

Timer2 can be programmed to run in fast increment
mode to count transitions every state time. Setting
IOC2.0 programs Timer2 in the Fast Increment mode.
In this mode, the events programmed on the HSO unit
with Timer2 as a reference will not execute properly
since the HSO requires eight state times to compare
every location in the HSO CAM. With Timer2 as a
reference for the HSO unit, Timer2 transitioning every
state time may cause programmed HSO events to be
missed. For this reason, Timer2 should not be used as a
reference for the HSO if transitions occur faster than
once every eight state times.

7.2 Timer2

Timer2 should not be RESET in the fast increment
mode. All Timer2 resets are synchronized to an eight
state time clock. If Timer2 is reset when clocking faster
than once every 8 states, it may' reset on a different
count.

Timer2 on the 80Cl96KB can be used as an external
reference for the HSO unit, an up/down counter, an
external event capture or as an extra counter. Timer2 is
clocked externally using either the T2CLK pin (P2.3)
or the HSI.l pin depending on the state of IOCO.7.
Timer 2 counts both positive and negative transitions.
The maximum transition speed is once per state time in
the Fast Increment mode, and once every 8 states otherwise. CLKOUT cannot be used directly to clock
Timer2. It must first be divided by 2. Timer2 can be
read and written through location OCH in Window O.
Figure 7-1 shows a block diagram of the timers.

Up/Down Counter Mode

Timer2 can be made to count up or down based on the
Port 2.6 pin if IOC2.1 = 1. However, caution must be
used when this feature is working in conjunction with
the HSO. If Timer2 does not complete a full cycle it is
possible to have events in the CAM which never match
the timer. These events would stay in the CAM until
the CAM is cleared or the chip is reset.

Timer2 can be reset by hardware, software or the HSO
unit. Either T2RST (P2.4) or HSl.O can reset Timer2
externally depending on the setting of IOCO.S. Figure
7-2 shows the configuration and input pins of Timer2.
Figure 7-3 shows the reset and clocking options for
Timer2. The appropriate control registers can be, read
in Window 15 to determine the programmed modes.
However,.IOCO.l(T2RST) is not latched and will read
al.

7.3 Sampling on External Timer Pins
The T2UP/DN, T2CLK, T2RST, and T2CAP pins are
sampled during PHI. PHI roughly corresponds to
CLKOUT low externally. For valid sampling, the inputs should be present 30 risec prior to the rising edge
of CLKOUT or it may not be sampled until the next
CLKOUT. If the T2UP/DN signal changes and becomes stable before, or, at the same time that the
T2CLK signal changes, the count will go into the new
direction.

Caution should be used when writing to the timers if
they are used as a reference to the High Speed Output
Unit. Programmed HSO commands could be missed if
the timers do not count continuously in one direction.
High Speed Ol:ltput events based on Timer2 must be
carefully programmed when using Timer2 as an
up/down counter or is reset externally. Programmed
events could be missed or occur in the wrong order.
Refer to section 9' for more information on using the
timers with the High Speed Output Unit.

4-39

80C196KB USER'S GUIDE

[J~[J+--------:--P2.7
....---P2.6

1+---T2CLK
1+---HSI.l

'----------T2RST
270651-5

Figure 7-1. Timer Block Diagram
Bit

Bit

IOCO.1

Reset Timer2 each write

No action

IOCO.3

Enable external reset

Disable

IOCO.5

HSI.O is ext. reset source

T2RST is reset source

lOCO.?

HSI.1 is T2 clock source

T2CLK is clock source

IOC1.3

Enable Timer2 overflow int.

Disable overflow interrupt

IOC2.0

Enable fast increment

Disable fast increment

IOC2.1

Enable downcount feature

P2.6

Count down if IOC2.1

IOC2.5

Interrupt on ?FFFH/SOOOH

P2.?

Capture Timer2 into
T2CAPture on rising edge

Disable downcount

Count up
Interrupt on OFFFFH/OOOOH

Figure 7-2. Timer2 Configuration and Control Pins

7.4 Timer Interrupts
Both Timer! and Timer2 can trigger a timer overflow
interrupt and set a flag in the I/O Status Register I
(lOS I). Timerl overflow is controlled oy setting
IOC1.2 and the interrupt status is indicated in IOSI.5.
The TIMER OVERFLOW interrupt is enabled by setting INT_MASK.O.
A Timer2 overflow condition interrupts through location 2000H by setting IOCI.3 and setting INT_
MASK.O. Alternatively, Timer2 overflow can interrupt
through location 2038H by setting INT_MASKI.3.
The status of the. Timer2 overflow interrupt is indicated
in IOSI.4.
IOCO.5

Interrupts can be generated if Timer2 crosses the
OFFFFH/OOOOH boundary or the 7FFFH/8000H
boundary in either direction. Byhaving two interrupt
points it is possible to have 'interrupts enabled even if

270651-17

Figure 7-3. Timer2 Clock and Reset Options

4-40

80C196KB USER'S GUIDE

Timer2 is counting up and down centered around one
of the interrupt points. The boundaries used to control
the Timer2 interrupt is determined by the setting of
IOC2.5. When set, Timer2 will interrupt on the
7FFFH/8000H boundary, otherwise, the OFFFFH/
OOOOH boundary interrupts.

timer interrupts are controlled by the Interrupt Mask
Register bit O. In all cases, setting a bit enables a function, while clearing a bit disables it.

A T2CAPTURE interrupt is enabled by setting INT_
MASK 1.3. The interrupt will vector through location
2036H.

The High Speed Input Unit (HSI) can record the time
an event occurs with respect to Timer!. There are 4
lines (HSI.O through HSI.3) which can be used in this
mode and up to a total of 8 events can be recorded.
HSI.2 and HSI.3 are bidirectional pins which can also
be used as HSO.4 and HSO.5. The I/O Control Registers (lOCO and lOCI) determine the functions of these
pins. The values programmed into lOCO and lOCI can
be read in Window IS. A block diagram of the HSI unit
is shown in Figure 8-1.

8.0 HIGH SPEED INPUTS

Caution must be used when examining the flags, as any
access (including Compare and Jump on Bit) of 10SI
clears bits 0 through 5 including the software timer
flags. It is, therefore, recommended to copy the byte to
a temporary register before testing bits. Writing to
10SI in Window 15 will set the status bits but not cause
interrupts. The general enabling and disabling of the
HSI Trigger Options

FIFO
INTERRUPT

~ HITOLO

-r--IHiOR

CONTROL
& LOGIC

LOTOHI

111

T
sliR

L'Ol-

7x20 BIT
FIFO

..n.nn.n.n.n.n.
EVERY EIGHTH POSITIVE
TRANSITION

HSLSTATUS '

270651-18

270651-19

Figure 8-1. High Speed Input Unit
HSI Status Register (HSI_Status)

I 3 I 2 I 1 I 0 I 06H '

C HSI.O STATUS
HSI.l STATUS
HSI.2 STATUS
HSI.3 STATUS

WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT (STATUS BIT) INDICATES WHETHER OR NOT AN EVENT
HAS OCCURED ON THIS PIN AND THE UPPER BIT (INPUT BIT)
INDICATES THE CURRENT INPUT LEVEL OF THE PIN.

Figure 8-2. HSI Status Register Diagram

4-41

270651-22

80C196KB USER'S GUIDE

When an HSI event occurs, a 7 X 20 FIFO stores the 16
bits of Timer!, and the 4 bits indicating which pins
recorded events associated with that time tag. Therefore, if multiple pins are being used as HSI inputs, software must check each status bits when processing on
HSI event. MuItiplepins can recognize events with the
same time tag. It can take up to 8 state times for this
information to reach the holding register. For this reason, 8 state times must elapse between consecutive
reads of HSI_TIME. When the FIFO is full, one additional event, for a total of 8 events, can be stored by
considering the holding register part of the FIFO. If the
FIFO and holding register are full, any additional
events will not be recorded.

T2RST - - 0 • - - IOCO.S

~~""'----T2

HSI.O

~_------HSI
••• IOCO.2

ro~-------HSI

TIMER2

T2CLK - - 0 ,l_ - IOCO.7

CLOCK

HSI.l

.-- IOCO.4

"-0------- HSI

HSI.2 - - 0

• - - IOCO.6

HSI.3

~"-o------- HSI

8.1 HSI Modes

270651-21

There are 4 possible modes of operation for each of the
HSI pins. The HSI_MODE register at location 03H
controls which pins wiIllook for what type of events. In
Window 15, reading the register will read back the programmed HSI mode. The 8-bit register is set up as
shown in Figure 8-3.

03H

' - - - - - - - - HSI.2 MODE
' - - - - - - - - - - HSI.3 MODE
WHERE EACH 2 - BIT MODE CONTROL FIELD
DEFINES ONE OF 4 POSSIBLE MODES:
00
01
10
11

RESET

• - - IOCO.3
• - - IOCO.O

8 POSITIVE TRANSITIONS
EACH POSITIVE TRANSITION
EACH NEGATIVE TRANSITION
EVERY TRANSITION
(POSITIVE AND NEGATIVE)

Figure 8·4. lOCO Control of HSI Pin Functions

8.2 HSI Status
Bits 6 and 7 of the I/O Status Register 1 (lOS I-see
Figure 8-5) indicate the status of the HSI FIFO. If bit 7
is set, the HSI holding-register is loaded. The FIFO
mayor may not contain 1-5 events. If bit 6 is set, the
FIFO contains 6 entries. If the FIFO fills, future events
will not be recorded. Reading 10SI clears bits 0-5, so
keep an image of the register and test the image to
retain all 6 bits.
Reading the HSI holding register must be done in ·a
certain order. The HSI_STATUS Register (Figure 82) is read first to obtain the status and input bits. Second, the HSI_TIME Register (04H) is read to obtain
the time tag. Reading HSI_TIME unloads one level of
the FIFO. If the HSI_TIME is read before
HSI_STATUS, the contents of HSI_STATUS associated with that HSI_TIME tag are lost.

270651-20

SOFTWARE TIMER 0 EXPIRED

Figure 8·3. HSI Mode Register 1

SOFTWARE TIMER 1 EXPIRED
SOFTWARE TIMER 2 EXPIRED

The maximum input speed is 1 event every 8 state times
except when the 8 transition mode is used, in which
case it is 1 transition per state time.

SOFTWARE TIMER 3 EXPIRED
TIMER 2 HAS OVERFLOW
TIMER 1 HAS OVERFLOW

The HSI pins can be individually enabled and disabled
using bits in lOCO as shown in Figure 8-4. If the pin is
disabled, transitions are not entered in the FIFO. However, the input bits of the HSI_STATUS register (Figure 8-2) are always valid regardless of whether the pin
is enabled to the FIFO. This allows the HSI pins to be
used as general purpose input pins.

HSI FIFO IS FULL
HSI HOLDING REGISTER DATA AVAILABLE
16H
270651-23

Figure 8·5. 110 Status Register 1

4-42

80C196Ka USER'S GUIDE

If the HSI_TIME register is read without the holding
register being loaded, the returned value will be indeterminate. Under the same conditions, the four bits in
HSI_STATUS indicating which events have occurred
will also be indeterminate. The four HSI_STATUS
bits which indicate the current state of the pins will
always return the correct value.

The HSI.O pin can g~nerate an interrupt on the rising
edge even if its not enabled to the HSI FIFO. An interrupt generated by this pin vectors through location
2008H.

It should be noted that many of the Status register conditions are changed by a reset, see section 13. Writing
to HSI_TIME in window 15 will write to the HSI
FIFO holding register. Writing to HSI_STATUS in
Window 15 will set the status bits but will not affect the
input bits.

The HSI pins are sampled internally once each state
time. Any value on these pins must remain stable for at
least 1 ful1 state time to guarantee that it is recognized:
The actual sampling occurs during PHI or during
CLKOUT low. The HSI inputs should be valid at least
30 nsec before the rising of CLKOUT. Otherwise, the
HSI input may be sampled in the next CLKOUT.
Therefore, if information is to be synchronized to the
HSI it should be latched on the rising edge of
CLKOUT.

8.4 HSI Input Sampling

8.3 HSI Interrupts
Interrupts can be generated by the HSI unit in three
ways: when a value moves from the FIFO into the
holding register; when the FIFO (independent of the
holding register) has 4 or more event stored; when the
FIFO has 6 or more events.

8.5 Initializing the HSI
To start the HSI, the fol1owing steps and the sequence
must be observed; 1) flush the FIFO, 2) enable the HSI
interrupts, and 3) initialize and enable the HSI pins.
The following section of code can be used to flush the
FIFO:

The HSI DATA AVAILABLE and HSI FIFO FULL
interrupts are shared on the 8096BH. The source for
the HSI DATA AVAILABLE interrupt is controlled
by IOC1.7. When IOC1.7 is cleared, the HSI will generate an interrupt when the holding register is loaded.
The interrupt indicates at least one HSI event has occurred and is ready to be processed. The interrupt vectors through location 2004H. The interrupt is enabled
by setting INT_MASK.2. The generation of a HSI
DATA AVAILABLE interrupt will set IOS1.7. The
HSI FIFO FULL interrupt will vector through HSI
DATA AVAILABLE if IOC1.7 is set. On the
80C196KB, the HSI FIFO FULL has a separate interrupt vector at location 203CH.

reflush: 1d 0, HSLT1ME ;c1ear an event
skipO
;wai t 8 state times
skipO
j bs 10S1, 7, reflush

Enabling the HSI pins before enabling the interrupts
can cause a FIFO lockout condition. For example, if
the HSI pins were enabled first, an event could get
loaded into the holding register before the HS1_
DAT A~VAILABLE interrupt is enabled. If this
happens, no HSI_DA TA_A VAILABLE interrupts
will ever occur.

A HSI FIFO FULL interrupt occurs when the HSI
FIFO has six or more entries loaded independent of the
holding register. Since all interrupts are rising edge triggered, the processor will not be reinterrupted until the
FIFO first contains 5 or less records, then contains six
or more. The HSI FIFO FULL interrupt mask bit is
INT_MASK1.6. The occurrence of a HSI FIFO
FULL interrupt is indicated by IOS1.6. Earlier warning
of a impending FIFO ful1 condition can be achieved by
the HSI FIFO 4th Entry interrupt.

9.0 HIGH SPEED OUTPUTS
The High Speed Output unit (HSO) trigger events at
specific times with minimal CPU overhead. Events are
generated by writing commands to the HSO_COMMAND register and the relative time at which the
events are to occur into the HSO_TIME register. In
Window IS, these registers will read the last value programmed in the holding register. The programmable
events include: starting an AID conversion, resetting
Timer2, setting 4 software flags, and switching 6 output
lines (HSO.O through HSO.5). The focinat of the
HSO_COMMAND register is.shown in Figure 9-1.
Commands OCH and ODH are reserved for use on future products. Up to eight events can be pending\at one
time and interrupts can be generated whenever any of
these events are triggered. HSO.4 and HSO.5 are bi-

The HSI_FIFO_4 interrupt generates an interrupt
when four or more events are stored in the HSI FIFO
independent of the holding register. The interrupt is
enabled by setting INT_MASK 1.2. The HSI_
FIFO_4 vectors indirectly through location 2034H.
There is no status flag associated with the HSI_
FIFO_4 interrupt since it has its own independent interrupt vector..

4-43

80C196KB USER'S.GUIDE

7
HSO_
COMMAND

CAM
LOCK

TMR2/ SET/
TMR1 CLEAR

INT/
lNT

CHANNEL

06H

CAM Lock - Locks event in CAM if this is enabled by IOC2.6 (ENA_LOCK)
TMR/TMRI - Events Based on Timer2lBased on Timer! If 0
SET/CLEAR - Set HSO pin/Clear HSO pin if 0
INT/INT
- Cause interrupt/No interrupt if 0
CHANNEL:
0-5: HSO pins 0-5 separately
6:
HSO pins 0 and I together
(in Hex)
7:
8-B:
C-D:
E:
F:

HSO pins 2 and 3 together
Software Timers 0-3
Unflagged Events (Do not use for future compatibility)
Reset Timer2
Start A to D Conversion
Figure 9·1. HSO Command Register

directional pins which are multiplexed with HSI.2 and
HSI.3 respectively. Bits 4 and 6 of 110 Control Register 1 (IOC1.4, IOC1.6) enable HSO.4 and HSO.5 as
outputs. The Control Registers can be read in Window
15 to determine the programmed modes for the HSO.
However, the IOC2.7(CAM CLEAR) bit is not latched
and will read as a one. Entries can be locked in the
CAM to generate periodic events or waveforms.

9.1 HSO Interrupts and Software
Timers
The IISO unit can generate two types of interrupts. The
High Speed Output execution interrupt can be generated (if enabled) for HSO commands which change one
or more of the six output pins. The other HSO interrupt is the interrupt which can be generated by any
other HSO command, (e.g. triggering the A/D, resetting Timer2 or generating a software time delay).

IOS2:

START
T2
HSO.5
AID RESET

17H
read

HSO Interrupt Status

Register IOS2 at location 17H displays the HSO events
which have occurred. IOS2 is shown in Figure 9-2. The
events displayed are HSO.O through HSO.5, Timer2
Reset and start of an A/D conversion. IOS2 is cleared
when accessed, therefore, the register should be saved
in an image register if more than one bit is being tested.
The status register is useful in determining which
events have caused an HSO generated interrupt. Writing to this regIster in Window 15 will set the status bits
but not cause interrupts. In Window 15, writing to
IOS2 can set the High Speed Output lines to an initial
value. Refer to Section 2.2 for more information on
Window 15.

HSO.4

HSO.3

HSO.2

HSO.1

HSO.O

Indicates which HSO event occcured
START A/D: HSO_CMD 15, start A/D
T2RESET:
HSO_CMD 14, Timer2 Reset
HSO.0-5:
Output pins HSO.O through HSO.5
Figure 9·2.

I/O Status Register 2

4-44

80C196KB USER'S GUIDE

SOFTWARE TIMERS

9.2 HSOCAM

The HSO can be programmed to generate interrupts at
preset times. Up to four such "Software Timers" can be
in operation at a time. As each preprogrammed time is
reached, the HSO unit sets a Software Timer Flag. If
the interrupt bit in the HSO command register was set
then a Software Timer Interrupt will also be generated.
The interrupt service routine can then examine I/O
Status register 1 (IOS1) to determine which software
timer expired and caused the interrupt. When the HSO
resets Timer2 or starts an A/D conversion, it can also
be programmed to generate a software timer interrupt.

A block diagram of the HSO unit is shown in Figure 93. The Content Addressable Memory (CAM) file is the
center of control. One CAM register is compared with
the timer values every state time, taking 8 state times to
compare all CAM registers with the timers. This defines the time resolution of the HSO to be 8 state times
(1.33 microseconds at an oscillator frequency of 12
MHz).
Each CAM register is 24 bits wide. Sixteen bits specify
the time at which the action is to be carried out, one bit
for the lock bit and 7 bits specify both the nature of the
action and whether Timer! or Timer2 is the reference.
The format of the command to the HSO unit is shown
in Figure 9-1. Note that bit 5 is ignored for command
channels 8 through OFH.

If more than one software timer interrupt occurs in the
same time frame, multiple status bits will be set. Each
read or test of any bit in 10SI (see Figure 9-5) will clear
bits 0 through 5. Be certain to save the byte before
testing it unless you are only concerned with I bit. See
also Section 11.5.

To enter a command into the CAM file, write the 8-bit
"Command Tag" into location 0006H followed by the
time the action is to be carried out into word address
0004H. The typical code w~)Uld be:

LDB HSO_COMMAND,#what_to_do
ADD HSO_TIME,Timerl.#when_to_do_it
16-81T

16-81T

XTAL1/16
CONTROL
LOGIC

HIGH SPEED 'OUTPUT CONTROLS
6 PINS
.
4 SOFTWARE TIMERS
2 INTERRUPTS
INITIATE AID CONVERSION
RESET TIMER2

270651-24

Figure 9-3_ High Speed Output Unit

4-:45

80C196KB USER'S GUIDE

16H

a EXPIRED

HSO.O CURRENT STATE

SOFTWARE TIMER

HSO.l CURRENT STATE

SOFTWARE TIMER 1 EXPIRED

HSO.2 CURRENT STATE

SOFTWARE TIMER 2

HSO.3 CURRENT STATE

SOFTWARE TIMER 3 EXPIRED

HSO.4CURRENT STATE

TIMER 2 HAS OVERFLOW

HSO.5 CURRENT STATE

TIMER 1 HAS OVERFLOW

CAM

Q!l HOLDING REGISTER IS FULL

EXPI~ED

HSI FIFO IS FULL

HSO HOLDING REGISTER IS FULL

HSI HOLDING REGISTER DATA AVAILABLE

270651-25

270651-26

Figure 9·4. 1/0 Status Register 0

Figure 9·5.110 Status Register 1 (IOS1) ,

this register in Window 15. The format for 1/0 Status
Register 0 is shown in Figure 9-4.
The expiration of software timer 0 through 4, and the
overflow of Timerl and Timer2 are indicated in 10S1.
The status bits can be set in Window 15 but not cause
interrupts .. The register is shown in Figure 9-5.

Commands in the holding register will not execute even
if their time tag is reached. Commands must be in the
CAM to execute. Commands in the holding register
can also be overwritten. Since it can take up to 8 state
times for a command to move from the holding register
to the CAM, 8 states must be allowed between succes·
sive writes to the CAM.

Whenever the processor reads this register all of the
time-related flags (bits 5 through 0) are cleared. This
applies not only to explicit reads such as:

LDB
To provide proper synchronization, the minimum time
that should be loaded to Timerl is Timerl + 2. Smaller values may cause the Timer match to occur 65,636
counts later than expected. A similar restriction applies
if Timer2 is used.

but also to implicit reads such as:

JBS

Before writing to the HSO, it is desirable to ensure that
the Holding Register is empty. If it is not, writing to the
HSO will overwrite the value in the Holding Register.
I/O Status Register 0 (IOSO) bits 6 and 7 indicate the
status of the HSO unit. If IOSO.6 equals 0, the holding
register is empty and at least one CAM register is empty. If IOSO.7 equals 0, the holding register is empty.
The programmer should carefully decide which of these
two flags is the best to use for each application. This
register also shows the current status of the HSO.O
through HSO.5. The HSO pins can be set by writing to

IOSl,3,somewhere_else

which jumps to somewhere_else if bit 3 of lOS I is set.
In most cases this situation can best be handled by having a byte in the register file which maintains an image
of the register. Any time a hardware timer interrupt or
a HSO, software timer interrupt occurs the byte can be
updated:

Care must be taken when writing the command tag for
the HSO, because an interrupt can occur between writing the command tag and loading the time value. If the
interrupt service routine writes to the HSO, t,he command tag used in the interrupt routine will overwrite
the command tag from the main routine. One way of
avoiding this problem would be to disable interrupts
when writing to the HSO unit.

9.3 HSO Status

AL,IOSl

ORB

IOSl_image,IOSl

leaving lOS I_image containing all the flags that were
set before plus all the new flags that were read and
cleared from 10S1. Any other routine which needs to
sample the flags can safely check lOS I_image. Note
, that if these routines need to clear the flags that they
have acted Qn, then the modification of IOSI_image
must be done from inside a critical region.

9.4 Clearing the HSO and Locked
Entries
All 8 CAM locations of the HSO are compared before
any action is taken. This allows a pending external

4-46

inter

80C196KB USER'S GUIDE

event to be cancelled by simply writing the opposite
event to the CAM. However, onc.e an entry is placed in
the CAM, it cannot be removed until e.ither the specified timer matches the written value , a chip reset occurs or IOC2.7 is set. IOC2.7 is the CAM clear bit
which clears all entries in the CAM.

be carefully done. The user should ensure writing to
Timer! will not cause programmed HSO events to be
missed or occur in the wrong order. rhe same precaution applies' to Timer2.
The HSO'requires at least eight state times to compare
each entry in the CAM. Therefore, the fast increment
mode for Timer2 cannot be used as a reference for the
HSO if transitions occur faster then once every eight
state times.

Internal events cannot be cleared by writing an opposite event. This includes events on HSO channels 8
through F. The only method for clearing these events
are by a reset or setting IOC2.7.

Referencing events when Timer2 is being us~d as an
up/down counter could cause events to occur m opposite order or be missed entirely. Additionally, locked
entries could possibly occur several times if Timer2 is
oscillating around the time tag for an entry.

HSO LOCKED ENTRIES

The CAM Lock bit (HSO_Command.7) can be set to
keep commands in the CAM, otherwise the commands
will clear from the CAM as soon as they cause an
event. This feature allows for generation periodic events
based on Timer2 and must be enabled by setting
IOC2.6. To clear locked events from the CAM, the entire CAM can be cleared by writing a one to the CAM
clear bit IOC2. 7. A chip reset will also clear the CAM.

When using Timer2 as the HSO reference, caution
must be taken that Timer2 is not reset prior to the
highest value for a Timer2 match in. the C~M. If t?at
match is never reached, the event will remam pendmg
in the CAM until the part is reset or CAM is cleared.

Locked entries are useful in applications requiring periodic or repetitive events to occur. Timer2 used as an
HSO reference can generate periodic events with the
use of the HSO T2RST command. HSO events programmed with a HSO time less then the Timer2 reset
time will occur repeatedly as Timer2 resets. Recurrent
software tasks can be scheduled by locking software
timers commands into the High Speed Output Unit.
Continuous sampling of the A/D converter can be accompished by programming a locked HSO A/D co~
version command. One of the most useful features IS
the generation of multiple PWM's on the High Speed
Output lines. Locked entries provide the ability to program periodic events while minimizing the software
overhead. Section 9.6 describes the generation of four
PWMs using locked entries.

9.6 PWM Using the HSO
The HSO unit can generate PWM waveforms with very
little CPU overhead using Timer2 as a reference. A
PWM is generated by programming an HSO line to a
high and a T2RST to occur at the same time. An HSO
low time is programmed on the CAM to generate t~e
duty cycle of the PWM. A repetitive PWM waveform IS
generated by locking the commands into the CAM. Reprogramming of the duty cycle or PWM frequency can
be accomplished by generating a software interrupt and
reprogramming the HSO high, HSO low and T2RST
commands.
Multiple PWMs can be programmed using Timer2 as a
reference and locked CAM entries. Up to four PWM's
can be generated by locking a PWM(High) and
PWM(low) into the CAM for each HSO.O through
HSO.3. Timer2 is used as a reference and set to zero by
programming a T2RST command at the same time an
HSO command sets all the lines high. Two CAM entries program the four PWM (high) times by setting
HSO.O/HSO.! and HSO.2/HSO.3 high with the same
command. Four entries in the CAM set each of the
HSO lines low. One entry is used to reset Timer2. This
method uses a total of seven CAM entries with little or
no software overhead. The PWMs can change their
duty cycle by reprogramming the CAM with different
HSO levels.

Individual external events setting or clearing an HSO
pin can by cancelled by writing the opposite event to
the CAM. The HSO events do not occur until the timer
reference has changed state. An event programmed to
set and clear an HSO event at the same time will cancel
each other out. Locked entries can correspondingly be
cancelled using this method. However, the entries remain in the HSO CAM and can quickly fill up the
available eight locations. As an alternative, all entries in
the HSO CAM can be cleared by setting IOC2.7.

9.5 HSO Precautions

Changing the duty cycle for each PWM requires the
flushing of the CAM and reprogramming of all seven
entries in the CAM. The 80C196KB can flush the entire CAM by setting bit 7 in the IOC2 register (location
16H). Each HSO(high) and HSO(low) times should be

Timer! is incremented once every 8 state-times. When
it is being used as the reference timer for an HSO command, the comparator has a chance to look at all. 8
CAM registers before Tinier! changes its value. Wnting to Timer!, which is allowed in Window 15, should

4-47

inter

80C196KB USER'S GUIDE

reprogrammed in addition to the Timer2 reset com·
mand. This method provides for up to four PWM's
with no software overhead except when reprogramming
the duty cycle of any particular PWM. The code to
generate these PWMs is shown in Figure 9·6.

er changes every eight state times during Phase!. From
an external perspective the HSO pin should change just
prior to the falling edge of CLKOUT and be stable by
its rising edge. Information from the HSO, can be
latched on the CLKOUT rising edge. Internal events
also occur when the reference timer increments. '

9.7 HSO Output Timing
Changes in the HSO lines are synchronized to either
Timerl or Timer2. All of the external HSO lines due to
change at a certain value of a timer will change just
after the incrementing of the timer. Internally, the tim·

10.0 SERIAL PC>EtT
The serial port on the 80C196KB has one synchronous
and 3 asynchronous modes. The asynchronous modes

$include (reg196.inc)

**********************************************************

·,
·,,
·
;
;
·,
;
;
·,,
·

*
*
*
*
*
*
*
*
*
*

GENERATION OF FOUR PWM'S USING LOCKED ENTRIES

*
*
*
*
*
*
*
*
*
*
*
**********************************************************
Timer2 is used as a reference and is clocked
externally by T2CLK. The High Speed outputs are
used as PWMs by programming each individual
PWM(low) and PWM(High) time as a locked entry.
The period of the PWM is programmed by resetting
timer2 and setting all the HSO lines high at the
same time. The PWMs are reprogrammed by
clearing the HSO CAM and reloading new values
for the PWM period and duty cycle.

RSEG at 60h
pwmOtiml: dsw 1
pwmltiml: dsw 1
pwm2timl: dsw 1
pwm3timl: dsw 1
PWM_period: dsw 1
temp: dsw 1
cseg at 2080h
ld sp.#OdOh
Id PWM_period.#OfOOOh
ld pwmOtiml.#2000h
ld pwmltiml.#4000h
Id pwm2timl.#6000h
Id pwm3timl.#8000h
Idb ioc2.#40h
Idb iocO.#Oh
'call pwm_program
here:
sjmp here

initialize stack pointer
intialize pwm period
initialize pwm 0-3 duty cycle

Enable locked entries
Enable t2clk for timer2 clock,
source
program pwm's on CAM
loop forever

Figure 9·6. Generating Four PWMs Using Locked Entries

4·48

80C196KB USER'S GUIDE

pwm_program:
Idb ioc2,#OcOh
Idb hso_command,#Oceh
Id hso_time,PWM_period
nop
nop
nop'
nop
Idb hso_command,#Oe6h
Id hso_time,PWM_period
nop
nop
nop
nop
Idb hso_command,#Oe7h
Id hso_time,PWM_period
nop
nop
nop
nop
Idb hso_command,#OcOh
Id hso_time,pwmOtiml
nop
nop
nop
nop
Idb hso_cbmmand,#Oclh
Id hso_time,pwmltiml
nop
nop
nop
nop
Idb hso_command,#Oc2h
Id hso_time,pwm2timl
nop
nop
nop
nop
Idb hso_command,#Oc3h
Id hso_time,pwm3timl
ret
end

flush entire cam
program timer2 reset time
delay eight state times before
next load
HSO OIl high, locked, timer2 as
reference
set hso_high on t2rst

; HSO 2/3 high, locked, timer2
; as referenoe
;'set hso_high on t2rst

set HSO.O low. locked, timer2
as reference
HSO.O time low

set HSO.l low, locked, timer2
reference
HSO.l time low

set HSO.2 low, 10cked,timer2
as refe,rence
HSO.2 time low

set HSO.3 low, 10oked,timer2
as reference
HSO.3 time low

Figure 9·6. Generating Four PWMs Using Locked Entries (Continued)

4·49

80C196KBUSER'SGUIDE

are full duplex, meaning they can transmit and receive
at the same time. The receiv~r is double buffered so that
the reception of a second byte can begin before the first
byte has been read. The transmitter on the SOCI96KB
is also double buffered allowing continuous transmissions. The port is functionally compatible with the serial port on the MCS-51 family of microcontrollers, although the software controlling the ports is different.

reading it accesses SP_STAT. The upper 3 bits of
SP_CON must be written as Os for future compatibility. On the SOCI96KB the SP_STAT register contains
new bits to indicate receive Overrun Error (OE), Framing Error (FE), and Transmitter Empty (TXE). The
bits which were also present on the S096BH are the
Transmit Interrupt (TI) bit, the Receive Interrupt (RI)
bit, and the Received Bit. S (RBS) or Receive Parity
Error (RPE) bit. SP_STAT is read-only in Window 0
and is shown in Figure 10-1.

Data to and from the serial port is transferred th~ough
SBUF(RX) and SBUF(TX), both located at 07H.
SBUF(TX) holds data ready for transmission and
SBUF(RX) contains data received by the serial port.
SBUF(TX) and SBUF(RX) can be read and can be
written in Window 15.

In all modes, the RI flag is set after the last data bit is
sampled, approximately in the middle of a bit time.
Data is held in the receive shift register until the last
data bit is received, then the data byte is loaded into
SBUF (RX). The receiver on the SOCI96KB also
checks Jor a valid stop bit. If a stop bit is not found
within the appropriate time, the Framing Error (FE)
bit is set.

Mode 0, the synchronous shift register mode, is designed to expand I/O over a serial line. Mode I is the
standard S bit data asynchronous mode used for normal
serial communications. Modes 2 and 3 are 9 bit data
asynchronous modes typically used for interprocessor
communications. Mode 2 provides monitoring of a
communication line for a I in the 9th bit position before
causing an interrupt. Mode 3 causes interrupts independant of the 9th bit value.

Since the receiver is double-buffered, reception on a
second data byte can begin before the first byte is read.
However, if data in the shift register is loaded into
SBUF (RX) before the previous byte is read, the Overflow Error (OE) bit is set. Regardless, the data in SBUF
(RX) will always be the latest byte received; it will never be a combination of the two bytes. The RI, FE, and
OE flags are cleared when SP_STAT is read. However, RI does not have to be cleared for the serial port to
receive data.

10.1 Serial Port Status and Control
Control of the serial port is done through the Serial
Port Control (SP_CON) register shown in Figure 10J. Writing to location llH accesses SP....,.CON while

~-:--~-:--~-:--~T-:-8-+I-R-:-N-+-P-:-N-+--~-2-+--;-1~1 11H
TBS

Sets the ninth data bit for transmission. Cleared after each transmission. Not valid
if parity is enabled.

REN . - Enables the receiver
PEN
- Enables the Parity function (even ~arity)
M2, MI - Sets the mode. ModeO = 00, Model = 01, Mode2 = 10, Mode3 = 11

RB8
Rf'E
RI
TI
FE
TXE
OE

- Set
- Set
- Set
- Set
- Set
- Set
.:..-. Set

RBS/
RPE

TXE

if the 9th data bit is high on reception (parity disabled)
if parity is enabled and a parity error occurred
after the last data bit is sampled
at the beginning of'the STOP bit transmission
if no STOP bit is found at the end of a reception
if two bytes can be transmitted
if the receiver buffer is overwritten

Figure 10-1. Serial Port ContrOl and Status Registers

4·50

11H

inter

80C196KB USER'S GUIDE

The Transmitter Empty (TXE) bit is set if the transmit
buffer is empty and ready to take up to two characters.
TXE gets cleared as soon as a byte is written to SBUF.
Two bytes may be written consecutively to SBUF if
TXE is set. One byte may be written if TI alone is set.
By definition, if TXE has just been set, a transmission
has completed and TI will be set. The TI bit is reset
when the CPU reads the SP_STAT registers.

BAUD RATES

Baud rates are generated based on either the T2CLK
pin or XT AL 1 pin. The values used are different than
those used for the S096BH because the 80C196KB uses
a divide-by-2 clock instead of a divide-by-3 clock to
generate the internal timings. Baud rates are calculated
using the following formulas where BAUD_REG is
the value loaded into the baud rate register:

The TBS bit is cleared after each transmission and both
TI and RI are cleared when SP_STAT reacj. The RI
and TI status bits can be set by writing to SP_STAT in
window 15 but they will not cause an interrupt. Reading of SP_CON in Window 15 will read the last value
written. Whenever the TXD pin is used for the serial
port it must be enabled by setting IOp.5 to a 1. I/O
control register 1 can be read in window 15 to determine the setting.

Asynchronous Modes 1, 2 and 3:
BAUD_REG =

XTAL1

-lOR

Baud Rate * 16

T2CLK

Baud Rate' 8

Synchronous Mode 0:
BAUD_REG = B XT;L 1,

aud ate' 2

- 1 OR

T2CLK

Baud Rate

STARTING TRANSMISSIONS AND RECEPTIONS

The most significant bit in the baud register value is set
to a one to select XT AL 1 as the source. If it is a zero
the T2CLK pin becomes the source. The following table shows some typical baud rate values.

In Mode 0, if REN = 0, writing to SBUF (TX) will
start a transmission. Causing a rising edge on REN, or
clearing RI with REN = 1, will start a reception. Setting REN = 0 will stop a reception in progress and
inhibit further receptions. To avoid a partial or complete undesired reception, REN must be set to zero before RI is cleared. This can be handled in an interrupt
environment by using software flags or in straight-line
code by using the Interrupt Pending register to signal
the completion of a reception.

BAUD RATES AND BAUD REGISTER VALUES
Baud
Rate

In the asynchronous modes, writing to SBUF (TX)
starts a transmission. A falling edge on RXD will begin
a reception if REN is set to 1. New data placed in ,
SBUF (TX) is held and will not be transmitted until the
end of the stop bit has been sent.

XTAL 1 Frequency
8.0 MHz

10.0 MHz

12.0 MHz

300 1666/ -0.02 2082/0.02 2499/0.00
1200 416/ -0.08 520/-0.03 624/0.00
2400
207/0.16
259/0.16 312/-0.16
4800
103/0.16
129/0.16
155/0.16
51 /0.16
64/0.16
9600
77 / 0.16
19.2K
25/0.16
32/1.40
38/0.16
Baud Register Value I % Error

In all modes, the RI flag is set after the last data bit is
sampled approximately in the middle of the bit time.
Also fdr all modes, the TI flag is set after the last data
bit (either 8th or 9th) is sent, also in the middle of the
bit time. The flags clear when SP_STAT is read, but
do not have to be clear for the port to receive or transmit. The serial port mterrupt bit is set as a logical OR
of the RI and TI bits. Note that changing modes will
reset the Serial Port and abort any transmission or reception in progress on the channel.
'

A maximum baud rate of 750 Kbaud is available in the
asynchronous modes with 12 MHz on XTAL). The
synchronous mode has a maximum rate of 3.0 Mbaud
with a 12 MHz clock. Location OEH is the Baud Register. It is loaded sequentially in two bytes, with the low
byte being loaded first. This register may not be loaded
with zero in serial port Mode O.

4-51

inter

80C196KBUSER'S GUIDE

mode the TXD pin outputs a set of 8 pulses while the

10.2 Serial Port Interrupts

RXP pin either transmits or .receivesdata. Data is
transferred 8 bits at a time with the LSB first. A diagram··of the relative timing.of these signals is shown in
Figure 10-2. Note that this is the only. mode which uses
RXD as an output.

TlJe. serial port generates one of three possible interrupts: Transmit Interrupt TI(2030H), Receive Interrupt RI(2032H) and SERIAL(200CH). When the RI
bit gets set an interrupt is generated through either
200CH or 2032H depending on which interrupt is enabled. INT_MASK 1.1 controls the serial port receive
interrupt through location 2032H and INT_MASK.6
controls serial port interrupts through location 200CH.
The 8096BH shared the TI and RI interrupts on the
SERIAL interrupt vector. On the 80C196KB, these interrupts share both the serial interrupt vector and have
their own interrupt vectors.

Mode 0 Timings

In Mode 0, the TXD pin sends but a clock train, while
the RXD pin transmits or receives the data. Figure 102 shows the waveforms and timing.
In this mode the serial port expands the I/O capability
of the 80C196KB by simply adding shift registers. A
schematic of a typical circuit is shown in Figure 10-3.
This circuit inverts the data coming in, so it must be
reinverted in software.

When the TI bit is set it can cause an interrupt through
the vectors at locations 200CH or 2030. Interrupt
through location 2030 is determined by INT_
MASK 1.0. Interrupts through the serial interrupt is
controlled by the same bit as the RI interrupt(INT_
MASK.6). The user should not mask off the serial port
interrupt when using the double-buffered feature of the
transmitter, .as it could cause a missed count in the
number of bytes being transmitted.

MODE 1

Mode 1 is the standard asynchronous communications
mode. The data frame used in this mode is shown in
Figure 10-4. It consists of 10 bits; a start bit (0), 8 data
bits (LSB first), and a stop bit (l). If parity is enabled
by setting SPCON.2, an even parity bit is sent instead
of the 8th data bit and parity is checked on reception.

10.3 Serial Port Modes
MODE 0

Mode 0 is a synchronous mode which is commonly
used for shift register based I/O expansion. In this

RXD(OUT) -,..(

D4'

D6
D6

t--

RXD(IN)
EXPANDED:

__......:D:.;1~

x::

RXO(OUT)

----{=JDO~==x::rl-:

RXO(IN)

~r-1---IDI--....,f:rr-:--

___

01
270651-28

Figure 10-2. Mode 0 Timing

4-52

inter

80C196KB USER'S GUIDE

CLOCK 1NHI8IT

..-------=-----4 PX.X
DATA

~_""'-"""-----4 RXD
CLOCK
1.----+----.....-..;...--1
TXD

INPUTS

.80C196KB

OUTPUTS
SERIAL IN A

ENABLE

a>-----I PX.X
270651-29

Figure 10-3. Typical Shift Register Circuit

·.STOP

270651-30

STOP
PROGRAMMABLE 9TH BIT - - _....
It·BIT FRAME
270651-31

Figure 10-4. Serial Port Frames, Mode 1,2, and 3

port will holt! off transmission until the stop bit is complete. RI is set when 8 data bits are received, not when
the stop bit is received. Note that when the serial port
status register is read both TI and RI are cleared.

The transmit and receive functions are controlled by
separate shift clocks. The transmit shift clock starts
when the baud rate generator is initialized, the receive
shift clock is reset when a 'I to 0' transition (start bit) is
received. The transmit clock may therefore not be in
sync with the receive clock, although they will both be
at the same frequency.

Caution should be. used when using the serial port to
connect more than two devices in half-duplex, (i.e. one
wire for transmit and receive). If the receiving processor does not wait for one bit time after RI is set before
starting to transmit, the stop bit on the link could be
corrupted. This could cause a problem for other devices
.
listening on the link.

The TI (Transmit Interrupt) and RI (Receive Inter·
rupt) flags are set to indicate when operations are' com·
plete. TI,is set when the last data bit of the message has
been sent, not when the stop bit is sent. If an attempt to
send another byte is made before the stop bit is sent the

4·53

inter

80C196KB USER'S GUIDE

MODE 2

Mode 2 is the asynchronous 9th bit recognition mode.
This mode is commonly used with Mode 3 for multiprocessor communications. Figure 10-4 shows the data
frame used in this mode. It consists of a start bit (0), 9
data bits (LSB first), and a stop bit (I). When transmitting, the 9th bit can be set to a one by setting the TB8
bit in the control register before writing to SBUF (TX).
The TB8 bit is cleared on every transmission, so it must
be set prior to writing to SBUF (TX). During reception, the serial port interrupt and the Receive Interrupt
will not occur unless the 9th bit being received is set.
This provides an easy way to have selective reception
on a data link. Parity cannot be enabled in this Il'\ode.

bit is set. Two types of frames are used: address frames
which have the 9th bit set and data frames which have
the 9th bit cleared. When the master processor wants to
transmit a block of data to one of several slaves, it first
sends out an address frame which identifies the target
slave. Slaves in Mode 2 will not be interrupted by a data
frame, but an address frame will interrupt all slaves.
Each slave can examine, the received byte and see if it is
being addressed. The addressed slave switches to Mode
3 to receive the coming data frames, while the slaves
that were not addressed stay in Mode 2 continue executing.

11;0 AID CONVERTER
Analog Inputs to the 80CI96KB System are handled
by the AID converter System. As shown in Figure
11-4, the converter system has an 8 channel multiplexer, a sample-and-hold, and a 10 bit successive approximation AID converter. Conversions can be performed
on one of eight channels, the inputs of which share pins
with port O. A conversion can be done in as little as 91
state t.irites.

MODE 3

Mode 3 is the asynchronous 9th bit mode. The data
frame for this mode is identical to that of Mode 2. The
transmission differences between Mode 3 and Mode 2
are that parity can be enabled (PEN = I) and cause the
9th data bit to take the even parity value. The TB8 bit
can still be used if parity is not enabled (PEN = 0).
When in Mode 3, a reception always causes an interrupt, regardless of the state of the 9th bit. The 9th bit is
stored if PEN = 0 and can be read in bit RB8. If
PEN = I then RBS becomes the Receive Parity Error
(RPE) flag.

Conversions are started by loading the AD_COMMAND register at location 02H with the channel number. The conversion can be started immediately by setting the GO bit to a one. If it is cleared the conversion
will start when the HSO unit triggers it. The AID command register must be written to for each conversion,
even if the HSO is used as the trigger. The result of
the conversion is read in the AD_RESULT(High)
and AD_RESULT(Low) registers. The AD_RESULT(High) contains the most significant eight bits of
the conversion. The AD_RESULT(Low) register contains the remaining two bits and the AID channel number and AID status. The format for the AD_COMMAND register is shown in Figure 11-1. In Window
15, reading the AD_COMMAND register will read
the last command written. Writing to the AD_RESULT register will write a value into the result register.

Mode 2 and 3 Timings

Modes 2 and 3 operate in a manner similar to that of
Mode 1. The only difference is that 'the data is now
made up of 9 bits, so II-bit packages are transmitted
and received. This means that 1'1 and RI,will be set on
the 9th data bit rather than the 8th. T.he 9th bit' can be
used for parity or multiple processor communications.

10.4 Multiprocessor Communications
Mode 2 and 3 are provided for multiprocessor communications. In Mode 2 if the received 9th data bit is zero,
the RI bit is not set and will not cause an interrupt. In
Mode 3, the RI bit is set and always causes an interrupt
regardless of the value in the 9th bit. The way to use
this feature in multiprocessor systems is described below.

02H

ml
1

The master processor is set to Mode 3 so it always gets
interrupts from serial receptions. The slaves are set in
Mode 2 so they only have receive interrupts if the 9th

CHANNEL # SELE,CTS WHICH OF THE 8 .
ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL FORM.
'
GO INDICATES WHEN THE CONVERSION IS TO
BE INITIATED (GO = 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).
270651-33

Figure 11·1. AID Command Register

4~54

inter

80C196KB USER'S GUIDE

The AID converter can cause an interrupt through the
vector at location 2002H when 'it completes a conversion. It is also possible to use a polling method by
checking the Status (S) bit in the lower byte of the
AD_RESULT register, also at location 02H. The
status bit will be a 1 while a conversion is in progress. It
takes 8 state times to set this bit after a conversion is

started. The upper byte of the result register contains
the most significant 8 bits of the conversion. The lower
b~te format is shown in Figure 11-2.
At high crystal frequencies, more time is needed to allow the comparator to settle. For this reason IOC2.4 is
provided to adjust the speed of the AID conversion by
disablinglenabling a clock prescaler.
A summary of the conversion time for the two options
is shown below. The numbers represent the number of
state times required for conversion, e.g., 91 states is
22.7 /ks with, an 8 MHz XTALl (providing a 250 ns
state time.)

A/D CHANNEL NUMBER
STATUS:
0= A/D CURRENTLY IDLE
1 CONVERSION IN PROCESS
X

}

A/D RESULT:
LEAST SIGN I,ICANT 2 BITS

Clock Prescaler On
IOC2.4 = 0

Clock Prescaler Off
IOC2.4 = 1

158 States
26.33 /ks @ 12 MHz

91 States
22.75 /ks @ 8 MHz.

Figure 11-3. AID Conversion Times
270651-32

Figure 11-2. AID Result Lo Register

'vREF

8 TO 1
ANALOG
MULTIPLEXER

SAMPLE
AND
HOLD

CHANNEL

START
CONVE~SION

HSO COMMAND "F"

Figure 11-4. AID

Conve~ter

4-55

Block Diagram

270651-34

; :,

80C196KB USER'S GUIDE

11.1 AID Conversion Process
The conversion process is initiated by the execution of
HSO command OFH, or by writing a one to the GO Bit
in'the AID Control Register. Either activity causes a
start conversion signal to be sent to the 'AID converter
control logic. If an HSO Command was used, the conversion process will begin when Timer! 'increments.
This aids applications attempting to approach spectrally pure -sampling, since successive samples spaced by
equal Timerl' delays will occur with a variance of about
±50 ns (assuming a stable clock on XTALI). However, conversions initiated by writing a one to the ADCON register GO Bit will start within three state times
after the instruction has completed, execution resulting
in a variance of about 0.50 p.s (XTALI = 12 MHz).
Once the A/D unit receives a start conversion signal,
there is a one state time delay before sampling (Sample
Delay) while the successive approximation register is
reset and tlte proper multiplexer channel is selected.
After the sample delay, the mUltiplexer output is connected to the sample capacitor and remains connected
for 8 state times in fast mode or 15 state times for slow
mode (Sample Time). After this 8/15 state time "sample window" closes, the input to the sample capacitor is
disconnected from the multiplexer so that changes on
the input pin will not alter the stored charge while the
conversion is in progress. The comparator is then autozeroed and the conversion begins. The sample delay
and sample time uncertainties are each approximately
± 50 ns, independent of clock speed.

\,' :

The total number of state times required for a 'conversion is determil'led,by the setting of IOC2.4' clock prescaler bit. With the bit set the conversion time is 91
states and 158 states when'the bit is cleared.

11.2 AID Interface Suggestions
(

The external interface circuitry to an analog input is
highly dependent upon the application, and can impact
converter characteristics. In the external circuit's design, important factors such as input pin leakage, sample capacitor size and multiplexer series resistance from
the input pin to the sample capacitor must bel considered.
For the 80C196KB, these factors are idealized in Figure 11-5. The external input circuit mllst be able to
charge a sample capacitor (Cs) t.hrough a ,series resistance (RI) to an accurate voltage -given a D.C. leakage
(IL)' On the 80C196KB; Cs is around 2 pF, RI is
around 5 Kn. and IL is specmed as 3 p.A maximum. In
determining the necessary source impedance Rs, the
value of VBIAS is not ,important.

~~
VB1A!i.

To perform the actual analog-to-digital conversion the
80CI96KB implements a successive approximation algorithm. The converter hardware consists of a 256-resistor ladder, a comparator, coupling capacitors and a
lO-bit successive approximation register (SAR) with
logic that guides the process. The resistor ladder provides 20 mV steps (VREF = 5.12V), while capacitive
coupling creates 5 m V steps within the 20 m V ladder
voltages. Therefore, 1024 internal reference voltages are
available for comparison' against the analog input to
generate a lO-bit conversion result.
A successive approximation conv~i!>n is performed by
comparing a sequence of reference voltages, to the analog input, in a binary search for the reference 'Voltage
that most clo.sely matches the input. The 'I. full scale
reference voltage is the rtrst tested. This corresponds to
a 1O.bit 'result where the most signmcant bit is zero,
and all other bits are one~ (Oll1.l1ll.11b). If the analog input was'less than the test voltage, bit 10 of the
SAR is left it zero, and a new test v..:--4--"VI.f'v-...
~
INPUT PIN
02

ANGNO
270651-36

Figure 11-6. Suggested AID Input Circuit
ANALOG REFERENCES

11.3 The AID Transfer Function
The conversion result is a to-bit ratiometric representation of the input voltage, so the numerical value obtained from the conversion will be:
INT [1023

(VIN - ANGND)/(VREF - ANGND)l.

This produces a stair-stepped transfer function when
the output code is plotted versus input voltage (see Figure 11-7). The resulting digital codes can be taken as '
simple ratiometric information, or they provide infor, mation about absolute voltages or relative voltage
changes on the inputs, The more demanding the application is on the AID converter, the more important it
is to fully understand the converter's operation, For
simple applications, kpowing the absolute error of the
converter is sufficient. However, closing a servo-loop
with' analog inputs necessitates a detailed understanding of an AID converter's operation apd errors.
The errors' inherent in an analog-to-digital conversion
process are many: quantizing error, zero offset, fullscale error, differential non-linearity, and non-linearity.
These are "transfer function" errors related to the AID
converter. In addit\on, converter temperature drift,
Vee rejection, sample-hold feedthrough, multiplexer
off-isolation, channel-to-channel matching and random
noise should be considered. Fqrtunately, one "Absolute
Error" specification is available which describes the
sum total of all deviations between the actual conversion process and an ideal converter, However, the vari'ous sub-components of error are important in many
applications. These error components are described in
Section I1.'S and in the text below where ideal and actual converters are compared.

Reference supply levels strongly influence the absolute
accuracy of the conversion. For this reason, it is recommended,that the ANGND pin be tied to the two Vss
pillS at the power supply. Bypass capacitors should also
be used betwe~n "REF and ANGND. ANGND should
be within about a tenth of a volt of Vss. VREF should
be well regulated and used only for the AID converter.
The VREF supply can be between 4.SV and 5.SV and
needs .to be able to source around SmA. See Section 13
for the minimum hardware connections.

An unavoidable error simply results from the conversion of a continuous voltage to an integer digital representation. This error is called quantizing error, and is
always ±O.S LSB. Quantizing error is the only error
seen in a perfect A/D,converter. and is obviously present in actual converters. Figure 11-7 shows the transfer
function for an ideal 3-bit AID converter (i.e. the Ideal
Characteristic).
.
Note that in Figure H-7 the Ideal Characteristic possesses unique qualities: it's first code transition occurs
when the input voltage is O.S LSB; it's full-scale code
transition occurs when the input voltage equals the full-

Note that if only ratiometric information is desired,
VREF can be connected to Vee. In addition, VREF and

4-57

(

7
FINAL CODE TRANSITION OCCURS
WHEN THE APPLIED VOLTAGE IS
EQUAL TO (Vref - 1 (/2 (LSB».

•

5
."

ci
r::

CD
0

....

~
oj>.

0:
CD
!!!.

....0

;:J!:

THE VOLTAGE CHANGE
BETWEEN ADJACENT CODE
TRANSITIONS (THE "CODE
WIDTH") IS
1 LSB •

(J)

:lJ

ene;)

:::r

1»I»

()

6
m

::l.
til
:::!:

()

H
.

FIRST CODE TRANSITION OCCURSJ
WHEN THE APPLIED VOLTAGE IS
- EQUAL TO 1/2 LSB.
------------------

O~--J---_r------_,--------,_------_r--------r_------_.--~--_,--------,

1/2

INPUT VOLTAGE (LSBs)

61/2

270651-37

--1

IDEAL
CHARACTERISTIC

'TI

FULL SCALE ERROR

ABSOLUTE ERROR

c"
c:

ACTUAL
CHARACTERISTIC

....
•
90

01)

o....

i:
!!!.

"c:
OJ

I»
:::I
0-

ii
CD
!!!.

en
C)

:::r

II)

g
In

--+
o

1/2

ZERO OFFSET

61/2

INPUT VOLTAGE (LSBs)

270651-38

. IDEAL FULL-SCALE CODE
TRANSITION

ACTUAL
FULL-SCALE CODE
TRANSITION

----

5-1

:!!
c

.....

TERMINAL BASED
CHARACTERISTIC

...{It

~
...
3
S'

~
!!.
cD UI
0

(II

ACTUAL
CHARACTERISTIC

c»

"c
UI

fI)

1ft

:If

rij

....

Ii)

NON-LINEARITY

....

C)'

1ft
2

:::!.

IDEAL CODE WIDTH

IDEAL FIRST TRANSITION

OK
1/2

INPUT VOLTAGE (LSBs)

61/2

·8

270651-39

80C196KB USER'S GUIDE

scale 'reference minus L5 LSB; and it's code widths are
all exactly one LSR Th~se' qualities result in a digitization without offset, full-scale or linearity errors, In other words, a perfect conversion.

Undesired signals come from three main sources, First,
noise on V cc-Vcc Rejection, Second, input signal
changes on the channel being converted after the sample window has closed-Feed through, Third, signals
applied to' channels not selected by the multiplexerOff-Isolation.

Figure 11-8 shows an Actual Characteristic of a hypothetical 3-bit converter, which is not perfect, When the
Ideal Characteristic is overlaid with the imperfect characteristic, the actual converter is seen to exhibit errors
in the location of the first and final code transitions and
cod~ widths, The deviation of the first code transition
from ideal is called "zero offset", and the deviation of
the final code transition from ideal is "full-scale error".
The deviation of the code widths from ideal causes two
types of errors. Differential Non-Linearity and NonLinearity. Differential Non-Linearity is a local linearity
error measurement, whereas Non-Linearity is an overall linearity error measure,

Finally, multiplexer on-channel resistances differ slightly from one channel to the next causing Channel-toChannel Matching errors, and random noise in general
results in Repeatability errors,

1'1.4 AID Glossary of Terms
Figures 11-7, 11-8, and 11-9 display many of these
terms, Refer to AP-406 'MCS-96 Analog Acquisition
Primer' for additional information on the AID terms.

Differential Non-Linearity is the degree to which actual
code widths differ from the ideal one LSB width, It
gives the user a measure of how' much the input voltage
may have changed in order to produce a one count
change in the conversion result, Non-Linearity is the
worst case deviation of code transitions from the corresponding code transitions of the Ideal Characteristic,
Non-Linearity describes how much Differential NonLinearities could add up to produce an overall maximum departure from a linear eharacteristic. If the Differential Non-Linearity errors are too large, it is possible for an AID converter to miss codes or exhibit nonmonotonicity, Neither behavior is desirable in a closedloop system, A converter has no missed codes if there
exists for each output code a unique input voltage range
that produces that code only. A converter is monotonic
if every subsequent code change represents an input
voltage change in the same direction, '

ABSOLUTE ERROR-The maximum difference between corresponding actual and ideal code transitions,
Absolute Error accounts for all deviations of an actual
converter from an ideal converter,

Differential Non-Linearity and Non-Linearity are
quantified by measuring the Terminal Based Linearity
Errors, A Terminal Based Characteristic results when
an Actual Characteristic is shifted and rotated to eliminate zero offset and full-scale error (see Figure 11-9),
The Tenninal Based Characteristic is similar to the Actual Characteristic that would be seen if zero offset and
full-scale error were externally trimmed away, In practice, this is done by using input circuits which include
gain and offset trimming, In addition, VREF on the
80C 196KB could also be closely regulated and trimmed
within the specified range to affect full-scale error,

CHANNEL-TO-CHANNEL MATCHING-The difference between corresponding code transitions of actual characteristics taken from different channels under
the same temperature, voltage and frequency conditions.

ACTUAL CHARACTERISTIC-The characteristic of
an actual converter. The characteristic of a given converter may vary over temperature, supply voltage, and
frequency conditions, An Actual Characteristic rarely
has ideal first and last transition locations or ideal code
widths, It may even vary over multiple conversion under the same conditions,
BREAK-BEFORE-MAKE-The property of a multiplexer which guarantees' that a previously selected
channel will be deselected befdre a new channel is selected. (e,g, the converter will not short inputs
together,)

CHARACTERISTIC-A graph of input voltage versus the resultant output code for an AID converter. It
describes the transfer function of the AID converter,
CODE-The digital value output by the converter,
CODE CENTER-The voltage corresponding to the
midpoint between two adjacent code transitions.

Other factors that affect a real AID Converter system
include sensitivity to temperature, failure to completely
reject all unwanted signals, mUltiplexer channel dissimilarities and random noise, Fortunately these effects are
small.

CODE TRANSITION-The point at which the converter changes from an output code of Q, to a code of
Q + L The input voltage corresponding to a code transition is defined to be that voltage which is equally likely to produce either of two adjacent codes,
'

Temperature sensitivities are described by the rate at
which typiCal specifications change with a change in
temperature.

CODE WIDTH-The voltage corresponding to the
difference between two adjacent code transitions,
4-61

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80C196KB USER'S'GUIDE

CROSSTALK-See "Off-Isolation".

REPEATABILITY-The difference between corresponding code transitions from different actual charac.
teristics taken from the same converter on the same
channel at the same temperature, voltage and frequency
conditions.

D.C. INPUT LEAKAG&-Leakage current to ground
from an analog input pin.
DIFFERENTIAL NON-LINEARITY-The difference between the ideal and actual code widths of the
terminal based characteristic of a converter.

RESOLUTION-The number of input voltage levels
that the converter can unambiguously distinguish between. Also defines the number of useful bits of information which the converter can return.

FEEDTHROUGH-Attenuation of a voltage a'pplied
on the selected channel of the AID converter after the
sample window closes,

SAMPLE DELAY-The delay from rect;iving the start
conversion signal to when the sample window opens.

FULL SCALE ERROR-The difference between the
expected and actual input voltage corresponding to the
full scale code transition.

SAMPLE DELAY UNCERTAINTY-The variation
in the Sample Delay,

IDEAL CHARACTERISTIC-A characteristic with
its first code transition at VIN = 0.5 LSB, its last code
(VREF
1.5 LSB) and all code
transition at VIN
widths equal to one LSB.

SAMPLE TIME-The time that the sample window is
open.

INPUT RESISTANCE-The effective series resistance
from the analog input pin to the sample capacitor.
LSB-LEAST SIGNIFICANT BIT: The voltage value
corresponding to the full scale voltage divided by 2n ,
where n is the number of bits of resolution of the converter. For a lO-bit converter with a reference voltage
of 5.12 volts, one LSB is 5.0 mY. Note that this is
different than digital LSBs, since an uncertainty of two
LSBs, when referring to an AID converter, equals
10 mY. (This has been confused with an uncertainty of
two digital bits, which would mean four counts, or
20 mV.)
.

SAMPLE TIME UNCERTAINTY-The variation in
the sample time.
SAMPLE WINDOW-Begins when the sample capac-itor is attached to a selected channel and ends when the
sample capacitor is disconnected from the selected
channel.
SUCCESSIVE APPROXIMATION-An AID conversion methOd which uses a binary search to arrive at
the best digital representation of an analog input.
TEMPERATURE COEFFICIENTS-Change in the
stated variable per degree centigrade temperature
change. Temperature coefficients are added to the typical values of a specification to see the effect of temperature drift.

MONOTONIC-The property of successive approximation converters which guarantees that increasing input voltages produce adjacent codes of increasing value,
and that decreasing input voltages produce adjacent
codes of decreasing value.

TERMINAL BASED CHARACTERISTIC-An Actual Characteristic which has been rotated and translated to remove zero offset and full-scale error.

NO MISSED CODES-For each and every output
code, there exists a unique input voltage range which
produces that code only. ,

Vee REJECTION-Attenuation of noise on the Vee
line to the AID converter.
.
ZERO OFFSET-The difference between the expected
and actual input voltage corresponding to the first code
transition.

NON-LINEARITY-The maximum deviation of code
transitions of the terminal based characteristic from the
corresponding code transitions of the ideal characteristics.
OFF-ISOLATION-Attenuation of a voltage applied
on a deselected channel of the AID converter. (Also
referred to as Crosstalk.)

4-62

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80C196KB USER'S GUIDE

In addition to acting as a digital input, each line of Port

12.0 1/0 PORTS

o can be selected to be the input of the A/D converter
as .discussed in Section 11. The capacitance on these
pins is approximately 1 pF and will instantaneously increase by around 2 pF when the pin is being sampled by
the A/D converter.

There are five 8-bit I/O ports on the 80C196KB. Some
of these ports, are input only, some are output only,
some are bidirectional and some have alternate functions. in addition to these ports, the HSI/O unit provides extra I/O lines if the timer related features of
these lines are not needed.

Port 0 pins are special in that they may individually be
used as digital inputs and analog inputs at the same
time. A Port 0 pin being used as a digital input acts as
the high impedance input ports just described. However, Port 0 pins being used as analog inputs are 'required
to provide current to the internal sample capacitor
when a conversion begins. This means that the input
characteristics of .a pin will change if a conversion is
being done on that pin. In either case, if Port 0 is to be
used as analog or digital I/O, it will be necessary to
provide power to this port through the VREF pin and
ANGNDpins.

Port 0 is an input port which is also used as the analog
input for the A/D converter. Port 0 is read at location
OEH. Port 1 is a quasi-bidirectional port and is read or
written to through location OFH. The three most significant bits of Port 1 are the control signals for .'the
HOLD/HLDA bus port pins. Polt 2 contains three
types of port lines: quasi-bidirectional, input and output. Port2 is read or written from location IOH. The
ports cannot be read or written in Window 15. The
input and output lines are shared with other functions
in the 80C196KB as shown in Figure 12-1. Ports 3 and
4 are open-drain bidirectional ports which share their
pins with the address/data bus. On EPROM and ROM
parts, Port 3 and 4 are read and written through location IFFEH.
ALTERNATE
FUNCTION

PIN FUNC.

Port 0 is only sampled when the SFR is read to reduce
the noise in the A/D converter. The data must be stable
one state time before the SFR is read.

CONTROL
REG.

2.0

Output TXO (Serial Port Transmit)

IOC1.S

2.1

Input

RXO (Serial Port Receive)

SPCON.3

P2.2 Input

EXTINT

IOC1.1

2.3.

Input

T2CLK (Timer2 Clock & Saud) lOCO.?

2.4

Input

T2RST (Timer2 Reset)

2.5

Output PWM Output

IOC1.0

2.6

OBO' Timer2 up/down select

IOC2.1

2.?

OBb' Timer2 Capture

N/A

IOCO.S

BUS

'OBO = Quasi-bidirectional,

Figure 12-1. Port 2 Multiple Functions

SAMPLE
270651-76

While discussing the characteristics of the I/O pins
some approximate current or voltage specifications will
be given. The exact specifications are available in the
latest version of the data sheet that corresponds to the
part being used.

NOTE:
'01 and 02 are ESO Protection Devices

Figure 12·2. Input Port Structure

12.1 Input Ports

12.2 Quasi·Bidirectional Ports

Input ports and pins can only be read. There are' no
output drivers on these pins. The input leakage of these
pins is in the microamp range. The specific values 'can
be found in the data sheet for the deyice being considered. Figure 12-2 shows the input port structure.

Port 1 and Port 2 have quasi-bidirectional I/O pins.
When used as inputs the data on these pins must be
stable one state time prior to reading the SFR. This
timing is also valid for the input-only pins of Port 2 and
is similar to the HSI in that the sample occurs during
,PHI or during CLKOUT low. When used as outputs,
the quasi-bidirectional pins will change state shortly after CLKOUT falls. If the change waS'from '0' to a 'I'

The high impedance input pins on the 80Cl96KB have
an input leakage of a few microamps and are pre\fominantly capacitive loads on the order of 10 pF.
4-63

80C196KB USER'S GUIDE

Vee

FROMPORTc;>-~----------------'-----~-1t-~~

LATCH

INPUT
.....::r--~X
DATA~
READ

PORT PIN u--~
270651-40
CHMOS Configuration. pFET 1 is turned on for 2 ose. periods after Q makes a O-to-1 transition. During this time, pFET 1
also turns on pFET 3 through the inverter to form a lateh which holds the 1. pFET 2 is also on.

Figure 12-3. CHMOS Quasi-Bidirectional Port Circuit

the low impedance pullup will remain on for one state
time after the change.

turns on for two oscillator periods. P2 remains on until
a zero is written to the pin. P3 is used as a latch, so it is
turned on whenever the pin is above the threshold value
'
(around 2 volts).

Port I, Port 2.6 and· Port 2.7 are quasi-bidirectional
ports. When the processor writes to the pins of a quasibidirectional port it actually writes into a register which
in turn drives the port pin. When the processor reads
these ports, it senses the status of the pin directly. If a
port pin is to be used as an input then the software
should write a one to its associated SFR bit, this will
cause the low-impedance pull-down device to turn off
and leave the pin pulled up with a relatively high impedance pullup deviCe which can be easily driven down
,by the device driving the input.

To reduce the amount of cutrent which flows when the
pin is externally pulled low, P3 is turned off when the
pin voltage drops below the threshold. The current required to pull the pin from a high to a low is at its
maximum just prior to the pull-up turning off. An external driver'can switch these pins easily. The maximum current required occurs at the threshold voltage
and is approximately 700 microamps.
When the Port 1 pins are used as their alternate functions (HOLD, HLDA, and BREQ), the pins act like a
standard output port.

If some pins of a port are to be used as inputs and some
are to be used as outputs the programmer should be
careful when writing to the port.

HARDWARE CONNECTION HINTS

Particular care should be exercised when using XOR
opcodes or any opcode which is a read-modify-write
instruction. It is possible for a Quasi-Bidirectional Pin
to be written as a one, but read back as a zero if an
external device (i.e., a transistor base) is pulling the pin
below VIH.
Quasi-bidirectional pins can be used as input and output pins without the need for a data di,rection register.
They output a strong low value and a weak high value.
The weak high value can be externally pulled low providing an input function. Figure 12-3 shows the configuration of a CHMOS quasi-bidirectional port.

When using the quasi-bidirectional ports as inputs tied
to switches, series resistors may be needed if the ports
will be written to internally after the part is initialized.
The amount of current sourced to ground from each
pin is typically 7 rnA or more. Therefore, if all 8 pins
are tied to ground, 56 rnA will be sourced. This is
equivalent to instantaneously doubling the power used
by the chip and may cause noise in some applications.
This potential problem can be solved in hardware or
software. In software, never write a zero to a pin being
'- usee! as an input.

Outputting a 0 on a quasi-bidirectional. pin turns on the
strong pull-down and turns off all of th,e pull-ups.
When a 1 is output the pull-down is turned off and 3
pull-ups (strong-PI, weak-P3, very weak-P2) are turned
on. Each time, a, pin switches from 0 to 1 transistor PI

In hardware, a LK resistor in series with each pin will
limit current to a reasonable value without impeding
the ability to override the high impedance p).llll,lp. If all
8 pins are tied together a 1200 resistor would be reasonable. The problem is not quite as severe when the
4-64

infef

80C196KB USER'S GUIDE

inputs are tied to electronic devices instead of switches,
as most external pulldowns will not hold 20 rnA to 0.0
volts.

the voltage present on the port pin. The second case can
be taken care of in the software fairly easily:

LDB
XORB
ORB
STB

Writing to a Quasi-Bidirectional Port with electronic
devices attached to' the pins requires special attention.
Consider using P1.0 as an input and trying to toggle
P 1.1 as an output:

ORB

IOPORT1, #OOOOOOOlB

XORB IOPORT1, #OOOOOOlOB

If a switch is used on a long line connected to a quasibidirectional pin, a pullup resistor is recommended to
reduce the possibility of noise glitches and to decrease
the rise time of the line. On extremely long lines that
are handling slow signals, a capacitor may be helpful in
addition to the resistor to reduce noise.

12.3 Output Ports
Output pins include the bus control lines, the HSO
lines, and some of Port 2. These pins can only be used
as outputs as there are no input buffers connected to
them. The output pins are output before the rising edge
of PHI and is valid some time during PHI. Externally,
PHI corresponds to CLKOUT low. It is not possible to
use immediate logical instructions such as XOR to toggle these pins.

The second problem, which is related to the first, is that
if P1.0 happens to be driven to a zero when Port 1 is
read by the XORB instruction, then the XORB will
write a zero to P1.0 and it will no longer be useable as
an input.

The control outputs and HSO pins have output buffers
with the same output characteristics as those of the bus
pins. Included in the category of control outputs are:
TXD, RXD (in Mode 0), PWM, CLKOUT, ALE~
BHE, RD, and WR. The bus pins have 3 states: output
high, output low, and high impedance. Figure 12-4
shows the internal configuration of an output pin.

The first situation can best be solved by the external
driver design. A series resistor between the port pin and
the base of the transistor often works by bringing up

IOPORTl
#OlOB
#OOlB
IOPORTl

A software solution to both cases is to keep a byte in
RAM as an image of the data to be output to the port;
any time the software wants to modify the data on the
port it can then modify the image byte and copy it to
the port.

Set PLO
for input
Complement
Pl.l

The first instruction will work as expected but two
problems can occur when the second instruction executes. The first is that even though P 1.1 is being driven
high by the 80C 196KB it is possible that it is being held
low externally. This typically happens when the port
pin drives the base of an NPN transistor which in turn
drives whatever there is in the outside world which
needs to be toggled. The base of the transistor will
clamp the port pin to the transistor's Vbe above
ground, typically 0.7V. The 80C196KB will input this
value asa zero even if a one has been written to the port
pin. When this happens the XORB instruction will always write a one to the port pin's SFR and the pin will
not toggle.

BUS

AL,
AL,
AL,
AL,

LATCH

IE
ALT. - - - 4 - - - - - 1
FUNCT.

BUS PORT

FCN SELECT

RESET

Figure 12·4. Output Port

4-65

270651-77

/ilOC196KB USER'S GUIDE

be used as inputs. Reading Port 3 and 4 from a previously written zero condition is as follows ...

12;4 Ports 3 and 4/ADO-15
These pins have two functions. They are either bidirectional ports with open-drain outputs or System Bus
pins which the memory controller uses when it is accessing off-chip memory. If the EA line is low, the pins
always act as the System Bus. Otherwise they act as bus
pins only during a memory access. If these pins are
being used ·as ports and bus pins, ones must be written
to them prior to bus operations.
Accessing Port 3 and 4 as I/O is easily done from internal registers. Since the LD and ST instructions require
the use of internal registers, it may be necessary to first
move the port information .into an internal location before utilizing the data. If the data is already internal,
the LD is unnecessary. For instance, to write a word
value to Port 3 and 4 ...

,register +data
not needed if
already
internal

LD intreg, portdata

ST intreg, IFFEH

To read Port 3 and 4 requires that "ones" be written to
the port registers to first setup the input port configuration circuit. Note that the ports are reset to this input
condition, but if zeroes have been written to the port,
then ones must be re-written to any pins which are to

BUS

LD intregA, #OFFFFH

ST intregA, lFFEH

LD intr,egB, lFFEH

setup port
change mode
pattern
register -+
., Port 3' and 4
LD II: ST not
needed if
previously
written as ones
register +,Port 3 and 4

Note that while the format of the LD and ST instructions are sirrtilar, the source and destination directions
change.
When acting as the system bus the pins have strong
drivers to both Vee and V ss. These drivers are used
whenever data is being output on the system bus.and
are not used when data is being output by Ports 3 and
4. The pins, external input buffers and pulldowns are
shared between the bus and the ports. The ports use
different output buffers which are configured as opendrain, and require external pull up resistors. (open-drain
is the MOS version of open-collector.) The port pins
and their system bus functions are shown in Figure
12-5.

P3/4

LATCH

ADDR~__~______~

DATA

PIN--+--+--+-+---__I-CI<
PORT BUS
SAMPLE
BUS PORT
FCN SELECT

RESET

Figure 12-5. Port 3, 4/ADO-15 Pins

270651-41

inter

80C196KB USER'S GUIDE

Ports 3 and 4 on the 80CI96KB are open drain ports.
There is no pullup when these pins are used as I/O
ports. A diagram of the output buffers connected to
Ports 3 and 4 and the bus pins is shown in Figure 12-5.

follow good design and board layout techniques to keep
noise to a minimum. Liberal use of decoupling caps,
Vee and ground planes, and transient absorbers can all
be of great help. It is much easier to design a board
with these features then to search for random noise on
a poorly designed PC board. For more information on
noise, refer to Applications Note AP-125, 'Designing
Microcontroller Systems for Noisy Environments' in
the Embedded Control Application Handbook.

When Ports 3 and 4 are to be used as inputs, or as bus
pins, they must first be written with a 'I'. This will put
the ports in a high impedance mode. When they are
used as outputs, a pullup resistor must be used externally. A 15K pullup resistor will source a maximum of
0.33 milliamps, so it would be a reasonable value to
choose if no other circuits with pullups were connected
to the pin.

13.3 Oscillator arid Internal Timings
ON-CHIP OSCILLATOR

Ports 3 and 4, are addressed as off-chip memorym;:tpped I/O. The port pins will change state shortly
after the falling edge ofCLKOUT. When these pins are
used as Ports 3 and 4 they are open drains, their structure is different when they are used as part of the bus.

The on-chip oscillator circuitry for the 80C196KB, as
shown in Figure 13.1, consists of a crystal-controlled,
positive reactance oscillator. In this application, the
crystal is operated in its fundamental response mode as
an inductive reactance in parallel resonance with capacitance external to the crystal.

Port 3 and 4 can be reconstructed as I/O ports from the
Address/Data bus. Refer to Section 15.7 for details.

Vee

13.0 MINIMUM HARDWARE
CONSIDERATIONS

,----------1--+

The 80C 196KB requires several external connections to
opera,te ,correctly. Power and ground must be connected, al clock source must be generated, and a reset circuit
must be present. We will look at each of these areas in
detail.

To internal
circuitry

Rf
XTAL1

13.1. Power Supply
Power to the 80C196KB flows'through 5 pins. Vee
supplies the positive voltage to the digital portion of the
chip while VREF supplies the A/D converter and PortO
with a positive voltage. These two pins need to be connected to a 5 volt power supply. When using the A/D
converter, it is desirable to connect VREF to a separate
power supply, or at least a separate trace to minimize
the noise in the A/D converter.

Vss
270651-42

Figure 13-1. On-Chip Oscillator Circuitry

The feedback resistor, Rf, consists of paralleled n-channel and p-channel FETs controlled by the PD (powerdown) bit. R,f acts as an open when in Powerdown
Mode. Both XTALl and XTAL2 also have ESD protection on the pins Which is not shown in the figure.

The four common return pins, VSSl, VSS2, Vss3, and
Angd, must all be nominally at 0 volts. Even if the
A/D converter is not being used, VREF and Angd must
still be connected for PortO to function.

The crystal specifications and capacitance values in
Figure 13-2 are not critical. 20 pF is adequate for any
frequency above I MHz with good quality ,crystals. Ceramic resonators can be used instead of a crystal in cost
sensitive applications. For ceramic resonators, the man,ufacturer .should be contacted for values of the capacitors.

13.2 Noise Protection Tips
Due to the fast rise and fall times of high speed CMOS
logic, noise glitches on the power supply lines and outputs at the chip are not uncommon. The 80C196KB is
no exception to this rule. So it is extremely important to

4-67

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80Ct96KB USER'S GUIDE

INTERNAL TIMINGS
TO INTERNAL
CIRCUITS

XTALI

QUARTZ CRYSTAL
OR CERAMIC
RESONATOR

---1=:::t.--1DI----J

XTAL2

20~PF

270651-43

Figure 13-2. External Crystal Connections

Internal operation of the chip is based on the oscillator
frequency divided by two, giving the basic time unit,
known as a 'state time'. With a 12 Mhz crystal, a state
time is 167 nS. Since the 80CI96KB can operate at
many frequencies, the times given throughout this overview will be in state times.
Two non-overlapping internal phases are created by the
clock generator: phase 1 and phase 2 as shown in Figure 13-4. CLKOUT is generated by the rising edge of
phase I and phase 2. This is not the same as the
8096BH, which uses a three phase clock. Changing
from a three phase clock to a two phase one speeds up
operation for a set oscillator frequency. Consult the latest data sheet for AC timing specifications.

To driv~ the 80CI96KB with an external clock source,
apply the external clock signal to XTALl and let
XTAL2 float. An example of this circuit is shown in
Figure 13-3. The required voltage levels on XTALl are
specified in the data sheet. The signal on XTALl must
be clean with good solid levels.

PHASE1~

PHASE2~
"

It is important that the minimum high and low times

270651-44

Figure 13-4. Internal Clock Phases

13.4 Reset and Reset Status
Reset starts the 80CI96KB off in a known state. To
reset the chip, the RESET pin must be held low for at
least four state times after the power supply is within
tolerance and the oscillator has stabilized. As soon as
the RESET pin is pulled low, the I/O and control pins
are asynchronously driven to their reset condition.

DIVIOER CIRCUITRY

Vce

After, the RESET pin is brought high, a ten state reset
sequence occurs as shown in Figure 13-5. During this
time the CCB (Chip Configuration Byte) is read from
location 2018H and stored in the CCR (Chip Configuration Register). The EA (External Access) pin qualifies whether the CCB is read from external or internal
memory. Figure 13-6 'gives the reset status of all the
pins and Special Function Registers.

--------------------- ------Vee
5K

CLKOUT~

are met to avoid having the XTAL I pin in the transition range for long periods of time. The longer the
signal is in the transition region, the higher the probability that an external noise glitch could be seen by the
clock generator circuitry. Noise glitches on the
,80C196KB internal c10ckilines will cause unreliable operation.

XTAL1

XTAL2
FLOAT

270651-78

Figure 13-3. External Clock Drive

4·68

l
8OC196KB Reset Sequence
RESET
PIN

"II

...r::

---C)
BYTE

___
.r

2081H

(

2080H

>--CJ(

::D

>---C)

2082H

270651-45

cii

80C196KB USER'S GUIDE

WATCHDOG TIMER

RST INSTRUCTION

There are three ways in which the 80Cl96KB can reset
itself. The watchdog timer will reset the 80C 196KB if it
is not cleared in 64K state times. The watchdog timer is
enabled the first time it is cleared. To clear the watchdog, write a 'IE' followed immediately by an 'EI' to
location OAH. Once enabled, the watchdog can only be
disabled by a reset.
.

Executing II RST instruction will also reset the
80C196KB. The opcode for the RST instruction is
OFFH. By putting pullups on the Addr/data bus, unimplemented areas of memory will read OFFH and cause
the 80Cl96KB to be reset.

Pin
Name

Multiplexed
Port Pins

Value of the
Pin on Reset

RESET

Mid-sized Pullup

ALE

Weak Pull up

Weak Pullup

8HE

Weak Pullup

INST

Weak Pullup

Undefined Input •

AD_RESULT

7FFOH

HSI_STATUS

xOxOxOx08

S8UF(RX)

Weak Pullup
\

Value

OOH

INT_MASK

000000008

INT_PENDING

000000008

TIMER1
TIMER2
IOPORT1

OOOOH
OOOOH
111111118

READY

Undefined Input •

IOPORT2

110000018

NMI

Undefined Input •

SP_STAT ISP_CON

000010118

8USWIDTH

Undefined Input •

IMASK1

000000008

CLKOUT

Phase 2 of Clock

IPEND1

000000008

WSR

XXXXOOO08

HSI_MODE

111111118

IOG2

XOOOOOO08

lOCO

000000X08

IOC1

001000018

System 8us

P3.0-P4.7

Weak Pullups

ACHO-7

PO.0-PO.7

Undefined Input •

PORT1

P1.0-P1.7

Weak Pullups

TXD

P2.0

Weak Pullup

RXD

P2.1

Undefined Input •

EXTINT

P2.2

Undefined Input •

PWM_CONTROL

T2CLK

P2.3

Undefined Input •

IOPORT3

111111118

T2RST

P2.4

Undefined Input •

IOPORT4

111111118

PWM

P2.5

Weak Pulldown

10SO

000000008

P2.6-P2.7

Weak Pullups

IOS1

000000008

IOS2

000000008

HSI0-HSI1

Undefined Input,'

HSI2/HS04

Undefined Input •

HSI3/HS05

Undefined Input •

HSOO-HS03

Weak Pull down

OOH

'These pins must be driven and not left floating.

Figure 13·6. Chip Reset Status

4-70

80C196KB USER'S GUIDE

is only asserted for four state times. If this is done, it is
possible for the 80CI96KB to start running before other chips in the system are out of reset. Software must
take this condition into account. A capacitor cannot be
connected directly to RESET if it is to drive the reset
pins of other chips in the circuit. The capacitor may
keep the voltage on the pin from going below guaranteed VIL for circuits connected to the RESET pin. Figure 13-8 shows an example of a system reset circuit.

RESET CIRCUITS

The si~plest way to reset an 80CI96KB is to insert a
capacitor between the RESET pin and Vss. The
80CI96KB has an internal pullup which has a value
between 6K and 50K ohms. A 5 uF or greater capacitor should provide sufficient reset time as long as Vcc
rises quickly.
, Figure 13-7 shows what the RESET pin looks like internally. The RESET pin functions' as an input and as
an output to reset an entire system with a watchdog
timer overflow, or by executing a RST instruction. For
a system reset application, the reset circuit should be a
one-shot with an open collector output. The reset pulse
may have to be lengthened and buffered since RESET

13.5 Minimum Hardware Connections
Figure 13-9 shows the minimum connections needed to
get the 80CI96KB up and running. It is important to
tie all unused inputs to Vee or V ss. If these pins are

. RESET
PIN

80C196KB CHIP
RESET

WATCHDOG TIMER
OVERFLOW
RESET INSTRUCTION
(OFFH)

270651-46

Figure 13-7. Reset Pin

80C196KB

Vee

RESET

1-......-1

OPTIONAL
ONE-SHOT
74LS123

OTHER
CIRCUITRY

(1 ) ,

270651-47

NOTE:
. 1. The diode will provide a faster eycle time repetitive power-on-resets.

Figure 13'-8. System Reset Circuit

4-71

80C196KB USER'S GUIDE

20pF

q,
+5V

"5V

vee

VREF

1 p.F
ANGND

VSS1
VSS2
VSS3

+5V
BUSWIDTH
READY
Vpp

RESET
5p.F

.l:

BUS
CONTROL
RXD
EXTINT
T2CLK
T2RST
HSI.O- HSI.3
NMI

ADO-AD15
PO.O- PO.7

80C196KB
270651-48

NOTE:

'Must be driven high or low.
"VSS3 was formerly the CDE pin. The CDE function is no longer available. This pin must be connectd to V$s.
Figure 13·9. 80C196KB Minimum Hardware Connections

left floating, they can float to a mid voltage level and
draw excessive current. Some pins such as NMI or
EXTINT may generate spurious interrupts if left unconnected.

the CPU out of the Idle Mode, the CPU vectors to the
corresponding interrupt service routine and begins exe~
cuting. The CPU returns from the interrupt service
routine to the next instruction following the 'IDLPD
# l' instruction that put the CPU in the Idle Mode.,

14.0 SPECIAL MODES OF
OPERATION

In the Idle Mode, the system bus control pins (ALE,
RD, WR, INST, and BHE), go to their inactive states.
Ports 3 and 4 will retain the value present in their data
latches if being used as I/O ports. If these ports are the
ADDR/DATA bus, the pins will float.

The 80C196KB has Idle and Powerdown Modes to reduce the amount of current consumed by the chip. The
80CI96KB also has an ONCE (ON-Circuit-Emulation)
Mode to isolate itself from the rest of the components
in the system.

It is important to note the Watchdog Timer continues
to run in the Idle Mode if it is enabled. So the chip
must be awakened every 64K state times to clear the
Watchdog or the chip will reset.

14.1 Idle Mode
The Idle Mode is entered by executing the instruction
'IDLPD # I'. In the Idle Mode, the CPU stops executing. The CPU clocks are frozen at logic ~tate zero, but
the peripheral clocks continue to be active. CLKOUT
continues to be active. Power consumption in the Idle
Mode is reduced to about 40% of the active Mode.

14.2 Powerdown Mode
The Powerdown Mode is entered by executing the instruction, 'IDLPD #2'. In the Powel-down Mode, all
internal clocks are frozen at logic state zero and the
oscillator is shut off. All 232 bytes of registers and rnPst
peripherals hold their values if Vee is maintained.
Power is reduced to the device leakage arid}s in the qA
range. The 87CI96KB (EPROM part) will consume
more power if the EPROM window is not covered<

The CPU exits the Idle Mode by any enabled interrupt
source or a hardware reset .. Since all of the peripherals
are running, the interrupt can be generated by the HSI,
HSO, A/D, serial port, etc. When an interrupt brings
4-72

inter

80C196KB USER'S GUIDE

XTAL1

CLKOUT

PHl

,,
INTERNAL'
i---+--;"--;~S
POWERDOWN :
SIGNAL ;"1--;---i---i---i---'

------;.-+--i

r-I

Vpp :

---------------'~S r-1

TIMEOUT .,..:

270651-49

Figure 14·1. Power Up and Power Down Sequence

In Powerdown, the bus control pins go to their Inactive
states. All of the"output pins will assume the value in
their data latches. Ports 3 and 4 will continue to act as
ports in the .single chip mode or will float if acting as
the ADDR/DATA bus.

If the external interrupt brings the chip Qut of Power-

down, the corresponding bit will be set in the interrupt
pending register. If the interrupt is unmasked, the part
will immediately execute the interrupt service routine,
and return to the instruction following the IDLPD instruction that put the 'chip into Powerdown. If the interrupt is masked, the chip will start at the instruction
following the IDLPD in~truction. The bit in the pending registe~ will remain set, however.

To pr~vent accidental entry into the Powerdown Mode,
this feature may be' disabled at reset by clearing bit 0 of
the CCR (Chip Configuration Register). Since the default value of the CCR bit 0 is 1, the Powerdown Mode
is normally enabled.

All peripherals should be in an inactive state before
entering Powerdown. If the AID converter is in the
middle of a conversion, it is aborted. If the chip comes
out of Powerdown by an external interrupt, the serial
port will continue where it left off. Make sure that the
serial port is done transmitting or receiving before entering Powerdown. The SFRs associated with the AID
and the serial port may also contain incorrect information when returning from Powerdown.

The Powerdown Mode can be exited by a chip reset or
a high level on the external interrupt pin. If the RESET
pin is used, it must be asserted long enough for the
oscillator to stabilize.
Whim exiting Powerdown with an external interrupt, a
positive level on the pin mapped to INT7 (either
EXTINT or portO.7) will bring the chip out of Powerdown MoX( _ _ _ _ _ _ _ _ _ _ X

I
--<:::::AD:D:RE:SS:O:U:T

DATA OUT

______
_
ADDRESS
270651-81

XTAL1

CLKOUT

ALE

BUSWIDTH

BUS

~ ,~:J ~~:'. )

~---------------I

--:'1-'- - -tAVGV
- -~
1

--<~--------~~~----)~----------

270651-84

Figure 15-14. AC Timing Diagrams (Continued)

4·83

80C196KB USER'S GUIDE

TIMINGS THE MEMORY SYSTEM MUST MEET:

TAVYV - ADDRESS Valid to READY Setup:
Maximum time the memory system has
to decode READY after ADDRESS is
output by the 80C196KB to guarantee at
least one-wait state will occur.
TLLYV - ALE Low to READY Setup: Maximum
time the memory system has to decode
READY after ALE falls to guarantee at
least one wait state will occur.
TYLYH - READY Low to READY HIGH:
Maximum amount of nonREADY time
or the maximum number of wait states
that can be inserted into a bus cycle.
Since the 80C196KB is a completely
static part, T YLYH is unbounded.
TCLYX - READY Hold after CLKOUT Low:
Minimum time the level on the READY
pin must be valid after CLKOUT falls.
The minimum hold time is always 0 ns.
If maximum value is exceeded, additional wait states will occur.
TLLYX - READY Hold AFTER ALE Low:
Minimum time the level on the READY
pin must be valid after ALE falls. If
maximum value is exceeded, additional
wait states will occur.
ITAVGV - ADDRESS Valid to BUSWIDTH Valid: Maximum' time the memory system
has to decode BUSWIDTH after ADDRESS is output by the 80C196KB. If
exceeded, it is not guaranteed the
80C196KB will respond with an 8- or
16-bit bus cycle.
TLLGV - ALE Low to BUSWIDTH Valid:
Maximum time after ALE/ADV falls
until BUSWIDTH must be valid. If exceeded, it is not guaranteed the
80C196KB will respond with an 8- or
16-bit bus cycle.
T CLGX - BUSWIDTH Hold after CLKOUT
Low: Minimum time BUSWIDTH must
be held valid after CLKOUT falls. Always 0 ns of the 80C I 96KB.
TAVDV - ADDRESS Valid to Input Data Valid:
Maximum time the memory system has
to output valid data after the 80C196KB.
outputs a valid address.
TRLDV - RD Low to Input Data Valid: Maximum
time the memory system has to output
valid data after the 80C 196KB asserts
RD.

TCLDV - CLKOUT Low to Input Data Valid:
Maximum time the memory system has
to output valid data'after. the CtKOUT
falls.
- RD High to Input Data Float: Time after RD is inactive until the memory system must flbat the bus. If this timing is
not met, bus contention will occur.
- Data Hold after RD Inactive: Time after
RD is inactive that the memory system
qlUst hold Data on the bus. Always 0 ns
on the 80C196KB.
TIMINGS THE 80C196KB WILL PROVIDE:

FXTAL

- Frequency on XTALl: Frequency ofsignal input into the 80C196KB. The
80C196KB runs internally at 1/2 FXTAL.
-l/FxTAL:
All A.C. Timings are referTosc
enced to T osc.
TXHCH - XTALl High to CLKOUT High or
Low: Needed in systems where the signal driving XTALl is also a clock for
external devices.
TCLCL - CLKOUT Cycle Time: Nominally 2
Tosc·
TCHCL - CLKOUT High Period: Needed in systems which use CLKOUT as clock for
external devices,
TCLLH - CLKOUT Falling Edge to ALE/ADV
Rising: A help in deriving other timings.
- ALE/ADV Falling Edge to CLKOUT
Rising: A help in deriving other timings.
- ALE Cycle Time: Time between ALE
pulses.
ALE/
ADV High Period:' Useful in deTiHLL
termining ALE/ADV rising edge to
ADDRESS valid. External latches must
also meet this spec.
- ADDRESS Setup to ALE/ADV Falling
Edge: Length of time ADDRESS is valid before ALE/ADV falls. External
latches must meet this spec.
- ADDRESS Hold after ALE/ADV Failing Edge: Length of Time ADDRESS is
valid after ALE/ADV falls. External
latches must meet this spec.
- ALE/ADV Low to RD Low: Len~ of
time after ALE/ADV falls before RD is
asserted. Could be needed to insure
proper memory decoding takes place before a device is enabled.

Figure 15-15. AC Timing Explanations

4-84

80C196KB USER'S GUIDE

TRLCL

- RD Low to CLKOUT Falling Edge:
Length of time from RD asserted to
CLKOUT falling edge: Useful for systems based on CLKOUT.
TRLRH - RD Low to RDHigh: RD pulse width.
- RD.High to ALE/ADV Asserted: Time
between RD going inactive and next
ALE/ADV, also used to calculate time
between inactive and next ADDRESS
valid.
- RD Low to ADDRESS Float: Us~d to
calculate when the 80C196KB stops
driving ADDRESS on the bus.
- ALE/ADV Low Edge to WR Low:
Length of time ALE/ADV falls before
WR is asserted. Could be needed to ensure proper memory decoding takes
place before a device is enabled.
TCLWL - CLKOUTFalling Edge to WR Low:
Time between CLKOUT going low and
WR being asserted. Useful in systems
based on CLKOUT.
- Data Valid to WR Rising Edge: Time
between data being valid on the bus and
WR going inactive. Memory devices
must meet this spec.
TCHWH - CLKOUT High to WR Rising Edge:
Time between CLKOUT going high and
WR going inactive. Useful in systems
based on CLKOUT.

TWLWH - WR Low to WR High: WR pulse width.
Memory devices must meet this spec.
TWHQX - Data Hold after WR Rising Edge:
Amount of time data is valid on the bus
after WR going inactive. Memory devices must meet this spec.
TWHLH - WR Rising Edge to ALE/ADV Rising
Edge: Time between WR goirig inactive
and next ALE/ADV. Also used to calculate WR inactive and next ADDRESS
valid.
TWHBX - BHE, INST, Hold after WR Rising
Edge: Minimum time these signals wiil
be valid after WR inactive.
TRHBX - BHE, INST HOLD after RD Rising
Edge: Minimum time these signals will
be valid after RD inactive.
TWHAX - ADS-IS Hold after WR Rising Edge:
Minimum time the high byte of the address in 8-bit mode will be valid after
WR inactive.
TRHAX - ADS-IS Hold after RD Rising Edge:
Minimum time the high byte of the address in 8-bit mode will be valid after
RD inactive.

Figure 15-15. AC Timing Explanations (Continued)

i5E

Ri5
AD8-15

80C196KB
ADO-7

ADV

HIGH ADDRESS

DATA

EPROM

74AC
373

LOW ADDRESS

-y-~

\
OPTIONAL IF

LATCHED EPROM
IS USED

Figure 15-16. 8-Bit System with EPROM

4-85

270651-66

inter

80C196KB USER'S GUIDE

ed in the lower half of memory,and the RAM in the
upper half.

15.6 Memory System Examples
External memory systems for the 80C196KB can be set
ull in many different ways. Figure 15-16 shows a simille
8 bit system with a single EPROM. The ADV Mode
can be selected to Ilrovide a chill select to the memory.
By setting bit CCR.I to 0, the system is locked into the
eight bit mode. An eight bit system with EPROM and
RAM is shown in Figure 15-17. The EPROM is decod-

Figure 15-18 shows a 16 bit system with 2 EPROMs.
Again, ADV is used to chip select the memory. Figure
15-19 shows a system with dynamic bus width. Code is
executed from the two EPROMs and data is stored in
the single RAM .. Note the Chip Select of the RAM also
is input to the BUSWIDTH pin to select an eight bit
cycle.

AD15
AD8-1SI-_ _...._ _..
. -_ _ _ _ DATA

80C196KB

DATA

EPROM

ADO-7t-. ..j
ADV

HIGH ADDRESS

RAM

LOW ADDRESS

1------1

~ ~--------4--------I
WR

~----------------------~
270651-67

Figure 15-17. 8-Bit System with EPROM and RAM

HIGH ADDRESS

EPROM

~~~;;:t~ DATA
LOW ADDRESS

DATA

LOW ADDRESS

80C196KB
~

____________-+__________-J
270651-68

Figure 15-18. 16-Bit System with EPROM

4-86

80C196KB USER'S GUIDE

EPROM
ADV

r~;;l::J

RAM

DATA

LOW ADDRESS

R5
WR

____________

DE
~~

__________

____________-J

~--------------------------------------------~
270651-69

Figure 15-19. 16-Bit System with Dynamic Buswidth

WRL----------q--,P-______________~

MDO-MD7

WRH

MD8-MD15

74LS
04
(x11Az)

74LS
273

CLR
RESET

INPUT

ADDR = P3, P4
RD
ADO-AD7

AD8-AD15

270651-70

Figure 15-20. 1/0 Port Reconstruction

4-87

inter

80C196KB USER'S GUIDE

The Run-Time Programming Mode allows individual EPROM'locations to be programmed at run-time
under complete software control. (Run-Time Programming is done with EA = 5V.)

15.7 1/0 Port Reconstruction
When a single-chip system is being designed using a
multiple chip system as a prototype, it may be necessary to reconstruct I/O Ports 3 and 4 using a memory
mapped I/O technique. The circuit to reconstruct the
Ports is shown in Figure 15-20. It can be attached to a
80C196KB system which has the required address decoding and bus demultiplexing.
The output circuitry is a latch that operates when
IFFEH or IFFFH are placed on the MA lines. The
inverters surrounding the latch create an open-collector
output to emulate~n-drain output found on the
80C196KB. The RESET line sets the ports to all Is
when the chip is reset. The voltage and current specifications of the port will be different from the
80C196KB, but the functionality will be the same.
The input circuitry is a bus transceiver that is addressed
at IFFEH and IFFFH. If the ports are going to be
either inputs or outputs, but not both, some of the circuitry may be eliminated.

In the Programming Mode some I/O pins have new
functions. These pins determine the programming function, provide programming control signals and slave ID
numbers, and pass error information. Figure 16-1
shows how the pins are renamed. Figure 16-2 describes
each new pin function.
PMODE sf;!lects the programming mode (see Figure
16-3). The 87C196KB does not need to be in the Programming Mode to do run-time programming; it can be
done at any time.
When an 87C196KB EPROM device is not being
erased the window must be covered with an opaque
label. This prevents ftmctional degradation and data
loss from the array.

16.1 Power-Up and Power-Down
16.0 USING THE EPROM

To avoid damaging devices during programming, follow these rules:

the 87CI96KB contains 8 Kbytes of ultraviolet Erasable and electrically Programmable Read Only Memory (EPROM). When EA is a TTL high, the EPROM is
located at memory locations 2000H through 3FFFH.

RULE # 1 Vpp must be within IV of Vee while Vee
is below 4.5V.
RULE #2 Vpp can not be higher than 5.0V until Vee
is above 4.5V.
RULE #3 Vpp must not have a low impedance path
to ground when Vee is above 4.5V.
RULE #4 EA must be brought to 12.75V before Vpp
is brought to 12.75V (not needed for runtime programming).
RULE # 5 The PMODE and SID pins must be in
their desired state before RESET rises.
RULE #,6 All voltages must be within tolerance and
the oscillator stable before RESET rises.
RULE #7 The supplies to Vee, Vpp, EA and RESET must be well regulated and free of
spikes and glitches.

Applying + 12.75V to EA when the chip is reset places
the 87C196KB device in the EPROM Programming
Mode. The Programming Mode supports EPROM programming and verification. The following is a brief description of each of the programming modes:
The Auto Configuration Byte Programming Mode
programs the Programming Chip Configuration Byte
and the Chip Configuration Byte.
The Auto Programming Mode enables an
87C196KB to program itself without using an
EPROM programmer.
The Slave Programming Mode provides a standard
interface for programming any number of
87C196KB's by a master device such as an EPROM
programmer.

To adhere to these rules you can use the following power-up and power-down sequences:

4-88

inter

80C196KB USER'S GUIDE

POWER-UP

RESET = OV
Vee = vpp = EA = 5V
CLOCK on (if using an external clock instead of the
internal oscillator)
PALE = PROG = PORT3,4 = VIH(1)
SID and PMODE valid
'
EA = 12.75V(2)
Vpp = 12.75V(3)
WAIT (wait for supplies and clock to settle)
RESET = 5V
WAIT Tshll (RESET high to first PALE low)
BEGIN
POWER-DOWN

EA = 5V
PALE = PROG = SID = PMODE = PORT3,4 =
OV
Vee = Vpp = EA = OV
CLOCK OFF
NOTES:
1. VIH = logical "I" (2.4V minimum)
2. The same power supply can be used for EA and
Vpp. However, the EA pin must be powered up before
Vpp is powered up. Also, EA should be protected
from noise to prevent damage to it.
3. Exceeding the maximum limit on Vpp for any
amount of time could damage the device permanently.
The Vpp source must be well regulated and free of
glitches.

RESET = OV
Vpp"" 5V

16.2 Reserved Locations
All Intel Reserved locations except address 2019H,
when mapped internally or externally, must be loaded
with OFFH to ensure compatibility with future devices.
Address 2019H must be loaded with 20H.

PROGRAMMING VOLTAGE

ADDRESS
P 2 . 7 1 - - - - - - - + PACT
P2.1
P2.2

PROG

P2.0

PVER

HSI.3
P2.4
87C196KB

AINC

HSI.O
~.".SI",.D-"\IHSI.1
~--"rIHSI.2

~VAL (P3.0)

PALE

270651-71

Figure 16-1. Programming Mode Pin Functions

4-89

80C196KB .USER'S GUIDE

Name

Function

General

PMODE
(PO-0.4, 0.5,
0.6,0.7)

Programming Mode Select. Determines the EPROM programming
algorithm that is performed. PMODE is sampled after a chip reset and
should be static while the part is operating.

Auto PCCB
Programming Mode

PVER
(P2.0)

Program Verification Output. A high signal indicates that the bytes
have programmed correctly.

f5iIIE

Programming ALE Input. Indicates that Port3 contains the data to be
programmed into the CCB and the PCCB.

Mode

(P2.1)
Auto Programming
Mode

Slave Programming
Mode

PACT
(P2.7)
P'i7A[
(P3.0)

Programming Active Output. Indicates when programming activity is
complete.

Ports
3 and4

Address/Command/Data Bus. Used in the Auto Programming Mode
as a regular system bus to access external memory. Should have
pullups to Vee (15 k!1).

SID
(HSI-O.O,
0.1, 0.2, 0.3)

Slave 10 Number. Used to assign a pin of Port 3 or 4 to each slave to
use for passing programming verification acknowledgement. For
example, ·if gang programming in the Slave Programming Mode, the
slave with SID = 001 will use Port 3.1 to signal correct or .incorrect
program verification.

f5iIIE
(P2.1)

Programming ALE Input. Indicates that Ports 3 and 4 contain a
command/ address.

PROG
(P2.2)

Programming Input. Falling edge indicates valid data on PBUS and the
beginning of programming. Rising edge indicates end of programming.

PVER
(P2.0)

Program Verification Output. Low signal after rising edge of PROG
indicates programming was not successful.

AINC
(P2.4)

Auto Increment Input. Active low input signal indicates that the auto
increment mode is enabled. Auto Increment will allow reading or
writing of sequential EPROM locations without address transactions
across the PBUS for each read or write.

Ports
3 and 4

Address/Command/Data Bus. Used to pass commands, addresses,
and data to and from 87C196KBs in the Slave Programming Mode.
One pin each can be assigned to up to 15 slaves to pass verification
information.

Program Valid Output. Indicates the success or failure of
programming. A zero indicates successful programming.

Figure 16-2.. Programming Mode Pin Definitions
PMODE

Programming Mode

0-4

Reserved

Slave Programming

ROM Dump

7-0BH

Reserved

OCH

Auto Programming

ODH

Program Configuration Byte

OEH-OFH

Reserved

Figure 16-3. Programming
Function Pmode Values

16.3 Programming Pulse Width
Register (PPW)
In the Auto and Run-Time Programming Modes the
width of the programming pulse is determined by the 8
bit PPW (Programming Pulse Width) register. In the
Auto Programming Mode, the PPW is loaded from location 4014H in external memory. In Run-time Programming Mode, the PPW is iocated in window 14 at
04H. In order for the EPROM to properly program,
the pulse width must'be set to approximately 100 uS.
The pulse width is dependent on the oscillator frequency and is calculated with the following formula:
Pulse Width = PPW
PPW = 150

* (Tosc

• 8)

12 Mhz

In the Slave Programming Mode the width of the programming pulse is determined by the PROG signal.

80C196KB USER'S GUIDE

or WRITE lock bits are enabled, some programming
modes will require security key verification before executing and some modes will not execute. See Figure
16-10 and the sections on each programming mode for
details of the effects of enabling the lock bits.

16.4 Auto Configuration Byte
Programming Mode
The Programming Chip Configuration Byte (PCCB) is
a non-memory mapped EPROM location. It gets loaded into the CCR during reset for auto and slave programming. The Auto Configuration Byte Programming
Mode programs the PCCB.

If the PCCB is not programmed, the CCR will be loaded with OFFFH when the device is iii the Programming
Mode.

The Chip Configuration Byte (CCB) is at location
2018H and can be programmed like any other EPROM
location using Auto, Slave, or Run-Time Programming.
However, you can also use Auto Configuration Byte
Programming to program the CCB when no other locations need to be programmed. The CCB is programmed
with the same value as the PCCB.

16.5 Auto Programming Mode
The Auto Programming Mode provides the ability to
program the 87C196KB EPROM without using an
EPROM programmer. For this mode follow the powerup sequence described in Section 16,1 with PMODE =
OCH. External location 4014H must contain the PPW.
When RESET rises, the 87CI96KB automatically programs itself with the data found at external locations
4000H through SFFFH.

The Auto Configuration Byte Programming Mode is
entered by following the power-up sequence described
in 'Section 16.1 with PMODE = ODH, Port 4 =
OFFH, and Port J = the data to be programmed into
the PCCB and CCB. When a 0 is placed on PALE the
CCB and PCCB are automatically programmed with
the data on Port 3. After programming, PVER is driven high if the bytes programmed correctly 'and low if
they did not.

The 87CI96KB begins progral)1ming by setting PACT
low. Then it reads a word from external memory, The
Modified Quick-Pulse Programming Algorithm (described later) programs the corresponding EPROM location. Since the erased state of a byte is OFFH, the
Auto Programming Mode will skip locations with
OFFH for data. When all 8K have been programmed,
PACT goes high and the device outputs a 0 on PV AL
(P3.0) if it programmed correctly and a 1 ,if it failed.
Figure 16-4 shows a minimum configuration using an
8K X 8 EPROM to program an 87CI96KB in the
Auto Programming Mode.

Once the PCCB and CCB are programmed, all programming activities and bus operations use the selected
bus width, READY control, bus controls, and READ/
WRITE protection until you erase the device. You
must be careful whsm programming the READ and
WRITE lock bits in the peCB and CCB. If the READ

AUTO PROGRAMMING MODE AND THE

+12,75 Vdc

CCB/PCCB
EA

Vpp

In the Auto Programming Mode the CCR is loaded
with the PCCB, The PCCB must correspond to the
memory system of the programming setup, including
the READY and bus control selections, You can program the PCCB using the Auto Configuration Byte
Programming Mode (see Section 16.4).
The data in the PCCB takes effect upon reset. 'If you
enable the READ and WRITE lock bits during Auto
Programming but do not reset the device,' Auto Programming will continue. If you enable either the
READ or WRITE lock bits in the CCB using Auto
Configuration Byte Programming and then reset the
87C196KB for Auto Programming, the device does a
security key verification. The same security keys that
reside at internal addresses 2020H-202FH must reside
at external locations 4020H-402FH. If the keys match,
auto programming continues. If the keys do not match,
the device enters an endless loop of internal execution.

270651-73

NOTES:
Tie Port 3 to the value desired to be programmed into
CCS and PCCS.
Make all necessary minimum connections for power,
ground and clock,

Figure 16·5. The PCCB Programming Mode

4-91

80Ct96KB USER'S GUIDE

0.1-1.0,uF
+5V

Rii

lOOK

AD8-AD15

RESET
HSI.0-HSI.3
ADO-AD7

RXD
T2CLK

ALE

NMI

2764

READY
BUSWIDTH

EA
+5V

AO-A7

+5V

T2RST
EXTINT

74LS
373

+5V

+12.75V
Vpp

PO.7
PO.6

+12.75V

PO.S
PACT

POA

87C196KB
27065~

NOTES:
~Inputs !pust be driven high or'low.

_
"Allow RESET to rise after the voltages to Vee. EA. and Vpp are stable.

Figure 16-4. Auto Programming Mode

4-92

-72

inter

80C196KB USER'S GUIDE

The 87C196KB receives an input signal, PALE, to in·
dicate a valid command is present. PROG causes the
87C196KB to read in or output a data word. PVER
indicates if the programming was successful. AINC au·
tomatically increments the address for the Data Program and Word Dump commands.

16.6 Slave Programming Mode
Any number of 87C196KBs can be programmed by a
master programmer through the Slave Programming
Mode. There is no 87C196KB dependent limit to the
number of devices that can be programmed.
In this mode, the 87C196KB programs like a simple
EPROM device and responds to three different com·
mands: data program, data verify, and word dump. The
87C196KB uses Ports 3 and 4 and five other pins to
select commands, to transfer data and addresses, and to
provide handshaking. The two most significant bits on
Ports 3 and 4 specify the command and the lower 14
bits contain the address. The address ranges from
2000H·3FFFH and refers to internal memory space.
Figure 16·6 is a list of valid Programming Commands.
P4.7

P4.6

Action

0
0
1
1

0
1
0
1

Word Dump
Data Verify
Data Program
Reserved

Data Program Command

A Data Program Command is illustrated in Figure 167. Asserting PALE latches the command and address
on Ports 3 and 4. PROG is asserted to latch the data
present oli Ports 3 and 4. PROG also starts the actual
programming sequence. The width of the PROG pulse
determines the programming pulse width. Note that the
PPW is not used in the Slave Programming Mode.
After the rising edge of PROG, the slaves automatically
verify the contents of the location just programmed.
PVER is asserted if the location programmed correctly.
This gives verification information to programmers
which can not use the Data Verify Command. The
AINC pin can increment to the next location or a new
Data Program Command can be issued.

Figure 16-6. Slave Programming
Mode Commands

PORTS
3/4

--<

ADDR/COMMAND

:>-----<:,___ --I:>-----<:
D_A_TA__

ADDR/COMMAND

!
\'--_-J!

\\.....---J!
Figur.e 16-7. Data Program Command in Slave Mode

4-93

270651-74

inter

80C196KB USER'S GUIDE

PVER is a I if the data program was successful. PVER
is a 0 if the data program was unsuccessful. Figure 16-7
shows the relationship of PALE, PROG, and PVER to
the Command/Data path on Ports 3 and 4 for the Data
Program Command.

mand and plac~s the value at the new address on Ports
3 and 4. For example, when the slave receives the ~om
mand OlOOH, it will place the' word at internal address
2100H on Ports 3 and 4. PROG governs when the slave
drives the bus. The Timings are the same as s'lOwnin
Figure 16-7.

Data Verify Command

Note that the Word Dump Command only works when
a single slave is attached to the bus. Also, there is no
restriction on commands that precede or follow a Word
Dump Command.

When the Data Verify Command is sent, the slaves indicate correct or incorrect verification of the previous
Data Program Command by driving one bit of Ports 3
and 4. A I indicates a correct verification, and a 0 indicates incorrect verification. The SID (Slave I.D) of each
slave determines which bit of Ports 3 and 4 will be
driven. For example, a SID of 0001 would drive Port
3.1. PROG governs when the slaves drive the bus. Figure 16-8 shows the relationship of ports 3 and 4 to
PALE and PROG.
A Data Verify Command is always preceded by a Data
Program Command in a programming system with as
many as 16 slaves. However, a Data Verify Command
does not have to follow every Data Program Command.

Word Dump Command

Gang Programming With the Slave
Programming Mode
Gang Programming of 87CI96KBs can be done using
the Slave Programming Mode. There is no 87CI96KB
based limit on the number of devices that may be
hooked to the same Port 3 and 4 data path for gang
programming.
If more than 16 devices are being gang programmed,
the PVER outputs of each chip can be used for verification. The master programmer can issue a Data Program Command, then either watch every device's error
signal, or AND all the signals together to form a system PVER.

When the Word Dump Command is issued, the
87C 196KB adds 2000H to the address field of the com-

PORTS
3/4

ADDR/COMMAND

ADDR

ADDR+ 2

VER BITS/WD DUMP

\~_---JI
\~_--.-JI

\~----------------------

270651-75

Figure 16-8. Ports 3 and 4 to PALE and PROG

4-94

inter

80C196KB USER'S GUIDE

If 16 or fewer 87CI96KBs are to be gang programmed
at once, a more flexible form of verification is available
by giving each device a unique SID. The master programmer can issue a Data Verify Command after the
Data Program Command. When a verify command is
seen by the slaves, each will drive a bit of Ports 3 or 4
corresponding to its unique SID. A I indicates the address verified, while a 0 means it failed.

16.7 Run-Time Programming
The 87Cl96KB can program itself under software control. One byte or word can be programmed instead of
the entire atray. The only additional requirement is
that you apply a programming voltage to Vpp and have
the ambient temperature at 25°C. Run-time programming is done with EA at a TTL high (internal memory
enabled).

SLAVE PROGRAMMING MODE AND THE

To Run-Time Program, the user writes to the location
to be programmed. The value of the PPW register determines the programming pulse. To ensure 87CI96KC
compatibility, the Idle Mode should be used for RunTime Programming. Figure 16-9 is the recommended
code sequence for Run-Time Programming" The Modified Quick Pulse algorithm guarantees the programmed
EPROM cell for the life of the part.

CCB/PCCB
Devices in the Slave Programming Mode use Ports 3
and 4 as the command/data path. The data bus is not
used. Therefore, you do not need to program either the
CCB or the PCCB before starting slave programming.
You can program the CCB like any other location in
slave mode. Data programmed into the CCB takes effect upon reset. If you enable eitller the READ or the
WRITE lock bits in the CCB during slave programming and do not reset the device, slave programming
will continue. If you do reset the device, the device first
does a security key verification. The same security keys
that reside at intern

0 0 0 0

"1
0

...........................................
"

NO,....

to')

...'" ...'" '"~ ...'" ...'" ...'"
CJ

~ I~ >tl

....

~:! j:!
> x x

.... '"b
I~
0
~ .........
~ ::>

::>
CJ

~ ~I~

1 68 67 66 65 64 63 6261

ACH5/PO.5

ADO/PM

ACH4/PO.4

AD1/P3.1
AD2/P3.2

ANGND
VREF

Vss
EXTINT/P2.2
RESET

MCS®-96
68 PIN
PLCC

RXD/P2.1

PLI
PL2
PL3
PL4
HSIO

AD4/P3.4
AD5/PM
AD6/P3.6
AD7/P3.7
AD8/P4.0

TXD/P2.0
P1.0

AD3/P3.3

AD9/P4.1

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD

HSII

AD10/P4.2
ADll/P4.3
ADI2/P4.4
ADI3/P4.5
ADI4/P4.6
ADI5/P4.7
T2CLK/P2.3

HSI2/HS04
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

270918-3

Figure 5. 5S-Pin Package (PLCC-Top View)

4-101

inter

87C196KB/83C196KB/80C196KB

80-Pln Quad Flat Pack (EIAJ)
Con~octs
Facing Up

Contacts

Facing Down
PIN NO. 1 MARK

24
40

41
25

270918-4

Top View

1111111111111111
64
A01/P3.1
ADD/P3.0

Rii
ALE/AOV
INST
BUSWIOTH
CLKOUT

VSS

READY

T2RST/P2.4

BHE/WRH

59
58
57

WR/WRL

XTAL2

XTALI
10

T2CLK/P2.3

PWM/P2.5
P2.7/T2CAPTURE

.,--

Vpp

55
54

VSS

HSO.3

52
51
50
49
48
47

Vee

VSS

Vss

Vee

NMI

ACH3/PO.3

ACH1/PO.l

ACHO/pO.O

18
19

Pl.5

HSO.l

HSO.O

ACH7/PO.7

20
21

HSO.5/HSI.3

N.C.

ACH5/PO.5

ACH2/PO.2
ACH6/PO.6

Vss
HSO.2
P2.6/T2UP/ON
PI.7
PI.6

Vss

HSO.4/HSI.2

ACH4/PO.4

1111111111111111
270918-5

Figure 6. 80·Pin Quad Flat Pack (QFP)

4·102

Thermal Characteristics
Package
Type
LCC
PGA
PLCC
OFP

Bja.
28°C/W

28°C/W
35°C/W
85°C/W

BJc

3SC/W
3SC/W
12°C/W

PIN DESCRIPTIONS
Symbol

Name and Function

Vee

Main supply voltage (5V).

Vss

Digital circuit ground (OV). There are two Vss pins, both of which must be connected.

VREF

Reference voltage for the AID converter (5V). VREF is also the supply voltage to the analog
portion of the AID converter and the logic used to read Port O. Must be connected for AID
and Port 0 to function.

ANGND

Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·

Vpp

XTAL1

. Timing pin for the return from powerdown circuit. Connect this pin with a 1 ).LF capacitor to·
VSS. If this function is not used, connect to Vee. This pin is the programming voltage on the
EPROM device.
Input of the oscillator inverter and of the internal clock generator.

XTAL2

Output of the oscillator inverter.

CLKOUT

Output of the internal clock generator. The frequency of CLKOUT is 1kthe oscillator
frequency. It has a 50% duty cycle.

RESET

Reset input to the chip. Input low for at least 4 state times to reset the chip. The subsequent
low-to-high transition re- synchronizes CLKOUT and commences a 1O-state-time sequence in
which the PSW is cleared, a byte read from 2018H loads CCR, and a jump to location 2080H
is executed. Input high for normal operation. RESET has an internal pullup.

BUSWIDTH

Input for buswidth selection. If CGR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit
cycle occurs. If eCR bit 1 js a 0, the bus is always an a-bit bus.

NMI

A positive transition causes a vector through 203EH.

INST

Output high during an external memory read indicates the read is an instruction fetch. INST is
valid throughout the bus cycle. INST is activated only during external memory accesses and
output .Iow for a data fetch.

Input for memory select (External Access). EA equal to a TTL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA equal to a
TTL-low causes accesses to these locations to be directed to off-chip memory. EAmust be
lied low for the 80G196KB ROM less device.

ALE/ADV

Address Latch Enable or Address Valid output, as selected by CGR. Both pin options provide
a latch to demultiplex the address from the address/data bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ADV can be used as a chip select for external
memory. ALE/ ADV is activated only during external memory accesses.

Read signal output to external memory. RD is activated only during external memory reads.

WR/WRL

Write and Write Low output to external memory, as selected by the GGR. WR will go low for
. every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.

4-103

87C196KB/83C196KB/80C196KB

PIN DESCRIPTIONS (Continued)
Symbol

Name and Function

BHE/WRH

Bus High Enable or Write High output to external memory, as selected by the CCR. BHE = 0
selects the bank of memory that is connected to the high byte of the data bus. AO = 0
selects the bank of memory that is connected ,to the low byte of the data bus. Thus accesses
to a 16-bit wide memory can be to the low byte only (AO = 0, BHE = 1), to the high byte only
(AO = 1, BHE = 0), or both bytes (AO = 0, BHE = 0). If the WRH function is selected, the
pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is valid only
during 16-bit external memory write cycles.

READY

Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. If the pin is high, CPU operation continues in a'normal manner. If the pin is
low prior to the falling edge of CLKOUT, the memory controller goes into a wait mode until the
next positive transition in CLKOUT occurs with READY high. When the external memory is
not being used, READY has no effect. Internal control of the number of wait states inserted
into a bus cycle held not ready is available through configuration of CCA.

HSI

Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2, and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. The HSI pins are also used as
the SIDin Slave Programming Mode on the EPROM device.

HSO

Outputs from High Speed Output Unit, Six HSO pins are available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.

PortO

B-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter. These pins set the Programming Mode on the
EPROM device.

Port 1

B-bit quasi-bidirectional 110 port.

Port 2

B-bit multi-functional port. All of its pins are shared with other fUQctions in the BOC196KB.

Ports 3 and 4 B-bit bi-directionall/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups. Available as I/O only on the
ROM and EPROM devices.
HOLD

Bus Hold input requesting control of the bus. Enabled by setting WSR. 7.

HLDA

Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.

BREQ

Bus Request output activated when the bus controller has a pending external memory cyc;le.
Enabled bY setting WSA.7.

TxD

The TxD pin is used for serial port transmission in M<;>des 1,2, and 3. The TxD function is
enabled by setting lOCi 5. In mode 0 the pin is used as the serial clock output.

RxD

Serial Port Receive pin used for serial port reception. The RxD function is enabled by setting
SPCON.3. In mode 0 the pin functions as input or output data.

EXTINT

A rising edge on the EXTINT pin will generate an external interrupt. EXrlNT is selected as the
external interrupt source by setting IOC1.1 high.

T2CLK

The T2CLKpin is the Timer2 clock input or the serial port baud rate generator input.

T2RST

A riSing edge on the T2RST pin will reset Timer2. The external reset function is enabled by
setting IOCO.03 T2RST is enabled as the reset source by clearing IOCO.5.

PWM

Port 2.5 can be enabled as a PWM output by setting IOC1.0 The duty cycle of the PWM is
determined by th~ value loaded into the PWM-CONTROL register (17H).

T2UPDN

The T2UPDN pin controls the direction of Timer2 as an up or down counter. The Timer2 up/
down function is enabled by setting IOC2.1.

T2CAP

A rising edge on P2.7 will capture 'the value of Timer2 in the T2CAPTURE register (location
OCH in Window 15).
..

4-104

inter

87C 196KB/83C196KB/80C 196KB

NEW INSTRUCTIONS
The following five instructions have been added to the 8096BH instruction set for the 80C196KB.
PUSHA -

PUSHes the PSW, IMASK, IMASK1, and WSR
(Used instead of PUSHF when new interrupts and registers are used.)
assembly language format: PUSHA
object code format: < 1111 01 00 >
bytes: 1
states: on-chip stack: 12 .
off-chip stack: 18

POPA

POPs the PSW, IMASK, IMASK1, and WSR .
(Used instead of POPF when new interrupts and registers are used.)
assembly language format: POPA
object code format: < 1111.0101 >
bytes: 1
states: on-chip stack: 12
off-chip stack: 18

IDLPD

Sets the part into Idle or Powerdown Mode
assembly language format: IDLPD # key (key = 1 for Idle, key = 2 for Powerdown.)
object code format: < 1111011 0> < key>
bytes: 2
states: legal key: 8 '
illegal key: 25

CMPL

Compare 2 long direct values
assembly language format:
CMPL

DST SRC
Lreg, Lreg

object code format: < 11000101 > < src Lreg> < dst Lreg>
bytes: 3
states: 7
BMOV

Block move using 2 auto-incrementing pointers and a counter
assembly language format:

PTRS CNTREG
Lreg, wreg
BMOV
object code format: <11000001> < Lreg>
bytes: 3
states:

internal/internal: 8 per transfer + 6
external/internal: 11 per transfer + 6
external/external: 14 per transfer + 6

4-105

87C 196KB/83C196KB/80C 196KB

SFR OP1:RATION
All of the registers that were present on the 8096BH work the same way as they did, except that the baud rate
value is different. The new registers shown in the memory map control new functions. The most important new
register is the Window Select Register (WSR) which allows reading of the formerly write-only registers and
'
vice-versa.

USING THE ALTERNATE REGISTER WINDOW (WSR= 15)
I/O register expansion on the new CHMOS members of the MCS-96 family has been provided by making two
register windows available. Switching between these windows is done using the Window Select Register
(WSR). The PUSHA and POPA instructions can be used to push and pop the WSR and second interrupt mask
when entering or leaving interrupts, so it is easy to change between windows.
'
On the 80C196KB only Window 0 and Window 15 are active. Window 0 is a true superset of the standard
8096BH SFR space, while Window 15 allows the read-only registers to be written and write-only registers to be
read, The only major exception to this is the Timer2 register which is the Timer2 capture register in Window 15,
The writeable register for Timer2 is in Window O. There are also some minor changes and cautions. The
descriptions of the registers which have different functions in Window 15 than in Window 0 are listed below:
AD_COMMAND (02H)

Read the last written command

AD_RESULT (02H, 03H) - Write a value into the result register
HSLMODE (03H)

HSI_TIME (04H,05H)

- Write to FIFO Holding register

Read the value in HSLMODE

HSO_TIME (04H,05H)

Read the last value placed in the holding register

HSLSTATUS (06H)

Write to status bits but not to HSI pin bits. (Pin bits are 1,3,5,7).

HSO_COMMAND (06H) -

Read the last value placed in the holding register

SBUF(RX) (07H)

Write a value into the receive buffer
Read the last value written to the transmit buffer

SBUF(TX) (07H)

WATCHDOG(OAH)

Read the value in the upper byte of the WDT

TIMER1 (OAH,OBH)

Write a value to Timer1

TIMER2 (OCH,ODH)

Read/Write the Timer2 capture register.
Note that Timer2 read/write is done with WSR = O.

IOC2(OBI-j)

Last written value is readable, except bit 7 (note 1)

BAUDRATE (OEH)

No function, cannot be read

PQRTO (OEH)

No function, no output drivers on the pins. Register reserved.

PORT1

IOPORT1 cannot be read or written in Window 15. Register reserved.

SP_STAT (11H)

Set the status bits, TI and RI can be set, but it will not cause an interrupt

SP_CON (11 H)

Read the current control byte

10SO (15H)

Writing to this register controls the HSO pins. Bits 6 and 7 are inactive for writes.

lOCO (15H)

Last written value is readable, except bit 1 (note 1)

IOS1 (16H)

Writing to this register will set the status bits, but not cause interrupts. Bits 6 and
7 are not functional

IOC1 (16H)

Last written value is readable

IOS2 (17H)

Writing to this register will set the status bits, but not cause interrupts.

PWM_CONTROL (17H) -

Read the duty cycle value written to PWM_CONTROL

NOTE:
1. IOC2.7 (CAM CLEAR) and IOCO.1 (T2RST) are not latched and will read as a 1 (precharged bus).

Being able to write to the read-only registers and vice-versa provides a lot of flexibility. One of the most useful
advantages is the ability to set the timers and HSO lines for initial conditions other than zero.
Reserved registers may be used for testing or for future features. Do not write to these registers. Reads from
reserved registers will return indeterminate values.
4-106

inter

87C196KB/83C196KB/80C196KB

80C196KBINTERRUPTS

MEMORY MAP
OFFFFH

Number

4000H

INT15

Vector
Priority
Location

Source

EXTERNAL MEMORY OR 1/0

NMI

203EH

INT14

HSI FIFO Full

203CH

INT13

EXTINTPin

203AH

2040H

INT12

TIMER2 Overflow

2038H

2030H

INT11

TIMER2 Capture

2036H

INT10

4th Entry into HSI FI FO

2034H

INT09

2032H

2019H

INT08

2030H

2018H

SPECIAL Unimplemented Opcode

INTERNAL ROMIEPROM OR
EXTERNAL MEMORY
2080H
RESERVED
UPPER 8 INTERRUPT VECTORS
ROM/EPROM SECURITY KEY
2020H
RESERVED
CHIP CONFIGURATION BYTE
RESERVED
2014H
LOWER 8 INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
2000H
PORT 3AND PORT 4
1FFEH
EXTERNAL MEMORY OR 1/0
0100H
INTE'RNAL DATA MEMORY· REGISTER FILE
(STACK POINTER. RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY

19H
18H
17H

N/A

2010H

N/A

INT07

EXTINT

200EH

INT06

Serial Port

200CH

INT05

Software Timer

200AH

INT04

HSI.O Pin

2008H

INT03

High Speed Outputs

2.006H

HSI Data Available

2004H

INT01

AID Conversion Complete

2002H

INTOO

Timer Overflow

2000H

.INT02
OOOOH

19H

STACK POINTER

2012H

SPECIAL Trap

18H

STACK POINTER

'IOS2

17H

PWM CONTROL

16H

IOS1

16H

IOC1

15H

10SO

15H

lOCO

14H

'WSR

14H

'WSR

13H

'INT_MASK1

13H

'INT_MASK1

12H

'INT PEND 1

12H

'INT PEND 1

11H

'SP STAT

11H

'SP CON

10H

PORT2

10H

PORT2

OFH

PORn

OFH

PORn

RESERVED (1)
OFH

RESERVED (1)

OEH

PORTO

OEH

BAUD RATE

OEH

RESERVED (1)

ODH

TIMER2(HI)

ODH

TIMER2(HI)

ODH

'T2 CAPTURE (HI)

OCH

TIMER2 (LO)

OCH

TIMER2(LO)

OCH

'T2 CAPTURE (LO)

OBH

TIMER1 (HI)

OBH

'IOC2

OAH

TIMER1 (LO)

OAH

WATCHDOG

09H

INT_PENDING

09H

INTJENDING

08H

INT_MASK

08H

INT_MASK

07H

SBUF(RX)

07H

SBUF(TX)

06H

HSI_STATUS

06H

HSO_COMMAND

05H

HSLTIME(HI)

05H

HSO_TIME (HI)
HSO TIME (LO)

04H

HSI TIME (LO)

04H

03H

RESULT (HI)

03H

HSI MODE

02H

RESULT (LO)

02H

AD COMMAND

01H

ZERO REG (HI)

01H

ZERO REG (HI)

OOH

ZERO REG (LO)

OOH

ZERO REG (LO)

WHEN READ

WSR

WHENWRITIEN

4-107

WSR

OTHER SFRS IN WSR
15 BECOME READABLE
IF THEY WERE WRITABLE
IN WSR ~ 0 AND WRITABLE
IF THEY WERE READABLE
INWSR ~ 0

'NEW OR CHANGED
REGISTER FUNCTION FROM B096BH
NOTE:
1. Reserved registers should not be written.

intJ

87C196KB/83C196KB/80C196KB

SFR BIT SUMMARY'
AD_Command (02H)

AD-Result (LO) (02H)

A/D CHANNEL NUMBER
STATUS:
.
0;; A/D CURRENTLY IDLE
X
1 CONVERSION IN PROCESS

CHANNEL # SELECTS WHICH OF THE 8
ANALOG INPUT CHANNELS IS TO BE
<;:ONVERTED TO DIGITAL FORM.

3 fo- GO INDICATES'WHEN THE CONVERSION IS TO
BE INITIATED (GO 1 MEANS START NOW,
X
GO = 0 MEANS THE CONVERSION IS TO BE
~
INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).

I--

SET UPPER FOUR BITS TO ZERO

A/D RESULT:
LEAST SIc;lNIFICANT 2 BITS

f0X

270918-8

270918-7

WSR (14H)

Chip Configuration (2018H)

117161514131211 10 ICHIP CONFIGURATION REGISTER
121 = SFR's FUNCllON UKE SUPERSET OF 8096BH
14(111I21B) = PPW REGISTER
15(1111B)=EXCHANGE READ/WRITE REGISTERS
OTHER UNDEFINED, DO NOT USE

L.:~OWERDOWN

MODE ENABLE
BUS WIDTH SELECT
(16 - BIT BUS /8- BIT BUS)

'--WRITE STROBE MODE SELECT
(WR AND BHE/WRI AND WRH)

121

ADDRESS VALID STROBE SELECT
(ALE/ ADV)

121

(IRCO) lNTERNAL READY CONTROL

ENABLES HOLD/HOLDA

(IRC1)

121

MODE

270918-10

(LOCO) }
(LOC1) PROGRAM LOCK MODE
270918-9

HSI_Mode (03H)
17

6 15 14 13

HSLStatus (06H)

2 11 1 0 1

413

211 101

HSI.O STATUS

HSI.O MODE

HSI.1 MODE

HSI.1 STATUS

HSI.2 MODE

HSI.2 STATUS
HSI.3 STATUS

HSI.3 MODE

WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.
270918-12

WHERE EACH 2 - BIT MODE CONTROL FtELD
DEFINES ONE OF 4 POSSIBLE MODES:
00 II POSITIVE TRANSITIONS
01 EACH POSITIVE TRANSITION
10 EACH NEGATIVE TRANSITION
11 EVERY TRANSITION
(POSITIVE AND NEGATIVE)
270918-11

4-10.8

87C196KB/83C196KB/80C196KB

INT_PEND1/INT~MASK1

INT_PEND/INT_MASK (09H/08H)

(12H/13H)

TIMER OVERFLOW

TRANSMIT INTERRUPT

AID CONVERSION COMPLETE

RECEIVE INTERRUPT

HSI DATA AVAILABLE

HSIFIFO 4

HIGH SPEED OUTPUTS

TIMER 2 CAPTURE

HSI.O PIN

TIMER 2 OVERFLOW

SOFTWARE TIMER

EXTINT PIN

SERIAL PORT

HSI 1'11'0 FULL

EXTERNAL INTERRUPT (EXTINT
OR PO.7 PIN)
270918-13

NMI (SET TO 0)
270918-14

SP_CON(11H)
BIT. 1, BIT.O SPECIFY THE MODE
0.0 = MODE 0 1.0 = MODE 2
0.1 = MODE 1 1. 1 = MODE 3
W

R
I

X
X
RECEIVE OVERRUI'l ERROR

PEN ENABLE THE PARITY FUNCTION
REN ENABLES THE RECEIVE FUNCTION:

TRANSMITIER EMPTY

TB8PROGRAMS THE 9TH DATA BIT

FRAMII'lG ERROR

TRAI'lSMIT INDICATOR
RECEIVE INDICATOR
RECEIVE PARITY ERROR
270918-16

270918-15

HSO Command (OSH)
CHANNEL: 0-5 HSO.O - HSO.5 II'lDIVIDUALLY
BIT:

HSO.O AND HSO.l
7
HSO.2 AND HSO.3
8-B SOFTWARE TIMERS
C- 0 RESERVED FOR FUTURE USE
RESET TlMER2
START AID CONVERSIOI'l
INTERRUPT I NO INTERRUPT
SET I CLEAR
TIMER 2/TIMER 1
LOCK CAM
270918-17,

4-109

87C 196KB/83C,196KS/80C196KB

lOCO (15H)

10SO (15H)
HSO.O CURRENT STATE

HSI.O INPUT ENABLE I DISABLE·

HSO.l CURRENT STATE

TIMER 2 RESET EACH WRITE

HSO.2 CURRENT STATE

HSI.1 INPUT ENABLE I DISABLE

HSO.3 CURRENT STATE

TIMER 2 EXTERNAL RESET ENABLE I DISABLE

HSO.4 CURRENT STATE

H$I.2 INPUT ENABLE I DISABLE

HSO.5 CURRENT STATE

TIMER 2 RESET SOURCE HSI.O I T2RST

CAM QB HOLDING REGISTER IS FULL

HSI.3 INPUT ENABLE I DISABLE

HSO HOLDING REGISTER IS FULL

TIMER 2 CLOCK SOURCE HSI.l /. T2CLK

270918-18

270918-19

IOS1 (16H)

19C1 (16H)

SOFTWARE TIMER 0 EXPIRED

SELECT PWM I SELECT P2.5

SOFTWARE TIMER 1 EXPIRED

EXTERNAL INTERRUPT ACH7 I EXTINT

SOFTWARE TIMER 2 EXPIRED

TIMER 1 .oVERFLOW INTERRUPT ENABLE I DISABLE

SOFTWARE TIMER 3 EXPIRED

TIMER 2 OVERFLOW INTERRUPT ENABLE I DISABLE

TIMER 2 HAS OVERFLOW

HSO.4 OUTPUT ENABLE I DISABLE

TIMER 1 HAS OVERFLOW

SELECT TXD I SELECT P2.0

HSI FIFO IS FULL

HSO.5 OUTPUT ENABLE I DISABLE

HSI HOLDING REGISTER DATA AVAILABLE

HSI INTERRUPT
FIFO FU LL I ;oH""OL"D'"IN"'G""RE"'G'"IS"'T""ER"'L"OAOiD'"E"'D
270918-21

270918-20

IOS2(17H)

IOC2 (OBH)

INDICATES WHICH HSO EVENT OCCURED

ENABLE FAST INCREMENT OF T2

HSO.O

ENABLE T2 AS UP IDOWN COUNTER

HSO.l

ENABLE +2 PRESCALER ON PWM

HSO.2

X (SET TO l'J)

HSO.3

AID CLOCK PRESCALER ·DISABLE

HSO.4

T2 ALTERNATE INTERRUPT

HSO.5

ENABLE LOCKED CAM ENTRIES

T2RESET

CLEAR ENTIRE CAM

START AID

BOOOH

270918-23
270918-22

4·110

87C196KB/83C196KB/80C196KB

ELECTRICAL CHARACTERISTICS

NOTICE: This data sheet contains preliminary information on new products in prqduction. The specifications are subject to change without notice.

Absolute Maximum Ratings*
Ambient Temperature
Under Bias ...................... O°C to + 70°C
Storage Temperature .......... - 65°C to + 150°C
Voltage On Any Pin to Vss ........ -0.5V to + 7.0V

Power Dissipation .......................... 1.5W

Operating Conditions
Description

Min

Max

Units

Ambient Temperature Under Bias

+70

°C

Symbol
TA
Vce

Oig.ital Supply Voltage

4.50

5.50

VREF

Analog Supply Voltage

4.50

5.50

fose

Oscillator Frequency

3.5

MHz

NOTE:

ANGND and Vss should be nominally at the same potential.

D.C. Characteristics
Symbol

(Over Specified Operating Conditions)

Description

Min

Max

Units

-0.5

0.8

Test Conditions

VIL

Input Low Voltage

VIH

Input High Voltage (Note 1)

VIH1

Input High Voltage on XTAL 1

0.7 Vee

Vee + 0.5

VIH2

Input High Voltage on RESET

2.6

Vcc + 0.5

VOL

Output Low Voltage

0.3
0.45
1.5

V
V
V

IOL = 200 p,A
IOL = 3.2 rnA
IOL = 7 rnA

VOH,

Output High Voltage
(Standard Outputs)

Vee - 0.3
Vee - 0.7
Vee - 1.5

V
V
V

IOH = -200 p,A
IOH = -3.2mA
IOH = -7 rnA

VOH1

Output High Voltage
(Quasi-bidirectional Outputs)

Vee - 0.3
Vee - 0.7
Vee - 1.5

V
V
V

IOH= -10 p,A
IOH = -30 p,A
IOH = -60 p,A

III

Input Leakage Current (Std. Inputs)

0.2 Vee + 0.9 Vee + 0.5

±10

p,A

0< VIN < Vee - 0.3V

ILl1

Inpu~

Leakage Current (Port 0)

p,A

0< VIN < VREF

ITL

1 to 0 Transition Current (QBO Pins)

-650

p,A

VIN = 2.0V

IlL

Logical 0 Input Current (QBO Pins)

-50

p,A

VIN = 0.45V

11L1

Logical 0 InPllt Current in Reset (Note 2)
(ALE, RD, WR, BHE, INST, P2.0)

-1.2

rnA

VIN = 0.45 V

Hyst

Hysteresis on RESET Pin

(Note 3)

300

NOTES:

1. All pins except RESET and XTAL 1.
2. Holding these pins below VIH in Reset may cause the part to enter test modes.
3. Not guaranteed for the 87C196KB.
4-111

inter

87C196KB/83C196KB/80C196KB

D.C. Characteristics
Symbol

(Continued)

Description

Min

Typ(7)

Max

Units

rnA

Test Conditions
XTAL 1 = 12 MHz
Vcc = Vpp = VREF

Icc

Active Mode Current in Reset

IREF

AID Converter Reference Current

rnA

IIDLE

Idle Mode Current

rnA

ICCl

Active Mode Current

rnA

XTAL 1

Ipo

Powerdown Mode Current

!LA

Vcc = Vpp

RRST

Reset Pullup Resistor

Pin Capacitance (Any Pin to Vss)

.-.

50K

fTEST

5.5V

3.5 MHz

VREF

1.0 MHz

NOTES:
(Notes apply to all specifications)
1. QBD (Quasi-bidirectional) pinS Include Port 1, P2.6 and P2.7.
2. Standard Outputs include ADO-15, RD, WR, ALE, SHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0, and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
3. Standard Inputs include HSI pins, CDE, EA, READY, SUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3, and
T2RST IP2.4.
'
4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0,7V:
/
IOl on Output pins: 10 mA
IOH on quasi-bidirectional Pins: self limiting
IOH on Standard Output pins: lOrnA
5. Maximum current per bus pin (data and control) during normal operation is ± 3.2 rnA.
6. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
IOl: 29 mA
IOH is self limiting
HSO, P2.0, RXD, RESET IOl: 29 mA
IOH: 26 rnA
P2.5, P2,7, WR, SHE
IOl: 13 mA
IOH: 11 mA
ADO-AD15
IOl: 52 mA
IOH: 52 mA
RD, ALE, INST-CLKOUT IOl: 13 rnA
IOH: 13 mA
7, Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V,

60r-----,------,-----,
50
---],1''---..,../

ICC

rnA

Icc TYPICAL (7)

30 I-----+-----;,~____:.....'---__t

--±..-"""'---+-----=o~

IIDLE TYPICAL

O'--____-L-____-L..____- J
ICC Max = 3.88 x FREQ + 8.43
IIDLE Max = 1.65 x FREQ + 2.2

4MHz

8MHz

12MHz

FREQ

Figure 7. Icc and IIDLE vs Frequency

4-112

270918-24

87C196KB/83C196KB/SOC196KB

A.C. Characteristics
For use over specified operating conditions
Test Conditions: Capacitive load on ali pins = 100 pF, Rise and fali times = 10 ns, fosc = 12'MHz
The system must meet 'these specifications to work with the 80C196KB: (Note 1)
Symbol
TAVYV

hLYV

Description

Min

Max

, Units

Address Valid to Ready Setup
87C196KB10/83C196KB10
87C196KB12/83C196KB12/80C196KB

2Tose - 90
2Tose ,- 85

ns
ns

ALE Low to READY Setup
80C196KB
87C196KB10/83C196KB10
87C196KB12/83C196KB12

Tose - 65
Tose - 80
Tose - 72

ns
ns
ns

TYLYH

Non READY Time

TeLYX

READY Hold after CLKOUT Low

TLLYX

READY Hold after ALE Low

TAVGV
TLLGV

No upper limit

Tose - 30

(Note 2)

Tose - 15

2Tose - 40

(Note 2)

Address Valid to Buswidth Setup

210se - 85

ALE Low to Buswidth Setup
80C196KB
87C196KB/83C196KB

Tose - 60
Tosc - 70

ns
ns

TCLGX

Buswidth Hold after CLKOUT Low

TAVDV

Address Valid tq Input Data Valid
80C196KB
87C196KB10/83C196KB10
87C196KB12/83C196KB12

3Tosc - 60
3Tosc- 70
3Tosc - 67

ns
ns
ns

RD Active to Input Data Valid
87C196KB10/83C196KB10
87C196KB12/83C196KB12/80C196KB

Tose - 30
Tosc - 23

ns
ns

TCLDV

CLKOUT Low to Input Data Valid

Tosc - 50

TRHDZ

End of RD to Input Data Float

Tosc - 20

,Os

TRXDX '

Data Hold after RD Inactive

TRLDV

Notes-

(Note 3)

NOTES:
1. Customers whose applications require an 83C1'96KB to meet the 80C196KB specifications listed above should contlict an
Inte.l Field Sales Representative,
2. If max is exceeded, additional wait states will occur.
3. When using wait states, add 2TOSC x n, where n = number of wait states.

4-113

87C196KB/83C196KB/80C196KB

A.C. Characteristics
For use over specified operating conditions
Test Conditions: Capacitive load on all pins

The

80~196KB

100 pF, Rise and f~1I times ~ 10 ns, fosc

12 MHz

will meet these specifications: (Note 1)
Description

Min

Max

Units

Notes

Frequency on XTAL1
87C196KB10/83C196KB10
87C196KB12/83C196KB12/80C196KB

3.5
3.5

10
12

MHz
MHz

(Note 2)
(Note 2)

II FXTAL
87C196KB10/83C196KB10
87C196KB12/83C196KB12/80C196KB

100
83

286
286

ns
ns

TXHCH

XTAL 1 High to CLKOUT High or Low

110

TCLCL

CLKOUT Cycle Time

Symbol
FXTAL

Tosc

TCHCL

CLKOUT High Period

Tosc - 10

Tosc+ 10

TCLLH

CLKOUT Falling Edge to ALE Rising

-5

,ns

TLLCH

ALE Falling Edge to CLKOUT Rising

-15

TLHLH'

ALE Cycle Time

TLHLL.

ALE High Period

Tosc - 10

TAVLL

Address Setup to ALE Falling Edge

Tosc - 20

TLLAX

Address Hold after ALE Falling Edge

Tosc - 40

TLLRL

ALE Falling Edge to RD Falling Edge
80C196KB
87C196KS/83C196KS

Tosc - 30
Tosc - 40,

ns
ns

TRLCL

RD Low to CLKOUT Falling Edge

TRLRH

RD Low Period

TRHLH

RD Rising Edge to ALE ,Rising Edge

TRLAZ

RD Low to Address Float

TLLWL

ALE Falling Edge to WR Falling Edge

TCLWL

CLKOUT Low to WR Falling Edge

TQVWH

Data Stable to WR Rising Edge
87C196KB10/83C196KB10
87C196KB12/83C196KB12/80C196KB

(Note 3)

2Tosc

4Tosc
Tosc+ 10

(Note 5)

Tosc - 5

Tosc + 25

(Note 5)

Tosc

Tosc + 25

(Note 4)

ns
ns

Tosc - 10
0

ns
ns
ns

Tosc - 30
Tosc - 23

TCHWH

CLKOUT High to WR Rising Edge

-10

TWLWH

WR Low Period

Tosc - 30

Tosc +5

TWHQX

Data Hold after WR Rising Edge

Tosc - 10

TWHLH

WR Rising Edge to ALE Rising Edge

Tosc - 10

TWHBX

BHE, INST Hold after WR Rising Edge

Tosc -10

TRHBX

BHE, INST Hold after RD Rising Edge

Tose - 10

TWHAX

AD8-15 Hold afterWR Rising Edge

Tosc - 50

TRHAX

AD8-15 Hold after RD Rising Edge

Tosc - 25

(Note 5)

ns
ns

. (Note 5)

ns
Tosc + 15

(Note 4)

NOTES:
Tosc = 83.3 ns at 12 MHz; Tosc = 100 ns at 10 MHz.
"
.
1. Customers whose applications require an 83C196KB to meet the 80C196KB specifications listed above should contact an
Intel Field Sales Representative.
2. Testing performed at 3.5 MHz. However. the part is static by design and will typically operate below 1 Hz.
3. Typical specification, not guaranteed.
4. Assumingback-to-back "bus cycles.
5. When using wait states, add 2Tosc x n, where n = number of wait states,
4.114

inter

87C 196KB/83C 196KB/80C196KB

System Bus Timings

XTAL1

CLKOUT

ALE

BUS

--<.

ADDRESS OUT

•.

DATA OUT

I
BHE.INST

AD8-15

}~~(_ _AD_D_RE_S_S_ _ __

LtRHBX.
itWHBX

VALID

ADDRESS OUT
270918-25

4-115

87C196KB/83C196KB/80C196KB

READY Timings (One Waitstate)

XTAL1

CLKOUT

ALE

READY

_+_______ 1 - - - - -

tRLRH + 2Tose

tRLDV + 2Tose
1 - - - - - - - - - tAvDV + 2Tose

~--AD-DR-ES-S-OU-T--~)

---4--------

==='

-------1--..1

(~-M-TA--»-»)~»~-------I

_~~~~~~~~~~~~~~~~
~:.:~~-----tW-L-W-H
r l~.--....

...+-2-T-os-e-4
tQVWH + 2Tose

~--A-D-DR-E-SS-·-OU-T--.u~~(~------D-AT-A-O-U-T-----~X~__A_DD_R_ES_S__
I

270918-26

Buswidth Timings
XTAL1

'~::: ~ .~~~ ] r- .~:.,,) ~ ~ ~
BUSWIDTH _ _

-----~'----------------

I--- t AVGV ---l

BUS

~-----)~----------

270918-27

4-116

inter

87C196KB/83C196KB/80C196KB

HOLD/HLDA TIMINGS
Descrlptl~n

Symbol

Max

Min

HOLD Setup
80C196KB
87C196KB/83C196KB

THVCH

Units

Notes
1

ns.

75
85

TCLHAL

CLKOUT Low to HLDA Low

. -15

TCLBRL

CLKOUT Low to BREQ Low

-15

THALAZ

HLDA Low to Address Float
80C196KB
87C196KB/83C196KB

15
20

THALBZ

HLDA Low to BHE, INST, RD, WR Float

TCLHAH

CLKOUT Low to HLDA High

-15

ns
ns

TCLBRH

CLKOUT Low to BREQ High

-15

THAHAX

HLDA High to Address No Longer Float

-5

THAHBV

HLDA High to BHE, INST, RD, WR Valid

-20

TCLLH

CLKOUT Low to ALE High

ns
ns

-5

NOTE:
1. To guarantee recognition at next clock.

BUS

-<~

____
,,

BHE,INST

Rii,WR
,ACE

r---\.

.-'

1.~
. "'-_____
~.~

!-_ _ _tC_LL_H

~!-I----~.II

270918-28

4-117

inter

87C196KB/83C196KB/80C196KB

EXTERNAL CLOCK DRIVE
Parameter

'Symbol
1/TxLXL

TXLXL

Min

Max

Units

' Oscillator Frequency
80C196KB10
80C196KB12

3.5
3.5

10.0
12.0

MHz
MHz

Oscillator Frequency
80C196KB10
80C198KB12

100
83

286
286

ns
ns

TXHXX

High Time

TXLXX

Low Time

TXLXH

Rise Time

TXHXL

Fall Time

EXTERNAL CLOCK DRIVE WAVEFORMS

270918-29

, An external oscillator may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external Signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.

A.C. TESTING INPUT, OUTPUT WAVEFORM
2 . 4 = X 2.0"

;> TEST POINTS

0.45

0.8

2.0
0.8

FLOAT WAVEFORM

270918-30
A.C. Testing inputs are driven at 2,4V for a Logic "I" and 0,45V
for a LogIc "0" Tlmlng'measurements are made at 2.0V for a
Logic "I" and 0,8V for a Logic "0"

,
270918-31
For TImIng Purposes a Port Pin is no Longer Floating when a
100 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded VOHIVOL Level occurs
IOLIiOH = ±15 mAo

EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.

Conditions:

Signals:

'" High

- Address

~Low

- ALE/ADV

- BREO

Rti5A

- Valid

- DATA OUT

,- CLKOUT

- RD

- Floating

- DATA IN

- Wi=i/WRH/'fRL

G
H

- Buswidth
- HOiJj
\

- XTAL1

- READY

No Longer Valid

(

. 4-118

87C196KB/83C196KB/80C196KB

EPROM SPECIFICATIONS
A.C. EPROM Programming Characteristics
Operating Conditions: Load Capacitance = 150 pF, TA = +25°C ±5°C, Vee, VREF = 5V, Vss, ANGND =
OV, Vpp = 12.75V ± 0.25V, EA = 12.75V ± 0.25

Symbol

Description

Min

TSHLL

Reset High to First PALE Low

TLLLH

PALE Pulse Width

Units

Max

1100

Tosc

TAVLL

Address Setup Time

Tosc

TLLAX

Address Hold Time

TLLVL

PALE Low to PVER Low

Tosc

PROG Low to Word Dump Valid

Tosc

Word Dump Data Hold

Tosc

TpLDV
. TpHDX

Tosc

TDVPL

Data Setup Time

Tosc

TpLDX

Data Hold Time

Tosc

TpLPH

PROG Pulse Width

Tosc

TPHLL

PROG High to Next PALE Low

120

Tosc

TLHPL

PALE High to PROG Low

220

Tosc

TpHPL

PROG High to Next PROG Low

120

Tosc

TpHIL

PROG High to AINC Low

Tosc

TILIH

AINC Pulse Width

Tosc

TILVH

PVER Hold after AINC Low

Tosc

TILPL

AINC Low to PROG Low

170

Tosc

TPHVL

PROG High to PVER Low

NOTE:

1. Run Time Programming is, <;lone with Fosc = 6.0 MHz to 12.0 MHz, VREF =: 5V ± 0.65V. TA =
Vpp = j'2.75V. For run-time programming over a full operating range, contact the factory.

TOsc

+ 25'e to ±5'e

and

D.C. EPROM Programming Characteristics
Symbol

Description

Ipp

Vpp Supply Current (When Programming)

NOTE:

Vpp must be within 1V of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground or \ISS while
Vee> 4.5V.

4·119

intJ·

81C196KB/83C196KB/80C196KB.

. EPROM PROGRAMMING WAVEFORMS
StAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE

PORTS
3/4

--t--~~~~~~

PVER

270918-32

SLAVE PROGRAM MODE IN WORD ,DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT·

~',

270918-33

SLAVE PROGRAMMiNG MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT

pbRTS
3/4

(

ACOR/COMMAND

>--<

ADDR
DATA

AODR+ 2

)>--------«

DATA

>--

PVER

tPHIL

270918-34

4-120

inter

87C196KB/83C196KB/80C196KB

A:C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE

Symbol

. Parameter

Min

TXLXL

Serial Port Clock Period (BRR 2 8002H)

TXLXH

Serial Port Clock Falling Edge
to 8ising Edge (BRR 2 13002H) ,

TXLXL

Serial Port Clock Period (BRR = 8001 H)

TXLXH

Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)

TQVXH

Max

Units

6 Tose

ns.

4 Tose ±50

4 Tose

2 Tose ±50

Output Data Setup to Clock Rising Edge

2 Tose -50

TXHQX

Output Data Hold after Clock Rising Edge

2 Tose

TXHQV

Next Output Data Valid after Clock Rising Edge

TDVXH

Input Data Setup to Clock RiSing Edge

TXHDX

Input Data Hold after Clock Rising Edge

TXHQZ

Last Clock Rising to Output Float

~50

ns
2 Tosc +50

Tosc +50

ns
1 Tose

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE

270918-35

4-121

87C196KB/83C196,KB/80C196KB

A TO D CHARACTERISTICS
There are two modes of AID operation: with or without clock prescaler. The speed of the AID converter
. can be adjusted by. setting a clock prescaler on or '
off. At high frequencies more time is needed for the
comparator to settle. The maximum frequency with
the clock prescaler disabled is 8 MHz. The conversion times with the prescaler turned on or off is
shown in the table below.

,stability of ,V REF .. VREF must ,be ,close to Vee sinc~ it
supplies both the resistor ladder and the digital section of the converter.

AID CONVERTER SPECIFICATIONS
The specifications given below assume adherence
to the Operating Conditions section of this data
sheet. Testing is performeci with VREF = 5.12V.,

The converter is ratiometric, so the absolute
accuracy is, directly dependent on the accuracy and

Clock Prescaler On
IOC2.4 = 0

Clock Prescaler Off ,
10C2.4 = 1

158 States
26.33 fJos @ 12 MHz

91 States
22.75 fJos @ 8 MHz

Parameter

Typle&I(1)

Minimum

Maximum

Units·

512
9

1024
10

Levels
Bits

±4

LSBs

Resolution
Absolute Error

0.25 :to.50

Full Scale Error

Notes

LSBs

-0.25 ±0.50

Zero Offset Error

1.5 ±2.5

Non-Linearity Error
Differential Non-Linearity Error
Channel-to~Channel

Matching

±0.1

LSBs

±4

LsBs

>-1

LsBs

±1

LSBs

Repeatability

±0,25

LsBs

Temperature Coefficients:
. Offset
Full Scale
Differentilil Non-Linearity

0.009
0.009
0.009

LsB/oC
,LsBI"C
LsBrC,

-60

Off Isolation

2,3

Feedthrough

-60

Vee Power Supply Rejecti~n

-60

Input Resistance

D.C. Input Leakage

3.0

fJoA

Sample Time: Prescaler On
Prescaler Off

15
8'

States
States

Input Capacitance

NOTES:
·An "LSB", as used here, has a value

ot approxh:nately 5 mV. '

1. Typical values are expect~d tor most devices at 25°e but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer Break-Betore-Make Guaranteed.
4. One state = 167 ns at 12 MHz, 250 ns at 8 MHz.

, 4-122

,4
4

inter

87C196KB/83C196KB/80C196KB

IDEAL CHARACTERISTIC-A characteristic with
its first code transition at VIN = 0.5 LSB, its last
code transition at VIN = (VR6F - 1.5 LS6) and all
code widths equal to one LSB.

AID GLOSSARY OF TERMS
ABSOLUTE ERROR-The maximum difference between corresponding actual and ideal code transitions. Absolute Error accounts for all deviations of
an actual converter from an ideal converter.
ACTUAL CHARACTERISTIC-The characteristic
of an actual converter. The characteristic of a given
converter may vary over temperature, supply voltage, and frequency conditions. An actual characteristic rarely has ideal first and last transition locations
or ideal code widths. It may even vary over multiple
conversions under the same conditions.
BREAK-BEFORE-MAKE-The property of multiplexer which guarantees that a previously selected
channel will be deselected before a new channel is
selected (e.g., the converter will not short inputs
together).
CHANNEL-TO-CHANNEL MATCHING-The, difference between corresponding code transitions of
actual characteristics taken from different channels
under the same temperature, voltage and frequency
conditions.
CHARACTERISTIC-A graph of input voltage
versus the resultant output code for an AID converter. It describes the transfer function of the AID converter.
CODE-The digital value output by the converter.

INPUT RESISTANCE-The effective series resistance from the analog input pin to the sample capacitor.
LSB-Least Significant Bit: The voltage corresponding to the full scale voltage divided by 2n,
where n is the number of bits of resolution of the
converter. For an 8-bit converter with a reference
voltage of 5.12V, one LSB is 20 mV. Note. that this is
different than digital LS6s, since an uncertainty of
two LSB, when referring to an AID converter, equals
40 mY. (This has been confused with an uncertainty
of two digital bits, which would mean four counts, or
80 mV.)
NON-LINEARITY-The maximum deviation of code
transitions of the terminal based characteristic from
the corresponding code transitions of the ideal characteristic.
OFF-ISOLATION-Attenuation of a voltage applied
on a deselected channel of the AID converter. (Also
referred to as Crosstalk.)
REPEATABILITY-The difference betweencorresponding code transitions from different actual characteristics taken from the same converter on the
same channel at the same temperature, voltage and
frequency conditions.

CODE TRANSITION-The point at which the converter changes from an output code of Q, to a code
of Q + 1. The input voltage corresponding to a code
transition is defined to be that voltage which is
equally likely to produce either of two adjacent
codes.

RESOLUTION-The number of input voltage levels
that the converter can unambiguously distinguish
between. Also defines the number of useful bits of
information which the converter can return.

CODE WIDTH-The voltage correspondin,g to the
difference between two adjacent code transitions.

SAMPLE TIME-Begins when the sample capaCitor
is attached to a selected channel and ends when
the sample capacitor is disconnected from the selected, channel.

D.C. INPUT LEAKAGE-leakage current to ground
from an analog input pin.
DIFFERENTIAL NON-LiNEARITY-The difference
between the ideal and actual code widths of the terminal based characteristic.

TEMPERATURE COEFFICIENTS-Change in the
stated variable per degree centigrade temperature
change. Temperature coefficients are added to the
typical values of a specification to see the effect of
temperature drift.

FEEDTHROUGH-Attenuation of a voltage applied
on the selected channel of the AID Converter after
the sample window closes.

TERMINAL BASED CHARACTERISTIC-An actual
characteristic which has been rotated and translated
to remove zero offset and full scale error.

FULL SCALE ERROR-The difference between the
expected and actual input voltage corresponding to
the full scale code transition.

Vee REJECTION-Attenuation of noise on the Vee
line to the AID converter.
ZERO OFFSET-The difference between the expected and actual input voltage corresponding to
the first code transition.
.

4-123

87C 196KB/83C196KB/80C196KB

80C196KB FUNCTIONA,L DEVIATIONS
The aOC196KB has the following problems.
1. The DJNZW instruction is not guaranteed to be
functional. The instruction, if encountered, will not
. cause an unimplemented opcode interrupt. (The
opcode for DJNZW is OE1 Hex.) The DJNZ (byte)
instruction works correctly and should be used instead.

2. The CDE function is not guaranteed to work. The
CDE pin must be directly connected to Vss.
3. The HSI unit has two errata: one dealing with resolution and the other with first entries into the
FIFO.
The HSI resolution is 9 states instead of a states:
Events on the same line may be lost if they occur
faster than once every 9 state times.
There is a mismatch between the 9 s~atetime HSI
resolution and the a state time timer. This causes
one time value to be unused every 9 timer counts.
Events may receive a time-tag one count later
than expected because of this "skipped" time value.
If the first two events into an empty FIFO (not
including the Holding Register) occur in the same
internal phase, both are recorded with one timetag. Otherwise, if the second event occurs within
9 states after the first, its time-tag is one count
later than the first's. If this is the "skipped" time
value, the second event's time-tag is 2 counts later than the first's.
If the FIFO and Holding Register are empty, the
first event will· transfer into the Holding Register
after a state times, leaving the FIFO empty again.
If the second event occurs after this time, it will
act as a new first event into an empty FIF~.
4. The serial port Framing Error flag fails to indicate
.an error if the bit preceding the stop bit is a 1. This
is the case in both the a-bit and 9-bit modes.
False framing errors are never generated.

DIFFERENCES BETWEEN THE'
80C196KA AND THE 80C196KB
The aXC196KB is Identical to aXC19'6KA except for
the following differences.
1. ALE is high after reset on the aOC19GKB instead
of low as on the aOC196KA.
2. The DJNZW instruction is not guaranteed to work
on the aOC196KB.
3. The RQ[iJ/HLDA bus protocol is available on the
aOC196KB.

CONVERTING FROM OTHER 8096BH
FAMILY PRODUCTS TO THE
80C196KB
The following list of suggestions for designing an
a09XBH system will yield a design that is easily converted to the aOC196KB.
1. Do not base critical timing loops on instruction or
peripheral execution times.
2. ·Use equate statements to set all timing parameters, including the baud rate.
3. Do not base hardware timings on CLKOUT or
XTAL1. The timings of the aOC196KB are different than those of the 8X9XBH, but they will function with standard ROM/EPROMlPeriphera:i type
memory systems.
4. Make sure all inputs are tied hjgh or low and not
left floating.
5. Indexed and indirect operations relative to the
stack pOinter (SP) work differently on the
aOC196KB than on the a096BH. On the a096BH,
the address is calculated based on the un-updated version of the stack pointer. The aOC196KB
uses the updated version. The offset for POP[SPj
and POP nn[SPj instructions may need to be,
changed .by a count of 2.
6. The VPD pin On the a096BH has changed to a
Vss pin on the aOC196KB.

4-124

87C196KB/83C196KB/80C196KB

DATA SHEET REVISION HISTORY
This data sheet is valid for the CPU and ROM devices which have a "B" suffix on th~ topside tracking number.
The 87C196 mayor may not have the suffix on the topside number.
This is a new data sheet that integrates the 87C196KB (order number 270590-003) and the 83C196KBI
80C196KB (order number 270634-003) data sheets.
The following differences exist between this data sheet (-001) and each of the above mentioned data sheets.
1. The status of the data ,sheet was upgraded from ADVANCE INFORMATION to PRELIMINARY.
2. The warning about the ABSOLUTE MAXIMUM RATINGS was reworded and a notice of disclaimer was
added to the electrical specific,'"
III

x x

......
~ I~I~
","-~
"< 'Iii!
IX
u
~ ~ ~ 'In
.. 0:

'"
t::..

.:'i
0:

l!'i
>-

N
0.

Figure. 3. 68-Pin Package (PLCC-Top View)
Thermal Characteristics

4-129

270909-2

intef "

87C196KB16

PIN DESCRIPTIONS
I

Symbol

Name and,Function

Vee

Main supply voltage (5V).

Vss

Digital circuit ground (OV). There are three Vss pins, all of them must be connected.

VREF

ANGND

Reference ground for the AID converter. Must be held at nominally the same potential as
Vss·

Vpp

Programming voltage. Also timing pin for the return from power down circuit. Connect this pin
with a 1 /LF capacitor to Vss. If this function is not used, connect to Vee.

XTAL1

Input of the oscillator inverter and of the internal clock generator.

XTAL2

Output of the oscillator inverter.

CLKOUT

Output of the internal clock generator. The frequency of CLKOUT is% the oscillator
frequency. It has a 50% duty cycle.

RESET

Reset input to the chip. Input low for at least 4 state times to reset the chip. The subsequent
low-to-high transition re- synchronizes CLKOUT and commences a 10-state-time sequence in
which the PSW is cleared, a byte read from 2018H loads CCR, and a jump to location 2080H
is executed. Input high for normal operation. RESET has an internal pullup.

BUSWIDTH

Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is ai, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit
cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.

NMI

A positive transition causes a vector through 203EH.

INST

Output high during an external memory read indicates the read is an instruction fetch and
output low indicates a data fetch. INST is valid throughout the bus cycle. INST is activated
only during external memory accesses.

Input for memory select (External Access). EA equal to a TIL-high causes memory accesses
to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM. EA equal to a
TTL-low causes accesses to these locations to be directed to off-chip memory.

ALE/ADV

Address Latch Enable or Address Valid output, as selected by CCA. Both pin options provide
a latch to demultiplex the address from the address/data ,bus. When the pin is ADV, it goes
inactive high at the end of the bus cycle. ADV can be used as a chip select for external
memory. ALE/ ADV is activated only during external memory accesses.

Read signal output to external memory. RD is activated only during external memory reads.

WR/WRL

Write and Write Low output to external memory, as selected by the CCA. WR will go low for
every external write, while WRL will go low only for external writes where an even byte is
being written. WR/WRL is activated only during external memory writes.

BHE/WRH

Bus High Enable or Write High output to external memory, as selected by the CCR. BHE = 0
selects the bank of memory that is connected to the high byte of th,e data bus. AO = 0
selects the bank of memory that is connected to the low byte of the data bus. Thus accesses
to a i6-bit wide memory can be to the low byte only (AO = 0, BHE = 1), to the high byte only
(AO = 1, BHE = 0), or both bytes (AO = 0, BHE = 0). If the WRH function is selected, the
pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is valid only
during 16-bit external memory write cycles.

4-130

infef

87C196KB16

PIN DESCRIPTIONS (Continued)
Symbol
READY

Name and Function
Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is
low prior to the faning edge of CLKOUT, the memory cory troller goes into a wait mode until the
hext positive transition in CLKOUT occurs with READY high. When the external memory is
not being used, READY has no effect. Internal control of the number of wait states inserted
into a bus cycle (held not ready) is available through configuration of CCR,.

HSI

Inputs to High Speed Input Unit. Four HSI pins are availa9le: HSI.O, HSI.1, HSI.2, and HSI.3.
" Two of them (HSI.2 and HSI.3) ar~ shared with the HSO Unit. The HSI pins are also used as
the SID in Slave Programming Mode.

HSO

Outputs from High Speed Output Unit. Six HSO pins are ,available: HSO.O, HSO.1, HSO.2,
HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO,5) are shared with the HSI Unit.

PortO

8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as
analog inputs to the on-Chip AID converter. These pins set the Programr:ning Mode.

Port 1

8-bit quasi-bidirectional I/O port. These pins are shared with HOLD, HLDA and BREQ.

Port 2

8-bit multi-functional'port. All of its pins are shared with other functions in the 87C196KB.

Ports3-and4 8-bit bi-directionalllO ports with open drain'outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pull ups.
HOLD

Bus Hold input requesting control of the bus. Enabled by setting WSR. 7.

HLDA

Bus Hold acknowledge output indicating release of the bus. Enabled by setting WSR.7.

BREQ

Bus Request outPl,lt activated when the bus controller has a pe.nding external memory cycle.
Enabled by setting WSR. 7.

TxD

The TxD pin is used for serial port transmission in Modes 1, 2, a,nd 3, The TxD function is
enabled by setting IOC1 ,5. In mode 0 the pin is used as the serial clock output.

RxD

.Serial Port Receive pin used for serial port reception. The RxD function is enabled by setting
SPCON.3. In mode 0 the pin iunction~ as input or O!)tput data.

EXTINT

A rising edge on the EXTINT pin will generate an external interrupt. EXTINT is selected as the
external interrupt source by setting IOC1. thigh. ,

T2CLK

The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.

T2RST

A rising edge on the T2RST pin will reset Timer2. The external reset function is enabled by
setting IOCO.3. T2RST is enabled as the reset source by clearing IOCO.5.

4-131

inter,

87C1'96KB16 '

PIN DESCRIPTIONS (Continued)
Symbol

1", "

Name and Function

PWM

Port 2.5 can be enabied as a PWM output by setting IOC1.0. The duty cycle of 'the PWM is
determined by the vallte loaded into the PWM-CONTROL register (17H).

T2UPDN

The T2UPDN pin controls the direction of Timer2 as an up or down counter. The Timer2
up/Qown function is enabled by setting IOC2.1.
/

T2CAP

A rising edge on P2.7 will capture the value of Timer2 in the T2CAPTURE register (location
OCH in Window 15).
'
,

PMODE

Programming Mode Select. Determines the EPROM programming algorithm that is
performed. PMqDE is sampled after a chip reset and should be static while the part is
operating.

SID

Slave 10 Number. Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement. For example, if gang programming in the Slave
Programming Mode, the slave with SID = 001 will use Port 3.1 to signal correct or incorrect
program verification.

pALE

' Programming ALE Input. Accepted by the 87C196KB when it is in SI~lVe Programming Mode.
Used to indicate that Ports 3 and 4 oontain a command/address. '

Programming. Falling edge indicates valid data on PBUS and the beginning of progfamming.
Rising edge indicates end of programming.

PACT

Programming Active. Used in the Auto Programming Mode to indicate when programming
activity is complete.

PVAL

Program Valid. This signal indicates the success or failure of programming in the Auto
Programming Mode. A zero indicates successful programming.

PVER

Program Verification. Used in Slave Programming and Auto CLB Programming Modes. Signal
is low after rising edge of PROG if the programming was not successful.

AING

Auto Increment. Active low signal indicates that the auto increment mode is enabled. Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.

PORTS

Address/CommandlData Bus. Used to pass commands, addresses, and data to and from
slave mode 87C196KBs. Used by chips in Auto Programming Mode to pass command,
addresses and data to slaves. Also used in the Auto Programming Mode as a regular system
bus to access external memory. Should have pull ups to Vee (15 kO).

4-132

inter

87C196KB16

NEW INSTRUCTIONS
The following five instructions have been added to the 8096BH instruction set for the 87C196KB.
PUSHA -

PUSHes the PSW, IMASK, IMASK1, and WSR
(Used instead of PUSHF when new interrupts and registers are used.)
assembly language format: PUSHA
object code format: <11110100>
bytes: 1
states: on-chip stack: 12
off-chip stack: 18

POPA

POPs the PSW, IMASK, IMASK1, and WSR
(Used instead of POPF when new interrupts and registers are used.)
assembly language format: POPA
object code format: < 11110101 >
bytes: 1
states: on-chip stack: 12
off-chip stack: 18

IDLPD

Sets the part into Idle or Powerdown Mode
assembly language format: IDLPD # key (key= 1 for Idle, key = 2 for Powerdown.)
object code format: <11110110>
bytes: 2
states: legal key: 8
illegal key: 25

CMPL

Compare 2 long direct values
assembly language format:
CMPL

DST
Lreg,

SRC
Lreg

object code format: < 11 000101 > < src Lreg> < dst Lreg>
bytes:

states: 7
BMOV

Block move using 2 auto-incrementing pointers and a counter
assembly language format:
BMOV

,PTRS
Lreg,

CNTREG
wreg

object code format: < 11 000001 > < wreg > < Lreg >
bytes: 3
states:

internal/internal: 8 per transfer + 6
external/internal: 11 per transfer + 6
external/external: 14 per transfer + 6

4-133

inter

87C196KB16

USING THE ALTERNATE REGISTER WINDOW (WSR= 15)
I/O register,expansion on the new CHMOS members of the MCS-96 family has been provided by making three
register windows available. switching between these windows is done using the Window Select Register
(WSR). The PUSHA and POPA instructions can be used to push and pop the WSR and second interrupt mask
when entering or leaving interrupts, so it is easy to change between windows.
On the 87C196KB only Window 0, Window 14 and Window 15 are active. Window 0 is a true superset of the
standard 8096EiH SFR space, while Window 15 allows the read-only registers to be written and write-only
registers to be read. The only major exception to this is the Timer2 register which is the Timer2 capture register
in Window 15. The writeable register for Timer2 is in Window O. There are also some minor changes and
cautions. Window 14 contains the Programmable Pulse Width register (PPW) at location 14H. The descriptions
of the registers which have different functions in Window 15 than in Window 0 are listed below,:
AD_COMMAND (02H)

Read the last written command

AD_RESULT (02H, 03H) - Write a value into the result register
HSI_MODE (03H)

Read the value in HSLMODE

HSI_TIME (04H,05H)

Write'to FIFO Holding register

HSO_TIME (04H,05H)

Read the last value placed in the holding register

HSI_STATUS (06H)

Write to status bits but not to HSI pin bits. (Pin bits are 1,3,5,7).

HSO_COMMAND (06H) -

Read the last value placed in the holding register

SBUF(RX) (07H)

Write a value into the receive buffer

SBUF(TX) (07H)

Read the last value written to the transmit buffer

WATCHDOG(OAH)

Read the value in the upper byte of the WDT

TIMER1 (OAH,OBH)

Write a value to Timer1

, TIMER2 (OCH,ODH)

Read/Write the Timer2 capture register.
Note that Timer2 read/write is done with WSR = o.

IOC2 (OBH)

Last written value is readable, except bit 7 (note 1)

BAUDRATE (OEH)

No function, cannot be read

PORTO (OEH)

No function, no output drivers on the pins. Registers reserved.

PORT1 (OFH)
SP_STAT (11 H)

IOPORT1 cannot be read or written in Window 15. Register reserved.

8et the status bits, TI and RI can be set, but it will not cause an interrupt

SP_CON (11 H)

Read the current control byte

1080 (15H)

Writing to this register controls the HSO pins. Bits 6 and 7 are inactive for writes.

lOCO (15H)

Last written value is readable, except bit 1 (note 1)

IOS1 (16H)

Writing to this register will set the status bits, but not cause interrupts. Bits 6 and
.
7 are, not functional'

IOC1 (16H)

Last written value is readable

1082 (17H)

Writing to this register will set the status bits, but not cause interrupts.

PWM_CONTROL (17H) -

Read the duty cycle value written to PWM_CONTROL

NOTE:
1. IOC2.7 (CAM CLEAR) and IOCO.1 (T2RST) are not latched and will read as a 1 (precharged bus) .
Being able to write to the read-only registers and vice-versa provides a lot of flexibility. One of the most useful
advantages is the ability to set the timers and HSO lines for initial conditions other than ,zero.
Reserved registers may be used for testing or future features. Do not write to these registers. Reads from
reserved registers will return indeterminate values.

4-134

inter

87C196KB16

87C196KBINTERRUPTS

MEMORY MAP

Vector
Priority
Location

Source

OFFFFH

Number

4000H

INT15

NMI

203FH

INT14

HSI FIFO Full

203CH

INT13

EXTINTPin

203AH

13
12

EXTERNAL MEMORY OR 1/0
INTERNAL ROMIEPROM OR
EXTERNAL MEMORY
20S0H
RESERVED
2040H

INT12

TIMER2 Overflow

2038H

2030H

INT11

TIMER2 Capture

2036H

INT10

4th Entry into HSI FIFO

2034H

INT09

2032H

2030H

2012H

N/A

SPECIAL Trap

2010H

N/A

INT07

EXTINT

200EH

INT06

Serial Port

200CH

INT05

Software Timer

200AH

INT04

HSI.O Pin

2008H

INT03

High Speed Outputs

2006H

INT02

HSI Data Available

2004H

UPPER S INTERRUPT VECTORS
ROMIEPROM SECURITY KEY
2020H
RESERVED
2019H

INT08

201SH

SPECIAL Unimplemented Opcode

CHIP CONFIGURATION BYTE
RESERVED
2014H
LOWER SINTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
2000H
PORT 3 AND PORT 4
lFFEH
EXTERNAL MEMORY OR 1/0
0100H
INTERNAL DATA MEMORY - REGISTER FILE
(STACK POINTER, RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY

19H

OOOOH

19H

STACK POINTER

INT01

AID Conversion Complete

2002H

INTOO

Timer Overflow

2000H

STACK POINTER

ISH

ISH
17H

'IOS2

17H

PWM_CONTROL

16H

10SI

16H

lOCI

15H

10SO

15H

lOCO

14H

'WSR

14H

'WSR

13H

'INT_MASKI

13H

'INT_MASKI

12H

'INT_PENDI

12H

'INT_PENDI

llH

'SP~STAT

llH

'SP_CON

10H

PORT2

10H

PORT2

10H

RESERVED(1)

OFH

PORTI

OFH

PORT1

OFH

RESERVED(1 )

OEH

PORTO

OEH

BAUD RATE

OEH

RESERVED(1)

ODH

TIMER2(HI)

ODH

TIMER2(HI)

ODH

'T2 CAPTURE (HI)

OCH

TIMER2 (LO)

OCH

TIMER2 (LO)

OCH

'T2 CAPTURE (LO)

OBH

TIMER 1 (HI)

OBH

'IOC2

OAH

TIMER 1 (LO)

OAH

WATCHDOG

09H

INT_PEND

09H

INT

PEND

OSH

INT_MASK

OSH

INT

MASK

07H

SBUF(RX)

07H

SBUF(TX)

06H

HSI

STATUS

06H

HSO COMMAND

05H

HSI

TIME (HI)

05H

HSO_TIME (HI)

04H

HSI

TIME (LO)

04H

HSO_TIME (LO)

03H

AD_RESULT (HI)

03H

HSLMODE

02H

AD_RESULT (LO)

02H

AD_COMMAND

01H

ZERO REG (HI)

01H

ZERO REG (HI)

OOH

ZERO REG (LO)

OOH

ZERO REG (LO)

WHEN READ

WSR

WHENWRITIEN

4-135

,OTHER SFRS IN WSR 15 BECOME
READABLE.
IF THEY WERE WRITABLE
IN WSR ~ OANDWRITABLE IFTHEY
WERE READABLE IN WSR ~ 0

PPW
WSR

'NEW OR CHANGED REGISTER
FUNCTION FROM S096BH
NOTE:
1. RESERVED REGISTERS SHOULD
Nor BE WRITIEN

inter

87C196KB16

SFR BIT SUMMARY
... AD_RESULT (LO) {02H}

~l-

A/D CHANNEL NUMBER
STATUS:
0= A/D CURRENTLY ID.LE
1 = CONVERSION IN PROCESS

3 -

GO INDICATES WHEN THE CONVERSION IS TO
BE INITIATED (GO = 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).

CHANNEL # SELECTS WHICH OF THE 8
ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL FORM.

A/D RESULT:
LEAST SIGNIFICANT 2 BITS

SET UPPER FOUR BITS TO ZERO

270909-4

270909-5

CCR {2018H}

WSR (14H)

IL7 lsJ 5141 3J 2111 0 ICHIP CONFIGURATION REGISTER

L.:

0 = SFR's FUNCTION LIKE SUPERSET OF 809SBH
14 (111 OB) = PPW REGISTER
15 (1111 B) = EXCHANGE. READ/WRITE REGISTERS
OTHER
UNDEFINED, 00 NOT USE

POWERDOWN MODE ENABLE
BUS WIDTH SELECT
(lS - BIT BUS /8- BIT BUS)

-WRITE STROBE MODE SELECT
(WR AND BHE/WRL AND WRH)

o
o

ADDRESS VALID STROBE SELECT
(ALE/ ADV)

(IRCO) }'NTERNAL READY CONTROL
(IRC1)

ENABLES HOLD/HOLDA

MODE

270909-7

(LOCO) }
(LOC1) PROGRAM LOCK MODE
270909-6

HSI_STATUS {OSH}

sI5

41 3 12 I

I
' - - - - - - - - H S I . 2 MODE

I
HSI.O STATUS
HSI.1 STATUS.
HSI.2 STATUS

' - - - - - - - - - - H S I . 3 MODE

HSI.3 STATUS

WHERE EACH 2 - BIT MODE CONTROL FIELD
DEFINES ONE OF 4 POSSIBLE MODES:
00
01
10
11

1 I 0

WHERE FOR EACH 2 - BIT STATUS .FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
. OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.
270909-9

8 POSITIVE TRANSITIONS
EACH POSITIVE TRANSITION
EACH NEGATIVE TRANSITION
EVERY TRANSITION
(POSITIVE AND NEGATIVE)
270909-8.

4-136

87C196KB16

SFR BIT SUMMARY
lOCO (15H)

IOSO(15H)
HSO.O CURRENT STATE

HSI.O INPUT ENABLE I DISABLE

HSO.l CURRENT STATE

TIMER 2 RESET EACH WRITE

HSO.2 CURRENT STATE

HSI.l INPUT ENABLE I DISABLE

HSO.3 CURRENT STATE

TIMER 2 EXTERNAL RESET ENABLE I DISABLE

HSO.4 CURRENT STATE

HSI.2 INPUT ENABLE I DISABLE

HSO.5 CURRENT STATE

TIMER 2 RESET SOURCE HSI.O I T2RST

CAM

HSI.3 INPUT ENABLE I DISABLE

HOLDING REGISlER IS FULL

HSO HOLDING REGISTER IS FULL

TIMER 2 CLOCK SOURCE HSt.l

T2CLK

270909-10

270909-11

IOS1 (16H)

IOC1 (16H)

SOFTWARE TIMER 0 EXPIRED

SELECT PWM I SELECT P2.5

SOFTWARE TIMER 1 EXPIRED

EXTERNAL INTERRUPT ACH7 I EXTINT

SOFTWARE TIMER 2 EXPIRED

TIMER 1 OVERFLOW INTERRUPT ENABLE I DISABLE

SOFTWARE TIMER 3 EXPIRED

TIMER 2 OVERFLOW INTERRUPT ENABL~ I DISABLE

TIMER 2 HAS OVERFLOW

HSO.4 OUTPUJ ENABLE I DISABLE

TIMER 1 HAS OVERFLOW

SELECT TXD I SELECT P2.0

HSI FIFO IS FULL

HSO.5 OUTPUT ENABLE I DISABLE

HSI HOLDING REGISTER DATA AVAILABLE

HSI INTERRUPT
FIFO FULL I ;'H"'OL"D'"IN"'G~RE"'G'"IS-'T""ER"'L"OA"D"E"'D
270909-13

270909-12

IOS2 (17H)

IOC2(OBH)

INDICATES WHICH HSO EVENT OCCUR ED

ENABLE FAST INCREMENT OF T2

HSO.O

ENABLE T2 AS UP jDOWN COUNTER

HSO.l

ENABLE +2 PRESCALER ON PWM

HSO.2

X (SET TO 0)

HSO.3

AID CLOCK PRESCALER DISABLE

HSO.4

T2 ALTERN'ATE INTERRUPT

HSO.5

ENABLE LOCKED CAM ENTRIES

T2RESET

CLEAR ENTIRE CAM

START AID

8000H

270909-15
270909-14

4-137

87C196KB16

SFR BIT SUMMARY
INLPEND/INLMASK (09H/08H)

INLPEND1/INLMASK1 (12H/13H)

TIMER OVERFLOW

TRANSMIT INTERRUPT

A/D CONVERSION COMPLETE

RECEIVE INTERRUPT

HSI DATA AVAILABLE

HSI FIFO 4

HIGH SPEED OUTPUTS

TIMER 2 CAPTURE

HSI.O PIN

TIMER 2 OVERFLOW

SOFTWARE TIMER

EXTINT PIN

SERIAL PORT

HSI FIFO FULL

EXTERNAL INTERRUPT (EXTINT
OR PO.7 PIN)
270909-16

NMI (SET TO 0)
270909-17

SP_STAT(11H)

W
R
I
T
E

BIT.1, BIT.O SPECIFY THE MODE
O.O=MODEO 1.0=MODE2
O. r = MODE 1 1.1 = MODE 3

PEN ENABLE THE PARITY FUNCTION

RECEIVE OVERRUN ERROR

REN ENABLES THE RECEIVE FUNCTION:

TRANSMITTER EMPTY

TB8 PROGRAMS THE 9TH DATA BIT

FRAMING ERROR
TRANSMIT INDICATOR
RECEIVE INDICATOR
RECEIVE PARITY ERROR
270909-19

270909-18

HSO_COMMAND (06H)
CHANNEL: 0-5 HSO.O - HSO.5 INDIVIDUALLY
BIT:

]6
7
8-B
C-D
E
F

HSO.O AND HSO.1
HSO.2 AND HSO.3
SOFTWARE TIMERS
RESERVED FOR FUTURE USE
RESET TIMER2
START A/D CONVERSION
INTERRUPT / NO INTERRUPT
SET /CLEAR
TIMER 2/TIMER 1

LOCK CAM
270909-20

4-138

inter

87C196KB16

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings*
Ambient Temperature
Under Bias ...................... O°C to + 70°C
Storage Temperature .......... - 65°C to + 150°C
Voltage On Any Pin to Vss ........ -0.5V to + 7.0V
Power Dissipation .......................... 1.5W

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex,
tended exposure beyond the "Operating Conditions"
may affect device reliability.

Operating Conditions
Symbol
TA

Description

Min

Max

Units

Ambient Temperature Under Bias

+70

°C

Vee

Digital Supply Voltage

4.50

5.50

VREF

Analog Supply Voltage

4.50

5.50

fose

Oscillator Frequency

3.5

MHz

NOTE:

ANGND and Vss should be nominally at the same potential.

D.C. Characteristics:

(Over Specified Operating Conditions)

Min

Max

Units

-0.5

0.8

0.2 Vee + 0.9

Vee + 0.5

Input High Voltage on XT AL 1

0.7 Vee

Vee + 0.5

VIH2

Input High Voltage on RESET

2.6

Vee + 0.5

VOL

Output Low Voltage

0.3
0.45
1.5

V
V
V

IOL
IOL
IOL

= 200 fLA
= 3.2 mA
= 7mA

VOH

Output High Voltage
(Standard Outputs)

Vee - 0.3
Vee - 0.7
Vce- 1.5

V
V
V

IOH
IOH
IOH

= - 200 fLA
= -3.2 mA
= -7mA

VOH1

Output High Voltage
(Quasi-bidirectional Outputs)

Vee - 0.3
Vee - 0.7
Vee - 1.5

V
V
V

IOH
IOH
IOH

= -10 fLA
= -30 fLA
= -60 fLA

III

Input Leakage Current (Std. Inputs)

ILl1

Input Leakage Current (Port 0)

ITL

1 to 0 Transition Current (QBD Pins)

-650

IlL

Logical 0 Input Current (QBD Pins)

IIL1

Logical 0 Input Current in Reset
ALE, RD, INST (Note 2)

Hyst.

Hysteresis on RESET Pin

Symbol

Description

VIL

Input Low Voltage

VIH

Input High Voltage (Note 1)

VIH1

±10

fLA

. fLA

Test Conditions

o < VIN

< Vee - 0.3V

0< VIN < VREF

fLA

VIN

= 2.0V

-50

fLA

VIN

= 0.45V

-6

VIN

= 0.45V

300

NOTES:

1. All pins except RESET and XTAL 1.
2. Holding these pins below VIH in Reset may cause the P!lrt to enter test modes.
4-139

87C196KB16

, Characteristics (Continued)
DC,
"

,Symbol

Typ(7)

Max

Units

rnA

Idle Mode Current

10'

rnA

Active Mode Current

rnA

XTAL 1
Vcc

Description

Min

Icc

Active Mode Current in Reset

IREF

AID Converter Reference Current

IIDLE
'ICCl
Ipo

Powerdown Mode Current

RRST

Reset Pullup Resistor

Pin Capacitance (Any Pin to VSS)

5
6K

/-I- A

50K

Test Conditions
XTAL1 = 16 MHz
Vcc = Vpp = VREF

fTEST

5.5V

3.5 MHz

Vpp

VREF

1.0 MHz

NOTES:
(Notes apply to all specifications)
1. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
2. Standard Outputs include ADO-15, RD, WR, ALE, SHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0, and RXD (in serial mode 0). The VQjj specification is' not valid for RESET. Ports 3 and 4 are open-drain outputs.
3. Standard Inputs include HSI pins, CDE, EA, READY, BUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3, and
T2RST IP2.4.
4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
, below Vee - 0.7V:
'
IOl on Output pins: 10 mA
IOH on quasi-bidirectional pins: self limiting
IOH on Standard Output pins: 10 mA
5. Maximum current per bus pin (data and control) during normal operation is ± 3.2 mA.
6. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
IOl: 29 mA
IOH is self limiting
HSO, P2.0, RXO, RESET IOl: 29 mA
IOH: 26 mA
P2.5, P2.7, WR, BHE
IOl: 13 mA
IOH: 11 mA
ADO-AD15
IOl: 52 mA
IOH: 52 mA
RD, ALE, INST -CLKOUT IOl: 13 mA
IOH: 13 mA
7. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V.

60r-----~------_r------,-----~

50~----_+------4_------~~--~

40~----_+------~~--~~~--~

ICC

rnA

30~----_+~~--~~----+-----~
20~----_+~~---r----~~~--~

FREQUENCY
ICC Max = 3.88 x FREQ + 8.43
IIDlE Max = .1.65 x FREQ + 2.2

Figure 4. ICC and IIDLE vs. Frequency

4-140

270909-21

87C196KB16

A.C.Characteristlcs (Over specified operating conditions)
Test Conditions: Capacitiveioad on all pins = 100 pF, Rise and fall times

10 ns, fose

16 MHz

The system must meet these specifications to work with the 87C196KB:
Symbol
TAVYV
TLLYV

Description

Min

Address Valid to READY Setup
. ALE Low to READY Setup

TYLYH

NonREADY Time

TeLYX

READY Hold after CLKOUT Low

TLLYX

READY Hold after ALE Low

Max

Units

2Tose - 75

Tose - 60

No upper limit

Notes

ns
ns

(Note 1)

2Tose - 40

(Note 1)

2Tose - 75

Tose - 60

Tose - 30

Tose - 15

TAVGV

Address Valid to Buswidth Setup

hLGV

ALE Low to Buswidth Setup

TeLGX

Buswidth Hold after CLKOUT Low

TAVDV

Address Valid to Input Data Valid

3Tose - 55

(Note 2)

TRLDV

RD Active to Input Data Valid

Tose - 23

(Note 2)

TeLDv

CLKOUT Low to Input Data Valid

Tose - 50

TRHDZ

End of RD to Input Data Float

Tose - 20

TRXDX

Data Hold after RD Inactive

NOTES:.
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2Tasc x n where n = number of wait states.

4-141

87C196KB16

. A.C. Characteristics (Over specified operating conditions) (Continued)
Test Conditions: Capacitive loat! on all pins

100 pF, Rise and fall times"" 10 ns, fosc "" 16MHz

The 87C196KB will meet these specifications:

Symbol

Description

Min

Max

Units

Notes

3.5

16.0

MHz

(Note 3)

62.5

' 286

110

FXTAL

Frequency on XTAL 1

Tosc

1/ FxTAL

TXHCH

XT AL 1 High to CU~»m»~-------I

t WLWH + 2Tosc
t AVWH + ZTose

DATA OUT

I---A-D-DR-E-SS-OU-T---»«

4
::=::j
X,--_AD_D_RE_S_S_ _

I
270909-23

Buswidth Bus Timings
XTAL1

~': ~ ,~c: J~ ~,:".)
BUSWIDTH

~----------------I

-":'"I.-------t~AU-G-V------1-

BUS

-{~:---------~~-----)~----------

270909-24

4-144

87C196KB16

HOLD/HLDA Timings
-----Description

tJ!in

Max

Units

Notes

ris

(Note 1)

CLKOUT Low to HLDA Low

-10

CLKOUT Low to BREQ Low

-10

Symbol
THVCH'

HOLD Setup

TCLHAL
TCLBRL

THALAZ

HLD-A Low to Address Float

THALBZ

HLDA Low to BHE, INST, RD, WR Float

TCLHAH

CLKOU T Low to HLDA High

-15

TCLBRH

CLKOUT Low to BREQ High

-15

._.

THAHAX

HLDA High to Address No Longer Float

-10

THAHBV

HLDA High to BHE, INST, RD; WR Valid

-10

CLKOUT Low to ALE High

-5
,--

TCLLH

ns
ns
15

NOTE:
1. To guarantee recognition at next clock,

Maximum Hold Latency
.-

------Internal Access

---_.

1.5 States
2.5 States

16-Bit External Execution

8-Bit External

Max Hold Latency

-------.

4.5 States

--_

CLKOUT

BUS

BHE,INST

RD.WR

ALE

- { ' - _ " " ' ; "_ __

\
I,
----~----~'--~!~/----~

~I-I

----""'lll-I_ _ _tC_L_LH_n.J
1--.
'-______
270909-25

L-.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .. _ _ _ _ _ _ _ _ _ _ .. _. _ _ _ _ _ _ _ _ _ _ _ _ _ _--'

4-145

inter

87C196KB16

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TxLXL

Oscillator Frequency

3.5

MHz

TXLXL

Oscillator Frequency

62.5

286

TXHXX

High Time

TXLXX

Low Time

TXLXH

Rise Time

TXHXL

Fall Time

ns
ns

EXTERNAL CLOCK DRIVE WAVEFORMS

270909-26

An external oscillator may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications, the capacitance will not exceed 20 pF.

A.C. TESTING INPUT, OUTPUT WAVEFORM

2.4~ 2.0> TEST POINTS

0 . 4 5 - 1 \ O.B

2.0

FLOAT WAVEFORM

O.B.

270909-27
A.C. Testing inputs are driven at 2.4V for a Logic "I" and 0.45V
for a Logic "0" Timing measurements are made at 2.0V for a
Logic "I" and 0.8V for a Logic "0".

270909-28
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded VOHIVOl Level occurs
IOl/lOH = :!; 15 mAo

EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by "T" for. time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.

Conditions:
H
High
L
Low
V
Valid
No Longer Valid
- Floating

x
z

Signals:
A
- Address
B
- BHE
BR - BREQ
C
- CLKOUT
o - DATA IN
G
- Buswidth
H
- HOLD

4-146

HA - HLDA·
L
- ALE/ADV
Q
- DATA OUT
R - RD
W - WR/WRH/WRL
x .- XTAL1
Y
-READY

inter

87C196KB16

EPROM SPECIFICATIONS
A.C. EPROM Programming Characteristics
Operating Conditions: Load Capacitance = 150 pF. TA
OV. Vpp = 12.75V ± 0.25V. EA = 12.75V ± 0.25
Symbol

= + 25°C ± 5°C.

Description

Min

Reset High to First PALE Low

TSHLL

Vee. VREF:'

Max

5V. Vss. ANGND
Units

1100

Tosc

TLLLH

PALE Pulse Width

Tosc

TAVLL

Address Setup Time

Tosc

TLLAX

Address Hold Time

hLVL

PALE Low to PVER Low

Tosc

TpLDV

PROG Low to Word Dump Valid

Tosc

TpHDX

Word Dump Data Hold

Tosc

TDVPL

Data Setup Time

Tosc

TpLDX

Data Hold Time

Tosc

TpLPH

PROG Pulse Width

Tosc

TpHLL

PROG High to Next PALE Low

120

Tosp

TLHPL

PALE High to PROG Low

220

Tosc

PROG High to Next PROG Low

Tosc

120

Tosc

TpHIL

PROG High to AINC Low

Tosc

TILIH

AINC Pulse Width

Tosc

TILVH

PVER Hold after AINC Low

Tosc

TILPL

AINC Low to PROG Low

170

TPHVL

PROG High to PVER Low

TpHPL

Tosc
90

Tosc

NOTES:

1. Run Time Programming is done with Fosc = 6.0 MHz to 16.0 MHz. VREF = 5V ± 0.65V. TA = -i- 25°C to ± 5°e and
Vpp = 12.75V. For run-time programming over a full operating range, contact the factory.

D.C. EPROM Programming Characteristics
Symbol

Description

Ipp

Vpp Supply Current (When Programming)

NOTE:

Vpp must be within 1V of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground or VSS while
Vee> 4.5V.

4-147

87C196KB16

EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE

PORTS
3/4

--t-~~:::!~~~~

PVER

270909-29

SLAVE PROGRAM MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT

--J

PORTS

ADDR/COt.4t.4AND

3/4

-tSHLl~

ADDR

VEA: BITS/WO DUMP

f--

tPLDV -

tPHDX

ADDR+ 2

VER BITS/WO DUMP

-+tPLDV -

tPHDX·

/
f

tlLPL~

-tPHPL-

i'-

270909-30

SLAVE PROGRAMMING MODE TIMING IN.DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT

PO:;! _ _ _--(

.. ODR/COMMAND

>---<

ADDR

DATA>

ADDR+ 2
DATA

) -

270909-31

4-148

inter

87C196KB16

A.C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE

Symbol
TXLXL

Min

Parameter.
Serial Port Clock Period (BRR ;;:: 8002H)

TXLXH

Serial Port Cloc.k Falling Edge to Rising Edge (BRR ;;:: 8002H)

TXLXL

Serial Port Clock Period (BRR

= 8001 H)
= 8001 H)

Max

Units

6 Tose

4Tose ±50

4 Tose

TXLXH

Serial Port Clock Falling Edge to Rising Edge (BRR

2 TosC ±50

TQVXH

Output Data Setup to Clock Rising Edge

2 Tose -50

TXHQX

Output Data Hold after Clock Rising Edge

TXHQV

Next Output Data Valid after Clock Rising Edge

TDVXH

Input Data Setup to Clock Rising Edge

TXHDX

Input Data Hold after Clock Rising Edge

TXHQZ

Last Clock Rising to Output Float

ns
2 Tosc +50

Tose +50

ns
1 Tose

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE

•

SERIAL· PORT WAVEFORM-SHIFT REGISTER MODE

RXO-""""'-'
(IN) __J~._CC:~"L
270909-32

4·149

87C196KB16

stability of VREF. VREF must be., close toVee since it
supplies both the resistor ladder and the digital section of the converter.

10-81T AID CHARACTERISTICS
The speed of the AID converter in the 10-bit mode
can be adjusted by setting a clock prescaler on or
off. At high frequencies more time is needed for the
comparator to settle. The maximum frequency with
the clock prescaler disabled is 6 MHz. The conversion times with the prescaler turned on or off is
shown in the table below. The AD_TIME register
has not been characterized for· the 10-bit mode.

AID CONVERTER SPECIFICATIONS
The specifications given below assume adherence
to the Operating Conditions section of this data
sheet. Testing is performed with VREF = 5.12V.

The converter is ratiometric, so the absolute
accuracy is directly dependent on the accuracy and

Clock Prescaler On
IOC2.4 = 0

Clock Prescaler Off
IOC2.4 ='1

156.5 States
19.5 fJ-s @ 16 MHz

89.5 States
29.8 fJ-s @ 6 MHz

Parameter

Typical(1)

Minimum

Maximum

Units'

1024
10

Levels
Bits

±3

LSBs

Resolution
Absolute Error
Full Scale Error
Zero Offset Error
Non-Linearity Error

0.25 ±0.50

LSBs

-0.25 ±0.50

LSBs

1.5 ±2.5

Differential Non-Linearity Error

±3

LSBs

> -1

LSBs

±1

Channel-to-Channel Matching

±0.1

Repeatability

±0.25

LSBs

Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity

0.009
0.009
0.009

LSBrC.
LSBrC
l,.SBrc
-60

Off Isolation
Feedthrough

-60

Vee Power Supply Rejection

-60

Input Resistance
D.C. Input Leakage
Sample Time:

Prescaler On
Prescaler Off

Sample Capacitive

750

1.2K

3.0

LSBs

2,3

n
fJ-A

15
8

States
States

NOTES:
'An "L$S", as used here, has a value of approximately 5 mY.
1. Typical values are expected for most devices at 25'e.
2. DC to 100 KHz.
3. Multiplexer Sreak-Sefore-Make Guaranteed.

4-150

Notes

87C196KS16

AID GLOSSARY QF TERMS
ABSOLUTE ERROR-The 'maximum difference between corresponding actual and ideal code transitions. Absolute Error accounts for all deviations of
an actual converter from an ideal converter.

INPUT RESISTANCE-The effective serie,s resistance from the analog input pin, to tf:le sample capacitor.

ACTUAL CHARACTERISTIC-The characteristic
of an a9tual converter. The characteristic of a given
converter may vary over temperature, supply voltage, and frequency conditions. An actual characteristic rarely has ideal first and I~st transition loca~ions
or ideal code widths. It may'even vary over multiple
conversions under the same con'ditions.

LSB-:-Least Significant Bit: The voltag~ corresponding to the full scale voltage divided by 2""
where n is the number of bits of resolution of the
converter. For an 8-bit converter with a reference
voltage of 5.12V, one LSB is 20 mV. Note that this is
different than digital LSBs, since an uncertainty of
two LSB, when referring to an AID converter, equals
40 mV. (This has been confused with an uncertainty
of two digital bit!!, which would mean four counts, or
80mV.)

BREAK BEFORE MAKE-The property of a multiplexer which .guarantees that a previously selected
channel is selected (i.e., the converter will not short
inputs together).

NON·LINEARITY-The maximum deviation of ~ode
transitions of the terminal based characteristic from
the corresponding code transitions of the ideal characteristic.

CHANNEL-TO-CHANNEL MATCHING-The difference between corresponding code transitions of actual characteristics taken from different channels under the same temperature, voltage and frequency
conditions.

OFF-ISOLATION-Attenuation of a voltage applied
on a deselected'channel of the AID converter. (Also
referred to as Crosstalk.)

CHARACTERISTIC-A graph of input voltage versus the resultant output code for an AID converter.
It describes the transfer function of the AID converter.
CODE-The digital value output by the converter.
CODE TRANSITION-The point at which the converter changes from an output code of Q, to a code
of Q + 1. The input voltage corresponding to a code
transition is defined to be that voltage which is
equally' likely to produce either of two adjacent
codes.
CODE WIDTH-The voltage corresponding to the
difference between two adjacent code transitions.
D.C. INPUT LEAKAGE-Leakage current to ground
from an analog input pin.

REPEATABILITY-The difference between corresponding code transitions from different actual characteristics taken from the same converter on the
same channel at the same temperature, voltage and
frequency conditions.
RESOLUTION-The number of input voltage levels
that the converter can unambiguously distinguish
between. Also defines the number of useful bits of
information which the converter can return.
SAMPLE TIME-The time that the sample window
is open.
SAMPLE WINDOW-Begins when the sample capacitor is attached to a selected channel and ends
when the sample capacitor is disconnected from the
selected channel.

DIFFERENTIAL NON-LINEARITY-The difference
between the ideal and actual code widths of the terminal based characteristic.

FEEDTHROUGH",,:,Attenuation of a voltage applied
on the selected channel of the AID Converter after
the sample window closes.

TERMINAL BASED CHARACTERISTIC-An actu,al
characteristic which has been rotated and translated
to remove zero offset and full scale error.

FULL SCALE ERROR-The difference between the
expected and actual input voltage corresponding to
the full 'scale code transition;

Vee REJECTION-Attenuation of noise on the Vee

IDEAL CHARACTERISTIC-A characteristic with
its first code transition at VIN = 0.5 LSB, its last
code transition at VIN = (VREF - 1.5 LSB) and all
code widths equal to one LSB.

line to the

AlP converter.

ZERO OFFSET-The difference between the expected and actual input voltage corresponding to
the first code,transition.

4-151

87C196KB16

CONVERTING FROM OTHER 8096BH
FAMILY PRODUCTS TO THE
8XC196KB
The following list of suggestions for designing 'an
879XBH system will yield· a design that is easily converted to the 87C196KB.
1. Do not base critical timing loops on 'instruction or
peripheral execution ti~es. '
2.. Use equate statements to set all timing parameters, Including the baud rate.
3. Do not base hardware -timings on CLK0UT or
XTAL1. The timings of the 87C196KB are different than those of the 8X9XBH, l;lUt they will func. tion with standard ROM/EPROM/Peripheral type
. memory systems.
4. Verify that all inputs are driven high or low and net
left floating.

5. Indexed and indirect operations relative- to the
stack pointer' (SP) work .differently . on the
80C196KB than on the 8096BH. On the 8096BH,
the address is calculatfild baSed on the· un-updated version ·of the. stack pointer. The 87C196KB
uses the updated version. The offset for POP[SPj
and POP nn[SPj instructions may need to be
changed by a count of 2.
6. PACT has changed from the HSO.O on the
8796BH to P2. '? on the 87C196KB.
7. The VPD on the 8096BH has changed to a Vss
pin on the 87C196KB.
.

DATA SHEET REVISION HISTORY
This data sheet (version -001) is valid for devices
with a "C" suffix on the topside tracking number.
This is the first version of the 87C196KB16 data
sheet.

4-152

~OO[gIl..O[M]OOO&OOW

83C198/80C198,83C194/80C194
16-BIT CHMOS MICROCONTROLLER
. 83C198 - 8 Kbytes of Factory Mask-Programmed ROM
80C198 -.ROMless

•
•
•
•
•
•
•
•

232 Byte Register File
Register-to-Register Architecture
28 Interrupt Sources/16 Vectors
2.3 ,."s 16 x 16 Multiply (12 MHz)
4.0 ,."s 32/16 Divide (12 MHz)
Powerdown and Idle Modes
16-Bit Watchdog Timer
8-Bit External Bus

•
•
•
•
•
•
•
•

Full Duplex Serial Port
High Speed 1/0 Subsystem
16-Bit Timer
16-Blt Counter
Pulse-Width-Modulated Output
Four 16-Blt Software Timers
10-Bit AID Converter with SamplelHold
The 8XC194 is an 8XC198 without an
On-Chip AID Converter

The 80C198 is the low cost member of the CHMOS MCS®-96 microcontroller family. Intel's CHMOS process
provides a high performance processor along with low power consumption. To further reduce power requirements, the processor can be placed into Idle or Powerdown Mode.
The 83C198 is an 80C198 with 8 Kbytes on-chip ROM. In this document, the 80C198 will refer to both
products unless otherwise stated.
.
Bit, byte, word and some 32-bit operations are available on the 80C198. With a 12 MHz oscillator a 16-bit
addition takes 0.66 J.A-s,and the instruction times average 0.5 J.A-s to 1.5 J.A-s in typical applications.
Four high-speed 'capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or counter.
Also provided on-chip are an AID converter, serial port, watchdog timer, and a pulse-width-modulated output
signal.
V EF

ANGND

CONTROL
SIGNALS

PORT 3
ADDR
} DATA
BUS

PORT 4

HSI
HSO

270815-1

Figure 1. 83C198/80C198 Block Diagram
MCS®-96 is a registered trademark of Intel Corporation.

4-153

October 1990
Order Number: 270815-002

83C198/80C198,83C194/80C194

PACKAGING
The BOC19B and B3C19B are available in a 52-pin
PLCC package and an BO-pin OFP package. Contact
your local sales office to determine the exact order-.
ing code for the part desired.
.

With AID

Without AID

ROMless

NBOC19B-PLCC
SBOC19B-OFP

NBOC194-PLCC
SBOC194-0FP

ROM

NB3C19B-PLCC
SB3C19B-OFP

NB3C194-PLCC
SB3C194-,QFP

The BXC194 is an BXC19B without the AID converter.

"ci c.i'"
"" '"
11.

:I:

:::;

:I:

.11.

..J

11.

....
8 ;:;
x x >~ ~ ~ I~ « «

~ ~~ ;5

« ~ I~ > >

(.)

..; ..;

11.

ACHS/PO.S

AD2/P3.2

. ACH4/PO.4 .

AD3/P3.3

ANGND

AD4/P3.4

VREF

AD5/P3.5

inter

vss
EXTINTjP2.2
RESET
RXD/P2.1

N80C198

TXD/P2.0

TOP VIEW

AD6/P3.6
AD7/P3;7
A8/P4.0
A9/P4.1
Al0/P4.2

HSI.O

All/P4.3

HSI.l

A12/P4.4

HSO.4/HSI.2

A13/P4.5

HSO.5/HSI.3

A14/P4.6

'" .
"''''

ci ci
ci >
Vl Vl Vl

:I:

0
Vl
:I:

ljl

> >

:::;
~

11.

...

I~ N ~
'"N
11.
11. «

,....

Vl
0::

"""

....
'"

0::

..J
(.)

Figure 2. 52-Pin PLCC Package

4-154

.....

...

11.
U")

:t
270815-2

inter

83C198/80C198,83C194/80C194

SO-Pin Quad Flat Pack (EIAJ)
Contacts

Contacts

Facing Up

Facing Down

41
40

270815-3

111111111111!1!!
64
AD1/P3.1

ADO/P3.0

Rli
ALE/ADV

T2CLK/P2.3

Vss

2
3

READY

T2RST/P2.4

---"--

N.C.

INST

Vss

PWt.l/P2.5
N.C.

N.C.

XTAL2

Vpp

XTAL1

vss

Vss

vss

Vss

HSO.3

Vee
Vee

52
51

Vee
¥ss

HSO.2

N.C.

.47

N.C.

HSO.1

Vss

N.C.

ACH6/PO.6

HSO.O

ACH7/PO.7

HSO.5/HSI.3

N.C.

ACH5/PO.5

ACH4/PO.4

~ ~ ::. ~ ~ :il ;;; ~ ::l ~ :ll ~ ::; :ll Sl

¥ss
HSO.4/HSI.2

!llllll!!!l!!l!!
270815-4

Figure 3. SO-Pin Quad Flat Pack (QFP)

4·155

inter

83C198/80C198,83C194/80C194

PIN DESCRIPTIONS
Symbol

Name and Function

Vee

Main supply voltage (5V).

Vss

The PLCC package has 5 VSS pins and the QFP package has 12 VSS pins. All must be
connected to circuit ground.

VREF

Reference voltage for the AID converter (5V). VREF is also the supply voltage to the
analog portior;J of the AID converter and the logic used to read Port O. Must be
connected for AID and Port 0 to function.

ANGND

Reference ground for the AID converter. Must be held at nominally the same potential
as Vss.

Vpp

Timing pin for the return from powerdOwn circuit. Connect this pin with a 1 p.F capacitor
to Vss. If this function is not used. connect to Vee. This pin is the programming voltage
on the EPROM device.

XTAL1

Input of the oscillator inverter and of the internal clock generator.

XTAL2

Output of the oscillator inverter.

RESET

Reset inpl,lt to the chip. Input low for at least 4 state times to reset the chip. The
subsequent low-to-high transition commences the Reset Sequence in which the PSW is
cleared. a byte read from 2018H loads CCR. and a jump to location 2080H is executed.
Input high for normal operation. RESET has an internal pull up.

INST

Output high during an external memo!), read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is activated only during external memory
accesses and output low for a data fetch.

Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 3FFFH to be directed to on-chip ROM/EPROM.
EA equal to a TTL-low causes accesses to these locations to be directed to off-chip
memory.

ALE/ADV

Address Latch Enable or Address Valid output. as selected by CCR. Both pin options
provide a latch to demultiplex the address from the addressl data bus. When the pin is
ADV. it goes inactive high at the end of the bus cycle. ADV can be used as a chip select
for external memory. ALEI ADV is activated only during external memory accesses.

Read signal output to external memory. RD is activated-only during external memory
reads.

Write output to external memory. WR will go low for every external write.

4-156

inter

. 83C198/80C198, 83C194/80C194

PIN DESCRIPTIONS (Continued)
Name and Function

Symbol
READY

Ready input to lengthen external memory cycles, for interfacing to slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. When the external memory is not being used, READY has no effect. Internal
control of the number of wait states inserted into a bus cycle held not ready is available
through configuration of CCR.

HSI

Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2, and
HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.

HSO

Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1,
HSO.2, HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the
HSI Unit.

Port

4-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip AID converter. These pins set the Programming Mode on
the EPROM device.

Port 2

Multi-functional port. All of its pins are shared with other functions in the 80C198.

Ports 3 and 4

8-bit bi-directionall/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pull ups. Available as I/O only
on the ROM and EPROM devices.

TxD

The TxD pin is used for serial port transmission in Modes 1, 2, and 3. The TxD function is
enabled by setting IOC1 5. In mode the pin is used as the serial clock output.

RxD

Serial Port Receive pin used for serial port reception. The RxD function is enabled by
setting SPCON.3. In mode the pin functions as input or output data.

EXTINT

A positive transition on the EXTINT pin will generate an external interrupt. EXTINT is
selected as the external interrupt source by setting IOC1.1 high.

T2CLK

The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.

T2RST

A rising edge on the T2RST pin will reset Timer2. The external reset function is enabled
by setting IOCO.03 T2RST is enabled as the reset source by clearing IOCO.5.

PWM

Port 2.5 can be enabled as a PWM output by setting IOC1.0 The duty cycle of the PWM
is determined by the value loaded into the PWM-CONTROL register (17H).

4-157

83C198/80C198,83C194/80C194

MEMORY MAP
OFFFFH
EXTERNAL MEMORY OR 1/0
4000H
INTERNAL ROMIEPROM OR
EXTERNAL MEMORY
2080H
RESERVED
2040H
UPPER 8 INTERRUPT VECTORS
2030H
ROMIEPROM SECURITY KEY
2020H
RESERVED
2019H
CHIP CONFIGURATION BYTE
2018H
RESERVED

1---

2014H,

LOWER 8 INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
2000H
PORT 3 AND PORT 4
1FFEH
EXTERNAL MEMORY OR 1/0
0100H
INTERNAL DATA MEMORY· REGISTER FILE
(STACK POINTER, RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY

1'9H
18H

19H

STACK POINTER

18H

OOOOH

STACK POINTER
PWM CONTROL

17H

IOS2

17H

16H

IOS1

16H

IOC1

15H

1050

15H

lOCO

14H

WSR

14H

WSR

13H

INT_MASK1

13H

INT_MASK1

12H

INT_PEND1

12H

INT_PEND1

11H

SP_STAT

11H

SP_CON

10H

PORT2

10H

PORT2

10H

RESERVED (1)

OFH

RESERVED (1)

OFH

RESERVED (1)

OFH

RESERVED (1)

OEH

PORTO

OEH

BAUD RATE

OEH

RESERVED (1)

ODH

TIMER2 (HI)

ODH

TIMER2(HI)

ODH

RESERVED (1)

OCH

TIMER2 (LO)

OCH

TIMER2 (LO)

OCH

RESERVED (1)

OBH

TIMER1 (HI)

OBH

IOC2

OAH

TIMER1 (LO)

OAH

WATCHDOG

OSH

INT PENDING

09H

INT PENDING

08H

INT MASK

08H

INT

WSR

MASK

07H

SBUF.(RX)

07H

SBUF(TX)

06H

HSI_STATUS

06H

HSO_COMMAND

05H

'HSI_TIME (HI)

05H

HSO_TIME (HI)

04H

HSI_TIME (LO)

04H

HSO_TIME (LO)

03H

AD RESULT (HI)

03H

HSI

02H

AD COMMAND

01H

ZERO REG (HI)

01H

ZERO REG (HI)

OOH

ZERO REG (LO)

OOH

ZERO REG (LO)

WHEN WRITTEN

RESULT (LO)

OTHER SFRS IN WSR
15 BECOME READABLE
IF THEY WERE WRITABLE
INWSR ~ OANDWRITABLE
IF THEY WERE READABLE
INWSR ~ 0

MODE

'NOTE,
1. Reserved registers should not be written.

WHEN READ

WSR

4-158

intJ

83C198/80C198,83C194/80C194

SFR BIT SUMMARY
AD-Result (LO) (02H)

AD_Command (02H)

AID CHANNEL NUMBER
STATUS:
o = AID CURRENTLY IDLE
X
1 = CONVERSION IN PROCESS

CHANNEL # SELECTS WHICH OF THE 4
ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL FORM.

3 '"- GO INDICATES WHEN THE CONVERSION IS TO
BE INITIATED (GO 1 MEANS START NOW,
X
GO = 0 MEANS THE CONVERSION IS TO BE
~
INITIATED BY THE HSO UNIT AT A SPECIFIED TIME).

f0-

AID RESULT:
LEAST SIGNIFICANT 2 BITS

SET UPPER FOUR BITS TO ZERO

f0-

....
X

270815-5

270815-6

Chip Configuration (2018H)

WSR (14H)

117161514131211 10 ICHIP CONFIGURATION REGISTER
L::OWERDOWN

o=SFR's FUNCTION UKE SUPERSET OF 80968H
14( 1 1 10B) = PPW REGISTER
.
15(111 lB)=EXCHANGE READ/WRIlt REGISTERS
OTHER = UNDEFINED, DO NOT USE

MO~E ENABLE

(lRCO)
(lRCt)

o
o

ADDRESS VALID STROBE SELECT
(ALE I ADV)

o
o

l~TERNAL READY CONTROL
MODE

270815-8

(LOCO) }
(LOC1) PROGRAM LOCK MODE
270815-7

HSI_Status (06H)

HS'-Mode (03H)

'-----HSl.l MODE
L - - - - - - - H S I . 2 MODE

L - - - - - - - H S I . 2 STATUS

' - - - - - - - - - - H S I . 3 MODE

L - - - - - - - - - H S I . 3 STATUS
WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.
270815-10

WHERE EACH 2 - BIT MODE CONTROL FIELD
DEFINES ONE OF 4 POSSiBLE MODES:
00
01
10
11

8 POSITIVE TRANSITIONS
EACH POSITIVE TRANSITION
EACH NEGATIVE TRANSITION
EVERY TRANSITION
(POSITIVE AND NEGATIVE)
270815-9

4-159

83C198/80C198,83C194/80C194

,..-----------'----- -------

,..-----------'------_._--'-------

INT_PENDIINT_MASK (09H/OSH)
TIMER OVERFLOW

TRANSMIT'INTERRUPT

AID CONVERSION COMPLETE

RECEIVE INTERRUPT

HSI DATA AVAILABLE

HSI FIFO 4

HIGH SPEED OUTPUTS

(SET TO 0)
, TIMER 2 OVERFLOW

HSI.O PIN
SOFTWARE TIMER

EXTINT 1

SERIAL PORT

HSI FIFO FULL
(SET TO 0)

EXTERNAL INTERRUPT
270815-11

270815-12

'--------_._------------'
,..-----------------

SP_CON (11H)

BIT. 1, BIT.O SPECIFY THE MODE
O.O=MOOEO 1.0=MODE2
0.1 = MODE 1 1.1 = MODE 3

,
R
I
T
E

RECEIVE OVERRUN ERROR

PEN ENABLE THE PARITY FUNCTION

REN ENABLES

TH~

TB8 PROGRAMS THE 9TH DATA BIT

SET UPPER THREE
BITS TO ZERO

TRANSMITIER EMPTY

RECEIVE FUNCTION:

FRAMING ERROR
TRANSMIT INDICATOR
RECEIVE INDICATOR
RECEIVE PARITY ERROR

270815-14

270815-13

...--------------------------------------------------~

HSO Command (06H)
CHANNEL: 0-5 HSO.O - HSO.5 INOIVIOUALL Y
BIT:

0]6
7
8-B
C-D
E
F

HSO.O AND HSO.l
HSO.2 AND HSO.3
SOFTWARE TIMERS
RESERVED FOR FUTURE USE
RESET TIMER2
'
START AID CONVERSION .

INTERRUPT 1 NO INTERRUPT
SET ICCEAR
TIMER

21 TIMER

LOCK CAM
270815-15

4-160

83C198/80C198,83C194/80C194
,-------~~---.

10$0 (15H)

-~---.-

-~- ~--------,

lOCO (15H)

HSO.O CURRENT STATE

HSI.O INPUT ENABLE / DISABLE

HSO.l CURRENT STATE

TIMER 2 RESET EACH WRITE

HSO.2 CURRENT STATE

HSl.l INPUT ENABl.E / DISABLE

HSO.3 CURRENT STATE

TIMER 2 EXTERNAL RE"SET ENABLE / DISABLE

HSO.4 CURRENT STATE

HSI.2 INPUT ENABLE/DISABLE

HSO.5 CURRENT STATE

TIMER 2 RESET SOURCE HSI.O / T2RST

CAM

Q.!l HOLDING REGISTER IS FULL

HSI.3 INPUT ENABLE /

i5iSABLE

TIMER 2 CLOCK SOURCE HSI.l / T2C~K

HSO HOLDING REGISTER IS FULL

270815-16

270815-17
,---------------------~

1051 (16H)

IOC1 (16H)

SOFTWARE TIMER 0 EXPIRED

SELECT PWM / SELECT P2.5

SOFTWARE TIMER 1 EXPIRED

EXTERNAL INTERRUPT ACH7/ EXTINT

SOFTWARE TIMER 2 EXPIRED

TIMER 1 OVERFLOW INTERRUPT ENABLE / DISABLE

SOFTWARE TIMER 3 EXPIRED

TIMER 2 OVERFLOW INTERRUPT ENABLE / DISABLE

TIMER 2 HAS OVERFLOW

HSO.4 OUTPUT ENABLE / DISABLE

TIMER 1 HAS OVERFLOW

SELECT TXD / SELECT P2.0

HSI FIFO IS FULL

HSO.5 OUTPUT ENABLE / DiSABLE

HSI HOLDING REGISTER DATA AVAILABLE

HSI INTERRUPT
FIFO FULL / HOLDING REGISTER LOADED
270815-19

270815-18

IOC2(OBH)

1052 (17H)
INDICATES WHICH HSO EVENT OCCURED

HSO.O

ENABLE FAST INCREMENT OF T2

HSO.l

ENABLE +2 PRESCALER ON PWM

HSO.2

X (SET TO 0)

HSO.3

A/D CLOCK PRESCALER DISABLE

HSO.4

T2 ALTERNATE INTERRUPT @ 8000H

HSO.5

ENABLE lOCKED CAM ENTRIES

T2RESET

CLEAR ENTIRE CAM

START A/D

270815-21

_ _ _ _ _ _ _ _ _ _ _ _ _ • _ _ _ _ _ _.....J

270815-20
L......_ _ _ _ _ _ _ _ _ _ _ _ _ _
_
~

4-161

inter,

83C198/80C198,83C194/80C194

ELECTRICAL CHARACTERISTICS

NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.

Absolute Maximum Ratings*

* WARNING: Stressing the device beyond the "Absolute
MaximUm Ratings". may cause permanent damage.
These' are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Ambient Temperature
Under Bias ...................... O°C to + 70°C
. Storage Temperature .......... -65°C to + 150°C
Voltage On Any Pin to VSS ........ -0.5V to + 7.0V
Power Dissipation .......................... 1.5W

Operating Conditions
Symbol
TA

Description

Min

Max

Units

Ambient Temperature Under Bias

+70

°C

Vee

Digital Supply Voltage

4.50

5.50

VREF

Analog Supply Voltage

4.50

5.50

fose

Oscillator Frequency

3.5

MHz

NOTE:

ANGND and Vss should be nominally at the same potential.

D.C. Characteristics
Symbol

(Over specified operating conditions)

Description

Min

Max

Units

-0.5

0.8

Vil

Input Low Voltage

VIH

Input High Voltage (Note 1)

VIHI

Input High Voltage on XTAL 1

0.7 Vee

Vee + 0.5

2.6

Vee + 0.5

0.3
0.45
1.5

V
V
V

VIH2

Input High Voltage on RESET

Val

Output Low Voltage

VOH

Output High Voltage
(Standard Outputs)

Input Leakage Current (Std. Inputs)

0.2 Vee + 1.0 Vee + 0.5

,---------

-IU1

Input Leakage Current (Port 0)

IlL 1

Logical 0 Input Current in Reset (Note 2)
(ALE, RD, WR, INST, P2.0)

Hyst

Hysteresis on.RE'SET Pin

Vee - 0.3
Vee - 0.7
Vee - 1.5

V
V
V

= 200 p.A
= 32mA
= 7 mA
IOH = - 200 p.A
IOH = -3.2 mA
IOH = -7 mA

IOl
IOl
IOl

p.A

0< VIN < VREF

-1.2

YiN

±10

300

NOTE:

1. All pms except RESET and XTAl1.
2. Holding these pins below VIH In Reset may cause the part to enter test modes.

4-162

Test Conditions

VIN < Vee - 0.3V

= 0.45 V

83C198/80C198,83C194/80C194

D.C. Characteristics
Symbol

(Over specified operating conditions) (Continued)

Description

Min

Typ(6)

Max

Units

rnA

Test Conditions
XTALl = 12MHz
Vce = Vpp = VREF

Icc

Active Mode Current in Reset

IREF

AID Converter Reference Current

rnA

IIDLE

Idle Mode Current

rnA

ICCl

Active Mode Current

rnA

XTAL 1

IpD

Powerdown Mode Current

/J- A

Vee

RRST

Reset Pullup Resistor

Pin Capacitance (Any Pin to VSS)

'6K

65K

fTEST

5.5V

3.5 MHz

Vpp

VREF

1.0 MHz

NOTES:
(Notes apply to all specifications)
,
1. Standard Outputs include ADO-15, RD, WR, ALE, INST, HSO pins, PWM/P2.5, RESET, Ports 3 and 4, TXO/P2.0, and
RXD (In serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
2. Standard Inputs include HSI pins, EA, READY, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3, and T2RST/P2.4.
3. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on Standard Output pins: 10 mA
4. Maximum current per bus pin (data and control) during normal operation is ± 3.2 rnA.
5. During normal (non-transient) conditions the following total current limits apply:
HSO, P2.0, RXD, RESET IOL: 29 rnA IOH: 26 rnA
P2.5, WR
IOL: 13 rnA IOH: 11 rnA
ADO-AD15
IOL: 52 rnA IOH: 52 rnA
RD, ALE,INST
IOL: 13 rnA IOH: 13 rnA
6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room. temperature
and VREF = Vee = 5V.

60r-----~-----r----~

ICC MAX
50~----+-----~---~~

40 f------t-----¥-

::J.ooo'''''---j-----==--.-1 IIDLE TYPICAL

4MHz

ICC Max = 3.88 x FREQ + 8.43
IIDLE Max = 1,65 x FREQ + 2.2

ICC TYPICAL (7)

8MHz

12MHz

FREQ

Figure 4.

Icc and IIDLE vs Frequency

4-163

270815-22

83C198/80C198,83C194/80C194

A.C. Characteristics
For uSe over specilie,d operatiRQ conditions,
Test Conditions: Capacitive load on all phlS = 100 pF, Rise and fall times = 10 ns, lose = 12 MHz
The system must meet these specifications to work with the 83C198/80C198:
Max

Vnlts

TAVYV

Address Valid to Ready Setup

2Tose - 85

hLYV

ALE Low to READY Setup

Tose - 70

Symbol

Description

TYLYH

Non READY Time

TLLYX

READY Hold alter ALE Low

TAVDV

Address Valid to Input Data Valid

TRLDV

RD Active to Input Data Valid

TRHDZ

End 01 RD to Input Data Float

TRXDX

Data Hold after RD Inactive

Min

' No upper limit
Tose - 15

NOTES:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2Tasc x n, where n = number of wait states.

4-164

Notes

2Tose -.40

(Note 1)

3Tose - 60

(Note 2)

Tose - 23

(Note 2)

Tose - 20

ns
ns

inter

83C198/80C198,83C194/80C194

A.C. Characteristics
For use over specified operating conditions
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times = 10 ns, fose = 12 MHz

The 83C198/80C198 will meet these specifications:
Min

Max

Units

Notes

Frequency on XTAL1

3.5

MHz

(Note 1)

Tosc

II FXTAL

286

TLHLH

ALE Cycle Time

TLHLL

. ALE High Period

Symbol
FXTAL

Description

4Tosc
Tose - 10

Tosc+ 10

Address Setup to ALE Falling Edge

Tose - 20

TLLAX

Address Hold after ALE Falling Edge

Tose - 40

TLLRL

. ALE Falling Edge to RD Falling Edge

Tosc - 30

TAVLL

TRLRH

RD Low Period

TRHLH·

RD Rising Edge to ALE Rising Edge

(Note 4)

Tose - 5

Tosc + 25

(Note 4)

Tose

Tose + 25

(Note 3)

TRLAZ

RD Low to Address Float

hLWL

ALE Falling Edge to WR Falling Edge

Tosc - 10

TQVWH

Data Stable to WR Rising Edge

Tosc - 23

(Note 4)

TWLWH

WR Low Period

Tose - 30

(Note 4)

TWHQX

Data Hold after WR Rising Edge

Tosc - 2.5

TWHLH

WR Rising Edge to ALE Rising Edge

rose - 10

TWHBX

INST HQld after WR Rising Edge

Tose - 10

TRHBX

INST Hold after RD Rising Edge

Tosc - 10

TWHAX

AD8-15 Hold after WR RiSing Edge

Tosc - 50

TRHAX

AD8-15 Hold after RD Rising Edge

Tose - 25

Tosc + 5

ns
Tosc + 15

NOTES:
1. Testing performed at 3.5 MHz. However, the part is static by design and will typically operate below 1 Hz.
2. Typical specification, not guaranteed.
3. Assuming back-to-back bus cycles.
4. When using wait states, add 2TOSC x n, where n = number of wait states.

4-165

(Note 3)

83C198/80C198,83C194/8QC194

System Bus Timings

XTALI

ALE

--1.

tLHLH

I+- tLHLL.-- I-- tLLRL --I--

tRLRH --- -

BUS

---<

ADDRESS OUT
tAVDV

DATA

I-- t LLWL

ADDRESS OUT)X(
••

I
BHE,INST

AS-IS

»}}~

~ tWLWH ~ ~tWHLH""
I--tOVWH

BUS - ( . ___

tRHLH ....

J
tRLDV

rt.t.vLL- ,-.tLLAX

tWHox.1
1

DATA OUT

}~y~__
AD_DR_E_SS_ _ __

LtRHBX ..
ItWHBX

VALID

ADDRESS OUT

,
270815-23

83C198/80C198,83C194/80C194

READY Timings (One Waitstate)

XTALI

ALE

READY

_+_______ 1 - - - - - tRLRH + 2Tose -----1-------tRLDV + 2Tose ~

1 - - - - - - - - - t AVDV + 2Tose

~--AD-DR-ES-S-OU-T--~)

--------1--

(C·!DA~~:]»~»~)-»r-------I

tWLWH+2Tos e

j.1·--- tOVWH ~ 2 Tose

J
=:::J

r---A-D-DR-E-SS-OU-T--~~~<~_ _ _ _._D_AT_A_O_UT_ _ _ _ _~X~

___

A_DD_R_ES_S__~

I
270815-24

.4-167

83C198/80C198,83C194/80C194

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TxLXL

Oscillatqr Frequency

3.5

12.0

MHz

TXLXL

Oscilll;ltor Period

286

TXHXX

High Time

TXLXX·

Low Time

TXLXH

Rise Time

TXHXL

Fall Time

EXTERNAL CLOCK DRIVE WAVEFORMS

270615-25

An external oscillator· may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier and .its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.
.

A.C. TESTING INPUT, OUTPUT WAVEFORM

2.4

-V-

2.0> TEST POINTS

0.45---1\ O.B

2.0

FLOAT WAVEFORM
VLOAO+ O. 15V - - - - - - - - ____ TIMING REF'ERENCE.____
....--POINTS
----..
VLOAO-O.15 V ' -_ _ _ _ _ _ __

V--

vLOAO

O.B-A-

270815-26
A.C. Testing Inputs are driven at 2 4V for a Logic "1" and 0.45V
for a LogiC "0" Timing measurements are made at 2.0V for a
Logic "I" and 0.8V for a Logic "0".

270815-27
For Timing Purposes a Port Pin IS no Longer Floating when a
100 mV change from Load Voltage Occurs and BeginS to Float
when a 100 mV change from the Loaded VOHIVOl Level occurs
IOl/lOH = ± 15 rnA

Conditions:

Signals:

- High

Low

DATA IN

- Valid

- ALE/ADV

- No Longer Valid

DATA OUT

RD
WR
XTAL1
READY

Floating

X
Y

4-168

Address

83C198/80C198,83C194/80C194 ,

A.C. CHARACTERISTICS--SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol

Parameter

Min

TXLXL

Serial Port Clock Period (BRR :2 8002H)

TXLXH

Serial Port Clock Falling Edge
to Rising Edge (BRR :2 8002H)

TXLXL

Serial Port Clock Period (BRR = 8001 H)

TXLXH

Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)

Max

6 Tose

Units
ns

4 Tose ±50

4 Tose

2 Tose ±50

TOVXH

Output Data Setup to Clock Rising Edge

2 Tose -50

TXHOX

Output Data Hold after Clock Rising Edge

2 Tose -50

TXHOV

Next Output Data Valid after Clock Rising Edge

TDVXH

Input Data Setup to Clock Rising Edge

TXHDX

Input Data Hold after Clock Rising Edge

TXHOZ

Last Clock Rising to Output Float

2 Tose +50

Tose +50
0

ns
ns

1 Tose

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE

r- --j
---U ---U ---U ---U- ---U ---U ---U
TXLXL

TXD---U
TovxW'1

TXLXH-I

(O~;)---

r- TXHDX

RXD
(IN)
270815-28

4-169

I"m:.-r
•• ~"'

83C198/80C198,83C194/80C194

A TO D CHARACTERJSTICS
There are two modes of AID operation: with or without clock prescaler. The speed of the AID converter
can be adjusted by setting a clock prescaler on or
off. At high frequencies more time is needed for the
comparator to settle. The maximum frequency with
the clock prescaler" disabled is 8 MHz. The conversion times with the prescaler turned on or off is
shown in the table below.
The converter is ratiometric, so the absolute
accuracy is directly dependent on the accuracy and

stability of VREF. VREF must be close to Vee since it
supplies both the resistor ladder and the digital sec'
tion of the converter.

AID CONVERTER SPECIFICATIONS
The specifications given below assume adherence
to the Operating Conditions section of this data
sheet. Testing is performed with VREF = 5.12V.
The 8XC194 does not have an AID converter.

Clock Prescaler On
IOC2.4 = 0

Clock Prescaler Off
IOC2.4 = 1

158 States
26.33 p.s @ 12 MHz

91 States
22.75 p.s @ 8 MHz

Parameter

Typical(1)

Minimum

Maximum

Units'

512
9

1024
10

Levels
Bits

±4

LSBs

Resolution
Absolute Error
Full Scale Error
Zero Offset Error
Non-Linearity Error

0.25 ±0.50

Notes

LSBs

-0.25 ±0.50

LSBs

1.5 ±2.5

Differential Non-Linearity Error

±4

LSBs

> -1

LSBs

±1

LSBs

Channel-to-Channel Matching

±0.1

Repeatability

±0.25

LSBs

Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity

0.009
0.009
0.009

LSBrC
LSBrC
LSBrC
-60

2,3

Feedthrough

-60

Vee Power Supply Rejection

-60

Off Isolation

Input Resistance

D.C. Input Leakage

3.0

p.A

Sample Time: Prescaler On
Prescaler Off

15
8

States
States

Input Capacitance

NOTES:
'An uLSB", as used here, has a value 01 approximately 5 mY.
1. Typical values are expected for most devices at 25°e but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer Break-Belore-Make Guaranteed.
4. One state = 167 ns at 12 MHz, 250 ns at 8 MHz.

4-170

4
4

83C198/80C198,83C194/80C194

80C198 FUNCTIONAL DEVIATIONS
The 80C198 has the following problems.
1. The DJNZW instruction is not guaranteed to be
functional. The instruction, if encountered, will not
cause an unimplemented opcode interrupt. (The
opcode for DJNZW is OE1 Hex.) The DJNZ (byte)
in.!ltruction works correctly and should be used instead.
2. Factory test' modes. On future devices, factory
test modes will be entered by holding the ALE,
RD, WR and PWM pins in their active states on
the rising edge of RESET. ALE, RD and WR are
active low, and PWM is active high. During RESET, these pins will be held inactive by semistrong devices. These semi-strong devices will
sink or source about 2 mA and still stay above VIH
or below VIL. Factory test modes are reserved by
Intel. However, a system must be designed so
that it does not inadvertantly enter one of these
modes.
The PWM pin is the qualifier. If the PWM pin is
above VIL and any of the other pins are below
VIH, the device may enter a factory test mode. A
system must not override any of these semistrong devices.

80C198 DESIGN CONSIDERATIONS
In order to remain compatible with future versions of
the 80C198, the following design considerations
need to be taken into account when implementing
an 80C198 design:
1. Reserved Bits in SFR spaGe. Reserved bits must
always be written as zeroes when writing to an
SFR that has reserved bits. Never rely on the
state of a reserved bit. when reading an SFR as
these bits are indeterminate. Reserved bits include:
Program Status Word bit two (PSW.2)
Window Select Register bits four through six
(WSR.4-.6)
.
110 Control Register Two bit three (IOC2.3)
AID Command Register bits four through seven (AD_COMMAND.4-.7)
Serial Port Control Register bits five through
seven (SP_CON.5-.7)
AID Result LO Register bits four and five
(AD_RESULT_L0.4-.5)
Serial Port Status Register bits zero and one
(SP_STAT.0-.1)
Interrupt Mask
(IMASK1.7)

one

bit

2. Location 201 AH is reserved for use by Intel and
must contain OFFH.
3. HSO commands OCH and ODH are reserved and
must not be used.
4. All unused Windows are reserved and must never
be accessed.
5. Do not toggle the EA pin when the device is executing.
6. The device will make use of many of the unimplemented opcodes and these opcodes will no longer cause an umimplemented opcode interrupt.
7. On future devices, An AID conversion may take·
1.5 less states to complete. Do not base critical
timing .Ioops on an AID conversion time.
8. The ONCE (ON Circuit Emulator) mode will be entered differently. ONCE is currently entered by
holding ALE high, and INST, RD, and EA low on
the rising edge of RESET. For future versions, the
ONCE mode will be entered by holding the TxD
(P2.0) pin low on the riSing edge of RESET.
ONCE mode entry is primarily a concern for emulators. However, a system needs to be designed so it
will not enter ONCE. Currently, the TXD pin is weakly
driven high during RESET. For future versions, the
TXD pin will be semi-strongly driven high during
RESET so an external load will not pull the TXD pin
below VIH and put the device into ONCE. The TXD
pin on future devices will source about 2.0 mA and
still remain above VIH. A system must not pull more
than 2.0 mA from the TXD pin during RESET or the
device will enter the ONCE mode.
9. RESET. The RESET pin currently must be held
low for a minimum of 4 states for a valid device
Reset. The two internal Reset sources, WDT
overflow and RST instruction, also drive the
RESET pin low for 4 states.
On future versions, the RESET pin must be held low
for a minimum of 16 states for a valid device Reset.
To remain compatible, always assert the RESET pin
for at least 16 states. The internal' Reset sources will
also drive the pin low for 16 states.
Also, future versions will take 5 to 8 more state times
from the rising edge of RESET to begin executing
from location 2080H.

seven

4-171

83C198/80C198,83C194/80C194
t, PORT1 is a qUlisi-bidirectional port.

REVISION HISTORY

1. PORT

This data sheet (270815-002) is valid for devices
with a "B" at the end of the topside tracking number.

A. HOLD/HLDA. This Jeature is multiplexed on
PORT1.5-.7 and Is not available.
2. The AID converter loses four of its input channels, ACHO-3.

The following differences exist between this and the
001 version of the 80C198 data sheet.
1. Vss pin description was altered to reflect the correct number of pins.
2. VIH2 min was changed from changed 2.2V to
2.6V.
3. Max IpD was added and the IpD note was deleted.
For more detailed information on the 80C198, refer to the 80C196KB User's Manual, Order #
270651. The 80Ct96KB User's Guide applies to
the 80C198 except for the design considerations
listed above. Because the 80C198 is a reduced
pin count version, some 80C196KB features are
not available and are listed here:

3. T2CAPTURE (P2.7) Timer2 Capture feature is not
available.
.
.
4. T2UP/DN (P2.6) The Timer2 UP/DOWN feature
is not available.
5.
6.
7.
8.

4-172

CLKOUT
NMI
BUSWIDTH
BHE

87C 198/87C 194
16-BIT CHMOS MICROCONTROLLER
8 Kbytes of OTPROM

•
•
•
•
•
•
•
•
•

8 Kbytes of On-Chip OTPROM
232 Byte Register File
Reglster-to-Register Architecture
28 Interrupt Sources/16 Vectors
2.3 ,""S 16 x 16 Multiply (12 MHz)
4.0 ,""S 32/16 Divide (12 MHz)
Powerdown and Idle Modes
16-Bit Watchdog Timer
8-Bit External Bus

•
•
•
•
•
•
••
•

Full Duplex Serial ~ort
High Speed I/O Subsystem
16-Bit Timer
16-Bit Counter
Pulse-Width-Modulated Output
Four 16-Blt Software Timers
10-Blt A/D Converter with Sample/Hold
The 87C194 is an 87C198 without an
On-Chip A/D Converter

The 87C198 is the one time user programmable version of the low-cost 83C198/80C198. The 8XC198 family
offers low-cost entry into Intel's powerful MCS-96® 16-bit microcontroller architectur~. Intel's CHMOS process
provides a high performance processor along with low power consumption. To further reduce power requirements, the processor can be placed into Idle or Powerdown Mode.
The 87C198 has 8 Kbytes of

on-~hip

One Time Programmable Read Only Memory (OTPROM).

Bit, byte, word and some 32-bit operations are available on the 87C198. With a 12 MHz oscillator a 16-bit
addition takes 0.66 f.Ls, and the instruction times average 0.5 f.Ls to 1.5 f.Ls in typic~1 applications.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or counter.
Also provided on-chip are an AID converter, serial port, watchdog timer, and a pulse-width-modulated output
signal.
V EF"

ANGNO

CONTROL
SIGNALS

PORT 3

ADOR
} DATA
BUS
PORT 4

HSI

270899-1

Figure 1. 87C198 Block Diagram

MCS®-96 is a registered trademark of Intel Corporation.

4-173

October 1990
Order Number: 270899-001

inter

87C198/87C194

PACKAGING
The 87C198 and 87C194 are available in a 52-pin
PLCC package and an 80-pin QFP package. Contact
your local sales office to determine the exact ordering code for the part desired.

87C19X

With AID

Without AID

N87C198-PLCC
S87C198-QFP

N87C194-PLCC
S87C194-QFP

The 87C194 is an 87C198 without the AID converter.

tl >~t!
x x
'~

If';

>-~

Jl ~

~ 1li1

COl

...'" .;...

"c
0

00(

c
00(

ACH5/PO.5

AD2/P3.2

ACH4/PO.4

AD3/P3.3

ANGND

AD4/P3.4

vREr
vss

AD5/P3.5
AD6/P3.6

inter

EXTINT/P2.2
RESET
RXD/P2.1

AD7/P3.7
A8/P4.0
A9/P4.1

TOP VIEW

TXD/P2.0

A10/P4.2

HSI.O

A11/P4.3

HSI.1

A12/P4.4

HSO.4/HSI.2

A13/P4.5

HSO.5/HSI.3

A14/P4.6

III
•
~
0VI 0Vl VI
0 >"''''
0
Vl

:I:

i ,...~ I~ ..... >-c~ '"... "...
'" '"
;::.
:::E

'" "'"
'"'">- U'">Vl

..J

Figure 2. 52-Pin PLCC Package

4-174

Q.
of)

:;c
270899-2

87C 198/87C 194

SO-Pin Quad Flat Pack (EIAJ)
Contacts '
Facing Up

Contacts
Foclng Down

PIN NO 1 MARK
65

41
40

270A99- 3

Top View

!l!!!!!!!!!!!!!!
~ ~ ~ ~ ~ ~ ~ ~ ~

; R~

~ ~ ~ ~

AD1/P3.1

ADO/P3.0

63
62

Rii

ALEji\DV

INST

XTAL2
XTAL1
10

VSS

Vee
Vee

VSS
N.C.

N.C.

ACH6/PO.6

ACH7/PO.7

N.C.

ACH5/PO.5

....-..-..:.

T2RST/P2.4
N.C.

ViR

PWM/P2.5

N.C.

Vpp

VSS

Vss

HSO.3

Vss
READY

VSS
N.C.

VSS

T2CLK/P2.3

51
50

Vee
VSS
HSO.2

N.C.

HSO.1

HSO.O

HSO.5/HSI.3

VSS
HSO.4/HSI.2

ACH4/PO.4

!!!!!!!!!!!!!!!l
270899-4

Figure 3. SO-Pin Quad Flat Pack (QFP)

4·175

87C1.98/87C194

PIN DESCRIPTIONS
Symbol

Name and Function

Vee

Main supply voltage (5V).

V~s

The PLCC package has 5 Vss pins and the QFP package has 12 Vss pins. All must be
connected to circuit ground.

VREF

Reference voitage for the AID converter (5V). VRI::F is ~Iso the supply voltage to the
analog portion of the AID converter and the logic used to read Port O. Must be
connected for AID and Port 0 to function .

ANGND

Reference ground for the AID converter. Must be held at nominally the same potential
as Vss.
Programming Voltage. Also, timing pin for the return from powerdown circuit. Connect
this pin with a 1 IJ.F capacitor to Vss. If this function is not used, connect to Vee.

._----

Vpp
XTAL1

Input of the oscillator inverter and of the internal clock generator.

XTAL2

Output of the oscillator inverter.

RESET

Reset input to the chip. Input low for at least 4 state times to reset the chip. The
subsequent low-to-high transition commences the Reset Sequence in which the PSW is
cleared, a byte read from 2018H loads CCR, and a jump to location 2080H is executed.
Input high tor ~ormal operation. RESET has an internal pullup.

INST

Output high during an external memory read indicates the read is an instruction fetch.
INST is valid throughout the bus cycle. INST is activated only during external memory
accesses and output low for a data fetch.

Input for memory select (External Access). EA equal to a TTL-high causes memory
accesses to locations 2000H through 3FFFH to be directed td on-chip ROM/EPROM.
EA equal to a TTL-low causes accesses to these locations to be directed to Off-chip
memory

ALE/ADV

Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive high at the end of the bus cycle. ADV can be used as a chip select
for external memory. ALE/ ADV is activated only during external memory accesses.

Read signal output to external memory. RD is activated only during external memory
reads .

Write output to external memory. WR will go low for every external write.
-

._ - -

4-176

inter

87C198/87C194

PIN DESCRIPTIONS (Continued)
Symbol

Name and Function

READY

Ready input to lengthen external memory cycles, for interfacing to slow or dynamic
memory, or for bus sharing. If the pin is high, CPU operation continues in a normal
manner. When the extf!r:1al memory is not being used, READY has no effect. Internal
control of the number of wait states inserted into a bus cycle held not ready is available
through configuration of CCA.

HSI

Inputs to High Speed Input Unit. Four HSI pins are available: HSI.O, HSI.1, HSI.2; and
HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.

HSO

Outputs from High Speed Output Unit. Six HSO pins are available: HSO.O, HSO.1,
HSO.2, HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the
HSI Unit.

Port 0

4-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter. These pins set the Programming Mode on
the EPROM device.

Port 2

Multi-functional port. All of its pins are shared with other functions in the 80C198.

Ports 3 and 4

TxD

The TxD pin is used for serial port transmission in Modes 1, 2, and 3. The TxD function is
enabled by setting IOC1 5. In mode 0 the pin is used as the serial clock output.

RxD

Serial Port Receive pin used for serial port reception. The RxD function is enabled by
setting SPCON.3. In mode 0 the pin functions as input or output data.

EXTINT

A positive transition on the EXTINT pin will generate an external interrupt. EXTINT is
selected as the external interrupt source by setting IOC1.1 high.

T2CLK

The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input.

T2RST

A rising edge on the T2RST pin will reset Timer2. The external reset function is enabled
by setting IOCO.03 T2RST is enabled as the reset source by clearing IOCO.5.

PWM

Port 2.5 can be enabled as a PWM output by setting IOC1.0 The duty cycle of the PWM
is determined by the value loaded into the PWM-CONTROL register (17H).

4-177

inter

87C198/87C194

MEMORY MAP
OFFFFH
EXTERNAL MEMORY OR I/O
4000H
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY
20S0H
RESERVED
2040H
UPPER 8 INTERRUPT VECTORS
2030H
ROM/EPROM SECURITY KEY
2020H
RESERVED
2019H
CHIP CONFIGURATION BYTE
201SH
RESERVED
2014H
LOWER S INTERRUPT VECTORS
PLUS 2 SPECIAL INTERRUPTS
2000H
PORT 3 AND PORT 4
lFFEH
EXTERNAL MEMORY OR I/O
0100H
INTERNAL DATA MEMORY - REGISTER FILE
(STACK POINTER, RAM AND SFRS)
EXTERNAL PROGRAM CODE MEMORY

19H
lSH

19H

STACK POINTER

OOOOH

STACK POINTER

lSH

17H

IOS2

17H

PWM CONTROL

16H

10Sl

16H

10Cl

15H

10SO

15H

lOCO

14H

WSR

14H

WSR

13H

INT_MASKl

13H

INT~ASKl

12H

INT_PENDl

12H

INT_PENDl

llH

SP_STAT

llH

SP_CON

10H

PORT2

10H

PORT2

10H

RESERVED (1)

OFH

RESERVED (1)

OFH

RESERVED (1)

OFH

RESERVED (1)

OEH

PORTO

OEH

BAUD RATE

OEH

RESERVED (1)

ODH

TlMER2(HI)

ODH

TIMER2 (HI)

ODH

RESERVED (1)

OCH

.TIMER2 (LO)

OCH

TIMER2(LO)

OCH

RESERVED (1)

OBH

TIMERl (HI)

OBH

IOC2

OAH

TIMERl (LO)

OAH

WATCHDOG

QSH

INT PENDING

OSH

INT PENDING

OSH

INT MASK

OSH

INT MASK

07H

SBUF(RX)

07H

SBUF(TX)

06H

HSI STATUS

06H

HSO_COMMAND

05H

HSI_TIME (HI)

OSH

HSO_TIME (HI)

04H

HSI_TIME (LO)

04H

HSO_TIME (LO)

03H

AD_RESULT (HI)

03H

HSI

02H

·AD RESULT (LO)

02H

AD COMMAND

WSR

OTHER SFRS IN WSR
15 BECOME READABLE
IF THEY WERE WRITABLE
INWSR ~ o AND WRITABLE
IF THEY WERE READABLE
INWSR ~ 0

MODE

01H

ZERO REG (HI)

01H

ZERO REG (HI)

OOH

ZERO REG (LO)

OOH

ZERO REG (LO)

NOTE:
1. Reserved registers should not be wntten.

WHEN READ

WSR

WHEN WRITTEN

4-178

inter

87C198/87C194

.SFR BIT SUMMARY
AD_Command (02H) ,

AD-Result (LO) (02H)

AID CHANNEL NUMBER
STATUS:
0= AID CURRENTLY IDLE
X
1 = CONVERSION IN PROCESS

3 -

I-X

I-X
t--

AID RESULT:
• LEAST SIGNIFICANT 2 BITS

CHANNEL # SELECTS WHICH OF THE 4
ANALOG INPUT CHANNELS IS TO BE
CONVERTED TO DIGITAL FORM.
GO INDICATES WHEN THE CONVERSiON is TO
BE INITIATED (GO = 1 MEANS START NOW,
GO = 0 MEANS THE CONVERSION IS TO BE
INITIATED BY THE HSO UNIT AT A S'PECIFIED TIME).
SET UPPER FOUR BITS TO ZERO .

.....
X

270899-6

270899-5

Chip Configuration (2018H)

WSR (14H)

71s1514131211 10 ICHIP CONFIGURATION REGISTER
0= SFR'. FUNCTION UKE SUPERSET OF B09SBH
14( 1110B} = PPW REGISTER
15(1111B)=EXCHANGE READ/WRITE REGISTERS
OTHER = UNDEFINED, DO NOT USE,

L,:POWERDOWN MODE ENABLE

-0

o
o
o
o

ADDRESS VALID STROBE SELECT
(ALEI ADV)
(IRCO) } INTERNAL READY CONTROL
(IRC1)

MODE

270899-8
(LOCO) }
(LOC1) PROGRAM LOCK MODE
270899-7

HSI_Mode (03H)

HSI_Status (OSH)

15 41

11 10 1

HSI.O MODE

HSI.O STATUS

L----HSI.1 MODE

HSI.1 STATUS

' - - - - - - - H S I . 2 MODE

HSI.2 STATUS

......- - - - - - - - H S I . 3 MODE

HSI.3 STATUS

WHERE EACH 2 - BIT MODE CONTROL FIELD
DEFINES ONE OF 4 POSSIBLE MODES:
00
01
10
11

WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT INDICATES WHETHER OR NOT AN EVENT HAS
OCCURED ON THIS PIN AND THE UPPER BIT INDICATES
THE CURRENT STATUS OF THE PIN.
270899-10

B POSITIVE TRANSITIONS
EACH POSITIVE TRANSITION
EACH NEGATIVE TRANSITION
EVERY TRANSITION
(POSITiVE AND NEGATiVE)
270899-9

4-179

87C198/87C194

tNT_PEND/tNT_MASK (09H/OSH)
TiMER OVERFLOW

TRANSMIT INTERRUPT

AID CONVERSION COMPLETE

RECEIVE INTERRUPT

HSI DATA AVAILAIiiLE

HSI FIFO 4

HIGH SPEED OUTPUTS

(SET TO 0)

HSI.O PIN

TIMER 2 OVERFLOW

SOFTWARE TIMER

EXTINT 1

SERIAL PORT

HSI FIFO FULL

(SET TO 0)

EXTERNAL INTERRUPT

270899-12

270899-11

SP_CON (11H)

W
R
I
T
E

BIT.1, BI.1.O SPECIFY THE MODE
O.O=MODEO 1.0 = MODE 2
0.1 =MODE 1 1.1 =MODE3

PEN ENABLE THE PARITY FUNCTION

REN ENABLES THE RECEIVE FUNCTION:

TRANSMITIER EMPTY

TB8 PROGRAMS THE 9TH DATA BIT

FRAMING ERROR

SET UPPER THREE
BITS TO ZERO

X
X

RECEIVE OVERRUN ERROR

TRANSMIT INDICATOR
RECEIVE INDICATOR
RECEIVE PARITY ERROR

270899-14

270899-13

HSO Command (06H)
CHANNEL: 0-5 HSO.O - HSO.5 INDIVIDUALLY
BIT:

0]6
7
8-B
2
C-D
E
3
F

HSO.O AND HSO.l
HSO.2 AND HSO.3
SOFTWARE TIMERS
RESERVED FOR FUTURE USE
RESET TIMER2
START A I D CONVERSION
,
INTERRUPT I NO INTERRUPT
SET ICLE;AR
TIMER 2/TIMER 1

LOCK CAM
270899-15

,4·180

87C198/87C194

lOCO (15H)

IOSO(15H)
'HSO.O CURRENT STATE

HSI.O INPUT ENABLE I

HSO.l CURRENT STATE

TIMER 2 RESET EACH WRITE

DiSABI'E

HSO.2 CURRENT STATE

HSI.l INPUT ENABLE I

HSO.3 CURRENT STATE

TIMER 2 EXTERNAL RESET ENABLE I DISABLE

DiSABI'E

HSO.4 CURRENT STATE

HSI.2 INPUT ENABLE I DISABLE

HSO.5 CURRENT STATE

TIMER 2 RESET SOURCE HSI.O I T2RST

CAM Q!! HOLDING REGISTER IS FULL

HSI.3 INPUT ENABLE I DISABLE

HSO HOLDING REGISTER IS FULL

TIMER 2 CLOCK SOURCE HSI.l

'----

T2CLK

270899-16

270899-17

IOS1 (16H)

IOC1 (16H)

SOFlWARE TIMER 0 EXPIRED

SELECT PWM I SELECT P2.5

SOFlWARE TIMER 1 EXPIRED

EXTERNAL INTERRUPT ACH7 I EXTINT

SOFlWARE TIMER 2 EXPIRED

TIMER 1 OVERFLOW INTERRUPT ENABLE I DISABLE

SOFlWARE TIMER 3 EXPIRED

TIMER 2 OVERFLOW INTERRUPT ENABLE I DISABLE

TIMER 2 HAS OVERFLOW

HSO.4 OUTPUT ENABLE I DISABLE

TIMER 1 HAS OVERFLOW

SELECT TXD I SELECT P2.0

HSI FIFO IS FULL

HSO.5 OUTPUT ENABLE I DISABLE

HSI HOLDING REGISTER DATA AVAILABLE

HSI INTERRUPT
FIFO FULL I H'""O"'L-=D"'"INC::G-:R"'E""GI""ST=E"'R"'7L-=O""'AD"'E"'D

270899-18

270899-19

IOS2 (17H)

IOC2(OBH)

INDICATES WHICH HSO EVENT OCCURED

ENABLE FAST INCREMENT OF T2

HSO.O

HSO.l

ENABLE +2 PRESCALER ON PWM

HSO.2

X (SET TO 0)

HSO.3

AID CLOCK PRES CALER DISABLE

HSO.4

T2 ALTERNATE INTERRUPT

HSO.5

ENABLE LOCKED CAM ENTRIES

T2RESET

CLEAR ENTIRE CAM

START AID

BOOOH

270899-21,
270899-20

4-181

87C198/87C194

ELECTRICAL CHARACTERISTICS

NOTICE: This document contains information on
products in the design phase of development. Do not
finalize a design with this information. Revised information will be published when the product is available.
'

Absolute Maximum Ratings*
Ambient Temperature
Under Bias ...... : ............... O°C to + 7.0°C

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond .the "Operating Conditions"
. may affect device reliability.

Storage Temperature .......... - 65°C to + 150°C
Voltage On Any Pin to Vss ........ -0.5V to+ 7.0V
Power Dissipation ..... : .................... 1.5W

Operating Conditions
Symbol

Description

Min

Max

Units

Ambient Temperature Under Bias

+70

°C

Vee

Digital Supply Voltage

4.50

5.50

VREF

Analog Supply Voltage

4.50

5.50

fose

Oscillator Frequency

3.5

MHz

NOTE:
ANGND and Vss should be nominally at the same potential.

D.C. Characteristics
Symbol

(Over specified operating conditions)

Description

Min
-0.5

. Max
0.8

Units

Test Conditions

Vil

Input Low Voltage

VIH

Input High Voltage (Note 1)

VIH1

Input High Voltage on XTAL 1

0.7 Vee

Vee + 0.5

VIH2

Input High Voltage on RESET

2.6

Vee + 0.5

Val

Output Low Voltage

0.3
0.45
1.5

V
V
V

VOH

Output High Voltage
(Standard Outputs)

III

Input Leakage Current (Std. Inputs)

±10

/LA

= 200/LA
= 32 mA
= 7 mA
IOH = - 200 /LA
IOH = -3.2 mA
IOH = -7mA
o < VIN < Vee -

ILl1

Input Leakage Current (Port 0)

/LA

0< VIN < VREF

11L1

Logical 0 Input Current in Reset(Note 2)
(ALE, RD, INST)

-6

VIN

0.2 Vee + 1.0 Vee + 0.5

V
V
V

Vee - 0.3
Vee - 0.7
Vee - 1.5

NOTE:
1. All pins except RESET and XTAL 1.
2. Holding these pins below VIH in Reset may cause the part to enter test modes.

4-182

IOL
IOl
IOl

0.45 V

0.3V

inter

87C198/87C194

D.C. Characteristics
Symbol

(Over specified operating conditions) (Continued)

Description

Min

Typ(6)

Max

Units

rnA

XTAL1

/-LA

Vee

65K

Icc

Active Mode Current in Reset

IREF'

AID Converter Reference Current

IIDLE

Idle Mode Current

ICC1

Active Mode Current

IpD

Powerdown Mode Current

RRST

Reset Pullup Resistor

Pin Capacitance (Any Pin to VSS)

61<

Test Conditions
XTAL1 = 12 MHz
Vee = Vpp = VREF

foreST

!).5V

5.5V

3.5 MHz

Vpp ;,. VREF

1.0 MHz

NOTES:
,
(Notes apply to all specifications)
1. Standard Olltputs include ADO-15, RD, WR, ALE, INST, HSO pins, PWM/P2.5, RESET, Ports 3 and 4, TXD/P2.0, and
RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
2. Standard Inputs include HSI pins, EA, READY, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3, and T2RST/P2.4.
3. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on Standard Output pins: 10 mA
4. Maximum current per bus pin (data and control) during normal operation is ±3.2 mAo
5. During normal (non-transient) conditions the following total' current limits apply:
HSO, P2.0, RXD, RESET IOL: 29 rnA IOH: 26 rnA
IOL: 13 rnA IOH: 11 rnA
P2.5, WR
ADO-AD15
IOL: 52 rnA IOH: 52 rnA
RD, ALE, INST
IOL: 13 rnA IOH: 13 rnA
6. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V.

, 60

r----,---,..--.,
Icct.lAX

50~----+------r--~~

40 1------+---~-__::..I1cc TYPICAL (7)
ICC
mA

30 ~----+-~"'---j;,~---l

10 I-------:!'OO~--_I_--_=-' IIDLE TYPICAL
o~-~~--~--~

ICC Max = 3.88 x FREQ + 8.43
IIDLE Max = 1.65 X FREQ + 2.2

4t.lHz

8t.lHz

12t.lHz

F'REQ

Figure 4. Icc and IIDLE VB Frequency

4~183

270899-22

87C198/87C194

A.C. Characteristics
For use ~)VE!r specified operating conditions
Test Conditions: Capacitive load on all pins

= 100 pF, Rise and 'fall times = 10 ns, fose = 12 MHz

The system must meet these specifications to work with the 87C198:
Symbol

Description

TAVYV

Address Valid to Ready Setup

TLLYV

ALE Low to READY Setup

TYLYH

Non READY Time

Min
~

Max

Units

2Tose - 85

. Tos~ - 70

, ns

No upper limit

Notes

TLLYX

READY Hold after ALE Low

2Tose - 40

(Note 1)

TAVDV

Address Valid to Input Data Valid

3Tose - 60

(Note 2)

TRLDV

RD Active to Input Data Valid

Tose - 23

(Note 2)

TRHDZ

End of RD to Input Data Float

Tose - 20

TRXDX

Data Hold after RD Inactive

Tose - 15

NOTES:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2T OSC x n, where n = number of wait states.

",' I,:'

4·184

87C198/87C194

A.C. Characteristics
For use over specified operating conditions
Test Conditions: Capapitive load on all pins = 100 pF, Rise and fall times = 10 ns, fose = 12 MHz

The 87C198 will meet these specifications:
Symbol

Description

Min

Max

Units

Notes
(Note 1)

FXTAL

Frequency on XTAL1

3.5

MHz

Tose

II FXTAL

286

TLHLH

ALE Cycle Time

TLHLL

ALE High Period

Tose - 10

TAVLL

Address Setup to ALE Falling Edge,

Tose - 20

TLLAX

Address Hold after ALE Falling Edge

Tose - 40

TLLRL

ALE Falling Edge to RD Falling Edge

Tose - 30

TRLRH

RD Low Period

TRHLH

RD Rising Edge to ALE Rising Edge

Tose - 5
Tose

(Note 4)

4Tose
Tose+ 10

Tose
Tose

+ 25
+ 25

(Note 4)

(Note 3)

TRLAZ

RD Low to Address Float

hLWL

ALE Falling Edge to WR Falling Edge

Tose - 10

TQVWH

Data Stable to WR Rising Edge

Tose - 23

(Note 4)

TWLWH

WR Low Period

Tose - 30

(Note 4)

TWHQX

Data Hold after WR Rising Edge

Tose - 2.5

TWHLH

WR Rising Edge to ALE Rising Edge

Tose - 10

TWHBX

INST Hold after WR Rising Edge

Tose - 10

TRHBX

INST Hold after RD Rising Edge

Tose - 10

TWHAX

AD8-15 Hold after WR Rising Edge

Tose - 50

TRHAX

AD8-15 Hold after RD RiSing Edge

Tose - 25

Tose

ns
"

NOTES:
1.
2.
3.
4.

Testing performed at 3.5 MHz. However, the part is static by design and will typically operate below 1 Hz.
Typical specification, not guaranteed.
Assuming back-to-back bus cycles.
When using wait states, add 2Tase x n, where n = number of wait states.

4-185

(Note 3)

87C198/87C194

System Bus Timings

XTAL1

ALE

--1

tLHLH

I-- tLHLL- I-- tLLRL- f.--

tRLRH

---I-- tRHLH .....

r-BUS

--(

t AVLL -

f.- tLLAX

tAVDV

I-- t LLWL

BUS

DATA

~ tWLWH - :
I--tOVWH

. ADDRESS OUT

,}'I..(

»»)~,
I--tWHLH .....

tWHo~1

DATA OUT.

I
BHE,INST

>---<.1

ADDRESS OUT

I--

I
tRLDV

VALID

II-

}X(

ADDRESS

tRHBX..,
tWHBX

tRHAX..,
tWHAX

A8-1S

ADDRESS OUT

270899-23

4,186

inter

87C198/87C194

READY Timings (One Waitstate)

XTAL1

ALE

READY

_+______""""\ 1 + - - - - tRLRH + 2Tose ----1---------1+--------

~--AD-DR-ES-S-OU-T--~)

:==I
-----1--1
{~-DA-~~»~»)m»~--------

tRLDV + 2 Tose
t AVDV + 2Tose

_~~~~~~~~~~~~~~~~_~:.:~~-----tw-L-W-H-+-2-T-os-e--4
--j,._ _ _ _ _ _ __
,.

1-01·>---- t QVWH + 2 Tose ~

~--A-D-DR-E-SS-OU-T--.u)~~(~-----D-AT-A-O-U-T------JX~__A_DD_R_ES_S__
I

270899-24

4·187

87C198/87C194

EXTERNAL CLOCK DRIVE
Symbol

Parameter

Min

Max

Units

1/TXLXL

Oscillator Frequency

TXLXL

Oscillator Period

3.5

12.0

MHz

286

TXHXX

High Time

TXLXX

Low Time

TXLXH

Rise Time

TXHXL

Fall Time

EXTERNAL CLOCK DRIVE WAVEFORMS

270899-25

An external oscillator may encounter as much as a 100 pF load at XTAL 1 when it starts-up. This is due to
interaction between the amplifier. and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed 20 pF.
A.C. TESTING INPUT, OUTPUT WAVEFORM

2.4

0: 45

-V
.--A

2.0> TEST POINTS

0.8

2.0

0.8 .

270899-26

A.C. Testing inputs are driven at 2.4V for a LogiC "1" and 0.45V
for a LogiC "0" Timing measurements are made at 2.0V for a
LogiC "1" and 0.8V for a LogiC "0".

FLOAT WAVEFORM

r-------_

VLOA O+O.20V
vLOAO
"",-----TIMING REFERENCE...___
---POINTS
-...........
VLOAO-O.20V - - - - - - - - 270899-27
For Timing Purposes a Port Pin is no Longer Floating when a
200 mV change from Load Voltage Occurs and Begins to Float
when a 200 mV change from the Loaded VOHIVOl Level occurs
IOl/loH ~ ± 15 mAo

EXPLANATION OF AC SYMBOLS

Each symbol is two pairs of letters prefixed by "T" for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.

Conditions:
H
High
L
- Low
V
Valid
No Longer Valid
X
Z
Floating

Signals:
A
- Address
D
- DATA IN
L
- ALE/ADV
Q
- DATA OUT
R
RD
W
WR
X
XTAL1
Y
READY

inter

87C198/87C194

EPROM SPECIFICATIONS
A.C. ~PROM Programming Characteristics
Operating Conditions: Load Capacitance = 150 pF, TA
OV, VPP = 12.7SV ±0.2SV, EA = 12.7SV ±0.2S

Symbol

+25°C ±5°C, Vee, VREF

Description

Min

SV, Vss, ANGND

Max

Units

TSHLL

Reset High to First PALE Low

TLLLH

PALE Pulse Width

TAVLL
TLLAX
TLLVL

PALE Low to PVER Low

Tosc

TpLDV

PROG Low to Word Dump Valid

Tosc

TpHDX

1100

Tosc

Address Setup Time

Tosc

Address Hold Time

Tosc

' Word Dump Data Hold

TDVPL

Data Setup Time

Tosc

TpLDX

Data Hold Time

Tosc

TpHLL

PROG High to Next PALE Low

120

Tosc

TLHPL

PALE High to PROGLow

220

Tosc

TpHPL

PROG High to Next PROG Low

120

Tosc

TpLPH

. PROG Pulse Width

TpHIL

PROG High to AINC Low

Tosc

TILIH

AINC Pulse Width

Tosc

TILVH

PVER Hold after AINC Low

Tosc

TILPL

AINC Low to PROG Low

170

Tosc

TPHVL

PROG High to PVER Low

Tosc

NOTES:

1. Run Time Programming is done with Fosc = 6.0 MHz to 12.0 MHz, VREF = 5V ± 0.65V. TA
Vpp = 12.75V. For run-time programming over a full operating range, contact the factory.

+ 25°e to ± 5°C and

D.C. EPROM Programming Characteristics
Symbol

.Descrlption

Min

Ipp

VPP Supply Current (when Programming)

NOTE:

Vpp must be within 1V of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground or Vss while
Vee> 4.5V.

4·189

inter

87C 198/8,7C 194

EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE W.ITH SINGLE PROGRAM PULSE

PORTS
3/<

--t--~~$~~~

PVER

270899-28

SLAVE PROGRAM MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT

.. I.

270899-29

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE
AND AUTO INCREMENT

ADOR

-«

PO:;: _ _ _

Aoo./eO".ANO

>---<:::!DA~TA~»>---:--

__----«

ADDR+ 2

DATA

>--

PVER

tPHIL

270899-30

4-190

87C198/87C194

A.C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol

Parameter

Min

TXLXL

Serial Port Clock Period (BRR 2 8002H)

TXLXH

Serial Port Clock Falling Edge
to Rising Edge (BRR 2 8002H)

TXLXL

Serial Port Clock Period (BRR

TXLXH

Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)

TOVXH

Max

Units

6 Tose

4 Tose ±50

4 Tose

2 Tose ±50

Output Data Setup to Clock Rising Edge

2 Tose -50

TXHOX

Output Data Hold after Clock Rising J;:dge

2 Tose -50

TXHOV

Next Output Data Valid after Clock Rising Edge

TOVXH

Input Data Setup to Clock Rising Edge

TXHOX

Input Data Hold after Clock Rising Edge

TXHOZ

Last Clock Rising to Output Float

8001 H)

2 Tose +50

ns
ns

Tose +50

0
1 Tose

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-'sHIFT REGISTER MODE

270899-31

4-191

inter

87C198/87C194

A TO D CHARACTERISTICS
There are two modes of AID operation: with or without clock prescaler. The speed of the AID converter
can' be adjusted by setting a clock prescaler on or
off. At high frequencies more time is needed for the
comparator to settle. The maximum frequency with
the clock prescaler disabled is 8 MHz. The conversion times with the prescaler turned on or off is
shown in the table below.
The converter is ratio metric, so the absolute
accuracy is directly dependent on the accuracy and

stability OfVREF. VREF must be close to Vee since it
supplies both the resistor ladder and the digital section of the converter.

AID CONVERTER SP,ECIFICATIONS
The specifications given below assume adherence
to the Operating Conditions section of this data
sheet. Testing is performed with VREF = 5.12V.
The 87C194 does not have an AID converter.

Clock Prescaler On
IOC2.4 = 0

Clock Prescaler Off
IOC2.4 = 1

158 States
26.33 p.s @ 12 MHz

91 States
22.75 p.s @ 8 MHz

Parameter

Typical(1)

Minimum

Maximum

Units'

512
9

1024
10

Levels
Bits

±4

LSBs

Resolution
Absolute Error
Full Scale Error
Zero Offset Error
Non-Linearity Error

0.25 ±0.50

LSBs

-0.25 ±0.50

LSBs

1.5 ±2.5

Differential Non-Linearity Error

±4

LSBs

> -1

LSBs

±1

LSBs

Channel-to-Channel Matching'

±0.1

Repeatability

±0.25

LSBs

Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity

0.009
0.009
0.009

LSBrC
LSBrC
LSBrC
-60

Off Isolation
Feedthrough

-60

Vee Power Supply Rejection

-60

Input Resistance
D.C. Input Leakage

3.0

2,3

n
p.A

Sample Time: Prescaler On
Prescaler Off

15
8

States
States

Input Capacitance

NOTES:
'An "LSB", as used here, has a value 01 approximately 5 mY.
1. Typical values are expected lor most devices at 25°e but are not tested or guaranteed.
2. De to 100 KHz.
3. Multiplexer Break-Belore·Make Guaranteed.
4. One state = 167 ns at 12 MHz, 250 ns at 8 MHz.

4-192

Notes

4
4

inter

87C198/87C194

87C198 FUNCTIONAL DEVIATIONS

REVISION HISTORY

The 87C198 has the following problems.
1. Factory test modes. On future devices, factory
test modes will be entered by holding the ALE,
RD, WR and PWM pins in their active states on
the rising edge of RESET. ALE, RD and WR are
active low, and PWM is active high. During RESET, these pins will be held inactive by semistrong devices. These semi-strong devices will
sink or source about 2 mA and still stay above VIH
or below VIL. Factory test modes are reserved by
Intel. However, a system must be designed so
that it does not inadvertently enter one of these
modes.
The PWM pin is the qualifier. If the PWM pin is
above VIL and any of the other pins are below
VIH, the device may enter a factory test mode. A
system must not override any of these semistrong devices.

This is the first version of the 87C198/87C194 Data
Sheet.
.
For more detailed information on the 87C198, refer to the 80C196KB User's Manual, Order
#270651. The 80C196KB User's GuIde applies to
the 87C198. Because the 87C198 is a reduced pin
count version, some 80C196KB features are not
available and are listed here:
1. PORT 1. PORT1 is a quasi-bidirectional port.
A. HOLD/HLDA. This feature is multiplexed on
PORT1.5-.7 and is not available.
2. The AID converter loses four of its input channels, ACHO-3.
3. T2CAPTURE (P2.7) Timer2 Capture feature is not
available.
4. T2UP/DN (P2.6) The Timer2 UP/DOWN feature
is not available.
5. CLKOUT
6. NMI
7. BUSWIDTH
8. SHE

4-193

MCS®-96
87C196KB/83C196KB/80C196KB

Express
•

Extended Temperature Range
( - 40°C to + 85°C)

•

Burn-In

The Intel EXPRESS system offers enhancements to the operational specifications of the MCS®:96 family of
microcQntroliers. These EXPRESS products are designed to meet the needs of those applications whose
operating requirements exceed commercial standards.
The EXPRESS program includes an extended temperature range with orwithout burn-in, depending on the package
type.
With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of O°C to +' 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to +' 85°C.
The optional burn-in is dynamic, for a minimum time of 160 hours at 125°C with Vcc = 5.5V ± 0.5V, following
.
guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
This data sheet specifies the parameters for the extended temperature range option. The commercial temperature
range data sheets including functional deviations are applicable otherwise.

VREF

ANGND

CONTROL
SIGNALS

PORT 3

} ~f~:
BUS

PORT 4

270590-1

Figure 1. 8XC196KB Block Diagram

Intel Corporation assumes no responsibilityforthe use of any circuitry other than circuitry embodied in an Intel product. No other circuit
patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
August 1989
© l[ltel Corporation, 1987
Order Number: 270780-002

4-194

8XC196KB,EXPRESS
Table 1. Express Prefix Identification
Prefix

Package,

Temperalure

Burn,-In

80C 196KB12/80C196TB12

LA
TN

PGA "
PLCC

Extended
Extended

' Yes
No

83C 196KB12/83C196TB12

filLCC

Extended

87C196KB10

LCC

Extended

Yes

Product

Table 2. Thermal'Cllaracteristlcs
Package Type
PGA

.28°CIW

PLCC

35°CIW

12°CIW

LCC

28°CIW

3.5°CIW

4·195

ajc

ala
"

3.5°CIW

8XC196KBEXPRESS

EXPRESS PACKAGING
The 80C196KBITB and 83C196KBITB are available in a 68~pin PLCC package. In addition, the80C196KBITB is
available in a 68-pin PGA package. The 87C196KB is only available in a 68-pin LCC package.

PGAI
LCC

PLCC

Description

PGAI
LCC

ACH7/PO.7

ACH6/PO.6

ACH2/PO.2

PLCC

Description

54
. 53

AD6/P3.6
AD7/P3.7
AD8/p4.0
. AD9/P4.1

PGAI
LCC

PLCC

Description

P1.6/HLDA

P1.5/BREQ

HSO.1

ACHO/PO.O

HSO.O

ACH1/pO.1

AD10.P4.2

HSO.5/HSL3

6
7

ACH3/PO.3

AD11/P4.3

HSO.4/HSL2

NMI

AD121P4.4

HSL1

HSLO

Vee

P1.4

P1.3

Vss
XTAL1

AD13/P4.5
AD14/P4.6
AD15/P4.7

3
2
1

T2CLKlP2.3

P1.2

XTAL2

READY

P1.1

CLKOUT

T2RST/P2.4/AINC

P1.0

BUSWIDTH

BHElWRH

TXD/P2.0

INST

WRIWRL

RXD/P2.1

ALE/ADV

PWM/P2.5

RESET

RD'

P2.71T2CAPTURE/PACT

EXTINT/P2.2

ADO/P3.0

Vpp

HSO.2/SID2

66
67

35
34

Vss
HSO.3/SID3

Vss
V REF
ANGND

ACH4/PO.4

ACH5/PO.5

AD1/P3.1
AD2/P3.2
AD3/P3.3

AD4/P3.4

P2.61T2UP-DN

AD5/P3.5

P1.7/HOLD

NOTE:

(1)

Figure 2. Pin Definitions

1. This pin was formerly the Clock Detect Enable Pin. The CDE function is not guaranteed t9 work, therefore this
pin must be directly connected to Vss'

Pins FaCing Down
7

18191614 1210 8

17 15 13 11
2021
2223
2425

~CSiP)-96
68 PIN
GRID ARRAY

3031
3233

6766
6564
6362
61 60

2627
2829

1'2 68

TOP VIEW
LOOKING DOWN ON
CO~PONENT SIDE
OF PC BOARD

5958
5756
5554

3436 38 40 4244 46 48 50 5352
35 37 39 41 43 45 47 49 51
270634-23

Figure 3. 68-Pin Package (Pin Grid Array - Top View) 80C196KB Only
·4-196

8XC196KB EXPRESS

ACH5/PO,5

1 68 67 66 65 64 63 62 61

AOO/P3,0

ACH4/PO,4

A01/P3,1

ANGND

AD2/P3,2

V REf

AD3/P3,l

MCS®-9.6
68 PIN
PLCC

'VSS

EXTINT/P2,2
RESET

AD4/P3.4
AD5/P3,5
AD6/P3,6

RXO/P2,1
TXO/P2,0

AD7/P3,7

P1.0

AD9/P4,1

AD&/R4,0
AD10/P4.2

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD

P1.1
P1.2
P1.3
P1.4

HSIO

ADll/PO
ADI2/P4,4
ADI3/P4,5 '
AD14/P46
AD15/P4.7

HSll

H512/H504

,
44
272,8 29 30 31 323334 35 36 37 38 3& 40 41 42 43

T2CLK/P2,3

270634-2

Figure 4. 58-Pin Package (PLCC-Top View) 83C196KB/80C196KB

.... co

....

...,

c:i c:i c:i c::i c:i c:i
~~.e::..e::.~~
.... co N O .... I")

.." .." ." "..

:>: :>: :>: :>: :>: :>:

~ ~

;'1
ACH5/PO,5

ACH4/PO.4

ANGND

VREF

v88

EXTINT/P2,2
RE5ET

..
::>

. ~ d.

Vl~
'i I~ ~ '"
z
> > x

~ Iii

::>

l!:

"~ 1~

1011 12 13 14 15 16 17 L

68 PIN

ADO/P3,0

AD1/P3,1

AD2/P3,2

AD3(P3,3

AD4/P3.4

ADS/P3,5

62 '

AD6/P3,6

A07/P3,7

RXO/P2,1

TXD/P2,0

PLO

Pt.1

P1.2

P1.3

P.l.4

H51.0

H51,1

H51.2/H50.4

LEADLESS CHIP CARRIER
TYPE "S"

0
(EPROM ONLY)
TOP VIEW

A08/P4,0

AD9/P4,1

A010/P4,2

A011/PO

AD12/PU

A013/P4,5

A014/P4,6

33 , A015/P4,7

52
34
., 51 50 49 48 47 46 45 44 43 4241 40 39 38 37 36 35 r"

T2CLK/P2,3

8 ~ ~ ~ ~:; ~ ~'~ ;>8:~

~ z

~ ~ ~ ~ x z

:>:

270680-2
(Top view looking down on component side of PC boards)

Figure 5. 58-Pin Package (LCC-Top View) 87C196KB Only

4-197

in1:el

8XC196KBEXPRESS
• Notice: Stresses above those listed under '~bso
lute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ................................... -40°C to +85°C
Storage Temperature ..................... -65°C to +150°C
Voltage On Any Pin to V ss ................ -0.5V to +7.0V

NOTICE Specifications contained within the
fol/owing tables are subject to change.

Power Dissipation ............................................. 1.5W

Operating Conditions
Symbol

•

Description

Min

Max

Units

Ambient Temperature Under Bias

-40

+85

·C

Vee

Digital Supply Voltage

4.50

5.50

VREF

Analog Supply Voltage

4.50

5.50

fose

Oscillator Frequency

3.5

MHz

NOTE:

ANGND and Vss should be nominally at the same potential.
This Is an Advance Data Sheet. It is expected that parameters may change before Intel releases this
product for sale. Contact your local sales office before finalizing the Timing ,and D.C. Characteristics
section of a design to verify you have the latest information.

D.C. Characteristics
Symbol
VIL

(Over specified operating conditions)

Description
• Input Low Voltage

Min

Max

Units

-0.5

0.8

VIH

Input High Voltage (Note 1)

VIH1

Input High Voltage on XTAL 1

VIH2

Input High Voltage on RESET

VOL

Output Low Voltage

VOH

Output High Voltage
(Standard Outputs)

Vee - 0.3
Vee - 0.7
Vee- 1.5

V
V
V

VOH1

Output High Voltage
(Quasi-bidirectional Outputs)

Vee - 0.3
Vee - 0.7
Vee - 1.5

V
V
V

III

Input Leakage Current (Std. Inputs)

ILl1

Input Leakage Current (Port 0)

0.2 Vee + 0.9 Vee + 0.5

0.7 Vee

Vee + 0.5

2.4

Vee + 0.5

0.3
0.45
1.5

V
V
V

Test Conditions

= 200/LA
= 3.2mA
= 7,mA
IOH = -200/LA
IOH = -3.2 mA
IOH = -7mA
IOH = -71lA
IOH = -30/LA
IOH = -60/LA

IOL
IOL
IOL

±10

/LA

±3

/LA

0< VIN < VREF

..,..650

ITL

1 to 0 Transition Current (QBD Pins)

/LA

VIN

IlL

Logical 0 Input Current (QBD Pins)

~50

/LA

VIN

IILl

Logical 0 Input Current in Reset (Note 2)
(ALE, RD, WR, BHE, INST,P2.0)

-1.2

VIN

NOTE:

1. All pins except RESET and XTAL 1.
,
2. Holding these pins below VIH in Reset may cause the part to enter test modes.
4-198

VIN < Vee - 0.3V

= 2.0V
= 0.45V
= 0.45 V

inl:el

8XC196KB EXPRESS

D.C. Characteristics
Symbol

(Over specified operating conditions) (Contirludd)

Description

Typ(7)

Min

Max

Units

Test Conditions
XTAL 1 = 12 MHz
Vcc = Vpp = VREF

Icc

Active Mode Current in Reset

rnA

IREF

AID Converter Reference Current

rnA

IIDLE

Idle Mode Current

2.5

rnA

ICCl

Active Mode Current in Reset

rnA

XTAL1

IpD(6)

Powerdown Mode Current

tJ-A

VCC

RRST.

Reset Pull up Resistor

Pin Capacitance (Any Pin to VSS)

100K

5.5V

3.5 MHz

= Vpp =

fTEST

VREF

1.0 MHz

NOTES:
(Notes apply to all specifications)
1. QSD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
"
2. Standard Outputs include ADO-15, RD, WR, ALE, SHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
'TXD/P2.0, and RXD (in serial mode 0). The V.Qt! specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
3. Standard Inputs include HSI pins, CDE, EA, READY, SUSWIDTH, NMI, RXD/P2,1, EXTINT/P2.2, T2CLK/P2.3, and
T2RST IP2.4.
4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held
below Vee - 0.7V:
IOL on Output pins: 10 mA
IOH on quasi-bidirectional pins: self limiting
IOH on Standard Output pins: 10 mA
5. Maximum current per bus pin (data and control) during normal operation is ±3.2 mAo
6. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6
IOL: 29 mA
IOH is self limiting
HSO, P2.0, RXD, RESET IOL: 29 mA
IOH: 26 mA
P2.5, P2.7, WR, SHE
IOL: 13 mA
IOH: 11 mA
ADO-AD15
IOL: 52 mA
IOH: 52 mA
RD, ALE, INST -CLKOUT IOL: 13 mA
IOH: 13 mA
.
7. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = 5V.
6. Ipo is not guaranteed on the standard 60C196KS part and may exceed 100 IJ.A on some parts. Customers whos.e applications use the powerdown mode and require a guaranteed maximum value of Ipo should contact an Intel Field Sales Representative.

60r------r-----,r-----~

40 f---+----:J~-__:;..! ICC lYPICAL (7)
ICC

rnA

30 f-------+-~fL-__j"""'----_j
20 f--___..::t-,"""''----c:J.....=---_jI,OLE MAX
10 f-----'9------If--:=:..-lIIDLE lYPICAL
O~----~----~~----~

ICC Max = 3.88 X FREO + 8.43
IIDLE Max = 1.65 X FREO + 5.2

4MHz

8MHz

12MHz

FREQ

Figure 6. Icc and IIDLE vs Frequency

4-199

270634-15

inter

8XC196KB 'EXPRESS

A.C. CHARACTERISTICS
For use over specified operating conditions
Test Conditions: Capacitive. load on. all pins'; 100 pF, Rise and fall times = 10 ns, fosc = 12 Mhz
The system must meet these specifications:

Symbol

Min

Description

Max

TAvyV

Address valid to READY setup
80C196KB12/83C196KB12
87C196KB10

T LLyV

ALE low to READY setup
80C196KB12/83C196KB12
87C196KB10

TYLYH

Non READY time

TCLYX

READY hold after CLKOUT low

TLLyX

READY hold after ALE low

TAVGV

Address valid to BUSWIDTH setup
80C196KB12/83C196KB12
87C196KB10

2Tosc-85
2Tosc-95

TLLGV

ALE low to BUSWIDTH setup
80C196KB12/83C196KB12
87C196KB10

Tosc--60
Tosc-85

TCLGX

BUSWIDTH hold after CLKOUT low

TAVDV

Address valid to input data valid
80C196KB12/83C196KB12
87C196KB10

TRLDV

Notes

2Toscr-85
2TosC:-105
Tosc-65
Tosc-95
No Upper Limit
0

Tosc-30

Note 1

Tosc-15

2Tosc-40

Note 1

0
3Tosc--60
3Tosc-80

Note 2

RD low to input data valid
80C 196KB 12/83C 196KB 12
87C196KB10

Tosc-25
Tosc-30

Note 2

TCLDV

CLKOUT low to input data valid
80C196KB12/83C196KB12
87C196KB10

Tosc-50
Tosc--60

T RHDZ

RD high to input data float

Tosc-20

T RXDX

Data hold after RD inactive

NOTE:
1. If max is exceeded, additional wait states will occur.
2. When using wait states, add 2Tosc x n where n = number of wait states.

4·200

8XC196KB EXPRESS

A.C. CHARACTERISTICS
For use over specified operating conditions
,
TestConditions: Capacitive load on all pins = 100 pF, Rise and fall.times = 10 ns, fosc =,12 Mhz
The 8XC196KB will meet these specifications:

Symbol
FXTAL

Tosc

T XHCH

Description

Min

Max

Notes

Frequen~y on XTAL 1
80C196KB12/83C196KB12
87C196KB10

3.5
3.5

12
10

Note 1
Note 1

1/FXTAL
80C 196KB12/83C 196KB 12
87C196KB10

83
100

286
286

XTAL 1 high to CLKOUT high or low
80C196KB12/83C196KB12
87C196KB10

35
40

110
130

Note 2

T CLCL

CLKOUT cycle time

T CHCL

CLKOUT high time

Tosc-10

Tosc+10

TCLLH

CLKOUT falling edge to ALE rising

-5

T LLCH

ALE falling edge to CLKOUT rising

-15

TLHLH

ALE cycle time

TLHLL

ALE high period

Tosc-12

T AVLL

Address setup to ALE falling

Tosc - 20

T LLAX

Address hold after ALE falling
80C196KB12/83C196KB12
87C196KB10

TLLRL

• T RLCL

2Tosc

4Tosc

ALE falling edge to RD falling
80C196KB12/83C196KB12
87C196KB10

Note 4
Tosc+12

Tosc-40
Tosc - 45
Tosc-40
Tosc-45

RD low to CLKOUT falling

Tosc- 5

Tosc+25

Tosc
Tosc

Tosc+25
Tosc+30

TRLRH

RD low period

TRHLH

RD rising edge.to ALE rising
80C196KB12/83C196KB12
87C196KB10

TRLAZ

RD low to address float

T LLWL

ALE falling edge to WR falling

TCLWL

CLKOUTlow to WR falling
80C196KB12/83C196KB12
87C196KB10

0
0

TOVWH

Data stable to WR rising
80C196KB12/83C196KB12
87C196KB10

Tosc-23
Tosc - 30

T CHWH

CLKOUT high to WR rising

-10

+10

T WLWH

WR low period

Tosc-30

Tosc+5

Note 4
Note 3

10
Tosc-10

4-201

25.
30
Note 4

Note 4

8XC196KB EXI:>RESS

A.C. CHARACTERISTICS (continued from page 8)
Symbol

Description

Min

TWHQX

Data hold after WR rising

Tosc-10

TWHLH

WR rising edge to ALE rising

Tosc-10

TWHBX

BHE, INST hold after WR rising

Tosc-10

TWHAX

AD8-15 hold after WR rising

Tosc-50

TRHBX

BHE, INST hold after RD rising

Tosc-10

TRHAX

AD8-15 hold after RD rising

Tosc-50

Max

Notes

Tosc+15

Note 3

NOTES:
1. Testing performed at 3.5 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Typical specification, not guaranteed.
3. Assuming.l;>ack-to-back bus cycles.
4. When using wait states, add 2 Tosc x n where n =number of wait states.

4-202

intel

8~C196KB EXPRESS

System Bus Timings

XTALl

CLKOUT

ALE

BUS

ADDRESS OUT

ADDRESS

BHE,INST

VALID

AD8-15

ADDRESS OUT
270634-24

4-203

aXC196KB EXPRESS

READY Timings (One Waitstate)

_TAVYV_
TRLRH + 2Tose
READ
T RLDV,+ 2Tose
TAVDV+ 2Tose
BUS

ADDRESS OUT

WRITE

TWLWH+ 2Tose

TOVWH+ 2Tose
BUS

ADDRESS OUT

DATA OUT

4·204

~
ADDRESS

8XC196KB EXPRESS

Buswidth Timings

XTAL1

CLKOUT

ALE

BUSWIDTH

~TAVGV
BUS

)~~(~_ _D_AT_A-J)~-------

ADDRESS OUT

4-205

inler

aXC196KB EXPRESS
HOLD/HLDA Timings

Symbol
THVCH

Description
--

Min
,

HOLD Setup

Max

Units

Notes

TCLHAL

-CLKOUT Low to HLDA Low

-15

TCLBRL

CLKOUT Low to BREQ Low

-15

THALAZ

HLDA Low to Address Float

-25

THALBZ

HLDA Low to SHE, INST, RD, WR Float

-30

TCLHAH

CLKOUT Low to HLDA High

-15

TCLBRH

CLKOUT Low to SREQ High

-15

THAHAX

HLDA High to Address No Longer Float

-5

IHAHBV

HLDAHigh to SHE, INST, RD, WR Valid

-25

TCLLH

CLKOUT Low to ALE High

-5

NOTES':
1, To guarantee recognition at next clock,

CLKOUT

HOLD
LATENCY
HOLD
TCLHAL_

TCLHAH_

HLDA
TCLBRHBREQ
THAHAX--BUS

THAHBV

BHE,
INST
Ro,WR

TCLLH
ALE.f\

----

{

4-206

\
\

' I

8XC196KB EXPRESS

EXTERNAL CLOCK DRIVE
Symbol
, 1fTXLXL

TXLXL

Parameter

Min

Max

Units

80C196KB12/83C196KB12

3.5

12.0

MHz

87C196KB10

3.5

10.0

MHz

80C 196KB12/83C196KB12

286

87C196KB10

100

286

Oscillator Frequency

TXLXX

High Time

TXLXX

Low Time

TXLXH

Rise Time

TXHXL

Fall Time

EXTERNAL CLOCK DRIVE WAVEFORMS

270634-18

An external oscillator may encounter as much as a 100 pf load at XTAL 1 when it starts-up. This is due to interaction
between the amplifier and its feedback capacitance. Once the external signal meets the V' I and V' h specifications,
the capacitance will not exceed 20pf.
'
I
I
A.C. TESTING INPUT, OUTPUT WAVEFORM

2,4=X
,

0.45

' 2 . 0 > TEST POINTS
. 0.8

2.0

FLOAT WAVEFORM

0.8 .

270634-19
A.C, Testing inputs are driven at 24V for a Logic "1" and 0.45V
for a Logic "0" Timing measurements are made at 2,OV for a
Logic "1" and 0,8V for a Logic "0",

270634-20
For Timing Purposes a Port Pin is no Longer Floating when a
100 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded VOHIVOL Level occurs
IOL/IOH = ± 15 mA.

EXPLANATION OF AC SYMBOLS

Eachsymbol is two pairs of letters prefixed by"T" fortime. The characters in a pair indicate a signal and its condition,
respectively. Symbols represent the time between the two signal/condition points.
Conditions:

Signals:

H
L
V
X

A - Address
B - BHE
BR - BREQ
C - CLKOUT
D - DATA IN

High
Low
Valid
No Longer Valid
Floating

G
H
HA
L
Q

4-207

Buswidth
HOLD
HLDA
ALElADV
DATA OUT

R
W
X
Y

RD
WRIWRHIWRL
XTAL1
READY

8XC196KB EXPRESS

A.C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol

Parameter

Min

Max

Units

TXLXL
TXLXH

Serial Port Clock Period (BRR

TXLXL
TXLXH

Serial Port Clock Period (BRR

Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)

TOVXH
TXHOX
TXHOV
TDVXH
TXHDX
TXHOZ

Output Data Setup to Clock Rising Edge

2 Tose -50

Output Data Hold after Clock Rising Edge

2 Tose -50

;?;

8002H)

Serial Port Clock Falling Edge
to Rising Edge (BRR ;?; 8002H)

8001 H)

{Hose
4 Tose ±50

4 Tose

2 Tose ±50

Input Data Hold after Cloqk Rising Edge

ns
2 Tose +50

Next Output Data Valid after Clock Rising Edge
Input Data Setup to Clock Rising Edge

Tose

+50

ns
1 Tose

Last Clock Rising to Output Float

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REG,ISTER MODE

270634-21

4-208

ifltel

8XC196KB EXPRESS

A TO D CHARACTERISTICS
There are two modes of AID operation: with or without clock prescaler. The speed of the AID converter
can be adjusted by setting a clock prescaler on or
off. At high frequencies more time is ne.:;ded for the
comparator to settle. The maximum frequency with
the clock prescaler disabled is 6 MHz. The conversion times with the prescaler turned on or off is
shown in the table below.

stability of VREF. VREF must be close to Vee since it
supplies both the resistor ladder and the digital section of the converter.,

AID CONVERTER SPECIFICATIONS
The specifications given below assume adherence
to the Operating Conditions section of this data
sheet. Testing is performed with VREF = 5.12V.

The converter is ratiometric, so the absolute
accuracy is directly dependent on the accuracy and
Clock Prescaler On
IOC2.4 = 0

Clock Prescaler Off
IOC2.4 = 1

158 States
26.33 J.Ls @ 12 MHz

91 States
30.3 J.Ls @ 6 MHz

Parameter

Typical(1)

Minimum

Maximum

Units'

512

1024
10

Levels
Bits

±6

LSBs

Resolution
Absolute Error
Full Scale Error

0.25±0.50

Zero Offset Error

-0.25±0.50

Non-Linearity Error

LSBs
LSBs

1.5±2.5

Differential Non-Linearity

±4

LSBs

>-1

LSBs

±1

LSBs

Channel-to-Channel Matching

±0.1

Repeatability

±0.25

LSBs

Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity

0.009
0.009
0.009

LSBI'C
LSBI'C
LSBI'C

-60

Off Isolation
Feedthrough

-60

Vee Power Supply Rejection

-60

Notes

Input Resistance
D.C. Input Leakage

3.0

2,3

n
/LA

Sample Time: Prescaler On
Prescaler Off

15
8

States
States

Input Capacitance

NOTES:
'An "LSB", as used here, has a value 01 approximately 5 mY.
1. Typical values are expected lor most devices at 25°C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Belore-Make Guaranteed.
4. One state = 167 ns at 12 MHz, 333 ns at 6 MHz.

4-209

4
4

inter

8XC196KB EXPRESS

DATA SHEET REVISION HISTORY
The following differences exist between this and the -001 version of the 8XC196KB Express data sheet.
1.
2.
3.
4.

The 83C 196KB ROM device was added.
The,CDE (Clock Detect Enable) pin wa~ changed to a Vss pin.
Thermal Characteristics for all packages were added.
The figures for System Bus Timings were redrawn to include missing timings and to more accurately describe'
a wait state condition.
5. HOLD/HLDA timings were added.

----

4-210

I ":nti Wd ci :1 4'1+' 'Ii i (1)@':il)iriP)

EV80C196KB FEATURES
• Zero Walt-State 12 MHz Execution Speed
• 24K Bytes of ROMsim
• Flexible Wait-State, Buswidth, Chip-Select Controller
• Totally CMOS, Low Power Board
• Concurrent Interrogation of Memory and Registers
• Sixteen Software Breakpoints
• Two Single Step Modes
-. High-Level Language Support
• Symbolic Debug
• RS-232-C Communication Link

LOW COST CODE EVALUATION TOOL
Intel's EV80C196KB evaluation board provides a hardware environment for code
execution and software debugging at a relatively low cost. The board features the
80C196KB advanced, CHMOS*, 16-bit microcontroller, the newest member of the
industry standard MCS®-96 family. The board allows the user to take full advantage of
the power of the MCS-96. The EV80C196KB provides zero wait-state, 12 MHz execution
of a user's code. Plus, its memory (ROMsim) can be reconfigured to match the user's
planned memory system, allowing for exact analysis of code execution speeds in a
particular application.
"CHMOS

a patented Intel process

UIBM PC, XT, AT s Mathmes Corporalion

intel~-~-_·----·---- .---~--~..---.. -.--.-.-.-.--.-.

Intel CorporatlOP assume~ no responslblhty for the use of any CircUitry other than CircUItry embodte~ ll1 an lntE:! product No other CIrcUIt patent
hcenses CIre llilphed Infornldtwn con tamed herem super~ede" preVIOusly pUbh"hed :.p(,-'::lhcntlon'> on th(>$'" dl'vKes from Intel
FEBRUARY 1989

Orde~ number 270729~OOl

IS'- Intel Corp(watlon 1989

4-211

P~pular features such as a symbolic single, line assembler / disassembler, si~gle-step'
p~ogram exec(ltion, ,and sixteen software breakpoints are standard on the EV80C196KB.
Intel provides a c,omplete code development environment using assembler (ASM-96) as
Well as high-level languages such as Intel's iC-96 or PL/M-96 to accelerate development
schedules.
"

The ,evaluation board is hosted on an IBM PC** or BIOS-compatible clone, already a
standard development solution in most of today's engineering environments. The source
code for the on~board monitor (written in ASM-96) is public domain. The program-is
about 1K,and can be easily modified to be included in the user's target hardware. In this
way, the provided PC host software can be used throughout the development phase.

FULL SPEED EXECUTION
The EV80C196KB executes the user's code from on-board ROMsim' at 12 MHz with zero
wait-states. By changing crystals on the 80C196KB any slower execution speed can be
evaluated. The boards host interface timing is not affected by this crystal change.

24KBYTES OF ROMSIM
the board comes with 24K bytes of SRAM to be used as ROMsim for the user s code and
as data memory if needed. 16K bytes of this memory are configured as sixteen bits wide,
and 8K bytes are configured as eight bits wide. The user can therefore evaluate the speed
of the part executing from either buswidth.
'

FLEXIBLE MEMORY DECODING
By changing the Programable Logic Device (PLD) on the board, thememory on the board
can be made to look like the memory system planned for the user's hardware application.
The PLD controls the buswidth of the 80C196KB and the chip-select inputs on the board.
It also controls the number of wait states (zero to three) generated by the 80C196KB
during a memory cycle. These features can all be selected with 256 byte boundaries
of resolution.

TOTALLY CMOS BOARD
The EV80C196KB board is built totally with CMOS components. Its power consumption
is therefore very low, requiring 5 volts at only 300 rnA. If the on board LED's are
disabled, the current drops to only 165 rnA. The board also reqUires + / - 12 volts at
15mA.

CONCURRENT INTERROGATION OF MEMORY AND REGISTERS
The monitor for the EV80C196KB allows the user to read and modify internal registers
and external memory while the users code is ruiming in the board.

SIXTEEN SOFTWARE BREAKPOINTS
There are sixteen breakpoints available which automatically substitute a TRAP
instruction for a user's instruction at the breakpoint location. The substitution occurs
when execution is started. If the code is halted or a breakpoint is reached, the user's code
is restored in the ROMsim.

4-212

TWO STEP MODES
There are two single-step modes available. The first stepping mode locks out all
interrupts which might occur during the step. The second mode enables interrupts, and
treats subroutine calls and interrupt routines as one indivisible instruction.

HIGH LEVEL LANGUAGE SUPPORT
The host software for the EV80C196KB board is able to load absolute object code
generated by ASM-96, iC-96, PL/M-96 or RL-96 all of which are available from Intel.

SYMBOLIC DEBUG
The host has a Single Line Assembler, and a Disassmbler, which recognize symbolics
generated by Intel software tools.

RS-232-C COMMUNICATION LINK
The EV80C196KB communicates with the host using an Intel 82510 UART provided on
board. This frees the on-chip UART of the 80C196KB for the user's application.

PERSONAL COMPUTER REQUIREMENTS
The EV80Cl96KB Evaluation Board is hosted on an IBM PC, XT, AT" or BIOS
compatible done. The PC must meet the following minimum requirements:
•
•
•
•
•
•

512K Bytes of Memory
One 360K Byte floppy Disk Drive
PC DOS" 3.1 or Later
A Serial Port (COM1 or COM2) at 9600 Baud
ASM-96, iC-96 or PL/M-96
A text editor such as AEDIT

RS·232
BUFFERS

ClFSELECT
BUSWDIli
8OCI96KB
CPU

READY

LOGIC

T.d
P2

ANALOG INPUT
ANALOG
DIGITAL
DIGITAL 110

110

R.d

ADDRESS

PortO

DATA

Port 1,2

8to32K
x16

8to32K
.16

8to32K
.8

RAMEPROM

CONTROL

HSO,HSI

Block Diagram of the 80C196KB Board

4-213

...

82510
UART

'----

"'.'

80C196KC, User's Guide
and Data Sheets

October 1990

80C196KC
User's Guide

Order Number: 270704·003

5·1

CONTENTS

· 80C196KC USER'S GUIDE

PAGE

1.0 CPU OPERATION ....................
1.1 Memory Controller ................
1.2 CPU Control ......................
1.3 Internal Timing .. '..................

5-4
5-5
5-5
5-5

2.0 MEMORY SPACE .................... 5-7
2.1 Register File ...................... 5-7
2.2 Special Function Registers ........ 5-7
2.3 Internal ROM and EPROM ....... 5-11
2.4 System Bus ...................... 5-11
3.0 SOFTWARE OVERViEW ............ 5-11
3.1 Operand Types .................. 5-11
3.2 Operand Addressing ............. 5-12
3.3 Register Windowing .............. 5-15
3.4 Program Status Word ............ 5-17
3.5 Instruction Set ................... 5-18
3.6 BOC196KC Instruction Set
Additions ...................... 5-27
3.7 Software Standards and
ConveJltions ................... 5-28
, ' 3.B Software Protection Hints ........ 5-29

4.,0 PERIPHERAL OVERVIEW .......... 5-29
4.1 POise Width Modulation Output
(D/A) .......................... 5-29

4.2 Timer1 and Timer2 ............... 5-29,
4.3 High Speed Inputs (HSI) ......... 5-29
4.4 High Speed Outputs (HSO) ....... 5-30
4.5 Serial Port ....................... 5-30
4.6 AID Converter ................... 5-31
4.7110 Ports ........................ 5-31
4.B Watchdog Timer ................. 5-31

5.0 INTERRUPTS ....................... 5-32
5.1 Interrupt Control ................. 5-33
5.2 Interrupt Priorities ................ 5-34
5.3 Critical Regions .................. 5-35
5.4 Interrupt Timing .................. 5-36
5.5 Interrupt Summary ............... 5-36
6.0 Peripheral Transaction Server ..... 5-38
6.1 PTS Control ..................... 5-39
6.2 PTS Modes ...................... 5-41
5-2

CONTENTS

PAGE

14.0 MINIMUM HARDWARE

7.0 Pulse Width Modulation Output
(D/A) ............................. 5-45
7.1 Analog Output ................... 5-46

CONSIDERATIONS ............. 5-75
14.1 Power Supply ................. 5-75
14.2 Noise Protection Tips .......... 5-75

8.0 TIMERS ............................. 5-47
8.1 Timer1 ........................... 5-47
8.2 Timer2 ........................... 5-47

14.3 Oscillator and Internal
. Timings ..................... 5-76
14.4 Reset and Reset Status ....... 5-77

8.3 Sampling on External Timer
Pins ............................ 5-49

14.5 Minimum Hardware
Connections .... : ........... 5-79

8.4 Timer Interrupts .................. 5-49

15.0 SPECIAL MODES OF
9.0 High Speed Inputs ................. 5-49
9.1 HSI Modes ...................... 5-50

OPERATION .................... 5-81
15.1 Idle Mode ~ .................... 5-81
15.2 Powerdown Mode ............. 5-81

9.2 HSI Status ........ : ............... 5-51 .
9.3 HSI Interrupts .................... 5-51

15.3 ONCE and Test Modes ........ 5-82

9.4 HSI Input Sampling .............. 5-52

16.0 EXTERNAL MEMORY

9.5 Initializing the HSI ................ !;i-52

10.0 HIGH SPEED OUTPUTS ...........
10.1 HSO Interrupts and Software
Timers ......................
10.2 HSO CAM .....................
10.3 HSO Status ...................

INTERFACING ..................
16.1 Bus CYperation ............... ,.
16.2 Chip Configuration Registers ..
16.3 Bus Width .....................
16.4 HOLD/HLDA Protocol .........
16.5 AC Timing Explanations .......
16.6 Memory System Examples ....
16.7 I/O Port Reconstruction .......

5-52
5-53
5-53
5-54

10.4 Clearing the HSO and Locked
Entries ...................... 5-55

5-82
5-82
5-83
5-86
5-87

5-89
5-93
5-95

10.5 HSO Precautions .............. 5-56

17.0 USING ROM AND EPROM

10.6 HSO Output Timing ............ 5-56.

PARTS .......................... 5-95

11.0 SERIAL PORT .................... . 5-56

17.1 Programming the 87C196KC .. 5-95

11.1 Serial Port Status and
Control ..................... 5-56
11.2 Serial Port Interrupts .......... 5-58

17.2 Auto Programming Mode ...... 5-96

11.3 Serial Port Modes ............. 5-58

17.5 ROM/EPROM Memory
Protection Options ......... 5-100

17.3 Slave Programming Mode ..... 5-98
17.4 Run-Time Programming ....... 5-99

11.4 Multiproc€lc;sor
Communications ............ 5-60

12.0 AID CONVERTER ............... ,.
12.1 AID Conversion Process .......
12.2 AID Interface S~ggestions ....
12.3 The AID Transfer Function ....
12.4 AID Glossary of Terms ........

17.6 UPROMs .................... 5-101

5-61

18.0 80C196KB to 80C196KC ......... 5-102
18.1 New Features of the
BOC196KC ................. 5-102
1B.2 Converting 80C196KB Designs
to 80C196KC Designs ...... 5-102

5-64
5-65
5-66
5-70

. 13.0 I/O PORTS ........................ 5-71
13.1 Input Ports .................... 5-71
13.2 Quasi-Bidirectional Ports ...... 5-72
13.3 Output Ports .................. 5-73
13.4 Ports 3 and 4/ADO-15 ........ 5-74
5-3

80C196KC USER'S GUIDE

The 80C196KC family is a CHMOS branqh of the
MCS®-96 family of high performance, 16-bit microcontrollers. Other members of the MCS-96 family include
the 8096BH, 8098 and 80C196KB. All of the MCS-96
components share a common instruction set and architecture. However the CHMOS components have enhancements to provide higher performance and lower
power consumptions. The .80C196KC has twice the
memory of any previous MCS-96 family member with
488 bytes of RAM and 16K of ROM/EPROM, and at
16 MHz, is 33% faster thanari 80C196KB at 12 MHz
and at least twice as fast as an 8096BH at 12 MHz.
Because some instructions operate in fewer clock cycles
than an NMOS device, the 80C196KC can be as much
as 2.5-3X the performance of an NMOS device.

There are many members of the 80C196KC family; to
provide easier reading this manual will refer to the family ge~erically as the 80Ct96KC. Where information
applies only to specific components it will be clearly
indicated.

The MCS-96 family is a register-to-register architec- .
ture, so no accumulator is needed, and most operations
can be quickly performed from or to any of the 256
registers. Using the Vertical Windowing scheme, the
additional 256 bytes of RAM can also be addressed as
registers. In addition, the register operations control
the many peripherals which are available on the chips.
These peripherals include a serial port; A/D converter,
three PWM outputs, up to48 I/O lines and a HighSpeed I/O subsystem which has two 16-bit timer/counters, an 8-level input capture FIFO and an 8-entry programmable output generator.

1.0 CPU OPERATION

This document was written to be a standalone users'
guide for anyone wishing to implement a design with
the 80C196KC. Those customers who are already familiar with the 80C196KB architecture can proceed to
section 18 for a description of the additional features of
the 80C 196KC. Section 18 also contains the information needed to convert an 80C196KB design to a
80C196KC.

Typical applications for MCS-96 products are closedloop control and mid-range digital signal processing.
MCS-96 products are being used in modems, motor
controls, printers, engine controls, photocopiers, antilock brakes, AC motor control, disk drives, and medical instrumentation.
V r

The major components of the CPU on the 80C196KC
are the Register File and the Register/Arithmetic Logic Unit (RALU). Communication with the outside
world is done through either the Special Function Registers (SFRs) or the Memory Controller. The RALU
does not use an accumulator. Instead, it operates directly on the 256-byte register space made; up of the
Register File and the SFRs. Efficient I/O operations
are possible by directly controlling the I/O through the
SFRs. The main benefits of this structure are the ability
to quickly change context, absence of accumulator bottleneck, and fast throughput and I/O times.

ANGND

CONTROL
SIGNALS

PORT 3

} ~~~:
BUS

PORT 4

1+--+~~]::=+:::
L

PWM1
PWM2

HSO

270704-1

Figure 1·1. 80C196KC Block Diagram

5-4

inter

80C196KC USER'S GUIDE

The CPU on the 80CI96KC is 16 bits wide and connects to the interrupt controller and the memory controller by a 16-bit bus. In addition, there is an 8-bit bus
which transfers instruction bytes from the memory controller to the CPU. An extension of the 16-bit bus connects the CPU to the peripheral devices.

Most calculations performed by the 80Cl96KC take
place in the RALU. The RALU, shown in Figure 1-2,
contains a l7-bit ALU, the Program Status Word
(PSW), the Program Counter (PC), a loop counter, and
three. temporary registers. All of the registers are 16bits or 17 -bits (16 + sign extension) wide. Some of the
registers have the ability to perform simple operations
to off-load the ALU.

1.1 Memory Controller
The RALU accesses the memory, except for the locations in the register file and SFR space, through the
memory controller. Within the memory controller is a
bus controller, a four byte prefetch queue and a Slave
Program Counter (Slave PC). Both the internal ROM/
EPROM bus and the external memory bus are driven
by the bus controller. Memory access requests to the
bus controller can come from either the RALU or the
queue, with queue accesses having priority. Requests
from the queue are always for data at the address in tl;ie
slave PC.

A separate incrementor is used for the Program Counter (PC) as it accesses operands. However, PC changes
due to jumps, calls, returns and interrupts must be handled through the ALU. Two of the temporary registers
have their own shift logic. These registers are used for
the operations which require logical shifts, including
Normalize, Multiply, and Divide. The "Lower Word"
and "Upper Word" are used together for the 32-bit
instructions and as temporary registers for many instructions. Repetitive shifts are counted by the 6-bit
"Loop Counter".

By having program fetches from memory referenced to
the slave PC, the processor saves time as addresses seldom have to be sent to the memory controller. If the
address sequence changes because of a jump, interrupt,
call, or return, the slave PC is loaded with a new value,
the queue is flushed, and processing continues.

A third temporary register stores the second operand of
two operand instructions. This includes the multiplier
during multiplications and the divisor during divisions.
To perform subtractions, the output of this register can
be complemented before being placed into the "B" input of the ALU.

Execution speed is increased by using a queue since it
usually keeps the next instruction byte available. The
instruction execution times shown in Section 3 show
the normal execution times with no wait states added
and the 16-bit bus selected, Reloading the slave PC and
fetching the first byte of the new instruction stream
takes 4 state times. This is reflected in the jump taken/
not-taken times shown in the table.

Several constants, such as 0, I and 2 are stored in the
RALU to speed up certain calculations. (e.g. making a
2's complement number or performing an increment or
decrement instruction.) In addition, single bit masks for
bit test instructions are generated lin the constant register based on the 3-bit Bit Select register.

1.3 Internal Timing
The 80Cl96KC requires an input clock on XTALl to
function. Since XTALl and XTAL2 are the input and
output of an inverter a crystal can be used to generate
the clock. Details of the circuit and suggestions for its
use can be found in Section 14. ,

1.2 CPU Control
Internal operation of the 80C196KC is based on the
crystal or external oscillator frequency divided by 2.
Every 2 oscillator periods is referred to as one "state
time", the basic time measurement for all 80C196KC
operations. With a 16 MHz oscillator, a state time is
125 nanoseconds. Since the 80CI96KC will be run at
many frequencies, the times given throughout this
chapter will be in state times 01: "states", unless otherwise specified. A clock out (CLKOUT) signal, shown
in Figure 1-3, is provided as an indication of the internal machine state. Details on timing relationships can
be found in Section 14.

A microcode engine controls the CPU, allowing it to
perform operations with any byte, ,word or double word
in the 256 byte register space. By using the VWindowing scheme discussed in Section 3-3, the additional 256
bytes of RAM can also be used as registers. Instructions to the CPU are taken from the queue and stored
temporarily in the instruction register. The microcode
engine decodes the instructions and generates the correct sequence of events to have the RALU perform the
desired function. Figure 1-2 shows the memory controller, RALU, instruction register and the control unit.

5-5

(
Master
Pro9ram Counter
w/Incrementer

::!!
co
c
....

Memory
Bus

Upper word
register
w/shifter

ID
....

RAM

»
I""

Lower word

011
C
(')

I»

"*
CO
CD

FlIe~

m '<0...

and

,Processor

0
0

Special
Function
Registers

--r--

......
j

...

(')

enC)

s:c

_ CPU
Control
and Status
Signals

til

0'
(')

"c::

Status
Word

RAM &: SFR
Control
Registers

71:'

!2
!II

3iill

CPU BUSES

270704-2

80C196KC USER'S GUIDE

2.1 Register File

PH:ASE1~
,

Locations OOH through IFFH contain the Register
File, Special Function Registers (SFRs), and 256 bytes
of additional RAM. If an attempt to execute instructions from locations ODOH through IFFH is made, the
instructions will be fetched from external memory. This
section of exterual memory is reserved for use by Intel
development tools. This memory region, as well as the
status of the majority of the chip, is kept intact while
the chip is in the Powerdown Mode. Details\ on the
Powerdown Mode are discussed in Section IS.

PHASE2~
,

CLKOUT~
270704-3

Figure 1-3. Internal Clock Waveforms

The interual RAM from location Ol8H (24 decimal) to
OFFH is the Register File. It contains 232 bytes of
RAM which can be accessed as bytes (8 bits), words
(16 bits), or double-words (32 bits). Since each of these
locations can be used by the RALU, there are essentially 232 "accumulators". Also, the extra 256 bytes of
RAM from lOOH-IFFH can be accessed as registers
by the RALU with Vertical Register Windowing. For
more on Register Windowing, see Section 3.3.

2.0 MEMORY SPACE
The addressable memory space on the 8OCl96KC consists of 64K bytes, most of which is available to the user
for program or data memory. Locations which have
special purposes are OOOOH through OIFFH and
IFFEH through 2080H. All other locations can be
used for either program or data storage or for memory
mapped peripherals. A memory map is shown in Figure
2-1. Those locations marked "Reserved" must be filled
with OFFHs for future compatibility, except for location 2019H which must contain 20H to avoid bus contention during the CCB fetch.

Locations 18H and 19H contain the stack pointer:
These are not SFRs and may be used as standard RAM
if stack operations are not being performed. Since the
stack pointer is in this area, the RALU can easily operate on it. The stack pointer must be initialized by the
user program and can point anywhere in the 64K memory space. Stack operations cause it to build down, so
the stack pointer should be initialized to 2 bytes above
the highest stack location. The stack must be word
aligned.

OFFFFH
EXTERNAL MEMORY OR I/O
6000H
INTERNAL ROM/EPROM OR
EXTERNAL MEMORY
20BOH
RESERVED
205EH
PTSVECTORS

2.2 Spec;ial Function Registers

2040H
UPPER INTERRUPT VECTORS

Locations OOH through 17H are the I/O control registers or SFRs. All of the peripheral .devices on the
80CI96KC (except Ports 3 and 4) are controlled
through the SFRs. As shown in Figure 2-2, three horizontal windows (HWindows) are provided on the
80CI96KC to increase SFR space while remaining upward compatible. with earlier MCS-96 products.
Switching between Horizontal Windows is discussed in
Section 3.3.

2030H
ROM/EPROM SECURITY KEY
2020H
RESERVED
20l9H
CHIP CONFIGURATION BYTE
201BH
RESERVED'
20l4H
LOWER INTERRUPT VECTORS
2000H

HWindow 0 is a superset of the SFR space on the
8096BH and identical to the 80C196KB. As depicted in
Figure 2-2, it has 24 registers, some of which have different functions when read than when written.

PORT 3 AND PORT 4
lFFEH
EXTERNAL MEMORY
200H
,

ADDITIONAL RAM

HWindow I contains the additional SFRs needed to
support the added functionality of the 80C196KC.
These SFRs support the Peripheral Transaction Server
(PTS), the two new PWMs, Timer2, and the new functions of the A/D converter. These registers are not
needed to remain compatible with the 80C196KB. All
SFRs are read/writable in this window.

100H
REGISTER FILE AND
EXTERNAL PROGRAM MEMORY

Figure 2-1. 80C196KC Memory Map

5-7

inter

80C 196KC, USER'S GUIDE

In register HWindow 15, the operation of the SFRs is
changed, so that those which were read-only in HWindow, 0 space are write-only and vice versa. The only
major exception is Timer2 is read/write in HWindow 0,
and T2 Capture is read/write in HWindow 15. Timer2
was read-only on the 8096BH.

labeled should be treated as reserved registers and bits.
Note that the default state of internal registers is 0,
while that for external memory is 1. This is because
SFR functions are typically disa,bled with a zero, while
external memory is typically erased to allis.
Caution must be taken when using the SFRs as sources
of operations or as base or index registers for indirect or
indexed operations. It is possible to get undesired results, since external events can change SFRs and some
SFRs clear when read. The potential for an SFR to
change value must be taken into account when operating on these registers. This is particularly important
when high level languages are used as they may not
make allowances for SFR-type registers. SFRs can be
operated on as bytes or words unless otherwise specified.

Figure 2-3 contains brief descriptions of the SFR registers. Detailed descriptions are contained in the seCtion
which discusses the peripheral controlled by the register. Figure 2-4 contains a description of the alternate
function in HWindow 15.
Within the SFR space are several registers and bit locations labeled "RESERVED". A reserved bit location
must always be written with 0 to maintain compatibility with future parts. Registers and bits which are not

19H

SP'(HI)

19H

SP(HI)

19H

SP(HI)

19H

SP(HI)

18H

SP(LO)

18H

SP(LO)

18H

SP(lO)

18H

SP(LO)

17H

IOS2

17H

PWMO

17H

PWM1_CONTROL

17H

16H

IOS1

16H

IOC1

16H

PWtvJ2_CONTROL

16H

15H

10SO

15H

lOCO

15H

RESERVED

15H

14H

WSR

14H

WSR

14H

WSR

14H

WSR

13H

INT_MASK1

13H

INT_MASK1

13H

INT_MASK1

13H

INT_MASK1

12H

INT_PEND1

12H

INT_PEND1

12H

INT_PEND1

12H

INT_PENDl

11H

SP_STAT

11H

SP_CON

11H

RESERVED

11H

CONTROL

10H

PORT2

10H

PORT2

10H

RESERVED·

10H

RESERVED

OFH

PORT1

OFH

PORT1

OFH

RESERVED

OFH

RESERVED

OEH

PORTO

OEH

BAUD RATE

OEH

RESERVED

oEi-!

RESERVED

ODH

TIMER2(HI)

ODH

TIMER2 (HI)

ODH

RESERVED

ODH

T2CAPTURE (HI)

OCH

TlMER2 (LO)

OCH

TIMER2(LO)

OCH

IOC3'

OCH

T2CAPTURE (LO)

OSH

TIMER1 (HI)

OSH

IOC2

OBH

RESERVED

OSH

OAH

TIMER1 (LO)

OAH

WATCHDOG

OAH

RESERVED

OAH

09H

INT_PEND

09H

INT_PEND

09H

INT_PEND

09H

INT_PEND

08H

INT_MASK

08H

INT_MASK

08H

INT_MASK

08H

INT_MASK

07H

SSUF(RX)

07H

SBUF(TX)

07H

PTSSRV(HI)

07H

06H

HSI_STATUS

06H

HSO_COMMAND

P6H

PTSSRV (LO)

06H

05H

HSI_TIME (HI)

05H

HSO_TIME, (HI)

05H

PTSSEL(HI)

05H

04H

HSI_TIME (LO)

04H

HSO_TIME (LO)

04H

PTSSEL(LO)

04H

03H

AD_RESULT (HI)

03H

HSI_MODE

03H

AD_TIME

03H

02H

AD_RESULT (LO)

02H

AD_COMMAND

02H

RESERVED

02H

01H

ZERO_REG (HI)

01H

ZERO_REG (HI)

01H

ZERO_REG (HI)

01H

ZERO_REG (HI)

OOH

ZERO~REG

OOH

ZERO_REG (LO)

OOH

ZERO_REG (LO)

OOH

ZERO_REG (LO)

(LO)

HWINDOWO
when Read

HWINDOWO
when Written

HWINDOW1
Read/Write

NOTE:
'This was previously called T2CONTROL or T2CNTC.

Figure 2-2. 'Multiple Register Windows

5-8

HWINDOW15

80C196KC USER'S GUIDE

Description

Zero Register· Always reads as a zero, useful ,for a base when indexing and as a
constant for calculations and compares.

AD_RESULT

AID Result Hillow • low and high order results of the A/D converter

AD_COMMAND

A/D Command Register· Controls the A/D

HSI_MODE

HSI Mode Register· Sets the mode of the High Speed Input unit.

HSI_TIME

HSI Time Hillo • Contains the time at which the High Speed Input unit was triggered.

HSO_TIME

HSO Time Hillo· Sets the time or count for the High Speed Output to execute the
command in the Command Register.

HSO_COMMAND

HSO Command Register· Determines what will happen at the time loaded into the
HSO Time registers.

HSI_STATUS

HSI Status Registers· Indicates which HSI pins were detected at the time in the HSI
Time registers and the 'current state of the pins.

SBUF(TX)

Transmit buffer for the serial port, holds contents to be outputted.

SBUF(RX)

Receive buffer for the serial port, holds the byte just received by the serial port.

INT_MASK

Interrupt Mask Register· Enables or disables the individual interrupts.

INT_PEND

Interrupt Pending Register· Indicates that an interrupt signal has occurred on one of
the sources and has not been serviced. (also INT_PENDING)

WATCHDOG

Watchdog Timer Register· W'ritten periodically to hold off automatic reset every 64K
state times.

TIMER1

Timer 1 Hilla· Timer1 high and low bytes.

TIMER2

Timer 2 Hilla· Timer2 high and low bytes.

10PORTO

Port 0 Register· levels on pins of Port O.

BAUD_RATE

IOPORT1

Port 1 Register· Used to read or write to Port 1,

IOPORT2

Port 2 Register. Used to read or write to Port 2.

SP_STAT

Serlal Port Status· Indicates the status of the serial port.

SP_CON

Serial Port Control· Used to set the mode of the serial port.

10SO

I/O Status Register 0 . Contains information on the HSO status.

IOS1

I/O Status Register 1 • Contains information on the status of the timers and of the
HSI.

lOCO

I/O Control Register O· Controls alternate functions of HSI pins, Timer 2 reset
sources and Timer 2 clock sources.

IOC1

I/O Control Register 1 • Controls alternate functions of Port 2 pins, timer interrupts
and HSI interrupts.

PWM_CONTROl

Pulse Width Modulation Control Register· Sets the duration of the PWM pulse.

Figure 2·3. Special Function Register Description

5·9

inter

80C196KC USER'S GUIDE

Description
.Interrupt Pending register for the 8 new interrupt vectors (also INT_PENDING1)

INT_MASK1

Interrupt Mask register for the 8 new interrupt vectors

IOC2

1/0 Control Register 2

IOS2

1/0 Status Register 2 - Contains information on HSO events

WSR

Window Select Register - Selects register window

AD_TIME

Determin~s

IOC3

New 80C196KC features (T2 internal clocking, PWMs) (PreviOusly T2CONTROL or
T2CNTC)

AID Conversion Time

PTSSEL

Individually enables PTS channels

PTSSRV

End-of-PTS Interrupt Pending Flags
Figure 2-3. Special Function Register Description (Continued)

AD_COMMAND (02H)
AD_RESULT (02H, 03H)
HSI_MODE (03H)
HSI_TIME (04H, 05H)
HSO_TIME (04H, 05H)
HSI_STATUS (06H)
HSO_COMMAND (06H)
SBUF(RX) (07H)
SBUF(TX) (07H)
WATCHDOG (OAH)
TIMER! (OAH, OBH)
TIMER2 (OCH, ODH)

IOC2 (OBH)
BAUD_RATE (OEH)
PORTO (OEH)
SP_STAT (llH)
SP_CON(IIH)
IOSO(!5H) .

lOCO (I5H)
lOS! (16H)

lOCI (16H)
IOS2 (I7H)
PWM_CONTROL (17H)

Read the last written command
Write a value into the result register
Read the value in HSI_MODE
Write to FIFO Holding register
Read the last value placed in the holding register
Write to status bits but not to HSI inputs bits. (Inputs bits are I, 3, 5, 7)
Read the last value placed in the holding register
Write a value into the receive buffer
Read the last value written to the transmit buffer
Read the value in the upper byte of the WDT
Write a value to Timer!
Read/Write the Timer2 capture register.
(Timer2 read/write is done with WSR = 0)
Last written value is read~ble, except bit 7 (Note I)
No function, cannot be read
No function, no output drivers on the pins
Set the status bits, TI and RI can be set, but it will not cause an interrupt
Read the, current control byte
Writing to this register controls the HSO pins. Bits 6 and 7 are inactive for
writes.
Last written value is niadable, except bit I (Note 1)
Writing to this register will set the status bits, but not cause interrupts. Bits
6 and 7 are not functional.
Last written value is readable
Writing to this register will set the status bits, but not cause interrupts.
Read the duty cycle value written to PWM_CONTROL

NOTE:
1. IOC2.7 (CAM CLEAR) and IOCO.1 (T2RST) are not latched and will read as a 1 (precharged bus).

Figure 2-4. Alternate SFR Function in HWindow 15

5-10

inter

80C196KC USER'S GUIDE

MCS®-96 UTILITIES USER'S GUIDE
Order Number 122049 (Intel Systems)
Order Number 122356 (DOS Systems)

2.3 Internal ROM and EPROM
For a ROM and EPRQM part, the internal memory
locations 20S0H through 5FFFH are user specified, as
are the interrupt vectors, and PTS (Peripheral Transaction Server) vectors, Chip Configuration Register and
Security Key in locations 2000H through 207FH.

PL/M-96 USER'S GUIDE
Order Number 122134 (Intel Systems)
'Order Number 122361 (DOS Systems)
C-96 USER'S GUIDE
Order Number 167632 (DOS Systems)

Instruction and data fetches from the internal ROM or
EPROM occur only if EA is tied high, and the address
is' between 2000H and 5FFFH. At all other times data
is accessed from either the internal RAM space or external memory and instructions are fetched from external memory. The EA pin is latched on RESET rising.
Information on programming EPROMs can be found
in Section 17 of this manual.

Throughout this chapter short sections of code are used
to illustrate the operation of the device. For these sections it is assumed that the following set of temporary
registers has been declared:
AX, BX, CX, and DX are 16-bit registers.
AL is the low byte of AX, AH is the high byte.
BL is the low byte of BX
CL is the low byte of CX
DL is the low byte of DX

A security feature can lock the chip against reading
and/or writing the internal memory. In order to maintain security, code can not be executed out of the last
four locations of internal ROM/EPROM if the lock is
enabled. Details on this feature are in Section 17.

These are the same as the mimes for the general data
registers used in the 8086. In the 80CI96KC these are
not dedicated registers but merely the symbolic names
assigned by the programmer to an eight byte region
within the on-board register file.

2.4 System Bus
There are several modes cif system bus operation on the
SOC 196KC. The standard bus mode uses a l6-bit multiplexed address/data bus. Other bus modes include an
S:bit mode and a mode in which the bus size can dynamically be switched between 8-bits and l6-bits.

'3.1 Operand Types
The MCS-96 architecture supports a variety of data
types ,likely to be useful in a control application. To
avoid confusion, the name of an operand type is capitalized. A "BYTE" is an unsigned eight bit variable; a
"byte" is an eight bit unit of data of any type.

Hold/Hold Acknowledge (HOLD/HLDA) and Ready
signals are available to create a variety of memory systems. The READY line extends the width of the RD
(read) and WR (write) pulses to allow a~ess of slow
memories. Multiple processor systems. with shared
memory can be designed using HOLD/HLDA. Details
on the System Bus are in Sections 15 and 16.

BYTES

BYTES are unsigned 8-bit variables which can take on
the values between 0 and 255. Arithmetic arid relational
operators can be applied to BYTE operands but the
result must be interpreted in modulo 256 arithmetic.
Logical operations on BYTES are applied bitwise. Bits
within BYTES are labeled from 0 to 7, with 0 being the
least significant bit.

3.0 SOFTWARE OVERVIEW
This section provides information on writing programs
to execute in the SOCI96KC. Additional information
can be found in the following documents:
MCS®-96 MACRO ASSEMBLER USER'S GUIDE
Order Number 122048 (Intel Systems)
Order Number 122351 (DOS Systems)

5-11

80C~96KC ,USER'S,GUIDE

WORDS,
WORDS are unsigned 16-bit variables which can take
on the values between 0 and 65535. Arithmetic and
relational operators can be,applie 255 (OFFH)

flag can be used along with the C flag to control
rounding after a right shift. Consider multiplying
two eight bit quantities and then scaling the result down to 12 bits:
MULUB
SHR

SIGNED
WORD
DIVIDE

If the C flag is set after the shift, it indicates that the
bits shifted off the end of the operand were greater-than
or equal-to one half the least significant bit (LSB) of the
result. If the C flag is c1el\r after the shift, it indicates
that the bits shifted off the end of tjIe operand were less
than half the LSB of the result. Without the ST flag,
the rounding decision must be made on the basis of the
C flag alone. (Normally the result would be rounded up
if the C flag is set.) The ST flag allows a finer resolution
in the rounding decision:

< -127(SlH)

< -32767(SOOlH)

> 32767 (7FFFH)
The oVerflow Trap flag is set when the V flag is
set, but it is only cleared by the CLRVT, JVT
and JNVT instructions. The operation of the VT
flag allows for the testing for a possible overflow
condition at the end of a sequence of related
arithmetic operations. This is normally more efficient than testing the V flag after each instruc"
tion.
C: ' The Carry flag is set to indicate the state of the
arithmetic carry from the most significant bit of
the ALU for an arithmetic operation, or the state
of the last bit shifted out of an operand for a
shift. Arithmetic Borrow after a subtract operation ·is the complement of the C flag (i.e. if the
operation generated a borrow then C~O.)
PSE: The Peripheral Transaction Server Enable bit.
Globally enables the PTS when set. Manipulated
by the EPTS and DPTS instructions.
I:
The global Interrupt disable bit disables all interrupts except NMI, TRAP, and unimplemented
opcode when cleared.
ST: The ST (STicky bit) flag is set to indicate that
during a right shift a I has been shifted first into
the C flag and then been shifted out. The ST flag
is undefined after a multiply operation. The ST

Value of the Bits Shifted Off
Value = 0

o < Value < % LSB

Value =

Value> Y2 LSB

or
> 127 (7FH)
or'

;AX:=CL*DL
;Shift right 4

places

UNSIGNED
WORD DIVIDE> 65535 (OFFFFH)
SIGNED
BYTE
DIVIDE

AX,CL,DL
AX,#4

% LSB

Figure 3-6. Rounding Alternatives

'Imprecise rounding can be a major source of error in a
numerical cl'llculation; use of the ST flag improves the
options available to the programmer.

VT:

INTERRUPT FLAGS

The lower eight bits of the PSW individually mask the
lowest 8 sources of interrupt to the 80C196KC. These
mask bits can be accessed as an eight bit byte (INT_
MASK-address 8) in the register file. A separate register (INT_MASKI-address I3H) contains the controlbits for the higher 8 interrupts. A logical '1' in
these bit positions enables the servicing of the corresponding interrupt. Bit 9 in the PSW is the global interrupt disable. If this bit is cleared then interrupts will be
locked out. Further information on the interrupt structure of the 80C196KC can be found in Section 5.

3.5 Instruction Set
The MCS-96 instruction set contains a full set of arithmetic and logical operations for the 8-bit data types
BYTE and SHORT INTEGER and for the 16-bit data
types WORD and INTEGER. The DOUBLE-WORD
and LONG data types (32 bits) are supported for shifts,
products of 16 by 16 multiplies, dividends of 32-by-16
divides, and for 32-bit compares. The remaining oper-

5-1S

inter

80C196KC USER'S GUIDE

unsigned operands were involved or a JGT Gump if
greater-than) if signed operands were involved.

ations on 32-bit variables can be implemented by combinations of 16-bit operations. As an example the sequence:

ADD
ADDC

Tables 3-7 and 3-8 summarize the operation of each of
the instructions.

AX,CX
BX,DX

The execution times for the instruction set is given in
Figure 3-8. These times ar.e given for a 16-bit bus with
no waitstates. On-chip EPROM/ROM space is a 16bit, zero waits tate bus. When executing from an 8-bit
external memory system or adding waitstates, the CPU
becomes bus limited and must sometimes wait for the
prefetch queue. The performance penalty for an 8-bit
external bus is difficult to measure, but has shown to be
between 10 and 30 percent based on the instruction
mix. The best way to measure code performance is to
actually benchmark the code and time it using an emulator or with TIMER!.'

performs a 32-bit addition, and the sequence

SUB
SUBC

AX,CX
BX,DX

performs a 32-bit subtraction. Operations on REAL
(i.e. floating point) variables are not supported directly
by the hardware but are supported by the floating point
library for the 80C196KC (FPAL-96) which implements a single precision subset of Draft 10 of the IEEE
Staildard for Floating Point Arithmetic. The performance of this software is significantly improved by the
80C196KC NORML instruction which normalizes a
32-bit variable and by the existence of the ST flag in the
PSW.

The indirect and indexed instruction timings are given
for two memory spaces; SFR/Internal RAM space (0IFFH), and a memory controller reference (200HOFFFFH). Any instruction that uses an operand that is
referenced thru the memory controller (ex. Add
rl,5000H[0l) takes 2-3 states longer than if the operand was in the SFR/Internal RAM space. Any data
access to on-chip ROM/EPROM is considered to be a
memory controller reference.

In addition to the operations on the various data types,
the 80C196KC supports conversions between these
types. LDBZE (load byte zero extended) converts a
BYTE to a WORD and LDBSE (load byte sign extended) converts a SHORT-INTEGER into an INTEGER.
WORDS can be converted to DOUBLE-WORDS by
simply clearing the upper WORD of the DOUBLEWORD (CLR) and INTEGERS can be converted to
LONGS with the EXT (sign extend) instruction.

Flag Settings. The modification to the flag setting is
shown for each instruction. A checkmark (,....) means
that the flag is set or cleared as appropriate. A hyphen
means that the flag is not modified. A one or zero (1) or
(0) indicates that the flag will be in that state after the
instruction. An up arrow (t) indicates that the instruction may set the flag if it is appropriate but will
not clear the flag. A down arrow ( J.- ) indicates that the
flag can be cleared but not set by the instruction. A
question mark (1) indicates that the flag will be left in
an indeterminant state after the operation.

5-19

80C196KC USER'S GUIDE

Table 3-7A.lnstruction Summary

,
Mnemonic

Flags

Operation (Note 1)

Operands

Notes

/;'

t
t
t
t
t
t
t

ADD/ADDB

2 .

D~D+A

/;'

ADD/ADDB

D~B+A

/;'

ADDC/ADDCB

D~D+A+C

J.-

/;'

SUB/SUBB

D~D-A

/;'

SUB/SUBB

D~B-A

/;'

SUBC/SUBCB

D~D-A+C-1

J.-

/;'

CMP/CMPB

D-A

/;'

MUL/MULU

D,D + 2

Dx A

MUL/MULU

D,D + 2

B x A

3
3

MULB/MULUB

D,D + 1 ~ D x A

MULB/MULUB

D,D + 1 ~ B x A

/;'

t
t
t
t

DIVU

(D,D + 2) / A,D + 2

remainder

DIVUB

(D,D + 1) / A,D + 1 ~ remainder

/;'

DIV

(D,D + 2) / A,D + 2

/;'

DIVB

(D,D + 1) / A,D + 1 ~ remainder

/;'

AND/ANDB

D~DANDA

/;'

AND/ANDB

D~BANDA

/;'

OR/ORB

DORA

/;'

XOR/XORB.

D (eexl. or) A

/;'

O. -

LD/LDB

D~A

ST/STB

A~D

XCH/XCHB

D~A,A~D

LDBSE

3,4

LDBZE

D~A;D

3,4'

PUSH

POP

PUSHF

SP ~ SP - 2; (SP) ~ PSW;
PSW ~ OOOOH; I ~ 0

POPF

PSW

/;'

SJMP

PC + 11-bit offset

LJMP

PC + 16-bit offset

BR[indireet]

PC~

(A)

TIJMP

[A] +2' ([B] AND C)

SCALL

SP~SP

LCALL

SP
PC

remainder

+ 1 ~O

SP - 2; (SP)

(SP); SP + 2

(SP)

A; D + 1 ~ SIGN(A)

~
~

(SP); SP

- 2;
PC; PC

SP + 2; I ~ /;'

PC + 11-bit offset

SP - 2; (SP) ~ PC;
PC + 16-bit offset

5-20

80C196KC USER'S GUIDE

Table 3-7B. Instruction Summary
Mnemonic

Operands

Flags

Operation (Note 1)
Z

RET

Notes

N C V VT ST

PC +- (SP); SP +- SP + 2

5
5

J (conditional)

PC +- PC + 8·bit offset (if taken)

Jump if C

-L

JNC

jump ifC = 0

jump if Z

JNE

Jump if Z = 0

, 5

JGE

Jump if N = 0

JLT

Jump if N

JGT

Jump if N = 0 and Z

JLE

Jump if N

Jump if C = 1 and Z

JNH

Jump if C = 0 or Z = 1

Jump if V = 0

JNV

1 ,

Jump if V = 1

1 or Z = 1

JVT

Jump if VT = 1; Clear VT

JNVT

Jump if VT

0; Clear VT

5
5

JST

JumpifST

..:.

JNST

Jump ifST

JBS

Jump if Specified Bit = 1

5,6

JBC

Jump if Specified Bit = 0

5,6

OJNZI
OJNZW

o +-

OEC/OECB

0+-0-1

NEG/NEGB

0+-0-0

INCIINCB

0+-0+1

II'

t
t
t

EXT

+- Sign (0)

EXTB

0; 0 + 1 +- Sign (0)

NOT/NOTB

o +o +o +-

Logical Not (0)

CLR/CLRB

0+-0

SHL/SHLB/SHLL

C +- msb····· Isb +- 0

SHRISHRB/SHRL

SHRA/SHRAB/SHRAL

msb

SETC

C+-1

CLRC

C+-O

- -

If 0

0 - 1;

"* 0 then PC +- PC + 8·bit offset

0; 0

msb·····lsb
~

msb····· Isb

5·21

C
~

inter

8OC196KC USER'S GUIDE

Table 3·7C. Instruction Summary
Mnemonic

Operands

Flags

Operation (Note 1)

Notes

ST
-

CLRVT

VT -

RST

PC -

2080H

Disable All Interupts (I -

Enable All Interupts (I - ' 1)

DPTS

Disable all PTS Cycles (PSE = 0)

EPTS

Enable all PTS Cycles (PSE = 1)

NOP

PC-PC+1

SKIP

PC-PC+2

NORML

Left shift till msb = 1; D -

TRAP

SP ~ SP - 2;
(SP) PC; PC -

".. ".

shift count

(2010H)

PU~HA

POPA

IMASK1/WSR (SP); SP PSW (SP); SP SP+2

IDLPD

IDLE MODE IF KEY= 1;
POWERDOWN MODE IF KEY = 2;
CHIP RESET OTHERWISE

CMPL

D-A

BMOV,
BMOVi

[PTA_HI] + [PTA_LOW] + ;
UNTILCOUNT=O

SP SP-2; (SP) PSW;
PSW OOOOH; SP SP-2;
(SP) IMASK1/WSR; IMASK1 -

OOH

SP+2

NOTES:
1. If the mnemonic ends in "B" a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment rules for the required operand type. D and B are locations in the Register File; A can ,be
located anywhere in memory.
2. D,D + 2 are consecutive WORDS in memory; D is DOUBLE-WORD aligned.
3. D,D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to word.
5. Offset is a 2's complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necesi;lary registers with code starting at
2080H.
9. The ~ssembler will not accept this mnemonic.

5-22

inter

80C196KC USER'S GUIDE

Table 3-7D.lnstructlon Length/Opcode

MNEMONIC

INDIRECT

INDEXED

DIRECT

IMMED

NORMAL*(1)

A-INC*(1)

4/44
4/48

5/45
5/49
4/S5
4/69
4/A5
4/A9
4/89
4/55
4/59

4/46
4/4A
3/66
3/6A
3/A6
3/AA
S/AB
4/56
4/5A

4/46
4/4A
3/66
3/SA
3/AS
3/AA
3/AB
4/5S
4/5A

3178

3175
3179

3176
317A

3/B4
3/B8

3/B5
3/B9

3/98

3/99

3/BS
3/BA
3/9A

MUL (3-op)
MULU (3-op)
MUL(2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB

5/(2)
4/4C
4/(2)
3/6C
4/(2)
3/8C
5/(2)
4/5C
4/(2)
3/7C
4/(2)
3/9C

6/(2)
5/4D
5/(2)

5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E

5/(2)
4/4E
4/(2)
3/6E
4/(2)
3/8E
5/(2)
4/5E
4/(2)
317E
4/(2)
3/9E

AND (3-op)
AND (2-op)
OR (2-op)
XOR
ANDB (3-op)
ANDB (2-op)
ORB (2-op)
XORB

4/40
3/60
3/80
3/84
4/50
3/70
3/90
3/94

PUSH
POP

2/C8
2/CC

ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB (2-op)
ADDC
SUBC
CMP
ADDB (3-op)
SUBB (3-op)
ADDB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB

3/64
3/68
3/A4
3/A8
3/88

4/54
4/58
3/74

4/6D
5/(2)
4/8D
5/(2)

4/5D
4/(2)
317D
4/(2)
3/9D
5/41

4/S1
4/81
4/85
4/51

3171
3/91
3/95
3/C9

4/(2)
317E
4/(2)
3/9E

SHORT*(1)

LONG*(1)

5/47
5/4B
4/67
4/6B·
4/A7
4/AB
4/8B
5/57
5/5B
4/77
417B
4/B7
4/BB
4/9B

6/47
6/4B
5/67
5/6B
5/A7
5/AB
5/8B
6/57
6/5B
5/77
5/7B
5/B7
5/BB
5/9B

6/(2)
5/4F
5/(2)
4/6F
5/(2)

6/4F
6/(2)
5/6F
6/(2)

4/8F

5/8F

6/(2)

7/(2)
6/5F
6/(2)'
517F
6/(2)
5/9F

5/5F
5/(2)
417F
5/(2)

4/9F

7/(2)

4/42
3/62
3/82
3/86
4/52
3/72
3/92
3/96

4/42
3/62
3/82
3/86
4/52

5/43
4/63
4/83
4/87
5/53

3172

4173

3/92
3/96

4/93
4/97

6/43
5/63
5/83
5/87
5/53
4/73
5/93
5/97

2/CA
2/CE

3/CB
3/CF

4/CB
4/GF

5-23

80C196KC USER'S GUIDE

Table 3-7E. Instruction Length (in bytes)/Opcode
MNEMONIC

DIRECT

INDIRECT

IMMED

NORMAL

SHORT

LONG

3/AO

4/A1

3/A2

4/A3

5/A3

LOB

3/BO

3/B1

3/B2

4/B3

5/B3

3/CO

.INDEXED
A-INC

STB

3/C4

XCI;i

3/04

XCHB

3/14

3/C2

4/C3

5/C3

3/C6

4/C7

5/C?

4/0B

5/0B

4/1B

5/1B

LOBSE

3/BC

3/BO

3/BE

4/BF

5/BF

LBSZE

3/AC

3/AO

3/AE

4/AF

5/AF

Mnemonic

Length/Opcode

Mnemonic

Length/Opcode

PUSHF
POPF
PUSHA
POPA

1/F2
1/F3
1/F4
1/F5

OJNZ
OJNZW
NORML
SHRL
SHLL
SHRAL
SHR
SHRB
SHL
SHLB
SHRA
SHRAB

3/EO
3/E1
3/0F
3/0C
3/00
3/0E
3/08
3/18
3/09
3/19
3/0A
3/1A

CLRC
SETC
01
EI
OPTS
EPTS
CLRVT
NOP
RST
SKIP
10LPO
BMOV
BMOVi

1/F8
1/F9
1/FA

TRAP
LCALL
SCALL
RET
L.)MP
SJMP
BR[)
TIJMP
JNST
JST
JNH
JH
JGT
JLE
JNC
JC
JNVT
JVT
JNV
JV
JGE
JLT
JNE
JE
JBC
JBS

1/F7

3/EF
2/28-2F(3)
1/FO
3/E7
2/20-27(3)
2/E3
4/E2
1/00
1/08
1/01
1/09
1/02
1/0A
1/B3
1/08
1/04
1/0C
1/05

1/00

1/FB
1/EC
1/EO
1/FC

1/FO
1/FF
2/00
1/F6
3/C1
3/CO

1/06
1/0E
1/07

1/0F
3/30-37
3/38-3F

NOTES:
3. The 3 least si.gnificant bits of. the opcode are concatenated with the 8 bits to form an 11-bit, 2's complement offset.

5-24

80C1'96KC USER'S GUIDE

Table 3-SA. Instruction Execution State Times (1)
MNEMONIC

INDIRECT

INDEXED

DIRECT

IMMED

NORMAL'

A-INC'

SHORT'

LONG"

ADD (3-op)
SUB (3-op)
ADD (2-op)
SUB, (2-op)
ADDC
SUBC
CMP
ADDB (3-op)
SUBB (3-op)
AD DB (2-op)
SUBB (2-op)
ADDCB
SUBCB
CMPB

5
5
4
4
4
4
4
5
5
4
4
4
4
4

6
6
5
5
5
5
5
5
5
4
4
4
4
4

7/10
7/10
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8

8/11
8/11
7/9
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9

7/10
7/10
6/8
6/8
6/8
6/8
6/8
7/10
7/10
6/8
6/8
6/8
6/8
6/8

8/11
8/11
7/9
7/9
7/9
7/9
7/9
8/11
8/11
7/9
7/9
7/9
7/9
7/9

MUL (3-op)
MULU (3-op)
MUL (2-op)
MULU (2-op)
DIV
DIVU
MULB (3-op)
MULUB (3-op)
MULB (2-op)
MULUB (2-op)
DIVB
DIVUB

16
14
16
14
26
24
12
10
12
10
18
16

17
15
17
15
27
25
12
10
12
10
18
16

18/21
16/19
18/21
16/19
28/31
26/29
14/17
12/15
14/17
12/15
20/23
18/21

19/22
17/19
19/22
29/32
27/30
13/15
12/16
15/18
13/15
21/24
19/22

19/22
17/20
19/22
17/20
29/32
27/30
15/18
12/16
15/18
12/16
21/24
19/22

20/23
18/21
20/23
18/21
30/33
28/31
16/19
14/17
16/19
14/17
22/25
20/23

AND (3-op)
AND (2-op)
OR (2-op)
XOR
ANDB (3-op)
ANDB (2-op)
ORB (2-op)
XORB

5
4
4
4
5
4
4
4

6
5
5
5
5
4
4
4

7/10
6/8
6/8
6/8
7/10
6/8
6/8
6/8

8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9

7/10
6/8
6/8
6/8
7/10
6/8
6/8
6/8

8/11
7/9
7/9
7/9
8/11
7/9
7/9
7/9

LD, LOB
STJ STB
XCH,XCHB
LDBSE
LDBZE

4,4
4,4
5,5
4
4

5,4

5/8
5/8

6/8
6/9

6/9
8/13
6/9
6/9

7/10
7/10
9/14
7/10
7/10

17119

4
4

5/8
5/8

6/8
6/8

6/9

BMOV

6 + 8 per word + 3 for each memory controller reference

BMOVi

7+8 per word
+ 14 for each interrupt + 3 for each memory controller reference

10/13
10/13
11/14
9/12
10/,12
11/13
11/13
12/14
12/15
12/15
13/16
11/14
14/16 "
14/16
15/17
13/15
"Times for operands addressed as SFRs and internal RAM (0-1 FFH)/memory controller references (200-0FFFFH)).
PUSH (int stack)
POP (int stack)
PUSH (ext stack)
POP (ext stack)

6
8
8
11

7
9
-

NOTE:
1. Execution times for memory controller references may be one to two states higher depending on the number of bytes in
the prefetch queue.
2. INT stack is 0-1FFH and EXT stack is 200-0FFFFH.

5-25

inter

80C 196KC USER'S GUIDE

Table 3·8B. Instruction Execution State Times,
MNEMONIC
PUSHF (int stack)
POPF (int stack)
PUSHA tint stack)
POPA (int stack)
TRAP (int stack)
LCALL (int stack)
SCALL (int stack)
RET (int stack)

MNEMONIC

12
12

PUSHF (ext stack)
POPF (ext stack)
PUSHA (ext stack)
POPA (ext stack)

8
10
18
18

16
11
11
11

TRAP (ext stack)
LCALL (ext stack)
SCALL (ext stack)
RET (ext stack)

18.
13
13
14

DEC/DECB
EXT/EXTB
INC/INCS

3
4
3

6
7

CMPL
CLR/CLRB
NOTINOTB
NEG/NEGB

3
3
3

LJMP
SJMP
BR [indirect]
TIJMP
JNST,JST
JNH, JH
JGT, JLE
JNC, JC
JNVT, JVT
JNV,JV
JGE, JLT
JNE, JE
JBC, JBS

15 + 3 ·for each memory controller reference
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump tak~n
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
4/8 jump not taken/jump taken
5/9 jump not taken/jump taken

OJNZ
OJNZW

5/9 jump not taken/jump taken
6/10 jump not taken/jump taken

NORML
SHRL
SHLL
SHRAL
SHR/SHRB
SHL/SHLB
SHRAISHRAB

CLRC
, SETC
01
EI
OPTS
EPTS
CLRVT
NOP
RST
SKIP
10LPO

7
7
7

5-26

80C196KC USER'S GUIDE

Table 3-8C. Instruction Execution State Times
PTSCYCLES
18 (+ 3 for each memory controller reference)
13 (+ 7 for each transfer, 1 minimum
+ 3 for each memory controller reference)
21
25
12 (+ 10 for each transfer, 1 minimum)
16 (+ 10 for each transfer, 1 minimum)
11 (+ 10 for each transfer, 1 minimum)
15 (+ ,11 for each transfer, 1 minimum)

Single Transfer
Block Transfer

AID Mode (SFRs/internal RAM)
(MEMORY CONT) ,
HSI MODE (SFRs/internal RAM)
(MEMORY CONT)
HSO MODE (SFRs/internal RAM)
(MEMORY CONT)

BMOVI

Block move using 2 auto-incrementing
pointers and a counter which can be interrupted. BMOV with interrupt.
BMOVI updates the counter when interrupted
XCH/XCHB Exchanges the contents of two registers
or a register and a memory location
Jumps to an address selected out of a
TIJMP
table of addresses. The table may have a
maxim,um 128 entries

3.6 80C196KC Instruction Set
Additions
For users already familiar with the 80C196KB, there
are six instructions added to the standard MCS-96 instruction set to form the 80C196KC instruction set. All
of the former instructions perform the same function.
The new instructions and their descriptions are listed
below:
OPTS Disables the Peripheral Transaction Server by
clearing the PSE flag in the PSW
EPTS
Enables the Peripheral Transaction Server by
setting the PSE flag in the PSW

TIJMP

See Figure 3-9 for TIJMP address calculation.

TBASE, [INDEX], #INDEX_MASK

TBASE = WORD REGISTER CONTAINING 16-BIT ADDRESS
OF BEGINNING OF JUMP TABLE
INDEX = WORD REGISTER CONTAINING 16-BIT ADDRESS
OF 8-BIT INDEX INTO JUMP TABLE
INDEX_MASK

= 8-BIT

IMMEDIATE DATA TO MASK (AND)
WITH INDEX
ADDRESS CALCULATION

[INDEX] AND INDEX_MASK = OFFSET .
(2 • OFFSET) + TBASE

Jump Table
TBASE -

DEST X

DESTO

DEST1

N+2

DEST2

N+4

DESTX

Figure 3-9. TIJMP Address Calculation

5-27

+ 2' X

80C,196KC USER'S GUIDE

3.7 Software Standards and
Conventions
For a software project' of any size it is a good idea to
modularize the program and to establish standards
which control the communication between these ,modules. The nature of these standards will vary with the
needs of the final application. A common component of
all of these standards, however, must be the mechanism
for passing parameters to procedures and returning re, suits from procedures. In the absence of some overriding consideration which prevents their use, it is suggested that the user conform to the conventions adopted by
the PLM-96 programming language for procedure linkage. It is a very usable standard for both the assembly
language and PLM-96 environment and it offers compatibility between these environments. Another advantage is that it allows the user access to the same floating
point arithmetics library that PLM-96 uses to operate
on REAL variables.

REGISTER UTILIZATION,
The MCS-96 architecture provides a 256 byte register
file. Some of these registers are used to control registermapped I/Q devices and for other special functions
such as the ZERO register and the stack pointer. The
remaining bytes in the register file, some 230 of them,
plus the extra 256 bytes of RAM, are available for allocation by the programmer. If these registers are to be
used effectively, some overall strategy for their allocation must be adopted. PLM-96 adopts the simple and
effective strategy of allocating the eight bytes between
addresses I CH and 23H as temporary storage. The
starting address of this region is called PLMREG. The
remaining area in the register file is treated as a segment of memory which is allocated as required.

ADDRESSING 32-BIT OPERANDS

, SUBROUTINE LINKAGE
Parameters are passed to subrouti~eS in the stack. Parameters are pushed into' the stack in the order that
they are encountered in the scanning of the source text.
Eight-bit parameters (BYTES or SHORT-INTEGERS) are pushed into the stack with the high order
byte undefined. Thirty-two bit par:;Uneters (LONG-INTEGERS, DOUBLE-WORDS, and REALS) are
pushed onto the stack as two l6-bit values; the most'
significant half of the parameter is pus,hed into the
stack first.
As an example, consider the following PLM-96 procedure:
example_procedure: PROCEDURE
(param l,param2,param3);
DECLARE paraml BYTE,
param2 DWORD,
param3 WORD;
When this procedure is entered at run time the stack
will contain the parameters in the following order:
, 7171?? : param 1
high word of' param2
low word of param2
param3
return address

StacLpointer

Flgl,lre 3-9. Stack Image
If a procedure returns a value to the calling code (as
opposed to modify~ng more global variables) then the
result is returned in the variable PLMREG. PLMREG
is viewed as either an 8-, 16- or 32-bit variable depending on the type of the procedure.

These operands are f!lrmed from two adjacent 16-bit
words in memory. The least significant word of the
double word is always in lower address, even when the
data, is in the'stack (which means that the most significant w\lrd must be pushed into the stllck first). A double word is addressed by the address of its least significant byte. Note that the hardware supports some operations on double words.
'

The standard calling convention adopted by PLM-96
has several key features:
a) Procedures can always assume, that the eight bytes of
register file memory starting at PLMREG can be
used as temporaries within the body of the procedure.
b) Code which calls a procedure must assume that the
eight bytes of register file memory starting at
PLMREG are modified by the procedure.
c) The Program Status,Word (PSW-see Section 3.4) is
not saved and restored by procedures so the calling
code must assume that the condition flags (Z, N, V,
VT, C, apd ST) are modified by the pr9cedure.
d) Function results from procedures ate always returned in the variable PLMREG.

5-28

inter

80C196KC USER'S GUIDE

PLM-96 allows the definition of INTERRUPT procedures which are executed when a predefined interrupt
occurs. These procedures do not c.onform to the rules of
a normal procedure. Parameters cannot be passed to
these procedures and they cannot return results. Since
they can execute essentially at any time (hence the term
interrupt), these procedures must save the PSW and
PLMREG when they are entered and restore these values before they exit.

3.8 Software Protection Hints
Several features to assist in recovery from hardware
and software errors are available on the SOCI96KC.
Protection is also provided against executing unimplemented opcodes by the unimplemented opcode interrupt. In addition, the hardware reset instruction (RST)
can cause a reset if the program counter goes out of
bounds. This instruction has an opcode of OFFH, so if
the processor reads in bus lines which have been pulled
high it will reset itself.

4.1 Pulse Width Modulation Output
(D/A)
Digital to analog conversion can be done with the Pulse
Width Modulation output. The SOCl96KC has 3 PWM
outputs, like the 1 PWM on the SOC196KB.
The output waveform is a variable duty cycle pulse
which is selectable to repeat every 256 state times or
512 state times. Changes in the duty cycle are made by
writing to the PWM registers. Several types of motors
require a PWM waveform for most efficient operation.
Additionally, if this waveform is filtered it will produce
a DC level which can be changed in 256 steps by varying the duty cycle. Details on the PWM are in Section
7.0.

4.2 Timer1 and Timer2
Two 16-bit timers are available for use on the
SOC 196KC. The first is designated "Timerl", the second "Timer2". The timers are the time bases for the
HSI and HSQ units and can be considered an integral
part of the HSI/Q. Details on the Timers are in Section
S4
.

The Watchdog Timer (WOT) further helps protect
against software and hardware errors. When using the
WOT to protect software it is desirable to reset it from
only one place in code, lessening the chance of an undesired WOT reset. The section of code that resets the
WOT should monitor the other code sections for proper operation. This can be done by checking variables to
make sure they are within reasonable values. Simply
using a software timer to reset the WOT every 10 milliseconds will provide protection only for catastrophic
failures.

Timer1

Timer1 is a free-running timer which is incremented
every eight state times. It can be read and written, but
care must bb taken when writing to it if the HSIQ Subsystem is being used. The precautions necessary when
writing to Timerl are described in Section S. Timerl
can cause an interrupt when it overflows.

4.0 PERIPHERAL OVERVIEW
Timer2

There ~re five major peripherals on the SOCI96KC: the
Pulse-Width-Modulated outputs (PWM), Timerl and
Timer2, High Speed I/O. Unit, Serial Port, and AID
Converter. A minor peripheral is the watchdog timer.
With the exception of the high speed I/O unit (HSIQ),
each of the peripherals is a single unit that can be discussed without further separation.

Timer2 counts transitions, both positive and negative,
on its input which can be either the T2CLK pin or the
HSI.1 pin. Also, the SOC196KC has added the capability to clock Timer2 internally every 1 or S state times.
Timer2 can be read and written and can be reset by
hardware, software or the HSQ unit. It can be configured to count up or down based on Port 2.6 and it's
value can be captured into the T2CAPTURE register
on a rising edge on Port 2.7.

Four individual sections make up the HSIQ and work
together to form a very flexible timer/counter based
I/O system. Included. in the HSIQ are a 16-bit timer
(Timerl), a l6-bit up/down counter (Timer2), a programmable high speed input unit (HSI), and a programmable high speed output unit (HSQ). With very
little CPU overhead ,.the HSIO can measure pulse
widths, generate waveforms, and create periodic interrupts. Oepending on the application, the HSI/O can
perform the work of up to IS timer/counters and capture/compare' registers.

When clocking Timer2 externally, the maximum input
transition speed is Once every S state times or once per
state time in the Fast Increment mode. CLKQUT cannot be used to clock Timer2 directly. It must first be
divided by 2 since Timer2 counts both positive and negative transitions.

4.3 High Speed Inputs (HSI)
A brief description of the peripheral functions and interractions is included in this section. All of the details
on control bits and precautions are in the individual
sections for each peripheral starting with Section 7.

The High Speed ·Input (HSI) unit can capture the value
of Timer1 when an event takes place on one of four
input pins (HSI.0-HSI.3). Four types of events can
5-29

80C196KC USER'S.GUIDE

trigger a capture: nsing edges only, falling edges onty,
rising or falling edges, or every eighth rising ,edge. Each
HSI pin can be independently programmed to look for
any of these conditions. A block diagram of this unit is
shown in Figure 4-1.
'
When events occur, the Timer! value gets stored in the
FIFO along with 4 status bits whioh indicate the input
line(s) that caused the event. The neltt event ready to Pe
unloadec;l from the FIFO is placed in the HSI Holding
Register, so a total of 8 pieces of data can be stored in
the FIFO. Data is taken off the FIFO by reading the
HSIJTA11US register, followed by reading, the
HSI_TIME register. When\ the time register is read
the next FIFO location is loaded into the holding register.
Independent of the HSI operation, the state of the HSI
pins is indicated by 4 bits of the HSI_STATUS register so the pins can also be inputs. Also independent of
the HSI operation is the HSI.O pin interrupt, which can
be used as an extra external interrupt. Details on the
HSI are in Section 9.0

4.4 High Speed Outputs (HSO)
The High Speed Output (HSO) unit can generate events
at specified values of Timet! or Timer2 with minimal
CPU overhead. A block diagram of the HSO unit is
shown in Figure 4-2. Up to 8 pending events can be
stored in the CAM (Content Addressable Memory) of
the HSO unit at one time. Commands are placed into

~he HSO unit by first writing to HSO_COMMAND
'with the event to occur, and then to HSO_TIME with
the, timer match'value.

Fourteen different types of events can be triggered by
the HSO: 8 external and 7 internal. There are two interrupt vectors associated with the HSO, one for external
events, and one for internal events. External events consist of switching one or more of the 6 HSO lines
(HSO.0-HSO.5). HSO.4 and HSO.5 share pins with
HSI.2 and HSI.3 and it is possible to have these pin~
enabled for both functions. Internal events include setting up 4 Software Timers, resetting Timer2, and starting an AID conversion. The software timers are flags
that can be set by the HSO and optionally cause interrupts.
'

4.5 Serial Port
The serial port on the 80C!96KC is functionally compatible with the serial port on the MCS-51 and MCS-96
families of microcontrollers. One synchronous and
three asynchronous modes are available. The asynchronous modes are full duplex. Double buffering is provided for the receiver so a second byte can be received
before the first byte has been read. The transmitter is
also double buffered, allowing bytes to be written 2 at a
time.
The Serial Port STATus (SPJ TAT) register contains
bits to indicate receive overrun, parity, and framing errors, and transmit and receive interrupts.

HSI Trigger Options
XTAL1/16

~ HITOLO

-r-

HSI.O

HSl.l

LOTOHI

--1""'HiOR "lO'"l..I

CHANGE
DETECTOR

HSI.2

TRIGGERED
INPUT(S)

HSI.3

.JlJ1JlJU1J1JUl
EVERY EIGHTH POSITIVE
TRANSITION

270704-6

270704-7

Figure 4~1 •.HSI Block Diagram
5-30

(

inter

80C196KC USER'S GUIDE

16-BIT

16-BIT
, T2CLK
T21NT

Him.! SPEED OUTPUT CONTROLS
6 PINS
4 SOFTWARE TIMERS
2 INTERRUPTS
INITIATE AID CONVERSION
RESET TIMER2

270704-8

Figure 4-2. HSO Block Diagram

tional and some have multiple functions. In addition to
these ports, the HSI/O lines can be used as standard
I/O lines.

BAUD RATES

Baud rates are generated in an independent IS-bit
counter based on either the T2CLK pin or XTALl pin.
Common baud rates can be easily generated with standard crystal frequencies. A maximum baud rate of I
Mbaud is available in the asynchronous modes with
16 MHz on XTAL1. The synchronous mode has a
maximum rate of 4.0 Mbaud with a 16 MHz clock.

Port 0 is an input port which is also the analog input
for the A/D converter. Port I is a quasi-bidirectional
port. The three MSBs of Port I are multiplexed with
the HOLD/HLDA functions. Also, the 2 extra PWM
outputs are multiplexed on Port 1.4 and 1.3. Port 2
contains three types of pins: quasi-bidirectional, input
and output. Its input and output lines are shared with
other functions. Ports 3 and 4 are open-drain bidirectional ports which share their pins with the address/
data bus.

4.6 AID Converter
The A/D Converter consists of a sample-and-hold, an
8-channel multiplexer, and a 8- or IO-bit successive approximation analog-to-digital converter.

Analog signals can be sampled by any of the 8 analog
input pins (ACHO through ACH7) which are shared
with Port O. An A/D conversion is performed on one
input at a time using successive approximation with a
result equal to the ratio of the input voltage divided by
the analog supply voltage. If the ratio is 1.00, then the
result will be all ones. A conversion can be started by
writing to the AD_COMMAND register or by an
HSO command. For details on the A/D Converter, see
Section 12.

4.8 Watchdog Timer
The Watchdog Timer (WDT) provides a means to recover gracefully from a software upset. When the
watchdog is enabled it will initiate a hardware reset
unless the software clears it every 64K state times.
Hardware resets on the 80CI96KC pull the RESET pin
low, providing a system reset to other components on
the board.

4.7 1/0 Ports
There are five 8-bit I/O ports on the 80C196KC. Some
are input only, some are output only, some are bidirec-

5-31

inter

80C196KC USER'S GUIDE

5.0 INTERRUPTS

NMI

Twenty-eight (28) sources of interrupts are available on
the 80C196KC. These sources are gathered into 15 vectors plus special vectors for NMI, the TRAP instruction, and Unimplemented Opcodes. Figure 5-1 shows
the routing of the interrupt sources into their vectors as
well as the control bits which enable some of the sources. The operation of the Peripheral Transaction Server
(PTS) is intimately a part of interrupt operation and is
discussed in Section 6.

NMI, the external Non-Maskable Interrupt, is the
highest priority interrupt. It vectors indirectly through
location 203EH. For design symmetry, a mask bit exists in INT_MASK1 for the NMI. However, the bit
does not function and will not stop an NMI from occurring. For future compatibility, the NMI mask bit
must be set to zero.

Special Interrupts

Three special interrupts are available on the
80C196KC: NMI, TRAP and Unimplemented opcode.
Although available for customer use, these interrupts
may be used in Intel development tools or evaluation
boards.

NMI on the 8096BH vectored directly to location
OOOOH, so for the 80C196KC to be compatible with
8096BH software, which uses the NMI, location
203EH must be loaded with OOOOH. The NMI interrupt
vector and interrupt vector location is used by some
Intel development tools. The NMI interrupt is rising
edge triggered.

SOURCES

VECTORS

NON - MASKABLE INTERRUPT - - - - - - - - - NMI
TIMER 2 CAPTURE - - - - - - - - - TIMER 2 CAPTURE
4TH FIFO ENTRY - - - - - - - - - HSI FIFO 4
UNIMPLEMENTED OPCODE - - - - - - - -___, UNIMPLEMENTED OPCODE
TRAP INSTRUCTION

SOFTWARE TRAP

,EXTINT (PORT 2.2) - - - - " ".....- - - - EXTINT 1
PORTO.7

---_e~IOC1.l
'

EXTINT

TI FLAG -~-...<:::;O\~----- TI FLAG
" " ' _ - - - - - - SERIAL PORT
RI FLAG _ _ _..c::;.;..._ _ _ _ RI FLAG
SWTO - 3
RESET TIMER 2 --------1
START AID - - - - -.....

SOF'TWA'RE TIMER

HSI.O PIN - - - - - - - - - HSI.O PIN
HSO LINES 0 - 5 - - - - - - - - - HIGH SPEED OUTPUT
HSI FIFO FULL
HSI HOLDING REGISTER LOADED

~IOC1.7

---_e -

HSI FIFO FULL
HSI DATA AVAILABLE

AID CONVERSION COMPLETE - - - - - - . - . - - AID CONVERSION COMPLETE
TIMER 2 OVERFLOW - - - _ - -....-.,,- TIMER 2 OVERFLOW
L..:.-j-IOC 1.3
TIMER 1 OVERFLOW
TIMER OVERFLOW
IOC1.2

--.:a-r--. . . ---

Figure 5-1. 80C196KC Interrupt Sources

5-32

270704-9

80C196KC USER'S GUIDE

5.1 Interrupt Control

TRAP

Interrupt Pending Register

When hardware detects one of the sixteen interrupts, it
sets the corresponding bit in one of two pending interrupt registers (INT_PEND @ 09H and INT_
PENDI @ 12H). When the interrupt 'vector is taken,
the pending bit is cleared. The~ registers, the formats
of which are shown in Figure 5-3, can be 'read or modified as byte registers. They can be read to determine
which of the interrupts are pending at any given time or
modified to either clear pending interrupts or generate
interrupts under software control. Any software which
modifies the INT_PEND registers should ensure that
the entire operation is inseparable: The easiest way to
do this is to use the logical instructions in the two or
three operand format, for example:

Unimplemented Opcode.

Opcodes which are not implemented on the 80C196KC
will cause an indirect vector through location 2012H if
executed;
The programmer must initialize the interrupt vector table with the starting addresses of the appropriate interrupt service routines. It is suggested that any unused
interrupts be vectored to an error handling routine.

ANDB
ORB

INTERRUPT SOURCES

INT_PEND,#llllllOlB
; Clears the AID Interrupt
INT_PEND.#OOOOOOIOB
; Sets the AID Interrupt

Caution must be used when writing to the pending register to clear interrupts. If the interrupt has already
been acknowledged when the bit is cleared, a 5 state
time "partial" interrupt cycle will occur. This is because the' 80CI96KC will have to fetch the next instruction of the normal instruction flow, instead of proceeding with the interrupt processing. The effect on the
program will be essentially that of an extra ,two NOPs.
This can be prevented by clearing the bits using a 2
operand immediate logical,as the 80C196KC holds off
acknowledging interrupts during these "read/modify/
write" instructions.

80C196KC

28 Sources
. 18 Vectors

Interrupt Mask Register

Individual interrupts can be enabled or disabled by setting or' clearing bits in the interrupt mask registers
(INT_MASK @ 08H and INT~ASKI @ 13H).
The format of these registers is the same as the Interrupt Pending Register shown in Figure 5-3. ,

VECTOR STATUS
270704-10

Figure 5-2. 80C196KC Interrupt Structure
Block Diagram

The INT_MASK and INT_MASKI registers can be
read or written as byte registers. A one in anY bit position will enable the corresponding interrupt source and
a zero will disable the source. The hardware will save
any interrupts that occur by setting bits in the pending
register, even if the interrupt mask bit is cleared.' The
INT_MASK register is the lower eight bits of the
PSW so the PUSHF and POPF instructions save and
restore the INT_MASK register as well as the PSW.
Both the INT_MASK and INT_MASKI registers
can be saved and restored with the PUSHA and POPA
Instructions.

Five registers control the operation of the interrupt system: INT....;PEND, INT_PENDl, INT_MASK and
INT_MASKI and the PSW which contains a global
disable bit. A block diagram of the system is shown in
Figure 5-2. The transition detector looks for 0 to I transitions on any of the sources. External sources have a
maximum transition speed of one edge every state time.

5-33

80C196KC USER'S GUIDE

,12H
13H

IPEND1:,
IMASK1:

NMI

FIFO
FULL

EXT
INT1

T2
0VF

T2
CAP

HSI4

,
09H
OSH

IPEND:
IMASK:

EXT
INT

SER SOFT HSI.O
PORT TIMER PIN

HSO
PIN

HSI
AID TIMER
DATA DONE OVF

Figure 5·3. Interrupt Mask
, and Pending Registers
Global Disable
Source

Number

The processing of all interrupts except the NMI, TRAP
and unimplemented opcode interrupts can be disabled
by clearing the I bit in the PSW. Setting the I bit will
enable interrupts that have mask register bits set. The I
bit is controlled by the EI (Enable Interrupts) and DI
(Disable Interrupts) instructions. Note that the I bit
only controls the actuat servicing of interrupts. Interrupts that occur when l'is cleared will be held in the
pending register and serviced on a prioritized basis
when I is set.

Vector
Location

Priority
15

INT15

NMI

203EH

INT14

HSI FIFO Full

203CH

INT13

EXTINT1

203AH

' 13

INT12

TIMEA2 Overflow

2038H

INT11

TIMEA2 Capture

2036H

INT10

4th Entry into' HSI FIFO

2034H

INT09

2032H

5.2 Interrupt Priorities

INT08, '

2030H

The priority encoder looks at all of the interrupts which
are both ,pending and enabled, and selects the one with
the highest priority. The priorities are shown in Figure
5-4 (15 is highest, 0 is lowest). The interrupt generator
then forces a call to the location in the indicated vector
'location. This location would be the starting location of
the Interrupt ServiCe Routine (ISR).

SPECIAL

Unimplemented Opcode

2012H

N/A

SPECIAL

Trap

2010H

N/A

INT07

EXTINT

200EH

INT06

Serial Port

200CH

INT05

Software Timer

200AH

This priority selection controls the order in which
pending interrupts are passed to the software via in~er
rupt calls. The software can then implement its own
priority structure by, controlling the mask registers
(INT_MASK and INT~ASKI). To see how this is
done, consider the case of a serial I/O service routine
which must run at a priority level which is lower than
the HSI data available interrupt ~ut higher than any
other source. The "preamble" and exit code for this
interrupt service routine would 1000k life this:

HSI.OPin

2008H

INT03

High Speed Outputs

2006H

INT02

HSI Data Available

2004H

INT01

AID Conversion Complete

2002H

INTOO

Timer Overflow

2000H

Figure 5·4. 80C196KC Interrupt Priorities

Note that location 200CH in the interrupt vector table
would have to be loaded with the lab!ll seriaLJo~sr
and the interrupt be enabled for this routine to execute.

serial_io_isr: ,
PUSHA
;: Save 'the PSW, INT_MASK
; INT_MASK1, and WSR
INT_MASK,#OOOOOlOOB
'
LDB
, ; Enable interrupts again
EI

POPA

INT04

There is an interesting chailil of instruction side~effects
which makes this (or any other) 80CI96KC interrupt,
service routine execute properly:
a) After the Irtterrupt controller decides to process ari
interrupt, it executes a "CALL", using the location
'froJ;Il the corresponding interrupt vector table entry
as the destination. The return address is pushed onto
the stack. Another interrupt cannot be serviced \lntil
after the first instruction following the interrupt call
is executed.

Service the interrupt

Restore'

RET
5-34

80C196KC USER'S GU!DE

b) The PUSHA instruction, which is guaranteed to execute, saves the PSW, INT-MASK, INT-MASKl,
and the WSR on the stack as two words, and clears
them. An interrupt cannot be serviced immediately
following a PUSHA instruction. (If INT-MASK 1
and the WSR register are not used, or 8096BH code
is being executed, PUSHF, which saves only the
PSW and INT~ASK, can be used in place of
PUSHA).
c) LO INT_MASK, which is guaranteed to execute,
enables those interrupts that are allowed to interrupt
this ISR. This allows the software to establish its
own priorities independent of the hardware.
d) The EI instruction reenables the processing of interrupts with the new priorities.
e) At the end of the ISR, the POPA instruction restores
the PSW, INT_MASK, INT_MASKl, and WSR
to their original state when the interrupt occurred.
Interrupts cannot occur immediately following a
POPA instruction so the RET instruction is guaranteed to execute. This prevents the stack from overflowing if interrupts are occurring at high frequency.
(IfINT_MASKl and the WSR are not being used,
or 8096BH code is being executed, POPF, which restores only the PSW and INT_MASK, can be used
in place of POPA.
Notice that the "preamble" and exit code for the interrupt service routine does not include any code for saving or restoring registers. This is because it has been
assumed that the interrupt service routine has been allocated its own private set of registers from the onboard register file. The availability of some 230 bytes of
register storage makes tl}is quite practical. By using the
VWindowing Scheme, an additional 256 bytes become
available (See Section 3.4).

sider clearing a bit in the interrupt pending register as
part of a non-interrupt routine:

LDB
ANDB
STB

A~,INT_PEND

AL,#b1t_mask
AL,INT_PEND

This code works if no other routines are operating concurrently, but can cause occasional and serious problems if used in a concurrent environment. (All programs which make use of interrupts must be considered
a concurrent environment.) For example, assume that
the INT_PEND register contains OOOOllllB and bit 3
(HSO event interrupt pending) is to be reset. The ~ode
does work for this data pattern but what happens if an
HSI interrupt occurs somewhere between the LDB and
, the STB instructiQns? Before the LOB instruction
INT_PEND contains OOOOllllB and after the LOB
instruction so does AL. If the HSI interrupt service
routine executes at this point then INTJENO will
change to 0000101 lB. The ANOB changes AL to
OOOOOlllB and the STB changes INT_PEND to
000001 1lB. It should be 0000001 lB. This code sequence has managed to generate a false HSI interrupt.
These problems can be avoided by assuring mutual exclusion which means that if more than one routine can
change a variable, then the programmer must ensure
exclusive access to the variable during the entire operation on the variable.
In many cases the instruction set ofthe 80C196KC allows the variable to be modified with a single instruction. The code in the above example can be implemented with a single instruction.

ANDB
Instructions an;: indivisible so mutual exclusion is ensured in this case. Changes to the INT_PENO or
INT_PENDI register must be made ,as a single instruction, since bits can be changed in this register even
if interrupts are disabled. Depending on system configurations, several other SFRs might also need to be
changed in .a single instruction for the same reason.

5.3 Critical Regions
Interrupt service routines sometimes must share data
with other routines. Whenever the programmer is coding those sections of a program which access these
shared pieces of data, great care must be taken to ensure that the integrity of the data is maintained. Con-

When variables must be modified without interruption,
and a single instruction can not be used, the programmer must create what is termed a critical region. One
way to do this is to simply disable interrupts with a 01
instruction, perform the modification, and then re-en-

5-35

80C'196KC USER'S GUIDE

able interrupts with an EI instruction. The problem
with this 'approach is that it leaves the interrupts enabled even if they were not enabled at the start. A better solution is to enter the critical region with a PUSHF
-instruction which saves the PSW and also cleani the
interrupt enable flag. The region can then be terminated with a POPF instruction which returns the ,interrupt
enable to the state it was in before the code sequence. It
should, be ,noted that some system cOnfigurations might
require more protection to form a critical region. An
example is a system in which more than one processor
has access to a common resource such as memory or
external 110 devices.

5.4 Interrupt Timing
The 80C196KC can be interrupted from four different
external sources; NMI, P2.2, HSI.O and PO.7. All external interrupts are sampled during PHI or CLKOUT
low and are latched internally. Holding levels on exter, nal interrupts for at least one state time wiII ensure
, recognition of the interrupts.
The externaI.interrupts on the 8OC196KC, although
sampled during PHI, are edge triggered interrupts as
opposed to level triggered.
Interrupts are not always acknowledged immediately.
If the interrupt signal does not occur prior to 4 statetimes before the end of an instruction, the interrupt
may not be acknowledged until after the next instruction has been executed. This is because an instruction is
fetched and prepared for execution a few state times
before it is actually executed.

When an interrupt is acknowledged the interrupt pending bit is cleared, and a call is forced to the location
indicated by the specified interrupt vector. This call occurs after the completion of the instruction in process,
except as noted above. The procedure of getting the
vector and forcing the call requires 16 state times. If the
stack is in external RAM an additional 2 state times are
required. This assumes a 0 wait-state bus.
The maximum number of state times required from the
time an interrupt is generated (not acknowledged) until
the 80C196KC begins executing code at the desired location is the time of the longest instruction, NORML
(Normalize - 39 state times), plus the 4 state times
prior to the end of the previous instruction, plus the
response time (16(internal stack) or 18(external stack)
state times). Therefore, the maximum response time is
61 (39 + 4 + 18) state times. This does not include the
6 state times required for PUSHF if jt is used as the
first instruction in the interrupt routine or additional
latency caused by having the' interrupt masked or disabled. Refer to Figure 5-5, Interrupt Response Time, to
visualize an example of worst case scenario.
Interrupt latency time can be reduced by careful selection of instructions in areas of code where interrupts
are expected. Using: 'EI' followed immediately by a
long instruction (e.g. MUL, NORML, etc.) will increase the maximum latency by 4 state times, as an
jnterrupt cannot occur between EI and the instruction
following EI. The DI, PUSHF, POPF, PUSHA, POPA
and TRAP instructions wiII also cause the same situation. Typically these instructions would only effect latency when one interrupt routine is already in process,
as these instructions are seldom used at other times.

There are 6 instructions which always inhibit interrupts
from being acknowledged until after the next instruction has been executed. These instructions'are:
EI, DI - Enable and disable all interrupts by toggling the global disable bit (PSW.9).
PUSHF - PUSH Flags ,pushes the PSW/INT_
MASK pair then clears it, leaving both
INt_MASK and PSW.9 clear.
POPF - POP Flags pops the PSWlINT.-MASK
pair off the stack
PUSHA - PUSH All does a PUSHF, then pushes
,
the INT_MASK I/WSR pair and clears
INT.-MASKI
POPA - POP All pops the INT.-MASKI/wSR
pair and then does a POPF

5.5 Interrupt Summary
Many of the interrupt veotors on the 8096BH were
shared by multiple interrupts. The interrupts which
were s~ared on the 8096BH are: Transmit Interrupt,
Receive Interrupt, HSI FIFO Full, Timer2 Overflow
and P2.2.0n the 8OC196KC, each of these interrupts
have their own interrupt vectors. The source of the interrupt vectors 'are typically programmed through control registers. These registers can be read in HWindow
15 to determine the source of any interrupt. Interrupt
sources with two possible interrupt vectors, serial receive interrupt sharing serial port and receive interrupt
vectors for example, should be configured for only one
interrupt vector.

Interrupts can also not occur immediately after execution of:
Unimple'mented Opcodes
TRAP - The software trap instruction
SIGND - The signed prefix for multiply and divide
instructions' \
5-36

inter

80C196KC USER'S GUIDE

STATE TIMES
EXECUTION

·EXTI~T~

INTERRUPT ROUTINE

PENDING
I SET
BIT - I
RESPONSE TIME

""1.-------270704-11

Figure 5-5. Interrupt Response Time

Interrupts with separate vectors include: NMI, TRAP,
Unimplemented Opcode" Timer2 Capture, 4th Entry
into HSr FIFO, Software timer, HSI.O Pin, High Speed
Outputs, and AID' conversion Complete, The NMI,
TRAP ,and Unimplemented Opcode interrupts were
.
covered in Section 5,1.

to one generates an interrupt when the FIFO, independent of the holding register, has six entries in it.
On the 80C196KC, separate interrupt vectors are available for the HSI FIFO FULL(203CH) and HSI DATA
AVAILABLE(2004H) interrupts. The interrupts
should be programmed for separate vector locations.
Refer to Section 9 for more information on the High
Speed Inputs.

EXTINT and PO.7

The 8OCl96KC has two external interrupt vectors;
EXTINT (200EH) and EXTINTl (203AH), The
EXTINT vector has two alternate sources selectable by
IOCLl, the external interrupt pin (Port 2.2) and Port
0.7. The external interrupt pin is the only source for the
EXTINTl interrupt vector. The external interrupt pin
should not be programmed to interrupt thro\1gh both
vectors. Both external interrupt sources are rising edge
triggered.

The HSI FIFO can generate an interrupt when the HSI
has four or more entries in the FIFO. The HSI
FIFO_4 interrupt vectors through location ·2034H.
Refer to Section 9 for more information on the High
Speed Inputs.
HSI.O External Interrupt

Serial Port Interrupts

A rising edge on HSI.O pin can be used as an external
interrupt. Sampling is guaranteed if the pin is held for
at least one state time. The interrupt vectors through
location 2008H. The pin does not have to be enabled to
the FIFO to cause an interrupt.

The serial port generates one of three possible interrupts: Transmit interrupt TI(2030H), Receive Interrupt
RI(2032H) and SERIAL(200cH). Refer to section 10
for information on· the serial port interrupts. The
8096BH shared the TI and RI interrupts on the
SERIAL interrupt vector. On the 80Cl96KC, these interrupts share both the serial interrupt vector and have
their own interrupt vectors. Ideally, the transmit and
receive interrupts should \:Ie programmed as sllParate
interrupt vectors while disabling the SERIAL interrupt. For 8096BH compatibility, the interrupts can still
use the SERIAL interrupt vector.

Tlmer2 and Tlmer1 OverflOW

Timer2 and Timer! can interrupt on overflow. These
interrupts shared the same interrupt vector TIMER
OVERFLOW(2000H) on the 8096BH. The interrupts
are individually enabled by setting bits 2 and 3 in lOCI.
Which timer actually caused the interrupt' can be determined by bits 4 and 5 of 10SL On the 80Cl96KC
Timer2 ovc;rflow (OH or 8000H) has a separate interrupt vector through location 2038H.

HSI FIFO FULL and HSI DATA AVAILABLE

HSI FIFO FULL and HSI DATA AVAILABLE in·terrupts shared the HSI DATA' AVAILABLE interrupt I vector on the 8096BH. The source of the HSI
DATA AVAILABLE interrupt is controlled by the
setting of I/O Control Register 1,(IOCL7). Setting
IOCL7 to zero will generate an interrupt when a time
value is loaded into the holding register. Setting the bit

Timer2 Capture

The 8OCl96KC can interrupt in response to a Timer2
capture triggered by a rising edge on P2.7. Timer2 Capture vectors through location 2036H.

5-37

80C196KC USER'S GUIDE

sion. The interrupt vectors indirectly through location
2002H. Refer to Section 12 for more information on the
AID Converter.

High Speed Output
The High Speed Output interrupt can be generated in
response to a programmed HSO command which causes,an external event. HSO commands which set or clear
the High Speed Output pins are considered external
events. Status Register IOS2 indicates which HSO
events have occured and can be used to arbitrate which
HSO command caused the interrupt. The Hig~ Speed
Output interrupt vectors indirectly through location
2006H. For more information on High Speed Outputs,
refer to Section 10.

6.0 PERIPHERAL TRANSACTION
SERVER

Software Timers

The Peripheral Transaction Server (PTS) is a new feature of the 80C196KC. ,The PTS provides DMA-like
response to an interrupt with much less CPU overhead.
Single and block transfer modes are supported, as well
as special modes to service the AID Converter and the
HSI/O. Any of the 15 interrupt vectors can be alternatively mapped to its PTS channel.

HSO commands which create internal events can interrupt through the Software Timer interrupt vector. Internal events include triggering an AID conversion, resetting Timer2 and software timers. Status registers
IOS2 and 10SI can be used to determine which internal
HSO event has occured. Location 200AH is the interrupt vector for the Software Timer interrupt. Refer to
Section 10 for more information on software timers and
the HSO.

Figure 6-1 shows the difference between a normal Interrupt Service Routine and the same interrupt mapped
to its PTS channel. Instead of an Interrupt Service
Routine, the PTS channel generates a PTS cycle. The
software overhead of forcing the interrupt call,
PUSHA, POPA, and executing the RET instruction is
eliminated. Instead, the PTS cycle is interleaved with
the normal instruction flow much like a DMA cycle.

AID Conversion Complete
The AID Conversion Complete interrupt can generate
an interrupt in response to a completed AID converNormal Interrupt Response
NORMAL EXECUTION

INTERRUPT SERVICE ROUTINE

LD
MUL

PUSHA
; RESPONSE TO
- ; INTERRUPT
; GOES HERE

VAR, TEMP3
/
SPEED, DISTANCE

INTERRUPT OCCURS
OR

_ _ POPA

RrT

HERE, THERE

270704-77

PTS Response
NORMAL EXECUTION

PTS CYCLE

LD
MUL

VAR, TEMP3
/
SPEED, DISTANCE / "

INTERRUPT OCCURS
OR

HERE, THERE

;
;
;
;

ONE OF 5 PTS MODES
EXECUTED IN MICROCODE
PROGRAM COUNTER NEVER
CHANGES

Figure 6-1. PTS vs Interrupt Response
5·38

270704-78

inter

80C196KC USER'S GUIDE

6.1 PTS Control

PTSVector

The PTS' vector table is composed of 15 words at loca·
tions 2040H-205CH as shown in Figure 6-2. The PTS
vector table has the same format as the Interrupt vector
table and the same priority scheme (14 highest, 0 low·
est). All PTS channels have higher priority over any
interrupts except NMI. Each PTS vector points t~ a
PTS Control Block (PTSCB) which must reside in the
internal RAM space (lAH-IFFH) at an address even·
ly divisible by 8. Figure 6-3 gives the format of the
PTSCB for the 5 PTS modes. Unused bytes in the
PTSCBs can be used as normal RAM locations. The
PTSCB must be initialized by the user before the PTS
channel is enabled. The function of each register is dis·
cussed in the next few sections.
The PTS is globally enabled by the PSE bit (Peripheral
transaction Server Enable) in the PSW. PSE is set by
the EPTS (Enable PTS) instruction and cleared by the
DPTS (Disable PTS) instruction. When executing a
PUSHA instruction the PSE bit is pushed onto the
stack with the PSW and then cleared. The PTSSEL
(PIS SELect) word register in HWindow 1 at O4H in·
dividually enables each PTS channel over the normal
interrupt response. PTSSEL has the same format as the
INT_PEND and INT~ASK registers and is shown
in Figure 6-4. When a bit in PTSSEl- is set, the associ·
ated interrupt request becomes a frrs request. Each
PTS request will set. the corresponding bit in the Inter·
rupt Pending Register. Ifthe corresponding bit in the
Interrupt Mask Register is also set, and the PTS is
globally enabled by the PSE bit, a PTS cycle will be
initiated. See Figure 6-5.

PTSVEC-+

Location

HSI FIFO Full

205CH

EXTINT1

205AH

TIMER2 Overflow

2058H

TIMER2 Capture

2056H

4th HSI FIFO Entry

2054H

2052H

2050H

EXTINT

204EH

Serial Port

204CH

Software Timer

204AH

HSI.O Pin

2048H

High Speed Outputs

2046H

HSI Data Available

2044H

AID Conversion. Complete

2042H

Timer OVerflow

2040H

Figure 6-2. PTS Vector Table
As in the normal interrupt response, the current in·
struction is completed before the PTS cycle actually
starts. The internal priority resolver handles the PTS
requests based on their priority. Next,'the PTS Vector
is read from the PTS Vector table to get the address of

UNUSED

UNI-'SED

UNUSED

PTSBLOCK

UNUSED

PTSBLOCK

PTSDST(HI)

REG (HI)

UNUSED

PTSDEST (HI)

PTSDST(LO)

REG (LO)

UN,USED

PTSDEST (LO)

PTSSRC(HI)

'S/D(HI)

PTSSRC(HI)

UNUSED

PTSSRC(LO)

SID (LO)

PT!:!SRC(LO)

UNUSED

PTSeoN

PTSCON

PTSCOUNT

PTSeoUNT

PTSCOUNT

PTSeoUNT

Single
Transfer

Block
Transfer

AID Mode

HSOMode

HSI Mode

Figure 6-3. PTS Control Blocks

5-39

)

80C196KC USER'S GUIDE

PTSSRV

06H, in HWINDOW 1

Figure 6-4. The PTSSRV and PTSSEL Registers
the PTS Control Block (PTSCB). The microcode then
executes the proper PTS cycle, based on the contents of
the PTSCB.'
The PTSCOUN1; in the "PTSCB defines the number of
PTS cycles to be run consecutively without software
intervention. Since PTSCOUNT is an 8-bit value, the
maximum number is 256. Loading PTSCOUNT with
zero causes 256 transfers to occur. At the end of each
'PTS cycle, PTSCOUNT is decremented. When
PTSCOUNT expires (i.e., equals 0), an actual interrupt
called the end-of-PTS interrupt is requested which
should inyoke any processing needed and reinitialize
the PTS chan!1el.
When PTSCOUNT expires; a unique series of events
happens. F~rst, the associated bit in PTSSEL is cleared
to inhibit any additional PTS cycles until after, the endof-PTS inter..rupt has executed. Secondly, the associated

bit in PTSSRV (PTS Serve) is set to actually request the
end-of-PTS interrupt. PTSSRV is located in HWindow
1 at 06H (see Figure 6-4). The PTSSRV register acts
just like the Interrupt Pending registers in requesting
interrupts. The PTSSRV register is used instead of the
Pending Registers for the end-of-PTS interrupt so one
actual PTS request from the interrupt source can be
buffered in the Pending Register.
The end-of-PTS interrupt vectors through, the associated location in the interrupt vector table. For example, if
the TI interrupt is mapped to its PTS channel with its
PTS vector at 2050H, its end-of-'PTS interrupt is at
2030H. The end-of-PTS interrupt has the same priority
as the normal interrupt vector. When the end-of-PTS
interrupt is called, the bit in PTSSRV is automatically
cleared .. however the PTSSEL bit must be set manually
t? reenable the PTS channel. See Figure 6-5.

5-40

80C196KC USER'S GUIDE

Interrupt Source,

270704-90

Figure 6-5

6.2 PTS Modes

I M2 I M1
PTS SINGLE TRANSFER MODE

IB/W I SU OU

PTSCON
M2, MI, MO (000) PTS Block Transfer Mode
(100) PTS Single Transfer Mode
B/W
Byte (1)/Word (0) Transfer
SU
Update PTSSRC at End ofPTS Cycle
DU
Update PTSDST at End ofPTS Cycle
SI
PTSSRC Auto-Increment
DI
PTSDST Auto-Increment

In the Single Transfer Mode, the PTSCB (Figure 6-3)
contains control (PTSCON), source (PTSSRC), destination (PTSDST), and count (PTSCOUNT) registers.
A single transfer may be a byte or word and the
PTSSRC and PTSDST may be optionally incremented
at the end of the PTS cycle (see PTSCON in Figure
6-6). The registers increment by I for a byte transfer or
by 2 for a word transfer. In the single transfer mode,
both the auto-increment (SI, DI) and update bits (SU,
DU) must be set if either PTSSRC or PTSDST are to
be incremented.

I M2 I M1 I MO I

IUPOTI

PTSCON
M2, MI, MO (110) PTS AID Mode
(011) PTS HSI Mode
(001) PTS HSQ Mode
Optional Update of Incremented
UPDT
Value to:
AlD- SID REGISTER
HSI- PTSDST
HSO-PTSSRC
Figure 6-6. PTS Control Register Format

5-41

80C196KC USER'S GUIDE

During a single transfer cycle, a byte or word is transferred from the memory location pointed to by the
PTSSRC to the memory location pointed to by
PTSDST. PTSSRC and PTSDST are optionally incremented with the SI, SU and DI, DU bits. PTSCOUNT
is then decremented. If PTSCOUNT equals 0, the appropriate PTSSRV bit is set and the PTSSEL bit is
cleared to disable any further PTS cycles until the Endof-PTS ISR is executed.
A single transfer takes 18 states + 3 for each memory
controller reference.
'
At this time, an example would probably be of great
help. Let's say a 128-byte block of contiguous memory
needs to be transmitted over the serial port to another
host processor. Figure 6-7 shows the code necessary to
accomplish this task using the TI interrupt and an Interrupt Service Routine. This code takes 35 state times

to set up the ISR, 84 states to transfer each byte, and 59
states for the final ISR for a total of 10727 state times
(35 + 127 (84) + 59).
This same task clm easily be accomplished using the
PTS channel associated with the TI interrupt with
much less CPU overhead. The PTS channel is set up to
do a single byte transfer on every TI PTS request. The
PTSDST register always points to SBUF and does not
increment. The PTSSRC register points to the beginning of the block of memory and is set up to increment
every PTS cycle. The code to set up the PTS channel
and the End-of-PTS interrupt is shown in Figure 6-6. It
takes 64 state times to set up the PTS channel, 21 state
times t9 transfer each byte, and 54 state times for the
End-of-PTS interrupt for a grand total of 2721 state
times (64 + 127 (21) + 54). This reduces the software
overhead of this task by 75% compared to an Interrupt
Service Routine.

CSEG AT 2030H
TI ISR
DCW

;SET UP TI INTERRUPT VECTOR

;code to initialize TI interrupt
LDB
LDB
LDB
LDB
LD

IOCl,#00100000B
SPCON,#00001001B
BAUD_REG, #77
BAUD REG,#80H
POINTER, #BEG_ TABL ,

LDB
EI
LDB

SBUF, [POINTER] +

; ENABLE TXD PIN
;SET UP SERIAL PORT FOR MODE 0
;SET UP FOR 9600 BAUD @ 12 MHz
;POINT AT BEGINNING OF TABLE
;TO BE TRANSMITTED.
;INTIALIZE INTERRUPT MASK REG
;ENABLE INTERRUPTS
;TRANSMIT FIRST BYTE IN TABLE

TRANSMIT INTERRUPT SERVICE ROUTINE
ROUTINE TAKES 84 STATE TIMES TO TRANSMIT BYTE, 59 IF IT SETS
THE TRANSMISSION DONE FLAG
TI ISR:
, PUSHF
;MAKE BACKUP COpy OF SP_STAT
LDB SP_TMP,SP_STAT
JBC SP_TMP,5,OUT
;CHECK FOR BOGUS INTERRUPTS
ANDB SP TMP,#00100000B
;CLEAR TI BIT INSP TEMP
CMP POINTER,#END_TABL
;CHECK TO SEE IF AT END OF TABLE
JNE TRANS AGAIN
ORB FLAGS;#OOOOOOOOIB
;IF AT END OF TABLE, SET A FLAG
SJMP OUT
;TO INDICATE DONE TRANSMITTING
TRANS AGAIN:
LDB SBUF, [POINTER] +
;SEND ANOTHER BYTE
OUT:
POPF
RET
;RETURN TO MAIN PROGRAM
270704-79

Figure 6-7. Transmit Interrupt Service Routine

5-42

inter

80C196KC USER'S GUIDE

CSEG AT 2030H
OCW TI END PTS_INT
CSEG AT 2050H
OCW TIPTSCNT

;SETUP END OF PTS INTERRUPT
;SETUP PTS VECTOR BY POINTING
;AT THE PTSCON REGISTER

RSEG AT OFOH
TIPTSCNT:
OSB
OSB
TIPTSCON:
OSW
TIPTSSRC:
OSW
TIPTSOST:

1
1
1
1

;COOE TO INITIALIZE THE PTS
LOB IOC1,#OOlOOOOOB
LOB SPCON,#OOOOlOOlB
LOB BAUD REG,#80H
LOB BAUD-REG, #77
LDB TIPTSCON,#10011010B
LD
TIPTSSRC,#BEG TABL

;SET
:PTS
:PTS
;PTS
;PTS

UP PTS CONTROL BLOCK
COUNT REGISTER
CONTROL REGISTER
SOURCE REGISTER
DESTINATION REGISTER

;ENABLE TXD PIN
;SET UP SERIAL PORT MODE 0
;9600 BAUD @ 12 MHz
;PTS CHANNNEL FOR SINGLE BYTE TRANSFER
;UPDATE SRC, DO NOT UPDATE DT

TIPTSDST,*SBU~

;POINT PTSDST AT TABLE, PTSSRC @ SBUF

LDB
LOB
LDB
LD
CLRB
LDB
EPTS
EI

TIPTSCNT,#127
INT MASK1,#OOOOOOOlB
WSR;#l
PTSSEL,#OlOOH
WSR
SBUF, [TIPTSSRC]+

;127 PTS CYCLES BEFORE END-OF-pts INTERRUPT
;SETUP INTERRUPT MASK
;CHANGE HWINDOW TO 1
;ENABLE PTS CHANNELOVER INTERRUPT
;SWITCH BACK TO WINDOW 0
;TRANSMIT FIRST £YTE MAUALLY
;ENABLE PTS

TI ENO_PTS_ISR:
PUSHF
FLAGS,#OOOOOOOlB
ANDB
POPF
RET

;SET FLAG INDICATING
;TRANSMISSIONS DONE
270704-80

Figure 6-8. Transmit Interrupt PTS Example

Transfer with the SI and DI bits, and using the SU and
DU bits, keep their final value or revert to their value at
the beginning of the PTS cycle. Finally, the
PTSCOUNT register is decremented and if it equals 0,
the PTSSRV bit is set and the PTSSEL bit is cleared to
request the end-of-PTS interrupt.

PTS BLOCK TRANSFER MODE

For a PTS Block Transfer, the PTSCB (Figure 6-3)
contains all the same registers as the Single Transfer
Mode with the addition of a block count (PTSBLOCK)
register. The PTSCON also retains the same format as
the Single TranSfer Mode (see Figure 6-6).

A Block Transfer PTS cycle takes 13 states + 7 for
each transfer (1 minimum) + 3 for each memory controller reference. ,

When a Block Transfer is selected, PTSBLOCK determines how many byte or word transfers will take place
(N = 1 to 32 transfers). Loading a zero in PTSBLOCK
causes 32 transfers to take place. N transfers take place
from the memory pointed to by PTSSRC to the memory pointed to by PTSDST. PTSSRC and PTSDST are
optionally incremented after each transfer by the SI and
DI bits. When N transfers have expired, the PTSSRC
and PTSDST registers are optionally updated with the
SU and DU. bits. This allows the PTSSRC and
PTSDST registers to be incremellted during a Block

Care must be taken when using the Block Transfer. A
Block Transfer cannot be interrupted. It would be very
easy to make a long uninterruptable instruction with a
Block Transfer. Taking the worst case, a Block Transfer of 32 words from ,external source to external destination over an 8-bit bus would take about 500 states
(assuming no wait states).

5-43

80C196KC USER'S GUIDE

PTS AID MODE

The AID mode al.1ows automatic restart of the AID
converter while storing the previous result in a table
located in memory by mapping the AID_DONE interrupt to its PTS channel. Figure 6-9 shows the AID
table format. The User sets up the AID commands in
the table and the PTSloads the AID with the commahd and stores the result in the appropriate table location. For more information on the AID Converter,
see Section 12.

This makes it easier to save several HSI events in memory for later processing. The format of the HSI table is
shown in Figure 6-10. For more information on the
HSI, see Section 9.

XXX+OA
XXX+8
XXX+6
XXX+4
XXX+2

XXX+OA
XXX+8
XXX+6
XXX+4
XXX+2
XXX'

AID RESULT 2

XXX'

I AID COMMAND 3

HSI_TIMEJ
HSLSTATUSJI HSI_STATUSJ
HSI TIME

HSI_STATUS_11 HSI_STATUS_1
HSI_TIME_O
HSI_STATUS_O I HSI_STATUS_O

+-PTSDST

'XXX Can Lie anywhere in addressable memory space

AID RESULT 1

Figure 6-10. HSI PTS Table

I AID COMMAND 2
AID RESULT

I AID COMMAND 1

+-S/D

'XXX Can lie anywhere in addressable memory space

The PTSCB is made up of a destination register
(PTSDST). a block count register (PTSBLOCK), and
the control register (PTSCON) as shown in Figures 6-3
and 6-5. PTSDST can be optionally updated at the end
of the PTS cycle by setting the UPDT bit in PTSCON.

Figure 6-9. PTS AID Table Format

When this PTS cycle is initiated, PTSBLOCK is read
to determine how many HSI transfers will take place
(N = I to 7). For each transfer, the HSI_STATUS
and HSI_TIME registers are written out to consecutive words in memory pointed to by the PTSDST.
When N transfers have finished, PTSDST is optionally
updated. Finally the value in PTSCOUNT is decremented and if it is 0, the PTSSRV bit is set and the
PTSSEL bit is cleared to request the End-of-PTS interrupt.

The PTSCB contains a sourceldestination register
(SID), a register address (REG), and the PTS control
register (PTSCON). The PTSCON format for the AID
Mode is shown in Figure 6-5. The SID register points
to the table in memory, and REG will point to the
AD_COMMAND register at location 02H in HWindow O.
In a PTS AID cycle, the word pointed to by SID is
loaded into a temporary internal register. SID is then
incremented by 2. Next, the AD_RESULT register is
stored at the location pointed to by SID. The AID
command stored in the temporary register is now loaded into the AD_COMMAND register to initiate another AID conversion. Now the SID is optionally updated to point to the next word in the table with the
UPDT bit in PTSCON. If the SID is not updated, the
same AID command is read and the result stored in
the same location for every PTS cycle.. Fiqally.
PTSCOUNT is decremented and if it is zero, t\le
PTSSEL bit is cleared and the PTSSRV bit is set to
request the end-of-PTS interrupt.

The HSI can generate an interrupt or PTS request
when the FIFO contains I, 5 or 7 entries, so the
PTSBLOCK register should contain one of these values.
The HSI mode takes 12 state times + 10 for each block
transfer (I minimum) for Internal RAM/SFR space
and 16 states + 10 for each block transfer (I minimum) with memory controller references.
PTS HSO (HIGH SPEED OUTPUT) Mode

The PTS HSOmode allows the HSO CAM to be loaded from a table located in internal or external memory
as shown in Figure 6-11. For further information on the
HSO, see Section 10. The HSO mode operates the same
way as the HSI mode except the table is read rather
than written.

The AID mode takes 21 states when the table is in
internal RAM/SFR space (O-IFFH) and 25 states
with memory ..controller references (200H -OFFFFH).
PTS HSIMODE

The PTS HSI mode allows the FIFO to be dumped out
to a table in ·either internal or external tnemory by mapping one of the 3 HSI interrupts to its PTS channel.

5-44

80C196KC USER'S GUIDE

HSO_TIME_2

XXX,+OA
XXX+8

UNUSED

XXX+6
XXX+4

UNUSED

COMMAND_2

I HSO

COMMAND_l

HSO_TIME_O

XXX+2
XXX'

I HSO

HSO_TIMLl

UNUSED

I HSO

COMMAND_O

<-PTSSRC

'XXX Can Lie anywhere in addressable memory space

Figure 6·11. PTS HSO Table

gram of the circuit is shown in Figure 7-1. The 8-bit
counter is incremented every state time. When it equals
0, the PWM output is set to a one. When the counter
matches the value in the corresponding PWM register,
the output is switched low. When the counter overflows, the outputs are once again switched high. A typical output waveform is shown in Figure 7-2. When the
PWM register equals 00, the output is always low. Additionally, the PWM register will only be reloaded from
the temporary latch when the counter"overtlows. This
means the compare circuit will not recognize, a new
value until the counter has expired preventing missed
edges.

The, PTSCB contains a PTSSRC, PTSBLOCK, and
PTSCON register. The PTSCON register for the HSO
mode is shown in Figure 6-6. The source must always
be incremented and the source can be optionally updated at the end of the PTS cycle. When this PTS cycle is
initiated, PTSBLOCK is read to determine how many
HSO transfers will take place (N ,= I to 8). For each
transfer, the two consecutive words pointed to by
PTSSRC are read and loaded into the HSO_COMMAND and HSO_TIME registers, respectively.
When the N transfers are done, PTSSRC is optionallY
incremented and PTSCOUNT is decremented. If
PTSCOUNT equals 0, the PTSSEL bi~ is cleared and
the PTSSRV is set to request an End-of"PTS interrupt.

The 80Cl96KC PWM unit has a prescaler bit (divide
by 2) which is enabled by setting IOC2.2 = I. ~he
output waveform is a variable duty cycle pulse whIch
repeats every 256 or 512 state times (32 JLS or 64 JLs ,at
16 MHz). Changes in the duty cycle are made by WrIt-,
ing to the PWM register, PWMO register is at l.ocation
l7H in HWindow 0 and the value programmed mto the
PWMO register can be read in HWindow 15 (WSR =
15). PWMO is compatible with the PWM output on the
80C196KB. PWMI and PWM2 registers are located at
location 16H and' 17H in HWindow 1 ,and are read!
writable in HWindow 1. There are several types of motors which require a PWM waveform for more efficient
operation. Additionally, if this waveform is integrated
it will produce a DC level which can be changed in 256
steps by varying the duty cycle, as described in the next
section.

The PTS HSO mode takes II state times + 10 for each
block transfer (l minim~m) with internal RAM!SFR
space or IS states + II for each block transfer (I minimum) with memory controller references.
PTS Latency

Because the prelude to a PTS request is so much like
that of an Interrupt, the latency is calculated in the
same manner. PTS latency is therefore defined to be the
longest instruction (NORML - 39 states) + 4 states
= 43 states. See Figure 5-5. This does not include any
higher priority PTS requests that may be executing or
any time that the PTS is disabled via the PSE bit in the
PSW.

XTAL1 =

8MHz

10 MHz

16MHz

IOC2.2 = 0
IOC2.2 = 1

15.6 KHz
7.8 KHz

19.6 KHz
9.8 KHz

31.25 KHz
15.63 KHz

Figure 7·3. PWM Frequencies

The PWMO output shares a pin with Port 2, pin 5 so
that these two features cannot be used at the same time.
IOC1.0 equal to 1 selects the PWM function. PWMI
and PWM2 are multiplexed on Port 1, pins 3 and 4,
respectively. IOC3 register bit 2 and 3 in HWindow 1
enables the PWM I and PWM2 outputs over the port
function. All three PWM outputs use the same timer.
Therefore, the outputs go high at the same time. When
the pins are enabled as PWMs, the pin is no longer a
quasi bidirectional port but has strong pullups and rulldowns. The ports cannot be returned to quasi bidirectionals unless the device is reset.

7.0 PULSE WIDTH MODULATION
OUTPUT (D/A)
Digital to analog conversion can be done with any.of
three Pulse Width Modulation outputs; a block dla-

5-45

intJ

80C196KC USER'S.GUIDE

7.1 Analog Outputs
Analog outputs can be generated by two methods, either by using the PWM output or the HSO. Either
device will generate a rectangular pulse train that varies
in duty cycle and period. If a smooth analog signal is
desired as an output, the rectangular waveform must be
filtered.
In most cases this filtering is best done after the signal
is buffered to make it swing from 0 to 5 volts since both
of the outputs are guaranteed only to low current levels. A block diagram of the type of circuit needed is
shown in Figure 7-4. By proper selection of compomints, accounting for temperature and power supply
drift, a highly accurate 8-bit D to A converter can be
made using either. the HSO or the PWM output. Figure
7-5 shows two typical circuits. If the HSO is used the
accuracy could be theoretically extended to 16-bits,
however the temperature and noise related problems
would be extremely hard to handle.

PWM
OUTPUT

STATE TIME CLOCK
F(XTALI )/2

270704-12

When driving some circuits it may be desirable to use
unfiltered Pulse Width Modulation. This is particularly
true for motor drive circuits. The PWM output can
generate these waveforms if a fixed period on the order
of 32 ,...S is acceptable. If this is not the case then the
HSO unit can be used. The HSO can generate a variable waveform with a duty cycle variable in up to 65536
steps and a period of up to 66 milliseconds with
Timer!'

• Duty Cycle Programmable in 256 Steps

Figure 7·1. PWM Block Diagram

DUTY
CYCLE

PWM CONTROL
REGISTER VALUE

OUTPUT WAVEFORM

HI
LO

10%

~~.Jl~__~n~____~n~____

50%

128

HI
LO

80%

230

~..J

119.8%

255

HI
LO

u
270704-13

Figure 7·2. Typical PWM Outputs

80C196KC
HSO
OR
PWM

f-+

BUFFER
TO MAKE
OUTPUT
SWING
RAIL
TO
RAIL

r--+

FILTER
(PASSIVE
OR
ACTIVE)
(OPTIONAL)

----.

POWER
AMP
(OPTIONAL)

ANALOG
f-+ OUTPUT

270704-14

Figure 7·4. 01 A Buffer, Block Diagram
5-46

inter

80C196KC USER'S GUIDE

Vee

* 1/2 VQ3001P
270'

5.lK

t-____~~----~-----AN;~~G

PWM----~~~----.

270704-15

~OC196:Kt ~._________

I- I

~ t"

1-:+--=
270704-16

. Figure 7-5. Buffer Circuits for 01 A

1+----------------P2.7
UP

DOWN __

't~P2.6
IOC2.1
1 + - - - T2 INTERNAL CLOCK
1+---T2CLK
1+---HSI.l

'------------------T2RST

270704-5

Figure 8-1. Timer Block Diagram

Timer!. Writes to Timerl should be taken into account
in software to -ensure events in the HSO CAM are not
missed or occur in an order which may be unexpected.
Changing Timerl with incoming events on the High
Speed Input lines may corrupt relative references between captured inputs. Further information on the
High Speed Outputs and High Speed Inputs can be
found in Sections 9 and 10 respectively.

8.0 TIMERS
Figure 8-1 shows Timerl and Timer2

8.1 Timer1
Timerl is a 16-bit free-running timer which is incremented every eight state times. An interrupt can be
generated in response to an overflow. It is read through
location OAH in HWindow 0 and written in HWindow
15. Care must be taken when writing to it if the High
Speed I/O (HSIO) Subsystem is being used. HSO time
entries in the CAM depend on exact matches with

8.2 Timer2
Timer2 on the 80C196KC can be used as a reference
for the HSO unit, an up/down counter; an external
event capture or as an extra counter. Timer2 is clocked
5-47

80C196KCWSER'S GUIDE

externally using either the T2CLK pin or the HSI.l pin
Timer2 counts on both positive and negative transitions. The maximum transition speed is once per state
time in the Fast Increment mode, and once every 8
states otherwise. New on the80C196KC, Timer2 can
be clocked internally every 1 or 8 state times. Timer2
can be read and written through location OCH in
HWindow O. Timer2 can be reset by hardware, software or the HSO unit. Either T2RST or HSI.O can
reset Timer2 externally depending on the setting of
IOCO.5. Figure 8-2 shows the configuration and input
pins of Timer2. Figure 8-3 shows the reset and clocking
options for Timer2. The appropriate control registers
can be read in HWindow 15 to determine the programmed modes. However, IOCO.l (T2RST) is not
latched and will read a 1.

Fast Increment Mode

Timer2 can be programmed to run in fast increment
mode to count transitions every state time. Setting.
IOC2.0 programs Timer2 in the Fast Increment mode.
IIi this mode, the events programmed on the HSO unit
with Timer2 as a reference will not execute properly
since the HSO requires eight state times to compare
every location in the HSO CAM. With Timer2 as a
reference for the HSO unit, Timer2 transitioning every
state time may cause programmed HSO events to be
missed. For this reason, Timer2 should not be used as a
reference for the HSO if transitions occur faster than
once every eight state times.
Timer2 should not be RESET in the fast increment
mode. All Timer2 resets are synchronized to an eight
stat<; time clock. If Timer2 is reset when clocking faster
than once every 8 states, it may reset on a different
count.

Caution should be used when writing to the timers if
they are used as a reference to the High Speed Output
Unit. Programmed HSO commands <;ould be missed if
the timers do not count continuously in one direction.
High Speed Output events based on Timer2 must be
carefully programmed when using Timer2 as an
up/down counter that can be reset externally. Programmed events could be missed or occur in the wrong
order. Refer to Section 9 for more information on using
the timers with the High Speed Output Unit.

Internal Clock Mode

A new feature on the 80Cl96KC is the ability for
Timer2 to be clocked internally. Timer2 can be clocked
every 1 or 8 states. In the 8 state mode, Timer2 increments at the same time as Timer!. Internal clocking is
enabled by setting IOC3.0 Clocking Timer2 every state
time is controlled by setting IOC2.0 while clearing
IOC2.0 causes Timer2 to count every 8 states.

.Capture Register

The value in Timer2 can be captured into the
TZCAPTURE register by a rising edge on Port 2 pin 7.
The logic level must be held for at least one state time
as discussed in the next section. T2CAPTURE is located at OCH in HWindow 15. The interrupt generated by
a T2CAPTURE vectors through location 2036H.
Bit

Up/Down Counter Mode

Timer2 can be made to count up or down based on the
Port 2.6 pin if IOC2.1 = 1. However, caution must be

Bit", 0
No action

IOCO.1

Reset Timer2 each write

IOCO.3

Enable external reset

Disable

IOCO.5

HSI.O is ext. reset source

T2RST is reset source

lOCO.?

HSI.1 is T2clock source

T2CLK is clock source

IOC1.3

Enable Timer2 overflow int.

Disable overflow interrupt

IOC2.0

Disable fast increment

. Enable fast increment

IOC2:1

Enable downcount feature

Disable down count

P2.6

Count down if IOC2.1 = 1

Count up

IOC2.5

Interrupt on 7FFFH/8000H

Interrupt on OFFFFH/OOOOH

P2.7

Capture Timer2 into
T2CAPTURE on rising edge

IOC3.0

Selects Timer2 internal
clock source

Selects Timer2
external clock source

Figure 8·2. Timer2 Configuration and Control Pins
5-48

80C196KC USER'S GUIDE

used when this feature is working in conjunction with
the HSO. If Timer2 does not complete a full cycle it is
possible to have events in the CAM which never match
the timer. These events would stay in the CAM until
the CAM is cleared or the chip is reset.

Interrupts can be generated if Timer2 crosses the
OFFFFH/OOOOH boundary or .the 7FFFH/8000H
boundary in either direction. By having two interrupt
points it is possible to have interrupts enabled even if
Timer2 is counting up and down centered around one
of the interrupt points. The boundaries used to control
the Timer2 interrupt is determined by the setting of
IOC2.5. When set, Timer2 will interrupt on the
7FFFH/8000H boundary, otherwise, the OFFFFH/
OOOOH boundary interrupts.

8.3 Sampling on External Timer Pins .
The T2UP/DN, T2CLK, T2RST, and T2CAP pins are
sampled during PH1. PHI roughly corresponds to
CLKOUT low externally. For valid sampling, the inputs should be present 45 ns prior to the rising edge of
CLKOUT or it may not be 'sampled until the next
CLKOUT. To synchronize the inputs, the rising edge
of CLKOUT should latch the inputs and hold them
until the next rising edge of CLKOUT. T2UP/DN and
T2CLK need to be synchronized unless they never
transition within one state time of each other. Otherwise, Timer2 may count in the wrong direction.

A T2CAPTURE interrupt is enabled by setting INT_
MASK1.3. The interrupt will vector through location
2036H.
Caution must be used when examining the flags, as any
access (including Compare and Jump on Bit) of 10SI
clears bits 0 through 5 including the software timer
flags. It is, therefore, recommended to copy the byte to
a temporary register before testing bits. Writing to
lOS I in HWindow 15 will set the status bits but not
cause interrupts. The general enabling and disabling of
the timer interrupts are controlled by the Interrupt
Mask Register bit O. In all cases., setting a bit enables a
function, while clearing a bit disables it.

8.4 Timer Interrupts
Both Timerl and Timer2 can trigger a timer overflow
interrupt and set a flag in the I/O Status Register I
(lOS I). Timerl! overflow is controlled by setting
IOC1.2 and the interrupt status is indifated in IOS1.5.
The TIMER OVERFLOW interrupt is enabled by setting INT_MASK.O.

9.0 HIGH SPEED INPUTS
The High Speed Input Unit (HSI) can record the time
an event occurs with respect to Timer!. There are 4
lines (HSI.O through HS1.3) and up tOI a total of 8
events can be recorded. HSI.2 and HSI:3 are bidirectional pins which can also be used as HSO.4 and
HSO.5. The I/O Control Registers (lOCO and lOCI)
determine the functions of these pins. The values programmed into lOCO and lOCI can be read in HWindow 15. A block diagram' of the HSI unit is shown in
Figure 9-1.
.

A Timer2 overflow condition interrupts through location 2000H by setting IOC1.3 and setting INT_
MASK.O. Alternatively, Timer2 overflow can interrupt
through location 2038H by setting INT_MASK1.4.
The status of the Timer2 overflow interrupt is indicated
in !OS 1.4.

HSI.1

T2CNT

IOCO.7- - - --

HSO# 14 ~----,
lOCO. 1 ~---I

,
IOCO.5

270704-17

Figure 8-3_ Timer2 Clock and Reset Options
5-49

inter

80C196KC USER'S GUIDE

FIFO
INTERRUPT
&:
CONTROL LOGIC

~lTSIMER
~

7x20 BIT
FIFO

HSI Trigger Option

270704-19

~ HITOlO

-r-

lOTOHI

~ORlo'""L..

.hnnruuuW
EVERY EIGHTH POSITIVE
TRANSITION

270704-18

Figure 9-1. High Speed Input Unit

9.1 HSI Modes

HSI Status Register (HSI_Status)
17

sl5

413

2 11 101 06H

HSI.O STATUS
HSI.1 STATUS
HSI;2 STATUS

There are 4 possible mqdes of operation for each of the
HSI pins. The HSI_MODE register at location 03H
controls which pins will look for what type of events. In
HWindow 15, reading the register will read back the
programmed HSI mode. The 8-bit register is set up as
shown in Figure 9-3.

HSI.3 STATUS
WHERE FOR EACH 2 - BIT STATUS FIELD THE LOWER
BIT (STATUS BIT) INDICATES WHETHER OR NOT.AN EVENT
HAS OCCURED ON THIS PIN AND THE UPPER BIT (INPUT BIT)
INDICATES THE CURRENT INPUT LEVEL Of" THE PIN.
270704-20

l7 61 5

41 3

211J

03H

HSI•O MODE
HSI.1 MODE

Figure 9-2. HSI Status Register Diagram

HSI.2 MODE

When an HSI event occurs, a 7X20 FIFO stores the 16
bits of Timerl, and the 4 bits indicating which pins
recorded events associated with that time tag. Multiple
pins can recognize events with the same time tag.
Therefore, if multiple pins are being used as HSI inputs,
software must check each status bit when processing an
HSI event. It can take up to 8 state times for this information to reach the holding register. For this reason, 8
state times must elapse between consecutive reads of
HSI_TIME. When the FIFO is full, one additional
event, for a total of 8 events, can be stored by considering the holding register part of the FIFO. If the FIFO
and holding register are full, any additional events will
not be recorded. .

HSI.3 MODE
WHERE EACH 2 - BIT MODE CONTROL FIELD
,
DEf"lNES ONE OF 4 POSSIBLE MODES:
00
01
10
11

8 POSITIVE TRANSITIONS
EACH POSITIVE TRANSITION
EACH NEGATIVE TRANSITION
EVERY TRANSITION
(POSITIVE AND NEGATIVE)
270704-21

Figure 9-3. HSI Mode Register 1

5-50

inter

80C196KC USER'S GUIDE

The maximum input speed is I event every 8 state times
except when the 8 transition mode is used, in which
case it is I transition per state time.

SOfTWARE TIMER 0 EXPIRED
SOfTWARE TIMER 1 EXPIRED

The HSI pins can be individually enabled and disabled
using bits in lOCO, as shown in Figure 9-4. If the pin is
disabled, events are not entered in the FIFO. However,
the input bits 9f the HSI_STATUS (Figure 9-2) are
always valid regardless of whether the pin is enabled to
the FIFO. This allows the HSI pins to be used as general purpose input pins.

SOfTWARE TIMER 2 EXPIRED
SOfTWARE TIMER 3 EXPIRED
TIMER 2 HAS OVERfLOW
TIMER 1 HAS OVERfLOW
HSI fifO IS fULL
HSI HOLDING REGISTER DATA AVAILABLE
16H

T2RST--o .'- - IOCO.S
,

HSI.O

270704-23

I : > ' o - o / - - - - T 2 RESET
i
~ - - IOCO.3
• - - IOCO.O

:>'0------:>'0-------

'Figure 9-5. 1/0 Status Register 1

will also be indeterminate. The four HSI_STATUS
bits which indicate the current state of the pins will
always return the correct value.

HSI

• - - IOCO.2

HSI.l
T2CLK - - 0 • -, IOCO.7

HSI

It should be noted that many of the status register conditions are changed by a reset, see Section 13. Writing
to HSI TIME in HWindow 15 will write to the HSI
FIFO holding register. Writing to HSI_STATUS in
HWindow 15 will set the status bits but will not affect
the input bits.

m.lER2
CLOCK

.- - IOCO.4

"'-0......------- HSI
• - - IOCO.6
HSI.3 - - 0
"'-0------.,..- HSI
HSI.2 - - 0

270704-22

9.3 HSllnterrupts

Fi9ure 9-4. lOCO Control of HSI Pin Functions

Interrupts can be generated by the HSI unit in three
ways: each time a value moves from the FIFO into the
holding register, when the FIFO has 4 or more'evcnts
stored; when the FIFO has 6 or more events.

9.2 HSI Status
Bits 6 and 7 of I/O Status Register I (lOCI-see Figure 9-5) indicate the status of the HSI FIFO. If bit 7 is
set, the HSI holding register is loaded. The FIFO may
or may not contain 1-5 events. If bit 6 of lOCI is set,
the FIFO contains 6 entries. If the FIFO fills, future
events will not be recorded. Reading lOCI clears bits
0-5, so keep an image of the register and test the image
to retain all 6 bits.

The HSI_DATA~VAILABLE and HSI_FIFO_
FULL interrupts are shared on the 8096BH. The
source for the HSLDATA-AVAILABLE interrupt
is controlled by IOCI.7. When IOC1.7 is cleared, the
HSI will generate an interrupt when the holding register is loaded. The interrupt indicates at least one HSl
event has occurred and is ready to be processed. The
interrupt vectors through location 2004H. The in.terrupt is enabled by setting INT_MASK.2. The generation of a HSI_DATA~VAILABLE interrupt will
set lOS 1.7. The HSI_FIFO_ FULL interrupt will
vector through HSI_DATA~VAILABLE if
IOC1.7 is set. On the 80C196KC, the HSI_FIFO_
FULL has a separate interrupt vector at location
203CH.

The HSI holding register must be read in a certain order. The HSI_STATUS Register (Figure 9-2) is read
first to obtain the status and input bits. Second, the
HSI~TIME Register (04H) is read to obtain the time
tag. Reading HSI_TIME unloads one level of the
FIFO. If the HSI_TIME is read before HSI_
STATUS, the contents of HSI_STATOS associated
with that time HSI_TIME tag are lost.

A HSI_FIFO_FULL interrupt occurs when the
HSI~FIFO has six or more entries loaded independent

If the HSI_TIME register is read without the holding
register being loaded, the returned value will be indeterminate. Under the, same conditions, the four bits in
HSI_STATUS indicating which events have occurred

5-51

inter

80C196KC USER'S GUIDE

of the holding register. Since all interrupts are rising
edge triggered, the processor will not be reinterrupted
until the FIFO first contains 5 or less records, then
contains six or more. The HSI FIFO FULL interrupt
mask bit is INT_MASKI.6. The occurrence of a HSI
FIFO FULL interrupt is indicated by IOSI.6. Earlier
warning of a impending FIFO full condition can be
achieved by the HSI FIFO 4th Entry interrupt.

9.5 Initializing the HSI
When starting the HSI, two things need to be done.
The FIFO should first be fl\lshed and the HSI initialized. The· FIFO should be flushed to clear out any
pending events. The following section of code can be
used to flush the FIFO:
reflush: ld 0., HSLTIME ;clear an event
skip
;wait 8 state times
skip
jbs 100Sl, 7, reflush

The HSI_FIFO_4 interrupt generates an interrupt
when four or more events are stored in the HSI FIFO
independent of the holding register. The interrupt is
enabled by setting·' INT_MASKI.2. The HSI_
FIFO_4 vectors indirectly through location 2034H,
There is no status flag associated with the HSI_
FIFO_4 interrupt since it has its own independent interrupt vector.
.

When initializing the HSI, interrupt(s) need to be enabled and the HSI pins need to be individually enabled
to the FIFO through lOCO. It is very important to
initialize the interrupts before the HSI pins or a FIFO
lockout condition could occur. For example, if the H~I
pins were enabled first, an event could get loaded into
the holding register before the HSI_DATA_A VAILABLE interrupt.is enabled. If this happens, no HSI_
DATA-..:AV AILABLE interrupts will ever OCCljr.

The HSI.O pin can generate an interrupt on the rising
edge even if its not enabled to the HSI FIFO. An interrupt generated by this pin vectors through location
2008H.

9.4 HSI Input Sampling

10.0 HIGH SPEED OUTPUTS

The HSI pins are sampled internally once each state
time. Any value on these pins must remain stable for at
least I full state time to guarantee that it is recognized.
The actual sampling occurs during PH I or during
CLKOUT low. The HSI inputs should be valid at least
45 ns before the rising of CLKOUT. Otherwise, the
HSI input may be sampled in the next CLKOUT.
Therefore, if information is to be synchronized to the
HSI it should be latched on the rising edge of
CLKOUT.

The High Speed Output unit (HSO) trigger events at
specific times with minimal CPU overhead. Events are
generated by writing commands to the HSO_COMMAND register and the relative time at which the
events are to occur into the HSO_TIME register. In
HWindow 15, these registers will read the last value
programmed in the holding register. The programmable events include: starting an A/D ~onversion, resetting Timer2, setting 4 software flags, and switching 6
output lines (HSO.O through HSO.S). The. format of

HSO_
COMMAND

CAM TMR2/ SET/
LOCK TMR1 CLEAR

CAM Lock
TMR2/'fMR}
SET/CI:EAR
INT/INT
CHANNEL:
(in Hex)

4
INT/
INT

CHANNEL

Locks event in CAM if this is enabled bi IOC2.6 (ENA_LOCK)
Events Based on Timer2/Basedon Timer! if 0
Set HSO pin/Clear HSO pin if 0
Cause interrupt/No interrupt if 0
0-5: HSO pins 0-5 separately
6:
HSO pins 0 and I together
7:
HSO pins 2 and 3 together
8-B: Software Timers 0-3
C:
HSO pins 0-$ together
D:
Unflagged Event (Do not use. for future compatibility~
E:
Reset Timer2
F:
Start A/D Conversion
Figure 10-1. HSO Command Register
5-52

06H

80C196KC USER'S GUIDE

the HSO'_CO'MMAND register is shown in Figure
10-1. Command O'CH, sets or clears all of the HSO'
pins, is new on the 80C196KC O'DH is reserved for use
on future products. Up to eight events can be pending
at one time and interrupts can be generated whenever
any of these events are triggered. HSO'.4 and HSO'.5 are
bidirectional pins which are multiplexed with HSI.2
and HSI.3 respectively. Bits 4 and 6 of I/O' Control
Register 1 (IO'C1.4, IO'C1.6) enable HSO'.4 and HSO'.S
as outputs. The Control Registers can be read in HWin,dow IS to determine the programmed modes for the
HSO'. However, the IOC2.1(CAM; CLEAR) bit is not
latched and will read as a one. Entries can be locked in
the CAM to' generate periodic events or waveforms.

SOFTWARE TIMERS
The HSO' can be programmed to generate interrupts at
preset times. Up to four such "Software Timers" can be
in operation at a time. As each preprogrammed time is
reached, the HSO' unit sets a Software Timer Flag. If
the interrupt bit in the HSO' command register was set
then a Software Timer Interrupt' will also be generated.
The interrupt service routine can then examine I/O'
Status register 1 (IO'S1) to determine which software
timer expired and caused the interrupt. When the HSO'
resets Timer2 or starts an A/D conversion, it can also
generate a software timer interrupt.
If more than one software timer interrupt occurs in the
same time, multiple status bits will be set. Each read of
lOS 1 (see Figure IO-S) will clear bits 0 through 5. Be .
certain to save the byte before testing it. See also Section l2.S.

10.1 HSO Interrupts and,Software
Timers
The HSO' unit can generate two types of interrupts. The
High Speed O'utput execution interrupt can be generated (if enabled) for HSO' commands which change one
or more of the six output pins. The other HSO' interrupt can be generated by any other HSO' command,
(e.g. triggering the A/D, resetting Timer2 or a software
Timer Interrupt).

10.2 HSOCAM
A block diagram of the HSO' unit is shown in Figure
10-3. The Content Addressable Memory (CAM) file is
the center of control. O'ne CAM register is compared
with the timer values every state time, taking 8 state
times to compare all CAM registers with the timers.
This defines the resolution of the HSO to be 8 state
times (1 microsecond at an oscillator frequency of
16 MHz).
'

HSO Interrupt Status
Register IO'S2 at location I1H displays the HSO' events
which have occurred. IO'S2 is shown in Figure 10-2.
The !!vents displayed are HSO'.O through HSO'.S,
Timer2 Reset and start of an A/D conversion. IO'S2 is
cleared when accessed. Therefore, the register should
be saved in an image register if more than one bit is
being tested. Writing to this register in HWindow IS
will set the status bits but not cause interrupts. In
HWindow IS, writing to IOS2 can set the High Speed
O'utput lines to an initial value.

IOS2:

7
START

AID
l1H
read

Each CAM register is 24 bits wide. Sixteen bits specify
the time the action is to be carried out, and 8 bits define
the action to take place. The format of the command to
the HSO' unit is shown in Figure 10-1. Note that bit S is
ignored for command channels 8 through OFH, except
for command OCH.
To enter a command into the CAM file, write the 8-bit
"Command Tag" into location 0006H followed by the

T2
HSO.5 HSO.4 HSO.3
RESET

HSO.2

HSO.1

HSO.O

Indicates which HSO' event occcured
START AID: HSO'_CMD IS, start AID
T2RESET:

HSO'_CMD 14, Timer2 Reset

HSO'.O-S:

O'utput pin's HSO'.O through HSO'.S

Figure 10-2.1/0 Status Register 2

5-53

80C196KC USER'S GUIDE

16-81T
XTAL1/16
CONTROL
LOGIC

L~J

16-81T
T2CLK
T2RST

24-----t

CAM FILE

HIGH SPEED OUTPUT CONTROLS
6 PINS
.
4 SOFTWARE lilMERS
2 INTERRUPTS
INITIATE AID CONVERSION
RESET TIMER2
270704-24

BUS

Figure 10-3. High Speed Output Unit
time the action is to be carried out into word address
0004H. The typical code would be:

LOB HSO_COMMAND,#what_to_do
ADD HSO_TIME,Timerl,#when_to_do_it

can also be overwritten. Since it can take up to 8 state
times for a command to move from the holding register
to the CAM, 8 states must be allowed between successive writes to the CAM.
To provide proper synchronization, the minimum time
that should be loaded to Timer! is Timerl + 2. Smaller values may cause the Timer match to occur 65,636
counts later than expected. A similar restriction applies
if Timer2 is used.

HSO.O CURRENT STATE
HSO.1 CURRENT STATE

Care must be taken when writing the command tag for
the HSO, because an interrupt can occur between writing the command tag and loading the time value. If the
interrupt service routine writes to the HSO, the command tag used in the interrupt routine will overwrite
the command tag from the main routine. One way of
aVdiding this problem would be to disable interrupts
when writing'to the HSO unit.

HSO.2 CURRENT STATE
HSO.3 CURRENT STATE
HSO.4 CURRENT STATE
HSO.5 CURRENT STATE
CAM

HOLDING REGISTER IS FULL

HSO HOLDING REGISTER IS FULL

270704-25

10.3 HSO Status

Figure 10-4.1/0 Status Register 0,

Before writing to the HSO, ensure that the Holding
Register is empty.]f it is not, writing to the HSO will
overwrite the value in the Holding Register. I/O Status
Register 0 (IOSO) bits 6 and 7 indicate the status of the
HSO unit. If IOSO.6 equals 0, the holding register is
empty and at least one CAM register is empty. If
IOSO.7 equals O,the holding register is empty. The programmer should carefully decide which of thes.e two
flags is the best to use for each application. This register

Writing the time value loads the HSO Holding Register
with both the time and the last written command tag.
The command does not actually enter the CAM file
until an empty CAM register becomes available.
Commands in the holding register will not execute even
if their time tag is reached. Commands must be in the
CAM to execute. Commands in the holding register

5-54

inter

80C196KC USER'S GUIDE

also shows the current status of the HSO.O through
HSO.5. The HSO pins can be set by writing to this
register in HWindow 15. The format for I/O Status
Register 0 is shown ,in Figure 10·4,

10.4 Clearing the HSO and Locked
Entries
All 8 CAM locations of the HSO are compared before
any action is taken. This allows a pending external
event to be cancelled by simply writing the opposite
event to the CAM. However, once an entry is placed in
the CAM, it cannot be removed until either the speci·
fied timer matches the written value; a chip reset occurs or IOC2.7 is set. IOC2.7 clears all entries in the
CAM.

16H

SOFTWARE TIMER 0 EXPIRED
SOFTWARE TIMER 1 EXPIRED
SOFTWARE TIMER 2 EXPIRED
SOFTWARE TIMER 3 EXPIRED

Internal events cannot be cleared by writing an opposite event. This includes events on HSO channels 8-B
and E-F. The only method for clearing these events is
by a reset or setting IOC2.7.

TIMER 2 HAS OVERFLOW
TIMER 1 HAS OVERFLOW
HSI FIFO IS FULL
HSI HOLDING REGISTER DATA AVAILABLE

HSO LOCKED ENTRIES

270704-26

The CAM Lock bit (HSO_Command.7) can be set to
keep commands in the CAM, otherwise the commands
will clear from the CAM as soon as they cause an
event. This feature allows for generation periodic events
based on Timer2 and must be enabled by setting
IOC2.6. To clear locked events from the CAM, the entire CAM can be cleared by writing a 'one to the CAM
clear bit IOC2.7. A chip reset will also clear the CAM.

Figure 10-5. 1/0 Status Register 1 (1051)

The expiration of software timer 0 through 4, and the
overflow of Timer! and Timer2 are indicated in lOS 1.
The status bits can be set in HWindow 15 but not cause
interrupts. The register is shown in Figure 10·5.
Whenever the processor reads this register all of the
time· related flags (bits 5 through 0) are cleared. This
applies not only to explicit reads such as:

LDB

Locked entries are useful in applications requiring periodic or repetitive events. Timer2 used as an HSO reference can generate periodic events with the use of the
HSO T2RST command. HSO events programmed with
a HSO time less then the Timer2 reset time will occur
repeatedly as Timer2 resets. Recurrent software tasks
can be scheduled by locking software timers commands
into the High Speed Output Unit. Continuous sampling
'of the A/D converter can be accompished by programming a locked HSO A/D conversion command. One of
the most useful features is the generation of multiple
PWM's on the High Speed Output lines. Locked entries
provide the ability to program periodic events While
minimizing software overhead.

AL,IOSI

but also to implicit reads such as:

IOSl.3,somewhere_else

which jumps to somewhere_else if bit 3 ofIOSI is set.
In most 'cases this situation can best be handled by hav·
ing a byte in the register file which maintains an image
of the register. Any time a hardware timer interrupt or
a HSO software timer interrupt occurs the byte can be
updated:

ORB

Individual external events setting or clearing an HSO
pin can by cancelled by writing the opposite event to
the CAM. The HSO events do not occur untU the timer
reference has changed state. An event programmed to
set and clear an HSO event at the same time will cancel
each other out. Locked entries can correspondingly be
cancelled using this method. However, the entries remain in the HSO CAM and can quickly fill up the
available eight locations. As an alternative, all entries in
the HSO CAM can be cleared by setting IOC2.7.

IOSLimage,IOSl

leaving 10SI_image containing all the flags that were
set before plus all the new flags that were read and
cleared from 10S1. Any other routine which needs to
sample the flags can safely check lOS I_image. Note
that .if these routines need to clear the flags that they
have acted on, then the modification of lOS I_image
must be done from inside a critical region.

5-55

80C196KC USER'S GUIDE

port is functionally compatible with the serial port on
the MCS-5l family of microcontrollers, although the
software controJling the ports is different.

10.5 HSO Precautions
Timer! is incremented every S state-times. When
Timer! is being used as the reference timer for an HSO
command, the comparator has a chance to look at all S
CAM registers before Timer! changes its value. Writing to, Timer!, which is allowed in HWindow 15,
should be carefully done. The user should ensure writing to Timer! will not cause programmed HSO events
to be missed or occur in the wrong order. The same
precaution applies to Timer2.

'Data to and from the serial port is transferred through
SBUF(RX) and SBUF(TX), both located at 07H.
SBUF(TX) holds data ready for transmission and
SBUF(RX) contains data received by the serial port.
SBUF(TX) and SBUF(RX) can be'read and written in
HWindow IS.
Mode 0, the synchronous shift register mode, is designed to expand I/O over a serial line. Mode' I is. the
standard S bit data asynchronous mode used for normal
serial communications. Modes 2 and' 3 are 9 bit data
asynchronous modes typically used for interprocessor
communications.

The HSO requires at least eight state times to compare
each entry in the CAM. Therefore, the fast increment
mode for Timer2 cannot be used as a reference for the
HSO if transitions occur faster then once every eight
state times.
Referencing events when Timer2 is being used as an
up/down counter could cause events to occur in opposite order or be missed entirely. Additionally, locked
entries' could occur several times if Timer2 is oscillating
around the time tag for an entry.

11.1 Serial Port Status and Control
Control of the serial port is done through the Serial
Port Control (SP_CON) register shown in Figure
II-I. Writing to location IIH accesses SP.-:...CON while
reading it accesses SP_STAT. The upper 3 bits of
SP_CON must be written as Os for future compatibil- '
ity, On the SOCI96KC the SP_STAT regisfer contains
bits to indicate receive Overrun Error (OE), Framing
Error (FE), and Transmitter Empty (TXE), The bits
which were also present on the S096BHare the Transmit Interrupt (TI) bit, the Receive Interrupt (RI) bit,
and the Received Bit S (RBS) or Receive Parity Error
(RPE) bit. SP_STAT is read-only in HWindowO and
is shown in Figure 11-1.

When using Timer2 as the HSO reference, caution
must be taken that Timer2 is not reset prior to the
highest value for a Timer2 match in the CAM. If that
match is never reached, the event will remain in the
CAM until the device is reset or CAM is cleared.

10.6 HSO Output Timing
Changes in the HSO lines are synchronized to Timer!
or Timer2. All of the external HSO lines due to change
at a certain vlllue of a timer will change just after the
incrementing of the timer. Internally, the timer changes
every eight state times during Phase 1. From an external
perspective the HSO pin should change just prior to the
falling edge of CLKOUT and be stable by its rising
edge. Information from the HSO can be latched on the
CLKOUT rising edge. Internal events also occur when
the refere)lce timer increments.

In aU modes, the RI flag is set after the last data bit is
sampled, approximately in the middle of a bit time.
Data is held in the receive shift register until the last
data bit is received, then the data byte is loaded into
SBUF (RX), The receiver on the 80CI96KB also
checks for a valid stop bit. If a stop bit is not found
within the appropriate time, the Framing Error (FE)
bit is set.

11.0 SJ:RIAL PORT
The serial port has one synchronous and 3 asynchro- .
nous modes. The asynchronous modes are full duplex,
meaning they can transmit and receive at the same
time. The receiver is double buffered so that the reception of a second byte can begin before the first byte has
been read. The transmitter on the SOCI96KC is also
double buffered allowing continuous transmissions. The

Since the receiver is double-buffered, reception on a
second data byte can begin before the first byte is read.
However, if data in the shift register is loaded into
SBUR (RX) before the previous byte is read, the Overflow Error (OE) bit· is set. Regardless, the data in SBUF
(RX) will aLways be the latest byte received; it will never be a combination of the two bytes. The RI, FE, and
OE flags are cleared when "SP_STAT" is read. However, RI does not have to be cleared for the serial port
to receive data.

5-56

inter

80C196KC USER'S GUIDE

~-~--+--:-'-+--:--~-T-:-8-r-R-:-N-+-P-~-N-+--M-12~r-M-~~1 11H
- Sets th~ ninth data bit for transmission. Cleared after each transmission. Not valid
if parity is enabled.
REN - Enables the receiver
PEN
- Enables the Parity function (even parity)
M2, MI - Sets the mode. ModeO = 00, Model = 01, Mode2 = 10, Mode3 = 11

TB8

RB8/
RPE
RB8
RPE
RI
TI
FE
. TXE
OE

,
RI

/TXE

11H

Set if the 9th data bit is high on reception (parity disabled)
Set if parity is enabled and a parity error occurred
Set when the last data bit is sampled
Set at the beginning of the STOP bit transmission
Set if no STOP bit is found at the end of a reception
Set if tw~ bytes can be transmitted
Set if receive~ is overwritten
Figure 11-1. Serial Port Control and Status Registers

The Transmitter Empty (TXE) bit is set if the transmit
buffer is empty and ready to take up to two characters. ;
TXE gets cleared as soon as a byte is written to SBUF.
Two. bytes may be written consecutively to SBUF if
TXE is set. One byte may be written if TI alone is set.
By definition, if TXE has just been set, a transmission
has completed and TI will be set. The TI bit is reset
when the CPU reads the SP_STAT registers.
The TB8 bit is cleared after each transmission and both
TI and RI are cleared when SP_STAT is read. The RI
and TI status bits cap. be set by writing to SP_STAT in
HWindow 15 but they will not cause an interrupt.
Reading of SP_CON in HWindow 15 will read the
last value written. Whenever the TXD pin is used for
the serial port it must be enabled by setting IOC1.5 to a
1. lOCI register 1 can be read in HWindow 15 to determine the setting.

In the asynchronous modes, writing to SBUF (TX)
starts a transmission. A falling edge on RXD will begin
a reception if REN is set to 1. New data placed in
SBUF (TX) is held and will not be transmitted until the
end of the stop bit has been sent.
In all modes, .the RI flag is set after the last data bit is
sampled approximately in the middle of the bit time.
For all modes, the TI flag is set after the last data bit
(either 8th or 9th) is sent, also in the middle of the bit
time. The flags clear when SP_STAT is read, but do
not have to be clear for the port to receive or transmit.
The serial port interrupt bit is set as a logical OR of the
RI and TI bits. Note that changing modes will reset the
Serial Port and abort any transmission or reception in
progress on the channel.
DETERMINING BAUD RATES
Baud rates in all modes are determined by the contents
of a 8-bit register at location OOOEH. Reading or writing this register in HWindow 15 is reserved by Intel for
future use. This register must be loaded sequentially
with 2 bytes (least significant byte first). The MSB of
this register selects one of two sources for the input
frequency to the baud rate generator. If it is a I, the
XTALl pin is selected, if not, the T2CLK pin is used.
The maximum input frequency is 4 MHz on T2CLK.

STARTING TRANSMISSIONS AND RECEPTIONS
In Mode 0, if REN = 0, writing to SBUF (TX) will
start a transmission. A rising edge on REN, or clearing
RI with REN = I, will start a reception. Setting
REN = 0 will stop a reception in progress and inhibit
further receptions. To avoid a partial reception, REN
must be set to zero before RI is cleared. This can be
handled in an interrupt environment by using software
flags or in straight-line code by using the Interrupt
Pending register to signal the completion of a reception.

5-57

80C196KC USER'S GUIDE

This provides the needed synchronization to the internal serial port clocks.
The unsigned integer represented by the lower 15 bits
of the baud rate register defines a number B, where B
has a maximum value of 32767. The baud rate equations are shown below.

Asynchronous Modes 1, 2 and 3:
BAUD REG
-

XTAL1
-10R
T2CLK
Baud Rate' 16
Baud Rate' 8

8096BH shared the TI and RI interrupts on the SERIAL interrupt vector. On the 80CI96KC, these interrupts share both the serial interrupt vector and have
'their own interrupt vectors. Because the interrupts now
have separate vectors, you do not have to sort the interrupts out in the same interrupt service routine.
When the TI bit is set it can cause an interrupt through
the vectors at locations 200CH or 2030H. Interrupt
through location 2030H is determined by INT_
MASKl.O. Interrupts through the Serial interrupt are
controlled by the sarrie bit as the RI interrupt (IN'I:_
MASK.6).

Synchronous Mode 0:
BAUD REG =
XTAL1
-10R T2CLK
Baud Rate' 2
Baud Rate
-

Note that B cannot equal 0, except when using XTALI
and not in mode O.
Common baud rate values, using XTALI at 16 MHz,
are shown below.
Baud Register Value

Baud
Rate

Mode 0

Others

9600
4800
2400
1200
300

8340H
8682H
8D04H
9AOAH
E82BH

8067H
80CFH
81AOH
8340H
8D04H

The maximum baud rates are 4.0 Mbaud synchronous
and 1.0 Mbaud asynchronous with 16 MHz on
XTAL1.

11.2 Serial Port Interrupts
The serial port generates one of three possible interrupts: Transmit Interrupt TI(2030H), Receive Interrupt RI(2032H) and SERIAL(200cH). When the RI
bit gets set an interrupt is generated through either
20DCH or 2032H depending on which interrupt is enabled. INT_MASKl.l controls the serial port receive
interrupt through location 2032H and INT_MASK.6
controls the RI interrupt through location 2ODCH. Th~

11.3 Serial Port Modes
MODE 0
Mode 0 is a synchronous mode and is commonly used
for shift register based I/O expansion. In this mode the
TXD pin outputs a set of 8 pulses while the RXD pin
either transmits or receives data. Data is transferred 8
bits at a time with the LSB first. A diagram of the
relative timing of these signals is shown in Figure 11-2.
This is the only mode which uses RXD as an output.
Mode 0 Timings

In Mode 0, the TXD pin sends out a clock train, while
the RXD pin transmits or receives the data. Figure
11-2 shows the waveforms and timing.
In this mode the serial port expands the I/O capability
of the 80CI96KC by simply adding shift registers. A
schematic of a typical circuit is shown in Figure 11-3.
This circuit inverts the data coming in, so it must be
reinverted in software.
MODE 1

Mode 1 is the standard asynchronous communications
mode. The data frame used in this mode is shown in
Figure 11-4. It consists of 10 bits; a start bit (0), 8 data
bits (LSB first), and a stop bit (1). If parity is enabled
by setting SPCON.2, an even parity bit is sent instead
of the 8th data bit and parity is checked on reception.-

5-58 '

inter

80C196KC USER'S GUIDE

TXD

AXD(OUT)

De
De

}--

AXD(IN)
EXPANDED:

TXD

~~I-DO

RXD(OUT)

x:::

DO
RXD (IN)

---c:J----I,I----IDI---;/F#-I-270704-27

Figure 11·2. Serial Port Mode 0 Timing

CLOCK INHIBIl
~

____________ ________-;PX.
~

15K

DATA

)o~~--~---------;AXD

CLOCK
L-____~--____~--__'TXD
INPUTS

80C196KC
SERIAL IN A
ENABLE

11>-----1 PX.X
270704-28

Figure 11·3. I/O Expansion in Mode 0

5·59

intJ

80C196KC USER'S GUIDE

STOP

270704-29

270704-30

Figure 11-4. Mode 1, 2, and 3 Timing
The transmit and receive functions' are controlled by
separate shift clocks. The transmit shift clock starts
when the baud rate generator is initialized, the receive
shift clock is reset when a 'I to 0' transition (start bit) is
received. The transmit clock may therefore not be in
sync with the receive clock, although they will both be
at the same frequency.

MODE 3

·The TI (Transmit Interrupt) and RI (Receive Interrupt) flags are set to indicate when operations are complete. TI is set when the last data bit of the m<;ssage has
been sent" not when the stop bit is sent. If an attempt to
send another byte is made before the stop bit is sent the
port will hold off transmission until the stop bit is complete. RI is set when 8 data bits are received, not when
the stop bit is reCeived. Note that when the serial port
status register is read both TI and RI are cleared.

11.4 Multiprocessor Communications
Mode 2 and 3 are provided for multiprocessor communications. In Mode 2 if the received 9th data bit is zero,
the RI bit is not set, and will not cause an interrupt. In
Mode 3, the RI bit is set and always causes an interrupt
regardless of the value in the 9th bit. The way to use
this feature in multiprocessor systems is described below.

Caution should be used when using the serial 'port' to
connect more than two devices in half-duplex, (i.e. one
wire for transmit and receive). If the receiving processor does not wait for one bit time after RI is set before
starting to transmit, the stop bit on the link could be
corrupted. This could cause a problem for other devices
listening on the link.
MODE 2

Mode 2 is the asynchronous 9th bit recognition mode.
This mode is commonly used with Mode 3 for multi"
processor communications. Figure 11-4 shows the data
frame used in this mode. It consists of a start bit (0),_ 9
data bits (LSB first), and a stop bit (I). When transmitting, the 9th bit can be set to a one by setting the TB8
bit in the control register before writing to SBUF (TX). )
The TB8 bit is cleared on every transmission. During
reception, the serial port interrupt and the Receive Interrupt will not happen unless the 9th bit being received
is set. This provides an easy way to have selective reception on a data link. Parity cannot be enabled in this
mode.

The master processor is set to Mode 3 so it always gets
interrupts from serial receptions. The slaves are set in
Mode 2 S0 they only have receive interrupts if the 9th
bit is set. Two types of frames are used: address frames
which have the 9th bit set and data frames which have
the 9th bit cleared. When the master processor wants to
transmit a block of data to one of several slaves, it first
sends out an address frame which identifies the target
slave. Each slave can examine the received byte and see
if it is being addressed. The addressed slave switches to
Mode 3 to receive the coming data frames, while the
slaves that were not addressed stllY in Mode 2 continue
executing.

5-60

80C196KC USER'S GUIDE

for a shorter conversion time. A significant improvement to the AID Converter is the Sample Window and
the Conversion time are programmable in state times.

12.0 AID CONVERTER
Analog Inputs to the 80Cl96KC System are handled
by the AID converter System. As shown in Figure
12-1, the converter system has an 8 channel multiplexer, a sample-and-hold, and a 10-bit successive approximation AID converter. Conversions can be performed
on one of eight channels, the inputs of which share pins
,with port O.

Conversions are started by loading the AD_COMMAND with the channel number, and whether an 8- or
to-bit conversion is performed, as shown in Figure
12-2. The conversion can be started immediately by setting the GO bit to a 1. If the GO bit is set to 0, the
conversion
start when triggered by the HSO. The
reSult and status of the conversion is read in the AD_
RESULT (High) and AD_RESULT (Low) registers,
as shown in Figure 12-3. The AD_RESULT register
can be accessed as a byte or word.

will

The AID converter on the 80C196KC has many improvements over the 8OC196KB converter. The converter can perform either 8- or 10-bit conv,ersions. By
perfotn;ling an 8-bit conversion, resolution is traded off

VREF

8 TO 1
ANALOG
MULTIPLEXER

START
CONVERSION
HSO COMMAND "F"

Figure 12·1. AID Converter Block Diagram

5-61

270704-33

80C196KC USER'S GUIDE

I....R_SV...' I.....R_SV......' I_R_Sv....I_IMO,..DE..
, I..,'
G°r--'--I--'-C.,.H.....
# 1..-......102H

AID CHANNEL
1

o
1

STA,RT NOW
STARTED BY HSO
10-BIT CONVERSION
8-BIT CONVERSION

270704-81

Figure 12-2. AID_COMMAND Register

~1__~~__..L-_M~S~BS__L-~__","-_,~I__L~S~BS__~IR_S_v.IM_O_OE.:I_S~T~1__~C~~_#L-~I02H

"
o

AlOIN USE

"AI D IDLE

LEAST SIGNIFICANT 2 BITS
OF CONVERSION
MOST SIGNIFICANT 8 BITS
OF CONVERSION

270704-82

Figure 12-3. AID_RESULT Register

5·62

80C196KC USER'S GUIDE

Because the 8OCl96KC can run from 3.5 MHz to
16 MHz, it is difficult to optimize both the Sample and
Convert times using only the fast and normal conversion modes on the 8OC196KB. Therefore, an
AD_TIME register in HWINDOW 1 was added so
both the Sample and Convert times could be programmed in number of state times. The fast and normal
conversions are still present to remain compatib~e with
the 8OC196KB. Figure 12-5 shows the AD_TIME
register and the equations for calculating the number of
state times for an AID conversion. IOC2 is shown in
Figure 12-6 which enables the different conversion
times.

Programmable Sample and Convert Times
There are two parameters,that define the time an AID
conversion will take; the Saplple Time plus the Convert
time. The Sample time is the time the analog input
channel. is actually connected to the Sample Capacitor.
If this time is too short, the Sample capacitor will not
charge properly. If the Sample time is too long, the
input may change and errors, occur. The Convert time
is defined to be the length of time to convert one bit of
the analog voltage on the Sample Capacitor to a digital
value. The Convert- time has to be long enough for the
comparator to settle and resolve the voltage, but short
enough so the Sample Capacitor will not discharge and
lose resolution.

270704-84

For 8 and 10 Bit Conversions T = 4 • SAM + B • (CONY
T = Number of States Times
B = Number of Bits (8 or 10)

+ 2.5

80C196KB Compatible Mode TImes
Prescalar On

156.5 States

Prescalar Off

89.5 States

Figure 12·5. AD_TIME Register

5-63

80C196KC USER'S GUIDE

control logic. If an H~O command was used, ,the conversion will begin when Timerl increments. This aids
applications' attempting, to approach spectrally pure
sampling, since successive, samples spaced by _equal
Timerl delays will occur with 'a variance of about ± 50
ns (assuming a stable cl0Ck on XTALl). However, conversions initiated by writing a one to the ADCoN register GO Bit will start within three state times after the
instruction has completed execution resulting in a variance of about 0.38 ,..,s,(XTALI = 16 MHz).

The AID...:-TIME register only prognup.s the speed the
AID can,run, NOT the speed it pan convert correctly.
The 80CI96KC data sheet will contain the correct values for the Sample and Convert times in microseconds.

Restrictions on the AID Converter
I. ,Fo~ an AID conversion, initiali~e the' AID registers
in the following order; AD_TIME, IOC2, and
AD_COMMAND.
2. Do 'not start a conversion using the AD_TIME register when Ii conversion using a 80CI96KB compatible mode is in progress (and VICE-VERSA).
3. Never write zero to the AD_TIME register.

To perform the actual analog-to-digital conversion the
8OC196KC implements a sucoessive approximation algorithm. The converter hlll'dware consists of a 256-rosistor ladder, a comparator, coupling capacitors and Ii
10-bit successive approximation register (SAR) with
logic that guides the process. The resistor ladder provides 20 mV steps (VREF = 5.12V), while capacitive
coupling creates 5 mV steps within the 20 mV ladder
voltages. Therefore, 1024 internal reference voltages are
available for comparison against the analog input to
generate a to-bit conversion result. For an 8-bit conver·
sion, there are 256 levels.

12.1 AID Conversion Process
The conversion process is initiated by the exe~ution of
HSO command OFH, or by writing a one to the GO Bit
in the AID Control Register. Either activity causes a
start conversion signal to be sent to the AID converter

: AID SE<

~~'---'---r-l-.a....-.a....-.a....--, 10C2

---------.~

Figure 12-6., IOC2

5-64

00
,10
Xl

= 80C196KB SLOW MODE
= 80C196KB FAST MODE
= AD_TIME ENABLED

270704-85

inter

80C196KC USER'S GUIDE

A successive approximation conversion is performed by
comparing a sequence of reference voltages, to the analog input, in a binary search for the reference voltage
that most closely matches the input. The 1/. full scale
reference voltage is the first tested. This corresponds to
a lO-bit result where the most significant bit is zero,
and 'all other bits are ones (0111.1111.1lb). If the analog input was less than the test voltage, bit 10 of the
SAR is left a zero, and a new test voltage of '/. full scale
(00 11.1111.11 b) is tried. If this test voltage was lower
than the analog input, bit 9 of the SAR is set and bit 8
is cleared for the next test (0101.l111.1,lb). This binary
searchcontiilUes until 10 or 8 tests have occurred, at'
which time the valid 100bit or 8-bit conversion result
resides in the SAR where it can be read by software.

may degrade converter accurliCY as a result of the internal sample capacitor not being fully charged during the
sample window.
If large source impedances degrade converter accuracy
because the sample capacitor is not charged during the
sample time, an external capacitor connected to the pin
compensates for this degradation. Since the sample capacitor is 2 pF, a 0.005 J.l-F capacitor will charge the
sample capacitor to an aecurate input voltage of
±0.5LSB (2048 * 2 pF). An external capacitor does not
compensate for the voltage drop across the source resistance, but charges the sample capacitor fully during
the sample time.
Placing an external capacitor on each analog input will
also reduce the sensitivity to noise, as the capacitor
combines with series resistance in the external circuit to
form a low-pass filter. In practice, one should include a
small series resistance pridr to the external capacitor on
the analog input pin and choose the largest capacitor
value practical, given the frequency of the signal being
converted. This provides a low-pass filter on the input,
while the resistor will also limit input current during
over-voltage conditi0!ls.

12.2 AID Interface Suggestions
The external interface circuitry to an analog input is
highly dependent upon the application, and can impact
converter characteristics. In the external circuit's design, important factors such as input pin leakage, sample capacitor size and multiplexer series resistance from
the input pin to the sample capacitor must be considered. The following calculation assumes a 1 ,..,S Sample
Window.

Figure 12-S shows a simple analog interface circuit
based upon the discussion above. The circuit in the fig- '
ure also provides limited protection against over-voltage conditions on the analog input. Should the input
voltage inappropriately drop significantly below •
ground, diode D2 will forward bias at about O.S DCY:
This will limit the current sourced by the input pin to
an acceptable amount. However, before any circuit is
used in an actual application, it should~ be thoroughly
analyzed for applicability to the specific problem at
hand.

For the 80C196KC, these factors are idealized in Figure 12-7. The external input circuit must be able to
charge a sample capacitor (Cs) through a series resistance (RI) to an accurate voltage given a D.C. leakage
(IL). On the SOC 196KC, Cs is around 2 pF, RI is
around ± 5 KO and IL is specified as 3 ,..,A maximum.
In determining the necessary source impedance Rs, the
\
value of YBIAS is not important.

VREF
01

-a

FROM USER CIRCUIT>--4...--j,JV'v-.....

ANALOG
INPUT PIN

02
270704-34

ANGNO
270704-35 '

Figure 12-7. Idealized AID Sampling Circuitry

Figure 12-8. Suggested AID Input Circuit

External circuits with source impedances of 1 KO or
less will be able to maintain an input voltage within a
tolerance of about ±0.61 LSB (1.0 KO X 3.0 ,..,A=
3.0 mY) given the D.C. leakage. So~rce impedances
above 2 KO can result in an external error of at least
one LSB due to the voltage drop caused by the 3 ,..,A
leakage. In addition, source impedances above 25 KO

5-65

80C196.KC USER'S GUIDE

ANAlOG REFERENCES

Reference supply levels strongly influence the absolute
accuracy of the conversion. Bypass capacitors should
be used between VREF and ANGND. ANGND should
be wjthin abo.llt a tenth of a volt of Vss. VREF should
be well reMted and used only for the AID converter.
The VREP supply can be between 4.5V.and 5.5V and
needs to. be able to source around 5 rnA. See Section 13
for the minimum hardware connections.
Note that·if only ratiometric information is desired,
VREF can be connected to Vee. In addition, VREP and
ANGND must be connected even if the AID converter
is not being used. Remember that Port 0 receives its
power from the VREP and ANGND pins even when it
is used as digital I/O.

12.3 The AID Transfer Function
The conversion result is .a 'lO-bit ratiometric representation of the input voltage, so the numerical value obtained from the conversion will be:
INT [1023

(VIN - ANGND)/(VREF - ANGNP)I.

This produces a stair-stepped, transfer function when
the output code is plotted versus input voltage (see Figure 12-9). The resulting digital codes can t>e taken as
simple ratio~etric information, or they provide infor.mation . about absolute voltages or relative voltage
changes on the inp~ts. The more demanding the application is on the AID converter, the more important i~
is to fully underst8lld the converter's operation .. For
simple applications, knowing the absolute error of the
converter is sufficient. However, closing a servo-loop
with analog inputs necessitates a detailed understanding of an AID converter's operation and errors.
The errors inherent in an analog-to-digital conversion
process are many: quantizing error, zero offset, fullscale error, differential non~finearity, and non-linearity.
These are "transfer function" errors related to the AID
converter. In addition, converter temperature drift,
Vee rejection, sample-hold feedthrough, multiplexer
off-isolation, channel-to-channel matching and random
noise should be considered. Fortunately, one "Absolute
Error" specification is available which describeS the
sum total of all deviations between the actual conversion process and an ideal converter. However, the various sub-components of error are important in many
applications. These error components are described in
Section 12.5 and in the text below where ideal and actual converters are compared.

An. unavoidable error simply results from the conversion of a continuous voltage to an integer digital representation. This error is called quantizing error, and is
always :to.5 LSB. Quantizing error is the only error
seen in a perfect AID converter, and is. obviously present in actual converters. Figme 12-9 shows the transfer
fUllction for an ideal 3-bit AID converter (i.e. the Ideal
Characteristic).
Note that in Figure 12-9 the Ideal Characteristic possesses unique qualities: .it's first code transition occurs
wb.en the input voltage is 0.5 LSB; it's full-scale code
. transition occurs when the input voltage equals the fullscale reference minus 1.5 LSB; and it's code widths are
all exactly one LSB. These qualities result in a digitization without offset, full-scale or linearity errors. In other words, a perfect conversion.
Figure 12-10 shows an Actual Characteristic of a hypothetical 3-bit converter, which is not perfect. When the
Ideal Characteristic is overlaid 'with the imperfect characteristic, the actual converter is seen to exhibit errors
in the location of the first and final code transitions and
code widths. The deviation of the first code transition
from ideal is called "zero offset", and the 'deviation of
the final code transition from ideal is "full-scale error".
The deviation of the code widths from ideal causes two
types of errors. Differential Non-Linearity and NonLinearity. Differential Non-Linearity is a local linearity
error measurement, whereas Non-Linearity is an overall linearity error measqre. '
Differential Non-Linearity is the degree to which actual
code widths differ from the ideal .one LSB width. It
gives the \lser a measure of how much the input voltage
may' h~ve changed in order to produce a one count
change in the conversion result. Non-Linearity is the
worst case deviation of code transitions from the corresponding code transitions of the Ideal Characteristic.
Non-Linearity describes how much Differential NonLinearities could add up to produce an overall maximunl departure from a linear characteristic. If the
Differential Non-Linearity errors are too large, it is
possible for an AID converter to miss codes or exhibit
non-monotonicity. Neither behavior is desirable ina
closed-loop system. A converter has no missed codes if
there exists for each output code a unique input voltage
range that produces that code only. A converter is
monotonic if every subsequent code change represents
an input'voltage change in the same direction.
I

Differential Non-Linearity anll Non-Linearity are
quantified. by m!l8suring the Terminai.Based Linearity
Errors. A Terminal Based Characteristic results when
. an Actual Characteristic is shifted and rotated to eliminate zero offset and full-scale error (see Figure·12-11).
'The Terminal Based Characteristic is similat to the Ac-

5-66

80C196KC USER'S GUIDE

1---_.

FINAL CODE TRANSITION OCCURS 1
WHEN THE APPLIED VOLTAGE IS
EQUAL TO (Vre! - 1 1/2 (LSB». 1

ACTUAL CHARACTERISTIC OF"
AN IDEAL A/D CONVERTER

a
3

THE VOLTAGE CHANGE
BETWEEN ADJACENT CODE
TRANSITIONS (THE "CODE
WIDTH") IS = 1 LSB.

FIRST CODE TRANSITION OCCURS
....-----1 WHEN THE APPLIED VOLTAGE IS
1
EQUAL TO 1/2 LSB.

O~---L---.----~---.---------r--------~--------r---~----r----r---'---------.

1/2

61/2

INPUT VOLTAGE (LSBs)
270704-36

Figure 12-9. Ideal AID C;:haracteristic
tual Characteristic that would be seen if zero offset and
full-scale error were externally trimmed away. In practice, this is done by using input circuits which include
gain and offset triJhming. In addition, VREF on the
80C196KC could also be closely regulated and
trimmed within the specified range to affect full-scale
error.

Undesired signals come from three main sources. First,
noise on Vee-Vee Rejection. Second, input signal
changes on the channel being converted after the sample window has closed-Feedthrough. Third, signals •
applied to channels not selected by the multiplexerOff-Isolation.
Finally, multiplexer on-channel resistances differ slightly from one channel to the next causing Channel-toChannel Matching errors, and random noise in general
results in Repeatability errors.

Other factors that affect a real A/D Converter system
include sensitivity to temperature, failure to completely
reject all un~anted signals, multiplexer channel dissimilarities and random noise. Fortunately these effects are
small.
Temperature sensitivities are described by the rate at
which typical specifications change with a change in
, temperature.
5-67

IDEAL
CHARACTERISTIC

~
C

--{!U~ ;~~lE ERROR

ABSOLUTE ERROR
ACTUAL
CHARACTERISTIC

.....

~
.....

'f
(l)
CO

8....
CD

0')

"~
(")

III
:::J

::D
(I)

...

6
rn

III

:lIn

.-4
o

I I
1/2

ZERO OFFSET

i i '

INPUT VOLTAGE (lSBs)

61/2

270704-37

(

7
IDEAL FULL-SCALE CODE
TRANSITION

ACTUAL
FULL-SCALE CODE
TRANSITION

ACTUAL
CHARACTERISTIC

"'1'1

c·
c
GJ

TERMINAL BASED
CHARACTERISTIC

...
......

';;}

-__......

PORT PIN
,

270704-39

CHMOS Configuration. pFET 1 is turned on for 2 'osc. periods after Q makes a' O-to-l transition. During th,is time, pFET 1
also turns on pFET 3 through the inverter to form a latch which holds the 1. pFET 2 is alsq on. '

Figure 13-3. CHMOS Quasi-Bidirectional Port Circuit

5-72

80C196KC USER'S GUIDE

Outputting a 0 on a quasi-bidirectional pin turns on the
strong pull-down and turns otT all of the pull-ups.
When a I is output the pull-down is turned otT and 3
pull-ups (strong-PI, weak-P3, very weak-P2) are turned
on. Each·time a pin switches from 0 to I transistor PI
turns on for two oscillator periods. ~2 remains on until
a zero is written to the pin. P3, is used as a latch, so it is
turned on whenever the pin is above the threshold.value
(around 2 volts).
To reduce the amount of current which flows when the
pin is externally pulled low, P3 is turned otT when the
pin voltage drops below the threshold. The current required to pull the pin from a high to a low is at its
maximum just prior to the pull-up turning otT. An external driver can switch these pins easily. The maximum current required occurs at the threshold voltage
and is approximately 700 microamps.

ecutes. The first is that even though Pl.l is being driv~
en high by the 80CI96KC it is possible that it is being
held low externally. This typically happens when the
port pin drives the base of an NPN transistor which in
turn drives whatever there is in the outside world which
needs to be toggled. The base of the transistor will
clamp the port pin to the transistor's Vbe above
ground, typically 0.7V. The 80CI96KC will input this
value as a zero even if a one has been written to the port
pin. When this happens the XORB instruction will always write a one to the port pin's SFR and the pin will
not toggle.
The second problem, which is related to the first, is that
if P1.0 happens to be driven to Ii zero when Port I is
read by the XORB instruction, then the XORB will
write a zero to P1.0 and it will no longer be useable as
an input.
.
The first situation can best be solved by the external
driver design. A series resistor between the port pin and
the base of the transistor often works by bringing up
the voltage present on the port pin. The second case can
be taken care of in the software fairly easily:

When the Port I pins are used as their alternate function, (HOLD, HLDA, BREQ, PWMs), the pins act like
a standard output port.
HARDWARE. CONNECTION HINTS

LDB
XORB
ORB
STB

When using the quasi-bidirectional ports as inputs tied
to switches, series resistors may be needed if the ports
will be written to internally after the part is initialized.
The amount of current sourced to ground from each
pin is typically 7 rnA or more. Therefore, if. all 8 pins
are tied to ground, 56 rnA will be sourced. This is
equivalent to instantaneously doubling the power used
by the chip and may cause noise in some applications.

If a switch is used on a long line connected to a quasibidirectional pin, a pullup resistor is recommended to
reduce the possibility of noise glitches and to decrease
the rise .time of the line. On extremely long lines that
are handling slow signals, a capacitor may be helpful in
addition to the resistor to reduce noise.

In hardware, a IK resistor in series with each pin will
limit current to a reasonable value without impeding
the ability to override the high imped~nce pullup. If all
8 pins are tied together a 120n resistor would be reasonable. The problem is not quite as severe when the
.inputs are tied to electronic devices instead of switches,
as most external pulldowns will not hold 20 rnA to 0.0
volts.

13.3 Output Ports
Output pins include the bus control lines, the HSO
lines, and some of Port 2. These pins can only be used
as outputs as there are no input butTers connected to
them. The output pins are changed before the rising
edge of PHI and is valid some time during PH1. Exter-'
nally, PHI corresponds to CLKOUT low. It isnot pos-'
sible to use immediate logical instructions such as XOR
to toggle these pins.

Writing to a Quasi-Bidirectional Port with electronic
devices attached to the pins requires special attention.
Consider using P 1.0 as an input and trying to toggle
PI. I as an output:

rOPORT1, #OOOOOOOlB

XORB rOPORT1, #OOOOOOlOB

rOPORTl
#OlOB
#OOlB
rOPORTl

This potential problem can be solved in hardware or
software. In software, never write a zero to a pin being
used as an input.

ORB

AL,
AL,
AL,
AL,

Set PLO
for input
Complement
Pl.l

The control outputs and HSO pins have output butTers
with the same output characteristics as those of the bus
pins. Included in the category of control outputs are:
TXD, RXD (in Mode 0), PWM, CLKOUT, ALE,
BHE, RD, and WR. The bus pins have 3 states: output

The first instruction will work as expected but two
problems can occur when the second instruction ex5-73

inter

80C196KC USER'S GUIDE

high,output low, and high impedance. 'Figure 13-4
shows. the internal configuration of an output pin.

13.4 Ports 3 and 41ADO-15
These pins have two functions. They are either bidirection~l ports with open-drain outputs or System Bus
pins which the memory controller uses when it is accessing off-chip memory. If the EA line is low, the pins
always act as the System Bus. Otherwise they act as bus
pins only during a memory access.

Accessing Port 3 and 4 as 1/0 is easily done from internal registers. Since the LD and ST instructions require
the use of internal registers, it may be necessary to first
move the port information into an internal location before utilizing the data. If ·the data is already internal,
the LD is unnecessary. For instance, to write a word
value to P!lrt 3 and 4 ...

LD intreg, portdata

ST intreg, lFFEH

LD intregA,' #OFFFFH

setup port
change mode
pattern

ST intregA, lFFEH

LD intregB, lFFEH

Port 3 and 4 '

When acting as the system bus the pins have strong
drivers to both Vee and Vss. These drivers are used
whenever data is being output on the system bus and
are not used when data is being output by Ports 3 and
4. The pins, external input buffers and pulldowns are
shared between the bus. and the ports. The ports use
different output buffers which are configured as opendrain, and require external pullup resistors. (open-drain
is the MOS version of open-collector.) The port pins
and their system bus functions are shown in Figure
13-5.
.

BUS

ALT.
F'UNCT. ---1"-----1

BUS PORT

RESET

fCN SELECT

Figure 13-4. Output Port

5-74

270704-87

inter

80C196KC USER'S GUIDE

BUS

ADDR
DATA

_-4-_+-___-1

PIN---t---t---t--+------1K"'- 1 - - - - - - - - '
SAMPLE
PORT BUS
BUS PORT
FCN SELECT

RESET
270704-40

Figure

13·5~

Port 3 and 4

Ports 3 and 4 on the 80C196KC are open drain ports.
A diagram of the output buffers cormected to Ports 3
and 4 and the bus pins is shown in Figure 13-5.,

14.1 Power Supply
Power to the 80C196KC flows through 6 pins. Vee
supplies the positive voltage to the digital portion of the
chip while VREF supplies the A/D converter and
Port 0 with a positive voltage. These two pins need'to
be connected to a 5 volt power supply. When using the
A/D converter, it is desirable to connect VREF to a
separate power supply, or at least a separate trace to
minimize the' noise in the A/D converter.

When Ports 3 and 4 are to be used as inputs, they must
first be written with a '1'. This will put the ports in a
high impedance mode. When they are used as outputs,
a pullup resistor must be used externally. A 15K pullup
resistor will source a maximum of 0.33 milliamps, so it
would be a reasonable value to choose if no other circuits with pullups were connected to the, pin,

The four common return pins, VSSl, VSS2, Vss3, and
Angd, must all be nominally at 0 volts. Even if the
A/D converter is not being used, VREF and Angd must
still be connected for PortO to function.

Ports 3 and 4 are, addressed as off-chip memorymapped I/O. The port pins will change state shortly
after the falling edge of CLKOUT. When these pins are
used as Ports 3 and 4 they are open drains, their structure is different when they are used as part of the bus.

14.2 NOise Protection Tips

Port 3 and 4 can be reconstructed as I/O ports from the
Address/Data bus.

Due to the fast rise and fall times of high speed CMOS
logic, noise glitches on the power supply lines and outputs at the chip are not uncommon, The 80C196KC is
no exception. So it is extremely important to follow
good design and board layout techniques to keep noise
to a minimum. Liberal use of deco\lpling· capacitors,
Vee and ground planes, and transient absorbers can all
be of great help. It is much easier to design a board
with these features then to search for random noise on
a poorly designed PC board. For more information on
noise, refer to Applications Note AP-125, 'Designing
Microcontroller Systems for Noisy Environments' in
the Embedded Control Application Handbook.

14.0 MINIMUM HARDWARE
CONSIDERATIONS
The 80C196KC requires several external connections to
operate correctly. Power and ground must be connected, a clock source must be generated, and a reset circuit
must be present. We will look at each of these areas in
detail.

5-75

80C196KC USER'S GUIDE

14.3 Oscillator and Internal Timings
ON-CHIP OSCILLATOR

The on~chip oscillator circuitry for the SOCI96KC, as
shown in Figure 14.1, consists of a crystal"controlled,
positive reactance oscillator. In this application, the
crystal is operated in its fundamental response mode as
an inductive reactance in parallel resonance with capacitance external to the crystal.

.--------1--_

INTERNAL TIMINGS

Internal operation of the chip is based on the oscillator
frequency divided by two, giving the basic time unit,
known as a 'state time'. With a 16 MHz crystal, a state
time is 125 ns. Since the SOCI96KC can operate at
many frequencies, the times given throughout this overview will be in state times.

TO INTERNAL
CIRCUITS

To Intemal
circuitry'
XTAL1
QUARTZ CRYSTAL---i==±'-I
OR CERAMIC
RESONATOR

XTAL2

XTAL1

V-;s
270704-42

Figure 14-2. External Crystal Connections
Vss
270704-41

Figure 14-1. On-chip Oscillator Circuitry
The feedback resistor, Rf, consists of paralleled n-channel' and p-channel FETs controlled by the PD (powerdown) bit. Rf acts as an open when in Powerdown
Mode. Both XTALl and XTAL2 also have ESD protection on the pins which is not shown in, the figure.

To drive the SOCI96KC with an external clock source,
apply the external clock signal to XTALl and let
XTAL2 float. An example of this circuit is shown in
Figure 14,-3. The required voltage levels on XTALI are
specified in the data sheet. The signal on XTALl must
be clean with good solid levels.
.
It is important that the minimum high and low times

are met to avoid having the XTALl pin in the transition range for long periods of time. The longer the
signal is in the transition region, the higher the probability that an external noise glitch could be seen by the
clock generator circuitry. Noise ,glitches on the
SOCI96KC internal clock lines will cause unreliable operation.

The crystal specifications and capacitance values in
Figure 14-2 are not critical. 20 pF is adequate for any
frequency above 1 MHz with good quality crystals. Ceramic resonators can be used instead of a crystal in cost
sensitive applications. For ceramic resonators, the manufacturer should be contacted for values of the capacitors.

DIVIDER CIRCUITRY

Vee

An external oscillator may encounter as much as a
100 pF load at XTALI when it starts-up. This is due to
interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and
VIH specifications the capacitance will not exceed
20 pF.

XTAL2

XTAL2
rLOAT

270704-91

Figure 14-3. External Clock Drive
5-76

80C196KC USER'S GUIDE

Two non-overlapping internal phases are created by the
clock generator: phase 1 and phase 2 as shown in Figure 14-4. CLKOUT is generated'by the rising edge of
phase 1 and phase 2. This is not the same as the
8096BH, which uses a three phase clock. Changing
from a three phase clock to aJwo phase speeds up operation for a set oscillator frequency. Consult the latest
data sheet for AC timing specifications.

14.4 Reset and Reset Status
Reset starts the SOC196KC off in a known state. To
reset the chip, the RESET pin must be held low for at
least 16 state times after the power supply is within
tolerance and the oscillator has stabilized. As soon as
the RESET pin is hel,d low, the 1/0 and control pins
are asynchronously driven to their reset condition.
After the RESET pin is brought high, state reset sequence occurs as shown in Figure 14-5. During this'
time the CCB (Chip Configuration Byte) is read from
location 2018H and stored in the CCR (Chip Configuration Register). The EA (External Access) pin qualifies whether the CCB is read from external or internal
memory. Figure 14-6 gives the reset status of all the
pins and Special Function Registers.

PHASE1~
,

PHASE 2

,,:
r.--\.
'-!----J :
~
,
,

CLKOUT~
270704-43

Figure 14-4. Internal Clock Phases
80C196KC Reset Sequence
INTERNAL - - - ,_ _ _ _ _ _ _ _ _ _ __
RESET
RESET PIN ~m,....----------.,...-CASE I
CLKOUT
CASE II
CLKOUT

ALE----I._____rLRii

------..,ul"-------,L

AID BUS

------C>-Of-----cr
cca
201 BH

Figure 14-5. Reset Sequence

5-77

20BOH

270704-44

80C196KC USER'S GUIDE

Multi~lexed

Pin
Name

Port Pins

Value of the
Pinon Reset

AD_RESULT

Value
7FFOH

RESET

Mid-sized Pull up

AD_TIME

ALE

Weak Pullup

HSI_STATUS

WeakPuliup

S8UF(RX)

8HE

Weak Pullup

INT_MASK

000000008
000000008

OFFH
xOxOxOx08
.. OOH

WeakPuliup

INT_PENDING

INST

Weak Pulldo.wn

TIMER1

Undefined Input •

TIMER2

READY

.Undefined Input •

IOPORT1

NMI

Undefined Input •

IOPORT2

110000018

8USWIDTH

Undefined Input •

000010118

CLKOUT

S1:AT/SP_CON

OOOOH
OOOOH
111111118

CLKOUT

1·IMASK1

System 8us

PS.0-P4.7

Weak Pullups

IPEND1

000000008

ACHO-7

PO.0-PO.7

Undefined Input •

WSR

XXXXOOO08

PORT1

P1.0-P1.7

Weak Pullups

HSI_MODE

111111118

TXD

P2.0

Semi-Weak Pullup

IOC2

XOOOOOO08

RXD

P2.1

Undefined Input •

lOCO

000000X08

EXTINT

P2.2

Undefined Input •

IOC1

001000018

T2CLK

P2.S

Undefined Input •

PWM_CONTROLS

T2RST

P2.4

Undefined Input •

10PORTS

PWM

P2.5

Semi-Weak Pulldown

IOPORT4

111111118

P2.6-P2.7

Weak Pullups

10SO

000000008

OOH
111111118

HSI0-HSI1

Undefined Input'

IOS1

000000008

HSI2/HS04

Undefined Input •

IOS2

000000008

HSIS/HS05

Undefined Input •

10CS"

111100108

HSOO-HSOS

Weak Pulldown
,

NOTES:
'These pins must be driven and not left floating.
"'Was previously called T2CONTROL or T2CNTC.

Figure 14-6. Chip Reset Status

5-78

inter

80C196KC USER'S GUIDE

Figure 14-7 shows what the RESET pin looks like internally. The RESET pin functions as an input and as
an output to reset an entire system with a watchdog
timer overflow; or by executing a RST instruction. For
a system reset application, the reset circuit should be a
one-shot with an open collector output. The reset pulse
may have to be lengthened and buffered since RESET
is only asserted for 16 state times. A capacitor cannot
be connected directly to RESET if it is to drive the reset
pins of other chips in the circuit. The capacitor may
keep 'the voltage on the pin from going below guaranteed VIL for circuits connected to the RESET pin. Figure 14-8 shows an example of a system reset circuit.

WATCHDOG TIMER

There are three ways in which the 80Cl96KC can reset
itself. The watchdog timer will reset the 80C 196KC if it
is not cleared in 64K state times. The watchdog timer is
enabled the first time it is cleared. To clear the watchdog, write a 'IE' followed immediately by an 'EI' to
location OAH. Once enabled, the watchdog can only be
disabled by a reset and on the 80C196KC. '
RST INSTRUCTION

Executing a RST instruction will also reset the
80C196KC. The opcode for the RST instruction is
OFFH. By putting pullups on the Addr/data'bus, unimplemented areas of memory will read OFFH and cause
,the 80Cl96KC to be reset.

14.5 Minimum Hardware Connections
Figure 14-9 shows the minimum connections needed to
get the 80C196KC up and running. It is important to
tie all unused inputs to Vee or Vss. If these pins are
left floating, they can float to a mid voltage level and
draw excessive current. Some pins such as NMI or
EXTINT may generate spurious interrupts if left unconnected.

RESET CIRCUITS

The simplest way to reset an 80C196KC is to insert a
capacitor between the RESET pin and Vss. The
80Cl96KC has an internal pullup. A 5 uF or greater
capacitor should provide sufficient reset time as' long as
Vee rises quickly.
'

Vce

RESET
PIN

80C196KC CHIP
RESET

WATCHDOG TIMER
OVERFLOW
RESET INSTRUCTION
(OFFH)

270704-45

Figure 14·7. Reset Pin

5-79

80C196KC USER'S GUIDE

80C196KC
RESET

Vee

1-.....-1

OTHER
CIRCUITRY

OPTIONAL
ONE-SHOT
74AC123

lOOK

l .0 J.l.F'

270704-46

NOTE:
1. The diode will provide a faster eycle time repetitive power-on,-resets.

Figure 14-8. System Reset Circuit

+5V

+5V
VREF

Vee

lJ.1.F'

lJ.1.F'
ANGND

V SS1

VSS2
VSS3

+5V

BUSWIDTH
READY
5 J.l.F

.::r:.

RESET
BUS
CONTROL
RXD
EXTINT
T2CLK
T2RST
HSI.O - HSI.3
NMI

ADO-AD15
PO.O - PO.7

BOC196KC
270704-47

NOTE:
'Inputs must be driven high or low.

"Figure 14-9. 80C196KC Minimum Hardware Connections

5-80

inter

80C196KC USER'S GUIDE

Ports 3 and 4 will retain the value present in their data
latches if being used as I/O ports. If these ports are the
ADDR/DATA bus, the pins will float.

15.0 SPECIAL MODES OF
OPERATION
The 80C196KC has Idle and Powerdown Modes to reduce the amount of current consumed by the chip. The
80C196KC also has an ONCE (ON-Circuit-Emulation)
Mode to isolate itself from the rest of the components
in the system.

It is important to note the Watchdog Timer continues

to run in the Idle Mode if it is enabled. So the chip
must be awakened every 64K state times to clear the
Watchdog or the chip will reset.

15.1 Idle Mode

15.2 Powerctown Mode

The Idle Mode is entered by executing the instruction
'IDLPD # 1'. In the Idle Mode, the CPU stops executing. The CPU clocks are frozen at logic state zero, but
the peripheral clocks and CLKOUT continue to be active. Power consumption in the Idle Mode is reduced to
'
about 40% of the active Mode.

The Powerdown Mode is entered by executing the instruction, 'IDLPD #2'. In the Powerdown Mode, all
internal clocks are frozen at logic state zero and the
oscillator is shut off. All 232 bytes of registers plus the
256 bytes of extra RAM and most peripherals hold
their values if Vee is maintained. Power is reduced to
the device leakage and is in the uA range.

The CPU exits the Idle Mode by any enabled interrupt
source or a hardware reset. Since all of the peripherals
are running, the interrupt can be generated by the HSI,
HSO, AID, serial port, etc. When an interrupt brings
the CPU out of the Idle Mode, the CPU vectors to the
corresponding interrupt service routine and begins executing. The CPU returns from the interrupt service
routine to the next instruction following the 'IDLPD
# l' instruction that. put the CPU in the Idle Mode.

In Powerdown, the bus control pins go to their inactive
states. All of the output pins will assume the value in
their data latches. Ports 3 and 4 will continue to act as
ports in the single chip mode or will float if ·acting as
the ADDR/DATA bus.
To prevent accidental entry into the Powerdown Mode,
this feature may be disabled at reset by clearing bit 0 of
the CCR (Chip Configuration Register). Since the default value of the CCR bit 0 is I, the Powerdown Mode
is normally enabled.

A PTS cycle also causes the CPU to exit the IDLE
mode. The CPU begins executing the instruction following the "IDLE # 1" instruction that put the device
into IDLE mode.

The Powerdown Mode can be exited by a chip reset or
a high level on the external interrupt pin. If the RESET
pin is used, it must be asserted long enough for the
oscillator to stabilize.

In the Idle Mode, the system bus control pins (ALE,
RD, WR, INST, and BHE), go to their inactive states.

XTALI

CLKOUT

.,
PHI

INTERNAL'
'---i-"';"--o-!I ~------""';--+--i
POWERDOWN :
SIGNAL ~i_...,._...,._....;_....;~....J.

--i--.;.-.....;~....;.-....;..-~'1r-flL....---"";"-";"'-+--';'-"""';

EXTINT ;.:-...;..-.....

Vpp :

-------..;.--..;.--.;...---~I~

TIMEOUT .:

270704.,.48

Figure 15-1. Power Up and Power Down Sequence
5-81

inter

80C196KC USER'S GUIDE

When exiting Powerdown with an external interrupt, a
positive level on the pin mapped to INT7 (either
EXTINT or portO. 7) will bring the chip out of Power·
down Mode. The interrupt does not have to be un·
masked to exit Powerdown. An interll'al timing circuit
ensures that the oscillator hils time to stabilize before
turning on the internal clocks. Figure 15·1 shows the
power down and power up sequence using an external
interrupt.
During normal operation, before entering Powerdown
Mode, the Vpp pin will rise to Vee through an internal
pullup. The user must connect a capacitor between Vpp
and VS8. A positive level on the external interrupt pin
starts to discharge this capacitor. The internal current
source that discharges the capacitor can sink approxi·
mately 100 uA. When the voltage goes below about 1
volt on the Vpp pin, the chip begins executing code. A
1uF capacitor would take about 4 ms to discharge to 1
volt.
If the external interrupt brings the chip out of Power·
down, the corresponding bit will be set in the interrupt
pending register. If the interrupt is unmasked, the. de·
vice will immediately execute the interrupt service rou·
tine, and return to the instruction following the IDLPD
instruction that put the chip into Powerdown. If the
interrupt is masked, the chip will start at the instruc·
tion following the IDLPD instruction. The bit in the
pending register will remain set, however.

at a logical 1 during reset. Exter!).al circuitry' must \lot
pull the pin low or the ONCE mode will be entered. All
pins except XTALI and XTAL2arefloated. Some of
the pins are not truly high impedance as they have
weak pullups or pulldowns. The ON<;E Mode is useful
in electrically removing the 8OC196KC from the rest of
the system. A typical application of the ONCE Mode
would be to program discrete EPROMs onboard with·
out removing the 80Cl96KC from its socket.

16.0 EXTERNAL MEMORY
INTERFACING
16.1 Bus Operation
There are several different external operating modes on
the 80C196KC. The standard bus mode uses a 16 bit
multiplexed address/data bus. Other bus modes include
an 8 bit extetnal bus mode and a mode in which'the bus
size can be dynamically switched between 8·bits and
16·bits. In addition, there are several options available
on the type of bus control signals which make an exter·
nal bus simple to design.
In the standard mode, external memory is addressed
through lines ADO·ADI5 which form a 16 bit multi·
plexed bus. The address/data bus shares pins with ports
3 and 4. Figure 16·1 shows an idealized timing diagram
for the external bus signals.

All peripherals should be in an inactive state before
entering Powerdown. If the AID converter is in the
middle of a conversion, iris aborted. If the chip comes
out of Powerdown by an external interrupt, the serial
port will continue where it left off. Make sure that the
serial port is done transmitting or receiving before en·
tering Powerdown. The SFRs associated with the A/D
and the serial port may also contain incorrect informa·
tion when returning from Powerdown.
When the chip is in Powerdown, it is impossible for the
watchdog timer to time out because its clock has
stopped. Systems which must use the Watchdog and
Powerdown, should clear the Watchdog right before
entering Powerdown. This will keep the Watchdog
from timing out when the oscillator is stabilizing after
leaving Powerdown.

15.3 ONCETM and Test Modes
Test Modes can be entered on the 80C196KC by hold·
ing ALE,WR, HLDA or RD in their active state on the
rising edge of RESET. For this reason the IOL and IOH
in Reset Specifications must be carefully verified. The
only Test Mode not reserved for use by Intel is the
ONCE, or ON·Circuit·Emulation Mode.

Address Latch Enable (ALE) provides a strobe to
transparent latches (74AC373s) to demultiplex the bus.
To avoid confusion, the latched address signals will be
called MAO·MAIS and the data signals will be named
MDO·MDI5.
The data returned from external memory must be on
the bus and stable for a specified setup time before the
rising edge of RD (read). The rising edge of RD signals
the end of the sampling window. Writing to external
memory is controlled with the WR (write) pin, Data is
valid on MDO-MDlS, ~m the rising edge of WR. At
this time data must be latched by the external system.
The 80C196KB has ample setup and hold times for
writes.
When BHE is asserted, the memory connected to the
high byte of the data bus is selected. When MAO is a 0,
.the memory connected to the low byte of the data bus is
selected. In this way accesses to a 16·bit wide memory
can be to the low (even) byte only (MAO =0, BHE= I),
to the high (odd) byte only (MAO = 1, BHE = 0), or the
both bytes (MAO = 0, BHE = AD).
When a block of memory is decoded for reads only, the
system does not have to decode BHE and MAO. The
80C196KB will discard the byte it does not need. For
systems that write to external memory, a system must
generate separate write strobes to both the high and low
byte o(memory, This is discussed in more detail later.

ONCE is entered by driving TXD pin low on the rising
edge of RESET. The TXD pin will source about 1 rnA

5·82

80C196KC USER'S GUIDE

XTAL1

CLKOUT

ALE

J\""'-________

READY

BUS WIDTH

BUS

ADDRESS OUT

)

(

OUT

»)

READ------------~~

WRITE ---------"'\~

270704-49

Figure 16·1. Ideaiized Bus Timings
All of the external bus signals are gated by the rising
and falling edges of CLKOUT. A zero waitstate bus
cycle consists of two CLKOUT periods. Therefore,
there are 4 clock edges that generate a complete bus
cycle. The first falling edge of CLKOUT asserts ALE
and drives an address on the bus: The rising edge of
CLKOUT drives ALE inactive. The next falling edge
of CLKOUT asserts RD (read) and floats the bus for a
read cycle. During a WR (write) cycle; this edge asserts
WR and drives valid data onthe bus. 'On the last rising
edge of CLKOUT, data is latched into the 80C196KB
for a read cycle, or data is valid for a write cycle.

The CCR is shown in Figure 16-2.
Bits 7 and 6 of the CCR contra! ROM/EPROM protection. ROM/EPROM protection is covered in Section 17. The next two bits control the internal READY
mode. The three next bits determine the. bus control
signals. The next bit enables or disables the Powerdown
Mode.

CHIP CONFIGURATION REGISTER
ENABLE POWER DOWN FEATURE

16.2 Chip Configuration Register

BUS WIDTH SELECT
. (16-8IT BUS/""8--B""IT""'B"'"U"'S)

The CCR (Chip Configuration Register) is the first
byte fetched from memory following a chip reset. The
CCR is fetched from the CCB (Chip Configuration
Byte) at location 2018H in either internal or external
memory depending on the EA pin. The CCR is only
loaded once during the reset sequence. Once loaded, the
CCR cannot be changed until the next reset. During
CCB fetch, strong drivers are active on AD8-AD15
only during the address portion of the cycle. Weak
drivers are applied during the read portion of the cycle
to avoid bus contention in 16-bit systems. Pull up resistors should not be installed on AD8-ADI5 in 8-bit
systems.

WRITE STROBE MODE SELECT
(WR AND BHE/WRL AND WRH)
L----ADDRESS VALID STROBE SELECT
(ALE/ADV)
(IRCO) } INTERNAL READY
.....- - - - ( I R C 1 )

CONTROL MODE

(LOCO) )PROGRAM LOCK
.....- - - - - - ( L O C 1 ) MODE
2~0704-50

Figure 16·2. Chip Configuration Register

5-83

80C196KC USER'S GUIDE

READY control
The uSer has two options for ready control. He can use
the READY pin and/or the internal ready control bits.
Ready control is only valid for external memory. Onchip RAM/SFR space and on-chip ROM/EPROM is
always accessed with 0 waitstates. The modes are chosen by bits 4 and 5 of the CCR and are shown in Figure
16-3.

IRC1

IRCO

Description

0
0

1
1

Limit to one waitstate
Limit to two waitstates
Limit to three waitstates
Wait states not limited internally

1
1

Figure 16-3. Ready Control Modes
The internal ready control logic limits the number of
waitstates that slow devices can insert into the bus cycle. When the READY pin is pulled low, waitstates are
inse~ted into the bus cycle until the READY pin goes
high, or the number of waitstate equal the number programmed into the CCR. So the ready control is a logicalOR between the READY pin and the internal ready
control.

Bus' control
Using .the CCR, the 80CI96KC can generate several
types of control signals designed to reduce external
hardware. The ALE, WR, and BHE pins serve dual
functions. Bits 2 and 3 of the CCR specify the function
performed by these control lines.

Standard bus control
If CCR bits 2 and 3 are Is, the standard bus control
signals ALE, WR, and BHE are generated as shown in
Figure .16-4. ALE rises as the address starts to be driven, and falls to externally latch the address. WR is driven for every write. BHE and MAO can be combined to
fO.rm WRL and WRH for even and odd byte writes.

ALE.Jl

ALE J l , , - '_ _

WRiTE

BHE

ADO'. 15 1

This feature gives very simple and flexible. ready control. For example, every slow memory chip select line
could be ORed together and connected to the READY:
pin with Internal Ready Control programmed to insert
the desired number of waitstates into the. bus cycle.

ADO-71

VALID

ADDR

·1

DATA OUT

AD8 -15

ADDR LOW

DATA OUT

~..._ _ _A_D_D_RE_S_S_H_IG_H_ _ _...

2,70704-51

270704-.52

16-BII Bus Cycle

8-BII Bus Cycle

Figure 16-4. Standard Bus Control

5-84

infef

80C196KC USER'S GUIDE

BHE

----

____ ________-Jr~

Figure 16-14. AC Timing Diagrams

5-90

270704-64

inter

80C196KC USER'S GUIDE

- CLKOUT Low to Input Data Valid:
Maximum time the memory system has
to output valid data after the CLKOUT
falls.
- RD High to Input Data Float: Time after RD is inactive until the memory system must float the bus. If this timing is
not met, bus contention will occur.
Data
Hold after RD Inactive: Time after
TRXDX
RD is inactive that the memory system
must hold Data on the bus. Always 0 ns
On the 80C196KC.
TCLDY

TIMINGS THE MEMORY SYSTEM MUST MEET:

TAYYY - ADDRESS Valid tl> READY Setup:
Maximum time the memory system has
to decode READY after ADDRESS is
output by the 80C196KC to guarantee
at least one-wait ",tate will occur.
TLLYY - ALE Low to READY Setup: Maximum
time the memory system has to decode
READY after ALE faUs to guarantee at
least one wait state will occur.
TYLYH -READY Low to READY HIGH:
Maximum amount of nonREADY time
or the maximum number of wait states
that can be inserted into a bus cycle.
Since the 80C196KC is a completely
static part, T YLYH is unbounded.
TCLYX - READY Hold after CLKOUT Low:
Minimum time the level on the READY
pin must be valid after CLKOUT falls.
The minimum hold time is always 0 ns.
If maximum value is exceeded, addition. al wait states will occur.
T LL YX - READY Hold AFI'ER ALE Low:
Minimum time the level on the READY
pin must be valid after ALE falls. If
maximum value is exceeded, additional
wait states will occur.
TAYGY - ADDRESS Valid to BUSWIDTH Valid: Maximum time the memory system
has to decode BUSWIDTH after ADDRESS is output by the 80C196KC. If
exceeded, it 1S not guaranteed the
80C196KC will respond with an 8- or
16-bit bus cycle.
- ALE Low to BUSWIDTH Valid:
Maximum time after ALE/ ADV falls
until BUSWIDTH must be valid. If exceeded, it is not guaranteed the
80C196KC will respond with an 8- or
16-bit bus cycle.
TCLGX - BUSWIDTH Hold after CLKOUT
Low: Minimum time BUSWIDTH must
be held valid after CLKOUT falls. Always 0 ns of the 80C196KC.
TAYDY - ADDRESS Valid to Input Data Valid:
Maximum time the memory system has
to output valid data after the 80Cl96KC
outputs a valid address.
- RD Low to Input Data Valid: Maximum
time the memory system has to output
valid data after the 80C196KC asserts
RD.

TIMINGS THE 80C196KC WILL PROVIDE:

FXTAL

- Frequency on XTALl: Frequency ofsignal input into the 80C196KC. The
80CI96KC runs internally at '/2 FXTAL.
T0SC
- l/FXTAL: All A.C. Timings are referenced to T OSC.
TXHCH - XTALl High to CLKOUT High or
Low: Needed in systems where the signal driving XTALl is also a clock for
external devices.
T CLCL - CLKOUT Cycle Time: Nominally 2

Tosc·
T CHCL

TCLLH

- CLKOUT High Period: Needed in systems which use CLKOUT as clock for
external devices.
- CLKOUT Falling Edge to ALE/ADV
Rising: A help in deriving other timings.
- ALE/ ADV Falling Edge to CLKOUT
Rising: A help in deriving other timings.
- ALE Cycle Time: Time between ALE
pulses.
- ALE/ADV High Period: Useful in determining ALE/ ADV rising edge to
ADDRESS valid. External latches must
also meet this spec.
- ADDRESS Setup to ALE/ADV Falling
Edge: Length of time ADDRESS is valid before ALE/ ADV falls. External
latches must meet this spec.
- ADDRESS Hold after ALE! ADV Falling Edge: Length of Time ADDRESS is
valid after ALE! ADV falls. External
latches must meet this spec.
-- ALE!ADV Low to RD Low: Len~ of
time after ALE! ADV falls before RD is
asserted. Could be needed to insure
proper memory decoding takes place before a device is enabled.

Figure 16·15. AC Timing Explanations

5-91

80C196KC USER'S GUIDE

TCHWH

~; ,

CLKOUT High to WR Rising Edge:
Time between CLKOUT going high and
WR going inactive. Useful in systems
based on CLKOUT.
TWLWH- WR Low to WR High: WR pulse width.
.
Memory devices must meet this spec.

TRt,CL

- RD Low to CLKOUT Falling Edge:
Length of time from RD asserted to
CLKOUT falling edge: Useful for systems based on CLKOUT.
TRLRH - RD Low to RD High: RD pulse width.
- RD High to ALE/ADV Asserted: Time
between RD going inactive and next
ALE/ADV, also used to calculate time
between inactive and next ADDRESS
valid.
TRLAZ - RD Low to ADDRESS Float: Used to
calculate when the 80Cl96KC stops
driving ADDRESS on the bus.
- ALE/ADV Low Edge to WR Low:
Length of time ALE/ADV falls before
WR is asserted. Could be needed to ensure proper memory decoding takes
place before a device is enabled.
TCLWL - CLKOUT Falling Edge to WR Low:
Time between CLKOUT going low and
WR being asserted. Useful in systems
based on CLKOUT.
- Data Valid to WR Rising Edge: Time
between data being valid on the bus and
WR going inactive. Memory devices
must meet this spec.

TWHQX - Data Hold after WR Rising Edge:
Amount of time data is valid on the bus
after WR gofng inactiv~. Memory devices must .meet this spec.
TWHLH - WR Rising Edge to ALE/ADV Rising
Edge: Time between WR going inactive
and next ALE/ADV. Also used to calculate WR inactive and next ADDRESS
valid.
TWHBX - BHE, INST, Hold after WR Rising
Edge: Minimum time these signals will
be valid after WR inactive.
- BHE, INST, Hold after RD Rising
Edge: Minimum time these signals will
be valid af~er RD inactive.
.
Hold
after
WR
Rising
Edge:
ADS·IS
TWHAX
Minimum time the high byte of the address in 8-bit mode will be valid after
WR inactive.
TRHAX - ADS-IS Hold after RD Rising Edge:
Minimum time the high byte of the address in 8-bit mode will be valid after
RD inactive.

Figure 16·15. AC Timing Explanations (Continued)

RD
AD8-15

80C196KC
ADO-.7

ADV

HIGH ADDRESS

DATA
~

EPROM

74AC
373

LOW ADDRESS

T-\
\
OPTIONAL IF

LATCHED EPROM
IS USED

Figure 16·16. 8·Bit System with EPROM

5-92

270704-65

intJ

80C196KC USER'S GUIDE

Figure 16-18 shows a 16 bit system with 2 EPROMs.
Again, ADV is used to chip select the memory. Figure
16-19 shows a system with dynamic bus width. Code is
executed from the two EPROMs and data is stored in
the single RAM. Note the Chip Select of the RAM also
is input to the BUSWIDTH pin to select an eight bit
cycle.

16.6 Memory System Examples
External memory systems for the 80C196KC can be set
up inmany different ways. Figure 16-16 shows a simple
8 bit system with a single EPROM. The ADV Mode
can be selected to provide a chip select to the memory.
By setting bit CCR.l to 0, the system is locked into the
eight bit mode. An' eight bit system with EPROM and
RAM is shown in Figure 16-17. The EPROM is decoded in the lower half of memory, and the RAM in the
upper half.
'

AD15
AD8-15

_ _...._ _..

HIGH ADDRESS

. ._ _ _..... DATA

80C196KC
ADO-7!-__.j

ADV

DATA

, EPROM

RAM

LOW ADDRESS

1-----1

RD I---------~-----~
WR
270704-66

Figure 16-17. 8-Bit System with EPROM and RAM

Cs
AD8-15

HIGH ADDRESS

EPROM
DATA

ADO-7

LOW ADDRESS

80C196KC
RD ~------~~----~
270704-67

Figure 16-18. 16-Bit System with EPROM

5-93

intJ

80C196KC USER'S GUIDE

RAM

EPROM
ADV

r~~~::JDATA
LOW ADDRESS

80C196KC

~ ~------------~~----------~------------~
WR

~--------------------------------------------~
270704-68

Figure 16-19. 16-Bit System with Dynamic Buswidth

WRL-----C(

MDO-MD7--------4---~~~

WRH----t~

8
MD&-MD'5--------~--~~~

~-----~

74HCT
~

(x, .....,

__------------L--J

74HCT
05

(X, .....)

INPUT

cr,Jo-______________--,

ADDR = P3, P4 - - - -....

RD ------aL~
ADO-AD7

AD8-AD1S

270704-69

Figure 16-20.1/0 Port Reconstruction

5-94

inter

80C196KC USER'S GUIDE

Three flexible EPROM programming modes are available on the '87CI96KC; Auto, Slave, and Run-time.
These modes can program the 87C196KC in a stand
alone or run-time environment.

16.7 1/0 Port Reconstruction
When a single-chip system is being designed using a
multiple chip system as a prototype, it may be necessary to reconstruct I/O Ports 3 and 4 using a memory
mapped I/O technique. The circuit to reconstruct the
Ports is shown in Figure ,16-20. It can be attached to a
80C196KC system which has the required address decoding and bus demultiplexing.

For ROM parts, a ROM dump mode allows the ROM
contents to be verified by the user.

17.1 Programming the 87C196KC
The output circuitry is a latch that operates, when
IFFEH or IFFFH are placed on the MA lines. The
inverters surrounding the latch create an open-collector
output to emulate the open-drain output found on the
80C196KC. The RESET line sets the ports to all Is
when the chip is reset. The voltage and current specifications of the port will be different from the
80C196KC, but the functionality will be the same.

The EPROM is ~ped into mem.ory locations
2000H-SFFF.!!.. if EA is at logical 1. By applying
+ 12.S0V to EA when RESET is asserted places the
87C196KC in Programming M.ode. The Programming
Mode supports programming and verification of
87C196KC EPROMs.
The Auto Programming Mode enables an 87C196KC
to program itself with the 16K bytes of code beginning
at address 4000H on its external bus. The Slave Mode
provides a standard interface for an EPROM programmer. The Run-time Mode allows individual EPROM
locations to be programmed at run-time under complete software control.

The input circuitry is a bus transceiver that is addressed
at IFFEH and IFFFH. If the ports are going to be
either inputs or outputs, but not both, some of the circuitry can be eliminated.

17.0 USING ROM AND EPROM
PARTS

In the Programming Mode, some I/O pins have new
functions. These new pin functions determine and support the different programming modes. Figure 17-1
shows how the pins are renamed and Figure 17-2 describes in detail each new pin function.

The 87C196KC contains 16K bytes of ultraviolet Erasable and Electrically Programmable Read Only Memory (EPROM). The 83C196KC contains 16K bytes .of
Read Qnly Memory (ROM).

SELEC
TSL
PROGRAMM ING
_
MO DE
EA
PC.7
PC.6
~DE
-y PC.S
PC.4

t PROGRAMMING VOLTAGE
VPP

...

PORT 4 ADDRESS
PORT 3 'I
P2.7

87C196KC

COMMAND DATA PATH
-y
PACT

P2.1

PALE

P2.2

PROG

P2.C

PVER

P2.4

AINC

P2.6

CPVER
270704-70

Figure 17·1. Programming Mode Pin Functions

5-95

inter

80C196KC USER'S GUIDE

N~me

Function

PMODE

Programming Input Mode Select. Determines the EPROM programming algorithm that is
performed. PMODE is sampled after a chip reset and should be static while the part is
operating.

PALE

Programming ALE Input. Accepted by an 87C196KC that is in Slave Programming Mode.
Used to indicate that Ports 3 and 4 contain a command/ address.

PROG

Programming Input. Falling edge indicates valid data on PBUS and the beginning of
programming. Rising edge indicates end of programming.

PACT

Programming Active. Output indicates when programming activity is complete.

PVER

Program Verification. Output signal is low after rising edge of PROG if the programming was
not successful.

AINC·

Auto Increment. Active low input Signal indicates that the auto increment mode is enabled.
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.

PORTS

Address/Command/Data Bus. Used to pass commands, addresses and data to and from
87C196KCs. Also used in the Auto Programming Mode as a regular system bus to access
external memory.

CPVER

Cummulative Program Output Verification. Pin is high if all locations since entering a
programming mode have programmed correctly.

Figure 17-2. Programming Mode Pin Definitions
While in Programming Mode, the PMODE value selects the programming function (see Figure 17-3). Runtime programming can be done at any time during normal execution.

PM ODE

Programming Mode

ming Chip Configuration Byte). The PCCB is a separate EPROM location that is not mapped I:Inder normal
operation. PCCB has implications in some of the programming modes, and also for the memory protection
options, discussed hit'er. Therefore, the PCCB must correctly correspond to the memory system in the programming setup, which is not necessarily the memory
system of the application.

0-4

Reserved

Slave Programming

ROM Dump

7-8

Reserve~

UPROM Programming

17.2 Auto Programming Mode

OAH-OBH

Reserved

OCH

Auto programming

ODH

PCCB Programming

The Auto Programming Mode allows an 87C196KC
EPROM to be programmed without a special EPROM
programmer. In this mode, the 87C196KC simply programs itself with the data found at external locations
4000H - 7FFFH. Figure 17-4 shows a minimum configurationusing an 16K X 8 EPROM to program an
87C196KC in the Auto Programming Mode.

OEH-OFH

Reserved

Figure 17-3. Programming
Function Pmode.Values

The following sections describe the 87C196KC programming modes in detail.

To guarantee proper functionality, the pins of PMODE
must be in their desired state before RESET rises. Once
the part is reset, it should not be ,switched to another
mode without a new reset sequence.

To start the Auto Programming Mode, PACT is asserted and the word at external location 4014H is read to
determine the programming pulse width. This allows
Auto Programming to be done at several different .frequencies. The formula for calculating the pulse width
is:

When EA selects the Programming Mode, the chip reset sequence loads the CCR from the PCCB (Program-

Pulse Width = XTAL1/t,600,OOO - t

5·96

inter

80C196KC USER'S GUIDE

The MSB of this word also must be set. For example,
with a 10 MHz Clock, the word at 4014H should be
loaded with 8005H for .the correct pulse width. For
8 MHz It is 8004H and for 6 MHz it is 8003H.·

PCCS Programming Mode

The PCCB (Programming Chip Configuration Byte)
can be treated just like any other EPROM location.
When in the Slave Programming Mode, the PCCB can
be programmed at location 2018H. .Butthe PCCB Programming Mode is a simple way to program the PCCB
when no other locations need be programmed. Figure
17-5 shows a block diagram for using the PCCB Programming Mode:

The 87CI96KC then reads a word from external memory, and the Modified Quick-Pulse Programming Algorithm (described later) programs the corresponding
EPROM location. Since the erased state of a byte is
OFFH,~ the Auto Programming Mode skips locations
containing OFFH. PVER will go low anytime there is a
programming error. When all 16K have been programmed, PACT goes high.

WithPMODE' = ODH and OFFH on Port 4, the
PCCB will be programmed with the data on Port 3
when a 0 is placed ,on PALE. Afterprograri1ihing is
complete, PVER is driven high if the PCCB was programmed correctly, and low if the programming failed.
PALE can be pulsed to repeat programming.

In the Auto Programming Mode, CCR is loaded with
the PCCB. The PCCB must correspond to the memory
system of the programming setup, which is not necessarily the same as the memory system of the actual
application.
Vpp and EA must be kept noise-free and must never go
above 12.7SV at any time. Do not put pull up resistors
on AD8-AD1S.

A15

+5V

lOOK

100}-"

~------------~~--~OE

1--------=---1 A8-A13

HAC
373
G

AO-A7
27C128

_ _ _ _ _~-iDO-D7
+5V

+5V

87C196KC
270704-71

-Inputs must be driven high or low.

Figure 17-4. Auto Programming Mode

5-97

inter

80C196KC USER'S GUIDE

In this mode, the 87CI96KC programs like'a simple
EPROM device. The 87CI96KC responds to two different commands while in this mode: data program,
and word dump. These commands, along w.ith the
transfer of appropriate data and addresses are selected
using Ports 3 and 4 and five other pins for handshaking. The least significant bit selects a Data Program or
Word Dump and the upper 15 bits contain the address
to be programmed or dumped. The address ranges from
2000H-5FFFH and refers to internal EPROM space.

+12.50V

Vce

vpp

pO.1

po.s
PO.5

nn.",...-. Vcc

1'0.4

87C19SKC
Data Program Command

PALEI-.....W .....

A Data Program Command is illustrated in Figure
17-6. The data program command is selected by setting
the LSB of the address to a I. For example, an address
of 350lH would program the word location at 3500H.
Asserting PALE latches the command and address to
be programmed from Ports 3 and 4. PROG also asserts
to latch the data. The width of the PROG pulse determines the length of the programming pulse.

270704-72

NOTES:

Tie Port 3 to the value desired to be programmed into

peGs.

Make all necessary minimum connections for power,
ground and clock.

After the rising edge' of PROG, the 87C196KC automatically performs a verification of the address just
programmed. PVER is asserted if the location programmed correctly. This gives verification information
t6 programmers which can not use the Word Dump
Command. CPVER is a cummulative program verify
that will remain low if a location did not verify correctly. The AINC pin can optionally be toggled in order to
increment to the next location or a new Data Program
Command can be issued.

Figure 17-5. The PCCB Programming Mode

17.3 Slave Programming Mode
A 87C196KC can be programmed by a master programmer through the Slave Programming Mode.

PORTS
3/4 «AOOR/COMMANO:>

PALE

PROG

AINC

PVER

I
\

U
0
Figure 17~6. Data Program Command

270704-73

intJ

80C196KC USER'S GUIDE

Figure 17.-6 shows the relationship of PALE, PROG,
PVER, AINC and CPVER to the Command/Data
path on Ports 3 and 4 for the Data Program Command.

17.4 Run-Time Programming
In Run-Time Programming, the user can program an
EPROM location during the normal execution of code.
Ifhe only additional requirement of Run-Time Programming is programming voltage is ~lied Vpp.
Run-Time Programming is done with EA at a TTL
high.

Word Dump Command
When the Word Dump Command is issued, the
87C196KC places the value at the requested address on
Ports 3 and 4. A Word Dump command is selected by a
o on Port pin 3.0. For example, sending the command
2100H to a slave results in the slave placing the word at
internal address 2100H on Ports 3 aIid 4. PROG governs when the 87C196KC drives the bus. The Timings
are shown in Figure 17-7. In the Word Dump mode,
the AINC pin can remain active and toggling. The
PROG pin will automatically increment the address.

To Run-Time Program. the user writes to the location
to be programmed. Figure 17-8 is the recommended
code seqll,ence for Run-Time Programming. The
EPROM cannot be accessed during Run-Time Programming. Therefore, the part must enter the IDLE
mode immediately after writing to the EPROM or begin executing immediately from external memory. The
Modified Quick Pulse algorithm guarantees the programmed EPROM cell for the life of tbe part.

PORTS _ _ _ _ _

3/4

\~---------------------270704-74

Figure 17-7. Word Dump Command

PROGRAM:

LOOP;

POP ADDRESS. TEMP
POP DATA.TEMP
PUSHF
LD COUNT, #25T

;Load program data
;and address

LDB INT.MASK,#ENABLE.SWT
LDB HSO.COMMAND,#SWTO.OVF
ADD HSO.TIME,TIMER1,#PROGRAM.PULSE
EI
ST DATA.TEMP,[ADDR.TEMP],
IDLPD 1
DJNZ COUNT, LOOP
POPF
RET

;program USing Modified
Quick Pulse
;program SWT for
;program pulse width
;enter idle mode until
;swt expires
;loop 25 times

;service swt and return

RET
Figure 17-8. Run-Time

Prog~amming

5-99

Algorithm Example

;

8OC196KC USER'S GUIDE

The OED (disable external Data fetch) bit disables the
bus controller from executing external data reads and
writes if the bit is O. If a data access is requested from
the bus controller, the part will Reset itself.

17.5 ROM/EPROM Memory Protection
Options
Write protection is available for EPROM parts, and
read protection is provided for both' ROM and
EPROM parts.

For more information on UPROMs, ~ Section '17.5.

Write protection is enabled by setting the LOCO bit in
either CCR or the PCCB to zero. Figure 17-9 summarizes the different write protection options. When write
protection is enabled, the bus controller will cycle
through the write sequence but will not actually drive
data to the EPROM or enable Vpp. This protects the
entire EPROM 2000 ... 5FFFH from inadvertent or unauthorized programming; With write protection enabled, the PTS cannot read the internal EPROM. '

CCB PCCB
LOCO LOCO

Authorized Access of Protected Memory
A "Security! Key" mechanism has been implemented
for authorized access of protected internal memory to
test internal ROM/EPROM. This allows users to verify the EPROM array and still keep their code protected.
'
The security key is a 128-bit number located in internal
memory at locations 2020H-202FH. The user programs his own security key into these locations. Figure
17-10 shows the different programming modes and
whether a security key verification is performed to allow entry into the programming mode.
'

Protection

. 1

Unprotected EPROM. Writes to
Internal M~mory always allowed.

Run-Time Programming Allowed.
No programming modes allowed

Run-Time programming not
allowed. Programming modes
allowed after key verification (if
needed).

Slave Programming

All programming unconditionally
disabled.

AUTO Programming

If Protected·

PCCB Programming

Never

Programming
Mode
ROM Dump

KeyVerification
If Protected·
Always

UPROM Programming

Figure 17-9. Write Protection Options

Never

•If read or Wrtte protected In GGA.

Read protection is enabled by setting the LOci bit of
CCR to a zero. When read protection is selected, the
bus controller will only perform a data read from the
address range 2020H-202FH and 2050H-5FFFH if
the Slave Program Counter is in the range 2000H5FFFH. Since the Slave PC can be as many as 4 bytes
ahead of the CPU program counter, an instruction after
address 5FFAH'may not access protected memory.
The interrupt vectors and CCB are not read protected
since interrupts can occur even when executing out of
external memory. LOCI in the PCCB can be programmed, b'ut has no memory protection implications.
Also, two UPROM (Unerasable PROM) bits are implemented on the 87C196KC for additional memory
protection. The DEI (Disable External Instruction
fetch) bit disables the bus controller from executing external instruction fetches if the bit is a O.If an attempt
is made to load the Slave PC with an external address,
the part will Reset itself. The automatic Reset also
gives extra protection against runaway code.
Because of the prefetch queue in the bus controlier,
code cannot be executed from the last four bytes of
"
internal memory if this feature is enabled.

Figure 17-10. Security Key Verification
I

The ROM Dump Mode is an easy way to verify the
contents of the EPROM or ·ROM array. The ROM
Dump writes out the entire EPROM or ROM to locations 4OOOH-7FFFH in external memory. If the DED
(Disable External Datil Fetches) bit has been programmed in the USFR, this mode is disabled entirely
(see Section 17.5).
The ROM Dump Mode is selected with PMODE =
06H and always begins with a security key verification.
The user puts the same security key at external locations 4020H-402FH that he has programmed in internal lpcations 2020H.202fH. Before doing a ROM
dump, the 80C196KC compa'r~s the two security keys.
If they match, the80C196KC dumps the array to external memory. If they do not match, the 8OC196KC
enters an endless loop of internal execution which can
be exited only by a chip reset.

When using the Auto Program1lling Mode, a security
key verification is done if the CCB has read and or
write protection enabled. The security key must reside

5-100

inter

80C196KC USER'S GUIDE

in external memory locations 4020H-402FH and the
two keys must match or the 80C196KC enters an endless internal loop.

programming a UPROM bit, it can be verified to make
sure that it did indeed program. Customers are advised
that devices with programmed UPROM bits cannot be
returned to Intel for failure analysis.

In the Slave Programming Mode, a security key verification is also performed if CCB has read and or write
protection enabled. The key verify is done 'somewhat
differently in the Slave Programming Mode. The user
must "program" the correct key into the array at locations 2020H-202FH using the Data Program Command described in Section 17.3. The locations are not
actually programmed, but the da~a is compared to the
internal security key. The key must be entered sequentially, and if any of the locations is "programmed" incorrectly, the 80C196KC will enter the elusive endless
internal loop.

Programming UPROMs

The UPROM bits in the USFR can be programmed
using the Slave Programming Mode, or with the separate UPROM Programming Mode. Figure 17-12 shows
the locations to program a UPROM bit and the data in
the Slave Programming Mode.

If CCB has any protection enabled, the security key is
write protected to keep unauthorized users from overwriting the key with a known security key.
If the PCCB is programmed with any read or write
protection, there is no way to enter any of the programming modes. So the last thing that should be done to
protect the part from unauthorized access, is to program the PCCB.

17.6 UPROMs
Unerasable PROM (UPROM) devices are implemented on the 87C196KC for some additional security features. The USFR (UPROMSpecial Function Register)
along with what bits are available for the .ROM and
EPROM versions is shown in Figure 17-11. The
UPROM bits act as fuses, i.e., they can be programmed, but not erased.
7

*IRSvIRSvIRSvIRSVIDEIIDEDIRSVIRSvl
USFR
DEI

DED

87C196KC

UPROM Bit

83C196KC

N/A

Bit

Address

Data

DED
DEI

0758H

OOO4H

0718H

0008H

Figure 17-12. Programming UPROMs
in the Slave Programming Mode

The UPROM Programming mode works much the
same way as the PCCB Programming Mode (see Figure
17-5). PMODE must be 09H, the value to program the
USFR is forced onto port 3, OFFH is forced on port 4,
and PALE is pulled low to begin programming. A 1 in
a bit location means to program the associated
UPROM bit. PACT remains low while programming
and PVER indicates if the data was programmed correctly.
The Modified Quick Pulse Algorithm

The Modified Quick Pulse Algorithm must be used to
guarantee programming ov.er the life of the EPROM in
Run-Time and Slave Programming Modes.
The Modified Quick-Pulse Algorithm calls for each
EPROM location to receive 25 separate 100 /bs
(± 5 /bs) programming cycles. Verification is done after
the 25th pulse. If the location verifies, the next location
is programmed. If the location fails to verify, the location fails the programming sequence.
Once all locations are programmed and verified, the
entire EPROM is again verified.
,

*Always program reserved (RSV) bits to 1

Programming of 87C196KC EPROMs is done with
Vpp = 12.50V ±0.25V and Vee = 5.0V ±0.5V.

Figure 17-11. USFR

Because the UPROM bits cannot be erased, the bits
cannot be tested by Intel prior to shipment. Intel does,
however, test the different features enabled by UPROM
bits. Therefore, only defects within the UPROM cells
themselves (rather unlikely) will be undetectable. When

Signature Word

The 87C196KC contains a signature word. The word
can be accessed in the Slave Mode by executing a Word
Dump Command at memory location 70H. The pro-

5-101

inter

80C196KCUSER'S GUIDE

gramming voltages are determined by reading locations
72H and 73H in Slave Frogramming Mode. The voltages are calculated by using the following equation.
Voltage

1S.0 SOC196KC to SOC196KB
1S.1 New Features of the SOC196KC

20/256 x (test ROM data)

1. The 80C196KC has 488 bytes of RAM and is available with 16K of EPROM/ROM. The 80C196KB
has 232 bytes of RAM and 8K of EPROM/ROM. A
Vertical Windowing scheme has been implemented
to allow the extra 256 bytes of RAM to be accessed
as Registers. See Section 3.3.
2. The 80CI96KC has an additiomil 2 PWM outputs
over the SOCI96KB. See Section S.O.
3. The SOCI96KC has the Peripheral Transaction Server (PTS), which can greatly reduce interrupt servicing overhead. See Section 6.0.
4. Timer2 can now be clocked internally as well as externally. Timer2 can clock internally every I or S
states selectable by software. See Section 7.0.
5. The HSO has one new command that allows all of
the pins to be addressed simultaneously. See Section
10.0.
6. The A/D on the SOCI96KC has an S-bit conversion
mode as well as IO-bit. Also, the A/D has selectable
sample and convert times. See Section 12.0.
7. The SOC196KC has 2 UPROM (unerasable programmable read only memory) for additional securityenhancements. See Section 17.5.

The values for the signature word and voltage levels are
shown in Figure 17-13.
Description

Location

Value

Signature Word
Programming Vee

70H
72H

Programming Vpp

73H

879CH
040H
5.0V
OAOH
12.50V

Figure 17-13. Signature Word and Voltage Levels
Erasing the 87C196KC

After each erasure, all bits pf the 87C 196KC are logical
"Is". Data is introduced by selectively programming
"Os". The only way to change a "0" to a "I" is by
exposure to ultraviolet light.
The erasure characteristics of the 87C196KC are so
that erasure begins upon exposure to light with wavelengths shorter than approximately 4OOOA. It should be
noted that sunlight and certain tYl?es of fluorescent
lamps have wavelengths in the 3000A-4000A range.
Opaque labels must always be placed over the Window
to prevent unintentional erasure. In the Powerdown
Mode, the part will draw more current than specified if
the EPROM window is exposed to light.
The recommended erasure procedure for the
87C196KC is exposure to ultraviolet light which has a
wavelength of 2537A.

1S.2 Converting SOC196KB Designs to
SOC196KC Designs
1. Clock Detect Enable Pin (CDE) -The CDE pin on
the SOCI96KB is a Vss pin on the SOCI96KC. An
extra VSS pin was needed on the SOC196KC to support the higher clock rates.

5-102

BOC196KC USER'S GUIDE

2. DJNZW tnstruction -The DJNZW will work
properly on the SOC196KC. However, it will take 6/
10 state times rather than 5/9 state times as on thj:
SOC196KB.
3. Internal Reset Pulse -The Reset pulse on' the
SOC196KC has been increased to 16 state times.
There are 2 ways a SOC196KB or SOC196KC can
internally assert the RESET pin; Watchdog Timer
Overflow, and a RST instruction. On the KB, the
Reset Pulse is 4 state times. Because the SOC196KC
and future proliferations will run at much higher frequencies, a 4 state time reset pulse was deemed unreasonably small. This should cause no problems in
most applications.
4. Memory Map -Because the' SOC196KC has 16K of
EPROM/ROM and 512 bytes of RAM, twice that of
the SOC196KB, the memory map is different to accommodate the extra memory. Locations 1001FFH contain the additional 256 bytes of RAM on
the SOC196KC. On the EPROM/ROM versions,locations 4000-5FFFH contain the extra SK of
EPROM.
5. ONCE Mode Entry -The SOC196KC enters the
ONCE mode by holding the TXD pin low on the
rising edge of RESET. See Section 15.3.

6. EPROM Programming Modes -Gang Programming with the Slave Programming Mode is no longer
supported. Also, the Auto-Programming and Slave
Programming Modes have been modified to support
the 16K of onboard memory. This should only affect
manufacturers of EPROM programmers, and should
not have an impact on the end user.

7. AID Converter -An

AID

conversion takes 1.5
state times less on the SOC196KC in both the fast
and slow conversion modes.
S. HOLDIHLDA -The RD, WR, WRC, INST,
BHE, ADV arid ALE pins are weakly held in their
inactive states during HOLD on the SOC19,6KC. On
the SOC 196KB, only ALE is weakly held during
HOLD.
9. The PSW -The PSW on the SOC196KC has an extra bit (PSE) to support the PTS. This bit was reserved on the SOC196KB.
10. HSO -HSO commands OCH and ODH were reserved on the SOC196KB. On the SOC196KC, OCH
becomes a new command.
11. WSR -WSR bits that were reserved to 0 on the
SOC196KB must be 0 to be SOC196KC compatible.

5-103

8XC196KC
; 16.-BITHIGH·PERFORMANCE CHMOS
MICROCONTROLLER
87C196KC-16 Kbytes of On-Chip EPRO,.,
80C196KC-ROMless
.

16 MHz 0p,eratI9n
• 232
Register File
• 256 Byte
Bytes of Additional
• Register-ta-Reglster
Architecture
• 28 Interrupt Sources/16
Vectors
• Peripheral Transaction Server
• 1.75 ,."s 16 x 16 Multiply (16 MHz)
•• 13.0,."s 32/16.Divide (16 MHz)
Powerdown and Idle Modes
• Five
I/O Ports
• 16-Bit8-Blt
• VVatchdog Timer
R~M

•
•
•
•
•
•
•
•
•
•

Dynamically Conflgurable 8-Bit or
16~Blt Buswidth
Full Duplex Serial Port
High Speed I/O Subsystem
16-Bit Timer
16-Bit Up/Down Counter with Capture
3 Pulse-Width-Modulated Outputs
Four 16~Bit Software Timer:s
8- or 10-Bit A/D Converter with·
Sample/Hold
HOLD/HLDA Bus 'Protocol
OTP One-Time Programmable Version

The 80C196KC 16-bit microcontroller is a high performance member of. the MCS®-96 microcontroller family.
The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 MHz operation ~nd an optional
16 Kbytes of ROM/EPROM. Intel's CHMOS IV process provides a high performance procesSor along with low
power consumption.
The 87C196KC is an 80C196KC with 16 Kbytes on-chip EPROM. In this document, the 80C196KC will refer to
all products unless otherwise stated.
'.,,'

Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an AID conversion. Events can be based on the timer or up/down counter.
VREF

ANGND

CONTROL
SIGNALS

PORT 3

} ~~:
BUS

•

PORT 4

I;~~~~PWMI

~PWM2
HSO

270942-1

Figure 1. 80C196KC Block Diagram
MCS$-96 is a

regist~red

trademark of Intel Corporation ..
November 1990
Order Number: 270942-001

inter

8XC196KC

80C196KC Enhanced Feature Set over the 80C196KB
1. The 80C196KC has twice the RAM and twice the ROM/EPROM of the 80C196KB. Also, a Vertical Register
Windowing Scheme allows the extra 256 bytes of RAM to be used as registers. This greatly reduces the
context switching time.
2. Peripheral Transaction Server (PTS). The PTS is an alternative way to service an interrupt, reducing latency
and overhead. Each interrupt can be mapped to its PTS channel, which acts like a DMA channel. Each
interrupt can now do a single or block transfer, without executing an Interrupt service routine. Special PTS
modes exist for the AID converter, HSI, and HSO.
3. Two extra Pulse Width Modulated outputs. The 80C196KC has added 2 PWM outputs that are functionally
compatible to the 80C196KB PWM.
4. Timer2 Internal Clocking. Timer2 can now be clocked with an internal source, every 1 or 8 state times.
5. The AID can now perform an 8- as well as a ,10-bit conversion. This trades off resolution for a faster
conversion time.
'
6. Additional On-chip Memory Security. Two UPROM (Uneraseable Programmable Read Only Memory) bits
can be programmed to disable the bus controller for external code and data fetches. Once programmed,' a
UPROM bit cannot be erased. By shutting off the bus controller for external fetches, no one can try and
gain access to your code by executing from external memory.
7. New Instructions. The 80C196KC has 5 new instructions. An exchange (XCHB/XCHW) instruction swaps
two memory locations, an Interruptable Block Move Instruction (BMOVI), a Table Indirect Jump (TIJMP)
instruction, and two instructions for enabling and disabling the PTS (EPTS/DPTS).
The 80C196KC User's Guide contains a complete desCiription of the feature set, order # 270704.

PACKAGING
QFP
Pin#

PLCC
Pin#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

59
60
61
62
63
64
65
66
67

N.C.

68
1
2,
3
4
5
6
7
8
9
10
11
12
13
14

Description

QFP
Pin#

PLCC
Pin#

AD1/P3.1
ADO/P3.0
RD
ALE/ADV
INST
BUSWIDTH
CLKOUT
XTAL2
XTAL1
Vss
Vss
Vec
Vcc
EA
NMI
ACH3/PO.3
ACH1/PO.1
ACHO/PO.O
ACH2/PO.2
ACH6/PO.6
ACH7/PO.7
N.C.
ACH5/PO.5
ACH4/PO.4
ANGND
VREF
Vss

28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

Description
EXTINT IP2.2
Vcc
RESET
RXD/P2.1
TXD/P2.0
Vss
P1.0
P1.1
P1.2
P1.3/PWM1
P1.4/PWM2
HSI.O
HSI.1
HSO.4/HSI.2
N.C.
HSO.5/HSI.3
HSO.O
HSO.1
P1.5/BREQ
P1.6/HLDA
P1.7/HOLD
P2.6/T2UP-DN
HSO.2
Vss
Vce
HSO.3
Vss

= No Connection
Figure 2. Pin Definitions
5-105

QFP PLCC
Pln# Pin#
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52,
53
54
55
56
57
58

Description
VSS
Vpp

P2.7/T2CAPTURE
PWMO/P2.5
WR/WRL
BHE/WRH
T2RST/P2.4
READY
N.C.
T2CLK/P2.3
AD15/P4.7
AD14/P4.6
AD13/P4.5
AD12/P4.4
AD11/P4.3
AD10/P4.2
AD9/P4.1
AD8/P4.0
AD7IP3.7
AD6/P3.6
N.C.
AD5/P3.5
AD4/P3.4
AD3/P3.3
N.C.
AD2/P3.2

inter

8XC196KC

:J:

CD
:J:

'" C! 0 '"0
''- '- '- '- '-,
"'"
u u '"
« « « « « ~ ~
00. ~
0 00..

Q..'Q..

:J:
U

:t:

:J:

I~«

0
:J: ,:J:
U U

I~ ~

11)«
11)1-

5 Q
'" 0 i::>
~
...J

> x x

(I)

""U
...J

III

, ,

0-'-

~ ~Ifi

ACH5/PO.5

ADO/P3.0

ACH4/PO.4

AD1/P3.1

ANGND

AD?/P3.2

VREF

AD3/P3.3

VSS

AD4/P3.4

EXTINTjP2.2

AD5/P3.5

RESET

AD6/P3.6

RXD/P2.1

AD7/P3.7

TXD/P2.D

AD8/P4.0

PI.O

Plol

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD

PI.2
PWMI/Pl.3
PWM2/PI.4
HSIO
HSII

AD9/P4.1
AD10/P4.2
ADll/P4.3
ADI2/P4.4
ADI3/P4.5
ADI4/P4.6
ADI5/P4.7

HSI2/HS04

T2CLK/P2.3
27 28 29 30 31 32 33 34 35 3637 38 39 40 41 42 43

o(I)

0
0

(I)

~:t:

'"iii
J:

270942-2

Figure 3. 6a·Pin PLCC Package
Table 1. Prefix Identification
QFP
80C196KC
87C196KC
'OTP Version

S80C196KC
S87C196KC'

5-106

PLCC

N80C196KC
N87C196KC •

inter

8XC196KC

aD-Pin Quad Flat Pack (EIAJ)
Contacts
Facing Up

Contacts
Facing Down
PIN NO.1 IotARK

41
40

270942-39

Top View

1111111111111111

., ....'" .,....
0

....
TEST POINTS

0.45~0.8

270942-21

FLOAT WAVEFORM

< 0.8~
V-2.0

270942-22
A,C, Testing inputs' are driven at 2AV for a Logic "1" and OA5V'
for a Logic "0" Timing measurements are made at 2,OV for a
Logic "1" and O,BV for a Logic "0",

270942-23
For Timing Purposes a Port Pin is no Longer Floating when a
100 mV change from Load Voltage Occurs and Begins to Float
when a 100 mV change from the Loaded VOHIVOl Level occurs
IOl/loH ~ ± 15 mA,

Signals:

L-

H- High

A-

BR-BREO

L-

Low

V-

Valid

xz-

Floating

No Longer Valid

Address

B- BHE
C- CLKOUT
D- DATA
G- Buswidth
H- HOLD
HA-HLDA

,.5-121

R-

ALE/ADV
RD

W- WR/WRH/wRL
X-

XTAL1

y- READY
0- Data Out

\ 8XC196KC

A.C. CHARACTERISTICS-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT TIMING-SHIFT REGISTER MODE
Symbol

Parameter

TXLXL

Serial Port Clock Period (BRR ~ 8002H)

TXLXH

Serial Port Clock Falling Edge
to Rising Edge (BRR ~ 8002H)

TXLXL

Serial Port Clock Period (BRR = 8001 H)

TXLXH

Min

Max·

Units

6 Tose

4 Tose ±50

4 Tose

Serial Port Clock Falling Edge
to Rising Edge (BRR = 8001 H)

2 Tose ±50

TQVXH

Output Data Setup to Clock Rising Edge

2 Tose - 50

TXHQX

Output Data Hold after Clock Rising Edge

2 Tose - 50

TXHQV

Next Output Data Valid after Clock Ri!?ing Edge

TOVXH

Input Data Setup to Clock Rising Edge

TXHOX

Input Data Hold after Clock Rising Edge·

TXHQZ

Last Clock Rising to Output Float

2 Tose + 50

Tose +50

ns
1 Tose

WAVEFORM-SERIAL PORT-SHIFT REGISTER MODE
SERIAL PORT WAVEFORM-SHIFT REGISTER MODE

RXD --" ....-ccc".".r .. ·_.".,'.:cc
(IN)_J'-~

270942-24

8XC196KC

EPROM SPECIFICATIONS
A.C. EPROM Programming Characteristl~s
Auto, Slave Mode Operating Conditions: Load Capacitance = 150 pF, TA = +25·C ±5·C, Vee, VREF =5V,
Vss, ANGND = OV, Vpp = 12.50V ±0.25V, EA = 12.50V ±0.25V
Run Time Programming Operating Conditions: Fosc = 6.0 MHz to 12.0 MHz, VREF = 5V ±0.50V. TA =
+ 25·C to ± 5·C and Vpp = 12.50V. For run·time programming over a full operating range, contact the factory.

Symbol

Descrlptlqn .

TSHLL

Reset High to First PAIl: Low

TLLLH

PALE Pulse Width

TAVLL
TLLAX

Min

Max

Units

1100

Tose

Tose'

Address Setup Time

Tose

Address Hold Tir:ne

100

Tose

TpLDV

~ Low to Word Dump Valid

Tose

TpHDX

Word Dump Data Hold

Tosc

TDVPL

Data Setup Time

Tose

TpLDX

Data Hold Time

400

Tose

TpLPH(1)

~ Pulse Width

Tose

TpHLL

~ High to Next PALE Low

220

Tose

TLHPL

PALE High to PRC:m" Low

220

Tose

~ High to Next ~ Low

220

Tose

240

Tose

TILVH

7iJiiIe Pulse Width
PVER Hold after 7iJiiIe Low
"

Tose

TILPL

AINC Low to ~ Low

170

Tose

TpHVL

PROG High to PVER Valid

TpHPL
·TpHIL
TILIH

., ~ High to AINC Low

220

Tosc

NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm.

D.C. EPROM Programming Characteristics
Symbol
Ipp

Description
Vpp Supply Current (When Programming)

NOTE:

Vpp must be within 1V of Vee while Vee < 4.5V. Vpp must not have a low impedance path to ground of VSS while
Vee> 4.5V.

5-123

•

EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITt! S.INGLE PROGRAM PULSE

PORTS

----r----

--+-0---<

3/4

ADDR/COt.tt.tAND

PVER

270942-27

SLAVE PROGRAM MODE IN WORD DUMP WITH AUTO INCREMENT

RESEt
I,

--'
I

P(lRTS
3/4

ADDR/COMMAND

I--PALE

tSHLL - -

tPLDV -

tPHDX

-00

ADDR+2

VER BITS/WD DUMP

1-,

KtPLDV -

tPHDX -

PROO
tlLPL
AINC

ADDR

VER BITS/WD DUMP

-"
\

-tPHPL'

V
"

270942-28

5·124

inter

8XC196KC

SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITWREPEATED PROGPULSE AND

AUTO INCREMENT

PO:;~

---_-«

. .

AOOR/COMMANO'

>---<

AOOR
OATA

AOOR '

>>----~

AOOR + 2
OATA

>--

PVER

27Q942-29

5-125

8XC196K:C

of VREF. VREF must be close to Vcc since it supplies
both the resistor ladder and the digital section of the
converter.

10-811 AID CHARACTERISTICS
The speed of the AI D' converter in the 10-bit mode
can be adjusted by setting a clock prescaler on or'
off. At high frequencies more time is needed for the
comparator to settle. The maximum frequency with
the clock prescaler disabled is 6 MHz. The conversion times' with the prescaler turned on or off is
shown in the table below. The following specifications are tested @ 16 MHz with OC7H in AD_TIME.

AID CONVERTER SPECIFICATIONS
The specifications given below assume adherence
, to the Operating Conditions section of this data
, sheet. Testing is performed with VREF = 5.12V.

The converter is ratiometric, so the absolute accuracy is dependent on the accuracy and stability

I Conv~rt Time

Clock Prescaler On
IOC2.4 = 0

Clock Prescaler Off
IOC2.4 = 1

Sample Time
24 States

156.5 States
19.5 JLS@ ,16 MHz

89.5 States
29.8 JLs @ 6 MHz

C7H in AD __TIME
13.3125 JLs @ 16 MHz

Parameter

Typical(3)

Resolution

80 States

Minimum

Maximum

Units·

1024
10

Levels
Bits

±3

LSBs

Absolute Error'
Full Scale Error

0.25 ± 0.5

LSBs

Zero Offset Error

0.25 ± 0.5

LSBs

Non-Linearity

1.0 ± 2.0

Differential Non-Linearity Error
Channel-to-Channel Matching

±3

LSBs

> -1

LSBs

±1

LSBs

±0.1

Repeatability

±0.25

LSBs

Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity

0.009
0.009
0.009

LSBrc
LSBrC
LSB/oC
-60

Off Isolation
Feedthrough

-60

Vcc Power Supply Rejection

-60

Input Resistance
D.C. Input Leakage

750

1.2K

3.0

1,2

n
JLA

Sample Time: Prescaler On
Prescaler Off

16
8

States
States

Input Capacitance

NOTES:
'An "LSB", as used here, has a value of approximately 5 mY.
1, DC to 100 KHz,
2. Multiplexer Break-Before-Make Guaranteed.
3, Typicalvalues are expected for most devices at 25'C.

5-126

Notes

8XC196KC

8-BIT MODE AID CHARACTERISTICS

Sample Time

Convert Time

The 8-bit mode trades off resolution for a faster conversion time. The AD_TIME register must be used
when performing an 8-bit conversion.

20 States

56 States

The following specifications are tested
with OA6H in AD_TIME.
Parameter

A6H in AD_TIME
9.8125 JA-S@ 16 MHz

16 MHz

Typical

Minimum

Maximum

Units·

256
8

Levels
Bits

±1

LSBs

Resolution
Absolute Error
Full Scale Error

±0.5

Zero Offset Error

±0.5

LSBs
LSBs
0

±1

LSBs

> -1

LSBs

±1

LSBs

Non-Linearity
Differential Non-Linearity Error

Notes

Channel-to-Channel Matching
Repeatability

±O.25

LSBs

Temperature Coefficients:
Offset
Full Scale
Differential Non-Linearity

0.003
0.003
0.003

LSBI"C
LSBI"C
LSBI"C

NOTES:
'An "LSB", as used here, has a value of approximately 20 mY.
1. Typical values are expected for most devices at 25'C.

80C196KB TO 80C196KC DESIGN
CONSIDERATIONS

5. During the bus HOLD state, the 80C196KC weakly holds RD, WR, ALE, BHE and INST in their
inactive states. The 80C196KB only holds ALE in
its inactive state.

1. Memory Map. The 80C196KC has 512 bytes of
RAM/SFRs and 16K of ROM/EPROM. The extra
256 bytes of RAM will reside in locations 100H1FFH and the extra 8K of ROM/EPROM will reside in locations 4000H-5FFFH. These locations
are external' memory on the 80C196KB.

6. A RESET pulse from the 80C196KC is 16 states
rather than 4 states as on the 80C196KB (Le., a
watchdog timer overflow). This provides a longer
RESET pulse for other devices in the system.

2. The CDE pin on the KB has become a VSS pin on
the KC to support 16 MHz operation.

80C196KC ERRATA

3. EPROM programming. The 80C196KC has a different programming algorithm to support 16K of
on-board memory. When performing Run-Time
Programming, use the section of code on page
3-91 of the 1989 16-bit Embedded Controller
Handbook.
4. ONCETM Mode Entry. The ONCE mode is entered on the 80C196KC by driving the TXD pin
low on the rising edge of RESET. The TXD pin is
held high by a pullup that is specified at 1.4 mA
and remain at 2.0V. This Pullup must not be overridden or the 80C196KC will enter the ONCE
mode.

1. Absolute maximum voltage on Port 0 is -0.5V to
9.0V relative to AVss.
2. The HSI unit has two errata: one dealing with resolution and the other with first entries into the
FIFO.
The HSI resolution is 9 states instead of 8 states.
Events on the same line maybe lost if they occur
faster than once every 9 state times. '
There is a mismatch between the 9 state time HS"i
resolution and the 8 state time timer. This causes
one time value to be unused every 9 timer counts.

inter "

8XC,196KC

Events may receive's time:tagon one count later
than expected because of this '''skipped;' time value.

later than the firs~ ,time tag. If this is the ':skipped"
time value, tlie second event's time-tag is 2
counts later than the first's.

If the first two eventsintb an empty FIFO (not
including the Holding Register) occur in the same
internal phase, both are recorded with one timetag. Otherwise, if the second event occurs within
9 states after the first, its time-tag is one count

If the FIFO and Holding Register are empty, the
first event will transfer into the Holding Register
atter8 state times, leaving the FIFO empty again.
If the second event occurs after this time, it will
act as a new first event into an empty FIFO.

DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a "C" at the end of the topside tracking number. Data sheets are
changed as new device information becomes available. Verify with your local Intel sales office that you have
the latest version before finalizing a design or ordering devices.
The following differences exist between this data sheet and 270741-003.
1. ONCE MODE VIL errata removed.
2. VREF Min changed from 4.5V to 4.0V.
The following differences exist between the -002 and -003 versions of data sheet 270741.
1. 80-Pin QFP package added, 68-pin Cerquad package deleted.
2. The following D.C. Characteristics were added:
VHYS RESET Hysteresis spec added
IIL1, AD BUS in RESET current Max added
3. The following A.C. Characteristics were changed:
TAVYV Max from 2Tasc-75 to 2Tasc-68

T AVGV Max from 2Tasc-7 5 to 2Tasc-68
TWLWH Min from Tasc-30 to T asc-20
TXHCH Min changed from 30 ns to 20 ns

'rHALBZ Max changed from 10 ns to 15 ns
4. Under 10-bit AID Characteristics:
Sample Time/Convert Time Testing Conditions added.
Typical values added for Full Scale Error, Zero Offset Error, Non-Linearity, and Channel-to-Channel Matching.
Max Absolute Error changed from ± 8 to ± 3 LSBs
Max Non-Linearity changed from ± 8 to ± 3 LSBs
5. Under 8-bit Mode AID Characteristics;
Max Absolute Error changed from ± 2 to ± 1 LSBs
Max Non-Linearity changed from ± 2 to ± 1 LSBs
Typical Full Scale Error changed from

± 1 to ±0.5 LSBs

Typical Zero Offset Error changed from ± 2 to ± 0.5 LSBs
6. The minimum freqUency at which the device is tested was changed to 8.0 MHz from 3.5 MHz. Thus, data
sheet specifications are guaranteed from 8 MHz to 16 MHz. However, the device is static and will function
below 1 Hz.
7. The T2CONTROL (T2CNTC) SFR was renamed IOC3.
S. ONCE MODE VII: errata added. Other errata removed.
9. The A:Step device corresponding to data sheet 270741-002 had bits IOC1.4 and IOC1.6 reversed. The
problem was corrected in the B-1 Step device corresponding to data sheet 270741-003.

5-128

8XC196KC

DATA SHEET REVISION HISTQRY (Gon~inued~,
The following are the important differences between the -001 and -002 versions of data sheet 270741. Please
review this revision history carefully. " '
1. The 83C196KC (ROM) was added to the product line.
2. The OTP version of the EPROM was added to the product line.
3. RClli5/HLOA Specifications were ,added.
4. The IOL test condition on VOl1 has changed to -0.5 mA from -0.4 mAo
5. The IOH test condition VOH2 has changed to 0.8 mA from 1.4 mA.
6. BMOVi errata w~s added.,
7. Errata was added for the 'HSI resolution arid first event anomalies.
8. Errata was added for the serial port Framing Errbr anomaly.
("

5-129

','. "

8XC196KC
16-BIT MICROCONTROLLER
. EXPRESS

87C196KC-16 Kbytes of On-Chip EPROM
80C196KC-ROMless
83C196KC-16 Kbytes of On-Chip ROM
Temperature Range
• (-Extended
40°C to + 85°C)
16 MHz Operation
• 232
Register File
• 256 Byte
Byles of Additional RAM
• Register-to-Register Architecture
• 28 Interrupt Sources/16 Vectors
• Peripheral Transaction Server
• 1.75 J-ts 16 x 16 Multiply (16 MHz)
• 3.0
J-ts 32/16 Divide (16 MHz)
• Powerdown
and Idle Modes

• Five 8-Bit I/O Ports

•
•

Configurable 8-Bit or
• Dynamically
16-Bit Buswidth .
Duplex Serial Port
• Full
Speed I/O Subsystem
• High
16-BitTimer
• 16-Bit Up/Down Counter with Capture
• 3 Pulse-Width-Modulated Outputs
• Four 16-Bit Software Timers
• 8- or 10-Bit A/DConverter with
• Sample/Hold
Bus Protocol
• HOLD/HLDA
OTP One-Time Programmable Version
•

16-Bit Watchdog Timer

With the commercial standard temperature range operational characteristics are guaranteed over the temperature range of O°C to + 70°C. With the extended temperature range option, operational characteristics are
guaranteed over the range of - 40°C to + 85°C.
Package types and EXPRESS versions are identified by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
All A.C. and D.C. parameters in the commercial data sheets apply to the Express devices.

CONTROL
SIGNALS

PORT 3

} ~f:
BUS

PORT"

1~~~~~PW~l

~PW~2
270794-1

Figure 1. 8XC196KC Block Diagram
MCS®-96 is a registered trademark of Intel Corporation.

5-130

November 1880
Order Number: 270794-001

intJ

8XC196KC EXPRESS.

PACKAGING
The 80C196KC is 8vailablein a 68-pin PLCC package and 87C196KC is available fn a 68-pin Cerquad package. Contact your looal sales office to determine the ~xact orde~ing code for., the part desired. .
Pin

Description

9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
60
59
58
57
56
55

ACH7/PO.7,
. ACH6/PO.6
ACH2/PO.2
ACHO/PO.O
ACH1lPO.1
ACH3/PO.'3
NMI
EA

'vdc '
Vss

XTAL1
"X-r:AL2
CLKOUT
SUSWIDTH
INST
ALE/ADV'

Pm:

ADO/P3.n'
AD1/P3.1
AD2JP3.2
AD3/P3.3
AD4/P3.4
AD5/P3.5

Pin.

Description

54
53
52
51
50

AD6/P3.6
AD7/P3.7
AD8/P4.0
AD9/P4.1
A010(P4,2 .
AD11/P4.3
AD12/P4.(
AD13/P4.5.
AD·14/P4.6
AD15/P4.7
T2CLK/P2.3
. READY
T2RST/P2.4,
SHE/WRH
WR/WRL
PWMO/P2.5
P2.7/T2CAPTURE
Vpp

\",

49
4$
47
46
45
44
43
42
41
40
39
38
37.
36
35
34
33
32

Vss'
HSO.3
HSO.2
P2.6/T2UP-DN
P1.7/HOLD

..
'.

Pin
31
30
29
28
27
.26
, 25
24
23

Description
P1.61HLDA

, P1.5/BFiEO

,-'.I

21
20
19
18
17
16
15
14
13
12
11
10

HSO.1
HSO.0
.HSQ.Sj'1SI.3
HSO.4/HSI.2
HSI.1.
HSI.O
P1A/PWM2
P1.3tPWM1
P1.2
P1.1
P1.0'
TXD/P2.0
RXD/P2.1
RESET
. EXTINT/P2.2

Vss
'VREF
ANGND'
ACH4/P.04
ACH5/P.05

Figure 2. Pin Definitions
Table 1. Prefix Identification
Cerquad
98765.3,

I~D~~~~~~

ACHS/PO.5

ADO/P30

ACH4/PO ...
ANGND

TN80C196KC

83C196KC

TN83C196KC

'OTP VersIon

EXTINT/P2.2

RESET

AD6/P3.e

RXD/P2.1
TXOjP2.Q

17
18

"'07/P3.?
AD8/P4.0

52
51
50

P1.0

Pl.1
PWW1/P13

80C196KC

87C196KC

Vss

TOP VIEW
LOOKING DOWN ON
COMPONENT SIDE
OF PC BOARD

AD9/P4.1
ADIO/P.2
ADfl/P •. 3
AD12/P44

47
46

...OI3/P45
ADI4/P4.6

HSI1

AOISiP4.?

HS12/HS04

T2CLK/P2".3

D~~~~.~M~~D~~~~aa

270794-2

Figure 3. 68-Pin Cerquad and PLCC Package

5-131

PLCC

TJ87C196KC

TN87C196KC'

EV80C196KC FEATURES·
•
•
•
•
•
•
•
•
•
•

Zero Wait-State 16 MHz Execution Speed
24K Bytes of ROMsim
Flexible Wait-State, Buswidth, Chip-Select Controller
Totally CMOS, Low Power Board
Concurrent Interrogation of Memory and Registers
Sixteen Software Breakpoints
Two Single Step Modes
High-Level Language Support
Symbolic Debug .
RS-232-C Communication Link

LOW COST CODE EVALUATION TOOL
Intel's EV80C196KC evaluation board provides a hardware environment for code
execution and software debugging at a relatively low cost. The board features the
80C196KC advanced, CHMOS*, 16-bit microcontroller, the newest member of the
industry standard MCS®-96 family. The board allows the user to take full advantage of
the power of the MCS-96. The EV80C196KB provides zero wait-state, 16 MHz execution
of a user's code. Plus, its memory (ROMsim) can be reconfigured to match the user's
planned memory system, allowing for exact analysis of.code execution speeds in a
particular application.
~CHMOS is a patented Intel process.
"IBM PC, XT, AT and DOS are regIstered trademarks of Intemahonal Busmess Machines Corporation.

inter---------'----'-------Intel Corporation assumes no responsibihty for the use of any circuitry other than circuitry embodies in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

APRIL 1989
@

Intel Corporation 1989

5-132

Order number: 270802-001

Popular features such as a symbolic single line assembler1disassembler, single-step
program execution, and sixteen software breakpoints are standard on the EV80C196KC
Intel provides a complete code development environment using assembler (ASM-96) as
well as high-level languages such as Intel's iC-96 or PL/M-96 to, accelerate development
schedules.
The evaluation board is hosted on an IBM PC·· or BiOS-compatible clone, already a
standard development solution in most of today's engineering environments. The source
code for the on-board monitor (written in ASM-96) is public domain. The program is
about 1K, and can be easily modified to be included in the user's target hardware, In this
way, the provided PC host software can be used throughout the development phase.

FULL SPEED EXECUTION
The EV80C196KC executes the user's code from on-board ROMsim at 16 MHz with zero
wait-states. By changing crystals on the 80C196KC any slower execution speed can be
evaluated. The boards host interface timing is not affected by this crystal change.

24K BYrES OF ROMSIM
The board comes with 24K bytes of SRAM to be used as ROMsim for the user's code and
as data memory if needed. 16K bytes of this memory are configured as sixteen bits wide,
and 8K bytes are configured as eight bits wide. The user can therefore evaluate the speed
of the part executing from either buswidth.

FLEXIBLE MEMORY DECODING
By changing the Programable Logic Device (PLD) on the board, the memory on the board
can be made to look like the memory system planned for the user's hardware application.
The PLD controls the buswidth of the 80C196KC and the chip-select inputs on the board.
It also controls the number of wait ~ates (zero to three) generated by the 80C196KC
during a memory cycle. These feafures can all be selected with 256 byte boundaries
of resolution.

TOTAtLY CMOS BOARD
The EV80C196KC board is built totally with CMOS components. Its power consumption
is therefore very low, requiring 5 volts at only300 rnA. If the on board LED's are
disabled, the current drops to only 165 rnA. The board also requires + 1- 12 volts at
15mA.

CONCURRENT INTERROGAT10N OF MEMORY AND REGISTERS
The mo~itor for th~ EV80C196KC allows the user to read and modify internal registers
and ext~rnal memory while the user's code is running in the board,

SIXTEEN SOFTWARE BREAKPOINTS
There are sixteen breakpoints available which automatically substitute Ii TRAP
instruction for a user's instruction at the breakpoint location. The substitution occurs
when execution is started. If the code is halted or a breakpoint is reached, the user's cod~
is restored in the ROMsim:
,

5·133

HIGH LEVEL LANGUAGE SUPPORT
The host software for the EV80C196KC board is able to load absolute object code
generated by ASM-96, iC-96, PL/M-96 or RL-96 all of which are available from Intel.

SYMBOLIC DEBUG
The host has a Single Line Assembler, and a Disassmbler, wl;1ich recognize symbolics
.
generated by Intel software tools.

RS-232-C COMMUNICATION LINK
The EV80C196KC communicates with the host using an Intel 82510 DART provided on
board. This frees the on-chip DART of the 80C196KC for the user's application.

PERSONAL COMPUTER REQUIREMENTS
The EV80C196KC Evaluation Board is hos~ed on an IBM PC, XT, AT** or BIOS
compatible clone. The PC must meet the following minimum requirements:
•
•
•
•
•
•

512K Bytes of Memory
One 360K Byte floppy Disk Drive
PC DOS** 3.1 or Later
A Serial Port (COMI or COM2) at 9600 Baud
ASM-96, iC-96 or PL/M-96
A text editor such as AEDIT

RS-232
BUFFERS

80C196K~

CPU
II-----...,Txd
~'-------I Rxd

ADDRESS

82510

UART
DIGITAL I/O

CONTROL

.Block Diagram of the 80C196KC Board

5-134

MCS®-96 Development
Support Tools

_IJ1TMSOFTWARE----

ACEi9lP'M SOFTWARE MAKES YOU AN ARCHITECTURAL WIZARD
··-INSTANTLY.
If you want to learn 80C196KB architecture as fast as possible, so that you can
develop hardware and software in parallel, Intel has the perfect solution.
We call it ACE 196TlII Software.
\

PC·BASED SOFTWAR~ TRAINING SPEEDS LEARNING
ACE196™ Software is a PC·Based Expert System that uses artificial intelligence
technology and your PC's high-resolution monitor to guide you through detailed
..
documentation training.
Its ~asy to use and highly graphic, designed to speed up your learning curve - and
. reduce your total design time, no matter what level ofMCS-96 experience you have.
ACE196TlII Software includes:
• A hypertext manual
, . Peripheral design modules
• An assembler editor
It uses "Hypertext" to efficiently present 80C196KB documentation by providing
·highlighted links to related topics. You can follow these links several layers into the
documentation - without having to search through hundreds of cross-referenced
pages.

CONCENTRATE ON APPLICATIONS INSTEAD OF BIT·BY·BIT
PROGRAMMING
After learning the basics of the architecture, you can use the ACE 196Tl11 desigil.
module to program peripherals. So, you can concentrate on application needs versus
bit by bit programming materials. You'll save design time and minimize
programming errors.
Also, ACE196TlII Software generates fully commented initialization code and features
scoreboards to document just how each peripheral has been programmed.
ACE196TlII Software's Assembler editor makes you syntax-literate right away. It
provides templates of over 100 instructions, on line help and automated register
programming and testing.
$ystem requirements: IBM compatible XT or AT**, EGA Monitor, hard disk. 1.2 meg·
floppy drive, 640K memory.

inter~~__~~·.___
. ___.__. _.______ ~_.. _______~_____\_ _
*IBM PC, XT, AT and DOS are registered trademarks of InternatlOnal Business Machines Corporation
Intel CorporatIOn assumes no responSIbility for the use of any cirCUItry other than cirCUItry embodies In an Intel
product. No other Circuit patent licenses are lmplIed InfonnatlOll contamed herem supersedes preVIOusly pubhshed
specifications on these devi«es from Intel

6-1

18096/196 SOFTWARE DEVELOPMENT' PACKAGES 1

280799-1

COMPLETE SOFTWARE DEVELOPMENT SUPPORT FOR THE
8096/196 FAMILY OF MICROCONTROLLERS
Intel supports application development for its 8096 and 80C196 family of
microcontrollers with a complete set of development languages and utilities. These tools
include a macroassembler, a PL/M compiler, a C compiler, linker/relocator program,
floating point arithmetic library, a librarian utility, and an object-to-hex utility. Develop
code in the language(s) you desire, then combine object modules from different languages
into a single, fast program.

FEATURES
• Software Tools support all members of
Intel's MCS®-96 family
• ASM-96/196 macroassembler for speed
critical code
• PL/M-96/196, packag~ for the
maintainability and reliability of a highlevel language with support for many
low-level hardware functions
• iC-961196 package for structured C
language programming, with many
hardware specific extensions
• Linker/Relocator program for linking
modules generated in assembler, PL/M
or C and assigning absolute addresses to
relocatable code. RL-96 prepares your

code for execution in target with a
simple, one-step operation
• 32-bit Floating Point Arithmetic Library
to reduce your development effort and to.
allow fast, highly optimized numerics,
intensive processing
• Library utility for creating and
maintaining software object module
libraries'
.
• PROM building utility that converts
object modules into standard
, hexadecimal format for easy download
into a non-Intel PROM Programmer
• Hosted on IBM PC XTI AT with PC-DOS
3.0 or above
6-2

November 1990
Order Number: 280793-001

intJ
.FEATURES
Create and

Molntaln
Llbrories WIth

Compile
WIth

Lli6'

VLSICE-96
ICE 196 PC

I
Include

rloatlng Point
LibrarIes With
280793-2

Figure 1. MCS®-96 Application Development Process

ASM·961196 MACROASSEMBLER

• Built-in functions. PL/M-96/196 includes

ASM-96/196 is the macroassembler for the
MCS-96 family of microcontrollers, incJuding
the 8OC196. ASM-96/196 translates symbolic
assembly language mnemonics into relocatable
object code.
The macro facility in ASM-96/196 saves
development and maintenance time, since
common code sequences need only be
developed once. The assembler also supports
symbolic access to the many features of the
8096/196 and provides an "include" file with
all 8096/196 registers defined.

•

PLIM·961196 SOFTWARE
PACKAGE
•

PL/M-96/196 is a high-level programming
language designed to support the software
requirements of advanced 16-bit
microcontrollers. The PL/M-96/196 compiler
translates PL/M high-level language
statements into 8096/196 relocatable object
code. Major features of the PL/M-96/196
compiler include:
• Structured programming. The PL/M
language supports modular and structured
programming, making programs easier to
understand, maintain, and debug.

•

6-3

an extensive list offunctions, including
TYPE CONVERSION functions, STRING
manipulations, and functions for
interrogating MCS-96 hardware flags.
Interrupt handling. The INTERRUPT
attribute allows you to define interrupt
handling procedures. The compiler generates
code to save and restore the program status
word for INTERRUPT procedures.
Compiler controls. Compile-time options
increase the flexibility ofthe PL/M-961196
compiler. These controls include: _
optimization, conditional compilation, the
inclusion of common PL/M source files from
disk, cross-reference of symbols, and optional
'assembly language code in the listing file ..
Data types. PL/M-96/196 supports seven
data types, allowing PL/M-96/196 to perform
three different kinds of arithmetic: signed,
unsigned, and floating point.
Language compatibility. PL/M-96/196
object modules are compatible with all other
object modules generated by Intel MCS-96
translators.

I. FEATURES
'iC-961196 SOFTWARE PACKAGE
Intel's iC-96/196 is a structured programming
language designed to support applications for
the 16-bit family of MPS-96 microcontrollers.
iC-96/196 implements the C language as
describe,d in the Kernighan and Ritchie book,
The C Programming Language, and includes
many of the enhancemen~ as defined by the
proposed ANSI C standard. Major features of
the iC-96/196 compiler include:
• Symbolics. The iC-96/196 compiler boosts
. programmer productivity by providing
extensive debug information, including
symbols. The debug information can be used
to debug the code using either the VLSiCE-96
emulator or the ICETM_196PC emulator.
• Architecture Support. iC-96/196 generates
cOde which is fully optimized for the MCS-96
architecture. iC-96/196 provides an
.INTERRUPT attribute, allowing you to
define interrupt handling functions in C, and
library routines which allow you to enable
and disable interrupts directly from C (mid1989). A REENTRANT/NOREENTRANT
control is alsq included, allowing the
compiler to identify non-reentrant
procedures. This gives you full access to the
large MCS-96 register !let.
• Standard language. iC-96J196 accepts
standard C source code. iC-96/196 code is
fully linkable with both PLlM-96/196 and .
ASM-96/196modules via an "alien"
attribute, allowing programmers to utilize
the optimallangilage for any appljcation. In
addition, programmers can quickly begin .
program~ing with iC-96/196 because it
conforms to accepted C language standards.
R~96/19.6 L{NKER/RELOCATOR

Intel's RL-196 utility is used to link multiple
MCS-96 object modules into a single program
and then assign absQIute addresses to all
relocatable addresses in the new program.

Modules can be written in ASM-96/196,
PL/M-96/196, or iC-96/196. The RL-96/196
lltility also promotes programmer producti~ity
by ~ncouraging modular programming.
Because applications can be broken into
separate modules, they're easier to design, test
and maintain. Standard modules can be reused
in different applications, saving software
development time.
FPA~96/196 FLOATING POINT

ARITHMETIC UBRARY

FPAL-961 1~6 is a library of single-precision 32bit floating point arithmetic functions. These
functions are compatible with the IEEE
floating point standard for accuracy and
reliability and include an error-handler
.
.library.

UB-96/196
The Intel LIB-96/196 utility creates and
maintains libraries of software object modules.
Standard modules can be placed in a librllry,
and linked into your applications programs
using RL-96/196.

OH-£!6/196 .
The OH-96/196 utility converts Intel OMF-96
object modules into standard hexadecimal
format. This allows the code to be loaded
directly into a P~OM via non-Intel PROM
'Programmers.

SERVICE, SUPPORT, AND
TRAINING
.
Intel augments its 'MCS-96 architec~ure family
development tools with a full array of
seminars, classes, and· workshops; on-site
consulting services; field application
engineering expertise; telephone hot-line
support; and software and hardware
maintenance contracts. This full line of
services will ensure your design success.

ORDERING lNFORMATIONI
D86ASM96* 961196 Assembler for PC XT or
D86C96·
iC-96/196 Software package fQr
AT system (or compatible),
PC XT or AT system (or
.
running DOS 3.0 or higher
compatible), ru~ing.DOS 3.0 or
higher.
. .
D86PLM96" PL/M-96/196 Software Package
for PC XT or AT system (or
compatible), running DOS 3.0 or
higher'
•i\Jso I~cludes: Relocator/LiDke~, Objecf;.to-hex converter, Floating Point Arithmetic Library, and Librarian.
6-4

VLSiCETM-96 IN-CIRCUIT EMULATOR

280794-1

IN-CIRCUIT EMULATOR FOR THE 8X9 X FAMILY OF
MICROCO!VTROLLERS
I
The VLSiCETM-96 emulator is a complete hardware/software debug environment for
developing systems based on the Intel 8 X 9 X family of microcontrollers. The VLSiCE-96
emulator supports all NMOS members ofIntel's MCS-96 microcontrollers, including the
8096BH, the 8098, the 8095, the 8097, and the 8096-90. With high performance 12 MHz
emulation, symbolic debugging, and flexible memory mapping, the VLSiCE-96 emulator
expedites all stages of development: software development, hardware development,
system integration: and system test.

FEATURES
• Real-time transparent emulation, up to
12 MHz
• 64K of mappable memory to allow early
software debug and (EP)ROM
simulation, even before any target
hardware is available
• Trace contains execution address,
opcode, symbolics, and bus information
• 4K frame trace buffer for storing realtime execution history
• Ability to break. or trace on execution
addresses, opCodes, data values, or flags
values

• Symbolic debugging for faster and easier
access to memory location and program
variables
• Fast breaks and dynamic trace to allow
the user to modify and interrogate
memory, and access the trace buffer
without stopping emulation
• On-line Help me to speed development
• Shadow Registers can read many writeonly registers and write to many readonly registers, allowing enhanced
debugging over component features

,
November 1990
Order Number: 280794-001

inter
FEATURES
~ Includes 68-pin PGA adaptor; optional 68-pin
I;'LCC and 48-pin DIP adaptors are, also
available
'
• Serially hosted on IBM PC AT/XT or
compatibles with DOS 3.0 or greater

ONE TOOL FOR ENTIRE

simply added to the prototype and tested in
real-time. When the prototype is complete, it is
tested with the final version ,of the system
software. The VLSiCE-96 emulator'can then be
used'to verify or debug the target system as a
completed unit.

DEVELO~MENTCYCLE '
The VLSiCE-96 emulator speeds target system
develOPment by allowing hardware and
software design to proceed simultaneously;
'You can develop software even before
prototype hardware is finished. And becauB,e'
the VLSiCE-96 emulator precisely matches the'
component's electrical and timing
,
characteristics, it's a vaLuable tool for
hardware development and debug.
The VLSiCE-96 emulator also s~plifies and
expediteS system .integratjonand, test. As each
section o( the hl:\rdware is completf;!(i, 'it is
,.

Because it SUPPOrtB the ROMlelillil, ROM and
EPROM versions ofIntel's microcontrollers,
the VLSiCE-96 emulatOr can debug a prototype
or production product at any stage in its
development without introdUcing extraneous
hardware or software test tools.

" , ',",'

6-6

inter
SPECIFICATIONS

HOST REQUIREMENTS
An IBM PC AT/XTor compatible with 512
Kbytes RAM and hard disk. Intel recommends
an IBM PC AT or compatible with 640 Kbytes
of RAM, one floppy drive and one hard disk
running PC-DOS 3.1 or later.
SYBtem Performance
Mappable to user
l\:Iappable zero wait
state (up to 12 MHz), memory or ICE
memory in 1K blocks
Min 0 Kbytes, Max
on 1K boundaries
64 Kbytes
4 Kbytes X 48 bits
Trace Buffer
Virtual Symbol Table A maximum of61
Kbytes of host memory
space is available for
the virtual symbol
table (VST)._ The rest of
the VST resides on disk
and is paged in and out
of host memory as
needed.

Electrical CharacteriBticB
Power Supply
100V -120V or 200V -240V (selectable)
50Hz-60Hz
2 amps (AC max) @ 120V
1 amp (AC max) @ 240V
PhYBical CharacteriBticB
Controller Pod
Width:
8'1." (21 cm)
Height: 1'/." (4 cm)
Depth:
13'1." (34cm)
Weight: 4lbs (2 kg)
Power Supply
Width:
7%" (18 cm)
Height: 4" (10 cm)
Depth:
11" (28 cm)
Weight: 15 lbs (7 kg)
User Cllble: 3' (1 m)

Vee BOOSTER MODULE

USER
CABLE

POWER
SUPPLY

TARGET
ADAPTER

280794-2

Figure 1. The VLSiCE·96™ Emulator
6-7

intJ
SPECIFICATIONS

.0. . . ·

68 PIN
PLCC ADAPTOR

.~.

PIN 1

,
!
"-+ •

.:
:

.!•

.:
:

: ................. =

~1~L3"
yyyyyyyyyyy .

,.."

1
C

,.."

68 PIN PGA
ADAPTOR

......
PIN 1 ::
.......... ::...
L. ...........

......

!.-.J

48 PIN DIP
ADAPTOR

3.2"

-4.8"---1.1

PIN 1

II---'

280794-3

Figure 2. Dimensions for the Emulator Processor Board and Adaptors

Environmental Characteristics
Operating Temperature: O°C to + 400C ( - 32"F
Operating Humidity:

to + 104°F)
.
Maximum to 85%
relative humidity,
non-condensing

SERVICE SUPPORT AND
TRAINING
Intel augments its MCS-96 architecture family
development tools with a full array of .
seminars, classes and workshops; on-site
consulting services; field application
engineering expertise; telephone hot-line
support; and software and hardware
maintenance contracts. This full line of
services will ensure your design success.

6-8

ORDERING INFORMATION
V096-KITA

VLSiCE-96 Power supply
cable, emulation base, user
cable, Crystal Power Accessory
(CPA), serial cables for PC AT I
XT,a 68-pin PGA target
adaptor, ASM-96, AEDIT Text
Editor. Host, probe,diagnostic
and tutorial software OQ 5,/••
. . media for DOS hosts running
. DOS VS.O or later. (Requires
software license.)
.
V096KITD
Same as V096KITA withou~
ASM-96 and AEDIT text
editor.
TA096E
Optional 68-pin PLCC Target
Adaptor Board
Optional 48-pin DIP Target
TA096B
Adaptor Board
Optional Multi-Synchronous
MSA96
Accessory for multi-ICE
capability

Software for host, pr~be,
diagnostic and tutorial on 5'/."
media for use with the PC AT I
XT under PC-DOS VS.O or
later. (Requires software
license.) (Included with
V096KITA and V096KITD.)
D86C96NL
C-96Compiler·
D86PLM96NL PL/l'rf-96 CoI;npiler·
D86ASM96NL ASM-96 Macroassembler·

SA096D

• Also Includes: Relocator/Linker, object-tp-hex converter,
librarian, and Floating Point Arithmetic· Library. .

6-9

REAL-TtME TRANSPARENT 80C196 IN-CIRCUIT
EMULATOR

280127-1

REAL-TIME TRANSPARENT 80C196 IN·CIRCUIT EMULATOR
The ICETM-196KB/PC in-circuit emulator delivers real-time high-level debugging
capabilities for developing, integrating and testing 80C196-based designs. Operating at
the full speed of the 8OC196KB microcontroller, the ICE-196KB/PC provides precise 110
pin timings and functionality. The ICE-196KB/PC also allows you to develop code before
prototype hardware is available. The in-circuit emulator represents a low-cost
development environment for designing real-time r.aicrocontroller-based applications
with minimal investment in time and resources.

ICETM·196KBIPC IN·CIRCUIT EMULATOR FEA'rURES
• Real-Time Emulation ofthe 80C196KB
Microcontroller
;, 64K Bytes of Mappable Memory
• 2K-entry Trace Buffer
• 3 Breakpoints or 1 Range Break

• Symbolic Support and Source Code
Display
• Standalone Operation
• Versatile and Powerful Host Software
• Hosted On IBM PC, XT, AT, or
Compatibles With DOS 3.x

6-10

November 1990
Order Number: 280727-004

FEATURES
REAL-TIME EMULATION
The ICE-196KB/PC provides real-time
emulation with the precise input/output pin
timings and funCtions across the full operating
frequencies of the 8OC196KB microcontroller.
The ICE-196KB/PC connects to the intended
8OC196KB microcontroller socket via a 16"
flex cable, which terminates in a 68-pin PLCC
probe.

MAPPABLE MEMORY
The ICE-196KB/PC has 64K bytes of ze.ro waitstate memory that can be enabled or mapped
as read-only, write-only or read/write in 4K
byte increments to simulate the internal
(EP)ROM ofthe 80C196KB or external
program memory.

TRACE BUFFER
The ICE-196KB/PC contains a 2K entry trace
buffer for keeping a history of actual
instruction execution. The trace buffer can be
conditionally turned off to collect a user
specified number of trace frames. Trace
information can be displayed as disassembled
instructions or, optionally, disassembled
instructions and the original iC-96 and
PL/M-96 source code.

BREAK SPECIFICATION
Three execution address breakpoints or one
range of addresses can be active at any time.
The ICE-196KB/PC allows any number of
breakpoints to be defined and activated when
needed.

SYMBOLIC SUPPORT AND
SOURCE CODE DISPLA Y
Full ASM-96, PL/M-96 and iC-96 language
symbolics, including variable typing and scope,
are supported by the rCE-196KB/PC memory
accesses, trace buffer display, breakpoint
specification, and assembler/disassembler.
Additionally, iC-96 and PL/M-9~ source code
can be displayed to make development and
debug easier.

STANDALONE OPERATION
Product software can be developed prior to
hardware availability with the optional
Crystal Power Accessory (CPA) and the
ICE-196KB/PC mappable memory. The CPA
also provides diagnostic testing to assure full
functionality of the ICE-196KB/PC.

VERSATILE AND POWERFUL
HOST SOFTWARE
The ICE-196KB/PC comes equipped with an
on-line help facility, a dynamic command
entry and syntax guide, built-in editor,
assembler and disassembler, and the ability to
customize the command set via literal
definitions and debug procedures.

HOSTING
The ICE-196KB/PC is hosted on the IBM PC·
XT, AT or compatibles with PC-DOS 3.x.

inter
SPECIFICATIONS
REQUIREMENTS"'
, Host
IBM PC XT, AT (or compatjble)
2K bytes RAM, Hard Disk
PC·DOS3.x
One Unused Peripheral Slot
DC Current 2.5A
Note: ICE·196KB/PC uses two bytes ofthe user
stack.

TARGET INTERFACE BOARD

ENVIRONMENTAL
CHARACTERISTICS
operating Temperature 10·C to 40·C
37.5·F to 104°F
Operating Humidity
Maximum 55%
Relative Humidity,
non-condensing

ORDERING INFORMATION
Order Code
ICE196KBPC

Description
Emulation
Board, user.
Length 2.0" (5.1cm)
cable, target interface
Height 1.2" (3.0cm)
board (PLCC), host,
Width
2.3" (5.8cm)
diagnostic, and tutorial
software on 5 'I." DOS
USER CABLE
diskette, and Crystal
Power Accessory with
Length 15.6" (39.6cm)
power cable
PROBE ELECTRICAL
. ICE196KBPCB
Same as above except
does not include Crystal ,
80C196KB plus per pin . 50 pf loading
Power Accessory
5ns propagation delay
CPA196KAKB
Crystal Po~er Accessory
Icc (from target system) 50 rnA @ 12 MHz
and power cable only
Operating Frequency 3.5 to 12 MHz,
TA196PLCC68PGA 68-Pin PGA Target
12 MHz only with
Adaptor
CPA

6·12

ICETM_196KB/HX IN~CIRCUIT EMULATOR

280847-1

MODULAR IN-CIRCUIT EMULATOR FOR THE 8xC196KB
FAMILY OF MICROCONTROLLERS
The ICETM_196KB/HX in-circuit emulator delivers a complete, real.time, hardware/
software debug environment for developing, integrating, and testing 8xC196KB-based
designs. The ICE-l96KB/HX emulator is a high-performance modular debugging system '
featuring real-time and transparent 12 MHz emulation, high-level symbolic debugging,
complete execution and bus break/trace capabilities, 128 Kbytes zero-waitstatE! mappable
memory, and emulation trace. The ICE-196KB/MX emulator, a companion entry~level
system, is also available. The ICE-196KB/MX emulator can be upgraded to an ICE196KB/HX emulator with optional add-in boards. Both systems feature an identical
human interface, utilize the same base chassis, and are serially hosted on IBM PC XTs,
ATs, and 100% compatibles.

JCETM-196KBlxX IN-CIRCUIT EMULATORS CORE FEATURES
• Precisely matches the component's
electrical and timing characteristics
,. Supports the ROMless and (EP)ROM
versions of the 8xCl96KB
• Does not introduce extraneous hardware
or software overhead
• Modular base for future growth and
migration
ICETM and ONCETM are trademarks of Intel Corporation.
. IBM- and PC AT- are registered trademarks of International Busineaa Machine. Corporation.
PC XTTM i. a tradamark of International Busine.s Machines Corporation.

6-13

November 1990
Order Number: 280847-002

inter,
;

ICETM .. 196KB/HX IN.. CIRCUIT EMULATOR
ICETM-196KBIMX IN-CIRCUIT
EMULATOR FEATURES

ICETM-196KBIHX IN-CIRCUIT
EMULATOR FEATURES

• Real-time transparent 8xC196KB emulation
to 12 MHz; inQluding ROM and EPROM
versions, either in-target or stand,alone
• Use of eithertarget system or 64 Kbytes of
zero-waltsta~e emulator memory for program
execution
• Event recognition of up to 255 execution
addre~s specifications, either specific or
ranges"
"
• Fastbreaks; wherein emulation is
immediately broken only for the 'duration of
a requested memory access
• Single-step execution of machine
instructions, high-level language statements,
or procedure call blocks
• Execution trace, 2K frames deep, including
address, opcode in hex and mnemonic
formats, and operands in hex and symbolic
formats
'
• Functions to disassemble/ assemble memory
in the form of machine instructions and to
display/modify program variables iind
specialfunCtioJ;1 registers
• Symbolicrefere,ncing to memory locations
and microcontroller objects and the output of
symbolic information in trace and memory
disassembly displays
• Automatic display of source statements
when memory is disassembled, the trace
buffer is displayed, or emulation is broken
• Automatic update of selected variables
displayed in a Watch Window
• Dynamic display of the trace buffer during
emulation
• A command line user interface with contextsensitive hlillp in pop-up windows
• User-definable function keys and procedures
with variables and literal definitions
• On-circuit emulation of surface mount
components
• An emulation timer returning the ,time from
entering until leaving emulation
• Synchronized multi-emulator start and
break and a trigger out for synchronization
with external logic analyzer or other device

Includes all features of the ICETM.196KBI
MX emulator plus the following;
• Recognition of bus events (either instruction
fetch, data read or write at a specific address
or range of addresses, or a specific value or
range of values)
• OR combinations of execution/bus events or
strictly bus events, plus AND combinations
of bus events
• Event counters
• Conditional arming and disarming of break
specifications
• A deferred Fastbreak option whereby
emulation is broken only after reaching a
sp~cified address
,
• Additional 64 Kbytes (128 Kbytes total) of
zero-waitstate emulation memory
• The addition of bus address/data, processor
status bits, and logic clips information in the
trace buffer
• Conditional arming and disarming of trace
specifications
'
• Reprogrammability of break and trace
specifications during emulation
• Eight logic clips input lines may be used to
trigger an action and are captured in the
trace buffer
• Qualification of events with an external
input SYSIN line
• Asynchronous break based on a signal from
an external device
• Eight logic clips output lines are settable to
simulate a condition in the target system
• SYSOUT output may be used to stimulate an
action in the target system based on a
recognized event
• An event timer calculating time between
specified conditions

6-14

inter
ICETM·196KB/HX IN· CIRCUIT EMULATOR,
FEATURE COMPARISON OF INTEL'S axC196KB IN·CIRCUIT
EMULATORS
Re~-time,

transparent

Hosting
Expandable/U pgradable
Mapped Memory (bytes)
Trace Buffer (frames)
Execution Breaks
Breakpoints
Fastbreaks
Bus Break/Trace
Complex Break/Trace Events
Reprogrammable Break/Trace
'Symbolic Debug
Source Code Display
Watch Windows
Dynamic Trace Display
Emulation Timer
Event Timer
Logic Analysis Clips
Multi-ICE Support

ICETM·196KB/PC
Yes
PCXTBus
No
64K
2K
Yes
3
No
No
No
No
Yes
Yes
Yes
No
No
No
No
No

COMPLETE FAMILY OFax196
DEVELOPMENT TOOLS
ICE-196KB/MX and ICE-196KB/HX
emulators are complemented by Intel's lowcost ICE-l96KB/PC emulator. All three
emulators utilize an upward-compatible
human interface to preserve your learning
investment and to allow multiple emulators
for large design teams. Each emulator has
been designed to work'in conjunction with
Intel's MCS-96 software tools, including a
macro assembler, a PL/M-96 compiler, an iC96 compiler, and various utilities.
Optional boards are available to upgrade an
ICE-196KB/MX emulator with some or a:ll of
the functionality of an ICE-196KB/HX

ICE-196KB/MX
Yes
PC XT, AT Serial
Yes
64K
2K '
Yes
255
Abrupt only
No
No
No
Yes
Yes
Yes
Yes,
Yes
No
No
' Yes

ICE·l96KB/HX
Yes
PC XT, AT Serial
Yes
128K
2K
Yes
255
Yes,
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Enhanced'

emula~or. In addition, the ICE-l96KB/MX and
ICE-196KB/HX. emulators have been designed
to support future proliferations within the '
8xC196 family of microcontrollers.

WORLDWIDE SERVICE AND
SUPPORT
Intel augments its MCs-96 architecture family
development tools with a full array of
seminars, classes, and workshops; on-site
consulting services~ field application
engineering expertise; telephone hot-line
suppOrt; and software and hardware
maintenance contracts. This full line of
, services will ensure your design- success.

6-1-5

I· SPECIFICATIONS' I
'HOSTREQUIREMENTS,

• ONCE support: If ONCE (on-circuit
emulation) mode is selected, the RD# and
INSr pins are driven low while RESET# is
active (low).

Emulators require an IBM PC AT, XT, or
100% compatible with 512 Kbytes RAM and
hard d~ running DOS 3.x.

PROCESSOR MODULE
DIMENSIONS-

ELECTRICAL
CHARACTERISTICS
Power SUpply: 1OOV-120V or 200V-240V
50Hz-60Hz
5 amps (AC max) @ 120V
2 amps (AC max) @ 240V

lIT.'"
'3J~
L
II08T

ELECTRICAL
CONSIDERATIONS

TARGET INTERfACE BOARD

The emulator processor's user-pin timings and
loadings are identical to the 8xC196KB
component except as follows:
• Additional pin capacitance:
Target interface board (TIB) Approximately
12pf
'
(30pf
maximum)
Pin 32 (Pl. 7/HOLD # )
Approximately
70pf
Pin 43 (READY)
Approximately
70pf
Pins 6 (RD # )
Approximately
60pf
Pin 63 (INST)
Approximately
60pf
Pin 16 (RESET #)
Approximately
.
325pf
All pins when using ~ hinge 10pf
cable
• DC loading: Pin l(VCC) can draw an
additional 5 mA (15mA worst case @ 5.5V)
due to power, sensing circuitry.
Sensing,circuitry may also draw
approximately ± O.lmA (± 0.4 mA
maximum) DC current from any 8xC196KB
output pin.
• AC timings:
Pin 32 (P1.7/HOLD#)
Pin 43 (READY)
Pin 63 (INST) if jumper
El-Ji:3 is installed
Pin 16 (RESET '#)

PLCCPROBE

280847-2

PHYSICAL CHARACTER!STICS
Target Probe
Width:
Height:
Length:
Package:

6.9 cm (2.7" )
3.0 cm (1.2" )
11.0 cm (4.3")
68-pin PLCC (optional 68-pin PGA
ad~ptor available)

Emulator Chassis
Power Supply
Width: 34 cm (13%") Width: 18 cm (7Ya" )
Height: 12cm(4%") Height: lOcm(4")
Depth: 28 cm (10%") Depth: 28 cm (U" )
Weight: 3.2 kg (7Ib)
Weight: 7 kg (15Ib)
Probe Cable Length: 40 cm (17")
Serial Cable Length: 3.65 m (12')

ENVIRONMENTAL '
CHARACTERISTICS'
Operkting Temperature: O"C to 40"C
Operating Humidity:
Maximum 85%
,
relative humidity,
non-condensing

Degraded Ins
Degraded Ins
Degraded Ins
Degraded 15ns

. I
6-16

ORDERING INFORMATION
ICE196KBHX

ICE196KBMX.

ICE in-circuit emulator
base chassis, 196
emulation control board
(ECB), 196KB target probe,
196KB crystal power
accessory (CPA), enhanced
break/trace board (BTB),
64K optional memory
board (OMB), clips in/out,
power supply and cable,
serial cables for PC XT /
AT, 68-pin PLCC target
adapter. Host, 196KB
probe, diagnostic, and
tutorial software on 5Y4·
media for DOS hosts
running DOS a.x.
(Requires software
license.)
Same as ICEl96KBHX
except ~thout enhanced
break/trace board (BTB),
without 64K optional
memory board (OMB), and
without clips in/out

ICEBTB

Enhanced break/trace
board (BTB) for upgrading
an ICE-l96KB/MX
system
ICEOMB
Optional memory board
with 64K zero-waitstate
mapped memory for
upgrading an ICE-l96KB/
MXsystem
ICECLIPS
Clips in/out for upgrading
an ICE-196KB/MX
system (requires an
enhanced break/trace
board)
ADPTCA68PGA
Hinge cable for 68 pin
PGA component
packaging
ADPTCA68PLCC Hinge cable for 68 pin
PLCC component
packaging
ADPTONC68PLCC Adaptor to support 68 pin
PLCC component
packaging ONCE (oncircuit emulation)

6-17

Memories Data Sheet

·'i

87C257
256K (32K x 8) CHMOS EPROM
•

CHMOS/NMOS Microcontroller and
Microprocessor Compatible
- 87C257-1ntegrated Address Latch
- Universal 28 Pin Memory Site, 2-line
Control
.

•

Low Power Consumption

•

High Performance Speeds,
-150 ns Maximum At:cess Time

•

Noise Immunity Features

- ± 10% Vee Tolerance
- Maximum Latch-up Immunity
Through EPI Processing
•

New Quick-Pulse Programming™
Algorithm
- 4 Second Programming

• . 28-Pin Cerdip and 32-Lead PLCC
Packages
(See Packaging Spec., Order # 231369)

Intel's 87C257 EPROM is a 5V-only, 262,144-bit Erasable Programmable Read Only Memory, organized as
32,768 words of 8 bits. It employs advanced CHMOS*III-E circuitry for systems requiring low power, high
speed performance, and noise immunity. The 87C257 is optimized for compatibility with multiplexed address/
data bus microcontrollers such as Intel's 16 MHz 8051- and 8096- families.
The 87C257 incorporates latches on all address inputs to minimize chip count, reduce cost, and simplify
design of multiplexed bus systems. The 87C257's internal address latch allows address and data pins to be
tied directly to the processor's'multiplexed address/data pins. Address information (inputs Ao-A14) is latched'
early in the memory-fetch cycle by the falling edge of the ALE input. Subsequent address information is
ignored while ALE remains low. The EPROM can then pass data (from pins 00-07) on the same bus during
the last part of the memory-fetch cycle.
The 87C257 is offered in ceramic DIP (CERDIP) and Plastic Leaded Chip Carrier (PLCC) packages. The
CERDIP package provides flexibility in prototyping and R&D environments while the PLCC version is used.in
surface mount and automated manufacturing. The 87C257 employs the Quick-Pulse Programming™ Algorithm for fast and reliable programming.
'CHMOS is a patented process of Intel Corporation.

DATA OUTPUTS
0 0-0 7

cr
ALE

OUTPUT ENABLE
PROG LOGIC

OUTPUT BUffERS

CHIP ENABLE
ADDRESS LATCH ENABLE

Y DECODE

Y-GATING

)( DECODE

262,144 BIT
CELL MATRIX

:x:
~

Ao-A I4
ADDRESS
INPUTS

VI
VI

w·

'"g
...:

290135-1

Figure 1. Block Diagram

7-1

September 1990
Order Number: 290135-007

inter

Q7'C257

Pin Names

87C257

ALE/Vpp

vee

A11
A7

A14
A13
As
,AI

Ao-AI4

ADDRESSES

00-0 7

OUTPUTS

OUTPUT ENABLE

CHIP ENABLE

ALE/vpp

ADDRESS LATCH
ENABLE/vpp

As
A4

NO CONNECT

DON'T USE

A11
OE

AI
A2
A1
Ao
00
01
02

A10

fE
07
06
0&
04
03

OND

290135-2

Figure 2, DIP Pin Configuration

N87C257

All

32 LEAD PLCC

0.450" X 0.550"
(11.430 X 13.970)
(MILLIMETERS)

AIO

,11

°7

TOP VIEW

290135-13

Figure 3. PLCC Lead Configuration

7·2

87C257

EXTENDED TEMPERATURE
.
(EXPRESS) EPROMs
The Intel EXPRESS 'EPROM family receives additional processing to enhance product characteristics. EXPRESS processing is available for several
densities allowing the appropriate memory, size to
match system requirements. EXPRESS EPROMs
are available with 168 ± 8 hour, 125°C dynamic
burn-in using Intel's standard bias configuration.
This processing meets or exceeds most industry
burn-in specifications. The EXPRESS product family
is available in both O°C to + 70°C and - 40°C to
+ 85°C operating temperature range versions. Like
all Intel EPROMs, the EXPRESS EPROM family is
inspected to 0.1 % electrical AQL. This allows reduction or elimination of incoming testing.

EXPRESS EPROM FAMILY

290135-4
5V R = 1 Kil vee = + 5V
ALElVpp = + 5V GND = OV CE = GND

OE =

OPTIONS
Packaging

Speed

CERDIP

PLCC

-200V10

AO.nJLS
Al..JLf
•

PRODUCT DEFINITIONS'
Type

Operating
Temperature eC)

Burn-in 125°C
(hr)

O°C to 70°C

168 ±8

- 40°C to 85°C

NONE

-40°C to 85°C

168 ±8

)J.S

•

290135-5

Binary Sequence from Ao to A14

Burn-In Bias and Timing Diagrams

7-3

inter

87C257

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifi.
cations are subject to change without notice.'
.

Operating Temperature .•.......... o·e to 70·e(1)
Temperature Under Bias •..•...••.. - 10°C to 80·e
Storage Temperature .. ,........... '- 65·e to 125·e
Voltage on any Pin
(except A9, Vcc and Vpp)
with Respectto GN D ............. - 2V to 7V(2)
Voltage on A9 with
Respect to GND •.............. :"'2V to 13.5V(2)
Vpp Supply Voltage with
Respect to GND .' .............. - 2V to 14.0V(2)
Vcc Supply Voltage with
Respect toGND ................ -2V to 7.0V(2)

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may Cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended ,exposure beyond the "Operating Conditions"
may affect device reliability.

READ OPERATION DC CHARACTERISTICS(1)
Symbol

Parameter

III

Input Load Current

ILO

Output Leakage Currerit

ISB

Vee Standby Current
with Inputs-

Ice

Vee Operating eurrent

Notes

Min

Vcc = 5 OV

+
- 10%

Typ

Max

Unit

0.01

1.0

p.A

Test Condition

VIN

= OV to 5.5V

±10

p.A

VOUT

Switching

Stable

1.0

los

Output Short Circuit Current

Vil

Input Low Voltage

4.6
-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

100

p.A

100

0.8

Vee

+ 0.5

0.45
2.4

OV to 5.5V

= ALE = VIH
CE = ALE = Vcc ±0.2V
CE = VIH, ALE = Vil
CE = Vee ±0.2v,ALE = GND
CE = Vil. ALE = VIH
f = 5 MHz. lOUT = 0 mA

V
V

10l

10H

= 2.1 mA
= - 400 p.A

NOTES:
1. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS versions. .
2. Minimum DC input voltage is -;-0.5V on input/output pins. During transitions. this level may undershoot to -2.0V for
periods < 20 ns. Maximum DC voltage on input/output pins is Vce + 0.5V which. during transitions. may overshoot to Vee
+ 2.0V for periods < 20 ns.
.
3. Maximum current value is with outputs 00 to 07 unloaded.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Vee must be applied simultaneously or before ALElVpp and removed simultaneously or after ALElVpp.
6. Sampled, not 100% tested.
7. Typical limits are at Vee = 5V. TA = 25'C.

7-4

intJ

87C257

READ OPERATION AC CHARACTERISTICS(1)vcc
Verslons(4)
Symbol
tACC

Vee ±10%

Parameter

Notes

= S.OV ±10%

. 87C257-150V10
N87C257-150V10 .
Min

Address to Output Delay

Max

87C257-200V10
N87C257·200V10
Min

Unit

Max

150

200

tCE

CE to Output Delay

150

200

tOE

OE to Output Delay

tOF

OE High to Output High Z

toH

Output Hold from Addresses, CE or
OE Change-Whichever is First

tLL

Latch Deselect Width

tAL

Address to Latch Set-Up

tLA

Address Hold from LATCH

tLOE

ALE to Output Enable

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to tCE-toE after the falling edge of CE without impact on tCE.
3. Sampled, not 100% tested.
4. Model Number Prefixes: No Prefix = CERDIP, N = PLCC.

AC WAVEFORMS

V1H

ALE
V1L

VIH----of-,~--+~

cr V

OUTPUT

VIH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...!:!!~L_{::§~~~~!£:~~
V1L

290135-6

7-5

87C257

CAPACITANCE(1) TA
Symbol

= 25°C,f =1.0 MH?

Parameter

Max Units Conditions

CIN

Address/Control Capacitance

VIN = OV

COUT·

Output Capacitance

VOUT =; OV

NOTE:
1. Sampled. not 100% tested.

AC INPUT/OUTPUT REFERENCE WAVEFORM

AC TESTING LOAD CIRCUIT

l.:.3~

~ .. lN914
IH
V1L

OUTPUT
RL

DEVICE
UNDER
TEST

290135-7

.I.

CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 KO

AC test inputs are driven at VOH (2.4 VnL) for a Logic
"1" and VOL (0.45 Vnu for a Logic "0". Input timing
begins at 1.5V. Output timing ends at VIH (2.0 Vnu
and VIL (0.8 Vnu. Input rise and fall times (10% to
90%) s: 10 ns.

OUT
CL
290135-S

DEVICE OPERATION
The Mode Selection table lists 87C257 operating modes. Read mode requires a single 5V power supply. All
inputs, except Vcc and ALElVpp, and A9 during inteligent Identifier Mode are TTL or CMOS.
Table I. Mode Selection .
Mode

Notes

ALE/
Vpp

Vee

Read

VIL

Vcc

DOUT

Output Disable

VIL

VIH

VCC

HighZ

Standby

VIH

Vcc

HighZ

VIL

VIH

Vpp

Vcp

DIN

Vpp

Program

Outputs

Program Verify

VIH

VIL

Vcp

DOUT

Optional program
Verify

VIL

Vcp

DOUT

VIH

Vpp

Vcp

HighZ

Vcc

89 H

Vce

24 H

Program Inhibit
intelig~nt Identifier

2,3

VIL

VID

VIL

2,3

VIL

VID

VIH

-Manufacturer
inteligent Identifier
-87C257

NOTES:
1. X can be VIL or VIH.
2. See DC Programming Characteristics for VCP, Vpp and VIO voltages.
3. AI-As, AlO-14 = VIL.

7-6

inter

87C257

Read Mode

Two Line Output Control

The 87C257 has two control functions; both must be
logically enabled to obtain data at the outputs. CE is
the power control and the device-select. DE gates
data to the output pins by controlling the output buffer. When the address is stable (ALE = V'H) or
latched (ALE = V,Ll, the address access time (tACe)
equals the delay from CE to output (tCE). Outputs
display valid data tOE after the falling edge of DE,
assuming tAce and teE times are met.

EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur
To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that oilly selected memory devices have active outputs while
deselected memory devices are in Standby Mode.

The 87C257 reduces the hardware interface in multiplexed address-data bus systems. Figure 4 shows a
low power, small board space, minimal chip
87C257/microcontroller design. The processor's
multiplexed bus (ADo-7) is tied to the 87C257's address and data pins. No separate address latch is
needed because the 87C257 latches all address inputs when ALE is low.

Standby Mode
StandbLmode substantially reduces Vee current.
When CE = V'H, the outputs are in a high impedance state, independent of OE.

ALE controls the 87C257's internal address latch.
As ALE transitions from V'H to V'L, the last address
present at the address pins is retained. OE can then
enable EPROM data onto the bus.

Program Mode

Vee must be applied simultaneously or before
ALE/Vpp and removed simultaneously or after
ALE/Vpp.

vss vee

Caution: Exceeding 14Von Vpp will permanently
damage the device.

Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".

RST

Program Mode is entered when Vpp is raised to
12.75V. Data is introduced by applying an 8-bit word
to the output pins. Pulsing CE low while OE = V'H
programs that data into the device.

290135-9

Figure 4. 80C31 with 87C257
System Configuration

7-7

Program Verify

SYSTEM CONSIDERATIONS

A verify should, be .performed following a program
operation to determine that bits have been correctly
programmed. With Vee at 6.25V, a substantial pro9!!m margin in ensured. The verify is performed with
CE at V,H. Valid data is available tOE after OE falls
low.
.

EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (Iss), active current levels (Icc), and transient
current peaks produced by falling and rising edges
of CE. Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-line control and proper de'coupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 /-,-F ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 /-,-F electrolytic
capaCitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.

Option;al Program Verify
The optional verify allows parallel programming and
verification when several devices share a common
bus. It is performed with CE = OE = V,L and Vpp =
Vee = 6:2.5V. The normal read mode is then used
for program verify. Outputs will tri-state depending
on OE and CEo

Program Inhibit
Program Inhibit Mode allows parallel prQ9!'amming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE and OE, parallel EPROMs may have common
"inputs.

ERASURE CHARACTERISTICS
Erasure begins when EPROMs ilre exposed to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase an
EPROM in approximately 3 years, while it takes approximately 1 week for direct sunlight. If the device
is exposed to these lighting conditions for extended
periods, opaque labels should be placed over the
window to prevent unintentional erasure.

inteligent Identifier™ Mode
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
This mode is activated when a programmer forces
12V ± 0.5V on Ag. With CE, OE, A1-AS and A1OA14 at V'L, Ao = V,L will present the the manufacturer code and Ao = V'r! the device code. When Ag =
VID, ALE need not be toggled to latch each identifier
address. This mode functions in the 25°C ± 5°C ambient temperature range required during programming.

The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537 A . The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 /-,-W/cm 2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258
Wsec/cm 2 (1 week @ 12000 /-,-W/cm2).

7-8

inter

87C257

290135-10

Figure 5. Quick-Pulse Programming™ Algorithm
The entire program-pulse/byte verify sequence is
performed with ALElVpp = 12.75V and Vee =
6:25V.When programming is complete, all bytes are
compared to the original data with Vee = 5.0V.·

Quick-Pulse Programming™ Algorithm
The Quick-Pulse programming algorithm programs
Intel's 87C257. Developed to substantially reduce
programming throughput, this algorithm can program
the 87C257 as fast as four seconds. Actual programming time depends on programmer overhead.

Alternate Programming
Intel's 27C256 and 27256 Quick-Pulse Programming
algorithms will also program the 87C257. Byoverriding a ch~ck for the inteligent Identifier, older or nonupgraded PROM programmers can program the
87C257. See Intel's 27C256 and 27256 data sheets
for programming waveforms of these alternate algorithms.

The Quick-Pulse programming algorithm employs a
100 ,...S pulse followed by a byte verificat.ion to determine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.

7-9

87C257

DC PROGRAMMING CHARACTERISTICS
Symbol

Parameter

. Notes

= 25°C

±5°C

Typ

Min

Max

Unit

Test Condition

III

Input Load Current

/LA

VIN

ICp

Vcc Program Current

Ipp

Vpp Program Current

Vil

Input Low Voltage

-0:2

VIH

Input High Voltage

2.0 .

Val

Output Low Voltage (Verify)

VOH

Output High Voltage (Verify)

VIO

A9 inteligent Identifier Voltage

Vpp

Vpp Program Voltage

VcP

Vcc Supply Voltage Program

1.0

0.8
VCC

+ 0.5

0:4
Vcc - 0.8

V
V

IOl

IOH

11.5

12.0

12.5

2,3

12.5

12.75

13.0

6.0

6.5

AC PROGRAMMING CHARACTERISTICS(4)

·6.25

= Vil or VIH
= Vil
= Vil

= 2.1 mA
= - 400 /LA

TA = 25°C ±5°C

Notes

Min'

tvcs

VCP Setup Time

/Ls

tvps

Vpp Setup Time

/Ls

tAS

Address Setup Time

/LS

tos

Data Setup Time

tpw

CE Program Pulse Width

tOH

Data Hold Time

tOES

OE Setup Time

tOE

Data Valid from OE

tOFP

OE High to
Output High Z

Symbol

tAH

Parameter

. - - r--'

Max

105
-- I - - '

fLs
/Ls

Unit

/Ls
100

5
5,6

Typ

/Ls
150

130

--,- ~-~

Address Hold Time

/Ls

NOTES:

1. Maximum current value is with outputs 00 to 07 unloaded.
.
2. VCP must be aRplied simultaneously or before Vpp and removed simultaned~sly or after Vpp.
.
3. When programming; a 0.1 ,..,F capacitor is required between Vpp and GNO to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference. Waveform for timing measurements.
5. tOE and tOFP are device characteristics but must be accommodated by the programmer.
6. Sampled, not 100% tested.
7. During programming, the addrEjss latch function is'bypassed whenever Vpp = 12.75V or ~g "' VH. When Vpp and Ag are
at TTL levels, the address latch function is enable<;l, and the device functions' in read mode.
8. Vpp can be 12.75V during Blank Check and Final Verify; if so, CE must be VIH.

7-10

inter

87C257

PROGRAMMING WAVEFORMS

V,H

Address V1l. _ _"""_"'::--:=--"""",+-~"':'::'

__"';:;""""';';;=;';";';;;;;;-J}-_ _......;A.;;;D;;,;DR;;;;ES;.;S..;S.;;.TA;;,;BL;;.E+_ _"'n",,"",A;;;;DD;;,;R;;,;ES..;;,S.;.;VA.;;;LI..;;,D-'I~_

Data

12.75V - - - - - - - - - - - ALE/Vpp V,H - -

- - - - - - - - - - - -

- - - - -

--,--....,----1---+-+--....,-+......+----+----..

--,----+------11---'1

tyPS

6.2SV
5.0V

Vee
V..

Ci'

V,H - - - ' - \ .

DE
290135-11

REVISION HISTORY
Number

Description

Revised general datasheet structure, text to improve clarity.
Combined TIL/NMOS and CMOS Read Operation DC Characteristics.
Deleted -250 EXPRESS option.
Added -150 speed bin.
Deleted -170 speed bin.

7-11

DOMESTIC 'SALES OFFICES
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~~IS(~~~)d~~~go
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~~~~m;n2~t~~5~~~g1

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~~~~g~r~~slness Center

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~~~~~~I~r 8'ii~~70

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Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2014:09:15 18:58:07-08:00
Modify Date                     : 2014:09:15 18:44:16-07:00
Metadata Date                   : 2014:09:15 18:44:16-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:7921174e-ffc4-9f44-8dc3-2f0e6cc1314a
Instance ID                     : uuid:76c1640a-12b7-f649-b3d9-71be79719995
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 624

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