1991_Intel_Memory_Products 1991 Intel Memory Products

User Manual: 1991_Intel_Memory_Products

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Intel Corporation is a leading supplier of microcomputer components,
modules and systems. When Intel invented the microprocessor in 1971, it
created the era of the microcomputer. Today, Intel architectures are considered
world standards. Whether used in embedded applications such as automobiles,
printers and microwave ovens, or as the CPU in personal computers, client
servers or supercomputers, Intel delivers leading-edge technology.

MEMORY PRODUCTS

1991

About Our Cover.'
Thinkers, inventors, and artists throughout history have breathed
life into their ideas by converting them into rough working sketches, models,
and products. This series of covers shows a few of these creations, along
with the applications and products created by Intel customers.

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel products:
287, 376, 386, 387, 486, 4-SITE, Above, ACE51 , ACE96, ACE186, ACE196, ACE960,
ActionMedia, BITBUS, COMMputer, CREDIT, Data Pipeline, DVI, ETOX, FaxBACK,
Genius, i, 1, i486, i750, i860, ICE, iCEL, ICEVIEW, iCS, iDBP, iDIS, 12 1CE, iLBX, iMDDX,
iMMX, Inboard, Insite, Intel, intel, Inte1386, intelBOS, Intel Certified, Intelevision, inteligent
Identifier, inteligent Programming, Intellec, Intellink, iOSP, iPAT, iPDS, iPSC, iRMK, iRMX,
iSBC, iSBX, iSDM, iSXM, Library Manager, MAPNET, MCS, Megachassis,
MICROMAINFRAME,
MULTICHANNEL,
MULTIMODULE,
MultiSERVER,
ONCE,
OpenNET, OTP, Pr0750, PROMPT, Promware, QUEST, QueX, Quick-Erase, Quick-Pulse
Programming, READY LAN, RMX/80, RUPI, Seamless, SLD, SugarCube, SX, TooITALK,
UPI, VAPI, Visual Edge, VLSiCEL, and ZapCode, and the combination of ICE, iCS, iRMX,
iSB'C, iSBX, iSXM, MCS, or UPI and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk
Data Sciences Corporation.
CHMOS and HMOS are patented processes of Intel Corp.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FAST PATH trademark or products.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
©INTEL CORPORATION 1990

CUSTOMER SUPPORT
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
Customer Support is Intel's complete support service that provides Intel customers with hardware support,
software support, customer training, consulting services and network management services. For detailed information contact your local sales offices.
After a customer purchases any system hardware or software product, service and support become major
factors in determining whether that product will continue to meet a customer's expectations. Such support
requires an international support organization and a breadth of programs to meet a variety of customer needs.
As you might expect, Intel's customer support is extensive. It can start with assistance during your development
effort to network management. 100 Intel sales and service offices are located worldwide-in the U.S., Canada,
Europe and the Far East. So wherever you're using Intel technology, our professional staff is within close
reach.

HARDWARE SUPPORT SERVICES
Intel's hardware maintenance service, starting with complete on-site installation wiII boost your productivity
from the start and keep you running at maximum efficiency. Support for system or board level products can be
tailored to match your needs, from complete on-site repair and maintenance support to economical carry-in or
mail-in factory service.
Intel can provide support service for not only Intel systems and emulators, but also support for equipment in
your development lab or provide service on your product to your end-user/customer.

SOFTWARE SUPPORT SERVICES
Software products are supported by our Technical Information Service (TIPS) that has a special toll free
number to provide you with direct, ready information on known, documented problems and deficiencies, as
well as work-arounds, patches and other solutions.
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information Phone Service), updates and subscription service (product-specific troubleshootmg guides and;
COMMENTS Magazine). Basic support consists of updates and the subscription service. Contracts are sold in
environments which represent product groupings (e.g., iRMX® environment).

NETWORK SERVICE AND SUPPORT
Today's broad spectrum of powerful networking capabilities are only as good as the customer support provided
by the vendor. Intel offers network services and support structured to meet a wide variety of end-user computing needs. From a ground up design of your network's physical and logical design to implementation, installation and network wide maintenance. From software products to turn-key system solutions; Intel offers the
customer a complete networked solution. With over 10 years of network experience in both the commercial
and Government arena; network products, services and support from Intel provide you the most optimized
network offering in the industry.

CONSULTING SERVICES
Intel provides field system engineering consulting services for any phase of your development ,or application
effort. You can use our system engineers in a variety of ways ranging from assistance in using a new product,
developing an application, personalizing training and customizing an Intel product to providing technical and
management conSUlting. Systems Engineers are well versed in technical areas such as microcommunications,
real-time applications, embedded microcontrollers, and network services. You know your application needs;
we know our products. Working together we can help you get a successful product to market in the least
possible time.

CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering various aspects of system design and implementation. In just three to ten days a limited number of individuals learn more in a single workshop than in weeks of
self-study. For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we
can take our workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course
categories include: architecture and assembly language, programming and operating systems, BITBUS'" and
LAN applications.

DATA SHEET DESIGNATIONS
Intel uses various data sheet markings to designate each phase of the document as it
relates to the product. The marking appears in the upper, right-hand corner of the data
sheet. The following is the definition of these markings:
Data Sheet Marking

Description

Product Preview

Contains information on products in the design phase of
development; Do not finalize a design with this
information. Revised information will be published when
the product becomes available.

Advanced Information

Contains information on products being sampled or in
the initial production phase of development. *

Preliminary

Contains preliminary information on new products in
production. *

No Marking

Contains information on products in full production. *

*Specifications within these data sheets are subject to change without notice. Verify with your local Intel sales
office that you have the latest data sheet before finalizing a design.

Memory Overview

Memory Technologies
Dynamic RAMs
(Random Access Memories)
Static RAMs
(Random Access Memories)
EPROMs
(Erasable Programmable
Read Only Memories)
Flash Memories (Electrically
Erasable and Reprogrammable
Non..Volatile Memories)

Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER 1
Memory Overview
Memory Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

CHAPTER 2
Memory Technologies
Intel Memory Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

CHAPTER 3
Dynamic RAMs (Random Access Memories)
DATA SHEETS
21256 262,144 x 1-Bit Dynamic RAM with Page Mode .........................
2146465,536 x 4-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .
21010 1,048,576 x 1-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . .
21014 262,144 x 4-Bit Dynamic RAM with Page Mode .........................
21040 4,194,304 x 1-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . .
2D2569 256K x 9-Bit High Density Dynamic RAM Memory Module with Page Mode
21019 1,048,576 x 9-Bit Dynamic RAM Memory Module with Page Mode. . . . . . . ..
225636 256K x 36-Bit Dynamic RAM Memory Module with Page Mode .......... ,
251236 512K x 36-Bit Dynamic RAM Memory Module with Page Mode. . . . . . . . . ..
RELIABILITY REPORT
RR-62 Dynamic RAM Reliability Report ......................................

3-1
3-19
3-37
3-53
3-69
3-90
3-107
3-124
3-141
3-158

CHAPTER 4
Static RAMs (Random Access Memories)
DATA SHEETS
5116S/L 2K x 8-Bit CMOS Static RAM.. . .. . . . . .. . .. .. .. . . . .. . . .. . . .. . . . . . . . .
5164S/L 8K x 8-Bit CMOS Static RAM.. .. . . . . . . . . . . .. .. . . . .. .. . . . . .. . . .. . . . .
51256S/L 32K x 8-Bit CMOS Static RAM.....................................
51C68 High Speed CHMOS 4096 x 4-Bit Static RAM...........................
51C98 High Speed CHMOS 16,384 x 4-Bit Static RAM.........................
5164 High Speed 8192 x 8-Bit Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51256 High Speed 32K x 8-Bit Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51258 High Speed 64K X 4-Bit Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RELIABILITY REPORT
RR-63 Static RAM Reliability Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1
4-9
4-18
4-26
4-32
4-39
4-47
4-56
4-63

CHAPTER 5
EPROMs (Erasable Programmable Read Only Memories)
DATA SHEETS
2716 16K (2K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2732A 32K (4K x 8) UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2764A 64K (8K x 8) UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27128A 128K (16K x 8) Production and UV Erasable PROMs ...................
27256 256K (32K x 8) Production and UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . .
27C256 256K (32K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27C512 512K (64K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . .
27C513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM. . . . . . . . . . . . . . . .
27C011 Page-Addressed 1M (8 x 16K x 8) EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C010 1M (128Kx8) CHMOS EPROM .....................................
27C100 1M (128K x 8) CHMOS EPROM .....................................
27C020 2M (256K x 8) CHMOS EPROM .....................................
27C040 4M (512K x,8) CHMOS EPROM.....................................
ix

5-1
5-9
5-18
5-28
5-38
5-50
5-62
5-72
5-85
5-100
5-113
5-124
5-134
5-144

Tabie of Contents (Continued)
27C210 1M (64K x 16) CHMOS EPROM .....................................
27C220 2M (128K x 16) CHMOS EPROM ....................................
27C240 4M (256K x 16) CHMOS EPROM ....................................
27C400 4M (256K x 16 or 512K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . ..
27960CX Pipelined Burst Access 1M (128K x 8) CHMOS EPROM ...............
27960KX Burst Access 1 M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . ..
APPLICATION NOTES
AP-329 68030/27960CX Burst EPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-346 29000/27960CX Burst EPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RELIABILITY REPORTS
RR-35 EPROM Reliability Data Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RR-67 EPROM Reliability Data Summary CHMOS III-E. . . . . . . . . . . . . . . . . . . . . . . ..
ARTICLE REPRINTS
AR-414 Marriage of CMOS and PLCC Sparking Rapid Change in Mounting
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-455 One Time Programmable EPROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-458 OTP EPROMs with Quick-Pulse Programming Offer Ideal Mass Production
Firmware Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-468 Keeping Data Safe with Nonvolatile Memory. . . . . . . . . . . . . . . . . . . . . . . . . ..

5-154
5-164
5-173
5-182
5-192
5-213
5-232
5-260
5-287
5-341

5-390
5-392
5-395
5-398

CHAPTER 6
Flash Memories (Electrically Erasable and Reprogrammable Non-Volatile
Memories)
Flash: A New Way to Deal with Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA SHEETS
28F256A 256K (32K x 8) CMOS Flash Memory ...............................
28F512 512K (64K x 8) CMOS Flash Memory................................ .
28F010 1024K (128K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28F020 2048K (256K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSM001 FLKA 1 Mbyte (512K x 16) CMOS Flash SIMM . .. . . . . .. .. . . . . . .. . .. . ...
iMC001FLKA 1-Megabyte Flash Memory Card ................................
iMC004FLKA 4-Megabyte Flash Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
APPLICATIt>N NOTES
AP-316 Using Flash Memory for In-System Reprogrammable Nonvolatile Storage.
AP-341 Designing An Updatable BIOS Using Flash Memory ....................
AP-343 Solutions for High Density Applications Using Intel Flash Memory ........
APPLICATION BRIEF
AB-25 Designing in Flexibility with a Universal Memory Site . . . . . . . . . . . . . . . . . . . ..
ENGINEERING REPORTS
ER-20 ETOX II Flash Memory Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
ER-24 The Intel 28F010 Flash Memory ......................................
ARTICLE REPRINTS
AR-463 Don't Write Off the U.S. in Memory Chips .............................
AR-466 Nonvolatility: Semi vs. Mag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ..
AR-470 A 90 ns 100K Erase/Program Cycle Megabit Flash Memory.............
AR-472 The Memory Driver ............................. :...................
AR-474 Memory Life-Cycle Cost............. ...............................
AR-478 Flash, Best of Two Worlds ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-484 PC Standard in the Cards ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-486 Flash Outshines ROM & EPROM ....................................
AR-490 Flash Memory Operates 10-20 Times Longer . . . . . . . . . . . . . . . . . . . . . . . ..
AR-491 Memory Breakthrough Drives Miniaturization ..........................

6-1
6-5
6-30
6-55
6-81
6-109
6-143
6-173
6-203
6-248
6-297
6-365
6-371
6-376
6-390
6-393
6-395
6-399
6-400
6-401
6-406
6-411
6-417
6-419

Alphanumeric Index
210101,048,576 x 1-Bit Dynamic RAM with Page Mode...............................
21014262,144 x 4-Bit Dynamic RAM with Page Mode................................
210191,048,576 x 9-Bit Dynamic RAM Memory Module with Page Mode................
21040 4,194,304 x 1-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21256 262,144 x 1-Bit Dynamic RAM with Page Mode .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21464 65,536 x 4-Bit Dynamic RAM with Page Mode .................................
225636 256K x 36-Bit Dynamic RAM Memory Module with Pag!3 Mode. . . . . . . . . . . . . . . . ..
251236 512K x 36-Bit Dynamic RAM Memory Module with Page Mode. . . . . . . . . . . . . . . . ..
27128A 128K (16K x 8) Production and UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . . . . . . .
2716 16K (2K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27256 256K (32K x 8) Production and UV Erasable PROMs ............. :.............
2732A 32K (4K x 8) UV Erasable PROMs ........................ . . . . . . . . . . . . . . . . . . .
27513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . .
2764A 64K (8K x 8) UV Erasable PROMs ........................ . . . . . . . . . . . . . . . . . . .
27960CX Pipelined Burst Access 1M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . ..
27960KX Burst Access 1M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C010 1M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C011 Page-Addressed 1 M (8 x 16K x 8) EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C020 2M (256K x 8) CHMOS EPROM . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C040 4M (512K x 8) CHMOS EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C100 1M (128Kx8) CHMOS EPROM ............................................
27C21 0 1M (64K x 16) CHMOS EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C220 2M (128K x 16) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C240 4M (256K x 16) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C256 256K (32K x 8) CHMOS EPROM ...........................................
27C400 4M (256K x 16 or 512K x 8) CHMOS EPROM· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C512 512K (64K x 8) CHMOS EPROM ...........................................
27C513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM ......................
28F010 1024K (128K x 8) CMOS Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28F020 2048K (256K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . .. . . .. . .. .. . . . . . . . . . .
28F256A 256K (32K x 8) CMOS Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28F512 512K (64K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2D2569 256K x 9-Bit High Density Dynamic RAM Memory Module with Page Mode. . . . . . .
5116S/L 2K x 8-Bit CMOS Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51256 High Speed 32K x 8-Bit Static RAM ..........................................
51256S/L 32K x 8-Bit CMOS Static RAM........................ ...................
51258 High Speed 64K x 4-Bit Static RAM ..........................................
5164 High Speed 8192 x 8-Bit Static RAM. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5164S/L 8K x 8-Bit CMOS Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
51 C68 High Speed CHMOS 4096 x 4-Bit Static RAM .................................
51C98 High Speed CHMOS 16,384 x 4-Bit Static RAM................................
AB-25 Designing in Flexibility with a Universal Memory Site. . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-316 Using Flash Memory for In-System Reprogrammable Nonvolatile Storage. . . . . . ..
AP-329 68030/27960CX Burst EPROM Interface ......... . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-341 Designing An Updatable BIOS Using Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-343 Solutions for High Density Applications Using Intel Flash Memory. . . . . . . . . . . . . ..
AP-346 29000/27960CX Burst EPROM Interface ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-414 Marriage of CMOS and PLCC Sparking Rapid Change in Mounting Memories. . . ..
AR-455 One Time Programmable EPROMs .........................................
AR-458 OTP EPROMs with Quick-Pulse Programming Offer Ideal Mass Production
Firmware Storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-463 Don't Write Off the U.S. in Memory Chips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-466 Nonvolatility: Semi vs. Mag .................................. ; ...... ". . . . . ..
AR-468 Keeping Data Safe with Nonvolatile Memory .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
xi

3-37
3-53
3-107
3-69
3-1
3-19
3-124
3-141
5-28
5-1
5-38
5-9
5-72
5-18
5-192
5-213
5-113
5-100
5-134
5-144
5-124
5-1.54
5-164
5-173
5-50
5-182
5-62
5-85
6-55
6-81
6-5'
6-30
3-90
4-1
4-47
4-18
4-56
4-39
4-9
4-26
4-32
6-365
6-203
5-232
6-248
6-297
5-260
5-390
5-392
5-395
6-390
6-393
5-398

Aiphanumeric index (Continued)
AR-470 A 90 ns 1OOK Erase/Program Cycle Megabit Flash Memory. . . . . . . . . . . . . . . . . . ..
AR-472 The Memory Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . ..
AR-474 Memory Life-Cycle Cost...................................................
AR-478 Flash, Best ofTwo Worlds. . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ..
AR-484 PC Standard in the Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-486 Flash Outshines ROM & EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-490 Flash Memory Operates 10-20 Times Longer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-491 Memory Breakthrough Drives Miniaturization.......................... .......
ER-20 ETOX II Flash Memory Technology :.........................................
ER-24 The Intel 28F01 0 Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Flash: A New Way to Deal with Memory ............................ '. . . . . . . . . . . . . .. . .
iMC001 FLKA 1-Megabyte Flash Memory Card.. .. .. . . .. .. .. . . .. . .. .. .. . .. .. .. .. . ....
iMC004FLKA 4-Megabyte Flash Memory Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Intel Memory Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .
iSM001 FLKA 1 Mbyte (512K x 16) CMOS Flash SIMM ...............................
Memory Overview .........................................................,......
RR-35 EPROM Reliability Data Summary .......................... ~ . . . . . . . . . . . . . . ..
RR-62 Dynamic RAM Reliability Report ........... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RR-63 Static RAM Reliability Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RR-67 EPROM Reliability Data Summary CHMOS III-E...............................

xii

6-395
6-399
6-400
6-401
6-406
6-411
6-417
6-419
6-371
6-376
6-1
6-143
6-173
2-1
6-109
1-1
5-287
3-158
4-63
5-341

Memory Overview

inter

MEMORY OVERVIEW

MEMORY BACKGROUND
AND DEVELOPMENT

computer systems' insatiable appetites for higher bit
capacities and faster access speeds.

Years ago, MOS LSI memories were little more than
laboratory curiosities. Any engineer brave enough to
design with semiconductor memories had a simple
choice of which memory type to use. The 2102 Static RAM for ease of use or the 1103 Dynamic RAM
for low power were the only two devices available.
Since then, the memory market has come a long
way, the types of memory devices have proliferated,
and more than 3,000 different memory devices are
.now available. Consequently, the designer has many
to choose from but the choice is more difficult, and
therefore, effective memory selection is based on
matching memory characteristics to the application.

RAM Types
Two basic RAM types have evolved since 1970. Dynamic RAMs are noted for high capacity, moderate
speeds and low power consumption. Their memory
cells are basically charge-storage capacitors with
driver transistors. The presence or absence of
charge in a capacitor is interpreted by the RAM's
sense line as a logical 1 or O. Because of the
charge's natural tendency to distribute itself into a
lower energy-state configuration, however, dynamic
RAMs require periodic charge refreshing to maintain
data storage.

Memory devices can be divided into two main categories: volatile and nonvolatile. Volatile memories
retain their data only as long as power is applied. In
a great many applications this limitation presents no
problem. The generic term random access memory
(RAM) has come to be almost synonymous with a
volatile memory in which there is a constant rewriting of stored data.

Traditionally, this requirement has meant that system designers had to implement added circuitry to
handle the dynamic RAM subsystem refresh. And at
certain times, when refresh procedures made the
RAM unavailable for writing and reading; the memory's control circuitry had to arbitrate access. LSI dynamic memory controllers reduce the refresh requirement to a minimal design by offering a monolithic controller solution.

Nonvolatile memories retain their data whether or
not power is applied. In some situations it is critical
that a nonvolatile device be used. An example of this
requirement would be retaining data during a power
failure. (Tape and disk storage are also non-volatile
memories but are not included within the scope of
this book, which confines itself to solid-state technologies in IC form.)
Thus, when conSidering memory devices, it's helpful
to see how the memory in computer systems is segmented by applications and then look at the state-ofthe-art in these cases.

Where users are less concerned with space and
cost than with speed and reduced complexity, the
second RAM type-static RAMs-generally prove
best. Unlike their dynamic counterparts, static RAMs
store ones and zeros using traditional flip-flop logicgate configurations. They are faster and require no
refresh. A user simply addresses the static RAM,
and after a very brief delay, obtains the bit stored in
that location. Static devices are also simpler to design with than dynamic RAMs, but the static cell's
complexity puts these volatile chips far behind dynamics in bit capacity per square mil of silicon.

Volatile Read/Write Memory

Nonvolatile Read-Only Memory
Another memory class, read-only memory (ROM), is
similar to RAM in that a computer addresses it and
then retrieves data stored at that address. However,
ROM includes no mechanism for altering the data
. stored at that address-hence, the term read only.

First examine read/write memory, which permits the
access of stored memory (reading) and the ability to
alter the stored data (writing).
Before the advent of solid-state read/write memory,
active data (data being processed) was stored and
retrieved from nonvolatile core memory (a magneticstorage technology). Solid-state RAMs solved the
size and power consumption problems associated
with core, but added the element of volatility. Because RAMS lose their memory when you turn off
their power, you must leave systems on all the time,
add battery backup or store important data on a
nonvolatile medium before the power goes down.

ROM is basically used for storing information that
isn't subject to change-at least not frequently. Unlike RAM, when system power goes down, ROM retains its contents.
ROM devices became very popular with the advent
of microprocessors. Most early microprocessor applications were dedicated systems; the system's
program was fixed and stored in ROM. Manipulated
data could vary and was therefore stored in RAM.
This application split caused ROM to be commonly
called program storage, and RAM, data storage.

Despite their volatility, RAMs have become very
popular, and an industry was born that primarily fed
1-1

inter

MEMORY OVERVIEW

The first ROMs contained cell arrays in which the
sequence of ones and zeros was established by a
metallization interconnect mask step during fabrication. Thus, users had to supply a ROM vendor with
an interconnect program so the vendor could complete the mask and build the ROMs. Set-up charges
were quite high-in fact, even prohibitive unless users planned for large volumes cif the same ROM.

EPROM or DRAM in bit capacity per square millimeter of silicon and the resulting lack of cost-effectiveness and density has caused it to lag behind other
memory technologies.
The latest advance·ment is Flash memory. Flash
memories combine the electrical erase capability of
the EEPROM with the simplicity, density and cost-effectiveness of EPROM cell layout. Modification to
the EPROM cell replaces block UV-erasure with
block electrical erasure, which can be accomplished
while the device is still installed in the host system.
Flash memory. can also be randomly read or written
by the local system microprocessor or microcontroller.

To offset this high set-up charge, manufacturers developed a user-programmable ROM (or PROM). The
first such devices used· fusible links that could be
melted or programmed with a special hardware system.
Once programmed, a PROM was just like a ROM. If
the program was faulty, the chip had to be discarded. But, PROMs furnished a more cost-effective way
to develop program memory or firmware for low-volume purposes than did ROMs.

The cost effectiveness and flexibility of Flash memory makes it applicable in code storage applications.
Code can be quickly and easily updated during prototyping, incoming test, assembly qr in the field,
quickly and easily. High density and nonvolatile
read/write capability also make Flash memory an
innovative alternative for mass storage, and integrating main memory and backup storage functions into
directly executable Flash memory boosts system
performance, shrinks system size, reduces power
requirements and increases reliability over that of
electromechanical media, especially in extreme environmental conditions.

As one alternative· to fusable-link programming, Intel
pioneered an erasable MOS-technology PROM
(termed an EPROM) that used charge-storage programming. It came in a standard ceramic DIP package but had a window that permitted die exposure to
light. When the chip was exposed to ultraviolet light,
high energy photons could collide with the EPROM's
electrons and scatter them at random, thus erasing
the memory.
The EPROM was not intended for use in read/write
applications, but it proved very useful in research
and development for prototypes, where the need to
alter the program several times is quite common.
Indeed, the EPROM market originally consisted almost exclusively of development labs. As the fabrication process became mature, and volumes increased, EPROM's lower prices made them attractive even for medium-volume production-system applications. Today, millions of EPROMs are used in
systems which require only periodic, off-line updates
of information and parameters.

APPLICATIONS OF MEMORY
DEVICES
Besides the particular characteristics of each device
that has been discussed, there are a number of other factors to consider when choosing a memory
product, such as cost, power consumption, performance, memory architecture and organization, and
size of the memory. Each of these factors plays an
important role in the final selection process.

Performance
Nonvolatile Read/Write Memory
Technology advances have blurred the traditional
lines drawn between read-only memories (ROMs)
and read/write memories (RAMs). The first alternative was the EPROM, which required removal from
the host system, placing it under ultraviolet light for
erasure, and subsequent reprogramming and reinstallation into the host system.
The next advancement was the introduction of a
nonvolatile memory that was electrically erasable
and user rewritable on a byte-by-byte basis, called
the EEPROM. The byte erase capability and highlevel of feature integration of the EEPROM came
with two penalties-density and cost. Cell and periphery complexity places EEPROM far behind

Generally, the term performance relates to how fast
the device can operate in a given system environment. This parameter is usually rated in terms of the
access time. Fast SRAMs can provide access times
as fast as 20 ns, while the fastest DRAM cannot go
much beyond the 100 ns mark. A bipolar PROM has
an access time of 35 ns. RAM and PROM access is
usually controlled by a ~nal most often referred to
as Chip Select (CS). CS often appears in device
specifications. In discussing access times, it is important to remember that in SRAMs and PROMs,
. the access time equals the cycle time of the system
whereas in DRAMs, the access time is always less
than the cycle time.

1-2

MEMORY OVERVIEW

Power consumption also depends upon the organization of the device in the system. Organization' usually refers to the width of the memory word. At the
time of their inception, memory devices were organized as nK x 1 bits. Today, they are available in
various configurations such as 4K x 1, 16K x 1, 64K
x 1, 1K x 4, 2K x 8, etc. As the device width increases, fewer devices are required to configure a given
memory word-although the total number of bits remains constant. The wider organization can provide
significant savings in power consumption, because a
fewer number of devices are required to be powered
up for access to a given memory word. In addition,
the board layout design is simpler due to fewer
traces and better layout advantages. The wider
width is of particular advantage in microprocessors
and bit-slice processors because most microprocessors are organized in 8-bit or 16-bit architectures. A
memory chip configured in the nK x 8 organization
can confer a definite advantage-especially in universal site applications. Conversely, there is usually
a small speed penalty, at the device level for a x8 or
x16 organization.

Cost
There are many ramifications to consider when evaluating cost. Often the cost of the physical device
used is the smallest portion of the total cost of using
a particular device. Total cost must comprehend
other factors such as design-in time, test expense,
update costs, as well as cost per bit, size of memory
power consumption, etc.
Cost of design time is proportional to design complexity. For example, SRAMs generally require less
design-in time than DRAMs because there is no refresh circuitry to consider. Conversely, the DRAM
provides the lowest cost per bit because of its higher
packing density. The cost of a service call to exchange or reprogram a ROM/PROM/EPROM versus an in-system update of a Flash memory costs
orders of magnitude more than the device itself.

Memory Size
Memory size is generally specified in the number of
bytes (a byte is a group of eight bits). The memory
size of a system is usually segmented depending
upon the general equipment category. Computer
mainframes and most of today's minicomputers use
blocks of read/write substantially beyond 64K
bytes-usually in the hundreds of thousands to millions of bytes.

Types of Memories
The first step to narrowing down your choice is to
determine the type of memory you are designingdata store or program store. After this has been
done, the next step is to prioritize the following factors:

The microprocessor user generally requires memory
sizes ranging from 2K bytes up to 64K bytes. In
memories of this size, the universal site concept allows maximum flexibility in memory design.

Performance
Power Consumption
Density
Cost

Power Consumption

SUMMARY

Power consumption is important because the total
power required for a system directly affects overall
cost. Higher power consumption requires bigger
power supplies, more cooling, and reduced device
density per board-all affecting cost and reliability.
All things considered, the usual goal is to minimize
power. Many memories now provide automatic power-down. With today's emphasis on saving energy
and reducing cost, the memories that provide these
features will gain an increasingly larger share of the
market.

Global Memory
Generally, a global memory is greater than 64K
bytes and serves as a main memory for a microprocessor system. Here, the use of dynamic RAMs or
Flash memory for read/write memory is dictated to
provide the highest density and lowest cost per bit.
The cost of providing refresh circuitry for the dynamic RAMs is spread over a large number of memory
bits, thus minimizing the cost impact.

In some applications, extremely low power consumption is required, such as battery operation. For
these applications, the use of devices made by the
CMOS technology have a distinct advantage over
the NMOS products. CMOS devices offer power
savings of several magnitudes over NMOS. Non-volatile devices such as EPROMs or Flash memories
are usually independent of power problems in these
applications.

Local Memory
Local memories are usually less than 64K bytes and
reside in the proximity of the processor itself-usuallyon the same PC board. Types of memories often
used in local memory applications are SRAM,
EPROM, Flash memory, and EEPROM.

1-3

Memory Technologies

INTEL MEMORY TECHNOLOGIES
Most of this handbook is devoted to techniques and
information to help you design and implement semiconductor memory in your application or system. In
this section, however, the memory chip itself will be
examined and the processing technology required to
turn a bare slice of silicon into high performance
memory devices is described. The discussion has
been limited to the basics of MOS (Metal Oxide
Semiconductor) technologies as they are responsible for the majority of memory devices manufactured
at Intel.

same silicon. Either p- or n-type silicon substrates
can be used, however, deep areas of the opposite
doping type (called wells) must be defined to allow
fabrication of the complementary transistor type.
Most of the early semiconductor memory devices,
like Intel's pioneering 1103 dynamic RAM and 1702
EPROM were made with PMOS technologies. As
higher speeds and greater densities were needed,
most new devices were implemented with NMOS.
This was due to the inherently higher speed of
n-channel charge carriers (electrons) in silicon along
with improved process margins. CMOS technology
has begun to see widespread commercial use in
memory devices. It allows for very low power devices used for battery operated or battery back-up applications. Historically, CMOS has been slower than
any NMOS device. However, CMOS technology has
been improved to produce higher speed devices.
The extra cost of processing required to make both
transistor types had kept CMOS memories limited to
those areas where the technology's special characteristics would justify the extra cost. In the future, the
learning curve for high performance CMOS costs
are making a larger number of memory devices
practical in CMOS.

There are three major MOS technology familiesPMOS, NMOS, and CMOS (Figure 1). They refer to
the channel type of the MOS transistors made with
the technology. PMOS technologies implement
p-channel transistors by diffusing p-type dopants
(usually boron) into an n-type silicon substrate to
form the source and drain. P-channel is so named
because the channel is comprised of positively
charged carriers. NMOS technologies are similar,
but use n-type dopants (normally phosphorus or arsenic) to make n-channel transistors in p-type silicon
substrates. N-channel is so named because the
channel is comprised of negatively charged carriers.
CMOS or Complementary MOS technologies combine both p-channel and n-channel devices on the

GATE

296102-2

296102-1
PMOS

NMOS

P-CHANNEL
DEVICE

N-CHANNEL
DEVICE
GATE

F.O.

P-SUBSTRATE

296102-3
CMOS

Figure 1. MOS Process Cross-sections

2-1

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INTEL MEMORY TECHNOLOGIES

In the following section, the basic fabrication sequence for an HMOS circuit will be described.
HMOS is a high performance n-channel MOS process developed by Intel for 5V single supply circuits.
HMOS, and CHMOS, CHMOS-E (EPROM) and
ETOXTM (Flash Memory), along with their evolutionary counterparts comprise the process family responsible for most of the memory components produced by Intel today.

Having fulfilled its purpose, the remaining silicon nitride layer is removed. A light oxide etch follows taking with it the underlying first oxide but leaving the
thick (field) oxide.
'
Now that the areas for active transistors have been
defined and isolated, the transistor types needed
can be determined. The wafer is again patterned
and then if special characteristics (such as depletion
mode operation) are required, it is implanted with
dopant atoms. The energy and dose at which the
dopant atoms are implanted determines much of the
transistor's characteristics. The type of the dopant
provides for depletion mode (n-type) or enhancement mode (p-type) operation.

The MOS IC fabrication process begins with a slice
(or wafer) of siJlgle crystal silicon. Typically, it's 100
or 150 millimeter in diameter, about a half millimeter
thick, and uniformly doped p-type. The wafer is then
oxidized in a furnace at around 1000°C to grow a
thin layer of silicon dioxide (Si02) on the surface.
Silicon nitride is then deposited on the oxidized wafer in a gas phase chemical reactor. The wafer is
now ready to receive the first pattern of what is to
become a many layered complex circuit. The pattern
is etched into the silicon nitride using a process
known as photolithography, which will be described
in a later section. This first pattern (Figure 2) defines
the boundaries of the active regions of the IC, where
transistors, capacitors, diffused resistors, and first
level interconnects will be made. .
ETCHED
AREAS

The transistor types defined, the gate oxide of the
active transistors are grown in a high temperature
furnace. Special care must be taken to prevent contamination or inclusion of defects in the oxide and to
ensure uniform consistent thickness. This is important to provide precise, reliable device characteristics. The gate oxide layer is then masked and holes
are etched to provide for direct gate to diffusion
("buried") contacts where needed.
The wafers are now deposited with a layer of gate
material. This is typically poly' crystaline silicon
("poly") which is deposited in a gas phase chemical
reactor similar to that used for silicon nitride. The
poly is then doped (usually with phosphorus) to bring
the sheet resistance down to 10-20 fi/square. This
layer is also used for circuit interconnects and if a
lower resistance is required, a refractory metal/polysilicon composite or refractory metal silicide can be
used instead. The gate layer is then patterned to
define the actual transistor gates and interconnect
paths (Figure 4).

NITRIDE---....

OXIDE-'"

)

P-SUBSTRATE

296102-4

Figure 2. First Mask
The patterned and etched wafer is then implanted
with additional boron atoms accelerated at high energy. The boron will only reach the silicon substrate
where the nitride and oxide was etched away, providing areas doped strongly p-type that will electrically separate active areas. After implanting, the wafers are oxidized again and this time a thick oxide is
grown. The. oxide only grows in the etched areas
due to silicon nitride's properties as an oxidation barrier. When the oxide is grown, some of the silicon
substrate is consumed and this gives a physical as
well as electrical isolation for adjacent devices as
can be seen in Figure 3.
NITRIDE

P+

POLYSILICON

P-SUBSTRATE

296102-6

Figure 4. Post Gate Mask
The wafer is next diffused with n-type dopant .(typically arsenic or phosphorus) to form the source and
drain junctions. The transistor gate material acts as
a barrier to the dopant providing an undiffused channel self-aligned to the two junctions. The wafer is
then oxidized to seal the junctions from contamination with a layer of Si02 (Figure 5).

FIELD OX

P-SUBSTRATE

P+

P+
296102-5

Figure 3. Post Field Oxidation
2-2

inter

INTEL MEMORY TECHNOLOGIES

+ Vo

SECOND-LEVEL
POLYSILICON

FIELD
OXIDE

296102-7

Figure 5. Post Oxidation

P-SUBSTRATE

A thick layer glass is then deposited over the wafer
to provide for insulation and sufficiently low capacitance between the underlying layers and the metal
interconnect signals. (The lower the capacitance,
the higher the inherent speed of the device.) The
glass layer is then patterned with contact holes and
placed in a high temperature furnace. This furnace
step smooths the glass surface and rounds the contact edges to provide uniform metal coverage. Metal
(usually aluminum or aluminum/silicon) is then deposited on the wafer and the interconnect patterns
and external bonding pads are defined and etched
(Figure 6). The wafers then receive a low temperature (approximately 500°C) alloy that insures good
ohmic contact between the aluminum and diffusion
.
or poly.

EPROM/FLASH MEMORY CELL

296102-9

Figure 7. Double Poly Structure
After fabrication is complete, the wafers are sent for
testing. Each circuit is tested individually under conditions designed to determine which circuits will operate properly both at low temperature and at conditions found in actual operation. Circuits that fail
these tests are inked to distinguish them from good
circuits. From here the wafers are sent from assembly where they are sawed into individual circuits with
a paper-thin diamond blade. The inked circuits are
then separated out and the good circuits are sent on
for packaging.
Packages fall into two categories-hermetic and
non-hermetic. Hermetic packages are Cerdip, where
two ceramic halves are sealed with a glass fritt, or
ceramic with soldered metal lids. An example of hermetic package assembly is shown in Table 1. Nonhermetic packages are molded plastics.
The ceramic package has two parts, the base, which
has the leads and die (or circuit) cavity, and the metal lid. The base is placed on a heater block and a
metal alloy preform is inserted. The die is placed on
top of the preform which bonds it to the package.
Once attached, wires are bonded to the circuit and
then connected to the leads. Finally the package is
placed in a dry inert atmosphere and the lid is soldered on.

296102-8

Figure 6. Complete Circuit (without paSSivation)
At this point the circuit is fully operational, however,
the top metal layer is very soft and easily damaged
by handling. The device is also susceptible to contamination or attack from moisture. To prevent this
the wafers are sealed with a passivation layer of silicon nitride or a silicon and phosphorus oxide composite. Patterning is done for the last time opening
up windows only over the bond pads where external
connections will be made.

The cerdip package consists of a base, lead frame,
and lid. The base is placed on a heater block and
the lead frame placed on top. This sets the lead
frame in glass attached to the base. The die is then
attached and bonded to the leads. Finally the lid is
placed on the package and it is inserted in a seal
furnace where the glass on the two halves melt together making a hermetic package.

This completes basic fabrication sequence for a single poly layer process. Double poly processes such
as those used for high density Dynamic RAMs,
EPROMs, flash memories, and EEPROMs follow the
same general process flow with the addition of gate,
poly deposition, doping, and interlayer dielectric process modules required for the additional poly layer
(Figure 7). These steps are performed right after the
active areas have been defined (Figure 3) providing
the capacitor or floating gate storage nodes on
those devices.
.

In a plastic package, the key component is the lead
frame. The die is attached to a pad on the lead
frame and bonded out to the leads with gold wires.
The frame then goes to an injection molding machine and the package is formed around the lead
frame. After mold the excess plastic is removed and
the leads trimmed.
2-3

INTEL MEMORY TECHNOLOGIES

After assembly, the individual circuits are retested at
an elevated operating temperature to assure critical
operating parameters and separated according to
speed and power consumption into individual specification groups. The finished circuits are marked and
then readied for shipment.

PHOTOLITHOGRAPHY
The photo or masking technology is the most important part of the manufacturing flow if for no other
reason than the number of times it is applied to each
wafer. The manufacturing process gets more complex in order to make smaller and higher performance circuits. As this happens the number of masking steps increases, the features get smaller, and
the tolerance required becomes tighter. This is
largely because the minimum size of individual pattern elements determine the size of the whole circuit, effecting its cost and limiting its potential complexity. Early MOS IC's used minimum geometries
(lines or spaces) of 8-1'0 microns (1 micron = 1'0- 6
meter "" 1/25,'0'0'0 inch). The n-channel processes
of the mid 197'O's brought this down to approximately 5 microns, and today minimum geometries of one
micron are in production. This dramatic reduction

The basic process flow described above may make
VLSI device fabrication sound straightforward, however, there are actually hundreds of individual operations that must be performed correctly to complete a
working circuit. It usually takes well over two months
to complete all these operations and the many tests
and measurements 'involved throughout the manufacturing process. Many of these details are responsible for ensuring the performance, quality, and'reliability you expect from Intel products. The following
sections will discuss the technology underlying each
of the major process elements mentioned in the basic process flow.

Table 1. Typical Hermetic Package Assembly
Flow

ProcessiMaterlals

Typical Item

Frequency

Criteria

Waler
Die saw, wafer break
Die wash and plate
Die visual inspection

Passivation, metal

OAgate
Die attach
(Process monitor)

0f76, LTPD=5%

Wet out

4 x/operator/shift

0111 LTPD=20%

Orientation, lead
dressing, etc.

4 x/operator/
machine/shift

All previous items
Cap align, glass
integrity. moisture

every lot

11129, LTPD=3%

4 x /furnace/shift

0115, LTPD= 15%

Post die attach visual
Wire bond
(Process monitor)

100% 01 devices

Post bond inspection

f-o

OAgate
Seal and Mark
(Process monilor)

100% devices

Temp cycle

I," ~

2,4-

100% oldie
Every lot

lOx to mil std.
,883cond. C

Hermeticity check
(Process monitor)

F/G leak

100% devices

Lead Trim
(Process monitor)

Burrs, etc, (visual)
Fine leak

4 x/station/shift
2 x/station/shift

External visual

Solder voids, cap
alignment, etc.

100% devices

OAgate

All previous items

All lots

Class test
(Process monitor)

Run standards
(good and reject)
Calibrate every
system using
"autover" program

Every 48 hrs.

1111, LTPD = 20%

0115, LTPD= 15%
11129, LTPD=3%

11129, LTPD. 3%

Mark and Pack
FinalQA

(See attached)
296102-11

NOTES:
1. Units for assembly reliability monitor.
2. Units for product reliability monitor.

2-4

inter

INTEL MEMORY TECHNOLOGIES

in feature size was achieved using the newer high
resolution photo resists and optimizing their processing to match improved optical printing systems.

DIFFUSION
The picture of clean room garbed operators tending
furnace tubes glowing cherry red is the one most
often associated with IC fabrication. These furnace
operations are referred to collectively as diffusion
because they employ the principle of sold state diffusion of matter to accomplish their results. In MOS
processing, there are three main types of diffusion
operations: predeps, drives, and oxidations.

A second major factor in determining the size of the
circuit is the registration or overlay error. This is how
accurately one pattern can be aligned to a previous
one. Design rules require that space be left in all
directions according to the overlay error so that unrelated patterns do not overlap or interfere with one
another. As the error space increases the circuit size
increases dramatically. Only a few years ago standard alignment tolerances were :<: ± 2 microns; now
advanced Intel processes have reduced this dramatically due mostly to the use of advanced projection
and step and repeat exposure equipment.

Predeposition, or "predep," is an operation where a
dopant is introduced into the furnace from a solid,
liquid, or gaseous source and at the furnace temperature (usually 900·C-1200·C) a saturated solution is
formed at the silicon surface. The temperature of the
furnace, the dopant atom, and rate of introduction
are all engineered to give a specific dose of the dopant on the wafer. Once this is completed the wafer is
given a drive cycle where the dopant left at the surface by the predep is driven into the wafer by high
temperatures. These are generally at different temperatures than the predeps and are designed to give
the required junction depth and concentration profile.

The wafer that is ready for patterning must go
through many individual steps before that pattern is
complete. First the wafer is baked to remove moisture from its surface and is then treated with chemicals that ensure good resist adhesion. The thick
photoresist liquid is then applied and the wafer is
spun flat to give a uniform coating, critical for high
resolution. The wafer is baked at a low temperature'
to solidify the resist into gel. It is then exposed with a
machine that aligns a mask with the new pattern on
it to a previously defined layer. The photo-resist will
replicate this pattern on the wafer.

Oxidation, the third category, is used at many steps
of the process as was shown in the process flow.
The temperature and oxidizing ambient can range
from 800·C to 1200·C and from pure oxygen to mixtures of oxygen and other gases to steam depending
on the type of oxide required. Gate oxides require
high dielectric breakdown strength for thin layers
(between 0.01 and 0.1 micron) and very tight control
over thickness (typically ± 0.005 micron or less than
± 1/5,000,000 inch), while isolation oxides need to
be quite thick and because of this their dielectric
breakdown strength per unit thickness is much less
important.

Negative working resists are polymerized by the light
and the unexposed resist can be rinsed off with solvents. Positive working resists use photosensitive
polymerization inhibitors that allow a chemically reactive developer to remove the exposed areas. The
positive resists require much tighter control of exposure and development but yield higher resolution
patterns than negative resistance systems.
The wafer is now ready to have its pattern etched.
The etch procedure is specialized for each layer to
be etched. Wet chemical etchants such as hydrofluoric acid for silicon oxide or phosphoric acid for
aluminum are often used for this. The need for
smaller features and tighter control of etched dimensions is increasing the use of plaslT)a etching in fabrication. Here a reactor is run with a partial vacuum
into which etchant gases are introduced and an
electrical field is applied. This yields a reactive plasma which etches the required layer.

The properties of the diffused junctions and oxides
are key to the performance and reliability of the finished device so the diffusion operations must be extremely well controlled for accuracy, consistency
and purity.

ION IMPLANT
Intel's high performance products require such high
accuracy and repeatability of dopant control that
even the high degree of control provided by diffusion
operations is inadequate. However, this limitation
has been overcome by replacing critical predeps
with ion implantation. In ion implantation, ionized
dopant atoms are accelerated by an electric field

The wafer is now ready for the next process step. Its
single journey through the masking process required
the careful engineering of mechanics, optics, organic chemistry, inorganic chemistry, plasma chemistry,
physics, and electronics.

2-5

inter

INTEL MEMORY TECHNOLOGIES

and implanted directly into the wafer. The acceleration potential determines the depth to which the
dopant is implanted.

The fabrication of modern memory devices is a long,
complex process where each step must be monitored, measured and verified. Developing a totally
new manufacturing process for each new product or
even product line takes a long time and involves significant risk. Because of this, Intel has developed
process families, such as HMOS, on which a wide
variety of devices can be made. These families are
scalable so that circuits need not be totally redesigned to meet your needs for higher
performance.(1) They are evolutionary so that development time of new processes and products can be
reduced without compromising Intel's commitment
to consistency, quality, and reliability.

The charged ions can be counted electrically during
implantation giving very tight control over dose. The
ion implanters used to perform this are a combination of high vacuum system, ion source, mass spectrometer, linear accelerator, ultra high resolution current integrator, and ion beam scanner. You can see
that this important technique requires a host of sophisticated technologies to support it.

THIN FILMS
The manufacture of today's MOS memory devices
requires a tremendous variety of technologies and
manufacturing techniques, many more than could be
mentioned here. Each requires a team of experts to
design, optimize, control and maintain it. All these
people and thousands of others involved in engineering, design, testing and production stand behind
Intel's products.

Thin film depositions make up most of the features
on the completed circuit. They include the silicon nitride for defining isolation, polysilicon for the gate
and interconnections, the glass for interlayer dielectric, metal for interconnection and external connections, and passivation layers. Thin film depositions
are done by two main methods: physical deposition
and chemical vapor deposition. Physical deposition
is most common for deposition metal. Physical depositions are performed in a vacuum and are accomplished by vaporizing the metal with a high energy
electron beam and redepositing it on the wafer or by
sputtering it from a target to the wafer under an electric field.

Because of these extensive requirements, most
manufacturers have not been able to realize their
needs for custom circuits on high performance, high
reliability processes. To address this Intel's expertise in this area is now available to industry through
the silicon foundry. Intel supplies design rules and
support to design and debug circuits. This includes
access to Intel's n-well CHMOS technology. Users
of the foundry can now benefit from advanced technology without developing processes and IC manufacturing capability themselves.

Chemical vapor deposition can be done at atmospheric pressure or under a moderate vacuum. This
type of deposition is performed when chemical gases react at the wafer surface and deposit a solid film
of the reaction product. These reactors, unlike their
general industrial counterparts, must be controlled
on a microscale to provide exact chemical and physical properties for thin films such as silicon dioxide,
silicon nitride, and polysilicon.

(1)R. Pashley, K. Kokkonen, E. Boleky. R. Jecmen, S. Liu,
and W. Owen, "H-MOS Scales Traditional Devices to Higher Performance Level," Electronics, August 18, 1977.

2-6

Dynamic RAMs
(Random Access Memories)

21256
262,144 x 1-BIT DYNAMIC RAM WITH PAGE MODE
Symbol

•
•
•
•

Parameter

21256-06

21256-07

21256-08

21256-10

Units

tRAG

Access Time from RAS

100

tGAC

Access Time from CAS

tRG

Read Cycle Time

110

130

150

190

•
•
•
•

Page Mode Capability
CAS-before-RAS Refresh Capability
RAS-Only and Hidden Refresh
Capability
TTL Compatible Inputs and Output

Common 1/0 Using Early Write
Single + 5V ± 10% Power Supply
256 Cycle/4 ms Refresh
JEDEC Standard Pinout in DIP, ZIP and
PLCC

The 21256 is a fully decoded dynamic random access memory organized as 262,144 one-bit words. The
design is optimized for high speed, high performance applications such as computer memory, buffer memory,
peripheral storage and environments where low power dissipation and compact layout are required.
The 21256 features page mode which allows high speed random access of memory cells within the same row.
CAS-before-RAS refresh capability provides on-chip auto refresh as an alternative to RAS-only refresh. Multiplexed row and column address inputs permit the 21256 to be housed in a JEDEC standard 16-pin DIP.
Clock timing requirements are noncritical, and power supply tolerance i!! very wide. All inputs and output are
TTL compatible.

RAS _1""""----,
CONTROL & t::===~----i:l
CLOCKS IVi -r."'T""---,~

CAS

AO
Al
A2
A3

A4
AS
A6

'"co
~

:=o

MEMORY ARRAY
262,144
CELLS
~vcc

A7
A8

~vss
240021-1

Figure 1_ Functional Block Diagram

3-1

September 1990
Order Number: 240021-004

intJ

21256

DIP
AS
0

VSS
CAS

RAS

Vee

A7
240021-2

·PLCC
0

AS VssCAS

~~! L~.! ~1~

•

W ~]
NC

{]
[]

RAS

!1.?!

(TOP VIEW)

[1]
[(§

~~
[1]
[1}

A6
A3
A4

~8~ r9~ ~C; ~1-1~
Al Vee A7 AS

240021-3

ZIP

OM'~
Q

Vss

RAS

vee

A3'-16
240021-4

(Bottom View)
Pin Names
Ao-As

W
RAS
CAS

Vee
Vss

Address Input
Data In
Data Out
Read/Write Input
Row Address Strobe
Column Address Strobe
Power (+5V)
Ground

3-2

intJ

21256

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Voltage on Any Pin
Relative to vss .......... VOUT -1.0V to + 7.0V

'WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Voltage on Vcc Supply
Relative to Vss ............... -1.0V to + 7.0V
Storage Temperature .......... - 55D C to + 125D C
Power Dissipation .......................... 1.0W
Short Circuit Output Current ................ 50 mA

RECOMMENDED OPERATING CONDITIONS
Symbol

Voltages referenced to Vss, TA

0 to 70D C

Parameter

Min

Typ

Max

Vcc

Supply Voltage

4.5

5.0

5.5

Vss

Ground

VIH

Input High Voltage

2.4

Vcc+ 1

VIL

Input Low Voltage

-1

0.8

Units

D.C. AND OPERATING CHARACTERISTicS
Recommended operating conditions unless otherwise noted.

Symbol

Parameter

Min Max Units

Test Condition

ICCl

Operating Current'

21256-06
21256-07
21256-08
21256-10

75
70
60
55

mA
mA
lilA
mA

(RASand CAS
cycling @ tRC = min.)

ICC2

Standby Current

21256-06
21256-07
21256-08
21256-10

2.0
2.0
2.0
5.0

mA
mA
mA
mA

(RAS = CAS = VIH)

ICC3

RAS-Only Refresh Current'

21256-06
21256-07
21256-08
21256-10

75
70
60
40

mA
mA
mA
mA

(CAS = VIH, RAS
cycling @ tRC = min.)

ICC4

Page Mode Current'

21256-06
21256-07
21256-08
21256-10

50
45
40
35

mA
mA
mA
mA

(RAS = VIL, CAS cycling;
tpc = min.)

ICC5

CAS-before-RAS Refresh Current' 21256-06
21256-07
21256-08
21256-10

75
65
55
55

mA
mA
mA
mA

(RAS cycling

Iccs

Standby Current

1.0

(RAS = CAS = Vcc - 0.2V)

IlL

Input Leakage Current

-10

p.A

(Any input 0 :5: VIN :5: 5.5V,
Vcc = 5.5V, Vss = OV, All other
pins not under test = 0.)

IOL

Output Leakage Current

-10

p.A

(Data out is disabled,
OV :5: VOUT :5: 5.5V,
Vcc = 5.5V, Vss = OV)

tRC = min.)

'NOTE:
and ICC5 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is
specified as average current.
ICCt, ICC3, ICC4

3-3

intJ

21256

D.C. AND OPERATING CHARACTERISTICS
Recommended operating conditions unless otherwise noted. (Continued)

Symbol

Parameter

Min

VOH

Output High Voltage Level

Val

Output 'Low Voltage Level

CAPACITANCE

I
I

Max

Units

2.4
0.4

(IOH

(IOl

= 5 mA)
= 4.2 mA)

TA = 25D C

Symbol

Parameter

Min

Input Capacitance (Ao-As, D)

CIN1

Test Condition

Max

Units

CIN2

Input Capacitance (RAS, CAS, W)

COUT

Output Capacitance (0)

A.C. CHARACTERISTICS
Symbol

(ODC ::;; TA ::;; 70DC, VCC = 5.0V ± 10%. See Notes 1, 2)

Parameter

21256-06
Min

21256-07

Max

Min

Max

21256-08
Min

Max

21256-10
Min

Units Notes

Max

tRC

Random Read or
Write Cycle Time

120

135

150

190

tRWC

Read-Modify-Write Cycle Time 135

155

175

220

tRAC

Access Time from RAS,

100'

3,4,11

tCAC

Access Time from CAS

3,4,5

tAA

Column Address Access Time

tClZ

CAS to Output in Low-Z

35
5

40
5

50
5

3,10

tOFF

Output Buffer Turn-Off Delay

Transition Time (Rise and Fall)

100

tRP

RAS Precharge Time

tRAS

RAS Pulse Width

65
10,000

10,000

10,000 100 10,000

tRSH

RAS Hold Time

tCPN

CAS Precharge Time
(All Cycles except Page Mode)

tCAS

CAS·Pulse Width

tCSH

CAS Hold Time

tRCD

RAS to CAS Delay Time

. 60

tRAD

RAS to Column Address
Delay Time

tCRP

CAS to RAS Precharge Time
(RAS Only Refresh)

tASR

Row Address Setup Time

10,000

3-4

10,000

100

ns
ns

21256

A.C. CHARACTERISTICS (o·c
Symbol

:S: T A :S: 70·C, VCC

Parameter

21256-06

5.0V ± 10%. See Notes 1, 2) (Continued)

21256-07

Min

Max Min

Max

21256-08

21256-10

Min

Max Min

Units Notes

Max

tAAH

Row Address Hold Time

tASC

Column Address Setup Time

tCAH

Column Address Hold Time

tAA

Column Address Hold Time
Referenced to RAS

tAAL

Column Address to RAS
Lead Time

tACS

Read Command Setup Time

tACH

Read Command Hold Time
Referenced to CAS

tAAH

Read Command Hold Time
Referenced to RAS

twcs

Write Command Setup Time

tWCH

Write Command Hold Time

twp

Write Command Pulse Width

tAWL

Write Command to RAS Lead Time

tcWL

Write Command to CAS Lead Time

tDS

Data-In Setup Time

10
10

tDH

Data-In Hold Time

tCWD

CAS to Write Enable Delay

' ns

tAWD

RAS to Write Enable Delay

100

tAWD

Column Address to W Delay Time

.40

tWCA

Write Command Hold Time
Referenced to RAS

tDHA

Data-In Hold Time
Reference9 to RAS

tAEF

Refresh Period (256 Cycles)

CAS-BEFORE-RAS REFRESH
tCSA

CAS Setup Time
(CAS-before-RAS Refresh)

tCHA

CAS Hold Time
(CAS-before-RAS Refresh)

tcPT

Refresh Counter Test
CAS Precharge Time

tAPC

RAS Precharge to CAS Active Time

PAGE MODE
tpc

Page Mode Cycle Time

tcp

CAS Precharge Time
(Page Mode Only)

3-5

intJ

21256

A.C. CHARACTERISTICS
Symbol

(O·C ::;; T A ::;; 70·C, Vee = 5.0V ± 10%. See Notes 1, 2) (Continued)

Parameter

21256-06
Min

Max

21256-07
Min

Max

21256-08
Min

Max

21256-10
Min

Units Notes

Max

PAGE MODE (Continued)
45

ePA

Access Time from CAS Precharge

PRwe

Fast Page Mode
Read-Modify-Write

RASP

RAS Pulse Width (Fast Page Mode)

60 10,000 70 10,000 80 10,000 100 10,000 ns

40
75

50
85

55
95

NOTES:
1. An initial pause of 200 JLs is required after power-up followed by any S RAS cycles before proper device operation is
achieved.
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5 ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100 pF.
4. Operation within the T RCD(max) limit ensures that T RAc(max) can be met, tRCD(max) is specified as a reference point
only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tcAC.
5. Assumes that tRCD ;;" tRCD(max).
• 6. tAR, tWCR, tDHR are referenced to tRAD(max)'
'
7. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or
VOL·
'
·S. twcs, tRWD, lewD and tAWD are non-restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If twcs ;;" tWCS(min) the cycle i,s an early write cycle and the data out pin will remain high impedance for
the duration of the cycle. If tCWD ;;" tcWD(min), tRWD ;;" tRWD(min) and tAWD ;;" tAWD(min), then the cycle is a read-write cycle
and the data out will contain the data read from the selected address. If ,neither of the above conditions are satisfied, the
condition of the data out is indeterminate.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write
cycles.
"
,
11. Operation within the tRAD!max) limit insures thattRAC(max) can be met. tRAD(max) is specified as a reference pOint only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tM'

TIMING DIAGRAMS
READ CYCLE
~---------------------tRC--------------------~

HAS

CAS

vlII VIL -

V1H V1L -

Q VOH -

VOL -

----------

240021-5

~Don·tCare

240021-6

3-6

inter

21256

TIMING DIAGRAMS (Continued)
WRITE CYCLE (EARLY WRITE)
t Rc
t RAS
RAS

V1H V1L -

CAS

V1H V1L -

tAR

I RSH
tCAS

240021-7

READ-WRITE/READ-MODIFY-WRITE CYCLE
t RWC
t RAS
RAS

V1H -

tAR

V1L t RSH

CAS

V1H V1L -

tCAS

240021-8

~Don·tcare

240021-6

3-7

inter

21256

TIMING DIAGRAMS (Continued)
PAGE MODE READ CYCLE
~------------------------tRASP--------------------~----~

o VOH - ------+.:....-{K
VOL -

V1H -

.............x.......,......OJ

V1L -

240021-9

PAGE MODE WRITE CYCLE (EARLY WRITE)

WVIH-~:"7I:~~~~
V1L -

.t...::.~~~"-l.~fIL+'-~=~~~~+:--~~~IUj"-\'~~iCfI-:--~~~IL.lo~~~

o V1H - ~:fu~:fu'\l~:-:-=::i"'7\Jv,,:,::,:-:-=':""'IVi:7\.rv~ },.,¥----,j.J<:~~:"7I:"7t"':'Tf:'7
V1L -

o VOH VOL -

..............

+.....,~

___

i'~.Y·

____

.T'''-lo~~

----------------OPEN---------------240021-10

~Don'tCore

240021-6

3-8

21256

TIMING DIAGRAMS (Continued)
PAGE MODE READ-WRITE CYCLE

Q VOH -

VOL -

---------(JXXI

-s.....;;;;~~

240021-14

3-9

21256

TIMING DIAGRAMS (Continued)
RAS-ONLY REFRESH CYCLE
i----------tRc---------l

Q VOH- _ _ _ _ _ _ _ _ _ _ _ OPEN _ _ _ _ _ _ _ _ _ _ _ _ _ __

VOL -

240021-11

NOTE:
CAS = VIH:

IN,

D = Don't Care

HIDDEN REFRESH CYCLE

QVOH VOL -

----240021-12

~Oonltcare

240021-6

3-10

inter

21256

TIMING DIAGRAMS (Continued)
CAS-BEFORE-RAS REFRESH CYCLE

i---------tRc--------.J

V1H V1L -

CAS

VOH VOL -

----------------------------OPEN--~----------------------------240021-13

NOTE:
Address,

'N,

D = Don't Care

Don't Care

240021-6

3-11

21256

TIMING DIAGRAMS (Continued)
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE

RAS V1H
V1L

=-----'\1

1----------tRAs--------------i

foo~----tRsH--------l

1,---,

READ CYClE
Q~H-

_____________________

_+~~--_Q.X

VOL -

WRITE CYCLE
f+--++-----tRWL---+--i

QVOH- _________________ OP~--------~~~---------------~----r_----------VOL -

WV1H V1L -

~~fu~~fu7l\1\7'\A.7I\1\7'\A.~
~~~~~.lL.:~!J,t;ilL.:~!J,t;~~~~-I-!-----~~~~¥-l~~~~~~~~

READ-WRITE CYCLE

W V1H V1L -

D V1H V1L -

~~~.K..~'_lj~~.K..~'_lj~.K.N

4o..li~~.K.~_'_lj~~.K..~'_lj~~.K..~_'_¥~....

1'-.-0---'[" ___.....~.K.~_.....00K.. .
240021-18

moon.teare

240021-6

3-12

intJ

21256

DEVICE OPERATION

Write

The 21256 contains 262,144 memory locations.
Eighteen address bits are required to address a particular memory location. Since the 21256 has only 9
address input pins, time multiplexed addressing is
used to input 9 row and 9 column addresses. The
multiplexing is controlled by the timing relationship
between the row address strobe (RAS), the column
address strobe (CAS) and the valid address inputs.

The 21256 can perform early write, late write and
read-modify-write cycles. The difference between
these cycles is in the state of data-out and is determined by the timing relationship between Wand
CAS. In any type of write cycle, data-in must be valid
at or before the falling edge of W or CAS, whichever
is later.
Early Write: An early write cycle is performed by
bringing W low before CAS. The data at the data
input pin (D) is written into the addressed memory
cell. Throughout the early write cycle the output remains in the Hi-Z state. This cycle is good for common liD applications because the data-in and dataout pins may be tied together without bus contention.

Operation of the 21256 begins by strobing in a valid
row address with RAS while CAS remains high.
Then the address on the 9 address input pins is
changed from a row address to a column address
and is strobed in by CAS. This is the beginning of
any 21256 cycle in which a memory location is accessed. The specific type of cycle is determined by
the state of the write enable pin and various timing
relationships. The cycle is terminated when both
RAS and CAS have returned to the high state. Another cycle can be initiated after RAS remains high
long enough to satisfy the RAS precharge time (tRP)
requirement.

Read-Modify-Write: In this cycle, valid data from
the addressed cell appears at the output before and
during the time that data is being written into the
same cell location. This cycle is achieved by bringing
W low after CAS and meeting the data sheet readmodify-write cycle timing requirements. This cycle
requires using a separate liD to avoid bus contention.

RAS and CAS Timing

Late Write: If W is brought low after CAS, a late
write cycle will occur. The late write cycle is very
similar to the read-modify-write cycle except that the
timing parameters, tRWO and lewo, are not necessarily met. The state of data-out is indeterminate
since the output could be either Hi-Z or contain data
depending on the timing conditions. This cycle requires a separate I/O to avoid bus contention.

The minimum RAS and CAS pulse widths are specified by tRAS(min) and tCAS(min) respectively. These
, minimum pulse widths must be satisfied for proper
device operation and data integrity. Once a cycle is
initiated by bringing RAS low, it must not be aborted
prior to satisfying the minimum RAS and CAS pulse
widths. In addition, a new cycle must not begin until
the minimum RAS precharge time, tRP, has been
satisfied. Once a cycle begins, internal clocks and
other circuits within the 21256 begin a complex sequence of events. If the sequence is broken by violating minimum timing requirements, loss of data integrity can occur.

Data Output
The 21256 has a tri-state output buffer which is controlled by CAS (and W for early write). Whenever
CAS is high (VIH) the output is in the high impedance
(Hi-Z) state. In any cycle in which valid data appears
at the output, the output first remains in the Hi-Z
state until the data is valid and then the valid data
appears at the output. The valid data remains at the
output until CAS returns high. This is true even if a
new RAS cycle occurs (as in hidden refresh). Each
of the 21256 operating cycles is listed below after
the corresponding output state produced by the cycle.

Read
A read, cycle is achieved by maintaining the write
enable input (W) high during a RAS/CAS cycle. The
output of the 21256 remains in the Hi-Z state until
valid data appears at the output. If CAS goes low
before tRCO(max), the access time to valid data is
specified by tRAC. If CAS goes low after tRCO(max),
the access time is measured from CAS and is specified by tCAC. In order to achieve the minimum access time, tRAc(min), it is necessary to bring CAS
low before tRCO(max).

Valid Output Data: Read, Read-Modify-Write, Hidden Refresh, Page Mode Read, Page Mode ReadModify-Write.

3-13

intJ

21256

HI-Z Output State: Early Write, RAS-only Refresh,
Page Mode Write, CAS-before-RAS Refresh, CASonly cycle.
Indeterminate Output State: Delayed Write

Refresh
The data in the 21256 is stored on a tiny capacitor
within each memory cell. Due to leakage, the data
will leak off after a period of time. To maintain data
integrity it is necessary to refresh each of the rows
every 4 ms. There are several ways to. accomplish
this.
RAS-Only Refresh: This is the most common method for performing refresh. It is performed by strobing
in a row address with RAS while CAS remains high.
CAS-before-RAS Refresh: The 21256 has CAS-before-RAS on-chip refreshing capability that eliminates the need for external refresh addresses. If
CAS is held low for the specified setup time (tCSR)
before RAS goes low, the on-chip refresh circuitry is
enabled. An internal refresh operation automatically
occurs and the on-chip refresh address counter is
internally incremented in preparation for the next
CAS-before-RAS refresh cycle.

read-modify-cycles. As long as the applicable timing
requirements are observed, it is possible to mix
these cycles in any order. A~e mode cycle begins
with a normal cycle. While RAS is kept low to maintain the row address, CAS is cycled to strobe in additional column addresses. This eliminates the time
required to set up and strobe sequential row addresses for the same page.

CAS-before-RAS Refresh Counter Test
Cycle
A special timing sequence using the CAS-beforeRAS counter test cycle provides a convenient method of verifying the functionality of the CAS-beforeRAS refresh activated circuitry.
After the CAS-before-RAS refresh operation, if CAS
goes high and then low again while RAS is held low,
the read and write operations are enabled.
This is shown in the CAS-before-RAS counter test
cycle timing diagram. A memory cell can be addressed with 9 row address bits and 9 column address bits defined as follows:
Row Address-Bits AO through A7 are supplied by
. the on-chip refresh counter. The AS bit is set high
internally.

Hidden Refresh: A hidden refresh cycle may be
performed while maintaining the latest valid data at
the output by extending the CAS active time and
cycling RAS. The 21256 hidden refresh cycle is actually a CAS-before-RAS refresh cycle within an extended read cycle. The refresh row address is provided by the on-chip refresh address counter. This
eliminates the need for the external row address
that is required in hidden refresh cycles by DRAMs
that do not have CAS-before-RAS refresh capability.

Column Address-Bits AO through AS are strobedin by the falling edge of CAS as in a normal memory
cycle.

Suggested CAS-before-RAS Counter
Test Procedure
The CAS-before-RAS refresh counter test cycle timing is used in each of the following steps:
1. Initialize the internal refresh counter by performing S cycles.
2. Write a test pattern of "lows" into the memory
cells at a single column address and 256 row addresses. (The row addresses are supplied by the
on-chip refresh counter.)
3. Using read-modify-write cycles, read the "lows"
written during step 2 and write "highs" into the
same memory locations. Perform this step 256
times so that highs are written into the 256 memory cells.
4. Read the "highs" written during step 3.
5. Complement the test pattern and repeat steps 2,
3 and 4.

Other Refresh Methods: It is also possible to refresh the 21256 by using read, write or read-modifywrite cycles. Whenever a row is accessed, all the
cells in that row are automatically refreshed. There
are certain applications in which it might be advantageous to perform refresh in this manner but in general RAS-only· or CAS-before-RAS refresh is the preferred method.

Page Mode
The 21256 has page mode capability. Page mode
memory cycles provide faster access and lower
power dissipation than normal memory cycles. In
page mode, it is possible to perform read, write or

3-14

inter

21256

ground lines act like transmission lines to the high
frequency transients generated by DRAMs. The impedance is minimized if all the power supply traces
to all DRAMs run both horizontally and vertically and
are connected at each intersection or better yet if
power and ground planes are used.

Power-Up
If RAS = Vss during power-up, the 21256 could begin an active cycle. This condition results in higher
than necessary current demands from the power
supply during power-up. It is recommended that
RAS and CAS track with Vee during power-up or be
held at a valid VIH in order to minimize the power-up
current.

Address and control lines should be as short as possible to avoid skew. In boards with many DRAMs
these lines should fan out from a central point like a
fork or comb rather than being connected in a serpentine pattern. Also the control logic should be
centrally located on large memory boards to facilitate the shortest possible address and control lines
to all the DRAMs.

An initial pause of 100 fts is required after power-up
followed by 8 initialization cycles before proper device operation is assured. 8 initialization cycles are
also required after any 4 ms period in which there
are no RAS cycles. An initialization cycle is any cycle
in which RAS is cycled.

Decoupling
Termination

The importance of proper decoupling cannot be over
emphasized. Excessil(e transient noise or voltage
droop on the Vee line can cause loss of data integrity (soft errors). The total combined voltage changes
over time in the Vee to Vss voltage (measured at
the device pins) should not exceed 500 mV.

The lines from the TIL driver circuits to the 21256
inputs act like unterminated transmission lines resulting in significant positive and negative overshoots at the inputs. To minimize overshoot it is advisable to terminate the inpu~ lines and to keep them
as short as possible. Although either series or parallel termination may be used, series termination is
generally recommended since it is simple and draws
no additional power. It consists of a resistor in series
with the input line placed close to the 21256 input
pin. The optimum value depends on the board layout. It must be determined experimentally and is
usually in the range of 200 to 400.

A high frequency 0.3 ftF ceramic decoupling capacitor should be connected between the Vee and
ground pins of each 21256 using the shortest possible traces. These capacitors act as a low impedance
shunt for the high frequency switching transients
generated by the 21256 and they supply much of the
current used by the 21256 during cycling.
In addition, a large tantalum capacitor with a value of
47 p.F to 100 ftF should be used for bulk decoupling
to recharge the· 0.3 ftF capacitors between cycles,
thereby reducing .power line droop. The bulk decoupiing capacitor should be placed near the point
where the power traces meet the power grid or power plane. Even better results may be achieved by
distributing more than one tantalum capacitor
throughout the memory array.

3-15

21256

PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL-IN-LINE PACKAGE

~50·20

I
~~~J
~-------A--------~.I

- . . . - f - - SEATING
PLANE

K
240021-15

Item

Millimeters

Inches

19.43 ±0.05

0.765 ± 0.002

6.86 ±0.05

0.270 ± 0.002

7.62

0.300

0.25 ±0.025

0.010 ±0.001

3.56 ±0.05

0.140 ±0.002

0.506 ±0.1

0.020 ± 0.004

3.3 ±0.1

0.130 ± 0.004

2.54

0.100

1.52

0.060

0.457 ±0.05

0.Q18 ± 0.002

0.1 ±0.05

0.040 ± 0.002

3-16

21256

PACKAGE DIMENSIONS (Continued)
18-PIN PLASTIC LEADED CHIP CARRIER

~--------L--------~

240021-16

Item

Millimeters

Inches

12.346 ±0.052

0.490 ± 0.002

13.2585 ± 0.0505

0.522 ± 0.002

7.366 ±0.051

0.290 ± 0.002

8.179 ±0.051

0.322 ± 0.002

2.083 ±0.051

0.082 ± 0.002

3.505 ±0.051

0.020 ± 0.004

0.7365 ±0.0505

0.029 ± 0.002

6.553 ±0.051

0.258 ±0.002

0.43 typ

0.017typ

0.279 ± 0.025

0.011 ± 0.001

0.76 typ

0.030typ

11.8365 ± 0.0505

0.466 ± 0.002

0.1 ±0.05

0.04 ±0.002

3-17

inter

21256

PACKAGE DIMENSIONS (Continued)
16-LEAD ZIG ZAG INLINE PACKAGE (ZIP)
1-------0.808- 0.812-----.f,!

·"'-nn
. '''Q....
,f \
MIN. 0 . 1 2 0 L

I
0.068 - 0.072

~
-11-0.008 - 0.Q12

3-18

-0.050 TYP.

--1-0.100 TYP.
240021-17

21464

65,536 x 4-BIT DYNAMIC RAM WITH PAGE MODE
Parameter

21464-06

21464-07

21464-08

21464-10

Units

tRAG

Access Time from RAS

100

tGAG

Access Time from CAS

tRG

Read Cycle Time

110

130

150

190

Symbol

Write or Output Enable Controlled
• Early
Write
+ 5V ± 10% Power Supply.
• Single
256 Cycle/4 ms Refresh
• JEDEC Standard Pinout in DIP, PLCC,
• ZIP

Mode Capability
• Page
CAS-Before-RAS Refresh Capability
• RAS-Only and Hidden Refresh
• Capability
• TTL Compatible Inputs and Outputs

The 21464 is a fully decoded 65,536 x 4 dynamic random access memory. The design is optimized for high
speed, high performance applications such as computer memory, buffer memory, peripheral storage and
environments where low power dissipation and compact layout are required.
The 21464 features page mode which allows high speed random access of memory cells within the same row.
CAS-before-RAS refresh capability provides on-chip auto refresh as l1n alternative to RAS-only refresh. Multiplexed row and column address inputs permit the 21464 to be housed in a standard 18-pin DIP.
Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and outputs are

TTL compatible.

RAS-.r-----'
CAS

DATA
IN
BUFF

Vi -?L-r--r--.......

COLUMhI DECODER
SENSE AMPS &: I/O GATINGS

A
D
D

R
0
W

B
U
F
F
E
R
S

D
E
C

MEMORY ARRAY
262, 144 CELLS

0
D
E
R

+-Vcc
+-Vss

240022-1

Figure 1. Functional Block Diagram

3-19

October 1990
Order Number: 240022-005

inter

21464

DIP

PLCC
DO, OE VSSD04

VSS

DO,

D0 4

D0 2

CAS

D0 3

RAS
A6
A5
A4
Vee

t~J
D0 2

AO
A,
A2
A3
A7

RAS

51
-~

(TOP VIEW)

Vee

A7 A3
240022-3

Figure 2. Pin Configurations
PIN NAMES

~l A2

ZJ
f81 f91 fl-01 f1-11

240022-4

Vee
Vss

D0 3

~j AO

r,"3

A6 ~]

ZIP

RAS
CAS

U~ CAS

V§

•

Vi ~J

240022-2

Ao-A7
DQ1-DQ4

L!J ~~J t1..?J

Address Input
Data In/Out
Read/Write Input
Row Address Strobe
Column Address Strobe
Power (+5V)
Ground
Output Enable

3-20

inter

21464

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin
Relative to vss ................... -1 V to

NOTICE: This is a production data sheet. The specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

+ 7V

Voltage on Vee Supply
Relative to Vss ................... -1 V to
Storage Temperature .......... - 55°C to

+ 7V
+ 125°C

Power Dissipation ...................•...... 1.0W
Short Circuit Output Current ................ 50 mA

RECOMMENDED OPERATING CONDITIONS
Symbol

Voltages referenced to Vss. TA = 0 to 70°C

Parameter

Min

Typ

Max

Units

Vee

Supply Voltage

4.5

5.0

5.5

VSS

Ground

VIH

Input High Voltage

2.4

VIL

Input Low Voltage

-1.0

3-21

0
Vee

0.8

V
V

21464

D.C. OPERATING CHARACTERISTICS
Recommended operating conditions unless otherwise noted

Parameter

Symbol

Min

Max

Units

Test Condition

ICC1

Operating Current'

21464-06
21464-07
21464-08
21464-10

75
70
65
55

mA
mA
mA
mA

RAS and CAS Cycling
@tRC = Min

ICC2

Standby Current

21464-06
21464-07
21464-08
21464-10

2.0
2.0
2.0
5.0

mA
mA
mA
mA

HAS = CAS = VIH

ICC3

RAS-Only Refresh Current'

21464-06
21464-07
21464-08
21464-10

75
70
60
40

mA
mA
mA
mA

CAS = VIH, RAS Cycling
@tRC = Min

ICC4

Page Mode Current·

21464-06
21464-07
21464-08
21464-10

50
45
40
35

mA
mA
mA
mA

RAS = VIL, CAS Cycling:
tpc = Min

ICC5

CAS-Before-RAS'
Refresh Current

21464-06
21464-07
21464-08
21464-10

75
70
65
55

mA
mA
mA
mA

RAS Cycling @ tRC = Min

IlL

Input Leakage Current

-10

}LA

Any Input 0 s:: VIN s:: 5.5V,
VCC = 5.5V, Vss = OV, All Other
Pins Not Under Test = OV

.'Output Leakage Current

-10

}LA

Data Out is Disabled, OV s:: Your
s:: 5.5V, Vcc = 5.5V, Vss = OV

IDOL
VOH

Output High Voltage Level

VOL

Output Low Voltage Level

2.4
0.4

IOH = 5mA

IOL = 4.2mA

NOTE:
'Icc is dependent on output loading and cycle rates. Specified values are obtained with the output open. IcC is specified as
an average current.
.

CAPACITANCE TA ~
Symbol

25 D C

Parameter

Max

Unit

CIN1

Input Capacitance (Ao-A7)

Min

CIN2

Input Capacitance (RAS, CAS, W, OE)

Coa

Output Capacitance (001- D04)

3-22

A.C. CHARACTERISTICS
Symbol

(O°C ~ T A ~ 70°C = 5.0V

Parameter

Min

c:.u

N
c:.u

± 10%. See notes 1, 2)

21464-06
Max

21464-07
Min

Max

21464-08
Min

Max

21464-10
Min

tRC

Random Read or Write Cycle Time

120

135

150

190

tRWC

Read-Modify-Write Cycle Time

165

195

225

265

tRAC

Access Time from RAS

tCAC

Access Time from CAS

tAA

Access Time from Column Address

Notes

ns
ns

100

3,4,11

3,4,5

3, 10

100

tClZ

CAS to Output in Low-Z

tOFF

Output Buffer Turn-Off Delay

Transition Time (Rise and Fall)

tRP

RAS Precharge Time

tRAS

RAS Pulse Width

tRSH

RAS Hold Time

tCPN

CAS Precharge Time
(All Cycles Except Page Mode)

tCAS

CAS Pulse Width

tCSH

CAS Hold Time

tRCD

RAS to CAS Delay Time

tRAD

RAS to Column Address Delay Time

n's

tCRP

CAS to RAS Precharge Time
(RAS Only Refresh)

65
10,000

75
10,000

80
10,000

100

(

Max

Units

ns
10,000

ns
I\)

10,000

100

""
""

O'l

ns
ns

tASR

Row Address Set-Up Time

tRAH

Row Address Hold Time

tASC

Column Address Set-Up Time

tCAH

Column Address Hold Time

tAR

Column Address Hold Time
Referenced to RAS

A.C. CHARACTERISTICS
Symbol

Parameter

21464-06
Min

'"
~

tRAL

Column Address to RAS Lead Time

tRCS
tRCH
tRRH

(

± 10%. See notes 1, 2) (Continued)

(O°C s T A S 70°C = 5.0V

Max

21464-07
Min

Max

21464-08
Min

Read Command Set-Up Time

Read Command Hold Time
Referenced to CAS

Read Command Hold Time
Referenced to RAS

twcs

Write Command Set-Up Time

tWCH

Write Command Hold Time

twp

Write Command Pulse Width

Max

21464-10
Min

Units

Notes

Max

tRWL

Write Command to RAS Lead Time

tCWL

Write Command to CAS Lead Time

tos

Data-In Set-Up Time

....
I\)

01:>0

tOH

Data-In Hold Time

tcwo

CAS to Write Enable Delay

tRWO

RAS to Write Enable Delay

100

110

135

tAWO

Column Address to W Delay Time

tWCR

Write Command Hold Time
Referenced to RAS

tOHR

Data-In Hold Time
Referenced to RAS

tOEA

Access Time from OE

tOEO

OE to Data in Delay Time

tOEZ

Output Buffer Turn Off Delay from OE

tOEH

OE Hold Time Referenced to W

tREF

Refresh Period (256 Cycles)

15
15

20
20

15
15

20
20

30
20

ns
ns

20
---

20
25

ns
ns

A.C. CHARACTERISTICS
Symbol

± 1 0%.

(O°C :;, T A :;, 70°C = 5.0V

Parameter

21464-06
Min

Max

21464-07
Min

Max

21464-08
Min

Max

21464-10
Min

Units

CAS Set-Up Time
(CAS-Before-RAS Refresh)

tCHR

CAS Hold Time
(CAS-Before-RAS Refresh)

tRPC

RAS Precharge to CAS Hold Time

tCPT

Refresh Counter Test
CAS Precharge

tpc

Page Mode Cycle Time

tcp

CAS Precharge Time (Page Mode Only)

tCPA

Access Time from CAS Precharge

tPRWC

Fast Page Mode Read-Modify-Write

tRASP

RAS Pulse Width (Fast Page Mode)

tROH

RAS Hold Time Referenced to OE

15
40

15
45

105
10,000

30
50

120
10,000

100

10,000

C11

ns
55

140
10,000

Notes

Max

tCSR

See notes 1, 2) (Continued)

NOTES:
1. An initial pause of 200 fLs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved.
2. VIN(min) and Vldmax) are referenced levels for measuring timing of input signals. Transition times are measured between VIH(min) and Vldmax) and are assumed to be 5 ns
for all inputs.
3. Measured with a load equivalent to 2 TIL loads and 100 pF.
4. Operation within the tRCO(max) limit insures that tRAc(max) can be met. tRco(max) is specified as a reference point only. If tRCO is greater than the specified tRCO(max) limit,
then access time is controlled exclusively by tCAC.
5. Assumes that tRco :?: tRCO(max).
6. tAR, tWCR, tOHR are referenced to tRAo(max).
7. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL'
8. twcs, tRWO, tcwo and tAWO are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs :?: twcs(min) the cycle is
an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tcwo :?: tcwo(min) and tRWO :?: tRWO(min) and tAWO :?: tRWO(min) and
tAWO :?: tAWO(min), then the cycle is a read-write cycle and the data out will contain the data read from the selected address. If neither of the above conditions are satisfied,
the condition of the data out is indeterminate.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write cycles.
11. Operation within the tRAO(max) limit insures that tRAc(max) can be met. tRAO(max) is specified as a reference point only. If tRAo is greater than the specified tRAO(max)
limit, then access time is controlled by tAA.

...
I\)

en
"'"
"'"

21464

TIMING DIAGRAMS
READ CYCLE
IRe
I RP
RAS

CAS

V'H VIL -

V1H Vil. -

V1H VIL -

DO,-DO.

V'H VIL -

V1H VIL -

~DH

----OPEN
DL -

240022-5

WRITE CYCLE (EARLY WRITE)

IDHR~
I-tDH

IDSg

~~~~!:~------

1H
VVIL -_ - - - - - - ~'!lID o~

OPEN-------

240022-7

NOTE:

~ DOH'T~ARE

OE = Don't Care

240022-6

3-26

infef

21464

TIMING DIAGRAMS

(Continued)

WRITE CYCLE (OE CONTROLLED WRITE)

V1H -

RAS

Vil -

CAS

DQ,-DQ4

V1H -

V1L V1H V1l -

V1H V1L -

240022-8

READ-MODIFY-WRITE CYCLE

~--------------------~WC--------------------~
~-----------------t~s----------------~

RAS

V1H V1L -

....;.._ _-,iJ----tAR

~__+---------tRSH-----------+_l

CAS

V1H V1L -

V'H V1L -

DO
,-

J;:::j.j:::=~!:;:::j~t-------tCAS--------Ir+....,.

__"'\

V 1H -

V1L V1H V1L -

DO VI/OH 4 VI/OL -

240022-9

DON'T CARE

240022-6 •

3-27

intJ

21464

TIMING DIAGRAMS

(Continued)

PAGE MODE READ CYCLE

RAS

,V'H V'L -

CAS

V'H V'L -

OQ,-OQ4

VOH VOL -

240022-10

PAGE MODE WRITE CYCLE

RAS

V'H V'L -

CAS

V'H V'L -

V1H V'L -

V1H V1L . -

OQ,_OO4

V1H V'L -

240022-11

NOTE:
OE = Don't Care

DON'T CARE

240022-6

3-28

21464

TIMING DIAGRAMS

(Continued)

PAGE MODE READ-MODIfY-WRITE CYCLE

V1H V1L -

240022-18

DON'T CARE

240022-6

3-29

21464

TIMING DIAGRAMS

(Continued)

RA8--0NLY REFRESH CYCLE

1----------tRc----------i

V1H -

~:A.7'V\7'\"''O\ .T.....:-----i.,~:""7'r~~~""l"r"7r"'l~:""7'r~~~""l"r"7r"'l~:""7'r~

V1L -

~~~Q/.~~ ~-----.;r"..K..x..l~~~~~..K..x..l~~~~~..K..x..l~

DATA VOH -

--------------HIGH-Z--------------

ADDRESS

(OUT) VOL -

240022-12

NOTE:

CAS

= VIH;

VIi,

OE, D = Don't Care.

CA8--BEFORE-RAS REFRESH CYCLE

i--------tRc-------..J

DATA

VOH - ----:LI>-_ _ _ _ _ _ _ _ _ _ _ _ _ HIGH_Z __________.....,__

(OUT) VOL 240022-13

NOTE:
Address VIi, OE, D = Don't Care.

DON"TCARE

240022-6

3-30

21464

TIMING DIAGRAMS

(Continued)

HIDDEN REFRESH CYCLE (READ)

RAS

CAS

VIH V1L -

VIH -

Vit. -

VIH V1L -

DO,-DQ,

VIH -

V1L -

240022-14

DON'T CARE

240022-6

HIDDEN REFRESH CYCLE (WRITE)

RAS

CAS

DO,_DO,

VIH -

V1L -

VIH -

V1L -

VIH V1L -

VIH -

V1L -

VIH V1L -

VIH -

Vil f-----tDH.--~

240022-19

~
240022-6

3-31

DON'T CARE

21464

TIMING DIAGRAMS

(Continued)

CAS-BEfORE-RAS REfRESH COUNTER TEST CYCLE
~----------------tAAS----------------~
RAS

V1H V1L -

CAS

V1H V1L -

t---------tRsH--------+/
1~----_(t--------tCAS------~~~---------

READ CYCLE
Vi

V1H V1L -

OQ1_0Q 4

VOH VOL -

OPEN

WRITE CYCLE
Vi

V1H V1L -

OQ1- oo4

V1H V1L -

OQ1_0Q4

VI/OH VI/OL -

240022-20

DON'T CARE

240022-6

3-32

21464

tRCO(max), the access time is measured from CAS
and is specified by tCAC. In order to achieve the minimum access time, tRAdmin), it is necessary to bring
CAS low before tRCO(max).

DEVICE OPERATION
The 21464 contains 262,144 memory locations organized as 65,536 4-bit words. Sixteen address bits
are required to address a particular 4-bit word in the
memory array. Since the 21464 has only 8 address
input pins, time multiplexed addressing is used to
input 8 row and 8 column addresses. The multiplexing is controlled by the timing relationship between
the row address strobe (RAS) , and the column address strobe (CAS) and the valid address inputs.

Write
The 21464 can perform early write and read-modifywrite cycles. The difference between these cycles is
in the state of data-out and is determined by the
timing relationship between W, OE and CAS. In any
type of write cycle Data-in must be valid at or before
the falling edge of W or CAS, whichever is later.

Operation of the 21464 begins by strobing in a valid
row address with RAS while CAS remains high.
Then the address on the 8 address input pins is
changed from a row address to a column address
and is strobed in by CAS. This is the beginning of
any 21464 cycle in which a memory location is accessed. The specific type of cycle is determined by
the state of the write enable pin and various timing
relationships. The cycle is terminated when both
RAS and CAS have returned to the high state. Another cycle can be initiated after RAS remains high
long enought to satisfy the RAS precharge time (tRP)
requirement.

Early Write: An early write cycle is performed by
bringing W low before CAS. The 4-bit wide data at
the data input pins is written into the addressed
memory cells. Throughout the early write cycle the
outputs remain in the Hi-Z state regardless of the
state of the OE input.
Read-Modify-Write: In this cycle, valid data from
the addressed cells appears at the outp'uts before
and during the time that data is being written into the
sam~cell locations. This cycle is achieved by bringing W low after CAS and meeting the data sheet
read-modify-write timing requirements. The output
enable input (OE) must be low during the time defined by tOEA and toEZ for data to appear at the
outputs. If tewo and tRWO are not met the output
may contain invalid data. Conforming to the OE timing requirements prevents bus contention on the
21464 DQ pins.

RAS and CAS Timing
The minimum RAS and CAS pulse widths are specified by tRAS(min) and tcAS(min) respectively. These
minimum pulse widths must be satisfied for proper
device operation and data integrity. Once a cycle is
initiated by bringing RAS low, it must not be aborted
prior to satisfying the minimum RAS and CAS pulse
widths. In addition, a new cycle must not begin until
the minimum RAS precharge time, tRP, has been
satisfied. Once a cycle begins, internal clocks and
other circuits within the 21464 begin a complex sequence of events. If the sequence is broken by violating minimum timing requirements, loss of data integrity can occur.

Data Output
The 21464 has tri-state output buffers which are
controlled by CAS and OE. When either CAS or OE
is high (VIH) the outputs are in the high impedance
(Hi-Z) state. In any cycle in which valid data appears
at the outputs, the outputs first remain in the Hi-Z
state until the data is valid and then the valid data
appears at the outputs. The valid data remains at the
outputs until either CAS or OE returns high. This is
true even if a new RAS cycle occurs (as in hidden
refresh). Each of the 21464 operating cycles is listed
below after the corresponding output state produced
by the cycle.

Read
A read cycle is achieved by maintaining the write
enable input (W) high during a RAS/CAS cycle. The
four outputs of the 21464 remain in the Hi-Z state
until valid data appears at the outputs. The 21464
has common data 1/0 pins. For this reason an output enable control input (OE) has been provided so
the output buffer can be precisely controlled. For
data to appear at the outputs, OE must be low for
the period of time defined by tOEA and toEZ. If CAS
goes low before tRCO(max), the access time to valid
data is specified by tRAC. If CAS goes low after

Valid Output Data: Read, Read-Modify-Write, Hidden Refresh, Page Mode Read, Page Mode, ReadModify-Write.
Hi-Z Output State: Early Write, RAS-Only Refresh,
Page Mode Write, CAS-Only CyCle.

3-33

inter

21464

strobe in additional column addresses. This eliminates the time required to set up and strobe sequential row addresses for the same page.

Indeterminate Output State; Delayed Write (tewD
or tRWD are not met).

Refresh

Power-Up

.The data in the 21464 is stored on a tiny capacitor
within each memory cell. Due to leakage the data
will'leak off after a period of time. To maintain data
integrity it is necessary to refresh each of the rows
every 4 ms. There are several ways to accomplish
this.

If RAS = Vss during power-up, the 21464 might
begin an active cycle. This condition results in higher
than necessary current demands from the power
supply during power-up. It is recommended that AS
and CAS track with Vee during power-up or be held
at a valid VIH in order to minimize the power-up current.

RAS-Only Refresh: This is the most common method for performing refresh. It is performed by strobing
in a row address with RAS while CAS remains high.
'This must be performed on each of the 256 row addresses (Ao-A7) every 4 ms.
CAS-Before-RAS Refresh: The 21464 has CASBefore-RAS refresh capability that eliminates the
need for external refresh addresses. If CAS is held
low for the specified set-up time (tesR) before RAS
goes low, the on-chip refresh circuity is enabled. An
internal refresh operation automatically occurs and
the on-chip refresh address counter is internally incremented in preparation for the next CAS-BeforeRAS refresh Cycle:
Hidden Refresh: A hidden refresh cycle may be
performed while maintaining the lastest valid data at
the outputs by extending the CAS active time and
cycling RAS. The 21464 hidden refresh cycle is actually a CAS-Before-RAS refresh cycle within an extended read cycle. The refresh row address is provided by the on-chip refresh address counter. This
eliminates the need for the external row address
that is required in hidden refresh cycles by DRAMS
that do not have CAS-Before-RAS refresh capability.

An initial pause of 100 p.s is required after power-up
followed by 8 initialization cycles before proper device operation is assured. Eight initializations cycles
are also required after an 4 ms period in which there
are no RAS cycles. An initialization cycle is any cycle
in which RAS is cycled.
I

Termination
The lines from the TTL driver circuits to the 21464
inputs act like unterminated transmission lines resulting in significant positive and negative overshoots at the inputs. To minimize overshoot it is advisable to terminate the input lines and to keep them
as short as possible. Although either series or parallel termination may be used, series termination is
generally recommended since it is simple and draws
no additional power. It consists of a resistor in series
with the input line placed close to the 21464 input
pin. The optimum value depends on the board layout. It must be determined experimentally and is
usually in the range of 20.0. to 40.0..

Board Layout

Other Refresh Methods: It is also possible to refresh the 21464 by using read, write or read-modifywrite cycles. Whenever a row is accessed all the
cells in that row are automatically refreshed. There
are certain applications in which it might be advantageous to perform refresh in this manner but in general RAS-only or CAS-Before-RAS refresh are the preferred methods.

It is important to layout the power and ground lines
on memory boards in such a way that switching transient effects are minimized. The recommended
methods are gridded power and ground lines or separate power and ground planes. The power and
ground lines act like transmission lines to the high
frequency transients generated by DRAMs. The impedance is minimized if all the power supply traces
to all the DRAMs run both horizontally and vertically
and. are connected at each intersection, or better
yet, if power and ground planes are used.

Page Mode
Page mode memory cycles provide faster access
and lower power dissipation than normal memory
cycles. In page mode, it is possible to perform read,
write or read-modify-write cycles. As long as the applicable timing requirements are observed, it is possible to mix these cycles in any order. A page mode
cycle begins with a normal cycle. While RAS is kept
low to maintain the row address, CAS is cycled to

Address and control lines should be as short as possible to avoid skew. In boards with many DRAMs
these lines should fan out from a central point like a
fork or comb rather than being connected in a serpentine pattern. Also the control logiC should be
centrally located on the memory boards to facilitate

3-34

21464

the shortest possible address and control lines to all
the DRAMs.

ground pins of each 21464 using the shortest possible traces. These capacitors act as a low impedance
shunt for the high frequency switching transients
generated by the 21464 and they supply much of the
current used by the 21464 during cycling.

Decoupling
The importance of proper decoupling cannot be
overemphasized. Excessive transient noise or voltage droop on the Vee line can cause loss of data
integrity (soft errors). The total combined voltage
changes over time in the Vee to Vss voltage (measured at the device pins) should not exce,ed 500 mV.

In addition, a large tantalum capacitor with a value of
47 ILF to 100 ILF should be used for bulk decoupling
to recharge the 0.3 ILF capacitors between cycles,
thereby reducing power line droop. The bulk decoupiing capacitor shuld be placed near the point where
the power traces meet the power grid or power
plane. Even better results may be achieved by distributing more than one tantalum capacitor around
the memory array.

A high frequency 0.3 ILF ceramic decoupling capacitor should be connected between the Vee and

PACKAGE DIMENSIONS
l8-LEAD PLASTIC DUAL IN·LINE PACKAGE

~ ~ ~ -"r.lI'" "l:~ "r': I(E.,J~ECTr°,!:R"=rM.,A~RKr)rP: r-r I
I.

r -........................................

~SEATING

PLANE

----1

240022-15

Item

Millimeters

Inches

22.950 ± 0.05

0.903 ± 0.002
0.252 ± 0.002

6.40 ± 0.05

7.62

0.300

0.025 ± 0.025

0.010 ± 0.001

3.25 ± 0.05

0.128 ± 0.002

0.506 ± 0.1

0.020 ± 0.004

3.302 ± 0.1

0.130 ± 0.004

2.54

0.100

1.27 ± 0.05

0.050 ± 0.002

0.457 ± 0.05

0.Q18 ± 0.002

1.32

0.052
3-35

inter

21464

PACKAGE DIMENSIONS

(Continued)

1S·PI" PLASTIC LEADED CHIP CARRIER

IT
D

[

~------L------~

240022-16

Item

Millimeters

Inches

Item

Millimeters

Inches

12.346 ± 0.052

0.490 ± 0.002

6.553 ± 0.051

0.258 ± 0.002

13.2585 ± 0.0505

0.522 ± 0.002

0.43 type

0.017typ

7.366 ± 0.051

0.290 ± 0.002

0.279 ± 0.025

0.011 ± 0.001

8.179 ± 0.051

0.322 ± 0.002

0.76 typ

O.030typ

2.083 ± 0.051

0.082 ± 0.002

11.8365 ± 0.0505

0.466 ± 0.002

3.505 ± 0.051

0.138 ± 0.002

6.756 ± 0.051

0.266 ± 0.002

0.7365 ± 0.0505

0.029 ± 0.002

20·LEAD ZIG·ZAG INLINE PACKAGE (ZIP)

1---------------- : :g~~

---------------1'1

o
I

o.olojL
REf.

0.01S-0.022J

0.fl50 TYP....

240022-17

3-36

21010
1,048,576 x 1-Bit Dynamic RAM with Page Mode
Performance Range

•

tRAC

tCAC

tRC

21010-06

60ns

20 ns

110 ns

21010-07

70 ns

20 ns

130 ns

21010-08

80 ns

20 ns

160 ns

21010-10

100 ns

25 ns

190 ns

• Single 5V

Fast Page Mode Operation

10% Power Supply

• CAS before RAS Refresh Capability

•

512 Cycles/S ms refresh

• Common I/O Using "Early Write"

•

Available in Plastic DIP, SOJ and ZIP
Packages

Intel 21010 is a CMOS high speed 1,048,576 x 1 dynamic RAM optimized for high performance applications
such as mainframes, graphics and microprocessor systems.
21010 features Fast Page Mode operation which allows high speed random access of memory cells within the
same row.
CAS before RAS refresh capability provides on-chip auto refresh as an alternative to RAS only refresh. All
Inputs, Output and Clocks are fully CMOS and TTL compatible.
Functional Block Diagram

"'---1..---'

.....,"""T-..~-----~~

iii .......

PIN CONFIGURATION
DIP

ZIP

SOJ

SENSE AMPS &: I/O GAnNGS
AD

...

MEMORY ARRA.Y
1048,576 CELLS

+-Vee
+-V55

240153-2

240153-16
240153-3

U L-L-L-_ _ _ _ _~
240153-1

NOTE:
T.F. = Test Function, Ground or No Connect

Pin Names
Ao-Ag Address Inputs

3-37

Read/Write Strobe

RAS

Row Address Strobe

CAS

Column Address Strobe

Data In

Data Out

VSS

Ground

Vee

Power +5V

August 1990
Order Number: 240153-005

21010

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Voltage on Any Pin Relative to vss
(VIN. VOUT) .................... -1V to + 7.0V

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
'may affect device reliability.

Voltage on Power Supply Relative to Vss
(Vcd ............... : .......... -1V to +7.0V
Storage Temperature (Tslg) ..... - 55°C to + 150°C
Power Dissipation (Pd) ................... 600 mW
Short Circuit Output Current (los) '........... 50 mA

RECOMMENDED OPERATING CONDITIONS
= O°C to + 70°C)

(Voltage Referenced to Vss. TA

Symbol

Parameter

Min

Typ

Max

Units

Vcc

Supply Voltage

4.5

5.0

5.5

Vss

Ground

VIH

Input High Voltage

2.4

VCC + 1

VIL

Input Low Voltage

-1.0

0.8

NOTES:

1. VIL (Min) = - 1.0V for continuous DC level.
2. VIL (Min) = -2.0V for pulse width < 20 ns.

Capacitance
Symbol

(TA = 25°C)

Parameter

Min

Max

Units
pF

Cinl

Input Capacitance (Ao-A9. D)

Cin2

Input Capacitance (RAS. CAS. WE)

Cout

Output Capacitance (0)

D.C. AND OPERATING CHARACTERISTICS
(Recommended Operating Conditions unless Otherwise Noted)

Symbol

Speed

Parameter

Min

Max

Units

ICCl
ICCl

Operating Current
(RAS and CAS Cycling
@tRC = Min

-06
-07
-08
-10

90
80
70
60

mA
mA
mA
mA

ICC2

Standby Current
(TTL Power Supply Current)

-06

ICC3
ICC3

RAS Only Refresh Current
(CAS = VIH. RAS Cycling
@tRC = Min

-06
-07
-08
-10

90
80
70
60

mA
mA
mA
mA

ICC4
ICC4

Fast Page Mode Current
(RAS = VIL. CAS Cycling
@tpc = Min

-06
-07
-08
-10

70
60
50
40

mA
mA
mA
mA

3-38

21010

D.C. AND OPERATING CHARACTERISTICS (Continued)
(Recommended Operating Conditions unless Otherwise Noted)

Symbol

Parameter

Speed

Min

Max

Units

90
80
70
60

mA
mA
mA
mA

ICC5

Standby Current
(CMOS Power Supply Current)

ICC6

CAS-before-RAS Refresh
Current (RAS and CAS Cycling
@tRC = Min

IlL

Input Leakage Current
(Any Input 0 < VIN < 6.5V
All Other Pins = OV)

-10

/LA

IOL

Output Leakage Current
(Data Out is Disabled
and 0 < VOUT < 5.5V)

-10

/LA

VOH

Output High Voltage Level
(IOH = -5mA)

2.4

VOL

Output Low Voltage Level
(IOL = 4.2 mAl

-06
-07
-08
-10

V
0.4

NOTE:

ICC1, ICC3, ICC4, and ICC6 are dependent on output loading and cyCle rates. Specified values are obtained with the output
open. Icc is specified as average current.

A.C. CHARACTERISTICS
(TA = O·C to +70·C, VCC = 5V
Symbol

Parameter

(See Notes 1,2)
+ 10%)

21010-06
Min

Max

21010-07
Min

Max

21010-08

21010-10

Min

Max

Notes

tREF

Time between
Refresh

tRC

RandomR/W
Cycle Time

110

tRWC

RMW Cycle Time

135

tRAC

Access Time
from RAS

100

(Notes 4, 7)

tCAC

Access Time
from CAS

(Notes 5,7)

tAA

Access Time from
Column Address

(Notes 6, 7)

tCLZ

CAS to Output in
LowZ

toFF

Output Buffer TurnOff Delay Time

Transition Time

130

Units

Max

160

190

185

155

ms
ns

220

3-39

inter

21010

A.C. CHARACTERISTICS (See Notes 1, 2)
(TA = ODC to + 70DC, VCC = 5V ,+ 10%) (Continued)
Symbol

Parameter

21010-06

21010-07

21010·08

21010-10

Min

Max

Notes

RAS Precharge
Time

tRAS

RAS Pulse Width

tRSH

RAS Hold Time

tCRP

CASto RAS
Precharge Time

tRCD

RAS to CAS
Delay Time

tCAS

CAS Pulse Width

10K

tCSH

CAS Hold Time

100

tCPN

CAS Precharge
Time

'tASR

Row Address
Set-Up Time

tRAH

Row Address
Hold Time

tASC

Column Address
Set-UpTime

tCAH

Column Address
Hold Time

tAR

Column Address
Time Referenced
toRAS

tRAD

RAS to Column
Address Delay Time

tRAL

Column Address to
RAS Lead Time

tRCS

Read Command
Set-UpTime

tRRH

Read Command
Hold Time
Referenced to RAS

(Note 12)

tRCH

Read Command
Hold Time
Referenced to CAS

(Note 12)

twcs

Write Command
Set-Up Time

(Note 13)

twci-!

Write Command
Hold Time

10K

Units

Max

tRP

Max

10K

3-40

80
10K

10K

100

ns
10K

10K

(Notes 9, 10)

(Note 11)

inter

21010

A.C. CHARACTERISTICS
(TA = O·C to +70·C, Vec = 5V
Symbol

(See Notes 1, 2)
+ 10%) (Continued)

Parameter

21010·06

21010·07

Min

Max

21010·08

21010-10

Min

Max
60

Max
75

Units

tWCR

Write Command
Referenced to RAS

twp

WE Pulse Width

tRWL

Write Command to
RAS Lead Time

tcWL

Write Command to
CAS Lead Time

tDS

DIN Set-Up Time

Notes

tDH

DIN Hold Time

tDHR

Data-In Hold Time
Referenced to RAS

tRWD

RAS to WE Delay Time

100

(Note 13)

tcWD

CAS to WE Delay Time

(Note 13)

tAWD

Column Address to
WE Delay Time

tRPC

RAS Precharge Time to
CAS Active Time

tesR

CAS Set-Up Time
for CAS before
RAS Refresh

tCHR

CAS Hold Time for CAS
before RAS Refresh

tePT

Refresh Counter Test
CAS Precharge Time

3-41

intJ

21010

A.C. CHARACTERISTICS (See Notes 1. 2)
(TA = O°C to + 70°C. VCC = 5V + 10%) (Continued)
Symbol

Parameter

21010-06
Min

Max

21010-07
Min

Max

21010-08
Min

Max

21010-10
Min

Max

Units

Notes

FAST PAGE MODE
tpc

Fast Page Mode
Cycle Time

tPRWC

Fast Page Mode
RMWCycle
Time

tePA

Access Time
from CAS
Precharge

tcp

Fast Page Mode
CAS Precharge
Time

tRASP

RASPulse
Width (Fast
Page Mode)

100K

100

(Notes 7.14)

100K

NOTES:
1. An initial pause of 200 ".s is required after power-up followed by any 8 RAS-only cycles before proper device operation is
achieved.
2. A.C. characteristics assume tT = 5 ns.
3. VIN (min) and VIL (max) are reference levels for measuring timing of input signals. Also. transition times are measured
between VIH (min) and VIL (max) ..
4. Assumes that tRCD ,;; tRCD (max). tRAD ,;; tRAD (max). If tRCD (or tRAD) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCD (or tRAD) exceeds the value shown.
5. If tRCD ;;, tRCD (max). tRAD ;;, tRAD (max). and tASC ;;, tAA - !cAC - tT access time is tCAC'
6. If tRAD ;;, tRAD (max) and tASC ,;; tAA - tCAC - tT. access time is tAA'
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. !oFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point
only; if tRCD is greater than the specified tRCD (max) limit. access time is controlled exclusively by tCAC or tAA.
10. tRCD (min) = tRAH (min) + 2 tT + tASC (min).
.
11. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference pOint
only; if tRAD is greater than the specified tRAD (max) limit. access time is exclusively controlled by tCAC or tAA'
12. Either tRRH or tRCH must be specified for a read cycle.
.
13. tWCS. !cwo. tRWD. and tAWD are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
.
14. !cPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").

3-42

21010

Read Cycle
t Rc
t RAS
RAS

VIH VIL -

CAS

VIH VIL -

tAR

t RSH

leAs
tRAL

VIH VIL -

----------OPEN

----- .•......... -1V to
Storage Temperature (Tstg) ..... -55°C to

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

+ 7.0V .

+ 7.0V
+ 150°C

Power Dissipation (PO) .................. 600 mW
Short Circuit Output Current (los) ........... 50 rnA

RECOMMENDED OPERATING CONDITIONS
Voltage referenced to Vss, T A = O°C to 70°C

Symbol

Parameter

Min

Typ

Max

Unit

Vcc

Supply Voltage

4.5

5.0

5.5

Vss

Ground

VIH

Input High Voltage

2.4

VIL

Input Low Voltage

-1.0

Vcc

0.8

NOTES:
1. VIL (min) = 1.0V for· continuous DC level.
2. VIL (min) = 2.0V for pulse width < 20 ns.

CAPACITANCE
Symbol

TA = 25°C

Parameter

CIN1

Input Capacitance (Ao-As)

CIN2

Input Capacitance (RAS, CAS, W, OE)

COUT

Output Capacitance (001-004)

Min

Max

Unit

D.C. AND OPERATING CHARACTERISTICS
Recommended operating conditions unless otherwise noted

Symbol

Speed

Parameter

ICC1

Operating Current
(RAS and CAS Cycling @ tRC = Min)

.ICC2

Standby Current
(TTL Power Supply Current)

ICC3

RAS Only Refresh Current
(CAS = VIH, RAS Cycling @ tRC = Min)

-06
-07
-08
-10

ICC4

Fast Page Mode Current
(RAS = VIL, CAS Cycling @tpc = Min)

-06
-07
-08
-10

ICC5

Standby Current
(CMOS Power Supply Current)

3-54

-06
-07
-08
-10

Min.

Max

Units

90
80
70
60

rnA
rnA
rnA
rnA

rnA

90
80
70
60

rnA
rnA
rnA
rnA

75
65
55
45

rnA
rnA
rnA
rnA

rnA

21014

D.C. AND OPERATING CHARACTERISTICS (Continued)
Recommended operating conditions unless otherwise noted
Symbol
ICC6

Parameter

Speed

CAS-before-RAS Refresh Current
(RAS and CAS Cycling @ tRC = Min)

-06
-07
-08
-10

Min

Max

Units

90
80
70
60

rnA
rnA
rnA
rnA

IlL

Input Leakage Current
(Any Input 0 ::;; VIN ::;; 6.5V
All Other Pins = OV)

-10

/LA

IOL

Output Leakage Current
(Data Out is Disabled and
0::;; VOUT ::;; 5.5V)

-10

/LA

VOH

Output High Voltage Level
(IOH = -5 rnA)

2.4

VOL

Output Low Voltage Level
(IOL = 4.2 rnA)

0.4

NOTE:
ICC1' ICC3, ICC4 and Iccs are dependent on output loading and cycle rates. Specified values are obtained with the output
open. Icc is specified as average current.

A.C. CHARACTERISTICS(1,2)
= O·C to 70·C, VCC = 5V ± 10%

Symbol
tREF

Parameter

21014-06

21014-07

21014-08

21014-10

Min

Time between Refresh

Max
8

Max

Units

Notes

Max
ms

tRC

Random R/W Cycle Time

110

130

150

180

tRWC

RMW Cycle Time

165

185

205

245

tRAC

Access Time from RAS

100

4, 7

tCAC

Access Time from CAS

5, 7

tAA

Access Time from
Column Address

6, 7

tCLZ

CAS to Output in Low Z

tOFF

Output Buffer Turn-Off
Delay Time

Transition Time

tRP

RAS Precharge Time

tRAS

RAS Pulse Width

tRSH

RAS Hold Time

tcRP

CAStoRAS
Precharge Time

tRCD

RAS to CAS Delay Time

tCAS
tCSH

0
0

10K

CAS Pulse Width

10K

CAS Hold Time

10K

70
3-55

10K

ns
ns

100

10K

100

9, 10

inter

21014

A.C. CHARACTERISTICS(1, 2) (Continued)
TA = O·C to 70·C, VCC = 5V ±10%

Symbol

Parameter

21014-06

21014-07

21014-08

21014-10

Min

Max

Units

Notes

Max

tCPN

CAS Precharge Time

tASR

Row Address Set-Up Time

tRAH.

Row Address Hold Time

tASC

Column Address
Set-UpTime

tCAH

Column Address
Hold Time

tAR

Column Address Time
Referenced to RAS

tRAO

RAS to Column Address
Delay Time

tRAL

Column Address to
RAS Lead Time

tRCS

Read Command
Set-UpTime

tRRH

Read Command Hold
Time Referenced to RAS

tRCH

Read Command Hold
Time Referenced to CAS

twcs

Write Command
Set-UpTime

tWCH

Write Command
Hold Time

twCR

Write Command Hold
Time Referenced to RAS

tRWL

•Write Command to
RAS Lead Time

tcwL

Write Command to
CAS Lead Time

tos

DIN Set-Up Time

tOH

DIN Hold Time

tOHR

Data-In Hold Time
Referenced to RAS

twp

WE Pulse Width

tRWO

RAS to WE Delay Time

100

110

135

tcwo

CAS to WE Delay Time

tAWO

Column Address to
WE Delay Time

tRPe

RAS Precharge Time to
CAS Active Time

tCSR

CAS Set-Up Time for CAS
before RAS Refresh

3-56

21014

A.C. CHARACTERISTICS(1, 2) (Continued)
= O·C to 70·C, VCC = 5V ±10%

Symbol

21014-06

21014-07

21014-08

21014-10

Min

Parameter

Max

Units

tCHR

CAS Hold Time for CAS
before RAS Refresh

tCPT

Refresh Counter Test CAS
Precharge Time

tROH

RAS Hold Time
Referenced to OE

tOEA

OE Access Time

tOED

OE to Data Delay

toEZ

Output Buffer Turn Off
Delay Time from OE

tOEH

OE Command Hold Time

20
20

0
20

25
25

Notes

Max

ns
ns

FAST PAGE MODE
Symbol

Parameter

21014-06
Min

Max

21014-07
Min

Max

21014-08
Min

Max

21014-10
Min

Units

tpc

Fast Page Mode
Cycle Time

tPRWC

Fast Page Mode RMW
Cycle Time

100

105

125

tCPA

Access Time from CAS
Precharge

tcp

Fast Page Mode CAS
Precharge Time

tRASP

RAS Pulse Width
(Fast Page Mode)

40
10
100K

45
10

100K

55
10

100K

100

Notes

Max

7, 14

ns
100K

NOTES:
1. An initial pause of 200 p-s is required after power-up followed by any 8 RAS-only cycles before proper device operation is
aChieved.
2. A.C. characteristics assume tT = 5 ns.
3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured
between VIH (min) and VIL (max).
4. Assumes that tRCD s; tRCD (max), tRAD s; tRAD (max). If tRCD (or tRAD) is greater than the maximum recommended value
shown in this table tRAc will be increased by the amount that tRCD (or tRAD) exceeds the value shown.
5. If tRCD :;, tRCD (max), tRAD :;, tRAD (max), and tASC :;, tM - !cAC - tT, access time is !cAC·
6. If tRAD :;, tRAD (max) and tASC s; tAA - tCAC - tT, access time is tM.
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. !oFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point
only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled exclusively by tCAC or tM.
10. tRCD (min) = tRAH (min) + 2tT + tASC (min).
11. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point
only; if tRAD is greater than the specified tRAD (max) limit, access time is exclusively controlled by tCAC or tM.
12. Either tRRH or tRCH must be specified for a read cycle.
13. twcs, tCWD, tRWD, and tAWD are non restrictive operating parameters. They are included in the Data Sheet as Electrical
characteristics only.
14. tCPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").

3-57

inter

21014

TIMING DIAGRAMS
READ CYCLE

RAS

V1H V1L -

CAS

V1HV1L -

V1H V1L -

V1HV1L -

DQ1-DQ4

VOHVOL ...:.

~DON'TCARE
240512-5

3-58

inter

21014

TIMING DIAGRAMS (Continued)
WRITE CYCLE (EARLY WRITE)

HAS

V1H V1L -

CAS

V1H V1L -

V1H Vil -

V1H V1l -

DQ1-DQ4

V1H Vil -

OPEN

240512-6

WRITE CYCLE (OE CONTROLLED WRITE)

RAS

V1H -

VIL -

CAS

V1H VIL -

V1H Vil -

V1H -

001-004

vlt -

YIH-

VIL -

V1H -

Vil -

~DON'TCARE
240512-7

3-59

inter

21014

TIMING DIAGRAMS (Continued)
READ-MODIFY-WRITE

~-------------~--------------~

I--------I.As---------I

V1H -

--~r---IA.

VIL -

icsH
--I-+-----I.SH------+-I

VIHVII..-

~it------t_,~-~----t~s------~~~~--~

OQ1-oo.4 VI/OH -

VVOL -

---------------h~~~~~
240512-8

FAST PAGE MODE READ CYCLE

v.. _ ---.u--V1L -

DQl-DQ4

•

~DON'TCAR[
240512-9

3-60

21014

TIMING DIAGRAMS (Continued)
FAST PAGE MODE WRITE CYCLE

RAs

V1H V1L -

CAS

V1H 'Y1L -

Y1H -

V1L -

Y1H -

'Ii

VIL-

Y1H V1L -

DQ1-DQ4

V1H -

V1L -

240512-10

FAST PAGE MODE READ-MODIFY-WRITE

RAS

CAS

v.. V1L -

Y1H -

VIL-

'Ii

V1H-

VIL -

V1H -

V1L -

DQ1-0Q4

240512-11

3-61

inter

21014

TIMING DIAGRAMS (Continued)
RAS-ONLY REFRESH CYCLE

Note:

IN, DE

Don't ca~e

1-----------tRc----------i
t--------tRAs------+l

RAS

V1H V1L -

CAS

V1H V1L -

240512-12

CAS-BEFORE-RAS, REFRESH CYCLE

Note:

IN,

CE, A = Don't care

t-----------tRC-----------t

1-------tRAs-------t------

RAS

V1H V1L -

CAS

V1H V1L -

1----tCHR - - - - . f

001-004

VI/OH
VI/OL

~---tCPN---,---i

~-----------------OPEN-----------------------------

~DON'TCARE
240512-13

3-62

intJ

21014

TIMING DIAGRAMS (Continued)
HIDDEN REFRESH CYCLE (READ)

CAS

V 1H V1L -

VIH -

liE

V,H -

DQ1-DQ4

V1L -

VOH VOL -

240512-14

HIDDEN REFRESH CYCLE (WRITE)

'Re
'RAS

m
CAS

Vi
liE

001-004

V1H -

V,L -

V1H -

V,L -

V1H -

V,L -

V'H-

V,L V1H -

V,L V1H V1L -

'OHR

~DON'TCARE
240512-15

3-63

inter

21014

TIMING DIAGRAMS (Continued)
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
i+----------tRAS----------i
V1H-----i.
V 1L -

f 4 - - - - - tR S H - - - - - I

Jr------,lI-----tcAs---....-..!

~H+-----

V1HV 1L -

READ CYCLE
Vi

OOl-0Q4

V 1H V1L -

VOHVOL -

------OPEN"----I-tt--~~--.:~~~~~-~---

WRITE CYCLE
Vi

V 1H VIL -

V 1H V 1L -

OQ1-0Q4

V1H V 1L -

OOl-0Q4

---------OPEN-------~--~~~:;--~--------~~---------

VIHV 1L -

V 1H V 1L -

VI/OH VI/OL -

1881 DON'T CARE
240512-16

3-64

intJ

21014

address becomes valid after tRAO (max), access is
specified by tCAC or tAA' In order to achieve the minimum access time, tRAC (min), it is necessary to meet
both tRCO (max) and tRAO (max).

21014 OPERATION
Device Operation
The 21014 contains 1,048,576 memory locations organized as 262,144 four-bit words. Eighteen address
bits are required to address a particular 4-bit word in
the memory array. Since the 21014 has only 9 address input pins, time multiplexed addressing is used
to input 9 row and 9 column addresses. The multiplexing is controlled by the timing relationship between the row address strobe (RAS), the column address strobe (CAS) and the valid address inputs.

The 21014 has common data I/O pins. For this reason an output enable control input (DE) has been
provided so the output buffer can be precisely controlled. For data to appear at the outputs, DE must
be low for the period of time defined by tOEA and
tOEZ·

Operation of the 21014 begins by strobing in a valid
row address with RAS while CAS remains high.
Then the address on the 9 address input pins is
changed from a row address to a column address
and is strobed in by CAS. This is the beginning of
any 21014 cycle in which a memory location is accessed. The specific type of cycle is determined by
the state of the write enable pin and various timing
relationships. The cycle is terminated when both
RAS and CAS have returned to the high state. Another cycle can be initiated after RAS remains high
long enough to satisfy the RAS precharge time (tRP)
requirement.

The 21014 can perform early write and read-modifywrite cycles. The difference between these cycles is
in the state of data-out and is determined by the
timing relationship between W, DE and CAS. In any
type of write cycle data-in must be valid at or before
the falling edge of W or CAS, whichever is later.

RAS and CAS Timing

Read-Modify-Write: In this cycle, valid data from the
addressed cells appears at the outputs before and
during the time that data is being written into the
same cell locations. This cycle is achieved by bringing W low after CAS and meeting the data sheet
read-modify-write timing requirements. This output
enable input (DE) must be low during the time defined by toEA and tOEZ for data to appear at the
outputs. If tCWD and tRwD are not met the output
may contain invalid data. Conforming to the DE timing requirements prevents bus contention on the
21014 OQ pins.

Write

Early Write: An early write cycle is performed by
bringing W low before CAS. The 4-bit wide data at
the data input pins is written into the addressed
memory cells. Throughout the early write cycle the
outputs remain in the Hi-Z state. In the early write
cycle the output buffers remain in the Hi-Z state regardless of the state of the DE input.

The minimum RAS and CAS pulse widths are specified by tRAS (min) and tCAS (min) respectively. These
minimum pulse widths must be satisfied for proper
device operation and data integrity. Once a cycle is
initiated by.bringing RAS low, it must not be aborted
prior to satisfying the minimum RAS and CAS pulse
widths. In addition, a new cycle must not begin until
the minimum RAS precharge time, tRP, has been
satisfied. Once a cycle begins, internal clocks and
other circuits within the 21014 begin a complex sequence of events. If the sequence is broken by violating minimum timing requirements, loss of data integrity can occur.

Data Output
The 21014 has tri-state output buffers which are
controlled by CAS and DE. When either CAS or DE
is high (VIH) the outputs are in the high impedance
(Hi-Z) state. In any cycle in which valid data appears
at the output the output goes into the low impedance
state in a time specified by tCLZ after the falling edge
of CAS. Invalid data may be present at the output
during the time after tClZ and before the valid data
appears at the output. The timing parameters tCAC,
tRAC and tAA specify when the valid data will be
present at the output. This is true even if a new RAS
cycle occurs (as in hidden refresh). Each of the
21014 operating cycles is listed below after the corresponding output state produced by the cycle.

Read
A read cycle is achieved by maintaining the write
enable input (W) high during a RAS/CAS cycle. The
access time is normally specified with respect to the
falling edge of RAS. But the access time also depends on the falling edge of CAS and on the valid
column address transition.
If CAS goes low before tRCO (max) and if the column
address is valid before tRAO (max) then the access
time to valid data is specified by tRAC (min). However, if CAS goes low after tRCO (max) or if the column
3-65

inter

21014

Valid Output Data: Read, Read-Modify-Write, Hidden
Refresh, Fast Page Mode Read, Fast Page Mode
Read-Modify-Write.
Hi-Z Output State: Early Write, RAS-only Refresh,
. Fast Page Mode Write, CAS-only cycle..
Indeterminate Output State: Delayed Write (tewD or
tRWD are not met).

Refresh
The data in the 21014 is stored on a tiny capacitor
within each memory cell. Due to leakage the data
may leak off after a period of time. To maintain data
integrity it is necessary to refresh each of the rows
every 8 ms. Either a burst refresh or distributed refresh may be used. There are several ways to accomplish this.
RAS-On/y Refresh: This is the most common method for performing refresh. It is performed by strobing
in a row address with RAS while CAS remains high.
.This cycle must be repeated for each of the 512 row
addresses, (Ao-As).

CAS-before-RAS Refresh Counter

Test Cycle
A special timing sequence· using the CAS-beforeRAS refresh counter test cycle provides a convenient method of verifying the functionality of the
CAS-before-RAS refresh activated circuitry. The cycle begins as a CAS-before-RAS refresh operation.
Then, if CAS is brought high and then low again
while RAS is held low, the read and write operations
are enabled. In this mode, the row address bits Ao
through As are supplied by the on-chip refresh counter.

Fast Page Mode
Fast page mode provides high speed read, write or
read-modify-write access to all memory cells within a
selected row. These cycles may be mixed in any
order. A fast page mode cycle begins with a normal
cycle. Then, while RAS is kept low to maintain the
row address, CAS is cycled to strobe in additional
column addresses. This eliminates the time required
to set up and strobe sequential row addresses for
the same page.

CAS-before-RAS Refresh: The 21014 has CAS-before-RAS on-chip refresh capability that eliminates
the need for external refresh addresses. If CAS is
held low for the specified set up time (tcSR) before
RAS goes low, the on-chip refresh circuitry is enabled. An internal refresh operation automatically
occurs. The refresh address is supplied by the onchip refresh address counter which is then internally
incremented in preparation for the next CAS-beforeRAS refresh cycle.

Power-Up
If RAS = VSS during power-up, the 21014 could begin an active cycle. This condition results in higher
than necessary current demands from the power
supply during power-up. It is recommended that
RAS and CAS track with Vee during power-up or be
held at a valid VIH in order to minimize the power-up
current.

Hidden Refresh: A hidden refresh cycle may be performed while maintaining the latest valid data at the
output by extending the CAS active time and cycling
RAS. The 21014 hidden refresh cycle is actually a
CAS-before-RAS refresh cycle within an extended
read cycle. The refresh row address is provided by
the on-chip refresh address counter.

An initial pause of 200 ,""S is required after power-up
followed by 8 initialization cycles before proper device operation is assured. Eight initialization cycles
are also required after any. 8 ms period in which
there are no RAS cycles. An initialization cycle is any
cycle in which RAS is cycled.

Other Refresh Methods: It is also possible to refresh
the 21014 by using read, write or read-modify-write
cycles. Whenever a row is accessed, all the cells in
that row are automatically refreshed. There are certain applications in which it might be advantageous
to perform refresh in this manner but in general
RAS-only or CAS-before-RAS refresh is the preferred method.

Termination
The lines from the TTL driver circuits to the 21014
inputs act like unterminated transmi~sion lines resulting in significant positive and negative overshoots at the inputs. To minimize overshoot it is advisable to terminate the input lines and to keep them
as short as possible. Although either series or parallel termination may be used, series termination is

3-66

inter

21014

generally recommended since it is simple and draws
no additional power. It consists of a resistor in series
with the input line placed close to the 21014 input
pin. The optimum value depends on the board layout. It must be determined experimentally and is
usually in the range of 20n to 40n.

Decoupling
The importance of proper decoupling can not be
overemphasized. Excessive transient noise or voltage droop on the Vee line can cause loss of data
integrity (soft errors). It is recommended that the total combined voltage changes over time in the Vee
to Vss voltage (measured at the device pins) should
not exceed 500 mV.

Board Layout
It is important to layout the power and ground lines
on memory boards in such a way that switching transient effects are minimized. The recommended
methods are gridded power and ground lines or separate power and ground planes. The power and
ground lines act like transmission lines to the high
frequency transients generated by DRAMs. The impedance is minimized if all the power supply traces
to all the DRAMs run both horizontally and vertically
and are connected at each intersection or better yet
if power and ground planes are used.

A high frequency 0.3 /JoF ceramic decoupling capacitor should be connected between the Vee and
ground pins of each 21014 using the shortest possible traces. These capacitors act as a low impedance
shunt for the high frequency switching transients
generated by the 21014 and they supply much of the
current used by the 21014 during cycling.

Address and control lines should be as short as pos, sible to avoid skew. In boards with many DRAMs
these lines should fan out from a central point like a
fork or comb rather than being connected in a serpentine pattern. Also the control logic should be '
centrally located on large memory boards to facilitate the shortest possible address and control lines
to all the DRAMs.

In addition, a large tantalum capacitor with a value of
47 /JoF to 100 /JoF should be used for bulk decoupling
to recharge the 0.3 /JoF capacitors between cycles,
thereby reducing power line droop. The bulk decoupiing capacitor should be placed near the point
where the power traces meet the power grid or power plane. Even better results may be achieved by
distributing more than one tantalum capacitor
around the memory array.

PACKAGE DIMENSIONS
20-LEAD PLASTIC DUAL-IN-LiNE PACKAGE Units: Inches (millimeters)

~
,rn
'.~".'"
J[!J
~: ::::::: ~IJ
~

~_100
J

0.012(0.30)

0.962 (24.43)
0.972 (24.69)

0.02~fH·50

~
"M(,~J~J
J
~ff::::~::
Jl

0.145(3.68)

0.100 (2.54)1
TYP
J---l1

0.047(1.19)
0.059 (1.49)

1 0.032 0.81
0.040 1.02

J-

0.016 0.41
0.023 0.58

240512-17

3-67

21014

PACKAGE DIMENSIONS (Continued)
20-LEAD PLASTIC SMALL OUTLINE J-LEAD Units: Inches (millimeters)

0.670 17.02
0.680 17.27

0.016 0.41
0.020 0.51
240512-18

20-PIN PLASTIC ZIGZAG-IN-L1NE PACKAGE

Units: Inches (millimeters)

1-------- 1.025~26.041 - - - - - - - 1

1~~~I"""""""'.035l26"""""""'.29}~"""""""'·Ii--TJ

r
~~~~~~~~
0

lNDEX

0.018 (0.46)
0.022 (0.56)

J L_

0.325 (8.26)
0.335 (8.51)

-r--I=--!

I0'"~~
~
ci

-l-

t!~I--'_"~l

I+- 0.050 (1.27)

.., 3!0 .....

0'"
....

TYP

0.113 (2.87)
0.123 (3.12)

0.012 (0.30)

0.100 (2.54)
TYP

ci
240512-19

3-68

21040
4,194,304 x 1-BIT DYNAMIC RAM
WITH PAGE MODE
• Performance Range
21040-08

21040-10

21040-12

tRAC

100

120

ns .

tCAC

tRC

160

190

220

Unlls

• Common I/O Using "Early Write"
Operation

• CAS before RAS refresh, RAS-only
Refresh, Hidden Refresh and Test
Mode Capability

•

• Single 5V ± 10% Power Supply

• Fast Page Mode Operation

1024 Cycles/16mS Refresh

•

Available in Plastic SOJ and ZIP
package types

GENERAL INFORMATION
Intel 21040 is a CMOS high speed 4,194,304 x 1-bit dynamic RAM optimized for high performance applications such as mainframes, graphics and microprocessor systems.
21040 features Fast Page Mode operation which allow high speed random access of memory cells within the
same row.
CAS before RAS refresh capability provides on-chip auto refresh as an alternative to RAS only refresh. All
Inputs, Output and clocks are fully CMOS and TTL compatible.
Multiplexed address inputs permit the 21040 device to be packaged in a standard 20/26 pin plastic SOJ and
20 pin plastic ZIP.
.

Functional Block Diagram

Pin Configuration
Plastic SOJ
Plastic ZIP

RAs-W------,
CAs
ii

-rt-,..,........

T21040

Z21040

REFRESH CONTROL &:
ADDRESS COUNTER

COLUMN DECODER
SENSE AIoIPS &r: 10

AO
IiIEWORY ARRAY
4,194,304 CELLS

......-vcc
+--Vss

240810-2
Pin Name

A,O

AQ-Al0

240810-1

3-69

240810-3
Pin Function
Address Inputs

Data In

Data Out

Read/Write Input

RAS

Row Address Strobe

CAS

Column Address Strobe

Vee

Power (+5V)

Vss
N.C.

Ground
No connection

September 1990
Order Number: 2408111-001

inter

21040

ABSOLUTE MAXIMUM RATINGS'
PARAMETER

VALUE

UNITS

Voltage on any pin relative to Vss
Voltage on power supply relative to Vss
Storage Temperature
Operating Temperature
Power Dissipation
Short Circuit Output Current

-1 to +7.0
-1to+7.0
-55 to + 150
Ot070
SOO
50

V
V
°C
°C
mW
mA

SYMBOL
Yin, Vout
Vee
Tstg
Topr
Pd
los

'Permanent damage may occur If "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional Operation should be restricted to the conditions as defined in the operational sections of the Data Sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

RECOMMENDED DC OPERATING CONDITIONS (Voltage referenced to Vss, Ta = O°C to 70°C)
SYMBOL
VCC
VSS
VIH
VIL

PARAMETER

MIN

TYP

MAX

UNIT

Supply Voltage
Ground
Input High Voltage
Input Low Voltage

4.5
0
2.4
--1.0

5.0
0

5.5
0
S.5
0.8

V
V
V
V

CAPACITANCE (Ta = 25°C)
SYMBOL
Cin1
Cin2
Cout

PARAMETER

MIN

MAX

UNIT

Input Capacitance (AO - A 10, Din)
Input Capacitance (RAS, CAS, WRITE)
Output Capacitance (Dout)

5
7
7

pF
pF
pF

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
SYMBOL
ICC1

PARAMETER
Operating Current'
(RAS and CAS cycling

tRC

min)

ICC2

Standby Current
(TTL Power Supply Current)

ICC3

RAS Only Refresh Current'
(CAS = VIH, RAS Cycling @ tRC

min)

Fast Page Mode Current'
(RAS = VIL, CAS Cycling

min)

ICC4

tpc

ICC5

Standby Current
(CMOS Power Supply Current)

ICCS

CAS-before-RAS Refresh Current'
(RAS and CAS Cycl!ng @ tRC = min)

SPEED

MIN

MAX

UNIT

-08
-10
-12

100
85
70

mA
mA
mA

-08
-10
-12
-08
-10
-12

100
85
70

mA
mA
mA

SO
50
40

mA
mA
mA

100
85
70

mA
mA
mA

3-70

-08
-10
-12

inter

21040

DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted) (Continued)
SYMBOL'

PARAMETER

SPEED

MIN

MAX

UNIT

-10

ICC7

Standby Current
(RAS = VIH, CAS

III

Input leakage Current
(Any Input 0 ,,; Vin ,,; 6.5 Volts
all other Pins = 0 Volts)

IOl

Output leakage Current
(Data out is disabled and
o ,,; Vout ,,; 5.5 V)

-10

VOH

Output High Voltage level
(IOH = -5mA)

2.4

VOL

Output low Voltage level
(IOl = 4.2 mA)

0.4

Vll, DOUT = Enable)

·Note:
ICCt, ICC3, ICC4 and ICC6 are dependant on output loading and cycle rates. Specified values are obtained with the output
open. ICC is specified as average current.
AC CHARACTERISTICS (See Notes 1, 2) (Ta

O·C to 70·, VCC
21040-08

SYMBOL

PARAMETER

Min

Max

5V ± 10%)
21040-10
Min

Max

21040-12
Min

Max

UNITS

Notes

tREF

Time between Refresh

tRC

Random R/W Cycle Time

150

180

220

tRWC

RMW Cycle Time

175

210

255

tRAC

Access Time From RAS

100

120

3,4

tCAC

Access Time From CAS

3,4

tAA

Access Time From Column Address

3,10

tell

CAS to Output in low Z

ns'

tQFF

Output Buffer Turn-Off Delay Time

Transition Time

tRP

RAS Precharge Time

tRAS

RAS Pulse Width

tRSH

RAS Hold Time

70
10K

100

10K

120

ns
10K

ns
' ns

teRP

CAS to RAS Precharge Time

tRCD

RAS to CAS Delay Time

10
90

ns
ns

teAS

CAS Pulse Width

10K

teSH

CAS Hold Time

100

120

tePN

CAS Precharge Time

tASR

Row Address Set-up Time

tRAH

Row Address Hold Time

tASC

Column Address Set-up Time

teAH

Column Address Hold Time

tAR

Column Address Time referenced to RAS

3-71

4,5

inter

21040

AC CHARACTERISTICS (See Notes 1, 2) (Ta

O°C to 70°, VCC
21040-08

SYMBOL

PARAMETER

± 10%) (Continued)

21040-10

21040-12

Min

Max

Min

Max

Min

Max

UNITS

Notes

tRAD

RAS to Column Address Delay Time

tRAL

Column Address to RAS Lead Time

tRCS

Read Command Set-Up Time

tRRH

Read Command Hold Time referenced to
RAS

tRCH

Read Command Hold Time referenced to
CAS

twcs

Write Command Set-Up Time

twCH

Write Command Hold Time

twCR

Write Command Hold referenced to RAS

twP

Write Command Pulse Width

tRWL

Write Command to RAS Lead Time

tCWL

Write Command to CAS Lead Time

tDS

Data Set-up Time

tDH

Data Hold Time

tDHR

Data-In Hold Time referenced to RAS .

tRWD

RAS to WRITE Delay Time

100

120

tCWD

CAS to WRITE Delay Time

tAWD

Column Address to WRITE Delay Time

tRPC

RAS Precharge Time to CAS Active Time

tGSR

CAS Set-up Time for CAS before RAS

refresh
tCHR

CAS Hold Time for CAS before RAS
refresh

tCPT

CAS Precharge Time (Refresh Counter
Test)

twTS

Write Command Set-up Time (Test Mode
in)

IWTH

Write Command Hold Time (Test Mode in)

twRP

WRITE to RAS Precharge Time (CAS
before RAS Cycle)

twRH

WRITE to RAS Hold Time
RASCycle)

(CAS before

3-72

21040

AC CHARACTERISTICS (FAST PAGE MODE)
(See Notes 1, 2) (Ta = O·C to 70·, VCC = 5V

10%) (Continued)

21040-08
SYMBOL

PARAMETER

Min

Max

21040-10

Min'

Max

21040-12
Min

tpc

Fast Page Mode Cycle Time

tpRWC

Fast Page Mode RMW Cycle Time

105

tCPA

Access Time from CAS Precharge

tcp

Fast Page Mode CAS Precharge Time

tRASP

RAS Pulse Width (Fast Page Mode)

55
10

200K

120

UNITS

Notes

ns
ns
60

200K

100

AC CHARACTERISTICS (TEST MODE)(Ta = 0·Ct070·, VCC = 5V

Max

10%)

(Note 11)
SYMBOL

PARAMETER

21040-08
Min

Max

21040-10
Min

Max

21040-12
Min

UNITS

Notes

Max

IRC

Random R/W Cycle Time

155

185

225

tRWC

RMW Cycle Time

180

215

260

tpc

Fast Page Mode Cycle Time

PRWC

Fast Page Mode RMW Cycle Time

110

tRAC

Access Time From RAS

105

125

3,4

tCAC

Access Time From CAS

3,4

tAA

Access Time From Column Address

3,10

tCPA

Access Time From CAS

tRASP

RAS Pulse Width (Fast Page Mode)

200K

105

200K

125

200K

I1s

tRAS

RAS Pulse Width

10K

105

10K

125

10K

tRSH

RAS Hold Time

ns
ns

!CAS

CAS Pulse Width

tCSH

CAS Hold Time

105

125

tRAL

Column Address To Lead Time

10K

tRWD

RAS to WRITE Delay Time

105

125

!CWO

CAS to WRITE Delay Time

tAWD

Column Address to WRITE Delay Time

NOTES:
1. An initial pause of 200 Microseconds is required after power-up followed by an 8 RAS-only cycles before proper device
operation is achieved.
'
2. Vih (min) and Vii (max) are reference levels for measuring timing of input signals. Also, transition times are measured
between Vih (min) and Vii (max) and are assumed to be 5 ns for all inputs.
3. Measured with a load equivalent to two 2 TTL loads and 100 pF.
4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point
only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled exclusively by tCAC.
5. Assumes that tRCD "' tRCD (max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to output
,
voltage levels.
7. twCS, two, tRWD, and tAWD are non restrictive operating parameters. They are included in the Data Sheet as Electrical
characteristics only. If twcs "' twcs (min), the cycle is an early write cycle and data out pin will remain open circuit through
the entire cycle; If tRWD "' tRWD (min), !CWO", tCWD (min) and tAWD "' tAWD (min), the cycle is a read-write cycle and
data out will contain data read from the selected cell; If neither of the above set of conditions is satisfied, the condition of
the data out (at access time) is indeterminate.
'
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to CAS leading edge in early write cycles and to the Vii leading edge in read-write
cycles.
10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point
only; if tRAD is greater than the specified tRAD (max) limit, access time is controlled by lAA.
11. These specifications are applicable in the test mode.'
.
3-73

21040

READ CYCLE
Timing Waveforms
~------------------------tRC----------~------------~

~---------------tRAS---------------.j

1-------tcSH-------.j

V1H -

-~~J""""':rI_l,....,,....,....,....,...,..,.,.~--+-----------+_--~~,....,,....,

WRITE

~-----------t~c--------_r~.j

VOH DOUT

VALID DATA

- - - - - - - OPEN
VOL -

: "H"or"L"
240810-4

3-74

inter

21040

WRITE CYCLE (EARLY WRITE)
~-----------------------tRC------------------------~
~---------------tRAS---------------~

~-------tRCD--------+-----tRSH----l
~-------t~H-------+----------~

VIH -

--Ir--!-+--------+_

VIH -

""""Ir-l.....,....,+07""'7'-r..,....,..""!I.

VIH -

""''''''''''''"'''7'''''''''''''''''''''''''''''''''''''' iI------' _.,....-.r-l"""....,....,.-r..,....,....,....,...,.....,

CAS

AO-AIO

WRITE

VOH Dour

- - - - - - - - - - - - - - - - - - - - OPEN - - - - - - - - - - VOL -

:"H"or"L"
240810-5

3-75

inter

21040

READ-WRITE CYCLE
t RWC

t RAS
V1H RAS
V1L t RSH

t RCD

tCAS

V1H CAS
V1L -

V1H WRITE
V1L -

V1H -

DjN

V1L -

VOH -

DOUT

VOL -

-------

I7lLI :

"H" or "L"

240810-6

3-76

inter

21040

FAST PAGE MODE READ CYCLE
IRASP
V1H -

-----------1

I--IR~

RAS
V1L -

i - - - Ipc - - -

ICSH

i--IRSH-

ICAS

~IRCD

i-Icp1-

V1H -

~ ,-.,l

CAS
VIL-J

~ ~~

i-ICp'"

r---,

~S,

~ ~~

IAR
IASR

AONAIO

V1H-W
V1L -

WRITE :::

I--

I,IRAH,

ROW

leAH

COL

=I 111/117

lASe

COL

KlIIIIIIII

VIII
i--IM

COL

I~CA~

r----

i - - - - - IRAC

OH DOUT VOL _

I'~C'
c-IAA-i--\cPA

-----------(V
_ 't

~LZ

VALID
DATA

~
~

I'~C'
i--IAA f - - -ICPA-f---

.-I. . _'fIX
'J.//-

"'---H'J'"
~
_

VALID I L -

~ DATA r -

t' Ii"i:::"
~

.£LZ

VALID
DATA

it'
I~
lorr
r.£LZ

l?Z2I :"H" or "L"
240810-7

3-77

inter

21040

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

DIN

V IH -

--,-r-r....,-lT~,...,\.~----~,rT\.Jr---Il~"'Jr---Il~-r-r-r-r-r-'7"'"r-T

VIL -

..."-""""""'-IT""...._-'

1'----""1

VOH -

DOUT

- - - - - - - - - - - - - - - - - - OPEN - - - - - - - - - - - - - VOL -

: "H"or"L"
240810-8

3-78

inter

21040

FAST PAGE MODE READ-WRITE CYCLE
t RASP

t=-tR=1

~
tCSH

1~CRP

i---tRCD

I-tcp'"

tCAS-

-"",i-""- - tASC

?lZ)

ROW

i-tAwD-

tos

~tDHtVALID
DATA

- tAA t RAC

Dour

VOL -

tCWL;'"

!--tAWD

tos

'III I) "'VAUo"" :JIIIIIIII
~

tCLl

,.:::::0

tCAC

r-tAA- tCPAVALID
DATA

-tCLl

- -:

tClZ

---

-:.~

L VALID
1111l,)r--DATA

VOH -

\-~

!---tRWD

IIIII 'lilli/Ii I:

tNt

II IIIIIIIII

COLUMN

tCWD

f-,tAWD--

tDS -

COLUMN

;::;

- tRAl-

tASC

..:=.

I' tCAH

tcw

tRCS -

COLUMN

- tCAS--

,---,

tASC

~ _ tcw~

i--- t RAD-

- tRSH-

- tcp'"

i--tCAS-

i---tpRWC-

rr-

)---1~
I"'-"

tCAC

I--tAA
i---tcPAVALID
DATA

~
~

-......

~ I/}!

VALID
DATA

: "H" Or "L"

240B10-9

3-79

21040

RAS ONLY REFRESH CYCLE
t----------tRc'----------t
1-------tRAs---------i

V1H -

CAS

- + 1 - - - - - - - - - - - - - - -.......-.....,..---

......

V1L -

~1z
ROW

VOH
.DOUT V
OL

7OlZOOZZOOO0OZ0

-----------OPEN ~-----------

: "H" or"L"
240810-10'

NOTE:
WRITE = "H" or "L", A 10 = "H" or "L"

3-80

inter

21040

CAS BEFORE RAS REFRESH CYCLE

1-----------tRc----------i
1------tRAs-----+i

V IL

_ __

VIH -

'"""'l,....,..,.-r-r-r-'7""'ir----.,..,.-.,-.,....,....,....,""'""l""'""l,...-:r-r-r-r-r-r--r--r--r--r--r"'7

WRITE

VOH------"""'\I
DOUT

VOL -

1)--------------- OPEN - - - - - - - - - -

_ _ _ _ _-'1

I?l2I :

"H" or ilL"

240810-11

NOTE:
AO - A10="H"or"L"

3-81

inter

21040

HIDDEN REFRESH CYCLE (READ)
1--------tRc------.j

VOH COUl

VOL -

-----------+

10
10

""""
"'6r-.

'",,;
,-

\..IY

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

x..:
::::E
N

....'"en

Ig
Ig

I
I

ci
+I

:!
N
10

0
~
~

...,
~

'+'

L--

£I'~

'xv., s.,'oz

Figure 3. Outline Drawing

3·92

"ot

intJ

202569

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative
to vss (VIN, VOUT) ........•..... -1V to

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of, development. The specifications are subject to
change without notice.

+ 7.0V

Voltage on Power Supply
Relative to Vss (Vee> ........... -1V to + 7.0V
Storage Temperature (TSTG) .... - 55DC to + 125DC

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the· "Operating Conditions"
may affect device reliability.

Soldering Temperature. Time
(Tsolder) ....................... 260DC • 10 Sec
Power Dissipation (P d) ....•..........•....... 9W
Short Circuit Output
Current (lOUT) .......•.............. _... 50 rnA

RECOMMENDED OPERATING CONDITIONS

(Voltage Referenced to Vss. TA = ODC to 70DC)

Parameter

Min

Typ

Max

Units

Vee

Supply Voltage

4.5

5.0

5.5

Vss

Ground.

VIH

Input High Voltage

2.4

VIL

Input Low Voltage

-1.0

Symbol

CAPACITANCE
Symbol

-.
-

Vee

0.8

V
V

(TA = 25D C)

Parameter

Cj(A)

Input Capacitance (AO-A9)

Min

Max

Units

Cdq

1/0 Capacitance

Cj(W)

Input Capacitance, Write Control Input

Cj (RAS)

Input Capacitance, RAS Input

100

Cj(CAS)

Input Capacitance, CAS Input

100

Cj(CASP)

Input Capacitance, CASP Input

Cj (DP)

Input Capacitance

Co (QP)

Output Capacitance

3-93

202569

D.C. AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)

Symbol
ICC1
ICC2

Standby Current

-I
Ice3

tRC

=
=

RAS
RAS

CAS

=
=

Min

Max

Units

205
175

rnA

VIH

rnA

Vec -0.2V

rnA

-08
-10

Min)

CAS

RAS Only Refresh Current
= VIH. RAS Cycling @ tRC

Min)

-08
-10

195
160

rnA

Fast Page Mode Current
(RAS = VIL. CAS Cycling

Min)

-08
-10

165
135

rnA

-08
-10

205
175

rnA

(CAS
ICC4

Speed

Parameter
Operating Current
(RAS and CAS Cycling

tpc

ICC6

CAS-before-RAS Refresh Current
(RAS and CAS Cycling @ tRC = Min)

IlL

Input Current
(Any Input 0 ~ VIN ~ 6.5V
All Other Pins = OV)

-90

,..,A

loz

Off State Output Current
(Data Out is Disabled and
~ VOUT ~ 5.5V)

-30

p,A

VOH

Output High Voltage Level
(IOH = -5 rnA)

2.4

Vce

VOL

Output Low Voltage Level
(IOL = 4.2 rnA)

0.4

NOTE:
ICC1. Icca. ICC4 and Ices are dependent on output loading and cycle rates. Specified values are obtained with the output

open. Icc is specified as average current.

3-94

inter

202569

A.C. CHARACTERISTICS(1,2) (TA =
Symbol

Parameter

0·Cto70·C, Vcc

2D2569-08

Min

Max

5V ±10%)

2D2569-10

Min

Notes

4, 7

tRAC

Access Time from RAS

tCAC

Acces Time from CAS

5, 7

tCAA

Access Time from
Column Address

6, 7

tCPA

Access Time from CAS
Precharge

7, 14

tCLZ

Output Low Impedance
Time from CAS Low

tOFF

Output Disable Time
after CAS High

tREF

Refresh Cycle Time

Transition Time

Units

Mas
100

5
0

tRP

RAS High Pulse Width

tCRP

CAS to RAS Precharge
Time

tRCD

RAS to CAS Delay Time

tCPN

CAS High Pulse Width

tRAD

Column Addres Delay
Time from RAS Low

tASR

Row Address Setup
Time before RAS Low

tASC

Column Address Time
before CAS Low

tRAH

Row Address Hold Time
after RAS LOW

tCAH

Column Address Hold Time
after CAS Low or W Low

3-95

25
40

9,10

ns
50

202569

A.C. CHARACTERISTICS(1, 2) (Continued) (TA =

O°C to 70°C, VCC

5V ± 10%)"

REAO ANO REFRESH CYCLES

Symbol

Parameter

202569-08
Min

202569·10

Max

Min

Units

Notes

Max

tRC

Read Cycle Time

150

tRAS

RAS Low Pulse Width

10K

100

10K

teAS

CAS Low Pulse Width

10K

tCSH

CAS Hold Time
after RAS Low

100

tRSH

RAS Hold Time after '
CAS Low

tRCS

Read Setup Time
before CAS Low

tRCH

Read Hold Time
after CAS High

tRRH

Read Hold Time
after RAS High

tRAL

Column Address to
RAS Setup Time

tRPC

Precharge to CAS
Active Time

190

CAS BEFORE RAS REFRESH CYCLE

Symbol

Parameter

202569-08
Max

Min

202569·10
Min

Units

Max

teSR

CAS Set Up Time for CAS
before RAS Refresh

tCHR

CAS Hold Time for CAS
before RAS Refresh

tRPC

Precharge to CAS
Active Time

3-96

Notes

infef

202569

A.C. CHARACTERISTICS (Continued) (TA =

O·C to 70·C, Vee

5V ± 10%)

WRITE CYCLE (Early'Write)
Symbol

Parameter

202569-08
Min

202569-10

Max

Min

10K

160

Units

twe

Write Cycle Time

160

tRAS

RAS Low Pulse Width

130

190

tDS

Data Setup Time

tDH

Data Hold Time
after CAS Low

teAS

CAS Low Pulse Width

tesH

CAS Hold Time
after RAS Low

100

tRSH

RAS Hold Time
after CAS Low

twes

Write Setup Time
before CAS Low

tweH

Write Hold Time
after CAS Low

twp

Write Pulse Width

10K

3-97

Notes

Max
ns
10K

inter

202569

FAST PAGE MODE CYCLE (Read, Early Write cycles)

Symbol

Parameter

202569-08
Min

Max

202569-10
Mi':'l

Units

tpc

Fast Page Mode
Cycle Time

tRAS

RAS Low Pulse Width
for Read, Write Cycle

130

10K

160

10K

,ns

teAS

CAS Low Pulse Width,
for Read Cycle

10K

tep

CAS High Pulse Width

Notes

Max
ns

NOTES:
1. An initial pause of 500 J.Ls is required after power-up followed by any 8 RAS-only cycles before proper device operation is
achieved.
2. A.C. Characteristics assume tT = 5 ns.
3. VIH(min) and Vldmax) are reference levels for measuring timing of input signals. Also, transition times are measured
between VIH (min) and VIL(max).
4. Assumes that tRCO ,;: tRco(max), tRAO ,;: tRAo(max). If tRCO (or tRAO) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCO (or tRAO) exceeds the value shown.
'
5. If tRCO :<: tRCO(max). tRAO :<: tRAO(max). and tASC :<: tM - tCAC - tT. access time is tCAC.
6. If tRAO ;;, tRAO(max) and tASC ,;: tM - tCAC - tT. access time is tM'
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. tOFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCO(max) limit insures that tRAc(max) can be met. tRco(max) is specified as a reference point only;
if tRCO is greater than the specified tRCO(max) limit. access time is controlled exclusively by tCAC or tM'
10. tRCO(min) = tRAH(min) + 2tT + tASc(min).
11. Operation, within the tRAo(max) limit insures that tRAc(max) can be met. tRAO (max) is specified as a reference point
only; if tRAO is greater than the specified tRAo(max) limit. access time is exclusively controlled by tCAC or tM'
12. Either tRRH or tRCH must be specified for a read cycle.
13. twCS. tCWO. tRWO and tAWO are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
14. tCPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").

3-98

202569

READ CYCLE

VIH -

VIH-~~~~~~~~~~~----~--------------~----~~~~
WRITE

VOH -

DOUT

VOL -

----------

: "HI! or ilL"
240838-4

3-99

2D2569

EARLY WRITE CYCLE

VOH -

Dour

VOL -

- - - - - - - - - - - - - OPEN - - - - - - - - - - - - -

:"H"or"L"
240838-5

3-100

inter

202569

RAS ONLY REFRESH CYCLE

VOH DOUT

- - - - - - - - - - - - OPEN - - - - - - - - - - - - VOL -

~ : "H"or"L"
240838-6

CAS BEFORE RAS REFRESH CYCLE

VOH DOUT
VOL -

1)------- OPEN

_ _ _ _-'I

-------------

: "H"or"L"
240838-7

3-101

inter

202569

HIDDEN REFRESH CYCLE (READ)

VOH -

Dour
VOL -

---------+

Access Time from CAS (teAC>

Read Cycle Time (tRC>

125

140

160

190

1,048,576 X 9-Bit Organization
Industry Standard Pin-Out in a 30-Pin
Single In-Line Memory Module (SIMM)
Common I/O Using "Early Write"
Single 5V

+ 10% Power Supply

512 Refresh Cycles every 8 ms

•
•
•

Separate CAS Control for Eight
Common Data-In and Data-Out Lines
Separate CAS (CAS8) Control for One
Separate Pair of Data-In and Data-Out
Lines
TTL Compatible Inputs and Outputs

The 21019 is a 1,048,576 words by 9-bit memory module consisting of industry standard 1 Meg x 1 dynamic
RAMs in SOJ package.
The 20 address bits are entered 10 bits at a time using RAS to latch the first 10 bits and CAS to control the
latter 10 bits. The ninth bit 08, 08 is generally used for parity and is controlled by CAS8.
The common I/O feature requires the use of an early write cycle to prevent data contention on DO lines.

-0
vee
CAS
000
AO
Al
001
A2
A3

vss
002
A4

AS
003
A6

A7
004
A8
A9
N.C.
DOS

(1) D
(2) D
(3) D
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)

D
D
D
D
D
D
D
D
D
D
D
D
D
D
~18) D
19) D
20) D

Pin Names

(21)
vss (22)
006 (23)
N.C. (24) D
007 (25)
08
(26)
RAS (27)
CAS8 (28)
08
(29)
vee (30)

~I
~I

AO-A9

Address Inputs

001-007

Data Inputs/Outputs

Data Input

Data Output

RAS

Row Address Strobe

CAS-CAS8

Column Address Strobe

R/W Input

Vee

Power (+5V)

Vss

Ground

N.C.

No Connection

0
240721-1

Figure 1. Pin Assignment

3-107

November 1990
Order Number: 240721-002

infef

21019

000

r-l\

f-c

r-c

f-c

r-c

RAS

I-<
f-c

WRITE

DOS

l....'\

RAS

CAS

~f-

WRITE

D03

r-c

DOS

I-<
f-c

[

RAS

WRITE

t-- D

f-c

r-c

AONA9
RAS
CAS
WRITE

t-- D

AONA9

HI-

WRITE

HI-

~ CAS

RAS
CAS

t-- 0

L..t-,

AONA9

-D

AONA9

HID02

r-l\

CAS

t-- D

AONA9

Hr
D01

004

AONA9
RAS

f-<

CAS

f-c

WRITE

HI-

D07

t-- D

AONA9
RAS

CAS

I-

WRITE

f-c
f-c

AONA9
RAS
CAS
WRITE

Hr
D8

I-- D

LJ\,
i-...y

RAS
CAS

RAS

CASs

CAS

WRITE

O~ 08

AONA9

WRITE

f-1r

Vee

Vss

240721-2

Figure 2. Block Diagram

3-108

inter

21019

'"cio
'"
~

H~ ,... ...."
.--

E
E

'xr-.

'"'"..;

O~
nnnnn

::!

nnnnn

<{
~

'"o '"ai
'" ,...
CQ

'"'"

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

'"ci
'"
'ot

'ot

.... N'"

, ,t\.

-:::

'+'

'---

·XVri

"'9

sv·oz

Figure 3. Outline Drawing
3-109

21019

ABSOLUTE MAXIMUM RATINGS*

. NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Voltage on Any Pin Relative
to vss (VIN' VOUT) .............. -1V to + 7.0V
Voltage on Power Supply
RelativetoVss(Vec) ........... -1Vto +7.0V

• WARNING: Stressing (he device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Storage Temperature (TSTG) .... - 55°C to + 125°C
'. Soldering Temperature. Time
(Tsolder) ....................... 260°C • 10 Sec
Power Dissipation (Pd) ....................... 9W
Short Circuit Output
Current (lOUT)' .... : .................... 50 mA

RECOMMENDED OPERATING CONDITIONS

(Voltage Referenced to Vss. T A

O°C to 70°C)

Parameter

Min

Typ

Max

Units

Vee

Supply Voltage

4:5

5.0

5.5

Vss

Ground

VIH

Input High Voltage

2.4

6.5

VIL

Input Low Voltage

-1.0

0.8

Symbol

CAPACITANCE
Symbol

(TA

25°C)

Parameter

Min

Max

Units

Ci(A)

Input Capacitance (AO-A9)

Cdq

1/0 Capacitance

Cj (W)

Input Capacitance, Write Control Input

Cj (RAS)

Input Capacitance, RAS Input

100

Cj (CAS)

. Input Capacitance, CAS Input

100

Input Capacitance, CASP Input

Cj(DP)

Input Capacitance

Co (QP)

Output Capacitance

Cj(CASP)

3-110

21019

D.C. AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)

Symbol
ICCl

ICC2

ICC3

ICC4

Speed

Max

Units

810
720
675
540

VIH

VCC -0.2V

-06
-07
-08
-10

810
720
675
540

-06
-07
-08
-10

630
560
540
450

-06
-07
-08
-10

810
720
675
540

Parameter
Operating Current
(RAS and CAS Cycling

Standby Current

I
I

tRC

=
=

RAS
RAS

Min)

CAS
CAS

=
=

RAS Only Refresh Current
(CAS = VIH. RAS Cycling @ tRC

Min)

Fast Page Mode Current
(RAS = VIL. CAS Cycling

Min)

tpc

Min

-06
-07
-08
-10

Iccs

CAS·before·RAS Refresh Current
(RAS and CAS Cycling @ tRC = Min)

IlL

Input Current
(Any Input 0 :;:;: VIN :;:;: 6.5V
All Other Pins = OV)

-90

/LA

loz

Off State Output Current
(Data Out is Disabled and
0:;:;: VOUT :;:;: 5.5V)

-20

/LA

VOH

Output High Voltage Level
(IOH = -5 mAl

2.4

VCC

VOL

Output Low Voltage Level
(IOL = 4.2 mAl

0.4

NOTE:
ICC1. ICC3. ICC4 and ICC6 are dependent on output loading anq cycle rates. Specified values are obtained with the output
open. Icc is specified as average current.

3·111

inter

21019

A.C. CHARACTERISTICS(1, 2) (TA = 0·Cto70·C, Vee = 5V ±10%)
Symbol

Parameter

21019-06

21019-07

;21019-08

21019-10

Min

Max

Units

Notes

Max

tRAC

Access Time from RAS

100

4, 7

tCAC

Acces Time from CAS

5, 7

tCAA

Access Time from
Column Address

6, 7

tCPA

Access Time from CAS
Precharge

7, 14

tClZ

Output Low Impedance
Time from CAS Low

toFF

Output Disable Time
after CAS High

tREF

Refresh Cycle Time

Transition Time

tRP

RAS High Pulse Width

tCRP

CAS to RAS Precharge
Time

8
50

5
20

8
3

tRCD

RAS to CAS Delay Time

tCPN'

CAS High Pulse Width

tRAD

Column Address Delay
Time from RAS Low

tASR

Row Address Setup
Time before RAS Low

tASC

Column Address Time
before CAS Low

tRAH

Row Address Hold Time
after RAS LOW

tCAH

Column Address Hold Time
after CAS Low or W Low

35
30

0
20

3-112

35
20

0
20

35
20

9,10

ns
50

0
20

ns
ns

intJ

21019

A.C. CHARACTERISTICS(1, 2) (Continued) (TA

O°Cto 70°C, Vee = 5V ±10%)

READ AND REFRESH CYCLES
Symbol

21019-06

Parameter

Min

Max

21019-07
Min

Max

21019-08
Min

Max

21019-10
Min

Units

Notes

Max

tRC

Read Cycle Time

125

tRAS

RAS Low Pulse Width

10K

tCAS

CAS Low Pulse Width

10K

tCSH

CAS Hold Time
after RAS Low

100

tRSH

RAS Hold Time after
CAS Low

tRCS

Read Setup Time
before CAS Low

tRCH

Read Hold Time
after CAS High

tRRH

Read Hold Time
after RAS High

tRAL

Column Address to
RAS Setup Time

tRPC

Precharge to CAS
Active Time

140
10K

10K

190

160

10K

100

10K

CAS BEFORE RAS REFRESH CYCLE
Symbol.

Parameter

21019-06

21019-07

21019-08

21019-10

Min

Max

Units

Max

tCSR

CAS Set Up Time for CAS
before RAS Refresh

tCHR

CAS Hold Time for CAS
before RAS Refresh

tRPC

Precharge to CAS
Active Time

3-113

Notes

intJ

21019

A.C. CHARACTERISTICS (Continued) (TA =

O·C to 70·C, Vcc

5V ± 10%)

WRITE CYCLE (Early Write)

Symbol

Parameter

21019-06

Min

Max

21019-07

Min

Max

21019-08

Min

Max

21019-10

Min

Units

twc

Write Cycle Time

150

160

tRAS

RAS Low Pulse Width

120

125

130

tDS

Data Setup Time

tDH

Data Hold Time
after CAS Low

tCAS

CAS Low Pulse Width

tcSH

CAS Hold Time
after RAS Low

100

tRSH

RAS Hold Time
after CAS Low

twcs

Write Setup Time
before CAS Low

tWCH

Write Hold Time
after CAS Low

twp

Write Pulse Width

.15

10K

3-114

10K

190
10K

10K

160

Notes

Max
ns
10K

inter

21019

FAST PAGE MODE CYCLE (Read, Early Write cycles)
Symbol

Parameter

21019-06
Min

Max

21019-07
Min

Max

21019-08
Min

Max

21019-10
Min

Units

tpc

Fast Page Mode
Cycle Time

tRAS

RAS Low Pulse Width
for Read, Write Cycle

120

10K

120

10K

130

10K

160

10K

tCAs

CAS Low Pulse Width
for Read Cycle

10K

tcp

CAS High Pulse Width

Notes

Max
ns

NOTES:
1. An initial pause of 500 ",s is required after power-up followed by any 8 RAS-only cycles before proper device operation is
aChieved.
2. A.C. Characteristics assume tT = 5 ns.
3. VIH(min) and Vldmax) are reference levels for measuring timing of input signals. Also, transition times are measured
between VIH (min) and VIL(max).
4. Assumes that tRCO ,,; tRCO(max), tRAO ,,; tRAo(max). If tRCO (or tRAO) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCO (or tRAO) exceeds the value shown.
5. If tRCO 2: tRCO(max), tRAO 2: tRAO(max), and tASC 2: tM - tCAC - tT, access time is tCAC.
6. If tRAO 2: tRAO(max) and tASC ,,; tM - tCAC - tT, access time is tM.
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. tOFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCO(max) limit insures that tRAc{max) can be met. tRco(max) is specified as a reference point only;
if tRCO is greater than the specified tRCO(max) limit, access time is controlled exclusively by tCAC or tAA.
10. tRco(min) = tRAH(min) + 2tT + tAsc{min).
11. Operation within the tRAO(max) limit insures that tRAc{max) can be met. tRAO (max) is specified as a reference point
only; if tAAO is greater than the specified tAAO(max) limit, access time is exclusively controlled by tCAC or tM.
12. Either tRRH or tACH must be specified for a read cycle.
13. twcs, tcwo, tRWO and tAWO are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
14. tePA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").

3-115

intJ

21019

READ CYCLE

tCSH

VIH CAS

VIL tRAD

VIH AONAg
VIL -

VOH POUT

VOL -

- - - - - - - OPEN

-------(1":
~

VALID DATA

: "H" or "Lu
240721-4

3-116

21019

EARLY WRITE CYCLE

VOH -

VALID DATA

DIN

VOL -

;..,:.'-6."""'''''''''''''''.......'-6.'-6..:.1

VOH -

DOUT

VOL -

- - - - - - - - - - - - - - OPEN - - - - - - - - - - - - - -

:"H"or"L"
240721-5

3-117

inter

21019

RAS ONLY REFRESH CYCLE

t RAS

V1H CAS
V1L t ASR

AO~A8

tRAH

V1H V1L -

VOH DOUT

- - - - - - - - - - - - - OPEN - - - - - - - - - - - - - VOL -

: !'H" or ilL"
240721-6

CAS BEFORE RAS REFRESH CYCLE

VOH DoUT

1>-------- OPEN - - - - - - - - - - - - -

.
VOL- _ _ _ _""""'I

: "H," or ilL"

240721-7

3-118

inter

21019

HIDDEN REFRESH CYCLE (READ)

t RAS

VOH DOUT

VOL -

----------+~

~ : "H"or"L"
240721-8

3-119

inter

21019

HIDDEN REFRESH CYCLE (WRITE)

DIN

VIL -

..............................*-1

1'-------'"'1

VOH DOUT

VOL -

- - - - - - - - - - - - - - OPEN - - - - - - - - - - - - - -

:"H"or"L"
240721-9

3-120

inter

21019

FAST PAGE MODE READ CYCLE
,

t RASP

RAS

VIH -

t RP

I-~

Vll -

t CRP

t RCD

,,\

CAS V I H - J
Vll -

tcp

tCAS

,,\

tcp
~

tCAS
~

-.::.:....

,,\

Ao~A9

VIH-~
Vll -

tRAl

ROW

t ASC

-leAH

COL

"~- f1

t RCS

F- ~

:::=~

tCAC
tAA

t Asc

tCAH

~
~~ -l

COL

tRAD

WRITE

-- - -- ~ - -- - -t AsC

tRAH

t CRP

tCAS

....::.:..:.:..

tAR
t ASR

'--

t RSH

tpc

tCSH

b
t RCS

tAA

t RCH

t Rcs

tAA

DATA

tCPA

..,. ,.............,

"" ..---.

~r-~
VALID

-- -

tCAC

tCPA

VOl -

tCAC

VOH -

COL

W -- W -I
I

t RAC

DOUT

tCAH

tOFF

tcLZ

[ZI

VALID
DATA

tOFF

-- -

VALID
DATA

tOFF

tClZ

: "H" or "L"
240721-10

3-121

inter

21019

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

DIN

VIL -

"""''''''''''''''''''''''''''''''''~ l'-----~

VOH -

Dour

VOL -

- - - - - - - - - - - - - - - OPEN

: "H" or"L"
240721-11

3-122

inter

21019

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

RAS

t RsH

VIH VIL tCHR

CAS

t CPT

tCAS

VIH VIL -

VIH Ao~A9

VIL -

READ CYCLE
VOH DOUT
VOL -

_ _ VIH WRITE
VIL WRITE CYCLE
VOH OPEN

DOUT
tCWL

VOL

t RWL
twcs

t WCH

VIH WRITE
VIL -

VIH DIN

VIL -

: "H"or"L"
240721-12

3-123

225636
256K x 36-BIT DYNAMIC RAM
MEMORY MODULE WITH PAGE MODE
•

Performance Range

•
•
•
•

Parameters

225636-08

225636-10

Access Time from RAS (tRAC>

100

Access Time from CAS (tcAC>

Read Cycle Time (tRC>

150

180

256K x 36-Bit Organization
Industry Standard Pin-Out in a 72-Pin
Single In-Line Memory Module (SIMM)
Common 1/0 Using "Early Write"
Single 5V

Units

10% Power Supply

•
•
•
•

512 Refresh Cycles every 8 ms
Separate CAS Control for Each Nine
Common Data-In and Data-Out Lines
Fast Page Mode Operation
TTL Compatible Inputs and Outputs·

The 225636 is a 256K x 36-bit ORAM memory module consisting of Industry Standard CMOS 256K x 4-bit
ORAMs and 256K x 1-bit DRAMs. The module contains eight 256K x 4-bit 20-pin SOJ packages and four 256K
x 1-bit 18-pin PLCC packages. There are bypass capacitors on board on each module.
The 18 address .bits are entered 9 bits at at time using RASO or RAS2 to latch the first 9 bits and CASO, CAS 1,
CAS2 or CAS3 to control the latter 9 bits.
The common liD feature requires the use of an early write cycle to prevent data contention on DO lines.

PIN CONFIGURATIONS (Front View)
Pin Symbol

Pin Symbol

1 Vss
2 000
3 0018
4 001
5 0019
6 002
7 0020
8 003
9 0021
10 Vee
·11 NC
12 Ao
13 Al
14 A2
15 A3
16 A4
17 A5
18 A6
19 NC
20 004
21 0022
22 005
23 0023
24 006

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

49 009
50 0027
51 0010
52 0028
53 0011
54 0029
55 0012
56 0030
57 0013
58 D031
59 Vee
60 0032
61 0014
62 0033
63 0015
64 0034
65 0016
66 NC
67 PD1
68 P02
69 P03
70 P04
71 NC
72 Vss

0024
007
0025
A7
NC
Vee
A8
NC
NC
RAS2
0026
D08
0017
D035
VSS
CASO
CAS2
CAS3
CAS1 '
RASO
NC
NC

W
NC

,dO
DO
DO
DO
DO

36
37

240837-1

Figure 1. Pin Assignment

3-124

October 1990
Order Number: 240837-001

inter

225636

Pin Name
Ao-As
000- 00 35

W
RASO, RAS2
CASO-CAS3
P01-P04
Vee
Vss
NC

Presence Detect Pins (Optional)

Pin Function
Address Inputs
Data In/Out
Read/Write Input
Row Address Strobe
Column Address Strobe
Presence Detect
Power (+5V)
Ground
No Connection

80 ns

100 ns

P01
P02
P03
P04

Vss
NC
NC
Vss

Vss
NC
Vss
Vss

AO-AS

iN
RASO
CASO

Ao-As

DQ 1 -oDQO
DQ2 -oOQl
DQ3 - o DQ2
DQ4 - o DQ3

RAS
CAS
W
Ao-As

DQ 1 ;-ODQ 4
DQ 2 -oDQS
DQ3 r-o DQ6
DQ 4 r-o DQ7

RAS
CAS

RAS2
CAS2

iN
Ao-As

RAS
CAS
W
Ao-As
RAS
CAS
W
Ao-As

d]OE

RAS
CAS
W
Ao-As

d]OE

RAS
CAS
W
Ao-As

Vee 0

Da 1
DQ2
OQ3
DQ4

~
~

DQ 1
D02
DQ3
00 4

d]OE

RAS
CAS

D U DQs

RAS
CAS

Ao-As

d]OE

RAS
CAS
W
Ao-As

DQ 1 r-oDOg
DQ2
00 11
DQ3
DQ 4 r-o DQ 12

~~O10

RAS
CAS
W
Ao-As

CAS3

:tr
DQ 1
002
00 3
DQ4

001
002
DQ3
00 4

~
~

mOE
DQ 1
DQ 2
DQ3
DQ4

~~Q13
DQ 14

RAS
CAS
W
Ao-As

f-o DQ 1S
f-o DQ16

mOE
D017

RAS
CAS
W
Ao-As

:tr

•

-L. Vee 0.22}'F Capacitor T II ORA"
.,.. on each DRAM
• 0 a
mS
VSSO~---~~--------------'.

240S37-2

Figure 2. 256K x 36-Bit SIMM Block Diagram

3-125

inter

225636

PACKAGE DIMENSIONS

0.133:t0.004, _
(3.38tO.l0)

______________________

~3~.9~84~

_____________________~,1

(101.19)

RO.062 t 0.004
(1.57tO.l0)

o~0

RO.125,--...
(3.18)
'\

/ 1[:: ::]0001 '"

§l~ ~[:::]

0.250tO.00~_

(107.95)
4250

0 c::: ::]'-El-++

--+

I '\.

I
(6.35tO.l0)
0.250 t 0.004
:.l
0.080 t 0.004, _
(6.35tO.l0)
RO.062 t 0.004
(2.03tO.l0)
(1.57tO.l0)
0.250 --l---I--------------------- ;~3.;:;75~0 --------------------+1
(6.35)
(95.25)

1---i=!o.125 MIN
(3.17)

I--t- 0.200 MAX

DETAIL OF CONTACTS

I ..:

(5.08)

-II- 0.053 (1.35)
0.047 (1.19)
unit: inches (millimeters)

240837-3
Tolerances:

± 0.005 (0.13) unless otherwise specified.

Figure 3. Outline Drawing

3-126

intJ

225636

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative
to vss (VIN, VOUT) .............. -1V to

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.

+ 7.0V

Voltage on Power Supply
Relative to Vss (Vecl ........... -1V to
Storage Temperature (Tsm) .... - 55·C to

+ 7.0V
+ 125·C

Soldering Temperature - Time
(Tsolder) ....................... 260·C -10 Sec
Power Dissipation (Pd) ....................... 9W
Short Circuit Output
Current (lOUT) .......................... 50 mA

RECOMMENDED OPERATING CONDITIONS
Symbol

(Voltage Referenced to VSS. T A = O·C to 70·C)

Parameter

Min

Typ

Max

Units

Vee

Supply Voltage

4.5

5.0

5.5

Vss

Ground

VIH

Input High Voltage

2.4

VIL

Input Low Voltage

-1.0

CAPACITANCE
Symbol

Vee

0.8

V
V

(TA = 25·C)
Min·

Parameter

Max

Units

Ci(A)

Input Capacitance (AO-A9)

Cdq

1/0 Capacitance

Cj (W)

Input Capacitance, Write Control Input

Cj (RAS)

Input Capacitance, RAS Input

Ci (CAS)

Input Capacitance, CAS Input

Ci(CASP)

Input Capacitance, CASP Input

Ci(DP)

Input Capacitance

Co (QP)

Output Capacitance

3-127

intJ

22'5636

D.C. AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)

Symbol
ICCl
ICC2

ICC3
ICC4

Speed

Parameter
Operating Current
(RAS and CAS Cycling
Standby Current

I
I

tRC

=
=

RAS
RAS

-08
-10

Min)

CAS
CAS

=
=

Min

VIH
VCC -0.2V

Max

Units

820
700

RAS OnlyHefresh Current
(CAS = VIH. RAS Cycling @ tRC

Min)

-08
-10

820
700

Fast Page Mode Current
(RAS = VIL. CAS Cycling

Min)

-08
-10

580
480

-08
-10

820
700

tpc

ICC6

CAS-before-RAS Refresh Current
(RAS and CAS Cycling @ tRC = Min)

IlL

Input Current
(Any Input 0 S VIN S 6.5V
All Other Pins = OV)

-120

120

,...A

loz

Off State Output Current
(Data Out is Disabled and
Os VOUT s 5.5V)

-20

,...A

VOH

Output High Voltage Level
(IOH = -5mA)

2.4

Vee

VOL

Output Low Voltage Level
(IOL = 4.2 mA)

0.4

NOTE:
ICC1. ICC3. ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output
open. Icc is specified as average current.

3-128

intJ

225636

A.C. CHARACTERISTICS(1, 2) (TA = O·Cto 70·C, Vcc = 5V ±10%)
Symbol

Parameter

225636·08
Min

Max

225636·10
Min

Units

Notes

Mas

tRAC

Access Time from RAS

100

4, 7

tCAC

Acces Time from CAS

5, 7

tAA

Access Time from
Column Address

6, 7

tCPA

Access Time from CAS
Precharge

7,14

tClZ

Output Low Impedance
Time from CAS Low

tOFF

Output Disable Time
after CAS High

tREF

Refresh Cycle Time

Transition Time

tRP

RAS High Pulse Width

tCRP

CAS to RAS Precharge
Time

tRCD

RAS to CAS Delay Time

tCPN

CAS High Pulse Width

tRAD

Column Addres Delay
Time from RAS Low

tASR

Row Address Setup
Time before RAS Low

tASC

Column Address Time
before CAS Low

tRAH

Row Address Hold Time
after RAS LOW

tCAH

Column Address Hold Time
after CAS Low or W Low

3-129

35
40

9,10

ns
50

a
20

ns
ns

225636

A.C. CHARACTERISTICS(1, 2) (Continued) (TA = O·C to 70·C, VCC = 5V ± 10%)
READ AND REFRESH CYCLES
Symbol

Parameter

225636-08
Min

225636-10

Max

Min

Units

Notes

Max

Read Cycle Time

150

tRAS

RAS Low Pulse Width

10K

100

10K

ris

teAs

CAS Low Pulse Width

10K

tesH

CAS Hold Time
after RAS Low

100

tRSH

RAS Hold Time after
CAS Low

tRCS

Read Setup Time
before CAS Low

tRCH

Read Hold Time
after CAS High

tRRH

Read Hold Time
after RAS High

tRAL

Column Address to
RAS Setup Time

tRPC

Precharge to CAS
Active Time

tRC

180

CAS BEFORE RAS REFRESH CYCLE
Symbol

Parameter

225636-08
Min

Max

225636-10
Min

Units

Max

tesR

CAS Set Up Time for CAS
before RAS Refresh

tCHR

CAS Hold Time for CAS
before RAS Refresh

tRPe

Precharge to CAS
Active Time

3-130

Notes

inter

225636

A.C. CHARACTERISTICS (Continued)

(TA

0·Cto70·C, Vcc

5V ±10%)

WRITE CYCLE (Early Write)
Symbol

Parameter

225636·08
Min

Max

225636·10
Min

Units

twc

Write Cycle Time

160

tRAS

RAS Low Pulse Width

130

190

tos

Data Setup Time

tOH

Data Hold Time
after CAS Low

tCAS

CAS Low Pulse Width

tCSH

CAS Hold Time
after RAS Low

100

tRSH

RAS Hold Time
after CAS Low

twcs

Write Setup Time
before CAS Low

tWCH

Write Hold Time
after CAS Low

twp

Write Pulse Width

10K

3·131

160

Notes

Max
ns
10K

10K

inter

225636

FAST PAGE MODE CYCLE (Read, Early Write cycles)

Symbol

Parameter

225636-08
Min

tpc

Fast Page Mode
Cycle Time

Max

225636-10
Min

Units

tRAS

RAS Low Pulse Width
. for Read, Write Cycle

10K

100

10K

teAS

CAS Low Pulse Width
for Read Cycle

10K

tcp

CAS High Pulse Width

Notes

Max

NOTES:
1. An initial pause of 500 ILs is required after power-up followed by any 8 RAS-only cycles before proper device operation is
achieved.
.
2. A.C. Characteristics assume tT = 5 ns.
3. VIH(min) and VIL(max) are reference levels for measuring timing of input Signals. Also, transition times are measured
between VIH (min) and Vldmax).
.
4. Assumes that tRCO ,;; tRco(max), tRAO ,;; tRAO(max). If tRCO (or tRAO) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCO (or tRAO) exceeds the value shown.
5. If tRCO ;;, tRCO(max), tRAO ;;, tRAO(max), and tASC ;;, tM - !cAC - tT, access time is !cAC.
6. If tRAo ;;, tRAo(max) and tASC ,;; tAA - tCAC - tT, access time is tAA.
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. tOFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCO(max) limit insures that tRAc(max) can be met. tRCO(max) is specified as a reference point only;
if tRCO is greater than the specified tRco(max) limit. access time is controlled exclusively by tCAC or tM.
.
10. tRco(min) = tRAH(min) + 21T + tAsc(min).
11. Operation within the tRAO(max) ·limit insures that tRAc(max) can be met. tRAO (max) is specified as a reference point
only; if tRAO is greater than the specified tRAO(max) limit, access time is exclusively controlled by tCAC or tAA.
12. Either tRRH or tRCH must be specified for a read cycle.
13. twcs. tCWO. tRWO and tAWO are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
14. tCPA is access time from the selection of a new column address (that is caused by changing ~ from "L" to "H").

3-132

225636

READ CYCLE

VOH -

Dour

VOL -

------

: "HI! or"L"
240837-4

3-133

inter

225636

EARLY WRITE CYCLE

VOH~~~~~~~~~ ~~--~--~ ,~~~~~~~~~~
DIN

VALID DATA

VOL--~~~~~~~~~

VOH - DOUT

- - - - - - - - - - - - - OPEN - - - - - - - - - - - - - -

VOL - -

:"H"or"L"
240837-5

3-134

225636

RAS ONLY REFRESH CYCLE

VOH -

DOUT

- - - - - - - - - - - - OPEN - - - - - - - - - - - - VOL -

I2ZJ :

"H" or "L"
240837-6

CAS BEFORE RAS REFRESH CYCLE

VOH -

Dour

1)------- OPEN

VOL- _ _ _ _""""'I

-------------

I2ZJ :"H" or "L"
240837-7

3-135

inter

225636

HIDDEN REFRESH CYCLE (READ)

_ _ V1H -

WRITE

DO~

VOH -

VOL -

----------------~~~
~

: "H"or"L"
240837-8

3-136

inter

225636

HIDDEN REFRESH CYCLE (WRITE)

DIN
VIL -

......"""''''''''''''''''''''''..,

~-----~ ~"'"''''"''''"''''"''''"'''''''''''''''''''''''''''''''''''''''''''~

VOH -

Dour

VOL -

- - - - - - - - - - - - - - OPEN - - - - - - - - - - - - - -

~ : UHf!

or '''L''
240837-9

3-137

inter

225636

FAST PAGE MODE READ CYCLE

--,........,

t RASP
RAS

VIH -

t RP

Vll -

t RCD

tcRP

tcp

tCAS

CAS V I H - J
Vll -

t RSH

tpc

tCSH

tcp

tCAS

AONAg

VIH~~
Vll -

ROW

tRAl

tAse

tRAH
~

I-

+-00

COL

1<,
.~

t RCS

r-I-

tCAC

:-+
tAA

tASC

tCAH

tASC

+-00

COL

- H t RCS

W
. I

tCAC

tAA

... -I

W
I

tCPA
VALID
~r-~
DATA

VOl -

t RCS

t RCH

tCAC
+-00

tAA

tRAC
VOH -

COL

Dour

tCAH
~

b~ b

tRAD

WRITE:::

t CRP

tCAS

......::..:.:.. f---=--

i---=--

tAR
t ASR

l\..

tCPA

'" r---.
~ VALID
DATA
tOrr

tClZ

-=. I-

~
tClZ

I-

tOrr

,.--...,
VALID
DATA

'-I

tOrr

tClZ

: "H" or "Lu
240837-10

3-138

inter

225636

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

DIN

VIL ---...:.

~""",,,",,,,,",,,~'..:..I 1'-----"'1

VOH -

Dour

VOL -

--------------

OPEN - - - - - - - - - - - - - - -

:"H" or"L"
240837-11

3-139

inter

225636

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

RAS

t RSH

VIH VIL tCHR

CAS

t CPT

tCAS

VIH VIL -

VIH Ao~A9

VIL -

READ CYCLE

VOH DOUT

------

VOL -

_ _ VIH WRITE

...:~~~~~"""""""""""""""".u

VIL WRITE CYCLE
VOH DOUT

--------------+1--- OPEN ---1--1----tCWL

VOL

twcs

DIN

VIL -

~~...""""..."'"""""''''''~~;,g l~----~ ""'~"""""'""""'~""""""""""'''''
~ : "H"or"L"
240837-12

3-140

251236
512K x 36-BIT DYNAMIC RAM
MEMORY MODULE WITH PAGE MODE
•

Performance Range
Parameters

251236-08

251236-10

Units

80
20
150

100
25
180

Acces Time from RAS (tRAd
Access Time from CAS (tcAd
Read Cycle Time (tRd

•
•
•
•
•

512K x 36-Bit Organization
Industry Standard Pin-Out in a 72-Pin
Single In-Line Memory Module (SIMM)
Common I/O Using "Early Write"
Single 5V

+ 10% Power Supply

Separate CAS Control for 4 Groups of
18 Common Data-In and Data-Out Lines

•
•
•
•
•

ns
ns

512 Refresh Cycles every 4 ms
Separate CAS (CAS8) Control for One
Separate Pair of Data-In and Data-Out
Lines
Separate RAS Control for 4 Groups of
18 Common Data-In and Data-Out Lines
Fast Page Mode Operation
TTL Compatible Inputs and Outputs

The 251236 is a 512K x 36-bit Oynamic RAM Memory Module consisting of industry standard CMOS, 256K x
4-bit ORAMs and 256K x 1-bit ORAMs. The module contains sixteen 256K x 4-bit in 20-pin plastic SOJ
package and eight 256K x 1-bit in 18-pin PLCC. There are bypass capacitors on board each SIMM module.
The common 1/0 feature requires the use of an early write cycle to prevent data contention on 00 lines.

PIN CONFIGURATIONS (FrontView)
Pin Symbol

Pin Symbol

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

Vss
000
0018
001
0019
002
0020
003
0021
Vee
NC
Ao
Al
A2
A3
A4
A5
A6
NC
004
0022
005
0023
006

0024
007
0025
A7
NC
Vee
A8
NC
NC
RAS2
0026
008
0017
0035
Vss
CASO
CAS2
CAS3
CAS 1
RASO
NC
NC

W
NC

Pin Symbol
49
50
51
52
53
54
,55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

009
0027
001O
0028
0011
0029
0012
0030
0013
0031
Vee
0032
0014
0033
0015
0034
0016
NC
P01
P02
P03
P04
NC
Vss

t---t- 0.350 MAX

I _ I

(8.89)

--II- 0.053(1.35)
0.047(1.19)

240836-13

NOTE:
Components are mounted
on both sides of the board.

240836-12

Figure 1. Pin Assignment
3-141

October 1990
Order Number: 240836-001

251236

CASO
000- 3
~

RASO

1m
~

001
00 2
003
Ao-As DO,

00 1
00 2
00 3
Ao-As DO,

CAS
RAS
OE

00,-7

CAS
RAS
OE

001
CAS I---00 2
_ R~
003
DO, Ao-As W OE:m
DOs

L-.fCAS _
RAS W Ao-As

I
~

001
CAS I---002
_ R~
003
DO, Ao-As W OE:m

CAS
RAS

mOE

-m

--I

-m
-

_ CA~l---"Ao-As W RAS

009- 12

001
00 2
003
Ao-As
0

001
-'002
~_ R~
003
DO, Ao-As W OE

00 17
CAS
RAS

Ao-As

oi-J

1 J

_CA~~

Ao-As W RAS

D0 1S- 21

001
CAS
002
RAS _
003
OE W Ao-As 'DO,

CAS
RAS
OE

001
'
CAS f - 00 2
003
- RAS
DO, Ao-As W OE:m

001
002
00 3
Ao-As DO,
0026

61-1

, 0
40

Ao-As

0027-30

001
002
003
Ao-As DO,

001
00 2
00 3
Ao-As DO,

CAS
RAS
OE

CAS
RAS

001
CAS f 00 2
00 3
_ R~
DO, Ao-As W OE:m
00 31 - 3,

CAS _
RAS W Ao-As

001
CAS002
003
_ R~
DO, Ao~As W OE

0035

6i-J

_CA~~

Ao-As W RAS

001
00 2
CAS
00 3
_ R~
DO, Ao-As W OE-m
0022-25

mOE

Ao-As

001
CAS f 00 2
_ R~
003
DO, Ao-As W OE:m
0013-16

CAS
RAS

--I

001
CAS
00 2
_
00
RAS
3
OE W Ao-As DO,

6t-I

L..-iCAS _
RAS W Ao-A s

, 0

vcco~-----Jt~~0~.2~2-~~F~C-op-0-cl~to-r--·

lr
.._u"_d_er__eO_C_h_D_RA_M__- . To all DRAMs

vsso_______

240836-1

Figure 2. Block Diagram

3-142

(
4.250
(107.95)
0.133:1: 0.004
(3.38:1: 0.1 0)

I·

3.984
(101.19)

RO.062:1: 0.004
(1.57:1: 0.1 0)

_
BQ,ill
(3.18)

0'
ci
ott
CD

c:J c:J c:J c:J
c:J 0 0 0 0 c:J ~+--+I

:uODuu uOCiEl:'ll'

.::.

"TI

cO'

...
e

~
~

aS·
(D

0.080:1: 0.004
(2.03:1: 0.1 0)
0.250
(6.35)

0.250:1:0.004
(6.35:1: 0.1 0)

01-

0.125 MIN
(3.17)

-1'--

...

RO.062:1: 0.004
(1.57:1: 0.1 0)
3.750 _ _ _ _ _ _ _ _ _ _ _ _ __
(95.25)

I\,)

C11

I\,)
(,,)

...IIIC

S·

~0.350

DETAIL OF CONTACTS

I _ I

(8.89) MAX

~
l§

0.010MAXlOAA=t
(0.25)

f
0.050
(1.27)

JJU L

~2~~~)

~
~

MIN

0 041 :I: 0.004
(;.04:1:0.10)

'1iil

-II-- 0.053 (1.35)
0.047 (1.19)
240836-2

@
2EJ
~
~

<=:J

inter

251236

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative
to vss (VIN, VOUT) .............. -1V to

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.

+ 7.0V

Voltage on Power Supply
Relative to vss (Vee> ........... -1V to
Storage Temperature (TSTG) .... - 55°C to

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the .
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

+ 7.0V
+ 125°C

Soldering Temperature. Time
(Tsolder) ....................... 260°C • 10 Sec
Power Dissipation (Pd) ....................... 9W
Short Circuit Output
Current (lOUT)' ...................•..... 50 mA

RECOMMENDED OPERATING CONDITIONS
Symbol
Vee

Parameter

Min

Typ

Max

Units

Supply Voltage

4.5

5.0

5.5

Vss

Ground

VIH

Input High Voltage

VIL

- Input Low Voltage

CAPACITANCE
Symbol

(Voltage Referenced to Vss. TA = O°C to 70°C)

2.4

-1.0

Vee

0.8

V
V

(TA = 25°C)

Max

Units

CdA)

Input Capacitance (AO-A9)

Parameter

Min

Cdq

1/0 Capacitance

Cj (W)

Input Capacitance, Write Control Input

Cj (RAS)

Input Capacitance, RAS Input

Cj (CAS)

Input Capacitance, CAS Input

Cj (CASP)

Input Capacitance, CASP Input

Cj(DP)

Input Capacitance

Co (QP)

Output Capacitance

3-144

251236

D.C. AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)

Parameter

Symbol
ICC1
ICC2

ICC3
iCC4

Operating Current
(RAS and CAS Cycling
Standby Current

I
I

tRC

=
=

RAS
RAS

Speed
-08
-10

Min)

CAS
CAS

=
=

Min

Max

Units

820
750

VIH

VCC -0.2V

RAS Only Refresh Current
(CAS = VIH. RAS Cycling @ tRC

Min)

-08
-10

820
700

Fast Page Mode Current
(RAS = Vil. CAS Cycling

Min)

-08
-10

580
480

mA
mA

-08
-10

820
700

-120

120

/-LA

tpc

ICC6

CAS-before-RAS Refresh Current
(RAS and CAS Cycling @ tRC = Min)

ill

Input Current
(Any Input 0 ,,:; VIN ,,:; 6.5V
All Other Pins = OV)

loz

Off State Output Current
(Data Out is Disabled and 0 ,,:; VOUT ,,:; 5.5V)

-20

/-LA

VOH

Output High Voltage Level
(IOH = -5 mAl

2.4

VCC

VOL

Output Low Voltage Level
(JOL = 4.2 mAl

0.4

NOTE:
ICC1. ICC3. ICC4 and ICG6 are dependent on output loading and cycle rates. Specified values are obtained with the output
open. Icc is specified as average current.

3-145

251236

A C CHARACTERISTICS(1, 2) (TA =
Symbol

Parameter

0°Ct070°C, Vcc

251236-08
Min

Max

5V +10%)
-

251236-10
Min

Units

Notes

Mas

tRAC

Access Time from RAS

100

4,7

·tCAC

Acces Time from CAS

5, 7

tCAA

Access Time from
Column Address

6, 7

tePA

Access Time from CAS
Precharge

7,14

tClZ

Output Low Impedance
Time from CAS Low

tOFF

Output Disable Time
after CAS High

tREF

Refresh Cycle Time

Transition Time

tRP

RAS High Pulse Width

teRP

CAS to RAS Precharge Time

tRCD

RAS to CAS Delay Time

tCPN

CAS High Pulse Width

tRAD

Column Addres Delay
Time from RAS Low

tASR

Row Address Setup
Time before RAS Low·

tASC

Column Address Time
before CAS Low

tRAH

RoW Address Hold Time
after RAS LOW

tCAH

Column Address Hold Time
after CAS Low or W Low

5
25

8
3

3-146

50
60

ns
75

35
40

0
20

9,10

ns
20

251236

A.C. CHARACTERISTICS(1, 2) (Continued) (TA = O°Cto 70°C, VCC = 5V ±10%)
READ AND REFRESH CYCLES
Symbol

Parameter

251236-08
Min

Max

251236-10
Min

Units

Notes

Max

Read Cycle Time

150

tAAS

RAS Low Pulse Width

10K

100

10K

tCAS

CAS Low Pulse Width

10K

tCSH

CAS Hold Time
after RAS Low

100

tASH

RAS Hold Time after
CAS Low

tACS

Read Setup Time
before CAS Low

tACH

Read Hold Time
after CAS High

tAAH

Read Hold Time
after RAS High

tAAL

Column Address to
RAS Setup Time

tAPC

Precharge to CAS
Active Time

tAC

180

CAS BEFORE RAS REFRESH CYCLE
Symbol

Parameter

251236-08
Min

Max

251236-10
Min

Units

Max

tCSA

CAS Set Up Time for CAS
before RAS Refresh

tCHA

CAS Hold Time for CAS
before RAS Refresh

tAPC

Precharge to CAS
Active Time

3-147

Notes

inter

251236

A.C. CHARACTERISTICS (Continued) (TA =

O·C to 70·C. Vcc

5V ± 10%)

WRITE CYCLE (Early Write)
Symbol

Parameter

251236-08
Min

Max

251236-10
Min

Units

twc

Write Cycle Time

160

tRAS

RAS Low Pulse Width

130

tos

Data Setup Time

tOH

Data Hold Time
after CAS Low

tCAS

CAS Low Pulse Width

tCSH

CAS Hold Time
after RAS Low

100

tRSH

RAS Hold Time
after CAS Low

twcs

Write Setup Time
before CAS Low

tWCH

Write Hold Time
after CAS Low

twp

Write Pulse Width

190
10K

10K

3-148

160

Notes

Max
ns
10K

10K

251236

FAST PAGE MODE CYCLE (Read. Early Write cycles)
Symbol

Parameter

251236-08
Min

Max

251236-10
Min

Units

Notes

Max

tpc

Fast Page Mode
Cycle Time

tRAS

RAS Low Pulse Width
for Read. Write Cycle

10K

100

10K

tCAS

CAS Low Pulse Width
for Read Cycle

10K

tcp

CAS High Pulse Width

NOTES:
1. An initial pause of 500 ,..s is required after power-up followed by any 8 RAS-only cycles before proper device operation is
achieved.
2. A.C. Characteristics assume tT = 5 ns.
3. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also. transition times are measured
between VIH (min) and Vldmax).
4. Assumes that tRCO :;; tRCO(max). tRAO :;; tRAo(max). If tRCO (or tRAO) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCO (or tRAO) exceeds the value shown.
5. If tRCO ;;, tRCO(max). tRAO ;;, tRAO(max). and tASC ;;, tAA - tCAC - tT. access time is tCAC'
6. If tRAO ;;, tRAO(max) and tASC :;; tAA - tCAC - tT. access time is tAA.
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. tOFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCO(max) limit insures that tRAdmax) can be met. tRCO(max) is specified as a reference point only;
if tRCO is greater than the specified tRCO(max) limit. access time is controlled exclusively by !cAe or tAA'
10. tRCO(min) = tRAH(min) + 2tT + tAsdmin).
11. Operation within the tRAO(max) limit insures that tRAdmax) can be met. tRAO (max) is specified as a reference paint
only; if tRAO is greater than the specified tRAO(max) limit. access time is exclusively controlled by tCAC or tAA.
12. Either tRRH or tRCH must be specified for a read cycle.
13. twCS. tcWO. tRWO and tAWO are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
14. tCPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").

3-149

251236

READ CYCLE

V1H CAS
V1L tRAD

V1H AO-Ag
V1L -

VOHDOUT

VOL -

- - - - - - OPEN -------<~

VALID DATA

:"H"or"L"
240836-3

3-150

intJ

251236

EARLY WRITE CYCLE

DIN

VOH '

VOL-~~~~""~~~ ~__________~

~~~. . . .~~~~~~. .

VOH -

Dour

VOL -

- - - - - - - - - - - - - OPEN - - - - - - - - - - - - -

:"H"or"L"
240838-4

3-151

inter

251236

RAS ONLY REFRESH CYCLE

VOH-

DOUT

VOL -

- - - - - - - - - - - - OPEN - - - - - - - - - - - - -

~ : "H"or"l"
240836-5

CAS BEFORE RAS REFRESH CYCLE

VOH -

DOUT

I}-------

VOL- _ _ _ _~

OPEN - - - - - - - - - - - - -

~ : "H"or"L"
240836-6

3-152

intJ

251236

HIDDEN REFRESH CYCLE (READ)

VOH DOUT

VOL -

------------l~

: "H" or"L"
240836-7

3-153

251236

HIDDEN REFRESH CYCLE (WRITE)

_ _ VIH WRITE

DIN

VIL -

"""'''''''''''''''''''''''"''''''''''''''';.,

jIo------oJ! """""""""""""""""""",;.0..:""""""""""""""""""""""",,,,,,"

VOH DOUT

- - - - - - - - - - - - - OPEN - - - - - - - - - - - - -

VOL - -

: "H"or "L"
240836-8

3-154

inter

251236

FAST PAGE MODE READ CYCLE
t RASP

RAS

VIH -

t RP

--:.::-..
~

Vll -

t CRP

CAS

tRCD

tcp

tCAS

VIH~J

1\\

Vll -

I-- I--

tcp

tCAS

I--

tRAH

Ao~A9

VIH~~
Vll -

ROW

tASC

tCAH

COL

tRAD

COL

r- f--

:::~

tCAC
tAA

I---

tAA

tCPA

DATA

'="

t RCH

~r-~
VALID
tClZ

t cAC

tCAC

tCPA

VOl -

COL

t RCH

VOH -

tCAH

I--

- -~~ - ~~~
W ....... W .......
I
I

t RAC

DOUT

tASC

tCAH

I--

t RCH

tRCS

WRITE

II
tRAl

tASC

-'-f- i--+

t CRP

,teAs,

tAR
t ASR

t RSH

tpc

tCSH

DATA

tOFF

tClZ

DATA

tOFF

tCLZ

: "H" or "L"
240836-9

3-155

251236

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

DIN

VIL -

"""""""".......'-'-''-'-'"*-' 1'-----""1

VOH -

DOUT

- - - - - - - - - - - - - - OPEN
VOL -

~ :"H" orul"
240836-10

3-156

inter

251236

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

RAS

t RSH

VIH VIL t CPT

tCHR

CAS

tCAS

VIH VIL -

Ao~A9

VIH VIL -

READ CYCLE

VOH DOUT

VOL -

------

_ _ VIH WRITE

VIL WRITE CYCLE
VOH DOUT

"""""""""'""""""""'""""'""""'""""'"""............,

--------------oHf--- OPEN --+-1----tCWL

VOL

twcs

DIN

VIL -

tWCH

.;...:..""""""""""""""""~~..........""'-'......,

: "H" or !fLU
240836-11

3-157

RELIABILITY
REPORT

RR-62

September 1989

Dynamic RAM
Reliability Report

MADHU NIMGAONKAR
COMPONENTS CONTRACTING DIVISION
QUALITY AND RELIABILITY ENGINEERING

Order Number: 240543-001
3-158

DRAM RELIABILITY DATA
SUMMARY

CONTENTS

PAGE

1.0 OVERViEW ........................ 3-160
2.0 RELIABILITY TESTS .............. 3-160
High Temperature Dynamic Lifetest ..... 3-160
High Voltage Dynamic Lifetest .......... 3-160
High Temperature/Humidity Test ....... 3-161
Autoclave .............................. 3-161
High Temperature Storage Test ........ 3-161
Temperature Cycle Test ................ 3-161
Electrostatic Discharge Test ............ 3-161
Soft Error Test ......................... 3-161

3.0 PLASTIC RELIABILITY DATA
SUMMARY ...................... 3-162
P21256 ................................ 3-162
P21464 ................................ 3-163
P21010 ................................ 3-164
P21014 ................................ 3-165
APPENDIX A
COMMON MOS FAILURE
MECHANISMS ......................... 3-166
Common MOS Failure Mechanisms .... 3-166
Oxide Defects .......................... 3-166
Silicon Defects ......................... 3-166
Refresh Degradation ................... 3-166
Contamination ......................... 3-166
Metallization Defects.; ................. 3-166
Soft Errors ............................. 3-166

3-159

RR-62

1.0 OVERVIEW
This reliability report is based on the combination of
actual data from all Intel qualified and approved vendors. This data may vary from lot to lot and under
different operating conditions encountered by the customer. Intel has published data sheet specifications that
should be considered in evaluating the performance for
specific application by the customer. This report does
not give any assurance that the product is appropriate
for any specific application as that decision is the responsibility of the customer.

When reviewing failure rate projections from different
sources, it is important to understand the assumptions
being made. Small changes in details can dramatically
alter an estimated failure rate.

107

Intel recognizes the need to monitor all contracted
products to maintain and improve the level of quality
and reliability consistent with internal goals and customer needs. This is achieved through continuous review of monitor data from all Intel qualified and approved vendors to acheive low defect levels.

106

;,..1
V>
0::

il ~/

105

:I:

'"=>
0::

2.0 RELIABILITY TESTS

...J

104

...
0

High Temperature Dynamic Lifetest

'"i=:::E

This test is performed to accelerate failure mechanisms
that are thermally activated through the application of
extreme temperatures (12S°C) and the use of biased operating conditions (S.SV). The translation from 12SoC
to SsoC is done by applying time acceleration factors
based on the thermal activation energy assignments
noted below. The time acceleration factors from 12SoC
to SsoC are: 3.42 for 0.3 eV, 7.67 for O.S eV and S8.96
for 1.0 eV, based on junction temperature offset for
power dissipation.
Failure rate calculations are given for each relevant activation energy. These are made using the appropriate
activation energy and the Arrhenius Plot as shown in
Figure 1. The total equivalent device hours at a given
temperature can be determined. The failure rate is then
calculated by dividing the number of failures by the
equivalent device hours and is expressed as a %/1000
hours. The failure rate is adjusted by a factor related to
the number of device hours using a chi-square distribution to arrive at a confidence level associated failure
rate. A conservative estimate of the failure rate is obtained by including zero failures at 0.3 eV, O.S eV and
1.0 eV. In cases where the mechanism of the catastrophic failures cannot be determined, 0.3 eV activation energy is assumed.

103

o·

102

III

10~

/
/

....
~~

7 o·

/1:2

./ o:!>
./

V /.V ,/

7
5 U I/./.
3

If) V

250200175150125100 75 50 25

TEMPERATURE (OC)
240543-1

Figure 1. Arrhenius Plot

High Voltage (7V) Dynamic Lifetest
This test is performed to detect failure mechanisms
which are accelerated by high voltage (7V) as well as
high temperature (12S°C). It is especially effective in
accelerating oxide and leakage related failures. The total acceleration factor includes the time acceleration
factors based on the assigned activation energies and
voltage activation factor of 12.7 (7V to "S.SV).

3-160

nt_f
•"••
'eII

RR-62

High Temperature/Humidity Lifetest

Temperature Cycle Test

This test is performed to evaluate moisture resistance
characteristics of plastic encapsulated devices. A woo2000 hour test is performed under static bias conditions
at 85·e/85% relative humidity with nominal voltages.
In order to maximize metal corrosion conditions, the
biasing configuration is either under low power or no
power, with alternate pins biased at + 5V or OV.

This test consists of cycling the temperature of a chamber housing device from -65·e to + l50·e with no
applied bias. Temperature cycling (WOO cycles) is used
to detect mechanical reliability problems and microcracks.

Electrostatic Discharge Test
Autoclave (Pressure Cooker) Test
This test is performed to identify the effects of high
humidity and heat conditions on the die surface. Steam
stressing accelerates moisture penetration through the
plastic package material to the surface of the die, resulting in corrosion of metals.

High Temperature Storage Test
High temperature storage (bake) is a test in which devices are subjected to elevated temperature of ISO·e
with no bias. This test is used to detect mechanical
reliability problems (e.g., bond integrity) and process
instability.

This test is performed to identify device sensitivity to
electrostatic discharge generated during system operation or device-handling. All products incorporate ESD
protection networks on the appropriate pins.

Soft Error Test (SER)
Soft error test is performed to identify the effects of
alpha particles which are emitted in the radioactive decay of uranium and thorium present in packaging materials. Two methods commonly used to measure soft error rates are: 1) accelerated testing using alpha particle
radiation source and 2) real time system level soft error
testing.

3-161

intJ

RR-62

3.0 PLASTIC RELIABILITY DATA SUMMARY
21256
Number of bits: 262,144
Organization: 256K x 1

Process: NMOS
Package: 16-Pin PDIP
Table 1_ Reliability Data Summ'ary
125°C Dynamic Lifetest

Year

168 Hrs

1988/89

3/11250

I
J

500 Hrs

0/11247

7V Dynamic Lifetest

1000 Hrs

168 Hrs

500 Hrs

2/11248

9/2400

5/2391

I
I

1000 Hrs

3/2386

Table 2. Failure Rate Predictions
125°C Actual
Device Hours
2E
21E

Ea
(eV)

+ 06
+ 05

Equivalent Hours
at 55°C

0.3BI
0.3VAF

30E
95E

+ 06
+ 06

5
17

Total 0.3 eV Failures

+ 06
11E + 06

11E

0.0193 (**)

0.0012

0.0001

+ 06
643E + 06

0.5

85E

1.0

Fall Rate %/1K Hours
(60% UCL)

Fail

0.0206
206

Combined Failure Rate:
FITs:
• °5.5V and 7V burn-in/lifetest equivalent hours have been combined.

6Ja
VCC
ICC@55°C
Icc@ 125°C
Icc (max)
Temp. with Tja
T(55)
T (125)

90°C/W (Est.)

=
=
=
=

5.5V
60 rnA
20 rnA
75 rnA (Spec)

BI/ELT
Accel.
Factors:

0.3eV
0.5eV
1.0eV

Thermal Accel_
Factors
55°C
3.42
7.67
58.96

Voltage Accel. Factor (VAF): 12.7

= 358K
= 411K

K = 8.62E -05 eV/K

NOTE:
FIT = Failures in Time. 1 FIT = 1 Failure per 10E

09 device hours.

Failure Analysis:
All failures assumed to be Oxide related.

Table 3. Additional Qualification Tests
Year

1988/89

1000
Temp Cycles

1500C/1K Hrs
High Temp Storage

9/2002

6/8120

0/12200

(0.5%)

(0.07%)

(0.0%)

1000 Hours
85°C/85% R.H.

204Hrs
Steam

9/12552
(0.07%)

Table 4. System SER Results .
Cycle Time

Device Hours

# of Errors

FIT (60%)

1 p.s

1.4M

654

3-162

RR·62

21464
Number of bits: 262,144
Organization: 64K x 4

Process: NMOS
Package: IS-Pin PDIP
Table 1. Reliability Data Summary
12S·C Dynamic Lifetest

Year

I
J

168 Hrs

1988/89

3/11250

I
1

SOO Hrs

0/11247

7V Dynamic Lifetest

1000 Hrs

168 Hrs

2/11248

8/2370

SOO Hrs

3/2362

1000 Hrs

0/2359

Table 2. Failure Rate Predictions
12S·C Actual
Device Hours
9E
21E

Ea
(eV)

+ 06
+ 05

Equivalent Hours
at SS·C

0.381
0.3 VAF

+ 06
+ 06

30E
91E

+ 06
11E + 06

0.0104 ( •• )

0.0012

0.0001

+ 06
645E + 06

0.5

11E

5
11

Total 0.3 eV Failures
84E

1.0

Fail Rate %/1K Hours
(60% UCL)

Fail

0.0117
117

Combined Failure Rate:
FITs:
• *S.SV and 7V burn·in/lifetest equivalent hours have been combined.

OJa

= 90·C/W (Est.)

VCC
ICC@ 55·C
ICC @ 125·C
ICC (max)

= 5.5V

Temp. with Tja
T(55)
T(125)

BI/ELT
Accel.
Factors:

= 60 rnA

0.3eV
0.5eV
1.0 eV

Thermal Accel.
Factors
SS·C
3.42
7.67
58.96

= 20 rnA

= 75 rnA (Spec)

Voltage Accel. Factor (VAF): 12.7

= 358K

= 8.62E -05 eV/K

411K

NOTE:
FIT = Failures in Time. 1 FIT = 1 Failure per 10E

09 device hours.

Failure Analysis:
All failures assumed to be Oxide related.

Table 3. Additional Qualification Tests
Year

1988/89

1000 Hours
8S·C/8S% R.H.

204 Hrs
Steam

1000
Temp Cycles

1S0·CI1K Hrs
High Temp Storage

6/2310

2/1320

5/564

1/1100

(0.25%)

(0.15%)

(0.6%)

(0.10%)

Table 4. System SER Result
Vee

Cycle Time

Device Hours

# of Errors

FIT (60%)

1 IJ-s

1.4M

630

3-163

RR-62

21010
Process: CMOS
Package: 18-Pin PDIP

Number of bits: 1,048,576
Organization: 1M x 1

Table 1. Reliability Data Summary
7V Dynamic Lifetest

Year

I
I

168 Hrs

1988/89

7/2060

I
I

SOO Hrs

4/2053

1000 Hrs

4/2049

Table 2. Failure Rate Predictions
12S·C Actual
Device Hours

Ea
(eV)

19E

+ 05
+ 05
19E + 05

0.3 )

19E

0.5

Equivalent Hours
atSS·C

Fail

+ 06
+ 06
112E + 06

1.0

Fail Rate %/1'K Hours
(60% UCL)

82E

0.0204

15E

0.0070

0.0009

Combined Failure Rate:
FITs:

90·C/W (Est.)

9Ja

Vcc
Icc@ 55·C
Icc@ 125·C
Icc (max)

= 5.5V

Temp. with Tja
T (55)
T (125)

BI/ELT
Accel.
Factors:

60mA

0.0283
283
Thermal Accel.
Factors
SS·C
3.42
7.67
58.96

0.3eV
0.5eV
1.0eV

= 20mA
=

75 mA (Spec)

Voltage Accel. Factor (VAF): 12.7

358K
411K

NOTE:
FIT = Failures in Time. 1 FIT = 1 Failure per 10E

8.62E -05 eViK

09 device hours.

Failure Analysis:
All failures assumed to be Oxide related.

Table 3. Additional Qualification Tests
Year

1988/89

1000 Hours
8S·C/8S%. R.H.

204 Hrs
Steam

1000
Temp Cycles

1S0·C/1K Hrs
High Temp Storage

9/2410

1/2420

1/1906

3/2140

(0.3%)

(0.04%)

(0.05%)

(0.14%)

Table 4. System SER Result
Cycle Time

Device Hours

'# of Errors

FIT (60%)

1 JLs

1.2M

763

3-164

inter

RR-62

Table S. Latch-Up/ESD Test Results
# of Runs

Sampl~Size

Latch-Up Level

ESD Level

25 Units

>125 rnA

> 2500V

SOJ Package Qualification Data Summary
Year

1000 Hours
8S·C/8S% R.H.

204 Hours
Steal11

1000
Temp Cycles

1988/89

1/645
(0.16%)

2/504
(0.4%)

1/300
(0.3%)

21014
Number of bits: 1,048,576
Organization: 256K x 4

Process: CMOS
Package: 20-Pin PDIP
Table 1. Reliability Data Summary
High Voltage (7V) Dynamic Lifetest

Year

168 Hrs
3/600

1989

I
I

SOO Hrs
1/597

I
I-

1000 Hrs
0/597

Failure Rate Prediction:
Due to small number of actual device hours on this new product, a detailed reliability prediction would not be meaningful.

Table 2. Additional Qualification Tests
Year

1000 Hours
8S·C/8S% R.H.

204 Hrs.
Steam

1000
Temp Cycles

1S0·C/1K Hrs
High Temp Storage

1989

1/250
(0.40%)

1/500
(0.20%)

0/250
(0.0%)

0/500
(0.0%)

3-165

inter

RR-62

APPENDIX A
COMMON MOS· FAILURE MECHANISMS
Oxide Defects

Contamination

Oxide defects cim cause dielectric breakdown in MOS
structures, resulting in: an electrical short. Oxide dielectric breakdown is dependent on time, ambient temperature and operating voltage. Oxide defects could be induced by excessively thin oxide, polarization and contamination. The activation energy for Oxide defects is
determined to be 0.3 eV.

MOS circuits can fail due to threshold voltage (Vt)
shifts when subjected to mobile ionic contamination.
This ionic contamination reaches critical circuits
through passivation defects subsequent to wafer processing. Sodium is the most common species of ionic
contamination. The activation energy of ionic contamination is 1.0 eV.

Silicon Defects

Metallization Defects

Silicon defects are inherent in the unprocessed silicon
wafers and may also be generated by stresses on the
lattice during MOS processing. These silicon defects enhance parasitic leakage when they become active by
"gettering" contaminants. The activation energy for silicon defects is determined to be 0.5 eV.

Metallization defects (defects relating to metal conductor paths on the semiconductor die) can occur due to
metal contamination, excess current density (electromigration) in the conductors, microcracks caused by
sharp oxide steps and overalloying due to migration of
metal through the semiconductor's contact. The activation energy is 0.5 eV.

Refresh Degradation
In general, refresh failures are the result of degradation
of random single bits caused by localized carrier generation. A localized silicon defect can act as a gathering
site for contaminants and if this defect is located near a
storage cell, it can cause this isolated cell to have poor
refresh characteristics. The activation energy of refresh
degradation is 0.5 eV.

Sof~

Errors

Soft errors refer to random non-recurring single bit er. rors and can be generated by noise in the device or
system or by impact ionization from alpha particles.
Alpha particles originating in the package penetrate the
die surface, sometimes generating sufficient charge to
switch the logic state of a cell. Soft error rates can be
reduced by using low alpha packaging materials, die
coating to prevent alpha particles from reaching the
chip surface and optimal circuit designs to resist alpha
particle disturbances.

3-166

Static RAMs
(Random Access Memories)

5116S/L
2K x 8-BIT CMOS STATIC RAM

•
•
•

51165·10

51165·12

Address Access Time (tAA)

100

120

Chip Select Access Time (tACS)

100

120

Output Enable Access Time (tOE)

•
•
•
•

Static Operation
- No Clock/Refresh Required
Equal Access and Cycle Times
- Simplifies System Design
Single

+ 5V Supply

Unit

Power Down Mode
TTL Compatible
Common Data Input and Output
High Reliability 24·Pin 600 Mil PDIP
Package

The 5116S is a 2048-word by 8-bit CMOS static RAM fabricated using CMOS Silicon Gate process.
When the Chip Select is brought high, the device assumes a standby mode in which the standby current is
reduced to 2 p,A (max). The 5116S has a data retention mode that guarantees that data will remain at
minimum power supply voltage of 2.0V.
Block Diagram

Pin Connections

vee
~
~

128 x 128
MEMORY ARRAY

GND

•••••••
COLUMN I/O

240571-2

Pin Names

cs 0o:::.:.r:CO:N~TR:O::-L'
CE

CIRCUIT

....

t----------------4~

O---L::=::.:......J

240571-1

4-1

AO-A1,O

Address Input

Do-D7

Data Input/Output

Chip Select Input

Write Enable Input

Output Enable Input

VCC

Power

GND

Ground

October 1989
Order Number: 240571-002

inter

5116S/L

Device Operation

Write Mode

The 5116S has two control inputs: Chip Select (CS)
and Write Enable (WE). CS is the power control pin
and should be used for device operation. WE is the
data control pin and should be used to gate data at
the 1/0 pins.

Write Cycles may be controlled by either WE or CS.
In either case, both WE and CS must be high (VIH)
during address transitions. During a WE Controlled
write cycle, CS must be held low (Vld while WE is
low. Address transfers occur on the falling edge of
WE and the data transfers on rising edge of WE.
During a CS controlled cycle, WE must be held low
(Vld while CS is low. The addresses are then transferred on the falling edge of CS and data on the
rising edge of CS. Data, in both cases, must be valid
for a time tDW before the controlling input is brought
high (VI H) and remain valid for a time tDH after the
controlling input is high.

Standby Power
The 5116S is placed in a standby or reduced power
consumption mode by applying a high (VIH) to the
CS input. When in standby mode, the device is deselected and the outputs are in a high impedance
state, ind.ependent of the WE input.

Read Mode

Table 1. Mode Selection Truth Table
CS

Mode

I/O

Power

Standby

HighZ

Standby

Write

DIN

Active

Read

Dour

Active

Read

HighZ

Active

CS must be low (Vld and WE must be high (VIH) to
activate a read cycle and obtain data at the outputs.
Given stable addresses, valid data is available after
a time tAA.

4-2

inter

5116S/L

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative
to Ground (VIN' VOUT) ..•........ -0.3V to
Storage Temperature (Tstg) ..... - 55°C to

NOTICE: This is a production data sheet. The specifi·
cations are subject to change without notice.

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex·
tended exposure beyond the "Operating Conditions"
may affect device reliability.

+ 7V

+ 150°C

Power Dissipation (Po) ..................... 1.0W
DC Continuous Output Current (los) ......... 50 mA

RECOMMENDED OPERATING CONDITIONS
Symbol

Voltage referenced to Vss, TA = O°C to 70°C

Parameter

Min

Typ

Max

Unit

Vee

Supply Voltage

4.5

5.0

5.5

Vss

Ground

VIH

Input High Voltage

2.2

Vee + 0.3

Input Low Voltage

-0.3

0.8

VIL
NOTE:

1. During transitions, the inputs may undershoot to - 3.5V for periods less than 20 ns.

CAPACITANCE
Symbol

25°C, f

1.0 MHz

Parameter

Min

CIN1

Input Capacitance (VIN

COUT

Output Capacitance (VOUT

OV)

NOTE:

This parameter is sampled and not 100% tested.

'4-3

Max

Unit

inter

5116S/L

D.C. AND OPERATING CHARACTERISTICS
Recommended Operating Conditions unless otherwise noted

Symbol

Typ

Max

Units

leGl

Operating Current

Parameter

rnA

Vee = Max, ~
Outputs open

lee2

Dynamic Current

rnA

T eye = Min, Vee
Outputs open

rnA

9S = VIH

p.A

CS;::;' Vee - 0.2V
VIN = GND to Vee

Min

19B
ISBl

Standby
Current

I
I

STD
L

0.2'

:rest Conditions

VIL

Max

III

Input Load Current

-1

/LA

Vee = Max
VIN = GND to Vee

ILO

Output Leakage

-1

/LA

CS = VIH, Vee = Max
VOUT = GND to Vee

VOH

Output High Voltage

2.4

VOL

Output Low Voltage

0.4

IOH

-1.0mA

IOL = 2.1 rnA

*TA = 25'e

DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Test Conditions

VeoR

Voltage for Data Retention

leeOR

Data Retention Current

teoR

Chip Deselect to
Data Retention Time

Operation Recovery Time

Min

. Typ

Max

Units

/LA

2
CS;::;' Vee - 0.2V
VIN ;::;, Vee - 0.2V

0.05
0

tRe

Low Vee Data Retention Waveform
DATA RETENTION MODE

vee

4.SV

VDR >2V

4.SV

~DON'T CARE
240571-3

4-4

5116S/L

Timing Reference Level ..................... 1.5V

A.C. TEST CONDITIONS

Output Load ................ 1 TTL Load

Input Pulse Levels ................... 0.8V to 2.4V

100 pF

Input Rise and Fall Times ................... 10 ns

A.C. CHARACTERISTICS

O·C to 70·C, Vcc

5V ± 10%

READ CYCLE
Symbol

51165·10

Parameter

Min

Max

100

51165·12
Min

Unit

Max

tRC

READ Cycle Time

tAA

Address Access Time

120

tACS

Chip Select Access Time

tOH

Output Hold from
Address Change

tCLZ

Chip Selection to
Output in Low Z

tcHZ

Chip Deselection to
Output in High Z

tOE

Output Enable
Access Time

toLZ

Output Enable to
Output in Low Z

tOHZ

Output Enable to
Output in High Z

100
100

ns
120

120

READ CYCLE NO. 1(1)

1--------

t Rc - - - - - - - - 1

ADDRESS

DATA OUT
240571-4

4-5

intJ

5116S/L

READ CYCLE NO. 2(1,2,4)

ADDRESS

-E ~? }

DATA OUT _________~_",/,I,ljX~X~~=======D=AT=A=VA=L=ID======l=~====

240571-5

READ CYCLE NO.3(1, 3, 4)

DATA OUT
240571-6

NOTES:
1. WE is high for READ Cycle. The first transitioning address.
2. Device is continuously selected; es = VA:.
3. Address valid prior to or coincident with CS transition low.
4. OE = VIL.
5. Transition is measured at ± 500 mV from steady. state voltage.

A.C. CHARACTERISTICS

TA = 0·Cto70·C, Vee = 5V ±10% (Continued)

WRITE CYCLE
Symbol

51165-10

Parameter

Min

51165-12

Max

Min

Unit

Max

twc

WRITE Cycle Time

100 .

120

tew

Chip Selection to
End of Write

tAW

Address Valid to
End of Write

105

tAS

Address Set-Up Time

twp

Write Pulse Width

tWR

Write Recovery Time

tDW

Data Valid to End
of Write

tDH

Data Hold Time

tWHZ

Write Enable to
Output in High Z

tow

Output Active from
End of Write

toHZ

Output Disable to
Output in High Z

10
30

ns
35

10
40

4-6

ns
ns

infef

5116S/L

WRITE CYCLE NO. 1(1)
Iwe
ADDRESS

f---oo

IIIIIIIII/:

IWR(3)

~\\\\\\\\\
lew

\\\ \ \ \ \ \ \ \' \\\\~

(5)

VIIIIIIIII~
lAW

--! lAS
\\\\~

IOHZ{4, 10)

==1

Iwp(2)

DATA OUT

lOW
DATA IN

DATA IN VALID

IOH

:XXXXXXXX
240571-7

WRITE CYCLE NO. 2(1, 6)
Iwe
ADDRESS
lew

\\\\\\'\ ,\\ \\\2

(5)

~ t WR (3)

'1/ 'II I I I II
lAW
t wp(2)

~\\W
lAS
DATA OUT

;:;:j t WHZ{4,lO)

r\C::J ~

DATA IN

I--loH ...tOW{l~

tow------+.I_. IOH:l(9)

----------------i~::======~~~~~IN~V~AL~ID======:tJ~)(~)(~)(~)(
240571-8

NOTES:
1. WE must be high during address transitions.
2. A Write occurs during the overlap (twp) of a low CS and a low WE.
3. All Write Cycle timings are referenced from the last valid address to the first transitioning address.
4. During this period, 1/0 pins are in tri-state.
5. If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in tristate.
6. OE is continuously low (OE = VIU.
7. DOUT is the same phase of write data on this write cycle.
8. DQUJ is the read data of next address.
9. If CS is low during this period, I/O pins are in output state.
10. Transition is measured at ±500 mV from steady state voltage.

4-7

5116S/L

PACKAGE OUTLINE
24-DIP

Normal

5:::f::fB
1

12.1

~t~'1

~ l=!.Jb
o

~~i~

0° .... 150

240571 9

4-8

(j)

13.2±0.25

Shrink

6.35±0.2

31.0±0.3

22.0±0.25

15.24TYP .

7.62TYP.

4.25±0.2

3.45±0.2

5.1 ±0.2

4.2±0.2

P-2.54TYP.

P-1.778TYP.

(lJ

0.5±0.1

0.46+ 0.1

5164S/L
8K x 8-BIT CMOS STATIC RAM
5164S/L-07

5164S/L-10

Units

Address Access Time (tAA)

100

Chip Select Access Time (tAes)

100

Output Enable Access Time (tOE)

Operation
• -Static
No Clock/Refresh Required
Access and Cycle Times
• -Equal
Simplifies System Design
• Single + 5V Supply

Power Down Mode
• TTL
Compatible
• Common
Data Input and Output
• High Reliability
28-Pin 600 Mil PDIP and
• 28-Pin SOP Package
Types

The 5164S/L is a 8192-word by 8-bit CMOS static RAM fabricated using CMOS Silicon Gate process.
The 5164S/L is placed in a standby or reduced power consumption mode by asserting either CS input (CS1,
CS2) false. When in standby mode, the device is deselected and the outputs are in a high impedance state,
independent of the WE input. When device is deselected, standby current is reduced to 100 IJ-A (max). The
device will remain in standby mode until both pins are asserted true again. The device has a data retention
mode that guarantees that data will remain valid at minimum Vee of 2.0V.
Pin Connections

Block Diagram
~vcc

256 x256

~GNO

Memory Array

0,
O2

GNO

240570-2

Pin Names

Ao-A12

240570-1

4-9

Address Input

Do-D7

Data Input/Output

CS1

Chip Select One

CS2

Chip Select Two

Write Enable

Output Enable

Vee

Power

GND

Ground
April 1990
Order Number: 240570-004

5164S/L

earliest transitiion of CS1, high WE or low CS2. Out
Enable (DE) is used for precise control of the outputs.

Device Operation
The 5164S/L has three control inputs: Two Chip Selects (CS1, CS2) and Write Enable (WE). WE is the
data control pin and should be used to gate data at
the I/O pins. A write cycle starts at the lowest transition of CS1, low WE or high CS2 and ends at the

The availability of active high and active low chip
enable pins provides more system design flexibility
than single chip enable devices.

Table 1. Mode Selection Truth Table
CS1

CS2

Mode

I/O

Power

Standby

HighZ

Standby

HighZ

Standby

Write

DIN

Active

Read

DOUT

Active

Read

HighZ

Active

ABSOLUTE MAXIMUM RATINGS

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Voltage on Any Pin
Relative to Ground (VIN, VOUT) ..... -0.3V to 7V
Storage Temperature (TSTG) .... - 55·C' to

+ 150·C

Power Dissipation (Po) .....•............... 1.0W
DC Continuous Output Current (los) ......... 50 rnA

RECOMMENDED OPERATING CONDITIONS
Voltage referenced to Vss, T A = O·C to 70·C
Symbol

Parameter

Min

Typ

Max

Units

Vee

Supply Voltage

4.5

5.0

5.5

VSS

Ground

VIH

Input High Voltage

2.2

VIL

Input Low Voltage

-0.3

Vee

+ 0.3

V
V'

0.8

NOTE:

1. During transitions, the inputs may undershoot to -3.5V for periods less than 20 ns.

CAPACITANCE
Symbol

= 25·C, f =

1.0 MHz

Parameter

CIN1

Input Capacitance (VIN

COUT

Output Capacitance (VOUT

OV)

NOTE:

This parameter is sampled and not 100% tested.

4-10

OV)

Min

Max

Units

intJ

5164S/L

D.C. AND OPERATING CHARACTERISTICS
Recommended Operating Conditions unless otherwise noted

Symbol

Min

Typ'

Max

Units

ICC1

Operating Current

Parameter

CS1 = VIL, CS2 = VIH
1/0 Open, Vcc = Max

ICC2

Dynamic Current

TCYC = Min, Vcc = Max
1/0 Open

CS1 = VIH or CS2 = VIL

0.02

100

p.A

CS1 ~ Vcc - 0.2V
VIN ~ Vec - 0.2V or VIN

ISB

ISB1
Standby
Current
ISB2

sm
L

Test Conditions

< 0.2V

0.02

CS2 ~ Vce - 0.2V

100

p.A

VIN ~ Vce - 0.2V or VIN ~ 0.2V

p.A

Vce = Max
VIN = GND to Vee
CS1 = VIH, CS2 = VIL
VOUT = Ground to Vcc

III

Input Load Current

-1

ILO

Output Leakage

-1

p.A

VOH

Output High Voltage

2.4

IOH =' -1.0 mA

VOL

Output Low Voltage

0.4

IOl = 2.1 mA

'Vcc = 5V, T A = 25'C

DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Min

VeDR

Voltage for Data Retention

IceDR

Data Retention Current

tCDR

Chip Deselect to
Data Retention Time

Opeation Recovery Time

• 'tRC

Typ

Max

Units

Test Conditions

p.A

CS1 ~ Vec - 0.2V
VIN ~ Vcc - 0.2V or VIN ~ 0.2V

p.A

CS2 ~ 0.2V
YiN ~ Vec - 0.2V or VIN ~ 0.2V

tRC"

= Read Cycle Time

4-11

inter

5164S/L

Low Vee Data Retention Waveform
DATA RETENTION MODE

VCC - - - - - - - - - - - - - ,

4.SV - - - - - - - - - - - - - -

Cs 1 C!:VCC -O.2V

cs 1 - - - - -

OV------------------------------------------------

240570-3

DATA RETENTION MODE
VCC-----------~

4.SV - - - - - - '- - - - - -

cs 2 - - - - _
VOR2
O.4V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CS 2 ::SO.2V
OV------------------------------------------------

4-12

240570-4

5164S/L

A.C. TEST CONDITIONS
Input Pulse Levels ................... O.BV to 2.4V
Input Rise and Fall Times .................... 5 ns
Timing Referen,ce Level .................... : 1.5V
Output Load ................ 1 TTL Load

100 pF

A.C. CHARACTERISTICS
= o·c to 70·C, Vcc = 5V ± 10%

READ CYCLE
Symbol

Parameter

5164S/L-07
Min

Max

5164S/L-10
Min

Units

Max

tRC

READ Cycle Time

tAA

Address Access Time

100

tACS

Chip Select Access Time'

100

tOH

Output Hold from
Address Change

tCLZ

Chip Selection to
Output in Low Z'

tCHZ

Chip Deselection to
Output in High Z·

tOE

Output Enable Access Time

tOLZ

Output Enable to
Output in Low Z

toHZ

Output Disable to
Output in High Z

"Timing parameters referenced to both CS1 and CS2.

4-13

100

inter

5164S/L

TIMING DIAGRAMS
READ CYCLE 1(1,2,4)

Address --4
IRC
~
Dala Oul ~----'==J~I~:~~~~I~OH2IM~~~~§l~'xx~*['====Da::J=IV;a;lId;.;IO~H=1=
240570-5

READ CYCLE 2(1,3,4,6)

t !cHI'=!

cs,~
~~(::====:IC::i~i.:~--=c1;,;:==::j,.------......
~

Data Out

Data Valid

240570-6

READ CYCLE 3(1, 4, 7)
Cs 2

--f

{ .

~IcL~~~t.----_~_IcHIZ1
~

Dato Out

=1--

Data Valid

240570-7

READ CYCLE 4(1)

IRC
1M

Address

Z '/L// I I/J /1/.

\.\.\.\\. ,\.\.\.\.\.'-\.\.\''-'k

cs,

\.\.\.\.\.

CSz

11111,

lACS'
IACS2

-IoH-

II 'IIIIII/J /1111

leu,

,\. \. ,\. \.\. \.\.\.\.\ r-,.\. .\.\.

!---ICHIZ(Z,S)-r! - - - I CH1 ,(3) -

leuz
Data Out

Data Valid

240570-8

NOTES:
1. WE is high for READ cycle.
2. Device is continuously selected CS1 = VIL and CS2 = VIH.
3. Address valid prior to or coincident with CS1 transition low.
4. OE = VIL.
S. Transition is measured ± SOO mV from steady state. This paramete~ is sampled and not 100% tested.
6. CS2 is high.
7. CS1 is low.

4-14

inter

5164S/L

A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
Symbol

5164S/L-07

Parameter

Min

5164S/L·10

Max

Min

Units

Max

twe

Write Cycle Time

100

tew

Chip Selection to
End of Write

tAW

Address Valid to
End of Write

tAS

Address Set-Up Time

twp

Write Pulse Width

tWR

Write Recovery Time

tow

Data Valid to End
of Write

tOH

Data Hold Time

tWHZ

Write Enable to
Output in High Z

tow

Output Active from
End of Write

tOHZ

Output Disable to
Output in High Z

WRITE CYCLE 1(1)
twc

Address

tWR1 (3)

,/1111111
tew1 (11)

CS 1

\"-\\~\~\\ --\\\\\\\\,

(5)

~/III

11111111, '11111111

VIIIIIIIII

.\\\\ ,\\\\\\\\\
tew2 (11)
tAW

tWR2 (3)

HtAS

,,\\\
tWHZ (410)

Data Out

Data

\\\~"
tWP (2)

J
~

.1.

In ---------------<(If===]D~ot!O~ln~VO~Ii!d=~:Jtxx~xx~Xgggxg
tow

tOH

240570-9

4-15

inter

5164S/L

WRITE CYCLE 2(1,6)
IWC
Address

cs, ,\.\. \.

\.\.\.\.\.\.\.\.\.\.\.

tWR1 (3)

ICW1 (11)

(5)

'//. '/ / / / / / / / / / / / /

'III. IIIIIIIIIII

(\.\. ,\.\.\.\.\.\.\.\.\.\.\.\.\.\
1cw2(11)
IWR2 (3)

lAW
tWP (2)

\:\.\.\.\.\.\.\.\.\:
- IAS

..!::::::::::1

--!

tWHZ (410)

I--to~.
IoW(10)
(7)

Data Oul
'1

Data In

ID~(9)1

IOW

(8)

DoIa In Valid

I
240570-10

NOTES:
1. WE must be high during address transitions.
2. A write occurs during the overlap (twp) of a low CS, a high es, and a low WE.
3. tWR is measured from the earlier of es or WE gOing high or es going low to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input Signals of opposite phase to the outputs must not be
applied.
5. If the CS low transition or the es high transition occurs simultaneously with the WE low transitions or after the WE
transition, outputs remain in a high impedance state.
6. OE is continuously low (OE = VII)
7. DOUT is the same phase of write data of this write cycle.
8. DQUJ is the read data of next address.
9. If CS is low and CS is high during this period, 1/0 pins are in the output state. Then the data input signals of opposite
phase to the outputs must not be applied to them.
10. Transition is measured ±500 mV from steady state. This parameter is sampled and not 100% tested.
.
11. tow is' measured from the later of es going low or es going high to the end of write.

PACKAGE OUTLINE
28·DIP

---e----+----e--

.....

150

1.465(37.2)
MAX

240570-11

Units = millimeter (mm)

4-16

5164S/L

PACKAGE OUTLINE
28·PIN sOP
28- 0.4:1:0.1

P- 1.27TYP.

-t+-l$1 ~ 0.12 @I
II 1'5

---;:;.--

ci
-It
++1

240442-3

Figure 1. Block Diagram

DEVICE OPERATION

Write Mode

The 51C98 has two control inputs: Chip Select (CS)
and Write Enable (WE). CS is the power control pin
and should be used for device operation. WE is the
data control pin and should be used to gate data at
the liD pins.

Write Cycles may be controlled by either WE or CS.
In either case, both WE and CS must be high (VIH)
during address transitions. During a WE Controlled
write cycle, CS must be held low eVIL! while WE is
low. Address transfers occur on the falling edge of
WE and the data transfers on rising edge of WE.
During a CS controlled cycle, WE must be held low
(Vld while CS is low. The addresses are then transferred on the falling edge of CS and data on the
rising edge of CS. Data, in both cases, must be valid
for a time tow before the controlling input is brought
high (VI H) and remain valid for a time tOH after the
controlling input is high.

Standby Power
The 51C98 is placed in a standby or reduced power
consumption mode by applying ii high (VI H) to the
CS input. When in standby mode, the device is deselected and the outputs are in a high impedance
state, independent of the WE input.
Table 1. Mode Selection Truth Table
CS

Mode

1/0

Power

Standby

High-Z

Standby

Write

DIN

Active

Read

DOUT

Active

Read Mode

cs must be low (Vld

and WE'must be high (VIH) to
activate a read cycle and obtain data at the outputs.
Given stable addresses, valid data is available after
a time tAA.
4-33

51C98

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Voltage on Any Pin Relative
to Ground (VIN. VOUT) ..•...... -1.0V to + 7.0V
Storage Temperature (Ceramic)
(Tstg) .....•............•... - 65°C to + 150°C

• WARNING: Stressing the device beyond the ''Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the ."Operating Conditions"
may affect device reliability.

Power Dissipation (Po) ..................... 1.0W
DC Continuous Output Current (los) ......... 50 mA

RECOMMENDED OPERATING CONDITIONS
Voltage referenced to Vss. TA = O°C to
Symbol

+ 70°C

Parameter

Min

Typ

Max

Units

Vee

Supply Voltage

4.5

5.0

5.5

Vss

Ground

VIH

Input High Voltage

2.2

Input Low Voltage

-0.5

Vil

Vee

O.S

V
V

NOTE:
,
1. During transitions. the inputs may undershoot to - 2.0V for periods less than 20 ns.

CAPACITANCE

TA =

+ 25°C. f =

Symbol

1.0 MHz
Min

Parameter

Max

Units

CIN1

Input Capacitance (VIN = OV)

COUT

Output Capacitance (VOUT = OV)

NOTE:
This parameter is sampled and not 100% tested.

D.C. AND OPERATING CHARACTERISTICS
Recommended Operating Conditions unless otherwise noted
Symbol

Parameter

Max

Units

100

Vee = Max
CS = Vil. Outputs
Open. T cycle = Min

Vee = Min to Max
CS = VIH

-10

p.A

Vee = Max
VIN = GND to Vee

Output Leakage

-10

p.A

CS = VIH. Vee = Max
VOUT = GND to 4.5V

VOH

Output High Voltage

2.4

VOL

Output Low Voltage

Icc

Operating Current .

ISB

Standby Current

III

Input Load Current

tlO

Min

0.4

4-34

Test Conditions

tOH =-4mA

tOl = SmA

infef

51C98

DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol

Parameter

VeDR

Voltage for Data
Retention

leCDR

Data Retention
Current

teDR

Chip Deselect to
Data Retention
Time

Operation Recovery
Time

Min

.Typ

Max

Test Conditions

Units

V
95
350

500
750

tRe

CS :;:: Vee - 0.2V
VIN:;:: Vee - 0.2V
or::; 0.2V

}J-A
/LA

Vee
Vee

= 2V
= 3V

Low Vee Data Retention Waveform

Vee

DATA RETENTION MODE

-:.SV

teOR

VOR >2V

4.S~

tR
~.~~.~~

VORo/#&

DON'T CARE
240442-4

A.C. TEST CONDITIONS
Input Pulse Levels ................... GND to 3.0V
Input Rise and Fall Times ...... '.............. 5 ns
Timing Reference Level ........... '.......... 1.5V
Output Load ..................... See Figures 2, 3

167.11

167.11
DOUT~I.73V

DOUT~I.73V

~5PF

~30PF
240442-5

240442-6

Figure 2. Output Load

Figure 3. Output Load for tHZ. tLZ. twz. tow

4-35

intJ

51C98

A.C. CHARACTERISTrcs
= o·c to +70·C, Vcc = 5V ± 10%

READ CYCLE

Symbol

51C98·20

Parameter

Min

Max

51C98-25

Min

Max

51C98-30

Min

Units

.Max

tRC

READ Cycle Time

tAA

Address Access Time

tACS

Chip Select Access Time

tOH

Output Hold from
Address Change

tlZ

Chip Selection to
Output in Low-Z

tHZ

Chip Deselection to
Output in High-Z

tpu

Chip Selection to
Power Up Time

tPD

Chip Deselection to
Power Down Time

15
0

0
20

20
0

ns
ns

NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage. tHz(Max) is less than tLz(Min). both for a given device and from device to device.
3. Transition is measured at ± 500 mV from steady state voltage with specified loading in Figure 3.

READ CYCLE NO. 1<1,2)
t Rc
ADDRESS
tAA
- tOH DATA OUT

PREVIOUS DATA VALID

DATA VALID
240442-7

4-36

51C98

READ CYCLE NO. 2(1,3)
1---------tRc-------------I

DATA OUT

~fil,PLY

f {) "

_ t LZ

tACS

-1~H~IG~H~IM~P~ED~A~NC!E__~i[1<~V*=:::::::!~~~::~::::*,~H~IG~Har1\\
DATA VALID
IMPEDANCE

ICC --

_r:-:. !ll..~

CURRENT ISS

~ tPD:l

r--

. 50%

240442-8

NOTES:
1. WE is high for Read Cycles.
2. Device is continuously selected. CS = VIL.
3. Addresses valid prior to or coincident with CS transition low.

A.C. CHARACTERISTICS (Continued)
WRITE CYCLE

Symbol

Parameter

51C98-20

Min

51C98-25

Max

Min

Max

51C98-30

Min

Units

Max

twc

Write Cycle Time(1)

tew

Chip Selection to
End of Write

tAW

Address Valid to
End of Write

tAS

Address Set-Up Time

twp

Write Pulse Width

tDW

Data Valid to End
of Write

tDH

Data Hold Time

twz

Write Enable to
Output in High-Z(2)

tow

Output Active from
End of Write(2)

tWR

_Write Recovery Time

0
0

4-37

0
0

ns
ns

inter

51C98

WRITE CYCLE NO. 1 (WE CONTROLLED)(3)

~----------------~c----------------~

~-----------t~------------~

cs ~m~1

1n"7"'J"'l"lr-rrm"'J"'l"lr-rr""-'"'J"'l"lr-rr'1"l

DATA IN

DATA IN VALID
______________~------'I~------~-JI'---------------

-+~_to_w_1-1""'-------

DATA OUT ----DA-l:-A-UN-D-m-N-E-D-I---t-.WZ-]......:.:HI;;:GH::..::;:IM;.:PE;:;DA;,;:N;;;C:.E

240442-9

NOTES:
1. All Write Cycle timings are referenced from the last valid address to the first transitioning address.
2. Transition is measured at + 500 mV from steady state voltage with specified loading in Figure 3.
3. CS or WE must be high during address transitions.

WRITE CYCLE NO.2 (CS' CONTROLLED)(1, 2)
twc
ADDRESS

:-tAS

tAW

~twR-

twp

r///////////////////////~

0.\\\\\\\\~

tow

DATA IN

~~OUT

______________

DATA INVALID

~HI;;:GH::..::;:IM;.:PE;:;DA;,;:N;;;C:.E

/OH
X
_ _ _ _ _ _ _ _ __
240442'"10

NOTES:
1. CS or WE must be high during address transitions.
,
2. If CS switches low coincident with or after WE switches low. the outputs will stay in a high impedance state. If CS
switches high or coincident with or after WE switches high, the outputs will stay in a high impedance state.

4-38

5164
HIGH SPEED 8192 x 8-BIT STATIC RAM
5164-20

5164-25

5164-30

5164-35

20
120
30

25
110
30

30
100
30

35
100
30

Max Access Time (ns)
Max Active Current (rnA)
Max Standby Current (rnA)

•
•

Static Operation
- No Clock/Refresh Required

•

Single

•

•
•
•
•

Equal Access and Cycle Times
- Simplifies System Design

+ 5V Supply

Power Down Mode
TTL Compatible
Common Data Input and Output
28-Pin 300 Mil Plastic Package

2V Data Retention Option Available

The 5164 is a 65,536-bit high speed static RAM configured as 8K x 8. Easy memory expansion is available with
two chip enables (CS1 and CS2) and an Output Enable (OE).
The power down feature contributes greatly to system reliability. The device's power consumption is reduced
when in this low power standby mode. In fact, 85% system power reduction is achievable in large systems
where a majority of the devices are deselected.

Functional Block Diagram

•
256 x 256
MEMORY ARRAY

Pin Configurations

COLUMN I/O

C~~~~~L

1-------------.....- . .
240674-1

240674-2

Pin Names
Ao-A12

Address

II01-IIOS

Data Input/Output

Write Enable
Output Enable

CS1

Chip Select

GND

Ground

CS2

Chip Select

Vee

Power

4-39

May 1990
Order Number: 240674-002

inter

5164

Device Operation.

Standby Power

The 5164 has three control inputs: Two Chip Selects
(CSt, CS2) and Write Enable (WE). WE is the data
control pin and should be used to gate data at the
1/0 pins. When CS1 and WE inputs are LOW and
CS2 is HIGH, data is written into the memory and
reading is accomplished when g§1 and OE are active LOW, CS2 aCtive HIGH and WE remains inactive
or HIGH.

The 5164 is placed in a standby or reduced power
consumption mode by applying a high (VI H) to the
CS1 input or low (VILl to the· CS2 input. When in
standby mode, the device is deselected and the outputs are in a high impedance state, independent of
the WE input.

Table 1. Mode Selection Truth Table
CS1

CS2

L
L
L

Mode

I/O

Power

Standby

HighZ

Standby

HighZ

Standby

Write

DIN

Active

Read

DOUT

Active

Read

HighZ

Active

ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin
Relative to Ground (VIN, VOUT) ... -1.0V to

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

+ 7V

Storage Temperature
(Ceramic) (TSTG) ............ - 65°C to + 150°C
Power Dissipation (Po) ..................... LOW

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended. exposure beyond the "Operating Conditions"
may affect device reliability.

DC Continuous Output Current (los) ......... 50 mA

RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T A = O°C to 70°C)
Symbol

Parameter

Min

Typ

Max

Unit

Vee

Supply Voltage

4.5

5.0

5.5

Vss

Ground

VIH

Input High Voltage

2.2

VIL

Input Low Voltage

-0.5

Vee

+ 0.5

0.8

NOTE:

1. During transitions, the inputs may undershoot to -2.0V for perio.ds less than 20 ns.

CAPACITANCE

(TA

= 25°C, f = 1.0 MHz)

Symbol

Parameter

CIN1

= OV)
Output Capacitance (VOUT = OV)

COUT

Min

Input Capacitance (VIN

NOTE:

This parameter is sampled and not 100% tested.
4-40

Max

Unit·

5164

D.C. AND OPERATING CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Parameter

Symbol

Min

Max

Units

Test Cc;mditions

lee

Operating Current

100

Vee = Max, CS1 = VIL
CS2 = VIH, Outputs Open,
TeyeLE = Min

ISB

Standby Current

Vee
CS1

CS1 2 Vee - 0.2V,
VIN 2 Vee - 0.2Vor
VIN ~ 0.2V, Vee = Max

ISB1

=
=

Min to Max
VIH or CS2 = VIL

III

Input Load. Current

-10

p.A

Vee = Max
VIN = GND to Vee

ILO

Output Leakage

-10

p.A

CS1 = VIH, Vee = Max
VOUT =: GND to Vee

VOH

Output High Voltage

2.4

VOL

Output Low Voltage

0.4

IOH

IOL

= -4mA
= 8 mA

DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Min

VeDR

Voltage for Data Retention

leCOR

Data Retention Current

teDR

Chip Deselect to
Data Retention Time

Operation Recovery Time

Low

Typ

Max

Units

Test Conditions

500

p.A

Vee

350

750

/LA

Vee

tRe

= 2V
= 3V

CS1 2 Vee - 0.2V
VIN 2 Vee - 0.2V
or ~ 0.2V

Vee Data Retention Waveform
DATA RETENTION MODE

Vee

240674-3

4-41

inter

5164

A.C. TEST CONDITIONS
Input Pulse Levels ................... GND to 3.0V
Input Rise and Fall Times .........•.......... 5 ns
Timing Reference Level ..................... 1.5V

A.C. CHARACTERISTICS

(TA

O'Cto 70'C, Vcc

5V ±10%)

READ CYCLE
Symbol.
tRC

Parameter

5164-20
Min

Read Cycle Time

Max

5164-25
Min

Max

5164-30
Min

Max

5164-35
Min

Unit

Max

tAA

Address Access Time

tACS1

Chip Select 1
Access Time

tACS2

Chip Select 2
Access Time

tOE

Output Enable to
Output Valid

tOH

Output Hold from
Address Change

tCLZ1

Chip Select 1 to
Output in Low Z

tcLZ2

Chip Select 2 to
Output in Low Z

ns'

tcHZ1

Chip Select 1 to
Output in High Z

tCHZ2

Chip Select 2 to
Output in High Z

toLZ

Output Enable to
Output in Low Z

tOHZ

Output Enable to
Output in High Z

tpu

Chip Selection to
Power Up Time

tpD

Chip Deselection to
Power Down Time

0
10

ns
20'

0
30

ns
ns

NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage, tcHZ(Max) is less than tcLZ(Min), both for a given device and from device to
device.

4-42

5164

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

ADDRESS

=f
-

IRC

' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.......

~-------IM-----___1

t------IOE - - - _ _ _ 1

t - - - - IoLz(S) - - - - - I

~~...,II------

CS 2 .....

I ACS2 - - - - j - - j

1 - - - - ICLZ2(S) - - - - I

240674-4

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

240674-5

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

DATAOUT

CURRENT

--..!::==t=7.~T--~~~[:::t=l:j

ISS

---Ir----------t--~,

--------.11

ICC • - - - - - - -

- - -

IpO

240674-6

NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS1 =
CS2 = VIH.
3. Address valid prior to or coincident with CS1 transition low and CS2 transition high.
4. OE = VIL
5. Transition is measured ± 500 mV from steady state.

.'!!!..

4-43

inter

5164

A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
Symbol

Parameter

5164-20

Min

Max

5164·25

Min

Max

5164-30

Min

Max

5164-35

Min

Units

Max

twc

Write Cycle Time

tCW1

Chip Selection 1 to
End of Write

tCW2

Chip Selection 2 to
End of Write

tAW

Address Valid to
End of Write

tAS

Address Set-Up Time

twp

Write Pulse Width ,

tWR

Write Recovery Time

tow

Data Valid to
End of Write

tOH

Data Hold Time

tWHZ

Write Enable to
Output in High Z

tow

Output Active from
End of Write

0
0

4-44

0
0

ns
ns

inter

5164

TIMING WAVEFORM OF WRITE CYCLE NO. 1(1)
1 - - - - - - - - twc - - - - - - - 0 0 1
ADDRESS

CS 2

DATAOUT

240674-7

TIMING WAVEFORM OF WRITE CYCLE NO. 2{1,6)

1 - - - - - - - - twc

-------1

ADDRESS

CS 2

CS 1

DATAOUT

VALIDXXXXX

240674-8

NOTES:
1. WE must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CSI and a high CS2.
3. tWR1,2 is measured from the earlier of CSI or WE going high or CS2 gOing low to the end of write cycle.
4. During this period, 1/0 pins are in the output state so that the input signals must not be applied.
5. If the CS 1 low transition or CS2 high transition occurs simultaneously with the WE low transitions or after the WE tran·
sition, outputs remain in a high impedance state.
6. OE is continuously low (OE = VII).
7. DATAOUT is the same phase of write data of this write cycle, as long as address does not change.
B. If CSI is low and CS2 is high during this period, 1/0 pins are in the output state. Data input signals must not be applied.
9. Transition is measured ± 200 mV from steady state.

4-45

inter

5164

28-PIN PLASTIC DIP
1

1.46 (37.08)
1.44 (36.57)

~.J::::::::::::] ~~:
o

0.330(8.26)
0.315(7.87)

SEATING PLANE

o::;:~::~~
~

,
0.062 158
0.050 1:27

~ 'J
'

0.1704.32
0.155 3.93

0.140 3.56

L__

II
II....

g:g~~ g:~~ ---r

0.120 3.05

~-T
1-

--l

0.380 9.65)
0.350 8.69

0.0140.36
0.008 0.20

I
I-

0.10~.54)

1------

1.300 (33.02)

TYP.

-----~
240674-9

4-46

51256

HIGH SPEED 32K x 8-BIT STATIC RAM
51256·20
Max Access Time (ns)

51256·25

51256·30

51256·35

Max. Active Current (rnA)

100

Max Standby Current (rnA)

Operation
• -Static
No Clock/Refresh required
Access and Cycle Times
• -Equal
Simplifies System Design
• Single + 5V Supply

2V Data Retention Option Available
• Power
Down Mode
• TTL compatible
• Common Data Input and Output
• .28·Pin 300 Mil Plastic PDIP Package.
•

The 51256 is a 32,76B-word by B-bit high speed static RAM fabricated using a CMOS silicon gate process.
Easy memory expansion is provided by an active low Chip Select (CS) and an active low Output Enable. (OE).
The power down feature contributes greatly to system reliability. The device's power consumption is reduced
when in this low power standby mode.

Pin Connections

Functional Block Diagram
+-0 vee
ROW
DECODER

+-OGND

1024x 256
Memory Array

240801-2

Pin Names
Ao-A14 ADDRESS

.............

cs"'-----.l~

~--------------------~~

WE ..,.--01.-_--'

240801-1

4-47

0 0- 0 7

DATAINPUT/OUTPUT

CHIP SELECT

WRITE ENABLE

OUTPUT ENABLE

Vee

POWER

GND

GROUND

August 1990
Order Number: 240801-001

inter

51,256

Table 1. Mode Selection Truth Table

DEVICE OPERATION
The 51256 has two control inputs: Chip Select (CS)
and Write Enable (WE). WE is the data control pin to
be used to gate data at the 1/0 pins. When CS and
WE inputs are LOW, data is written into the memory
and reading is accomplished when CS and OE are
active LOW while Write Enable (WE) remains inac·
tive or HIGH.
.

STANDBY POWER
The 51256 is placed in a standby or reduced power
consumption mode by applying a high (VIH) to the
CS input. When in standby mode, the device is deselected and outputs are in a high impedance state,
independent of the WE input.

4-48

Mode

I/O

Power

Standby

HighZ

Standby

Write

Din

Active

Read

Dout

Active

Read

HighZ

Active

intJ

51256

ABSOLUTE MAXIMUM RATINGS
PARAMETER

SYMBOL

VALUE

UNITS

Vin, Vout

-1.0to +7V

Voltage on any pin relative to Ground

Tstg

-65 to + 150

°C

Power Dissipation

1.0

DC Continuous Output Current

los

rnA

Storage Temperature (Ceramic)

NOTICE: This is a production data sheet. The specifications are subject to change without notice .

• WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device reliability.

RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T A = O°C to 70°C)

Parameter

Symbol

Min

Typ

Max

Units

Vee

4.5

5.0

5.5

Vee + 0.5

0.8

Supply Voltage

. Vss

Ground
Input High Voltage

VIH

2.2

Input Low Voltage

VIL

-0.5

NOTE:

During transitions, the inputs may undershoot to - 2.0V for periods less than 20ns.

CAPACITANCE

(TA

25°C, f

1.0 MHz)

Parameter
Input Capacitance (VIN

Symbol

OV)

Output Capacitance (VOUT

OV)

Max

Units

CIN

COUT

NOTE:

This parameter is sampled and not 100% tested.

4-49

Min

inter

51256

D.C. AND OPERATING CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)

Max

Units

Test Conditions

Operating Current

lee

100

Vee = Max., CS s VIL
outputs open, Tcycle = Min.

Standby Power

ISB

Vee

ISB1

CS:<: Vee-0.2V,
VIN:<: Vee-0.2V or
VIN s 0.2V, Vee = Max

Parameter.

Symbol

Supply Current

Min

Max, CS :<: VIH

Input Load Current

III

-10

p.A

Vee = Max
OV s VIN s Vee

Output Leakage

ILO

-10

p.A

CS = VIH, Vee = Max
OV s VOUT s Vee

Output High Voltage

VOH

2.4

Output Low Voltage

VOL

0.4

IOH

IOL

= -4.0mA
= 8.0mA

DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol

Parameter

VeDA

Voltage for Data Retention

leeDA

Data Retention Current

teDA

Chip Deselect to Data
Retention Time

Operation Recovery Time

Test Conditions

Min

Typ

Max

V
95

CS :<: (Vee - 0.2 V)
VIN :<: (Vee - 0.2 V)·
or s 0.2V (Vee = 2V)

0
tAe

p.A

ns
ns

LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE

vcc

240801-3

4-50

Units

inter

51256

A.C. TEST QUESTIONS
Input Pulse Levels ................... GND to 3.0V
Input Rise and Fall Times .................... 5 ns
Timing Reference Level ..................... 1.5V

A.C. CHARACTERISTICS
(TA = 0° to 70°C, VCC = 5V ± 10%)
READ CYCLE
Symbol

Parameter

51256-25

51256-30

51256-35

51256-45

Min

Max

Units

Max

tRC

Read Cycle Time

tAA

Address Access Time

tACS

Chip Select Access Time

tOE

Output Enable to Output Valid

tOH

Output Hold from Address Change

tClZ

Chip Select to Output in Low Z

tCHZ

Chip Deselect to Output in High Z

tOll

Output Enable to Output in Low Z

tpu

Chip Selection to Power Up Time

tpD

Chip Deselection to Power Down Time

15
0

0
35

0
30

ns
45

20
0

0
25

NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage, teHZ (Max) is less than telZ (Min), both for a given device and from device to
device.

4-51

inter

51256

-------=i tAA

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

ADDRESS

--------1

tRC

_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

~------

------.!.'

---+----

DATAOUT
240801-4

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)

-=Jk
~
- ~I +-I+-.:===-tOH -tAA-bk

~-tOH-l---

DATAOUT
240801-5

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)

DATAOUT
240801-6

NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = Vlk
3. Address valid prior to or coincident with CS transition low.
4.

= VIL

5. Transition is measured ± 200 mV from steady state with 5 pF load (including scope and jig). '

4-52

inter

51256

A.C. CHARACTERISTICS

(Continued)

WRITE CYCLE
Symbol

Parameter

51256·25
Min

Max

51256-30
Min

Max

51256-35
Min

Max

51256-45
Min

Units

Max

twe

Write Cycle Time

tew

Chip Select To End of Write

tAW

Address Valid to End of Write

tAS

Address Set-up Time

twp

Write Pulse Width

tWR

Write Recovery Time

tow

Data Valid to End of Write

tOH

Data Hold Time

tWHZ

Write Enable to Output in High Z

tow

Output Active from End of Write

0
5

4-53

0
5

ns
ns

inter

51256

TIMING WAVEFORM OF WRITE CYCLE NO.1,
(WE CONTROLLED TIMING)(1, 2, 3, 5, 7)
twc

ADDRESS

:)K:

X
~ t cHZ(6)

----

tAW

I\..
I--

~~
t wp (7)

tAS
.."

DATAOUT

(4)

tWR

~V'

'_tWHZ(6)~
"

_tOW-i

_tow _

tOH _

....

240801-7

TIMING WAVEFORM OF WRITE CYCLE NO.2,
(WE CONTROLLED TIMING)(1, 2, 3, 5)
twc

ADDRESS

)(
tAW

t AS

}

t cW(7)

tWR

I-- tow _
/

tOH _

240801-8

NOTES:
1. WE must be high during all address transitions.
2. A write occurs during the overlap (~or twe). of a low CS and low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in the high impedance state.
6. Transition is measured ± 200 mV from steady state with a 5 pF load (including scope and 'jig).
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or:..fuyz + tow) to allow the
I/O drivers to ,turn off and data to be placed on the bus for the required tow. If OE is high during a WE controlled write cycle,
this requirement does not apply and the write pulse can be as short as the specified twP.

4-54

inter

51256

PACKAGE DIMENSIONS

2lI-I'In Plastic Dip

•

1.46 (37.08)

1.47 (36.57)

L-

SEATING PLANE

y--- l:rO=TI:;:nTrr;::;:~:;:;:;::;:;:::;::::J
"0.~17~0~~
0'135(3'43)~~-t----L-

0.155 (3.94)

,.~ (..,.,:JIl J l
0.050 (1.27)

II
-II- 0.021
(0.53
0.018 (0.41

~~;"
I

0.325 (8.26)

0.31.~~:.87)

R. ,. ",.",

0.008 (0.20)

0.380 9.65)
0.350 8.69

0~gO(2.54)

1.300J~3.02) _ _ _ _ _-1

All dimensions In Inches (millimeters)

Uax.

Min.

240801-9

4-55

51258
HIGH SPEED 64k x 4-BIT STATIC RAM
51258-20

Max Access Time (ns)
Max Active Current(mA)
Max Standby Current (rnA)

•
•
•

51258-25

51258-35

100

•
•
•
•
•

Static Operation
- No Clock/Refresh required
Equal Access and Cycle Times
- Simplifies System Design

+ 5V Supply

Single

51258-30

2V Data Retention Option Available
Power Down Mode
TTL compatible
Common Data Input and Output
24-Pin 300 Mil Plastic PDIP Package

The 51258 is a 65,536-word by 4 bit high speed static RAM fabricated using a CMOS silicon gate process:
Easy memory expansion is provided by an active low Chip Select (CS).
The power down feature contributes greatly to system reliability.
when in this low power standby mode.

Th~

device's power consumption is reduced

Pin Configuration
DIP/SOle

Functional Block Diagram

AODRESSES {

262.144-BIT

MEMORY ARRAY

A,s----I

1/0,--......-1

240802-1

Top View
Pin Names
Ao-A15

Addresses

1/01-1/04

Data Input/Output

Chip Select

Write Enable

GND

Ground

Vee

Power

240802-2

4-56

August 1990
Order Number: 240802-001

inter

51258

Table 1. Mode Selection Truth Table

DEVICE OPERATION
The 51258 has two control inputs: Chip Select (CS)
and Write Enable (WE). WE is the data control pin to
be used to gate data at the 1/0 pins. When CS and
WE inputs are LOW, data is written into the memory
and reading is accomplished when CS goes active
LOW while Write Enable (WE) remains inactive or
HIGH.

Mode

1/0

Standby

HighZ

Standby

Write

Din

Active

Read

Dout

Active

H
L
L

Power

STANDBY POWER
The 51258 is placed in a standby or reduced power
consumption mode by applying a high (VIH) to the
CS input. When in standby mode, the device is deselected and outputs are in a high impedance state,
independent of the WE input.

ABSOLUTE MAXIMUM RATINGS*
Symbol

Parameter

Value

Units

-1.0to +7V

Tstg

Storage Temperature -65 to +150
(Ceramic)

°C

Power Dissipation

1.0

los

D.C. Continuous
Output Current

rnA

Yin, Vout Voltage on any pin
relative to Ground

RECOMMENDED OPERATING CONDITIONS
= O°C to 70°C)

(Voltage referenced to Vss, T a

Parameter

Min

Typ

Max

Units

Vee

Supply Voltage

4.5

5.0

5.5

Vss

Ground

VIH

Input High Voltage

2.2

Vee+ 0.5V

VIL

Input Low Voltage

-0.5

0.8

Symbol

NOTE:
During transitions, the inputs may undershoot to - 2.0V for periods less than 20 ns.

4-57

inter

51258

CAPACITANCE

(TA

25°C, f

Symbol

1.0 MHz)

Parameter

Min

CIN

Input Capacitance (VIN

GOUT

Output Capacitance (VOUT

OV)

Max

Units

8pF

NOTE:
This parameter is sampled and not 100% tested.

D.C. AND OPERATING CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)

Symbol

Parameter

Min

Max

Units

Test Conditions

100

Vee = Max., CS s VIL
Outputs Open, T Cycle = min.

Standby Power

Vee

ISB1

Supply Current

CS ~ Vee-0.2V,
VIN ~ Vee-0.2V or
VIN s 0.2V, Vcc=Max

III

Input Load Current

-10

/LA

Vee = Max
OV s VIN s Vee

ILO

Output Leakage

-10

/LA

CS = VIH, Vee = Max
OV s VOUT s Vcc

VOH

Output High Voltage

2.4

IOH = -4.0mA

VOL

Output Low Voltage

0.4

IOL = 8.0mA

Icc

Operating Current

ISB

4-58

= Max, CS

~ VIH

51258

DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol

Parameter

VCDR

Voltage for Data Retention

ICCDR

Data Retention Current

tCDR

Chip Deselect to
Data Retention Time

Operation Recovery Time

Test Conditions

Min

CS ~ (VCC - 0.2 V)
VIN ~ (VCC - 0.2 V)
or ~ 0.2V
(VCC = 2V)

Typ

Max

500

}J-A

Units

tRC

LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE

240802-3

A.C. TEST QUESTIONS
Input Pulse Levels ....••............. GND to 3.0V
Input Rise and Fall Times .••......•.......... 5 ns
Timing Reference Level ..................... 1.5V

A.C. CHARACTERISTICS (TA = 0°0 to 70 0C. Vcc
0

5V ± 10%)

READ CYCLE
Symbol

Parameter

tRC

Read Cycle Time

tAA

Address Access Time

51258-20

51258-25

Min

Max

20
20

tACS

Chip Select Access Time

tOH

Output Hold from Address Change

tCLZ

Chip Select to Output in Low Z

tCHZ

Chip Deselect to Output in High Z

tpu

Chip Selection to Power Up Time

tpD

Chip Deselection to Power Down Time

Max

30
5

0
25

ns
ns

5
20

ns
35

ns
20

ns
ns

0
30

Units

Max

35
30

Max

51258-35
Min

51258-30
Min

NOTES:

1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage. tCHZ (Max) is less than tClZ (Min). both for a given device and from device to

device.

4-59

intJ

51258

TIMING WAVEFORM OF READ CYCLE NO. 1(1)

""'"

~j.

_____ lu

1 + - - - - - tACS
t CLZ (4)

----%.-1•~t-OH------

---,-,

--+-----+/

DATAOUT
240802-4

TIMING WAVEFORM OF READ CYCLE NO. 2(1,2)

-=Jk
-.

~:=t

-fl

===-tOH _tAA

~
~-tOH-l---

DATAOUT
240802-5

TIMING WAVEFORM OF READ CYCLE NO. 3(1,3)

DATAOUT
240802-6

NOTES:
1. WE is high for read cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ± 200 mV from steady state with 5 pF load (including scope and jig).

4-60

inter

51258

A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
Symbol

51258-20

Parameter

Min

51258-30

51258·25

Max

Min

Max

Min

51258-35

Max

Min

Units

Max

twc

Write Cycle Time

lew

Chip Select to
End of Write

tAW

Address Valid to
End of Write

tAS

Address Set-up Time

twp

Write Pulse Width

tWR

Write Recovery Time

tDW

Data Valid to
End of Write

a
a

tDH

Data Hold Time

tWHZ

Write Enable to
Output in High Z

tow

Output Active from
End of Write

a
a

TIMING WAVEFORM OF WRITE CYCLE NO.1
(WE CONTROLLED TIMING)(1, 2, 3, 6)
twc
ADDRESS

~'"

)K:
tAW

)1'

OATA OUT

DATAIN

,
"

tWR
........:;.;.:.

twp

- - tAS

''"

__ tWHZ(6)~

(4)

tow

----i,
I'

(4)

------------ICR"""------9. ----tow

-00

__ tOH

240802-7

4-61

51258

TIMING WAVEFORM OF WRITE CYCLE NO.2,
(CS CONTROLLED TIMING)(1, 2, 3, 5)
twc
ADDRESS

:)V'

V'
tAW

_tAS

)

tWR

--::.::....

tcw
~

tDW _

DATAIN

tDH

----------.....(~----- ~lI-----...

240802-8

NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (ICW or twP) of a low CS and low WE.
3. twR is measured from the earlier of CS or WE going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in the high impedance state.
6. Transition is measured ± 200 mV from steady state with 5 pF load (including scope 'and jig).

PACKAGE DIMENSIONS
1.250 (51.75)
1.230 (31.24)

[~~~~~~~~~~]~~:
~J
"._=;
0.145(3.68)
0.135 (3.43)

r-0.062 (1.57)
0.050 (1.27)

~ ~

L
I

0.170(4.32)
0.155 (3.94)

0.140 (3.56)
0.1202.05)

0.021 (0.53)
0.018 (0.41)

-r

0.325 (8.26)
0.310 (7.87)

Ir-

IIS\--\-I .... ,...,
0.008 (0.20)

...,

0.380 (9.65)
0.330 (8.38)

0.100 (2.54)

TYP
1.100 (27.94) - - - - + (

TYP
All dimension. In Inche. (millimeters)

~~~.
240802-9

24-Pln Plastic Dip

4-62

RR-63

RELIABILITY
REPORT

August 1989

. Static RAM
Reliability Report

MADHU NIMGAONKAR
COMPONENTS CONTRACTING DIVISION
QUALITY AND RELIABILITY. ENGINEERING

Order Number: 240544-001
4-63

SRAM RELIABILITY DATA
SUMMARY

CONTENTS

PAGE

1.0 INTRODUCTION ...... : ............. 4-65
2.0 RELIABILITY TESTS ............... 4-65
High Temperature Burn-In ............... 4-65
High Temperature Dynamic Lifetest ...... 4-65
High Voltage (7V) Dynamic Lifetest ...... 4-65
High Temperature Reverse Bias Test .... 4-65
Low Temperature Lifetest ............... 4-65
High Temperature Storage Test ......... 4-66
Temperature Cycle Test ................. 4-66
3.0 RELIABILITY DATA SUMMARy .... 4-66

51C68 .................................. 4-66
51C98 .................................. 4-67
APPENDIX A ........................... 4-71
Common MOS Failure Mechanisms ...... 4-71
Oxide Defects ............................ 4-71
Silicon Defects .......................... 4-71
Contamination .......................... 4-71
Metallization Defects .................... 4-71

4-64

intJ

RR-63

1.0 INTRODUCTION
This report summarizes the ~eliability predictions of the
MOS memory components and the methodology used
in making the predictions. The methodology adopted
by Intel is among the most conservative in the electronics industry. The reader should be aware of the different methodologies used by various manufacturers in
making the reliability predictions and the profound effect a more liberal approach has on the failure rate reported.

'I
107

106

::..1

J/~7
<:>

'"0

105

::t:
I

..,
:>
'"

2.0 RELIABILITY TESTS

...I

I I

104

High Temperature Burn-In

..,e

This test is used to establish infant mortality failure
rates. Intel defines infant mortality as the early life failures observed after a 48 hour 125°C dynamic burn-in.
In order to eliminate infant mortality fallout in determining long term failure rates, all devices used for lifetesting are subjected to standard Intel production
screens plus a 48 burn-in.

;::

:::E

JII

103

o·
7

102

JII

~~Z

/ 1/ ./

10~
7
5
3

High Temperature Dynamic Lifetest

V ~ '/ V1/ /./.

If) V

250200175150125100 75 50 25

This test is performed to accelerate failure mechanisms
that are thermally activated through the application of
extreme temperatures (125°C) and the use of biased operating conditions (5.5V). The translation from 125°C
to 55°C is done by applying time acceleration factors
based on the thermal activation energy assignments.

TEMPERATURE (Oc)

240544-1

Figure 1. Arrhenius Plot

High Voltage (7V) Dynamic Lifetest

Failure rate calculations are given for each relevant activation energy. These are made using the appropriate
activation energy and the Arrhenius Plot as shown in
Figure 1. The total equivalent device hours at a given
temperature can be determined. The failure rate is then
calculated by dividing the number of failures by the
equivalent device hours and is expressed as a %/1000
hours. The failure rate is adjusted by a factor related to
the number of device hours using a chi-square distribution to arrive at a confidence level associated failure
.rate. A conservative estimate of the failure rate is obtained by including zero failures at 0.3 eV, 0.5 eVand
1.0 eV. In cases where the mechanism of the catastrophic failures cannot be determined, 0.3 eV activation energy is assumed.

This test is used to detect failure mechanisms which are
accelerated by high voltage as well as high temperature.
It is especially effective in accelerating oxide and leakage related failures. The total acceleration factor includes the time acceleration factors based on the assigned activation energies and voltage acceleration factor (7V to 5.5V).

High Temperature Reverse Bias Test
This test is used to detect failure mechanisms which are
accelerated by high temperature (1500C). This test is
effective in accelerating leakage related failures and
drifts in device parameters due to process instability.

When reviewing failure rate projections from ditTe~ent
sources, it is important to understand the assumptions
being made. Small changes in details can dramatically
alter an estimated failure rate.

Low Temperature Lifetest
This test is performed at maximum operating frequency
to detect the effects of electron injection into the gate
oxide. The conditions for electron injection occur during transitions when the transistors are in saturation.
4-65

inter

RR-63

High Temperature Storage Test

Temperature Cycle Test

High temperature storage (bake) is a test in which devices are subjected to elevated temperatures (1SO"C for
plastic packages and 2SO"C for hermetic packages) with
no applied bias. This test is used to detect mechanical
reliability problems (e.g., bond integrity) and process
instability.

This test consists of cycling the temperature of a chamber housing device from -6S'C to + 1SO"C with no
applied bias. Temperature cycling (1000 cycles) is used
to detect mechanical reliability problems and microcracks.

,3.0 RELIABIL{TY DATA SUMMARY

51C68
Number of bits: 16,384
Organization:
4K x 4

Process: CHMOS III
Package: 20-Pin
Table 1. Failure Rate Predictions

Actual
Device Hours
12S'C

+ 06,
+ O~
3.B5E + 06

Ea
(eV)

Equivalent Hours

Fall
SS'C

3.B5E

0.3

2.00E

3.B5E

0.5

6.01E

1.0

9.40E

70'C

+ 07
+ 07
+ OB

+ 07
+ 07
2.42E + OB

SS'C

70"C

1.33E

0.0101

0.0152

3.05E

0.0015

0.0032

0.0001

0.0002

0.0117
117

0.01B6
186

Combined Failure Rate: .
FITs:
NOTE:
FIT = Failures in Time. 1 FIT = 1 failure per 10E

Fall Rate %/1K Hours
(60% UCL)

+ 09 device hours.

Table 2. Reliability Summary
Month

12S'C DynamiC Llfetest

Package
48 Hrs

168 Hrs

500 Hrs

1KHrs

2KHrs

1/B6 •

Cerdip

1/1061

0/1034

0/600

3/B6 •
3/B6 ••

Plastic

0/1536

0/1531

0/579

1/579

Plastic

0/150

5/B6

Cerdip

0/1000

0/150

6/B6

Cerdip

0/B79

0/B6B

0/150

9/B6

Cerdip

1/1125

0/1123

0/150

5/87

Cerdip

01743

0/150

7IB7

Cerdip

0/1000

0/150

7/B7

Cerdip

01769

0/200

7IB7

Cerdip

2/675

0/673

0/200

4/B93B
(A)

0/8891

0/2479

0/2464

1/729

(8)

(C)

(0)

(E)

Total

NOTE:
°Qual Data
o07V Qual Data

4-66

RR·63

Table 3. Package Thermal Characteristics
Package
Type

Junction Temp.
@55·C Ambient

Junction Temp.
@70·C Ambient

Junction Temp.
@125·CAmbient

Cerdip

148

Plastic

106

161

Table 4. Failure Analysis Summary
Time Frame

Group

# Fail

Description

Ea(eV)

1/86

ISB Failure, Hot Spot on Cont.
Gate Edge of Y4 Driver

0.3

9/86

Defect Not Found

0.3

7/87

1
1

Contamination
Assembly Defect at Wire Heel

1.0
0.5

3/86

Single Bit Defect Not Found

0.3

51C98
Number of bits: 65,536
Organization:
16K x 4

Process: CHMOS IV
Package: 22-Pin
Table

Year

High Temperature Llfetest Data
125·C (5.5V) DynamiC Llfetest

Lot #
48Hrs

168 Hrs

500Hrs

1KHrs

2KHrs

04/88

27-921

3/1043

0/1040

0/890

04/88

22-957

0/488

1/488

1/337

0/336

2/335

Q4/88

24-985

41759

11755

0/604

1/604

0/603

04/88

26-903

21708

1/556

0/755

11755

04/88

26-910

1/999

01706
0/997

1/847

0/845

01/89

40-980

0/536

Oi536

01/89

42-988

Total

1/580

1/579

0/578

11/5113

315101

3/4348

1/4344

3/3228

(A)

(B)

(C)

(0)

(E)

4-67

RR-63

, Table 2, Failure Analysis Summary
Group

# Fail

Description

Ea(eV.)

1 Ea Lost during Failure Analysis
2 Ea A 1/Ti Particle in via Seam
2 Ea BPSG Crystals
1 Ea Passivation Damage
2 Ea Single Bit
1 Ea Bond Pad Corrosion
1 Ea Column Fail (M2 Particle)
1 Ea Column Fail (M1 Particle)

0.3
0.3
0.5
0.5
1.0
0.3
0.3

1 Ea Single Bit (Poly Extra)
1 Ea EOS (Electrical Overstress)
1 Ea Open (Lifted Bond)

0.3

2 Ea Single Bit
1 Ea Open (Lifted Bond)

0.3
1.0

1.0

1 Ea Single Bit

0.3

1 Ea Passivation Damage
1 Ea Leakage
1 Ea Metal 2 Input Open

0.5
0.3
0.5

Table 3. High Voltage Lifetest Data
Year

Lot #

04/88

27-921

04/88
04/88

High Voltage (7V) Dynamic Llfetest
48 Hrs

168 Hrs

500 Hrs

1KHrs

2KHrs

1/597

2/596

1/593

0/592

22-957

2/599
'0/200

01200

0/200

3/200

0/197

24-985

0/379

1/379

0/378

04/88

26-903

2/354,

1/350

2/348

0/346

04/88

26-910

3/513

1/509

0/508

1/508

01/89

40-980

1/268

0/267

01/89

42-988

0/291

1/291

0/290

8/2604

4/2593

4/2588

5/25~3

1/2021

(.1\)

(B)

(C)

(D)

(E)

Total

4-68

intJ

RR-63

Table 4. Failure Analysis Summary
Ea (eV)

Group

# Fail

1 Ea for Abnormal Contact
2 Ea A 1/Ti in via Seam
3 Ea BPSG Crystals
1 Ea BPSG Crystal
1 Ea Column Fail (M2 Particle)

0.5
0.3
0.3
0.3
0.3

1 Ea Bond Pad Corrosion
1 Ea ISB Leakage (Corrosion)
1 Ea BPSG Crystal
1 Ea Single Bit

0.5
0.5
0.3
0.3

2 Ea BPSG Crystals
1 Ea Column (Passivation Damage)
1 Ea Column Fail

0.3
0.5
0.3

4 Ea Lifted Bond
1 Ea Passivation Damage

1.0
0.5

1 Ea Metal 2 Input Open

0.5

Description

Table 5. Failure Rate Predictions

5.5V

7.0V

Totals
( )

125°C Actual
Device Hours

Ea
(eV)

Equivalent Hours
at 55°C

7,4BE

+ 06
+ 06
7,4BE + 06
4,46E + 06
4,46E + 06
4.46E + 06
11.9E + 06
11.9E + 06
11.9E + 06

0.3

7,4BE

0.5

+ 07
+ 07
26.9E + OB
11.BE + 07
B,47E + 07
16.1E + OB
16.2E + 07
22.7E + 07
43.0E + OB

1.0
0.3
0.5
1.0
0.3
0.5
1.0

Fail

FIT Rate
(60% UCL)

4,41E

0.0142

14.2E

0.0022

0.0001

0.0053

0.0074

0.0003

0.0071

0.0037

0.0002

Total
FIT
Rate

165

130

110

'48 Hour faIlures at 12S'C are not Included In long term failure rate calculatIons.
"S.SV and 7V bum-inllifetest equivalent hours have been combined.

Temp. with Tja
T(55)
= 33BK
= 40BK
T (125)

BIIELT
Accel.
Factors:

0.3eV
0.5eV
1.0 eV

K = B.62E -05 eV/K
Voltage Accel. Factor: 4,4B
NOTE:
FIT = Failures in Time. 1 FIT = 1 Failure per 10E

09 device hours.

4-69

Thermal Accel.
Factors
55°C
5.90
19.0
360

RR-63

Table 6. Infant Mentality Evaluation Results
High Temperature (7V) Burn-In

Year

Lot #
6Hrs

Hrs

24Hrs

48Hrs

168 Hrs

01/89

42-995

0/672

1/672

0/671

01/89

44-997

0/688

01/89

45-900

1/655

0/654

01/89

48-909

0/614

1/2629

0/2628

0/2627

Total

(8)

(A)

Failure Analysis
A) 1 Ea Func. fail (Metal 1 particle)
B) 1 Ea Invalid Failure (Cracked Package)

Table 7. Additional Qual!flcation Tests
Year

Low Temp (-10·C)
Llfetest (2K Hrs)

1500CHTRB
1K Hrs.

Temp Cycle
1KCycies

1600C
1000 Hrs. Bake

1988/89

0/120

5/240

0/250

1/~00

(A)
Failure Analysis
A) 1 Ea Passivation damage
1 Ea Func. fail @ < 2.6V
1 Ea Open (Lifted Bond)
1 Ea Qlown V88 Pin
1 Ea Healed
B) 1 Ea Open (Lifted Bond)

4-70

(8)

RR-63

APPENDIX A
COMMON MOS FAILURE MECHANISMS
Oxide Defects

Contamination

Oxide defects can cause dielectric breakdown in MOS
structures resulting in an electrical short. Oxide dielectric breakdown is dependent on time, ambient temperature and operating voltage. Oxide defects could be
induced by excessively thin oxide, polarization and contamination. The thermal activation energy for oxide defects is determined to be 0.3 eV.

Silicon Defects

Metallization Defects

4-71

EPROMs
(Erasable Programmable
Read Only Memories)

2716
16K (2K x 8) UV ERASABLE PROM

•
•

Access Time
• -Fast2716-1:
350 ns Max

•
•

- 2716-2: 390 ns Max
-2716: 450 ns Max
Single + 5V Power Supply
Low Power Dissipation
- Active Power: 525 mW Max
-Standby Power: 132 mW Max

•
•

Pin Compatible to Intel "Universal Site"
EPROMs
Simple Programming Requirements
- Single Location Programming
- Programs with One 50 ms Pulse
Inputs and Outputs TTL Compatible
During Read and Program
Completely Static

The Intel 2716 is a 16,384-bit ultraviolet erasable and electrically programmable read-only memory (EPROM).
The 2716 operates from a single 5-volt power supply, has a static standby mode, and features fast singleaddress programming. It makes designing with EPROMs fast, easy and economical.
The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with highperformance + 5V microprocessors such as Intel's 8085 and 8086. Selected 2716-5s and 2716-6s are also
available for slower speed applications. The 2716 also has a static standby mode which reduces power
consumption without increasing' access time. The maximum active power dissipation is 525 mW while the
maximum standby power dissipation is only 132 mW, a 75% savings.
The 2716 uses a simple and fast method for programming-a single TTL-level pulse. There is no need for high
voltage pulsing because all programming controls are handled by TTL signals. Programming of any location at
any time-either individually, sequentially or at random is possible with the 2716's single-address programming. Total programming time for all 16,384 bits is only 100 seconds.

DATA OUTPUTS
0 0 -0 7

cr--,~

AD
- A 10
ADDRESS

INPUTS

'PinNames

__~__~~

Addresses
Chip Enable
Output Enable

00-0 7

Outputs

Ao-Al0
CE

Y GATING

16,.384 - BIT
CELL MATRIX

210310-1

Figure 1. Block Diagram

5-1

September 1989
Order Number: 210310-003

intJ

2716

2716
~---\.J---~

2764A
27512 27256 27128A 27C64 2732A
27C512 27C256 27C128 87C64
Vpp
Vpp
Vpp
AIS
A12
A12
A12
A12
A7
A7
A7
A7
A7
As
As
As
As
As
As
As
A5
A5
A5
A4
A4
A4
~
~
A3
A3
Aa
A3
Aa
A2
A2
A2
A2
A2
Al
Al
Al
Al
Al
Ao
Ao
AO
AO
AO
00
00
00
00
00
01
01
01
01
01
02
02
02
02
02
GND GND GND GND GND

2764A
2732A 27C64 27128A 27256 27512
87C64 27C128 27C256 27C512

•

Vee

PGM PGM

Vee

A14
A13
As
Ag
A11
OE
Al0
CE
07
Os
Os
04
03

A14
A13
As
Ag
A11
OEIVPF
Al0

N.C. .A13
As
As
As
Ag
Ag
Ag
A11
A11
A11
OElVpp OE
OE
AlO
Al0
Al0
CE
CE AlE/CE
CE
07
07
07
Os
06
06
Os
05
Os
04
04
04
03
03
.03
Vee

CE
07
Os
Os
04
03

NOTE:
Intel "Universal Site" compatible EPROM configurations are shown in the blocks adjacent to the 2716 pins.

Figure 2. Cerdip Pin Configuration

EXTENDED TEMPERATURE
(EXPRESS) EPROMs

EXPRESS EPROM PRODUCT FAMILY

The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM, allowing
the choice of appropriate memory size to match system applications. EXPRESS EPROM products are
available with 168 ± 8 hour, 125°C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROM operating temperature range is O°C to 70°C. Extended operating temperature range (- 40°C to + 85°C) EXPRESS products are available.' Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AOL. This may allow the user to
reduce or eliminate incoming inspection testing.

PRODUCT DEFINITONS
Type Operating Temperature Burn-In 125°C (hr)
168 ±8
O°Cto +io°c
0
. -40°C to + 85°C
I
44

EXPRESS OPTIONS
2716 Versions
Packaging Options
Speed Versions
Cerdip
, -1
0

5-2

0,1

inter

2716

a) the lowest possible memory power dissipation,
and
b) complete assurance that output bus contention
will not occur.

DEVICE OPERATION
The six modes of operation of the 2716 are listed in
Table 1. It should be noted that inputs for all modes
are TIL levels. The power supplies required are a
+ 5V Vcc and a Vpp. The Vpp power supply must be
at 25V during the three programming modes, and
must be at 5V in the other three modes.

To use these two control lines most efficiently, CE
(pin 18) should be decoded and used as the primary
device selecting function, while OE (pin 20) should
be made a common connection to all devices in the
array and connected to the READ line from the system control bus. This assures that all deselected
memory devices are in their low-power standby
modes and that the output pins are active only when
data is desired from a particular memory device.

Read Mode
The 2716 has two control functions, both of which
must be logically satisfied in order to obtain data at
the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable (OE) is the output control and should be used
to gate data from the output pins, independent of
device selection. Assuming that addresses are stable, address access time (tACe) is equal to the delay
from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that
CE has been low and addresses have been stable
for at least tACC-tOE.

Programming
Initially, and after each erasure, all bits of the 2716
are in the "1" state. Data is introduced by selectively
programming "O's" into the desired bit locations. Although only "O's" will be programmed, both "1 's"
and "O's" can be presented in the data word. The
only way to change a "0" to a "1" is by ultraviolet
light erasure.

Standby Mode

The 2716 is in the programming mode when the Vpp
power supply is at 25V and OE is at VIH. The data to
be programmed is applied 8 bits in parallel to the
data output pins. The levels required for the address
and data inputs are TIL.

The 2716 has a standby mode which reduces the
maximum active power dissipation by 75%, from
525 mW to 132 mW. The 2716 is placed in the
standby mode by applying a TIL-high signal to the
CE input. When in standby mode, the outputs are in
a high impedance state, independent of the OE in.

Output OR-Tieing
Because 2716s are usually used in larger memory
arrays, Intel has provided a 2-line control function
that accommodates this use of multiple memory
connections. The two-line control function allows
for:

When the address and data are stable, a 50 ms,
active-high, TIL program pulse is applied to the CE
input. A pulse must be applied at each address location to be programmed. You can program any location at any time-either individually, sequentially, or
at random. The program pulse has a maximum width
of 55 ms. The 2716 must not be programmed with a
DC signal applied to the CE input.

Table 1 Mode Selection
Pins

Mode

CE
(18)

OE
(20)

Vpp
(21)

Vcc
(24)

Outputs
(9-11,13-17)

Read

VIL

DOUT

Output Disable

VIL

VIH

HighZ

Standby

VIH

HighZ

Program

Pulsed VIL to VIH

VIH

+25

DIN

Verify

VIL

+25

DOUT

Program Inhibit

VIL

VIH

+25

HighZ

NOTE:
1. X can be VIL or VIH.

5-3

inter

2716

ABSOLUTE MAXIMUM RATINGS'"

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

+ 80·C
+ 125·C

Temperature Under, Bias ....•...• -1 O·C to
Storage Temperat!Jre ..•.•.•... - 65·C to

All Input or Output Voltages with
Respect to Ground •...•.•.•..... + 6V to - 0.3V
Vpp Supply Volume with Respect
to Ground During Program ..... + 26.5V to - 0,3V

D.C. AND A.C. OPERATING CONDITIONS DURING READ
2716

2716-1

2716-2

Temperature Range

0·C-70·C

Vee Power Supply(1, 2)

5V ±5%

Vee

Vpp Power Supply(2)

READ OPERATION
D.C. CHARACTERISTICS
Symbol

Limits

Parameter

Units

Typ(3)

Min

Test Conditions

Max

III

Input Load Current

IJ-A

VIN

= 5.25V
= 5.25V
CE = VIH, OE =
OE = CE = VIL

ILO

Output Leakage Current

IJ-A

VOUT

IpP1(2)

Vpp Current

rnA

Vpp

lee1(2)

Vee Current (Standby)

rnA

ICC2(2)

Vee Current (Active)

100

rnA

VIL

Input Low Voltage

-0.1

0.8

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Vcc

0.45
2.4

5.25V

VIL

V
V

IOL

IOH

= 2.1 rnA
= - 4OO IJ-A

A.C. CHARACTERISTICS
Limits (ns)

Symbol

Parameter

2716

Min

Max

2716-1

Min

Max

2716-2

Min

Max

tACC

Address to Output Delay

450

350

390'

teE

CE to Output Delay

450

350

390

toE(4)

Output Enable to Output Delay

tOF(4,6)

CE or OE High to OutP!Jt Float

toH

Output Hold from Addres!?es, CE
or OE Whichever Occurred First

120
100

5-4

120

120
0

100

0
0

Test
Conditionst

100

= OE =
ot:: = VIL
CE = VIL
CE = VIL
CE = OE =
CE

VIL

intJ

2716

Programming of multiple 2716s in parallel with the
same data can be easily accomplished due to the
simplicity of the programming requirements. Like inputs of the paralleled 2716s may be connected together when they are programmed with t~ same
data. A low level TTL pulse applied to the CE input
programs the paralleled 2716s.

ERASURE CHARACTERISTICS
The erasure characteristics of the 2716 are such
that erasure begins to occur upon exposure to light
with wavelengths shorter than aproximately 4000
Angstroms (A). It should be noted that sunlight and
certain types of fluorescent lamps have wavelengths
in the 3000-4000A range. Data show that constant
exposure to room-level fluorescent lighting could
erase the typical 2716 in approximately 3 years,
while it would take approximately 1 week to cause
erasure when exposed to direct sunlight. If the 2716
is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels should
be placed over the window to prevent unintentional
erasure.

Program Inhibit
Programming of multiple 2716s in parallel with different data is also easily accomplished. Except for CE,
all like inputs (including DE) of the parallel 2716s
may be common. A TTL-level program pulse applied
to a 2716's CE input with Vpp at 25V will program
that 2716. A low-level CE input inhibits the other
2716 from being programmed.

The recommended erasure procedure for the 2716
is exposure to shortwave ultraviolet light which has a
wavelength of 2537 Angstroms (A). The integrated
dose (Le., UV intensity x exposure time) for erasure
should be a minimum of 15 Ws/cm 2. The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 p.W/cm 2
power rating. The 2716 should be placed within 1
inch of the lamp tubes during erasure.

Verify
A verify should be performed on the programmed
bits to determine that they were correctly programmed. The verify may be performed with Vpp at
25V. Except during programming and program verify, Vpp must be at 5V.

210310-3

Figure 3. Standard Programming Flowchart
5-5

2716

CAPACITANCE(4)

25°C, f

Symbol Parameter Typ(3) Max Unit

1 MHz

t A.C. TEST CONDITIONS

Test
Conditions

Output Load .................... '.. 1 TTL gate and
. CL = 100 pF

CIN

Input
Capacitance

pF VIN

COUT

Output
Capacitance

pF VOUT

Input Rise and Fall Times .............,.... :S::20 ns
Input Pulse Levels ............ , ...... 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs ........................... O.BV and 2V
Outputs .......................... 0.8V and 2V

OV
OV

A.C. WAVEFORMS(1)

... ----_1

VIH - - - - " "

ADDRESS
VALID

ADDRESSES
V1L----J

V1H

1'----------- · .. -----"1

-----+...,.

1'-------- · · · · ----"1
V1H

------1----...,.

OE
(5)
(5)

•••••••••

(4,6)
tOF

tOE

tOH

•••••••••

V1H
HIGH Z

OUTPUT-----------~~~~~~

VALID OUTPUT

•••••••••
210310-4
NOTES:
1. Vcc must be' applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected to Vcc except during programming. The supply current would then be the sum of Icc and IpP1.
3. Typical values are for T A = 25'C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested.
5. OE may be delayed up to tAcc-tOE after the falling edge of CE without impact on tACC.
6. tDF is specified from OE or CE, whichever occurs first.

5-6

intJ

2716

PROGRAMMING CHARACTERISTICS
=

D.C. PROGRAMMING CHARACTERISTICS TA
Symbol

Parameter

25°C ±5°C, Vec!1)

Min

Typ

5V ±5%, Vpp(1,2)

Max

25V ±1V

Test
Conditions

Units

III

Input Current (for Any Input)

p,A

VIN

5.25V/0.45

IpP1

Vpp Supply Current

VIL

IpP2

Vpp Supply Current during
Programming Pulse

=
=

lee

Vee Supply Current

100

VIL

Input Low Level

-0.1

O.B

VIH

Input High Level

2.0

5V ± 5%, Vpp(1, 2)

25V ± 1V

A.C. PROGRAMMING CHARACTERISTICS T A
Symbol

Vee

25°C ± 5°C, Vee(1)

Parameter

Min

Typ

+
=

Max

Units

tAS

Address Setup Time

p,s

tOES

OE Setup Time

p,s

tAH

Address Hold Time

p,s

tOEH

OE Hold Time

p,s

tOH

Data HoldTime

p,s

tOFP

Output Enable to Output Float Delay

tOE

Output Enable to Output Delay

tpw

Program Pulse Width

tpRT

Program Pulse Rise Time

tpFT

Program Pulse Fall Time

tos

. Data Setup Time

VIH

Test
Conditions'

200

CE = VIL

200

CE = VIL

• A.C. CONDITIONS OF TEST
Input Rise ar:td Fall Times (10% to 90%) ...... 20 ns
Input Pulse Levels ................... O.BV to 2.2V
Input Timing Reference Level ......... O.BV and 2V
Output Timing Reference Level ........ O.BV and 2V
NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The 2716 must not be
inserted into or removed from a board with Vpp at 25 ± 1V to prevent damage to the device.
2. The maximum allowable voltage which may be applied to the Vpp pin during programming is + 26V. eare must be taken
when switching the Vpp supply to prevent overshoot exceeding this 26V maximum specification.

5-7

2716

PROGRAMMING WAVEFORMS
PROGRAM

---J.----

VERIFY - - - - - I

VIH - - - - -...
ADDRESSES

ADDRESS

VIL---J

VIH - - - - _ 1
DATA IN
STABLE

DATA
VIL----....II
t oFP
(D.20 MAX)

VIH

OE
VIL---J

VIH

CE
VIL

---------'1
210310-5

NOTES:
1. All times shown in parenthesis are minimum times and are JLs unless otherwise noted.
2. toE and tOFP are characteristics of the device but must be accommodated by the programmer.

REVISION HISTORY
Number

Description

Deleted -5 and -6 speed bins. Added Express options.
Added Standard Programming Flowchart.
Revised Pin Configuration and Block Diagram.

5-8

2732A
32K (4K x 8) UV ERASABLE PROMS
200 ns (2732A-2) Maximum Access
• Time
.•. HMOS*-E Technology
with High-Speed
• Compatible
Microcontrollers and Microprocessors
••• Zero WAIT State
Two Line Control
• 10% Vcc Tolerance Available
•

Current Requirement
• Low
-100 rnA Active
- 35 rnA Standby
inteligent IdentifierTM Mode
• - Automatic Programming Operation
Standard Pinout •.• JEDEC
• Industry
Approved 24 Pin Ceramic Package
(See Packaging Spec. Order #231369)

The Intel 2732A is a 5V-only, 32,768-bit ultraviolet erasable (cerdip) Electrically Programmable Read-Only
Memory (EPROM). The standard 2732A access time is 250 ns with speed selection (2732A-2) available at
200 ns. The access time is compatible with high performance microprocessors such as the 8 MHz iAPX 186. In
these systems, the 2732A allows the microprocessor to operate without the addition of WAIT states.
An important 2732A feature is Output Enable (DE) which is separate from the Chip Enable (CE) control. The
OE control eliminates bus contention in microprocessor systems. The CE is used by the 2732A to place it in a
standby mode (CE = VI H) which reduces power consumption without increasing access time. The standby
mode reduces the current requirement by 65%; the maximum active current is reduced from 100 rnA to a
standby current of 35 rnA.
'HMOS is a patented process of Intel Corporation.
DATA OUTPUTS

00-07

vcc_

Pin Names

OEIVpp_

~~C:::::::-

OUTPUT BUFfERS
Y·GATING

Ao-A"
ADDRESS
INPUTS

32.768·BIT

DECODER

CELL MATRIX

AO-A11

Addresses

Chip Enable

OElVpp

Output EnablelVpp

0 0 -07

Outputs

290081-1

Figure 1. Block Diagram
2764A
27512 27256 27128A
27C64 2716
27C512 27C256 27C128
87C64

vpp

Vpp

A'2
A7
A6
As
A2
AI
Ao
00
0,
02

A'2
A7
As
As
A4
A3
A2
AI
Ao
00
0,
02

A'2
A7
A6
As
A4
A3
A2
AI
Ao
00
0,
02

GND

GND GND

Aa,

~---\..J---:

A,S
A'2
A7
A6
As
A4
A3
A2
AI
Ao
00
0,
02

A7
A6
As
A4
A3
A2
AI
Ao
00
0,
02

2764
27128A 27256 27512
2716 2764A
27C128 27C256 27C512
87C64

2732A

Vcc

Vee
AS

As
A11

Vpp

A,O

A'0

CE
07

°5
°40

GND

As
Ag

liE/vpp

°2

PGM
Vce N.C.
As
Ag
AI1

VCC
J5GM

VCC

Vcc

A'3

A'4
A'3

Ag
AI1

A'4
A'3
As
Ag
AI1

Ag
AI1

OElVpp

A'0

AIO

07
06
05
04
03

ALE/CE

07
06
05
04
03

CE
07
06
05
04
03

290081-2

NOTE:
Intel "Universal Site" compatible EPROM configurations are shown in the blocks adjacent to the 2732A pins.

Figure 2. Cerdip Pin Configuration

5-9

September 1989
Order Number: 290081-004

2732A

EXTENDED TEMPERATURE
(EXPRESS) EPROMs

EXPRESS EPROM PRODUCT FAMILY

The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM, allowing
the choice of appropriate memory size to match system applications. EXPRESS EPROM products are
available with 168 ±8 hour, 125·C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROM operating temperature range is O·C to 70·C. Extended operating temperature range (-40·C to + 85·C) EXPRESS products are available. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.

PRODUCT DEFINITONS
Type Operating Temperature Burn-In 125·C (hr)
Q
O·Cto +70·C
168 ±8
- 40·C to + 85·C
T
None
-40·Cto +85·C
168 ±8
L

EXPRESS OPTIONS'
2732A Versions
Packaging Options
Speed Versions
-2

Cerdip
Q

-25

Q, T,L

READ OPERATION
D.C. CHARACTERISTICS

Electrical Parameters of EXPRESS EPROM products are identical to standard EPROM parameters
except for:
Symbol
ISB

ICC1(1)

Parameter

TD2732A
LD2732A
Min

Max

Test
Conditions

Vee Standby
Current (mAl

CE
OE

= VIH,
= VIL

VccActive
Current (mAl

150

VccActive
Current at High
Temperature (mAl

125

OE = CE = VIL,
Vpp = Vee,
T Ambient = 85·C

VIL

NOTE:
1. Maximum current value is with outputs 00 to 07 unloaded.

30 J1.s

°70

AonnJ
.J"LJ
•

°s
°40 3

Binary Sequence from Ao to A11

Vee
6

OElVpp = +5V. R = 1Kn.
vss = GND. CE = GND

vcc

•

290081-4

290081-3
=

+5V

Burn-In Bias and Timing Diagrams
5-10

inter

2732A

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temp. During Read ....... O·C to + 70·C
Temperature Under Bias ......... -10·C to + SO·C
Storage Temperature .......... - 55·C to + 125·C
All Input or Output Voltages with
Respect to Ground .............. - 0.3V to + 5V
Voltage on A9 with Respect
to Ground ................... - 0.3V to + 13.5V
Vpp Supply Voltage with Respect to Ground
During Programming ........... - 0.3V to + 22V
Vcc Supply Voltage with
Respect to Ground ............ - 0.3V to + 7.0V

READ OPERATION
D.C. CHARACTERISTICS o·c s
Symbol

TA S

+ 70·C
Limits

Parameter

Typ(3)

Min
III

Input Load Current

Units

Conditions

Max
10

p.A

VIN

5.5V

ILO

Output Leakage Current

p.A

VOUT

15S(2)

Vcc Current (Standby)

rnA

VIH, OE

ICC1(2)

Vcc Current (Active)

100

rnA

=
OE =

VIL

Input Low Voltage

-0.1

O.S

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

A.C. CHARACTERISTICS o·c s
Versions
Symbol

Vcc

5.5V

VIL

0.45

= 2.1 rnA
10H = - 400 p.A

2.4

10L

T A S 70·C

Vee ±5%

2732A-2

2732A

Vee ±10%

2732A-20

2732A-25

Parameter

Min

Max

Min

Units

Test
Conditions

Max

tACC

Address to Output Delay

200

250

tCE

CE to Output Delay

200

250

tOE

OElVpp to Output Delay

100

tDF(4)

OElVpp High to Output Float

tOH(4)

Output Hold from Addresses,
CE or OElVpp, Whichever
Occurred First

0
0

= OE =
= VIL
= VIL
= VIL
= OE =

VIL

NOTES:

1. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
2. The maximum current value is with outputs 00 to 07 unloaded.
3. Typical values are for TA = 25'C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.

5-11

intJ

2732A

CAPACITANCE (2) TA =
Symbol

25'C. f

= 1 MHz

Parameter

CIN1

Input Capacitance
Except OElVpp

CIN2

OElVpp Input
Capacitance

COUT

Output Capacitance

Typ

Max

Unit

VIN = OV

VOUT = OV

A.C. TESTING INPUT/OUTPUT WAVEFORM

Conditions

A.C. TESTING LOAD CIRCUIT

l'N...

2.4

2.0>
0.8

0.45

___
TEST POINTS ---.....

2.0
OUTPUT

3.3Kn

,,0:;,;;.8:...._ _
DEVICE
UNDER

290081-5

~oUT

TEST

rc,,='OOPF
A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for
a logic "0". Timing measurements are made at 2.0V for a logic
"I" and 0.8V for a logic "0".

290081-6

CL = 100 pF
CL Includes Jig Capacitance

A.C. WAVEFORMS
VIH - - - - - - - " ' ' \ .

V _ _ _ _ _ _ _.1
ADDRESSES
IL

1,.--------_ ....... .
1'-------........ .
ADDRESS
VALID

VIH - - - - - - - - - / - "

CE
VIL

VIH

1'-----........ .
--------+--_

OE/Vpp
VIL

~--.-+

........ .

OUTPUT _ _ _ _ _ _~H_IG;;.;H_Z:-_ _ _~E_++

TEST POINTS _ _ _

0.8

A.C. TESTING LOAD CIRCUIT

2.0
OUTPUT
=0.;:.8_ __

3.3KU

0.45
DEVICE

230864-3

UNDER
T~ST

A.C. Testing; Inputs are Driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing Measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".

I---+--O~

ICL '"

OUT

100pF

230864-4
CL = 100 pF
CL Includes Jig Capacitance

A.C. WAVEFORMS

V,H-----_
ADDRESSES

VIL _ _ _ _ _- J

ADDRESS
VALID

V,H --------11-""\

V,H --------1----"""\

OUTPUT _ _ _ _ _ _H:.::I.:::OH::;Z=-_ _ _ _~~+H~

HIOHZ

230864-5

NOTES:
1. Typical values are for T A = 25'C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE.

5·22

2764A

To use these two control lines most efficiently, CE
should be decoded and used as the primary device
selecting function, while OE should be made a common connection to all devices in the array and connected to the READ line from the system control
bus. This assures that all deselected memory devices are in their low power standby mode and that the
output pins are active only when data is desired from
a particular memory device.

DEVICE OPERATION
The modes of operation of the 2764A are listed in
Table 1. A single 5V power supply is required in the
read mode. All inputs are TTL levels except for Vpp
and 12V on Ag for inteligent identifier mode.
Table 1. Mode Selection
Pins
Mode

CE OE PGM

AD Vpp Vee Outputs

Read

VIL VIL

VIH

X(I)

X Vee 5.0V

DOUT

Output Disable

VIL VIH

VIH

HighZ

Standby

VIH

X Vee 5.0V
X Vee 5.0V

Programming

VIL VIH

VIL

(4)

Program Verify

VIL VIL

VIH

(4)

DOUT

Program Inhibit

VIH

(4)

HighZ

inleligent Identifier(3)
-manufacturer
VIL VIL
-device

VIL VIL

SYSTEM CONSIDERATIONS

HighZ

The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The as-'
sociated transient voltage peaks can be suppressed
by complying with Intel's Two-Line Control and by
properly selected decoupling capacitors. It is recommended that a 0.1 /kF ceramic capacitor be used on
every device between Vcc and GND. This should be
a high frequency capacitor of low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 /kF bulk electrolytic
capacitor should be used between Vcc and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effect of· PC board-traces.

DIN

VIH

VH(2) VIL Vee 5.0V

B9H

VIH

VH(2) VIH Vee 5.0V

OBH

NOTES:
1. X ean be VIH or VIL.
2. VH = 12.0V±O.5V.

3. Al-AB, Al0-A12 = VIL.
4. See Table 2 for Vee and Vpp voltages.

Read,Mode
The 2764A has two control functions, both of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to
gate data from the output pins, independent of de'vice selection. Assuming that addresses are stable,
the address access time (tACel is equal to the delay
from CE to output (teE), Data is available at the outputs after a delay of toE from the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tACC-toE'

PROGRAMMING MODES
Caution: Exceeding 14V on Vpp will permanently
damage the device.

Standby Mode

Initially, all bits of the EPROM are in the "1" state.
Data is introduced by selectively programming "Os"
into the desired bit locations. Although only "Os" will
be programmed, both "1s" and "Os" can be present
in the data word. The only way to change a "0" to a
"1" is by ultraviolet light exposure (Cerdip
EPROMs).

EPROMs can be placed in a standby mode which
reduces the maximum current of the devices by applying a TTL-high signal to the CE input. When in the
standby mode, the outputs are in a high impedance
state, independent of the. OE input.

Two Line Output Control
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 control lines which
accommodate this multiple memory connection. The
two control lines allow for:
a) the lowest possible memory power dissipation,
and

The device is in the programming mode when Vpp is
. raised to its programming voltage (see Table 2) and
CE and PGM are both at TTL-low. The data to be
programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and
data inputs are TTL.

b) complete assurance that output bus contention
will not occur.
5-23

2764A

Program Inhibit

dress line AO from VIL to VIH. All other address lines
must be held at VIL during inteligent Identifier Mode.

Programming of multiple EPROMs in parallel with
different data is easily accomplished by using the
Program Inhibit mode. A high-level CE or PGM input
inhibits the other devices from being programmed.

Byte 0 (AO = VIU represents the manufacturer code
and byte 1(AO = VI H) the device identifier code.
These two identifier bytes are given in Table 1.

Except for CE, all like inputs (including OE) of the
parallel EPROMs may be common. A TIL low-level
pulse applied to the CE input with Vpp at its programming voltage (see Table 2) will program the selected device.

Program Verify
A verify should be performed on the programmed
bits to determine that they have been correctly programmed. The verify is performed with OE at VIL,
PGM at VIH and Vpp and Vee at their programming
voltages.

inteligent Identifier™ Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device.
To activiate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling ad-

ERASURE CHARACTERISTICS
The erasure characteristics are such that erasure
begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000 A range. Data shows that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately three years, while it
would take approximately one week to cause erasure when exposed to direct sunlight. If the EPROM
is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels should
be placed over the window to prevent unintentional
erasure.
The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a
minimum of fifteen (1'5) Wsec/cm 2. The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 p.W/cm2
power rating. The EPROM should be placed 'within
one inch of the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to
without damage is 7258 Wsec/cm 2 (1 week @
12000 p,W/cm2). Exposure of the EPROM to high
intensity UV light for longer periods may cause permanent damage.

5-24

2764A

DEVICE

FAILED

DEVICE
FAILED

230864-7

Figure 3. inteligent Programmlng™ Flowchart
gram pulse of length 3X msec. X is an iteration counter and is equal to the number of the initial one millisecond pulses applied to a particular location, before a correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram pulse is applied.

inteligent Programming™ Algorithm
The inteligent Programming Algorithm, a standard in
the industry for the past few years, is required for all
of Intel's 12.5V CERDIP EPROMs. Plastic EPROMs
may also be programmed using this method. A flowchart of the inteligent Programming Algorithm is
'
shown in Figure 3.

The entire sequence of program pulses and byte
verifications Is performed at Vee = 6.0V and

The inteligent Programming Algorithm utilizes two
different pulse types: initial and overprogram. The
duration of the initial PGM pulse(s) is one millisecond, which will then be followed by a longer overpro-

Vpp = 12.SV. When the inteligent Programming cycle has been completed, all bytes should be compared to the original data with Vee = Vpp = 5.0V.

5-25

intJ

2764A

Table 2

D.C. PROGRAMMING CHARACTERISTICS
Symbol

TA = 25°C ± 5°C
Limits

Parameter

III

Input Current (All Inputs)

Vil

Input Low Level (All Inputs)

Min

Max

Unit

10
-0.1

0.8

/LA
V

2.0

Vee
0.45

VIN

= Vil or VIH

IOl

IOH

= 2.1 mA
= - 400 /LA

= Vil

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH
lee2(4)

Output High Voltage During Verify
Vee Supply Current (Program & Verify)

IpP2(4)

Vpp Supply Current (Program)

VIO
Vpp

Ag inteligent Identifier Voltage

12.5

inteligent Programming Algorithm

12.0

13.0

Vee

inteligent Programming Algorithm

5.75

6.25

2.4

11.5

Test Conditions
(see Note 1)

PGM

= Vil

A.C. PROGRAMMING CHARACTERISTICS.
TA = 25°C ±5°C (see table 2 for Vee and Vpp voltages)
Symbol

Limits

Parameter
Min

Typ

Max

Unit

tAS

Address Setup Time

/Ls

tOES

OE Setup Time

/Ls

tos

Data Setup Time

/Ls

tAH

Address Hold Time

/Ls

tOH

Data Hold Time

tOFP

OE High to Output
Float Delay

130

/Ls
ns

tvps

Vpp Setup Time

/Ls

tves

Vee Setup Time

/Ls

teEs
tpw

CE Setup Time

PGM Initial Program Pulse Width

0.95

topw

PGM Overprogram Pulse Width

2.85

tOE

Data Valid from OE

1.0

1.05

/Ls
ms

78.75

150

Test Conditions'
(see Note 1)

(See Note 3)

(see Note 2)

NOTES:
1. Vee must be applied simultaneously or before Vpp and
.
removed simultaneously or after Vpp.
2. The length of the overprogrampulse may vary from 2.85
msec to 78.75 msec as a function of the iteration counter
value X.
3. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no longer driven-see timing diagram.
4. The maximum current value is with Outputs 00 to 07
unloaded.

• A.C. CONDITIONS OF TEST
Input Rise and Fall Times
(10% to 90%) ............... , ...........•. 20 ns
Input Pulse Levels .................. 0.45V to 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 2.0V

5-26

inter

2764A

PROGRAMMING WAVEFORMS
VERIFY

PROGRAM

ADDRESSES

ADDRESS STABLE

DATA

_IAS_

DATA IN STABLE

HlghZ

_IAH

DATA OUT JALID

~IDH.

_'DS_

C
r ' D..

12.SY

vpp

s.w

I--'vps6.DV
, Vee

5.GV

f---Ivcs-

VrH

I--tc.s -

V,H

Ipw

I-

I-to"1

'OPW

I-

*- to._

230864-8

NOTES:
1. The input timing reference level is O.BV for VIL and 2V for a VIH.
2. toE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the 2764A, a 0.1 ,..F capacitor is required across Vpp and ground to suppress spurious voltage
transients which can damage the device.

REVISION HISTORY
Description

Number
06

Deleted Plastic DIP package. Deleted QuickPulse sections.
Revised Pin Configuration. Revised Express options. Deleted
- 3, - 30, - 4 and ~ 45 speed bins.
D.C. Characteristics - III Conditions are VIN = OV to Vee
D.C. Characteristics - ILO Conditions are VOUT = OV to Vee

5-27

27128A
128K (16K x 8) PRODUCTION AND UV ERASABLE PROMs
• Fast 150 nsec Access Time
- HMOS* II-E Technology
• Low Power
- 100 mA Maximum Active
- 40 mA Maximum Standby

• inteligent Identifier™ Mode
- Automated Programming Operations

•

± 10% Vee Tolerance Available

• Available in 28-Pin Cerdip Package
(See Packaging Spec, Order #231369)

The Intel 27128A is a 5Vonly, 131,072-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The 27128A is fabricated with Intel's HMOS* II-E technology which significantly reduces die size
and greatly improves the device's performance, reliability and manufacturability.
The 27128A is currently available in the CERDIP package providing flexibility in prototyping and R&D environments where reprogrammability is required.
The 27128A is available in fast access times including 150 ns (27128A-l). This ensures compatibility with highperformance microprocessors, such as Intel's 8 MHz 80186 allowing full speed operation without the addition
of WAIT states. The 27128A is also directly compatible with the 12 MHz 8051 family.
"HMOS is a patented process of Intel Corporation.

DATA OUTPUTS

vcco-o--..
.
GNDo-o--..
.
Vpp 0

00-0 7

•

OUTPUT BUFFERS

Y-GATING
Ao-A13
ADDRESS
INPUTS

X
DECODER

131,072·BIT
CELL MATRIX

230849-1

Figure 1. Block Diagram

5-28

October 1990
Order Number: 230849-009

27128A

Pin Names

27512
27C512

27256
27C256

2764A
27C64
87C64

A,S

Vpp

A'2
A7
A.
As

A'2
A7

As
A.
A3
A2
A,
Ao
00
0,
02
GND

A3
A2
A,
Ao
00
0,
O2
GND

A3
A2
A,
Ao
00
0,
02
GND

2732A

Ao-A'3

ADDRESSES

CHIP ENABLE

OUTPUT ENABLE

Do-Or

OUTPUTS

PGM

PROGRAM

NO INTERNAL CONNECT

27128A

2716
Vpp

Aa
A2
A,
Ao
00
0,
02
GND

2716

27256
27C256

27512
27C512

Vee

PGM

Vee
A,.

N.C.
As
Ag

A"
A'3
As
Ag

Al1
OE
A,o

A"
OE/Vpp
A,o

Vee

PGM

A'2
A7
As

Au
As
Ag

A3
A2
A,

Ao
00
0,
02
GND

A7
A.
As

2764A
27C64
87C64

2732A

Vee

Vee
As
Ag
Vpp
OE

A,o

A"
OE/Vpp
A,o

Al£/CE

ALE/CE

Ao
00

°7
0.

°s

°2
GND

07
D.
05
D.
03

07
D.
Os
D.
03

07
D.
Os
D.

°3

07
D.
05
D.
03

230849-2
NOTE: Intel ".Universal Site"-Compatible EPROM Pin Configurations are Shown in the Blocks Adjacent to the 27128A Pins

Figure 2. Cerdlp(D) DIP Pin Configuration

5-29

A'3

As
Ag

inter

27128A

EXTENDED TEMPERATURE
(EXPRESS) EPROMS
The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is'
available for several densities of EPROM, allowing
the choice of appropriate memory size to match sys, tem applications. EXPRESS EPROM products are

available with 168 ± 8 hour, 125'C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROM operat,ing temperature range is O'C to 70·C. Extended operating temperature range (- 40'C to + 85'C) EXPRESS products are available. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AQL. This may allow the user to
,reduce or eliminate incoming inspection testing.

EXPRESS EPROM PRODUCT FAMILY

EXPRESS OPTIONS

PRODUCT DEFINITIONS

27128A Versions

Type

Operating Temperature

Burn-in 125'C (hr)

0'
T

O'Cto +70'C

168 ±8

- 40'C to + 85'C

None

-40'Cto +85'C

168 ±8

Packaging Options

Speed Versions

Cerdlp

' I

-20

T,L,O

READ OPERATION
DC CHARACTERISTICS
Electrical Parameters of Express EPROM Products are identical to standard EPROM parameters except for'
Symbol

TD27128A, LD27128A

Parameter

Min
ISB

leel(l)

Test Conditions

Max

Vcc Standby Current (mA)

Vee Active Current (mA)

125

Vee Active Current
at High Temperature (mA)

100

CE = VIH, OE = VIL
OE = CE = VIL
OE = CE = VIL,VPP = Vee
TAmbient = 85'C

NOTE:
1. The maximum current value is with Outputs 00 to 07 unloaded.

30 P"

AonrlS

AIJLr'

AI3

Binary Sequence from Ao to AI3

OE=+5V
vpp = +5V

R=lkfl
Vss = GND

230849-10
Vcc=+5V
eE = GND

Burn-In Bias and Timing Diagrams

5-30

230849-11

intJ

27128A

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature During
Read ................. '.' ........ O°C to

+ 70°C
Temperature Under Bias ......... -10°C to + ao°c
Storage Temperature .......... - 65°C to + 125°C
All Input or Output Voltages with
Respect to Ground ........... - O.6V to

+ 6.25V

Voltage on Ag with
Respect to Ground ........... - O.6V to

+ 13.5V

Vpp Supply Voltage with Respect to
Ground During Programming .... - O.6V to

+ 14V

VCC Supply Volt~ge
with Respect to Ground ........ - O.6V to

+ 7.0V

READ OPERATION
DC CHARACTERISTICS
Symbol

O°C :;;; T A :;;;

+ 70°C
Limits

Parameter

Notes

Typ(3)

Min

Units

Max

Conditions

III

Input Load Current

).LA

VIN=OV to Vcc

ILO

Output Leakage Current

).LA

VOUT=OVto Vcc

IpP1

Vpp Current Read

Vpp=5.5V

IS8

Vcc Current Standby

CE=VIH

ICC1

Vcc Current Active

100

CE=OE=VIL

VIL

Input Low Voltage

-0.1

+0.8

VIH

Input High Voltage

2.0

Vcc+ 1

VOL

Output Low Voltage

0.45

IOL =2.1 mA

VOH

Output High Voltage

IOH= -400).LA

Vpp

Vpp Read Voltage

Vcc=5.0V±0.25

AC CHARACTERISTICS
Versions(5)

2
2

2.4
2
O°C :;;; T A :;;;

VCC±5%
Vcc±10%

Symbol

3.8

Vcc

+ 70°C

Notes

Characteristics

27128A-l
Min

Max

27128A-2

27128A

27128A-20

27128A-25

Min

Max

Min

Unit

Max

tACC

Address to Output Delay

150

200

250

,ns

tCE

CE to Output Delay

150

200

250

tOE

OE to Output Delay

100

tOF

OE High to Output Float

tOH

Output Hold from
Addresses CE or OE
Whichever Occurred First

0
0

NOTES:
1. Vec must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vcc except during programming. The supply current would then be the sum of Icc and
IpP1. The maximum current value is with Outputs 00 to 07 unloaded.
3. Typical values are for TA = 25'C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested. Output Float is defined as. the point where data is no longer
drlven-see timing diagram.

5-31

intJ

27128A

CAPACITANCE(2hA =
Symbol

25°C, f

Parameter

CIN

Input Capacitance

COUT

Output Capacitance

1MHz

Typ(l)

Max

Unit

4
8

VIN = OV

VOUT = OV

AC TESTING INPUT/OUTPUT WAVEFORM

Conditions

AC TESTING LOAD CIRCUIT
1.3V
lNS14

2.4

2.0>

TEST POINTS _ _

0.8

0.45

2.0
~0.;.;.8

OUTPUT'
_ __

3.3Kn

DEVICE
UNDER
TEST

230849-3

OUT
-'

A.C. lesling inpuls are driven al 2.4V for a Logic '"''" and 0.45V
for a Logic "'0"'. Timing measuremenls are made al 2.0V for a
Logic """' and O.BV for a Logic "'0.'"

CL = ,00 pF
CL Includes Jig Capacilance

I-

CL~100pF

230B49-4

AC WAVEFORMS

V , H - - - - - -....
ADDRESS
VALID

ADDRESSES
VIL------.1

V,H

--------t--,
_ - - - t e e I31 _ _ _ _ + _

V,H

-------+----_

'-----1-- •••.

~----t.cc-----.-.j

OUTPUT _ _ _ _ _ _....:.:H;.::IG::;H~Z;...._ _ _ _ _~Ht_++<

HIGHZ

230B49-5

NOTES:
1. Typical values are for T A = 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE-toE after the falling edge of CE without impact on teE.

5-32

inter

27128A

DEVICE OPERATION
The modes of operation of the 27128A are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for Vpp and 12V on·A9 for inteligent Identifier.
Table 1 Modes Selection
Ag
Outputs
Mode
Notes
CE
OE
PGM
Vpp
AD
Vee
Read

Output Disable
Standby
Programming

5.0V

DOUT
HighZ

Vee
Vpp

5.0V

HighZ

6.0V

DIN

Vpp

6.0V

VIH

VIH
X

VIL

VIH

VIL

VIL
VIH

VIL
X

Vpp

6.0V

DOUT
HighZ

Manufacturer

2,3

VIL

VIH

VIL

Vee

5.0V

89H

Device

2,3

VIL

VIH

Vee

5.0V

89H

Program Inhibit

I
I

5.0V

Vee

VIL

4
4
4

Program Verify
inteligent
Identifier

X
X
X
X
X
X

Vee

VIH
X

X
X
X
X
X
X

VIL

NOTES:

1.
2.
3.
4.

X can be VIL or VIH
VH = 12.0V ±O.5V
A1-Aa, A10-A12 = VIL
See Table 2 for Vee and Vpp voltages.
To use these two control lines most efficiently, CE
should be decoded and used as the primary device
selecting function, while OE should be made a common connection to all devices in the array and connected to the READ line from the system control
bus. This assures that all deselected memory
devices are in their low power standby mode and
that the output pins are active only when data is
desired from a particular memory device.

Read Mode
The 27128A has two control functions, both of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to
gate data from the output pins, independent of device selection. Assuming that addresses are stable,
the address access time (tAee) is equal to the delay
from CE to output (teE). Data is available at the outputs after a delay of toE from the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tAee-tOE.

SYSTEM CONSIDERATIONS
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, IcC, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed
by complying with Intel's Two-Line Control, and by
properly selected decoupling capacitors. It is recommended that a 0.1 /LF ceramic capacitor be used on
every device between Vee and GND. This should be
a high frequency capacitor for low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 /LF bulk electrolytic
capacitor should be used between Vee and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effect of PC board-traces.

Standby Mode
EPROMs can be placed in standby mode which reduces the maximum current of the device by applying a TTL-high signal to the CE input. When in standby mode, the outputs are in a high impedance state,
independent of the OE input.

5-33

inter

27128A

PROGRAMMING MODES
Caution: Exceeding 14 V on Vpp will permanently
damage the device.
Initially, and after each erasure, all bits of the
EPROM are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations. Although only "Os" will be programmed,
both "1 s" and "Os" can be present in the data word.
The only way to change a "0" to a "1" is by ultraviolet light erasure.
The device is in the programming mode when Vpp is
raised to its programming voltage (See Table 2) and
CE and PGM are both at TTL low. The data to be
programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and
data inputs are TTL.

of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line Ag of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line Ao from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
M~&
.
Byte 0 (Ao = VII) represents the manufacturer code
and byte 1 (Ao = VI H) the device identifier code.
These' two identifier bytes are given in Table 1.

ERASURE CHARACTERISTICS
Program Inhibit
Programming of multiple EPROMS in parallel with
different data is easily accomplished by using the
Program Inhibit mode. A high-level CE or PGM input
. inhibits the other devices from being programmed.
Except for CE, all like inputs (including OE) of the
parallel EPROMs may be common. A TTL low-level
pulse applied to the PGM input with Vpp at its programming voltage and CE at TTL-Low will program
the selected device.

The erasure characteristics are such that erasure
begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the device is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.

Program Verify

The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 /kW/cm2 power rating. The EPROM should be placed within 1 inch of
the lamp tubes during erasure. The maicimum integrated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000 /kW/
cm 2). Exposure of the device to high intensity UV
light for longer periods may cause permanent damage.

A verify should be performed on the programmed
bits to determine that they have been correctly programmed. The verify is performed with OE at VIL, CE
at VIL, PGM at VIH and Vpp and Vee at their programming voltages.

inteligent Identifier Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the pl1lrpose

5-34

27128A

DEVICE
FAILED

230849-6

Figure 3. inteligent Programming Flowchart
pulse of iength 3X msec. X is an iteration counter
and is equal to the number of the initial one millisecond pulses applied to a particular location, before a
correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram
pulse is applied.

inteligent Programming™ Algorithm
The inteligent Programming™ Algorithm, a standard
in the industry for the past few years, is required for
the 27128A. A flow-chart of the inteligent Programming Algorithm is shown in Figure 3.

The entire sequence of program pulses and byte
verifications is performed at Vee = 6.0V and
Vpp = 12.Sv' When the inteligent Programming cy-

The inteligent Programming Algorithm utilizes two
different pulse types: initial and overprogram. The
duration of the initial pulse(s} is one millisecond,
which will then be followed by a larger overprogram

cle has been completed, all bytes should be compared to the original data with Vee = Vpp = 5.0V.

5-35

inter

27128A

DC PROGRAMMING CHARACTERISTICS
Symbol

TA = 25°C ±5°C

limits
Min

Max

Unit

Test Conditions
(Note 1)

p.A

VIN "'" VIL or VIH

-0.1

0.8

2.0

Vee + 1

0.45

10L = 2.1 mA

10H = - 400 p.A

Parameter

III

Input Current (All Inputs)

VIL

Input Low Level (All Inputs)

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

lee2(4)

Vee Supply Current (Program & Verify)

100

rnA

IpP2

Vpp Supply Current (Program)

rnA

2.4

VIO

Ag inteligent Identifier Voltage

11.5

12.5

Vpp

inteligent Programming Algorithm

12.0

13.0

Vee

inteligent Programming Algorithm

5.75

6.25

VIL

PGM

VIL

AC PROGRAMMING CHARACTERISTICS
= 25°C ±5°C (See Table 2 for Vee and Vpp voltages.)

Symbol

Limits

Parameter
Min

Typ

Max

Unit

tAS

Address Setup Time

p.s

toES

OE Setup Time

p.s

tos

Data Setup Time

p.s

tAH

Address Hold Time

p.s

tOH

Data Hold Time

tOFP

OE High to Output Float Delay

tvps

Vpp Setup Time

p.s

tves

Vee Setup Time

p.s

teEs

CE Setup Time

tpw

PGM Initial Program Pulse Width

0.95

topw

PGM OVerprogram Pulse Width

2.85

tOE

Data Valid from OE

*AC

Conditions·
(Note 1)

p.s
130

(Note 3)

p.s
1.0

1.05

78.75

150

(Note 2)

NOTES:

CONDIT,ONS OF TEST

1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp.
2. The length of the overprogram pulse may vary from
2.85 msec to 78.75 msec as a function of the iteration
counter value X.
3. This parameter is only sampled and is not 100% tested.
Output Float is defined as the pOint where data is no longer driven-see liming diagram.
4. The maximum current value is with outputs 00-07 un·
loaded.

Input Rise and Fall Times (10% to 90%) ...... 20 ns
Input Pulse Levels ....•.........•... 0.45V to 2.4V
Input Timing Reference Level ...•... 0.8V and 2.0V
Output Timing Reference Level ..•..• 0.8V and 2.0V

5-36

27128A

PROGRAMMING WAVEFORMS
PROGRAM
V'H
ADDRESSES
VIL

VERIFY

ADDRESS STABLE

f4--'A5_

DATA

DATA IN STABLE

HIGHZ

_'AH

DATA OUT VALID

~.tOH ...

f4-- ' 0 5 _

L
r-

tOFP

12.5V
V__
5.OV

f4--'vP5 _

6.0V
Vee
S.OV

V'H

CE
VIL

l-'ve5_

~
~'CES_

V'H

PGM
VIL

V'H

VIL

\.....-..J

Ipw

topw

I-

_ ' 0' 5 1

I-

10.

230849-7

NOTES:
1. The Input Timing Reference Level is 0.8V for VIL and 2V for a VIH.
2. toE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the 27128A, a 0.1 J.'F capaCitor is required across Vpp and ground to suppress spurious voltage
transients which can damage the device.

REVISION HISTORY
Number

Description

009

Removed Plastic Package

5-37

in1:el®

27256
256K (32K x 8) PRODUCTION AND UV ERASABLE PROMS

•

New Quick-Pulse Programming™
Algorithm for Plastic P27256
- 4 Second Programming
- inteligent Programming™ Algorithm
Compatible

• Fast Access Time
-170 ns 027256-1
- 200 ns P27256-2

•

Plastic Production P27256 is
Compatible with Auto-Insertion
Equipment

•
•

Moisture Resistant
Industry Standard Pinout •.. JEOEC
Approved ••• 28 Lead Cerdip and
Plastic Package
(See Packaging Spec, Order # 231369)

• inteligent IdentifierTM Mode
The Intel 27256 is a 5V only, 262,144-bit Ultraviolet Erasable (Cerdip)/plastic production (P27256) electrically
programmable read-only memory (EPROM). Organized as 32K words by 8 bits, individual bytes can be accessed in less than 170 ns (27256-1). This is compatible with high performance microprocessors, such as the
Intel iAPX 186, allowing full speed operation without the addition of performance-degrading WAIT states. The
27256 is also directly compatible with Intel's 8051 family of microcontrollers.
The Plastic P27256 is ideal for high volume production environments where code flexibility is crucial. Plastic
packaging is also well-suited to auto-insertion equipment in cost-effective automated assembly lines. Intel's
new Quick-Pulse Programming Algorithm enables the P27256 to be programmed within four seconds (plus
programmer overhead). Programming equipment which takes advantage of this innovation will electronically
identify the EPROM with the help of the inteligent Identifier and rapidly program it using a superior programming method. The inteligent Programming Algorithm may be utilized in the absence of such equipment.
The 27256 enables implementation of new, advanced systems with firmware-intensive' architectures. The
combination of the 27256's high-density, cost-effective EPROM storage, and new advanced microprocessors
having megabit addressing capability provides designers with opportunities to engineer user-friendly, high
reliability, high-performance systems.
The 27256's large storage capability of 32 K-bytes enables it to function as a high-density software carrier.
Entire operating systems, diagnostics, high-level language programs and specialized application software can
reside in a 27256 EPROM directly on a system's memory bus. This permits immediate microprocessor access
and execution of software and elminates the need for time-consuming disk accesses and downloads.
Two-line control and JEDEC-approved, 28-pin packaging are standard features of all Intel high-density
EPROMs. This assures easy microprocessor interfacing and minimum design efforts when upgrading, adding,
or choosing between nonvolatile memory alternatives.
The 27256 is manufactured using Intel's advanced HMOS*II-E technology.
"HMOS is a patented process of Intel Corporation.
DATA OUTPUTS

0.-0,

A14

- AoADDRESS
INPUTS

~~:::::!..J~-~
Y.(lATING

262,144 BIT
CELLMAmlX

290097-1

Figure 1. Block Diagram

5-38

September 1989
Order Number: 290097-004

inter

27256

Pin Names

2764A
27C64
87C64

27512
27C512

27128A
27C128

AIS
A12
A7

A.
A2
Al
AD
00
01
02

Vpp
A12
A7
As
AS
A4
A.
A2
Al
AD
00
01
02

Vpp
A12
A7
As
As
A4
A.
A2
Al

GND

As
AS

Pv.

2732A

Ao-A14

Addresses

Chip Enable

Output Enable

00-0 7

Outputs

N.C.

No Connect

27256
P27256

2716

2732A

Ye e

Vee
PGM

A"
A7.

As
AS

Pv.

A7
As
AS
A4

A2
Al

00
01
02

A2
Al
AD
00
01
02

GND

A,
Au

DE
0,
00
0,

0&
O!l

GND""L.:....-_....:.;;rO,

2764A
27C64
87C64

Vee
As

Vpp
OE
AID

eE
07
06
Os
04
O.

27182A
27C128

27512
27C512

Vee

Vee
A14
AI.
As
A9
All
OElVpp
AID

PGM

Vee
As
Ag
Al1
OElVpp
AID

N.C.
As
A9
All
AID

AI.
As
A9
All
OE
AID

07
06
Os
04
O.

07
Os
Os
04
O.

, 290097-2

NOTE:
Intel"Universal Site"-Compatible EPROM pin configurations are shown in the blocks adjacent to the P27256 pins.

Figure 2_ Cerdip/Plastic DIP Pin Configuration

5-39

intJ

27256

available with 168 ± 8 hour, 125·C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROM operating temperature range is O·C to 70·C. Extended operating temperature range (- 40·C to + 85·C) EXPRESS products are available. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.

EXPRESS EPROM PRODUCT FAMILY

EXPRESS OPTioNS

PRODUCT DEFINITIONS

27256 VERSIONS

EXTENDED TEMPERATURE
(EXPRESS) EPROMs

Operating
Temperature
O·Cto +70·C
- 40·C to + 85·C
- 40·C to + 85·C

Type
Q
T
L

Packaging Options
Speed
Cerdip
Versions
-20
Q,T,L

Burn-In
125·C (hr)
168 +8
None
168 +8

READ OPERATION

D.C. CHARACTERISTICS
Electrical parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for·
Symbol
ISB
leel 1)

Parameter
Vee Standby Current (rnA)
Vee Active Current (mA)

TD27256
LD27256
Min
Max
50
125

Test Conditions
CE = VIH,OE = VIL
OE = CE = VIL

NOTE:
1. The maximum current value is with outputs 00 to 07 unloaded.

30 Jo'S

AOfiJ1.I
A1ILJ
.
•

AU
Binary Sequence from Ao !o A14

OE ~ +5V
Vpp ~ +5V

290097-9
R ~ 1 kG
Vr::&..~ +5V
Vss ~ GND
CE ~ GNp

Burn·ln Bias and Timing Diagrams
5-40

290097-10

27256

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature
During Read .................... O°C to + 70°C

Temperature Under Bias ......... -10°C to + BO°C
Storage Temperature .......... -65°C to + 125°C
All Input or Output Voltages with
Respect to Ground ........... - 0.6V to + 6.25V
Voltage on Pin 24 with
Respect to Ground ........... - 0.6V to + 13.5V
Vpp Supply Voltage with Respect
to Ground ................... - 0.6V to + 14.0V
Vee Supply Voltage with
Respect to Ground ............ -0.6V to + 7.0V

READ OPERATION
D.C. CHARACTERISTICS
Symbol

Parameter

O°C ::;: TA ::;: + 70°C

27256·1,27256·2,
27256·20, P27256-2
Limits
Min

Typ(3)

Max

27256·25, 27256,
P27256-25,P27256
Limits
Min

Typ (3)

Test
Conditions

Unit

Max

III

Input Load Current

p.A VIN = OV to Vee

ILO

Output Leakage
Current

p.A VOUT

IpPl(2)

VppCurrent
Read/Standby

mA Vpp

IS8(2)

Vee Current Standby

mA CE = VIH

leel(2)

Vee Current Active

125

100

mA CE = OE = VIL
Vpp = Vee

VII':.

Input Low Voltage

-0.1

+0.8

-0.1

+O.B

VIH

Input High Voltage

2.0

Vee + 1

2.0

Vee + 1

VOL

Output Low Voltage

0.45

VOH

Output High Voltage

2.4

Vpp(2)

Vpp Read Voltage

3.B

0.45
2.4
Vee

5-41

3.8

Vee

OV to Vee

5.5V

IOL = 2.1 mA

IOH = -400p.A

Vee = 5.0V±0.25V

inter

27256

READ OPERATION

A.C. CHARACTERISTICS

O°C

VCC±5%

s: + 70°C

27256-1

Versions(5)
Vcc±10%
Symbol

Parameter

Min

Max

27256-2
P27256-2

27256
P27256

27256-20

27256-25
P27256-25

Min

Max

Min

Test
Conditions

Unit

Max

tACC

Address to Output
Delay

170

200

250

tCE

CE to Output Delay

170

200

250

tOE

OE to Output Delay

100

VIL

tOF(4)

OE High to Output
Float

=
=
=

tOH(4)

Output Hold from
Address, CE or OE
Whichever
Occurred First

VIL

NOTES:

1. VCC must be applied simultaneously or before Vpp and removed Simultaneously or after Vpp.
2. Vpp may be. connected directly to Vee except during programming. The supply current would then be the sum of ICC and
Ipp. The maximum current value is with outputs 00 to 07 unloaded.
3. Typical values are for TA = 25°C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested. Output Data Float is defined as the point where. data is no longer
driven-see timing diagram.
5. Packaging Options: No prefix = Cerdip; P = Plastic DIP.

CAPACITANCE(2) (TA =

25°C, f

1 MHz)

Typ(l)

Max

Unit

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT

Symbol

Parameter

Conditions

NOTES:
1. TA = 25°C, Vcc

= S.OV.
2. This parameter is only sampled and is not 100% tested.

A.C. TESTING INPUT/OUTPUT WAVEFORM

A.C. TESTING LOAD CIRCUIT
1.3V

~N."
3.3KII
DEVICE
UNDER
TEST

290097-3

I---+---QOUT

:::

100 pi

290097-4

A.c. Testing; Inputs are Driven at 2.4V for a Logic "1" and 0.4SV
for a Logic "0". Timing Measurements are made at 2.0V for a
Logic "1" and O.BV for a Logic "0".

CL = 100 pF
CL Includes Jig Capacitance

5-42

inter

27256

A.C. WAVEFORMS
VIH - - - - - - - - . .

• •••

·...

ADDRESS
VALID

ADDRESSES
VIL------~

VIH

--------+_

• •••

VIL

VIH

--------+---"""

i'----f- ••••

VIL

1"7"""',.-,10- • • • • --oI-r......l

----++-t+<

OUTPUT _ _ _ _ _.....;H~I;:;;GH.;..;;.Z

HIGH Z

~~~-

••••

--~.4f

290097-5
NOTES;
1. Typical values are for T A = 25'C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. DE may be delayed up to teE-tOE after the falling edge of CE without impact on teE.

Table 1. Operating Modes
Pins CE OE

DEVICE OPERATION

Vpp Vcc

The modes of operation of the 27256 are listed in
Table 1. A single 5V power supply is required in the
read mode. All inputs are TTL levels except for Vpp
and 12V on A9 for inteligent identifier mode.

Outputs

Mode
Read

VIL VIL X(1)

Output Disable

VIL VIH

X Vee 5.0V HighZ

Standby

VIH X

X Vee 5.0V HighZ

Programming

VIL VIH

(4)

DIN

Program Verify

VIH VIL· X

(4)

Dour

Optional Program
Verify

VIL VIL

X Vee (4)

Dour

Program Inhibit

VIH VIH

HighZ

X Vee 5.0V

(4)

Dour

Read Mode
The P27256 has two control functions, both of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to
gate data from the output pins, independent of device selection. Assuming that addresses are stable,
the address access time (tACe) is equal to the delay
from CE to output (tCE). Data is available at the outputs after a de~ of tOE from the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tACC-tOE.

a9H(5)
inteligent Identifier(3)
-manufacturer
VIL VIL VH(2) VIL 5.0V 5.0V aaH(S)
-device

VIL VIL VH(2) VIH 5.0V 5.0V

04H

NOTES;
1. X can be VIH or VIL.
2. VH = 12.0V±0.5V.
3. A1-Ae. A10-A13 = VIL. A14 = VIH·
4. See Table 2 for Vee and Vpp voltages.
5. The manufacturers identifier reads a9H for Cerdip
EPROMs; aaH for Plastic EPROMs.

Standby Mode
EPROMs can be placed in a standby mode which
reduces the maximum current of the devices by applying a TTL-high signal to the CE input. When in
standby mode, the outputs are in a high impedance
state, independent of the OE input.

5-43

27256

Two Line Output Control
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 control lines which
accommodate this multiple memory connection. The
two control lines allow for:

The device is in the programming mode'when Vpp is
raised to its programming voltage (see Table 2) and
CE is at TIL-low. The data to be programmed is
applied 8 bits in parallel to the data output pins. The
levels required for the address and data inputs are
TIL.

a) the lowest possible memory power dissipation,
and

Program Inhibit

b) complete assurance that output bus contention
will not occur.

Programming of multiple EPROMs in parallel with
different data is easily accomplished by using the
Program Inhibit mode. A high-level CE input inhibits
the other devices from being programmed.

Except for CE, all like inputs of the parallel EPROMs
may be common. A TIL low-level pulse applied to
the CE input with Vpp at its programming voltage will
program the selected device.

Program Verify
SYSTEM CONSIDERATIONS

A verify should be performed on the programmed
bits to determine that they have been correctly programmed. The verify is performed with OE at VIL, CE
at VIH, and Vpp and Vee at their programming voltages.

The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed
by complying with Intel's Two-Line Control and by
properly selected decoupling capacitors. It is recommended that a 0.1 /LF ceramic capacitor be used on
every device between Vee and GND. This should be
a high frequency capacitor of low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 /LF bulk electrolytic
capacitor should be used between Vee and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effects of PC board traces.

Optional Program Verify
The optional verify may be performed in place of the
verify mode. It is performed with OE at VIL, CE at VIL
(as opposed to the standard verify which has CE at
VIH), and Vpp at its programming voltage. The outputs will tri-state according to the signal presented
to OE. Therefore, all devices with '{eE. = 12.75V
(12.5V inteligent programming) and OE = VIL will
present data on the bus independent of the CE
state. When parallel programming several devices
which share a common bus, Vpp should be lowered
to Vee (= 6.25/6.0V-see Table 2) and the normal
read mode used to execute a program verify.

inteligent IdentifierTM Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device.

inter

27256

To activiate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO from VIL to VIH. All other address lines
must be held at VIL during inteligent Identifier Mode.

sure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the EPROM is to be
exposed to these types of lighting conditions for extended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.

Byte 0 (AO = Vld represents the manufacturer code
and byte 1 (AO = VIH) the device identifier code.
These two identifier bytes are given in Table 1.

The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 }LW/cm2 power rating. The EPROM should be placed within 1 inch of
the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000
}LW/cm2). Exposure of the device to high intensity
UV light for long periods may cause permanent damage.

5-45

intJ

27256

290097-6

Figure 3. Quick-Pulse Programming™ Algorithm
been successfully programmed. Up to 25 100 IJ.s
pulses per byte are provided before a failure is recognized. A flowchart of the Quick-Pulse Programming Algorithm is shown in Figure 3.

Quick·Pulse Programming™ Algorithm
(For Plastic EPRONis)
Intel's Plastic EPROMs can now be programmed using the Quick-Pulse Programming Algorithm, developed by Intel to substantially reduce the throughput
time in the production programming environment.
This algorithm allows Plastic devices to be programmed in under four seconds, almost a hundred
fold improvement over previous algorithms. Actual
programming time is a function of the PROM pro, grammer being used.

For the Quick-Pulse Programming Algorithm, the entire sequence of programming pulses and byte verifications is performed at Vee = 6.25V and Vpp at
12.75V. When programming of the EPROM has
been completed, all bytes should be compared to
the original data with Vee = Vpp = 5.0V.
In addition to the Quick-Pulse Programming Algorithm, Plastic EPROMs are also compatible with Intel's inteligent Programming Algorithm.

The Quick-Pulse Programming Algorithm uses initial
pulses of 100 microseconds followed by a byte verification to determine when the address byte has

5-46

inter

27256

DEVICE

FAILEO

DEVICE

FAILED

290097-8

Figure 4. inteligent Programming™ Flowchart
pulse of length 3X msec. X is an iteration counter
and is equal to the number of the initial one millisecond pulses applied to a particular location, before a
correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram
pulse is applied.

inteligent Programming™ Algorithm
The inteligent Programming Algorithm has been a
standard in the industry for the past few years. A
flowchart of the inteligent Programming Algorithm is
shown in Figure 4.
The inteligent
different pulse
duration of the
which will then

The entire sequence of program pulses and byte
verifications is performed at Vee = 6.0V and
Vpp = 12.SV. When the inteligent Programming cycle has been completed, all bytes should be compared to the original data with Vee = Vpp = 5.0V.

Programming Algorithm utilizes two
types: initial and overprogram. The
initial CE pulse(s) is one millisecond,
be followed by a longer overprogram

5-47

27256

TABLE 2. D.C. PROGRAMMING CHARACTERISTICS
Symbol

Parameter

III

Input ClIrrent (All Inputs)

VIL

Input Low Level (All Inputs)

25 ±5°C

Limits
Min

Max

Unit

10
-0.1

0.8

/LA
V

2.0

Vee
0.45

VIN

10L

10H

= 2.1 mA
= -400,...A

VIL

=
=

VIL

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH
lee2(4)

Output High Voltage During Verify
Vee Supply Current (Program & Verify)

125

IpP2(4)

Vpp Supply Current (Program)

VID
Vpp

Aginteligent Identifier Voltage

11.5

12.5

Vee

Test Conditions
(see Note 1)
VIL or VIH

2.4

in\aligent Programming Algorithm

12.0

13.0

Quick-Pulse Programming Algorithm

12.5

13.0

in\aligent Programming Algorithm

5.75

6.25

Quick-Pulse Programming Algorithm

6.0

6.5

VIL

A.C. PROGRAMMING CHARACTERISTICS
TA = 25 ± 5°C (see table 2 for Vee and Vpp voltages)

Symbol

Limits

Parameter
Min

Typ

Max

Unit

tAS

Address Setup Time

/Ls

toES
tDS

OE Setup Time

/Ls

Data Setup Time

,...S

tAH

Address Hold Time

/Ls

tDH

Data Hold Time

tDFP

OE High to Output
Data Float Delay

tvps

Vpp Setup Time

tves

Vee Setup Time

tpw

CE Initial Program Pulse Width

topw

CE Overprogram Pulse Width

toE

Data Valid from OE

Test Conditions'
(Note 1)

/Ls

130

(Note 3)

/Ls

0.95

1.0

1.05

100

105

2.85

/Ls

/Ls
ms

78.75

/Ls
ms

150

inteligent Programming
Quick-Pulse Programming
(Note 2)

NOTES:

• A.C. CONDITIONS OF TEST

1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp.
2. The length of the overprogram pulse may vary from
2.85 msec to 78.75 msec as a function of the iteration
counter value X (inteligent Programming Algorithm only).
3. This parameter is only sampled and is not 100% tested.
Output Data Float is defined as the point where data is no
longer driven-see timing diagram on the following page.
4. The maximum current value is with outputs 00 to 07 unloaded.

Input Rise and Fall Times
(10% to 90%) ............................. 20 ns
Input Pulse Levels .................. O.45V to 2.4V
Input Timing Reference Level.: .•... O.8Vand 2.0V
Output Timing Reference Level ...... O.8V and 2.0V

5-48

intJ

27256

PROGRAMMING WAVEFORMS
!-------IPROGRAM------.;..e----- P~~~:~M-----I
ADDRESSES

HIGHZ

DATA

12.75V/12.5V(4)

8.25VILOVC4j
Vee
S.Oy

CE
V"
tOES

to.

V,"

CE
V"

290097-7

NOTES:
1. The input timing reference level is 0.8V for a VIL and 2V for a VIH.
2. toE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the 27256 a 0.1 p.F capacitor is required across Vpp and ground to suppress spurious voltage tranI
sients which can damage the device.
4. 12.75V Vpp & 6.25V Vee for Quick-Pulse Programming Algorithm. 12.5V Vpp & 6.0V Vee for inleligent Programming
Algorithm.

REVISION HISTORY
Number

Description

Revised Pin Configuration. Revised Express options.
Deleted -3, -30, -5, L-2, L-20 and L-1 speed bins.
D.C. Characteristics -Ill Conditions are VIN = OV to VeeD.C. Characteristics -ILO Conditions are VOUT = OV to Vee.

5-49

27C256
256K (32K x 8) CHMOS EPROM
• High Speed
- 120 ns Access Time

• EPI Processing
- Maximum Latch-up Immunity

• Low Power Consumption
-100 p,A Standby, 30 mA Active

• Simple Interfacing
- Two Line Control
- CMOS and TTL Compatible

• Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as 4
Seconds

• Versatile JEDEC-Approved Packaging
,
- Standard 28-Pin CERDIP
- Compact 32-Lead PLCC
- Cost Effective Plastic DIP
(See Packaging Spec.,

Or~er

#231369)

Intel's 27C256 is a 5V only, 262,144-bit Erasable Programmable Read Only Memory, organized as 32,768
words of 8 bits. Its standard pinouts provide for simple upgrades to 512 Kbits in the future in both DIP and
SMT.
The 27C256 is ideal in embedded control applications based on advanced 16-bit CPUs. Fast 120 ns access
times allow no-wait-state operation with the 12 MHz 80286. The 27C256 also excels in reprogrammable
environments where the system designer must strike an optimal density/performance balance. For example,
bootstrap and diagnostic routines run 1-wait-state on a 16 MHz 386™ microprocessor.
Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic dip
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic dip (PDIP) one-time programmable part provides a lower cost alternative
that is well adapted for auto insertion.
In addition to the JEDEC 28-pin DIP package, Intel also offers a 32-lead PLCC version of the 27C256. This
one-tirne-programmable surface mount device is ideal where board space consumption is a major concern or
where surface mount manufacturing technology is being implemented across an entire production line.
The 27C256 is equally at home in both TTL and CMOS environments. The Quick-Pulse programming™
algorithm improves speed as much as 100 times over older methods, further reducing cost for system manufacturers.
DATA OUTPUTS

vcc-

0 0-0,

GND_

vpp_

Y-GATING

AcrAl. {
ADDRESS
INPUTS

212,144 BIT
CELLMATAIX
290044-1

Figure 1. Block Diagram

5-50

September 1990
Order Number: 290044-010

27C256

Pin Names
AO-:"A15

ADDRESSES

00- 0 7

OUTPUTS

OUTPUT ENABLE

CE
PGM

CHIP ENABLE
PROGRAM

NO CONNECT

DON'T USE

27512

27128A

2764A

27C512

27C128

27C64

A1s

Vpp

vpp

vcc

A12

A14
A13

Vee

All

A10

2732A

27C256

2716

°7

°0

°6

°1

°5

°2

GND

°4
03

GND

2732A

27C64 27128A

27512

27C64 27C128

27C512

Vee

PGM

A14

Vee

Ala

Vpp

A11

All

OElVpp

Al0

AIO

Al0

Cl:

290044-2

Figure 2. DIP Pin Configuration
27C64

32 LEAD PLCC
0.4S0" X 0.550"
(11.430 X 13.970)
(MILLIMETERS)
TOP VIEW

290044-10

Figure 3. PLCC Lead Configuration

5-51

27C256

EXTENDED TEMPERAtURE
(EXPRESS) EPROMs

EXPRESS EPROM FAMILY
PRODUCT DEFINITIONS

The . Intel. EXPRESS EPROM family receives addi·
tional .processing to enhance product characteristics. EXPRESS processing is available for several
densities allowing the appropriate memory size to
match system requirements. EXPRESS EPROMs
are available with 168 ±8 hour, 125·C. dynamic
burn-in using Intel's standard bias configuration.
This processing meets or exceeds most industry
burn-in specifications. The EXPRESS product .family
is available in both O·C to 70·C and - 40·C to 85·C
operating temperature range versions. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0: 1% electrical AQL. This allows reduction or
elimination of incoming testing.

Operating
Temperature ("C)

Burn-In 12S·C (hr)

O·Cto 70·C

168 ±8

- 40·C to 85·C

NONE

- 40·C to 85·C

168 ±8

Type

Options
Packaging

Speed
CERDIP

PLCC

PDIP

-120V10

Q,T,L

-200V10

Q,T,L

290044-12
R=lKO.Vcc=+5V
Vpp = +5V GND = OV CE = GND

~=+5V

Binary Sequence from Ao to A14

290044-13

Burn-In Bias and Timing Diagrams

5-52

intJ

27C256

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature ............. O·C to 70·C(1)

Temperature Under Bias .......•... -1 O·C to BO·C
Storage Temperature ............. -65·C to 125·C
Voltage on Ar)Y Pin (except Ag, Vee and Vpp)
with Respect to GND ......•....• ; - 2V to 7V(2)
Voltage on Ag with
Respect to GND ....•.......... -2V to 13.5V(2)
Vpp Supply Voltage
with Respect to GND ........... - 2V to 14.0V(2)
Vee Supply Voltage with
Respectto GND ................ -2V to 7.0V(2)

READ OPERATION DC CHARACTERISTICS(1)
Symbol

Parameter

III

Input Load Current

ILO

Output Leakage Current

ISB

Vee Standby Current

Notes

Min

Vee = 5.0V ±10%

Typ

Max

Unit

Test Condition

0.01

1.0

J.l.A

VIN = OVtoVee

±10

J.l.A

VOUT = OV to Vee

1.0

CE = VIH

100

J.l.A

CE = Vee ±0.2V

lee

Vee Operating Current

CE = VIL
f = 5 MHz

Ipp

Vpp Operating Current

200

p.A

Vpp = Vee

los

Output Short Circuit Current

100

VIL

Input Low Voltage

-0.5

O.B

VIH

Input High Voltage

2.0'

VOL

Output Low Voltage

VOH

Output High Voltage

Vpp

Vpp Operating Voltage

4,6

Vee

+ 0.5

0.45

V
V

IOL =2.1 mA

2.4

IOH= -400 J.l.A

Vee - 0.7

NOTES:
1. Operating temperature is for commercial product defined
by this specification. Extended temperature options are
available in EXPRESS versions.
2. Minimum De voltage is -O.SV on input/output pins. During transitions, this level may undershoot to - 2.OV for periods <20 ns. Maximum DC voltage on input/output pins is
Vee + O.SV which, during transitions, may overshoot to
Vee + 2.OV for periods <20 ns.
3. Maximum active power usage is the sum Ipp + Icc.
Maximum current value is with outputs 00 to 07 unloaded.

Vee

4. Output shorted for no more than one second. No more
than one output shorted at a time.
s. Vpp may be connected directly to Vee, or may be one
diode voltage drop below Vee. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
6. Sampled, not 100% tested.
7. Typical limits are at Vee = SV, TA = 2SoC.

5-53

intJ

27C25S·

READ OPERATION AC CHARACTERISTICS(1) vcc
Vee ±10%
Versions(4)
Symbol

Parameter

tACC

Address to Output Delay

teE

CE to Output Delay

toE

Notes

27C256-120V10
P27C256-120V10
N27C256-120V10
Min

Max

5.0V ± 10%
27C256-150V10
P27C256-150V10
N27C256-150V10
. Min
Max

27C256-200V10
P27C256-200V10
N27C256-200V10 Unit
Min

Max

120

150

200

120

150

200

OE to Output Delay

tOF

OE High to Output High Z

tOH

Output Hold from Addresses, CE or
OE Change-Whichever is First

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to tCE-toE after the falling edge of CE without impact on tCE'
3. Sampled, not 100% tested.
4. Package Prefixes: No Prefix = CERDIP; N = PLCC; P = PDIP.

5-54

ns
ns

27C256

AC WAVEFORMS

V,H-----...,.
ADDRESS
VALID

ADDRESSES

V,, _ _ _ _ __

V,H

---------l-""

V,H

---------l----...,.

V,l

'D_

V,H
O~ftITS

HIGH Z

_ _ _ _ _ _H~I~GH~Z~_ _ _ _ _~~~~~

V,l

290044-5

CAPACITANCE(1)TA
Symbol

= 25°C,

f = 1.0 MHz

Parameter

Max

Units

CIN

Address/Control Capacitance

COUT

Output Capacitance

, pF

Conditions

VIN

= OV

VOUT

= OV

NOTE:

1. Sampled, not 100% tested.

AC INPUT/OUTPUT REFERENCE WAVEFORM

AC TESTING LOAD CIRCUIT
1.3V
-~

2.4
0.45

2.0>
0.8

____

TEST POINTS _____

2.0

~~ 1N914

OUTPUT

,0;;:;.8=--_ _

290044-9
DEVICE
AC test inputs are driven at VOH (2.4 VTTI) for a logic "1" and
VOL (0.45 VTTU for a logic "0". Input timing begins at VIH (2.0
VTTU and VIL (O.B VTTU. Output timing ends at VIH and VIL. Input
rise and fall times (10% to 90%) :>:10 ns.

UNDER
TEST

t--+--oOUT

CL = 100 pF
CL Includes Jig Capacitance

RL = 3.3 KI1

5-55

290044-3

inter

27C256

DEVICE OPERATION
The Mode Selection table lists 27C256 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, and Ag 'during inteligent Identifier Mode, are TIL or CMOS.
Table 1. Mode Selection
Notes

Vpp

Vee

Outputs

VIL

Vee

Vcc

DOUT

Output Disable

VIL

VIH

Vcc

HighZ

Standby

VIH

Vcc

HighZ

Mode
Read

VIL

VIH

Vpp

Vcp

DIN

Program Verify

VIH

VIL

Vpp

VCP

DOUT

Program Inhibit

VIH

Vpp

Vcp

HIGHZ

Program

inteligent Identifier
-Manufacturer

2,3

VIL

VIO

VIL

Vcc

89H

inteligent Identifier
-Device

2,3,4

VIL

VIO

VIH

Vcc

8DH

NOTES:
1. X can be VIL or VIH.
2. See OC Programming Characteristics for VCP, Vpp and VIO voltages.
3. Al-Aa, Al0-14 = VIL·
4. Programming equipment may also refer to this device as the 27C256A. Older devices may have device 10 = eCHo

Read Mode
The 27C256 has two control functions, both must be
. enabed to obtain data at the ~uts. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (teE). Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.
'

To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.

Standby Mode
StandbLMode substantially reduces Vcc current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.

Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.

5-56

intJ

27C256

allows upgrade using the Vpp pin. Systems designed
for 256 Kbit program memories today can be upgraded to 512 Kbit in the future with no circuit board
changes.

Program Mode
Initially, an.d after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "O's" into the desired bit locations. Although only "O's" are programmed, the data word
can contain both "1's" and "O's". Ultraviolet light
erasure is the only way to change "O's" to "1's".

SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (ISB), active current levels (Icc>, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-Line Control and proper decoupling capacitor
selection will suppress trarisient voltage peaks.
Each device should have a 0,·1 ,...F ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,...F electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.

Program Mode is entered when Vpp is raised to
12.75V. Data is introduced ~applying an 8-bit word
to the output pins. Pulsing CE low while OE = VIH
programs that data into the device.

Program Verify
A vertfy should be performed following a prcigrar:n
operation to determine that bits have been correctly
programmed. With Vee at 6.25V a substantial pro~m margin is ensured. The verify is performed with
CE at VIH. Valid data is available tOE after OE falls
low.

Program Inhibit
Program Inhibit Mode allows parallel prQg!"amming
of multiple EPROMs with different data. CE-high inhibi!!Progr!!!!ming of non-targeted devices. Except
for CE and OE, parallel EPROMs may have common
inputs.

ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter .than approximately 4000
Angstroms (A). It should be rioted that sunlight and
certain flourescent lamps have wavelengths in the
3000A-4000A range, Data shows that constant exposure to room level. fluprescent lighting can erase
an EPROM in approximately 3 years, while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.

lritaligent Identifler™ Mode
The. inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programrriing algorithm.
This mode is activated when ~rogrammer forces
12V + 0.5V on Ag. With CE; DE, A1-Aa, and A10A14 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± SoC ambient temperature
range required during programming.

UPGRADE PATH
Future upgrade to the 512 Kbit density is easily accomplished due to the standardized pin configuration of the 27C256. A jumper between A15 and Vee

The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity exposure time) for erasure should be a minimum of 15 Wsec/cm 2 . Erasure
time is approximately 1S to 20 minutes using an ultraviolet lamp with a ~2000 ,...W/cm2 power rating.
The EPROM should be piaced within 1 inch of the
lamp tubes. An EPROM can be permanently
damaged if the integrated dose exceeds
. 7258 Wsec/cm2 (1 week @ 12000 ,...W/cm2 ).

5-57

inter

27C256

,290044-:11

Figure 4.,Quick-Pulse Programmlng™ Algorithm
The Quick-Pulse programniing algorithm employs a
100 p.s pulse followed by a byte verification to determine when the addressed byte has been sucessfully
programmed. The algorithm terminates if 25 attempts fail to program a byte.

Quick-Pulse Programming™
Algo,rithm
',
The Quick-Pulse Programming' algorithm programs
Intel's 27C256. Developed to substantially reduce
programming throughput, this algorith[T1 ca'n program
the 27C256 as fast as 4 seconds. Actual programming time depends on programmer overhead,
'

'The entire program pulse/byte verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all bytes are compared to th,e original data with Vee = Vpp = 5.0V.

5-58

27C256

DC PROGRAMMING CHARACTERISTICS
Symbol

Parameter

Notes

25"C ±5°C

Min

III

Input Load Current

Icp

Vcc Program Current

Ipp

Vpp Program Current

V,L

Input Low Voltage

-0.1

V,H

Input High Voltage

2.4

VOL

Output Low Voltage (Verify)

Typ

Max

Unit

Test Condition

1.0

,...A

Y,N = V,L or V,H

rnA

CE = V,L

rnA

CE = V,L

0.8

6.5

0.45

IOL = 2.1 rnA

IOH = -2.5 rnA

VOH

Output High Voltage (Verify)

3.5
11.5

12.0

12.5

2,3

12.5

12.75

13.0

6.0

6.25

6.5

V'O

A9 Inteligent Identifier Voltage

Vpp

Vpp Program Voltage

Vcp

Vcc Supply Voltage (Program)

AC PROGRAMMING CHARACTERISTICS(4)
Symbol

Parameter

TA = 25°C ±5°C

Notes

Min

tvcs

Vcp Setup Time

Typ

,...s

tvps

Vpp Setup Time

,...s

tAS

Address Setup Time

,...s

Max

Unit

tDS

Data Setup Time

tpw

CE Program Pulse Width

tOH

Data Hold Time

,...s

tOES

OE Setup Time

,...s

toE

Data Valid from OE

tOFP

OE High to
Output High Z

tAH

Address Hold Time

5
5,6

0
0

,...s
100

105

,...s

150

130

ns
,...s

4. See AC Input/Output Reference Waveform for timing
measurmenlS.
5. tOE and tOFP are device characteristics but must be accommodated by the programmer.
6. Sampled,. ~.ot 100% tested.

NOTES:
1. Maximum current value"is with outputs 00 to 07 unloaded.
2. Vep must be applied simu'itaneously or before Vpp and
removed simultaneously or after Vpp.
3. When programming, a 0.1 ,.,.F capacitor is required
across Vpp and GNO to suppress spurious voltage transients which can damage the device.

5-59

r-------------------------------------------------------------------------------,I~

~
~

~
~
.~
Inlellgent Identilier

-ManufactuAr

Blank Check
"'egal Bit Check

'I'

Program

'I'

~~m

Read Verify

'2.OV
VII

. Add ....
VL

Ao=V'L

<
m
~

ADDRESS SlABl£

VII

Data

vI.
t2.75Y

(11

•.av-

Vpp

N
CI'I

.Q)

I.25Y

•.avVee

v.,

CE
VL

toE
v.,

.DE
vL
290044-8

inter

27C256

REVISION HISTORY
Number

Description

010

Revised general datasheet structure, text to improve clarity
Revised ISB Test Condition from CE = Vee to CE = Vee ± 0.2V
Revised VOH from 3.5V to 2.4V, IOH from -2.5 mA to -400 p.A
Deleted 512K PLCC pinout references
Deleted -150V10, -2, -20, -STD and -25 EXPRESS offerings
Added -120V1 0, - 200V1 0, PLCC and PDIP EXPRESS offerings
Deleted -20, -25 and all 5% Vee speed bins
Added PLCC and PDI P -120 speed bin packages

5-61

27C512
512K (64K x 8) CHMOS EPROM,
• Low Power
- 30 mA Max. Active
"";"100 p.A Max. Standby

• Software Carrier Capability
•

120 ns Access Time

• Two-Line Control
• Inteligent Identifier™ Mode
- Automated Programming Operations
• CMOS and TTL Compatible

• Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as 8
Seconds

The Intel 27C512 is a 5V-only, 524, 288-bit Erasable Programmable Read Only Memory (EPROM), organized
as 65,536 words of 8 bits. Individual bytes are accessed in 120 ns. This ensures compatibility with high-performance microprocessors, such as the Intel 12 MHz iAPX 286, allowing full speed operation without the
addition of performance-degrading WAIT states. The 27C512 is also directly compatible with Intel's 80C51
family of microcontrollers.
The 27C512 enables implementation of new, advanced systems with firmware intensive architectures. The
combination of the 27C512's high-density, cost-effective EPROM storage, and new advanced microprocessors having megabyte addressing capability provides designers with opportunities to, engineer user-friendly,
high-reliability, high-performance systems.
The 27C512's large storage capability of 64 K-bytes enables it to function as a high-density software carrier.
Entire operating systems, diagnostics, high-level language programs and specialized application software can
'reside in a 27C512 directly on a system's memory bus. This permits immediate microprocessor access and
execution of software and eliminates the need for time-consuming disk accesses and downloads.
Intel's Quick-Pulse Programming™ algorithm enables the 27C512 to be programmed as fast as eight seconds
(plus programmer overhead). Programming equipment which takes advantage of the inteligent IdentifierTM will
electronically identify the EPROM and automatically program it using a superior programming method.
Two-line control and JEDEC-approved, 28-pin packaging are standard features of the 27C512. This assures
easy microprocessor interfacing and minimum design efforts when upgrading, adding, or choosing between
nonvolatile memory alternatives.
CHMOS is a patented process of Intel Corporation.

DATA OUTPUTS

0.-0,

Y.QAnNQ

ADDRESS
ActA" {

524,288-BIT
CELL MATRIX

INPUTS

290228-1

Figure 1. Block Diagram

5-62

October 1990
Order Number: 290228-003

inter

27C512
Pin Names

Ao-A15
CE
OElVpp
PGM
00-0 7
NC

ADDRESSES
CHIP ENABLE
OUTPUT ENABLElVpp
PROGRAM
OUTPUTS
NO CONNECT
27C512

27256 27C12B 2764A
2732A 2716
27C256 2712BA 27C64

Vpp
A12
A7
A6
A5
A4
A3
A2
A1
Ao
00
01
02
GND

Vpp
A12
A7
A6
A5
A4
A3
A2
Al
AO
00
01
02
GND

2716 2732A

A15
A12
A7
As
A5

Vee
A1"
A13
As
Ag

A7
A7
A6
A6
A5
A5
A4
A4
A"
A3
A3
A3
A2
A2
A2
Al
Al
Al
AO
Ao
Ao
00
00
°0
01 01
°1
O2 O2
°2
GND GND GND

All
OE/Vpp
A10
CE
°7
Os
°5
0"

°3

290228-2
Figure 2. DIP Pin Configuration

5·63

2764A 27C12B 27256
27C64 27128A 27C256

Vee
PGM
NC
Vee Vee
As
As
A8
Ag
A9
A9
Vpp All
All
OE OE/vpp OE
AlO AlO
Al0
CE
CE
CE
07
07
07
06
06
06
05
05
05
04
04
04
03
03
03

Vee
PGM
A13
As
Ag
All
OE
AlO
CE
07
06
05
04
03

Vee
A14
A13
As
Ag
All
OE
AlO
CE
07
06
05
04
03

27C512

EXTENDED TEMPERATURE
(EXPRESS) EPROMs

EXPRESS EPROM FAMILY

The Intel EXPRESS EPROM family receives additional processing to enhance product characteristics. EXPRESS processing is available for several
densities allowing the appropriate memory size to
match system requirements. EXPRESS EPROMs
are available with 168 ±8 hour, 125"C dynamic
burn-in using Intel's standard bias configuration.
This processing meets or exceeds most industry
burn-in specifications. The EXPRESS product family
is available in both O"C to 70"C and - 40·C to 85·C
operating temperature range versions. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AQL. This allows reduction or
elimination of incoming testing.

PRODUCT DEFINITIONS
Operating
Type
Temperature
O·Cto 70"C
Q
-40"C to 85"C
T
-40·C to 85"C
L

Burn-In
12S"C {hr}
168 ± 8
None
168 ± 8

OPTIONS
Packaging

I
I

Speed
-120V10

CERDIP
Q,T,L

READ OPERATION DC CHARACTERISTICS
Electrical parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for:
Symbol

TD27CS12(2)
LD27CS12

Parameter

Min
Icel 1)

Test Condition

Max

Vcc Operating Current (mA)

. OENpp = CE = V,L

Vcc Operating Current
at High Temperature (mA)

OENpp = CE = V,L
TAmbient = 85·C

NOTE:
1. The maximum current value is with outputs 00 to 07 unloaded.

2. C refers to the CERCIP package.
30 J.'s

A0S-UU·
A1FL-r
•
•

A 15

290228-5

Binary sequence from

OElVpp
GND =

= +5V
R = 1 kO
ov eE = GND

vee =

290228-4
+5V

Burn-In Bias and Timing Diagrams

5-64

A() to A15

27C512

ABSOLUTE MAXIMUM RATINGS·
Operating Temperature .....•..... O·C to

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

+ 70·C(I)

+ SO·C
+ 125·C

Temperature Under Bias •....•... - 1O~C to
Storage Temperature .......... -65·C to

All Input or Output Voltages
(except A9, Vee and Vpp)
.
with Respect to GND .......... - 2.0V to 7.0V(2)
Voltage on A9 with
Respect to GNP ............. - 2.0V to 13.5V(2)
Vpp Supply Voltage
with Respect to GND ........... - 2.0V to 14V(2)
Vee Supply Voltage
with Respect to GND .......... - 2.0V to 7.0V(2)

READ OPERATION DC CHARACTERISTICS(1)
Symbol
III

Parameter
Input Load Current

Notes

Min

Vee = 5.0V ±10%

Typ

Max

Unit

0.01

1.0

,...A

Test Condition

+ 5.5V
OV to + 5.5V

VIN = OV to

ILO

Output Leakage Current

±10

,...A

VOUT =

ISB

Vee Standby Current

1.0

CE =

100

,...A

CE = Vee ±0.2V

lee

Vee Operating Current

rnA

CE = VIL
f = 5 MHz, lOUT = 0 rnA

Ipp

Vpp Operating Current

,...A

Vpp.= Vee

los

Output Short Circuit
Current

4,6

100

rnA

VIL

Input Low Voltage

-0.5

O.S

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

Vee

+ 0.5

0.45

VIH

V
V

10L = 2.1 rnA

Output High Voltage
2.4
V
10H = -400,...A
VOH
NOTES:
1. Operating temperature is for commercial product definE!d by this specification. Extended temperature options are available
in EXPRESS versions.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which during transitiops, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. ~aximum active power usage is the sum Ipp + ICC. Maximum current value is with outputs 00 to 07 unloaded.
4. Qutput shorted for no more than onl1 second. No more than one output shorted at a time.
5. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
6. Sampled, not 100% tested.
'
7. Typical limits are at Vee = 5V, TA = 25°C.

5-65

inter

27C512

READ OPERATION AC CHARACTERISTICS Vee = 5.0V ±10%

vee ± 10%

Versions(4)
Symbol

Parameter

27C512-120V10
Notes

Min

tAce

Address to
Output Delay

teE

CE to Output Delay

toE

OElVpp
to Output Delay

tDF

OElVppHigh
to Output High Z

tOH

Output Hold from
Addresses, CE or
OElVpp, Whichever
Occurred First

Max

27C512-150V10
Min

Max

120

150

120
55
30

27C512-200V1Q
Min

Max

Unit

200

150

200

NOTES:
1. See AC input/output reference waveform for .timing measurements.
2. DE may be delayed up to tCE-toE after the falling edge of eE without impact on tCE.
3. Sampled, not 100% tested.
4. Packaging Options: No Prefix = CERDIP.
5. Typical values are for T A = 25°e and nominal supply voltages.

CAPACITANCE(3) TA = 25°C, f = 1 MHz
Typ(5)

Max

Unit

Condition

CIN

Input Capacitance

VIN = OV·

COUT

Output Capacitance

VOUT = OV

COElVpp

OElVpp Capacitance

VIN= OV

Symbol

Parameter

AC INPUT/OUTPUT REFERENCE WAVEFORM

AC TESTING LOAD CIRCUIT

2.:3:!,.

2.4
2.0 ' - TEST POINTs . 0.45

0.5-

2.00UlPUT

~ .. lN914

~0;:::.5~_

290228-6

RL
DEVICE
UNDER
TEST

NOTE:
AC test inputs are driven at VOH(2.4 VTnJfor a Logic
"1" and VOL (0.45 VnU for a Logic "0". Input timing
begins at VIH (2.0 VnU and VIL (0.8 VnU. Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) s; 10 ns.

OUT
. l CL

CL = 100 pF
CL includes Jig Capacitance
RL;'" 3.3 kO

5-66

290228-7

inter

27C512

AC WAVEFORMS
VIH - - - - - - -

ADDRESS
VALID

ADDRESSES
VIL - - - - - - - - '

VIH - - - - - - - - - + _ , .

Cf
VIL

VIH--------+--~

OE/Vpp
VIL

+H+<

OUTPUTS _ _ _ _ _~H::.::IG;.:.H.:.Z_ _ _ _

HIGH Z

290228-8

DEVICE OPERATION
The Mode Selection table lists 27C512 operating
modes. Read Mode requires a single 5V power supply. All inputs, except Vcc and OElVpp, and Ag during inteligent Identifier Mode, are TTL or CMOS.

Table 1. Mode Selection
Mode

Notes

Read

VIL

VIH

VIL

Vpp

Output Disable
Standby
Program

OE/Vpp

Outputs

Vee

Vcc

DOUT

Vcc

HighZ

Vcc

HighZ

Vcp

DIN

.Ag

Program Verify

. VIL

VIL

Vcp

DOUT

Program Inhibit

VIH

Vpp

VCP

HighZ

VIL

VID

VIL

Vcc

89H

VIL

VID

VIH

Vcc

FDH

Inteligent
Identifier

- Manufacturer
-Device.

2,3

NOTES:

1. X can be VIH or VIL.
2. See DC Programming Characteristics for Vep. Vpp and
3. A1-A8. A10-A15 = VIL.

VID

voltages.

5-67

27C512

Read Mode
The 27CS12 has two control functions; both must be
!'lnabled to obtain data at the 0Y!E.uts. CE is the pow,
er .ponteol and device select. OElVpp controls the
P4tput buffers to gate data to t~e outputs. With addresses stable, the address access time (tACe)
~~uals the del~y from CE to output (teE), Outputs
~Isplay valid data toE after OElVpp's falling' edge,
~~~ming tACC and teE times are met.
.
~ m~st

g@m margin is ensured. The verify is performed with
OElVpp at VIL. Valid data is available tov after CE
falls low.
"

Program Inhibit
Program Inhibit Mode ~lIows parallel pr2ll!'amming
of multiple EPROMs with different data. CE-high in~
hibit.!.Programming of non-targeted devices. Except
for CE and OElVpp, parallel EPROMS may have
common inputs.

be applied sImultaneously or before

QE/Vpp and removed simultaneously or after

OE/Vpp.

Stan~by

Mode

StandbLMoqe substantially reduces Vee current.
W/len C~ = VIH, the outputs are in a high i",pedarce state, independent of OElVpp:
'.
.

T!l0 Line Output Control
EF,ROMS are often used in larger memory arrays.
Intel provides two control inputs to accommodate
rlllJltiple memory connections. Two-line control pro"
vidEls for:
~) !ow~st possible memory power dissipation
b) pomplete assurance that data bus contention will
. , not occur
.

To. $fficiently

use these two control inputs, an adqi-ess decoder should enable CE, ~hile OElVpp
snould be connected to all memory qevices and the
sy§tem's READ control line. This assure!l that only
!!elepted memory devices have actiVe outpu1!l while
de~elected memory devices are. in Stardby Mode.

progrljlm Mode
Csl!tlOf1: Exi:esdlng 14.0Von (JE1Vep will Pflrrna-

.",htly damage the device.

!nt~ligent

Initially, and after each erasure, all EPROM bits are
irr the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. AIthdljgh only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light era~~re'ls the only way to change "OSi;' to "1s".

This mO,de is activated when I!..£fogrammer forces
12V ± O.SV on A9. With CE, OElVpp, A1-AB and
A10-A15 at VIL, Ao = VIL wi'l present the manufacturer code and Ao = VIH the device cpde. This
mode functions in the 2SoC' ± SoC ambient tempera'
ture range reguired during programming.

SYSTEM CONSIDERATIONS
EPROM power switching ,characteristics require
careful device decouj:lling. System designers are interested in 3 supply current issues: standby current
levels (ISB), active' current levels (Ice), and transient
curren!.E.eaks produced by the falling and rising edges of CE. Transient current magnitudes depend on
the device output's capacitive and inductive loading.
Two-line control and proper decoupling capapitor
selection will suppress' transient volta,ge peaks.
, Each device should have a 0.1 ,..,F ceramic capacitor
connected between its Vcc and GND. This high fre~
quency, low inherent-inductance capaCitor 'should
be placed as close as possible to the device. AdditiOnally for every 8 devices, a 4.7 ,..,F electrolytic capacitor should be placed at the array's power supply
connection between Vcc and GND. The bIJlk capacitor will overcome voltage slumps caused by PC
board trace inductances.

ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
wavelengths shorter than approximately 4000
Angstroms (A). It should be noted'that sunlight and
certain fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase an
EPROM in approximately 3 years, while it takes approximately 1 week when exposed to direct sunlight.
If the device is exposed to these lighting conditions
for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
wi~h

P.rogram Mode is entered when OElVpp is raised to
1~t7PV. Data is introduced by~pll{ing an 8 bit word
to t~t3 output "ins. Pulsing CE low programs that
d~ta into the device.
.

Pr~~ram

Verify

A veiify should be performed following a program

9per~fion to determine that bits have been correctly
prQgr~lilmed. With Vce at 6.2SV, a substantial pro"!

,.'

Identifier Mode

The 'inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.

S-68

27C512

290228-9

Figure 3. Quick-Pulse Programming Algorithm

The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537 A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 p.W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsec/
cm 2 (1 week @ 12000 p.W/cm2).

programming throughput, this algorithm can program
the 27C512 as fast as "8 seconds. Actual programming time depends on the programmer overhead.
The Quick-Pulse Programming algorithm employs a
100 p.s pulse followed by a byte verification to determine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.
The entire program pulse/byte verify sequence is
performed with Vee = 6.25V. OElVpp toggles between 12.75V and VIL for program and verify operations. When programming is complete, all bytes are
compared to the original data with Vee = 5.0V.

Quick-Pulse Programming Algorithm
The Quick-Pulse Programming algorithm programs
Intel's 27C512. Developed to substantially reduce
5·69

27C512

DC PROGRAMMING CHARACTERISTICS
Symbol

Parameter

III

Input Load Current

Notes

± 5°C

T A = 25

Min

Typ

Max

Unit

p.A

VIN = VIL or VIH

Test Condition

ICp

V CC Program Current

CE= VIL,OElVpp = Vpp

Ipp

Vpp Program Current

CE = VIL,OElVpp = Vpp

VIL

Input Low Voltage

-0.1

0.8

VIH

Input High Voltage

2.4

6.5

VOL

Output Low Voltage (Verify)

0.45

IOL = 2.1 mA

VOH

Output High Voltage (Verify)

3.5

IOH = -2.5mA

11.5

12.0

12.5

2,3

12.5

12.75

13.0

6.0

6.25

6.5

VIO

Ag inteligent Identifier Voltage

Vpp

Vpp Program Voltage

Vcp

Vcc Supply Voltage (Program)

AC PROGRAMMING CHARACTERISTICS(4) T A =
Symbol

Parameter

± 5°C

Notes

Min

P.s

OElVpp Pulse Rise Time
During Programming

tvcs

Vcp Setup Time

tpRT

Typ

Max

Unit

tAS

Address Setup Time

p.s

tos

Data Setup Time

P.s

tOES

OElVpp Setup Time

tpw

CE Program
Pulse Width

tOH

Data Hold Time

fJ-s

tOEH

OElVpp Hold Time

fJ-s

tVR

OElVpp Recovery Time

tov

Data Valid from CE

tOFP

Output Disable to Output High Z

tAH

Address Hold Time

2,3

5
5,6

0
0

p.s
100

105

p.s

fJ-s

130

ns
fJ-s

NOTES:

1. Maximum current value is with outputs 00 to 07 unloaded.
2. VCP must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
3. When programming, a 0.1 ).tF capacitor is required across OElVpp and GNO to suppress spWious voltage transients
which can damage the device.
4. See AC Input/Output Reference Waveforms for timing measurements.
5. tDV and tDFP are device characteristics but must be accommodated by the programmer.
6. Sampled, not 100% tested.

5-70

inter

27C512

PROGRAMMING WAVEFORMS
~----PROGRAM---__~~r'~-

VIH
ADDRESSES

ADDRESS STABLE

VIL
VIH
DATA

VIL

6.25V
Vee
S.OV

12.15V
OElVpp
VIL
IpAT

VIH
CE

VIL

290228-10

REVISION HISTORY
Description
Deleted preliminary classification.

5-71

27513
PAGE-ADDRESSED 512K (4 x 16K x 8)
UV ERASABLE PROM
•

Paged Organization
- Reduced Physical Address
Requirement
- No Bank Switching Logic Needed

•

Software Carrier Capacity

•

Automatic Page Clear
- Resets to Page 0 on Power Up and
On Demand with RST Signal(1)

•

TTL and CMOS Compatible

•

170 ns Access Time

•

Two Line Control

•

Low Power
-125 mA max. Active
- 40 mA max. Standby

•

Compatible with Industry Standard
EPROM Pinouts
- Direct 27128A Compatibility
- 28-Pin Cerdip

The Intel 27513 is a 5V-only, 524,288-bit ultraviolet Erasable and Electrically Programmable Read Only Memory. It is organized as 4 pages of 16K 8-bit words. The 27513's paged organization brings 64 K-byte storage
capacity to existing 128K EPROM-based designs arid to popular 8-bit microprocessor or microcontroller systems that have 64 K-byte total addressing capability. The 27513 provides an ideal means of quadrupling
current 16 K-byte code space.
The 27513's large storage capability of 64 K-bytes and 170 ns access time enables it to function as a high
density software carrier. Entire operating systems, diagnostics, high-level language programs and specialized
application software can reside in a 27513 EPROM directly on a system's memory bus. This permits immediate microprocessor access and execution of software and eliminates the need for time-consuming disk accesses and downloads.
The 27513 has an automatic page clear circuit for ease of use of the page-addressed organization. The pageselect latch is automatically cleared to the lowest order page upon system power up.
Two-line control and industry standard 28-pin packaging are features common to all Intel high-density
EPROMs. This assures easy microprocessor interfaCing and minimum design efforts when upgrading, adding,
or choosing between nonvolatile memory alternatives.
The 27513 is manufactured using Intel's Compacted HMOS· II technology.
NOTE:
1. RST feature only available on devices with 6-digit suffix.

5-72

September 1989
Order Number: 231113-007

27513

D,U,lilIITJ

I
I

Vee 0 - GND 0----

PAGE SELECT
LOGIC

1
Ce
OilY,.

PRDGRAU

Oe ...HDC!
'LOQIC

OUTPUT
BUFFERS

III V,6

ADD~~::JjI
X
INPUTS j
•
DECODE"

OECOO£R

r¥'
•

¥GATlNQ
121,(172

CELL MATRIX

......
......
......

L.J
~--,J

..... ,

231113-5

Figure 1. Block Diagram
2764A

~716 2732A 27C64
87C64

27128A 27256 27512
27C128 27C256 27C51~
Vpp
A12
A7

Vpp
A12
A7

A15
A12
A7

A7
A6
A5

Vpp
A12
A7

A3
A2
Al

A3
A2
Al
AO
00
01
02

A4
A3

,Ao

00
01
02

GND

00
01
02

~ND GND GND GND

27512 27256 27128A
27C512 27C25E 27C128

27513
Vee

Vee
A14
A13

WE
A"

...
...

A"
iji/yPP

A2
Al

As
Ail
All

2732A 271E

1!7C6~

Vee

PID;1

PGM

A13
A8
A9
All

N,C.

As
A9
All

Vee
A8
A9
Al1

l:5E

OE PEIVPF i5E

.1\10

Al0

07
06
05
04
03

07
06
()5
04
03

~
06
05
04
03

07
06
05
04
03

Os
Os
04

Figure 2. Pin Configuration

1. Intel "Universal Site" compatible EPROM pin configurations are shown in the blocks adjacent to the 27513 pins.

Pin Name.
Addresses

AO-A15
CE

Chip Enabie

OElVpp

Output EnablelVpp

Page·Select Write Enable

02-0 7

Outputs

Do/00,Dl /01

Input/Outputs

RST

Page Reset(l)

5-73

A9
Vpp

,0.10

231113-6

NOTE:
1. RSi' feature only available on devices with E!-digit suffix.

Al0

NOTES:

Vee

PEIVPF

--...._ _ _ _ _r-"

27C6~

0,,0,

Vee
A14
A13
A8
A9
All

2764A

inter

27513

:The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM,allowing
the choice of appropriate memory size to match system applications. EXPRESS EPROM products are

available with 168 ± 8 hour, 125·C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burri-in. The standard EXPRESS EPROM operating temperature range is O·C to 70·C. Extended operating temperature range (-40·C to + 85·C) EXPRESS products are available. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected·
to 0.15 electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.

EXPRESS EPROM PRODUCT FAMILY

EXPRESS OPTIONS

PRODUCT DEFINITIONS
Type Operating Temperature Burn-in 12S·C (hr)
O·Cto +70·C
·168 +8
Q
-40·C to + 85·C
T
None
-40·C to + 85·C
168 ±8
L

27513 VERSIONS
Packaging Options
Speed Versions
Cerdlp
1
-200V10
Q,L,T
.1

EXTENDED TEMPERATURE
(EXPRESS) EPROMs

READ OPERATION
D.C. CHARACTERISTICS
•
Electrical Parameters of Express EPROM Products are identical to standard EPROM parameters except for'
Symbol

Parameter
Vee Standby Current (rnA)
Vee Active Current (rnA)
Vee Active Current
at High Temperature (rnA)

ISB
lee1(1)

NOTE:
1. The maximum current value is with outiluts 00 to

TD27513
LD27S13
Min
Max
50
150
125

Test Conditions
CE = VIH, OElVpp = VIL
OElVpp = CE = VIL

a: = VIL, TAmbient: = 85·C

OElVpp ;"

0, unloaded.

30 }.IS

AoIlIlJ

'.• r L J

Voc

vee

°7
0.

°0
°1
°2

+5V

R = 1 KIl

vss = GND

A15

0.
03

Binary Sequence from Ao to A15
231113-9

aE:lVpp

Vee = +sv

= GND
Burn-In Bias and Timing Dill9rams

5-74

231113-10

27513

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature
During Read .................... O°C to + 70°C
Temperature Under Bias ......... -10°C to + 80°C
Storage Temperature .......... - 65°C to + 125°C
All Input or Output Voltages with
Respect to,Groundt ........... - 0.6V to + 6.5V
Voltage on Pin 24 with
Respect to Ground ........... - 0.6V to + 13.5V
OElVpp Supply Voltage with
'
Respect to Ground ........... - 0.6V to + 14.0V
Vee Supply Voltage with
Respect to Ground ............ - 0.6V to + 7.0V

,t includes Don't Connect (pin 1)

READ AND PAGE-SELECT WRITE OPERATIONS
D.C. CHARACTERISTICS O°C ~ T A ~ + 70°C
Symbol

Limits

Parameter
Min

Test
Conditions

Units

Typ(2)

Max

III

Input Load Current

p.A

VIN

ILO
158(4)

Output Leakage Current

p.A

VOUT

Vee Current Standby

lee1(4)

Vee Current Active

125

VIL

Input Low Voltage

-0.1

+0.8

VIH

Input High Voltage

2.0

VOL

Vee+ 1
0.45

Output Low Voltage

VOH

Output High Voltage

VeLR

Page Latch Clear
Vee Supply Voltage

20
90

2.4
3.5

4.0

IOL

V
V,

IOH

=
=

OVtoVee

OV to Vee

VIH
OElVpp

VIL

= 2.1 mA
= -400 p.A

READ OPERATION
A.C. CHARACTERISTICS O°C ~ T A ~

+ 70°C

Vcc ±5%

27513·170V05

27513·2 '
27513·200V05

27513

Vee ±10%

27513·170V10

27513·20
27513-200V10

27513·25

Verslons(5)
"

Symbol

Parameter

Min

Max

Min

Max

Min

Units

Test
Conditions

CE = OElVpp = VIL

Max

tAcc

Address to Output Delay

170

200

250

teE

CE to Output Delay

170

200

250

OElVpp = VIL

tOE
tDF(3).

OElVpp to Output Delay

100

CE = VIL

OElVpp High to
Output Float

eE = VIL

toH

Output Hold from
Addresses eE or OElVpp,
Whichever Occurred First

eE = OElVpp = VIL

0
0

5-75

0
0

•

27513

PAGE-SELECT WRITE AND PAGE-RESET OPERATION

A.C. CHARACTERISTICS
Symbol

Limits

Parameter

Min

tew

'CE to End of Write

twp

Write Pulse Width

tWR

Write ReC9very Time

tos

Data Setup Time

tOH

Data Hold Time

los

cE to Write Setup Time

tWH

WE Low from OE/Vpp High

Test
Conditions

Units

Max

180
100
20
50
20
0
55

OE/vpp

OE/Vpp = VIH

VIH

=
=
OE/Vpp =

ns
ns
ns

oE/Vpp

VIH

OE/Vpp

VIi-!
VIH

Delay Tiine
tRsT

Reset l.:ow Time

tRAv

Reset to Address Valid

250
250

ns
ns

NOTES:

1. Vee must be applied simultaneous.IY or before 'OElVpp and removed simultaneously or after 'OElVpp.
2. Typical values are for TA "" 25°C and nominal supply voltages.
3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
4. The maximum current value is with outputs 00-07 unloaded.
5. Packaging Options: No prefix = Cerdip; P "'" Plastic DIP; N = PLCC.
6. AST function is available only on parts with 6-digit suffix.

CAPACITANCE(2hA = + 25°C, f = 1 MHz
Typ(1)

Max

Units

Input Capacitance

COUT

Output Capacitance

12
25

VOUT

OE/Vpp Capacitance

8
18

CoElVpp'

VIN

Symbol
CIN

Param,ter

C,ondltlons
,VIN

A.C. TESTING LOAD CIRCUIT

A.C. TESTING INPUT/OUTPUT WAVEFORM

1N914

2 ••

2.0___

3.3KII

_ _ TEST POINTS
0.4$

0.8

DEVICE
UNDER
TEST

231113-1

AC Testing Inputs are driven a12.4V for a Logic 1 and O.45V for a
logic O. Timing measurements are made al 2.0V for a logic 1
and O.SV for a Logic O.

1----+---0 OUT

;131113-2
CL = 100 pF
CL Includes Jig Capacitance

5-76

27513

A.C. WAVEFORMS FOR READ OPERATION
V'H _ _ _ _
ADDRESSES
VIL _ _ _- J

ir--------ADORESS

VALID
1'-_ _ _ _ _
_ __

-+_

V'H _ _ _ _

V~----~---~

OilY""
VIL

OUTPUT _ _ _ _-=HIGH~Z_ _ __i+i:+i~

HIGH

VM _ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _~~_ _ __

231113-3

VIL

A.C. WAVEFORMS FOR PAGE-SELECT WRITE OPERATION
ADllII2SS
DON'T CARE

ADORESSES

c;; _ _ _ _ _ _ _'"\. j4'_ _ _ _ 1cw(4( _ _ _ _. .

WE----------~

"r"I"I'~mT't"nT

1wP(41--t:~~::!---

llIIv,. _ _ _ _ _-'1

Do/Oa. D,/O,

11>-0,

INPUT/OUTPUTS

outPUTS _ _ _ _...:::HI::;,GH:.,:Z_ _ _ _ _ _ _ _ _ _ _ _ _ _...;.._

231113-4

5-77

inter

27513

A.C. WAVEFORMS FOR PAGE-RESET. OPERATIONS

::::J<.....__.;.A.;.DD;;..R.;;E.;.SS~DO.;.N_'T....;.;CA..;..R.;;E

~_
......~;;..AD;.;D.;..R.;..ES;.;S;..V.;.;.A.;;L.;.ID_

_____.{:tRST .V_-t-RA-V-==:r------231113-12

NOTES:
1. Typical values are for TA = + 25"C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE/vpp may be delayed up to tCE-tOE after the falling edge of CE without impact on leE.
4. Write may be terminated by either CE or WE, providing that the minimum lew requirement is met before bringing WE high '
or that the minimum twp requirement is met before bringing CE high.
5. OElVpp must be high during write cycle.

DEVICE OPERATION
The modes of operation of the 27513 are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for OElVpp and 12V on A9 for inteligent Identifier mode.
Table 1. Operating Modes
Pins

Inputl
Outputs

OE/Vpp

RST

Vee

Read

VIL

VIH

X(1)

5.0V

DOUT

Output Disable

VIL

VIH

Vec

HighZ

Standby

VIH

Vce

HighZ

Programming

VIL

Vpp(3)

VIH

(Note 3)

DIN

(Note 3)

Outputs

Mode

Verify

VIL

VIH

DOUT

Program Inhibit

VIH

Vpp(3)

VIH

(Note 3)

HighZ

Page-Select
Write

VIL

VIH

VIL

VIH

Vec<5)

HighZ

Page(2)

Page-Reset

VIL

"cd

HighZ

VIL

VIH

VH(7)

VIL

5.0V

89H

VIL

VIH

VH(7)

VIH

5.0V

OFH(6)

inte ligent(4) -Manufacturer
Identifier
-Device

DIN
5)

NOTES:
1. X can be VIH or VIL.
2. Addresses are don't care for page selection. See Table 2 for DIN values.
3. See Table 2 for Vcc and Vpp voltages.
4. A1-Aa, A10-A13, = VIL.
·5. Page 0 is automatically selected at power-up (Vcc < 4.0V).
6. 27513s before 2H/86 have a device identifier of ODH. 27513s after 2H/86 will have a device identifier of OFH.
7. VH = 12.0V ±0.5%.

5-78

27513

Read Mode

Page Reset

The 27513 has three control functions, two of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OElVpp) is the output control and should be used
to gate data from the output pins, independent of
device selection. Assuming that addresses are stable, the address access time (tAccl is equal to the
delay from CE to output (tCE). Data is available at
the outputs after a delay ofJQE from the falling edge
of OElVpp, assuming that CE has been low and addresses have been stable for at least tACC-tOE. WE
is held high during read operations.

The 27513 has an automatic page latch clear circuit
to ensure consistent page selection during system
bootstrapping. The page latch is automatically
cleared to page 0 upon power-up. As the Vcc supply
voltage ramps up, the page latch is cleared. After
Vcc exceeds the 4.0V maximum page latch clear
voltage (VCLR), the latch clear circuit is disabled.
rhis ensures an adequate safety margin (500 mV of
system noise below the worst case -10% Vcc supply condition) against spurious page latch clearing.
27513 parts with 6-digit suffixes also have a page
reset pill: RST. This pin should be tied to an active
low system reset signal. These 27513s will be reset
to page 0 when this line is brought to TTL Low (VILl.

Standby Mode
Two Line Control

The 27513 has a standby mode which reduces the
maximum active current from 125 mA to 40 mA. The
27513 is placed in the standby mode by applying a
TTL-high signal to the CE input. When in standby
mode, the outputs are in a high impedance state,
independent of the OElVpp and WE inputs.

Because EPROMs are usually used in larger memory arrays, Intel has provided 2 output control lines
which accommodate this multiple memory connection. The two control lines for read operation allow
for:
a) the lowest possible memory power dissipation,
and,
b) complete assurance that output bus contention
will not occur.

Page-Select Write Mode
The 27513 is addressed by first selecting one of four
16 K-byte pages. Individual bytes are then selected
by normal random access within the 16 K-byte page
using the proper combination of Ao-A13 address inputs. By applying a TTL low signal to the WE fnput
with CE low and OE high, the desired page is
latched in according to the combination of 00/00
and 01/01. Address inputs are "don't care" during
page selection.

To use these two control lines most efficiently, CE
should be decoded and used as the primary device
selecting function, while OElVpp should be made a
common connection to all devices in the array and
connected to the READ line from the system control
bus. This assures that all deselected memory devices are in their low power standby mode and that the
output pins are active only when data is desired from
a particular memory device.

Care should be taken in organizing software programs such that the number of page changes is minimized. This allows maximum system perforniance.
Also, the processor's program counter status must
be considered when page changes occur in the middle of an opcode sequence. After a page-select
write, the program counter will be incremented to the
next location (or further in pipelined systems) in the
new page relative to that of the page-select write
opcode in the previous page.

Similarly, CE deselects other 27513s or RAMs during page select write operation while WE is in common with other devices in the array. WE is connected to the WRITE system control line.

SYSTEM CONSIDERATIONS
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced' by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed
by complying with Intel's Two·Line Control and by

Table 2. Page Selection Data
Input/Output
(Pin)
Page Selection

01/0 1
(12)

00/0 0
(11)

Select Page 0
Select Page 1
Select Page 2
Select Page 3

VIL
VIL
VIH
VIH

VIL
VIH
VIL
VIH
5-79

27513

properly selected decoupling capacitors. It is recommended that a 0.1 p.F ceramic capacitor be used on
every device between Vee and GND. This should be
a high frequency capacitor of low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 p.F bulk electrolytic
capacitor should be used between Vee and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effects of PC board traces. This inductive effect
should be further minimized through special layout
considerations such as larger traces and gridding
(refer to High Speed Memory System Design Using
the 2147H, AP-74). In particular, the Vss (Ground)
plane should be as stable as possible.

PROGRAMMING
Caution: Exceeding 14.0 V on OE/Vpp will permanently damage the 27513.
Initially, and after each erasure, all bits of the
EPROM are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations. Although only "Os" will be programmed,
both "1s" and "Os" can be present in the data word.
The only way to change a "0" to a "1" is by ultraviolet light erasure.

Except for CE, all inputs of the parallel 27513s may
be common. A TTL low-level pulse applied to the CE
input with OElVpp at its programming voltage will
program the selected 27513.

Verify

A verify (read) should be performed on the programmed bits to determine that they have been correctly pro9@.mmed. The verify is performed with OEI
Vpp and CE at VIL and Vee is at its programming
voltage. Data should be verified tov after the falling
edge of CEo

inteligent Identifier™ Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufcturer and type. This mode is intended for use
by programming equipment for the purpose of automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming
the device.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
Mode.

The EPROM is in the programming mode when the
OElVpp input is raised to its programming voltage
(see Table 2) and CE is at TTL-low. The data to be
programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and
data inputs are TTL.

Byte 0 (AO = VII) represents the manufacturer code
and byte 1 (AO = VIH) the device identifier code.
These two identifier bytes are given in Table 1.

Program Inhibit
Programming of multiple 27513s in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE input inhibits the
other 27513s from being programmed.

5-80

27513

DEVICE
FAILED

231113-7

Figure 5. 27513 Intellgent Programmlng™ Flowchart

5-81

inter

27513

ERASURE CHARACTERISTICS
The erasure characteristics are such that erasure
begins to occur upon exposure to light with wave'lengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and, certain
wpes of fluorescent lamps have wavelengths il) the
3000-4000 A range. Data show that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the device is to be exposed to these types of lighting conditions for ex,tended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.

the lamp tubes during erasure. The maximum inte, grated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000
p,W/cm2). Exposure of the device to high intensity
UV light for long periods may cause permanent damage.

inte.ligent Programming™
ALGORITHM
The inteligent Programming Algorithm programs
Intel EPROMs using an efficient and reliable method
Plirticularly suited to the production programming
environment. Typical programming times for individual devices are on the order of six minutes. Actual
Programming times may vary due to differe\1ces in
programming equipment. Programming reliability is
also ensured as the incremental program margin of
each byte is continually monitored to determine
when it has been successfully programmed. A flowchart of the 27513 inteligent Programming Algorithm
is shown in Figure 3. The only difference between
the 27513 and other EPROM inteligent Programr:ning is that the 27513 is programmed one 16 K-byte
page at a time.

The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
'of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
this dosage is approximately 15 to 20 minutes using
an ultravioletlamp with a 12000 p,W/cm2 power rating. The EPROM should be placed within 1 inch of

TABLE 2. D.C. PROGRAMMING CHARACTERISTICS
TA

25°C ±5°C

Symbol

Limits

Parameter

III

Input Current (All Inputs)

VIL

Input low level (All Inputs)

VIH

Input High level

VOL

Output low Voltage During Verify

VOH
lee2(2)

Output High Voltage During Verify

Min

Max

Units

p,A

-0.1

0.8

2.0

Vee + 1
, '0.45

2.4

Test Conditions
(Note 1)
VIN

10L

10H

= 2.1 rnA
= -400 p,A

VIL or VIH

Vee Supply Current
(Program and Verify)

125

rnA

Ipp:i(2)

Vpp Supply Current (Program)

rnA

VIO
Vpp

Ag inteligent Identifier Voltage

11.5

12.5

inteligen~

Programming Algorithm

12.0

13.0

Vee

inteligent Programming Algorithm

5.75

6.25

CE = VIL,
OElVpp = Vpp

NOTES:
.
1. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp:
2. The maximum current value is with outputs 00-07 unloaded.

5-82

intJ

27513

correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram
pulse is applied. The entire sequence of program

The inteligent Programming Algorithm utilizes two
different pulse types: initial and overprogram. The
duration of the initial pulse(s) is one millisecond,
which will then be followed by a longer overprogram
pulse of length '3X msec. X is an iteration counter
and is equal to the number of the initial one millisecond pulses applied to a particular location, before a

pulses and byte verifications Is performed at
Vee = 6.0V. When the in1eligent Programming cycle has been completed, a" bytes should be compared to the original data with Vee = 5.0V.

A.C. PROGRAMMING CHARACTERISTICS
TA = 25°C ±5°C
Symbol

limits

Parameter
Min

Typ

Max

Units

tAS

Address Setup Time

,""S

toES

OElVpp Setup Time

,""S

tos

Data Setup Time

,""S

tAH

Address Hold Time

,""S

tOH

Data Hold Time

tOFP

Output Enable to Output Float Delay

tves

Vee Setup Time

tpw

CE Initial Program Pulse Width

0.95

topw

CE Overprogram Pulse Width

2.85

tOEH

OElVpp Hold Time

tov

Data Valid from CE

tVR

OElVpp Recovery Time

,""S

tpRT

OElVpp Pulse Rise Time
During Programming

Conditions'
(Note 1)

,""S
ns

(Note 3)

,""S

(Note 1)

1.05

inteligent Programming

78.75

(Note 2)

130

1.0

,""S
1

,""S

NOTES:
1. Vce must be applied simultaneously or before OElVpp
and removed simultaneously or after OElVpp.
2. The length of the overprogram pulse (inleligent Programming Algorithm only) may vary from 2.85 ms to 78.75 ms
as a function of ,the iteration counter value X.
3. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no longe,r driven-see timing diagram.

• A.C. CONDITIONS OF TEST
Input Rise and Fa" Times (10% to 90%) ...... 20 ns
Input Pulse Levels .................. 0.45V to 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 2.0V

5-83

intJ

27513

PROGRAMMING WAVEFORMS

)(

..-K

ADDRESS STABLE

.... IAS ......

VIH

DATA IN STABLE

DATA

14-1086.OV

Vcc
S.OV

.Ioy.

I-IOH

{iVCS.

1Z.5V

OE/Vpp

IPRT-I

DATA OUT VALID
_IAH
~IOFP

~ES--

+-IOEH-

I-IVR-+t
~

...

~to.....

VIH------------------------------------____________________________
VIL
231113-8

NOTES:
1. The Input Timing Reference Level is O.BV for a VIL and 2.0V for a VIH.
2. toE and tOFP are characteristics of the d~ice but must be accommodated by the programmer.
3. The proper page to be programmed must be selected by a page-select write operation prior to programming each of the
four 16 K-byte pages. See Page Select Write AC and DC Characteristics for information on page selection operations.

REVISION HISTORY
Number

Description

Revised Express Options
Revised Pin Configuration
D.C. Characteristics-Ill Test Conditions-VIN = OV to Vee
D.C. Characteristics-ILO Test Conditions-VOUT= 0" to Vee

5-84

27C513
PAGE-ADDRESSED 512K (4 x 16K x 8)
UV ERASABLE PROM

•

•
•
•

Paged Organization
- Reduced Physical Address
Requirement
- No Bank Switching Logic Needed

Carrier Capacity
• Software
Automatic Page Clear

•
•

•

- Resets to Page 0 on Power Up and
On Demand with RST Signal
TTL and CMOS Compatible

170 ns Access Time
Two Line Control
Low Power
- 30 rnA max. Active
-100 #LA max. Standby
Compatible with Industry Standard
EPROM Pinouts
- Direct 27128A Compatibility
- 28-Pin Cerdip

The Intel 27C513 is a 5V-only, 524,288-bit ultraviolet Erasable and Electrically Programmable Read Only
Memory. It is organized as 4 pages of 16K 8-bit words. The 27C513's paged organization brings 64 Kbyte
storage capacity to existing 128K EPROM-based designs and to popular 8-bit microprocessor or microcontroller systems that have 64 Kbyte total addressing capability. The 27C513 provides an ideal means of quadrupling current 16 Kbyte code space.
'The 27C513's large storage capability of 64 Kbytes and 170 ns access time enables it to function as a high
density software carrier. Entire operating systems, diagnostics, high-level language programs and specialized
application software can reside in a 27C513 EPROM directly on a system's memory bus. This permits immediate microprocessor access and execution of software and eliminates the need for time-consuming disk accesses and downloads.
The 27C513 has an automatic page clear circuit for ease of use of the page-addressed organization. The
page-select latch is automatically cleared to the lowest order page upon system power up.
Two-line control and industry standard 28-pin packaging are features common to all Intel high-density
EPROMs. This assures easy microprocessor interfacing and minimum design efforts when upgrading, adding,
or choosing between nonvolatile memory alternatives.
The 27C513 is manufactured using Intel's 1 micron CHMOS· III-E technology.

CHMOS is a patented process of Intel Corporation.

5-85

October 1990
Order Number: 290231-002

inter

27C513

DATA
INPUTI
OUTPUTS

D.U.'(RSl')
Vee

I
I

0-----:.

GNO 0------+

l l

PAGE SELECT

LOGIC

DATA
OUTPUTS

DO/O~1/0, ~~

BUFFERS

A''''':=:I X,I, ,b

V-GATING

PROGRAM

CE AND Ce
LOGIC

OelVpp

ADDRESS

INPUTS

DECODER

OUTPUT

DECODER
y

131,072

CELL MATRIX

L
E

PAGE 0

L.J

PAGE 1

L,J

PAGE 2

PAGE 3

290231-1

Figure 1. Block Diagram
27C64
27C128 27C256 27C512 27C011
2732A 2764A
27128A 27256 27512 27011
87C64
Vpp

Vpp

. Vpp

A'2
A7
AS
AS
A4
A3
A2
A,
AD
00
0,
02

A'2
A7
AS
AS
A4
A2
A,

A'2
A7
AS
AS
A4
A3
A2
A,

00
0,
02

A3
A2
A,
AD
00
0,
02

GNO GNO

GNO

A7
AS
AS
A4
A3
A2
A,

As
00
0,
02

A,S
A'2
A7

As
As
~

27C64
27C011 27C512 27C256 27C128
27C64A 2732A
27011
27512 27256 27128A
87C64

27C513

Vpp/RST

Yee

A'2
A7
Ae
AS
A4
A3
A2
A,
AD

A'0

07
Os
Os
04
03

07
Oe
Os
04
03

07
Os
Os
04
03

Oe/VPP

DolCe

0, 10,

0,10,

02102

GND

--..-----....-

Vee
PGM
N.C
As
Ag
Al1
DE

00100

GNO

Vee
PGM
A3
'
As
Ag

A"
DE
AlO

Vee
A'4
A'3

Vee
As
Ag
Al1
DElVpp
AlO

Vee
Vee
PGM/WE .' A'4
A' 3
A3
'
As
As
Ag
Ag
All
Al1
DE
DElVpp

As
Ag
All
DE

290231-2

Figure 2. Pin Configuration

NOTES:
1. Intel "Universal Site" compatible EPROM pin configurations are shown in the blocks adjacent to the 27C513 pins.
Pin Names
Ao-AI5
CE
OElVpp

Addresses

Page-Select Write Enable
Outputs

02-0 7
Do/Oo,DI /O ,
RST

Chip Enable
Output EnablelVpp

Input/Outputs
Page Reset

5-86

27C513

available with 168 ± 8 hour, 125·C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROM operating temperature range is O·C to 70·C. Extended operating temperature range (- 40·C to + 85·C) EXPRESS products are available. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.15 electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.

EXPRESS EPROM PRODUCT FAMILY

EXPRESS OPTIONS

PRODUCT DEFINITIONS

27CS13 VERSIONS

EXTENDED TEMPERATURE
(EXPRESS) EPROMs

Type Operating Temperature Burn-in 12S·C (hr)

Q
T

O·Cto +70·C
-40·C to + 85·C

-40·Cto + 85·C

Packaging Options

168 ±8

Speed Versions

None
168 ±8

-200V10

I
I

Cerdip

Q, T,L

READ OPERATION
DC CHARACTERISTICS
Electrical Parameters of Express EPROM Products are identical to standard EPROM parameters except for·
Symbol

TD27CS13
LD27CS13

Parameter

Min

ISB
lee1(1)

Test Conditions

Max

Vee Standby Current (mA)

1.0

CE = VIH,OE/Vpp = VIL

Vee Active Current (mA)

OE/vpp = CE = VIL

Vee Active Current
at High Temperature (mA)

OE/vpp = CE = VIL, T Ambient = 85·C

NOTE:

1. The maximum current value is with outputs 00 to 07 unloaded.

290231-4
Binary Sequence from Ao to A15

OElVpp

+sv
R
vss ~ GIliD
~

1 K!l
CE

vee
~

290231-3

+sv

GND

Burn-In Bias and Timing Diagrams

5-87

intJ

27C513

ABSOLUTE MAXIMUM RATINGS'"

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.

Operating Temperature
During Read .................. O"C to + 70°C(2)
Temperature Under Bias ....... -10°C to + 80°C(2)
Storage Temperature .......... -65°C to + 125°C
Voltage on Any Pin with
Respectto Ground ............. - 2V to + 7V(I)
Voltage on As with
Respect to Ground .; ........ - 2V to + 13.5V(I)

Vpp Supply Voltage with Respect to Ground
during Programming ..•...... - 2V to + 14.0V(I)
Vcc Supply Voltage with
Respect to Ground .•.•........ - 2V to + 7.0V(I)

READ OPERATION
DC CHARACTERISTICS TIL and NMOS Inputs
Symbol
III
ILO

Parameter

Notes

Min

Input Load Current
Output Leakage Current

ISB

' Vee Current Standby

ICCI

Vee Current Active

IpP1

Vpp Current Read

Vil

Input Low Voltage (± 10% Supply)

VIH

Input High Voltage (± 10% Supply)

VOL

Output Low Voltage

VOH

Output High Voltage

los

Output Short Circuit Current

Vpp

Vpp Read Voltage

VClR

Page Latch Clear
VCC Supply Voltage

Typ(3)

Max

0.01

1.0

Units

' Test Condition

}LA VIN

OV to 5.5V

±10

}LA VOUT

1.0

mA CE

mA CE = Vil
f = 5 MHz, lOUT

}LA Vpp

-0.5

0.8

2.0

Vcc+0.5

0.45

100

Vcc-0.7

Vcc

3.5

4.0

2.4

OV to 5.5V

VIH

0 mA

Vcc

= 2.1 mA
10H = 400}LA

10l

NOTES:
'1. Minimum DC input voltage is -0.5V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V which may overshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. Typical limits are at Vee = 5V, TA = + 25°C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100%
tested.
7. Vee must be applied simultaneously or before C5ElVpp and removed simultaneously or after OElVpp.
8. Maximum active power usage is the sum of Ipp and lee. The maximum current value is with no loading on outputs 00 to
07·

5-88

intJ

27C513

DC CHARACTERISTICS CMOS Inputs
Symbol

Parameter

,Notes

Min

Input Load Current

III
ILO

Output Leakage Current

ISB

Vee Current Standby
with Inputs-

leel

Vee Current Active

VIL

Input Low Voltage (± 10% Supply)

VIH

Input High Voltage (± 10% Supply)

VOL

Output Low Voltage

VOH

Output High Voltage

los

Output Short Circuit Current

ISwitching
IStable

Typ(3j

Max

Units

Test Condition

0.01

1.0

,...A

= OV to 5.5V
Your = OV to 5.5V
CE = VIH
CE = VIH
CE = VIL
f = 5 MHz, lOUT = 0 mA

±10

,...A

100

,...A

-0.2

O.B

0.7 Vee

Vee+ 0.2

0.4
Vee - O.B

100

VIN

= 2.1

10L

10H == -2.5mA

NOTES:
1. Minimum DC input voltage is -0.5V. During transitiohS, the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V which may overshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. Typical limits are at Vee = 5V, TA = + 25'C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100%
tested.
7. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
8. Maximum active power usage is the sum of Ipp and Icc. The maximum current value is with no loading on outputs 00 to
~

PAGE-SELECT WRITE AND PAGE-RESET OPERATION
AC CHARACTERISTICS
Symbol

Parameter

Limits
Min

Max

Units

Test
Conditions

tew

CE to End cif Write

100

OElVpp = VIH

twp

Write PiJlse Width

OElVpp = VIH

tWR

Write Recovery Time

tDS

Data Setup Time

OElVpp = VIH

OElVpp = VIH
OElVpp = VIH

tDH

D~ta Hold Time

les

CE to Write Setup Time

tWH

WE Low from OElVpp High
Delay Time

tRST

Reset Low Time

100

tRAV

Reset to Address Valid

150

NOTES:
1. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
2. Typical values are for T A = ,25'C and nominal supply voltages.
3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
'
4. The maximum current value is with outputs 00-07 unloaded.
5. Packaging Options: No prefix = Cerdip.
.S. FiS'i' function is available only on parts with B-digit suffix.

5-89

"n+_r

111'eII"

27C513

CAPACITANCE(2hA = + 25·C, f =
Symbol
CIN
, COUT

C~lVpp

Parameter

1 MHz

Typ(1)

Max

Units

Conditions

Input Capacitance

VIN

Output Capacitance

VOUT

OElVpp Capacitance

VIN

~C TESTING INPUT/OUTPUT WAVEI:ORM

AC TESTING LOAD CIRCUIT

1N914
2.4

2.0 ____

_ _ _ TEST POINTS
0.45

O.B

DEVICE
UNDER
TEST

290231-5

AC Testing inputs are driven at2.4V for a Logie 1 and 0.45V for a
Logic O. Timing measurements are made at 2.0V for a Logic 1
and O.BV for a Logic O.

AC CHARACTERISTICS O·C s; T A s;
Versions(4)

VCC ±10%

Symbol

Parameter

1----+---0() OUT

290231-6

CL = 100 pF
CL Includes Jig Capacitance

+ 70·C
27C513-170V10
Min

Max

27C513-200V10
Min

Max

27C513-250V10 Units Test Conditions
Min

Max

tACC

Address to Output Delay

170

,200

250

CE= OEI
Vpp = VIL

tCE

CE to Output Delay

170

200

250

OElVpp = 'vIL

toE
tOF(3)

OElVpp to Output Delay

100

CE = VIL

OElVpp High to Output Float

tOH

Output Hold from Addresses
CE or OElVpp, Whichever
Occurred First

CE == VIL
CE = OEI
Vpp = VIL

0
0

NOTES:
1. Typical values are for TA = 25D C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
.
'
.
3. The maximum current value is with outputs 00-07 'unloaded.
4. Packaging: No prefix = Cerdip.
AC CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) .•.... 10 ns
Input Pulse Levels .................... VOL to VOH
Input Timing Reference Level .......••....... 1.5V
Output Timing Reference Level ..•. ' .•.• VIL and VIH

5-90

inter

27C513

AC WAVEFORMS FOR READ OPERATION
VIH _ _ _ __

'----------- ....
ADDRESS
VALID

ADDRESSES
VIL _ _ _ _--'

VIH------t-~

r'-------- ....

VIH - - - - - - t - - - - " ' "
OElVpp

VIL

......- - - - t A C c - - - - t
17.,..,~rOU~UT

_ _ _ _ _~H~IG~H~Z_ _ _ __i~r+~

••.• -....,"",",
HIGH Z

VIH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......_ _ _ _.L...-"_ _ _ __

WE
VIL
290231-7

5-91

27~513

AC WAVEFORMS FOR PA~E-SELECT WRITE 'OPERATION
ADDRESS
DON'T CARE

ADDRESSES

ADDRESS
VALID

1 4 - - - -__ I CW(4) _ _ _ _- - t
CE ...- - - -__----------~

/ 4 - - - I W p ( 4 ) _ - - - o....-

WE--------------------~----~

OE/Vpp __________..,jrl

DOIOO.O,IO,

....

,-----~----

14--- tDs---t

INPUTIOUTPUTS
DATA IN STABLE

02.1)7

OUTPUTS _ _ _ _ _ _ _ _...
H._IG_H_Z__~----------~----------290231-8

AC WAVEFORMS FOR PAGE-RESET OPERATIONS

:::J<______

4__·

A
...D;.;D...
RE..,S;.;S..;D..;O...
N'T
......
CA.;,R._E____

-----------r'" l,

_.p-A_D...
DR...ES.;,S
......
VA
...L..;ID_

~,==r

.
290231-9

NOTES:

1. Typical values are for TA = + 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OElVpp may be delayed up to teE-toE after the falling edge of ~ without impact on teE'
4. Write may be terminated by either CE or WE. providing that the minimum lew requirement is met before bringing WE high
or that'the minimum twp requirement is met before bringing ~ high.
~. OElVpp must be high during write cycle.
.

5-92

inter

27C513

DEVICE OPERATION
The modes of operation of the 27C513 are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for OElVpp and 12V on As for inteligent Identifier mode.
Table 1. Operating Modes
Pins

OE/Vpp

RST

Read

VIL

VIH

Output Disable

VIL

VIH

Standby

VIH

Programming

VIL

Vpp(3)

Input!
Outputs

Vee

X(1)

5.0V

DOUT

VIH

Vee

HighZ

VIH

Vee

HighZ

VIH

(Note 3)

DIN

(Note 3)

Outputs

Mode

Verify

VIL

VIH

DOUT

Program Inhibit

VIH

VIL
Vpp(3)

VIH

(Note 3)

HighZ

Page-Select
Write

VIL

VIH

VIL

VIH

Vec<5)

HighZ

Page(2)
DIN

Page-Reset

VIL

Vec<5)

HighZ

VIL

VIH

VH(6)

VIL

5.0V

89H

VIH

VH(6)

VIH

5.0V

F9H

inteligent(4) -Manufacturer
Identifier
-Device

VIL

NOTES:

1. X can be VIH or VIL.
2. Addresses are don't care for page selection. See Table 2 for DIN values.
3. See Table 2 for Vee and Vpp voltages.
4. A1-Aa, A10-A13, = VIL.
5. Page 0 is automatically selected at power-up (Vee < 4.0V).
6. VH = 12.0V ±O.5%.

5-93

intJ

27C513

Read Mode

Page Reset

The 27C513 has three control functions, two of
which must be logically active in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable (OElVpp) is the output control and should be
used to gate data from the output pins, independent
of device selection. Assuming that addresses are
stable, the address access time (tAee) is equal to
the delay from CE to output (teE)' Data is available
at the outputs after a delay of tOE from the falling
edge of OElVpp, assuming that CE has been low
and addresses have been stable for at least
tAee-tOE. WE is held high during read operations.

The 27C513 has an automatic page latch clear circuit to ensure consistent page selection during system bootstrapping. The page latch is automatically
cleared to page 0 upon power-up. As the Vee supply
voltage ramps up, the page latch is cleared. After
Vee exceeds the 4.0V maximum page latch clear
voltage (VelR), the latch clear circuit is disabled.
This ensures an adequate safety margin (500 mV of
system noise below the worst case -10% Vee supply condition) against spurious page latch clearing.
The 27C513 also has a page reset pin: RST. This pin
should be tied to an active low system reset signal.
These 27C513s will be reset to page 0 when this line
is brought to TTL Low (VIL>.

Page-Select Write Mode
The 27C513 is addressed by first selecting one of
four 16 Kbyte pages. Individual bytes are then
selected by normal random access within the
16 Kbyte page using the proper combination of
Ao-A13 address inputs. By applying a TTL low signal to the WE input with CE low and OE high, the
desired page is latched in according to the combination of 00/00 and 01/01. Address inputs are "don't
care" during page selection.
Care should be taken in organizing software programs such that the number of page changes is minimized. This allows maximum system performance.
Also, the processor's program counter status must
be considered when page changes occur in the middle of an opcode sequence. After a page-select
write, the program counter will be incremented to the
next location (or further in pipelined systems) in the
new page relative to that of the page-select write
opcode in the previous page.

Two Line Control
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 output control lines
which accommodate this multiple memory connection. The two control lines for read operation allow
for:
a) the lowest possible memory power dissipation,
and
b) complete assurance that output bus contention
. will not oc'cur.
To use these two control lines most efficiently, CE
-should be decoded and used as the primary device
selecting function, while OElVpp should be made a
common connection to all devices in the array and
connected to the READ line from the system control
bus. This assures that all deselected memory devices are in their low power standby mode and that the
output pins are active only when data is desired from
a particular memory device.
Similarly, CE deselects other 27C513s or RAMs during page select write operation while WE is in common with other devices in the array. WE is connected to the WRITE system control line.

SYSTEM CONSIDERATIONS
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed
by complying with Intel's Two-Line Control and by

Table 2. Page Selection Data
Input/Output
(Pin)
Page Selection
Select Page 0
Select Page 1
Select Page 2
Select Page 3

01 /0 1

00/00

(12)

(11)

Vil
Vil
VIH
VIH

Vil
VIH
Vil
VIH

5-94

inter

27C513

properly selected decoupling capacitors. It is recommended that a 0.1 /-LF ceramic capacitor be used on
every device between Vee and GND. This should be
a high frequency capacitor of low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 /-LF bulk electrolytic
capacitor should be used between Vee and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effects of PC board traces. This inductive effect
should be further minimized through special layout
considerations such as larger traces and gridding
(refer to High Speed Memory System Design Using
the 2147H, AP-74). In particular, the Vss (Ground)
plane should be as stable as possible.

inteligent Identifier™ Mode
The inteligent IdentifierTM Mode allows the reading
out of a binary code from an EPROM that will identify its manufcturer and type. This mode is intended
for use by programming equipment for the purpose
of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when
programming the device.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line Ag of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line Ao from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
Mode.
.

PROGRAMMING
Byte 0 (Ao = VILl represents the manufacturer code
and byte 1 (Ao = VIH) the device identifier code.
These two identifier bytes are given in Table 1.

Caution: Exceeding 14.0 V on OE/Vpp will permanently damage the 27C513.

Initially, and after each erasure, all bits of the
EPROM are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations. Although only "Os" will be programmed,
both "1 s" and "Os" can be present in the data word.
The only way to change a "0" to a "1" is by ultraviolet light erasure.

Quick Pulse Programming™ Algorithm
Intel's 27C513 EPROM can be programmed using
the Quick-Pulse Programming™ algorithm, developed by Intel to substantially reduce the throughput
time in the production programming environment.
this algorithm allows these devices to be programmed as fast as fourteen seconds, almost a hundred fold improvement over previous algorithms. Actual programming time is a function of the PROM
programmer being used.

The Quick-Pulse Programming algorithm uses initial
pulses of 100 /-Ls followed by a byte verification to
determine when the address byte has been successfully programmed. Up to 25 100 /-Ls pulses per
byte are provided before a failure is recognized. A
flowchart of the Quick-Pulse Programming Algorithm
is shown in Figure 3.

Program Inhibit
Programming of multiple 27C513s in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE input inhibits the
other 27C513s from being programmed.

For the Quick-Pulse Programming algorithm, the entire sequence of programming pulses and byte verifications is performed at Vee = 6.25V and Vpp at
12.75V. When programming of the EPROM has
been completed, all bytes should be compared to
the original data with Vee = Vpp = 5.0V.

Except for CE, all inputs of the parallel 27C513s may
be common. A TTL low-level pulse applied to the CE
input with OElVpp at its programming voltage will
program the selected 27C513.

Verify
A verify (read) should be performed on the pro. grammed bits to determine that they have been correctly programmed. The verify is performed with OEI
Vpp and CE at VIL and Vee is at its programming
Voltage. Data should be verified tDV after the falling
edge of CEo
5-95

intJ

27C513

START

DEVICE
FAILED

INCREMENT ADDR

SELECT
NEXT PAGE

DEVICE
FAILED

290231-10

Figure 3. 27C513 Quick-Pulse Programming Flowchart

5-96

inter

27C513

The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 /-tW/cm 2 power rating. The EPROM should be placed within 1 inch of
the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000
/-tW/cm2). Exposure of the device to high intensity
UV light for long periods may cause permanent damage.

ERASURE CHARACTERISTICS
(FOR CERDIP EPROMs)
The erasure characteristics are such that erasure
begins to occur upon exposure to light with waveI~ngths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000 A range. Data show that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the device is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.

TABLE 2. DC PROGRAMMING CHARACTERISTICS
TA

25°C ±5°C

Symbol

Limits

Parameter

Input Current (All Inputs)

VIL

Input Low Level (All Inputs)

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

lee2(2)

Min

Max

Units

/-t A

-0.1

0.8

2.4

Test Conditions
(Note 1)

VIN = VIL or VIH

6.5

0.45

IOL = 2.1 mA

IOH = -2.5mA

Vee Supply Current
(Program and Verify)

IpP2(2)

Vpp Supply Current (Program)

VID

Ag inteligent Identifier Voltage

11.5

12.5

Vpp

Quick-Pulse Programming Algorithm

12.5

13.0

Vee

Quick-Pulse Programming Algorithm

6.0

6.5

3.5

CE = VIL,
OElVpp = Vpp

NOTES:
1. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
2. The maximum current value is with outputs 00-07 unloaded.

5-97

inter

27C513

AC PROGRAMMING CHARACTERISTICS
TA = 25°C ±5°C.

Symbol

Limits

Parameter
Min

Typ

Max

Units

tAS

Address Setup Time

,""S

toES

OElVpp Setup Time

,""S

tos

Data Setup Time

,""S

tAH

Address Hold Time

,""S

tOH

Data Hold Time

,""S

tOFP

Output Enable to Output Float Delay

tvcs

Vee Setup Time

tpw

CE Initial Program Pulse Width

toEH

OElVpp Hold Time

130

100

105

Conditions·
(Note 1)

(Note 2)

,""S

(Note 1)

,""S
,""S

tov

Data Valid from CE

tVR

OElVpp Recovery Time

,""S

tpRT

OElVpp Pulse Rise Time
During Programming

,""S

• AC CONDITIONS OF TEST

NOTES:
1. Vee must be applied simultaneously· or before OElVpp

Input Rise and Fall Times (10% to 90%): ..... 20 ns

and removed simultaneously or after OElVpp.
2. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no longer driven-see timing diagram.

Input Pulse Levels .................. 0.45V to 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... O.8V .and 2.0V

5-98

intJ

27C513

PROGRAMMING WAVEFORMS
VIH
ADDRESSES
VIL
VIH
DATA
VIL

6J:1V
Vee

5.OV
12.5V
OE/Vpp
VIL
IPRT
VIH
CE
VIL

VIH-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

WE
VIL
290231-11

NOTES:
1. The Input Timing Reference Level is O.SV for a VIL and 2.0V for a VIH.
2. tOE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. The proper page to be programmed must be selected by a page-select write operation prior to programming each of the
four 16 Kbyte pages. See Page Sel~ct Write AC and DC Characteristics for information on page selection operations.

REVISION HISTORY
Description
Change 150 speed option to 170.

5-99

27C011
PAGE-ADDRESSED 1M (8 x 16K x 8) EPROM

•
•
•
•

No~Hardware-Change Upgrades
- Drop-In 27513 Replacement

•
•
•

Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as
15 Seconds

•

Pag,d Organization
- Reduced Physical Address
Requirement
Compati~le

with 28-Pin JEDEC EPROMs
-Single-Trace Modification for
Retrofitting 27128-Ba.sed Designs

Automatic Page Clear
- Resets to Page 0 on Power-Up and
On Demand with RST Signal
High-Performance
- 200 nsA~cessl Time
- Low 30 mA Active Power
Standard EPROM Features
- TTL Compatibility
- Two Line Control
- intel/gent IdentifierTM for Automated
Programming
Smallest Megabit DIP Package
- 28-Pin DIP, Minimal Footprint without
Address/Data Multiplexing

The Inte! 27C011 is a 5V-only, 1,048,576-bit Erasable Programmable Read Only Memory. It is organized as 8
pages of 16K 8-bit words. Its pin-compatibility with byte-wide JEDEC EPROMs allows retrofitting existing
designs to the greater storage capacity afforded by the page-addressed organization. Its 16 K-byte physical
address space requirement allows the 27C011 to be utilized in address-constrained system designs.
When a 28-pin DIP socket is configured for 27C64 or 27C128 EPROMs, it is easily retrofitted to the 27C011.
By. adding a WRITE ENABLE signal to pin 27 (DIP) (unused on 27C64 and 27C128). the 27C011 can be used
in an existing design. Thus, the 27C011 enables product enhancements via additional feature sets and firmware-intensive performance upgrades.
The page-addressed organization allows the use of 28-pin DIP packages, the smallest megabit EPROM
footprint with applicability to all microprocessors. This provides very efficient circuit board layouts.
The 27C011 is part of a multi-product megabit EPROM family. The other members are standard-addressed
byte-wide and word-wide versions; the 27C010 and 27C210, respectively. The 27C010 is organized as
128K x 8 in a 32-pin DIP package which is pin-compatible with JEDEC-standard 28-pin 512K EPROMs. The
27C210 is packaged in a 40-pin DIP with a 64K x 1q organization.
The 27C011 has an automatic page clear circuit for ease of use of its paged organization. The page-select
latch is automatically cleared to the lowest order page upon system power-up. The 27C011 also contains
many industry-standard features such as two-line output control for simple interfacing and the inteligent IdentifierTM feature for automated programming. It also can be programmed rapidly using Intel's Quick-Pulse Programming™ Algorithm.
.

5-100

. October 1990
Order Number: 290232-002

inter

27C011

DATA
INPUTS/
OUTPUTS
oo,D~D~

DATA
OUTPUTS
03-07

tlo'01b2~

GNDo-+

PAGE SELECT
LOGIC

LOGIC

'0-'13 (
ADDRESS
INPUTS

+
X
DECODER

I
I

PROGRAW

OE AND CE

PGii~

+
y
DECODER

OUTPUT
BUFFERS

.r:1

"Y"-GATING

131,072
CELL MATRIX

SELECT

PAGE 0

I
I
I
I
I
I
I

PAGE 1

•
~

.iUI

PAGE 2

PAGE 3

PAGE 4

.rw
I

PAGE 5

PAGE 6

PAGE 7

290232-1

Figure 1. Block Diagram

27C513
27513

27C128
27128A

FiST
A12
A7
Av
As
A4
Aa
A2
A1
Ao

Vpp
A12
A7
As
As
A4
A3
A2
A1
Ao
00
01
O2
GNO

00 /00
01 /01

02
GNO

27C128
27128A

27C513
27513

VCC

Vee

PGM/WE

PGM

Vee
WE
A1a
As
Ag
All
OElVpp
A1D
CE
07
06
Os
04
03

27C011
Vpp/RST
A12

A13

A7
A6

A11

A2
AI

A10

00 /0 0

0 1/0 1

O2/0 2

GND

290232-2

Figure 2. Pin Configuration

5-101

A13
As
Ag
All
OE
A10
CE
07
Os
Os
04
03

inter

27C011

Pin Names
Ao-A13

Addresses

Chip Enable

Output Enable

Page-Select Write Enable

03-0 7

Outputs

= 0, 1, or 2)

Ox/Ox

Input/Outputs (X

Vpp/RST

Vpp/Page Reset

No Internal Connection

D.U.

Don't Use

EXTENDED TEMPERATURE
(EXPRESS) EPROMs

EXPRESS EPROM PRODUCT FAMILY .
PRODUCT DEFINITIONS

The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM, allowing
the choice of appropriate memory size to match system applications. EXPRESS EPROM products are
available with 168 ±8 hour, 125°C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROMoperating temperature range is O°C to 70°C. Extended operating temperature range (- 40°C to + 85°C) EXPRESS products are available. Like' all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.

Operating
Temperature

Type
Q

O°Cto

Burn-In
125°C (hr)

+ 70°C

168 ±8

EXPRESS OPTIONS
27C011 VERSIONS
Packaging Options
Speed Versions
-200V10

I
I

Cerdip
Q,T,L

Al~
A13

290232-4
Binary Sequence from Ao to A13 required for each page. Page
changes during burn-in, require the following minimum timing
parameter values (see Page-Select AC Characteristics):
tWH = 500 ns
twp = 500 ns
tWR = 500 ns
tos = 500 ns
IcH = 500 ns

290232-3
Vpp

+5V
. GND =

1 KG
vee = +5V
CE = GND

Burn-In Bias and Timing Diagrams
5-102

27C011

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.

Operating Temperature During
Read .....................•..... O°C to

+ 70°C
+ BO·C
+ 125·C

Temperature Under Bias ......... -1Q°C to
Storage Temperature .....•.... - 65·C to

All Input or Output Voltages with
Respect to Ground ............ - 0.6V to

+ 6.5V

Voltage on A9 with

Respect to Giound ...........

O.SV to + 13.0V

Vpp Supply Voltage with Respect to
Ground During Programming .... -0.6V to

+ 14V

VCC Supply Voltage
with Respect to Ground ........ -0.6V to

+ 7.0V

READ OPERATION
DC CHARACTERISTICS TTL and NMOS Inputs, O·C
Parameter

,;;; T A ,;;;
Typ(3)

+ 70·C , VCC +- 10%
Max

Units

1.0

fLA

±10

fLA

500

fLA
mA

Vpp/RST

1.0
5

CE = VIL
f = 5 MHz, lOUT

Vpp Current Read

Vpp

VIL

Input Low Voltage (± 10% Supply)

fLA
V

VIH

Input High Voltage (± 10% Supply)

VOL

Output Low Voltage

VOH

Output High Voltage

VelR

Page Latch Clear-Vee

los
Vpp

Output Short Circuit Current

Vpp Read Voltage

Symbol
III

Input Load Current

ILO

Output Leakage Current

ILRST

Vpp/RST Load Current

IS8

Vce Current Standby

leel

Vee Current Active

IpPl

Notes

Min

0.Q1

-0.5

0.8

2.0

Vee+ 0.5
0.45

2.4
3.5
Vee- 0.7V

Test Condition

= OV to 5.5V
VOUT = OV to 5.5V
VIN

:0;

Vec

= VIH

= 0 mA

Vee

V
V

10L

= 2.1 rnA

10H

4.0

100

Vee

-400 fLA

NOTES:
1. Minimum DC input voltage is -0.5V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V which may overshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. Typical limits are at Vee = 5V, TA = + 25·C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100%
tested.
7. Maximum active power usage is the sum of Ipp and Icc. The maximum current value is with no loading on outputs 00 to

07·
8. Vpp may be one diode voltage drop below Vee. It may be connected directly to Vee. Also, Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
9. Vpp/RST should be at a TTL VIH level except during programming or during page 0 reset.

5-103

intJ

27C011

READ OPERATION (Continued)
DC CHARACTERISTICS CMOS Inputs
Symbol

Parameter

Notes

Min

Typ(3)

Max

Units

0.01

1.0

p.A

VIN

Input Load Current

III

Test Condition

OV to 5.5V

ILO

Output Leakage Current

±10

p.A

VOUT

ISB

VCC Current Standby

100

p.A

Vcc Current Active

CE =
CE =

Vcc

ICC1

f
IpP1

Vpp Current Read

p.A

VIL

Input Low Voltage
( ± 10% Supply)

7
-0.5

0.8

VIH

Input High Voltage
(± 10% Supply)

0.7Vcc

Vcc+ 0.5

VOL

Output Low Voltage

0.4

VOH

Output High Voltage

los

Output Short Circuit Current

100

rnA

Vcc- 0.8

OV to 5.5V

VIL
5 MHz, lOUT

Vpp

0 mA

Vcc

= 2.1 rnA
10H = -400 p.A

10L

NOTES:

1. Minimum DC input voltage is -0.5V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V which may oV!lrshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. !}tpicallimits are at Vee = 5V, TA = + 25"C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled, not 100%
tested.
7. Maximum active power usage is the sum of Ipp and lee.,The maximum current value is with no loading on outputs 00 to
07·

AC CHARACTERISTICS(1) O·C ~ TA S; + 70·C
Versions

Vee ±10%

Symbol

Characteristics

27C011-200V10
Min

Units

Max

tACC

Address to Output Delay

200

tCE

CE to Output Delay

200

tOE

OE to Output Delay

tDF(2)

OE High to Output Float

tOH(2)

Output Hold from Addresses CE or OE,
Whichever Occurred First

NOTES:

1. See AC Waveforms for Read Operation for timing mea·
surements.
2. Sampled, not 100% tested.

CONDITIONS Of TEST

h1put Rise arid,Fall Times (10% to 90%) .••... 10 ns
Input Pulse Levels .................. 0.45V to 2.4V
Input Timing Reference Level .•....• 0.8V and 2.0V
Output Timing Reference Level ...•.. 0.8V and 2.0V

5·104

intJ

27C011

PAGE-SELECT WRITE AND PAGE-RESET OPERATION
O·C ~ T A ~

AC CHARACTERISTICS
Symbol

+ 70·C
Limits

Parameter

Min

Max

Test
Conditions

Units

tew

CE to End of Write

100

OE = VIH

twp

Write Pulse Width

OE = VIH

tWR

Write RecoveryTime

!DS

Data Setup Time

OE = VIH

OE = VIH
OE = VIH

tDH

Data Hold Time

tes

CE to Write Setup Time

tWH

WE Low from OE High Delay Time

tRST

Reset Low Time

100

tRAY

Reset to Address Valid

150

CAPACITANCE(1hA = + 25·C, f =
Parameter·

Symbol

1 MHz

Typ(1)

Max

Units

Input Capacitance

CIN

Conditions
VIN

= OV

COUT

Output Capacitance

VOUT:;O OV

CVpp/RST

Vpp/RST Capacitance

VIN

= OV

1. Sampled. Not 100% tested.

AC TESTING INPUT/OUTPUT WAVEFORM

AC TESTING LOAD CIRCUIT
1.3V

2.4~

0.45

:::

POINTS

2.0

3.3Kll
OUTPUT

DEVICE
UNDER
TEST

0.8

290232-5

~--+----o OUT

290232-6

AC Testing inputs are driven at 2.4V for a logic 1 and 0.45V for a
logic Timing measurements are made at 2.0V for a logic 1 and
O.BV for a logic O.

CL=100pF

CL Includes Jig Capacitance

5-105

inter

~IQ)W~OO©(g OOOIr@~IMl~iiO@OO

27C011

AC WAVEFORMS FOR READ OPERATION
V~ _ _ _ _~

W---------ADDRESS
VALID

ADDRESSES

V,L _ _ _ _J

VI" _____

V,L

VI"-----t---~

iiE

V,"
OUTPUT _ _ _ _......:H;:::IG::;:H.:.Z_ _ _ _tt~i+{

HIGH

V,L

V," ____________________............I_ _ _ __
We
V,L

290232-7

AC WAVEFORMS FOR PAGE-SELECT WRITE OPERATION
ADDRESS
DON'T CARE

ADDRESSES

-------~ 1-----tcwl.I----~ "rn~rl-lf'T'rn:T

i'liIi/WE-----------~

!I!------I
DoIOoo D,/D,. D./Oz

Da-a,

.....1.1_-1';2:=!:!.::L__

IDS

INPUT IOUTPUTS
DATA IN STABLE

DUTPUTS _ _ _ _ _H_.IO_H;.;;;Z_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

290232-8

5-106

intJ

27C011

AC WAVEFORMS FOR PAGE-RESET OPERATION
ADDRESSES

=:x
______.r

r:__t_RA_V_~

ADDRESS DON'T CARE

"+--

Vpp/RST

tRST

•

ADDRESS VALID

_ _ _ _ _ _ __

290232-9
NOTES:

1. Typical values are for TA = + 25'C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE.
4. Write may be terminated by either CE or WE, providing that the minimum tcw requirement is met before bringing WE high
or that the minimum twp requirement is met before bringing CE high.
5. OE must be high during write cycle.

DEVICE OPERATION
The modes of operation of the 27C011 are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for Vpp and 12V on Ag for inteligent Identifier.

Table 1. Operating Modes
Pins
Mode
Read

Input!
Outputs

PGMI
WE

Vpp/RST

VIL

VIH

X(I)

VIH

5.0V

DOUT

VIH

5.0V

HighZ

Vee

Outputs

Output Disable

VIL

VIH

Standby

VIH

5.0V

HighZ

Programming

VIL

VIH

VIL

Vpp(3)

VCC(3)

DIN

Verify

VIL

VIH

Vpp(3)

Vcd3)

DOUT

Program Inhibit

VIH

Vpp(3)

Vcd3)

HighZ

Page-Select Write

VIL

VIH

VIL

VIH

Vcd 5)

(Note 7)

Page DIN

VIL

VCC

(Note 7)

VIL

VIH

5.0V

89H

VIH

5.0V

31H

Page-Reset
inteligent
Identifier

-Manufacturer
-Device

VIL

VIH

VH(6)

VIL

VIH

VH(6)

NOTES:

1.
2.
3.
4.
5.
6.
7.

X can be VIH or VIL'
Addresses are don't care for page selection. See Table 2 for DIN values.
See Table 3 for VCC and Vpp.
A1-AS, A10-A13, = VIL.
Page 0 is automatically selected at power·up (Vcc < 4.0V).
VH = 12.0V ±0.5%.
State of outputs depends on state of CE and OE. See Outputs State for Read, Output Disable, and Standby Modes.

5-107

27C011

Read Mode

Page Reset

The 27C011 has three control functions, two of
which must be logically active in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable (OE) is the output control and should be used
to gate data from the output pins, independent of
device selection. Assuming that addresses are stable, the address access time (tACe) is equal to the
delay from CE to output (tCE)' Data is available at
the outputs after a de~ of tOE from the falling edge
of QE, assuming that CE has been low and addresses have been stable for at least tACC-tOE. WE is
held high during read operations.

The 27C011 has an automatic page latch clear circuit to ensure consistent page selection during system bootstrapping. The page latch is automatically
cleared to page 0 upon power-up. As the Vcc supply
voltage ramps up, the page latch is cleared. After
Vcc exceeds the 4.0V maximum page latch clear
voltage (VCLR), the latch clear circuit is disabled.
This ensures an adequate safety margin (500 mV of
system noise below the worst case -10% VCC supply condition) against spurious page latch clearing.
The 27C011 also has a page reset pin: Vpp/RST.
This pin shol.!ld be tied to an active low reset line.
These 27C011 s will be reset to page 0 when this line
is brought to TIL Low (VIL>.

Standby Mode·
EPROMs can be placed in standby mode which reduces the maximum current of the device by applying a TIL-high signal to the CE input. When in standby mode, the outputs are in a high impedance state,
independent of the OE and WE inputs.

Two Line Control

Page-Select Write Mode

a) the lowest possible memory power dissipation,
and
.

The 27C011 is addressed by first selecting one of
eight 16 K-byte pages. Individual bytes are then se"
lected by normal random access within the 16
K-byte page using the proper combination of
Ao-A13 address inputs. By applying a TIL low signal to the WE input with CE low and OE high, the
desired page is latched in according to the combination of 00/00, 01/01 and 02/02. Address inputs
are "don't care" during page selection.
Care should be taken in organizing software programs such that the number of page changes is minimized. This allows maximum system performance.
Also, the processor's program counter status must
be considered when page changes occur in the middle of an opcode sequence. After a page-select
write, the program counter will be incremented to the
next location (or further in pipelined systems) in the
new page relative to that of the page-select write
opcode in the previous page.
Table 2. Page Selection Data
Input/Output
Page Selection
Select Page 0
Select Page 1
Select Page 2
Select Page 3
Select Page 4
Select Page 5
Select Page 6
Select Page 7

02 /0 2

01 /0 1

00 /0 0

VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH

VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH

VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH

b) complete assurance that output bus contention
will not occur.
To use these two control lines most efficiently, CE
should be decoded and used as the primary device
selecting function, while OE should be made a common connection to all devices in the array and connected to the READ line from the system control
bus. This assures that all deselected memory devices are in their low power standby mode and that the
output pins are active only when data is desired from
a particular memory device.
Similarly, CE deselects other 27C011 s or RAMs during page select write operation while WE is in common with other devices in the array.. WE is connected to the WRITE system control line.

SYSTEM CONSIDERATIONS
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The as-

5-108

27C011

sociated transient voltage peaks can be suppressed
by complying with Intel's Two-Line Control and by
properly selected decoupling capacitors. It is recommended that a 0.1 JLF ceramic capacitor be used on
every device between Vee and GND. This should be
a high frequency capacitor of low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 JLF bulk electrolytic
capacitor should be used between Vee and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effects of PC board traces. This inductive effect
should be further minimized through special layout
considerations such as larger traces and gridding. In
particular, the Vss (Ground) plane should be as stable as possible.

PROGRAMMING
Caution: Exceeding 14.0Von Vpp will permanently damage the 27COtt.
Initially, and after each erasure, all bits of the
. EPROM are in the "1" state. Data is introduced by
selectively programming "Os" into the-desired bit locations. Although only "Os" will be programmed,
both "1s" and "Os" can be present in the data word.
The only way to change a "0" to a "1" is by ultraviolet light erasure.
The 27C011 is in the programming mode when the
Vpp input is at its programming voltage and CE is at
TTL-low. The data to be programmed is applied 8
bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.

Program Inhibit
Programming of multiple 27C011 s in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE input inhibits the
other 27C011 s from being programmed.
Except for CE, all inputs of the parallel 27C011 s may
be common. A TTL low-level pulse applied to the
PGM/WE input with Vpp at its programming voltage
will program the selected 27C011.

Verify
A verify (read) should be performed on the programmed bits to determine that they have been correctly programmed. The verify is performed with OE
and CE at VIL and Vee is at its programming voltage

Data should be verified tDV after the falling edge of

CEo

inteligent Identifier™ Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when
programming the device.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
. Mode.
Byte 0 (AO = VILl represents the manufacturer code
and byte 1 (AO = VIH) the device identifier code.
These two identifier bytes are given in Table 1.

ERASURE CHARACTERISTICS
(FOR CERDIP EPROMs)
The erasure characteristics are such that erasure
begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000 A range. Data show that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the device is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 JLW/cm 2 power rating. The EPROM should be placed within 1 inch of
the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000
JLW/cm2). Exposure of the device to high intensity
UV light for long periods may cause permanent damage.

5-109

inter

27C011

Vee = &.25V
Vpp'" 12.75V

OORAM ONE 100 ,,8 PULS

290232-10

Figure 4. 27C011 Quick-Pulse Programming Flowchart

Quick Pulse Programming Algorithm
Intel's 27C011 EPROM is programmed using the
Quick-Pulse Programming algorithm, developed by
Intel to substantially reduce the throughput time in
the production programming environment. This algo·
rithm allows these devices to be programmed as
fast as fourteen seconds, almost a hundred fold improvement over previous algorithms. Actual programming time is a function of the PROM programmer being used.

fication to determine when the address byte has
been successfully programmed. Up to 25 100 JLs
pulses per byte are provided before a failure is recognized. A flowchart of the Quick-Pulse Programming algorithm is shown in Figure 4.
For the Quick-Pulse Programming algorithm, the entire sequence of programming pulses and byte verifications is performed at Vee = 6.25V and Vpp at
12.75V. When programming of the EPROM has
been completed, all bytes should be compared to
the original data with Vee = Vpp = 5.0V.

The Quick-Pulse Programming algorithm uses initial
pulses of 100 microseconds followed by a byte veri5-110

infef

27C011

DC PROGRAMMING CHARACTERISTICS

25°C ±5°C

Table 3
Symbol

Limits

Parameter

III

Input Current (All Inputs)

VIL

Input Low Level (All Inputs)

VIH

Input High Level

VOL

Output Low Voltage During Verify

VOH

Output High Voltage During Verify

Min

Max

Units

p.A

-0.1

0.8

2.4

6.5

0.45

3.5

Test Conditions
(Note 1)
VIN

lee2(3)

Vee Supply Current (Program and Verify)

rnA

Vpp Supply Current (Program)

rnA

VIO

A9 inteligent Identifier Voltage

11.5

12.5

Vpp

Quick-Pulse Programming Algorithm

12.5

13.0

Vee

Quick-Pulse Programming Algorithm

6.0

6.5

VIL or VIH

= 2.1 mA
10H = - 2.5 p.A

10L

IpP2

VIL

AC PROGRAMMING CHARACTERISTICS
= 25°C ±5°C (See Table 3 for Vee and Vpp voltages.)

Symbol

Limits

Parameter

Typ

Min

Max

Units

tAS

Address Setup Time

p.s

tOES

OE Setup Time

p.s

tos

Data Setup Time

p.s

tAH

Address Hold Time

p.s

tOH

Data Hold Time

tOFP

OE High to Output Float Delay

tvps

Vpp Setup Time

p.s
p.s

tves

Vee Setup Time

teEs

CE Setup Time

tpw

PGM Program Pulse Width

tOE

Data Valid from OE

Conditions'
(Note 1)

p.s
130

(Note 2)

p.s
100

105

p.s

150

Quick-Pulse Programming

NOTES:

• AC CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) ...... 20 ns
Input Pulse Levels .................. 0.45V to 2.4V
Input Timing Reference Level ....... O.8Vand 2.0V
OutputTiming Reference Level ...... O.8V and 2.0V

1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp.
2. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no longer driven-see timing diagram.
3. The maximum current value is with outputs 00-07 unloaded.

5-111

intJ

27C011

PROGRAMMING WAVEFORMS
PROGRAM

v,"
ADDRESSES

V'H

DATA

VERIFY

ADDRESS STAlLE

-'''-

DATA IN STABLE

HIGHZ

1--'4"

DATA OUT vluD

..'D".

I+--'D'_

-1

K=
I..-

tOFP

12.75V

v..

,---I

5.0V
B.25V

Vee

-''''-

,---I I-',e,_
V,", \

s.ov

_'cES_

V,"

'ow

-'D"1

V,"

_'0'_

"\
290232-11

NOTES:
1. The Input Timing Reference Level is O.BV for a VIL and 2.0V for a VIH.
2. tOE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. The proper page to be programmea must be selected by a page-select write operation prior to programming each of the
four 16 Kbyte pages. See Page Select Write AC and DC Chara~eristics for information on page selection operations.

REVISION HISTORY
Number

Description

002

Remove 150 speed option

5-112

27C010
1M (128K x 8) CHMOS EPROM
• JEDEC Approved EPROM Pinouts
- 32-Pin DIP, 32-Pin PLCC
- Simple Upgrade from Lower
Densities
• Complete Upgrade Capability to Higher
Densities
•

Versatile EPROM Features
- CMOS and TTL Compatibility
- Two Line Control

• Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as 15
Seconds
• High-Performance
-1~O ns, ± 'iO% vcc
- 30 mA Icc Active
• Surface Mount Packaging Available
- Smallest 1 Mbit Footprint in SMT

Intel's 27C010 is a 5V only, 1,048,576-bit, Erasable Programmable Read Only Memory, organized as 129,536
words of 8 bits. It is pin compatible with lower density DIP EPROMs (JEDEC) and provides for simple upgrades
to 8 Mbits in the future in both DIP and PLCC.
The 27C010 represents state-of-the-art 1 micron CHMOS manufacturing technology while providing unequaled performance. Its 120 ns speed (tACC> offers no-wait-state operation with high performance CPUs in
applications ranging from numerical control to office automation to telecommunications.
Intel offerS two DIP profile options to meet your prototyping and production needs. The windowed ceramic DIP
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic DIP (PDIP) one-time programmable part provides a lower cost alternative that is well adapted for auto insertion. .
In addition to the JEDEC 32-pin DIP package, Intel also offers a 32-lead PLCC version of the 27C010. This
one-time-programmable surface mount device is ideal where board space consumption is a major concern or
where surface mount manufacturing technology is being implemented across an entire production line.
The 27C010 is equally at home in both a TTL or CMOS environment. It programs as fast as 15 seconds using
Intel's industry leading Quick~Pulse Programming algorithm.

vcc _

DATA OUTPUTS

0 0 -07

GND_

vpp_

OUTPUT BUFFERS

Y-GATING
Ag-A16
ADDRESS
INPUTS

1,048,578-BIT
CELL MATRIX

290174-1

Figure 1. Block Diagram '

5-113

September 1990
Order Number: 290174-004

27C010
Pin Names

512K

Ao-A'9

ADDRESSES

C'E

CHIP ENABLE

rn:

OUTPUT ENABLE

00-07
Pl.m

OUTPUTS

NO INTERNAL CONNECT

PROGRAM

27C010

aMbit

4Mblt

2Mblt

4Mblt

aMbit

A'9
A'6
A,s
A'2
Aj

Vpp

Vee

A'6
A,s
A'2
A7

PGN

0.8

.
__
TEST POINTS _ _ _

2.0

I·

~ lN914

OUTPUT

,0_..8_ _ __

0.45

RL
290174-6

DEVICE
UNDER
TEST

AC test inputs are driven at VOH (2.4V TTU for a Logic '"1'" and
VOL (0.45V TTU for a Logie '"0'". Input timing begins at VIH (2.0V
TTU and VIL (O.BV TTU. Output timing ends at VIH and VIL. Input
Rise and Fall Times (10% to 90%) ,; 10 ns.

OUT

i--

290174-7

CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 Kfl

AC WAVEFORMS
V,H-----'
ADDRESSES
V,, _ _ _ _ _J

V'H

V,H

\ ADDRESS
VALID

------+-_
------+----'""

V,H
OUTPUTS _ _ _ _ _..:H~IO::;.H:.:Z~_ _ _ _E_+~E_+_<

HIOHZ

290174-8

'5-118

inter

27C010

DEVICE OPERATION
The Mode Selection table lists 27C010 operating modes. Read Mode requires a single 5V power supply. All
inputs, except VCC and Vpp, and Ag during inteligent Identifier Mode, are TTL or CMOS.
Table 1. Mode Selection'
Notes

PGM

Vpp

Vee

Outputs

VIL

Vee

Dour

Output Disable

VIL

VIH

Vee

High:':

Standby

VIH

Vee

HighZ

Mode
Read

Program

VIL

VIH

VIL

Vpp

Vep

DIN'

Program Verify

VIL

VIH

Vpp

Vep

Dour

Program Inhibit

VIH

Vpp

Vep

HighZ

VIL

VIO

VIL

Vee

89H

VIL

VIO

VIH

Vee

35H

inteligent
Identifier

I Manufac~urer
I Device

2,3

VIL

NOTES:
1. X can be VIL or VIH.
2. See DC Programming Characteristics for VCP, Vpp and VIO voltages.
3. A1-AS, A1O-A16 = VIL.

Read Mode

multiple memory connections. Two-line control provides for:

The 27C01 0 has two control functions: both must be
enabled to obtain data at the ~uts. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (tCE)' Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.

a) lowest possible memory power dissipation

Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.

b) complete assurance that data bus contention will
not occur
To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.

Standby Mode

Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate

S~andby Mode substantially reduces VCC current.
When CE = VIH,the outputs are in a high imped.
ance state, independent of OE.

5-119

27C010

tiona!. The PGM and NC pins may be VIL or VIH. This
allows address lines A17-A18 to be routed directly
to these inputs in anticipation of future density upgrades. A jumper between Vee and A19 allows further upgrade using the Vpp pin. Systems designed
for 1-Mbit program memories today can be upgraded to higher densities (2-Mbit, 4-Mbit, and 8-Mbit) in
the future with no circuit board changes.

Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. AIthough only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".

SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (Iss), active current levels (Icc), and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 ,...F ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,...F electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances:

Program Mode is 'entered when Vpp is raised to
12.75V. Data is introduced by applying an 8-bit word
to the output pins. Pulsing PGM low while CE = VIL
and DE = VIH programs that data into the device.

Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
programmed. With Vee at 6.25V, a substantial pro9!!!m margin is ensured. The verify is performed with
CE at...Yu. and PGM at VIH. Valid data is available tOE
after OE falls low.

Program Inhibit
Program Inhibit Mode allows parallel pr29!'amming
of multiple EPROMs with different data. CE-high inhibi!!'programming of non-targeted devices. Except
for CE, parallel EPROMs may have common inputs.

inteligent Identifier™ Mode
The intellgent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with it's proper programming algorithm. '
This mode is activated when a programmer forces
12V ±0.5V on A9. With CE, OE, A1-A8, and A10A16 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.

UPGRADE PATH
Future upgrade to 2-Mbit, 4-Mbit, and 8-Mbit densities are easily accomplished due to the standardized
pin configuration of the 27C010. When the 27C010
is in Read Mode, the PGM input becomes non-func-

ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase
an EPROM in approximately 3 years, while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity X exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 ,...W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsecl
cm 2 (1 week @ 12000 ,...W/cm2).

5-120

intJ

27C010

290174-9

Figure 4. Quick-Pulse Programmlng™ Algorithm
mine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.

Quick-Pulse Programming n , Algorithm
The Quick-Pulse programming algorithm programs
Intel's 27C010. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C010 as fast as 15 seconds. Actual programming time depends on programmer overhead.

The entire program pulse/byte verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all bytes are compared to the original data with Vee = Vpp = 5.0V.

The Quick-Pulse programming algorithm employs a
100 p.s pulse followed by a byte verification to deter-

5-121

27C010

DC PROGRAMMING CHARACTERISTICS
Symbol

Parameter

Notes

= 25°C ±5°C

Min

Typ

Unit

Max

III

Input Load Current

Icp

Vcc Program Current

Ipp

Vpp Program Current

VIL

Input Low Voltage

-0.1

VIH

Input High Voltage

2.4

VOL

Output Low Voltage (Verify)

VOH

Output High Voltage (Verify)

3.5

VIO

A9 inteligent Identifier Voltage

11.5

12.0

12.5

2,3

12.5

12.75

13.0

6.0

6.25

6.5

Vpp

Vpp Program Voltage

Vcp

Vcc Supply Voltage (Program)

AC PROGRAMMING CHARACTERISTICS(4)
Symbol

Parameter

Test Condition

= VIL or VIH
= PGM = VIL
CE = PGM = VIL

p.A

VIN

0.8

6.5

0.45

V
V

= 2.1 mA
10H = -2.5mA

10L

TA = 25°C ±5°C

Notes

Min

Typ

Max

Unit

tvcs

Vcp Setup Time

p.s

tvps

Vpp Setup Time

,...s

teES

CE Setup Time

p.s

tAS

Address Setup Time

p.s

tos

Data Setup Time

tpw

PGM Program Pulse Width

tOH

Data Hold Time

p.s

tOES

OE Setup Time

p.s

tOE

Data Valid from OE

tOFP

OE High to Output High Z

tAH

Address Hold Time

5
5,6

0
0

p.s
100

105

p.s

150

130

ns
p.s

NOTES:
1. Maximum current is with outputs 00-07 unloaded.
2. Vcp must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming. a 0.1 p,F capacitor is required across Vpp and GNO to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. toE and tOFP are device characteristics but must be accommodated by the programmer.
S. Sampled. not 100% tested.
.

5-122

27C010

PROGRAMMING WAVEFORMS
VERIFY

PROGRAM

V,H

VII

ADDRESSES

_'AS,

DATA IN STAILE

DATA

ADDRESS STABLE

r=t-:L _'AH
-

HIGHZ

DATA OUT

V~LlD

IOFP

_'05_

>--

. . 'DH.

12.75V

,--.-1 _'''5_

Vpp

5_0V

6.25V

,--.-1 1-',e5_

Vee

5_0V

V,HI~

\
_'CU_

V, H

'.w

1-'0E5

V, H

1
\

'0'

290174-10

REVISION HISTORY
Number

Description

Revised general datasheet structure, text to improve clarity.
Added PDIP package
Combined TTL/NMOS and CMOS Read Operation DC Characteristics tables.
Deleted 4 Meg and 8 Meg PLCC pinout references.

5-123

27C100
1M (128K x 8) CHMOS EPROM
II! High Performance

• Pin Compatible with 28-Pln 1 Mbit
MASK ROM

- ±10% Vee
-120 ns Maximum Access Time
• Quick-Pulse Programmlng™ Algorithm
- Programming as Fast as 15 SecQnds
• 32-Pin CERDIP and PDIP Packages

• Low Power Consumption
- 30 rnA Max. Active
--: 100 /LA Ma~. Standby
.

• CMOS ~nd TTL Compatibility

Intel's 27G100 is a 5V-qnly, 1,048,576 bit, Erasable Programmabie Read Only Memory organized as 131,072
bytes of 8 bits. It employs advanced CHMOS· III E circuitry for systems requiring low power, high speed
performance and noise immunity. This device is pin compatible with 28-pin 1 Mbit MASK ROMs.
The 27C100's 120 ns speed (tACe) offers no-wait-state operation with high-performance CPUs in applications
ranging from numerical control to office automation and telecommunications. The 27C100 is equally at home
in both TIL a:nd CMOS environments.
Intel offers two DIP profile option$ to meet your prototyping and production needs. The windowed ceramic DIP
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic DIP (PDIP) one-time programmable part provides a lower cost !!-Iternative that is well adapted for auto insertion. This EPROM solution is particularly well-suited for "Just-In Time"
code customiza:tion to meet specific geographic or application needs in your product line. The Quick-Pulse
ProgramminQTM AlgOrithm provides fast, reliable programming.
'CHMOS is a patented procel?s of Intel Corporation.

DATA OUTPUTS

Vee ~o- - - ;..~
GND ~o- - - ;..~
VPPO

00-0 7

OUTPUT BUFFERS

Y-GATING

Ao- A 16

ADDRESS
INPUTS

X
DECODER

1,048,576-SIT
CELL MATRIX

290270-1

Figure 1. Block Diagram

5-124

October 1990
Order Numbe" 290270-002

inter

27C100

1 Mb Mask ROM

1 Mb Mask ROM
Vpp

Vee

PGt.l

A15
A12

A7
A6
A5
A4
A3
A2
A1

GND

A14
A13
As

CE
°7
°6

°0
°1
°2

Vee

A14
A13
As
Ag
A11
A16
A10

A2
Al
Ao

Ao
00
01

Os
°4
°3

GND

290270-2

Figure 2. DIP Pin Configuration
Pin Names
AO-A16

ADDRESSES

00-0 7

OUTPUTS

OUTPUT ENABLE

CHIP ENABLE

PGM

PROGRAM

NO CONNECT

5-125

Ag
A11
A16
A10
CE

07
06
05
04
03

27C100

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to chilnge without notice.

Operating Temperature ............. O·C to 70·C(1)
Temperature under Bias ........... -1 O·C to BO·C
Storage Temperature ............. - 65·C to 125·C
Voltage on Any Pin (except
Ag, Vee and Vpp)
with Respect to GND ......... - 0.6V to .6.25V(2)

Voltage on Ag with
Respect to GND ............... - 0.6V to 13V(2)
Vpp Program Voltage
with Respect to GND ........... -0.6V to 14V(2)
Vee Supply Voltage with
Respect to GND ................ - 0.6V to 7V(2)

READ OPERATION DC CHARACTERISTICS
Symbol

Parameter

III

Input Load Current

ILO

Output Leakage Current

ISB

Vee Standby Current

Notes

Min

Vee

Typ
0.01

5.0V ±10%

Max

Unit
p,A

VIN

p,A

VOUT

=
=

OV to 5.5V

oy to 5.5V

1.0

100

p,A

f = 5 MHz,
CE = VIL, lOUT

Vee Operating Current

Ipp

Vpp Operating Current

p,A

los

Output Short Circuit Current

4,6

100

VIL

Input Low Voltage

-0.5

O.B

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Vpp

Vpp Operating Voltage

Vee

+ 0.5

0.45
2.4
Vee - 0.7

1.0
±10

lee

Test Condition

Vee ±0.2V

0 mA

Vee

V
V
V

Vee

Vpp

VIH

= 2.1 mA
10H = - 400 p,A

10L

NOTES:

1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum DC voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. Maximum active power usage is the sum Ipp + Icc. Maximum current value is with outputs 00-07 unloaded.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Vpp may be connected directly to Vee or may be 1 diode voltage drop below Vee. Vee must be applied Simultaneously or
before Vpp and removed simultaneously or after Vpp.
6. Sampled, not 100% tested.
7. Typical limits are at Vee = 5V, TA = 25°e.
B. Absolute Maximum rating applies to Ne pins.

5-126

27C100

READ OPERATION AC CHARACTERISTICS(1)
Versions(4)
Symbol

27C100-120V10

Vee ±10%

Parameter

Notes

tAcc

Address to Output Delay

teE

CE to Output Delay

tOE

OE to Output Delay

tDF

OE High to Output High Z

tOH

Output Hold from
Addresses, CE or OE
Change- Whichever
Occurs First

Min

27C100-200V10
27C100-150V10
P27C100-150V10 P27C100-200V10 Unit
Min

Max

Min

Max

120

150

200

120

150

200

ns
\

NOTES:

1.
2.
3.
4.

Max

vcc = 5.0V ±10%

See AC Input/Output Reference Waveform for timing measurements.
OE may be delayed up to tCE-toE after the falling edge of CE without impact on teE,
Sampled, not 100% tested.
Model Number Prefixes: No Prefix = CERDIP, P = PDIP.

AC WAV,EFORMS
V,H - - - - - - , .
ADDRESS
VALID

ADDRESSES

VIl------I

1'----------....

V,H ---~-_+__..

V,H

------+----"\
'OF

1'7"""""",,- ••,•• - ......ri'l"'.-i

-+H+K

OUTPUTS _ _ _ _ _H:::;IO:::H:,.:Z_ _ _ _

HIOHZ

290270-6

5-127

27C100

CAPACITANCE(4)
Symbol

= 25°C, f = 1 MHz

Parameter

Typ(5)

Max

Unit

Condition

= OV
= OV
Vpp = OV

CIN

Input Capacitance

COUT

Output Capacitance

Cvpp

Vpp Capacitance

AC INPUT/OUTPUT REFERENCE WAVEFORM'

VIN

VOUT

AC TESTING LOAD CIRCUIT
1.3V

2.4

2.0>
0.8

TEST POINTS ____

2.0

OUTPUT
'1.,;0;,;;;.8___

0.45

290270-7
AC test inputs are driven at VOH (2.4 VTTU for a Logic
"1" and VOL (0.45 VTTU for a Logic "0". Input timing
begins at VIH (2.0 VTTU and VIL (0.8 VTTU. Output timing ends at VIH and VIL. Input rise and fall times (10%
to eO%) s; 10 ns.

t-~~-oOUT

290270-8
CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 KG

DEVICE OPERATION
The Mode Selection table lists 27C100 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, and Ae during inteligent IdentifierTM Mode, are TTL or CMOS.
Table 1. Mode Selection
Mode
Read

PGM

VIL

VIH

Output Disable
Standby
Program

Notes

Vpp

Vee

Outputs

VCC

Vee

DOUT

Vee

Vcc

HighZ

VIH

VCC

HighZ

VIL

VIH

VIL

Vpp

Vcp

DIN

Program Verify

VIL

VIH

Vpp

Vcp

DOUT

Program Inhibit

VIH

Vpp

VCP

HighZ

VIL

VID

VIL

Vee

Vce

B9H

VIL

VID

VIH

Vec

VCC

32H

inteligent Identifier
-Manufacturer
-Device

2,3

NOTES:
1. X can be VIL or VIH.
2. See DC Programming Characteristics for Vep, Vpp and VIO voltages.
3. Al-Ae, Al0-A16 = VIL.
'
4. Sampled, not 100% tested.
5. Typical limits are at Vee = 5V, TA = 25'C.

5-128

intJ

27C100

Read Mode

Program Mode

The 27C100 has two control functions; both must be
enabled to obtain data at the Q!!!puts. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (tCE). Outputs display valid
data toE after OE's falling edge, assuming tACC and
teE times are met.

Caution: Exceeding 14Von Vpp will permanently
damage the device.

Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. AI·
though only "Os" are programmed, the data word
can contain poth "1 s" and "Os". Ultraviolet light erasure is lile ouly way io cili:lllye "Os" io "Is".

Vee must be applied simultaneously or before
Program Mode is entered when Vpp is raised to
12.75V. Data is introduced by applying an a-bit word
to the output pins. Pulsing PGM low while CE = VIL
and OE = VIH programs that data into the device.

Vpp and removed simultaneously or after Vpp.

Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention wil!
not occur
To efficiently use these two control i~ts, an address decoder should enable CE while OE should be
connected to all memory devices and the system's
READ control line. This assures that only selected
memory devices have active outputs while deselected memory devices are in Standby Mode.

Standby Mode

Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
programmed with VCC at 6.25V, a substantial pro~m margin is ensured. The verify is performed with
CE at~ and PGM at VIH. Valid data is available tOE
after OE falls low.

Program Inhibit
Program Inhibit Mode allows parallel pr2.9!"amming
of multiple EPROMs with different data. CE-high inhibi~rogramming of non-targeted devices. Except
for CE, parallel EPROMs may have common inputs.

Standby Mode substantially reduces Vee current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.

5-129

inter

27C100

inteligent IdentifierTM Mode
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
This mode is activated when a programmer .forces
12V ±0.5V onAg. With A1-AS, A10-A16, CE and
OE at VIL, Ao = VIL will present the manufacturer's
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.

Two-Line Control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 /LF ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 /LF electrolytic
c;:apacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.

ERASURE CHARACTERISTICS
ROM Compatibility
The 27C100 is compatible with 28-pin mask ROMs
to provide a reprogrammable memory solution durc
ing prototyping and early production. Reference Figure 2; design in the 32-pin socket for the 27C100
EPROM and connect Vee to pins 1, 30 and 32. If the
EPROM is replaced with a MROM, socket pins 1, 2,
31 and 32 are' no longer required.

SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are in~
terested in 3.supply current issues-standby current
levels (Iss), active current levels (Icel, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device outputs' capacitive and inductive loading.

Erasure begins when EPROMs are expos~d to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase an
EPROM in approximately 3 years, while it takes approximately 1 week when exposed to direct sunlight.
If the device is exposed to these lighting conditions
for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
'
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537 A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 /LW/cm2 power rating.
The EPROM should be placed within 1, inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsec/
cm 2 (1 week @ 12000 jLW/cm 2 ).

5-130

inter

27C100

290270-10

Figure 3. Quick-Pulse Programming Algorithm

Quick-Pulse Programming Algorithm
The Quick-Pulse programming algorithm programs
Intel's 27C100. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C100 as fast as 15 seconds. Actual programming time depends on programmer overhead.

The Quick-Pulse programming algorithm e!"1ploys a
100 Il-s pulse followed by a byte verification to determine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.

5-131

The entire program-pulse/byte verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all bytes are compared to the original data with Vee = Vpp = 5.0V.

inter

27C100

DC PROGRAMMING CHARACTERISTICS TA = 25°C ± 5°C
Symbol

Parameter

Notes

Min

Unit

p.A

VIN = VIL or VIH

CE = PGM = VIL

CE =

-0·1

0.8

2.4

6.5

0.45

IOL = 2.1 mA

IOH = -2.5 mA

12.0

12.5

12.q

·12.75

13.0

6.0

6.25

6.5

Input Lo~d Current

Icp

Vcc Program Current

Ipp

Vpp Program Current

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage (Verify)

VOH

Output High Voltage (Verify)

:3.5
11.5
2,3
2

VIO

A9 intaligent Identifier Voltage

Vpp

Vpp Progral"!l Voltage

Vcp

Vcc Supply Voltage (Program)

Typ

Max

III

Test Condition

P~M =

VIL

.
.
AC PROGRAMMING
CHARACTERISTICS(4} TA = 25°C ± 5°C
.,
Symbol

Parameter

Typ

Notes

Min

tvcs

Vcp Setup Time

p.s

tvps

Vpp Setup Time

p.s

teES

CE Setup Time

p.s

tAS

Address Setup Time

p.s

tos

Data Setup Time

p.s

tpw

PGM Program Pulse Wiclth

tOH

Data Hold Time

toES

m: Setup Time

toE

Data Valid from OE

tOFP

OE High to Output High Z

tAH

Address Hold Time

100

Max

105

5,6

0
0

p.s
p.s

2
5

Unit

p.s
150

130

ns
p.s

NOTES:
'1. Maximum current is with outputs 00-0;: unloaded.
2. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 ""F capacitor is required between Vpp and GND to s!lPpress spurious voltage transients, which
can damage the device,
4. See AC Input/Output RefElren~e Waveform for timing mElasurements.
5. toE and tOFP are device characteristics but must be accommodated by the programmer.
S. Sampled. not 1QO% test~d.
.
.

5-132

inter

27C100

PROGRAMMING WAVEFORMS
PROGRAM
V,"
ADDRESSES

VERIFY

ADDRESS STABLE

I+--'AS ___

•

V,H
DATA

DATA IN STABLE

1--- 105 _ _

VIL

HIGHZ

X
_'A"

DATA OUT VALID

.'0" ...

IOFP

>--

12.75V

5.0V~

Vpp

I---IVP5_ _

6.25V
Vee
5.0V

V,"

Ce
V"

_',e5_

~
I-

tCES _ _

V,"

PGM
V"

v,"
Oe

-H-

I""-

10 ' 5 1

10'

290270-11

REVISION HISTORY
Description

Number

002

Deleted -120 PDIP package.
Revised classification from Advance Information to Preliminary.
Deleted Express Offerings.

5-133

'27C020
2M (256K x 8) CHMOS EPROM
• JEDEC Approved EPROM Pinouts
- 32-Pin DIP, 32-Pin PLCC
- Simple Upgrade from Lower
Densities
•

Complete Upgrade Capability to Higher
Densities

•

Versatile EPROM Features
- CMOS and TTL Compatibility
- Two Line Control

• Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as 30
Seconds
•

High~Performance

-150 ns, ± 10% Vce
- 30 mA Icc Active.

• Surface Mount Packaging Available
- Smallest 1 Mbit Footprint in SMT

Intel's 27C020 is a 5V-only, 2,097,152-bit Erasable Programmable Read .Only Memory, organized as 262,144
words of 8 bits each. It is pin compatible with lower density DIP EPROMs (JEDEC) and provides for simple
upgrades to 8 Mbits in the future in both DIP and PLCC.
The 27C020 represents state-of-the-art. 1 micron CMOS manufacturing technology while providing unequaled
performance. Its 150 ns speed (tACC> offers no-wait-state operation with high performance CPUs in applications ranging from numerical control to office automation to te.lecommunications.
Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic DIP
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic DIP (PDIP) one-time programmable part provides a lower cost alternative that is well adapted for auto insertion.
In addition to the JEDEC 32-lead DIP package, Intel also offers a 32-lead PLCC version of the 27C020. This
one-time-programmable surface mount device is ideal where .board space consumption is a major concern or
'
where surface mount manufacturing technology is being implemented across an entire production· line.
The 27C020 is equally at home in both a TTL or CMOS environment. It programs as fast as 30 seconds using
Intel's industry leading Quick-Pulse Programming algorithm.

DATA OUTPUTS

Vcc~

0 0 -0 7

GND 0 - - - - - - .
Vpp 0 - - - - - - .

OUTPUT BUFFERS

V-GATING.

Ao- A 17
ADDRESS
INPUTS

X
DECODER

2M BIT
CELL MATRIX'

290226-1

Figure 1. Block Diagram

5-134

September 1990
Order Number: 290226-003

intJ

27C020

Pin Names
Ao-A,9 ADDRESSES
CHIP ENABLE
CE
OE
OUTPUT ENABLE
0 0 .07
OUTPUTS
PGM
PROGRAM
NC
NO INTERNAL CONNECT

27CC20

8Mblt

4Mblt

1Mbit

A'9
A,6
A,s

Vpp
A,6
A,s

Vpp

vpp

vee

A'6
A,s

A16

PG"

A,s

Vpp

A'5

A17

Vee

A'2
A7
A6
As
A4
A3
A2
A,
AD
00
0,
02
GND

A'2
A7
A6
As
. A4

A'2
A7
A6
As
A4
A3
A2
A,
AD
00
0,
02
GND

A'2

A,.

A7
A.

A"
As

A3
A2
A,
AD
00
0,
02
GND

512K

256K

A2
A,

AlO

A'4
A,3
Aa
Ag
All
OE
AlO

°7

07
06
05
04
03

°5

°2

GNo

512K

Vee
A'4
A,3
Aa
Ag
A"
OElVpp
AlO
CE
07
06
05
04
03

1Mblt

4Mblt

8Mbit

Vec
PGM
N.C.

Vee
A,a

Vee
A,a
A17

A'4
A'3
Aa
Ag

A'7
A'4
A'3
Aa
Ag

All
OE
AlO
CE
07
06
05
04
03

A"
OE
AlO
CE
07
06
Os
04
03

290226-2

Figure 2. DIP Pin Configuration

290226-9

Figure 3. PLCC Lead Configuration

5-135

A'4
A,3
Aa
Ag
All
OElVpp
AlO
CE
07
06
05
04
03

27C020

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice.

Operating Temperature ...•......•.. O·C to 70·C(1)
Temperature Under Bias ........•.. -10·C to SO·C

Storage Temperature ............. -:- 65·C to 125·C
Voltage on Any Pin
(except Ag, Vee and Vpp)
with Respect to GND ..••...... - 0.6V to 6.5V(2)
Voltage on Ag with
Respect to GND •.•••.•.•••.• -0.6V to 13.0V(2)
Vpp Program Voltage
with Respect to GND ........••. -0.6V to 14V(2)
Vee Supply Voltage
with Respect to GND .....••.•. -0.6V to 7.0V(2)

READ OPERATION DC CHARACTERISTICS
Symbol
III
ILO
ISB

lee

Parameter
Input Load Current

Notes

Min

Output Leakage Current
. Vee Standby Current

Vee Operating Current

Ipp

Vpp Operating Current

los

Output Short Circuit Current

Vee

5.0V ±10%

Typ

Max

Unit

0.Q1

1.0

p.A

VIN

±10

p.A

1.0

= OV to 5.5V
= VIH
CE = Vee ±0.2V
CE = VIL
f = 5 MHz, lOUT = 0 mA
Vpp = Vee

100

p.A

4,6

100

O.S

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Vpp

Vpp Operating Voltage

Vee

+ 0.5

0.45
2.4
5

Vee - 0.7

Vee

Test Condition

OV to 5.5V

VOUT
CE

V
V

10L

10H

= 2.1 mA
= - 400 p.A

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for
periods <20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which, during transitions. may overshoot to Vee
+ 2.0V for periods <20 ns.
3. Maximum active power usage is the sum Ipp + lee. Maximum current is with outputs 00 to 07 unloaded.
4. Output shorted·for no more than one second. No more than one output shorted at a time.
5. Vpp may be connected directly to Vee. or may be one diode voltage drop below Vee. Vee must be applied simultaneously
or before Vpp and removed simultaneously or after Vpp.
6. Sampled. not 1'00% tested.
7. Typical limits are at Vee = 5V. TA = 25·C.

5-136

inter

27C020

READ OPERATION AC CHARACTERISTICS(1) vcc = 5.0V ±10%
Versions(4)
Symbol

vee ±10%

Parameter

27C020-150V10 .

Notes

Min

Max

27C020-200V10
P27C020-200V10
N27C020-200V10
Min

Unit

Max

150

200

150

200

OE to Output Delay

tDF

OE High to Output High Z

tOH

Output Hold from
Addresses, CE or OE
Change-Whichever is First

tACC

Address to Output Delay

tCE

CE to Output Delay

tOE

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to tCE-toE after the falling edge of CE without impact on toE.
3. Sampled, not 100% tested.
4. Model number prefixes: No Prefix = CERDIP, P = PDIP, N = PLCC.

5-137

inter

27C020

CAPACITANCE(1}

= 25°C, f = 1MHz

Parameter -

Symbol

Typ(2)

Max

Unit

VIN = OV

VOUT = OV

Vpp = OV

CIN

Input Capacitance

COUT

Output Capacitance

4
8

Cvpp

Vpp Capacitance

Conditions

NOTES:
1. Sampled, not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.

AC INPUT/OUTPUT REFERENCE WAVEFORM

1.3V

2.4
2.0>
0.45

AC TESTING LOAD CIRCUIT

~
TEST POINTS ~

0.6

2.0

OUTPUT
,,0;;,;;.6~_ _

!lN914

290226-4
RL
DEVICE
UNDER
TEST

AC testing inputs are driven at VOH (2.4 Vnu for a logic "1" and
VOL (0.45 VnL) for a logic "0". Input timing begins at VIH (2.0
Vnu and VIL (O.B VITu, Output timing ends at VIH and VIL. Input
rise and fall times (10% to 90%) ,;;10 ns.

CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 Kfl

OUT

f---

CL
290226-5

AC WAVEFORMS

.,H------,.
ADDRESS

ADDRESSES

VALID

VOL-----

V,H

VOL

V,H

-------t-""'"

1'-----------····
~-----+_-----"'\

V,H

~un--------~H~IG~H~Z----~~~~<

HIOHZ

290226-6

5-138

inter

27C020

DEVICE OPERATION
The Mode Selection table lists 27C020 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vcc and Vpp, and A9 during inteligent Identifier Mode, are TTL or CMOS.
Table 1. Mode Selection
Mode

Notes

PGM

Vpp

Vee

Outputs

VIL

Vcc

DOUT

Read
Output Disable

VIL

VIH

Vee

Vec

HighZ

Standby

VIH

Vcc

HighZ

VIL

VIH

VIL

Vpp

Vcp

DIN

VIL

VIH

Vpp

Vcp

DOUT

Program
Program Verify
Program Inhibit
inteligent
Identifier

I Manufacturer
I Device

2,3

VIH

Vpp

Vcp

HighZ

VIL

VID

VIL

Vcc

89H

VIL

VID

VIH

Vcc

34H

NOTES:
1. X can be VIL or VIH
2. See DC Programming Characteristics for VCP, Vpp, and VID voltages.
3. Al-Aa, AlO-A17 = VIL

a) lowest possible memory power dissipation

Read Mode
The 27C020 has two control functions; both must be
enabled to obtain data at the Q!:!!puts. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACc) equals the
. delay from CE to output (teE)' Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.
Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.

Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:

Standby Mode
Standby Mode substantially reduces Vcc current.
When CE = VIH the outputs are in a high impedance state, independent'of OE.

5-139

intJ

27C020

to this input in anticipation of future density upgrades. A jumper between Vee and A19 allows further upgrade using the Vpp pin. Systems designed
for 2-Mbit program memories today can be upgraded to higher densities (4-Mbit and 8-Mbit) in the future with rio circuit board changes.

Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.

SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (ISB), active current levels (lee), and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend On the
device output's capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 ,...F ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,...F electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board inductances.

Program mode is entered when Vpp is raised to
12.75V. Data is introduced by applying an 8-bit word
to the output pins. Pulsing PGM low while CE = VIL
and OE = VIH programs that data into the device.

Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
programmed. With Vee at 6.25V, a substantial pro~m margin is ensured. The verify is performed with
CE a~ and PGM at VIH. Valid data is available toE
after OE falls low.

Program Inhibit
ERASURE CHARACTERISTICS·

Program Inhibit Mode allows parallel prQ9!"amming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE, parallel EPROMs may have common inputs.

Inteligent IdentifierTM Mode
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
This mode is activated when a programmer forces
12V ±0.5V on Ag. With CE, OE, A1-AS, and A10A17 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.

UPGRADE PATH
Future upgrade to 4-Mbit and 8-Mbit densities are
easily accomplished due to the standardized pin
configuration of the 27C020. When the 27C020 is in
Read Mode, the PGM input becomes non-functional.
This allows address Une A1 S to be routed directly to

Erasure begins when EPROMs are exposed to light .
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase
an EPROM in approximately 3 years, while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537 A. The integrated dose (UV intensity X. exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an Ultraviolet lamp with a 12000 ,...W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsecl
cm 2 (1 week @ 12000 ,...W/cm2 ).

5-140

27C020

290226-7

Figure 4. Quick-Pulse Programming™ Algorithm

Quick-Pulse Programming™ Algorithm
The Quick-Pulse programming algorithm programs
Intel's 27C020. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C020 as fast as 30 seconds. Actual programming time depends on programmer overhead.

The Quick-Pulse programming algorithm employs a
100 ,""S pulse followed by a byte verification to determine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.
The entire program pulse/byte verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all bytes are compared to the original data with Vee = Vpp = 5.0V.

5-141

27C020

DC PROGRAMMING CHARACTERISTICS
Symbol

Parameter

TA = 25°C ±5°C

Notes

Min

Typ

Max

Unit

III

Input Load Current

Icp

Vcc Program Current

Ipp

Vpp Program Current

VIL

Input Low Voltage

-0.1

VIH

Input High Voltage

2.4

VOL

Output Low Voltage (Verify)

VOH

Output High Voltage (Verify)

3.5

VIO

Ag inteligent Identifier Voltage

11.5

12.0

12.5

2,3

12.5

12.75

13.0

6.0

6.25

6.5

Vpp

Vpp Program Voltage

VcP

Vcc Supply Voltage (Program)

AC PROGRAMMING CHARACTERISTICS(4)
Symbol

Parameter

Test Condition

!k A

VIN = VIL or VIH

CE = PGM = VIL

0.8

6.5

0.45

IOL = 2.1 mA

IOH = -2.5mA

TA = 25°C ±5°C

Notes

Min

Typ

Max

Unit

tvcs

Vcc Setup Time

!ks

tvps

Vpp Setup Time

!ks

tCES

CE Setup Time

!ks

tAS

Address Setup Time

!ks

tos

Data Setup Time

tpw

PGM Program Pulse Width

tOH

Data Hold Time

!ks

tOES

OE Setup Time

!ks

tOE

Data Valid from OE

tOFP

OE High to Output High Z

tAH

Address Hold Time

5
5,6

0
0

!ks
100

105

!ks

150

130

ns
!ks

NOTES:
1. Maximum current is with outputs 00':'07 unloaded.
2. VcP must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 ,."F capacitor is required across Vpp and GNO to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. tOE and tDFP are device characteristics but must be accommodated by the programmer.
6. Sampled, not 100% tested.

5-142

inter

27C020

PROGRAMMING WAVEFORMS
VERIFY

PROGRAM

V'H

ADDRESSES

ADDRESS STABLE

DATA IN STABLE

DATA

~'D'---'--

•

4O~T V~LlD

~1A5=:j

~'D".

HIGHZ

DATA

L
I+-"H

tOFP

12.15V

,---1 _',.,_

Ypp

5.0V

6.25V

Vee

,---1

5.0Y

l-'ve5_

~
I-Y,"

V,"
OE

'CES_

1005

..
V, l

-10E

290226-8

REVISION HISTORY
Number

003

Description
Revised general datasheet structure, text to improve clarity
Added PDIP package
Combined TTL/NMOS and CMOS Read Operation Characteristics tables
Revised classification from Advance Information to Preliminary
Deleted 4 Meg and 8 Meg PLCC pinout references.
·Deleted EXPRESS page.

5-143

27C040
4M (S12K x 8) CHMOS EPROM
• Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as 60
Seconds
• High-Performance
-150 ns, ± 10% Vee
- 50 mA lee Active

• JEDEC Approved EPROM Pinout
-32-Pln DIP
- Simple Upgrade from Lower
Densities
• Easy Upgrade Capability to 8 Mbit
Density,
•

Versatile' EPROM Features
- CMOS and TTL Compatibility
- Two Line Control

The Intel 27C040 is a 5V-only,4,194;304-bit Erasable Programmable Read Only Memory, organized as
524,288 words of 8 bits each. It is pin compatible with lower density DIP EPROMs (JEDEC) and provides for
simple upgrade to 8 Mbits in the future.
The 27C040 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled
performance. Its 150 ns speed (TACel offers no-wait-state operation with high performance CPUs in applications ranging from numerical, control to office automation to telecommunications.
The 27C040 is equally at home in both a TTL or CMOS environment. It programs as fast as 60 seconds using
Intel's industry leading Quick-Pulse Programming algorithm.

DATA OUTPUTS

vee O-O-----i...
GND

00-0 7

()oo- - - . , . "

OUTPUT BUFFERS

Y-GATING

Ao- A18
ADDRESS
INPUTS

X
DECODER

4,194,304-BIT
CELL MATRIX

290239-1

Figure 1. Block Diagram

5-144

September 1990
Order Number: 290239-002

27C040
Pin Names

00-0 7

ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
PROGRAM
OUTPUTS

NO INTERNAL CONNECT

Ao-A,9

OE
J5lm

.....,.."' .. '"

",",V"'IU

1Mbl!

2Mblt

8Mblt

vpp

Vee

256K

vee

A,.

PGM

NC
A14

A17
A,4
A,s

vee
A,s
A17
A'4
A'3
As
As
Al1
OElVpp
A10

8Mbl!

2Mbl!

1Mbl!

A,g
A,S

VPP
A,s

A'5
A,2
A7
As
A5
A4

A'5
A'2
A7
A5

A'5
A'2
A7
As
A5

A'5
A,2
A7
AS
A5

Vpp
A,2
A7
AS
A5

A'7
A,.
A,.
A.
A.

A:!

A3
A2
A,
Ao
00
0,
02
GND

A2
A,

Ao
00
0,
02
GND

512K

256K

Of
AIO

A,
A,

AO
00
0,

°7

GNO

°3

290239-2

Figure 2. DIP Pin Configuration

5-145

Vee
A,4

512K

A'3
As
Ag
Al1
OE
A,o

Vee
A'4
A'3
As
Ag
Al1
OElVpp
A,o

07
Oa
05
04
03

07
Os
05
04
03

A'3
Aa
Ag
Al1
OE
A10
CE
07
Oe
Os
04
03

As
As
Al1

DE
A,o
CE

Or
06
Os
04
03

CE
07.
Oe
Os
04
03

inter

27C040

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains information on
products in the sampling and'initial production phases
of development. The specifications are subject to
change without notice.

Operating Temperature ............. ooe to 70oe(1)
Temperature Under Bias ........... - 1ooe to aooe
Storage Temperature ............. - 65°e to 125°e
Voltage on Any Pin
(except Ag, VCC and Vpp)
with Respect to GND .......... - O.6V to 6.5V(2)
Voltage on Ag with
Respect to GND .....•....... - O.6V to 13.0V(2)

Vpp Supply Voltage with
Respect to GND ............... - O.6V to 14V(2)
VccSupply Voltage with
Respect to GND ............... -O.6V to 7.0V(2)

READ OPERATION DC CHARACTERISTICS
Symbol

Parameter

Notes

Vcc

Min

Typ

Max

Unit

Test Condition

= OV to 5.5V

III

Input Load Current

1.0

)-LA

VIN

ILO

Output Leakage Current

±10

)-LA

VOUT

Vee Standby Current

1.0

100

)-LA

CE = VIL
f = 5 MHz, lOUT

)-LA

Vpp

100

0.8

10L

= 2.1

10H

IS8

0.Q1

5.0V ±10%

Icc

Vee Operating Current

Ipp

Vpp Operating Current

los

Output Short Circuit Current

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Vpp

Vpp Operating Voltage

4,6

Vee

+ 0.5

0.45
2.4
5

Vee - 0.7

Vee

= OV to 5.5V

= VIH
= Vee

±0.2V

= 0 mA

Vee

V
mA

-400)-LA

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for
periods < 20 ns. Maximum DC voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee
+ 2.0V for periods < 20 ns.
3. Maximum active power usage is the sum Ipp + Icc. Maximum current is with outputs 00 to 07 unloaded.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Vpp may be connected directly to Vee, or may be one diode voltage drop below Vee. Vee must be applied simultaneously
or before Vpp and removed simultaneously or after Vpp.
6. Sampled, not 100% tested.
7. Typical limits are at Vee = 5V, TA = 25°C.

5-146

inter

27C040

READ OPERATION AC CHARACTERISTICS(1) vcc
Verslons(4)
Symbol

Vee ±10%

Parameter

tACC

Address to Output Delay

tCE

CE to Output Delay

tOE
t __

·ur

tOH

Notes

OE to Output Delay

5.0V ± 10%

27C040-150V10

27C040-200V10

Min

Max

Units

Max

150

200

150

200

ncui
.........
"''''.,
........ ·u: .......I ...
.,
_ ......
I
_ .... t' ••u. I

..."

Output Hold from Addresses, CE or
OE Change-Whichever is First

"~I

II~'

NOTES:
1. See AC Input/Output Reference, Waveform for timing measurements.
2. OE may be delayed up to tCE-toE after the falling edge of CE without impact on tCE.
3. Sampled, not 100% tested.
4. Model number prefixes: No prefix = CERDIP.
5. Typical values are for T A = 25"C and nominal supply voltages.

CAPACITANCE(3) TA '7

25"C, f = 1MHz'
Typ(5)

Max

Unit

CIN

Input Capacitance

COUT

Output Capacitance

Cvpp

Vpp Capacitance

Symbol

Parameter

AC INPUT/OUTPUT REFERENCE WAVEFORM

2.4
2.0>
0.45

0.8

TEST POINTS

Conditions

= OV
= OV
Vpp = OV
VIN

VOUT

AC TESTING LOAD CIRCUIT
1.3V
-r-

~~ lN914

2.0

OUTPUT
,'0;;,:;.8:;..._ _

290239-3

DEVICE
UNDER
TEST

AC test inputs are driven at VOH (2.4 VnLl for a logic "1" and
VOL (0.45 VnLl for a logic "0". Input timing begins at VIH
(2.0 VnLl and VIL (O.S VnLl. Output liming ends at VIH and VIL.
Input rise and fall times (10% to 90%) ,;; 10 ns.

CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 Kn

5-147

t--+--oOUT

290239-4

inter

27C040

AC WAVEFORMS

V,. _____
ADDIIUS
VALID

ADDRESSES

VIL----- 1'----------....

I---ICE---+\

V,.

-------r---"""

V,.
HIOHZ

oo~~S _ _ _ _ _~H='Q~H~Z_ _ _ _ _ _~ti~~

290239-5

DEVICE OPERATION
The Mode Selection table lists 27C040 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, and A9 during inteligent Identifier Mode, are TIL or CMOS.
Table 1. Mode Selection
Mode

Notes

Vpp

Vee

Read

VIL

Vee

Dour

Output Disable

VIL

ViH

Vee

HighZ

Standby

VIH

Vee.

Vee

HighZ

Program

Program Verify
Program Inhibit
inteligent
Identifier

I
I

Manufacturer
Device

2,3

Outputs

VIL

VIH

Vpp

Vep

DIN

VIH

VIL

Vpp

Vep

Dour

VIH

Vpp

Vep

HighZ

VIL

VIO

VIL

Vee

89H

VIL

VIO

VIH

Vee

3DH

NOTES:
1. X can be VIL or VIH
2. See DC Programming Characteristics for Vcp, Vpp and VIO voltages.
3. Al-Aa, Al0-Ala. = VII:

5-148

inter

27C040

Read Mode
The 27C040 has two control functions; both must be
enabled to obtain data at the outputs. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (tCE). Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.

Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.

Two Line Output Control

Program Mode is entered when Vpp is raised to
12.75V. Data is introduced by applying an a-bit word
to the output pins. Pulsing CE low while OE = VIH
programs that data into the device.

Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
~fugfilIYIl-fl~u. vvm-, Vee at O.25V it suusiafli.iai tJIUgram margain is ensured. The verify is performed
with CE at VIH. Valid data is available toE after OE
falls low.

Program Inhibit

EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for: .
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur

Program Inhibit Mode allows parallel prQg!'amming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE and OE, parallel EPROMs may have common
inputs.

inteligent IdentifierTM Mode

To efficiently use these two control inputs, and address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.

The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.

Standby Mode

This mode is activated when a programmer forces
12V ±0.5V on Ag. With CE, OE, A1-A8, and A10A18 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.

Standby Mode substantially reduces VCC current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.

UPGRADE PATH

Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".

Future upgrade to the a Mbit density is easily accomplished due 1to the standardized pin configuration of the 27C040. A jumper between VCC and A19
allows upgrade using the Vpp pin. Systems designed
for 4 Mbit program memories today can be upgraded
to a Mbit in the future with no circuit board changes.

5-149

inter

27C040

SYSTEM CONSID~RATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (Iss), active current levels (lcd, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive arid inductive loading.
Two-line control and. proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 JlF ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 JlF electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor viill overcome voltage slumps caused by PC
board trace inductances.
.

Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase an
EPROM in approximately 3 years, while it takes approximately 1 week when exposed to direct sunlight.
If the device is exposed to these. lighting conditions
. for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/ cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 JlW/cm2 powerrating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds
7258 Wsec/cm 2 (1 week @ 12000 JlW/cm2).

ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000

5-150

27C040

290239-6

Figure 3. Quick-Pulse Programming Algorithm

Quick-Pulse Programming™ Algorithm
The Quick-Pulse Programming Algorithm programs
Intel's 27C040. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C040 as fast as 60 seconds. Actual programming time depends on programmer overhead.

mine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.

The Quick·Pulse Programming Algorithm employs a
100 J.Ls pulse followed by a byte verification to deter-

5·151

The entire program pulse/byte verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all bytes are compared to the original data with Vee = Vpp = 5.0V.

27C040

DC PROGRAMMING CHARACTERISTICS TA = 25°C ±5°C
Symbol

Parameter

III

Input Load Current

Notes

Min

Typ

Max

Unit

Test Condition

}LA

VIN = VIL or VIH

ICp

Vcc Program Current

CE = VIL

Ipp

Vpp Program Current

VIL

Input Low Voltage

-0.1

VIH

Input High Voltage

2.4

VOL

Output Low Voltage (Verify)

VOH

Output High Voltage (Verify)

VIO

Ag inteligent Identifier Voltage

Vpp

Vpp Program Voltage

Vcp

Vcc Supply Voltage (Program)

Parameter

6.5

0.45
3.5

10L = 2.1 mA

10H = -2.5mA

11.5

12.0

12.5

2,3

12.5

12.75

13.0

6.0

6.25

6.5

AC PROGRAMMING CHARACTERISTICS(4)TA
Symbol

·0.8

= VIL

= 25°C ±5°C

Notes

Min

Typ

Max

Unit

tvcs

Vcp Setup Time

}Ls

tvps

Vpp Setup Time

}Ls

tAS

Address Setup Time

}Ls

tos

Data Setup Time

}Ls,

tpw

CE Program Pulse Width

tOH

Data Hold Time

tOES

OE Setup Time

tOE

Data Valid from OE

tOFP

OE High to Output High Z

tAH

Address Hold Time

100

105

}Ls

2
5
5,6

}Ls
150

0
0

}Ls

130

ns
ns

}Ls

NOTES:
1. Maximum current is with outputs 00-07 unloaded.
2. Vep must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 ",F capacitor is required across Vpp and ground to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. toE and tDFP are device characteristics but must be accommodated by the programmer.
6. Sampled, not 100% tested.

5-152

intJ

27C040

PROGRAMMING WAVEFORMS
! 4 - - - - - - P A O G . A M - - - - - - i - - - - V••,fY - - - - I

v,"
ADO.ESSES

v"
IA.
'';IH

HIGHZ

DATA
VII

12.75Y
Vpp
S.OV
UsV

vee
S.OV

v,"
CE
v"
·OES

10.

v,"
iI£

v"
290239-7

REVISION HISTORY
Number

\ Description
Revised general datasheet structure, text to improve clarity.
Combined TTL/NMOS and CMOS Read Operation DC Characteristics Tables.
Mode Selection table-Program Inhibit-OE revised from X to VIH.

5-153

27C210
. 1M (64K x 16) CHMOS EPROM
• High-Performance
-120 ns ±10% Vcc
,- 50 rnA Icc Active
• Fast Programming
- Quick-Pulse Programming™
Algorithm
.:- Programming Times As Fast As
. 8 Seconds

• JEDEC Approved EPROM Pinouts
-40-Pin DIP
- 44-Pin PLCC
• Complete Upgrade to Higher Densities
• Versatile EPROM Features
- CMOS and TTL Compatibility
- Two Line Control

Intel's 27C210 is a 5V only, 1,048,576-bit Erasable Programmable Read Only Memory, organized as 65,536
words of 16 bits each. Its standard pinouts provide for simple upgrades to 4 Mbits in the future.
The 27C210 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled
performance. Its 120 ns speed (tACe) offers no-wait-state operation with high performance CPUs in applications ranging from numerical control to office automation to telecommunications.
Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic dip
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic dip (PDIP) one-time programmable part provides a lower cost alternative
that is well adapted for auto insertion.
.
In addition to the JEDEC 40-pin DIP package, Intel also offers a 44-lead PLCC version of the 27C210. This
one-time-programmable surface mount device is ideal where board spac~ consumption is a major concern or
where surface mount manufacturing techn?logy is being implemented across an entire production line.
The 27C21 0 is equally at home in both a TTL or CMOS environment. And like Intel's other 1 Mbit EPROMs,
the 27C210 programs quickly using Intel's industry leading Quick-Pulse Programming algorithm.

Vee

DATA OUTPUTS
00-0 15

•

GND~

Vpp 0

•

. OUTPUT BUFFERS

V-GATING

Ao- A 15
ADDRESS
INPUTS

X
DECODER

1,048,576-BIT
CELL MATRIX

290193-1

Figure 1. Block Diagram

5~154

, September 1990
Order Number: 290193.003

inter

Pin Names
lAo-Ani ADDRESSES
vI:
CHI~ t=i. . Ai3LE
OE
OUTPUT ENABLE
OO.Q1S OUTPUTS
PROGRAM
PGM
NO INTERNAL CONNECT
NC

27C210

Vpp

Vpp·

VPP

vee

015
01'
0 13
012
011
010

CE
°°15_
1

PGM
Ne

0 15
0 1,
0 13
012
011
010
0:::
08
GND
07
06
Os
0,
03
02
01
00

O"E

('I:::

08
GND
07
06
Os
0,
03
02
01

°13
°12
°11
°10

Vee

PGM

A1S
Al_
A13
A12
All

A16
A1S
Al'
A13
.A12
All

Ai7
A16
A15
A14
A13
A12
All

"IU

.A.~y

.A·i;j

As
GND
A7

Ag
GND
A8
A7

As
A4
A3
A2
Al
Ao

As
A,
A3
A2
Al
Ao

Os
GND

GND

AS
A7
A6
AS

°7
°6
°5

°3
O2
01
00

A-

A3
A2
Al

290193-2

Figure 2. DIP Pin
Configuration

290193-3

Figure 3. PLCC Lead Configuration

5-155

inter

27C210

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature ......•....•. O°C to 70°C(1)

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond ·the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Temperature Under Bias .........•. -10°C to. 80°C
Storage Temperature ......•...... - 65°C to 125°C
Voltage on Any Pin
(except Ag, Vee and Vpp)
with Respect to GND ......•. -0.6V to 6.5V(2, 8)

Notice: Specifications contained within the following
tables are subject to change.

Voltage on Ag with
Respect to GND ......•....•. - 0.6V to 13.0V(2)
Vpp Program Voltage
with Respect to GND ......•.... -0.6Vto 14V(2)
Vee Supply Voltage
with RespeCt to GND ..•....... - 0.6V to 7.0V(2)

READ OPERATION DC CHARACTERISTICS(1)
Symbol
III

Parameter
Input Load Current

Notes

Min

Vee

5.0V ±10%

Typ

Max

Unit

0.01

1.0

/LA

VIN

Test Condition

OVtoVee

ILO

Output Leakage Current

±10

/LA

VOUT

ISB

Vee Standby Current

1.0

rnA

100

/LA

lee

Vee Operating
Current

rnA

CE
VIL
f = 5 MHz, lOUT

Ipp

Vpp Operating Current

/LA

Vpp

los

Output Short
Cir~uit Current

4,6

100

rnA

VIL

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

2.0

Vee +0.5

VOL

Output Low Voltage

0.45

10L

VOH

Output High Voltage

10H

= 2.1 rnA
= -400/LA

Vpp

Vpp Operating Voltage

2.4
5

Vee - 0.7

Vee

=
=
=

OV to Vee

VIH
Vee ±0.2Y

0 rnA

Vee

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -0.5V on input/output pins. During tranSitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. Maximum active power usage is the sum Ipp + lee. Maximum current value is with outputs 00 to 015 unloaded.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Vpp may be connected directly to Vee, or may be one diode voltage drop below Vce. Vee must be applied simultaneously
or before Vpp and removed simultaneously or after Vpp.
6. Sampled, not 100% tested.
7. Typical limits are at Vee = 5V, TA = 25·C.
8. Absolute Maximum ratings apply to Ne pins.

5-156

inter

27C210

READ OPERATION AC CHARACTERISTICS(1) vcc

vee ± 10%

Verslons(4)
Parameter

Symbol
tACC

Address to Output Delay

teE

CE to Output Delay

27C210·120V10

Notes

Min

5.0V ±10%

27C210·150V10
P27C210·150V10
N27C210·150V10

Max

Min

Max

150

200

120

150

200

OE to Output Delay

tOF

OE High to Output High Z

Unit

120

toE

Output Hold from
Addresses, CE or OE
Change-Whichever is
First

Min

Max

toH

27C210·200V10
P27C21D-200V10
N27C210·200V10

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to teE-tOE after the falling edge of CE without impact on tCE.
3. Sampled, not 100% tested.
4. Model Number Prefixes: no prefix = CERDIP, P = PDIP, N = PLCC.
5. Typical limits are set for TA = 25°C and nominal supply voltages.

CAPACITANCE(3)
Symbol

Parameter

1 MHz

Typ(S)

Max

Unit

VIN = OV

VOUT = OV
Vpp = OV

CIN

Input Capacitance

COUT
Cvpp

Output Capacitance

4
8

Vpp Capacitance

AC INPUT/OUTPUT REFERENCE WAVEFORM

25°C, f

Conditions

AC TESTING LOAD CIRCUIT
1.3V

2.4~
0.45

:::

POINTS<=::

2.0

OUTPUT

lN914

0.8

290193-6
DEVICE
UNDER
TEST

AC test inputs are driven at VOH (2.4 Vnu for a Logic "I" and
VOL (0.45 Vnu for a Logic "0". Input timing begins at VIH
(2.0 Vnu and VIL (O.B Vnu. Output timing ends at VIH and VIL.
Input Rise and Fall times (10% to 90%) ,;: 10 ns.

CL = 100pF
CL Includes Jig Capacitance
RL = 3.3 kfl

5·157

OUT

i--

Cl
290193-7

intJ

27C210

AC WAVEFORMS
VI"----~
ADDRESS-

ADDRESSES

VALID

V,, _ _ _ _- - '

V," _ _ _ _ _

_+_~

V," _ _ _ _ _-+____

'""
V,"
OUTPUTS _ _ _ _ _;;;HIO~H;.:Z_ _ _ __+H*'H

HIGHZ

290193-8

DEVICE OPERATION
The Mode Selection table lists 27C21 0 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vcc and VPP, and Ag during inteligent Identifier Mode, are TTL or CMOS.
Table 1. Mode Selection
Notes

PGM

Vpp

Vee

Outputs

VIL

Vec

Vee

DOUT

Output Disable

VIL

VIH

Vee

Vce

HighZ

Standby

VIH

Vee

HighZ

Mode
Read

VIL

VIH

VIL

Vpp

Vep

DIN

Program Verify

VIL

VIH

Vpp

Vep

DOUT

Program Inhibit

VIH

Vpp

.Vcp

HighZ

VIL

VID

VIL

Vee

0089 H

VIL

VID

VIH

Vee

11EEH

Program.

inteligent
Identifier

I
I

Manufacturer
Device

2,3

NOTES:

1. X can be VIL or VIH
2. See DC Programming Characteristics for Yep. Vpp and VID voltages.
3. A1-A8. A1Q-A15 = VIL

5-158

intJ

27C210

Read Mode

Program Verify

The 27C21 0 has two control functions; both must be
enabled to obtain data at the outputs. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (tCE)' Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.

A verify should be performed following a program
operation to determine that bits have been correctly
programmed. With Vcc at 6.25V, a substantial program margin is ensured. The verify is performed with
CE a~ and PGM at VIH. Valid data is available tOE
after OE falls low.

i=rogram inhiDii
Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.

Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power dissipation .
b) complete assurance that data bus contention will
not 'occur
To efficiently use these two control inputs, an ad~
dress decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.

Program Inhibit Mode allows parallel programming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE, parallel EPROMs may have common inputs.

,inteligent IdentifierTM Mode .
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with it's proper programming algorithm.
This' mode is activated when a programmer forces
12V ± 0.5V on Ag. With CE, OE, A1-Aa, and A1OA15 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.

UPGRADE PATH

Standby Mode
Standby Mode substantially reduces VCC current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.

Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".

Future upgrades to 2 Mbit and 4 Mbit densities are
easily accomplished due to the standardized pin
configuration of the 27C210. When the 27C21 0 is in
Read Mode, the PGM input becomes non-functional.
The PGM and NC pins may be VIL and VIH. This
allows address lines A16-A17 to be routed directly
to these inputs in anticipation of future density upgrades. Systems designed for 1 Mbit program memories today can be upgraded to higher densities (2
Mbit and 4 Mbit) in the future with no circuit board
changes.

Program Mode is entered when Vpp is raised to
12.75V. Data is introduced by applying a 16-bit word
to the output pins. Pulsing PGM low while CE = VIL
and OE = VIH programs that data into the device.

5-159

inter

27C210

SYSTEM CONSIDERATIONS

ERASURE CHARACTERISTICS

EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (ISB), active current levels (Ieel, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 ,...F ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,...F electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.

Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase
an EPROM in approximately 3 years, while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an Ultraviolet lamp with a 12000 ,...W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose ,exceeds 7258
Wsec/cm 2 (1 week @ 12000 ,...W/cm2).

5-160

inter

27C210

290193-9

Figure 4. Quick-Pulse Programming™ Algorithm

Quick-Pulse Programming™ Algorithm
The Quick-Pulse Programming algorithm programs
Intel's 27C210. Developed to substantially reduce
programming t/lroughput, this algorithm can program
the 27C210 as fast as 8 seconds. Actual programming time depends on programmer overhead.

The Quick-Pulse Programming algorithm employs a
100 ,""S pulse followed by a word verification to de·
termine when the addressed word has been successfully programmed. The algorithm terminates if
25 attempts fail to program a word. '
The entire program pulse/word verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all words are compared to the original data with Vee = Vpp = 5.0V.

5-161

intJ

27C210

DC PROGRAMMING CHARACTERISTICS
Symbol

Parameter

TA = 25°C ±5°C

Min

Typ

Max

Unit·

,...A

VIN

,mA

0.8

Notes

III

Input Load Current

Icp

Vcc Program Current

Ipp

Vpp Program Current

VIL

Input Low Voltage

-0.1

VIH

Input High Voltage

2.4

VOL

Output Low Voltage (Verify)

6.5

0.45

VOH

Output High Voltage (Verify)

3.5

VIO

Ag intaligent Identifier Voltage

11.5 '

12.0

12.5

2,3

12.5

12.75

13.0

6,.0

6.25

6.5

Vpp
Vcp

, Vpp Program Voltage
Vcc Supply Voltage (Program)

AC PROGRAMMING CHARACTERISTICS(4)
Symbol

Parameter

Notes

Test Condition

= VIL or VIH
= PGM = VIL
= PGM = VIL

= 2.1 mA
IOH = -2.5 mA

10L

25°C ± 5°C

Min

Typ

Max

Unit

tvcs

Vcp Setup Time

tvps

Vpp Setup Time

,...s

tees

CE Setup Time

,...s
,...s

,...s

tAS

Address Setup Time

tos

Data Setup Time

tpw

PGM Program Pulse Width

tOH

Data Hold Time

,...s

toes

OE Setup Time

,...s

toe

Data Valid from OE

tOFP

OE High to Output High Z

tAH

Addr~ss

5
5,6

Hold Time

0
0

,...s
100

105

,...s

150

130

ns
,...s

NOTES:
1. Maximum current is with outputs 00-015 unloaded.
2. Vep must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 p.F capaCitor is required across Vpp and GND to suppress spurious voltage transients which
,'.
,
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. tOE and tOFP are device characteristics but must be accommodated by the programmer.
6. Sam·pled,. not 100% tested.

5-162

27C210

PROGRAMMING WAVEFORMS
VERIFY

PROGRAM

---")

ADDRESSES

ADDRESS STABLE

_I"j

DATA

DATA IN STABLE

r--- IO' _ _

•

HIGHZ

I+IOH.

-:1
l

~_IA"

DATA OUT VALID
tOFP

12.75V
Vp p

S.OV

---11---

1",_ _

6.25V

,~ I-Ivc,_

Vee

5.0V

i\
I--

ICES _ _

,}{

_IOES_j
I+-

V, H

V, L

10E

---.

REVISION HISTORY
Number

Description
Revised gen~ral datasheet structure, text to improve clarity
Revised speed bin as follows:
tACC was 130 ns, is now 120 ns
teE was 130 ns, is now 120 ns
tOE was 60 ns, is now 55 ns
Added PDIP package
Revised IS9 Text Condition from CE = Vee to CE = Vee ± 0.2V
Revised VOL from 0.4V to 0.45V
Revised VOH from Vee - O.BV to 2.4V
Deleted 8 meg DIP, 4 and 8 Meg PLCC references
Deleted EXPRESS page

5-163

290193-10

27C220

2M (128K

x 16) CHMOS EPROM
Programming
• -FastQuick-Pulse
Programming™

JEDEC Approved EPROM Pinouts
• -40-Pin
DIP

Algorithm
- Programming Times As Fast As
15 Seconds

- 44-Pin PLCC
EPROM Features
• -Versatile
CMOS and TTL Compatibility
- Two Line Control
High-Performance
• -150
ns ± 10% Vee

Mount Packaging Available
• Surface
• Complete Upgrade to Higher Densities

- 50 mA lee Active
Intel's 27C220 is a 5Vonly, 2,097,152-bit Erasable Programmable Read Only Memory. Organized as 131,072
words of 16 bits each. It is pin compatible with Intel's 1 Mbit 27C210 and provides for a simple upgrade to
4 Mbits in the future.
The 27C220 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled
performance. Its 150 ns speed (tACe) offers no-wait-state operation with high performance CPUs in applications ranging from numerical control to office automation to telecommunications.
Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic dip
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once tlie
design is in full production, the plastic dip (PDIP) one-time programmable part provides a lower cost alternative
that is well adapted for auto insertion.
In addition to the JEDEC 40-pin DIP package, Intel also offers a 44-lead PLCC version of the 27C220. This
one-time-programmable surface mount device is ideal where board space consumption is a major concern or
where surface mount manufacturing technology is being implemented across an entire production line.
The 27C220 is equally at home in both a TTL or CMOS environment. And like Intel's other high density
EPROMs, the 27C220 programs quickly using Intel's industry leading Quick-Pulse Programming algorithm.

DATA OUTPUTS

Vee <>-0--••
GND<>-o--••
Vpp 0

00-0 15

•

OUTPUT BUFFERS

V-GATING
AO-A16
ADDRESS
INPUTS

X
DECODER

2,097,152-BIT
CELL MATRIX

290217-1

Figure 1. Block Diagram

5-164

October 1990
Order Number: 290217-005

inter

Pin Names

lAo-A,R ADDRESSES
CE

CHIP ENABLE

OUTPUT ENABLE

00.0 ,5 OUTPUTS
PROGRAM
PGM
NC

NO INTERNAL CONNECT

27C220

Vpp

Vee

PGM

PlThi

015
0,4
0,3
0,2

0,5
0,4
0 ,3
0 ,2

A"
A,.

A'7
A,S

0"
0,0
09

A"
All

A'5
A'4
A'3
A'2
A"
A'0

A'5
A'4
A 3
'
A'2
A"
A'0

GND

A"
A"

A,o
O.
GND

Os
05
04
03
02
0,
00

C5E

GND

Aa
A7
As
A5

Aa
A7

A7
A,
A,
A.
A3

~
A3
A2
A,
Ao

As
A5
~

A3
A2
A,

290217-2

Figure 2. DIP Pin Configurations

44 LEAD PLCC

0.650" x 0.650"
TOP VIEW

290217-14

Figure 3. PLCC Lead Configuration

5-165

27C220

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change' without notice.

Operating Temperature .......•..... O°C to 70°C(1)
Temperature Under Bias ........... -10°C to 80°C
Storage Temperature ......... '.... - 65°C to 125°C
Voltages on Any Pin '
(except A9, Vee and Vpp)
with Respect to GND .......... - O.6V to 6.5V(2)

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These' are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Voltage on A9 with
Respect to GND ............. - 0.6V to 13.0V(2)
Vpp Supply Voltage
with Respect to GND ........... ~ 0.6V to 14V(2)
Vee Supply Voltage
with Respect to GND ........... ,~ 0.6V to 7.0V(2)

READ OPERATION DC CHARACTERISTICS

Vee

Symbol

Typ

Parameter

Notes

Min

5.0V ±10%
Max

Unit

Test Condition

III

Input Load Current

1.0

p.A

VIN

ILO

Output Leakage Current

±10

p.A

VOUT

IS8

Vee Standby Current

1.0

rnA

p.A

=
=

VIH

100
50

rnA

VIL

lee

Vee Operating Current

0.01

OV to Vee

Vee ±0.2V

f = 5 MHz, lOUT = 0 rnA
Ipp

Vpp Operating Current

los

Output Short Circuit Current

VIL

Input LowVoltage

-0.5

VIH

Input HighVoltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Vpp

Vpp Operating Voltage

3
4,6

p.A

100

rnA

0.8

Vee

+ 0.5

0.45
2.4
5

Vee - 0.7

Vee

V
V
V

Vee

Vpp

= 2.1 rnA
10H = - 400 p.A

10L

NOTES: ,
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -O.SV on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + O.SV which, during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. Maximum active power usage is the sum Ipp + Icc. Maximum current is with outputs 00 to 015 unloaded.
4. Output shorted" for no more than one second. No more than one output shorted at a time.
S. Vpp may be connected directly to Vee, or may be one diode voltage drop below Vee. Vee must be applied simultaneously
or before Vpp and removed simultaneously or after Vpp.
6. Sampled, not'100o;.,'tested.
7. Typical limits are at Vee = SV, TA = 2Soe.

5-166

intJ

27C220

READ OPERATION AC CHARACTERISTICS(1)
Versions(4)
Symbol

5.0V ±10%
27C220-200V 10
P27C220-200V 10
N27C220-200V10

27C220-150V10

Vcc ±10%

Parameter

vcc

Notes

Min

Max

Min

Units

Max

tAcC

Address to Output Delay

tCE

CE to Output Delay

150

200

tOE

OE io OuifJui ut:liaY

'1':"1"1.

tOF

OE High to Output High Z

tOH

Output Hold from _
Addresses, CE or OE
Change-Whichever is'First

150

200

ns
ns

,,~

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. DE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE.
3. Sampled, not 100% tested.
4. Model Number Prefixes: No Prefix = CERDIP, P = PDIP, N = PLCC.
5. Typical limits are for TA = 25°C and nominal supply voltages.

CAPACITANCE(3)
Symbol
GIN
GOUT
Cvpp

25°C, f

1MHz

Parameter

Typ(5)

Max

Unit

Input Capacitance
Output Capacitance

8
12
25

Vpp Capacitance

AC INPUT/OUTPUT REFERENCE WAVEFORM

8
18

pF
pF

Conditions
VIN

= OV

VOUT = OV
Vpp = OV

AC TESTING LOAD CIRCUIT
1.3V

2.4
0.45

2.0>'
____
TEST POINTS _ _
0.8

2.0

lNB14
OUTPUT
__

~0.8=--

RL
290217-6

DEVICE
UNDER
TEST

AC test inputs are driven at VOH (2.4 VTTL) for a logic "1" and
VOL (0.45 V-riLl for a logic "0". Input timing begins at VIH (2.0
VnLl and VIL (O.B VnLl. Output timing ends at VIH and VIL' Input
rise and fall times (10% to 90%) ,;; 10 ns.
CL=100pF
CL Includes Jig Capacitance
RL = 3.3 kll

5-167

""'OUT

290217-7

27C220

AC WAVEFORMS
V," _ _ _ __
ADOIIEIIS

ADOIIUSES

VALID

V,, _ _ _ __

v," _ _ _ _ _-+__

I-v," _ _ _ _ _-+___
_- l c e - - - i

v,"
~

_____

H~IG~H~Z

____

HIGHZ

~~~r<

290217-8

DEVICE OPERATION
The Mode Selection table lists 27C220 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, ~nd Ag during inteligent Identifier Mode, are TTL or CMOS.
Table 1. Mode Selection
Mode

Notes

Read

Output Disable
Standby

PGM

VIL

X(I)

VIL

VIH

Vpp

Vee

DOUT

Vee

HighZ

Vee

Outputs

VIH

X·

Vee

HighZ

VIL

VIH

VIL

Vpp

Vep

DIN

Program Verify

VIL

VIH

Vpp

Vep

DOUT

Program Inhibit

VIH

Vpp

Vep

HighZ

VIL

VIO

VIL

Vee

0089H

VIL

VIO

VIH

Vee

22EEH

Program

inteligent
Identifier

I Manufacturer
I Device

2,3

NOTES:

1. X can be VIL or VIH
2. See DC Programming Characteristics for Yep, Vpp and VIO voltages.
3. Al-As. Al0-A16 = VIL

5-168

intJ

27C220

margin is ensured. The verify is performed with
CE at-.Yu.. and PGM at VIH. Valid data is available tOE·
after OE falls low.

Read Mode
The 27C220 has two control functions; both must be
enabled to obtain data at the outputs. CE is the powe(control arid device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACC> equals the
delay from CE to output (tCE). Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.

Program Inhibit
Program Inhibit Mode allows 'parallel pr29!"amming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE, parallel EPROMs may have common inputs.

Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.

inteligent Identifier™ Mode

Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power dissipation
b) complete assuranc~ that data bus contention will
not occur
To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.

Standby Mode
Standby Mode substantially reduces Vce current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.

Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.

Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
Program Mode is entered when Vpp is raised to
12.75V. Data is introduced by applying a 16-bit word
to the output pins. Pulsing PGM low while CE = VIL
and OE = VIH programs that data into the device.

Program Verify
A verify should· be performed following a program
operation to determine that bits have been correctly
programmed. With VCC at 6.25V, a substantial pro-

The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
This mode is activated when a programmer forces
12V ± 0.5V on Ag. With CE, OE, A1-Aa, and A1OA16 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.

UPGRADE PATH
Future upgrade to the 4-Mbit density is easily accomplished due to the standardized pin configuration of the 27C220. When the 27C220 is in Read
Mode, the PGM input becomes non-functional. This
allows address line A17 to be routed directly to this
input in anticipation of future density upgrades. Systems designed for 2-Mbit program memories today
can be upgraded to 4-Mbit in the future with no circuit board changes.

SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System deSigners are interested in 3 supply current issures: standby current
levels (ISB), active current levels (IcC>, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 ,...F ceramic capacitor
connected between its Vcc and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,...F electrolytic
capacitor should be placed at the array's power supply connection between Vec and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.

5-169

inter

"",

27C220

290217-9

Figure 4. Quick-Pulse Programming™ Algorithm
aged if the integrated dose exceeds 7258 Wsec/
cm 2 (1 week @ 12000 fJ-W/cm2).

ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
. Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase
an EPROM in approximately 3 years, 'while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 fJ-W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can' be permanently dam-

Quick-Pulse Programming™ Algorithm
The. Quick-Pulse programming algorithm programs
Intel's 27C220. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C220 as fast as 15 seconds. Actual programming time depends on programmer' overhead.

,
The Quick-Pulse programming algorithm employs a
100 fJ-s pulse followed by a word verification to determine when the addressed word has been successfully programmed. The algorithm terminates if
25 attempts fail to program.a word.
The entire program pulse/word verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all words are compared to the original data with Vee = Vpp = 5.0V~

5-170

27C220

DC PROGRAMMING CHARACTERISTICS
Symbol

Parameter

III

Input Load Current

Icp

Vcc Program Current

Ipp

Vpp Program Current

Notes

Min

25°C ± 5°C

Typ

Max

Unit

p.A

VIN

VIL

Input Low Voltage

-0.1

1__ ..... IB_L.. \1_1.1. _ _ _

VIH

IIIIJU\ I II!::III

2.4

VOL

Output Low Voltage (Verify)

VOH

Output High Voltage (Verify)

3.5

VIO

Ag inteligent Identifier Voltage

11.5

12.0

12.5

2,3

12.5

12.75

13.0

6.0

6.25

6.5

V·

v VILCl!::l"""

Vpp

Vpp Program Voltage

Vcp

Vcc Supply Voltage (Program)

AC PROGRAMMING CHARACTERISTICS(4)
Symbol

Parameter

Test Condition

0.8

6.5

0.45

10L

10H

= VIL or VIH
= PGM = VIL
= PGM = VIL

= 2.1 mA
= -2.5 mA

TA = 25°C ±5°C

Notes

Min

tvcs

Vcp Setup Time

p.s

tvps

Vpp Setup Time

p.s

teES

CE Setup Time

p.s

tAS

Address Setup Time

p.s

tos

Data Setup Time

p.s

tpw

PGM Program Pulse Width

tOH

Data Hold Time

toES

OE Setup Time

tOE

Data Valid from OE

tOFP

OE High to Output High Z

tAH

Typ

100

Max

105

5,6

. Address Hold Time

0
0

p.s
p.s

2
5

Unit

p's
150

130

ns
p.s

NOTES:

1. Maximum current is with outputs 00-015 unloaded.
2. Vcp must be applied simultaneously or before Vpp and removed simultaneously or aiter Vpp.
3. When programming, a 0.1 f-tF capacitor is required across Vpp and GNO to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. tOE and tOFP are device characteristics but must be accommodated by the programmer.
6. Sampled, not 100% tested.

5-171

intJ

27C220

PROGRAMMING WAVEFORMS
VERIFY

PROGRAM
V'M
ADDRESSES

)

ADDRESS STABLE

VOl
I--'AS _ _

V'H

HIGHZ

V,L
1--'05 _ _

_'AM

DATA OUT VALID

DATA IN STABLE

DATA

.'OM~

IOFP

12.75V

,---1

.Vpp

5.OV

_'vPS _ _

8.25V
Vee

/
5.0V-

l-'ve5_

V'M

Ce
VOl

\
_'CES _ _

V'H

PGM
VOl

V'H

Oil

f4-

'O'S1.

VOl

f4-

'0'

290217-10

REVISION HISTORY
O,scrlptlon
Deleted -150 PDIP, PLCC packages

5-172

27C240
4M (256K x 16) CHMOS EPROM
• JEDEC Approved EPROM Pinout
-40-Pln DIP
• Versatile EPROM Features
- CMOS and TTL Compatibility
- Two Line Control

• Fast Programming
- Quick-Pulse Programmlng™
Algorithm
- Programming Times as Fast as 30
Seconds

!! I-Ilnh_PArfnrmlllnt.!A

::'1'70 ns -i10%' vcc
- 50 mA Icc Active

Intel's 27C240 is a 5V only, 4,194,304-bit Erasable Programmable Read Only Memory, organized as 262,144
words of 16 bits each. It provides for a simple upgrade from 1 and 2 Mbits.
The 27C240 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled
performance. Its 170 ns speed (tACe) optimizes operation with high performance CPUs in applications ranging
from numerical control to office automation to telecommunications.
The 27C240 is equally at home in both a TTL or CMOS environment. And like Intel's other high density
EPROMs, the 27C240 programs quickly using Intel's industry leading Quick-Pulse Programming™ algorithm.
CHMOS Is a patented process of Intel Corporation.

DATA OUTPUTS
00-0 15

---l".
---l".

vee

0-0

GND

0-0

VPPO

l:E

OUTPUT BUFfERS

V·GATING
AO"A17
ADDRESS
INPUTS

X
DECODER

4,194,304-BIT
CELL MATRIX

290229-1

Figure 1. Block Diagram

5-173

October 1990
Order Number: 290229-004

27C240

Pin Names

Ao-A17
CE
OE
00-0 15
PGM
NC

ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
OUTPUTS
PROGRAM
NO INTERNAL CONNECT
27C240

Vpp

vee

Vee

CE
015
014
013
012
011
010
Os
Oe
GND
07
Os
05
04
03
02
01
00
OE

CE
015
014
013
012
011
010,
Os
Oe
GND
07
Os
05
04
03
02
01
00
OE

A17
A16
A15

PGM
NC
A15
A14
A13,
A12
All
Al0
As
GND
Ae
A7
As
A5
A4
A3
A2
Al
Ao

PGM
A1S
A15
A14
A13
A12
All
Al0
As
GND
Ae
A7
As
A5
A4
A3
A2
Al
Ao

0 13
A13
A12
A11
AID

°12
°10
°9
Os

GND

°7
°6
°5

As
A7
A6
A5
A4
A3
A2
AI
AD,

°3
°2
°1
00

290229-2

Figure 2. DIP Pin Configuration

5-174

27C240

ABSOLUTE MAXIMUM RATINGS*

-NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
.
change without notice.

Operating Temperature ............. O°C to 70°C(1)
Temperature Under Bias ........... -10°C to BO°C
Storage Temperature ............. - 65°C to 125°C
Voltage on Any Pin
(except Ag, Vee and Vpp)
with Respect to GND .......... - 0.6V to 6.5V(2)
Voltaae on Aa with
Respectto-GND ............. -0.6Vto 13.0V(2)

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation' beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Vpp Supply Voltage
with Respect to GND ........... -0.6V to 14V(2)
Vee Supply Voltage
with Respect to GND .......... -0.6V to 7.0V(2)

READ OPERATION DC CHARACTERISTICS
Symbol

Parameter

III

Input Load Current

ILO

Output Leakage Current

IS8

Vee Standby Current'

lee

Vee Operating Current

Notes

Min

Vee = 5.0V ±10%

Typ
0.01

Max

Units

Test Condition

J-LA

VIN

J-LA

VOUT

1.0

100

J-LA

f
Ipp

Vpp Operating Current

los

Output Short Circuit Current

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Vpp

Vpp Operating Voltage

J-LA

4,6

100

O.B

Vee

+ 0.5

0.45
2.4
5

Vee - 0.7

1.0
±10

Vpp

=
=
=

OV to Vee

VIH
Vee ±0.2V

VIL
5 MHz, lOUT

0 mA

Vee

V
V
V

Vee

OV to Vee

= 2.1 mA
10H = - 400 J-LA

10L

NOTES:
1. Operating temperature. is for commercial product defined by this specification.
2. Minimum De voltage is -O.SV on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vcc + O.SV which, during transitions, may overshoot to Vcc + 2.0V
for periods <20 ns.
.
3, Maximum active power usage is the sum Ipp + ICC. Maximum current is with outputs 00 to 015 unloaded.
4. Output shorted for no more than one second. No more than one output shorted at a time.
S. Vpp may be connected directly to Vcc, or may be one diode voltage drop below Vee. Vee must be applied simultaneously
.
or before Vpp and removed simultaneously or after Vpp.
6. Sampled, not 100% tested.
7, Typical limits are at Vee = SV, TA = 2Soe.

5-175

•

27C240

READ OPERATION AC CHARACTERISTICS(1) vcc

Verslons(4)
Symbol

Vee ± 10%

Parameter
Address to Output Delay

tCE

CE to Output Delay
DE to Output Delay

tOF

OE High to Output High Z

toH

Output Hold from Addresses,
CE or DE Change-Whichever
is First

. toE'

5.0V ±10%
27C24Q-200V10

Min

Units

Notes

tACC

27C24Q-170V10
Max

Max

170

200

170

200

55
0

NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. DE may be delayed up to tCE-toE after the falling edge of CE without impact on teE.
3. Sampled, not 1000;. tested.
4. Model number prefixes: No Prefix = Ceramic Dip.
5. Typical limits are for TA = 25°C and nominal supply voltages.

CAPACITANCE(3)

f = 1 MHz

25°C,

Typ(5)

Max

Unit

CIN

Input Capacitance

COUT

Output Capacitance

Cvpp

Vpp Capacitance

Symbol

Parameter

AC INPUT/OUTPUT REFERENCE WAVEFORM

Conditions

= OV
= OV
Vpp = OV
VIN

VOUT

AC TESTING LOAD CIRCUIT
1.3V

2.4
0.45

2.0>
0.8

___
TEST POINTS ----...

!IN914

2.0
OUTPUT

,,0_..8......._ _

290229-3

DEVICE
UNDER
TEST

AC test inputs are driven at VOH (2.4 VTTU for a logic "1" and
VOL (0.45 VTTU for a logic "0". Input timing begins at VIH
(2.0 VTTU and VIL (0.8 VTTd. Output timing ends at VIH and VIL.
Input rise and fall times (10% to 90%) ,;10 ns.

OUT

,
CL = l00pF
CL Includes Jig Capacitance
RL = 3.3 Kfl

5-176

CL
290229-4

intJ

27C240

AC WAVEFORMS
V'H----_
ADDRESS

ADDRESSES
V,, _ _ _ __

V'H -

VALID

_ _ _ _-+-....

1--

V'H _ _ _ _ _-+____

to.

V'M
OUTPUTS _ _ _ _--'H;;;;IG;;;,;H~Z_ _ _ __+H~r_<

HIOHZ

v"
290229-5

DEVICE OPERATION
The Mode Selection table lists 27C240 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, and A9 during inteligent IdentifierTM Mode, are TTL or CMOS.

Table 1. Mode Selection
Mode

Notes

Vpp

Vee

Outputs

VIL

Vee

DOUT

Output Disable

VIL

VIH

Vee

HighZ

Standby

VIH

Vee

HighZ

Read

Program
Program Verify
Program Inhibit
inteligent
Identifier

I
I

Manufacturer
Device

2,3

VIL

VIH

Vpp

Vep

DIN

VIH

VIL

Vpp

Vep

DOUT

VIH

Vpp

Vep

HighZ

VIL

VID

VIL

Vee

0089H

VIL

VID

VIH

Vee

44EEH

NOTES:
1. X can be VIL or VIH
2. See DC Programming Characteristics for VcP. Vpp and VIO voltages.
3. A1-AS. AlO-A17. = VIL

5-177

intJ

27C240

programmed. With Vcc at 6.2SV, a substantial program margin is ensured. The verify is performed with
CE at VIH. Valid data is available tOE after OE falls
~Iow.
.

Read Mode
The 27C240 has two control functions; both must be
enabled to obtain data at the outputs. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (tCE)' Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.

Program Inhibit
Program Inhibit Mode allows parallel pr~amming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE and OE, parallel EPROMs may have common
inputs.

Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.

inteligent Identifier™ Mode

Two Line Output Control

The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with it's proper programming algorithm.

EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur

This mode is activated when a programmer forces
12V ± O.SV on Ag. With CE, OE, A1-AB, and A1OA17 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 2SoC ± SoC ambient temperature
range required during programming.

SYSTEM CONSIDERATIONS

Standby Mode
Standby Mode substantially reduces Vcc current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.

Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.

EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (Iss), active current levels (ICe), and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 fLF ceramic capacitor
connected between its Vce and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 p,F electrolytic
capacitor should be placed at the array's power supply connection between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.

ERASURE CHARACTERISTICS
Program Mode is entered when Vpp is raised to
12.7SV. Data is introduced by applying a 16-bit word
to the output pins. Pulsing CE low while OE = VIH
programs that data into the device.

Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly

S-178

27C240

290229-6

Figure 3. Quick-Pulse Programming Algorithm
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light cif wavelength 2537A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 p.W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsec/
cm 2 (1 week @ 12000 p.W/cm2).

Quick-Pulse Programming Algorithm
The" Quick-Pulse Programming algorithm programs
Intel's 27C240. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C240 as fast as 30 seconds. Actual programming time depends on programmer overhead.
The Quick-Pulse Programming algorithm employs a
100 p.s pulse followed by a word verification to determine when the addressed word has been successfully programmed. The algorithm terminates if
25 attempts fail to program a word.
The entire program pulse/word verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all words are compared to the original data with Vee = Vpp = 5.0V.

5-179

27C240

DC PROGRAMMING CHARACTERISTICS
Symbol

Parameter

III

Input Load Current

Icp

Vcc Program Current

Ipp

Vpp Program Current

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage (Verify)

VOH

Output High Voltage (Verify)

VIO

Ag inteligent Identifier Voltage

Vpp

Vpp Program Voltage

Vcc

Vcc Supply Voltage (Program)

TA = 25°C ±5°C

Notes

Min

Parameter

Max

Unit.

Test Condition

/LA

VIN

-0.1

0.8

2.4

6.5

0.45

10L

10H

3.5
11.5

12.0

12.5

2,3

12.5

12.75

13.0

6.0

6.25

6.5

AC PROGRAMMING CHARACTERISTICS(4)
Symbol

Typ

= VIL or VIH
= VIL
CE = VIL

= 2.1 mA
= -2.5mA

TA =. 25°C ±5°C

Notes

Min

Typ

Max

Unit

tvcs

VCP Setup Time

p.s

tvps

Vpp Setup Time

p.s

tAS

Address Setup Time

tos

Data Setup Time

tpw

CE Program Pulse Wi9th

tOH

Data Hold Time

p.s

tOES

OE Setup Time

p.s

toE

Data Valid from OE

tOFP

OE High to Output High Z

tAH

Address Hold Time

5
5,6

0
0

p.s
100

105

p.s

150

130

ns
p.s

NOTES:
1. Maximum current is with outputs 00-015 unloaded.
2. Vep must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 /LF capacitor is required across Vpp and GNO to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. tOE and tDFP are device characteristics, but must be accommodated by the programmer.
6. Sampled, not 100% tested.

5-180

inter

. 27C240

PROGRAMMING WAVEFORMS
VERIFY

PROGRAM

v,.
ADDRESSES

,
DATA

ADDRESS STABLE

~'AS~
~

J
f.--'DS __

I--'A.

HIOiHZ
DATA OUT VALID

DATA IN STABLE

---

f.'D••

tOFF>

12.7SV

,---.I I--'VP5___

v••

5.0V
8.25V

Vee

,---.I f---',es_

S.OV

V,.

~'DES~

V, L

I+-

'e.

290229-7

REVISION HISTORY
Number
04

DescrIptIon
Deleted -150 speed bin

5-181

27C400
4M (256K x 16 or 512K x 8) CHMOS EPROM
or Byte-Wide Configurable
• Word-Wide
4M 40-Pin Mask ROM Compatible
• - 40-Pin CERDIP Package
Dissipation
• -Low50Power
mA Max Active
5 MHz

• -High150Performance
ns Maximum Access Time
-Vcc

5V ±10%

•
• UV Erasable

Quick-Pulse Programming™ Algorithm
- Programming as Fast as 28 Seconds

-100 /-LA Max Standby

Intel's 27C400 is a 5V-only, 4,194,304 bit, Erasable Programmable Read Only Memory. It employs advanced
CHMOS' III-E circuitry for systems requiring low power, high speed performance and noise immunity.
The device is organized as 262,144 words of 16 bits or 524,288 bytes of 8 bits through use of a byte enable
switch on pin 31. The 27C400 is pinout and functionally compatible with 40-pin 4M Mask ROMs, providing a
solution for both prototyping and production applications.
The 27C400 is offered in a ceramic DIP package. The UV-erasable CERDIP package facilitates fast time-tomarket in minimum quantities with migration to mask ROMs for volume production. The Quick-Pulse Programming algorithm provides fast, reliable programming.
'CHMOS is a patented process of Intel Corporation.

DATA OUTPUTS
0 0 -0 15

VccOO---+~

Vpp

Oo---+~

GNDO""'·--+~

A-1

DE
CE
BYTE

OUTPUT ENABLE
CHIP ENABLE
.
AND

OUTPUT
BUFFERS

PROGRAM LOGIC

Y GATING

Y DECODER

AO-A 17
ADDRESS
INPUTS

4,194.304 BIT
X DECODER

CELL MATRIX

290273-1

Figure 1. 27C400 Block Diagram

5-182

November 1990
Order Number: 290273-002

inter

27C400

Pin Names

8Mb

Ao-A18

ADDRESSES

00-0 15

OUTPUTS

OUTPUT ENABLE

CHIP ENABLE

BYTE

WORD/BYTE ENABLE

A.-1

BYTE SELECT

NO CONNECT

4Mb

Mask ROM

27C400

8Mb
NC

A18
A17
A7
A6
A5
A4
A3
A2
A1
Ao
CE
GND
OE

~
A3
A2
A1
Ao
CE
GND
OE

00
Os
01.
Og

00
Os
01
Og

°7
°0 6

02
010
03
011

A17
A7
A6
A5

A8
Ag

AlO
A11
A12
A13
A14
A15
A16
BYTE
GND

015 /A-1
07
014
06
013
05
012
0-'1

A10
A11
A12
A13
A14
A15
A16
BYTElVpp
GND
015 /A -1
07
014
06
013
05
012
04

Vee

Ag
A 10

All
A12
A 13

AI.
A1S
A 16

8YTE/Vpp

GNO
°lS/A-l'

1•

0 13

0 12

290273-2

Figure 2. DIP Pin Configuration

5-183

inter

27C400

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.

Operating Temperature ............. O·C to 70'C(1)
Temperature under Bias ........... -1 O'C to 80'C

Storage Temperature ............. - B5'C to 125'C
Voltage on Any Pin
(Except Ag, Vcc and BYTElVpp)
with Respect to GND ....•..... - O.BV to B.5V(2)
Voltage on Ag, with
Respectto GND •.......•...... -O.BV.to 13V(2)
BYTElVpp Program Voltage
with Respect to GND ........... - O.BV to 14V(2)
Vcc Supply Voltage
with Respect to GND ............ - O.BV to 7V(2)

READ OPERATION DC CHARACTERISTICS(1)Vcc =
Symbol

Parameter

III

Input Load Current

ILO

output Leakage Current

ISB

Vcc Standby Current

Icc

Vce Operating Current

Notes

Min

Typ
0.01

Ipp

Vpp Operating Current

loS

Output Short Circuit
Current

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

5.0V ±10%

Max

Unit

1.0

/LA

VIN

. ±10

/LA

VOUT

OVto Vcc

=
=

OVto Vcc

1.0

100

/LA

f = 5 MHz,
CE = VIL, lOUT

/LA

4,B

100

0.8

Vec

+ 0.5

0.45
2.4

Test Condition

Vpp

VIH
Vce ± 0.2V

0 mA

Vcc

V
V
V

= 2.1 mA
10H = -400/LA
10L

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum DC voltage on input/output pins is Vce'+ 0.5V which, during transitions, may overshoot to Vce + 2.0V
for periods < 20 ns.
3. Maximum active power usage is the sum Ipp + Icc. Maximum current value is with outputs 00-015 unloaded.
4. outPt shorted for no more than one second. No more than one output shorted at a time.
5. BYT /Vpp = Vee ± 0.2V or GND ± 0.2V.
6. Sampled, not 100% tested.
7. Typical limits are at Vec = 5V, TA = 25'C.

5-184

inter

27C400

READ OPERATION AC CHARACTERISTICS(I)vcc

vee ±

Version(4)
Symbol

Parameter

Notes

Address to Output Delay

tCE

CE to Output Delay

Min

Unit

Max
ns

150

200

!"'!S

tOE

('"\t::

U;,..h +,... (",\, .+"' ,+ Ui"h 7
, "~II " ..... _
... ,t"' ........ ~ •• -

tOH

Output Hold from Addresses,
CE or OE ChangeWhichever Occurs First

....

Max

200

'--

Min

27C400-200V10

150

OE to Output Delay

'ut"

±10%

27C400-150V10(7)

10%

tACC

= 5.0V

NOTES:

I. See AC Inpul/Output Reference Waveform for timing measurements.
2. OE may be delayed up to teE-toE after the falling edge of CE without impact on tCE'
3. Sampled, not 100% tested.
4. Model Number Prefixes: No Prefix = CERDIP.
5. Typical values are for TA = + 25°C and nominal supply voltages.
6. Includes Ols/A-l.
7. Both byte- and word-wide-read mode are available with the 27C400-200Vl0. 27C400-150VIO specs are valid only in
word-wide-read mode operation.

CAPACITANCE(3lTA =
Symbol

25°C, f

Parameter

= 1 MHz

Typ(5) Max Unit

Condition

CIN

Input Capacitance

VIN

COUT

Output Capacitance(6)

VOUT

Cvpp

VPP Capacitance

VPP

AC INPUT/OUTPUT REFERENCE WAVEFORM

2.4",,-IN_P_UT_ ) (
J
0.45·

~:~

TE!T POINTS
;

2.0

0.8

=
=

AC TESTING LOAD CIRCUIT

1.3V

OUTPUT

IN914

290273-5
AC test inputs are driven at VOH (2.4 VTTU for a Logic "I" and
VOL (0.45 VTTU for a Logic "0". Input timing begins at VIH (2.0
VTTU and VIL (0.8 VTTU. Output timing ends at VIH and VIL: Input
rise and fall times (10% to 90%) ,;; 10 ns.

t--+--oOUT

290273-6
CL ~ 100pF
CL Includes Jig Capacitance
RL ~ 3.3 kO

5-185

27C400

AC WAVEFORMS
Word-Wide Read Mode
AO- 17

V,H -

........ .,..------~,.----

V,L ...,...-J'.,....-~~~~-of'"----

V,H
0 0- 15

V·----=----C
IL

290273-7

NOTE:
BYTEIVpp = Vee

± O.2V

Byte-Wide Read Mode
A-l-A 17

V,H - - - .•

.Jo-------....,----

V,L --J'.,....-~~~~-of'"----

290273-8

NOTE:
BYTEIVpp

= GND ± O.2V

5-186

27C400

DEVICE OPERATION
The Mode Selection table lists 27C400 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vcc and BYTElVpp, and Ag during inteligent IdentifierTM Mode, are TIL or CMOS.
Table 1. Mode Selection
Mode
Read (Word)

BYTEI
Vpp(4)

Notes

015 /A - 1

VIL

D15 Out

Vee

VIL

VIH

GND

Vcc

HighZ

DS-15 Out

Read (Upper Byte)

Vee

08-14

00-7

D8-14 Out . DO-7 Out

Read (Lower Byte)

VIl.~

VIL

GND

Vcc

HighZ

DO-7 Out

Output Disable

VIL

VIH

HighZ

Vcc

HighZ

VIH

HighZ

Vcc

HighZ

VIL

VIH

D15 1n

Vpp

Vcp

DS-14In

D15 Out

Vpp

Vcp

DS-14 Out

DO-7 Out

HighZ

Vpp

Vcp

HighZ

Vcc

OOH

89H

Vcc

44H

EFH

Standby
Program

Program Verify

VIH

VIL

Program Inhibit

VIH

inteligent Identifier
-Manufacturer
-Device

2,3

VIL

VID

VIL

VID

VIH

DO-7 In ·

NOTES:

1. X can be VIL or VIH.
2. See DC Programming Characteristics for VcP. Vpp and VIO voltages.
3. A,-A6. A,o-A17 = VIL.
4. BYTElVpp is intended for operation under DC Voltage conditions only.

Read Mode

Two Line Output Control

The 27C400 has two control functions; both must be
enabled to obtain data at the outputs. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACC> equals the
delay from CE to output (tCE)' Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.

EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:

Word-Wide Mode
With BYTElVpp at VCC ± 0.2V outputs 00-7 present data.QQ_7 an~utputs 0S-15 present data Ds15, after CE and OE are appropriately enabled.

a. lowest possible memory power dissipation
b. complete assurance that data bus contention will
not occur
To efficiently use these two control inputs, an address decoder should enable CE while OE should be
connected to all memory devices and the system's
READ control line. This assures that only selected
memory devices have active outputs while deselected memory devices are in Standby Mode.

Byte-Wide Mode
With BYTElVpp at GND ± 0.2V. outputs OS-15 are
tri-stated. If 015/A-1 = VIH, outputs 00-7 present
data bits DS-15. If 015/A-1 = VIL, outputs 00-7
present data bits DO-7.

Standby Mode
Standby Mode substantially reduces Vcc current.
When CE = VIH, outputs are in a high impedance
state, independent of OE.

Read Operation AC Characteristic specifications are
currently valid in byte-wide mode only when using
the 27C400-200V1 O. Please contact your local Intel
sales office for additional information.
5-187

intJ

27C400

tion of the 27C400. Simply design in the 27C400
using pins 2-41 of a 42-pin socket. Route address
line A18 directly to pin 1 in anticipation of future den~
sity upgrades. See Figure 2 for additional information. Systems designed for 4M-bit program memories today can be upgraded to 8M-bit in the future
with no circuit board changes.

Program Mode
Caution: Exceeding 14V on BYTE/Vpp .will
permanently damage the device.

Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although .only "Os" are programmed the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".

SYSTEM CONSIDERATIONS

Program Mode is entered when BYTElVpp is raised
to 12.75V. Data is introduced by applying a 16-bit
word to the .output pins. Pulsing CE low while OE =
VIH programs that data into the device.

Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
programmed. With Vee at 6.25V, a substantial pro9@m margin is ensured. The verify is performed with
CE at VIH. Valid data is available on 00-15 tOE after
OE falls low.

Program Inhibit
Program Inhibit mode allows parallel programming
of multiple EPROMs with different data. CE-high inhibi~rogran\ming of non-targeted devices. Except
for CE and OE, parallel EPROMs may have common
.
inputs.

inteligent IdentifierTM Mode
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
This mode is activated when a programmer forces
12V ±0.5V on Ag. With CE, OE, A1-A8, and A10A17 = VIL, Ao = VIL will present the manufacturer's
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.

UPGRADE PATH
Future upgrade to the 8M-bit density is easily accomplished due to the standardized pin configura-

EPROM power switching characteristics require
careful device decoupling. System designers are interested in three supply current issues-standby
currents levels (Iss), active current levels (IcC>, and
transient current peaks produced by falling and rising edges of CEo Transient current magnitudes depend on the device outputs' capacitive and inductive
loading. Two-Line Control and proper decoupling capacitor selection will suppress transient voltage
peaks. Each device should have a 0.1 /kF ceramic
capacitor connected between its Vee and GND. This
high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device.
Additionally, for every eight devices, a 4.7 /kF electrolytic capacitor should be placed at the array's
power supply connection between Vee and GND.
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductances.

ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase an
EPROM in approximately 3 ·years, while it takes approximately 1 week when exposed to direct sunlight.
It the device is exposed to these lighting conditions
for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelengths 2537A. The intergrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 /kW/cm 2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsecl
cm 2 (1 week @ 12000 p,W/cm2).

5-188

inter

27C400

INCREMENT ADDRESS

290273-9

Figure 3. Quick-Pulse Programming Algorithm

Quick-Pulse Programming Algorithm
The Quick-Pulse Programming™ algorithm programs Intel's 27C400. Developed to substantially reduce programming throughput, this algorithm can
program the 27C400 as fast as 28 seconds. Actual
programming time depends on programmer overhead.

determine ,when the addressed word has been successfully programmed. The algorithm terminates if
25 attempts fail to program a word.
The entire program-pulse/word-verify sequence is
performed with BYTElVpp = 12.75V and Vee =
6.25V. When programming is complete, all words
are compared to the original data with Vee =
BYTElVpp = 5.0V.

The Quick-Pulse Programming algorithm employs a
100 }ks pulse followed by a word verification to

5-189

27C400

DC PROGRAMMING CHARACTERISTICS
Symbol

Parameter

III

Input Load Current

Icp

Vcp Program Current

Ipp

Vpp Program Current

T A = 25°C ± 5°C

' Min

Notes

Typ

Max

Unit

Test Conditions

p..A

rnA

= VIL or VIH
= VIL
CE = VIL

VIL

Input Low Voltage

-0.1

0.8

VIH

Input High Voltage

2.4

6.5

VOL

Output Low Voltage (Verify)

VOH

Output High Voltage (Verify)

VID

Ag inteligent Identifer Voltage

Vpp

Vpp Program Voltage

Vcp

Vcc Supply Voltage (Program)

0.45
3.5

Symbol

Parameter

IOL

IOH

11.5

12.0

12.5

2,3

12.5

12.75

13.0

6.0

6.25

6.5

AC PROGRAMMING CHARACTERISTICS(4) TA =

VIN

= 2.1 rnA
= -2.5 rnA

25°C ± 5°C

Notes

Min

Typ

Max

Unit

tvcs

Vcp Setup Time

p..s

tvps

Vpp ,~etup Time

p..s

tAS

Address Setup Time

p..s

los

Data Setup Time

p..s

tpw

CE Program Pulse Width

tOH

Data Hold Time

tOES

OE Setup Time

tOE

Data Valid from OE

tDFP

OE High to Output High Z

tAH

Address Hold Time

100

105

p..s

2
5
5,6

p..s
150

0
0

p..s

130

ns
ns
p..s

NOTES:
1. Maximum current is with outputs 00-015,unloaded.
2. Vep must be' applied simultl;lneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 ",F capacitor is required between Vpp and GNO to suppress spurious voltage transients, which
can damage the device.
.
4. See AC .input/Output Reference Waveform for timing measurements.
5. tOE and tDFP are device characteristics 'but must be accommodated by the programmer.
6. Sampled, not 100% tested.

5-190

27C400

PROGRAMMING WAVEFORMS

ADDRESSES

Y1H
Y 1L
Y 1H

°0-15

BYTE/Y pp

Y1L
Y 1H
Y1L

Y ee

Y1H
Y 1L
Y1H
Y 1L

liE

Y 1H
Y1L

290273-10

5-191

27960CX
PIPELINED BURST ACCESS 1M (128K x 8) CHMOS· EPROM
4 Byte Data Burst Access
Pipellned Addressing for Optimal Bus
• Synchronous
•
Bandwidth on' 80960CA
No Glue Interface to 80960CA
• High
- Next Addressing Overlaps Last Data
Clock to Data Out
Byte
• - ZeroPerformance
Wait State Data to Data Burst
CHMOS
III-E for High Performance and
- Up to 33 MHz 80960CA Performance
• Low Power
Microcontroller Reset Function
-125 mA Active, 30 mA Standby
• -Asynch
Returns to Known State with Hlgh-Z
- TTL Compatible Inputs
Outputs
1 Mbit Density Configures as 128K x 8
• -Upgrade
Path to 512K x 8
Intel's 27960CX is a 5V only, 1,048,576 bit, Erasable Programmable Read Only Memory, organized as 128K
words of 8 bits. It is a member of a new family of high performance EPROMs with synchronous burst access.
The 27960CX provides a no glue synchronous burst interface to the 80960CA bus. Internally the 27960CX is
organized in 4 byte blocks, in which each byte is accessed sequentially. The internal state machine is factory
configured to generate either 1 or 2 wait-states between the address and first data byte. High performance
outputs provide zero wait-state data to data accesses at clock frequencies up to 33 MHz.
Pipelining capability allows addresses to overlap previous data, further optimizing bus bandwidth in 80960CA
applications. An asynchronous microcontroller RESET feature puts the outputs in the high impedance state
and takes the internal state machine to a known state where a new burst access can begin.
The 27960CX is available in' either 44-lead Cerquad (reprogram mabie) or PLCC packages. Cerquad allows for
code changes in the R&D environment while PLCC provides optimum cost effectiveness during production.
Two No Connects (NC) on the package allow for an upgrade to 4 Mbits (512K x 8).
The 27960CX is manufactured on Intel's 1 micron CHMOS III-E technology. The Quick-Pulse Programming™
algorithm provides fast, reliable programming with throughput uflder 17 seconds for optimized equipment.
'CHMOS is a Palenlenled Process of Inlel Corporation.

A l
D

D T

R C
E H
S

T A
A C

T H
ClK

I
N
E

290236-1

Figure 1. 27960CX Burst EPROM Block Diagram

5-192

January 1991
Order Number: 290236-004

inter

27960CX

27960CX BURST EPROM

Architecture

EPROMs are established as the preferred code storage device in embedded applications. The non-volatile, flexible, reliable, cost effective EPROM makes a
product easier to design, manufacture and service.
Until recently, however, EPROMs could not match
the performance needs of high-end systems. The
27960CX was designed to support the B0960CA embedded processor. It utilizes the burst interface to
otter near zero walt-state performance without the
high cost normally associated with this performance.

The 27960CX provides a no-glue, synchronous burst
interface to the B0960CA's bus. It operates in pipelined or non-pipelined modes. Internally, the
27960CX is organized in 4 byte blocks which are
accessed sequentially. A burst access begins on the
first clock pulse after ADS and CS are asserted. The
address of the 4 byte block is latched on the rising
edge of clock following ADS. After a preset number
OT wait-states (i or 2i, data is ouipui one oyie ai a
time on each subsequent clock cycle. A burst access is terminated on the rising edge of clock with
BLAST asserted. High performance outputs provide
zero wait-state data to data accesses at clock frequencies up to 33 MHz. Extra power and ground
pins dedicated to the outputs reduce the effects of
fast output switching on device performance.

In embedded designs, board space and cost must
be kept at a minimum without impacting performance and reliability. The 27960CX removes the need
for expensive high-speed shadow RAM backed up
by slow EPROM or ROM for non-volatile code storage. Code optimization concerns are reduced with
"off-chip" code fetches no longer crippling to system performance. FONTs can be run directly out of
these EPROMs at the same performance as highspeed DRAMs. With the 27960CX, the EPROM is
the ideal code or FONT storage device for your
B0960CA system.

The pipelining capability of the 27960CX allows the
address to overlap the last data byte of the burst,
further optimizing bus band width in 80960CA applications. In the pipelined mode, with a non-buffered
interface, the 27960CX delivers 4 bytes of data, in
6 clock cycles at 33 MHz. In a 32-bit configuration,
this translates into a read bandwidth of 88 Mbytes/
sec. Performance capability of the 27960CX in different 80960CA systems is given in Table I.

'CERQUAD is available in a socket only version.

ADDRESS

17
A

DATA

27960CX

8
ADS
BLAST

BURST
EPROt.!

128K

RESET

ClK
PGt.!
290236-2

Figure 2. 27960CX Burst EPROM Signal Set

5-193

intJ

~OO[gIl.O~OOOIA\OOW

27960CX

Table 1. Performance Capability

33 MHz 2WS
AOOR
OATA
PCLK

Aoo
Cl

WS
C2

25 MHz
AOOR
OATA
PCLK

Aoo

AOOR
OATA
. PCLK

Aoo

WS
C2

000
C3

16MHz
AOOR
DATA
PCLK

Aoo
Cl

000
C4
2WS

001
Cs

000
C4
1 WS

001
C4
1 WS

000
C3

001·
C4

Aol
003
C7

WS
Cl

WS
010
C3

A02
013
Cs

012
Cs

A02
013
Cs

. D12·
Cs

011
C4

Buffered: 4 Words/6 Clock Cycles ---+ 66 Mbytes/Sec

001
Cs

002
Cs

AOl
003
C7

WS
Cl

WS
D11
C4

010
C3

Buffered: 4 Words/5 Clock Cycles ---+ 64 Mbytes/Sec

002
Cs

AOl
003
Cs

WS
Cl

010
C2

011
C3

·A02

013
Cs

012
C4

Buffered: 4 W~rds/5 Clock Cycles ---+ 51 Mbytes/Sec.

WS
C2

002
Cs

20 MHz

Non-Buffered: 4 Words/6 Clock Cycles ---+ 88 Mbytes/Sec

002
Cs

AOl
003
(:s

WS
Cl

010
C2

011
C3

012
C4

A02
013
Cs

WS
Cl

A 16
A 15
A14

CJ27960CX

A 13

44 LEAD CERQUAD

A12

N27960CX

Al1

44 LEAD PLCC

A 10
Ag

0.650" x 0.650"
TOP VIEW

As
A7
A6

290236-3.

Figure 3. 27960CX 44 Lead PLCC/CERQU~D Pinout

5-194

inter

27960CX

PIN DESCRIPTIONS
Symbol

·Ao-A16

23-39

00- 0 7

6,7,10,
11, 13, 14,
17,18

ADS

Function
ADDRESS INPUTS: During a burst operation, A2-A16 provides the
base address pointing to a block of four consective bytes. Ao and A1
select the first byte of the burst access. The 27960CX latches
addressf;ls in the first clock cycle. An internal address generator
increments addresses Ao and A1 for subsequent bytes of the burst.
DATAINPUTS/OUTPUTS

ADDRESS STROBE: Indicates the start of a new bus access. ADS is
active low in the first clock cycle of a bus access.

CHIP SELECT: Master device enable. When asserted (active low)
data can be written to and read from the device. In read mode, CS
enables the state machine and the 1/0 circuitry.
NOTE:
1. The address decode path is independent of CS, i.e., X and Y
decoding is always powered up.
2. For programming, CS should remain low for the entire cycle.
Program and verify functions are done one byte at a time.
3. CS going high does not terminate a concurrent burst cycle.

BLAST

BURST LAST: Terminates a concurrent burst data cycle at the riSing
edge of the ClK. It must be asserted by the fourth data byte.

RESET

ASYNCHRONOUS RESET INPUT: Resets the state machine into a
known state, tri-states the outputs and puts address latches into the
flow through mode. RESET must be asserted for a minimum of 10
clock cycles. At least 5 clock cycles are required after deassertion of
RESET before beginning the next cycle. RESET will abort a concurrent
bus cycle.

PGM

PROGRAM-PULSE CONTROL INPUT

Vpp
Vss

Vee

5,8,12,
15,19,21
9,16,20,44

PROGRAMMING POWER SUPPLY
GROUND
SUPPLY VOLTAGE INPUT

5-195

•

27960CX

on the address lines (due to the EPROM only) is
24 pF for a 128K x 32 system and 48 pF for a 256K x
32 system. The EPROM is specified at 6 pF for input
capacitance (15 pF max) and 12 pF typical for output capacitance. Larger systems Can be implemented with buffers (Figure 48).

INTERFACE EXAMPLE
Overview

This example illustrates 8-, 16- and 32-bit wide
27960CX interfaces to the 80960CA. The designs
offer a simple "no-glue" interface.

. Chip Select Logic

A non-buffered 27960CX system organized as 256K
x 32 is shown in Figure 4A. Since the 27960CX is
capable of driving a 80 pF load, large, non-buffered
systems can be implemented by stacking up to 2
banks of 4 EPROMs, resulting in a 256K x 32 memory subsystem. The input capacitive load seen

High order address lines are decoded .to provide CS.
Qualification with other signals is not required. The
chip select logic can be implemented with standard
asynchronous decoders, PAL's or PLO's(like Intel's
85C508).

27960CX

128K
x
8

B0960CA

290236-4

Figure 4A. 256K x 32 Non-Buffered Burst EPROM Memory System

DEC

CS N
CS 2
CS,

cs
~~--

"
ADDRESS

j-1I

'---

B0960CA

DATA

r--A

XCVR

~~s_......

-""'-

ADDRESS

1CS cs

CS
27960CX

128K
x
8

1-.

CS
~~-~

CS
CS
27960CX

128K
x
8

'--290236-5

Figure 4B. Buffered Burst EPROM Memory System

5-196

inter

27960CX

In a non:buffered, 16-bit system (Figure 6A) BE1
and A2 connect to the lower order address bits of
the 27960CX. BE1 connects to Ao of both EPROMs,
while A2 connects to both A1 'so

Schematics

Figure 5 shows a non-buffered, 128K x 32 27960CX
EPROM system.
Chip select logic, the only external logic that is required for this interface, can be derived from the
global system chip select circuitry.

DECODER
(S5C5,OS)

ADDRESS

In a non-buffered, 8-bit system (Figure 6B) BEO and
BE1 connect to Ao and A1 respectively.

t---.-------.-------..--------.

A2-A'8

ADS
ADS

PClK
BLAST
S0960CA

Ao-A 16

Ao-A'6
17

27960CX
12SKxS

Ao-A'6

27960ex
ADS

27960ex
12SKxS

ClK

elK

ClK

BLAST

DATA

32
290236-6

Figure 5. 128K x 32 27960CX Burst EPROM System

A3-A 17
II.
/
15 V'

ADDRESS

ADS

A2
BEl

--'\
~

27960CX
128K x 8

ClK

BLAST

A2-A '6
ADS

PClK
80960CA

DECODER
(8SCS08)

CS
A2-A '6
ADS

27960ex
128K x 8

ClK

BLAST

Al
Ao

~O-D7

DATA

~S-DI5/

290236-7

Figure 6A. 27960CX Burst EPROM In a 16-Bit System

5-197

inter

21960CX

r-'

DECODER
(85C508)

ADDRESS

A2-:A,6

''S

ADS

PClK

27960CX
128K x 8

ClK

BLAST
80960CA

CS
A2-A'6

BLAST

BEl
A,

BEO

06- 0 7

DATA,

/
J

290236-8

Figure 6B. 27960CX Burst EPROM in a a-Bit System
required. With the 80960CA's maximum valid address delay of 18 ns at 33 MHz, 7 ns remains for CS
decoding logic.
'

Waveforms
Figure 7 shows the timing waveforms of a 27960CX
pipelined read in a 32-bit system.

, Bootup
CS Setup Time
CS setup time is the time between CS being asserted and the first ClK rising edge (during the address
cycle). Since a memory access begins on the first
ClK risin~dge after ADS and CS are asserted, a
minimum CS setup time of 5 ns (tSVCH) at 33 MHz is

The Wait state configuration (1 or 2), of the 27960CX
is programmed by the user into the 80960CA Region
Table parameters of NRAD, NRDD, and NXDA.
NRDD is always 0 for the 27960CX.

5-198

inter

27960CX

elK

DATA

t---t--+---{

290236-9

NOTES:

1. The EPROM can also operate in non pipelined mode i.e, next address and ADS can be asserted in the clock cycle
following the last data word of the burst.
2. 2 - 0 - 0 - 0 Burst Read -+ 2 indicates the number of wait states to access the first word
O's indicate the number of wait states for subsequent data words:
o in this case!
3. 27960CX latches addresses on the falling edge of clock cycle 1 after sampling CS and ADS it has an internal address
generator which increments addresses for subsequent words of the burst. It ignores the states of A2, A3 and BEO-BE3
during a burst.

Figure 7. Two Cycles of a 27960CX 2 Wait State 4 Byte Read (2-0-0-0 Burst Read) in a 32 Bit System
During boot-up (Figure 8), the 80960CA picks up it's
Region Table data from addresses FFFF FFOO;
FFFF FF04; FFFF FF08 and FFFF FFOC. Only the
least significant byte of each of the above four 32-bit
accesses is used to configure the Region Table. For
boot-up, the wait-state parameters NRAD and NXDA
default to 31 and 3 respectively. During boot-up, the
27960CX will wrap around the first word of the fourword burst and hold the first word until BLAST is
asserted.

27960CX DEVICE NAMES
The device names on the 27960CX were derived as
mnemonics that correspond to the number of wait
states and expected operating frequency for the device. For example, the 25 MHz, 2 wait state
27960CX is named 27960C2-25.

AC TIMING DERIVATIONS

always assumed. The example below shows how
the 27960C2-33 tavcoh timing was derived.
@33 MHz the clock cycle is

30 ns.

tOV2 of the 80960CA is 3 ns - 16 ns.
Typical 2 ns guardband.
27960C2-33 tavcoh = 30 ns - 16 ns - 2 ns
=

12 ns

On timings where the EPROM is faster than the microprocessor, we specified the time required by the
EPROM and left the excess time as additional system guardband:
Decoders are needed for the systems chip select
decoding. For the 27960CX timings we assumed a
10 ns chip select decoder for 20 MHz and 16 MHz
and a 7 ns decoder for 25 MHz and 33 MHz
systems. The example below shows how the
27960C2-33 tsvch timing was derived.

The AC timings for the 27960CX were generated
specifically to meet the requirements of the
80960CA microprocessor. In each case the applicable 80960CA clock frequency and AC timing were
taken together with an address buffer delay (if needed) and a typical 2 ns guardband to generate the
27960CX AC timing. Worst case timings were

@33 MHz the clock cycle is

27960C2·33 tsvch

30 ns.

30 ns - 16 ns - 7 ns

= 7 ns
5·199

tOV2 of the 80960CA is 3 ns - 16 ns.
Decoder = 7 ns

l
D

PCLK

."
ADDR

!»

....

ADS

(J1

N
0
0

><
.....

'~I

III

FFFF FF04

FFFF FFOO

FFFF FrOC

FFFF FF06

DATA

.....
CO

/ ' i--~

n. n. rI- n. n. n. n. tl rt tl tl tl n. n.n.n.n. rt rt n. n.n. n. n. n.n. n. n. n. n.n. n. tl tl tl n. rt n.n.n.n. ~
II III mn
mmmI
~] m
ml~
I
K

>
g"

V'I

~i\

...cCD

Ilmm m mOO~01~02~03~ ~

I FIRST BYTE WRAPPED AROUND

'00

nHI mm

04~05~06~07n

08~09~A~BY

III XXX

mOC~OD~OE~OF~

!-NWS 1

C
"C

S-

BLAST

NRAD = 31

I-NXDA=3-

1-2WS~

I-NXDA=3-

\lr

1-2WS~

I-NXDA=3~

1-2WS~

290236-10

2EJ
Iiiiil

~
~

2.§J
~

27960CX

iii '"

>Vl

"I~ >

ClK

uOQUU

D....J

c:(

0 6 I-'l Vpp > VIL will cause a slight increase in standby current.
6. The device must be in the idle state (by asserting RESET or using BLAST) before going intp standby.

CAPACITANCE(1) TA
Symbol

= 25°C, f = 1.0 MHz

Parameter

Typ

Max

Unit

Condition

CIN

Input Capacitance

VIN

COUT

Output Capacitance

VOUT

Cvpp

Vpp Capacitance

VIN

NOTE:
1. Sampled. Not 100% tested.

5-205

inter

27960CX

AC INPUT/OUTPUT REFERENCE WAVEFORMS

. AC TESTING LOAD CIRCUIT.

1.5V

TIMING PARAMETER
_

--VOH

780.0.

DEVICE
UNDER
TEST

11--+_

OUTPUT

CL =80 Pf

'---VOL
290236-15
290236-14

CL includes jig capacitance
For tCHQZ CL = 5 pF and RL = 4050.

Input and output timings are measured from 1.5V.
Timing values are specified assuming maximum input
and output rise and fall time = 4 ns.

CLOCK CHARACTERISTICS
Versions

25 MHz

33 MHz

Symbol

Parameter

Min

30.3

Max

Min

20 MHz

Max

16 MHz

Max

Units

Max

ClK

Period
Rise Time

tpF

Fall Time

tPL

low Time

(tl2) - 2

tl2

(tl2) - 3

t/2

(tl2) - 4

tl2

(tl2) - 4

tl2

tpH

High Time

(tl2) - 2

tl2

(tl2) - 3

tl2

(tl2) - 4

tl2

(tl2) - 4

ti2

Min

tpR

Min

Max Rise Time for Programming ClK

62.5
4

= 100 ns

CLOCK WAVEFORM
i----CLK----i

290236-16

5-206

ns
4'

inter

27960CX

Program/Program Verify
Initially, and after each erasure, all bits of the
EPROM are in the "1's" state. Data is introduced by
selectively programming "O's" into the desired bit
locations. Although only "O's" can be programmed,
both "1's" and "O's" can be present in the data
word. Ultraviolet erasure is the only way to change
"Dis" to "1 IS".
'.1._

n _______ : ____ -'_: ___ .1. _ _ _ ...1 _ •• L _ _ "
: ___ : ___
rluylQllllllllly IIIUU~ ' " CllLClt:;U VVIIV'II vpp 10:. I ClI:;'t:;;U LU

12.75V. ProgramlVerify operation is synchronous
with the clock and can only be initiated following an
idle state. Program and Program Verify take place in
3 clock cycles. In the first clock cycle, addresses
and data are input and programming occurs. Program Verify follows in the second clock cycle and
the third clock cycle terminates synchronous Pro~
gramlVerify operation, returning the state machine
to the idle state with outputs at high impedance.

The programmer can verify the device identifier and
choose the programming algorithm that corresponds
to the Intel 27960eX. The inteligent Identifier can
also be used to verify that the product is configured
with the desired Read mode options for wait states.
inteligent Identifier mode is entered when A9 (pin 32) ,
is raised to its high voltage (VID) level. The internal
state machine is then set for intelligent Identifier
Read operation. Reading the identifier is similar to a
0 ....... ...1 ................... +:"" ....... ""

................... _i ........... +............ _4': ............ ...1

",",,,\.1 "" .......... ICU.IVII VII Cl

VII~

.,a.L .:na.u;;

vUIIII~UlvU

......... ....
...,IV""-

uct. Up to four bytes can be read in a single burst
access. inteligent Identifier read is terminated by a
synchronous BLAST input, returning the state machine to the .idle state with outputs at high impedance.
The four byte block code for the inteligent Identifier
code is located at address OOH through 03H and is
encoded as follows:

As in the Read mode, A2-A16 point to a four byte
block in the memory array. During programming, the
,internal address increment circuitry is disabled and
the programmer must supply Ao and A1 to point to
an individual byte within the four byte block that is to
be programmed. Only one byte is programmed in
,each 3 cycle ProgramlVerify sequence.

MEANING
IntellD

(A1, AO)
Byte 00

DATA
89h

27960
ex

Byte 01
Byte 10

EOh
01b

1 Wait State
2 Wait States

Byte 11
Byte 11

01b
10b

Program Inhibit'
RESET MODE
The Program Inhibit mode allows parallel programming and verification of multiple devices with different data. With Vpp at 12.75V, a ProgramlVerify sequence is initiated for any device that receives a valid ADS pulse and rising clock edge while es is asserted. A PGM pulse programs data in the first cycle
of the sequence and data for Program Verify is output in the second cycle. The ProgramlVerify sequence is inhibited on any devices for which es is
not asserted. Data will not be programmed and the
outputs will remain in their high impedance state.

inteligent IdentifierTM Mode
The device's manufacturer, product type, and configuration are stored in a four byte block that can be
accessed by using the inteligent IdentifierTM mode.

Due to the synchronous nature of the 27960eX, the
Various operating modes must be initiated from a
known idle state. During normal operation, the internal state machine returns to an idle state at the termination of a bus access (after BLAST is asserted).
During initial device power up, the state machine is
in an indeterminant state. The reset mode is provided to force operation into the idle state. Reset mode
is entered when the RESET pin is asserted. Output
pins are asynchronously set to the high impedance
state' and address latches are put into the flow
through mode. A reset is successfully completed
and the state machine set in an idle state when
RESET has been asserted for a minimum of 10
clock cycles and deasserted for five clock cycles.

5-207

inter

27960CX

FAIL

290236-17

Figure 11. Qulck·Pulse Programmlng™ Algorithm

5-208

27960CX

ERASURE CHARACTERISTICS
(FOR WINDOWED DEVICES)

QUICK-PULSE PROGRAMMINGTM
ALGORITHM

Exposure to light of wavelength shorter than 4000
Angstroms begins erasure. Sunlight and some fluorescent lamps have wavelengths in the 3000-4000
Angstrom range. Constant exposure to room-level
fluorescent light can erase the EPROM array in
about 3 years (about 1 week for direct sunlight).
Opaque labels over the window will prevent unintentionai erasure under these iighting conditions.

The Quick-Pulse Programming algorithm programs
Intel's 27960CX. Developed to substantially reduce
programming throughput time, this algorithm allows
optimized equipment to program a 27960CX in under 17 seconds. Actual programming time depends
on the programmer used.

The recommended erasure procedure is exposure
to 2537 Angstrom ultraviolet light. The minimum integrated erasure time using a 12000 fW/cm2 ultraviolet lamp is approximately 15 to 20 minutes. The
EPROM should be placed about 1 inch from the
lamp. The maximum integrated dose is 7258
Wsec/cm2 (1 week @ 12000 fW/cm 2). High intensity UV light exposure for longer periods can cause
permanent damage.

The uuick-Puise Programming aigorithm uses a
100 /-Ls pulse followed by a byte verification to determine when the addressed byte is correctly programmed. The algorithm terminates if 25 100 /-Ls
pulses fail to program a byte. Figure 11 shows the
27960CX Quick-Pulse Programming algorithm flowchart.
The entire program-pulse/byte-verify sequence is
performed with Vee = 6.25V and Vpp = 12.75V.
The program equipment must establish Vee before
applying voltages to any other pins. When programming is complete, all bytes should be compared to
the original data with Vee = 5.0V and Vpp =
12.75V.

D.C. PROGRAMMING CHARACTERISTICS TA
Symbol

Parameter

III

Input Load Current

Notes

= 25° ±5°C

Min

Max

Unit

Condition

/-LA

VIN = VIH or VIL

lee

Vee Program Current

125

CS = VIL

Ipp

Vpp Program Current

CS = VIL

VIL

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

2.0

VOL

Output Low Voltage(Verify)

VOH

Output High Voltage(Verify)

VID

As inteligent Identifier
Voltage

Vee

Supply Voltage (Program)

Vpp

Program Voltage

Vee

+ 0.5

0.40
Vee - 0.8
11.5

IOL = 2.1 mA

IOH = -400/-LA

12.5

6.0

6.5

12.5

13.0

NOTES:
1. The maximium current value is with outputs unloaded.
2. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. During programming clock levels are VIH and VIL.

5-209

27960CX

A.C. PROGRAMMING, RESET AND 10 CHARACTERISTICS O·C < T A < + 70·C
No_

Symbol

tAVPL

Address Valid to PGM low

/A-s

tCHAX

ClK High to Address Invalid

lis

tLLC::H

ADS low to ClK High

tCHLH

ClK High to ADS High

. . 50

'. tSVCH

Parameter

Notes

CS Valid to ClK High

tCHSX

ClK High to CS Invalid

tCHQV

ClK High to DOUTValid

tCHQX

tBVCH

Min

Max

Unit

ns .

ns
100

ClK High to DOUT Invalid

BLAST Valid to ClK High

50 .

ns
/A-s

tCHBX

elK High to BLAST Invalid

taVPL

DATA Valid to PGM low

tpLPH

PGM Program Pulse Width

95
2

/A-s

105

/A-s

tpHQX

PGM High to DIN Invalid

tcLPL

ClK low to PGM low

tQZCH

DIN Tri-State to ClK High

/A-s

tvcs

Vee Program Voltage to ClK High

/A-s

tvps

Vpp Program Voltage to ClK High

/A-s

tAeHCH

Ae VID Voltage to ClK High

/A-s

tcHAeX

ClK High to Ae Not VID Voltage

tRVCH

RESET Valid to ClK High

tCHCL

ClK High to ClK !-ow

100

tCLCH

ClK low to ClK High

100

NOTES:
1. If CS is low, ADS can go low no sooner than the falling edge of the previous ClK.
2. ADS must return high prior to the next rising edge of clock.
3. CS must remain low until after the rising edge of CLK1.
.
4. BLAST must return high prior to the next rising edge of CLK.
5. Max CLK rise/fall time is 100 ;'s.
6. RESET must be low for 10 clock cycles and high for 5 clock cycles.
7. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.

5-210

inter

27960CX

elK

V1H
V1L

J !

ADDR V1H

V1L

CD:

}-EM
:0

ADDRESS 0

(

ADDRESS 1

u
DATA 0

J>---<~ DATA 1

C\ '......."'....";;,OU;;";,T..,,,,,

\!VX~

f-- e
:

--1'--..1

_ _ VIH
BLAST

k0 Vpp > VIL will cause a slight increase in standby current
The device must be in the idle state (by asserting RESET or using BLASn before going into standby.

5-224

infef

27960KX

CAPACITANCE(1)

TA = 25°C, f = 1.0 MHz

Symbol

Parameter

Typ

Max

Unit

Condition

CIN

Input Capacitance

VIN =OV

COUT

Output Capacitance

VOUT =OV

CVPP

VPP Capacitance

VIN =OV

NOTE:
1. !';"mpIRri. nnt 1nn% tA"tRrI

AC INPUT/OUTPUT REFERENCE WAVEFORMS

AC TESTING LOAD CIRCUIT
2.1V

1.5V

780D.
TIMING PARAMETER

CL =120 PF

290237-15
VOL

For tCHQZ CL = 5 pF and RL = 4050
CL includes jig capacitance

290237-14

AG test inputs are driven at 2.4V (VOH) for a logic '1'
and 0.45V (VoLl for a logic '0'.
Input timing begins at 1.5V.
Output timing ends at VIH (2.0V) and VIL (O.SV)
Input Rise and fall times (10% to 90%) < 4.0 ns

CLOCK CHARACTERISTICS
Versions
Symbol

25 MHz

Parameter

Min
40

ClK

Period

Rise Time

Fall Time

low Time

High Time

20 MHz

Max

Min

16 MHz

Max

50
10

Min
62.5

Units

Max

ns
10

Max ClK Rise Time during Programming is 100 ns

CLOCK WAVEFORM

290237-16

5-225

inter

27960KX

accessed by using the inteligent Identifier™ mode.
The programmer can verify the device identifier and
choose the programming algorithm that corresponds
to the Intel 27960KX. The inteligent Identifier can
also be used to verify that the product is configured
with the desired Read mode options for wait states.

Inteligent Identifier mode is entered when Ag (pin
32) is raised to its high voltage (VH) level. The internal state machine is then set for inteligent Identifier
Read operation. Reading the Identifier is similar to a
Read operation on a one wait state configured product. Up to four bytes can be read in a single burst
access. inteligent Identifier read is terminated by a
synchronous BLAST input, returning the state machine to the idle state with outputs at high impedance.

"O's" to "1'8".

Program mode is entered when Vpp is raised to
12.75V. ProgramlVerify operation is synchronous
with the clock and can only be initiated following an
idle state. Program and Program Verify take place in
3 clock cycles. In the first clock cycle, addresses
and data are input and programming occurs. Program Verify follows in the second clock cycle and
the third clock cycle terminates synchronous ProgramlVerify operation, returning the state machine
to the idle state with outputs at high impedance.

The four byte block code for the inteligent Identifier
code is located at address OOH through 03H and is
encoded as follows:

As in the Read mode, A2-A16 point to a four byte
block in the memory array. During Programming the
internal address increment circuitry is disabled and
the programmer must supply Ao and A1 to point to
an individual byte within the four byte block that is to
be programmed. Only one byte is programmed in
each 3 cycle programlVerify sequence.

MEANING
IntellD
27960
KX
1 wait state
2 wait states

Program Inhibit

RESET MODE

Program Inhibit mode allows parallel programming
and verification of multiple devices with different
data. With Vpp, at 12.75V, a ProgramlVerify sequence is initiated for any device that receives a valid ALE pulse and rising clock edge while CS is asserted. A PGM pulse programs data in the first cycle
of the sequence and data for Program Verify is output in the second cycle. The ProgramlVerify sequence is inhibited on any devices for which CS is
not asserted during the first (ALE) cycle. Data will
not be programmed and the outputs will remain in
their high impedance state.

Due to the synchronous nature of the 27960KX, the
various operating modes must be initiated from a
known idle state. During normal operation, the internal state machine returns to an idle state at the termination of a bus access (after BLAST is asserted).

inteligent IdentifierTM Mode
The device's manufacturer, product type, and configuration are stored in a four byte block that can be

(A1> Ao)
Byte 00
Byte 01
Byte 10
Byte 11
Byte 11

DATA
89h
EOh
OOb
01b
10b

During initial device power up, the state machine is
in an indeterminant state. The reset mode is provided to force operation in to the idle state. Reset mode
is entered when the RESET pin is asserted. Output
pins are asynchronously set to the high impedance
state and address latches are put into the flow
through mode. A reset is successfully completed
and the state machine set in an idle state in the
cycle after RESET has been asserted for a minimum
of 10 clock cycles and deasserted for five clock cycles.

5-226

27960KX

FAil

290237-17

Figure 8. Quick-Pulse Programming™ Algorithm

5-227

27960KX

programming throughput time, this algorithm allows
optimized equipment to program a 27960KX in under 17 seconds. Actual programming time depends
on the programmer used.
.

ERASURE CHARACTERISTICS
(FOR W\NDOWED DEVICES)
Exposure to light of wavelength shorter than 4000
Angstroms begins erasure. Sunlight and some fluorescent lamps have wavelengths in the 3000-4000
Angstrom range. Constant exposure to room-level
fluorescent light can erase the EPROM array in
about 3 years (about 1 week for direct sunlight).
Opaque labels over the window will prevent unintentional erasure under these lighting conditions.

The Quick-Pulse Programming algorithm uses a
100 ,...s pulse followed by a byte verfication to determine when the addressed byte is correctly programmed. The algorithm terminates if 25 100,...s
pulses fail to program a byte. Figure B shows the
27960KX Quick-Pulse Programming algorithm flowchart.

The recommended erasure procedure is exposure
. to 2537 Angstrom ultraviolet light. The minimum integrated erasure time using a 12000 fW I cm2 ultraviolet lamp is approximately 15 to 20 minutes. The
EPROM should be placed about 1 inch from the
lamp. The maximum integrated dose is 725B Wsecl
cm2 (1 week @ 12000 fW/cm2). High intensity UV
light exposure for longer periods can cause permanent damage.

The entire program-pulse,· byte-verify sequence is
performed with Vee = 6.25V and Vpp = 12.75V.
The programming equipment must establish Vee before applying voltages to any other pins. When programming is complete, all bytes should be compared
to the original data with Vee = 5.0V and Vpp
12.75V.

QUICK-PULSE PROGRAMMING
ALGORITHM
The· Quick-Pulse Programming algorithm programs
Intel's 27960KX. Developed to substantially reduce

D.C. PROGRAMMING CHARACTERISTICS TA = 25°C ±5°C
Symbol

Parameter

Notes

Min

Max

Unit

Test Condition

= VIH or VIL
= VIL
CS = VIL

III

Input Load Current

,...A

VIN

lee

Vee Program Current

125

Ipp

Vpp Program Current

VIL

Input Low Voltage

-0.5

O.B

VIH

Input High Voltage

2.0

Vee + 0.5

VOL

Output Low Voltage (Verify)

0.40

IOL

VOH

Output High Voltage (Verify)

IOH

VID

A9 inteligent Identifier Voltage

11.5

12.5

Vee

Supply Voltage (Program)

6.0

6.5

Vpp

Program Voltage

12.5

13.0

Vee- O.B

NOTES:
1. The maximum current value is with outputs unloaded.
2. Vec must be applied simultaneously or before Vpp and remove simultaneously or after Vpp.
3. During programming clock levels are VIH and VIL.

5-22B

= 2.1 mA
= -400,...A

27960KX

AC PROGRAMMING, RESET AND 10 CHARACTERISTICS
No

Symbol

Parameter

Notes

O°C

< T A < + 70°C

Min

Max

Units

tAvPl

Address Valid to PGM low

J.Ls

tCHAX

ClK High to Address Invalid

tllCH

ALE low to ClK High

tCHlH
... _.. - ..

ClK High to ALE High

"::SVL;H

,-.e
\/ .... 1;""""""
_ _ ,"UIIU "V

tCHSX

ClK High to CS Invalid

v
""'-'"

f""

U; .... h
I

"Mil

tCHQV

ClK High to DOUT Valid

tCHQX

ClK High to DOUT Invalid

tBVCH

BLAST Valid to ClK High

tCHBX

ClK High to BLAST Invalid

tQVPl

DATA Valid to PGM low

tplPH

PGM Program Pulse Width

100

ns
ns

2
95

J.Ls
105

J.Ls

tPHQX

PGM High to DIN Invalid

J.Ls

tClPl

ClK low to PGM low

tQZCH

DIN in Tri-State to ClK High

/Ls

tvcs

VCC Program Voltage to ClK High

/Ls

tvps

Vpp Program Voltage to ClK High

J.Ls

tAAHCH

Ag VID Voltage to ClK High

/Ls

tCHAgX

ClK High to A9 not VID Voltage

/Ls

tRVCH

RESET Valid to ClK High

tCHCl

ClK High to ClK low

100

tclCH

ClK low to ClK High

100

NOTES:

1. If CS is low, ALE can go low no sooner than the falling edge of the previous ClK.
2. ALE must return high prior to the next rising edge of clock.
3. CS must remain low until after the rising edge ClK1.
4. BLAST must return high prior to the next rising edge of ClK.
5. Max ClK rise/fall time is 100 ns.
6. RESET must be held low for 10 cycles and high for 5 cycles before performing a read.
7. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.

5-229

intJ

27960KX

.......

............. .

'"
c · · · · · -----------

---....-ri-+"" ............................... .

.. J ....

®
:r:

..J

:> :>

'"u
..J

:r:

..J

>- :>
c
c

...'"

:r:
:> >-

:> :>

...c~

..J

:r:

..J

:r:

..J

:r:

..J

:r:

Figure 9. 27960KX Programming Waveforms
5-230

..J

:> :>
113

l>l>-

e.>
e.>

intJ

27960KX

:@f
v
CLOCK

n LJn Lfr: -LF--

:---..:
.
•

IH
VIL.....J

____;....-___...J·XI!:~~:::

ADDR

XXXXXxxxxXXXXXX

_ _ _ _'!--_ _ _ _...;...._~:,««

DATA

1.0.

~ Byte 0

@~~

Vpp
VIO
Ag V

\_~--~------------~---

\:-;_-----If

'r~-:-'---:------------'~-+:

xxxxxxxxxxxxf

\xx

290237-19

Figure 10. 27960KX RESET and 10 Waveforms

5-231

APPLICATION
NOTE

AP-329

November 1990'

68030/27960CX
Burst EPROM Interface

DEAN PARMAR
SENIOR APPLICATIONS ENGINEER
PROGRAMMABLE MEMORY OPERATION

Order Number: 292064·001
5·232

68030/27960CX BURST EPROM INTERFACE
CONTENTS

PAGE

1.0 SIGNAL DEFINITIONS ............. 5-234
1.1 68030 Signals ................... 5-235
1.2 27960 EPROM Signals .......... 5-236

2.u

iNT~Ri=AC~ R~Qi.iiR~ivi~NT5

..... 5-236

CONTENTS

PAGE

3.0 CIRCUIT DESCRIPTION ...........
3.1 ADS Generation .................
3.2 STERM Generation ..............
3.3 CBACK Generation ..............
3.4 BLAST Generation ..............
3.5 Data Latches ....................

5-236
5-240
5-241
5-241
5-241
5-241

APPENDIX A .......................... 5-248
Delay Line Information ................. 5-259

5-233

intJ

AP-329

INTRODUCTION·
This application note describes the design of a circuit to
interface the 27960CX burst EPROM to Motorola's
68030 microprocessors (J.LP). The 68030 jJ,P is capable
of burst mode operation, accessing a maximum of four
long words (long word = 32 bits) during a burst cycle.
A 2-0-0-0 burst operation (2 wait states for the first
word access and zero wait state for subsequent accesses) is possible at 25 MHz using the 27960C2-25 burst
EPROM. At 33 MHz, a 3-0c()..0 operation is possible
using the 27960C2-33 burst EPROM. This memory interface monitors control signals from the J.LP, provides
handshake logic for the J.LP and generates ADS and
BLAST signals for the EPROMs. It also monitors

cache burst request (CBREQ) and cache inhibit (CIIN)
signals from the J.LP, and generates BLAST as appropriate.
Two designs are considered for this interface, a 33MHz system and a 25/20 MHz system. The 33-MHz
interface can be implemented with a 16R4-7 PAL, four
74F374 latches and a D-type flip/flop. The latches are
required because the 68030 latches data on the falling
edge of the clock, while the 27960 provides data on the
rising edge of clock. The latches provide plenty of setup
and hold time. The 25/20 MHz interface can be implemented with a 16R4-7 PAL and a couple of D-type
flip/flops, but requires a delayed clock for the PAL and
EPROMs. Because the clock is delayed no latches are
required.

1.0 SIGNAL DEFINITIONS

FUNCTION CODES

ADDRESS BUS

DATA BUS

TRANSFER SIZE

{<
{<
{<
{

IPlO
FeO-Fe2

IPL1
IPl2
IPEND

AO-A31

AVEC

00-031

lNTERRUPT
CONTROL

-v

SIZO

BGACK

}

BUS ARBITRATION
CONTROL

}

BUS EXCEPTION
CONTROL

}

SYNCHRONOUS
BUS CONTROL .

SIZI
RESET
OCS
ECS

HALT
MC68030

BERR

R/W
RMC

STERM

ASYNCHRONOUS
BUS CONTROL

illiIT

DBEN

STATUS

DSACKO

CDiS

DSACKI

MMUDIS

EMULATOR
SUPPORT

CIIN
CACHE CONTROL

ClK

ClOUT

Vee

CBREQ

GND

CBACK

292064-1

Figure 1. MC68030 Functional Signal Groups

5-234

intJ

AP-329

1.1 68030 Signals

1.1.6 DBEN (Output)

This section describes 68030
vant to this interface.

signals which are rele-

1.1.1 ECS (Output)

Provides an indication that a bus cycle is beginning.
The external cycle start (ECS) signal is the earliest indi,..~t1nTl

th'!llt th""

;nit1'!l1ttnlT

'!lI

hll<1 ,..",..1,.".

Th""

MC68030-initi;rte;; b~s ~;~i;'b; drlvi;; th~ -;ddr~~~:
size, function code, cache inhibit-out, and read/write
outputs and asserting ECS.
1.1.2 ADDRESS BUS

The address bus signals (AO-A31) define the address of
the byte (or the significant byte) to be transferred during a bus cycle. The ~P places the address on the bus at
the beginning of a bus cycle. The address is valid while
AS is asserted.
1.1.3 AS (Output) .

The address strobe (AS) is a timing signal that indicates
the validity of an address on the address bus and of
many control signals. It is asserted one half clock after
the beginning of a bus cycle.

The data buffer enable signal (DBEN) can be used to
enable external data buffers while data is present on the
data bus. During a read operation DBEN is asserted
one clock cycle after the beginning of the bus cycle, and
is negated as DS is negate~In a write operation,
DBEN is asserted at the time AS is asserted, and is held
active for the duration of the cycle. DBEN timings may
prevent the use of a synchronous system using twoclock bus cycles.
1.1.7 STERM (Input)

This input is a bus handshake signal indicating that the
addressed port size is 32 bits and that data is to be
latched on the next falling clock edge for a read cycle.
This signal applies only to synchronous operation. For
synchronous bus cycles, external devices assert the synchronous termination signal (STERM) as part of the
bus protocol. During a read cycle, the assertion of
STERM causes the ~P to latch the data. During a
write cycle, it indicates that the external device has successfully stored the data. In either case, it terminates
the cycle, and indicates that the transfer was made to a
32-bit port.
1.1.8 CBREQ (Output)

This three-state output signal requests a burst mode
operation to fill a line in the instruction or data cache.

1.1.4 DATA BUS

The data bus signals (DO-D31) run on a bi-directional,
non-multiplexed, parallel bus that contains the data being transferred to or from the ~P. A read or write operation may transfer 8, 16, 24 or 32 bits of data (one, two,
three or four bytes) in one bus cycle. During a read
cycle the data is latched by the ~P on the last falling
edge of the clock -for that bus cycle.

1.1.9 CBACK (Input)

This input signal indicates that the accessed device can
operate in the burst mode, and can supply at least one
more long word for the instruction or data cache.
1.1.10 CIIN (Input)

1.1.5 DS (Output)

The data strobe (OS) is a timing signal that applies to
the data bus. For a read cycle the· ~P asserts DS to
signal the external device to place data on the bus. It is
asserted at the same time as AS during a read cycle.
For a write cycle DS signals to the external device that
the data to be written is valid. The /loP asserts DS one
full clock cycle after the assertion of AS during a write
cycle.

This input signal prevents data from being loaded into
the MC68030 instruction and data caches. It is a synchronous input signal and is interpreted on a bus-cycleby-bus-cycle basis. CIIN is ignored during all write cycles.

5-235

intJ

AP-329

2.0 INTERFACE REQUIREMENTS

1.2 27960 EPROM Control Signals
1.2.1 ADS: ADDRESS STROBE

Indicates the start of a new bus access. It is active low·
in the first clock cycle of a bus access.
1.2.2 BLAST: BURST LAST

Terminates a concurrent burst data cycle at the rising
edge of CLK. Must be asserted by the fourth data
word.
1.2.3 CS: CHIP SELECT

Master device enable. When asserted (active low) data
can· be written to and read from the device. In read
mode, CS, enables the state machine and the 1/0 circuitry. A memory access begins on the first rising edge
of clock after ADS and CS are asserted. CS can be deasserted after the number of wait-states, N, has expired,
and the EPROM will continue to burst out data for the
current cycle. If CS is de-asserted during the wait-state
period the burst access will be aborted.

The interface logic is designed to work in burst mode,
with the synchronous termination signal, STERM, as
the handshake for the p.P indicating EPROM readiness
for a burst transfer. The interface logic will monitor
control signals from the ,...P, i.e., ECS, AS, DBEN and
CBREQ .and generate ADS and BLAST signals for the
27960 and STERM and CBACK signals for the, lip.
STERM will be asserted by the interface logic after the
number of wait states, N, has expired. The logic will
also monitor CBREQ and CIIN signals and generate
BLAST as appropriate.
Figures 2 and 3 show schematics of the 68030/27960
Burst EPROM interfaces.

3.0 CIRCUIT DESCRIPTION
This section describes the burst mode operation of the
68030 p.P followed by a brief description of the interface circuits (Figures 2 and 3). Figure 2 shows a
33 MHz design which allows 3-0-0-0 burst operation;
Figure 3 shows a 25/20 MHz design which allows a
2-0-0-0 and a 1-0-0-0 burst operation at 25 MHz and
20 MHz respectively.

5-236

33 MHz
CLOCK
GENERATOR

r--

r-L,.)

(

CS2

ADDRESS
DECODER

CLK

ClK

'11

ADDR

rEi
c

""3:
Co)
Co)

ClK

CBACK

::E:

STERM

(II

DB EN
68030
00-031

BlASTl

CBREQ

PAL
16R4-7

ADS

BlAST2

BLAST

r:--.

CD
0

C{'
I\)
t.)

Co)

0
.....
N

CS
ClK
27960
128K

X
8
BLAST

~
~
~
~

CS
ClK
27960
128K

X
8
BLAST

~c1r-

~
~
~
~

ClK
27960
12E,K

X
8
BlASl'

L...- r-

I----t
~

I:---t
I---'

CS
CLK
27960
12BK

X
8
BLAST

ADS

>
12
Co:!

l+CIIN I+-

...... .....
CD

I\)

(II

"::u

BlAST3

0
3:

;.-

S"
CD

CIIN

CLK

---.~7~4

L...!~

OE
Y-D
32

1/2

74.74

CIIN
292064-2

(

CLK

I--CLOCK
OSCILLATOR

f---I

CLOCK
DRIVER/
INVERTER

CLK

~CLK
at

.--

ADDRESS
DECODER

"11

iri

1
ADDRJ

~
U1
......
I\)

:I:
N

CBACK
STERIo4

CXl

......
I\)

DBEN
68030
00-031

-.j

CIIN

..-....

III
()

8
BLAST

27960.
128K

x
8

BLAST

~
~
~
~

CLK
27960
128K

x
8

BLAST

f---I
f---I
f---I

CLK
27960
128K

X
8
BLAST

»
"'tI
Co)
r.)

I+~
R
0

L.....-~ S Q~

BLAST3

74F74

A~
BLAST

cs
CLK

BLAST2

PAL
16R4-7

27960
128K

f------.
f------.
f------.
f------.

ADS_CK
~

::u

I-

BLASTl

cs
CLK

CBREO

c.n 0
w
N
0
U)

CLK

I\)

74F74

L....--

CIIN

CLK

74F74

---t

--,R.....32

CIIN

292064-3

AP-329

The circuits are designed to operate in a 32-bit burst mode. Four long words (long word
transferred during a single burst operation. Figure 4 shows a burst operation cycle.

BURST OPERATION

ICYCLE 1

CYCLE 2

FIRST ACCESS OF
BURST OPERATION

"\~~~U~~~~E~~~;;;u/

CYCLE 4

BURST FILL CYCLE

BURST t.lODE
REQUESTED AND
ACKNOWLEDGED

----------------+1CYCLE 3

BURST FILL CYCLE

32 bits) may be

BURST FILL CYCLE

BURST t.lODE BEGINS HERE

292064-4

, Figure 4_ Burst Operation Cycles

The circuits also allow address wrap around so that the entire four long words in the cache line can be filled in a
single burst operation regardless of the initial address. Figure 5 shows a burst filling wrap-around example.

SOD

I
FINAL CACHE ENTRY
TO BE FILLED

S04

SOB

I b41 b5 Ib61 b71

IbBI b91 bA I bB I

I
FIRST LONG WORD ACCESS
- INCLUDES FIRST PART
OF OPERAND REQUIRED

I
SECOND CACHE ENTRY
TO BE fiLLED

SOC

I
THIRD CACHE ENTRY
TO BE FILLED

292064-5

Figure 5_ Burst Filling Wrap-Around Example

The initial cycle is a long word access from address $06. Because the interface logic returns CBACK and STERM
(signaling a 32-bit port), the entire long word at base address $04 is transferred. Since the initial address is $06 when
CBREQ is asserted, the next entry to be burst filled into the cache should correspond to address $08, then $OC, and
last, $00.
The 68030 ,...p does not assert CBREQ during the first portion of a misaligned access if the remainder of the access
does not correspond to the same cache line. Figure 6 shows an example in which the first portion of a misaligned
access is at address $OF. With a 32-bit port the first access corresponds to the cache entry at address $OC, which is
filled using a single-entry load operation. The second access at address $10 (corresponding to the second cache line)
requests a burst fill and the processor asserts CBREQ. During this burst operation long words $10, $14, $18 and $IC
are all filled, and in that order.

5-239

inter

AP-329

JOO

JOB

J04

JOC

I I I I I
bC

NO CBREQ ASSERTED I'----'-----'-_L---'

I
FIRST LONG WORD CACHED
,NO BURST REQUEST

Jl0

J14

I
SECOND CYCLE BURST
REQUESTED

J18

J1C

I
THE REMAINING CACHE ENTRIES FOR SECOND BLOCK ARE BURSTED

292064-6

Figure 6. Deferred Burst Filling Example
The ,...p does not assert CBREQ if the cycle is for the first access of an operand that spans two cache lines (crosses a
modulo 16 boundary).,

3.1 ADS Generation
Figure 7 shows the timing of ADS for the 33·MHz design of Figure 2. A 4-bit counter is implemented in the PAL
which is used for timing of ADS, STERM, CBACK, and BLAST. Assertion of AS enables the 4·bit counter. ADS is
asserted following Count I (CNTl), and de-asserted at Count 2 (CNT2).

30ns

2
CNT1

,.. CNT2

ClK

292064-7

Figure 7. ADS Generation for 33·MHz Circuit

5·240

of Figure 2

inter

AP"'329

For the 25/20-MHz system (Figure 3) ADS is referenced to D_CLK (Figure SA). D CLK is the inverted and delayed version of CLK. D_CLK is used for
generating ADS, STERM, CBACK and BLAST. For
this design a 3-bit counter is implemented in the PAL.
ADS is asserted when ADS_CK clocks the first flip/
flop. ADS_CK makes the low to high transition when
both AS and CS are vaJid. The next rising edge of D_
CLK resets the first flip/flop, and ADS is pulled high.
With this implementation data latches are not required,
__ ...lI_"'nnn ____ t n n n 1 __ ..__ .L

ClUU

~-v-u-v

____ •• :_

Ul '" l-V-V-V UUl:!JL upCaaLIUll

___ ."

•

l'U:!J:!JIUIC i1t.

25 MHz and 20 MHz respectively. This design buys an
extra wait state as shown in the timing diagram of Figure 10. If the use of delay line is not preferred, then the
design shown in Figure 2 can be used to provide 3-0-0-0
and 2-0-0-0 performance at 25 MHz and 20 MHz respectively.

3.2 STERM Generation
3.2.1 33 MHz DESIGN

STERM is asserted after the number of wait states, N,
has expired (N is the number of wait states with respect
to the EPROM). For the 33-MHz design, a 2 wait-state
EPROM (27960C2-33) is used, which equates to a
3 wait state system performance. STERM is asserted on
count 4 and de-asserted on count 8 (Figure 9).

It is also used to terminate a burst operation of less

than 4 words. Assertion of BLAST during the waitstate period is ignored by the EPROM. There are three
conditions for generation of BLAST (i.e., BLAST!
through BLAST3) which are AND gated to produce
the BLAST signal for the EPROM:
3.4.1 BLAST1: (Normal Burst End)

BLAST! is used to terminate a 4-word burst. For the
33-MHz design BLASTI is asserted on count 7 and deasserted on count 8 (Figure 9). For the 25-MHz design,
BLAST! is asserted on count 6 of D_CLK and de-asserted on count 7 of D_CLK (Figure 10).
3.4.2 BLAST2: (Deferred Burst)

BLAST2 is generated if the ,...p accesses a misaligned
operand. Figure IIA shows an access.to a misaligned
operand followed by a deferred burst access. In this
case the burst operation is deferred because the first
access corresponds to cache entry at $OC which is accessed as a single word. The second access at address
$10 corresponds to the second cache line, and a burst
request is made: The ,...p asserts CBREQ during a burst
request. BLAST2 is used to terminate the single word
access. Figure liB shows the logic for generating
BLAST2. The state of CBREQ is monitored, and if it is
high BLAST2 is asserted on count 4 (after the number
of wait states, N, has expired) and de-asserted on COl;.,t

3.2.2 25 MHz DESIGN

For the 25 MHz design, STERM is asserted on count 3
(reference to D_CLK) and de-asserted on count 7
(Figure 10).

3.4.3 BLAST3

3.3 CBACK Generation

BLAST3 is generated if CIIN is asserted during a burst
cycle. Figure 12 shows the timing diagram for generation of BLAST3. CIIN resets the flip/flop, and the next
rising edge of clock pulls BLAST3 high.

The timing of CBACK is the same as STERM.

3.5 Data Latches
3.4 BLAST Generation
BLAST is used to terminate a burst cycle. For a 4-word
burst BLAST is asserted following the rising edge of
CLK in the next to last clock cycle (Figures 9 and 10).

The four data latches latch the 32-bit data on the rising
edge of CLK (since the 27960 burst EPROM provides
data on the rising edge of CLK). The 68030 ,...p reads
the data on the falling edge of CLK. The latches provide plenty of setup and hold times for the data. DBEN
signal is used to enable the data latches.

5-241

AP-329

Q 1----1 0

74F74

',CS

x/
,--

Q
I

' '

Implemented in PAL

292064-8

NOTES:

~ is inverted and delayed version of elK.
at = 5 ± 1 ns for 25 MHz System.
at = 9 ± 1 ns for 20 MHz System.

Figure SA. ADS Generation for 25/20 MHz Circuit of Figure 3

CLOCK INPUT
FROM OSCILLATOR

....f'lF
292064-9

Figure SB. Circuit for Generating Opposite Phases of ClK

5-242

inter

AP-329

30no

EPROM
DATA

J.'P DATA

292064-10

NOTES:
3-0-0-0 = 3 wait states for first word access, 0 wait states for subsequent words.
68030 latches data on the falling edge of clock.
A 4-bit counter is implemented in the PAL which provides timing for STERM, CBACK, ADS and BLAST1.
BLAST1 is ANDed with BLAST2/3 to generate BLAST for the EPROMs (see Figure 2).

Figure 9. 3-0-0-0

4 Word Burst Operation (33 MHz)

5-243

intJ

AP-329

40 ns

II)

ns '0-10

..
..J

Vi
a.

=I.

::~"':"""'r-"'''':'''''''r-"'
tS:
:
:
:............:
:

BlAST3

,....;- tH

latch' delay
.

J"P OATA

~C!:::
00

"":--1-0.

-:--r-"'

BlAST3 AS A RESULT OF CIIN

I
292064-14

elK
FROM PAL
292064-15

Figure 12. Timing Diagram for Generation of BLAST as Result of CIIN While STERM is Asserted

5-247

AP-329

APPENDIX A
CONTENTS
i. AC parameters and timing waveforms for the
27960CX burst EPROM and the 68030 ""P.
ii. Delay line information.

EXPLANATION OF AC SYMBOLS
The nomenclature used for timing parameters are as
per IEEE STD 662-1980 IEEE Standard Terminology
for Semiconductor Memory.

The fifth character represents the signal level indicated
by the fourth character. The list below shows character
representations.
A:
B:
C:
H:
L:
P:
X:

Each timing symbol has five characters. The first is
always a "t" (for time). The second character represents a signal name (e.g., CLK, ADS, etc.). The third
character represents the signal's level -(high or low) for
the signal indicated by the second character. The fourth
character represents a signal name at which a transition
,occurs marking the end of the time interval being specified.

5-248

Address
R: Reset
BLAST
Q: Data
Clock
S: "'C;:';hi=-p"'S-=;el;::"ec=Ot
Logic High Level
t: Time
ADS/Logic Low Level
V: Valid
Vpp Programming Voltage
Z: Tristate Level
No longer a valid "driven" logic level

inter

AP-329

AC CHARACTERISTICS

o·c < TA <

Versions
No_
1

+70·C,

vcc =

5V ±10%

27960C2-33

27960C2-25

27960C1-20

33 MHz

20 MHz

16MHz

2 Wait State

25 MHz
2 Wait State

1 Wait State

Min

Max

27960C1-16
Units

Symbol

Parameter

Notes

Min

tAVCoH

Address
Valid to

ClKO

Max

_I '"

11:_1VL.~nlyll

tCNHAX

ClK High to
Address
Invalid

tllCH

ADS low to
ClK High

ClKO

tCHlH

ClK High to
ADS High

tsvCH

Chip Select
Valid to
ClK High

tCNHSX

ClK High to
Chip Select
Invalid

tCHQV

ClK High to
Data Valid

tCHQX

ClK High to
Data Invalid

tcHQZ

ClK High to
Data Hi-Z

tBVCH

BLAST
Valid to
ClKHigh

tcHBX

ClKHighto
BLAST
Invalid

27
5

ns
ns

NOTES:
1. Valid signal level is meant to be either a logic high or logic low.
2. The subscript N represents the number of wait states for this parameter. CS can be de-asserted (high) after the number
of wait states (N) has expired. The EPROM will continue to burst out data for the current cycle.
3. BLAST must be returned high before the next rising clock edge.
4. The sum of tcHOV + tAVCH + NClK will not ,equal actual tAVOV if independent test conditions are used to obtain tAVCH
and tCHOV (N = number of wait states).
5. ADS must be returned high before the next rising clock edge.
6. Sampled but not 100% tested. The transition is measured ± 500 mV from steady state voltage.
7. For capacitive loads above 80 pF, tcHOV can be derated by 1 ns/20 pF.

5-249

inter

AP-329

..,J.

®
®

J
en
~

Figure 10. 27960CX

2 Walt State AC Waveforms
5-250

AP-329

AC ELECTRICAL SPECIFICATIONS -

Num.

CLOCK INPUT (see Figure 9)

16.67 MHz

Characteristic

20 MHz

Min

16.67

12.5

Ma.

Min

12.5
60

2.3 Clock Pulse Width Measured from 1.5 V 10 1.5 V
4,5 Clock Rise and Fall Times

Frequency of Operation

Cycle Time Clock

25 MHz

Max

Min

33.33 MHz

Min

Ma.

Unit

33.33

MHz

Ma.

2.0 V
0.8 V

Figure 9. Clock Input Timing Diagram

292064-17
Reprinted with permission of Motoro)a Inc.

5-251

inter

AP-329

AC ELECTRICAL SPECIFICATIONS see Figures 11 through 16)

READ AND WRITE CYCLES (VCC=5.0 Vdc ± 5%; GND=O Vdc; TA=O to 70'C;

16.67 MHz
Num.
6

Characteristic
Clock High to Function Code. Size, RMC. IPEND,
Address Valid

CiOiJ'i',

ZOMHz

25 MHz

33.33 MHz

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Clock High to ECS. OCS Asserted

Function Code, Size, RMC, IPENO, CIQIiL
Address Valid to Negating Edge of ECS

ns
\

Clock High to Function Code, Size, RMC, ClOUT, Address,
Data High Impedance

Clock High to Function Code, Size, RMC, IPEND, ClOUT,
Address Invalid

Clock Low to AS, OS Asserted. CBREO Valid

9A'

AS to OS Assertion Skew (Read)

-15

-10

-8

9B'4

AS Asserted to OS Asserted (Write)

lOA

OCS Width Asserted

10B7

ECS, OCS Width Negated

Function Code, Size, RMC, ClOUT, Address Valid to AS
Asserted (and OS Asserted, Read)

ECS Width Asserted

Clock Low to AS, OS, CBREO Negated

Clock Low to ECS/OCS Negated

AS, OS Negated to Function Code, Size, RMC ClOUT,
Address Invalid

AS (and OS Read) Width Asserted (Asynchronous Cycle)

12A

15
15
10

10
10

ns
ns

OS Width Asserted (Write)

AS (and OS, Read) Width Asserted (Synchronous Cycle)

AS, OS Width Negated

OS Negated to AS Asserted

Clock High 10 AS, OS, RIW, DBEN, CBREO High Impedance

AS, OS Negated to RIW Invalid

Clock High to RIW High

Clock High to RIW Low

RIW High to AS Asserted

RIW Low to OS Asserted (Write)

Clock High to Data-Out Valid

Data-Out Valid to Negating Edge of AS

25A9." OS Negated to DBEN Negated (Write)

AS, OS Negated to Data-Out Invalid

Data-Out Valid to OS Asserted (Write)

Late BERR/HALT Asserted to Clock Low (Setup)

27A

Data-In Valid to Clock Low (Setup)

28'2

AS, OS Negated to DSACK., BERR, HALT. AVEC
Negated (Asynchronous Hold)

Clock Low to DSACKx, BERR, HALT, AVEC Negated
(Synchronous Hold)

100

AS, OS Negated to Data-In Invalid (Asynchronous Hold)

AS, OS Negated to Data-In High Impedance

Clock Low to Data-In Invalid (Synchronous Hold)

Clock Low to Oata·ln High Impedance (Read followed by Wrke)

14A"
14B
15
15AB

25"
26"
27

2BA'2
29'2
29A'2
30'2
3OA'2

'100

292064-18
Reprinted w~h permission of Motorola Inc.

5-252

intJ

AP-329

AC ELECTRICAL SPECIFICATIONS (Continued)
16.67 MHz
Hum.

Chlrlet.risti.

31 2
3M3

20 MHz

25 MHz

Min

MI.

Min

MIX

Min

MIX

DSACKx Asserted to Data-In Valid (Asynchronous Data Setup)

DSACK. Asserted to DSACK. Valid (Skew)

1.5

33.33 MHz
Min

Mo.

Unit

1.5

Clks
ns

RESET Input Transition Time

Clock Low to BG Asserted

Clock Low to BG Negated

BR Asserted to BG Asserted (RMC Not Asserted)

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

BGACK Asserted to BG Negated

1.5

3.5

1.5

3.5

1.5

3.5

1.5

3.5

Clks

37A

BGACK Asserted to BR Negated

1.5

Clks

396

BG Width Negated

BG Width Asserted

39A

Clock High to DBEN Asserted (Read)

Clock Low to DBEN Negated (Read)

Clock Low to DBEN Asserted (Write)

Clock High to DBEN Negated (Write)

RIW Low to DBEN Asserted (Write)

455

DBEN Width Asserted

45A9

DBEN Width ASserted

Asynchronous Read
Asynchronous Write
Synchronous Read
Synchronous Write

60
120
10
60

RIW Width Asserted (Asynchronous Write or Read)

150

46A

RIW Width Asserted (Synchronous Write or Read)

47A

Asynchronous Input Setup Time to Clock Low

47B

Asynchronous Input Hold Time from Clock Low

484

50
100

40
80

10
50

5
40

125
75

DSACKx Asserted to BERR. HALT Asserted

Data-Out Hold from Clock High

RIW Asserted to Data Bus Impedance Change

RESET Pulse Width (Reset Instruction)

512

100
60
2

2
8

45
2

ns
ns

BG Negated to Bus Driven

Synchronous Input Valid to Clock High (Setup Time)

61 '3

Clock High to Synchronous Input Invalid (Hold Time)

Clock Low to STATUS. REFILL Asserted

Clock Low to STATUS. REFILL Negated

59'0

BGACK Negated to Bus Driven

20
512

60 '3

BERR Negated to HALT Negated (Rerun)

5
30

sa tO

25
512

512

Clks

Clks
ns

NOTES:
,. This number can be reduced to 5 nanoseconds if strobes have equal loads.
2. If the asynchronous setup time (#47A) requirements are satisfied. the DSACKx low to data setup time (#311 and DSACKx low
to BERR low set':!E..!!!!'e (#48) can be ignored. The data must only satisfy the data-in clock low setup time (#27) for the following
clock cycle and BERR must only satisfy the late BERR low to clock low setup time (#27A) for the following clock cycle.
3. This parameter specifies the maximum allowable skew between DSACKO to DSACKI asserted or DSACKI to OSACKO asserted;
specification #47A must be met by DSACKO or OSACKI.
4. This specification applies to the first (DSACKO or OSACKlI DSACKx Signal asserted. In the absence of DSACKx. BERR is an
asynchronous input using the asynchronous input setup time (#47A).
5. CBEN may stay asserted on consecutive write eyeles.
6. The minimum values must be met to guarantee proper operation. If this maximum value is exceeded. BG may be reasserted.
7 .This specification indicates the minimum high time for ECS and OCS in the event of an internal cache hit followed immediately
by another cache hit, a cache miss, or an operand cycle.

8. This specification guarantees operation with the MC68881/MC68882. which specifies a minimum time for iSS negated to

asserted (specification #13A in the MC688871MC68882 User's Manuan. Without this specification. incorrect interpretation of
specifications #9A and #15 would indicate that the MC68030 does not meet the MC68881/MC68882 requirements.

292064-19
Reprinted with permiSSion of Motorola Inc.

5-253

inter

Ap·329

NOTES (Conlinued)
9. This specificalion allows a system designer 10 guaranlee dala hold times on Ihe oulpul side of dala buffers Ihal have oulpul
enable signals generaled wilh OBEN. The liming on OBEN precludes ils use for sYl)chronous READ cycles wilh no wail slates.
10. These specifications allow system designers to guarantee that an alternate bus master has stopped'driving the bus when the
MC68030 regains control of the bus after an arbitration sequence.
II. OS will not be asserted for synchronous write cycles with no wait states.
.
12. These hold times are specified with respect to strobes (asynchronous) and with respect to the clock (synchronous). The designer

is free to use either time.

13. Synchronous inputs must meet specifications #60 and #61 with stable logic levels for all rising edges of the clock while AS is
asserted. These values are specified relative to the high level of the rising clock edge. The values originally published were
specified relative to the low level of the rising clock edge.
14. This specification allows ~ste~esigners to qualify the til signal of an MC6888I/MC88882 with AS (allowing 7·ns for a gate
delay) and still meet the CS to OS set~p time requirement (spec 88) of the MC68881/MC68882.

292064-20

Reprinted with permission of Motorola Inc.

5-254

intJ

AP-329

These waveforms should only be referenced in regard to the edge-ta-edge measurement of the timing specifications. They are not
intended 8S a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams
for device operation.
SO

ClK

AD-AJ1, feD·Fe2
SIlO-SIll

AMf

itS

iiCS

os
A/W

iiilii
DSiCiii

DSTcii

DO Oll

Hilf
All
ASYIOCH11ONOUS
INPUTS

fiN

CIII(i!

Figure 11. Asynchronous Read Cycle Timing Diagram

292064-21
Reprinted with permission of Motorola Inc.

5-255

intJ

AP-329

These waveforms should onlv be referenced in regard to the edge-to-edge maasuremant of tho timing specifications. They are nOl
intended as a functional description of the input and output signals. Refer to other functional descriptions and thair related diagrams
for device operation.

AD-A31. fCO-fC2
SllO-SIZl

R/W

00·031

Figure 12. Asynchronous Write Cycle Timing Diagram

292064-22
Reprinted wHh permission of Motorola Inc.

5-256

AP-329
These waveforms should only be referenced in regard to the edge~to-edge measurement of the timing spe'cifications. They are not
intended as a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams
for device operation.
.

cue
AD·All. FCIl-FC2 ---I-ud---+--I--~oL,,------..,...
SllD·SIZl

R/W

00·031

Figure 14. Synchronous Write Cycle Timing Diagram

292064-24
Reprinted

w~h

permission of Motorola Inc.

5-258

AP-329

Delay Line Information
Delay lines with tolerances of
from:

+ 1 ns

can be obtained

ECC
3580 Sacramento Drive
San Luis Obispo, CA 93403
This company can also manufacture at customer's reqUest i& delay liuli3 with iii.;·~rt~d vutput ut virtuuHy th~
same cost as their regular devices.
Other delay line manufacturers are:
Dallas Semiconductor
4350 Beltwood Parkway South
Dallas, Texas 75244
EG&G Reticon Corp.
345 Portero Ave.
Sunnyvale, CA 94086

5-259

APPLICATION
NOTE

November 1990 .

Am29000* /27960CX
Burst EPROM 'Interface

INTEL
PROGRAMMABLE MEMORY OPERATION

*Am29000 is a trademark of Advanged Micro Devices, Inc.

Order Number: 292081-001
5-260

29000/27960CX BURST EPROM INTERFACE
CONTENTS

PAGE

1.0 SIGNAL DEFINITIONS . ............ 5-262
1.1 29000 Signals ................... 5-262
1.2 279960CX Burst EPROM Control
Signals ........................... 5-262
2.0 INTERFACE REQUIREMENTS . .... 5-263

CONTENTS

PAGE

3.0 CIRCUIT DESCRIPTION ........... 5-263
4.0 29000/27960CX INTERFACE . ..... 5-263
5.0 LOGIC DETAILS ................... 5-265
APPENDIX A .......................... 5-273
27960CX Datasheet ......... : ....... 5-274
Am29000 Datasheet ................ 5-278

5-261

intJ

Ap·346

This application note describes the design of a circuit to
interface the 27960CX burst EPROM to AMD's
Am29OO0· mi9roprocessor. The 29000 microprocessor
is capable qf operating in a burst mode, accessing a
maximum of 256 long words (long word = 32 bits)
. during a burst access. The burst EPROM supports a
maximum of 4 words during a burst access. To accommodate the longer burst cycle of the 29k, the interface
has an 8-bit external counter which supplies the lower
eight addresses to the EPROMs.
'

1.1.3 BINV...,...BUS INVALID (OUTPUT)

This signal indicates that the Address Bus and related
control signals are invalid. It defines an idle cycle for
the channel.
1.1.4 IRDY-INSTRUCTION READY (INPUT)

This signal indicates that a valid instruction is on the
instruction bus.

A 1-0-0-0 burst operation (one wait-state for the first
word access and zero wait-state for the remaining three
accesses) is possible at 20 MHz using the 27960CI-20
burst EPROMs. Effectively this results in a4 words/5
clock cycles performance for this interface. A 2-0-0-0
burst operation (non-buffered system) is possible at
25 MHz/33 MHz using the 27960C2-25/33 bUrst
EPROMs. This memory interface monitors control signals from the microprocessor and provides handshake
logic for the microprocessor, and generates ADS and
BLAST signals for the burst EPROMs.

1.1.5 IREQT-INSTRUCTION REQUEST TYPE
.(OUTPUT)

This signal specifies the address space of an instruction
request, when IREQ is active:
IREOT
0-- Instruction/Data Memory Access

l-.Jnstruction Read Only Memory Access

The interface can be implemented with a 16R6D PAL,
an 8-bit counter, a 9-bit latch, a .o-type flip-flop, an
address decoder and some discrete AND and OR gates.
The discrete gates may be integrated into the control
logic PAL or another system PAL. Address and data
buffers may be required if the capacitive loading is
large.

This input is active whenever a burst-mode instruction
has been established·. It may be active even though no
instructions are currently being accessed, for example
in a suspended burst access.

SIGNAL DEFINITIONSIINTERFACE
REQUIREMENTS

1.2 27960CX Burst EPROM Control
Signals

1.0 SIGNAL DEFINITIONS

1.2.1 ADS-ADDRESS STROBE (INPUT)

1.1 29000 Signals

Indicates the start of a new bus access. It is active low
in the first clock cycle of a bus access,

This section describes the 29000 signals which are relevant to this interface.

1.2.2 BLAST-BURST LAST (INPUT)

1.1.1 IREQ---;INSTRUCTION REQUEST (OUTPUT),

Terminates a concurrent burst data cycle. Must be asserted by the fourth data word.

1.1.6 IBACK-INSTRUCTION BURST
ACKNOWLEDGE (INPUT)

This signal requests an instruction access. When it is
active, the address bus has a valid address for the access.
1.1.2 IBREQ-INSTRUCTION BURST REQUEST
(OUTPUT)

This signal is used to establish a burst-mode instruction
access and to request instruction transfers during a
burst-mode instruction access.

1.2.3 CS-CHIP SELECT (INPUT)

Master device enable. When asserted, data can be written to and read from the device. In read mode, CS
enables the state machine and the I/O' circuitry. A
memory access begins on the first rising edge of CLK
after ADS and CS are asserted. CS can be de-asserted
after the number of wait-states, N, has expired, but the
EPROM will continue to burst out data for the current
cycle. If CS is de-asserted during the wait-state period,
the burst access will be aborted .

• Am29000 is a trademark of Advanced Micro Devices, Inc.

5-262

intJ

Ap·346

2.0 INTERFACE REQUIREMENTS

3.2 Burst Suspension

The interface is designed to work in the burst
mode,with the instruction burst acknowledge signal,
IBACK, as the handshake for the microprocessor indicating that the EPROM memory is capable of supporting a burst access. The interface logic will monitor control signals from the microprocessor, i.e., IREQ,
IBREQ, BINV, and generate IRDY and IBACK for
the microprocessor and ADS and BLAST signals for
the 27960 EPROM. Since the burst EPROM is capable
of bursting a maximum of four words, the interface will
suspend the burst after the fourth word by de-asserting
IRDY and resume the burst by re-asserting IRDY one
clock cycle later. The interface will preempt the burst
access in response to the burst access being suspended
by the microprocessor.

The burst-mode instruction access may be suspended in
certain situations. The processor suspends a burst-access by de-asserting IBREQ. The burst-mode access remains suspended unless the processor requests a new
instruction access (in which case IREQ is asserted), or
unless the instruction memory preempts the burstmode access. A suspended burst-mode instruction becomes active whenever the processor activates the
burst-mode access by assertmg l1:lKbI..!.

3.3 Burst Preemption

3.0 CIRCUIT DESCRIPTION

A burst access is preempted by de-asserting IBACK. If
IBREQ was active in the cycle before IBACK was deasserted, one last word of information must be transferred before the burst access is ended. The last word
can be transferred in the same cycle that the Burst Acknowledge is de-asserted or some later cycle, but until
it is transferred the burst access is not complete and no
new access of the memory may begin.

This section describes the burst-mode operation of the
29000 microprocessor followed by a description of the
interface circuit as shown in Figure 1.

4.0 29000/27960CX INTERFACE
(FIGURE 1)

3.1 Burst-Mode Access

4.1 Burst EPROMS .

The burst mode-access allows mUltiple instructions or
data words at sequential addresses to be accessed with a
single address transfer. A burst access is requested via
the Instruction Burst Request (IBREQ). The initial address of this burs.t access is indicated by assertion of
Instruction Request (IREQ) signal. The memory system may assert Instruction Burst Acknowledge
(IBACK) to indicate that it supports burst-mode accesses. If IBACK is asserted while the initial address
appears on the address bus, the burst-mode access is
established. In the following cycle, the 29k will de-assert the IREQ signal and remove the initial address of
the burst access, but will continue to assert IBREQ. If
the burst-mode is never established, the default behavior is to have the processor transmit an address every
access. After the burst-mode access is established,
IBREQ is used during subsequent accesses to indicate
that the processor requires at least one more access. If
IBREQ is active at the end of a cycle in which an access
is successfully completed (IRDY is active), the processor requires another access.

The memory block consists of 27960CX, 128k x 8-bit
burst EPROMs. A minimum of four EPROMS are required for a 32-bit system. The 27960CX supports
burst-mode operation, and is capable of accessing four
long words (long word = 32 bits) during a burst cycle.
Each burst cycle begins with a valid address be~
latched in the first clock cycle, when both ADS and CS
are asserted. After a set number of wait-states (lor 2),
data is output one word at a time on each subsequent
clock cycle. A burst access is terminated with the
BLAST signal. A 1-0-0-0 burst operation (1 wait-state
for the first word access and zero wait-state for subsequent accesses) is possible at 20 MHz using 27960Cl20 burst EPROMs. A 2-0-0-0 burst operation (nonbuffered system) is possible at 25 MHz/33 MHz using
the 27960C2-25/33 burst EPROMs.

Figure 1 shows the block diagram of the 29000/
27960CX Burst EPROM interface.

4.2 Address/Instruction Bus Buffers
The address and instruction buses may be buffered with
high speed buffers. If the memory block were made up
of multiple banks of memory devices, the instruction
bus might need buffering to isolate the heavier capacitive load of multiple memory banks from the rest of the
system. Also address buffers may be needed to drive
address inputs of multiple banks.

5-263

intJ

AP-346

I
l!l

I§

lU
~

N-

I
~ aD

I§ ~ ~. E~

l!l
I~

N-

~ ..r 1:111

iU I
D

..rI
~

~~
i!!

Ie-

NOTES:
The discrete gates in this design could be integrated in an another system PAL or a bigger PAL could be used.
Address and data boffers are required if capacitive loading is large.

Figure 1. 29000/27960CX Interface

5-264

Ap·346

4.3 Address Latch and Counter

A registered PAL output will be represented by : =

To support burst accesses, the lower eight address bits
to the burst EPROMs come from a loadable counter.
The 8-bit counter is built from 74FCT191 4-bit binary
counters. These high speed counters are needed if the
access is to begin in the first clock cycle when IREQ is
asserted: If the initial access begins in the second clock
cycle, i.e., ADS is generated in the next clock cycle
following assertion of IREQ, a slower 8-bit counter
may be used. The upper eight bits need not come from
a counter, since the 29k will always output a new address when a 256-word boundary is crossed. The upper
8 bits of address are simply latched.

A combinatorial PAL output will be represented by =

5.1 Signal Descriptions
A 16R6D PAL is used to general IRDY, ADS,
BLAST, and !BACK. A modulo 5 counter is implemented in the PAL which is used to generate timings
to

...................

lUI

.. T"A.
.
8. Asynchronous Inputs include: WAm. iNTFi,-iNiR,. "i"RAP.-TRAP,. and CNTL,-CNTL".
9. RESET is an asynchronous input on assertion/deassertion. As an option to the user. ~ deassertion can be used to
force the state of the internal divide-by-two flip-flop to synchronize the phase of SYSCLK (H internally generated) relative to RESETIINCLK.
.
.
10. WARN has a minimum pulse width requirement upon deassertion.
11. To guarantee Storelload with one-cycle memories. 0,,-0. must be asserted relative to SYSCLK lalling edgelrom an
external drive source.
12. Refer to Capacitive Output Delay table when capacitive loads exceed 80 pF.
13. When used as an input. SYSCLK presents a 90-pF max. load to the external driver. When SYSCLK is used as an output. timing is specified with an external load capacitance of s 200 pF.
, 4. Three-State Output Inactive Test Load. Three-Slale Sy'nchronous Output Invalid Delay is measured as the time to a
±500 mV change from prior output level.
'
, 5. When a three-state output makes a synchronous transition Irom a valid logic level to a high-impedance state. data is
guaranteed to be held valid for an amounl of time equal to the lesser of the minimum Three-State Synchronous Output
Invalid Delay and the minimum Synchronous OiJtput Valid Delay.
Conditions:
a. All inputs/outputs are TTL compatible for V,H• VIL' VOH ' and V04. unless otherwise noted.
b. All output timing specHications are lor 80 pF of loading. .
c. All setup. hold. and delay times are measured relative to SYSCLK or INCLK ,,\nless otherwise noted.
d. All input Low levels must be driven to 0.45 V and all input High levels must be driven to 2.4 V except SYS~LK.
292081-20

Am29000TM

PRELIMINARY
Reprinted with permission of Advanced Micro Devices, Inc.

5-282

inter

AP-346

SWITCHING WAVEFORMS

~r~

•

0-+1 rVee-I.O V
I.SV
O.BV

• +---@-+

SYSClK
Synchronous
Outputs

I.SV

1.5 V

I.SV

1.5 V

-.~
~

Synchronous Inputs
1.5 V

Relative to SYSCLK
292081-21

Am29000TM

PRELIMINARY
Reprinted with permission of Advanced Micro Devices, Inc.

5-283

AP-346

SWITCHING WAVEFORMS

INCLK

J,-,sv-----{~f---~.~
1~4~--------~G9~--------~.~1
Asynchronous
Inputs

1.5V

1.5 V

INCLK and Asynchronous Inputs
292081-22

Am29000TM

PRELIMINARY
Reprinted with permission of Advanced Micro Devices, Inc.

5-284·

inter

~OO~Il.O~OOOb:\OOW

Ap·346

SWITCHING WAVEFORMS

}

SYSCLK Definition

1.5V

SYSCLK

INCLK

O.BV

2.0V
1.5V

I+-----{ 12}----+I

INCLK to SYSCLK Delay
292081-23

Am29000TM

PRELIMINARY
Reprinted with permission of Advanced Micro Devices, Inc.

5-285

inter

Ap·346

Capacitive Output Delays·
For loads greater than 80 pF
This table describes the additional output delays for capacitive loads greater than 80 pF. Values in the Maximum
Additional Delay column should be added to the value listed in the Switching Characteristics table. For loads less
than or equal to 80 pF, refer to the delays listed in the Switching Characteristics table.
\

No.
6

Parameter Description
Synchronous SYSCLK Output Valid Delay

Synchronous SYSCLK Output Valid Delay for 0 3 ,-0.

Synchronous SYSCLK Output Valid Delay

BINV Synchronous Output Valid Delay from SYSCLK

Total
External
Capacitance
100pF
150 pF
200pF
250pF
300 pF
100 pF
150 pF
200pF
250 pF
300pF
100 pF
150 pF
200 pF
250 pF
300 pF
100 pF
150 pF
200 pF
250pF
300 pF

Maximum
Additional
Delay
+1 ns
+2 ns
+4ns
+6 ns
+8 ns
+1 ns
+6ns
+10ns
+15 ns
+19 ns
+1 ns
+2 ns
+4ns
+6 ns
+8 ns
+1 ns
+3ns
+4ns
+6 ns
+7ns

SWITCHING TEST CIRCUIT
VL

IOL

= 3:2 rnA

.i
-

v_" ' "

I
CL .

Am29000
Pin Under Test

I"" - 400l1A
090758-00'11.

ICOO1030
V.
"

CL is guaranteed to 80 pF. For capacitive loading greater
than 80 pF, refer to the Capacitive Output Delay table.
292081-24

Am29000TM

PRELIMINARY
Reprinted with permission of Advanced Micro Devices, Inc.

5-286

RELIABILITY
REPORT

RR-35

November 1990

EPROM RELIABILITY
DATA SUMMARY

Order Number: 210473-007
5-287

RR-35

INTEL EPROM
RELIABILITY DATA
SUMMARY

CONTENTS

PAGE

The Importance of Reliability ......... 5-289
EPROM Reliability Data Summary .... 5-289
EPROM Reliability Testing ............ 5-289
CERDIP:
D2732A .............................
D2764A .............................
D27128A ............................
D27256 .. : ...........................
D27C256 ............................
D87C257 ............................

5-294
5-296
5-298
5-300
5-302
5-304

PLASTIC:
P2764A ..............................
P27128A ............................
P27256 ..............................
PIN27C256 ..........................

5-310
5-312
5-314
5-316

Appendix A. Failure Rate
Calculations for 60%
Upper Confidence Level .............. 5-319
Appendix B. EPROM Bit Maps
and Die Photos ....................... 5-325

5-288

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RR-35

THE IMPORTANCE OF RELIABILITY
Reliability of the non-volatile memories in your end
product is critical to your total system reliability. The
use ofIntel EPROMs can make a difference. Reliability
is not just tested, but designed into each component
Intel manufactures.
QUALITY

RELIABILITY

A quality component is one that meets your specification when received and tested. A reliable component
continues to meet your specification even years after
you have shipped your product. While Intel is a quality
leader, we also adhere to stringent reliability standards
which we have established for ourselves.
Consider Quality v~. Reliability

The true cost of any component involves more than just
the purchase price. The true component cost encompasses the initial purchase price, cost of rework during
system production, and the cost of field repairs due to
component failures. "Rework" costs during system
production are incurred prior to shipment of your end
product, and are a function of the quality of the component you purchase.
Repair costs incurred in the field after end product
shipments, are a function of the reliability of the components. In addition to the increasing real cost of a
system field service call, there is the intangible cost of a
poor reliability reputation to the end user of your product. These costs depend upon the reliability of the components you purchase. Thus, reliability may impact
costs during the system lifetime more than the initial
quality of the components!
MONITOR PROGRAM

Reliability is designed into each component Intel manufactures. From the moment the design is put to paper,
stringent reliability standards must be met at each step
for a product to bear the Intel name.
Designing-in reliability, however, is only the beginning.
Ongoing tests must be conducted to ensure that the
original reliability specifications remain as valid in volume production as they were when the device was first
qualified.
Intel's Reliability Monitor Program, devised to measure and control device reliability in production, is a
proven tool that Intel has used for seven years and is
now available to its customers. The Monitor Program
subjects all of Intel's technologies to a 48 hour dynamic
bum-in at 125°C (with a portion of these devices con-

tinued for a 1000 hour lifetest) and provides answers
about device reliability that are not generally available
from limited testing programs. But it's much more than
bum-in and device testing. When test rejects are encountered, failure analysis is performed on each failed
part. Isolating the fault and determining the failure
mechanism is a critical part of the Monitor Program. It
is the most comprehensive reliability program anywhere.
The paramount objective is to cieiiver reiiaoie, quaiiry
devices. Actions that Intel takes to meet this objective
may include a process or design change, or added reliability screen. Each decision is made with our customers in mind so that they ·receive the parts-and the
performance-that they ordered by specifying Intel.
Reliability qualification assures that all new production
meets Intel's reliability standards. The Reliability Monitor Program ensures that these high standards are
continually maintained, day in, day out, over the duration of a device's life. This reliability improves the lifetime reputation of your product, reducing the required
number of field service calls.
EPROM RELIABILITY DATA SUMMARY

Intel routinely publishes this "EPROM Reliability
Data Summary", a continuing update of reliability information covering Intel's entire EPROM product line.
This document includes a discussion on EPROM reliability testing methodology and the most current failure rate calculations, failure analyses and lifetest results.
Intel's commitment to the reliability of our products is
clearly reflected in the information we make available
. to customers. We beli,eve that supplying detailed reliability information to our customers is part of the total
solution Intel offers, and is an important part of Intel's
leadership in microelectronics technology.

EPROM RELIABILITY TESTING
Intel EPROMs undergo comprehensive testing to insure electrical reliability. This testing is done at qualification and/or during ongoing monitor checks. Where
testing differs for plastic packaged production
EPROMs, it is so noted.
Intel continually reviews its testing procedures and
makes improvements to its methodology whenever
overall reliability can be enhanced. Our goal is to be the
industry leader in delivering reliable parts and no compromises are accepted.
Information on Intel's reliability testing procedures
follows.

5-289

inter

RR-35

calculated by dividing the number of failures by the
equivalent device hours and is expressed as a %/1000
hours. To arrive at a confidence level associated failure
rate, the failure rate is adjusted by a factor related to
the number of device hours using a chi-square distribution. A conservative estimate of the failure rate is obtained by including zero failures at 0.3 eV. Devices submitted to stresses other than Iifetest received a 168 hour
Iifetest prior to stressing.

High Temperature Dynamic Lifetest-This test is used
to accelerate failure mechanisms by operating the devices at an elevated temperature of 125°C. During the
test the memory is sequentially addressed and the outputs are exercised, but not monitored or loaded. A
checkerboard data pattern is used to simulate random
patterns expected during actual use. Results of Iifetesting have· been summarized along with the failure analysis.

'The activation energies for various failure mechanisms are listed in
Table 1. For an explanation of this plot, see Appendix A.

In order to best determine long-term failure rate, all
devices used for Iifetesting are first subjected to standard INTEL testing. The 48 hour burn-in results are an
indication of infant mortality. These results are not included in the failure rate calculation. (See Figure 1 for
typical burn-in bias and timing diagrams.)

,
I

10'

.e 193

10'

= DE = PGM =

Vpp

S.2SV, R

0.3 eV

./'

= GND, C5E = GND

// /

Vcc
Vss

1
Z

O.6eV/

VCC

1.0aV

10'

,.48

VCC

1 kn,

10'

1//
10·

j:/

250

200

175 150

125
100
75
TEMPERATURE 'C

210473-2

Ax
210473-1

Figure 2. Arrhenius Plot

NOTE:
Alternate Configuration is the same as Figure 3.
Binary Sequence From Ao to Ax
00-07 may be N/C

Table 1. Failure Mechanism Activation
Energies Relevant to EPROMs
Failure Mechanism

Figure 1. 2764A Burn-In Bias
and Timing Diagrams

Failure Rate Calculations-Failure rate calculations
are given for each relevant activation energy. Failure
rate calculations are made using the appropriate
energy(I,2,3,4) and the Arrhenius Plot as shown in Figure 2*. The total equivalent device hours at a given
temperature can be determined. The failure rate is then

5-290

Each

Oxide

0.3

SBCL/SBCG/MBCLlMBCG

0.6

Contamination

1.0

. . Speed Degradation
Intrinsic Charge Loss

0.3-1.0
1.4

RR-35

Failure Definitions

to further validate protection occurring during mechanical handling.

Oxide-An Oxide Failure Related Fault
SBCL-Single Bit Charge Loss
SBCG-Single Bit Charge Gain
MBCL-Multiple Bit Charge Loss
MBCG-Multiple Bit Charge Gain
Contamination-Ionic Contamination Failure
Speed Degradation-Device Speed Degraded Over Test

A typical Iifetest bias and timing diagram is shown in
Figure 3.
V••

High Temperature 6.SV Dynamic Lifetest-This test is

A'2

used to accelerate oxide breakdown failures. The test
setup is identical to the one used for the dynamic life
test except Vee and Vpp are at 6.5V. The acceleration
factor due to this test can be found in Figure 4. This
data plus the standard dynamic Iifetest data are used to
calculate the 0.3 eV failure rate.

A,
As
As

A.
A3
A2

High Temperature Storage-This test is used to accelerate charge loss from the floating gate. The test is performed by subjecting devices containing a 98% +
programmed pattern to a 250"C bake (140" for plastic)
with no applied bias. In addition to data retention, this
test is used to detect mechanical reliability problems
(e.g., bond integrity) and process instability. This test is
sometimes referred to as Data Retention Bake Test.
Temperature Cycle-This test consists of cycling the
temperature of the chamber housing the subject devices
from -65°C to + 150"C and back. Two hundred cycles
are performed with a complete cycle taking 20 minutes.
This test is to detect mechanical reliability problems
and microcracks.
ESD Testing-This test is performed -to validate the
products tolerance to Electro Static Discharge damage.
All products incorporate ESD protection networks on
appropriate pins. Two types of tests are performed.
First, all devices are tested using Mil STD 883 test
criteria. In addition, a charged device test is performed

A,
Ao

Vss

Vcc = Vpp = PGM = 5.25V
Vss = CE = OE = GND
All Outguts Floating
10,.S

Ao~
A 1-.J
I
r
AX

210473-3

Binary Sequence from Ao to Ax

Figure 3. 2764A Lifetest Bias
and Timing Diagram

Supply
Voltage
(Volts)

Oxide
Thickness
(A)

Operating
Stress
(MY/cm)

10%

20%

30%

50%

100%

HMOSE

700

0.714

3.2

3.2E+2

1.0E+5

HMOSIIE

400

1.25

7.5

422

2.4E+4

5.6E+8

CHMOSIIE

400

1.25

7.5

422

2.4E+4

5.6E+8

Type

Acceleration Factor at _ % Over Stress

ASSUMES:
I. No bias generators

2. Depletion loads
3. Failure rate calculations use the appropriate acceleration factor for stress voltage and maximum operating voltage (conservative).

Figure 4. Time-Dependent Oxide Failure Acceleration
'HMOS and CHMOS are patented processes of Intel Corporation.

5-291

infef

RR-35

REFERENCES
1. S. Rosenberg, D. Crook, B. Euzent, "16th Annual

Proceedings of the International Reliability Physics
Symposium," pp i9-2S, 1978.
2. J. Caywood, B. Euzent, B. Shiner, "Data Retention
in EPROMs," 1980 IEEE International Reliability
Physics Symposium.
. .
3. S. Rosenberg, B. Euzent, "HMOS Reliability" Reliability Report RR-18, INTEL Corporation, 1979.

4. N. Mielke, "New EPROM Data-Loss Mechanisms,"
1983. International Reliability Physics Symposium.
S. R.M. Alexander, "CalCulating Failure Rates From
Stress Data," April 1984 International Reliability
Physics Symposium.
NOTE:
The methodology for calculating failure rates is detailed in Appendix A.

5-292

RR-35

CERDIP Reliability Data Summary
The following data is an accumulation of recent qualification and monitor program results. Failure rate calculation methods listed in Appendix A were used to
arrive at the tabularized failure rates. Data for
CERDIP and plastic EPROMs is treated separately.
In reviewing the reliability data as presented, questions
may arise as to why lot sizes often decrease from one
test to another without a corresponding number of
identified failures. This is due to a variety of factors.
Many tests require smaller sample sizes and as a result
all parts from a previous test do not necessarily flow
through to a succeeding test.

In addition, various parts are pulled from a sample lot
when mechanical or handler problems cause failures to
occur. These "failures" are not a result of the specific
test just completed. They are removed from the sample
lot size and are not included in any failure rate calculation. It can also happen that a particular test is done
incorrectiy through human error or fauity test equipment and these suspected "invalid" failures are put
aside for retesting at a later date, decreasing the lot size
for a succeeding test. If these parts are found to be truly
defective, they are treated as failures and listed. If they
test out properly, they are removed from any calculation data base.

5-293

inter

RR-35
,

D2732A
The Intel 2732A (CERDIP) is a 32K ultraviolet erasable and Electrically Programmable Read Only Memory (EPROM).
Number of Bits:
32,768
Organization:
4Kx 8
PinOut:
24 pin, JEDEC Approved

Die Size:
Process: '

163 x 97 mil.
HMOS-E
Cell Size:
11.5 x 8.75 /LM
Programming Voltage: 21.0V
Technology
NMOS

Table 1: Reliability Data Summary
125°C Dynamic
Llfetest

6.5V Dynamic
Llfetest

Year

Burn-In
48Hrs
168 Hrs

500 Hrs

1K Hrs

48Hrs

168 Hrs

500 Hrs

1988

3/21982

5/21977

0/2112

0/2111

0/1056

0/1055

0/0

1989

0/10998

0/10997

0/192

0/672

0/575

Totals

3/32980

5/32974

0/2304

0/2303

0/1728

0/1727

0/575

1KHrs

Table 2: Additional Qualification Tests
250°C
Data Retention Bake

Year

1988

48 Hrs

168 Hrs

500 Hrs

4/2836

1/2830

1/2828

200 Temp
Cycles

0/858

1989

2/1419

1/1417

0/1031

01779

Totals

6/4255

2/4247

1/3859

0/1637

5-294

inter

RR·35

D2732A (Continued)
Table 3: Failure Rate Predictions

125°C Actual
Device Hours
_ ......... "

....... a

IU'"

0.01

Equivalent Hours

Ea
(eV)
..... ,..

U."

1.15 X 106

55°C

.... 1"'1 A

0.1.

0.3·VAF

70°C

0.0020

0.0032

0.0002

0.0006

0.0001

0.0004

Combined Failure Rate:
FITs:

0.0023
23

0.0042
42

IV'

6.55 X 107

5.87 x 106
1.99 X 106
1.15 X 106

0.6 B.1.
0.6 BAKE
0.6 HVELT

1.90
5.46
3.72

5.87 x 106
1.15 X 106

1.0 B.1.
1.0 HVELT

1.93
3.79

Fail Rate %/1K Hrs
(60% UCL)

55°C

~n7

..:I.u"1' A

#
Fail

2.16)( 107

4.23 X 107

Total 0.3 eV Failures =

x 108
x 109
x 107

3
9
0

7.94 X 107
2.16 X 109
1.56 X 107

Total 0.6 eV Failures =

x 109
x 108

4.51 X 108
8.84 X 107

1
0

Total 1.0 eV Failures =

48 Hour Burn-In Infant Mortality: 91 DPM

ThetaJa
·Vcc
Icc@55
Icc@70
Icc@ 125

'=
=
=
=
=

55° C/W
5.50V
69mA
72mA
80mA

Temp with Bja
T(55) = 347.92°K
T(70) = 363.79°K
T(125) = 421.25°K
T(250) = 523.15°K
K = 8.62 X 10- 5 eVrK

BI/ELT
Accel.
Factors:

0.3
0.6
1.0

250°C Bake 0.3
Accel.
0.6
Factors:
1.0

Thermal Accel. Factors
55°C
70°C
5.7
3.7
32.4
43.5
329.1
76.8

N/A

2737.2

1081.8

N/A

Voltage Accel. Factor (VAF)
for HVELT on this process is
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.

Failure Analysis:
A. 1-column charge loss
2-SBCG
B.2-SBCG
1-ionic contamination
1-oxide breakdown
1-line corrosion

0.6 eV
0.6 eV
0.6 eV
1.0 eV

0.3eV
0.6eV

0.6eV
0.6eV
0.6eV
0.6eV

C. 5-SBCL
1-SBCG
D. 2-SBCL
E. 1-SBCL

5-295

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RR-35

D2764A
The Intel 2764A (CERDIP) is a 64K ultraviolet erasable and Electrically Programmable Read Only Memory (EPROM).
Number of Bits:
65,536
Organization:
8K x 8
PinOut:
28 pin, JEDEC Approved

Die Size:
Process:
Cell Size:
Programming Voltage:
Technology:

98 x 117 mils
HMOS II-E
6x6/LM
12.5V
NMOS

Table 1: Reliability Data Summary

12SoC Dynamic Llfetest

Burn-In
48 Hrs

168 Hrs

1988

0/15993

2/15990

0/1536

1989

0/4923

1/4921

0/192

0/20916

3/20911

0/1728

Year

Totals

SOO Hrs

6.SV Dynamic Lifetest

1K Hrs

48Hrs

168 Hrs

SOOHrs

1KHrs

0/1536

0/768

0/192

0/384

0/768

1/768

0/0

0/383

0/285

0/1152

0/1151

1/1151

0/285

B
Table 2: Additional Qualification Tests

2S0°C

1988

200 Temp

Data Retention Bake

Year

Cycles

48Hrs

168 Hrs

SOOHrs

6/2063

1/2056

2/2045

0/623

1989

0/645

0/644

0/234

Totals

6/2708

1/2700

2/2689

0/857

5-296

RR-35

D2764A (Continued)
Table 3: Failure Rate Predictions
125°C Actual
Device Hours
....... _ , , ....... a
A IU'"

...1.~O

7.18 X 105

Equivalent Hours

Ea
(eV)

55°C
C.I'

Fail

70°C

., .. ..., , " .. ",7

0.3 B.L
0.3*VAF

IV'

A A

I."'t .... ;",

2.16 x 108

,,7

1.43 X 108

5.25 X 107
1.46 X 109
9.55 x 10S

2
9
0

Total 0.6 eV Failures =

3.95 x
1.34 X
7.18 x 105

0.6 B.1.
0.6 BAKE
0.6 HVELT

1.20 x 108
3.69 x 109

3.95 x 10S
7.18 X 105

1.0 B.1.
1.0 HVELT

1.16 x 109
2.11 x 108

2.17x107

55°C

70°C

0.0013

0.0020

0.0003

0.0008

0.0000

0.0016
16

0.0028
28

1
1

IV'

Total 0.3 eV Failures =
10s
10s

Fail Rate %/1K Hrs
(60% UCL)

2.95 X 108
5.36 X 107

0
0

Total 1.0 eV Failures =

Combined Failure Rate:
FITs:

48 Hour Burn-In Infant Mortality: 0 DPM

ThetaJa
Vcc
Icc @55
Icc@70
Icc@125

=
=
=
=
=

48°C/W

Temp with 0ja
T(55) = 340. WK
T(70) = 354.34°K
T(125) = 408.08°K
T(250) = 523.15°K

5.50V
48mA
45mA
40mA

K = 8.62 X 10- 5 eV/oK

BIIELT
Accel.
Factors:

0.3
0.6
1.0

250°C Bake 0.3
Accel.
0.6
Factors:
1.0

Thermal Accel. Factors
55°C
70°C
5.5
3.6
30.3
13.3
294.1
74.6

N/A

2737.2

1081.8

N/A

Voltage Accel. Factor (VAF)
for HVELT on this process is
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.

Failure Analysis:
A. l-oxide breakdown
l-MBCL
l-SBCL
B. l-oxide breakdown
c. 2-MBCL
3-SBCL
l-oxygen doner

0.3eV
O.SeV
0.6eV
0.3 eV
0.6 eV
0.6 eV
0.6 eV

D. l-MBCL
E. l-SBCL
l-MBCL

0.6eV
O.SeV
0.6eV

5-297

RR-35

D27.128A
The Intel 27128A (CERDIP) is a 128K ultraviolet
erasable and Electrically Programmable Read Only
Memory (EPROM). This part differs from the 27128 in
that it requires 12.5 Vpp vs. 21.0 Vpp and the process
technology is HMOS II-E vs. HMOS-E.
Number of Bits:
131,072
Organization:
16K x 8
PinOut:
28 pin, JEDEC Approved

Die Size:
Process:
Cell Size:
Programming Voltage:
Technology:

169 x 117 mils
HMOS II-E
6x6jJoM
12.5V
NMOS

Table 1· Reliability Data Summary

125·C Dynamic Lifetest

6.5V Dynamic Llfetest

Year

Burn-In
48Hrs

168 Hrs

500 Hrs

1K Hrs

48Hrs

168 Hrs

500Hrs

1K Hrs

1988

0/5953

0/5952

0/576

1/288

0/286

0/0

1989

010

0/0

010

0/0

010

0/0

Totals

0/5953

0/5952

0/576

1/288

0/286

010

Table 2: Additional Qualification Tests

250·C

200 Temp

Data Retention Bake

Y~ar

Cycles

48Hrs

168 Hrs

500Hrs

1988

1/774

01772

11771

0/234

1989

0/0

010

0/0

Totals

1/774

0/772

1/771

0/234

5-298

intJ

RR-35

D27128A (Continued)
Table 3: Failure Rate Predictions
125°C Actual
Device Hours

Equivalent Hours

Ea
(eV)

55°C

............ ... ,.,c,

"" ....... ,. ... "",c

0.1"+ A

1.43 X 105
1.19 x 106
3.86 105
1.43 X 105

0.6 B.1.
0.6 BAKE
0.6· HVELT

3.16X10 7
1.05 x 109
3.78 x 106

1.19 x 106
1.43 X 105

1.0 B.1.
1.0 HVELT

2.80
3.36

J\,

IU""

4.02

Fail

70°C

0.3 D.i.
0.3*VAF

I.I~

......... ,

.. "".Q

....10 A

IV'"

2.74 X 107

0
0

Total 0.3 eV Failures =

IV ....

x 107

1.46 X 107
4.17 X 108
1.75 X 106

0
2
1

Total 0.6 eV Failures =

x 108
x 107

7.78 X 107
9.32 X 106

0
0

Total 1.0 eV Failures =

Combined Failure Rate:
FITs:

Fail Rate %/1K Hrs
(60% UCL)
55°C

70°C

0.0020

0.0029

0.0004

0.0010

0.0000

0.0024
24

0.0039
39

48 Hour Burn-In Infant Mortality: 0 DPM
ThetaJa
Vcc
Icc@55
Icc@70
Icc@125

=
=
=
=

45°C/W
5.50V
80mA
75mA
.70mA

Temp with 0ja
T(55) = 346.90o K
T(70) = 360.72°K
T(125) = 414.54°K
T(250) = 523.15°K
K = 8.62 X 10-5 eVI"K

BIIELT .
Acce!.
. Factors:

0.3
0.6
1.0

250°C Bake 0.3
Acce!.
0.6
Factors:
1.0

Thermal Accel. Factors
55°C
70°C
5.1
3.5
26.4
12.3
65.1
234.7.

N/A

2737.2

1081.8

N/A

Voltage Acce!. Factor (VA F)
for HVELT on this process is
NOTE:
FIT = Failure Unit. 1 FIT

= 1 failure per 109 device hours.

Failure Analysis:
A. 1-SBCG
B. 1-SBCL
C. 1-multi bit charge loss

0.6 eV
0.6 eV
0.6 eV

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RR-35

027256
Intel 27256 (CERDIP) is a 256K ultraviolet erasable
and Electricaly Programmable Read Only Memory
(EPROM).
Number of Bits:
262,144
Organization:

32K x 8
28 pin, JEDEC Approved

PinOut:

Die Size:
Process:
Cell Size:
Programming Voltage:

180 x 193 mils
HMOS H-E
6x6p.M
12.5V

Technology:

NMOS

Table 1: Reliability Data Summary
Year

Burn-In
48Hrs

1988
1989

Totals

12S·C DynamiC L1fetest
168 Hrs

SOOHrs

1KHrs

0/13954

1/13909

0/1344

3/10715

4/10709

0/384

4/24669

5/24918

0/1728

6.SV Dynamic Lifetest
48Hrs

168 Hrs

SOO Hrs

1KHrs

1/1344

0/672

0/633

0/0

0/383

0/864

Q/864

0/863

0/671

0/1727

0/1536

0/1526

0/671

Table 2: Additional Qualification Tests
2S0·C
Data Retention Bake

Year

200
Temp Cycles

48Hrs

168 Hrs

SOOHrs

1988

7/1806

8/1799

8/1790

1989

2/1404

7/1402

5/1395

0/546

9/3210

15/3201

13/3185

011091

Totals

5·300

0/545 .

RR-35

027256 (Continued)
Table 3: Failure Rate Predictions
12S·C Actual
Device Hours

4.39 x 10e
1.10 X 106

Equivalent Hours

Ea
(eV)

5S·C
,.. ....... ' "

0.38.L
0.3*VAF

C..e.1

Fail

70·C

.. ,,7

IV'

1.'-'6f' A

...

,,7

0.6 B.1.
0.6 BAKE
0.6 HVELT

1.17 x 108
4.37 x 109
2.94 x 107

4;39 x 106
1.10 X 106

1.0 B.1.
1.0 HVELT

1.05 x 109
2.62 x 108

70·C

0.0009

0.0014

0.0009

0.0023

Total 0.3 eV Failures =
4.39 x 106
1.59 X 106
1.10 x 106

SS·C

IV'

2.11 X 108

3.10 x 108

Fall Rate %/1K Hrs
(60% UCL)

5.41 X 107
1.73 X 109
1.36 X 107

2
37
0

Total 0.6 eV Failures =

2.89 X 108
7.24 X 107

1
0

Total 1.0 eV Failures =

Combined Failure Rate:
FITs:

0.0002
0.0020
20

0.0006

0.0043
43

48 Hour Burn-In Infant Mortality: 162 DPM
ThetaJa
Vee
lee@55
lee@70
lee@125

=
=

44°C/W
5.50V
80mA
75mA
70mA

Temp with (Jja
T(55) = 346.48°K
T(70) = 360.33°K
T(125) = 414.17°K
T(250) = 523.15°K
K = 8.62 X 10- 5 eVI"K

BIIELT
Accel.
Factors:

0.3
0.6
1.0

250° Bake 0.3
Accel.
0.6
Factors: 1.0

Thermal Accel. Factors
55°C
70°C
5.2
3.5
26.7
12.3
238.4
65.8

N/A

2737.2

1081.8

N/A

Voltage Accel. Factor (VAF)
for HVELT on this process is
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.

Failure Analysis:
A.2-SBCL
1-ionic breakdown
l-oxide breakdown
B. 2-oxide breakdown
l-package crack
l-decoder charge loss
l-single row charge loss

0.6eV
1.0eV
0.3eV
0.3eV
1.0eV
0.6eV
0.6eV

6-SBCL
2-clustered bit charge loss
l-MBCL
D. 15-SBCL
E. 5-SBCL
5-clustered bit charge loss
3-MBCL

5-301

0.6 eV
0.6 eV
0.6 eV
0.6 eV
O.~ eV
0.6 eV
0.6 eV

RR-35

D27C256
The Intel 27C256 (CERDIP) is a 256K ultraviolet erasable and Electrically Programmable Read Only Memory (EPROM).
Number of Bits:
262,144
Organization:
Pin Out:

Die Size:
Process:
Cell Size:
Programming'Voltage:
Technology:

32K x 8
28 Pin JEDEC Approved

172 x 176 mils
CHMOS II-E
6x6J.1oM
12.5V
CMOS

Table 1: Reliability Data Summary
125°C DynamiC
Lifetest

6.5V DynamiC Lifetest

Year

Burn-In
48 Hrs

168 Hrs

500 Hrs

1K Hrs

48 Hrs

168 Hrs

500 Hrs

1K Hrs

1988

2/14976

1/14973

0/960

0/863

0/432

0/431

010

1989

0/10937

0/10931

0/1055

0/864

0/863

010

Totals

2/25913

1/25904

0/2015

0/1918

0/1296

0/1294

010

B
Table 2: Additional Qualification Tests
250°C
Data Retention Bake

Year

200
Temp Cycles

48 Hrs

168 Hrs

500 Hrs

1988

0/1934

2/1921

0/1401

1989

0/1418

2/1417

1/1414

0/702

Totals

0/3352

4/3338

1/2815

0/1092

5-302

0/390

inter

RR-35

D27C256 (Continued)
Table 3: Failure Rate Predictions
Equivalent Hours

125°C Actual
Device Hours

Ea
(eV)

'l.?'l x 106
6.47 X 105

0.38.!.

3.00

0.3*VAF

2.24

55°C

70°C

107

1.90'><' 107

108

1.41 X 108

1
0

7.59 X 107
1.62 X 109
1.04 X 106

2
3
0

4.82 X 108
6.59 X 107

0
0

Total 0.3 eV Failures
4.74 x 106
1.50 X 106
6.47 X 105

1.90 x 108
4.10 x 109
2.59 X 107

0.6 B.I.
0.6 BAKE
0.6 HVELT

Total 0.6 eV Failures
4.74 X 106
6.47 X 105

2.22 X 109
3.04 X 107

1.0 B.I.
1.0 HVELT

#
Fail

Total 1.0 eV Failures

Combined Failure Rate:
FITs:

Fail Rate O/O/1K Hrs
(600/0 UCL)
55°C

70°C

0.0008

0.0013

0.0001

0.0004

0.0000

0.0009
9

0.0017
17

48 Hour Burn-In Infant Mortality: 77 DPM

ThetaJa
Vee
lee@55
lee@70
lee@125

=
=
=
=
=

40°C/W
5.50V
"10mA
10mA
10mA
K

Temp with 9ja
T(55) = 330.35°K
T(70) = 345.35°K
T(125) = 400.35°K
'T(250) = 523.15°K

BIIELT
Accel.
Factors:

8.62 X 10- 5 eVrK

250° Bake 0.3
0.6
Accel.
Factors:
1.0

0.3
0.6
1.0

Thermal Aeeei. Factors
55°C
70°C
6.3
4.0
40.1
16.0
468.9
101.7

N/A

2737.2

1081.8

N/A

Voltage Aceel. Factor (VAF)
for HVELT on this process is
NOTE:

FIT

= Failure Unit. 1 FIT = 1 failure per 109 device hours.

"
Failure Analysis:
A. I-charge loss (defect)
I-charge gain (defect)
B. I-oxide breakdown
C. 2-charge loss (defect)
2-charge loss (intrinsic)
D. l·charge loss (defect)

0.6 eV
0.6 eV
0.3 eV
0.6 eV
1.0 eV
0.6 eV

5-303

RR-35

D87C257
The Intel 87C257 (CERDIP) is a 256K ultraviolet erasable and Electrically Programmable Read Only Memory (EPROM) which incorporates an internal address
latch.
Number orBits:
262,144
Organization:
32K x 8
PinOut:
28 Pin JEDEC Approved

Die Size:
Process:
Cell Size:
Program1Iling Voltage:
Technology:

182 x 175 mils
CHMOS II-E
6x6tJ.M
12.5V
CMOS

Table 1: Reliability Data Summary
12S·C Dynamic Llfetest

Year

Burn-In
48Hrs

1988

0/6965

1989

0/2951

Totals

0/9916

0/9912

DID

168 Hrs

6.SV Dynamic Llfetest

SOO Hrs

1K Hrs

0/6961

DID

0/0

DID

0/2951

0/0

OlD
OlD

0/0

OlD

0/0

48Hrs

168 Hrs

SOOHrs

1KHrs

OlD

0/0

OlD
OlD

Table 2: Additional Qualification Tests
2S0·C
Data Retention Bake

Year

1988

200 Temp

Cycles

48Hrs

168 Hrs

SOOHrs

2/903

1/901

0/0

1989

0/187

1/187

0/0.

0/0

Totals

2/1090

2/1088

DID

0/0

5-304

inter

RR-35

D87C257 (Continued)
Table 3: Failure Rate Predictions
125DC Actual
Device Hours

1.19 X 1C
0
A

Equivalent Hours

Ea
(eV)

55DC

0.3*VAF

10A
0

1.90 X 107
1.98 X 108
0

0
2
0

1.21 X 108
0

0
0

!!.76

Total 0.3 eV Failures
1.19 x 10S
1.83 X 105
0

0.6 B.1.
0.6 BAKE
0.6 HVELT

4.16
5.01

x 107
x 108
0

Total 0.6 eV Failures
1.19

x 10S
0

1.0 B.1.
1.0 HVELT

5.58

Fail

70DC

7.53 x 10n

0.3 8.!.

108
0

Total 1.0 eV Failures

Fail Rate O/O/1K Hrs
(600/0 UCL)
55DC

70DC

0.0122

0.0192

0.0006

0.0014

Combined Failure Rate:
FITs:

0.0000

0.0128
128

0.0206
206

48 Hour Burn-In Infant Mortality: 0 DPM

ThetaJa
Vcc
Icc@55
Icc@70
Icc@125

=
=
=
=
=

40 DC/W
5.50V
10mA
10mA
10mA

Temp with 6ja
T(55) = 330.35DK
T(70) = 345.35DK
T(125) = 400.35DK
T(250) = 523.15DK
K

= 8.62

X 10- 5 eV/DK

NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.

Failure Analysis:
A. 1-charge 1055 (defect)
1-charge 1055 (intrinsic)
B. 1-charge 1055 (defect)
1-charge 1055 (intrinsic)

O.S eV
1.0 eV
O.S eV
1.0 eV

5-305

BI/ELT
Accel.
Factors:

0.3
0.6
1.0

Thermal Accel. Factors
55DC
70DC
6.3
4.0
40.1
16.0
468.9
101.7

N/A
250DC Bake 0.3
2737.2
Accel.
0.6
1.0
NI A
Factors:
Voltage Accel. Factor (VAF)
for HVELT on this process is

N/A
1081.8

N/A
55

inter

RR-35

Plastic Reliability Data Summary
INTRODUCTION
The following information is written to provide OTP
(one time programmable) users with the description
and reliability summary of Intel's plastic production
EPROMs in both DIP and PLCC packages. It includes
brief test descriptions, a description of plastic packaging compounds and the reliability data obtained during
the qualification and subsequent product monitors of
the P2764A, P27128A, P27256 and P/N27C256 devices.

High Temperature Extended Lifetest (HTELT)-This
test is also performed at 125°C but uses a smaller sample size. The parts are kept in the full active mode for
the duration of the test with outputs driven. The test is
intended to evaluate the long-term reliability of the
product.

PLASTIC PACKAGE
CHARACTERISTICS

High Voltage 6.5V Extended Lifetest (HVELT)-This
test is used to accelerate oxide breakdown failures. The
test is set up identical to the one used for dynamic lifetest except for Vee and Vpp which are raised to 6.5V.
The voltage acceleration factor for this configuration
on Intel HMOS lIE product has been determined to be
55 and is applicable to the 0.3 eV failure mode components.

The EPROM plastic package is composed of flame retardant plastic/epoxy which meets the rating requirements of US94VO '/." minimum. The die attach incorporates a silver-filled adhesive die attach on a silver
spot plated leadframe. Bonding is accomplished
through gold thermal compression bonding and lead
finish is either tin plated or 60/40 solder dipped tin/
lead.

High Temperature Storage-This test is used to accelerate charge loss from the floating gate. The test is performed by subjecting devices containing a 98% + program pattern to a 140·C bake with no applied bias. In
addition to data retention, this test can also be used to
detect mechanical reliability problems such as bond integrity or process instabilities. The test is sometimes
referred to as a data retention bake test.

EPROM ELECTRICAL
CHARACTERISTICS
OTP EPROMs in plastic are tested to the same electrical/parametric levels as their counterparts in CERDIP.
The characteristics include input/output voltage levels,
speeds, leakage, and power requirement characteristics
over the full commercial temperature operating range
of O·C-70·C. Performance capabilities are identical to
that of CERDIP EPROMs with speeds to 200 ns currently available.

Programmability-Device programmability is routinely monitored through the process of programming the
devices for product monitors and qualifications. Programmability is treated as a distinct part of a product
qualification. All voltage combinations are qualified.
Program margin is measured and tested on 100% of
Intel EPROM products. The new Quick-Pulse Programming™ Algorithm has been extensively verified
and the data easily surpasses the 99.5% programmability criteria of Intel's qualification requirements. Qualification results are presented in the following table:

RELIABILITY/QUALITY STRESSES
High Temperature 125°C Dynamic Lifetest (HTDL)This test is used to accelerate failure mechanisms by
operating the devices at an elevated temperature of
125°C. During the test, the memory is sequentially addressed and outputs are exercised but not monitored or
loaded. A checkerboard data pattern is typically used
to simulate random patterns expected during actual
use. Results of Iifetesting have been summarized along
with failure analysis. In order to best determine longterm failure rates, all devices used for lifetesting are
SUbjected to a standard Intel screening. The 48-hour
burn-in results measure infant mortality and are not
included in the failure rate calculations.

Product

Quantity

# Fail

% Yield

P2764A
P27128A
P27256
N27C256

8269
10,399
19,040
2079

0
2
10
1

100%
99.98%
99.95%
99.95%

MOISTURE RESISTANCE
Two types of moisture resistance testing are performed
by Intel. The first is 85·C/85% relative humidity
stressing and the second is steam stressing consisting of
121·C, 2 atm.

5-307

RR-35

OPENC 1
GROUNDC 2
5.25VC 3
GROUND C 4

5:25V

Ground

28 POPEN

5.25V

27 pGROUND

Ground

P 5.25V

5.25V

25 :::J GROUND

Ground

5.25V

Ground

22 :::J 5.2SV

5.25V

21 :::J GROUND

Ground

20 :::J 5.25V

5.25V

19 :::J "vV'f GROUND

Ground

18 :::J "vV'f 5.25V

Ground

17 :::J "vV'f GROUND

5.25V

16 :::J "vV'f 5.2SV

Ground

15 :::J "vV'f GROUND

5.25V

Ground

5.25VC 9

S.2SV"vV'fr:. 13

r:.

Ground

GROUNDC 10

GROUND

A12

5.25V C 7

"vV'f r:.
"vV'f r:.

Open'

GROUNDC 8

5.25 v

Str~ss

Vpp

23 :::JGROUND

5.25V C 5
GROUNDC 6

GROUND

\.J

Pin Name

24 :::I5.2SV

210473-22

5.25V

A10

Ground

5.25V

A11

Ground

5.25V

Ground

A13

5.25V

A14

Ground

28
Open'
VCC
'NMOS has pins 1 and 28 open
CMOS has Vpp and Vee at S.2SV

Figure 1. Typical 85/85 Bias Diagram

5-308

RR-35

During the,8S'C/8S% relative humidity test, the devices are subjected to a high temperature, high humidity
environment. The object of the test is to accelerate failure mechanisms through an electrolytic process. This is
accomplished through a combination of moisture penetration of the plastic, voltage potentials and contamination which, if present, would combine with the moisture to act as an electrolyte. See Figure 1 for typical
85/85 Bias Diagram.
Steam stressing accelerates moisture penetration
through the plastic package material to the surface of
the die. The objective of this test is to accelerate failures
of the device as a result of moisture on the die surface.
Corrosion, as typically seen in plastic encapsulated devices, is a very minor contributor to the EPROM failure mechanisms. Due to the floating gate storage cell
composition, EPROMs have a distinctive failure mode
which requires special considerations and solutions.

HTDL

HTELT

48·Hr

168/500/1K Hrs
\.

<.05%

140'C Bake

481 168/500·Hrs

The floating gate itself is a highly phosphorous doped
structure on which electrons are stored, thus creating
the non-volatile memory cell. Passivation defects or
marginalities can allow moisture penetration to a single
EPROM cell causing oxide deterioration, thus showing
up as a charge loss failure. This becomes the predominant failure mode for EPROMs, opposed to corrosion
which historically has been the dominant plastic mode
offailure. Intel has developed a proprietary, multi-layer
passivation which has successfully solved this problem.

QUALITYIRELIABILITY STANDARDS
The table below contains Intel's current requirements
for qualification for plastic OTP EPROMs. The failure
rate criteria has been established based on a survey of
major customers world-wide. Intel consistently meets
or exceeds these requirements.

HVELT
168/500/1K Hrs
I

<200 FITs Combined Failure Rate

5-309

Steam
168·Hrs

85/85
1K Hrs

<2%

<0.5% cum

RR-35

P2764A

a~indowless pl~stic .package and is

The P2764A is functionally identical to the 2764A except that it is housed in
one-time programmable."

Table 1: Reliability Data Summary
12S·(: Dyriamic Lifetest

6.SV Dynamic Lifetest

Year

Burn-In
48Hrs

168 Hrs

SOO Hrs

1KHrs

48Hrs

168 Hrs

500Hrs

1K Hrs

1988

1/2668

1/2667

0/384

0/192

0/0'

1989

0/0

Totals

1/2668

112667

0/384

0/192

0/0

B
Table 2: Additional Qualification Tests
140·C
Data Retention Bake

48 Hrs

168 Hrs

SOO Hrs

1K Hrs

200
Temp
Cycles

1988

0/0

0/514

0/156

1989

0/0

Totals

0/0

0/514

0/156

0/192

0/396

Year

168 Hrs
Steam

0/192

8S·C/8S% RH
168 Hrs

500 Hrs

1KHrs

0/396

Table 3: Failure Rate Predictions
125·C Actual
Device Hours

Ea
(eV)

6.39 X 105
9.60 X 104

0.3 B.1.
0.3*VAF

6.39 x 105
5.14 X 105
9.60 X 104
6.39 X 105
9.60 X 104

0.6 B.1.
0.6 BAKE
0.6 HVELT
1.0 B.1.
1.0 HVELT

Equivalent Hours

Fail

S5·C

70·C

2.98 x 106
2.44 x 107

2.08 X 106
1.71 X 107

0
0

Total 0.3 eV Failures =

1.39 x 107
4.06 x 107
2.09 x 106

6.79 X 106
1.60 X 107
1.02 X 106

0
0
0

Total 0.6 eV Failures =

1.08 x 108
1.62 x 107

3.28 X 107
4.92 X 106

1
0

Total 1.0 eV Failures =

Combined Failure Rate:
FITs:

Fail Rate %/1K Hrs
(60% UCL)
5S·C

70·C '

0.0033

0.0048

0.0000

0.0016

0.0054

0.0049
49

0.0102
102

48 Hour Burn-In Infant Mortality: 375 DPM

5-310

RR-35

P2764A (Continued)
ThetaJa
, vee
lee@55
Icc@70
r.:. ..
'CC e' "'J
I

=
=
=
_
-

103°C/W
5.25V
48mA
45mA
An_A
.... U I I . n

Temp with 8ja
T(55) = 353.96°K
T(70) = 367.33°K
T(125) = 419.63°K
_ ' ... An\ _
'\I~VI

BI/ELT
Accel.
Factors:

0.3
0.6
1.0

Thermal Accel. Factors
55°C
70°C
4.7
3.3
21.7
10.6
169.1
51.3

A-t" -1.:01/

"T'V.'''''\'

K = 8.62 X 10- 5 eVrK

140° Bake 0.3
Accel.
0.6
Factors: 1.0

N/A

79.0

31.2

N/A

Voltage Accel. Factor (VAF)
for HVELT on this process is = 55
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.

Failure Analysis:
A. I-microcracks

0.6 eV

B. 1-ionic contamination

1.0 eV

5-311

inter

RR·35

P27128A
The P27128A is functionally identical to the 27128A except that it is housed in a windowless plastic package and is
one-time programmable.
Table 1: Reliability Data Summary
12S·C Dynamic Llfetest .

6.SV Dynamic Lifetest

Year

Burn-In
48Hrs

168 Hrs

500 Hrs

1KHrs

48Hrs

168 Hrs

500 Hrs

1K Hrs

1988

0/2673

0/384

0/192

0/191

0/192

0/0

1980

0/0

Totals

0/2673

0/384

0/192

0/191

0/192

0/0

Table 2: Additional Qualification Tests
140·C Data Retention Bake

8S·C/8S% RH

48Hrs

168 Hrs

500 Hrs

1KHrs

200 Temp
Cycles

1988

0/0

0/516

0/514

0/156

1989

0/0

Totals

0/0

0/516

0/514

0/156

0/312

0/384

0/373

1/369

Year

168 Hrs
Steam

168 Hrs

500 Hrs

1K Hrs

0/312

0/384

0/373

1/369

A
Table 3: Failure Rate Predictions
12S·C Actual
Device Hours

Ea
(eV)

6.40 X 105
9.60 X 104

0.38.1.
0.3·VAF

Equivalent Hours
SS·C

70·C

2.65 x 106
2.17 x 107

1.94 X 106
1.59 X 107

Total 0.3 eV Failures =
6.40 x 105
4.28 X 105
9.60 X 104

0.6 B.1.
0.6 BAKE
0.6 HVELT

1.10X107
3.38 x 107
1.65 x 106

5.89 X 106
1.34 X 107
8.83 X.105

Total 0.6 eV Failures =
6.40 X 105
9.60 X 104

1.0 B.1.
1.0 HVELT

7.30 x 107
1.09 x 107

2.59 X 107
3.88 X 106

Total 1.0 eV Failures =

Fall

Fall Rate %/1K Hrs
(60% UCL)
SS·C

70·C

0.0038

0.0051

0.0000

0.0038
38

0.0051
51

0
0
0
0
0
0
0
0
0
0

Combined Failure Rate:
FITs:

48 Hour Burn-In Infant Mortality: 0 DPM

RR-35

P27128A (Continued)
ThetaJa
Vee
lee@55
lee@70
Icc@125

=
=
=
=
=

95°C/W
5.25V
80 rnA
75 rnA
70mA
K

Temp with ilja
T(55) = 367.95°K
T(70) = 380.41°K
T(125) = 432.91°K
T(140) = 41::l.15°K

BI/ELT
Accel.
Factors:

140° Bake 0.3
Accel.
0.6
1.0
Factors:

8.62 X 10- 5 eVrK

0.3
0.6
1.0

Thermal Accel. Factors
55°C
70°C
4.1
3.0
17.1
9.2
114.1
40.4

N/A

79.0

31.2

N/A

Voltage AcceJ. Factor (VAF)
for HVELT on this process is
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.

Failure Analysis:
A. l-oxide breakdown

0.3 eV

5-313

= 55

RR-35

P27256
The P27256 is 'functionally identical to the 27256 except that it is housed in a windowless plastic package and is onetime programmable.

Table 1: Reliability Data Summary
Year

125·C DynamiC Llfetest

6.5V Dynamic Llfetest

Burn-In
48Hrs

168 Hrs

500Hrs

1KHrs

48Hrs

168 Hrs

500Hrs

1KHrs

1988

2/8706

1/8662

0/1248

0/624

0/591

0/0

1989

0/6684

1/6680

0/288

0/624

0/615

0/470

Totals

2/15390

2/15342

0/1536

0/1248

.0/1239

1/1206

0/470

Table 2: Additional Qualification Tests
140"C
Data Retention Bake .

Year
48Hrs

168 Hrs

200 Temp
Cycles

500 Hrs

1KHrs

85"C/85% RH

168 Hrs
Steam

168 Hrs

500Hrs

1KHrs

1988

0/0

2/1672

0/1669

0/468

2/1012

0/1264

0/1262

0/1243

1989

0/0

0/1031

4/624

11780

0/960

1/960

3/956

Totals

0/0

2/2703

0/2700

4/1092

3i1792

0/2224

1/2222

3/2199

Table 3: Failure Rate Predictions
125·C Actual
Device Hours
3.12 x 106
8.44 X 105

Ea
(eV)
0.3 B.I.
0.3·VAF

Equivalent Hours

Fall
55·C

70·C

1.32 x 107
1.95 x 108

9.59 X 106
1.42 X 108

0
0

Total 0.3 eV Failures
3.12 x 106
2.70 X 106
8.44 X 105

0.6 B.1.
0.6 BAKE
- 0.6 HVELT

5.51 x 107
1.77 x 108
1.51 x 107

2.95 X 107
7.01 X 107
7.98 X 106

2
2
1

1.32 X 108
3.57 X 107

0
0

Total 0.6 eV Failures
3.12 x 106
8.44 X 105

1.0 B.1.
1.0 HVELT

3.81 x 108
1.03 x 108

Total 1.0 eV Failures

Combined Failure Rate:
FITs:

Fall Rate %/1K Hrs
(60% UCL)
55"C

70"C

0.0004

0.0006

0.0025

0.0058

0.0000

0.0029
29

0.0064
64

48 Hour Burn-In Infant Mortality: 130 DPM

5-314

RR·35

P27256 (Continued)
ThetaJa =
Vcc =
Icc@55 =
Icc@70 =
1 __

r.;'\,-4"~

'vLi '\;;

1'-'tJ

90°C/W

5.25V
80 rnA
75 rnA
70mA

Temp with 8ja
T(55) = 365.85°K
T(70) = 378.44°K
T(125) = 431.0BoK
T/1An\ -

",-orv,

BI/ELT
Accel.
Factors:

0.3
0.6
1.0

Thermal Accel. Factors
55°C
70°C
4.2
3.1
17.9
9.5
122.0
42.3

Aill -t£:oV

""T'...,.ltJ.,

K = B.62 X 10- 5 eVrK

140° Bake 0.3
Accel.
0.6
Factors: 1.0

. N/A

31.2

N/A

Voltage Accel. Factor (VAF)
for HVELT on this process is = 55
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.

Failure Analysis:
A. l-ionic contamination
l-MBCL
B. 2cSBCL
C. l-SBCL
D. l-scratched die
l-MBCL
. E. 3-cracked die
l-microcracks

1.0eV
0.6eV
0.6eV
0.6eV
0.5eV
0.6eV
0.5eV
0.6eV

F. l-SBCL
l-passivation. hole
l-partial row charge gain
G. l-pad corrosion
H. l-ref. generator charge gain
l-ionic contamination
l-pad corrosion

5-315

0.6eV
1.0 eV
0.6 eV
0.5 eV
0.6 eV
1.0 eV
0.5 eV

N/A

79.0

RR-35

P/N27C256
The J>/N27C256 products are functionally identical to the 27C256 except that they are housed in a windowless
plastic DIP (P) or a windowless plastic PLCC (N) package and are one-time programmable.
Table 1: Reliability Data Summary
12SoC Dynamic L:lfetest

. 6.SV Dynamic Llfetest

Year

Burn-In
48Hrs

168 Hrs

SOOHrs

1K Hrs

48Hrs

168 Hrs

SOOHrs

1KHrs

1988

0/4615

0/4607

0/672

1/663

0/336

0/334

0/333

0/0

1989

0/7355

0/7345

0/480

0/478

0/525

0/523

0/512

0/0

Totals

0/11970

0/11952

0/1152

1/1141

0/861

0/857

0/845

0/0

A
Table 2: Additional Qualification Tests
140"C Data
Retention Bake

Year

200 Temp
Cycles

168 Hrs

Sieam

8S0C/8S% RH

48Hrs

168 Hrs

SOOHrs

1KHrs

168 Hrs

SOO Hrs

1KHrs

1988

0/0

0/883

1/883

0/312

·0/542

0/700

0/697

1989

0/0

0/1031

0/1029

0/468

2/854

0/898

0/893

0/789

Totals

0/0

0/1914

1/1912

01780

2/1396

0/1598

0/1590

0/148~

Table 3: Failure Rate Predictions
12S0C Actual
Device Hours

Ea
(eV)

Equivalent Hours

Fail
SsoC

70°C
. 9.38 X 106
9.11 X 107

2.39 x 106
4.25 X 105

0.3 B.1.
0.3*VAF

1.47 x 107
1.43 x 108

2.39 x 106
1.59 X 106
4.25 X 105

0.6 B.I.
0.6 BAKE
0.6 HVELT

9.09 x 107
1.26 x 108
1.62 x 107

2.39 X 1Q6
4.25 X 105

1.0 B.I.
1.0 HVELT

1.03 x 109
1.83 x 108

Total 0.3 eV Failures =
3.68 X 107
4.97 X 107
6.55 X 106

Total 0.6 fJV Failures =
2.28 X 108
4.06 X 107

Total 1.0 eV Failures =

Fall Rate %/1K Hrs
(60% UCL)
55"C

70°C

0.0006

0.0009

0.0000

0.0006
6

0.0009
9

0
0
0
0
0
0
0
0
0
0

Combined Failure Rate:
FITs:

48 Hour Burn-In Infant Mortality: 0 DPM

5-316

intJ

RR-35

PIN27C256 (Continued)
ThetaJa
Vee
lee@55
lee@70
Icc @125

=
=
=
=
=

88°C/W
5.25V
10mA
10mA
10mA
K

Temp with 8ja
T(55) = 332.62°K
T(70) = 347.62°K
T(125) = 402.62°K
T(140) = 413.15°K

BI/ELT
Accel.
Factors:

8.62 X 10- 5 eVrK

140° Bake 0.3
0.6
Accel.
Factors: 1.0

0.3
0.6
1.0

Thermal Accel. Factors
55°C
70°C
6.2
3.9
38.1
15.4
430.8
95.6
N/A
79.0
N/A

Voltage Accel. Factor (VAF)
for HVELT on this process is = 55

Failure Analysis:
A. 1 Au cratering
B. 1 Au cratering
c. 2 Ionic contamination

1.2 eV
1.2 eV
1.0 eV

5-317

N/A
31.2
N/A

inter

RR-35

APPENDIX A
Failure Rate Calculations for
600/0 Upper Confidence Level
Step 1. Collect bum-in and lifetest data for each lot after 48 hours of bum-in through lifetest for each lot.
Step 2. Determine the failure mechanism and assign an activation energy (EM for each failure, except those occurring during the first 48 hrs. (See Table 1 below.)
.
Table 1. Failure Mechanism Activation Energies
Relevant to EPROMs

Failure Mode

Activation Energy

Defective bit charge gainlloss
Oxide breakdown
Silicon defects
Contamination
Intrinsic charge loss

0.6eV
0.3eV
0.3eV
1.0-1.2 eV
1.4eV

Step 3. Calculate the total number of device hours accumulated beyond 48 hours of bum-in. (Note: 48 hour bum-in
results measure infant mortality and are not included in the failure rate calculation.)
Example: 125°C Bum-In/Lifetest for a 2 lot sample
# failures
total # devices

48 Hours

168 Hours

500 Hours

1KHours

2K Hours

Lot #1
Lot #2

0/1000
0/221

1/1000
0/201

0/999
1/201

0/998
1/100

0/994
0/99

Totals

0/1221

1/1201

1/1200

1/1098

0/1093

Device Hours
Total Device Hours

(Number of Devices in Stress Interval) (Number of Hours in Stress Interval)

1201 (168 hrs - 48 hrs) + 1200 (500 hrs - 168 hrs)

+ 1098 (1000 hrs - 500 hrs) + 1093 (2000 hrs - 1000 hrs)
=

1201 (120 hrs)

+ 1200 (332 hrs) + 1098 (500 hrs)

+ 1093 (1000 hrs)
=

2.185

106 Device Hours

5-319

RR-35

Step 4. Use EA tables to find the equivalent device hours at a desired temperature for each activation energy (failure

mechanism), or use the Arrhenius relation.
R = Aexp

K = 8.617 X 10- 5 eVI"K
A = proportionality constant
R = mean rate to failure
EA = activation energy
T = temperature in Kelvin

[-K~A]

(Boltzmann's constant)

,Where AI. = A2 = A for the same failure mechanism (i.e., sameEA>
Where RI and R2 are rates for a normal operating temp and an elevated temperature respectively.
R1 = R2 x exp [ (E:) (;2

-;1)]

However, since rate (R) has the units l/time, we can think in terms of time to one failure or MTBF.
Thus:
, 1
R1 = -where t1 = MTBF at some temperature T1
t1

and:
1
R2 = ~ where t2 = MTBF at some temperature T2

Thus the Arrhenius Relation becomes:

or:

We then define the Acceleration Factor

as:

For example: For EA = 0.6 eV, T2 = 398°K, TI = 328°K

Therefore, one hour at 125°C is equivalent to 41.7 hours at 55°C for a failure mechanism of activation energy EA =
0.6 eV. Then 41.7 is the thermal acceleration factor for time.

5-320

intJ

RR-35

NOTE:
The Arrhenius Plot (Figure 2 Page 2) is simply In (Acceleration Factor) vs. l/Temperature normalized for an
MTBF (tv of one hour at 250·C (T2)' This plot can also be used to determine the acceleration factor between two
temperatures (other than 250·C).
For example: For a 0.3 eV failure at 125·C, the acceleration factor is 8.1 relative to a 0.3 eV failure at 250·C. For a
0.3 eV failure at 25·C, the acceleration factor is 152 relative to 250·C. Therefore, the acceleration factor between
125·C and 25·C is:
.

"I: ~ !!12 = 152
8.1 =

• ••• •

1A 7
'_00

Step 5. Organize the burn-in/lifetest data by EA, Total Device Hours at the burn-in/lifetest temperature T2, Thermal Acceleration Factors for each failure mechanism (EA>, Number of Failures for each failure mechanism,
and the calculated equivalent device hours at the desired operating temperature T I.
NOTE:
The rise in junction temperature due to the thermal resistivity of the package (81A> must be added to the ambient
temperature to arrive at the actual burn-inllifetest temperature.
Ttest

= TJ + TAmbient = 6JA (IV @ TAmbienU + TAmbient

EA ('V)

Total
Device Hrs @ T2

Acceleration
Factors

# Fall

Equivalent
Hours@T1

0.3
0.6
1.0

T.D.H.
T.D.H.
T.D.H.

X
Y
Z

N1
N2
Ns

X (T.D.H.)
Y(T.D.H.)
Z (T.D.H.)

The failure rates for individual failure mechanisms and the total combined failure rate can be predicted using the
data table and the following formula:
%fail/1Khrs =
.

x2 2T
(n,a) (105)

Where ](.2 (n, a) is the value of the chi-squared distribution for n degrees of freedom and confidence level of a. The
degrees offreedom, n = [2 (# of failures) + 2] for this application. T is the total equivalent device hours at TI. The
total combined failure rate is just the sum of the individual failure rates for each failure mechanism.
For a 60% UCL, the above formula converts to the following:
I

# Failures

o
1
2
3

3 < # < 15

>15

% Fall/1K Hours (60% UCL)
0.915 x 105/T
2.02 X 105 /T
3.105 X 105/T
4.17 X 105 /T
[1.049 (#failures for a ~articuiar EA) + 1.0305] [ 10 5]

[0.2533 + ~(4 X # Failed) + 3]2 [ 5]
4T
10
.

5·321

inter

RR-35

Example I:
Assume for this example. that Icc active is 57 rnA at TAmbient = 125°C and ICC active is 60 rnA at
T Ambient = 55°C.
Also assume that

(JJA

= 35°C/W.

Then.
T2 = (3S'C/W) (S7 rnA) (SV)

12S'C,

SS'C

:::: 13S'C = 408'K
T1 = (3S'C/W) (60 rnA) (SV)
:::: 6S'C = 338'K

EA (eV)

Actual Device
Hours @ 125°C

Acceleration Factors
for 135°C to 65°C

Equivalent
Hours
at 55°C

# Fail

55°C
% Fail/
1KHrs

0.3
0.6
1.0

2.185 x 106
2.185x 106
2.185x106

5.85
34.18
359.93

1.278x107
7.468 x 107
7.864 x 108

0
2
1

0.0081
0.0042
0.0003

Total Combined Failure Rate =

0.0126
126 FITs

Example 2:
Assume that an additional lot of 800 HMOS· lIE devices is burned in using a 6.5V lifetest. Using Table 2 below. a
.
voltage acceleration factor of 55 results from a 20% overstress (5.5V to -6.5V).

Device Hours = 800 (48 hrs - 0 hrs)
= 3.997 x 105

48 Hours

168 Hours

500 Hours

0/800

1/800

0/799

800 (168 hrs --48 hrs)

799 (SOO hrs - 168 hrs)

Table 2. Time-Dependent Oxide Failure Accelerations
Type

Oxide
Operating
Supply
Voltage Thickness
Stress
(A)
(MV/cm)
(Volts)

Acceleration Factor at __ % Over Stress
10%

20%

30%

50%

100%

HMOSE

700

0.714

3.2

3.2E+2

1.0E+5

HMOSIIE

400

1.25

7:.5

422

2.4E+4

5.6E+8

CHMOsil E

400

1.25

7.5

422

2.4E+4

5.6E+8

ASSUMES:
1. No Bias Generators
2. Depletion Loads
3. Failure rate calculations use the appropriate acceleration factor for stress voltage and maximum operating voltage
(conservative).

5-322

inter

RR-35

Since this voltage accelerated stress is used to predict an oxide breakdown failure rate, the S.SV burn-in/lifetest SS·C
equivalent hours for EA = 0.3 eV are added to the 6.SV burn-in/lifetest SS·C equivalent hours as follows:
12S·C
Burn-ln/Lifetest

EA (eY)

Actual Device
Hours @ 12S·C

Acceleration Factors
for 13S·C to 6S·C

Equivalent
Hours
@SS·C

5.5V
6.5V

0.3
0.3

2.185 x 106
3.997 x 105

5.85
(5.85 x 55)

1.278x 107
1.286 x 108

Total Equivalent E.A.

= 0.3 eV Device Hours = 1.414 x 108

The following failure rate predictions include the total equivalent SS·C, EA = 0.3 eV device hours found above:

EA(eY)
0.3

0.3

+ 55(1)
0.6
1.0

Actual Device
Hours @ 125·C

Acceleration Factors
for 13S·C to 6S·C

2.185 x 106
3.997 x 105
2.185 x 106
2.185 x 106

5.85
(5.85 x 55)
34.18
359.93

Equivalent
Hours
@S5·C

1.414 x 108
7.468 x 107
7.864 x 108

# Fail

NOTES:

0.0015
0.0042
0.0003

1
2
1

Total Combined Failure Rate

S5·C
% Faill
1KHours

=
=

0.0060
60 FITs

(1) The notation 0.3 + 55 is used to show that 6.5V and 5.5V burn-in/lifetest equivalent hours have been combined.
(2) Additional information on calculating failure rates is contained in the April 2. 1984 International Reliability Physics Symposium editorial entitled "Calculating Failure Rates from Stress Data" by Robert M. Alexander.

"HMOS & CHMOS are patented processes of Intel Corporation.

5-323

intJ

RR-35

APPENDIX B
EPROM ·Bit Maps and Die Photos

5-325

inter

RR-35

10 II

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··
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!i!ilriiiiiiiiii!iiiiiii!l!iiiii ii!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

it:::::::::::::::::::::::::::::: it::::::::::::::::::::::::::::::

ifl:::l::::::!::::::;:::::;;;:l! 1!1:::::ll: ili::::::::l:l::::::i
IHIIIIJlIIII\lIIIIIIIIHII!(1I1

!III1I1HlIIIIIIIHIrIlIIII\l\ll

210473-5

2732A Bit Map (1 of 8 Outputs Shown)

5-326

inter

RR-35

210473-6

2732A Die Photograph

5-327

inter

RR·35

Column Selects
Yo Yl Y2 Y3 Y4 YS Y6 Y7 Y8 Yg Yl0 Yll Y12 Y13 Y14 YIS Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y2S Y26 Y27 Y28 Y29 Y30 Y31

A2 0 0
Al 0 0
AoO 0
Ala 0 0
All 0 1

0 0 0 0
0 0 0 0
0 0 1 1
1 1 0 0
1 0 o 1

0 0 0
0 0 1
1 1 0
1 1 0,
1 0 0

0 0

l' 1

1
1

1
1 ,0

0
0
0

0
0

0
0
0
0

0
0

1
1
1

1
1

0 0
0 1

1
1

1 1
1 1
1 ,0

1
1

Row Selects
Xo Xl
A7
As
A5
A4
Aa
A12
Ag
As

0 ,0
0 0
0 0
0 0
0 0
0 0
0 0
0 1

0
0
0
0
0
0
1
1

0
0
0
0
0
1
0
0

0
0
0
0
0
1
0
1

1
1
1
1
1
1
0
1

1
1
1
1

1
1
1
0

1
1

0
0

1
1

0
0

1
1
1

0
0

0
1

1
1
1
1
1

Bit Map for One Output
(Same for All Outputs)

X2 X3 X4 X5 X253 X254 X255

0
0
0
0
0
0
1
0

1
1

1
1
1
1
1
1
1

4-----32

COLUMNS~

Xo
Xl

Array Organization

256

ROWS

R
0

x 254
x 255

E
L

'YOY1YZ

Y31

210473-7

C
T
Column'Select

2764A Bit Map

~-328

1
1
1
1

inter

RR·35

210473-8

2764A Die Photograph

5-329

(
Z DECODER)O--Al0 0 01 1 110 00 01 111 00 aD 1 11 10 00 01 11 10 00 01 1 11 00 00 11 1 10 00 01 11 10 00 01 11 1 a a

Y DECODER

~AO
AI

W DECODER
(OUTPUTS 0-3)·

(J1

CN
til

N
011

»
ID
::;

A13 A12 All A9
0
0
a
0

A6
0

A5
0

··
··
·
1

1111 111 10 00 000 00 111 11 11 1 a 00 00 a a 01 111 11 11 00 00 000 01 11 11 11 1 a a a 00 000

1111 111 11 11 111 11 000 00 00 00 00 00 00 01 111 11 11 11 11 111 10 00 00 00 00 00 00 000

01 10 01 1 00 11 a 01 10 01 1 00 11 00 11 00 11 00 1 1 a 01 1 0 01 10 01 1 00 11 00 11 00 11 00 1 10

0000 000 00 00 000 00 000 00 00 00 00 00 00 01 111 11 11 11 11 111 11 11 11 11 11 11 11 111

R DECODER

X DECODER

........

1111 000 01 11 1 a a 00 111 10 00 01 11 1 a a a 01 111 00 00 11 11 000 01 11 1 a 00 01 11 10 000

A7
0
0

A8
1
0

1
0
0
1
1
0
0
1
1
a

0
1
0
1
0
1
0
1
0
1

:JJ
:JJ
I

Co)
(1'1

0
0
1

0
1
- 0
0
1
0

210473-14
·Outputs 4-7 are mirrored images of outputs (0-3)

infef

RR-35

27128A Die Photograph

5-331

210473-15

intJ

RR-35

Yo
Y1
Y2

0
0
0

•
•
•

XS11

0
0
0

0
0
1

0
1
0

•
•

WDecode

Wo
W1
W2
Wa

•

Y15

Xo
X1
X2

Address Decoding
YDecode
A1
A2
A10

X Decode
RDecode
A14 A13 A12 As A7 A6 A11 Ag As
0
0
0
0 0 0
0
0 0
0
0
0 0 0
0
0 1 .
0
1 0
0
0
0
0
0 0 0

0
0
1
1

0
1
0
1

Array Organization

•

•
•

210473-16

Bit Map
OUTPUT 4 THROUGH 7

1--!'-~------64 COLUIoINS - - - - - - - - - I !

v,.

....-----.....-----.

W1 WOWZ W3 W1 WOWZ W3

W1 WO WZ W3 WoW, W3 W2

OUTPUT 0 THROUGH 3

!I--.--------

COLUIoI~S

-----------I!

210473-17

27256 Bit Map.
5-332

RR-35

210473-18

27256 Ole Photograph

5-333

inter

RR-35

Yo
Yl
Y2

A2
0
0
0

•

Address Decoding
Y Decode
WDecode
A1
Ao
A4
A3
A10
0
0
0
0
0
Wo
0
0
1
0
1
Wl
0
0
0
W2
1
W3

•

Y15

Xo
Xl
X2

Array Organization

X Decode
A14 A13 A12 A7 A6 As A11 A9 As
0
0
0 0 0
·0
0
0 0
0
0
0
0 0 0
0
0 1
0
0 0 0
0
0
1 0
0

•
•

X510
X511

0
1

210473-16

Bit Map
.OUTPUT 0 THROUGH 3
'64 COLUMNS
Xo

•
•
•
X254

256
.ROWS

X 255

I I

• • •

'wow,'
'w,w~

210473-24

OUTPUT 4 THROUGH 7
64 COLUMNS

Xo
X,
X2

•

256

•

ROWS

X254
X255

· ~L_LILILIJLlul~I_·_·_·J~I_ILlwl~~I~~I_·_·_·~I~I~. 1
Y,

•••

Y2 • • •

'wow,'
'w,w~

210473-25

27C256 Bit Map
5-334

inter

RR-35

210473-26

27C256 Die Photograph

5-335

inter
A14
WLO
WL1
WL2

Address Decoding
X Decoders
A13 A12 A7 A6 As A11 Ag As
0
0
0 .0
0
0
0
0
0
0
0
0
0
1
0
.0
0
0
0
0
0
0
0

I
I
I

1
,1

WL510
WL511

·WDecoders
W
A3

0
0
1
1

0
1
0

WO
W1
W2
W3

0
1

Array Organization·

V Decoders
Ao
A10

0
0
0
0
0
0
0
0
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0

0
0
.1
1
0
0
1
1
0
0

0
1
1
1
1

1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

YO
Y1
Y2
Y3
Y4.
Y5
Y6
Y7
YB
Y9
Y10
Y11
Y12
Y13
Y14
Y15

0 0 OJ 02 0 3 0" 05 0& 07
210473-36

OUTPUT. THROUGH 7
6. COLUMNS

..II
X511

, 1,1,1,1"·1 , I,
YO

'WoW?

'WiWa

Y2. • •

'WoW?

Y104

I ,

V15

I ,1"·1

'WOWl
'W2vi3
'WiWa
'Wm

210473-37

OUTPUT 0 THROUGH 3
64 COLUMNS
Xl .
XO

512
ROWS

X5I
X511

, I, 1,1,1"·1
Y15

Y14 Y13

'W2vi3

'W2vi3
'Wm

I,
Y1

I
Y15

I···

I ,

Yl.

'WoW1
'WiWa

27C256 Bit Map (Six Digit Suffixes)
5-336

I ,
Yl

'WiiVR
'WiWa

210473-38

intJ

RR-35

210473-35

27C256 Die Photograph
(Six Digit Suffix)

5-337

intJ

RR·35

Yo
Y,
Y2

Address Decoding
YDecode
A1
Ao
A10

0
0
0

•
•
•

0
0
0

0
0
1

0
1
0

X Decode
A14 A13 A12 A7 As As A11 As ·Aa

0
0
0

•
•
•

X510
X511

0
0
0

.wo
W1
W2
W3

0
0

0
1
0
1

Y15

Xo
X,
X2

WDecode
A4
A3

0
0
0

0
0
1

0
1
0

1
1

0
1

Array Organization

210473-16

Bit Map
OUTPUT 0 THROUGH 3

64 COLUMNS

256

ROWS

1
•••

'WOw,'

'W,W~

210473-24

OUTPUT 4 THROUGH 7

64 COLUMNS
Xo

X,
X2

•
•

256
ROWS

•
X254
X255

•••

1
210473-25

87C257 Bit Map

5-338

intJ

RR-35

210473-34

87C257 Die Photograph

5-339

RELIABILITY
REPORT

RR-67

November 1990

EPROM Reliability
Data Summary
CHMOS III-E

Order Number: 293004-002
5-341

INTEL EPROM
RELIABILITY DATA SUMMARY: CHMOS III-E
CONTENTS

CONTENTS

PAGE

D27C210 .............................. 5-354

INTRODUCTION/SCOPE .............. 5-343

D27C020 .............................. 5-356

Quality and Reliability: The Cornerstone
of Business .......................... 5-343

D27C220 .............................. 5-358

Quality versus Reliability ................ 5-343

PLASTIC RELIABILITY DATA
SUMMARY ........... _.............. 5-360

The Roots of Reliability ................. 5-343

N27C256 .............................. 5-362

MONITORS: THE CONTROL
MECHANISM OF RELIABILITY ..... 5-343

N27C010 .............................. 5-364
N27C210 .............................. 5-366

STRESSES: THE ACCELERATION OF
TIME AND USE ..................... 5-345
REFERENCES ......................... 5-346

APPENDIX A: CALCULATION OF
FAILURE RATES, 60%
CONFIDENCE ....................... 5-369

CERDIP RELIABILITY DATA
SUMMARY .......................... 5-347

APPENDIX B: BIT MAPS AND DIE
FHOiOS ............................ 5-375

D27C256 .............................. 5-348
D27C512 .............................. 5-350
D27C01 01011/100 ..................... 5-352.

5-342

inter

RR-67

Therefore, Intel advocates that you make reliability a
key consideration for the selection of your system's
components.

INTRODUCTION/SCOPE
Quality and Reliability: The
Cornerstone of Business

The Roots of Reliability

In the world of electronic hardware, no facet is more
important to the user of a system than the reliability of
its individual components. This single point has been an
instrumental factor in the philosophy of product development, qualification, and manufacturing within Intel.
Being the inventor of the EPROM, we are proud of the
continuous quality and reliability leadership position
that we have maintained.
"In the spirit of service to our customers and their customers, this publication has been assembled for your
convenience and reference. The scope of this document
is limited to Intel's latest EPROM VLSI products from
the 256 Kbit to the 2 Mbit density manufactured on
our CHMOS' III-E process technology. Other
EPROM product/process reliability summaries can be
found in the latest revision of RR-35. The data provided herein is the product of just one of Intel's qualification and reliability monitoring systems. The purpose of
this report is to supplemerit Intel's Quality and Reliability handbook with product specific data. For additional information, please contact your Field Sales or
Customer Quality Engineer.

The manufacture of a reliable VLSI semiconductor
device using a modem technology is a dynamic and
evolutionary process. Success of this process is highly
dependem upon [ite imerpiay Deiween Knuwit:ugt:auit:
and experienced manufacturing engineers, materials
physicists, and responsible/responsive management.
Only the correct combination can consistently deliver
high volumes of reliable product. In this model, the
experienced process engineer selects and defines the
stresses to be performed and the performance criteria to
be met, utilizing appropriate statistical tools and limits.
The materials physicist then determines the root causes
of failure, if and when failure occurs, and provides effective solutions and/or containment recommendations. Finally, management provides the resources for
the entire process from initial monitor to root cause
corrective action.

MONITORS: THE CONTROL
MECHANISM OF RELIABILITY
A Comprehensive Program Is The Key

Quality Versus Reliability
The traditional concepts segregating quality from reliability is one of time. Quality is a measure of the ability
of a product to meet performance expectations at a single point in time. This "point in time" is usually interpreted as your initial board power-up or incoming inspection. Reliability, on the other hand, is a measure of
a product's ability to maintain its "time zero" quality
throughout its life cycle. A reliability failure usually
occurs after your product has shipped to your customer.
The cost of poor quality can be objectively totalled
within your organization. It includes the cost of detection and in-house repair. However, the cost of poor
reliability has a much higher cost. Besides an inherently
higher repair cost per defective unit, reliability failures
create customer concern about design and/or workmanship standards used in the manufacture of the
product. Loss of goodwill with your customers can
have many long term negative effects on your business.

Intel has developed and implemented many types of
reliability monitoring systems. Since continuous delivery of reliable product is of paramount importance,
most of the, monitors are in-line and are designed to
provide as close to "real time" feedback on the reliability of the product in-process as possible. The monitors
are located throughout the fab, assembly and test areas.
, The data from these monitors are an indication of process health' and overall statistical control. They are not
necessarily directly correlatable to the reliability of the
product that will ship to your location. For this reason,
a final finished product monitor which randomly selects product is used as the yardstick to measure the
success of our factory in meeting your customer's reliability goals. Figure I demonstrates the typical monitor
stress cells and flows which are periodically used on
every major product in Intel's EPROM family. A similar stress flow is also used for plastic devices. The data
presented in the device section of this report is a compilation of this monitor data plus the initial product qualification testing results.

'CHMOS is a patented process of Intel Corporation.
5-343

RR·67

STRESS DEFINITIONS:
TIC = Temperature Cycle
HV ELT = High Voltage Electrical Life Test
Bake = High Temperature Storage
Burn-In = 5.25V Electrical Life Test

. 293004-11

Figure 1. CERDIP EPROM Standard Monitor Flow

5-344

inter

RR-67

EPROM Failure Mechanisms
The typical EPROM is about 10% decoder and "special" test mode circuitry. This 10% of the circuitry is
similar in design and layout to the circuitry found in a
common logic device. Expected failure mechanisms are
therefore considered to be primarily oxide stress and
contamination based. For more information on these
and other mechanisms, please refer to the Intel Quality
and Reliability Handbook. The remaining 90% of the
EPROM area is a very dense matrix of isolated tloatmg
gate memory cells manufactured using the latest process technology. The major function of the EPROM
cell is to store a very small amount of charge on a
floating polysilicon gate, and to do so for a time period
well in excess of 20 years under normal operating conditions. Electrons are electrically injected through the
isolating oxides onto the floating polysilicon gate during programming. Because a typical EPROM cell may
only need 100,000 electrons on this floating gate to look
"programmed," it can be sensitive to leakage currents
of as little as 1 x 10- 23 amps [1]. Small amounts of
charge loss or gain in excess of intrinsic expectations
can, through time and usage, significantly raise or lower the threshold voltage of the memory cell causing the
device to functionally misread the intended pattern.

1.4ev/ 1.0e,,/
106

I;'
0

"''"
'"....o .s::"

104

z ...
QI!!
'<~

... "
'" r::
...J

105

L
0.6eV/

1/
1/

103

102

/11

... 0

u"o
« J:!"

0.3eV'/

101

U/ . /
100

V
250 200175150125 100 75

1/TEMPERATURE °C
293004-12

Figure 2. Arrhenius Plot and Failure Activation
Energies Relevant to EPROMs

STRESSES: THE ACCELERATION OF
TIME AND USE

Table 1. Activation Energy Table
Failure Mechanism

Acceleration Factors
In order to determine if a device's reliability performance can be accelerated, normal operating condition
failure mechanisms must be completely understood and
characterized to the accelerating stress. The familiar
Arrhenius equation is then used for the calculation of
the acceleration factor which most clos~ly approximates the condition of the stress. Figure 2 is an example of how the Arrhenius curves would appear
for the most common semiconductor failure mechanisms which are accelerated by temperature over a period of time. All known operating condition failure
mechanisms in semiconductor devices can be accelerated with the use of various stresses. These stresses include: temperature, voltage, current, moisture, mechanical stress, and radiation. Table 1 indicates the most
common failure mechanisms and their activation energies which are associated with being thermally accelerated. The mechanics of deriving an operating failure
rate (FIT rate) from these factors is described in Appendix A.

5-345

Each

Oxide

0.3

Single Bit Charge Loss/Gain

0.6

Contamination
Speed Degradation
Intrinsic Charge Loss

1.0
0.3-1.0
1.4

inter

RR-67

sheet parameters. The Memory Components Division
also periodically takes variables data on selected data
sheet parameters to monitor the stability of the process.
Low-temperature Iifetesting has also been performed on
this process to assure that no intrinsic hot electron
mechanisms are present.

Commonly Monitored EPROM
Stresses
As discussed earlier, it is important to have a comprehensive reliability monitoring program that can uncover the many potential failure mechanisms which may
have an impact to total quality, reliability and deliverability. The listing below represents only the major and
most consistently performed reliability monitor stresses. They are executed on randomly selected finished
product inventory.

DATA RETENTION BAKE

HIGH·TEMPERATURE DYNAMIC LIFETEST
(5.25V and 6.5V)
This stress is considered the most relevant of all accelerating stresses. The device is programmed with a
checkerboard data pattern to simulate a random customer pattern. It is then functionally exercised at 12S·C
at either aVec of S.2SV or 6.SV. The memory is sequentially addressed and the outputs are exercised but
not loaded. See Figure 3 for a typical bias and timing
diagram. The S.2SV stress is considered thermally accelerating only. The 6.SV stress is considered both thermally and voltage accelerating for oxide fault type
mechanisms(\). The end point electrical tests are conducted within a fixed period of time to worst case data

°7

°s
0.
°3

°2

293004-3

m: = +ov R = 1 KIl. VJ 15

FIT Rate (60% UCL)
0.915 x 109fT
2.02 x 109 fT
3.105 x 109 fT
4.17 x 109fT
[ 1.049 (# failures for a ~rticular EA) + 1.0305] [ 10 9 ]

[0.2533

+ J(4 x

5-371

Failed)

+ 3]2 [

9]
10

inter

RR-67

Example I:
Assume for this example, that ICC active is 57 rnA at TAmbient
55°C. I
Also assume that 6JA

125°C and ICC active is 60 rnA at TAmbient

35°C/W.

Then,
T2 = (35'C/W) (57 mAl (5V)
'" 135'C
T1

125'C

408'K

(35'C/W) (60 mAl (5V) ,: 55'C

'" 65'C = 338'K

EA (eV)

Actual Device
Hours @ 125°C

Acceleration Factors
For 135°C to 65°C

Equivalent
Hours at 55°C

# Fail

55°C
FIT Rate

0.3
0.6
1.0

2.185 x 106
2.185 x 106
2.185 x 106

5.85
34.18
359.93

1.278 x 107
7.468 x 107
7.864 x 108

0
2
1

81
42
3
126 FITs

Total Combined Failure Rate =

Example 2:
AssJ.lme than an additional lot of 800 CHMOS III-E devices is burned in using a 6.5V lifetest as shown below.
Assume further that the one failure shown at 168 hours is a 0.3 eV oxide failure. Using Table 2 below, a voltage
acceleration factor of 26 results from a 1.25V voltage overstress (5.25V to 6.5V).

Actual Device Hours = 800 (48 hrs-O hrs)
3.997 x 105

800 (168 hrs-48 hrs)

799 (500 hrs-168 hrs)

Table 2. Time-Dependent Oxide Failure Voltage Accelerations Relative to 5.25V
Type

CHMOS

III~E

Supply
Voltage
(Volts)

Oxide
Thickness
(A)

Operating
Stress
(MV/cm)

5.5V

235

2.15

1.9

Ufetest Stress Voltage

I
I

6.0V

7.0

6.5V

J
I

7.0V

ASSUMES:
1. Failure rate calculations use the appropriate acceleration factor for stress voltage versus 5.25V operating voltage (conservative) ..
2. Reference [2] E. Nelson Anolick.

5-372

inter

RR-67

Since this voltage accelerated stress is used to predict an oxide breakdown failure rate, the S.2SV burn-in/lifetest
SS·C equivalent hours for EA = 0.3 eV are added to the 6.SV burn-in/lifetest SS·C equivalent hours as follows:
12S·C
Burn-ln/Lifetest

EA (eV)

Actual Device
Hours @ 12S·C

Acceleration Factors
for 13S·C to 6S·C

Equivalent
Hours
@SS·C

5.25V
6.5V

0.3
0.3

2.185 x 106
3.997 x 105

5.85
(5.85 x 26)

1.278 x 107
6.079 x 107

Tnt~1 J:'nlli\l~lont

nO\li,..o

I-Inl"~

fnr n

~ t::l\lI=~ihlrjOC::

= 7

~~7

y 1n7

The following failure rate predictions include the total equivalent SS·C, EA = 0.3 eV device hours found above:
EA (eV)

Actual Device
Hours @ 12S·C

Acceleration Factors
for 13S·C to 6S·C

Equivalent
Hours
@SS·C

# Fail

SS·C
FIT
Rate

0.3 ELT
0.3 HVELT

2.185x10 6
3.997 x 105

5.85
(5.85 x 26)

7.357 x 107

0.6 ELT
0.6 HVELT

2.185 x 106
3.997 x 105

34.18
34.18

8.834 x 107

1.0 ELT
1.0 HVELT

2.185x10 6
3.997 x 105

359.93
359.93

9.303 x 108

Total Combined Failure Rate =

84 FITs

NOTES:
1. Additional information on calculating failure rates is contained in the April 2, 1984 International Reliability Physics Symposium editorial entitled "Calculating Failure Rates from Stress Data" by Robert M. Alexander.
2. 1 FIT = 1 Failure Unit = 0.0001 %/1 K hours.

5-373

inter

RR-67

APPENDIX B
EPROM Bit Maps and Die Photos

5-375

inter

RR-67

21C256
(Six Digit Suffix) Array Organization and Bitmap
f----

256 COLUMNS

-----i

ARRAY A

293004-22

ARRAY B

293004-23

OUTPUTS 0-7
64 COLUMNS (32 IN ARRAY A, 321N ARRAY B)

ARRAY B Yo

• • • • • • • • • • • • • • • • • • • • • • • • • Y31

ARRAY A Y32 Y33 Y34 • • • • • • • • • • • • • • • • • • • • • • • • • Y63

YDECODE
YOO
Y01
Y02

•

•
YS3

ARRAY SELECT

A12

A13

A10

0
0
0

0
0
1

0
1
0

•

•
•

•

•
•

•
•
X DECODE

A11

0
0

0
0
0

0
0
1

0
1
0

•

XOO
X01
X02

•

•
•

•

X511

•

•
1

•

5-376

•
•

inter

RR-67

27C256 (Six Digit Suffix) Die Photograph

293004-18

5-377

inter

RR-67

27C512 Array Organization and Bitmap

293004-25

OUTPUTS 0 THROUGH 3

OUTPUTS 4 THROUGH 7

[~~~.
•

R'5

[

:~:

•
• 1 - - - - - - - '28 COLUMNS - - - - - - - - 1

1 - - - - - - - '28 COLUMNS - - - - - - - 1

Roo

.{~:
Roo~+._~~+._~~+._~__~~~~~~
W7 We •• W7 We Ws
L....J

L....J

v's··· Yoo

w, •• Ws W4 W3 w2 •• W3 W2

L...J

W, Wo ••

L...J

L....J

Y,s ••• Voo

Y,s •• • Voo

L...J

w, Wo

Wo W, •• Wo W, W2 W3 •• W2 W3 W4 Ws •• W4 Ws We w7 •• WI W7
L....J
L..JL...J
L..JL...J
L..JL...J
L....J

L...J

v's··· YOD
293004-26

Voo ••• Y,s

Yoo ••• VIS

0
0
0

0
0
1

0
1
0

•
•

Wo
WI
W2

•
•

Y15

WDECODE

Al0

•
•

•

A15

0
0
0

~
0
0
0

0
0
0

0
0
1

0
1
0

ROO
ROI
. R02

X31

R15

•
•

A14

0
0
1

0
1
0

•
•

RDECODE

•
•

0
0
0

•

Xoo
XOI
X02

•
•

A12

•

•
•

X DECODE

•
•

Yoo ••• v,s

293004-27

YDECODE
Yoo
YOI
Y02

Yoo ••• VIS

•
•

5-378

A13

All

0
0
0

0
0
1

0
1
0

•
•

inter

RR·67

27C512 Die Photograph

293004-24

5-379

intJ

RR·67

27C010/100 Array Organization and Bitmap
COLUMNS

-5,2-

-512-

LITDJi[IIJ

ROWS

00 0, 02 03

04 05 0 6 07

293004-19

OUTPUTS 0 THROUGH 3

['"

OUTPUTS 4 THROUGH 7

R14
0

0
0

Roo

R~,

128 COLUMNS

R, •

. .
0

[~
ROI
0

XI!

•

R15
W, We ••
LJ

w, We Ws W.... Ws W.. W3 W2 •• W:s W2 W, Wo •• w, Wo
LJ

Y,s ••• '1'00

'1"5··· Yoo

w, •• wo W, W2 W3 •• W2 W3 W.. Ws •• W" Ws We W, •• We W,

LJ
Yoo

LJ.

'1',5 ••• Yoo

Y'5 ••• Yoo

•••

'1"5

Yoo ••• '1"5

Yoo

•••

V'5

'1'00 ••• '1"5

293004-20

293004-21

WDECODE

YDECODE
YOO
YOl
Y02

•
•

Y15

Al0

0
0
0

0
0
1

0
1
0

•

•
•

..•

•

A16

0
'0
0

Wo
Wl
W2

•

•
•

•

XOO
XOl
Xo2

•
•

X63

•
•

0
0
0

•
•
1

As
0
0
0

•
•

A12

A14

0
0
0

0
0
1

0
1
0

•

0
0
1

0
1
0

•
•

RDECODE

•
•

A15

•
•

X DECODE
~
0
0
0

•
•

•
1

5-380

A13

All

ROO
ROl
R02

0
0
0

0
0
.1

0
1
0

•

..•

R15

•
•
1

•

•
1

RR·67

27C010/27C100 Die Photograph

293004-7

5-381

intJ

RR-67

27C011 Array' Organization and Bitmap
COLUMNS

[In[ill
-512-

,1,

ROWS

-512-

00 0, 02 03

o. Os 06 07

293004-15

OUTPUTS 0 THROUGH 3

[."

OUTPUTS 4 THROUGH 7

R,.
0

0
0

Roo

[~Ro,
0

128 COLUMNS

R:5
0

['.
0

ROI

0
0
0

R'5
W~6··W~6W~4··W~.W~2··W~2W~O··W~o
Y,S ••• Yoo

Y,s ••• Yoo

Y,S ••• Yoo

We W, •• Wo W, W2 W3 •• W2 W3
L...J

Yoo

Y,S ••• Yoo

•••

L...J

YIS

Yoo

w. Ws •• W",Ws W6 w7 •• W6 w7·

L...J

L...J '

Y,s

Yoo ••• Y,s

•••

L...J

293004-16

•
•

Y15

WDECODE

Al0

0
0
0

0
0
1

0
1
0

Wo
Wl
W2

•

•
•
1

•

•
1

•
•

•

•
•

X63

0
0
0

•

•
•
1

•

0
0
0

0
0
1

0
1
0

.•
1

•
•

•

•
1

R DECODE

•
•

A12

X DECODE
XOO
XOl
X02

L...J

Yoo ••• Y,s

293004-17

YDECODE
Yoo
YOl
Y02

L...J

•

As
0
0
1

•

•
1

0
1
0

•
•

A13

All

ROO
ROl
R02

0
0
0

0
0
1

0
1
0

•

R15

5-382

•
1

•

•
•
1

•
•

infef

RR-67

27C011 Die Photograph

293004-7

5-383

RR-67

27C210 Array Organization and Bitmap
I

y--------------~

111111111111111111
293004-30

OUTPUTS 15 THROUGH 8

OUTPUTS 7 THROUGH 0

[:~:
•

•

Roo

[:~~
•

• 1------

64 COLUMNS

1-----

------I

64 COLUMNS

------I

R15

•
•
•
XS3

•
•

[:~~
•
•

R15

'":':W~3~W2""":W~3-::W~2-.-• •""":W~3-::W"'2~W""":1W~O-::W"'l~Wo-.-.-.-::W"',~Wo""
L.J

L.J

Y'5

Y'4.··

L.J

Y'5

Y14

•••

w, Wo w, ••• Wo W, w2 W3 w2 W3 ••• w2 W3

L.J

Yl···

L.J

Y15

L.J

YDECODE

•
•

A15

A14

0
0
0

0
0
1

•
•

•

Y15

WDECODE

A13

•

Wo
Wl
W2
W3

•
•

•

•
•

XS3

0
0
0

0
0
1

0
1
0

•

•
1

•
•
1

0
0
1
1

0
1
0
1

RDECODE

•
•

X DECODE
Xoo
XOl
X02

Y15

293004-9

293004-8

Yoo
YOl
Y02

L.J

Y1···

•

•
1

•
•
1

Roo
ROl
R02

•

•
•

•

R15

5-384

A12

All

Al0

0
0
0

0
0
1

0
1
0

•
•
1

•

•
1

intJ

RR-67

27C210 Die Photograph

5-385

inter

RR-67

27C020 Array Organization and Bitmap
COLUMNS

l[]]um
-512-

ROWS

-512-

00 0, 02 03

0" 05 0 6 0,

OUTPUTS 0 THROUGH 3

['"

293004-29

OUTPUTS 4 THROUGH 7

R,.
0

0
0

ROO

[~R:,•

·
·· ··
· ·

128 COLUWNS

'28 COLUMNS '

R,.

[~
Ro ,

X127

R,.
w,WS •• W7W.WS W4 •• WSW. W3 W2 •• W:s W2 w, Wo •• w, Wo
LJ
LJ LJ
LJ LJ
LJ LJ
LJ
Y,S ••• Yoo
Y,s ••• Yoo YIS ••• Yoo Y,S ••• Yoo

Wo w,
LJ

•• Wo W, W2 W:S •• W2 W:s W.. Ws •• W... Ws We W, •• w. W7
LJ

Yoo ••• Y'5

Yoo ••• Y,5

LJ
Yoo

Yoo ••• lUS

293004-13

•
•

Y15

WDECODE

A10

.0
.0

.0
.0
.0

..•

•
•
1

•
•

X127

A17

A16

A12

.0
.0
.0

.0
.0

•

•
•
1

•
•

•
•
1

A15

.0
.0
1

0
.o·

•
•

Aa
.0

•

•
•

•

RDECODE

X DECODE
Xoo
X01
X02

A14
Wo
W1
W2

•
•

As
.0
.0
.0

•
•

.0
.0
1

•
•
1

LJ
Y,s

293004-14

YDECODE
YOO
Y01
Y02

•••

A4
.0
1
.0

•

A13

A11

Roo
R01
R02

.0
.0
.0

.0
.0
1

.0
1
.0

R15

•
•

•

5-386

•
•

infef

RR-67

27C020 Die Photograph

293004-10

!.:' ,

5-387

inter

RR-67

27C220 Array Organization and Bitmap
0 .................................. 1023

1023 .................................. 0

•
•
•
•
•
•
•

07' 06

OUTPUTS 15 THROUGH 8

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
X 1022
X 1023

COLUMN • • • • • • • • • • • • • • • • • • • • COLUMN
IV'
0

127

~---------~,.....--~
YO ••.•••••••••.••.•••••••• : •••••• Y127

Y127 .••••••..•..•.••.••..•.•..••.•. YO
293004-6

293004-5

YDECODE
A16

•
•

Y127

0,
0
0

•
•

AIS

.A14

A13

0
0
0

0
0
1

•

•
•

•

•
•

Ao
0
1
0

•
•

•
•
1

X DECODE '
, A12
Xoo
Xol
Xo2

•
•

Xl 023

0
0
0

•
•

All

0
0
0

•
•
1

OUTPUTS 7 THROUGH 0

COLUMN . . . . . . . . . . . . . . . . . . . . . COLUMN

Yoo
YOI
Y02

0
0
0

•

•
1

0
0

•
1

Al0

0
0
0

0
0
1

0
1
0

A4'

'.•
5-388

•
•

inter

RR-S7

27C220 Die Photograph

293004-1

5-389

inter

ARTICLE REPRINT·

AR-414

Marriage Of CMOS And PLeC Sparking
Rapid Change In Mounting Memories
duce component weight as much as 75
-Is the proper assembly equipment
already available?
percent.
-Do components meet JEDEC stanLightweight PLee packages tend to
dards?
be' ideal for high-vibration industrial
he surge in circuit complexity
-Will socketing be required?
and automotive applications, as well as
over the past year or two has
The drive for smaller, more functional
for portable applications.
pushed the standard DIP size beand more competitive products is forcing
Surface mounting requires a subyond workable dimensions, and renmany engineers to scale down existing
stantial investment in capital equipdered it obsolete where high lead count
designs; to strive for VLSI solutions; and
ment. New techniques for soldering
is required.
to use PLCC packages and other surfacecomponents to boards (i.e., vapor phase
Meanwhile, the semiconductor inmount packaging options, which can reor wave soldering) must be considered
dustry's shift to CMOS processing for
duce board size dramatically.
and automated machinery such as
memories, as we,!1 as other ICs, is helpDecisions as to which surface-mount
pick-and-place assemblers must be eming usher in the era of surface-mountoption to use are usually based on boardployed-new pick-and-place machinery
able packages. Chief among these'
size restrictions. In general, PLCes
employing vacuum pickup has been depackages for memories is the plasticminimize the area footprint on a board
veloped
to handle the wide array of
, leaded chip carrier (PLCC).
for lead counts ranging from 28 to 124.
different sized packages available for
The technology for surface mountaOne example of the space-saving
surface mounting.
bles and CMOS processing emerged
ability of a PLeC package is In~l's new
Today, many different machines are
from shaky beginnings. Although sur32-lead PLCe package which it is deavailable. Their processing capacity
face-mount packaging has been availveloping for its 64k and 256k CHMOS
ranges anywhere from 500 to 500,000
able for nearly two decades, its potenEPROMS; The PLeC measures 0.45 x
de\-1ccs per hour. (SurfaCe-mounting
tial has just begun to be realized.
0.55 inch, whereas the 28-pin DIP that
technology is even used in small-volume,
Several technical problems hamwould normally be used here measures
custom facilities, such as for making porpered its early acceptance:- the need for
1.4 x 0.6 inch. The reduction in area
table medical equipment, where the deautomated factory equipment; prohibifootprint is 70 percent.
vices are manually soldered to boards.)
tively high packaging costs; and the
The contact area for chip leads can be
The benefits of factory-automated aslack of necessary construction tools.
closer for a PLCC device because the
As of 1984, only 6 percent of all commounting 'holes 'mandatory for inser- , sembly are numerous. Less floor space
ponents used in the United States were
is
required. Since raw materials are
tion devices are eliminated. Surface
contained in smaller packages, storage
surface-mount types. Industry analysts
mounting also allows components to be
predict, however, that with the inspace is diminished. Lighter-weight
placed and soldered on both sides of a pc
crease in packaging options, the availcomponents reduce shipping and hanboard where through-hole mounting is
dling expenses. Space-saving benefits
ability of development tools and the ' not employed. Depending on the comrising demand for surface-mountable
can be achieved in the layout of the
plexity and type of components reassembly equipment itself. Some mandevices, more than 25 pe~nt of compoquired in the board layout, a 35- to 60nents will be surface mounted by 1988.
ufacturers have been able to reduce the
percent reduction in board size is
required factory floor space by as much
And an estimated 128 million of the
possible.
'
as 25 percent. Other cost savings in600 million PLeCs manufactured in
To minimize total chip requirements,
clude a reduced labor force, the ability
1988 are expected to be memories.
manufacturers of products such
CMOS has had to fight a similar batas EPROMs are incorporating an adto maintain a no-shutdown assembly,
tle. Prohibitively high cost, inherently
improved reliability and reduction of
dress latch on the address and data pins
low performance (metal gates) and lack . to allow direct interface with a microinspection and rework.
of a complete lineup of products neces- _ controller or microprocessor. This
These Qenefits must outweigh, of
sary to provide low-power system solueliminates the need for an external
course, the costs of automating the factions were the chief reasons for CMOS'
tory, as well as the cost of restructuring
latch, as well as reducing board size.
slow start. But, these problems' have
and retraining.
Surface-mount elements can also renow been overcome and the number of
products combining CMOS technology
and surface-mol1nt packages is accelerating rapidly.

By Alan Hanson

:S. ;"'H~

PLCC Inroads
The decision to move from insertion
(through-hole) to surface-mount technology is not an easy one. The available
options are somewhat confusing:
-Are space constraints a problem?
-Is more functionality required?
-Will surface mounting make a more
competitive product?
-Will manufacturing-cost savings be
realized?

.. Letaral

Parasitic
R.u.r
Verticil
Bipolar
wV.
PNP Transistor

Bipolar
NPN Tranllslo

ThIs CMOS EPROM combines both n-channel and p-channel transistors onto a ptype epitaxial substrate to reduce greatly current requirements as compared with
an NMOS counterpart_
,

Ekctrrmic Engw.ring Tu... - MDNIDy. September 30. /985

Copyright" t985 by CMP Publications, Inc., 600 Community Drive, Manhasset, N.Y. 11030.
Reprinted with permission from Electronic Engineering Times.

5-390

Order Number: 295007-001

When choosing between packaging
alternatives, consideration should always be given to industry-wide standardization to avoid unnecessary design mismatching and insure
upgradeability. For example, the 32lead PLeC package was chosen for
high-density EPROMs because as
much as 512 kbits of address space is
easily contained within this package
size. Furthermore, PLCC devices with
as many as 124 J-type leads have been
I i:;i;i.iitci'~i! .....-it..L;. JE!)EC. th.~ et:!!!d~!t::!~
setting body for the industry.
A J-type lead extends out of the four
sides of a PLCC package and is tucked
under the body into small pockets. It
was chosen as the industry-standard
lead type as opposed to gull wing for
several reasons. A minimum-area footprint is best achieved with a J-Ieadgull wings extend horizontally out from
the body of the package, increasing the
required area footprint of the component. Because of their extended leads,
gull-wing devices are also at greater
risk to damage during assembly or
transporting.
J -type leads are also more aptly suited for socketing, which may be particularly important for memory components subject to periodic updates. The
J-lead PLCC does, however, have its
drawbacks, the most noticeable being
the difficulty encountered in inspecting
solder joints.
The next step for design engineers
who have decided to use PLCC components is to investigate the available
process-technology alternatives.

CMOS And PLCC Packaging
Applications ideal for both CMOS
parts and PLCC packages lie in lowpower portable products in space-constrained environments. Examples can
easily be found in the automotive, telecommunication and portable-instrument markets.
Alan Hanson is product marketing
enginaer, Intel Corp., Folsom, Calif.

CMOS' greatest strength lies in its
low-power properties. For example, intel's 27C64 CHMOS EPROM, which
combines both n-channel and p-channel transistors onto a p-type epitaxial
substrate, maintains a maximum operating current of 10 mA, standby current of 100 mA and otTers 200-ns total
access time. Its NMOS counterpart
would require six times more active
current, 200 times greater standby current and would otTer no improvement to
t~tA 1 Arr.p'j::lS time.

•
Both the 28-pln DIP and 32·leed PLCC
can hold anywllere from 32k to 512k
EPROMs. But, the carrier Is roughly a
third smaller.

PLeC packages are essential in portable applications because of their
space-saving and lightweight features.
Minimizing component packaging size,
however, achieves little if used in conjunction with bulky power supplies,
batteries and cooling devices. Because
of its low-power reql,lirements, CMOS
helps minimize the need for large power supplies and cooling devices, as well
as enhancing PLCC-device reliability.
Because of their reduced package size
and plastic construction, PLeCs are poor
beat conductors compared with the larger DIP packages. So heat-related breakdowns are more likely-heat dissipation
is generally a function of package material, length and construction of leads,
package surface area and, of course, the

5-391

power conswned by the devices.
In improving the overall integrity
and reliability of surface-mountable
components, methods must be em·
ployed to deal with thermal-management problems. The chief way to accomplish this for PLCCs is to reduce
the resistance to heat flow from the
active junction to the atmosphere.
Thermal resistance ranges from
about 40C· per watt for a 68-lead PLCC
package to more than 100C· per watt
for the 20-lead device. Copper alloy
leads, modified substrate materials,
and special heat sink~ are being used at
the package and board levels to maximize heat conduction.
In VLSI applications where increased
device functionality is required, thermal
management becomes an acute problem.
As functionality increases, power demands likewise increase. The resulting
higher operating temperatures may result in severe degradation to device operation and performance.
CMOS otTers a solution to thermalmanagement problems. For example,
the 27C64, with a maximum operating
current of 10 mA, generates 50 mW of
heat--a sixth the amount of its NMOS
counterpart.
Depending on the particular design
and application, special heat-sink designs and/or cooling fans can be reduced
or even eliminated with CMOS parts.
CMOS is particularly valuable in extended-temperature environments,
such as automotive engine-control applications where operating temperatures range from - 40·C to 80·C and as
high as 125·C. In these applications,
CMOS may be the only way to provide
reliable device operation.
CMOS also brings to a PLCC package wider Vcc tolerances and HMOS
compatability.
Support tools such as testing, soldering and programming equipment have
also become available for CMOS-based
surface-mount designs.
EET

ARTICLE
REPRINT

AR-455

One-Tilne

ProgrslDmable EPROMs
Plastic-packaged OTP EPROMs can offer the same performance
as their cerdip counterparts, while being more cost-effective.

1. Eight OTP EPROMs of varying densities stuffed in this EPROM library board store
bootstrap code, the microprocessor instruction set, and EPROM programming algorithms.

By Richard Immekus and Richard
Foehringer, Memory Components
Div., Intel Corp., Folsom, Calif.

inherent flexibility of EPROMs (they been available in plastic for years, this
can be programmed at a moment's has not been the case with EPROMs.
notice) and the rapid convergence of The essential characteristic of these
EPROM and ROM prices over the last devices, i.e., their UV-erasibility,
made packaging them in plastic exUltraviolet EPROMs (erasable, pro· few years.
tremely difficult. Some early attempts
grammable read-only memory), introwere made by various manufacturers
duced in the early 1970s, have encoun- OTPs and test
A type of device known as "one-time to produce plastic parts that incorpotered phenomenal acceptance in the
marketplace in the past few years. programmable" (OTP) EPROMs offers rl,ite a "window," similar to cerdip
Annual usage is measured today in the the same performance as its cerdip parts. These windows, however,
counterpart, yet is inherently more tended to fall out or leak during steam
hundreds of millions of units.
Where once EPROMs were used pri- cost-effective. In addition, these plastic and moisture testing and never proved
marily in R&D environments and pre- production EPROMs can now be pro- reliable.
production phases of a new product, grammed nearly 100 times faster than
Without the window, the UVtoday they are found in a multitude of cerdips. This dramatically reduces erasability feature of an EPROM is
mass-produced products ranging from throughput time and paves the way for lost and a major barrier to manufactelephones and video games to automo- cost-effective, automated on-line pro- turing OTP parts is erected. To be
biles and home computers. The pene- gramming.
useful to the customer, EPROMs must
tration into markets once .dominated
Although most memory products be received in a blank state, yet still be
by masked ROMs is both due to their (ROMs, DRAMs, SRAMs, etc.) have tested during the manufacturing pro-

Order Number: 295016-001

5-392

OTPs are preferable for auto-insertion.

cess to verify that they comply to pub·
lished specifications and that each cell
can in fact be programmed. Thus, verification entails programming, testing,
and erasure. Intel has succeeded in
refining its testing methodology to the
point that each die is individually and
thoroughly tested at the wafer level;
the wafer is then UV-erased. In addition, proprietary innovative test
modes have been incorporated into the
EPROM design to allow performance
testing at the post-packaging level.
The result is that the customer receives fully tested OTP parts with the
same guaranteed performance and
programmability found on cerdip
EPROMs.
Because plastic-packaged parts are
non-hermetic, moisture resistance is
always a concern to reliability engineers. In the semiconductor industry,

marginalities and causes oxide damage, thereby creating a leakage path
for the charge cell. Such occurrences
can readily be induced via steam "pressure cooker" testing or extended 85°C,
85 percent RH exposure, and are manifested as charge-loss taliures.
In order to provide OTP parts that
can withstand the effects of moisture
and steam - i.e., exhibit no evidence
of corrosion or charge loss and still be
erased properly when exposed to UV
light - Intel developed a proprietary
multilayer passivation process. The resulting protective layers were the last
missing element in a systems solution
to providing cost-effective production
EPROMs.

(Fig. 2) and lot-quality inspection sampling are carried out on each and every
manufacturing lot. Electrical and visual inspection is performed to a 0.1
percent acceptable quality level (AQL).
Not only is outgoing quality sampled
ana verifiea, Dut prograIIllllHuiliLy, iu~
fant mortality and long-term reliability are monitored on a weekly basis.
These tests are conducted on finished
products and, since OTPs are non-erasable, all devices used for quality and
reliability monitors must be scrapped.
The results of electrical testing carried out to date show that OTP
EPROMs are as reliable as cerdip
EPROMs. Using data from qualification and process monitor tests, the
calculated low failure rates of OTPs
Qualification
(less than 0.02 percent per 1,000 device
Every engineer knows that the tran- hours) match those of their cerdip
sition from lab-condition product de- counterparts.
In addition, moisture resistance is
exceptionally high for these plastic
OTP qualification process
OTP parts. A survey of major customConditions
Test
ers regarding needs for moisture performance
has revealed that a percentProgrammability
All voltage corners
age defect allowable (PDA) of 3 to 5
O°C, 25°C, 70°C (equivalent)
Speed performance
percent is required. Intel's in-house
Theta JA by device type
Thermal impedance of the package
qualification procedures generally re48-hrI168-hr 125°C dynamic burn-in
Burn-in
quire plastic packaged parts to withElevated temperature life test
500-hrll.000-hr 125°C dynamic life test
stand 96 hours of steam and 1,000
168-hrI125°C high-voltage ELT (6.5 V)
High·voltage ELT
hours of 85°C, 85 percent RH. This
I ,000-hrI140°C static data retention bake
Data retention bake
specification equals or exceeds that of
96-hrI16B-hr 121°C 30 psi steam
Steam
Intel's
major customers.
I,OOO-hr 85°CI85% relative humidity
85185
Many people today assume that beDescrlptlonlmethodology
Test'
cause cerdip packages are hermetic,
they are inherently more reliable and
Mil std 883, method 1010C
Temperature cycle
Mil std 883, method 10llC
better suited to production than plastic
Thermal shock
units. This was true years ago, but
Mil std 883, method 2001
Centrifuge
Mil std 883, method 2011
with the advent of automated assemBond pull
,
Mil std 883, method 2019
bly lines, and particularly autoinserDie shear
Mil
std
883,
method
2004
tion
equipment, a problem with cerdip
Lead fatigue
In-house, 2-hr 170°C, I-hr steam
usage began to emerge. It was found
Solderability
that cerdip packages occasionally chip
'Tests conducted to determine the mechanical worthiness of Intel's 28'pin OTP package.
or crack if not handled properly. Plastic packaged components, however, do
nitride is' very commonly used as a sign to mass production in a high- not experience this deficiency.
passivation layer and moisture barrier volume manufacturing environment is
Today, plastic EPROMs are prevaon ICs. With EPROMs, however, stan- difficult at best. To minimize risks and lent in most computers, video games,
dard nitride passivation is not accepta- ensure reproduceability, Intel takes modems, printers, electronic typewritble due to its non-UV-transmissive each new product through a rigorous ers, and other products. The increasing
composition. In addition, EPROMs qualification procedure (see table) in demand for highly automated assemhave a special sensitivity to moisture which exhaustive tests, both destruc- bly lines and production flow denot found in any other state-of-the-art tive and non-destructive, are per- manded by these items will lead to
formed for both electrical and mechan- increasing use of plastic packaged
NMOS product.
Due to the nature of the storage cell ical testing. Substantial amounts of components at the expense of cerdip
in an EPROM structure, data is main- electrical data are collected and scruti- packages.
tained in a non-volatile state via nized, and failures are analyzed to the
charges trapped on a phosphorus- last detail.
Fast programming issues
doped floating polysilicon gate. Entry
To ensure the quality and reliability
Earlier it was stated that OTP proof moisture is due to passivation de- of its products, Intel follows a "zero duction EPROMs can be programmed
fects
or
passiva,tion
process defects" program. Reliability monitors almost two orders of magnitude faster

5-393

2. Sample tests in this OTP monitor flow
are conducted on each manufacturing lot
on a monthly basis.

than cerdip equivalents. When one
considers that most 256K EPROMs
generally program in four to six minutes and that an OTP such as the
P27256 can be programmed in less
than four seconds, one begins to realize
the magnitude of the time savings and
increased throughput potentially
available to the user with OTPs, without a corresponding compromising of
device reliability.
A new approach, designated by Intel
as the Quick-Pulse Programming algorithm, permits these faster program-

ming speeds through the use of much
shorter pulses than required by previous programming algorithms. For example, Intel's earlier Intelligent programming algorithm, which is still
required for cerdip parts, uses a one
millisecond pulse and an overpulse
scheme. By contrast, the Quick-Pulse
Programming algorithm usually needs
only a short 0.1 millisecond pulse with
no overpulse. Increased Vpp latch-up
protection is designed into these new'
OTP devices, and when Vpp and V", are
raised program cell margin increases. _

.Reprinted from ELECTRONIC PACKAGING & PRODUCTION February, 1987
@ 1987 by CAHNERS PUBLISHING COMPANY

5-394

AR-458

"V ...I "r 1""'""".
__ ...:...... n .. :_1.... n •• 1__
!l;;,rnVIVI~ WVlLla UUI""n.-rUI"'~
Programming ™ offer ideal mass
production firmware storage
V. Siva Kumar
Product Marketing Engineer
Intel Corporation
In today's manufacturing environment-where as the 256-kilobit, as many as 24 minutes would Quick.. Pulse Programming algorithm
production flexibility. just-in-time inventory be required to program the device. The Inteligent
For the first time, advances in EPROM design
management, and, above all, quick throughput algorithm therefore was devised to improve pro- and process technology aHow the use of short proare needed - EPROMs have established them- gramming throughput for the higher densities gramming pulses of only 100 microseconds.
The Quick-Pulse Programming algorithm takes
selves as the solution for cost-effective firmware available at that time-namely the 64-kilobit and
production. Intel Corporation, having invented 128-kilobit EPROMs.
advantage of tighter programming voltage tolerthe EPROM in the seventies, has continued to pioThe Inteligent Programming algorithm was the ances in conjunction with the increased V pp latchneer advances that have made EPROMs the first algorithm to exploit the fact that only a few up protection designed into Intel EPROMs. This
choice over masked ROMs as high-volume EPROM cells required 50-millisecond pulses to latch-up protection allows V pp and Vee to be
firmware carriers. Intel's one· time programmable program while a majority of the cells were sue- raised above the levels previously employed for
(Q TP) pi asti c-pae ka ged
programming, thus providing for
EPROMs, that can be progreater program cell margins.
grammed in a few seconds using
The algorithm is made possible
the new Quick-Pulse Programbecause of the improved HMOS
mingT~ algorithm, will supplant
II-E EPROM cell characteristics,
both CERDIP EPROMs and
carefully controlled cell profiles,
oxide thickness and quality and
masked ROMs in this firmware
storage task.
channel length controls (see
These plastic-packaged produc"Quick-Pulse-a Techni.cal Extion EPROMs, currently avail'planation").
able in densities up to 256 kiloThe flow chart of the Quickbits, are the world's first
Pulse Programming algorithm is
EPROMs that are programmable
shown in Fig. 1. One can immediusing the new Quick-Pulse Proately see that the algorithm is ingramming algorithm. This proherently similar to the earlier
gramming algorithm achieves up
Inteligent Programming algoto two orders of magnitude reduerithm in that it benefits from the
tion in programming time comdifferent characteristics of indipared to existing programming
vidual EPROM bits. Different
algorithms. Volume usage of high
cells require a varying number of
density EPROMs is now more
programming pulses, and an itercast-effective than ever through
ative closed-loop scheme allows
the use of OTP plastic packaged
flexibility in employing just the
EPROMs with programming
right number of pulses required
techniques employing this algoby each cell.
rithm.
The programming of an
To high-volume users of
EPROM using the Quick-Pulse
EPROMs, programming time is a
Programming algorithm is done
large component of throughput
as follows. The programming
time. As EPROM density has can·
voltage Vpr should be set at 12.75
tinued to treadmill toward the
li~·"'"
V with V('(: set to 6.25 V (higher
megabit level, programming
than the 5V V('e used during nortimes have become a major conFig. 1 - Quick-Pulse Programming Flowchart
mal operation). Iterative pro- .
cern to system manufacturers. Even the industry cessfully programmed with substantially shorter grammingpulsesof 100 microseconds are then apstandard Inteligent™ algorithm consumes a siz- pulses.
plied. Mter each pulse, the algorithm checks the
able amount of time in programming mature denThis algorithm employed a closed-loop tech- EPROM output to verify the desired programmed
sities. Therefore, if high-density EPROMs are to nique of margin checking. Nevertheless, this pro- value. If the output is incorrect, the algorithm reserve the manufacturing requirement of quick gramming technique still required pulse widths peats the pulse·and·check operation. If after 25
throughput, programming times must be reduced. in the millisecond range with mandatory such iterations the output of that byte still does
Innovation yielded the answer to this problem in overpulses. Hence. the Inteligent algorithm takes not verify correctly, the device failed programthe form of Intel's new Quick-Pulse Programming several minutes to program the highest density ming and is rejected. If the byte verifies accuratealgorithm.
EPROMs available today (265 and 512 kilobits). ly within 25 pulses, programming of that byte has
EPROM programming time evolution
Thus, the stage was set for a breakthrough in been accomplished and the next byte is similarly
programming algorithm development. The objec- treated. Data gathered from the programming
Until the advent of Intel's Inteligent Program- lives were simple: (1) ensure the shortest possible characterization of the Intel EPROM cell shows
ming algorithm in 1983, EPROM programming programming time with the present technology that over 99 percent of the cells only require one
was done using a nominal 50-millisecond pro- and (2) maintain the programmability and data programming pulse. Mter all the bytes are programming pulse per EPROM byte, a method that retention characteristics of the earlier algorithms. grammed, there is a final verification operation
required about 1.5 minutes to program a 16 kilo- The Quick-Pulse Programming algorithm satis- that compares all the programmed bytes to the
bit EPROM. If that same programming technique ties these objectives.
original.
were employed for higher EPROM densities such

r--------------------------,

ECN Published by Chilton Publishing, Radnor, PA 19089,
© Chilton Publishing,
5-395

Order Number: 295019-001

I~I
AlJ1O.pROGRAMMING: PRODUCTION FLOW, BLOCK DIAGRAM
BlANK

f~'t~~~LER

PRODUCTION
EPROMS

DATA 110
HANDLER 600)

r BI:;:".:.'_ _-,~
II.

_~JN 2

Comparison:
Quick·Pulse Programming
,vs, Intellgent Programming

Good parts to'

.)Invenlory

:ERFACE

b.)manualassemblyJlne

c ) automated assembly line

SINGLE·SOCKET

PROGRAMMER,

SUCH AS'
INTEL IUP 2001201

RejeetedDr

1"ledparts

Using the Quick-Pulse Programming algo- their own programmers or employ ~'on-bo8rd" pro·
rithm, the 256-kilobit EPROM can be programmed in a theoretical minimum time of 3.3
seconds compared to about four to six minutes required if the Inteligent algorithm were used. This
fast programming time is achievable when the
overhead associated with the programming equipment is minimized. The term "overhead" refers to
the time required by the EPROM programming
equipment to perform some operations needed to
program an EPROM. Some of these operations are
(a) verifying that the EPROM is inserted into the
socket in the correct orientation, (b) reading the
EPROM device identifier and manufacturer's
code, (c) selecting the appropriate programming
voltages, and (d) checking to see if the EPROM is
in an unprogrammed state.
. Most programmers currently available in the
market are based on older and slower microprocessor designs and consequently have large programming overhead. However, newer programa
mer designs anticipated in the near future will
utilize more efficient microprocessors, such 88 the
Intel 80186 or 80188, and should therefore have
substantially reduced overhead. The Quick-Pulse
Programming algorithm, when used in conjunction with low programming overhead, achieves
programming times close to the theoretical minimum, yielding a major improvement over the
Inteligent Programming algorithm. Many manUa
facturers using large volumes of EPROMs design

gramming (in-circuit programming of EPROMs).
This new programming algorithm will allow these
manufacturers to obtain the benefits of the reo
duced programming time. Table 1 shows the comparison of the programming times possible with
the Quick-Pulse Programming algorithm on programmers available today as well as the theoretical minimu~ programming time with no programmer overhead.

PROGRAMMING TIMES
With Data UO Model 120/121
(Firmware version V10):

2764A
Current algorithm 62 sec.

Quick-Pulse 16 sec.
Improvement 3.9 x

27128A

27256

124 sec. 272 sec .

32 sec.
3.9 x

68 sec.
4x

With Intel Fast 27/K'

2764A

27128A

27256

Current algorithm 41 sec.
Quick-Pulse 10 sec.

80 sec.
14 sec.

158 sec.
35 sec.

TheoretIcal limit with no overhead
on programmer

2764A

27128A

27256

0.9 sec.

1.7 sec.

3.3 sec.

Table 1

5·396

Tlle two main reasons that the Quick-Pulse Programming algorithm achieves its speed are the
extremely short programming pulses and the
elimination of the over-programming pulses.
The Inteligent Programming algorithm needed
longer pulses of 1 millisecond for programming.
However, the use of a higher Vpp 'programming

voltage in the Quick-pulse algorithm (12.75 V
compared to 12.5 V) increases etiiCiency (due to
higher drain voltage) and maximum margin (due
to higher gate voltages). This reduces the need for
longer pulses and allows the new algorithm to employ pulses of 100 microseconds.
The Inteligent Programming algorithm utilizes
a 3 x over-program pulse at the end of each byte
verification to ensure programming margin. This
means that even when a cell takes only one 1-millisecond pulse to program, the over-programming
caused the cell programming time to be 4 millisec·
onds; if the cell takes 2 milliseconds to program,
the total time increases to 8 milliseconds. Thus, if
the cell needed the maximum of 25 pulses to program, the total time consumed for program pulses
and overprogram pulse would add up to 100 milliseconds.
The Quick-Pulse Programming algorithm does
not need the over-programming J?ulse to ensure
adequate progra.mming margins. The use of a
higher Vee is a more direct means of achieving the
same result.
Thus, other than the reduction in the pulse
width and the elimination of the over-programming pulse, the Quick-Pulse Programming algorithm resembles the lnteligent Programming ala
gorithm, with both Vee and Vpp programming
voltages increased by 0.25 V. Table 2 shows the
comparison of the two algorithms.
(eont. on next page)

~====~======;------.

COMPARISON: QUICK-PULSE
VS. IHTEUGENT PROGRAMMING
Quick-Pulse
Inteligent
Pulse width
0.1 msec.
1 msec.
25
25
Max. # of pulses
Over-prog. pulses
no
yes (3 x msec.)

Vpp
Vee (programming)

12.~13.0 V
6.0-6.5 V
Table 2

12.0-13.0 V
5.75-6.25 V

Programmability and data retention test resuIts for the Intel P2764A and P27256 EPROMs
are as follows for 1GS·hour bum-in: P2764A 1700
............110

r ... I ....I. '7~AI;;

t ..d<>r1fn

f",;~~ '1'M ..

tAd

rp_

;~lt;~ho;-t"h;t t"h"; Q~i~k:P~lse Programming nl·
gorithm does not compromi~e reliability and qU;ality to achieve programming speed. Extensive
characterization and reliability data were accrued
to validate the algorithm.

breakages when machine handled. The plastic

OTPs make ROMs obsolete

packages are molded in one single piece with no
OTP plastic EPROMs have a ml\ior advantage
separate lid or base and consequently have no
to traditional ROM users and that is greater flexi·
alignment-related auto-handling losses.
bility.
In the fiercely competitive environment of
Modern production technology is increasingly today quick
time to market with the right product
focusing towards complete automation as the that ~eets the customers' changing needs is of the
menns of improving quality and reliability and re- utmost importance. Maintaining an inventory of
ducing manufacturing costs. With full automation
as the goal, the advent of the Quick-Pulse Pro- unprogrammed OTPs saves the firm from having
grammingalgorithm coupled with the OTP allows to store many line items of masked ROMs. The
simplicity and speed of programmi~g an OTP ~.
for the first time for the programming process to lows for quick changes of software. WIthout any inbe incorporated in the manufacturing flow. Using
automatic handlers that are available today, one creased overhead and management costs. With
can completely process the P2764A (64.kilobit changing requirements, ROM code obsolesce~ce is
a major cost increase factor that can agam be
--~-=9

,~n~~,:I:;!""""':";:o<"-,;:I-¥--< BIT LINE

1Stal~Cc~AM

...--1-''----'--+--<, Word hne

-re===:======;:;?1

E2PROM enable
Chip enable

Read enable ~~f
Write enable

Fil..

4: An NVRAM contains both a standard RAM and an
E 'PROM; data is written into the RAM during system opera·
tion, then stored in the E"PROM on power·down. When power
is restored, the data is loaded from E 2PROM to RAM.

most control applications. A single chip could contain the
microcontroller and this small memory. Today it is not unusual to find controllers connected to 8K or even 64K byte
NVM arrays. In fact, some applications use 16-bit processors not for their power but for additional address lines.
Nonvolatile memories come in densities-per-package
that range from 128 bytes to as much as 512K bytes. ROMs
and EPROMs have the highest densities. Both can accommodate densities up to 1 megabit (131,072 bytes).
NVRAMs, PROM., and E'PROMs have lower densities;their
applications, however, are usually less memory intensive.
Comparing the alternatives
Each nonvolatile memory type fits specific application
needs depending on its particular characteristics and limitations. Memory-related variables include unit quantity
(present and future), application, software and hardware

overhead, data security, available board space, package
style, and programming ease. Manufacturing-related
variables include production quantities, upgrade frequency, inventory logistics, service needs, code stability, and
cost. Further, the particular application will determine
the proportion of read-only and alterable memory amounts
required. General purpose computers may require less
than 1% of the total memory to be nonvolatile. In control
systems, however, NVM may comprise over 98% of total·
memory-mostly ROM or EPROM with E'PROM, NVRAM,
and RAM in lesser amounts. Keep in mind that device cost
is only part of a nonvolatile memory's cost effectiveness.
Weighing NVM costs
Device costs are directly related to die size and manufacturing technology. Simple devices, such as ROMs, EPROM.,
and E2 PROMs, have very low cost-per-bit. More complex
memories-NVRAM, RAM, and bubbles-have fewer bits
per die area and more complicated manufacturing processes. These memories have much higher per-bit costs.
Per-bit costs should not be confused with cost E'!ffectiveness, however, since other factors enter into the equation.
ROM. are the lowest cost-per-bit memories, but only for
high-volume productions, and only if code crashes
(firmware that outgrows a memory chip's capacity) and
firmware errors do not occur. Frequently, firmware errors
are discovered after system production begins; their likelihood increases as codes become longer and more complex.
A severe error could require costly scrapping of an entire
stock of ROMs; in this case, EPROMs can be more cost-effective. They offer erasability, on-the-spot programmability,
and a single-device inventory. Since production EPROMs
are usually programmed only once, plastic DIP EPROMs
can be used to decrease costs even further.
IfEPROMs are erased and reprogrammed in a field application, the EPROM must be replaced. Returned EPROM.
are cleaned, erased, reprogrammed, inventoried, and restocked. These maintenance costs could probably be deferred by using E2 PROMs. Because E2 PROMs are in-circuit
reprogrammable, new code can be downloaded via modem,
eliminating the need for a service call.
Battery-backed RAM is initially less expensive than
E2PROM or NVRAM, and it can be cost effective in properly
maintained systems. However, battery failure wipes out
stored memory and requires servicing to replace the battery and reestablish destroyed data.
Initial costs, software and hardware overhead costs,
code failure costs, and maintenance costs should all be
evaluated when considering nonvolatile memory alternatives. The NVM that provides the lowest system life-cycle
cost will be the most cost-effective memory. •
About the author
Terry Kendall has been with Intel for roughly two years.
His present assignment is in the Memory Components Division, working on EPROM products applications. He has a
BA in architecture from the University of Oregon and a
BSEE from California State ·University in Sacramento.

I&CS September. 1987

5-400

Flash Memories
(Electrically Erasable and .
Reprogrammable Non-Volatile
Memories)

FLASH
A NEW WAY TO DEAL WITH MEMORY
higher densities (Figure I), and highly reliable-a combination of characteristics other semiconductor memory technologies currently lack.

Computers use memory to· perform several functionsbackup storage, executable code storage, and data manipulation. Today, in systems where the code changes,
RAM is used to serve the function of code storage for
execution by the processor. RAM also serves the purpose of allowing data manipulation in the same technology. since DRAM is voiatiie, mass storage or t>atterybacked SRAM is used to provide nonvolatility. A small
amount of ROM/EPROM also provides the storage
technology to start computers (direct executable and
nonvolatile).

In contrast to EPROMs, however, which can only be
erased through exposure to ultraviolet light, the flash
memory array is eiectricaiiy erasabie-in buik. This
distinguishes it from traditional EEPROMs (electrically erasable programmable read-only memory) that are
by definition byte-alterable; the flash memory erase
function empties the entire device all at once (the device can be programmed incrementally, however-an
important capability for PC applications that require
frequent data/file updates). EEPROM technology's
byte-alterability, truly needed in a very small number of
applications, comes at a high price in terms of cell complexity, limited density and questionable reliability
(Figure 2).

A relatively new semiconductor technology, called
flash memory, stands to fundamentally change this scenario. Because of its true nonvolatility, electrical erasability and low cost, flash memory is regarded as an
ideal memory for embedded applications requiring code
or data updates. And so it is. However, because of its
inherent performance and cost characteristics and recent third-party software developments, flash memory
is also the technology that will reshuffle the existing
memory hierarchy within portable reprogrammable applications more dramatically than any other.

Intel
EEPROM
ETOXTM Flash

15J.L

38J.L

0.1%

Transistors
Cell Size
(1-Micro Lithography)

WHAT IS FLASH MEMORY?

Cycling Failures

At the semiconductor technology level, Intel's
ETOXTM (EPROM tunnel oxide) flash memory is
based on a single-transistor EPROM cell. As such,
flash memory is nonvolatile, meaning that it retains
its contents even if power is removed. This is in contrast to volatile memory technologies like static and dynamic RAMs that require continuous power to store
information. Flash memory's cell structure and
EPROM foundation also ensure that it is extremely
cost-effective to manufacture, continually scalable to

Figure 2

Lastly, unlike competitive approaches to flash memory,
Intel's ETOX process produces devices that can be cycled, or erased and reprogrammed, hundreds of thousands of times without fail. Again, this is a unique and
essential capability within reprogrammable applications
where files are updated frequently.

1000
500

...!::!

200
100

III

...
,..
...J
...J

..J
0

a:
......

Ow
Vee

±10.0

Vpp s Vee

IpP2

Vpp Programming Current

1,2

8.0

mA Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

4.0

mA Vpp = VPPH
. Erasure in Progress

IpP4

Vpp Program Verify Current·

1,2

2.0

5.0

mA Vpp = VpPH
Program Verify in Progress

IpP5

Vpp Erase Verify Current

1,2

2.0

5.0

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

0.8
Vee

+ 0.5

0.45

,mA Vpp = VPPH
Erase Verify in Progress
V
V
V

IOL = 5.8mA
Vee = Vee min

IOH = -2.5 mA
Vee = Veemin

VOH1

Output High Voltage

VID

Ag inteligent Identifier
Voltage

110

Ag intaligent Identifier
Current

VPPL

Vpp During Read-Only
Operations

VPPH

Vpp During Read/Write
Operations

VLKO

Vee Erase/Write Lock Voltage

2.4
11.50

13.00

200

/LA

0.00

6.5

11.40

12.60

2.5
6-18

VID

Note: Erase/Program are
Inhibited when Vpp = VPPL

intJ

28F256A

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

Limits

Notes
Min

Typical

Unit

Test Conditions

Max

III

Input Leakage Current

±1.0

/LA Vee = Vee max
VIN = VeeorVss

ILO

Output Leakage Current

±10.0

/LA Vee = Vee max
VOUT = Vee or Vss

Ices

Vee Standby Current

100

/LA Vee = Veemax
CE = Vee ±0.2V

leel

Vee Active Read Current

mA Vee = Veemax CE = VIL
f = 6 MHz, lOUT = 0 mA

lee2

Vee Programming Current

1,2

1.0

mA Programming in Progress

lee3

Vee Erase Current

1,2

5.0

mA Erasure in Progress

lee4

Vee Program Verify Current

1,2

5.0'

mA Vpp = VPPH
Program Verify in Progress

lee5

Vee Erase Verify Current

1,2

5.0

mA Vpp = VPPH
Erase Verify in Progress

Ipps

Vpp Leakage Current

±10.0

/LA Vpp

IpPl

Vpp Read Current, 10
Current, or Standby Current

200

/LA

±10.0

Vee

Vpp

> Vee

Vpp

Vee

IpP2

Vpp Programming Current

1,2

8.0

mA Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

4.0

mA Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

1,2

2.0

5.0

mA Vpp = VPPH
Program Verify in Progress

IpP5

Vpp Erase Verify Current

1,2

2.0

5.0

mA Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7Vee

VOL

Output Low Voltage

VOHl

Output High Voltage

VOH2

0.8
Vee

+ 0.5

0.45

0.85Vee

V
V
V

IOL = 5.8mA
Vee = Vee min

IOH = - 2.5 mA,
Vee = Vee min
IOH = 100 /LA,
Vee = Vee min

Vee -0.4

VIO

Ag inteligent Identifier
Voltage

110

Ag inteligent Identifier
Current

11.50

13.00
90

6-19

200

V
/LA Ag

VIO

inter

28F256A

DC CHARACTERISTICS-CMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes
Min

Typical

Unit

Test Conditions
Note: Erase/Program are
Inhibited when Vpp = VPPL

Max

VPPL

Vpp During Read-Only
Operations

0.00

6.5

VpPH

Vpp During Read/Write
Operations

11.40

12.60

VLKO

Vee Erase/Write Lock Voltage

CAPACITANCE(3)T
Symbol

25°C, f

2.5

Min

1.0 MHz

Limits

Parameter

Unit

Conditions

Max

CIN

Address/Control
Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

NOTES FOR DC CHARACTERISTICS AND CAPACITANCE:
1. Ali currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, Vpp = 12.0V, T
are valid for ali product versions (Packages and Speeds).
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.

25'e. These currents

AC TESTING LOAD CIRCUIT

.AC TESTING INPUT/OUTPUT WAVEFORM

1.3V

INPUT

2.4~
P
0.45

OUTPUT

-'r-

xx ~:~

~ ~ lN914

TEST POINTS

~-------

3.3k

» TEST POINTS

DEVICE
UNDER
TEST

290243-7
AC Testing: Inputs are driven at:2.5V for a logic '"',. and 0.45 for a
logic "0". Testing measurements are made at 2.0 for a logic "I"
and 0.8 for a logic "0'". Rise/Fall time ,; IOns.

Cl = 100 pF
Cl includes Jig Capacitance

AC Test Conditions
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................... 0.45 and 2.4
Input Timing Reference Level .......... 0.8 and 2.0
Output Timing Reference Level ......... 0.8 and 2.0

6-20

OUT
iCL

= 100pF
290243-8

28F256A

AC CHARACTERISTICS

Read-Only Operations(2)

Versions

Notes

Symbol

Characteristic

tAVAV/tRC

Read Cycle Time

tELQV/tCE

Chip Enable Access Time

28F256A-120

28F256A-150

28F256A-200

Min

120

tAVQV/tACC Address Access Time
tGLQ\,'/to~

Max

Olltpllt Enable

Max

150

Unit

Max

200

120

150

200

120

150

200

Access Time
tELQX/tLZ

Chip Enable to Output
in LowZ

tEHQZ

Chip Disable to Output
in High Z

tGLQX/tOLZ Output Enable to Output
in Low Z

tGHQZ/tDF

Output Disable to Output
in High Z

tOH

Output Hold from Address,
CE, or OE Change(1)

tWHGL

Write Recovery Time
before Read

0
55

0
30

p.s

NOTES:
1. Whichever" occurs first.
2. Rise/Fall time"; 10 [IS.
3. Not 100% tested: characterization data available.
4. Guaranteed by design.
Vee POWER-UP

STANDBY

DEVICE AND
ADDRESS SELECTION

A.DDRESSES

OUTPUTS ENABLED

DATA VALID

STANDBY

Vee POWER DOWN

ADDRESSES STABLE

f-------

t AvAV ('oc) :...'- - - - - - - - - j

cr (E)

OE (0)

tGLQV

iYE(iii)

(tOE)
t ELOY (t cE )

(:~~~~ -i
tELQX

(tLZ)

DATA (DO) _..--;H.;;;IG;;;.H.;;.Z_ _~_ _ _ _ _~fEt«1

Vee

5,OV

VALID OUTPUT

tAVOV (t ACC)

290243-9

Figure 6. AC Waveform for Read Operations

6-21

28F256A

AC CHARACTERISTICS-For Write/Erase/Program Operations(1,2)
Versions

Notes

Symbol

Characteristic

28F256A-120

28F256A-150

Min

tAVAV/twc

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

tWLAX/tAH

Address Hold Time

tOVWH/tOS

Data Set-Up Time

tWHOX/tOH

Data Hold Time

tWHGL

Write Recovery Time
before Read

tGHWL

Max

28F256A-200
Min

Unit

Max

200

/Ls

Read Recovery Time
before Write

/Ls

tELWL/tCS

Chip Enable Set-Up
Time before Write

tWHEH/tCH

Chip Enable Hold Time

tWLWH/twp

Write Pulse Width

120

tWHWL/twPH Write Pulse Width High

150

tWHWH1

Duration of
Programming Operation

/Ls

tWHwH2

Duration of
Eras~ Operation

9.5

1.0

/Ls

Vpp Set-Up Time to
Chip Enable Low

tVPEL

1.0

NOTES: .
1. Read timing parameters during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Rise/Fall time s; 10 ns.
3. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum
specification.

ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter

Notes

28F256A-120
Min

28F256A-150

Typ

Max

Min

Unit

28F256A-200

Typ

Max

Min

Typ

Max

Chip Erase Time

1,3,4

sec

Chip Program Time

.1,2,4

0.5

sec

Erase/Program Cycles

1,5

10,000 100,000

cycles

NOTES:
1. "Typicals" are not guaranteed, but based on a limited number of samples taken from production lots. Data taken at 25°C,

12.0V Vpp.

2. Minimum byte programming time excluding system overhead is 16 p.s program + 6 p.s write recovery), while maximum is
400 p.s/byte (16 p.s x 25 loops allowed by algorithm). Max chip programming is specified lower than the worst case allowed
by the programming algorithm since most bytes program significantly faster than the worst case byte.
3. Excludes OOH Programming Prior to Erasure.
4. Excludes System-Level Overhead.
5. Refer to RR-60 "ETOX" II Flash Memory Reliability Data Summary for typical cycling data and failure rate calculations .

. 6-22

28F256A

99.9

/.,

//
1/

/
/

.f.'"

/'/

V./

60
50
40

...-

.
:

20
10

O. 1

0.5

2.5

0.630.75 0.BB1.01.11.3

3.B

5.0

Chip Program Time (sec)
- - - 12V; 10 kc; 23°C
...... -- .... 11,4V: 10 kc; 70°C
_ .... 12V; 100 kc: 23°C

290243-10

Figure 7. 28F256A Typical Programming Capability

1.9

;

1.8

,1.5

'U'

1.4

.!
~

1.25

I.o

;
.....

1.0

..-

0.9

- -" "
,

;
I

D.6

I
I

.
10

.. .. ."

0.75

0.5

,,
60

J
V

100

110

120

lJO

n:WP (OC)
- - l k Cycles
----. 10k Cycles

•• lOOk Cycles

290243-11

Figure 8. 28F256A Typical Program Time at 12V

6-23

28F256A

99.9

/',1
99

1/ ,,

95
90
80
70

60
50
40

I ,'

,",
'/

,' -

'/
,

J '
/ ,'/"

,,','

,, ,

1// i
1
1/ I,1-.'

2TTiTr

,'/

0.3

0.5

0.7

3.4

~.200

5 6 789 10

CHIP ERASE TIME ( •• c)

- - - 1 2 V ; 10 kC; 230C
----1).4V; 10 kc; O"C
-····--12V; 100 kc; 230C

290243-12

Figure 9_ 28F256A Typical Erase Capability

1.8

1.6

1,04

'0' 1.1

!...

...'";:::
ill
II>

1.0

!!.
%
0

0.8

' ..

.
"

"
........

.........

0.6

"
"
r..... ....

'. ,

' .".

.......... '.
r-... ....

0,04

0.2

20 30

40 50

...

90 100 110 120 130 140

TEMP (OC)
--lkCyclo.
_••• - 10k Cyelet
--lOOk Cycle.

Figure 10. 28F256A Typical Erase Time at 12.0V
6-24

290243-13

Vee POWER-UP &:
STANDBY

SET-UP PROGRAM
COMMAND

PROGRAM COMMAND
LATCH ADDRESS &: DATA

PROGRAM
VERIFY
COMMAND

PROGRAMMING

PROGRAM
VERifiCATION

(

STANDBY/
Vee POWER- DOWN
A ( GOOOO ) A

ADDRESSES

CE(E)

iilC

..J

...

I ELWL .

~
~

~ IWHEH
(leu)

ELWL
I(Ies)

::eIII I

Of: (0)

111

t WHWH 1

t WHGL

Ol!
N

WE (Vi)

o'Jl

~
3

~
(t
)

»
~

OLZ

HIGH-Z

DATA (DQ)

O...J

g.
ijl

tGLOV~j
~

5.0V
Vee

1'----1'1

''----I'I

t ELOX (tLZ )

~~-

12V~
Vpp

2.2J

c::::::J

~
290243-14

~
~
~

2.2J

Vee POWER-UP &:
STANDBY

SET-UP ERASE
COMMAND

ERASE COMMAND

ERASING

ERASE
VERIFY
COMMAND

ERASE
VERIFICATION

STANDBY!
Vee POWER-DOWN

ADDRESSES

CE (E)
"'11

cO"
e..,
III

.....

>1
0

DE (0)

:e
III

III

r\:,

..,0

iYE(W)

0'
..,
m
..,

~'~11
(toE)

N
00
'T1
N

C1I

III
III
III

DATA (DQ)

1111

5.0V

III

0"
::J

Vee
OV

'@
a§J

12V~
Vpp

VpPL

IMI

IF
=
~
290243-15

=
~
~

a§J
~

28F256A

ALTERNATIVE CE-CONTROLLED WRITES
Versions
Symbol

Notes
Characteristic

28F256A-120

28F256A-150

Min

tAVAV

Write Cycle Time

tAvEL

Address Set-Up Time

tELAX

Address Hold Time

&.- .• _ ••

LUVt:.H

n,..t"
Cr..+_1 In Tirno
..... \04u... _ ........ ,... ••••• _

tEHDX

Data Hold Time

tEHGL

Write Recovery Time
before Read

tGHEL

Max

28F256A-200

Min

Unit

Max

200

f.Ls

Read Recover Time
before Write

f.Ls

tWLEL

Write Enable Set-Up Time
before Chip-Enable

tEHwH

Write Enable Hold Time

tELEH

Write Pulse Width

tEHEL

Write Pulse Width High

tVPEL

Vpp Set-Up Time

1.0

f.Ls

120

150

to Chip-Enable Low
NOTE:
1. Chip·Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and_Write-Enable. In
systems where Chip-Enable defines the write pulse width (with a longer Write-Enable timing waveform) aU set-up, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

6-27

Vee POWER-UP &
STANDBY

SET-UP PROGRAM
COMMAND

PROGRAM COMMAND
LATCH ADDRESS & DATA

PROGRAM
VERIFY
COMMI,ND

PROGRAMMING

PROGRAM
VERI FICA TlON

STANDBY/
Vee POWER-DOWN

ADDRESSES

cEo

...
c:

...!'J
(!)

WE (E)

...::sCD

tWLEL

III
(!)

:t:-

DE (Q)

::eIII

-...

t EHGL

tEHEH

\ln~)

<
(!)

(])

N
co

I\)

CE ('ii)

1\1

III

til

...
..."tI
0
ID
...III
0

3
3

"TI

I\)

U1
Ol

tEHDX

-l-l

I--

(t ..... l

tEHDX

DATA (DQ)

:i"

t ELOY

(teE)

1:1

...
(!)

S.OV

!!!.

Vec

0°
::s
en

12V
Vpp
VpPL

~ ~~n

'\§J

\\..--

290243-16

22J

[iiii)

~
~

22J
~

intJ

28F256A

ORDERING INFORMATION

Ip121BIF121S161AI-11121 0

LPACKAGE
P 32-PIN PLASTIC OIP
N 32-LEAD PLCC

=
=

VALID COMBINATIONS:
P28F256A-120
P28F256A-150
P28F256A-200

ACCESS SPEED {ns}
120 ns
1S0n.
200n.

N28F256A-120
N28F256A-150
N28F256A-200

ADDITIONAL INFORMATION
ER-20, "ETOX \I Flash Memory Technology"
ER-24, "The Intel 28F01 0 Flash Memory"
RR-60, "ETOX \I Flash Memory Reliability Data Summary"
AP-316, "Using Flash Memory for In-System Reprogramming
Nonvolatile Storage"
AP-325, "Guide to Flash Memory Reprogramming"

6-29

Order Number
294005
294008
293002
292046
292059

28F512
512K (64K x 8) CMOS FLASH MEMORY

•
•-

Flash Electrical Chip-Erase
- 1 Second Typical Chip-Erase

•

Quick-Pulse Programming™ Algorithm
10 j.Ls Typical Byte-Program
- 1 Second Chip-Program

Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface

•

•
•
•

Noise Immunity Features
- ± 10% Vee Tolerance
- Maximum Latch-Up Immunity
through EPI Processing.

•

ETOXTM II Nonvolatile Flash
Technology
- EPROM-Compatible Process Base
- High-Volume Manufacturing
Experience

•

JEDEC-Standard Pinouts
- 32-Pin Plastic Dip
- 32-Lead PLCC

•
•

10,000 Erase/Program Cycle Minimum
12.0V ±5% Vpp
High-Performance Read
-120 ns Maximum Access Time
CMOS Low Power Consumption
-10 mA Typical Active Current
- 50 j.LA Typical Standby Current
- OW Data Retention Power
Integrated Program/Erase Stop Timers

(See Packaging Spec., Order #231369)

Intel's 28F512 CMOS flash memory offers the most cost·effective and reliable alternative for read/write
random access nonvolatile memory. The 28F512 adds electrical chip·erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM·programmer socket; onboard during subassembly test; in·system during final test; and in·system after-sale. The 28F512 increases
memory flexibility, while contributing to time· and cost·savings.
The 28F512 is a 512·kilobit nonvolatile memory organized as 65,536 bytes of 8 bits. Intel's 28F512 is offered
in 32·pin plastic dip or 32·lead PLCC packages. Pin assignments conform to JEDEC standards for byte·wide
EPROMs.
Extended erase and program cycling capability is designed into Intel's ETOX II (EPROM Tunnel Oxide) process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the 28F512
performs a minimum of 10,000 erase and program cycles well within the time limits of the Quick-Pulse Programming™ and Quick-Erase™ algorithms. .
Intel's 28F512 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 120 nanosecond access time provides no-WAlT-state performance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 /LA translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 rnA
on address and data pins, from -1V to Vee + 1V.
With Intel's ETOX II process base, the 28F512 levers years of EPROM experience to yield the highest levels of
quality, reliability, and cost-effectiveness.

6-30

October 1990
Order Number: 290204-005

inter

28F512

--+
5-+

.I ERASE VOLTAGE

SWITCH

.1 INPUT/OUTPUT
~

TO ARRAY
SOURCE

I--

,)11'\1'-

:...-....
--+

CONTRO~

COt.lt.lAND
REGISTER
INTEGRATED
STOP
TIt.lER

PGt.I VOLTAGE
SWITCH

CHIP ENABLE
OUTPUT ENABLE
LOGIC

...

STB

;::..

r--

7DATA
LATCH

Y-DECODER
STB
15

BUffERS

---+

Y-GATING

OJ:

"
I/'

---+

CI)

1:3

...'"

c
c

X-DECODER

•
•
•
•
---+

524,288 BIT
CELL MATRIX

290204-1

Figure 1. 28F512 Block Diagram

6-31

intJ

28F512

vcc
WE

~, ~ 0
< < z >t

NC
A14
A13

~I~

A14
A13

A11

A 10

A10

N28F512
32 - LEAD PLCC
0.450" x 0.550"
TOP VIEW

Ag
A11

D0 7

D0 6

DO O

D0 7

DOS
D04

Graphic Not to Scale

D0 3

.....

ttl

...

It)

VlOOOO
>·0 Q
0
a

290204-3
290204-2

Figure 2. 28F512 Pin Configurations
Table 1. Pin Description
Symbol
Ao-A15

Name and Function

Type
INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally

latchea during a write cycle.
DOO-DO?

INPUT/OUTPUT

DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri·state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.

INPUT

CHIP ENABLE: Activates the device's controllog!s input buffers,

decoders and sense amplifiers. CE is active low; CE high deselects the
memory device and reduces power consumption to standby levels.
OE

INPUT

OUTPUT ENABLE: Gates the devices output through the data buffers

during a read cycle. OE is active low.
WE

Vpp

INPUT

WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE pulse.
Note: With Vpp ::;: 6.5V, memory contents cannot be altered.
ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.

Vee

DEVICE POWERSUPPLY (5V ± 10%)

Vss

GROUND

NO INTERNAL CONNECTION to device. Pin may be driven or left

floating.

6·32

intJ

28F512

circuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.

APPLICATIONS
The 28F512 flash memory provides nonvolatility
along with the capability to typically perform over
100,000 electrical chip-erasure/reprogram cycles.
These features make the 28F512 an innovative alternative to disk, EEPROM, and battery-backed static RAM. Where periodic updates of code and datatables are required, the 28F512's reprogrammability
and nonvolatility make it the obvious and ideal replacement for EPROM.

Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption - a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable BIOS, system manufacturers can easily accommodate last-minute changes as
revisions are made.

For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.

In diskless workstations and terminals, network traffic reduces to a minimum and systems are instanton. Reliability exceeds that of electromechanical
media. Often in these environments, power interruptions force extended re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communication protocols and primary applications are flash-resident in
each terminal.

Flash memory's f3lectrical chip erasure, byte programmability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a "blank slate" in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new "blank slate".
A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 3 depicts two 28F512s tied to the 80C186 system bus.
The 28F512's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.

For embedded systems that rely on dynamic RAMI
disk for main system memory or nonvolatile backup
storage, the 28F512 flash memory offers a solid
state alternative in a minimal form factor. The
28F512 provides higher performance, lower power
consumption, instant-on capability, and allows an
"execute in place" memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail.
.

With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility,
the 28F512 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs .

The need for code updates pervades all phases of a
system's life - from prototyping to system manufacture to after-sale service. The electrical chip-erasure
. and reprogramming ability of the 28F512 allows in-

6-33

inter

28F512

Vee

80C186
SYSTEt.4 BUS
A1-A16

----------+I

DQO-DQ7

+----------1

Vee

Ao-A 15

28F512

28F512
t.4CS1 _ _ _ _ _ _ _ _ _

I - -.....

iiHE

>-------1~ WE

~---------~oc
290204-5

Figure 3. 28F512 in a 80C186 System
standard microprocessor read tiniings output array
data, access the inteligent Identifier codes, or output
data for erase and program verification.

PRINCIPLES OF OPERATION
Flash·memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F512 introduces a command register to manage
this new functionality. The command register allows
for: 100% TIL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.

Integrated Stop Timer
Successive command write cycles define the duration of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these, operations; thus eliminating the need for maximum program/.erase timing
specifications. Programming and erase pulse
durations are minimums only. When the stop timer
terminates a program or erase operation, the device
enters an inactive state and remains inactive until
r7ceiviIJg the appropriate, verify or reset command.

In the absence of high voltage on the Vpp pin, the
28F512 is a read·only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and inteligent
IdentifierTM operations.
The same EPROM read, standby, and' output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasure and programming of the device. All
functions associated with altering memory contents-inteligent Identifier, erase, erase verify, program, and program verify-are accessed via the
command register.

Write Protection
The command register is only active when Vpp is at
high voltage. Depending upon the application, the.
system designer may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When Vpp = VPPL, the contents of the register default to the read command,
making the 28F512 a read-only memory. In this
mode, the memory contents cannot be altered.

Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming or erase operations. With
the appropriate command written to the register,
6-34

inter

28F512

Table 2. 28F512 Bus Operations
Pins

Vpp(1)

Read

VpPL

VIL

VIH

Data Out

Output Disable

OQO-OQ7

Operation

READ-ONLY

READ/WRITE

VPPL

VIL

VIH

Tri-State

Standby

VPPL

VIH

Tri-State

inteligent IdentifierTM (Mfr)(2)

VPPL

VIL

VID(3)

VIL

VIH

Data = 89H

inteligent IdentifierTM (Device)(2)

VPPL

VIH

VID(3)

VIL

VIH

Data = B8H

Read

VPPH

VIL

VIH

DataOut(4)

Output Disable

VPPH

VIL

VIH

Tri-State

Standby(5)

VPPH

VIH

Tri-State

Write

VPPH

VIL

VIH

VIL

Data In(6)

NOTES:
1. Refer to DC Characteristics. When Vpp = VpPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VID is the inleligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with Vpp = VPPH may access array data or the inleligent Identifier™ codes.
5. With Vpp at high voltage, the standby current equals leo + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.

Or, the system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever VCC is below the write
lockout voltage VLKO. (See Power Up/Down Protection). The 28F512 is designed to accommodate either design practice, and to encourage optimization
of the processor-memory interface.

Output Disable
With Output-Enable at a logic-high level (VIH), output
from the device is disabled. Output pins are placed
in a high-impedance state.
Standby
With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F512's circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable signal.
If the 28F512 is deselected during erasure, programming, or program/erase verification, the
device draws active current until the operation is
terminated.

BUS OPERATIONS
Read
The 28F512 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CE) is the power control and
should be used for device selection. Output-Enable
(OE) is the output control and should be used
to gate data from the output pins, independent of
device selection. Refer to AC read timing
waveforms.

intellgent IdentlflerTM Operation
The inteligent Identifier operation outputs the manufacturer code (89H) and device code (B8H). Programming equipment automatically matches the device with its proper erase and programming algorithms.

When Vpp is high (VPPH), the read operation can be
used to access array data, to output the inteligent
Identifier™ codes, and to access data for program/
erase verification. When Vpp is low (Vppd, the read
operation can only access the array data.

6-35

inter

28F512

used to store the command, 'along with address and
data information needed to execute the command.
The command register is written by bringing WriteEnable to a logic-low level (VIL>, while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.

The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F512 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the device code (B8H).

Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.

Write

COMMAND DEFINITIONS

Device erasure arid programming are accomplished
via the command register, when high voltage is ap- "
plied to the Vpp pin. The contents of the register
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.

When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.

The command register itself does not occupy an addressable memory location. The register is a latch

Placing high voltage on the Vpp pin enables read/
write operations. Device operations are selected by
writing specific data patterns into the command regisler. Table 3 defines these 2BF512 register
commands.

Table 3. Command Definitions
Command

Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)

Read Memory

Write

OOH

Read inteligent IdentifierTM Code(4)

Write

90H

Read

(4)

Set-up Erase/Erase(5)

Write

20H

Write

20H

Erase Verify(5)

Write

AOH

Read

EVD

Set-up Program/Program(6)

Write

40H

Write

Program Verify(6)

Write

COH

Read

PVD

Reset(?)

Write

FFH

Write

FFH

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID = Data read from location IA during device identification (Mfr = 89H, Device = B8H).
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read inteligent ID command, two read operations access manufacturer and device codes.
5. Figure 5 illustrates the Quick-Erase™ algorithm.
6. Figure 4 illustrates the Quick-Pulse Programming™ algorithm.
7. The second bus cycle must be followed by the desired command register write.

6-36

(4)

28F512

of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.

Read Command

While Vpp is high, for erasure and program!lling,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.

Erase-Verify Command

The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing AOH into the command register. The address
for the byte to be verified must be supplied as it is
latched on the falling edge of the Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.

Tilt:: u~rC1uii liUllit:'-li~ 01 the ,t:Qisttil LipGi"i Vpp puwv·
er-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 2BF512, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.

The 2BF512 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.

inteligent IdentifierTM Command

Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, mUltiplexing high voltage onto address lines is not a desired system-design practice.

In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 5, the Quick-Erase™ algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 2BF512.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.

The 2BF512 contains an inteligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address OOOOH retrieves the manufacturer code of B9H. A read cycle
from address 0001 H returns the device code of
BBH. To terminate the operation, it is necessary to
write another valid command into the register.

Set-up Program/Program Commands
Set-up Erase/Erase Commands

Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation ..

Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.

Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write-Enable ·pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
. .
parameters.

To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (Le., Erase-Verify Command).
This two-step sequence of set-up followed byexecution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pin. In the absence

6-37

intJ

- 28F512

Program-Verify Command

The 28F512 is programmed on a byte-by-byte basis.
'Byte programming may occur sequentially or at random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F512 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 4,
the 28F512 Quick-Pulse Programming™ algorithm,
illustrates how commands are combined with bus
operations to perform byte programming. Refer to
AC Programming Characteristics and Waveforms for
specific timing parameters.

greatly reduces oxide stress and the probability of
failure-increasing time to wearout by a factor of
100,000,000.
The 28F512 is specified for a minimum of 10,000
program/erase cycles. The device is programmed
and erased using Intel's Quick-Pulse ProgrammingTM and Quick-Erase™ algorithms. Intel's algorithmic approach uses a series of operations (pulses), along with byte verification, to completely and
reliably erase and program the device.
For further information, see Reliability Report RR-60
(ETOX-II Reliability Data Summary).
QUICK-PULSE PROGRAMMINGTM ALGORITHM

The Quick-Pulse Programming algorithm uses programming operations of 10 fJ.s duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with Vpp at high Voltage. Figure 4 illustrates the Quick-Pulse Programming algorithm.

Reset Command

A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.

QUICK-ERASETM ALGORITHM

Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming™ algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F512 is erased when shipped from the factory.
Reading FFH data from the device would immediately be followed by device programming.

EXTENDED ERASE/PROGRAM CYCLING

EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubledan expensive solution.

For devices being erased and reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state
(Data = OOH). This is accomplished, using the
Quick-Pulse Programming algorithm, in approximately one second.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 5 illustrates the Quick-Erase algorithm.

Intel has designed extended cycling capability into
its ETOX II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately 2 MV /
cm lower than EEPROM. The lower electric field
6-38

infef

28F512

(4) Start

Bus
Operation

Programming

Apply
VpPH [I]

PLSCNT -0

I
I

J
WRITE Set-up
Program Cmd

Write Program

Cmd (A/D)

Standby

Write Program
Verify Cmd

Initialize Pulse-Count

I
I

from Device

Write

Set-up
Program

Data = 40H

Write

Program

Valid Address/Data

Duration of Program
Operation (tWHWH1)

Standby

Write

r Time Out 61's I

-+
Read Data

Program(2)
Verify

y
iI
II

Increment

Inc
PLSCNT
=251

Data = COH; Stops Program
Operation(3)

Standby

tWHGL

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected

Verify
Data

Comments

Wait for Vpp Ramp to VPPH(1)

LTIme Out IOl's I

Command

Lost

Address

1
y

I
I

Write
Read Cmd

Apply
VpPL [I]

I
I I

(Prog rommln9)
Completed

Write
Apply
VpPL [I]

Standby

Read

Data = OOH, Resets the
Register for Read Operati.ons
WaitforVpp Ramp to VPPL(1)

( Program)
Error

290204-6
NOTES:
1. See DC Characteristics for value of VpPH and VpPL.
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command.

3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.

Figure 4. 28F512 Quick-Pulse Programming™ Algorithm

6-39

inter

28F512

Bus
Operation

Command

Comments
Entire memory must
before erasure

OOH

Use Quick-Pulse
Programming™ Algorithm
(Figure 4)
Standby

Wait for Vpp Ramp to VPPH(1)

Initialize Addresses and
Pulse-Count

Write

Set-up
Erase

Data

20H

Write

Erase

Data

20H

Standby
Write

Duration of Erase Operation
(tWHWH2)
Erase(2)
Verify

Standby

tWHGL

Read

Read Byte to Verify Erasure

Standby

Compare Output to FFH ,
Increment Pulse-Count

Write

Read

Standby

290204-7
NOTES:
1. See DC Characteristics for value of VPPH and VPPL.
2. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.

Addr = Byte to Verify;
Data = AOH;-Stops Erase
Operation(3)

Data = OOH. Resets the
Register for Read Operations
Wait for Vpp Ramp to Vppd1)

3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.

Figure 5. 28F512 Quick-Erase™ Algorithm

6-40

28F512

Power Up/Down Protection

DESIGN CONSIDERATIONS

The 28F512 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F512 is indifferent
as to which power supply, Vpp or Vee, powers up
first. Power supply sequencing is not required. Internal circuitry in the 28F512 ensures that the command register is reset to the read mode on power
up.

Two-Line Output Control
Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.

A system designer must guard against active writes
for Vee vo~es above VLKO when Vpp is active.
Since both WE and CE must be low for a command
write, driving either to VIH will inhibit writes. The control register architecture provides an added level of
protection since alteration of memory contents only
occurs after successful completion of the two-step
command sequences.

To efficiently use these two control inputs, an address-decoder output should drive chip-enable,
while the system's read signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power standby condition.

28F512 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F512 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F512.

Power Supply Decoupling
Flash-memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current (Ieel issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.

Table 4. 28F512 Typical Update
Power Disslpation(4)

Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 JLF ceramic capacitor
connected between Vee and Vss, and between Vpp
and Vss.

Notes

Power Dissipation
(Watt-Seconds)

Array Program/
Program Verify

0.085

Array Erase/
Erase Verify

0.092

One Complete Cycle

0.262

Operation

Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 JLF electrolytic capacitor should be placed at the array's power supply
connection, between Vee and Vss. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.

NOTES:
1. Formula to calculate typical Program/Program Verify
Power = [Vpp x # Bytes x Typical # Prog Pulses
(tWHWH1 x IpP2 Typical + tWHGL x IpP4 Typical)] +
[Vee x # Bytes x Typical # Prog Pulses (twHWH1 x
ICC2 Typical + tWHGL x ICC4 Typical).
2. Formula to calculate typical Erase/Erase Verify Power
= [Vpp(lpP3 Typical x tERASE Typical + IpP5 Typical x
tWHGL x # Bytes)] + [VCC(lCC3 Typical x tERASE Typical + ICC5 Typical x tWHGL x # Bytes)].
3. One Complete Cycle = Array Preprogram + Array
Erase + Program.
4. "Typicals" are not guaranteed, but based on a limited
number of samples from production lots.

Vpp Trace on Printed Circuit Boards
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the Vee power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.

6-41

28F512

Vee Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Output Short Circuit Current ............. 100 mA(4)

ABSOLUTE MAXIMUM RATINGS*
Operating Temperature
During Read .................. O·C to + 70·C(1)
During Erase/Program . ~ ......... O·C to + 70·C
Temperature Under Bias ......... -1 O·C to + 800C
Storage Temperature ....•..... - 65·C to + 125·C

NOTICE: This is a production data sheet. The specifi·
cations are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex·
tended exposure beyond the "Operating Conditions"
may affect device reliability.

Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Voltage on Pin A9 with
Respect to Ground ....... - 2.0V to + 13.5V(2, 3)
Vpp Supply Voltage with
Respect to Ground
During Erase/Program .... - 2.0V to

+ 14.0V(2, 3)

NOTES:

1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum De voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for periods less than 20 ns.
3. Maximum De voltage on A9 or Vpp may overshoot to + 14.0V for periods less than 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING CONDITIONS
Symbol

Limits

Parameter

Operating Temperature

Vee

Vee Supply Voltage

Unit

Comments

·C

For Read·Only and
Read/Write Operations

5.50

Min

Max'

0
4.50

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE
Symbol

Parameter

Notes

Limits
Min

Typ

Max

Unit

Test Conditions

III

Input Leakage Current

±1.0

/LA

Vee = Vee Max
VIN = VeeorVss

ILO

Output Leakage Current

±10.0

p.A

Vee = Vee Max
VOUT = Vee or Vss

lees

Vee Standby Current

1.0

Vee = Vee Max
CE = VIH

lee1

Vee Active Read Current

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

ICC2

Vcc Programming Current,

1,2

1.0

Programming in Progress

lec3

Vec Erase Current

1,2

5.0

Erasure in Progress

leC4

Vee Program Verify Current

1,2

5.0

Vpp = VPPH
Program Verify in Progress

leC5

Vce Erase Verify Current

1,2

5.0

Vpp = VpPH
Erase Verify in Progress

IpPS

VPP Leakage Current

±10.0

/LA

Vpp:5: Vee

IpP1

VPP Read Current, Standby
Current, or 10 Current

200

/LA

Vpp> Vec

±10.0
6-42

Vpp:5: Vce

inter

28F512

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes
Min

Unit

Typ

Max

Test Conditions

IpP2

VPP Programming Current

1,2

8.0

rnA

VPP = VPPH
Programming in Progress

IpP3

VPP Erase Current

1,2

4.0

rnA

VPP = VPPH
Erasure in Progress

IpP4

VPP Program Verify Current

1,2

2.0

5.0

rnA

VPP = VpPH
Program Verify in Progress

IpP5

VPP Erase Verify Current

1,2

2.0

5.0

rnA

VPP = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

0.8

2.0

VIH

Input High Voltage

VOL

Output Low Voltage

VOHl

Output High Voltage

VID

Ag inteligent IdentifierTM
Voltage

Vee

+ 0.5

0.45
2.4
11.50
90

V
V

IOL = 5.8 rnA
Vee = Vee Min

IOH = -2.5 rnA
Vee = Vee Min

13.00

liD

Ag inteligent Identifier Current

200

/LA

VPPL

VPP during Read-Only
Operations

0.00

6.5

VPPH

VPP during Read/Write
Operations

11.40

12.60

VLKO

Vee Erase/Write Lock Voltage

= VID

NOTE: Erase/Program are

Inhibited when VPP

2.5

= VPPL

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

Limits

Notes
Min

Typ

Unit

Test Conditions

Max

III

Input Leakage Current

±1.0

/LA

Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

±10.0

p.A

Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

100

p.A

Vee = Vee Max
CE = Vee ±0.2V

leel

Vee Active Read Current

rnA

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 rnA

lee2

Vee Programming Current

1,2

1.0

rnA

Programming in Progress

lee3

Vee Erase Current

1,2

5.0

rnA

Erasure in Progress

lee4

Vee Program Verify Current

1,2

5.0

rnA

VPP = VpPH
Program Verify in Progress

lee5

Vee Erase Verify Current

1,2

5.0

rnA

VPP = VPPH
Erase Verify in Progress

6-43

intJ

28F512

DC CHARACTERISTICS-CMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes
Min

Ipps

VPP Leakage Current

IpP1

Vpp Read Current, 10
Current, or Standby
Current

Unit

Typ

T~st

Conditions

Max
±10.0

/LA

Vpp';:; Vee

200

/LA

Vpp> Vee

±10.0

Vpp';:; Vee

IpP2

Vpp Programming Current

1,2

8.0

Vpp= VPPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

4.0

Vpp = VPPH
Erasure in Progress

IpP4

VPP Program Verify Current

1,2

2.0

5.0

VPP = VPPH
Program Verify in Progress

IpP5

VPP Erase Verify Current

1,2

2.0

5.0

VPP = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

VOH1

Output High Voltage

Vee

+ 0.5

0.45

0.85 Vee

VIO

Ag inteligent Identifier
Voltage

110

Ag inteligent Identifier
Current

VPPL

VPP during Read-Only
Operations

VPPH
VLKO

IOH = -2.5 mA,
Vee = Vee Min
IOH = -100/LA,
Vee = Vee Min

Vee - 0.4

VOH2

IOL = 5.8mA
Vee = Vee Min

11.50

13.00

Ag = VIO

200

./LA

Ag = VIO

0.00

6.5

VPP during Read/Write
Operations

11.40

12.60

Vee Erase/Write Lock
Voltage

2.5

NOTE: Erase/Program
are Inhibited When
VPP = VPP·L

CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol

Parameter

Limits

Notes
Min

Unit

Conditions

Max

CIN

Address/Control Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, VPP = 12.0V; T =
currents are valid for all product versions (packages and speeds).
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.

6-44

+ 25°C.

These

28F512

AC TESTING INPUT/OUTPUT WAVEFORM

AC TESTING LOAD CIRCUIT

2.4

.!.:~

INPUT

- ...

0.45

.ol~ lN914

~:~

TEST POINTS

290204-B

AC Testing: Inputs are driven at 2.4V for a logic "1" and O.4SV for
a logic "0". Testing measurements are made at 2.0V for a logic
"1" and O.BV for a logic "0". Rise/Fall time,; 10 ns.

DEVICE

UNDER

I--t--o OUT

I~"f

I-L

3.3K

=100pF
290204-9

CL ~ 100 pF
CL includes Jig Capacitance

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................ 0.45Vand 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ....... 0.8V and 2.0V

AC CHARACTERISTICS-Read-Only Operations(2)
Versions
Symbol

Notes
Characteristic

28F512·120

28F512·150

28F512·200

Min

Max

Unit

Max

tAVAV/tRC

Read Cycle Time

tELQv/tCE

Chip Enable Access Time

120

150

200

tAVQV/tACC

Address Access Time

120

150

200

tGLQV/tOE

Output Enable Access Time

tELQXltLZ

Chip Enable to Output in Low Z

120

150

tEHQZ

Chip Disable to Output in High Z

tGLQXltOLZ

Output Enable to Output in
LowZ

tGHQz/tDF

Output Disable to Output in
HighZ

tOH

Output Hold from Address, CE,
or OE Change(l)

tWHGL

Write Recovery Time
before Read

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time:;; 10 ns.
3. Not 100% tested: characterization data available.
4. Guaranteed by design.

6-45

200

55
0

0
55

55
0

0
30

ns
55

0
35

ns
ns

IJ-s

(
Vee POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENABLED

DATA VALID

ADDRESSES

STANDBY

---

Vee POWER-DOWN

ADDRESS STABLE

--t AVAV (t RC )

."
ce·
I:
...

CE (E)

(II

---

»
0
~

-3
<
(II

.i>.
0>

OE (G)

til

...0

:2J

1 t WHGL 1

.....
N

(II

t GLOV (tOE)

I»

J.------

"iii

t ELOV (tCE)

'I
tOH

t GLOX (tOLZ)--I

(II

::J

."
UI

WE (W)

Il.

---

t ELOX (t LZ )

HIGH Z

DATA (DO)

I'~~lll

til

s.OV
Vec

I----

t AVOV (t ACC)

VALID OUTPUT

HIGH Z

ov
290204-10

intJ

28F512

AC CHARACTERISTICS-Wrile/Erase/Program Operations(1, 2)
Versions

Notes

Symbol

Characteristic

tAvAv/twc

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

tWLAX/tAH
tD'./N!-!/tDS

28F512-120

28F512-150

28F512-200

Min

Max

Unit

Max

120

150

200

Address Hold Time

DRtR Set-up Time

tWHOX/tOH

Data Hold Time

tWHGL

Write Recovery Time before Read

,""s

tGHWL

Read Recovery Time before Write

,""S

tELWL/tCS

Chip Enable Set-Up Time before
Write

tWHEH/tcH

Chip Enable Hold Time

tWLWH/twp

Write Pulse Width

tWHWL/twPH

Write Pulse Width High

tWHWH1

Duration of Programming Operation

tWHWH2

Duration of Erase Operation

tVPEL

Vpp Set-Up Time to Chip Enable Low

,..s

9.5

1.0

,""S

NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Rise/Fall time,;; 10 ns.
3. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum
specification.

ERASE AND PROGRAMMING PERFORMANCE
Limits
28F512-120

28F512-200

Notes

Typ

Max

Typ

Max

Typ

Max

Chip Erase
Time

1,3,4

Sec

Chip
Program
Time

1,2,4

6.25

Sec

Min

Erasel

1,5

10,000

100,000

28F512-150

Unit

Parameter

Min

10,000

100,000

Min

10,000

100,000

Cycles

Program
Cycles

NOTES:
1. "Typicals" are not guaranteed, but based on a limited number of samples from production lots. Data taken at 2SoC, 12.0V
Vpp.
2. Minimum byte programming time excluding system overhead is 16
(10 p.s program + 6 P.s write recovery), while
- maximum is 400 p.s/byte (16 p.s x 2S loops allowed by algorithm). Max chip programming time is specified lower than the
worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte.
3. Excludes OOH Programming Prior to Erasure.
4. Excludes System-Level Overhead.
S. Refer to RR-60 "ETOXTM II Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.

,..S

6-47

28F512

3.75

2.75

2.5

...
~

.o~225

..... 1--" ~

1.75

1.25
I

V
V
."
~

,
,,

o w

"
I

/
,/

... --..-

TEMP (OC)
-1kCycles
---- 10k Cycl..
----- 1OOk Cyc~.

290204-14

Figure 7. 28F512 Typical Program Time at 12V
99.9

90
80

50
40

30
20
10

.
..
.
.
/

"""

./...'"

././
.

V,"
..
.
.
.....

;

O.1

1 '1.25 1.51.7522.252.5

7.5

Chlp Program TIm. (sec)

- - - 1 2 V ; 10 kc; 230C
·-----·11.4V; 10 kc; 70CC
- - - - 12V; 100 kc; 23CC

. Figure 8. 28F512 Typical Programming Capability
6-48

290204-15

intJ

28F512

1.9

1.8

1.7

.
\

1.6

1.5

1.4

~,.

1.3

;:
~

i:l

..
.,

1.2

...

1.1

1.0

. .,
",

., ,

"',-

.. ,

r--...

0..9

.
"
"

........

0.8

.....
'.
'.
. . . . 1"- . '. .

"- I'-....

0.7

0.6

0.5

l00lmlWl~l~

TEMP (OC)

--1kCycles
----10k Cycles
... __ • 100k Cycles

290204-16

NOTE:
Does not include Pre-Erase program.

Figure 9. 28F512 Typical Erase Time at 12V
99.9

'/ , "

//
I

1/ "

0. 1
0.3

I,'

40
30

,'j

" I

' ,

I ""

1//'
!I
II

o.s

0.7

2TTTli E
3

200

5 6 7 8 9 10

CHIP ERASE TIME (sec)
- - - 12V: 10 kc: 230C
_ •• 11.4V; 10 kc; OOC
------- 12V; 100 kc; 230C

NOTE:
Does not include Pre-Erase program.

Figure 10. 28F512 Typical Erase Capability

6-49

290204-17

Vee POWER-UP &:
STANDBY

SET-UP PROGRAM
COMMAND

PROGRAM COMMAND
LATCH ADDRESS &: DATA

PROGRAMMING

PROGRAM
VERIFY
COMMAND

PROGRAM
VERIFICATION

STANDBY/
Vee POWER-DOWN

(

ADDRESSES

eg."'11 I
Cil
....
....

CE (E)

>
o
~I

OE (G)

~!I .,,~ I I ~ r=\ r 4 J
o
cc
iil

I-l 1"')1 \ II ~

3
3

~. I

o
"0
1\1

iil

DATA (DQ)

~,~
Vee

",)

I--- tELQV

12.0V

Vpp
VpPL

290204-11

intJ

28F512

ALTERNATIVE CE·CONTROLLED WRITES

28F512·120

28F512·150

28F512·200

Symbol

Characteristic

Min

tAVAV

Write Cycle
Time

120

150

200

tAvEL

Address SetUpTime

tELAX

Address Hold
Time

t:lU

-II:>

tDVEH

DataSet-Up
Time

tEHDX

Data Hold
Time

tEHGL

Write
Recovery Time
before Read

JLs

tGHEL

Read
Recovery Time
before Write

JLs

tWLEL

Write Enable
Set-UpTime
before Chip
Enable

tEHWH

Write Enable
Hold Time

tELEH

Write Pulse
Width

tEHEL

Write Pulse
Width High

tVPEL

VppSet-Up
Time to Chip
Enable Low

1.0

JLs

Versions

Notes

Max

Unit

Max

NOTE:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.

6-51

Vee POWER-UP &.
STANDBY

SET-UP ERASE
COMMAND

ERASE
VERIFY
COMMt,ND

ERASING

ERASE COMMAND

ERASE
VERIFICATION

STANDBY/
Vee POWER-DOWN

ADDRESSES

cr (E)
"T1

....

cS'
C

(II

!'l

C')

DE (G)

::E

III

-.
-

1-1

<
(II

3
tn VI
I\)

WE (iii)

GHWL
tt

tWHWH2

t WHGL

"T1

.....

~
~I

I I tGLQV

---I I--

III
VI

tWHDX

H I--

tWHDX

\ tOEi

tWHDX

(II

HIGH Z
DATA (DQ)

(II

a0'

::::I
VI

S.OV
Vee
OV
t VPEL
12.0V
Vpp
VpPL

f-.

~
290204-12

Vee POWER-UP &:
STANDBY

SET-UP PROGRAM
COMMAND

PROGRAM COMMAND
LATCH ADDRESS &: DATA

PROGRAMMING

PROGRAM
VERIFY
COMMAND

PROGRAM
VERIFICATION

STANDBY!
Vee POWER-DOWN
---.A ( 0 0 0 ' A

ADDRESSES

"II

cO'
I:

iil

... I
~

WE (E)

..it>
:::l

!CD

>I
o

II.

(0)

cr~)

~ ~

r'- " " t:-]- 't.
A7

AIO

0°7

00 0

DOs

DO,

0°5

0°2

D0.

Vss

DO,

A'3

N28FOIO
32 - LEAD PLCC
U.4:JU" x u.55u·
TOP VIEW

A.
A3

A,.

>'dI3: ~

A.
A"

A2
A,

AIO

00 0

0°7

C'oI

fI'I

•

0011)0000
C
C > Q C
0
C

290207-3
290207-2

A"
A.
As

AIO

CE
07

A'3
A,.
NC

Os
05
D.
03
Vss
O2

STANDARD PINOUT
E28F'010
32-LEAD TSOP
0.31" X 0.72"
TOP VIEW

WE
vee
Vpp
AU
A,s
A12
A7
As
As
A.

0,
Do
Ao
A,
A2
A3

290207-17

OE
AIO

CE
07
Os
05
D.
03
Vss
O2
0,
Do
Ao
A,
A2
A,

1\7
2

•
5

REVERSE PINOUT
F'28F'010
32-LEAD TSOP
0.31" X 0.72"
TOP VIEW

14
IS
16

32
31
30
29
28
27
26
25
2.
23
22
21
20
19
18
17

AU
A.
AS
A'3
A,.
NC

WE
Vee
VPP
A,s
A,s
A'2
A7
AS
As
A.

290207-18

Figure 2. 28F010 Pin Configurations

6-57

28F010

APPLICATIONS
The 28F010 flash memory provides nonvolatility
along with the capability to typically perform over
100,000 electrical chip-erasure/reprogram cycles.
These features make the 28F010 an innovative alternative to disk, EEPROM, and battery-backed static RAM. Where periodic updates of code and datatables are required, the 28F010's reprogrammability
and nonvolatility make it the obvious and ideal replacement for EPROM.
Primary applications and operating systems stored
in flash eliminate the.slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption - a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable BIOS, system manufacturers can easily accommodate last-minute changes as
revisions are made.
In diskless workstations and terminals, network traffic reduces to a minimum and systems are instanton. Reliability exceeds that of electromechanical
media. Often in these environments, power interruptions force extended re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communication protocols and primary applications are flash-resident in
each terminal.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F010 flash memory offers a solid
state alternative in a minimal form factor. The
28F010 provides higher performance, lower power
consumption, instant-on capability, and allows an
"execute in place" memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail.

Material and labor costs associated with code
changes increases at higher levels of system integration - the most costly being code updates after
sale. Code "bugs", or the desire .to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the removal of EPROM components or entire boards. With
the 28F010, code updates are implemented locally
via an edge-connector, or remotely over a communcation link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory's electrical chip erasure, byte programmability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a "blank slate" in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new "blank slate".
A high degree of on-chip feature integration simplifies memory-to-processor interfaCing. Figure 4 depicts two 28F010s tied to the 80C186 system bus.
The 28F010's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.
.
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. With standard and reverse pin configurations, TSOP reduces
the number of board layers and overall volume necessary to layout multiple 28F010s. TSOP is particularly suited for portable equipment and applications
requiring large amounts of flash memory. Figure 3
illustrates the TSOP Serpentine layout.
With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility,
the 28F010 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs.

The need for code updates pervades all phases of a
system's life - from prototyping to system manufacture.to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F010 allows incircuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.

6-58

28F010

fn nnnnn nnnn no~

IIIIIIIII!!!

lIn!!1m11m

IIII i i
....00

....00

......

i jill

....

......

N
......

LLI

-----.. WE
1---"'"

RD----------+loc
290207-4

Figure 4. 28F010 In a 80C186 System
needed for programming or erase operations. With
the appropriate command written to the register,
standard micr()processor read timings output array
data, access the inteligent Identifier codes, or output
data for erase and program verification.

PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F010 introduces a command register to manage
this new functionality. The command register allows
for: 100% TIL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.

Integrated Stop Timer
Successive command write cycles define the durations of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command.

In the absence of high voltage on the Vpp pin, the
28F010 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and inteligent
Identifier™ operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasure and programming of the device. All
functions associated with altering memory contents-inteligent Identifier, erase, erase verify, program, and program verify-are accessed via the
command register.

Wri.te Protecticm
The command register is only active when Vpp is at
high Voltage. Depending upon the application, the
system designer may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When Vpp = VPPL, the con-

Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry: Write
cycles also internally latch addresses and data

6-60

28F010

Table 2. 28F010 Bus Operations
Pins

Vpp(l)

DQo-DQ7

Operation
VPPL

VIL

VIH

Data Out

Output Disable

VPPL

VIL

VIH

Tri-State

Standby

VPPL

VIH

Tri-State

inteligent IdentifierTM (Mfr)(2)

VPPL

VIL

VIO(3)

VIL

VIH

Data = 89H

VIL

V IL

VIH

Data = B4H

Read

READ-ONLY

READ/WRITE

inteligent IdentifierTM (Device)(2)

VPPL

VIH

VIO(3)

Read

VPPH

VIL

VIH

Data Out(4)

Output Disable

VPPH

VIL

VIH

Tri-State

Standby(5)

VPPH

VIH

Tri-State

Write

VPPH

VIL

VIH

VIL

Data In(6)

NOTES:
1. Refer to DC Characteristics. When Vpp = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VID is the inteligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with Vpp = VPPH may access array data or the inteligent IdentifierTM codes.
5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH'

tents of the register default to the read command,
making the 28F010 a read-only memory. In this
mode, the memory contents cannot be altered.

erase verification. When Vpp is low (Vppd, the read
operation can only access the array data.

Or, the system designer may choose to "hardwire"

Output Disable

Vpp, making the high voltage supply constantly

With Output-Enable at a logic-high level (VIH), output
from the device is disabled. Output pins are placed
in a high-impedance state.

available. In this case, all Command Register functions are inhibited whenever VCC is below the write
lockout voltage VLKO. (See Power Up/Down Protection) The 28F010 is designed to accommodate either design practice, and to encourage optimization
of the processor-memory interface.

Standby
With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F010's circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable signal.
If the 28F010 is deselected during erasure, programming, or program/erase verification, the
device draws active current until the operation is
terminated.

BUS OPERATIONS
Read
The 28F01 0 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CE) is the power control and
should be used for device selection. Output-Enable
(OE) is the output control and should be used to
gate data from the output pins, independent of device selection. Refer to AC read timing waveforms.

inteligent IdentifierTM Operation
The inteligent Identifier operation outputs the manufacturer code (89H) and device code (B4H). Programming equipment automatically matches the device with its proper erase and programming algorithms.

When Vpp is high (VPPH), the read operation can be
used to access array data, to output the inteligent
Identifier™ codes, and to access data for program/

6-61

inter

28F010

With Chip-Enable and Output-Enable at a logic low
level, raising A9 to high voltage VID (see DC Characteristics) activates the operation. Data read from locations OOOOH and 0001 H represent the manufacturer's code and the device code, respectively.
The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F010 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the device code (B4H).

used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WriteEnable to a logic-low level (VIL>, while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.

Write

COMMAND DEFINITIONS

Device erasure and programming are accomplished
via the command register, when high voltage is applied to the Vpp pin. The contents of the register
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.

When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.

The command register itself does not occupy an addressable memory location. The register is a latch

Placing high voltage on the Vpp pin enables read/
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F010 register
commands.

Table 3. Command Definitions
Command

Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)

Read Memory

Write

OOH

Read inteligent Identifier™
Codes(4)

Write

90H

Read

(4)

Set-up Erase/Erase(5)

Write

20H

Write

20H

Erase Verify(5)

Write

AOH

Read

EVD

Set-up Program/Program(6)

Write

40H

Write

Program Verify(6)

Write

COH

Read

PVD

Reset(7)

Write

FFH

Write

FFH

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID = Data read from location IA during device identification (Mfr = 89H, Device = B4H).
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read inteligent ID command, two read operations access manufacturer and device codes.
5. Figure 6 illustrates the Quick-Erase™ Algorithm.
6. Figure 5 illustrates the Quick-Pulse Programming™ Algorithm.
7. The second bus cycle must be followed by the desired command register write.

6-62

inter

28F010

of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.

Read Command

While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for· reads until the command register contents are altered.

Erase-Verify Command

The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify ope·ration is initiated by
writing AOH into the command register. The address
for the byte to be verified must be supplied as II IS
latched on the falling edge of the Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.

The deiauii conieni::; u( ii,,,, ,"'yi;;,.... UPUI' 'v'pp jju..... er-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F010, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.

The 28F010 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last. address is accessed.

inteligent Identifier™ Command

Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising A9 to a high voltage. Ho",{ever, multiplexing high voltage onto address lines is not a desired system-design practice.

In the case where the data read is not FFH, another
erase operation is performed. (Ref~r to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 6, the Quick-Erase™ algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F010.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.

The 28F010 contains an inteligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address OOOOH retrieves the manufacturer code of 89H. A read cycle
from address 0001 H returns the device code of
B4H. To terminate the operation, it is necessary to
write another valid command into the register.

Set-up Program/Program Commands
Set-up Erase/Erase Commands

Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.

Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.

Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses 'are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters.

To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (Le., Erase-Verify Command).
This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pin. In the absence
6-63

inter

28F010

Program-Verify Command

The 28F01 0 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F010 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 5,
the 28F010 Quick-Pulse Programming™ algorithm,
illustrates how commands are combined with bus
operations to perform byte programming. Refer to
AC Programming Characteristics and Waveforms for
specific timing parameters.

field greatly reduces oxide stress and the probability
of failure-increasing time to wearout by a factor of
100,000,000.
The 28F010 is specified for a minimum of 10,000
program/erase cycles. The device is programmed
and erased using Intel's Quick-Pulse ProgrammingTM and Quick-Erase™ algorithms. Intel's algorithmic approach uses a series of operations (pulses), along with byte verification, to completely and
reliably erase and program the device.
For further information, see Reliability Report RR-60.
QUICK-PULSE PROGRAMMINGTM ALGORITHM

The Quick-Pulse Programming algorithm uses programming operations of 10 ILs duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with Vpp at high voltage. Figure 5 illustrates the Quick-Pulse Programming algorithm.

Reset Command

QUICK-ERASETM ALGORITHM

Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming™ algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F010 is erased when shipped from the factory~
Reading FFH data from the device would immediately be followed by device programming.

EXTENDED ERASE/PROGRAM CYCLING

EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes; reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubledan expensive solution.

For devices being erased and reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state
(Data = OOH). This is accomplished, using the
Quick-Pulse Programming algorithm, inapproximately two seconds.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 6 illustrates the Quick-Erase algorithm.

Intel has designed extended cycling capability into
its ETOX II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
-advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately
2 MV/cm lower than EEPROM. The lower electric
6-64

intJ

28F010

(

(4) Start ;)
Programming

Apply
VpPH[I]

PLSCNT=O

Bus
Operation

Command

Comments

,l.

I
I

Standby

•

WRITE Set-up
Program Cmd

..
..

Write Program
Cmd (A/D)

Initialize Pulse-Count
I

I
I

I TIme Out 10}," I

,l.
Write Program
Verify Cmd

Read Data
from Device

Set-up
Program

Data

Write

Program

Valid Address/Data

Write

= 40H

Write

Duration of Program
Operation (tWHWH1)

Standby

I TIme Out 6}'s I
-1-

Wait for Vpp Ramp to VPPH(1)

Program(2)
Verify

Data = COH; Stops Program
Operation(3)

Standby

tWHGL

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected

Verify
Data

Inc
PLSCNT
=25?

Increment

Last
Address
?

Address

I
I

Write
Read Cmd

,l.
Apply
VpPL[I]

I
I I

(prOgramming)
Completed

Write
Apply
VpPL[I]

Standby

Read

Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to Vppdl)

( Program)
Error

290207-5
NOTES:
1. See DC Characteristics for the value of VPPH and
VPPL·
2. Program Verify is only performed aiter byte programming. A final read/compare may be performed (optional) after the register is written with the Read command.

3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.

Figure 5. 28F010 Quick-Pulse Programming™ Algorithm

6-65

inter

28F010

Bus
Operation

Command

Comments

Entire Memory Must
Before Erasure

= OOH

Use Quick-Pulse
Programming™ Algorithm
(Figure 5)
Standby

Wait for Vpp Ramp to VpPH(1)

Initialize Addresses and
Pulse-Count

Write

Set-up
Erase

Data

= 20H

Write

Erase

Data

= 20H

Standby

Duration of Erase Operation
(tWHWH2)

Standby

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(3)
tWHGL

Read

Read Byte to Verify Erasure

Standby

Compare Output to FFH
Increment Pulse-Count

Write

Erase(2)
Verify

Read

Standby

290207-6
1. See DC Characteristics for the value of VPPH and
VPPL·
2. Erase Verijy is performed only after Chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.

Data = OOH, Resets the
Register for Read Operations
Wait for VPP Ramp to Vppd1)

3. Refer to principles of operation.

4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.

Figure 6. 28F010 Qulck-Erase™ Algorithm

6-66

inter

28F010
circuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.

DESIGN CONSIDERATIONS
Two-Line Output Control

Vpp Trace on Printed Circuit Boards

Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory 'connections. Two-line
control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.

Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the Vpp power supply trace. The Vpp pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the Vee power bus. Ad- - .. _ ... - \/_ - - •• __ 1............................................."'1; ... " ,.,ill ,.. ....
""'''IU(:;Uu '" tJt" ,:,u .... ..,., I.. Uv .... WO """'-&
........ """, ....
crease Vpp voltage spikes and overshoots.
~

To efficiently use these two control inputs, an address-decoder output should drive chip-enable,
while the system's read Signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power standby condition.

t"1I1 I~

........ _

Power Up/Down Protection
The 28F010 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F010 is indifferent
as to which power supply, Vpp or Vee, powers up
first. Power supply sequencing is not required. Internal circuitry in the 28F010 ensures that the command register is reset to the read mode on power
up.

Power Supply Decoupling
Flash-memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current (Icc> issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.

Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 ,...F ceramic capacitor
connected between Vee and Vss, and between Vpp
and Vss.

28F010 Power Dissipation
When designing portable systems, designers must
consider battery power consumption n'ot only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F010.

Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 ,...F electrolytic capacitor should be placed at the array's power supply
connection, between Vee and Vss. The bulk capacitor will overcome voltage slumps caused by printed-

Table 4. 28F010 Typical Update Power Dlssipatlon(4)
Operation

Notes

Power Dissipation
(Watt-Seconds)

Array Program/Program Verify

0.171

Array Erase/Erase Verify

0.136

One Complete Cycle

0.478

NOTES:
1. Formula to calculate typical Program/Program Verify Power = [Vpp x
# Bytes x typical # Prog Pulses (tWHWHl x IpP2 typical + tWHGL X IpP4
typical)] + [Vcc x # Bytes x typical # Prog Pulses (tWHWHl x ICC2 typical
+ tWHGL x ICC4 typical].
2. Formula to calculate typical Erase/Erase Verify Power = [Vpp (VPP3 typical
x tERASE typical + IpP5 typical x tWHGL x # Bytes)) + [VCC (Icca typical x
tERASE typical + ICC5 typical x tWHGL x # Bytes)).
3. One Complete Cycle = Array Preprogram + Array Erase + Program.
4. "Typicals" are not guaranteed, but based on a limited number of samples
from production lots.

6-67

inter

28F010

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature
During Read .......... : ....... O°C to + 70°C(1)
During Erase/Program ........... O°C to + 70°C
Temperature Under Bias ......... -10°C to + 80°C
Storage Temperature .......... - 65°C to + 125°C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Voltage on Pin Ag with
Respect to Ground ....... - 2.0V to + 13.5V(2, 3)
Vpp Supply Voltage with
Respect to Ground
During Erase/Program .... - 2.0V to + 14.0V(2, 3)
Vee Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Output Short Circuit Current ......... ',' .. 100 mA(4)

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for
.
periods less than 20 ns.
3. Maximum DC voltage on Ag or Vpp may overshoot to + 14.0V for periods less than 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING CONDITIONS
Symbol

Limits

Parameter

Operating Temperature

Vee

Vee Supply Voltage

Unit

Comments

°C

For Read-Only and
Read/Write Operations

5.50

Min

Max

0
4.50

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE
Symbol

Parameter

Limits

Notes
Min

Typical

Unit

Test Conditions

Max

III

Input Leakage Current

±1.0

/J- A

Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

±10

/J- A

Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

1.0

Y..s;;..e = Vee Max
CE = VIH

lee1

Vee Active Read Current

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

lee2

Vee Programming Current

1,2

1.0

Programming in Progress

lee3

Vee Erase Current

1,2

5.0

Erasure in Progress

lee4

Vee Program Verify Current

1,2

5.0

Vpp = VPPH, Program
Verify in Progress

Ices

Vee Erase Verify Current

1,2

5.0

Vpp = VpPH, Erase
Verify in Progress

Ipps

Vpp Leakage Current

±10

/J- A

Vpp::;: Vee

6-68

intJ

28F010

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes

Min Typical
IpP1

VppRead Current
or Standby Current

Unit

Test Conditions

Max
200

p.A Vpp> Vee
Vpp ~ Vee

±10.0

IpP2

Vpp Programming Current

1,2

8.0

rnA Vpp = VpPH
Programming in Progress

IpP3

vpp t:rase L;urrem

i,2

0.0

IliA

IpP4

Vpp Program Verify Current

1,2

2.0

5.0

rnA Vpp = VPPH, Program
Verify in Progress

IpP5

Vpp Erase Verify Current

1,2

2.0

5.0

rnA Vpp = VPPH, Erase
Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH1

Output High Voltage

VID

Ag inteligent IdentiferTM Voltage

0.8
Vee

2.4
11.50

13.00

+ 0.5

0.45

V
V

IOL = 5.8 rnA
Vee = Vee Min

IOH = -2.5 rnA
Vee = Vee Min

liD

Ag inteligent IdentifierTM Current

VPPL

Vpp during Read-Only
Operations

0.00

6.5

VPPH

Vpp during Read/Write
Operations

11.40

12.60

VLKO

Vee Erase/Write Lock Voltage

200

2.5

YPPH
Erasure in Progress

ypp -

p.A Ag

VID

NOTE: Erase/Program are
Inhibited when Vpp = VPPL

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

Limits

Notes
Min

Typical

Unit

Test Conditions

Max

III

Input Leakage Current

±1.0

p.A

Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

±10

p.A

Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

100

':!.s:..e = Vee Max
CE = Vee ±0.2V

lee1

Vee Active Read Current

rnA

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 rnA

leC2

Vee Programming Current

1,2

1.0

rnA

Programming in Progress

ICC3

Vec Erase Current

1,2

5.0

rnA

Erasure in Progress

leC4

Vce Program Verify Current

1,2

5.0

rnA

Vpp = VPPH, Program
Verify in Progress

lec5

Vee Erase Verify Current

1,2

5.0

rnA

Vpp = VPPH, Erase
Verify in Progress

Ipps

Vpp Leakage Current

±10

p.A

Vpp ~ Vee

6-69

inter

28F010

DC CHARACTERISTICS-CMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes
Min

Vpp Read Current, 10
Current or Standby
Current

IpP1

Unit

Typical

Max

200

Test Conditions

/LA Vpp

±10

> Vee

VPP. $ Vee

IpP2

Vpp Programming
Current

.1,2

8.0

rnA Vpp = VpPH
Programming in Progress

IpP3

Vpp Erase Current

1,2

6.0

rnA Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify
Current

1,2

2.0

5.0

rnA Vpp = VpPH, Program
Verify in Progress

1,2

2.0

5.0

rnA Vpp = VPPH, Erase
Verify in Progress

Ipps

Vpp Erase Verify
. Current
Input Low Voltage

-0;5

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

VOH1

Output High Voltage

VIL

0.8
Vee

+ 0.5

0.45
0.85 Vee

V
V IOL = 5.8 rnA
Vee = Vee Min
IOH = -2.5 rnA, Vee = Vee Min

IOH = -100 /LA, Vee = Vee Min

Vee - 0.4

VOH2
VIO

As inteligent IdentiferTM
Voltage

110

As inteligent IdentifierTM
Current

VPPL

Vpp during Read-Only
Operations

0.00

6.5

VPPH

Vpp during Read/Write
Operations

11.40

12.60

VLKO

Vee Erase/Write Lock
Voltage

2.5

CAPACITANCE TA
Symbol

13.00

11.50
1

200

V
/LA As = VIO
V NOTE: Erase/Programs are
Inhibited when Vpp = VPPL
V
V

= 25°C, f = 1.0 MHz
Parameter

Limits

Notes
Min

Unit

Conditions

Max

CIN

Address/Control Capacitance

VIN = OV

COUT

Output Capacitance

VbUT = OV

NOTES:
1. AII,currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T
are valid for all product versions (packages and speeds).
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.

6-70

25°e. These currents

inter

28F010

AC TESTING INPUT/OUTPUT WAVEFORM

AC TESTING LOAD CIRCUIT

2.4

1.3V
--

INPUT
0.45

~ .. IN914
2.0
0.8

TEST POINTS

3.3K

DEVICE
UNDER

I i~3i

290207-7

AC Testing: Inputs are driven at 2.4 for a logic "'I"' and 0.45 for a
logic "'0"'. Testing measurements are made at 2.0 for a logic "'I'"
and 0.6 for a logic "'0'". Rise/Fall time ,; IOns.

I1--+-0 OUT
I ..L

CL =100pF'

290207-6
CL = 100 pF
CL includes Jig Capacitance

.AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................... 0.45 and 2.4
Input Timing Reference Level .........• 0.8 and 2.0
Output Timing Reference Level ......... 0.8 and 2.0

AC CHARACTERISTICS-Read-Only Operations(2)
Versions
Symbol

Characteristic

tAVAV/tRC

Read Cycle Time

tELQV/tCE

Chip Enable
Access Time

Notes
3

28F010-120

Min

Max

120

Output Enable
Access Time

tELQX/tLZ

Chip Enable to
Output in Low Z

tEHQZ

Chip Disable to
Output in High Z

tGLQX/tOLZ Output Enable to
Output in Low Z

tGHQZ/tOF

Output Disable to
Output in High Z

tOH

Output Hold from
Address, CE,
orOEChange

1,3

tWHGL

Write Recovery Time
before Read

28F010-200

Min

Max

200

Unit
ns

120

150

200

120

150

200

0
55

0
30

ns
55

ns
40

/Jos

NOTES:
1.
2.
3.
4.

Max

150

tAVQV/tACC Address Access
Time
tGLQV/tOE

28F010-150

Min

Whichever occurs first.
Rise/Fall Time s 10 ns.
Not 100% tested: characterization data available.
Guaranteed by design.

6-71

(
Vee POWER-UP

STANDBY

DEVICE AND
ADDRESS SELECTION

ADDRESSES

OUTPUTS ENABLED

DATA VALID

STANDBY

Vcc POWER-DOWN

ADDRESS STABLE

t AVAV (t RC)

iFi
c::

...CD

cr (E)

;"I

l>
0

:E
II)

-...
<
CD

cp
-.j

Of (G)

01)

1/1

...0'
:XI

o
....
o

1 t WHGL -+1----,

WE (Vi)

tGLQV (tOE)

II)

tELQV

(tOLZ ) -+l
(t lZ )

...
CD

o·

::J
1/1

·1

(teE)

DATA (DO)

HIGH Z

VALID OUTPUT

I
I------

~J
VCC

tOH

HIGH Z

"~\\~\\r--t AVQV

(IACC)

290207-9

28F010
AC CHARACTERISTICS-Write/Erase/Program Operations(1,2)
Versions

Notes

Symbol

Characteristic

tAVAV/tWC

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

28F010-120

28F010-150

28F010-200

Min

Niln

Min

Max

Unit

120

150

200

tWLAX/tAH

Address Hold Time

tnvwH/tns

Data Set-Up Time

tWHDX/tDH

Data Hold Time

tWHGL

Write Recovery Time
before Read

p.s

tGHWL

Read Recovery Time
before Write

p.s

tELWL/tCS

Chip Enable
Set-Up Time before Write

tWHEH/tCH

Chip Enable
Hold Time

tWLWH/tWP

Write Pulse Width

tWHWL/tWPH Write Pulse
Width High
tWHwH1

Duration of
Programming Operation

p.s

tWHWH2

Duration of
Erase Operation

9.5

tVPEL

VppSet-Up
Time to Chip Enable Low

1.0

p.s

NOTES:

1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Rise/Fall time s: 10 ns.
3. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum
specification.

ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter

Notes

28F010-120
Min

Chip Erase Time

1,3,4

Chip Program Time

1,2,4

Erase/Program Cycles

1,5

Max

1.0

10·

12.5

10,000 100,000

28FO 10-200

28F010-150

Typ

Min

Typ

Max

1.0

12.5

10,000 100,000

Min

Unit

Typ

Max

1.0

12.5

10,000 100,000

Sec
Sec
Cycles

NOTES:

1. "Typicals" are not guaranteed, but based on a limited number of samples from production lots. Data taken at 25'C, 12.0V
Vpp.
2. Minimum byte programming time excluding system overhead is 16 J.Lsec (10 J.Lsec program + 6 fLsec write recovery),
while maximum is 400 J.Lsec/byte (16 J.Lsec x 25 loops allowed by algorithm). Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes DOH Programming prior to Erasure.
4. Excludes System-Level Overhead.
5. Refer to RR-60 "ETOXTM II Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.

6-73

intJ

28F010

99.9

../.

I,"

.....
. ...
/ ..
..
:/'
/

80
70
60

50
40
30

..,1"""
.
'

/ ...,

l,'

O.1
2

2.5

3.544.55

Chfp Program Time (Sec)
- - - f 2 V ; 10 ke; 23C
- ••••• - 11.4V; 10 kc: 70C
- - - - 12V; 100 kc; 23C

290207-13

Figure 8. 28F010 Typical Programming Capability

,..,. .,
~

.co

-' -~ ~
/
J

J/
V

V
,
,,

III

100

110

120

130

TEMP (c)

_ _ lk Cycles
- •• - 10k Cycle,
-.-.- lOOk Cycle.

Figure 9. 28F010 Typical Program Time at 12V
6-74

290207-14

inter

28F010

99.9

1';·'" ,.

1/ ,

., .'

/ ,,' .I

90
80

' I

ii , ,/

'" 60
50

40
=>
o 30

::IE

I '1
I '

1//
/11

10
S

I/,'i,.

28F010-120/1S0

28FOlO-200

/i"

('"
I

;

O. 1
0.5

0.7

4 5 6 78910

CHIP ERASE TIME (SEC)
12V; 10 kc;23C
11.4V; 10 kCjOC

------

12V,100 kc,23C

290207-15

Figure 10. 28F010 Typical Erase Capability
3.2
3.0

~
~

2.8
2.6

!;l
en

2.4

... 2.2
...;:::en
'
......"''" 2.0
;:.
::IE

1.8

1.6
1.4

"', '"

' ....
I"- r--.... .....

....

.......

1.2
1.0

r-.... .....
~...

i"- I-..

1'r-

r- r-r-

90 100 110 120 130 140

TEMP (OC)
--lkCycl..
----10k Cycles
.._ .. lOOk Cycl..

290207-16

Figure 11. 28F010 Typical Erase Time at 12V

6-75

Vee POWER-UP .!c
STANDBY

SET-UP PROGRAM
CO ....AND

PROGRA .. CO .. MAND
LATCH ADDRESS .!c DATA

PROGRAMMING

PROGRAM
VERIFY
COMMAND

PROGRAM
VERIFICATION

STANDBY/
Vee POWER-DOWN

(

ADDRESSES

cEll
c

...

CE (E)

.....

!'l

;:1
<

OE(G)

-...
CD

m
.!..,
(1)

0...

WE (Vi)

...

."
0

...

r4J

I
I I

(tOF)

I\)

3
3

~'I

DATA (DO)

'tI

...CD
I\)

~'I

S.OV
Vee
ov
'VPEL
12.0V

I+-

vPP
VpPL
290207-10

c»

"TI

0
I I 0....

Vcc POWER-UP 8<
STANDBY

SET-UP ERASE
COMMAND

ERASE COMMAND

ERASE
VERIFY
COMMAND

ERASING

ERASE
VERIFICATION

STANOBY/
Vce POWER-DOWN

ADDRESSES

CE (E)
."

10'
c

...
!.ol
CD

~I
::e:

(J)

.!..J

-oJ

il
..

DE (G)

1-1

-..
~I

t GHWL

t WHWL (twPH )

I·

tWHWH2

·1·

t WHGL

N
00

...o

WE (Vi)

--'.J '---- 1",,,.,,

III

U '---- 1",,,.,,

U '---- tWHDX

CII

~I
ao·

DATA (DO)

HIGH Z

tELQV (ICE)

::I
CII

5,OV
Vee
OV
t VPEL
12,OV
Vpp
VpPL

i----

~
290207-11

inter

28F010

ALTERNATIVE CE·CONTROLLED WRITES
Versions
Symbol

Characteristic

Notes

28F010·120

28F010·150

28F010·200

Min

Max

Unit

tAVEL

Address Set-Up Time

tElAX

Address Hold Time

tOVEH

Data Set-Up Time

tEHOX

Data Hold Time

tEHGL

Write Recovery Time
before Read

IJ-s

tGHEL

Read Recovery Time
before Write

IJ-s

tWLEL

Write Enable Set-Up Time
before Chip Enable

tEHWH

Write Enable Hold Time

Write Cycle Time

150

Max

200
'0

tAVAV

120

Max

ns
ns

tELEH

Write Pulse Width

tEHEL

Write Pulse Width High

tVPEL

Vpp Set-Up Time to
Chip Enable Low

1.0

IJ-s

6-78

»z

;::;0

!'l-t

Vee POWER-UP &:
STANDBY

=>m
III ""

""<

PROGRAM COMMAND
LATCH ADDRESS &: DATA

PROGRAMMING

PROGRAM
VERIFY
COMMAND

PROGRAI4
VERIFICATION

STANDBY/
Vec POWER-DOWN

(!)

fril

SET-UP PROGRAM
COMMAND

ADDRESSES

0
0

"TI

...

m
a.
::E
~

::!
3

cO"

...

C
II

;:;

...

II
:::J
III
II
~

...

WE (E)

co
en

!!!.
en
0

III
"0
"0

OE (G)

:E -<
0

III

<
II

....

...

m 0
!.J 3
co

1/1
....
0

...
...0

(!)

r-:I

iil
en
(!)

....o~

(Vi)

(!)

ea
...
III

3
3
5"
ea

DATA (00)

5.0V

Vee

:::J

iil
0

1/1

12.0V
Vpp
V pPL

\.~
290207-19

28F010

ORDERING INFORMATION

121 a l F Ia 11 Ia 1-11 121 a I

L-,-------J

PACKAGE
P
32-PIN PLASTIC DIP
N
32-LEAD PLCC
E = STANDARD 32-LEAD TSOP
F
REVERSE 32-LEAD TSOP,

=
=
=

ACCESS SPEED (ns)
120ns
150 ns
200 ns

VALID COMBINATIONS:
P28F010-120
N28F010-120
P28F010-150
N28F010-150
P28F010-200
N28F010-200

E28F010-120
E28F010-150
E28F010-200

F28F010-120
F28F010-150
F28F010-200

ADDITIONAL INFORMATION
Order
Number
294005

ER-20,

"ETOXTM II Flash Memory
Technology"

ER-24,

"The Intel 28F01 0 Flash
Memory"

294008

RR-60,

"ETOXTM II Flash Memory
Reliability Data Summary"

293002

AP-316,

"Using Flash Memory for
In-System
Reprogrammable
Nonvolatile Storage"

292046

AP-325

"Guide to Flash Memory
Reprogramming"

292059

6-80

290207-20

28F020
2048K (256K x 8) CMOS FLASH MEMORY
Electrical Chip-Erase
Immunity Features
• -Flash
• -Noise
2 Second Typical Chip-Erase
± 10% Vee Tolerance
- Maximum Latch-Up Immunity
auick-Pulse Programming™ Algorithm
• -10
through EPI Processing
}..Ls Typical Byte-Program
ETOXTM Nonvolatile Flash
- 4 Second Chip-Program
• Technology
Erase/Program Cycles Minimum
_... _1.. __ . . . . _. . _._. __ . .; ______-__• 10,000
12.0V ± 5% Vpp
High-Volume
Manufacturing
• High-Performance Read
Experience
• - 150 ns Maximum Access Time
Pinouts
• -JEDEC-Standard
32-Pin Plastic Dip
CMOS Low Power Consumption
• - 10 mA Typical Active Current
- 32-Lead PLCC
- 32-Lead TSOP
- 50 }..LA Typical Standby Current
- 0 Watts Data Retention Power
• Integrated Program/Erase Stop Timer
Command Register Architecture for
• Microprocessor/Microcontroller
\I

I::DDn.._I' ........ "'tihl.. Dr",,...cc

R~!IU:'

(See Packaging Spec., Order '" 231369)

Compatible Write Interface
Intel's 28F020 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F020 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F020 increases
memory flexibility, while contributing to time- and cost-savings.
The 28F020 is a 2048-kilobit nonvolatile memory organized as 262,144 bytes of 8 bits. Intel's 28F020 is
offered in 32-pin plastic DIP, 32-lead PLCC, and 32-lead TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel's ETOXTM II (EPROM Tunnel Oxide)
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the
28F020 performs a minimum of 10,000 erase and program cycles well within the time limits of the Quick-Pulse
Programming™ and Quick-Erase™ algorithms.
Intel's 28F020 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 150 nanosecond access time provides no-WAlT-state performance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 /LA translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins, from -1V to Vee + 1V.
With Intel's ETOX II process base, the 28F020 levers years of EPROM experience to yield the highest levels of
quality, reliability, and cost-effectiveness.

6-81

November 1990
Order Number: 290245-003

intJ

28F020

Vcc"-'

Vss"-'

vpp - - -....- - - - .......

STB

Ao-A 17

...J

~-----------~~

--------------v1~
a:
o

~
290245-1

Figure 1. 28F020 Block Diagram
Table 1. Pin Description
Symbol

Type

Name and Function

Ao-A17

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.

DQo-DQ7

INPUTIOUTPUT

DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.

INPUT

CHIP ENABLE: Activates the device's controllo9!s, input buffers,
decoders and sense amplifiers. CE is active low; CE high deselects the
memory device and reduces power consumption to standby levels.

INPUT

OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE is active low.

INPUT

Vpp

ERASE/PROGRAM POWER SUPPLY for writing the command
register, eraSing the entire array, or programming bytes in the array.

Vee

DEVICE POWER SUPPLY (5V ± 10%)

Vss

GROUND

6-82

inter

28F020

VPP

Vee

.r 11 J: ~I~;

A16

A1S

A17

A12

A14

A13

A14

A 13

All

N2BF"020
32 - LEAD PLCC
0.450" x 0.550"
TOP VIEW

A8
Ag

A 10

00 7

DOD

006

DOD

001

DOs

00 2

00 4

Vss

00 3

Al1

CE
00 7

290245-3
290245-2

06
~

0.
03

vss

9
10
11
12
13
14
15 ______________________________

6
7

~o
CE
STANDARD PINOUT
E2BF"020
32-LEAD TSOP
Bmm x 20mm
TOP VIEW

~
01
~
~
~
~

290245-4

290245-5

Figure 2. 28F020 Pin Configurations

6-83

28F020

APPLICATIONS
The 28F020 flash memory provides nonvolatility
along with the capability to typically perform over
100,000 electrical chip-erasure/reprogram cycles.
These features make the 28F020 an innovative alternative to disk, EEPROM, and battery-backed stat- '
ic RAM. Where periodic updates of code and datatables are required, the 28F020's reprogrammability
and nonvolatility make it the obvious and ideal replacement for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of .
performance and substantial reduction of power
consumption - a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable BIOS, system manufacturers can easily accommodate last-minute changes as
revisions are made.
In diskless workstations and terminals, network traffic reduces to a minimum and systems are instanton. Reliability exceeds that of electromechanical
media. Often in these environments, power interruptions force extended re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communication protocols and primary applications are flash-resident in
each terminal.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the. 28F020 flash memory offers a solid
state alternative in a minimal form factor. The
28F020 provides higher performance, lower power
consumption, instant-on capability, and allows an
"execute in place" memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
.
disk-based systems to fail.

Material and labor costs associated with code
changes increases at higher levels of system integration - the most costly being code updates after
sale. Code "bugs", or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the removal of EPROM components or entire boards. With
the 28F020, code updates are implemented locally
via an edge-connector, or remotely over a communcations link.
For systems currently using a high-density static
RAM/battery' configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory's electrical chip erasure, byte programmability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a "blank slate" in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new "blank slate".
A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 3 depicts two 28F020s tied to the 80C186 system bus.
The 28F020's architecture minimizes interface circuitry needed for complete in-circuit' updates of
memory contents.
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. With standard and reverse pin configurations, TSOP reduces
the number of board .layers' and overall volume necessary to layout multiple 28F020s. TSOP is particularly suited for portable equipment and applications
requiring large amounts of flash memory. Figure 4
illustrates the TSOP Serpentine layout.
With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility,
the 28F020 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs.

The need for code updates pervades all phases of a
system's life - from prototyping to system manufacture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F020 allows incircuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.

6-84

intJ

28F020

Vee

80C18S
SYSTEM BUS

Vee
A,-A,8 _ _ _ _ _ _ _ _--.. Ao-A'7

DQO-DQ7

+---------1
28F020

28F020
ADDRESS DECODED _ _ _ _ _ _ _ _ _....
CHIP SELECT
BHE

~---""'WE

1--+1 WE

RD _ _ _ _ _ _ _ _........ OE
290245-6

Figure 3. 28F020 in a 80C186 System
standard microprocessor read timings output array
data, access the inteligent Identifier codes, or output
data for erase and program verification.

PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F020 introduces a command register to manage
this new functionality~ The command register allows
for: 100% TTL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.

Integrated Stop Timer

In the absence of high voltage on the Vpp pin, the'
28F020 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and inteligent
IdentifierTM operations.
.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasiJre and programming of the device. All
functions associated with altering memory contents-inteligent Identifier, erase, erase verify, program, and program verify-are accessed via the
command register.

Successive command write cycles define the durations of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command.

Write Protection
The command register is only active when Vpp is at
high voltage. Depending upon the application, the.
system designer may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When Vpp = VPPL, the contents of the register default to the read command,
making the 28F020 a read-only memory. In this
mode, the memory contents cannot be altered.

inter

28F020

nIl ann llil 0000000 0n-~~~I
00.,. .,0n-n
11 00 0

IlL

~II

no 011 00110 nIlllOIlOm

I-

~r-.<
,
"

0
N
0

lL.

0
N
0

lL.

.....

lL.

UUUUUUUUUUUUUUUU UUUUUUUUUUUUUUUL UUUUUUUUUUUUUUUU

Figure 4. TSOP Serpentine Layout
6~86

0
N
0

lL.

.....

UUUUUUUUUUUUUUU~

inter

28F020

Table 2. 28F020 Bus Operations
Pins

Vpp(1)

VIL

VIH

Data Out

DQo-DQ7

Operation
Read

READ-ONLY

READ/WRITE

VpPL

Output Disable

VPPL

VIL

VIH

Tri-State

Standby

VPPL

VIH

Tri-State

int::ligent IdentifierTM (Mfr)(2)

VPPI

VII_

VIO(3)

VIL

VIH

Data

inteligent IdentifierTM (Device)(2)

VIL

VIH

Data

=
=

89H

VPPL

VIH

VIO(3)

Read

VPPH

VIL

VIH

Data Out(4)

Output Disable

VPPH

VIL

VIH

Tri-State

Standby(5)

VPPH

VIH

Tri-State-

Write

VPPH

VIL

VIH

VIL

Data In(6)

BDH

NOTES:

1. Refer to DC Characteristics. When Vpp = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VID is the inteligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with Vpp = VPPH may access array data or the inteligent IdentifierTM codes.
5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.
Or, the system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever VCC is below the write
lockout voltage VLKO. (See Power Up/Down Protection.) The 28F020 is designed to accommodate either design practice, and to encourage optimization
of the processor-memory interface.

Output Disable
With Output-Enable at a logic-high level (VIH), output
from the device is disabled. Output pins are placed
in a high-impedance state.
Standby
With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F020's circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable signal.
If the 28F020 is deselected during erasure, programming, or program/erase verification, the
device draws active current until the operation is
terminated.

BUS OPERATIONS
Read
The 28F020 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CE) is the power control and
should be used for device selection. Output-Enable
(OE) is the output control and should be used
to gate data from the output pins, independent of
device selection. Refer to AC read timing
waveforms.

inteligent IdentifierTM Operation
The inteligent Identifier operation outputs the manufacturer code (89H) and device code (BDH). Programming equipment automatically matches the device with its proper erase and programming algorithms.

When Vpp is high (VPPH), the read operation can be
used to access array data, to output the inteligent
Identifier™ codes, and to access data for program/
erase verification. When Vpp is low (VppLl, the read
operation can only access the array data.

6-87

intJ

28F020

With Chip-Enable and Output-Enable at a logic low
level, raising A9 to high voltage'VID (see DC Characteristics) activates the operation. Data read from locations OOOOH and 0001 H represent the manufacturer's code and the device code, respectively.
The manufacturer- arid device-codes can also be
read via the command register, for instances where
the 28F020 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the device code (BDH).

used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WriteEnable to a logic-low level (VIU, while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erasel
Programming Waveforms for specific timing
parameters.

Write

COMMAND DEFINITIONS

When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.

The command register itself does not occupy an addressable memory location. The register is a latch

Placing high voltage on the Vpp pin enables readl
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F020 register
commands.

Table 3_ Command Definitions
Command

Bus
Second Bus Cycle
First Bus Cycle
Cycles
Req'd Operatlon(1) Address(2) Data(3) Operatlon(1) Address(2) Data(3)

Read Memory

Write

OOH

Read inteligent IdentifierTM Codes(4)

Write

90H

Read

(4)

Set-up Erase/Erase(5)

Write

20H

Write

20H

Erase Verify(5)

Write

AOH

Read

EVO

Set-up Program/Program(6)

Write

40H

Write

Program Verify(6)

Write

COH

Read

PVO

Reset(7)

Write

FFH

Write

FFH

NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. 10 = Data read from location IA during device identification (Mfr = 89H, Device = BDH).
EVD = Data read from location EA during erase verify.
PO = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read in!eligent 10 command, two read operations access manufacturer and device codes.
5. Figure 6 illustrates the Quick-Erase™ Algorithm.
6. Figure 5 illustrates the Quick-Pulse Programming™ Algorithm.
7. The second bus cycle must be followed by the desired command register write.

6-88

intJ

28F020

of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.

Read Command

While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.

Erase-Verify Command

The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing AOH into the command register. The address
for the byte to be verified must be supplied as It IS
latched on the falling edge of the Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.

The deiauit contenis oi iilll rllyisitl, ujJu(, Vpp pu;,;;er-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F020, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.

The 28F020 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.

inteligent IdentifierTM Command

Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice.

In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 6, the Quick-Erase™ algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F020.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters..

The 28F020 contains an inteligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address OOOOH retrieves the manufacturer code of 89H. A read cycle
from address 0001 H returns the device code of
SOH. To terminate the operation, it is necessary to
write another valid command into the register.

Set-up Program/Program Commands
Set-up Erase/Erase Commands

Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.

Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.

Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters.

To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (i.e., Erase-Verify Command).
This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, Chip-erasure can only occur when
high voltage is applied to the Vpp pin. In the absence
6-89

intJ

28F020

Program-Verify Command

The 28F020 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F020 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 5,
the 28F020 Quick-Pulse Programming™ algorithm,
illustrates how commands are combined with bus
operations to perform byte programming. Refer to
AC Programming Characieristics and 'vVaveforms for
specific timing parameters.

2 MV/cm lower than EEPROM. The lower electric
field greatly reduces oxide stress and the probability
of failure-increasing time to wearout by a factor of
100,000,000.
The 28F020 is specified for a minimum of 10,000
program/erase cycles. The device is programmed
and erased using Intel's Quick-Pulse ProgrammingTM and Quick-Erase™ algorithms. Intel's algorithmic approach uses a series of operations (pulses), along with byte verification, to completely and
reliably erase and program the device.
For further information, see Reliability Report RR-60.
QUICK-PULSE PROGRAMMINGTM ALGORITHM

The Quick-Pulse Programming algorithm uses programming operations of 10 JLs duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with Vpp at high Voltage. Figure 5 illustrates the Quick-Pulse Programming algorithm.

Reset Command
QUICK-ERASETM ALGORITHM

Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming™ algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F020 is erased when shipped from the factory.
Reading FFH data from the device would immediately be followed by device programming.

EXTENDED ERASE/PROGRAM CYCLING

Intel has designed extended cycling capability into
its ETOX II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second,the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately

Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in two seconds. Figure 6 illustrates the Quick-Erase algorithm.
6-90

28F020

Bus
Operation

Command

Standby

Comments

Wait for Vpp Ramp to VpPH(1)

Initialize Pulse-Count

Set-up
Program

Data

Write

Program

Valid Address/Data

Standby
Write

Duration of Program
Operation (twHWH1)
Program(2)
Verify

Data = COH; Stops Program
Operation(3)

Standby

tWHGL

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected

Write

Standby

290245-7
NOTES:
1. See DC Characteristics for the value of VPPH and
VPPL·
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command.

= 40H

Write

Read

Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to VppL!1)

3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.

Figure 5. 28F020 Quick-Pulse Programming™ Algorithm

6-91

intJ

28F020

Bus
Command
Operation

Comments

Entire Memory Must
Before Erasure

OOH

Use Quick-Pulse
Programming™ Algorithm
(Figure 4)
Standby

WaitforVpp Ramp to VPPH(1)

Initialize Addresses and
Pulse-Count

Write

Set-up
Erase

Data = 20H

Write

Erase

Data

Standby

20H

Duration of Erase Operation
(tWHWH2)

Standby

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(3)
tWHGL

Read

Read Byte to Verify Erasure

Standby

Compare Output to FFH
Increment Pulse-Count

Write

Erase(2)
Verify

Read

Standby

290245-8
1. See DC Characteristics for the value of VPPH and
VPPL·
2. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.

Data = OOH. Resets the
Register' for Read Operations
Wait for Vpp Ramp to Vppd1)

3. Refer to principles of operation.

4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.

Figure 6. 28F020 Quick-Erali!e™ Algorithm

6-92

inter

28F020

DESIGN CONSIDERATIONS

Power Up/Down Protection
The 28F020 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F020 is indifferent
as to which power supply, Vpp or Vce, powers up
first. Power supply sequencing is not required.
Internal circuitry in the 28F020 ensures that the
command register is reset to the read mode on power up.

A system designer must guard against active writes
for Vcc voltages above VLKO when Vpp is active.
Since both WE and CE must be low for a command
write, driving either to VIH will inhibit writes. The control register architecture provides an added level of
protection since alteration of memory contents only
occurs after successful completion of the two-step
command sequences.

28F020 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F020 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F020.

Power Supply Decoupling
Flash-memory power-switching characteristics require careful device'decoupling. System designers
are interested in three supply current {lcd issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.

Table 4. 28F020 Typical
Update Power Dissipation(4)

Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 IlF ceramic capacitor
connected between Vcc and Vss, and bely.leen Vpp
and Vss.
Place the high-frequency, low-inherent-inductance
capacrtors as close as possible to the devices. Also,
for every eight devices, a 4.7 IlF electrolytic capacitor should be placed at the array's power supply
connection, between Vcc andVss. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.

Operation

Notes

Power Dissipation
(Watt-Seconds)

Array Program/Program Verify

0.34

Array Erase/Erase Verify

0.37

One Complete Cycle

1.05

NOTES:
1. Formula to calculate typical Program/Program Verify
Power = [Vpp x # Bytes x typical # Prog Pulse
(twHWH1 x IpP2 typical + tWHGL X IpP4 typical)] + [Vcc
x # Bytes x typical # Prog Pulses (tWHWH1 x ICC2 typi·
cal + tWHGL X ICC4 typical)].
2. Formula to calculate typical Erase/Er<;lse Verify Power
= [Vpp (lpP3 typical x tERASE typical + IpP5 typical x
tWHGL x # Bytes)] + [VCC (ICC3 typical x tERASE typical
+ Iccs typical x tWHGL x # Bytes)].
3. One Complete Cycle = Array Preprogram + Array
Erase + Program.
4. "Typicals" are not guaranteed but based on a limited
number of samples from production lots.

Vpp Trace, on Printed Circuit Boards
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the Vpp power supply trace. The Vpp pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the Vce power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.

6-93

28F020

ABSOLUTE MAXIMUM RATINGS·

NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice.

Operating Temperature
During Read .................. O·C to + 70·C(1)
During Erase/Program ........... O·C to + 70·C
Temperature Under Bias ......... -1 O·C to + 80·C
Storage Temperature .......... - 65·C to + 125·C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Voltage on Pin Ag with
Respect to Ground ....... - 2.0V to + 13.5V(2, 3)
Vpp Supply Voltage with
Respect to Ground
During Erase/Program .... - 2.0V to + 14.0V(2, 3)
Vee Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Output Short Circuit Current ............. 100 mA(4)

NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for
periods less than 20 ns.
3. Maximum DC voltage on Ag or Vpp may overshoot to +, 14.0V for periods less than 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING CONDITIONS
Symbol

Limits

Parameter

Operating Temperature

Vee

Vee Supply Voltage

Unit

Comments

·C

For Read-Only and
Read/Write Operations

5.50

Min

Max

0
4.50

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE
Symbol

Parameter

Notes

Limits
Min

Typical

Max

Unit

Test Conditions

III

Input Leakage Current

±1.0

jJoA

Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

±10

jJoA

Vee = Vee Max
VOUT = VeeorVss

Ices

Vee Standby Current

1.0

Vee = Vee Max
CE = VIH

lee1

Vee Active Read Current

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

lee2

Vee Programming Current

1,2

1.0

Programming in Progress

lee3

Vee Erase Current

1,2

5.0

Erasure in Progress

lee4

Vee Program Verify Current

1,2

5.0

Vpp = VpPH,
Program Verify in Progress

lee5

Vee Erase Verify Current

1,2

5.0

Vpp = VPPH,
Erase Verify in Progress

Ipps

Vpp Leakage Current

1,2

±10

jJoA

Vpp ~ Vee

6-94

inter

28F020

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes

Min Typical
IpPl

Vpp Read Current, 10 Current
or Standby Current

Unit

Test Conditions

Max
200

IJ-A Vpp> Vee

±10

Vpp"; Vee

mA Vpp = VPPH
Programming in Progress

::lU

mA Ypp

Vpp Program Verify Current

1,2

2.0

5.0

mA Vpp = VPPH,
Program Verify in Progress

IpP5

Vpp Erase Verify Current

1,2

2.0

5.0

mA Vpp = VPPH,
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOHl

Output High Voltage

VID

Ag inteligent IdentiferTM
Voltage

liD

Ag inteligent Identifier™
Current

VPPL

Vpp during Read-Only
Operations

0.00

6.5

VPPH

Vpp during Read/Write
Operations

11.40

12.60

VLKO

Vee Erase/Write Lock Voltage

IpP2

Vpp Programming Current

1,2

IpP3

v PP t::rase Current

IpP4

0.8
Vee

2.4
11.50

13.00

+ 0.5

0.45

200

2.5

= YPPH

V
V

IOL = 5.8mA
Vee = Vee Min

IOH = -2.5mA
Vee = Vee Min

V
IJ-A Ag

= VID

NOTE: Erase/Program are
Inhibited when Vpp = VPPL

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

Limits

Notes
Min

Typical

Unit

Test Conditions

Max

Input Leakage Current

± 1.0

IJ-A

Vee = Vee Max
VIN = VeeorVss

ILO

Output Leakage Current

±10

IJ-A

Vee = Vee Max
VOUT = Vee or VSS

Iccs

Vce Standby Current

100

IJ-A

Vee = Vec Max
CE = Vee ±0.2V

leel

Vee Active Read Current

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

lee2

Vee Programming Current

1,2

1.0

Programming in Progress

lee3

Vee Erase Current

1,2

5.0

Erasure in Progress

lee4

Vee Program Verify Current

1,2

5.0

Vpp = VpPH, Program
Verify in Progress

lee5

Vee Erase Verify
Current

1,2

5.0

Vpp = VPPH,
Erase Verify in Progress

6-95

inter

28F020

DC CHARACTERISTICS-CMOS COMPATIBLE (Continued)
Symbol

Parameter

Limits

Notes

Typical

Min
Ipps

Vpp Leakage Current

IpPl

Vpp Read Current, ID Current
or Standby Current

Unit

Test Conditions

Max
±10

p.A Vpp::;; Vcc

200

p.A Vpp> Vcc

±10

Vpp::;; Vcc

IpP2

Vpp Programming
Current

1,2

mA Vpp = VPPH,
Programming in Progress

IpP3

Vpp Erase Current

1,2

mA Vpp = VPPH,
Erasure in Progress

IpP4

Vpp Program Verify
Current

1,2

2.0

5.0

mA Vpp = VPPH,

IpP5

Vpp Erase Verify
Current

1,2

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7Vcc

VOL

Output Low Voltage

Program Verify in Progress
2.0

mA Vpp = VPPH,
Erase Verify in Progress

5.0
0.8
Vcc

+ 0.5

0.45

VOHl

0.85 Vcc
Output High Voltage

VOH2
Ag inteligent Identifer™
Voltage

liD

Ag inteligent IdentifierTM
Current

VPPL

Vpp during Read-Only
Operations

0.00

VPPH

Vpp during Read/Write
Operations

11.40

VLKO

Vee Erase/Write Lock
Voltage

2.5

CAPACITANCE TA
Symbol

11.50

13.00

IOH = - 2.5 mA,
Vcc = Vcc Min
IOH = -100 p.A,
Vcc = Vcc Min

Vcc - 0.4

VID

IOL = 5.8mA
Vcc = Vcc Min

200

p.A Ag

6.5

12.60

VID

NOTE: Erase/Programs are
Inhibited when Vpp

VPPL

= 25°C, f = 1.0 MHz
Limits

Notes

CIN

Address/Control Capacitance

VIN

COUT

Output Capacitance

VOUT

Min

Max

Unit

Conditions

Parameter

NOTES for DC Characteristics and Capacitance:
1. All currents are in RMS unless otherwise noted. Typical values at Vee"" 5.0V, Vpp = 12.0V, T = 25°C. These currents
are valid for all product versions (packages and speeds).
2. Not 100% tested: Characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.

6-96

intJ

28F020

AC TESTING INPUT/OUTPUT WAVEFORM

, AC TESTING LOAD CIRCUIT
1.3V

2.4

-r-

INPUT
~

0.45

~~ lN914

2.0

0.8

3.3K

DEVICE
UNDER

TEST POINTS

290245-9

i~5i

I1--+-0 OUT
I ..L

CL =100pF

i.c Testing: Inputs are driven at 2.4 for a logic "1" and 0.45 for a

290245-10

logic "0". Testing measurements are made at 2.0 for a logic "1"
and O.B for a logic "0". Rise/Fall time ,; 10 ns.

CL = 100 pF
CL includes Jig Capacitance

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ..•................ 0.45 and 2.4
Input Timing Reference Level .......... 0.8 and 2.0
Output Timing Reference Level .•..... : .0.8 and 2.0

AC CHARACTERISTICS-Read-Only Operations(2)
Versions
Symbol

Notes

Characteristic

Max

150

28F020-200
Min

Unit

Max

200

tAvAV/tRC

Read Cycle Time

tELQV/tCE

Chip Enable Access Time

150

200

tAVQV/tACC

Address Access Time

150

200

taLQV/tOE

Output Enable Access Time

tELQX/tLZ

Chip Enable to
Output in Low Z

tEHQZ

Chip Disable to
Output in High Z

tGLQX/tOLZ

Output Enable to
Output in Low Z

tGHQZ/tDF

Output Disable to
Output in High Z

toH

Output Hold from Address,
CE, or OE Change(l)

tWHGL

Write Recovery Time
before Read

NOTES:
1.
2.
3.
4.

28F020-150
Min

Whichever occurs first.
Rise/Fall Time,;; 10 ns.
Not 100% Tested: Characterization Data Available.
Guaranteed by Design.

6-97

0
55

55
0

ns
ns

p.s

(
Vcc POWER-UP

STANDBY

DEVICE AND
ADDRESS SELECTION

OUTPUTS ENABLED

DATA VALID

STANDBY

ADDRESS STABLE

ADDRESSES

·1

tAVAV (t RC)
"TI

fi!i
c...

v CC POWER- DOWN

cr (E)

:'"
;so.
0

-...
CD

OE (e)
N
CD

-...

3
cO 1/1
co

1 t WHGL 1

·1

WE (Vi)

tGLOV (tOE)

C-

I - - - tELOV

..
...

tELOX (tLZ)

O·

1/1

tOH

t GLOX (tOLZ)--I

·1

(tCE)

DATA (DO)

HIGH Z

VALID OUTPUT

I
I----t
5.0V

VCC

I'~'

HIGH Z

I' - -

""+'--'

AVOV

(tACC)

290245-11

IiiiiI
F

~
~
~

inter

28F020

AC CHARACTERISTICS-Write/Erase/Program Operations(1, 2)
Versions
Symbol

Notes

Characteristic

28F020-150
Min

Max

28F020-200
Min

Unit

Max

150

200

Address Hold Time

Data ::;et-up Time

tWHDX/tDH

Data Hold Time

tWHGL

Write Recovery Time
before Read

p.s

tGHWL

Read Recovery Time
before Write

p.s

tELWL/tCS

Chip Enable
Set-Up Time before Write

tWHEH/tCH

Chip Enable Hold Time

tWLWH/tWP

Write Pulse Width

tWHWL/tWPH

Write Pulse Width High

tWHWH1

Duration of
Programming Operation

p.s

Duration of
Erase Operation

9.5

3
1.0

1.0

p's

tAVAV/tWC

Write Cycle Time

tAVWL/tAS

Address Set-Up Time

tWLAX/tAH
tDVWH/tDS

tWHWH2
tVPEL

VppSet-Up
Time to Chip Enable Low

NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Rise/Fall time"; 10 ns.
3. The integrated stop timer terminates the programming/erase operations. thereby eliminating the need for a maximum
specification.

ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter

Notes

Chip Erase Time

1.3.4

Chip Program Time

1.2.4

Min

Erase/Program Cycles

28F020-200

28F020-150

10,000

Typ

Max

100,0001,5

Min

10,000

Unit

Typ

Max

100,000

Sec
Sec
Cycles

NOTES:
1. "Typicals" are not guaranteed, but based on a limited number of samples from production lots. Data taken at 25'C, 12.0V

Vpp.

2. Minimum byte programming time excluding system overhead is 16 ",sec (10 ",sec program + 6 ",sec write recovery).
while maximum is 400 ",sec/byte (16 ",sec x 25 loops allowed by algorithm). Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes OOH Programming prior to Erasure.
4. Excludes System-Level Overhead.
5. Refer to RR-60 "ETOXTM II Flash Memory Reliability Data Summary" for typical cycling data and failure rate calculations.

6-99

inter

28F020

99.9

V
/

C
u
m

(

a
1
1
1
t
y

/,-/'
,,

, 1/ ,

,f,''',
V , ,,

,I ,

,
,,
,
,

, ,

b
b

" ,
,
,,

., ~/ ,,/ ,,
,,

,
,,

I ,,"

10
5

0.1

Chip Program Time (Sec)
- - - . , . 12V; 10ke; 23C
- ••••• -11.4v; 10ke: lOC
.,.---- 12V; 100ke; 23C
290245-12

Figure 8. 28F020 Typical Programming Capability

6-100

28F020

C
h

P
0

9
r

a
m

T
I

m
e

",,"

e
c
7

,.1
.. .--.'
o

"",F

,
,,
,,

,
,,
,, ,
,

1t.·1

.
,
.
.'

,,
,, ,
,

. .- .. ----

---

,.-

/
90

I
100

110

120

130

Temp (C)
- - - 1k Cycles
------- 10k Cycles
- - - - lOOk Cycles
290245-13

Figure 9. 28F020 Typical Program Time at 12V

6-101

28F020

99.9

/i,

,I
,
,, ,

"
/ ,/'/
I

a
b
I
I
I
t

,,','1'

V , ,
" ~'
,
V , ,I

C
u
m

1./"

.. .I

,'1'

,,
J , !
,: ,l

40
30

/
j/ II!
I ,! .I

10
5

~i/

ii.

:i•

J:1i
0.1

7 8 910

Chip Erase TIme (Sec)
- - - 12V; 10ke; 23C
------- 12V; 100ke; 23C
- - - - 11.4V; 10ke; OC
290245-14

NOTE:
Does not include Pre-Erase Program.'

Figure 10. 28F020 Typical Erase Capability

6-102

inter

28F020

5.2
5.0

4.B

1\,

4.6

,
\

4.4

4.2

h
I

4.0

a
s
e

3.6

T
i

m
e
S
e
c

,,
,

3.B

3.4

1\ "

,
" ,

r"\..

3.2

",,

3.0

2.B
2.6

. .
.. . .
. ..
r-...
......

2.4
2.2
2.0

I'" .
.. .
..

..........

" '- .

.. .. r ....
1'-0...

.... .
r--...... ............ ...... .. ..

-- t'-

100

110

120

130

Temp (C)
- - - lk Cycles

-------10k Cycles

- - - - lOOk Cycles

NOTE:

Does not include Pre-Erase Program.

Figure 11_ 28F020 Typical Erase Time at 12.0V.

6-103

290245-15

Vee POWER-UP &:
STANDBY

SET-UP PROGRAM
COMMAND

PROGRAM COMMAND
LATCH ADDRESS &: DATA

PROGRAMMING

PROGRAM
VERIFY
COMMAND

PROGRAM
VERlriCATION

STANDBY!
Vee POWER-DOWN

(

ADDRESSES

(II

:::E

-...

::!

(II

::J

!!l.
(II

<0
IJ>

!!!.
IJ>

0
l»

III

-...
-......
<
(II
0

(II

WE (E)

::>

0
-..J

...
....

[

"Q.

OE (G)

(!)

iil
IJ>

I\)

c»
~
I\)

(!)

iil
d"•

"'0
0

IJ>

CE ('iI)

0
::>

iil

3
~.

DATA (DQ)

::J

"...
g.
(II

::J

III

5~::J

\11 ~

12'OV~

pPL
V

290245-18

IF'

~
~

inter

28F020

ORDERING INFORMATION

Ip12181 r lo121 01-lll s101

L-,---J

PACKAGE
P = 32-PIN PLASTIC DIP
N = 32-LEAD PLCC
E STANDARD 32-LEAD TSOP
r = REVERSE 32-LEAD TSOP

ACCESS SPEED. (ns)
ISO ns
200 ns
290245-19

VALID COMBINATIONS:
P28F020-150
N28F020-150
P28F020-200
N28F020-200

E28F020-150
E28F020-200

F28F020-150
F28F020-200

ADDITIONAL INFORMATION
Order
Number
294005

ER-20,

"ETOXTivi II Flash iviemory
Technology"

ER-24,

"The Intel 28F020 Flash"
Memory"

294008

RR-60,

"ETOXTM II Flash Memory
Reliability Data Summary"

293002

AP-316,

"Using Flash Memory for
In-System
Reprogrammable
Nonvolatile Storage"

292046

AP-325

"Guide to Flash Memory
Reprogramming",

292059

6-108

iSM001FLKA
1 MBYTE (512K x 16) CMOS FLASH SIMM
III High-Performance

- 120 ns Maximum Access Time
-16.67 MB/s Read Transfer Rate
In 10,000 Rewrite Cycles Minimum/

Componeni

80-Pin Insertable Module
• -Standard
0.050 Centerline Lead Spacing
- Upgrade Path through 128M bytes
III Hardware Presence Detect
li!I Command Register Architecture for

II Flash Electrical Chip-Erase

Microprocessor /Microcontroller
Compatible Write lnteriace

1 Second Typical Chip-Erase

I!l 16 p.s Typical Word Write

- Up to 1 Mb/s Write Transfer Rate
I:iJ Inherent Non-volatility

- No Batteries or Disk Required for
Back-up
- OW Data Retention Power
£llI CMOS Low Power Consumption \

- 20.3 mA Typical Active Current
- 0.4 mA Typical Standby Current

Noise Immunity Features
- ±,10% Vee Tolerance
- Maximum Latch-Up Immunity
Through EPI Processing

II 12.0V ± 5% Vpp
II Integrated Program/Erase Stop Timer
III ETOXTM II Nonvolatile Flash

Technology
- High-Volume Manufacturing
Experience

Intel's iSM001 FLKA flash SIMM (Single In-Line Memory Module) is targeted at high-density read/write nonvolatile memory. The iSM001 FLKA enables you to optimize board space; to offer incremental memory expansion
similar to today's DRAM; and to assure continued access to today's and tomorrow's surface-mount technologies. Intel's iSM001 FLKA offers a reliable sold-state alternative for mass storage. The flash memory module is
also ideal for high performance code and data storage as well as data recording and accumulation.
The iSM001 FLKA, composed of eight 1 Mb flash memories in plastic leaded chip carrier (N28F01 0), is organized as 524,288 words of 16 bits. The PLCCs are mounted, four to a side, together with 0.1 /o'F decoupling
capacitors on an 80-pin standard, low-profile module.
Extended erase and program cycling capability is designed into Intel's ETOXTM II (EPROM Tunnel Oxide),
process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field
combine to extend reliable cycling beyond that of traditional nonvolatile memory.
Intel's iSM001 FLKA flash SIMM employs advanced CMOS circuitry for systems requiring high-performance
access speeds, low power consumption, and immunity to noise. Its 120 ns access time provides no WAIT
state performance for a wide range of microprocessors and microcontrollers. Maximum standby current of
0.8 mA translates into power savings when the memory module is deselected. Finally, the highest degree of
latch-up protection is achieved through Intel's unique EPI processing. Prevention of latch-Up is provided for
stresses up to 100 mA on address and data pins, from -1V to Vee + 1V.

6-109

November 1990
Order Number: 290244-004

inter

iSM001FLKA

PO,-P07 (7'3-79)
DOS-00, 5 (62-55)
DOO-00 7 (70-63)
AO-AI6 (52-36)

CEO (24)
CE I (23)
CEZ (22)
CE 3 (21)
Of (4)

WEH

(5)

(6)
WE L .;..
~

~ Ao-A '6 °0-°7
l- CE
Of
WE

,..

IIIIi
~

Of
WE

VSS Vee Vpp

Vss

AD-A, 6 00-°7 !!!!!!I

""'"

CE
Of
WE
Vss Vee Vpp

~ Ao-A,6 00-07
CE
Of
WE

,..

(1)

~
Vee
Vpp

~
(3)

Vpp

Ao-A,6 °S-0,5

Vee

Vpp

I I I
Ao-A '6 °S-0,5 !I'I

CE
Of
WE
Vss

(s4)
(80)

Vss Vee Vpp

(25)
Vss

Ao-A '6 °0-°7

Yee

I I

Vss

I I I

CE
Of
WE

'"'"

Vss Vee Vpp

CE
Of
WE

Vpp

AD-A, 6 Ds -0 ,5

Vss

I I I

Vee

I I I
"""

AD-A, 6 °S-0'5

l- CE

Vee

Vpp

CO '"

=Co .. · ==C7

~
290244-1

Figure 1. iSM001FLKA Functional Block Diagram

6-110

infef

iSM001FLKA

1+-1.- - - - - - - - 4.65" --.,---------1·1

~IIQ~~~,~,~Q.~~g,LII~;.~1
FRONT VIEW

r....__I__
1

Tffikl
0.33"

....
O
·_l_D_D_D
___D_D_D
___D_D____~__::_::,_~::_:_O---,B
80

Mblt
32-LEAD

(55~L;~50 MILS)

0.05"+0.004/-0.003-11- SIDE VIEW

BACK VIEW

290244-2

Figure 2. iSM001FLKA Pin Configurations
Table 1. Pinout

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

VSS
Vee
Vpp
OE
WEH
WEL
NC
RES
RES
RES
RES
RES
RES
RES
RES
RES
NC
NC
NC
NC

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

CE3

A11

CE2
CE1'

42
43
44
45
46
47
48
49
50
51
52
53
54

A10

CEO

Vss
RES
RES
RES
RES
NC
NC
NC
NC
NC
NC

55
56
57
58
59
60

A16
A15
A14
A13
A12

6·111

Ag
Aa

61
62
63
64

DOg
OOa·
DOl
006

P0 5

0014

65
66
67
68
69
70
71
72
73
74
75
76

0013

P05

0012

78
79
80

P06

Al
A6
A5
A4
A3
A2
A1
Ao

RES

Vss
0015

0011
0010

004
003
002
001
000

Vpp
Vee
P01
P02
P03
P04

POl

Vss

•

iSM001FLKA

Table 2. Pin Description
Symbol

Ao-A16

Type .

INPUT

Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle.

INPUT/
OUTPUT

DATA INPUT/OUTPUT.: Inputs data during memory write cycles; outputs data
during memory read cycles. The data pins,are active high and float to tri-state
OFF when the chip is deselected or the outputs are disabled. Data is internally
latched during a write cycle.

CEo-CE3

INPUT

CHIP ENABLE: Activates each device's control logic, input buffers, decoders,
and sense amplifiers. Each Ijne is unique to one set of 2 devices (word). CEx is
active low; CEx high deselects the memory device and reduces power
consumption to standby levels. Only one CEx may be active at a time.

INPUT

OUTPUT ENABLE: Gates the devices outputs through the data buffers during a
read cycle. OE is active low.

WEH;WEL

INPUT

WRITE ENABLE controls writes to the control register and the array.
(WEH = High Byte; WEL = Low Byte)
Write enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE pulse.
NOTE: With Vpp S 6.5V, memory contents cannot be altered.

000- 0015

ERASE/PROGRAM POWER SUPPLY for writing the command register, erasing
the entire array, or programming bytes in the array (12V ± 5%).

Vpp

± 10%).

Vee

DEVICE POWER SUPPLY: (5V

Vss

GROUND.

NO INTERNAL CONNECTION to device. Pin may be driven or left floating.
Pin

Function

CE7

CE6

CE5

CE4

A22

A21

A20

A19

A,a

A17

RES

RESERVED for future product enhancements.

PD1-PD7

PRESENCE DETECT: Denotes word depth (512K) and access time of device.
See Table 3, "Presence Detect "PO" Pins" on Page 5.

6-112

"-+_f

i11-e-

iSM001FLKA

Table 3. Presence Detect "PD" Pins
MODULE CAPACITY IDENTIFICATION
MODULE CAPACITY
WORD DEPTH

PD6

PD2

PD1

NO MOOULE

256K/32M

512K/64M

1M/128M

2M/256M

4M/512M

8M/1G

16M/2G

MODULE SPEED IDENTIFICATION
MAXIMUM
ACCESS
TIME

PD7

PD5

PD4

PD3

>300 ns

300 ns

250 ns

200 ns

185ns

150 ns

135 ns

120 ns

100 ns

85 ns

70 ns

60 ns

50 ns

40ns

30 ns

= OPEN CIRCUIT ON MODULE
S = SHORT CIRCUIT TO GROUND ON MODULE
ND = NOT DEFINED

6·113

intJ

iSM001FLKA

SINGLE IN-LINE MEMORY MODULE
BOARD
'pc substrate: Glass Epoxy [0.05" + 0.004/- 0:003
nominal thickness]. The iSM001 FLKA low-profile
SIMM mounts easily between expansion slots. See
Appendix A for a list of 80-pin socket suppliers.

APPLICATIONS
With high density, nonvolatility, and extended «ycling
capability, Intel's iSM001 FLKA flash SIMMs offer an
innovative alternative to disk and battery-backed
static RAM.
Primary applications and operating systems can be
stored in .flash, eliminating the slow disk-to-DRAM
download process. Performance is dramatically enhanced and power consumption is reduced-a consideration particularly important in portable equipment. Flexibility is increased with Flash's electrical
chip erasure allowing in-system updates to operating
systems and application code.
In diskless workstations and terminals, network traffic is reduced to a minimum and systems are instanton. Reliability exceeds that of electro-mechanical
media. Often in these environments, power glitches
force extended re-boot periods for all networked terminals. This mishap is no longer an issue if boot
code, operating systems, communication protocols
and primary applications are flash-resident in each
terminal.
.
.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, Flash SIMMs provide a solid state alternative in a minimal form factor. Flash memory provides
higher performance, lower power consumption and
instant-on capability; Additionally, flash is more rugged and reliable in harsh environments where extreme temperatures and shock can cause diskbased systems to fail.
For systems currently using a high-density static
RAM/battery configuration for code updates and
data accumulation, flash memory's inherent nonvolatility eliminates the need for battery backup. The
possibility of battery failure is removed. This consideration is important for portable equipment and medical instruments, both requiring continuous performance. In addition, flash memory offers a four-to-one
cost advantage over SRAM.
Flash memory's electrical chip erasure, byte reprogrammability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a "blank-slate" in
which to log or record data. Data can be periodically
off-loaded for analysis-erasing the slate and repeating the cycle.

Flash SIMMs add additional flexibility to designers
by offering end-users incremental expansion memo. ry. As code requirements grow or as memory prices
drop, your customers have the option of adding
more memory.

PRINCIPALS OF OPERATION
The iSM001 FLKA operates as eight N28F010 flash
memories connected as shown in the Functional
Block Diagram on Page 2.
The iSM001 FLKA, organized as 512K x 16, can also
be configured for 8- and 32-bit systems. For
32-bit systems, add a second SIMM to your design
as currently done with DRAM. For byte-wide operation, buffer the SIMMs DOo-D07 and D08-D015
lines with "an octal transceiver; then, tie the buffered
outputs together to form the 8-bit bus. Decode the
transceiver's enable input with an address line.
The iSM001 FLKA features hardware presence detect pins to facilitate memory design. The presence
detect pins (PD1-PD7) indicate module word depth
and maximum access speed (see Table 3 on the
previous page). The pins allow memory-specific
wait-state generation upon system initialization. To
use the presence capability, pull-up the PD1-PD7
lines through a pull-up resistor. Read the lines
through a port and select the appropriate memory
depth and speed from a PD data table.
In the absence of high voltage on the modules Vpp
pins, the iSM001 FLKA is a read-only memory array.
Manipulation of the module's control pins yields
standard read, standby and output disable functions.
Read, standby and output disable operations are
also available when high voltage is applied to the
Vpp pins. In addition, high voltage on the Vpp pins
enables erasure and programming of the module's
devices. All functions associated with altering the
memory contents of one or more devices-erase,
erase verify, program and program verify-are accessed via each flash device's command register.
Commands are written to a device's command register using standard microprocessor write timings.
Register contents serve as input to the devices internal state-machine which controls the erase and
programming circuitry. Write cycles to a device also
internally latch addresses and data needed for programming or erase operations. With the appropriate
command written to a device's register, standard microprocessor read timings output array data, access
the inteligent identifier codes, or output data for
erase and program verification.

6-114

iSM001FLKA

Table 4. Bus Operations
Pins

Vpp(1)

DQO-DQ15

Read

VPPL

VIL

VIH

Data Out

Output Disable

VPPL

VIL

VIH

Tri-State

Operation
READ-ONLY

READ/WRITE

Standby

VPPL

VIH

Read

VPPH

VIL

VIH

DataOut(3)

VIH

Tri-State

Output Disable

VPPH

VIL

Standby(4)

VPPH

VIH

Tri-State

Write

VPPH

VIL

VIH

VIL

Data In(5)

NOTES:
1. Refer to DC Characteristics. When Vpp = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes are accessed via a command register write sequence. Refer to Table 5. All other addresses are low.
.
3. Read operations with Vpp = VPPH may access array data or the inteligent IdentifierTM codes.
4. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
5. Refer to Table 5 for valid Data-In during a write operation.
6. X can be VIL or VIH.

Integrated Stop Timer
Successive command write cycles define the duration of program and erase operations; ,specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus elimi-.
nating the need for maximum program/erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command.

Write Protection
A device's command register is only active when
Vpp is at high voltage. Depending upon the application, the system designer may choose to make the
Vpp power supply switchable-available only when
memory updates are desired. When Vpp = VpPL,
the contents of the register default to the read command, making the iSM001 FLKA a read-only memory. In this mode, the memory contents cannot be
altered.
Or, the system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly

available. In this instance, all operations are performed in conjunction with the command register.
The iSM001 FLKA is designed to accommodate either design practice, and to encourage optimization
of flash's processor-memory interface.
The following section first discusses byte-wide organization, building a basic understanding of byte-wide

bus operations, command definitions, and programming and erasure algorithms. The section concludes
with performance enhancements for both 16- and
32-bit systems.

BUS OPERATIONS
Read
Each of the iSM001 FLKA's flash memory devices
has two control functions, both of which must be
logically active, to obtain data. Chip-Enable (CEx) is
the power control and should be used for device
selection. Four chip enables (CEo-CE3) control the
array's eight devices. Each line is unique to one set
of two devices (word). Only one CEx may be active
at a time.
Output-Enable (OE) is'the output control and should
be used to gate data from a device to the output pins
on the module, independent of device selection.
One OE line serves the iSM001 FLKA's flash devices. Figure 7 illustrates read timing waveforms.
When the Vpp lines are high (VPPH), a read operation can be used to access array data, to output a
device's inteligent identifier™ code, and to access a
device's data for program/erase verification. When
Vpp is low (VppU, a read operation can only access
array data.

Output Disable
With the iSM001FLKA's Output-Enable pin at a logic-high level (VIH), outputs from all devices are disabled. They are placed in a high-impedance state.

6-115

inter

iSM001FLKA
A device's command register itself does not occupy
an addressable memory location. The register is a
latch used to store the command, along with address and data information needed to execute the
command.

STANDBY
With Chip-Enable at a logic-high level, the standby
operation disables most of the deselected devices
circuitry and substantially reduces device power
consumption. The outputs of the deselected devices
are place in a high-impedance state, independent of
the Output-Enable signal. If a word is deselected
during erase, programming, or program/erasure verification, the device draws active current until the operation is terminated.

Two write enable lines are provided, WEH and
WEL, allowing selective write control of upper
and lower bytes.

Inteligent IdentifierTM Operation
The inteligent identifier operation outputs the selected devices' l'T)anufacturer code (89H; and device
code (B4H). The manufacturer code and device
code are read via the devices' command' register,
Following a write of 90H to a device's command reg~
ister, a read from address location OOOOH outputs
the manufacture code (89H). A read from address
0001 H outputs the device code (B4H).

A device's command register is written by selecting
the device (Chip-Enable low), then bringing WriteEnable (WEH or WEll to a logic-low level (VILl. If
both WE lines are a logic low, both upper and lower
bytes are written. Addresses are latched on the fall-'
ing edge of the Write-Enabie signai, whiie data is
latched on the rising edge of the Write-Enable pulse.
Standard microprocessor write timing are \,lsed.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing parameters.

Write

COMMAND DEFINITIONS

Erasure and programming is accomplished via each
device's command register, when high voltage is applied to the Vpp pins. The contents of each device's
register serve as input to its internal state-machine.
The state machine outputs dictate the function of
each device.

When low voltage is applied to the module's Vpp
pins, the 'contents of all devices' command registers
default to OOH, enabling read-or:1ly operatioris.
Placing high voltage on the module's Vpp pins allows read/write operation on selected devices. OPerations are selected by writing specific data patterns to the device(s) commarid register. Table 5 defines these register commands.

Table 5. Command Definitions
Command
Read Memory
Read inteligent identifier™ Codes(4)
Set-up Erase/Erase(5)
Erase Verify(5)
Set-up Program/Program(6)
Program Verify(6)
Reset(7)

Bus
Cycles
First Bus Cycle
Second Bus Cycle
Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3
1
3
2
2
2
2
2

Write
Write
Write
Write
Write
Write
Write

X
X
X
EA
X
X
X

OOH
90H
20H
AOH
40H
COH
FFH

Read
Write
Read
Write
Read
Write

NOTES:'
1. Bus operations are defined in Table 4,
2. lA' = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write· Enable pulse.
3. 10 = Data read from location IA during device identification (Mfr = 89H, Device B4H).
EVD = Data read from location EA during erase verify.
PO = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read inteligent 10 command, two read operations access manufacturer and device codes.
5. Figure 4 illustrates the Quick-Erase™ Algorithm.
'
6. Figure 3 illustrates the Quick-Pulse Programming™ Algorithm.
7. The second bus cycle must be followed by the desired command register write.

6-116

(4)

X
X
PA
X
X

20H
EVO
PO
PVO
FFH

:--1. r
111'eI

iSM001FLKA

with the rising edge of the next Write-Enable pulse
(Le., Erase-Verify Command).

Read Command
While Vpp is high, for erasure and programming, the
selected devices memory contents can be accessed
via the read command. The read operation is initiated by writing OOH into the command register of each
device. Microprocessor read cycles retrieve array
data. The selected devices remain enabled for reads
until their command register contents are altered.

This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pins. In the
absence of this high voltage, memory contents are
protected against erasure. Refer to AC Erase Characteristics and Waveforms for specific timing param-

The Uldictuii t;UIIi.~lliti UI t:dd-, Jt;,Vil..t:J'~ (aJ.-(I.-.-ICii-IU
register upon Vpp power-up is OOH. This default value ensures ,that no spurious alteration to the
iSM001 FLKA's memory contents occurs during the
Vpp power transition. Where the Vpp supply is hardwired to the iSM001 FLKA's Vpp pins, all eight devices power-up and remain enabled for reads until their
command-register contents are changed. Refer to
the AC Read Characteristics and Waveforms for
specific timing parameters.

inteligent Identifier™ Command
Flash memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system.
Each flash memory device contains an inteligent
Identifier operation. The operation is initiated by writing 90H into the command register. Following the
command write, a read cycle from address OOOOH
retrieves the manufacturer code of 89H. A read cycle from address 0001 H returns the device code of
B4H. To terminate the operation, it is necessary to
write another valid command into the register.
The inteligent Identifier and the Presence Detect
pins give you complementary information. While the
PO pins denote speed and depth, the inteligent Identifier operation gives you manufacture and device
data.

Set-Up Erase/Erase Commands
Set-up Erase is a command-only operation that
stages a selected device for electrical erasure of all
bytes in its array. The set-up erase operation is performed by writing 20H to the command register.

..................,.
..............

Erase-Verify Command
The erase command erases all bytes of the selected
device(s) in parallel. After each erase operation, all
bytes must be verified. The erase verify operation is
initiated by writing AOH into the command register of
the device. The address for the byte to be verified
must be supplied as it is latched on the falling edge
of a Write-Enable pulse. The register write terminates the erase operation with the rising edge of its
Write-Enable pulse.
Each 28F010 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte of the device until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes of
the device have been verified, the erase step is
complete. The device can be programmed. At this
point, the verify operation is terminated by writing a
valid command (e.g., Program Set-up) to the command register of the device. Figure 4, the QuickErase™ algorithm, illustrates how commands and
bus operations are combined to perform electrical
erasure of each 28F010. Refer to AC Erase Characteristics and Waveforms for specific timing parameters.

Set-Up Program/Program Commands
To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of a
Write-Enable pulse (WEH or WEll and terminates

Set-up program is a command-only operation that
stages a device for byte programming. Writing 40H
into the command register of the device performs
the set-up operation.

6-117

inter

iSM001FLKA

Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched 6n the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable ·also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters.
.

EXTENDED ERASE/PROGRAM CYCLING

Frogriim-Veriiy Command

creaSing memory cell size

EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some
suppliers have implemented redundancy schemes,
reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubled-an expensive solution.
Intel has designed extended cycling capability into
its ETOX II flash memory teqhnology. Resulting improvements in cycling reliability come without inOi

complexity. Fiist, an

advanced tunnel oxide increases the charge· carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately
2 MV/cm lower than EEPROM. The lower electric
field greatly reduces oxide stress and the probability
of failure-increasing time to wearout by a factor of
100,000,000.

Each 28F010 is programmed on a byte-by-byte basis. Byte programming may occur sequentially or at
random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register of the device. The
register write terminates the programming operation
with the rising edge of its Write-Enable pulse. The
program-verify operation stages the device for verification of the byte last programmed. No new address
information is latched.
Each 28F010 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 3,
the Quick-Pulse Programming™ algorithm (8-bit
Systems), illustrates how commands are combined
with bus operations to perform byte programming.
Refer to AC Programming Characteristics and
Waveforms for specific timing parameters.

Reset Command
A reset command is provided as a means to safely
abort the erase- or program-command sequences to
a device. Following either set-up command (erase or
program) with two consecutive writes of FFH will
safely abort the operation. Memory contents will not
be altered. A valid command must then be written to
place the device in the desired state.

Each of the iSM001 FLKA's eight 28F010s is specified for a minimum of 10,000 program/erase cycles.
Each device is programmed and erased using Intel's
Quick-Pulse Programming and Quick-Erase algorithms. Intel's algorithmic approach uses a series of
operations (pulses), along with byte verification, to
completely and reliably erase and program the device.
For further information, see Reliability Report RR-60
(ETOX II Reliability Data Summary).

QUICK-PULSE PROGRAMMINGTM. ALGORITHM
The Quick-Pulse Programming algorithm uses programming operations of 10 /-Ls duration. Each operation is follQwed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with Vpp at high voltage. Figure 3 illustrates the Quick-Pulse Programming algorithm for
8-bit systems.

6-118

inter

iSM001FLKA

QUICK-ERASETM ALGORITHM

Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming™ algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
iSM001 FLKA is erased when shipped from the factory. Heaolng I"FH data from each device wouid immediately be followed by device programming.

Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last by1e verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 4 iiiustrates the uuick-i::rase aigoriihm
for B-bit systems.

6-119

intJ

iSM001FLKA

Bus
Operation Command

Standby

Comments

Wait for VPP Ramp to VPPH(I)

Initialize Pulse·Count

Write

Set·up
Program

Data = 40H

Write

Program

Valid Address/Data

Standby
Write

Duration of Program
Operation (tWHWH1)
Program(3) Data = COH; Stops Program
Verify
Operation(4)

Standby

tWHGL

Read

Read Byte to Verify
Programming

Standby

Compare Data Output to Data
Expected

Write

Standby

Read

Data = OOH, Resets the
Register for Read Operations
Wait for VPP Ramp to VppL<2)

290244-3

NOTES:
1. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de·
vice.
2. See DC Characteristics for value of Vi'PH and VPPL.

3. Program Verify is only performed after byte program·
mingo A final read/compare may be performed (optional) after the register is written with the Read command.
4. Refer to principles of operation

Figure 3. Quick-Pulse Programming™ Algorithm (8-Bit Systems)

6-120

iSM001FLKA

Bus
Command
Operation

Comments

Entire Memory Must = OOH
Before Erasure

Use Quick-Pulse
Programming™ Algorithm
(Figure 4)
Standby

Wait for Vpp Ramp to VpPH(2)

Initialize Addresses and
Pulse-Count

Write

Set-up
Erase

Data = 20H

Write

Erase

Data = 20H
Duration of Erase Operation
(tWHWH2)

Standby

Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(4)
tWHGL

Read

Read Byte to Verify Erasure

Standby

Compare Output to FFH
Increment Pulse-Count

Write

Write
Standby

290244-4
NOTES:
1. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the dev/ee.
2. See DC Characteristics for value of VPPH and VPPL.

Erase(S)
Verify

Read

Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to VppLl2)

S. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
4. Refer to principles of operation.

Figure 4. Quick-Erase™ Algorithm (8-Bit Systems)
6-121

iSM001FLKA

HIGH PERFORMANCE PARALLEL
DEVICE ERASURE

HIGH PERFORMANCE PARALLEL
DEVICE PROGRAMMING

Total erase time for the SM28F001AX is reduced by
implementing a parallel erase algorithm (Note 1).
You save time by erasing all devices at the same
time. However, since flash memories may erase at
different rates, you must verify each device separately. This can be done in a word-wise fashion with
the command register Reset command and a special masking algorithm.

Software for word- or double-word programming can
be written in two different manners. The first method
offers simplicity of design and minimizes software
overhead by using a byte programming routine on
each device independently (using host CPU's byte
addressing mode). The second method offers higher
performance by programming the word or doubleword data in parallel. This method manipulates the
command register instructions for independent byte
control. See Figure 6 for conceptual 2-device parallel programming flow chart and Appendix C for the
detailed version. Here you can use the host CPU's
appropriate word- or double-word addressing modes
(Le., incrementing by 2- or 4-byte addresses, respectively).

Take for example the case of two-device (parallel)
erasure. The CPU first writes the data word erase
command 2020h twice in succession. This starts
erasure. After 10 ms, the CPU writes the data word
verify command AOAOh to stop erasure and setup
erase verification. If both bytes are erased at the
given address, then the CPU increments the address (by 2) and then writes the verify command
AOAOh again. If neither byte is erased, then the CPU
issues the erase sequence again without incrementing the address.

NOTE:
Word or double-word programming assumes 2 or 4
8-bit flash memory devices.

Parallel Programming Algorithm Summary:
Suppose at the given address only the low byte verifies FFh data? Could the whole chip be erased? The
answer is yes. Rather than check the rest of the low
byte addresses independently of the high byte, simply use the reset command to mask the low byte
from erasure and erase verification on the next
erase loop. In this -example the erase command
would be 20FFh and the verify command would be
AOFFh. Once the high byte verifies at that address,
the CPU modifies the command back to the default
2020h and AOAOh, increments the address by 2, and
writes the verify command to the next address.
See Figure 5 for a conceptual view of the parallel
erase flow chart and Appendix B for the detailed version. These flow charts are for 16-bit systems and
can be e~panded for 32-bit designs.

Decreases programming time by programming 2
flash memories (16 bits) .in parallel. The algorithm
can be expanded for 32-bit systems.
• Eliminates tracking of high/low byte addresses
and respective number of program pulses by directing the CPU to write data-words (16-bit) to the
command register.
.• Maintains word write and read operations. Should
a byte on one device program prior to a byte on
the other, the CPU continues to write word-commands to both devices. However, it deselects the
verified byte with software commands. An alternative is to independently program high and low
bytes using hardware select capability (byte-addressing mode of host CPU).

NOTE:
1. Parallel Erasure and Programming require appropriate choice of Vpp supply to support the increased power consumption.

6-122

iSM001FlKA

RAISE Vpp
PROGRAM ALL DEVICES TO OOh
RESET ALL VARIABLES
ISSUE ERASE COMMAND

TIME OUT

, . . . VERIFY COMMAND

BOTH DEVICES ERASED...!:!.... MASK"
HI-OR LO-BYTE
Y
COMMANDS

N LAST ADDRESS

LAST PULSE N

DONE

ERROR

290244-5

·You mask the device by substituting a Reset command for the Erase and Verify commands. That way, the erased byte
.
•
idles through the next erase loop.

Figure 5. High Performance Parallel Erasure (Conceptual Overview)

RAISE Vpp
GET ADDRESS/DATA WORD
RESET COMMAND AND
COUNTER VARIABLES
PROGRAM DATA - - - - - - - - - - - - - - - - ,
WORD

TIME OUT 10 ~s

STOP PROGRAMMING WITH
PROGRAM VERIFY COMMAND

DATA WORD PROGRAMMED? -

MASK HI OR LO BYTE
INCREMENT PULSE COUNTER

LAS~ PjULSE?

'------MORE DATA?

WRITE READ COMMAND
LOWER vpp
PROGRAMMING COMPLETE

WRITE READ COMMAND
LOWER Vpp
PROGRAM ERROR

290244-6

·You mask the device by substituting a Reset command for the Program and Verify commands. That way, the programmed bytes do not get further programmed on subsequent pulses.

Figure 6. Parallel Programming Flow Chart (Conceptual Overview)

6-123

iSM001FLKA

Power Up/Down Protection

DESIGN CONSIDERATIONS

The iSM001 FLKA is designed to offer protection
against accidental erasure or programming during
power transitions. Upon power-up, each 28F010 is
indifferent as to which power supply, Vpp or Vee,
powers up first. Power supply sequencing is not required. Internal circuitry in each 28F01 0 ensures that
the command register is reset to' the read mode on
power up.

Two-Line Output Control
Two-line control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.

A system designer must guard against active writes
for Vee voltages above VLKO when Vpp is active.
Since both WE and CE must be low for a command
write, driving either to VIH will inhibit writes. The control register architecture provides an added level of
protection since alteration of memory contents only
occurs after successful completion of the two-step
command sequences.

Power Supply Decoupling

Power Dissipation

Flash-memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current (led issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
. Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. The
iSM001 FLKA features a 0.1 /-LF ceramic capacitor
connected be~ween Vee and Vss, and between Vpp
and Vss.

When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your' system because each
28F010 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating each 28F010.
Table 4. 28F010 Typical Update Power
. Dissipation(4)

Also, a 4.7 /-LF tantalum capaqitor decouples the array's power supply between Vee and Vss and between Vpp and Vss. The bulk capacitors will overcome voltage slumps caused by printed-circuitboard trace inductance, and will supply charge to
the smaller capacitors as needed.

Operation

Power
Dissipation
(Watt-Seconds)

Array Program/Program Verify(1)

0.171

Array Erase/Erase Verify(2)

0.136

One Complete Cycle(3)"

0.478

NOTES:

Vpp Trace on Printed Circuit Boards
. Programming flash memories, while they reside in
the target system, requires that the printed circuit
, board designer pay attention to the Vpp power supply trace. The two Vpp pins supply current for programming. Use similar trace widths and layout considerations given the Vee power bus. Adequate Vpp
supply traces and decoupling will decrease Vpp voltage spikes and overshoots. Be sure to connect both
module Vpp inputs to your 12V supply.

1. Formula to calculate typical Program/Program Verify
Power = [Vpp x # Bytes x typical # Prog Pulses
(twHWH1 x IpP2typicai + tWHGL X IpP4 typical)) + [Vcc
x # Bytes x typical # Prog Pulses (tWHWH1 x ICC2 typical + tWHGL x ICC4 typical].
2. Formula to calculate typical Erase/Erase Verify Power
= [Vpp (VPP3 typical x tERASE typical + IpP5 typical x
tWHGL X # Bytes)] + [VCC (ICC3 typical x tERASE typical
+ ICC5 typical x tWHGL X # Bytes)).
3. One Complete Cycle = Array Preprogram + Array
.
Erase + Program.
4. "Typicals are not guaranteed but based on a limited
number of samples taken from production lots.

6-124

iSM001FLKA

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Operating Temperature
During Read .. '.' .............. O°C to + 70°C(1)
During Erase/Program ........... O°C to + 70°C
Storage Temperature .......... - 50°C to

+ BO°C
+ 100°C

Voltage on Any Pin with
Rp."l!1p.r.t to Grnllnn .......... - 2.0V to

+ 7.0V(2)

Temperature Under Bias ......... -10°C to

Vpp Supply Voltage with
Respect to Ground
During Erase/Program .... - 2.0V to

+ 14.0V(2, 3)

Vee Supply Voltage with
Respect to Ground '" ........ - 2.0V to

+ 7.0V(2)

Output Short Circuit Current ......... " ... 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is - 0.5V. During transitions, inputs may undershoot to - 2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for
periods less than 20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods less than 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING CONDITIONS
Symbol

Limits

Parameter

Operating Temperature

Vee

Vee Supply Voltage

Unit

Comments

°c

For Read-Only and
Read/Write Operations

5.50

Min

Max

0
4.50

6-125

intJ

iSM001FLKA

DC CHARACTERISTICS-TTL/NMOS COMPATIBLE
Symbol

Parameter

Notes

limits
Min

Typ

Max

Unit

Test Conditions

Input Leakage Current

±8.0

,...A

Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Curre,nt

±40.0

,...A

Vee = Vee Max
VOUT = Vee or Vss

Ices

Vee Standby Current

1,3

8.0

Vee = Vee Max
CE = VIH

leel

Vee Active Read Current

2,3

Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 mA

lee2

Vee Programming Current

2,3

8.0

Programming in Progress

lee3

Vee Erase Current

2,3

16.0

Erasure in Progress

lee4

Vee Program Verify Current

2,3

16.0

Vpp = VPPH
Program Verify in Progress

lee5

Vee Erase Verify Current

2,3

16.0

Vpp = VPPH
Erase Verify in Progress

Ipps

Vpp Leakage Current

±80

,...A

Vpp::;; Vee

IpPl.

Vpp Read Current
or Standby Current

1.6

Vpp> Vee

0.7

±80

,...A

Vpp::;; Vee

IpP2

Vpp Programming Current

2,3

16.5

61.2

Vpp = VPPH
Programming in Progress

IpP3

Vpp Erase Current

2,3

12.5

61.2

Vpp = VPPH
Erasure in Progress

IpP4

Vpp Program Verify Current

2,3

4.5

11.2

Vpp = VPPH
Program Verify in Progress

IpP5

Vpp Erase Verify Current

2,3

4.5

11.2

Vpp = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOHl

Output High Voltage

2.4

VPPL

Vpp during Read-Only
Operations

0.00

VPPH

Vpp during Read/Write
Operations

11.40

VLKO

Vee Erase/Write
Lock Voltage

Vee

+ 0.5

IOL = 5.8mA
Vee = Vee Min

IOH = -2.5mA
Vee = Vcc Min

6.5

NOTE: Erase/Program are
Inhibited when Vpp = VPPL

12.60

0.45

2.5

NOTES:
1. Vee standby current for 8 devices.
2. Calculations assume only the 2 devices of the 16-bit word are enabled. The remaining 6 devices are in standby.
Current will be higher if interleaving is used.
3. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25°C. These currents
are valid for all product versions (packages and speeds).

6-126

infei

iSM001FLKA

DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol

Parameter

Notes

Limits
Min

Typ

Max

Unit

Test Conditions

III

Input Leakage Current

±8.0

/k A Vee = Vee Max
VIN = Vee or Vss

ILO

Output Leakage Current

±40.0

/k A Vee = Vee Max
VOUT = Vee or Vss

1 ___

\1 __ CO"" __ ...IL,,,... ,... ........... _ ...

'ljlj::;

VLv

'VLQIIUUy VUIIOIII.

0.420.3

',u

c.e

rnA

_ _ _ \ I __ AA,....,

..!.!.i.lj

LA;

IVIa.,..

= Vee ±0.2V
Vee = Vee Max, CE = VIL
f = 6 MHz, lOUT = 0 rnA
CE

60.6

rnA

2.3

20.6

rnA Programming in Progress

10.3

30.6

rnA Erasure in F;lrogress

10.3

30.6

rnA VPP = VPPH
Program Verify in Progress

2,3

10.3

30.6

rnA VPP = VPPH
Erase Verify in Progress

±80
3

0.7

/k A VPP::;; Vee
rnA Vpp> Vee

lee1

Vee Active Read Current

2,3

lee2

Vee Programming Current

2,3

lee3

Vee Erase Current

2,3

lee4

Vee Program Verify Current

2,3

lee5

Vee Erase Verify Current

Ipps

VPP Leakage Current

IpP1

VPP Read Current
or Standby Current

1.6
±80

/k A VPP s Vee
rnA VPP = VPPH
Programming in Progress

IpP2

VPP Programming Current

2,3

16.5

61.2

IpP3

VPP Erase Current

2,3

12.5

61.2

rnA VPP = VPPH
Erasure in Progress

IpP4

VPP Program Verify Current

2,3

4.5

11.2

rnA VPP = VPPH
Program Verify in Progress

IpP5

VPP Erase Verify Current

2,3

4.5

11.2

rnA VPP = VPPH
Erase Verify in Progress

VIL

Input Low Voltage

-0.5

VIH

Input High Voltage

0.7 Vee

VOL

Output Low Voltage

0.8
Vee

+ 0.5

0.45

V·
V
V

VOH1
Output High Voltage

0.85 Vee

VpPL

VPP during Read-Only
Operations

0.00

6.5

VPPH

VPP during Read/Write
Operations

11.40

12.60

VLKO

Vee Erase/Write
Lock Voltage

2.5

IOH = - 2.5 rnA,
Vee = Vee Min
IOH = -100/kA,
Vee = Vee Min

Vee - 0.4

VOH2

IOL = 5.8 rnA
Vee = Vee Min

NOTE: Erase/Program are
Inhibited when VPP = VPPL

6-127

iSM001FLKA

CAPACITANCE(1) TA = 25°C, f = 1.0 MHz
Symbol

Parameter

Limits

Notes
Min

Unit

Conditions

Max

CIN1

Address Capacitance

VIN = OV

CIN2

Control Capacitance

VIN = OV

COUT

Output Capacitance

VOUT = OV

NOTES:
1. Trace capacitance calculated, not measured.
2. Address and control capacitance of a typical device is 6 pF.
3. Output capacitance of a typical device is 12 pF.

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ....•........... 0.45V and 2.4V
Input Timing Reference Level .....•. 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 2.0V

AC CHARACTERISTICS-Read-Oniy Operations(2)
Versions
Symbol

Notes
. Characteristic

ISM001FLKA-120 Min
120

iSMOO1FLKA-200
Min

Unit

Max

tAVAV/tRC

Read Cycle Time

tELQV/tCE

Chip Enable
Access Time

120

200

tAVQv/tACC

Address Access
Time

120

200

tGLQv/tOE

Output Enable
Access Time

tELQX/tLZ

Chip Enable to
Output in LowZ

tEHQZ

Chip Disable to '
Output in High Z

tGLQx/toLZ

Output Enable to
Output in Low Z

tGHQZ/tDF·

Output Disable to
Output in High Z

toH

Output Hold from
Address, CE,
orOEChange

tWHGL

Max

Write Recovery
Time before
Read

0
55

0
4

200

55
0

-30

ns
ns

,...s

NOTES:
1. Whichever occurs first.
2. Rise/Fall Time S; 10 ns.
3. Not 100% tested: Characterization data available ..
4. Guaranteed by design.

6-128

cl
Vce POWER-UP
X

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENABLED

DATA VALID

---

ADDRESSES

---

Vee POWER-DOWN

ADDRESS STABLE

r
~
c

STAtlDBY

tAyAy (tRe)

CE (f)

:"'I

»
0

---

=e
~

..
-..
!t

~ 3
(/I

I\)

I-

:D
CD
1\1

'/ "

60
50
40

I '

20
10

III

I :1

28F010-120/150

28FOlO-200

f--

2345678910

CHIP ERASE T1ME (SEC)

,----~'-

12V,10 ke,23C
11.4V:l0 ke,OC
12V,I00 ke,23C

290244-10

Figure 10. 28F010 Typical Erase Capability
3.2

3.D

i\
~

2.8

2.6

...,,2.4

...j!2.2

II)

...

1',

II)

S2.0
e,

1.8
1.6

"Ii'

',r-....

',- ~

t"'- r--..... "
~'"
..... r---.

1.4

1.2

1.0
o

"..
~

I"- ~

......

"- -..

--..... ..

40 50 61) 70 80 90 100 110 120 130 140
TEMP ("1:)
-lkC)'ctes
----10k Cyell.
-_.- lOOk Cycloo

Figure 11. 28F010 Typical Erase nme at 12!OV

6-132

290244-11

~.
SET-UP PIWGRAW
COMWAND

Vce POWER-UP &;
STANDBY

PROGRAM COMMAND
LATCH ADDRESS &; DATA

PROGRAWMING

PROGRAI.!
VERlrY
COI.!MAND

PROGRAW
VERIfiCATION

STANDBY/
Vee POWER- DOWN

ADDRESSES

~I
c

cr(E)

;;

....

:e I
~~
0'

OE (G)

---l
I

m 03
~ -

~~ ~~

'GHWL

-en

I GHQZ

I WHGL

3:
0

(lor)

~
~

WE (W)

aiil

Iwu"v

3
3

~. I

DATA (DQ)

I--~:;-

t ';: J~
I

""y
Vpp

pPL
V

"----290244-12

SET-UP ERASE
COMMAND

Vee POWER-UP &:
STANDBY

ERASE COMMAND

ERASE
VERIFY
COMMAND

ERASING

(

ERASE
VERIFICATION

ADDRESSES

CE (E)
"11

c·
C
~
CD

..~

OE (G)

~
Co)
.f>.

1-1 I

il
0

'GHWL

tWHWL (tWPH )

I·

tWHWH2

en
s:::

tWHGL

...
o

(Vi)

'TI

0!:til
I»

"»

-nLnn I

1...-1••••••"

1...-1......"

I...- tWHDX

1/1

DATA (DQ)

HIGH Z

I»

O·
~

1/1

5.0V
Vee
OV
t VPEL
120V

I---

Vpp
VpPL
290244-13

iSM001FLKA

ALTERNATIVE CE-CONTROLLED WRITES
28F010-120

Versions
Symbol

Characteristic

Notes

Min

Max

28F010-200
Min.

Unit

Max

tAVAV

Write Cycle Time

120

200

tAvEL

Address Set-Up Time

tELAX

Address Hold Time

tDVC::

De.te. Set-Up Time

!"'!S

tEHDX

Data Hold Time

tEHGL

Write Recovery Time
before Read

,""S

tGHEL

Read Recovery Time
before Write

,""S

tWLEL

Write Enable Set-Up Time
before Chip Enable

tEHWH

Write Enable Hold Time

tELEH

Write Pulse Width

tEHEL

Write Pulse Width High

tVPEL

Vpp Set-Up Time to Chip

1.0

,""S

Enable Low
NOTE:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set~up, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
.

6-135

(

»z

;::;:0

CD-I

l» ••

Vee POWER-UP ole
STANDBY

SET-uP PROGRAM
COMMAND

PROGRAM COMMAND
LATCH ADDRESS ole DATA

PROGRAMMING

PROGRAM
VERIFY
COMMAND

PROGRAM
VERIFICATION

STANDBY/
Vee POWER-DOWN

-«

(:)

ADDRESSES

::!!
cc

......

»
;:;:

.
CD
::J

3Q.
:::E
::::!.
128 K-Bytes/Sec

Protect Switch to Prevent
• Write
Accidental Data Loss
Command Register Architecture jor
• Microprocessor/Microcontroller

•

Compatible Write Interface
ETOX™ II Flash Memory Technology
- 5V Read, 12V Erase/Write
- High-Volume Manufacturing
Experience

58-Pin Standard
• -PCMCIA/JEIDA
Byte- or Word-wide Selectable
Independent Software & Hardware
• Vendor
Support
- Integrated System Solution Using
Flash Filing Systems

Writes to Erased Zones
• -Random
10 fls Typical Byte Write

Intel's Flash Memory Card is the integrated memory solution for portable PCs. The iMC001 FLKA enables
OEM system manufacturers to design portable PCs that no longer require rotating electro-mechanical media
to store application code and data files. This allows the design and manufacture of PCs that are higher
performance, more rugged, consume less battery power, and weigh much less than traditional disk-based
portable PCs. The flash memory card supports the emerging "Mobile Office" by allowing the user to transport
both application code and data files between desktop PCs and portables.
The iMC001 FLKA conforms to the PCMCIA/JEIDA international standard, providing compatibility at the
hardware and data interchange level. OEMs may opt to write the Card Information Structure (CIS) at the
memory card's address OOOOOH with a format utility. This information provides data interchange functional
compatibility. The 250 nanosecond access time allows for "execute-in-place" capability, for popular lowpower microprocessors .. Intel's 1-Megabyte Flash Memory Card operates in a byte-wide and word-wide
configuration providing performance/power options for different systems.
Intel's Flash Memory card employs Intel's ETOX II Flash Memories. Filing systems, such as Microsoft's'
Flash File System (FFS), facilitate sequential data file storage and card erasure using a purely nonvolatile
medium. Flash filing systems, coupled with the Intel Flash Memory Card, effectively create an all-silicon
nonvolatile read/write random access memory system that is more reliable and higher performance than
disk-based memory systems.
'Microsoft is a trademark of Microsoft Corp.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. October 1990
© INTEL CORPORATION, 1990
Order Number: 290399-001

6-143

iMC001FLKA

E
E
N

d
+1
II!

E
c

§.

:E
co

....d

o
1
2
3
4
5
·6
7
8
9
10
11
12
13
14
15
16
17

GNO
03
04
05
06
07
CE,
A,D
OE
A"
Ag
As
A13
A14
WE
NC
Vee

FRONT SlOE

188888888888888888888888888888888~

68 ~

BACK SlOE
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

VpP1
A'6
A'5
A'2
A7
A6
A5
A4
A3
A2
A,
AD
00
01
O2
WP
GNO

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

35
GNO
COl
0'1
0 12
013
0 14
0 15
CE 2
NC
NC
NC
A17
A1s
A19
NC
NC
V""

52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

Vpp2
NC
NC
NC
NC
NC
NC
NC
NC
REG1
BVO/
BVO/
Os
Og
010
CO2
GNO

NOTES:
1. REG = register memory select = No Connect (NC), unused. When REG is brought low, PCMCIAlJEIDA standard
card information structure data is expected. This is accomplished by formatting the card with this data.
2. BVD = battery detect voltage = No Connect (NC), unused.

, Figure 1. iMC001 FLKA Pin Configurations
6-144

iMC001FLKA

Table 1. Pin Description
Symbol

Type

Name and Function

Ao -A'9

INPUT

ADDRESS INPUTS for memory locations. Addresses are internally
latched during a write cycle.

0 0 -0'5

INPUT/
OUTPUT

DATA INPUT/OUTPUT: inputs data during memory write cycles; outputs
data during memory read cycles. The data pins are active high and float to
tri-state OFF when the card is deselected or the outputs are disabled.
Data is intema!!y iE'.tGhed riming;:! write cycle.

CE" CE,

INPUT

CARD ENABLE: activates the card's high and low byte control logic, input
buffers, zone decoders, and associated memory devices. CE is active
low; CE high deselects the memory card and reduces power consumption
to standby levels.

INPUT

OUTPUT ENABLE: gates the cards output through the data buffers during
a read cycle. OE is active low.

INPUT

WRITE ENABLE controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE pulse.
Note: With Vpp ,,;; 6.5V, memory contents cannot be altered.

Vpp " Vpp,

ERASE/WRITE POWER SUPPLY for writing the command register,
erasing the entire array, or writing bytes in the array.

Vee

DEVICE POWER SUPPLY (5V ± 5%).

GNO

GROUND

CO" CD,

OUTPUT

CARD DETECT. The card is detected at CD,., = ground.

OUTPUT

WRITE PROTECT. All write operations are disabled with WP = active high.
NO INTERNAL CONNECTION to device. Pin may be driven or left
floating.

NC
BVO" BVO,

OUTPUT

BATTERY VOLTAGE DETECT. NOT REQUIRED.

6-145

iMC001FLKA

°S-015

0 0 - 0 15

I/O TRANS- .00 - 0 7
CEIVERS WE
AND
BUFFERS OE

WE
OE

veer~,
~I
,
,

•..::......:..~RITE PROTECT
SWITCH

Ao-A16

A1 -A 19
CE2
CE 1

ADDRESS
BUFFERS
AND
DECODERS

CEHo•
CEH3
CELo•
CEL3

28F010

r- Ao -A16

28F010

00 - 07

..... I-- CE

-REG- -

COl

OE
V••

~-=

0S- 0 15 t-<

Vee Vpp1

V••

Vpp2

Vee

I I, I

A o -A 16

,.... Au-A16

0 0 -07

OE
BOV1

V••

Vee

Vpp1

BVO

Vee

..... f"- CE

GNO

Ao-A16

CARD DETECT

Vee
'B ATIERYVOLTAGE
DETECT

••
•

L~-A161 OO~07J

Z3
Vee

LA:~A16

••
•

Vpp2

Los_1015

' - - CE

OE
V••

Vee

WE
OE
V••

,--CE

0S- 0 15 t-<~

,I
Vpp1

I
..I..

VpP1
VpP2

Figure 2_ iMC001 FLKA Block Diagram

6-146

oq.s
I

Z7
Vee

Vpp2

iMC001FLKA

APPLICATIONS
The iMC001 FLKA Flash Memory Card allows for the
storage of data files and application programs on a
purely solid-state removable medium. System resident flash filing systems, such as Microsoft's Flash
File System, allow Intel's ETOX II highly reliable
Flash Memory Card to effectively function as a
physical disk drive. The Intel Flash Memory Card in
i:OiijUiictioii 'vA;ith f~ash fmiig :;~i:;tcm3 prc'v':dc:; er:
innovative alternative to both fixed hard disks
and floppy disks in DOS-compatible portable PCs.
User application software stored on the flash memory card substantially reduces the slow disk-DRAM
download process. Replacing the disk results in a
dramatic enhancement of read performance and
substantial reduction of active power consumption,
size, and weight - considerations particularly important in portable PCs and equipment. The
iMC001 FLKA's high performance read access time
and command register microprocessor write interface allows for use of the flash memory system in
an "execute-in-place" architecture. This configuration eliminates the need for the redundancy associated with DRAM and Disk memory system
architectures. ROM based operating systems, such
as·Microsoft's MS-DOS ROM Version allow for
"instant-an" capability. This enables the design of
PCs that boot, operate, store data files, and execute
application code from/to purely nonvolatile memory.

Flash filing systems implement Intel's Flash Memory
Card as a redirected disk drive; similar to structures
used in local area networks. This enables the end
user to interact with the flash memory card in precisely the same way as a magnetic disk. Filing systems that run under popular operating systems,
such as MS-DOS, can use the installed base of
application software.
Th<>. Mir.rn~nft Flash File Svstem enables the stor-

age and modification of data files by utilizing a linked
list directory structure that is evenly distributed
along with the data across the memory card. The
linked list approach minimizes file fragmentation
losses by using variable-sized data structures
rather than the standard sector/cluster method of
disk-based systems.
The integration of the PCMCl.A/JEIDA 68-pin interface with flash filing systems enables the end-user
to transport user files and application code between
portable PCs and desktop PCs with memory card
Reader/Writers. Intel Flash PC cards provide durable nonvolatile memory storage for Notebook PCs
on the road, facilitating simple. transfer back into the
desktop environment.

Flash write performance is often 50% higher than
hard disks for typical user file storage. This equates
to ten times more performance when compared to
"spun-down" disks, the common practice for portable machines.
Flash filing systems enable the storage and modification of data files by allocating flash Il)emory
space intelligently, thus minimizing the number of
rewrite cycles. This management function allows
tlie user to rewrite reliably to the flash memory card
many more times than a fixed or floppy disk which
concentrate rewrite operations into small fixed por.•
tions of the medium.

6-147

For systems currently using a static RAM/battery
configuration for data acquisition, the iMC001 FLKA's
inherent nonvolatility eliminates the need for battery
backup. The concern for battery failure no longer
exists, an important consideration for portable computers and medical instruments, both requiring continuous operation. The iMC001 FLKA consumes no
power when the system. is off. In addition, the
iMC001 FLKA offers a considerable cost and density advantage over memory cards based on static
RAM with battery backup.
The flash memory card's electrical zone-erasure,
byte writability, and complete nonvolatility fit well
with data accumulation and recording needs. Electrical zone-erasure gives the designer the flexibility
to selectively rewrite zones of data while saving
other zones for infrequently updated look-up tables.

iMC001FLKA

operation in that zone (or two 128 K-Byte zones
under word-wide operation).

PRINCIPLES OF OPERATION
Intel's Flash Memory Card combines the functionality of two mainstream memory technologies: the
rewritability of RAM and the nonvolatility of EPROM.
The flash memory card consists of an array of individual memory devices, .each of which defines a
physical zone. The iMC001 FLKA's memory devices
erase as individual blocks, equivalent in size to the
128 K-Byte zone. Multiple zones can be erased simultaneously provided sufficient current fO,r the appropriate number of zones (memory devices). Note,
multiple zone erasure requires higher current from
both the VPP and Vee power supplies. Erased zones
can then be written in bit- or byte-at-a-time fashion
and read randomly like RAM. Bit level write capa.
bility also supports disk emulation.
In the absence of high voltage on the VPP1I2 pins,
the iMC001 FLKA remains in the read-only mode:
Manipulation of the external memory card-control
pins yields the standard read, standby,and output
disable operations.
The same read, standby, and output disable operations are available when high voltage is applied to
the VPP '12 pins. In addition, high voltage on VPP1I2
enables erasure and rewriting of the accessed
zone(s). All functions associated with altering zone
contents - erase, erase verify, write, and write verify - are accessed via the command register.
Commands are written to the internal· memory register(s), decoded by zone size, using standard microprocessor write timings. Register contents for a
given zone serve as input to that zone's internal
state-machine which controls the erase and rewrite
circuitry. Write cycles also internally latch addresses
and data needed for write and erase operations.
With the appropriate command written to the register(s), standard microprocessor read timings output zone data, or output data for erase and write
verification.
Byte-wide or Word-wide Selection

The flash memory card can be read, erased, and
written in a byte-wide or word-widl!...!!'0de. In the
word-wide configuration VPP' and/or CE, control the
LO-Byte (with Ao =0) while VPP2 and CE 2control the
HI-Byte (Ao =don't care).
Read, Write. and Verify operations are byte- or
word-oriented, thus zone independent. Erase Setup and Begin Erase Commands are zone dependent such that commands written to any address
within a 128 K-Byte zone boundary initiate the erase

Conventional x8 operation uses CE,' active-low,
with CE2 high, to read or write data through the Do0 7 only.."Even bytes" are accessed when Ao is low,
corresponding to the low byte of the complete x16
word.When Ao is high, the "odd byte" is accessed
by transposing the high byte of the complete x16
word onto the 0 0 -0 7 outputs. This odd byte corresponds to data presented on Oe-O'5 pins in x16
mode.
Note that two zones logically adjacent in x16 mode
are multiplexed through 0 0 -07 in x8 mode and are
toggled by the Ao address. Thus, zone specific
erase operations must be kept discrete in x8 mode
by addressing even bytes only for one-half of the
zone pair, then addressing odd bytes only for the
other half.
Card Detection

The flash memory card features two card detect
pins (C0 1l2) that allow the host system to determind
if the card is properly loaded. Note that the two p'ins
are located at opposite ends of the card. Each CO
output should be read through a port bit. Should only
one of the two bits show the card to be present, then
the system should instruct the user to re~insert the
card squarely into the socket. Card detection can
also tell the system whether or not to redirect drives
in the case of system booting. C0 1l2 is active low,
internally tied to ground.
Write Protection

The flash memory card'features three types of write
protection. The first type features a mechanical
Write Protect Switch that disables the circuitry that
control Write Enable to the flash devices. When the
switch is activated, WE is forced high, which disables any writes to the Command Register. The
second type of write protection is based on the
PCMCIA/JEIOA socket. Unique pin length assignments provide protective power supply sequencing
during hot insertion and removal. The third type operates via software control through the Command
Register when the card resides in its connector. The
Command Register of each zone is only active when
VPPl12 is at high voltage. Depending upon the application, the system designer may choose to make
VPP1I2 power supply switchable - available only
when writes are desired. When VPP 'f2 = VPPL ' the
contents of the register default to the read command, making the iMC001 FLKA a read-only memory card. In this mode, the memory contents cannot
be altered.

6-148

iMC001FLKA

The system designer may choose to leave VPP1I2 =
VPPH ' making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever Vee is below the write
lockout voltage, VLKO • (See the section on Power
Up/Down Protection.) The iMC001 FLKA is designed to accommodate either design practice, and
to encourage optimization of the processor-memory
card interface.

BUS OPERATIONS

Intellgent Identifier" Command
The manufacturer- and device-codes can be read
via the Command Register, for instances where the
iMC001 FLKA is erased and rewritten in a universal
reader/writer. Following a write of 90H to a zone's
Command Register, a read from address location
OOOOOH on any zone outputs the manufacturer code
(89H). A read from address 0002H outputs the
memory device code (B4H).
Write

Read
The iMC001 FLKA has two control functions, both
of which must be logically active, to obtain data at
the outputs. Card Enable (CE) is the power control
and should be used forJ:!jgh and/or low zone(s) selection. Output Enable (OE) is the output control and
should be used to gate data from the output pins,
independent of accessed zone selection. In the
byte-wide configuration, only one CE is required.
The word-wide configuration requires both CEs
active low.
When VPP1I2 is high (V PPH ), the read operations can
be used to access zone data and to access data for
write/erase verification. When VPP1I2 is low (Vppd,
only read accesses to the zone data are allowed.
Output Disable

Zone erasure and rewriting are accomplished via
the Command Register, when high voltage is applied to VPP1I2 . The contents of the register serve
as input to that zone's internal state-machine. The
state-machine outputs dictate the function of the
targeted zone.
The Command Register itself does not occupy an
addressable memory location. The register is a
latch used to store the command, along with address and data information needed to execute the
command.
The Command Register is written by bringing Write
Enable to a logic-low level (V1L), while Card Enable(s) is/are low. Addresses are latched on the failing edge of Write Enable, while data is latched on
the riSing edge of the Write Enable pulse. Standard
microprocessor write timings are used.

With Output Enable at a logic-high level (VIH) , output
from the card is disabled. Output pins are placed in
a high-impedance state.

Refer to AC Write Characteristics and the ·Erase/
Write Waveforms for specific timing parameters.

Standby

COMMAND DEFINITIONS

With one Card Enable at a logic-high level, the
standby operation disables one-half of the x16 output's read/write buffer. Further, only tne zone correspondi!!9Jo the selected address within the upper
or lower CE'.2 bank is active at a time. (NOTE: At,
must be low to select the low half of the x16 word
when CE2 = 1 and CE, = 0.) All other zones are
deselect~d, substantially reducing card power consumption. For deselected banks, the outputs are
placed in a high-impedance state, independent of
the Output Enable signal. If the iMC001 FLKA is deselected during erasure, writing, or write/erase verification, the accessed zone draws active .current
until the operation is terminated.

When low voltage is applied to the Vpp pin(s), the
contents of the zone Command Register(s) default
to OOH, enabling read-only operations.

6-149

Placing high voltage on the Vpp pin(s) enable(s)
read/write operations. Zone operations are selected by writing specific data patterns into the
Command Register. Tables 3 and 4 define these
iMC001 FLKA register commands for both bytewide and word-wide configurations.

iMC001FLKA

Table 2. Bus Operations
Pins
" Operation

Notes

Read (x8)

[1,7]

VPP•

Vpp,

0.-0,.

CEo

CE,

VIL

V IL

VIH

HighZ

VP~L

VPPL

VIL

VIH

Oo-D7
Data Out-Even

Read (x8)

VPPL

VIH

VIL

,VIL

VIH

HighZ

Data Out-Odd

Read (x8)

VpPL

VP~L

VIL

VIH

VIL

VIH

Data Out

HighZ

«w

Read (x16)

VPPL

VIL

VIH

Data Out

Output Disable

VPPL

VIH

HighZ

Standby

VPPL

V~PL

VIH

HighZ

?J
z
6

II:

Read (x8)
Read (ie8)

,,'

Read (x8)

«w

II:

Vppx

VPPH

VIL

VIH

VIL

VIH

HighZ

Data Out-Even

3,9

VPPH ,

VpPX

VIH

VIL

VIH

HighZ

Data Out-Odd

VPPH

Vppx

VIL

VIH

VIL

VIH

Data Out

HighZ

VPPH

,VPPH

VIL

VI~

Data Out

Write (x8)

5;8

Vppx

VPPH

VI~

VIH

VIL

V'IH

. VIL

HighZ

Data In-Even

Write (x8)

VPPH

Vppx

VIH

VIL

VIH

'\IlL

HighZ

Data In-Odd

Write (x8)

VPPH

Vppx

VIL

VIH

VIL

Data In

HighZ

. Write (x16)

VPPH

VIL

VIH

VIL

Data In

'HighZ

HighZ

VIH

VIL

HighZ

1-. ,Read (x16)

3,8

3,11

Standby
Output Disable

VPPH

VIH

' VIH

VPPH

Notes:

1,. Refer to DC Characteristics. When VPP1I2 = VPPL memory contents can be read but not written or'erased.
2. Manufacturer and device codes may be accessed via a command register write sequence.
Refer io Table 3. All other addresses low. .
3. Read operations with VPP1I2 = Vpph may access array data or the Inteligent Identifier codes.
4. With VPP1I2 at high'voltage, the staridbycurrent equals Icc + Ipp (standby).
5. Refer to Table 3 for valid Data-In during a write operation.
6: X can be VIL or VIH .
7. Vppx = VPPH or V~PL'
.
8. This x8 operation' reads or writes the low' byte of the x16 word on DO()'7' I.e., AD low rellds "even" byte in xB mode.
9. This x8 operation reads or writes the high byte of the x16 word on DOo_7 (transpo~ed from D08-'5)' I.e., Ao high reads
'''odd'' byte in x8 mode.'
'
Hi; This x8 operation reads or writes the, high byte of the x16 on DO._'5' Ao is "don't care.'"
11. Ao is "don't care," unused in x16 mode. High and low bytes are presented simultaneously.

6-150

iMC001FLKA

Table 3, Command Definitions byte-wide mode

Command

Notes

Bus
Cycles
Req'd

Read Memory

First Bus Cycle

Second Bus Cycle

Operation(1(

Address(2(

Data(3(

Write

OOH

Write

90H

Read

Write

20H

Write

Operation(1(

Address(2)

Data(3)

20H

Read Inteligent ID Codes

Set-up Erase/Erase

Erase Verify

Write

AOH

Read

EVD

Set-up Write/Write

Write

40H

Write

Write Verify

Write

COH

Read

WVD

Reset

Write

FFH

Write

FFH

Table 4, Command Definitions word-wide mode

Notes

Bus
Cycles
Req'd
1

Write

OOOOH

Read Inteligent ID Codes

Write

9090H

Read

Set-up Erase/Erase

Write

2020H

Erase Verify

Write

AOAOH

Command
Read Memory

First Bus Cycle
Operation(1)

Second Bus Cycle
Data(3)

Address(2)

Data(3)

Write

2020H

Read

EVD

Operation(1)

Set-up Write/Write

Write

4040H

Write

Write Verify

Write

COCOH

Read

WVD

Reset

Write

FFFFH

Write

FFFFH

Notes:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
WA = Address of memory location to be written.
ZA = Address of 128 K-Byte zones involved in erase operation.
Addresses are latched on the falling edge of the Write Enable pulse:'

3. ID = Data read from location IA during device identification. (Mfr = 89H, Device = B4H).
EVD = Data read from location EA during erase verify.
WD = Data to be written at location WA. Data is latched on the rising edge of Write Enable.
WVD = Data read from location WA during write verify. WA is latched on the Write command.
4. Following the Read Inteligent ID command, two read operations access manufacturer find device codes.
5. Figure 5 illustrates the Erase Algorithm.
6. Figure 6 illustrates the Write Algorithm.
7. The second bus cycle must be followed by the desired command register write.

6-151

iMC001FLKA

Read Command

While VPP1I2 is high, for erasure and writing, zone
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH (OOOOH for the word-wide configuration) into
the zone Command Register(s). Microprocessor
read cycles retrieve zone data. The accessed zone
remains enabled for reads until the Command Register(s) contents are altered.
The default contents of each zone's register(s) upon
VPP1/2 power-up is OOH (OOOOOH for word-wide). This
default value ensures that no spurious alteration of
memory card contents occurs during the VPP1/2
power transition. Where the VPP1/2 supply is left at
V PPH , the memory card powers-up and remains
enabled for reads until the command Register contents of targeted zones are changed. Refer to the
AC Read Characteristics and Waveforms for specific timing parameters.
inteligent Identifier Command

Each zone of the iMC001 FLKA contains an intj;lligent Identifier to identify memory card device
characteristics. The operation is initiated by writing
90H (9090H for word-wide) into the Command Register(s). Following the command write, a read cycle
from address OOOOOH retrieves the manufacturer
code 89H (8989H for word-wide). A read cycle from
address 0002H returns the device code B4H
(B4B4H for word-wide). To terminate the operat!on,
it is necessary to write another valid command mto
the register(s).
Set-up Erase/Erase Commands

Set-up Erase is a command-only operation that
stages the targeted zone(s) for electrical erasure of
all bytes in the zone. The set-up erase operation is
performed by writing 20H to the Command Register
(2020H for word-wide).

To commence zone-erasure, the erase command
(20H or 2020H) must again be written to the register(s). The erase operation begins with the rising
edge of the Write-Enable pulse and terminates with
the rising edge of the next Write-Enable pulse (i.e.,
Erase-Verify Command).
This two-step sequence of set-up followed by execution ensures that zone memory contents are not
accidentally erased. Also, zone-erasure can only
occur when high voltage is applied to the VPP1/2 pins.
In the absence of this high voltage, zone memory
contents are protected against erasure. Refer to AC
'Erase Characteristics and Waveforms for specific
timing parameters.
Erase-Verify Command

The erase command erases all of the bytes of the
zone in parallel. After each erase operation, all
bytes in the zone must be individually verified. In
byte-mode operations, zones are segregated by Ao
in odd and even banks; erase and erase verify
operations must be done in complete passes of
even-bytes-only then odd-bytes-only. See the Erase
Algorithm for byte-wide mode. The erase verify
operation is initiated by writing AOH (AOAOH for
word-wide) into the Command Register(s). The address for the byte(s) to be verified must be supplied
as it is latched on the falling edge of the Write Enable
pulse. The register write terminates the erase operation with the rising edge of its Write Enable pulse.
The enabled zone applies an internally-generated
margin voltage to the addressed byte. Reading FFH
from the addressed byte indicates that all bits in the
byte are erased. Similarly, reading FFFFH from the
addressed word indicates that all bits in the word
are erased.
The erase-verify command must be written to the
Command Register prior to each byte (word) verification to latch its address. The process continues
for each byte (word) in the zone(s) until a byte (word)
does not return FFH (FFFFH) data, or the last
address is accessed.

6-152

iMC001FLKA

In the case where the data read is not FFH (FFFFH),
another erase operation is performed. (Refer to Setup Erase/Erase.) Verification then resumes from
the address of the last-verified byte (word). Once all
bytes (words) in the zone(s) have been verified, the
erase step is complete. The accessed zone can now
be written. At this point, the verify operation is terminated by writing a valid command (e.g., Write Setup) to the Command Register. The Erase algorithms
for byte-wide and word-wide configurations illustrate how commands and bus operations are
combined to perform electrical erasure of the
iMC001 FLKA. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.
Set-up Write/Write Commands
Set-up write is a command-only operation that
stages the targeted zone for byte writing. Writing
40H (4040H) into the Command Register(s) performs the set-up operation.
Once the write set-up operation is performed, the
next Write Enable pulse causes a transition to an
active write operation. Addresses are internally
latched on the falling edge of the Write Enable
pulse. Data is internally latched on the rising edge
of the Write Enable pulse. The rising edge of Write
Enable also begins the write operation. The write
operation terminates with,the next rising edge of
Write Enable, which is used to write the verify command. Refer to AC Write Characteristics and Waveforms for specific timing parameters.
Write Verify Command
The iMC001 FLKA is written on a byte-by-byte or
word-by-word basis. Byte or word writing may occur
sequentially or at random. Following each write
operation, the byte or word just written must be,
verified.
The write-verify operation is initiated by writing COH
(COCO) into the Command Register(s). The register
write(s) terminate(s) the write operation with the rising edge of its Write Enable pulse. The write-verify
operation stages the accessed zone(s) for verification of the byte or word last written. No new address information is latched. The zone(s) apply(ies)
an internally-generated margin voltage to the byte

6-153

or word. A microprocessor read cycle outputs the
data. A successful comparison between the written
byte or word and true data means that the byte or
word is successfully written. The write operation
then proceeds to the next desired byte or word location. The Write algorithms for byte-wide and
word-wide configurations illustrate how commands
are combined with bus operations to perform byte
and word writes. Refer to AC Write Characteristics
and Waveforms for specific timing parameters.
Reset Command
A reset command is provided as a means to safely
abort the erase- or write-command sequences. Following either set-up command (erase or write) with
two consecutive writes of FFH (FFFFH for wordwide) will safely abort the operation. Zone memory
contents will not be altered. A valid command must
then be written to place the accessed zone in the
desired state.

EXTENDED ERASE/WRITE CYCLING
Intel has designed extended cycling capability into
its ETOX II flash memory technology enabling a
flash memory card with a MTBF that is approximately 20 times more reliable than rotating disk
technology. Resulting improvements in cycling reliability come without increasing memory cell size or
complexity. First, an advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell subjected to the
tunneling electric field minimizes the probability of
oxide defects in the region. The lower electric field
greatly reduces oxide stress and the probability of
failure.

WRITE ALGORITHMS
The write algorithm(s) use write operations of 10fLS
duration. Each operation is followed by a byte or
word verification to determine when the addressed
byte or word has been successfully written. The algorithm(s) allows for up to 25 write operations per
byte or word, although most bytes and words verify
on the first or second operation. The entire sequence of writing and byte/word verification is performed with Vpp at high voltage.

iMC001FLKA

ERASE ALGORITHM
The Erase algorithm(s) yield(s) fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the write
algorithm, to simultaneously remove charge from all
bits in the accessed zorie(s).
Erasure begins with a read of memory zone contents. Reading FFH (FFFFH) data from the accessed zone(s) can be immediately followed by
writing to the desired zone(s).
For zones being erased and rewritten, uniform and
reliable erasure is ensured by first writing all bits in
the accessed zone to the.ir charged state (data =
OOH byte-wide, OOOOOH word-wide). This is accomplished, using the write algorithm, in approximately
two seconds per zone.

Erase execution then continues with an initial erase
operation. Erase verification (data = FFH bytewide, FFFFH word-wide) begins at address OOOOOH
and continues through the zone to the last address;
or until data other than FFH (FFFFH) is encountered. (Note: byte-wide erase operation requires
separate even- and odd-address passes to handle .
the individual 128 K-Byte zones.) With each erase
operation, an increasing number of bytes or words
verify to the erased state. Erase efficiency may be
improved by storing the address of the last by.te or
word verified in a register(s). Following the next
erase operation, verification starts at that stored address location. Follow this procedure untifall bytes
in the zone are erased. Then, re-start the procedure
for the next zone or word-wide zone pair. Erasure
typically occurs in one second per zone.

INITIALIZE SIZE
AND NUMBER OF ZONES
ZONE L = 0
ZONE H = 1

Figure 3. Full Card Erase Flow

6-154

iMC001FLKA

BUS
OPERATION COMMAND

Standby

COMMENTS

Wait for Vpp ramp
to VPPH (= 12.0V) [2]
Initialize pulse-count

Write

Set-up
Write

Write

= 40H

Valid address/data

Standby

Duration Of Write
operation (tWHWH1)
Write
Verify

Write

Data

[3]

Data = COH; Stops [4]
Write Operation

Standby

tWHGL

Read

Read byte to verify
Write Operation

Standby

Compare data output
to data expected

Write

Read

Standby

Data = OOH, resets the
register for read
operations.
Wait for Vpp ramp
to VPPL [2]

Notes:
1. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of
the device.

3. Write Verify is only performed after
a byte write operation. A final readlcom'pare
may be performed (optional) after the
,regIster is written with the Read command.

2. See DC Characteristics for the value of VPPH and VpPL•
4. Refer to principles of operation.

Figure 4. Write Algorithm for byte-wide mode

iMC001FLKA

BUS
OPERATION COMMANDS
Standby

COMMENTS
Wait for Vpp ramp
to VPPH (= 12.0V) [2)
Use Write Operation
Algorithm
Initialize even/odd
Addresses,
Erase Pulse Width,
and Pulse Count

Write

Set-up
Erase

Data = 20H

Write

Erase

Data = 20H

Standby

Write

Duration of Erase
operation (tWHWH2)
Erase
Verify

[3)

Standby
Read

Standby

Write

Read

Data = OOH, resets the
register for read
operations.
Wait for Vpp ramp
toVppd2)

3. Erase Verify Is only performed after
chip erasure. A final read/compare
may be performed (optional) after the
register is written with the Read command.
4. Refer to principles of operation.

Figure 5. Erase Algorithm for byte-wide mode

6-156

Compare output to FFH
increment pulse count

Standby

Notes:
1. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operetlon of
the device.
2. See DC Charecteristlcs for the value of VPPH and VPPL.

Addr = BfHe to verify;
Data = A H; Stops
Erase Operation [4)
tWHGL
Read byte to verify
erasure

iMC001~LKA

Start Write Operation

COMMENTS

ApplyVpPH

Wait for Vpp ramp to VPPH

AUteS = address to write
W_DAT = data word to write
Initialize:
V_DAT = W_DAT
W_COM = 4040H
V_COM = COCOH

Initialize Data Word Variables:
V OAT valid data
W- COM Write Command
V COM Write Verify Command
P[SCNT_HI HI Byte Pulse
Counter
PLSCNT_LO LO Byte Pulse
Counter
FLAG Write Error Flag

=
=
= =
=
=

PLSCNT_HI = 0
PLSCNT_LO = 0
FLAG =0

Write xxJW_COM

Write Set-up Command

xx = Address don't care

Write ADRSIW_DAT

Write

Time Out 10uS

High/Low Byte
Compare & Mask
Subroutine

Write ADRSN_COM

See Write Verify and Mask
Subroutine.
Write Verify Command

Time Out 6uS

F_DAT = flash memory data
Compare flash memory data
to valid data (word compare).
If not equal, check for Write
Error flag. If Flag not set,
compare High and Low Bytes
in the Subroutine.
Check buffer of 110 port for more
data fo write.

Write READ_COM
ApplyVpPL

(

::t::

Write Complete

ApplyVpPL

)

Reset device for read operation.
Turn off Vpp•

Write Error

Figure 6. Write Algorithm fqr word-wide mode

6-157

iMC001FLKA

START SUBROUTINE

COMMENTS: '

LO-BYTE = (F_OAT AND OOFFH)

To look at the LO Byte, Mask* the
HI Byte with 00.

If the LO Byte verifies, mask the
LO Byte commands with the
reset command (FFH)

If the LO Byte does not verify,
then increment its pulse counter
and check for max count.
FLAG 1 denotes a LO Byte error.

N
Repeat the sequence for
the HI Byte.
'

INCREMENT PLSCNT_HI

FLAG

= FLAG + 2
FLAG;' 2 denotes a HI Byte error.
FLAG = 3 denotes both a HI and
LO Byte errors. Flag = 0 denotes
no max count errors; continue
with algorithm.
'

SUBROUTINE RETURN
*Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming data (F_OAT),
the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 7. Write Verify and Mask Subroutine for word-wide mode

6-158

iMC001FLKA

COMMENTS:

START ERASURE

Wait for Vpp to stabilize.
WRITE ALL DEVICES
TOOOH

Use Write operation algorithm
in xS or x16 configuration
!!'!!t!:!H:!~ \f!!!'!!!h!~~:

PLSCNT_HI = 0
PLSCNT_LO = 0
ADRS =0

=
=

PLSCNT_HI HI Byte Pulse Counter
PLSCNT_LO LO Byte Pulse Counter
FLAG Erasure error flag
ADRS Address
E COM Erase Command
V:::COM Verify Command

FLAG = 0
E_COM = 2020H
V_COM = AOAOH

=
=
=
=

Erase Set-up Command
Start Erasing
Duration of Erase Operation.
Erase Verify Command stops
erasure.
See Block Erase Verify &
Mask Subroutine
When both devices at ADRS are
erased, F_DATA = FFFFH.
If not equal, increment the
pulse counter and check for
last pulse.
N
Reset commands default to
(E_COM = 2020H)
(V_COM = AOAOH)
before verifying next ADRS.

Reset device for read operation.
Turn off Vpp •
ERASE ERROR
NOTES:
X16 Addressing uses A1-A19 only. Ao=O throughout word-wide operation.

Figure S. Erase Algorithm for word-wide mode

6-159

iMC001FLKA

Start Subroutine

COMMENTS:
This subroutine reads the data word
(F DATA). It then masks the HI or
LO" Byte of the Erase and Verify
commands from executing during the
next operation.

TimeOut 6 uS

Read ADRS/F_DATA

If both HI and LO Bytes verify, then
return.

Mask· the HI Byte with OOH.

If the LO Byte verifies erasure, then
mask· the next erase and verify
commands with FFH (RESET).

INCREMENT PLSCNT_LO
If the LO BY.le does not verify, then
increment Its pulse counter and
check for max count. FLAG = 1
denotes a LO Byte error.

Repeat the sequence for the HI Byte.

Flag 2 denotes a HI Byte error. Flag
3 denotes both a HI and LO Byte
errors. FLAG 0 denotes no max
count errors; continue with algorithm.

Subroutine Return
"Masking can easily and efficiently be done in assembly languages. Simply load word registers with t~e Incoming data (F_DAn,
the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 9. Erase Verify and Mask Subroutine for word-wide mode.

6-160

iMC001FLKA

SYSTEM DESIGN CONSIDERATIONS

Power Up/Down Protection

Three-Line Control

The PCMCIA/JEIDA socket is specified, via unique
Pin lengths, to properly sequence the power supplies to the flash memory card. This assures that
hot insertion and removal will not result in card damage or data loss.

Three-line control provides for:
a. the lowest possible power dissipation and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these three control inputs, an
address-decoder output should drive CE,.2.!....!Vhile
the system's Read signal controls the card OE signal, and other parallel zones. This, coupled with the
internal zone decoder, assures that only enabled
memory zones have active outputs, while deselected zones maintain the low power standby
condition.
Power-Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current issues standby, active and transient currelJ!..peaks, produced by falling and rising edges of CE'J2' The capacitive and inductive loads on the card and internal
flash memory zones determine the magnitudes of
these peaks.
Three-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. The
iMC001 FLKA features on-card ceramic decoupling
capacitors connected between Vee and Vss , and
between VPP,IVPP2 and Vss.
The card connector should also have a 4.7j.1.F electrolytic capacitor between Vee and Vss , as well as
between VPP,IVPP2 and Vss. The bulk capacitors will
overcome voltage slumps caused by printed-circuitboard trace inductance, and will supply charge to
the smaller capacitors as needed.

6-161

Each zone in the iMC001 FLKA is designed to offer
protection against accidental erasure or writing,
caustad by spuriuus systt::iTI-l.::v€;1 siynals that i-'-Iay
exist during power transitions. The card will powerup into the read state.
A system designer must guard against active writes
for Vee volt~s above VLKO when V pp is active.
Since both WE and CE,.2 must be low for a command write, driving either to V 1H will inhibit writes.
With its control register architecture, alteration of
zone contents only occurs after successful completion of the two-step command sequ~nces.
While these precautions are sufficient for most applications, it is recommended that Vee reach its
steady state value before raising V PP 'J2 above
Vee+2.OV. In addition, upon powering-down,
V PP1I2 should be below Vee + 2.0V, before lowering
Vee·

iMC001FLKA

ABSOLUTE MAXIMUM RATINGS·
Operating Temperature
During Read ................ O°C to + 60°C(1)
During EraselWrite ............ O°C to + 60°C
Temperature Under Bias ....... -10°C to + 70°C
Storage Temperature .......... - 30°C to + 70°C
Voltage on Any Pin with
Respect to Ground. . . . . . .. - 2.0V to + 7.0V(2)
VpP1IVpP2 Supply Voltage with .
Respect to Grou"nd
During Erase/Write. . . . .. - 2.0V to + 14.0V(2.3)
Vee Supply Voltage with
Respect to Ground. . . . . . .. - 2.0V to + 7.0V(2)

'Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the card. This is a stress rating only and
functional operation of the card at these or any other
conditions above those indicated in the operationa"/
sections ofthis specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect card reliability.
NOTICE: Specifications contained within the following tables are subject to change.

Notes:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is - 0.5V. During transitions, inputs may undershoot to - 2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for periods less than 20 ns.
3. Maximum DC input voltage on VPP '/VPP2 may overshoot to + 14.0V for periods less than 20 ns.

OPERATING CONDITIONS

Limits
Symbol

Parameter

Unit

Comments

°C

For Read-Only and
Read/Write Operations

Min

Max

Operating Temperature

Vee

Vee Supply Voltage

4.75

5.25

VPPH

Active VpP', VPP2
Supply Voltages

11.40

12.60

VPPL

Vpp During Read Only
Operations

0.00

6.50

6-162

iMC001FLKA

DC CHARACTERISTICS -- Byte Wide Mode
Symbol

Parameter

Notes

Limits
Min

Typical

Max

Unit

Test Condition

III

Input Leakage Current

±1.0

±20

Vee = Vee max
V1N = Vee or Vss

ILO

Output Leakage Current

±1.0

±20

Vee = Vee max
VOUT = Vee or Vss

Ices

Vee Standby Current

0.4

0.8

Vee = Vee max
CE = V 1H

lee1

Vee Active Read Current 1,2

Vee = Vee max CE = V 1L
f = 6MHz, louT = OmA

lee2

Vee Write Current

1,2

1.0

10.0

Writing in progress

lee3

Vee Erase Current

1,2

5.0

Erasure in progress

Icc.

Vee Write Verify Current

1,2

5.0

Vpp = VPPH
Write Verify in progress

Ices

Vee Erase Verify Current 1,2

5.0

Vpp = V PPH
Erase Verify in progress

Ipps

Vpp Leakage Current

±40

Vpp"", Vee

1
0.4

0.8

Vpp

Vee

IpP1

V PP Read Current
or Standby Current

1,3

IpP2

Vpp Write Current

1,3

8.0

IpP3

Vpp Erase Current

1,3

Vpp = V PPH
Erasure in progress

Ipp•

Vpp Write Verify Current

1,3

2.0

5.0

Vpp = V PPH
Write Verify in progress

Ipps

Vpp Erase Verify Current 1,3

2.0

5.0

Vpp = V PPH
Erase Verify in progress

V 1L

Input Low Voltage

-0.5

0.8

V 1H

Input High Voltage

2.4

Vee+ 0.3

VOL

Output Low Voltage

0.40

IOL = 3.2mA
Vee = Vee min

VOH1

Output High Voltage

IOH = -2.0mA
Vee = Vee min

V PPL

Vpp During Read-Only
Operations

0.00

6.5

Note: Erase/Write are
inhibited when Vpp = V PPL

V PPH

Vpp During Read/Write
Operations

11.40

12.60

VLKO

Vee Erase/Write lock
voltage

±.04

3.8

2.5

V pp "'" Vee
Vpp = V PPH
Write in progress

Notes:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25° C.
2. 1 chip active and 7 in standby for byte-wide mode.
3. Assumes 1 Vpp is active.

6-163

iMC001FLKA

DC CHARACTERISTICS Symbol

Word Wide Mode

Parameter

Notes

Limits
Min Typical

Max

Unit

Test Condition

III

Input Leakage Current

±1.0

±20

uA Vee = Vee ~ax
Y'N = Vee or Vss

ILO

Output Leakage Current

±1.0

±20

Vee = Vee max
VOUT = Vee or Vss

Ices

Vee Standby Current

0.4

O.B

rnA

Vee = Vee max
CE '= V ,H

Icc,

Vee Active Read Current

1,2

rnA

Vee = Vee max CE = V'L
f = 6MHz, louT = OrnA

lee2

Vee Write Current

1,2

2.0

rnA Writing in progress

lee3

Vee Erase Current

1,2

rnA Erasure in progress

lee4

Vee Write Verify Current

1,2

rnA

Vpp = VPPH
Write Verify in progress

lee5

Vee Erase Verify Current

1,2

rnA

Vpp = V PPH
Erase Verify in progress

Ipps

Vpp Leakage Current

±BO,

Vpp~

0.7

1.6

\l pp

Vee
Vee

Ipp,

Vpp Read Current
or Standby Current

1,3

IpP2

Vpp Write Current

1,3

rnA

Vpp = V PPH
Write in progress

IpP3

Vpp Erase Current

1,3

rnA

Vpp = V PPH
Erasure in progress

Ipp4

Vpp Write Verify Current

1,3

5.0

rnA

Vpp = V PPH
Write Verify in progress

Ipp5

Vpp Erase'Verify Current

1,3

5.0

rnA

Vpp = V PPH
Erase Verify in progress

V'L
V,H

Input Low Voltage

-0.5

O.B

Input High Voltage

2.4

Vee+ 0.3

VOL

Output Low Voltage

0.40

IOL = 3.2rnA
Vee = 'Vee min

VOH '

Output High Voltage

3.B

IOH = -2.0rnA
Vee = Vee min

VpPL

Vpp During Read-Only
Operations

0.00

6.5

Note; Erase/Write are
inhibited when Vpp = VPPL

VPPH

Vpp During Read/Write
Operations

11.40

12.60

VLKO

Vee Erase/Write lock
voltage

±.OB

2.5

rnA

Vpp ~ Vee

Notes:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V"Vpp = 12.0V, T = 25° C.
2. 2 chips active and 6 in standby for word-wide mode.
3. Assumes 2 Vpps are active.

6-164

iMC001FLKA

CAPACITANCE T

=25° C, f =1.0 MHz
Limits

Symbol

Parameter

C'N1

Address Capacitance

Notes

Min

Max

Unit

Conditions

'pF

V,N

= OV
=

C'N2

Control Capacitance

V,N

COUT

Output Capacitance

VOUT

CliO

I/O Capacitance

= OV

AC TEST CONDiTiONS
Input Rise and Fall Times (10% to 90%) ...................................................... 10 ns
Input Pulse Levels ................................................................... Vol and Voh1 .
Input Timing Reference Level.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vii and Vih
Output Timing Reference Level ......................................................... Vii and Vih
AC CHARACTERISTICS -

Read-Only Operations
Notes

Min

tAVAV/tRC

Read Cycle Time

250

Max

Unit

tELQv/tCE

Chip Enable Access Time

250

tAVQv/tACC

Address Access Time

250

tGLQv/tOE

Output Enable
Access Time

120

tELQx/tL2

Chip Enilble to Output
in Low Z

tEHQZ

Chip Disable to Output
in High Z

tGLQx/tOLz

Output Enable to Output
in Low Z

tGHQZ/tOF

Output Disable to Output
in High Z

tOH

Output Hold from Address,
CE, or OE Change

Symbol

t WHGL

Characteristic

Write Recovery Time
Before Read

Notes:
1. Whichever occurs first..
2. Rise/Fall time,;; 10ns.

6-165

ns
60

ns
ns

5
60

1,2

i
Vee POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENABLED

DATA VALID

ADDRESSES

STANDBY

---

Vcc POWER~OOWN

ADDRESS STABLE

I·

·1

IAVAY (IRe>

'TI

...
c

CE (1:)

...
?
CD

---

CJ)
CJ)

OE (G)

<
CD

...30

I------t

t WHGL

---

oCI

...
CI

-+1-----1

'TI

1/1

...

;lII\

WE(;;;)
t ELOY (ICE)

(IoLZ)

-o·

DATA (00)

tOH

1,»))17

HIGH Z

1""
I AyOY ' (lACe>

\1'~

--VALID OUTPUT.

I -1

::::J
1/1

---I

--t

(Ill)

"C
CD

iil

I GLOY (tOE)

HIGH Z

---

~
~

[Ml

5.0Y

Vee

NOTE: CE refers to CE 1 ,2

'lilJ

~
~

9
.=

iMC001FLKA

AC CHARACTERISTICS -

For Write/Erase Operations
Characteristic

Symbol

Notes

Min

Max

250

Unit

tAVAVItWC

Write Cycle Time

1,2

tAVWL/tAS

Address Set-up Time

1,2

tWLAX/tAH

Address Hold Time

1,2

100

tOVWH/tOS

Data Set-up Time

1,2

tWHox/tOH

Data Hold Time

1,2

tWHGL

Write Recovery Time Before Read

1,2

t GHWL

Read Recovery Time Before Write

1,2

t WLOZ

Output High-Z from Write Enable

1,2

t WHOX

Output Low-Z from Write Enable

1,2

tELWL/tCS

Chip Enable Set-up Time Before Write

1,2

tWHEH/tCH

Chip Enable Hold Time

1,2

tWLWH/twp

Write Pulse Width

1,2

100

tWHWL/twPH

Write Pulse Width High

1,2

tWHWH1

Duration of Write Operation

1,2,3

tWHWH2

Duration of Erase Operation

1,2,3

9.5

t VPEL

Vpp Set-up Time to Chip Enable Low

1,2

100

Notes:
1. Read timing parameters during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read-Only Operations.
2. Rise/Fall time.;; 10ns.
3. The integrated stop timer terminates the write/erase operations, thereby eliminating the need for a maximum
specification.

ERASEIWRITE PERFORMANCE
Parameter

Notes

Min

Typ

Max

Unit

Zone Erase Time

1,3,4

1.0

sec

Zone Write Time

1,2,4

2.0

12.5

sec

106

MTBF

Hrs

Notes:
1. 25° C, 12.0V Vpp.
2. Minimum byte writing time excluding system overhead is 16 usee (10 usee program + 6 usee write recovery), while
maximum is 400 usee/byte (16 usee x 25 loops allowed by algorithm). Max chip write time is specified lower than the
worst case allowed by the write algorithm since most bytes write Significantly faster than the worst case byte.
3. Excludes OOH writing Prior to' Erasure.
4. One zone equals 128K Bytes.
5. MTBF = Mean Time Between Failure, 50% failure point for disk drives.

6-167

SET-UP WRITE
COMMAND

Yee POWER-UP &
STANDBY

WRITE COMMAND
LATCH ADDRESS & DATA

WRITING

WRITE
VERIFY
COMMAND

WRITE
VERIFICATION

STANDBY I
Yee POWER.DOWN

ADDRESSES

~
c

CE (E)

...

....

:-"
l>

DE (G)

~
ca

'l'
....

-...

1/1

C1>

tWHWHl

i
oo

twHGL

....
"11

WE (W)

...0!l::;:

::-;
l>

tWHDX

(\oH)

"...

DATA (DQ)

HIGH Z

1\1

(= 4().4OH fat word-wide mode)

COCOH for _d_.de mode) tELQX

::I

1/1

5.0V

Vee

=
~

t VPEL
12.0V

I---

Vpp
VpPL

NOTE: CE refers to CE 1 .2

~
290245-16

SET-UP ERASE
COMMAND

Vee POWER-UP ole
STANDBY

ERASE COMMAND

ERASE
VERIFY
COMMAND

ERASING

ERASE
VERIFICATION

STANDBY/
Vee POWER-DOWN

..A

ADDRESSES

"11

CE (E)

ID·

...e

...
CD

:I>
0

Of (G)

<
CD

O'l

IWHWL (lwpH)

...03

-......

I·

I WHWH2

i:
oc

- + - - - - I t - - - IWHGL

...c

WE(W)

"11

"
:I>

IwHDX

III
UI
CD

-g

DATA (DQ)

HIGH Z

...
!!l.
o·
:::s

lQl

(= AOAOH for word-wide mode)

s.OV

Vee

ov
IYPEL

12.0V
VPP
V pPL

NOTE: CE refers to CE 1 •2

~
~
(0)

fMl
=
~

"!ill

cQI
~

~J
~1

',<»
C--J]
<=1
C"::l

([21
~~

iMC001FLKA

ALTERNATIVE CE-CONTROLLED WRITES
Symbol

Characteristic

Notes

Min

Max

Unit

250

Address Hold Time

100

t DVEH

Data Set-up Time

tEHDX

Data Hold Time

t EHGL

Write Recovery Time
Before Read

tGHEL

Read Recovery Time
Before Write

tWLEL

Write Enable Set-Up Time
before Chip-Enable

t EHWH

Write Enable Hold Time

tELEH

Write Pulse Width

100

tEHEL

Write Pulse Width High

tpEL

Vpp Set-Up Time
to Chip-Enable Low

100

tAVAV

Write Cycle Time

tAvEL

Address Set-up Time

tELAX

Notes:
1. Chip Enable Controlled Writes: Write operations are driven by the valid combination of Chip Enable and Write Enable.
In systems where Chip Enable defines the write pulse width (with a longer Write Enable timing waveform) all set-up,
hold and inactive Write Enable times should be measured relative to the Chip Enable waveform.

6-170

Vee POWER-UP 50
STANDBY

SET-UP PROGRAM
COMMAND

PROGRAM COMMANO
LATCH ADDRESS 50 DATA

PROGRAMMING

PROGRAM
VERIFY
COMMAND

PROGRAd
VERIFICAT ON

STANDBY/
Vee POWER-DOWN

ADDRESSES

cO'
I:

iil

...

WE (E)

;::;
CD

:;
III

DE (G)

l>
(")

-.J
~

i§

(")

...o

(Vi)

3
1/1

-...

29
©

DATA (DO)

'0
CD

o·
:l

(= "0-40H

word-wide mode)

~
es
7='

(Oo COCOH in word_wide mode)

the
contents of the register default to the read command, making the iMC004FLKA a read-only memory card. In this mode, the memory contents cannot
be altered.

6-17S

iMC004FLKA

The system designer may choose to leave VPP1I2 =
VPPH ' making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever Vee is below the write
lockout voltage, VLKO ' (See the section on Power
Up/Down Protection.) The iMC004FLKA is designed to accommodate either design practice, and
to encourage optimization ofthe processor-memory
card interface.

BUS OPERATIONS

Inteligent Identifier'· Command

The manufacturer- and device-codes can be read
via the Command Register, for instances where the
iMC004FLKA is erased and rewritten in a universal
reader/writer. Following a write of 90H to a zone's
Command Register, a read from address location
OOOOOH on any zone outputs the manufacturer code
(89H). A read from address 0002H outputs the
memory device code (SDH).
Write

Read

The iMC004FLKA has two control functions, both
of which must be logically active, to obtain data at
the outputs. Card Enable (CE) is the power control
and should be used for..b19h and/or low zone(s) selection. Output Enable (OE) is the output control and
should be used to gate data from the output pins,
independent of accessed zone selection. In the
byte-wide configuration, only one CE is required.
The word-wide configuration requires both CEs
active low.
When VPP '/2 is high (VPPH )' the read operations can
be used to access zone data and to access data for
write/erase verification. When VPP1I2 is low (V PPL )'
only read accesses to the zone data are allowed.
Output Disable

Zone erasure and rewriting are accomplished via
the Command Register, when high voltage is applied to VpP'/2' The contents of the register serve
as input to that zone's internal state-machine. The
state-machine outputs dictate the function of the
targeted zone.
The Command Register itself does not occupy an
addressable memory location. The register is a
latch used to store the command, along with address and data information needed to execute the
command.
The Command Register is written by bringing Write
Enable to a logic-low level (Vlcl, while Card Enable(s) is/are low. Addresses are latched on the failing edge of Write Enable, while data is latched on
the rising edge of the Write Enable pulse. Standard
microprocessor write timings are used.

With Output Enable at a logic-high level (V'H)' output
from the card is disabled. Output pins are placed in
a high-impedance state.

Refer to AC Write Characteristics and the Erase/
Write Waveforms for specific timing ·parameters.

Standby

COMMAND DEFINITIONS

With one Card Enable at a logic-high level, the
standby operation disables one-half of the x16 output's read/write buffer. Further, only the zone correspondi~o the selected address within the upper
or lower CE,.2 bank is active at a time. (NOTE: Ao
must be low to select the low half of the x16 word
when CE 2 = 1 and CE, = 0.) All other zones are
deselected, substantially reducing card power consumption. For deselected banks, the outputs are
placed in a high-impedance state, independent of
the Output Enable signal. If the iMC004FLKA is deselected during erasure, writing, or write/erase verification, the accessed zone draws active current
until the operation is terminated.

When low voltage is applied to the Vpp pin(s), the
contents of the zone Command Register(s) default
to OOH, enabling read-only operations.

Placing high voltage on the Vpp pin(s) enable(s)
read/write operations. Zone operations are selected by writing specific data patterns into the
Command Register. Tables 3 and 4 define these
iMC004FLKA register commands for both bytewide and word-wide configurations.

6-179

iMC004FLKA

Table 2 .. Bus Operations
Pins

[1,7]
VPP•

Operation

Notes

Read (x8)

VPPL

[1,7]
Vpp,

CEo

CE,

VPPL

V'L

V,H

V'L

V,H

HighZ

Data Out-Even

V'L

V,H

HighZ

Data Out-Odd

V'L

V,H

Data Out

High Z

Read (x8)

VPPL

V,H

V'L

Read (x8)

VPPL

V'L

V,H

Read (x16)

z
6
«
w

D.-D,s

0 0-07

VPPL

V'L

V,H

Data Out

Output Disable

VPPL

V,H

HighZ

High Z

Standby

VPPL

V,H

HighZ

High Z

V'L

V,H

HighZ

Data Out-Even

HighZ

Data Out-Odd

II:

Read (x8)

3,8

VpPx

VPPH

VII.

V,H

Read (x8)

3,9

VPPH

Vppx

V,H

V'L

V,H

Read (x8)

VPPH

Vppx

V'L

V,H

V'L

V,H

Data Out

HighZ

I-

Read (x16)

3,11.

VPPH

V'L

V,H

DataOuf

Data Out

Write (x8)

5,8

Vppx

VPPH

V'L

V,H

V'L

V,H

V'L

High Z

Data In-Even

«
w

Write (xB)

VPPH

Vppx

V,H

V'L

V,H

V'L

High Z

Data In-Odd

Write (x8)

VPPH

Vppx

V'L

V,H

V'L

Data In

High Z

Write (x16)

VPPH

V'L

V,H

V'L

Data In

Standby

VpPH

VPPH

V,H

High Z

VPPH

V,H

V'L

High Z

HighZ

II:

Output Disable

Notes:
1. Refer to DC Characteristics. When VPP1I2 = VPPL memory contents can be read but not writlenor erased.
2. Manufacturer and device codes may be accessed via a command register write sequence.
Refer to Table 3. All other addresses low.'
3. Read operations with VPP1I2 = Vpph may access array data or the Inteligent Identifier codes.
4. With VPP1I2 at high voltage, the standby current equals Icc + Ipp (standby).
5. Refer to Table 3 for valid Data-In during a write operation.
6. X can be V'L or V,H.
7. Vppx = VPPH or VPPL '
8. This x8 operation reads or writes the low byte of the x16 word on'DO!)'7, i.e., AD low reads "even" byte in x8 mode.
9. This x8 operation reads or writes the high byte of the x16 word on DOo.7 (transposed from DO•. ,s), i.e., AD high reads
"odd" byte in x8 mode.
10. This x8 operation reads or writes the high byte of the x16 on DO•.,s. AD is "don't care."
11. AD is "don't care," unused in x16 mode. High and low bytes are presented simultaneously.

6-180

iMC004FLKA

Table 3. Command Definitions byte-wide mode

Command

Notes

Read Memory

Bus
Cycles
Req'd

Operatlon(1]

First Bus Cycle
Address(2]

Data(3]

Second Bus Cycle

Write

OOH

Operation(1]

Address(2]

Data(3]

Read Inteligent ID Codes

Write

90H

Read

Set·up Erase/Erase

Write

20H

Write

20H

t:A

AOri

Read

t=:A

i::VU

Erase Verify

Wrtte

Set-up Write/Write

Write

40H

Write

COH

Read

WVD

FFH

Write

FFH

Write Verify

Write

Reset

Write

Table 4. Command Definitions word-wide mode

Notes

Bus
Cycles
Req'd
1

Write

OOOOH

Read Inteligent ID Codes

Write

9090H

Set-up Erase/Erase

Write

2020H

Erase Verify

Write

AOAOH

,Command
Read Memory

Second Bus Cycle

First Bus Cycle
Operation!1]

Address(2]

Data(3]

Address(2]

Data(3]

Write

2020H

Read

EVD

Operation[1]

Read

Set-up Write/Write

Write

4040H

Write

Write Verify

Write

COCOH

Read

WVD

Reset'

Write

FFFFH

Write

FFFFH

Notes:
1, Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
WA = Address of memory location to be written,
ZA = Address of 256 K-Byte zones involved in erase operation.
Addresses are latched on the falling edge of the Write Enable pulse.
3. ID = Data read from location IA during device identification. (Mfr = 89H, Device = BDH).
EVD = Data read from location EA during erase verify.
WD = Data to be written at location WA. Data is latched on the rising edge of Write Enable.
WVD = Data read from location WA during write verify. WA is latched on the Write command.
4. Following the Read Inteligent ID command, two read operations access manufacturer and device codes.
5. Figure 5 illustrates the Erase Algorithm.
6. Figure 6 illustrates the Write Algorithm.
7. The second bus cycle must be followed by the desired command register write.

6-181

iMC004FLKA

Read Command
While VPP1I2 is high, for erasure and writing, zone
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH (OOOOH for the word-wide configuration) into
the zone Command Register(s). Microprocessor
read cycles retrieve zone data. The accessed zone
remains enabled for reads until the Command Register(s) contents are altered.
The default contents of each zone's register(s) upon
VPP1I2 power-up is OOH (OOOOOH for word-wide). This
default value ensures that no spurious alteration of
memory card contents occurs during the V PP1I2
power transition. Where the VpP1I2 supply is left at
V PPH ' the memory card powers-up and remains
enabled for reads until the command Register contents of targeted zones are changed. Refer to the
AC Read Characteristics and Waveforms for specific timing parameters.
inteligent Identifier Command
Each zone of the iMC004FLKA contains an inteligent Identifier to identify memory card device characteristics. The operation is initiated by writing 90H
(9090H for word-wide) into the Command Register(s). Following 'the command write, a read cycle
from address OOOOOH retrieves the manufacturer
code 8SH (8989H for word-wide). A read cycle from
address 0002H returns the device code BOH
(BDBOH for word-wide). To terminate the. operation,
it is necessary to write another valid command into
the register( s).
Set-up Erase/Erase Commands
Set-up Erase is a command-only operation that·
stages the targeted zone(s) for electrical eras~re ?f
all bytes in the zone. The set-up erase operatIOn IS
performed by writing 20H to the Command Register
(2020H for word-wide).

6-182

To commence zone-erasure, the erase command
(20H or 2020H) must again be written.to the register(s). The erase operation begins with the rising
edge of the Write-Enable pulse and terminates ~ith
the rising edge of the next Write-Enable pulse (I.e.,
Erase-Verify Command).
This two-step sequence of set-up followed by execution ensures that zone memory contents are not
accidentally erased. Also, zone-erasure can only
occur when high voltage is applied to the VPP1/2 pins.
In the absence of this high voltage, zone memory
contents are protected against erasure. Refer to AC
Erase Characteristics and Waveforms for specific
timing parameters.
Erase-Verify Command
The erase command erases all of the bytes of the
zone in parallel. After each erase operation, all
bytes in the zone must be individually verified. In
byte-mode operations, zones are segregated by Ao
in odd and even banks; erase and erase verify
operations must be done in complete passes of
even-bytes-only then odd-bytes-only. See the Erase
Algorithm for byte-Wide mode. The erase verify
operation is initiated by writing AOH (AOAOH for
word-wide) into the Command Register(s). The address for the byte(s) to be verified must be supplied
as it is latched on the falling edge of the Write Enable
pulse. The register write terminates the erase operation with the rising edge of its Write Enable pulse.
The enabled zone applies an internally-generated
margin voltage to the addressed byte. Reading FFH
from the addressed byte indicates that all bits in the
byte are erased. Similarly, reading FFFFH from the
addressed word indicates that all bits in the word
are erased.
The erase-verify command must be written to the
Command Register prior to each byte (word) verification to latch its address. The process continues
for each byte (word) in the zone(s) until a byte (word)
does not return FFH (FFFFH) data, or the last
address is accessed.

iMC004FLKA

In the case where the data read is not FFH (FFFFH),
anoJher erase operation is performed. (Refer to Setup Erase/Erase.) Verification then resumes from
the address of the last-verified byte (word). Once all
bytes (words) in the zone(s) have been verified, the
erase step is complete. The accessed zone can now
be written. At this point, the verify operation is terminated by writing a valid command (e.g., Write Setup) to the Command Register. The Erase algorithms
fnr
~nn
ulnrrLu,irl.c.
I""nnfinllr!:lltinnt:.
illllC:::_
....... h"to_\Alirio
••• _ _ _
............
_ ..............
_ ....
•• _ •• _ •..
__
Ooi~"'"

~_._

trate how commands and bus operations are
combined to perform electrical erasure of the
iMC001 FLKA. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.
Set-up Write/Write Commands
Set-up write is a command-only operation that
stages the targeted zone for byte writing. Writing
40H (4040H) into the Command Register(s) performs the set-up operation.
Once the write set-up operation is performed, the
next Write Enable pulse causes a transition to an
active write operation. Addresses are internally
latched on the falling edge of the Write Enable
pulse. Data is internally latched on the rising edge
of the Write Enable pulse. The rising edge of Write
Enable also begins the write operation. The write
operation terminates with the next rising edge of
Write Enable, which is used to write the verify command. Refer to AC Write Characteristics and Waveforms for specific timing parameters.
Write Verify Command
The iMC004FLKA is written on a byte-by-byte or
word-by-word basis. Byte or word writing may occur
sequentially or at random. Following each write
operation, the byte or word just written must be
verified.
.
The write-verify operation is initiated by writing COH
(COCO) into the Command Register(s). The register
write(s) terminate(s) the write operation with the rising edge of its Write Enable pulse. The write-verify
operation stages the accessed zone(s) for verification of the byte or word last written. No new address information is latched. The zone(s) apply(ies)
an internally-generated margin voltage to the byte

or word. A microprocessor read cycle outputs the
data. A successful comparison between the written
byte or word and true data means that the byte or
word is successfully written. The write operation
then proceeds to the next desired byte or word location. The Write algorithms for byte-wide and
word-wide configurations illustrate how commands
are combined with bus operations to perform byte
and word writes. Refer to AC Write Characteristics
:!r.d \/\f=,-,ef0rm~ for specific tirni!1!] r~r~m~t~rB
Reset Command
A reset command is provided as a means to safely
abort the erase- or write-command sequences. Following either set-up command (erase or write) with
two consecutive writes of FFH (FFFFH for wordwide) will safely abort the operation. Zone memory
contents will not be altered. A valid command must
then be written to place the accessed zone in the
desired state.

EXTENDED ERASE/WRITE CYCLING
Intel has designed extended cycling capability into
its ETOX II flash memory technology enabling a
flash memory card with a MTBF that is approximately 20 times more reliable than rotating disk
technology. Resulting improvements in cycling reliability come without increasing memory cell size or
complexity. First, an advanced tunnel oxide increases the charge carrying ability ten-fold. Sec-.
ond, the oxide area per cell subjected to the,
tunneling electric field minimizes the probability of
oxide defects in the region. The lower electric field
greatly reduces oxide stress and the probability of
failure.

WRITE ALGORITHMS
The write algorithm(s) use write operations of 10f,Ls
duration. Each operation is followed by a byte or
word verification to determine when the addressed
byte or word has been successfully written. The algorithm(s) allows for up to 25 write operations per
byte or word, although most bytes and words verify
on the first or second operation. The entire sequence of writing and byte/word verification is performed with V pp at high voltage.

6-183

iMC004FLKA

ERASE ALGORITHM
The Erase algorithm(s) yield(s) fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the write
algorithm, to simultaneously remove charge from all
bits in the accessed zone(s).
Erasure begins with a read of memory zone contents. Reading FFH (FFFFH) data from the accessed zone(s) can be immediately followed by
writing to the desired zone(s).
For zones being erased and rewritten, uniform and
reliable erasure is ensured by first writing all bits in
the accessed zone to their charged state (data =
OOH byte-wide, OOOOOH word-wide). This is accomplished, using the write algorithm, in approximately
four seconds per zone.

Erase execution then continues with an initial erase
operation. Erase verification (data = FFH blltewide, FFFFH word-wide) begins at address OOOOOH
and continues through the zone to the last address,
or until data other than FFH (FFFFH) is encountered. (Note: byte-wide erase operation requires
separate even- and odd-address passes to handle
the individual 256 K-Byte zones.) With each erase
operation, an increasing number of bytes or words
verify to the erased state. Erase efficiency may be
improved by storing the address of the last byte or
word verified in a register(s). Following the next
erase operation, verification starts at that stored address location. Follow this procedure until all bytes
in the zone are erased. Then, re-start the procedure
for the next zone or word-wide zone pair. Erasure
typically occurs in two seconds per zone.

INITIALIZE SIZE
AND NUMBER OF ZONES
ZONEL=O
ZONE H = 1

Figure 3. Full Card Erase Flow

6-184

iMC004FLKA

BUS
OPERATION COMMAND

COMMENTS

Wait for Vpp ramp
to VPPH (= 12.0V) [2]

Standby

Initialize pulse-count

= 4DH

Write

Set-up
Write

Data

Write

Valid address/data
Duration Of Write
operation (tWHWH1)

Standby
Write
Verify

Write

[3]

Data = COH; Stops [4]
Write Operation

Standby

tWHGL

Read

Read byte to verify
Write Operation

Standby

Compare data output
to data expected '

Write

Read

Standby

Data = DOH, resets the
register for read
operations.
Wait for Vpp ramp
to VPPL [2]

Notes:
1. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of
the device.

3. Write VerlfY,ls only performed after
a byte write operation. A final read/compare
may be performed (optional) after the
register is written with the Read command.

2. See DC Characteristics for the value of VPPH and VPPL.
4. Refer to principles of operation.

Figure 4. Write Algorithm for byte-wide mode

6-185

iMC004FLKA

BUS
OPERATION COMMANDS
DATA

Wait for Vpp ramp
to VPPH (= 12.0V) [2]

Standby

=OOH?

COMMENTS

Use Write Operation
Algorithm
Initialize even/odd
Addresses,
Erase Pulse Width,
and Pulse Count

Write,

Set-up
Erase

Data =20H

Write

Erase

Data = 20H

Standby

Write

Duration of Erase
operation (tWHWH2)
Erase
Verify

Addr = Byte to verify;

[3] ,Data = AOH; Stops
Erase Operation [4]
tWHGL
Read byte to verify
erasure

Standby
Read

Standby

Write

Compare output to FFH
increment pulse count

Read

Standby

Data = OOH, resets the
register for read
operations.
Wait for Vpp ramp
toVppL!2]
"

Notes:
1. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of
the device.
2. See DC Characteristics for the value of VPPH and VPPL.

3. Erase Verify is only performed after
chip erasure. A final read/compare
may be performed (optional) after the
register is written with the Read command.
4. Refer to principles of operation.

Figure 5. Erase Algorithm for byte-wide mode

6-186

iMC004FLKA

Start Write Operation

COMMENTS
Wait for Vpp ramp to VPPH

ADRS = address to write
W_DAT = data word to write
Initialize:
V_DAT = W_DAT
W_COM = 4040H
V_COM = COCOH

Initialize Data Word Variables:

=
=

V OAT valid data
W- COM Write Command
VSOM = Write Verify Command
PLSCNT_HI = HI Byte Pulse
Counter
PLSCNT_LO LO Byte Pulse
Counter
FLAG Write Error Flag

PLSCNT_HI = 0
PLSCNT_LO = 0
FLAG =0

Write Set-up Command
xx = Address don't care
Write ADRSIW_DAT

Write
High/Low Byte
Compare & Mask
Subroutine

See Write Verify and Mask
Subroutine.

Write Verify Command

Reset device for read operation.
Turn off Vpp•
y

(

Write Complete

)

Write Error

Figure 6. Write Algorithm for word-wide mode

6-187

iMC004FLKA

START SUBROUTINE

LO-BYTE

COMMENTS:

= (F_OAT AND OOFFH)

To look at the LO Byte, Mask" the
HI Byte with 00.
If the LO Byte verifies, mask the
LO Byte commands with the
reset command (FFH)

INCREMENT PLSCNT_LO
If the LO Byte does not verify,
then increment its pulse counter
and check for max count.
FLAG = 1 denotes a LO Byte error.

N
HI.:..BYTE = (F_OAT AND FFOOH)

Repeat the sequence for
the HI Byte.

INCREMENT PLSCNT_HI

FLAG

= FLAG + 2
FLAG = 2 denotes a HI Byte error.
FLAG = 3 denotes both a HI and
LO Byte errors. Flag = 0 denotes
no max count errors; continue
with algorithm.

SUBROUTINE RETURN
"Masking can easily and efficienlly be done in assembly languages. Simply load word registers with the incoming data (F_DAn,
the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 7. Write Verify and Mask Subroutine for word-wide mode

6.. 188

iMC004FLKA

COMMENTS:

START ERASURE

Wait for Vpp to stabilize.
WRITE ALL DEVICES
TOOOH

Use Write operation algorithm
in x8 or x16 configuration
iniiii:liize iiarii:luie:;;

INITIALIZE:

PLSCNT_HI = 0
PLSCNT_LO = 0
ADRS =0

PLSCNT_HI = HI Byte Pulse Counter
PLSCNT_LO LO Byte Pulse Counter
FLAG Erasure error flag
ADRS = Address
E COM Erase Command
V:::COM Verify Command

FLAG =0
E_COM = 2020H
V_COM = AOAOH

=
=
=

Erase Set-up Command
Start Erasing
Duration of Erase Operation.

Erase Verify Command stops
erasure.
See Block Erase Verify &
Mask Subroutine
When both devices at ADRS are
erased, F_DATA = FFFFH.
If not equal, increment the
pulse counter and check for
last pulse.
.
N

Reset commands default to
(E_COM = 2020H)
(V_COM = AOAOH)
before verifying next ADRS.

Reset device for read operation.
Turn off Vpp•
ERASE ERROR
NOTES:
X16 Addressing uses A,-A21 only. Ao=O throughout word-wide operation.

Figure 8. Erase Algorithm for word-wide mode

6-189

iMC004FLKA

Start Subroutine

COMMENTS:
This subroutine reads the data word
(F_DATA). It then masks the HI or
LO Byte of the Erase and Verify
commands from executing during the
next operation.

Time Out 6 uS

Read ADRS/F_DATA

If both HI and LO Bytes verify, then
return.

Mask' the HI Byte with DOH.

If the LO Byte verifies erasure, then
mask" the next erase and verify
commands with FFH (RESET).

INCREMENT PLSCNT_LO
If the LO BY.le does not verify, then
increment Its pulse counter and
check for max count. FLAG 1
denotes a LO Byte error.

Repeat the sequence for the HI Byte.

E_COM = (E_COM or FFOOH)
V_COM (V_COM or FFOOH)

Flag

=2 denotes a HI Byte error.

Flag

= 3 denotes both a HI and LO Byte

errors. FLAG = 0 denotes no max
count errors; continue with algorithm.

Subroutine Return
'Masking can easily and efficiently be done in assembly languages. Simply load word registers with the Incoming data (F_DAn,
the program commands and the verify commands. Then manipulate the HI or LO register contents.

Figure 9. Erase Verify and Mask Subroutine for word-wide mode.

6-190

iMC004FLKA

SYSTEM DESIGN CONSIDERATIONS
Three-Line Control

The card connector should also have a 4.7f..1.F electrolytic capacitor between Vee and Vss , as well as
between Vpp,IVpP2 and Vss. The bulk capacitors will
overcome voltage slumps caused by printed-circuitboard trace inductance, and will supply charge to
the smaller capacitors as needed.
Power Up/Down Protection

The PCMCIA/JEIDA socket is specified, via unique
Pi" it:lllyiilt;, iu pruperiy sequence the power supplies to the flash memory card. This assures that
hot insertion and removal will not result in card damage or data loss.
Each zone in the iMC004FLKA is designed to offer
protection against accidental erasure or writing,
caused by spurious system-level signals that may
exist during power transitions. The card will powerup into the read state.

Power-Supply Decoupling

Flash memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current issues standby, active and transient curre~eaks, produced by falling and rising edges of CE 1I2 . The capacitive and inductive loads on the card and internal
flash memory zones determine the magnitudes of
these peaks.
Three-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. The
iMC004FLKA features on-card ceramic decoupling
capacitors connected between Vee and Vss , and
between Vpp,IVpP2 and Vss.

A system designer must guard against active writes
for Vee volt~s above VLKO when Vpp is active.
Since both WE and CE'.2 must be low for a command write, driving either to V'H will inhibit writes.
With its control register architecture, alteration of
zone contents only occurs after successful completion of the two-step command sequences.
While these precautions are sufficient for most applications, it is recommended that Vee reach its
steady state value before raising VPP1I2 above
Vee + 2.0V. In addition, upon powering-down,
VPP1I2 should be below Vee+2.OV, before lowering
Vee·

6-191

iMC004FLKA

ABSOLUTE MAXIMUM RATINGS·
Operating Temperature
"
During Read ................ O°C to + 60°C(1)
During Erase/Write ............ O°C to + 60°C
Temperature Under Bias ....... - 10°C to + 70°C
Storage Temperature .......... - 30°C to + 70°C
Voltage on Any Pin with
Respect to Ground. . . . . . .. - 2.0V to + 7.0V(2)
VPP,IVPP2 Supply Voltage with
Respect to Ground
During Erase/Write .. ~ . .. - 2.0V to + 14.0V(2.3)
Vcc Supply Voltage with
Respect to Ground. . . . . . .. - 2.0V to + 7.0V(2)

'Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the card. This is a stress rating only and
functional operation of the card at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect card reliability.
NOTICE: Specifications contained within the following tables are subject to change.

Notes:
1. Operating temperature is for'commercial product defined by this specification.
2. Minimum DC input voltage is - 0.5V. During transitions, inputs may undershoot to - 2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V, whieh may overshoot to Vee + 2.0V for periods less than 20 ns.
3. Maximum DC input voltage on Vpp,IVpP2 may overshoot to + 14.0V for periods less than 20 ns.

OPERATING CONDITIONS

Limits
Symbol

Parameter

Unit

Comments

°C

For Read-Only and
Read/Write Operations

Min

Max

Operating Temperature

Vcc

V cc Supply Voltage

4.75

5.25

VPPH

Active Vpp " VPP2
Supply Voltages

11.40

12.60

VPPL

V pp During Read Only
Operations

0.00

6.50

6-192

iMC004FLKA

DC CHARACTERISTICS Symbol

Byte Wide Mode

Parameter

Notes

Limits
Min

Typical

Max

Unit

Test Condition

III

Input Leakage Current

± 1.0

±20

Vee = Vee max
V ,N = Vee or Vss

ILO

Output Leakage Current

± 1.0

±20

Vee = Vee max
VOUT = Vee or Vss

Ices

Vee Standby Current

O.B

1.6

leel

Vee Active Read Current 1,2

Vee

___ . .

Vee IllelA

= V,H
mA Vee = Vee max CE = V'L
f = 6MHz, louT = OmA
CE

lee2

Vee Write Current

1,2

1.0

12.0

Writing in progress

lee3

Vee Erase Current

1,2

6.0

Erasure in progress

lee4

Vee Write Verify Current

1,2

6.0

Vpp = VpPH
Write Verify in progress

Ices

Vee Erase Verify Current 1,2

6.0

Vpp = V PPH
Erase Verify in progress

Ipps

Vpp Leakage Current

±BO

IpP1

Vpp Read Current
or Standby Current

1,3

IpP2

Vpp Write Current

1,3

B.O

Vpp = VpPH
Write in progress

IpP3

Vpp Erase Current

1,3

Vpp = VpPH
Erasure in progress

IpP4

Vpp Write Verify Current

1,3

3.0

6.0

Vpp = VPPH
Write Verify in progress

Ipps

Vpp Erase Verify Current 1,3

3.0

6.0

Vpp = VpPH
Erase Verify in progress

V'L
V ,H

Input Low Voltage

-0.5

O.B

Input High Voltage

2.4

Vee+ 0.3

VOL

Output Low Voltage

0.40

IOL = 3.2mA
Vee = Vee min

VOH1

Output High Voltage

3.B

IOH = -2.0mA
Vee = Vee min

VpPL

Vpp During Read·Only
Operations

0.00

6.5

Note: Erase/Write are
inhibited when Vpp = V PPL

VPPH

Vpp During Read/Write
Operations

11.40

12.60

V LKO

Vee Erase/Write lock
voltage

1
0.7

1.6

±.OB

2.5

Vpp~

Vpp

Vee

> Vee

Vpp ~ Vee

Notes:
1. All currents are in RMS unless otherwise noted. Typical values at Vee
2. 1 ehip active and 15 in standby for byte·wide mode.
3. Assumes 1 Vpp is active.

6·193

= 5.0V, Vpp =

12.0V, T

= 25' C.

iMC004FLKA

DC CHARACTERISTICS Symbol

Word Wide Mode

Parameter

Notes

Limits
Min Typical

Max

Unit

Test Condition

III

Input Leakage Current

±1.0

±20

Vee = Vee max
VIN = Vee or Vss

ILO

OLitput Leakage Current

±1.0

±20

Vee = Vee max
VOUT = Vee or Vss

Ices

Vee Standby Current

0.8

1.6

Vee = Vee max
CE = V IH

Icc,

Vee Active Read Current

1,2

100

Vee = Vee max CE = V IL
f = 6MHz, lOUT = OmA

lee2

Vee Write Current

1,2

2.0

mA Writing in progress

lee3

Vee Erase Current

1,2

mA Erasure in progress

lee4

Vee Write Verify Current

1,2

Vpp = VPPH
Write Verify in progress

lee5

Vee Erase Verify Current

1,2

Vpp = V PPH
Erase Verify in progress

Ipps

Vpp Leakage Current

±160

Ipp,

Vpp Read Current
or Standby Current

1,3

IpP2

Vpp Write Current

1,3

Vpp = V PPH
Write in progress

IpP3

V PP Erase Current

1,3

Vpp = V PPH
Erasure in progress

Ipp4

Vpp Write Verify Current

1,3

5.0

Vpp = V PPH
Write Verify in progress

Ipp5

Vpp Erase Verify Current

1,3

5.0

Vpp = VPPH
Erase Verify in progress

1.5

3.0
±.16

Vpp~

Vee

Vpp > Vee
Vpp ~ Vee

V IL

Input Low Voltage

-0.5

0.8

V IH

Input High Voltage

2.4

Vee+ 0.3

VOL

Output Low Voltage

0.40

IOL = 3.2mA
Vee = Vee min

VOH ,

Output High Voltage

3.8

IOH = -2.0mA
Vee = Vee min

VPPL

Vpp During Read-Only
Operations

0.00

6.5

Note: Erase/Write are
inhibited when Vpp = VPPL

VPPH

Vpp During Read/Write
Operations

11.40

12.60

V LKO

Vee Erase/Write lock
voltage

2.5

Notes:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25° C.
2. 2 chips active and 14 in standby for word-wide mode.
3. Assumes 2 Vpps are active.

6-194

iMC004FLKA

CAPACITANCE T=2So C, 1=1.0 MHz
Limits
Symbol

. Parameter

Notes

Min

Max

Unit

Conditions

C,N •

Address Capacitance

V,N

= OV

C'N2

Control Capacitance

V,N

= OV

COUT

Output Capacitance
I'" _____ :& ____

. VOUT

11\.1

\"IQtJa.\.oIlQllu~

VI/Q

fI'

= OV
n ..

AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...................................................... 10 ns
Input Pulse Levels ................................................................... Vol and Voh1
Input Timing Reference Level ........................................................... Vii and Vih
Output Timing Reference Level ......................................................... Vii and Vih
AC CHARACTERISTICS Symbol

Read-Only Operations
Notes

Min

tAVAV/tRC

Read Cycle Time

250

tELOV/tCE

Chip Enable Access Time ,

250

tAvOV/tACC

Address Access Time

250

tGLOV/tOE

Output Enable
Access Time

120

tELOX/tLZ

Chip Enable to Output
in Low Z

t EHOZ

Chip Disable to Output
in High Z

tGLOX/tOLZ

Output Enable to Output
in Low Z

tGHOZ/tOF

Output Disable to Output
in High Z

tOH

Output Hold from Address,
CE, or OE Change

t WHGL

Characteristic

Write Recovery Time
Before Read

Notes:
1. Whichever occurs first.
2. Rise/Fall time,;;; 10ns.

6-195

Max

Unit
ns

ns
60

ns
ns

1,2

l
Vee POWER-UP

DEVICE AND
ADDRESS SELECTION

STANDBY

OUTPUTS ENABLED

STANDBY

DATA VALID

Vcc POWER-DOWN

X
ADDRESS STABLE

ADDRESSES

t AVAV (tRC)

"'II

cD·

...
c

CE (f)

.....
~

'f>
.....

-...

1/1

Of (G)

-...

;II;
)0

:II

\m.QV (tOE)
tELQV (te.)

-----I

(toLZ) --l
(tLZ)

"C
CD
DI

:3
1/1

....
"'II

iiiE(W)

CD
DI

-...o·

1----+ t WH G1. - t l - - - - - i

HIGHZ
DATA (DO)

I. _
'II

(tACe>

tOH

\\~\\\~f_
.

VALID OUTPUT

- --

AVQV

s.OV

fMJ

Vcc

NOTE: CE refers to CE 1 ,2

~
<
~
~

co
CD

DE (6)

'WHWHl

31/1

..0'=E

iVE(iY)

"T1

c;-

'WHDX

('oH)

o
"C

-o·

'GlQY ('OE)

:::!.

(I)

iil

3:
oo

'CHQZ
('OF)

'WHCl

DATA (DO)

>
'OH

~
(9

HIGH Z

("" 4040H for word-wide mode)

:::I
1/1

(= COCOH fcrword_wicle mode)

S.OY

tELQX (tLZ) ~I~-----,

Yee
OY
'VPEl
12.0Y

'ljj]

I--

Ypp
YpPl

~
~
[i1il]
=
~

NOTE: CE refers to CE 1 •2

~
290245-16

SET-UP ERASE
COlO/AND

Vee POWER-UP '"
STANDBY

ERASE COIlIiAND

ERASE
VERIFY
COIlIiAND

ERASING

ERASE
VERIFICATION

STANDBY/
Vee POWER-OOWN
.d

cf
@J

ADDRESSES

CE (E)
"II

cS'
e

...
CD

-"
~
)0
(')

i5E (ii)

~
<

9"
.....

-...

1/1

t WHWL (tWPH)

tWHWH2

+----1---

tWHGL

(')

o
o

WE(W)

"'"IIr-"

...0'

m
iil
1/1
CD

"
)0

tWHDX

DATA (00)

HIGH Z

©J

...

CD
DI

-o·
:::I
1/1

('" AOAOH for word-wiele mode)

S.OV

Vee
. OV
tYPEL

12.0V
Vpp
V pPL

NOTE: CE refers to CE 1 . 2

(f2)

fruu
=
~

'liD
(Q)
~

~
~

(Q)
~

iMC004FLKA

ALTERNATIVE CE-CONTROLLED WRITES

Symbol

Characteristic

Notes

Min·

Max

Unit

250

Address Hold Time

100

tovEH

Data Set-up Time

t EHoX

Data Hold Time

t EHGL

Write Recovery Time
Before Read

tGHEL

Read Recovery Time
Before Write

tWLEL

Write Enable Set-Up Time
before Chip-Enable

tEHWH

Write Enable Hold Time

tELEH

Write Pulse Width

100

tEHEL

Write Pulse Width High

tpEL

Vpp Set-Up Time
to Chip-Enable Low

100

tAVAV

Write Cycle Time

tAVEL

Address Set-up Time

tELAX

Notes:
1. Chip Enable Controlled Writes: Write operations are driven by the valid combination of Chip Enable and Write Enable:
In systems where Chip Enable defines the write pulse width (with a longer Write Enable timing waveform) all set-up,
hold and inactive Write Eriable times should be measured relative to the Chip Enable waveform.

6-200

Vee POWER-UP '"
STANDBY

SET-UP PROGRAM
COMMAND

PROGRAM COt.tt.tAND
LATCH ADDRESS'" DATA

PROGRAMMING

PROGRAM
VERIFY
COMMAND

PROGRAM
VERIFICATIOIl

STANDBY/
Vee POWER-DOWN

ADDRESSES

'TI
tEo

e::

iil
....
~
»
;:;

WE (E)

III

OE (G)

O'l

o
~
~

3:
oo
o

CE (w)

'TI

»""

III

...0'
~

DATA (DO)

©J

o
"C

...

('" 4040H

word,wld .. mode)

(= COCOH

word_wIde mode)

!!l.

o·

:::s

III

S.OV

vee
ov

~
(0)

fMl
~

'li1l

12.0V

VPP
VpPL

NOTE: CE refers to CE 1 ,2

2jJJ
~
~

iMC004FLKA

ORDERING INFORMATION

L
"., I ' ,---'-'--

CUSTOMER IDENTIFIER
ACCESS SPEED (ns)

A= REVISION
'--_ _ _ _ _ _ _ _ _ _ _ _ K = WORD-WIDE
ARCHITECTURE
' - - - - - - - - - - - - - - - FL = FLASH
' - - - - - - - - - - - - - - - - - - 004 = 4 MEGABYTE
DENSITY IN MEGABYTES
' - - - - - - - - - - - - - - - - - - - - - - - MC = MEMORY CARD
'------------------------I=INTEL

ADDITIONAL INFORMATION

Order Number

ER-20, "ETOX II Flash Memory Technology"
RR-60, "ETOX II Flash Memory Reliability Data Summary"
AP-343, "Solutions for High Density Applications using Flash Memory"

6-202

294005
293002
292079

APPLICATION
NOTE

AP-316

October 1990

Using Flash Memory for
In-System Reprogrammable
Nonvolatile Storage

SAUL ZALES
DALE ELBERT
APPLICATIONS ENGINEERING
INTEL CORPORATION

Ordar Number: 292046-003
6-203

USING FLASH MEMORY
FOR IN-SYSTEM
REPROGRAMMABLE
NONVOLATILE STORAGE

CONTENTS

PAGE

1.0 INTRODUCTION ................... 6-206.
1.1 PROM Programmer vs SystemProcessor Controlled
Programming ................. 6-206
1.2 Information Download and
Upload ....................... 6-206
Version Updates (Download) .... 6-206
Data Acquisition (Upload) ....... 6-206
2.0 DEVICE FEATURES AND ISW
APPLICATION
CONSIDERATIONS .............. 6-207
,2.1 Flash Memory Pinouts .......... 6-207
2.2 Command Register
Architecture .............. ,.... 6-209
Simplified Processor Interface .. 6-209
Command Register Reset ...... 6-210
Data Protection on Power
Transitions .................. 6-210
2.3 Vpp Specifications .............. 6-211
3.0 HARDWARE DESIGN FOR ISW ... 6-211
3.1 Vpp Generation ................. 6-211
3.1.1 Regulating Down from
Higher Voltage .......... 6-211
3.1.2 Pumping 5V up to 12V ..... 6-211
3.1.3 Absolute Data Protection Vpp On/Off Control ..... 6-212
3.1.4 Writes and Reads during
Vpp Transitions ......... 6-212
3.1.5 Other Vpp
Considerations .......... 6-212
3.1.6 Vpp Circuitry and Trace
Layout .................. 6-213
3.2 Communications - Getting Data
to and from the Flash
Memory ...................... 6-213
4.0 SOFTWARE DESIGN FOR ISW .... 6-213
4.1 System Integration - Boot Code
Requirements ................ 6-213
4.1.1 ISW Flag Check ........... 6-214
4.2 Communication Protocols and
Flash Memory ISW ........... 6-214
4.3 Data Accumulation Software
Techniques ................... 6-215

6-204

CONTENTS

PAGE

4.4 Reprogramming Routines ....... 6-215
4.4.1 Quick-Erase™ Algorithm .. 6-215

CONTENTS

PAGE

Algorithm Timing Delays .. 6-215

APPENDIX A:
ON BOARD PROGRAMMING DESIGN
CONSIDERATIONS ................. 6-221

High Performance Parallel
Device Erasure ......... 6-216

APPENDIX B:
Vpp GENERATION CiRCUiTS ......... 6-231

4.4.2 Quick-Pulse Programming™
Ai!:luriiiull ............... o-2i7
Algorithm Timing Delays .. 6-217
High Performance Parallel
Device Programming ... 6-217

4.4.3 Pulse Width Timing
Techniques ............. 6-218

A~~!:~D!X

LIST OF DC-DC CONVERTER
COMPANIES ........................ 6-235
APPENDIX D:
DETAILED PARALLEL ERASE FLOW
CHART .............................. 6-236

Hardware Methods ........ 6-218

APPENDIX E:
DETAILED PARALLEL
PROGRAMMING FLOW CHART .... 6-238

5.0 SYSTEM DESIGN EXAMPLE: AN
80C186 DESiGN ................. 6-219

APPENDIX F:
.
DETAILED SYSTEM SCHEMATICS ... 6-240

Software Methods and
Examples .............. 6-218

6.0 SUMMARY ......................... 6-220

6-205

AP-316

NOTE:
See Appendix A for OPB design considerations.

1..0 INTRODUCTION
Intel's ETOXTM II (EPROM tunnel oxide) flash memory technology uses a single-transistor cell to provide
in-system reprogrammable nonvolatile storage. Reprogramming entails electrically erasing all bits in parallel
and then randomly programming any byte in the array.
This new technology offers designers alternatives for
two of industry's needs: I) a cost-effective means of
updating program code; and 2) a solid-state approach
for non-volatile data accumulation or storage.

1.2 Information Download and Upload
ETOX II flash memory technology programs extremely quick, permitting "on-the-fly" programming with
unbuffered 19.2K baud data input. The remote ISW
system handles the serial communication link for the
host interface, as well as the flash memory reprogramming.

This application note:
• introduces you to the concepts of in-system writing;

Version Updates (Download)

• discusses the hardware and software considerations
for reprogramming flash memories in-system;
• offers a checklist for integrating Intel's flash memories into microprocessor- or microcontroller-based
systems; and
• shows an example of an 80CI86 design which incorporates flash memory.

1.1 PROM Programmer vs SystemProcessor Controlled
Programming
While soldered to a printed circuit board, one of two
sources controls flash memory reprogramming: I) a
PROM programmer connected to the board, or 2) the
system's own central processing unit (CPU). These are
called on-board programming (OBP), and in-system
writing (ISW), respectively. With OBP, the PROM
programmer supplies the programming voltage (Vpp)
and the programming intelligence; with ISW, Vpp is
generated locally and the system itself drives the reprogramming process. Both methods offer a variety of benefits. However this application note focuses on ISW.

Flash memories enable code version updates using simple hardware designs. Beyond the basic system, a local
Vpp supply is all that is needed for remote code download.
A central host computer can download program code
to many remote systems. Flash memory offers this capability without the drawbacks of other technologies. It
is solid-state and nonvolatile, thus eliminating mechanical component wear-out (common with disk drives)
and the risk of losing updates (a concern with batterybacked RAM). These aspects of flash memory offer
major advantages in automated factories, remote systems, portable equipment and other applications. Finally, flash memories provide this capability at a much
lower cost than byte-alterable EEPROM and batterybacked SRAM.
Data Acquisition (Upload)

Intel's flash memories allow single-byte programming
for data accumulation applications. A remote data-logger uploads its information to a central host via serial
link. The flash memory device is then in-system erased

,On·Board Programming

In-System Writing

REMOTE SYSTEM

292046-1
FilE SERVER

292046-2

Figure 1. These diagrams illustrate OBP and ISW. In OBP, a PROM programmer updates a system's
flash memory. The ISW diagram shows a host updating remote flash memory via serial link. The
remote system performs the flash reprogramming with its own CPU.

Intel's ETOX flash memory process has patents pending.

6-206

AP-316

for resumption of data acquisition. This is useful in an
advanced electrical power meter, for example. It could
be configured to track and monitor power usage and
report the data to a central computer for billing and
utility management. This reduces the cost of manual
door-to-door meter reading.

2.0 DEVICE FEATURES AND ISW
APPL!CAT!O~ CO~S!DERATIQNS

2.1 Flash Memory Pinouts
The 32-pin DIP memory site is forward-compatible
from the 256K bit to the 2 Mbit flash memory density.
It fits into the 27COlO Mbit EPROM pinout and requires no multiplexed pins. Also, with just a single circuit-board jumper trace, a 28-pin EPROM can be
placed in the lower pins of the 32-pin flash memory
site. (See Figures 2A and 2B, Flash Memory Pinouts.)
For more information on intertechnolol!:Y pin compatibility see Ap Brief AB-25.

This section gives a brief overview of Intel's flash memory features and explains how they facilitate ISW design.
Byte-Wide Flash Memory in 32-Pin DIP

1M (128Kx 8)
512K (64Kx8)
256K (32Kx 8)

C
C

A15 NC

Vpp

+
l~

A16

2M (256Kx8)

A12
A7

C
C

J;
A5 J;
A6

::J Vee
::J WE
::J NC
::J A14

28 PA13
27

6
7

J; 9
A2 J; 10
A3

C
C

32 PIN DIP
0.800" WIDE
TOP VIEW

P OE

23 pAlO
22 P

21 PDQ7

DQOl; 13

20 PDQ6

C
C
C

19 I::JDQ5

DQ2
Vss

A17

25 pAll
24

DQl

P A8
P A9

Al
AO

18 I::JDQ4

tJ DQ3
292046-26

Figure 2A. Flash Memory Pinouts

6-207

AP-316

Byte-Wide Flash Memory in 32-Pln PLCC
2M (256K X 8)
1M (128K X 8)

A15

512K (UK X 8)
256K (32K X 8)

Al2

Vpp

Vee

A14
A13

AB
A9

All

OE
Al0

CE
DQ7

"15

DQt

DQ2

Vss

DQ3

DQ4

DQ5

DQ6

292046-27

Figure 2B. Flash Memory Pinout~

6-20B

AP-316

Table 1. Command Register Instructions
First Bus Cycle

Second Bus Cycle

Bus
Cycles
Req'd

Operaation

Addr(1)

Oata(2)

Operation

Read Memory(3)

Write

OOH

Read inteligent Identifier™

Write

90H

Set-Up Erase/Erase

Write

Erase Verify

Write

t:A

Set-Up Program/Program

Write

Program Verify
Reset(3)

Write

FFH

Command

Addr(1)

Oata(2)

Read

Valid

Read

00/01H

20H

Write

20H

AOi-i

Rectu

EVD

40H

Write

COH

Read

PVO

Write

FFH

NOTES:
.'
1. Addresses are latched on the falling edge of the Write-Enable pulse.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be read during program verify.
2. EVD = Data read from location EA during erase verify. .
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
3. The second bus cycle must be followed by the next desired command register write. given the proper delay times.

at system speeds. Once placed in the read mode no
further action is required on the command register for
subsequent read operations.

2.2 Command Register Architecture
Simplified Processor Interface

Intel's command register architecture simplifies the
processor interface. The command register allows CE\,
WE\, and OE\ to have standard read/write functionality. All commands such as "Set-up Program" or "Prognim Verify" can be written with standard system timings. Raising Vpp to 12V enables the command register
for memory read/write operation, while lowering Vpp
below Vee + 2V restores the device to a read only
memory.
Writing to the register toggles an internal state-m,achine. The state-machine output controls device functionality. Some commands require one write cycle,
while others require two. The command register itself
does not occupy an addressable memory location. The
register simply stores the command, along with address
and data needed to execute the command. With this
architecture, the device expects the first write cycle to
be a command and does not corrupt data at the specified address. Table I contains a list of command register instructions.
The following sections describe the commands in relation to device operation. For more information on the
command register see the appropriate flash memory
data sheets, and Section 4.4 "Reprogramming Routines".
Read Memory Command-OOH

This command allows for normal memory read operations with Vpp turned on. After writing the command
and waiting 6 /-Ls, the CPU can read from the memory

Read inteligent IdentifierTM Command-90H

Most PROM programmers read the device's inteligent
Identifier to select the proper programming algorithm.
On EPROMs, raising A9 to the Vpp level configures
the device for this purpose. Since this is unacceptable
in-system, you can read the flash memory inteligent
Identifier by first writing command 90H. Follow this
by reading address 0000 and 000lH for the manufacturer and device ID. Reset the device with the Read
Memory command after you have read the identifier.
Set-Up Erase/Erase Commands-20H

Write this command (20H) twice in succession to initiate erasure. The first write cycle sets up the device for
erasure. The device starts erasing itself on the second
command's rising edge of Write-Enable. Erasure is
stopped when the CPU issues the Erase Verify command or when the device's integrated stop timer times
out. Integrated stop timers provide a safety net for
complex system environments. In these environments,
s/w timer· accuracy may be difficult to achieve. Some
method of timing is still required, however the timer
need only meet a minimum specification (10 ms). This
is far easier than calibrating a timer to meet both a
minimum and 1llaximum specification (10 ms
±500 /-Ls).
NOTE:
. Prior to erasure, it is necessary to program all bytes to
the same level (data = OOH). See the Quick-Erase™
algorithm for more details.

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device .executes this command on the rising edge of
Write-Enable. The program Verify command stages the
device for verification of the byte last programmed. No
new address information is latched.

Erase Verify Command-AOH
The erase command erases all bytes of the array in parallel. After each erase operation, all bytes must be verified to see if they erased. Write the Erase Verify command (AOH) to stop erasure and setup verification.

The flash memory applies an internally-generated reference voltage to the addressed byte. Wait 6 JLs for the
internal voltages to settle before reading the data at the
address programmed. Reading valid data indicates that
the byte programmed successfully.

Alternatively, you may allow the internal stop timer to
halt erasure. You must still issue the ~rase Verify command to set up verification.
The device latches the address to be verified on the
falling edge of WE \ and the actual command on the
rising edge. Wait 6 JLs before reading the data at the
address specified on the previous write cycle.

Command Register Reset-FFH
Flash memories reset to the read mode during powerup, and remain in this mode as long as Vpp is less than
Vee + 2V. If your system leaves Vpp turned-on during a system reset, then incorporate a command register
device reset into the hardware initialization routines.
This is necessary because the CPU might be controlling
programming or erasure when the system reset hits.

The flash memory applies an internally-generated reference voltage to the addressed byte. Reading OFFH from
the addressed byte in this mode indicates that all bits in
the byte are erased with sufficient margin to Vee and
temperature fluctuations.
If the location is erased, then repeat the Erase Verify
procedure for the next address location. Write the command prior to each byte verification to latch the byte's
address. Continue this process for each byte in the array until a byte does not return OFFH data, or the last
address is accessed.

In the case where the data read is not OFFH, perform
another erase operation. (Refer to Set-up Erase/Erase).
Continue verifying from the address of the last verified
byte. Once you have accessed the last address, erasure
is complete and you can proceed to program the device.
Terminate the erase verify operation by writing another
valid command (e.g., Program Set-up).
Set-up Program/Program Commands-40H
Write this command (40H) twice in succession to initiate programming. The first write cycle sets up the device for programming. The device latches address and
data on the falling and rising edges of the second write
cycle, respectively. It also begins programming on the
rising edge. You stop the programming operation by
issuing the Program Verify command, or by allowing
the integrated program stop timer to time out. This
timer works similiar to the erase stop timer. Again, a
minimum specifkation replaces a tougher minimum!
maximum combination (10 JLs-25 JLs).
Program Verify Command-COH
Flash memory devices program on a byte-by-byte basis.
After each programming operation, the byte just programmed must be verified. Write the Program Verify
command (COH) to stop programming and set-up verification. Should your software allow the integrated stop
timer to halt programming, the software must resume
the algorithm with the Program Verify command. The

Write the reset command (OFFH) twice in succession
to reset the device. The double write is necessary because of the state-machine reprogramming structure.
For example, suppose the system is reset after a Set-up
Program command. The flash memory state machine
expects ,the next write cycle to contain valid address
and data for programming, followed by another write
cycle for. program verification. The first Reset command will be mistaken for program data but will not
corrupt the existing data. This is because the command
(data = OFFH) is a null condition for flash memory
programming. Only data bits programmed to zero pull
charge onto the memory cell and change the data. The
second write cycle actually resets the device to the read
function. Following the second reset cycle, you can
write the next command (Read, Program Set-up, Erase
Set-up, etc.).
If the Vpp supply is turned off upon system reset, the
software reset is not required. The flash memory will
reset itself automatically when Vpp powers down.
Data Protection on Power Transitions
The command register architecture offers another benefit in addition to simplified processor interface-4150H, loop and wait
for host (the link probably went down during
update);
4. When "HOST_INT" is active,vector to
host interaction code.
(See next section.)

292046-9

Figure 6. Example of ISW Integration to the Boot Sequence
An alternaiive to storing these routines in a separate
boot device is storing them in the flash memory con·
taining the program code. Prior to erasure, the CPl,J
would transfer the ISW routines to system RAM and
execute from there. This type of approach is suitable for
battery-operated equipment or systems with back-up
power supplies.
The communication link could be disrupted during reprogramming, leaving the device in an unknown configuration. Therefore, the boot code should reset the flash
memory and check two ISW flags. The following section discusses the flag check concept.

4.1.1 ISW FLAG CHECK
After resetting the flash memories and initializing other
system components, the CPU should check the communications link for a host interrupt. We will call this
the HOST_INT flag. Had the communication link
gone down prior to completion of downloading, then
the host would have to re-establish contact to complete
the task.
Assuming no HOST~NT request has been made, the
boot protocol then checks a data sequence in the flash
memory siguifying a valid application (VALID~P).
You program this sequence into the memory. array after
confirmation of a successful download. If a download is
interrupted midway through erasure or programming,
then the VALID~P flag locations will not contain
the VALID~P code. On the next system bootstrap
the CPU recognizes this and holds up system boot until
valid code is programmed. In Figure 6 an example flag
protocol uses the VALID~P sequence of 4150H
(ASCII codes for "AP").

structions and program code. This protocol can be as
simple as a read-back technique or as complex as an
error-free transmission protocol. (See Figure 7 for possible system-level flash memory instructions.)
A simple read"back technique optimizes download for
boot code memory needs and ease of implementation.
The embedded CPU echoes the flash memory instruction (i.e., Erase or Program) to the host, and waits for a
confirmation prior to execution. After programming
the update, the remote system checks the update by
transmitting it back to the host for confirmation. The
remote system then programs the VALID~P sequence. Note that programming and reading back
64 Kbytes at 19.2K baud takes about 0.57 minutes per
direction:
(65,536 bytes) • (10 bits/byte) • (1 sec/19.2 Kbits) •
(1 min/60 sec) = 0.57 minutes.

Implementing either software- or hardware-based error-free communications protocol improves transmission efficiency. It eliminates the possibility of errant
data being programmed if not buffered and checked,
and optimizes the download process for transmiSsion
time. Additionally, me compression and decompression
routines can improve the transmission rate.
General ISW Instructions Include:
STATUS CHECK
INITIATE REPROGRAMMING
MOVE ISW ROUTINES FROM FLASH MEMORY TO RAM
. (If not resident In separate boot memory)
Data accumulation-specific commands Include:
RETRIEVE DATA
ERASE FLASH MEMORY

Figure 7. Sample System-Level
ISW Instruction Set

4.2 Communication Protocols and
Flash Memory ISW
The remote download communications protocol must
guarantee accurate transmission of flash memory in-

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Status Check

The host should request a status update from the remote system prior to sending a reprogramming instruction. Depending on the response, the host may break
the link and reconnect later, or it may send an erasure
or data-upload command. This type of handshaking is
necessary when system downtime for reprogramming
might not be acceptable. An example of this is an automated factory where robots handle caustic chemicals.

4.3 Data Accumulation Software
Techniques

NOTE:
Contact your nearest sales office for details.
I

If you prefer to implement the algorithms yourself, they
are outlined in the device data sheets. Command register instructions required for the various operations are
included in the data sheet flow charts.
The following sections describe both single-device and
multiple-device parallel reprogramming implementations.
4.4.1 Quick-Erase™ Algorithm

Data can be accumulated in a remote environment with
flash memory and then uploaded to a host computer for
manipulation. You can adapt various standard datalogging techniques for use with flash memory. With
any technique, you determine the next available memory location by reading for erased data (OFFH). This
address would only be located once on system bootstrap and then recalled from RAM and incremented as
needed.
Given a repeating data string of known length and
composition, program start and stop codes at either end
of the string. Do not pick ooH or OFFH data for these
codes because they are used during erasure. The start
and stop codes enable the CPU to differentiate between
available memory for logging and logged data equal to
ooH orOFFH.
For non-regular data input, you can address this same
issue by programming the logged data followed by the
variable identifier. Again, do not pick ooH or OFFH
data for the variable identifiers.
With any technique, the host computer separates and
manipulates the data after the uploading operation.

4.4 Reprogramming Routines
Intel's ETOX flash memories provide a cost-effective
updatable, non-volatile code storage medium. The reliability and operation of the device is based on the use of
specified erasure and programming algorithms.
Intel offers reprogramming software drivers to make it
easy for you to design and implement flash memory
applications. The software is designed around the CPUfamily architectures and requires minimal modification
to define your system parameters. For example, you
supply the memory width (8-bit, 16-bit, or 32-bit), system timing, and a subroutine for control of Vpp.

Flash memories chip-erase all bits in the array in parallel. The erase time depends on the Vpp voltage level
(11.4V -12.6V), temperature, and number of erase/
write cycles on the part. See the device data sheets for
specific parametric influences on reprogramming times.
Note that prior to erasing a flash memory device the
processor must program all locations to OOH. This equalizes the charge on all memory cells insuring uniform and
reliable erasure.
'
Algorithm Timing Delays

The Quick-Erase algorithm has three different time delays:
1) The first is an assumed delay when Vpp first turns
on. The capacitors on the Vpp bus cause an RC
ramp. After switching on Vpp, the delay required is
proportional to· the number of flash memory devices
times 0.1 /LF/device. Vpp must reach its final value
100 ns before the CPU writes to the command register. Systems that hardwire Vpp to the device can
eliminate this delay.
2) The second delay is the "Time Out TEW" function,
where TEW is the erase timing width. The function
occurs after writing the erase command (the second
time) and before writing the erase-verify command.
The erase-verify command or the integrated stop
timer internally stops erasure.
TEW for ETOX II flash memories is a minimum of
10 ms. This delay can be either software or hardware controlled. Either way, the minimum nature of
the timing specification allows for interrupt-driven
timeout routines. Should the interrupt latency be
longer than the minimum delay specification, the
stop timer halts erasure.
3) The third delay in the erase algorithm is a 6 /Ls time
out between writing the erase verify command and
reading for OFFH. During this delay, the internal
voltages of the memory array are changing from the

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erase levels to the verify levels. A read attempt prior
to waiting 6 ,""S will give false data-it will appear
that the chip does not erase. Repeatedly trying to
erase verify the device without waiting 6 ,""S will
cause over-erasure. This delay is short enough that
it is best handled with software timing. Again, note
that the delay specification is a minimum.

tion. If both bytes are erased at the given address, then
the CPU increments the address (by 2) and then writes
the verify command AOAOh again. If neither byte is
erased, then the CPU issues the erase sequence again
without incrementing the address.
Suppose at the given address only the low byte verifies
FFh data? Could the whole chip be erased? The answer
is yes. Rather than check the' rest of the low byte addresses Independently of the high byte, simply use the
reset command to mask the low byte from erasure and
erase verification on the next erase loop. In this example the erase command would be 20FFh and the verify
command would be AOFFh. Once the high byte verifies
at that address, the CPU modifies the command back
to the default 2020h and AOAOh, increments the address by 2, and writes the verify command to the next
address.

High Performance Parallel Device Erasure

In applications containing more than one flash memory, you can erase each device serially or you can reduce
total erase time by implementing a parallel erase algorithm'? You save time by erasing all devices at the same
time. However, since flash memories may erase at different rates, you must verify each device separately.
This can be done in a word-wise fashion with the command register Reset command and a special masking
algorithm.

See Figure 8 for a conceptual view of the parallel erase
flow chart and Appendix D for the detailed version.
These flow charts are for 16-bit systems and can be
expanded for 32-bit designs.

PROGRAM ALL DEVICES TO OOh
RESET ALL VARIABLES,
ISSUE ERASE COMMAND - - - - - - - - ,
TIME OUT
VERIFY COMMAND
[

BOTH DEVICES ERASED

...!!... MASK·

HI-OR LO-BYTE
COMMANDS

N LAST

ADD~ESS
IY

LAST PULSE

DONE

ERROR

• YOU MASK THE DEVICE BY SUBSTITUTING A RESET COMMAND
FOR THE ERASE &: VERIFY COMMANDS. THAT WAY THE
ERASED BYTE IDLES THROUGH THE NEXT ERASE LOOP.

292046-28

Figure 8. High Performance Parallel Erasure (Conceptual Overview)

7. Parallel Erasure and Programming require appropriate choice of Vpp supply to support the increased power consumption.
6-216

Ap·316

• The second delay is the "Time Out 10 f.Ls" function,
which occurs after writing the data and before writing the program-verify command. This write command internally stops programming. The section entitled "Pulse Width Timing Techniques" gives 86family assembly code for generating a 10 f.Ls timer
routine.

4.4.2 Quick·Pulse Programming™ Algorithm

Flash memories program with a modified version of the
Quick-Pulse Programming algorithm used for V.V.
EPROMs. It is an optimized closed-loop flow consisting of 10 f.Ls program pulses followed by byte verification. Most bytes verify after the first pulse, although
some m:ay require more passes through the pulse/verify
loop. As with V.V. EPROMs, this algorithm guarantees a minimum of ten years data retention. See the

High Performance Parallel Device Programming

algorithm.
Algorithm Timing Delays

The Quick-Pulse Programming algorithm has three different time delays:
• The first and third-Vpp set-up and verify set-up
delays-are the same as discussed in the erasure section. In this case the third delay is for the transition
between writing the Program Verify command and
reading for valid data.

Software for word- or doubie-worri programming "all
be written in two different manners. The first method
offers simplicity of design and minimizes software overhead by using a byte programming routine on each device independently. Here you increment the address by
2 or 4 when addressing 1 of 2 or 4 devices, respectively.
The second method offers higher performance by programming the word or double-word data in parallel.
This method manipulates the command register instructions for independent byte control. See Figure 9
for conceptual 2-device parallel programming flow
chart and Appendix E for the detailed version.

Get Ad:.:::;tr:ta Word
.. Reset Command and
Counter Variable.
Program Data +-------~---...,
Word

TimeOrlOfL.

Stop Programming with
Program Verify command

N
Mask HI or Lo Byle
Data Word Programmed?.... lncrement Pulse Counter
V Last Pul.e?
N

c.,-

·:'r' I

Write Read command Write Read command
LowerVpp
LowerVpp'
Program Error
Programming Complete

292046-11

'You mask the device by substituting a Reset command for the Program and Verify commands. That way, the programmed bytes do not get further programmed on subsequent pulses.

Figure 9. Parallel Programming Flow Chart (Conceptual Overview)

6-217

AP-316

NOTE:
Word or double-word programming assumes 2 or 4
8-bjt flash memory devices.

LOOP instruction takes 16 clock cycles to execute per
pass. It decrements the CX register on each pass and
jumps to the specified operand until CX equals zero.

Parallel Programming Algorithm Summary:
• Decreases programming time by programming 2
flash memories (16 bits) in parallel. The algorithm
can be expanded for 32-bit systems.

When writing a delay loop consider all instructions between the start and end of the delay. If a macro is
written that delays 10 ,""S, add the clock cycles for all
instructions in the macro.
-

• Eliminates tracking of high/low byte addresses and
respective number of program pulses by directing
the CPU to write data-words (16-bit) to the command register.

Here is an example of a 10 ,""S delay and the calculation
of the constant required for a 10 MHz 80C186.
WAIT_1O ,""s:
push cx
mov cX,DELAY
loop $
pop cx

• Maintains word write and word read operations.
Should a byte on one device program prior to a byte
on the other, the CPU continues to write word-commands to both devices. However, it deselects the
verified byte with software commands. An alternative is to independently program high and low bytes .
using hardware select capability.

1. Start to End

; 10 clock cycles
;4 clock cycles
;see calculation
; 10 clock cycles

10 ,""s/cycle time
10,""s/loons
100 cycles

4.4.3 Pulse Width Timing Techniques

2. Loop Instruction = 100-24 cycles
= 76 cycles

Software or hardware methods can be used to generate
the timing required for erasure and programming. With
either method you should use an in-circuit emulator
(ICETM) and an oscilloscope to verify proper timing.
Also remove the flash memory device from the system
during initial algorithm testing.

3. Loop Cycles

= 76
= (IS X [DELAY -I]

+ 5)

4. Solving for DELAY = 6

Software Methods and Examples
Software loops are easily constructed using a number of
techniques. Timing loops need to be done in assembly
language so that the number of clock cycles can be
obtained from the instructions.
In order to calculate a delay loop three things are needed1) processor clock speed,
2) clock cycles per instruction, and
3) the duration of the delay loop.
As an example, the 80C186 divides the input clock by
2. With a 20 MHz input clock the processor's internal
clock r.uns at 10 MHz. This translates to a 100 ns cycle
time. Delays can be made.by loading the CX register
with a count and using the LOOP instruction. The

Hardware Methods
Using an Internal TimerMany microcontrollers and some microprocessors have
on-chip timers. At higher input clock speeds these internal timers have a resolution of I ,""S or better. The
timers are loaded with a count and then enabled. The
timer starts counting and when it reaches the terminal
count a bit is set. The CPU executes a polling algorithm
that checks the timer status. Alternatively, a timer-controlled interrupt can be used. After the timer has been
set and the interrupt enabled, the CPU can be programmed to wait in idle mode or it could continue executing until the timed interrupt.

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Ap-316

One thing to take into account when using interrupts is
the time required for the CPU to recognize and interrupt request (interrupt latency). This is important when
figuring the timer value, because the time seen by the
part will be the programmed delay plus the minmum
interrupt latency time.
.

Boot

.............
........."", 1n
•• " ...
nl........................................
.. ~ ....... .-1 10 ........ c:o
LWV ":• .1. .......
.LV,...."
pu.

..... 111"'~

,t"_a... _ .... "''lIn
__ A A

FCOOOH

UCS

The 80Cl86 has three 16-bit timers on-chip. Timer #2
can be a prescaler for the other two timers, which extends timers #0 and # I range out to 2'32. By using

Application

h"" ""0::11",1\7

Initialize HIW, Comm,
flash memory algo's, etc.

Version update code,
Data Accumulation storage,
etc.
40000H

~ _ _ _ ~ • •. ;

achieved.

Vector table, Stack,
Buffers, etc.

Using an External Timer-

0000

External timers can take many forms. One popular example is the 82C54 (CHMOS Programmable Interval
Timer) which has three 16-bit timers on-chip. One timer can be used as a prescaler for the others so that a
count of2'32 can be achieved as with the 80Cl86 internal timers.

Figure 10. 80C186 Memory Map

The permanent code was placed in an EPROM in the
UCS memory segment; this code includes routines for
hardware initialization, communications, data uploading and downloading, erasure and programming algorithms, I/O drivers, ASCII to binary conversion tables,
etc. This would be useful for systems reconfigured for
different communication protocols as the last step prior
to shipment.

5.0 SYSTEM DESIGN EXAMPLE:
AN 80C186 DESIGN
A general purpose controller and/or data acquisition
system was built to demonstrate 86-based ISW. The
80C186 CPU drives the system, which contains
16 Kbytes of EPROM (two 27C64's), 64 Kbytes of
flash memory (two 28F256's), 64 Kbytes of SRAM
(two 32K x 8's) three 8-bit ports (82C55A), one serial
port (82510), and a 5V to 12.0V DC/DC converter.
Three 74HC573's demultiplex the address/data bus
and latch the byte high enable line (BHE) and the
status lines (if needed). Two data transceivers
(74HC245) simulate the worst case data path for a system requiring added drive capability. If the transceivers
are not needed they can be replaced with wired headers.
See Appendix F for detailed schematics parts list, and
changes for the 28F5l2 or 28F010.
The 80C186 reset (output) drives the reset input on the
82510, 82C55A, and the OE\ inputs on the address
latches and data transceivers. The reset line goes inactive 5 clock cycles before the first code fetch. Also, the
CPU's write signal is split into byte-write-high and
byte-write-low to allow for byte or word writes.
The 80C186 has on-chip memory and peripheral chip
selects. Two of the memory chip selects are dedicated.
One is the Upper Chip Select (UCS, dedicated for the
boot area) and the second is the Lower Chip Select
(LCS, for the interrupt vector table area). See the memory map in Figure 10.

Code and constants that might change are placed in the
64 Kbytes of flash memory. Application examples include operating systems, code for rapidly advancing
biomedical technologies such as blood test software, engine-control code and parameters, character fonts for
printers, postage rates, etc. The RAM is used for the
interrupt table, stack, ·variable data storage, and buffers.
The three 8-bit ports on the 82C55A peripheral controller can be used for control and/or data acquisition.
It powers-up with all port pins high. Similarly, all port
pins go high after warm resets as well. Because the pins
are high after a power-up/reset, an open collector invertor was used to control the MOSPOWER switch
which in turn controls Vpp. You must drive the FET
switch to one rail or the other to guarantee its low onresistance. Vpp is turned off during power-up or reset
as a hardware write protection solution. The DC/DC
converter supplies Vpp.
The 82510 is a flexible single channel CHMOS UART
offering high integration. The device off-loads the system and CPU of many tasks associated with asynchronous serial communications.

6-219

inter

AP-316

The part can be used as a basic serial port for the host
serial link, or can be configured to support high speed
modem applications. For more information on' the
82510 see the 82510 data sheet and AP-401 "Designing
with the 82510 Asynchronous Serial Controller".
Software was written to download code and data parameters (code updates) from a PC to the demo board
through the PC's COMI port (serial port). The system
also can upload data (remote data acquisition) to the
PC via the same link.
Once the download code and data has been programmed it can not be lost, even if power should fail.
This is because Intel's ETOX flash memory technology
is based on EPROM technology and does not need
power to retain data.

6.0 SUMMARY
Intel's flash memories offer designers cost-effective alternatives for remote version updates or 'for reliable
data accumulation in the field or factory. Designers will
also benefit from time savings in any kind of code development-no 15 minute waits for U.V. EPROM erasure.
This application note covers the basics of in-system
writing to flash memories and can be used as a check
list for systems other than the 80C186 design shown.
The basic concepts remain the same: a CPU controls
the reprogramming operations; a 12V supply must be
applied to the flash memory for' erasure and programming; and a communications link connects the host to
the remote system and supplies the code to be programmed.

The end result: rugged, solid state, low power nonvolatile storage.

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Ap·3i6

APPENDIX A
ON-BOARD PROGRAMMING DESIGN
CONSIDERATIONS

6-221

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This appendix:

INTRODUCTION
On-board programming! (OBP) with Intel's flash
memory provides designers with cost reduction capabilities for alterable code storage designs. When used in
conjunction with on-board programming, flash memory presents opportunities for savings in two areas:
greater testability in the factory, which translates to
improved outgoing quality and reduced return rate; and
quicker, more reliable field updates, which translates to
decreased product support cost.

• outlines the design considerations associated with'
on-board programming, and the improvements afforded by Intel's flash memory;
• offers guidelines for converting current 64K
EPROM OBP designs;
• designs an 8-bit system for on-board programming;
• suggests some 16-bit flash design considerations;
and offers information on OBP equipment and vendors.

1. With on-board programming, non-volatile memory is programmed while socketed or soldered on the application board,

rather than before hand as a discrete component. This programming method is also called in-module or in-circuit programming, and has been practiced by some major corporations since 1981. See sidebar on following pages for more information
on U.V. EPROM OSP us!!ge.
BOARD-PROGRAMM!:R

HOST APPLICATION

(Printer Shown Here)

< )
292046-29

On-Board Programming Manufacturing Example-A printer is customized via OBP for international markets:
1. printer assembly completed, diagnostics code programmed and tested, and unit stored in inventory;· 2. order
arrives for printer with foreign language font; 3. diagnostics code flash-erased, and desired font programmed; 4.
printer ships to customer.

INTEL'S FLASH MEMORY-DESIGNED
TO MEET YOUR OBP NEEDS

5 Volt Vee Erasure and Programming
Verification

Intel's flash memory simplifies OBP code updates by
offering designers the command register architecture.
As described in section 2.2, this architecture offers the
full reliability of EPROM off-board programming
without the hassles of elevating Vee.

Unlike EPROM OBP, flash memory enables Vcc to
remain at S.OV throughout all operations. Internal circuitry derives the erasure and programming verification
levels from the voltage on Vpp rather than from Vcc.
These verify modes enable use of a single Vcc bus for
the entire board, as opposed to the two buses needed for
U.V. EPROM OBP. (See sidebar entitled EPROM
OBP).

EPROM OSP
EPROM OBP has been a proven manufacturing technique smce1981.1ngetniity and clever citeuit design have
enabled manufacturers to overcome the hurdles associated with OBP and enjoy the benefits.
. .
· In many cases, Intel's flash memory simplities todaT$ S

~-------------

A15

rI l j

Address Bus for
Chip Enables
and Flash Memory
Address Inputs

A13
A12

Ao
07
0

DO
Sys. Interface
Control Lines

{

RESET
MEMWR
MEMEN
MEMRD
WE
Vpp
GND

~-------------

Device Address
I inAIIZ

Ao
07

{

Data Bus for
Input/Output

High Order Address
Line for Memory
Select

'. 1

A14
A 13
A12

}

Data Lines

DO
PSI,
PS 2

CE -

Decoder Enable Line
Read Control Line
WE - Erase/Program Lines
Vpp - Programming Power

OE -

GND

--------------)

292046-30

NOTE:
During normal system read operation, all interface traces are left open-circuited. Some of the lines have pull-downs or
weak pull-ups to insure proper device operation.

Figure 2. System to Board-Programmer Interface

EPROM OBP (cont'd) ,
~ Special U.V. board eraSers must be purchased, at si,gnificant costs and With limited throughput. A low-end
U.V. bulb costs $75-$100 each. A U.V. board eraser system could cost upwards ofSlO,ooo, with recurring costs
of light bulbs and energy. Thus, the cost of U.V. erasure is often under-estimated. ,
.

. ~ Although pc.lrtable board programmers are commercially available, U.V. 'light$ by nature are not very
~, and arc not suited for out·of.factory code updates. This complicates field service.

-+ Erasurc can be easily controlled in a lab environment; however, it is not as cleat on the manufacturing floor
which label to remove for U.V. erasure. because parts other tluul E})ROMs have windows (i.e. RPLD's, microcontrollers with embedded EPROM memory. etc.)

6-225

AP-316

At first all of these alternatives may seem expensive or
superfluous, but keep in mind that the cost of a single
cable and programmer gets amortized over the total
number of systems programmed.

The System/Board-Programmer Hardware
Connection

In most U.V. EPROM OBP applications, designers use
the board's edge-connector as the programmer interface. This approach is the lowest cost solution for standard EPROM technology because U.V. erasable devices require system disassembly for erasure anyway. 'With
flash memory, you can eliminate the system dismantling and capitalize on the erase feature by adding a
cable connector to the board for reprogramming purposes. The connector should extend from the board
through the system's chassis, and should be easy to
reach by a serviceman.

AN 8-BIT BUS DESIGN EXAMPLE
An example of an in-circuit reprogrammable controller
board is an SOC3!, two 2SF256's and some glue chips.
(See Figure 3. for a system block diagram. See Appendix A. for a detailed system schematic.)3 The important
issues for erasure and reprogramming are as follows:
1. the board-programmer must have uncontested access
and control of the flash memory array; and
2. the microcontroller must be reset (un-active) during
the erasure and programming cycles.

Various types of cables exist on the market that could
be used to connect programming equipment to the system. The key design consideration when choosing the
type of cable is elimination of all transient noise that
would interfere with the programming or erasure process.

SYSTEM DESIGN

Three types of noise interference and methods to diminish the noise are as follows:
1. line to line cross-talk (due to board-programmer's
drivers that drive sharp step functions on adjacent
address lines); solved with either ribbon cables, having alternate lines grounded, or with braided twistedpairs that have a ground line for each active signal;
2. programmer line-driver-to-board impedance mismatches leading to transmission line effects of signal
reflection, and interference; solved by limiting cable
length, decreasing programmer switching speed (or
allowing longer settling time between address
switches) or by using matched line drivers on the
programmer and high impedance buffers on. the
board end, or by using series termination resistors on
the driving end of the cable (i.e.-board-programmer
end, with the exception of the bi-directional data bus
which needs series resistors at both ends);
3. rf pick-up in electrically noisy environments; use either shielded cable such as cOax, ribbon cable with
solid copper ground plane, or a new type that has
recently become available called Flex cable.
Braided twisted-pair cables when kept under three feet
in length generally reduce cross-talk to acceptable levels. This type of cable offers the most cost-effective solution which works well in most applications. Depending on the environment, the programmer and your design, you may need a combination of solutions, such as
braided twisted-pairs with series termination.

Bus Control Circuitry

The SOC3! has an active-high reset pin, which tristates
the address and data bases. Route this line (RESET) to
the programming connector. Tie the OE pins on the
low-order address latch (74HCT573), and the PSEN
buffer-enable (74HCT125)4 together, and route that
line MEMWR5 to another pin on the programmer-interface connector.
During normal system operations when the IkC reads
program code from the 2SF256 devices, the pull-down
on MEMWR keeps the address latches and PSEN buffer active. During flash memory OBP, the board-programmer drives MEMWR active-high, which disables
these outputs, and isolates the address bus and PSEN
from the programming signals.
The board-programmer must independently control the
RESET and MEMWR traces because they disable at
different VIL values (2.5V for RESET vs O.SV for
MEMWR). If controlled by the same 5V supply, on
power-up or after a reset condition the IkC would try to
execute code while still isolated from its code sourcespecifically before the address latches and PSEN buffer
activate.
.Address Decode Circuitry

This design shows two 2SF256 flash memories. Systems
with more than one memory device typically decode
the CPU's high-order address to select a particular device.

3. Note that the flow-through latch on the data bus is not needed with the 80C31 , but is drawn as an example for CPU's that
can not tristate their data bus.
4. The isolation buffer is required on PSEN in this design because the 80C31 goes into unspecified states when the Reset
and PSEN lines are active simultaneously. To avoid any possible problems, buffer PSEN.
5. MEMWR = > bus isolation control of PSEN and the data bus.

6-226

~i"

RESET

Reset

t.lEt.lEN

A15 '

J
CE

As -A I5

iil

en
-CD
o
~ 3
-.J CD

A15

Ao-AI4

Ao-A 4

J. ~ J.~

• Port 1

28F256
• Port 3

ALE
ADo-AD7

Latch

8
Do-D7

OE
'--- Q

Vpp

.:r:.

---,
CE
15

Dt-Flow
Through
Latch

t.lEt.lWR

PS2

I--- t.lEt.lRD

Progl emmar
Edge
Conn ector

WE
Vpp

Ao-AI4

DO-D7
28F256

...
~

-=-

"tI

"!:

iil

V pl ;

-L

PSEN

~pp
OE

CRT
Interface

...

WI'.~

80C31

PSI

DO-D '7

..r

GND
292046-31

inter

Ap·316

This is accomplished as illustrated. When AI5 is low,
the lower 32K bytes are selected. The output of the
inverter drives the other 28F256's chip enable. This
type of memory architecture promotes power savings
by disabling all memories but the one being addressed.

buses into a high impedance state. Next PS2, which
controls MEMWR should be tristated thus disabling
the PSEN/Address latch isolation. Finally the boardprogrammer should switch PSI, which drives the RESET line to reactivate the /LC. This sequence guaran-'
tees that the /LC will begin operation at a known program code location.

To accomplish this two-line memory control architecture, route the inverter's input A 15 to the 80C31 and to
the programmer interface connector. 8 The board-programmer controls the inverter's output enable with
MEMEN.9 The MEMEN line performs the function
normally performed by CE in component programming. When driven to a logic "I" level MEMEN pulls
the inverter's output high. This deselects all memory
devices controlled by that I.C. During normal read and
standby operations, the pull-down on MEMEN keeps
the decoder enabled.

16·BIT BUS DESIGN
CONSIDERATIONS
An example of an On-Board programmable 16-bit system board would be an 80CI86 microprocessor, two
28FOlO flash memories, RAM, and some glue chips.
The basic hardware design considerations would be the
same as those in the previously discussed 8-bit bus example.

Erasure and Programming Control Circuitry

There are a few issues with l6-bit designs that do not
arise in 8-bit designs. For the programmer to take control of the system, it must tristate and ,reset the /LP as
well as tristate the bus buffers and latches. The HOLD
and RESET lines of Intel's 86-based fa~ily of microprocessors have been designed with bus isolation in
mind for use in multiprocessor systems.

In this design, Vpp and WE are active only during reprogramming. At other times, the two inputs would be
inactive. Simply tie the WE line to Vee through a pullup resistor. The pull-up limits the current to the board
programmer during reprogramming. (Recall that WE
is active low.) Flash memories allow Vpp to be at 12V,
Vee or ground for read operations. This design ties
Vpp to Vee through a diode and resistor to allow for
EPROM OBP compatibility. If this option is not required, simply tie Vpp to ground through a currentlimiting pull-down resistor.

The designer has two options for erasing and programming the high and low bytes of the flash memory array
independently.
I) The designer can route two WE lines to the programmer connector-BYTE HIGH WE and BYTE
LOW WE.

Returning Control to the Host System

The board-programmer should return system-control
to the host processor in an organized manner. First it
should lower Vpp from 12V to 5V, or ground. Then the
board programmer should place its address and data

2) The reprogramming software can follow the masking
procedure shown in section' 4.4. This method allows a
common WE line for the high and low bytes.

8. Note the lack of isolation buffers between the 80C31 's high order addresses (Port 2) and the board-programmer interface;
compared to the latch separating the low order addresses (Port 0) and the interface. In this design example, we make use of
the 80C31 ,s ability to tristate these ports, so no isolation is needed for any of the addresses. The latch on Port 0 is for the
time-multiplexed address/data architecture of this microcontroller, and not specifically for isolation.
9. MEMEN = memory enable, active low.

6-228

J 31

f>.
c,J!
"11

ili
c:

(1)

!.
iii

I\)

co c:

III

C
(1)

III

ijj'
~

GND

10 9
~
R.set

':"

A'5

.:: S
:~ ',§l

:1" 2

;

RT
"
~
Interface

y~
@

A2
1 AI

Vee

AD,
Ao., 32

19 XTAL.

PS[N~

':'

2~CC

:::T

@ 0, 9

,~ °0 ,
l~===~ g~

02
J

GND
~
10

(j) - 12WHz OSC C, -

-7"HCTI38

10~r

C:2.c, -

O.llo'r

@-74HCT5730,-IN914

5 ,,,

@ - 74HCT573-

R, - 8.2k.o.

®-

Rz.R4,RS - 10k4
R3- 1k4

7.HCTIlS

0.1 }.'f c:op on 011 VCC

p~ns.

'"Th. 7"HCTS7] I. only needed If thl Jl.C'1 Data Bus does

not trtstot. durlng RIMt.

»
'U

...
I

DE
24

CJ~

J'3

.:I:

gCEOEbt",4

,,"=- '"
L...-.....-j
""
-----,
"12
~O

Vo:: 1

y~~ tii---

....

::
"3

o.,lll;'~~~~~~~~
~

DS
l8F2S6

D3 '5

;

t---m

---.J

JJ5

~_ _ _ _ _ _

Ko,

J l4

DD'b I

(

o,.l'~~~~@~~~~
~:

28F256

GHD

WE 31

LEI!

yQ~D68

(1)

':"

Vpp 1

if,

L.._ _ _..J

o,.@o, 112_

::~

D,' :.
¥" .

Vee

A:~
At

!:~

GNO DE

XTA~

en
n

22
29 :"CE

l£ Vee

F EA::

~DOUT

AlE 30

lO GNO

Illl

~llt I

80C31

•

Yo 15

10 R

D-

IP
Cl
ID
-'> ;;

Vee

~ ~4

EDGE
NNECTOR

i,
I

'ARD
I'8oA~

Ao
PO
L...;:,,";:D~_.J

'~
-

~
~
!
[
!
!

292046-32

intJ

AP-316

OBP EQUIPMENT AND VENDORS
If you are considering OBP for your next design, and
have not used on-board programming before, you will
need to choose a board-programmer vendor. Various
suppliers offer OBP systems; therefore, it is well worth
it to send out requests for programming support bids. If
your production volume justifies the purchase of more
than one board-programmer, you may want to negotiate a non-recurring engineering charge for development
cost, followed by variable costs for additional units.

Most vendors offer a variety of basic systems, designed
to easily adapt to your needs. Systems can be purchased
that program either single boards serially, or a number
of boards in parallel. Light-weight OBP equipment designed for field reprogramming can also be obtained
from some of the vendors.
Most companies will work directly with you at the beginning of your design phase to ensure OBP compatibility. If your design is beyond the definition stage, the
programmer manufacturer will request a copy of your
schematics or block diagrams under non-disclosure.
The vendor has an OBP design specialist that will
check the design for OBP compatibility. Any potential
problems will be located and corrected at this early
stage.
Every board's architecture is different (i.e., based on
different central processing units (CPU), decoding
schemes, buffering methodologies, interface connectors,
and types and densities of memories). Vendors write
custom software modules for each application. Also,
the vendor or the board designer typically builds an
.interface jig to connect tile board's edge connector to
the programmer. This choice is often left as a decision
for the designer.

Partial List* of Companies Selling
Board-Programmers
Following are a few of the companies who offer onboard programming solutions today:

Data I/O Corp.
Digelec
Elan Digital Systems
Oliver Advanced Engineering, Inc.
Stag Microsystems, Inc.
'This list is intended for example only, and in no way
represents all companies that support on-board programming. Intel Corporation assumes no responsibility for circuity other than circuitry embodied in an Intel product. No other circuit patent licenses are implied.

SUMMARY
• On-board programming (OBP) has been around
since 1981.
• Designing a board for OBP can be easily done by
working with a board-programmer vendor's OBPdesign-specialist during the initial design phase.
• In-circuit alterable code storage can be easily implemented by using flash memory and it's features.
• Time and money savings can be realized in a number of ways by taking advantage of flash memory
OBP:
< > Decreased board costs and improved reliability
from elimination of EPROM sockets;
< > Decreased manufacturing costs from elimination
of board eraser depreciation costs, recurring U.V.
light bulb and energy expenses;
< > Decreased inventory expense from simplified test
and rework methods (one-step diagnostics, erasure, and board configuration);
< > Decreased product costs based on decreased
board-handling loss;
< > Improved board diagnostics and testability leading
to higher quality and decreased customer returns;
and
< > Quicker, more reliable field code updates.

6-230

inter

AP-316

APPENDIX B
Vpp GENERATION CIRCUITS
Circuit
Circuit
Circuit
Circuit
Circuit
Circuit

# I-Regulation from a higher voltage
#2-Regulation from a higher voltage
Ii 3-Regulation from a higher voltage
#4--5V to 12V Boost
#5-5V to 12V Boost
#6-Monolithic DC/DC Convertor

Circuit #1
Down Conversion
(From 14.0V-2B.OV to 12.00V)
Vln )---0-- In

Vee

Out H _.....-O~ VoU!

LM2391CT

R3
OnlOO

vpp

Enable

GncI

AdJ

>-~~:::r--I--LI=

' ;::r- C2

~ LrV~~t-~-1~20;(R1iR2-~-1i-l
________________________ .. ____
.J

292046-12

COMPONENTS

COST·

LM2391CT
R1 = 20 KIl,1%
R2 = 180KIl,1%
R3=10KIl
C1 = 0.1 /-IF
C2=100/-IF

$0.75
0.045
0.045
0.02
0.02
0.15
$1.03

NOTES:
-The LM2391 offers an enable pin for added data protection.
-The drop out voltage is O.BV.
-R3 is NOT required if Vpp enable is driven by a CMOS device.
·Cost approximations assume 10,000 piece quantity.

6-231

AP·316

Circuit #2
Down Conversion
(From 16.00V-26.00V to 12.00V)

Vln>---.--iln

LM.317

You!

-o

Outf-....-

....

Voltage Regulator

~ Rl

Ad)

{1%

IL---___•

1%$

iVoui-;--i25Y-(R2TR1-+--W!
L_~

.. __________________________________ -I

292046-13

COMPONENTS

COST·

LM-317
Rl = 1240,1%
R2 = 10700,1%
Cl = 0.1 ,...F
C2 = 100,...f

0.40
0.045
0.045
0.02
0.15
$0.66

NOTES:
LM-317 requires a minimum VIN-VOUT = 3.0V
·Cost approximations assume 10,000 piece quantity.

Circuit #3
Down Conversion
(From 15.0V-40:0V to 12.00V)

Vln>---.--iln

LT1085

Out

Voltage Regulator
Cl

Yout

'~ R1

Ad)

<;
R2

' . 1%<;<>

iVout-;--i25Y-(R-1iR2-+--1)-!

L _____________________________________ ..t

292046-14

COMPONENTS

COST·

LT-l085
Rl = 1240,1%
R2 = 10700,1 %
Cl = 10,...F
C2= 10,...F

2.50
0.045
0.045
0.10
0.10
$2.79

NOTES:
LT-l085 requires a minimum VIN-VOUT = 1.5V
'Cost approximations assume 10,000 piece quantity.

6-232

Ap·316

Circuit #4
. Up Conversion
(From 5V to 12.0V)
5V

lotT"" ~"
_

150uH

Vpp

.--.....- -....- - - 0 OUTPUT
LT1072

200mA MAX

Vpp

FB 1--....- .

COMMAND

GND

292046-33

COMPONENTS

COST"

lTl072
Rl = 10.7k, 1%
R2 = 1.24k, 1%
R3 = lk,5%
R4 = 120k, 5%
R5 = 270k,5%
Cl = l,...F
C2 = l,...F
C3 = 10,...F
11 = 150,...H
Ql = 2N3904

1.82
0.045
0.045
0.02
0.02
0.02
0.10
0.10
0.15
1.00
0.10

VppOUT

12.0V

$3.42
NOTES:
Drive Vpp COMMAND low to turn on the circuit.
·Cost approximations assume 10,000 piece quantity.

6-233

10.7k 1.24k

Resistor
Tolerance

intJ

AP-316

Circuit #5
Up Conversion Circuit
(From 5.0V to 12.0V)

5.00v

VppOul
, - - - - - - - - - - - - - - - - - - - - , 11
+5v
v+ 1-....- - - 0
24 +5v
V+ 14

Valor

PM7006

V-

Vpp
Enable >--.,..-!---'

292046-16

COMPONENTS

COST"

PM7006
Cl = O.l,..F
BuzllA

$6.25
0.05
2.59
$8.89

NOTES:
1. The capacitor decreases output noise to 140 mV pk-pk.
2. We added the Buzl1 A Mospower nFET to. enable/ disable the converter. This control minimizes power consumption
which under full load can reach 600 mAo
3. The voltage drop across the switch is O.lV. Due to this drop the PM7006 will not maintain the Vpp spec with 10%
fluctuations in Vee supply.
"Cost approximations assume 10,000 piece quantity.

6-234

AP-316

APPENDIX C
LIST OF DC-DC CONVERTER COMPANIES
BURR-BROWN
I'.U. Hox 114UU

Tucson, AZ 85734
(602) 746-1111
CARITRONICS INC.
P.O. Box 821
West Caldwell, NJ 07007
(201) 575-8916
LINEAR TECHNOLOGY CORP.
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
(408) 432-1900
NOVA-TRONIX
4701 Patrick Henry Dr. #24
Santa Clara, CA 95054
(408) 727-9530
RELIABILITY INC.
(713) 492-0550
SEMICONDUCTOR CIRCUITS INC.
49 Range Road
Windham, New Hampshire 03087
(603) 893-2330.
UNIVERSAL MICROELECTRONICS
Marcon Sales Inc.
2672 Bayshore Parkway, Suite 1000
Mountain View, CA 94043
(415) 964-8046
VALOR ELECTRONICS
6275 Nancy Ridge Dr.
San Diego, CA 92121
(619) 458-1471

6-235

inter

AP-316

APPENDIX D
PARALLEL ERASE FLOW CHART

COMMENTS·

Wait for Vpp to stabilize.
Use Quick-Pulse Programming
algorithm.
Initialize Variables:
PLSCNT_HI = HI Byte Pulse
Counter
.
PLSCNT_LO = Low,Byte Pulse
Counter
FLAG = Erasure Error Flag
ADRS = Address
E_COM = Erase Command
V_COM = Verify Command

INITIALIZE:
PLSCNLHI=O
PLSCNLLO =0
FLAG;;; 0
ADRS = 0
E·_COM = 2020H
• V_COM = AOAOH

Erase Set-up Command
Start Erasing

Duration of Erase Operation.
Erase Verify Command stops
erasure.
See next page for subroutine.
When both devices at ADRS are
erased, F_DATA=FFFFH.
If not equal, increment the pulse
counter and check for last pulse.
Reset commands to default
(E_COM = 2020H,
V_COM = AOAOH)
before verifying next ADRS.

Reset devices for read operation.

Turn off Vpp.

292046-34

6-236

inter

AP-316

Device Erase Verify and Mask Subroutine
COMMENTS
This subroutine reads the data word
(F_DATA). It then masks the HI or
LO Byte of the Erase and Verify
commands from executing during
the next operation.

If both HI and LO bytes verify, then
return.
Mask' the HI Byte with OOH.

LCOt.l = (LCOt.l OR OOFFH)
V_COt.l = (V_COt.l OR OOFFH)

If the LO Byte verifies erasure, then
mask' the next erase and verify
commands with FFH (Reset).
If the LO Byte does not verify,
increment its pulse counter and
check for max count. FLAG = 1
denotes a LO Byte error.

Repeat sequence for the HI Byte

FLAG = 2 denotes a HI Byte error.
FLAG = 3 denotes both HI and LO
Byte errors.

292046-35
NOTE:
"Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming flash
data (F_DATA), the erase commands and the verify commands. Then manipulate the HI or LO register contents.

6-237

inter

AP-316

APPENDIX E
PARALLEL PROGRAMMING FLOW CHART

COMMENTS

Start Program
Wait for Vpp ramp to VPPH

ApplyVPPH
Get AORS/P_OAT

ADRS = address to program
P_DAT = data word to program

Initialize:
PLSCNT_HI = 0
PLSCNT_La = 0
FLAG = 0
V_OAT = P_OAT
P_COM = 4040H
V_COM = COCOH

Initialize Data Word Variables:
PLSCNT_HI = HI Byte Pulse
Counter
PLSCNT_LO = LO Byte Pulse
Counter
•
FLAG = Program Error Flag
V_DAT = valid data
P_COM = Program Command
V_COM = Verify Command

Write xx/P_COM

Program Set-up Command
xx = Address don't care
Program

High/Low Byte
Compare & Mask
Subroutine

See next page for subroutine
Program Verify Command

F_OAT = flaSh memory data
Compare flash memory data
to valid data (word compare). If not
equal, check for program error
flag. If flag not set, compare High
and Low Byte in subroutine.

N
Check buffer or I/O port for
more data to program.

Reset device for read operation.

ApplyVPPL

Program Error

Program Complete

Turn off Vpp.

292046-19

6-238

·....;._f

I.-.~

Ap·316

Program Verify and Mask Subroutine
COMMENTS
To look at the La Byte. mask"
the HI Byte with 00.

P_COM = (p_COM OR OOFFHl
V_COM (V_COM OR OOFFH

If the La Byte Verifies. mask
the La Byte commands with
the reset command (FFH).

If the La Byte does not verify.
then increment its pulse
counter and check for max
count. FLAG = 1 denotes a
La byte error.

Repeat the sequence for the
HI Byte.

FLAG = 2 denotes a HI Byte
error. FLAG = '3 denotes both
HI and LO Byte errors. FLAG
= 0 denotes no max count
errors; continue with algorithm.

292046-40

NOTE:
"Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming data
(F-DAT). the program commands and the verify c;ommands. Then manipulate the HI or LO register contents.

6-239

inter

AP-316

APPENDIX F
DETAILED SYSTEM SCHEMATICS
,

Vee
Vee

TIS
SRoV
MoV

r--vccf#

BHEi&<

.02
01

A17/54

A16iS3

00
11 LE

ALEi.,

AD15
AD1.
AD13

ao~
G~

0001

GNO
7

"ft

04
03131
02
01

A07

AD6

....

Vee

A7
AS
AS
A4
A3
A2
A1

AQ3

03 (4J
02
01

02
01

05
Q3

DO ~
-...l.I LE GNo

- --

m:so 38
MC!I

~~A3

(1J

~A2
Al

PSW1

NJ
olR

DTtA 40

(5J

015
014
013
012
011
010
09

:sa

821
81

--1l DE GNo~
'--

RESETisz

r
9

A7
AS
~ AS
~

(71

Vee
B7
B6

A2
~ A1
"AO
DlR

......=:J:

06
05
04

82
B1
SO

02
01

GNo

'--

RESET

~=.=

to-

~ I..

i'e"S3

Ii195l

-v.;;;
_~A7

8OC188

A1S
A17
A1S
A15
A14
A13
A12
Al1
A10
A9
AS

f-I

A02
A01
AOO

llEIi

1Il'

RES

12:5~ INTO
INT 1
INT 2
. - U INT 3

W!;LOW

05
04

':'

rf>'

W!; ~'r.H

"""

ADS
A04

OE~
~~-

l1l'l!1 ..
L

...L C1

,.
-y'y
1

....

07
as

A09
ADS

A012
A01t
A010

Vee

D2 17t::

OSC-l

'--

~i63

Vss
Vas

03 121

A191S6I ..
A181SS

MNI
HOLD

07
as

07
S 06
705
604

03
00

12:18
19:6

292046-21

6-240

inter

AP·316

120
~

120
Vee
Vpp

~
~
~

PGM

A12
All
Al0
A9
AS
A7

r!--

8~
§

0E22
0719
06

g~ ~~

D3
021
01
DO 11

A2
Al
AD

(8L]

GNO~

122 i32

A18
A17
A16
A15
A14
A13
A12
All
Al0
A9
AS
A7
AS
AS
A4
A3

A2
Al

A16
A15
A14
A13
A12
All
Al0
A9
AS
A7
AS
A5
A4

Vpp L -

ClE

07 1
06
05
04
D3 17
02
01
DO

A2
Al
AD

WE.ll

(9L(

~
~

0E22
0719
06
05
04
03
021
01
DO 11

••

A4
A3

A2
Al
AD

(8H(

GNO~

A17~
A16
A15
A14
A13
A12
All
Al0
A9
AS
A7

GNO~

i32

Vee

WE
Vpp

ClE

r!-24

07121
0620
05
041
D3
02
01 14
DO

AS
A4
A3

A2
Al
AO

.L...

i'llM~

A12
All
Al0
A9
AS
A7
A6

122

Vee

A17~

Vee Z§..
Vpp

(9H]

GNO~

DO
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015

292046-22

6-241

AP-316

DE
WE HIGH
WE LOW
Les

20
CE

A,s
A,.
A'3
A'2
A11
A,o
Ag
A8
A7
A6
As

A.
A3
A2
A,

1 A,.
26 A'3
A'2
23 A11
21 AtO
Ag
25 A8
3 A7
4 A6
As
6 A.
A3
8 A2
9 A,
1 flo

t
vcc~
WE

OE 22

0719
0618
0517
0.16
031
0 2 13
0,
Do 11
110L)

q
q

~
~

GNO~

A,.
A'3
A'2
A11
A,o
Ag
A8
A7
A6
As
A.
A3
A2
A,
Ao

vcc~
WE

DE 22
07 HI
08 18
05 17
0.16
03 15
02 13
0,1
Do 11
110H)

GNO~

DO
0,
02
03
D.
Os
06
~

08
09
0'0
0 11
0'2
0'3
0,.
D,S
292046-23

6-242

AP-316

35 RESET

RESET
1:27

es·
AD

Wi'!

WAIOW
W

o7
o5
o4
o3

27 Eq
28 O.
Os

82C55A
(151

31 0_

"" ""Do

PA,
PA,
PAo
PB7 25
PBo
PBs
PB_ 22
PS,
PBD

PC7 10
Pc.
PCs
PC. 3
PC_ I
PC,
PC,
PCD

~ Vee

-F

~g~

i?2

PA3

PA_

4:1 7 A
4:1 8

PA7 7

GND

lh24
Vee Vee
Vpp

14 +V

L.!.

+V
DC/~C

15 -V

5112.00±5%
(161
GNOl2

GN013

.::0

~
5

-:~

6-243

I
2

~
(171

292046-24

AP-316

+12V

F~kJ

7 GNO Vee 14

Out

8
X2

Vee

RESET
RO
WR

1:25
RESE T

~LOW
A3
Az
A,

24 A2
23 A,
Ao

07
D6
Os
D,
03
D2
D,
Do

4 D7
06
Ds
D,
~It 03
2. D2
0,
zo Do

9
X1 TxO 6
OTR
RTS
RxO 13
CTS
Rlll0
OSR

j4
Vee
lA 1
31Y
2Y
1489
: 10
83Y
4Y [13) 4A l~

Jl:4
GNO

Jl:7
....c-::-

Jl:3
Jl:5
Jl:22
Jl:6

GND

-J.
DCD 12

31Y

h4
Vee

lA 1

8 ~~ 1469 ~~ lio
11 4Y [14) 4A 13

7 GNO

Jl:2
Jl:20

J. J.

5 INT

1.45

14
Vee +
21A
lY 3
2A
2Y
28 1488
3A [12[ 3Y 8
38
Vee- GNO

Jl:8

GND

82510
[11]

~
-

6-244

292046-25

iniJ

AP-316

256K FLASH MEMORY DEMO PARTS LIST
Device
[1]
[2,3,4]
[5,6]
[7]
[8L,8H]
[9L,9H1
[10L,10Hj
[11]
[12]
[13,141
[15]
[16]
[17]
C1
01
F1
J1
OSC-1
OSC-2
R1
R2
SW1

Component
80C186
74HC573
74HC245
74HC32
27C64
28F256

Description

Pins
68
20
20
14
28
32

::l~Kxt:lSRAM

82510
14C88
14C89
82C55A
PM7006
7406
20/kF
1N914
BUZ11A
DB-25
20 MHz
18.432 MHz
10 KO
1 KO

28
14
14
40
24
14
2
2
3
25
14
14
2
2
3

16-bit high integration CPU
Latch
Transceiver
OR gate
16 Kbyte EPROM
64 Kbyte flash memory
64 KiJyie SRAiv;
Asynchronous Serial Controller
RS-232 Line Driver
RS-232 Line Receiver
Programmable Peripheral Controller
DC/DC Convertor (5V-12.00V)
Invertor-Open Collector (O.C.)
Capacitor for CPU reset
Diode for CPU reset
MOSPOWER nFET
Connector (male)
CPU Oscillator
Serial Controller Oscillator
%W, 10% Resistor for CPU reset
%W, 10% Resistor for O.C. pull-up
Momentary Push Button for CPU reset

NOTES:

1. Place a 0.1 p.F bypass capacitor at the VCC input of each IC.
2. Place a 0.1 p.F bypass capacitor on the Vpp input of each 28F256 flash memory.

28F512 UPGRADE FOR THE
80C186/FLASH MEMORY DESIGN
To upgrade the 80C186/Flash memory design to handle 28F512's, the range of the CE signal has to be increased. There are a number of ways to generate a CE
signal that will span the 128 Kbyte address range of
two 28F512 devices.

2. Change the MCS individual block-select size from
64 Kbytes:
MMCS_VALUE = 41F8H,
MPCS_VALUE = OAOB8H

1. AND two of the current MCS lines together (defined'
for 64 Kbytes each); or

6-245

to 128 Kbytes:
MMCS_VALUE = 0IFEH,
MPCS_VALUE = OCOBEH
Also, cut the CE trace to the RAM sockets. Then
wire MCSO to the RAM CEo This eliminates the
MCSO and LMCS range overlap caused by increas~
ing the MCS range to 128 Kbytes. See 80C186 Data
Sheet page 21 and 22 (Order # 270354).

inter

Ap·316

28F010 UPGRADE TO THE
80C186/FLASH MEMORY DESIGN
To upgrade the 80C186/Flash memory design to handle 28FOlO's, a CE signal has to buenerated. There
are a nu~ber of ways to generate a CE signal that will
span the 256 Kbyte address range of two 28FOIO devices.
1. AND two of the MCS lines together (defined for 128
Kbytes each as noted in the 28F512 modifications):
Cut the LMCS trace to the RAM sockets. Connect
MCSO to CE on the RAM sockets (UIOL,UH).
Cut the MCS2 trace to the flash memory. Add an
AND gate. Connect MCS2 (cut trace) and MCS3 to
the inputs of the AND gate. Then wire the AND
gate output to the CE of the flash memories ..
Also, change the onboard memory MCS register to:
MMCS_VALUE = OIFEH, MPCS_
VALUE=OCOBEH [128K blocks],
and delete:
LMCS_REG and LMCS_Value.
2. Add a decoder;
Add a decoder (74HC138). Connect address lines
A18 and A19 to the B and C inputs of the decoder.
Tie the A input of the decoder low, and enable all the
enables. B~sing outputs YO, Y2, Y4, and Y6, you
have four CE lines decoding 256 Kbyte blocks each.
Cut the MCS2 trace to the flash memories. Connect
the Y2 output from the decoder to the CE input of
the flash memory.

3. Replace the address latch (U2) with a PLD that
latches and decodes.
Program a 5C032 as an integrated latch and decoder.
Replace the upper address latch [U2] with the Intel
5C032 EPLD. Cut the CE trace to the flash memories. Connect the flash memories' CE to the 5C032
pin 12. This maps the address space 40000H to
7FFFFH. See Figures 1 and 2 for a comparison of
the 74HC573 (U2) and programmed 5C032 pin outs.
Figure 3 is the source code for the EPLD. .
Also, change the value of the MMCS and MPCS
registers to 64 Kbyte blocks so that the MCSO range
does not overlap the LMCS range.
MMCS_VALUE= 4lF8H, MPCS_
VALUE= OAOB8H.

RESET

Vee

A 16

LA 16

A17

LA17

AlB

LAIB

A 19

LA 19

BHE

LBHE

LS o

LSI

LS 2

GND

ALE

292046-36

Figure 1. Latch Pinout

RESET

Vee

A 16

LA 16

A17

LA17

AlB

LAIB

A19

LA 19

BHE

LBHE

cr (40000H-OBFFFFH)
cr (80000H-OBFFFFH)
.cr (40000H-7FFFFFH)

So
SI
S2

GND

ALE

292046-37

Figure 2. Integrated Latch and Decoder

6-246

intJ

AP-316

Thom Bowns - PLFG Appl!cations
Intel
.
January 13, 19S9
EPLD HOTLINE: 1-SOO-323-EPLD
002
5C032
Custom Latched Decoder
OPTIONS: TURBO=ON
FilRT; 5CQ3;a

INPUTS: ALE@ll, RESET@l, A19@5, A18@4, A17@3, A16@2, nBHE@6
OUTPUTS:

LA1S@17, LA17@18, LA16@19, LnBHE@15, nCE3@14, LA19@16,
nCE2@13, nCE1@12

NETWORK:
ALE = IN (ALE)
RESET = INP (RESET)
nRESET = NOT (RESET)
A19 = INP (A19)
A1S = INP (A1S)
A17 = IMP (A17)
A16 = INP (AlS)
nBHE = INP (nBHE)
LA19, LA19 = COIF (LA19d, nRESET)
LA1S, LA18 = COIF (LAiSd, nRESEr)
LA17, LA17.= COIF (LA17d, nRESET)
LA16, LA1S = COIF (LA16d, nRESET)
LnBHE, LnBHE ='COI~ (LnBHE, nRESET)
nCE3, nCE3 = COIF (nCE3, nRESET)
nCE2, nCE2 = COIF (nCE2, nRESET)
nCE1, nCEl ? COIF (nCE1, nRESET)
EQUATIONS:

LA19d = A19 * ALE + LA19 * IALE;
LA18d = A18 * ALE + LA18 * !ALE;
LA17d = A17 * ALE + LA17 * !ALE;
LA1Sd = A16 * ALE + LA1S * !ALE;
LnBHEd = nBHE * ALE + LnBHE * !ALE;
nCE3d = nCE3EQN * ALE + nCE3* !ALE;
nCE2d = nCE2EQN * ALE + nCE2 * !ALE;
nCEld = nCE1EQN * ALE + nCEl * !ALE;
nCE2EQN = !(A19 * !A18);
riCE1EQN:;: ! (!A19 * A18) ;
nCE3EQN = !( !A19 * A18 + A19 * IA18);

ENDS
Figure 3. Source Code for the Integrated Latch and Decoder .

6-247

APPLICATION
NOTE

. Ap..341

October 1990

Designing an UpdatableBIOS
Using Flash Memory

.' ..

DON VERNER

APPLICATION ENGINEER

Order Number: 292077-001
6-248

Ap·341

CONTENTS

PAGE

1.0 INTRODUCTION ....................... 6-251
2.0 FLASH MEMORy ...................... 6-251
2.1 EPROM Roots; Review of EPROM
Process vs. EPROM & EEPROM ........ 6-251
2.2 Stop Timers .... : ................ :...... 6-252
'" n

r-I __ ........ ____ ••

n: __ .• & _ _ _ ..... nl."" .... :,.. .... 1

c..~

.-IQo:IIll IVIt;;IIIUI

I-VUl":» D,IIU I

IIY';)I""'1tI1

Layout ................................... 6-252
2.4 Vpp Specifications ...................... 6-257
3.0 HARDWARE DESIGN CONSIDERA·
TIONS (BLOCK DIAGRAM OF SYSTEM) 6-258
3.1 Modifying an EXisting Motherboard ... . 6-260
3.2 Vpp Generation ..................... : : . .6-261
3.2.1· Using System 12V Directly .......... . 6-261
3.2.2 Pumping SV to 12V ................. . 6-261
3.2.3 Using a MOSFET Switch ........ .' .. . 6-263
3.3 Ideas for Using Extra Adaptor Space .. . 6-264
3.4 BIOS Boot Code Requirements ., ..... . 6~265
3.4.1 Socketing a Flash-Only Design ..... . 6-265
3.4.2 Small EPROM for Boot Recovery, .
Flash the Rest ............... : . .' ...... .. 6-265
3.4.2.1 8K EPROM at Top of Memory
Map ..................... : ..... ; ......... . 6-265
3.4.2.1 8K EPROM at Bottom of BIOS
Code ............... : ................. .. 6-267
3.4.3 Half EPROM, Half Flash ............ . 6-268
3.S In-System Write VS. On-Board
Programming ........................... 6-268
4.0 SOFTWARE DESIGN
CONSIDERATIONS ....................
4.1 Update Software for a Modified System .................................
4.2 Pseudocode Overview ................
4.3 Initializing the System .................
4.4 Code Loader Routine.. .. .. .. .. .. .. ....
4.S Reprogramming Routines .............
4.S.1 Quick Erase ™ Algorithm .............
4.S.2 Quick-Pulse. Programming T.
Algorithm ...............................
4.6 Timing Calibration .....................
4.6.1 Using the Processor .. . . . . . . . . . . . . . ..
4.6.2 Using System Timers to Self-Calibrate
Software Delays ........................

6-249

6-269
6-270
6-270
6-271
6-272
6-272
6-272
6-272
6-275
6-275
6-275

AP·341

5.0 SUMMARY ........................... 6·276
5.1 traditional BIOS Storage arid . ,
Disadvantage ........................... 6·276
5.2 Advantages of an Updatable BIOS with
Flash Memory ........................ :. 6·276
5.3 Advantages of Adding ROM-DOS and
. . Applications .......................•.... 6·276
Advantages of Adding Resident
'
Appiication Code ....................... 6·277

5.4

Appendices

A. Software Routine to Enable Flash
. Writes and. Reads
B. Flash 10 Software Routines
C. Software Calibration timers
D. MS·DOS ROM Version Overview
Trademarks:

• IBM, IBM P,C are trademarks of international Business Machines corporation
• MS, MS·OOS, are trademarks of Microsoft Corporation
• Tandy Deskmate is a registered trademark of Tandy Corporation
• Lotus 123 is a registered trademark of Lotus Corporation
• Wordstar is a registered trademark of Wordstar Corporation
• Digital Research is a trademark of Oigital Research, Inc.
Intel, ETOX II are trademarks of Intel Corporation
Patents are still pending on Intel's ETOX memory

6-250

AP-341

1.0 INTRODUCTION

As PC computing platforms increase in complexity, so does the associated BIOS code. Sophisticated hardware and BIOS software increase the potential for revisions. Time-to-market goals
require faster completion of designs from conception to production, leaving less time for test and
debug of PC platforms and greater potential for hardware/software bugs. Once a computer is out
the door, code revisions are far more difficult and costly. Code revisions with EPROM require
either a service call or'sending EPROMs to the end user, assuming nothing else goes wrong in ,
the process.
Flash memory offers the same nonvolatile storage as EPROM, but additionally offers in-system
write capability. Using Intel's flash memory for BIOS storage, code updates are done quicKly in
the factory during test and debug, while allowing cost-effective field updates to end users via
floppy disks.
This application-note describes various methods of implementing a flash BIOS. Design targets
are both laptop and desktop systems. The primary emphasis is on application of flash for BIOS
and ROM executable software applications. Detailed information on flash memory is covered in
other references, including data sheets and other application notes.,
<

2.0 FLASH MEMORY

This section provides a brief overview of Intel's flash memory. It covers the following:
• Flash memory's EPROM roots
• Stop Timers
• Pin-outs and physical layout for different packages
• Vpp specifications
Major benefits of flash memory are in-system write, SRAM-like command interface (for programming and erasure), fixed Vee and Vpp supplies, Vee and V pp lockout protection, and stop
timers for erase and program operations.
2.1 EPROM Roots; Review of Flash Process vs. EPROM & EEPROM

Intel's ETOX™ II (EPROM Tunnel OXide) flash memory is a single-transistor cell providing
nonvolatile storage like EPROM, with electrical erase similar EEPROM. Reprogramming flash
memory entails electrically erasing all data bits in parallel, then randomly programming data
into any byte in the array: The programming operation is achieved via channel hot electron
injection (CHE), just like EPROMs. Flash electrical erasure however, is accomplished through
Fowler-Nordheim (FN) tunneling. Using separate program and erase methods (CHE vs. FN
Tunneling), in different cell locations, drain vs. source, permits process optimization for high
cycling endurance - the number of complete erase and re-writes. Traditional low-density
EEPROMs tunnel through the same memory cell junction for both programming and erasure.
Because EEPROMs erase before programming each byte, these processes must occur very fast.
Therefore, voltages used to program or erase EEPROM memory cells are high (e.g. 18-30 volts).
The combination of higher voltage with programming and erasing through the same junction
contributes to EEPROM's oxide breakdown and reduced cycling capability.
6-251

AP·341

Intel's flash memory erasure (tunneling) voltage is below the critical oxide breakdown voltage.
By using block erasure instead of EEPROM's byte erasure, erase times are relaxed, reducing
tunneling voltages. Programming Intel's flash memory is non-destructive to the floating gate
oxide compared to EEPROM's use of tunneling for programming. These features for erase and
programming provide Intel's flash memory with the highest endurance (typically over lOOK
cycles) compared to that of traditional EEPROM cycling. Furthermore, flash memory exh.ibits
lower failure rates at any given cycle count.

2.2 Stop Timers ,
Programming and erasing Intel flash memory requires time delays of lOfJ.S and lOmS, respectively. Internal stop timers assist debugging by stopping individual programming or erase
timeouts, preventing violations of specified programming or erase timing requirements. For
instance, when single-stepping through code, you accidentally leave the device in erase mode
while you take your coffee break. The erase timeout requirement would certainly be violated,
but since stop t,imers are present the" erase operation is halted internally, providing you with a
functional flash device when you return.
2.3 Flash Memory Pinouts and Ph"ysical Layout

Intel's flash memory is offered in three standard 32-pin packages: Plastic Dual In-line Package
(PDIP), Plastic Leaded Chip Carrier (PLCC) , and Thin Small Outline Package (TSOP). 256Kb
to 2Mb densities are available in PDIP and PLCC, 'while 1Mb and 2Mb densities also come in
TSOP versions. See figures 1, 2, and 3 for pinout details.

6-252

•

l®

Intel

AP-341

2M (256K x 8)

-.-..
-------..
---..
--

....-..

----..
-

/;;
A'6

.A,s

1M (128K x 8)
512K (64K x 8)
256K (32K x 8)

\.J

~~~ --

Vee

Vpp L

NC L

tJ NC

A'2 L

A7 L

A6 L

As L
~

o A'4

....

-...
A17

....

-.......
-.....

J A'3
JAa

P A"

A3 L

-...

A2 L

...

Ao L

J
J
J

DQo L

20 ~ DQ6

DQ'L

DQ2 L

Vss L

32-PIN PDlP
0.62" x 1.64"

~ OE
A,o
CE
DQ7

b DQs

18 ~ DQ4
TOP VIEW

b DQ3

Figure 1. PDIP Pinouts from 256Kb to 2Mb

6·253

....

-....
p

-.....
....

--...
......

AP-341

2M (256K X8)
1M (128K X 8)
512K (64K X 8)
256K (32K X 8)
4
A7

30
29

A14

A13

Alo

DQo

0
32-LEAD
PLCC
0:450" X 0.550"

TOP VIEW

DQl DQ2 'Vss

DQ3 D~ DQs DQ6

Figure 2. PLCC Pinouts from 256Kb to 2Mb

6-254

'DQ7

AP-341

2Mj2S6Kx8)
1M (128K x 8)
S12K (64K X 8)
2S6K(32K X 8)

•• • • • • • • • •I. • • • • •
,..
•
A17

I I I I I I
I I

A,.

I I I
I

A,s

I I I I I

A. A7 A12 NC NC Vpp Vee WE NC A,. A" A.

16 15 14 13 12 11

A, An
2

DDDDDDDDDDDDDDDDDDDD
-I
'-!

32 LEAD TSOP
0.31S" X 0.787"

TOP VIEW
uuuuuuu~uuuuuuuuuuuu

17 18 19 20 21

A, A, A,

I I
I I

22 23

24 25 26 27 28 29 30 31

Ao Do 0, 0, V•• 0, D.

I I
I I

I i
I I

I I I
I I I

Os D.

I I I
I I I

I
I

CE Al0 OE

I I
I I

I
I

,,,, ,,,,, ,,,,,,,
Figure 3. TSOP Pinouts from 2S6Kb to 2Mb

Plastic Dual In-line Package
•. .
•
PDIPs with sockets provide an excellent way to prototype and debug new designs. IMbit and
2Mbit flash memories are pin-compatible with the corresponding EPROMS. Lower-density
EPROM can be placed pin-for-pin in the lower 28 pins of a 32-pin flash memory socket. Siillply
jumper Vcc to pin 30 of the higher density socket.

Plastic Leaded Chip Carrier
Most system designs today require surface mount technology (SMT) due to shrinking board real
estate and portable form factors. PLCe is one SMT component that uses as little as 35% of the
overall board space compared to PDIP. Its small size is attributed to the center-to-center lead
spacing of 50 mils versus 100 mils as well as its four-sided pinout. The J-Iead design allows the
PLee to be directly soldered to the circuit board. Most SMT manufacturing equipment can
easily handle the PLeC's 50-mil lead pitch.
Recently, AMP introduced a SMT socket for PLees (PIN 821977-1) that has an identical footprint for 32-pin devices. This socket can be used in place of directly soldering a PLee for
prototype build and code testing. Once the reprogramming code is tested and debugged, flash
PLees can then be surface-mounted without secketing during production-runs.
6-255

Ap·341

Thin Small Outline Package
TSOP is the package of choice for hand-held equipment or palmtop/laptop computers. These
compact systems require minimal height and area for all components, for which TSOP excels.
TSOP Ileight measures 1.2mm versus 3.5mm for PLCC. TSOP an~a is 8mm x 20mm compared
to PLCC's 11.43mm x 13.97mm. Therefore, TSOP has significantly less total volume:
TSOP= 172.8mm3 , while PLCC=656.3mm3, and DIP= 1872.3mm3 • State-of-the-art centerto-center terminal spacing of 20 mils yields a smaller package with narrower conductor traces
than PLCC or PDIP. Location of pins on. both ends of the package allow traces for TSOP to be
routed underneath the chip, reducing board layers. TSOP is available in standard and reverse pin
configurations (see figure 4) allowing components to be laid out end-to-end and side-to-side (in
serpentine fashion) for highest board density (see figure 5). Note how pins 32-17 on the standard
pinout match pins 1-15 on the reverse pinout, and how pins 1-16 on the standard pinout match
pins 32-17 on the reverse pinouts.

A13
1\14

4
5

07
D6

"17

-?c"

7
8

29
28
27
26
25
24
23
22
21
20
19
18

DE
A10

______________________________________________

;\7
3

07
DB

05
D4

REVERSE PINOUT

vss
D2
01

DO
AO
A1
A2
A3

F28F020

6-256

AD
A1
A2
A3

32
31
3D
29
28
27

"11
A9
A8
A13
A14
A17

28
25
24

23
22
21
2D
19

A16
A15
A12
A7
A8
A5
A:4

Figure 4. TSOP Standard and Reversed Pinouts

AS
A4

03
VSS
02
01

,E28F020

A18
A15
A12
A7

os
D4

VPP

A10

vee

STANDARD PINOUT

32
31

A11
A9
A8

vee
vpp

AP-341

F2BF020

0(:0::18(:3

I
~

?--C

s---c

II-

F28F020

E28F020

i
0
""===

-==

I
ilL

0(:0::18(:3

F2BF020

c ~

'--

/\. ;i-----<
0--

lof-

t--

F28F020

E2BF020

~
Figure 5. TSOP Serpentine Layout

2.4 V pp Specifications

Fixed Vpp and Vee
Flash memories, like EPROMs, require a 12V programming power supply. Unlike EPROMs,
however, the Vpp for flash memory is a fixed, standard level. When combined with the Command
Register erase/write control, Intel flash memories use a simple, SRAM-like hardware interface
with standard microprocessor timing.
.
Intel's flash memory V pp specification is 12.0V ± O.6V (5%), compatible with most off-theshelf system power supplies. The IBM PC* technical reference manual specifies the 12V power
supply at 12.0V, +5% and -4%. Additionally, some hard and floppy drives require 12V ±
5%. Therefore, most PC power supplies have 12V supplies with ± 5% or better tolerance. Possible
exceptions to this are laptop and/or palmtop PCs. Some of these require 5-volt-only designs, in
which case 5 volts is charge-pumped to 12V.
It is essential to use the specified Vpp when programming and erasing flash; Once the commands
to program, erase or verify are issued, the device internally derives the required voltage references

6-257

AP-341

from the V pp supply. Therefore, an improper Vpp level degrades the performance of the part.
The hardware design section discusses various methods of Vpp generation if your 12 volt power
supply does hot meet the proper tolerances or 12 volts is not available.

vcc and Vpp Lockout Protection
Intel flash memory provides additional protection for designs that tie 12 volts directly to the
device. Since the 12 volt supply is less capacitively loaded than the 5 volt supply, the 12 volt
power supply reaches full value faster during power-on. If command register lockout protection
was not provided,a small, finite possibility exists that inadvertent writes may occur during
power-on. For this case, Intel flash memory affords command register lockout protection when
Vee is below 2.5 volts and Vpp is below 6.5 volts, preventing any writes to flash memory from
occurring. Since CMOS logic is valid at 2.0 volts, a 0.5 volt margin of protection exists, providing
extra time for control signals to settle before the Command Register is activated. Once Vc~
reaches 2.5 volts and V pp is greater than 6.5 volts, the Command Register begins processing
valid commands. At this point, the system is responsible for write filtering.
3.0 HARDWARE DESIGN CONSIDERATIONS
The system level hardware requirements for implementing BIOS and application storage in
flash are:
• Write Enable available to all of the flash memory
• 12V routed to flash location or generated on-board
• CMOS control-signal interface, or WE gated by a power-good signal
• Data buffer or transceiver that works in both write and read directions
• Space in memory map allocated for each application's size
The VIP 8000 (Vadem, Intel, Phoenix) laptop demo board was chosen as a flash BIOS system
design example because it demonstrates the modification of an existing laptop chipset. The VIP
8000 chipset consists of an 80386SX™ processor, an 82344 bus controller, an 82343 system
controller, and a Vadem power management chip. The bus controller and system controller
contain configuration registers that must be set for flash BIOS updates. Some particulars relating
to this chipset are:
1) Configuration register RAMMAP bit 7" when changed to a 0 will not generate a ROMCS,
but accesses to FOOOO-FFFFF still does.
2) The EAXS and FAXS registers must be set to OOH in order for ROMCS to be generated.
3) If any of the 4 EMS Page registers in the EOOOO-EFFFF range are active, they create a 16K
window with no ROMCS.
4) The XD (82343) 8-bit data bus transceiver is prevented (internal logic) from writing data out
to the BIOS address range .
. 5) ROMCS and MEMWR is not a valid condition, so flash CE must be generated externally.
6-258

AP-341

Other chipsets may have similar restrictions. Figure 6 is a block diagram for a flash BIOS
implementation on the VIP 8000 chipset, which will be referenced throughout the rest of the
hardware and software sections of this application note.

VIP 8000SX Flash BIOS
System Block Diagram
... -.

ra.",ntrnl ,..-,- - - - ,
,..;-~

Line
Bus

Addr
23-1

WIO
80386SX

W/R

Data
15-0

82344
ISABUS
Controller

SD7·SD~

Bus

i--f

I
I

12V

-r.-

Write
Buffer

GPIIO

RESET~

12V Vpp
Switch

MEMR

SA16..IJ

.Vpp

....

SA19·17

82343
SYSTEM
Controller

I
CE
Decode

OECE

Flash
BIOS
28F010

..
~

XD7·XDO Bus

Figure 6. VIP8000 Flash BIOS Block Diagram

A write buffer is used on the SD bus since data for writes is not allowed on the XD bus in BIOS
memory address locations. Data for reads is passed on the XD bus using the 82343 internal data
buffer. The 82344 provides internally-latched system address lines to address the 28FOlO. The
flash write enable signal is generated using the 386SX™ write signal in combination with the
CE signal from the decoder. The 82344 MEMRD signal controls output enable while the decoder
controls chip enable. The Vpp switch block controls the application of 12 volts to flash memory
and is discussed in section 3.2.3.

6·259

AP-341

3.1 Modifying an Existing Motherboard
If you are modifying an existing motherboard design to accommodate a flash BIOS, there are a
few things you should consider. First, check the logic design to determine if WE is decoded out
to the BIOS EPROM location. Typical motherboard logic designs do not allow writes to the
EPROM locations and treat EPROM writes as invalid (e.g. ROMCS not generated with
MEMWR). This is overcome by generating the BIOS location's WE externally by either adding
the necessary discrete logic or~ding a 3-to-8 decoder (see figure 7 for an example). In either
case, tap into the 386SX™ MIlO and WIR control lines and configure the decoder to provide a
logic low for the { M "OR" W "OR" BIOS address} condition. Secondly, check to see if the
BIOS code transceiver or buffer for the EPROM location works in both directions. The transceiver
may need a special BIOS call to unlock it in the "write" direction, or you may have to reprogram
the logic for that portion of your board. If your chipset data buffer works only in one direction,
a transceiver and direction logic must be added to the CPU bus to pass data to and from flash
memory.

Discret.e Flash WE Solution
NAND

FLASHWR
FLASHCE

Decoder Flash WE Solution

74 x 138
A17

FLASHWR

FLASHCE

Vee

Figure 7. Discrete and single-chip decoder WE solutions

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AP-341

3.2 Vpp Generation
For flash BIOS designs, the 12V Vpp can be provided by:
I) Using existing 12V supply from PC Power Supply;
2) Generating 12V using a charge pump or DC-DC converter from the 5V supply.
Flash typically requires only 10 rnA for program or erase (30 rnA max); otherwise only 100
.
, IJ.A is drawn in standby mode.
3.2.1 USING SYSTEM 12V

UIHt::(;TLY

As stated earlier, the IBM PC technical reference manual specifies the 12V supply as + 5% and
- 4%, which meets the Intel flash memory Vpp requirement. If your power supply meets this
condition and has CMOS logic, 12V from the PC power supply can be tied directly to flash
memory, elimin~ting the need to add extra circuitry for Vpp generation. This is possible due to
Vee and Vpp lockout protection offered in Intel's flash memory. However, it is recommended
that you switch V pp if writes to the BIOS location occur (e.g. loading the GDT from BIOS
location) during boot loading or normal operations.
3.2.2 PUMPING 5V TO 12V

If your system does not provide 12V or does not meet flash memory specifications, several 5-to-

12V converters are available, including surface-mount versions. AP-316 lists several Vpp solutions
which offer on/off control of V pp and provide a steady Vpp rise and little overshoot.
Figure 8 shows one example of one charge pump design. On power-up, system reset or when
Vee is below 4.SV, V pp is forced off..It is enabled (or disabled) by writing to the VPPEN 110
port address. On/off capability is essential for battery-operated equipment and eliminates the
need for WE filtering. The VPPEN signal "OR'ed" with the system memory write (MEMWR)
functions as the clock signal for the 74FC74 D-flip-flop. The D-input is latched when MEMWR
goes high. Writing a one or a zero turns V pp on or off, respectively. Linear Technology's LTl0n,
a switching regulator, is used as a SV to 12V charge pump. The 1O.7K and 1.24K resistors are
used to establish the correct reference voltage to obtain 12 volts. The 100 uF capacitor at the
output is used to handle up to 200 rnA. For a single- or double-chip BIOS design, this capacitor
value can be halved or even quartered to allow selection of a SMT capacitor value, since ~he
maximum Ipp current per device is only 30ma (lOrna typical). Sufficient time should be aflowed
when switching Vpp on, allowing the charge pump to level out and enabling the command register
to receive commands(!). The diode, MUR120, keeps the inductor from absorbing current from
the charged output capacitor. The 5.6 volt zener diode ensures that when V pp is less then 5.6
volts, the Vpp output is held at zero volts(2).
Notes:
1. See section on Software Timing Delays for Vpp-on times.
2. This is optional if the power draw with Vpp @ 5 volts or less is tolerable.

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Ap·341

Read to determine
.-------{
Vpp status

MUR120

74F125
Vee

5.6V

RESET
(V.. OFF ON POWER·UP)

.GND

r---------------RESET

(from system bus)

Figure 8. Vpp Generation with WE protection.

Controlling Vpp provides an additional benefit of system security. Beyond this, you can design
for.even higher security levels. The first level could be the design of a simple software password
routine that would only turn on Vpp when a correct password is given. Alternatively, you can
provide a jumper to allow 12V to the part for a BIOS update and then return it when reprogramming is finished. The system should check this pin to see if the jumper was left in the programming
position and remind the user to move it. Unless Vpp is at 12 volts, the flash memory contents
cannot be changed and acts just like ROM.
Disabling Vpp until voltages have stabilized provides additional power-up protection. The Motorola component, MC34064, is an under-voltage sensing circuit that begins functioning when
Vee is above 1 volt. Between 1 and 4.6 volts, the RESET output is active. The RESET output
(or a system RESET) clears the 74FC74, keeping Vpp off when Vee is less than 4.6 volts.
Alternatively, if you use CMOS logic, you could make use of Intel's flash memory Vpp and Vee
lockout function. While Vee is below 2.5 volts and Vpp is below 6.5 volts, the Command Register
is locked out. Since CMOS control logic is active at 2.0 volts, a 0.5 volt safety margin exists for
control logic to settle down before the part becomes active. For designs that do not use CMOS
logic (i.e. control logic active at 2.0V), gate WE with the power supply's "Power Good" signal
or the MC34064's RESET output (Figure 8).
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AP-341

3.2.3 USING A MOSFET SWITCH

For laptops/palmtops, an always-active 12V may not provide acceptable power management.
Additionally, there may not be enough space for a charge pump, but 12V is provided - VIP8000
for example. For these systems, a MOSFET switch will work adequately. Several DC switches
exist, but there are a few issues to consider in your selection. The "ON" resistance must be very
small for the Vpp voltage to stay within flash memory specifications. The system 12V power
supply must be specified to a tighter range to allow for the voltage drop through the switch. An
i/O lillt (V pp i;iiabk) iIiU:;t be u!lc::::!ted to tur~ the switch OJ!' flnct off. To handle "warm RESETS"
the V pp enable must be gated with the system RESET line. The Motorola MTD3055E is one
example of a surface-mount switch with low drain-source resistance. Assuming a 12V + 5% and
-4% supply:
Ipp= 30mA (worst case)
R Ds =0.150
aV.witch Drop = 30mA x 0.150 = 0.0045 V,«

5% ofVpp= O.6V.

Figure 9 shows a schematic of a Vpp switch design.

Vpp Switch Schematic
12V

R1=10K
GPI/O

Vpp out

T
Figure 9. Vpp Switch using MTD3055E

6-263

AP-341

3.3 Ideas for Using Extra Adaptor Space
Laptop systems may have extra adaptor space available since there typically isn't much room for
add-in boards. The extra space can hold ROM executable programs (e.g .. Tandy* Deskmate) like
Lotus 123*, Wordstar*, etc. Using Intel's flash TSOPs, a small application cache can reduce a
laptop's disk access and increase battery life. Additionally, Microsoft's ROM-Executable DOS
Version 3.22* can be placed anywhere in adaptor space. "MS-DOS ROM Version 3.22" requires
64KB of adaptor space today (this may change on subsequent revisions).
One location for MS-DOS ROM executable 3.22 is directly under the BIOS (see figure 10).
Today's typical BIOS consumes 64KB; consequently, both the BIOS and MS-DOS ROM executable can reside in a single 28FOlO (128 K-bytes), yielding reduced chip count. However, if
power management code is added to the BIOS (e.g. VIP 8000), system BIOS code could grow
. to 80KB or more. Therefore, designs that include both power management and MS-DOS ROM
executable should consider using the larger 28F020 (256 K-bytes) flash device. This leaves extra
space for BIOS and DOS in ROM to grow in the design, while providing additional storage for
.
the video BIOS.

1Mbyte DOS Map
FFFFFh , - - - - - - - - - - , . . . .

~ 16 BYTE JUMP VECTOR

64K

BIOS Location

64K

Additional BIOS Space
MS-DOS ROM 3.22

232K

Adapter Space

640K

BIOS CODE MAP

32K

8K IBM BIOS Compatibility Area
IBM Standard BIOS
(Minimal BIOS for Discrete AT,
No Chipsets)

32K

Extended BIOS Area
(Chipsets Support, Power Mgmt.,
EMS, Extended Setup Routines)

32K

~elocated VGA Drivers

User Area

OOOOh
SCSI Drivers
128K

Figure 10. DOS Memory Map

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AP-341

3.4 BIOS Boot Code Requirements
A key flash memory benefit is soldering it directly onto a circuit board, eliminating sockets for
production runs. A concern some designers might have when implementing a SMT flash BIOS
is: what to do in the unlikely event that the BIOS update is incomplete (e.g. power failure during
update)? One manufacturer looked at the probability of something else failing in the system
versus an incomplete BIOS update. Their analysis showed a far higher probability of other system
hardware failures (typically the hard disk or power supply) verses the probability of an incomplete
BIOS update. Consider that a BIOS update for two 28F512 's only takes 7 seconds'" - inciuding
the loading of MS-DOS ROM executable. The chances are very slim - (# of power outages/
year * 7seconds / 31.5 x \06seconds/year) for an incomplete update to occur, once th,e update
code is tested and verified. However unlikely BIOS updates may be, you may choose to provide
special protection against power loss during BIOS updates. The following section discusses three
methods of implementing designs that can handle the incomplete update scenarios.

3.4.1 SOCKETING A FLASH-ONLY DESIGN

Sockets, both DIP and PLCC, provide update protection by allowing the removal of an incompletely updated flash part. PLCC sockets are no higher than the PLCC itself and just 2mm wider
on each side. If an incomplete update occurs', the socketed parts can be removed and reprogrammed locally by the OEM. Another benefit for flash-only designs is that no changes to the
BIOS code are needed, just add your standard BIOS code in file form for use by the update
utility software.
One manufacturer who uses a socketed flash BIOS design stated that even if a few updates were
unsuccessful, all the other successful updates on other systems would easily cover the cost of the
few updates that might not succeed. This scenario is still-cost effective compared to updating
all machines with EPROMs or having users update machines with EPROMs.

3.4.2 SMALL EPROM FOR BOOT RECOVERY, FLASH THE REST

Adding a small 8KB boot EPROM, in addition to flash, provides maximum security for incomplete BIOS updates. The EPROM could be placed above or below the flash memory in the system
address map. The next two s~ctions discuss each option. Both methodologies require some
external logic and additions to the BIOS code.

BKB Boot at TOP (see figure 11)
This scenario places the processor jump vector, BIOS check-sum and initialization code, and
the basic system start-up code (if an invalid BIOS is detected), within a small 8KB EPROM.
The regular 64KB BIOS code (including the jump vector) is placed in flash starting from the
top (lFFFFH). This positions all the regular BIOS code 8K below where the system expects it.
At boot time the processor jumps to the EPROM and starts setting the system up. It also checks
the BIOS code in flash. After the flash BIOS is determined to be valid, system RAM is checked,
then the BIOS code is copied into shadow RAM. The system finishes boot and is ready to use.
Notes:
1. Demonstrated on Intel's 386'·, 16MHz, 301Z flash BIOS demo

6-265

Ap·341

When a BIOS check determines an invalid BIOS, the system RAM and floppy drive (or possibly
" a modem) are initialized With the boot recovery code located in the 8KB EPROM. Next, a request
to install the BIOS update floppy disk is written to the screen while the floppy driver routine
polls the drive until a floppy is loaded. A search on the floppy is performed for the file(1) with
the correct BIOS file name. Once the file is found, the update code is loaded to RAM and the
update utility proceeds to erase and reprogram flash with the loaded BIOS file.

8KB Boot EPROM
~16BYTEJUMPVECTOR

aKB

8KB BIOS Boot Recovery Block

28F010 128KB Flash
32KB

Standard BIOS
(Minimal BIOS for Discrete AT,
No Chipsets)
32KB

Extended BIOS Area
(Chipsets Support, Power Mgmt.,
EMS, Extended Setup Routines)

72KB

32KB

Relocated VGA Drivers

SCSI Drivers

136KB

Flgure"11. Top EPROM Boot/Flash BIOS Code Combination

Some systems require capability to turn shadowing off and directly execute BIOS code. Since
the BIOS code is shifted off by 8KB for the Boot EPROM, an address shifter is needed to allow
direct execution of BIOS code. Figure 12 shows an EPLD address shifter with a SHIFT8K input.
Once the signal to direct execute is given, the EPLD shifts all address requests by 8KB to the
flash part and generates the proper chip select.
Note:
Alternatively, the BIOS recovery code can contain specific, non-DOS, sector/track information pertaining to
the location of the new BIOS update file. Thus, the file is not readable to basic DOS users and is protected.

6-266

AP-341

Addr 15
Addr 16
Addr 17

EPLD
8K Address

YAddr 15

Shifter-

"11,.-1.....1_
I""''-'UI

85C220

, ....
'"''''

YAddr 17

Addr 18

YAddr 18

MEMWR

ROMeE

MEMRD

FLASHCE

SHIFTBK

Figure 12. 8KB Address Shifter

8KB Boot at Bottom (see figure 13)
In this scenario, the 8KB EPROM with boot recovery code resides below flash memory in the
system address map. The regular 64KB BIOS code is stored starting from the top of flash memory
starting. As long as updates are successful, no changes are needed for the system to freely shadow
or direct-execute the BIOS code. If an update is incomplete, the system may boot partially or
won't boot at all. The user would then move a jumper or an external switch, which places the
8KB boot EPROM at the top of the 1MB system memory map. When the processor reboots, it
jumps to the EPROM and begins the BIOS recovery process just like the previous top boot
solution. Once the BIOS update is finished, remind the user to move the jumper back, moving
the EPROM below flash. Until this is done, the system will keep trying to run the update utility.

Since standard BIOS code does not support boot recovery, your BIOS software engineers must
design the boot recovery code for the 8KB EPROM. Alternatively, your BIOS vendor can be
contracted to develop the code. The rest of the BIOS code located in flash memory stays the
same.

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AP-341

28F010 128KB Flash
~ 16 BYTE JU.MP VECTOR

32KB

Standard BIOS
(Minimal BIOS for Discrete AT,
No Chipsets)
Extended BIOS Area
(Chipsets Support, Power Mgmt.,
EMS, Extended Setup Routines)

32KB
64KB

32KB

Relocated VGA Drivers

SCSI Drivers

32KB
128KB

8KB Boot EPROM
~

16 BYTE JUMP VECTOR

8KB , - - - , . - - - - - - - - - - - ,

8KB BIOS Boot Recovery Block
_____

1.3~KJJ _

-"-_ _ _ _ _ _ _ _ _ _ _ _-'

Figure 13. Bottom Boot EPROM/Flash BIOS Combination

3.4.3 HALF EPROM, HALF FLASH

Another alternative is to put half the BIOS code in EPROM and half in flash memory . One
positive is that the system would have enough EPROM to reboot itself but still have some flash
memory for partial code updates. There are a few negatives to this solution, however. One is
that a direct-execute xl6 system would require 4 chips, actually increasing chip count. Another
is that only half of the BIOS code could be updated.
.

3.5 In-System Write vs. On-Board Programming
When devices are soldered directly to a printed circuit board, one of two sources control flash
memory reprogramming: I) the system's own processor, or 2) a PROM programmer connected
to the board. These options are called In-System Write (ISW) and On-Board Programming (OBP),
respectively. Their respective benefits are discussed in detail in AP-316.
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AP-341

With ISW, the system drives the reprogramming process and generates V pp locally. A good
design practice for ISW-type designs is to socket the first few flash BIOS prototypes. SMT-only
designs can also socket using PLCC SMT sockets. Socketing enables the system designer to
easily work out any bugs with in-system flash reprogramming by allowing the removal of a flash
part for external reprogramming in a prom programmer. Once ISW reprogramming is fully
debugged, pre-programmed flash parts can be soldered directly to the circuit board without a
socket. All flash memory components are exposed to a data-retention bake testing and checked
for any data loss before shipping. It is extremely unlikely that data in a production flash device
can be corrupted from heat by a production-run SOldering applicarion.
OBP uses a PROM programmer to supply Vpp and control the programming process. Certain
design considerations must be evaluated prior to laying out the design. Some manufacturers using
TSOP may also want to remove a handling step from the manufacturing process by providing
the capability to program flash for the first time after being soldered directly onto the circuit
board. OBP can accomplish this if the design is first laid out correctly to support OBP.
NOTE: See AP-316 appendix A for OBP design considerations.

4.0 SOFTWARE DESIGN CONSIDERATIONS
Intel's flash memory provides a cost-effective, updatable, nonvolatile code storage medium. The
reliability and operation of the device is based on the correct use of specified erasure and
programming algorithms. To assist debug and prototyping, Intel's flash memory features stop
timers, which terminate a single erase or programming operation at the maximum spec allowed
by the silicon. However, please note that the stop timers on the 28F256A, 28F512, 28FOI0,
or 28F020 do not provide fully automated erase or programming. More detail on this feature
is covered in each part's respective data sheet.
Intel offers standard software drivers to assist software engineers implementing flash memory
reprogramming for update utilities. The software is tailored around each CPU family (i.e., x86,
51, 196, and 960) and requires modification of the timings to your specific application. For
example, you supply the memory width (8-, 16-, or 32-bit), system timing, and a subroutine for
control of Vpp. PC-specific timers are discussed in this application note. If you use another CPU
from Intel, call your FAE who has access to the drivers or call the Intel Embedded Controller
Operation (ECO) Bulletin Board System (BBS). Look under the flash memory section for drivers.
You'll find 51, 186, 196, and 960 drivers in archived form.
Note: Please contact your sales office for details.

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AP-341

If you prefer to implement the flash memory algorithms yourself, flow-chart outlines appear in
the flash re-programming section.
Covered in this section are the major software steps for a flash BIOS update utility:
• Update software for a modified system
• Pseudo-Code overview
• Initializing the system
• Code loader routine
• Flash re-programming
• Timing calibration options
The software code patches used in this example are specific to a "flash-only" hardware design
for a demo flash BIOS add-in board. Modifications for flash writing and reading on the VIP8000
must still be made for your design. Other hardware/software designs can easily build upon the
concepts and code patches discussed here. For a more detailed source listing, call your FAE or'
the ECO BBS.

4.1 Update Software for a Modified System
Our design example assumes BIOS shadowing for BIOS code execution while allowing BIOS
writes to, the flash socket. Many systems provide a port by which BIOS. writes and reads are
enabled by toggling the port bit. Some systems may not allow BIOS reads from RAM while
performing BIOS writes to the flash socket, or vice versa. The reasons may be simple - there
is no shadow RAM in the system (8088 or 8086 systems) - or as complicated as system logic
treating it as an invalid operation. In these cases, perform all your required BIOS calls before
you erase and program the flash memory. But keep in mind, to update the user on the progress
of flash programming and indicate when programming is finished, you should add some basic
screen BIOS routines to your update utility.

4.2 Pseudo-Code Overview
The following pseudo-code for an update utility provides a brief description of the process of
updating a BIOS in-situ. It is based on an Intel BIOS update demo and must be modified for
your particular chipset and hardware environment. The code for the BIOS demo was initially
developed by Phoenix Technologies* and later modified by a consultant for new flash devices.

Pseudocode for Flash Update Routine
Initialize system (calibrate timers, set up user screen, check battery power, check device ID)
Get BIOS file (from floppy or modem)
If file not present,
send error message to insert BIOS update floppy, or press esc to exit
6-270'

Ap·341

If extra space available, prompt user with space size and binary application file option

If user indicates yes, prompt for file and load
If file invalid,

Prompt for file or exit
RIse save what was in the extra space to a buffer
Inform user what is about to happen, with option to continue or exit
If user continues, inform them to not turn off the power
Disable all interrupts
Erase flash memory
Write file[s] into flash memory
Indicate to user flash reprogramming is over .
Reboot the system

4.3 Initializing the System

Checking Power
If your application is a laptop or palmtop computer, first check the battery to make sure there is
enough power to do the update. If not, inform the user to re-charge the system before continuing
the update and exit the update program. This ensures that the system won't stop in the middle
of an update. Next, initialize access to flash for reads and writes, then try reading the device ID
through the command register. Checking the device ID before programming or erasing helps
determine if V pp, writes and reads work correctly and that the flash memory in the system
matches your code before starting to reprogram the part.

Device ID Check and Table
Since varieties of flash BIOS components (256Kb - 2Mb) and configurations (x8, x16) are
possible, a device-unspecific update utility is preferred over a device-specific utility. Intel's flash
memories contain a unique device ID for each density and/or device configuration. To read the
device ID, turn on Vpp (if it is not directly connected), wait the appropriate on-delay time, then
write a 90H anywhere within memory address range of the part you are checking. Next execute
two read cycles in succession from the flash device, first from address OOOOH, second from
address OOOIH-of the flash memory. The data returned on the first read cycle 89H, the manufacturing code, while the second read cycle returns the device ID code (see the Device ID Table
below). If the part does not read correctly, then exit the update program.
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Device Type

Device ID

28F256 PIC2 Sb62

BIH.

28F256A

B9H

28F512

B8H

28FOIO

B4H

28F020

BOH

Note: During the initialization, you can also perform a scan of the adaptor space to ascertain if
there is more flash in the system. This will help determine if there is any flash applications
present that may need to be updated. See code example in appendix B "GeLFlash_ID."

4.4 Code Loader Routine
The routine used for the BIOS demo prompts the user for file type (Hex or Binary) and then the
file name. System OEMs may want to encode the BIOS file name into the generic loader utility
".COM" or ".EXE" file. This allows automatic reading of the new BIOS file into a program
buffer, bypassing the user prompt. Otherwise, you may want to duplicate the process listed here ..
First, the file loader portion of the utility checks for available space left in flash memory,
assuming the size of the BIOS file is known. Since the available flash memory check is accomplished in the initialization section (under device ID check), sizing information is already known.
Extra space within a chip is determined by subtracting out the BIOS file size from the total flash
memory space found. This extra space can easily be used for MS DOS ROM-executable (or
similar OS), or other ROM-executable software packages that can fit in whatever space is left
over by the BIOS.
Once the files are loaded, inform the user what is about to be done and provide the option to
exit if they wish. If they continue, give a warning message telling the user to not turn off the
power during the BIOS update procedure. Next, disable all interrupts to ensure an uninterrupted
reprogramming operation.

4.5

Fla~h

Reprogramming Routines

4.5.1 QUICK ERASE'· ALGORITHM

Flash memories chip-erase all bits in the array in parallel. The erase time depends on the V pp
voltage level (l1.4V-12.6V), temperature and the number of erase/write cycles on the part. See
individual device data sheets for specific parametric influences on Iieprogramming times.
Please note that all flash memory locations must be programmed to OOH before erasing the device.
This provides equal charge throughout the array, insuring uniform and reliable erasure.
The algorithm has three different timing delays (Figure 14). The first is an assumed delay when
Vpp first turns on. Systems that direct-wire 12 volts need not worry about this delay. The other
two delays are the Erase Pulse (IOmS) and Erase Verify Pulse (6,.,..S). See section "Timing
Calibration" for a discussion of how to generate time delays for PC systems.
4.5.2 QUICK-PULSE'· PROGRAMMING ALGORITHM

Flash memories program with a modified version of the Quick-Pulse Programming ™ algorithm
used forU.V. EPROMs (Figure 15). Programming is accomplished via a closed loop algorithm
consisting of IO,.,..S program pulses followed by the 6,.,..S program verify. pulse. See section
"Timing Calibration" for a discussion of how to generate time delays for PC systems.
6-272

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BUS
OPERATION COMMAND

Standby

COMMENTS

Walt for VPP ramp
to VPPH (= 12.0V) [1]
Use Quick·Pulse
Programmlng™ (Fig. 4)

Initialize Addresses,
Erase Pulse Width,
and Pulse Count

Write

Set·up
Erase

Data =20H

Write

Erase

Data = 20H
Duration of Erase
Operation (tWHWH2)

Standby
Write

Erase
Verify [2]

Standby

Addr = Byte to verify;
Data = AOH; Stops
Erase Operation [3]
tWHGL

Read

Read byte to verify
erasure

Standby

Compare output to FFH
increment pusle count

Write
Standby

Read

Data = OOH, resets the
register for read
operations.
Wait for VPP ramp
to VPPL [1]

Notes:
1. See DC Characteristics for the value of VPPH and VPPL.

3. Refer to principles of operation.

2. Erase Verify is only performed after chip·
erasure. A final read/compare
may be performed (optional) after the
register is written with the read command.

4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of
the device.

Figure 14. ETOX II Erase Algorithm

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AP-341

BUS
OPERATION COMMAND

Standby

«::CLMMENTS

Walt for Vpp ramp
to VPPH (= 12.0V) [1]
Initialize pulse-count

Write

Set-up
Program

Data = 40H

Write

Program

Valid address/data

Standby

Duration of Program
Operation (tWHWH,)
[2]

Write

Write
Program

Data = COH; Stops [3]
Program Operation

Standby

tWHGL

Read

Read byte to verify
Programming

Standby

Compare data output
to data expected

Write

Read

Standby

Data = OOH, resets the
register for read
operations.
Walt for Vpp ramp
to VPPL [1]

Notes:
1. See DC Characteristics for the value of VPPH and VPPL.

3. Refer to principles of operation.

2. Program Verify is only performed after
byte programming. A final read/compare
may be performed (optional) after the
register is written with the Read c,?mmand.

4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of
the device.

Figure 15. ETOX II Programming Algorithm

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AP-341

4.6 Timing Calibration
Intel's flash memory uses the following time delays:
• Vpp turn-on delay (for systems w/out hardwired Vpp)
• lOf.LS timeouts for program
• lOmS timeouts for erasure
• 6f.LS timeouts for program or erase verify.

Vpp-on delay
Capacitors on the V pp bus cause an RC ramp. After switching on Vpp, the delay required is
proportional to the number of flash memory devices times O.luF/device. lOOnS must pass after
Vpp reaches its final voltage threshold before the CPU writes to the command register. Systems
with hardwired V pp eliminate this delay.

Erase, Program & EraselProgram Verify time outs
By using the lOf.LS programming pulse width for program/erase verify delay (which has no
maximum value), all three timeouts are reduced to two individual timing loops, a lOf.LS loop
and mUltiple lOOf.LS loops. There are essentially two methods for PC time delays. One utilizes
the CPU and the other uses the CPU plus a standard system timer (8254) available in all PC
architectures.

4.6.1 USING THE PROCESSOR

PC platform CPUs range in performance from the 5MHz 8086 to the new 33MHz 80486. Each
processor has multiple running speeds and whether it uses a cached or non-cached IIF, so software
timings tailored around one processor will not necessarily work for another. Therefore, separate
timing routines are needed for each processor and each possible configuration. For an OEM with
a small product offering, this may be acceptable. For an OEM with a wide range of systems and
processor speeds, this becomes a software support issue. In the latter case, system timers provide
a more universal solution.

4.6.2 USING THE SYSTEM TIMERS TO SELF-CALIBRATE SOFTWARE DELAYS

System timers help make time delays more consistent across processor lines. Caching can affect
timing, so this should be turned off before starting a BIOS update. The software timer example
in Appendix C uses the 8254 system timer to calibrate the necessary software delays for flash.
First the timer is initialized to the correct mode. Second, a 100f.LS loop is checked by starting
the timer, then starting the software loop. Once the software loop is finished, check the 8254.
Adjust delay loop value accordingly. Next, the lOf.LS is checked in the same fashion as the 100f.LS
delay and adjusted. The values found are then used for program and erase time delays.
Once reprogramming flash is completed, provide a message to user letting them know and then
reboot the system.
6-275

AP-341

5.0 SUMMARY
5.1 Traditional BIOS Storage and Disadvantages

Traditional BIOS storage has been in EPROM, which offers nonvolatility and external programming capability. In earlier PCs, the BIOS code was fairly simple (relative to today's software)
and updates were infrequent, so EPROMs were an acceptable BIOS storage medium. Today's
systems are much more sophisticated with many designs supporting the Intel 386™ /486 ™ pro-'
cessors and new bus architectures like MCA™ and EISA™ for the first time. Therefore, the
potential for a change in the BIOS code is much greater and the frequency of change is likely to
increase. A system designer may use EPROMs for BIOS storage to reduce initial system (component) costs, but the long-term update cost is much more than the difference between EPROM
and flash memory components. A major manufacturer of PCs stated that a service call for a
BIOS update with EPROMs can cost upwards to $300.00 for one update at one site. EPROM
updates are also susceptible to bent leads during insertion by the technician, or more likely, the
end user. Service is becoming a key differentiator between the multitudes of PC makers. Reducing
the number of times a PC has to be opened for any reason increases customer confidence and
promotes a reliable image.
5.2 Advantages of an Updatable BIOS

Using flash memory for BIOS storage provides a flexible code storage medium that allows the
BIOS code to adapt to changing hardware and software conditions. BIOS updates in flash are
inexpensive, via a floppy disk or modem(l), and thereby remove EPROM inventories, reduce
packaging requirements, reduce total postage costs and reduce service cost for BIOS code updates
by removing the need for a technician to do the update. A company that supports multiple OEMs
can reduce version management control by using a flash BIOS and floppys for updates. An
additional benefit is that not only the BIOS, but DOS itself can be stored in the same flash
memory device.
5.3 Advantages of Adding DOS in ROM .

Once the requirements for flash BIOS are met, all the capability is also in place for adding DOS
in ROM. "Why put DOS in ROM?," one might ask. For laptop/palmtop PCs, battery longevity
is of paramount concern, followed closely by weight and increasing user RAM (640KB) space.
Extra user RAM is needed for applications that need more than the typical 570K bytes (640KB70KB) available with disk-based DOS. Digital Research Incorporated* and Microsoft both make
DOS-in-ROM products that address these needs. MS-DOS ROM-executable 3.22 for example,
reduces power and increases avaiiable·RAM. Microsoft's· ROM-executable version of DOS is a
full-function version of MS-DOS 3.2. It features instant-on and employs only 15KB of the 640KB
MS-DOS user space, leaving the rest for applications. Since MS-DOS ROM-executable 3.22
loads from adaptor space, both disk access and DOS load time are reduced. For laptops,. anything
that can reduce disk access equates to battery longevity. Laptops can reduce weight by using
DOS in ROM and replacing the floppy drive with an IC card. Adding ROM-DOS to desktops
also liberates additional user RAM for the same above reasons, but may not be beneficial on
high speed 32-bit systems.
Note:
1. Intel's fast flash memory programming allows modem updates at 19.2K baud.

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· +-;®
In'e'

Ap·341,

5.4 Advantages of Adding 1-4MB of Resident Code Storage

There is a growing need for systems to be able to provide a small suite of bundled applications.
Benefits to the user are reduced hard or floppy disk access, no power used to store the resident
code, and instant-on as there is little time wasted transferring data over a disk 110 interface,' the
code loaded to RAM with a simple memory copy function or procedure or, in some cases, code
is directly executed by the processor. Tandy Deskmate* is an example of such a system. Future
versions of Deskmate-like user interfaces could easily be made flash-updatable.
SRAM is too expensive and requires power to just store files. Furthermore, battery backup is
not a reliable means of providing nonvolatility. Intel's flash memory can provide user configurability for 1-4 M-bytes of code storage for just 2x-3x the cost of EPROMs, less than half the cost
of SRAM. Applications such as Lotus 123 ™and Wordstar™ also come in either a direct-execute
"ROM" version, or a copy-from-ROM format. Many other ROM application software packages
are in development, servicing the successful and growing needs of the laptop/palmtop computers.
Therefore, if an application can be stored or runs from ROM, it can be stored, run and additionally
updated from flash.

6-277

Appendices
A. Software Routines to Enable Flash Writes and Reads
B. Flash 10 Software Routines
C.Software Calibration Timers
D. MS-DOS ROM executable-DOS Overview

6-278

AP-341

APPENDIX A
ENABLE FLASH WRITES AND READS
bcfore--,cUlash

proc

ncar

Input: Nothing
Output:

Aii registers prcseIVcU

Function:
This routine is called during system initialiution before any
access is attempted to the flash memory parts. The usage of this
roptil!e is depcndent on the system architecture.
The known usages are:

I. System can be placed in a state where FOOO segment reads come
from ROM, and FOOO segment writes go to ROM.
In this event, the system is placed into that state here.

2. System cannot be placed in a single state where FOOO segment
reads and writes are addressed to the ROM.
If the system protects the access to the shadow register via
an I/O lock mechanism, then the I/O lock is unlocked here.
If the system will be placed in states where shadow RAM read
access is enabled (e.g. while writing ROM), then this routine
must pcrform a s~adow copy of the BIOS ROM (and if OOS is in
ROM, it must also be copied) here. .

push
push
push
push
push
p~sh

call

ax
cx
di
si
ds
es
wfibe

;In 301Z, lock pon is Kbd controller

eli
mov al, SHAOOW_UNLOCK
out
SHADOW_LOCK_PORT, al
;unlock shadow control register
call
read_rom_enbl
;set to read ROM I write RAM state
mov ax, ORlOOh'
;shadow the BIOS .
.
mov ds, ax
;This is necessary for the 30lZ
moves, ax
:becaQse shadow may have not beep
xor
si, si
;enabled, and enabling write ROM

6-279

AP-341

xor
di, di
;access in the 301Z relies on the
;presence of a shadowed BIOS.
mov cx, 8000h
movsw·
rep
;set up for possible EOOOh option
mov ax, OEOOOh
mov ds, ax
;ROM shadow
moves, ax
xor
si, si
xor
di, di
cmp ds:[si1, word ptr OAA55h
;test for option ROM
jne
unlock_done
mov cx, 8000h
;if present, then shadow it
rep
movsw
unlock_done:
sti
pop
pop
pop
pop
pop
pop
ret

es
ds
si
di
cx
ax

before;..geUlash

endp
proc

near

Input: Nothing
Output:

All registers preserved

Function:

Enable writes to the· ROM area to go through 19 the
Flash parts

push
mov
out
pop
ret

ax
al, SHADOW_ON
SHADOW_PORT, al
ax

;enable ROM writes

6-280

AP-341

proc

near

Input: Nothing
Output:

All registers preserved

Function:

Enable reads to the ROM area to go through to the
Flash parts

push
mov
out
pop
ret

ax
al, SHADOW_OFF
SHADOW_PORT, al
ax

proc

;enable ROM reads

near

Input: Nothing
Output:

All registers preserved

Function:

Raise the Vpp voltage, and wait for it

push
push
push
mov
mov
out
mov
delay_loop:
call
loop
pop
pop
pop
ret

ax
cx
dx
:Vpp control pon
dx' VPP_CONTROL
al, VPP_ON
;On value
dx, al
cx, 500
waiClOO_micro
delay_loop
dx
cx
ax

:call 100 microsecond delay

1·n+~I®
I IV

lower_vpp

AP-341

proc

near

. Input: Nothing
Output:

All registers preserved

Function:

Lower the Vpp voltage, and wait for it

push ax
pusb c:x
push dX
mov dx, VPP_CONTROL
;Vpp control port
mov 'ai, VPP_OFF
;Off value
oUt

dx, aI

mov ex, 500
delay_loop2:
can waiU()(Lmicro
loop delay_loop2
po~

pop

;ea11100 microsecond delay

ex
aX

ret

6·282

Ap·341

wfibe

proc

near

Input: Nothing
Output:

All registers preserved

Function:

Wait for the 8042 input buffer to be empty, and
then exit.

push
push
xor
jmp

ax
cx
cx, cx
wfibe_check

retry:
waicU)()_micro
call
wfibe_check:
al,64h
in
al,02h
test
loopnz
retry
ex
pop
pop ax
ret
wfibe

;wait 100 microseconds

;check input buffer full

endp

code

ends
end

code

ends
end

6-263

Ap·341

APPENDIX B,
GET FLASH 10
proc

near

Input: Nothing
Output:
cy - set if not flash installed
All other registers preserved

push ax
push bx
push cx
push dx
push si
gecflash_id
;send read flash OJ command,interpret
call
;save the Flash tytjecode .'
mov FlashType, al
cmp al, NO_FLASH
je
bad_flash
clc
jmp
bad_flash:
mov bl, ErrorAttr
;attribute of prompt
mov ex, NoFlashLen
;display File read error
;row position
mov db, NOFLASH_ROW
mov dl, NOFLASH_COL
;eolumn position
mov si, offset NoFlashMsg
pucstring
call
xor
ah, ah
Int
16h
ste
geUlash_exit:
pop
si
pop dx
pop ex
pop
bx
pop
ax
ret

6-284

geUlash_id

proc

near

Input: Nothing
Output:

al - flash memory space I ID types

Function:

Return code for Flash part types and memory
map. Possible codes specified in flash.inc

READ_ID_CMD_OLD_256 equ
~_ll)_C~_256

READ_ID_CMD_512
READ_ID_CMD_I024
MANU_CODE
ID_CODE_OLD_256
ID_CODE2_0LD_256
ID_CODE_256
ID_CODE_512
ID_CODE_I024
push
push
mov
call

equ
equ
equ
equ
equ
equ

080h
equ
090h
equ
090h
090h
089h
equ
OBlh
OB2h
OB9h
OB8h
OB4h

di
es
RmForDos, byte ptr FALSE ;default state
raise_vpp
;Set Vpp = 12 volts

;-------------------------------;Tests for 128K of flash
mov ax, OEOOOh
moves, ax
xor
di, di

;BIOS ROM segment
;EOOO:OOOO is the address to test for
;Two 512s or One 1024

;-------------------------------;512 x 2 test
;The 512 x 2 test tests the high ROM. This will prevent accidental
;mis-detection of a pair of 512K ROMs in systems that have only
;one 512K part, and memory accesses to EOOO segment are mapped into
;the FOOO segment. This also allows an independent test for two 512K
;parts that are not odd-even byte interleaved.
call
mov
call
call
mov
cmp
jne
mov

write_rom.:..enbl
;enable write of command to ROM area
es:[di+l), byte ptr READ_ID_CMD_512
word ptr DelaylORout
;wait 10 microseconds
read_rom_enbl
;enable read of results from ROM area
ai, es:[di+l)
;test at high ROM byte 0
ai, MANU_CODE
;test for manufacturers code
tescone_1024
ai, es:[di+3)
;look at High ROM byte 1 for ID

6-285

•-n+'e'I

cmp
jne
mov
mov
jmp

AP-341

ai, ID_CODE_512
;test for part ID
tescone_l024
aI,1WO_512
;Found two 512s
RmForDos, byte ptr TRUE
have~flash

;------------------------------; 1024 x 1 test
tescone_I024:
call
write_rom_enbl
;enable write of command to ROM area
mov es:[di], byte ptr READ_ID_CMD_1024
call
word ptr Delayl0Rout
;wait 10 microseconds
;enable read of results from ROM area
call reacCrom_enbl
mov ai, es:[di]
cmp ai, MANU_CODE
;test for manufacturer's code
jne
tesC64k_flash
mov ai, es:[di+2]
;Iook at offset I of chip 0
cmp ai, ID_CODE_I024 ;test for part ID
tesC64k_flash
jne
mov aI,ONE_I024
;Found one 1024
mov RmForDos, byte ptr TRUE
jmp short have_flash
;----------------~------------;Tests

tesC64k_flash:
mov ax, OFOOOh
moves, ax
xor
di, di

for 64K of flash only
;BIOS ROM segment
;FOOO:OOOO is the address to test for
;1WO 2565 or ONE 512

;-------------------------------;256 x 2 test
;The 256 x 2 test tests the high ROM. This. aIlows an independent test
;for two 256K parts that are not odd-even byte interleaved.
call write_rom_enbl
. ;enable write of command to ROM area
mov es:[di+l], byte ptr READ_ID_CMD_256
call word ptr DelaylORout
;wait 10 microseconds
call read_rom_enbl
;enable read of results from ROM area
mov ai, es:[di+l]
;test at high ROM byte 0
cmp ai, MANU_CODE
;test for manufacturers code
jne . tescone_512
mov ai, es:[di+3)
;look at High ROM byte 1 for ID
cmp ai, ID_CODE_256
;test for part ID
jne . tescone_512
mov ai, 1WO_256
;Found two 256s
jmp short have_flash

6-286

AP·341

;-------------------------------;512 x 1 test
tescone_512:
write30m_enbl
;enable write of command to ROM area
call
mov es:[diJ, byte ptr READ_ID_CMD_512
;wait 10 microseconds
call
word ptr Delay1ORout
call read_rom_enbl
;enable read of results from ROM area
mov al, es:[diJ
cmp al, MANU_CODE
;test for manufacturer's code
In!::
!e~U~'!!U~!!:L256
mov al, es:[di+1J
;look at offset 1 of chip 0
cmp al, ID_CODE_512
;test for part ID
jne
tesUwo_old_256
mov al,ONE_512
;Found one 512
jmp short have_flash
;-------------------------------;Old 256 x 2 test
tesCtwo_old_256:
call
write_rom_enbl
;enable write of command to ROM area
mov es:[diJ, byte ptr READ_ID_CMD_OLD_256
;wait 10 microseconds
call
word ptr Delay1ORout
call read_rom_enbl
;enable read of results from ROM area
mov al, es:[diJ
cmp al, MANU_CODE
;test for manufacturer's code
jne
nouwo_256
mov al, es:[di+2J
;look at offset 1 of low ROM
cmp al, ID_CODE_OLD_256
;test for part ID
je
iUwo_256
cmp al, ID_CODE2_0LD_256 ;test for 2nd possible part ID
jne
nouwo_256
is_1WO_256:
mov al, 1WO_OLD_256
;Found two 256s
jmp short have_flash
noctwo_256:
;debugging code
mov ab, al
mov al, NO_FLASH
have_flash:
call
write_rom_enbl
;enable write of command to ROM area
;Allow memory read
mov es:[diJ, byte ptr READ_MEM_CMD
call
lowecvpp
;Clear Vpp
pop es
pop di
ret
geCflash_id endp

6-287

AP-341

APPENDIX C
CALIBRATION TIMERS
,••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
,
Timer.asm - Timer utilities for flash.com
Included in this .file are:
rpcCmilli
- execute 1 millisecond delay "cx" times
waicCmilli - wait 1 milllisecond and exit
waicU)()_micro
- wait 100 microseconds and exit
waic1O_micro
- wait 10 microseconds and exit, loop version
waic1O_micro2
- wait 10 microseconds, push/mov r,m/pop/ret
waiC1O_micro3
- wait 10 microseconds, push/pop/ret
waicl0_micr04
- wait 10 microseconds, ret only
calc_spd1O . - calibrate 10 microsecond loop
calc_spdl00 - calibrate 100 microsecond loop
try_calb
- test 10 or 100 microsecond loop
beep_spkr
- beep the speaker
TRUE
FALSE

equ

Include

Flash.inc

code

equ

0
;flash utility specific equates

segment byte public 'code'
assume
cs:code

PUBLIC
rpU_milli

calc_spd1O, calc_spdl00, waiUOO_micro, waiCCmilli, beep_spier PUBLIC

TICKS
PIT_MODE equ
PlTO_CNT equ
PIT2_CNT equ
SYS_PORT_A

equ
43h
40h
42h
equ

175
;ticks in 100 microseconds
;Timer 0, Timer 2 control register
;Timer 0 count register
;Timer 2 count register
61h
;System Control Port A

PUBLIC
Delay 1ORout
DELAY_ROUT_MAX
equ
3
?,
;Routine used for delaying 10 microseconds
Delay1ORout dw
?
;Index into table of delay routines
DelayRoutNum
dw
waiclO_micro
DelayRoutTbI
dw
dw
waic1O_micro2
dw
waiCIO_micro3
dw
waiClO_micr04
?
DelayCntlO dw
?
DelayCntlOO dw
. CaibLoopSiz dw
?
6-288

AP·341

Input: cx - number of times to wait I millisecond
Output:

All registers preserved

Function:

Do nothing for a period equal to I millisecond
times the repeat count in cx.

push cx
loop_l_milli:
call
waicl_milli ;wait 1 millisecond
loop loop_l_milli
pop cx
ret

waicCmilli proc

near

Input: Nothing
Output:

All registers preserved

Function: .

Wait 1 millisecond and then exit

push cx
mov cx, 10
loop_l DO_micro:
call
waicl00_micro
loop loop_l Do_micro
pop
cx
ret

;wait 100 microseconds

6-289

Ap·341

waiCl(XUnicro

proc

near

Input: Nothing
Output:

All registers preserved

Function:

Wait 100 microseconds and then exit Uses a purely
software delay loop. The initial value of the
delay loop is stored in the variable DelayCntlOO.

push
mov
selflOO:
loop
pop
ret

ex
ex, DelayCntlOO
selfl 00
ex

waiclOO_micro

endp·
proc

near

Input: Nothing
Output:

All registers preserved

Function:

Wait 10 microseconds and then exit Uses a purely
software delay loop. The initial value of the
delay loop is stored in the variable DelayCntlO.

push
mov

ex
ex, DelayCntl0

loop

self
ex

self:

pop
ret

endp

6-290

AP-341

proc

near

Input: Nothing
Output:

All registers preserved

Function:

Wait 10 microseconds and then exit Uses only
some instructions to kill time.

push
mov
pop
ret

cx
CK,

DelayCntlO

proc

near

Input: Nothing
Output:

All registers preserved

Function:

Wait 10 microseconds and then exit Uses only
some instructions to kill time.

push
pop
ret

cx
cx

6-291

I"n+'e-I ®

calc_spdl00 proc

AP-341

near

Input: Nothing
Output:

All registers preserved

Function:

Attempt to calculate the loop count by testing
different values for the loop delay for a 100
microsecond wait routine.

push ax
push bx
push si
mov CalbLoopSiz, word ptr 10 ;10 * 100 = 1000
mov DelayCntl00, byte ptr 100 ;try 100 ruSt
mov si, offset waiCl00_micro
mov DelaylORout, si
retry_calblOO:
call
try_calb
;see what delay cnt value is returned
2350
;see if its too low
;if so increment delay value
inc_delayl00
jbe
cmp bX,2750
;see if its too high
jae
dec_delayl00
;if so decrement delay value
jmp delay 1OO_cncset
inc_delayl00:
inc
byte ptr DelayCntl00
jmp retry_calbl00
dec_delay 100:
;see if we bottomed out
cmp DelayCntlOO, byte ptr 1
je
delayl00_cncset
dec
byte ptr DelayCntl00
jmp retry_calbl00.
delayl00_cncset:
pop si
pop bx
pop ax
ret
calc_spdlOO endp

6-292

cmp

bx,

AP-341

calc_spdlO

proc

near

Input: Nothing
Output:

ax - loop count for lO microsecond delay

Function:

Attempt to calculate the loop count by testing
different values for the loop delay for a 10
Illil:lU~C(;u.lid waiL ,vULi"c.

push
push
push
mov
mov
mov
mov
retry_calb:
call
2200

ax
bx
si
CalbLoopSiz, word ptr 100
DelayCntlO, byte ptr 20
DelayRoutNum, word ptr 0
si, offset waiCIO_micro
try_calb
;see if its too low
inc_delay
bx, 2600
dec_delay
delay_cncset

;100'" 10 = 1000
;try 20 fU'St
;start with loop routine
;stan with standard routine

mov

;see what delay cnt value is returned

jbe
;if so increment delay value
;see if its too high
cmp
jae
;if so decrement delay value
jmp
inc_delay:
inc
byte ptr DelayCntlO
jmp retry_calb
dec_delay:
cmp DelayCntlO, byte ptr 1
;see if we bottomed out
je
delay_roucchg
dec
byte ptr DelayCntlO
jmp retry3alb
delay_t'Oucchg:
inc
word ptr DelayRoutNum
mov ax, DelayRoutNum
cmp ax,DELA Y_ROUT_MAX
ja
delay_cncset
shl
ax, 1
;conven to word index
mov si, offset DelayRoutTbI
add
si, ax
mov si, lsi]
;fetch new delay routine offset
mov DelaylORout, si
;put in standard vector
jmp retry_calb
delay_cnt_set:
pop
si
pop
bx
pop
ax
ret
calc_spdlO endp

6-293

DelaylORout, si
cmp

bx,

Ap·341

proc

near

Input: Nothing
Output:
bx = elapsed timer count
all other registers preserved
Function:

Test current delay routine for 10 microseconds
and see how many time ticks go by when it is called
lO times. Return timer tick count in bx.

push ax
push cx
; Disable Ints .
cli
try_calb1:
mov cx, CalbLoopSiz
;count out 1 millisecond delay
xor
al, al
; Set counter latch for 8254
out
43h, al
WaForlo
in
al, 40h
;Read high byte
mov ah, al
WaForlo
in
al, 40h
;Read low byte
xchg ah, al
mov bx, ax
;save count
try_calb2:
call
word ptr DelaylORout
loop try_calb2
xor
al, al
; Set counter latch ~or 8254
out
43h, al
WaForlo
in
al,40h
mov ah, al
;Read low byte
WaForIo
in
al,40h
;Read high byte
xchg ah, al.
sub
bx, ax
;Check for rollover
jnc
calb_exit
;Return, if no rollover
;otherwise, repeat
jmp try_calbl
calb_exit:
sti
pop cx

pop

ret

6-294

AP-341

beep_spla

proc

near

;Make a sound at the speaker

Input: Nothing
'Output:
TIME_K_ffi equ
TlME_K_LO equ

All registers preserved
18
12772

;Timer time constant

CDD""J
n::1IJ1"'V
... "''-AJ''£ _ _''''._''

push
push
push
mov
mov
mov
mov
div
out
mov
out
in
or
out
mov

ax
cx
dx
al,OB6h
dx, TIME_K_ffi
ax, TIME_K_LO
cx, FREQUENCY
ex
PIT2_CNT, al
al, ah
PIT2_CNT, al
al, SYS_PORT_A
al,003h
SYS_PORT_A, al
eX,OAOOh

call
loop

waiClO_miero
beep 1

in
and
out
pop
pop
pop
ret

al, SYS_PORT_A
al,OFCh
SYS_PORT_A,al
dx
ex
ax

;Henz

;notify 8253 that freq. data coming

;count

= 1,193,280 I frequency

;send low byte
;prepare high byte
;activate speaker
; 1 to low two bits
;time delay for sound

beepl:

beep_spla
code

;10 us delay

;deaetivate speaker
;0 to low two bits

endp

ends
end

6-295

out

PIT_MODE, al

AP-341

APPENDIXD
MS-DOS ROM VERSION OVERVIEW
Technical Highlights (Taken from Microsoft Product Overview)
Ram Economy
Because MS-DOS Rom Version executes from ROM, only 15KB of system RAM space is required
for MS-DOS. For a typical user, this will result in a savings of about 40KB of RAM over diskbased MS-DOS. As a result of this savings, the user is able to run more programs and work with
'
larger data files with the ROM Version than with disk-based MS-DOS.
Instant-On
MS-DOS ROM Version provides a significant reduction i~ "boot time," or the amount of time
it takes' from the completion of the power-on self test until a DOS prompt appears. With the
ROM Version, this typically takes one second.
No End-User Installation
MS-DOS ROM Version is pre-installed by the OEM (original equipment manufacturer). in the
system, thus freeing end users from the task of installing MS-DOS.
Adaptable to OEM Hardware Platforms
MS-DOS ROM Version is structured such that it allows the OEM to include a specific routine
to determine which drive' to boot from and any specific parameters if booting from the ROM
drive. This makes it possible to easily port the ROM Version to a wide variety of hardware
environments. MS-DOS ROM Version is also positioned independent, in that it can reside anywhere in the "reserved" space (the area between 640KB and 1MB). This provides an additional
level of flexibility in allowing the OEM to adapt MS-DOS ROM Version to the specific requirements of the OEM's hardware platform.
ROM Economy
MS-DOS ROM Version occupies only 62 KB of ROM space, thus minimizing the amount of·
ROM that an OEM must include in the system. Three modules reside in the reserved space
Command. com, IO.sys and the DOS Kernel. All three are position independent, so an OEM
can decide where to place these modules in the reserved area.
National Language Support
. '
Microsoft offers a full compliment of localized version of MS-DOS ROM Version, including
Kanji and Chinese translations.
Ease of Development
As PCs become the engines for many embedded applications, manufacturers would like to
develop new applications utilizing existing PC software tools. MS-DOS ROM allows manufacturers to take full advantage of these tools. For instance, a programmer can develop and debug
an application onto a PC subsystem which may be embedded into a larger system. This benefit
translates into a cost savings when developing a solution for vertical markets.

6-296

APPLICATION

AP-343

NOTE

. October 1990

Solutions"for High Density.
, Applications
Using Intel Flash Memory

MARKUS A. LEVY
DALE ELBERT
APPLICATIONS ENGINEERING
INTEL CORPORATION

Order Number: 292079-001
6-297

Solutions For High Density Applications
Using Intel Flasl1 Memory
CONTENTS

PAGE

INTROPUCTION ....................... 6-299
ADVANCED PACKAGING ............. 6-299
Plastic Leaded Chip Carrier (PLCC) ..... 6-299
Thin Small Outline Package (TSOP) .... 6-300
Single In-Line Memory Module (SIMM) .. 6-301
Memory Cards ......................... ~-304
HARDWARE DESIGN
IMPLEMENTATIONS ................ 6-306
Design Example-A Paged-Mapped
Memory Board ...................... , 6-306
Optional Board Features ............... 6-317
Initializing Software for the Paged
Memory Board ....................... 6-321
Linear Addressing ...................... 6-323
1/0 Addressing ......................... 6-324
Capacitive Loading ..................... 6-326

CONTENTS

PAGE

SOFTWARE DESIGN
IMPLEMENTATIONS ................ 6-327
Data Recording ........................ 6-327
Interleaving ... : ......................... 6-327
Write-Once-Read-Many (WORM)
Drives ............................... 6-331
Disk Emulation ......................... 6-336
Creating a Bootable Drive .............. 6-336
WHY FLASH?-CHARACTERISTICS

OF INTEL FLA~H MEMORY ........ 6-336
Power Consumption Comparison
(Watts) .............................. 6-336
Data Access Time ...................... 6-336
Reliability .............................. 6-337
Weight ................................. 6-338
SUMMARY ............................ 6-338
APPENDIX A .......................... 6-339
SCHEMATICS ......................... 6-345

6-298

"-t_f
in~

AP-343

INTRODUCTION
Mass storage encompasses many different technologies.
Though commonalities exist, mass storage strives for
nonvolatility, low cost per bit, and high density. Disk
drives provide the best known example. However,
many environments now require higher performance
and reliability with lower power consumption, even at
the expense of capacity. Flash memory uniquely meets
these demands.
Flash memory can be used as a mass storage medium in
applications including factory automation, notebook
computers, high-end workstations, point of sale terminals, and data acquisition systems. Even desktop computers benefit from solid-state storage. The motivation
to incorporate flash memory in any of these applications becomes obvious to the system designer who understands flash memory's benefits and density projec.
tions.
In an effort to understand these benefits, this document
includes both conceptual and application oriented discussions. These discussions will be kept to a minimum
with the real focus being on specific design techniques
and considerations.

ADVANCED PACKAGING
Mass storage is synonymous with high density. Disk
drives have increased the bit density of the rotating media via material improvements and closer tolerances.
For semiconductors, density requires advanced packag-

ing as well as higher capacity silicon (improved photolithography). Intel's Flash Memory devices are based on
the company's EPROM Tunnel Oxide (ETOXTM)
technology that enables the high degree of scaling required to achieve high density.
Intel offers the high density flash memories in several
package types. The standard packages are the Plastic
Dual In-line Package (PDIP), the Plastic Leaded Chip
Carrier (PLCC), and the Thin Small Outline Package
(TSOP). AdV!!!1('P(1 mnclnlar packaging in the form of
Single In-line Memory Modules (SIMM) and IC memory cards (small enough to fit in your shirt pocket),
provide the total splution.
Which package would be best for your application?

Plastic Leaded Chip Carrier (PLCC)
The engineer striving to reduce board space is already
using surface-mounted technology, such as PLCC. The
PLCC is seen frequently on PC add-in cards and motherboards. Compared to the DIP, PLCC uses as little as
35% the overall board space. Its small size, compared
to the DIP, is attributed to the terminal center-to-center spacing-50 mils versus 100 mils-as well as its
four-sided pinout. No drilling or lead-cutting is necessary as leads are soldered directly to pads on the circuit
board. The PLCC's 50-mil pad pitch is compatible with
most circuit board manufacturing equipment. Additionally, components can be mounted on both sides of
the board. However,the four-sided PLCC generally requires the use of a multi-layered board to layout conductor traces for maximum compaction.

6-299

inter

AP-343

Thin Small Outline Package (TSOP)
When overall space constraints· are critical, the TSOP is
the best choice. This is best exemplified by IC memory
cards. Low height is the key attribute of the TSOP,
measuring 1.2 mm versus 3.5 mm for the PLCC. (Mechanical drawings in Appendix;) State-of-the-art center-to-center terminal spacing of 0.5 mm yields a smaller package and narrower conductor traces than the
PLCC or DIP. In comparison, the volume of the TSOP
is t72.8 mm 3 versus 656.3 mm3 for the PLCC and
1872.3 mm3 for the DIP.

The TSOP is available in standard and reverse pin configurations (Figure I). Pins are located on only two
ends of the package. This approach simplifies trace layout while reducing the number of board layers because
traces can be routed out the non-leaded sides of the
devices. Very dense board layouts are accommodated
because components can literally be laid out end-to-end
and side-by-side. Figure 2 displays an optimal layout
best utilizing the TSOP's attributes. The close spacing
allows one bypass capacitor to be used for two devices
(provided they are not simultaneously selected). This
optim!ll component layout can be mirror-imaged
through th~ board to easily double the memory capacity.

All

As
~3

STANDARD PINOUT
E28F"020

Vce

Vpp
A 1S
A 15

03
Vss
O2

~
~

~
A4--~~

________________________________________________

~~~A3

~1
~

~
05

~,
A17

0,
~

REVERSE PINOUT

WE
~

Vss

F28F020

Vpp

~
~
Do
~

~S
~5

A12

AI
~
A3 ___

____________________________________________________

AS
~
__ A,
292079-17

Figure 1. 28F020 32-Lead TSOP-Standard and Reverse Pinouts

6-300

AP-343

E2BF020

F2BF020

It-

-v

E2BF020

-====

F2BF020

--==

- -=

F2BF020

E28F020

,
~O

It-

F28F020

E2BF020

292079-18

Figure 2. TSOP Optimal Layout: Highest Density Configuration

Single In-Line Memory Module (SIMM)
The SIMM is optimal where minimized board space
and upgrade capability are required. Compared to using S discrete PLCCs plus capacitors (3019.4mm2), the
equivalent memory capacity SIMM (926.lmm2) consumes 70% less motherboard real estate.
The Intel Flash Memory SIMM is an SO-pin, 0.050 mil
centerline lead spaced, insertable module designed with
a 16-bit wide data bus interface. Intel's SIMM pin configuration allows convenient implementation:
• No Address or Data Bus Multiplexing-RAS# and
CAS # are not needed;
• Reserved Pins-For product expansion and enhancements: Upgrade capability to 128 Mbytes;
• Presence Detect Eliminates Jumpering-Simplifies
user installation.

The SO-pin definition of the flash memory SIMM includes 7 pins for Presence Detect (PD). (See Appendix
or SIMM Data Sheet.) The PD pins are read to determine module memory capacity and speed of the devices. The PD pins are either Open circuit or Shorted to
ground. By attaching a pull-up resistor to each pin,
Open circuits will read as a binary I and Shorts as a
binary O. Before implementing the presence detect feature, define your system criteria:
How many modules will be used?

Decide how much total memory your system is to contain. The limit is dictated by the space available, as well
as cost.
Flash memory SIMMs can easily accommodate different
memory capacities and speeds. Could your system handle mismatched SIMMs?

6-301

AP-343

There are two basic design implementations for interpreting presence detect information. The first approach
requires that matching SIMMs are used. The PO pins
of all SIMMs are tied to one transceiver that is read as
an I/O port (Figure 3).

transceivers, resistors, and I/O ports (Figure 4). Flexibility is increased at the expense of board real estate.
Assume your system accommodates several SIMMs but
complete population is not needed. Can the system handle empty sockets?

Invalid reads occur if the user installs mismatched
SIMM configurations. Any PO pin shorted to ground
makes an open circuit pin appear as a binary zero (0).
Mixing module speeds is acceptable, but the PO pins
reflect the slower module.

SIMM upgrade capability is not limited to increases in
memory density. A system may be designed with several SIMM sockets on the circuit board. To keep initial
end-customer costs down, the system ships with only
one SIMM installed. This provides the option of populating the empty sockets at a later time. The PO pins
are designed to eliminate jumper or software setups by
the end-user when SIMM upgrades are made.

The second approach, allowing any mixture of flash
SIMMs, requires more hardware and software for interpretation. The PO pins from each SIMM have separate

100i

I~ch

PD IIno I. attachod

t. a

separate 100k resistor tied to

+SV.

292079-19

Figure 3. All SIMMs Should Reflect the Same PO Configuration

I/O PORT_2 Enable

I/o

PORL4 Enable

100:[

I~?ch

PD IIno I. attachod t. a
separate 100k resistor tied to
+5V.

292079-20

Figure 4. Multiple 110 Transceivers Are Needed If Mismatched SIMMs Are Used

6-302

Ap-343

Using the previous scenario, will it matter, which socket is
used? In other words, what is the installation procedure?

Presence Detect for WAIT-State
Interpretation

With respect to the PD feature, it does not matter
which sockets are full. (However, most designers request that sockets are filled in sequential order to minimize hardware and softwear requirements.) To explain
this, look again at the bit-level interpretation of the PD
, pins. An empty socket also appears as an open circuit.
Your software can determine a full (or empty) socket in
ont: 01 iwu Wtlyi);

Using Method One or Method Two from above, the
device speed information is read from the pins. This
information can be interpreted by software to issue the
proper command to the system's programmable
WAIT-state generator. By guaranteeing the use of
matching SIMMs, the WAIT-state generator would not
have
to be..1 reprogrammed each time a different SIMM
=_ - ______

Method One (Figure 3)-Reading the PD pins is insufficient. An empty socket will reflect the value ofthe full
socket. Your software will have to read the chip level
device identifier hardwired in each flash memory device., (See Intel Flash Memory data sheets regarding
inteligent™ identifiers.) Reading an invalid device
identifier from a SIMM address signifies an empty
socket. Software demonstrating the use of this method
to determine memory capacity is discussed further in
the section on "Verifying Paged Memory Board Functionality".
'

A hardware driver alternative implements an 8SC220
EPLD configured with an internal counter (Figure 5).
The rising edge of the clock, following Chip Enable
going active, latches the count value derived from the
PD speed pins (Figure 6).

Method Two (Figure 4)-Each SIMM's PD pins are
read separately. Reading all ones (the result of all Open
circuits) signifies an empty socket. The chip level device
identifiers should still be read to establish the number
of flash memory devices on the SIMM.

1;) a.\"\"~""",,,.

Each subsequent rising edge of the clock input decrements the counter. A READY signal is output to the
CPU (or the system's READY logic circuitry) when
the count reaches zero (0). The READY signal remains
active until LOAD (Chip Enable, CE) goes inactive at
the completion of the bus cycle.
The clock signal for the internal EPLD coun,ter is derived directly from the CPU, therefore the count rate
and WAIT-states will be system dependent. An EPLD
Advanced Design File was generated to demonstrate
this application. (See Appendix A.) This is a straightforward approach until designing systems, such as power-saving laptops, that have changeable system clock
rates. '

CPU CLOCK DETERMINES COUNTER RATE

ClK
EPLD
D85C22D-aO
INP:z
1/0.1 INP
3
INP4
INP s INP s

CLOCK
READY

CPU

PD3
PD4
PDs
P~

SIMMs

J
ADDRESSES

DECODE
LOGIC

CHIP ENABLES

292079-21

Figure 5. WAIT-State Generator Using an EPLD Configured as a Counter
6-303

inter

AP-343

ctK

L ___ ____-1__
~

lOAD

.;.;PD;;;;n=PD3.pD4.P05.PD7

(eE)

T1 =7n.

T2=5.5n.
T3=Onl

,READY

292079-22

Figure 6. Timing for SIMM Presence Detect WAIT-State Generator
infinite storage time with power off (10 years minimum,
100 years typical). Additionally, SRAM is expensive
and not a high density solution. Intel Flash Memory
prOVides a denser, more cost effective and reliable solution.
'

Memory Cards
Many laptop and notebook computer manufacturers
are pursuing the IC memory card to incorporate a removable mass storage medium. This is an ideal application for the Intel Flash Memory TSOP, due to the
package's minimal height.

System level cost is about the same for, Intel Flash
Memory and SRAM + batteryFlash memory requires l2V for programming and erasing. If a 12V supply is not available, 5V can easily be
boosted. (See Application Note AP-3l6.) SRAM +
battery requires battery state detect circuitry.

Solid-State Memory Alternatives
ROM and SRAM are currently the dominant IC card
memory technologies. ROM has the advantage of being
inexpensive, but is not changeable. When' newer software revisions (e.g. Lotus· 123, Wordstar··, etc.) are
. available, the user must buy a new ROM card for each
upgrade. Intel Flash Memory's reprogrammability
minimizes the user's expense and the OEM's inventory
risk.

Card hivel cost differences are substantial (Figure 7)SRAM must have a battery to retain data. It also requires aVec monitor and Write Lockout circuitry. Intel's Flash Memory only requires Write Lockout circuitry (switching Vpp to OV is an alternative write protect). This leads to increased ,area for memory components. More importantly, Intel's Flash Memory density
is 4 times that of static RAM, yielding for lower cost
per bit.

SRAM is reprogrammable but batteries are required to
maintain data, risking data loss. Like magnetic disks,
flash memory is truly nonvolatile and thus has virtually .'

CARD LEVEL

Iii

...
5
...
a::

Balle"
Higher Otnsltles

InCreG.ed ANa
for ...mory

SYSTEt.I LEVEL

J v~~. J

Bolter),

Stat.

Detect
CircuIt

rLASH

SRAt.t

Components

W~.

Lockout

Vee Monitor
CIrcuits

Write
Lockout
ClrcuH

CIrcuit

Low"
Dtn,ltle.

ruSH

SRAt.t

Figure 7. Support Circuitry Cost Com,parison
*LOTUSIII> is a registered trademark of LOTUS Development Corporation.
"WORDSTARIII> is a. registered trademark of MICROPRO.

6-304

292079-23

Ap·343

tary formats are also available from their respective

Designing a PCMCIA/JEIDA Standard

manufacturers, but these same manufacturers now offer
PCMCIA/JEIDA versions. The PCMCIA/JEIDA
standard specifies physical, electrical, information
structure, and data format characteristics of the card.
This standard accommodates either 8- or 16-bit data
bus widths.

Memory Card
Choosing among IC card design options depends on
card architecture (standardization), memory capacity,
data bus width, card intelligence, Vpp generation, and
reliability.

The following 2 Mbyte memory card design provides a
byte-addressable interface using 8-28F020s (2 Mbit,
256k x 8 devices) as shown in Figure 8. While TTL
equivalent interfacing is shown, most cards will use
gate arrays to reduce chip count. Address lines AlB
and Al9 are decoded with a 2-to-4 decoder (74HC139)
to generate high and low byte chip select signals for
each 9f the 4 pairs of flash memory devices (one pair =
high and low byte). The PCMCIA/JEIDA format
specifies inputs CSL and CSH (along with the AO address line) which select the low and high byte, respectively.

What are the advantages of a standardized memory card
pinout?
From the computer system's viewpoint, a standardized
pinout enables the use of multiple third-party memory
cards. This ensures competitive pricing and wide availability. From the memory card point of view, standardization allows use in a variety of systems.
The Personal Computer Memory Card International
Association/Japan Electronic Industry Development
Association (PCMCIA/JEIDA) 68-pin format is the
emerging IC memory card standard. Several proprie-

HIGH

LOW

"0-17

AO- 17

28F020

74HC244

ADDRESSES

------+-----.---~~
------r-~--~~

(Octal Buffer)

DATA

+-.....- - - _

DB- 15

/"'3-r-----......-I

DATA
00-7
High byte
to low bus

292079-24

Figure 8. Decoding for PCMCIAI JEIDA Standard Bus Interface

6-305

inter

: AP-343

According to the PCMCIA/JEIDA standard, the
memory card is designed with the flexibility to have
both an 8-bit or a 16-bit interface, dependent upon the
machine it is plugged' into. When the memory card is
plugged into an 8-bit systein, the high byte transceiver
is multiplexed to the low byte of the system. In Figure
8, the highlighted transceiver (#2), maps the upper
byte to the lower byte of the data bus (i.e., DS-Is to
DO-7). Signals are decoded according to the truth table
in the Appendix. (1, 2, and 3 denote transceiver numbersof Figure 8.)

and is only practical in a 386TM microprocessor (or
other 32-bit processor) family system because of the
large memory space available above I Mbyte. The I/O
mapped memory array consumes the smallest amount
of the system adqress space but has the lowest performance. A page-mapped memory array, also called a sliding AT window, is a hybrid of the linear and I/O designs. The memory array is usually very large relative
to the system interface, consisting of pages typically
ranging in size from 8 Kbytes to 64 Kbytes. (LIM-EMS
use four to twelve 16 Kbyte pages.)

One can double the memory capacity and select from
among 8 pairs of flash memory devices by using a 3 to 8
decoder with inputs AIS-20. Notice that additional
transceivers are not needed to support the addi~ional
data fanout. (See section' on capacitive loading.)

Design Example-A Paged-Mapped
Memory Board

HARDWARE DESIGN
IMPLEMENTATIONS
Paged, linear, and I/O are the three fundamental addressing methods that can be used for accessing an array of memory devices. Linear addressing offers the
fastest and most direct access to a memory array. It
consumes the largest portion of the system's memory

A paged design employs addressing techniques similar
to the Lotus-Intel-Microsoft expanded memory specification (LIM-EMS). It allows access to one or more
sections (or pages) of the flash memory array at a time.
This minimal interface is particularly useful within the
DOS I Mbyte memory space. The DOS map (Figure 9)
shows 128 K;bytes of memory' space available in the
Optional I/O Adapter ROM area. LIM-EMS, LAN,
the flash memory design discussed in the following sections, and other accessory cards can use this area.

1000000H (16 MBytes)
EXTENDED
MEMORY
100000H (I MByte)
PC/XT/AT PS/2
ROM-BIOS
FOOOOH (960k)
PC/AT PS/2
ROM-BIOS
EOOOOH (896k)

../"

PAGE MEMORY BOARD CAN
BE INSTALLED
WITHIN THIS
128 Kbyte AREA '-...

OPTIONAL I/O
ADAPTER ROM
COOOOH (768k)
DISPLAY
BUFFERS
AOOOOH (640k)
APPLICATIONS
DEVICE DRIVERS
DOS
OOOOOH

Figure 9. DOS Memory Map

6-306

292079-25

AP-343

Figure 10 shows the block diagram of the page-mapped
flash memory board design. (Except for the addressing
method, all the functional components of this board
could be used on a linear or I/O mapped flash memory
array.) This PC-AT'" compatible design example
consists of a flash memory array (using SIMMs) and
the corresponding memory and VO decoding, Vpp
generation, and the interface to the system bus. (Comp-

onent numbers shown with the following diagrams correlate with the actual schematics in the appendix.) A
page size of 64 Kbytes is used. Depending on the system's configuration, memory contention may require a
smaller page size. (Note that the LIM EMS 4.0 standard uses 4 contiguous 16 Kbyte pages. Multiple pages
can exist as space permits.)

i
I/o

ADDRESS

DECODE

DATA

PRESENCE DETECT

I/O CONTROL

SELECT

Vpp ENABLE

vpp
GENERATOR

SYSTEM
BUS

INTEL
FLASH
MEMORY
SIMMs

vpp

I
""MEMORY CONTROL

CHIP ~NABLE

MEMORY
DECODE

RD.

(C'El

WEL. WEH

TRANSCEIVER SELECT

292079-26

Figure .10. Page-Mapped Flash Memory Board

"'PC-AT® is a registered trademark of International Business Machine Corporation.

6-307

inter

Ap·343

The Decoding Scheme
The Intel Flash Memory on this board is installed in 4
SIMM sockets. With a fully populated board, the memory capacity ranges from 4 Mbytes to 16 Mbytes depending on the SIMM density used.
~ending

on the density, up to ei~ chip enables,
CEo-CE7' are used on a SIMM (4 CEs for 8-chip, 8
CEs for 16-chip SIMMs). Standard decoding techniques generate separate chip enables, output enables,
and write enables. This method has the disadvantage of
having to accommodate a large number of traces. The
addressing scheme incorporated in this design min-

imizes the number of board traces neeed to select individual devices. Device selection is made on a row-column basis where: rows are Output Enables (OEs),
Write Lows (WRLs), and Write Highs (WRHs) and
columns are Chip Enables (CEs). (For low-powered
systems, this method may be unacceptable because each
chip enable activates a maximum of 8 components.)
These signals are generated by decoding the page lines
P3-P7 (Figure 11, U22). (See Page Number section.)
Pages within a component are selected by tying Po, PI
and P2, respectively, into pins 37 (A1S), 36 (A16), and
3S (A17) on the SIMM (Pin 3S on the iSM001FLKA is
a no-connect (NC».

74F138
3 TO 8 DECODER

-A

-B

CEo

-c

MEMDECODE

--<

U22

vee

Gl
GZA
GZB

Y5
Y6
Y7

74139

P6 - A
P7 - B

U24B
R--(G

Yl
Y2
Y3

CE7

°Eo
OE 1

l--:-

DEo
WRLo
WRHo

OE2

74139
YO

U28A
C--(G

Yl
Y2
Y3

74139
P6 - A

7- B

Yl
Y2

U28B
l--(G

••••••••
CE7

CEG CEs

CE 4

CE3

CE2

CE 1 CEo

PO PI P2

IIIIIIII

OE3

' - - - OE 1

P6 - A
P7 - B

WRLo
WRL 1

WRL 1
WRH 1

WRL 2
WRL3

WRHo
WRH 1

OE2
WRL 2
WRH 2

WRH 2
WRH3

OE 3
WRL3
WRH3

••••••••
IIIIIIII
••••••••
I
••••••••

PO PI P2

292079-27

Figure 11. Individual Components Selected by Row-Column Addressing Saves Board Traces

6-308

il"nt'eIr

AP-343

Planning for upgrades also presents another interesting
situation. The iSMOOIFLKA (I Mbyte SIMM) has
four chip enables (CEo-CE3), one for each pair of components. The pair of components represent high and
low bytes and are selected by WRH and WRL, respectively.

The iSMOOIFLKA represents sixteen 64-Kbyte pages
(eight 128-Kbyte components). To accommodate upgrade capability, pages within the iSMOOIFLKA will
not be contiguous because a "4-page hole" exists every
4 pages (P2 is attached to a no connect). To overcome
this rearrange the page select lines with jumpers (Figure 12):

2 iviuYLE:

.:JIIVIlVI

"' .......

[(iSM001 FLKA)
(16 • 28F010s)
In * "or::nl")n .... \
.c:..VI v,-vVI
\U

4 Mbyte

SIMM

(16 • 28F020s)

1 Mbyte
2 Mbyte

SIMM
SIMM

8 • 28F010s]

JP2, JP4, JP6, JP8
JP2, JP3, JP7, JP9
JP1, JP3, .-,Pi> .. IP7
JP2, JP3, JP6, JP7

TO SIMM

TO CHIP ENABLE DECODER

JUMPERS

fROM PAGE

: :
o

JP4

SELECTING
P2

JP7

JP8
JP9
JP5

LATCHES

JP3

~L :

JPl

DE, WRL, WRH
~

DECODERS

TO CHIP ENABLE DECODER

JP6

1GND

JP2

Figure 12. SIMM Density Upgrading Jumpers

6·309

DE, WRL, WRH

DECODERS
292079-28

inter

AP-343

If a system is designed that uses PCMCIA/JEIDA
standard memory cards instead of SIMMs, this decoding is greatly simplified. The memory card is treated
like a large memory array. Using a 64 Kbyte page size
as' an example: .

Address lines AO-15 are supplied directly from the system address bus (after buffering). Address lines AI6-23,
which select the pages, are sent as data to a latch before
entering the memory card (Figure 13).

PCMCIA STANDARD
MEMORY CARD

74FS21
COMPARATOR

AO- 15

SWITCH

---'""1

" - - - _ I AO- 15

A16- 23

1---.....

PO- 7

-aG

~A~E~N~____________

Control signals and data lines

74F273
(D-TYPE FLIP-FLOP)

A16- 23

00- 7
t------~---'" 00-7

QO-7t----~~!!!"'~~----_IA16-23
SELECTS PAGES

/>----1> ClK

Ir----L---10 PAGE
NUMBER
(from I/O decode circuitry,
not shown)

ClR

RESET
(forces page zero on power up)

292079-29

Figure 13. Memory Card Interfacing

6-310

AP·343

The page inputs to the "Chip Enable" decoder (Figure
14, U22) are redefined as follows:

For a better understanding, you should verify the bit
combinations while stepping through the first few
pages. Notice that the sequenCing of page numbers does
not correspond linearly with the Chip Enables. This is
not significant because the data is read the same way it
is written.

P3 = P3, P4 = P2, P5 = GND,
P6 = P4, and P7 = P5.

Page
Numbers

Chip
Enable

u,l,2,3

4,5,6,7
8,9,10,11
12,13,14,15

2
1
3

NOTE:
Linear Page Selection Results in
Nonlinear Chip Enable.
74F138
3 TO 8 DECODER
PIN ARRANGEMENT
ArTER JUMPERING

P3-A

P2-B

U22

Vee

Gl
MEMDECODE----<: GiA

GiB

Y3
ENABLES FOR HIGH AND LOW BYlES

Y40
Y50
Y60

.PO- A15

P l - A'6
P 2 - NC

••••
CEJ

CE2

CE,· CEo

292079-30

Figure 14. Component Selection Relative to Page Number for 1 Mbyte SIMM (iSM001FLKA)

6-311

inter

AP-343

AEN (address enable), the chip select for·the 74F521
comparator, is supplied by the PC I/O channel. It-distinguishes processor bus cycles from DMA bus cycles.
A high on AEN indicates that a DMA (or DRAM
refresh) cycle is in progress and we must stay off the
bus. The enables for the 74F138 10DECODER (U31)
are provided by 10DECODE ENABLE along with the
"ANDing" of lOR and lOW. This decoder selects the
I/O ports that access the page window address, the
SIMM presence detect pins, the Vpp Enable, and the
page number. Each of these I/O ports are described in
detail:

I/O Decoding
Multiple 'functions can be implemented with I/O decoding access. Some examples include: reading the current window address, reading the presence detect pins,
enabling Vpp, and reading/writing the page number.
The eight consecutively addressed I/O ports on this
board (4 reserved for optional features) are located at a
user-selectable address. This base I/O port address is
setup on an 8-byte boundary by using A3-10 as inputs
to the 74F521 comparator (Figure 15, U30). When any
of the eight consecutive I/O port addresses matches the
dip switch settings (and AEN is low), the comparator
outputs the I/O Decode Enable (to decoder U31).

74;521
COMPI~~~-----

Y1K>~~~----
Y2K>~~~------

U31 Y31O-=-'-----Y4 K>..:.R::Et.:;;:D;,.W:;;I::;.NDO=W:...;I<:;;:D::D:::RE:::S::.S_

vee
'"---IGI

'"-----aG21<

REt.D PRESENCE DETECT PINS -

Y6K>~V~P~PE:N~_ _ _ ___

REt.D

RITE PI is a registered trademark of International Business Machine Corporation.

0-317

inter

AP~343

Access to a word (2 bytes) requires two bus cycles to
generate two addresses in an 8-bit system. As an example referring to Figure 20, when accessing a memory
word at address zero (0):

The circuitry at the SIMM transceiver interface deter- ,
mines whether to use the Bus High Enable (SBHE)
signal or Ao to select the high byte. The 16BIT signal
selects the "A" or "B" inputs of the 74F157 multiplexer (Figure 21, U27). Regardless of the bus size, the
WRL signal is generated on a system memory write
(SMEMW) to an even address (AO = 0). During a 16bit write, the WRH signal is generated by a system
memory write to the high bus (BHE). H~r in,an 8bit system, where SBHE is absent, the WRH signal is
generated by a system memory write to an odd addressed byte (Ao = 1).

16BIT = 1, MEMDECODE = 0;

During access to the low byte -+ AO = 0, so the signal
"LOW 8/16 BIT" is active;
.
During access to the high byte -+ AO = 1, so the
signal "HIGH 8 BIT" is active.
The high byte from the SIMM is multiplexed onto the
low byte of the system bus.

TO WRL DECODER ENABLE

St.lEt.lW

-',/

I)-

SBHE

GND

PC AT

not present on PC XT)

I- .,"

t.lEt.lDECODE

TRANSCEIVER BAN K DECODERS

)
)

LOW BANK

U27

HIGH BANK

4A
4B

AlB

_....f---------+PLD
}-------+i'Li

, SAD

7-4f'138
3 TO 8 DECODER
A

SA,

5',
Ul

ENABLE the
and
~~~~~~~l:I-______+TOdtransceivers
....lc. decoder

)----+CLOCILPULSE

Vee

1O------------------------+VppEN

o.
0'
02
03
O.
05

DIP SWITCH
TO SET

I/O BASE
ADDRESS

P=Q
74f521
COWPARATOR

292079-46

Figure 29. I/O Decode and Enable Circuitry

6-324

AP-343

An I/O write to the first and second ports generates
parallel load signals, PLo and PLIo These signals latch
the "data" (addresses) into the 4-bit counters (Figure
30, U3-UIO). This latched data represents the address
for the flash memory devices.

A read or.write from the selected flash memory address
is performed when the third I/O port is accessed (Figure 29, Ul); this generates an enable for the flash memory device decoder and associated transceivers (Figure
31, To and T\).

TO '6TRANSCEIVER

BUFFERED
DATA BUS

Do
0,
O2
0,

ufu
A
aA
B
aB

Pla

E
Pi:

CLOCK_PUL~

ac
aD

r-r-+
r--

t---+

Do
0,
O2

Ao
A,
A2
A,

O.
Os
Os
07

E
Pi:

010
D11

B
C

E
Pi:

D11

r-+

aA _ A , .
aB _ A , s
ae _A,S
00 _A27

E RCO
Pi:
'-~

""'-'--0.:.:'2'-1 A
r,.,,_,-.:.:13~

Olt.

--+

A30

--+

A31

aB _

Pl\.._,-O.:.:14~ C
"'--I-_O':':'s~ D

A28

A,.

RCO

+----+--1 Pi:
' - - CP

Ul0

74HCi9i

PI,

292079-47

NOTE:

Ao-A3l are inputs to flash memory devices. Only address lines Ao-A18 are used for the
2BF020s.

Figure 30. Counter Circuitry

6-325

-L G,

r
.J:.

aA
A,o
aB _ A "
ac _A22

010

Y' 0 - YS 0 - -

Vee
ENABLE

Y' 0 - -

Y60--

::.;fro::.:m:...:u:.:.'_~ G2A

C
DaD_A"

00 _ A "

'-~

Rcon

Reo

I I _

Y20--

A18

E
Pi:

,2L- e

r--v A,.

-,;:--

A17

aA _ A s
aB _ A .
ac _ A , o

RCO

Os
07

00 _ A 7
RCO

TUC

aA~ A,s

~
A

B
C
0

aA _ A .
aB _ A s
ac _ A s

-~
O.
D.

"I"

Rcon

~
A
B

J;:,

.r-~

2Bf020's

A19~

Y70--

LG_2".B=:-:-.J

74F138

GNO

292079-48

NOTE:

All counters are configured in the UP count
mode.

AP-343

- - - - W E L

10W_
BHE

'~------------------------------------~-------------------WEH

0- 0 7
TO TRANSC ElVER
BUFFERED
DATA BUS

A3
A4
A5

r-<=

B5
B7

FDO
FDI
FD2
FD3

F04
FDS
FD6
FD7

G
DIR
74F245
(TRANSCEIVER)

,DATA
ENABLE

74F125

FOa
FOg

FOio
FO ll
FD12
FD 13
FD14
FD 1S

G
Da-0 15
TO TRANSC ElVER
BUFFERED
DATA BUS

DIR

TO DATA BUS OF
FLASH MEMO RY
DEVICES

74F245
(TRANSCEIVER)
292079-49

NOTE:
The 16-28F020's are arranged as a 16-bit word configuration. WEL and WEH are for the low and high bytes, respective-

ly.

Figure 31. Transceiver Enable Circuitry
The fourth I/O port activates the circuitry that obtains
very high performance from an I/O board. A read from
the fourth I/O port address generates the clock signal
for the 74HC191s, CLOCK_PULSE. The counter increments on the rising edge of the clock (read signal),
selecting the next flash memory address. This rising
edge occurs at the end of the I/O read cycle and the
data has already been read. This method is analogous
to address pipelining. It is perfect for a "string" read
because continuous reads from the fourth I/O port automatically increments the address to access the next
word of data stored in the flash memory array.

Capacitive Loading
Capacitive loading is an important consideration for a
solid-state mass storage device. If proper buffering
techniques are not followed, performance degradation
will occur.
The specifications for Intel's Flash Memory devices are
based on a test capacitive load of 100 pF. Each data line
contributes 12 pF, therefore 8 devices connected to one
data transceiver will not experience speed derating
(12 pF • 8 = 96 pF). Additional flash memory devices

6-326

intJ

AP-343

on that transceiver will increase the loading seen by any
one device.
Degradation is calculated as follows (Q = Amount of
Charge, T = Time, C = Capacitance, V = Voltage,
and I = Current):

disks will also be replaced by Intel's Flash Memory
when higher reliability, lower power consumption,
higher performance, and lighter weight are required.

Interleaving
Although the basic concept of data recording is similar
from system to system, variations in implementation
exist. For instance, some applications require high-

COULOMBS LAW STATES:
0= laT

!:peed de!:! 2Cq!!!5!!!0!!

AND GIVEN THE RELATION:

aO/C -- I = C aV/aT

FROM THIS RELATION, THE CHANGE IN ACCESS TIME CAN BE EXPRESSED IN TERMS OF
CAPACITIVE LOAD:
aT=CaViI

For example, using four SIMMs, each with 8 components in a 16-bit configuration (4 components on high
byte and 4 components on low byte), each Intel Flash
Memory device sees a load of 15 devices (12 pF • 15 =
180 pF). This loading is 80 pF iii excess of the device
specification so therefore:
Time
_ Additional
x (Vee - Vou
Change - Capacitance
IOL

=BOpFX

(5.0 - 0.4)V
A
= 64n5
5.Bm

nAt~

programming rates are im..

proved considerably by employing interleaving techniques. The majority of time spent programming or
erasing a flash memory device results from the delay
times in the software algorithms. (It is advised to review the standard algorithms first. See any Intel Flash
Memory data sheet for Quick-Pulse Programming™
algorithm.) Interleaving takes advantage of these delay
times to begin programming consecutive devices.
There are hardware and software mechanisms for interleaving. The flash niemory array for hardware interleaving requires special decoding techniques (Figure
32). Contrary to linear decoding, the system address
lines Ao-A3 are decoded to provide the chip select signals and individual bytes are selected with the address
lines A4-A20. (For the Intel 28FOIO.) This decoding
technique allows software to automatically access sequential devices by writing or reading sequential memory addresses. (Data accumulated with program interleaving will not be stored consecutively within a single
device.)
The. interleaving algorithm to program the 2 Mbyte
flash memory array is shown in Figure 34 and 35. The
basic goal is to utilize the delay times. To simplfy the
algorithm for this discussion, the data will be programmed on a-byte-wide basis. Word-wide and double
word-wide techniques, discussed later, will further increase programming speeds.

(Reflecting worst case conditions.)

SOFTWARE DESIGN
IMPLEMENTATIONS
Each hardware implementation discussed above can be
used in several types of mass storage applications. The
general categories include: data recoders, Write-OnceRead-Many (WORM) drives for storing application
programs and fixed data, and magnetic disk emulators.

Data Recording
The applications for data recording represent an endless list. Examples include digital imaging, digital photography, point-of-sale terminals, patient monitors, and
flight recorders. These systems will use Intel Flash
Memory as a more economical and reliable replacement for SRAM + battery. Alternatively, mechanical

During multi-component programming, the number of
pulses required could vary between different devices.
Code is reduced if the programming loop does not have
to selectively "decide" if a byte has programmed correctly (verified). However, continual programming of a
programmed byte is not necessary and should be avoided. This is done by masking the command sent to that
particular device. The RAM table in Figure 33 is used
as a data and flash memory command buffer. After a
programmed byte has verified, its associated data and
commands in the RAM table are written with the value
OFFH (RESET command for Intel flash memory). The
data is also written as an OFFH since this is null program data.

6-327

AP-343

28FOID

A[4: 20) WORD SELECT

AD-16

Connection of Pins
at the Device Level
System
, Address
A4
As
A20

---

Device
Pin

Ao
Al
A16

292079-S0

Figure 32. Hardware Interleaving Block Diagram

DEVICE#
DATA

T AI

I 'N P 'U T I

6
F

0 I,M

I / 10

n+l n+2
Ip O'R T

PROGRAM COMMAND 40H 40H 40H 40H 40H 40H 40H

40H 40H 40H

VERIFY COMMAND COH COH COH COH COH COH COH

COH COH COH

VERIFY DATA D AI T AI

I ~ ,0 I

ro M

A ~ 0

)
292079-51

NOTE:
n = 14 for the example shown in text.

Figure 33. RAM Array Used as Data Buffer and Command Mask Storage

6-328

AP-343

COUNTO=SIZLOF_COMPONENT
PTR1=1ST ADDRESS OF FLASH MEMORY ARRAY
A

'" 4

LOAD RAM TABLE (AS SHOWN IN FIGURE 30)
FLAG =OFFFFH
STORLPTR= PTR1
COUNT1 =MAX-PROGRAM_TRIES

"'nIIIlJT?~

JJ.

FLAG used as indicator for successful byte program
verify.
MAX PROGRAM TRIES = 25
B

'" 4

t"'nupnNI="NTC::

1..................
~ "'I'\rnnnn.o.nt~
thic:: tlV~mnlA
- .. ... - fnr.....
..

PIlli;';,si'ADDRES-S ·oF RAM -TABLE DATA

PTR3=1ST ADDESS OF RAM TABLE PROGRAM_COMMAND
PTR4=1 ST ADDRESS OF RAM TABLE VERIFY-COMMAND
PTR5=lST ADDRESS OF RAM TABLE VERIFY_DATA

Initialize pointers.

CONTENTS AT PTRI-CONTENTS AT PTR3
CONTENTS AT PTR1 =CONTENTS AT PTR2
INCREMENT PTR1, PTR2, and PTR3
COUNT2=COUNT2 - 1

Program command to flash device.
Program data to flash device.
To get to next byte location.

"'~

All components gone through?

YES

PTRI =STORLPTR
COUNT2= #_OF_COMPONENTS

.1
CONTENTS AT PTR 1=CONTENTS AT PTR4
INCREMENT PTR1 AND PTR4
COUNT2 = COUNT2 - 1

Verify command to flash device.

~~
YES

D
292079-52

Figure 34. Program Interleaving AlgOrithm

6-329

inter

AP-343

D
COUNT2= # OF COMPONENTS
PTR 1=STORLPTR
PTR2=1 ST ADDRESS oF' RAM TABLE DATA
PTR3=IST ADDRESS OF RAM TABLE PROGRAM_COMMAND
PTR4=IST ADDRESS OF RAM TABLE VERIFY-COMMAND

Does Flash Memory Byte = Verify
Byte?

Shift bits .of flag left.

YES, GO TO PROGRAMMING ERROR

Exceeded program tries, go to error.
>~N;;.O_ _ _- .

All I's shifted out?

To access next byte of each device.
>~N.;.O_ _ _- .

292079-53

Figure 35. Program Interleaving Algorithm (Continued)

6-330

AP-343

Software and hardware interleaving are very similar.
Software interleaving is performed using conventional
decoding and addressing methods. Instead of incrementing flash memory addresses by one to access the
next byte (as with hardware decoding), the address is
incremented by the size of the component. While allowing the use of "general-purpose" (non-interleaved)
hardware, software interleaving requires reading back
the data in the same, non-sequential fashion as was
used for recording.

ly consumes 9 rnA (1 rnA ICC and 8 rnA Ipp) while
programming or erasing; this translates to about 100
mW. If interleaving with 16 devices, about 144 rnA (16
devices • 9 rnA) or 1.6W, is drawn. Battery powered
systems will have a practical limit on the number of
components in the interleaving loop. Failure to accommodate these current levels, resulting in Vpp voltage
drop, will compromise programming and erase reliability.

Interleaved erase is useful for erasing an array of flash
memory devices. This approach greatly reduces the total subsystem format time. As specified in the erase
algorithm, each erase pulse requires a 10 ms delay. (See
Quick-Erase™ algorithm in Intel Flash Memory data
sheet.) Without interleaving, the processor is idle during this delay time. As with program interleaving, this
time is used to begin the erasure of consecutive devices,
thereby reducing the overall erase time.

Write-Once-Read-Many (WORM)
Drives

Further program and erase time can be saved by supplementing the byte-wide algorithm with 16- or 32-bit
interleaving. Extra data and commands are added to
the RAM Mask Table. The major difference in the algorithms involves the verify operation. Depending on
the bus width, 2 or 4 bytes are verified simultaneously
as shown in Figure 36 (for a 16-bit algorithm).

Power Requirements for Interleaving
Current consumption is an important consideration for
interleaving. During programming, each device typical-

~"":'-+I

:::::=~~~=.:~

The optical disk is an example of a typical WORM
drive application. Its str.engths are extremely high densities and low cost per bit. However, it is an unacceptable solution for a low powered, lightweight laptop
computer system. It is this environment that solid-state
drives offer the greatest benefit. Solid-state ROMs have
historically been used in laptop systems to store software programs that seldom change. When the software
does change, the ROM "application hardfile" is discarded and a new one is programmed.
.
Unlike the ROM drive, Intel Flash Memories can be
reused and reprogrammed in a true WORM fashion. A
computer user can load favorite software programs on
the flash memory drive. Adding revised programs to
the drive is accomplished by writing to the next free
space or by erasing and reprogramming the entire
drive. Software drivers can be written to implement this
functionality in most operating systems.

PROGRAtoLCOMMAND=~PROGRAM_COMMAND OR OOFFH)

VERIFLCOMMAND= VERIFLCOMMAND OR OOFFH)
VERIFY_DATA= VERIFY_DATA OR OOFFH)

PROGRAM_COMMAND=(PROGRAM_COMMAND OR FFOOH)
VERIFY_COIIIIAND=(VERIFY_COIIIIAND OR FFOOH)
VERIFLDATA=(VERIFY_DATA OR FFOOH)

292079-54

NOTES:
1. MASK the HI Byte with OOH.
2. If the LO Byte verifies, then mask the data, program, and verify command with OOFFH (RES En.
3. Mask the LO Byte with OOH.
4. If HI Byte verifies, then mask the data, program, and verify command with OOFFH (RESET).

Figure 36. 16-Bit Masking for Verify Operation

6-331

intJ

AP-343

Microsoft has a flash memory file system for DOS. It
stores and retrieves data or application programs in a
manner that, to the end user, appears similar to a diskdrive. Employing "WORM" functional characteristics,
new files are written sequentiaIiy from beginning of
memory. However, when the disk is full, it can be
erased (saving the "good" files) and reused.
When an application accesses a disk through INT 21H,
the MS-DOS' .kernel checks the drive letter (Figure
37). If the drive has been declared as a flash memory

disk, the Installable File System (lFS) intercepts the
call. (This is very similar for accesses to a networked
drive.) Otherwise, if the drive letter is· that of a floppy
or hard disk, the call is handled by the standard DOS
block device driver. The Installable File System (IFS)
provides the link. between DOS and the Microsoft'
Flash File System driver. (The Flash File System and
Installable File System Driver are purchased through
Microsoft.) It changes all DOS commands into a form
understood by this unique file structure.

~PurChased
through

/MicrOSOft

'-----,r----'
Developed by
Computer OEM

INTEL
FLASH MEMORY
SOLID-STATE
DISK

292079-55

Figure 37. Disk Interface Levels

*MS-DOS® and Microsoft® are registered trademarks of Microsoft Corporation.

6-332

Ap·343

The Flash File System Driver is the "intelligence" of
this file system. It consists of:
I. A Boot Record that identifies the file system and
version, and locates the start of the data area;
2. The Root Directory Entry Record and many Directory and File Entry Records.
The file system driver is independent of the hardware
interface to the flash memory disk. The hardware deo

•

••

•

1- _

'-"'T"1I.1

VIce anvec, oevl:JUpCU uy UJC v ......n ...

__
V,L

........ &'+ ......... 0
.v ... _ ..... uov ............... _

DT£,,\CI

be variable, abandoning the traditional sector/cluster
approach of DOS. When "the stack" is full, the user
copies the desired files to another disk and erases the
current disk for reuse.
File and subdirectory information is attached to the beginning of each file, unlike the standard DOS approach
of directory and FAT placement. As directory and file
entries are added, they are located by building a linkedlist. Besides containing the customary fields (e.g., name,
•
.'
'II.
-I" ____ ... : __
_4-_ \
..
A: ... """' .. ,... ..'r ... "....1
eXtenSIon, LlIIlC, UaLC UI .... u::aLlvu, "''''-''J' ""' ........... _ ......... .,l' ...... _

vendor, interfaces the flash memory disk to the flash
file system. It is responsible for the low level calls to the
Intel flash memory devices. The actual implementation
of the interface is dependent on the hardware configuration of the disk (I/O, paged, and linear addressing are
examples).

file entry contains a status byte and various pointers
used for the linked-list process. The status byte, besides
indicating whether a file/subdirectory exists or is deleted is also used to signify valid sibling and/or child
pointers and to determine if a directory entry pertains
to a file or a directory.

The flash memory drive is treated as a WORM drive
with a bulk erase feature. To minimize fragmentation
losses and allow arbitrary extension of files, the flash
memory file system uses variable sized blocks rather
than the standard sector/cluster method of more traditional file systems. The fundamental structure employed to offer this flexibility is based on linked list
concepts; files are chained together using address pointers located within directory entries for each file.

When a directory or file is requested or added, the flash
memory disk is searched beginning at the bottom of the
linked-list. The chain is followed from pointer to pointer until the correct entry is found. If the search arrives
at the chain's end (an FNULL is encountered), the system responds analogously to DOS with a "File not
found" message.

Files and directories are written to the flash memory
disk using sequentially free memory locations-a stacklike operation (Figure 38). Furthermore, file sizes can

This linked-list chain consists of two basic types of
pointers: sibling and child. Sibling pointers are used to
locate directories or files at the same hierarchial level.
Child pointers are used to locate subdirectories or the
first file of a particular directory. The following examples elaborate these concepts.

BOOT RECORD
292079-56

Figure 38. FFS Storage

6-333

inter

AP·343

In Figure 39, Directories Band C are subdirectories of
Directory A. Specifically, Directory C is a sibling of
Directory B and both are children of Directory A.
FNULL indicates the end of the chain.
Figure 40 shows two files (File A and File B) added to
a directory (Directory A). File A and File B are at the
same level, therefore they are siblings. A file's directory
entry contains a Primary and Secondary pointer that
indicates the start of its data area.
An important function of FFS is related to deleting or
renaming files. Each file's directory entry contains a
primary and secondary pointer. When a file is first created, the primary pointer is set to point to the beginning
of the data. If that file is modified and rewritten to the
flash memory disk (because the original file cannot be
overwritten), the primary pointer is marked as invalid
(in the status byte). To make use of the existing directory entry for that file, the secondary pointer is used (see
Figure 41).

DIRECTORY ENTRY 8
(Subdirectory of A)

Sib lin
Pointer

When a file appears multiple times (because of deleted
versions) on the flash memory disk, the file system
must find the most recent version. The status byte contains bit fields that indicate whether that particular file
is a valid or deleted file. The directory information of a
deleted file is used for pointers of the linked list and the
search would proceed until the most recent version is
found.
A key point to be made for using this method of file
storage is that the user is in control of the rate in which
the disk becomes full; using the flash memory disk predominantly for application code storage and non-temporary data files reduces the frequency of disk "cleanup". However, flash memory will· typically perform
100,000 cycles and eliminates reliability concerns when
used as a hard or floppy disk replacement.

DIRECTORY ENTRY C
(Subdirectory of A)

Sib lin

STORAGE ON DISK
rNULL
DIRECTORY ENTRY C
Child
Pointer

DIRECTORY ENTRY 8

Sibling

DIRECTORY ENTRY A

Pointer

Data
Area
ROOT DIR
Pointer ' - - - - - - - . . ; . ,

Figure 39. Directory Arrangement

6-334

292079-57

Ap-343

Sibling

DIRECTORY ENTRY A

Pointer

fNULL

Child .,l.Pointer
Sibling
Pointer

fiLE ENTRY 8

Child lpointer

i
f~~~:

Pointer

fNULL

I PRIMARY POINTER

fNULL

Sibling

fiLE ENTRY C

...

file sizes are variable

MA.SS

fiLE C
DATA
CARRIB[AN
VACATIONS

STORACE

APNOTE

292079-58

Figure 40. File Arrangement

DIRECTORY ENTRY A

Child

Sibling

Pointer

Sibling

Pointer

...

NEW
fiLE B
DATA
I won
the !gUery.

fNULL

I PRIUARY POINTER (Recorded

I
. Child

Pointer

fiLE ENTRY 8

SECO NDARY POINTER

fNULL

Pointer

fNULL

...

as del eted in status byte)

OLD
fiLE B
DATA

STORAGE ON DISK

I will win
the lottery.

FNULL
. NEW FILE B DATA

New data is written
to next sequentially

Primary
Pointer

free space on the
flash memo~y disk

Data
Area

Pointer

OLD FILE 8 DATA
FILE 8 DIR
DIR A

Secondary

Pointer
Child

Pointer

ROOT DIR

292079-59

Figure 41. Modifying a File

6-335

intJ

AP·343

Power Consumption Comparison
(Watts)

Disk Emulation
A disk emulator represents the optimal use of flash
memory as a mass storage medium. However, this also
embodies the most sophisticated software implementation. Block erasability of flash memory requires modifications to the base level constructs of the magnetic
disk. Ideally these changes are transparent to the system user.

(Based on typical performance characteristics. The
20 Mbyte Flash Memory disk is based on the use of 8028F020s. Only two of the forty devices are accessed at a
time, the remainder are in standby mode.)
Active
Modes

Creating a Bootable Drive

Ready

The startup time of the PC can be decreased by booting
from a flash memory disk instead of the magnetic disk.
To do this, a "disk-image" is installed on the flash
memory disk which is located in the system memory
space between COOOOH and EOOOOH (Figure 10). (The
"disk image" contains the Boot Record, Directory; and
FAT.) This memory space is referred to as Expansion
ROM. During the system Power-On-Self-Test (POST),
the system searches this memory area for the ROM
adapter signature, 055AAh, marking the beginning of
the disk image. Once this signature is found, 'the
BOOTSTRAP process begins. The software to create
and install this "disk image" is available as a product
from Microsoft Corporation as ROM executable MSDOS.

WHY FLASH?
CHARACTERISTICS OF INTEL FLASH
MEMORY
Power consumption, weight, performance, and reliability are the key criteria for a system design. The discussion of Intel flash memory as a mass storage medium
would not be complete without a performance analysis
and comparison to other technologies.

Hard Disk Drive
(2.5" , 20 Mbytes)

1.7":'2.0

Read

3.5-4.0

0.15

Write

3.5-4.0

0.25

Power Savings

1.5

0.05
(Same as Standby)

Standby
Spinup
(from Standby)

0.1-0.5

0.05

9.3

For a battery-powered system, 3-4 hours of operation
is unacceptable. Battery longevity is achieved by using
Intel Flash Memory solid-state storage as a disk replacement. The following table relates battery life and
the different functions of disk operation. A "AA" battery with a capacity of 2215 mAH is used for the comparison. Obviously, for a truly accurate representation,
other components of the system should be included.
But from the data storage point of view, the flash memory disk will operate many more hours than the hard
disk drive on a set of batteries.
Hours of Operation for a "AA" Battery
(Based on Data from Previous Table
and 2215 mAH Battery Capacity)

Read

A drive has three basic operating modes: active, power
savings, and standby. The active mode consists of reading, writing, and ready. Ready condition allows "instantaneous" transitions into the read or write states. In
the power-savings mode only the drive motor continues
. ' to run. Standby shuts off all functionality except for the
circuitry needed to "spin-up" the drive. From the
standby mode, extra power and considerable time, is
required to "spin-up" the disk.

0.05
(Same as Standby)

Hard Disk Drive
(2.5" , 20 Mbytes)

INTEL
Flash Memory
(20 Mbytes)

0.83

22.15

Power Consumption
Portability of a computer demands battery longevity
1Illd consequently minimal power consumption. Small
form factor disk drives are being designed specifically
for the size and power requirements of laptops.

INTEL
Flash Memory
(20 Mbytes)

Write

0.83

13.29

Standby

6.64

66.45

Data Access Time

Reading data from a magnetic disk is a very slow process compared to a solid-state disk (SSD). Disk transfer
time is lengthy dJle to four time components: spin-up,
seek time, latency, and data transfer time. Spin-up is a
factor to consider for battery-powered systems, where
most disk accesses are begun from the standby mode.
During the seek time, the arm is repositioned to the
correct track. Latency is the delay from arm repositioning until the first sector of the transfer moves under the
6-336

AP-343

read/write head. This is dependent on the speed of rotation. The actual transfer of data is the third component. The standard SCSI interface transfers data between 5 Mbits and 10 Mbits per second, with which
flash memory compares very favorable.
For this example it is reasonable to assume a transfer
rate of 1.0 Mbytes per second. Using a full word-wide
(xI6) bus bandwidth (120 ns access speed of the device), flash achieves a transfer rate of 16.6 Mbytes per
second.
Read Speed Comparisons
Hard Disk
(Standard
SCSI
Interface)
Seek Time

28ms

Latency

8.3 ms

Floppy
Disk

Flash Memory
(16-Bit Bus,
120 ns
Access)

Transfer Rate 1.0'Mbyte/s 62 Kbyte/s 16.6 Mbyte/s
Total for
10 Kbyte File

46.54 ms

261.3 ms

The vagueness of the test procedures makes it difficult
to compare the MTBF for a flash memory solid-state
disk !!nn ~ hard disk. Based on the fact that disk usage
is 80% reads and 20% writes, a reasonable comparison
can be made. (What is not taken into account is that
disks are an 'infinite' write, but rmite read medium.
Continuous reading causes reduced magnetic field
strength, a failure mechanism hidden by re-writing the
disk.)
Intel's Flash Memory typically performs 100,000
erase/program cycles; (Failure does not occur at this
point. The only noticeable change is a gradual increase
in program and erase times.) Assume a flash memory
disk size of 4 Mbytes that functions like a WORM
drive; it is erased and reused after filling.

0
100 ms

One method uses the overall mean failure. The MTBF
of all critical components is computer analyzed and the
lowest one is selected. A second method tests 100
drives. The hours or the first ones to fail are multiplied
by the number of drives. How many reads or writes are
performed? Is the disk stopped and started during the
process? Standard answers do not exist.

0.62ms

(Floppy disk drive specifications combine access into
one category.)
In this example, the flash memory disk has 75 times the
read performance over the hard disk. Smaller files result in even greater differences. Additionally, the 5 second spin-up of the hard disk gives the flash memory
disk over 8,000 times the performance!
A byte will typically program in Intel Flash Memory in
one pulse. (See Intel Flash Memory Data sheet for programming algorithm.) Based on this and the parameters used in the example above, a 10 Kbyte file is written to the flash memory disk in 87.04 ms. Because
writes to a hard disk typically begin from spin-down,
the flash memory disk is still over 50 times faster. Since
reads are 80% of disk access, flash memory's user-perceptible performance advantage is substantial.

Based on a typical disk MTBF of 50,000 hours and the
80/20% division, 10,000 hours are used for writing
files. Assume the average file size written to disk is
10 Kbytes. A '4 Mbyte flash disk can store approximately 400 ><; 10 Kbyte files (4 Mbyte/lOK = 408)
before erasure is necessary.
These 400 files could be writen to the disk 40 X 106
times - (400 files X 100,000 cycles = 40 X 106). The
result is that within a 10,000 hour period, one 10 Kbyte
file could be written once every 0.9 seconds.
10,000 hours x 3600 Seconds = 0.9 Seconds
40 x 106 Files
1 Hour
File

It would be more realistic (although still extremely aggressive) to assume that this 10 Kbyte file is written to
this disk every 10 minutes. At 100,000 cycles, 40 X 106
files will have been written. The MTBF can be calculated as follows:
40 X 106 Files x 10 Minutes x ~ = 6.6 x lOS Hours
60 Minutes
File

Reliability
The definition of hard disk mean-time-before-failure
(MTBF) is extremely ambiguous. There are no industry-wide standards for making a reliable calculation.
Disk drive manufacturers choose whichever method
best suits their product's reliability perception.

This is an MTBF of over 6 million hours! (See Reliability Report RR60 for more details.)
A flash memory solid-state disk outlasts its mechanical
counterpart by at least two orders of magnitude, especially if head parking problems and limited start/stop
cycles of the mechanical disk are taken into account.

6-337

•

AP·343

Weight

SUMMARY

Lowering the power consumption of your portable system also lowers the weight. Reduced battery demands
mean smaller and'lighter batteries and power supplies.
Weight savings is also gained by the proper choice of
the mass storage medium. The small 20 Mbyte 2.5"
disk drives weigh between 9 and 21 ounces. The equivalent capacity of flash memory using 80-2 Mbit TSOPs
(which ipdividually weigh L16 x 10- 2 ounces) weighs
0.93 ounces plus the weight of the circuit board. (See
section on Intel flash memory packaging.) This difference is critical when the computer weight requirement
is under five (5) pounds.

The advent of Intel Flash Memory has led to the evolution of solid-state mass storage. This application note
has provided the building blocks that will allo~ the
innovative manufacturer to remain on the forefront of
technology.
• Advanced packaging, such as the TSOP, SIMM,
and Ie memory cards, is necessary for high-density
applications.
• Intel Flash Memory allows flexible system interfacing by using 110, paged, or linear addressing methods.
• Software variations enable an unlimited number of
mass storage applications for Intel Flash Memory.
• Intel Flash Memory offers superior performance
over the magnetic disk.

6-338

inter

AP-343

APPENDIX A

TSOP Dimensions

~-------------HD--------------+-~~==~~==~

DETAIL A

Symbol

-1.1

•

Description
Package Height

Standoff

Package' Body Height

Lead Width

Lead Thickness

Package Body Length

Package Body Width

Terminal Dimension

Lead Tip Length
Lead Count

Z
(2)

292079-60

Dimensions in mm
Nom
Max
1.27
0.15
0.20
0.25
0.96
1.01
1.06
0.30
0.15
0.20
0.10
0.15
0.20
18.20
18.40
18.60
7.80
8.00
8.20
20.20
19.80
20.00
0.35
0.30
0.33
Min

N
y

!-$-!O.05@!C!.®-B®!

DETAIL B

Seating Plane Coplanarity
Lead to Package Offset
Lead Tip Angle

0.00
0.20
1

0.25
3

0.10
0.30
5

TSOP Physical Dimensions Drawings and Specifications
6-339

AP-343

TSOP Sockets and Wands
32-Lead TSOP test sockets are available from the following vendors:
Yamaichi Eletronics
1420 Koll Circle, Suite B
San Jose, CA 95112
(408) 452-0797
Enplas
Distributed by:
Tesco International Inc. .
1825 S. Grant Street, Suite 745
San Mateo, CA 94402
(415) 572-1683

32-Lead TSOP to DIP adapter sockets are available
from the following vendor:
California Integration Coordinators Inc.
582 Main Street
Placerville, CA 95667
(916) 626-6168
Suction wands for transferring units are available from
the following vendor:
H-Square Corp.
1289-H Reamwood Avenue
Sunnyvale, CA 94089

6-340

AP-343

1
2
3

VSS
Vee
Vpp

CE3

CE2

CE1

A11
A10
Ag

CEO

WEH

VSS

WEL

As
A7
A6

A"7

009

008

007

D06

005

004

n03

002

N(';

"T ,

":J

RES

I'lC

RES

A4
A3
A2
A1
Ao

RES

P01

RES

VSS

P02

RES

0015

P03

RES

0014

P04

RES

0013

P05

RES

0012

P06

RES

A16
A15
A14
A13
A12

001

000

71
72

Vpp
Vee

0011

P07

0010

Vss

Figure 43. iSM001 FLKA (1 Mbyte SIMM) Pinout

6-341

inter

AP-343

I·

4.65"

----------..j,1

FRONT VIEW

0.33"

&"'D:':D~:15:':15:':"""""""~II'-:1~~'.,~)
~b

BACK VIEW

SIDE VIEW
292079-61

Figure 44. iSM001FLKA (1 Mbyte SIMM) Dimensions
Module Capacity Idenfitication
Module Capacity
Word Depth

Module Speed Identification

PD6

PD2

PD1

Maximum
Access Time

PD7

PD5

PD4

No Module

>300 ns

256K/32M

300ns

512K/64M

250ns

1M/128M

200 ns

2M/256M

185 ns

4M/512M

150 ns

8M/1G

135 ns

16M/2G

120 ns

100 ns

85 ns

70 ns

60 ns

50 ns

40 ns

30 ns

= Open Circuit On Module

S = Short Circuit to Ground on Module
ND = Not Defined

6-342

PD3

AP·343

EPLD ADF for Presence Detect WAIT-State Generator
PLFG Applications
1-800-323-EPLD
Intel Corp.
June 6, 1990
U999
002
85C220
Pre-loadable wait state down counter/READY generator
OPTIONS: TURBO
ON

PART: 85C220
INPUTS: CLK@l, nLOAD@2, PD7@3, PD6@4, PD5@5, PD4@6
OUTPUTS: nREADY@19, Q3@18, Q2@17, Ql@16, QO@15, nDL@14
NETWORK:
CLK
INP(CLK)
% System clock input %
nLOAD
INP(nLOAD)
% Load count input %
PD7
INP(PD7)
% PD[7:4] Wait state %
PD6
INP(PD6)
% count size inputs %
PD5
INP(PD5)
% to lookup table %
PD4.
INP(PD4)
nREADY, nREADY
RORF(nREADYd,CLK,GND,GND,VCC) % /READY Output %

=
=

=
=
=

=RORF
=RORF
= RORF
=RORF

Q3,Q3
Q2,Q2
Ql,Ql
QO,QO
nDL,nDL

(Q3d,CLK,GND,GND,VCC)
(Q2d,CLK,GND,GND,VCC)
(Qld,CLK,GND,GND,VCC)
(QOd,CLK,GND,GND,VCC)
RORF (nDLd,CLK,GND,GND,VCC)

EQUATIONS:
QOd
QOEQN * !READY * !COUNT_ZERO
+ QO • (READY + !LOAD)
+ XO • LOAD • !READY • COUNT_ZERO;
QOEQN = !QO;

Qld

% counter outputs • • • %
% not externally %
% necessary %

% count if not ready·%
% hold if ready %
% read inputs on LOAD %.

QIEQN • !READY * !COUNT_ZERO
+ Ql • (READY + !LOAD)
+ Xl • LOAD • !READY • COUNT_ZERO;
QIEQN
Ql • QO + !Ql • !QO;

Q2d

Q2EQN • !READY • !COUNT_ZERO
+ Q2 • (READY + !LOAD)
+ X2 • LOAD' !READY • COUNT_ZERO;
Q2EQN
Q2 • (Ql + QO) + !Q2 • .!Ql • !QO;

=Q3EQN

Q3d

• !READY • !COUNT_ZERO

+ Q3 * (READY + !LOAD)

+ X3 • LOAD' !READY • COUNT_ZERO;
Q3EQN
Q3 • (Q2 + Ql + QO) + !Q3 • !Q2 • !Ql • !QO
nREADYd'
nDLd

=
= !Q3

• !Q2 • !Ql • LOAD • !nDL;

=nLOAD;

% Anticipate
% to provide
% hold until
% taken away

EPLD ADF for Presence Detect WAIT·State Generator

6-343

counter %
READY%
LOAD is%

AP-343

COUNT_ZERO
lQ3 •
LOAD
NLOAD' ;
READY
nREADY' ;

=
=

lQ2 •

lQl •

lQO;

= GND;
= 3CNT;
=8CNT + 7CNT + 6CNT + 5CNT;
=5CNT;
8CNT = PD7 • IPD6 • IPD5 • IPD4;
7CNT = IPD7 • PD6 • PD5 • PD4;
6CNT = IPD7 • PD6 • PD5 • IPD4;
5CNT = IPD7 • PD6 • IPD5 • PD4;
4CNT = IPD7 • PD6 • IPD5 • .IPD4;
3CNT = IPD7 • IPD6 • PD5 • PD4;
2CNT = IPD7 • IPD6 • PD5 • IPD4;

% Wait State Scrambler %
% lookup table %

X3
X2
Xl
XO

END$

EPLD ADF for Presence Detect WAIT-State Generator (Continued)
Decoding Truth Table for "Multiplexing" Data Bus of PCMCIA/JEIDA Memory Card
System Bus Width

Data Transfer

CSH

CSL

80r 16

None

8 or 16

Lo-Byte

Hi-Byte to Lo-Byte

Hi-Byte

Low and High Byte

NOTE:

References Figure 8 in Memory Card Section.

6-344

inter

AP-343

PAGE MEMORY BOARD
SCHEMATICS

6-345

JA/81

-.-my

L~~--++-....;_~~~

~-I+--I,ifI

~g:
~g~
~~

GNO
SMEMW#
SUEMR,
14 lOW,
81
~tK3'
'6 DR03

L=J

:~~"

1 REfRESH,
1 eLK

8~~ ::g~

1 ::g;
B" IRQS

DACK2,

9 +5V
+--iH+'I---ii82m-1

t¥.¥-

50(0.• '5)
"(0.. '9)

0 .. "

SA.1Ii
1
SAtB A'4
:~~ A'
SA1S A16

A'8
SAt
A1
5A15

A!7

sit!"

SAt2:"
SAlt A21

SA!Z
SAID

:~;

~~ '2~

SA7

SAS

:;:27

SA5 A 8

SA2

LD(0 •• '5)

LD(O •• 'S)

,",(0•. '9)

LA(O....)

'OR,

""E(0••7)

lOW,

IWRL(O•.3)

.EN
MEMCS,.,
RESET

'WRH(O....)
'.0(0....)

GND
OWS

PO(O••6)
'
T{0 ••7)
Vpp

+5V

RESET,

~~
""E(0••7)
#WRL(D ••3)

tw RH(O••3)
,'0(0..3)
PD(O •.6)
T(0 ••7)
Vpp
RESETI

KA(O •• lS)
r---

r--

SAS A"

SOCKETS

r-"'-----

'/0 CH ROY,
'EN . "

2 ~E

i31

SOJ

••

~~~

a: WEll DECODE

SO(O•• '5)

507 A2

t"t-;:::tt:::t!U
~
!

I/O

1/0CHCK#~

, ONO
2 RESET'

KA(O •• I5)
+5V

SWEhlR,
SMEWI

16BITI

L-_ _ _ _ _ _--!

r--

~ ONO

...._ _ _ _ __

:~ A3~

•

"til
I

CONNECTOR PC-leT-1O

~ ::~,.,

:II

1/OCS'.#
IROtO

IRQ't
~ IROt2
~ IRQU
7 IRQ'"

,
11
~
~

:iJj

S8HE C,

LUll
,",23~
lA22~

LAZD
LA,9

,",'8

:g~o,.

..~~; ~

OACK5,
DROS

MEMW#
SDB C11

DACK6,

50s tt2

DRQB

15 DRQ7

WASTER,

18 GND

SOB

to
511

SD12

+--I____~'~ +SY

5011 CU·

5010

'4 DACK7,

Co)
~
Co)

SOt

5013 CtS
SDl04 1

SOt
104

$D15 CI8

SDI5

CONNECTOR PC-AT-IO

?BVPASS CAP'S

'---F::~

292079-16

ci:

VCC

£mJ----T
~

GND

SIMtLL2
C

(J)

c.:,
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"""

T 0 •• 7

T(0 .. 7)

+5V I

RESET#

GNDI

LA 0 •• 19

A(0 .. 14)

LD 0 •. 15

D(0 .• 15)

#RD 0 .. 3

#IlD(0 •• 3)

#CE 0 •• 7

#CE(0 •. 7)

IIWRL 0 .. 3

#WEL(0 •. 3)

IJlWRH 0 •• 3

#WEH(0 .. 3)

[ Vpp

Vpp

PD(0 .• 6)

PD 0 •• 6
P 0 .. 7

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I

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TCO .. 7)
RESET#
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A(0 .. 14)
D(0 .. 15)
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#WEH(0 •. 3)
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+5V I

PD(0 .. 6)

GNDI

P(0 •• 7)

'--

292079-15

AP-343

SAO
SAl
'SA2
SA3
SA4
SA5
SA6
SA7

2
4
6
S
11
13
15
17

lAl
tA2
lA3
lA4
2Al
2A2
2A3
2A4

IS
16
14
12
9
7
5
3

lYl
lY2
1Y3
lY4
2Yl
2Y2
2Y3
2Y4

,F
191 G
2G
GNO

LAO
LAI
LAlLA3
LA4
LAS
LA6
LA7

U19

4 lAl
lA2
6 lA3
S lA4
11 2Al
13 2A2
IS 2A3
172M

SA11

U168

5
rsiiE"'!!L?

GNO

SA12
SA13
SA14
SA15

~
19

GNO

6
S
11
13
~
17

lAl
lA2
lA3
lA4
2Al
2A2
2A3
2A4

lYl
lY2
lY3
lY4
2Yl
2Y2
2Y3
2Y4

KAO _
KAI _"
KA2 _"I
KA3_
KA4
KA5
KA6
KA7

IS
16
14
12
9
7
5

tA-

~lG
19
2G

74f244

SAO
SAl
SA2
SA3
SA4
'-SA5
SA6
SA7

U1S
SAS
SA9
SA10

LA(0 •. 19)

U17

SA 0 .. 19,-",

lYl
lY2
lY3
lY4
2Yl
2Y2
2Y3
2Y4

lS
16
14

GNO

LAS
LA9_
LAlO
LAll
LA12
LA13
LA14
LA15

I1z

tg
7
5
3

U20
SAS
2
SA9
4
SA10
6
SAll
S
SAl 2
11
SA13......l3
SA14
IS
SA15
17

lG
2G

74f244

SA16
'-SA17
SA1S
SA19

74f244

LA16........
LA17 J
LA1S__

GNO

lAl
lA2
lA3
1M
2Al
2A2
2A3
2A4

-lS
lYl 16
lY2 14
lY3 12
lY4 9
2Yl 7
2Y2 5
2Y3 3
2Y4

lG
2G

KAS
KA9
KAl0
KAll
KA12
KA13
KA14
KA15

...J

74f244

LA19-..J

S8Hu.:>

~
r RESET"";>
~-

[I~

U!!!U..>-

..,l!MEM.!!!.?

4
5

74fOS

1
..... MEMCS1Q.t-

3.".
U16A
74f125

2
GNO

SOO
SOl
S02
S03
S04
S05
S06
S07

2
3
4
5
6
7
S
9

~
Al
A2
A3
A4
AS
A6
A7
AS

~~
1 D1R

Vee

~
~

GNO

<]!l(0 .. 1a,..

SO(0 .. 15)

SOS
S09
SOlO
SOll
S012
S013
S014
SOlS

Bl
B2
83
B4
85
B6
B7
BS

~~
16
15
14
13
12
11

LOO
LOI
L02
L03
L04
LOS
L06
L07

!;;;;;;;;o

SDO
SOl
'-S02
S03
, - SD4
SD5
S06
S07

3
4
5
6
7
S
9
19

A2
A3
A4
AS
A6
A7
AS

B2 16
83 IS
B4 14
85 13
B6 12
B7Ji1
BSt'

L---t-2i1~1

74f245

~
Al
A2
A3
A4
AS
A6
A7
AS

~G
1

~
2~Al
Bl ~~

2
3
4
5
6
7
S
9

D1R

81
82
83
B4
85
B6
87
BS

LOS
L09
L010
tOl I
L012
L013
L014
LOIS

16
15
14
13
12
11

ro-

LD(0 .. 15)
LOB
L09
L010
LOI I
L012
L013
L014
L015

•

LOW S/16 81T
HIGH S 81T
1681T

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9
R1H
10k

292079

6-348

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i11'el

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Vee

MElli DEC!lDE &: SU.tt.t

L ~

#CE(O •• 7)

+SV
LA(0 .• 19)

#WRL(0 .• 3)

AEN

#WRH(0 .• 3)

.. " ..

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T(O •

#RD(0 •. 3)

P(0 .• 7)
W(0 •• 3)

OWS

16911N

BRDRST#

SMEMW#

StotEMR#

..--- I-

MEMDECODE#

GNDI~
GND

Vce

I/O DECODE &: Vpp

""L-- ~ +SV

Vpp

SA(0 .. 19)

lOR"

P(0 •• 7)

IOWN

W(0 •• 3)

AEN
RESET
10R#

AEN

BRDRST#

RESET

PD(0 .• 6)

100(0 •• 15)

16BIT#

RESET#

10DECOO[# •

~~GND

>
~

GND
~~

U13A

KAO

LOW 8/16 BIT
3

IOD[CODE#

'7:4132
U12A

U15A

~ H20~

MEMDECODE#

74F08

HIGH 8 BIT
12

~
U13B
1..--..

16 BIT
6

1681T#

292079-2

6-349

AP·343

100(0.. 7)
C' 1000..7

SW 01P-8

~
Vee
2 AI 91 ,,1!.!8;""'_1I SW91
! A2 92 :~
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1000

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5 A3 93
1004
6 A4 94
100S
7 AS 9S
1006
8:~:;
1007
9 A8 98
100
19 G

~
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IS
14
13
12
11

SW94
SW9S
SW96
SW97
SW98

GNO'h
GNO

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SW 01P-8

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1000
2
1001
3 AI 91
1002
4 A2 92
1003
S A3 93
1004
6 A4 94
1005
7 AS 95
1006
8 A6 96
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19 G

GNO

U29A
74F125
2
:5

BIOR#

17
16
IS
14
13
12
11

SW92
SW93
SW94
SW95
SW96
SW97
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+sv.i-J'
GNOlh
GNO

L.._ _ _ _...

OIR

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U299
74F125
6

'tn

910WN

131

VppEN#

74F08

GNO
SA(0 .• 19)
SA 0 .. 19

U31
SAO
SAl
SA2

YO ~
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13
Y2
12
Y3
11
Y4
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7
G29
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74F138

1
2
3

A
9
C

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f....§.(

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POETECT

PS2

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PSS

U30

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PI
P2
P3

---t~

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AEN

3
5
7
9
12
14
16
18

JP,:'Q:-;
JUMPER
JP5
P5

']MP~

JP~~
.r-iilMPER
GNO

"--+.HP4

SA3
SA4
SAS
SA6
SA7
SA8
SA9
SA10

PAGE-EN

.
....' PSO
PS
~ PS2
PS3

00
01
02
03
04
05
06
07
G
74F521

6-350

SWITCH9
Vee

" ' - -.... SW81
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- - - SWB3
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SWB5
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GNO'h
GNO

PO
PI
P2
P,l

Ap·343

1000
~
1001
4
1002
5
1003
6
1004
7
1005
8
1006
9
1007
102
19

SW 01P-8

~
AI
A2
A3
A4
AS
A6
A7
A8

18
17
16
15
14
13
12
11

81
B2
83
84
85
86
87
88

SW81
SWB2
SW83
SW84
SWB5
SW86
SW87
SWBB

U37

+5V I
GNO I

Vee

:--L L-.-J
nlR

~
AI Bl

18
17
16
15
14
13
12
"

A2 82
A3 B3
A4 B4
AS 85
A6 B6
A7 B7
ABB8

SWBI
SWB2
SWB3
SWB4
SWB5
SWB6
SWB7
SWB8

+5V I
GNOI

Vee

-:!o

....

3
4
5
6
7
8
9
19
. 1

A4
AS
A6
A7

18
17
16
15

rl4-

WO
WI
W2
W3

A2 B2
A3B3
A4 B4
AS B5
A6 B6
A7 B7
A8BS

rl*-

17
'6
15
14
13
12
"

PSO
PSI
PS2
PS3
PS4
PS5
PS6
PS7

g'R

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100(0••7)

'7ill"2

VppEN#

U408

RESET

5
~6

+5VI ~vcc

8RORST

8RORST#

GNOI~
GNO

74F32

f-l4.-

RESETI

RESET"
Vpp·

10W#

;:::tr)2-

WINDOW ADDRESS

(READ PAGE #)

VOLTAGE GENERATOR

U40A

~
Bl
82
83
84
85
86
97

£:~

AI
A2
A3

PSO
PSI
PS2
PS3
PS4
PS5
PS6
PS7

eLK
CLR

2~18

1000
1001
1002
1003
1004
1005
1006
1007

BIORII
lOW
VPPEN

2
3
4
5
6
7
8

g~ g~

U38

g'R

U32

2
5
:
12
15
16

02
03
04
05
06

74F273

SW OIP-B

£:"""7ill45

1000
1001
1002
1003
1004
1005
1006
1007

18
11
1

74F245

1000
2
1001
3
1002
4
1003
5
1004
6
1005
7
1006
8
1007
9
103
19

3 01
4 02
~ 03
13 04
14 05
17 06

..L

GNO

(WRITE PAGE #)

F01

1000
1001
1002
1003
1004
1005
1006
1007

W(O ••7)

WO •• 7

9A898~

GNO

OIR

74rns
PO(0 .. 6)

PS7

JPl

~M~:J

1000
1001
1002
1003
1004
1005
1006
1007

~JP2

JUMPER

PS6

JP3

PS4

JP4

~M~:J

JP7

~
4
5
6
7
8
9

~
AI
A2
A3
A4
AS
A6
A7
AS

91
92
93
84
95
B6
87
88

18
17
16
15
14
13
12
11

POD
POI
P02
P03
P04
P05
P06

P DETECT 19

£:""~
1

~MPER
PS4

PO 0 .. 6
PRESENCE
DETECT

g'R

P(0 ..7)
P 0 ..7

~M~:J
PS2

JP8

JUMPER

292079-4

6-351

AP-343

P(O ..71
SIIEIIRN

0 •• 1

1111

LAO
DE
U21
PO
Pl
P2
P3
P4
PS
P6
P7

P=.O

74r32

W 0 •• 3
2

00
01
02
03
04
OS
06
07

AEN
BRDRST

74r32

G
74rS21

74r32

SIIEIIW
BHE
16BIT

Vee
1

1
4

5
R2A
10k

R2B
10k
2

1
3
R2C
10k

8
R2D
10k

wo
WI
W2
W3
SW DIP-4

Vee

GND

crID--J
~

GND

292079-9

6-352

iniJ

AP-343

P(O 7)

U22
P3

A
B
C

i+Gl
G2A

MEMDECODE#

~G2B

GND

74F138
U24B

fl13

~4
lA
lB

3Y
4Y

LOW_BANK

HIGH_BANK

i, .....

MRD:

~
.:'I
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U28A
P6

::IT 3

A
B
G

YO
Yl
Y2
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74F139

A/B
~G
1

GND

YO
Yl
Y2
Y3

74F139
7

2B
3A
3B
4A
4B

A
B

YO
Yl
Y2
Y3
Y4
Y5
Y6

U28B

:n:

A
B
G

YO
Yl
Y2
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MWRHn
#WRH'~

74F139
U24A
P6

:n:

3
1-

A
B
G

Y1
Y2
Y3

.5
6

S'
'S2

74F139
JP10

JUMPER

LOW_BANK
HIGH_BANK

S2~8
I
I

S3~11

I
I

5(0 ..3)

74F32
292079-10

6-353

AP-343

coo(0 •. 15)

08
D9
DO
011
012
03
014
015

19
1

~
Al
A2
A3
A4
A5
A6
A7
A8

Bl
82
83
B4
85
B6
B7
B8

18
17
16
15
14
13
12
11

c
c
cD
cD
c
cO
cO
c

8
9
10
11
12
13
14
15

DO
01
02
03
04
05
06
07

glR

0 •• 15

4
5
6
7
8
9

..!!!....-

2 Al
A2
4
A3
5
A4
6
A5
7
A6
8
9 A7
A8
19
1 glR

18
17
16
15
14
13
12
87 11
88

Bl
82
83
84
85
86

c
c
c
c
cO
c
c

0
1
2
3
4
5
6
7

[~
IRD2

RD3
doo(0•• 15)

08
D9
010
011
012
013
014
015
T7

~~2
3
4
5
6
7
8
9
19
1

!!!..Al 81 j8
A282
...3 83
A4 84
A5 85
A6 86
A7 87
A8 88
glR

7m4s

17
16
15
14
13
12
11

d
d
d
d
d
d
d
d

8
9
0
11
12
13
14

00
01
02
03
04
05
06
07

4
5
6
7
8
9

~
"'1
A2
A3
A4
A5
A6
A7
A8

81
82
83
84
85
86
87
88

18
17
16
15
14
13
12
11

d
d
d
d

d
d

0
1
2
3
4
5
6
7

a
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0 ..

Vee

~========~T================

I IWEH(0 ..31
I IWEUO ..31

~~----------------------------------------------------------------------------------------(PI80.. 6)
I ,eE(O .•7l

I P(0 ..71

~
aND
292079-5

6-354

AP-343

p p p p p p p

ccccccc cccccc c c c
0000000 000000 ODD

DO 00000

0000000 000000 000

65 4 3 2 1 0

0123456 7 8 9 1 1 1 111
o 1 2 345

IrJ

KKK K K KKK K K K K

A A A A A A A A A A A A
o 1 234 5 6 7 8 9 11
o1

~I!I~

7 7 7 7 7 7 d7 7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 5
5 55 4 4 4 4 4 4 4 4 4
0987654321098765432109876543210987654321

8777777777766666666665~:J:J:J:J:J:J:J:>444"".j..j..j."

098765432109876543210987654321098765 4 3 2 1

.ij
SIMM CONNECTOR

111111111122222222223333333 3 3 3 4
123456789012345678901234567890123456 7 8 9 0

1 23
1

f----l

8191~P 1~I~PI~I,1

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3 3 3 4
1 2 2 2
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45617 89012345678
3 3 7 8 9 0
2

###

KKK
P P P A A A

## # # # # # #

RWW
DEE

C C C C C C C C
E E E E E E E E

2 H L
2 2

2 1

1 1
432

76 5432 1 0

P P P P P P P
DO 00000

65 432 1 0

dddddd ddddddd d d d
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KKKKKKKK KKK K
AAAAAAA A A A A A

012345 6789 1 1 1 111
o 1 2 345

0123456 7 8 9 1 1
o1

6 6 6 6 6 6666655
J877 7777
5 5 illl5 5 554444 44444
o 9 8 7654 32 77
1 0 9 8 7 6 5 4321098 765432 109876 5432 1
877777777776666666666555555555544444 4444
098765432109876543210987654321098765 4 3 2 1

J2
SIMM

CONNECTOR

111111111122222222223333333 3 3 3 4
123456789012345678901234567890123456 7890
112 3 4 5 617

## #

RWW
DEE

3 H L
3 3

8191~PI~I~lll~l~ ;

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1 1 22
3 3 3 34
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2 2
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#### # ## #

C C C C C C C C
E E E E E E E E

K K
p P P A AA

2 1 0 1 11
432

76543 2 1 0

GND

292079-6

6-355

inter

AP-343

aOa(O. lS)
~

4
5
6

011
012

A2
A3
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I
I

82
93
84

16
15
14

:gg~o

aDQll
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A2
A3
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82
83
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17
16
15

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93
95

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3
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J " 7.4f24s"

~----------------~

T 0 .. 7

1
1
1
31Rl0 21R1E 11Rlr 01R1G
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1
210k 310k " 10k S10k " 10k 10k
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7

I
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292079-7

6-356

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AP-343

p p p p p p P
D D D D D D D
6 5 4 3 2 1 0

a a a a a a a a

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a a a a

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7 7 7 7 7 7
7 7 6 6 6 6 6 6 6 6 6 6 5 5 5 5
5 5 5 4 4 4 4 4 4 4 4 4
0987654321098765432109876543210987654321

1877777777776666666666555555555'444444444
0987654321098765432109876543210987654321

"SlMM CO NNECTOR

1111111111222222222233333333334
1234567890123456789012345678901234567890
2 2 2 ~I~I~I~I;I*I~IW 3 6 7 8 9 K
Impl~p 7 8 9 0 2123456789012345

1 1 1 2

:........:...J

4 5 617 819161:

# # #

3 3 3 3 4

L L L
p P P A A A
2 1 0 1 11
4 3 2

# # # # # # # #

RWW
DEE
o H L
o 0

cccc

C c c C
E E E E E E E E
7 6 5 4 .3 2 1 a

P P P P P P P
DO DOD DO
6 5 4 3 2 1 0

b b b b b b b b b b bbbbbb
ODD 0 0 DOD D 0 000000

a a a a a a a a a a 0000 aa
o 1 2 3 4 5 6 7 8 9 111111
012345

~17

L L L L L L L L L L L L
A A A A A A A A A A A A
o 1 234 5 6 7 8 9 11
o 1

5~55

8 7 7 7 7 7
7 7 6 6 6 6 6 6 6 6 6 6 5 5 5
5 5 4 4 44444 44
7
o 9 8 7 6 5 4 3 2 1 0 9 8 7 6 54.3 2 1 o 9 8 7 6 5 4 .3 2 1 0 9 8 7 6 5 4 .3 2 1
8777777777766666666665555555555444444444
0987654321098765432109876543210987654321

J4
51M ...

CONNECTOR

1111111111222222222233333333334
1234567890123456789012345678901234567890
112 3 4 5 617 819161:

# # #
RWW
DEE
1 H L
11

I*I*I~

~I~I~I~I~I~I~I~IW

1 1 1 2
3 3 3 3 4
7 8 9 0 2
123456789012345
3 6 7 8 K K
2 2 2

#### ## ##

C C C C C C C C
E E E E E E E E
7 6 5 4 3 2 1 0

L
p P P A
2 1 0 1
4

L L
A A
11
32

GNo

292079-8

6-357

100(0••71

0= OFr
, =ON

~ VSW~14~

U42A

__. . .

Vpp

!'CSI

I'00

ral-

Vee

Rl1

GND

1.241<

GND

U29C

74ft25
GND

"'D

W
.a:o.

(.0)

Co)

IIASTER BOARD

.JUMI"t.1C

I I

JPll
O· 0

JUMPER

O=OFT
1 =ON

IOD.

"'.D PR

~.
Qt:"'".~-.--------CL

SLAVE BOARD
JP14

JP12

JUMPER

JUWPER

292079-11

AP-343

292079-13

Vee
Vee

RE
10k

--5

GND

-sWs1
SW82

~
SW84

~
SW86
~
~

1
1

1
2

1
0
Rf
10k

1
6

9
RG
10k

RH
10k

16
15
14
13
12
11
10
9

1
5
RA
10k

1
4
RB
10k

1
3
RC
10k

RD
10k

~
'E::.. H-

-==H-==-==r4-==- 104-==-14-==-==~

6-359

~
B

.l..
GND
292079-14

intJ

AP-343

I/O Port Usage for peAT
Range
Usage

Range

0390-0393h

Usage
Cluster (Adapter 0)

,oOOO-OOOfh

DMA Controller 1, B237 A

0020-0021h

Interrupt Controller 1, B259A

03aO-03a9h

BSC Communications (Primary)

0040-005fh

Programmable Timer, B254

03bO-03bfh

0060-006fh

Keyboard Controller, B042

Monochrome/Parallel Printer
Adapter

0070-007fh

CMOS Real-Time Clock, NMI
Mask

03cO-03cfh

EGA (Primary)

03dO-03dfh

CGA

00BO-009fh

DMA Page Registers, 74LS612

03fO-03f7h

Floppy Disk Controller

OOaO-00a1h

Interrupt Controller 2, B259A

03fB-03ffh

Serial Communications (COM 1)

OOcO-OOdfh

DMA Controller 2, B237 A

06e2-06e3h

Data Acquisition (Adapter 1)

OOfO-OOffh

Math Coprocessor

0790-0793h

Cluster (Adapter 1)

01f0-01fBh

Fixed Disk

Oae2-0ae3h

Data Acquisition (Adapter 2)

0200-020fh

Game Controller

Ob90-0b93h

Cluster (Adapter 2)

027B-027fh

Parallel Printer Port 2

Oee2-0ee3h

Data Acquisition (Adapter 3)

02bO-027dfh

EGA (Alternate)

1390-1393h

Cluster (Adapter 3)

02e1h

GPIB (Adapter 0)

2390-2393h

Cluster (Adapter 4)

02e2-02e3h

Data Acquisition (Adapter 0)

42e1h

GPIB (Adapter 2)

02fB-02ffh

Serial Communications (COM2)

62e1h

GPIB (Adapter 3)

0300-031fh

Prototype Card

B2e1h

GPIB (Adapter 4)

0360-036fh

PC Network

a2e1h

GPIB (Adapter 5)

037B-037fh

Parallel Printer Port 1

c2e1h

GPIB (Adapter 6)

03BO-03Bch

SDLC Communications

e2e1h

GPIB (Adapter 7)

6-360

Ap·343

ASSEMBLY LANGUAGE CODE FOR PAGED BOARD

,.***************************************************************************
jLocat1ng the Base I/O Address.
jBOARD_NOT_FOUND 1s an error procedure and 1s not shown.
BRD_IDO
dw 4 dup
' dw ?
Window_Base
Presence_Detect dw ?
VpPEN

ci.w

Page_Number

dw ?

mov dX,02FBh
KEEP_LOOKING:
add dx,B
cmp dx,31B
jg board_not_found
in al,dx
cmp al,ODh
jne KEEP_LOOKING

( ?)

jSet port pointer to 02FBH.
jFirst valid address after adding.
jPort pointer
B less than highest port address?
jHey, you forgot to install the board!!!

jRead port data into al register.
jDoes ,register
1st identifier value?
jNot equal Not located yet

inc dx
in al,dx
cmp al,OAh
jne KEEP_LOOKING

'jDoes register

= 2nd

identifier value?

inc dx
in al,dx
cmp al,Olh
jne KEEP_LOOKING

jDoes register

=3rd

identifier value?

inc dx
in al,dx
cmp al,OEh
jne KEEP_LOOKING
jFOUND-Good Job!
sub dx,3
mov BRD_IDO,dx

jDoes register
last identifier value?
JTOO BAD, you almost had it!
jRestored to base address.
jSave the value in RAM.
Locating the Base 110 Address

NOTE:
A review of BOB6 asembly language programming fundamentals might be necessary at this point.

6-361

AP-343

iLocating the Base Memory Address

i***************************************************************************
iThis Information is loaded into a segment register to access data

i***************************************************************************
mov ax,O
mov dx,Window_Base
in al,dx
mov bX,256
mul ax
mov eS,ax

iClear register
iPort pointer
1/0 to read base memory address
iRead port

iShifts address information left.
ies used as segment register for board.

6-362

inter

AP·343

;***************************************************************************
;Determining Memory Capacity

Density_Lookup_Table dw ?,?,Offfh,7ffh,03ffh
DENSITY dw ?
mov ax,O
mov dX,Page_Number
mov al,O
out dx,!11
mov dX,Presence_Detect
in al,dx
and al,23H
cmp al,20H
jng Skip_or
or al,4

;Clears register.
;Port pointer accesses page number.
;Wi"!. t~

Q. ;:~~c

t::

;~ge :l~!!!ber he..!'d1;l!e..!'~:

;Port pointer accesses presence detect pins.
;Clears all but density information.
;Checks if PD6 is set.
;If greater than 20H, set bit 2 of ale

;Go to density lookup table, translate value from PD pins, store in RAM
;variable DENSITY. Density value must be 2, 3, or 4 to be valid.
Skip_or:
cmp al,4
je okay
cmp al,3
je okay
cmp al,2
je okay
jmp Unknown_Device
;Invalid or no SIMMs present, routine not shown.
;Base address of density lookup table stored in bx register.
mov bX,offset Density_Lookup_Table
mov si,ax
;si register will be pointer into density table
;Density values for lM-4M, multiples of 1 Kbytes, stored in lookup table.
movax,[bx+si)
;Density read into ax register
mov DENSITY,ax
;Read the device identifier. Use the es segment register for the base
;address of the memory.
;28FOlO
OB4h,28F020
OBDh
mov aX,DENSITY
;Put RAM held density info into ax.
mov bX,l
;Write ID command.
moves:[bx),90H
;Read device identifier.
mov bX,es: [bx)
cmp bX,OB4h
je lMEG

Determining Memory Capacity

6-363

intJ

Ap·343

cmp bX,OBDh
je 2MEG
jmp Unknown_device

;If other t'han 28FOIO or 28F020.

;Divide SIMM density by component density to determine number of components
;on SIMM.
IMEG:
mov bX,3FFh
div ax
jmp NEXT_OPERATION

;Divide ax/bx, # of components stored in al.

2MEG:
mov bX,7FFh
div ax
jmp NEXT_OPERATION
;Read from the next SIMM location to verify its presence.
;As an example, assume that the SIMM's density is 1 Mbyte.
;A 1 Mbyte SIMM has 16 pages.
mov dX,Page_Number
mov al,16
;Switch to Page 16 for next SIMM location.
out dX,al
mov bX,l
;Write ID Command to first device of next SIMM.
mov ex: [bx] ,90H
mov ax,es:[bx]
;Read the identifier. Invalid data
empty socket
;Repeat the process for all SIMMs.

;***************************************************************************
Determining Memory Capacity (Continued)

6-364

APPLICATION

AB-25

BRIEF

May 1990

Designing In Flexibility With A
Universal Memory S,ite

DALE ELBERT

APPLICATIONS ENGINEERING

Order Number: 292061-001
6-365

DESIGNING IN
FLEXIBILITY WITH A
UNIVERSAL MEMORY SITE

CONTENTS

PAGE

INTRODUCTION ....................... 6-367
FLASH MEMORY TO EPROM/ROM ... 6-367
FLASH MEMORY TO SRAM ........... 6-368
FLASH MEMORY TO EEPROM . ........ 6-369
DESIGNING THE UNIVERSAL SITE ... 6-369
SUMMARY ............................ 6-369

6-366

inter

AB-25

INTRODUCTION
A universal memory site permits end-product flexibility
and cost reduction at product maturity. This application brief illustrates the design of a universal DIP site
that accepts Intel's ETOXTM flash memory, EPROM,
EEPROM, and SRAM.

Figure 1 illustrates the flash memory density upgrade
path for both 32-pin DIP and 32-lead PLCC configurations. -System designs using the 256 K-bit device can
increase memory capacity eightfold with no hardware
, change.

FLASH MEMORY-EPROM SITE
ETOXTM FLASH MEMORY
Intel's ETOX flash memory offers the most cost-effective and reliable alternative for read-write random-access nonvolatile memory. Flash memory adds electrical
chip-erasure and rewrite capability to EPROM density
and nonvolatility. Memory contents can be rewritten:
in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final
test; and in-system after sale. Flash memory increases
memory flexibility while contributing to time- and costsavings.
Flash memory is ideal for storing code and data tables
in embedded control applications where periodic updates are required. With extended cycling capability,
Intel flash memory also offers an innovative alternative
for mass storage.

In most systems, code is more volatile during the proto!jtp:::g !!::d e!!dy pr0~:h~~tif)n dHge~ of the system's life
cycle. EPROMs must be removed from the system for
replacement or reprogramming. EPROM updates are
labor intensive and hence expensive, adding cost to system design, manufacturing, and after-sale service. Other alternatives have been more costly or less reliable.
The remote update capability of flash memory simplifies updates. New code can be introduced over any serial communication line. No disassembly as such, many
designers have opted to use flash memory prototyping
and early production. As the system matures and code
updates cease, the balance of production can be converted to EPROM for further cost reduction when a
compatible memory site is used. This is the most costeffective approach, since flash memory equals EPROM
in density while its cost difference is far less than that of
manuaIly updating EPROMs.

Intel Flash Memory Products
Byte-Wide Flash Memory In 32-Pin DIP

Byte-Wide Flash Memory in 32-Pin PLCC

292061-2
292061-1

Figure 1. Intel Flash Memory DIP and PLCC Pinouts
6-367

AB·25

Figure 2 illustrates the jumpers necessary to convert
between 32-pin flash devices and 28-pin or 32-pin
EPROM devices. For 256K or 512K densities, jumpers
A, C, and F would be used for flash memory operation.
Jumpers B, D, and E would be used for EPROM.
Flash To EPROM
Vee
A15

vpp

Il·
-.J-C~

_ ..

J-A

_.J-B

A17

.
I

.1.

A12

J-E

In recent years, designers have turned to batterybacked SRAMs for flexible nonvolatile storage, especially in consumer-oriented or very price-sensitive designs. In, applications desiring updatable code or data
table storage, or data accumulation, flash memory offers a more dense, cost-effective, and reliable alternative
to battery-backed SRAMs.
The SRAM memory cell requires four or six transistors
to store a bit of information. Intel's flaSh memory employs a single transistor cell. As such, flash memory
garners an immediate density advantage. And since
density translates into cost-per-bit effectiveness, flash
memory is roughly one-half the price of the batterybacked SRAM solution.

J-D

-. - A16

FLASH MEMORY-SRAM SITE

J-F

292061-3

Figure 2. Flash Memory-EPROM DIP Site

The conversion is simpler for one-megabit and two-megabit densities as both flash memory and EPROM
share the 32-pin configuration. Jumper C would connect the Vpp supply for flash memory operation. Jumper D would route Vee to the Vpp pin for EPROM
read-only operation.
'
The write-enable trace used for flash memory can remain hard-wired. The PGM input to EPROMs is a
"don't care" for read opera,tions, when the voltage applied to the Vpp pin is between Vee and ground.
When PLCC EPROMs were first introduced, the packaging technology used leads 1 and 17 for mechanical
support of the die. Pins 1 and 17 were unavailable and
were labeled "don't use". As packaging technology
evolved, different means 'of mechanical support allowed
'
the use of leads 1 and 17.

Beyond the cost/density advantage, flash memory provides greater data integrity. Battery failure is unpredictable, resulting in system downtime and loss of critical
data. Eliminating the battery means eliminating battery
limitations-mechanical holders, special' a~cess required for battery maintenance, and limited durability
in harsh environments.
It is still useful to be able to design an SRAM/flash
memory-compatible site for a general-purpose memory·
board. This allows custom configuration of the memory
map = SRAM for working data (scratchpad) and flash
memory for non-volatile code and archival data storage.

Fignre 3 illustrates the jumpers required to reroute
A14, A15, and the write-enable signal. Jumpers A, C,
and F are used for flash memory operation. Jumpers B,
D, and E are used for SRAM.
Flash To SRAM
A15

Flash memory and one-megabit EPROMs use this newer packaging technology. In 32-1ead PLCC, as in the
32-pin DIP, flash is upgradable from 256K through
tWQ-megabits with no hardware change. However, a
conversion from 256K or 512K PLCC flash to a likedensity EPROM requires relayout of the board, as the
address lines and power supplies have a different orientation. At the 1M and 2M densities, the conversion is
quite simple and is the same as the DIP strategy. A
jumper removes V pp and applies Vee to the V pp pin
for EPROM re~d-only operation.
'

6-sea

A14

I.. 1.

.- -.I

-J-A

Vpp_

A16_

J-B

Vee

A12_

1
2
3
4

32
31
30
29

A15

A14

J-C

;;.;......

. _! ,.
-.- . . .1.\
-.- -. I

J-D

J-E

J- F
292061-4

Figure 3. Flash Memory-SRAM DIP Site

·...;._f
I.-.-e-

AB-25

FLASH MEMORY-EEPROM SITE

~ESIGNING

EEPROM has long-promised flexible, dense, and costeffective nonvolatile storage. EEPROM offers a high
degree of functionality-the ability to alter data on an
individual-byte basis. However, EEPROM is burdened
with high cost, low density, and erase/write cycling
wearout.

The site in Figure 5 combines the strategies in the previous sections and illustrates the design of a universal
site to accept flash memory, EPROM, SRAM, or
EEPROM. Table 1 is a pin-by-pin comparison of devices on each technology for use with the universal memory site.

The EEPROM memory cell consists of two transistors,
a floating gate lor charge storage ami a ~d"", 'iaii;;i;;tGr.
Intel's flash memory employs a single transistor cell.
Immediately, flash garners a density advantage. Again,
density leads to cost-effectiveness, making flash less
than half the price of EEPROM.

Universal

vee

FiashToE2

vee

A15

A14

.!.

.1.

A16

"-0

A12

J-A

Vpp

J-B

A14

32
2
r
I

,
I

ill

A12

2
3

32
31
30

1 1

Figure 5. Universal Memory Site

SUMMARY
This application brief has illustrated the hardware design steps needed to specify a universal memory stie
that accommodates Intel's flash memory, EPROM,
SRAM, and EEPROM. By designing memory sites for
mUltiple memory technologies, production can be easily
retrofitted to use the device that makes most sense during the different stages of the product life cycles or to
customize a general-purpose design for unique applications.

"_0 "_0
J-C

A16

292061-6

.I.
I

WE A15 A17 A14

A15 A14 Vpp

Often, the high level of functionality of EEPROM is
overkill for many applications. Designing the memory
site to accommodate flash, in addition to EEPROM,
allows manufacturing to easily switch to flash when
EEPROM functionality is not required or where like
the SRAM, it allows flexibility in combining EEPROM
and flash memory on a general-purpose memory board.
Figure 4 illustrates the jumpers required to reroute
A14, A15, and write-enable (256K only). Jumpers A
and D are connected for flash memory operation.
Jumpers Band C are used for 256K EEPROM operation. Jumpers A and D are used for one-megabit
EEPROM operation.

THE UNIVERSAL SITE

J-D

292061-5

Figure 4_ Flash Memory-EEPROM DIP Site

6-369

'SRAM

'EPROM
1M 512K 256K 2M

NC
Vpp
NC
A16
A16
A16
A14 A14 A15 A14 A15
A12 A12 A12 A12 A12

A16
A15 A15
A12 A12

Vpp

DIP Pin .,

' FLASH

1M 256K ,1M 256K :2M

FLASH

. EPROM

1M 512K 256K Number 256K 512K 1M ,·2M "256K 512K ' 1M

Vpp Vpp Vpp

Vpp

A16 A16 NC
Vpp' A15 ·A15 A15
A12 A12 A12 A12

NC
NC
A12

1
2
3
4

32
31
30
29

Vee Vee Vee Vee
WE WE WE WE
NC
A14

NC NC A17 Vee
A14 A14 A14 A14

E2
2M

Vee Vee
PGM PGM

Vee
A14

NC
A14

A17
A14

SRAM

256K 1M 2561<: 1M

Vee
WE

Vee
A15

Vee NC Vee CS2
WE A14 WE WE

Table 1. Pin Configurations by Technology and Density

'r'
c,,)
~

qJ
N

(J'I

ENGINEERING
REPORT

ER-20

September 1989

ETOXTMII Flash Memory
Technology

JASON ZILLER .

PRODUCT ENGINEERING

Order Number: 294005-006

6-371

ETOXTMII FLASH MEMORY
TECHNOLOGY

CONTENTS

PAGE

INTRODUCTION ....................... 6-373
ETOX II FLASH MEMORY CELL ...... 6-373
MEMORY ARRAY
CONSIDERATIONS ................. 6-373
ETOX II FLASH MEMORY
RELIABILITY ........................ 6-373
SUMMARY ............................ 6-374

6-372

ER-:20

INTRODUCTION

MEMORY ARRAY CONSIDERATIONS

Intel's ETOXTM II (EPROM tunnel oxide) flash memory technology is derived from the CHMOS" III-E
EPROM technology. It replaces ultraviolet erasability
with a non-volatile memory cell that is electrically erasable in bulk array form. Intel flash memory combines
the EPROM programming mechanism with EEPROM
erase, producing a versatile memory device that is highly reliable and cost effective. This report describes the
luUl.laljl~iitul.; Gf th~ ETOX I! !!:!sh !!!e!!!0!"y ('~11 in
comparison to the standard EPROM, and gives insight
into its operation in a system environment.

The ETOX II flash memory cells have the same array
configuration as standard EPROM, thereby matching
EPROM in density. Also, identical peripheral circuitry
for normal access achieves the same read performance
as the Intel CHMOS II1-E EPROMs.

The ETOX II flash memory cell is nearly identical in
size to CHMOS III-E EPROM. This allows comparable densities. The primary difference between ETOX II
flash memory and EPROM cells is the flash memory
cell's thinner gate oxide, which permits the electrical
erase capability. (See Photo 1.)

ETOXTM II FLASH MEMORY CELL
Intel's ETOX II flash memory cell is composed of a
single transistor with a floating gate for charge storage,
like the traditional EPROM. (See Figure 1.) In contrast, conventional two-transistor EEPROM cells are
typically much larger. Intel produces ETOX II flash
memory devices on 1.01l- photolithography.
The ETOX II cell's programming mechanism is identical to the EPROM; that is, hot channel electron injection. The device programming mode forces the cell's
control gate and drain to a high voltage while leaving
the source grounded. The high drain voltage generates
"hot" electrons that are swept across the channel.
These hot electrons collide with other atoms along the
way, creating even more free electrons. Meanwhile, the
high voltage on the control gate attracts these free electrons across the lower gate oxide into the floating gate,
where they are trapped. (See Figure 2.) Typically, this
process takes less than 10 Il-s.
Flash memory's advantage over EPROM is electrical
erasure, discharging the floating gate without ultraviolet light exposure. The erase mechanism is an
EEPROM adaptation which uses "Fowler-Nordheim'"
tunneling. A high electric field across the lower gate
oxide pulls electrons off the floating' gate. The erase
mode routes the same external voltage used for programming to the source of the memory cell, while the
gate is grounded and the drain is left disconnected.
(Figure 3.)

Intel flash memory's programming circuitry is also
identical to Intel's EPROM designs. Row decoders
drive the selected wordline to high voltage, while input
data combined with column decoders determine Lhe
number of bitlines that are gated to high voltage. This
provides the same byte programmability as an
EPROM. Intel flash memories offer the efficient QuickPulse Programming™ algorithm that is featured on
advanced EPROMs.
Array erase is unique to flash memory technology. Unlike conventional EEPROMs, which use a select transistor for individual byte erase control, flash memories
achieve much higher density with single transistor cells.
Therefore, the erase mode supplies high voltage to the
sources of every cell simultaneously, performing a full
array erasure. A programming operation must be performed before every erase to equalize the amou~t of
charge on each cell. Then Intel's Quick-Erase™ algorithm intelligently erases the array down to the appropriate minimum threshold level required to read all
"ones" data. This procedure ensures a tight distribution
of erased cell thresholds throughout the array.

ETOXTM II FLASH MEMORY
RELIABILITY
The reliability of Intel's CHMOS ETOX II flash memory process is equivalent to its sister EPROM technology. The ETOX II and EPROM processes share the
same data retention characteristics. Preliminary qualification data shows that 1 Megabit flash memories produced on the ETOX II process provide at least 10,000
program and erase cycles with no cycling failures due
to oxide stress or breakdown. In fact, several 1 Megabit
flash memories were cycled past 100,000 cycles with no
apparent oxide damage. This extended cycling capability is attributed to improvements in tunnel oxide processing and advantages inherent in the ETOX II cell
approach.

1M. lenzlinger, E.H. Snow, "Fowler-Nordheim Tunneling into Thermally Grown Si02," Journal of Applied Physics, Vol. 40
(1969), p. 27B.
*Intel's ETOX II flash memory process has patents pending.
**CHMOS is a patented process of Intel Corporation.

6-373

ER·20

development and manufacturing stages. Also, flash
memory density is ideally suited for applications requiring version updates of entire programs which,' in turn,
suit the "flash" characteristics of erasing the entire array at once. In addition, individual byte programming
allows for data acquisition. Flash memory devices produce on the ETOX II process provide a high density,'
low cost solution to many system memory storage requirements which were previously unavailable.

SUMMARY
ETOX II flash memory technology is the optimal combination of EPROM and E2PROM technologies. Intel's new ETOX II flash memory process offers extended cycling capability with the density and manufacturability of EPROMs. From an application standpoint,
flash memory technology provides the capability to
improve overall system quality throughout the product

Table I

EPROM

ETOXTMII Flash
Memory

EEPROM

1.0

1.2-1.3

3.0

Resolution
Typ. Time

Hot Electron
Injection
Byte
< 100 ,","S

Hot Electron
Injection
Byte
< 10 ,","S

Tunneling
Byte
5ms

Erase:
Mechanism
Resolution
Typ. Time

UV Light
Bulk Array
20 Min.

Tunneling
Bulk Array
< 1 Sec.

Tunneling
Byte
5ms

Normalized Cell Size
Programming:
Mechanism

294005-1

Figure 1. ETOXTMII Flash Memory Cell Layout (Top View)

294005-2

Figure 2. ETOXTMII Flash Memory Cell during Programming (Side View)

6-374

ER-20

294005-3

Figure 3. ETOXTMII Flash Memory Cell during Erase (Side View)

PHOTO 1

294005-4

294005-5

ETOXTMII Cell

CHMOS III-E EPROM Cell

(50,000 x Magnification)

6-375

· ENGINEERING
REPORT

ER-24

October 1990

The Intel 28F010
Flash Memory

Order Number: 294008-004

6-376

THE INTEL 28F010
FLASH MEMORY

CONTENTS

PAGE

INTRODUCTION ............ : .......... 6-378
TECHNOLOGY OVERVIEW ........... 6-378
DEVICE ARCHITECTURE ............. 6-378
DEVICE RELIABILITy ................. 6-379
- ••••••• P'tI"

~UlVlm""n

•

~ 'JRn
. •••••••••••••.••••••.•••••• _- __ _

•
6-377

inter

ER-24

INTRODUCTION

DEVICE ARCHITECTURE

Intel's ZSFOI0 ETOXTM II (EPROM tunnel oxide)
flash memory adds electrical chip erasure and reprogramming to EPROM'non-volatility and ease of use.
Advances in tunnel oxides and photolithography have
made it possible to develop a double-polysilicon singletransistor read/write random access nonvolatile memory, capable of greater than reprogramming cycles (typical 100,000). The 2SFOI0 flash memory electrically
erases all bits in the array matrix via electron tunneling.
The EPROM programming mechanism of hot electron
injection is employed for electrical byte programming.

Command Port
One feature which differentiates Intel's one-megabit
flash memory is the command port architecture, illustrated in Figures 2 and 3.
The command port simplifies microprocessor control of
the erase, erase verify, program, program verify, and
read operations, without the need for additional control
pins or the multiplexing of high voltage with control
functions. On-chip address and data latches minimize
system interface logic and free the system bus during
erase and program operations. High voltage (12V) on
the Vpp pin enables the command port. In the absence
of this high voltage, the command port defaults to the
read operation, inhibiting erasure or programming of
the device.

A command port interface, internal margin voltage
generation, power up/down protection and address and
data latches augment standard EPROM circuitry to
optimize Intel's 2SFOI0 for microprocessor-controlled
reprogramming.
Read timing parameters are equivalent to those of
CMOS EPROMs, EEPROMs, and SRAMs. The
120 ns access time results from a memory cell current
of approximately 50 /LA, low resistance poly-silicide
wordlines, advanced scaled periphery transistors, and
an optimized data-out buffer.

EPROM Cell
SECOND LEVEL
+VG
POLYSILICON '\. "'~

... 'It

The dense one-transistor cell structure, coupled with
high array efficiency, yields a one megabit die measuring 225 by 265 mils.

FIRST LEVEL
POLYSILlCDN
(FLOATING)

+Vo

Yl f I:E

GATE OXIDE

32SX

N+

P-SUBSTRATE

294008-1

TECHNOLOGY' OVERVIEW
Flash Memory Cell

Intel's ETOX II flash memory technology is derived '
from its standard CMOS EPROM process base. Using
advanced 1.0 /Lm double-polysilicon n-well CMOS
technology, the 131,072 x S bit flash memory employs a
3.S /Lm x 4.0 /Lm single transistor cell, affording equivalent array density as comparable EPROM technology.
The flash memory cell structure is identical to the
EPROM structure, except for the thinner gate (tunnel)
oxide. Figure 1 compares the flash memory cell to the
EPROM cell.
High quality tunnel oxide under the single floating
polysilicon gate promotes electrical erasure. All cells in
the array are simultaneously erased via FowlerNordheim tunneling. Applying 12V on the sourcejunctions and grounding the select gates erases the entire
array in one second (typical). Programming is accomplished with the standard EPROM mechanism of hot
electron injection from the cell drain junction to the
floating gate. Programming is initiated by bringing both
the select gate and the cell drain to high voltage. Programming occurs at a rate of 10 /Ls pulses per byte.

P-SUBSTRATE

294008-2

Figure 1. EPROM Cell vs. Flash Memory Cell

The command port consists of a command register,
command decoder and state latch, the data-in latch,
and the address latch. The command decoder output
directs the operation of the high voltage flash-erase
switch, program voltage generator, and the erase/pro·
gram verify voltage generator.
Functions are selected via the command port in a mi·
croprocessor write cycle controlled by the Chip-Enable
and Write-Enable pins. Contents of the address latch
are updated on the falling edge of Write-Enable. The
rising edge of Write-Enable latches the command and
data registers, and initiates operations.

6-378

ER-24

DEVICE RELIABILITY

Erasure
Erasure is achieved through a two-step write sequence.
The erase set-up code is written to the command register in the first cycle. The erase confirmation code is
written in the second cycle. The rising edge of this second Write-Enable pulse initiates the erase operation.
The command decoder triggers the high voltage flasherase switch, connecting the 12V supply to the source
of all bits in the array, while all wordlines are grounded. Fowler-Nordheim tunneling results in the simultaneous erasure of all bits.
The array source switch, shown in Figure 4, switches
high voltage onto the source junctions. During erasure,
the high voltage latch formed by MS through M8 enables transistor MIS. Transistor MIS pulls the array
source up to 12V. Transistor Ml6 pulls the source to
ground during read and program operations.
To obtain fast erase times, the device .must supply the
grounded gate breakdown current which occurs on the
sources of the memory array. The upper boundary for
current sourcing capability of MIS is set by the maximum allowable substrate current. If Vpp is raised to
12V before Vee is above approximately 1.8V, the low
Vee detect circuit formed by transistors Ml to M4
drives the node LOW Vee to 9V. Transistors M9 to
M II then force the erase circuit into a non-erase state
with Ml5 off and Ml6 on. When Vee rises above 1.8V,
the chip will be reset into the read state.
Writing the erase verify code into the command register
terminates erasure, latches the address of the byte to
verify, and sets the internally-generated erase margin
voltage. The microprocessor then accesses the output
from the addressed byte using standard read timings.
The verify procedure repeats for all addresses. Should a
byte require more time to reach the erased state, another erase operation is applied. The erase and verify operations continue until the entire array is erased.

Programming
Programming follows a similar flow. The program setup command is written to the command register on the
first cycle. The second cycle loads the address and data
latches. The rising edge of the second Write-Enable
pulse initiates programming by applying high voltage to
the gates and drains of the bits to be programmed.
Writing the program verify command to the register
terminates the programming operation and applies the
program verify voltage to the newly programmed byte.
Again, the addressed byte can be read using standard
microprocessor read timings. Should the addressed byte
require more time to reach the programmed state, the
programming operation and verification are repeated
until the byte is programmed.

Cell Margining
Erase and program verification ensure the data retention of the newly altered memory bits. The cell margining performed in the Quick-Pulse Programming™ and
Quick-Erase™ algorithms is more reliable than historical overpulsing schemes as margining tests the amount
of charg~ StU! eu uu ihc fluatiiig gat;:.
Intel's flash memories employ a unique circuit to internally generate the erase and program verify voltages.
Figure 5 shows a simplified version of the circuit. The
circuit consists of a high voltage switch and the verify
voltage generator. Transistors Ml through ¥4 constitute the high voltage switch which disconnects Vpp
from the resistor when the device is not in the verify
mode. The verify voltage generator includes a resistor
divider and a buffer. Internal margin voltage generation
maintains microprocessor compatibility by eliminating
the need for external reference voltages.

Erase/Program Cycling
One of the most significant aspects of the 28FOIO is its
capability for a minimum of 10,000 erase/program cycles (typical 100,000). Destructive oxide breakdown has
been a limiting factor in extended cycling of thin oxide
EEPROMs. Intel's ETOX II flash memory technology
extends cycling performance through: improved tunnel
oxide processing that increases charge carrying capability ten-fold; reduced oxide area under stress minimizing
probability of oxide defects in the region; and reduced
oxide stress due to a lower peak electric field (lower
erase voltage than EEPROM).
A typical cell erase/program margin (Vt) is shown as a
function of reprogramming cycles in Figure 6. After
10,000 reprogramming cycles, a 2.5V program read
margin exists, ensuring reliable data retention. Accelerated retention bake experiments, for devices cycled
10,000 times, show minimal program Vt shift.
Reliable erase/program cycling also requires proper selection of the erase Vt maximum and maintenance of a
tight Vt distribution. The maximum erased Vt is set to
3.2V via the erase algorithm and the internal erase verify circuits. Superior oxide quality gives an erased Vt
distribution width that improves slightly with cycling
(Figure 7). The tight erase Vt distribution gives an order of magnitude of erase time margin to the fastest
erasing cell (Figure 8).

6-379

intJ

. ER-24

Figures 9 and 10 illustrate typical programming performance as a function of cycling, temperature, and
Vpp. Figures 11 and 12 depict typical erase performance as a function of cycling, temperature, and Vpp.

ty EPROM technology. Intel's 28F01O CMOS flash
memory offers the most cost-effective and reliable alternative for read/write random access non-volatile
memory. Microprocessor-compatible specifications,
straightforward interfacing, and in circuit alterability
allow designers to easily augment memory flexibility
and satisfy the need for nonvolatile storage in today's
designs.

SUMMARY
Intel's ETOX II flash memory technology is a breakthrough in adding electrical chip-erasure to high-densi-

Vee

Vss

---.
---.

vpp

I
---.

CE
OE

~I ERASE VOLTAGE
SWITCH

STATE
CONTROL
COMMAND
REGISTER
INTEGRATED
STOP TIMER

T I

'I
TO ARRAY
SOURCE

I-

[.hr

PGM VOLTAGE
SWITCH

CHIP ENABLE
OUTPUT ENABLE
LOGIC

+
STB
-A'6

Y-DECODER

~...
C/1

I:J
a:

X-DECODER

0
0

STB

rr-•
••
r-•

Figure 2. 28F010 Block Diagram

CE--..r::~:.:l

WE--"1..;;:::::.J

DATA

REPROGRAMMING
CONTROL CIRCUITS

Figure 3. Command Port Block D_iagram

6-380

INPUT/OUTPUT
BUFFERS

~
~

DATA
LATCH

Y-GATING

',048,576 BIT
CELL MATRIX

~
294008-3

--t_f

irl-e-

ER-24

ARRAY
SOURCE

ERASE--~------------+-----------------~

294008-5

Figure 4. Array Source Switch

Vpp

.-_~Verlfy

Voltage
Enable>-------~

High Voltage Switch

Verify Generator
294008-6

Figure 5. Erase/Program Verify Generator

6-381

inter

ER-24

10.5

7.5

PROGRAM Vt MAX

PROGRAM Vt MIN

PROGRAM READ MARGIN

Vee MAX

-> 4.5 -

Vee MIN

ERASE Vt MAX

ERASE READ MARGIN

ERASE Vt MIN

1.5 i--

o
10

100
10000
1000
NUMBER OF CYCLES

100000

1M
294008-7

Figure 6. 1M Array Vt vs Cycles

99.99
99,9
~

1111
'-"

'"'
!:l
II<

()

'"'
'"'

..J
..J

'"',
~

0,1

()

0.01
0.001
0
ERASE Vt (VOLTS)

Figure 7. Erase Vt Distribution vs Cycling

6-382

294008-8

8
7.5
7
6.5
6
5.5
5
4.5
0
4
~
:> 3.5
3
II)
...:
II<
2.5
2
1.5

g
...
...

. FAST ERASE BIT

0.5
0

ERASE TIME (mS)

294008-9

Figure 8. Array Erase Vt vs Erase Time

99.9

v
V-

70
III

...
II<

::E
:::>
(.)

,
~

" ,
/ ,,
, ,,
II' ,,

SO
40

,I'

",
,,/,
,
,
.f./
' "
~' "
.(./

V, ,",
,

..,,.

20
10
5

0.1
2

2.5

33.544.55

Chip Program TIme (Sec)
~ 12V; 10 kc; 23C
- ••••• -11.4V; .10 kc: 70C
-~.- 12V; 100 kc; 23C

Figure 9. 28F010 Typical Programming Capability

6-383

294008-10

ER-24

!:l
en

s.s

"0=~ 4S

/
V

•

3.5

2!J

......" ,
~

,
,,

<10

...

-" ./

'l"

.•""

,"
J

IKl

100

110

120 130

TEMP (C)
- - l k Cycle.
----10k Cycl..
----- lOOk Cycl••

294008-11

Figure 10_ 28F01Q Typical Program Time at 12V

,,;.,.. ,

99.9

,'/

, ..'

~
95
90
SO

Ii...!

60
50

V , .'
'

I , '/
I ,"
I '7

a 30

I '

1 .1
II!

10
5

I ,I,."
';

2srOlO-200

I-

o.I
0.5

2srOI0-120/150

0.7

5 6 7 S 9 10

CHIP ERASE TIME (SEC)
------

------

12Y; 10 kc ;23C
11.4V; 10 kc ;OC
12Y; 100 kc ;23C

Figure 11. 28F010typicai Erase Capability
-6-384

294008-12

inter

iER-24

3.2
3.0

2.8

,'~
'~

2.6

...
...

2.4

(/I

~
;:: 2.2

...
...~

(/I

2.0

D..

:f
0

1.8
1.6

r-o...

1.4

I\~

"'" ~.

"'-

"',

'", i'o.

"'~

I'-... ......

i"....

1.2
1.0

'" ""
~

1"....

.... ~...

~ r-....

.........
r-- •

i"""--

90 100 110 120 130 140

TEMP ("C)
-lkCycles
- - - - 10k Cycles
._--- lOOk Cycles

Figure 12. 28F010 Typical Erase Time at 12V

6-385

294008-13

inter

ER·24

294008-14

Figure 13. 28F010 Die Photograph

ER-24

28F010

.r.[.[ J: ~I~

A14
A 13

A6
AS

281'010

32-LEAD PLCC

0.450" X 0.550"

A11

TOP VIEW

Ala

A"0

007

000

..,

.....

g g ::' g g g g

notto scale
29400B-16

29400B-15

Pin Names
Ao-AI6

Address Inputs

000-DQ7

Data Input/Output

Chip Enable

Output Enable

Write Enable

Vpp
Vee
Vss

Program/Erase Power
Device Power
Ground

Figure 14. 28F010 Pin Configurations

6-387

ER·24

Columns are number 0 through 511 beginning with the column nearest the X-decoder.
Outputs are grouped as follows:
Left Half Array
100101 102 103
BL384- BLo

Array Organization:
Address
A16
0
0
0
0
0
0
0
0

A1S
0
0
0
0
0

1
1
1
1

•

0
0

•

Right Half Array
104 lOs 106 107
BLo- BL384
Bltllnes

A10
0
0
0
0
0
0
0
0

A2
0
0
0
0
0
0
0
0

A1
0
0
0
0
1
1
1
1

Ao
0
0
1
1
0
0
1
1

A3
0
1
0
1
0
1
0
1

100& 107

101 & 106

102& lOs

103& 104

BLa84
BLa85
BLa86
BLa87
Bl388
BL389
BLa90
Bl391

Bl256
Bl257
Bl258
Bl259
Bl260
Bl261
Bl262
Bl263

Bl128
Bl129
Bl130
Bl131
Bl132
Bl133
Bl134
Bl135

BLo
Bl1
BL2
Bl3
B4
Bl5
BLa
Bl7

1
1

1
1
1
1

0
0

0
1
0

Bl508
BL509
Bl510
Bl511

Bl380
BLa81
Bl382
Bl383

Bl252
Bl253
Bl254
Bl255

Bl124
Bl125
Bl126
Bl127

•

1
1

•

1
1

•

Figure 15. Bltllne Decoding
X Address
A14

A12

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

A7
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

Row

A13

A11

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
'0
0
0
0
0

0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0

1
1
1
1
1
1
1
1
1
.1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
0
0
0
0
1
1
1
1

0
0
0
0
0
0
0
0

Figure 16. Wordllne Decoding

6-388

1
1
1
1

0
0
0
0

A9
0

0
1
1
0
0
1
1

0
0
1
1
0

0
1
1
1
1

0
0
1
1
0

0
1
1
0
0
1
1

0
0

A8
0
1
0
1

0
1

0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

WL
XLo
XL1
XL2
Xl3
X4
Xl5
XLs
Xl7
Xl8
Xl9
Xl10
Xl11
Xl12
Xl13
Xl14
Xl15
Xl16
Xl17
Xl18
Xl19
Xl20
Xl21
Xl22
Xl23
Xl24
Xl25
Xl26
Xl27
Xl28
Xl29
XLao
Xl31

inter

ER-24

X Address

A11
0

A13
0

A12
0

A7
0

A6
0

•

•
•

•

XL47

XL48

•••

XL63

XL64

XL79

XL80

•

•••
•••

•
1

XL95

XL992

XL1007

XL1008

•
1

•
•

•

•
1

•
•

•

XL32

•

As
0

•

Row

A4
0

A14
0

•

•
•

•••
•••
•••

XL1023

Figure 16. Word line Decoding (Continued)
BitMap for
One Output

Array Organization

.---.---.---~-.

.---,---,---,--.

WLO
WL1
WL2
WL3

S
E 1100 1/01 1/02 1/03

1104 1/05 1/06 1/07

L
E
C

•
•
•

WL1020
WL1021
WL1022
WL1023

T
S
COLUMN SELECTS

BLO BL1 BL2 ... BL127

Figure 17. Bit Map

6-389

ARTICLE
REPRINT

AR-463

DOII'T WRITE OFF THE U. S. III MEMORY CHIPS!

The Japanese may own the dynamic RAM world,
but the Americans are taking the lead in what
ultimately may be the more important technology

on't be too quick 00 write off the
Americans in semiconducoor memories-a business that's by far the big.
gest chip market going these days. The
longer-term memory picture is definitely turning brighter for U. S. chip makers. This dramatic turnabout wasn't the
subject of any paper or panel at the
recent International Solid State Circuits
Conference. But it was the biggest story, as far as senior technical edioors
Sam Weber and Stan Runyon were concerned, at a meeting they had already
. labeled the strongest ISSCC ever.
seems clear that American memory technology now has
a good .shot at making a surprising and perhaps overwhelming comeback. While many foreign governments and corporate giants were investing hundreds of millions of dollars in
chip plants 00 tum out millions of low-cost, low-profit dynamic
RAMS, several U. S. semiconducoor houses have been working
quietly for several years 00 develop a new kind of memory
that now stands an excellent chance of eclipsing the dynamic
RAM's influence on computer design.
The potential of this new challenger, called the flash memory, is staggering (see p.47). If the new class of memory
moves inoo volume production as expected-and there seem
00 be few technological reasons for it not to-it wiil be
denser, maybe faster, and more reliable than any other type
of semiconducoor memory. Flash memory ·not only will resoore the memory-chip leadership 00 the U. S. if it pans out as
we think it will, but also will radically alter computer architecture. It will likely displace magnetic disks for program soorage as well as allow computers 00 be designed with all nonvolatile memory. The potential of the dense flash memories is
so vast that Intel, which has been working hard on flash
processes for four years, has decided 00 fold its triple-poly
EEPROM program and concentrate instead on flash.
Flash may also be arriving just in the nick of time. Despite
the glamour of reaching I6-Mbit parts, the dynamic RAM is
running out of steam in density improvement. Trench capacioors and other processing and circuit tricks are troublesome
and require painstaking care in processing. Flash memories,
on the other hand, can be made with one-transisoor cells, are
highly scalable, and do not need elaborate engineering. While
the Japanese may own the dynamic RAM world, the U. S. is in
a strong position 00 take the lead in what ultimately may be
the more important memory technology. ROBERT W. H. .KIIL
@

1988, Reprinted with permiSSion' from ELECTRONICS,
a McGraw-Hili Publication, March 3.' 1988.

Electronics/March 3. 1988

6-390

MARCH 3 1988

PROBING THE NEWS
HIGH·DENSITY FLASH EEPROMS ARE ABOUT
TO BURST ON THE MEMORY MARKET
They could end up being the dominant low·cost, high·density memory
by J. Robert Lineback

9he market is about to be hit with a
• wave of new electrically erasable nonvolatile memory chips that may soon
match the bit density of dynamic randomaccess memories. This emerging breed of
programmable read-only memories-built
with single-transistor cells and called
flash EEPROMs-could pack 64 Mbits on
a chip by the turn of the century.
At least a half dozen silicon merchants-among them such giants as Intel, National Semiconductor, Texas Instruments, and Toshiba-are working
on flash EEPROMs, using a variety of
cell layouts (see figure). First out of the
gate will be a CMOS 512-Kbit flash EEPROM, coming this month from Seeq
Technology Inc. in San Jose, Calif.
Right on Seeq's heels is Intel Corp.,
which has developed what executives
will only say is a significant "process
trick" for its flash parts that allows it to '
use the same design as in its ultraviolet
erasable PROMs.
RADICAL CHANGE. Intel believes that by
the year 2000, flash memories will
emerge as the low-cost, high-density
champion memory. If they are right, flash
EEPROMs could radically change systein
architectures, making it po~sible to build
computers with all-solid-state memory
systems. The flash EEPROMs would be
the only direct-access mass storage in the
system, replacing disk drives feeding
DRAM-based main memory.
Flash memories are a marriage of
conventional EEPROM and EPROM
technologies, offering the high densities
of EPROM thanks to one-transistor
cells. The write operation is like that of
EPROMs, using hot-electron injection.
The erase operation borrows the mechanism of floating-gate EEPROMs-electrical erasure by cold-elec.tron tunneling.
Most full-featured EEPROMs have
two-transistor cells and can reprogram
individual bytes one at a time. In contrast, the entire contents of flash-EEPROM arrays are erased quickly and simultaneously. The flash memory trades
selective-erase capabilities for space-saving single-transistor cells.
"Flash" also describes the way the new

memory's market segment IS expected to right away. Nor will they cut quickly into
grow, surging from near nothing today to EEPROM sales. Right now they pose a
over $1 billion in the early 1990s (see real threat to EPROMs. Because of their
chart, left). The lIash movement has be- high cost, conventional EEPROMs did
come so explosive that market researcher not, as some thought they would, push
Dataquest Inc., San Jose, Calif., is wait- EPROMs out of the market Flash EEing for key product unveilings before it PROMs, however, could succeed where
, . . . - - ' - - - - - - - - - - - - - - , full featured EEPROMs failed.
Although flash has tremendous
market potential, vendors are being
cautious about projections. "There
will be room for all three types of
3,000,...------------,
nonvolatile memory: flash, UVEPROM, and full-featured EE01988
PROM," says Mike Vilott, vice presi.. 2.500f--f--.,1992dent of marketing at Seeq. ''There is
z
a slight price and space penalty for
co
::;
flash, but there are also benefits."
~2.000r-The benefits are electrical erasability
and the ability to test parts, which
f(l
*
can not be done for EPROMs in
r~1.500~
cheap windowless packages.
w
c
Two styles of flash memories are
~ I,DOOrbeing developed by most suppliers .
...II:
One is aimed at EPROM sockets,
il 500fother at price-sensitive EE~ r- the
PROM jobs that don't require byte
erasure. Seeq ,is working on products in both styles.
0'- ....UV L . Q . h S H ' EPROM
FEATURED
EEPROM
Seeq, the first company to move
EEPROM
flash EEPROMs into the marketlI'IIjBE.sT.,c.A.sEiiis.cEiiiNAiiiRiiiloii'_ _~_.so_uRiiiciiE'.DAiiT.AQ.U.".T place with an nMOS part [Electronwill venture any formal forecasts of the ics, Aug. 21, 1986, p.53], uses a splitbusiness's growth. ''We have made some gate layout. The top layer of polysilicon
initial estimates that show it could repre- forms the control gate, slopping down
sent a third of the total nonvolatile area over a portion of the channel to form a
[by 1992], if all of the companies we think select device. The folded-structure cell
are going to be in the business are actual- takes up about 10% more space than a
ly in volume production," says Mary Ols- conventional EPROM cell, says Gary
son, an industry analyst at Dataquest
Rauh, strategic marketing manager at
The potential density of EEPROMs is Seeq, which will use its split-gate design
what has got everyone excited. DRAMs in the CMOS flash memories being intraare hitting a density barrier, says Bruce duced later this month.
McCormick, product marketing manager
Allied with Seeq and also working on
at Intel-'-it is getting harder and harder the design of the two lIash families is
to reduce the space needed for the capaci- National Semiconductor Corp. The pact
tors that store charge in each cell to re- between Seeq and 'National, signed last
tain data: Many lIash-memory proponents fall, is aimed at establishing feature-set
agree. They see nothing but problems for standards quickly in the emerging marDRAM makers trying to push 'the density keto They need to move fast; coming up
of their parts in coming years.
behind them are a host of major semiMost observers also agree, though, that conductor merchants, notably Intel.
lIash parts will not threaten DRAMs
Managers at Intel won't say much

A.IIGHT OUTLOOK
FOI FLASH EEPROMS

Electronlcsl March 3, 1988

6·391

.-10

tion. "When yoll get out into fu'ture generations, there might be
a slight si•.e' penalty, but today it
~
~ is zero. We think we see ways of
I!'"
holding the size' difference between future EPROM cells and"
flash memories to about 'lffo,"
says Pllshley.
Also moving in is Toshiba
,";,
Corp. The Kawasaki, Japan,
'••1" .
company says it has begun se~:":"';"';'----------'---~"-;-"-;...;I.f lectively providing samples of
256-Kbit nMOS flash parts,
which are based on a complex
triple-level polysilicon structure
using a relativel:{ thick gate oxide region (500 A). Toshiba officials decline to say when parts
1-';,;;b.:,.I_ _ _.......;.._ _ _ _ _..;..______-t will become widely available,
but observers believe the firm is
working on a new CMOS design
based on a recently disclosed
NAND structure that shrinks
cell size by some 30%. .
And Hitachi Ltd. of Tokyo is
also .pursuing flash memory, specifically a 1-Mbit chip. Like Intel,
Hitachi eliminates the select transistor to build a small cell, but its
is different,
.._____________-.1 approach
double-diffused
profile using
in thea
"I'IIBI!II!
1__ .

~..

eu EEPIOII .
_LD
A ...
_ _.........
_.........
________

Intel ........ gates (a), Seeq extends a gate over the source and drain regions of the
channel (b). Toshiba uses a three-level layout (c),
channel to prevent leakage.
Despite all the activity in
about the process fiddling they've done, flash EEPRO Ms, and the evident interexcept that it makes it possible to use est of major semiconductor companies,
an EPROM structure in flash memories. not everyone thinks they're the wave of
More than 100,000 256-Kbit chips have the future. At Xicor Inc., fOf example,
been produced at Intel's newly renamed executives continue to believe that fullFlash Memory Operation in Folsom, featured EEPROMs will be the EECalif., say managers there, and the new PROMs of choice. ''There are limits on
technique has helped Intel reach tight . write-erase Cycles, and standards are
voltage-threshold margins in arrays. not well defined when it comes to proControl over the margins means Intel gramming voltages," points out Krish
can make flash memories with cells that Panu, Xicor marketing manager. "Some
are very similar to those used in its people are talking 21 y; others 12 V.
high-density UV-EPROMs. The principal But how long will it be before they have
difference between Intel's flash EE- I).V-only flash parts?" he asks. Xicor
PROM and its EPROM is that the gate will use its thick-oxide technology to inoxide is thinner-100 Ainstead of 350 A. troduce a 1-Mbit full-featured I).V EEAt the 256-Kbit level, the cell size of PROM by the year end.
Although most flash proponents agree
Intel's flash is exactly the same as its
EPROM, says Richard Pashley, general that I).V programming would be an atmanager of Intel's Flash Memory Opera- tractive feature, many believe it is not
tion. Many competitors' cells are larger- worth the price of adding charge-pumping
they have had to modify stacked-gate cir- circuitry to each chip. Still, several firms
cuit layouts to emulate the effects of are reportedly exploring I).V flash parts.
phantom select devices. The devices pre- Topping the list of those rumored to be
vent error-generating current leakage and doing so is TI, which wm only confirm
maintain voltage thresholds.
that it is working on products based on
Intel executives will not talk about its its Array Contactless EPROM technoltimetables for specific product inirodue- ogy [Electronics, Nov. ZT, 1986, p.70].
tions, but they're promising big things Managers at its nonvolatile memory operahead. ''We are confident that our tech- ations in Houston believe Texas Instrunology is scalable, and it will catch up ment's technology makes a good starting
with the density levels of DRAMs and point for small flash cells, since 1.1).,.m
UV-EPROMs. We see 2D years of scalabi- feature sizes, are currently producing
lity in this technology," says McCormick. EPROM cells measuring 13.5 ,.m". Some
The company plans to apply the flash pre- of today's smallest flash memory cells are
cess quickly to each new EPROM genera- just over 2D ,.m2•
0

ElectronIcs / March 3, 1988

6-392

ARTICLE

AR-466

REPRINT

Non'Volatility: Semiconductor
'Vs. Mal!netic
'-'

Nonvolatility: Semiconductor vs. Magnetic
Organizer/Moderator: Richard Pashley, Intel Corp., Folsom, CA
Semiconductor nonvolatile memory is on the verge of challenging magnetic media for future computer storage applications. With solid-state costs dropping faster than rotating magnetic media costs, the cost of semiconductor nonvolatile memory should reach parity with magnetic disks before the end of the century. The
advent of CPU miniaturization and personal computing may accelerate the conversion to solid-state by
changing the traditional main-store user requirements_ With distributed, processing, user memory requirements will shift to lower power, no wait state-access times, and a small light-weight for factor. How each
technology will meet this challenge in the year 2000, will be reviewed.
Since their invention, rotating magnetic memories have dominated the computer main-store market Their
low cost and high density combined with their high endurance have been unsurpassed_ The magnetic disk
market has grown to a $20B annual sales level. The average hard disk cost is between $10 and $20 per Megabyte with densities of over a Gigabyte. Historically, magnetic disk costs have reduced 20% per year, which by
the year 2000 should allow magnetic disks to break the $1 per Megabyte barrier.
The semiconductor nonvolatile memory revolution started with the disclosure of a 2Kb EPROM at ISSCC in
1971. EPROM nonvolatility was achieved by storing electrons on a floating gate. Unfortunately, EPROM
erasure required a 15-minute ultraviolet light exposure to neutralize the electrons stored on the floating gate.
Because of the relative difficulty of erasing an EPROM once it was in a system, the search began for an electrically-erasable memory. The solution was .found with the announcement of a byte-erasable 16Kb E2PROM
in 1980. Still utilizing the floating gate for the storage element, the E2PROM introduced electron tunneling
for programming and erasing. Typically, writing was limited to the 104-10 5 cycles. But this was still not the
cost-effective solution users wanted, as E2PROM memory was 6-10 times more expensive than EPROM and
trailed EPROM by 4x in density. Enter the flash memory. In 1985, a single transistor electrically-erasable
flash memory cell, that writes like an EPROM and erases like an E2PROM, was invented. Long term, flash
memory density and cost could approach EPROM values. However, flash is a block erase memory with
write endurance limited to 100 cycles today. Is flash the ultimate nonvolatile memory? Can flash endurance
be extended to the 104-10 6 cycle range? Will there be an E2PROM breakthrough that brings byte alterable
memory costs closer to EPROM? Today, the combined nonvolatile semiconductor annual market size is
under $1.5·billion with EPROM cost per Megabyte in the $100 range. Assuming the proven 70% silicon cost
learning curve, flash memory will cost under a $1 per Megabyte and reach the 1Gb per chip density by the
turn of the century.
Comparing today's cost of rotating memory to semiconductor nonvolatile memory, disks enjoy a 100x cost
advantage over E2PROMs. However, by the turn of the century, flash memory will achieve cost parity with
disks. For low-density memory systems, cost parity may be reached much sooner_ Magnetic media has a floor
price that is limited by the cost of the disk drive itself, while semiconductor memory system cost is fairly
linear with memory size. Clearly, magnetic disks will maintain their endurance advantage, but solid-state
memory will offer substantially improved reliability without disk' drive crashes, eliminating the need for tape
drive backup. Furthermore, users can execute directly from semiconductor memory, whereas disk drive
latency requires downloading into DRAM. This could be a lOx performance advantage for disk bound multitasking, multi-user systems. For portable systems, credit card format solid-state memory will offer a significant reduction in system weight, power, and space.
Will we see a major nonvolatile memory system architecture departure from disk to semiconductors? Can
solid-state memory maintain its accelerated density/cost treadmill to catch disks? Is solid-state endurance of
104 write-erase cycles adequateTThe' panel will explore these issues and discuss the system interaction with
evolving memory technologies.
© 1988, IEEE. Reprinted, with permission,lnternational Solid-State Circuits Conference. San Francisco, CA, February 17-19. 1988.

6-393

Nonvolatility: Semiconductor vs. Magnetic
I

============Synopses of Introductory Statements by Panelists============
The nonvolatile data storage requirements for information processing and display applications increase as subsystems be·
come

mor~

complex. During the past twenty years, developers of memory

t~chnologies

have made

en~lrmous

advances in

improving memory device densities, speed and reliability. Nonvolatile memory systems are required in applications where it
is vital that stored information not be lost in case of power failure. It is impractical, and in some cases impossible, to reload
the memory under realistic operational conditions. The advent of nonvolatile and NORO (Non-Destructive Read Out)
memory technologies was a major milestone for the, information processing system designer; as a result of this, significant
commercial, aerospace, and military applications are currently emerging, utilizing these attributes. - - R. Fedorak

In large nonvolatile memory systems, magnetic memories such as floppy disks and magnetic tapes have dominated the
market. The cost of magnetic memories is very inexpensive. Magnetic memories, however, require mechanical mechanisms
to operate the memory. The mechanical portion of the disk limits the reliability and the access speed of magnetic memory
syst~ms. e 2 PROMs offer the nonvolatility, but do not haVe' high density or low cost to replace magnetic memories. To
realize a high-density electrically-erasable memory,' the flash e 2pROM was introduced in 19B4. In the near future, these
flash high-density E2PROMs will be expected to replace the magnetic memory. - - F. Masuoka

Semicond,uctors are gaining exponentially on magnetic storage in density/component and cost at a particular density. A
single transistor nonvolatile R/W technology will b'ecome the clear winner for converting this market. Recent advancements
in microprocessor memory management facilities marry well with newly·developed flash technology to produce solid·state
diskless computer·systems. Combined with 'anticipated R/W optical technologies; hig~end systems are also envisioned.
- - 8. McCormick

The current trend towards, larger, more powerful, and more distributed 'personal' computers is also a trend towards
mathine-oriented. impersonal use. One way for the next breakthrough in personal computing to occur is to allow the
customer to feel more powerful ... more enabled through the use of a tool that is truly a persona," aid, or agent. Solid-state
memory components will play
important'role in the coming generation of such tools. - - R. Mohme

Todays high-density EEPROM is really a complete, random-access nonvolatile semiconductor memory system on a chip.
EEPROMs are currently used in systems up to 4Mb to provide enhanced speed, reliability, power or temperature range
operation. As 1Mb and 4Mb EEPROMs are developed, their cast per bit will continue to decrease and EEPROMs will
become the' best solution for'larger nonvolatile memory systems in the future. - - W. Owen

The user cost of rotating memories is c~rrentJY between $10 and $20 per Mb. Historical cost reduc~ion of 20% a year
for disks will bring the ultimate user costs down the $3 to $6 per Mb range in five years. Smaller form factor, mass-produced disk driv'es also address the space, power and portability issues. All of this leads to the conclusion that both magnetic
and semiconductor technologies will ~oexist for th'e foreseeable future. - - G.M. Scalise

Organizer/Moderator/Panel Members
Fedorak, R., Project 'Engineer/Memory Technology-Information Processing, Naval Air Dev. Ctr., Warminster, PA
Masuoka, F., Engineering ManagerfToshiba VLSI Research Center, Kawasaki, Japan
McCormick, B., Marketing Manager/EEPROM. Intel COTP .. Folsom, CA
Mohme, R., Project Manager/CPU Engineering, Apple Corp.. Cupertino, CA
Owen, W., Vice President/Product Planning, Xic"r Corp., Milpitas, CA
Pashle"y, R., General Manager/EEPROM Business, Intel Corp .. Folsom, CA
Scalise, G.M., President, Maxtor Corp., San Jose, CA

.i.
R. Fedorak

~
~

.A!"\:'.

~.,

F. Masuoka

B. McCormick

•

R. Mohme

6-394

(:)
'.":'io

....~........
W. Owen

.~
.......
.

.~ ~.

':'

.!l

R. Pashley

G.M. Scalise
Order Number: 295027·001

A 90ns lOOK Erase/
PrograInCycle Megabit
Flash MeInory
by Virgil Niles Kynett. Jim Anderson. Greg Atwood. Pat Di.t. Mick Fandrich. Owen Jungroth. Susan Kao. Jerry A. Kreifels. Stefan Lai.
Ho-Chun Liou. Benedict Liu. Richard Lodenquai. Weh-Juei Lu. Roy Pavlaf/. Daniel Tang. J.e. Tzeng. George Tsau. Branislav Vajdic.
Gau/am Verma. Siman Wang. Steven Wells. Mark Winston. and Lisa Yang

ABSTRACT
Using advanced 1. O"m CMOS technology, a 245 mil square
131072 X 8 device has been fabricated with a 3.8"m X 4.0"m
cell. The memory exhibits a 90ns read access time with a 900ms
electrical array erase and lOlls/byte program time. The device
has been optimized for in-system microprocessor-controlled repro.gramming with endurance performance greater than 100,000 erase/
program cycles. Column redundancy is implemented with the utilization of flash memory cells to store repaired addresses.
AOV ANCES in photolithography have made it possible to develop
an electrically erasable reprogram mabie 90ns I Mb nash memory
which is capable of greater than 100,000 erase/program cycles.
This I Mb memory implements a command port and an internal
reference voltage generator, allowing microprocessor-controlled
reprogramming [I].
The 90ns access time results from a high memory cell current
(9S"A), low resistance poly-silicide wordlines, advanced scaled

© 1989 IEEE. Reprinted, with permission, from
1989 IEEE lnteraational Solid-State Circuits Conference Digest of Tet:hnical Papers.
New York. NY, February 15-17. 19&9.

6-395

periphery transistors, and a di/dt optimized data-out buffer. U;ing
CMOS inputs, power dissipation is 40mW in the active state and
20" W in the standby mode. The memory electrically erases in.
900ms and programs at the rate of lO"s/byte. The device contains
thirty-two columns of redundant elements and utilizes nash memory
cells to store the address of repaired columns. The use of the nash
memory cell reduces the required silicon area significantly over
the commonly found large metal-shielded EPROM cells [2].
The I Mb nash memory was fabricated on a 1.0"m double poly·
n-well CMOS process. Silicide was utilized on the word lines to
help achieve the 90ns access time performance. The CMOS
periphery circuits were constructed with 0.9"m L,rr, 2S0 A gate
oxide LOO transistors. The density of this I"m nash technology is
demonstrated on the 1.0"m and I.S"m memory cell comparison
shown in Figure I. The 1.0"m memory cell has a IS.2"m' area,
which is over twice as small as the I.S"m memory cell. A microphotograph of the 24S mil', 128K X 8 nash memory is shown in
Figure 2. The process/device characteristics are summarized in
Table I.

a) 1.5JL Lithography

b) 1.0JL Lithography

(5,000 x magnification)

Figure 1. Array SEM microphotograph: (a) 1.5"m memory cell (6" X 6,,) (b) 1.0"m memory cell (3.8" X 4,,)

One of the most significant aspects of this device is its 100,000·
cycle capability. A typical cell erase/program Vt margin is shown
as a function of reprogramming cycles in Figure 3. After 100,000
cycles there still exists a 2.5V program read margin to insure relia·
ble data retention. Accelerated retention bake experiments done

at 250'C for 168 hours indicate that after 10,000 cycles the
memory will exhibit only 0.7V program Vt shift. Program and erase
time degrade slightly due to normal charge trap·up in the tunnel
oxide (Figure 4). in addition, endurance reliability has been excel·
lent with no tunnel oxide breakdown.

Table 1. Device Parameters
Technology

Periphery

Cell

= 3.8/tm X 4/tm

1.a-/tm Lithography

Area

1.Plol~,

Gate Oxide> 100 A

l·SlIIclde

N·Well,CMOS

Read Current

Epion P+

Terase
Tprog

Tox

250.0.

Leff N+P

951'A

900ms
lOps/byte

Device
Die Size: 60116 mils'

0.91'm

Organized: 128K X 8

Xjn

0.31'm

Access Time: 90ns

Xjp

0.61'm

Active Power: SmA
Standby Power: 41'A
Package: 32·pin Cerdip

6·396

"00
'00

...
!&OO
!

TYPICAL ARRAY ERASE T I l l l y

500
400

300

'.oo:~:__--

TYPICAL BYTEPRQGRAM TIME

100
NUMBER OF CYCLES

10000

l0000D

Figure 4. Erase/program time vs. cycling

.....
Figure 2. 1Mb die photograph

However, to build a manufacturable I Mb flash memory, it is
essential to be able to control the memory array erase Vt. The key
is the proper selection of the erase Vt maximum and maintenance
of a tight Vt distribution. The maximum erased Vt is set to 3.2V
via the erase algorithm and the internal erase verify circuits [3].
Good oxide quality gives an erased Vt distribution width that does
not change appreciably with cycling (Figure 5). The tight erase Vt
distribution gives an order of magnitude of erase time margin to
the fastest erasing cell (Figure 6).

.00'
1.5

1.75

2.0
ERASE VI (VOLTS)

Figure 5. Erase Vt distribution vs. cycling

---PROGRAM VT MAX

ARRAY ERASE

PROGRAM VT MIN

7.S

PROGRAM READ MARGIN

'SC-'~r-

__________________

ERASE READ MARGIN

~V~~~M~'N~

ERAU: CELl. Vt VERIFY LEVEL

___

'.S

1=--------------_____----_

ERASEVTMIN

'.S

............. SLOW ERASE :!~ICA1. ERASE BITS

ERASEVT MAX

FAST ERASE Brr

ERASE CELL Vt MINUMUM

.00

10000

100000

1000000

NUMBER OF CYCLES

Figure 3. Array Vt vs. cyles

2000

3000

'000

ERASE TIME (mS)

Figure 6. Array erase Vt profile VS. erase time

6-397

Array erase is executed by switching high voltage onto the source
junction of all cells and grounding all select lines. The array source
switch: shown in Figure 7, switches high voltage onto the source
junctions. Transistor M 16 is a very large device which pulls the
source to ground during read and program modes. During erase
mode,the high voltage latch formed by 1\15-MS enables transistor
M 15, which then pulls the array source up to 12V. To obtain fast
array erase times, this device must be made large enough to supply
the grounded gate breakdown current which occurs on the sources
of the memory array. The upper boundary on MI5 current sourcing capability is set by the maximum allowable substrate current.
If VPP is raised to 12V before VCC is above approximately l.SV,
the low VCC detect circuit formed by MI-M4 drives the node
LOWVCC to 9V. Transistors M9-MII then force the erase circuit
into a non-erase state with MI5 off and MI6 on. When VCC rises
above I.SV, the chip will be reset into a read state.
Redundancy circuits consist of two flash memory cells combined
with a cross-coupled bias and sense circuit ensuring low power
consumption (Figure S). When either M7 or MS is programmed,
the latch no longer draws power. By setting the levels of CLAMP
and BIAS to Vt and 2Vt respectively, the Band BB levels are held
to approximately one Vt. The signals F and FB along with the
address signal drive the inputs to the XNOR circuits. The MATCH
signals for all column addresses are combined to create the full
match signal which enables a redundant column.
In summary, a 90ns I Mb flash memory has been developed
through the ability to scale the flash memory cell onto a standard
CMOS 1.0l'm technology. This memory has been optimized for
in-system microprocessor-controlled reprogramming for more than
100,000 erase/program cycles.

ERASE-,--~-t------'

Figure 7. Array source switch

REFERENCES
[1] V. Kynett et aI., "An In-System Reprogrammable 256K CMOS Flash
Memory," in ISSCC Dig. Tech. Papers, Feb. 1988, pp. 132-133, 345.
[2J G. Canepa et al., "A 90ns 4Mb CMOS EPROM," in ISSCC Dig. Tech. Papers.
Feb. 1988, pp. 120-121.323.

[3] V. Kynett et aI., "An In-System Reprogrammable 32K X 8 CMOS Flash
Memory," IEEE J. Solid-State Circuits, vol. 23, pp. 1157-1163, Oct. 1988.

Figure B. Redundancy circuits

6-398

ARTICLE REPRINT

AR-472

SILICON BITS
Stan Baker

The Memory Driver

The primary driVing force behind the personal
computer revolution has been memory, not
microprocessors. While one cannot give all
.,. .
the credit in one place, and microprocessors
......
and software have their essential roles, the
~
architectures and viability of these small computers has been due mostly to memory tech.
nologies-both semiconductor and magnetic.
That situation continues and more memory trends are afoot that
wiD force computer systems in new directions in the near future.
DRAMs are running out of the economic gas that has propeUed the
memory costs downward, not only leaving the door open for other
memory technologies but demanding they enter.
Today's memory technologies are bubbling with new possibilities that will further revolutionize systems. At the heart of
the changes will be nonvolatile devices. And the major player
there will be flash technology.
Tbe initial personal computers could have been made with CPUs
that were not fuDy integrated, using gate arrays, LSI discrete logic
or 2901 bit-slice architectures. But they could not have been made
without low-cost, dense DRAM chips and low-cost floppy disk
drives. Tbe success of PCs then gave the economic stimulus to
miniaturize hard disks which stimulated the PC business further.
The center of the computing universe is the data, not the
processing engine. And the data is in the memory. And the
ideal memory is nonvolatile.
Besides changing systems, the nonvolatile technologies will
also alter the architecture of the semiconductor business internationally, with large sc3.1e impact on trade, political, and macro-economic issues. The leaders in the nonvolatile technologies are American companies. And they will not license their
technology so readily as in the past.
There is a host of possibilities' from flash, EPROM, EEPROM, battery backing, magnetic, optical, and the more remote ferroelectric technologies. Ferroelectric comes the closest to being the'ideal nonvolatile RAM, but it is the furthest
from reality. However, flash is here and, for the first time,
promises to bring nonvolatile devices into the processing heart
of computing systems in a big way.
Flash memories can have smaller cells than DRAMS and
will be able to get more benefit from the latest lithographic
and other processing equipment than DRAMs will. With only a.
year on the market the bit-count of flash devices has caught
up with EPROMs and DRAMs, all now at 1 megabit per chip.
The I-Mbit flash device just introduced by Intel has a die of
60,000 square mils. Current I-Mbit DRAMs are larger, at
about 70,000 square mils, and 256 kilobit SRAMs use about
75,000 square mils. I-Mbit EEPROMs are about double, on
the order of.l30,OOO square mils.
Flash will continue to track EPROM densities and soon outstrip even DRAMs, according to Richard Pashley, general
manager of Intel's nonvolatile memory business. The only
memory technologies that continue to track lithography in
their cell size are EPROMs and flash devices.

Flash devices can be read as rapidly as EPROMs or DRAMs.
But writing into them takes tens of microseconds per byte. And
they are bulk erased in tens to hundreds of milliseconds .
Such long erase and write times may seem extremely limiting
at first thought. But actually, the bulk of program and data storage does not need fast erase/write. That is why magnetic storage is so important. And that is what has some flash memory
marketeers so excitOO-especially at Intel, which is nowhere in
the DRAM and SRAM businesses, but the world leader in
EPROMs. For flash devices are very similar to EPROMs.
Consider this example. If a computer were constructed with
megabytes of fast volatile RAM directly serving the CPU, that
can be erased and rewritten rapidly, massive blocks of nonvolatile flash RAM can take the place of magnetic storage backing that volatile memory. A few 4-Mbit flash chips will carry
more data than most floppy disks.
That backup storage will significantly speed-up system performance and eliminate electro-mechanical reliability problems,
as well as lots of weight and
power drain. The flash devices that has put the most corporate
can also be used to reduce the commitment-money and talentamount of volatile RAM, be- behind flash. At Intel, flash technolcause some is used to store pro- ogy plays directly off its EPROM
grams and data that seldom technology in which Intel is still the
needs to be erased and changed. world leader.
Such write-seldom sections of
memory can be updated in a sec- A passion for fI••h
ond or so, which is less than According to Pashley, "nash is
would irritate a human operator. the way Intel will get back in the
read-write memory business." In
Fitting in this scenario, future Pashley, Intel and perhaps the inwill
have
more
microprocessors
dustry has its flash champion, and
and more memory on their die. the success of any new technolThat will be a good place for the ogy depends on having the capafast RAM, made even faster by ble individuals that have the faith
eliminating the inter-package wir- and lead the charge.
ing. And these internal RAMs will
Pashley was the pioneer of
be organized to match the processing characteristics of the scaling, the technique of shrinking
CPU which is not the case now MOS devices that is fundamental
with discrete RAMs. The flash .to the evolution .of more and more
and EPROM devices can then dense MOS ICs. His process at
connect directly to the micropro- Intel was termed "HMOS."
. cessor package, eliminating disAt the recent ISSCC in New
crete DRAMs and SRAMs.
York Intel described its I-Mbit
Memory companies everywhere
are working on flash devices. But
Seeq Technology and Intel were
the first to market. Since then,
Texas Instruments and Toshiba
have introduced versions. But Intel
seems to be the only one supplying
in significant volume, and it's Intel

6-399

flash memory chip. Seeq Technology and National Semiconductor, who are jointly working
on nash devices, described a 1Mbit as well. And Texas Instruments described its latest·
nash, a 256k device that uses
only a single 5-V supply.

AR-474

ARTICLE.

REPRINT
Executive Comment
By Laurence R. Hootnlell

MeIllory life-Cycle Costs

oday's memory market is inundated with competing alternatives.
Given so many choices,
designers will tend to specify a part based on its density, read/
write speeds, flexibility, reliability and
space and power requirements. Purchaser,s, however, are more sensitive to
a given memory's price (cost per bit)
and availability.
Without question, these are the proper criteria on which to judge a memory's merits and identify the right mix
for specific application needs. But there
should be one more: life-cyCle cost.
Those who specify memories must consider how much a technology is costing
them over the lifetime of the system
because of its inherent performance
and/or reliability limitations. S\lch
costs are incurred in several ways:
• Manufacturing/Assembly. Systems manufacturers who use ROMs to
store code know they have little flexibility if that code ever needs to be
changed. New masks must be made, old
inventory scrapped, nonrecurring engineering (NRE) charges paid and.weeks
of potential production wasted.
.
EPROMs remedy these problems to
a. certain degree. However, if the
EPROM has already been programmed
and code changes are required, then the
manufacturer is faced with the undesirable task of disassembling the system, pulling out the EPROM (and run-.
ning the risk of damaging it), erasing
and reprogramming the device and
reassembling "'e system.
If, instead, a manufacturer decides to
pay a high ·unit cost up front to. obtain
the in-system electrical erasure of
EEPROMs, it is likely to mount them in
.sockets because of relatively high failure
rates, thereby incurring even more costs
from the socket, the added space and,
failed products. In-system electrical era'
sure eliminates the inventory problems
of ROMs and the update limitstions of
EPROMs, yet EEPROMs frequently
lack the required density and ongoing
reliability needed by many systems.
On' the other hand, Flash memory
offers a mix of performance characteristics to provide the optimum cOst efficiency: in-system electrical read/write
capability and proven reliability.
• Customer Service. If your com-

The mosteffective
memory
purchase
decision is not
limited to shortterm price and
availability
issues.
pany has a service organization chartered to maintain systems once they're
sold, then chances are your service

technicians travel to customer sites,
pull apart systems, diagnose problems
·and perhaps end up reprogramming
the EPROMs or replacing dead batteries. Because of the handling required
for reprogramming and the likelihood
of damage, they may even be replacing
the old memories with entirely new
ones because each unit is 80 "inexpena
sive." But how much does this procedure cost-in time, labor, parts ... and
. in customer inconvenience?
With Flash memory, a technician
can read the mem~ry remotely over a

phone line, diagnose the problem and
perhaps correct it through an immediate rewrite of the memory-or at least
identify the exact problem and take the
correct replacement parts with him on
the initial service call. This reduces the
number of service calls as well as the
duration of those calls still required.
This level of service could save a systems supplier with a large installed
base a tremendous amount of service
labor and time, as well as improve ita
customer relationships through improved product reliability.
'. Response to Market Needs.
Most systems have their own carefully
formulate!! cost-effectiveneas lifetime,
after which their f~atures may become
obsolete because of continually emerging
state-of-the-art alternatives. Premature
obsolescence makes for a costly system.
Consider the possibilities instead if
your embedded system could be updated in the field. For example, a printer
or copy machine or modem could be
feature customized using an in-system
read/write nonvolatile memory. The
system could be updated not only at the
very end of your manufacturing line,
but potentially also.by your reseller to
meet a customer's immediate requiremente-or, at some point in the future,
at the customer's site over a phone line
to provide added or enhanced features
as they become available or desired.
The memories available previously,
such as static RAMs and EEPROMs,
that cbuld achieve this level of functionality, come up short on some of the
other key criteria used by the'deSign!
purchasing team, such as density, cost
per bit and reliability.
In contrast, Flash memory combines '
the key memory characteristics (fast
readlwrite capability, inherent
volatility, low cost per bit, reliability and
density) to provide a balanced solution.
The most-effective memory purchase
decision, therefore, is not limited to
short-term price and. availability issues. Rather, an analysis of how a particular technology might impact different organizational bottom lines can
yield much more significant, long-term
cost savings for your company.

non-

Laurence R. Hootnick is senior VP and
general manager of the Embedd,ed Controller and Memo", Group at Intel Corp:

©INTELCORPORATION
.
Copyrighl© 1989 by CMf> Pub'ications,,'nc., 600 Community Drive, Manhasset; NY 1:1030
Reprinted from Ele~tronic Buyers' News with permission. June 26, 1989

6-400

ARTICLE
REPRINT

AR-478

December 1989

Flash Memories: The Best
Of Two Worlds

By
RICHARD D. PASHLEY
STEFAN K. LAI
INTEL CORPORATION

1989 Intel Corp.
Reprinted from IEEE Spectrum with permission.

Order number 295040-001

6-401

Flash tnemories:
the best of two worlds
Filling a niche between conventional EPROMs and EEPROMs, these dense memories
offer the latter's reprogramming convenience at relative cost advantages
APPLICATIONS

In evolving from a concept paper in 1984 to megabit
SOLID
devices only five years later, flash memories have
moved up the transistor-density curve faster than any
previous semiconductor memory IC. They are based
on the technology of either erasable programmable
ROMs (EPROMs) or electrically erasable programmable ROMs (EEPROMs), and in price and functionality fall somewhere between the two, suiting any
applications that require the former's denser storage plus the latter's ability to be reprogrammed without removal from Ii system. They also share these memories' nonvolatility and fast read access.
Those flash devices more akin to EPROMs cost less and promise rapid device and price scaling; their suppliers include Intel
Corp., Santa Clara, Calif.; Seeq 'Iechnology Inc., San Jose, Calif.;
and Tokyo's Toshiba Corp. The others, which utilize the more
complex EEPROM technology, are slightly more expensive but
provide more flexible reprogramming. They are made by Thxas
Instruments Inc., Houston, Texas, and sampled by Atmel Corp.,
San Jose, Calif., among others.
Of these three types of reprogrammable memory, EPROMs
remain the best choice for applications where data almost never
needs changing. Otherwise, flash memory devices should be considered. Although the average EPROM may sell for' about $7,
and a flash memory for about $25, the differential is wiped out
by the expense of a single reprogramming. The in-system
reprogramming of a flash device may cost as little as $1, whereas pulling an EPROM out of a system to erase it by exposure to
20 minutes of ultraviolet (UV) light may cost over $80 when equipment, downtime, and labor are factored in.
Meanwhile, EEPROMs should remain popular wherever it is
necessary to erase bytes selectively. But flash products, which are
erased in tlieir entirety or section by large section, might do better for updating stored logic, when this must be done more than
once but less often than in main memory, cache memory, or
registers. Reprogramming costs are similar, but flash memories
are less than half the price of EEPROMs.
Flash memories may even oust some battery-backed static
RAMs (SRAMs), a bulky combination. In laptop computers, the
flash device would occupy less space, at a lower cost per bit, and
eliminate the dependency of memory on battery power.
Most flash memories have the same pinout as EPROMs, so
that substituting them in a system requires primarily software alterations. (The densest flash ICs may have a few extra pins, however.) Furthef11lore, whereas a flash memory will nearly always
be surface-mouniable, that is not the case for some applications
of EPROMs, whose packages include a window that must be accessible to UV reprogramming equipment. A flash-for-EEPROM
swap, though, will almost certainly require rerouting the printed circuit, because flash memories may be up to four times denser.
Also, flash ICs closer to EEPROM technology need only a 5-

volt supply, whereas those closer to EPROMs require
a 12-V one as well, to drive the high-energy electrons
that write data into them. This kind also requires
a multistep algorithm that verifies erasure. Its makers
say that the 12-V supply helps protect the IC against
accidental erasure; those that supply S-V-only versions counter that there are software techniques that
may be employed to'render such an accident too rare
to be worth consideration.
The choice between the two flash memory types
is sometimes determined by the application. In small embedded
controller systems, missiles, or remote battery-powered systems,
a S-V-only flash memory is preferable. On the other hand, a 12V supply is already available in some systems, such as desktop
personal computers and laser printers.
'
With software of all kinds becoming more complex, the likelihood of changes to it, to update it or eliminate bugs, increases
proportionately. That, in turn, argues for efficiently reprogrammabIe nonvolatile memories, and bodes well for the popularity
of flash memory.
Consider the basic 110 system of a PC. It is typically stored
in ROMs or PROM. Flash memory would allow the changing
of 1/0 system code over a network or modem within minutes.
Also, portable computer systems' hard-disk drives may' be
replaced by flash memory modules offering lower cost, size, and
weight, plus the greater reliability of solid state.
The operating system for an IBM PC AT or an Apple Macintosh is big enough as a rule to need storing on magnetic hard disk.
With each year, however, flash ICs become more economical for
greater amounts of storage; up to 2M bytes of flash memory are
available with a new laptop from Psion Inc., Watertown, Conn.,
for example [see photo). As this trend continues, flash ICs may
supplant hard-disk drives of small capacity (up to 10 megabytes)
in systems that could use a small, reliable memory with low power

STATE

Richard D. Pashley and Stefan K. Lai Intel Corp.

Defining terms
Electron trapping: the accumulation of electrons in Imperfec·
tlons in silicon dioxide, so that negative charge builds up and
delays erasure of programmable memory devices.
Fowler·Nordhelm tunneling: a quantum mechanical process
In which electrons tunnel through a thin dielectric from (or
to) a floating gate to (or from) a conducting channel-the
erase mechanism In flash memories and the program and
erase mechanism In electrically erasable programmable'
ROMs (EEPROMs).
Hot·electron Injection: in this context, the injection into the
memory cell's floating gate by a vertical electric field of elec·
trons with 'excess energy acquired from a high source·to-draln
channel electric field.
Nonvolatile memory: memory that does not lose stored bits
after power is switched off (Includes ROMs, PROMs, EPROMs,
EEPROMs, and flash memories).
'

IEEE SPEctRUM DECEMBER 1989

6-402

The MC400 laptop computer Jrom Psion Inc., Watertown, Conn., uses flash memory modules to replace
disk drives. ThecomputerhasJourmoduleslots, and
each module contains Jour Intel I28K-bit flash ICs
in plastic leaded chip-carriers Jor a total oj 2M bits
oj memory. The primary requirement Jor switching
Jrom disk to solid-state memory is rewriting the operating system's memory management code. Psion also
makes an accessory that lets the user plug the MC4()()'s
modules into any IBM Corp. or compatible personal
computer.

.,
\

·0

Most flash memories are programmed with the
EPROM's hot-electron injection technique. Each
............................... 11' ..

,:0: .. 1..1

"'f'f'.................. : .. +..... f't;''CT': ............ ..-1

~;;~~-~ff-b~ ~h;-~bs~~~;-o-;;;~~";~~e'~f ~h~;~;~~-;

.'
~.

-""""

.. i:~.···

....
'."

,,~:

consumption. In such cases, though, another software modification becomes necessary. Data is stored in serial form on hard
disk, and must be reformatted into bytes before it can be sent
to RAM. Data stored on flash ICs is already in byte format, and
operating systems are being rewritten to accommodate this.
At present, the programs for embedded controllers, such as
those that operate automobiles and production machinery, are
kept in other forms of nonvolatile memory. But flash ICs could
serve here, too. And they could also speed up laser printers. Much
of the formatting font and size information, along with the data
to be printed, must now be loaded for each page from the central processing unit to the laser printer. Flash memory in a laser
printer could store the font information for an entire print session just the once, so that pages would print out one after the
other with less delay. A change in print session parameters would
simply invoke an erase/reprogram cycle.
Flash memories are also candidates for use in flight data recorders and in communication equipment where parameters change
often to accommodate different data communication formats.

Flash technology
Even as semiconductor memory began displacing magnetic
core memory in the early 1970s, the inability of RAMs to retain
data after power was turned off remained a problem. The invention of the nonvolatile EPROM deserved to be successful, despite the clumsiness and low repeatability of UV erasure.
EEPROMs subsequently offered speedy in-system erasure with
a strong electric field, which, however, at 12 megavolts per centimeter, so stressed the device's tunnel oxide as to limit the number of erase and write cycles possible. Also, the EEPROM memory cell, larger than the EPROM's, meant less favorable
economics.
Accordingly, the challenge for semiconductor engineers was
to fabricate a memory with the EEPROM's electric eras ability
but priced more like an EPROM, of comparable memory retention and cell size, and higher read/write cycling capability. Like
both devices, the new one was to have high-speed read access.
The flash memory is the response to this challenge.

Pashley and Lai-Flash memories: the besl of Iwo worlds

6-403

floating gate sitting above the conducting channel.
Electrons accumulate on the floating gate because of
the field produced by a large positive voltage on the
select gate above the floating gate, and a similar voltage on the drain while the source is grounded. Once
on the floating gate, the electrons are trapped there
by the surrounding nonconducting oxide. The electric field they produce will then turn off the FET, storing a logic 0 in that bit location. Where no excess electrons are trapped on the floating gate, the FET's
channel can conduct current and the cell has a logic
value of I. Thus, both in cell structure and in programming technique, the flash memory is very similar to
the EPROM.
All flash memories are erased electrically in the system and in I or 2 seconds, like EEPROMs, but in bulk,
like EPROMs. Electrons tunnel back into the source region in
response to an electric field between gate and source. Some devices
have been designed to make programming and erasing consistent with microprocessor control. The EEPROM's individual byte
erasure is made possible by equipping each memory cell with a
second, select transistor, and by forgoing the select transistor to
obtain bulk erasure, flash memories can be built with much higher
densities than EEPROMs.
Structurally, the flash memory cell is like the EPROM cell,
being only slightly larger and with a thinner gate-oxide layer,
usually 10-20 nanometers deep. But each supplier of flash memories has taken a slightly different approach to the device. Intel
uses its ETOX (EPROM tunnel oxide) technology. Seeq employs
a "phantom transistor" approach, which has a stepped-gate structure. Toshiba employs a triple-polysilicon, three-gate design. TI's
is also a stepped, two-gate structure, with a thin dielectric to ease
electron tunneling to the floating gate. The first three designs are
programmed by hot-electron injection and erased via FowlerNordheim tunneling. Tl's design depends on tunneling for both
the write and erase mechanisms.
The Seeq cell puts a second transistor in series with the first
to.control erasure and also enable the erasure of small subsections. The approach in effect lengthens the channel, however, and
limits programming performance. Programming and erasure
occur through the same junction, stressing the gate oxide and
guaranteeing fewer than 10 000 cycles, although up to 100 000
is typical.
Toshiba's flash cell is the most complex and largest of these
three. It his a phantom transistor like Seeq's, also to control erasure. It has another layer of polysilicon for erasure through a
polysilicon-to-polysilicon oxide. The poly-to-poly-oxide erase
path requires higher voltage than either the Intel or the Seeq flash
cell. Tunneling through poly-to-poly oxide tends to trap more electrons, so that the cell'threshold increases with cycling. As a consequence, Toshiba's memory cells are specified for 100 cycles, and
to 1000 cycles with special electrical screening tests.
TI calls its flash memory a merged-transistor advanced contactless EEPROM. The cell transistor and pass transistor are

merged so that its flash memory cell is structurally similar to
Seeq's phantom cell, except that it has a thin (IO-nanometer) oxide
tunnel window for programming erasure.
Intel's cell is programmed through the drain, and erased
through the source, which results in the reduction of stress on
the gate oxide and a typical cycling capability in the 100 000 to
I million range. The cell is smaller than the other three, which
means not just smaller chips and more of them per wafer but
a faster-to-program device with a shorter channel length.
The Intel cell uses a single FET with a floating gate for storage. To program a row of eight cells (a byte), the row decoder
selects them and drives them to 12 V. The bits within the byte
that are to be programmed as logic 0 are selected by the column
decoders, which takes them to about 7 V.
'JYpically, hot-electron programming takes less than 10 microseconds per byte while tunneling takes between 5 and 20 milliseconds per page for programming, per chip for erasing. For bulk
erasure, a second is more than adequate, and the reduced stress
on the flash memory's gate oxide (compared with the EEPROM's)
markedly ameliorates oxide-related problems that affect memory retention, time to program; and time to erase. All involve
mechanisms affecting device quality and reliability.

Quality vs. reliability
IC quality is not to be confused with IC reliability. Quality
describes how closely a chip conforms to its specifications upon
delivery and is a manufacturing concern, dependent on the
thoroughness of testing processes. Reliability describes how closely an IC continues to conform to its specifications over years of
use, measured by failure rates of components that have been qualified and installed in fielded systems. Reliability will bear on the
overall cost of ownership of a system because repair in the field
costs far more than repair during production.
The failure mechanisms usually associated with program/erase
cycling of electrically erasable memories (EEPROMs and flash
memories) are charge loss due to latent oxide breakdown and electron trapup. Both manifest themselves when a device cannot be
reliably programmed or erased within the maximum time
specified.
To reduce oxide breakdown, a chip manufacturer can both improve oxide quality and attempt to reduce the stress on the tunnel oxide during programming and erasing. With Intel's flash IC,
for example, the area of oxide involved (and the area that is
stressed by the electric field) is confined to an overlapping area
between source and gate. In addition, the reduction in electric

field intensity across the tunnel oxide in flash memories to 10
MY/cm from the 12 MY/cm typical for an EEPROM theoretically should increase its reprogramming durability. In experiments
where over 2000 Intel 1M-bit flash, memories were cycled more
than 20 000 times, none of the dev1ces failed because of oxide
breakdown, and several devices survived I million program/erase
cycles.
The smaller the memory cell, the less capacitance it has, and
the less charge need be added or removed for programming or
erasing. Trapup is directly related to the amount of charge moving through the oxide, so the smaller charge requirement will tend
to postpone its occurrence, stretching it out over many more program/erase cycles than for larger cells, with higher capacitance.
Thus, the larger the cell, the more susceptible it is to trapup, and
the more programming or erase pulses it will take to push sufficient electrons onto or off the floating gate.
Beyond the cell itself, peripheral chip functions and oxides are
affected by repeated program/erase cycles. In general, the higher
those voltages, the more vulnerable the peripheral circuitry is to
functional failures. Intel's flash memories need no more than 11.4
V to meet their program/erase specifications. Other (lash memories that require the same nominal 12-V external supply have
on-chip charge pumps and internal voltage levels of 20 V and
higher. These voltages put more stress on peripheral circuit oxides, to the possible detriment of reliability.

Looking down the road
CMOS is today's mainstream technology for both logic and
memories. Within that technology, EPROMs and flash memories should be more scalable than dynamic RAMs (DRAMs) or
SRAMs and EEPROMs. At a first level. there are differences in
memory cell complexity. SRAM cells have four or six transistors.
Thrning transistors on or off to store logic levels (writing) is faster
than storing charge in a capacitive well (DRAMs) or on a floating gate (EPROMs, flash memories, and EEPROMs). Sensing
logic levels (reading) on SRAMs is also faster than on the other
devices. But the price of that speed is increased cell complexity.
Absolute SRAM cell sizes are over 10 times larger than for singletransistor devices (EPROMs and some flash memories) and scaling is more complicated because all dimensions cannot be reduced
proportionately without upsetting some minimum spacing rules
between lines and active devices. For example, distances between
devices may not be allowed to shrink proportionately with line
widths.
An EEPROM cell, employing both a bit-storage and a select

A comparison of flash ICs, EPROMs, and EEPROMs
Voltage
Access time,
Company, location

reqUirements,

nanoseconds

1M bit

120

10'

Bulk

1M bil

200/250

10'

Sector, bulk

256K bits

170

10'

Bulk

256K bits

170

10'

Bulk

10'

Byt,

10'

Byt.

Up to 100

Blanket,ultraviolet

20 minutes max.

5/12

Up to 100

Blanket. UV

20 minutes max.

5112

Density

Erase/write
cycles

Mmimum
erase area

Power consumption,
milliamperes

Erase/Write limes

volts

1 second/chip,

5/12

Fluhmtmorlea
Intel Corp.,

sanla Clara, Calif.
s"q Technology Inc.,
San Jose, Calif.
Texas Instruments Inc.,
Houston, Texas
Toshiba America Electronic Components Inc.,
Irvine. Calif.

Electrically erasable programmable ROMs (EEPROMs)
Simtek Corp.,
256K bits
120
Colorado Springs. Colo.
Xicor Inc ..
1M bit
200
Milpitas. Calif.
ero..ble programmable ROMa (EPROMa)
Microchip Technology
256K bits
55
Inc., Chandler, Ariz.
Texas Instruments Inc.,
1M bit
170
Houston, Texas

10.s/byt,
12 secondslchip,
525.s/byte
15 mslchip,
15 mslpag'
100 ms/chip.
200.s/byte

10 mslchip,
160.s/byt.
5 ms/pag.

IEEE SPECTRUM

6-404

5/12
5

5112.75

5
5

DECEMBER 1989

Toshiba cell

,-"'''.~

Intel cell
Selecl gale--£
Floating gale

:======~

Gale oxide

Erase gale

P substrate

Texas Instruments cell
Seeq cell

----.

Floatlna gate,

Phan.omtran.~FIOatingga.e
Ga.e oxide

Burled N+psource
N + sourco

Merged pass gale

~
Ga.e

OX~'des N+ dram

N + dr"n

Psubstrate

~Substrate

can be much more functional
than microcontroller processors.
The tendency is to view nonvolatile memories as vehicles
for software modification; but
in the future they may also be
used to change the functions of
hardware. Just as some of today's programmable logic
devices (PLDs) use SRAM to
control logic programming,
tomorrow's PLDs may use
flash memories for the same
j um.. l.iu.l.1. Gli~ 0th\';t u.i"~u iil
which flash memories promise
to contribute is neural network
systems, or processors that
mimic the way the human
brain works. It is likely that
computers based upon neural
networking concepts will use
flash memories or EEPROM
memories as key elements of
their processing units.

Ofthefour approaches to flash memory technology, Intel Corp., Toshiba Corp., and Seeq Technology Inc. have chosen designs closer to EPROM technology, Texas Instruments Inc. one closer to
EEPROM technology. Flash memory cells are similar to an EPROM cell, except they have shal- To probe further
lower gate oxides, usually 10-20 nanometers deep, to allow Fowler-Nordheim electron tunneling.
The first concept paper on
Intel's cell employs a singlefield-effect transistor with afloating gatefor storage, and is programmed flash memories was presented
and erased through different areas of its gate oxide. Seeq employs a stepped-gate, two-transistor by Toshiba Corp., Tokyo, at the
structure; the second transistor helps control erasure and also enables the erasure of small subsec- 1984 International Electron
tions. Toshiba's cell has a triple-polysilicon, three-gate design; it also uses an additional transistor Devices Meeting. The 1984
to control erasure. The source and drain of the Toshiba cell are perpendicular to the plane of the IEDM Technical Digest can be
page. These three designs are programmed by hot-electron injection and erased by tunneling. Tl's ordered from the IEEE New
cell is also a stepped-gate, two-transistor design, but its oxide layer is constructed to ease tunneling, Jersey Service Center, at 445
upon which it depends for both its write and erase mechanisms. Though several of these designs Hoes Lane, Piscataway, N.J.
have more than one transistor, only the memory cell is depicted. Intel and Seeq are currently the 08855; or call 201-562-5493.
only two companies producing 1M-bit flash memory products.
The nonvolatile memory
section of the 1989 Internatransistor, is over 2.5 times the size of a flash cell. Here, too, the
added complexity and high voltages required may make proportionate scaling (equal reduction of dimensions and spacings)
somewhat elusive. Surprisingly, even the DRAM cell, composed
of a select transistor and a storage capacitor, is over 1.5 times as
large as the flash memory cell. But on today's submicrometer
scale, planar DRAM capacitors hold too little charge for reliable bit sensing, so that designers have gone to three-dimensional
structures, such as stacked or trench capacitors. These constructions complicate manufacturing, reducing reliability and raising
costs.
Having an active memory-cell transistor sense current like an
SRAM and lacking the soft-error sensitivity of DRAMs, flash
and EPROM technology may well be the most scalable memory
technologies by the year 2000.
In geological terms, 10 years is insignificant, but in solid-state
technology, 10 years is one-fourth the age of the transistor. However, by the year 2000, a 256M-byte flash memory using 0.25micrometer geometry on a die 0.7 inch on a side is projected to
sell for $1 per megabyte. Alternatively, less flash memory could
be combined on the same die with application interfaces, such
as high-speed data transfer interfaces, similar to today's burst
mode, page mode, and "nibl" mode transfer schemes.
Several 256M-bit flash devices, without today's on-chip control features, may form a multichip memory subsystem run by
a single controller IC, akin to the DRAM and DRAM controller
subsystems of today. In embedded control systems, the flash
memory device may be combined with other application-oriented
logic to simplify and shrink the design and lower its cost. Such
chips will be similar to EPROM-resident microcontrollers (such
as Intel's 8748, 8749, and 8751) but have far more memory and

tional Solid- State Circuits Conference (ISSCC) Digest of Technical Papers contains papers on flash technology from intel
Corp., Santa Clara, Calif.; Seeq Technology Inc., San Jose, Calif.;
and Texas Instruments Inc., Houston, fuas. It is also available
from the service center.
The paper, ''A 90ns One-Million Erase/Program Cycle Megabit
Flash Memory," from Intel Corp., was published in the October
1989 Journal of Solid State Circuits special issue on logic and
memory.

About the authors
Richard D. Pashley (SM) has served as general manager of Intel's Flash Memory Operation, Folsom, Calif" since April 1986.
The previous five years he was director of Intel's Technology Development group in Santa Clara, and before that, he managed
Intel's static RAM, static logic, bipolar memory, EPROM and
EEPROM technology development activities. In 1976, Pashley
developed Intel's HMOS (high-performance metal oxide semiconductor) process technology. He holds a doctorate in electrical engineering from the California Institute of Thchnology in
Pasadena.
Stefan K. Lai (SM) has been engineering manager for Intel
flash memories since 1986. As program manager for flash memory technology deveiopment during the two years prior to that,
he co-invented Intel's ETOX (EPROM tunneling oxide) flash
memory process technology. From 1979 to 1982, he worked at
IBM Corp.'s Thomas J. Watson Research Center, Yorktown
Heights, N.Y., where he was involved in tunnel oxide dielectric
research. He holds a B.S. in applied physics from the California
Institute of Thchnology and a Ph.D. in applied quantum physics
from Yale University, New Haven, Conn.
•

Pashley and Lai-Flash memories: the best of two worlds

6-405

ARTICLE
REPRINT

AR-484

May 1990

PC Standard
in the Cards

BY TOM WOLFE

Order Number 295048-001

Reprinted with permission from EETimes, May 1990

6-406

AGREEMENT AT HAND FOR Ie-BASED STORAGE MEDIUM

PC standard in the cards
ciation (PCMCIA) and the MIT!affiliated Japan Electronics Industry Development Association
minent on a Japan-U.S. standard UEIDA), which includes about 40
for the "PC Card," a 2 x 3-inch major Japanese companies. The
IC·based card to be used as a 70-member PCMCIA includes
removable data·storage medium nearly all of the personal computfor portable computers.
er industry's movers and shakers,
Expectations are high that this with IBM, Lotus Development
transPacific standard will do for no- Corp. and Microsoft Corp. playtebook and laptop computers what ing particularly active roles.
MS-DOS, the floppy disk and the
Today and tomorrow in SeatIBM PC did for desktop machines: tle, Microsoft will host the May
allow software to be sold for, and meeting of the PCMCIA, at which
data to be exchanged over, a medi- members are expected to apum compatible across a broad prove a draft agreed to in Tokyo
range of portables from a long list on May 10 by PCMCIA members
and the memory card working
of manufacturers worldwide.
With notebook and low-end lap- group of JEIDA. The agreement
tops expected to constitute half of specifies the JEIDA V. 4.0 forJapan's PC market by 1994-and mat, 68-pin card; the DOS file
perhaps a thfrd of PC sales around format; a means for the system to
the world by then-approva! of know what kind of card it is dealthe standard is especially impor- ing with; and other hardware and
tant to U.S. computer and soft- system-software specifications.
It's expected that Poqet Comware companies. Proponents of
the PC Card concept hope that, puter's (Sunnyvale, Calif.) Poqet
with the standard approved, soft- PC, a palmtop unit that accepts
ware vendors will quickly begin the IC cards, will spearhead pene- ,
porting applications to the cards tration of the U.S. market.
Dan Sternglass, founder of Daand users here and in Japan will
tabook Inc. (Ithaca, N.Y.), which
embrace the new technology.
The PC Card standard is being manufactures a series of IC-card
forged by the Personal Computer reader/writers and programmers,
Memory Card International Asso- said: "What's going to drive the

By DAVID LAMMERS
Tokyo - Agreement could be im-

6-407

market flrst are portable systems, starting with the Poqet. We
still have to see how much of the
market will be penetrated by the
handheld-type computers. Then,

FuJitsu's version of the
credlt-card-slze 'PC Card.'

PC Card standard drafted
if everyone owns a handheld, IC
cards might be used in desktops,"
A host of notebook machines
coming to market in Japan is expected to fuel use of the new
cards there.
Last week at the Japan Business Show, NEC Corp., \>ujitsu
Ltd. and Mitsubishi Electric
Corp. all introduced powerful new
notebook computers that include
IC reader/writers compatible with
the new 68-pin standard. Fujitsu
offered a half dozen applications in
ROM-based IC card format, along
with various data file cards using
SRAMs.

Little pes will make big strides'in Japan market

....,.;00........

,'.·&';..·.;;~..
·'I.....
,. ...,-0+0-.............;..'...;.,';;..;.........--:-.........

'.,,'
.
•••~.....,...,..

N_ notebook

How standard came about
Tokyo - The people who hammered out the IC card standard
between Japan and the United States described it as an exercise
in quick compromises-and a demonstration that good will exists
in abundance between Japan and America.
Basically, the standard took most of the hardware specifications developed over the past five years by the Japanese and
added software standards prompted by the U .S,'s Personal
Computer Memory Card International Association (PCMCIA),
Fujitsu Microelectronics memory card manager John Reimer'
said Poqet Computer executives realized a year ago that a
standard for the cards
would expand the software
base for their palmtop machine. Reimer-rithms that require 500 to 1,000 bytes of code. (Intel offers
sample rode generated fur different base processors to m·inimize the software effort.) Because flash memory is bulkerasable, this code must be stored and executed from another
memory while the main code is updared. Por this process,
many designs rely on internal ROM space on mkrocontrollers
or small I>PROM boot loaders On Intel SOX86 sysrems. The
boor loader contains su(fident code to initialize the sYStem
and reprog!':lm the flash memory.
As with EPROM, flash memory requires a programming

power supply of 12·v :!;:; percent. Some systems feature •
12-v supply. hut others do not. Systems with analog
circuitry, for insrance, ofren cOMain rails of 15 Vor higher.
In these systems, the programming power supply can be
generated by regulating the higher voltage using an
LM317 -rype regulator.
For memories that have a power supply of 5 V, designers
can Opt fot either monolithic or discrete charge pumps, such
as those as offered by Valor Electronics and Linear Technologies. Since flash memory requires only 30 mA per device.
from the programming power supply during active programming and erasure, these boost circui~s can be made fairly'
small.
Some flash-memory manufacturers daim to have simplified programming and erasure by developing automatk controls and S-v-only programming. The 5-v technologies arc
based on EEPROM-programming !':lther rhan EPROM-programming techniques and generate high volrages internally.
They require larger boatacked Fig Whereas in workstations Flash memory is used as cache for the OS and code. the laptop uses Flash memory for direct
SRAM drives are actually more execution.
common because of familiarity.
However, each has' inherent very scalable for photolitho- on linked-list techniques, this their nonvolatility and RAMdrawbacks. ROMs have histori- graphic processes, promoting Dos-compatible file system, disk equivalent access speeds.
cally been uSed in laptop sys- very high density devices. In an with superior performance over Many types of industrial equiptems to store unchangeable, environment where high den- the mechanical disk, takes ment are using F\ash memory
preloaded software programs. sity is synonymous with sec- advantage of the chip-level for code storage and data accuTo upgrade with software revi- ondary storage, Hash will out- erasability of Flash memory.
mulation, replacing all forms of
sions, the ROM application sell and outlast volatile SRAMs
Although we have only dis- disk drives, both mechanical
hardfile is discarded and a new because of cost and reliability cussed Flash memory applica- and solid-state.
'
card is purchased-an undesir- advantages.
Flash memory will continue
tions in the notebook computer,
able expense for the user.
its usage spreads well beyond. to play a dominant role in the
Battery-backed SRAMs en- U.IOg Flub memory .
BIOS modification in desktop evolution of the notebook comable the flexibility to continuThe adoption of Flash mem- computers is' also unavoidable puter as well as every other
ously 'modify files. SRAMs are ory in a solid-stale disk comes due to increasing system com- application requiring a nonused both
floppy and hard with the design challenge of pleXity. Primarily aimed at fix- volatile, reprogrammable, relidriVe replacements, only where interfacing a bulk-erasable ing bugs, this technique also able, high density, and low cost
very low densities are required. memory with a file system alleviates compatibility prob- memory. The flexibility of this
Besides not being practical for requiring byte-level alterability. lems that might arise from the new memory technology is
high-density applications, The simplest SQiution is to use a installation of the myriad of driving costs down and generatSRAMs also draw concern from RPM-like approach and use the add-in boards and software ing an important alternative to
drive as an application hardfile packages. In addition, the OEM disk memory. •
'
unpredictable battery life.
Unlike the ROM drive, flash with the extra benefit· of being ('.an promote upgrade service
erase
and
reuse
the
able
to
as
a
market
distinction,
as
done
Mark1U Levy is technical marmemories can be reproketing engineer at Intel Corp.
grammed many times. Unlike , disk. Microsoft has made major by NCR and Olivetti.
F\ash memory disks are use- (Folsom, CA).
.
SRAMs, the ~ingle transistor advanc~ over this approach by
memory cell of flaSh (compared developing a special file system ful as application caches in
to 4-6 transistors for SRAM) is it calls Flash File System. Based high-end systems because of

6-418

ARTICLE
REPRINT

AR-491

UPDATE

October 1990

Memory breakthrough
.. •
- - I
,urives minia,uriza,lon

can use it like RAM and carry it around like a disk. Flash EPROM technology is poised to
change the way portables are made.

YOg

ast year---;a year in which assump- ory cards, providing a removable stor- to store programs (such as Tandy's
tions about the world seemed to fall age medium for software. Intel guar- Deskmate interface or MS-DOS)
with bewildering regularity-a tru- antees 10 years of data life.
which now take several seconds to
ism about computers suddenly beFlash EPROMs are likely to rear- load from hard disk to RAM while
came irrelevant. Intel Corp. in Santa range the mix of chip- and disk-based sucking up precious electricity. ProClara, Calif., unveiled a new type of storage in all computers, especially grams stored in flash EPROMs load
memory chip, the flash EPROM, the smallest portables. When used on nearly instantaneously. One compawhich combines the flexibility of RAM removable cards, they can replace ny, Cardinal Technologies Inc.
with the permanence of disks. The floppy drives, eventually for one- (Lancaster, Pa.) plans to offer an exdistinction between RAM and disk quarter the cost of currently available pansion board containing Digital Restarted crumbling like the Berlin Wall. SRAM cards, according to Intel. At this search's DR DOS inregular ROM
Now the implications of flash writing, however, computer makers paired with 2MB of flash EPROM for
EPROMs for portable computing- were waiting for lower prices before storing applications.
Engineers also envision flash
particularly notebooks and hand- making the jump from SRAMs to the
helds-are becoming clearer. If sup- new chips.
EPROMs bringing major changes to
porters of the technology are correct,
Flash EPROMs could also be used the embedded computers and conflash EPROMs could
trollers that are becoming
eventually replace bulky,
mainstays of modem life.
power-sapping disk
Computerized engines
drives in computers and
could be reprogrammed
to reflect evolving fuel
serve as a universal stormixtures as a car ages
age medium for nearly
(currently, such programevery electronic device
mable memory is dethat uses memory.
Based on older
pendent on battery power). Digital electronic
EPROM (erasable procameras will use flash
grammable read-only
EPROMs instead of digital
memory) technology,
tape or film to store phoflash EPROMs do not
tographs with sharpness
need a backup power
comparable to that of 35supply to retain data.
millimeter cameras.
Like regular EPROMs
Although Londonand dynamic RAMs
based Psion PLC is first .
(DRAMs), they can be
out of the gate with two
packaged in plastic cases
flash-based notebook
and plugged into comcomputers, the MC200
puter motherboards. And
and MC400 (available this
like static RAMs (SRAMs),
they can be integrated Intel's fluh EPROM chIps can store data wIthouIa conatanl8uppIy summer) you can expect
to see other innovative
on credit-card-size mem- of electricity.
o

Order Number: 295055-001

6-419

machines using the new technology
by early next year, according to Intel.
Hardware and software vendors
are already using flash EPROMs to
store vital code normally residing on
ROM chips that can't be conveniently
reprogrammed. When encoded in
flash EPROMs, the computer's ROM
BIOS, which manages hardware's interaction with !jOfiware, can be updated via modem or floppy disk.
(Phoenix Technologies Ltd., the
largest BIOS maker, began offering
flash EPROM versions of its products
last spring.) BIOS upgradability will
let you take advantage of new powermanagement breakthroughs and laptop periphera1s without buying a new
machine.
Flash EPROMs have one disadvantage that slightly limits their use:
writing data to them takes nearly as
much time as writing to a floppy. For
this reason, they aren't as efficient as
regular RAM at running applications
like word processors and databases,
which involve opening and closing
files regularly. Flash EPROM proponents admit that computers based on
the technology will sometimes use
traditional DRAM storage for data
manipulation, with flash EPROM
cards taking the place of floppy and
hard disks.
All the major laptop vendors are
considering flash EPROMs, according
to Kurt Robinson, Intel's product line
architect for flash EPROMs. "Just
about everybody is updating the'
BIOS portion of their machines from

ROM to flash," Robinson says. In addition, Microsoft has thrown its support behind the technology by releasing file-management software that
lets MS-DOS treat flash EPROMs like
disk drives.
Intel expects steady increases in
flash EPROM storage density at least
through 1996. One-megabit chips are
selling now, two-megabit versions
should be available later this year, and
four-megabit chips should follow in
1991. When 16-megabit chips arrive
by 1994, vendors could introduce
32MB and 48MB ·hard drives· on a
card roughly two by three inches.
Texas Instruments (TI) is offering a
similar technology that uses less power than Intel's flash EPROMs during
data writing. In the typical flashEPROM computeJ; all logic and memory operations require five volts of
electricity, except for writing to the
flash EPROM, which takes 12 volts.
TI's new chips e1iminate the need for
a 12-volt power supply anywhere in
the machine, saving space and
weight. 256-kilobit chips are already
available, with one-megabit versions
expected by the end of this year.
Production efficiencies and price
competition are likely to drive flash
EPROM prices down to the level of
dynamic RAM chips by 1994, Robinson asserts. By then, the whir of disk
drives could be little more than a fastfading memory.

6-420

inter

DOMESTIC SALES OFFICES

ALABAMA

FLORIDA

MICHIGAN

OHIO

VIRGINIA

Intel Corp.
5015 Bradford Or., #2
Huntsville 35805
Tel: (205) 830-4010
FAX: (205) 837-2640

tlntel Corp.
BOO Fairway Drive

tlntal Corp.

tlntal Corp."
3401 Park Center Drive
Suite 220

tlntel Corp.
9030 Stony Point Pkwy.
Suite 360
Richmond 23235
Tel: (804) 330-9393
FAX: (804) 330-3019

ARIZONA

tlntal Corp.
410 North 44th Street

SUite 500
Phoenix 85008
Tel: (602) 231-0386
FAX: (602) 244-0446

~nJ~k~~tona Lisa Rd.

Suite 215
Tucson 85741
Tel: (602) 544-0227
FAX: (602) 544-0232
CALIFORNIA

tlntel Corp.
21515 Van owen Street
Suite 116
Canoga Park 91303
Tel: (818) 704-8500
FAX: (818) 340-1144
tlntal Corp.
300 N. Continental Blvd.
Suite 100
El Segundo 90245
Tel: (213) 640-6040
FAX: (213) 640-7133
Intel Corp.
1 Sierra Gate Plaza
Suite 280C
Roseville 95678
Tel: (916) 782-8086
FAX: (916) 782-8153
tlntal Corp.
9665 Chesapeake Dr.
Suite 325
San Diego 92123
Tel: (619) 292-8086
FAX: (619) 292-0628
tlntel Corp.·
400 N. Tustin Avenue
Suite 450
Santa Ana 92705
Tel: (714) 835-9642
TWX: 910-595-1114
FAX: (714) 541-9157
tlntel Corp."
San Tomas 4
2700 San Tomas Expressway
2nd Floor
Santa Clara 95051
Tel: (408) 986-8086
TWX: 910-338-0255
FAX: (408) 727-2620
COLORADO
Intel Corp.
4445 Northpark Drive
Suite 100
Colorado Springs 80907
Tel: (719) 594-0022
F~: (303) 594-0720
tlntel Corp. *
600 S. Cherry S1.
Suite 700
Denver 80222
Tel: (303) 321-8086
TWX: 910-931-2289
FAX: (303) 322-8670
CONNECTICUT

~~rL;O~rm Corporate Park

83 Wooster Heights Rd.
Danbury 06810
Tel: (203) 748-3130
FAX: (203) 794-0339

tSales and Servica Offica
·Field Application Location

Suite 160
Deerfield Beach 33441
Tel: (305) 421-0506
FAX: (305) 421-2444

7071 Orchard Lake Road
Suite 100
West Bloomfield 48322
Tel: (313) 851-8096
FAX: (313) 851-8770

tlntal Corp.
5850 T.G. Lee Blvd.

MINNESOTA

Suite 340
Orlando 32822
Tel: (407) 240-8000
FAX: (407) 240-8097

3500 W. 80th SI.
Suite 360

Intel Corp.
11300 4th Street North
SUite 170
St. Petersburg 33716
Tel: (813) 577-2413
FAX: (813) 578-1607
GEORGIA
tlntel Corp.
20 Technology Parkway
Suite 150
Norcross 30092
Tel: (404) 449-0541
FAX: (404) 605·9762
ILLINOIS
t1ntel Corp.·
Woodfield Corp. Center III
300 N. Martingale Road
Suite 400
Schaumburg 60173
Tel: (708) 605-8031
FAX: (709) 706-9762
INDIANA
tlntel Corp.
8910 Purdue Road
Suite 350
Indianapolis 46268
Tel: (317) 875-0623
FAX: (317) 875-8938
IOWA
Intel Corp.
1930 St. Andrews Drive N.E.
2nd Floor
Cedar Rapids 52402
Tel: (319) 393-5510
KANSAS
tlntal Corp.
10985 Cody S1.
Suita 140
Overland Park 66210
Tel: (913) 345-2727
FAX: (913) 345-2076
MARYLAND
tlntel Corp.·
10010 Junction Dr.
Suite 200
Annapolis Junction 20701
Tel: (301) 206·2860
FAX: ~3011206-3677
30t 206-3678
MASSACHUSETTS
tlntal Corp. *
Westford Corp. Center
3 Carlisle Road
2nd Floor
Westford 01886
Tel: (508) 692-0960
TWX: 710-343-6333
FAX: (508) 692-7867

Dayton 45414
Tel: (513) 890-5350
TWX: 810-450-2528
FAX: (513) 890-8858

tlntsl Corp."
25700 SCience Park Dr.

tlntal Corp.

~~~.o~~n.,~t~~~~
iVix~-916-576-2867
FAX: (612) 831-6497
MISSOURI

l~ci~' ~~~'City Expressway
Suite 131
Earth Ci~ 63045
Tel: (314 291-1990
FAX: (314) 291-4341
NEW JERSEY
tlntel Corp.·
Uncroft Office Center
125 Ha~ Mile Road
Red Bank 07701
Tel: (908) 747-2233
FAX: (908) 747-{)983

Suite 100
Beachwood 44122
Tel: (216) 464-2736

BeHevue 98004
"Iei: (~uoJ ..53·guou

OKLAHOMA

TWX: 910-443-3002
FAX: (206) 451-9556

Intel Corp.
6801 N. Broadway
Suite 115
Oklahoma City 73162
Tel: (405) 848-8086
FAX: (405) 840-9819

tlntel Corp.·
400 Penn Center Blvd.
Suite 610
Office Park

~~~7t;~r 8~~2J~70

FAX: (412) 829-7578

ONTARIO
tlntel Semiconductor of
Canada, Ltd.
2650 Queensview Drive
Suite 250
Ottawa K2B 8H6
Tel: (613) 829-9714
FAX: (613) 820-5936

TEXAS
Intal Corp.
8911 N. Capital of Texas Hwy.
Suite 4230
Austin 78759
Tel: (512) 794-8086
FAX: (512) 338-9335

tlntel Corp.
5800 Executive Center Dr.
Sune 105
Charlotte 28212
Tel: (704) 568-8966
FAX: (704) 535-2236
tlntal Corp.
5540 Centerview Dr.
Suite 215

~:I~\%~ &7:2t9537

FAX: (919) 851-8974

BRITISH COLUMBIA
Intel Semiconductor of
Canada, Ltd.
4585 Caneda Way
Suite 202
Burnaby V5G 4L6
Tel: (804) 298-0387
FAX: (604) 298-8234

PUERTO RICO

tlntal Corp.
300 Wastage Business Center
Suite 230
Fishkill 12524
Tel: (914) 897-3860
FAX: (914) 897-3125

NORTH CAROLINA

CANADA

tlntal Corp.
South Industrial Park
P.O. Box 910
Las Piedras 00671
Tel: (809) 733-8616

tlntal Corp.·
2950 Express Dr., South
Suite 130
Islandia 11722
Tel: (516) 231-3300
TWX: 510-227-6236
FAX: (516) 348-7939

Intel Corp.
Seventeen State Street
14th Floor
New York 10004
Tel: (212) 248-8086
FAX: (212) 248-0888

WISCONSIN
Intel Corp.
330 S. executive Dr.
Suite 102
Brookfield 53005
Tel: (414) 784-8087
FAX: (414) 796-2115

PENNSYLVANIA

NEW YORK
Intal Corp.·

~J~' ~~Ul1an

Road
Suite 102
Spokane 99206
Tel: (509) 928-8086
FAX: (509) 928-9467

OREGON
tlntel Corp.
15254 N.W. Greenbrier Pkwy.
Building B
Beaverton 97006
Tel: (503) 645-8051
TWX: 910-467-8741
FAX: (503) 645-8181

tlntel Corp.·
925 Harvest Drive
Suite 200
Blue Bell 19422
Tel: (215) 641-1000
FAX: (215) 641-0785

~p~~~s:ra

155 tOath Avenue N.E.
Suite 386

FfJ: \~~~~4~J:9~~:!

Intel Corp.
280 Corporate Center
75 Uvingston Avenue
First Floor
Roseland 07068
Tel: (201) 74O-{)111
FAX: (201) 740-0626

Tel: (716) 425-2750
TWX: 510-253-7391
FAX: (716) 223-2561

WASHINGTON

tlntal Corp.

tlntel Corp.·
12000 Ford Road
Suite 400
Dallas 75234
Tel: (214) 241-8087
FAX: (214) 484-1180
tlntsl Corp.·
7322 S.w. Freeway
Suite 1490
Houston n074
Tel: (713) 988-8086
TWX: 910-881-2490
FAX: (713) 988-3860
UTAH
tlntal Corp.
428 Eest 6400 South
Suite 104

~.::~r(l0~~8051

FAX: (801) 288-1457

tlntal Semiconductor of
Canada, ltd.
190 Attwell Drive
Suite SOO
Rexdale M9W 6He
Tel: (416) 675-2105
FAX: (416) 675-2438
QUEBEC
tlntel Semiconductor of
Canada, Ltd.
1 Rue Holiday
Suite 115
Tour East
Pt. Claire H9R 5N3
Tel: (514) 694-9130
FAX: 514-694-0064

DOMESTIC DISTRIBUTORS
ALABAMA
ArraN Eleclronlcs, Inc.

1015 Henderson Road
Huntsville 35805
Tel: (205) 837-6955
FAX: 205-751-1581

Hamllton/Avnet Computer
~=~~~rg:~~ Drive
Hamllton/Avnet Electronics
4940 Research Drive

tArrow Electronics, Inc.
2961 Dow Avenue

1~~~ g=~,:~~~up

Tustin 92680
Tel: (714) 838·5422
TWX: 910·595-2880

Irvine 92714
Tel: (714) 863-9953
TWX: 910-371·7127

337 Northlake BMI., SuHe 1000
Alta Monte Springs 32701
Tel: (407) 634-9090
FAX: 407-634-0865

Hamilton/Avnet Computer

twyle Distribution Group
26677 W. Agoura Rd.
Calabasas 91302
Tel: (818) 880-9000
TWX: 372-0232

Deerfield Beach 33442
Tel: (305) 428-6877
FAX: 305-481-2950

3170 Pullman Street
Coste Mesa 92626

Hamilton/Avnst Computer
1381 B West 190th Street
Gardena 90248

Hamilton/Avnet Computer

Huntsville 35805
Tel: (205) 837-7210
FAX: 205-721-0356

Sacramento 95834

~lJo~:~~:6~

Hamilton/Avnet Computer
4545 Viewridge Avenue

4103 Northgate Blvd.

SuHe 120

San Diego 92123

Huntsville 35806

Hamilton/Avnet Computer
1175 Bordeaux Drive'

Tel: (205) 830-9526
FAX: (205) 830-9557

PioneerfTechnolQgies Group, Inc.
4825 Universl1y Square
Huntsville 35805
Tel: (205) 837·9300
FAX: 205-837-9358
ALASKA

Hamilton/Avnet Computer
1400 W. Benson Blvd., Suite 400

tHamllton/Avnet Electronics

~:xrJ~~.~s11~g

ARIZONA

Sunnyvale 94086
Tel: (408) 743·3300
TWX: 910-339-9332

Phoenix 85040

tHamilton/Avnet Electronics

4545 Ridgeview Avenue

Hamilton/Avnet Computer
30 South McKemy Avenue

TWX: 910·595-2638

Hamilton/Avnet Computer
90 South McKemy Road
Chandler 85226

~:~ gif£o5~~~?~00

21150 Califa St.
Woodland Hills 91376
Tel: (818) 594-0404
FAX: 818-594-8233

tHamiltonJAvnet Electronics
10950 W. Washington Blvd.
Culver CHy 20230
Tel: (213) 558-2458
TWX: 910-340-6364

Hamilton/Avnet Electronics

Wyle Distribution Group
4141 E. Raymond
Phoenix 85040
Tel: (602) 249-2232
TWX: 910-371-2871
CAUFORNIA

ArraN Commercial System Group
1502 Crocker Avenue

~:n:{g)~5371

FAX: (415) 489-9393

Arrow Commercial System Group
14242 Chambers Road

Tustin 92680
Tel: (714) 544-0200
FAX: (714) 731-8438

tArrow Electronics, Inc.

tHamilton/Avnet Electronics
1361B West 190th Street

Gardena 90248
Tel: (213) 217-6700

tHamilton/Avnet ElectroniCS
4103 Northgate Blvd.

Pioneer{Technologies Group. Inc.
134 Rio Robles
San Jose 95134
Tel: (408) 954-9100
FAX: 408-954-91 I 3

Wyle Distribution Group
7431 Chapman Ave.
Garden Grove 92641
Tel: (714) 891 -1717
FAX: 714-891-1621
tWyle Distribution Group

tArrow Electronics, Inc.

twyIe Distribution Group
9525 Chesapeake Drive

851 I Rldgehaven Court

~:r gife!'~~:Oo
FAX: 619-279-6062

tArrow Electronics. Inc.

2951 Sunrise Blvd., Suite 175
Rancho Cordova 95742
Tel: (916) 638-5282

f.~~lia~{~~~~~1

TWX: 710-476-0162
Commerce Drive
Danbury 06810

Danbury 06810
Tel: (203) 797-2800

TWX: 710-456-9974
tPloneer/Standard Electronics
112 Main Street
Norwalk 06851
Tel: (203) 853-1515
FAX: 203-838-9901

tArrow Electronics, Inc.
400 Fairway Drive
Tel: (305) 429-8200
FAX: 305-428-3891

Lake Marv 32746
Tel: (407) 323-0252
FAX: 407-323-3189

HamlitonJAvnet Computer
6801 N.W. 15th Way

Tel: (404) 447-7500

~~~O~r~~~=!e~I:6~uP. Inc.
Norcross 30071
Tel: (404) 448·171 I
FAX: 404-446-8270
ILLINOIS

tArrow Electronics. Inc.
1140 W. Thorndale
Itasca 80143
Tel: (708) 250-0500
TWX: 708-250-D916

Hamihon/Avnet Computer
1130 Thorndale Avenue
Bensenville 60106
tHamiltOn/Avnot Electronics
1130 Thorndale Avenue
Bensenville 60106

~r~&:~~~g
MTI Systems Sales
1100 W. Thorndale
Hosea 80143
Tel: (708) 773-2300

tPioneer/Standard Electronics
2171 Executive Dr., Suite 200
Addison 60101
Tel: (708) 495-9680
FAX: 709-495-9631
INDIANA

tArrow Electronics. Inc.
71 OS' Lakeview Parkway West Drive

~:WI~~~~nro~m~~!~r

fndlanapolis 48268
Tel: (317) 289-2071
FAX: 317-299-0255

St. Petersburg 33702

tHamilton/Avnet Electronics
6801 N.W. 15th Way
Ft. Lauderdale 33309
Tel: (305) 971 -2900
FAX: 305-971-5420

tHamiltonJAvnet Electronics

Hamllton/Avnet Computer
485 Gradle Drive
Carmel 48032

Hamilton/Avnet Electronics
485 Gradle Drive

~:I~ gif£05~~71

Carmel 48032
Tel: (317) 844-9333
FAX: 3t7-844-5921

TWX: 910-335-1590

3197 Tech Drive North
St Petersburg 33702
Tel: (813) 573-3930
FAX: 813-572-4329

9350 Priority Way

twyle Distribution Group

tHamlitonJAvnet Electronics

Sunnyvale 94086

6947 University Boulevard
Winter Park 32792

Tel: (408) 745-6600
TWX: 910-339-9371

Tel: (408) 727·2500
TWX: 408-988-2747

Tel: (407) 628-3888
FAX: 407-678-1878

tCertified Technical Distributor

Norcross 30092

Ft. Lauderdale 33309

3000 Bowers Avenue
Santa Clara 95051

521 Wadden Drive

~~i~n~~~~\r~~~~~rs E.

TWX: 810-766-0432

~~i~~~~~ Drive
.

Deluth 30136

~~~~-~~

CONNECnCIIT

tArrow Electronics, Inc.

Wyle Distribution Group

tArrow Electronics. Inc.
4250 E. Rivergreen Parkway

'tHamiltonJAvnet Electronics
5825 0 Peachtree Corners
Norcross 30092

Deerfield Beach 33441

Tel: (916) 920-3150

Deluth 30139
Tel: (404) 623-8825
FAX: (404) 623-8802

Tel: (303) 457-8953
TWX: 910-936-0770

Suite 102

Sacramento 95834

19748 Dearbom Street
Chatsworth 9131 I

~~'il~~~~~g

twyle Distribution Group
451 E. 1241h Avenue
Thornton 80241

FLORIDA

TWX: 910-340-6364

124 Maryland Street
EI Segundo 90254
Tel: (213) 322·8100

~~3~~~~~~=

tHamiitonJAvnet Electronics
Commerce Industrial Park
Commerce Drive

Mad~n Drive
Tempe 85281
Tel: (802) 231-5140
TWX: 910-850-0077

30 South McKemy
Chandler 85226
Tel: (602) 961 -6869
FAX: 802·961-4073

9605 Maroon Circle, Ste. 200
Engelwood 80112

~~~~~%~V'~~u~~~F~~~~

tHamilton/Avnet Electronics

'tHamiltonlAvnet Electronics

505 S.

HamlhonJAvnet Computer

tArrow Electronics, Inc.
12 Beaumont Road

Tel: (802) 437-0750
TWX: 910-951-1550

Chandler 85226

~80wtf.cc~~~= ~:m Group

SuHe 200
Englewood 80112

tHamilton/Avnet Electronics
1175 Bordeaux Drive

4134 E. Wood Streot

GEORGIA

7080 South Tucson Way
Englewood 801 I 2
Tel: (303) 79D-4444

Hamilton/Avnet Electronics

Anchorage 99503

tArrow Electronics, Inc.

COLORADO

tHamiltonJAvnet Electronics
9605 Maroon Circle

3170 Pullman Street
Costa Mesa 92626

~~~'ar:;~~a~lies Group. Inc.

Arrow Electronics, Inc.

Sunnyvale 94089
21150 Califa Street
Woodland Hills 91367

tPioneerrrechnologies Group, Inc.

tPioneer/Standard Electronics

West Drive
Indianapolis 46250
Tel: (317) 573-0880
FAX: 317-573-D979

DOMESTIC DISTRIBUTORS {Contd.}
IOWA

Hamilton/Avnet Computer

Hamilton/Avnst Computer

2215 S.E. A-5
Grand Rapids 49506

Fairlield 07006

~f~go8~~d~~tR~,m&~e{oo

tHamllton/Avnet Electronics
1 Keystone Ave., Bldg. 36

Novl46050

Cherry HIli 08003
Tel: (609) 424-0110
FAX: 609-751-2552

915 33rd Avenue SW

Cedar Rapids 52404

HamiltonfAvnet Electronics
915 33rd Avenue, S.W.
Cedar Rapids 52404
Tel: (319) 362-4757
KANSAS

Arrow Electronics, Inc.
8208 Melrose Dr.. Suite 210
Lanexa 66214
Tel: (913) 541-9542
FAX: 913-541-0326

Hamilton/Avnet Computer
15313 W_ 95th Street

lenexa 61219
tHamilton/Avnet Electronics
15313 W. 95th

Overland Park 66215
Tel: (913) 868-6900
FAX: 913-541-7951

Hamilton/Avnet Electronics
2215 29th Street S.E.

Space AS
Grand Rapids 49508
Tel: (616) 243-8805
FAX: 616-696-1631
MamillolljAvlltli ~itl ... i.lvl·.;~ii

41650 Garden Brook
Novl46050 .
Tel: (313) 347-4271
FAX: 313-347-4021

tPloneerlStandard Electronics
4505 Broadmoor S.E.
Grand Rapids 49508
Tel: (616) 696-1600
FAX: 616-696-1631

tPioneer/Standard Bectronics
13465 Stamford

Hamilton/Avnet Computer
10 Industrial Road

tHamilton/Avnet Electronics
10 Industrial
Fairfield 07006
Tel: (201) 575-3390
FAX: 201-575-5839

~M~s~~~ems Sales
Fairlield 07006
Tel: (201) 227-5552
FAX: 201-575-8336

tPioneerlStandard ElectroniCS
14-A Madison Rd.

Fairfield 07006
Tel: (201) 575-3510
FAX: 201-575-3454

KENTUCKY

livonia 48150

NEW MEXICO

Hamilton/Avnet Electronics

~J&f~~~l::J:~g

Alliance Bectronics Inc.
10510 Research Avenue
Albuquerque 87123

805 A. Newtown Circle
Lexington 40511
Tel: (606) 259-1475
MARYLANO

tArrow Electronics, Inc.
8300 Guilford Drive
Suite H, River Center
Columbia 21046
Tel: (301) 995-8002
FAX: 301-361-3654

Hamilton/Avnet Computer

MINNESOTA

tArrow Electronics, Inc.
5230 W. 73rd Street
Edina 55435
Tel: (612) 830-1800
TWX: 910-576-3125

Hamilton/Avnet Computer
12400 Whitewater Drive
Minnetonka 55343

Columbia 21045

tHamilton/Avnet Electronics
12400 Whitewater Drive
Minnetonka 55434

tHamiiton/Avnet Electronics

Tel: (612) 932-0600
TWX: 910-576-2720

6622 Oak Hall Lane

Columbia 21045
Tel: (301) 995-3500
FAX: 301 -995-3593

~~:~~!t~:'~cro~~r8r.

Columbia 21046
Tel: (301) 290-8150
FAX: 301-290-6474

tPioneerlTechnologies Group, Inc.
9100 Gaither Road
Gaithersburg 20877
Tel: (301) 921-0660
FAX: 301-921-4255
MASSACHUSElTS

Arrow ElectroniCS, Inc.
25 Upton Or.
Wilmington 01887
Tel: (506) 658-0900
TWX: 710-393-6770

Hamilton/Avnet Computer
10 D Centennial Drwe
Peabody 01960

tHamilton/Avnet Electronics
10D Centennial Drive
Peaibody 01960
Tel: (506) 532-9838
FAX: 508-596-7802

tPioneer/Standard Electronics
7625 Golden Triange Dr.
SUiteG
Eden Prairie 55343
Tel: (612) 944-3355
FAX: 612-944-3794
MISSOURI

tArrow ElectroniCS, Inc.
2360 Schuetz
51. Louis 83141
Tel: (314) 587-6688
FAX: 314-567-1164

Hamilton/Avnet Computer
739 Goddard Avenue
Chesterfield 83005

tHamitton/Avnet Electronics
741 Goddard
Chesterfield 83005
Tel: (314) 537-1600
FAX: 314-537-4248

~:1~il~~~~~n~~~~~~:~r
Raieigh 27604

tHamilton/Avnet Electronics
~;1~g~~~~~orest DrWe
Tel: (919) 878-0819
TWX: 510-926-1836

~~~e~~q:u;~~~~~:~: g~3.P' Inc.
Charlotte 26210
Tel: (919) 527-11186
FAX: 704-522-8564

~~~~e~e~~T~~~~~:;roup,

Albuquerque 87109
Tel: (505) 765-1500
FAX: 505-243-1395
NEW YORK

tArrow Electronics, Inc.
3375 Brighton Henrietta Townline Rd.
Rochester 14623

OHIO

Arrow Commercial System Group
284 Cramer Creek Court
Dublin 43017
Tel: (614) 669-9347
FAX: (614) 889-9680

Tel: (716) 427-0300
TWX: 510-253-4768

tArrow Electronics, Inc.
6238 Cochran Road
Solon 44139

Arrow Electronics, Inc.
20 Oser Avenue

Tel: (216) 248-3990
TWX: 610-427-9409

Hauppauge 11786
Tel: (516) 231-1000
TWX: 510-227-6623

~~~~~r~:o~Vru~~rDr.

Hamilton/Avnet Computer
933 Motor Parkway
Haupauge11788

Cayton 45459

Hamilton/Avost Computer
30325 Bainbridge Rd., Bldg. A
Solon 44139

Hamilton/Avnst Computer
2060 Townline
Rochester 14623

tHamilton/Avnet Electronics

tHamliton/Avnet Electronics
933 Motor Parkway
Hauppauge 11766
Tel: (516) 231-9800
TWX: 510-224-11166

Tel: (513) 439-8733
FAX: 513-439-6711

lJ.~o~'fs~~ton

Village Cr.

30325 Bainbridge
Solon 44139
Tel: (216) 349-5100
TWX: 810-427-9452

Tel: (614) 682-7004
FAX: 614-882-8650

MICHIGAN

Tel: (201) 536-0900
FAX: 201-538-0900

~~~~~~~~v~~~~rlo~~6

Cherry Hill 06003

Tel: (315) 437-0266
TWX: 710-541-1560

•

tHamilton/Avnet Electronics

Hamilton/Avnet Electronics
103 Twin Oaks Drive
Syracuse 13206

Unij 11
Marllon 06053
Tel: (609) 596-6000
FAX: 609-596-9832

Inc.

Suite 148
Durham 27713
Tel: (919) 544-5400
FAX: 919-544-5885

Bedford 03102

Hamllton/Avnet Computer
444 East Industrial Park Dr.
Manchester 03103

tArrow Electronics, Inc.

tCertified Technical Distributor

tArrow ElectroniCS, Inc.

.:" .. " r..· ............. i", 0".. 1"1
Fia.ii
gh·27604-··' .. _--

Tel: (919) 876-3132
TWX: 510-926-1856

777 Brooksedge Blvd.

tArrow Electronics
6 Century Drive
Parsipanny 07054

livonia 48152

NORTH CAROUNA

Tel: (716) 272-2744
TWX: 510-253-5470

iArrow Electronics, Inc.
4 East Stow Road

Tel: (313) 665-4100
TWX: 810-223-6020

Tel: (716) 381-7070
FAX: 716-381-5955

NEW HAMPSHIRE

Tel: (617) 681-9200
FAX: 617-1183-1547

19880 Haggerty Road

tHamiiton/Avnet Electronics
5659A Jefferson N.E.

tPioneer/Standard Electronics
840 Fairport Park
Fairport 14450

Hamilton/Avnet Computer
2 Executive Park Drive

NEW JERSEY

Tel: (617) 272-7300
FAX: 617-272-6809

Hamilton/Avnet Computer
5659 Jefferson, N.E. Suites A & B
Albuquerque 87109
-

:o~~~s;,~;~s~~~t 11797

Tel: (516) 921-6700
FAX: 516-921-2143

tHamilton/Avnet Electronics
2060 Townline Rd.
Rochester 14623

tPioneer/Standard Electronics
44 Hartwell Avenue
lexington 02173

Wyle Distribution Group
15 Third Avenue
Burlington 01803

Tel: (505) 292-3360
FAX: 505-292-6537

tPioneer/Standard Electronics

Hamilton/Avnet Computer
Westerville 43081

Hamilton/Avnet Electronics
777 Brooksedge Blvd.

WesterviUe 43081

~~~a~~e~ksg~:e

Tel: (614) 862-7004

Port Washington 11050

23400 Commerce Park Road
Beachwood 44122

Tel: (516) 621-6200
FAX: 510-223-0846

Pioneer/Standard Electronics
68 Corporate Drive
Binghamton 13904
Tel: (607) 722-9300
FAX: 607-722-9562

MTI Systems Sales
Tel: (216) 464-8688

tPioneerlStandard Electronics
4433 Interpoint Boulevard

~:rr5~ ~~~-9900
FAX: 513-236-8133

Pioneer/Standard Electronics
40 Oser Avenue
Hauppauge 11787

tPioneer/Standard Electronics
Cleveland 44105

Tel: (516) 231-9200
FAX: 510-227-9869

Tel: (216) 567-3600
FAX: 216-663-1004

4800 E. 131st Street

DOMESTIC DISTRIBUTORS (Contd.)·
OKLAHOMA

Arrow Electronics, Inc.
4719 South Memorial Dr.
Tulsa 74145

tHamiiton/Avnet Electronics

12121 E. 51st St., Su~e 102A
Tulsa 74146
Tel: (918) 252·7297

Hamihon/Avnet Computer
1807A West Braker Lane
Austin 78758

HamlitonlAvnet Computer
17761 Northeast 78th Place
Redmond 98052

Hamllton/Avnet Computer
Forum 2
4004 Behline, Suite 200

Redmond 98052

Dallos 75244

!:s~lre~~Ah~n~~~~f~{oo

OREGON

Stafford 77477

tAimac Electronics Corp.

tHamiiton/Avnet Electronics
1807 W. Braker Lane

1885 N.w. 169th Place
Beaverton 97005

~~:(~W.~tso;I0

=1~~:~:t~I~~~:Ave.
Beaverton 97005

tHamilton/Avnet Electronics
9409 S.W. Nimbus Ave.
Beaverton 97005
Tel: (503) 827·0201
FAX: 503-641·4012
Wyle

9640 Sunshine Court
Bldg. G, Su~e 200

Beaverton 97005
Tel: (503) 643·7900
FAX: 503·646-5468
PENNSYLVANIA

Arrow Electronics, Inc.
650 Seco Road

Monroeville 15146
Tel: (412) 856-7000

Hamllton/Avnet Computer

WISCONSIN

Misslssuaga L4V 1M5

tHamiiton/Avnet Electronics

Arrow Electronics, Inc.
200 N. Patrick Blvd., Ste. 100
Brookfield 53005
Tel: (414) 792-0150
FAX: 414-792-0t56

~~i~~:~t ~:J'uler

Austin 78758
Tel: (512) 837-8911

4004 Be~line, Suite 200
Dallas 75234
Tel: (214) 308-811t
TWX: 910-860-5929

tHamilton/Avnet Bectronlcs

4850 Wright Rd., Su~e 190
Stsfford 77477
Tel: (713) 240-7733
TWX: 910-881-5523

tPloneer/Standard Electronics
182&-0 Kramer
Austin 78758
Tel: (512) 835-4000
FAX: 512-835-9829

tploneer/Standard Electronics
13710 Omega Road
Dallas 75244
Tel: (214) 386-7300
FAX: 214-490-6419

Tel: (713) 4954700
FAX: 713-495-5642

Pioneer/Standard Electronics

Un~s7&8

TWX: 910-874-1319

Hamilton/Avnet Electronics

(41~) 2814150

Wyle Distribution Group

Hamilton/Avnet Computer
Canada System Engineering
Group
3688 Nashua Drive
Mississuaga L4V 1M5
Hamilton/Avnel Compuler
3688 Nashua Drive

tPioneer/Standard Electronics
10530 Rockley Road
Houston 77099

~~a.ob~i~'~~

1776t N.E. 78th Place
Tel: (206) 881-6697
FAX: 206-867-0159
15385 N.E. 90th Street
Redmond 98052
Tel: (206) 881-1150
FAX: 206-881-1567

2800 Liberty Ave., Bldg. E
Pittsburgh 15222

Tel:

tHamihon/Avnet Electronics

tArrow Electronics, Inc.
1093 Meyerside, Unit 2
Mississaugs LST 1M4
Tel: (416) 673-7769
FAX: 416-672-0849

tWyle Distribution Group

1810 Greenville Avenue
Richardson 75081

~~~to8:::~~brr~~:r

Su~e 400
Waukesha 53186

tHamilton/Avnel Electronics
28875 Crossroads Circle
Suite 400
Waukesha 53186
Tel: (414) 784-4510
FAX: 414-784-9509

CANADA

Un~s 9 & 10

Un~s

7, 8, & 9

Mississuaga L4V 1R2
Hamilton/Avnet Computer
190 Colonade Road
Nepean K2E 7J5

tHamilton/Avnet Electronics
6845 Rexwood Road
Un~3-4-5

Mississauga L4T 1R2
Tel: (416) 677-7432
FAX: 416-677-0940

tHamiiton/Avnet Electronics
190 Colonnade Rood South
Nepean K2E· 7LS
Tel: (613) 226-1700
FAX: 613-226-1164

ALBERTA

tZentronics
1355 Meyerside Drive
Mississauga L5T 1C9

Hamilton/Avnet Computer
2816 21 sl Sireet Northeast

Tel: (416) 564-9600
FAX: 416-564-8320

Calgary T2E 6Z2

tZentronics
155 Colonnade Road
Unit 17

Hamilton/Avnet Electronics
2816 21st Street N.E. #3

¥~1:9~'6:!j2M~lj86
FAX: 403-250-159t

Nepean K2E 7Kl
Tel: (613) 226-8640
FAX: 613-226-6352

259 Kappa Drive
Pittsburgh 15238
Tel: (412) 782-2300
FAX: 412-983-8255

Tel: (214) 235-9953
FAX: 214-644-5064

Zentronlcs

QUEBEC

6815 #8 Street N.E.

Arrow Electronics Inc.

UTAH

tPloneerfTechnologies Group, Inc.
Delaware Valley

Haml~nlAvnet

¥::g~'6:!j~~l~818

1100 SI. Regis
Dorval H9P 2T5
Tel: (514) 421-7411
FAX: 514-421-7430

BRITISH COLUMBIA

Arrow Electronics, Inc.
500 Boul. St-Jean·Baptiste

261 Gibraltar Road
Horsham 19044
Tel: (215) 6744000
FAX: 215-674-3107
TENNESSEE

Arrr:m Commercial System Group
3635 Knight Rosd
Suite 7

~e'i~(g~\~ ~~~g540

Computer
1585 West 2100 South
Salt Lake City 64119

tHamiiton/Avnet Electronics

Suite 100
FAX: 403-295-8714

tHamiHon/Avnet ElectroniCS
8610 Commerce Ct.
Burnaby VSA 4N6

1585 West 2100 South
Salt Lake City 84119
Tel: (801) 972-2800
TWX: 910-925-4018

Tel: (604) 420-4101
FAX: 604-437-4712

twyle Distribution Group

Zentronics

1325 West 2200 South

Suite E

~':h~~og ~~~~~ort Rosd

FAX: (901) 367-2081

~~:Sl~~I~'7~~~

TEXAs

WASHtNGTON

ONTARIO

Arrow Electronics, Inc.
3220 Commander Drive

tAlmac Electronics Corp.

Arrow Electronics, Inc.
36 Antares Dr., Unit 100

75006
Tel: (214) 380-6464
FAX: (214) 248-7208

Bellevue 98007

carrol~n

1Certifred Technical Distributor

14380 S.E. Eostgate Way
Tel: (206) 643-9992
FAX: 206-643-9709

Tel: (604) 273-5575
FAX: 604-273-2413

Nepeen K2E 7W5
Tel: (613) 226-8903
FAX: 613-723-20t8

Su~e 280
Quebec G2E 5R9
Tel: (418) 871-7500
FAX: 418-871-6816

Hamilton/Avnet Computer
2795 Rue Halpem
SI. Leurent H4S 1P8

tHamlltonJAvnet Electronics
2795 Halpern
SI. Leurent H2E 7Kl
Tel: (514) 335-1000
FAX: 514-335-2481

tZentronics
520 McCaffrey

St. Laurent H4T 1N3
Tel: (514) 737-9700
FAX: 514-737-5212

EUROPEAN SALES OFFICES
FINLAND

ITALY

SWEDEN

UNITED KINGDOM

Intel GmbH

Intel Rnland OY

Intel Corporation Iialia S.p.A.
Milanofiori Palazzo E

Intel Sweden A.B.
Dalvagen 24

Intel Corporation (U.K.) ltd.

Abraham Lincoln Strasse 16-18
6200 Wiesbaden

Pipers Way

17136 Solna
Tel: (46) 8 734 01 00
Tl.X: 12261

Tel: (44) (0793) 696000
Tl.X: 444447/8

RUDsiiantie 2
00390 Helsinki

20094 Assago

Tel: (358) 0544644
Tl.X: t 23332

Milano
Tel: (39) (02) 89200950
Tl.X: 341286

Swindon, Wiltshire SN3 1RJ

~~t~lu~~~g~~~pS3~3R.L.
Tel: (33) (t) 30 57 70 00
Tl.X: 699016
ISRAEL

Intel Semiconductor Ltd.
Atidim Industrial Park-Neve Sharet

NETHERLANDS

SWITZERLAND

WEST GERMANY

Intel Semiconductor B.V.
Postbus 64130
3099 CC Rotterdam

Intel Semiconductor A.G.
Zuerichstrasse
8185 Winkel·Rueti be; Zuerich

Inlel GmbH
Dornacher Strasse 1
B016 Feldklrchen be; Muenchen

Tel: (31) 10.407.11.11
Tl.X: 22283

Tel: (41) 01/860 62 62
Tl.X: 8259n

Tel: (49) 089/90992-0
FAX: (49) 089/904/3948

7000 Stuttgart 80

Tel: (49) 0711/7287-280
Tl.X: 7-254826

SPAIN

Intel Iberia SA

P.O. Box 43202

Zurbaran, 28

Tel-Aviv 61430

28010 Madrid
Tel: (34) (1) 308.25.52
Tl.X: 46880

Tel: (972) 03-498080
Tl.X: 371215

Inlel GmbH

Zettachring lOA

FRANCE

78054 St Quenlin·en-YveJines
Cedex

Tel: (49) 06121/7605-0
Tl.X: 4-186183

EUROPEAN DISTRIBUTORS/REPRESENTATIVES
AUSTRIA

IRELAND

NORWAY

UNITED KINGDOM

Rapid Recall, Ltd.

Bacher Electronics G.m.b.H.
Rotenmuehlgasse 26
1120 Wien

~;~~~~e~~c;t~ark

Nordisk Elektronikk (Norge) NS
Postboks t23

Accent Electronic Components Ltd.
Jubilee House, Jubilee Road

Glenageary
Co. Dublin

Smedsvingen 4
1364 Hvalstad

28 High Street
Nantwich
Cheshire CW5 5AS

Tel: (21) (353) (01) 856288
~~Y8lf53) (01) 857364

Tel: (47) (02) 846210
Tl.X: 77546

Tel: (43) (0222) 83 56 46
Tl.X: 31532
BELGIUM

Inelco Belgium S.A.
Av. des Croix de Guerre 94
1120 Bruxelles
?1~O~~~~rnlaan, 94
Tel: (32) (02) 21601 60
Tl.X: 64475 or 22090
DENMARK

ITI-Multlkomponent
Naverland 29
2600 Glostrup
Tel: (45) (0) 2 45 66 45
Tl.X: 33 355
FINLAND

OY Fintronic AB
Melkonkatu 24A
00210 Helsinki

fti;

PORTUGAL
ISRAEL

Eastronics Ltd.
11 Aozanis Street

Rua Dos Lusiados, 5 Sala B
1300 Lisboa

P.O.B. 39300
Tel-Aviv 61392
Tel: (972) 03-475151
Tl.X: 33638

Tel: (35) (1) 648091
Tl.X: 61562

ITALY

Tel: (35) (1) 64 5313
Tl.X: 14182

Intesi
Divisions In Industries GmbH
Viale Milanofiori
Palazzo E/5

~~~9~~8~~J~Jl

Tl.X: 311351

Tl.X: 124224

Lasi Elettronica S.pA
V. Ie Fulvia Testi, 126
20092 Cinisello Balsamo (MI)

FRANCE

Tel: (39) 02/2440012
Tl.X: 352040

Tel: (358) (0) 6926022

Almex
Zone industrielle d'Antony
48, rue de l'Aubepine
BP 102

92164 Antony cedex
Tel: (33) (1) 46 66 21 12
Tl.X: 250067

Jermyn
60, rue des Gemeaux
Silic 580

¥:~3~u(~?~9C;~~~ 78

Tl.X: 261585

~~J~o~'?t~ieres

4, avo Laurent-Cery
92606 Asnieres Cedex
Tel: (33) (1) 47906240
Tl.X: 611448

Tekelec-Airtronic
Cite des Bruyeres
Rue Carle Vemet - BP 2
92310 Sevres
Tel: (33) (1) 45 34 75 35
Tl.X: 204552

ATD Portugal LOA

Telcom S.r.1.
Via M. Civitali 75
20148 Milano
Tel: (39) 02/4049046
Tl.X: 335654

ITT Multicomponents
Viale MllanoflOrl E/5

~~~~g~~~J~Jl

Ditram
Avenida Miguel Bombarda, 133
1000 Lisboa

SPAIN

ATD Electronica, S.A.
Plaza C;udad de Viena, 6
28040 Madrid
Tel: (34) (1) 2344000
Tl.X: 42477

Metrolagia Iberica, S.A.
CtTa. de Fuencarral, n.SO
28100 Alcobendas (Madrtd)
Tel: (34) (1) 653 86 11

Tel: (39) 02/49961
Tl.X: 332189

Nordisk Elektronik AB
Torshamnsgatan 39
Box 36
164 93 Kista
Tel: (46) 08-034630
Tl.X: 10547
SWITZERLAND

Industrade A.G.
Hertistrasse 31
8304 Wallisellen
Tel: (41) (01) 8328111
Tl.X: 56788

NETHERLANDS

Koning en Hartman
Elektrotechniek B.V.
Energieweg 1
2627 AP Delft
Tel: (31) (1) 15/609906
Tl.X: 38250

~r:'te~~~~ents Ltd.
Chineham Business Park
Crockford Lane
Basingstoke

TURKEY

EMPA Electronic
Lindwurmstrasse gSA
8000 Muenchen 2
Tel: (49) 089/53 80 570
Tl.X: 528573

Tel: (0270) 627505
FAX: (0270) 629883
TWX: 36329
WEST GERMANY

Electronic 2000 AG

~b~~~~~~~~n 1:2

Hants RG24 OW~
Tel: (0256) 707107
FAX: 0256-707162

Tel: (49) 089/42001-0
Tl.X: 522561

Conformix
UnitS
AI M Business Centre
Dixons Hill Road
Welham Green
South Hatfield

Bahnhofstrasse 44
7141 Moeglingen

HertsAL97JE
Tel: (07072) 73282
FAX: (07072) 61678

In Multikomponent GmbH
Postfach 1265
Tel: (49) 07141/4879
Tl.X: 7264472

Jermyn GmbH
1m Dachsstueck 9
6250 Limburg

Bytech Systems
3 The Western Centre
Western Road
Bracknell RG12 1RW

Tel: (49) 06431/508-0
Tl.X: 415257-0

Tel: (44) (0344) 55333
FAX: (44) (0344) 867270
TWX: 849624

~oBJ1riir;2~!~~~~e7~9

Jermyn
SWEDEN

Tl.X: 311351

Silverstar
Via Dei Gracchl 20
20146 Milano

Letchworth, Herts 8G6 10H
Tel: (44) (0462) 670011
FAX: (44) (0462) 682467
TWX: 826505

Vestry Estate
Otlord Road

Sevenoaks
Kent TN14 5EU
Tel: (44) (0732) 450144
FAX: (44) (0732) 451251
TWX: 95142
MMO Ltd.

3 Bennet Court
Bennet Road
Reading
Berkshire RG2 oax

Tel: (44) (0734) 313232
FAX: (44) (0734) 313255
TWX: 84B689

Rapid Recall, Ltd.
Rapid House

Metrologie GmbH
Tel: (49) 089/78042-0
Tl.X: 5213189

Proelectron Vertriebs GmbH
Max Planck Strasse 1-3
6072 Dreieich
Tel: (49) 06103/30434-3
Tl.X: 417903
YUGOSLAVIA

H.R. Microelectronics Corp.
2005 de 10 Cruz Blvd., Ste. 223
Santa Clara, CA 95050
U.S.A.
Tel: (1) (408) 988-0286
Tl.X: 387452

High Wycombe
Buckinghamshire HPl t 2EE

Rapido Electronic Components
S.p.a.
Via C. Beccaria, 8
34133 Trieste

Tel: (44) (0494) 26271
FAX: (44) (0494) 21860 .
TWX: 837931

11;1110
Tel: (39) 040/360555
Tl.X: 460461

Oxford Road

INTERNATIONAL SALES OFFICES
Intel Japan KKKswa-asa Bldg. '
2-11-5 Shin-Yokohama
Kohoku-ku, Yokohama-shi
Kanagawa, 222
Tol: 045-474-7661
FAX: 045-471-4394

AUSTRALIA

INDIA

Intel Australia Ply. Ltd.
Unft 13
Aflamble Grove Business Park
25 Frenchs Forest Road East
Tol: 61-2975-3300
FAX: 61·2975-3375

Intel Asia Electronics, Inc.
4/2. Samrah Plaza
SI. Mark's Road
Bangalore 560001
Tol: 011-91·812-215055
TLX: 953-845-2846 INTL IN
FAX: 091-812-215067

BRAZIL

JAPAN

i~O~=~I~saka 560

Intel Semioondutores do Brazil LIDA
Av. Paulista, 1159-CJS 404/4D5
01311 - Sao Paulo - S.P.
Tol: 55-11-287-5899
TLX: 3911153146IS08
FAX: 55-11·287-5119

Intel Japan KK

FAX: 06-863-1084

5-6 Tokodal, Tsukuba-shi
Ibarakl, 300-26 ,
Tol: 0298-47-8511
TLX: 3656-160
FAX: 0298-47·8450

Intol Japan KK
Shlnmaru Bldg.
1-5-1 Marunouchl
Chlyoda-ku, Tokyo 1DO
Tol: 03-201·3621
FAX: 03-201-6650
Intel Japan K.K.
Groon Bldg.
1-16-20 Nishiki
Naka-ku, Nagoya-shl
Aichl450
Tol: 052-204-1261
FAX: 052-204-1285

Frenchs forest, NSW. 2086

~~~~~~~~~g.

SINGAPORE
Intel Singapore Technology, Ltd.
101 Thomson Road #21-05106
UnHod Squara
Singapore 1130
Tel: 250-7811
TLX: 39921 INTEL
FAX: 250-9256

2..~H Terauchi

CHINA/HONG KONG

Intel PAC Corporation
15/F, OIIice 1, CHic Bldg.
Jlan Guo Mon Wal Street

r.l1''ilt :~50

TLX: 22947 INTEL CN
FAX: (1) 500-2953

Intel Semiconductor Ltd. *
10lF East Tower
Bond Center
Quoonsway, Control

~!~~~=~g~~ld9.

1..ijsa9 Fuchu-cho
Fuchu-shi, Tokyo 183
Tol: 0423-60-7871
FAX: 0423-60-0315
Intel

K.K*

~~'Hon~'W~

Kumagaya-shl, Sanama 360
Tol: 0465-24-6871
FAX: 0485-24-7518

~~~M~)~

TAIWAN

llr~~T;::'Il'~,r:ar East Ltd.
Bank Tower Bldg.
Tung Hua N. Road
Taipei
Tel: 886-2-716·9660
FAX: 886-2-717-2455

kOREA
Intel Korea, Ltd.
16th Floor, Ufo Bldg.
61 Yoldo·dong, Youngdeungpo-Ku
Sooul 150-010

~,<~t81~~E~~~' B386

FAX: (852) 868-1989

FAX: (2) 784-8098

INTERNATIONAL DISTRIBUTORS/REPRESENTATIVES
ARGENTINA
Dalsys S.R.L.
Chacebuco, 9D-6 Piso
1069-Buenos Aires
Tol: 54-1-334-7726
FAX: 54-1-334-1871
AUSTRALIA
Email Electronics
15-17 HUmo Street
Huntingdale, 3166
Tel: 011-61-3-544-8244
TLX: M30B95
FAX: 011-61-3-543-8179
NSD·Austraila

~ ~:~d~:~~~~2~d.

Tol: 03 8900970
FAX: 03 8990819

Mlcronic Devices
No. 516 5th Roor
Swastik Chambors
Slon, Trombay Road
Chembur

~~'lr3f\(W1l7 MOEV
Mlcronlc Devices
2518, 1st Roor
Bada Bazaar Marg
Old Rajinder Nagar
Now Deihl 110 060
Tel: 011-91-11·5723509
011-91-11-589771
TLX: 031-63253 MONO IN
Micronic Devices
8-3-348/12A Owarakapurl Colony
Hyderabad 50D 482
Tel: 011-91-842-226748

BRAZIL
'Elebra ComPQnentes
Rua Garsldo Aausina Gomes, 78
7Andar
04575 - Sao Paulo - S.P.
Tol: 55-11-534-9641
TLX: 55-11-54593/54591
FAX: 55-11-534-9424

S&S Corporation
1587 Kooser Road
San Joss, CA 95118
Tel: (408) 976-6216
TLX: 820281
FAX: (408) 978-6635

CHINA/HONG KONG
Novel Precision Machinery Co., Ltd.
Room 728 Trado Square
681 Choung Sha Wan Road
Kowloon, Hong Kong
Tel: (852) 360-8999
1WX: 32032 NVTNL HX
FAX: (852) 725-3695

Asahi Electronics Co. Ltd.
KMM Bldg. 2-14-1 Asano
Kokurakita·ku

INDIA
Micronlc

Kawasakl-shi, Kanagawa 213
Tel: 044-852-5121
FAX: 044-877-4268

~evices

~n55CoOm~~x Road
Basavanagudl

~:r~~f~I~r,'2~D-631

011·91-812-811-385
TLX: 9538458332 MOBG

-Field Application Location

JAPAN

~'a'~~~-~_~~~2
FAX: 093-551-7861

CTC Compononts Systoms Co., Ltd.
4-8·1 Oobashi, Miyamae-ku

Ole Semlcon Systams, IQc.
Flower Hili Shlnmachl Hlgashl·kan
1-23-9 Shin machi, Setagaya-ku
Tokyo 154
Tol: 03-439-1600
FAX: 03-439-1601

~~"ra=o

~~~'1i~:~:la6shi 460
FAX: 052-204-2901
Ryoyo Eloctro Corp.
Konwa Bldg.
1-12·22 Tsukiji

~~~g:~~~J'd'l'1104
FAX: 03-546-5044

NEW ZEALAND

Email Eleclronlcs
36 Olivo Road
Penrose. Auckland
Tel: 011-64-9-591-155
FAX: 011-64-9-592-681
SINGAPORE

KOREA

Electronic Resources Pte, Ltd.

J·Tek Corporation
Dong Sung Bldg. 9/F
158·24, Samsung-Dong, Kangnam-Ku
Seoul 135-090
Tel: (822) 557·8039
FAX: (822) 557-8304

1336
Tel: (65) 2B3-0BB8
TWX: AS 56541 EAS
FAX: (55) 289·5327

Samsung Eleclron~s
Samsung MaIn BId~.
~af&r_~~~-RO- KA, Chung-Ku

SOUTH AFRICA

C.P.O. Box 8780
Tol: (822) 751-3680

1WX: KORSST K 27970
FAX: (822) 753-9065

MEXICO
SSB Electronics, Inc,
675 Palomar Street, Bldg. 4, Suite A
Chula Vista, CA 92011
Tol: (619) 585-3253
TLX: 287751 CBALL UR
FAX: (619) 585·6322
Oicopal S.A.
Tochtli 368 Fracc. Ind. San Antonio
Azcapotzalco
C.P. 02760-Mexico, O.F.
Tol: 52-5-561-3211
TLX: 177 3790 Dicome
FAX: 52·5-561-1279
PHI S.A. do C.V.
Fco. Villa esq. Ajusco sin
Cuemavaca- Morelos
Tol: 52-73-13-9412
FAX: 52-73-17-5333

::~~',""?;n~~~re

i~~~~!;~~i~:~foil~~~':eyet St.)

Meyerspark, Pretoria, 0184
Tel: 011-2712-803-7680
FAX: 011·2712-603-8294
TAIWAN

Micro Electronics COrporation
12th Floor, Section 3

~:~~~~~~~ast Road
Tel: (BB6) 2-7198419
FAX: (BB6) 2-7197916
Acer Sertek Inc.
15th Floor, Section 2
Chien Kuo North Ad.
Taipall8479 R.O.C.
Tol: 886-2-501-0055
1WX: 23756 SEATEK
FAX: (BB6) 2-5012521

DOMESTIC SERVICE OFFICES
ALASKA

CONNEcnCUT

MARYLANO

NEW YORK

PUERTO RICO

Intel Corp.

;~ite~o~rm Corporate Park

U'ntel Corp.

*ln1el Corp.
2950 Expressway Dr. South
Suite 130
Islandia 11122
Tel: (516) 231-3300

Inlel Corp.
South Industrial Park
P.O. Box 910
Las Piedras 00671
Tel: (809) 733·8616

C/o TransAJaska Network
1515 Lore Rd.

r.1~~g~~~e5~~lo;'76
Intel Corp.

c/o TransAlaska Data Systems

~~ ~~'hCf;.~~~~e 407

Fairbanks 99701
Tel: (907) 452-6264
AHIZUNA

*Intel Corp.
410 North 44lh Streel
Suite 500
Phoenix 85008
Tel: (602) 231-0386
FAX: (602) 244-0446
*Intel Corp.
500 E. Fry Blvd., Suile M-15
Sierra Vista 65635
Tel: (602) 459-5010
ARKANSAS
Inlel Corp.

r5~~~::lp,;er~~ive
UtIle Rock 72204
CALIFORNIA
'*Intel Corp.
21515 Vanowen St., Ste. 116

~~~'iBf8~"{~J~gg

*Intel Corp.
3DO N. Continental Blvd.
Sunel00
EI Segundo 90245
Tel: (213) 640-6040
*Inte! Corp.

~~::;.r;~~~na'5~~·

Tel: (916) 351-6143

*Intel Corp.
9665 Chesapeake Dr., Suite 325

~:I~ ~~&O~~~~6

**Intel Corp.
400 N. Tustin Avenue
SuHe 450
Santa Ana 92705
Tel: (714) 83&-9642
'**Intel Corp.
2700 San Tomas Exp., 1st Aoor
Santa Clara 95051
Tel: (408) 970-1747
COLORAOO
*Intel Corp.
600 S. Cherry Sl, Suite 700
Denver 80222
Tel: (303) 321-8086

83 Wooster Heights Rd.
Danbury 06811
Tel: (203) 748·3130
FLORIDA

**Inlel Corp.
BOO Fahway Dr., Suite 160
Deerfield Beach 33441
Tel: (305) 421-0506
FAX: (305) 421·2444
*Intel Corp.
5850 T.G. Lee Blvd., Sle. 340
Orlando 32822
Tel: (407) 240-8000
GEORGIA
*Intel Corp.
20 Technology Park. Suite 150
Norcross 30092
Tel: (404) 449-0541
5523 Theresa Street
Columbus 31907

10010 Junction Dr., Suite 200
Annapolis Junction 20701
Tel: (301) 206'2860
MASSACHUSETIS

Intel Corp.

TEXAS

**Intel Corp.
Westford Corp. Center
3 Carlisle Rd., 2nd Floor
Westford 01886
Tel: (508) 692-0960

Fishkill 12524
Tel: (914) 897-3860

Westech 360. Suite 4230
8911 Capitol of Texas Hwy.
Austin 78752-1239
Tel: (512) 794-8086

MICHIGAN

.. u..u ........... w" ...." ..........
Syracuse 13211
Tel: (315) 454-0576

*'ntel Corp.
7071 Orchard Lake Rd., Sle. 100
West Bloomfield 48322
Tol: (313) 851·8905
MINNESOTA
*Intel Corp.
3500 W. 80th St., Suite 360

~~~~~~n21~~lli

HAWAII

MISSISSIPPI

**Inlel Corp.
Honolulu 96820
Tel: (808) 847-6738

Intel Corp.
c/o Compu-Care
2001 Airport Road, Suite 205F
Jackson 39208
Tel: (601) 932·6275

ILLINOIS

;;~n~W~~O~rp.

Center III
300 N. Martingale Rd., Ste. 400
Schaumburg 60173
Tel: (708) 605·8031

MISSOURI

;~~I~a':t~·CiIy Exp., Sle.131

INDIANA

Earth Ci~ 63045
Tel: (314 291-1990

*\ntel Corp.
8910 Purdue Rd., Ste. 350
Indianapolis 46268
Tel: (317) 87&-0623

Intel Corp.
Route 2, Box 221
Smilhville 64089
Tel: (913) 345-2727

KANSAS

NEW JERSEY

'*Intel Corp.
10985 Cody, Suite 140
Overland Park 66210
Tel: (913) 345-2727

'**Intel Corp.
300 Sylvan Avenue
Englewood Cliffs 07632
Tel: (201) 567-0821

KENTUCKY

*Intel Corp.
Parkway 109 Office Centsr
328 Newman Springs Road
Red Bank 07701
Tel: (201) 747-2233

Inlel Corp.
133 Walton Ave., Office 1A
Lexington 40508
Tel: (606) 255·2957
Inlel Corp.
898 Hillcrest Road, Apt. A
Radcliff 40160 (louisville)
LOUISIANA
Hammond 70401
(serviced from Jackson, MS)

NEW MEXICO
Intel Corp.
Rio Rancho 1
4100 Sara Road
Rio Rancho 87124-1025
(near Albuquerque)
Tel: (505) 893-7000

:~~~~o~~~~e:~ Center
Ln12~SO!R' U_II_.,

" __

NORTH CAROLINA
*Inlel Corp.
5600 Executive Center Drive
Suite 105
Charlotte 28212
Tel: (704) 568-8966
**lntel Corp.
5540 Centerview Dr., SUite 215
Raleigh 27606
Tel: (919) 851-9537
OHIO

MARYLAND

2700 San Tomas Expressway
Sonta Clara 95051
Tel: .1-800-328-0386

10010 Junction Dr.
Suite 200
Annapolis Junction 20701
Tel: 1-800-328-0386

NEW YORK

3500 W. BOth Street
Suite 360
Bloomington 55431
Tel: (612) 835-6722

2950 Expressway Dr., Soulh
Islandia 11722
Tel: (506) 231-3300

*Qarry-in locations
**Carry-in/mail-In locations

;~~~e~~ofPreeway, Suite 1490
Houston 77074
Tel: (713) 988·8086
UTAH
Intel Corp.
428 East 6400 South
Suite 104
Murray 84107
Tel: (801) 263-8051
FAX: (801) 268-1457
VIRGINIA
*Intel Corp.
1504 Santa Rosa Rd., Sle. 108
Richmond 23288
Tel: (804) 282-5668

'*Intel Corp.
25700 SCience Park'Dr., Ste. 100
Beachwood 44122
Tel: (216) 464-2736

WASHINGTON

OREGON
**Intel Corp.
15254 N.W. Greenbrier Parkway
Building B
Beaverton 97005
Tel: (503) 645-8051
PENNSYLVANIA
*tlntel Corp.
925 Harvest DrIve
Suite 200
Blue Bell 19422
Tel: (215) 641-1000
1·800-468-3548
FAX: (215) 641-0785
**tlntel Corp.
400 Penn Cenler Blvd., Sle. 610
Pittsburgh 15235
Tel: (412) 823-4970
*Intel Corp.
1513 Cedar Cliff Dr.
Camp Hill 17011
Tel: (717) 761-(1860

SYSTEMS ENGINEERING OFFICES
MINNESOTA

"'jilli"iGvl/oJ'
12000 Ford Rd., SUite 401
Dallas 75234
Tel: (214) 241·8087

**Inlel Corp.
3401 Park Center Dr., Ste. 220
Dayton 45414
Tel: (513) 890-5350

CUSTOMER TRAINING CENTERS
CALIFORNIA

**lntel Corp.

'**Intel Corp.
155 lOath Avenue N.E., Ste. 386
Bellevue 98004
Tel: (206) 453·8086

CANADA
ONTARIO
*'*Intel Semiconductor of
Canada, Ltd.
2650 Queensview Dr., Ste. 250
Ottawa K2B 8H6
Tel: (613) 829·9714
**Intel Semiconductor 01
Canada, Ltd.
190 Attwell Dr., Sle. 102
Rexdale (Toronto) M9W 6H8
Tel: (416) 675-2105
QUEBEC
**Intel Semiconductor of
Canada, Lid.
1 Rue Holiday
Sulle115
Tour East
Pt. Claire H9R 5N3
Tel: (514) 694-9130
FAX: 514-694-0064

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