1991_Intel_Memory_Products 1991 Intel Memory Products

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Intel Corporation is a leading supplier of microcomputer components,
modules and systems. When Intel invented the microprocessor in 1971, it
created the era of the microcomputer. Today, Intel architectures are considered
world standards. Whether used in embedded applications such as automobiles,
printers and microwave ovens, or as the CPU in personal computers, client
servers or supercomputers, Intel delivers leading-edge technology.

MEMORY PRODUCTS

1991

About Our Cover.'
Thinkers, inventors, and artists throughout history have breathed
life into their ideas by converting them into rough working sketches, models,
and products. This series of covers shows a few of these creations, along
with the applications and products created by Intel customers.

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
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iSBC, iSBX, iSDM, iSXM, Library Manager, MAPNET, MCS, Megachassis,
MICROMAINFRAME,
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©INTEL CORPORATION 1990

CUSTOMER SUPPORT
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
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After a customer purchases any system hardware or software product, service and support become major
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As you might expect, Intel's customer support is extensive. It can start with assistance during your development
effort to network management. 100 Intel sales and service offices are located worldwide-in the U.S., Canada,
Europe and the Far East. So wherever you're using Intel technology, our professional staff is within close
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HARDWARE SUPPORT SERVICES
Intel's hardware maintenance service, starting with complete on-site installation wiII boost your productivity
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Intel can provide support service for not only Intel systems and emulators, but also support for equipment in
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Software products are supported by our Technical Information Service (TIPS) that has a special toll free
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Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information Phone Service), updates and subscription service (product-specific troubleshootmg guides and;
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by the vendor. Intel offers network services and support structured to meet a wide variety of end-user computing needs. From a ground up design of your network's physical and logical design to implementation, installation and network wide maintenance. From software products to turn-key system solutions; Intel offers the
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Intel provides field system engineering consulting services for any phase of your development ,or application
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DATA SHEET DESIGNATIONS
Intel uses various data sheet markings to designate each phase of the document as it
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Data Sheet Marking

Description

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Contains information on products in the design phase of
development; Do not finalize a design with this
information. Revised information will be published when
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*Specifications within these data sheets are subject to change without notice. Verify with your local Intel sales
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Memory Overview

Memory Technologies
Dynamic RAMs
(Random Access Memories)
Static RAMs
(Random Access Memories)
EPROMs
(Erasable Programmable
Read Only Memories)
Flash Memories (Electrically
Erasable and Reprogrammable
Non..Volatile Memories)

Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xi

CHAPTER 1
Memory Overview
Memory Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

CHAPTER 2
Memory Technologies
Intel Memory Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

CHAPTER 3
Dynamic RAMs (Random Access Memories)
DATA SHEETS
21256 262,144 x 1-Bit Dynamic RAM with Page Mode .........................
2146465,536 x 4-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .
21010 1,048,576 x 1-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . .
21014 262,144 x 4-Bit Dynamic RAM with Page Mode .........................
21040 4,194,304 x 1-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . .
2D2569 256K x 9-Bit High Density Dynamic RAM Memory Module with Page Mode
21019 1,048,576 x 9-Bit Dynamic RAM Memory Module with Page Mode. . . . . . . ..
225636 256K x 36-Bit Dynamic RAM Memory Module with Page Mode .......... ,
251236 512K x 36-Bit Dynamic RAM Memory Module with Page Mode. . . . . . . . . ..
RELIABILITY REPORT
RR-62 Dynamic RAM Reliability Report ......................................

3-1
3-19
3-37
3-53
3-69
3-90
3-107
3-124
3-141
3-158

CHAPTER 4
Static RAMs (Random Access Memories)
DATA SHEETS
5116S/L 2K x 8-Bit CMOS Static RAM.. . .. . . . . .. . .. .. .. . . . .. . . .. . . .. . . . . . . . .
5164S/L 8K x 8-Bit CMOS Static RAM.. .. . . . . . . . . . . .. .. . . . .. .. . . . . .. . . .. . . . .
51256S/L 32K x 8-Bit CMOS Static RAM.....................................
51C68 High Speed CHMOS 4096 x 4-Bit Static RAM...........................
51C98 High Speed CHMOS 16,384 x 4-Bit Static RAM.........................
5164 High Speed 8192 x 8-Bit Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51256 High Speed 32K x 8-Bit Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51258 High Speed 64K X 4-Bit Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RELIABILITY REPORT
RR-63 Static RAM Reliability Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-1
4-9
4-18
4-26
4-32
4-39
4-47
4-56
4-63

CHAPTER 5
EPROMs (Erasable Programmable Read Only Memories)
DATA SHEETS
2716 16K (2K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2732A 32K (4K x 8) UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2764A 64K (8K x 8) UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27128A 128K (16K x 8) Production and UV Erasable PROMs ...................
27256 256K (32K x 8) Production and UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . .
27C256 256K (32K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27C512 512K (64K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . .
27C513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM. . . . . . . . . . . . . . . .
27C011 Page-Addressed 1M (8 x 16K x 8) EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C010 1M (128Kx8) CHMOS EPROM .....................................
27C100 1M (128K x 8) CHMOS EPROM .....................................
27C020 2M (256K x 8) CHMOS EPROM .....................................
27C040 4M (512K x,8) CHMOS EPROM.....................................
ix

5-1
5-9
5-18
5-28
5-38
5-50
5-62
5-72
5-85
5-100
5-113
5-124
5-134
5-144

Tabie of Contents (Continued)
27C210 1M (64K x 16) CHMOS EPROM .....................................
27C220 2M (128K x 16) CHMOS EPROM ....................................
27C240 4M (256K x 16) CHMOS EPROM ....................................
27C400 4M (256K x 16 or 512K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . ..
27960CX Pipelined Burst Access 1M (128K x 8) CHMOS EPROM ...............
27960KX Burst Access 1 M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . ..
APPLICATION NOTES
AP-329 68030/27960CX Burst EPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-346 29000/27960CX Burst EPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RELIABILITY REPORTS
RR-35 EPROM Reliability Data Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RR-67 EPROM Reliability Data Summary CHMOS III-E. . . . . . . . . . . . . . . . . . . . . . . ..
ARTICLE REPRINTS
AR-414 Marriage of CMOS and PLCC Sparking Rapid Change in Mounting
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-455 One Time Programmable EPROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-458 OTP EPROMs with Quick-Pulse Programming Offer Ideal Mass Production
Firmware Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-468 Keeping Data Safe with Nonvolatile Memory. . . . . . . . . . . . . . . . . . . . . . . . . ..

5-154
5-164
5-173
5-182
5-192
5-213
5-232
5-260
5-287
5-341

5-390
5-392
5-395
5-398

CHAPTER 6
Flash Memories (Electrically Erasable and Reprogrammable Non-Volatile
Memories)
Flash: A New Way to Deal with Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA SHEETS
28F256A 256K (32K x 8) CMOS Flash Memory ...............................
28F512 512K (64K x 8) CMOS Flash Memory................................ .
28F010 1024K (128K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28F020 2048K (256K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSM001 FLKA 1 Mbyte (512K x 16) CMOS Flash SIMM . .. . . . . .. .. . . . . . .. . .. . ...
iMC001FLKA 1-Megabyte Flash Memory Card ................................
iMC004FLKA 4-Megabyte Flash Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
APPLICATIt>N NOTES
AP-316 Using Flash Memory for In-System Reprogrammable Nonvolatile Storage.
AP-341 Designing An Updatable BIOS Using Flash Memory ....................
AP-343 Solutions for High Density Applications Using Intel Flash Memory ........
APPLICATION BRIEF
AB-25 Designing in Flexibility with a Universal Memory Site . . . . . . . . . . . . . . . . . . . ..
ENGINEERING REPORTS
ER-20 ETOX II Flash Memory Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
ER-24 The Intel 28F010 Flash Memory ......................................
ARTICLE REPRINTS
AR-463 Don't Write Off the U.S. in Memory Chips .............................
AR-466 Nonvolatility: Semi vs. Mag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ..
AR-470 A 90 ns 100K Erase/Program Cycle Megabit Flash Memory.............
AR-472 The Memory Driver ............................. :...................
AR-474 Memory Life-Cycle Cost............. ...............................
AR-478 Flash, Best of Two Worlds ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-484 PC Standard in the Cards ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-486 Flash Outshines ROM & EPROM ....................................
AR-490 Flash Memory Operates 10-20 Times Longer . . . . . . . . . . . . . . . . . . . . . . . ..
AR-491 Memory Breakthrough Drives Miniaturization ..........................

x

6-1
6-5
6-30
6-55
6-81
6-109
6-143
6-173
6-203
6-248
6-297
6-365
6-371
6-376
6-390
6-393
6-395
6-399
6-400
6-401
6-406
6-411
6-417
6-419

Alphanumeric Index
210101,048,576 x 1-Bit Dynamic RAM with Page Mode...............................
21014262,144 x 4-Bit Dynamic RAM with Page Mode................................
210191,048,576 x 9-Bit Dynamic RAM Memory Module with Page Mode................
21040 4,194,304 x 1-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21256 262,144 x 1-Bit Dynamic RAM with Page Mode .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21464 65,536 x 4-Bit Dynamic RAM with Page Mode .................................
225636 256K x 36-Bit Dynamic RAM Memory Module with Pag!3 Mode. . . . . . . . . . . . . . . . ..
251236 512K x 36-Bit Dynamic RAM Memory Module with Page Mode. . . . . . . . . . . . . . . . ..
27128A 128K (16K x 8) Production and UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . . . . . . .
2716 16K (2K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27256 256K (32K x 8) Production and UV Erasable PROMs ............. :.............
2732A 32K (4K x 8) UV Erasable PROMs ........................ . . . . . . . . . . . . . . . . . . .
27513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . .
2764A 64K (8K x 8) UV Erasable PROMs ........................ . . . . . . . . . . . . . . . . . . .
27960CX Pipelined Burst Access 1M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . ..
27960KX Burst Access 1M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C010 1M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C011 Page-Addressed 1 M (8 x 16K x 8) EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C020 2M (256K x 8) CHMOS EPROM . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C040 4M (512K x 8) CHMOS EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C100 1M (128Kx8) CHMOS EPROM ............................................
27C21 0 1M (64K x 16) CHMOS EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C220 2M (128K x 16) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C240 4M (256K x 16) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C256 256K (32K x 8) CHMOS EPROM ...........................................
27C400 4M (256K x 16 or 512K x 8) CHMOS EPROM· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C512 512K (64K x 8) CHMOS EPROM ...........................................
27C513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM ......................
28F010 1024K (128K x 8) CMOS Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28F020 2048K (256K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . .. . . .. . .. .. . . . . . . . . . .
28F256A 256K (32K x 8) CMOS Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28F512 512K (64K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2D2569 256K x 9-Bit High Density Dynamic RAM Memory Module with Page Mode. . . . . . .
5116S/L 2K x 8-Bit CMOS Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51256 High Speed 32K x 8-Bit Static RAM ..........................................
51256S/L 32K x 8-Bit CMOS Static RAM........................ ...................
51258 High Speed 64K x 4-Bit Static RAM ..........................................
5164 High Speed 8192 x 8-Bit Static RAM. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5164S/L 8K x 8-Bit CMOS Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
51 C68 High Speed CHMOS 4096 x 4-Bit Static RAM .................................
51C98 High Speed CHMOS 16,384 x 4-Bit Static RAM................................
AB-25 Designing in Flexibility with a Universal Memory Site. . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-316 Using Flash Memory for In-System Reprogrammable Nonvolatile Storage. . . . . . ..
AP-329 68030/27960CX Burst EPROM Interface ......... . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-341 Designing An Updatable BIOS Using Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-343 Solutions for High Density Applications Using Intel Flash Memory. . . . . . . . . . . . . ..
AP-346 29000/27960CX Burst EPROM Interface ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-414 Marriage of CMOS and PLCC Sparking Rapid Change in Mounting Memories. . . ..
AR-455 One Time Programmable EPROMs .........................................
AR-458 OTP EPROMs with Quick-Pulse Programming Offer Ideal Mass Production
Firmware Storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-463 Don't Write Off the U.S. in Memory Chips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-466 Nonvolatility: Semi vs. Mag .................................. ; ...... ". . . . . ..
AR-468 Keeping Data Safe with Nonvolatile Memory .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
xi

3-37
3-53
3-107
3-69
3-1
3-19
3-124
3-141
5-28
5-1
5-38
5-9
5-72
5-18
5-192
5-213
5-113
5-100
5-134
5-144
5-124
5-1.54
5-164
5-173
5-50
5-182
5-62
5-85
6-55
6-81
6-5'
6-30
3-90
4-1
4-47
4-18
4-56
4-39
4-9
4-26
4-32
6-365
6-203
5-232
6-248
6-297
5-260
5-390
5-392
5-395
6-390
6-393
5-398

Aiphanumeric index (Continued)
AR-470 A 90 ns 1OOK Erase/Program Cycle Megabit Flash Memory. . . . . . . . . . . . . . . . . . ..
AR-472 The Memory Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . ..
AR-474 Memory Life-Cycle Cost...................................................
AR-478 Flash, Best ofTwo Worlds. . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ..
AR-484 PC Standard in the Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-486 Flash Outshines ROM & EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-490 Flash Memory Operates 10-20 Times Longer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-491 Memory Breakthrough Drives Miniaturization.......................... .......
ER-20 ETOX II Flash Memory Technology :.........................................
ER-24 The Intel 28F01 0 Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Flash: A New Way to Deal with Memory ............................ '. . . . . . . . . . . . . .. . .
iMC001 FLKA 1-Megabyte Flash Memory Card.. .. .. . . .. .. .. . . .. . .. .. .. . .. .. .. .. . ....
iMC004FLKA 4-Megabyte Flash Memory Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Intel Memory Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .
iSM001 FLKA 1 Mbyte (512K x 16) CMOS Flash SIMM ...............................
Memory Overview .........................................................,......
RR-35 EPROM Reliability Data Summary .......................... ~ . . . . . . . . . . . . . . ..
RR-62 Dynamic RAM Reliability Report ........... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RR-63 Static RAM Reliability Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RR-67 EPROM Reliability Data Summary CHMOS III-E...............................

xii

6-395
6-399
6-400
6-401
6-406
6-411
6-417
6-419
6-371
6-376
6-1
6-143
6-173
2-1
6-109
1-1
5-287
3-158
4-63
5-341

Memory Overview

1

inter

MEMORY OVERVIEW

MEMORY BACKGROUND
AND DEVELOPMENT

computer systems' insatiable appetites for higher bit
capacities and faster access speeds.

Years ago, MOS LSI memories were little more than
laboratory curiosities. Any engineer brave enough to
design with semiconductor memories had a simple
choice of which memory type to use. The 2102 Static RAM for ease of use or the 1103 Dynamic RAM
for low power were the only two devices available.
Since then, the memory market has come a long
way, the types of memory devices have proliferated,
and more than 3,000 different memory devices are
.now available. Consequently, the designer has many
to choose from but the choice is more difficult, and
therefore, effective memory selection is based on
matching memory characteristics to the application.

RAM Types
Two basic RAM types have evolved since 1970. Dynamic RAMs are noted for high capacity, moderate
speeds and low power consumption. Their memory
cells are basically charge-storage capacitors with
driver transistors. The presence or absence of
charge in a capacitor is interpreted by the RAM's
sense line as a logical 1 or O. Because of the
charge's natural tendency to distribute itself into a
lower energy-state configuration, however, dynamic
RAMs require periodic charge refreshing to maintain
data storage.

Memory devices can be divided into two main categories: volatile and nonvolatile. Volatile memories
retain their data only as long as power is applied. In
a great many applications this limitation presents no
problem. The generic term random access memory
(RAM) has come to be almost synonymous with a
volatile memory in which there is a constant rewriting of stored data.

Traditionally, this requirement has meant that system designers had to implement added circuitry to
handle the dynamic RAM subsystem refresh. And at
certain times, when refresh procedures made the
RAM unavailable for writing and reading; the memory's control circuitry had to arbitrate access. LSI dynamic memory controllers reduce the refresh requirement to a minimal design by offering a monolithic controller solution.

Nonvolatile memories retain their data whether or
not power is applied. In some situations it is critical
that a nonvolatile device be used. An example of this
requirement would be retaining data during a power
failure. (Tape and disk storage are also non-volatile
memories but are not included within the scope of
this book, which confines itself to solid-state technologies in IC form.)
Thus, when conSidering memory devices, it's helpful
to see how the memory in computer systems is segmented by applications and then look at the state-ofthe-art in these cases.

Where users are less concerned with space and
cost than with speed and reduced complexity, the
second RAM type-static RAMs-generally prove
best. Unlike their dynamic counterparts, static RAMs
store ones and zeros using traditional flip-flop logicgate configurations. They are faster and require no
refresh. A user simply addresses the static RAM,
and after a very brief delay, obtains the bit stored in
that location. Static devices are also simpler to design with than dynamic RAMs, but the static cell's
complexity puts these volatile chips far behind dynamics in bit capacity per square mil of silicon.

Volatile Read/Write Memory

Nonvolatile Read-Only Memory
Another memory class, read-only memory (ROM), is
similar to RAM in that a computer addresses it and
then retrieves data stored at that address. However,
ROM includes no mechanism for altering the data
. stored at that address-hence, the term read only.

First examine read/write memory, which permits the
access of stored memory (reading) and the ability to
alter the stored data (writing).
Before the advent of solid-state read/write memory,
active data (data being processed) was stored and
retrieved from nonvolatile core memory (a magneticstorage technology). Solid-state RAMs solved the
size and power consumption problems associated
with core, but added the element of volatility. Because RAMS lose their memory when you turn off
their power, you must leave systems on all the time,
add battery backup or store important data on a
nonvolatile medium before the power goes down.

ROM is basically used for storing information that
isn't subject to change-at least not frequently. Unlike RAM, when system power goes down, ROM retains its contents.
ROM devices became very popular with the advent
of microprocessors. Most early microprocessor applications were dedicated systems; the system's
program was fixed and stored in ROM. Manipulated
data could vary and was therefore stored in RAM.
This application split caused ROM to be commonly
called program storage, and RAM, data storage.

Despite their volatility, RAMs have become very
popular, and an industry was born that primarily fed
1-1

inter

MEMORY OVERVIEW

The first ROMs contained cell arrays in which the
sequence of ones and zeros was established by a
metallization interconnect mask step during fabrication. Thus, users had to supply a ROM vendor with
an interconnect program so the vendor could complete the mask and build the ROMs. Set-up charges
were quite high-in fact, even prohibitive unless users planned for large volumes cif the same ROM.

EPROM or DRAM in bit capacity per square millimeter of silicon and the resulting lack of cost-effectiveness and density has caused it to lag behind other
memory technologies.
The latest advance·ment is Flash memory. Flash
memories combine the electrical erase capability of
the EEPROM with the simplicity, density and cost-effectiveness of EPROM cell layout. Modification to
the EPROM cell replaces block UV-erasure with
block electrical erasure, which can be accomplished
while the device is still installed in the host system.
Flash memory. can also be randomly read or written
by the local system microprocessor or microcontroller.

To offset this high set-up charge, manufacturers developed a user-programmable ROM (or PROM). The
first such devices used· fusible links that could be
melted or programmed with a special hardware system.
Once programmed, a PROM was just like a ROM. If
the program was faulty, the chip had to be discarded. But, PROMs furnished a more cost-effective way
to develop program memory or firmware for low-volume purposes than did ROMs.

The cost effectiveness and flexibility of Flash memory makes it applicable in code storage applications.
Code can be quickly and easily updated during prototyping, incoming test, assembly qr in the field,
quickly and easily. High density and nonvolatile
read/write capability also make Flash memory an
innovative alternative for mass storage, and integrating main memory and backup storage functions into
directly executable Flash memory boosts system
performance, shrinks system size, reduces power
requirements and increases reliability over that of
electromechanical media, especially in extreme environmental conditions.

As one alternative· to fusable-link programming, Intel
pioneered an erasable MOS-technology PROM
(termed an EPROM) that used charge-storage programming. It came in a standard ceramic DIP package but had a window that permitted die exposure to
light. When the chip was exposed to ultraviolet light,
high energy photons could collide with the EPROM's
electrons and scatter them at random, thus erasing
the memory.
The EPROM was not intended for use in read/write
applications, but it proved very useful in research
and development for prototypes, where the need to
alter the program several times is quite common.
Indeed, the EPROM market originally consisted almost exclusively of development labs. As the fabrication process became mature, and volumes increased, EPROM's lower prices made them attractive even for medium-volume production-system applications. Today, millions of EPROMs are used in
systems which require only periodic, off-line updates
of information and parameters.

APPLICATIONS OF MEMORY
DEVICES
Besides the particular characteristics of each device
that has been discussed, there are a number of other factors to consider when choosing a memory
product, such as cost, power consumption, performance, memory architecture and organization, and
size of the memory. Each of these factors plays an
important role in the final selection process.

Performance
Nonvolatile Read/Write Memory
Technology advances have blurred the traditional
lines drawn between read-only memories (ROMs)
and read/write memories (RAMs). The first alternative was the EPROM, which required removal from
the host system, placing it under ultraviolet light for
erasure, and subsequent reprogramming and reinstallation into the host system.
The next advancement was the introduction of a
nonvolatile memory that was electrically erasable
and user rewritable on a byte-by-byte basis, called
the EEPROM. The byte erase capability and highlevel of feature integration of the EEPROM came
with two penalties-density and cost. Cell and periphery complexity places EEPROM far behind

Generally, the term performance relates to how fast
the device can operate in a given system environment. This parameter is usually rated in terms of the
access time. Fast SRAMs can provide access times
as fast as 20 ns, while the fastest DRAM cannot go
much beyond the 100 ns mark. A bipolar PROM has
an access time of 35 ns. RAM and PROM access is
usually controlled by a ~nal most often referred to
as Chip Select (CS). CS often appears in device
specifications. In discussing access times, it is important to remember that in SRAMs and PROMs,
. the access time equals the cycle time of the system
whereas in DRAMs, the access time is always less
than the cycle time.

1-2

MEMORY OVERVIEW

Power consumption also depends upon the organization of the device in the system. Organization' usually refers to the width of the memory word. At the
time of their inception, memory devices were organized as nK x 1 bits. Today, they are available in
various configurations such as 4K x 1, 16K x 1, 64K
x 1, 1K x 4, 2K x 8, etc. As the device width increases, fewer devices are required to configure a given
memory word-although the total number of bits remains constant. The wider organization can provide
significant savings in power consumption, because a
fewer number of devices are required to be powered
up for access to a given memory word. In addition,
the board layout design is simpler due to fewer
traces and better layout advantages. The wider
width is of particular advantage in microprocessors
and bit-slice processors because most microprocessors are organized in 8-bit or 16-bit architectures. A
memory chip configured in the nK x 8 organization
can confer a definite advantage-especially in universal site applications. Conversely, there is usually
a small speed penalty, at the device level for a x8 or
x16 organization.

Cost
There are many ramifications to consider when evaluating cost. Often the cost of the physical device
used is the smallest portion of the total cost of using
a particular device. Total cost must comprehend
other factors such as design-in time, test expense,
update costs, as well as cost per bit, size of memory
power consumption, etc.
Cost of design time is proportional to design complexity. For example, SRAMs generally require less
design-in time than DRAMs because there is no refresh circuitry to consider. Conversely, the DRAM
provides the lowest cost per bit because of its higher
packing density. The cost of a service call to exchange or reprogram a ROM/PROM/EPROM versus an in-system update of a Flash memory costs
orders of magnitude more than the device itself.

Memory Size
Memory size is generally specified in the number of
bytes (a byte is a group of eight bits). The memory
size of a system is usually segmented depending
upon the general equipment category. Computer
mainframes and most of today's minicomputers use
blocks of read/write substantially beyond 64K
bytes-usually in the hundreds of thousands to millions of bytes.

Types of Memories
The first step to narrowing down your choice is to
determine the type of memory you are designingdata store or program store. After this has been
done, the next step is to prioritize the following factors:

The microprocessor user generally requires memory
sizes ranging from 2K bytes up to 64K bytes. In
memories of this size, the universal site concept allows maximum flexibility in memory design.

Performance
Power Consumption
Density
Cost

Power Consumption

SUMMARY

Power consumption is important because the total
power required for a system directly affects overall
cost. Higher power consumption requires bigger
power supplies, more cooling, and reduced device
density per board-all affecting cost and reliability.
All things considered, the usual goal is to minimize
power. Many memories now provide automatic power-down. With today's emphasis on saving energy
and reducing cost, the memories that provide these
features will gain an increasingly larger share of the
market.

Global Memory
Generally, a global memory is greater than 64K
bytes and serves as a main memory for a microprocessor system. Here, the use of dynamic RAMs or
Flash memory for read/write memory is dictated to
provide the highest density and lowest cost per bit.
The cost of providing refresh circuitry for the dynamic RAMs is spread over a large number of memory
bits, thus minimizing the cost impact.

In some applications, extremely low power consumption is required, such as battery operation. For
these applications, the use of devices made by the
CMOS technology have a distinct advantage over
the NMOS products. CMOS devices offer power
savings of several magnitudes over NMOS. Non-volatile devices such as EPROMs or Flash memories
are usually independent of power problems in these
applications.

Local Memory
Local memories are usually less than 64K bytes and
reside in the proximity of the processor itself-usuallyon the same PC board. Types of memories often
used in local memory applications are SRAM,
EPROM, Flash memory, and EEPROM.

1-3

Memory Technologies

2

INTEL MEMORY TECHNOLOGIES
Most of this handbook is devoted to techniques and
information to help you design and implement semiconductor memory in your application or system. In
this section, however, the memory chip itself will be
examined and the processing technology required to
turn a bare slice of silicon into high performance
memory devices is described. The discussion has
been limited to the basics of MOS (Metal Oxide
Semiconductor) technologies as they are responsible for the majority of memory devices manufactured
at Intel.

same silicon. Either p- or n-type silicon substrates
can be used, however, deep areas of the opposite
doping type (called wells) must be defined to allow
fabrication of the complementary transistor type.
Most of the early semiconductor memory devices,
like Intel's pioneering 1103 dynamic RAM and 1702
EPROM were made with PMOS technologies. As
higher speeds and greater densities were needed,
most new devices were implemented with NMOS.
This was due to the inherently higher speed of
n-channel charge carriers (electrons) in silicon along
with improved process margins. CMOS technology
has begun to see widespread commercial use in
memory devices. It allows for very low power devices used for battery operated or battery back-up applications. Historically, CMOS has been slower than
any NMOS device. However, CMOS technology has
been improved to produce higher speed devices.
The extra cost of processing required to make both
transistor types had kept CMOS memories limited to
those areas where the technology's special characteristics would justify the extra cost. In the future, the
learning curve for high performance CMOS costs
are making a larger number of memory devices
practical in CMOS.

There are three major MOS technology familiesPMOS, NMOS, and CMOS (Figure 1). They refer to
the channel type of the MOS transistors made with
the technology. PMOS technologies implement
p-channel transistors by diffusing p-type dopants
(usually boron) into an n-type silicon substrate to
form the source and drain. P-channel is so named
because the channel is comprised of positively
charged carriers. NMOS technologies are similar,
but use n-type dopants (normally phosphorus or arsenic) to make n-channel transistors in p-type silicon
substrates. N-channel is so named because the
channel is comprised of negatively charged carriers.
CMOS or Complementary MOS technologies combine both p-channel and n-channel devices on the

GATE

GATE

296102-2

296102-1
PMOS

NMOS

P-CHANNEL
DEVICE

N-CHANNEL
DEVICE
GATE

F.O.

P-SUBSTRATE

296102-3
CMOS

Figure 1. MOS Process Cross-sections

2-1

inter

INTEL MEMORY TECHNOLOGIES

In the following section, the basic fabrication sequence for an HMOS circuit will be described.
HMOS is a high performance n-channel MOS process developed by Intel for 5V single supply circuits.
HMOS, and CHMOS, CHMOS-E (EPROM) and
ETOXTM (Flash Memory), along with their evolutionary counterparts comprise the process family responsible for most of the memory components produced by Intel today.

Having fulfilled its purpose, the remaining silicon nitride layer is removed. A light oxide etch follows taking with it the underlying first oxide but leaving the
thick (field) oxide.
'
Now that the areas for active transistors have been
defined and isolated, the transistor types needed
can be determined. The wafer is again patterned
and then if special characteristics (such as depletion
mode operation) are required, it is implanted with
dopant atoms. The energy and dose at which the
dopant atoms are implanted determines much of the
transistor's characteristics. The type of the dopant
provides for depletion mode (n-type) or enhancement mode (p-type) operation.

The MOS IC fabrication process begins with a slice
(or wafer) of siJlgle crystal silicon. Typically, it's 100
or 150 millimeter in diameter, about a half millimeter
thick, and uniformly doped p-type. The wafer is then
oxidized in a furnace at around 1000°C to grow a
thin layer of silicon dioxide (Si02) on the surface.
Silicon nitride is then deposited on the oxidized wafer in a gas phase chemical reactor. The wafer is
now ready to receive the first pattern of what is to
become a many layered complex circuit. The pattern
is etched into the silicon nitride using a process
known as photolithography, which will be described
in a later section. This first pattern (Figure 2) defines
the boundaries of the active regions of the IC, where
transistors, capacitors, diffused resistors, and first
level interconnects will be made. .
ETCHED
AREAS

!

The transistor types defined, the gate oxide of the
active transistors are grown in a high temperature
furnace. Special care must be taken to prevent contamination or inclusion of defects in the oxide and to
ensure uniform consistent thickness. This is important to provide precise, reliable device characteristics. The gate oxide layer is then masked and holes
are etched to provide for direct gate to diffusion
("buried") contacts where needed.
The wafers are now deposited with a layer of gate
material. This is typically poly' crystaline silicon
("poly") which is deposited in a gas phase chemical
reactor similar to that used for silicon nitride. The
poly is then doped (usually with phosphorus) to bring
the sheet resistance down to 10-20 fi/square. This
layer is also used for circuit interconnects and if a
lower resistance is required, a refractory metal/polysilicon composite or refractory metal silicide can be
used instead. The gate layer is then patterned to
define the actual transistor gates and interconnect
paths (Figure 4).

~\

NITRIDE---....

OXIDE-'"

)

P-SUBSTRATE

296102-4

Figure 2. First Mask
The patterned and etched wafer is then implanted
with additional boron atoms accelerated at high energy. The boron will only reach the silicon substrate
where the nitride and oxide was etched away, providing areas doped strongly p-type that will electrically separate active areas. After implanting, the wafers are oxidized again and this time a thick oxide is
grown. The. oxide only grows in the etched areas
due to silicon nitride's properties as an oxidation barrier. When the oxide is grown, some of the silicon
substrate is consumed and this gives a physical as
well as electrical isolation for adjacent devices as
can be seen in Figure 3.
NITRIDE

P+

POLYSILICON

P-SUBSTRATE

296102-6

Figure 4. Post Gate Mask
The wafer is next diffused with n-type dopant .(typically arsenic or phosphorus) to form the source and
drain junctions. The transistor gate material acts as
a barrier to the dopant providing an undiffused channel self-aligned to the two junctions. The wafer is
then oxidized to seal the junctions from contamination with a layer of Si02 (Figure 5).

FIELD OX

P-SUBSTRATE

P+

P+
296102-5

Figure 3. Post Field Oxidation
2-2

inter

INTEL MEMORY TECHNOLOGIES

+ Vo

SECOND-LEVEL
POLYSILICON

FIELD
OXIDE

296102-7

Figure 5. Post Oxidation

P-SUBSTRATE

A thick layer glass is then deposited over the wafer
to provide for insulation and sufficiently low capacitance between the underlying layers and the metal
interconnect signals. (The lower the capacitance,
the higher the inherent speed of the device.) The
glass layer is then patterned with contact holes and
placed in a high temperature furnace. This furnace
step smooths the glass surface and rounds the contact edges to provide uniform metal coverage. Metal
(usually aluminum or aluminum/silicon) is then deposited on the wafer and the interconnect patterns
and external bonding pads are defined and etched
(Figure 6). The wafers then receive a low temperature (approximately 500°C) alloy that insures good
ohmic contact between the aluminum and diffusion
.
or poly.

EPROM/FLASH MEMORY CELL

296102-9

Figure 7. Double Poly Structure
After fabrication is complete, the wafers are sent for
testing. Each circuit is tested individually under conditions designed to determine which circuits will operate properly both at low temperature and at conditions found in actual operation. Circuits that fail
these tests are inked to distinguish them from good
circuits. From here the wafers are sent from assembly where they are sawed into individual circuits with
a paper-thin diamond blade. The inked circuits are
then separated out and the good circuits are sent on
for packaging.
Packages fall into two categories-hermetic and
non-hermetic. Hermetic packages are Cerdip, where
two ceramic halves are sealed with a glass fritt, or
ceramic with soldered metal lids. An example of hermetic package assembly is shown in Table 1. Nonhermetic packages are molded plastics.
The ceramic package has two parts, the base, which
has the leads and die (or circuit) cavity, and the metal lid. The base is placed on a heater block and a
metal alloy preform is inserted. The die is placed on
top of the preform which bonds it to the package.
Once attached, wires are bonded to the circuit and
then connected to the leads. Finally the package is
placed in a dry inert atmosphere and the lid is soldered on.

296102-8

Figure 6. Complete Circuit (without paSSivation)
At this point the circuit is fully operational, however,
the top metal layer is very soft and easily damaged
by handling. The device is also susceptible to contamination or attack from moisture. To prevent this
the wafers are sealed with a passivation layer of silicon nitride or a silicon and phosphorus oxide composite. Patterning is done for the last time opening
up windows only over the bond pads where external
connections will be made.

The cerdip package consists of a base, lead frame,
and lid. The base is placed on a heater block and
the lead frame placed on top. This sets the lead
frame in glass attached to the base. The die is then
attached and bonded to the leads. Finally the lid is
placed on the package and it is inserted in a seal
furnace where the glass on the two halves melt together making a hermetic package.

This completes basic fabrication sequence for a single poly layer process. Double poly processes such
as those used for high density Dynamic RAMs,
EPROMs, flash memories, and EEPROMs follow the
same general process flow with the addition of gate,
poly deposition, doping, and interlayer dielectric process modules required for the additional poly layer
(Figure 7). These steps are performed right after the
active areas have been defined (Figure 3) providing
the capacitor or floating gate storage nodes on
those devices.
.

In a plastic package, the key component is the lead
frame. The die is attached to a pad on the lead
frame and bonded out to the leads with gold wires.
The frame then goes to an injection molding machine and the package is formed around the lead
frame. After mold the excess plastic is removed and
the leads trimmed.
2-3

INTEL MEMORY TECHNOLOGIES

After assembly, the individual circuits are retested at
an elevated operating temperature to assure critical
operating parameters and separated according to
speed and power consumption into individual specification groups. The finished circuits are marked and
then readied for shipment.

PHOTOLITHOGRAPHY
The photo or masking technology is the most important part of the manufacturing flow if for no other
reason than the number of times it is applied to each
wafer. The manufacturing process gets more complex in order to make smaller and higher performance circuits. As this happens the number of masking steps increases, the features get smaller, and
the tolerance required becomes tighter. This is
largely because the minimum size of individual pattern elements determine the size of the whole circuit, effecting its cost and limiting its potential complexity. Early MOS IC's used minimum geometries
(lines or spaces) of 8-1'0 microns (1 micron = 1'0- 6
meter "" 1/25,'0'0'0 inch). The n-channel processes
of the mid 197'O's brought this down to approximately 5 microns, and today minimum geometries of one
micron are in production. This dramatic reduction

The basic process flow described above may make
VLSI device fabrication sound straightforward, however, there are actually hundreds of individual operations that must be performed correctly to complete a
working circuit. It usually takes well over two months
to complete all these operations and the many tests
and measurements 'involved throughout the manufacturing process. Many of these details are responsible for ensuring the performance, quality, and'reliability you expect from Intel products. The following
sections will discuss the technology underlying each
of the major process elements mentioned in the basic process flow.

Table 1. Typical Hermetic Package Assembly
Flow

ProcessiMaterlals

Typical Item

Frequency

Criteria

Waler
Die saw, wafer break
Die wash and plate
Die visual inspection

~

Passivation, metal

OAgate
Die attach
(Process monitor)

0f76, LTPD=5%

Wet out

4 x/operator/shift

0111 LTPD=20%

Orientation, lead
dressing, etc.

4 x/operator/
machine/shift

All previous items
Cap align, glass
integrity. moisture

every lot

11129, LTPD=3%

4 x /furnace/shift

0115, LTPD= 15%

Post die attach visual
Wire bond
(Process monitor)

100% 01 devices

Post bond inspection

f-o

OAgate
Seal and Mark
(Process monilor)

100% devices

Temp cycle

I," ~

2,4-

100% oldie
Every lot

lOx to mil std.
,883cond. C

Hermeticity check
(Process monitor)

F/G leak

100% devices

Lead Trim
(Process monitor)

Burrs, etc, (visual)
Fine leak

4 x/station/shift
2 x/station/shift

External visual

Solder voids, cap
alignment, etc.

100% devices

OAgate

All previous items

All lots

Class test
(Process monitor)

Run standards
(good and reject)
Calibrate every
system using
"autover" program

Every 48 hrs.

1111, LTPD = 20%

0115, LTPD= 15%
11129, LTPD=3%

11129, LTPD. 3%

Mark and Pack
FinalQA

(See attached)
296102-11

NOTES:
1. Units for assembly reliability monitor.
2. Units for product reliability monitor.

2-4

inter

INTEL MEMORY TECHNOLOGIES

in feature size was achieved using the newer high
resolution photo resists and optimizing their processing to match improved optical printing systems.

DIFFUSION
The picture of clean room garbed operators tending
furnace tubes glowing cherry red is the one most
often associated with IC fabrication. These furnace
operations are referred to collectively as diffusion
because they employ the principle of sold state diffusion of matter to accomplish their results. In MOS
processing, there are three main types of diffusion
operations: predeps, drives, and oxidations.

A second major factor in determining the size of the
circuit is the registration or overlay error. This is how
accurately one pattern can be aligned to a previous
one. Design rules require that space be left in all
directions according to the overlay error so that unrelated patterns do not overlap or interfere with one
another. As the error space increases the circuit size
increases dramatically. Only a few years ago standard alignment tolerances were :<: ± 2 microns; now
advanced Intel processes have reduced this dramatically due mostly to the use of advanced projection
and step and repeat exposure equipment.

Predeposition, or "predep," is an operation where a
dopant is introduced into the furnace from a solid,
liquid, or gaseous source and at the furnace temperature (usually 900·C-1200·C) a saturated solution is
formed at the silicon surface. The temperature of the
furnace, the dopant atom, and rate of introduction
are all engineered to give a specific dose of the dopant on the wafer. Once this is completed the wafer is
given a drive cycle where the dopant left at the surface by the predep is driven into the wafer by high
temperatures. These are generally at different temperatures than the predeps and are designed to give
the required junction depth and concentration profile.

The wafer that is ready for patterning must go
through many individual steps before that pattern is
complete. First the wafer is baked to remove moisture from its surface and is then treated with chemicals that ensure good resist adhesion. The thick
photoresist liquid is then applied and the wafer is
spun flat to give a uniform coating, critical for high
resolution. The wafer is baked at a low temperature'
to solidify the resist into gel. It is then exposed with a
machine that aligns a mask with the new pattern on
it to a previously defined layer. The photo-resist will
replicate this pattern on the wafer.

Oxidation, the third category, is used at many steps
of the process as was shown in the process flow.
The temperature and oxidizing ambient can range
from 800·C to 1200·C and from pure oxygen to mixtures of oxygen and other gases to steam depending
on the type of oxide required. Gate oxides require
high dielectric breakdown strength for thin layers
(between 0.01 and 0.1 micron) and very tight control
over thickness (typically ± 0.005 micron or less than
± 1/5,000,000 inch), while isolation oxides need to
be quite thick and because of this their dielectric
breakdown strength per unit thickness is much less
important.

Negative working resists are polymerized by the light
and the unexposed resist can be rinsed off with solvents. Positive working resists use photosensitive
polymerization inhibitors that allow a chemically reactive developer to remove the exposed areas. The
positive resists require much tighter control of exposure and development but yield higher resolution
patterns than negative resistance systems.
The wafer is now ready to have its pattern etched.
The etch procedure is specialized for each layer to
be etched. Wet chemical etchants such as hydrofluoric acid for silicon oxide or phosphoric acid for
aluminum are often used for this. The need for
smaller features and tighter control of etched dimensions is increasing the use of plaslT)a etching in fabrication. Here a reactor is run with a partial vacuum
into which etchant gases are introduced and an
electrical field is applied. This yields a reactive plasma which etches the required layer.

The properties of the diffused junctions and oxides
are key to the performance and reliability of the finished device so the diffusion operations must be extremely well controlled for accuracy, consistency
and purity.

ION IMPLANT
Intel's high performance products require such high
accuracy and repeatability of dopant control that
even the high degree of control provided by diffusion
operations is inadequate. However, this limitation
has been overcome by replacing critical predeps
with ion implantation. In ion implantation, ionized
dopant atoms are accelerated by an electric field

The wafer is now ready for the next process step. Its
single journey through the masking process required
the careful engineering of mechanics, optics, organic chemistry, inorganic chemistry, plasma chemistry,
physics, and electronics.

2-5

inter

INTEL MEMORY TECHNOLOGIES

and implanted directly into the wafer. The acceleration potential determines the depth to which the
dopant is implanted.

The fabrication of modern memory devices is a long,
complex process where each step must be monitored, measured and verified. Developing a totally
new manufacturing process for each new product or
even product line takes a long time and involves significant risk. Because of this, Intel has developed
process families, such as HMOS, on which a wide
variety of devices can be made. These families are
scalable so that circuits need not be totally redesigned to meet your needs for higher
performance.(1) They are evolutionary so that development time of new processes and products can be
reduced without compromising Intel's commitment
to consistency, quality, and reliability.

The charged ions can be counted electrically during
implantation giving very tight control over dose. The
ion implanters used to perform this are a combination of high vacuum system, ion source, mass spectrometer, linear accelerator, ultra high resolution current integrator, and ion beam scanner. You can see
that this important technique requires a host of sophisticated technologies to support it.

THIN FILMS
The manufacture of today's MOS memory devices
requires a tremendous variety of technologies and
manufacturing techniques, many more than could be
mentioned here. Each requires a team of experts to
design, optimize, control and maintain it. All these
people and thousands of others involved in engineering, design, testing and production stand behind
Intel's products.

Thin film depositions make up most of the features
on the completed circuit. They include the silicon nitride for defining isolation, polysilicon for the gate
and interconnections, the glass for interlayer dielectric, metal for interconnection and external connections, and passivation layers. Thin film depositions
are done by two main methods: physical deposition
and chemical vapor deposition. Physical deposition
is most common for deposition metal. Physical depositions are performed in a vacuum and are accomplished by vaporizing the metal with a high energy
electron beam and redepositing it on the wafer or by
sputtering it from a target to the wafer under an electric field.

Because of these extensive requirements, most
manufacturers have not been able to realize their
needs for custom circuits on high performance, high
reliability processes. To address this Intel's expertise in this area is now available to industry through
the silicon foundry. Intel supplies design rules and
support to design and debug circuits. This includes
access to Intel's n-well CHMOS technology. Users
of the foundry can now benefit from advanced technology without developing processes and IC manufacturing capability themselves.

Chemical vapor deposition can be done at atmospheric pressure or under a moderate vacuum. This
type of deposition is performed when chemical gases react at the wafer surface and deposit a solid film
of the reaction product. These reactors, unlike their
general industrial counterparts, must be controlled
on a microscale to provide exact chemical and physical properties for thin films such as silicon dioxide,
silicon nitride, and polysilicon.

(1)R. Pashley, K. Kokkonen, E. Boleky. R. Jecmen, S. Liu,
and W. Owen, "H-MOS Scales Traditional Devices to Higher Performance Level," Electronics, August 18, 1977.

2-6

Dynamic RAMs
(Random Access Memories)

3

21256
262,144 x 1-BIT DYNAMIC RAM WITH PAGE MODE
Symbol

•
•
•
•

Parameter

21256-06

21256-07

21256-08

21256-10

Units

tRAG

Access Time from RAS

60

70

80

100

ns

tGAC

Access Time from CAS

20

20

20

50

ns

tRG

Read Cycle Time

110

130

150

190

ns

•
•
•
•

Page Mode Capability
CAS-before-RAS Refresh Capability
RAS-Only and Hidden Refresh
Capability
TTL Compatible Inputs and Output

Common 1/0 Using Early Write
Single + 5V ± 10% Power Supply
256 Cycle/4 ms Refresh
JEDEC Standard Pinout in DIP, ZIP and
PLCC

The 21256 is a fully decoded dynamic random access memory organized as 262,144 one-bit words. The
design is optimized for high speed, high performance applications such as computer memory, buffer memory,
peripheral storage and environments where low power dissipation and compact layout are required.
The 21256 features page mode which allows high speed random access of memory cells within the same row.
CAS-before-RAS refresh capability provides on-chip auto refresh as an alternative to RAS-only refresh. Multiplexed row and column address inputs permit the 21256 to be housed in a JEDEC standard 16-pin DIP.
Clock timing requirements are noncritical, and power supply tolerance i!! very wide. All inputs and output are
TTL compatible.

RAS _1""""----,
CONTROL & t::===~----i:l
CLOCKS IVi -r."'T""---,~

CAS

o

Q

AO
Al
A2
A3

A4
AS
A6

IX

'"co
~

c

:=o

MEMORY ARRAY
262,144
CELLS
~vcc

IX

A7
A8

~vss
240021-1

Figure 1_ Functional Block Diagram

3-1

September 1990
Order Number: 240021-004

intJ

21256

DIP
AS
0

VSS
CAS

W

Q

RAS

A6

AO

A3

A2

A4

Al

AS

Vee

A7
240021-2

·PLCC
0

AS VssCAS

~~! L~.! ~1~

•

W ~]
NC

{]
[]

AO

~J

A2

fl

RAS

!1.?!

(TOP VIEW)

[1]
[(§

Q

~~
[1]
[1}

NC

A6
A3
A4

~8~ r9~ ~C; ~1-1~
Al Vee A7 AS

240021-3

ZIP

OM'~
Q

Vss

0

RAS

A2

vee

AS

A3'-16
240021-4

(Bottom View)
Pin Names
Ao-As

o

Q

W
RAS
CAS

Vee
Vss

Address Input
Data In
Data Out
Read/Write Input
Row Address Strobe
Column Address Strobe
Power (+5V)
Ground

3-2

intJ

21256

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Voltage on Any Pin
Relative to vss .......... VOUT -1.0V to + 7.0V

'WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Voltage on Vcc Supply
Relative to Vss ............... -1.0V to + 7.0V
Storage Temperature .......... - 55D C to + 125D C
Power Dissipation .......................... 1.0W
Short Circuit Output Current ................ 50 mA

RECOMMENDED OPERATING CONDITIONS
Symbol

Voltages referenced to Vss, TA

=

0 to 70D C

Parameter

Min

Typ

Max

Vcc

Supply Voltage

4.5

5.0

5.5

V

Vss

Ground

0

0

0

V

VIH

Input High Voltage

2.4

Vcc+ 1

V

VIL

Input Low Voltage

-1

0.8

V

Units

D.C. AND OPERATING CHARACTERISTicS
Recommended operating conditions unless otherwise noted.

Symbol

Parameter

Min Max Units

Test Condition

ICCl

Operating Current'

21256-06
21256-07
21256-08
21256-10

75
70
60
55

mA
mA
lilA
mA

(RASand CAS
cycling @ tRC = min.)

ICC2

Standby Current

21256-06
21256-07
21256-08
21256-10

2.0
2.0
2.0
5.0

mA
mA
mA
mA

(RAS = CAS = VIH)

ICC3

RAS-Only Refresh Current'

21256-06
21256-07
21256-08
21256-10

75
70
60
40

mA
mA
mA
mA

(CAS = VIH, RAS
cycling @ tRC = min.)

ICC4

Page Mode Current'

21256-06
21256-07
21256-08
21256-10

50
45
40
35

mA
mA
mA
mA

(RAS = VIL, CAS cycling;
tpc = min.)

ICC5

CAS-before-RAS Refresh Current' 21256-06
21256-07
21256-08
21256-10

75
65
55
55

mA
mA
mA
mA

(RAS cycling

Iccs

Standby Current

1.0

mA

(RAS = CAS = Vcc - 0.2V)

IlL

Input Leakage Current

-10

10

p.A

(Any input 0 :5: VIN :5: 5.5V,
Vcc = 5.5V, Vss = OV, All other
pins not under test = 0.)

IOL

Output Leakage Current

-10

10

p.A

(Data out is disabled,
OV :5: VOUT :5: 5.5V,
Vcc = 5.5V, Vss = OV)

@

tRC = min.)

'NOTE:
and ICC5 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is
specified as average current.
ICCt, ICC3, ICC4

3-3

intJ

21256

D.C. AND OPERATING CHARACTERISTICS
Recommended operating conditions unless otherwise noted. (Continued)

Symbol

Parameter

Min

VOH

Output High Voltage Level

Val

Output 'Low Voltage Level

CAPACITANCE

I
I

Max

Units

2.4
0.4

V

(IOH

V

(IOl

= 5 mA)
= 4.2 mA)

TA = 25D C

Symbol

Parameter

Min

Input Capacitance (Ao-As, D)

CIN1

Test Condition

Max

Units

5

pF

CIN2

Input Capacitance (RAS, CAS, W)

8

pF

COUT

Output Capacitance (0)

7

pF

A.C. CHARACTERISTICS
Symbol

(ODC ::;; TA ::;; 70DC, VCC = 5.0V ± 10%. See Notes 1, 2)

Parameter

21256-06
Min

21256-07

Max

Min

Max

21256-08
Min

Max

21256-10
Min

Units Notes

Max

tRC

Random Read or
Write Cycle Time

120

135

150

190

ns

tRWC

Read-Modify-Write Cycle Time 135

155

175

220

ns

tRAC

Access Time from RAS,

60

70

80

100'

ns

3,4,11

tCAC

Access Time from CAS

15

25

30

50

ns

3,4,5

tAA

Column Address Access Time

tClZ

CAS to Output in Low-Z

5

35

35
5

40
5

50
5

ns

3,10

ns

3

tOFF

Output Buffer Turn-Off Delay

0

25

0

25

0

25

0

30

ns

7

tT

Transition Time (Rise and Fall)

3

50

3

50

3

50

3

100

ns

2

tRP

RAS Precharge Time

55

tRAS

RAS Pulse Width

60

65
10,000

70

10,000

75

80

ns

80

10,000 100 10,000

ns

tRSH

RAS Hold Time

15

25

30

50

ns

tCPN

CAS Precharge Time
(All Cycles except Page Mode)

10

10

15

25

ns

tCAS

CAS·Pulse Width

15

tCSH

CAS Hold Time

60

tRCD

RAS to CAS Delay Time

15

50

25

50

25

. 60

25

75

ns

4

tRAD

RAS to Column Address
Delay Time

15

25

20

35

20

40

20

55

ns

11

tCRP

CAS to RAS Precharge Time
(RAS Only Refresh)

5

15

15

15

ns

tASR

Row Address Setup Time

0

0

0

0

ns

10,000

25

10,000

70

3-4

30

10,000

80

50

10,000

100

ns
ns

--

""

21256

A.C. CHARACTERISTICS (o·c
Symbol

:S: T A :S: 70·C, VCC

Parameter

21256-06

=

5.0V ± 10%. See Notes 1, 2) (Continued)

21256-07

Min

Max Min

Max

21256-08

21256-10

Min

Max Min

Units Notes

Max

tAAH

Row Address Hold Time

15

15

15

15

ns

tASC

Column Address Setup Time

0

0

0

0

ns

tCAH

Column Address Hold Time

10

15

20

20

ns

tAA

Column Address Hold Time
Referenced to RAS

50

55

65

75

ns

tAAL

Column Address to RAS
Lead Time

30

35

40

50

ns

tACS

Read Command Setup Time

0

0

0

0

ns

tACH

Read Command Hold Time
Referenced to CAS

5

5

5

5

ns

9

tAAH

Read Command Hold Time
Referenced to RAS

5

5

5

5

ns

9

twcs

Write Command Setup Time

0

0

0

0

ns

8

tWCH

Write Command Hold Time

15

15

15

35

ns

twp

Write Command Pulse Width

10

15

15

35

ns

tAWL

Write Command to RAS Lead Time

15

25

30

35

ns

tcWL

Write Command to CAS Lead Time

15

25

30

35

ns

tDS

Data-In Setup Time

0

0

0

0

ns

10
10

6

tDH

Data-In Hold Time

10

15

15

35

ns

tCWD

CAS to Write Enable Delay

15

20

25

40

' ns

8

tAWD

RAS to Write Enable Delay

60

70

80

100

ns

8

tAWD

Column Address to W Delay Time

35

35

.40

50

ns

8

tWCA

Write Command Hold Time
Referenced to RAS

40

55

60

85

ns

6

tDHA

Data-In Hold Time
Reference9 to RAS

50

55

60

85

ns

6

tAEF

Refresh Period (256 Cycles)

4

4

4

4

ms

CAS-BEFORE-RAS REFRESH
tCSA

CAS Setup Time
(CAS-before-RAS Refresh)

10

10

10

15

ns

tCHA

CAS Hold Time
(CAS-before-RAS Refresh)

10

20

25

30

ns

tcPT

Refresh Counter Test
CAS Precharge Time

15

35

50

60

ns

tAPC

RAS Precharge to CAS Active Time

10

10

10

10

ns

PAGE MODE
tpc

Page Mode Cycle Time

40

50

55

90

ns

tcp

CAS Precharge Time
(Page Mode Only)

10

15

15

30

ns

3-5

intJ

21256

A.C. CHARACTERISTICS
Symbol

(O·C ::;; T A ::;; 70·C, Vee = 5.0V ± 10%. See Notes 1, 2) (Continued)

Parameter

21256-06
Min

Max

21256-07
Min

Max

21256-08
Min

Max

21256-10
Min

Units Notes

Max

PAGE MODE (Continued)
45

ns

ePA

Access Time from CAS Precharge

PRwe

Fast Page Mode
Read-Modify-Write

65

RASP

RAS Pulse Width (Fast Page Mode)

60 10,000 70 10,000 80 10,000 100 10,000 ns

40
75

50
85

55
95

3

ns

NOTES:
1. An initial pause of 200 JLs is required after power-up followed by any S RAS cycles before proper device operation is
achieved.
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5 ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100 pF.
4. Operation within the T RCD(max) limit ensures that T RAc(max) can be met, tRCD(max) is specified as a reference point
only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tcAC.
5. Assumes that tRCD ;;" tRCD(max).
• 6. tAR, tWCR, tDHR are referenced to tRAD(max)'
'
7. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or
VOL·
'
·S. twcs, tRWD, lewD and tAWD are non-restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If twcs ;;" tWCS(min) the cycle i,s an early write cycle and the data out pin will remain high impedance for
the duration of the cycle. If tCWD ;;" tcWD(min), tRWD ;;" tRWD(min) and tAWD ;;" tAWD(min), then the cycle is a read-write cycle
and the data out will contain the data read from the selected address. If ,neither of the above conditions are satisfied, the
condition of the data out is indeterminate.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write
cycles.
"
,
11. Operation within the tRAD!max) limit insures thattRAC(max) can be met. tRAD(max) is specified as a reference pOint only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tM'

TIMING DIAGRAMS
READ CYCLE
~---------------------tRC--------------------~

HAS

CAS

vlII VIL -

V1H V1L -

Q VOH -

VOL -

----------

240021-5

~Don·tCare

240021-6

3-6

inter

21256

TIMING DIAGRAMS (Continued)
WRITE CYCLE (EARLY WRITE)
t Rc
t RAS
RAS

V1H V1L -

CAS

V1H V1L -

A

V1H V1L -

tAR

I RSH
tCAS

240021-7

READ-WRITE/READ-MODIFY-WRITE CYCLE
t RWC
t RAS
RAS

V1H -

tAR

V1L t RSH

CAS

V1H V1L -

A

V1H V1L -

Vi

V1H V1L -

tCAS

240021-8

~Don·tcare

240021-6

3-7

inter

21256

TIMING DIAGRAMS (Continued)
PAGE MODE READ CYCLE
~------------------------tRASP--------------------~----~

o VOH - ------+.:....-{K
VOL -

Vi

V1H -

.............x.......,......OJ

V1L -

240021-9

PAGE MODE WRITE CYCLE (EARLY WRITE)

WVIH-~:"7I:~~~~
V1L -

.t...::.~~~"-l.~fIL+'-~=~~~~+:--~~~IUj"-\'~~iCfI-:--~~~IL.lo~~~

o V1H - ~:fu~:fu'\l~:-:-=::i"'7\Jv,,:,::,:-:-=':""'IVi:7\.rv~ },.,¥----,j.J<:~~:"7I:"7t"':'Tf:'7
V1L -

o VOH VOL -

..............

+.....,~

___

i'~.Y·

____

.T'''-lo~~

----------------OPEN---------------240021-10

~Don'tCore

240021-6

3-8

21256

TIMING DIAGRAMS (Continued)
PAGE MODE READ-WRITE CYCLE

Q VOH -

VOL -

---------(JXXI

-s.....;;;;~~

240021-14

3-9

21256

TIMING DIAGRAMS (Continued)
RAS-ONLY REFRESH CYCLE
i----------tRc---------l

Q VOH- _ _ _ _ _ _ _ _ _ _ _ OPEN _ _ _ _ _ _ _ _ _ _ _ _ _ __

VOL -

240021-11

NOTE:
CAS = VIH:

IN,

D = Don't Care

HIDDEN REFRESH CYCLE

QVOH VOL -

----240021-12

~Oonltcare

240021-6

3-10

inter

21256

TIMING DIAGRAMS (Continued)
CAS-BEFORE-RAS REFRESH CYCLE

i---------tRc--------.J

V1H V1L -

CAS

Q

VOH VOL -

----------------------------OPEN--~----------------------------240021-13

NOTE:
Address,

1m

'N,

D = Don't Care

Don't Care

240021-6

3-11

21256

TIMING DIAGRAMS (Continued)
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE

RAS V1H
V1L

=-----'\1

1----------tRAs--------------i

foo~----tRsH--------l

1,---,

READ CYClE
Q~H-

_____________________

_+~~--_Q.X

VOL -

WRITE CYCLE
f+--++-----tRWL---+--i

QVOH- _________________ OP~--------~~~---------------~----r_----------VOL -

WV1H V1L -

~~fu~~fu7l\1\7'\A.7I\1\7'\A.~
~~~~~.lL.:~!J,t;ilL.:~!J,t;~~~~-I-!-----~~~~¥-l~~~~~~~~

READ-WRITE CYCLE

W V1H V1L -

D V1H V1L -

~~~.K..~'_lj~~.K..~'_lj~.K.N

4o..li~~.K.~_'_lj~~.K..~'_lj~~.K..~_'_¥~....

1'-.-0---'[" ___.....~.K.~_.....00K.. .
240021-18

moon.teare

240021-6

3-12

intJ

21256

DEVICE OPERATION

Write

The 21256 contains 262,144 memory locations.
Eighteen address bits are required to address a particular memory location. Since the 21256 has only 9
address input pins, time multiplexed addressing is
used to input 9 row and 9 column addresses. The
multiplexing is controlled by the timing relationship
between the row address strobe (RAS), the column
address strobe (CAS) and the valid address inputs.

The 21256 can perform early write, late write and
read-modify-write cycles. The difference between
these cycles is in the state of data-out and is determined by the timing relationship between Wand
CAS. In any type of write cycle, data-in must be valid
at or before the falling edge of W or CAS, whichever
is later.
Early Write: An early write cycle is performed by
bringing W low before CAS. The data at the data
input pin (D) is written into the addressed memory
cell. Throughout the early write cycle the output remains in the Hi-Z state. This cycle is good for common liD applications because the data-in and dataout pins may be tied together without bus contention.

Operation of the 21256 begins by strobing in a valid
row address with RAS while CAS remains high.
Then the address on the 9 address input pins is
changed from a row address to a column address
and is strobed in by CAS. This is the beginning of
any 21256 cycle in which a memory location is accessed. The specific type of cycle is determined by
the state of the write enable pin and various timing
relationships. The cycle is terminated when both
RAS and CAS have returned to the high state. Another cycle can be initiated after RAS remains high
long enough to satisfy the RAS precharge time (tRP)
requirement.

Read-Modify-Write: In this cycle, valid data from
the addressed cell appears at the output before and
during the time that data is being written into the
same cell location. This cycle is achieved by bringing
W low after CAS and meeting the data sheet readmodify-write cycle timing requirements. This cycle
requires using a separate liD to avoid bus contention.

RAS and CAS Timing

Late Write: If W is brought low after CAS, a late
write cycle will occur. The late write cycle is very
similar to the read-modify-write cycle except that the
timing parameters, tRWO and lewo, are not necessarily met. The state of data-out is indeterminate
since the output could be either Hi-Z or contain data
depending on the timing conditions. This cycle requires a separate I/O to avoid bus contention.

The minimum RAS and CAS pulse widths are specified by tRAS(min) and tCAS(min) respectively. These
, minimum pulse widths must be satisfied for proper
device operation and data integrity. Once a cycle is
initiated by bringing RAS low, it must not be aborted
prior to satisfying the minimum RAS and CAS pulse
widths. In addition, a new cycle must not begin until
the minimum RAS precharge time, tRP, has been
satisfied. Once a cycle begins, internal clocks and
other circuits within the 21256 begin a complex sequence of events. If the sequence is broken by violating minimum timing requirements, loss of data integrity can occur.

Data Output
The 21256 has a tri-state output buffer which is controlled by CAS (and W for early write). Whenever
CAS is high (VIH) the output is in the high impedance
(Hi-Z) state. In any cycle in which valid data appears
at the output, the output first remains in the Hi-Z
state until the data is valid and then the valid data
appears at the output. The valid data remains at the
output until CAS returns high. This is true even if a
new RAS cycle occurs (as in hidden refresh). Each
of the 21256 operating cycles is listed below after
the corresponding output state produced by the cycle.

Read
A read, cycle is achieved by maintaining the write
enable input (W) high during a RAS/CAS cycle. The
output of the 21256 remains in the Hi-Z state until
valid data appears at the output. If CAS goes low
before tRCO(max), the access time to valid data is
specified by tRAC. If CAS goes low after tRCO(max),
the access time is measured from CAS and is specified by tCAC. In order to achieve the minimum access time, tRAc(min), it is necessary to bring CAS
low before tRCO(max).

Valid Output Data: Read, Read-Modify-Write, Hidden Refresh, Page Mode Read, Page Mode ReadModify-Write.

3-13

intJ

21256

HI-Z Output State: Early Write, RAS-only Refresh,
Page Mode Write, CAS-before-RAS Refresh, CASonly cycle.
Indeterminate Output State: Delayed Write

Refresh
The data in the 21256 is stored on a tiny capacitor
within each memory cell. Due to leakage, the data
will leak off after a period of time. To maintain data
integrity it is necessary to refresh each of the rows
every 4 ms. There are several ways to. accomplish
this.
RAS-Only Refresh: This is the most common method for performing refresh. It is performed by strobing
in a row address with RAS while CAS remains high.
CAS-before-RAS Refresh: The 21256 has CAS-before-RAS on-chip refreshing capability that eliminates the need for external refresh addresses. If
CAS is held low for the specified setup time (tCSR)
before RAS goes low, the on-chip refresh circuitry is
enabled. An internal refresh operation automatically
occurs and the on-chip refresh address counter is
internally incremented in preparation for the next
CAS-before-RAS refresh cycle.

read-modify-cycles. As long as the applicable timing
requirements are observed, it is possible to mix
these cycles in any order. A~e mode cycle begins
with a normal cycle. While RAS is kept low to maintain the row address, CAS is cycled to strobe in additional column addresses. This eliminates the time
required to set up and strobe sequential row addresses for the same page.

CAS-before-RAS Refresh Counter Test
Cycle
A special timing sequence using the CAS-beforeRAS counter test cycle provides a convenient method of verifying the functionality of the CAS-beforeRAS refresh activated circuitry.
After the CAS-before-RAS refresh operation, if CAS
goes high and then low again while RAS is held low,
the read and write operations are enabled.
This is shown in the CAS-before-RAS counter test
cycle timing diagram. A memory cell can be addressed with 9 row address bits and 9 column address bits defined as follows:
Row Address-Bits AO through A7 are supplied by
. the on-chip refresh counter. The AS bit is set high
internally.

Hidden Refresh: A hidden refresh cycle may be
performed while maintaining the latest valid data at
the output by extending the CAS active time and
cycling RAS. The 21256 hidden refresh cycle is actually a CAS-before-RAS refresh cycle within an extended read cycle. The refresh row address is provided by the on-chip refresh address counter. This
eliminates the need for the external row address
that is required in hidden refresh cycles by DRAMs
that do not have CAS-before-RAS refresh capability.

Column Address-Bits AO through AS are strobedin by the falling edge of CAS as in a normal memory
cycle.

Suggested CAS-before-RAS Counter
Test Procedure
The CAS-before-RAS refresh counter test cycle timing is used in each of the following steps:
1. Initialize the internal refresh counter by performing S cycles.
2. Write a test pattern of "lows" into the memory
cells at a single column address and 256 row addresses. (The row addresses are supplied by the
on-chip refresh counter.)
3. Using read-modify-write cycles, read the "lows"
written during step 2 and write "highs" into the
same memory locations. Perform this step 256
times so that highs are written into the 256 memory cells.
4. Read the "highs" written during step 3.
5. Complement the test pattern and repeat steps 2,
3 and 4.

Other Refresh Methods: It is also possible to refresh the 21256 by using read, write or read-modifywrite cycles. Whenever a row is accessed, all the
cells in that row are automatically refreshed. There
are certain applications in which it might be advantageous to perform refresh in this manner but in general RAS-only· or CAS-before-RAS refresh is the preferred method.

Page Mode
The 21256 has page mode capability. Page mode
memory cycles provide faster access and lower
power dissipation than normal memory cycles. In
page mode, it is possible to perform read, write or

3-14

inter

21256

ground lines act like transmission lines to the high
frequency transients generated by DRAMs. The impedance is minimized if all the power supply traces
to all DRAMs run both horizontally and vertically and
are connected at each intersection or better yet if
power and ground planes are used.

Power-Up
If RAS = Vss during power-up, the 21256 could begin an active cycle. This condition results in higher
than necessary current demands from the power
supply during power-up. It is recommended that
RAS and CAS track with Vee during power-up or be
held at a valid VIH in order to minimize the power-up
current.

Address and control lines should be as short as possible to avoid skew. In boards with many DRAMs
these lines should fan out from a central point like a
fork or comb rather than being connected in a serpentine pattern. Also the control logic should be
centrally located on large memory boards to facilitate the shortest possible address and control lines
to all the DRAMs.

An initial pause of 100 fts is required after power-up
followed by 8 initialization cycles before proper device operation is assured. 8 initialization cycles are
also required after any 4 ms period in which there
are no RAS cycles. An initialization cycle is any cycle
in which RAS is cycled.

Decoupling
Termination

The importance of proper decoupling cannot be over
emphasized. Excessil(e transient noise or voltage
droop on the Vee line can cause loss of data integrity (soft errors). The total combined voltage changes
over time in the Vee to Vss voltage (measured at
the device pins) should not exceed 500 mV.

The lines from the TIL driver circuits to the 21256
inputs act like unterminated transmission lines resulting in significant positive and negative overshoots at the inputs. To minimize overshoot it is advisable to terminate the inpu~ lines and to keep them
as short as possible. Although either series or parallel termination may be used, series termination is
generally recommended since it is simple and draws
no additional power. It consists of a resistor in series
with the input line placed close to the 21256 input
pin. The optimum value depends on the board layout. It must be determined experimentally and is
usually in the range of 200 to 400.

A high frequency 0.3 ftF ceramic decoupling capacitor should be connected between the Vee and
ground pins of each 21256 using the shortest possible traces. These capacitors act as a low impedance
shunt for the high frequency switching transients
generated by the 21256 and they supply much of the
current used by the 21256 during cycling.
In addition, a large tantalum capacitor with a value of
47 p.F to 100 ftF should be used for bulk decoupling
to recharge the· 0.3 ftF capacitors between cycles,
thereby reducing .power line droop. The bulk decoupiing capacitor should be placed near the point
where the power traces meet the power grid or power plane. Even better results may be achieved by
distributing more than one tantalum capacitor
throughout the memory array.

Board Layout
It is important to layout the power and ground lines
on memory boards in such a way that switching transient effects are minimized. The recommended
methods are gridded power and ground lines or separate power and ground planes. The power and

3-15

21256

PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL-IN-LINE PACKAGE

~50·20

t

I
~~~J
~-------A--------~.I

- . . . - f - - SEATING
PLANE

H

J

K
240021-15

Item

Millimeters

Inches

A

19.43 ±0.05

0.765 ± 0.002

8

6.86 ±0.05

0.270 ± 0.002

C

7.62

0.300

0

0.25 ±0.025

0.010 ±0.001

E

3.56 ±0.05

0.140 ±0.002

F

0.506 ±0.1

0.020 ± 0.004

G

3.3 ±0.1

0.130 ± 0.004

H

2.54

0.100

I

1.52

0.060

J

0.457 ±0.05

0.Q18 ± 0.002

K

0.1 ±0.05

0.040 ± 0.002

3-16

21256

PACKAGE DIMENSIONS (Continued)
18-PIN PLASTIC LEADED CHIP CARRIER

M

~--------L--------~

240021-16

Item

A

Millimeters

Inches

12.346 ±0.052

0.490 ± 0.002

B

13.2585 ± 0.0505

0.522 ± 0.002

C

7.366 ±0.051

0.290 ± 0.002

0

8.179 ±0.051

0.322 ± 0.002

E

2.083 ±0.051

0.082 ± 0.002

F

3.505 ±0.051

0.020 ± 0.004

G

0.7365 ±0.0505

0.029 ± 0.002

H

6.553 ±0.051

0.258 ±0.002

I

0.43 typ

0.017typ

J

0.279 ± 0.025

0.011 ± 0.001

K

0.76 typ

0.030typ

L

11.8365 ± 0.0505

0.466 ± 0.002

M

0.1 ±0.05

0.04 ±0.002

3-17

inter

21256

PACKAGE DIMENSIONS (Continued)
16-LEAD ZIG ZAG INLINE PACKAGE (ZIP)
1-------0.808- 0.812-----.f,!

o

·"'-nn
. '''Q....
,f \
MIN. 0 . 1 2 0 L

I
0.068 - 0.072

~
-11-0.008 - 0.Q12

-+

3-18

-0.050 TYP.

--1-0.100 TYP.
240021-17

21464

65,536 x 4-BIT DYNAMIC RAM WITH PAGE MODE
Parameter

21464-06

21464-07

21464-08

21464-10

Units

tRAG

Access Time from RAS

60

70

80

100

ns

tGAG

Access Time from CAS

15

25

30

50

ns

tRG

Read Cycle Time

110

130

150

190

ns

Symbol

Write or Output Enable Controlled
• Early
Write
+ 5V ± 10% Power Supply.
• Single
256 Cycle/4 ms Refresh
• JEDEC Standard Pinout in DIP, PLCC,
• ZIP

Mode Capability
• Page
CAS-Before-RAS Refresh Capability
• RAS-Only and Hidden Refresh
• Capability
• TTL Compatible Inputs and Outputs

The 21464 is a fully decoded 65,536 x 4 dynamic random access memory. The design is optimized for high
speed, high performance applications such as computer memory, buffer memory, peripheral storage and
environments where low power dissipation and compact layout are required.
The 21464 features page mode which allows high speed random access of memory cells within the same row.
CAS-before-RAS refresh capability provides on-chip auto refresh as l1n alternative to RAS-only refresh. Multiplexed row and column address inputs permit the 21464 to be housed in a standard 18-pin DIP.
Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and outputs are

TTL compatible.

RAS-.r-----'
CAS

DATA
IN
BUFF

Vi -?L-r--r--.......

COLUMhI DECODER
SENSE AMPS &: I/O GATINGS

AO

A7

A
D
D

R
0
W

B
U
F
F
E
R
S

D
E
C

MEMORY ARRAY
262, 144 CELLS

0
D
E
R

+-Vcc
+-Vss

240022-1

Figure 1. Functional Block Diagram

3-19

October 1990
Order Number: 240022-005

inter

21464

DIP

PLCC
DO, OE VSSD04

OE

VSS

DO,

D0 4

D0 2

CAS

Vi

D0 3

RAS
A6
A5
A4
Vee

t~J
D0 2

~]

AO
A,
A2
A3
A7

RAS

51
-~

(TOP VIEW)

A5

~-

Vee

A7 A3
240022-3

Figure 2. Pin Configurations
PIN NAMES

OE

A,

~l A2

ZJ
f81 f91 fl-01 f1-11

240022-4

Vee
Vss

D0 3

~j AO

r,"3

A6 ~]

ZIP

RAS
CAS

U~ CAS

V§

A4

IN

•

Vi ~J

240022-2

Ao-A7
DQ1-DQ4

L!J ~~J t1..?J

Address Input
Data In/Out
Read/Write Input
Row Address Strobe
Column Address Strobe
Power (+5V)
Ground
Output Enable

3-20

inter

21464

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin
Relative to vss ................... -1 V to

NOTICE: This is a production data sheet. The specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

+ 7V

Voltage on Vee Supply
Relative to Vss ................... -1 V to
Storage Temperature .......... - 55°C to

+ 7V
+ 125°C

Power Dissipation ...................•...... 1.0W
Short Circuit Output Current ................ 50 mA

RECOMMENDED OPERATING CONDITIONS
Symbol

Voltages referenced to Vss. TA = 0 to 70°C

Parameter

Min

Typ

Max

Units

Vee

Supply Voltage

4.5

5.0

5.5

V

VSS

Ground

0

0

VIH

Input High Voltage

2.4

VIL

Input Low Voltage

-1.0

3-21

V

0
Vee

+

0.8

1

V
V

21464

D.C. OPERATING CHARACTERISTICS
Recommended operating conditions unless otherwise noted

Parameter

Symbol

Min

Max

Units

Test Condition

ICC1

Operating Current'

21464-06
21464-07
21464-08
21464-10

75
70
65
55

mA
mA
mA
mA

RAS and CAS Cycling
@tRC = Min

ICC2

Standby Current

21464-06
21464-07
21464-08
21464-10

2.0
2.0
2.0
5.0

mA
mA
mA
mA

HAS = CAS = VIH

ICC3

RAS-Only Refresh Current'

21464-06
21464-07
21464-08
21464-10

75
70
60
40

mA
mA
mA
mA

CAS = VIH, RAS Cycling
@tRC = Min

ICC4

Page Mode Current·

21464-06
21464-07
21464-08
21464-10

50
45
40
35

mA
mA
mA
mA

RAS = VIL, CAS Cycling:
tpc = Min

ICC5

CAS-Before-RAS'
Refresh Current

21464-06
21464-07
21464-08
21464-10

75
70
65
55

mA
mA
mA
mA

RAS Cycling @ tRC = Min

IlL

Input Leakage Current

-10

10

}LA

Any Input 0 s:: VIN s:: 5.5V,
VCC = 5.5V, Vss = OV, All Other
Pins Not Under Test = OV

.'Output Leakage Current

-10

10

}LA

Data Out is Disabled, OV s:: Your
s:: 5.5V, Vcc = 5.5V, Vss = OV

IDOL
VOH

Output High Voltage Level

VOL

Output Low Voltage Level

2.4
0.4

V

IOH = 5mA

V

IOL = 4.2mA

NOTE:
'Icc is dependent on output loading and cycle rates. Specified values are obtained with the output open. IcC is specified as
an average current.
.

CAPACITANCE TA ~
Symbol

25 D C

Parameter

Max

Unit

CIN1

Input Capacitance (Ao-A7)

Min

5

pF

CIN2

Input Capacitance (RAS, CAS, W, OE)

8

pF

Coa

Output Capacitance (001- D04)

7

pF

3-22

A.C. CHARACTERISTICS
Symbol

(O°C ~ T A ~ 70°C = 5.0V

Parameter

Min

c:.u

N
c:.u

± 10%. See notes 1, 2)

21464-06
Max

21464-07
Min

Max

21464-08
Min

Max

21464-10
Min

tRC

Random Read or Write Cycle Time

120

135

150

190

tRWC

Read-Modify-Write Cycle Time

165

195

225

265

tRAC

Access Time from RAS

tCAC

Access Time from CAS

tAA

Access Time from Column Address

Notes

ns
ns

80

100

15

25

30

35

35

40

ns

3,4,11

50

ns

3,4,5

50

ns

3, 10

ns

3

0

30

ns

7

3

100

ns

2

tClZ

CAS to Output in Low-Z

5

tOFF

Output Buffer Turn-Off Delay

0

25

tT

Transition Time (Rise and Fall)

3

50

tRP

RAS Precharge Time

55

tRAS

RAS Pulse Width

60

tRSH

RAS Hold Time

15

25

30

50

ns

tCPN

CAS Precharge Time
(All Cycles Except Page Mode)

10

10

15

25

ns

tCAS

CAS Pulse Width

15

tCSH

CAS Hold Time

60

tRCD

RAS to CAS Delay Time

15

50

25

50

25

60

25

75

ns

4

tRAD

RAS to Column Address Delay Time

15

25

20

35

20

40

20

55

n's

11

tCRP

CAS to RAS Precharge Time
(RAS Only Refresh)

5

5

5

0

25

3

50

65
10,000

70

5

0

25

3

50

75
10,000

80

80
10,000

100

(

Max

70

60

Units

ns
10,000

ns
I\)

10,000

25

10,000

70

15

30

10,000

15

50

10,000

100

80

15

-"

""
""

O'l

ns
ns

ns

tASR

Row Address Set-Up Time

0

0

0

0

ns

tRAH

Row Address Hold Time

15

15

15

15

ns

tASC

Column Address Set-Up Time

0

0

0

0

ns

tCAH

Column Address Hold Time

10

15

20

20

ns

tAR

Column Address Hold Time
Referenced to RAS

50

55

65

75

ns

6

A.C. CHARACTERISTICS
Symbol

Parameter

21464-06
Min

tv

'"
~

tRAL

Column Address to RAS Lead Time

tRCS
tRCH
tRRH

(

± 10%. See notes 1, 2) (Continued)

(O°C s T A S 70°C = 5.0V

Max

21464-07
Min

Max

21464-08
Min

30

35

40

Read Command Set-Up Time

0

0

Read Command Hold Time
Referenced to CAS

5

5

Read Command Hold Time
Referenced to RAS

5

twcs

Write Command Set-Up Time

0

tWCH

Write Command Hold Time

15

15

twp

Write Command Pulse Width

10

15

Max

21464-10
Min

Units

Notes

Max

50

ns

0

0

ns

5

5

ns

9

5

5

5

ns

9

0

0

0

ns

8

15

35

ns

15

35

ns

tRWL

Write Command to RAS Lead Time

15

25

30

35

ns

tCWL

Write Command to CAS Lead Time

15

25

30

35

ns

tos

Data-In Set-Up Time

0

0

0

0

ns

....
I\)

01:>0

10

en

01:>0

tOH

Data-In Hold Time

10

15

15

35

ns

10

tcwo

CAS to Write Enable Delay

35

50

60

70

ns

8

tRWO

RAS to Write Enable Delay

90

100

110

135

ns

8

tAWO

Column Address to W Delay Time

60

65

70

85

ns

8

tWCR

Write Command Hold Time
Referenced to RAS

40

55

60

85

ns

6

tOHR

Data-In Hold Time
Referenced to RAS

50

55

60

85

ns

6

tOEA

Access Time from OE

tOEO

OE to Data in Delay Time

tOEZ

Output Buffer Turn Off Delay from OE

tOEH

OE Hold Time Referenced to W

tREF

Refresh Period (256 Cycles)

15
15

20
20

15
15

20
20

4

30
20

4

0

4

ns
ns

30

25

20
---

25

20
25

ns
ns

4

ms

.

i

A.C. CHARACTERISTICS
Symbol

± 1 0%.

(O°C :;, T A :;, 70°C = 5.0V

Parameter

21464-06
Min

Max

21464-07
Min

Max

21464-08
Min

Max

21464-10
Min

Units

CAS Set-Up Time
(CAS-Before-RAS Refresh)

10

10

10

15

ns

tCHR

CAS Hold Time
(CAS-Before-RAS Refresh)

10

20

25

30

ns

tRPC

RAS Precharge to CAS Hold Time

10

10

10

10

ns

tCPT

Refresh Counter Test
CAS Precharge

15

35

50

60

ns

tpc

Page Mode Cycle Time

40

50

55

90

ns

tcp

CAS Precharge Time (Page Mode Only)

10

tCPA

Access Time from CAS Precharge

tPRWC

Fast Page Mode Read-Modify-Write

95

tRASP

RAS Pulse Width (Fast Page Mode)

60

tROH

RAS Hold Time Referenced to OE

10

15
40

15
45

105
10,000

70

30
50

120
10,000

80

100

ns

10,000

ns

3

ns

C11

15

20

20

cf

ns
55

140
10,000

Notes

Max

tCSR

U)

N

See notes 1, 2) (Continued)

ns

NOTES:
1. An initial pause of 200 fLs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved.
2. VIN(min) and Vldmax) are referenced levels for measuring timing of input signals. Transition times are measured between VIH(min) and Vldmax) and are assumed to be 5 ns
for all inputs.
3. Measured with a load equivalent to 2 TIL loads and 100 pF.
4. Operation within the tRCO(max) limit insures that tRAc(max) can be met. tRco(max) is specified as a reference point only. If tRCO is greater than the specified tRCO(max) limit,
then access time is controlled exclusively by tCAC.
5. Assumes that tRco :?: tRCO(max).
6. tAR, tWCR, tOHR are referenced to tRAo(max).
7. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL'
8. twcs, tRWO, tcwo and tAWO are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs :?: twcs(min) the cycle is
an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tcwo :?: tcwo(min) and tRWO :?: tRWO(min) and tAWO :?: tRWO(min) and
tAWO :?: tAWO(min), then the cycle is a read-write cycle and the data out will contain the data read from the selected address. If neither of the above conditions are satisfied,
the condition of the data out is indeterminate.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write cycles.
11. Operation within the tRAO(max) limit insures that tRAc(max) can be met. tRAO(max) is specified as a reference point only. If tRAo is greater than the specified tRAO(max)
limit, then access time is controlled by tAA.

...
I\)

en
"'"
"'"

21464

TIMING DIAGRAMS
READ CYCLE
IRe
I RP
RAS

CAS

V'H VIL -

V1H Vil. -

V1H VIL -

Vi

Of

DO,-DO.

V'H VIL -

V1H VIL -

~DH

----OPEN
DL -

240022-5

WRITE CYCLE (EARLY WRITE)

IDHR~
I-tDH

IDSg

~~~~!:~------

1H
VVIL -_ - - - - - - ~'!lID o~

OPEN-------

240022-7

NOTE:

~ DOH'T~ARE

OE = Don't Care

240022-6

3-26

infef

21464

TIMING DIAGRAMS

(Continued)

WRITE CYCLE (OE CONTROLLED WRITE)

V1H -

RAS

Vil -

CAS

A

Vi

Of

DQ,-DQ4

V1H -

V1L V1H V1l -

V1H V1L -

240022-8

READ-MODIFY-WRITE CYCLE

~--------------------~WC--------------------~
~-----------------t~s----------------~

RAS

V1H V1L -

....;.._ _-,iJ----tAR

~__+---------tRSH-----------+_l

CAS

V1H V1L -

A

V'H V1L -

Vi

Of

DO
,-

J;:::j.j:::=~!:;:::j~t-------tCAS--------Ir+....,.

__"'\

V 1H -

V1L V1H V1L -

DO VI/OH 4 VI/OL -

240022-9

~

DON'T CARE

240022-6 •

3-27

intJ

21464

TIMING DIAGRAMS

(Continued)

PAGE MODE READ CYCLE

RAS

,V'H V'L -

CAS

V'H V'L -

A

V'H V'L -

Vi

V'H V'L -

OE

V'H V'L -

OQ,-OQ4

VOH VOL -

240022-10

PAGE MODE WRITE CYCLE

RAS

V'H V'L -

CAS

V'H V'L -

A

V1H V'L -

Vi

V1H V1L . -

OE

OQ,_OO4

V1H V'L -

V1H V'L -

240022-11

NOTE:
OE = Don't Care

~

DON'T CARE

240022-6

3-28

21464

TIMING DIAGRAMS

(Continued)

PAGE MODE READ-MODIfY-WRITE CYCLE

Vi

V1H V1L -

DE

V1H V1L -

240022-18

~

DON'T CARE

240022-6

3-29

21464

TIMING DIAGRAMS

(Continued)

RA8--0NLY REFRESH CYCLE

1----------tRc----------i

V1H -

~:A.7'V\7'\"''O\ .T.....:-----i.,~:""7'r~~~""l"r"7r"'l~:""7'r~~~""l"r"7r"'l~:""7'r~

V1L -

~~~Q/.~~ ~-----.;r"..K..x..l~~~~~..K..x..l~~~~~..K..x..l~

DATA VOH -

--------------HIGH-Z--------------

ADDRESS

(OUT) VOL -

240022-12

NOTE:

CAS

= VIH;

VIi,

OE, D = Don't Care.

CA8--BEFORE-RAS REFRESH CYCLE

i--------tRc-------..J

DATA

VOH - ----:LI>-_ _ _ _ _ _ _ _ _ _ _ _ _ HIGH_Z __________.....,__

(OUT) VOL 240022-13

NOTE:
Address VIi, OE, D = Don't Care.

~

DON"TCARE

240022-6

3-30

21464

TIMING DIAGRAMS

(Continued)

HIDDEN REFRESH CYCLE (READ)

RAS

CAS

A

VIH V1L -

VIH V1L -

VIH -

Vit. -

Vi

VIH V1L -

OE

VIH V1L -

DO,-DQ,

VIH -

V1L -

240022-14

~

DON'T CARE

240022-6

HIDDEN REFRESH CYCLE (WRITE)

RAS

CAS

A

Vi

OE

DO,_DO,

VIH -

V1L -

VIH -

V1L -

VIH V1L -

VIH -

V1L -

VIH V1L -

VIH -

Vil f-----tDH.--~

240022-19

~
240022-6

3-31

DON'T CARE

21464

TIMING DIAGRAMS

(Continued)

CAS-BEfORE-RAS REfRESH COUNTER TEST CYCLE
~----------------tAAS----------------~
RAS

V1H V1L -

CAS

V1H V1L -

A

V1H V1L -

t---------tRsH--------+/
1~----_(t--------tCAS------~~~---------

READ CYCLE
Vi

V1H V1L -

OE

V1H V1L -

OQ1_0Q 4

VOH VOL -

OPEN

WRITE CYCLE
Vi

V1H V1L -

OE

V1H V1L -

OQ1- oo4

V1H V1L -

Vi

V1H V1L -

OE

V1H V1L -

OQ1_0Q4

VI/OH VI/OL -

240022-20

~

DON'T CARE

240022-6

3-32

21464

tRCO(max), the access time is measured from CAS
and is specified by tCAC. In order to achieve the minimum access time, tRAdmin), it is necessary to bring
CAS low before tRCO(max).

DEVICE OPERATION
The 21464 contains 262,144 memory locations organized as 65,536 4-bit words. Sixteen address bits
are required to address a particular 4-bit word in the
memory array. Since the 21464 has only 8 address
input pins, time multiplexed addressing is used to
input 8 row and 8 column addresses. The multiplexing is controlled by the timing relationship between
the row address strobe (RAS) , and the column address strobe (CAS) and the valid address inputs.

Write
The 21464 can perform early write and read-modifywrite cycles. The difference between these cycles is
in the state of data-out and is determined by the
timing relationship between W, OE and CAS. In any
type of write cycle Data-in must be valid at or before
the falling edge of W or CAS, whichever is later.

Operation of the 21464 begins by strobing in a valid
row address with RAS while CAS remains high.
Then the address on the 8 address input pins is
changed from a row address to a column address
and is strobed in by CAS. This is the beginning of
any 21464 cycle in which a memory location is accessed. The specific type of cycle is determined by
the state of the write enable pin and various timing
relationships. The cycle is terminated when both
RAS and CAS have returned to the high state. Another cycle can be initiated after RAS remains high
long enought to satisfy the RAS precharge time (tRP)
requirement.

Early Write: An early write cycle is performed by
bringing W low before CAS. The 4-bit wide data at
the data input pins is written into the addressed
memory cells. Throughout the early write cycle the
outputs remain in the Hi-Z state regardless of the
state of the OE input.
Read-Modify-Write: In this cycle, valid data from
the addressed cells appears at the outp'uts before
and during the time that data is being written into the
sam~cell locations. This cycle is achieved by bringing W low after CAS and meeting the data sheet
read-modify-write timing requirements. The output
enable input (OE) must be low during the time defined by tOEA and toEZ for data to appear at the
outputs. If tewo and tRWO are not met the output
may contain invalid data. Conforming to the OE timing requirements prevents bus contention on the
21464 DQ pins.

RAS and CAS Timing
The minimum RAS and CAS pulse widths are specified by tRAS(min) and tcAS(min) respectively. These
minimum pulse widths must be satisfied for proper
device operation and data integrity. Once a cycle is
initiated by bringing RAS low, it must not be aborted
prior to satisfying the minimum RAS and CAS pulse
widths. In addition, a new cycle must not begin until
the minimum RAS precharge time, tRP, has been
satisfied. Once a cycle begins, internal clocks and
other circuits within the 21464 begin a complex sequence of events. If the sequence is broken by violating minimum timing requirements, loss of data integrity can occur.

Data Output
The 21464 has tri-state output buffers which are
controlled by CAS and OE. When either CAS or OE
is high (VIH) the outputs are in the high impedance
(Hi-Z) state. In any cycle in which valid data appears
at the outputs, the outputs first remain in the Hi-Z
state until the data is valid and then the valid data
appears at the outputs. The valid data remains at the
outputs until either CAS or OE returns high. This is
true even if a new RAS cycle occurs (as in hidden
refresh). Each of the 21464 operating cycles is listed
below after the corresponding output state produced
by the cycle.

Read
A read cycle is achieved by maintaining the write
enable input (W) high during a RAS/CAS cycle. The
four outputs of the 21464 remain in the Hi-Z state
until valid data appears at the outputs. The 21464
has common data 1/0 pins. For this reason an output enable control input (OE) has been provided so
the output buffer can be precisely controlled. For
data to appear at the outputs, OE must be low for
the period of time defined by tOEA and toEZ. If CAS
goes low before tRCO(max), the access time to valid
data is specified by tRAC. If CAS goes low after

Valid Output Data: Read, Read-Modify-Write, Hidden Refresh, Page Mode Read, Page Mode, ReadModify-Write.
Hi-Z Output State: Early Write, RAS-Only Refresh,
Page Mode Write, CAS-Only CyCle.

3-33

inter

21464

strobe in additional column addresses. This eliminates the time required to set up and strobe sequential row addresses for the same page.

Indeterminate Output State; Delayed Write (tewD
or tRWD are not met).

Refresh

Power-Up

.The data in the 21464 is stored on a tiny capacitor
within each memory cell. Due to leakage the data
will'leak off after a period of time. To maintain data
integrity it is necessary to refresh each of the rows
every 4 ms. There are several ways to accomplish
this.

If RAS = Vss during power-up, the 21464 might
begin an active cycle. This condition results in higher
than necessary current demands from the power
supply during power-up. It is recommended that AS
and CAS track with Vee during power-up or be held
at a valid VIH in order to minimize the power-up current.

RAS-Only Refresh: This is the most common method for performing refresh. It is performed by strobing
in a row address with RAS while CAS remains high.
'This must be performed on each of the 256 row addresses (Ao-A7) every 4 ms.
CAS-Before-RAS Refresh: The 21464 has CASBefore-RAS refresh capability that eliminates the
need for external refresh addresses. If CAS is held
low for the specified set-up time (tesR) before RAS
goes low, the on-chip refresh circuity is enabled. An
internal refresh operation automatically occurs and
the on-chip refresh address counter is internally incremented in preparation for the next CAS-BeforeRAS refresh Cycle:
Hidden Refresh: A hidden refresh cycle may be
performed while maintaining the lastest valid data at
the outputs by extending the CAS active time and
cycling RAS. The 21464 hidden refresh cycle is actually a CAS-Before-RAS refresh cycle within an extended read cycle. The refresh row address is provided by the on-chip refresh address counter. This
eliminates the need for the external row address
that is required in hidden refresh cycles by DRAMS
that do not have CAS-Before-RAS refresh capability.

An initial pause of 100 p.s is required after power-up
followed by 8 initialization cycles before proper device operation is assured. Eight initializations cycles
are also required after an 4 ms period in which there
are no RAS cycles. An initialization cycle is any cycle
in which RAS is cycled.
I

Termination
The lines from the TTL driver circuits to the 21464
inputs act like unterminated transmission lines resulting in significant positive and negative overshoots at the inputs. To minimize overshoot it is advisable to terminate the input lines and to keep them
as short as possible. Although either series or parallel termination may be used, series termination is
generally recommended since it is simple and draws
no additional power. It consists of a resistor in series
with the input line placed close to the 21464 input
pin. The optimum value depends on the board layout. It must be determined experimentally and is
usually in the range of 20.0. to 40.0..

Board Layout

Other Refresh Methods: It is also possible to refresh the 21464 by using read, write or read-modifywrite cycles. Whenever a row is accessed all the
cells in that row are automatically refreshed. There
are certain applications in which it might be advantageous to perform refresh in this manner but in general RAS-only or CAS-Before-RAS refresh are the preferred methods.

It is important to layout the power and ground lines
on memory boards in such a way that switching transient effects are minimized. The recommended
methods are gridded power and ground lines or separate power and ground planes. The power and
ground lines act like transmission lines to the high
frequency transients generated by DRAMs. The impedance is minimized if all the power supply traces
to all the DRAMs run both horizontally and vertically
and. are connected at each intersection, or better
yet, if power and ground planes are used.

Page Mode
Page mode memory cycles provide faster access
and lower power dissipation than normal memory
cycles. In page mode, it is possible to perform read,
write or read-modify-write cycles. As long as the applicable timing requirements are observed, it is possible to mix these cycles in any order. A page mode
cycle begins with a normal cycle. While RAS is kept
low to maintain the row address, CAS is cycled to

Address and control lines should be as short as possible to avoid skew. In boards with many DRAMs
these lines should fan out from a central point like a
fork or comb rather than being connected in a serpentine pattern. Also the control logiC should be
centrally located on the memory boards to facilitate

3-34

21464

the shortest possible address and control lines to all
the DRAMs.

ground pins of each 21464 using the shortest possible traces. These capacitors act as a low impedance
shunt for the high frequency switching transients
generated by the 21464 and they supply much of the
current used by the 21464 during cycling.

Decoupling
The importance of proper decoupling cannot be
overemphasized. Excessive transient noise or voltage droop on the Vee line can cause loss of data
integrity (soft errors). The total combined voltage
changes over time in the Vee to Vss voltage (measured at the device pins) should not exce,ed 500 mV.

In addition, a large tantalum capacitor with a value of
47 ILF to 100 ILF should be used for bulk decoupling
to recharge the 0.3 ILF capacitors between cycles,
thereby reducing power line droop. The bulk decoupiing capacitor shuld be placed near the point where
the power traces meet the power grid or power
plane. Even better results may be achieved by distributing more than one tantalum capacitor around
the memory array.

A high frequency 0.3 ILF ceramic decoupling capacitor should be connected between the Vee and

PACKAGE DIMENSIONS
l8-LEAD PLASTIC DUAL IN·LINE PACKAGE

~ ~ ~ -"r.lI'" "l:~ "r': I(E.,J~ECTr°,!:R"=rM.,A~RKr)rP: r-r I
I.

.1

J

r -........................................

~~

r

E

~SEATING

f!

PLANE

G

----1

L

K

K

240022-15

Item

Millimeters

Inches

A

22.950 ± 0.05

0.903 ± 0.002
0.252 ± 0.002

B

6.40 ± 0.05

C

7.62

0.300

D

0.025 ± 0.025

0.010 ± 0.001

E

3.25 ± 0.05

0.128 ± 0.002

F

0.506 ± 0.1

0.020 ± 0.004

G

3.302 ± 0.1

0.130 ± 0.004

H

2.54

0.100

,

I

1.27 ± 0.05

0.050 ± 0.002

J

0.457 ± 0.05

0.Q18 ± 0.002

K

1.32

0.052
3-35

inter

21464

PACKAGE DIMENSIONS

(Continued)

1S·PI" PLASTIC LEADED CHIP CARRIER

IT
D

C

[

~------L------~

240022-16

Item

Millimeters

Inches

Item

Millimeters

Inches

A

12.346 ± 0.052

0.490 ± 0.002

H

6.553 ± 0.051

0.258 ± 0.002

B

13.2585 ± 0.0505

0.522 ± 0.002

I

0.43 type

0.017typ

C

7.366 ± 0.051

0.290 ± 0.002

J

0.279 ± 0.025

0.011 ± 0.001

D

8.179 ± 0.051

0.322 ± 0.002

K

0.76 typ

O.030typ

E

2.083 ± 0.051

0.082 ± 0.002

L

11.8365 ± 0.0505

0.466 ± 0.002

F

3.505 ± 0.051

0.138 ± 0.002

M

6.756 ± 0.051

0.266 ± 0.002

G

0.7365 ± 0.0505

0.029 ± 0.002

20·LEAD ZIG·ZAG INLINE PACKAGE (ZIP)

1---------------- : :g~~

---------------1'1

o
I

o.olojL
REf.

0.01S-0.022J

L

0.fl50 TYP....

I

240022-17

3-36

21010
1,048,576 x 1-Bit Dynamic RAM with Page Mode
Performance Range

•

tRAC

tCAC

tRC

21010-06

60ns

20 ns

110 ns

21010-07

70 ns

20 ns

130 ns

21010-08

80 ns

20 ns

160 ns

21010-10

100 ns

25 ns

190 ns

• Single 5V

Fast Page Mode Operation

+

10% Power Supply

• CAS before RAS Refresh Capability

•

512 Cycles/S ms refresh

• Common I/O Using "Early Write"

•

Available in Plastic DIP, SOJ and ZIP
Packages

Intel 21010 is a CMOS high speed 1,048,576 x 1 dynamic RAM optimized for high performance applications
such as mainframes, graphics and microprocessor systems.
21010 features Fast Page Mode operation which allows high speed random access of memory cells within the
same row.
CAS before RAS refresh capability provides on-chip auto refresh as an alternative to RAS only refresh. All
Inputs, Output and Clocks are fully CMOS and TTL compatible.
Functional Block Diagram

"'---1..---'

.....,"""T-..~-----~~

W

iii .......

PIN CONFIGURATION
DIP

ZIP

SOJ

SENSE AMPS &: I/O GAnNGS
AD

...

I

MEMORY ARRA.Y
1048,576 CELLS

+-Vee
+-V55

240153-2

~

240153-16
240153-3

U L-L-L-_ _ _ _ _~
240153-1

NOTE:
T.F. = Test Function, Ground or No Connect

Pin Names
Ao-Ag Address Inputs

W

3-37

Read/Write Strobe

RAS

Row Address Strobe

CAS

Column Address Strobe

0

Data In

Q

Data Out

VSS

Ground

Vee

Power +5V

August 1990
Order Number: 240153-005

21010

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Voltage on Any Pin Relative to vss
(VIN. VOUT) .................... -1V to + 7.0V

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
'may affect device reliability.

Voltage on Power Supply Relative to Vss
(Vcd ............... : .......... -1V to +7.0V
Storage Temperature (Tslg) ..... - 55°C to + 150°C
Power Dissipation (Pd) ................... 600 mW
Short Circuit Output Current (los) '........... 50 mA

RECOMMENDED OPERATING CONDITIONS
= O°C to + 70°C)

(Voltage Referenced to Vss. TA

Symbol

Parameter

Min

Typ

Max

Units

Vcc

Supply Voltage

4.5

5.0

5.5

V

Vss

Ground

0

0

0

V

VIH

Input High Voltage

2.4

VCC + 1

V

VIL

Input Low Voltage

-1.0

0.8

V

NOTES:

1. VIL (Min) = - 1.0V for continuous DC level.
2. VIL (Min) = -2.0V for pulse width < 20 ns.

Capacitance
Symbol

(TA = 25°C)

Parameter

Min

Max

Units
pF

Cinl

Input Capacitance (Ao-A9. D)

6

Cin2

Input Capacitance (RAS. CAS. WE)

7

pF

Cout

Output Capacitance (0)

7

pF

D.C. AND OPERATING CHARACTERISTICS
(Recommended Operating Conditions unless Otherwise Noted)

Symbol

Speed

Parameter

Min

Max

Units

ICCl
ICCl

Operating Current
(RAS and CAS Cycling
@tRC = Min

-06
-07
-08
-10

90
80
70
60

mA
mA
mA
mA

ICC2

Standby Current
(TTL Power Supply Current)

-06

2

mA

ICC3
ICC3

RAS Only Refresh Current
(CAS = VIH. RAS Cycling
@tRC = Min

-06
-07
-08
-10

90
80
70
60

mA
mA
mA
mA

ICC4
ICC4

Fast Page Mode Current
(RAS = VIL. CAS Cycling
@tpc = Min

-06
-07
-08
-10

70
60
50
40

mA
mA
mA
mA

3-38

21010

D.C. AND OPERATING CHARACTERISTICS (Continued)
(Recommended Operating Conditions unless Otherwise Noted)

Symbol

Parameter

Speed

Min

Max

Units

1

mA

90
80
70
60

mA
mA
mA
mA

ICC5

Standby Current
(CMOS Power Supply Current)

ICC6

CAS-before-RAS Refresh
Current (RAS and CAS Cycling
@tRC = Min

IlL

Input Leakage Current
(Any Input 0 < VIN < 6.5V
All Other Pins = OV)

-10

10

/LA

IOL

Output Leakage Current
(Data Out is Disabled
and 0 < VOUT < 5.5V)

-10

10

/LA

VOH

Output High Voltage Level
(IOH = -5mA)

2.4

VOL

Output Low Voltage Level
(IOL = 4.2 mAl

-06
-07
-08
-10

V
0.4

V

NOTE:

ICC1, ICC3, ICC4, and ICC6 are dependent on output loading and cyCle rates. Specified values are obtained with the output
open. Icc is specified as average current.

A.C. CHARACTERISTICS
(TA = O·C to +70·C, VCC = 5V
Symbol

Parameter

(See Notes 1,2)
+ 10%)

21010-06
Min

Max

21010-07
Min

8

Max

21010-08

21010-10

Min

Min

8

Max

Notes

tREF

Time between
Refresh

tRC

RandomR/W
Cycle Time

110

tRWC

RMW Cycle Time

135

tRAC

Access Time
from RAS

60

70

80

100

ns

(Notes 4, 7)

tCAC

Access Time
from CAS

20

20

20

25

ns

(Notes 5,7)

tAA

Access Time from
Column Address

30

35

40

50

ns

(Notes 6, 7)

tCLZ

CAS to Output in
LowZ

0

toFF

Output Buffer TurnOff Delay Time

0

20

0

20

0

20

0

20

ns

tT

Transition Time

3

50

3

50

3

50

3

50

ns

130

8

Units

Max

160

190

185

155

0

ms
ns

220

0

3-39

8

ns

0

ns

inter

21010

A.C. CHARACTERISTICS (See Notes 1, 2)
(TA = ODC to + 70DC, VCC = 5V ,+ 10%) (Continued)
Symbol

Parameter

21010-06

21010-07

21010·08

21010-10

Min

Min

Min

Min

Max

Max

Notes

RAS Precharge
Time

40

tRAS

RAS Pulse Width

60

tRSH

RAS Hold Time

20

20

25

25

ns

tCRP

CASto RAS
Precharge Time

5

5

5

5

ns

tRCD

RAS to CAS
Delay Time

20

40

tCAS

CAS Pulse Width

20

10K

tCSH

CAS Hold Time

60

70

80

100

ns

tCPN

CAS Precharge
Time

10

10

15

15

ns

'tASR

Row Address
Set-Up Time

0

0

0

0

ns

tRAH

Row Address
Hold Time

10

10

15

15

ns

tASC

Column Address
Set-UpTime

0

0

0

0

ns

tCAH

Column Address
Hold Time

15

15

20

20

ns

tAR

Column Address
Time Referenced
toRAS

50

55

65

75

ns

tRAD

RAS to Column
Address Delay Time

15

tRAL

Column Address to
RAS Lead Time

30

35

40

50

ns

tRCS

Read Command
Set-UpTime

0

0

0

0

ns

tRRH

Read Command
Hold Time
Referenced to RAS

0

0

0

0

ns

(Note 12)

tRCH

Read Command
Hold Time
Referenced to CAS

0

0

0

0

ns

(Note 12)

twcs

Write Command
Set-Up Time

0

0

0

0

ns

(Note 13)

twci-!

Write Command
Hold Time

15

15

20

20

ns

10K

30

70

70

Units

Max

tRP

,

50

Max

10K

20

50

20

10K

15

35

3-40

80

80
10K

25

60

20

10K

20

40

100

ns
10K

ns

25

75

ns

25

10K

ns

20

50

ns

(Notes 9, 10)

(Note 11)

inter

21010

A.C. CHARACTERISTICS
(TA = O·C to +70·C, Vec = 5V
Symbol

(See Notes 1, 2)
+ 10%) (Continued)

Parameter

21010·06

21010·07

Min

Min

Max

Max

21010·08

21010-10

Min

Min

Max
60

Max
75

Units

tWCR

Write Command
Referenced to RAS

50

55

twp

WE Pulse Width

15

15

15

20

ns

tRWL

Write Command to
RAS Lead Time

20

20

25

25

ns

tcWL

Write Command to
CAS Lead Time

20

20

20

25

ns

tDS

DIN Set-Up Time

0

0

0

0

ns

Notes

ns

tDH

DIN Hold Time

15

15

20

20

ns

tDHR

Data-In Hold Time
Referenced to RAS

50

55

60

75

ns

tRWD

RAS to WE Delay Time

60

70

80

100

ns

(Note 13)

tcWD

CAS to WE Delay Time

20

20

20

25

ns

(Note 13)

tAWD

Column Address to
WE Delay Time

30

35

40

50

ns

tRPC

RAS Precharge Time to
CAS Active Time

10

10

10

10

ns

tesR

CAS Set-Up Time
for CAS before
RAS Refresh

10

10

10

10

ns

tCHR

CAS Hold Time for CAS
before RAS Refresh

20

20

30

30

ns

tePT

Refresh Counter Test
CAS Precharge Time

30

35

40

50

ns

3-41

intJ

21010

A.C. CHARACTERISTICS (See Notes 1. 2)
(TA = O°C to + 70°C. VCC = 5V + 10%) (Continued)
Symbol

Parameter

21010-06
Min

Max

21010-07
Min

Max

21010-08
Min

Max

21010-10
Min

Max

Units

Notes

FAST PAGE MODE
tpc

Fast Page Mode
Cycle Time

45

45

50

60

ns

tPRWC

Fast Page Mode
RMWCycle
Time

70

70

75

90

ns

tePA

Access Time
from CAS
Precharge

tcp

Fast Page Mode
CAS Precharge
Time

10

tRASP

RASPulse
Width (Fast
Page Mode)

60

40

40

10

100K

70

45

10

10

100K

80

55

100K

100

ns

(Notes 7.14)

ns

100K

ns

NOTES:
1. An initial pause of 200 ".s is required after power-up followed by any 8 RAS-only cycles before proper device operation is
achieved.
2. A.C. characteristics assume tT = 5 ns.
3. VIN (min) and VIL (max) are reference levels for measuring timing of input signals. Also. transition times are measured
between VIH (min) and VIL (max) ..
4. Assumes that tRCD ,;; tRCD (max). tRAD ,;; tRAD (max). If tRCD (or tRAD) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCD (or tRAD) exceeds the value shown.
5. If tRCD ;;, tRCD (max). tRAD ;;, tRAD (max). and tASC ;;, tAA - !cAC - tT access time is tCAC'
6. If tRAD ;;, tRAD (max) and tASC ,;; tAA - tCAC - tT. access time is tAA'
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. !oFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point
only; if tRCD is greater than the specified tRCD (max) limit. access time is controlled exclusively by tCAC or tAA.
10. tRCD (min) = tRAH (min) + 2 tT + tASC (min).
.
11. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference pOint
only; if tRAD is greater than the specified tRAD (max) limit. access time is exclusively controlled by tCAC or tAA'
12. Either tRRH or tRCH must be specified for a read cycle.
.
13. tWCS. !cwo. tRWD. and tAWD are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
.
14. !cPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").

3-42

21010

Read Cycle
t Rc
t RAS
RAS

VIH VIL -

CAS

VIH VIL -

tAR

t RSH

leAs
tRAL

A

VIH VIL -

Vi

----------OPEN

Q

-----