1991_Intel_Memory_Products 1991 Intel Memory Products
User Manual: 1991_Intel_Memory_Products
Open the PDF directly: View PDF 
.
Page Count: 1100
| Download | |
| Open PDF In Browser | View PDF |
Intel Corporation is a leading supplier of microcomputer components,
modules and systems. When Intel invented the microprocessor in 1971, it
created the era of the microcomputer. Today, Intel architectures are considered
world standards. Whether used in embedded applications such as automobiles,
printers and microwave ovens, or as the CPU in personal computers, client
servers or supercomputers, Intel delivers leading-edge technology.
MEMORY PRODUCTS
1991
About Our Cover.'
Thinkers, inventors, and artists throughout history have breathed
life into their ideas by converting them into rough working sketches, models,
and products. This series of covers shows a few of these creations, along
with the applications and products created by Intel customers.
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel products:
287, 376, 386, 387, 486, 4-SITE, Above, ACE51 , ACE96, ACE186, ACE196, ACE960,
ActionMedia, BITBUS, COMMputer, CREDIT, Data Pipeline, DVI, ETOX, FaxBACK,
Genius, i, 1, i486, i750, i860, ICE, iCEL, ICEVIEW, iCS, iDBP, iDIS, 12 1CE, iLBX, iMDDX,
iMMX, Inboard, Insite, Intel, intel, Inte1386, intelBOS, Intel Certified, Intelevision, inteligent
Identifier, inteligent Programming, Intellec, Intellink, iOSP, iPAT, iPDS, iPSC, iRMK, iRMX,
iSBC, iSBX, iSDM, iSXM, Library Manager, MAPNET, MCS, Megachassis,
MICROMAINFRAME,
MULTICHANNEL,
MULTIMODULE,
MultiSERVER,
ONCE,
OpenNET, OTP, Pr0750, PROMPT, Promware, QUEST, QueX, Quick-Erase, Quick-Pulse
Programming, READY LAN, RMX/80, RUPI, Seamless, SLD, SugarCube, SX, TooITALK,
UPI, VAPI, Visual Edge, VLSiCEL, and ZapCode, and the combination of ICE, iCS, iRMX,
iSB'C, iSBX, iSXM, MCS, or UPI and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk
Data Sciences Corporation.
CHMOS and HMOS are patented processes of Intel Corp.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FAST PATH trademark or products.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
©INTEL CORPORATION 1990
CUSTOMER SUPPORT
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
Customer Support is Intel's complete support service that provides Intel customers with hardware support,
software support, customer training, consulting services and network management services. For detailed information contact your local sales offices.
After a customer purchases any system hardware or software product, service and support become major
factors in determining whether that product will continue to meet a customer's expectations. Such support
requires an international support organization and a breadth of programs to meet a variety of customer needs.
As you might expect, Intel's customer support is extensive. It can start with assistance during your development
effort to network management. 100 Intel sales and service offices are located worldwide-in the U.S., Canada,
Europe and the Far East. So wherever you're using Intel technology, our professional staff is within close
reach.
HARDWARE SUPPORT SERVICES
Intel's hardware maintenance service, starting with complete on-site installation wiII boost your productivity
from the start and keep you running at maximum efficiency. Support for system or board level products can be
tailored to match your needs, from complete on-site repair and maintenance support to economical carry-in or
mail-in factory service.
Intel can provide support service for not only Intel systems and emulators, but also support for equipment in
your development lab or provide service on your product to your end-user/customer.
SOFTWARE SUPPORT SERVICES
Software products are supported by our Technical Information Service (TIPS) that has a special toll free
number to provide you with direct, ready information on known, documented problems and deficiencies, as
well as work-arounds, patches and other solutions.
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information Phone Service), updates and subscription service (product-specific troubleshootmg guides and;
COMMENTS Magazine). Basic support consists of updates and the subscription service. Contracts are sold in
environments which represent product groupings (e.g., iRMX® environment).
NETWORK SERVICE AND SUPPORT
Today's broad spectrum of powerful networking capabilities are only as good as the customer support provided
by the vendor. Intel offers network services and support structured to meet a wide variety of end-user computing needs. From a ground up design of your network's physical and logical design to implementation, installation and network wide maintenance. From software products to turn-key system solutions; Intel offers the
customer a complete networked solution. With over 10 years of network experience in both the commercial
and Government arena; network products, services and support from Intel provide you the most optimized
network offering in the industry.
CONSULTING SERVICES
Intel provides field system engineering consulting services for any phase of your development ,or application
effort. You can use our system engineers in a variety of ways ranging from assistance in using a new product,
developing an application, personalizing training and customizing an Intel product to providing technical and
management conSUlting. Systems Engineers are well versed in technical areas such as microcommunications,
real-time applications, embedded microcontrollers, and network services. You know your application needs;
we know our products. Working together we can help you get a successful product to market in the least
possible time.
CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering various aspects of system design and implementation. In just three to ten days a limited number of individuals learn more in a single workshop than in weeks of
self-study. For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we
can take our workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course
categories include: architecture and assembly language, programming and operating systems, BITBUS'" and
LAN applications.
DATA SHEET DESIGNATIONS
Intel uses various data sheet markings to designate each phase of the document as it
relates to the product. The marking appears in the upper, right-hand corner of the data
sheet. The following is the definition of these markings:
Data Sheet Marking
Description
Product Preview
Contains information on products in the design phase of
development; Do not finalize a design with this
information. Revised information will be published when
the product becomes available.
Advanced Information
Contains information on products being sampled or in
the initial production phase of development. *
Preliminary
Contains preliminary information on new products in
production. *
No Marking
Contains information on products in full production. *
*Specifications within these data sheets are subject to change without notice. Verify with your local Intel sales
office that you have the latest data sheet before finalizing a design.
Memory Overview
Memory Technologies
Dynamic RAMs
(Random Access Memories)
Static RAMs
(Random Access Memories)
EPROMs
(Erasable Programmable
Read Only Memories)
Flash Memories (Electrically
Erasable and Reprogrammable
Non..Volatile Memories)
Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xi
CHAPTER 1
Memory Overview
Memory Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
CHAPTER 2
Memory Technologies
Intel Memory Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
CHAPTER 3
Dynamic RAMs (Random Access Memories)
DATA SHEETS
21256 262,144 x 1-Bit Dynamic RAM with Page Mode .........................
2146465,536 x 4-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .
21010 1,048,576 x 1-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . .
21014 262,144 x 4-Bit Dynamic RAM with Page Mode .........................
21040 4,194,304 x 1-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . .
2D2569 256K x 9-Bit High Density Dynamic RAM Memory Module with Page Mode
21019 1,048,576 x 9-Bit Dynamic RAM Memory Module with Page Mode. . . . . . . ..
225636 256K x 36-Bit Dynamic RAM Memory Module with Page Mode .......... ,
251236 512K x 36-Bit Dynamic RAM Memory Module with Page Mode. . . . . . . . . ..
RELIABILITY REPORT
RR-62 Dynamic RAM Reliability Report ......................................
3-1
3-19
3-37
3-53
3-69
3-90
3-107
3-124
3-141
3-158
CHAPTER 4
Static RAMs (Random Access Memories)
DATA SHEETS
5116S/L 2K x 8-Bit CMOS Static RAM.. . .. . . . . .. . .. .. .. . . . .. . . .. . . .. . . . . . . . .
5164S/L 8K x 8-Bit CMOS Static RAM.. .. . . . . . . . . . . .. .. . . . .. .. . . . . .. . . .. . . . .
51256S/L 32K x 8-Bit CMOS Static RAM.....................................
51C68 High Speed CHMOS 4096 x 4-Bit Static RAM...........................
51C98 High Speed CHMOS 16,384 x 4-Bit Static RAM.........................
5164 High Speed 8192 x 8-Bit Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51256 High Speed 32K x 8-Bit Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51258 High Speed 64K X 4-Bit Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RELIABILITY REPORT
RR-63 Static RAM Reliability Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4-9
4-18
4-26
4-32
4-39
4-47
4-56
4-63
CHAPTER 5
EPROMs (Erasable Programmable Read Only Memories)
DATA SHEETS
2716 16K (2K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2732A 32K (4K x 8) UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2764A 64K (8K x 8) UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27128A 128K (16K x 8) Production and UV Erasable PROMs ...................
27256 256K (32K x 8) Production and UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . .
27C256 256K (32K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27C512 512K (64K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . .
27C513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM. . . . . . . . . . . . . . . .
27C011 Page-Addressed 1M (8 x 16K x 8) EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C010 1M (128Kx8) CHMOS EPROM .....................................
27C100 1M (128K x 8) CHMOS EPROM .....................................
27C020 2M (256K x 8) CHMOS EPROM .....................................
27C040 4M (512K x,8) CHMOS EPROM.....................................
ix
5-1
5-9
5-18
5-28
5-38
5-50
5-62
5-72
5-85
5-100
5-113
5-124
5-134
5-144
Tabie of Contents (Continued)
27C210 1M (64K x 16) CHMOS EPROM .....................................
27C220 2M (128K x 16) CHMOS EPROM ....................................
27C240 4M (256K x 16) CHMOS EPROM ....................................
27C400 4M (256K x 16 or 512K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . ..
27960CX Pipelined Burst Access 1M (128K x 8) CHMOS EPROM ...............
27960KX Burst Access 1 M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . ..
APPLICATION NOTES
AP-329 68030/27960CX Burst EPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-346 29000/27960CX Burst EPROM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RELIABILITY REPORTS
RR-35 EPROM Reliability Data Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RR-67 EPROM Reliability Data Summary CHMOS III-E. . . . . . . . . . . . . . . . . . . . . . . ..
ARTICLE REPRINTS
AR-414 Marriage of CMOS and PLCC Sparking Rapid Change in Mounting
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-455 One Time Programmable EPROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-458 OTP EPROMs with Quick-Pulse Programming Offer Ideal Mass Production
Firmware Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-468 Keeping Data Safe with Nonvolatile Memory. . . . . . . . . . . . . . . . . . . . . . . . . ..
5-154
5-164
5-173
5-182
5-192
5-213
5-232
5-260
5-287
5-341
5-390
5-392
5-395
5-398
CHAPTER 6
Flash Memories (Electrically Erasable and Reprogrammable Non-Volatile
Memories)
Flash: A New Way to Deal with Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA SHEETS
28F256A 256K (32K x 8) CMOS Flash Memory ...............................
28F512 512K (64K x 8) CMOS Flash Memory................................ .
28F010 1024K (128K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28F020 2048K (256K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSM001 FLKA 1 Mbyte (512K x 16) CMOS Flash SIMM . .. . . . . .. .. . . . . . .. . .. . ...
iMC001FLKA 1-Megabyte Flash Memory Card ................................
iMC004FLKA 4-Megabyte Flash Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
APPLICATIt>N NOTES
AP-316 Using Flash Memory for In-System Reprogrammable Nonvolatile Storage.
AP-341 Designing An Updatable BIOS Using Flash Memory ....................
AP-343 Solutions for High Density Applications Using Intel Flash Memory ........
APPLICATION BRIEF
AB-25 Designing in Flexibility with a Universal Memory Site . . . . . . . . . . . . . . . . . . . ..
ENGINEERING REPORTS
ER-20 ETOX II Flash Memory Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
ER-24 The Intel 28F010 Flash Memory ......................................
ARTICLE REPRINTS
AR-463 Don't Write Off the U.S. in Memory Chips .............................
AR-466 Nonvolatility: Semi vs. Mag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... ..
AR-470 A 90 ns 100K Erase/Program Cycle Megabit Flash Memory.............
AR-472 The Memory Driver ............................. :...................
AR-474 Memory Life-Cycle Cost............. ...............................
AR-478 Flash, Best of Two Worlds ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-484 PC Standard in the Cards ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-486 Flash Outshines ROM & EPROM ....................................
AR-490 Flash Memory Operates 10-20 Times Longer . . . . . . . . . . . . . . . . . . . . . . . ..
AR-491 Memory Breakthrough Drives Miniaturization ..........................
x
6-1
6-5
6-30
6-55
6-81
6-109
6-143
6-173
6-203
6-248
6-297
6-365
6-371
6-376
6-390
6-393
6-395
6-399
6-400
6-401
6-406
6-411
6-417
6-419
Alphanumeric Index
210101,048,576 x 1-Bit Dynamic RAM with Page Mode...............................
21014262,144 x 4-Bit Dynamic RAM with Page Mode................................
210191,048,576 x 9-Bit Dynamic RAM Memory Module with Page Mode................
21040 4,194,304 x 1-Bit Dynamic RAM with Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21256 262,144 x 1-Bit Dynamic RAM with Page Mode .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21464 65,536 x 4-Bit Dynamic RAM with Page Mode .................................
225636 256K x 36-Bit Dynamic RAM Memory Module with Pag!3 Mode. . . . . . . . . . . . . . . . ..
251236 512K x 36-Bit Dynamic RAM Memory Module with Page Mode. . . . . . . . . . . . . . . . ..
27128A 128K (16K x 8) Production and UV Erasable PROMs. . . . . . . . . . . . . . . . . . . . . . . . . .
2716 16K (2K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27256 256K (32K x 8) Production and UV Erasable PROMs ............. :.............
2732A 32K (4K x 8) UV Erasable PROMs ........................ . . . . . . . . . . . . . . . . . . .
27513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . .
2764A 64K (8K x 8) UV Erasable PROMs ........................ . . . . . . . . . . . . . . . . . . .
27960CX Pipelined Burst Access 1M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . ..
27960KX Burst Access 1M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C010 1M (128K x 8) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C011 Page-Addressed 1 M (8 x 16K x 8) EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C020 2M (256K x 8) CHMOS EPROM . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C040 4M (512K x 8) CHMOS EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C100 1M (128Kx8) CHMOS EPROM ............................................
27C21 0 1M (64K x 16) CHMOS EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C220 2M (128K x 16) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C240 4M (256K x 16) CHMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C256 256K (32K x 8) CHMOS EPROM ...........................................
27C400 4M (256K x 16 or 512K x 8) CHMOS EPROM· . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
27C512 512K (64K x 8) CHMOS EPROM ...........................................
27C513 Page-Addressed 512K (4 x 16K x 8) UV Erasable PROM ......................
28F010 1024K (128K x 8) CMOS Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28F020 2048K (256K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . .. . . .. . .. .. . . . . . . . . . .
28F256A 256K (32K x 8) CMOS Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28F512 512K (64K x 8) CMOS Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2D2569 256K x 9-Bit High Density Dynamic RAM Memory Module with Page Mode. . . . . . .
5116S/L 2K x 8-Bit CMOS Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51256 High Speed 32K x 8-Bit Static RAM ..........................................
51256S/L 32K x 8-Bit CMOS Static RAM........................ ...................
51258 High Speed 64K x 4-Bit Static RAM ..........................................
5164 High Speed 8192 x 8-Bit Static RAM. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5164S/L 8K x 8-Bit CMOS Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
51 C68 High Speed CHMOS 4096 x 4-Bit Static RAM .................................
51C98 High Speed CHMOS 16,384 x 4-Bit Static RAM................................
AB-25 Designing in Flexibility with a Universal Memory Site. . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-316 Using Flash Memory for In-System Reprogrammable Nonvolatile Storage. . . . . . ..
AP-329 68030/27960CX Burst EPROM Interface ......... . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-341 Designing An Updatable BIOS Using Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-343 Solutions for High Density Applications Using Intel Flash Memory. . . . . . . . . . . . . ..
AP-346 29000/27960CX Burst EPROM Interface ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-414 Marriage of CMOS and PLCC Sparking Rapid Change in Mounting Memories. . . ..
AR-455 One Time Programmable EPROMs .........................................
AR-458 OTP EPROMs with Quick-Pulse Programming Offer Ideal Mass Production
Firmware Storage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-463 Don't Write Off the U.S. in Memory Chips. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-466 Nonvolatility: Semi vs. Mag .................................. ; ...... ". . . . . ..
AR-468 Keeping Data Safe with Nonvolatile Memory .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
xi
3-37
3-53
3-107
3-69
3-1
3-19
3-124
3-141
5-28
5-1
5-38
5-9
5-72
5-18
5-192
5-213
5-113
5-100
5-134
5-144
5-124
5-1.54
5-164
5-173
5-50
5-182
5-62
5-85
6-55
6-81
6-5'
6-30
3-90
4-1
4-47
4-18
4-56
4-39
4-9
4-26
4-32
6-365
6-203
5-232
6-248
6-297
5-260
5-390
5-392
5-395
6-390
6-393
5-398
Aiphanumeric index (Continued)
AR-470 A 90 ns 1OOK Erase/Program Cycle Megabit Flash Memory. . . . . . . . . . . . . . . . . . ..
AR-472 The Memory Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . ..
AR-474 Memory Life-Cycle Cost...................................................
AR-478 Flash, Best ofTwo Worlds. . .. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ..
AR-484 PC Standard in the Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-486 Flash Outshines ROM & EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-490 Flash Memory Operates 10-20 Times Longer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AR-491 Memory Breakthrough Drives Miniaturization.......................... .......
ER-20 ETOX II Flash Memory Technology :.........................................
ER-24 The Intel 28F01 0 Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Flash: A New Way to Deal with Memory ............................ '. . . . . . . . . . . . . .. . .
iMC001 FLKA 1-Megabyte Flash Memory Card.. .. .. . . .. .. .. . . .. . .. .. .. . .. .. .. .. . ....
iMC004FLKA 4-Megabyte Flash Memory Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Intel Memory Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .
iSM001 FLKA 1 Mbyte (512K x 16) CMOS Flash SIMM ...............................
Memory Overview .........................................................,......
RR-35 EPROM Reliability Data Summary .......................... ~ . . . . . . . . . . . . . . ..
RR-62 Dynamic RAM Reliability Report ........... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RR-63 Static RAM Reliability Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RR-67 EPROM Reliability Data Summary CHMOS III-E...............................
xii
6-395
6-399
6-400
6-401
6-406
6-411
6-417
6-419
6-371
6-376
6-1
6-143
6-173
2-1
6-109
1-1
5-287
3-158
4-63
5-341
Memory Overview
1
inter
MEMORY OVERVIEW
MEMORY BACKGROUND
AND DEVELOPMENT
computer systems' insatiable appetites for higher bit
capacities and faster access speeds.
Years ago, MOS LSI memories were little more than
laboratory curiosities. Any engineer brave enough to
design with semiconductor memories had a simple
choice of which memory type to use. The 2102 Static RAM for ease of use or the 1103 Dynamic RAM
for low power were the only two devices available.
Since then, the memory market has come a long
way, the types of memory devices have proliferated,
and more than 3,000 different memory devices are
.now available. Consequently, the designer has many
to choose from but the choice is more difficult, and
therefore, effective memory selection is based on
matching memory characteristics to the application.
RAM Types
Two basic RAM types have evolved since 1970. Dynamic RAMs are noted for high capacity, moderate
speeds and low power consumption. Their memory
cells are basically charge-storage capacitors with
driver transistors. The presence or absence of
charge in a capacitor is interpreted by the RAM's
sense line as a logical 1 or O. Because of the
charge's natural tendency to distribute itself into a
lower energy-state configuration, however, dynamic
RAMs require periodic charge refreshing to maintain
data storage.
Memory devices can be divided into two main categories: volatile and nonvolatile. Volatile memories
retain their data only as long as power is applied. In
a great many applications this limitation presents no
problem. The generic term random access memory
(RAM) has come to be almost synonymous with a
volatile memory in which there is a constant rewriting of stored data.
Traditionally, this requirement has meant that system designers had to implement added circuitry to
handle the dynamic RAM subsystem refresh. And at
certain times, when refresh procedures made the
RAM unavailable for writing and reading; the memory's control circuitry had to arbitrate access. LSI dynamic memory controllers reduce the refresh requirement to a minimal design by offering a monolithic controller solution.
Nonvolatile memories retain their data whether or
not power is applied. In some situations it is critical
that a nonvolatile device be used. An example of this
requirement would be retaining data during a power
failure. (Tape and disk storage are also non-volatile
memories but are not included within the scope of
this book, which confines itself to solid-state technologies in IC form.)
Thus, when conSidering memory devices, it's helpful
to see how the memory in computer systems is segmented by applications and then look at the state-ofthe-art in these cases.
Where users are less concerned with space and
cost than with speed and reduced complexity, the
second RAM type-static RAMs-generally prove
best. Unlike their dynamic counterparts, static RAMs
store ones and zeros using traditional flip-flop logicgate configurations. They are faster and require no
refresh. A user simply addresses the static RAM,
and after a very brief delay, obtains the bit stored in
that location. Static devices are also simpler to design with than dynamic RAMs, but the static cell's
complexity puts these volatile chips far behind dynamics in bit capacity per square mil of silicon.
Volatile Read/Write Memory
Nonvolatile Read-Only Memory
Another memory class, read-only memory (ROM), is
similar to RAM in that a computer addresses it and
then retrieves data stored at that address. However,
ROM includes no mechanism for altering the data
. stored at that address-hence, the term read only.
First examine read/write memory, which permits the
access of stored memory (reading) and the ability to
alter the stored data (writing).
Before the advent of solid-state read/write memory,
active data (data being processed) was stored and
retrieved from nonvolatile core memory (a magneticstorage technology). Solid-state RAMs solved the
size and power consumption problems associated
with core, but added the element of volatility. Because RAMS lose their memory when you turn off
their power, you must leave systems on all the time,
add battery backup or store important data on a
nonvolatile medium before the power goes down.
ROM is basically used for storing information that
isn't subject to change-at least not frequently. Unlike RAM, when system power goes down, ROM retains its contents.
ROM devices became very popular with the advent
of microprocessors. Most early microprocessor applications were dedicated systems; the system's
program was fixed and stored in ROM. Manipulated
data could vary and was therefore stored in RAM.
This application split caused ROM to be commonly
called program storage, and RAM, data storage.
Despite their volatility, RAMs have become very
popular, and an industry was born that primarily fed
1-1
inter
MEMORY OVERVIEW
The first ROMs contained cell arrays in which the
sequence of ones and zeros was established by a
metallization interconnect mask step during fabrication. Thus, users had to supply a ROM vendor with
an interconnect program so the vendor could complete the mask and build the ROMs. Set-up charges
were quite high-in fact, even prohibitive unless users planned for large volumes cif the same ROM.
EPROM or DRAM in bit capacity per square millimeter of silicon and the resulting lack of cost-effectiveness and density has caused it to lag behind other
memory technologies.
The latest advance·ment is Flash memory. Flash
memories combine the electrical erase capability of
the EEPROM with the simplicity, density and cost-effectiveness of EPROM cell layout. Modification to
the EPROM cell replaces block UV-erasure with
block electrical erasure, which can be accomplished
while the device is still installed in the host system.
Flash memory. can also be randomly read or written
by the local system microprocessor or microcontroller.
To offset this high set-up charge, manufacturers developed a user-programmable ROM (or PROM). The
first such devices used· fusible links that could be
melted or programmed with a special hardware system.
Once programmed, a PROM was just like a ROM. If
the program was faulty, the chip had to be discarded. But, PROMs furnished a more cost-effective way
to develop program memory or firmware for low-volume purposes than did ROMs.
The cost effectiveness and flexibility of Flash memory makes it applicable in code storage applications.
Code can be quickly and easily updated during prototyping, incoming test, assembly qr in the field,
quickly and easily. High density and nonvolatile
read/write capability also make Flash memory an
innovative alternative for mass storage, and integrating main memory and backup storage functions into
directly executable Flash memory boosts system
performance, shrinks system size, reduces power
requirements and increases reliability over that of
electromechanical media, especially in extreme environmental conditions.
As one alternative· to fusable-link programming, Intel
pioneered an erasable MOS-technology PROM
(termed an EPROM) that used charge-storage programming. It came in a standard ceramic DIP package but had a window that permitted die exposure to
light. When the chip was exposed to ultraviolet light,
high energy photons could collide with the EPROM's
electrons and scatter them at random, thus erasing
the memory.
The EPROM was not intended for use in read/write
applications, but it proved very useful in research
and development for prototypes, where the need to
alter the program several times is quite common.
Indeed, the EPROM market originally consisted almost exclusively of development labs. As the fabrication process became mature, and volumes increased, EPROM's lower prices made them attractive even for medium-volume production-system applications. Today, millions of EPROMs are used in
systems which require only periodic, off-line updates
of information and parameters.
APPLICATIONS OF MEMORY
DEVICES
Besides the particular characteristics of each device
that has been discussed, there are a number of other factors to consider when choosing a memory
product, such as cost, power consumption, performance, memory architecture and organization, and
size of the memory. Each of these factors plays an
important role in the final selection process.
Performance
Nonvolatile Read/Write Memory
Technology advances have blurred the traditional
lines drawn between read-only memories (ROMs)
and read/write memories (RAMs). The first alternative was the EPROM, which required removal from
the host system, placing it under ultraviolet light for
erasure, and subsequent reprogramming and reinstallation into the host system.
The next advancement was the introduction of a
nonvolatile memory that was electrically erasable
and user rewritable on a byte-by-byte basis, called
the EEPROM. The byte erase capability and highlevel of feature integration of the EEPROM came
with two penalties-density and cost. Cell and periphery complexity places EEPROM far behind
Generally, the term performance relates to how fast
the device can operate in a given system environment. This parameter is usually rated in terms of the
access time. Fast SRAMs can provide access times
as fast as 20 ns, while the fastest DRAM cannot go
much beyond the 100 ns mark. A bipolar PROM has
an access time of 35 ns. RAM and PROM access is
usually controlled by a ~nal most often referred to
as Chip Select (CS). CS often appears in device
specifications. In discussing access times, it is important to remember that in SRAMs and PROMs,
. the access time equals the cycle time of the system
whereas in DRAMs, the access time is always less
than the cycle time.
1-2
MEMORY OVERVIEW
Power consumption also depends upon the organization of the device in the system. Organization' usually refers to the width of the memory word. At the
time of their inception, memory devices were organized as nK x 1 bits. Today, they are available in
various configurations such as 4K x 1, 16K x 1, 64K
x 1, 1K x 4, 2K x 8, etc. As the device width increases, fewer devices are required to configure a given
memory word-although the total number of bits remains constant. The wider organization can provide
significant savings in power consumption, because a
fewer number of devices are required to be powered
up for access to a given memory word. In addition,
the board layout design is simpler due to fewer
traces and better layout advantages. The wider
width is of particular advantage in microprocessors
and bit-slice processors because most microprocessors are organized in 8-bit or 16-bit architectures. A
memory chip configured in the nK x 8 organization
can confer a definite advantage-especially in universal site applications. Conversely, there is usually
a small speed penalty, at the device level for a x8 or
x16 organization.
Cost
There are many ramifications to consider when evaluating cost. Often the cost of the physical device
used is the smallest portion of the total cost of using
a particular device. Total cost must comprehend
other factors such as design-in time, test expense,
update costs, as well as cost per bit, size of memory
power consumption, etc.
Cost of design time is proportional to design complexity. For example, SRAMs generally require less
design-in time than DRAMs because there is no refresh circuitry to consider. Conversely, the DRAM
provides the lowest cost per bit because of its higher
packing density. The cost of a service call to exchange or reprogram a ROM/PROM/EPROM versus an in-system update of a Flash memory costs
orders of magnitude more than the device itself.
Memory Size
Memory size is generally specified in the number of
bytes (a byte is a group of eight bits). The memory
size of a system is usually segmented depending
upon the general equipment category. Computer
mainframes and most of today's minicomputers use
blocks of read/write substantially beyond 64K
bytes-usually in the hundreds of thousands to millions of bytes.
Types of Memories
The first step to narrowing down your choice is to
determine the type of memory you are designingdata store or program store. After this has been
done, the next step is to prioritize the following factors:
The microprocessor user generally requires memory
sizes ranging from 2K bytes up to 64K bytes. In
memories of this size, the universal site concept allows maximum flexibility in memory design.
Performance
Power Consumption
Density
Cost
Power Consumption
SUMMARY
Power consumption is important because the total
power required for a system directly affects overall
cost. Higher power consumption requires bigger
power supplies, more cooling, and reduced device
density per board-all affecting cost and reliability.
All things considered, the usual goal is to minimize
power. Many memories now provide automatic power-down. With today's emphasis on saving energy
and reducing cost, the memories that provide these
features will gain an increasingly larger share of the
market.
Global Memory
Generally, a global memory is greater than 64K
bytes and serves as a main memory for a microprocessor system. Here, the use of dynamic RAMs or
Flash memory for read/write memory is dictated to
provide the highest density and lowest cost per bit.
The cost of providing refresh circuitry for the dynamic RAMs is spread over a large number of memory
bits, thus minimizing the cost impact.
In some applications, extremely low power consumption is required, such as battery operation. For
these applications, the use of devices made by the
CMOS technology have a distinct advantage over
the NMOS products. CMOS devices offer power
savings of several magnitudes over NMOS. Non-volatile devices such as EPROMs or Flash memories
are usually independent of power problems in these
applications.
Local Memory
Local memories are usually less than 64K bytes and
reside in the proximity of the processor itself-usuallyon the same PC board. Types of memories often
used in local memory applications are SRAM,
EPROM, Flash memory, and EEPROM.
1-3
Memory Technologies
2
INTEL MEMORY TECHNOLOGIES
Most of this handbook is devoted to techniques and
information to help you design and implement semiconductor memory in your application or system. In
this section, however, the memory chip itself will be
examined and the processing technology required to
turn a bare slice of silicon into high performance
memory devices is described. The discussion has
been limited to the basics of MOS (Metal Oxide
Semiconductor) technologies as they are responsible for the majority of memory devices manufactured
at Intel.
same silicon. Either p- or n-type silicon substrates
can be used, however, deep areas of the opposite
doping type (called wells) must be defined to allow
fabrication of the complementary transistor type.
Most of the early semiconductor memory devices,
like Intel's pioneering 1103 dynamic RAM and 1702
EPROM were made with PMOS technologies. As
higher speeds and greater densities were needed,
most new devices were implemented with NMOS.
This was due to the inherently higher speed of
n-channel charge carriers (electrons) in silicon along
with improved process margins. CMOS technology
has begun to see widespread commercial use in
memory devices. It allows for very low power devices used for battery operated or battery back-up applications. Historically, CMOS has been slower than
any NMOS device. However, CMOS technology has
been improved to produce higher speed devices.
The extra cost of processing required to make both
transistor types had kept CMOS memories limited to
those areas where the technology's special characteristics would justify the extra cost. In the future, the
learning curve for high performance CMOS costs
are making a larger number of memory devices
practical in CMOS.
There are three major MOS technology familiesPMOS, NMOS, and CMOS (Figure 1). They refer to
the channel type of the MOS transistors made with
the technology. PMOS technologies implement
p-channel transistors by diffusing p-type dopants
(usually boron) into an n-type silicon substrate to
form the source and drain. P-channel is so named
because the channel is comprised of positively
charged carriers. NMOS technologies are similar,
but use n-type dopants (normally phosphorus or arsenic) to make n-channel transistors in p-type silicon
substrates. N-channel is so named because the
channel is comprised of negatively charged carriers.
CMOS or Complementary MOS technologies combine both p-channel and n-channel devices on the
GATE
GATE
296102-2
296102-1
PMOS
NMOS
P-CHANNEL
DEVICE
N-CHANNEL
DEVICE
GATE
F.O.
P-SUBSTRATE
296102-3
CMOS
Figure 1. MOS Process Cross-sections
2-1
inter
INTEL MEMORY TECHNOLOGIES
In the following section, the basic fabrication sequence for an HMOS circuit will be described.
HMOS is a high performance n-channel MOS process developed by Intel for 5V single supply circuits.
HMOS, and CHMOS, CHMOS-E (EPROM) and
ETOXTM (Flash Memory), along with their evolutionary counterparts comprise the process family responsible for most of the memory components produced by Intel today.
Having fulfilled its purpose, the remaining silicon nitride layer is removed. A light oxide etch follows taking with it the underlying first oxide but leaving the
thick (field) oxide.
'
Now that the areas for active transistors have been
defined and isolated, the transistor types needed
can be determined. The wafer is again patterned
and then if special characteristics (such as depletion
mode operation) are required, it is implanted with
dopant atoms. The energy and dose at which the
dopant atoms are implanted determines much of the
transistor's characteristics. The type of the dopant
provides for depletion mode (n-type) or enhancement mode (p-type) operation.
The MOS IC fabrication process begins with a slice
(or wafer) of siJlgle crystal silicon. Typically, it's 100
or 150 millimeter in diameter, about a half millimeter
thick, and uniformly doped p-type. The wafer is then
oxidized in a furnace at around 1000°C to grow a
thin layer of silicon dioxide (Si02) on the surface.
Silicon nitride is then deposited on the oxidized wafer in a gas phase chemical reactor. The wafer is
now ready to receive the first pattern of what is to
become a many layered complex circuit. The pattern
is etched into the silicon nitride using a process
known as photolithography, which will be described
in a later section. This first pattern (Figure 2) defines
the boundaries of the active regions of the IC, where
transistors, capacitors, diffused resistors, and first
level interconnects will be made. .
ETCHED
AREAS
!
The transistor types defined, the gate oxide of the
active transistors are grown in a high temperature
furnace. Special care must be taken to prevent contamination or inclusion of defects in the oxide and to
ensure uniform consistent thickness. This is important to provide precise, reliable device characteristics. The gate oxide layer is then masked and holes
are etched to provide for direct gate to diffusion
("buried") contacts where needed.
The wafers are now deposited with a layer of gate
material. This is typically poly' crystaline silicon
("poly") which is deposited in a gas phase chemical
reactor similar to that used for silicon nitride. The
poly is then doped (usually with phosphorus) to bring
the sheet resistance down to 10-20 fi/square. This
layer is also used for circuit interconnects and if a
lower resistance is required, a refractory metal/polysilicon composite or refractory metal silicide can be
used instead. The gate layer is then patterned to
define the actual transistor gates and interconnect
paths (Figure 4).
~\
NITRIDE---....
OXIDE-'"
)
P-SUBSTRATE
296102-4
Figure 2. First Mask
The patterned and etched wafer is then implanted
with additional boron atoms accelerated at high energy. The boron will only reach the silicon substrate
where the nitride and oxide was etched away, providing areas doped strongly p-type that will electrically separate active areas. After implanting, the wafers are oxidized again and this time a thick oxide is
grown. The. oxide only grows in the etched areas
due to silicon nitride's properties as an oxidation barrier. When the oxide is grown, some of the silicon
substrate is consumed and this gives a physical as
well as electrical isolation for adjacent devices as
can be seen in Figure 3.
NITRIDE
P+
POLYSILICON
P-SUBSTRATE
296102-6
Figure 4. Post Gate Mask
The wafer is next diffused with n-type dopant .(typically arsenic or phosphorus) to form the source and
drain junctions. The transistor gate material acts as
a barrier to the dopant providing an undiffused channel self-aligned to the two junctions. The wafer is
then oxidized to seal the junctions from contamination with a layer of Si02 (Figure 5).
FIELD OX
P-SUBSTRATE
P+
P+
296102-5
Figure 3. Post Field Oxidation
2-2
inter
INTEL MEMORY TECHNOLOGIES
+ Vo
SECOND-LEVEL
POLYSILICON
FIELD
OXIDE
296102-7
Figure 5. Post Oxidation
P-SUBSTRATE
A thick layer glass is then deposited over the wafer
to provide for insulation and sufficiently low capacitance between the underlying layers and the metal
interconnect signals. (The lower the capacitance,
the higher the inherent speed of the device.) The
glass layer is then patterned with contact holes and
placed in a high temperature furnace. This furnace
step smooths the glass surface and rounds the contact edges to provide uniform metal coverage. Metal
(usually aluminum or aluminum/silicon) is then deposited on the wafer and the interconnect patterns
and external bonding pads are defined and etched
(Figure 6). The wafers then receive a low temperature (approximately 500°C) alloy that insures good
ohmic contact between the aluminum and diffusion
.
or poly.
EPROM/FLASH MEMORY CELL
296102-9
Figure 7. Double Poly Structure
After fabrication is complete, the wafers are sent for
testing. Each circuit is tested individually under conditions designed to determine which circuits will operate properly both at low temperature and at conditions found in actual operation. Circuits that fail
these tests are inked to distinguish them from good
circuits. From here the wafers are sent from assembly where they are sawed into individual circuits with
a paper-thin diamond blade. The inked circuits are
then separated out and the good circuits are sent on
for packaging.
Packages fall into two categories-hermetic and
non-hermetic. Hermetic packages are Cerdip, where
two ceramic halves are sealed with a glass fritt, or
ceramic with soldered metal lids. An example of hermetic package assembly is shown in Table 1. Nonhermetic packages are molded plastics.
The ceramic package has two parts, the base, which
has the leads and die (or circuit) cavity, and the metal lid. The base is placed on a heater block and a
metal alloy preform is inserted. The die is placed on
top of the preform which bonds it to the package.
Once attached, wires are bonded to the circuit and
then connected to the leads. Finally the package is
placed in a dry inert atmosphere and the lid is soldered on.
296102-8
Figure 6. Complete Circuit (without paSSivation)
At this point the circuit is fully operational, however,
the top metal layer is very soft and easily damaged
by handling. The device is also susceptible to contamination or attack from moisture. To prevent this
the wafers are sealed with a passivation layer of silicon nitride or a silicon and phosphorus oxide composite. Patterning is done for the last time opening
up windows only over the bond pads where external
connections will be made.
The cerdip package consists of a base, lead frame,
and lid. The base is placed on a heater block and
the lead frame placed on top. This sets the lead
frame in glass attached to the base. The die is then
attached and bonded to the leads. Finally the lid is
placed on the package and it is inserted in a seal
furnace where the glass on the two halves melt together making a hermetic package.
This completes basic fabrication sequence for a single poly layer process. Double poly processes such
as those used for high density Dynamic RAMs,
EPROMs, flash memories, and EEPROMs follow the
same general process flow with the addition of gate,
poly deposition, doping, and interlayer dielectric process modules required for the additional poly layer
(Figure 7). These steps are performed right after the
active areas have been defined (Figure 3) providing
the capacitor or floating gate storage nodes on
those devices.
.
In a plastic package, the key component is the lead
frame. The die is attached to a pad on the lead
frame and bonded out to the leads with gold wires.
The frame then goes to an injection molding machine and the package is formed around the lead
frame. After mold the excess plastic is removed and
the leads trimmed.
2-3
INTEL MEMORY TECHNOLOGIES
After assembly, the individual circuits are retested at
an elevated operating temperature to assure critical
operating parameters and separated according to
speed and power consumption into individual specification groups. The finished circuits are marked and
then readied for shipment.
PHOTOLITHOGRAPHY
The photo or masking technology is the most important part of the manufacturing flow if for no other
reason than the number of times it is applied to each
wafer. The manufacturing process gets more complex in order to make smaller and higher performance circuits. As this happens the number of masking steps increases, the features get smaller, and
the tolerance required becomes tighter. This is
largely because the minimum size of individual pattern elements determine the size of the whole circuit, effecting its cost and limiting its potential complexity. Early MOS IC's used minimum geometries
(lines or spaces) of 8-1'0 microns (1 micron = 1'0- 6
meter "" 1/25,'0'0'0 inch). The n-channel processes
of the mid 197'O's brought this down to approximately 5 microns, and today minimum geometries of one
micron are in production. This dramatic reduction
The basic process flow described above may make
VLSI device fabrication sound straightforward, however, there are actually hundreds of individual operations that must be performed correctly to complete a
working circuit. It usually takes well over two months
to complete all these operations and the many tests
and measurements 'involved throughout the manufacturing process. Many of these details are responsible for ensuring the performance, quality, and'reliability you expect from Intel products. The following
sections will discuss the technology underlying each
of the major process elements mentioned in the basic process flow.
Table 1. Typical Hermetic Package Assembly
Flow
ProcessiMaterlals
Typical Item
Frequency
Criteria
Waler
Die saw, wafer break
Die wash and plate
Die visual inspection
~
Passivation, metal
OAgate
Die attach
(Process monitor)
0f76, LTPD=5%
Wet out
4 x/operator/shift
0111 LTPD=20%
Orientation, lead
dressing, etc.
4 x/operator/
machine/shift
All previous items
Cap align, glass
integrity. moisture
every lot
11129, LTPD=3%
4 x /furnace/shift
0115, LTPD= 15%
Post die attach visual
Wire bond
(Process monitor)
100% 01 devices
Post bond inspection
f-o
OAgate
Seal and Mark
(Process monilor)
100% devices
Temp cycle
I," ~
2,4-
100% oldie
Every lot
lOx to mil std.
,883cond. C
Hermeticity check
(Process monitor)
F/G leak
100% devices
Lead Trim
(Process monitor)
Burrs, etc, (visual)
Fine leak
4 x/station/shift
2 x/station/shift
External visual
Solder voids, cap
alignment, etc.
100% devices
OAgate
All previous items
All lots
Class test
(Process monitor)
Run standards
(good and reject)
Calibrate every
system using
"autover" program
Every 48 hrs.
1111, LTPD = 20%
0115, LTPD= 15%
11129, LTPD=3%
11129, LTPD. 3%
Mark and Pack
FinalQA
(See attached)
296102-11
NOTES:
1. Units for assembly reliability monitor.
2. Units for product reliability monitor.
2-4
inter
INTEL MEMORY TECHNOLOGIES
in feature size was achieved using the newer high
resolution photo resists and optimizing their processing to match improved optical printing systems.
DIFFUSION
The picture of clean room garbed operators tending
furnace tubes glowing cherry red is the one most
often associated with IC fabrication. These furnace
operations are referred to collectively as diffusion
because they employ the principle of sold state diffusion of matter to accomplish their results. In MOS
processing, there are three main types of diffusion
operations: predeps, drives, and oxidations.
A second major factor in determining the size of the
circuit is the registration or overlay error. This is how
accurately one pattern can be aligned to a previous
one. Design rules require that space be left in all
directions according to the overlay error so that unrelated patterns do not overlap or interfere with one
another. As the error space increases the circuit size
increases dramatically. Only a few years ago standard alignment tolerances were :<: ± 2 microns; now
advanced Intel processes have reduced this dramatically due mostly to the use of advanced projection
and step and repeat exposure equipment.
Predeposition, or "predep," is an operation where a
dopant is introduced into the furnace from a solid,
liquid, or gaseous source and at the furnace temperature (usually 900·C-1200·C) a saturated solution is
formed at the silicon surface. The temperature of the
furnace, the dopant atom, and rate of introduction
are all engineered to give a specific dose of the dopant on the wafer. Once this is completed the wafer is
given a drive cycle where the dopant left at the surface by the predep is driven into the wafer by high
temperatures. These are generally at different temperatures than the predeps and are designed to give
the required junction depth and concentration profile.
The wafer that is ready for patterning must go
through many individual steps before that pattern is
complete. First the wafer is baked to remove moisture from its surface and is then treated with chemicals that ensure good resist adhesion. The thick
photoresist liquid is then applied and the wafer is
spun flat to give a uniform coating, critical for high
resolution. The wafer is baked at a low temperature'
to solidify the resist into gel. It is then exposed with a
machine that aligns a mask with the new pattern on
it to a previously defined layer. The photo-resist will
replicate this pattern on the wafer.
Oxidation, the third category, is used at many steps
of the process as was shown in the process flow.
The temperature and oxidizing ambient can range
from 800·C to 1200·C and from pure oxygen to mixtures of oxygen and other gases to steam depending
on the type of oxide required. Gate oxides require
high dielectric breakdown strength for thin layers
(between 0.01 and 0.1 micron) and very tight control
over thickness (typically ± 0.005 micron or less than
± 1/5,000,000 inch), while isolation oxides need to
be quite thick and because of this their dielectric
breakdown strength per unit thickness is much less
important.
Negative working resists are polymerized by the light
and the unexposed resist can be rinsed off with solvents. Positive working resists use photosensitive
polymerization inhibitors that allow a chemically reactive developer to remove the exposed areas. The
positive resists require much tighter control of exposure and development but yield higher resolution
patterns than negative resistance systems.
The wafer is now ready to have its pattern etched.
The etch procedure is specialized for each layer to
be etched. Wet chemical etchants such as hydrofluoric acid for silicon oxide or phosphoric acid for
aluminum are often used for this. The need for
smaller features and tighter control of etched dimensions is increasing the use of plaslT)a etching in fabrication. Here a reactor is run with a partial vacuum
into which etchant gases are introduced and an
electrical field is applied. This yields a reactive plasma which etches the required layer.
The properties of the diffused junctions and oxides
are key to the performance and reliability of the finished device so the diffusion operations must be extremely well controlled for accuracy, consistency
and purity.
ION IMPLANT
Intel's high performance products require such high
accuracy and repeatability of dopant control that
even the high degree of control provided by diffusion
operations is inadequate. However, this limitation
has been overcome by replacing critical predeps
with ion implantation. In ion implantation, ionized
dopant atoms are accelerated by an electric field
The wafer is now ready for the next process step. Its
single journey through the masking process required
the careful engineering of mechanics, optics, organic chemistry, inorganic chemistry, plasma chemistry,
physics, and electronics.
2-5
inter
INTEL MEMORY TECHNOLOGIES
and implanted directly into the wafer. The acceleration potential determines the depth to which the
dopant is implanted.
The fabrication of modern memory devices is a long,
complex process where each step must be monitored, measured and verified. Developing a totally
new manufacturing process for each new product or
even product line takes a long time and involves significant risk. Because of this, Intel has developed
process families, such as HMOS, on which a wide
variety of devices can be made. These families are
scalable so that circuits need not be totally redesigned to meet your needs for higher
performance.(1) They are evolutionary so that development time of new processes and products can be
reduced without compromising Intel's commitment
to consistency, quality, and reliability.
The charged ions can be counted electrically during
implantation giving very tight control over dose. The
ion implanters used to perform this are a combination of high vacuum system, ion source, mass spectrometer, linear accelerator, ultra high resolution current integrator, and ion beam scanner. You can see
that this important technique requires a host of sophisticated technologies to support it.
THIN FILMS
The manufacture of today's MOS memory devices
requires a tremendous variety of technologies and
manufacturing techniques, many more than could be
mentioned here. Each requires a team of experts to
design, optimize, control and maintain it. All these
people and thousands of others involved in engineering, design, testing and production stand behind
Intel's products.
Thin film depositions make up most of the features
on the completed circuit. They include the silicon nitride for defining isolation, polysilicon for the gate
and interconnections, the glass for interlayer dielectric, metal for interconnection and external connections, and passivation layers. Thin film depositions
are done by two main methods: physical deposition
and chemical vapor deposition. Physical deposition
is most common for deposition metal. Physical depositions are performed in a vacuum and are accomplished by vaporizing the metal with a high energy
electron beam and redepositing it on the wafer or by
sputtering it from a target to the wafer under an electric field.
Because of these extensive requirements, most
manufacturers have not been able to realize their
needs for custom circuits on high performance, high
reliability processes. To address this Intel's expertise in this area is now available to industry through
the silicon foundry. Intel supplies design rules and
support to design and debug circuits. This includes
access to Intel's n-well CHMOS technology. Users
of the foundry can now benefit from advanced technology without developing processes and IC manufacturing capability themselves.
Chemical vapor deposition can be done at atmospheric pressure or under a moderate vacuum. This
type of deposition is performed when chemical gases react at the wafer surface and deposit a solid film
of the reaction product. These reactors, unlike their
general industrial counterparts, must be controlled
on a microscale to provide exact chemical and physical properties for thin films such as silicon dioxide,
silicon nitride, and polysilicon.
(1)R. Pashley, K. Kokkonen, E. Boleky. R. Jecmen, S. Liu,
and W. Owen, "H-MOS Scales Traditional Devices to Higher Performance Level," Electronics, August 18, 1977.
2-6
Dynamic RAMs
(Random Access Memories)
3
21256
262,144 x 1-BIT DYNAMIC RAM WITH PAGE MODE
Symbol
•
•
•
•
Parameter
21256-06
21256-07
21256-08
21256-10
Units
tRAG
Access Time from RAS
60
70
80
100
ns
tGAC
Access Time from CAS
20
20
20
50
ns
tRG
Read Cycle Time
110
130
150
190
ns
•
•
•
•
Page Mode Capability
CAS-before-RAS Refresh Capability
RAS-Only and Hidden Refresh
Capability
TTL Compatible Inputs and Output
Common 1/0 Using Early Write
Single + 5V ± 10% Power Supply
256 Cycle/4 ms Refresh
JEDEC Standard Pinout in DIP, ZIP and
PLCC
The 21256 is a fully decoded dynamic random access memory organized as 262,144 one-bit words. The
design is optimized for high speed, high performance applications such as computer memory, buffer memory,
peripheral storage and environments where low power dissipation and compact layout are required.
The 21256 features page mode which allows high speed random access of memory cells within the same row.
CAS-before-RAS refresh capability provides on-chip auto refresh as an alternative to RAS-only refresh. Multiplexed row and column address inputs permit the 21256 to be housed in a JEDEC standard 16-pin DIP.
Clock timing requirements are noncritical, and power supply tolerance i!! very wide. All inputs and output are
TTL compatible.
RAS _1""""----,
CONTROL & t::===~----i:l
CLOCKS IVi -r."'T""---,~
CAS
o
Q
AO
Al
A2
A3
A4
AS
A6
IX
'"co
~
c
:=o
MEMORY ARRAY
262,144
CELLS
~vcc
IX
A7
A8
~vss
240021-1
Figure 1_ Functional Block Diagram
3-1
September 1990
Order Number: 240021-004
intJ
21256
DIP
AS
0
VSS
CAS
W
Q
RAS
A6
AO
A3
A2
A4
Al
AS
Vee
A7
240021-2
·PLCC
0
AS VssCAS
~~! L~.! ~1~
•
W ~]
NC
{]
[]
AO
~J
A2
fl
RAS
!1.?!
(TOP VIEW)
[1]
[(§
Q
~~
[1]
[1}
NC
A6
A3
A4
~8~ r9~ ~C; ~1-1~
Al Vee A7 AS
240021-3
ZIP
OM'~
Q
Vss
0
RAS
A2
vee
AS
A3'-16
240021-4
(Bottom View)
Pin Names
Ao-As
o
Q
W
RAS
CAS
Vee
Vss
Address Input
Data In
Data Out
Read/Write Input
Row Address Strobe
Column Address Strobe
Power (+5V)
Ground
3-2
intJ
21256
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Voltage on Any Pin
Relative to vss .......... VOUT -1.0V to + 7.0V
'WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage on Vcc Supply
Relative to Vss ............... -1.0V to + 7.0V
Storage Temperature .......... - 55D C to + 125D C
Power Dissipation .......................... 1.0W
Short Circuit Output Current ................ 50 mA
RECOMMENDED OPERATING CONDITIONS
Symbol
Voltages referenced to Vss, TA
=
0 to 70D C
Parameter
Min
Typ
Max
Vcc
Supply Voltage
4.5
5.0
5.5
V
Vss
Ground
0
0
0
V
VIH
Input High Voltage
2.4
Vcc+ 1
V
VIL
Input Low Voltage
-1
0.8
V
Units
D.C. AND OPERATING CHARACTERISTicS
Recommended operating conditions unless otherwise noted.
Symbol
Parameter
Min Max Units
Test Condition
ICCl
Operating Current'
21256-06
21256-07
21256-08
21256-10
75
70
60
55
mA
mA
lilA
mA
(RASand CAS
cycling @ tRC = min.)
ICC2
Standby Current
21256-06
21256-07
21256-08
21256-10
2.0
2.0
2.0
5.0
mA
mA
mA
mA
(RAS = CAS = VIH)
ICC3
RAS-Only Refresh Current'
21256-06
21256-07
21256-08
21256-10
75
70
60
40
mA
mA
mA
mA
(CAS = VIH, RAS
cycling @ tRC = min.)
ICC4
Page Mode Current'
21256-06
21256-07
21256-08
21256-10
50
45
40
35
mA
mA
mA
mA
(RAS = VIL, CAS cycling;
tpc = min.)
ICC5
CAS-before-RAS Refresh Current' 21256-06
21256-07
21256-08
21256-10
75
65
55
55
mA
mA
mA
mA
(RAS cycling
Iccs
Standby Current
1.0
mA
(RAS = CAS = Vcc - 0.2V)
IlL
Input Leakage Current
-10
10
p.A
(Any input 0 :5: VIN :5: 5.5V,
Vcc = 5.5V, Vss = OV, All other
pins not under test = 0.)
IOL
Output Leakage Current
-10
10
p.A
(Data out is disabled,
OV :5: VOUT :5: 5.5V,
Vcc = 5.5V, Vss = OV)
@
tRC = min.)
'NOTE:
and ICC5 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is
specified as average current.
ICCt, ICC3, ICC4
3-3
intJ
21256
D.C. AND OPERATING CHARACTERISTICS
Recommended operating conditions unless otherwise noted. (Continued)
Symbol
Parameter
Min
VOH
Output High Voltage Level
Val
Output 'Low Voltage Level
CAPACITANCE
I
I
Max
Units
2.4
0.4
V
(IOH
V
(IOl
= 5 mA)
= 4.2 mA)
TA = 25D C
Symbol
Parameter
Min
Input Capacitance (Ao-As, D)
CIN1
Test Condition
Max
Units
5
pF
CIN2
Input Capacitance (RAS, CAS, W)
8
pF
COUT
Output Capacitance (0)
7
pF
A.C. CHARACTERISTICS
Symbol
(ODC ::;; TA ::;; 70DC, VCC = 5.0V ± 10%. See Notes 1, 2)
Parameter
21256-06
Min
21256-07
Max
Min
Max
21256-08
Min
Max
21256-10
Min
Units Notes
Max
tRC
Random Read or
Write Cycle Time
120
135
150
190
ns
tRWC
Read-Modify-Write Cycle Time 135
155
175
220
ns
tRAC
Access Time from RAS,
60
70
80
100'
ns
3,4,11
tCAC
Access Time from CAS
15
25
30
50
ns
3,4,5
tAA
Column Address Access Time
tClZ
CAS to Output in Low-Z
5
35
35
5
40
5
50
5
ns
3,10
ns
3
tOFF
Output Buffer Turn-Off Delay
0
25
0
25
0
25
0
30
ns
7
tT
Transition Time (Rise and Fall)
3
50
3
50
3
50
3
100
ns
2
tRP
RAS Precharge Time
55
tRAS
RAS Pulse Width
60
65
10,000
70
10,000
75
80
ns
80
10,000 100 10,000
ns
tRSH
RAS Hold Time
15
25
30
50
ns
tCPN
CAS Precharge Time
(All Cycles except Page Mode)
10
10
15
25
ns
tCAS
CAS·Pulse Width
15
tCSH
CAS Hold Time
60
tRCD
RAS to CAS Delay Time
15
50
25
50
25
. 60
25
75
ns
4
tRAD
RAS to Column Address
Delay Time
15
25
20
35
20
40
20
55
ns
11
tCRP
CAS to RAS Precharge Time
(RAS Only Refresh)
5
15
15
15
ns
tASR
Row Address Setup Time
0
0
0
0
ns
10,000
25
10,000
70
3-4
30
10,000
80
50
10,000
100
ns
ns
--
""
21256
A.C. CHARACTERISTICS (o·c
Symbol
:S: T A :S: 70·C, VCC
Parameter
21256-06
=
5.0V ± 10%. See Notes 1, 2) (Continued)
21256-07
Min
Max Min
Max
21256-08
21256-10
Min
Max Min
Units Notes
Max
tAAH
Row Address Hold Time
15
15
15
15
ns
tASC
Column Address Setup Time
0
0
0
0
ns
tCAH
Column Address Hold Time
10
15
20
20
ns
tAA
Column Address Hold Time
Referenced to RAS
50
55
65
75
ns
tAAL
Column Address to RAS
Lead Time
30
35
40
50
ns
tACS
Read Command Setup Time
0
0
0
0
ns
tACH
Read Command Hold Time
Referenced to CAS
5
5
5
5
ns
9
tAAH
Read Command Hold Time
Referenced to RAS
5
5
5
5
ns
9
twcs
Write Command Setup Time
0
0
0
0
ns
8
tWCH
Write Command Hold Time
15
15
15
35
ns
twp
Write Command Pulse Width
10
15
15
35
ns
tAWL
Write Command to RAS Lead Time
15
25
30
35
ns
tcWL
Write Command to CAS Lead Time
15
25
30
35
ns
tDS
Data-In Setup Time
0
0
0
0
ns
10
10
6
tDH
Data-In Hold Time
10
15
15
35
ns
tCWD
CAS to Write Enable Delay
15
20
25
40
' ns
8
tAWD
RAS to Write Enable Delay
60
70
80
100
ns
8
tAWD
Column Address to W Delay Time
35
35
.40
50
ns
8
tWCA
Write Command Hold Time
Referenced to RAS
40
55
60
85
ns
6
tDHA
Data-In Hold Time
Reference9 to RAS
50
55
60
85
ns
6
tAEF
Refresh Period (256 Cycles)
4
4
4
4
ms
CAS-BEFORE-RAS REFRESH
tCSA
CAS Setup Time
(CAS-before-RAS Refresh)
10
10
10
15
ns
tCHA
CAS Hold Time
(CAS-before-RAS Refresh)
10
20
25
30
ns
tcPT
Refresh Counter Test
CAS Precharge Time
15
35
50
60
ns
tAPC
RAS Precharge to CAS Active Time
10
10
10
10
ns
PAGE MODE
tpc
Page Mode Cycle Time
40
50
55
90
ns
tcp
CAS Precharge Time
(Page Mode Only)
10
15
15
30
ns
3-5
intJ
21256
A.C. CHARACTERISTICS
Symbol
(O·C ::;; T A ::;; 70·C, Vee = 5.0V ± 10%. See Notes 1, 2) (Continued)
Parameter
21256-06
Min
Max
21256-07
Min
Max
21256-08
Min
Max
21256-10
Min
Units Notes
Max
PAGE MODE (Continued)
45
ns
ePA
Access Time from CAS Precharge
PRwe
Fast Page Mode
Read-Modify-Write
65
RASP
RAS Pulse Width (Fast Page Mode)
60 10,000 70 10,000 80 10,000 100 10,000 ns
40
75
50
85
55
95
3
ns
NOTES:
1. An initial pause of 200 JLs is required after power-up followed by any S RAS cycles before proper device operation is
achieved.
2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5 ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100 pF.
4. Operation within the T RCD(max) limit ensures that T RAc(max) can be met, tRCD(max) is specified as a reference point
only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tcAC.
5. Assumes that tRCD ;;" tRCD(max).
• 6. tAR, tWCR, tDHR are referenced to tRAD(max)'
'
7. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or
VOL·
'
·S. twcs, tRWD, lewD and tAWD are non-restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If twcs ;;" tWCS(min) the cycle i,s an early write cycle and the data out pin will remain high impedance for
the duration of the cycle. If tCWD ;;" tcWD(min), tRWD ;;" tRWD(min) and tAWD ;;" tAWD(min), then the cycle is a read-write cycle
and the data out will contain the data read from the selected address. If ,neither of the above conditions are satisfied, the
condition of the data out is indeterminate.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write
cycles.
"
,
11. Operation within the tRAD!max) limit insures thattRAC(max) can be met. tRAD(max) is specified as a reference pOint only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tM'
TIMING DIAGRAMS
READ CYCLE
~---------------------tRC--------------------~
HAS
CAS
vlII VIL -
V1H V1L -
Q VOH -
VOL -
----------
240021-5
~Don·tCare
240021-6
3-6
inter
21256
TIMING DIAGRAMS (Continued)
WRITE CYCLE (EARLY WRITE)
t Rc
t RAS
RAS
V1H V1L -
CAS
V1H V1L -
A
V1H V1L -
tAR
I RSH
tCAS
240021-7
READ-WRITE/READ-MODIFY-WRITE CYCLE
t RWC
t RAS
RAS
V1H -
tAR
V1L t RSH
CAS
V1H V1L -
A
V1H V1L -
Vi
V1H V1L -
tCAS
240021-8
~Don·tcare
240021-6
3-7
inter
21256
TIMING DIAGRAMS (Continued)
PAGE MODE READ CYCLE
~------------------------tRASP--------------------~----~
o VOH - ------+.:....-{K
VOL -
Vi
V1H -
.............x.......,......OJ
V1L -
240021-9
PAGE MODE WRITE CYCLE (EARLY WRITE)
WVIH-~:"7I:~~~~
V1L -
.t...::.~~~"-l.~fIL+'-~=~~~~+:--~~~IUj"-\'~~iCfI-:--~~~IL.lo~~~
o V1H - ~:fu~:fu'\l~:-:-=::i"'7\Jv,,:,::,:-:-=':""'IVi:7\.rv~ },.,¥----,j.J<:~~:"7I:"7t"':'Tf:'7
V1L -
o VOH VOL -
..............
+.....,~
___
i'~.Y·
____
.T'''-lo~~
----------------OPEN---------------240021-10
~Don'tCore
240021-6
3-8
21256
TIMING DIAGRAMS (Continued)
PAGE MODE READ-WRITE CYCLE
Q VOH -
VOL -
---------(JXXI
-s.....;;;;~~
240021-14
3-9
21256
TIMING DIAGRAMS (Continued)
RAS-ONLY REFRESH CYCLE
i----------tRc---------l
Q VOH- _ _ _ _ _ _ _ _ _ _ _ OPEN _ _ _ _ _ _ _ _ _ _ _ _ _ __
VOL -
240021-11
NOTE:
CAS = VIH:
IN,
D = Don't Care
HIDDEN REFRESH CYCLE
QVOH VOL -
----240021-12
~Oonltcare
240021-6
3-10
inter
21256
TIMING DIAGRAMS (Continued)
CAS-BEFORE-RAS REFRESH CYCLE
i---------tRc--------.J
V1H V1L -
CAS
Q
VOH VOL -
----------------------------OPEN--~----------------------------240021-13
NOTE:
Address,
1m
'N,
D = Don't Care
Don't Care
240021-6
3-11
21256
TIMING DIAGRAMS (Continued)
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
RAS V1H
V1L
=-----'\1
1----------tRAs--------------i
foo~----tRsH--------l
1,---,
READ CYClE
Q~H-
_____________________
_+~~--_Q.X
VOL -
WRITE CYCLE
f+--++-----tRWL---+--i
QVOH- _________________ OP~--------~~~---------------~----r_----------VOL -
WV1H V1L -
~~fu~~fu7l\1\7'\A.7I\1\7'\A.~
~~~~~.lL.:~!J,t;ilL.:~!J,t;~~~~-I-!-----~~~~¥-l~~~~~~~~
READ-WRITE CYCLE
W V1H V1L -
D V1H V1L -
~~~.K..~'_lj~~.K..~'_lj~.K.N
4o..li~~.K.~_'_lj~~.K..~'_lj~~.K..~_'_¥~....
1'-.-0---'[" ___.....~.K.~_.....00K.. .
240021-18
moon.teare
240021-6
3-12
intJ
21256
DEVICE OPERATION
Write
The 21256 contains 262,144 memory locations.
Eighteen address bits are required to address a particular memory location. Since the 21256 has only 9
address input pins, time multiplexed addressing is
used to input 9 row and 9 column addresses. The
multiplexing is controlled by the timing relationship
between the row address strobe (RAS), the column
address strobe (CAS) and the valid address inputs.
The 21256 can perform early write, late write and
read-modify-write cycles. The difference between
these cycles is in the state of data-out and is determined by the timing relationship between Wand
CAS. In any type of write cycle, data-in must be valid
at or before the falling edge of W or CAS, whichever
is later.
Early Write: An early write cycle is performed by
bringing W low before CAS. The data at the data
input pin (D) is written into the addressed memory
cell. Throughout the early write cycle the output remains in the Hi-Z state. This cycle is good for common liD applications because the data-in and dataout pins may be tied together without bus contention.
Operation of the 21256 begins by strobing in a valid
row address with RAS while CAS remains high.
Then the address on the 9 address input pins is
changed from a row address to a column address
and is strobed in by CAS. This is the beginning of
any 21256 cycle in which a memory location is accessed. The specific type of cycle is determined by
the state of the write enable pin and various timing
relationships. The cycle is terminated when both
RAS and CAS have returned to the high state. Another cycle can be initiated after RAS remains high
long enough to satisfy the RAS precharge time (tRP)
requirement.
Read-Modify-Write: In this cycle, valid data from
the addressed cell appears at the output before and
during the time that data is being written into the
same cell location. This cycle is achieved by bringing
W low after CAS and meeting the data sheet readmodify-write cycle timing requirements. This cycle
requires using a separate liD to avoid bus contention.
RAS and CAS Timing
Late Write: If W is brought low after CAS, a late
write cycle will occur. The late write cycle is very
similar to the read-modify-write cycle except that the
timing parameters, tRWO and lewo, are not necessarily met. The state of data-out is indeterminate
since the output could be either Hi-Z or contain data
depending on the timing conditions. This cycle requires a separate I/O to avoid bus contention.
The minimum RAS and CAS pulse widths are specified by tRAS(min) and tCAS(min) respectively. These
, minimum pulse widths must be satisfied for proper
device operation and data integrity. Once a cycle is
initiated by bringing RAS low, it must not be aborted
prior to satisfying the minimum RAS and CAS pulse
widths. In addition, a new cycle must not begin until
the minimum RAS precharge time, tRP, has been
satisfied. Once a cycle begins, internal clocks and
other circuits within the 21256 begin a complex sequence of events. If the sequence is broken by violating minimum timing requirements, loss of data integrity can occur.
Data Output
The 21256 has a tri-state output buffer which is controlled by CAS (and W for early write). Whenever
CAS is high (VIH) the output is in the high impedance
(Hi-Z) state. In any cycle in which valid data appears
at the output, the output first remains in the Hi-Z
state until the data is valid and then the valid data
appears at the output. The valid data remains at the
output until CAS returns high. This is true even if a
new RAS cycle occurs (as in hidden refresh). Each
of the 21256 operating cycles is listed below after
the corresponding output state produced by the cycle.
Read
A read, cycle is achieved by maintaining the write
enable input (W) high during a RAS/CAS cycle. The
output of the 21256 remains in the Hi-Z state until
valid data appears at the output. If CAS goes low
before tRCO(max), the access time to valid data is
specified by tRAC. If CAS goes low after tRCO(max),
the access time is measured from CAS and is specified by tCAC. In order to achieve the minimum access time, tRAc(min), it is necessary to bring CAS
low before tRCO(max).
Valid Output Data: Read, Read-Modify-Write, Hidden Refresh, Page Mode Read, Page Mode ReadModify-Write.
3-13
intJ
21256
HI-Z Output State: Early Write, RAS-only Refresh,
Page Mode Write, CAS-before-RAS Refresh, CASonly cycle.
Indeterminate Output State: Delayed Write
Refresh
The data in the 21256 is stored on a tiny capacitor
within each memory cell. Due to leakage, the data
will leak off after a period of time. To maintain data
integrity it is necessary to refresh each of the rows
every 4 ms. There are several ways to. accomplish
this.
RAS-Only Refresh: This is the most common method for performing refresh. It is performed by strobing
in a row address with RAS while CAS remains high.
CAS-before-RAS Refresh: The 21256 has CAS-before-RAS on-chip refreshing capability that eliminates the need for external refresh addresses. If
CAS is held low for the specified setup time (tCSR)
before RAS goes low, the on-chip refresh circuitry is
enabled. An internal refresh operation automatically
occurs and the on-chip refresh address counter is
internally incremented in preparation for the next
CAS-before-RAS refresh cycle.
read-modify-cycles. As long as the applicable timing
requirements are observed, it is possible to mix
these cycles in any order. A~e mode cycle begins
with a normal cycle. While RAS is kept low to maintain the row address, CAS is cycled to strobe in additional column addresses. This eliminates the time
required to set up and strobe sequential row addresses for the same page.
CAS-before-RAS Refresh Counter Test
Cycle
A special timing sequence using the CAS-beforeRAS counter test cycle provides a convenient method of verifying the functionality of the CAS-beforeRAS refresh activated circuitry.
After the CAS-before-RAS refresh operation, if CAS
goes high and then low again while RAS is held low,
the read and write operations are enabled.
This is shown in the CAS-before-RAS counter test
cycle timing diagram. A memory cell can be addressed with 9 row address bits and 9 column address bits defined as follows:
Row Address-Bits AO through A7 are supplied by
. the on-chip refresh counter. The AS bit is set high
internally.
Hidden Refresh: A hidden refresh cycle may be
performed while maintaining the latest valid data at
the output by extending the CAS active time and
cycling RAS. The 21256 hidden refresh cycle is actually a CAS-before-RAS refresh cycle within an extended read cycle. The refresh row address is provided by the on-chip refresh address counter. This
eliminates the need for the external row address
that is required in hidden refresh cycles by DRAMs
that do not have CAS-before-RAS refresh capability.
Column Address-Bits AO through AS are strobedin by the falling edge of CAS as in a normal memory
cycle.
Suggested CAS-before-RAS Counter
Test Procedure
The CAS-before-RAS refresh counter test cycle timing is used in each of the following steps:
1. Initialize the internal refresh counter by performing S cycles.
2. Write a test pattern of "lows" into the memory
cells at a single column address and 256 row addresses. (The row addresses are supplied by the
on-chip refresh counter.)
3. Using read-modify-write cycles, read the "lows"
written during step 2 and write "highs" into the
same memory locations. Perform this step 256
times so that highs are written into the 256 memory cells.
4. Read the "highs" written during step 3.
5. Complement the test pattern and repeat steps 2,
3 and 4.
Other Refresh Methods: It is also possible to refresh the 21256 by using read, write or read-modifywrite cycles. Whenever a row is accessed, all the
cells in that row are automatically refreshed. There
are certain applications in which it might be advantageous to perform refresh in this manner but in general RAS-only· or CAS-before-RAS refresh is the preferred method.
Page Mode
The 21256 has page mode capability. Page mode
memory cycles provide faster access and lower
power dissipation than normal memory cycles. In
page mode, it is possible to perform read, write or
3-14
inter
21256
ground lines act like transmission lines to the high
frequency transients generated by DRAMs. The impedance is minimized if all the power supply traces
to all DRAMs run both horizontally and vertically and
are connected at each intersection or better yet if
power and ground planes are used.
Power-Up
If RAS = Vss during power-up, the 21256 could begin an active cycle. This condition results in higher
than necessary current demands from the power
supply during power-up. It is recommended that
RAS and CAS track with Vee during power-up or be
held at a valid VIH in order to minimize the power-up
current.
Address and control lines should be as short as possible to avoid skew. In boards with many DRAMs
these lines should fan out from a central point like a
fork or comb rather than being connected in a serpentine pattern. Also the control logic should be
centrally located on large memory boards to facilitate the shortest possible address and control lines
to all the DRAMs.
An initial pause of 100 fts is required after power-up
followed by 8 initialization cycles before proper device operation is assured. 8 initialization cycles are
also required after any 4 ms period in which there
are no RAS cycles. An initialization cycle is any cycle
in which RAS is cycled.
Decoupling
Termination
The importance of proper decoupling cannot be over
emphasized. Excessil(e transient noise or voltage
droop on the Vee line can cause loss of data integrity (soft errors). The total combined voltage changes
over time in the Vee to Vss voltage (measured at
the device pins) should not exceed 500 mV.
The lines from the TIL driver circuits to the 21256
inputs act like unterminated transmission lines resulting in significant positive and negative overshoots at the inputs. To minimize overshoot it is advisable to terminate the inpu~ lines and to keep them
as short as possible. Although either series or parallel termination may be used, series termination is
generally recommended since it is simple and draws
no additional power. It consists of a resistor in series
with the input line placed close to the 21256 input
pin. The optimum value depends on the board layout. It must be determined experimentally and is
usually in the range of 200 to 400.
A high frequency 0.3 ftF ceramic decoupling capacitor should be connected between the Vee and
ground pins of each 21256 using the shortest possible traces. These capacitors act as a low impedance
shunt for the high frequency switching transients
generated by the 21256 and they supply much of the
current used by the 21256 during cycling.
In addition, a large tantalum capacitor with a value of
47 p.F to 100 ftF should be used for bulk decoupling
to recharge the· 0.3 ftF capacitors between cycles,
thereby reducing .power line droop. The bulk decoupiing capacitor should be placed near the point
where the power traces meet the power grid or power plane. Even better results may be achieved by
distributing more than one tantalum capacitor
throughout the memory array.
Board Layout
It is important to layout the power and ground lines
on memory boards in such a way that switching transient effects are minimized. The recommended
methods are gridded power and ground lines or separate power and ground planes. The power and
3-15
21256
PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL-IN-LINE PACKAGE
~50·20
t
I
~~~J
~-------A--------~.I
- . . . - f - - SEATING
PLANE
H
J
K
240021-15
Item
Millimeters
Inches
A
19.43 ±0.05
0.765 ± 0.002
8
6.86 ±0.05
0.270 ± 0.002
C
7.62
0.300
0
0.25 ±0.025
0.010 ±0.001
E
3.56 ±0.05
0.140 ±0.002
F
0.506 ±0.1
0.020 ± 0.004
G
3.3 ±0.1
0.130 ± 0.004
H
2.54
0.100
I
1.52
0.060
J
0.457 ±0.05
0.Q18 ± 0.002
K
0.1 ±0.05
0.040 ± 0.002
3-16
21256
PACKAGE DIMENSIONS (Continued)
18-PIN PLASTIC LEADED CHIP CARRIER
M
~--------L--------~
240021-16
Item
A
Millimeters
Inches
12.346 ±0.052
0.490 ± 0.002
B
13.2585 ± 0.0505
0.522 ± 0.002
C
7.366 ±0.051
0.290 ± 0.002
0
8.179 ±0.051
0.322 ± 0.002
E
2.083 ±0.051
0.082 ± 0.002
F
3.505 ±0.051
0.020 ± 0.004
G
0.7365 ±0.0505
0.029 ± 0.002
H
6.553 ±0.051
0.258 ±0.002
I
0.43 typ
0.017typ
J
0.279 ± 0.025
0.011 ± 0.001
K
0.76 typ
0.030typ
L
11.8365 ± 0.0505
0.466 ± 0.002
M
0.1 ±0.05
0.04 ±0.002
3-17
inter
21256
PACKAGE DIMENSIONS (Continued)
16-LEAD ZIG ZAG INLINE PACKAGE (ZIP)
1-------0.808- 0.812-----.f,!
o
·"'-nn
. '''Q....
,f \
MIN. 0 . 1 2 0 L
I
0.068 - 0.072
~
-11-0.008 - 0.Q12
-+
3-18
-0.050 TYP.
--1-0.100 TYP.
240021-17
21464
65,536 x 4-BIT DYNAMIC RAM WITH PAGE MODE
Parameter
21464-06
21464-07
21464-08
21464-10
Units
tRAG
Access Time from RAS
60
70
80
100
ns
tGAG
Access Time from CAS
15
25
30
50
ns
tRG
Read Cycle Time
110
130
150
190
ns
Symbol
Write or Output Enable Controlled
• Early
Write
+ 5V ± 10% Power Supply.
• Single
256 Cycle/4 ms Refresh
• JEDEC Standard Pinout in DIP, PLCC,
• ZIP
Mode Capability
• Page
CAS-Before-RAS Refresh Capability
• RAS-Only and Hidden Refresh
• Capability
• TTL Compatible Inputs and Outputs
The 21464 is a fully decoded 65,536 x 4 dynamic random access memory. The design is optimized for high
speed, high performance applications such as computer memory, buffer memory, peripheral storage and
environments where low power dissipation and compact layout are required.
The 21464 features page mode which allows high speed random access of memory cells within the same row.
CAS-before-RAS refresh capability provides on-chip auto refresh as l1n alternative to RAS-only refresh. Multiplexed row and column address inputs permit the 21464 to be housed in a standard 18-pin DIP.
Clock timing requirements are noncritical, and power supply tolerance is very wide. All inputs and outputs are
TTL compatible.
RAS-.r-----'
CAS
DATA
IN
BUFF
Vi -?L-r--r--.......
COLUMhI DECODER
SENSE AMPS &: I/O GATINGS
AO
A7
A
D
D
R
0
W
B
U
F
F
E
R
S
D
E
C
MEMORY ARRAY
262, 144 CELLS
0
D
E
R
+-Vcc
+-Vss
240022-1
Figure 1. Functional Block Diagram
3-19
October 1990
Order Number: 240022-005
inter
21464
DIP
PLCC
DO, OE VSSD04
OE
VSS
DO,
D0 4
D0 2
CAS
Vi
D0 3
RAS
A6
A5
A4
Vee
t~J
D0 2
~]
AO
A,
A2
A3
A7
RAS
51
-~
(TOP VIEW)
A5
~-
Vee
A7 A3
240022-3
Figure 2. Pin Configurations
PIN NAMES
OE
A,
~l A2
ZJ
f81 f91 fl-01 f1-11
240022-4
Vee
Vss
D0 3
~j AO
r,"3
A6 ~]
ZIP
RAS
CAS
U~ CAS
V§
A4
IN
•
Vi ~J
240022-2
Ao-A7
DQ1-DQ4
L!J ~~J t1..?J
Address Input
Data In/Out
Read/Write Input
Row Address Strobe
Column Address Strobe
Power (+5V)
Ground
Output Enable
3-20
inter
21464
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin
Relative to vss ................... -1 V to
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 7V
Voltage on Vee Supply
Relative to Vss ................... -1 V to
Storage Temperature .......... - 55°C to
+ 7V
+ 125°C
Power Dissipation ...................•...... 1.0W
Short Circuit Output Current ................ 50 mA
RECOMMENDED OPERATING CONDITIONS
Symbol
Voltages referenced to Vss. TA = 0 to 70°C
Parameter
Min
Typ
Max
Units
Vee
Supply Voltage
4.5
5.0
5.5
V
VSS
Ground
0
0
VIH
Input High Voltage
2.4
VIL
Input Low Voltage
-1.0
3-21
V
0
Vee
+
0.8
1
V
V
21464
D.C. OPERATING CHARACTERISTICS
Recommended operating conditions unless otherwise noted
Parameter
Symbol
Min
Max
Units
Test Condition
ICC1
Operating Current'
21464-06
21464-07
21464-08
21464-10
75
70
65
55
mA
mA
mA
mA
RAS and CAS Cycling
@tRC = Min
ICC2
Standby Current
21464-06
21464-07
21464-08
21464-10
2.0
2.0
2.0
5.0
mA
mA
mA
mA
HAS = CAS = VIH
ICC3
RAS-Only Refresh Current'
21464-06
21464-07
21464-08
21464-10
75
70
60
40
mA
mA
mA
mA
CAS = VIH, RAS Cycling
@tRC = Min
ICC4
Page Mode Current·
21464-06
21464-07
21464-08
21464-10
50
45
40
35
mA
mA
mA
mA
RAS = VIL, CAS Cycling:
tpc = Min
ICC5
CAS-Before-RAS'
Refresh Current
21464-06
21464-07
21464-08
21464-10
75
70
65
55
mA
mA
mA
mA
RAS Cycling @ tRC = Min
IlL
Input Leakage Current
-10
10
}LA
Any Input 0 s:: VIN s:: 5.5V,
VCC = 5.5V, Vss = OV, All Other
Pins Not Under Test = OV
.'Output Leakage Current
-10
10
}LA
Data Out is Disabled, OV s:: Your
s:: 5.5V, Vcc = 5.5V, Vss = OV
IDOL
VOH
Output High Voltage Level
VOL
Output Low Voltage Level
2.4
0.4
V
IOH = 5mA
V
IOL = 4.2mA
NOTE:
'Icc is dependent on output loading and cycle rates. Specified values are obtained with the output open. IcC is specified as
an average current.
.
CAPACITANCE TA ~
Symbol
25 D C
Parameter
Max
Unit
CIN1
Input Capacitance (Ao-A7)
Min
5
pF
CIN2
Input Capacitance (RAS, CAS, W, OE)
8
pF
Coa
Output Capacitance (001- D04)
7
pF
3-22
A.C. CHARACTERISTICS
Symbol
(O°C ~ T A ~ 70°C = 5.0V
Parameter
Min
c:.u
N
c:.u
± 10%. See notes 1, 2)
21464-06
Max
21464-07
Min
Max
21464-08
Min
Max
21464-10
Min
tRC
Random Read or Write Cycle Time
120
135
150
190
tRWC
Read-Modify-Write Cycle Time
165
195
225
265
tRAC
Access Time from RAS
tCAC
Access Time from CAS
tAA
Access Time from Column Address
Notes
ns
ns
80
100
15
25
30
35
35
40
ns
3,4,11
50
ns
3,4,5
50
ns
3, 10
ns
3
0
30
ns
7
3
100
ns
2
tClZ
CAS to Output in Low-Z
5
tOFF
Output Buffer Turn-Off Delay
0
25
tT
Transition Time (Rise and Fall)
3
50
tRP
RAS Precharge Time
55
tRAS
RAS Pulse Width
60
tRSH
RAS Hold Time
15
25
30
50
ns
tCPN
CAS Precharge Time
(All Cycles Except Page Mode)
10
10
15
25
ns
tCAS
CAS Pulse Width
15
tCSH
CAS Hold Time
60
tRCD
RAS to CAS Delay Time
15
50
25
50
25
60
25
75
ns
4
tRAD
RAS to Column Address Delay Time
15
25
20
35
20
40
20
55
n's
11
tCRP
CAS to RAS Precharge Time
(RAS Only Refresh)
5
5
5
0
25
3
50
65
10,000
70
5
0
25
3
50
75
10,000
80
80
10,000
100
(
Max
70
60
Units
ns
10,000
ns
I\)
10,000
25
10,000
70
15
30
10,000
15
50
10,000
100
80
15
-"
""
""
O'l
ns
ns
ns
tASR
Row Address Set-Up Time
0
0
0
0
ns
tRAH
Row Address Hold Time
15
15
15
15
ns
tASC
Column Address Set-Up Time
0
0
0
0
ns
tCAH
Column Address Hold Time
10
15
20
20
ns
tAR
Column Address Hold Time
Referenced to RAS
50
55
65
75
ns
6
A.C. CHARACTERISTICS
Symbol
Parameter
21464-06
Min
tv
'"
~
tRAL
Column Address to RAS Lead Time
tRCS
tRCH
tRRH
(
± 10%. See notes 1, 2) (Continued)
(O°C s T A S 70°C = 5.0V
Max
21464-07
Min
Max
21464-08
Min
30
35
40
Read Command Set-Up Time
0
0
Read Command Hold Time
Referenced to CAS
5
5
Read Command Hold Time
Referenced to RAS
5
twcs
Write Command Set-Up Time
0
tWCH
Write Command Hold Time
15
15
twp
Write Command Pulse Width
10
15
Max
21464-10
Min
Units
Notes
Max
50
ns
0
0
ns
5
5
ns
9
5
5
5
ns
9
0
0
0
ns
8
15
35
ns
15
35
ns
tRWL
Write Command to RAS Lead Time
15
25
30
35
ns
tCWL
Write Command to CAS Lead Time
15
25
30
35
ns
tos
Data-In Set-Up Time
0
0
0
0
ns
....
I\)
01:>0
10
en
01:>0
tOH
Data-In Hold Time
10
15
15
35
ns
10
tcwo
CAS to Write Enable Delay
35
50
60
70
ns
8
tRWO
RAS to Write Enable Delay
90
100
110
135
ns
8
tAWO
Column Address to W Delay Time
60
65
70
85
ns
8
tWCR
Write Command Hold Time
Referenced to RAS
40
55
60
85
ns
6
tOHR
Data-In Hold Time
Referenced to RAS
50
55
60
85
ns
6
tOEA
Access Time from OE
tOEO
OE to Data in Delay Time
tOEZ
Output Buffer Turn Off Delay from OE
tOEH
OE Hold Time Referenced to W
tREF
Refresh Period (256 Cycles)
15
15
20
20
15
15
20
20
4
30
20
4
0
4
ns
ns
30
25
20
---
25
20
25
ns
ns
4
ms
.
i
A.C. CHARACTERISTICS
Symbol
± 1 0%.
(O°C :;, T A :;, 70°C = 5.0V
Parameter
21464-06
Min
Max
21464-07
Min
Max
21464-08
Min
Max
21464-10
Min
Units
CAS Set-Up Time
(CAS-Before-RAS Refresh)
10
10
10
15
ns
tCHR
CAS Hold Time
(CAS-Before-RAS Refresh)
10
20
25
30
ns
tRPC
RAS Precharge to CAS Hold Time
10
10
10
10
ns
tCPT
Refresh Counter Test
CAS Precharge
15
35
50
60
ns
tpc
Page Mode Cycle Time
40
50
55
90
ns
tcp
CAS Precharge Time (Page Mode Only)
10
tCPA
Access Time from CAS Precharge
tPRWC
Fast Page Mode Read-Modify-Write
95
tRASP
RAS Pulse Width (Fast Page Mode)
60
tROH
RAS Hold Time Referenced to OE
10
15
40
15
45
105
10,000
70
30
50
120
10,000
80
100
ns
10,000
ns
3
ns
C11
15
20
20
cf
ns
55
140
10,000
Notes
Max
tCSR
U)
N
See notes 1, 2) (Continued)
ns
NOTES:
1. An initial pause of 200 fLs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved.
2. VIN(min) and Vldmax) are referenced levels for measuring timing of input signals. Transition times are measured between VIH(min) and Vldmax) and are assumed to be 5 ns
for all inputs.
3. Measured with a load equivalent to 2 TIL loads and 100 pF.
4. Operation within the tRCO(max) limit insures that tRAc(max) can be met. tRco(max) is specified as a reference point only. If tRCO is greater than the specified tRCO(max) limit,
then access time is controlled exclusively by tCAC.
5. Assumes that tRco :?: tRCO(max).
6. tAR, tWCR, tOHR are referenced to tRAo(max).
7. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL'
8. twcs, tRWO, tcwo and tAWO are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs :?: twcs(min) the cycle is
an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tcwo :?: tcwo(min) and tRWO :?: tRWO(min) and tAWO :?: tRWO(min) and
tAWO :?: tAWO(min), then the cycle is a read-write cycle and the data out will contain the data read from the selected address. If neither of the above conditions are satisfied,
the condition of the data out is indeterminate.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the CAS leading edge in early write cycles and to the W leading edge in read-write cycles.
11. Operation within the tRAO(max) limit insures that tRAc(max) can be met. tRAO(max) is specified as a reference point only. If tRAo is greater than the specified tRAO(max)
limit, then access time is controlled by tAA.
...
I\)
en
"'"
"'"
21464
TIMING DIAGRAMS
READ CYCLE
IRe
I RP
RAS
CAS
V'H VIL -
V1H Vil. -
V1H VIL -
Vi
Of
DO,-DO.
V'H VIL -
V1H VIL -
~DH
----OPEN
DL -
240022-5
WRITE CYCLE (EARLY WRITE)
IDHR~
I-tDH
IDSg
~~~~!:~------
1H
VVIL -_ - - - - - - ~'!lID o~
OPEN-------
240022-7
NOTE:
~ DOH'T~ARE
OE = Don't Care
240022-6
3-26
infef
21464
TIMING DIAGRAMS
(Continued)
WRITE CYCLE (OE CONTROLLED WRITE)
V1H -
RAS
Vil -
CAS
A
Vi
Of
DQ,-DQ4
V1H -
V1L V1H V1l -
V1H V1L -
240022-8
READ-MODIFY-WRITE CYCLE
~--------------------~WC--------------------~
~-----------------t~s----------------~
RAS
V1H V1L -
....;.._ _-,iJ----tAR
~__+---------tRSH-----------+_l
CAS
V1H V1L -
A
V'H V1L -
Vi
Of
DO
,-
J;:::j.j:::=~!:;:::j~t-------tCAS--------Ir+....,.
__"'\
V 1H -
V1L V1H V1L -
DO VI/OH 4 VI/OL -
240022-9
~
DON'T CARE
240022-6 •
3-27
intJ
21464
TIMING DIAGRAMS
(Continued)
PAGE MODE READ CYCLE
RAS
,V'H V'L -
CAS
V'H V'L -
A
V'H V'L -
Vi
V'H V'L -
OE
V'H V'L -
OQ,-OQ4
VOH VOL -
240022-10
PAGE MODE WRITE CYCLE
RAS
V'H V'L -
CAS
V'H V'L -
A
V1H V'L -
Vi
V1H V1L . -
OE
OQ,_OO4
V1H V'L -
V1H V'L -
240022-11
NOTE:
OE = Don't Care
~
DON'T CARE
240022-6
3-28
21464
TIMING DIAGRAMS
(Continued)
PAGE MODE READ-MODIfY-WRITE CYCLE
Vi
V1H V1L -
DE
V1H V1L -
240022-18
~
DON'T CARE
240022-6
3-29
21464
TIMING DIAGRAMS
(Continued)
RA8--0NLY REFRESH CYCLE
1----------tRc----------i
V1H -
~:A.7'V\7'\"''O\ .T.....:-----i.,~:""7'r~~~""l"r"7r"'l~:""7'r~~~""l"r"7r"'l~:""7'r~
V1L -
~~~Q/.~~ ~-----.;r"..K..x..l~~~~~..K..x..l~~~~~..K..x..l~
DATA VOH -
--------------HIGH-Z--------------
ADDRESS
(OUT) VOL -
240022-12
NOTE:
CAS
= VIH;
VIi,
OE, D = Don't Care.
CA8--BEFORE-RAS REFRESH CYCLE
i--------tRc-------..J
DATA
VOH - ----:LI>-_ _ _ _ _ _ _ _ _ _ _ _ _ HIGH_Z __________.....,__
(OUT) VOL 240022-13
NOTE:
Address VIi, OE, D = Don't Care.
~
DON"TCARE
240022-6
3-30
21464
TIMING DIAGRAMS
(Continued)
HIDDEN REFRESH CYCLE (READ)
RAS
CAS
A
VIH V1L -
VIH V1L -
VIH -
Vit. -
Vi
VIH V1L -
OE
VIH V1L -
DO,-DQ,
VIH -
V1L -
240022-14
~
DON'T CARE
240022-6
HIDDEN REFRESH CYCLE (WRITE)
RAS
CAS
A
Vi
OE
DO,_DO,
VIH -
V1L -
VIH -
V1L -
VIH V1L -
VIH -
V1L -
VIH V1L -
VIH -
Vil f-----tDH.--~
240022-19
~
240022-6
3-31
DON'T CARE
21464
TIMING DIAGRAMS
(Continued)
CAS-BEfORE-RAS REfRESH COUNTER TEST CYCLE
~----------------tAAS----------------~
RAS
V1H V1L -
CAS
V1H V1L -
A
V1H V1L -
t---------tRsH--------+/
1~----_(t--------tCAS------~~~---------
READ CYCLE
Vi
V1H V1L -
OE
V1H V1L -
OQ1_0Q 4
VOH VOL -
OPEN
WRITE CYCLE
Vi
V1H V1L -
OE
V1H V1L -
OQ1- oo4
V1H V1L -
Vi
V1H V1L -
OE
V1H V1L -
OQ1_0Q4
VI/OH VI/OL -
240022-20
~
DON'T CARE
240022-6
3-32
21464
tRCO(max), the access time is measured from CAS
and is specified by tCAC. In order to achieve the minimum access time, tRAdmin), it is necessary to bring
CAS low before tRCO(max).
DEVICE OPERATION
The 21464 contains 262,144 memory locations organized as 65,536 4-bit words. Sixteen address bits
are required to address a particular 4-bit word in the
memory array. Since the 21464 has only 8 address
input pins, time multiplexed addressing is used to
input 8 row and 8 column addresses. The multiplexing is controlled by the timing relationship between
the row address strobe (RAS) , and the column address strobe (CAS) and the valid address inputs.
Write
The 21464 can perform early write and read-modifywrite cycles. The difference between these cycles is
in the state of data-out and is determined by the
timing relationship between W, OE and CAS. In any
type of write cycle Data-in must be valid at or before
the falling edge of W or CAS, whichever is later.
Operation of the 21464 begins by strobing in a valid
row address with RAS while CAS remains high.
Then the address on the 8 address input pins is
changed from a row address to a column address
and is strobed in by CAS. This is the beginning of
any 21464 cycle in which a memory location is accessed. The specific type of cycle is determined by
the state of the write enable pin and various timing
relationships. The cycle is terminated when both
RAS and CAS have returned to the high state. Another cycle can be initiated after RAS remains high
long enought to satisfy the RAS precharge time (tRP)
requirement.
Early Write: An early write cycle is performed by
bringing W low before CAS. The 4-bit wide data at
the data input pins is written into the addressed
memory cells. Throughout the early write cycle the
outputs remain in the Hi-Z state regardless of the
state of the OE input.
Read-Modify-Write: In this cycle, valid data from
the addressed cells appears at the outp'uts before
and during the time that data is being written into the
sam~cell locations. This cycle is achieved by bringing W low after CAS and meeting the data sheet
read-modify-write timing requirements. The output
enable input (OE) must be low during the time defined by tOEA and toEZ for data to appear at the
outputs. If tewo and tRWO are not met the output
may contain invalid data. Conforming to the OE timing requirements prevents bus contention on the
21464 DQ pins.
RAS and CAS Timing
The minimum RAS and CAS pulse widths are specified by tRAS(min) and tcAS(min) respectively. These
minimum pulse widths must be satisfied for proper
device operation and data integrity. Once a cycle is
initiated by bringing RAS low, it must not be aborted
prior to satisfying the minimum RAS and CAS pulse
widths. In addition, a new cycle must not begin until
the minimum RAS precharge time, tRP, has been
satisfied. Once a cycle begins, internal clocks and
other circuits within the 21464 begin a complex sequence of events. If the sequence is broken by violating minimum timing requirements, loss of data integrity can occur.
Data Output
The 21464 has tri-state output buffers which are
controlled by CAS and OE. When either CAS or OE
is high (VIH) the outputs are in the high impedance
(Hi-Z) state. In any cycle in which valid data appears
at the outputs, the outputs first remain in the Hi-Z
state until the data is valid and then the valid data
appears at the outputs. The valid data remains at the
outputs until either CAS or OE returns high. This is
true even if a new RAS cycle occurs (as in hidden
refresh). Each of the 21464 operating cycles is listed
below after the corresponding output state produced
by the cycle.
Read
A read cycle is achieved by maintaining the write
enable input (W) high during a RAS/CAS cycle. The
four outputs of the 21464 remain in the Hi-Z state
until valid data appears at the outputs. The 21464
has common data 1/0 pins. For this reason an output enable control input (OE) has been provided so
the output buffer can be precisely controlled. For
data to appear at the outputs, OE must be low for
the period of time defined by tOEA and toEZ. If CAS
goes low before tRCO(max), the access time to valid
data is specified by tRAC. If CAS goes low after
Valid Output Data: Read, Read-Modify-Write, Hidden Refresh, Page Mode Read, Page Mode, ReadModify-Write.
Hi-Z Output State: Early Write, RAS-Only Refresh,
Page Mode Write, CAS-Only CyCle.
3-33
inter
21464
strobe in additional column addresses. This eliminates the time required to set up and strobe sequential row addresses for the same page.
Indeterminate Output State; Delayed Write (tewD
or tRWD are not met).
Refresh
Power-Up
.The data in the 21464 is stored on a tiny capacitor
within each memory cell. Due to leakage the data
will'leak off after a period of time. To maintain data
integrity it is necessary to refresh each of the rows
every 4 ms. There are several ways to accomplish
this.
If RAS = Vss during power-up, the 21464 might
begin an active cycle. This condition results in higher
than necessary current demands from the power
supply during power-up. It is recommended that AS
and CAS track with Vee during power-up or be held
at a valid VIH in order to minimize the power-up current.
RAS-Only Refresh: This is the most common method for performing refresh. It is performed by strobing
in a row address with RAS while CAS remains high.
'This must be performed on each of the 256 row addresses (Ao-A7) every 4 ms.
CAS-Before-RAS Refresh: The 21464 has CASBefore-RAS refresh capability that eliminates the
need for external refresh addresses. If CAS is held
low for the specified set-up time (tesR) before RAS
goes low, the on-chip refresh circuity is enabled. An
internal refresh operation automatically occurs and
the on-chip refresh address counter is internally incremented in preparation for the next CAS-BeforeRAS refresh Cycle:
Hidden Refresh: A hidden refresh cycle may be
performed while maintaining the lastest valid data at
the outputs by extending the CAS active time and
cycling RAS. The 21464 hidden refresh cycle is actually a CAS-Before-RAS refresh cycle within an extended read cycle. The refresh row address is provided by the on-chip refresh address counter. This
eliminates the need for the external row address
that is required in hidden refresh cycles by DRAMS
that do not have CAS-Before-RAS refresh capability.
An initial pause of 100 p.s is required after power-up
followed by 8 initialization cycles before proper device operation is assured. Eight initializations cycles
are also required after an 4 ms period in which there
are no RAS cycles. An initialization cycle is any cycle
in which RAS is cycled.
I
Termination
The lines from the TTL driver circuits to the 21464
inputs act like unterminated transmission lines resulting in significant positive and negative overshoots at the inputs. To minimize overshoot it is advisable to terminate the input lines and to keep them
as short as possible. Although either series or parallel termination may be used, series termination is
generally recommended since it is simple and draws
no additional power. It consists of a resistor in series
with the input line placed close to the 21464 input
pin. The optimum value depends on the board layout. It must be determined experimentally and is
usually in the range of 20.0. to 40.0..
Board Layout
Other Refresh Methods: It is also possible to refresh the 21464 by using read, write or read-modifywrite cycles. Whenever a row is accessed all the
cells in that row are automatically refreshed. There
are certain applications in which it might be advantageous to perform refresh in this manner but in general RAS-only or CAS-Before-RAS refresh are the preferred methods.
It is important to layout the power and ground lines
on memory boards in such a way that switching transient effects are minimized. The recommended
methods are gridded power and ground lines or separate power and ground planes. The power and
ground lines act like transmission lines to the high
frequency transients generated by DRAMs. The impedance is minimized if all the power supply traces
to all the DRAMs run both horizontally and vertically
and. are connected at each intersection, or better
yet, if power and ground planes are used.
Page Mode
Page mode memory cycles provide faster access
and lower power dissipation than normal memory
cycles. In page mode, it is possible to perform read,
write or read-modify-write cycles. As long as the applicable timing requirements are observed, it is possible to mix these cycles in any order. A page mode
cycle begins with a normal cycle. While RAS is kept
low to maintain the row address, CAS is cycled to
Address and control lines should be as short as possible to avoid skew. In boards with many DRAMs
these lines should fan out from a central point like a
fork or comb rather than being connected in a serpentine pattern. Also the control logiC should be
centrally located on the memory boards to facilitate
3-34
21464
the shortest possible address and control lines to all
the DRAMs.
ground pins of each 21464 using the shortest possible traces. These capacitors act as a low impedance
shunt for the high frequency switching transients
generated by the 21464 and they supply much of the
current used by the 21464 during cycling.
Decoupling
The importance of proper decoupling cannot be
overemphasized. Excessive transient noise or voltage droop on the Vee line can cause loss of data
integrity (soft errors). The total combined voltage
changes over time in the Vee to Vss voltage (measured at the device pins) should not exce,ed 500 mV.
In addition, a large tantalum capacitor with a value of
47 ILF to 100 ILF should be used for bulk decoupling
to recharge the 0.3 ILF capacitors between cycles,
thereby reducing power line droop. The bulk decoupiing capacitor shuld be placed near the point where
the power traces meet the power grid or power
plane. Even better results may be achieved by distributing more than one tantalum capacitor around
the memory array.
A high frequency 0.3 ILF ceramic decoupling capacitor should be connected between the Vee and
PACKAGE DIMENSIONS
l8-LEAD PLASTIC DUAL IN·LINE PACKAGE
~ ~ ~ -"r.lI'" "l:~ "r': I(E.,J~ECTr°,!:R"=rM.,A~RKr)rP: r-r I
I.
.1
J
r -........................................
~~
r
E
~SEATING
f!
PLANE
G
----1
L
K
K
240022-15
Item
Millimeters
Inches
A
22.950 ± 0.05
0.903 ± 0.002
0.252 ± 0.002
B
6.40 ± 0.05
C
7.62
0.300
D
0.025 ± 0.025
0.010 ± 0.001
E
3.25 ± 0.05
0.128 ± 0.002
F
0.506 ± 0.1
0.020 ± 0.004
G
3.302 ± 0.1
0.130 ± 0.004
H
2.54
0.100
,
I
1.27 ± 0.05
0.050 ± 0.002
J
0.457 ± 0.05
0.Q18 ± 0.002
K
1.32
0.052
3-35
inter
21464
PACKAGE DIMENSIONS
(Continued)
1S·PI" PLASTIC LEADED CHIP CARRIER
IT
D
C
[
~------L------~
240022-16
Item
Millimeters
Inches
Item
Millimeters
Inches
A
12.346 ± 0.052
0.490 ± 0.002
H
6.553 ± 0.051
0.258 ± 0.002
B
13.2585 ± 0.0505
0.522 ± 0.002
I
0.43 type
0.017typ
C
7.366 ± 0.051
0.290 ± 0.002
J
0.279 ± 0.025
0.011 ± 0.001
D
8.179 ± 0.051
0.322 ± 0.002
K
0.76 typ
O.030typ
E
2.083 ± 0.051
0.082 ± 0.002
L
11.8365 ± 0.0505
0.466 ± 0.002
F
3.505 ± 0.051
0.138 ± 0.002
M
6.756 ± 0.051
0.266 ± 0.002
G
0.7365 ± 0.0505
0.029 ± 0.002
20·LEAD ZIG·ZAG INLINE PACKAGE (ZIP)
1---------------- : :g~~
---------------1'1
o
I
o.olojL
REf.
0.01S-0.022J
L
0.fl50 TYP....
I
240022-17
3-36
21010
1,048,576 x 1-Bit Dynamic RAM with Page Mode
Performance Range
•
tRAC
tCAC
tRC
21010-06
60ns
20 ns
110 ns
21010-07
70 ns
20 ns
130 ns
21010-08
80 ns
20 ns
160 ns
21010-10
100 ns
25 ns
190 ns
• Single 5V
Fast Page Mode Operation
+
10% Power Supply
• CAS before RAS Refresh Capability
•
512 Cycles/S ms refresh
• Common I/O Using "Early Write"
•
Available in Plastic DIP, SOJ and ZIP
Packages
Intel 21010 is a CMOS high speed 1,048,576 x 1 dynamic RAM optimized for high performance applications
such as mainframes, graphics and microprocessor systems.
21010 features Fast Page Mode operation which allows high speed random access of memory cells within the
same row.
CAS before RAS refresh capability provides on-chip auto refresh as an alternative to RAS only refresh. All
Inputs, Output and Clocks are fully CMOS and TTL compatible.
Functional Block Diagram
"'---1..---'
.....,"""T-..~-----~~
W
iii .......
PIN CONFIGURATION
DIP
ZIP
SOJ
SENSE AMPS &: I/O GAnNGS
AD
...
I
MEMORY ARRA.Y
1048,576 CELLS
+-Vee
+-V55
240153-2
~
240153-16
240153-3
U L-L-L-_ _ _ _ _~
240153-1
NOTE:
T.F. = Test Function, Ground or No Connect
Pin Names
Ao-Ag Address Inputs
W
3-37
Read/Write Strobe
RAS
Row Address Strobe
CAS
Column Address Strobe
0
Data In
Q
Data Out
VSS
Ground
Vee
Power +5V
August 1990
Order Number: 240153-005
21010
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Voltage on Any Pin Relative to vss
(VIN. VOUT) .................... -1V to + 7.0V
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
'may affect device reliability.
Voltage on Power Supply Relative to Vss
(Vcd ............... : .......... -1V to +7.0V
Storage Temperature (Tslg) ..... - 55°C to + 150°C
Power Dissipation (Pd) ................... 600 mW
Short Circuit Output Current (los) '........... 50 mA
RECOMMENDED OPERATING CONDITIONS
= O°C to + 70°C)
(Voltage Referenced to Vss. TA
Symbol
Parameter
Min
Typ
Max
Units
Vcc
Supply Voltage
4.5
5.0
5.5
V
Vss
Ground
0
0
0
V
VIH
Input High Voltage
2.4
VCC + 1
V
VIL
Input Low Voltage
-1.0
0.8
V
NOTES:
1. VIL (Min) = - 1.0V for continuous DC level.
2. VIL (Min) = -2.0V for pulse width < 20 ns.
Capacitance
Symbol
(TA = 25°C)
Parameter
Min
Max
Units
pF
Cinl
Input Capacitance (Ao-A9. D)
6
Cin2
Input Capacitance (RAS. CAS. WE)
7
pF
Cout
Output Capacitance (0)
7
pF
D.C. AND OPERATING CHARACTERISTICS
(Recommended Operating Conditions unless Otherwise Noted)
Symbol
Speed
Parameter
Min
Max
Units
ICCl
ICCl
Operating Current
(RAS and CAS Cycling
@tRC = Min
-06
-07
-08
-10
90
80
70
60
mA
mA
mA
mA
ICC2
Standby Current
(TTL Power Supply Current)
-06
2
mA
ICC3
ICC3
RAS Only Refresh Current
(CAS = VIH. RAS Cycling
@tRC = Min
-06
-07
-08
-10
90
80
70
60
mA
mA
mA
mA
ICC4
ICC4
Fast Page Mode Current
(RAS = VIL. CAS Cycling
@tpc = Min
-06
-07
-08
-10
70
60
50
40
mA
mA
mA
mA
3-38
21010
D.C. AND OPERATING CHARACTERISTICS (Continued)
(Recommended Operating Conditions unless Otherwise Noted)
Symbol
Parameter
Speed
Min
Max
Units
1
mA
90
80
70
60
mA
mA
mA
mA
ICC5
Standby Current
(CMOS Power Supply Current)
ICC6
CAS-before-RAS Refresh
Current (RAS and CAS Cycling
@tRC = Min
IlL
Input Leakage Current
(Any Input 0 < VIN < 6.5V
All Other Pins = OV)
-10
10
/LA
IOL
Output Leakage Current
(Data Out is Disabled
and 0 < VOUT < 5.5V)
-10
10
/LA
VOH
Output High Voltage Level
(IOH = -5mA)
2.4
VOL
Output Low Voltage Level
(IOL = 4.2 mAl
-06
-07
-08
-10
V
0.4
V
NOTE:
ICC1, ICC3, ICC4, and ICC6 are dependent on output loading and cyCle rates. Specified values are obtained with the output
open. Icc is specified as average current.
A.C. CHARACTERISTICS
(TA = O·C to +70·C, VCC = 5V
Symbol
Parameter
(See Notes 1,2)
+ 10%)
21010-06
Min
Max
21010-07
Min
8
Max
21010-08
21010-10
Min
Min
8
Max
Notes
tREF
Time between
Refresh
tRC
RandomR/W
Cycle Time
110
tRWC
RMW Cycle Time
135
tRAC
Access Time
from RAS
60
70
80
100
ns
(Notes 4, 7)
tCAC
Access Time
from CAS
20
20
20
25
ns
(Notes 5,7)
tAA
Access Time from
Column Address
30
35
40
50
ns
(Notes 6, 7)
tCLZ
CAS to Output in
LowZ
0
toFF
Output Buffer TurnOff Delay Time
0
20
0
20
0
20
0
20
ns
tT
Transition Time
3
50
3
50
3
50
3
50
ns
130
8
Units
Max
160
190
185
155
0
ms
ns
220
0
3-39
8
ns
0
ns
inter
21010
A.C. CHARACTERISTICS (See Notes 1, 2)
(TA = ODC to + 70DC, VCC = 5V ,+ 10%) (Continued)
Symbol
Parameter
21010-06
21010-07
21010·08
21010-10
Min
Min
Min
Min
Max
Max
Notes
RAS Precharge
Time
40
tRAS
RAS Pulse Width
60
tRSH
RAS Hold Time
20
20
25
25
ns
tCRP
CASto RAS
Precharge Time
5
5
5
5
ns
tRCD
RAS to CAS
Delay Time
20
40
tCAS
CAS Pulse Width
20
10K
tCSH
CAS Hold Time
60
70
80
100
ns
tCPN
CAS Precharge
Time
10
10
15
15
ns
'tASR
Row Address
Set-Up Time
0
0
0
0
ns
tRAH
Row Address
Hold Time
10
10
15
15
ns
tASC
Column Address
Set-UpTime
0
0
0
0
ns
tCAH
Column Address
Hold Time
15
15
20
20
ns
tAR
Column Address
Time Referenced
toRAS
50
55
65
75
ns
tRAD
RAS to Column
Address Delay Time
15
tRAL
Column Address to
RAS Lead Time
30
35
40
50
ns
tRCS
Read Command
Set-UpTime
0
0
0
0
ns
tRRH
Read Command
Hold Time
Referenced to RAS
0
0
0
0
ns
(Note 12)
tRCH
Read Command
Hold Time
Referenced to CAS
0
0
0
0
ns
(Note 12)
twcs
Write Command
Set-Up Time
0
0
0
0
ns
(Note 13)
twci-!
Write Command
Hold Time
15
15
20
20
ns
10K
30
70
70
Units
Max
tRP
,
50
Max
10K
20
50
20
10K
15
35
3-40
80
80
10K
25
60
20
10K
20
40
100
ns
10K
ns
25
75
ns
25
10K
ns
20
50
ns
(Notes 9, 10)
(Note 11)
inter
21010
A.C. CHARACTERISTICS
(TA = O·C to +70·C, Vec = 5V
Symbol
(See Notes 1, 2)
+ 10%) (Continued)
Parameter
21010·06
21010·07
Min
Min
Max
Max
21010·08
21010-10
Min
Min
Max
60
Max
75
Units
tWCR
Write Command
Referenced to RAS
50
55
twp
WE Pulse Width
15
15
15
20
ns
tRWL
Write Command to
RAS Lead Time
20
20
25
25
ns
tcWL
Write Command to
CAS Lead Time
20
20
20
25
ns
tDS
DIN Set-Up Time
0
0
0
0
ns
Notes
ns
tDH
DIN Hold Time
15
15
20
20
ns
tDHR
Data-In Hold Time
Referenced to RAS
50
55
60
75
ns
tRWD
RAS to WE Delay Time
60
70
80
100
ns
(Note 13)
tcWD
CAS to WE Delay Time
20
20
20
25
ns
(Note 13)
tAWD
Column Address to
WE Delay Time
30
35
40
50
ns
tRPC
RAS Precharge Time to
CAS Active Time
10
10
10
10
ns
tesR
CAS Set-Up Time
for CAS before
RAS Refresh
10
10
10
10
ns
tCHR
CAS Hold Time for CAS
before RAS Refresh
20
20
30
30
ns
tePT
Refresh Counter Test
CAS Precharge Time
30
35
40
50
ns
3-41
intJ
21010
A.C. CHARACTERISTICS (See Notes 1. 2)
(TA = O°C to + 70°C. VCC = 5V + 10%) (Continued)
Symbol
Parameter
21010-06
Min
Max
21010-07
Min
Max
21010-08
Min
Max
21010-10
Min
Max
Units
Notes
FAST PAGE MODE
tpc
Fast Page Mode
Cycle Time
45
45
50
60
ns
tPRWC
Fast Page Mode
RMWCycle
Time
70
70
75
90
ns
tePA
Access Time
from CAS
Precharge
tcp
Fast Page Mode
CAS Precharge
Time
10
tRASP
RASPulse
Width (Fast
Page Mode)
60
40
40
10
100K
70
45
10
10
100K
80
55
100K
100
ns
(Notes 7.14)
ns
100K
ns
NOTES:
1. An initial pause of 200 ".s is required after power-up followed by any 8 RAS-only cycles before proper device operation is
achieved.
2. A.C. characteristics assume tT = 5 ns.
3. VIN (min) and VIL (max) are reference levels for measuring timing of input signals. Also. transition times are measured
between VIH (min) and VIL (max) ..
4. Assumes that tRCD ,;; tRCD (max). tRAD ,;; tRAD (max). If tRCD (or tRAD) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCD (or tRAD) exceeds the value shown.
5. If tRCD ;;, tRCD (max). tRAD ;;, tRAD (max). and tASC ;;, tAA - !cAC - tT access time is tCAC'
6. If tRAD ;;, tRAD (max) and tASC ,;; tAA - tCAC - tT. access time is tAA'
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. !oFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point
only; if tRCD is greater than the specified tRCD (max) limit. access time is controlled exclusively by tCAC or tAA.
10. tRCD (min) = tRAH (min) + 2 tT + tASC (min).
.
11. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference pOint
only; if tRAD is greater than the specified tRAD (max) limit. access time is exclusively controlled by tCAC or tAA'
12. Either tRRH or tRCH must be specified for a read cycle.
.
13. tWCS. !cwo. tRWD. and tAWD are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
.
14. !cPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").
3-42
21010
Read Cycle
t Rc
t RAS
RAS
VIH VIL -
CAS
VIH VIL -
tAR
t RSH
leAs
tRAL
A
VIH VIL -
Vi
----------OPEN
Q
----- .•......... -1V to
Storage Temperature (Tstg) ..... -55°C to
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 7.0V .
+ 7.0V
+ 150°C
Power Dissipation (PO) .................. 600 mW
Short Circuit Output Current (los) ........... 50 rnA
RECOMMENDED OPERATING CONDITIONS
Voltage referenced to Vss, T A = O°C to 70°C
Symbol
Parameter
Min
Typ
Max
Unit
Vcc
Supply Voltage
4.5
5.0
5.5
V
Vss
Ground
0
0
0
V
VIH
Input High Voltage
2.4
VIL
Input Low Voltage
-1.0
-
Vcc
+1
V
0.8
V
NOTES:
1. VIL (min) = 1.0V for· continuous DC level.
2. VIL (min) = 2.0V for pulse width < 20 ns.
CAPACITANCE
Symbol
TA = 25°C
Parameter
CIN1
Input Capacitance (Ao-As)
CIN2
Input Capacitance (RAS, CAS, W, OE)
COUT
Output Capacitance (001-004)
Min
Max
Unit
-
6
pF
7
pF
7
pF
D.C. AND OPERATING CHARACTERISTICS
Recommended operating conditions unless otherwise noted
Symbol
Speed
Parameter
ICC1
Operating Current
(RAS and CAS Cycling @ tRC = Min)
.ICC2
Standby Current
(TTL Power Supply Current)
ICC3
RAS Only Refresh Current
(CAS = VIH, RAS Cycling @ tRC = Min)
-06
-07
-08
-10
ICC4
Fast Page Mode Current
(RAS = VIL, CAS Cycling @tpc = Min)
-06
-07
-08
-10
ICC5
Standby Current
(CMOS Power Supply Current)
3-54
-06
-07
-08
-10
Min.
-
-
-
Max
Units
90
80
70
60
rnA
rnA
rnA
rnA
2
rnA
90
80
70
60
rnA
rnA
rnA
rnA
75
65
55
45
rnA
rnA
rnA
rnA
1
rnA
21014
D.C. AND OPERATING CHARACTERISTICS (Continued)
Recommended operating conditions unless otherwise noted
Symbol
ICC6
Parameter
Speed
CAS-before-RAS Refresh Current
(RAS and CAS Cycling @ tRC = Min)
-06
-07
-08
-10
Min
-
Max
Units
90
80
70
60
rnA
rnA
rnA
rnA
IlL
Input Leakage Current
(Any Input 0 ::;; VIN ::;; 6.5V
All Other Pins = OV)
-10
10
/LA
IOL
Output Leakage Current
(Data Out is Disabled and
0::;; VOUT ::;; 5.5V)
-10
10
/LA
VOH
Output High Voltage Level
(IOH = -5 rnA)
2.4
-
V
VOL
Output Low Voltage Level
(IOL = 4.2 rnA)
-
0.4
V
NOTE:
ICC1' ICC3, ICC4 and Iccs are dependent on output loading and cycle rates. Specified values are obtained with the output
open. Icc is specified as average current.
A.C. CHARACTERISTICS(1,2)
= O·C to 70·C, VCC = 5V ± 10%
TA
Symbol
tREF
Parameter
21014-06
21014-07
21014-08
21014-10
Min
Min
Min
Min
Time between Refresh
Max
8
Max
8
Max
8
8
Units
Notes
Max
ms
tRC
Random R/W Cycle Time
110
130
150
180
ns
tRWC
RMW Cycle Time
165
185
205
245
ns
tRAC
Access Time from RAS
60
70
80
100
ns
4, 7
tCAC
Access Time from CAS
20
20
20
25
ns
5, 7
tAA
Access Time from
Column Address
30
35
40
50
ns
6, 7
tCLZ
CAS to Output in Low Z
0
tOFF
Output Buffer Turn-Off
Delay Time
0
20
tT
Transition Time
3
50
tRP
RAS Precharge Time
40
tRAS
RAS Pulse Width
60
tRSH
RAS Hold Time
20
20
20
25
ns
tcRP
CAStoRAS
Precharge Time
5
5
5
5
ns
tRCD
RAS to CAS Delay Time
tCAS
tCSH
0
0
20
3
50
10K
20
40
CAS Pulse Width
20
10K
CAS Hold Time
60
70
10K
20
50
20
10K
70
3-55
0
20
3
50
80
10K
25
60
20
10K
80
0
20
ns
3
50
ns
ns
70
60
50
ns
0
0
100
10K
ns
25
75
ns
25
10K
ns
100
ns
9, 10
inter
21014
A.C. CHARACTERISTICS(1, 2) (Continued)
TA = O·C to 70·C, VCC = 5V ±10%
Symbol
Parameter
21014-06
21014-07
21014-08
21014-10
Min
Min
Min
Min
Max
Max
Max
Units
Notes
Max
tCPN
CAS Precharge Time
10
10
10
15
ns
tASR
Row Address Set-Up Time
0
0
0
0
ns
tRAH.
Row Address Hold Time
10
10
15
15
ns
tASC
Column Address
Set-UpTime
0
0
0
0
ns
tCAH
Column Address
Hold Time
15
15
20
20
ns
tAR
Column Address Time
Referenced to RAS
50
55
65
75
ns
tRAO
RAS to Column Address
Delay Time
15
tRAL
Column Address to
RAS Lead Time
30
35
40
50
ns
tRCS
Read Command
Set-UpTime
0
0
0
0
ns
tRRH
Read Command Hold
Time Referenced to RAS
0
0
0
0
ns
12
tRCH
Read Command Hold
Time Referenced to CAS
0
0
0
0
ns
12
twcs
Write Command
Set-UpTime
0
0
0
0
ns
13
tWCH
Write Command
Hold Time
15
15
15
20
ns
twCR
Write Command Hold
Time Referenced to RAS
50
55
65
75
ns
30
15
35
20
40
20
50
ns
15
15
20
20
ns
tRWL
•Write Command to
RAS Lead Time
20
20
20
25
ns
tcwL
Write Command to
CAS Lead Time
20
20
20
25
ns
tos
DIN Set-Up Time
0
0
0
0
ns
tOH
DIN Hold Time
15
15
20
20
ns
tOHR
Data-In Hold Time
Referenced to RAS
50
55
65
75
ns
twp
WE Pulse Width
11
tRWO
RAS to WE Delay Time
80
100
110
135
ns
13
tcwo
CAS to WE Delay Time
40
50
50
60
ns
13
tAWO
Column Address to
WE Delay Time
50
65
70
85
ns
tRPe
RAS Precharge Time to
CAS Active Time
10
10
10
10
ns
tCSR
CAS Set-Up Time for CAS
before RAS Refresh
10
10
10
10
ns
3-56
21014
A.C. CHARACTERISTICS(1, 2) (Continued)
= O·C to 70·C, VCC = 5V ±10%
TA
Symbol
21014-06
21014-07
21014-08
21014-10
Min
Min
Min
Min
Parameter
Max
Max
Max
Units
tCHR
CAS Hold Time for CAS
before RAS Refresh
20
20
25
30
ns
tCPT
Refresh Counter Test CAS
Precharge Time
30
35
40
50
ns
tROH
RAS Hold Time
Referenced to OE
10
20
20
20
ns
tOEA
OE Access Time
tOED
OE to Data Delay
15
toEZ
Output Buffer Turn Off
Delay Time from OE
0
tOEH
OE Command Hold Time
15
15
20
20
20
15
0
20
20
0
20
20
25
25
20
0
Notes
Max
ns
ns
25
25
ns
ns
FAST PAGE MODE
Symbol
Parameter
21014-06
Min
Max
21014-07
Min
Max
21014-08
Min
Max
21014-10
Min
Units
tpc
Fast Page Mode
Cycle Time
45
45
50
60
ns
tPRWC
Fast Page Mode RMW
Cycle Time
75
100
105
125
ns
tCPA
Access Time from CAS
Precharge
tcp
Fast Page Mode CAS
Precharge Time
10
tRASP
RAS Pulse Width
(Fast Page Mode)
60
45
40
10
100K
70
45
10
100K
80
55
10
100K
100
Notes
Max
ns
7, 14
ns
100K
ns
NOTES:
1. An initial pause of 200 p-s is required after power-up followed by any 8 RAS-only cycles before proper device operation is
aChieved.
2. A.C. characteristics assume tT = 5 ns.
3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured
between VIH (min) and VIL (max).
4. Assumes that tRCD s; tRCD (max), tRAD s; tRAD (max). If tRCD (or tRAD) is greater than the maximum recommended value
shown in this table tRAc will be increased by the amount that tRCD (or tRAD) exceeds the value shown.
5. If tRCD :;, tRCD (max), tRAD :;, tRAD (max), and tASC :;, tM - !cAC - tT, access time is !cAC·
6. If tRAD :;, tRAD (max) and tASC s; tAA - tCAC - tT, access time is tM.
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. !oFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point
only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled exclusively by tCAC or tM.
10. tRCD (min) = tRAH (min) + 2tT + tASC (min).
11. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point
only; if tRAD is greater than the specified tRAD (max) limit, access time is exclusively controlled by tCAC or tM.
12. Either tRRH or tRCH must be specified for a read cycle.
13. twcs, tCWD, tRWD, and tAWD are non restrictive operating parameters. They are included in the Data Sheet as Electrical
characteristics only.
14. tCPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").
3-57
inter
21014
TIMING DIAGRAMS
READ CYCLE
RAS
V1H V1L -
CAS
V1HV1L -
A
V1H V1L -
W
V1H V1L -
OE
V1HV1L -
DQ1-DQ4
VOHVOL ...:.
~DON'TCARE
240512-5
3-58
inter
21014
TIMING DIAGRAMS (Continued)
WRITE CYCLE (EARLY WRITE)
HAS
V1H V1L -
CAS
V1H V1L -
A
V1H Vil -
W
V1H Vil -
OE
V1H V1l -
DQ1-DQ4
V1H Vil -
OPEN
240512-6
WRITE CYCLE (OE CONTROLLED WRITE)
RAS
V1H -
VIL -
CAS
V1H VIL -
A
V1H Vil -
W
V1H -
OE
001-004
vlt -
YIH-
VIL -
V1H -
Vil -
~DON'TCARE
240512-7
3-59
inter
21014
TIMING DIAGRAMS (Continued)
READ-MODIFY-WRITE
~-------------~--------------~
I--------I.As---------I
V1H -
--~r---IA.
VIL -
icsH
--I-+-----I.SH------+-I
VIHVII..-
~it------t_,~-~----t~s------~~~~--~
A
OQ1-oo.4 VI/OH -
VVOL -
---------------h~~~~~
240512-8
FAST PAGE MODE READ CYCLE
v.. _ ---.u--V1L -
A
DQl-DQ4
•
~DON'TCAR[
240512-9
3-60
21014
TIMING DIAGRAMS (Continued)
FAST PAGE MODE WRITE CYCLE
RAs
V1H V1L -
CAS
V1H 'Y1L -
Y1H -
A
V1L -
Y1H -
'Ii
VIL-
Y1H V1L -
a.
DQ1-DQ4
V1H -
V1L -
240512-10
FAST PAGE MODE READ-MODIFY-WRITE
RAS
CAS
v.. V1L -
Y1H -
VIL-
A
'Ii
OE
V1H-
VIL -
V1H -
V1L -
DQ1-0Q4
240512-11
3-61
inter
21014
TIMING DIAGRAMS (Continued)
RAS-ONLY REFRESH CYCLE
Note:
IN, DE
=
Don't ca~e
1-----------tRc----------i
t--------tRAs------+l
RAS
V1H V1L -
CAS
V1H V1L -
A
V1H V1L -
240512-12
CAS-BEFORE-RAS, REFRESH CYCLE
Note:
IN,
CE, A = Don't care
t-----------tRC-----------t
1-------tRAs-------t------
RAS
V1H V1L -
CAS
V1H V1L -
1----tCHR - - - - . f
001-004
VI/OH
VI/OL
~---tCPN---,---i
~-----------------OPEN-----------------------------
~DON'TCARE
240512-13
3-62
intJ
21014
TIMING DIAGRAMS (Continued)
HIDDEN REFRESH CYCLE (READ)
m
CAS
V 1H V1L -
A
Vi
VIH -
liE
V,H -
DQ1-DQ4
V1L -
V1L -
VOH VOL -
240512-14
HIDDEN REFRESH CYCLE (WRITE)
'Re
'RAS
m
CAS
A
Vi
liE
001-004
V1H -
V,L -
V1H -
V,L -
V1H -
V,L -
V'H-
V,L V1H -
V,L V1H V1L -
'OHR
~DON'TCARE
240512-15
3-63
inter
21014
TIMING DIAGRAMS (Continued)
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
i+----------tRAS----------i
V1H-----i.
V 1L -
f 4 - - - - - tR S H - - - - - I
Jr------,lI-----tcAs---....-..!
A
~H+-----
V1HV 1L -
READ CYCLE
Vi
OE
OOl-0Q4
V 1H V1L -
V 1H V1L -
VOHVOL -
------OPEN"----I-tt--~~--.:~~~~~-~---
WRITE CYCLE
Vi
V 1H VIL -
OE
V 1H V 1L -
OQ1-0Q4
V1H V 1L -
Vi
OE
OOl-0Q4
---------OPEN-------~--~~~:;--~--------~~---------
VIHV 1L -
V 1H V 1L -
VI/OH VI/OL -
1881 DON'T CARE
240512-16
3-64
intJ
21014
address becomes valid after tRAO (max), access is
specified by tCAC or tAA' In order to achieve the minimum access time, tRAC (min), it is necessary to meet
both tRCO (max) and tRAO (max).
21014 OPERATION
Device Operation
The 21014 contains 1,048,576 memory locations organized as 262,144 four-bit words. Eighteen address
bits are required to address a particular 4-bit word in
the memory array. Since the 21014 has only 9 address input pins, time multiplexed addressing is used
to input 9 row and 9 column addresses. The multiplexing is controlled by the timing relationship between the row address strobe (RAS), the column address strobe (CAS) and the valid address inputs.
The 21014 has common data I/O pins. For this reason an output enable control input (DE) has been
provided so the output buffer can be precisely controlled. For data to appear at the outputs, DE must
be low for the period of time defined by tOEA and
tOEZ·
Operation of the 21014 begins by strobing in a valid
row address with RAS while CAS remains high.
Then the address on the 9 address input pins is
changed from a row address to a column address
and is strobed in by CAS. This is the beginning of
any 21014 cycle in which a memory location is accessed. The specific type of cycle is determined by
the state of the write enable pin and various timing
relationships. The cycle is terminated when both
RAS and CAS have returned to the high state. Another cycle can be initiated after RAS remains high
long enough to satisfy the RAS precharge time (tRP)
requirement.
The 21014 can perform early write and read-modifywrite cycles. The difference between these cycles is
in the state of data-out and is determined by the
timing relationship between W, DE and CAS. In any
type of write cycle data-in must be valid at or before
the falling edge of W or CAS, whichever is later.
RAS and CAS Timing
Read-Modify-Write: In this cycle, valid data from the
addressed cells appears at the outputs before and
during the time that data is being written into the
same cell locations. This cycle is achieved by bringing W low after CAS and meeting the data sheet
read-modify-write timing requirements. This output
enable input (DE) must be low during the time defined by toEA and tOEZ for data to appear at the
outputs. If tCWD and tRwD are not met the output
may contain invalid data. Conforming to the DE timing requirements prevents bus contention on the
21014 OQ pins.
Write
Early Write: An early write cycle is performed by
bringing W low before CAS. The 4-bit wide data at
the data input pins is written into the addressed
memory cells. Throughout the early write cycle the
outputs remain in the Hi-Z state. In the early write
cycle the output buffers remain in the Hi-Z state regardless of the state of the DE input.
The minimum RAS and CAS pulse widths are specified by tRAS (min) and tCAS (min) respectively. These
minimum pulse widths must be satisfied for proper
device operation and data integrity. Once a cycle is
initiated by.bringing RAS low, it must not be aborted
prior to satisfying the minimum RAS and CAS pulse
widths. In addition, a new cycle must not begin until
the minimum RAS precharge time, tRP, has been
satisfied. Once a cycle begins, internal clocks and
other circuits within the 21014 begin a complex sequence of events. If the sequence is broken by violating minimum timing requirements, loss of data integrity can occur.
Data Output
The 21014 has tri-state output buffers which are
controlled by CAS and DE. When either CAS or DE
is high (VIH) the outputs are in the high impedance
(Hi-Z) state. In any cycle in which valid data appears
at the output the output goes into the low impedance
state in a time specified by tCLZ after the falling edge
of CAS. Invalid data may be present at the output
during the time after tClZ and before the valid data
appears at the output. The timing parameters tCAC,
tRAC and tAA specify when the valid data will be
present at the output. This is true even if a new RAS
cycle occurs (as in hidden refresh). Each of the
21014 operating cycles is listed below after the corresponding output state produced by the cycle.
Read
A read cycle is achieved by maintaining the write
enable input (W) high during a RAS/CAS cycle. The
access time is normally specified with respect to the
falling edge of RAS. But the access time also depends on the falling edge of CAS and on the valid
column address transition.
If CAS goes low before tRCO (max) and if the column
address is valid before tRAO (max) then the access
time to valid data is specified by tRAC (min). However, if CAS goes low after tRCO (max) or if the column
3-65
inter
21014
Valid Output Data: Read, Read-Modify-Write, Hidden
Refresh, Fast Page Mode Read, Fast Page Mode
Read-Modify-Write.
Hi-Z Output State: Early Write, RAS-only Refresh,
. Fast Page Mode Write, CAS-only cycle..
Indeterminate Output State: Delayed Write (tewD or
tRWD are not met).
Refresh
The data in the 21014 is stored on a tiny capacitor
within each memory cell. Due to leakage the data
may leak off after a period of time. To maintain data
integrity it is necessary to refresh each of the rows
every 8 ms. Either a burst refresh or distributed refresh may be used. There are several ways to accomplish this.
RAS-On/y Refresh: This is the most common method for performing refresh. It is performed by strobing
in a row address with RAS while CAS remains high.
.This cycle must be repeated for each of the 512 row
addresses, (Ao-As).
CAS-before-RAS Refresh Counter
Test Cycle
A special timing sequence· using the CAS-beforeRAS refresh counter test cycle provides a convenient method of verifying the functionality of the
CAS-before-RAS refresh activated circuitry. The cycle begins as a CAS-before-RAS refresh operation.
Then, if CAS is brought high and then low again
while RAS is held low, the read and write operations
are enabled. In this mode, the row address bits Ao
through As are supplied by the on-chip refresh counter.
Fast Page Mode
Fast page mode provides high speed read, write or
read-modify-write access to all memory cells within a
selected row. These cycles may be mixed in any
order. A fast page mode cycle begins with a normal
cycle. Then, while RAS is kept low to maintain the
row address, CAS is cycled to strobe in additional
column addresses. This eliminates the time required
to set up and strobe sequential row addresses for
the same page.
CAS-before-RAS Refresh: The 21014 has CAS-before-RAS on-chip refresh capability that eliminates
the need for external refresh addresses. If CAS is
held low for the specified set up time (tcSR) before
RAS goes low, the on-chip refresh circuitry is enabled. An internal refresh operation automatically
occurs. The refresh address is supplied by the onchip refresh address counter which is then internally
incremented in preparation for the next CAS-beforeRAS refresh cycle.
Power-Up
If RAS = VSS during power-up, the 21014 could begin an active cycle. This condition results in higher
than necessary current demands from the power
supply during power-up. It is recommended that
RAS and CAS track with Vee during power-up or be
held at a valid VIH in order to minimize the power-up
current.
Hidden Refresh: A hidden refresh cycle may be performed while maintaining the latest valid data at the
output by extending the CAS active time and cycling
RAS. The 21014 hidden refresh cycle is actually a
CAS-before-RAS refresh cycle within an extended
read cycle. The refresh row address is provided by
the on-chip refresh address counter.
An initial pause of 200 ,""S is required after power-up
followed by 8 initialization cycles before proper device operation is assured. Eight initialization cycles
are also required after any. 8 ms period in which
there are no RAS cycles. An initialization cycle is any
cycle in which RAS is cycled.
Other Refresh Methods: It is also possible to refresh
the 21014 by using read, write or read-modify-write
cycles. Whenever a row is accessed, all the cells in
that row are automatically refreshed. There are certain applications in which it might be advantageous
to perform refresh in this manner but in general
RAS-only or CAS-before-RAS refresh is the preferred method.
Termination
The lines from the TTL driver circuits to the 21014
inputs act like unterminated transmi~sion lines resulting in significant positive and negative overshoots at the inputs. To minimize overshoot it is advisable to terminate the input lines and to keep them
as short as possible. Although either series or parallel termination may be used, series termination is
3-66
inter
21014
generally recommended since it is simple and draws
no additional power. It consists of a resistor in series
with the input line placed close to the 21014 input
pin. The optimum value depends on the board layout. It must be determined experimentally and is
usually in the range of 20n to 40n.
Decoupling
The importance of proper decoupling can not be
overemphasized. Excessive transient noise or voltage droop on the Vee line can cause loss of data
integrity (soft errors). It is recommended that the total combined voltage changes over time in the Vee
to Vss voltage (measured at the device pins) should
not exceed 500 mV.
Board Layout
It is important to layout the power and ground lines
on memory boards in such a way that switching transient effects are minimized. The recommended
methods are gridded power and ground lines or separate power and ground planes. The power and
ground lines act like transmission lines to the high
frequency transients generated by DRAMs. The impedance is minimized if all the power supply traces
to all the DRAMs run both horizontally and vertically
and are connected at each intersection or better yet
if power and ground planes are used.
A high frequency 0.3 /JoF ceramic decoupling capacitor should be connected between the Vee and
ground pins of each 21014 using the shortest possible traces. These capacitors act as a low impedance
shunt for the high frequency switching transients
generated by the 21014 and they supply much of the
current used by the 21014 during cycling.
Address and control lines should be as short as pos, sible to avoid skew. In boards with many DRAMs
these lines should fan out from a central point like a
fork or comb rather than being connected in a serpentine pattern. Also the control logic should be '
centrally located on large memory boards to facilitate the shortest possible address and control lines
to all the DRAMs.
In addition, a large tantalum capacitor with a value of
47 /JoF to 100 /JoF should be used for bulk decoupling
to recharge the 0.3 /JoF capacitors between cycles,
thereby reducing power line droop. The bulk decoupiing capacitor should be placed near the point
where the power traces meet the power grid or power plane. Even better results may be achieved by
distributing more than one tantalum capacitor
around the memory array.
PACKAGE DIMENSIONS
20-LEAD PLASTIC DUAL-IN-LiNE PACKAGE Units: Inches (millimeters)
~
,rn
'.~".'"
J[!J
~: ::::::: ~IJ
~
~_100
J
~~
0.012(0.30)
0.962 (24.43)
0.972 (24.69)
l
0.02~fH·50
~
"M(,~J~J
J
~ff::::~::
Jl
0.145(3.68)
0.100 (2.54)1
TYP
J---l1
0.047(1.19)
0.059 (1.49)
Mi
1 0.032 0.81
0.040 1.02
J-
0.016 0.41
0.023 0.58
240512-17
3-67
21014
PACKAGE DIMENSIONS (Continued)
20-LEAD PLASTIC SMALL OUTLINE J-LEAD Units: Inches (millimeters)
0.670 17.02
0.680 17.27
0.016 0.41
0.020 0.51
240512-18
20-PIN PLASTIC ZIGZAG-IN-L1NE PACKAGE
r
Units: Inches (millimeters)
1-------- 1.025~26.041 - - - - - - - 1
1~~~I"""""""'.035l26"""""""'.29}~"""""""'·Ii--TJ
r
~~~~~~~~
0
lNDEX
I
0.018 (0.46)
0.022 (0.56)
J L_
0.325 (8.26)
0.335 (8.51)
-r--I=--!
f
I0'"~~
~
ci
-l-
t!~I--'_"~l
I
I
q
I+- 0.050 (1.27)
.., 3!0 .....
0'"
....
TYP
0.113 (2.87)
0.123 (3.12)
0.012 (0.30)
_
0.100 (2.54)
TYP
ci
240512-19
3-68
21040
4,194,304 x 1-BIT DYNAMIC RAM
WITH PAGE MODE
• Performance Range
21040-08
21040-10
21040-12
tRAC
80
100
120
ns .
tCAC
20
25
30
ns
tRC
160
190
220
ns
Unlls
• Common I/O Using "Early Write"
Operation
• CAS before RAS refresh, RAS-only
Refresh, Hidden Refresh and Test
Mode Capability
•
• Single 5V ± 10% Power Supply
• Fast Page Mode Operation
1024 Cycles/16mS Refresh
•
Available in Plastic SOJ and ZIP
package types
GENERAL INFORMATION
Intel 21040 is a CMOS high speed 4,194,304 x 1-bit dynamic RAM optimized for high performance applications such as mainframes, graphics and microprocessor systems.
21040 features Fast Page Mode operation which allow high speed random access of memory cells within the
same row.
CAS before RAS refresh capability provides on-chip auto refresh as an alternative to RAS only refresh. All
Inputs, Output and clocks are fully CMOS and TTL compatible.
Multiplexed address inputs permit the 21040 device to be packaged in a standard 20/26 pin plastic SOJ and
20 pin plastic ZIP.
.
Functional Block Diagram
Pin Configuration
Plastic SOJ
Plastic ZIP
RAs-W------,
CAs
ii
-rt-,..,........
T21040
Z21040
REFRESH CONTROL &:
ADDRESS COUNTER
COLUMN DECODER
SENSE AIoIPS &r: 10
AO
IiIEWORY ARRAY
4,194,304 CELLS
......-vcc
+--Vss
240810-2
Pin Name
A,O
AQ-Al0
240810-1
3-69
240810-3
Pin Function
Address Inputs
0
Data In
Q
Data Out
IN
Read/Write Input
RAS
Row Address Strobe
CAS
Column Address Strobe
Vee
Power (+5V)
Vss
N.C.
Ground
No connection
September 1990
Order Number: 2408111-001
inter
21040
ABSOLUTE MAXIMUM RATINGS'
PARAMETER
VALUE
UNITS
Voltage on any pin relative to Vss
Voltage on power supply relative to Vss
Storage Temperature
Operating Temperature
Power Dissipation
Short Circuit Output Current
-1 to +7.0
-1to+7.0
-55 to + 150
Ot070
SOO
50
V
V
°C
°C
mW
mA
SYMBOL
Yin, Vout
Vee
Tstg
Topr
Pd
los
'Permanent damage may occur If "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional Operation should be restricted to the conditions as defined in the operational sections of the Data Sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS (Voltage referenced to Vss, Ta = O°C to 70°C)
SYMBOL
VCC
VSS
VIH
VIL
PARAMETER
MIN
TYP
MAX
UNIT
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
4.5
0
2.4
--1.0
5.0
0
5.5
0
S.5
0.8
V
V
V
V
-
CAPACITANCE (Ta = 25°C)
SYMBOL
Cin1
Cin2
Cout
PARAMETER
MIN
MAX
UNIT
Input Capacitance (AO - A 10, Din)
Input Capacitance (RAS, CAS, WRITE)
Output Capacitance (Dout)
-
5
7
7
pF
pF
pF
-
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
SYMBOL
ICC1
PARAMETER
Operating Current'
(RAS and CAS cycling
@
tRC
=
min)
ICC2
Standby Current
(TTL Power Supply Current)
ICC3
RAS Only Refresh Current'
(CAS = VIH, RAS Cycling @ tRC
=
min)
Fast Page Mode Current'
(RAS = VIL, CAS Cycling
=
min)
ICC4
@
tpc
ICC5
Standby Current
(CMOS Power Supply Current)
ICCS
CAS-before-RAS Refresh Current'
(RAS and CAS Cycl!ng @ tRC = min)
SPEED
MIN
MAX
UNIT
-08
-10
-12
-
100
85
70
mA
mA
mA
-08
-10
-12
-08
-10
-12
-
2
mA
-
-
100
85
70
mA
mA
mA
-
SO
50
40
mA
mA
mA
1
mA
100
85
70
mA
mA
mA
-
3-70
-08
-10
-12
-
-
inter
21040
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted) (Continued)
SYMBOL'
PARAMETER
SPEED
MIN
MAX
UNIT
-
-
5
mA
-10
10
uA
ICC7
Standby Current
(RAS = VIH, CAS
III
Input leakage Current
(Any Input 0 ,,; Vin ,,; 6.5 Volts
all other Pins = 0 Volts)
IOl
Output leakage Current
(Data out is disabled and
o ,,; Vout ,,; 5.5 V)
-
-10
10
uA
VOH
Output High Voltage level
(IOH = -5mA)
-
2.4
-
V
VOL
Output low Voltage level
(IOl = 4.2 mA)
-
-
0.4
V
=
Vll, DOUT = Enable)
·Note:
ICCt, ICC3, ICC4 and ICC6 are dependant on output loading and cycle rates. Specified values are obtained with the output
open. ICC is specified as average current.
AC CHARACTERISTICS (See Notes 1, 2) (Ta
=
O·C to 70·, VCC
21040-08
SYMBOL
PARAMETER
Min
Max
=
5V ± 10%)
21040-10
Min
Max
21040-12
Min
Max
UNITS
Notes
tREF
Time between Refresh
tRC
Random R/W Cycle Time
150
180
220
ns
tRWC
RMW Cycle Time
175
210
255
ns
tRAC
Access Time From RAS
80
100
120
ns
3,4
tCAC
Access Time From CAS
20
25
30
ns
3,4
tAA
Access Time From Column Address
40
50
60
ns
3,10
tell
CAS to Output in low Z
5
ns'
3
16
16
5
16
5
ms
tQFF
Output Buffer Turn-Off Delay Time
0
15
0
20
0
30
ns
6
IT
Transition Time
3
50
3
56
3
50
ns
2
tRP
RAS Precharge Time
60
tRAS
RAS Pulse Width
80
tRSH
RAS Hold Time
20
90
70
10K
100
10K
25
5
120
ns
10K
10
ns
' ns
30
teRP
CAS to RAS Precharge Time
tRCD
RAS to CAS Delay Time
20
60
25
75
25
10
90
ns
ns
teAS
CAS Pulse Width
20
10K
25
10K
30
10K
ns
teSH
CAS Hold Time
80
100
120
tePN
CAS Precharge Time
35
40
45
ns
tASR
Row Address Set-up Time
0
0
0
ns
10
15
20
ns
0
0
0
ns
ns
tRAH
Row Address Hold Time
tASC
Column Address Set-up Time
teAH
Column Address Hold Time
15
20
25
ns
tAR
Column Address Time referenced to RAS
60
75
90
ns
3-71
4,5
inter
21040
AC CHARACTERISTICS (See Notes 1, 2) (Ta
=
O°C to 70°, VCC
21040-08
SYMBOL
PARAMETER
=
5V
± 10%) (Continued)
21040-10
21040-12
Min
Max
Min
Max
Min
Max
40
20
50
25
60
UNITS
Notes
tRAD
RAS to Column Address Delay Time
15
tRAL
Column Address to RAS Lead Time
40
50
60
ns
tRCS
Read Command Set-Up Time
0
0
0
ns
tRRH
Read Command Hold Time referenced to
RAS
0
0
0
ns
8
tRCH
Read Command Hold Time referenced to
CAS
0
0
0
ns
8
twcs
Write Command Set-Up Time
0
0
0
ns
7
twCH
Write Command Hold Time
15
20
25
ns
twCR
Write Command Hold referenced to RAS
60
75
90
ns
twP
Write Command Pulse Width
15
20
25
ns
tRWL
Write Command to RAS Lead Time
20
25
30
ns
tCWL
Write Command to CAS Lead Time
20
25
30
ns
tDS
Data Set-up Time
0
0
0
ns
9
tDH
Data Hold Time
15
20
25
ns
9
tDHR
Data-In Hold Time referenced to RAS .
60
75
90
ns
tRWD
RAS to WRITE Delay Time
80
100
120
ns
7
tCWD
CAS to WRITE Delay Time
20
25
30
ns
7
tAWD
Column Address to WRITE Delay Time
40
50
60
ns
7
tRPC
RAS Precharge Time to CAS Active Time
tGSR
CAS Set-up Time for CAS before RAS
ns
0
0
0
ns
10
10
10
ns
refresh
tCHR
CAS Hold Time for CAS before RAS
refresh
30
30
30
ns
tCPT
CAS Precharge Time (Refresh Counter
Test)
40
50
60
ns
twTS
Write Command Set-up Time (Test Mode
in)
10
10
10
ns
IWTH
Write Command Hold Time (Test Mode in)
10
10
10
ns
twRP
WRITE to RAS Precharge Time (CAS
before RAS Cycle)
10
10
10
ns
twRH
WRITE to RAS Hold Time
RASCycle)
10
10
10
ns
(CAS before
3-72
10
21040
AC CHARACTERISTICS (FAST PAGE MODE)
(See Notes 1, 2) (Ta = O·C to 70·, VCC = 5V
±
10%) (Continued)
21040-08
SYMBOL
PARAMETER
Min
Max
21040-10
Min'
Max
21040-12
Min
tpc
Fast Page Mode Cycle Time
55
60
70
tpRWC
Fast Page Mode RMW Cycle Time
80
90
105
tCPA
Access Time from CAS Precharge
tcp
Fast Page Mode CAS Precharge Time
10
tRASP
RAS Pulse Width (Fast Page Mode)
80
50
55
10
200K
200K
±
120
UNITS
Notes
ns
ns
60
ns
200K
ns
15
100
AC CHARACTERISTICS (TEST MODE)(Ta = 0·Ct070·, VCC = 5V
Max
ns
10%)
(Note 11)
SYMBOL
PARAMETER
21040-08
Min
Max
21040-10
Min
Max
21040-12
Min
UNITS
Notes
Max
IRC
Random R/W Cycle Time
155
185
225
ns
tRWC
RMW Cycle Time
180
215
260
ns
tpc
Fast Page Mode Cycle Time
60
65
75
ns
PRWC
Fast Page Mode RMW Cycle Time
85
95
110
ns
tRAC
Access Time From RAS
85
105
125
ns
3,4
tCAC
Access Time From CAS
25
30
35
ns
3,4
tAA
Access Time From Column Address
45
55
65
ns
3,10
tCPA
Access Time From CAS
55
60
65
ns
tRASP
RAS Pulse Width (Fast Page Mode)
85
200K
105
200K
125
200K
I1s
tRAS
RAS Pulse Width
85
10K
105
10K
125
10K
tRSH
RAS Hold Time
25
30
35
ns
ns
!CAS
CAS Pulse Width
25
tCSH
CAS Hold Time
85
105
125
ns
tRAL
Column Address To Lead Time
45
55
65
ns
10K
30
10K
35
10K
ns
tRWD
RAS to WRITE Delay Time
85
105
125
ns
7
!CWO
CAS to WRITE Delay Time
25
30
35
ns
7
tAWD
Column Address to WRITE Delay Time
45
55
65
ns
7
NOTES:
1. An initial pause of 200 Microseconds is required after power-up followed by an 8 RAS-only cycles before proper device
operation is achieved.
'
2. Vih (min) and Vii (max) are reference levels for measuring timing of input signals. Also, transition times are measured
between Vih (min) and Vii (max) and are assumed to be 5 ns for all inputs.
3. Measured with a load equivalent to two 2 TTL loads and 100 pF.
4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point
only; if tRCD is greater than the specified tRCD (max) limit, access time is controlled exclusively by tCAC.
5. Assumes that tRCD "' tRCD (max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to output
,
voltage levels.
7. twCS, two, tRWD, and tAWD are non restrictive operating parameters. They are included in the Data Sheet as Electrical
characteristics only. If twcs "' twcs (min), the cycle is an early write cycle and data out pin will remain open circuit through
the entire cycle; If tRWD "' tRWD (min), !CWO", tCWD (min) and tAWD "' tAWD (min), the cycle is a read-write cycle and
data out will contain data read from the selected cell; If neither of the above set of conditions is satisfied, the condition of
the data out (at access time) is indeterminate.
'
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to CAS leading edge in early write cycles and to the Vii leading edge in read-write
cycles.
10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point
only; if tRAD is greater than the specified tRAD (max) limit, access time is controlled by lAA.
11. These specifications are applicable in the test mode.'
.
3-73
21040
READ CYCLE
Timing Waveforms
~------------------------tRC----------~------------~
~---------------tRAS---------------.j
1-------tcSH-------.j
V1H -
-~~J""""':rI_l,....,,....,....,....,...,..,.,.~--+-----------+_--~~,....,,....,
WRITE
~-----------t~c--------_r~.j
VOH DOUT
VALID DATA
- - - - - - - OPEN
VOL -
~
: "H"or"L"
240810-4
3-74
inter
21040
WRITE CYCLE (EARLY WRITE)
~-----------------------tRC------------------------~
~---------------tRAS---------------~
~-------tRCD--------+-----tRSH----l
~-------t~H-------+----------~
VIH -
--Ir--!-+--------+_
VIH -
""""Ir-l.....,....,+07""'7'-r..,....,..""!I.
VIH -
""''''''''''''"'''7'''''''''''''''''''''''''''''''''''''' iI------' _.,....-.r-l"""....,....,.-r..,....,....,....,...,.....,
CAS
AO-AIO
WRITE
VOH Dour
- - - - - - - - - - - - - - - - - - - - OPEN - - - - - - - - - - VOL -
~
:"H"or"L"
240810-5
3-75
inter
21040
READ-WRITE CYCLE
t RWC
t RAS
V1H RAS
V1L t RSH
t RCD
tCAS
V1H CAS
V1L -
V1H WRITE
V1L -
V1H -
DjN
V1L -
VOH -
DOUT
VOL -
-------
I7lLI :
"H" or "L"
240810-6
3-76
inter
21040
FAST PAGE MODE READ CYCLE
IRASP
V1H -
-----------1
I--IR~
L
~
RAS
V1L -
i - - - Ipc - - -
ICSH
i--IRSH-
~
~
ICAS
~IRCD
i-Icp1-
V1H -
~ ,-.,l
CAS
VIL-J
~ ~~
I
i-ICp'"
r---,
~S,
~ ~~
IAR
IASR
AONAIO
V1H-W
V1L -
WRITE :::
I--
~
I,IRAH,
ROW
~
~
leAH
~
0
COL
=I 111/117
lASe
~
~
COL
KlIIIIIIII
VIII
i--IM
v
COL
I~CA~
r----
i - - - - - IRAC
OH DOUT VOL _
~
I'~C'
c-IAA-i--\cPA
rh
-----------(V
_ 't
~LZ
VALID
DATA
~
~
I'~C'
i--IAA f - - -ICPA-f---
.-I. . _'fIX
'J.//-
"'---H'J'"
~
_
VALID I L -
~ DATA r -
t' Ii"i:::"
~
.£LZ
_
VALID
DATA
it'
I~
lorr
r.£LZ
l?Z2I :"H" or "L"
240810-7
3-77
inter
21040
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
DIN
V IH -
--,-r-r....,-lT~,...,\.~----~,rT\.Jr---Il~"'Jr---Il~-r-r-r-r-r-'7"'"r-T
VIL -
..."-""""""'-IT""...._-'
1'----""1
VOH -
DOUT
- - - - - - - - - - - - - - - - - - OPEN - - - - - - - - - - - - - VOL -
~
: "H"or"L"
240810-8
3-78
inter
21040
FAST PAGE MODE READ-WRITE CYCLE
t RASP
t=-tR=1
1"
~
tCSH
1~CRP
i---tRCD
I-tcp'"
tCAS-
-"",i-""- - tASC
?lZ)
ROW
@
~
~
-
i-tAwD-
,
tos
1-
1+
~tDHtVALID
DATA
~
-
- tAA t RAC
Dour
VOL -
tCWL;'"
!--tAWD
~
~
tos
'III I) "'VAUo"" :JIIIIIIII
~
tCLl
--
~
,.:::::0
tCAC
r-tAA- tCPAVALID
DATA
~
~
.~
F
-tCLl
I~
- -:
tClZ
-
---
-:.~
L VALID
1111l,)r--DATA
-~
VOH -
~
\-~
!---tRWD
IIIII 'lilli/Ii I:
~
tNt
/
II IIIIIIIII
COLUMN
tCWD
f-,tAWD--
~~
tDS -
~
~/
COLUMN
;::;
-
- tRAl-
tASC
..:=.
I' tCAH
tcw
tRCS -
fJ
-
F
COLUMN
I
- tCAS--
,---,
tASC
~ _ tcw~
i--- t RAD-
- tRSH-
- tcp'"
i--tCAS-
~
\\
J
i---tpRWC-
rr-
)---1~
I"'-"
tCAC
I--tAA
i---tcPAVALID
DATA
~
~
-......
~ I/}!
-
VALID
DATA
~
: "H" Or "L"
240B10-9
3-79
21040
RAS ONLY REFRESH CYCLE
t----------tRc'----------t
1-------tRAs---------i
V1H -
CAS
-
- + 1 - - - - - - - - - - - - - - -.......-.....,..---
......
V1L -
.
~1z
ROW
VOH
.DOUT V
OL
7OlZOOZZOOO0OZ0
-----------OPEN ~-----------
~
: "H" or"L"
240810-10'
NOTE:
WRITE = "H" or "L", A 10 = "H" or "L"
3-80
inter
21040
CAS BEFORE RAS REFRESH CYCLE
1-----------tRc----------i
1------tRAs-----+i
V IL
_ __
VIH -
'"""'l,....,..,.-r-r-r-'7""'ir----.,..,.-.,-.,....,....,....,""'""l""'""l,...-:r-r-r-r-r-r--r--r--r--r--r"'7
WRITE
VOH------"""'\I
DOUT
VOL -
1)--------------- OPEN - - - - - - - - - -
_ _ _ _ _-'1
I?l2I :
"H" or ilL"
240810-11
NOTE:
AO - A10="H"or"L"
3-81
inter
21040
HIDDEN REFRESH CYCLE (READ)
1--------tRc------.j
VOH COUl
VOL -
-----------+
10
10
""""
"'6r-.
'",,;
,-
\..IY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x..:
::::E
N
....'"en
Ig
Ig
I
I
~
ci
+I
:!
N
10
0
0
~
~
...,
~
~
'+'
L--
10
£I'~
i.
'xv., s.,'oz
Figure 3. Outline Drawing
3·92
"ot
10
N
intJ
202569
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative
to vss (VIN, VOUT) ........•..... -1V to
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of, development. The specifications are subject to
change without notice.
+ 7.0V
Voltage on Power Supply
Relative to Vss (Vee> ........... -1V to + 7.0V
Storage Temperature (TSTG) .... - 55DC to + 125DC
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the· "Operating Conditions"
may affect device reliability.
Soldering Temperature. Time
(Tsolder) ....................... 260DC • 10 Sec
Power Dissipation (P d) ....•..........•....... 9W
Short Circuit Output
Current (lOUT) .......•.............. _... 50 rnA
RECOMMENDED OPERATING CONDITIONS
(Voltage Referenced to Vss. TA = ODC to 70DC)
Parameter
Min
Typ
Max
Units
Vee
Supply Voltage
4.5
5.0
5.5
V
Vss
Ground.
VIH
Input High Voltage
2.4
VIL
Input Low Voltage
-1.0
Symbol
CAPACITANCE
Symbol
0
0
V
0
-.
-
Vee
+
1
0.8
V
V
(TA = 25D C)
Parameter
Cj(A)
Input Capacitance (AO-A9)
Min
Max
Units
75
pF
Cdq
1/0 Capacitance
20
pF
Cj(W)
Input Capacitance, Write Control Input
80
pF
Cj (RAS)
Input Capacitance, RAS Input
100
pF
Cj(CAS)
Input Capacitance, CAS Input
100
pF
Cj(CASP)
Input Capacitance, CASP Input
20
pF
Cj (DP)
Input Capacitance
15
pF
Co (QP)
Output Capacitance
15
pF
3-93
202569
D.C. AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
ICC1
ICC2
Standby Current
1
-I
Ice3
@
tRC
=
=
RAS
RAS
=
CAS
=
=
Min
Max
Units
205
175
rnA
VIH
11
rnA
Vec -0.2V
9
rnA
-08
-10
Min)
CAS
RAS Only Refresh Current
= VIH. RAS Cycling @ tRC
Min)
-08
-10
195
160
rnA
=
Fast Page Mode Current
(RAS = VIL. CAS Cycling
Min)
-08
-10
165
135
rnA
=
-08
-10
205
175
rnA
(CAS
ICC4
Speed
Parameter
Operating Current
(RAS and CAS Cycling
@
tpc
ICC6
CAS-before-RAS Refresh Current
(RAS and CAS Cycling @ tRC = Min)
IlL
Input Current
(Any Input 0 ~ VIN ~ 6.5V
All Other Pins = OV)
-90
90
,..,A
loz
Off State Output Current
(Data Out is Disabled and
~ VOUT ~ 5.5V)
-30
30
p,A
VOH
Output High Voltage Level
(IOH = -5 rnA)
2.4
Vce
V
VOL
Output Low Voltage Level
(IOL = 4.2 rnA)
0
0.4
V
o
NOTE:
ICC1. Icca. ICC4 and Ices are dependent on output loading and cycle rates. Specified values are obtained with the output
open. Icc is specified as average current.
3-94
inter
202569
A.C. CHARACTERISTICS(1,2) (TA =
Symbol
Parameter
0·Cto70·C, Vcc
2D2569-08
Min
Max
=
5V ±10%)
2D2569-10
Min
Notes
ns
4, 7
tRAC
Access Time from RAS
tCAC
Acces Time from CAS
40
50
ns
5, 7
tCAA
Access Time from
Column Address
45
50
ns
6, 7
tCPA
Access Time from CAS
Precharge
45
55
ns
7, 14
tCLZ
Output Low Impedance
Time from CAS Low
5
ns
7
tOFF
Output Disable Time
after CAS High
0
25
3
50
tREF
Refresh Cycle Time
tT
Transition Time
80
Units
Mas
100
5
0
30
ns
4
ms
3
50
ns
4
tRP
RAS High Pulse Width
60
80
ns
tCRP
CAS to RAS Precharge
Time
10
15
ns
tRCD
RAS to CAS Delay Time
20
tCPN
CAS High Pulse Width
20
tRAD
Column Addres Delay
Time from RAS Low
20
tASR
Row Address Setup
Time before RAS Low
0
0
ns
tASC
Column Address Time
before CAS Low
0
0
ns
tRAH
Row Address Hold Time
after RAS LOW
15
15
ns
tCAH
Column Address Hold Time
after CAS Low or W Low
15
20
ns
3-95
40
25
50
25
40
20
ns
9,10
ns
50
ns
11
202569
A.C. CHARACTERISTICS(1, 2) (Continued) (TA =
O°C to 70°C, VCC
=
5V ± 10%)"
REAO ANO REFRESH CYCLES
Symbol
Parameter
202569-08
Min
202569·10
Max
Min
Units
Notes
Max
tRC
Read Cycle Time
150
tRAS
RAS Low Pulse Width
80
10K
100
10K
ns
teAS
CAS Low Pulse Width
40
10K
50
10K
ns
tCSH
CAS Hold Time
after RAS Low
80
100
ns
tRSH
RAS Hold Time after '
CAS Low
40
50
ns
tRCS
Read Setup Time
before CAS Low
0
0
ns
tRCH
Read Hold Time
after CAS High
0
0
ns
12
tRRH
Read Hold Time
after RAS High
0
0
ns
12
tRAL
Column Address to
RAS Setup Time
45
55
ns
tRPC
Precharge to CAS
Active Time
10
10
ns
190
\
ns
CAS BEFORE RAS REFRESH CYCLE
Symbol
Parameter
202569-08
Max
Min
202569·10
Min
Units
Max
teSR
CAS Set Up Time for CAS
before RAS Refresh
10
10
ns
tCHR
CAS Hold Time for CAS
before RAS Refresh
30
30
ns
tRPC
Precharge to CAS
Active Time
0
0
ns
3-96
Notes
infef
202569
A.C. CHARACTERISTICS (Continued) (TA =
O·C to 70·C, Vee
=
5V ± 10%)
WRITE CYCLE (Early'Write)
Symbol
Parameter
202569-08
Min
202569-10
Max
Min
10K
160
Units
twe
Write Cycle Time
160
tRAS
RAS Low Pulse Width
130
190
tDS
Data Setup Time
0
0
ns
tDH
Data Hold Time
after CAS Low
20
20
ns
teAS
CAS Low Pulse Width
20
tesH
CAS Hold Time
after RAS Low
80
100
ns
tRSH
RAS Hold Time
after CAS Low
20
25
ns
twes
Write Setup Time
before CAS Low
0
0
ns
tweH
Write Hold Time
after CAS Low
15
20
ns
twp
Write Pulse Width
15
20
ns
10K
3-97
25
Notes
Max
ns
10K
10
ns
ns
13
inter
202569
FAST PAGE MODE CYCLE (Read, Early Write cycles)
Symbol
Parameter
202569-08
Min
Max
202569-10
Mi':'l
Units
tpc
Fast Page Mode
Cycle Time
75
90
tRAS
RAS Low Pulse Width
for Read, Write Cycle
130
10K
160
10K
,ns
teAS
CAS Low Pulse Width,
for Read Cycle
20
10K
25
10K
ns
tep
CAS High Pulse Width
25
30
Notes
Max
ns
ns
NOTES:
1. An initial pause of 500 J.Ls is required after power-up followed by any 8 RAS-only cycles before proper device operation is
achieved.
2. A.C. Characteristics assume tT = 5 ns.
3. VIH(min) and Vldmax) are reference levels for measuring timing of input signals. Also, transition times are measured
between VIH (min) and VIL(max).
4. Assumes that tRCO ,;: tRco(max), tRAO ,;: tRAo(max). If tRCO (or tRAO) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCO (or tRAO) exceeds the value shown.
'
5. If tRCO :<: tRCO(max). tRAO :<: tRAO(max). and tASC :<: tM - tCAC - tT. access time is tCAC.
6. If tRAO ;;, tRAO(max) and tASC ,;: tM - tCAC - tT. access time is tM'
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. tOFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCO(max) limit insures that tRAc(max) can be met. tRco(max) is specified as a reference point only;
if tRCO is greater than the specified tRCO(max) limit. access time is controlled exclusively by tCAC or tM'
10. tRCO(min) = tRAH(min) + 2tT + tASc(min).
11. Operation, within the tRAo(max) limit insures that tRAc(max) can be met. tRAO (max) is specified as a reference point
only; if tRAO is greater than the specified tRAo(max) limit. access time is exclusively controlled by tCAC or tM'
12. Either tRRH or tRCH must be specified for a read cycle.
13. twCS. tCWO. tRWO and tAWO are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
14. tCPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").
3-98
202569
READ CYCLE
VIH -
VIH-~~~~~~~~~~~----~--------------~----~~~~
WRITE
VOH -
DOUT
VOL -
----------
~
: "HI! or ilL"
240838-4
3-99
2D2569
EARLY WRITE CYCLE
VOH -
Dour
VOL -
- - - - - - - - - - - - - OPEN - - - - - - - - - - - - -
~
:"H"or"L"
240838-5
3-100
inter
202569
RAS ONLY REFRESH CYCLE
VOH DOUT
- - - - - - - - - - - - OPEN - - - - - - - - - - - - VOL -
~ : "H"or"L"
240838-6
CAS BEFORE RAS REFRESH CYCLE
VOH DOUT
VOL -
1)------- OPEN
_ _ _ _-'I
-------------
~
: "H"or"L"
240838-7
3-101
inter
202569
HIDDEN REFRESH CYCLE (READ)
VOH -
Dour
VOL -
---------+
60
70
80
Access Time from CAS (teAC>
20
20
20
25
ns
Read Cycle Time (tRC>
125
140
160
190
ns
1,048,576 X 9-Bit Organization
Industry Standard Pin-Out in a 30-Pin
Single In-Line Memory Module (SIMM)
Common I/O Using "Early Write"
Single 5V
+ 10% Power Supply
512 Refresh Cycles every 8 ms
•
•
•
Separate CAS Control for Eight
Common Data-In and Data-Out Lines
Separate CAS (CAS8) Control for One
Separate Pair of Data-In and Data-Out
Lines
TTL Compatible Inputs and Outputs
The 21019 is a 1,048,576 words by 9-bit memory module consisting of industry standard 1 Meg x 1 dynamic
RAMs in SOJ package.
The 20 address bits are entered 10 bits at a time using RAS to latch the first 10 bits and CAS to control the
latter 10 bits. The ninth bit 08, 08 is generally used for parity and is controlled by CAS8.
The common I/O feature requires the use of an early write cycle to prevent data contention on DO lines.
-0
vee
CAS
000
AO
Al
001
A2
A3
vss
002
A4
AS
003
A6
A7
004
A8
A9
N.C.
DOS
Vi
(1) D
(2) D
(3) D
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
D
D
D
D
D
D
D
D
D
D
D
D
D
D
~18) D
19) D
20) D
Pin Names
(21)
vss (22)
006 (23)
N.C. (24) D
007 (25)
08
(26)
RAS (27)
CAS8 (28)
08
(29)
vee (30)
~I
~I
~I
AO-A9
Address Inputs
001-007
Data Inputs/Outputs
08
Data Input
08
Data Output
RAS
Row Address Strobe
CAS-CAS8
Column Address Strobe
W
R/W Input
Vee
Power (+5V)
Vss
Ground
N.C.
No Connection
0
240721-1
Figure 1. Pin Assignment
3-107
November 1990
Order Number: 240721-002
infef
21019
000
1
oW
0
r-l\
~
f-c
r-c
1
~
f-c
r-c
~
RAS
I-<
f-c
r-
WRITE
oW
1
DOS
I
l....'\
3
RAS
~
CAS
~f-
WRITE
D03
r-c
oj
DOS
1
~
I-<
f-c
[
LA
~
RAS
WRITE
t-- D
~
~
r-
f-c
r-c
oW
AONA9
RAS
CAS
WRITE
t-- D
AONA9
HI-
WRITE
HI-
~ CAS
r-
RAS
CAS
t-- 0
L..t-,
AONA9
-D
AONA9
Hr
HID02
oW
0
r-l\
CAS
t-- D
~
1
AONA9
Hr
D01
004
oj
AONA9
RAS
f-<
CAS
f-c
WRITE
HI-
oW
D07
1
t-- D
~
AONA9
RAS
~
CAS
I-
WRITE
~
f-c
f-c
~~
oW
AONA9
RAS
CAS
WRITE
Hr
D8
I-- D
LJ\,
i-...y
RAS
CAS
RAS
CASs
CAS
WRITE
O~ 08
AONA9
WRITE
f-1r
Vee
Vss
240721-2
Figure 2. Block Diagram
3-108
inter
21019
'"cio
'"
~
H~ ,... ...."
.--
E
E
.s
r-
'xr-.
o
'"'"..;
O~
nnnnn
::!
-
nnnnn
x
<{
~
'"o '"ai
'" ,...
CQ
'"'"
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
'"ci
'"
'ot
N
'"
'ot
.... N'"
, ,t\.
-:::
'+'
'---
i.
·XVri
"'9
sv·oz
Figure 3. Outline Drawing
3-109
21019
ABSOLUTE MAXIMUM RATINGS*
. NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Voltage on Any Pin Relative
to vss (VIN' VOUT) .............. -1V to + 7.0V
Voltage on Power Supply
RelativetoVss(Vec) ........... -1Vto +7.0V
• WARNING: Stressing (he device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Storage Temperature (TSTG) .... - 55°C to + 125°C
'. Soldering Temperature. Time
(Tsolder) ....................... 260°C • 10 Sec
Power Dissipation (Pd) ....................... 9W
Short Circuit Output
Current (lOUT)' .... : .................... 50 mA
RECOMMENDED OPERATING CONDITIONS
(Voltage Referenced to Vss. T A
=
O°C to 70°C)
Parameter
Min
Typ
Max
Units
Vee
Supply Voltage
4:5
5.0
5.5
V
Vss
Ground
0
0
0
V
VIH
Input High Voltage
2.4
6.5
V
VIL
Input Low Voltage
-1.0
-
0.8
V
Symbol
CAPACITANCE
Symbol
(TA
=
25°C)
Parameter
Min
Max
Units
75
pF
20
pF
Ci(A)
Input Capacitance (AO-A9)
Cdq
1/0 Capacitance
Cj (W)
Input Capacitance, Write Control Input
80
pF
Cj (RAS)
Input Capacitance, RAS Input
100
pF
Cj (CAS)
. Input Capacitance, CAS Input
,
100
pF
Input Capacitance, CASP Input
20
pF
Cj(DP)
Input Capacitance
15
pF
Co (QP)
Output Capacitance
15
pF
Cj(CASP)
3-110
21019
D.C. AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
ICCl
ICC2
ICC3
ICC4
Speed
Max
Units
810
720
675
540
mA
VIH
18
mA
VCC -0.2V
9
mA
-06
-07
-08
-10
810
720
675
540
mA
-06
-07
-08
-10
630
560
540
450
mA
-06
-07
-08
-10
810
720
675
540
mA
Parameter
Operating Current
(RAS and CAS Cycling
Standby Current
I
I
@
tRC
=
=
RAS
RAS
=
Min)
CAS
CAS
=
=
RAS Only Refresh Current
(CAS = VIH. RAS Cycling @ tRC
=
Min)
Fast Page Mode Current
(RAS = VIL. CAS Cycling
=
Min)
@
tpc
Min
-06
-07
-08
-10
Iccs
CAS·before·RAS Refresh Current
(RAS and CAS Cycling @ tRC = Min)
IlL
Input Current
(Any Input 0 :;:;: VIN :;:;: 6.5V
All Other Pins = OV)
-90
90
/LA
loz
Off State Output Current
(Data Out is Disabled and
0:;:;: VOUT :;:;: 5.5V)
-20
20
/LA
VOH
Output High Voltage Level
(IOH = -5 mAl
2.4
VCC
V
VOL
Output Low Voltage Level
(IOL = 4.2 mAl
0
0.4
V
NOTE:
ICC1. ICC3. ICC4 and ICC6 are dependent on output loading anq cycle rates. Specified values are obtained with the output
open. Icc is specified as average current.
3·111
inter
21019
A.C. CHARACTERISTICS(1, 2) (TA = 0·Cto70·C, Vee = 5V ±10%)
Symbol
Parameter
21019-06
21019-07
;21019-08
21019-10
Min
Min
Min
Min
Max
Max
Max
Units
Notes
Max
tRAC
Access Time from RAS
60
70
80
100
ns
4, 7
tCAC
Acces Time from CAS
20
20
20
25
ns
5, 7
tCAA
Access Time from
Column Address
30
35
45
50
ns
6, 7
tCPA
Access Time from CAS
Precharge
40
45
45
55
ns
7, 14
tClZ
Output Low Impedance
Time from CAS Low
0
20
0
20
5
ns
7
toFF
Output Disable Time
after CAS High
0
20
0
20
0
tREF
Refresh Cycle Time
tr
Transition Time
3
tRP
RAS High Pulse Width
55
60
70
80
ns
tCRP
CAS to RAS Precharge
Time
10
10
10
10
ns
8
8
50
3
50
5
20
0
8
3
50
3
30
ns
8
ms
50
ns
tRCD
RAS to CAS Delay Time
20
tCPN'
CAS High Pulse Width
35
tRAD
Column Address Delay
Time from RAS Low
15
tASR
Row Address Setup
Time before RAS Low
0
tASC
Column Address Time
before CAS Low
0
tRAH
Row Address Hold Time
after RAS LOW
15
15
15
15
ns
tCAH
Column Address Hold Time
after CAS Low or W Low
20
20
20
20
ns
40
20
50
35
30
15
35
0
20
0
3-112
25
60
35
20
40
0
20
0
25
75
35
20
0
9,10
ns
50
0
20
ns
ns
ns
20
ns
11
intJ
21019
A.C. CHARACTERISTICS(1, 2) (Continued) (TA
=
O°Cto 70°C, Vee = 5V ±10%)
READ AND REFRESH CYCLES
Symbol
21019-06
Parameter
Min
Max
21019-07
Min
Max
21019-08
Min
Max
21019-10
Min
Units
Notes
Max
tRC
Read Cycle Time
125
tRAS
RAS Low Pulse Width
60
10K
tCAS
CAS Low Pulse Width
20
10K
tCSH
CAS Hold Time
after RAS Low
60
70
80
100
ns
tRSH
RAS Hold Time after
CAS Low
20
20
20
30
ns
tRCS
Read Setup Time
before CAS Low
0
0
0
0
ns
tRCH
Read Hold Time
after CAS High
0
0
0
0
ns
12
tRRH
Read Hold Time
after RAS High
10
10
10
10
ns
12
tRAL
Column Address to
RAS Setup Time
30
35
45
55
ns
tRPC
Precharge to CAS
Active Time
10
10
10
10
ns
140
10K
20
10K
ns
190
160
70
80
10K
20
10K
100
10K
ns
25
10K
ns
CAS BEFORE RAS REFRESH CYCLE
Symbol.
Parameter
21019-06
21019-07
21019-08
21019-10
Min
Min
Min
Min
Max
Max
Max
Units
Max
tCSR
CAS Set Up Time for CAS
before RAS Refresh
10
10
10
10
ns
tCHR
CAS Hold Time for CAS
before RAS Refresh
15
15
30
30
ns
tRPC
Precharge to CAS
Active Time
0
0
0
0
ns
3-113
Notes
intJ
21019
A.C. CHARACTERISTICS (Continued) (TA =
O·C to 70·C, Vcc
=
5V ± 10%)
WRITE CYCLE (Early Write)
Symbol
Parameter
21019-06
Min
Max
21019-07
Min
Max
21019-08
Min
Max
21019-10
Min
Units
twc
Write Cycle Time
150
160
160
tRAS
RAS Low Pulse Width
120
125
130
tDS
Data Setup Time
0
0
0
0
ns
tDH
Data Hold Time
after CAS Low
20
20
20
20
ns
tCAS
CAS Low Pulse Width
20
tcSH
CAS Hold Time
after RAS Low
60
70
80
100
ns
tRSH
RAS Hold Time
after CAS Low
20
20
20
25
ns
twcs
Write Setup Time
before CAS Low
0
0
0
0
ns
tWCH
Write Hold Time
after CAS Low
15
15
15
20
ns
twp
Write Pulse Width
.15
15
15
20
ns
10K
20
3-114
10K
20
190
10K
10K
160
25
Notes
Max
ns
10K
10
ns
ns
13
inter
21019
FAST PAGE MODE CYCLE (Read, Early Write cycles)
Symbol
Parameter
21019-06
Min
Max
21019-07
Min
Max
21019-08
Min
Max
21019-10
Min
Units
tpc
Fast Page Mode
Cycle Time
45
tRAS
RAS Low Pulse Width
for Read, Write Cycle
120
10K
120
10K
130
10K
160
10K
ns
tCAs
CAS Low Pulse Width
for Read Cycle
20
10K
20
10K
20
10K
25
10K
ns
tcp
CAS High Pulse Width
10
25
10
25
10
25
15
25
ns
50
60
50
Notes
Max
ns
NOTES:
1. An initial pause of 500 ",s is required after power-up followed by any 8 RAS-only cycles before proper device operation is
aChieved.
2. A.C. Characteristics assume tT = 5 ns.
3. VIH(min) and Vldmax) are reference levels for measuring timing of input signals. Also, transition times are measured
between VIH (min) and VIL(max).
4. Assumes that tRCO ,,; tRCO(max), tRAO ,,; tRAo(max). If tRCO (or tRAO) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCO (or tRAO) exceeds the value shown.
5. If tRCO 2: tRCO(max), tRAO 2: tRAO(max), and tASC 2: tM - tCAC - tT, access time is tCAC.
6. If tRAO 2: tRAO(max) and tASC ,,; tM - tCAC - tT, access time is tM.
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. tOFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCO(max) limit insures that tRAc{max) can be met. tRco(max) is specified as a reference point only;
if tRCO is greater than the specified tRCO(max) limit, access time is controlled exclusively by tCAC or tAA.
10. tRco(min) = tRAH(min) + 2tT + tAsc{min).
11. Operation within the tRAO(max) limit insures that tRAc{max) can be met. tRAO (max) is specified as a reference point
only; if tAAO is greater than the specified tAAO(max) limit, access time is exclusively controlled by tCAC or tM.
12. Either tRRH or tACH must be specified for a read cycle.
13. twcs, tcwo, tRWO and tAWO are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
14. tePA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").
3-115
intJ
21019
READ CYCLE
tCSH
VIH CAS
VIL tRAD
VIH AONAg
VIL -
VOH POUT
VOL -
- - - - - - - OPEN
-------(1":
~
VALID DATA
: "H" or "Lu
240721-4
3-116
21019
EARLY WRITE CYCLE
VOH -
VALID DATA
DIN
VOL -
;..,:.'-6."""'''''''''''''''.......'-6.'-6..:.1
VOH -
DOUT
VOL -
- - - - - - - - - - - - - - OPEN - - - - - - - - - - - - - -
~
:"H"or"L"
240721-5
3-117
inter
21019
RAS ONLY REFRESH CYCLE
t RAS
V1H CAS
V1L t ASR
AO~A8
tRAH
V1H V1L -
VOH DOUT
- - - - - - - - - - - - - OPEN - - - - - - - - - - - - - VOL -
~
: !'H" or ilL"
240721-6
CAS BEFORE RAS REFRESH CYCLE
VOH DoUT
1>-------- OPEN - - - - - - - - - - - - -
.
VOL- _ _ _ _""""'I
~
: "H," or ilL"
240721-7
3-118
inter
21019
HIDDEN REFRESH CYCLE (READ)
t RAS
VOH DOUT
VOL -
----------+~
~ : "H"or"L"
240721-8
3-119
inter
21019
HIDDEN REFRESH CYCLE (WRITE)
DIN
VIL -
..............................*-1
1'-------'"'1
VOH DOUT
VOL -
- - - - - - - - - - - - - - OPEN - - - - - - - - - - - - - -
~
:"H"or"L"
240721-9
3-120
inter
21019
FAST PAGE MODE READ CYCLE
,
t RASP
RAS
VIH -
t RP
I-~
~
Vll -
I
t CRP
t RCD
,,\
CAS V I H - J
Vll -
tcp
tCAS
,,\
'I
tcp
~
tCAS
~
-.::.:....
,,\
I
-~
I
Ao~A9
VIH-~
Vll -
tRAl
ROW
~
t ASC
-leAH
COL
"~- f1
t RCS
F- ~
:::=~
tCAC
tAA
~
t Asc
tCAH
~
~~ -l
COL
tRAD
WRITE
,I
-- - -- ~ - -- - -t AsC
tRAH
t CRP
tCAS
....::.:..:.:..
tAR
t ASR
'--
t RSH
tpc
tCSH
b
t RCS
tAA
~H
t RCH
t Rcs
~
tAA
1
~
DATA
~
tCPA
..,. ,.............,
"" ..---.
~r-~
VALID
-- -
~
tCAC
tCPA
VOl -
b
tCAC
1
VOH -
COL
W -- W -I
I
t RAC
DOUT
tCAH
tOFF
tcLZ
--
~
tcLZ
[ZI
~
VALID
DATA
tOFF
-- -
VALID
DATA
I
tOFF
tClZ
: "H" or "L"
240721-10
3-121
inter
21019
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
DIN
VIL -
"""''''''''''''''''''''''''''''''''~ l'-----~
VOH -
Dour
VOL -
- - - - - - - - - - - - - - - OPEN
~
: "H" or"L"
240721-11
3-122
inter
21019
CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
RAS
t RsH
VIH VIL tCHR
CAS
t CPT
tCAS
VIH VIL -
VIH Ao~A9
VIL -
READ CYCLE
VOH DOUT
VOL -
_ _ VIH WRITE
VIL WRITE CYCLE
VOH OPEN
DOUT
tCWL
VOL
t RWL
twcs
t WCH
VIH WRITE
VIL -
VIH DIN
VIL -
~
: "H"or"L"
240721-12
3-123
225636
256K x 36-BIT DYNAMIC RAM
MEMORY MODULE WITH PAGE MODE
•
Performance Range
•
•
•
•
Parameters
225636-08
225636-10
Access Time from RAS (tRAC>
80
100
ns
Access Time from CAS (tcAC>
20
25
ns
Read Cycle Time (tRC>
150
180
ns
256K x 36-Bit Organization
Industry Standard Pin-Out in a 72-Pin
Single In-Line Memory Module (SIMM)
Common 1/0 Using "Early Write"
Single 5V
+
Units
10% Power Supply
•
•
•
•
512 Refresh Cycles every 8 ms
Separate CAS Control for Each Nine
Common Data-In and Data-Out Lines
Fast Page Mode Operation
TTL Compatible Inputs and Outputs·
The 225636 is a 256K x 36-bit ORAM memory module consisting of Industry Standard CMOS 256K x 4-bit
ORAMs and 256K x 1-bit DRAMs. The module contains eight 256K x 4-bit 20-pin SOJ packages and four 256K
x 1-bit 18-pin PLCC packages. There are bypass capacitors on board on each module.
The 18 address .bits are entered 9 bits at at time using RASO or RAS2 to latch the first 9 bits and CASO, CAS 1,
CAS2 or CAS3 to control the latter 9 bits.
The common liD feature requires the use of an early write cycle to prevent data contention on DO lines.
PIN CONFIGURATIONS (Front View)
Pin Symbol
Pin Symbol
Pin Symbol
1 Vss
2 000
3 0018
4 001
5 0019
6 002
7 0020
8 003
9 0021
10 Vee
·11 NC
12 Ao
13 Al
14 A2
15 A3
16 A4
17 A5
18 A6
19 NC
20 004
21 0022
22 005
23 0023
24 006
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49 009
50 0027
51 0010
52 0028
53 0011
54 0029
55 0012
56 0030
57 0013
58 D031
59 Vee
60 0032
61 0014
62 0033
63 0015
64 0034
65 0016
66 NC
67 PD1
68 P02
69 P03
70 P04
71 NC
72 Vss
0024
007
0025
A7
NC
Vee
A8
NC
NC
RAS2
0026
D08
0017
D035
VSS
CASO
CAS2
CAS3
CAS1 '
RASO
NC
NC
W
NC
,dO
DO
DO
DO
DO
36
37
72
Qo
240837-1
Figure 1. Pin Assignment
3-124
October 1990
Order Number: 240837-001
inter
225636
Pin Name
Ao-As
000- 00 35
W
RASO, RAS2
CASO-CAS3
P01-P04
Vee
Vss
NC
Presence Detect Pins (Optional)
Pin Function
Address Inputs
Data In/Out
Read/Write Input
Row Address Strobe
Column Address Strobe
Presence Detect
Power (+5V)
Ground
No Connection
Pin
80 ns
100 ns
P01
P02
P03
P04
Vss
NC
NC
Vss
Vss
NC
Vss
Vss
AO-AS
iN
RASO
CASO
Ao-As
DQ 1 -oDQO
DQ2 -oOQl
DQ3 - o DQ2
DQ4 - o DQ3
RAS
CAS
W
Ao-As
DQ 1 ;-ODQ 4
DQ 2 -oDQS
DQ3 r-o DQ6
DQ 4 r-o DQ7
RAS
CAS
iN
RAS2
CAS2
iN
Ao-As
RAS
CAS
W
Ao-As
RAS
CAS
W
Ao-As
d]OE
RAS
CAS
W
Ao-As
d]OE
RAS
CAS
W
Ao-As
Vee 0
~
Da 1
DQ2
OQ3
DQ4
~
~
DQ 1
D02
DQ3
00 4
~
d]OE
d]OE
d]OE
RAS
CAS
D U DQs
o
RAS
CAS
w
Ao-As
d]OE
RAS
CAS
W
Ao-As
.
DQ 1 r-oDOg
DQ2
00 11
DQ3
DQ 4 r-o DQ 12
~~O10
RAS
CAS
W
Ao-As
CAS3
:tr
DQ 1
002
00 3
DQ4
~
001
002
DQ3
00 4
~
~
mOE
DQ 1
DQ 2
DQ3
DQ4
~~Q13
DQ 14
RAS
CAS
W
Ao-As
f-o DQ 1S
f-o DQ16
:r
mOE
D017
RAS
CAS
W
Ao-As
~
~
:tr
•
-L. Vee 0.22}'F Capacitor T II ORA"
.,.. on each DRAM
• 0 a
mS
VSSO~---~~--------------'.
240S37-2
Figure 2. 256K x 36-Bit SIMM Block Diagram
3-125
inter
225636
PACKAGE DIMENSIONS
0.133:t0.004, _
(3.38tO.l0)
~
______________________
r
r
~3~.9~84~
_____________________~,1
(101.19)
RO.062 t 0.004
(1.57tO.l0)
r
L
o~0
0
'I
RO.125,--...
(3.18)
'\
/ 1[:: ::]0001 '"
§l~ ~[:::]
0.250tO.00~_
(107.95)
4250
~o
~d
0 c::: ::]'-El-++
!=
--+
I '\.
I
(6.35tO.l0)
0.250 t 0.004
:.l
0.080 t 0.004, _
(6.35tO.l0)
RO.062 t 0.004
(2.03tO.l0)
(1.57tO.l0)
0.250 --l---I--------------------- ;~3.;:;75~0 --------------------+1
(6.35)
(95.25)
1---i=!o.125 MIN
(3.17)
I--t- 0.200 MAX
DETAIL OF CONTACTS
I ..:
(5.08)
-II- 0.053 (1.35)
0.047 (1.19)
unit: inches (millimeters)
240837-3
Tolerances:
± 0.005 (0.13) unless otherwise specified.
Figure 3. Outline Drawing
3-126
intJ
225636
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative
to vss (VIN, VOUT) .............. -1V to
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.
+ 7.0V
Voltage on Power Supply
Relative to Vss (Vecl ........... -1V to
Storage Temperature (Tsm) .... - 55·C to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 7.0V
+ 125·C
Soldering Temperature - Time
(Tsolder) ....................... 260·C -10 Sec
Power Dissipation (Pd) ....................... 9W
Short Circuit Output
Current (lOUT) .......................... 50 mA
RECOMMENDED OPERATING CONDITIONS
Symbol
(Voltage Referenced to VSS. T A = O·C to 70·C)
Parameter
Min
Typ
Max
Units
Vee
Supply Voltage
4.5
5.0
5.5
V
Vss
Ground
0
0
0
V
VIH
Input High Voltage
2.4
VIL
Input Low Voltage
-1.0
-
CAPACITANCE
Symbol
Vee
+1
0.8
V
V
(TA = 25·C)
Min·
Parameter
Max
Units
Ci(A)
Input Capacitance (AO-A9)
80
pF
Cdq
1/0 Capacitance
20
pF
Cj (W)
Input Capacitance, Write Control Input
94
pF
Cj (RAS)
Input Capacitance, RAS Input
50
pF
Ci (CAS)
Input Capacitance, CAS Input
40
pF
Ci(CASP)
Input Capacitance, CASP Input
20
pF
Ci(DP)
Input Capacitance
15
pF
15
pF
Co (QP)
\
Output Capacitance
3-127
intJ
22'5636
D.C. AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
ICCl
ICC2
ICC3
ICC4
Speed
Parameter
Operating Current
(RAS and CAS Cycling
Standby Current
I
I
@
tRC
=
=
RAS
RAS
=
-08
-10
Min)
CAS
CAS
=
=
Min
VIH
VCC -0.2V
Max
Units
820
700
mA
24
mA
9
mA
RAS OnlyHefresh Current
(CAS = VIH. RAS Cycling @ tRC
Min)
-08
-10
820
700
mA
=
Fast Page Mode Current
(RAS = VIL. CAS Cycling
Min)
-08
-10
580
480
mA
=
-08
-10
820
700
mA
@
tpc
ICC6
CAS-before-RAS Refresh Current
(RAS and CAS Cycling @ tRC = Min)
IlL
Input Current
(Any Input 0 S VIN S 6.5V
All Other Pins = OV)
-120
120
,...A
loz
Off State Output Current
(Data Out is Disabled and
Os VOUT s 5.5V)
-20
20
,...A
VOH
Output High Voltage Level
(IOH = -5mA)
2.4
Vee
V
VOL
Output Low Voltage Level
(IOL = 4.2 mA)
0
0.4
V
NOTE:
ICC1. ICC3. ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output
open. Icc is specified as average current.
3-128
intJ
225636
A.C. CHARACTERISTICS(1, 2) (TA = O·Cto 70·C, Vcc = 5V ±10%)
Symbol
Parameter
225636·08
Min
Max
225636·10
Min
Units
Notes
Mas
tRAC
Access Time from RAS
80
100
ns
4, 7
tCAC
Acces Time from CAS
20
25
ns
5, 7
tAA
Access Time from
Column Address
40
50
ns
6, 7
tCPA
Access Time from CAS
Precharge
45
55
ns
7,14
tClZ
Output Low Impedance
Time from CAS Low
5
ns
7
tOFF
Output Disable Time
after CAS High
a
25
50
5
a
30
ns
8
ms
3
50
ns
tREF
Refresh Cycle Time
tT
Transition Time
3
8
tRP
RAS High Pulse Width
60
70
ns
tCRP
CAS to RAS Precharge
Time
5
5
ns
tRCD
RAS to CAS Delay Time
25
tCPN
CAS High Pulse Width
35
tRAD
Column Addres Delay
Time from RAS Low
20
tASR
Row Address Setup
Time before RAS Low
a
tASC
Column Address Time
before CAS Low
0
tRAH
Row Address Hold Time
after RAS LOW
15
15
ns
tCAH
Column Address Hold Time
after CAS Low or W Low
20
20
ns
3-129
60
25
75
35
40
20
a
9,10
ns
50
a
20
ns
ns
ns
20
ns
11
225636
A.C. CHARACTERISTICS(1, 2) (Continued) (TA = O·C to 70·C, VCC = 5V ± 10%)
READ AND REFRESH CYCLES
Symbol
Parameter
225636-08
Min
225636-10
Max
Min
Units
Notes
Max
Read Cycle Time
150
tRAS
RAS Low Pulse Width
80
10K
100
10K
ris
teAs
CAS Low Pulse Width
20
10K
25
10K
ns
tesH
CAS Hold Time
after RAS Low
80
100
ns
tRSH
RAS Hold Time after
CAS Low
20
25
ns
tRCS
Read Setup Time
before CAS Low
0
0
ns
tRCH
Read Hold Time
after CAS High
0
0
ns
12
tRRH
Read Hold Time
after RAS High
0
0
ns
12
tRAL
Column Address to
RAS Setup Time
40
50
ns
tRPC
Precharge to CAS
Active Time
10
10
ns
tRC
180
ns
CAS BEFORE RAS REFRESH CYCLE
Symbol
Parameter
225636-08
Min
Max
225636-10
Min
Units
Max
tesR
CAS Set Up Time for CAS
before RAS Refresh
10
10
ns
tCHR
CAS Hold Time for CAS
before RAS Refresh
30
30
ns
tRPe
Precharge to CAS
Active Time
10
10
ns
3-130
Notes
inter
225636
A.C. CHARACTERISTICS (Continued)
(TA
=
0·Cto70·C, Vcc
=
5V ±10%)
WRITE CYCLE (Early Write)
Symbol
Parameter
225636·08
Min
Max
225636·10
Min
Units
twc
Write Cycle Time
160
tRAS
RAS Low Pulse Width
130
190
tos
Data Setup Time
0
0
ns
tOH
Data Hold Time
after CAS Low
20
20
ns
tCAS
CAS Low Pulse Width
20
tCSH
CAS Hold Time
after RAS Low
80
100
ns
tRSH
RAS Hold Time
after CAS Low
20
25
ns
twcs
Write Setup Time
before CAS Low
0
0
ns
tWCH
Write Hold Time
after CAS Low
20
20
ns
twp
Write Pulse Width
15
20
ns
10K
10K
3·131
160
25
Notes
Max
ns
10K
10K
ns
ns
13
inter
225636
FAST PAGE MODE CYCLE (Read, Early Write cycles)
Symbol
Parameter
225636-08
Min
tpc
Fast Page Mode
Cycle Time
Max
50
225636-10
Min
Units
60
ns
tRAS
RAS Low Pulse Width
. for Read, Write Cycle
80
10K
100
10K
ns
teAS
CAS Low Pulse Width
for Read Cycle
20
10K
25
10K
ns
tcp
CAS High Pulse Width
10
15
Notes
Max
ns
NOTES:
1. An initial pause of 500 ILs is required after power-up followed by any 8 RAS-only cycles before proper device operation is
achieved.
.
2. A.C. Characteristics assume tT = 5 ns.
3. VIH(min) and VIL(max) are reference levels for measuring timing of input Signals. Also, transition times are measured
between VIH (min) and Vldmax).
.
4. Assumes that tRCO ,;; tRco(max), tRAO ,;; tRAO(max). If tRCO (or tRAO) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCO (or tRAO) exceeds the value shown.
5. If tRCO ;;, tRCO(max), tRAO ;;, tRAO(max), and tASC ;;, tM - !cAC - tT, access time is !cAC.
6. If tRAo ;;, tRAo(max) and tASC ,;; tAA - tCAC - tT, access time is tAA.
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. tOFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCO(max) limit insures that tRAc(max) can be met. tRCO(max) is specified as a reference point only;
if tRCO is greater than the specified tRco(max) limit. access time is controlled exclusively by tCAC or tM.
.
10. tRco(min) = tRAH(min) + 21T + tAsc(min).
11. Operation within the tRAO(max) ·limit insures that tRAc(max) can be met. tRAO (max) is specified as a reference point
only; if tRAO is greater than the specified tRAO(max) limit, access time is exclusively controlled by tCAC or tAA.
12. Either tRRH or tRCH must be specified for a read cycle.
13. twcs. tCWO. tRWO and tAWO are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
14. tCPA is access time from the selection of a new column address (that is caused by changing ~ from "L" to "H").
3-132
225636
READ CYCLE
VOH -
Dour
VOL -
------
~
: "HI! or"L"
240837-4
3-133
inter
225636
EARLY WRITE CYCLE
VOH~~~~~~~~~ ~~--~--~ ,~~~~~~~~~~
DIN
VALID DATA
VOL--~~~~~~~~~
VOH - DOUT
- - - - - - - - - - - - - OPEN - - - - - - - - - - - - - -
VOL - -
~
:"H"or"L"
240837-5
3-134
225636
RAS ONLY REFRESH CYCLE
VOH -
DOUT
- - - - - - - - - - - - OPEN - - - - - - - - - - - - VOL -
I2ZJ :
"H" or "L"
240837-6
CAS BEFORE RAS REFRESH CYCLE
VOH -
Dour
1)------- OPEN
VOL- _ _ _ _""""'I
-------------
I2ZJ :"H" or "L"
240837-7
3-135
inter
225636
HIDDEN REFRESH CYCLE (READ)
_ _ V1H -
WRITE
DO~
VOH -
VOL -
----------------~~~
~
: "H"or"L"
240837-8
3-136
inter
225636
HIDDEN REFRESH CYCLE (WRITE)
DIN
VIL -
......"""''''''''''''''''''''''..,
~-----~ ~"'"''''"''''"''''"''''"'''''''''''''''''''''''''''''''''''''''''''~
VOH -
Dour
VOL -
- - - - - - - - - - - - - - OPEN - - - - - - - - - - - - - -
~ : UHf!
or '''L''
240837-9
3-137
inter
225636
FAST PAGE MODE READ CYCLE
--,........,
t RASP
RAS
VIH -
t RP
i\
Vll -
t RCD
tcRP
tcp
tCAS
\\
CAS V I H - J
Vll -
t RSH
tpc
tCSH
\\
I
tcp
tCAS
~
\\
I
I
--
AONAg
VIH~~
Vll -
ROW
tRAl
tAse
tRAH
~
~
I-
+-00
~
~
COL
1<,
.~
t RCS
r-I-
~
tCAC
:-+
tAA
,I
-
tASC
tCAH
-
tASC
+-00
~
COL
- H t RCS
W
. I
.~
tCAC
tAA
~
... -I
W
I
tCPA
VALID
~r-~
DATA
VOl -
~
~H
t RCS
t RCH
~
tCAC
+-00
tAA
1
tRAC
VOH -
~
COL
1
Dour
tCAH
~
b~ b
tRAD
WRITE:::
t CRP
tCAS
......::..:.:.. f---=--
i---=--
tAR
t ASR
l\..
I
tCPA
'"
'" r---.
~ VALID
DATA
tOrr
tClZ
-=. I-
~
-
~
tClZ
I-
~
tOrr
-
,.--...,
VALID
DATA
'-I
tOrr
,
tClZ
~.
: "H" or "Lu
240837-10
3-138
inter
225636
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
DIN
VIL ---...:.
~""",,,",,,,,",,,~'..:..I 1'-----"'1
VOH -
Dour
VOL -
--------------
~
OPEN - - - - - - - - - - - - - - -
:"H" or"L"
240837-11
3-139
inter
225636
CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
RAS
t RSH
VIH VIL tCHR
CAS
t CPT
tCAS
VIH VIL -
VIH Ao~A9
VIL -
READ CYCLE
VOH DOUT
------
VOL -
_ _ VIH WRITE
...:~~~~~"""""""""""""""".u
VIL WRITE CYCLE
VOH DOUT
.
--------------+1--- OPEN ---1--1----tCWL
VOL
twcs
DIN
VIL -
~~...""""..."'"""""''''''~~;,g l~----~ ""'~"""""'""""'~""""""""""'''''
~ : "H"or"L"
240837-12
3-140
251236
512K x 36-BIT DYNAMIC RAM
MEMORY MODULE WITH PAGE MODE
•
Performance Range
Parameters
251236-08
251236-10
Units
80
20
150
100
25
180
ns
Acces Time from RAS (tRAd
Access Time from CAS (tcAd
Read Cycle Time (tRd
•
•
•
•
•
512K x 36-Bit Organization
Industry Standard Pin-Out in a 72-Pin
Single In-Line Memory Module (SIMM)
Common I/O Using "Early Write"
Single 5V
+ 10% Power Supply
Separate CAS Control for 4 Groups of
18 Common Data-In and Data-Out Lines
•
•
•
•
•
ns
ns
512 Refresh Cycles every 4 ms
Separate CAS (CAS8) Control for One
Separate Pair of Data-In and Data-Out
Lines
Separate RAS Control for 4 Groups of
18 Common Data-In and Data-Out Lines
Fast Page Mode Operation
TTL Compatible Inputs and Outputs
The 251236 is a 512K x 36-bit Oynamic RAM Memory Module consisting of industry standard CMOS, 256K x
4-bit ORAMs and 256K x 1-bit ORAMs. The module contains sixteen 256K x 4-bit in 20-pin plastic SOJ
package and eight 256K x 1-bit in 18-pin PLCC. There are bypass capacitors on board each SIMM module.
The common 1/0 feature requires the use of an early write cycle to prevent data contention on 00 lines.
PIN CONFIGURATIONS (FrontView)
Pin Symbol
Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Vss
000
0018
001
0019
002
0020
003
0021
Vee
NC
Ao
Al
A2
A3
A4
A5
A6
NC
004
0022
005
0023
006
0024
007
0025
A7
NC
Vee
A8
NC
NC
RAS2
0026
008
0017
0035
Vss
CASO
CAS2
CAS3
CAS 1
RASO
NC
NC
W
NC
Pin Symbol
49
50
51
52
53
54
,55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
009
0027
001O
0028
0011
0029
0012
0030
0013
0031
Vee
0032
0014
0033
0015
0034
0016
NC
P01
P02
P03
P04
NC
Vss
t---t- 0.350 MAX
I _ I
(8.89)
--II- 0.053(1.35)
0.047(1.19)
240836-13
NOTE:
Components are mounted
on both sides of the board.
240836-12
Figure 1. Pin Assignment
3-141
,
October 1990
Order Number: 240836-001
251236
CASO
000- 3
~
RASO
1m
~
Im
Vi
001
00 2
003
Ao-As DO,
Vi
00 1
00 2
00 3
Ao-As DO,
CAS
RAS
OE
00,-7
CAS
RAS
OE
001
CAS I---00 2
_ R~
003
DO, Ao-As W OE:m
DOs
L-.fCAS _
RAS W Ao-As
I
~
001
CAS I---002
_ R~
003
DO, Ao-As W OE:m
CAS
RAS
mOE
-m
--I
-m
-
1m
Vi
-
_ CA~l---"Ao-As W RAS
I
009- 12
001
00 2
003
Ao-As
0
001
-'002
~_ R~
003
DO, Ao-As W OE
m
00 17
CAS
RAS
Vi
4~
0
Ao-As
oi-J
1 J
_CA~~
Ao-As W RAS
I
D0 1S- 21
001
CAS
002
RAS _
003
OE W Ao-As 'DO,
-
CAS
RAS
OE
Vi
001
'
CAS f - 00 2
003
- RAS
DO, Ao-As W OE:m
001
002
00 3
Ao-As DO,
0026
61-1
I
, 0
40
Ao-As
Vi
I
I
0027-30
Vi
001
002
003
Ao-As DO,
Vi
001
00 2
00 3
Ao-As DO,
CAS
RAS
OE
0'
CAS
RAS
001
CAS f 00 2
00 3
_ R~
DO, Ao-As W OE:m
00 31 - 3,
CAS _
RAS W Ao-As
0'
001
CAS002
003
_ R~
DO, Ao~As W OE
m
0035
4~
6i-J
_CA~~
Ao-As W RAS
~
Vi
I
001
00 2
CAS
00 3
_ R~
DO, Ao-As W OE-m
0022-25
mOE
I
I
1
Ao-As
I
001
CAS f 00 2
_ R~
003
DO, Ao-As W OE:m
0013-16
CAS
RAS
--I
40
001
CAS
00 2
_
00
RAS
3
OE W Ao-As DO,
I
1m
6t-I
I
L..-iCAS _
RAS W Ao-A s
~
, 0
0'
vcco~-----Jt~~0~.2~2-~~F~C-op-0-cl~to-r--·
lr
.._u"_d_er__eO_C_h_D_RA_M__- . To all DRAMs
vsso_______
240836-1
Figure 2. Block Diagram
3-142
(
4.250
(107.95)
0.133:1: 0.004
(3.38:1: 0.1 0)
I·
3.984
(101.19)
RO.062:1: 0.004
(1.57:1: 0.1 0)
_
BQ,ill
(3.18)
~
I
I
'I
0'
ci
ott
CD
c:J c:J c:J c:J
c:J 0 0 0 0 c:J ~+--+I
ci
:uODuu uOCiEl:'ll'
.::.
"TI
cO'
...
e
(D
~
~
~
'"
0
aS·
(D
0.080:1: 0.004
(2.03:1: 0.1 0)
0.250
(6.35)
0.250:1:0.004
(6.35:1: 0.1 0)
I.
01-
I.
0.125 MIN
(3.17)
-1'--
...
RO.062:1: 0.004
(1.57:1: 0.1 0)
3.750 _ _ _ _ _ _ _ _ _ _ _ _ __
(95.25)
I\,)
C11
I\,)
(,,)
en
...IIIC
:e
S·
~0.350
DETAIL OF CONTACTS
I _ I
CC
(8.89) MAX
~
l§
UU
0.010MAXlOAA=t
(0.25)
f
0.050
(1.27)
JJU L
~2~~~)
~
~
©
fi'iiiI
=
~
MIN
0 041 :I: 0.004
(;.04:1:0.10)
'1iil
-II-- 0.053 (1.35)
0.047 (1.19)
240836-2
@
2EJ
~
~
<=:J
©
~
inter
251236
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative
to vss (VIN, VOUT) .............. -1V to
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.
+ 7.0V
Voltage on Power Supply
Relative to vss (Vee> ........... -1V to
Storage Temperature (TSTG) .... - 55°C to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the .
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 7.0V
+ 125°C
Soldering Temperature. Time
(Tsolder) ....................... 260°C • 10 Sec
Power Dissipation (Pd) ....................... 9W
Short Circuit Output
Current (lOUT)' ...................•..... 50 mA
RECOMMENDED OPERATING CONDITIONS
Symbol
Vee
Parameter
Min
Typ
Max
Units
Supply Voltage
4.5
5.0
5.5
V
0
V
Vss
Ground
VIH
Input High Voltage
VIL
- Input Low Voltage
CAPACITANCE
Symbol
(Voltage Referenced to Vss. TA = O°C to 70°C)
0
0
2.4
-
-1.0
-
Vee
+1
0.8
V
V
(TA = 25°C)
Max
Units
CdA)
Input Capacitance (AO-A9)
Parameter
Min
75
pF
Cdq
1/0 Capacitance
20
pF
Cj (W)
Input Capacitance, Write Control Input
94
pF
Cj (RAS)
Input Capacitance, RAS Input
50
pF
Cj (CAS)
Input Capacitance, CAS Input
40
pF
Cj (CASP)
Input Capacitance, CASP Input
20
pF
Cj(DP)
Input Capacitance
15
pF
Co (QP)
Output Capacitance
15
pF
3-144
251236
D.C. AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Parameter
Symbol
ICC1
ICC2
ICC3
iCC4
Operating Current
(RAS and CAS Cycling
Standby Current
I
I
@
tRC
=
=
RAS
RAS
=
Speed
-08
-10
Min)
CAS
CAS
=
=
Min
Max
Units
820
750
mA
VIH
18
mA
VCC -0.2V
9
mA
RAS Only Refresh Current
(CAS = VIH. RAS Cycling @ tRC
Min)
-08
-10
820
700
mA
=
Fast Page Mode Current
(RAS = Vil. CAS Cycling
=
Min)
-08
-10
580
480
mA
mA
-08
-10
820
700
mA
-120
120
/-LA
@
tpc
ICC6
CAS-before-RAS Refresh Current
(RAS and CAS Cycling @ tRC = Min)
ill
Input Current
(Any Input 0 ,,:; VIN ,,:; 6.5V
All Other Pins = OV)
loz
Off State Output Current
(Data Out is Disabled and 0 ,,:; VOUT ,,:; 5.5V)
-20
20
/-LA
VOH
Output High Voltage Level
(IOH = -5 mAl
2.4
VCC
V
VOL
Output Low Voltage Level
(JOL = 4.2 mAl
0
0.4
V
NOTE:
ICC1. ICC3. ICC4 and ICG6 are dependent on output loading and cycle rates. Specified values are obtained with the output
open. Icc is specified as average current.
3-145
251236
.
A C CHARACTERISTICS(1, 2) (TA =
Symbol
Parameter
0°Ct070°C, Vcc
=
251236-08
Min
Max
5V +10%)
-
251236-10
Min
Units
Notes
Mas
tRAC
Access Time from RAS
80
100
ns
4,7
·tCAC
Acces Time from CAS
20
25
ns
5, 7
tCAA
Access Time from
Column Address
40
50
ns
6, 7
tePA
Access Time from CAS
Precharge
45
55
ns
7,14
tClZ
Output Low Impedance
Time from CAS Low
5
ns
7
tOFF
Output Disable Time
after CAS High
0
tREF
Refresh Cycle Time
tT
Transition Time
tRP
RAS High Pulse Width
teRP
CAS to RAS Precharge Time
5
tRCD
RAS to CAS Delay Time
25
tCPN
CAS High Pulse Width
35
tRAD
Column Addres Delay
Time from RAS Low
20
tASR
Row Address Setup
Time before RAS Low·
0
tASC
Column Address Time
before CAS Low
0
tRAH
RoW Address Hold Time
after RAS LOW
15
15
ns
tCAH
Column Address Hold Time
after CAS Low or W Low
20
20
ns
5
25
0
8
3
50
60
3-146
3
30
ns
8
ms
50
ns
70
ns
50
60
25
ns
75
ns
50
ns
35
40
20
ns
0
20
0
9,10
ns
20
ns
11
251236
A.C. CHARACTERISTICS(1, 2) (Continued) (TA = O°Cto 70°C, VCC = 5V ±10%)
READ AND REFRESH CYCLES
Symbol
Parameter
251236-08
Min
Max
251236-10
Min
Units
Notes
Max
Read Cycle Time
150
tAAS
RAS Low Pulse Width
80
10K
100
10K
ns
tCAS
CAS Low Pulse Width
20
10K
25
10K
ns
tCSH
CAS Hold Time
after RAS Low
80
100
ns
tASH
RAS Hold Time after
CAS Low
20
25
ns
tACS
Read Setup Time
before CAS Low
0
0
ns
tACH
Read Hold Time
after CAS High
0
0
ns
12
tAAH
Read Hold Time
after RAS High
0
0
ns
12
tAAL
Column Address to
RAS Setup Time
40
50
ns
tAPC
Precharge to CAS
Active Time
10
10
ns
tAC
ns
180
..
CAS BEFORE RAS REFRESH CYCLE
Symbol
Parameter
251236-08
Min
Max
251236-10
Min
Units
Max
tCSA
CAS Set Up Time for CAS
before RAS Refresh
10
10
ns
tCHA
CAS Hold Time for CAS
before RAS Refresh
30
30
ns
tAPC
Precharge to CAS
Active Time
10
10
ns
3-147
Notes
inter
251236
A.C. CHARACTERISTICS (Continued) (TA =
O·C to 70·C. Vcc
=
5V ± 10%)
WRITE CYCLE (Early Write)
Symbol
Parameter
251236-08
Min
Max
251236-10
Min
Units
twc
Write Cycle Time
160
tRAS
RAS Low Pulse Width
130
tos
Data Setup Time
0
0
ns
tOH
Data Hold Time
after CAS Low
20
20
ns
tCAS
CAS Low Pulse Width
20
tCSH
CAS Hold Time
after RAS Low
80
100
ns
tRSH
RAS Hold Time
after CAS Low
20
25
ns
twcs
Write Setup Time
before CAS Low
0
0
ns
tWCH
Write Hold Time
after CAS Low
20
20
ns
twp
Write Pulse Width
15
20
ns
190
10K
10K
3-148
160
25
Notes
Max
ns
10K
10K
ns
ns
13
251236
FAST PAGE MODE CYCLE (Read. Early Write cycles)
Symbol
Parameter
251236-08
Min
Max
251236-10
Min
Units
Notes
Max
tpc
Fast Page Mode
Cycle Time
50
60
tRAS
RAS Low Pulse Width
for Read. Write Cycle
80
10K
100
10K
ns
tCAS
CAS Low Pulse Width
for Read Cycle
20
10K
25
10K
ns
tcp
CAS High Pulse Width
10
10
15
10
ns
ns
NOTES:
1. An initial pause of 500 ,..s is required after power-up followed by any 8 RAS-only cycles before proper device operation is
achieved.
2. A.C. Characteristics assume tT = 5 ns.
3. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also. transition times are measured
between VIH (min) and Vldmax).
4. Assumes that tRCO :;; tRCO(max). tRAO :;; tRAo(max). If tRCO (or tRAO) is greater than the maximum recommended value
shown in this table tRAC will be increased by the amount that tRCO (or tRAO) exceeds the value shown.
5. If tRCO ;;, tRCO(max). tRAO ;;, tRAO(max). and tASC ;;, tAA - tCAC - tT. access time is tCAC'
6. If tRAO ;;, tRAO(max) and tASC :;; tAA - tCAC - tT. access time is tAA.
7. Measured with a load equivalent to two TTL loads and 100 pF.
8. tOFF is specified that output buffer changes to high impedance state.
9. Operation within the tRCO(max) limit insures that tRAdmax) can be met. tRCO(max) is specified as a reference point only;
if tRCO is greater than the specified tRCO(max) limit. access time is controlled exclusively by !cAe or tAA'
10. tRCO(min) = tRAH(min) + 2tT + tAsdmin).
11. Operation within the tRAO(max) limit insures that tRAdmax) can be met. tRAO (max) is specified as a reference paint
only; if tRAO is greater than the specified tRAO(max) limit. access time is exclusively controlled by tCAC or tAA.
12. Either tRRH or tRCH must be specified for a read cycle.
13. twCS. tcWO. tRWO and tAWO are non-restrictive operating parameters. They are included in the Data Sheet as Electrical
Characteristics only.
14. tCPA is access time from the selection of a new column address (that is caused by changing CAS from "L" to "H").
3-149
251236
READ CYCLE
V1H CAS
V1L tRAD
V1H AO-Ag
V1L -
VOHDOUT
VOL -
- - - - - - OPEN -------<~
~
VALID DATA
:"H"or"L"
240836-3
3-150
intJ
251236
EARLY WRITE CYCLE
DIN
VOH '
VOL-~~~~""~~~ ~__________~
~~~. . . .~~~~~~. .
VOH -
Dour
VOL -
- - - - - - - - - - - - - OPEN - - - - - - - - - - - - -
~
:"H"or"L"
240838-4
3-151
inter
251236
RAS ONLY REFRESH CYCLE
VOH-
DOUT
VOL -
- - - - - - - - - - - - OPEN - - - - - - - - - - - - -
~ : "H"or"l"
240836-5
CAS BEFORE RAS REFRESH CYCLE
VOH -
DOUT
I}-------
VOL- _ _ _ _~
OPEN - - - - - - - - - - - - -
~ : "H"or"L"
240836-6
3-152
intJ
251236
HIDDEN REFRESH CYCLE (READ)
VOH DOUT
VOL -
------------l~
~
: "H" or"L"
240836-7
3-153
251236
HIDDEN REFRESH CYCLE (WRITE)
_ _ VIH WRITE
DIN
VIL -
"""'''''''''''''''''''''''"''''''''''''''';.,
jIo------oJ! """""""""""""""""""",;.0..:""""""""""""""""""""""",,,,,,"
VOH DOUT
- - - - - - - - - - - - - OPEN - - - - - - - - - - - - -
VOL - -
~
: "H"or "L"
240836-8
3-154
inter
251236
FAST PAGE MODE READ CYCLE
t RASP
RAS
VIH -
t RP
--:.::-..
~
~
Vll -
II
t CRP
CAS
tRCD
tcp
tCAS
VIH~J
1\\
Vll -
I
I-- I--
\\
II
tcp
tCAS
I--
tRAH
Ao~A9
VIH~~
Vll -
ROW
~
f-
~
,I
-
tASC
tCAH
-
~
COL
tRAD
COL
r- f--
:::~
tCAC
tAA
I---
~
tAA
~
~
tAA
tCPA
~~
DATA
'="
~H
t RCH
I
~r-~
VALID
tClZ
~
t cAC
tCAC
tCPA
VOl -
COL
t RCH
I
VOH -
tCAH
I--
- -~~ - ~~~
W ....... W .......
I
I
t RAC
DOUT
-
tASC
tCAH
I--
t RCH
tRCS
WRITE
II
tRAl
tASC
-'-f- i--+
t CRP
,teAs,
\\
I
tAR
t ASR
IL
t RSH
tpc
tCSH
~~
DATA
tOFF
~
~
-
~
tClZ
~.
DATA
tOFF
-
~
tOFF
tCLZ
~'
: "H" or "L"
240836-9
3-155
251236
FAST PAGE MODE WRITE CYCLE (EARLY WRITE)
DIN
VIL -
"""""""".......'-'-''-'-'"*-' 1'-----""1
VOH -
DOUT
- - - - - - - - - - - - - - OPEN
VOL -
~ :"H" orul"
240836-10
3-156
inter
251236
CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
RAS
t RSH
VIH VIL t CPT
tCHR
CAS
tCAS
VIH VIL -
Ao~A9
VIH VIL -
READ CYCLE
VOH DOUT
VOL -
------
_ _ VIH WRITE
VIL WRITE CYCLE
VOH DOUT
"""""""""'""""""""'""""'""""'""""'"""............,
--------------oHf--- OPEN --+-1----tCWL
VOL
twcs
DIN
VIL -
tWCH
.;...:..""""""""""""""""~~..........""'-'......,
~
: "H" or !fLU
240836-11
3-157
RELIABILITY
REPORT
RR-62
September 1989
Dynamic RAM
Reliability Report
MADHU NIMGAONKAR
COMPONENTS CONTRACTING DIVISION
QUALITY AND RELIABILITY ENGINEERING
Order Number: 240543-001
3-158
DRAM RELIABILITY DATA
SUMMARY
CONTENTS
PAGE
1.0 OVERViEW ........................ 3-160
2.0 RELIABILITY TESTS .............. 3-160
High Temperature Dynamic Lifetest ..... 3-160
High Voltage Dynamic Lifetest .......... 3-160
High Temperature/Humidity Test ....... 3-161
Autoclave .............................. 3-161
High Temperature Storage Test ........ 3-161
Temperature Cycle Test ................ 3-161
Electrostatic Discharge Test ............ 3-161
Soft Error Test ......................... 3-161
3.0 PLASTIC RELIABILITY DATA
SUMMARY ...................... 3-162
P21256 ................................ 3-162
P21464 ................................ 3-163
P21010 ................................ 3-164
P21014 ................................ 3-165
APPENDIX A
COMMON MOS FAILURE
MECHANISMS ......................... 3-166
Common MOS Failure Mechanisms .... 3-166
Oxide Defects .......................... 3-166
Silicon Defects ......................... 3-166
Refresh Degradation ................... 3-166
Contamination ......................... 3-166
Metallization Defects.; ................. 3-166
Soft Errors ............................. 3-166
3-159
RR-62
1.0 OVERVIEW
This reliability report is based on the combination of
actual data from all Intel qualified and approved vendors. This data may vary from lot to lot and under
different operating conditions encountered by the customer. Intel has published data sheet specifications that
should be considered in evaluating the performance for
specific application by the customer. This report does
not give any assurance that the product is appropriate
for any specific application as that decision is the responsibility of the customer.
When reviewing failure rate projections from different
sources, it is important to understand the assumptions
being made. Small changes in details can dramatically
alter an estimated failure rate.
II
I
107
1
Intel recognizes the need to monitor all contracted
products to maintain and improve the level of quality
and reliability consistent with internal goals and customer needs. This is achieved through continuous review of monitor data from all Intel qualified and approved vendors to acheive low defect levels.
1/
106
J
;,..1
V>
0::
=>
il ~/
105
.:
C)
0
:I:
I
'"=>
0::
2.0 RELIABILITY TESTS
...J
//
104
~
...
0
High Temperature Dynamic Lifetest
'"i=:::E
This test is performed to accelerate failure mechanisms
that are thermally activated through the application of
extreme temperatures (12S°C) and the use of biased operating conditions (S.SV). The translation from 12SoC
to SsoC is done by applying time acceleration factors
based on the thermal activation energy assignments
noted below. The time acceleration factors from 12SoC
to SsoC are: 3.42 for 0.3 eV, 7.67 for O.S eV and S8.96
for 1.0 eV, based on junction temperature offset for
power dissipation.
Failure rate calculations are given for each relevant activation energy. These are made using the appropriate
activation energy and the Arrhenius Plot as shown in
Figure 1. The total equivalent device hours at a given
temperature can be determined. The failure rate is then
calculated by dividing the number of failures by the
equivalent device hours and is expressed as a %/1000
hours. The failure rate is adjusted by a factor related to
the number of device hours using a chi-square distribution to arrive at a confidence level associated failure
rate. A conservative estimate of the failure rate is obtained by including zero failures at 0.3 eV, O.S eV and
1.0 eV. In cases where the mechanism of the catastrophic failures cannot be determined, 0.3 eV activation energy is assumed.
~
II
103
o·
I'
AI
102
III
10~
/
/
/
V
....
~~
7 o·
/1:2
./ o:!>
./
V /.V ,/
7
5 U I/./.
3
If) V
250200175150125100 75 50 25
TEMPERATURE (OC)
240543-1
Figure 1. Arrhenius Plot
High Voltage (7V) Dynamic Lifetest
This test is performed to detect failure mechanisms
which are accelerated by high voltage (7V) as well as
high temperature (12S°C). It is especially effective in
accelerating oxide and leakage related failures. The total acceleration factor includes the time acceleration
factors based on the assigned activation energies and
voltage activation factor of 12.7 (7V to "S.SV).
3-160
nt_f
•"••
'eII
RR-62
High Temperature/Humidity Lifetest
Temperature Cycle Test
This test is performed to evaluate moisture resistance
characteristics of plastic encapsulated devices. A woo2000 hour test is performed under static bias conditions
at 85·e/85% relative humidity with nominal voltages.
In order to maximize metal corrosion conditions, the
biasing configuration is either under low power or no
power, with alternate pins biased at + 5V or OV.
This test consists of cycling the temperature of a chamber housing device from -65·e to + l50·e with no
applied bias. Temperature cycling (WOO cycles) is used
to detect mechanical reliability problems and microcracks.
Electrostatic Discharge Test
Autoclave (Pressure Cooker) Test
This test is performed to identify the effects of high
humidity and heat conditions on the die surface. Steam
stressing accelerates moisture penetration through the
plastic package material to the surface of the die, resulting in corrosion of metals.
High Temperature Storage Test
High temperature storage (bake) is a test in which devices are subjected to elevated temperature of ISO·e
with no bias. This test is used to detect mechanical
reliability problems (e.g., bond integrity) and process
instability.
This test is performed to identify device sensitivity to
electrostatic discharge generated during system operation or device-handling. All products incorporate ESD
protection networks on the appropriate pins.
Soft Error Test (SER)
Soft error test is performed to identify the effects of
alpha particles which are emitted in the radioactive decay of uranium and thorium present in packaging materials. Two methods commonly used to measure soft error rates are: 1) accelerated testing using alpha particle
radiation source and 2) real time system level soft error
testing.
3-161
intJ
RR-62
3.0 PLASTIC RELIABILITY DATA SUMMARY
21256
Number of bits: 262,144
Organization: 256K x 1
Process: NMOS
Package: 16-Pin PDIP
Table 1_ Reliability Data Summ'ary
125°C Dynamic Lifetest
Year
I
168 Hrs
1988/89
I
3/11250
I
J
500 Hrs
0/11247
7V Dynamic Lifetest
1000 Hrs
168 Hrs
I
500 Hrs
2/11248
9/2400
J
5/2391
I
I
1000 Hrs
3/2386
Table 2. Failure Rate Predictions
125°C Actual
Device Hours
2E
21E
Ea
(eV)
+ 06
+ 05
Equivalent Hours
at 55°C
0.3BI
0.3VAF
30E
95E
+ 06
+ 06
5
17
=
Total 0.3 eV Failures
+ 06
11E + 06
11E
22
0.0193 (**)
0
0.0012
0
0.0001
+ 06
643E + 06
0.5
85E
1.0
Fall Rate %/1K Hours
(60% UCL)
#
Fail
0.0206
206
Combined Failure Rate:
FITs:
• °5.5V and 7V burn-in/lifetest equivalent hours have been combined.
6Ja
VCC
ICC@55°C
Icc@ 125°C
Icc (max)
Temp. with Tja
T(55)
T (125)
=
90°C/W (Est.)
=
=
=
=
5.5V
60 rnA
20 rnA
75 rnA (Spec)
BI/ELT
Accel.
Factors:
0.3eV
0.5eV
1.0eV
Thermal Accel_
Factors
55°C
3.42
7.67
58.96
Voltage Accel. Factor (VAF): 12.7
= 358K
= 411K
K = 8.62E -05 eV/K
NOTE:
FIT = Failures in Time. 1 FIT = 1 Failure per 10E
+
09 device hours.
Failure Analysis:
All failures assumed to be Oxide related.
Table 3. Additional Qualification Tests
Year
1988/89
1000
Temp Cycles
1500C/1K Hrs
High Temp Storage
9/2002
6/8120
0/12200
(0.5%)
(0.07%)
(0.0%)
1000 Hours
85°C/85% R.H.
204Hrs
Steam
9/12552
(0.07%)
Table 4. System SER Results .
Cycle Time
Device Hours
# of Errors
FIT (60%)
1 p.s
1.4M
o
654
3-162
RR·62
21464
Number of bits: 262,144
Organization: 64K x 4
Process: NMOS
Package: IS-Pin PDIP
Table 1. Reliability Data Summary
12S·C Dynamic Lifetest
Year
I
J
168 Hrs
1988/89
3/11250
I
1
SOO Hrs
0/11247
7V Dynamic Lifetest
1000 Hrs
168 Hrs
2/11248
8/2370
I
I
SOO Hrs
3/2362
I
1000 Hrs
I
0/2359
Table 2. Failure Rate Predictions
12S·C Actual
Device Hours
9E
21E
Ea
(eV)
+ 06
+ 05
Equivalent Hours
at SS·C
0.381
0.3 VAF
+ 06
+ 06
30E
91E
\
+ 06
11E + 06
16
0.0104 ( •• )
0
0.0012
0
0.0001
+ 06
645E + 06
0.5
11E
5
11
=
Total 0.3 eV Failures
84E
1.0
Fail Rate %/1K Hours
(60% UCL)
#
Fail
0.0117
117
Combined Failure Rate:
FITs:
• *S.SV and 7V burn·in/lifetest equivalent hours have been combined.
OJa
= 90·C/W (Est.)
VCC
ICC@ 55·C
ICC @ 125·C
ICC (max)
= 5.5V
Temp. with Tja
T(55)
T(125)
BI/ELT
Accel.
Factors:
= 60 rnA
0.3eV
0.5eV
1.0 eV
Thermal Accel.
Factors
SS·C
3.42
7.67
58.96
= 20 rnA
= 75 rnA (Spec)
Voltage Accel. Factor (VAF): 12.7
= 358K
K
=
= 8.62E -05 eV/K
411K
NOTE:
FIT = Failures in Time. 1 FIT = 1 Failure per 10E
+
09 device hours.
Failure Analysis:
All failures assumed to be Oxide related.
Table 3. Additional Qualification Tests
Year
1988/89
1000 Hours
8S·C/8S% R.H.
204 Hrs
Steam
1000
Temp Cycles
1S0·CI1K Hrs
High Temp Storage
6/2310
2/1320
5/564
1/1100
(0.25%)
(0.15%)
(0.6%)
(0.10%)
Table 4. System SER Result
Vee
Cycle Time
Device Hours
# of Errors
FIT (60%)
5V
1 IJ-s
1.4M
o
630
3-163
RR-62
21010
Process: CMOS
Package: 18-Pin PDIP
Number of bits: 1,048,576
Organization: 1M x 1
Table 1. Reliability Data Summary
7V Dynamic Lifetest
Year
I
I
168 Hrs
1988/89
7/2060
I
I
SOO Hrs
4/2053
1000 Hrs
4/2049
Table 2. Failure Rate Predictions
12S·C Actual
Device Hours
Ea
(eV)
19E
+ 05
+ 05
19E + 05
0.3 )
19E
0.5
Equivalent Hours
atSS·C
#
Fail
+ 06
+ 06
112E + 06
1.0
Fail Rate %/1'K Hours
(60% UCL)
82E
15
0.0204
15E
0
0.0070
0
0.0009
Combined Failure Rate:
FITs:
90·C/W (Est.)
9Ja
=
Vcc
Icc@ 55·C
Icc@ 125·C
Icc (max)
= 5.5V
Temp. with Tja
T (55)
T (125)
=
BI/ELT
Accel.
Factors:
60mA
0.0283
283
Thermal Accel.
Factors
SS·C
3.42
7.67
58.96
0.3eV
0.5eV
1.0eV
= 20mA
=
75 mA (Spec)
Voltage Accel. Factor (VAF): 12.7
=
358K
411K
K
=
NOTE:
FIT = Failures in Time. 1 FIT = 1 Failure per 10E
+
=
8.62E -05 eViK
09 device hours.
Failure Analysis:
All failures assumed to be Oxide related.
Table 3. Additional Qualification Tests
Year
1988/89
1000 Hours
8S·C/8S%. R.H.
204 Hrs
Steam
1000
Temp Cycles
1S0·C/1K Hrs
High Temp Storage
9/2410
1/2420
1/1906
3/2140
(0.3%)
(0.04%)
(0.05%)
(0.14%)
Table 4. System SER Result
Cycle Time
Device Hours
'# of Errors
FIT (60%)
1 JLs
1.2M
o
763
3-164
inter
RR-62
Table S. Latch-Up/ESD Test Results
# of Runs
Sampl~Size
Latch-Up Level
ESD Level
5
25 Units
>125 rnA
> 2500V
SOJ Package Qualification Data Summary
Year
1000 Hours
8S·C/8S% R.H.
204 Hours
Steal11
1000
Temp Cycles
1988/89
1/645
(0.16%)
2/504
(0.4%)
1/300
(0.3%)
21014
Number of bits: 1,048,576
Organization: 256K x 4
Process: CMOS
Package: 20-Pin PDIP
Table 1. Reliability Data Summary
High Voltage (7V) Dynamic Lifetest
Year
168 Hrs
3/600
1989
I
I
SOO Hrs
1/597
I
I-
1000 Hrs
0/597
Failure Rate Prediction:
Due to small number of actual device hours on this new product, a detailed reliability prediction would not be meaningful.
Table 2. Additional Qualification Tests
Year
1000 Hours
8S·C/8S% R.H.
204 Hrs.
Steam
1000
Temp Cycles
1S0·C/1K Hrs
High Temp Storage
1989
1/250
(0.40%)
1/500
(0.20%)
0/250
(0.0%)
0/500
(0.0%)
3-165
inter
RR-62
APPENDIX A
COMMON MOS· FAILURE MECHANISMS
Oxide Defects
Contamination
Oxide defects cim cause dielectric breakdown in MOS
structures, resulting in: an electrical short. Oxide dielectric breakdown is dependent on time, ambient temperature and operating voltage. Oxide defects could be induced by excessively thin oxide, polarization and contamination. The activation energy for Oxide defects is
determined to be 0.3 eV.
MOS circuits can fail due to threshold voltage (Vt)
shifts when subjected to mobile ionic contamination.
This ionic contamination reaches critical circuits
through passivation defects subsequent to wafer processing. Sodium is the most common species of ionic
contamination. The activation energy of ionic contamination is 1.0 eV.
Silicon Defects
Metallization Defects
Silicon defects are inherent in the unprocessed silicon
wafers and may also be generated by stresses on the
lattice during MOS processing. These silicon defects enhance parasitic leakage when they become active by
"gettering" contaminants. The activation energy for silicon defects is determined to be 0.5 eV.
Metallization defects (defects relating to metal conductor paths on the semiconductor die) can occur due to
metal contamination, excess current density (electromigration) in the conductors, microcracks caused by
sharp oxide steps and overalloying due to migration of
metal through the semiconductor's contact. The activation energy is 0.5 eV.
Refresh Degradation
In general, refresh failures are the result of degradation
of random single bits caused by localized carrier generation. A localized silicon defect can act as a gathering
site for contaminants and if this defect is located near a
storage cell, it can cause this isolated cell to have poor
refresh characteristics. The activation energy of refresh
degradation is 0.5 eV.
Sof~
Errors
Soft errors refer to random non-recurring single bit er. rors and can be generated by noise in the device or
system or by impact ionization from alpha particles.
Alpha particles originating in the package penetrate the
die surface, sometimes generating sufficient charge to
switch the logic state of a cell. Soft error rates can be
reduced by using low alpha packaging materials, die
coating to prevent alpha particles from reaching the
chip surface and optimal circuit designs to resist alpha
particle disturbances.
3-166
Static RAMs
(Random Access Memories)
4
5116S/L
2K x 8-BIT CMOS STATIC RAM
•
•
•
51165·10
51165·12
Address Access Time (tAA)
100
120
ns
Chip Select Access Time (tACS)
100
120
ns
Output Enable Access Time (tOE)
40
50
ns
•
•
•
•
Static Operation
- No Clock/Refresh Required
Equal Access and Cycle Times
- Simplifies System Design
Single
+ 5V Supply
Unit
Power Down Mode
TTL Compatible
Common Data Input and Output
High Reliability 24·Pin 600 Mil PDIP
Package
The 5116S is a 2048-word by 8-bit CMOS static RAM fabricated using CMOS Silicon Gate process.
When the Chip Select is brought high, the device assumes a standby mode in which the standby current is
reduced to 2 p,A (max). The 5116S has a data retention mode that guarantees that data will remain at
minimum power supply voltage of 2.0V.
Block Diagram
Pin Connections
vee
~
~
128 x 128
MEMORY ARRAY
GND
•••••••
COLUMN I/O
240571-2
Pin Names
cs 0o:::.:.r:CO:N~TR:O::-L'
CE
WE
CIRCUIT
....
t----------------4~
O---L::=::.:......J
240571-1
4-1
AO-A1,O
Address Input
Do-D7
Data Input/Output
CS
Chip Select Input
WE
Write Enable Input
OE
Output Enable Input
VCC
Power
GND
Ground
October 1989
Order Number: 240571-002
inter
5116S/L
Device Operation
Write Mode
The 5116S has two control inputs: Chip Select (CS)
and Write Enable (WE). CS is the power control pin
and should be used for device operation. WE is the
data control pin and should be used to gate data at
the 1/0 pins.
Write Cycles may be controlled by either WE or CS.
In either case, both WE and CS must be high (VIH)
during address transitions. During a WE Controlled
write cycle, CS must be held low (Vld while WE is
low. Address transfers occur on the falling edge of
WE and the data transfers on rising edge of WE.
During a CS controlled cycle, WE must be held low
(Vld while CS is low. The addresses are then transferred on the falling edge of CS and data on the
rising edge of CS. Data, in both cases, must be valid
for a time tDW before the controlling input is brought
high (VI H) and remain valid for a time tDH after the
controlling input is high.
Standby Power
The 5116S is placed in a standby or reduced power
consumption mode by applying a high (VIH) to the
CS input. When in standby mode, the device is deselected and the outputs are in a high impedance
state, ind.ependent of the WE input.
Read Mode
Table 1. Mode Selection Truth Table
CS
WE
OE
Mode
I/O
Power
H
X
X
Standby
HighZ
Standby
L
L
X
Write
DIN
Active
L
H
L
Read
Dour
Active
L
X
H
Read
HighZ
Active
CS must be low (Vld and WE must be high (VIH) to
activate a read cycle and obtain data at the outputs.
Given stable addresses, valid data is available after
a time tAA.
4-2
inter
5116S/L
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative
to Ground (VIN' VOUT) ..•........ -0.3V to
Storage Temperature (Tstg) ..... - 55°C to
NOTICE: This is a production data sheet. The specifi·
cations are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex·
tended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 7V
+ 150°C
Power Dissipation (Po) ..................... 1.0W
DC Continuous Output Current (los) ......... 50 mA
RECOMMENDED OPERATING CONDITIONS
Symbol
Voltage referenced to Vss, TA = O°C to 70°C
Parameter
Min
Typ
Max
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
Vss
Ground
0
0
0
V
VIH
Input High Voltage
2.2
Vee + 0.3
V
Input Low Voltage
-0.3
0.8
V
VIL
NOTE:
1. During transitions, the inputs may undershoot to - 3.5V for periods less than 20 ns.
CAPACITANCE
Symbol
TA
=
25°C, f
=
1.0 MHz
Parameter
Min
=
CIN1
Input Capacitance (VIN
COUT
Output Capacitance (VOUT
OV)
=
OV)
NOTE:
This parameter is sampled and not 100% tested.
'4-3
Max
Unit
6
pF
8
pF
inter
5116S/L
D.C. AND OPERATING CHARACTERISTICS
Recommended Operating Conditions unless otherwise noted
Symbol
Typ
Max
Units
leGl
Operating Current
Parameter
30
40
rnA
Vee = Max, ~
Outputs open
lee2
Dynamic Current
30
60
rnA
T eye = Min, Vee
Outputs open
3
rnA
9S = VIH
p.A
CS;::;' Vee - 0.2V
VIN = GND to Vee
Min
19B
ISBl
Standby
Current
I
I
STD
L
4
50
0.2'
2
:rest Conditions
=
VIL
=
Max
III
Input Load Current
-1
1
/LA
Vee = Max
VIN = GND to Vee
ILO
Output Leakage
-1
1
/LA
CS = VIH, Vee = Max
VOUT = GND to Vee
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
0.4
=
V
IOH
-1.0mA
V
IOL = 2.1 rnA
*TA = 25'e
DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
VeoR
Voltage for Data Retention
leeOR
Data Retention Current
teoR
Chip Deselect to
Data Retention Time
tR
Operation Recovery Time
Min
. Typ
Max
Units
2
/LA
V
2
CS;::;' Vee - 0.2V
VIN ;::;, Vee - 0.2V
0.05
0
ns
tRe
ns
Low Vee Data Retention Waveform
DATA RETENTION MODE
vee
4.SV
VDR >2V
4.SV
~DON'T CARE
240571-3
4-4
5116S/L
Timing Reference Level ..................... 1.5V
A.C. TEST CONDITIONS
Output Load ................ 1 TTL Load
Input Pulse Levels ................... 0.8V to 2.4V
+
100 pF
Input Rise and Fall Times ................... 10 ns
A.C. CHARACTERISTICS
TA
=
O·C to 70·C, Vcc
=
5V ± 10%
READ CYCLE
Symbol
51165·10
Parameter
Min
Max
100
51165·12
Min
Unit
Max
tRC
READ Cycle Time
tAA
Address Access Time
120
tACS
Chip Select Access Time
tOH
Output Hold from
Address Change
10
10
ns
tCLZ
Chip Selection to
Output in Low Z
10
10
ns
tcHZ
Chip Deselection to
Output in High Z
0
tOE
Output Enable
Access Time
40
50
ns
toLZ
Output Enable to
Output in Low Z
10
10
ns
tOHZ
Output Enable to
Output in High Z
0
100
100
40
40
0
0
ns
120
ns
120
ns
40
40
ns
ns
READ CYCLE NO. 1(1)
1--------
t Rc - - - - - - - - 1
ADDRESS
DATA OUT
240571-4
4-5
intJ
5116S/L
READ CYCLE NO. 2(1,2,4)
ADDRESS
-E ~? }
k1
DATA OUT _________~_",/,I,ljX~X~~=======D=AT=A=VA=L=ID======l=~====
240571-5
READ CYCLE NO.3(1, 3, 4)
DATA OUT
240571-6
NOTES:
1. WE is high for READ Cycle. The first transitioning address.
2. Device is continuously selected; es = VA:.
3. Address valid prior to or coincident with CS transition low.
4. OE = VIL.
5. Transition is measured at ± 500 mV from steady. state voltage.
A.C. CHARACTERISTICS
TA = 0·Cto70·C, Vee = 5V ±10% (Continued)
WRITE CYCLE
Symbol
51165-10
Parameter
Min
51165-12
Max
Min
Unit
Max
twc
WRITE Cycle Time
100 .
120
ns
tew
Chip Selection to
End of Write
65
70
ns
tAW
Address Valid to
End of Write
80
105
ns
tAS
Address Set-Up Time
0
0
ns
twp
Write Pulse Width
60
70
ns
tWR
Write Recovery Time
10
10
ns
tDW
Data Valid to End
of Write
30
35
ns
tDH
Data Hold Time
10
tWHZ
Write Enable to
Output in High Z
0
tow
Output Active from
End of Write
10
toHZ
Output Disable to
Output in High Z
0
10
30
ns
35
10
40
4-6
0
0
ns
ns
40
ns
infef
5116S/L
WRITE CYCLE NO. 1(1)
Iwe
ADDRESS
f---oo
IIIIIIIII/:
IWR(3)
~\\\\\\\\\
lew
\\\ \ \ \ \ \ \ \' \\\\~
(5)
VIIIIIIIII~
lAW
--! lAS
\\\\~
IOHZ{4, 10)
==1
Iwp(2)
"
DATA OUT
II
lOW
DATA IN
DATA IN VALID
"
IOH
:XXXXXXXX
240571-7
WRITE CYCLE NO. 2(1, 6)
Iwe
ADDRESS
lew
\\\\\\'\ ,\\ \\\2
(5)
~ t WR (3)
'1/ 'II I I I II
lAW
t wp(2)
~\\W
lAS
DATA OUT
H
;:;:j t WHZ{4,lO)
V&
r\C::J ~
II
r.
DATA IN
I--loH ...tOW{l~
tow------+.I_. IOH:l(9)
----------------i~::======~~~~~IN~V~AL~ID======:tJ~)(~)(~)(~)(
240571-8
NOTES:
1. WE must be high during address transitions.
2. A Write occurs during the overlap (twp) of a low CS and a low WE.
3. All Write Cycle timings are referenced from the last valid address to the first transitioning address.
4. During this period, 1/0 pins are in tri-state.
5. If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in tristate.
6. OE is continuously low (OE = VIU.
7. DOUT is the same phase of write data on this write cycle.
8. DQUJ is the read data of next address.
9. If CS is low during this period, I/O pins are in output state.
10. Transition is measured at ±500 mV from steady state voltage.
4-7
5116S/L
PACKAGE OUTLINE
24-DIP
Normal
24
5:::f::fB
1
12.1
@
~t~'1
~ l=!.Jb
o
~~i~
0° .... 150
240571 9
4-8
(j)
13.2±0.25
Shrink
6.35±0.2
®
31.0±0.3
22.0±0.25
@
15.24TYP .
7.62TYP.
@)
4.25±0.2
3.45±0.2
®
5.1 ±0.2
4.2±0.2
@
P-2.54TYP.
P-1.778TYP.
(lJ
0.5±0.1
0.46+ 0.1
5164S/L
8K x 8-BIT CMOS STATIC RAM
5164S/L-07
5164S/L-10
Units
Address Access Time (tAA)
70
100
ns
Chip Select Access Time (tAes)
70
100
ns
Output Enable Access Time (tOE)
35
55
ns
Operation
• -Static
No Clock/Refresh Required
Access and Cycle Times
• -Equal
Simplifies System Design
• Single + 5V Supply
Power Down Mode
• TTL
Compatible
• Common
Data Input and Output
• High Reliability
28-Pin 600 Mil PDIP and
• 28-Pin SOP Package
Types
The 5164S/L is a 8192-word by 8-bit CMOS static RAM fabricated using CMOS Silicon Gate process.
The 5164S/L is placed in a standby or reduced power consumption mode by asserting either CS input (CS1,
CS2) false. When in standby mode, the device is deselected and the outputs are in a high impedance state,
independent of the WE input. When device is deselected, standby current is reduced to 100 IJ-A (max). The
device will remain in standby mode until both pins are asserted true again. The device has a data retention
mode that guarantees that data will remain valid at minimum Vee of 2.0V.
Pin Connections
Block Diagram
~vcc
256 x256
~GNO
Memory Array
0,
O2
GNO
240570-2
Pin Names
Ao-A12
240570-1
4-9
Address Input
Do-D7
Data Input/Output
CS1
Chip Select One
CS2
Chip Select Two
WE
Write Enable
OE
Output Enable
Vee
Power
GND
Ground
April 1990
Order Number: 240570-004
5164S/L
earliest transitiion of CS1, high WE or low CS2. Out
Enable (DE) is used for precise control of the outputs.
Device Operation
The 5164S/L has three control inputs: Two Chip Selects (CS1, CS2) and Write Enable (WE). WE is the
data control pin and should be used to gate data at
the I/O pins. A write cycle starts at the lowest transition of CS1, low WE or high CS2 and ends at the
The availability of active high and active low chip
enable pins provides more system design flexibility
than single chip enable devices.
Table 1. Mode Selection Truth Table
CS1
CS2
WE
OE
Mode
I/O
Power
H
X
X
X
Standby
HighZ
Standby
X
L
X
X
Standby
HighZ
Standby
L
H
L
X
Write
DIN
Active
L
H
H
L
Read
DOUT
Active
L
H
H
H
Read
HighZ
Active
ABSOLUTE MAXIMUM RATINGS
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Voltage on Any Pin
Relative to Ground (VIN, VOUT) ..... -0.3V to 7V
Storage Temperature (TSTG) .... - 55·C' to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 150·C
Power Dissipation (Po) .....•............... 1.0W
DC Continuous Output Current (los) ......... 50 rnA
RECOMMENDED OPERATING CONDITIONS
Voltage referenced to Vss, T A = O·C to 70·C
Symbol
Parameter
Min
Typ
Max
Units
Vee
Supply Voltage
4.5
5.0
5.5
V
VSS
Ground
0
0
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.3
-
Vee
0
V
+ 0.3
V
V'
0.8
NOTE:
1. During transitions, the inputs may undershoot to -3.5V for periods less than 20 ns.
CAPACITANCE
Symbol
TA
= 25·C, f =
1.0 MHz
Parameter
=
CIN1
Input Capacitance (VIN
COUT
Output Capacitance (VOUT
OV)
=
NOTE:
This parameter is sampled and not 100% tested.
4-10
OV)
Min
Max
Units
-
6
pF
8
pF
intJ
5164S/L
D.C. AND OPERATING CHARACTERISTICS
Recommended Operating Conditions unless otherwise noted
Symbol
Min
Typ'
Max
Units
ICC1
Operating Current
Parameter
-
30
40
mA
CS1 = VIL, CS2 = VIH
1/0 Open, Vcc = Max
ICC2
Dynamic Current
-
30
60
mA
TCYC = Min, Vcc = Max
1/0 Open
-
3
mA
CS1 = VIH or CS2 = VIL
0.02
2
mA
2
100
p.A
CS1 ~ Vcc - 0.2V
VIN ~ Vec - 0.2V or VIN
ISB
sm
ISB1
Standby
Current
ISB2
L
-
sm
L
Test Conditions
< 0.2V
0.02
2
mA
CS2 ~ Vce - 0.2V
-
2
100
p.A
VIN ~ Vce - 0.2V or VIN ~ 0.2V
-
1
p.A
Vce = Max
VIN = GND to Vee
CS1 = VIH, CS2 = VIL
VOUT = Ground to Vcc
III
Input Load Current
-1
ILO
Output Leakage
-1
-
1
p.A
VOH
Output High Voltage
2.4
-
-
V
IOH =' -1.0 mA
VOL
Output Low Voltage
-
-
0.4
V
IOl = 2.1 mA
'Vcc = 5V, T A = 25'C
DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min
VeDR
Voltage for Data Retention
2
IceDR
Data Retention Current
tCDR
Chip Deselect to
Data Retention Time
tR
Opeation Recovery Time
• 'tRC
Typ
Max
-
Units
Test Conditions
V
-
1
p.A
CS1 ~ Vec - 0.2V
VIN ~ Vcc - 0.2V or VIN ~ 0.2V
-
1
p.A
CS2 ~ 0.2V
YiN ~ Vec - 0.2V or VIN ~ 0.2V
0
-
-
ns
tRC"
-
-
ns
= Read Cycle Time
4-11
inter
5164S/L
Low Vee Data Retention Waveform
DATA RETENTION MODE
VCC - - - - - - - - - - - - - ,
4.SV - - - - - - - - - - - - - -
Cs 1 C!:VCC -O.2V
cs 1 - - - - -
OV------------------------------------------------
240570-3
DATA RETENTION MODE
VCC-----------~
4.SV - - - - - - '- - - - - -
cs 2 - - - - _
VOR2
O.4V - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CS 2 ::SO.2V
OV------------------------------------------------
4-12
240570-4
5164S/L
A.C. TEST CONDITIONS
Input Pulse Levels ................... O.BV to 2.4V
Input Rise and Fall Times .................... 5 ns
Timing Referen,ce Level .................... : 1.5V
Output Load ................ 1 TTL Load
+
100 pF
A.C. CHARACTERISTICS
= o·c to 70·C, Vcc = 5V ± 10%
TA
READ CYCLE
Symbol
Parameter
5164S/L-07
Min
Max
5164S/L-10
Min
Units
Max
tRC
READ Cycle Time
tAA
Address Access Time
70
100
ns
tACS
Chip Select Access Time'
70
100
ns
tOH
Output Hold from
Address Change
10
10
ns
tCLZ
Chip Selection to
Output in Low Z'
5
10
ns
tCHZ
Chip Deselection to
Output in High Z·
0
tOE
Output Enable Access Time
35
55
ns
tOLZ
Output Enable to
Output in Low Z
5
5
ns
toHZ
Output Disable to
Output in High Z
0
70
"Timing parameters referenced to both CS1 and CS2.
4-13
100
30
30
0
0
ns
35
35
ns
ns
inter
5164S/L
TIMING DIAGRAMS
READ CYCLE 1(1,2,4)
Address --4
IRC
~
Dala Oul ~----'==J~I~:~~~~I~OH2IM~~~~§l~'xx~*['====Da::J=IV;a;lId;.;IO~H=1=
240570-5
READ CYCLE 2(1,3,4,6)
t !cHI'=!
cs,~
~~(::====:IC::i~i.:~--=c1;,;:==::j,.------......
~
Data Out
~
Data Valid
240570-6
READ CYCLE 3(1, 4, 7)
Cs 2
--f
{ .
~IcL~~~t.----_~_IcHIZ1
~
Dato Out
=1--
Data Valid
240570-7
READ CYCLE 4(1)
IRC
1M
Address
Z '/L// I I/J /1/.
\.\.\.\\. ,\.\.\.\.\.'-\.\.\''-'k
~~
cs,
\.\.\.\.\.
CSz
11111,
lACS'
IACS2
-IoH-
II 'IIIIII/J /1111
leu,
,\. \. ,\. \.\. \.\.\.\.\ r-,.\. .\.\.
!---ICHIZ(Z,S)-r! - - - I CH1 ,(3) -
leuz
Data Out
Data Valid
,X
240570-8
NOTES:
1. WE is high for READ cycle.
2. Device is continuously selected CS1 = VIL and CS2 = VIH.
3. Address valid prior to or coincident with CS1 transition low.
4. OE = VIL.
S. Transition is measured ± SOO mV from steady state. This paramete~ is sampled and not 100% tested.
6. CS2 is high.
7. CS1 is low.
4-14
inter
5164S/L
A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
Symbol
5164S/L-07
Parameter
Min
5164S/L·10
Max
Min
Units
Max
twe
Write Cycle Time
70
100
ns
tew
Chip Selection to
End of Write
60
70
ns
tAW
Address Valid to
End of Write
60
80
ns
tAS
Address Set-Up Time
0
0
ns
twp
Write Pulse Width
40
60
ns
tWR
Write Recovery Time
10
15
ns
tow
Data Valid to End
of Write
30
40
ns
tOH
Data Hold Time
0
15
ns
tWHZ
Write Enable to
Output in High Z
0
tow
Output Active from
End of Write
5
tOHZ
Output Disable to
Output in High Z
0
30
0
35
10
ns
0
30
ns
35
ns
WRITE CYCLE 1(1)
twc
Address
tWR1 (3)
,/1111111
tew1 (11)
CS 1
\"-\\~\~\\ --\\\\\\\\,
(5)
~/III
11111111, '11111111
VIIIIIIIII
.\\\\ ,\\\\\\\\\
tew2 (11)
tAW
tWR2 (3)
HtAS
,,\\\
tWHZ (410)
Data Out
Data
\\\~"
tWP (2)
J
~
.1.
In ---------------<(If===]D~ot!O~ln~VO~Ii!d=~:Jtxx~xx~Xgggxg
tow
tOH
240570-9
4-15
inter
5164S/L
WRITE CYCLE 2(1,6)
IWC
Address
cs, ,\.\. \.
\.\.\.\.\.\.\.\.\.\.\.
tWR1 (3)
ICW1 (11)
(5)
'//. '/ / / / / / / / / / / / /
'III. IIIIIIIIIII
/
(\.\. ,\.\.\.\.\.\.\.\.\.\.\.\.\.\
1cw2(11)
IWR2 (3)
lAW
tWP (2)
.1
\:\.\.\.\.\.\.\.\.\:
- IAS
..!::::::::::1
--!
tWHZ (410)
-
I--to~.
IoW(10)
(7)
Data Oul
'1
C
Data In
1
ID~(9)1
IOW
(8)
x:
DoIa In Valid
I
240570-10
NOTES:
1. WE must be high during address transitions.
2. A write occurs during the overlap (twp) of a low CS, a high es, and a low WE.
3. tWR is measured from the earlier of es or WE gOing high or es going low to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input Signals of opposite phase to the outputs must not be
applied.
5. If the CS low transition or the es high transition occurs simultaneously with the WE low transitions or after the WE
transition, outputs remain in a high impedance state.
6. OE is continuously low (OE = VII)
7. DOUT is the same phase of write data of this write cycle.
8. DQUJ is the read data of next address.
9. If CS is low and CS is high during this period, 1/0 pins are in the output state. Then the data input signals of opposite
phase to the outputs must not be applied to them.
10. Transition is measured ±500 mV from steady state. This parameter is sampled and not 100% tested.
.
11. tow is' measured from the later of es going low or es going high to the end of write.
PACKAGE OUTLINE
28·DIP
---e----+----e--
00
.....
150
J
1.465(37.2)
MAX
240570-11
Units = millimeter (mm)
4-16
5164S/L
PACKAGE OUTLINE
28·PIN sOP
28- 0.4:1:0.1
P- 1.27TYP.
11
28
-t+-l$1 ~ 0.12 @I
II 1'5
.
---;:;.--
N
ci
-It
++1
240442-3
Figure 1. Block Diagram
DEVICE OPERATION
Write Mode
The 51C98 has two control inputs: Chip Select (CS)
and Write Enable (WE). CS is the power control pin
and should be used for device operation. WE is the
data control pin and should be used to gate data at
the liD pins.
Write Cycles may be controlled by either WE or CS.
In either case, both WE and CS must be high (VIH)
during address transitions. During a WE Controlled
write cycle, CS must be held low eVIL! while WE is
low. Address transfers occur on the falling edge of
WE and the data transfers on rising edge of WE.
During a CS controlled cycle, WE must be held low
(Vld while CS is low. The addresses are then transferred on the falling edge of CS and data on the
rising edge of CS. Data, in both cases, must be valid
for a time tow before the controlling input is brought
high (VI H) and remain valid for a time tOH after the
controlling input is high.
Standby Power
The 51C98 is placed in a standby or reduced power
consumption mode by applying ii high (VI H) to the
CS input. When in standby mode, the device is deselected and the outputs are in a high impedance
state, independent of the WE input.
Table 1. Mode Selection Truth Table
CS
WE
Mode
1/0
Power
H
X
Standby
High-Z
Standby
L
L
Write
DIN
Active
L
H
Read
DOUT
Active
Read Mode
cs must be low (Vld
and WE'must be high (VIH) to
activate a read cycle and obtain data at the outputs.
Given stable addresses, valid data is available after
a time tAA.
4-33
51C98
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Voltage on Any Pin Relative
to Ground (VIN. VOUT) ..•...... -1.0V to + 7.0V
Storage Temperature (Ceramic)
(Tstg) .....•............•... - 65°C to + 150°C
• WARNING: Stressing the device beyond the ''Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the ."Operating Conditions"
may affect device reliability.
Power Dissipation (Po) ..................... 1.0W
DC Continuous Output Current (los) ......... 50 mA
RECOMMENDED OPERATING CONDITIONS
Voltage referenced to Vss. TA = O°C to
Symbol
+ 70°C
Parameter
Min
Typ
Max
Units
Vee
Supply Voltage
4.5
5.0
5.5
V
Vss
Ground
0
0
0
V
VIH
Input High Voltage
2.2
Input Low Voltage
-0.5
Vil
Vee
+1
O.S
V
V
NOTE:
,
1. During transitions. the inputs may undershoot to - 2.0V for periods less than 20 ns.
CAPACITANCE
TA =
+ 25°C. f =
Symbol
1.0 MHz
Min
Parameter
Max
Units
CIN1
Input Capacitance (VIN = OV)
7
pF
COUT
Output Capacitance (VOUT = OV)
7
pF
NOTE:
This parameter is sampled and not 100% tested.
D.C. AND OPERATING CHARACTERISTICS
Recommended Operating Conditions unless otherwise noted
Symbol
Parameter
Max
Units
100
mA
Vee = Max
CS = Vil. Outputs
Open. T cycle = Min
15
mA
Vee = Min to Max
CS = VIH
-10
10
p.A
Vee = Max
VIN = GND to Vee
Output Leakage
-10
10
p.A
CS = VIH. Vee = Max
VOUT = GND to 4.5V
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
Icc
Operating Current .
ISB
Standby Current
III
Input Load Current
tlO
Min
0.4
4-34
Test Conditions
V
tOH =-4mA
V
tOl = SmA
infef
51C98
DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VeDR
Voltage for Data
Retention
leCDR
Data Retention
Current
teDR
Chip Deselect to
Data Retention
Time
tR
Operation Recovery
Time
Min
.Typ
Max
Test Conditions
Units
2
V
95
350
500
750
0
ns
tRe
ns
i
CS :;:: Vee - 0.2V
VIN:;:: Vee - 0.2V
or::; 0.2V
}J-A
/LA
Vee
Vee
= 2V
= 3V
j
Low Vee Data Retention Waveform
Vee
DATA RETENTION MODE
-:.SV
teOR
VOR >2V
.
4.S~
6
tR
~.~~.~~
VORo/#&
~
DON'T CARE
240442-4
A.C. TEST CONDITIONS
Input Pulse Levels ................... GND to 3.0V
Input Rise and Fall Times ...... '.............. 5 ns
Timing Reference Level ........... '.......... 1.5V
Output Load ..................... See Figures 2, 3
167.11
167.11
DOUT~I.73V
DOUT~I.73V
~5PF
~30PF
240442-5
240442-6
Figure 2. Output Load
Figure 3. Output Load for tHZ. tLZ. twz. tow
4-35
intJ
51C98
A.C. CHARACTERISTrcs
= o·c to +70·C, Vcc = 5V ± 10%
TA
READ CYCLE
Symbol
51C98·20
Parameter
Min
Max
20
51C98-25
Min
Max
25
51C98-30
Min
Units
.Max
tRC
READ Cycle Time
tAA
Address Access Time
20
25
30
ns
tACS
Chip Select Access Time
20
25
30
ns
tOH
Output Hold from
Address Change
3
3
3
ns
tlZ
Chip Selection to
Output in Low-Z
0
0
0
ns
tHZ
Chip Deselection to
Output in High-Z
tpu
Chip Selection to
Power Up Time
tPD
Chip Deselection to
Power Down Time
15
30
15
0
0
20
ns
20
0
25
ns
ns
30
ns
NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage. tHz(Max) is less than tLz(Min). both for a given device and from device to device.
3. Transition is measured at ± 500 mV from steady state voltage with specified loading in Figure 3.
READ CYCLE NO. 1<1,2)
t Rc
ADDRESS
tAA
- tOH DATA OUT
PREVIOUS DATA VALID
XX
DATA VALID
240442-7
4-36
51C98
READ CYCLE NO. 2(1,3)
1---------tRc-------------I
_
DATA OUT
~fil,PLY
f {) "
_ t LZ
J
tACS
-1~H~IG~H~IM~P~ED~A~NC!E__~i[1<~V*=:::::::!~~~::~::::*,~H~IG~Har1\\
DATA VALID
IMPEDANCE
ICC --
_r:-:. !ll..~
CURRENT ISS
~ tPD:l
r--
. 50%
240442-8
NOTES:
1. WE is high for Read Cycles.
2. Device is continuously selected. CS = VIL.
3. Addresses valid prior to or coincident with CS transition low.
A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
Symbol
Parameter
51C98-20
Min
51C98-25
Max
Min
Max
51C98-30
Min
Units
Max
twc
Write Cycle Time(1)
20
25
30
ns
tew
Chip Selection to
End of Write
15
20
25
ns
tAW
Address Valid to
End of Write
15
20
25
ns
tAS
Address Set-Up Time
0
0
0
ns
twp
Write Pulse Width
15
20
20
ns
2
2
2
ns
tDW
Data Valid to End
of Write
12
15
15
ns
tDH
Data Hold Time
0
0
0
ns
twz
Write Enable to
Output in High-Z(2)
0
tow
Output Active from
End of Write(2)
0
tWR
_Write Recovery Time
15
0
0
4-37
15
0
0
15
ns
ns
inter
51C98
WRITE CYCLE NO. 1 (WE CONTROLLED)(3)
~----------------~c----------------~
~-----------t~------------~
cs ~m~1
1n"7"'J"'l"lr-rrm"'J"'l"lr-rr""-'"'J"'l"lr-rr'1"l
WE
DATA IN
DATA IN VALID
______________~------'I~------~-JI'---------------
-+~_to_w_1-1""'-------
DATA OUT ----DA-l:-A-UN-D-m-N-E-D-I---t-.WZ-]......:.:HI;;:GH::..::;:IM;.:PE;:;DA;,;:N;;;C:.E
240442-9
NOTES:
1. All Write Cycle timings are referenced from the last valid address to the first transitioning address.
2. Transition is measured at + 500 mV from steady state voltage with specified loading in Figure 3.
3. CS or WE must be high during address transitions.
WRITE CYCLE NO.2 (CS' CONTROLLED)(1, 2)
twc
ADDRESS
~
:-tAS
tAW
~twR-
twp
r///////////////////////~
0.\\\\\\\\~
.C
tow
DATA IN
~~OUT
X
______________
DATA INVALID
~HI;;:GH::..::;:IM;.:PE;:;DA;,;:N;;;C:.E
/OH
X
_ _ _ _ _ _ _ _ __
240442'"10
NOTES:
1. CS or WE must be high during address transitions.
,
2. If CS switches low coincident with or after WE switches low. the outputs will stay in a high impedance state. If CS
switches high or coincident with or after WE switches high, the outputs will stay in a high impedance state.
4-38
5164
HIGH SPEED 8192 x 8-BIT STATIC RAM
5164-20
5164-25
5164-30
5164-35
20
120
30
25
110
30
30
100
30
35
100
30
Max Access Time (ns)
Max Active Current (rnA)
Max Standby Current (rnA)
•
•
Static Operation
- No Clock/Refresh Required
•
Single
•
•
•
•
•
Equal Access and Cycle Times
- Simplifies System Design
+ 5V Supply
Power Down Mode
TTL Compatible
Common Data Input and Output
28-Pin 300 Mil Plastic Package
2V Data Retention Option Available
The 5164 is a 65,536-bit high speed static RAM configured as 8K x 8. Easy memory expansion is available with
two chip enables (CS1 and CS2) and an Output Enable (OE).
The power down feature contributes greatly to system reliability. The device's power consumption is reduced
when in this low power standby mode. In fact, 85% system power reduction is achievable in large systems
where a majority of the devices are deselected.
Functional Block Diagram
•
256 x 256
MEMORY ARRAY
Pin Configurations
COLUMN I/O
C~~~~~L
1-------------.....- . .
240674-1
240674-2
Pin Names
Ao-A12
Address
WE
II01-IIOS
Data Input/Output
OE
Write Enable
Output Enable
CS1
Chip Select
GND
Ground
CS2
Chip Select
Vee
Power
4-39
May 1990
Order Number: 240674-002
inter
5164
Device Operation.
Standby Power
The 5164 has three control inputs: Two Chip Selects
(CSt, CS2) and Write Enable (WE). WE is the data
control pin and should be used to gate data at the
1/0 pins. When CS1 and WE inputs are LOW and
CS2 is HIGH, data is written into the memory and
reading is accomplished when g§1 and OE are active LOW, CS2 aCtive HIGH and WE remains inactive
or HIGH.
The 5164 is placed in a standby or reduced power
consumption mode by applying a high (VI H) to the
CS1 input or low (VILl to the· CS2 input. When in
standby mode, the device is deselected and the outputs are in a high impedance state, independent of
the WE input.
Table 1. Mode Selection Truth Table
CS1
CS2
WE
OE
H
X
X
X
L
X
L
L
L
Mode
I/O
Power
X
Standby
HighZ
Standby
X
Standby
HighZ
Standby
H
L
X
Write
DIN
Active
H
H
L
Read
DOUT
Active
H
H
H
Read
HighZ
Active
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin
Relative to Ground (VIN, VOUT) ... -1.0V to
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
+ 7V
Storage Temperature
(Ceramic) (TSTG) ............ - 65°C to + 150°C
Power Dissipation (Po) ..................... LOW
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended. exposure beyond the "Operating Conditions"
may affect device reliability.
DC Continuous Output Current (los) ......... 50 mA
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T A = O°C to 70°C)
Symbol
Parameter
Min
Typ
Max
Unit
Vee
Supply Voltage
4.5
5.0
5.5
V
Vss
Ground
0
0
VIH
Input High Voltage
2.2
VIL
Input Low Voltage
-0.5
Vee
0
V
+ 0.5
V
0.8
V
NOTE:
1. During transitions, the inputs may undershoot to -2.0V for perio.ds less than 20 ns.
CAPACITANCE
(TA
= 25°C, f = 1.0 MHz)
Symbol
Parameter
CIN1
= OV)
Output Capacitance (VOUT = OV)
COUT
Min
Input Capacitance (VIN
NOTE:
This parameter is sampled and not 100% tested.
4-40
Max
Unit·
7
pF
7
pF
5164
D.C. AND OPERATING CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Min
Max
Units
Test Cc;mditions
lee
Operating Current
100
mA
Vee = Max, CS1 = VIL
CS2 = VIH, Outputs Open,
TeyeLE = Min
ISB
Standby Current
30
mA
Vee
CS1
7
mA
CS1 2 Vee - 0.2V,
VIN 2 Vee - 0.2Vor
VIN ~ 0.2V, Vee = Max
ISB1
=
=
Min to Max
VIH or CS2 = VIL
III
Input Load. Current
-10
10
p.A
Vee = Max
VIN = GND to Vee
ILO
Output Leakage
-10
10
p.A
CS1 = VIH, Vee = Max
VOUT =: GND to Vee
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
0.4
V
IOH
V
IOL
= -4mA
= 8 mA
DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Min
VeDR
Voltage for Data Retention
2
leCOR
Data Retention Current
teDR
Chip Deselect to
Data Retention Time
tR
Operation Recovery Time
Low
Typ
Max
Units
Test Conditions
95
500
p.A
Vee
350
750
/LA
Vee
V
0
ns
tRe
ns
= 2V
= 3V
CS1 2 Vee - 0.2V
VIN 2 Vee - 0.2V
or ~ 0.2V
Vee Data Retention Waveform
DATA RETENTION MODE
Vee
240674-3
4-41
inter
5164
A.C. TEST CONDITIONS
Input Pulse Levels ................... GND to 3.0V
Input Rise and Fall Times .........•.......... 5 ns
Timing Reference Level ..................... 1.5V
A.C. CHARACTERISTICS
(TA
=
O'Cto 70'C, Vcc
=
5V ±10%)
READ CYCLE
Symbol.
tRC
Parameter
5164-20
Min
Read Cycle Time
Max
20
5164-25
Min
Max
25
5164-30
Min
Max
30
5164-35
Min
Unit
Max
35
ns
tAA
Address Access Time
20
25
30
35
ns
tACS1
Chip Select 1
Access Time
20
25
30
35
ns
tACS2
Chip Select 2
Access Time
20
25
30
35
ns
tOE
Output Enable to
Output Valid
15
15
20
20
ns
tOH
Output Hold from
Address Change
3
3
3
3
ns
tCLZ1
Chip Select 1 to
Output in Low Z
5
5.
5
5
ns
tcLZ2
Chip Select 2 to
Output in Low Z
5
5
5
5
ns'
tcHZ1
Chip Select 1 to
Output in High Z
15
15
20
20
ns
tCHZ2
Chip Select 2 to
Output in High Z
15
15
20
20
ns
toLZ
Output Enable to
Output in Low Z
tOHZ
Output Enable to
Output in High Z
tpu
Chip Selection to
Power Up Time
tpD
Chip Deselection to
Power Down Time
0
0
0
10
10
20
0
25
ns
20'
15
0
0
0
-
0
30
ns
ns
35
ns
NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage, tcHZ(Max) is less than tcLZ(Min), both for a given device and from device to
device.
4-42
5164
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
=f
-
IRC
' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.......
~-------IM-----___1
t------IOE - - - _ _ _ 1
t - - - - IoLz(S) - - - - - I
~~...,II------
CS 2 .....
I ACS2 - - - - j - - j
1 - - - - ICLZ2(S) - - - - I
240674-4
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
240674-5
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
DATAOUT
CURRENT
--..!::==t=7.~T--~~~[:::t=l:j
ISS
---Ir----------t--~,
--------.11
ICC • - - - - - - -
- - -
IpO
240674-6
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS1 =
CS2 = VIH.
3. Address valid prior to or coincident with CS1 transition low and CS2 transition high.
4. OE = VIL
5. Transition is measured ± 500 mV from steady state.
.'!!!..
4-43
inter
5164
A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
Symbol
Parameter
5164-20
Min
Max
5164·25
Min
Max
5164-30
Min
Max
5164-35
Min
Units
Max
twc
Write Cycle Time
20
25
30
35
ns
tCW1
Chip Selection 1 to
End of Write
15
20
25
30
ns
tCW2
Chip Selection 2 to
End of Write
15
20
25
30
ns
tAW
Address Valid to
End of Write
15
20
25
30
ns
tAS
Address Set-Up Time
0
0
0
0
ns
twp
Write Pulse Width ,
15
20
25
25
ns
tWR
Write Recovery Time
0
0
0
0
ns
tow
Data Valid to
End of Write
15
15
15
15
ns
tOH
Data Hold Time
0
0
0
0
ns
tWHZ
Write Enable to
Output in High Z
0
tow
Output Active from
End of Write
0
12
0
0
4-44
15
0
0
15
0
0
15
ns
ns
inter
5164
TIMING WAVEFORM OF WRITE CYCLE NO. 1(1)
1 - - - - - - - - twc - - - - - - - 0 0 1
ADDRESS
CS 2
DATAOUT
240674-7
TIMING WAVEFORM OF WRITE CYCLE NO. 2{1,6)
1 - - - - - - - - twc
-------1
ADDRESS
CS 2
CS 1
DATAOUT
VALIDXXXXX
240674-8
NOTES:
1. WE must be high during all address transitions.
2. A write occurs during the overlap (twp) of a low CSI and a high CS2.
3. tWR1,2 is measured from the earlier of CSI or WE going high or CS2 gOing low to the end of write cycle.
4. During this period, 1/0 pins are in the output state so that the input signals must not be applied.
5. If the CS 1 low transition or CS2 high transition occurs simultaneously with the WE low transitions or after the WE tran·
sition, outputs remain in a high impedance state.
6. OE is continuously low (OE = VII).
7. DATAOUT is the same phase of write data of this write cycle, as long as address does not change.
B. If CSI is low and CS2 is high during this period, 1/0 pins are in the output state. Data input signals must not be applied.
9. Transition is measured ± 200 mV from steady state.
4-45
inter
5164
28-PIN PLASTIC DIP
1
'I
1.46 (37.08)
1.44 (36.57)
~.J::::::::::::] ~~:
o
~
1
0.330(8.26)
0.315(7.87)
SEATING PLANE
o::;:~::~~
~
,
0.062 158
0.050 1:27
l
~ 'J
'
0.1704.32
0.155 3.93
0.140 3.56
L__
II
II....
g:g~~ g:~~ ---r
0.120 3.05
t
~-T
1-
--l
0.380 9.65)
0.350 8.69
0.0140.36
0.008 0.20
I
I-
0.10~.54)
,
1------
l
r
1.300 (33.02)
TYP.
-----~
240674-9
4-46
51256
HIGH SPEED 32K x 8-BIT STATIC RAM
51256·20
Max Access Time (ns)
51256·25
51256·30
51256·35
20
25
30
35
Max. Active Current (rnA)
100
100
100
100
Max Standby Current (rnA)
30
30
30
30
Operation
• -Static
No Clock/Refresh required
Access and Cycle Times
• -Equal
Simplifies System Design
• Single + 5V Supply
2V Data Retention Option Available
• Power
Down Mode
• TTL compatible
• Common Data Input and Output
• .28·Pin 300 Mil Plastic PDIP Package.
•
The 51256 is a 32,76B-word by B-bit high speed static RAM fabricated using a CMOS silicon gate process.
Easy memory expansion is provided by an active low Chip Select (CS) and an active low Output Enable. (OE).
The power down feature contributes greatly to system reliability. The device's power consumption is reduced
when in this low power standby mode.
Pin Connections
Functional Block Diagram
+-0 vee
ROW
DECODER
+-OGND
1024x 256
Memory Array
240801-2
Pin Names
Ao-A14 ADDRESS
.............
cs"'-----.l~
~
~--------------------~~
WE ..,.--01.-_--'
240801-1
4-47
0 0- 0 7
DATAINPUT/OUTPUT
CS
CHIP SELECT
WE
WRITE ENABLE
OE
OUTPUT ENABLE
Vee
POWER
GND
GROUND
August 1990
Order Number: 240801-001
inter
51,256
Table 1. Mode Selection Truth Table
DEVICE OPERATION
The 51256 has two control inputs: Chip Select (CS)
and Write Enable (WE). WE is the data control pin to
be used to gate data at the 1/0 pins. When CS and
WE inputs are LOW, data is written into the memory
and reading is accomplished when CS and OE are
active LOW while Write Enable (WE) remains inac·
tive or HIGH.
.
STANDBY POWER
The 51256 is placed in a standby or reduced power
consumption mode by applying a high (VIH) to the
CS input. When in standby mode, the device is deselected and outputs are in a high impedance state,
independent of the WE input.
4-48
CS
WE
OE
Mode
I/O
Power
H
X
X
Standby
HighZ
Standby
L
L
X
Write
Din
Active
L
H
L
Read
Dout
Active
L
H
H
Read
HighZ
Active
intJ
51256
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
UNITS
Vin, Vout
-1.0to +7V
V
Voltage on any pin relative to Ground
Tstg
-65 to + 150
°C
Power Dissipation
Pd
1.0
W
DC Continuous Output Current
los
50
rnA
Storage Temperature (Ceramic)
NOTICE: This is a production data sheet. The specifications are subject to change without notice .
• WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to Vss, T A = O°C to 70°C)
Parameter
Symbol
Min
Typ
Max
Units
Vee
4.5
5.0
5.5
V
0
0
0
V
Vee + 0.5
V
0.8
V
Supply Voltage
. Vss
Ground
Input High Voltage
VIH
2.2
Input Low Voltage
VIL
-0.5
NOTE:
During transitions, the inputs may undershoot to - 2.0V for periods less than 20ns.
CAPACITANCE
(TA
=
25°C, f
=
1.0 MHz)
Parameter
Input Capacitance (VIN
Symbol
=
OV)
Output Capacitance (VOUT
=
OV)
Max
Units
CIN
8
pF
COUT
8
pF
NOTE:
This parameter is sampled and not 100% tested.
4-49
Min
inter
51256
D.C. AND OPERATING CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Max
Units
Test Conditions
Operating Current
lee
100
mA
Vee = Max., CS s VIL
outputs open, Tcycle = Min.
Standby Power
ISB
30
mA
Vee
ISB1
7
mA
CS:<: Vee-0.2V,
VIN:<: Vee-0.2V or
VIN s 0.2V, Vee = Max
Parameter.
Symbol
Supply Current
Min
=
Max, CS :<: VIH
Input Load Current
III
-10
10
p.A
Vee = Max
OV s VIN s Vee
Output Leakage
ILO
-10
10
p.A
CS = VIH, Vee = Max
OV s VOUT s Vee
Output High Voltage
VOH
2.4
Output Low Voltage
VOL
0.4
V
IOH
V
IOL
= -4.0mA
= 8.0mA
DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VeDA
Voltage for Data Retention
leeDA
Data Retention Current
teDA
Chip Deselect to Data
Retention Time
tA
Operation Recovery Time
Test Conditions
Min
Typ
Max
2
V
95
CS :<: (Vee - 0.2 V)
VIN :<: (Vee - 0.2 V)·
or s 0.2V (Vee = 2V)
50
0
tAe
p.A
ns
ns
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
vcc
240801-3
4-50
Units
inter
51256
A.C. TEST QUESTIONS
Input Pulse Levels ................... GND to 3.0V
Input Rise and Fall Times .................... 5 ns
Timing Reference Level ..................... 1.5V
A.C. CHARACTERISTICS
(TA = 0° to 70°C, VCC = 5V ± 10%)
READ CYCLE
Symbol
Parameter
51256-25
51256-30
51256-35
51256-45
Min
Min
Min
Min
Max
Max
Max
Units
Max
tRC
Read Cycle Time
tAA
Address Access Time
25
30
35
tACS
Chip Select Access Time
25
30
35
45
ns
tOE
Output Enable to Output Valid
15
20
20
20
ns
tOH
Output Hold from Address Change
5
5
5
5
ns
tClZ
Chip Select to Output in Low Z
5
5
5
5
ns
tCHZ
Chip Deselect to Output in High Z
tOll
Output Enable to Output in Low Z
0
tpu
Chip Selection to Power Up Time
0
tpD
Chip Deselection to Power Down Time
25
30
35
20
15
0
20
ns
ns
0
35
ns
ns
0
0
30
ns
45
20
0
0
25
45
45
ns
NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage, teHZ (Max) is less than telZ (Min), both for a given device and from device to
device.
4-51
inter
51256
-------=i tAA
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
~
--------1
tRC
_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~------
------.!.'
DE
---+----
DATAOUT
240801-4
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
-=Jk
~
- ~I +-I+-.:===-tOH -tAA-bk
~
~-tOH-l---
DATAOUT
240801-5
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
DATAOUT
240801-6
NOTES:
1. WE is High for Read Cycle.
2. Device is continuously selected. CS = Vlk
3. Address valid prior to or coincident with CS transition low.
4.
OE
= VIL
.
5. Transition is measured ± 200 mV from steady state with 5 pF load (including scope and jig). '
4-52
inter
51256
A.C. CHARACTERISTICS
(Continued)
WRITE CYCLE
Symbol
Parameter
51256·25
Min
Max
51256-30
Min
Max
51256-35
Min
Max
51256-45
Min
Units
Max
twe
Write Cycle Time
25
30
35
45
ns
tew
Chip Select To End of Write
20
25
30
40
ns
tAW
Address Valid to End of Write
20
25
30
40
ns
tAS
Address Set-up Time
0
0
0
0
ns
twp
Write Pulse Width
20
25
25
30
ns
tWR
Write Recovery Time
0
0
0
0
ns
tow
Data Valid to End of Write
15
15
15
20
ns
tOH
Data Hold Time
0
0
0
0
ns
tWHZ
Write Enable to Output in High Z
0
tow
Output Active from End of Write
5
15
0
5
4-53
15
0
5
15
0
5
20
ns
ns
inter
51256
TIMING WAVEFORM OF WRITE CYCLE NO.1,
(WE CONTROLLED TIMING)(1, 2, 3, 5, 7)
twc
ADDRESS
:)K:
X
~ t cHZ(6)
----
tAW
~
I\..
I--
~~
t wp (7)
tAS
.."
DATAOUT
(4)
-
tWR
~V'
'_tWHZ(6)~
"
_tOW-i
/I
_tow _
~
_.
~
tOH _
....
"'
"
/
240801-7
TIMING WAVEFORM OF WRITE CYCLE NO.2,
(WE CONTROLLED TIMING)(1, 2, 3, 5)
twc
ADDRESS
~(
)(
tAW
_
t AS
}
~,
t cW(7)
tWR
I-- tow _
/
"
_
l-
tOH _
"'
/
240801-8
NOTES:
1. WE must be high during all address transitions.
2. A write occurs during the overlap (~or twe). of a low CS and low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in the high impedance state.
6. Transition is measured ± 200 mV from steady state with a 5 pF load (including scope and 'jig).
7. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of twp or:..fuyz + tow) to allow the
I/O drivers to ,turn off and data to be placed on the bus for the required tow. If OE is high during a WE controlled write cycle,
this requirement does not apply and the write pulse can be as short as the specified twP.
4-54
inter
51256
PACKAGE DIMENSIONS
I
2lI-I'In Plastic Dip
•
1.46 (37.08)
I
1.47 (36.57)
L-
.
SEATING PLANE
y--- l:rO=TI:;:nTrr;::;:~:;:;:;::;:;:::;::::J
"0.~17~0~~
0'135(3'43)~~-t----L-
0.155 (3.94)
,.~ (..,.,:JIl J l
0.050 (1.27)
II
-II- 0.021
(0.53
0.018 (0.41
~~;"
I
1
0.325 (8.26)
0.31.~~:.87)
r-
R. ,. ",.",
~
0.008 (0.20)
0.380 9.65)
0.350 8.69
I
r-
0~gO(2.54)
1.300J~3.02) _ _ _ _ _-1
All dimensions In Inches (millimeters)
Uax.
Min.
240801-9
4-55
51258
HIGH SPEED 64k x 4-BIT STATIC RAM
51258-20
Max Access Time (ns)
Max Active Current(mA)
Max Standby Current (rnA)
•
•
•
51258-25
51258-35
20
25
30
35
100
100
100
100
30
30
30
30
•
•
•
•
•
Static Operation
- No Clock/Refresh required
Equal Access and Cycle Times
- Simplifies System Design
+ 5V Supply
Single
51258-30
2V Data Retention Option Available
Power Down Mode
TTL compatible
Common Data Input and Output
24-Pin 300 Mil Plastic PDIP Package
The 51258 is a 65,536-word by 4 bit high speed static RAM fabricated using a CMOS silicon gate process:
Easy memory expansion is provided by an active low Chip Select (CS).
The power down feature contributes greatly to system reliability.
when in this low power standby mode.
Th~
device's power consumption is reduced
Pin Configuration
DIP/SOle
Functional Block Diagram
AODRESSES {
262.144-BIT
Ao
MEMORY ARRAY
A,s----I
1/0,--......-1
240802-1
Top View
Pin Names
Ao-A15
Addresses
1/01-1/04
Data Input/Output
CS
Chip Select
WE
Write Enable
GND
Ground
Vee
Power
240802-2
4-56
August 1990
Order Number: 240802-001
inter
51258
Table 1. Mode Selection Truth Table
DEVICE OPERATION
The 51258 has two control inputs: Chip Select (CS)
and Write Enable (WE). WE is the data control pin to
be used to gate data at the 1/0 pins. When CS and
WE inputs are LOW, data is written into the memory
and reading is accomplished when CS goes active
LOW while Write Enable (WE) remains inactive or
HIGH.
Mode
1/0
X
Standby
HighZ
Standby
L
Write
Din
Active
H
Read
Dout
Active
CS
WE
H
L
L
Power
STANDBY POWER
The 51258 is placed in a standby or reduced power
consumption mode by applying a high (VIH) to the
CS input. When in standby mode, the device is deselected and outputs are in a high impedance state,
independent of the WE input.
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Value
Units
-1.0to +7V
V
Tstg
Storage Temperature -65 to +150
(Ceramic)
°C
Pd
Power Dissipation
1.0
W
los
D.C. Continuous
Output Current
50
rnA
Yin, Vout Voltage on any pin
relative to Ground
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
= O°C to 70°C)
(Voltage referenced to Vss, T a
Parameter
Min
Typ
Max
Units
Vee
Supply Voltage
4.5
5.0
5.5
V
Vss
Ground
0
0
0
V
VIH
Input High Voltage
2.2
-
Vee+ 0.5V
V
VIL
Input Low Voltage
-0.5
-
0.8
V
Symbol
NOTE:
During transitions, the inputs may undershoot to - 2.0V for periods less than 20 ns.
4-57
inter
51258
CAPACITANCE
(TA
=
25°C, f
Symbol
=
1.0 MHz)
Parameter
Min
=
CIN
Input Capacitance (VIN
GOUT
Output Capacitance (VOUT
OV)
=
OV)
Max
Units
-
8pF
-
8pF
NOTE:
This parameter is sampled and not 100% tested.
D.C. AND OPERATING CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Symbol
Parameter
Min
Max
Units
Test Conditions
-
100
mA
Vee = Max., CS s VIL
Outputs Open, T Cycle = min.
Standby Power
-
30
mA
Vee
ISB1
Supply Current
-
7
mA
CS ~ Vee-0.2V,
VIN ~ Vee-0.2V or
VIN s 0.2V, Vcc=Max
III
Input Load Current
-10
10
/LA
Vee = Max
OV s VIN s Vee
ILO
Output Leakage
-10
10
/LA
CS = VIH, Vee = Max
OV s VOUT s Vcc
VOH
Output High Voltage
2.4
-
V
IOH = -4.0mA
VOL
Output Low Voltage
-
0.4
V
IOL = 8.0mA
Icc
Operating Current
ISB
4-58
= Max, CS
~ VIH
51258
DATA RETENTION ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VCDR
Voltage for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to
Data Retention Time
tR
Operation Recovery Time
Test Conditions
Min
CS ~ (VCC - 0.2 V)
VIN ~ (VCC - 0.2 V)
or ~ 0.2V
(VCC = 2V)
-
Typ
Max
-
V
95
500
}J-A
-
ns
2
0
Units
tRC
ns
LOW Vee DATA RETENTION WAVEFORM
DATA RETENTION MODE
240802-3
A.C. TEST QUESTIONS
Input Pulse Levels ....••............. GND to 3.0V
Input Rise and Fall Times .••......•.......... 5 ns
Timing Reference Level ..................... 1.5V
A.C. CHARACTERISTICS (TA = 0°0 to 70 0C. Vcc
0
=
5V ± 10%)
READ CYCLE
Symbol
Parameter
tRC
Read Cycle Time
tAA
Address Access Time
51258-20
51258-25
Min
Min
Max
25
20
20
tACS
Chip Select Access Time
tOH
Output Hold from Address Change
3
tCLZ
Chip Select to Output in Low Z
5
tCHZ
Chip Deselect to Output in High Z
tpu
Chip Selection to Power Up Time
tpD
Chip Deselection to Power Down Time
Max
30
5
0
0
25
ns
35
ns
ns
5
20
15
ns
35
5
5
5
ns
20
ns
ns
0
30
Units
Max
35
30
25
15
Max
30
5
20
51258-35
Min
25
20
0
51258-30
Min
35
ns
NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage. tCHZ (Max) is less than tClZ (Min). both for a given device and from device to
device.
4-59
intJ
51258
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
""'"
~j.
_____ lu
t~
1 + - - - - - tACS
t CLZ (4)
----%.-1•~t-OH------
---,-,
--+-----+/
DATAOUT
240802-4
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2)
-=Jk
-.
~:=t
'"
-fl
===-tOH _tAA
~
~-tOH-l---
DATAOUT
240802-5
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3)
DATAOUT
240802-6
NOTES:
1. WE is high for read cycle.
2. Device is continuously selected, CS = VIL.
3. Address valid prior to or coincident with CS transition low.
4. Transition is measured ± 200 mV from steady state with 5 pF load (including scope and jig).
4-60
inter
51258
A.C. CHARACTERISTICS (Continued)
WRITE CYCLE
Symbol
51258-20
Parameter
Min
51258-30
51258·25
Max
Min
Max
Min
51258-35
Max
Min
Units
Max
twc
Write Cycle Time
20
25
30
35
ns
lew
Chip Select to
End of Write
15
20
25
25
ns
tAW
Address Valid to
End of Write
15
20
25
25
ns
tAS
Address Set-up Time
a
a
a
a
ns
twp
Write Pulse Width
15
20
25
25
ns
tWR
Write Recovery Time
a
a
a
a
ns
tDW
Data Valid to
End of Write
10
12
15
15
ns
a
a
tDH
Data Hold Time
tWHZ
Write Enable to
Output in High Z
tow
Output Active from
End of Write
a
a
15
5
a
a
15
15
5
5
a
a
ns
15
ns
5
ns
TIMING WAVEFORM OF WRITE CYCLE NO.1
(WE CONTROLLED TIMING)(1, 2, 3, 6)
twc
ADDRESS
~'"
)K:
tAW
)1'
OATA OUT
DATAIN
,
"
tWR
........:;.;.:.
twp
- - tAS
~,
''"
__ tWHZ(6)~
(4)
"
-
'I
tow
----i,
I'
(4)
------------ICR"""------9. ----tow
-00
__ tOH
240802-7
4-61
51258
TIMING WAVEFORM OF WRITE CYCLE NO.2,
(CS CONTROLLED TIMING)(1, 2, 3, 5)
twc
ADDRESS
:)V'
V'
tAW
_tAS
)
tWR
--::.::....
tcw
~
tDW _
DATAIN
_
tDH
----------.....(~----- ~lI-----...
240802-8
NOTES:
1. WE or CS must be high during all address transitions.
2. A write occurs during the overlap (ICW or twP) of a low CS and low WE.
3. twR is measured from the earlier of CS or WE going high to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CS low transition occurs simultaneously with or after the WE low transition, the outputs remain in the high impedance state.
6. Transition is measured ± 200 mV from steady state with 5 pF load (including scope 'and jig).
PACKAGE DIMENSIONS
1.250 (51.75)
1.230 (31.24)
1
.
'I
[~~~~~~~~~~]~~:
~J
"._=;
0.145(3.68)
0.135 (3.43)
~
r-0.062 (1.57)
0.050 (1.27)
~ ~
L
I
Jl
/
~
0.170(4.32)
0.155 (3.94)
0.140 (3.56)
0.1202.05)
~~
0.021 (0.53)
0.018 (0.41)
-r
j
f
1
0.325 (8.26)
0.310 (7.87)
Ir-
IIS\--\-I .... ,...,
0.008 (0.20)
...,
0.380 (9.65)
0.330 (8.38)
r-
0.100 (2.54)
TYP
1.100 (27.94) - - - - + (
TYP
All dimension. In Inche. (millimeters)
~~~.
240802-9
24-Pln Plastic Dip
4-62
RR-63
RELIABILITY
REPORT
August 1989
. Static RAM
Reliability Report
MADHU NIMGAONKAR
COMPONENTS CONTRACTING DIVISION
QUALITY AND RELIABILITY. ENGINEERING
Order Number: 240544-001
4-63
SRAM RELIABILITY DATA
SUMMARY
CONTENTS
PAGE
1.0 INTRODUCTION ...... : ............. 4-65
2.0 RELIABILITY TESTS ............... 4-65
High Temperature Burn-In ............... 4-65
High Temperature Dynamic Lifetest ...... 4-65
High Voltage (7V) Dynamic Lifetest ...... 4-65
High Temperature Reverse Bias Test .... 4-65
Low Temperature Lifetest ............... 4-65
High Temperature Storage Test ......... 4-66
Temperature Cycle Test ................. 4-66
3.0 RELIABILITY DATA SUMMARy .... 4-66
51C68 .................................. 4-66
51C98 .................................. 4-67
APPENDIX A ........................... 4-71
Common MOS Failure Mechanisms ...... 4-71
Oxide Defects ............................ 4-71
Silicon Defects .......................... 4-71
Contamination .......................... 4-71
Metallization Defects .................... 4-71
4-64
intJ
RR-63
1.0 INTRODUCTION
This report summarizes the ~eliability predictions of the
MOS memory components and the methodology used
in making the predictions. The methodology adopted
by Intel is among the most conservative in the electronics industry. The reader should be aware of the different methodologies used by various manufacturers in
making the reliability predictions and the profound effect a more liberal approach has on the failure rate reported.
'I
107
I
II
j
106
::..1
J/~7
<:>
VI
'"0
:>
105
.:
::t:
I
..,
:>
'"
2.0 RELIABILITY TESTS
...I
I I
104
~
High Temperature Burn-In
..,e
This test is used to establish infant mortality failure
rates. Intel defines infant mortality as the early life failures observed after a 48 hour 125°C dynamic burn-in.
In order to eliminate infant mortality fallout in determining long term failure rates, all devices used for lifetesting are subjected to standard Intel production
screens plus a 48 burn-in.
;::
:::E
)~
JII
103
o·
7
102
JII
/
~~
o~
~~Z
/ 1/ ./
10~
7
5
3
High Temperature Dynamic Lifetest
V ~ '/ V1/ /./.
If) V
250200175150125100 75 50 25
This test is performed to accelerate failure mechanisms
that are thermally activated through the application of
extreme temperatures (125°C) and the use of biased operating conditions (5.5V). The translation from 125°C
to 55°C is done by applying time acceleration factors
based on the thermal activation energy assignments.
TEMPERATURE (Oc)
240544-1
Figure 1. Arrhenius Plot
High Voltage (7V) Dynamic Lifetest
Failure rate calculations are given for each relevant activation energy. These are made using the appropriate
activation energy and the Arrhenius Plot as shown in
Figure 1. The total equivalent device hours at a given
temperature can be determined. The failure rate is then
calculated by dividing the number of failures by the
equivalent device hours and is expressed as a %/1000
hours. The failure rate is adjusted by a factor related to
the number of device hours using a chi-square distribution to arrive at a confidence level associated failure
.rate. A conservative estimate of the failure rate is obtained by including zero failures at 0.3 eV, 0.5 eVand
1.0 eV. In cases where the mechanism of the catastrophic failures cannot be determined, 0.3 eV activation energy is assumed.
This test is used to detect failure mechanisms which are
accelerated by high voltage as well as high temperature.
It is especially effective in accelerating oxide and leakage related failures. The total acceleration factor includes the time acceleration factors based on the assigned activation energies and voltage acceleration factor (7V to 5.5V).
High Temperature Reverse Bias Test
This test is used to detect failure mechanisms which are
accelerated by high temperature (1500C). This test is
effective in accelerating leakage related failures and
drifts in device parameters due to process instability.
When reviewing failure rate projections from ditTe~ent
sources, it is important to understand the assumptions
being made. Small changes in details can dramatically
alter an estimated failure rate.
Low Temperature Lifetest
This test is performed at maximum operating frequency
to detect the effects of electron injection into the gate
oxide. The conditions for electron injection occur during transitions when the transistors are in saturation.
4-65
inter
RR-63
High Temperature Storage Test
Temperature Cycle Test
High temperature storage (bake) is a test in which devices are subjected to elevated temperatures (1SO"C for
plastic packages and 2SO"C for hermetic packages) with
no applied bias. This test is used to detect mechanical
reliability problems (e.g., bond integrity) and process
instability.
This test consists of cycling the temperature of a chamber housing device from -6S'C to + 1SO"C with no
applied bias. Temperature cycling (1000 cycles) is used
to detect mechanical reliability problems and microcracks.
,3.0 RELIABIL{TY DATA SUMMARY
51C68
Number of bits: 16,384
Organization:
4K x 4
Process: CHMOS III
Package: 20-Pin
Table 1. Failure Rate Predictions
Actual
Device Hours
12S'C
+ 06,
+ O~
3.B5E + 06
Ea
(eV)
Equivalent Hours
#
Fall
SS'C
3.B5E
0.3
2.00E
3.B5E
0.5
6.01E
1.0
9.40E
70'C
+ 07
+ 07
+ OB
+ 07
+ 07
2.42E + OB
SS'C
70"C
1.33E
1
0.0101
0.0152
3.05E
0
0.0015
0.0032
0
0.0001
0.0002
0.0117
117
0.01B6
186
Combined Failure Rate: .
FITs:
NOTE:
FIT = Failures in Time. 1 FIT = 1 failure per 10E
Fall Rate %/1K Hours
(60% UCL)
+ 09 device hours.
Table 2. Reliability Summary
Month
12S'C DynamiC Llfetest
Package
48 Hrs
168 Hrs
500 Hrs
1KHrs
2KHrs
1/B6 •
Cerdip
1/1061
0/1034
0/600
0/600
-
3/B6 •
3/B6 ••
Plastic
0/1536
0/1531
0/579
0/579
1/579
Plastic
0/150
0/150
0/150
0/150
0/150
5/B6
Cerdip
0/1000
0/1000
0/150
0/150
-
6/B6
Cerdip
0/B79
0/B6B
0/150
0/150
9/B6
Cerdip
1/1125
0/1123
0/150
0/150
-
5/87
Cerdip
01743
01743
0/150
0/150
-
7IB7
Cerdip
0/1000
0/1000
0/150
0/150
7/B7
Cerdip
01769
01769
0/200
0/200
7IB7
Cerdip
2/675
0/673
0/200
0/200
-
4/B93B
(A)
0/8891
0/2479
0/2464
1/729
(8)
(C)
(0)
(E)
Total
NOTE:
°Qual Data
o07V Qual Data
4-66
RR·63
Table 3. Package Thermal Characteristics
Package
Type
Junction Temp.
@55·C Ambient
Junction Temp.
@70·C Ambient
Junction Temp.
@125·CAmbient
Cerdip
78
93
148
Plastic
91
106
161
Table 4. Failure Analysis Summary
Time Frame
Group
# Fail
Description
Ea(eV)
1/86
A
1
ISB Failure, Hot Spot on Cont.
Gate Edge of Y4 Driver
0.3
9/86
A
1
Defect Not Found
0.3
7/87
A
1
1
Contamination
Assembly Defect at Wire Heel
1.0
0.5
3/86
E
1
Single Bit Defect Not Found
0.3
51C98
Number of bits: 65,536
Organization:
16K x 4
Process: CHMOS IV
Package: 22-Pin
Table
Year
i
High Temperature Llfetest Data
125·C (5.5V) DynamiC Llfetest
Lot #
48Hrs
168 Hrs
500Hrs
1KHrs
2KHrs
04/88
27-921
3/1043
0/1040
0/890
0/890
0/890
04/88
22-957
0/488
1/488
1/337
0/336
2/335
Q4/88
24-985
41759
11755
0/604
1/604
0/603
04/88
26-903
21708
1/556
0/755
11755
04/88
26-910
1/999
01706
0/997
1/847
0/845
0/845
01/89
40-980
0/536
0/536
0/536
Oi536
-
01/89
42-988
Total
1/580
1/579
0/578
0/578
-
11/5113
315101
3/4348
1/4344
3/3228
(A)
(B)
(C)
(0)
(E)
4-67
RR-63
, Table 2, Failure Analysis Summary
Group
# Fail
Description
Ea(eV.)
A
11
1 Ea Lost during Failure Analysis
2 Ea A 1/Ti Particle in via Seam
2 Ea BPSG Crystals
1 Ea Passivation Damage
2 Ea Single Bit
1 Ea Bond Pad Corrosion
1 Ea Column Fail (M2 Particle)
1 Ea Column Fail (M1 Particle)
0.3
0.3
0.5
0.5
1.0
0.3
0.3
B
3
C
3
-
1 Ea Single Bit (Poly Extra)
1 Ea EOS (Electrical Overstress)
1 Ea Open (Lifted Bond)
0.3
2 Ea Single Bit
1 Ea Open (Lifted Bond)
0.3
1.0
1.0
D
1
1 Ea Single Bit
0.3
E
3
1 Ea Passivation Damage
1 Ea Leakage
1 Ea Metal 2 Input Open
0.5
0.3
0.5
Table 3. High Voltage Lifetest Data
Year
Lot #
04/88
27-921
04/88
04/88
High Voltage (7V) Dynamic Llfetest
48 Hrs
168 Hrs
500 Hrs
1KHrs
2KHrs
1/597
2/596
1/593
0/592
22-957
2/599
'0/200
01200
0/200
3/200
0/197
24-985
0/379
0/379
0/379
1/379
0/378
04/88
26-903
2/354,
1/350
2/348
0/346
0/346
04/88
26-910
3/513
1/509
0/508
0/508
1/508
-
01/89
40-980
1/268
0/267
0/267
0/267
01/89
42-988
0/291
1/291
0/290
0/290
8/2604
4/2593
4/2588
5/25~3
1/2021
(.1\)
(B)
(C)
(D)
(E)
Total
4-68
intJ
RR-63
Table 4. Failure Analysis Summary
Ea (eV)
Group
# Fail
A
B
1 Ea for Abnormal Contact
2 Ea A 1/Ti in via Seam
3 Ea BPSG Crystals
1 Ea BPSG Crystal
1 Ea Column Fail (M2 Particle)
0.5
0.3
0.3
0.3
0.3
B
4
1 Ea Bond Pad Corrosion
1 Ea ISB Leakage (Corrosion)
1 Ea BPSG Crystal
1 Ea Single Bit
0.5
0.5
0.3
0.3
C
4
2 Ea BPSG Crystals
1 Ea Column (Passivation Damage)
1 Ea Column Fail
0.3
0.5
0.3
D
5
4 Ea Lifted Bond
1 Ea Passivation Damage
1.0
0.5
E
1
1 Ea Metal 2 Input Open
0.5
Description
Table 5. Failure Rate Predictions
5.5V
7.0V
..
Totals
( )
125°C Actual
Device Hours
Ea
(eV)
Equivalent Hours
at 55°C
7,4BE
+ 06
+ 06
7,4BE + 06
4,46E + 06
4,46E + 06
4.46E + 06
11.9E + 06
11.9E + 06
11.9E + 06
0.3
7,4BE
0.5
+ 07
+ 07
26.9E + OB
11.BE + 07
B,47E + 07
16.1E + OB
16.2E + 07
22.7E + 07
43.0E + OB
1.0
0.3
0.5
1.0
0.3
0.5
1.0
Fail
FIT Rate
(60% UCL)
4,41E
5
0.0142
14.2E
2
0.0022
#
2
0.0001
5
0.0053
5
0.0074
4
0.0003
10
0.0071
7
0.0037
6
0.0002
Total
FIT
Rate
165
130
110
'48 Hour faIlures at 12S'C are not Included In long term failure rate calculatIons.
"S.SV and 7V bum-inllifetest equivalent hours have been combined.
Temp. with Tja
T(55)
= 33BK
= 40BK
T (125)
BIIELT
Accel.
Factors:
0.3eV
0.5eV
1.0 eV
K = B.62E -05 eV/K
Voltage Accel. Factor: 4,4B
NOTE:
FIT = Failures in Time. 1 FIT = 1 Failure per 10E
+
09 device hours.
4-69
Thermal Accel.
Factors
55°C
5.90
19.0
360
RR-63
Table 6. Infant Mentality Evaluation Results
High Temperature (7V) Burn-In
Year
Lot #
6Hrs
1~
Hrs
24Hrs
48Hrs
168 Hrs
01/89
42-995
0/672
0/672
0/672
1/672
0/671
01/89
44-997
0/688
0/688
0/688
0/688
0/688
01/89
45-900
1/655
0/654
0/654
0/654
0/654
01/89
48-909
0/614
0/614
0/614
0/614
0/614
1/2629
0/2628
0/2628
0/2627
0/2627
Total
(8)
(A)
Failure Analysis
A) 1 Ea Func. fail (Metal 1 particle)
B) 1 Ea Invalid Failure (Cracked Package)
Table 7. Additional Qual!flcation Tests
Year
Low Temp (-10·C)
Llfetest (2K Hrs)
1500CHTRB
1K Hrs.
Temp Cycle
1KCycies
1600C
1000 Hrs. Bake
1988/89
0/120
5/240
0/250
1/~00
(A)
Failure Analysis
A) 1 Ea Passivation damage
1 Ea Func. fail @ < 2.6V
1 Ea Open (Lifted Bond)
1 Ea Qlown V88 Pin
1 Ea Healed
B) 1 Ea Open (Lifted Bond)
4-70
(8)
RR-63
APPENDIX A
COMMON MOS FAILURE MECHANISMS
Oxide Defects
Contamination
Oxide defects can cause dielectric breakdown in MOS
structures resulting in an electrical short. Oxide dielectric breakdown is dependent on time, ambient temperature and operating voltage. Oxide defects could be
induced by excessively thin oxide, polarization and contamination. The thermal activation energy for oxide defects is determined to be 0.3 eV.
MOS circuits can fail due to threshold voltage (Vt)
shifts when subjected to mobile ionic contamination.
This ionic contamination reaches critical circuits
through passivation defects subsequent to wafer processing. Sodium is the most common species of ionic
contamination. The activation energy of ionic contamination is 1.0 eV.
Silicon Defects
Metallization Defects
Silicon defects are inherent in the unprocessed silicon
wafers and may also be generated by stresses on the
lattice during MOS processing. These silicon defects enhance parasitic leakage when they become active by
"gettering" contaminants. The activation energy for silicon defects is determined to be 0.5 eV.
Metallization defects (defects relating to metal conductor paths on the semiconductor die) can occur due to
metal contamination, excess current density (electromigration) in the conductors, microcracks caused by
sharp oxide steps and overalloying due to migration of
metal through the semiconductor's contact. The activation energy is 0.5 eV.
4-71
EPROMs
(Erasable Programmable
Read Only Memories)
5
2716
16K (2K x 8) UV ERASABLE PROM
•
•
Access Time
• -Fast2716-1:
350 ns Max
•
•
- 2716-2: 390 ns Max
-2716: 450 ns Max
Single + 5V Power Supply
Low Power Dissipation
- Active Power: 525 mW Max
-Standby Power: 132 mW Max
•
•
Pin Compatible to Intel "Universal Site"
EPROMs
Simple Programming Requirements
- Single Location Programming
- Programs with One 50 ms Pulse
Inputs and Outputs TTL Compatible
During Read and Program
Completely Static
The Intel 2716 is a 16,384-bit ultraviolet erasable and electrically programmable read-only memory (EPROM).
The 2716 operates from a single 5-volt power supply, has a static standby mode, and features fast singleaddress programming. It makes designing with EPROMs fast, easy and economical.
The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with highperformance + 5V microprocessors such as Intel's 8085 and 8086. Selected 2716-5s and 2716-6s are also
available for slower speed applications. The 2716 also has a static standby mode which reduces power
consumption without increasing' access time. The maximum active power dissipation is 525 mW while the
maximum standby power dissipation is only 132 mW, a 75% savings.
The 2716 uses a simple and fast method for programming-a single TTL-level pulse. There is no need for high
voltage pulsing because all programming controls are handled by TTL signals. Programming of any location at
any time-either individually, sequentially or at random is possible with the 2716's single-address programming. Total programming time for all 16,384 bits is only 100 seconds.
DATA OUTPUTS
0 0 -0 7
OE
cr--,~
AD
- A 10
ADDRESS
INPUTS
1
'PinNames
__~__~~
OE
Addresses
Chip Enable
Output Enable
00-0 7
Outputs
Ao-Al0
CE
Y GATING
16,.384 - BIT
CELL MATRIX
210310-1
Figure 1. Block Diagram
5-1
September 1989
Order Number: 210310-003
intJ
2716
2716
~---\.J---~
2764A
27512 27256 27128A 27C64 2732A
27C512 27C256 27C128 87C64
Vpp
Vpp
Vpp
AIS
A12
A12
A12
A12
A7
A7
A7
A7
A7
As
As
As
As
As
As
As
A5
A5
A5
A4
A4
A4
~
~
A3
A3
Aa
A3
Aa
A2
A2
A2
A2
A2
Al
Al
Al
Al
Al
Ao
Ao
AO
AO
AO
00
00
00
00
00
01
01
01
01
01
02
02
02
02
02
GND GND GND GND GND
o
2764A
2732A 27C64 27128A 27256 27512
87C64 27C128 27C256 27C512
0
•
•
Vee
Vee
Vee
PGM PGM
Vee
A14
A13
As
Ag
A11
OE
Al0
CE
07
Os
Os
04
03
A14
A13
As
Ag
A11
OEIVPF
Al0
N.C. .A13
As
As
As
Ag
Ag
Ag
A11
A11
A11
OElVpp OE
OE
AlO
Al0
Al0
CE
CE AlE/CE
CE
07
07
07
Os
06
06
Os
05
Os
04
04
04
03
03
.03
Vee
CE
07
Os
Os
04
03
NOTE:
Intel "Universal Site" compatible EPROM configurations are shown in the blocks adjacent to the 2716 pins.
Figure 2. Cerdip Pin Configuration
EXTENDED TEMPERATURE
(EXPRESS) EPROMs
EXPRESS EPROM PRODUCT FAMILY
The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM, allowing
the choice of appropriate memory size to match system applications. EXPRESS EPROM products are
available with 168 ± 8 hour, 125°C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROM operating temperature range is O°C to 70°C. Extended operating temperature range (- 40°C to + 85°C) EXPRESS products are available.' Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AOL. This may allow the user to
reduce or eliminate incoming inspection testing.
PRODUCT DEFINITONS
Type Operating Temperature Burn-In 125°C (hr)
168 ±8
O°Cto +io°c
0
. -40°C to + 85°C
I
44
EXPRESS OPTIONS
2716 Versions
Packaging Options
Speed Versions
Cerdip
, -1
0
8m
5-2
0,1
inter
2716
a) the lowest possible memory power dissipation,
and
b) complete assurance that output bus contention
will not occur.
DEVICE OPERATION
The six modes of operation of the 2716 are listed in
Table 1. It should be noted that inputs for all modes
are TIL levels. The power supplies required are a
+ 5V Vcc and a Vpp. The Vpp power supply must be
at 25V during the three programming modes, and
must be at 5V in the other three modes.
To use these two control lines most efficiently, CE
(pin 18) should be decoded and used as the primary
device selecting function, while OE (pin 20) should
be made a common connection to all devices in the
array and connected to the READ line from the system control bus. This assures that all deselected
memory devices are in their low-power standby
modes and that the output pins are active only when
data is desired from a particular memory device.
Read Mode
The 2716 has two control functions, both of which
must be logically satisfied in order to obtain data at
the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable (OE) is the output control and should be used
to gate data from the output pins, independent of
device selection. Assuming that addresses are stable, address access time (tACe) is equal to the delay
from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that
CE has been low and addresses have been stable
for at least tACC-tOE.
Programming
Initially, and after each erasure, all bits of the 2716
are in the "1" state. Data is introduced by selectively
programming "O's" into the desired bit locations. Although only "O's" will be programmed, both "1 's"
and "O's" can be presented in the data word. The
only way to change a "0" to a "1" is by ultraviolet
light erasure.
Standby Mode
The 2716 is in the programming mode when the Vpp
power supply is at 25V and OE is at VIH. The data to
be programmed is applied 8 bits in parallel to the
data output pins. The levels required for the address
and data inputs are TIL.
The 2716 has a standby mode which reduces the
maximum active power dissipation by 75%, from
525 mW to 132 mW. The 2716 is placed in the
standby mode by applying a TIL-high signal to the
CE input. When in standby mode, the outputs are in
a high impedance state, independent of the OE in.
p~
Output OR-Tieing
Because 2716s are usually used in larger memory
arrays, Intel has provided a 2-line control function
that accommodates this use of multiple memory
connections. The two-line control function allows
for:
When the address and data are stable, a 50 ms,
active-high, TIL program pulse is applied to the CE
input. A pulse must be applied at each address location to be programmed. You can program any location at any time-either individually, sequentially, or
at random. The program pulse has a maximum width
of 55 ms. The 2716 must not be programmed with a
DC signal applied to the CE input.
Table 1 Mode Selection
Pins
Mode
CE
(18)
OE
(20)
Vpp
(21)
Vcc
(24)
Outputs
(9-11,13-17)
Read
VIL
VIL
+5
+5
DOUT
Output Disable
VIL
VIH
+5
+5
HighZ
Standby
VIH
X
+5
+5
HighZ
Program
Pulsed VIL to VIH
VIH
+25
+5
DIN
Verify
VIL
VIL
+25
+5
DOUT
Program Inhibit
VIL
VIH
+25
+5
HighZ
NOTE:
1. X can be VIL or VIH.
5-3
inter
2716
ABSOLUTE MAXIMUM RATINGS'"
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
+ 80·C
+ 125·C
Temperature Under, Bias ....•...• -1 O·C to
Storage Temperat!Jre ..•.•.•... - 65·C to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
All Input or Output Voltages with
Respect to Ground •...•.•.•..... + 6V to - 0.3V
Vpp Supply Volume with Respect
to Ground During Program ..... + 26.5V to - 0,3V
D.C. AND A.C. OPERATING CONDITIONS DURING READ
2716
2716-1
2716-2
Temperature Range
0·C-70·C
0·C-70·C
0·C-70·C
Vee Power Supply(1, 2)
5V ±5%
5V ±5%
5V ±5%
Vee
Vee
Vee
Vpp Power Supply(2)
READ OPERATION
D.C. CHARACTERISTICS
Symbol
Limits
Parameter
Units
Typ(3)
Min
Test Conditions
Max
III
Input Load Current
10
IJ-A
VIN
=
= 5.25V
= 5.25V
CE = VIH, OE =
OE = CE = VIL
ILO
Output Leakage Current
10
IJ-A
VOUT
IpP1(2)
Vpp Current
5
rnA
Vpp
lee1(2)
Vee Current (Standby)
10
25
rnA
ICC2(2)
Vee Current (Active)
57
100
rnA
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Vcc
+1
0.45
2.4
\
5.25V
VIL
V
V
IOL
V
IOH
= 2.1 rnA
= - 4OO IJ-A
A.C. CHARACTERISTICS
Limits (ns)
Symbol
Parameter
2716
Min
Max
2716-1
Min
Max
2716-2
Min
Max
tACC
Address to Output Delay
450
350
390'
teE
CE to Output Delay
450
350
390
toE(4)
Output Enable to Output Delay
tOF(4,6)
CE or OE High to OutP!Jt Float
0
toH
Output Hold from Addres!?es, CE
or OE Whichever Occurred First
0
120
100
0
5-4
120
120
0
100
0
0
Test
Conditionst
100
= OE =
ot:: = VIL
CE = VIL
CE = VIL
CE = OE =
CE
VIL
VIL
intJ
2716
Programming of multiple 2716s in parallel with the
same data can be easily accomplished due to the
simplicity of the programming requirements. Like inputs of the paralleled 2716s may be connected together when they are programmed with t~ same
data. A low level TTL pulse applied to the CE input
programs the paralleled 2716s.
ERASURE CHARACTERISTICS
The erasure characteristics of the 2716 are such
that erasure begins to occur upon exposure to light
with wavelengths shorter than aproximately 4000
Angstroms (A). It should be noted that sunlight and
certain types of fluorescent lamps have wavelengths
in the 3000-4000A range. Data show that constant
exposure to room-level fluorescent lighting could
erase the typical 2716 in approximately 3 years,
while it would take approximately 1 week to cause
erasure when exposed to direct sunlight. If the 2716
is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels should
be placed over the window to prevent unintentional
erasure.
Program Inhibit
Programming of multiple 2716s in parallel with different data is also easily accomplished. Except for CE,
all like inputs (including DE) of the parallel 2716s
may be common. A TTL-level program pulse applied
to a 2716's CE input with Vpp at 25V will program
that 2716. A low-level CE input inhibits the other
2716 from being programmed.
The recommended erasure procedure for the 2716
is exposure to shortwave ultraviolet light which has a
wavelength of 2537 Angstroms (A). The integrated
dose (Le., UV intensity x exposure time) for erasure
should be a minimum of 15 Ws/cm 2. The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 p.W/cm 2
power rating. The 2716 should be placed within 1
inch of the lamp tubes during erasure.
Verify
A verify should be performed on the programmed
bits to determine that they were correctly programmed. The verify may be performed with Vpp at
25V. Except during programming and program verify, Vpp must be at 5V.
210310-3
Figure 3. Standard Programming Flowchart
5-5
2716
CAPACITANCE(4)
TA
=
25°C, f
=
Symbol Parameter Typ(3) Max Unit
1 MHz
t A.C. TEST CONDITIONS
Test
Conditions
Output Load .................... '.. 1 TTL gate and
. CL = 100 pF
=
CIN
Input
Capacitance
4
6
pF VIN
COUT
Output
Capacitance
8
12
pF VOUT
,
=
,
Input Rise and Fall Times .............,.... :S::20 ns
Input Pulse Levels ............ , ...... 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs ........................... O.BV and 2V
Outputs .......................... 0.8V and 2V
OV
OV
A.C. WAVEFORMS(1)
... ----_1
VIH - - - - " "
ADDRESS
VALID
ADDRESSES
V1L----J
V1H
1'----------- · .. -----"1
-----+...,.
CE
1'-------- · · · · ----"1
V1H
------1----...,.
OE
(5)
(5)
•••••••••
(4,6)
tOF
tOE
tOH
•••••••••
V1H
HIGH Z
OUTPUT-----------~~~~~~
VALID OUTPUT
•••••••••
210310-4
NOTES:
1. Vcc must be' applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected to Vcc except during programming. The supply current would then be the sum of Icc and IpP1.
3. Typical values are for T A = 25'C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested.
5. OE may be delayed up to tAcc-tOE after the falling edge of CE without impact on tACC.
6. tDF is specified from OE or CE, whichever occurs first.
5-6
intJ
2716
PROGRAMMING CHARACTERISTICS
=
D.C. PROGRAMMING CHARACTERISTICS TA
Symbol
Parameter
,
=
25°C ±5°C, Vec!1)
Min
Typ
=
5V ±5%, Vpp(1,2)
Max
25V ±1V
Test
Conditions
Units
III
Input Current (for Any Input)
10
p,A
VIN
=
5.25V/0.45
IpP1
Vpp Supply Current
5
mA
CE
VIL
IpP2
Vpp Supply Current during
Programming Pulse
30
mA
CE
=
=
lee
Vee Supply Current
100
mA
VIL
Input Low Level
-0.1
O.B
V
VIH
Input High Level
2.0
5V ± 5%, Vpp(1, 2)
=
25V ± 1V
A.C. PROGRAMMING CHARACTERISTICS T A
Symbol
=
Vee
25°C ± 5°C, Vee(1)
Parameter
Min
Typ
+
=
V
1
Max
Units
tAS
Address Setup Time
2
p,s
tOES
OE Setup Time
2
p,s
,
2
p,s
tAH
Address Hold Time
2
p,s
tOEH
OE Hold Time
2
p,s
tOH
Data HoldTime
2
p,s
tOFP
Output Enable to Output Float Delay
0
tOE
Output Enable to Output Delay
tpw
Program Pulse Width
45
tpRT
Program Pulse Rise Time
5
ns
tpFT
Program Pulse Fall Time
5
ns
tos
. Data Setup Time
50
VIH
Test
Conditions'
200
ns
CE = VIL
200
ns
CE = VIL
55
ms
• A.C. CONDITIONS OF TEST
Input Rise ar:td Fall Times (10% to 90%) ...... 20 ns
Input Pulse Levels ................... O.BV to 2.2V
Input Timing Reference Level ......... O.BV and 2V
Output Timing Reference Level ........ O.BV and 2V
NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The 2716 must not be
inserted into or removed from a board with Vpp at 25 ± 1V to prevent damage to the device.
2. The maximum allowable voltage which may be applied to the Vpp pin during programming is + 26V. eare must be taken
when switching the Vpp supply to prevent overshoot exceeding this 26V maximum specification.
5-7
2716
PROGRAMMING WAVEFORMS
PROGRAM
---J.----
VERIFY - - - - - I
VIH - - - - -...
ADDRESSES
ADDRESS
VIL---J
VIH - - - - _ 1
DATA IN
STABLE
DATA
VIL----....II
t oFP
(D.20 MAX)
VIH
OE
VIL---J
VIH
CE
VIL
---------'1
210310-5
NOTES:
1. All times shown in parenthesis are minimum times and are JLs unless otherwise noted.
2. toE and tOFP are characteristics of the device but must be accommodated by the programmer.
REVISION HISTORY
Number
Description
03
Deleted -5 and -6 speed bins. Added Express options.
Added Standard Programming Flowchart.
Revised Pin Configuration and Block Diagram.
5-8
2732A
32K (4K x 8) UV ERASABLE PROMS
200 ns (2732A-2) Maximum Access
• Time
.•. HMOS*-E Technology
with High-Speed
• Compatible
Microcontrollers and Microprocessors
••• Zero WAIT State
Two Line Control
• 10% Vcc Tolerance Available
•
Current Requirement
• Low
-100 rnA Active
- 35 rnA Standby
inteligent IdentifierTM Mode
• - Automatic Programming Operation
Standard Pinout •.• JEDEC
• Industry
Approved 24 Pin Ceramic Package
(See Packaging Spec. Order #231369)
The Intel 2732A is a 5V-only, 32,768-bit ultraviolet erasable (cerdip) Electrically Programmable Read-Only
Memory (EPROM). The standard 2732A access time is 250 ns with speed selection (2732A-2) available at
200 ns. The access time is compatible with high performance microprocessors such as the 8 MHz iAPX 186. In
these systems, the 2732A allows the microprocessor to operate without the addition of WAIT states.
An important 2732A feature is Output Enable (DE) which is separate from the Chip Enable (CE) control. The
OE control eliminates bus contention in microprocessor systems. The CE is used by the 2732A to place it in a
standby mode (CE = VI H) which reduces power consumption without increasing access time. The standby
mode reduces the current requirement by 65%; the maximum active current is reduced from 100 rnA to a
standby current of 35 rnA.
'HMOS is a patented process of Intel Corporation.
DATA OUTPUTS
00-07
vcc_
Pin Names
OEIVpp_
CE
~~C:::::::-
OUTPUT BUFfERS
Y·GATING
Ao-A"
ADDRESS
INPUTS
X
32.768·BIT
DECODER
CELL MATRIX
AO-A11
Addresses
CE
Chip Enable
OElVpp
Output EnablelVpp
0 0 -07
Outputs
290081-1
Figure 1. Block Diagram
2764A
27512 27256 27128A
27C64 2716
27C512 27C256 27C128
87C64
vpp
vpp
Vpp
A'2
A7
A6
As
A2
AI
Ao
00
0,
02
A'2
A7
As
As
A4
A3
A2
AI
Ao
00
0,
02
A'2
A7
A6
As
A4
A3
A2
AI
Ao
00
0,
02
GND
GND
GND
GND GND
~
Aa,
~---\..J---:
CI
A,S
A'2
A7
A6
As
A4
A3
A2
AI
Ao
00
0,
02
0
I
A7
A6
As
A4
A3
A2
AI
Ao
00
0,
02
2764
27128A 27256 27512
2716 2764A
27C128 27C256 27C512
87C64
2732A
Vcc
I
Vee
AS
As
A11
Vpp
DE
A,O
A'0
CE
07
00
0&
0,
°5
°40
3
GND
As
Ag
liE/vpp
Ao
°2
PGM
Vce N.C.
As
Ag
AI1
VCC
J5GM
VCC
Vcc
A'3
A'4
A'3
As
As
Ag
AI1
A'4
A'3
As
Ag
AI1
Ag
AI1
OE
OE
OE
OElVpp
A'0
A'0
AIO
AIO
CE
CE
07
06
05
04
03
07
06
05
04
03
CE
ALE/CE
07
06
05
04
03
07
06
05
04
03
CE
CE
07
06
05
04
03
290081-2
NOTE:
Intel "Universal Site" compatible EPROM configurations are shown in the blocks adjacent to the 2732A pins.
Figure 2. Cerdip Pin Configuration
5-9
September 1989
Order Number: 290081-004
2732A
EXTENDED TEMPERATURE
(EXPRESS) EPROMs
EXPRESS EPROM PRODUCT FAMILY
The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM, allowing
the choice of appropriate memory size to match system applications. EXPRESS EPROM products are
available with 168 ±8 hour, 125·C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROM operating temperature range is O·C to 70·C. Extended operating temperature range (-40·C to + 85·C) EXPRESS products are available. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.
PRODUCT DEFINITONS
Type Operating Temperature Burn-In 125·C (hr)
Q
O·Cto +70·C
168 ±8
- 40·C to + 85·C
T
None
-40·Cto +85·C
168 ±8
L
EXPRESS OPTIONS'
2732A Versions
Packaging Options
Speed Versions
-2
Cerdip
Q
-25
Q, T,L
READ OPERATION
D.C. CHARACTERISTICS
Electrical Parameters of EXPRESS EPROM products are identical to standard EPROM parameters
except for:
Symbol
ISB
ICC1(1)
Parameter
TD2732A
LD2732A
Min
Max
Test
Conditions
Vee Standby
Current (mAl
45
CE
OE
= VIH,
= VIL
VccActive
Current (mAl
150
OE
=
VccActive
Current at High
Temperature (mAl
125
OE = CE = VIL,
Vpp = Vee,
T Ambient = 85·C
CE
=
VIL
NOTE:
1. Maximum current value is with outputs 00 to 07 unloaded.
30 J1.s
H
°70
AonnJ
.J"LJ
•
°s
°40 3
Binary Sequence from Ao to A11
Vee
6
OElVpp = +5V. R = 1Kn.
vss = GND. CE = GND
vcc
A1
•
290081-4
290081-3
=
+5V
Burn-In Bias and Timing Diagrams
5-10
inter
2732A
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temp. During Read ....... O·C to + 70·C
Temperature Under Bias ......... -10·C to + SO·C
Storage Temperature .......... - 55·C to + 125·C
All Input or Output Voltages with
Respect to Ground .............. - 0.3V to + 5V
Voltage on A9 with Respect
to Ground ................... - 0.3V to + 13.5V
Vpp Supply Voltage with Respect to Ground
During Programming ........... - 0.3V to + 22V
Vcc Supply Voltage with
Respect to Ground ............ - 0.3V to + 7.0V
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
READ OPERATION
D.C. CHARACTERISTICS o·c s
Symbol
TA S
+ 70·C
Limits
Parameter
Typ(3)
Min
III
Input Load Current
Units
Conditions
Max
10
p.A
VIN
=
5.5V
ILO
Output Leakage Current
10
p.A
VOUT
=
15S(2)
Vcc Current (Standby)
35
rnA
CE
VIH, OE
ICC1(2)
Vcc Current (Active)
100
rnA
=
OE =
VIL
Input Low Voltage
-0.1
O.S
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
A.C. CHARACTERISTICS o·c s
Versions
Symbol
Vcc
+
5.5V
CE
=
=
VIL
VIL
V
1
0.45
= 2.1 rnA
10H = - 400 p.A
V
2.4
10L
V
T A S 70·C
Vee ±5%
2732A-2
2732A
Vee ±10%
2732A-20
2732A-25
Parameter
Min
Max
Min
Units
Test
Conditions
Max
tACC
Address to Output Delay
200
250
ns
CE
tCE
CE to Output Delay
200
250
ns
OE
tOE
OElVpp to Output Delay
70
100
ns
CE
tDF(4)
OElVpp High to Output Float
0
50
ns
CE
tOH(4)
Output Hold from Addresses,
CE or OElVpp, Whichever
Occurred First
0
ns
CE
50
0
0
= OE =
= VIL
= VIL
= VIL
= OE =
VIL
VIL
NOTES:
1. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
2. The maximum current value is with outputs 00 to 07 unloaded.
3. Typical values are for TA = 25'C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
5-11
intJ
2732A
CAPACITANCE (2) TA =
Symbol
25'C. f
= 1 MHz
Parameter
CIN1
Input Capacitance
Except OElVpp
CIN2
OElVpp Input
Capacitance
COUT
Output Capacitance
Typ
Max
Unit
4
6
pF
VIN = OV
20
pF
VIN = OV
12
pF
VOUT = OV
8
A.C. TESTING INPUT/OUTPUT WAVEFORM
Conditions
A.C. TESTING LOAD CIRCUIT
f
l'N...
2.4
2.0>
0.8
0.45
___
TEST POINTS ---.....
2.0
OUTPUT
3.3Kn
,,0:;,;;.8:...._ _
DEVICE
UNDER
290081-5
~oUT
TEST
rc,,='OOPF
A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for
a logic "0". Timing measurements are made at 2.0V for a logic
"I" and 0.8V for a logic "0".
=
290081-6
CL = 100 pF
CL Includes Jig Capacitance
A.C. WAVEFORMS
VIH - - - - - - - " ' ' \ .
V _ _ _ _ _ _ _.1
ADDRESSES
IL
1,.--------_ ....... .
1'-------........ .
ADDRESS
VALID
VIH - - - - - - - - - / - "
CE
VIL
VIH
1'-----........ .
--------+--_
OE/Vpp
VIL
~--.-+
........ .
OUTPUT _ _ _ _ _ _~H_IG;;.;H_Z:-_ _ _~E_++
__
TEST POINTS _ _ _
0.8
A.C. TESTING LOAD CIRCUIT
2.0
OUTPUT
=0.;:.8_ __
3.3KU
0.45
DEVICE
230864-3
UNDER
T~ST
A.C. Testing; Inputs are Driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing Measurements are made at 2.0V for a
Logic "1" and 0.8V for a Logic "0".
I---+--O~
ICL '"
OUT
100pF
230864-4
CL = 100 pF
CL Includes Jig Capacitance
A.C. WAVEFORMS
V,H-----_
ADDRESSES
VIL _ _ _ _ _- J
ADDRESS
VALID
V,H --------11-""\
V,H --------1----"""\
OUTPUT _ _ _ _ _ _H:.::I.:::OH::;Z=-_ _ _ _~~+H~
HIOHZ
230864-5
NOTES:
1. Typical values are for T A = 25'C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE.
5·22
2764A
To use these two control lines most efficiently, CE
should be decoded and used as the primary device
selecting function, while OE should be made a common connection to all devices in the array and connected to the READ line from the system control
bus. This assures that all deselected memory devices are in their low power standby mode and that the
output pins are active only when data is desired from
a particular memory device.
DEVICE OPERATION
The modes of operation of the 2764A are listed in
Table 1. A single 5V power supply is required in the
read mode. All inputs are TTL levels except for Vpp
and 12V on Ag for inteligent identifier mode.
Table 1. Mode Selection
Pins
Mode
CE OE PGM
Ag
AD Vpp Vee Outputs
Read
VIL VIL
VIH
X(I)
X Vee 5.0V
DOUT
Output Disable
VIL VIH
VIH
X
HighZ
Standby
VIH
X
X
X
X Vee 5.0V
X Vee 5.0V
Programming
VIL VIH
VIL
X
X
(4)
(4)
Program Verify
VIL VIL
VIH
X
X
(4)
(4)
DOUT
Program Inhibit
VIH
X
X
X
(4)
(4)
HighZ
X
inleligent Identifier(3)
-manufacturer
VIL VIL
-device
VIL VIL
SYSTEM CONSIDERATIONS
HighZ
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The as-'
sociated transient voltage peaks can be suppressed
by complying with Intel's Two-Line Control and by
properly selected decoupling capacitors. It is recommended that a 0.1 /kF ceramic capacitor be used on
every device between Vcc and GND. This should be
a high frequency capacitor of low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 /kF bulk electrolytic
capacitor should be used between Vcc and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effect of· PC board-traces.
DIN
VIH
VH(2) VIL Vee 5.0V
B9H
VIH
VH(2) VIH Vee 5.0V
OBH
NOTES:
1. X ean be VIH or VIL.
2. VH = 12.0V±O.5V.
3. Al-AB, Al0-A12 = VIL.
4. See Table 2 for Vee and Vpp voltages.
Read,Mode
The 2764A has two control functions, both of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to
gate data from the output pins, independent of de'vice selection. Assuming that addresses are stable,
the address access time (tACel is equal to the delay
from CE to output (teE), Data is available at the outputs after a delay of toE from the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tACC-toE'
PROGRAMMING MODES
Caution: Exceeding 14V on Vpp will permanently
damage the device.
Standby Mode
Initially, all bits of the EPROM are in the "1" state.
Data is introduced by selectively programming "Os"
into the desired bit locations. Although only "Os" will
be programmed, both "1s" and "Os" can be present
in the data word. The only way to change a "0" to a
"1" is by ultraviolet light exposure (Cerdip
EPROMs).
EPROMs can be placed in a standby mode which
reduces the maximum current of the devices by applying a TTL-high signal to the CE input. When in the
standby mode, the outputs are in a high impedance
state, independent of the. OE input.
Two Line Output Control
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 control lines which
accommodate this multiple memory connection. The
two control lines allow for:
a) the lowest possible memory power dissipation,
and
The device is in the programming mode when Vpp is
. raised to its programming voltage (see Table 2) and
CE and PGM are both at TTL-low. The data to be
programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and
data inputs are TTL.
b) complete assurance that output bus contention
will not occur.
5-23
2764A
Program Inhibit
dress line AO from VIL to VIH. All other address lines
must be held at VIL during inteligent Identifier Mode.
Programming of multiple EPROMs in parallel with
different data is easily accomplished by using the
Program Inhibit mode. A high-level CE or PGM input
inhibits the other devices from being programmed.
Byte 0 (AO = VIU represents the manufacturer code
and byte 1(AO = VI H) the device identifier code.
These two identifier bytes are given in Table 1.
Except for CE, all like inputs (including OE) of the
parallel EPROMs may be common. A TIL low-level
pulse applied to the CE input with Vpp at its programming voltage (see Table 2) will program the selected device.
Program Verify
A verify should be performed on the programmed
bits to determine that they have been correctly programmed. The verify is performed with OE at VIL,
PGM at VIH and Vpp and Vee at their programming
voltages.
inteligent Identifier™ Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device.
To activiate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling ad-
ERASURE CHARACTERISTICS
The erasure characteristics are such that erasure
begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000 A range. Data shows that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately three years, while it
would take approximately one week to cause erasure when exposed to direct sunlight. If the EPROM
is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels should
be placed over the window to prevent unintentional
erasure.
The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a
minimum of fifteen (1'5) Wsec/cm 2. The erasure
time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12,000 p.W/cm2
power rating. The EPROM should be placed 'within
one inch of the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to
without damage is 7258 Wsec/cm 2 (1 week @
12000 p,W/cm2). Exposure of the EPROM to high
intensity UV light for longer periods may cause permanent damage.
5-24
2764A
DEVICE
FAILED
DEVICE
FAILED
230864-7
Figure 3. inteligent Programmlng™ Flowchart
gram pulse of length 3X msec. X is an iteration counter and is equal to the number of the initial one millisecond pulses applied to a particular location, before a correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram pulse is applied.
inteligent Programming™ Algorithm
The inteligent Programming Algorithm, a standard in
the industry for the past few years, is required for all
of Intel's 12.5V CERDIP EPROMs. Plastic EPROMs
may also be programmed using this method. A flowchart of the inteligent Programming Algorithm is
'
shown in Figure 3.
The entire sequence of program pulses and byte
verifications Is performed at Vee = 6.0V and
The inteligent Programming Algorithm utilizes two
different pulse types: initial and overprogram. The
duration of the initial PGM pulse(s) is one millisecond, which will then be followed by a longer overpro-
Vpp = 12.SV. When the inteligent Programming cycle has been completed, all bytes should be compared to the original data with Vee = Vpp = 5.0V.
5-25
intJ
2764A
Table 2
D.C. PROGRAMMING CHARACTERISTICS
Symbol
TA = 25°C ± 5°C
Limits
Parameter
III
Input Current (All Inputs)
Vil
Input Low Level (All Inputs)
Min
Max
Unit
10
-0.1
0.8
/LA
V
2.0
Vee
0.45
VIN
= Vil or VIH
V
IOl
V
IOH
= 2.1 mA
= - 400 /LA
CE
= Vil
CE
=
VIH
Input High Level
VOL
Output Low Voltage During Verify
VOH
lee2(4)
Output High Voltage During Verify
Vee Supply Current (Program & Verify)
75
mA
IpP2(4)
Vpp Supply Current (Program)
50
mA
VIO
Vpp
Ag inteligent Identifier Voltage
12.5
V
inteligent Programming Algorithm
12.0
13.0
V
Vee
inteligent Programming Algorithm
5.75
6.25
V
2.4
11.5
Test Conditions
(see Note 1)
V
PGM
= Vil
A.C. PROGRAMMING CHARACTERISTICS.
TA = 25°C ±5°C (see table 2 for Vee and Vpp voltages)
Symbol
Limits
Parameter
Min
Typ
Max
Unit
tAS
Address Setup Time
2
/Ls
tOES
OE Setup Time
2
/Ls
tos
Data Setup Time
2
/Ls
tAH
Address Hold Time
0
/Ls
tOH
Data Hold Time
2
tOFP
OE High to Output
Float Delay
0
130
/Ls
ns
tvps
Vpp Setup Time
2
/Ls
tves
Vee Setup Time
2
/Ls
teEs
tpw
CE Setup Time
2
PGM Initial Program Pulse Width
0.95
topw
PGM Overprogram Pulse Width
2.85
tOE
Data Valid from OE
1.0
1.05
/Ls
ms
78.75
ms
150
ns
Test Conditions'
(see Note 1)
(See Note 3)
(see Note 2)
NOTES:
1. Vee must be applied simultaneously or before Vpp and
.
removed simultaneously or after Vpp.
2. The length of the overprogrampulse may vary from 2.85
msec to 78.75 msec as a function of the iteration counter
value X.
3. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no longer driven-see timing diagram.
4. The maximum current value is with Outputs 00 to 07
unloaded.
• A.C. CONDITIONS OF TEST
Input Rise and Fall Times
(10% to 90%) ............... , ...........•. 20 ns
Input Pulse Levels .................. 0.45V to 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 2.0V
5-26
inter
2764A
PROGRAMMING WAVEFORMS
VERIFY
PROGRAM
.~
ADDRESSES
ADDRESS STABLE
~
DATA
~
_IAS_
1\
DATA IN STABLE
HlghZ
~
_IAH
DATA OUT JALID
-
~IDH.
_'DS_
C
r ' D..
12.SY
,~
vpp
s.w
I--'vps6.DV
, Vee
r~
5.GV
,-
f---Ivcs-
VrH
~
I--tc.s -
-
~
V,H
I
Ipw
I-
I-to"1
'OPW
I-
\
*- to._
230864-8
NOTES:
1. The input timing reference level is O.BV for VIL and 2V for a VIH.
2. toE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the 2764A, a 0.1 ,..F capacitor is required across Vpp and ground to suppress spurious voltage
transients which can damage the device.
REVISION HISTORY
Description
Number
06
Deleted Plastic DIP package. Deleted QuickPulse sections.
Revised Pin Configuration. Revised Express options. Deleted
- 3, - 30, - 4 and ~ 45 speed bins.
D.C. Characteristics - III Conditions are VIN = OV to Vee
D.C. Characteristics - ILO Conditions are VOUT = OV to Vee
5-27
27128A
128K (16K x 8) PRODUCTION AND UV ERASABLE PROMs
• Fast 150 nsec Access Time
- HMOS* II-E Technology
• Low Power
- 100 mA Maximum Active
- 40 mA Maximum Standby
• inteligent Identifier™ Mode
- Automated Programming Operations
•
± 10% Vee Tolerance Available
• Available in 28-Pin Cerdip Package
(See Packaging Spec, Order #231369)
The Intel 27128A is a 5Vonly, 131,072-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The 27128A is fabricated with Intel's HMOS* II-E technology which significantly reduces die size
and greatly improves the device's performance, reliability and manufacturability.
The 27128A is currently available in the CERDIP package providing flexibility in prototyping and R&D environments where reprogrammability is required.
The 27128A is available in fast access times including 150 ns (27128A-l). This ensures compatibility with highperformance microprocessors, such as Intel's 8 MHz 80186 allowing full speed operation without the addition
of WAIT states. The 27128A is also directly compatible with the 12 MHz 8051 family.
"HMOS is a patented process of Intel Corporation.
DATA OUTPUTS
vcco-o--..
.
GNDo-o--..
.
Vpp 0
00-0 7
•
OUTPUT BUFFERS
Y-GATING
Ao-A13
ADDRESS
INPUTS
X
DECODER
131,072·BIT
CELL MATRIX
230849-1
Figure 1. Block Diagram
5-28
October 1990
Order Number: 230849-009
27128A
Pin Names
27512
27C512
27256
27C256
2764A
27C64
87C64
A,S
Vpp
Vpp
A'2
A7
A.
As
A'2
A7
A'2
A7
A7
As
As
As
As
As
A.
A3
A2
A,
Ao
00
0,
02
GND
As
~
A3
A2
A,
Ao
00
0,
O2
GND
~
A3
A2
A,
Ao
00
0,
02
GND
2732A
Ao-A'3
ADDRESSES
CE
CHIP ENABLE
DE
OUTPUT ENABLE
Do-Or
OUTPUTS
PGM
PROGRAM
NC
NO INTERNAL CONNECT
27128A
2716
Vpp
~
Aa
A2
A,
Ao
00
0,
02
GND
2716
27256
27C256
27512
27C512
Vee
Vee
PGM
Vee
A,.
Ag
N.C.
As
Ag
A"
A'3
As
Ag
Al1
OE
A,o
Al1
OE
A,o
A"
OE/Vpp
A,o
Vee
PGM
A'2
A7
As
Au
As
Ag
~
A4
A"
A3
A2
A,
A3
Ao
00
0,
02
GND
A7
A.
As
2764A
27C64
87C64
2732A
Vee
Or
Vee
As
Ag
Vpp
OE
A2
A,o
A,o
A"
OE/Vpp
A,o
A,
EE
CE
CE
Al£/CE
ALE/CE
CE
CE
Ao
00
°7
0.
0,
°s
°2
GND
07
D.
05
D.
03
07
D.
Os
D.
03
07
D.
Os
D.
03
07
D.
Os
D.
°3
07
D.
05
D.
03
A.
O~
As
CE
230849-2
NOTE: Intel ".Universal Site"-Compatible EPROM Pin Configurations are Shown in the Blocks Adjacent to the 27128A Pins
Figure 2. Cerdlp(D) DIP Pin Configuration
5-29
A'3
As
Ag
Os
inter
27128A
EXTENDED TEMPERATURE
(EXPRESS) EPROMS
The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is'
available for several densities of EPROM, allowing
the choice of appropriate memory size to match sys, tem applications. EXPRESS EPROM products are
available with 168 ± 8 hour, 125'C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROM operat,ing temperature range is O'C to 70·C. Extended operating temperature range (- 40'C to + 85'C) EXPRESS products are available. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AQL. This may allow the user to
,reduce or eliminate incoming inspection testing.
EXPRESS EPROM PRODUCT FAMILY
EXPRESS OPTIONS
PRODUCT DEFINITIONS
27128A Versions
Type
Operating Temperature
Burn-in 125'C (hr)
0'
T
O'Cto +70'C
168 ±8
- 40'C to + 85'C
None
L
-40'Cto +85'C
168 ±8
Packaging Options
I
Speed Versions
Cerdlp
' I
-20
T,L,O
READ OPERATION
DC CHARACTERISTICS
Electrical Parameters of Express EPROM Products are identical to standard EPROM parameters except for'
Symbol
TD27128A, LD27128A
Parameter
Min
ISB
leel(l)
Test Conditions
Max
Vcc Standby Current (mA)
50
Vee Active Current (mA)
125
Vee Active Current
at High Temperature (mA)
100
CE = VIH, OE = VIL
OE = CE = VIL
OE = CE = VIL,VPP = Vee
TAmbient = 85'C
NOTE:
1. The maximum current value is with Outputs 00 to 07 unloaded.
30 P"
H
AonrlS
.
AIJLr'
AI3
Binary Sequence from Ao to AI3
OE=+5V
vpp = +5V
R=lkfl
Vss = GND
230849-10
Vcc=+5V
eE = GND
Burn-In Bias and Timing Diagrams
5-30
230849-11
intJ
27128A
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temperature During
Read ................. '.' ........ O°C to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 70°C
Temperature Under Bias ......... -10°C to + ao°c
Storage Temperature .......... - 65°C to + 125°C
All Input or Output Voltages with
Respect to Ground ........... - O.6V to
+ 6.25V
Voltage on Ag with
Respect to Ground ........... - O.6V to
+ 13.5V
Vpp Supply Voltage with Respect to
Ground During Programming .... - O.6V to
+ 14V
VCC Supply Volt~ge
with Respect to Ground ........ - O.6V to
+ 7.0V
READ OPERATION
DC CHARACTERISTICS
Symbol
O°C :;;; T A :;;;
+ 70°C
Limits
Parameter
Notes
Typ(3)
Min
Units
Max
Conditions
III
Input Load Current
10
).LA
VIN=OV to Vcc
ILO
Output Leakage Current
10
).LA
VOUT=OVto Vcc
IpP1
Vpp Current Read
5
mA
Vpp=5.5V
IS8
Vcc Current Standby
40
mA
CE=VIH
ICC1
Vcc Current Active
100
mA
CE=OE=VIL
VIL
Input Low Voltage
-0.1
+0.8
V
VIH
Input High Voltage
2.0
Vcc+ 1
V
VOL
Output Low Voltage
0.45
V
IOL =2.1 mA
VOH
Output High Voltage
V
IOH= -400).LA
Vpp
Vpp Read Voltage
V
Vcc=5.0V±0.25
AC CHARACTERISTICS
Versions(5)
2
2
2.4
2
O°C :;;; T A :;;;
VCC±5%
Vcc±10%
Symbol
3.8
Vcc
+ 70°C
Notes
Characteristics
27128A-l
Min
Max
27128A-2
27128A
27128A-20
27128A-25
Min
Max
Min
Unit
Max
tACC
Address to Output Delay
150
200
250
,ns
tCE
CE to Output Delay
150
200
250
ns
tOE
OE to Output Delay
65
75
100
ns
tOF
OE High to Output Float
4
0
60
ns
tOH
Output Hold from
Addresses CE or OE
Whichever Occurred First
4
0
55
0
0
55
0
0
ns
NOTES:
1. Vec must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vcc except during programming. The supply current would then be the sum of Icc and
IpP1. The maximum current value is with Outputs 00 to 07 unloaded.
3. Typical values are for TA = 25'C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested. Output Float is defined as. the point where data is no longer
drlven-see timing diagram.
5-31
intJ
27128A
CAPACITANCE(2hA =
Symbol
25°C, f
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
=
1MHz
Typ(l)
Max
Unit
4
8
6
pF
VIN = OV
12
pF
VOUT = OV
AC TESTING INPUT/OUTPUT WAVEFORM
Conditions
AC TESTING LOAD CIRCUIT
1.3V
lNS14
2.4
2.0>
__
TEST POINTS _ _
0.8
0.45
2.0
~0.;.;.8
OUTPUT'
_ __
3.3Kn
DEVICE
UNDER
TEST
230849-3
OUT
-'
A.C. lesling inpuls are driven al 2.4V for a Logic '"''" and 0.45V
for a Logic "'0"'. Timing measuremenls are made al 2.0V for a
Logic """' and O.BV for a Logic "'0.'"
CL = ,00 pF
CL Includes Jig Capacilance
I-
CL~100pF
230B49-4
AC WAVEFORMS
V , H - - - - - -....
ADDRESS
VALID
ADDRESSES
VIL------.1
V,H
--------t--,
_ - - - t e e I31 _ _ _ _ + _
V,H
-------+----_
'-----1-- •••.
~----t.cc-----.-.j
OUTPUT _ _ _ _ _ _....:.:H;.::IG::;H~Z;...._ _ _ _ _~Ht_++<
HIGHZ
230B49-5
NOTES:
1. Typical values are for T A = 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE-toE after the falling edge of CE without impact on teE.
5-32
inter
27128A
DEVICE OPERATION
The modes of operation of the 27128A are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for Vpp and 12V on·A9 for inteligent Identifier.
Table 1 Modes Selection
Ag
Outputs
Mode
Notes
CE
OE
PGM
Vpp
AD
Vee
Read
1
Output Disable
Standby
Programming
5.0V
DOUT
HighZ
Vee
Vpp
5.0V
HighZ
6.0V
DIN
Vpp
6.0V
VIH
VIH
VIH
X
VIH
X
VIL
VIH
VIL
VIL
VIH
VIL
X
Vpp
6.0V
DOUT
HighZ
Manufacturer
2,3
VIL
VIL
VIH
VH
VIL
Vee
5.0V
89H
Device
2,3
VIL
VIL
VIH
VH
VIH
Vee
5.0V
89H
Program Inhibit
I
I
5.0V
Vee
VIL
VIL
4
4
4
Program Verify
inteligent
Identifier
X
X
X
X
X
X
Vee
VIH
X
X
X
X
X
X
X
VIL
NOTES:
1.
2.
3.
4.
X can be VIL or VIH
VH = 12.0V ±O.5V
A1-Aa, A10-A12 = VIL
See Table 2 for Vee and Vpp voltages.
To use these two control lines most efficiently, CE
should be decoded and used as the primary device
selecting function, while OE should be made a common connection to all devices in the array and connected to the READ line from the system control
bus. This assures that all deselected memory
devices are in their low power standby mode and
that the output pins are active only when data is
desired from a particular memory device.
Read Mode
The 27128A has two control functions, both of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to
gate data from the output pins, independent of device selection. Assuming that addresses are stable,
the address access time (tAee) is equal to the delay
from CE to output (teE). Data is available at the outputs after a delay of toE from the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tAee-tOE.
SYSTEM CONSIDERATIONS
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, IcC, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed
by complying with Intel's Two-Line Control, and by
properly selected decoupling capacitors. It is recommended that a 0.1 /LF ceramic capacitor be used on
every device between Vee and GND. This should be
a high frequency capacitor for low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 /LF bulk electrolytic
capacitor should be used between Vee and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effect of PC board-traces.
Standby Mode
EPROMs can be placed in standby mode which reduces the maximum current of the device by applying a TTL-high signal to the CE input. When in standby mode, the outputs are in a high impedance state,
independent of the OE input.
Two Line Output Control
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 control lines which
accommodate this multiple memory connection. The
two control lines allow for:
a) the lowest possible memory power dissipation,
and
b) complete assurance that output bus contention
will not occur
5-33
inter
27128A
PROGRAMMING MODES
Caution: Exceeding 14 V on Vpp will permanently
damage the device.
Initially, and after each erasure, all bits of the
EPROM are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations. Although only "Os" will be programmed,
both "1 s" and "Os" can be present in the data word.
The only way to change a "0" to a "1" is by ultraviolet light erasure.
The device is in the programming mode when Vpp is
raised to its programming voltage (See Table 2) and
CE and PGM are both at TTL low. The data to be
programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and
data inputs are TTL.
of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line Ag of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line Ao from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
M~&
.
Byte 0 (Ao = VII) represents the manufacturer code
and byte 1 (Ao = VI H) the device identifier code.
These' two identifier bytes are given in Table 1.
ERASURE CHARACTERISTICS
Program Inhibit
Programming of multiple EPROMS in parallel with
different data is easily accomplished by using the
Program Inhibit mode. A high-level CE or PGM input
. inhibits the other devices from being programmed.
Except for CE, all like inputs (including OE) of the
parallel EPROMs may be common. A TTL low-level
pulse applied to the PGM input with Vpp at its programming voltage and CE at TTL-Low will program
the selected device.
The erasure characteristics are such that erasure
begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the device is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.
Program Verify
The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (i.e., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 /kW/cm2 power rating. The EPROM should be placed within 1 inch of
the lamp tubes during erasure. The maicimum integrated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000 /kW/
cm 2). Exposure of the device to high intensity UV
light for longer periods may cause permanent damage.
A verify should be performed on the programmed
bits to determine that they have been correctly programmed. The verify is performed with OE at VIL, CE
at VIL, PGM at VIH and Vpp and Vee at their programming voltages.
inteligent Identifier Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the pl1lrpose
5-34
27128A
DEVICE
FAILED
DEVICE
FAILED
230849-6
Figure 3. inteligent Programming Flowchart
pulse of iength 3X msec. X is an iteration counter
and is equal to the number of the initial one millisecond pulses applied to a particular location, before a
correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram
pulse is applied.
inteligent Programming™ Algorithm
The inteligent Programming™ Algorithm, a standard
in the industry for the past few years, is required for
the 27128A. A flow-chart of the inteligent Programming Algorithm is shown in Figure 3.
The entire sequence of program pulses and byte
verifications is performed at Vee = 6.0V and
Vpp = 12.Sv' When the inteligent Programming cy-
The inteligent Programming Algorithm utilizes two
different pulse types: initial and overprogram. The
duration of the initial pulse(s} is one millisecond,
which will then be followed by a larger overprogram
cle has been completed, all bytes should be compared to the original data with Vee = Vpp = 5.0V.
5-35
inter
27128A
DC PROGRAMMING CHARACTERISTICS
Symbol
TA = 25°C ±5°C
limits
Min
Max
Unit
Test Conditions
(Note 1)
10
p.A
VIN "'" VIL or VIH
-0.1
0.8
V
2.0
Vee + 1
V
0.45
V
10L = 2.1 mA
V
10H = - 400 p.A
Parameter
III
Input Current (All Inputs)
VIL
Input Low Level (All Inputs)
VIH
Input High Level
VOL
Output Low Voltage During Verify
VOH
Output High Voltage During Verify
lee2(4)
Vee Supply Current (Program & Verify)
100
rnA
IpP2
Vpp Supply Current (Program)
50
rnA
2.4
VIO
Ag inteligent Identifier Voltage
11.5
12.5
V
Vpp
inteligent Programming Algorithm
12.0
13.0
V
Vee
inteligent Programming Algorithm
5.75
6.25
V
CE
=
VIL
CE
=
PGM
=
VIL
AC PROGRAMMING CHARACTERISTICS
= 25°C ±5°C (See Table 2 for Vee and Vpp voltages.)
TA
Symbol
Limits
Parameter
Min
Typ
Max
Unit
tAS
Address Setup Time
2
p.s
toES
OE Setup Time
2
p.s
tos
Data Setup Time
2
p.s
tAH
Address Hold Time
0
p.s
tOH
Data Hold Time
2
tOFP
OE High to Output Float Delay
0
tvps
Vpp Setup Time
2
p.s
tves
Vee Setup Time
2
p.s
teEs
CE Setup Time
2
tpw
PGM Initial Program Pulse Width
0.95
topw
PGM OVerprogram Pulse Width
2.85
tOE
Data Valid from OE
*AC
Conditions·
(Note 1)
p.s
130
ns
(Note 3)
p.s
1.0
1.05
ms
78.75
ms
150
ns
(Note 2)
NOTES:
CONDIT,ONS OF TEST
1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp.
2. The length of the overprogram pulse may vary from
2.85 msec to 78.75 msec as a function of the iteration
counter value X.
3. This parameter is only sampled and is not 100% tested.
Output Float is defined as the pOint where data is no longer driven-see liming diagram.
4. The maximum current value is with outputs 00-07 un·
loaded.
Input Rise and Fall Times (10% to 90%) ...... 20 ns
Input Pulse Levels ....•.........•... 0.45V to 2.4V
Input Timing Reference Level ...•... 0.8V and 2.0V
Output Timing Reference Level ..•..• 0.8V and 2.0V
5-36
27128A
PROGRAMMING WAVEFORMS
PROGRAM
V'H
ADDRESSES
VIL
~
VERIFY
ADDRESS STABLE
--
f4--'A5_
DATA
~
DATA IN STABLE
HIGHZ
_'AH
DATA OUT VALID
-
~.tOH ...
f4-- ' 0 5 _
L
r-
tOFP
12.5V
V__
5.OV
I
f4--'vP5 _
6.0V
Vee
S.OV
V'H
CE
VIL
I
l-'ve5_
~
~'CES_
V'H
PGM
VIL
V'H
DE
VIL
-
\.....-..J
-
Ipw
topw
I-
_ ' 0' 5 1
"\
I-
I-
10.
230849-7
NOTES:
1. The Input Timing Reference Level is 0.8V for VIL and 2V for a VIH.
2. toE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the 27128A, a 0.1 J.'F capaCitor is required across Vpp and ground to suppress spurious voltage
transients which can damage the device.
REVISION HISTORY
Number
Description
009
Removed Plastic Package
5-37
in1:el®
27256
256K (32K x 8) PRODUCTION AND UV ERASABLE PROMS
•
New Quick-Pulse Programming™
Algorithm for Plastic P27256
- 4 Second Programming
- inteligent Programming™ Algorithm
Compatible
• Fast Access Time
-170 ns 027256-1
- 200 ns P27256-2
•
Plastic Production P27256 is
Compatible with Auto-Insertion
Equipment
•
•
Moisture Resistant
Industry Standard Pinout •.. JEOEC
Approved ••• 28 Lead Cerdip and
Plastic Package
(See Packaging Spec, Order # 231369)
• inteligent IdentifierTM Mode
The Intel 27256 is a 5V only, 262,144-bit Ultraviolet Erasable (Cerdip)/plastic production (P27256) electrically
programmable read-only memory (EPROM). Organized as 32K words by 8 bits, individual bytes can be accessed in less than 170 ns (27256-1). This is compatible with high performance microprocessors, such as the
Intel iAPX 186, allowing full speed operation without the addition of performance-degrading WAIT states. The
27256 is also directly compatible with Intel's 8051 family of microcontrollers.
The Plastic P27256 is ideal for high volume production environments where code flexibility is crucial. Plastic
packaging is also well-suited to auto-insertion equipment in cost-effective automated assembly lines. Intel's
new Quick-Pulse Programming Algorithm enables the P27256 to be programmed within four seconds (plus
programmer overhead). Programming equipment which takes advantage of this innovation will electronically
identify the EPROM with the help of the inteligent Identifier and rapidly program it using a superior programming method. The inteligent Programming Algorithm may be utilized in the absence of such equipment.
The 27256 enables implementation of new, advanced systems with firmware-intensive' architectures. The
combination of the 27256's high-density, cost-effective EPROM storage, and new advanced microprocessors
having megabit addressing capability provides designers with opportunities to engineer user-friendly, high
reliability, high-performance systems.
The 27256's large storage capability of 32 K-bytes enables it to function as a high-density software carrier.
Entire operating systems, diagnostics, high-level language programs and specialized application software can
reside in a 27256 EPROM directly on a system's memory bus. This permits immediate microprocessor access
and execution of software and elminates the need for time-consuming disk accesses and downloads.
Two-line control and JEDEC-approved, 28-pin packaging are standard features of all Intel high-density
EPROMs. This assures easy microprocessor interfacing and minimum design efforts when upgrading, adding,
or choosing between nonvolatile memory alternatives.
The 27256 is manufactured using Intel's advanced HMOS*II-E technology.
"HMOS is a patented process of Intel Corporation.
DATA OUTPUTS
0.-0,
OE
CE
A14
- AoADDRESS
INPUTS
~~:::::!..J~-~
Y.(lATING
1
262,144 BIT
CELLMAmlX
290097-1
Figure 1. Block Diagram
5-38
September 1989
Order Number: 290097-004
inter
27256
Pin Names
2764A
27C64
87C64
27512
27C512
27128A
27C128
AIS
A12
A7
A.
A2
Al
AD
00
01
02
Vpp
A12
A7
As
AS
A4
A.
A2
Al
AD
00
01
02
Vpp
A12
A7
As
As
A4
A.
A2
Al
GND
GND
As
AS
Pv.
2732A
Ao-A14
Addresses
CE
Chip Enable
DE
Output Enable
00-0 7
Outputs
N.C.
No Connect
27256
P27256
2716
2716
2732A
Ye e
Vee
PGM
A"
A"
A7.
As
AS
Pv.
A.
A7
As
AS
A4
Aa
Aa
A2
Al
Ao
Ao
00
01
02
00
01
02
A2
Al
AD
00
01
02
GND
GND
GND
A,
Au
DE
0,
00
0,
0&
O!l
02
04
GND""L.:....-_....:.;;rO,
2764A
27C64
87C64
Vee
As
As
Vpp
OE
AID
eE
07
06
Os
04
O.
27182A
27C128
27512
27C512
Vee
Vee
A14
AI.
As
A9
All
OElVpp
AID
PGM
Vee
As
Ag
Al1
OElVpp
AID
N.C.
As
A9
All
AID
AI.
As
A9
All
OE
AID
eE
eE
eE
07
06
Os
04
O.
07
06
Os
04
O.
07
Os
Os
04
O.
07
Os
Os
04
O.
cr
DE
, 290097-2
NOTE:
Intel"Universal Site"-Compatible EPROM pin configurations are shown in the blocks adjacent to the P27256 pins.
Figure 2_ Cerdip/Plastic DIP Pin Configuration
5-39
intJ
27256
The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM, allowing
the choice of appropriate memory size to match system applications~ EXPRESS EPROM products are
available with 168 ± 8 hour, 125·C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROM operating temperature range is O·C to 70·C. Extended operating temperature range (- 40·C to + 85·C) EXPRESS products are available. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.
EXPRESS EPROM PRODUCT FAMILY
EXPRESS OPTioNS
PRODUCT DEFINITIONS
27256 VERSIONS
EXTENDED TEMPERATURE
(EXPRESS) EPROMs
Operating
Temperature
O·Cto +70·C
- 40·C to + 85·C
- 40·C to + 85·C
Type
Q
T
L
Packaging Options
Speed
Cerdip
Versions
-20
Q,T,L
Burn-In
125·C (hr)
168 +8
None
168 +8
READ OPERATION
D.C. CHARACTERISTICS
Electrical parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for·
Symbol
ISB
leel 1)
Parameter
Vee Standby Current (rnA)
Vee Active Current (mA)
TD27256
LD27256
Min
Max
50
125
Test Conditions
CE = VIH,OE = VIL
OE = CE = VIL
NOTE:
1. The maximum current value is with outputs 00 to 07 unloaded.
30 Jo'S
H
AOfiJ1.I
A1ILJ
.
•
.
AU
Binary Sequence from Ao !o A14
OE ~ +5V
Vpp ~ +5V
290097-9
R ~ 1 kG
Vr::&..~ +5V
Vss ~ GND
CE ~ GNp
Burn·ln Bias and Timing Diagrams
5-40
290097-10
27256
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temperature
During Read .................... O°C to + 70°C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Temperature Under Bias ......... -10°C to + BO°C
Storage Temperature .......... -65°C to + 125°C
All Input or Output Voltages with
Respect to Ground ........... - 0.6V to + 6.25V
Voltage on Pin 24 with
Respect to Ground ........... - 0.6V to + 13.5V
Vpp Supply Voltage with Respect
to Ground ................... - 0.6V to + 14.0V
Vee Supply Voltage with
Respect to Ground ............ -0.6V to + 7.0V
READ OPERATION
D.C. CHARACTERISTICS
Symbol
Parameter
O°C ::;: TA ::;: + 70°C
27256·1,27256·2,
27256·20, P27256-2
Limits
Min
Typ(3)
Max
27256·25, 27256,
P27256-25,P27256
Limits
Min
Typ (3)
Test
Conditions
Unit
Max
III
Input Load Current
10
10
p.A VIN = OV to Vee
ILO
Output Leakage
Current
10
10
p.A VOUT
IpPl(2)
VppCurrent
Read/Standby
5
5
mA Vpp
IS8(2)
Vee Current Standby
25
50
20
40
mA CE = VIH
leel(2)
Vee Current Active
55
125
45
100
mA CE = OE = VIL
Vpp = Vee
VII':.
Input Low Voltage
-0.1
+0.8
-0.1
+O.B
V
VIH
Input High Voltage
2.0
Vee + 1
2.0
Vee + 1
V
VOL
Output Low Voltage
0.45
V
VOH
Output High Voltage
2.4
Vpp(2)
Vpp Read Voltage
3.B
0.45
2.4
Vee
5-41
3.8
Vee
=
=
OV to Vee
5.5V
IOL = 2.1 mA
V
IOH = -400p.A
V
Vee = 5.0V±0.25V
inter
27256
READ OPERATION
A.C. CHARACTERISTICS
O°C
VCC±5%
s:
TA
s: + 70°C
27256-1
Versions(5)
Vcc±10%
Symbol
Parameter
Min
Max
27256-2
P27256-2
27256
P27256
27256-20
27256-25
P27256-25
Min
Max
Min
Test
Conditions
Unit
Max
tACC
Address to Output
Delay
170
200
250
ns
CE
=
OE
tCE
CE to Output Delay
170
200
250
ns
OE
tOE
OE to Output Delay
70
75
100
ns
CE
VIL
tOF(4)
OE High to Output
Float
0
60
ns
CE
=
=
=
tOH(4)
Output Hold from
Address, CE or OE
Whichever
Occurred First
0
35
0
55
0
0
0
=
VIL
VIL
VIL
ns
NOTES:
1. VCC must be applied simultaneously or before Vpp and removed Simultaneously or after Vpp.
2. Vpp may be. connected directly to Vee except during programming. The supply current would then be the sum of ICC and
Ipp. The maximum current value is with outputs 00 to 07 unloaded.
3. Typical values are for TA = 25°C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested. Output Data Float is defined as the point where. data is no longer
driven-see timing diagram.
5. Packaging Options: No prefix = Cerdip; P = Plastic DIP.
CAPACITANCE(2) (TA =
25°C, f
=
1 MHz)
Typ(l)
Max
Unit
CIN
Input Capacitance
4
6
pF
VIN
COUT
Output Capacitance
8
12
pF
VOUT
Symbol
Parameter
Conditions
=
OV
=
OV
NOTES:
1. TA = 25°C, Vcc
= S.OV.
2. This parameter is only sampled and is not 100% tested.
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
1.3V
~N."
3.3KII
DEVICE
UNDER
TEST
290097-3
I---+---QOUT
I
Cl
:::
100 pi
290097-4
A.c. Testing; Inputs are Driven at 2.4V for a Logic "1" and 0.4SV
for a Logic "0". Timing Measurements are made at 2.0V for a
Logic "1" and O.BV for a Logic "0".
CL = 100 pF
CL Includes Jig Capacitance
5-42
inter
27256
A.C. WAVEFORMS
VIH - - - - - - - - . .
• •••
·...
ADDRESS
VALID
ADDRESSES
VIL------~
VIH
--------+_
CE
• •••
VIL
VIH
--------+---"""
OE
i'----f- ••••
VIL
1"7"""',.-,10- • • • • --oI-r......l
----++-t+<
OUTPUT _ _ _ _ _.....;H~I;:;;GH.;..;;.Z
HIGH Z
~~~-
••••
--~.4f
290097-5
NOTES;
1. Typical values are for T A = 25'C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. DE may be delayed up to teE-tOE after the falling edge of CE without impact on teE.
Table 1. Operating Modes
Pins CE OE
Ag
Ao
DEVICE OPERATION
Vpp Vcc
The modes of operation of the 27256 are listed in
Table 1. A single 5V power supply is required in the
read mode. All inputs are TTL levels except for Vpp
and 12V on A9 for inteligent identifier mode.
Outputs
Mode
Read
VIL VIL X(1)
Output Disable
VIL VIH
X
X Vee 5.0V HighZ
Standby
VIH X
X
X Vee 5.0V HighZ
Programming
VIL VIH
X
X
(4)
(4)
DIN
Program Verify
VIH VIL· X
X
(4)
(4)
Dour
Optional Program
Verify
VIL VIL
X
X Vee (4)
Dour
Program Inhibit
VIH VIH
X
X
HighZ
X Vee 5.0V
(4)
(4)
Dour
Read Mode
The P27256 has two control functions, both of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to
gate data from the output pins, independent of device selection. Assuming that addresses are stable,
the address access time (tACe) is equal to the delay
from CE to output (tCE). Data is available at the outputs after a de~ of tOE from the falling edge of OE,
assuming that CE has been low and addresses have
been stable for at least tACC-tOE.
a9H(5)
inteligent Identifier(3)
-manufacturer
VIL VIL VH(2) VIL 5.0V 5.0V aaH(S)
-device
VIL VIL VH(2) VIH 5.0V 5.0V
04H
NOTES;
1. X can be VIH or VIL.
2. VH = 12.0V±0.5V.
3. A1-Ae. A10-A13 = VIL. A14 = VIH·
4. See Table 2 for Vee and Vpp voltages.
5. The manufacturers identifier reads a9H for Cerdip
EPROMs; aaH for Plastic EPROMs.
Standby Mode
EPROMs can be placed in a standby mode which
reduces the maximum current of the devices by applying a TTL-high signal to the CE input. When in
standby mode, the outputs are in a high impedance
state, independent of the OE input.
5-43
27256
Two Line Output Control
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 control lines which
accommodate this multiple memory connection. The
two control lines allow for:
The device is in the programming mode'when Vpp is
raised to its programming voltage (see Table 2) and
CE is at TIL-low. The data to be programmed is
applied 8 bits in parallel to the data output pins. The
levels required for the address and data inputs are
TIL.
a) the lowest possible memory power dissipation,
and
Program Inhibit
b) complete assurance that output bus contention
will not occur.
Programming of multiple EPROMs in parallel with
different data is easily accomplished by using the
Program Inhibit mode. A high-level CE input inhibits
the other devices from being programmed.
To use these two control lines most efficiently, CE
should be decoded and used as the primary device
selecting function, while OE should be made a common connection to all devices in the array and connected to the READ line from the system control
bus. This assures that all deselected memory devices are in their low power standby mode and that the
output pins are active only when data is desired from
a particular memory device.
Except for CE, all like inputs of the parallel EPROMs
may be common. A TIL low-level pulse applied to
the CE input with Vpp at its programming voltage will
program the selected device.
Program Verify
SYSTEM CONSIDERATIONS
A verify should be performed on the programmed
bits to determine that they have been correctly programmed. The verify is performed with OE at VIL, CE
at VIH, and Vpp and Vee at their programming voltages.
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed
by complying with Intel's Two-Line Control and by
properly selected decoupling capacitors. It is recommended that a 0.1 /LF ceramic capacitor be used on
every device between Vee and GND. This should be
a high frequency capacitor of low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 /LF bulk electrolytic
capacitor should be used between Vee and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effects of PC board traces.
Optional Program Verify
The optional verify may be performed in place of the
verify mode. It is performed with OE at VIL, CE at VIL
(as opposed to the standard verify which has CE at
VIH), and Vpp at its programming voltage. The outputs will tri-state according to the signal presented
to OE. Therefore, all devices with '{eE. = 12.75V
(12.5V inteligent programming) and OE = VIL will
present data on the bus independent of the CE
state. When parallel programming several devices
which share a common bus, Vpp should be lowered
to Vee (= 6.25/6.0V-see Table 2) and the normal
read mode used to execute a program verify.
inteligent IdentifierTM Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the device.
PROGRAMMING MODES
Caution: Exceeding 14V on Vpp will permanently
damage the device.
Initially, and after each erasure, all bits of the
EPROM are in the "1" state. Data is introduced by
selectively programming "as" into the desired bit locations. Although only "as" will be programmed,
both "1 s" and "as" can be present in the data word.
The only way to change a "a" to a "1 "is by ultraviolet light exposure (Cerdip EPROMs).
5-44
inter
27256
To activiate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO from VIL to VIH. All other address lines
must be held at VIL during inteligent Identifier Mode.
sure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the EPROM is to be
exposed to these types of lighting conditions for extended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.
Byte 0 (AO = Vld represents the manufacturer code
and byte 1 (AO = VIH) the device identifier code.
These two identifier bytes are given in Table 1.
The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 }LW/cm2 power rating. The EPROM should be placed within 1 inch of
the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000
}LW/cm2). Exposure of the device to high intensity
UV light for long periods may cause permanent damage.
ERASURE CHARACTERISTICS (FOR
CERDIP EPROMs)
The erasure characteristics are such that erasure
begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant expo-
5-45
intJ
27256
290097-6
Figure 3. Quick-Pulse Programming™ Algorithm
been successfully programmed. Up to 25 100 IJ.s
pulses per byte are provided before a failure is recognized. A flowchart of the Quick-Pulse Programming Algorithm is shown in Figure 3.
Quick·Pulse Programming™ Algorithm
(For Plastic EPRONis)
Intel's Plastic EPROMs can now be programmed using the Quick-Pulse Programming Algorithm, developed by Intel to substantially reduce the throughput
time in the production programming environment.
This algorithm allows Plastic devices to be programmed in under four seconds, almost a hundred
fold improvement over previous algorithms. Actual
programming time is a function of the PROM pro, grammer being used.
For the Quick-Pulse Programming Algorithm, the entire sequence of programming pulses and byte verifications is performed at Vee = 6.25V and Vpp at
12.75V. When programming of the EPROM has
been completed, all bytes should be compared to
the original data with Vee = Vpp = 5.0V.
In addition to the Quick-Pulse Programming Algorithm, Plastic EPROMs are also compatible with Intel's inteligent Programming Algorithm.
The Quick-Pulse Programming Algorithm uses initial
pulses of 100 microseconds followed by a byte verification to determine when the address byte has
5-46
inter
27256
DEVICE
FAILEO
DEVICE
FAILED
290097-8
Figure 4. inteligent Programming™ Flowchart
pulse of length 3X msec. X is an iteration counter
and is equal to the number of the initial one millisecond pulses applied to a particular location, before a
correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram
pulse is applied.
inteligent Programming™ Algorithm
The inteligent Programming Algorithm has been a
standard in the industry for the past few years. A
flowchart of the inteligent Programming Algorithm is
shown in Figure 4.
The inteligent
different pulse
duration of the
which will then
The entire sequence of program pulses and byte
verifications is performed at Vee = 6.0V and
Vpp = 12.SV. When the inteligent Programming cycle has been completed, all bytes should be compared to the original data with Vee = Vpp = 5.0V.
Programming Algorithm utilizes two
types: initial and overprogram. The
initial CE pulse(s) is one millisecond,
be followed by a longer overprogram
5-47
27256
TABLE 2. D.C. PROGRAMMING CHARACTERISTICS
Symbol
Parameter
III
Input ClIrrent (All Inputs)
VIL
Input Low Level (All Inputs)
=
TA
25 ±5°C
Limits
Min
Max
Unit
10
-0.1
0.8
/LA
V
2.0
Vee
0.45
VIN
=
V
10L
V
10H
= 2.1 mA
= -400,...A
CE
=
VIL
=
=
VIL
VIH
Input High Level
VOL
Output Low Voltage During Verify
VOH
lee2(4)
Output High Voltage During Verify
Vee Supply Current (Program & Verify)
125
mA
IpP2(4)
Vpp Supply Current (Program)
50
mA
VID
Vpp
Aginteligent Identifier Voltage
11.5
12.5
V
Vee
Test Conditions
(see Note 1)
VIL or VIH
V
2.4
in\aligent Programming Algorithm
12.0
13.0
V
CE
Quick-Pulse Programming Algorithm
12.5
13.0
V
CE
in\aligent Programming Algorithm
5.75
6.25
V
Quick-Pulse Programming Algorithm
6.0
6.5
V
VIL
A.C. PROGRAMMING CHARACTERISTICS
TA = 25 ± 5°C (see table 2 for Vee and Vpp voltages)
Symbol
Limits
Parameter
Min
Typ
Max
Unit
tAS
Address Setup Time
2
/Ls
toES
tDS
OE Setup Time
2
/Ls
Data Setup Time
2
,...S
tAH
Address Hold Time
0
/Ls
tDH
Data Hold Time
2
tDFP
OE High to Output
Data Float Delay
0
tvps
Vpp Setup Time
2
tves
Vee Setup Time
2
tpw
CE Initial Program Pulse Width
topw
CE Overprogram Pulse Width
toE
Data Valid from OE
Test Conditions'
(Note 1)
/Ls
130
(Note 3)
/Ls
,
0.95
1.0
1.05
95
100
105
2.85
/Ls
/Ls
ms
78.75
/Ls
ms
150
ns
inteligent Programming
Quick-Pulse Programming
(Note 2)
NOTES:
• A.C. CONDITIONS OF TEST
1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp.
2. The length of the overprogram pulse may vary from
2.85 msec to 78.75 msec as a function of the iteration
counter value X (inteligent Programming Algorithm only).
3. This parameter is only sampled and is not 100% tested.
Output Data Float is defined as the point where data is no
longer driven-see timing diagram on the following page.
4. The maximum current value is with outputs 00 to 07 unloaded.
Input Rise and Fall Times
(10% to 90%) ............................. 20 ns
Input Pulse Levels .................. O.45V to 2.4V
Input Timing Reference Level.: .•... O.8Vand 2.0V
Output Timing Reference Level ...... O.8V and 2.0V
5-48
intJ
27256
PROGRAMMING WAVEFORMS
!-------IPROGRAM------.;..e----- P~~~:~M-----I
ADDRESSES
HIGHZ
DATA
12.75V/12.5V(4)
V"
8.25VILOVC4j
Vee
S.Oy
V"
CE
V"
tOES
to.
V,"
CE
V"
290097-7
NOTES:
1. The input timing reference level is 0.8V for a VIL and 2V for a VIH.
2. toE and tDFP are characteristics of the device but must be accommodated by the programmer.
3. When programming the 27256 a 0.1 p.F capacitor is required across Vpp and ground to suppress spurious voltage tranI
sients which can damage the device.
4. 12.75V Vpp & 6.25V Vee for Quick-Pulse Programming Algorithm. 12.5V Vpp & 6.0V Vee for inleligent Programming
Algorithm.
REVISION HISTORY
Number
Description
04
Revised Pin Configuration. Revised Express options.
Deleted -3, -30, -5, L-2, L-20 and L-1 speed bins.
D.C. Characteristics -Ill Conditions are VIN = OV to VeeD.C. Characteristics -ILO Conditions are VOUT = OV to Vee.
5-49
27C256
256K (32K x 8) CHMOS EPROM
• High Speed
- 120 ns Access Time
• EPI Processing
- Maximum Latch-up Immunity
• Low Power Consumption
-100 p,A Standby, 30 mA Active
• Simple Interfacing
- Two Line Control
- CMOS and TTL Compatible
• Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as 4
Seconds
• Versatile JEDEC-Approved Packaging
,
- Standard 28-Pin CERDIP
- Compact 32-Lead PLCC
- Cost Effective Plastic DIP
(See Packaging Spec.,
Or~er
#231369)
Intel's 27C256 is a 5V only, 262,144-bit Erasable Programmable Read Only Memory, organized as 32,768
words of 8 bits. Its standard pinouts provide for simple upgrades to 512 Kbits in the future in both DIP and
SMT.
The 27C256 is ideal in embedded control applications based on advanced 16-bit CPUs. Fast 120 ns access
times allow no-wait-state operation with the 12 MHz 80286. The 27C256 also excels in reprogrammable
environments where the system designer must strike an optimal density/performance balance. For example,
bootstrap and diagnostic routines run 1-wait-state on a 16 MHz 386™ microprocessor.
Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic dip
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic dip (PDIP) one-time programmable part provides a lower cost alternative
that is well adapted for auto insertion.
In addition to the JEDEC 28-pin DIP package, Intel also offers a 32-lead PLCC version of the 27C256. This
one-tirne-programmable surface mount device is ideal where board space consumption is a major concern or
where surface mount manufacturing technology is being implemented across an entire production line.
The 27C256 is equally at home in both TTL and CMOS environments. The Quick-Pulse programming™
algorithm improves speed as much as 100 times over older methods, further reducing cost for system manufacturers.
DATA OUTPUTS
vcc-
0 0-0,
GND_
vpp_
Y-GATING
AcrAl. {
ADDRESS
INPUTS
212,144 BIT
CELLMATAIX
290044-1
Figure 1. Block Diagram
5-50
September 1990
Order Number: 290044-010
27C256
Pin Names
AO-:"A15
ADDRESSES
00- 0 7
OUTPUTS
OE
OUTPUT ENABLE
CE
PGM
CHIP ENABLE
PROGRAM
NC
NO CONNECT
DU
DON'T USE
27512
27128A
2764A
27C512
27C128
27C64
A1s
Vpp
Vpp
vpp
vcc
A12
A12
A12
A12
A7
A7
A7
A7
A7
A7
A14
A13
Vee
A6
A6
A6
A6
A6
A6
As
As
As
As
As
As
As
A9
A4
A4
A4
~
~
A4
All
Aa
Aa
Aa
Aa
A3
A3
DE
A2
A2
A2
A2
A2
A2
A10
AI
AI
AI
AI
AI
AI
2732A
27C256
2716
2716
cr
Ao
Ao
Ao
Ao
Ao
AO
°7
00
00
00
00
00
°0
°6
01
01
01
01
01
°1
°5
02
02
02
02
02
°2
GND
GND
GND
GND
GND
°4
03
GND
2732A
27C64 27128A
27512
27C64 27C128
27C512
Vee
Vee
Vee
PGM
PGM
A14
Vee
NC
Ala
Ala
As
As
As
As
As
A9
A9
A9
A9
A9
Vpp
A11
A11
A11
All
OE
OElVpp
OE
OE
OElVpp
Al0
AIO
AIO
Al0
Al0
Cl:
CE
CE
CE
Cl:
07
07
07
D7
07
Os
Os
Os
Os
Os
Os
Os
Os
Os
Os
04
04
04
04
04
Oa
Oa
03
Oa
03
290044-2
Figure 2. DIP Pin Configuration
27C64
o
32 LEAD PLCC
0.4S0" X 0.550"
(11.430 X 13.970)
(MILLIMETERS)
TOP VIEW
290044-10
Figure 3. PLCC Lead Configuration
5-51
27C256
EXTENDED TEMPERAtURE
(EXPRESS) EPROMs
EXPRESS EPROM FAMILY
PRODUCT DEFINITIONS
The . Intel. EXPRESS EPROM family receives addi·
tional .processing to enhance product characteristics. EXPRESS processing is available for several
densities allowing the appropriate memory size to
match system requirements. EXPRESS EPROMs
are available with 168 ±8 hour, 125·C. dynamic
burn-in using Intel's standard bias configuration.
This processing meets or exceeds most industry
burn-in specifications. The EXPRESS product .family
is available in both O·C to 70·C and - 40·C to 85·C
operating temperature range versions. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0: 1% electrical AQL. This allows reduction or
elimination of incoming testing.
Operating
Temperature ("C)
Burn-In 12S·C (hr)
Q
O·Cto 70·C
168 ±8
T
- 40·C to 85·C
NONE
L
- 40·C to 85·C
168 ±8
Type
Options
Packaging
Speed
CERDIP
PLCC
PDIP
-120V10
Q,T,L
T
T
-200V10
Q,T,L
T
290044-12
R=lKO.Vcc=+5V
Vpp = +5V GND = OV CE = GND
~=+5V
Binary Sequence from Ao to A14
290044-13
Burn-In Bias and Timing Diagrams
5-52
intJ
27C256
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temperature ............. O·C to 70·C(1)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Temperature Under Bias .......•... -1 O·C to BO·C
Storage Temperature ............. -65·C to 125·C
Voltage on Ar)Y Pin (except Ag, Vee and Vpp)
with Respect to GND ......•....• ; - 2V to 7V(2)
Voltage on Ag with
Respect to GND ....•.......... -2V to 13.5V(2)
Vpp Supply Voltage
with Respect to GND ........... - 2V to 14.0V(2)
Vee Supply Voltage with
Respectto GND ................ -2V to 7.0V(2)
READ OPERATION DC CHARACTERISTICS(1)
Symbol
Parameter
III
Input Load Current
ILO
Output Leakage Current
ISB
Vee Standby Current
Notes
Min
7
Vee = 5.0V ±10%
Typ
Max
Unit
Test Condition
0.01
1.0
J.l.A
VIN = OVtoVee
±10
J.l.A
VOUT = OV to Vee
1.0
mA
CE = VIH
100
J.l.A
CE = Vee ±0.2V
lee
Vee Operating Current
3
30
mA
CE = VIL
f = 5 MHz
Ipp
Vpp Operating Current
3
200
p.A
Vpp = Vee
los
Output Short Circuit Current
100
mA
VIL
Input Low Voltage
-0.5
O.B
V
VIH
Input High Voltage
2.0'
VOL
Output Low Voltage
VOH
Output High Voltage
Vpp
Vpp Operating Voltage
4,6
Vee
+ 0.5
0.45
5
V
V
IOL =2.1 mA
2.4
V
IOH= -400 J.l.A
Vee - 0.7
V
NOTES:
1. Operating temperature is for commercial product defined
by this specification. Extended temperature options are
available in EXPRESS versions.
2. Minimum De voltage is -O.SV on input/output pins. During transitions, this level may undershoot to - 2.OV for periods <20 ns. Maximum DC voltage on input/output pins is
Vee + O.SV which, during transitions, may overshoot to
Vee + 2.OV for periods <20 ns.
3. Maximum active power usage is the sum Ipp + Icc.
Maximum current value is with outputs 00 to 07 unloaded.
Vee
4. Output shorted for no more than one second. No more
than one output shorted at a time.
s. Vpp may be connected directly to Vee, or may be one
diode voltage drop below Vee. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
6. Sampled, not 100% tested.
7. Typical limits are at Vee = SV, TA = 2SoC.
5-53
intJ
27C25S·
READ OPERATION AC CHARACTERISTICS(1) vcc
Vee ±10%
Versions(4)
Symbol
Parameter
tACC
Address to Output Delay
teE
CE to Output Delay
toE
Notes
27C256-120V10
P27C256-120V10
N27C256-120V10
Min
Max
=
5.0V ± 10%
27C256-150V10
P27C256-150V10
N27C256-150V10
. Min
Max
27C256-200V10
P27C256-200V10
N27C256-200V10 Unit
Min
Max
120
150
200
ns
2
120
150
200
ns
OE to Output Delay
2
55
60
75
ns
tOF
OE High to Output High Z
3
30
50
55
tOH
Output Hold from Addresses, CE or
OE Change-Whichever is First
3
0
0
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to tCE-toE after the falling edge of CE without impact on tCE'
3. Sampled, not 100% tested.
4. Package Prefixes: No Prefix = CERDIP; N = PLCC; P = PDIP.
5-54
0
ns
ns
27C256
AC WAVEFORMS
V,H-----...,.
ADDRESS
VALID
ADDRESSES
V,, _ _ _ _ __
V,H
---------l-""
V,H
---------l----...,.
V,l
'D_
V,H
O~ftITS
HIGH Z
_ _ _ _ _ _H~I~GH~Z~_ _ _ _ _~~~~~
V,l
290044-5
CAPACITANCE(1)TA
Symbol
= 25°C,
f = 1.0 MHz
Parameter
Max
Units
CIN
Address/Control Capacitance
Ii
pF
COUT
Output Capacitance
12
, pF
Conditions
VIN
= OV
VOUT
= OV
NOTE:
1. Sampled, not 100% tested.
AC INPUT/OUTPUT REFERENCE WAVEFORM
AC TESTING LOAD CIRCUIT
1.3V
-~
2.4
0.45
2.0>
0.8
____
TEST POINTS _____
2.0
~~ 1N914
OUTPUT
,0;;:;.8=--_ _
290044-9
DEVICE
AC test inputs are driven at VOH (2.4 VTTI) for a logic "1" and
VOL (0.45 VTTU for a logic "0". Input timing begins at VIH (2.0
VTTU and VIL (O.B VTTU. Output timing ends at VIH and VIL. Input
rise and fall times (10% to 90%) :>:10 ns.
UNDER
TEST
t--+--oOUT
CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 KI1
5-55
290044-3
inter
27C256
DEVICE OPERATION
The Mode Selection table lists 27C256 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, and Ag 'during inteligent Identifier Mode, are TIL or CMOS.
Table 1. Mode Selection
Notes
CE
OE
Ag
Ao
Vpp
Vee
Outputs
1
VIL
VIL
X
X
Vee
Vcc
DOUT
Output Disable
VIL
VIH
X
X
Vcc
Vcc
HighZ
Standby
VIH
X
X
X
Vcc
Vcc
HighZ
Mode
Read
VIL
VIH
X
X
Vpp
Vcp
DIN
Program Verify
VIH
VIL
X
X
Vpp
VCP
DOUT
Program Inhibit
VIH
VIH
X
X
Vpp
Vcp
HIGHZ
Program
2
inteligent Identifier
-Manufacturer
2,3
VIL
VIL
VIO
VIL
Vcc
Vcc
89H
inteligent Identifier
-Device
2,3,4
VIL
VIL
VIO
VIH
Vcc
Vcc
8DH
NOTES:
1. X can be VIL or VIH.
2. See OC Programming Characteristics for VCP, Vpp and VIO voltages.
3. Al-Aa, Al0-14 = VIL·
4. Programming equipment may also refer to this device as the 27C256A. Older devices may have device 10 = eCHo
Read Mode
The 27C256 has two control functions, both must be
. enabed to obtain data at the ~uts. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (teE). Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.
'
To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.
Standby Mode
StandbLMode substantially reduces Vcc current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.
Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.
Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power diSSipation
b) complete assurance that data bus contention will
not occur
5-56
intJ
27C256
allows upgrade using the Vpp pin. Systems designed
for 256 Kbit program memories today can be upgraded to 512 Kbit in the future with no circuit board
changes.
Program Mode
Initially, an.d after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "O's" into the desired bit locations. Although only "O's" are programmed, the data word
can contain both "1's" and "O's". Ultraviolet light
erasure is the only way to change "O's" to "1's".
SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (ISB), active current levels (Icc>, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-Line Control and proper decoupling capacitor
selection will suppress trarisient voltage peaks.
Each device should have a 0,·1 ,...F ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,...F electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.
Program Mode is entered when Vpp is raised to
12.75V. Data is introduced ~applying an 8-bit word
to the output pins. Pulsing CE low while OE = VIH
programs that data into the device.
Program Verify
A vertfy should be performed following a prcigrar:n
operation to determine that bits have been correctly
programmed. With Vee at 6.25V a substantial pro~m margin is ensured. The verify is performed with
CE at VIH. Valid data is available tOE after OE falls
low.
Program Inhibit
Program Inhibit Mode allows parallel prQg!"amming
of multiple EPROMs with different data. CE-high inhibi!!Progr!!!!ming of non-targeted devices. Except
for CE and OE, parallel EPROMs may have common
inputs.
ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter .than approximately 4000
Angstroms (A). It should be rioted that sunlight and
certain flourescent lamps have wavelengths in the
3000A-4000A range, Data shows that constant exposure to room level. fluprescent lighting can erase
an EPROM in approximately 3 years, while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
lritaligent Identifler™ Mode
The. inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programrriing algorithm.
This mode is activated when ~rogrammer forces
12V + 0.5V on Ag. With CE; DE, A1-Aa, and A10A14 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± SoC ambient temperature
range required during programming.
UPGRADE PATH
Future upgrade to the 512 Kbit density is easily accomplished due to the standardized pin configuration of the 27C256. A jumper between A15 and Vee
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity exposure time) for erasure should be a minimum of 15 Wsec/cm 2 . Erasure
time is approximately 1S to 20 minutes using an ultraviolet lamp with a ~2000 ,...W/cm2 power rating.
The EPROM should be piaced within 1 inch of the
lamp tubes. An EPROM can be permanently
damaged if the integrated dose exceeds
. 7258 Wsec/cm2 (1 week @ 12000 ,...W/cm2 ).
x
5-57
inter
27C256
,290044-:11
Figure 4.,Quick-Pulse Programmlng™ Algorithm
The Quick-Pulse programniing algorithm employs a
100 p.s pulse followed by a byte verification to determine when the addressed byte has been sucessfully
programmed. The algorithm terminates if 25 attempts fail to program a byte.
Quick-Pulse Programming™
Algo,rithm
',
The Quick-Pulse Programming' algorithm programs
Intel's 27C256. Developed to substantially reduce
programming throughput, this algorith[T1 ca'n program
the 27C256 as fast as 4 seconds. Actual programming time depends on programmer overhead,
'
'The entire program pulse/byte verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all bytes are compared to th,e original data with Vee = Vpp = 5.0V.
5-58
27C256
DC PROGRAMMING CHARACTERISTICS
Symbol
Parameter
TA
Notes
=
25"C ±5°C
Min
III
Input Load Current
Icp
Vcc Program Current
1
Ipp
Vpp Program Current
1
V,L
Input Low Voltage
-0.1
V,H
Input High Voltage
2.4
VOL
Output Low Voltage (Verify)
Typ
Max
Unit
Test Condition
1.0
,...A
Y,N = V,L or V,H
30
rnA
CE = V,L
50
rnA
CE = V,L
0.8
V
6.5
V
0.45
V
IOL = 2.1 rnA
V
IOH = -2.5 rnA
VOH
Output High Voltage (Verify)
3.5
11.5
12.0
12.5
2,3
12.5
12.75
13.0
V
2
6.0
6.25
6.5
V
V'O
A9 Inteligent Identifier Voltage
Vpp
Vpp Program Voltage
Vcp
Vcc Supply Voltage (Program)
AC PROGRAMMING CHARACTERISTICS(4)
Symbol
Parameter
V
TA = 25°C ±5°C
Notes
Min
tvcs
Vcp Setup Time
2
2
Typ
,...s
tvps
Vpp Setup Time
2
2
,...s
tAS
Address Setup Time
2
,...s
Max
Unit
tDS
Data Setup Time
2
tpw
CE Program Pulse Width
95
tOH
Data Hold Time
2
,...s
tOES
OE Setup Time
2
,...s
toE
Data Valid from OE
tOFP
OE High to
Output High Z
tAH
Address Hold Time
5
5,6
0
0
,...s
100
105
,...s
150
ns
130
ns
,...s
4. See AC Input/Output Reference Waveform for timing
measurmenlS.
5. tOE and tOFP are device characteristics but must be accommodated by the programmer.
6. Sampled,. ~.ot 100% tested.
NOTES:
1. Maximum current value"is with outputs 00 to 07 unloaded.
2. Vep must be applied simu'itaneously or before Vpp and
removed simultaneously or after Vpp.
3. When programming, a 0.1 ,.,.F capacitor is required
across Vpp and GNO to suppress spurious voltage transients which can damage the device.
5-59
r-------------------------------------------------------------------------------,I~
~
o
~
~
~
~
.~
Inlellgent Identilier
-ManufactuAr
Blank Check
"'egal Bit Check
'I'
Program
'I'
P
~~m
Z
Read Verify
Q
~
'2.OV
VII
. Add ....
VL
l
x:
Ao=V'L
<
m
~
ADDRESS SlABl£
~
VII
~
o
Data
vI.
t2.75Y
(11
0,
.~
•.av-
Vpp
N
CI'I
0
.Q)
I.25Y
•.avVee
v.,
CE
VL
toE
v.,
.DE
vL
290044-8
inter
27C256
REVISION HISTORY
Number
Description
010
Revised general datasheet structure, text to improve clarity
Revised ISB Test Condition from CE = Vee to CE = Vee ± 0.2V
Revised VOH from 3.5V to 2.4V, IOH from -2.5 mA to -400 p.A
Deleted 512K PLCC pinout references
Deleted -150V10, -2, -20, -STD and -25 EXPRESS offerings
Added -120V1 0, - 200V1 0, PLCC and PDIP EXPRESS offerings
Deleted -20, -25 and all 5% Vee speed bins
Added PLCC and PDI P -120 speed bin packages
5-61
27C512
512K (64K x 8) CHMOS EPROM,
• Low Power
- 30 mA Max. Active
"";"100 p.A Max. Standby
• Software Carrier Capability
•
120 ns Access Time
• Two-Line Control
• Inteligent Identifier™ Mode
- Automated Programming Operations
• CMOS and TTL Compatible
• Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as 8
Seconds
The Intel 27C512 is a 5V-only, 524, 288-bit Erasable Programmable Read Only Memory (EPROM), organized
as 65,536 words of 8 bits. Individual bytes are accessed in 120 ns. This ensures compatibility with high-performance microprocessors, such as the Intel 12 MHz iAPX 286, allowing full speed operation without the
addition of performance-degrading WAIT states. The 27C512 is also directly compatible with Intel's 80C51
family of microcontrollers.
The 27C512 enables implementation of new, advanced systems with firmware intensive architectures. The
combination of the 27C512's high-density, cost-effective EPROM storage, and new advanced microprocessors having megabyte addressing capability provides designers with opportunities to, engineer user-friendly,
high-reliability, high-performance systems.
The 27C512's large storage capability of 64 K-bytes enables it to function as a high-density software carrier.
Entire operating systems, diagnostics, high-level language programs and specialized application software can
'reside in a 27C512 directly on a system's memory bus. This permits immediate microprocessor access and
execution of software and eliminates the need for time-consuming disk accesses and downloads.
Intel's Quick-Pulse Programming™ algorithm enables the 27C512 to be programmed as fast as eight seconds
(plus programmer overhead). Programming equipment which takes advantage of the inteligent IdentifierTM will
electronically identify the EPROM and automatically program it using a superior programming method.
Two-line control and JEDEC-approved, 28-pin packaging are standard features of the 27C512. This assures
easy microprocessor interfacing and minimum design efforts when upgrading, adding, or choosing between
nonvolatile memory alternatives.
CHMOS is a patented process of Intel Corporation.
DATA OUTPUTS
0.-0,
Y.QAnNQ
ADDRESS
ActA" {
524,288-BIT
CELL MATRIX
INPUTS
290228-1
Figure 1. Block Diagram
5-62
October 1990
Order Number: 290228-003
inter
27C512
Pin Names
Ao-A15
CE
OElVpp
PGM
00-0 7
NC
ADDRESSES
CHIP ENABLE
OUTPUT ENABLElVpp
PROGRAM
OUTPUTS
NO CONNECT
27C512
27256 27C12B 2764A
2732A 2716
27C256 2712BA 27C64
Vpp
A12
A7
A6
A5
A4
A3
A2
A1
Ao
00
01
02
GND
Vpp
A12
A7
A6
A5
A4
A3
A2
Al
AO
00
01
02
GND
Vpp
A12
A7
A6
A5
A4
A3
A2
Al
AO
00
01
02
GND
2716 2732A
A15
A12
A7
As
A5
Vee
A1"
A13
As
Ag
A7
A7
A6
A6
A5
A5
A4
A4
A"
A3
A3
A3
A2
A2
A2
Al
Al
Al
AO
Ao
Ao
00
00
°0
01 01
°1
O2 O2
°2
GND GND GND
All
OE/Vpp
A10
CE
°7
Os
°5
0"
°3
290228-2
Figure 2. DIP Pin Configuration
5·63
2764A 27C12B 27256
27C64 27128A 27C256
Vee
PGM
NC
Vee Vee
As
As
A8
Ag
A9
A9
Vpp All
All
OE OE/vpp OE
AlO AlO
Al0
CE
CE
CE
07
07
07
06
06
06
05
05
05
04
04
04
03
03
03
Vee
PGM
A13
As
Ag
All
OE
AlO
CE
07
06
05
04
03
Vee
A14
A13
As
Ag
All
OE
AlO
CE
07
06
05
04
03
27C512
EXTENDED TEMPERATURE
(EXPRESS) EPROMs
EXPRESS EPROM FAMILY
The Intel EXPRESS EPROM family receives additional processing to enhance product characteristics. EXPRESS processing is available for several
densities allowing the appropriate memory size to
match system requirements. EXPRESS EPROMs
are available with 168 ±8 hour, 125"C dynamic
burn-in using Intel's standard bias configuration.
This processing meets or exceeds most industry
burn-in specifications. The EXPRESS product family
is available in both O"C to 70"C and - 40·C to 85·C
operating temperature range versions. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AQL. This allows reduction or
elimination of incoming testing.
PRODUCT DEFINITIONS
Operating
Type
Temperature
O·Cto 70"C
Q
-40"C to 85"C
T
-40·C to 85"C
L
Burn-In
12S"C {hr}
168 ± 8
None
168 ± 8
OPTIONS
Packaging
I
I
Speed
-120V10
CERDIP
Q,T,L
READ OPERATION DC CHARACTERISTICS
Electrical parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for:
Symbol
TD27CS12(2)
LD27CS12
Parameter
Min
Icel 1)
Test Condition
Max
Vcc Operating Current (mA)
50
. OENpp = CE = V,L
Vcc Operating Current
at High Temperature (mA)
50
OENpp = CE = V,L
TAmbient = 85·C
NOTE:
1. The maximum current value is with outputs 00 to 07 unloaded.
2. C refers to the CERCIP package.
30 J.'s
H
A0S-UU·
A1FL-r
•
•
A 15
290228-5
Binary sequence from
OElVpp
GND =
= +5V
R = 1 kO
ov eE = GND
vee =
290228-4
+5V
Burn-In Bias and Timing Diagrams
5-64
A() to A15
27C512
ABSOLUTE MAXIMUM RATINGS·
Operating Temperature .....•..... O·C to
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
+ 70·C(I)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability. .
+ SO·C
+ 125·C
Temperature Under Bias •....•... - 1O~C to
Storage Temperature .......... -65·C to
All Input or Output Voltages
(except A9, Vee and Vpp)
.
with Respect to GND .......... - 2.0V to 7.0V(2)
Voltage on A9 with
Respect to GNP ............. - 2.0V to 13.5V(2)
Vpp Supply Voltage
with Respect to GND ........... - 2.0V to 14V(2)
Vee Supply Voltage
with Respect to GND .......... - 2.0V to 7.0V(2)
READ OPERATION DC CHARACTERISTICS(1)
Symbol
III
Parameter
Input Load Current
Notes
Min
7
Vee = 5.0V ±10%
Typ
Max
Unit
0.01
1.0
,...A
Test Condition
+ 5.5V
OV to + 5.5V
VIN = OV to
ILO
Output Leakage Current
±10
,...A
VOUT =
ISB
Vee Standby Current
1.0
mA
CE =
100
,...A
CE = Vee ±0.2V
lee
Vee Operating Current
3
30
rnA
CE = VIL
f = 5 MHz, lOUT = 0 rnA
Ipp
Vpp Operating Current
3
10
,...A
Vpp.= Vee
los
Output Short Circuit
Current
4,6
100
rnA
VIL
Input Low Voltage
-0.5
O.S
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
Vee
+ 0.5
0.45
VIH
V
V
10L = 2.1 rnA
Output High Voltage
2.4
V
10H = -400,...A
VOH
NOTES:
1. Operating temperature is for commercial product definE!d by this specification. Extended temperature options are available
in EXPRESS versions.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which during transitiops, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. ~aximum active power usage is the sum Ipp + ICC. Maximum current value is with outputs 00 to 07 unloaded.
4. Qutput shorted for no more than onl1 second. No more than one output shorted at a time.
5. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
6. Sampled, not 100% tested.
'
7. Typical limits are at Vee = 5V, TA = 25°C.
5-65
inter
27C512
READ OPERATION AC CHARACTERISTICS Vee = 5.0V ±10%
vee ± 10%
Versions(4)
Symbol
Parameter
27C512-120V10
Notes
Min
tAce
Address to
Output Delay
teE
CE to Output Delay
2
toE
OElVpp
to Output Delay
2
tDF
OElVppHigh
to Output High Z
3
0
tOH
Output Hold from
Addresses, CE or
OElVpp, Whichever
Occurred First
3
0
..
,
Max
27C512-150V10
Min
Max
120
150
120
55
30
27C512-200V1Q
Min
Max
Unit
200
ns
150
200
ns
60
70
ns
60
ns
0
.'
50
0
0
0
ns
NOTES:
1. See AC input/output reference waveform for .timing measurements.
2. DE may be delayed up to tCE-toE after the falling edge of eE without impact on tCE.
3. Sampled, not 100% tested.
4. Packaging Options: No Prefix = CERDIP.
5. Typical values are for T A = 25°e and nominal supply voltages.
CAPACITANCE(3) TA = 25°C, f = 1 MHz
Typ(5)
Max
Unit
Condition
CIN
Input Capacitance
4
8
pF
VIN = OV·
COUT
Output Capacitance
8
12
pF
VOUT = OV
COElVpp
OElVpp Capacitance
18
25
pF
VIN= OV
Symbol
Parameter
AC INPUT/OUTPUT REFERENCE WAVEFORM
AC TESTING LOAD CIRCUIT
2.:3:!,.
2.4
2.0 ' - TEST POINTs . 0.45
0.5-
"
2.00UlPUT
~ .. lN914
~0;:::.5~_
290228-6
RL
DEVICE
UNDER
TEST
NOTE:
AC test inputs are driven at VOH(2.4 VTnJfor a Logic
"1" and VOL (0.45 VnU for a Logic "0". Input timing
begins at VIH (2.0 VnU and VIL (0.8 VnU. Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) s; 10 ns.
OUT
. l CL
CL = 100 pF
CL includes Jig Capacitance
RL;'" 3.3 kO
5-66
--
290228-7
inter
27C512
AC WAVEFORMS
VIH - - - - - - -
ADDRESS
VALID
ADDRESSES
VIL - - - - - - - - '
VIH - - - - - - - - - + _ , .
Cf
VIL
VIH--------+--~
OE/Vpp
VIL
+H+<
OUTPUTS _ _ _ _ _~H::.::IG;.:.H.:.Z_ _ _ _
HIGH Z
290228-8
DEVICE OPERATION
The Mode Selection table lists 27C512 operating
modes. Read Mode requires a single 5V power supply. All inputs, except Vcc and OElVpp, and Ag during inteligent Identifier Mode, are TTL or CMOS.
Table 1. Mode Selection
Mode
Notes
CE
Read
1
VIL
VIL
VIL
VIH
VIH
X
VIL
Vpp
Output Disable
Standby
Program
2
OE/Vpp
Outputs
Ao
Vee
X
X
Vcc
DOUT
X
X
Vcc
HighZ
X
X
Vcc
HighZ
X
X
Vcp
DIN
.Ag
Program Verify
. VIL
VIL
X
X
Vcp
DOUT
Program Inhibit
VIH
Vpp
X
X
VCP
HighZ
VIL
VIL
VID
VIL
Vcc
89H
VIL
VIL
VID
VIH
Vcc
FDH
Inteligent
Identifier
- Manufacturer
-Device.
2,3
NOTES:
1. X can be VIH or VIL.
2. See DC Programming Characteristics for Vep. Vpp and
3. A1-A8. A10-A15 = VIL.
VID
voltages.
5-67
27C512
Read Mode
The 27CS12 has two control functions; both must be
!'lnabled to obtain data at the 0Y!E.uts. CE is the pow,
er .ponteol and device select. OElVpp controls the
P4tput buffers to gate data to t~e outputs. With addresses stable, the address access time (tACe)
~~uals the del~y from CE to output (teE), Outputs
~Isplay valid data toE after OElVpp's falling' edge,
~~~ming tACC and teE times are met.
.
~ m~st
g@m margin is ensured. The verify is performed with
OElVpp at VIL. Valid data is available tov after CE
falls low.
"
Program Inhibit
Program Inhibit Mode ~lIows parallel pr2ll!'amming
of multiple EPROMs with different data. CE-high in~
hibit.!.Programming of non-targeted devices. Except
for CE and OElVpp, parallel EPROMS may have
common inputs.
be applied sImultaneously or before
QE/Vpp and removed simultaneously or after
OE/Vpp.
Stan~by
'.
Mode
StandbLMoqe substantially reduces Vee current.
W/len C~ = VIH, the outputs are in a high i",pedarce state, independent of OElVpp:
'.
.
T!l0 Line Output Control
EF,ROMS are often used in larger memory arrays.
Intel provides two control inputs to accommodate
rlllJltiple memory connections. Two-line control pro"
vidEls for:
~) !ow~st possible memory power dissipation
b) pomplete assurance that data bus contention will
. , not occur
.
To. $fficiently
use these two control inputs, an adqi-ess decoder should enable CE, ~hile OElVpp
snould be connected to all memory qevices and the
sy§tem's READ control line. This assure!l that only
!!elepted memory devices have actiVe outpu1!l while
de~elected memory devices are. in Stardby Mode.
progrljlm Mode
Csl!tlOf1: Exi:esdlng 14.0Von (JE1Vep will Pflrrna-
.",htly damage the device.
!nt~ligent
.
.
Initially, and after each erasure, all EPROM bits are
irr the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. AIthdljgh only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light era~~re'ls the only way to change "OSi;' to "1s".
This mO,de is activated when I!..£fogrammer forces
12V ± O.SV on A9. With CE, OElVpp, A1-AB and
A10-A15 at VIL, Ao = VIL wi'l present the manufacturer code and Ao = VIH the device cpde. This
mode functions in the 2SoC' ± SoC ambient tempera'
ture range reguired during programming.
SYSTEM CONSIDERATIONS
EPROM power switching ,characteristics require
careful device decouj:lling. System designers are interested in 3 supply current issues: standby current
levels (ISB), active' current levels (Ice), and transient
curren!.E.eaks produced by the falling and rising edges of CE. Transient current magnitudes depend on
the device output's capacitive and inductive loading.
Two-line control and proper decoupling capapitor
selection will suppress' transient volta,ge peaks.
, Each device should have a 0.1 ,..,F ceramic capacitor
connected between its Vcc and GND. This high fre~
quency, low inherent-inductance capaCitor 'should
be placed as close as possible to the device. AdditiOnally for every 8 devices, a 4.7 ,..,F electrolytic capacitor should be placed at the array's power supply
connection between Vcc and GND. The bIJlk capacitor will overcome voltage slumps caused by PC
board trace inductances.
ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
wavelengths shorter than approximately 4000
Angstroms (A). It should be noted'that sunlight and
certain fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase an
EPROM in approximately 3 years, while it takes approximately 1 week when exposed to direct sunlight.
If the device is exposed to these lighting conditions
for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
wi~h
P.rogram Mode is entered when OElVpp is raised to
1~t7PV. Data is introduced by~pll{ing an 8 bit word
to t~t3 output "ins. Pulsing CE low programs that
d~ta into the device.
.
Pr~~ram
Verify
A veiify should be performed following a program
9per~fion to determine that bits have been correctly
prQgr~lilmed. With Vce at 6.2SV, a substantial pro"!
,.'
Identifier Mode
The 'inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
.
S-68
27C512
290228-9
Figure 3. Quick-Pulse Programming Algorithm
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537 A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 p.W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsec/
cm 2 (1 week @ 12000 p.W/cm2).
programming throughput, this algorithm can program
the 27C512 as fast as "8 seconds. Actual programming time depends on the programmer overhead.
The Quick-Pulse Programming algorithm employs a
100 p.s pulse followed by a byte verification to determine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.
The entire program pulse/byte verify sequence is
performed with Vee = 6.25V. OElVpp toggles between 12.75V and VIL for program and verify operations. When programming is complete, all bytes are
compared to the original data with Vee = 5.0V.
Quick-Pulse Programming Algorithm
The Quick-Pulse Programming algorithm programs
Intel's 27C512. Developed to substantially reduce
5·69
27C512
DC PROGRAMMING CHARACTERISTICS
Symbol
Parameter
III
Input Load Current
Notes
± 5°C
T A = 25
Min
Typ
Max
Unit
1
p.A
VIN = VIL or VIH
Test Condition
ICp
V CC Program Current
1
40
mA
CE= VIL,OElVpp = Vpp
Ipp
Vpp Program Current
1
50
mA
CE = VIL,OElVpp = Vpp
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.4
6.5
V
VOL
Output Low Voltage (Verify)
0.45
V
IOL = 2.1 mA
VOH
Output High Voltage (Verify)
3.5
V
IOH = -2.5mA
11.5
12.0
12.5
V
2,3
12.5
12.75
13.0
V
2
6.0
6.25
6.5
V
VIO
Ag inteligent Identifier Voltage
Vpp
Vpp Program Voltage
Vcp
Vcc Supply Voltage (Program)
AC PROGRAMMING CHARACTERISTICS(4) T A =
Symbol
Parameter
25
± 5°C
Notes
Min
2
2
P.s
OElVpp Pulse Rise Time
During Programming
50
ns
tvcs
Vcp Setup Time
tpRT
Typ
Max
Unit
tAS
Address Setup Time
2
p.s
tos
Data Setup Time
2
P.s
tOES
OElVpp Setup Time
tpw
CE Program
Pulse Width
95
tOH
Data Hold Time
2
fJ-s
tOEH
OElVpp Hold Time
2
fJ-s
tVR
OElVpp Recovery Time
2
tov
Data Valid from CE
tOFP
Output Disable to Output High Z
tAH
Address Hold Time
2,3
2
5
5,6
0
0
p.s
100
105
p.s
fJ-s
1
fJ-s
130
ns
fJ-s
NOTES:
1. Maximum current value is with outputs 00 to 07 unloaded.
2. VCP must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
3. When programming, a 0.1 ).tF capacitor is required across OElVpp and GNO to suppress spWious voltage transients
which can damage the device.
4. See AC Input/Output Reference Waveforms for timing measurements.
5. tDV and tDFP are device characteristics but must be accommodated by the programmer.
6. Sampled, not 100% tested.
5-70
inter
27C512
PROGRAMMING WAVEFORMS
~----PROGRAM---__~~r'~-
VIH
ADDRESSES
ADDRESS STABLE
VIL
VIH
DATA
VIL
6.25V
Vee
S.OV
12.15V
OElVpp
VIL
IpAT
VIH
CE
VIL
290228-10
REVISION HISTORY
Description
Deleted preliminary classification.
5-71
27513
PAGE-ADDRESSED 512K (4 x 16K x 8)
UV ERASABLE PROM
•
Paged Organization
- Reduced Physical Address
Requirement
- No Bank Switching Logic Needed
•
Software Carrier Capacity
•
Automatic Page Clear
- Resets to Page 0 on Power Up and
On Demand with RST Signal(1)
•
TTL and CMOS Compatible
•
170 ns Access Time
•
Two Line Control
•
Low Power
-125 mA max. Active
- 40 mA max. Standby
•
Compatible with Industry Standard
EPROM Pinouts
- Direct 27128A Compatibility
- 28-Pin Cerdip
The Intel 27513 is a 5V-only, 524,288-bit ultraviolet Erasable and Electrically Programmable Read Only Memory. It is organized as 4 pages of 16K 8-bit words. The 27513's paged organization brings 64 K-byte storage
capacity to existing 128K EPROM-based designs arid to popular 8-bit microprocessor or microcontroller systems that have 64 K-byte total addressing capability. The 27513 provides an ideal means of quadrupling
current 16 K-byte code space.
The 27513's large storage capability of 64 K-bytes and 170 ns access time enables it to function as a high
density software carrier. Entire operating systems, diagnostics, high-level language programs and specialized
application software can reside in a 27513 EPROM directly on a system's memory bus. This permits immediate microprocessor access and execution of software and eliminates the need for time-consuming disk accesses and downloads.
The 27513 has an automatic page clear circuit for ease of use of the page-addressed organization. The pageselect latch is automatically cleared to the lowest order page upon system power up.
Two-line control and industry standard 28-pin packaging are features common to all Intel high-density
EPROMs. This assures easy microprocessor interfaCing and minimum design efforts when upgrading, adding,
or choosing between nonvolatile memory alternatives.
The 27513 is manufactured using Intel's Compacted HMOS· II technology.
NOTE:
1. RST feature only available on devices with 6-digit suffix.
5-72
September 1989
Order Number: 231113-007
27513
D,U,lilIITJ
I
I
Vee 0 - GND 0----
t
t
WE
PAGE SELECT
LOGIC
1
Ce
OilY,.
PRDGRAU
Oe ...HDC!
'LOQIC
!
!
I
~
OUTPUT
BUFFERS
III V,6
ADD~~::JjI
X
INPUTS j
•
DECODE"
OECOO£R
r¥'
•
¥GATlNQ
121,(172
CELL MATRIX
L
......
......
......
~~
f-
L.J
~--,J
U
J
..... ,
231113-5
Figure 1. Block Diagram
2764A
~716 2732A 27C64
87C64
27128A 27256 27512
27C128 27C256 27C51~
Vpp
A12
A7
Vpp
A12
A7
A15
A12
A7
A7
A6
A5
A7
Vpp
A12
A7
As
As
As
As
As
A5
A5
AS
A5
A5
A4
A4
A4
A4
A4
A3
A2
Al
A3
A2
Al
A3
A2
Al
A3
A2
Al
Ao
Ao
A3
A2
Al
AO
00
01
02
A4
A3
,Ao
Ao
Ao
00
01
02
00
01
02
00
01
02
GND
GND
00
01
02
00
01
02
~ND GND GND GND
27512 27256 27128A
27C512 27C25E 27C128
27513
Vee
Vee
A14
A13
WE
A"
...
...
A"
iji/yPP
A2
Al
A,
As
Ail
All
2732A 271E
1!7C6~
Vee
Vee
PID;1
PGM
A13
A8
A9
All
N,C.
As
A9
All
Vee
A8
A9
Al1
l:5E
l:5E
OE PEIVPF i5E
.1\10
Al0
Al0
Al0
CE
eE
CE
eE
eE
eE
eE
'"
07
06
05
04
03
07
06
05
04
03
~
07
06
()5
04
03
~
06
05
04
03
07
06
05
04
03
.
Os
Os
04
Qa
Figure 2. Pin Configuration
1. Intel "Universal Site" compatible EPROM pin configurations are shown in the blocks adjacent to the 27513 pins.
Pin Name.
Addresses
AO-A15
CE
Chip Enabie
OElVpp
Output EnablelVpp
WE
Page·Select Write Enable
02-0 7
Outputs
Do/00,Dl /01
Input/Outputs
RST
Page Reset(l)
5-73
A9
Vpp
,0.10
231113-6
NOTE:
1. RSi' feature only available on devices with E!-digit suffix.
As
Al0
O.
NOTES:
Vee
PEIVPF
0,
--...._ _ _ _ _r-"
27C6~
A"
0.
0,,0,
Vee
A14
A13
A8
A9
All
2764A
inter
27513
:The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM,allowing
the choice of appropriate memory size to match system applications. EXPRESS EPROM products are
available with 168 ± 8 hour, 125·C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burri-in. The standard EXPRESS EPROM operating temperature range is O·C to 70·C. Extended operating temperature range (-40·C to + 85·C) EXPRESS products are available. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected·
to 0.15 electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.
EXPRESS EPROM PRODUCT FAMILY
EXPRESS OPTIONS
PRODUCT DEFINITIONS
Type Operating Temperature Burn-in 12S·C (hr)
O·Cto +70·C
·168 +8
Q
-40·C to + 85·C
T
None
-40·C to + 85·C
168 ±8
L
27513 VERSIONS
Packaging Options
Speed Versions
Cerdlp
1
-200V10
Q,L,T
.1
EXTENDED TEMPERATURE
(EXPRESS) EPROMs
READ OPERATION
D.C. CHARACTERISTICS
•
Electrical Parameters of Express EPROM Products are identical to standard EPROM parameters except for'
Symbol
Parameter
Vee Standby Current (rnA)
Vee Active Current (rnA)
Vee Active Current
at High Temperature (rnA)
ISB
lee1(1)
NOTE:
1. The maximum current value is with outiluts 00 to
TD27513
LD27S13
Min
Max
50
150
125
Test Conditions
CE = VIH, OElVpp = VIL
OElVpp = CE = VIL
a: = VIL, TAmbient: = 85·C
OElVpp ;"
0, unloaded.
30 }.IS
H
AoIlIlJ
'.• r L J
Voc
vee
A1
°7
0.
°0
°1
°2
'
=
+5V
R = 1 KIl
vss = GND
CE
,
A15
0.
03
Binary Sequence from Ao to A15
231113-9
aE:lVpp
,
Os
Vee = +sv
= GND
Burn-In Bias and Timing Dill9rams
5-74
231113-10
27513
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temperature
During Read .................... O°C to + 70°C
Temperature Under Bias ......... -10°C to + 80°C
Storage Temperature .......... - 65°C to + 125°C
All Input or Output Voltages with
Respect to,Groundt ........... - 0.6V to + 6.5V
Voltage on Pin 24 with
Respect to Ground ........... - 0.6V to + 13.5V
OElVpp Supply Voltage with
'
Respect to Ground ........... - 0.6V to + 14.0V
Vee Supply Voltage with
Respect to Ground ............ - 0.6V to + 7.0V
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
,t includes Don't Connect (pin 1)
READ AND PAGE-SELECT WRITE OPERATIONS
D.C. CHARACTERISTICS O°C ~ T A ~ + 70°C
Symbol
Limits
Parameter
Min
Test
Conditions
Units
Typ(2)
Max
=
III
Input Load Current
10
p.A
VIN
ILO
158(4)
Output Leakage Current
10
p.A
VOUT
Vee Current Standby
40
mA
CE
lee1(4)
Vee Current Active
125
mA
CE
VIL
Input Low Voltage
-0.1
+0.8
V
VIH
Input High Voltage
2.0
VOL
Vee+ 1
0.45
V
Output Low Voltage
VOH
Output High Voltage
VeLR
Page Latch Clear
Vee Supply Voltage
20
90
2.4
3.5
4.0
V
IOL
V
V,
IOH
=
=
OVtoVee
=
OV to Vee
VIH
OElVpp
=
VIL
= 2.1 mA
= -400 p.A
READ OPERATION
A.C. CHARACTERISTICS O°C ~ T A ~
+ 70°C
Vcc ±5%
27513·170V05
27513·2 '
27513·200V05
27513
Vee ±10%
27513·170V10
27513·20
27513-200V10
27513·25
Verslons(5)
"
Symbol
Parameter
Min
Max
Min
Max
Min
Units
Test
Conditions
ns
CE = OElVpp = VIL
Max
,
tAcc
Address to Output Delay
170
200
250
teE
CE to Output Delay
170
200
250
ns
OElVpp = VIL
tOE
tDF(3).
OElVpp to Output Delay
60
75
100
ns
CE = VIL
OElVpp High to
Output Float
0
60
ns
eE = VIL
toH
Output Hold from
Addresses eE or OElVpp,
Whichever Occurred First
0
ns
eE = OElVpp = VIL
50
0
0
5-75
55
0
0
•
27513
PAGE-SELECT WRITE AND PAGE-RESET OPERATION
A.C. CHARACTERISTICS
Symbol
Limits
Parameter
Min
tew
'CE to End of Write
twp
Write Pulse Width
tWR
Write ReC9very Time
tos
Data Setup Time
tOH
Data Hold Time
los
cE to Write Setup Time
tWH
WE Low from OE/Vpp High
Test
Conditions
Units
Max
180
100
20
50
20
0
55
=
ns
OE/vpp
ns
OE/Vpp = VIH
VIH
ns
=
=
OE/Vpp =
ns
ns
ns
oE/Vpp
VIH
OE/Vpp
VIi-!
VIH
ns
Delay Tiine
tRsT
Reset l.:ow Time
tRAv
Reset to Address Valid
250
250
ns
ns
NOTES:
1. Vee must be applied simultaneous.IY or before 'OElVpp and removed simultaneously or after 'OElVpp.
2. Typical values are for TA "" 25°C and nominal supply voltages.
3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
4. The maximum current value is with outputs 00-07 unloaded.
5. Packaging Options: No prefix = Cerdip; P "'" Plastic DIP; N = PLCC.
6. AST function is available only on parts with 6-digit suffix.
CAPACITANCE(2hA = + 25°C, f = 1 MHz
Typ(1)
Max
Units
Input Capacitance
4
6
pF
COUT
Output Capacitance
12
25
VOUT
OE/Vpp Capacitance
8
18
pF
CoElVpp'
pF
VIN
Symbol
CIN
Param,ter
C,ondltlons
,VIN
=
OV
=
=
OV
OV
A.C. TESTING LOAD CIRCUIT
A.C. TESTING INPUT/OUTPUT WAVEFORM
1N914
2 ••
2.0___
'
3.3KII
_ _ TEST POINTS
0.4$
0.8
DEVICE
UNDER
TEST
231113-1
AC Testing Inputs are driven a12.4V for a Logic 1 and O.45V for a
logic O. Timing measurements are made al 2.0V for a logic 1
and O.SV for a Logic O.
1----+---0 OUT
;131113-2
CL = 100 pF
CL Includes Jig Capacitance
5-76
27513
A.C. WAVEFORMS FOR READ OPERATION
V'H _ _ _ _
ADDRESSES
VIL _ _ _- J
ir--------ADORESS
VALID
1'-_ _ _ _ _
_ __
-+_
V'H _ _ _ _
V~----~---~
OilY""
VIL
OUTPUT _ _ _ _-=HIGH~Z_ _ __i+i:+i~
HIGH
VM _ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _~~_ _ __
WE
231113-3
VIL
A.C. WAVEFORMS FOR PAGE-SELECT WRITE OPERATION
ADllII2SS
DON'T CARE
ADORESSES
c;; _ _ _ _ _ _ _'"\. j4'_ _ _ _ 1cw(4( _ _ _ _. .
WE----------~
"r"I"I'~mT't"nT
1wP(41--t:~~::!---
llIIv,. _ _ _ _ _-'1
Do/Oa. D,/O,
11>-0,
INPUT/OUTPUTS
outPUTS _ _ _ _...:::HI::;,GH:.,:Z_ _ _ _ _ _ _ _ _ _ _ _ _ _...;.._
231113-4
5-77
inter
27513
A.C. WAVEFORMS FOR PAGE-RESET. OPERATIONS
::::J<.....__.;.A.;.DD;;..R.;;E.;.SS~DO.;.N_'T....;.;CA..;..R.;;E
~_
......~;;..AD;.;D.;..R.;..ES;.;S;..V.;.;.A.;;L.;.ID_
__
_____.{:tRST .V_-t-RA-V-==:r------231113-12
NOTES:
1. Typical values are for TA = + 25"C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE/vpp may be delayed up to tCE-tOE after the falling edge of CE without impact on leE.
4. Write may be terminated by either CE or WE, providing that the minimum lew requirement is met before bringing WE high '
or that the minimum twp requirement is met before bringing CE high.
5. OElVpp must be high during write cycle.
DEVICE OPERATION
The modes of operation of the 27513 are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for OElVpp and 12V on A9 for inteligent Identifier mode.
Table 1. Operating Modes
Pins
Inputl
Outputs
CE
OE/Vpp
WE
RST
A9
Ao
Vee
Read
VIL
VIL
VIH
VIH
X(1)
X
5.0V
DOUT
DOUT
Output Disable
VIL
VIH
VIH
VIH
X
X
Vec
HighZ
HighZ
Standby
VIH
X
X
VIH
X
X
Vce
HighZ
HighZ
Programming
VIL
Vpp(3)
VIH
VIH
X
X
(Note 3)
DIN
DIN
X
(Note 3)
Outputs
Mode
Verify
VIL
VIL
VIH
VIH
X
DOUT
DOUT
Program Inhibit
VIH
Vpp(3)
VIH
VIH
X
X
(Note 3)
HighZ
HighZ
Page-Select
Write
VIL
VIH
VIL
VIH
X
X
Vec<5)
HighZ
Page(2)
Page-Reset
X
X
X
VIL
X
X
"cd
HighZ
VIL
VIL
VIH
VIH
VH(7)
VIL
5.0V
89H
89H
VIL
VIL
VIH
VIH
VH(7)
VIH
5.0V
OFH(6)
OFH(6)
inte ligent(4) -Manufacturer
Identifier
-Device
DIN
5)
NOTES:
1. X can be VIH or VIL.
2. Addresses are don't care for page selection. See Table 2 for DIN values.
3. See Table 2 for Vcc and Vpp voltages.
4. A1-Aa, A10-A13, = VIL.
·5. Page 0 is automatically selected at power-up (Vcc < 4.0V).
6. 27513s before 2H/86 have a device identifier of ODH. 27513s after 2H/86 will have a device identifier of OFH.
7. VH = 12.0V ±0.5%.
5-78
X
27513
Read Mode
Page Reset
The 27513 has three control functions, two of which
must be logically active in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OElVpp) is the output control and should be used
to gate data from the output pins, independent of
device selection. Assuming that addresses are stable, the address access time (tAccl is equal to the
delay from CE to output (tCE). Data is available at
the outputs after a delay ofJQE from the falling edge
of OElVpp, assuming that CE has been low and addresses have been stable for at least tACC-tOE. WE
is held high during read operations.
The 27513 has an automatic page latch clear circuit
to ensure consistent page selection during system
bootstrapping. The page latch is automatically
cleared to page 0 upon power-up. As the Vcc supply
voltage ramps up, the page latch is cleared. After
Vcc exceeds the 4.0V maximum page latch clear
voltage (VCLR), the latch clear circuit is disabled.
rhis ensures an adequate safety margin (500 mV of
system noise below the worst case -10% Vcc supply condition) against spurious page latch clearing.
27513 parts with 6-digit suffixes also have a page
reset pill: RST. This pin should be tied to an active
low system reset signal. These 27513s will be reset
to page 0 when this line is brought to TTL Low (VILl.
Standby Mode
Two Line Control
The 27513 has a standby mode which reduces the
maximum active current from 125 mA to 40 mA. The
27513 is placed in the standby mode by applying a
TTL-high signal to the CE input. When in standby
mode, the outputs are in a high impedance state,
independent of the OElVpp and WE inputs.
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 output control lines
which accommodate this multiple memory connection. The two control lines for read operation allow
for:
a) the lowest possible memory power dissipation,
and,
b) complete assurance that output bus contention
will not occur.
Page-Select Write Mode
The 27513 is addressed by first selecting one of four
16 K-byte pages. Individual bytes are then selected
by normal random access within the 16 K-byte page
using the proper combination of Ao-A13 address inputs. By applying a TTL low signal to the WE fnput
with CE low and OE high, the desired page is
latched in according to the combination of 00/00
and 01/01. Address inputs are "don't care" during
page selection.
To use these two control lines most efficiently, CE
should be decoded and used as the primary device
selecting function, while OElVpp should be made a
common connection to all devices in the array and
connected to the READ line from the system control
bus. This assures that all deselected memory devices are in their low power standby mode and that the
output pins are active only when data is desired from
a particular memory device.
Care should be taken in organizing software programs such that the number of page changes is minimized. This allows maximum system perforniance.
Also, the processor's program counter status must
be considered when page changes occur in the middle of an opcode sequence. After a page-select
write, the program counter will be incremented to the
next location (or further in pipelined systems) in the
new page relative to that of the page-select write
opcode in the previous page.
Similarly, CE deselects other 27513s or RAMs during page select write operation while WE is in common with other devices in the array. WE is connected to the WRITE system control line.
SYSTEM CONSIDERATIONS
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced' by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed
by complying with Intel's Two·Line Control and by
Table 2. Page Selection Data
Input/Output
(Pin)
Page Selection
01/0 1
(12)
00/0 0
(11)
Select Page 0
Select Page 1
Select Page 2
Select Page 3
VIL
VIL
VIH
VIH
VIL
VIH
VIL
VIH
5-79
27513
properly selected decoupling capacitors. It is recommended that a 0.1 p.F ceramic capacitor be used on
every device between Vee and GND. This should be
a high frequency capacitor of low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 p.F bulk electrolytic
capacitor should be used between Vee and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effects of PC board traces. This inductive effect
should be further minimized through special layout
considerations such as larger traces and gridding
(refer to High Speed Memory System Design Using
the 2147H, AP-74). In particular, the Vss (Ground)
plane should be as stable as possible.
PROGRAMMING
Caution: Exceeding 14.0 V on OE/Vpp will permanently damage the 27513.
Initially, and after each erasure, all bits of the
EPROM are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations. Although only "Os" will be programmed,
both "1s" and "Os" can be present in the data word.
The only way to change a "0" to a "1" is by ultraviolet light erasure.
Except for CE, all inputs of the parallel 27513s may
be common. A TTL low-level pulse applied to the CE
input with OElVpp at its programming voltage will
program the selected 27513.
Verify
'"
A verify (read) should be performed on the programmed bits to determine that they have been correctly pro9@.mmed. The verify is performed with OEI
Vpp and CE at VIL and Vee is at its programming
voltage. Data should be verified tov after the falling
edge of CEo
inteligent Identifier™ Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufcturer and type. This mode is intended for use
by programming equipment for the purpose of automatically matching the device to be programmed
with its corresponding programming algorithm. This
mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming
the device.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
Mode.
The EPROM is in the programming mode when the
OElVpp input is raised to its programming voltage
(see Table 2) and CE is at TTL-low. The data to be
programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and
data inputs are TTL.
Byte 0 (AO = VII) represents the manufacturer code
and byte 1 (AO = VIH) the device identifier code.
These two identifier bytes are given in Table 1.
Program Inhibit
Programming of multiple 27513s in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE input inhibits the
other 27513s from being programmed.
5-80
27513
DEVICE
FAILED
DEVICE
FAILED
231113-7
Figure 5. 27513 Intellgent Programmlng™ Flowchart
5-81
inter
27513
ERASURE CHARACTERISTICS
The erasure characteristics are such that erasure
begins to occur upon exposure to light with wave'lengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and, certain
wpes of fluorescent lamps have wavelengths il) the
3000-4000 A range. Data show that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the device is to be exposed to these types of lighting conditions for ex,tended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.
the lamp tubes during erasure. The maximum inte, grated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000
p,W/cm2). Exposure of the device to high intensity
UV light for long periods may cause permanent damage.
inte.ligent Programming™
ALGORITHM
The inteligent Programming Algorithm programs
Intel EPROMs using an efficient and reliable method
Plirticularly suited to the production programming
environment. Typical programming times for individual devices are on the order of six minutes. Actual
Programming times may vary due to differe\1ces in
programming equipment. Programming reliability is
also ensured as the incremental program margin of
each byte is continually monitored to determine
when it has been successfully programmed. A flowchart of the 27513 inteligent Programming Algorithm
is shown in Figure 3. The only difference between
the 27513 and other EPROM inteligent Programr:ning is that the 27513 is programmed one 16 K-byte
page at a time.
The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
'of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
this dosage is approximately 15 to 20 minutes using
an ultravioletlamp with a 12000 p,W/cm2 power rating. The EPROM should be placed within 1 inch of
TABLE 2. D.C. PROGRAMMING CHARACTERISTICS
TA
=
25°C ±5°C
Symbol
Limits
Parameter
III
Input Current (All Inputs)
VIL
Input low level (All Inputs)
VIH
Input High level
VOL
Output low Voltage During Verify
VOH
lee2(2)
Output High Voltage During Verify
Min
Max
Units
10
p,A
-0.1
0.8
V
2.0
Vee + 1
, '0.45
2.4
Test Conditions
(Note 1)
VIN
=
V
10L
V
10H
= 2.1 rnA
= -400 p,A
VIL or VIH
V
Vee Supply Current
(Program and Verify)
125
rnA
Ipp:i(2)
Vpp Supply Current (Program)
40
rnA
VIO
Vpp
Ag inteligent Identifier Voltage
11.5
12.5
V
inteligen~
Programming Algorithm
12.0
13.0
V
Vee
inteligent Programming Algorithm
5.75
6.25
V
I
CE = VIL,
OElVpp = Vpp
NOTES:
.
1. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp:
2. The maximum current value is with outputs 00-07 unloaded.
5-82
intJ
27513
correct verify occurs. Up to 25 one-millisecond pulses per byte are provided for before the overprogram
pulse is applied. The entire sequence of program
The inteligent Programming Algorithm utilizes two
different pulse types: initial and overprogram. The
duration of the initial pulse(s) is one millisecond,
which will then be followed by a longer overprogram
pulse of length '3X msec. X is an iteration counter
and is equal to the number of the initial one millisecond pulses applied to a particular location, before a
pulses and byte verifications Is performed at
Vee = 6.0V. When the in1eligent Programming cycle has been completed, a" bytes should be compared to the original data with Vee = 5.0V.
A.C. PROGRAMMING CHARACTERISTICS
TA = 25°C ±5°C
Symbol
limits
Parameter
Min
Typ
Max
Units
tAS
Address Setup Time
2
,""S
toES
OElVpp Setup Time
2
,""S
tos
Data Setup Time
2
,""S
tAH
Address Hold Time
0
,""S
tOH
Data Hold Time
2
tOFP
Output Enable to Output Float Delay
0
tves
Vee Setup Time
2
tpw
CE Initial Program Pulse Width
0.95
topw
CE Overprogram Pulse Width
2.85
tOEH
OElVpp Hold Time
tov
Data Valid from CE
tVR
OElVpp Recovery Time
2
,""S
tpRT
OElVpp Pulse Rise Time
During Programming
50
ns
Conditions'
(Note 1)
,""S
ns
(Note 3)
,""S
(Note 1)
1.05
ms
inteligent Programming
78.75
ms
(Note 2)
130
1.0
2
,""S
1
,""S
NOTES:
1. Vce must be applied simultaneously or before OElVpp
and removed simultaneously or after OElVpp.
2. The length of the overprogram pulse (inleligent Programming Algorithm only) may vary from 2.85 ms to 78.75 ms
as a function of ,the iteration counter value X.
3. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no longe,r driven-see timing diagram.
• A.C. CONDITIONS OF TEST
Input Rise and Fa" Times (10% to 90%) ...... 20 ns
Input Pulse Levels .................. 0.45V to 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 2.0V
5-83
intJ
27513
PROGRAMMING WAVEFORMS
)(
..-K
ADDRESS STABLE
.... IAS ......
VIH
~
-
DATA IN STABLE
DATA
14-1086.OV
Vcc
S.OV
.Ioy.
I-IOH
{iVCS.
1Z.5V
I
OE/Vpp
IPRT-I
--
DATA OUT VALID
_IAH
~IOFP
~
~ES--
+-IOEH-
~
I-IVR-+t
~
CE
l
...
J
..
-
~to.....
WE
VIH------------------------------------____________________________
VIL
231113-8
NOTES:
1. The Input Timing Reference Level is O.BV for a VIL and 2.0V for a VIH.
2. toE and tOFP are characteristics of the d~ice but must be accommodated by the programmer.
3. The proper page to be programmed must be selected by a page-select write operation prior to programming each of the
four 16 K-byte pages. See Page Select Write AC and DC Characteristics for information on page selection operations.
REVISION HISTORY
Number
Description
07
Revised Express Options
Revised Pin Configuration
D.C. Characteristics-Ill Test Conditions-VIN = OV to Vee
D.C. Characteristics-ILO Test Conditions-VOUT= 0" to Vee
5-84
27C513
PAGE-ADDRESSED 512K (4 x 16K x 8)
UV ERASABLE PROM
•
•
•
•
Paged Organization
- Reduced Physical Address
Requirement
- No Bank Switching Logic Needed
Carrier Capacity
• Software
Automatic Page Clear
•
•
•
- Resets to Page 0 on Power Up and
On Demand with RST Signal
TTL and CMOS Compatible
170 ns Access Time
Two Line Control
Low Power
- 30 rnA max. Active
-100 #LA max. Standby
Compatible with Industry Standard
EPROM Pinouts
- Direct 27128A Compatibility
- 28-Pin Cerdip
The Intel 27C513 is a 5V-only, 524,288-bit ultraviolet Erasable and Electrically Programmable Read Only
Memory. It is organized as 4 pages of 16K 8-bit words. The 27C513's paged organization brings 64 Kbyte
storage capacity to existing 128K EPROM-based designs and to popular 8-bit microprocessor or microcontroller systems that have 64 Kbyte total addressing capability. The 27C513 provides an ideal means of quadrupling current 16 Kbyte code space.
'The 27C513's large storage capability of 64 Kbytes and 170 ns access time enables it to function as a high
density software carrier. Entire operating systems, diagnostics, high-level language programs and specialized
application software can reside in a 27C513 EPROM directly on a system's memory bus. This permits immediate microprocessor access and execution of software and eliminates the need for time-consuming disk accesses and downloads.
The 27C513 has an automatic page clear circuit for ease of use of the page-addressed organization. The
page-select latch is automatically cleared to the lowest order page upon system power up.
Two-line control and industry standard 28-pin packaging are features common to all Intel high-density
EPROMs. This assures easy microprocessor interfacing and minimum design efforts when upgrading, adding,
or choosing between nonvolatile memory alternatives.
The 27C513 is manufactured using Intel's 1 micron CHMOS· III-E technology.
CHMOS is a patented process of Intel Corporation.
5-85
October 1990
Order Number: 290231-002
inter
27C513
DATA
INPUTI
OUTPUTS
D.U.'(RSl')
Vee
I
I
0-----:.
~
GNO 0------+
-
WE
l l
I
PAGE SELECT
LOGIC
1
CE
DATA
OUTPUTS
DO/O~1/0, ~~
l-
BUFFERS
A''''':=:I X,I, ,b
V-GATING
PROGRAM
CE AND Ce
LOGIC
OelVpp
j
ADDRESS
INPUTS
I
.:
1
DECODER
OUTPUT
DECODER
y
~
131,072
CELL MATRIX
S
E
L
E
C
PAGE 0
T
L
L.J
PAGE 1
I
I
L,J
PAGE 2
LJ
PAGE 3
290231-1
Figure 1. Block Diagram
27C64
27C128 27C256 27C512 27C011
2732A 2764A
27128A 27256 27512 27011
87C64
Vpp
Vpp
. Vpp
A'2
A7
AS
AS
A4
A3
A2
A,
AD
00
0,
02
A'2
A7
AS
AS
A4
A2
A,
A'2
A7
AS
AS
A4
A3
A2
A,
As
As
00
0,
02
00
0,
02
A3
A2
A,
AD
00
0,
02
GNO GNO
GNO
GNO
GNO
A7
AS
AS
A4
A3
A2
A,
As
00
0,
02
~
A,S
A'2
A7
As
As
~
27C64
27C011 27C512 27C256 27C128
27C64A 2732A
27011
27512 27256 27128A
87C64
27C513
Vpp/RST
Yee
A'2
A7
Ae
AS
A4
A3
A2
A,
AD
A"
WE
A,
A"
AI
AI
A"
A'0
A'0
A'0
A'0
CE
CE
CE
CE
CE
CE
0,
07
Os
Os
04
03
07
Os
Os
04
03
07
Os
Os
04
03
07
Os
Os
04
03
07
Oe
Os
04
03
07
Os
Os
04
03
A"
A,
Oe/VPP
DolCe
0, 10,
0,10,
02102
02
04
GND
03
05
--..-----....-
Vee
PGM
N.C
As
Ag
Al1
DE
CE
AI
00100
GNO
Vee
PGM
A3
'
As
Ag
A"
DE
AlO
As
.
Vee
A'4
A'3
Vee
As
Ag
Al1
DElVpp
AlO
A.
"
Vee
Vee
PGM/WE .' A'4
A' 3
A3
'
As
As
Ag
Ag
All
Al1
DE
DElVpp
As
Ag
All
DE
290231-2
Figure 2. Pin Configuration
NOTES:
1. Intel "Universal Site" compatible EPROM pin configurations are shown in the blocks adjacent to the 27C513 pins.
Pin Names
Ao-AI5
CE
OElVpp
Addresses
WE
Page-Select Write Enable
Outputs
02-0 7
Do/Oo,DI /O ,
RST
Chip Enable
Output EnablelVpp
Input/Outputs
Page Reset
5-86
27C513
The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM, allowing
the choice of appropriate memory size to match system applications. EXPRESS EPROM products are
available with 168 ± 8 hour, 125·C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROM operating temperature range is O·C to 70·C. Extended operating temperature range (- 40·C to + 85·C) EXPRESS products are available. Like all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.15 electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.
EXPRESS EPROM PRODUCT FAMILY
EXPRESS OPTIONS
PRODUCT DEFINITIONS
27CS13 VERSIONS
EXTENDED TEMPERATURE
(EXPRESS) EPROMs
Type Operating Temperature Burn-in 12S·C (hr)
Q
T
O·Cto +70·C
-40·C to + 85·C
L
-40·Cto + 85·C
Packaging Options
168 ±8
Speed Versions
None
168 ±8
-200V10
I
I
Cerdip
Q, T,L
READ OPERATION
DC CHARACTERISTICS
Electrical Parameters of Express EPROM Products are identical to standard EPROM parameters except for·
Symbol
TD27CS13
LD27CS13
Parameter
Min
ISB
lee1(1)
Test Conditions
Max
Vee Standby Current (mA)
1.0
CE = VIH,OE/Vpp = VIL
Vee Active Current (mA)
50
OE/vpp = CE = VIL
Vee Active Current
at High Temperature (mA)
50
OE/vpp = CE = VIL, T Ambient = 85·C
NOTE:
1. The maximum current value is with outputs 00 to 07 unloaded.
290231-4
Binary Sequence from Ao to A15
OElVpp
+sv
R
vss ~ GIliD
~
~
1 K!l
CE
vee
~
290231-3
~
+sv
GND
Burn-In Bias and Timing Diagrams
5-87
intJ
27C513
ABSOLUTE MAXIMUM RATINGS'"
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.
Operating Temperature
During Read .................. O"C to + 70°C(2)
Temperature Under Bias ....... -10°C to + 80°C(2)
Storage Temperature .......... -65°C to + 125°C
Voltage on Any Pin with
Respectto Ground ............. - 2V to + 7V(I)
Voltage on As with
Respect to Ground .; ........ - 2V to + 13.5V(I)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Vpp Supply Voltage with Respect to Ground
during Programming ..•...... - 2V to + 14.0V(I)
Vcc Supply Voltage with
Respect to Ground .•.•........ - 2V to + 7.0V(I)
READ OPERATION
DC CHARACTERISTICS TIL and NMOS Inputs
Symbol
III
ILO
Parameter
Notes
Min
Input Load Current
Output Leakage Current
ISB
' Vee Current Standby
ICCI
Vee Current Active
5
IpP1
Vpp Current Read
8
Vil
Input Low Voltage (± 10% Supply)
1
VIH
Input High Voltage (± 10% Supply)
VOL
Output Low Voltage
VOH
Output High Voltage
los
Output Short Circuit Current
6
Vpp
Vpp Read Voltage
7
VClR
Page Latch Clear
VCC Supply Voltage
Typ(3)
Max
0.01
1.0
Units
' Test Condition
}LA VIN
=
OV to 5.5V
=
±10
}LA VOUT
1.0
mA CE
30
mA CE = Vil
f = 5 MHz, lOUT
10
}LA Vpp
-0.5
0.8
V
2.0
Vcc+0.5
V
0.45
V
100
mA
Vcc-0.7
Vcc
V
3.5
4.0
V
V
2.4
=
=
OV to 5.5V
VIH
=
0 mA
Vcc
= 2.1 mA
10H = 400}LA
10l
NOTES:
'1. Minimum DC input voltage is -0.5V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V which may overshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. Typical limits are at Vee = 5V, TA = + 25°C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100%
tested.
7. Vee must be applied simultaneously or before C5ElVpp and removed simultaneously or after OElVpp.
8. Maximum active power usage is the sum of Ipp and lee. The maximum current value is with no loading on outputs 00 to
07·
5-88
intJ
27C513
DC CHARACTERISTICS CMOS Inputs
Symbol
Parameter
,Notes
Min
Input Load Current
III
ILO
Output Leakage Current
ISB
Vee Current Standby
with Inputs-
leel
Vee Current Active
VIL
Input Low Voltage (± 10% Supply)
VIH
Input High Voltage (± 10% Supply)
VOL
Output Low Voltage
VOH
Output High Voltage
los
Output Short Circuit Current
ISwitching
IStable
Typ(3j
Max
Units
Test Condition
0.01
1.0
,...A
= OV to 5.5V
Your = OV to 5.5V
CE = VIH
CE = VIH
CE = VIL
f = 5 MHz, lOUT = 0 mA
4
±10
,...A
6
mA
100
,...A
30
mA
-0.2
O.B
V
0.7 Vee
Vee+ 0.2
V
5
0.4
Vee - O.B
6
100
VIN
= 2.1
V
10L
V
10H == -2.5mA
mA
mA
NOTES:
1. Minimum DC input voltage is -0.5V. During transitiohS, the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V which may overshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. Typical limits are at Vee = 5V, TA = + 25'C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100%
tested.
7. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
8. Maximum active power usage is the sum of Ipp and Icc. The maximum current value is with no loading on outputs 00 to
~
,
PAGE-SELECT WRITE AND PAGE-RESET OPERATION
AC CHARACTERISTICS
Symbol
Parameter
Limits
Min
Max
Units
Test
Conditions
tew
CE to End cif Write
100
ns
OElVpp = VIH
twp
Write PiJlse Width
50
ns
OElVpp = VIH
tWR
Write Recovery Time
20
ns
tDS
Data Setup Time
50
ns
OElVpp = VIH
20
ns
OElVpp = VIH
OElVpp = VIH
tDH
D~ta Hold Time
les
CE to Write Setup Time
0
ns
tWH
WE Low from OElVpp High
Delay Time
55
ns
tRST
Reset Low Time
100
ns
tRAV
Reset to Address Valid
150
ns
NOTES:
1. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
2. Typical values are for T A = ,25'C and nominal supply voltages.
3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
'
4. The maximum current value is with outputs 00-07 unloaded.
5. Packaging Options: No prefix = Cerdip.
.S. FiS'i' function is available only on parts with B-digit suffix.
5-89
"n+_r
111'eII"
.
27C513
CAPACITANCE(2hA = + 25·C, f =
Symbol
CIN
, COUT
C~lVpp
Parameter
1 MHz
Typ(1)
Max
Units
Conditions
=
Input Capacitance
4
8
pF
VIN
Output Capacitance
8
12
pF
VOUT
OElVpp Capacitance
18
25
pF
VIN
~C TESTING INPUT/OUTPUT WAVEI:ORM
=
OV
=
OV
OV
AC TESTING LOAD CIRCUIT
1N914
2.4
2.0 ____
_ _ _ TEST POINTS
0.45
O.B
DEVICE
UNDER
TEST
290231-5
AC Testing inputs are driven at2.4V for a Logie 1 and 0.45V for a
Logic O. Timing measurements are made at 2.0V for a Logic 1
and O.BV for a Logic O.
AC CHARACTERISTICS O·C s; T A s;
Versions(4)
VCC ±10%
Symbol
Parameter
1----+---0() OUT
290231-6
CL = 100 pF
CL Includes Jig Capacitance
+ 70·C
27C513-170V10
Min
Max
27C513-200V10
Min
Max
27C513-250V10 Units Test Conditions
Min
Max
tACC
Address to Output Delay
170
,200
250
ns
CE= OEI
Vpp = VIL
tCE
CE to Output Delay
170
200
250
ns
OElVpp = 'vIL
toE
tOF(3)
OElVpp to Output Delay
65
65
100
ns
CE = VIL
OElVpp High to Output Float
0
60
ns
tOH
Output Hold from Addresses
CE or OElVpp, Whichever
Occurred First
0
CE == VIL
CE = OEI
Vpp = VIL
55
0
0
55
0
0
ns
NOTES:
1. Typical values are for TA = 25D C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven-see timing diagram.
.
'
.
3. The maximum current value is with outputs 00-07 'unloaded.
4. Packaging: No prefix = Cerdip.
AC CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) .•.... 10 ns
Input Pulse Levels .................... VOL to VOH
Input Timing Reference Level .......••....... 1.5V
Output Timing Reference Level ..•. ' .•.• VIL and VIH
5-90
inter
27C513
AC WAVEFORMS FOR READ OPERATION
VIH _ _ _ __
'----------- ....
ADDRESS
VALID
ADDRESSES
VIL _ _ _ _--'
VIH------t-~
CE
r'-------- ....
VIH - - - - - - t - - - - " ' "
OElVpp
VIL
......- - - - t A C c - - - - t
17.,..,~rOU~UT
_ _ _ _ _~H~IG~H~Z_ _ _ __i~r+~
••.• -....,"",",
HIGH Z
VIH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......_ _ _ _.L...-"_ _ _ __
WE
VIL
290231-7
5-91
27~513
AC WAVEFORMS FOR PA~E-SELECT WRITE 'OPERATION
ADDRESS
DON'T CARE
ADDRESSES
ADDRESS
VALID
1 4 - - - -__ I CW(4) _ _ _ _- - t
CE ...- - - -__----------~
/ 4 - - - I W p ( 4 ) _ - - - o....-
WE--------------------~----~
OE/Vpp __________..,jrl
DOIOO.O,IO,
....
,-----~----
14--- tDs---t
INPUTIOUTPUTS
DATA IN STABLE
02.1)7
OUTPUTS _ _ _ _ _ _ _ _...
H._IG_H_Z__~----------~----------290231-8
AC WAVEFORMS FOR PAGE-RESET OPERATIONS
:::J<______
4__·
A
...D;.;D...
RE..,S;.;S..;D..;O...
N'T
......
CA.;,R._E____
-----------r'" l,
_.p-A_D...
DR...ES.;,S
......
VA
...L..;ID_
~,==r
.
290231-9
NOTES:
1. Typical values are for TA = + 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OElVpp may be delayed up to teE-toE after the falling edge of ~ without impact on teE'
4. Write may be terminated by either CE or WE. providing that the minimum lew requirement is met before bringing WE high
or that'the minimum twp requirement is met before bringing ~ high.
~. OElVpp must be high during write cycle.
.
5-92
inter
27C513
DEVICE OPERATION
The modes of operation of the 27C513 are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for OElVpp and 12V on As for inteligent Identifier mode.
Table 1. Operating Modes
Pins
CE
OE/Vpp
WE
RST
As
Read
VIL
VIL
VIH
VIH
Output Disable
VIL
VIH
VIH
Standby
VIH
X
Programming
VIL
Vpp(3)
Input!
Outputs
Ao
Vee
X(1)
X
5.0V
DOUT
DOUT
VIH
X
X
Vee
HighZ
HighZ
X
VIH
X
X
Vee
HighZ
HighZ
VIH
VIH
X
X
(Note 3)
DIN
DIN
X
(Note 3)
Outputs
Mode
Verify
VIL
VIH
VIH
DOUT
DOUT
Program Inhibit
VIH
VIL
Vpp(3)
X
VIH
VIH
X
X
(Note 3)
HighZ
HighZ
Page-Select
Write
VIL
VIH
VIL
VIH
X
X
Vec<5)
HighZ
Page(2)
DIN
Page-Reset
X
X
X
VIL
X
X
Vec<5)
HighZ
X
VIL
VIL
VIH
VIH
VH(6)
VIL
5.0V
89H
89H
VIH
VIH
VH(6)
VIH
5.0V
F9H
F9H
inteligent(4) -Manufacturer
Identifier
-Device
VIL
VIL
NOTES:
1. X can be VIH or VIL.
2. Addresses are don't care for page selection. See Table 2 for DIN values.
3. See Table 2 for Vee and Vpp voltages.
4. A1-Aa, A10-A13, = VIL.
5. Page 0 is automatically selected at power-up (Vee < 4.0V).
6. VH = 12.0V ±O.5%.
5-93
-
intJ
27C513
Read Mode
Page Reset
The 27C513 has three control functions, two of
which must be logically active in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable (OElVpp) is the output control and should be
used to gate data from the output pins, independent
of device selection. Assuming that addresses are
stable, the address access time (tAee) is equal to
the delay from CE to output (teE)' Data is available
at the outputs after a delay of tOE from the falling
edge of OElVpp, assuming that CE has been low
and addresses have been stable for at least
tAee-tOE. WE is held high during read operations.
The 27C513 has an automatic page latch clear circuit to ensure consistent page selection during system bootstrapping. The page latch is automatically
cleared to page 0 upon power-up. As the Vee supply
voltage ramps up, the page latch is cleared. After
Vee exceeds the 4.0V maximum page latch clear
voltage (VelR), the latch clear circuit is disabled.
This ensures an adequate safety margin (500 mV of
system noise below the worst case -10% Vee supply condition) against spurious page latch clearing.
The 27C513 also has a page reset pin: RST. This pin
should be tied to an active low system reset signal.
These 27C513s will be reset to page 0 when this line
is brought to TTL Low (VIL>.
Standby Mode
EPROMs can be placed in standby mode which reduces the maximum current of the device by applying a TTL-high signal to the CE input. When in standby mode, the outputs are in a high impedance state,
independent of the OElVpp and WE inputs.
Page-Select Write Mode
The 27C513 is addressed by first selecting one of
four 16 Kbyte pages. Individual bytes are then
selected by normal random access within the
16 Kbyte page using the proper combination of
Ao-A13 address inputs. By applying a TTL low signal to the WE input with CE low and OE high, the
desired page is latched in according to the combination of 00/00 and 01/01. Address inputs are "don't
care" during page selection.
Care should be taken in organizing software programs such that the number of page changes is minimized. This allows maximum system performance.
Also, the processor's program counter status must
be considered when page changes occur in the middle of an opcode sequence. After a page-select
write, the program counter will be incremented to the
next location (or further in pipelined systems) in the
new page relative to that of the page-select write
opcode in the previous page.
Two Line Control
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 output control lines
which accommodate this multiple memory connection. The two control lines for read operation allow
for:
a) the lowest possible memory power dissipation,
and
b) complete assurance that output bus contention
. will not oc'cur.
To use these two control lines most efficiently, CE
-should be decoded and used as the primary device
selecting function, while OElVpp should be made a
common connection to all devices in the array and
connected to the READ line from the system control
bus. This assures that all deselected memory devices are in their low power standby mode and that the
output pins are active only when data is desired from
a particular memory device.
Similarly, CE deselects other 27C513s or RAMs during page select write operation while WE is in common with other devices in the array. WE is connected to the WRITE system control line.
SYSTEM CONSIDERATIONS
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The associated transient voltage peaks can be suppressed
by complying with Intel's Two-Line Control and by
Table 2. Page Selection Data
Input/Output
(Pin)
Page Selection
Select Page 0
Select Page 1
Select Page 2
Select Page 3
01 /0 1
00/00
(12)
(11)
Vil
Vil
VIH
VIH
Vil
VIH
Vil
VIH
5-94
inter
27C513
properly selected decoupling capacitors. It is recommended that a 0.1 /-LF ceramic capacitor be used on
every device between Vee and GND. This should be
a high frequency capacitor of low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 /-LF bulk electrolytic
capacitor should be used between Vee and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effects of PC board traces. This inductive effect
should be further minimized through special layout
considerations such as larger traces and gridding
(refer to High Speed Memory System Design Using
the 2147H, AP-74). In particular, the Vss (Ground)
plane should be as stable as possible.
inteligent Identifier™ Mode
The inteligent IdentifierTM Mode allows the reading
out of a binary code from an EPROM that will identify its manufcturer and type. This mode is intended
for use by programming equipment for the purpose
of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when
programming the device.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line Ag of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line Ao from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
Mode.
.
PROGRAMMING
Byte 0 (Ao = VILl represents the manufacturer code
and byte 1 (Ao = VIH) the device identifier code.
These two identifier bytes are given in Table 1.
Caution: Exceeding 14.0 V on OE/Vpp will permanently damage the 27C513.
Initially, and after each erasure, all bits of the
EPROM are in the "1" state. Data is introduced by
selectively programming "Os" into the desired bit locations. Although only "Os" will be programmed,
both "1 s" and "Os" can be present in the data word.
The only way to change a "0" to a "1" is by ultraviolet light erasure.
Quick Pulse Programming™ Algorithm
Intel's 27C513 EPROM can be programmed using
the Quick-Pulse Programming™ algorithm, developed by Intel to substantially reduce the throughput
time in the production programming environment.
this algorithm allows these devices to be programmed as fast as fourteen seconds, almost a hundred fold improvement over previous algorithms. Actual programming time is a function of the PROM
programmer being used.
The EPROM is in the programming mode when the
OElVpp input is raised to its programming voltage
(see Table 2) and CE is at TTL-low. The data to be
programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and
data inputs are TTL.
The Quick-Pulse Programming algorithm uses initial
pulses of 100 /-Ls followed by a byte verification to
determine when the address byte has been successfully programmed. Up to 25 100 /-Ls pulses per
byte are provided before a failure is recognized. A
flowchart of the Quick-Pulse Programming Algorithm
is shown in Figure 3.
Program Inhibit
Programming of multiple 27C513s in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE input inhibits the
other 27C513s from being programmed.
For the Quick-Pulse Programming algorithm, the entire sequence of programming pulses and byte verifications is performed at Vee = 6.25V and Vpp at
12.75V. When programming of the EPROM has
been completed, all bytes should be compared to
the original data with Vee = Vpp = 5.0V.
Except for CE, all inputs of the parallel 27C513s may
be common. A TTL low-level pulse applied to the CE
input with OElVpp at its programming voltage will
program the selected 27C513.
Verify
A verify (read) should be performed on the pro. grammed bits to determine that they have been correctly programmed. The verify is performed with OEI
Vpp and CE at VIL and Vee is at its programming
Voltage. Data should be verified tDV after the falling
edge of CEo
5-95
intJ
27C513
START
DEVICE
FAILED
INCREMENT ADDR
SELECT
NEXT PAGE
DEVICE
FAILED
290231-10
Figure 3. 27C513 Quick-Pulse Programming Flowchart
5-96
inter
27C513
The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 /-tW/cm 2 power rating. The EPROM should be placed within 1 inch of
the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000
/-tW/cm2). Exposure of the device to high intensity
UV light for long periods may cause permanent damage.
ERASURE CHARACTERISTICS
(FOR CERDIP EPROMs)
The erasure characteristics are such that erasure
begins to occur upon exposure to light with waveI~ngths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000 A range. Data show that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the device is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.
TABLE 2. DC PROGRAMMING CHARACTERISTICS
TA
=
25°C ±5°C
Symbol
Limits
Parameter
lu
Input Current (All Inputs)
VIL
Input Low Level (All Inputs)
VIH
Input High Level
VOL
Output Low Voltage During Verify
VOH
Output High Voltage During Verify
lee2(2)
Min
Max
Units
1
/-t A
-0.1
0.8
V
2.4
Test Conditions
(Note 1)
VIN = VIL or VIH
6.5
V
0.45
V
IOL = 2.1 mA
V
IOH = -2.5mA
Vee Supply Current
(Program and Verify)
40
mA
IpP2(2)
Vpp Supply Current (Program)
50
mA
VID
Ag inteligent Identifier Voltage
11.5
12.5
V
Vpp
Quick-Pulse Programming Algorithm
12.5
13.0
V
Vee
Quick-Pulse Programming Algorithm
6.0
6.5
V
3.5
CE = VIL,
OElVpp = Vpp
NOTES:
1. Vee must be applied simultaneously or before OElVpp and removed simultaneously or after OElVpp.
2. The maximum current value is with outputs 00-07 unloaded.
5-97
inter
27C513
AC PROGRAMMING CHARACTERISTICS
TA = 25°C ±5°C.
Symbol
Limits
Parameter
Min
Typ
Max
Units
tAS
Address Setup Time
2
,""S
toES
OElVpp Setup Time
2
,""S
tos
Data Setup Time
2
,""S
tAH
Address Hold Time
0
,""S
tOH
Data Hold Time
2.
,""S
tOFP
Output Enable to Output Float Delay
0
tvcs
Vee Setup Time
2
tpw
CE Initial Program Pulse Width
95
toEH
OElVpp Hold Time
130
100
105
2
Conditions·
(Note 1)
ns
(Note 2)
,""S
(Note 1)
,""S
,""S
tov
Data Valid from CE
tVR
OElVpp Recovery Time
2
1
,""S
tpRT
OElVpp Pulse Rise Time
During Programming
50
ns
,""S
• AC CONDITIONS OF TEST
NOTES:
1. Vee must be applied simultaneously· or before OElVpp
Input Rise and Fall Times (10% to 90%): ..... 20 ns
and removed simultaneously or after OElVpp.
2. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no longer driven-see timing diagram.
Input Pulse Levels .................. 0.45V to 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... O.8V .and 2.0V
5-98
intJ
27C513
PROGRAMMING WAVEFORMS
VIH
ADDRESSES
VIL
VIH
DATA
VIL
6J:1V
Vee
5.OV
12.5V
OE/Vpp
VIL
IPRT
VIH
CE
VIL
VIH-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
WE
VIL
290231-11
NOTES:
1. The Input Timing Reference Level is O.SV for a VIL and 2.0V for a VIH.
2. tOE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. The proper page to be programmed must be selected by a page-select write operation prior to programming each of the
four 16 Kbyte pages. See Page Sel~ct Write AC and DC Characteristics for information on page selection operations.
REVISION HISTORY
Description
Change 150 speed option to 170.
5-99
27C011
PAGE-ADDRESSED 1M (8 x 16K x 8) EPROM
•
•
•
•
No~Hardware-Change Upgrades
- Drop-In 27513 Replacement
•
•
•
Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as
15 Seconds
•
Pag,d Organization
- Reduced Physical Address
Requirement
Compati~le
I
with 28-Pin JEDEC EPROMs
-Single-Trace Modification for
Retrofitting 27128-Ba.sed Designs
Automatic Page Clear
- Resets to Page 0 on Power-Up and
On Demand with RST Signal
High-Performance
- 200 nsA~cessl Time
- Low 30 mA Active Power
Standard EPROM Features
- TTL Compatibility
- Two Line Control
- intel/gent IdentifierTM for Automated
Programming
Smallest Megabit DIP Package
- 28-Pin DIP, Minimal Footprint without
Address/Data Multiplexing
The Inte! 27C011 is a 5V-only, 1,048,576-bit Erasable Programmable Read Only Memory. It is organized as 8
pages of 16K 8-bit words. Its pin-compatibility with byte-wide JEDEC EPROMs allows retrofitting existing
designs to the greater storage capacity afforded by the page-addressed organization. Its 16 K-byte physical
address space requirement allows the 27C011 to be utilized in address-constrained system designs.
When a 28-pin DIP socket is configured for 27C64 or 27C128 EPROMs, it is easily retrofitted to the 27C011.
By. adding a WRITE ENABLE signal to pin 27 (DIP) (unused on 27C64 and 27C128). the 27C011 can be used
in an existing design. Thus, the 27C011 enables product enhancements via additional feature sets and firmware-intensive performance upgrades.
The page-addressed organization allows the use of 28-pin DIP packages, the smallest megabit EPROM
footprint with applicability to all microprocessors. This provides very efficient circuit board layouts.
The 27C011 is part of a multi-product megabit EPROM family. The other members are standard-addressed
byte-wide and word-wide versions; the 27C010 and 27C210, respectively. The 27C010 is organized as
128K x 8 in a 32-pin DIP package which is pin-compatible with JEDEC-standard 28-pin 512K EPROMs. The
27C210 is packaged in a 40-pin DIP with a 64K x 1q organization.
The 27C011 has an automatic page clear circuit for ease of use of its paged organization. The page-select
latch is automatically cleared to the lowest order page upon system power-up. The 27C011 also contains
many industry-standard features such as two-line output control for simple interfacing and the inteligent IdentifierTM feature for automated programming. It also can be programmed rapidly using Intel's Quick-Pulse Programming™ Algorithm.
.
5-100
. October 1990
Order Number: 290232-002
inter
27C011
DATA
INPUTS/
OUTPUTS
oo,D~D~
DATA
OUTPUTS
03-07
tlo'01b2~
H~
GNDo-+
'"
PAGE SELECT
LOGIC
1
CE
LOGIC
OE
.J
'0-'13 (
ADDRESS
INPUTS
:
+
X
DECODER
I
tt
I
I
PROGRAW
OE AND CE
PGii~
+
y
DECODER
OUTPUT
BUFFERS
L
J\
.r:1
"Y"-GATING
131,072
CELL MATRIX
SELECT
PAGE 0
I
I
I
I
I
I
I
PAGE 1
•
~
.iUI
.r
PAGE 2
PAGE 3
PAGE 4
.rw
I
PAGE 5
.
u
PAGE 6
PAGE 7
290232-1
Figure 1. Block Diagram
27C513
27513
27C128
27128A
FiST
A12
A7
Av
As
A4
Aa
A2
A1
Ao
Vpp
A12
A7
As
As
A4
A3
A2
A1
Ao
00
01
O2
GNO
00 /00
01 /01
02
GNO
27C128
27128A
27C513
27513
VCC
Vee
PGM/WE
PGM
Vee
WE
A1a
As
Ag
All
OElVpp
A1D
CE
07
06
Os
04
03
27C011
Vpp/RST
A12
A13
A7
A6
A8
As
As
A4
A11
A3
OE
A2
AI
CE
Ao
07
A10
00 /0 0
06
0 1/0 1
Os
O2/0 2
04
GND
03
290232-2
Figure 2. Pin Configuration
5-101
A13
As
Ag
All
OE
A10
CE
07
Os
Os
04
03
inter
27C011
Pin Names
Ao-A13
Addresses
CE
Chip Enable
OE
Output Enable
WE
Page-Select Write Enable
03-0 7
Outputs
= 0, 1, or 2)
Ox/Ox
Input/Outputs (X
Vpp/RST
Vpp/Page Reset
NC
No Internal Connection
D.U.
Don't Use
EXTENDED TEMPERATURE
(EXPRESS) EPROMs
EXPRESS EPROM PRODUCT FAMILY .
PRODUCT DEFINITIONS
The Intel EXPRESS EPROM family is a series of
electrically programmable read only memories which
have received additional processing to enhance
product characteristics. EXPRESS processing is
available for several densities of EPROM, allowing
the choice of appropriate memory size to match system applications. EXPRESS EPROM products are
available with 168 ±8 hour, 125°C dynamic burn-in
using Intel's standard bias configuration. This process exceeds or meets most industry specifications
of burn-in. The standard EXPRESS EPROMoperating temperature range is O°C to 70°C. Extended operating temperature range (- 40°C to + 85°C) EXPRESS products are available. Like' all Intel
EPROMs, the EXPRESS EPROM family is inspected
to 0.1 % electrical AQL. This may allow the user to
reduce or eliminate incoming inspection testing.
Operating
Temperature
Type
Q
O°Cto
Burn-In
125°C (hr)
+ 70°C
168 ±8
EXPRESS OPTIONS
27C011 VERSIONS
Packaging Options
Speed Versions
-200V10
I
I
Cerdip
Q,T,L
Al~
A13
290232-4
Binary Sequence from Ao to A13 required for each page. Page
changes during burn-in, require the following minimum timing
parameter values (see Page-Select AC Characteristics):
tWH = 500 ns
twp = 500 ns
tWR = 500 ns
tos = 500 ns
IcH = 500 ns
290232-3
Vpp
~
+5V
. GND =
R
ov
=
1 KG
vee = +5V
CE = GND
Burn-In Bias and Timing Diagrams
5-102
27C011
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.
Operating Temperature During
Read .....................•..... O°C to
+ 70°C
+ BO·C
+ 125·C
Temperature Under Bias ......... -1Q°C to
Storage Temperature .....•.... - 65·C to
All Input or Output Voltages with
Respect to Ground ............ - 0.6V to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 6.5V
Voltage on A9 with
Respect to Giound ...........
~
O.SV to + 13.0V
Vpp Supply Voltage with Respect to
Ground During Programming .... -0.6V to
+ 14V
VCC Supply Voltage
with Respect to Ground ........ -0.6V to
+ 7.0V
READ OPERATION
DC CHARACTERISTICS TTL and NMOS Inputs, O·C
Parameter
,;;; T A ,;;;
Typ(3)
+ 70·C , VCC +- 10%
Max
Units
1.0
fLA
±10
fLA
500
fLA
mA
Vpp/RST
1.0
5
30
mA
CE = VIL
f = 5 MHz, lOUT
Vpp Current Read
7
10
Vpp
VIL
Input Low Voltage (± 10% Supply)
1
fLA
V
VIH
Input High Voltage (± 10% Supply)
VOL
Output Low Voltage
VOH
Output High Voltage
VelR
Page Latch Clear-Vee
los
Vpp
Output Short Circuit Current
6
Vpp Read Voltage
8
Symbol
III
Input Load Current
ILO
Output Leakage Current
ILRST
Vpp/RST Load Current
IS8
Vce Current Standby
leel
Vee Current Active
IpPl
Notes
Min
0.Q1
9
-0.5
0.8
2.0
Vee+ 0.5
0.45
2.4
3.5
Vee- 0.7V
Test Condition
= OV to 5.5V
VOUT = OV to 5.5V
VIN
CE
:0;
Vec
= VIH
=
= 0 mA
Vee
V
V
10L
= 2.1 rnA
V
10H
=
4.0
V
100
mA
Vee
V
-400 fLA
NOTES:
1. Minimum DC input voltage is -0.5V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V which may overshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. Typical limits are at Vee = 5V, TA = + 25·C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled but not 100%
tested.
7. Maximum active power usage is the sum of Ipp and Icc. The maximum current value is with no loading on outputs 00 to
07·
8. Vpp may be one diode voltage drop below Vee. It may be connected directly to Vee. Also, Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
9. Vpp/RST should be at a TTL VIH level except during programming or during page 0 reset.
5-103
intJ
27C011
READ OPERATION (Continued)
DC CHARACTERISTICS CMOS Inputs
Symbol
Parameter
Notes
Min
Typ(3)
Max
Units
0.01
1.0
p.A
VIN
Input Load Current
III
Test Condition
=
OV to 5.5V
ILO
Output Leakage Current
±10
p.A
VOUT
=
ISB
VCC Current Standby
4
100
p.A
Vcc Current Active
5
30
mA
CE =
CE =
Vcc
ICC1
f
IpP1
Vpp Current Read
10
p.A
VIL
Input Low Voltage
( ± 10% Supply)
7
-0.5
0.8
V
VIH
Input High Voltage
(± 10% Supply)
0.7Vcc
Vcc+ 0.5
V
VOL
Output Low Voltage
0.4
V
VOH
Output High Voltage
los
Output Short Circuit Current
100
rnA
V
Vcc- 0.8
6
OV to 5.5V
VIL
5 MHz, lOUT
=
Vpp
=
=
0 mA
Vcc
= 2.1 rnA
10H = -400 p.A
10L
NOTES:
1. Minimum DC input voltage is -0.5V. During transitions, the inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum DC voltage on output pins is Vee + 0.5V which may oV!lrshoot to Vee + 2V for periods less than 20 ns.
2. Operating temperature is for commercial product defined by this specification. Extended temperature options are available
in EXPRESS and Automotive versions.
3. !}tpicallimits are at Vee = 5V, TA = + 25"C.
4. CE is Vee ±0.2V. All other inputs can have any value within spec.
5. Maximum current value is with outputs 00 to 07 unloaded.
6. Output shorted for no more than one second. No more than one output shorted at a time. los is sampled, not 100%
tested.
7. Maximum active power usage is the sum of Ipp and lee.,The maximum current value is with no loading on outputs 00 to
07·
AC CHARACTERISTICS(1) O·C ~ TA S; + 70·C
Versions
Vee ±10%
Symbol
Characteristics
27C011-200V10
Min
Units
Max
tACC
Address to Output Delay
200
ns
tCE
CE to Output Delay
200
ns
tOE
OE to Output Delay
70
ns
tDF(2)
OE High to Output Float
0
eo
ns
tOH(2)
Output Hold from Addresses CE or OE,
Whichever Occurred First
0
NOTES:
1. See AC Waveforms for Read Operation for timing mea·
surements.
2. Sampled, not 100% tested.
~c
ns
CONDITIONS Of TEST
h1put Rise arid,Fall Times (10% to 90%) .••... 10 ns
Input Pulse Levels .................. 0.45V to 2.4V
Input Timing Reference Level .•....• 0.8V and 2.0V
Output Timing Reference Level ...•.. 0.8V and 2.0V
5·104
intJ
27C011
PAGE-SELECT WRITE AND PAGE-RESET OPERATION
O·C ~ T A ~
AC CHARACTERISTICS
Symbol
+ 70·C
Limits
Parameter
Min
Max
Test
Conditions
Units
tew
CE to End of Write
100
ns
OE = VIH
twp
Write Pulse Width
50
ns
OE = VIH
tWR
Write RecoveryTime
20
ns
!DS
Data Setup Time
50
ns
OE = VIH
20
ns
OE = VIH
OE = VIH
tDH
Data Hold Time
tes
CE to Write Setup Time
0
ns
tWH
WE Low from OE High Delay Time
55
ns
tRST
Reset Low Time
100
ns
tRAY
Reset to Address Valid
150
ns
CAPACITANCE(1hA = + 25·C, f =
Parameter·
Symbol
1 MHz
Typ(1)
Max
Units
4
8
pF
Input Capacitance
CIN
Conditions
VIN
= OV
COUT
Output Capacitance
8
12
pF
VOUT:;O OV
CVpp/RST
Vpp/RST Capacitance
18
25
pF
VIN
= OV
1. Sampled. Not 100% tested.
AC TESTING INPUT/OUTPUT WAVEFORM
AC TESTING LOAD CIRCUIT
1.3V
2.4~
0.45
:::
>
7
TE
POINTS
<
2.0
3.3Kll
OUTPUT
DEVICE
UNDER
TEST
0.8
290232-5
~--+----o OUT
290232-6
AC Testing inputs are driven at 2.4V for a logic 1 and 0.45V for a
logic Timing measurements are made at 2.0V for a logic 1 and
O.BV for a logic O.
CL=100pF
o.
CL Includes Jig Capacitance
5-105
,
inter
~IQ)W~OO©(g OOOIr@~IMl~iiO@OO
27C011
AC WAVEFORMS FOR READ OPERATION
V~ _ _ _ _~
W---------ADDRESS
VALID
ADDRESSES
V,L _ _ _ _J
VI" _____
+~
CE
V,L
VI"-----t---~
iiE
V,"
OUTPUT _ _ _ _......:H;:::IG::;:H.:.Z_ _ _ _tt~i+{
HIGH
V,L
V," ____________________............I_ _ _ __
We
V,L
290232-7
AC WAVEFORMS FOR PAGE-SELECT WRITE OPERATION
ADDRESS
DON'T CARE
ADDRESSES
CE
-------~ 1-----tcwl.I----~ "rn~rl-lf'T'rn:T
i'liIi/WE-----------~
!I!------I
DoIOoo D,/D,. D./Oz
Da-a,
.....1.1_-1';2:=!:!.::L__
IDS
INPUT IOUTPUTS
DATA IN STABLE
DUTPUTS _ _ _ _ _H_.IO_H;.;;;Z_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
290232-8
5-106
intJ
27C011
AC WAVEFORMS FOR PAGE-RESET OPERATION
ADDRESSES
=:x
______.r
~
r:__t_RA_V_~
ADDRESS DON'T CARE
"+--
Vpp/RST
tRST
•
ADDRESS VALID
_ _ _ _ _ _ __
II
290232-9
NOTES:
1. Typical values are for TA = + 25'C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE.
4. Write may be terminated by either CE or WE, providing that the minimum tcw requirement is met before bringing WE high
or that the minimum twp requirement is met before bringing CE high.
5. OE must be high during write cycle.
DEVICE OPERATION
The modes of operation of the 27C011 are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for Vpp and 12V on Ag for inteligent Identifier.
Table 1. Operating Modes
Pins
Mode
Read
Input!
Outputs
CE
OE
PGMI
WE
Ag
Ao
Vpp/RST
VIL
VIL
VIH
X(I)
X
VIH
5.0V
DOUT
DOUT
X
VIH
5.0V
HighZ
HighZ
Vee
Outputs
Output Disable
VIL
VIH
VIH
X
Standby
VIH
X
X
X
X
VIH
5.0V
HighZ
HighZ
Programming
VIL
VIH
VIL
X
X
Vpp(3)
VCC(3)
DIN
DIN
Verify
VIL
VIL
VIH
X
X
Vpp(3)
Vcd3)
DOUT
DOUT
Program Inhibit
VIH
X
VIH
X
X
Vpp(3)
Vcd3)
HighZ
HighZ
Page-Select Write
VIL
VIH
VIL
X
X
VIH
Vcd 5)
(Note 7)
Page DIN
X
X
X
X
X
VIL
VCC
(Note 7)
X
VIL
VIH
5.0V
89H
89H
VIH
VIH
5.0V
31H
31H
Page-Reset
inteligent
Identifier
-Manufacturer
-Device
VIL
VIL
VIH
VH(6)
VIL
VIL
VIH
VH(6)
NOTES:
1.
2.
3.
4.
5.
6.
7.
X can be VIH or VIL'
Addresses are don't care for page selection. See Table 2 for DIN values.
See Table 3 for VCC and Vpp.
A1-AS, A10-A13, = VIL.
Page 0 is automatically selected at power·up (Vcc < 4.0V).
VH = 12.0V ±0.5%.
State of outputs depends on state of CE and OE. See Outputs State for Read, Output Disable, and Standby Modes.
5-107
27C011
Read Mode
Page Reset
The 27C011 has three control functions, two of
which must be logically active in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable (OE) is the output control and should be used
to gate data from the output pins, independent of
device selection. Assuming that addresses are stable, the address access time (tACe) is equal to the
delay from CE to output (tCE)' Data is available at
the outputs after a de~ of tOE from the falling edge
of QE, assuming that CE has been low and addresses have been stable for at least tACC-tOE. WE is
held high during read operations.
The 27C011 has an automatic page latch clear circuit to ensure consistent page selection during system bootstrapping. The page latch is automatically
cleared to page 0 upon power-up. As the Vcc supply
voltage ramps up, the page latch is cleared. After
Vcc exceeds the 4.0V maximum page latch clear
voltage (VCLR), the latch clear circuit is disabled.
This ensures an adequate safety margin (500 mV of
system noise below the worst case -10% VCC supply condition) against spurious page latch clearing.
The 27C011 also has a page reset pin: Vpp/RST.
This pin shol.!ld be tied to an active low reset line.
These 27C011 s will be reset to page 0 when this line
is brought to TIL Low (VIL>.
Standby Mode·
EPROMs can be placed in standby mode which reduces the maximum current of the device by applying a TIL-high signal to the CE input. When in standby mode, the outputs are in a high impedance state,
independent of the OE and WE inputs.
Two Line Control
Page-Select Write Mode
a) the lowest possible memory power dissipation,
and
.
Because EPROMs are usually used in larger memory arrays, Intel has provided 2 output control lines
which accommodate this multiple memory connection. The two control lines for read operation allow
for:
The 27C011 is addressed by first selecting one of
eight 16 K-byte pages. Individual bytes are then se"
lected by normal random access within the 16
K-byte page using the proper combination of
Ao-A13 address inputs. By applying a TIL low signal to the WE input with CE low and OE high, the
desired page is latched in according to the combination of 00/00, 01/01 and 02/02. Address inputs
are "don't care" during page selection.
Care should be taken in organizing software programs such that the number of page changes is minimized. This allows maximum system performance.
Also, the processor's program counter status must
be considered when page changes occur in the middle of an opcode sequence. After a page-select
write, the program counter will be incremented to the
next location (or further in pipelined systems) in the
new page relative to that of the page-select write
opcode in the previous page.
Table 2. Page Selection Data
Input/Output
Page Selection
Select Page 0
Select Page 1
Select Page 2
Select Page 3
Select Page 4
Select Page 5
Select Page 6
Select Page 7
02 /0 2
01 /0 1
00 /0 0
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
b) complete assurance that output bus contention
will not occur.
To use these two control lines most efficiently, CE
should be decoded and used as the primary device
selecting function, while OE should be made a common connection to all devices in the array and connected to the READ line from the system control
bus. This assures that all deselected memory devices are in their low power standby mode and that the
output pins are active only when data is desired from
a particular memory device.
Similarly, CE deselects other 27C011 s or RAMs during page select write operation while WE is in common with other devices in the array.. WE is connected to the WRITE system control line.
SYSTEM CONSIDERATIONS
The power switching characteristics of EPROMs require careful decoupling of the devices. The supply
current, Icc, has three segments that are of interest
to the system designer-the standby current level,
the active current level, and the transient current
peaks that are produced by the falling and rising
edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitive and inductive loading of the device. The as-
5-108
27C011
sociated transient voltage peaks can be suppressed
by complying with Intel's Two-Line Control and by
properly selected decoupling capacitors. It is recommended that a 0.1 JLF ceramic capacitor be used on
every device between Vee and GND. This should be
a high frequency capacitor of low inherent inductance and should be placed as close to the device
as possible. In addition, a 4.7 JLF bulk electrolytic
capacitor should be used between Vee and GND for
every eight devices. The bulk capacitor should be
located near where the power supply is connected
to the array. The purpose of the bulk capacitor is to
overcome the voltage droop caused by the inductive
effects of PC board traces. This inductive effect
should be further minimized through special layout
considerations such as larger traces and gridding. In
particular, the Vss (Ground) plane should be as stable as possible.
PROGRAMMING
Caution: Exceeding 14.0Von Vpp will permanently damage the 27COtt.
Initially, and after each erasure, all bits of the
. EPROM are in the "1" state. Data is introduced by
selectively programming "Os" into the-desired bit locations. Although only "Os" will be programmed,
both "1s" and "Os" can be present in the data word.
The only way to change a "0" to a "1" is by ultraviolet light erasure.
The 27C011 is in the programming mode when the
Vpp input is at its programming voltage and CE is at
TTL-low. The data to be programmed is applied 8
bits in parallel to the data output pins. The levels
required for the address and data inputs are TTL.
Program Inhibit
Programming of multiple 27C011 s in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE input inhibits the
other 27C011 s from being programmed.
Except for CE, all inputs of the parallel 27C011 s may
be common. A TTL low-level pulse applied to the
PGM/WE input with Vpp at its programming voltage
will program the selected 27C011.
Verify
A verify (read) should be performed on the programmed bits to determine that they have been correctly programmed. The verify is performed with OE
and CE at VIL and Vee is at its programming voltage
Data should be verified tDV after the falling edge of
CEo
inteligent Identifier™ Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C ± 5°C
ambient temperature range that is required when
programming the device.
To activate this mode, the programming equipment
must force 11.5V to 12.5V on address line A9 of the
EPROM. Two identifier bytes may then be sequenced from the device outputs by toggling address line AO from VIL to VIH. All other address lines
must be held at VIL during the inteligent Identifier
. Mode.
Byte 0 (AO = VILl represents the manufacturer code
and byte 1 (AO = VIH) the device identifier code.
These two identifier bytes are given in Table 1.
ERASURE CHARACTERISTICS
(FOR CERDIP EPROMs)
The erasure characteristics are such that erasure
begins to occur upon exposure to light with wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain
types of fluorescent lamps have wavelengths in the
3000-4000 A range. Data show that constant exposure to room level fluorescent lighting could erase
the EPROM in approximately 3 years, while it would
take approximately 1 week to cause erasure when
exposed to direct sunlight. If the device is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to shortwave ultraviolet light which has a wavelength
of 2537 Angstroms (A). The integrated dose (Le., UV
intensity x exposure time) for erasure should be a
minimum of 15 Wsec/cm 2. The erasure time with
this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000 JLW/cm 2 power rating. The EPROM should be placed within 1 inch of
the lamp tubes during erasure. The maximum integrated dose an EPROM can be exposed to without
damage is 7258 Wsec/cm 2 (1 week @ 12000
JLW/cm2). Exposure of the device to high intensity
UV light for long periods may cause permanent damage.
5-109
inter
27C011
Vee = &.25V
Vpp'" 12.75V
x=
0
OORAM ONE 100 ,,8 PULS
290232-10
Figure 4. 27C011 Quick-Pulse Programming Flowchart
Quick Pulse Programming Algorithm
Intel's 27C011 EPROM is programmed using the
Quick-Pulse Programming algorithm, developed by
Intel to substantially reduce the throughput time in
the production programming environment. This algo·
rithm allows these devices to be programmed as
fast as fourteen seconds, almost a hundred fold improvement over previous algorithms. Actual programming time is a function of the PROM programmer being used.
fication to determine when the address byte has
been successfully programmed. Up to 25 100 JLs
pulses per byte are provided before a failure is recognized. A flowchart of the Quick-Pulse Programming algorithm is shown in Figure 4.
For the Quick-Pulse Programming algorithm, the entire sequence of programming pulses and byte verifications is performed at Vee = 6.25V and Vpp at
12.75V. When programming of the EPROM has
been completed, all bytes should be compared to
the original data with Vee = Vpp = 5.0V.
The Quick-Pulse Programming algorithm uses initial
pulses of 100 microseconds followed by a byte veri5-110
infef
27C011
DC PROGRAMMING CHARACTERISTICS
TA
=
25°C ±5°C
Table 3
Symbol
Limits
Parameter
III
Input Current (All Inputs)
VIL
Input Low Level (All Inputs)
VIH
Input High Level
VOL
Output Low Voltage During Verify
VOH
Output High Voltage During Verify
Min
Max
Units
1
p.A
-0.1
0.8
V
2.4
6.5
V
0.45
V
3.5
Test Conditions
(Note 1)
VIN
lee2(3)
Vee Supply Current (Program and Verify)
40
rnA
Vpp Supply Current (Program)
50
rnA
VIO
A9 inteligent Identifier Voltage
11.5
12.5
V
Vpp
Quick-Pulse Programming Algorithm
12.5
13.0
V
Vee
Quick-Pulse Programming Algorithm
6.0
6.5
V
VIL or VIH
= 2.1 mA
10H = - 2.5 p.A
10L
V
IpP2
=
CE
=
VIL
AC PROGRAMMING CHARACTERISTICS
= 25°C ±5°C (See Table 3 for Vee and Vpp voltages.)
TA
Symbol
Limits
Parameter
Typ
Min
Max
Units
tAS
Address Setup Time
2
p.s
tOES
OE Setup Time
2
p.s
tos
Data Setup Time
2
p.s
tAH
Address Hold Time
0
p.s
tOH
Data Hold Time
2
tOFP
OE High to Output Float Delay
0
tvps
Vpp Setup Time
2
p.s
p.s
tves
Vee Setup Time
2
teEs
CE Setup Time
2
tpw
PGM Program Pulse Width
95
tOE
Data Valid from OE
Conditions'
(Note 1)
p.s
130
ns
(Note 2)
p.s
100
105
p.s
150
ns
Quick-Pulse Programming
NOTES:
• AC CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) ...... 20 ns
Input Pulse Levels .................. 0.45V to 2.4V
Input Timing Reference Level ....... O.8Vand 2.0V
OutputTiming Reference Level ...... O.8V and 2.0V
1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp.
2. This parameter is only sampled and is not 100% tested.
Output Float is defined as the point where data is no longer driven-see timing diagram.
3. The maximum current value is with outputs 00-07 unloaded.
5-111
intJ
27C011
PROGRAMMING WAVEFORMS
PROGRAM
v,"
ADDRESSES
v"
~
V'H
DATA
VERIFY
ADDRESS STAlLE
-'''-
1
~
DATA IN STABLE
HIGHZ
1--'4"
DATA OUT vluD
-
..'D".
I+--'D'_
-1
K=
I..-
tOFP
12.75V
v..
,---I
5.0V
B.25V
Vee
-''''-
,---I I-',e,_
V,", \
s.ov
_'cES_
V,"
'ow
-'D"1
V,"
_'0'_
"\
290232-11
NOTES:
1. The Input Timing Reference Level is O.BV for a VIL and 2.0V for a VIH.
2. tOE and tOFP are characteristics of the device but must be accommodated by the programmer.
3. The proper page to be programmea must be selected by a page-select write operation prior to programming each of the
four 16 Kbyte pages. See Page Select Write AC and DC Chara~eristics for information on page selection operations.
REVISION HISTORY
Number
Description
002
Remove 150 speed option
5-112
27C010
1M (128K x 8) CHMOS EPROM
• JEDEC Approved EPROM Pinouts
- 32-Pin DIP, 32-Pin PLCC
- Simple Upgrade from Lower
Densities
• Complete Upgrade Capability to Higher
Densities
•
Versatile EPROM Features
- CMOS and TTL Compatibility
- Two Line Control
• Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as 15
Seconds
• High-Performance
-1~O ns, ± 'iO% vcc
- 30 mA Icc Active
• Surface Mount Packaging Available
- Smallest 1 Mbit Footprint in SMT
Intel's 27C010 is a 5V only, 1,048,576-bit, Erasable Programmable Read Only Memory, organized as 129,536
words of 8 bits. It is pin compatible with lower density DIP EPROMs (JEDEC) and provides for simple upgrades
to 8 Mbits in the future in both DIP and PLCC.
The 27C010 represents state-of-the-art 1 micron CHMOS manufacturing technology while providing unequaled performance. Its 120 ns speed (tACC> offers no-wait-state operation with high performance CPUs in
applications ranging from numerical control to office automation to telecommunications.
Intel offerS two DIP profile options to meet your prototyping and production needs. The windowed ceramic DIP
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic DIP (PDIP) one-time programmable part provides a lower cost alternative that is well adapted for auto insertion. .
In addition to the JEDEC 32-pin DIP package, Intel also offers a 32-lead PLCC version of the 27C010. This
one-time-programmable surface mount device is ideal where board space consumption is a major concern or
where surface mount manufacturing technology is being implemented across an entire production line.
The 27C010 is equally at home in both a TTL or CMOS environment. It programs as fast as 15 seconds using
Intel's industry leading Quick~Pulse Programming algorithm.
vcc _
DATA OUTPUTS
.
0 0 -07
GND_
vpp_
OUTPUT BUFFERS
Y-GATING
Ag-A16
ADDRESS
INPUTS
1,048,578-BIT
CELL MATRIX
290174-1
Figure 1. Block Diagram '
5-113
September 1990
Order Number: 290174-004
27C010
Pin Names
512K
Ao-A'9
ADDRESSES
C'E
CHIP ENABLE
rn:
OUTPUT ENABLE
00-07
Pl.m
OUTPUTS
NC
NO INTERNAL CONNECT
PROGRAM
27C010
aMbit
4Mblt
2Mblt
2Mblt
4Mblt
aMbit
A'9
A'6
A,s
A'2
Aj
Vpp
Vpp
Vee
Vee
Vee
Vee
A'6
A,s
A'2
A7
A'6
A,s
A'2
A7
PGN
J5
0.8
.
__
TEST POINTS _ _ _
2.0
I·
~ lN914
OUTPUT
,0_..8_ _ __
0.45
RL
290174-6
DEVICE
UNDER
TEST
AC test inputs are driven at VOH (2.4V TTU for a Logic '"1'" and
VOL (0.45V TTU for a Logie '"0'". Input timing begins at VIH (2.0V
TTU and VIL (O.BV TTU. Output timing ends at VIH and VIL. Input
Rise and Fall Times (10% to 90%) ,; 10 ns.
OUT
i--
CL
290174-7
CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 Kfl
AC WAVEFORMS
V,H-----'
ADDRESSES
V,, _ _ _ _ _J
V'H
V,H
\ ADDRESS
VALID
------+-_
------+----'""
V,H
OUTPUTS _ _ _ _ _..:H~IO::;.H:.:Z~_ _ _ _E_+~E_+_<
HIOHZ
290174-8
'5-118
inter
27C010
DEVICE OPERATION
The Mode Selection table lists 27C010 operating modes. Read Mode requires a single 5V power supply. All
inputs, except VCC and Vpp, and Ag during inteligent Identifier Mode, are TTL or CMOS.
Table 1. Mode Selection'
Notes
CE
OE
PGM
Ag
Ao
Vpp
Vee
Outputs
1
VIL
VIL
X
X
X
Vee
Vee
Dour
Output Disable
VIL
VIH
X
X
X
Vee
Vee
High:':
Standby
VIH
X
X
X
X
Vee
Vee
HighZ
Mode
Read
Program
2
VIL
VIH
VIL
X
X
Vpp
Vep
DIN'
Program Verify
VIL
VIL
VIH
X
X
Vpp
Vep
Dour
Program Inhibit
VIH
X
X
X
X
Vpp
Vep
HighZ
VIL
VIL
X
VIO
VIL
Vee
Vee
89H
VIL
X
VIO
VIH
Vee
Vee
35H
inteligent
Identifier
I Manufac~urer
I Device
2,3
VIL
NOTES:
1. X can be VIL or VIH.
2. See DC Programming Characteristics for VCP, Vpp and VIO voltages.
3. A1-AS, A1O-A16 = VIL.
Read Mode
multiple memory connections. Two-line control provides for:
The 27C01 0 has two control functions: both must be
enabled to obtain data at the ~uts. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (tCE)' Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.
a) lowest possible memory power dissipation
Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.
b) complete assurance that data bus contention will
not occur
To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.
Standby Mode
Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
S~andby Mode substantially reduces VCC current.
When CE = VIH,the outputs are in a high imped.
ance state, independent of OE.
5-119
27C010
tiona!. The PGM and NC pins may be VIL or VIH. This
allows address lines A17-A18 to be routed directly
to these inputs in anticipation of future density upgrades. A jumper between Vee and A19 allows further upgrade using the Vpp pin. Systems designed
for 1-Mbit program memories today can be upgraded to higher densities (2-Mbit, 4-Mbit, and 8-Mbit) in
the future with no circuit board changes.
Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. AIthough only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (Iss), active current levels (Icc), and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 ,...F ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,...F electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances:
Program Mode is 'entered when Vpp is raised to
12.75V. Data is introduced by applying an 8-bit word
to the output pins. Pulsing PGM low while CE = VIL
and DE = VIH programs that data into the device.
Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
programmed. With Vee at 6.25V, a substantial pro9!!!m margin is ensured. The verify is performed with
CE at...Yu. and PGM at VIH. Valid data is available tOE
after OE falls low.
Program Inhibit
Program Inhibit Mode allows parallel pr29!'amming
of multiple EPROMs with different data. CE-high inhibi!!'programming of non-targeted devices. Except
for CE, parallel EPROMs may have common inputs.
inteligent Identifier™ Mode
The intellgent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with it's proper programming algorithm. '
This mode is activated when a programmer forces
12V ±0.5V on A9. With CE, OE, A1-A8, and A10A16 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.
UPGRADE PATH
Future upgrade to 2-Mbit, 4-Mbit, and 8-Mbit densities are easily accomplished due to the standardized
pin configuration of the 27C010. When the 27C010
is in Read Mode, the PGM input becomes non-func-
ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase
an EPROM in approximately 3 years, while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity X exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 ,...W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsecl
cm 2 (1 week @ 12000 ,...W/cm2).
5-120
intJ
27C010
290174-9
Figure 4. Quick-Pulse Programmlng™ Algorithm
mine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.
Quick-Pulse Programming n , Algorithm
The Quick-Pulse programming algorithm programs
Intel's 27C010. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C010 as fast as 15 seconds. Actual programming time depends on programmer overhead.
The entire program pulse/byte verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all bytes are compared to the original data with Vee = Vpp = 5.0V.
The Quick-Pulse programming algorithm employs a
100 p.s pulse followed by a byte verification to deter-
5-121
27C010
DC PROGRAMMING CHARACTERISTICS
Symbol
Parameter
TA
Notes
= 25°C ±5°C
Min
Typ
Unit
Max
III
Input Load Current
Icp
Vcc Program Current
1
Ipp
Vpp Program Current
1
VIL
Input Low Voltage
-0.1
VIH
Input High Voltage
2.4
VOL
Output Low Voltage (Verify)
VOH
Output High Voltage (Verify)
3.5
VIO
A9 inteligent Identifier Voltage
11.5
12.0
12.5
V
2,3
12.5
12.75
13.0
V
2
6.0
6.25
6.5
V
Vpp
Vpp Program Voltage
Vcp
Vcc Supply Voltage (Program)
AC PROGRAMMING CHARACTERISTICS(4)
Symbol
Parameter
Test Condition
= VIL or VIH
= PGM = VIL
CE = PGM = VIL
1
p.A
VIN
40
mA
CE
50
mA
0.8
V
6.5
V
0.45
V
V
= 2.1 mA
10H = -2.5mA
10L
TA = 25°C ±5°C
Notes
Min
Typ
Max
Unit
tvcs
Vcp Setup Time
2
2
p.s
tvps
Vpp Setup Time
2
2
,...s
teES
CE Setup Time
2
p.s
tAS
Address Setup Time
2
p.s
tos
Data Setup Time
2
tpw
PGM Program Pulse Width
95
tOH
Data Hold Time
2
p.s
tOES
OE Setup Time
2
p.s
tOE
Data Valid from OE
tOFP
OE High to Output High Z
tAH
Address Hold Time
5
5,6
0
0
p.s
100
105
p.s
150
ns
130
ns
p.s
NOTES:
1. Maximum current is with outputs 00-07 unloaded.
2. Vcp must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming. a 0.1 p,F capacitor is required across Vpp and GNO to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. toE and tOFP are device characteristics but must be accommodated by the programmer.
S. Sampled. not 100% tested.
.
5-122
27C010
PROGRAMMING WAVEFORMS
VERIFY
PROGRAM
V,H
v"
~
VII
,
ADDRESSES
_'AS,
--
~
DATA IN STAILE
DATA
C
ADDRESS STABLE
r=t-:L _'AH
-
HIGHZ
DATA OUT
V~LlD
IOFP
_'05_
>--
. . 'DH.
12.75V
,--.-1 _'''5_
Vpp
5_0V
6.25V
,--.-1 1-',e5_
Vee
5_0V
V,HI~
V,
,
\
_'CU_
V, H
V,
,
'.w
1-'0E5
V, H
OE
V,
1
\
,
~
'0'
290174-10
REVISION HISTORY
Number
Description
04
Revised general datasheet structure, text to improve clarity.
Added PDIP package
Combined TTL/NMOS and CMOS Read Operation DC Characteristics tables.
Deleted 4 Meg and 8 Meg PLCC pinout references.
5-123
27C100
1M (128K x 8) CHMOS EPROM
II! High Performance
• Pin Compatible with 28-Pln 1 Mbit
MASK ROM
- ±10% Vee
-120 ns Maximum Access Time
• Quick-Pulse Programmlng™ Algorithm
- Programming as Fast as 15 SecQnds
• 32-Pin CERDIP and PDIP Packages
• Low Power Consumption
- 30 rnA Max. Active
--: 100 /LA Ma~. Standby
.
"
• CMOS ~nd TTL Compatibility
Intel's 27G100 is a 5V-qnly, 1,048,576 bit, Erasable Programmabie Read Only Memory organized as 131,072
bytes of 8 bits. It employs advanced CHMOS· III E circuitry for systems requiring low power, high speed
performance and noise immunity. This device is pin compatible with 28-pin 1 Mbit MASK ROMs.
The 27C100's 120 ns speed (tACe) offers no-wait-state operation with high-performance CPUs in applications
ranging from numerical control to office automation and telecommunications. The 27C100 is equally at home
in both TIL a:nd CMOS environments.
Intel offers two DIP profile option$ to meet your prototyping and production needs. The windowed ceramic DIP
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic DIP (PDIP) one-time programmable part provides a lower cost !!-Iternative that is well adapted for auto insertion. This EPROM solution is particularly well-suited for "Just-In Time"
code customiza:tion to meet specific geographic or application needs in your product line. The Quick-Pulse
ProgramminQTM AlgOrithm provides fast, reliable programming.
'CHMOS is a patented procel?s of Intel Corporation.
DATA OUTPUTS
Vee ~o- - - ;..~
GND ~o- - - ;..~
VPPO
00-0 7
..
OUTPUT BUFFERS
Y-GATING
Ao- A 16
ADDRESS
INPUTS
X
DECODER
1,048,576-SIT
CELL MATRIX
290270-1
Figure 1. Block Diagram
5-124
October 1990
Order Numbe" 290270-002
inter
27C100
27C100
1 Mb Mask ROM
1 Mb Mask ROM
Vpp
1
Vee
OE
PGt.l
A15
A12
A15
A12
A7
A6
A5
A4
A3
A2
A1
AS
GND
A14
A13
As
CE
°7
°6
°0
°1
°2
02
Vee
A14
A13
As
Ag
A11
A16
A10
A2
Al
Ao
Ao
00
01
NC
Os
°4
°3
GND
290270-2
Figure 2. DIP Pin Configuration
Pin Names
AO-A16
ADDRESSES
00-0 7
OUTPUTS
OE
OUTPUT ENABLE
CE
CHIP ENABLE
PGM
PROGRAM
NC
NO CONNECT
5-125
Ag
A11
A16
A10
CE
07
06
05
04
03
27C100
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to chilnge without notice.
Operating Temperature ............. O·C to 70·C(1)
Temperature under Bias ........... -1 O·C to BO·C
Storage Temperature ............. - 65·C to 125·C
Voltage on Any Pin (except
Ag, Vee and Vpp)
with Respect to GND ......... - 0.6V to .6.25V(2)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage on Ag with
Respect to GND ............... - 0.6V to 13V(2)
Vpp Program Voltage
with Respect to GND ........... -0.6V to 14V(2)
Vee Supply Voltage with
Respect to GND ................ - 0.6V to 7V(2)
READ OPERATION DC CHARACTERISTICS
Symbol
Parameter
III
Input Load Current
ILO
Output Leakage Current
ISB
Vee Standby Current
Notes
Min
7
Vee
Typ
0.01
=
5.0V ±10%
Max
Unit
p,A
VIN
p,A
VOUT
=
=
OV to 5.5V
=
oy to 5.5V
1.0
mA
CE
100
p,A
CE
mA
f = 5 MHz,
CE = VIL, lOUT
Vee Operating Current
.3
30
Ipp
Vpp Operating Current
3
10
p,A
los
Output Short Circuit Current
4,6
100
mA
VIL
Input Low Voltage
-0.5
O.B
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Vpp
Vpp Operating Voltage
Vee
+ 0.5
0.45
2.4
Vee - 0.7
=
1.0
±10
lee
5
Test Condition
=
Vee ±0.2V
=
0 mA
Vee
V
V
V
Vee
Vpp
VIH
= 2.1 mA
10H = - 400 p,A
10L
V
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum DC voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. Maximum active power usage is the sum Ipp + Icc. Maximum current value is with outputs 00-07 unloaded.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Vpp may be connected directly to Vee or may be 1 diode voltage drop below Vee. Vee must be applied Simultaneously or
before Vpp and removed simultaneously or after Vpp.
6. Sampled, not 100% tested.
7. Typical limits are at Vee = 5V, TA = 25°e.
B. Absolute Maximum rating applies to Ne pins.
5-126
27C100
READ OPERATION AC CHARACTERISTICS(1)
Versions(4)
Symbol
I
27C100-120V10
Vee ±10%
Parameter
Notes
tAcc
Address to Output Delay
teE
CE to Output Delay
tOE
OE to Output Delay
tDF
OE High to Output High Z
3
tOH
Output Hold from
Addresses, CE or OE
Change- Whichever
Occurs First
3
Min
27C100-200V10
27C100-150V10
P27C100-150V10 P27C100-200V10 Unit
Min
Max
Min
Max
120
150
200
ns
2
120
150
200
ns
2
55
60
70
ns
30
50
60
ns
0
0
0
ns
\
NOTES:
1.
2.
3.
4.
Max
vcc = 5.0V ±10%
.
See AC Input/Output Reference Waveform for timing measurements.
OE may be delayed up to tCE-toE after the falling edge of CE without impact on teE,
Sampled, not 100% tested.
Model Number Prefixes: No Prefix = CERDIP, P = PDIP.
AC WAV,EFORMS
V,H - - - - - - , .
ADDRESS
VALID
ADDRESSES
VIl------I
1'----------....
V,H ---~-_+__..
V,H
------+----"\
'OF
1'7"""""",,- ••,•• - ......ri'l"'.-i
-+H+K
OUTPUTS _ _ _ _ _H:::;IO:::H:,.:Z_ _ _ _
HIOHZ
290270-6
5-127
27C100
CAPACITANCE(4)
Symbol
= 25°C, f = 1 MHz
TA
Parameter
Typ(5)
Max
Unit
Condition
= OV
= OV
Vpp = OV
CIN
Input Capacitance
4
B
pF
COUT
Output Capacitance
B
12
pF
Cvpp
Vpp Capacitance
16
25
pF
AC INPUT/OUTPUT REFERENCE WAVEFORM'
VIN
VOUT
AC TESTING LOAD CIRCUIT
1.3V
2.4
2.0>
0.8
__
TEST POINTS ____
2.0
OUTPUT
'1.,;0;,;;;.8___
0.45
290270-7
AC test inputs are driven at VOH (2.4 VTTU for a Logic
"1" and VOL (0.45 VTTU for a Logic "0". Input timing
begins at VIH (2.0 VTTU and VIL (0.8 VTTU. Output timing ends at VIH and VIL. Input rise and fall times (10%
to eO%) s; 10 ns.
t-~~-oOUT
290270-8
CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 KG
DEVICE OPERATION
The Mode Selection table lists 27C100 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, and Ae during inteligent IdentifierTM Mode, are TTL or CMOS.
Table 1. Mode Selection
Mode
Read
PGM
Ag
Ao
VIL
VIL
X
X
VIL
VIH
X
X
CE
1
Output Disable
Standby
Program
OE
Notes
2
Vpp
Vee
Outputs
X
VCC
Vee
DOUT
X
Vee
Vcc
HighZ
VIH
X
X
X
X
VCC
VCC
HighZ
VIL
VIH
VIL
X
X
Vpp
Vcp
DIN
Program Verify
VIL
VIL
VIH
X
X
Vpp
Vcp
DOUT
Program Inhibit
VIH
X
X
X
X
Vpp
VCP
HighZ
VIL
VIL
X
VID
VIL
Vee
Vce
B9H
VIL
VIL
X
VID
VIH
Vec
VCC
32H
inteligent Identifier
-Manufacturer
-Device
2,3
NOTES:
1. X can be VIL or VIH.
2. See DC Programming Characteristics for Vep, Vpp and VIO voltages.
3. Al-Ae, Al0-A16 = VIL.
'
4. Sampled, not 100% tested.
5. Typical limits are at Vee = 5V, TA = 25'C.
5-128
intJ
27C100
Read Mode
Program Mode
The 27C100 has two control functions; both must be
enabled to obtain data at the Q!!!puts. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (tCE). Outputs display valid
data toE after OE's falling edge, assuming tACC and
teE times are met.
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. AI·
though only "Os" are programmed, the data word
can contain poth "1 s" and "Os". Ultraviolet light erasure is lile ouly way io cili:lllye "Os" io "Is".
Vee must be applied simultaneously or before
Program Mode is entered when Vpp is raised to
12.75V. Data is introduced by applying an a-bit word
to the output pins. Pulsing PGM low while CE = VIL
and OE = VIH programs that data into the device.
Vpp and removed simultaneously or after Vpp.
Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention wil!
not occur
To efficiently use these two control i~ts, an address decoder should enable CE while OE should be
connected to all memory devices and the system's
READ control line. This assures that only selected
memory devices have active outputs while deselected memory devices are in Standby Mode.
Standby Mode
Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
programmed with VCC at 6.25V, a substantial pro~m margin is ensured. The verify is performed with
CE at~ and PGM at VIH. Valid data is available tOE
after OE falls low.
Program Inhibit
Program Inhibit Mode allows parallel pr2.9!"amming
of multiple EPROMs with different data. CE-high inhibi~rogramming of non-targeted devices. Except
for CE, parallel EPROMs may have common inputs.
Standby Mode substantially reduces Vee current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.
5-129
inter
27C100
inteligent IdentifierTM Mode
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
This mode is activated when a programmer .forces
12V ±0.5V onAg. With A1-AS, A10-A16, CE and
OE at VIL, Ao = VIL will present the manufacturer's
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.
Two-Line Control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 /LF ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 /LF electrolytic
c;:apacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.
ERASURE CHARACTERISTICS
ROM Compatibility
The 27C100 is compatible with 28-pin mask ROMs
to provide a reprogrammable memory solution durc
ing prototyping and early production. Reference Figure 2; design in the 32-pin socket for the 27C100
EPROM and connect Vee to pins 1, 30 and 32. If the
EPROM is replaced with a MROM, socket pins 1, 2,
31 and 32 are' no longer required.
SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are in~
terested in 3.supply current issues-standby current
levels (Iss), active current levels (Icel, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device outputs' capacitive and inductive loading.
Erasure begins when EPROMs are expos~d to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase an
EPROM in approximately 3 years, while it takes approximately 1 week when exposed to direct sunlight.
If the device is exposed to these lighting conditions
for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
'
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537 A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 /LW/cm2 power rating.
The EPROM should be placed within 1, inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsec/
cm 2 (1 week @ 12000 jLW/cm 2 ).
5-130
inter
27C100
290270-10
Figure 3. Quick-Pulse Programming Algorithm
Quick-Pulse Programming Algorithm
The Quick-Pulse programming algorithm programs
Intel's 27C100. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C100 as fast as 15 seconds. Actual programming time depends on programmer overhead.
The Quick-Pulse programming algorithm e!"1ploys a
100 Il-s pulse followed by a byte verification to determine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.
5-131
The entire program-pulse/byte verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all bytes are compared to the original data with Vee = Vpp = 5.0V.
inter
27C100
DC PROGRAMMING CHARACTERISTICS TA = 25°C ± 5°C
Symbol
Parameter
Notes
Min
Unit
1
p.A
VIN = VIL or VIH
1
40
mA
CE = PGM = VIL
1
50
mA
CE =
-0·1
0.8
V
2.4
6.5
V
0.45
V
IOL = 2.1 mA
V
IOH = -2.5 mA
12.0
12.5
V
12.q
·12.75
13.0
V
6.0
6.25
6.5
V
Input Lo~d Current
Icp
Vcc Program Current
Ipp
Vpp Program Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage (Verify)
VOH
Output High Voltage (Verify)
:3.5
11.5
2,3
2
VIO
A9 intaligent Identifier Voltage
Vpp
Vpp Progral"!l Voltage
Vcp
Vcc Supply Voltage (Program)
Typ
Max
III
Test Condition
P~M =
VIL
.
.
AC PROGRAMMING
CHARACTERISTICS(4} TA = 25°C ± 5°C
.,
Symbol
Parameter
Typ
Notes
Min
tvcs
Vcp Setup Time
2
2
p.s
tvps
Vpp Setup Time
2
2
p.s
teES
CE Setup Time
2
p.s
tAS
Address Setup Time
2
p.s
tos
Data Setup Time
2
p.s
tpw
PGM Program Pulse Wiclth
95
tOH
Data Hold Time
2
toES
m: Setup Time
toE
Data Valid from OE
tOFP
OE High to Output High Z
tAH
Address Hold Time
100
Max
105
5,6
0
0
p.s
p.s
2
5
Unit
p.s
150
ns
130
ns
p.s
NOTES:
'1. Maximum current is with outputs 00-0;: unloaded.
2. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 ""F capacitor is required between Vpp and GND to s!lPpress spurious voltage transients, which
can damage the device,
4. See AC Input/Output RefElren~e Waveform for timing mElasurements.
5. toE and tOFP are device characteristics but must be accommodated by the programmer.
S. Sampled. not 1QO% test~d.
.
.
5-132
inter
27C100
PROGRAMMING WAVEFORMS
PROGRAM
V,"
ADDRESSES
).
V"
VERIFY
ADDRESS STABLE
I+--'AS ___
•
V,H
DATA
1\
DATA IN STABLE
1--- 105 _ _
VIL
HIGHZ
-
X
_'A"
!
DATA OUT VALID
'(
.'0" ...
IOFP
>--
12.75V
5.0V~
Vpp
I---IVP5_ _
6.25V
Vee
5.0V
V,"
Ce
V"
J
_',e5_
~
I-
tCES _ _
V,"
\
PGM
V"
v,"
Oe
-H-
I""-
10 ' 5 1
"\
v"
r-
10'
290270-11
REVISION HISTORY
Description
Number
002
Deleted -120 PDIP package.
Revised classification from Advance Information to Preliminary.
Deleted Express Offerings.
5-133
'27C020
2M (256K x 8) CHMOS EPROM
• JEDEC Approved EPROM Pinouts
- 32-Pin DIP, 32-Pin PLCC
- Simple Upgrade from Lower
Densities
•
Complete Upgrade Capability to Higher
Densities
•
Versatile EPROM Features
- CMOS and TTL Compatibility
- Two Line Control
• Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as 30
Seconds
•
High~Performance
-150 ns, ± 10% Vce
- 30 mA Icc Active.
• Surface Mount Packaging Available
- Smallest 1 Mbit Footprint in SMT
Intel's 27C020 is a 5V-only, 2,097,152-bit Erasable Programmable Read .Only Memory, organized as 262,144
words of 8 bits each. It is pin compatible with lower density DIP EPROMs (JEDEC) and provides for simple
upgrades to 8 Mbits in the future in both DIP and PLCC.
The 27C020 represents state-of-the-art. 1 micron CMOS manufacturing technology while providing unequaled
performance. Its 150 ns speed (tACC> offers no-wait-state operation with high performance CPUs in applications ranging from numerical control to office automation to te.lecommunications.
Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic DIP
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic DIP (PDIP) one-time programmable part provides a lower cost alternative that is well adapted for auto insertion.
In addition to the JEDEC 32-lead DIP package, Intel also offers a 32-lead PLCC version of the 27C020. This
one-time-programmable surface mount device is ideal where .board space consumption is a major concern or
'
where surface mount manufacturing technology is being implemented across an entire production· line.
The 27C020 is equally at home in both a TTL or CMOS environment. It programs as fast as 30 seconds using
Intel's industry leading Quick-Pulse Programming algorithm.
DATA OUTPUTS
Vcc~
.
0 0 -0 7
GND 0 - - - - - - .
Vpp 0 - - - - - - .
OUTPUT BUFFERS
V-GATING.
Ao- A 17
ADDRESS
INPUTS
X
DECODER
2M BIT
CELL MATRIX'
290226-1
Figure 1. Block Diagram
5-134
September 1990
Order Number: 290226-003
intJ
27C020
Pin Names
Ao-A,9 ADDRESSES
CHIP ENABLE
CE
OE
OUTPUT ENABLE
0 0 .07
OUTPUTS
PGM
PROGRAM
NC
NO INTERNAL CONNECT
27CC20
8Mblt
4Mblt
1Mbit
A'9
A,6
A,s
Vpp
A,6
A,s
Vpp
vpp
vee
A'6
A,s
A16
PG"
A,s
Vpp
A'5
A17
Vee
A'2
A7
A6
As
A4
A3
A2
A,
AD
00
0,
02
GND
A'2
A7
A6
As
. A4
A'2
A7
A6
As
A4
A3
A2
A,
AD
00
0,
02
GND
A'2
A7
A6
As
A4
A3
A2
A,
AD
00
0,
02
GND
A'2
A7
A6
As
A4
A3
A2
A,
AD
00
0,
02
GND
A'2
A,.
A7
A.
A"
As
A3
A2
A,
AD
00
0,
02
GND
512K
256K
256K
A5
A.
A,
A"
A,
6E
A2
A,
AlO
A'4
A,3
Aa
Ag
All
OE
AlO
cr
CE
AD
°7
00
0.
07
06
05
04
03
0,
°5
°2
0,
GNo
0,
512K
Vee
A'4
A,3
Aa
Ag
A"
OElVpp
AlO
CE
07
06
05
04
03
1Mblt
4Mblt
8Mbit
Vec
PGM
N.C.
Vee
A,a
Vee
A,a
A17
A'4
A'3
Aa
Ag
A'7
A'4
A'3
Aa
Ag
All
OE
AlO
CE
07
06
05
04
03
A"
OE
AlO
CE
07
06
Os
04
03
290226-2
Figure 2. DIP Pin Configuration
290226-9
Figure 3. PLCC Lead Configuration
5-135
A'4
A,3
Aa
Ag
All
OElVpp
AlO
CE
07
06
05
04
03
27C020
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice.
Operating Temperature ...•......•.. O·C to 70·C(1)
Temperature Under Bias ........•.. -10·C to SO·C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Storage Temperature ............. -:- 65·C to 125·C
Voltage on Any Pin
(except Ag, Vee and Vpp)
with Respect to GND ..••...... - 0.6V to 6.5V(2)
Voltage on Ag with
Respect to GND •.•••.•.•••.• -0.6V to 13.0V(2)
Vpp Program Voltage
with Respect to GND ........••. -0.6V to 14V(2)
Vee Supply Voltage
with Respect to GND .....••.•. -0.6V to 7.0V(2)
READ OPERATION DC CHARACTERISTICS
Symbol
III
ILO
ISB
lee
Parameter
Input Load Current
Notes
Min
7
Output Leakage Current
. Vee Standby Current
Vee Operating Current
Ipp
Vpp Operating Current
los
Output Short Circuit Current
3
Vee
=
5.0V ±10%
Typ
Max
Unit
0.Q1
1.0
p.A
VIN
±10
p.A
1.0
mA
= OV to 5.5V
= VIH
CE = Vee ±0.2V
CE = VIL
f = 5 MHz, lOUT = 0 mA
Vpp = Vee
100
p.A
30
mA
3
10
p.A
4,6
100
mA
O.S
V
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Vpp
Vpp Operating Voltage
Vee
+ 0.5
0.45
2.4
5
Vee - 0.7
Vee
Test Condition
=
OV to 5.5V
VOUT
CE
V
V
10L
V
10H
= 2.1 mA
= - 400 p.A
V
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC input voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for
periods <20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which, during transitions. may overshoot to Vee
+ 2.0V for periods <20 ns.
3. Maximum active power usage is the sum Ipp + lee. Maximum current is with outputs 00 to 07 unloaded.
4. Output shorted·for no more than one second. No more than one output shorted at a time.
5. Vpp may be connected directly to Vee. or may be one diode voltage drop below Vee. Vee must be applied simultaneously
or before Vpp and removed simultaneously or after Vpp.
6. Sampled. not 1'00% tested.
7. Typical limits are at Vee = 5V. TA = 25·C.
5-136
inter
27C020
READ OPERATION AC CHARACTERISTICS(1) vcc = 5.0V ±10%
Versions(4)
Symbol
vee ±10%
Parameter
27C020-150V10 .
Notes
Min
Max
27C020-200V10
P27C020-200V10
N27C020-200V10
Min
Unit
Max
150
200
ns
2
150
200
ns
OE to Output Delay
2
60
70
ns
tDF
OE High to Output High Z
3
50
60
ns
tOH
Output Hold from
Addresses, CE or OE
Change-Whichever is First
3
tACC
Address to Output Delay
tCE
CE to Output Delay
tOE
0
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to tCE-toE after the falling edge of CE without impact on toE.
3. Sampled, not 100% tested.
4. Model number prefixes: No Prefix = CERDIP, P = PDIP, N = PLCC.
5-137
0
ns
inter
27C020
CAPACITANCE(1}
= 25°C, f = 1MHz
TA
Parameter -
Symbol
Typ(2)
Max
Unit
8
pF
VIN = OV
12
pF
VOUT = OV
25
pF
Vpp = OV
CIN
Input Capacitance
COUT
Output Capacitance
4
8
Cvpp
Vpp Capacitance
18
Conditions
NOTES:
1. Sampled, not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
AC INPUT/OUTPUT REFERENCE WAVEFORM
1.3V
2.4
2.0>
0.45
AC TESTING LOAD CIRCUIT
~
TEST POINTS ~
0.6
2.0
OUTPUT
,,0;;,;;.6~_ _
!lN914
290226-4
RL
DEVICE
UNDER
TEST
AC testing inputs are driven at VOH (2.4 Vnu for a logic "1" and
VOL (0.45 VnL) for a logic "0". Input timing begins at VIH (2.0
Vnu and VIL (O.B VITu, Output timing ends at VIH and VIL. Input
rise and fall times (10% to 90%) ,;;10 ns.
CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 Kfl
OUT
f---
CL
290226-5
AC WAVEFORMS
.,H------,.
ADDRESS
ADDRESSES
VALID
VOL-----
V,H
VOL
V,H
-------t-""'"
1'-----------····
~-----+_-----"'\
V,H
~un--------~H~IG~H~Z----~~~~<
HIOHZ
290226-6
5-138
inter
27C020
DEVICE OPERATION
The Mode Selection table lists 27C020 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vcc and Vpp, and A9 during inteligent Identifier Mode, are TTL or CMOS.
Table 1. Mode Selection
Mode
Notes
CE
OE
PGM
Ag
Ao
Vpp
Vee
Outputs
1
VIL
VIL
X
X
X
Vcc
Vcc
DOUT
v
v
Read
Output Disable
VIL
VIH
v
A
A
Vee
Vec
HighZ
Standby
VIH
X
X
X
X
Vcc
Vcc
HighZ
VIL
VIH
VIL
X
X
Vpp
Vcp
DIN
VIL
VIL
VIH
X
X
Vpp
Vcp
DOUT
2
Program
Program Verify
Program Inhibit
inteligent
Identifier
I Manufacturer
I Device
2,3
A
VIH
X
X
X
X
Vpp
Vcp
HighZ
VIL
VIL
X
VID
VIL
Vcc
Vcc
89H
VIL
VIL
X
VID
VIH
Vcc
Vcc
34H
NOTES:
1. X can be VIL or VIH
2. See DC Programming Characteristics for VCP, Vpp, and VID voltages.
3. Al-Aa, AlO-A17 = VIL
a) lowest possible memory power dissipation
Read Mode
The 27C020 has two control functions; both must be
enabled to obtain data at the Q!:!!puts. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACc) equals the
. delay from CE to output (teE)' Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.
Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.
Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
b) complete assurance that data bus contention will
not occur
To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.
Standby Mode
Standby Mode substantially reduces Vcc current.
When CE = VIH the outputs are in a high impedance state, independent'of OE.
5-139
intJ
27C020
to this input in anticipation of future density upgrades. A jumper between Vee and A19 allows further upgrade using the Vpp pin. Systems designed
for 2-Mbit program memories today can be upgraded to higher densities (4-Mbit and 8-Mbit) in the future with rio circuit board changes.
Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (ISB), active current levels (lee), and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend On the
device output's capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 ,...F ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,...F electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board inductances.
Program mode is entered when Vpp is raised to
12.75V. Data is introduced by applying an 8-bit word
to the output pins. Pulsing PGM low while CE = VIL
and OE = VIH programs that data into the device.
Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
programmed. With Vee at 6.25V, a substantial pro~m margin is ensured. The verify is performed with
CE a~ and PGM at VIH. Valid data is available toE
after OE falls low.
Program Inhibit
ERASURE CHARACTERISTICS·
Program Inhibit Mode allows parallel prQ9!"amming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE, parallel EPROMs may have common inputs.
Inteligent IdentifierTM Mode
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
This mode is activated when a programmer forces
12V ±0.5V on Ag. With CE, OE, A1-AS, and A10A17 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.
UPGRADE PATH
Future upgrade to 4-Mbit and 8-Mbit densities are
easily accomplished due to the standardized pin
configuration of the 27C020. When the 27C020 is in
Read Mode, the PGM input becomes non-functional.
This allows address Une A1 S to be routed directly to
Erasure begins when EPROMs are exposed to light .
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase
an EPROM in approximately 3 years, while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537 A. The integrated dose (UV intensity X. exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an Ultraviolet lamp with a 12000 ,...W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsecl
cm 2 (1 week @ 12000 ,...W/cm2 ).
5-140
27C020
290226-7
Figure 4. Quick-Pulse Programming™ Algorithm
Quick-Pulse Programming™ Algorithm
The Quick-Pulse programming algorithm programs
Intel's 27C020. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C020 as fast as 30 seconds. Actual programming time depends on programmer overhead.
The Quick-Pulse programming algorithm employs a
100 ,""S pulse followed by a byte verification to determine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.
The entire program pulse/byte verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all bytes are compared to the original data with Vee = Vpp = 5.0V.
5-141
27C020
DC PROGRAMMING CHARACTERISTICS
Symbol
Parameter
TA = 25°C ±5°C
Notes
Min
Typ
Max
Unit
III
Input Load Current
Icp
Vcc Program Current
1
Ipp
Vpp Program Current
1
VIL
Input Low Voltage
-0.1
VIH
Input High Voltage
2.4
VOL
Output Low Voltage (Verify)
VOH
Output High Voltage (Verify)
3.5
VIO
Ag inteligent Identifier Voltage
11.5
12.0
12.5
2,3
12.5
12.75
13.0
2
6.0
6.25
6.5
Vpp
Vpp Program Voltage
VcP
Vcc Supply Voltage (Program)
AC PROGRAMMING CHARACTERISTICS(4)
Symbol
Parameter
Test Condition
1
!k A
VIN = VIL or VIH
40
mA
CE = PGM = VIL
50
mA
CE = PGM = VIL
0.8
V
6.5
V
0.45
V
IOL = 2.1 mA
V
IOH = -2.5mA
V
V
TA = 25°C ±5°C
Notes
Min
Typ
Max
Unit
tvcs
Vcc Setup Time
2
2
!ks
tvps
Vpp Setup Time
2
2
!ks
tCES
CE Setup Time
2
!ks
tAS
Address Setup Time
2
!ks
tos
Data Setup Time
2
tpw
PGM Program Pulse Width
95
tOH
Data Hold Time
2
!ks
tOES
OE Setup Time
2
!ks
tOE
Data Valid from OE
tOFP
OE High to Output High Z
tAH
Address Hold Time
5
5,6
0
0
!ks
100
105
!ks
150
ns
130
ns
!ks
NOTES:
1. Maximum current is with outputs 00':'07 unloaded.
2. VcP must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 ,."F capacitor is required across Vpp and GNO to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. tOE and tDFP are device characteristics but must be accommodated by the programmer.
6. Sampled, not 100% tested.
5-142
inter
27C020
PROGRAMMING WAVEFORMS
VERIFY
PROGRAM
~
V'H
ADDRESSES
ADDRESS STABLE
r\
DATA IN STABLE
DATA
~'D'---'--
•
4O~T V~LlD
~1A5=:j
~'D".
HIGHZ
DATA
"
-
L
I+-"H
r-
tOFP
12.15V
,---1 _',.,_
Ypp
5.0V
6.25V
Vee
,---1
5.0Y
l-'ve5_
~
I-Y,"
X
V,"
OE
'CES_
f-
1005
..
V, l
1
"\
-10E
290226-8
REVISION HISTORY
Number
003
Description
Revised general datasheet structure, text to improve clarity
Added PDIP package
Combined TTL/NMOS and CMOS Read Operation Characteristics tables
Revised classification from Advance Information to Preliminary
Deleted 4 Meg and 8 Meg PLCC pinout references.
·Deleted EXPRESS page.
5-143
27C040
4M (S12K x 8) CHMOS EPROM
• Fast Programming
- Quick-Pulse Programming™
Algorithm
- Programming Time as Fast as 60
Seconds
• High-Performance
-150 ns, ± 10% Vee
- 50 mA lee Active
• JEDEC Approved EPROM Pinout
-32-Pln DIP
- Simple Upgrade from Lower
Densities
• Easy Upgrade Capability to 8 Mbit
Density,
•
Versatile' EPROM Features
- CMOS and TTL Compatibility
- Two Line Control
The Intel 27C040 is a 5V-only,4,194;304-bit Erasable Programmable Read Only Memory, organized as
524,288 words of 8 bits each. It is pin compatible with lower density DIP EPROMs (JEDEC) and provides for
simple upgrade to 8 Mbits in the future.
The 27C040 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled
performance. Its 150 ns speed (TACel offers no-wait-state operation with high performance CPUs in applications ranging from numerical, control to office automation to telecommunications.
The 27C040 is equally at home in both a TTL or CMOS environment. It programs as fast as 60 seconds using
Intel's industry leading Quick-Pulse Programming algorithm.
DATA OUTPUTS
vee O-O-----i...
GND
00-0 7
()oo- - - . , . "
OUTPUT BUFFERS
Y-GATING
Ao- A18
ADDRESS
INPUTS
X
DECODER
4,194,304-BIT
CELL MATRIX
290239-1
Figure 1. Block Diagram
5-144
September 1990
Order Number: 290239-002
27C040
Pin Names
00-0 7
ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
PROGRAM
OUTPUTS
NC
NO INTERNAL CONNECT
Ao-A,9
CE
OE
J5lm
.....,.."' .. '"
",",V"'IU
1Mbl!
2Mblt
8Mblt
vpp
Vee
256K
vee
vee
A,.
A,.
PGM
PGM
NC
A14
A17
A,4
A,s
vee
A,s
A17
A'4
A'3
As
As
Al1
OElVpp
A10
8Mbl!
2Mbl!
1Mbl!
A,g
A,S
VPP
A,s
VPP
A,s
A'5
A,2
A7
As
A5
A4
A'5
A'2
A7
A5
A'5
A'2
A7
As
A5
A'5
A,2
A7
AS
A5
Vpp
A,2
A7
AS
A5
A'7
A,.
A,.
A.
A.
A4
A4
A4
A4
A"
A:!
A3
A2
A,
Ao
00
0,
02
GND
A3
A2
A,
Ao
00
0,
02
GND
A3
A2
A,
Ao
00
0,
02
GND
A3
A2
A,
Ao
00
0,
02
GND
A2
A,
Ao
00
0,
02
GND
As
512K
256K
Of
AIO
A,
A,
cr
AO
00
0,
°7
0,
0.
GNO
°3
290239-2
Figure 2. DIP Pin Configuration
5-145
Vee
A,4
512K
A'3
As
Ag
Al1
OE
A,o
Vee
A'4
A'3
As
Ag
Al1
OElVpp
A,o
CE
CE
07
Oa
05
04
03
07
Os
05
04
03
A'3
Aa
Ag
Al1
OE
A10
CE
07
Oe
Os
04
03
As
As
Al1
DE
A,o
CE
Or
06
Os
04
03
CE
07.
Oe
Os
04
03
inter
27C040
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains information on
products in the sampling and'initial production phases
of development. The specifications are subject to
change without notice.
Operating Temperature ............. ooe to 70oe(1)
Temperature Under Bias ........... - 1ooe to aooe
Storage Temperature ............. - 65°e to 125°e
Voltage on Any Pin
(except Ag, VCC and Vpp)
with Respect to GND .......... - O.6V to 6.5V(2)
Voltage on Ag with
Respect to GND .....•....... - O.6V to 13.0V(2)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Vpp Supply Voltage with
Respect to GND ............... - O.6V to 14V(2)
VccSupply Voltage with
Respect to GND ............... -O.6V to 7.0V(2)
READ OPERATION DC CHARACTERISTICS
Symbol
Parameter
Notes
Vcc
Min
=
Typ
Max
Unit
Test Condition
= OV to 5.5V
III
Input Load Current
1.0
)-LA
VIN
ILO
Output Leakage Current
±10
)-LA
VOUT
Vee Standby Current
1.0
mA
CE
100
)-LA
CE
50
mA
CE = VIL
f = 5 MHz, lOUT
10
)-LA
Vpp
=
100
mA
0.8
V
V
10L
= 2.1
V
10H
=
IS8
0.Q1
5.0V ±10%
7
Icc
Vee Operating Current
3
Ipp
Vpp Operating Current
3
los
Output Short Circuit Current
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Vpp
Vpp Operating Voltage
4,6
Vee
+ 0.5
0.45
2.4
5
Vee - 0.7
Vee
= OV to 5.5V
= VIH
= Vee
±0.2V
= 0 mA
Vee
V
mA
-400)-LA
V
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for
periods < 20 ns. Maximum DC voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee
+ 2.0V for periods < 20 ns.
3. Maximum active power usage is the sum Ipp + Icc. Maximum current is with outputs 00 to 07 unloaded.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Vpp may be connected directly to Vee, or may be one diode voltage drop below Vee. Vee must be applied simultaneously
or before Vpp and removed simultaneously or after Vpp.
6. Sampled, not 100% tested.
7. Typical limits are at Vee = 5V, TA = 25°C.
5-146
inter
27C040
READ OPERATION AC CHARACTERISTICS(1) vcc
Verslons(4)
Symbol
Vee ±10%
Parameter
tACC
Address to Output Delay
tCE
CE to Output Delay
tOE
t __
·ur
tOH
Notes
-
OE to Output Delay
=
5.0V ± 10%
27C040-150V10
27C040-200V10
Min
Min
Max
Units
Max
150
200
ns
2
150
200
ns
2
60
70
ns
ncui
.........
"''''.,
........ ·u: .......I ...
.,
_ ......
I
_ .... t' ••u. I
..."
GO
60
ns
Output Hold from Addresses, CE or
OE Change-Whichever is First
3
"~I
~v
II~'
0
0
ns
NOTES:
1. See AC Input/Output Reference, Waveform for timing measurements.
2. OE may be delayed up to tCE-toE after the falling edge of CE without impact on tCE.
3. Sampled, not 100% tested.
4. Model number prefixes: No prefix = CERDIP.
5. Typical values are for T A = 25"C and nominal supply voltages.
CAPACITANCE(3) TA '7
25"C, f = 1MHz'
Typ(5)
Max
Unit
CIN
Input Capacitance
4
8
pF
COUT
Output Capacitance
8
12
pF
Cvpp
Vpp Capacitance
18
25
pF
Symbol
Parameter
AC INPUT/OUTPUT REFERENCE WAVEFORM
2.4
2.0>
0.45
0.8
TEST POINTS
<
Conditions
= OV
= OV
Vpp = OV
VIN
VOUT
AC TESTING LOAD CIRCUIT
1.3V
-r-
~~ lN914
2.0
OUTPUT
,'0;;,:;.8:;..._ _
290239-3
DEVICE
UNDER
TEST
AC test inputs are driven at VOH (2.4 VnLl for a logic "1" and
VOL (0.45 VnLl for a logic "0". Input timing begins at VIH
(2.0 VnLl and VIL (O.S VnLl. Output liming ends at VIH and VIL.
Input rise and fall times (10% to 90%) ,;; 10 ns.
CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 Kn
5-147
t--+--oOUT
290239-4
inter
27C040
AC WAVEFORMS
V,. _____
ADDIIUS
VALID
ADDRESSES
VIL----- 1'----------....
I---ICE---+\
V,.
-------r---"""
V,.
HIOHZ
oo~~S _ _ _ _ _~H='Q~H~Z_ _ _ _ _ _~ti~~
290239-5
DEVICE OPERATION
The Mode Selection table lists 27C040 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, and A9 during inteligent Identifier Mode, are TIL or CMOS.
Table 1. Mode Selection
Mode
Notes
CE
OE
A9
Ao
Vpp
Vee
Read
1
VIL
VIL
X
X
Vee
Vee
Dour
Output Disable
VIL
ViH
X
X
Vee
Vee
HighZ
Standby
VIH
X
X
X
Vee.
Vee
HighZ
Program
2
Program Verify
Program Inhibit
inteligent
Identifier
I
I
Manufacturer
Device
2,3
Outputs
VIL
VIH
X
X
Vpp
Vep
DIN
VIH
VIL
X
X
Vpp
Vep
Dour
VIH
VIH
X
X
Vpp
Vep
HighZ
VIL
VIL
VIO
VIL
Vee
Vee
89H
VIL
VIL
VIO
VIH
Vee
Vee
3DH
NOTES:
1. X can be VIL or VIH
2. See DC Programming Characteristics for Vcp, Vpp and VIO voltages.
3. Al-Aa, Al0-Ala. = VII:
5-148
inter
27C040
Read Mode
The 27C040 has two control functions; both must be
enabled to obtain data at the outputs. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (tCE). Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.
Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.
Two Line Output Control
Program Mode is entered when Vpp is raised to
12.75V. Data is introduced by applying an a-bit word
to the output pins. Pulsing CE low while OE = VIH
programs that data into the device.
Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
~fugfilIYIl-fl~u. vvm-, Vee at O.25V it suusiafli.iai tJIUgram margain is ensured. The verify is performed
with CE at VIH. Valid data is available toE after OE
falls low.
Program Inhibit
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for: .
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur
Program Inhibit Mode allows parallel prQg!'amming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE and OE, parallel EPROMs may have common
inputs.
inteligent IdentifierTM Mode
To efficiently use these two control inputs, and address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
Standby Mode
This mode is activated when a programmer forces
12V ±0.5V on Ag. With CE, OE, A1-A8, and A10A18 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.
Standby Mode substantially reduces VCC current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.
UPGRADE PATH
Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
Future upgrade to the a Mbit density is easily accomplished due 1to the standardized pin configuration of the 27C040. A jumper between VCC and A19
allows upgrade using the Vpp pin. Systems designed
for 4 Mbit program memories today can be upgraded
to a Mbit in the future with no circuit board changes.
5-149
inter
27C040
SYSTEM CONSID~RATIONS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (Iss), active current levels (lcd, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive arid inductive loading.
Two-line control and. proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 JlF ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 JlF electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor viill overcome voltage slumps caused by PC
board trace inductances.
.
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase an
EPROM in approximately 3 years, while it takes approximately 1 week when exposed to direct sunlight.
If the device is exposed to these. lighting conditions
. for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/ cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 JlW/cm2 powerrating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds
7258 Wsec/cm 2 (1 week @ 12000 JlW/cm2).
ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
5-150
27C040
290239-6
Figure 3. Quick-Pulse Programming Algorithm
Quick-Pulse Programming™ Algorithm
The Quick-Pulse Programming Algorithm programs
Intel's 27C040. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C040 as fast as 60 seconds. Actual programming time depends on programmer overhead.
mine when the addressed byte has been successfully programmed. The algorithm terminates if 25 attempts fail to program a byte.
The Quick·Pulse Programming Algorithm employs a
100 J.Ls pulse followed by a byte verification to deter-
5·151
The entire program pulse/byte verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all bytes are compared to the original data with Vee = Vpp = 5.0V.
27C040
DC PROGRAMMING CHARACTERISTICS TA = 25°C ±5°C
Symbol
Parameter
III
Input Load Current
Notes
Min
Typ
Max
Unit
Test Condition
1
}LA
VIN = VIL or VIH
ICp
Vcc Program Current
1
50
mA
CE = VIL
Ipp
Vpp Program Current
1
50
mA
CE
VIL
Input Low Voltage
-0.1
VIH
Input High Voltage
2.4
VOL
Output Low Voltage (Verify)
VOH
Output High Voltage (Verify)
VIO
Ag inteligent Identifier Voltage
Vpp
Vpp Program Voltage
Vcp
Vcc Supply Voltage (Program)
Parameter
V
6.5
V
0.45
3.5
V
10L = 2.1 mA
V
10H = -2.5mA
11.5
12.0
12.5
V
2,3
12.5
12.75
13.0
V
2
6.0
6.25
6.5
V
AC PROGRAMMING CHARACTERISTICS(4)TA
Symbol
·0.8
= VIL
= 25°C ±5°C
Notes
Min
Typ
Max
Unit
tvcs
Vcp Setup Time
2
2
}Ls
tvps
Vpp Setup Time
2
2
}Ls
tAS
Address Setup Time
2
}Ls
tos
Data Setup Time
2
}Ls,
tpw
CE Program Pulse Width
95
tOH
Data Hold Time
2
tOES
OE Setup Time
tOE
Data Valid from OE
tOFP
OE High to Output High Z
tAH
Address Hold Time
100
105
}Ls
2
5
5,6
}Ls
150
0
0
}Ls
130
ns
ns
}Ls
NOTES:
1. Maximum current is with outputs 00-07 unloaded.
2. Vep must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 ",F capacitor is required across Vpp and ground to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. toE and tDFP are device characteristics but must be accommodated by the programmer.
6. Sampled, not 100% tested.
5-152
intJ
27C040
PROGRAMMING WAVEFORMS
! 4 - - - - - - P A O G . A M - - - - - - i - - - - V••,fY - - - - I
v,"
ADO.ESSES
v"
IA.
'';IH
HIGHZ
DATA
VII
12.75Y
Vpp
S.OV
UsV
vee
S.OV
v,"
CE
v"
·OES
10.
v,"
iI£
v"
290239-7
REVISION HISTORY
Number
02
\ Description
Revised general datasheet structure, text to improve clarity.
Combined TTL/NMOS and CMOS Read Operation DC Characteristics Tables.
Mode Selection table-Program Inhibit-OE revised from X to VIH.
5-153
27C210
. 1M (64K x 16) CHMOS EPROM
• High-Performance
-120 ns ±10% Vcc
,- 50 rnA Icc Active
• Fast Programming
- Quick-Pulse Programming™
Algorithm
.:- Programming Times As Fast As
. 8 Seconds
• JEDEC Approved EPROM Pinouts
-40-Pin DIP
- 44-Pin PLCC
• Complete Upgrade to Higher Densities
• Versatile EPROM Features
- CMOS and TTL Compatibility
- Two Line Control
Intel's 27C210 is a 5V only, 1,048,576-bit Erasable Programmable Read Only Memory, organized as 65,536
words of 16 bits each. Its standard pinouts provide for simple upgrades to 4 Mbits in the future.
The 27C210 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled
performance. Its 120 ns speed (tACe) offers no-wait-state operation with high performance CPUs in applications ranging from numerical control to office automation to telecommunications.
Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic dip
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the
design is in full production, the plastic dip (PDIP) one-time programmable part provides a lower cost alternative
that is well adapted for auto insertion.
.
In addition to the JEDEC 40-pin DIP package, Intel also offers a 44-lead PLCC version of the 27C210. This
one-time-programmable surface mount device is ideal where board spac~ consumption is a major concern or
where surface mount manufacturing techn?logy is being implemented across an entire production line.
The 27C21 0 is equally at home in both a TTL or CMOS environment. And like Intel's other 1 Mbit EPROMs,
the 27C210 programs quickly using Intel's industry leading Quick-Pulse Programming algorithm.
Vee
0
DATA OUTPUTS
00-0 15
•
GND~
Vpp 0
•
. OUTPUT BUFFERS
V-GATING
Ao- A 15
ADDRESS
INPUTS
X
DECODER
1,048,576-BIT
CELL MATRIX
290193-1
Figure 1. Block Diagram
5~154
, September 1990
Order Number: 290193.003
inter
Pin Names
lAo-Ani ADDRESSES
vI:
CHI~ t=i. . Ai3LE
OE
OUTPUT ENABLE
OO.Q1S OUTPUTS
PROGRAM
PGM
NO INTERNAL CONNECT
NC
27C210
27C210
4M
2M
Vpp
Vpp·
VPP
vee
CE
CE
015
01'
0 13
012
011
010
CE
°°15_
1
PGM
Ne
00
0 15
0 1,
0 13
012
011
010
0:::
08
GND
07
06
Os
0,
03
02
01
00
O"E
OE
('I:::
08
GND
07
06
Os
0,
03
02
01
°13
°12
°11
°10
2M
4M
Vee
Vee
PGM
A1S
Al_
A13
A12
All
A16
A1S
Al'
A13
.A12
All
Ai7
A16
A15
A14
A13
A12
All
"IU
.A.~y
.A·i;j
As
GND
A7
Ag
GND
A8
A7
As
As
As
A4
A3
A2
Al
Ao
As
A,
A3
A2
Al
Ao
..
-.
n.
Ag
Os
GND
GND
AS
A7
A6
AS
°7
°6
°5
0_
°3
O2
01
00
A-
DE
Ao
A3
A2
Al
As
290193-2
Figure 2. DIP Pin
Configuration
290193-3
Figure 3. PLCC Lead Configuration
5-155
inter
27C210
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temperature ......•....•. O°C to 70°C(1)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond ·the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Temperature Under Bias .........•. -10°C to. 80°C
Storage Temperature ......•...... - 65°C to 125°C
Voltage on Any Pin
(except Ag, Vee and Vpp)
with Respect to GND ......•. -0.6V to 6.5V(2, 8)
Notice: Specifications contained within the following
tables are subject to change.
Voltage on Ag with
Respect to GND ......•....•. - 0.6V to 13.0V(2)
Vpp Program Voltage
with Respect to GND ......•.... -0.6Vto 14V(2)
Vee Supply Voltage
with RespeCt to GND ..•....... - 0.6V to 7.0V(2)
READ OPERATION DC CHARACTERISTICS(1)
Symbol
III
Parameter
Input Load Current
Notes
Min
7
Vee
=
5.0V ±10%
Typ
Max
Unit
0.01
1.0
/LA
VIN
Test Condition
=
OVtoVee
=
ILO
Output Leakage Current
±10
/LA
VOUT
ISB
Vee Standby Current
1.0
rnA
CE
100
/LA
CE
lee
Vee Operating
Current
3
50
rnA
CE
VIL
f = 5 MHz, lOUT
Ipp
Vpp Operating Current
3
10
/LA
Vpp
=
los
Output Short
Cir~uit Current
4,6
100
rnA
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee +0.5
V
VOL
Output Low Voltage
0.45
V
10L
VOH
Output High Voltage
V
10H
= 2.1 rnA
= -400/LA
Vpp
Vpp Operating Voltage
2.4
5
Vee - 0.7
Vee
=
=
=
OV to Vee
VIH
Vee ±0.2Y
=
0 rnA
Vee
V
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -0.5V on input/output pins. During tranSitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. Maximum active power usage is the sum Ipp + lee. Maximum current value is with outputs 00 to 015 unloaded.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Vpp may be connected directly to Vee, or may be one diode voltage drop below Vce. Vee must be applied simultaneously
or before Vpp and removed simultaneously or after Vpp.
6. Sampled, not 100% tested.
7. Typical limits are at Vee = 5V, TA = 25·C.
8. Absolute Maximum ratings apply to Ne pins.
5-156
inter
27C210
READ OPERATION AC CHARACTERISTICS(1) vcc
vee ± 10%
Verslons(4)
Parameter
Symbol
tACC
Address to Output Delay
teE
CE to Output Delay
27C210·120V10
Notes
Min
2
5.0V ±10%
=
27C210·150V10
P27C210·150V10
N27C210·150V10
Max
Min
Max
150
200
ns
120
150
200
ns
70
ns
60
ns
OE to Output Delay
2
55
tOF
OE High to Output High Z
3
30
50
3
Unit
120
toE
Output Hold from
Addresses, CE or OE
Change-Whichever is
First
Min
Max
60
toH
27C210·200V10
P27C21D-200V10
N27C210·200V10
0
0
0
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE may be delayed up to teE-tOE after the falling edge of CE without impact on tCE.
3. Sampled, not 100% tested.
4. Model Number Prefixes: no prefix = CERDIP, P = PDIP, N = PLCC.
5. Typical limits are set for TA = 25°C and nominal supply voltages.
CAPACITANCE(3)
Symbol
TA
=
Parameter
1 MHz
Typ(S)
Max
Unit
8
pF
VIN = OV
12
pF
25
pF
VOUT = OV
Vpp = OV
CIN
Input Capacitance
COUT
Cvpp
Output Capacitance
4
8
Vpp Capacitance
18
AC INPUT/OUTPUT REFERENCE WAVEFORM
=
25°C, f
Conditions
AC TESTING LOAD CIRCUIT
1.3V
2.4~
0.45
:::
>
TE
7
POINTS<=::
2.0
TE
OUTPUT
lN914
0.8
RL
290193-6
DEVICE
UNDER
TEST
AC test inputs are driven at VOH (2.4 Vnu for a Logic "I" and
VOL (0.45 Vnu for a Logic "0". Input timing begins at VIH
(2.0 Vnu and VIL (O.B Vnu. Output timing ends at VIH and VIL.
Input Rise and Fall times (10% to 90%) ,;: 10 ns.
CL = 100pF
CL Includes Jig Capacitance
RL = 3.3 kfl
5·157
OUT
i--
Cl
290193-7
intJ
27C210
AC WAVEFORMS
VI"----~
ADDRESS-
ADDRESSES
VALID
V,, _ _ _ _- - '
V," _ _ _ _ _
_+_~
V," _ _ _ _ _-+____
'""
V,"
OUTPUTS _ _ _ _ _;;;HIO~H;.:Z_ _ _ __+H*'H
HIGHZ
290193-8
DEVICE OPERATION
The Mode Selection table lists 27C21 0 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vcc and VPP, and Ag during inteligent Identifier Mode, are TTL or CMOS.
Table 1. Mode Selection
Notes
CE
OE
PGM
Ag
Ao
Vpp
Vee
Outputs
1
VIL
VIL
X
X
X
Vec
Vee
DOUT
Output Disable
VIL
VIH
X
X
X
Vee
Vce
HighZ
Standby
VIH
X
X
X
X
Vee
Vee
HighZ
Mode
Read
VIL
VIH
VIL
X
X
Vpp
Vep
DIN
Program Verify
VIL
VIL
VIH
X
X
Vpp
Vep
DOUT
Program Inhibit
VIH
X
X
X
X
Vpp
.Vcp
HighZ
VIL
VIL
X
VID
VIL
Vee
Vee
0089 H
VIL
VIL
X
VID
VIH
Vee
Vee
11EEH
2
Program.
inteligent
Identifier
I
I
Manufacturer
Device
2,3
NOTES:
1. X can be VIL or VIH
2. See DC Programming Characteristics for Yep. Vpp and VID voltages.
3. A1-A8. A1Q-A15 = VIL
5-158
intJ
27C210
Read Mode
Program Verify
The 27C21 0 has two control functions; both must be
enabled to obtain data at the outputs. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (tCE)' Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.
A verify should be performed following a program
operation to determine that bits have been correctly
programmed. With Vcc at 6.25V, a substantial program margin is ensured. The verify is performed with
CE a~ and PGM at VIH. Valid data is available tOE
after OE falls low.
i=rogram inhiDii
Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.
Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power dissipation .
b) complete assurance that data bus contention will
not 'occur
To efficiently use these two control inputs, an ad~
dress decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.
Program Inhibit Mode allows parallel programming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE, parallel EPROMs may have common inputs.
,inteligent IdentifierTM Mode .
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with it's proper programming algorithm.
This' mode is activated when a programmer forces
12V ± 0.5V on Ag. With CE, OE, A1-Aa, and A1OA15 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.
UPGRADE PATH
Standby Mode
Standby Mode substantially reduces VCC current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.
Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
Future upgrades to 2 Mbit and 4 Mbit densities are
easily accomplished due to the standardized pin
configuration of the 27C210. When the 27C21 0 is in
Read Mode, the PGM input becomes non-functional.
The PGM and NC pins may be VIL and VIH. This
allows address lines A16-A17 to be routed directly
to these inputs in anticipation of future density upgrades. Systems designed for 1 Mbit program memories today can be upgraded to higher densities (2
Mbit and 4 Mbit) in the future with no circuit board
changes.
Program Mode is entered when Vpp is raised to
12.75V. Data is introduced by applying a 16-bit word
to the output pins. Pulsing PGM low while CE = VIL
and OE = VIH programs that data into the device.
5-159
inter
27C210
SYSTEM CONSIDERATIONS
ERASURE CHARACTERISTICS
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (ISB), active current levels (Ieel, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 ,...F ceramic capacitor
connected between its Vee and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,...F electrolytic
capacitor should be placed at the array's power supply connection between Vee and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase
an EPROM in approximately 3 years, while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an Ultraviolet lamp with a 12000 ,...W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose ,exceeds 7258
Wsec/cm 2 (1 week @ 12000 ,...W/cm2).
5-160
inter
27C210
290193-9
Figure 4. Quick-Pulse Programming™ Algorithm
Quick-Pulse Programming™ Algorithm
The Quick-Pulse Programming algorithm programs
Intel's 27C210. Developed to substantially reduce
programming t/lroughput, this algorithm can program
the 27C210 as fast as 8 seconds. Actual programming time depends on programmer overhead.
The Quick-Pulse Programming algorithm employs a
100 ,""S pulse followed by a word verification to de·
termine when the addressed word has been successfully programmed. The algorithm terminates if
25 attempts fail to program a word. '
The entire program pulse/word verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all words are compared to the original data with Vee = Vpp = 5.0V.
5-161
intJ
27C210
DC PROGRAMMING CHARACTERISTICS
Symbol
Parameter
TA = 25°C ±5°C
Min
Typ
Max
Unit·
1
,...A
VIN
1
50
mA
CE
1
50
,mA
CE
0.8
V
Notes
III
Input Load Current
Icp
Vcc Program Current
Ipp
Vpp Program Current
VIL
Input Low Voltage
-0.1
VIH
Input High Voltage
2.4
VOL
Output Low Voltage (Verify)
6.5
V
0.45
V
VOH
Output High Voltage (Verify)
3.5
VIO
Ag intaligent Identifier Voltage
11.5 '
12.0
12.5
V
2,3
12.5
12.75
13.0
V
2
6,.0
6.25
6.5
V
Vpp
Vcp
, Vpp Program Voltage
Vcc Supply Voltage (Program)
AC PROGRAMMING CHARACTERISTICS(4)
Symbol
Parameter
TA
Notes
V
=
Test Condition
= VIL or VIH
= PGM = VIL
= PGM = VIL
= 2.1 mA
IOH = -2.5 mA
10L
25°C ± 5°C
Min
Typ
Max
Unit
tvcs
Vcp Setup Time
'2
2
tvps
Vpp Setup Time
2
2
,...s
tees
CE Setup Time
2
,...s
,...s
,...s
tAS
Address Setup Time
2
tos
Data Setup Time
2
tpw
PGM Program Pulse Width
95
tOH
Data Hold Time
2
,...s
toes
OE Setup Time
2
,...s
toe
Data Valid from OE
tOFP
OE High to Output High Z
tAH
Addr~ss
5
5,6
Hold Time
0
0
,...s
100
105
,...s
150
ns
130
ns
,...s
NOTES:
1. Maximum current is with outputs 00-015 unloaded.
2. Vep must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 p.F capaCitor is required across Vpp and GND to suppress spurious voltage transients which
,'.
,
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. tOE and tOFP are device characteristics but must be accommodated by the programmer.
6. Sam·pled,. not 100% tested.
5-162
27C210
PROGRAMMING WAVEFORMS
VERIFY
PROGRAM
---")
ADDRESSES
-
V"
ADDRESS STABLE
_I"j
1
DATA
1\
DATA IN STABLE
r--- IO' _ _
•
HIGHZ
'f
I+IOH.
-:1
l
~_IA"
I
DATA OUT VALID
tOFP
~
12.75V
Vp p
S.OV
---11---
1",_ _
6.25V
,~ I-Ivc,_
Vee
5.0V
I
i\
I--
ICES _ _
,}{
_IOES_j
I+-
V, H
DE
"
V, L
10E
---.
REVISION HISTORY
Number
03
Description
Revised gen~ral datasheet structure, text to improve clarity
Revised speed bin as follows:
tACC was 130 ns, is now 120 ns
teE was 130 ns, is now 120 ns
tOE was 60 ns, is now 55 ns
Added PDIP package
Revised IS9 Text Condition from CE = Vee to CE = Vee ± 0.2V
Revised VOL from 0.4V to 0.45V
Revised VOH from Vee - O.BV to 2.4V
Deleted 8 meg DIP, 4 and 8 Meg PLCC references
Deleted EXPRESS page
5-163
290193-10
27C220
2M (128K
x 16) CHMOS EPROM
Programming
• -FastQuick-Pulse
Programming™
JEDEC Approved EPROM Pinouts
• -40-Pin
DIP
Algorithm
- Programming Times As Fast As
15 Seconds
- 44-Pin PLCC
EPROM Features
• -Versatile
CMOS and TTL Compatibility
- Two Line Control
High-Performance
• -150
ns ± 10% Vee
Mount Packaging Available
• Surface
• Complete Upgrade to Higher Densities
- 50 mA lee Active
Intel's 27C220 is a 5Vonly, 2,097,152-bit Erasable Programmable Read Only Memory. Organized as 131,072
words of 16 bits each. It is pin compatible with Intel's 1 Mbit 27C210 and provides for a simple upgrade to
4 Mbits in the future.
The 27C220 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled
performance. Its 150 ns speed (tACe) offers no-wait-state operation with high performance CPUs in applications ranging from numerical control to office automation to telecommunications.
Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic dip
(CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once tlie
design is in full production, the plastic dip (PDIP) one-time programmable part provides a lower cost alternative
that is well adapted for auto insertion.
In addition to the JEDEC 40-pin DIP package, Intel also offers a 44-lead PLCC version of the 27C220. This
one-time-programmable surface mount device is ideal where board space consumption is a major concern or
where surface mount manufacturing technology is being implemented across an entire production line.
The 27C220 is equally at home in both a TTL or CMOS environment. And like Intel's other high density
EPROMs, the 27C220 programs quickly using Intel's industry leading Quick-Pulse Programming algorithm.
DATA OUTPUTS
Vee <>-0--••
GND<>-o--••
Vpp 0
00-0 15
•
OUTPUT BUFFERS
V-GATING
AO-A16
ADDRESS
INPUTS
X
DECODER
2,097,152-BIT
CELL MATRIX
290217-1
Figure 1. Block Diagram
5-164
October 1990
Order Number: 290217-005
inter
Pin Names
I
lAo-A,R ADDRESSES
CE
CHIP ENABLE
~
OUTPUT ENABLE
00.0 ,5 OUTPUTS
PROGRAM
PGM
NC
NO INTERNAL CONNECT
27C220
27C220
4M
1M
1M
4M
Vpp
Vpp
Vee
Vee
Vee
CE
CE
PGM
PlThi
015
0,4
0,3
0,2
0,5
0,4
0 ,3
0 ,2
A"
A,.
NC
A'7
A,S
0"
0,0
09
0"
0,0
09
A"
All
A'5
A'4
A'3
A'2
A"
A'0
A'5
A'4
A 3
'
A'2
A"
A'0
00
00
GND
GND
A"
A"
A,o
O.
GND
07
Or
Or
Os
05
04
03
02
0,
00
Os
05
04
03
02
0,
00
~
C5E
A~
A~
GND
GND
Aa
A7
As
A5
Aa
A7
A,
0,
A7
A,
A,
A.
A3
.,
Az
0,
'0
OE
~
A3
A2
A,
Ao
As
A5
~
A3
A2
A,
An
290217-2
Figure 2. DIP Pin Configurations
44 LEAD PLCC
0.650" x 0.650"
TOP VIEW
290217-14
Figure 3. PLCC Lead Configuration
5-165
27C220
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change' without notice.
Operating Temperature .......•..... O°C to 70°C(1)
Temperature Under Bias ........... -10°C to 80°C
Storage Temperature ......... '.... - 65°C to 125°C
Voltages on Any Pin '
(except A9, Vee and Vpp)
with Respect to GND .......... - O.6V to 6.5V(2)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These' are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Voltage on A9 with
Respect to GND ............. - 0.6V to 13.0V(2)
Vpp Supply Voltage
with Respect to GND ........... ~ 0.6V to 14V(2)
Vee Supply Voltage
with Respect to GND ........... ,~ 0.6V to 7.0V(2)
READ OPERATION DC CHARACTERISTICS
Vee
Symbol
Typ
Parameter
Notes
Min
5.0V ±10%
Max
Unit
Test Condition
=
III
Input Load Current
1.0
p.A
VIN
ILO
Output Leakage Current
±10
p.A
VOUT
IS8
Vee Standby Current
1.0
rnA
CE
p.A
CE
=
=
VIH
100
50
rnA
CE
=
VIL
lee
Vee Operating Current
7
=
0.01
3
OV to Vee
=
OV to Vee
Vee ±0.2V
f = 5 MHz, lOUT = 0 rnA
Ipp
Vpp Operating Current
los
Output Short Circuit Current
VIL
Input LowVoltage
-0.5
VIH
Input HighVoltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Vpp
Vpp Operating Voltage
3
4,6
10
p.A
100
rnA
0.8
V
Vee
+ 0.5
0.45
2.4
5
Vee - 0.7
=
Vee
V
V
V
Vee
Vpp
= 2.1 rnA
10H = - 400 p.A
10L
V
NOTES: ,
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -O.SV on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + O.SV which, during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. Maximum active power usage is the sum Ipp + Icc. Maximum current is with outputs 00 to 015 unloaded.
4. Output shorted" for no more than one second. No more than one output shorted at a time.
S. Vpp may be connected directly to Vee, or may be one diode voltage drop below Vee. Vee must be applied simultaneously
or before Vpp and removed simultaneously or after Vpp.
6. Sampled, not'100o;.,'tested.
7. Typical limits are at Vee = SV, TA = 2Soe.
5-166
intJ
27C220
READ OPERATION AC CHARACTERISTICS(1)
Versions(4)
Symbol
=
5.0V ±10%
27C220-200V 10
P27C220-200V 10
N27C220-200V10
27C220-150V10
Vcc ±10%
Parameter
vcc
Notes
Min
Max
Min
Units
Max
tAcC
Address to Output Delay
tCE
CE to Output Delay
2
150
200
tOE
OE io OuifJui ut:liaY
2
'1':"1"1.
70
tOF
OE High to Output High Z
3
tOH
Output Hold from _
Addresses, CE or OE
Change-Whichever is'First
3
150
200
ns
ns
VV
50
,,~
60
0
ns
0
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. DE may be delayed up to tCE-tOE after the falling edge of CE without impact on tCE.
3. Sampled, not 100% tested.
4. Model Number Prefixes: No Prefix = CERDIP, P = PDIP, N = PLCC.
5. Typical limits are for TA = 25°C and nominal supply voltages.
CAPACITANCE(3)
Symbol
GIN
GOUT
Cvpp
TA
=
=
25°C, f
1MHz
Parameter
Typ(5)
Max
Unit
Input Capacitance
Output Capacitance
4
8
12
25
pF
Vpp Capacitance
AC INPUT/OUTPUT REFERENCE WAVEFORM
8
18
pF
pF
Conditions
VIN
= OV
VOUT = OV
Vpp = OV
AC TESTING LOAD CIRCUIT
1.3V
2.4
0.45
2.0>'
____
TEST POINTS _ _
0.8
2.0
lNB14
OUTPUT
__
~0.8=--
RL
290217-6
DEVICE
UNDER
TEST
AC test inputs are driven at VOH (2.4 VTTL) for a logic "1" and
VOL (0.45 V-riLl for a logic "0". Input timing begins at VIH (2.0
VnLl and VIL (O.B VnLl. Output timing ends at VIH and VIL' Input
rise and fall times (10% to 90%) ,;; 10 ns.
CL=100pF
CL Includes Jig Capacitance
RL = 3.3 kll
5-167
""'OUT
i-
eL
290217-7
27C220
AC WAVEFORMS
V," _ _ _ __
ADOIIEIIS
ADOIIUSES
VALID
V,, _ _ _ __
v," _ _ _ _ _-+__
I-v," _ _ _ _ _-+___
_- l c e - - - i
v,"
~
_____
H~IG~H~Z
____
HIGHZ
~~~r<
290217-8
DEVICE OPERATION
The Mode Selection table lists 27C220 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, ~nd Ag during inteligent Identifier Mode, are TTL or CMOS.
Table 1. Mode Selection
Mode
Notes
Read
1
Output Disable
Standby
OE
PGM
VIL
VIL
X(I)
VIL
VIH
X
CE
Au
Vpp
X
X
Vee
Vee
DOUT
X
X
Vee
Vee
HighZ
Ag
Vee
Outputs
VIH
X
X
X
X·
Vee
Vee
HighZ
VIL
VIH
VIL
X
X
Vpp
Vep
DIN
Program Verify
VIL
VIL
VIH
X
X
Vpp
Vep
DOUT
Program Inhibit
VIH
X
X
X
X
Vpp
Vep
HighZ
VIL
VIL
X
VIO
VIL
Vee
Vee
0089H
VIL
VIL
X
VIO
VIH
Vee
Vee
22EEH
Program
inteligent
Identifier
2
I Manufacturer
I Device
2,3
NOTES:
1. X can be VIL or VIH
2. See DC Programming Characteristics for Yep, Vpp and VIO voltages.
3. Al-As. Al0-A16 = VIL
5-168
intJ
27C220
~m
margin is ensured. The verify is performed with
CE at-.Yu.. and PGM at VIH. Valid data is available tOE·
after OE falls low.
Read Mode
The 27C220 has two control functions; both must be
enabled to obtain data at the outputs. CE is the powe(control arid device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACC> equals the
delay from CE to output (tCE). Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.
Program Inhibit
Program Inhibit Mode allows 'parallel pr29!"amming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE, parallel EPROMs may have common inputs.
Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.
inteligent Identifier™ Mode
Two Line Output Control
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power dissipation
b) complete assuranc~ that data bus contention will
not occur
To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.
Standby Mode
Standby Mode substantially reduces Vce current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.
Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
Program Mode is entered when Vpp is raised to
12.75V. Data is introduced by applying a 16-bit word
to the output pins. Pulsing PGM low while CE = VIL
and OE = VIH programs that data into the device.
Program Verify
A verify should· be performed following a program
operation to determine that bits have been correctly
programmed. With VCC at 6.25V, a substantial pro-
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
This mode is activated when a programmer forces
12V ± 0.5V on Ag. With CE, OE, A1-Aa, and A1OA16 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.
UPGRADE PATH
Future upgrade to the 4-Mbit density is easily accomplished due to the standardized pin configuration of the 27C220. When the 27C220 is in Read
Mode, the PGM input becomes non-functional. This
allows address line A17 to be routed directly to this
input in anticipation of future density upgrades. Systems designed for 2-Mbit program memories today
can be upgraded to 4-Mbit in the future with no circuit board changes.
SYSTEM CONSIDERATIONS
EPROM power switching characteristics require
careful device decoupling. System deSigners are interested in 3 supply current issures: standby current
levels (ISB), active current levels (IcC>, and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 ,...F ceramic capacitor
connected between its Vcc and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 ,...F electrolytic
capacitor should be placed at the array's power supply connection between Vec and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.
5-169
inter
.
"",
27C220
"
290217-9
Figure 4. Quick-Pulse Programming™ Algorithm
aged if the integrated dose exceeds 7258 Wsec/
cm 2 (1 week @ 12000 fJ-W/cm2).
ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
. Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase
an EPROM in approximately 3 years, 'while it takes
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelength 2537A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 fJ-W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can' be permanently dam-
Quick-Pulse Programming™ Algorithm
The. Quick-Pulse programming algorithm programs
Intel's 27C220. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C220 as fast as 15 seconds. Actual programming time depends on programmer' overhead.
,
The Quick-Pulse programming algorithm employs a
100 fJ-s pulse followed by a word verification to determine when the addressed word has been successfully programmed. The algorithm terminates if
25 attempts fail to program.a word.
The entire program pulse/word verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all words are compared to the original data with Vee = Vpp = 5.0V~
5-170
27C220
DC PROGRAMMING CHARACTERISTICS
Symbol
Parameter
III
Input Load Current
Icp
Vcc Program Current
Ipp
Vpp Program Current
TA
Notes
=
Min
25°C ± 5°C
Typ
Max
Unit
1
p.A
VIN
1
50
mA
CE
1
50
mA
CE
VIL
Input Low Voltage
-0.1
1__ ..... IB_L.. \1_1.1. _ _ _
VIH
IIIIJU\ I II!::III
2.4
VOL
Output Low Voltage (Verify)
VOH
Output High Voltage (Verify)
3.5
VIO
Ag inteligent Identifier Voltage
11.5
12.0
12.5
2,3
12.5
12.75
13.0
V
2
6.0
6.25
6.5
V·
v VILCl!::l"""
Vpp
Vpp Program Voltage
Vcp
Vcc Supply Voltage (Program)
AC PROGRAMMING CHARACTERISTICS(4)
Symbol
Parameter
Test Condition
0.8
V
6.5
\j
0.45
V
10L
V
10H
= VIL or VIH
= PGM = VIL
= PGM = VIL
= 2.1 mA
= -2.5 mA
V
TA = 25°C ±5°C
Notes
Min
tvcs
Vcp Setup Time
2
2
p.s
tvps
Vpp Setup Time
2
2
p.s
teES
CE Setup Time
2
p.s
tAS
Address Setup Time
2
p.s
tos
Data Setup Time
2
p.s
tpw
PGM Program Pulse Width
tOH
Data Hold Time
toES
OE Setup Time
tOE
Data Valid from OE
tOFP
OE High to Output High Z
tAH
95
Typ
100
Max
105
2
5,6
. Address Hold Time
0
0
p.s
p.s
2
5
Unit
p's
150
ns
130
ns
p.s
NOTES:
1. Maximum current is with outputs 00-015 unloaded.
2. Vcp must be applied simultaneously or before Vpp and removed simultaneously or aiter Vpp.
3. When programming, a 0.1 f-tF capacitor is required across Vpp and GNO to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. tOE and tOFP are device characteristics but must be accommodated by the programmer.
6. Sampled, not 100% tested.
5-171
intJ
27C220
PROGRAMMING WAVEFORMS
VERIFY
PROGRAM
V'M
ADDRESSES
)
ADDRESS STABLE
-
VOl
I--'AS _ _
V'H
HIGHZ
V,L
1--'05 _ _
_'AM
DATA OUT VALID
DATA IN STABLE
DATA
X
.'OM~
~
IOFP
12.75V
,---1
.Vpp
5.OV
_'vPS _ _
8.25V
Vee
/
5.0V-
l-'ve5_
V'M
Ce
VOl
\
_'CES _ _
V'H
M
PGM
VOl
V'H
Oil
f4-
'O'S1.
"\
VOl
f4-
'0'
290217-10
REVISION HISTORY
O,scrlptlon
Deleted -150 PDIP, PLCC packages
5-172
27C240
4M (256K x 16) CHMOS EPROM
• JEDEC Approved EPROM Pinout
-40-Pln DIP
• Versatile EPROM Features
- CMOS and TTL Compatibility
- Two Line Control
• Fast Programming
- Quick-Pulse Programmlng™
Algorithm
- Programming Times as Fast as 30
Seconds
!! I-Ilnh_PArfnrmlllnt.!A
::'1'70 ns -i10%' vcc
- 50 mA Icc Active
Intel's 27C240 is a 5V only, 4,194,304-bit Erasable Programmable Read Only Memory, organized as 262,144
words of 16 bits each. It provides for a simple upgrade from 1 and 2 Mbits.
The 27C240 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled
performance. Its 170 ns speed (tACe) optimizes operation with high performance CPUs in applications ranging
from numerical control to office automation to telecommunications.
The 27C240 is equally at home in both a TTL or CMOS environment. And like Intel's other high density
EPROMs, the 27C240 programs quickly using Intel's industry leading Quick-Pulse Programming™ algorithm.
CHMOS Is a patented process of Intel Corporation.
DATA OUTPUTS
00-0 15
---l".
---l".
vee
0-0
GND
0-0
VPPO
I
..
l:E
OUTPUT BUFfERS
V·GATING
AO"A17
ADDRESS
INPUTS
X
DECODER
4,194,304-BIT
CELL MATRIX
290229-1
Figure 1. Block Diagram
5-173
October 1990
Order Number: 290229-004
27C240
Pin Names
Ao-A17
CE
OE
00-0 15
PGM
NC
ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
OUTPUTS
PROGRAM
NO INTERNAL CONNECT
27C240
2M
1M
1M
2M
Vpp
Vpp
vee
Vee
Vee
CE
015
014
013
012
011
010
Os
Oe
GND
07
Os
05
04
03
02
01
00
OE
CE
015
014
013
012
011
010,
Os
Oe
GND
07
Os
05
04
03
02
01
00
OE
A17
A16
A15
PGM
NC
A15
A14
A13,
A12
All
Al0
As
GND
Ae
A7
As
A5
A4
A3
A2
Al
Ao
PGM
A1S
A15
A14
A13
A12
All
Al0
As
GND
Ae
A7
As
A5
A4
A3
A2
Al
Ao
0 13
A13
A12
A11
AID
°12
°10
°9
Os
As
GND
GND
°7
°6
°5
As
A7
A6
A5
A4
A3
A2
AI
AD,
O~
°3
°2
°1
00
OE
290229-2
Figure 2. DIP Pin Configuration
5-174
27C240
ABSOLUTE MAXIMUM RATINGS*
-NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
.
change without notice.
Operating Temperature ............. O°C to 70°C(1)
Temperature Under Bias ........... -10°C to BO°C
Storage Temperature ............. - 65°C to 125°C
Voltage on Any Pin
(except Ag, Vee and Vpp)
with Respect to GND .......... - 0.6V to 6.5V(2)
Voltaae on Aa with
Respectto-GND ............. -0.6Vto 13.0V(2)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation' beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Vpp Supply Voltage
with Respect to GND ........... -0.6V to 14V(2)
Vee Supply Voltage
with Respect to GND .......... -0.6V to 7.0V(2)
READ OPERATION DC CHARACTERISTICS
Symbol
Parameter
III
Input Load Current
ILO
Output Leakage Current
IS8
Vee Standby Current'
lee
Vee Operating Current
Notes
Min
7
Vee = 5.0V ±10%
Typ
0.01
Max
Units
Test Condition
J-LA
VIN
J-LA
VOUT
1.0
mA
CE
100
J-LA
CE
50
mA
CE
3
f
Ipp
Vpp Operating Current
los
Output Short Circuit Current
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Vpp
Vpp Operating Voltage
3
10
J-LA
4,6
100
mA
O.B
V
Vee
+ 0.5
0.45
2.4
5
Vee - 0.7
=
1.0
±10
Vpp
=
=
=
OV to Vee
VIH
Vee ±0.2V
VIL
5 MHz, lOUT
=
=
0 mA
Vee
V
V
V
Vee
=
OV to Vee
=
= 2.1 mA
10H = - 400 J-LA
10L
V
NOTES:
1. Operating temperature. is for commercial product defined by this specification.
2. Minimum De voltage is -O.SV on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vcc + O.SV which, during transitions, may overshoot to Vcc + 2.0V
for periods <20 ns.
.
3, Maximum active power usage is the sum Ipp + ICC. Maximum current is with outputs 00 to 015 unloaded.
4. Output shorted for no more than one second. No more than one output shorted at a time.
S. Vpp may be connected directly to Vcc, or may be one diode voltage drop below Vee. Vee must be applied simultaneously
.
or before Vpp and removed simultaneously or after Vpp.
6. Sampled, not 100% tested.
7, Typical limits are at Vee = SV, TA = 2Soe.
5-175
•
27C240
READ OPERATION AC CHARACTERISTICS(1) vcc
I
Verslons(4)
Symbol
Vee ± 10%
Parameter
Address to Output Delay
tCE
CE to Output Delay
DE to Output Delay
tOF
OE High to Output High Z
3
toH
Output Hold from Addresses,
CE or DE Change-Whichever
is First
3
. toE'
5.0V ±10%
27C24Q-200V10
Min
Min
Units
Notes
tACC
=
27C24Q-170V10
Max
Max
170
200
ns
2
170
200
ns
2
65
70
ns
60
ns
55
0
0
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. DE may be delayed up to tCE-toE after the falling edge of CE without impact on teE.
3. Sampled, not 1000;. tested.
4. Model number prefixes: No Prefix = Ceramic Dip.
5. Typical limits are for TA = 25°C and nominal supply voltages.
CAPACITANCE(3)
TA
=
f = 1 MHz
25°C,
Typ(5)
Max
Unit
CIN
Input Capacitance
4
8
pF
COUT
Output Capacitance
8
12
pF
Cvpp
Vpp Capacitance
18
25
pF
Symbol
Parameter
AC INPUT/OUTPUT REFERENCE WAVEFORM
Conditions
= OV
= OV
Vpp = OV
VIN
VOUT
AC TESTING LOAD CIRCUIT
1.3V
2.4
0.45
2.0>
0.8
___
TEST POINTS ----...
!IN914
2.0
OUTPUT
,,0_..8......._ _
RL
290229-3
DEVICE
UNDER
TEST
AC test inputs are driven at VOH (2.4 VTTU for a logic "1" and
VOL (0.45 VTTU for a logic "0". Input timing begins at VIH
(2.0 VTTU and VIL (0.8 VTTd. Output timing ends at VIH and VIL.
Input rise and fall times (10% to 90%) ,;10 ns.
OUT
,
CL = l00pF
CL Includes Jig Capacitance
RL = 3.3 Kfl
5-176
i-
CL
290229-4
intJ
27C240
AC WAVEFORMS
V'H----_
ADDRESS
ADDRESSES
V,, _ _ _ __
V'H -
VALID
_ _ _ _-+-....
1--
v"
V'H _ _ _ _ _-+____
to.
V'M
OUTPUTS _ _ _ _--'H;;;;IG;;;,;H~Z_ _ _ __+H~r_<
HIOHZ
v"
290229-5
DEVICE OPERATION
The Mode Selection table lists 27C240 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vee and Vpp, and A9 during inteligent IdentifierTM Mode, are TTL or CMOS.
Table 1. Mode Selection
Mode
Notes
CE
OE
Ag
Ao
Vpp
Vee
X
Outputs
VIL
VIL
X
Vee
Vee
DOUT
Output Disable
VIL
VIH
X
X
Vee
Vee
HighZ
Standby
VIH
X
X
X
Vee
Vee
HighZ
1
Read
2
Program
Program Verify
Program Inhibit
inteligent
Identifier
I
I
Manufacturer
Device
2,3
VIL
VIH
X
X
Vpp
Vep
DIN
VIH
VIL
X
X
Vpp
Vep
DOUT
VIH
VIH
X
X
Vpp
Vep
HighZ
VIL
VIL
VID
VIL
Vee
Vee
0089H
VIL
VIL
VID
VIH
Vee
Vee
44EEH
NOTES:
1. X can be VIL or VIH
2. See DC Programming Characteristics for VcP. Vpp and VIO voltages.
3. A1-AS. AlO-A17. = VIL
5-177
intJ
27C240
programmed. With Vcc at 6.2SV, a substantial program margin is ensured. The verify is performed with
CE at VIH. Valid data is available tOE after OE falls
~Iow.
.
Read Mode
The 27C240 has two control functions; both must be
enabled to obtain data at the outputs. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACe) equals the
delay from CE to output (tCE)' Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.
Program Inhibit
Program Inhibit Mode allows parallel pr~amming
of multiple EPROMs with different data. CE-high inhibits programming of non-targeted devices. Except
for CE and OE, parallel EPROMs may have common
inputs.
Vee must be applied simultaneously or before
Vpp and removed simultaneously or after Vpp.
inteligent Identifier™ Mode
Two Line Output Control
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with it's proper programming algorithm.
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur
This mode is activated when a programmer forces
12V ± O.SV on Ag. With CE, OE, A1-AB, and A1OA17 at VIL, Ao = VIL will present the manufacturer
code and Ao = VIH the device code. This mode
functions in the 2SoC ± SoC ambient temperature
range required during programming.
To efficiently use these two control inputs, an address decoder should enable CE, while OE should
be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while
deselected memory devices are in Standby Mode.
SYSTEM CONSIDERATIONS
Standby Mode
Standby Mode substantially reduces Vcc current.
When CE = VIH, the outputs are in a high impedance state, independent of OE.
Program Mode
Caution: Exceeding 14Von Vpp will permanently
damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" are programmed, the data word
can contain both "1 s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
EPROM power switching characteristics require
careful device decoupling. System designers are interested in 3 supply current issues: standby current
levels (Iss), active current levels (ICe), and transient
current peaks produced by falling and rising edges
of CEo Transient current magnitudes depend on the
device output's capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 fLF ceramic capacitor
connected between its Vce and GND. This high frequency, low inherent-inductance capacitor should
be placed as close as possible to the device. Additionally, for every 8 devices, a 4.7 p,F electrolytic
capacitor should be placed at the array's power supply connection between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC
board trace inductances.
ERASURE CHARACTERISTICS
Program Mode is entered when Vpp is raised to
12.7SV. Data is introduced by applying a 16-bit word
to the output pins. Pulsing CE low while OE = VIH
programs that data into the device.
Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000A-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase
an EPROM in approximately 3 years, while it takes
S-178
27C240
290229-6
Figure 3. Quick-Pulse Programming Algorithm
approximately 1 week when exposed to direct sunlight. If the device is exposed to these lighting conditions for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light cif wavelength 2537A. The integrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 p.W/cm2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsec/
cm 2 (1 week @ 12000 p.W/cm2).
Quick-Pulse Programming Algorithm
The" Quick-Pulse Programming algorithm programs
Intel's 27C240. Developed to substantially reduce
programming throughput, this algorithm can program
the 27C240 as fast as 30 seconds. Actual programming time depends on programmer overhead.
The Quick-Pulse Programming algorithm employs a
100 p.s pulse followed by a word verification to determine when the addressed word has been successfully programmed. The algorithm terminates if
25 attempts fail to program a word.
The entire program pulse/word verify sequence is
performed with Vpp = 12.75V and Vee = 6.25V.
When programming is complete, all words are compared to the original data with Vee = Vpp = 5.0V.
5-179
27C240
DC PROGRAMMING CHARACTERISTICS
Symbol
Parameter
III
Input Load Current
Icp
Vcc Program Current
Ipp
Vpp Program Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage (Verify)
VOH
Output High Voltage (Verify)
VIO
Ag inteligent Identifier Voltage
Vpp
Vpp Program Voltage
Vcc
Vcc Supply Voltage (Program)
TA = 25°C ±5°C
Notes
-
Min
Parameter
Max
Unit.
Test Condition
1
/LA
VIN
1
50
mA
CE
1
50
mA
-0.1
0.8
V
2.4
6.5
V
0.45
V
10L
V
10H
3.5
11.5
12.0
12.5
V
2,3
12.5
12.75
13.0
V
2
6.0
6.25
6.5
V
AC PROGRAMMING CHARACTERISTICS(4)
Symbol
Typ
= VIL or VIH
= VIL
CE = VIL
= 2.1 mA
= -2.5mA
TA =. 25°C ±5°C
Notes
Min
Typ
Max
Unit
tvcs
VCP Setup Time
2
2
p.s
tvps
Vpp Setup Time
2
2
p.s
2
p.s
tAS
Address Setup Time
tos
Data Setup Time
,2
tpw
CE Program Pulse Wi9th
95
tOH
Data Hold Time
2
p.s
tOES
OE Setup Time
2
p.s
toE
Data Valid from OE
tOFP
OE High to Output High Z
tAH
Address Hold Time
5
5,6
0
0
p.s
100
105
p.s
150
ns
130
ns
p.s
NOTES:
1. Maximum current is with outputs 00-015 unloaded.
2. Vep must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 /LF capacitor is required across Vpp and GNO to suppress spurious voltage transients which
can damage the device.
4. See AC Input/Output Reference Waveform for timing measurements.
5. tOE and tDFP are device characteristics, but must be accommodated by the programmer.
6. Sampled, not 100% tested.
5-180
inter
. 27C240
PROGRAMMING WAVEFORMS
VERIFY
PROGRAM
v,.
ADDRESSES
V"
~
,
DATA
ADDRESS STABLE
-
~'AS~
~
J
f.--'DS __
I--'A.
HIOiHZ
DATA OUT VALID
DATA IN STABLE
1.
~-
---
f.'D••
tOFF>
>-
12.7SV
,---.I I--'VP5___
v••
5.0V
8.25V
Vee
,---.I f---',es_
S.OV
V,.
V,
DE
H
.
~'DES~
"\
V, L
I+-
'e.
290229-7
REVISION HISTORY
Number
04
DescrIptIon
Deleted -150 speed bin
5-181
27C400
4M (256K x 16 or 512K x 8) CHMOS EPROM
or Byte-Wide Configurable
• Word-Wide
4M 40-Pin Mask ROM Compatible
• - 40-Pin CERDIP Package
Dissipation
• -Low50Power
mA Max Active
5 MHz
• -High150Performance
ns Maximum Access Time
-Vcc
5V ±10%
=
•
• UV Erasable
Quick-Pulse Programming™ Algorithm
- Programming as Fast as 28 Seconds
@
-100 /-LA Max Standby
Intel's 27C400 is a 5V-only, 4,194,304 bit, Erasable Programmable Read Only Memory. It employs advanced
CHMOS' III-E circuitry for systems requiring low power, high speed performance and noise immunity.
The device is organized as 262,144 words of 16 bits or 524,288 bytes of 8 bits through use of a byte enable
switch on pin 31. The 27C400 is pinout and functionally compatible with 40-pin 4M Mask ROMs, providing a
solution for both prototyping and production applications.
The 27C400 is offered in a ceramic DIP package. The UV-erasable CERDIP package facilitates fast time-tomarket in minimum quantities with migration to mask ROMs for volume production. The Quick-Pulse Programming algorithm provides fast, reliable programming.
'CHMOS is a patented process of Intel Corporation.
DATA OUTPUTS
0 0 -0 15
VccOO---+~
Vpp
Oo---+~
GNDO""'·--+~
A-1
DE
CE
BYTE
OUTPUT ENABLE
CHIP ENABLE
.
AND
.
OUTPUT
BUFFERS
PROGRAM LOGIC
Y GATING
Y DECODER
AO-A 17
ADDRESS
INPUTS
4,194.304 BIT
X DECODER
CELL MATRIX
290273-1
Figure 1. 27C400 Block Diagram
5-182
November 1990
Order Number: 290273-002
inter
27C400
Pin Names
8Mb
Ao-A18
ADDRESSES
00-0 15
OUTPUTS
OE
OUTPUT ENABLE
CE
CHIP ENABLE
BYTE
WORD/BYTE ENABLE
A.-1
BYTE SELECT
NC
NO CONNECT
4Mb
4Mb
Mask ROM
Mask ROM
27C400
8Mb
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
Ao
CE
GND
OE
~
A3
A2
A1
Ao
CE
GND
OE
00
Os
01.
Og
00
Os
01
Og
°7
°0 6
02
010
03
011
02
010
03
011
Os
AS
A17
A7
A6
A5
A8
Ag
A8
Ag
AlO
A11
A12
A13
A14
A15
A16
BYTE
GND
0.
015 /A-1
07
014
06
013
05
012
0-'1
A10
A11
A12
A13
A14
A15
A16
BYTElVpp
GND
015 /A -1
07
014
06
013
05
012
04
Vee
Vee
Vee
Ag
A 10
All
A12
A 13
AI.
A1S
A 16
8YTE/Vpp
GNO
°lS/A-l'
1•
0 13
0 12
290273-2
Figure 2. DIP Pin Configuration
5-183
inter
27C400
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.
Operating Temperature ............. O·C to 70'C(1)
Temperature under Bias ........... -1 O'C to 80'C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect deyice reliability.
Storage Temperature ............. - B5'C to 125'C
Voltage on Any Pin
(Except Ag, Vcc and BYTElVpp)
with Respect to GND ....•..... - O.BV to B.5V(2)
Voltage on Ag, with
Respectto GND •.......•...... -O.BV.to 13V(2)
BYTElVpp Program Voltage
with Respect to GND ........... - O.BV to 14V(2)
Vcc Supply Voltage
with Respect to GND ............ - O.BV to 7V(2)
READ OPERATION DC CHARACTERISTICS(1)Vcc =
Symbol
Parameter
III
Input Load Current
ILO
output Leakage Current
ISB
Vcc Standby Current
Icc
Vce Operating Current
Notes
Min
7
Typ
0.01
5
3
Ipp
Vpp Operating Current
loS
Output Short Circuit
Current
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
5.0V ±10%
Max
Unit
=
1.0
/LA
VIN
. ±10
/LA
VOUT
OVto Vcc
=
=
=
OVto Vcc
1.0
mA
CE
100
/LA
CE
50
mA
f = 5 MHz,
CE = VIL, lOUT
3
10
/LA
4,B
100
mA
0.8
V
Vec
+ 0.5
0.45
2.4
Test Condition
Vpp
=
VIH
Vce ± 0.2V
=
0 mA
Vcc
V
V
V
= 2.1 mA
10H = -400/LA
10L
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum DC voltage on input/output pins is Vce'+ 0.5V which, during transitions, may overshoot to Vce + 2.0V
for periods < 20 ns.
3. Maximum active power usage is the sum Ipp + Icc. Maximum current value is with outputs 00-015 unloaded.
4. outPt shorted for no more than one second. No more than one output shorted at a time.
5. BYT /Vpp = Vee ± 0.2V or GND ± 0.2V.
6. Sampled, not 100% tested.
7. Typical limits are at Vec = 5V, TA = 25'C.
5-184
inter
27C400
READ OPERATION AC CHARACTERISTICS(I)vcc
vee ±
Version(4)
Symbol
Parameter
Notes
Address to Output Delay
tCE
CE to Output Delay
Min
Unit
Max
ns
2
150
200
ns
2
60
70
ns
60
!"'!S
tOE
('"\t::
U;,..h +,... (",\, .+"' ,+ Ui"h 7
, "~II " ..... _
... ,t"' ........ ~ •• -
3
tOH
Output Hold from Addresses,
CE or OE ChangeWhichever Occurs First
3
....
Max
200
'--
-
Min
27C400-200V10
150
OE to Output Delay
'ut"
±10%
27C400-150V10(7)
10%
tACC
= 5.0V
50
0
0
ns
NOTES:
I. See AC Inpul/Output Reference Waveform for timing measurements.
2. OE may be delayed up to teE-toE after the falling edge of CE without impact on tCE'
3. Sampled, not 100% tested.
4. Model Number Prefixes: No Prefix = CERDIP.
5. Typical values are for TA = + 25°C and nominal supply voltages.
6. Includes Ols/A-l.
7. Both byte- and word-wide-read mode are available with the 27C400-200Vl0. 27C400-150VIO specs are valid only in
word-wide-read mode operation.
CAPACITANCE(3lTA =
Symbol
25°C, f
Parameter
= 1 MHz
Typ(5) Max Unit
Condition
CIN
Input Capacitance
4
8
pF
VIN
COUT
Output Capacitance(6)
8
12
pF
VOUT
Cvpp
VPP Capacitance
18
25
pF
VPP
AC INPUT/OUTPUT REFERENCE WAVEFORM
2.4",,-IN_P_UT_ ) (
J
0.45·
~:~
>
TE!T POINTS
;
<
2.0
0.8
=
=
OV
=
OV
OV
AC TESTING LOAD CIRCUIT
1.3V
OUTPUT
IN914
290273-5
AC test inputs are driven at VOH (2.4 VTTU for a Logic "I" and
VOL (0.45 VTTU for a Logic "0". Input timing begins at VIH (2.0
VTTU and VIL (0.8 VTTU. Output timing ends at VIH and VIL: Input
rise and fall times (10% to 90%) ,;; 10 ns.
t--+--oOUT
290273-6
CL ~ 100pF
CL Includes Jig Capacitance
RL ~ 3.3 kO
5-185
27C400
AC WAVEFORMS
Word-Wide Read Mode
AO- 17
V,H -
........ .,..------~,.----
V,L ...,...-J'.,....-~~~~-of'"----
V,H
0 0- 15
V·----=----C
IL
290273-7
NOTE:
BYTEIVpp = Vee
± O.2V
Byte-Wide Read Mode
A-l-A 17
V,H - - - .•
.Jo-------....,----
V,L --J'.,....-~~~~-of'"----
290273-8
NOTE:
BYTEIVpp
= GND ± O.2V
5-186
27C400
DEVICE OPERATION
The Mode Selection table lists 27C400 operating modes. Read Mode requires a single 5V power supply. All
inputs, except Vcc and BYTElVpp, and Ag during inteligent IdentifierTM Mode, are TIL or CMOS.
Table 1. Mode Selection
Mode
Read (Word)
BYTEI
Vpp(4)
Notes
CE
OE
Ag
Ao
015 /A - 1
1
VIL
VIL
X
X
D15 Out
Vee
Vee
VIL
VIL
X
X
VIH
GND
Vcc
HighZ
DS-15 Out
Read (Upper Byte)
Vee
08-14
00-7
D8-14 Out . DO-7 Out
Read (Lower Byte)
VIl.~
VIL
X
X
VIL
GND
Vcc
HighZ
DO-7 Out
Output Disable
VIL
VIH
X
X
HighZ
X
Vcc
HighZ
HighZ
VIH
X
X
X
HighZ
X
Vcc
HighZ
HighZ
VIL
VIH
X
X
D15 1n
Vpp
Vcp
DS-14In
X
D15 Out
Vpp
Vcp
DS-14 Out
DO-7 Out
X
HighZ
Vpp
Vcp
HighZ
HighZ
Vcc
Vcc
OOH
89H
Vcc
Vcc
44H
EFH
Standby
Program
2
Program Verify
VIH
VIL
X
Program Inhibit
VIH
VIH
X
inteligent Identifier
-Manufacturer
-Device
2,3
VIL
VIL
VID
VIL
OB
VIL
VIL
VID
VIH
OB
DO-7 In ·
NOTES:
1. X can be VIL or VIH.
2. See DC Programming Characteristics for VcP. Vpp and VIO voltages.
3. A,-A6. A,o-A17 = VIL.
4. BYTElVpp is intended for operation under DC Voltage conditions only.
Read Mode
Two Line Output Control
The 27C400 has two control functions; both must be
enabled to obtain data at the outputs. CE is the power control and device select. OE controls the output
buffers to gate data to the outputs. With addresses
stable, the address access time (tACC> equals the
delay from CE to output (tCE)' Outputs display valid
data tOE after OE's falling edge, assuming tACC and
tCE times are met.
EPROMs are often used in larger memory arrays.
Intel provides two control inputs to accommodate
multiple memory connections. Two-line control provides for:
Word-Wide Mode
With BYTElVpp at VCC ± 0.2V outputs 00-7 present data.QQ_7 an~utputs 0S-15 present data Ds15, after CE and OE are appropriately enabled.
a. lowest possible memory power dissipation
b. complete assurance that data bus contention will
not occur
To efficiently use these two control inputs, an address decoder should enable CE while OE should be
connected to all memory devices and the system's
READ control line. This assures that only selected
memory devices have active outputs while deselected memory devices are in Standby Mode.
Byte-Wide Mode
With BYTElVpp at GND ± 0.2V. outputs OS-15 are
tri-stated. If 015/A-1 = VIH, outputs 00-7 present
data bits DS-15. If 015/A-1 = VIL, outputs 00-7
present data bits DO-7.
Standby Mode
Standby Mode substantially reduces Vcc current.
When CE = VIH, outputs are in a high impedance
state, independent of OE.
Read Operation AC Characteristic specifications are
currently valid in byte-wide mode only when using
the 27C400-200V1 O. Please contact your local Intel
sales office for additional information.
5-187
intJ
27C400
tion of the 27C400. Simply design in the 27C400
using pins 2-41 of a 42-pin socket. Route address
line A18 directly to pin 1 in anticipation of future den~
sity upgrades. See Figure 2 for additional information. Systems designed for 4M-bit program memories today can be upgraded to 8M-bit in the future
with no circuit board changes.
Program Mode
Caution: Exceeding 14V on BYTE/Vpp .will
permanently damage the device.
Initially, and after each erasure, all EPROM bits are
in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although .only "Os" are programmed the data word
can contain both "1s" and "Os". Ultraviolet light erasure is the only way to change "Os" to "1s".
SYSTEM CONSIDERATIONS
Program Mode is entered when BYTElVpp is raised
to 12.75V. Data is introduced by applying a 16-bit
word to the .output pins. Pulsing CE low while OE =
VIH programs that data into the device.
Program Verify
A verify should be performed following a program
operation to determine that bits have been correctly
programmed. With Vee at 6.25V, a substantial pro9@m margin is ensured. The verify is performed with
CE at VIH. Valid data is available on 00-15 tOE after
OE falls low.
Program Inhibit
Program Inhibit mode allows parallel programming
of multiple EPROMs with different data. CE-high inhibi~rogran\ming of non-targeted devices. Except
for CE and OE, parallel EPROMs may have common
.
inputs.
inteligent IdentifierTM Mode
The inteligent Identifier Mode will determine an
EPROM's manufacturer and device type, allowing
programming equipment to automatically match a
device with its proper programming algorithm.
This mode is activated when a programmer forces
12V ±0.5V on Ag. With CE, OE, A1-A8, and A10A17 = VIL, Ao = VIL will present the manufacturer's
code and Ao = VIH the device code. This mode
functions in the 25°C ± 5°C ambient temperature
range required during programming.
UPGRADE PATH
Future upgrade to the 8M-bit density is easily accomplished due to the standardized pin configura-
,
EPROM power switching characteristics require
careful device decoupling. System designers are interested in three supply current issues-standby
currents levels (Iss), active current levels (IcC>, and
transient current peaks produced by falling and rising edges of CEo Transient current magnitudes depend on the device outputs' capacitive and inductive
loading. Two-Line Control and proper decoupling capacitor selection will suppress transient voltage
peaks. Each device should have a 0.1 /kF ceramic
capacitor connected between its Vee and GND. This
high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device.
Additionally, for every eight devices, a 4.7 /kF electrolytic capacitor should be placed at the array's
power supply connection between Vee and GND.
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductances.
ERASURE CHARACTERISTICS
Erasure begins when EPROMs are exposed to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain fluorescent lamps have wavelengths in the
3000-4000A range. Data shows that constant exposure to room level fluorescent lighting can erase an
EPROM in approximately 3 ·years, while it takes approximately 1 week when exposed to direct sunlight.
It the device is exposed to these lighting conditions
for extended periods, opaque labels should be
placed over the window to prevent unintentional erasure.
The recommended erasure procedure is exposure
to ultraviolet light of wavelengths 2537A. The intergrated dose (UV intensity x exposure time) for erasure should be a minimum of 15 Wsec/cm 2. Erasure
time is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 /kW/cm 2 power rating.
The EPROM should be placed within 1 inch of the
lamp tubes. An EPROM can be permanently damaged if the integrated dose exceeds 7258 Wsecl
cm 2 (1 week @ 12000 p,W/cm2).
5-188
inter
27C400
INCREMENT ADDRESS
290273-9
Figure 3. Quick-Pulse Programming Algorithm
Quick-Pulse Programming Algorithm
The Quick-Pulse Programming™ algorithm programs Intel's 27C400. Developed to substantially reduce programming throughput, this algorithm can
program the 27C400 as fast as 28 seconds. Actual
programming time depends on programmer overhead.
determine ,when the addressed word has been successfully programmed. The algorithm terminates if
25 attempts fail to program a word.
The entire program-pulse/word-verify sequence is
performed with BYTElVpp = 12.75V and Vee =
6.25V. When programming is complete, all words
are compared to the original data with Vee =
BYTElVpp = 5.0V.
The Quick-Pulse Programming algorithm employs a
100 }ks pulse followed by a word verification to
5-189
27C400
DC PROGRAMMING CHARACTERISTICS
Symbol
Parameter
III
Input Load Current
Icp
Vcp Program Current
Ipp
Vpp Program Current
T A = 25°C ± 5°C
' Min
Notes
Typ
Max
Unit
Test Conditions
1
p..A
1
50
rnA
1
50
rnA
= VIL or VIH
= VIL
CE = VIL
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.4
6.5
V
VOL
Output Low Voltage (Verify)
VOH
Output High Voltage (Verify)
VID
Ag inteligent Identifer Voltage
Vpp
Vpp Program Voltage
Vcp
Vcc Supply Voltage (Program)
0.45
3.5
Symbol
Parameter
CE
V
IOL
V
IOH
11.5
12.0
12.5
V
2,3
12.5
12.75
13.0
V
2
6.0
6.25
6.5
V
AC PROGRAMMING CHARACTERISTICS(4) TA =
VIN
= 2.1 rnA
= -2.5 rnA
25°C ± 5°C
Notes
Min
Typ
Max
Unit
tvcs
Vcp Setup Time
2
2
p..s
tvps
Vpp ,~etup Time
2
2
p..s
tAS
Address Setup Time
2
p..s
los
Data Setup Time
2
p..s
tpw
CE Program Pulse Width
95
tOH
Data Hold Time
2
tOES
OE Setup Time
tOE
Data Valid from OE
tDFP
OE High to Output High Z
tAH
Address Hold Time
100
105
p..s
2
5
5,6
p..s
150
0
0
p..s
130
ns
ns
p..s
NOTES:
1. Maximum current is with outputs 00-015,unloaded.
2. Vep must be' applied simultl;lneously or before Vpp and removed simultaneously or after Vpp.
3. When programming, a 0.1 ",F capacitor is required between Vpp and GNO to suppress spurious voltage transients, which
can damage the device.
.
4. See AC .input/Output Reference Waveform for timing measurements.
5. tOE and tDFP are device characteristics 'but must be accommodated by the programmer.
6. Sampled, not 100% tested.
5-190
27C400
PROGRAMMING WAVEFORMS
ADDRESSES
Y1H
Y 1L
Y 1H
°0-15
BYTE/Y pp
Y1L
Y 1H
Y1L
Y ee
CE
Y1H
Y 1L
Y1H
Y 1L
liE
Y 1H
Y1L
290273-10
5-191
27960CX
PIPELINED BURST ACCESS 1M (128K x 8) CHMOS· EPROM
4 Byte Data Burst Access
Pipellned Addressing for Optimal Bus
• Synchronous
•
Bandwidth on' 80960CA
No Glue Interface to 80960CA
• High
- Next Addressing Overlaps Last Data
Clock to Data Out
Byte
• - ZeroPerformance
Wait State Data to Data Burst
CHMOS
III-E for High Performance and
- Up to 33 MHz 80960CA Performance
• Low Power
Microcontroller Reset Function
-125 mA Active, 30 mA Standby
• -Asynch
Returns to Known State with Hlgh-Z
- TTL Compatible Inputs
Outputs
1 Mbit Density Configures as 128K x 8
• -Upgrade
Path to 512K x 8
Intel's 27960CX is a 5V only, 1,048,576 bit, Erasable Programmable Read Only Memory, organized as 128K
words of 8 bits. It is a member of a new family of high performance EPROMs with synchronous burst access.
The 27960CX provides a no glue synchronous burst interface to the 80960CA bus. Internally the 27960CX is
organized in 4 byte blocks, in which each byte is accessed sequentially. The internal state machine is factory
configured to generate either 1 or 2 wait-states between the address and first data byte. High performance
outputs provide zero wait-state data to data accesses at clock frequencies up to 33 MHz.
Pipelining capability allows addresses to overlap previous data, further optimizing bus bandwidth in 80960CA
applications. An asynchronous microcontroller RESET feature puts the outputs in the high impedance state
and takes the internal state machine to a known state where a new burst access can begin.
The 27960CX is available in' either 44-lead Cerquad (reprogram mabie) or PLCC packages. Cerquad allows for
code changes in the R&D environment while PLCC provides optimum cost effectiveness during production.
Two No Connects (NC) on the package allow for an upgrade to 4 Mbits (512K x 8).
The 27960CX is manufactured on Intel's 1 micron CHMOS III-E technology. The Quick-Pulse Programming™
algorithm provides fast, reliable programming with throughput uflder 17 seconds for optimized equipment.
'CHMOS is a Palenlenled Process of Inlel Corporation.
A l
D
A
D T
R C
E H
S
E
S
S
S
II
T A
A C
T H
ClK
E
I
N
E
290236-1
Figure 1. 27960CX Burst EPROM Block Diagram
5-192
January 1991
Order Number: 290236-004
inter
27960CX
27960CX BURST EPROM
Architecture
EPROMs are established as the preferred code storage device in embedded applications. The non-volatile, flexible, reliable, cost effective EPROM makes a
product easier to design, manufacture and service.
Until recently, however, EPROMs could not match
the performance needs of high-end systems. The
27960CX was designed to support the B0960CA embedded processor. It utilizes the burst interface to
otter near zero walt-state performance without the
high cost normally associated with this performance.
The 27960CX provides a no-glue, synchronous burst
interface to the B0960CA's bus. It operates in pipelined or non-pipelined modes. Internally, the
27960CX is organized in 4 byte blocks which are
accessed sequentially. A burst access begins on the
first clock pulse after ADS and CS are asserted. The
address of the 4 byte block is latched on the rising
edge of clock following ADS. After a preset number
OT wait-states (i or 2i, data is ouipui one oyie ai a
time on each subsequent clock cycle. A burst access is terminated on the rising edge of clock with
BLAST asserted. High performance outputs provide
zero wait-state data to data accesses at clock frequencies up to 33 MHz. Extra power and ground
pins dedicated to the outputs reduce the effects of
fast output switching on device performance.
In embedded designs, board space and cost must
be kept at a minimum without impacting performance and reliability. The 27960CX removes the need
for expensive high-speed shadow RAM backed up
by slow EPROM or ROM for non-volatile code storage. Code optimization concerns are reduced with
"off-chip" code fetches no longer crippling to system performance. FONTs can be run directly out of
these EPROMs at the same performance as highspeed DRAMs. With the 27960CX, the EPROM is
the ideal code or FONT storage device for your
B0960CA system.
The pipelining capability of the 27960CX allows the
address to overlap the last data byte of the burst,
further optimizing bus band width in 80960CA applications. In the pipelined mode, with a non-buffered
interface, the 27960CX delivers 4 bytes of data, in
6 clock cycles at 33 MHz. In a 32-bit configuration,
this translates into a read bandwidth of 88 Mbytes/
sec. Performance capability of the 27960CX in different 80960CA systems is given in Table I.
'CERQUAD is available in a socket only version.
ADDRESS
17
A
"v
~-
DATA
<
27960CX
'I
8
ADS
BLAST
BURST
EPROt.!
128K
x
8
RESET
ClK
PGt.!
290236-2
Figure 2. 27960CX Burst EPROM Signal Set
5-193
intJ
~OO[gIl.O~OOOIA\OOW
27960CX
Table 1. Performance Capability
33 MHz 2WS
AOOR
OATA
PCLK
Aoo
Cl
WS
C2
C3
25 MHz
AOOR
OATA
PCLK
Aoo
WS
Cl
C2
AOOR
OATA
. PCLK
Aoo
WS
C2
C3
000
C3
16MHz
AOOR
DATA
PCLK
Aoo
Cl
000
C4
2WS
001
Cs
000
C4
1 WS
001
C4
1 WS
000
C3
001·
C4
Aol
003
C7
WS
Cl
WS
010
C3
C~
A02
013
Cs
WS
012
Cs
A02
013
Cs
WS
. D12·
Cs
011
C4
Cl
Buffered: 4 Words/6 Clock Cycles ---+ 66 Mbytes/Sec
001
Cs
002
Cs
AOl
003
C7
WS
Cl
WS
D11
C4
010
C3
C2
Buffered: 4 Words/5 Clock Cycles ---+ 64 Mbytes/Sec
002
Cs
AOl
003
Cs
WS
Cl
010
C2
011
C3
·A02
WS
013
Cs
Cl
012
C4
Buffered: 4 W~rds/5 Clock Cycles ---+ 51 Mbytes/Sec.
WS
C2
002
Cs
WS
20 MHz
Cl
Non-Buffered: 4 Words/6 Clock Cycles ---+ 88 Mbytes/Sec
WS
002
Cs
AOl
003
(:s
WS
Cl
010
C2
011
C3
012
C4
A02
013
Cs
WS
Cl
A 16
A 15
A14
CJ27960CX
A 13
44 LEAD CERQUAD
A12
N27960CX
Al1
44 LEAD PLCC
A 10
Ag
0.650" x 0.650"
TOP VIEW
31
As
A7
A6
290236-3.
Figure 3. 27960CX 44 Lead PLCC/CERQU~D Pinout
5-194
Cl
inter
27960CX
/
PIN DESCRIPTIONS
Symbol
Pin
·Ao-A16
23-39
00- 0 7
6,7,10,
11, 13, 14,
17,18
ADS
42
Function
ADDRESS INPUTS: During a burst operation, A2-A16 provides the
base address pointing to a block of four consective bytes. Ao and A1
select the first byte of the burst access. The 27960CX latches
addressf;ls in the first clock cycle. An internal address generator
increments addresses Ao and A1 for subsequent bytes of the burst.
DATAINPUTS/OUTPUTS
ADDRESS STROBE: Indicates the start of a new bus access. ADS is
active low in the first clock cycle of a bus access.
CS
3
CHIP SELECT: Master device enable. When asserted (active low)
data can be written to and read from the device. In read mode, CS
enables the state machine and the 1/0 circuitry.
NOTE:
1. The address decode path is independent of CS, i.e., X and Y
decoding is always powered up.
2. For programming, CS should remain low for the entire cycle.
Program and verify functions are done one byte at a time.
3. CS going high does not terminate a concurrent burst cycle.
BLAST
1
BURST LAST: Terminates a concurrent burst data cycle at the riSing
edge of the ClK. It must be asserted by the fourth data byte.
RESET
22
ASYNCHRONOUS RESET INPUT: Resets the state machine into a
known state, tri-states the outputs and puts address latches into the
flow through mode. RESET must be asserted for a minimum of 10
clock cycles. At least 5 clock cycles are required after deassertion of
RESET before beginning the next cycle. RESET will abort a concurrent
bus cycle.
PGM
43
PROGRAM-PULSE CONTROL INPUT
Vpp
Vss
2
Vee
5,8,12,
15,19,21
9,16,20,44
PROGRAMMING POWER SUPPLY
GROUND
SUPPLY VOLTAGE INPUT
5-195
•
27960CX
on the address lines (due to the EPROM only) is
24 pF for a 128K x 32 system and 48 pF for a 256K x
32 system. The EPROM is specified at 6 pF for input
capacitance (15 pF max) and 12 pF typical for output capacitance. Larger systems Can be implemented with buffers (Figure 48).
INTERFACE EXAMPLE
Overview
This example illustrates 8-, 16- and 32-bit wide
27960CX interfaces to the 80960CA. The designs
offer a simple "no-glue" interface.
. Chip Select Logic
A non-buffered 27960CX system organized as 256K
x 32 is shown in Figure 4A. Since the 27960CX is
capable of driving a 80 pF load, large, non-buffered
systems can be implemented by stacking up to 2
banks of 4 EPROMs, resulting in a 256K x 32 memory subsystem. The input capacitive load seen
High order address lines are decoded .to provide CS.
Qualification with other signals is not required. The
chip select logic can be implemented with standard
asynchronous decoders, PAL's or PLO's(like Intel's
85C508).
cs
27960CX
128K
x
8
B0960CA
290236-4
Figure 4A. 256K x 32 Non-Buffered Burst EPROM Memory System
DEC
CS N
CS 2
CS,
-
cs
~~--
~
"
ADDRESS
~
j-1I
I'
'---
B0960CA
A
'4
DATA
r--A
XCVR
~~s_......
-""'-
ADDRESS
CS
CS
I
1CS cs
CS
27960CX
CS
27960CX
CS
27960CX
128K
x
8
128K
x
8
128K
x
8
~
J
J
r-
1-.
J
CS
~~-~
CS
CS
27960CX
128K
x
8
~
J
'4
'--290236-5
Figure 4B. Buffered Burst EPROM Memory System
5-196
inter
27960CX
In a non:buffered, 16-bit system (Figure 6A) BE1
and A2 connect to the lower order address bits of
the 27960CX. BE1 connects to Ao of both EPROMs,
while A2 connects to both A1 'so
Schematics
Figure 5 shows a non-buffered, 128K x 32 27960CX
EPROM system.
Chip select logic, the only external logic that is required for this interface, can be derived from the
global system chip select circuitry.
DECODER
(S5C5,OS)
ADDRESS
In a non-buffered, 8-bit system (Figure 6B) BEO and
BE1 connect to Ao and A1 respectively.
t---.-------.-------..--------.
cs
A2-A'8
cs
ADS
ADS
PClK
BLAST
S0960CA
es
Ao-A 16
Ao-A'6
17
27960CX
12SKxS
Ao-A'6
27960ex
ADS
27960ex
12SKxS
ClK
elK
ClK
BLAST
BLAST
BLAST
DATA
32
290236-6
Figure 5. 128K x 32 27960CX Burst EPROM System
-
A3-A 17
II.
/
15 V'
ADDRESS
ADS
A2
BEl
~
CS
--'\
~
27960CX
128K x 8
ClK
BLAST
A
A2-A '6
ADS
PClK
80960CA
cs
DECODER
(8SCS08)
CS
A2-A '6
ADS
27960ex
128K x 8
ClK
BLAST
BLAST
Al
Ao
Al
Ao
~O-D7
DATA
~S-DI5/
,
,
16
290236-7
Figure 6A. 27960CX Burst EPROM In a 16-Bit System
5-197
inter
21960CX
r-'
CS
DECODER
(85C508)
"
ADDRESS
A2-:A,6
''S
"
ADS
ADS
PClK
27960CX
128K x 8
ClK
BLAST
80960CA
CS
A2-A'6
Y'
BLAST
BEl
A,
BEO
Ao
~'
06- 0 7
It
,
DATA,
.-
/
J
8
"
290236-8
Figure 6B. 27960CX Burst EPROM in a a-Bit System
required. With the 80960CA's maximum valid address delay of 18 ns at 33 MHz, 7 ns remains for CS
decoding logic.
'
Waveforms
Figure 7 shows the timing waveforms of a 27960CX
pipelined read in a 32-bit system.
, Bootup
CS Setup Time
CS setup time is the time between CS being asserted and the first ClK rising edge (during the address
cycle). Since a memory access begins on the first
ClK risin~dge after ADS and CS are asserted, a
minimum CS setup time of 5 ns (tSVCH) at 33 MHz is
The Wait state configuration (1 or 2), of the 27960CX
is programmed by the user into the 80960CA Region
Table parameters of NRAD, NRDD, and NXDA.
NRDD is always 0 for the 27960CX.
5-198
inter
27960CX
ws
ws
elK
DATA
t---t--+---{
290236-9
NOTES:
1. The EPROM can also operate in non pipelined mode i.e, next address and ADS can be asserted in the clock cycle
following the last data word of the burst.
2. 2 - 0 - 0 - 0 Burst Read -+ 2 indicates the number of wait states to access the first word
O's indicate the number of wait states for subsequent data words:
o in this case!
3. 27960CX latches addresses on the falling edge of clock cycle 1 after sampling CS and ADS it has an internal address
generator which increments addresses for subsequent words of the burst. It ignores the states of A2, A3 and BEO-BE3
during a burst.
Figure 7. Two Cycles of a 27960CX 2 Wait State 4 Byte Read (2-0-0-0 Burst Read) in a 32 Bit System
During boot-up (Figure 8), the 80960CA picks up it's
Region Table data from addresses FFFF FFOO;
FFFF FF04; FFFF FF08 and FFFF FFOC. Only the
least significant byte of each of the above four 32-bit
accesses is used to configure the Region Table. For
boot-up, the wait-state parameters NRAD and NXDA
default to 31 and 3 respectively. During boot-up, the
27960CX will wrap around the first word of the fourword burst and hold the first word until BLAST is
asserted.
27960CX DEVICE NAMES
The device names on the 27960CX were derived as
mnemonics that correspond to the number of wait
states and expected operating frequency for the device. For example, the 25 MHz, 2 wait state
27960CX is named 27960C2-25.
AC TIMING DERIVATIONS
always assumed. The example below shows how
the 27960C2-33 tavcoh timing was derived.
@33 MHz the clock cycle is
~
30 ns.
tOV2 of the 80960CA is 3 ns - 16 ns.
Typical 2 ns guardband.
27960C2-33 tavcoh = 30 ns - 16 ns - 2 ns
=
12 ns
On timings where the EPROM is faster than the microprocessor, we specified the time required by the
EPROM and left the excess time as additional system guardband:
Decoders are needed for the systems chip select
decoding. For the 27960CX timings we assumed a
10 ns chip select decoder for 20 MHz and 16 MHz
and a 7 ns decoder for 25 MHz and 33 MHz
systems. The example below shows how the
27960C2-33 tsvch timing was derived.
The AC timings for the 27960CX were generated
specifically to meet the requirements of the
80960CA microprocessor. In each case the applicable 80960CA clock frequency and AC timing were
taken together with an address buffer delay (if needed) and a typical 2 ns guardband to generate the
27960CX AC timing. Worst case timings were
@33 MHz the clock cycle is
27960C2·33 tsvch
=
30 ns.
30 ns - 16 ns - 7 ns
= 7 ns
5·199
~
tOV2 of the 80960CA is 3 ns - 16 ns.
Decoder = 7 ns
l
D
PCLK
."
ADDR
!»
....
ADS
Q
0
(J1
N
0
0
><
.....
'~I
CS
cg
Q)
5
6
31
7
III
FFFF FF04
FFFF FFOO
\J
\~
1
FFFF FrOC
FFFF FF06
DATA
\J
\J
N
.....
CO
/ ' i--~
II
0
-
4
n. n. rI- n. n. n. n. tl rt tl tl tl n. n.n.n.n. rt rt n. n.n. n. n. n.n. n. n. n. n.n. n. tl tl tl n. rt n.n.n.n. ~
II III mn
mmmI
~] m
ml~
I
K
Q
>
g"
3
V'I
N
~I
2
~i\
iQ
...cCD
1
Ol
o
\
Ilmm m mOO~01~02~03~ ~
o
><
I FIRST BYTE WRAPPED AROUND
'00
nHI mm
04~05~06~07n
m
08~09~A~BY
m
III XXX
mOC~OD~OE~OF~
0
!-NWS 1
C
"C
~I
S-
IC
BLAST
NRAD = 31
I-NXDA=3-
1-2WS~
I-NXDA=3-
\lr
\V
\V
\V
W
1-2WS~
I-NXDA=3~
1-2WS~
290236-10
'@
2EJ
Iiiiil
F
~
~
~
2.§J
~
27960CX
6'
iii '"
>Vl
d
"I~ >
ClK
uOQUU
D....J
m
Q.
c:(
Z
Z
0 6 I-'l Vpp > VIL will cause a slight increase in standby current.
6. The device must be in the idle state (by asserting RESET or using BLAST) before going intp standby.
CAPACITANCE(1) TA
Symbol
= 25°C, f = 1.0 MHz
Parameter
Typ
Max
Unit
Condition
=
CIN
Input Capacitance
4
6
pF
VIN
COUT
Output Capacitance
12
15
pF
VOUT
Cvpp
Vpp Capacitance
40
45
pF
VIN
NOTE:
1. Sampled. Not 100% tested.
5-205
=
OV
=
OV
OV
inter
27960CX
AC INPUT/OUTPUT REFERENCE WAVEFORMS
. AC TESTING LOAD CIRCUIT.
1.5V
I
TIMING PARAMETER
_
--VOH
780.0.
1
DEVICE
UNDER
TEST
11--+_
i
OUTPUT
CL =80 Pf
'---VOL
290236-15
290236-14
CL includes jig capacitance
For tCHQZ CL = 5 pF and RL = 4050.
Input and output timings are measured from 1.5V.
Timing values are specified assuming maximum input
and output rise and fall time = 4 ns.
CLOCK CHARACTERISTICS
Versions
25 MHz
33 MHz
Symbol
Parameter
Min
30.3
Max
Min
20 MHz
Max
16 MHz
Max
Units
Max
ClK
Period
Rise Time
tpF
Fall Time
1
4
1
4
1
4
1
4
ns
tPL
low Time
(tl2) - 2
tl2
(tl2) - 3
t/2
(tl2) - 4
tl2
(tl2) - 4
tl2
ns
tpH
High Time
(tl2) - 2
tl2
(tl2) - 3
tl2
(tl2) - 4
tl2
(tl2) - 4
ti2
ns
.'
4
50
Min
tpR
1
40
Min
1
4
1
Max Rise Time for Programming ClK
62.5
4
= 100 ns
CLOCK WAVEFORM
i----CLK----i
290236-16
5-206
1
ns
4'
ns
inter
27960CX
Program/Program Verify
Initially, and after each erasure, all bits of the
EPROM are in the "1's" state. Data is introduced by
selectively programming "O's" into the desired bit
locations. Although only "O's" can be programmed,
both "1's" and "O's" can be present in the data
word. Ultraviolet erasure is the only way to change
"Dis" to "1 IS".
'.1._
n _______ : ____ -'_: ___ .1. _ _ _ ...1 _ •• L _ _ "
: ___ : ___
rluylQllllllllly IIIUU~ ' " CllLClt:;U VVIIV'II vpp 10:. I ClI:;'t:;;U LU
12.75V. ProgramlVerify operation is synchronous
with the clock and can only be initiated following an
idle state. Program and Program Verify take place in
3 clock cycles. In the first clock cycle, addresses
and data are input and programming occurs. Program Verify follows in the second clock cycle and
the third clock cycle terminates synchronous Pro~
gramlVerify operation, returning the state machine
to the idle state with outputs at high impedance.
The programmer can verify the device identifier and
choose the programming algorithm that corresponds
to the Intel 27960eX. The inteligent Identifier can
also be used to verify that the product is configured
with the desired Read mode options for wait states.
inteligent Identifier mode is entered when A9 (pin 32) ,
is raised to its high voltage (VID) level. The internal
state machine is then set for intelligent Identifier
Read operation. Reading the identifier is similar to a
0 ....... ...1 ................... +:"" ....... ""
................... _i ........... +............ _4': ............ ...1
",",,,\.1 "" .......... ICU.IVII VII Cl
VII~
.,a.L .:na.u;;
vUIIII~UlvU
......... ....
...,IV""-
uct. Up to four bytes can be read in a single burst
access. inteligent Identifier read is terminated by a
synchronous BLAST input, returning the state machine to the .idle state with outputs at high impedance.
The four byte block code for the inteligent Identifier
code is located at address OOH through 03H and is
encoded as follows:
As in the Read mode, A2-A16 point to a four byte
block in the memory array. During programming, the
,internal address increment circuitry is disabled and
the programmer must supply Ao and A1 to point to
an individual byte within the four byte block that is to
be programmed. Only one byte is programmed in
,each 3 cycle ProgramlVerify sequence.
MEANING
IntellD
(A1, AO)
Byte 00
DATA
89h
27960
ex
Byte 01
Byte 10
EOh
01b
1 Wait State
2 Wait States
Byte 11
Byte 11
01b
10b
Program Inhibit'
RESET MODE
The Program Inhibit mode allows parallel programming and verification of multiple devices with different data. With Vpp at 12.75V, a ProgramlVerify sequence is initiated for any device that receives a valid ADS pulse and rising clock edge while es is asserted. A PGM pulse programs data in the first cycle
of the sequence and data for Program Verify is output in the second cycle. The ProgramlVerify sequence is inhibited on any devices for which es is
not asserted. Data will not be programmed and the
outputs will remain in their high impedance state.
inteligent IdentifierTM Mode
The device's manufacturer, product type, and configuration are stored in a four byte block that can be
accessed by using the inteligent IdentifierTM mode.
Due to the synchronous nature of the 27960eX, the
Various operating modes must be initiated from a
known idle state. During normal operation, the internal state machine returns to an idle state at the termination of a bus access (after BLAST is asserted).
During initial device power up, the state machine is
in an indeterminant state. The reset mode is provided to force operation into the idle state. Reset mode
is entered when the RESET pin is asserted. Output
pins are asynchronously set to the high impedance
state' and address latches are put into the flow
through mode. A reset is successfully completed
and the state machine set in an idle state when
RESET has been asserted for a minimum of 10
clock cycles and deasserted for five clock cycles.
5-207
inter
27960CX
FAIL
290236-17
Figure 11. Qulck·Pulse Programmlng™ Algorithm
5-208
27960CX
ERASURE CHARACTERISTICS
(FOR WINDOWED DEVICES)
QUICK-PULSE PROGRAMMINGTM
ALGORITHM
Exposure to light of wavelength shorter than 4000
Angstroms begins erasure. Sunlight and some fluorescent lamps have wavelengths in the 3000-4000
Angstrom range. Constant exposure to room-level
fluorescent light can erase the EPROM array in
about 3 years (about 1 week for direct sunlight).
Opaque labels over the window will prevent unintentionai erasure under these iighting conditions.
The Quick-Pulse Programming algorithm programs
Intel's 27960CX. Developed to substantially reduce
programming throughput time, this algorithm allows
optimized equipment to program a 27960CX in under 17 seconds. Actual programming time depends
on the programmer used.
The recommended erasure procedure is exposure
to 2537 Angstrom ultraviolet light. The minimum integrated erasure time using a 12000 fW/cm2 ultraviolet lamp is approximately 15 to 20 minutes. The
EPROM should be placed about 1 inch from the
lamp. The maximum integrated dose is 7258
Wsec/cm2 (1 week @ 12000 fW/cm 2). High intensity UV light exposure for longer periods can cause
permanent damage.
The uuick-Puise Programming aigorithm uses a
100 /-Ls pulse followed by a byte verification to determine when the addressed byte is correctly programmed. The algorithm terminates if 25 100 /-Ls
pulses fail to program a byte. Figure 11 shows the
27960CX Quick-Pulse Programming algorithm flowchart.
The entire program-pulse/byte-verify sequence is
performed with Vee = 6.25V and Vpp = 12.75V.
The program equipment must establish Vee before
applying voltages to any other pins. When programming is complete, all bytes should be compared to
the original data with Vee = 5.0V and Vpp =
12.75V.
D.C. PROGRAMMING CHARACTERISTICS TA
Symbol
Parameter
III
Input Load Current
Notes
= 25° ±5°C
Min
Max
Unit
Condition
10
/-LA
VIN = VIH or VIL
lee
Vee Program Current
1
125
mA
CS = VIL
Ipp
Vpp Program Current
1
50
mA
CS = VIL
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage(Verify)
VOH
Output High Voltage(Verify)
VID
As inteligent Identifier
Voltage
Vee
Supply Voltage (Program)
2
Vpp
Program Voltage
2
Vee
+ 0.5
0.40
Vee - 0.8
11.5
V
IOL = 2.1 mA
V
IOH = -400/-LA
12.5
V
6.0
6.5
V
12.5
13.0
V
NOTES:
1. The maximium current value is with outputs unloaded.
2. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
3. During programming clock levels are VIH and VIL.
5-209
V
27960CX
A.C. PROGRAMMING, RESET AND 10 CHARACTERISTICS O·C < T A < + 70·C
No_
Symbol
1
tAVPL
Address Valid to PGM low
2
/A-s
2
tCHAX
ClK High to Address Invalid
50
lis
3
tLLC::H
ADS low to ClK High
1
50
ns
4
tCHLH
ClK High to ADS High
2
. . 50
5
'. tSVCH
Parameter
Notes
CS Valid to ClK High
6
tCHSX
ClK High to CS Invalid
7
tCHQV
ClK High to DOUTValid
8
tCHQX
9
tBVCH
Min
Max
Unit
ns .
50
ns
3
ns
100
ns
ClK High to DOUT Invalid
0
ns
BLAST Valid to ClK High
50
ns
50 .
ns
/A-s
10
tCHBX
elK High to BLAST Invalid
11
taVPL
DATA Valid to PGM low
2
12
tpLPH
PGM Program Pulse Width
95
2
/A-s
13
4
105
/A-s
tpHQX
PGM High to DIN Invalid
14
tcLPL
ClK low to PGM low
50
ns
15
tQZCH
DIN Tri-State to ClK High
2
/A-s
16
tvcs
Vee Program Voltage to ClK High
7
2
/A-s
17
tvps
Vpp Program Voltage to ClK High
7
2
/A-s
18
tAeHCH
Ae VID Voltage to ClK High
2
/A-s
2
/A-s
19
tcHAeX
ClK High to Ae Not VID Voltage
20
tRVCH
RESET Valid to ClK High
6
50
ns
21
tCHCL
ClK High to ClK !-ow
5
100
ns
22
tCLCH
ClK low to ClK High
5
100
ns
NOTES:
1. If CS is low, ADS can go low no sooner than the falling edge of the previous ClK.
2. ADS must return high prior to the next rising edge of clock.
3. CS must remain low until after the rising edge of CLK1.
.
4. BLAST must return high prior to the next rising edge of CLK.
5. Max CLK rise/fall time is 100 ;'s.
6. RESET must be low for 10 clock cycles and high for 5 clock cycles.
7. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
5-210
inter
27960CX
0
elK
V1H
V1L
1
@
J !
H'
ADDR V1H
:
V1L
,
CD:
i
2
}-EM
:0
.:
S
ADDRESS 0
(
ADDRESS 1
u
DATA 0
J>---<~ DATA 1
C\ '......."'....";;,OU;;";,T..,,,,,
\!VX~
f-- e
:
\
I
--1'--..1
B
_ _ VIH
BLAST
k0 Vpp > VIL will cause a slight increase in standby current
The device must be in the idle state (by asserting RESET or using BLASn before going into standby.
5-224
infef
27960KX
CAPACITANCE(1)
TA = 25°C, f = 1.0 MHz
Symbol
Parameter
Typ
Max
Unit
Condition
CIN
Input Capacitance
4
6
pF
VIN =OV
COUT
Output Capacitance
12
15
pF
VOUT =OV
CVPP
VPP Capacitance
40
45
pF
VIN =OV
NOTE:
1. !';"mpIRri. nnt 1nn% tA"tRrI
AC INPUT/OUTPUT REFERENCE WAVEFORMS
AC TESTING LOAD CIRCUIT
2.1V
1.5V
780D.
TIMING PARAMETER
I
CL =120 PF
290237-15
VOL
For tCHQZ CL = 5 pF and RL = 4050
CL includes jig capacitance
290237-14
AG test inputs are driven at 2.4V (VOH) for a logic '1'
and 0.45V (VoLl for a logic '0'.
Input timing begins at 1.5V.
Output timing ends at VIH (2.0V) and VIL (O.SV)
Input Rise and fall times (10% to 90%) < 4.0 ns
CLOCK CHARACTERISTICS
Versions
Symbol
25 MHz
Parameter
Min
40
ClK
Period
T5
Rise Time
T4
Fall Time
T2
low Time
T3
High Time
20 MHz
Max
Min
16 MHz
Max
50
10
Min
62.5
10
10
Units
Max
10
ns
10
ns
10
ns
7
8
11
ns
7
8
11
ns
Max ClK Rise Time during Programming is 100 ns
CLOCK WAVEFORM
290237-16
5-225
inter
27960KX
accessed by using the inteligent Identifier™ mode.
The programmer can verify the device identifier and
choose the programming algorithm that corresponds
to the Intel 27960KX. The inteligent Identifier can
also be used to verify that the product is configured
with the desired Read mode options for wait states.
Program/Program Verify
Initially, and after each erasure, all bits of the
EPROM are in the "1's" state. Data is introduced by
selectively programming "O's" into the desired bit
locations. Although only "O's" can be programmed,
both "1's" and "O's" can be present in the data
word. Ultraviolet erasure is the only way to change
Inteligent Identifier mode is entered when Ag (pin
32) is raised to its high voltage (VH) level. The internal state machine is then set for inteligent Identifier
Read operation. Reading the Identifier is similar to a
Read operation on a one wait state configured product. Up to four bytes can be read in a single burst
access. inteligent Identifier read is terminated by a
synchronous BLAST input, returning the state machine to the idle state with outputs at high impedance.
"O's" to "1'8".
Program mode is entered when Vpp is raised to
12.75V. ProgramlVerify operation is synchronous
with the clock and can only be initiated following an
idle state. Program and Program Verify take place in
3 clock cycles. In the first clock cycle, addresses
and data are input and programming occurs. Program Verify follows in the second clock cycle and
the third clock cycle terminates synchronous ProgramlVerify operation, returning the state machine
to the idle state with outputs at high impedance.
The four byte block code for the inteligent Identifier
code is located at address OOH through 03H and is
encoded as follows:
As in the Read mode, A2-A16 point to a four byte
block in the memory array. During Programming the
internal address increment circuitry is disabled and
the programmer must supply Ao and A1 to point to
an individual byte within the four byte block that is to
be programmed. Only one byte is programmed in
each 3 cycle programlVerify sequence.
MEANING
IntellD
27960
KX
1 wait state
2 wait states
Program Inhibit
RESET MODE
Program Inhibit mode allows parallel programming
and verification of multiple devices with different
data. With Vpp, at 12.75V, a ProgramlVerify sequence is initiated for any device that receives a valid ALE pulse and rising clock edge while CS is asserted. A PGM pulse programs data in the first cycle
of the sequence and data for Program Verify is output in the second cycle. The ProgramlVerify sequence is inhibited on any devices for which CS is
not asserted during the first (ALE) cycle. Data will
not be programmed and the outputs will remain in
their high impedance state.
Due to the synchronous nature of the 27960KX, the
various operating modes must be initiated from a
known idle state. During normal operation, the internal state machine returns to an idle state at the termination of a bus access (after BLAST is asserted).
inteligent IdentifierTM Mode
The device's manufacturer, product type, and configuration are stored in a four byte block that can be
(A1> Ao)
Byte 00
Byte 01
Byte 10
Byte 11
Byte 11
DATA
89h
EOh
OOb
01b
10b
During initial device power up, the state machine is
in an indeterminant state. The reset mode is provided to force operation in to the idle state. Reset mode
is entered when the RESET pin is asserted. Output
pins are asynchronously set to the high impedance
state and address latches are put into the flow
through mode. A reset is successfully completed
and the state machine set in an idle state in the
cycle after RESET has been asserted for a minimum
of 10 clock cycles and deasserted for five clock cycles.
5-226
27960KX
FAil
290237-17
Figure 8. Quick-Pulse Programming™ Algorithm
5-227
27960KX
programming throughput time, this algorithm allows
optimized equipment to program a 27960KX in under 17 seconds. Actual programming time depends
on the programmer used.
.
ERASURE CHARACTERISTICS
(FOR W\NDOWED DEVICES)
Exposure to light of wavelength shorter than 4000
Angstroms begins erasure. Sunlight and some fluorescent lamps have wavelengths in the 3000-4000
Angstrom range. Constant exposure to room-level
fluorescent light can erase the EPROM array in
about 3 years (about 1 week for direct sunlight).
Opaque labels over the window will prevent unintentional erasure under these lighting conditions.
The Quick-Pulse Programming algorithm uses a
100 ,...s pulse followed by a byte verfication to determine when the addressed byte is correctly programmed. The algorithm terminates if 25 100,...s
pulses fail to program a byte. Figure B shows the
27960KX Quick-Pulse Programming algorithm flowchart.
The recommended erasure procedure is exposure
. to 2537 Angstrom ultraviolet light. The minimum integrated erasure time using a 12000 fW I cm2 ultraviolet lamp is approximately 15 to 20 minutes. The
EPROM should be placed about 1 inch from the
lamp. The maximum integrated dose is 725B Wsecl
cm2 (1 week @ 12000 fW/cm2). High intensity UV
light exposure for longer periods can cause permanent damage.
The entire program-pulse,· byte-verify sequence is
performed with Vee = 6.25V and Vpp = 12.75V.
The programming equipment must establish Vee before applying voltages to any other pins. When programming is complete, all bytes should be compared
to the original data with Vee = 5.0V and Vpp
12.75V.
QUICK-PULSE PROGRAMMING
ALGORITHM
The· Quick-Pulse Programming algorithm programs
Intel's 27960KX. Developed to substantially reduce
D.C. PROGRAMMING CHARACTERISTICS TA = 25°C ±5°C
Symbol
Parameter
Notes
Min
Max
Unit
Test Condition
10
= VIH or VIL
= VIL
CS = VIL
III
Input Load Current
,...A
VIN
lee
Vee Program Current
1
125
mA
CS
Ipp
Vpp Program Current
1
50
mA
VIL
Input Low Voltage
-0.5
O.B
V
VIH
Input High Voltage
2.0
Vee + 0.5
V
VOL
Output Low Voltage (Verify)
0.40
V
IOL
VOH
Output High Voltage (Verify)
V
IOH
VID
A9 inteligent Identifier Voltage
11.5
12.5
V
Vee
Supply Voltage (Program)
2
6.0
6.5
V
Vpp
Program Voltage
2
12.5
13.0
V
Vee- O.B
NOTES:
1. The maximum current value is with outputs unloaded.
2. Vec must be applied simultaneously or before Vpp and remove simultaneously or after Vpp.
3. During programming clock levels are VIH and VIL.
5-22B
= 2.1 mA
= -400,...A
27960KX
AC PROGRAMMING, RESET AND 10 CHARACTERISTICS
No
Symbol
1
Parameter
Notes
O°C
< T A < + 70°C
Min
Max
Units
tAvPl
Address Valid to PGM low
2
J.Ls
2
tCHAX
ClK High to Address Invalid
50
ns
3
tllCH
ALE low to ClK High
1
50
ns
2
50
ns
5
tCHlH
... _.. - ..
ClK High to ALE High
"::SVL;H
,-.e
\/ .... 1;""""""
_ _ ,"UIIU "V
50
..
6
tCHSX
ClK High to CS Invalid
4
v
""'-'"
f""
U; .... h
I
"Mil
3
7
tCHQV
ClK High to DOUT Valid
8
tCHQX
ClK High to DOUT Invalid
9
tBVCH
BLAST Valid to ClK High
10
tCHBX
ClK High to BLAST Invalid
11
tQVPl
DATA Valid to PGM low
12
tplPH
PGM Program Pulse Width
100
4
~
ns
ns
0
ns
50
ns
50
ns
2
95
J.Ls
105
J.Ls
13
tPHQX
PGM High to DIN Invalid
2
J.Ls
14
tClPl
ClK low to PGM low
50
ns
15
tQZCH
DIN in Tri-State to ClK High
2
/Ls
16
tvcs
VCC Program Voltage to ClK High
7
2
/Ls
17
tvps
Vpp Program Voltage to ClK High
7
2
J.Ls
18
tAAHCH
Ag VID Voltage to ClK High
2
/Ls
19
tCHAgX
ClK High to A9 not VID Voltage
2
/Ls
20
tRVCH
RESET Valid to ClK High
6
50
ns
21
tCHCl
ClK High to ClK low
5
100
ns
22
tclCH
ClK low to ClK High
5
100
ns
NOTES:
1. If CS is low, ALE can go low no sooner than the falling edge of the previous ClK.
2. ALE must return high prior to the next rising edge of clock.
3. CS must remain low until after the rising edge ClK1.
4. BLAST must return high prior to the next rising edge of ClK.
5. Max ClK rise/fall time is 100 ns.
6. RESET must be held low for 10 cycles and high for 5 cycles before performing a read.
7. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
5-229
intJ
27960KX
.......
~
............. .
@
©
o
Vl
~
'"
c · · · · · -----------
0
~
~
~
---....-ri-+"" ............................... .
.. J ....
®
:r:
..J
:> :>
'"u
..J
:r:
..J
>- :>
c
c
...'"
:r:
:> >-
:> :>
:> :>
:> :>
I~
...c~
I~
I~
..J
:r:
..J
:r:
..J
:r:
..J
:r:
Figure 9. 27960KX Programming Waveforms
5-230
..J
:> :>
113
l>l>-
>
e.>
e.>
>
intJ
27960KX
:@f
v
CLOCK
n LJn Lfr: -LF--
:---..:
.
•
IH
VIL.....J
____;....-___...J·XI!:~~:::
ADDR
\
XXXXXxxxxXXXXXX
tV
_ _ _ _'!--_ _ _ _...;...._~:,««
DATA
1.0.
~
~ Byte 0
@~~
Vpp
VIO
Ag V
IH
\_~--~------------~---
\:-;_-----If
.,
@!
@!
'r~-:-'---:------------'~-+:
xxxxxxxxxxxxf
i
\xx
290237-19
Figure 10. 27960KX RESET and 10 Waveforms
5-231
APPLICATION
NOTE
AP-329
November 1990'
68030/27960CX
Burst EPROM Interface
DEAN PARMAR
SENIOR APPLICATIONS ENGINEER
PROGRAMMABLE MEMORY OPERATION
Order Number: 292064·001
5·232
68030/27960CX BURST EPROM INTERFACE
CONTENTS
PAGE
1.0 SIGNAL DEFINITIONS ............. 5-234
1.1 68030 Signals ................... 5-235
1.2 27960 EPROM Signals .......... 5-236
2.u
iNT~Ri=AC~ R~Qi.iiR~ivi~NT5
..... 5-236
CONTENTS
PAGE
3.0 CIRCUIT DESCRIPTION ...........
3.1 ADS Generation .................
3.2 STERM Generation ..............
3.3 CBACK Generation ..............
3.4 BLAST Generation ..............
3.5 Data Latches ....................
5-236
5-240
5-241
5-241
5-241
5-241
APPENDIX A .......................... 5-248
Delay Line Information ................. 5-259
5-233
intJ
AP-329
INTRODUCTION·
This application note describes the design of a circuit to
interface the 27960CX burst EPROM to Motorola's
68030 microprocessors (J.LP). The 68030 jJ,P is capable
of burst mode operation, accessing a maximum of four
long words (long word = 32 bits) during a burst cycle.
A 2-0-0-0 burst operation (2 wait states for the first
word access and zero wait state for subsequent accesses) is possible at 25 MHz using the 27960C2-25 burst
EPROM. At 33 MHz, a 3-0c()..0 operation is possible
using the 27960C2-33 burst EPROM. This memory interface monitors control signals from the J.LP, provides
handshake logic for the J.LP and generates ADS and
BLAST signals for the EPROMs. It also monitors
cache burst request (CBREQ) and cache inhibit (CIIN)
signals from the J.LP, and generates BLAST as appropriate.
Two designs are considered for this interface, a 33MHz system and a 25/20 MHz system. The 33-MHz
interface can be implemented with a 16R4-7 PAL, four
74F374 latches and a D-type flip/flop. The latches are
required because the 68030 latches data on the falling
edge of the clock, while the 27960 provides data on the
rising edge of clock. The latches provide plenty of setup
and hold time. The 25/20 MHz interface can be implemented with a 16R4-7 PAL and a couple of D-type
flip/flops, but requires a delayed clock for the PAL and
EPROMs. Because the clock is delayed no latches are
required.
1.0 SIGNAL DEFINITIONS
FUNCTION CODES
ADDRESS BUS
DATA BUS
TRANSFER SIZE
{<
{<
{<
{
IPlO
FeO-Fe2
IPL1
IPl2
IPEND
AO-A31
AVEC
00-031
..
j
lNTERRUPT
CONTROL
BR
-v
BG
SIZO
BGACK
}
BUS ARBITRATION
CONTROL
}
BUS EXCEPTION
CONTROL
}
SYNCHRONOUS
BUS CONTROL .
SIZI
RESET
OCS
ECS
HALT
MC68030
BERR
R/W
RMC
STERM
AS
ASYNCHRONOUS
BUS CONTROL
OS
illiIT
DBEN
STATUS
DSACKO
CDiS
DSACKI
MMUDIS
1J
EMULATOR
SUPPORT
CIIN
CACHE CONTROL
1
ClK
ClOUT
Vee
CBREQ
GND
CBACK
292064-1
Figure 1. MC68030 Functional Signal Groups
5-234
intJ
AP-329
1.1 68030 Signals
1.1.6 DBEN (Output)
This section describes 68030
vant to this interface.
~P
signals which are rele-
1.1.1 ECS (Output)
Provides an indication that a bus cycle is beginning.
The external cycle start (ECS) signal is the earliest indi,..~t1nTl
th'!llt th""
II
P
i~
;nit1'!l1ttnlT
'!lI
hll<1 ,..",..1,.".
Th""
MC68030-initi;rte;; b~s ~;~i;'b; drlvi;; th~ -;ddr~~~:
size, function code, cache inhibit-out, and read/write
outputs and asserting ECS.
1.1.2 ADDRESS BUS
The address bus signals (AO-A31) define the address of
the byte (or the significant byte) to be transferred during a bus cycle. The ~P places the address on the bus at
the beginning of a bus cycle. The address is valid while
AS is asserted.
1.1.3 AS (Output) .
The address strobe (AS) is a timing signal that indicates
the validity of an address on the address bus and of
many control signals. It is asserted one half clock after
the beginning of a bus cycle.
The data buffer enable signal (DBEN) can be used to
enable external data buffers while data is present on the
data bus. During a read operation DBEN is asserted
one clock cycle after the beginning of the bus cycle, and
is negated as DS is negate~In a write operation,
DBEN is asserted at the time AS is asserted, and is held
active for the duration of the cycle. DBEN timings may
prevent the use of a synchronous system using twoclock bus cycles.
1.1.7 STERM (Input)
This input is a bus handshake signal indicating that the
addressed port size is 32 bits and that data is to be
latched on the next falling clock edge for a read cycle.
This signal applies only to synchronous operation. For
synchronous bus cycles, external devices assert the synchronous termination signal (STERM) as part of the
bus protocol. During a read cycle, the assertion of
STERM causes the ~P to latch the data. During a
write cycle, it indicates that the external device has successfully stored the data. In either case, it terminates
the cycle, and indicates that the transfer was made to a
32-bit port.
1.1.8 CBREQ (Output)
This three-state output signal requests a burst mode
operation to fill a line in the instruction or data cache.
1.1.4 DATA BUS
The data bus signals (DO-D31) run on a bi-directional,
non-multiplexed, parallel bus that contains the data being transferred to or from the ~P. A read or write operation may transfer 8, 16, 24 or 32 bits of data (one, two,
three or four bytes) in one bus cycle. During a read
cycle the data is latched by the ~P on the last falling
edge of the clock -for that bus cycle.
1.1.9 CBACK (Input)
This input signal indicates that the accessed device can
operate in the burst mode, and can supply at least one
more long word for the instruction or data cache.
1.1.10 CIIN (Input)
1.1.5 DS (Output)
The data strobe (OS) is a timing signal that applies to
the data bus. For a read cycle the· ~P asserts DS to
signal the external device to place data on the bus. It is
asserted at the same time as AS during a read cycle.
For a write cycle DS signals to the external device that
the data to be written is valid. The /loP asserts DS one
full clock cycle after the assertion of AS during a write
cycle.
This input signal prevents data from being loaded into
the MC68030 instruction and data caches. It is a synchronous input signal and is interpreted on a bus-cycleby-bus-cycle basis. CIIN is ignored during all write cycles.
5-235
intJ
AP-329
2.0 INTERFACE REQUIREMENTS
1.2 27960 EPROM Control Signals
1.2.1 ADS: ADDRESS STROBE
Indicates the start of a new bus access. It is active low·
in the first clock cycle of a bus access.
1.2.2 BLAST: BURST LAST
Terminates a concurrent burst data cycle at the rising
edge of CLK. Must be asserted by the fourth data
word.
1.2.3 CS: CHIP SELECT
Master device enable. When asserted (active low) data
can· be written to and read from the device. In read
mode, CS, enables the state machine and the 1/0 circuitry. A memory access begins on the first rising edge
of clock after ADS and CS are asserted. CS can be deasserted after the number of wait-states, N, has expired,
and the EPROM will continue to burst out data for the
current cycle. If CS is de-asserted during the wait-state
period the burst access will be aborted.
The interface logic is designed to work in burst mode,
with the synchronous termination signal, STERM, as
the handshake for the p.P indicating EPROM readiness
for a burst transfer. The interface logic will monitor
control signals from the ,...P, i.e., ECS, AS, DBEN and
CBREQ .and generate ADS and BLAST signals for the
27960 and STERM and CBACK signals for the, lip.
STERM will be asserted by the interface logic after the
number of wait states, N, has expired. The logic will
also monitor CBREQ and CIIN signals and generate
BLAST as appropriate.
Figures 2 and 3 show schematics of the 68030/27960
Burst EPROM interfaces.
3.0 CIRCUIT DESCRIPTION
This section describes the burst mode operation of the
68030 p.P followed by a brief description of the interface circuits (Figures 2 and 3). Figure 2 shows a
33 MHz design which allows 3-0-0-0 burst operation;
Figure 3 shows a 25/20 MHz design which allows a
2-0-0-0 and a 1-0-0-0 burst operation at 25 MHz and
20 MHz respectively.
5-236
33 MHz
CLOCK
GENERATOR
r--
r-L,.)
X
1
(
cs
CS2
ADDRESS
DECODER
CLK
IJ
ClK
'11
ADDR
rEi
c
ia
""3:
Co)
Co)
ClK
AS
CBACK
I
::E:
STERM
(II
DB EN
68030
00-031
-
BlASTl
CBREQ
h
PAL
16R4-7
ADS
I
BlAST2
BLAST
r:--.
N
CD
0
C{'
I\)
t.)
Co)
0
.....
N
CS
ClK
27960
128K
X
8
BLAST
~
~
~
~
CS
ClK
27960
128K
X
8
BLAST
~c1r-
~
~
~
~
ClK
27960
12E,K
X
8
BlASl'
L...- r-
I----t
~
I:---t
I---'
CS
CLK
27960
12BK
X
8
BLAST
ADS
>
12
Co:!
l+CIIN I+-
...... .....
CD
I\)
CD
(II
0
In
"::u
BlAST3
0
3:
;.-
H
S"
CD
so
H
-
CIIN
n
CD
CLK
~>
4
X
---.~7~4
L...!~
OE
Y-D
32
1/2
Q
/
32
74.74
CIIN
292064-2
(
CLK
I--CLOCK
OSCILLATOR
f---I
CLOCK
DRIVER/
INVERTER
CLK
~CLK
at
.--
Cs
ADDRESS
DECODER
X
"11
.
iri
c
CD
1
ADDRJ
~
U1
......
I\)
9
~
:I:
N
Q)
CBACK
STERIo4
CXl
......
I\)
DBEN
68030
00-031
-.j
~
CIIN
0
h
Cs
3"
..-....
III
()
CD
8
BLAST
27960.
128K
x
8
BLAST
cs
~
~
~
~
CLK
27960
128K
x
8
BLAST
CS
~
f---I
f---I
f---I
CLK
27960
128K
X
8
BLAST
.
»
"'tI
Co)
r.)
co
I+~
R
0
r-
L.....-~ S Q~
BLAST3
0
0
74F74
CD
A~
BLAST
X
cs
CLK
~
~
~
BLAST2
PAL
16R4-7
27960
128K
f------.
f------.
f------.
f------.
ADS_CK
~
"0
::u
I-
BLASTl
m
0
cs
CLK
CBREO
co
c.n 0
w
N
0
U)
CLK
AS
I\)
D~
74F74
a
L....--
H
CIIN
H
S
H
-
CLK
74F74
---t
--,R.....32
CIIN
292064-3
AP-329
The circuits are designed to operate in a 32-bit burst mode. Four long words (long word
transferred during a single burst operation. Figure 4 shows a burst operation cycle.
BURST OPERATION
ICYCLE 1
CYCLE 2
FIRST ACCESS OF
BURST OPERATION
/
"\~~~U~~~~E~~~;;;u/
CYCLE 4
BURST FILL CYCLE
/~
+
BURST t.lODE
REQUESTED AND
ACKNOWLEDGED
I
----------------+1CYCLE 3
BURST FILL CYCLE
~
32 bits) may be
BURST FILL CYCLE
/~
/~
BURST t.lODE BEGINS HERE
292064-4
, Figure 4_ Burst Operation Cycles
The circuits also allow address wrap around so that the entire four long words in the cache line can be filled in a
single burst operation regardless of the initial address. Figure 5 shows a burst filling wrap-around example.
SOD
I
FINAL CACHE ENTRY
TO BE FILLED
S04
SOB
I b41 b5 Ib61 b71
IbBI b91 bA I bB I
I
FIRST LONG WORD ACCESS
- INCLUDES FIRST PART
OF OPERAND REQUIRED
I
SECOND CACHE ENTRY
TO BE fiLLED
SOC
I
THIRD CACHE ENTRY
TO BE FILLED
292064-5
Figure 5_ Burst Filling Wrap-Around Example
The initial cycle is a long word access from address $06. Because the interface logic returns CBACK and STERM
(signaling a 32-bit port), the entire long word at base address $04 is transferred. Since the initial address is $06 when
CBREQ is asserted, the next entry to be burst filled into the cache should correspond to address $08, then $OC, and
last, $00.
The 68030 ,...p does not assert CBREQ during the first portion of a misaligned access if the remainder of the access
does not correspond to the same cache line. Figure 6 shows an example in which the first portion of a misaligned
access is at address $OF. With a 32-bit port the first access corresponds to the cache entry at address $OC, which is
filled using a single-entry load operation. The second access at address $10 (corresponding to the second cache line)
requests a burst fill and the processor asserts CBREQ. During this burst operation long words $10, $14, $18 and $IC
are all filled, and in that order.
5-239
inter
AP-329
JOO
JOB
J04
JOC
I I I I I
bC
NO CBREQ ASSERTED I'----'-----'-_L---'
bD
bE
bF
I
FIRST LONG WORD CACHED
,NO BURST REQUEST
Jl0
J14
I
SECOND CYCLE BURST
REQUESTED
J18
J1C
I
THE REMAINING CACHE ENTRIES FOR SECOND BLOCK ARE BURSTED
292064-6
Figure 6. Deferred Burst Filling Example
The ,...p does not assert CBREQ if the cycle is for the first access of an operand that spans two cache lines (crosses a
modulo 16 boundary).,
3.1 ADS Generation
Figure 7 shows the timing of ADS for the 33·MHz design of Figure 2. A 4-bit counter is implemented in the PAL
which is used for timing of ADS, STERM, CBACK, and BLAST. Assertion of AS enables the 4·bit counter. ADS is
asserted following Count I (CNTl), and de-asserted at Count 2 (CNT2).
30ns
o
1
r
2
CNT1
,.. CNT2
ClK
292064-7
Figure 7. ADS Generation for 33·MHz Circuit
5·240
of Figure 2
inter
AP"'329
For the 25/20-MHz system (Figure 3) ADS is referenced to D_CLK (Figure SA). D CLK is the inverted and delayed version of CLK. D_CLK is used for
generating ADS, STERM, CBACK and BLAST. For
this design a 3-bit counter is implemented in the PAL.
ADS is asserted when ADS_CK clocks the first flip/
flop. ADS_CK makes the low to high transition when
both AS and CS are vaJid. The next rising edge of D_
CLK resets the first flip/flop, and ADS is pulled high.
With this implementation data latches are not required,
__ ...lI_"'nnn ____ t n n n 1 __ ..__ .L
ClUU
a
~-v-u-v
____ •• :_
Ul '" l-V-V-V UUl:!JL upCaaLIUll
'.
l~
___ ."
•
l'U:!J:!JIUIC i1t.
25 MHz and 20 MHz respectively. This design buys an
extra wait state as shown in the timing diagram of Figure 10. If the use of delay line is not preferred, then the
design shown in Figure 2 can be used to provide 3-0-0-0
and 2-0-0-0 performance at 25 MHz and 20 MHz respectively.
3.2 STERM Generation
3.2.1 33 MHz DESIGN
STERM is asserted after the number of wait states, N,
has expired (N is the number of wait states with respect
to the EPROM). For the 33-MHz design, a 2 wait-state
EPROM (27960C2-33) is used, which equates to a
3 wait state system performance. STERM is asserted on
count 4 and de-asserted on count 8 (Figure 9).
It is also used to terminate a burst operation of less
than 4 words. Assertion of BLAST during the waitstate period is ignored by the EPROM. There are three
conditions for generation of BLAST (i.e., BLAST!
through BLAST3) which are AND gated to produce
the BLAST signal for the EPROM:
3.4.1 BLAST1: (Normal Burst End)
BLAST! is used to terminate a 4-word burst. For the
33-MHz design BLASTI is asserted on count 7 and deasserted on count 8 (Figure 9). For the 25-MHz design,
BLAST! is asserted on count 6 of D_CLK and de-asserted on count 7 of D_CLK (Figure 10).
3.4.2 BLAST2: (Deferred Burst)
BLAST2 is generated if the ,...p accesses a misaligned
operand. Figure IIA shows an access.to a misaligned
operand followed by a deferred burst access. In this
case the burst operation is deferred because the first
access corresponds to cache entry at $OC which is accessed as a single word. The second access at address
$10 corresponds to the second cache line, and a burst
request is made: The ,...p asserts CBREQ during a burst
request. BLAST2 is used to terminate the single word
access. Figure liB shows the logic for generating
BLAST2. The state of CBREQ is monitored, and if it is
high BLAST2 is asserted on count 4 (after the number
of wait states, N, has expired) and de-asserted on COl;.,t
3.2.2 25 MHz DESIGN
5.
For the 25 MHz design, STERM is asserted on count 3
(reference to D_CLK) and de-asserted on count 7
(Figure 10).
3.4.3 BLAST3
3.3 CBACK Generation
BLAST3 is generated if CIIN is asserted during a burst
cycle. Figure 12 shows the timing diagram for generation of BLAST3. CIIN resets the flip/flop, and the next
rising edge of clock pulls BLAST3 high.
The timing of CBACK is the same as STERM.
3.5 Data Latches
3.4 BLAST Generation
BLAST is used to terminate a burst cycle. For a 4-word
burst BLAST is asserted following the rising edge of
CLK in the next to last clock cycle (Figures 9 and 10).
The four data latches latch the 32-bit data on the rising
edge of CLK (since the 27960 burst EPROM provides
data on the rising edge of CLK). The 68030 ,...p reads
the data on the falling edge of CLK. The latches provide plenty of setup and hold times for the data. DBEN
signal is used to enable the data latches.
5-241
AP-329
40
o
o
Q 1----1 0
74F74
,
-
',CS
,,
x/
,--
Q
I
' '
H
Implemented in PAL
292064-8
NOTES:
~ is inverted and delayed version of elK.
at = 5 ± 1 ns for 25 MHz System.
at = 9 ± 1 ns for 20 MHz System.
Figure SA. ADS Generation for 25/20 MHz Circuit of Figure 3
H
CLOCK INPUT
FROM OSCILLATOR
....f'lF
292064-9
Figure SB. Circuit for Generating Opposite Phases of ClK
5-242
inter
AP-329
30no
o
2
3
4
5
6
7
8
9
r
EPROM
DATA
J.'P DATA
292064-10
NOTES:
3-0-0-0 = 3 wait states for first word access, 0 wait states for subsequent words.
68030 latches data on the falling edge of clock.
A 4-bit counter is implemented in the PAL which provides timing for STERM, CBACK, ADS and BLAST1.
BLAST1 is ANDed with BLAST2/3 to generate BLAST for the EPROMs (see Figure 2).
Figure 9. 3-0-0-0
4 Word Burst Operation (33 MHz)
5-243
intJ
AP-329
-
40 ns
~
II)
:
ns '0-10
..
..J
J~
Vi
a.
=I.
::~"':"""'r-"'''':'''''''r-"'
tS:
:
:
:............:
:
BlAST3
,....;- tH
latch' delay
.
:
J"P OATA
:
~C!:::
00
"":--1-0.
01
X
02
-:--r-"'
BlAST3 AS A RESULT OF CIIN
I
I
I
292064-14
H
elK
FROM PAL
292064-15
Figure 12. Timing Diagram for Generation of BLAST as Result of CIIN While STERM is Asserted
5-247
AP-329
APPENDIX A
CONTENTS
i. AC parameters and timing waveforms for the
27960CX burst EPROM and the 68030 ""P.
ii. Delay line information.
EXPLANATION OF AC SYMBOLS
The nomenclature used for timing parameters are as
per IEEE STD 662-1980 IEEE Standard Terminology
for Semiconductor Memory.
The fifth character represents the signal level indicated
by the fourth character. The list below shows character
representations.
A:
B:
C:
H:
L:
P:
X:
Each timing symbol has five characters. The first is
always a "t" (for time). The second character represents a signal name (e.g., CLK, ADS, etc.). The third
character represents the signal's level -(high or low) for
the signal indicated by the second character. The fourth
character represents a signal name at which a transition
,occurs marking the end of the time interval being specified.
5-248
Address
R: Reset
BLAST
Q: Data
Clock
S: "'C;:';hi=-p"'S-=;el;::"ec=Ot
Logic High Level
t: Time
ADS/Logic Low Level
V: Valid
Vpp Programming Voltage
Z: Tristate Level
No longer a valid "driven" logic level
inter
AP-329
AC CHARACTERISTICS
o·c < TA <
Versions
No_
1
+70·C,
vcc =
5V ±10%
27960C2-33
27960C2-25
27960C1-20
33 MHz
20 MHz
16MHz
2 Wait State
25 MHz
2 Wait State
1 Wait State
1 Wait State
Min
Min
Min
Max
Max
Max
27960C1-16
Units
Symbol
Parameter
Notes
Min
tAVCoH
Address
Valid to
ClKO
12
10
14
22
ns
Max
_I '"
11:_1VL.~nlyll
2
tCNHAX
ClK High to
Address
Invalid
2
0
0
0
0
ns
3
tllCH
ADS low to
ClK High
ClKO
B
B
14
22
ns
4
tCHlH
ClK High to
ADS High
5
6
5
tsvCH
Chip Select
Valid to
ClK High
1
7
7
6
14
ns
6
tCNHSX
ClK High to
Chip Select
Invalid
2
0
0
0
0
ns
7
tCHQV
ClK High to
Data Valid
7
8
tCHQX
ClK High to
Data Invalid
9
tcHQZ
ClK High to
Data Hi-Z
10
tBVCH
BLAST
Valid to
ClKHigh
11
tcHBX
ClKHighto
BLAST
Invalid
22
27
5
6
40
30
6
40
5
14
32
6
35
30
6
36
5
B
22
6
30
25
6
32
5
8
3
6
30
6
ns
ns
22
36
ns
ns
ns
40
ns
NOTES:
1. Valid signal level is meant to be either a logic high or logic low.
2. The subscript N represents the number of wait states for this parameter. CS can be de-asserted (high) after the number
of wait states (N) has expired. The EPROM will continue to burst out data for the current cycle.
3. BLAST must be returned high before the next rising clock edge.
4. The sum of tcHOV + tAVCH + NClK will not ,equal actual tAVOV if independent test conditions are used to obtain tAVCH
and tCHOV (N = number of wait states).
5. ADS must be returned high before the next rising clock edge.
6. Sampled but not 100% tested. The transition is measured ± 500 mV from steady state voltage.
7. For capacitive loads above 80 pF, tcHOV can be derated by 1 ns/20 pF.
5-249
inter
AP-329
..,J.
®
®
_0
.9
.9
.9
J
en
~
Figure 10. 27960CX
2 Walt State AC Waveforms
5-250
AP-329
AC ELECTRICAL SPECIFICATIONS -
Num.
CLOCK INPUT (see Figure 9)
16.67 MHz
Characteristic
20 MHz
Min
16.67
12.5
20
12.5
80
50
80
40
28
52
23
57
19
-
5
-
5
-
Ma.
Min
12.5
60
2.3 Clock Pulse Width Measured from 1.5 V 10 1.5 V
4,5 Clock Rise and Fall Times
Frequency of Operation
1
Cycle Time Clock
25 MHz
Max
Min
33.33 MHz
Min
Ma.
Unit
25
20
33.33
MHz
80
30
50
ns
61
14
36
ns
4
-
3
ns
Ma.
2.0 V
0.8 V
Figure 9. Clock Input Timing Diagram
292064-17
Reprinted with permission of Motoro)a Inc.
5-251
inter
AP-329
AC ELECTRICAL SPECIFICATIONS see Figures 11 through 16)
READ AND WRITE CYCLES (VCC=5.0 Vdc ± 5%; GND=O Vdc; TA=O to 70'C;
16.67 MHz
Num.
6
Characteristic
Clock High to Function Code. Size, RMC. IPEND,
Address Valid
CiOiJ'i',
ZOMHz
25 MHz
33.33 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Unit
0
30
0
25
0
20
0
14
ns
6A
Clock High to ECS. OCS Asserted
0
20
0
15
0
15
0
12
ns
6B
Function Code, Size, RMC, IPENO, CIQIiL
Address Valid to Negating Edge of ECS
5
-
4
-
3
-
3
-
ns
\
7
Clock High to Function Code, Size, RMC, ClOUT, Address,
Data High Impedance
0
60
0
50
0
40
0
30
ns
8
Clock High to Function Code, Size, RMC, IPEND, ClOUT,
Address Invalid
0
-
0
-
0
-
0
-
ns
9
Clock Low to AS, OS Asserted. CBREO Valid
3
30
3
20
3
18
2
10
ns
9A'
AS to OS Assertion Skew (Read)
-15
15
-10
10
-10
10
-8
8
ns
9B'4
AS Asserted to OS Asserted (Write)
37
32
lOA
OCS Width Asserted
20
8
-
ns
20
10B7
ECS, OCS Width Negated
15
5
5
ns
Function Code, Size, RMC, ClOUT, Address Valid to AS
Asserted (and OS Asserted, Read)
15
-
10
7
-
-
11
-
-
22
ECS Width Asserted
-
27
10
-
5
-
ns
12
Clock Low to AS, OS, CBREO Negated
0
30
0
20
0
18
0
10
ns
Clock Low to ECS/OCS Negated
0
30
0
20
0
18
0
15
ns
13
AS, OS Negated to Function Code, Size, RMC ClOUT,
Address Invalid
15
10
-
7
-
5
-
ns
14
AS (and OS Read) Width Asserted (Asynchronous Cycle)
85
70
-
45
-
ns
30
-
23
-
ns
30
23
-
ns
30
-
23
-
ns
30
ns
5
-
ns
12A
15
15
10
10
10
8
ns
ns
OS Width Asserted (Write)
40
-
AS (and OS, Read) Width Asserted (Synchronous Cycle)
40
-
35
AS, OS Width Negated
40
38
OS Negated to AS Asserted
35
30
-
25
-
18
16
Clock High 10 AS, OS, RIW, DBEN, CBREO High Impedance
-
-
50
-
40
17
AS, OS Negated to RIW Invalid
15
-
10
-
7
-
-
18
Clock High to RIW High
0
30
0
25
0
20
0
15
ns
20
Clock High to RIW Low
0
30
0
25
0
20
0
15
ns
21
RIW High to AS Asserted
15
10
-
ns
75
60
47
-
5
RIW Low to OS Asserted (Write)
-
7
22
-
35
-
ns
23
Clock High to Data-Out Valid
-
30
-
25
-
20
14
ns
24
Data-Out Valid to Negating Edge of AS
12
8
-
3
10
7
-
5
25A9." OS Negated to DBEN Negated (Write)
15
-
10
-
7
-
-
ns
15
-
5
AS, OS Negated to Data-Out Invalid
-
5
"-
ns
Data-Out Valid to OS Asserted (Write)
15
10
-
7
-
ns
5
4
-
2
1
Late BERR/HALT Asserted to Clock Low (Setup)
15
-
10
-
5
3
-
ns
27A
-
5
Data-In Valid to Clock Low (Setup)
-
28'2
AS, OS Negated to DSACK., BERR, HALT. AVEC
Negated (Asynchronous Hold)
0
60
0
50
0
40
0
30
ns
Clock Low to DSACKx, BERR, HALT, AVEC Negated
(Synchronous Hold)
15
100
12
85
8
70
6
50
ns
AS, OS Negated to Data-In Invalid (Asynchronous Hold)
0
0
-
-
0
-
ns
AS, OS Negated to Data-In High Impedance
-
-
0
60
-
50
-
40
-
30
ns
Clock Low to Data-In Invalid (Synchronous Hold)
15
-
12
-
8
ns
Clock Low to Oata·ln High Impedance (Read followed by Wrke)
-
90
-
75
-
45
ns
14A"
14B
15
15AB
25"
26"
27
2BA'2
29'2
29A'2
30'2
3OA'2
'100
60
38
-
60
6
-
ns
ns
ns
292064-18
Reprinted w~h permission of Motorola Inc.
5-252
intJ
AP-329
AC ELECTRICAL SPECIFICATIONS (Continued)
16.67 MHz
Hum.
Chlrlet.risti.
31 2
3M3
20 MHz
25 MHz
Min
MI.
Min
MIX
Min
MIX
DSACKx Asserted to Data-In Valid (Asynchronous Data Setup)
-
50
-
43
-
28
DSACK. Asserted to DSACK. Valid (Skew)
-
15
-
10
-
7
1.5
-
1.5
-
33.33 MHz
Min
Mo.
Unit
20
ns
5
ns
1.5
-
1.5
Clks
ns
32
RESET Input Transition Time
33
Clock Low to BG Asserted
0
30
0
25
0
20
0
15
34
Clock Low to BG Negated
0
30
0
25
0
20
0
15
ns
35
BR Asserted to BG Asserted (RMC Not Asserted)
1.5
3.5
1.5
3.5
1.5
3.5
1.5
3.5
Clks
37
BGACK Asserted to BG Negated
1.5
3.5
1.5
3.5
1.5
3.5
1.5
3.5
Clks
37A
BGACK Asserted to BR Negated
0
1.5
0
1.5
0
1.5
0
1.5
Clks
396
BG Width Negated
90
-
75
60
45
-
ns
BG Width Asserted
90
-
-
39A
75
-
60
-
45
-
ns
40
Clock High to DBEN Asserted (Read)
0
30
0
25
0
20
0
18
ns
41
Clock Low to DBEN Negated (Read)
0
30
0
25
0
20
0
18
ns
42
Clock Low to DBEN Asserted (Write)
0
30
0
25
0
20
0
18
ns
43
Clock High to DBEN Negated (Write)
0
30
0
25
0
20
0
t8
ns
15
-
-
5
-
ns
30
-
ns
44
RIW Low to DBEN Asserted (Write)
455
DBEN Width Asserted
45A9
DBEN Width ASserted
Asynchronous Read
Asynchronous Write
Synchronous Read
Synchronous Write
60
120
10
60
46
RIW Width Asserted (Asynchronous Write or Read)
150
46A
RIW Width Asserted (Synchronous Write or Read)
90
47A
Asynchronous Input Setup Time to Clock Low
5
47B
Asynchronous Input Hold Time from Clock Low
484
-
10
-
7
50
100
-
40
80
10
50
-
5
40
125
75
15
-
12
DSACKx Asserted to BERR. HALT Asserted
-
30
-
53
Data-Out Hold from Clock High
3
55
RIW Asserted to Data Bus Impedance Change
30
56
RESET Pulse Width (Reset Instruction)
512
57
4
8
-
20
-
25
-
3
-
100
60
2
-
0
1
-
1
1
2
8
-
18
ns
2
-
ns
45
2
ns
ns
ns
BG Negated to Bus Driven
1
Synchronous Input Valid to Clock High (Setup Time)
5
-
4
61 '3
Clock High to Synchronous Input Invalid (Hold Time)
15
-
12
-
62
Clock Low to STATUS. REFILL Asserted
0
30
0
25
0
20
0
15
ns
63
Clock Low to STATUS. REFILL Negated
0
30
0
25
0
20
0
15
ns
1
0
ns
6
-
75
59'0
0
BGACK Negated to Bus Driven
20
512
ns
60 '3
BERR Negated to HALT Negated (Rerun)
-
-
5
30
-
sa tO
25
512
-
60
3
1
15
-
ns
512
-
Clks
0
-
ns
1
Clks
2
-
-
6
-
ns
1
Clks
ns
NOTES:
,. This number can be reduced to 5 nanoseconds if strobes have equal loads.
2. If the asynchronous setup time (#47A) requirements are satisfied. the DSACKx low to data setup time (#311 and DSACKx low
to BERR low set':!E..!!!!'e (#48) can be ignored. The data must only satisfy the data-in clock low setup time (#27) for the following
clock cycle and BERR must only satisfy the late BERR low to clock low setup time (#27A) for the following clock cycle.
3. This parameter specifies the maximum allowable skew between DSACKO to DSACKI asserted or DSACKI to OSACKO asserted;
specification #47A must be met by DSACKO or OSACKI.
4. This specification applies to the first (DSACKO or OSACKlI DSACKx Signal asserted. In the absence of DSACKx. BERR is an
asynchronous input using the asynchronous input setup time (#47A).
5. CBEN may stay asserted on consecutive write eyeles.
6. The minimum values must be met to guarantee proper operation. If this maximum value is exceeded. BG may be reasserted.
7 .This specification indicates the minimum high time for ECS and OCS in the event of an internal cache hit followed immediately
by another cache hit, a cache miss, or an operand cycle.
8. This specification guarantees operation with the MC68881/MC68882. which specifies a minimum time for iSS negated to
AS
asserted (specification #13A in the MC688871MC68882 User's Manuan. Without this specification. incorrect interpretation of
specifications #9A and #15 would indicate that the MC68030 does not meet the MC68881/MC68882 requirements.
292064-19
Reprinted with permiSSion of Motorola Inc.
5-253
inter
Ap·329
NOTES (Conlinued)
9. This specificalion allows a system designer 10 guaranlee dala hold times on Ihe oulpul side of dala buffers Ihal have oulpul
enable signals generaled wilh OBEN. The liming on OBEN precludes ils use for sYl)chronous READ cycles wilh no wail slates.
10. These specifications allow system designers to guarantee that an alternate bus master has stopped'driving the bus when the
MC68030 regains control of the bus after an arbitration sequence.
II. OS will not be asserted for synchronous write cycles with no wait states.
.
12. These hold times are specified with respect to strobes (asynchronous) and with respect to the clock (synchronous). The designer
is free to use either time.
'
13. Synchronous inputs must meet specifications #60 and #61 with stable logic levels for all rising edges of the clock while AS is
asserted. These values are specified relative to the high level of the rising clock edge. The values originally published were
specified relative to the low level of the rising clock edge.
14. This specification allows ~ste~esigners to qualify the til signal of an MC6888I/MC88882 with AS (allowing 7·ns for a gate
delay) and still meet the CS to OS set~p time requirement (spec 88) of the MC68881/MC68882.
292064-20
Reprinted with permission of Motorola Inc.
5-254
intJ
AP-329
These waveforms should only be referenced in regard to the edge-ta-edge measurement of the timing specifications. They are not
intended 8S a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams
for device operation.
SO
51
S2
S3
54
S~
ClK
AD-AJ1, feD·Fe2
SIlO-SIll
AMf
itS
iiCS
AS
os
A/W
iiilii
DSiCiii
DSTcii
DO Oll
fi
Hilf
All
ASYIOCH11ONOUS
INPUTS
fiN
CIII(i!
\
Figure 11. Asynchronous Read Cycle Timing Diagram
292064-21
Reprinted with permission of Motorola Inc.
5-255
intJ
AP-329
These waveforms should onlv be referenced in regard to the edge-to-edge maasuremant of tho timing specifications. They are nOl
intended as a functional description of the input and output signals. Refer to other functional descriptions and thair related diagrams
for device operation.
so
SI
S2
S3
54
S5
so
AD-A31. fCO-fC2
SllO-SIZl
R/W
00·031
Figure 12. Asynchronous Write Cycle Timing Diagram
292064-22
Reprinted wHh permission of Motorola Inc.
5-256
AP-329
These waveforms should only be referenced in regard to the edge~to-edge measurement of the timing spe'cifications. They are not
intended as a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams
for device operation.
.
so
SI
S3
so
SI
Sl
cue
AD·All. FCIl-FC2 ---I-ud---+--I--~oL,,------..,...
SllD·SIZl
R/W
00·031
Figure 14. Synchronous Write Cycle Timing Diagram
292064-24
Reprinted
w~h
permission of Motorola Inc.
5-258
AP-329
Delay Line Information
Delay lines with tolerances of
from:
+ 1 ns
can be obtained
ECC
3580 Sacramento Drive
San Luis Obispo, CA 93403
This company can also manufacture at customer's reqUest i& delay liuli3 with iii.;·~rt~d vutput ut virtuuHy th~
same cost as their regular devices.
Other delay line manufacturers are:
Dallas Semiconductor
4350 Beltwood Parkway South
Dallas, Texas 75244
EG&G Reticon Corp.
345 Portero Ave.
Sunnyvale, CA 94086
5-259
APPLICATION
NOTE
November 1990 .
Am29000* /27960CX
Burst EPROM 'Interface
INTEL
PROGRAMMABLE MEMORY OPERATION
*Am29000 is a trademark of Advanged Micro Devices, Inc.
Order Number: 292081-001
5-260
29000/27960CX BURST EPROM INTERFACE
CONTENTS
PAGE
1.0 SIGNAL DEFINITIONS . ............ 5-262
1.1 29000 Signals ................... 5-262
1.2 279960CX Burst EPROM Control
Signals ........................... 5-262
2.0 INTERFACE REQUIREMENTS . .... 5-263
CONTENTS
PAGE
3.0 CIRCUIT DESCRIPTION ........... 5-263
4.0 29000/27960CX INTERFACE . ..... 5-263
5.0 LOGIC DETAILS ................... 5-265
APPENDIX A .......................... 5-273
27960CX Datasheet ......... : ....... 5-274
Am29000 Datasheet ................ 5-278
5-261
intJ
Ap·346
This application note describes the design of a circuit to
interface the 27960CX burst EPROM to AMD's
Am29OO0· mi9roprocessor. The 29000 microprocessor
is capable qf operating in a burst mode, accessing a
maximum of 256 long words (long word = 32 bits)
. during a burst access. The burst EPROM supports a
maximum of 4 words during a burst access. To accommodate the longer burst cycle of the 29k, the interface
has an 8-bit external counter which supplies the lower
eight addresses to the EPROMs.
'
1.1.3 BINV...,...BUS INVALID (OUTPUT)
This signal indicates that the Address Bus and related
control signals are invalid. It defines an idle cycle for
the channel.
1.1.4 IRDY-INSTRUCTION READY (INPUT)
This signal indicates that a valid instruction is on the
instruction bus.
A 1-0-0-0 burst operation (one wait-state for the first
word access and zero wait-state for the remaining three
accesses) is possible at 20 MHz using the 27960CI-20
burst EPROMs. Effectively this results in a4 words/5
clock cycles performance for this interface. A 2-0-0-0
burst operation (non-buffered system) is possible at
25 MHz/33 MHz using the 27960C2-25/33 bUrst
EPROMs. This memory interface monitors control signals from the microprocessor and provides handshake
logic for the microprocessor, and generates ADS and
BLAST signals for the burst EPROMs.
1.1.5 IREQT-INSTRUCTION REQUEST TYPE
.(OUTPUT)
This signal specifies the address space of an instruction
request, when IREQ is active:
IREOT
0-- Instruction/Data Memory Access
l-.Jnstruction Read Only Memory Access
The interface can be implemented with a 16R6D PAL,
an 8-bit counter, a 9-bit latch, a .o-type flip-flop, an
address decoder and some discrete AND and OR gates.
The discrete gates may be integrated into the control
logic PAL or another system PAL. Address and data
buffers may be required if the capacitive loading is
large.
This input is active whenever a burst-mode instruction
has been established·. It may be active even though no
instructions are currently being accessed, for example
in a suspended burst access.
SIGNAL DEFINITIONSIINTERFACE
REQUIREMENTS
1.2 27960CX Burst EPROM Control
Signals
1.0 SIGNAL DEFINITIONS
1.2.1 ADS-ADDRESS STROBE (INPUT)
1.1 29000 Signals
Indicates the start of a new bus access. It is active low
in the first clock cycle of a bus access,
This section describes the 29000 signals which are relevant to this interface.
1.2.2 BLAST-BURST LAST (INPUT)
1.1.1 IREQ---;INSTRUCTION REQUEST (OUTPUT),
Terminates a concurrent burst data cycle. Must be asserted by the fourth data word.
1.1.6 IBACK-INSTRUCTION BURST
ACKNOWLEDGE (INPUT)
This signal requests an instruction access. When it is
active, the address bus has a valid address for the access.
1.1.2 IBREQ-INSTRUCTION BURST REQUEST
(OUTPUT)
This signal is used to establish a burst-mode instruction
access and to request instruction transfers during a
burst-mode instruction access.
1.2.3 CS-CHIP SELECT (INPUT)
Master device enable. When asserted, data can be written to and read from the device. In read mode, CS
enables the state machine and the I/O' circuitry. A
memory access begins on the first rising edge of CLK
after ADS and CS are asserted. CS can be de-asserted
after the number of wait-states, N, has expired, but the
EPROM will continue to burst out data for the current
cycle. If CS is de-asserted during the wait-state period,
the burst access will be aborted .
• Am29000 is a trademark of Advanced Micro Devices, Inc.
5-262
intJ
Ap·346
2.0 INTERFACE REQUIREMENTS
3.2 Burst Suspension
The interface is designed to work in the burst
mode,with the instruction burst acknowledge signal,
IBACK, as the handshake for the microprocessor indicating that the EPROM memory is capable of supporting a burst access. The interface logic will monitor control signals from the microprocessor, i.e., IREQ,
IBREQ, BINV, and generate IRDY and IBACK for
the microprocessor and ADS and BLAST signals for
the 27960 EPROM. Since the burst EPROM is capable
of bursting a maximum of four words, the interface will
suspend the burst after the fourth word by de-asserting
IRDY and resume the burst by re-asserting IRDY one
clock cycle later. The interface will preempt the burst
access in response to the burst access being suspended
by the microprocessor.
The burst-mode instruction access may be suspended in
certain situations. The processor suspends a burst-access by de-asserting IBREQ. The burst-mode access remains suspended unless the processor requests a new
instruction access (in which case IREQ is asserted), or
unless the instruction memory preempts the burstmode access. A suspended burst-mode instruction becomes active whenever the processor activates the
burst-mode access by assertmg l1:lKbI..!.
3.3 Burst Preemption
3.0 CIRCUIT DESCRIPTION
A burst access is preempted by de-asserting IBACK. If
IBREQ was active in the cycle before IBACK was deasserted, one last word of information must be transferred before the burst access is ended. The last word
can be transferred in the same cycle that the Burst Acknowledge is de-asserted or some later cycle, but until
it is transferred the burst access is not complete and no
new access of the memory may begin.
This section describes the burst-mode operation of the
29000 microprocessor followed by a description of the
interface circuit as shown in Figure 1.
4.0 29000/27960CX INTERFACE
(FIGURE 1)
3.1 Burst-Mode Access
4.1 Burst EPROMS .
The burst mode-access allows mUltiple instructions or
data words at sequential addresses to be accessed with a
single address transfer. A burst access is requested via
the Instruction Burst Request (IBREQ). The initial address of this burs.t access is indicated by assertion of
Instruction Request (IREQ) signal. The memory system may assert Instruction Burst Acknowledge
(IBACK) to indicate that it supports burst-mode accesses. If IBACK is asserted while the initial address
appears on the address bus, the burst-mode access is
established. In the following cycle, the 29k will de-assert the IREQ signal and remove the initial address of
the burst access, but will continue to assert IBREQ. If
the burst-mode is never established, the default behavior is to have the processor transmit an address every
access. After the burst-mode access is established,
IBREQ is used during subsequent accesses to indicate
that the processor requires at least one more access. If
IBREQ is active at the end of a cycle in which an access
is successfully completed (IRDY is active), the processor requires another access.
The memory block consists of 27960CX, 128k x 8-bit
burst EPROMs. A minimum of four EPROMS are required for a 32-bit system. The 27960CX supports
burst-mode operation, and is capable of accessing four
long words (long word = 32 bits) during a burst cycle.
Each burst cycle begins with a valid address be~
latched in the first clock cycle, when both ADS and CS
are asserted. After a set number of wait-states (lor 2),
data is output one word at a time on each subsequent
clock cycle. A burst access is terminated with the
BLAST signal. A 1-0-0-0 burst operation (1 wait-state
for the first word access and zero wait-state for subsequent accesses) is possible at 20 MHz using 27960Cl20 burst EPROMs. A 2-0-0-0 burst operation (nonbuffered system) is possible at 25 MHz/33 MHz using
the 27960C2-25/33 burst EPROMs.
Figure 1 shows the block diagram of the 29000/
27960CX Burst EPROM interface.
4.2 Address/Instruction Bus Buffers
The address and instruction buses may be buffered with
high speed buffers. If the memory block were made up
of multiple banks of memory devices, the instruction
bus might need buffering to isolate the heavier capacitive load of multiple memory banks from the rest of the
system. Also address buffers may be needed to drive
address inputs of multiple banks.
5-263
intJ
AP-346
I
l!l
I§
~
lU
~
N-
"
~
I
~ aD
I§ ~ ~. E~
"
ij
I
-
l!l
I~
-
is
~
N-
~ ..r 1:111
"
~
1
iU I
D
..rI
~
~
~~
i!!
~
Ie-
-
II
~
NOTES:
The discrete gates in this design could be integrated in an another system PAL or a bigger PAL could be used.
Address and data boffers are required if capacitive loading is large.
Figure 1. 29000/27960CX Interface
5-264
Ap·346
4.3 Address Latch and Counter
A registered PAL output will be represented by : =
To support burst accesses, the lower eight address bits
to the burst EPROMs come from a loadable counter.
The 8-bit counter is built from 74FCT191 4-bit binary
counters. These high speed counters are needed if the
access is to begin in the first clock cycle when IREQ is
asserted: If the initial access begins in the second clock
cycle, i.e., ADS is generated in the next clock cycle
following assertion of IREQ, a slower 8-bit counter
may be used. The upper eight bits need not come from
a counter, since the 29k will always output a new address when a 256-word boundary is crossed. The upper
8 bits of address are simply latched.
A combinatorial PAL output will be represented by =
5.1 Signal Descriptions
A 16R6D PAL is used to general IRDY, ADS,
BLAST, and !BACK. A modulo 5 counter is implemented in the PAL which is used to generate timings
to
...................
lUI
~
.. T"A.
.
8. Asynchronous Inputs include: WAm. iNTFi,-iNiR,. "i"RAP.-TRAP,. and CNTL,-CNTL".
9. RESET is an asynchronous input on assertion/deassertion. As an option to the user. ~ deassertion can be used to
force the state of the internal divide-by-two flip-flop to synchronize the phase of SYSCLK (H internally generated) relative to RESETIINCLK.
.
.
10. WARN has a minimum pulse width requirement upon deassertion.
11. To guarantee Storelload with one-cycle memories. 0,,-0. must be asserted relative to SYSCLK lalling edgelrom an
external drive source.
12. Refer to Capacitive Output Delay table when capacitive loads exceed 80 pF.
13. When used as an input. SYSCLK presents a 90-pF max. load to the external driver. When SYSCLK is used as an output. timing is specified with an external load capacitance of s 200 pF.
, 4. Three-State Output Inactive Test Load. Three-Slale Sy'nchronous Output Invalid Delay is measured as the time to a
±500 mV change from prior output level.
'
, 5. When a three-state output makes a synchronous transition Irom a valid logic level to a high-impedance state. data is
guaranteed to be held valid for an amounl of time equal to the lesser of the minimum Three-State Synchronous Output
Invalid Delay and the minimum Synchronous OiJtput Valid Delay.
Conditions:
a. All inputs/outputs are TTL compatible for V,H• VIL' VOH ' and V04. unless otherwise noted.
b. All output timing specHications are lor 80 pF of loading. .
c. All setup. hold. and delay times are measured relative to SYSCLK or INCLK ,,\nless otherwise noted.
d. All input Low levels must be driven to 0.45 V and all input High levels must be driven to 2.4 V except SYS~LK.
292081-20
Am29000TM
PRELIMINARY
Reprinted with permission of Advanced Micro Devices, Inc.
5-282
inter
AP-346
SWITCHING WAVEFORMS
~r~
•
CD
0-+1 rVee-I.O V
I.SV
O.BV
@
• +---@-+
SYSClK
Synchronous
Outputs
SYSClK
Synchronous
Outputs
I.SV
1.5 V
I.SV
1.5 V
-.~
~
Synchronous Inputs
1.5 V
Relative to SYSCLK
292081-21
Am29000TM
PRELIMINARY
Reprinted with permission of Advanced Micro Devices, Inc.
5-283
AP-346
SWITCHING WAVEFORMS
INCLK
J,-,sv-----{~f---~.~
1~4~--------~G9~--------~.~1
Asynchronous
Inputs
1.5V
1.5 V
INCLK and Asynchronous Inputs
292081-22
Am29000TM
PRELIMINARY
Reprinted with permission of Advanced Micro Devices, Inc.
5-284·
inter
~OO~Il.O~OOOb:\OOW
Ap·346
SWITCHING WAVEFORMS
:
t
}
G)
~
SYSCLK Definition
1.5V
SYSCLK
INCLK
O.BV
2.0V
1.5V
I+-----{ 12}----+I
INCLK to SYSCLK Delay
292081-23
Am29000TM
PRELIMINARY
Reprinted with permission of Advanced Micro Devices, Inc.
5-285
inter
Ap·346
Capacitive Output Delays·
For loads greater than 80 pF
This table describes the additional output delays for capacitive loads greater than 80 pF. Values in the Maximum
Additional Delay column should be added to the value listed in the Switching Characteristics table. For loads less
than or equal to 80 pF, refer to the delays listed in the Switching Characteristics table.
\
No.
6
Parameter Description
Synchronous SYSCLK Output Valid Delay
6A
Synchronous SYSCLK Output Valid Delay for 0 3 ,-0.
8
Synchronous SYSCLK Output Valid Delay
19
BINV Synchronous Output Valid Delay from SYSCLK
Total
External
Capacitance
100pF
150 pF
200pF
250pF
300 pF
100 pF
150 pF
200pF
250 pF
300pF
100 pF
150 pF
200 pF
250 pF
300 pF
100 pF
150 pF
200 pF
250pF
300 pF
Maximum
Additional
Delay
+1 ns
+2 ns
+4ns
+6 ns
+8 ns
+1 ns
+6ns
+10ns
+15 ns
+19 ns
+1 ns
+2 ns
+4ns
+6 ns
+8 ns
+1 ns
+3ns
+4ns
+6 ns
+7ns
SWITCHING TEST CIRCUIT
VL
~
P
IOL
= 3:2 rnA
q
.i
-
v_" ' "
I
CL .
I
Am29000
Pin Under Test
I
-
I"" - 400l1A
090758-00'11.
ICOO1030
V.
"
CL is guaranteed to 80 pF. For capacitive loading greater
than 80 pF, refer to the Capacitive Output Delay table.
292081-24
Am29000TM
PRELIMINARY
Reprinted with permission of Advanced Micro Devices, Inc.
5-286
RELIABILITY
REPORT
RR-35
November 1990
EPROM RELIABILITY
DATA SUMMARY
Order Number: 210473-007
5-287
RR-35
INTEL EPROM
RELIABILITY DATA
SUMMARY
CONTENTS
PAGE
The Importance of Reliability ......... 5-289
EPROM Reliability Data Summary .... 5-289
EPROM Reliability Testing ............ 5-289
CERDIP:
D2732A .............................
D2764A .............................
D27128A ............................
D27256 .. : ...........................
D27C256 ............................
D87C257 ............................
5-294
5-296
5-298
5-300
5-302
5-304
PLASTIC:
P2764A ..............................
P27128A ............................
P27256 ..............................
PIN27C256 ..........................
5-310
5-312
5-314
5-316
Appendix A. Failure Rate
Calculations for 60%
Upper Confidence Level .............. 5-319
Appendix B. EPROM Bit Maps
and Die Photos ....................... 5-325
5-288
inter
RR-35
THE IMPORTANCE OF RELIABILITY
Reliability of the non-volatile memories in your end
product is critical to your total system reliability. The
use ofIntel EPROMs can make a difference. Reliability
is not just tested, but designed into each component
Intel manufactures.
QUALITY
*-
RELIABILITY
A quality component is one that meets your specification when received and tested. A reliable component
continues to meet your specification even years after
you have shipped your product. While Intel is a quality
leader, we also adhere to stringent reliability standards
which we have established for ourselves.
Consider Quality v~. Reliability
The true cost of any component involves more than just
the purchase price. The true component cost encompasses the initial purchase price, cost of rework during
system production, and the cost of field repairs due to
component failures. "Rework" costs during system
production are incurred prior to shipment of your end
product, and are a function of the quality of the component you purchase.
Repair costs incurred in the field after end product
shipments, are a function of the reliability of the components. In addition to the increasing real cost of a
system field service call, there is the intangible cost of a
poor reliability reputation to the end user of your product. These costs depend upon the reliability of the components you purchase. Thus, reliability may impact
costs during the system lifetime more than the initial
quality of the components!
MONITOR PROGRAM
Reliability is designed into each component Intel manufactures. From the moment the design is put to paper,
stringent reliability standards must be met at each step
for a product to bear the Intel name.
Designing-in reliability, however, is only the beginning.
Ongoing tests must be conducted to ensure that the
original reliability specifications remain as valid in volume production as they were when the device was first
qualified.
Intel's Reliability Monitor Program, devised to measure and control device reliability in production, is a
proven tool that Intel has used for seven years and is
now available to its customers. The Monitor Program
subjects all of Intel's technologies to a 48 hour dynamic
bum-in at 125°C (with a portion of these devices con-
tinued for a 1000 hour lifetest) and provides answers
about device reliability that are not generally available
from limited testing programs. But it's much more than
bum-in and device testing. When test rejects are encountered, failure analysis is performed on each failed
part. Isolating the fault and determining the failure
mechanism is a critical part of the Monitor Program. It
is the most comprehensive reliability program anywhere.
The paramount objective is to cieiiver reiiaoie, quaiiry
devices. Actions that Intel takes to meet this objective
may include a process or design change, or added reliability screen. Each decision is made with our customers in mind so that they ·receive the parts-and the
performance-that they ordered by specifying Intel.
Reliability qualification assures that all new production
meets Intel's reliability standards. The Reliability Monitor Program ensures that these high standards are
continually maintained, day in, day out, over the duration of a device's life. This reliability improves the lifetime reputation of your product, reducing the required
number of field service calls.
EPROM RELIABILITY DATA SUMMARY
Intel routinely publishes this "EPROM Reliability
Data Summary", a continuing update of reliability information covering Intel's entire EPROM product line.
This document includes a discussion on EPROM reliability testing methodology and the most current failure rate calculations, failure analyses and lifetest results.
Intel's commitment to the reliability of our products is
clearly reflected in the information we make available
. to customers. We beli,eve that supplying detailed reliability information to our customers is part of the total
solution Intel offers, and is an important part of Intel's
leadership in microelectronics technology.
EPROM RELIABILITY TESTING
Intel EPROMs undergo comprehensive testing to insure electrical reliability. This testing is done at qualification and/or during ongoing monitor checks. Where
testing differs for plastic packaged production
EPROMs, it is so noted.
Intel continually reviews its testing procedures and
makes improvements to its methodology whenever
overall reliability can be enhanced. Our goal is to be the
industry leader in delivering reliable parts and no compromises are accepted.
Information on Intel's reliability testing procedures
follows.
5-289
inter
RR-35
calculated by dividing the number of failures by the
equivalent device hours and is expressed as a %/1000
hours. To arrive at a confidence level associated failure
rate, the failure rate is adjusted by a factor related to
the number of device hours using a chi-square distribution. A conservative estimate of the failure rate is obtained by including zero failures at 0.3 eV. Devices submitted to stresses other than Iifetest received a 168 hour
Iifetest prior to stressing.
High Temperature Dynamic Lifetest-This test is used
to accelerate failure mechanisms by operating the devices at an elevated temperature of 125°C. During the
test the memory is sequentially addressed and the outputs are exercised, but not monitored or loaded. A
checkerboard data pattern is used to simulate random
patterns expected during actual use. Results of Iifetesting have· been summarized along with the failure analysis.
'The activation energies for various failure mechanisms are listed in
Table 1. For an explanation of this plot, see Appendix A.
In order to best determine long-term failure rate, all
devices used for Iifetesting are first subjected to standard INTEL testing. The 48 hour burn-in results are an
indication of infant mortality. These results are not included in the failure rate calculation. (See Figure 1 for
typical burn-in bias and timing diagrams.)
,
I
1
~
.
~
/
1
10'
0
~
ID
Os
0,
05
.e 193
~
10'
04
= DE = PGM =
Vpp
=
S.2SV, R
=
0.3 eV
./'
L
/
V
= GND, C5E = GND
/
// /
0
03
Vcc
Vss
/
1
Z
02
O.6eV/
V
/
/
~
VCC
I
I
..
21
II
/
u
24
00
1.0aV
II
I
10'
07
I
,.48
26
VCC
I
1 kn,
L
10'
V
L
V
V
1//
10·
j:/
250
200
175 150
125
100
75
TEMPERATURE 'C
50
25
210473-2
Ax
210473-1
Figure 2. Arrhenius Plot
NOTE:
Alternate Configuration is the same as Figure 3.
Binary Sequence From Ao to Ax
00-07 may be N/C
Table 1. Failure Mechanism Activation
Energies Relevant to EPROMs
Failure Mechanism
Figure 1. 2764A Burn-In Bias
and Timing Diagrams
Failure Rate Calculations-Failure rate calculations
are given for each relevant activation energy. Failure
rate calculations are made using the appropriate
energy(I,2,3,4) and the Arrhenius Plot as shown in Figure 2*. The total equivalent device hours at a given
temperature can be determined. The failure rate is then
5-290
Each
Oxide
0.3
SBCL/SBCG/MBCLlMBCG
0.6
Contamination
1.0
. . Speed Degradation
Intrinsic Charge Loss
0.3-1.0
1.4
RR-35
Failure Definitions
to further validate protection occurring during mechanical handling.
Oxide-An Oxide Failure Related Fault
SBCL-Single Bit Charge Loss
SBCG-Single Bit Charge Gain
MBCL-Multiple Bit Charge Loss
MBCG-Multiple Bit Charge Gain
Contamination-Ionic Contamination Failure
Speed Degradation-Device Speed Degraded Over Test
Programmability-Device programmability is routinely monitored through the process of programming the
devices for product monitors and qualifications. Programmability is a distinct part of a product qual. All
voltage combinations are qualified. Program margin is
measured and tested on 100% of Intel EPROM products.
A typical Iifetest bias and timing diagram is shown in
Figure 3.
V••
High Temperature 6.SV Dynamic Lifetest-This test is
A'2
used to accelerate oxide breakdown failures. The test
setup is identical to the one used for the dynamic life
test except Vee and Vpp are at 6.5V. The acceleration
factor due to this test can be found in Figure 4. This
data plus the standard dynamic Iifetest data are used to
calculate the 0.3 eV failure rate.
A,
As
As
A.
A3
A2
High Temperature Storage-This test is used to accelerate charge loss from the floating gate. The test is performed by subjecting devices containing a 98% +
programmed pattern to a 250"C bake (140" for plastic)
with no applied bias. In addition to data retention, this
test is used to detect mechanical reliability problems
(e.g., bond integrity) and process instability. This test is
sometimes referred to as Data Retention Bake Test.
Temperature Cycle-This test consists of cycling the
temperature of the chamber housing the subject devices
from -65°C to + 150"C and back. Two hundred cycles
are performed with a complete cycle taking 20 minutes.
This test is to detect mechanical reliability problems
and microcracks.
ESD Testing-This test is performed -to validate the
products tolerance to Electro Static Discharge damage.
All products incorporate ESD protection networks on
appropriate pins. Two types of tests are performed.
First, all devices are tested using Mil STD 883 test
criteria. In addition, a charged device test is performed
a:
A,
Ao
0,
00
O.
0,
05
02
D.
Vss
03
Vcc = Vpp = PGM = 5.25V
Vss = CE = OE = GND
All Outguts Floating
10,.S
Ao~
A 1-.J
I
r
AX
210473-3
Binary Sequence from Ao to Ax
Figure 3. 2764A Lifetest Bias
and Timing Diagram
Supply
Voltage
(Volts)
Oxide
Thickness
(A)
Operating
Stress
(MY/cm)
10%
20%
30%
50%
100%
HMOSE
5
700
0.714
3.2
10
32
3.2E+2
1.0E+5
HMOSIIE
5
400
1.25
7.5
55
422
2.4E+4
5.6E+8
CHMOSIIE
5
400
1.25
7.5
55
422
2.4E+4
5.6E+8
Type
Acceleration Factor at _ % Over Stress
ASSUMES:
I. No bias generators
2. Depletion loads
3. Failure rate calculations use the appropriate acceleration factor for stress voltage and maximum operating voltage (conservative).
Figure 4. Time-Dependent Oxide Failure Acceleration
'HMOS and CHMOS are patented processes of Intel Corporation.
5-291
infef
RR-35
REFERENCES
1. S. Rosenberg, D. Crook, B. Euzent, "16th Annual
Proceedings of the International Reliability Physics
Symposium," pp i9-2S, 1978.
2. J. Caywood, B. Euzent, B. Shiner, "Data Retention
in EPROMs," 1980 IEEE International Reliability
Physics Symposium.
. .
3. S. Rosenberg, B. Euzent, "HMOS Reliability" Reliability Report RR-18, INTEL Corporation, 1979.
4. N. Mielke, "New EPROM Data-Loss Mechanisms,"
1983. International Reliability Physics Symposium.
S. R.M. Alexander, "CalCulating Failure Rates From
Stress Data," April 1984 International Reliability
Physics Symposium.
NOTE:
The methodology for calculating failure rates is detailed in Appendix A.
5-292
RR-35
CERDIP Reliability Data Summary
The following data is an accumulation of recent qualification and monitor program results. Failure rate calculation methods listed in Appendix A were used to
arrive at the tabularized failure rates. Data for
CERDIP and plastic EPROMs is treated separately.
In reviewing the reliability data as presented, questions
may arise as to why lot sizes often decrease from one
test to another without a corresponding number of
identified failures. This is due to a variety of factors.
Many tests require smaller sample sizes and as a result
all parts from a previous test do not necessarily flow
through to a succeeding test.
In addition, various parts are pulled from a sample lot
when mechanical or handler problems cause failures to
occur. These "failures" are not a result of the specific
test just completed. They are removed from the sample
lot size and are not included in any failure rate calculation. It can also happen that a particular test is done
incorrectiy through human error or fauity test equipment and these suspected "invalid" failures are put
aside for retesting at a later date, decreasing the lot size
for a succeeding test. If these parts are found to be truly
defective, they are treated as failures and listed. If they
test out properly, they are removed from any calculation data base.
5-293
inter
RR-35
,
D2732A
The Intel 2732A (CERDIP) is a 32K ultraviolet erasable and Electrically Programmable Read Only Memory (EPROM).
Number of Bits:
32,768
Organization:
4Kx 8
PinOut:
24 pin, JEDEC Approved
Die Size:
Process: '
163 x 97 mil.
HMOS-E
Cell Size:
11.5 x 8.75 /LM
Programming Voltage: 21.0V
Technology
NMOS
Table 1: Reliability Data Summary
125°C Dynamic
Llfetest
6.5V Dynamic
Llfetest
Year
Burn-In
48Hrs
168 Hrs
500 Hrs
1K Hrs
48Hrs
168 Hrs
500 Hrs
1988
3/21982
5/21977
0/2112
0/2111
0/1056
0/1056
0/1055
0/0
1989
0/10998
0/10997
0/192
0/192
0/672
0/672
0/672
0/575
Totals
3/32980
5/32974
0/2304
0/2303
0/1728
0/1728
0/1727
0/575
A
B
1KHrs
Table 2: Additional Qualification Tests
250°C
Data Retention Bake
Year
1988
48 Hrs
168 Hrs
500 Hrs
4/2836
1/2830
1/2828
200 Temp
Cycles
0/858
1989
2/1419
1/1417
0/1031
01779
Totals
6/4255
2/4247
1/3859
0/1637
C
D
E
5-294
inter
RR·35
D2732A (Continued)
Table 3: Failure Rate Predictions
125°C Actual
Device Hours
_ ......... "
....... a
A
IU'"
0.01
Equivalent Hours
Ea
(eV)
..... ,..
U."
1.15 X 106
55°C
--
.... 1"'1 A
0.1.
I
0.3·VAF
,/
70°C
70°C
0.0020
0.0032
0.0002
0.0006
1
0.0001
0.0004
Combined Failure Rate:
FITs:
0.0023
23
0.0042
42
IV'
6.55 X 107
5.87 x 106
1.99 X 106
1.15 X 106
0.6 B.1.
0.6 BAKE
0.6 HVELT
1.90
5.46
3.72
5.87 x 106
1.15 X 106
1.0 B.1.
1.0 HVELT
1.93
3.79
Fail Rate %/1K Hrs
(60% UCL)
55°C
~n7
..:I.u"1' A
#
Fail
2.16)( 107
~
4.23 X 107
0
Total 0.3 eV Failures =
1
x 108
x 109
x 107
3
9
0
7.94 X 107
2.16 X 109
1.56 X 107
Total 0.6 eV Failures =
x 109
x 108
12
4.51 X 108
8.84 X 107
1
0
Total 1.0 eV Failures =
48 Hour Burn-In Infant Mortality: 91 DPM
ThetaJa
·Vcc
Icc@55
Icc@70
Icc@ 125
'=
=
=
=
=
55° C/W
5.50V
69mA
72mA
80mA
Temp with Bja
T(55) = 347.92°K
T(70) = 363.79°K
T(125) = 421.25°K
T(250) = 523.15°K
K = 8.62 X 10- 5 eVrK
BI/ELT
Accel.
Factors:
0.3
0.6
1.0
250°C Bake 0.3
Accel.
0.6
Factors:
1.0
Thermal Accel. Factors
55°C
70°C
5.7
3.7
32.4
43.5
329.1
76.8
N/A
N/A
2737.2
1081.8
N/A
N/A
Voltage Accel. Factor (VAF)
for HVELT on this process is
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.
Failure Analysis:
A. 1-column charge loss
2-SBCG
B.2-SBCG
1-ionic contamination
1-oxide breakdown
1-line corrosion
0.6 eV
0.6 eV
0.6 eV
1.0 eV
0.3eV
0.6eV
0.6eV
0.6eV
0.6eV
0.6eV
C. 5-SBCL
1-SBCG
D. 2-SBCL
E. 1-SBCL
5-295
10
inter
RR-35
D2764A
The Intel 2764A (CERDIP) is a 64K ultraviolet erasable and Electrically Programmable Read Only Memory (EPROM).
Number of Bits:
65,536
Organization:
8K x 8
PinOut:
28 pin, JEDEC Approved
Die Size:
Process:
Cell Size:
Programming Voltage:
Technology:
98 x 117 mils
HMOS II-E
6x6/LM
12.5V
NMOS
Table 1: Reliability Data Summary
12SoC Dynamic Llfetest
Burn-In
48 Hrs
168 Hrs
1988
0/15993
2/15990
0/1536
1989
0/4923
1/4921
0/192
0/20916
3/20911
0/1728
0/1728
Year
Totals
SOO Hrs
6.SV Dynamic Lifetest
1K Hrs
48Hrs
168 Hrs
SOOHrs
1KHrs
0/1536
0/768
0/192
0/384
0/768
1/768
0/0
0/383
0/383
0/285
0/1152
0/1151
1/1151
0/285
A
B
Table 2: Additional Qualification Tests
2S0°C
1988
200 Temp
Data Retention Bake
Year
Cycles
48Hrs
168 Hrs
SOOHrs
6/2063
1/2056
2/2045
0/623
1989
0/645
0/644
0/644
0/234
Totals
6/2708
1/2700
2/2689
0/857
C
D
E
5-296
RR-35
D2764A (Continued)
Table 3: Failure Rate Predictions
125°C Actual
Device Hours
....... _ , , ....... a
A IU'"
...1.~O
7.18 X 105
Equivalent Hours
Ea
(eV)
55°C
C.I'
A
Fail
70°C
., .. ..., , " .. ",7
0.3 B.L
0.3*VAF
#
..
IV'
A A
,"
I."'t .... ;",
2.16 x 108
..
,,7
1.43 X 108
1
5.25 X 107
1.46 X 109
9.55 x 10S
2
9
0
Total 0.6 eV Failures =
11
3.95 x
1.34 X
7.18 x 105
0.6 B.1.
0.6 BAKE
0.6 HVELT
1.20 x 108
3.69 x 109
3.95 x 10S
7.18 X 105
1.0 B.1.
1.0 HVELT
1.16 x 109
2.11 x 108
2.17x107
55°C
70°C
0.0013
0.0020
0.0003
0.0008
0.0000
0.0000
0.0016
16
0.0028
28
1
1
IV'
Total 0.3 eV Failures =
10s
10s
Fail Rate %/1K Hrs
(60% UCL)
2.95 X 108
5.36 X 107
0
0
Total 1.0 eV Failures =
0
Combined Failure Rate:
FITs:
48 Hour Burn-In Infant Mortality: 0 DPM
ThetaJa
Vcc
Icc @55
Icc@70
Icc@125
=
=
=
=
=
48°C/W
Temp with 0ja
T(55) = 340. WK
T(70) = 354.34°K
T(125) = 408.08°K
T(250) = 523.15°K
5.50V
48mA
45mA
40mA
K = 8.62 X 10- 5 eV/oK
BIIELT
Accel.
Factors:
0.3
0.6
1.0
250°C Bake 0.3
Accel.
0.6
Factors:
1.0
Thermal Accel. Factors
55°C
70°C
5.5
3.6
30.3
13.3
294.1
74.6
N/A
N/A
2737.2
1081.8
N/A
N/A
Voltage Accel. Factor (VAF)
for HVELT on this process is
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.
Failure Analysis:
A. l-oxide breakdown
l-MBCL
l-SBCL
B. l-oxide breakdown
c. 2-MBCL
3-SBCL
l-oxygen doner
0.3eV
O.SeV
0.6eV
0.3 eV
0.6 eV
0.6 eV
0.6 eV
D. l-MBCL
E. l-SBCL
l-MBCL
0.6eV
O.SeV
0.6eV
5-297
55
RR-35
D27.128A
The Intel 27128A (CERDIP) is a 128K ultraviolet
erasable and Electrically Programmable Read Only
Memory (EPROM). This part differs from the 27128 in
that it requires 12.5 Vpp vs. 21.0 Vpp and the process
technology is HMOS II-E vs. HMOS-E.
Number of Bits:
131,072
Organization:
16K x 8
PinOut:
28 pin, JEDEC Approved
Die Size:
Process:
Cell Size:
Programming Voltage:
Technology:
169 x 117 mils
HMOS II-E
6x6jJoM
12.5V
NMOS
Table 1· Reliability Data Summary
125·C Dynamic Lifetest
6.5V Dynamic Llfetest
Year
Burn-In
48Hrs
168 Hrs
500 Hrs
1K Hrs
48Hrs
168 Hrs
500Hrs
1K Hrs
1988
0/5953
0/5952
0/576
0/576
1/288
0/286
0/286
0/0
1989
010
0/0
010
010
0/0
0/0
010
0/0
Totals
0/5953
0/5952
0/576
0/576
1/288
0/286
0/286
010
A
Table 2: Additional Qualification Tests
250·C
200 Temp
Data Retention Bake
Y~ar
Cycles
48Hrs
168 Hrs
500Hrs
1988
1/774
01772
11771
0/234
1989
0/0
010
010
0/0
Totals
1/774
0/772
1/771
0/234
B
C
5-298
intJ
RR-35
D27128A (Continued)
Table 3: Failure Rate Predictions
125°C Actual
Device Hours
Equivalent Hours
Ea
(eV)
55°C
............ ... ,.,c,
"" ....... ,. ... "",c
0.1"+ A
1.43 X 105
1.19 x 106
3.86 105
1.43 X 105
«
0.6 B.1.
0.6 BAKE
0.6· HVELT
3.16X10 7
1.05 x 109
3.78 x 106
1.19 x 106
1.43 X 105
1.0 B.1.
1.0 HVELT
2.80
3.36
J\,
IU""
4.02
Fail
70°C
0.3 D.i.
0.3*VAF
I.I~
#
......... ,
.. "".Q
....10 A
IV'"
2.74 X 107
0
0
Total 0.3 eV Failures =
0
IV ....
x 107
1.46 X 107
4.17 X 108
1.75 X 106
0
2
1
Total 0.6 eV Failures =
3
x 108
x 107
7.78 X 107
9.32 X 106
0
0
Total 1.0 eV Failures =
0
Combined Failure Rate:
FITs:
Fail Rate %/1K Hrs
(60% UCL)
55°C
70°C
0.0020
0.0029
0.0004
0.0010
0.0000
0.0000
0.0024
24
0.0039
39
48 Hour Burn-In Infant Mortality: 0 DPM
ThetaJa
Vcc
Icc@55
Icc@70
Icc@125
=
=
=
=
=
45°C/W
5.50V
80mA
75mA
.70mA
Temp with 0ja
T(55) = 346.90o K
T(70) = 360.72°K
T(125) = 414.54°K
T(250) = 523.15°K
K = 8.62 X 10-5 eVI"K
BIIELT .
Acce!.
. Factors:
0.3
0.6
1.0
250°C Bake 0.3
Acce!.
0.6
Factors:
1.0
Thermal Accel. Factors
55°C
70°C
5.1
3.5
26.4
12.3
65.1
234.7.
N/A
N/A
2737.2
1081.8
N/A
N/A
Voltage Acce!. Factor (VA F)
for HVELT on this process is
NOTE:
FIT = Failure Unit. 1 FIT
= 1 failure per 109 device hours.
Failure Analysis:
A. 1-SBCG
B. 1-SBCL
C. 1-multi bit charge loss
0.6 eV
0.6 eV
0.6 eV
5-299
55
RR-35
027256
Intel 27256 (CERDIP) is a 256K ultraviolet erasable
and Electricaly Programmable Read Only Memory
(EPROM).
Number of Bits:
262,144
Organization:
32K x 8
28 pin, JEDEC Approved
PinOut:
Die Size:
Process:
Cell Size:
Programming Voltage:
180 x 193 mils
HMOS H-E
6x6p.M
12.5V
Technology:
NMOS
Table 1: Reliability Data Summary
Year
Burn-In
48Hrs
1988
1989
Totals
12S·C DynamiC L1fetest
168 Hrs
SOOHrs
1KHrs
0/13954
1/13909
0/1344
3/10715
4/10709
0/384
4/24669
5/24918
0/1728
A
B
6.SV Dynamic Lifetest
48Hrs
168 Hrs
SOO Hrs
1KHrs
1/1344
0/672
0/672
0/633
0/0
0/383
0/864
Q/864
0/863
0/671
0/1727
0/1536
0/1536
0/1526
0/671
Table 2: Additional Qualification Tests
2S0·C
Data Retention Bake
Year
200
Temp Cycles
48Hrs
168 Hrs
SOOHrs
1988
7/1806
8/1799
8/1790
1989
2/1404
7/1402
5/1395
0/546
9/3210
15/3201
13/3185
011091
C
0
E
Totals
5·300
0/545 .
RR-35
027256 (Continued)
Table 3: Failure Rate Predictions
12S·C Actual
Device Hours
4.39 x 10e
1.10 X 106
Equivalent Hours
Ea
(eV)
5S·C
,.. ....... ' "
0.38.L
0.3*VAF
C..e.1
A
#
Fail
70·C
.. ,,7
..
IV'
~A
"
1.'-'6f' A
...
,,7
0.6 B.1.
0.6 BAKE
0.6 HVELT
1.17 x 108
4.37 x 109
2.94 x 107
4;39 x 106
1.10 X 106
1.0 B.1.
1.0 HVELT
1.05 x 109
2.62 x 108
70·C
0.0009
0.0014
0.0009
0.0023
&.
0
Total 0.3 eV Failures =
4.39 x 106
1.59 X 106
1.10 x 106
SS·C
"
IV'
2.11 X 108
3.10 x 108
Fall Rate %/1K Hrs
(60% UCL)
2
5.41 X 107
1.73 X 109
1.36 X 107
2
37
0
Total 0.6 eV Failures =
39
2.89 X 108
7.24 X 107
1
0
Total 1.0 eV Failures =
1
Combined Failure Rate:
FITs:
0.0002
0.0020
20
0.0006
,
0.0043
43
48 Hour Burn-In Infant Mortality: 162 DPM
ThetaJa
Vee
lee@55
lee@70
lee@125
=
=
=
=
=
44°C/W
5.50V
80mA
75mA
70mA
Temp with (Jja
T(55) = 346.48°K
T(70) = 360.33°K
T(125) = 414.17°K
T(250) = 523.15°K
K = 8.62 X 10- 5 eVI"K
BIIELT
Accel.
Factors:
0.3
0.6
1.0
250° Bake 0.3
Accel.
0.6
Factors: 1.0
Thermal Accel. Factors
55°C
70°C
5.2
3.5
26.7
12.3
238.4
65.8
N/A
N/A
2737.2
1081.8
N/A
N/A
Voltage Accel. Factor (VAF)
for HVELT on this process is
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.
Failure Analysis:
A.2-SBCL
1-ionic breakdown
l-oxide breakdown
B. 2-oxide breakdown
l-package crack
l-decoder charge loss
l-single row charge loss
0.6eV
1.0eV
0.3eV
0.3eV
1.0eV
0.6eV
0.6eV
c.
6-SBCL
2-clustered bit charge loss
l-MBCL
D. 15-SBCL
E. 5-SBCL
5-clustered bit charge loss
3-MBCL
5-301
0.6 eV
0.6 eV
0.6 eV
0.6 eV
O.~ eV
0.6 eV
0.6 eV
55
RR-35
D27C256
The Intel 27C256 (CERDIP) is a 256K ultraviolet erasable and Electrically Programmable Read Only Memory (EPROM).
Number of Bits:
262,144
Organization:
Pin Out:
Die Size:
Process:
Cell Size:
Programming'Voltage:
Technology:
32K x 8
28 Pin JEDEC Approved
172 x 176 mils
CHMOS II-E
6x6J.1oM
12.5V
CMOS
Table 1: Reliability Data Summary
125°C DynamiC
Lifetest
6.5V DynamiC Lifetest
Year
Burn-In
48 Hrs
168 Hrs
500 Hrs
1K Hrs
48 Hrs
168 Hrs
500 Hrs
1K Hrs
1988
2/14976
1/14973
0/960
0/863
0/432
0/432
0/431
010
1989
0/10937
0/10931
0/1055
0/1055
0/864
0/864
0/863
010
Totals
2/25913
1/25904
0/2015
0/1918
0/1296
0/1296
0/1294
010
A
B
Table 2: Additional Qualification Tests
250°C
Data Retention Bake
Year
200
Temp Cycles
48 Hrs
168 Hrs
500 Hrs
1988
0/1934
2/1921
0/1401
1989
0/1418
2/1417
1/1414
0/702
Totals
0/3352
4/3338
1/2815
0/1092
C
D
5-302
0/390
inter
RR-35
D27C256 (Continued)
Table 3: Failure Rate Predictions
Equivalent Hours
125°C Actual
Device Hours
Ea
(eV)
'l.?'l x 106
6.47 X 105
0.38.!.
3.00
0.3*VAF
2.24
55°C
70°C
y
107
1.90'><' 107
x
108
1.41 X 108
1
0
=
1
7.59 X 107
1.62 X 109
1.04 X 106
2
3
0
=
5
4.82 X 108
6.59 X 107
0
0
=
0
Total 0.3 eV Failures
4.74 x 106
1.50 X 106
6.47 X 105
1.90 x 108
4.10 x 109
2.59 X 107
0.6 B.I.
0.6 BAKE
0.6 HVELT
Total 0.6 eV Failures
4.74 X 106
6.47 X 105
2.22 X 109
3.04 X 107
1.0 B.I.
1.0 HVELT
#
Fail
Total 1.0 eV Failures
Combined Failure Rate:
FITs:
Fail Rate O/O/1K Hrs
(600/0 UCL)
55°C
70°C
0.0008
0.0013
0.0001
0.0004
0.0000
0.0000
0.0009
9
0.0017
17
48 Hour Burn-In Infant Mortality: 77 DPM
ThetaJa
Vee
lee@55
lee@70
lee@125
=
=
=
=
=
40°C/W
5.50V
"10mA
10mA
10mA
K
=
Temp with 9ja
T(55) = 330.35°K
T(70) = 345.35°K
T(125) = 400.35°K
'T(250) = 523.15°K
BIIELT
Accel.
Factors:
8.62 X 10- 5 eVrK
250° Bake 0.3
0.6
Accel.
Factors:
1.0
0.3
0.6
1.0
Thermal Aeeei. Factors
55°C
70°C
6.3
4.0
40.1
16.0
468.9
101.7
N/A
N/A
2737.2
1081.8
N/A
N/A
Voltage Aceel. Factor (VAF)
for HVELT on this process is
NOTE:
FIT
= Failure Unit. 1 FIT = 1 failure per 109 device hours.
"
Failure Analysis:
A. I-charge loss (defect)
I-charge gain (defect)
B. I-oxide breakdown
C. 2-charge loss (defect)
2-charge loss (intrinsic)
D. l·charge loss (defect)
0.6 eV
0.6 eV
0.3 eV
0.6 eV
1.0 eV
0.6 eV
5-303
55
RR-35
D87C257
The Intel 87C257 (CERDIP) is a 256K ultraviolet erasable and Electrically Programmable Read Only Memory (EPROM) which incorporates an internal address
latch.
Number orBits:
262,144
Organization:
32K x 8
PinOut:
28 Pin JEDEC Approved
Die Size:
Process:
Cell Size:
Program1Iling Voltage:
Technology:
182 x 175 mils
CHMOS II-E
6x6tJ.M
12.5V
CMOS
Table 1: Reliability Data Summary
12S·C Dynamic Llfetest
Year
Burn-In
48Hrs
1988
0/6965
1989
0/2951
Totals
0/9916
0/9912
DID
168 Hrs
6.SV Dynamic Llfetest
SOO Hrs
1K Hrs
0/6961
DID
0/0
DID
0/2951
0/0
OlD
OlD
0/0
OlD
0/0
0/0
48Hrs
168 Hrs
SOOHrs
1KHrs
OlD
OlD
0/0
0/0
0/0
OlD
OlD
Table 2: Additional Qualification Tests
2S0·C
Data Retention Bake
Year
1988
200 Temp
Cycles
48Hrs
168 Hrs
SOOHrs
2/903
1/901
0/0
0/0
1989
0/187
1/187
0/0.
0/0
Totals
2/1090
2/1088
DID
0/0
A
B
5-304
inter
RR-35
D87C257 (Continued)
Table 3: Failure Rate Predictions
125DC Actual
Device Hours
1.19 X 1C
0
A
Equivalent Hours
Ea
(eV)
55DC
0.3*VAF
x
10A
0
0
=
0
1.90 X 107
1.98 X 108
0
0
2
0
=
2
1.21 X 108
0
0
0
=
0
!!.76
0
Total 0.3 eV Failures
1.19 x 10S
1.83 X 105
0
0.6 B.1.
0.6 BAKE
0.6 HVELT
4.16
5.01
x 107
x 108
0
Total 0.6 eV Failures
1.19
x 10S
0
1.0 B.1.
1.0 HVELT
5.58
x
Fail
70DC
7.53 x 10n
0.3 8.!.
#
108
0
Total 1.0 eV Failures
Fail Rate O/O/1K Hrs
(600/0 UCL)
55DC
70DC
0.0122
0.0192
0.0006
0.0014
0
Combined Failure Rate:
FITs:
0.0000
0.0000
0.0128
128
0.0206
206
48 Hour Burn-In Infant Mortality: 0 DPM
ThetaJa
Vcc
Icc@55
Icc@70
Icc@125
=
=
=
=
=
40 DC/W
5.50V
10mA
10mA
10mA
Temp with 6ja
T(55) = 330.35DK
T(70) = 345.35DK
T(125) = 400.35DK
T(250) = 523.15DK
K
= 8.62
X 10- 5 eV/DK
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.
Failure Analysis:
A. 1-charge 1055 (defect)
1-charge 1055 (intrinsic)
B. 1-charge 1055 (defect)
1-charge 1055 (intrinsic)
O.S eV
1.0 eV
O.S eV
1.0 eV
5-305
BI/ELT
Accel.
Factors:
0.3
0.6
1.0
Thermal Accel. Factors
55DC
70DC
6.3
4.0
40.1
16.0
468.9
101.7
N/A
250DC Bake 0.3
2737.2
Accel.
0.6
1.0
NI A
Factors:
Voltage Accel. Factor (VAF)
for HVELT on this process is
N/A
1081.8
N/A
55
inter
RR-35
Plastic Reliability Data Summary
INTRODUCTION
The following information is written to provide OTP
(one time programmable) users with the description
and reliability summary of Intel's plastic production
EPROMs in both DIP and PLCC packages. It includes
brief test descriptions, a description of plastic packaging compounds and the reliability data obtained during
the qualification and subsequent product monitors of
the P2764A, P27128A, P27256 and P/N27C256 devices.
High Temperature Extended Lifetest (HTELT)-This
test is also performed at 125°C but uses a smaller sample size. The parts are kept in the full active mode for
the duration of the test with outputs driven. The test is
intended to evaluate the long-term reliability of the
product.
PLASTIC PACKAGE
CHARACTERISTICS
High Voltage 6.5V Extended Lifetest (HVELT)-This
test is used to accelerate oxide breakdown failures. The
test is set up identical to the one used for dynamic lifetest except for Vee and Vpp which are raised to 6.5V.
The voltage acceleration factor for this configuration
on Intel HMOS lIE product has been determined to be
55 and is applicable to the 0.3 eV failure mode components.
The EPROM plastic package is composed of flame retardant plastic/epoxy which meets the rating requirements of US94VO '/." minimum. The die attach incorporates a silver-filled adhesive die attach on a silver
spot plated leadframe. Bonding is accomplished
through gold thermal compression bonding and lead
finish is either tin plated or 60/40 solder dipped tin/
lead.
High Temperature Storage-This test is used to accelerate charge loss from the floating gate. The test is performed by subjecting devices containing a 98% + program pattern to a 140·C bake with no applied bias. In
addition to data retention, this test can also be used to
detect mechanical reliability problems such as bond integrity or process instabilities. The test is sometimes
referred to as a data retention bake test.
EPROM ELECTRICAL
CHARACTERISTICS
OTP EPROMs in plastic are tested to the same electrical/parametric levels as their counterparts in CERDIP.
The characteristics include input/output voltage levels,
speeds, leakage, and power requirement characteristics
over the full commercial temperature operating range
of O·C-70·C. Performance capabilities are identical to
that of CERDIP EPROMs with speeds to 200 ns currently available.
Programmability-Device programmability is routinely monitored through the process of programming the
devices for product monitors and qualifications. Programmability is treated as a distinct part of a product
qualification. All voltage combinations are qualified.
Program margin is measured and tested on 100% of
Intel EPROM products. The new Quick-Pulse Programming™ Algorithm has been extensively verified
and the data easily surpasses the 99.5% programmability criteria of Intel's qualification requirements. Qualification results are presented in the following table:
RELIABILITY/QUALITY STRESSES
High Temperature 125°C Dynamic Lifetest (HTDL)This test is used to accelerate failure mechanisms by
operating the devices at an elevated temperature of
125°C. During the test, the memory is sequentially addressed and outputs are exercised but not monitored or
loaded. A checkerboard data pattern is typically used
to simulate random patterns expected during actual
use. Results of Iifetesting have been summarized along
with failure analysis. In order to best determine longterm failure rates, all devices used for lifetesting are
SUbjected to a standard Intel screening. The 48-hour
burn-in results measure infant mortality and are not
included in the failure rate calculations.
Product
Quantity
# Fail
% Yield
P2764A
P27128A
P27256
N27C256
8269
10,399
19,040
2079
0
2
10
1
100%
99.98%
99.95%
99.95%
MOISTURE RESISTANCE
Two types of moisture resistance testing are performed
by Intel. The first is 85·C/85% relative humidity
stressing and the second is steam stressing consisting of
121·C, 2 atm.
5-307
RR-35
Pin
OPENC 1
GROUNDC 2
5.25VC 3
GROUND C 4
3
A7
5:25V
4
As
Ground
28 POPEN
5
As
5.25V
27 pGROUND
6
A4
Ground
P 5.25V
7
A3
5.25V
25 :::J GROUND
8
A2
Ground
26
5.25V
Ao
Ground
22 :::J 5.2SV
11
00
5.25V
21 :::J GROUND
12
01
Ground
20 :::J 5.25V
13
02
5.25V
19 :::J "vV'f GROUND
14
Ground
Ground
11
18 :::J "vV'f 5.25V
15
03
Ground
12
17 :::J "vV'f GROUND
16
04
5.25V
16 :::J "vV'f 5.2SV
17
05
Ground
15 :::J "vV'f GROUND
18
Os
5.25V
19
07
Ground
5.25VC 9
S.2SV"vV'fr:. 13
r:.
Ground
A1
GROUNDC 10
GROUND
A12
9
5.25V C 7
"vV'f r:.
"vV'f r:.
Open'
2
10
GROUNDC 8
5.25 v
Str~ss
Vpp
23 :::JGROUND
5.25V C 5
GROUNDC 6
GROUND
\.J
Pin Name
1
14
24 :::I5.2SV
210473-22
20
CE
5.25V
21
A10
Ground
22
OE
5.25V
23
A11
Ground
24
A9
5.25V
25
A8
Ground
26
A13
5.25V
27
A14
Ground
28
Open'
VCC
'NMOS has pins 1 and 28 open
CMOS has Vpp and Vee at S.2SV
Figure 1. Typical 85/85 Bias Diagram
5-308
RR-35
During the,8S'C/8S% relative humidity test, the devices are subjected to a high temperature, high humidity
environment. The object of the test is to accelerate failure mechanisms through an electrolytic process. This is
accomplished through a combination of moisture penetration of the plastic, voltage potentials and contamination which, if present, would combine with the moisture to act as an electrolyte. See Figure 1 for typical
85/85 Bias Diagram.
Steam stressing accelerates moisture penetration
through the plastic package material to the surface of
the die. The objective of this test is to accelerate failures
of the device as a result of moisture on the die surface.
Corrosion, as typically seen in plastic encapsulated devices, is a very minor contributor to the EPROM failure mechanisms. Due to the floating gate storage cell
composition, EPROMs have a distinctive failure mode
which requires special considerations and solutions.
HTDL
HTELT
48·Hr
168/500/1K Hrs
\.
<.05%
I
140'C Bake
481 168/500·Hrs
The floating gate itself is a highly phosphorous doped
structure on which electrons are stored, thus creating
the non-volatile memory cell. Passivation defects or
marginalities can allow moisture penetration to a single
EPROM cell causing oxide deterioration, thus showing
up as a charge loss failure. This becomes the predominant failure mode for EPROMs, opposed to corrosion
which historically has been the dominant plastic mode
offailure. Intel has developed a proprietary, multi-layer
passivation which has successfully solved this problem.
QUALITYIRELIABILITY STANDARDS
The table below contains Intel's current requirements
for qualification for plastic OTP EPROMs. The failure
rate criteria has been established based on a survey of
major customers world-wide. Intel consistently meets
or exceeds these requirements.
I
T
HVELT
168/500/1K Hrs
I
<200 FITs Combined Failure Rate
5-309
Steam
168·Hrs
85/85
1K Hrs
<2%
<0.5% cum
RR-35
P2764A
a~indowless pl~stic .package and is
The P2764A is functionally identical to the 2764A except that it is housed in
one-time programmable."
.
Table 1: Reliability Data Summary
12S·(: Dyriamic Lifetest
6.SV Dynamic Lifetest
Year
Burn-In
48Hrs
168 Hrs
SOO Hrs
1KHrs
48Hrs
168 Hrs
500Hrs
1K Hrs
1988
1/2668
1/2667
0/384
0/384
0/192
0/192
0/192
0/0'
1989
0/0
0/0
0/0
0/0
0/0
0/0
0/0
0/0
Totals
1/2668
112667
0/384
0/384
0/192
0/192
0/192
0/0
A
B
Table 2: Additional Qualification Tests
140·C
Data Retention Bake
48 Hrs
168 Hrs
SOO Hrs
1K Hrs
200
Temp
Cycles
1988
0/0
0/0
0/514
0/514
0/156
1989
0/0
0/0
0/0
0/0
0/0
0/0
0/0
0/0
0/0
Totals
0/0
0/0
0/514
0/514
0/156
0/192
0/396
0/396
0/396
Year
168 Hrs
Steam
0/192
8S·C/8S% RH
168 Hrs
500 Hrs
1KHrs
0/396
0/396
0/396
Table 3: Failure Rate Predictions
125·C Actual
Device Hours
Ea
(eV)
6.39 X 105
9.60 X 104
0.3 B.1.
0.3*VAF
6.39 x 105
5.14 X 105
9.60 X 104
6.39 X 105
9.60 X 104
0.6 B.1.
0.6 BAKE
0.6 HVELT
1.0 B.1.
1.0 HVELT
Equivalent Hours
#
Fail
S5·C
70·C
2.98 x 106
2.44 x 107
2.08 X 106
1.71 X 107
0
0
Total 0.3 eV Failures =
0
1.39 x 107
4.06 x 107
2.09 x 106
6.79 X 106
1.60 X 107
1.02 X 106
0
0
0
Total 0.6 eV Failures =
0
1.08 x 108
1.62 x 107
3.28 X 107
4.92 X 106
1
0
Total 1.0 eV Failures =
1
Combined Failure Rate:
FITs:
Fail Rate %/1K Hrs
(60% UCL)
5S·C
70·C '
0.0033
0.0048
0.0000
0.0000
0.0016
0.0054
0.0049
49
0.0102
102
48 Hour Burn-In Infant Mortality: 375 DPM
5-310
RR-35
P2764A (Continued)
ThetaJa
, vee
lee@55
Icc@70
r.:. ..
'CC e' "'J
I
"~
=
=
=
=
_
-
103°C/W
5.25V
48mA
45mA
An_A
.... U I I . n
Temp with 8ja
T(55) = 353.96°K
T(70) = 367.33°K
T(125) = 419.63°K
_ ' ... An\ _
'\I~VI
-
BI/ELT
Accel.
Factors:
0.3
0.6
1.0
Thermal Accel. Factors
55°C
70°C
4.7
3.3
21.7
10.6
169.1
51.3
A-t" -1.:01/
"T'V.'''''\'
K = 8.62 X 10- 5 eVrK
140° Bake 0.3
Accel.
0.6
Factors: 1.0
N/A
N/A
79.0
31.2
N/A
N/A
Voltage Accel. Factor (VAF)
for HVELT on this process is = 55
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.
Failure Analysis:
A. I-microcracks
0.6 eV
B. 1-ionic contamination
1.0 eV
5-311
inter
RR·35
P27128A
The P27128A is functionally identical to the 27128A except that it is housed in a windowless plastic package and is
one-time programmable.
Table 1: Reliability Data Summary
12S·C Dynamic Llfetest .
6.SV Dynamic Lifetest
Year
Burn-In
48Hrs
168 Hrs
500 Hrs
1KHrs
48Hrs
168 Hrs
500 Hrs
1K Hrs
1988
0/2673
0/2673
0/384
0/384
0/192
0/191
0/192
0/0
1980
0/0
0/0
0/0
0/0
0/0
0/0
0/0
0/0
Totals
0/2673
0/2673
0/384
0/384
0/192
0/191
0/192
0/0
Table 2: Additional Qualification Tests
140·C Data Retention Bake
8S·C/8S% RH
48Hrs
168 Hrs
500 Hrs
1KHrs
200 Temp
Cycles
1988
0/0
0/0
0/516
0/514
0/156
1989
0/0
0/0
0/0
0/0
0/0
0/0
0/0
0/0
0/0
Totals
0/0
0/0
0/516
0/514
0/156
0/312
0/384
0/373
1/369
Year
168 Hrs
Steam
168 Hrs
500 Hrs
1K Hrs
0/312
0/384
0/373
1/369
A
Table 3: Failure Rate Predictions
12S·C Actual
Device Hours
Ea
(eV)
6.40 X 105
9.60 X 104
0.38.1.
0.3·VAF
Equivalent Hours
SS·C
70·C
2.65 x 106
2.17 x 107
1.94 X 106
1.59 X 107
Total 0.3 eV Failures =
6.40 x 105
4.28 X 105
9.60 X 104
0.6 B.1.
0.6 BAKE
0.6 HVELT
1.10X107
3.38 x 107
1.65 x 106
5.89 X 106
1.34 X 107
8.83 X.105
Total 0.6 eV Failures =
6.40 X 105
9.60 X 104
1.0 B.1.
1.0 HVELT
7.30 x 107
1.09 x 107
2.59 X 107
3.88 X 106
Total 1.0 eV Failures =
#
Fall
Fall Rate %/1K Hrs
(60% UCL)
SS·C
70·C
0.0038
0.0051
0.0000
0.0000
0.0000
0.0000
0.0038
38
0.0051
51
0
0
0
0
0
0
0
0
0
0
Combined Failure Rate:
FITs:
48 Hour Burn-In Infant Mortality: 0 DPM
RR-35
P27128A (Continued)
ThetaJa
Vee
lee@55
lee@70
Icc@125
=
=
=
=
=
95°C/W
5.25V
80 rnA
75 rnA
70mA
K
Temp with ilja
T(55) = 367.95°K
T(70) = 380.41°K
T(125) = 432.91°K
T(140) = 41::l.15°K
BI/ELT
Accel.
Factors:
=
140° Bake 0.3
Accel.
0.6
1.0
Factors:
8.62 X 10- 5 eVrK
0.3
0.6
1.0
Thermal Accel. Factors
55°C
70°C
4.1
3.0
17.1
9.2
114.1
40.4
N/A
N/A
79.0
31.2
N/A
N/A
Voltage AcceJ. Factor (VAF)
for HVELT on this process is
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.
Failure Analysis:
A. l-oxide breakdown
0.3 eV
5-313
= 55
RR-35
P27256
The P27256 is 'functionally identical to the 27256 except that it is housed in a windowless plastic package and is onetime programmable.
Table 1: Reliability Data Summary
Year
125·C DynamiC Llfetest
6.5V Dynamic Llfetest
Burn-In
48Hrs
168 Hrs
500Hrs
1KHrs
48Hrs
168 Hrs
500Hrs
1KHrs
1988
2/8706
1/8662
0/1248
0/1248
0/624
0/624
0/591
0/0
1989
0/6684
1/6680
0/288
0/288
0/624
0/615
0/615
0/470
Totals
2/15390
2/15342
0/1536
0/1536
0/1248
.0/1239
1/1206
0/470
A
B
C
Table 2: Additional Qualification Tests
140"C
Data Retention Bake .
Year
48Hrs
168 Hrs
200 Temp
Cycles
500 Hrs
1KHrs
85"C/85% RH
168 Hrs
Steam
168 Hrs
500Hrs
1KHrs
1988
0/0
0/0
2/1672
0/1669
0/468
2/1012
0/1264
0/1262
0/1243
1989
0/0
0/0
0/1031
0/1031
4/624
11780
0/960
1/960
3/956
Totals
0/0
0/0
2/2703
0/2700
4/1092
3i1792
0/2224
1/2222
3/2199
E
F
G
H
D
Table 3: Failure Rate Predictions
125·C Actual
Device Hours
3.12 x 106
8.44 X 105
Ea
(eV)
0.3 B.I.
0.3·VAF
Equivalent Hours
Fall
55·C
70·C
1.32 x 107
1.95 x 108
9.59 X 106
1.42 X 108
0
0
=
0
Total 0.3 eV Failures
3.12 x 106
2.70 X 106
8.44 X 105
0.6 B.1.
0.6 BAKE
- 0.6 HVELT
5.51 x 107
1.77 x 108
1.51 x 107
2.95 X 107
7.01 X 107
7.98 X 106
2
2
1
=
5
1.32 X 108
3.57 X 107
0
0
=
0
Total 0.6 eV Failures
3.12 x 106
8.44 X 105
1.0 B.1.
1.0 HVELT
#
3.81 x 108
1.03 x 108
Total 1.0 eV Failures
Combined Failure Rate:
FITs:
Fall Rate %/1K Hrs
(60% UCL)
55"C
70"C
0.0004
0.0006
0.0025
0.0058
0.0000
0.0000
0.0029
29
0.0064
64
48 Hour Burn-In Infant Mortality: 130 DPM
5-314
RR·35
P27256 (Continued)
ThetaJa =
Vcc =
Icc@55 =
Icc@70 =
1 __
r.;'\,-4"~
'vLi '\;;
_
1'-'tJ
90°C/W
5.25V
80 rnA
75 rnA
70mA
Temp with 8ja
T(55) = 365.85°K
T(70) = 378.44°K
T(125) = 431.0BoK
T/1An\ -
",-orv,
BI/ELT
Accel.
Factors:
0.3
0.6
1.0
Thermal Accel. Factors
55°C
70°C
4.2
3.1
17.9
9.5
122.0
42.3
Aill -t£:oV
""T'...,.ltJ.,
K = B.62 X 10- 5 eVrK
140° Bake 0.3
Accel.
0.6
Factors: 1.0
. N/A
31.2
N/A
N/A
Voltage Accel. Factor (VAF)
for HVELT on this process is = 55
NOTE:
FIT = Failure Unit. 1 FIT = 1 failure per 109 device hours.
Failure Analysis:
A. l-ionic contamination
l-MBCL
B. 2cSBCL
C. l-SBCL
D. l-scratched die
l-MBCL
. E. 3-cracked die
l-microcracks
1.0eV
0.6eV
0.6eV
0.6eV
0.5eV
0.6eV
0.5eV
0.6eV
F. l-SBCL
l-passivation. hole
l-partial row charge gain
G. l-pad corrosion
H. l-ref. generator charge gain
l-ionic contamination
l-pad corrosion
5-315
0.6eV
1.0 eV
0.6 eV
0.5 eV
0.6 eV
1.0 eV
0.5 eV
N/A
79.0
RR-35
P/N27C256
The J>/N27C256 products are functionally identical to the 27C256 except that they are housed in a windowless
plastic DIP (P) or a windowless plastic PLCC (N) package and are one-time programmable.
Table 1: Reliability Data Summary
12SoC Dynamic L:lfetest
. 6.SV Dynamic Llfetest
Year
Burn-In
48Hrs
168 Hrs
SOOHrs
1K Hrs
48Hrs
168 Hrs
SOOHrs
1KHrs
1988
0/4615
0/4607
0/672
1/663
0/336
0/334
0/333
0/0
1989
0/7355
0/7345
0/480
0/478
0/525
0/523
0/512
0/0
Totals
0/11970
0/11952
0/1152
1/1141
0/861
0/857
0/845
0/0
A
Table 2: Additional Qualification Tests
140"C Data
Retention Bake
Year
200 Temp
Cycles
168 Hrs
Sieam
8S0C/8S% RH
48Hrs
168 Hrs
SOOHrs
1KHrs
168 Hrs
SOO Hrs
1KHrs
1988
0/0
0/0
0/883
1/883
0/312
·0/542
0/700
0/697
0/697
1989
0/0
0/0
0/1031
0/1029
0/468
2/854
0/898
0/893
0/789
Totals
0/0
0/0
0/1914
1/1912
01780
2/1396
0/1598
0/1590
0/148~
B
C
Table 3: Failure Rate Predictions
12S0C Actual
Device Hours
Ea
(eV)
Equivalent Hours
#
Fail
SsoC
70°C
. 9.38 X 106
9.11 X 107
2.39 x 106
4.25 X 105
0.3 B.1.
0.3*VAF
1.47 x 107
1.43 x 108
2.39 x 106
1.59 X 106
4.25 X 105
0.6 B.I.
0.6 BAKE
0.6 HVELT
9.09 x 107
1.26 x 108
1.62 x 107
2.39 X 1Q6
4.25 X 105
1.0 B.I.
1.0 HVELT
1.03 x 109
1.83 x 108
Total 0.3 eV Failures =
3.68 X 107
4.97 X 107
6.55 X 106
Total 0.6 fJV Failures =
2.28 X 108
4.06 X 107
Total 1.0 eV Failures =
Fall Rate %/1K Hrs
(60% UCL)
55"C
70°C
0.0006
0.0009
0.0000
0.0000
0.0000
0.0000
0.0006
6
0.0009
9
0
0
0
0
0
0
0
0
0
0
Combined Failure Rate:
FITs:
48 Hour Burn-In Infant Mortality: 0 DPM
5-316
intJ
RR-35
PIN27C256 (Continued)
ThetaJa
Vee
lee@55
lee@70
Icc @125
=
=
=
=
=
88°C/W
5.25V
10mA
10mA
10mA
K
=
Temp with 8ja
T(55) = 332.62°K
T(70) = 347.62°K
T(125) = 402.62°K
T(140) = 413.15°K
BI/ELT
Accel.
Factors:
8.62 X 10- 5 eVrK
140° Bake 0.3
0.6
Accel.
Factors: 1.0
0.3
0.6
1.0
Thermal Accel. Factors
55°C
70°C
6.2
3.9
38.1
15.4
430.8
95.6
N/A
79.0
N/A
Voltage Accel. Factor (VAF)
for HVELT on this process is = 55
Failure Analysis:
A. 1 Au cratering
B. 1 Au cratering
c. 2 Ionic contamination
1.2 eV
1.2 eV
1.0 eV
5-317
N/A
31.2
N/A
inter
RR-35
APPENDIX A
Failure Rate Calculations for
600/0 Upper Confidence Level
Step 1. Collect bum-in and lifetest data for each lot after 48 hours of bum-in through lifetest for each lot.
Step 2. Determine the failure mechanism and assign an activation energy (EM for each failure, except those occurring during the first 48 hrs. (See Table 1 below.)
.
Table 1. Failure Mechanism Activation Energies
Relevant to EPROMs
Failure Mode
Activation Energy
Defective bit charge gainlloss
Oxide breakdown
Silicon defects
Contamination
Intrinsic charge loss
0.6eV
0.3eV
0.3eV
1.0-1.2 eV
1.4eV
Step 3. Calculate the total number of device hours accumulated beyond 48 hours of bum-in. (Note: 48 hour bum-in
results measure infant mortality and are not included in the failure rate calculation.)
Example: 125°C Bum-In/Lifetest for a 2 lot sample
# failures
total # devices
48 Hours
168 Hours
500 Hours
1KHours
2K Hours
Lot #1
Lot #2
0/1000
0/221
1/1000
0/201
0/999
1/201
0/998
1/100
0/994
0/99
Totals
0/1221
1/1201
1/1200
1/1098
0/1093
Device Hours
Total Device Hours
=
=
L
(Number of Devices in Stress Interval) (Number of Hours in Stress Interval)
1201 (168 hrs - 48 hrs) + 1200 (500 hrs - 168 hrs)
+ 1098 (1000 hrs - 500 hrs) + 1093 (2000 hrs - 1000 hrs)
=
1201 (120 hrs)
+ 1200 (332 hrs) + 1098 (500 hrs)
+ 1093 (1000 hrs)
=
2.185
X
106 Device Hours
5-319
RR-35
Step 4. Use EA tables to find the equivalent device hours at a desired temperature for each activation energy (failure
mechanism), or use the Arrhenius relation.
R = Aexp
K = 8.617 X 10- 5 eVI"K
A = proportionality constant
R = mean rate to failure
EA = activation energy
T = temperature in Kelvin
[-K~A]
(Boltzmann's constant)
,Where AI. = A2 = A for the same failure mechanism (i.e., sameEA>
Where RI and R2 are rates for a normal operating temp and an elevated temperature respectively.
R1 = R2 x exp [ (E:) (;2
-;1)]
However, since rate (R) has the units l/time, we can think in terms of time to one failure or MTBF.
Thus:
, 1
R1 = -where t1 = MTBF at some temperature T1
t1
and:
1
R2 = ~ where t2 = MTBF at some temperature T2
Thus the Arrhenius Relation becomes:
or:
We then define the Acceleration Factor
as:
For example: For EA = 0.6 eV, T2 = 398°K, TI = 328°K
Therefore, one hour at 125°C is equivalent to 41.7 hours at 55°C for a failure mechanism of activation energy EA =
0.6 eV. Then 41.7 is the thermal acceleration factor for time.
5-320
intJ
RR-35
NOTE:
The Arrhenius Plot (Figure 2 Page 2) is simply In (Acceleration Factor) vs. l/Temperature normalized for an
MTBF (tv of one hour at 250·C (T2)' This plot can also be used to determine the acceleration factor between two
temperatures (other than 250·C).
For example: For a 0.3 eV failure at 125·C, the acceleration factor is 8.1 relative to a 0.3 eV failure at 250·C. For a
0.3 eV failure at 25·C, the acceleration factor is 152 relative to 250·C. Therefore, the acceleration factor between
125·C and 25·C is:
.
"I: ~ !!12 = 152
8.1 =
• ••• •
1A 7
'_00
Step 5. Organize the burn-in/lifetest data by EA, Total Device Hours at the burn-in/lifetest temperature T2, Thermal Acceleration Factors for each failure mechanism (EA>, Number of Failures for each failure mechanism,
and the calculated equivalent device hours at the desired operating temperature T I.
NOTE:
The rise in junction temperature due to the thermal resistivity of the package (81A> must be added to the ambient
temperature to arrive at the actual burn-inllifetest temperature.
Ttest
= TJ + TAmbient = 6JA (IV @ TAmbienU + TAmbient
EA ('V)
Total
Device Hrs @ T2
Acceleration
Factors
# Fall
Equivalent
Hours@T1
0.3
0.6
1.0
T.D.H.
T.D.H.
T.D.H.
X
Y
Z
N1
N2
Ns
X (T.D.H.)
Y(T.D.H.)
Z (T.D.H.)
The failure rates for individual failure mechanisms and the total combined failure rate can be predicted using the
data table and the following formula:
%fail/1Khrs =
.
x2 2T
(n,a) (105)
Where ](.2 (n, a) is the value of the chi-squared distribution for n degrees of freedom and confidence level of a. The
degrees offreedom, n = [2 (# of failures) + 2] for this application. T is the total equivalent device hours at TI. The
total combined failure rate is just the sum of the individual failure rates for each failure mechanism.
For a 60% UCL, the above formula converts to the following:
I
# Failures
o
1
2
3
3 < # < 15
>15
% Fall/1K Hours (60% UCL)
0.915 x 105/T
2.02 X 105 /T
3.105 X 105/T
4.17 X 105 /T
[1.049 (#failures for a ~articuiar EA) + 1.0305] [ 10 5]
[0.2533 + ~(4 X # Failed) + 3]2 [ 5]
4T
10
.
5·321
.
inter
RR-35
Example I:
Assume for this example. that Icc active is 57 rnA at TAmbient = 125°C and ICC active is 60 rnA at
T Ambient = 55°C.
Also assume that
(JJA
= 35°C/W.
Then.
T2 = (3S'C/W) (S7 rnA) (SV)
+
12S'C,
+
SS'C
:::: 13S'C = 408'K
T1 = (3S'C/W) (60 rnA) (SV)
:::: 6S'C = 338'K
EA (eV)
Actual Device
Hours @ 125°C
Acceleration Factors
for 135°C to 65°C
Equivalent
Hours
at 55°C
# Fail
55°C
% Fail/
1KHrs
0.3
0.6
1.0
2.185 x 106
2.185x 106
2.185x106
5.85
34.18
359.93
1.278x107
7.468 x 107
7.864 x 108
0
2
1
0.0081
0.0042
0.0003
Total Combined Failure Rate =
0.0126
126 FITs
=
Example 2:
Assume that an additional lot of 800 HMOS· lIE devices is burned in using a 6.5V lifetest. Using Table 2 below. a
.
voltage acceleration factor of 55 results from a 20% overstress (5.5V to -6.5V).
Device Hours = 800 (48 hrs - 0 hrs)
= 3.997 x 105
+
48 Hours
168 Hours
500 Hours
0/800
1/800
0/799
800 (168 hrs --48 hrs)
+
799 (SOO hrs - 168 hrs)
Table 2. Time-Dependent Oxide Failure Accelerations
Type
Oxide
Operating
Supply
Voltage Thickness
Stress
(A)
(MV/cm)
(Volts)
Acceleration Factor at __ % Over Stress
10%
20%
30%
50%
100%
HMOSE
5
700
0.714
3.2
10
32
3.2E+2
1.0E+5
HMOSIIE
5
400
1.25
7:.5
55
422
2.4E+4
5.6E+8
CHMOsil E
5
400
1.25
7.5
55
422
2.4E+4
5.6E+8
ASSUMES:
1. No Bias Generators
2. Depletion Loads
3. Failure rate calculations use the appropriate acceleration factor for stress voltage and maximum operating voltage
(conservative).
5-322
inter
RR-35
Since this voltage accelerated stress is used to predict an oxide breakdown failure rate, the S.SV burn-in/lifetest SS·C
equivalent hours for EA = 0.3 eV are added to the 6.SV burn-in/lifetest SS·C equivalent hours as follows:
12S·C
Burn-ln/Lifetest
EA (eY)
Actual Device
Hours @ 12S·C
Acceleration Factors
for 13S·C to 6S·C
Equivalent
Hours
@SS·C
5.5V
6.5V
0.3
0.3
2.185 x 106
3.997 x 105
5.85
(5.85 x 55)
1.278x 107
1.286 x 108
Total Equivalent E.A.
I
= 0.3 eV Device Hours = 1.414 x 108
The following failure rate predictions include the total equivalent SS·C, EA = 0.3 eV device hours found above:
EA(eY)
0.3
0.3
+ 55(1)
0.6
1.0
Actual Device
Hours @ 125·C
Acceleration Factors
for 13S·C to 6S·C
2.185 x 106
3.997 x 105
2.185 x 106
2.185 x 106
5.85
(5.85 x 55)
34.18
359.93
Equivalent
Hours
@S5·C
1.414 x 108
7.468 x 107
7.864 x 108
# Fail
-
NOTES:
0.0015
0.0042
0.0003
1
2
1
Total Combined Failure Rate
S5·C
% Faill
1KHours
=
=
0.0060
60 FITs
(1) The notation 0.3 + 55 is used to show that 6.5V and 5.5V burn-in/lifetest equivalent hours have been combined.
(2) Additional information on calculating failure rates is contained in the April 2. 1984 International Reliability Physics Symposium editorial entitled "Calculating Failure Rates from Stress Data" by Robert M. Alexander.
"HMOS & CHMOS are patented processes of Intel Corporation.
5-323
intJ
RR-35
APPENDIX B
EPROM ·Bit Maps and Die Photos
5-325
inter
RR-35
,.
A
10 II
·..
··
··
A
A
0
7
""
""
"" ""
""
""
A
e
00
1 0
o0
o0
0
,
0
1
0
0
0
1
0
0
0
0
0
I
0
0
0
0
0
1
0
I
0
1
0
1
1
I
0
0
I
I
0
0
1
0
000
1 0 I
1 1 1
0 1 1
0
1
1
0
0
0
I
0
1 1
1 0
00
00
1
,
0
1
,
0
0
1
1
0
0
0
1
1
0
0
1
0
0
1
1
1
0
1
1
1
1
1
1 1
00
1 1
I 0
1
I
1
0
1
0
1
1
1
1
1
1
1 1
1 0
1 1
00
All
A3
A.2
AI
A
§
I H H 1111 II I (1111 III! II Ii II II 1"
1111111111111 HIIIIIIHHIIIt III
I HIC1111111111IIHIIIIIIILIIIII
Illlllllllllllllllillltlllllllll
IIIIIHIIIII(!LHIIHIOIIIIIIII
1IIIIJlllltllllltlillHIIHIIIII
IIIHIIHIII1111()llf1IIlHIIIII
1I(1I111111111111111111HIIIII(I
IHllllllllllllllfillllHlllllI1
IHIIIIIIIIIIIIIIIIIII!1t11111l1
IHIiI! I I H I l l l t l l l l l l i H H 11111
IllltllllJlllllHllHl(lll1HlI1
:1: f:l:i1 ii iliii::):;:1:l:l:::::
iii!!!!!!!1[!!!!!!!!!!!!!!!!!!!!
1111111111111(1)1111111)11111111
IIIH1I1I111I11)(11111I11111I111
1111411 H 1IIIIIIIHI!II1111HIII
1jjj1jjl11j%]1]ljjjlll11]1]]] !]]]!]!:!]11!]]]1]1]111]1]1]!]!j
::::::::::::::::::::::::::::::::
il:::::::::::i:::::::::::::::::: ]]1]1]1]11]]!1]]]1]jj!11]1]1!]]]
IHIIll1111111111111111111111111
I H II 111111 H 1111 II H H II II II HI
11111111111141111111111111111111
!!!!!!!!!!!!!!!!!!!!!!!::!:!!!!! !j!!1]!!11!]!!!!!]!]!!!!!!!]1!!!
iil1 i1i11 ~ 1i1i1~ 1~ l 1!1 iit ii~
! i i lill!!llll!l!l!l!l!l]ljlllll1!ll
I II HI I t( 1I11 H 11111111111111111
IIIHIIIlIlIIItIlIlIlIIIIIlI(IlI
11111111111111111111111111111111
11111111111111111111111111(11111
I H II H 1111(1)( II I III II 1114 11I1I
1((111111111,11111111111114)(11\
11111111111111111111111111111111
'1111111111111111111111111111111
:::::::::::::::::::::::::::::::: I:::::::::::::::::::::::::::::::
11I1I1I111111111l1011C1I111I1I1 IJlII)lIIIIHIIIIHIIIIIIICIIIII
11111111(11)1 IIIIIIIIIIHIIIIHI 1111111111111111111101111111111
1IIIIIIIIIIIIIIIIIIIIIII1111111111111HIIIIIIIIIIIIlIIIIIIIIIIII
11I1I11111I1111I1I11I1I11!!1I111111111l11111l1l1111l11l11l11l1l1
IIlHIIIIIl:IIIIIIIIlIIH)c1I1I1 1IIIIIIHII!lIIII)((I)!1I1111111
IIIHI(I(IIIIII1IlIIlI(IIJ!II)1I 11I)(lIlIllllIIIIH)111111111111
IIIJllllllIl(llIlIllIlllIlI)(l() 111111I111lHIIII)(l111l11I1I11I
1I11\111\lIHIIII)lIIIII\l11l111 \1111111111\111\11111\1111111111
:::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::
ill::::::::::::::::::::::::::::: I:::::::::::::::::::::::::::::::
I::::::::::::::::::::::::::::::: I:::::::::::::::::::::::::::::::
I::::::::::::::::::::::::::::::: ::::::::::i:::::::::::::::::::::
Hl:: UHII nn::nH l HHH::: ::::::::::::::::::: ::::::: ~:::::
I::::::::::::::::::::::::::::::: l l l 1l l1l111l111l1nUll 1l1l
I::::::::::::::::::::::::::::::: I:::::::::::::::::::::::::::::::
:::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::
I II H II II III lit 111(1111) 11111 HI
11I11l1 I I II 111111 1111111111 1(11)
11(1(II1(IIHIIIIIIHIIIIIIIIIII
11I1I1l1l1(1(1l1l101l1JiIIHII!
:i:::llil:::l:l11:l11il:l:ltl:Ji :liililil11illlllUUllililii:i:
l:l:lil::ill:ill:::lli::i::::l:l iill1:i;:::::i:::::::::;l:::::i:
iill:l::l:::::;:::::::::::::l::: iil:l:::;:::i:::::::::;:::::::::
IllllIIIIllI()llIJlIIJiIIIlIlIlI
Illllllllllllltlllllllllllllllll
IHI(Illllllllllllllllllllllll11
IIIIIHIIIIIIIIIIIIIIIlII)l1(111
11111111111111111111111111111111
1)(((IIJIHJII(IIJlIlllllllIlIII
1IIIIIIIIIlIIIIllIIIIIIIIIIIIIII
1IIIIIIIIHJIIIIIIIlIIIIIHII!i)
1)111) I II II I( IIllJllIlIHII II II)
1(1)1111111111111111111)(1111111
11111 1 III II II 10111 II )(1111 I( III
IIlIIlllllllllllIlllllIllIlllHI
111111111111111111(11)(111111111
11111111111111111111111111111111
IHIIHIIIIIIIIIIIIIIIIII)IIIIII
III II II H H 1111 111111111111 II II 1
III II II II II II)II! 111111 II I (II II 1
111111I1I!11I)IIIIO()IIIIIII)(1
I II II II II II 1I1111111111l 11111111
IlllllllIlllllllIlllI)(IIIIIIHl
1IIIIIIlIllllllIlJ(II)(1I1111111
111111l1I1I1l1l11I1111111111I1I1
11111(111)(111I11)11I111I1I1I)1I
1IIIIIIIIIIIIIIIIIIIIJI1I1I1I1I1
11111111(1111)11111111111111(111
1l11l1l(1)1111I1I1l1I1lHIIIIIIl
(1111111111111111111111111111111
11111111111111111111111111111111
1IIIIIIIIIIIIIIIIIIIIIIHlIII)(1
IIIIIHIIlIIIIII(IIIIIIlIllJllll
11I1I1l1l1l1l1l1l1l1l1l1l1111l11
:::::::::n::::::::::::::::::::: ::::::::::::::::::::::::::::::::
:::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::
It 1111111 H H IlIttl IC ICIIIIIIIII
:::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::
1IIIIIIIIlIIIIIIIIIIIIIIIIIIIIII 111111111111111111111111111111(1
11111111111111111111111111111111 11I1I(1)111111I1I)llIlIlllIllll)
1111111111111111111111111111(11111111111111111111111111111111111
11'1111111111111111111(1)11111111 IIIIIIIIIIIIIII)IIIIII!IIIIIIIII
11111 1I111111111111111(111111)() 111111111111(11)(111111((1111111
1111I111I111111111111111111111l111l1(11)IIIIIIIIIIIIIIIIIIIlIlII
IIIHIIIlIIIIIIIIIIIII(111111111 Iltll)IIIIIIIIIIIIIIIlIII\llllll
:::::::::::::::::::::::::::::::: ::::::::::::::::::::::::::::::::
IJllIIIHlIlI)IIOIHllllIlllIII 1IIIlIIIIIIllllllIIIllIIl)IJlHI
1111I1!1l1l1l1111l11l1l1l11HIIl ()lllllllIIHIIH)IlIlI((1I1l1I1
1(1)11!11111(11)111111111111!111 11111111(1111111111111111111(111
1IIIIIIIIIIIIIIIIlIlIlll(lIIIIIIIIIIIIIIIIIIIIIIIIIlIlIIIl(IIII)
!lIlllllll1l1llll1lllllJIlIIlIII 1111111111(1111\11001111111111
(1Il1lll1lllllll1l1llllllllllllJ 11I11I11I1(11\lH IIlIlIIII!I!!ll
IIIH 111111111111111111111111111 f111l111111HHI(IIIlJ(lIlll1ll)
11I!llllllllllllllll1l(111111111 1IIIIIIII111111111111111llllllli
IIIIIHIIII 11111111111111111( 1(1 ()llIlIlflllllllllllllllllll(lll
1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII(I(llll)(1I111
ttl::::::::::::::::::::::::::::: :::::::::::n:::::::::::::::::::
1111111111111111111111111111111111111111111111111111111111111111
!i!ilriiiiiiiiii!iiiiiii!l!iiiii ii!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
it:::::::::::::::::::::::::::::: it::::::::::::::::::::::::::::::
ifl:::l::::::!::::::;:::::;;;:l! 1!1:::::ll: ili::::::::l:l::::::i
IHIIIIJlIIII\lIIIIIIIIHII!(1I1
!III1I1HlIIIIIIIHIrIlIIII\l\ll
210473-5
2732A Bit Map (1 of 8 Outputs Shown)
5-326
inter
RR-35
210473-6
2732A Die Photograph
5-327
inter
RR·35
Column Selects
Yo Yl Y2 Y3 Y4 YS Y6 Y7 Y8 Yg Yl0 Yll Y12 Y13 Y14 YIS Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y2S Y26 Y27 Y28 Y29 Y30 Y31
A2 0 0
Al 0 0
AoO 0
Ala 0 0
All 0 1
0 0 0 0
0 0 0 0
0 0 1 1
1 1 0 0
1 0 o 1
0 0 0
0 0 1
1 1 0
1 1 0,
1 0 0
0 0
0
0
0
0
0
1
1
1
1
1
1
1
1
l' 1
1
1
1
0
0
1
1 ,0
1
1
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0 0
0 1
1
1
0
1
1 1
1 1
1 ,0
1
1
1
1
1
0
Row Selects
Xo Xl
A7
As
A5
A4
Aa
A12
Ag
As
0 ,0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
Bit Map for One Output
(Same for All Outputs)
X2 X3 X4 X5 X253 X254 X255
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
4-----32
COLUMNS~
Xo
Xl
x2
1
1
Array Organization
1
256
ROWS
I'
R
0
W
00
01
02
Oa
04
05
Os
07
S
x 254
x 255
E
L
'YOY1YZ
E
Y31
210473-7
C
T
Column'Select
2764A Bit Map
~-328
1
1
1
1
0
inter
RR·35
210473-8
2764A Die Photograph
5-329
(
Z DECODER)O--Al0 0 01 1 110 00 01 111 00 aD 1 11 10 00 01 11 10 00 01 1 11 00 00 11 1 10 00 01 11 10 00 01 11 1 a a
"
Y DECODER
~AO
AI
W DECODER
(OUTPUTS 0-3)·
N
(J1
CN
til
o
N
011
»
ID
::;
1
I
A13 A12 All A9
0
0
a
0
A6
0
I
A5
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
0
~
"0
··
··
·
1
1
1
1
1
1
1
1
1111 111 10 00 000 00 111 11 11 1 a 00 00 a a 01 111 11 11 00 00 000 01 11 11 11 1 a a a 00 000
A2
1111 111 11 11 111 11 000 00 00 00 00 00 00 01 111 11 11 11 11 111 10 00 00 00 00 00 00 000
A3
01 10 01 1 00 11 a 01 10 01 1 00 11 00 11 00 11 00 1 1 a 01 1 0 01 10 01 1 00 11 00 11 00 11 00 1 10
A4
0000 000 00 00 000 00 000 00 00 00 00 00 00 01 111 11 11 11 11 111 11 11 11 11 11 11 11 111
n
R DECODER
X DECODER
........
1111 000 01 11 1 a a 00 111 10 00 01 11 1 a a a 01 111 00 00 11 11 000 01 11 1 a 00 01 11 10 000
1
1
A7
0
0
A8
1
0
1
0
0
1
1
0
0
1
1
a
0
1
0
1
0
1
0
1
0
1
:JJ
:JJ
I
Co)
(1'1
0
0
1
0
1
- 0
0
1
0
210473-14
·Outputs 4-7 are mirrored images of outputs (0-3)
infef
RR-35
27128A Die Photograph
5-331
210473-15
intJ
RR-35
A4
Yo
Y1
Y2
0
0
0
•
•
•
•
•
•
XS11
0
0
0
0
0
1
0
1
0
1
•
•
1
1
1
,
WDecode
Wo
W1
W2
Wa
•
Y15
Xo
X1
X2
Address Decoding
YDecode
A1
A2
A10
X Decode
RDecode
A14 A13 A12 As A7 A6 A11 Ag As
0
0
0
0 0 0
0
0 0
0
0
0 0 0
0
0 1 .
0
1 0
0
0
0
0
0 0 0
Ao
A3
0
0
1
1
0
1
0
1
Array Organization
•
•
•
1
1
1
1
1
1
1
1
1
210473-16
Bit Map
OUTPUT 4 THROUGH 7
1--!'-~------64 COLUIoINS - - - - - - - - - I !
Yo
v,.
Y7
....-----.....-----.
YB
....-----.....-----.
W1 WOWZ W3 W1 WOWZ W3
W1 WO WZ W3 WoW, W3 W2
OUTPUT 0 THROUGH 3
!I--.--------
64
COLUIoI~S
-----------I!
210473-17
27256 Bit Map.
5-332
RR-35
210473-18
27256 Ole Photograph
5-333
inter
RR-35
Yo
Yl
Y2
..
A2
0
0
0
•
Address Decoding
Y Decode
WDecode
A1
Ao
A4
A3
A10
0
0
0
0
0
Wo
0
0
1
0
1
Wl
0
0
0
W2
1
W3
•
Y15
Xo
Xl
X2
Array Organization
X Decode
A14 A13 A12 A7 A6 As A11 A9 As
0
0
0 0 0
·0
0
0 0
0
0
0
0 0 0
0
0 1
0
0 0 0
0
0
1 0
0
•
•
'1
X510
X511
0
1
1
210473-16
Bit Map
.OUTPUT 0 THROUGH 3
'64 COLUMNS
Xo
X,
x2
•
•
•
X254
256
.ROWS
X 255
I I
1
I
Yo
• • •
Y,
Yo
'wow,'
'w,w~
210473-24
OUTPUT 4 THROUGH 7
64 COLUMNS
Xo
X,
X2
•
256
•
ROWS
X254
X255
· ~L_LILILIJLlul~I_·_·_·J~I_ILlwl~~I~~I_·_·_·~I~I~. 1
Y,
•••
Y2 • • •
'wow,'
'w,w~
210473-25
27C256 Bit Map
5-334
inter
RR-35
210473-26
27C256 Die Photograph
5-335
inter
A14
WLO
WL1
WL2
Address Decoding
X Decoders
A13 A12 A7 A6 As A11 Ag As
0
0
0 .0
0
0
0
0
0
0
0
0
0
1
0
.0
0
0
0
0
0
0
0
I
I
I
1
,1
WL510
WL511
A4
·WDecoders
W
A3
0
0
1
1
0
1
0
WO
W1
W2
W3
0
1
Array Organization·
V Decoders
Ao
A10
A2
A1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
.1
1
0
0
1
1
0
0
b
1
0
1
1
1
1
1
0
0
1
1
V
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
YO
Y1
Y2
Y3
Y4.
Y5
Y6
Y7
YB
Y9
Y10
Y11
Y12
Y13
Y14
Y15
0 0 OJ 02 0 3 0" 05 0& 07
210473-36
OUTPUT. THROUGH 7
6. COLUMNS
..II
X511
, 1,1,1,1"·1 , I,
YO
Y1
'WoW?
'WiWa
Y2. • •
'WoW?
Y104
I ,
V15
I ,1"·1
YO
Y1
'WOWl
'W2vi3
'WiWa
'Wm
210473-37
OUTPUT 0 THROUGH 3
64 COLUMNS
Xl .
XO
I
512
ROWS
X5I
X511
11
.
, I, 1,1,1"·1
Y15
Y14 Y13
'W2vi3
'W2vi3
'Wm
I,
Y1
I
YO
,
I
Y15
,
I···
I ,
Yl.
'WoW1
'WiWa
27C256 Bit Map (Six Digit Suffixes)
5-336
I ,
Yl
YO
I
'WiiVR
'WiWa
210473-38
intJ
RR-35
210473-35
27C256 Die Photograph
(Six Digit Suffix)
5-337
intJ
RR·35
A2
Yo
Y,
Y2
Address Decoding
YDecode
A1
Ao
A10
0
0
0
•
•
•
0
0
0
0
0
1
0
1
0
X Decode
A14 A13 A12 A7 As As A11 As ·Aa
0
0
0
0
0
0
0
0
0
•
•
•
X510
X511
0
0
0
.wo
W1
W2
W3
0
0
0
1
0
1
1.
Y15
Xo
X,
X2
WDecode
A4
A3
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
Array Organization
210473-16
Bit Map
OUTPUT 0 THROUGH 3
64 COLUMNS
256
ROWS
1
•••
Y,
Yo
'WOw,'
'W,W~
210473-24
OUTPUT 4 THROUGH 7
64 COLUMNS
Xo
X,
X2
•
•
256
ROWS
•
X254
X255
•••
1
210473-25
87C257 Bit Map
5-338
intJ
RR-35
210473-34
87C257 Die Photograph
5-339
RELIABILITY
REPORT
RR-67
November 1990
EPROM Reliability
Data Summary
CHMOS III-E
Order Number: 293004-002
5-341
INTEL EPROM
RELIABILITY DATA SUMMARY: CHMOS III-E
CONTENTS
CONTENTS
PAGE
PAGE
D27C210 .............................. 5-354
INTRODUCTION/SCOPE .............. 5-343
D27C020 .............................. 5-356
Quality and Reliability: The Cornerstone
of Business .......................... 5-343
D27C220 .............................. 5-358
Quality versus Reliability ................ 5-343
PLASTIC RELIABILITY DATA
SUMMARY ........... _.............. 5-360
The Roots of Reliability ................. 5-343
N27C256 .............................. 5-362
MONITORS: THE CONTROL
MECHANISM OF RELIABILITY ..... 5-343
N27C010 .............................. 5-364
N27C210 .............................. 5-366
STRESSES: THE ACCELERATION OF
TIME AND USE ..................... 5-345
REFERENCES ......................... 5-346
APPENDIX A: CALCULATION OF
FAILURE RATES, 60%
CONFIDENCE ....................... 5-369
CERDIP RELIABILITY DATA
SUMMARY .......................... 5-347
APPENDIX B: BIT MAPS AND DIE
FHOiOS ............................ 5-375
D27C256 .............................. 5-348
D27C512 .............................. 5-350
D27C01 01011/100 ..................... 5-352.
5-342
inter
RR-67
Therefore, Intel advocates that you make reliability a
key consideration for the selection of your system's
components.
INTRODUCTION/SCOPE
Quality and Reliability: The
Cornerstone of Business
The Roots of Reliability
In the world of electronic hardware, no facet is more
important to the user of a system than the reliability of
its individual components. This single point has been an
instrumental factor in the philosophy of product development, qualification, and manufacturing within Intel.
Being the inventor of the EPROM, we are proud of the
continuous quality and reliability leadership position
that we have maintained.
"In the spirit of service to our customers and their customers, this publication has been assembled for your
convenience and reference. The scope of this document
is limited to Intel's latest EPROM VLSI products from
the 256 Kbit to the 2 Mbit density manufactured on
our CHMOS' III-E process technology. Other
EPROM product/process reliability summaries can be
found in the latest revision of RR-35. The data provided herein is the product of just one of Intel's qualification and reliability monitoring systems. The purpose of
this report is to supplemerit Intel's Quality and Reliability handbook with product specific data. For additional information, please contact your Field Sales or
Customer Quality Engineer.
The manufacture of a reliable VLSI semiconductor
device using a modem technology is a dynamic and
evolutionary process. Success of this process is highly
dependem upon [ite imerpiay Deiween Knuwit:ugt:auit:
and experienced manufacturing engineers, materials
physicists, and responsible/responsive management.
Only the correct combination can consistently deliver
high volumes of reliable product. In this model, the
experienced process engineer selects and defines the
stresses to be performed and the performance criteria to
be met, utilizing appropriate statistical tools and limits.
The materials physicist then determines the root causes
of failure, if and when failure occurs, and provides effective solutions and/or containment recommendations. Finally, management provides the resources for
the entire process from initial monitor to root cause
corrective action.
MONITORS: THE CONTROL
MECHANISM OF RELIABILITY
A Comprehensive Program Is The Key
Quality Versus Reliability
The traditional concepts segregating quality from reliability is one of time. Quality is a measure of the ability
of a product to meet performance expectations at a single point in time. This "point in time" is usually interpreted as your initial board power-up or incoming inspection. Reliability, on the other hand, is a measure of
a product's ability to maintain its "time zero" quality
throughout its life cycle. A reliability failure usually
occurs after your product has shipped to your customer.
The cost of poor quality can be objectively totalled
within your organization. It includes the cost of detection and in-house repair. However, the cost of poor
reliability has a much higher cost. Besides an inherently
higher repair cost per defective unit, reliability failures
create customer concern about design and/or workmanship standards used in the manufacture of the
product. Loss of goodwill with your customers can
have many long term negative effects on your business.
Intel has developed and implemented many types of
reliability monitoring systems. Since continuous delivery of reliable product is of paramount importance,
most of the, monitors are in-line and are designed to
provide as close to "real time" feedback on the reliability of the product in-process as possible. The monitors
are located throughout the fab, assembly and test areas.
, The data from these monitors are an indication of process health' and overall statistical control. They are not
necessarily directly correlatable to the reliability of the
product that will ship to your location. For this reason,
a final finished product monitor which randomly selects product is used as the yardstick to measure the
success of our factory in meeting your customer's reliability goals. Figure I demonstrates the typical monitor
stress cells and flows which are periodically used on
every major product in Intel's EPROM family. A similar stress flow is also used for plastic devices. The data
presented in the device section of this report is a compilation of this monitor data plus the initial product qualification testing results.
'CHMOS is a patented process of Intel Corporation.
5-343
RR·67
STRESS DEFINITIONS:
TIC = Temperature Cycle
HV ELT = High Voltage Electrical Life Test
Bake = High Temperature Storage
Burn-In = 5.25V Electrical Life Test
. 293004-11
Figure 1. CERDIP EPROM Standard Monitor Flow
5-344
inter
RR-67
EPROM Failure Mechanisms
The typical EPROM is about 10% decoder and "special" test mode circuitry. This 10% of the circuitry is
similar in design and layout to the circuitry found in a
common logic device. Expected failure mechanisms are
therefore considered to be primarily oxide stress and
contamination based. For more information on these
and other mechanisms, please refer to the Intel Quality
and Reliability Handbook. The remaining 90% of the
EPROM area is a very dense matrix of isolated tloatmg
gate memory cells manufactured using the latest process technology. The major function of the EPROM
cell is to store a very small amount of charge on a
floating polysilicon gate, and to do so for a time period
well in excess of 20 years under normal operating conditions. Electrons are electrically injected through the
isolating oxides onto the floating polysilicon gate during programming. Because a typical EPROM cell may
only need 100,000 electrons on this floating gate to look
"programmed," it can be sensitive to leakage currents
of as little as 1 x 10- 23 amps [1]. Small amounts of
charge loss or gain in excess of intrinsic expectations
can, through time and usage, significantly raise or lower the threshold voltage of the memory cell causing the
device to functionally misread the intended pattern.
1.4ev/ 1.0e,,/
106
I;'
0
"''"
'"....o .s::"
I
104
z ...
QI!!
'<~
... "
'" r::
...J
II
,
~
~;
1
I
105
L
0.6eV/
1/
1/
103
/
102
/11
/
V
~
... 0
u~
u"o
« J:!"
"~
V
0.3eV'/
0
z
/
/
./
V
/.
101
U/ . /
100
V
250 200175150125 100 75
50
25
1/TEMPERATURE °C
293004-12
Figure 2. Arrhenius Plot and Failure Activation
Energies Relevant to EPROMs
STRESSES: THE ACCELERATION OF
TIME AND USE
Table 1. Activation Energy Table
Failure Mechanism
Acceleration Factors
In order to determine if a device's reliability performance can be accelerated, normal operating condition
failure mechanisms must be completely understood and
characterized to the accelerating stress. The familiar
Arrhenius equation is then used for the calculation of
the acceleration factor which most clos~ly approximates the condition of the stress. Figure 2 is an example of how the Arrhenius curves would appear
for the most common semiconductor failure mechanisms which are accelerated by temperature over a period of time. All known operating condition failure
mechanisms in semiconductor devices can be accelerated with the use of various stresses. These stresses include: temperature, voltage, current, moisture, mechanical stress, and radiation. Table 1 indicates the most
common failure mechanisms and their activation energies which are associated with being thermally accelerated. The mechanics of deriving an operating failure
rate (FIT rate) from these factors is described in Appendix A.
5-345
Each
Oxide
0.3
Single Bit Charge Loss/Gain
0.6
Contamination
Speed Degradation
Intrinsic Charge Loss
1.0
0.3-1.0
1.4
inter
RR-67
sheet parameters. The Memory Components Division
also periodically takes variables data on selected data
sheet parameters to monitor the stability of the process.
Low-temperature Iifetesting has also been performed on
this process to assure that no intrinsic hot electron
mechanisms are present.
Commonly Monitored EPROM
Stresses
As discussed earlier, it is important to have a comprehensive reliability monitoring program that can uncover the many potential failure mechanisms which may
have an impact to total quality, reliability and deliverability. The listing below represents only the major and
most consistently performed reliability monitor stresses. They are executed on randomly selected finished
product inventory.
DATA RETENTION BAKE
HIGH·TEMPERATURE DYNAMIC LIFETEST
(5.25V and 6.5V)
This stress is considered the most relevant of all accelerating stresses. The device is programmed with a
checkerboard data pattern to simulate a random customer pattern. It is then functionally exercised at 12S·C
at either aVec of S.2SV or 6.SV. The memory is sequentially addressed and the outputs are exercised but
not loaded. See Figure 3 for a typical bias and timing
diagram. The S.2SV stress is considered thermally accelerating only. The 6.SV stress is considered both thermally and voltage accelerating for oxide fault type
mechanisms(\). The end point electrical tests are conducted within a fixed period of time to worst case data
°7
00
0&
°s
0.
°3
0,
°2
293004-3
m: = +ov R = 1 KIl. VJ 15
FIT Rate (60% UCL)
0.915 x 109fT
2.02 x 109 fT
3.105 x 109 fT
4.17 x 109fT
[ 1.049 (# failures for a ~rticular EA) + 1.0305] [ 10 9 ]
[0.2533
+ J(4 x
#
4T
5-371
Failed)
+ 3]2 [
9]
10
inter
RR-67
Example I:
Assume for this example, that ICC active is 57 rnA at TAmbient
55°C. I
Also assume that 6JA
=
=
125°C and ICC active is 60 rnA at TAmbient
=
35°C/W.
Then,
T2 = (35'C/W) (57 mAl (5V)
'" 135'C
T1
=
=
+
125'C
408'K
(35'C/W) (60 mAl (5V) ,: 55'C
'" 65'C = 338'K
EA (eV)
Actual Device
Hours @ 125°C
Acceleration Factors
For 135°C to 65°C
Equivalent
Hours at 55°C
# Fail
55°C
FIT Rate
0.3
0.6
1.0
2.185 x 106
2.185 x 106
2.185 x 106
5.85
34.18
359.93
1.278 x 107
7.468 x 107
7.864 x 108
0
2
1
81
42
3
126 FITs
Total Combined Failure Rate =
Example 2:
AssJ.lme than an additional lot of 800 CHMOS III-E devices is burned in using a 6.5V lifetest as shown below.
Assume further that the one failure shown at 168 hours is a 0.3 eV oxide failure. Using Table 2 below, a voltage
acceleration factor of 26 results from a 1.25V voltage overstress (5.25V to 6.5V).
Actual Device Hours = 800 (48 hrs-O hrs)
3.997 x 105
+
800 (168 hrs-48 hrs)
+
799 (500 hrs-168 hrs)
Table 2. Time-Dependent Oxide Failure Voltage Accelerations Relative to 5.25V
Type
CHMOS
III~E
Supply
Voltage
(Volts)
Oxide
Thickness
(A)
Operating
Stress
(MV/cm)
5.5V
5
235
2.15
1.9
Ufetest Stress Voltage
I
I
6.0V
7.0
I
I
6.5V
26
J
I
7.0V
93
ASSUMES:
1. Failure rate calculations use the appropriate acceleration factor for stress voltage versus 5.25V operating voltage (conservative) ..
2. Reference [2] E. Nelson Anolick.
5-372
inter
RR-67
Since this voltage accelerated stress is used to predict an oxide breakdown failure rate, the S.2SV burn-in/lifetest
SS·C equivalent hours for EA = 0.3 eV are added to the 6.SV burn-in/lifetest SS·C equivalent hours as follows:
12S·C
Burn-ln/Lifetest
EA (eV)
Actual Device
Hours @ 12S·C
Acceleration Factors
for 13S·C to 6S·C
Equivalent
Hours
@SS·C
5.25V
6.5V
0.3
0.3
2.185 x 106
3.997 x 105
5.85
(5.85 x 26)
1.278 x 107
6.079 x 107
Tnt~1 J:'nlli\l~lont
nO\li,..o
I-Inl"~
fnr n
~ t::l\lI=~ihlrjOC::
= 7
~~7
y 1n7
The following failure rate predictions include the total equivalent SS·C, EA = 0.3 eV device hours found above:
EA (eV)
Actual Device
Hours @ 12S·C
Acceleration Factors
for 13S·C to 6S·C
Equivalent
Hours
@SS·C
# Fail
SS·C
FIT
Rate
0.3 ELT
0.3 HVELT
2.185x10 6
3.997 x 105
5.85
(5.85 x 26)
7.357 x 107
1
27
0.6 ELT
0.6 HVELT
2.185 x 106
3.997 x 105
34.18
34.18
8.834 x 107
2
35
1.0 ELT
1.0 HVELT
2.185x10 6
3.997 x 105
359.93
359.93
9.303 x 108
1
2
Total Combined Failure Rate =
84 FITs
NOTES:
1. Additional information on calculating failure rates is contained in the April 2, 1984 International Reliability Physics Symposium editorial entitled "Calculating Failure Rates from Stress Data" by Robert M. Alexander.
2. 1 FIT = 1 Failure Unit = 0.0001 %/1 K hours.
5-373
inter
RR-67
APPENDIX B
EPROM Bit Maps and Die Photos
5-375
inter
RR-67
21C256
(Six Digit Suffix) Array Organization and Bitmap
f----
256 COLUMNS
-----i
ARRAY A
293004-22
ARRAY B
293004-23
OUTPUTS 0-7
64 COLUMNS (32 IN ARRAY A, 321N ARRAY B)
ARRAY B Yo
Y1
Y2
• • • • • • • • • • • • • • • • • • • • • • • • • Y31
ARRAY A Y32 Y33 Y34 • • • • • • • • • • • • • • • • • • • • • • • • • Y63
YDECODE
YOO
Y01
Y02
•
•
YS3
ARRAY SELECT
A12
A13
A10
A1
AO
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
•
•
1
1
•
•
1
•
1
•
•
•
1
•
•
X DECODE
A7
As
A5
~
A3
A2
A11
A9
As
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
•
•
•
1
1
1
1
XOO
X01
X02
0
•
•
•
•
1
1
•
X511
•
•
1
•
1
•
1
5-376
•
•
•
•
•
•
•
•
inter
RR-67
27C256 (Six Digit Suffix) Die Photograph
293004-18
5-377
inter
RR-67
27C512 Array Organization and Bitmap
293004-25
OUTPUTS 0 THROUGH 3
Xo
OUTPUTS 4 THROUGH 7
[~~~.
•
R'5
[
:~:
x,
•
• 1 - - - - - - - '28 COLUMNS - - - - - - - - 1
1 - - - - - - - '28 COLUMNS - - - - - - - 1
Roo
.{~:
Roo~+._~~+._~~+._~__~~~~~~
W7 We •• W7 We Ws
L....J
L....J
v's··· Yoo
w, •• Ws W4 W3 w2 •• W3 W2
L...J
L...J
W, Wo ••
L...J
L....J
Y,s ••• Voo
Y,s •• • Voo
L...J
w, Wo
Wo W, •• Wo W, W2 W3 •• W2 W3 W4 Ws •• W4 Ws We w7 •• WI W7
L....J
L..JL...J
L..JL...J
L..JL...J
L....J
L...J
v's··· YOD
293004-26
Voo ••• Y,s
Yoo ••• VIS
A2
Al
AO
0
0
0
0
0
0
0
0
1
0
1
0
•
•
•
•
Wo
WI
W2
•
•
1.
1
1
Y15
WDECODE
Al0
•
•
•
•
1
A5
A15
0
0
0
~
0
0
0
A3
0
0
0
0
0
1
0
1
0
ROO
ROI
. R02
X31
1
1
1
1
1
R15
•
•
A14
0
0
1
0
1
0
1
1
•
•
1
•
•
RDECODE
A6
•
•
A7
0
0
0
•
W7
Xoo
XOI
X02
•
•
A12
•
•
•
X DECODE
•
•
Yoo ••• v,s
293004-27
YDECODE
Yoo
YOI
Y02
Yoo ••• VIS
•
•
•
•
•
•
5-378
A13
All
Ag
AS
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
•
•
•
•
•
•
•
•
,
inter
RR·67
27C512 Die Photograph
293004-24
5-379
intJ
RR·67
27C010/100 Array Organization and Bitmap
COLUMNS
-5,2-
-512-
LITDJi[IIJ
ROWS
0
~
j
00 0, 02 03
04 05 0 6 07
293004-19
OUTPUTS 0 THROUGH 3
['"
OUTPUTS 4 THROUGH 7
R14
0
Xo
0
0
Roo
[~
R~,
X,
0
128 COLUMNS
0
128 COLUMNS
R, •
. .
0
0
0
0
[~
ROI
0
XI!
•
0
R15
W, We ••
LJ
w, We Ws W.... Ws W.. W3 W2 •• W:s W2 W, Wo •• w, Wo
LJ
Y,s ••• '1'00
LJ
LJ
'1"5··· Yoo
LJ
LJ
LJ
Wo
w, •• wo W, W2 W3 •• W2 W3 W.. Ws •• W" Ws We W, •• We W,
LJ
Yoo
LJ.
'1',5 ••• Yoo
Y'5 ••• Yoo
•••
LJ
LJ
LJ
LJ
'1"5
Yoo ••• '1"5
Yoo
•••
LJ
LJ
V'5
'1'00 ••• '1"5
293004-20
293004-21
WDECODE
YDECODE
YOO
YOl
Y02
•
•
Y15
Al0
A2
Al
AO
0
0
0
0
0
0
0
0
1
0
1
0
•
•
•
..•
1
1
1
•
A16
0
'0
0
Wo
Wl
W2
•
•
•
•
•
•
1
XOO
XOl
Xo2
•
•
X63
•
•
1
A5
0
0
0
•
•
1
As
0
0
0
•
•
1
A12
A14
0
0
0
0
0
1
0
1
0
•
1
A3
0
0
1
0
1
0
•
•
1
1
RDECODE
A7
•
•
A15
•
•
1
W7
X DECODE
~
0
0
0
LJ
•
•
1
•
1
5-380
A13
All
A9
AS
ROO
ROl
R02
0
0
0
0
0
0
0
0
.1
0
1
0
•
•
•
•
..•
R15
1
1
•
•
1
•
•
1
RR·67
27C010/27C100 Die Photograph
293004-7
5-381
intJ
RR-67
27C011 Array' Organization and Bitmap
COLUMNS
[In[ill
-512-
,1,
ROWS
l
-512-
0
~
00 0, 02 03
o. Os 06 07
293004-15
OUTPUTS 0 THROUGH 3
[."
OUTPUTS 4 THROUGH 7
R,.
0
Xo
0
0
Roo
x,
[~Ro,
0
128 COLUMNS
128 COLUMNS
R:5
0
0
0
0
0
['.
0
ROI
Xu
0
0
0
R'5
W~6··W~6W~4··W~.W~2··W~2W~O··W~o
Y,S ••• Yoo
Y,s ••• Yoo
Y,S ••• Yoo
We W, •• Wo W, W2 W3 •• W2 W3
L...J
Yoo
Y,S ••• Yoo
•••
L...J
L...J
YIS
Yoo
w. Ws •• W",Ws W6 w7 •• W6 w7·
L...J
L...J '
Y,s
Yoo ••• Y,s
•••
L...J
293004-16
•
•
Y15
WDECODE
Al0
A2
Al
AO
0
0
0
0
0
0
0
0
1
0
1
0
Wo
Wl
W2
•
•
•
•
1
•
•
1
•
•
•
1
•
1
•
•
X63
A3
~
A5
0
0
0
0
0
0
0
0
0
0
0
0
•
•
1
•
•
1
•
1
A7
Do
0
0
0
0
0
1
0
1
0
.•
1
W7
•
•
•
•
1
1
R DECODE
01
•
•
A12
'
X DECODE
XOO
XOl
X02
L...J
Yoo ••• Y,s
293004-17
YDECODE
Yoo
YOl
Y02
L...J
•
1
As
0
0
1
•
•
1
AS
0
1
0
•
•
A13
02
A9
All
ROO
ROl
R02
0
0
0
0
0
0
0
0
1
0
1
0
•
•
•
•
1
R15
5-382
•
1
•
1
•
•
1
•
•
1
infef
RR-67
27C011 Die Photograph
293004-7
5-383
RR-67
27C210 Array Organization and Bitmap
I
y--------------~
111111111111111111
293004-30
OUTPUTS 15 THROUGH 8
Xo
OUTPUTS 7 THROUGH 0
[:~:
•
•
Roo
Xl
[:~~
•
• 1------
64 COLUMNS
1-----
------I
64 COLUMNS
------I
R15
•
•
•
XS3
•
•
[:~~
•
•
R15
'":':W~3~W2""":W~3-::W~2-.-• •""":W~3-::W"'2~W""":1W~O-::W"'l~Wo-.-.-.-::W"',~Wo""
L.J
L.J
Y'5
Y'4.··
L.J
L.J
L.J
Yo
Y'5
Y14
Wo
•••
w, Wo w, ••• Wo W, w2 W3 w2 W3 ••• w2 W3
L.J
L.J
L.J
Yo
Yo
Yl···
L.J
L.J
Y15
Yo
L.J
YDECODE
•
•
A15
A14
Ao
0
0
0
0
0
0
0
0
1
0
•
•
•
Y15
WDECODE
A13
•
1
1
Wo
Wl
W2
W3
1
0
•
•
•
•
•
•
XS3
A7
As
A5
A4
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
•
•
1
•
•
1
A2
0
0
1
1
0
1
0
1
RDECODE
A8
•
•
Al
1
1
X DECODE
Xoo
XOl
X02
Y15
293004-9
293004-8
Yoo
YOl
Y02
L.J
Y1···
•
•
1
•
•
1
Roo
ROl
R02
•
•
•
•
1
R15
5-384
A12
All
Al0
A9
0
0
0
0
0
0
0
0
1
0
1
0
•
•
1
•
•
1
•
•
1
•
•
1
intJ
RR-67
27C210 Die Photograph
5-385
inter
RR-67
,
27C020 Array Organization and Bitmap
COLUMNS
l[]]um
-512-
g
ROWS
I
,
-512-
~
00 0, 02 03
0" 05 0 6 0,
OUTPUTS 0 THROUGH 3
['"
293004-29
OUTPUTS 4 THROUGH 7
R,.
0
Xo
0
0
ROO
x,
[~R:,•
·
·· ··
· ·
128 COLUWNS
'28 COLUMNS '
R,.
.
[~
Ro ,
X127
:
R,.
w,WS •• W7W.WS W4 •• WSW. W3 W2 •• W:s W2 w, Wo •• w, Wo
LJ
LJ LJ
LJ LJ
LJ LJ
LJ
Y,S ••• Yoo
Y,s ••• Yoo YIS ••• Yoo Y,S ••• Yoo
Wo w,
LJ
•• Wo W, W2 W:S •• W2 W:s W.. Ws •• W... Ws We W, •• w. W7
LJ
Yoo ••• Y'5
LJ
LJ
Yoo ••• Y,5
LJ
LJ
LJ
Yoo
Yoo ••• lUS
293004-13
•
•
Y15
WDECODE
Ao
A10
A2
A1
.0
.0
.0
.0
.0
.0
.0
.0
1
.0
6
..•
•
•
1
1
•
•
1
•
•
X127
A17
A16
A12
A7
.0
.0
.0
.0
.0
.0
.0
.0
.0
.0
.0
.0
•
•
1
•
•
1
•
•
1
•
•
1
A15
.0
.0
.0
1
0
.o·
•
•
1
•
•
Aa
.0
1
.0
•
•
•
•
1
W7
1
1
RDECODE
X DECODE
Xoo
X01
X02
A14
Wo
W1
W2
1
•
•
As
.0
.0
.0
•
•
1
A5
.0
.0
1
•
•
1
LJ
Y,s
293004-14
YDECODE
YOO
Y01
Y02
•••
A4
.0
1
.0
•
A13
A11
A9
As
Roo
R01
R02
.0
.0
.0
.0
.0
.0
.0
.0
1
.0
1
.0
R15
1
1
1
1
•
•
•
1
5-386
•
•
•
•
•
•
•
•
infef
RR-67
27C020 Die Photograph
293004-10
!.:' ,
5-387
inter
RR-67
27C220 Array Organization and Bitmap
0 .................................. 1023
1023 .................................. 0
o
•
•
•
•
•
•
•
07' 06
OUTPUTS 15 THROUGH 8
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
X 1022
X 1023
05
04
03
02
o
COLUMN • • • • • • • • • • • • • • • • • • • • COLUMN
IV'
0
127
~---------~,.....--~
YO ••.•••••••••.••.•••••••• : •••••• Y127
Y127 .••••••..•..•.••.••..•.•..••.•. YO
293004-6
293004-5
YDECODE
A16
•
•
Y127
0,
0
0
•
•
1
AIS
.A14
A13
A2
Al
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
~
•
1
1
•
•
•
1
•
1
•
•
1
Ao
0
1
0
•
•
•
•
1
X DECODE '
, A12
Xoo
Xol
Xo2
•
•
Xl 023
0
0
0
•
•
1
All
0
0
0
•
•
1
00
OUTPUTS 7 THROUGH 0
COLUMN . . . . . . . . . . . . . . . . . . . . . COLUMN
Yoo
YOI
Y02
01
As
As
0
0
0
!>
•
•
•
1
0
0
•
1
A3
Al0
As
As
A7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
A4'
'.•
5-388
•
•
•
•
•
•
•
•
•
•
inter
RR-S7
27C220 Die Photograph
293004-1
5-389
inter
ARTICLE REPRINT·
AR-414
Marriage Of CMOS And PLeC Sparking
Rapid Change In Mounting Memories
duce component weight as much as 75
-Is the proper assembly equipment
already available?
percent.
-Do components meet JEDEC stanLightweight PLee packages tend to
dards?
be' ideal for high-vibration industrial
he surge in circuit complexity
-Will socketing be required?
and automotive applications, as well as
over the past year or two has
The drive for smaller, more functional
for portable applications.
pushed the standard DIP size beand more competitive products is forcing
Surface mounting requires a subyond workable dimensions, and renmany engineers to scale down existing
stantial investment in capital equipdered it obsolete where high lead count
designs; to strive for VLSI solutions; and
ment. New techniques for soldering
is required.
to use PLCC packages and other surfacecomponents to boards (i.e., vapor phase
Meanwhile, the semiconductor inmount packaging options, which can reor wave soldering) must be considered
dustry's shift to CMOS processing for
duce board size dramatically.
and automated machinery such as
memories, as we,!1 as other ICs, is helpDecisions as to which surface-mount
pick-and-place assemblers must be eming usher in the era of surface-mountoption to use are usually based on boardployed-new pick-and-place machinery
able packages. Chief among these'
size restrictions. In general, PLCes
employing vacuum pickup has been depackages for memories is the plasticminimize the area footprint on a board
veloped
to handle the wide array of
, leaded chip carrier (PLCC).
for lead counts ranging from 28 to 124.
different sized packages available for
The technology for surface mountaOne example of the space-saving
surface mounting.
bles and CMOS processing emerged
ability of a PLeC package is In~l's new
Today, many different machines are
from shaky beginnings. Although sur32-lead PLCe package which it is deavailable. Their processing capacity
face-mount packaging has been availveloping for its 64k and 256k CHMOS
ranges anywhere from 500 to 500,000
able for nearly two decades, its potenEPROMS; The PLeC measures 0.45 x
de\-1ccs per hour. (SurfaCe-mounting
tial has just begun to be realized.
0.55 inch, whereas the 28-pin DIP that
technology is even used in small-volume,
Several technical problems hamwould normally be used here measures
custom facilities, such as for making porpered its early acceptance:- the need for
1.4 x 0.6 inch. The reduction in area
table medical equipment, where the deautomated factory equipment; prohibifootprint is 70 percent.
vices are manually soldered to boards.)
tively high packaging costs; and the
The contact area for chip leads can be
The benefits of factory-automated aslack of necessary construction tools.
closer for a PLCC device because the
As of 1984, only 6 percent of all commounting 'holes 'mandatory for inser- , sembly are numerous. Less floor space
ponents used in the United States were
is
required. Since raw materials are
tion devices are eliminated. Surface
contained in smaller packages, storage
surface-mount types. Industry analysts
mounting also allows components to be
predict, however, that with the inspace is diminished. Lighter-weight
placed and soldered on both sides of a pc
crease in packaging options, the availcomponents reduce shipping and hanboard where through-hole mounting is
dling expenses. Space-saving benefits
ability of development tools and the ' not employed. Depending on the comrising demand for surface-mountable
can be achieved in the layout of the
plexity and type of components reassembly equipment itself. Some mandevices, more than 25 pe~nt of compoquired in the board layout, a 35- to 60nents will be surface mounted by 1988.
ufacturers have been able to reduce the
percent reduction in board size is
required factory floor space by as much
And an estimated 128 million of the
possible.
'
as 25 percent. Other cost savings in600 million PLeCs manufactured in
To minimize total chip requirements,
clude a reduced labor force, the ability
1988 are expected to be memories.
manufacturers of products such
CMOS has had to fight a similar batas EPROMs are incorporating an adto maintain a no-shutdown assembly,
tle. Prohibitively high cost, inherently
improved reliability and reduction of
dress latch on the address and data pins
low performance (metal gates) and lack . to allow direct interface with a microinspection and rework.
of a complete lineup of products neces- _ controller or microprocessor. This
These Qenefits must outweigh, of
sary to provide low-power system solueliminates the need for an external
course, the costs of automating the factions were the chief reasons for CMOS'
tory, as well as the cost of restructuring
latch, as well as reducing board size.
slow start. But, these problems' have
and retraining.
Surface-mount elements can also renow been overcome and the number of
products combining CMOS technology
and surface-mol1nt packages is accelerating rapidly.
By Alan Hanson
T
:S. ;"'H~
PLCC Inroads
The decision to move from insertion
(through-hole) to surface-mount technology is not an easy one. The available
options are somewhat confusing:
-Are space constraints a problem?
-Is more functionality required?
-Will surface mounting make a more
competitive product?
-Will manufacturing-cost savings be
realized?
.. Letaral
Parasitic
R.u.r
Verticil
Bipolar
wV.
PNP Transistor
.
Bipolar
NPN Tranllslo
ThIs CMOS EPROM combines both n-channel and p-channel transistors onto a ptype epitaxial substrate to reduce greatly current requirements as compared with
an NMOS counterpart_
,
Ekctrrmic Engw.ring Tu... - MDNIDy. September 30. /985
Copyright" t985 by CMP Publications, Inc., 600 Community Drive, Manhasset, N.Y. 11030.
Reprinted with permission from Electronic Engineering Times.
5-390
Order Number: 295007-001
When choosing between packaging
alternatives, consideration should always be given to industry-wide standardization to avoid unnecessary design mismatching and insure
upgradeability. For example, the 32lead PLeC package was chosen for
high-density EPROMs because as
much as 512 kbits of address space is
easily contained within this package
size. Furthermore, PLCC devices with
as many as 124 J-type leads have been
I i:;i;i.iitci'~i! .....-it..L;. JE!)EC. th.~ et:!!!d~!t::!~
setting body for the industry.
A J-type lead extends out of the four
sides of a PLCC package and is tucked
under the body into small pockets. It
was chosen as the industry-standard
lead type as opposed to gull wing for
several reasons. A minimum-area footprint is best achieved with a J-Ieadgull wings extend horizontally out from
the body of the package, increasing the
required area footprint of the component. Because of their extended leads,
gull-wing devices are also at greater
risk to damage during assembly or
transporting.
J -type leads are also more aptly suited for socketing, which may be particularly important for memory components subject to periodic updates. The
J-lead PLCC does, however, have its
drawbacks, the most noticeable being
the difficulty encountered in inspecting
solder joints.
The next step for design engineers
who have decided to use PLCC components is to investigate the available
process-technology alternatives.
CMOS And PLCC Packaging
Applications ideal for both CMOS
parts and PLCC packages lie in lowpower portable products in space-constrained environments. Examples can
easily be found in the automotive, telecommunication and portable-instrument markets.
Alan Hanson is product marketing
enginaer, Intel Corp., Folsom, Calif.
CMOS' greatest strength lies in its
low-power properties. For example, intel's 27C64 CHMOS EPROM, which
combines both n-channel and p-channel transistors onto a p-type epitaxial
substrate, maintains a maximum operating current of 10 mA, standby current of 100 mA and otTers 200-ns total
access time. Its NMOS counterpart
would require six times more active
current, 200 times greater standby current and would otTer no improvement to
t~tA 1 Arr.p'j::lS time.
•
Both the 28-pln DIP and 32·leed PLCC
can hold anywllere from 32k to 512k
EPROMs. But, the carrier Is roughly a
third smaller.
PLeC packages are essential in portable applications because of their
space-saving and lightweight features.
Minimizing component packaging size,
however, achieves little if used in conjunction with bulky power supplies,
batteries and cooling devices. Because
of its low-power reql,lirements, CMOS
helps minimize the need for large power supplies and cooling devices, as well
as enhancing PLCC-device reliability.
Because of their reduced package size
and plastic construction, PLeCs are poor
beat conductors compared with the larger DIP packages. So heat-related breakdowns are more likely-heat dissipation
is generally a function of package material, length and construction of leads,
package surface area and, of course, the
5-391
power conswned by the devices.
In improving the overall integrity
and reliability of surface-mountable
components, methods must be em·
ployed to deal with thermal-management problems. The chief way to accomplish this for PLCCs is to reduce
the resistance to heat flow from the
active junction to the atmosphere.
Thermal resistance ranges from
about 40C· per watt for a 68-lead PLCC
package to more than 100C· per watt
for the 20-lead device. Copper alloy
leads, modified substrate materials,
and special heat sink~ are being used at
the package and board levels to maximize heat conduction.
In VLSI applications where increased
device functionality is required, thermal
management becomes an acute problem.
As functionality increases, power demands likewise increase. The resulting
higher operating temperatures may result in severe degradation to device operation and performance.
CMOS otTers a solution to thermalmanagement problems. For example,
the 27C64, with a maximum operating
current of 10 mA, generates 50 mW of
heat--a sixth the amount of its NMOS
counterpart.
Depending on the particular design
and application, special heat-sink designs and/or cooling fans can be reduced
or even eliminated with CMOS parts.
CMOS is particularly valuable in extended-temperature environments,
such as automotive engine-control applications where operating temperatures range from - 40·C to 80·C and as
high as 125·C. In these applications,
CMOS may be the only way to provide
reliable device operation.
CMOS also brings to a PLCC package wider Vcc tolerances and HMOS
compatability.
Support tools such as testing, soldering and programming equipment have
also become available for CMOS-based
surface-mount designs.
EET
ARTICLE
REPRINT
AR-455
One-Tilne
ProgrslDmable EPROMs
Plastic-packaged OTP EPROMs can offer the same performance
as their cerdip counterparts, while being more cost-effective.
1. Eight OTP EPROMs of varying densities stuffed in this EPROM library board store
bootstrap code, the microprocessor instruction set, and EPROM programming algorithms.
By Richard Immekus and Richard
Foehringer, Memory Components
Div., Intel Corp., Folsom, Calif.
inherent flexibility of EPROMs (they been available in plastic for years, this
can be programmed at a moment's has not been the case with EPROMs.
notice) and the rapid convergence of The essential characteristic of these
EPROM and ROM prices over the last devices, i.e., their UV-erasibility,
made packaging them in plastic exUltraviolet EPROMs (erasable, pro· few years.
tremely difficult. Some early attempts
grammable read-only memory), introwere made by various manufacturers
duced in the early 1970s, have encoun- OTPs and test
A type of device known as "one-time to produce plastic parts that incorpotered phenomenal acceptance in the
marketplace in the past few years. programmable" (OTP) EPROMs offers rl,ite a "window," similar to cerdip
Annual usage is measured today in the the same performance as its cerdip parts. These windows, however,
counterpart, yet is inherently more tended to fall out or leak during steam
hundreds of millions of units.
Where once EPROMs were used pri- cost-effective. In addition, these plastic and moisture testing and never proved
marily in R&D environments and pre- production EPROMs can now be pro- reliable.
production phases of a new product, grammed nearly 100 times faster than
Without the window, the UVtoday they are found in a multitude of cerdips. This dramatically reduces erasability feature of an EPROM is
mass-produced products ranging from throughput time and paves the way for lost and a major barrier to manufactelephones and video games to automo- cost-effective, automated on-line pro- turing OTP parts is erected. To be
biles and home computers. The pene- gramming.
useful to the customer, EPROMs must
tration into markets once .dominated
Although most memory products be received in a blank state, yet still be
by masked ROMs is both due to their (ROMs, DRAMs, SRAMs, etc.) have tested during the manufacturing pro-
Order Number: 295016-001
5-392
OTPs are preferable for auto-insertion.
cess to verify that they comply to pub·
lished specifications and that each cell
can in fact be programmed. Thus, verification entails programming, testing,
and erasure. Intel has succeeded in
refining its testing methodology to the
point that each die is individually and
thoroughly tested at the wafer level;
the wafer is then UV-erased. In addition, proprietary innovative test
modes have been incorporated into the
EPROM design to allow performance
testing at the post-packaging level.
The result is that the customer receives fully tested OTP parts with the
same guaranteed performance and
programmability found on cerdip
EPROMs.
Because plastic-packaged parts are
non-hermetic, moisture resistance is
always a concern to reliability engineers. In the semiconductor industry,
marginalities and causes oxide damage, thereby creating a leakage path
for the charge cell. Such occurrences
can readily be induced via steam "pressure cooker" testing or extended 85°C,
85 percent RH exposure, and are manifested as charge-loss taliures.
In order to provide OTP parts that
can withstand the effects of moisture
and steam - i.e., exhibit no evidence
of corrosion or charge loss and still be
erased properly when exposed to UV
light - Intel developed a proprietary
multilayer passivation process. The resulting protective layers were the last
missing element in a systems solution
to providing cost-effective production
EPROMs.
(Fig. 2) and lot-quality inspection sampling are carried out on each and every
manufacturing lot. Electrical and visual inspection is performed to a 0.1
percent acceptable quality level (AQL).
Not only is outgoing quality sampled
ana verifiea, Dut prograIIllllHuiliLy, iu~
fant mortality and long-term reliability are monitored on a weekly basis.
These tests are conducted on finished
products and, since OTPs are non-erasable, all devices used for quality and
reliability monitors must be scrapped.
The results of electrical testing carried out to date show that OTP
EPROMs are as reliable as cerdip
EPROMs. Using data from qualification and process monitor tests, the
calculated low failure rates of OTPs
Qualification
(less than 0.02 percent per 1,000 device
Every engineer knows that the tran- hours) match those of their cerdip
sition from lab-condition product de- counterparts.
In addition, moisture resistance is
exceptionally high for these plastic
OTP qualification process
OTP parts. A survey of major customConditions
Test
ers regarding needs for moisture performance
has revealed that a percentProgrammability
All voltage corners
age defect allowable (PDA) of 3 to 5
O°C, 25°C, 70°C (equivalent)
Speed performance
percent is required. Intel's in-house
Theta JA by device type
Thermal impedance of the package
qualification procedures generally re48-hrI168-hr 125°C dynamic burn-in
Burn-in
quire plastic packaged parts to withElevated temperature life test
500-hrll.000-hr 125°C dynamic life test
stand 96 hours of steam and 1,000
168-hrI125°C high-voltage ELT (6.5 V)
High·voltage ELT
hours of 85°C, 85 percent RH. This
I ,000-hrI140°C static data retention bake
Data retention bake
specification equals or exceeds that of
96-hrI16B-hr 121°C 30 psi steam
Steam
Intel's
major customers.
I,OOO-hr 85°CI85% relative humidity
85185
Many people today assume that beDescrlptlonlmethodology
Test'
cause cerdip packages are hermetic,
they are inherently more reliable and
Mil std 883, method 1010C
Temperature cycle
Mil std 883, method 10llC
better suited to production than plastic
Thermal shock
units. This was true years ago, but
Mil std 883, method 2001
Centrifuge
Mil std 883, method 2011
with the advent of automated assemBond pull
,
Mil std 883, method 2019
bly lines, and particularly autoinserDie shear
Mil
std
883,
method
2004
tion
equipment, a problem with cerdip
Lead fatigue
In-house, 2-hr 170°C, I-hr steam
usage began to emerge. It was found
Solderability
that cerdip packages occasionally chip
'Tests conducted to determine the mechanical worthiness of Intel's 28'pin OTP package.
or crack if not handled properly. Plastic packaged components, however, do
nitride is' very commonly used as a sign to mass production in a high- not experience this deficiency.
passivation layer and moisture barrier volume manufacturing environment is
Today, plastic EPROMs are prevaon ICs. With EPROMs, however, stan- difficult at best. To minimize risks and lent in most computers, video games,
dard nitride passivation is not accepta- ensure reproduceability, Intel takes modems, printers, electronic typewritble due to its non-UV-transmissive each new product through a rigorous ers, and other products. The increasing
composition. In addition, EPROMs qualification procedure (see table) in demand for highly automated assemhave a special sensitivity to moisture which exhaustive tests, both destruc- bly lines and production flow denot found in any other state-of-the-art tive and non-destructive, are per- manded by these items will lead to
formed for both electrical and mechan- increasing use of plastic packaged
NMOS product.
Due to the nature of the storage cell ical testing. Substantial amounts of components at the expense of cerdip
in an EPROM structure, data is main- electrical data are collected and scruti- packages.
tained in a non-volatile state via nized, and failures are analyzed to the
charges trapped on a phosphorus- last detail.
Fast programming issues
doped floating polysilicon gate. Entry
To ensure the quality and reliability
Earlier it was stated that OTP proof moisture is due to passivation de- of its products, Intel follows a "zero duction EPROMs can be programmed
fects
or
passiva,tion
process defects" program. Reliability monitors almost two orders of magnitude faster
5-393
/
2. Sample tests in this OTP monitor flow
are conducted on each manufacturing lot
on a monthly basis.
than cerdip equivalents. When one
considers that most 256K EPROMs
generally program in four to six minutes and that an OTP such as the
P27256 can be programmed in less
than four seconds, one begins to realize
the magnitude of the time savings and
increased throughput potentially
available to the user with OTPs, without a corresponding compromising of
device reliability.
A new approach, designated by Intel
as the Quick-Pulse Programming algorithm, permits these faster program-
ming speeds through the use of much
shorter pulses than required by previous programming algorithms. For example, Intel's earlier Intelligent programming algorithm, which is still
required for cerdip parts, uses a one
millisecond pulse and an overpulse
scheme. By contrast, the Quick-Pulse
Programming algorithm usually needs
only a short 0.1 millisecond pulse with
no overpulse. Increased Vpp latch-up
protection is designed into these new'
OTP devices, and when Vpp and V", are
raised program cell margin increases. _
.Reprinted from ELECTRONIC PACKAGING & PRODUCTION February, 1987
@ 1987 by CAHNERS PUBLISHING COMPANY
5-394
AR-458
"V ...I "r 1""'""".
__ ...:...... n .. :_1.... n •• 1__
!l;;,rnVIVI~ WVlLla UUI""n.-rUI"'~
Programming ™ offer ideal mass
production firmware storage
V. Siva Kumar
Product Marketing Engineer
Intel Corporation
In today's manufacturing environment-where as the 256-kilobit, as many as 24 minutes would Quick.. Pulse Programming algorithm
production flexibility. just-in-time inventory be required to program the device. The Inteligent
For the first time, advances in EPROM design
management, and, above all, quick throughput algorithm therefore was devised to improve pro- and process technology aHow the use of short proare needed - EPROMs have established them- gramming throughput for the higher densities gramming pulses of only 100 microseconds.
The Quick-Pulse Programming algorithm takes
selves as the solution for cost-effective firmware available at that time-namely the 64-kilobit and
production. Intel Corporation, having invented 128-kilobit EPROMs.
advantage of tighter programming voltage tolerthe EPROM in the seventies, has continued to pioThe Inteligent Programming algorithm was the ances in conjunction with the increased V pp latchneer advances that have made EPROMs the first algorithm to exploit the fact that only a few up protection designed into Intel EPROMs. This
choice over masked ROMs as high-volume EPROM cells required 50-millisecond pulses to latch-up protection allows V pp and Vee to be
firmware carriers. Intel's one· time programmable program while a majority of the cells were sue- raised above the levels previously employed for
(Q TP) pi asti c-pae ka ged
programming, thus providing for
EPROMs, that can be progreater program cell margins.
grammed in a few seconds using
The algorithm is made possible
the new Quick-Pulse Programbecause of the improved HMOS
mingT~ algorithm, will supplant
II-E EPROM cell characteristics,
both CERDIP EPROMs and
carefully controlled cell profiles,
oxide thickness and quality and
masked ROMs in this firmware
storage task.
channel length controls (see
These plastic-packaged produc"Quick-Pulse-a Techni.cal Extion EPROMs, currently avail'planation").
able in densities up to 256 kiloThe flow chart of the Quickbits, are the world's first
Pulse Programming algorithm is
EPROMs that are programmable
shown in Fig. 1. One can immediusing the new Quick-Pulse Proately see that the algorithm is ingramming algorithm. This proherently similar to the earlier
gramming algorithm achieves up
Inteligent Programming algoto two orders of magnitude reduerithm in that it benefits from the
tion in programming time comdifferent characteristics of indipared to existing programming
vidual EPROM bits. Different
algorithms. Volume usage of high
cells require a varying number of
density EPROMs is now more
programming pulses, and an itercast-effective than ever through
ative closed-loop scheme allows
the use of OTP plastic packaged
flexibility in employing just the
EPROMs with programming
right number of pulses required
techniques employing this algoby each cell.
rithm.
The programming of an
To high-volume users of
EPROM using the Quick-Pulse
EPROMs, programming time is a
Programming algorithm is done
large component of throughput
as follows. The programming
time. As EPROM density has can·
voltage Vpr should be set at 12.75
tinued to treadmill toward the
li~·"'"
V with V('(: set to 6.25 V (higher
megabit level, programming
than the 5V V('e used during nortimes have become a major conFig. 1 - Quick-Pulse Programming Flowchart
mal operation). Iterative pro- .
cern to system manufacturers. Even the industry cessfully programmed with substantially shorter grammingpulsesof 100 microseconds are then apstandard Inteligent™ algorithm consumes a siz- pulses.
plied. Mter each pulse, the algorithm checks the
able amount of time in programming mature denThis algorithm employed a closed-loop tech- EPROM output to verify the desired programmed
sities. Therefore, if high-density EPROMs are to nique of margin checking. Nevertheless, this pro- value. If the output is incorrect, the algorithm reserve the manufacturing requirement of quick gramming technique still required pulse widths peats the pulse·and·check operation. If after 25
throughput, programming times must be reduced. in the millisecond range with mandatory such iterations the output of that byte still does
Innovation yielded the answer to this problem in overpulses. Hence. the Inteligent algorithm takes not verify correctly, the device failed programthe form of Intel's new Quick-Pulse Programming several minutes to program the highest density ming and is rejected. If the byte verifies accuratealgorithm.
EPROMs available today (265 and 512 kilobits). ly within 25 pulses, programming of that byte has
EPROM programming time evolution
Thus, the stage was set for a breakthrough in been accomplished and the next byte is similarly
programming algorithm development. The objec- treated. Data gathered from the programming
Until the advent of Intel's Inteligent Program- lives were simple: (1) ensure the shortest possible characterization of the Intel EPROM cell shows
ming algorithm in 1983, EPROM programming programming time with the present technology that over 99 percent of the cells only require one
was done using a nominal 50-millisecond pro- and (2) maintain the programmability and data programming pulse. Mter all the bytes are programming pulse per EPROM byte, a method that retention characteristics of the earlier algorithms. grammed, there is a final verification operation
required about 1.5 minutes to program a 16 kilo- The Quick-Pulse Programming algorithm satis- that compares all the programmed bytes to the
bit EPROM. If that same programming technique ties these objectives.
original.
were employed for higher EPROM densities such
r--------------------------,
ECN Published by Chilton Publishing, Radnor, PA 19089,
© Chilton Publishing,
5-395
Order Number: 295019-001
o
L
0
I~I
AlJ1O.pROGRAMMING: PRODUCTION FLOW, BLOCK DIAGRAM
BlANK
f~'t~~~LER
PRODUCTION
EPROMS
DATA 110
HANDLER 600)
1
r BI:;:".:.'_ _-,~
II.
_~JN 2
Comparison:
Quick·Pulse Programming
,vs, Intellgent Programming
Good parts to'
.)Invenlory
:ERFACE
b.)manualassemblyJlne
c ) automated assembly line
SINGLE·SOCKET
PROGRAMMER,
SUCH AS'
INTEL IUP 2001201
RejeetedDr
1"ledparts
Using the Quick-Pulse Programming algo- their own programmers or employ ~'on-bo8rd" pro·
rithm, the 256-kilobit EPROM can be programmed in a theoretical minimum time of 3.3
seconds compared to about four to six minutes required if the Inteligent algorithm were used. This
fast programming time is achievable when the
overhead associated with the programming equipment is minimized. The term "overhead" refers to
the time required by the EPROM programming
equipment to perform some operations needed to
program an EPROM. Some of these operations are
(a) verifying that the EPROM is inserted into the
socket in the correct orientation, (b) reading the
EPROM device identifier and manufacturer's
code, (c) selecting the appropriate programming
voltages, and (d) checking to see if the EPROM is
in an unprogrammed state.
. Most programmers currently available in the
market are based on older and slower microprocessor designs and consequently have large programming overhead. However, newer programa
mer designs anticipated in the near future will
utilize more efficient microprocessors, such 88 the
Intel 80186 or 80188, and should therefore have
substantially reduced overhead. The Quick-Pulse
Programming algorithm, when used in conjunction with low programming overhead, achieves
programming times close to the theoretical minimum, yielding a major improvement over the
Inteligent Programming algorithm. Many manUa
facturers using large volumes of EPROMs design
gramming (in-circuit programming of EPROMs).
This new programming algorithm will allow these
manufacturers to obtain the benefits of the reo
duced programming time. Table 1 shows the comparison of the programming times possible with
the Quick-Pulse Programming algorithm on programmers available today as well as the theoretical minimu~ programming time with no programmer overhead.
PROGRAMMING TIMES
With Data UO Model 120/121
(Firmware version V10):
2764A
Current algorithm 62 sec.
Quick-Pulse 16 sec.
Improvement 3.9 x
27128A
27256
124 sec. 272 sec .
32 sec.
3.9 x
68 sec.
4x
With Intel Fast 27/K'
2764A
27128A
27256
Current algorithm 41 sec.
Quick-Pulse 10 sec.
80 sec.
14 sec.
158 sec.
35 sec.
TheoretIcal limit with no overhead
on programmer
2764A
27128A
27256
0.9 sec.
1.7 sec.
3.3 sec.
Table 1
5·396
Tlle two main reasons that the Quick-Pulse Programming algorithm achieves its speed are the
extremely short programming pulses and the
elimination of the over-programming pulses.
The Inteligent Programming algorithm needed
longer pulses of 1 millisecond for programming.
However, the use of a higher Vpp 'programming
voltage in the Quick-pulse algorithm (12.75 V
compared to 12.5 V) increases etiiCiency (due to
higher drain voltage) and maximum margin (due
to higher gate voltages). This reduces the need for
longer pulses and allows the new algorithm to employ pulses of 100 microseconds.
The Inteligent Programming algorithm utilizes
a 3 x over-program pulse at the end of each byte
verification to ensure programming margin. This
means that even when a cell takes only one 1-millisecond pulse to program, the over-programming
caused the cell programming time to be 4 millisec·
onds; if the cell takes 2 milliseconds to program,
the total time increases to 8 milliseconds. Thus, if
the cell needed the maximum of 25 pulses to program, the total time consumed for program pulses
and overprogram pulse would add up to 100 milliseconds.
The Quick-Pulse Programming algorithm does
not need the over-programming J?ulse to ensure
adequate progra.mming margins. The use of a
higher Vee is a more direct means of achieving the
same result.
Thus, other than the reduction in the pulse
width and the elimination of the over-programming pulse, the Quick-Pulse Programming algorithm resembles the lnteligent Programming ala
gorithm, with both Vee and Vpp programming
voltages increased by 0.25 V. Table 2 shows the
comparison of the two algorithms.
(eont. on next page)
~====~======;------.
COMPARISON: QUICK-PULSE
VS. IHTEUGENT PROGRAMMING
Quick-Pulse
Inteligent
Pulse width
0.1 msec.
1 msec.
25
25
Max. # of pulses
Over-prog. pulses
no
yes (3 x msec.)
Vpp
Vee (programming)
12.~13.0 V
6.0-6.5 V
Table 2
12.0-13.0 V
5.75-6.25 V
Programmability and data retention test resuIts for the Intel P2764A and P27256 EPROMs
are as follows for 1GS·hour bum-in: P2764A 1700
............110
r ... I ....I. '7~AI;;
t ..d<>r1fn
f",;~~ '1'M ..
tAd
rp_
;~lt;~ho;-t"h;t t"h"; Q~i~k:P~lse Programming nl·
gorithm does not compromi~e reliability and qU;ality to achieve programming speed. Extensive
characterization and reliability data were accrued
to validate the algorithm.
breakages when machine handled. The plastic
OTPs make ROMs obsolete
packages are molded in one single piece with no
OTP plastic EPROMs have a ml\ior advantage
separate lid or base and consequently have no
to traditional ROM users and that is greater flexi·
alignment-related auto-handling losses.
bility.
In the fiercely competitive environment of
Modern production technology is increasingly today quick
time to market with the right product
focusing towards complete automation as the that ~eets the customers' changing needs is of the
menns of improving quality and reliability and re- utmost importance. Maintaining an inventory of
ducing manufacturing costs. With full automation
as the goal, the advent of the Quick-Pulse Pro- unprogrammed OTPs saves the firm from having
grammingalgorithm coupled with the OTP allows to store many line items of masked ROMs. The
simplicity and speed of programmi~g an OTP ~.
for the first time for the programming process to lows for quick changes of software. WIthout any inbe incorporated in the manufacturing flow. Using
automatic handlers that are available today, one creased overhead and management costs. With
can completely process the P2764A (64.kilobit changing requirements, ROM code obsolesce~ce is
a major cost increase factor that can agam be
--~-=9
,~n~~,:I:;!""""':";:o<"-,;:I-¥--< BIT LINE
1Stal~Cc~AM
...--1-''----'--+--<, Word hne
-re===:======;:;?1
E2PROM enable
Chip enable
Read enable ~~f
Write enable
Fil..
4: An NVRAM contains both a standard RAM and an
E 'PROM; data is written into the RAM during system opera·
tion, then stored in the E"PROM on power·down. When power
is restored, the data is loaded from E 2PROM to RAM.
most control applications. A single chip could contain the
microcontroller and this small memory. Today it is not unusual to find controllers connected to 8K or even 64K byte
NVM arrays. In fact, some applications use 16-bit processors not for their power but for additional address lines.
Nonvolatile memories come in densities-per-package
that range from 128 bytes to as much as 512K bytes. ROMs
and EPROMs have the highest densities. Both can accommodate densities up to 1 megabit (131,072 bytes).
NVRAMs, PROM., and E'PROMs have lower densities;their
applications, however, are usually less memory intensive.
Comparing the alternatives
Each nonvolatile memory type fits specific application
needs depending on its particular characteristics and limitations. Memory-related variables include unit quantity
(present and future), application, software and hardware
overhead, data security, available board space, package
style, and programming ease. Manufacturing-related
variables include production quantities, upgrade frequency, inventory logistics, service needs, code stability, and
cost. Further, the particular application will determine
the proportion of read-only and alterable memory amounts
required. General purpose computers may require less
than 1% of the total memory to be nonvolatile. In control
systems, however, NVM may comprise over 98% of total·
memory-mostly ROM or EPROM with E'PROM, NVRAM,
and RAM in lesser amounts. Keep in mind that device cost
is only part of a nonvolatile memory's cost effectiveness.
Weighing NVM costs
Device costs are directly related to die size and manufacturing technology. Simple devices, such as ROMs, EPROM.,
and E2 PROMs, have very low cost-per-bit. More complex
memories-NVRAM, RAM, and bubbles-have fewer bits
per die area and more complicated manufacturing processes. These memories have much higher per-bit costs.
Per-bit costs should not be confused with cost E'!ffectiveness, however, since other factors enter into the equation.
ROM. are the lowest cost-per-bit memories, but only for
high-volume productions, and only if code crashes
(firmware that outgrows a memory chip's capacity) and
firmware errors do not occur. Frequently, firmware errors
are discovered after system production begins; their likelihood increases as codes become longer and more complex.
A severe error could require costly scrapping of an entire
stock of ROMs; in this case, EPROMs can be more cost-effective. They offer erasability, on-the-spot programmability,
and a single-device inventory. Since production EPROMs
are usually programmed only once, plastic DIP EPROMs
can be used to decrease costs even further.
IfEPROMs are erased and reprogrammed in a field application, the EPROM must be replaced. Returned EPROM.
are cleaned, erased, reprogrammed, inventoried, and restocked. These maintenance costs could probably be deferred by using E2 PROMs. Because E2 PROMs are in-circuit
reprogrammable, new code can be downloaded via modem,
eliminating the need for a service call.
Battery-backed RAM is initially less expensive than
E2PROM or NVRAM, and it can be cost effective in properly
maintained systems. However, battery failure wipes out
stored memory and requires servicing to replace the battery and reestablish destroyed data.
Initial costs, software and hardware overhead costs,
code failure costs, and maintenance costs should all be
evaluated when considering nonvolatile memory alternatives. The NVM that provides the lowest system life-cycle
cost will be the most cost-effective memory. •
About the author
Terry Kendall has been with Intel for roughly two years.
His present assignment is in the Memory Components Division, working on EPROM products applications. He has a
BA in architecture from the University of Oregon and a
BSEE from California State ·University in Sacramento.
I&CS September. 1987
5-400
Flash Memories
(Electrically Erasable and .
Reprogrammable Non-Volatile
Memories)
6
FLASH
A NEW WAY TO DEAL WITH MEMORY
higher densities (Figure I), and highly reliable-a combination of characteristics other semiconductor memory technologies currently lack.
Computers use memory to· perform several functionsbackup storage, executable code storage, and data manipulation. Today, in systems where the code changes,
RAM is used to serve the function of code storage for
execution by the processor. RAM also serves the purpose of allowing data manipulation in the same technology. since DRAM is voiatiie, mass storage or t>atterybacked SRAM is used to provide nonvolatility. A small
amount of ROM/EPROM also provides the storage
technology to start computers (direct executable and
nonvolatile).
In contrast to EPROMs, however, which can only be
erased through exposure to ultraviolet light, the flash
memory array is eiectricaiiy erasabie-in buik. This
distinguishes it from traditional EEPROMs (electrically erasable programmable read-only memory) that are
by definition byte-alterable; the flash memory erase
function empties the entire device all at once (the device can be programmed incrementally, however-an
important capability for PC applications that require
frequent data/file updates). EEPROM technology's
byte-alterability, truly needed in a very small number of
applications, comes at a high price in terms of cell complexity, limited density and questionable reliability
(Figure 2).
A relatively new semiconductor technology, called
flash memory, stands to fundamentally change this scenario. Because of its true nonvolatility, electrical erasability and low cost, flash memory is regarded as an
ideal memory for embedded applications requiring code
or data updates. And so it is. However, because of its
inherent performance and cost characteristics and recent third-party software developments, flash memory
is also the technology that will reshuffle the existing
memory hierarchy within portable reprogrammable applications more dramatically than any other.
Intel
EEPROM
ETOXTM Flash
1
2
15J.L
38J.L
0.1%
5%
Transistors
Cell Size
(1-Micro Lithography)
WHAT IS FLASH MEMORY?
Cycling Failures
At the semiconductor technology level, Intel's
ETOXTM (EPROM tunnel oxide) flash memory is
based on a single-transistor EPROM cell. As such,
flash memory is nonvolatile, meaning that it retains
its contents even if power is removed. This is in contrast to volatile memory technologies like static and dynamic RAMs that require continuous power to store
information. Flash memory's cell structure and
EPROM foundation also ensure that it is extremely
cost-effective to manufacture, continually scalable to
Figure 2
Lastly, unlike competitive approaches to flash memory,
Intel's ETOX process produces devices that can be cycled, or erased and reprogrammed, hundreds of thousands of times without fail. Again, this is a unique and
essential capability within reprogrammable applications
where files are updated frequently.
1000
500
N
.5
...!::!
200
100
III
...
,..
...J
...J
..J
0
~
a:
......
Ow