1991_Lattice_GAL_Data_Book 1991 Lattice GAL Data Book
User Manual: 1991_Lattice_GAL_Data_Book
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GAL PRODUCT INDEX
Commercial Grade Devices
DEVICE
PINS
tpD
(ns)
Icc (rnA)
DESCRIPTION
PAGE
GAL16V8NB
20
7.5,10,15,25
55,90,115
FCMOS Generic PLD
2-1
GAL20V8NB
24
7.5,10,15,25
55,90,115
GAL18V10
20
15,20
115
E2CMOS Generic PLD
2-25
E2CMOS Universal PLD
2-47
GAL22V10/B
24
10,15,25
130
E2CMOS Universal PLD
2-61
GAL26CV12
28
15, 20
130
E2CMOS Universal PLD
2-81
GAL20RA10
24
12,15,20,30
100
E2CMOS Asynchronous PLD
2-95
GAL6001
24
30,35
150
E2CMOS FPLA
2-109
ispGAL 16Z8
24
20, 25
90
E2CMOS In-System-Programmable PLD
2-121
DESCRIPTION
PAGE
Industrial Grade Devices
DEVICE
PINS
tpD
(ns)
Icc (rnA)
GAL16V8NB
20
10,15,20,25
65, 130
E2CMOS Generic PLD
2-1
GAL20V8A
24
15,20,25
65, 130
FCMOS Generic PLD
2-25
GAL18V10
20
20
125
E2CMOS Universal PLD
2-47
GAL22V10/B
24
15,20,25
150
E2CMOS Universal PLD
2-61
GAL26CV12
28
20
150
E2CMOS Universal PLD
2-81
GAL20RA10
24
20
120
E2CMOS Asynchronous PLD
2-95
MIL-STD-883C Grade Devices
DEVICE
PINS
tpD
(ns)
Icc (rnA)
DESCRIPTION
65,130
E2CMOS Generic PLD
3-5
E2CMOS Generic PLD
3-13
PAGE
GAL16V8NB
20
GAL20V8A
24
15,20,25,30
65,130
GAL22V10/B
24
15,20,25,30
150
E2CMOS Universal PLD
3-19
120
E2CMOS Asynchronous PLD
3-27
GAL20RA10
24
10,15,20,25,30
20, 25
Thank you for your interest in our high performance GAL product line.
As the inventor and world leader of the GAL· device, we at Lattice are
dedicated to providing you with the fastest, highest quality and most
flexible solution to your logic needs.
In our new 1991 Data Book, you will see that we have substantially
expanded our product line and continue to offer the world's highest
performance CMOS programmable logic devices.
We look forward to satisfying all of your programmable logic requirements.
~~
.Steven Laub
Vice President and General Manager
ii
GAL Data Book
1991
Lattice®
f/J
.l..I
Semiconductor
Corporation
iii
it /;Lattire°
.l.J
SemiconducUJr
Corporation
Copyright © 1991 Lattice Semiconductor Corporation
Generic Array Logic, Latch-Lock, and RFT are trademarks of Lattice Semiconductor Corporation.
ispGAL, GAL, PCMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corporation.
PAL is a registered trademark of Advanced Micro Devices, Inc.
Products discussed in this literature are covered by U.S. Patents No.4, 761,768, 4,766,569, 4,833,646, 4,852,044,
4,855,954, 4,879,688, 4,887,239 and 4,896,296 issued to Lattice Semiconductor Corporation, and by U.S. and
foreign patents pending.
LATTICE SEMICONDUCTOR CORP.
5555 Northeast Moore Court
Hillsboro, Oregon 97124 U.S.A.
Tel.: (503) 681-0118
FAX: (503) 681-3037
TELEX 277338 LSC UR
iv
Section 1: Introduction to Generic Array Logic
Introduction to Generic Array Logic
1-1
II
2
Section 2: GAL Datasheets
2-ii
2-1
2-25
2-47
2-61
2-81
2-95
2-109
2-121
Datasheet Levels
GAL16V8A1B
GAL20V8A1B
GAL18V10
GAL22V10/B
GAL26CV12
GAL20RA10
GAL6001
ispGAL16Z8
Section 3: GAL Military Products
Military Program Overview
MIL-STD-883C Flow
Military Ordering Information
GAL 16V8A1B Military Datasheet
GAL20V8A Military Datasheet
GAL22V10/B Military Datasheet
GAL20RA 10 Military Datasheet
3-1
3-2
3-3
3-5
3-13
3-19
3-27
Section 4: Quality and Reliability
Quality Assurance Program
Qualification Program
E2CMOS Testability Improves Quality
4-1
4-3
4-5
Section 5: Technical Notes
5-1
5-17
GAL Metastability Report
Latch-up Protection
3
4
5
Section 6: Article Reprints
Avoid the Pitfalls of High-Speed Logic Design
Extending the 22V1 0 EPLD
In-Circuit Logic Device Can be Reprogrammed on the Fly
Multiple Factors Define True Cost of PLDs
6-1
6-7
6-9
6-13
6
7-1
7-3
7-5
7-8
7-9
7-16
7-17
7
Section 7: General Information
Development Tools
Copying PAL, EPLD & PEEL Patterns into GAL Devices
GAL Product Line Cross Reference
Package Thermal Resistance
Package Diagrams
Tape-and-Reel Specifications
Sales Offices
1-i
1-ii
Introduction to
Generic Array Logic
INTRODUCTION
THE GAL CONCEPT
Lattice Semiconductor, located in Hillsboro, Oregon, was
founded in 1983 to design, develop and manufacture
high-performancesemiconductorcomponents.ltisafirm
belief at Lattice that technological evolution can be
accelerated through the continued development of higherspeed and architecturally superior products.
EZCMOS - THE IDEAL TECHNOLOGY
Of the three major technologies available for producing
PLDs, the technology of choice is clearly E2CMOS.
E2CMOS offers testability, quality, high speed, low power,
and instant erasure.
TESTABILITY
GAL devices are ideal for four important reasons:
1. GAL devices have inherently superior quality and
reliability.
2. GAL devices can directly replace PAL devices in nearly
every application.
3. GAL devices have the low power consumption of
CMOS, one-fourth to one-haH that of bipolar devices.
4. GAL devices utilize Output Logic Macrocells (OLMCs),
which allow the user to configure outputs as needed.
The biggest advantage of PCMOS over competing
technologies is its inherent testability. Capitalizing on
veryfast (1 OOms) erase times, Lattice repeatedly patterns
and erases all devices during manufacture. Lattice tests
each GAL device for AC, DC, and functional characteristics.
The result is guaranteed 100% programming and
functional yields.
LOW POWER
Another advantage of E2CMOS technology is the low
power consumption of CMOS. CMOS provides users the
immediate benefit of decreased system power
requirements allowing for higher reliability and cooler
running systems. Low power CMOS technology also
permits circuit designs of much higher functional density,
because of lower junction temperatures and power
requirements on Chip. The user benefits because higher
functional density means further reduction of chip count
and smaller boards in the system.
HIGH SPEED
Also advantageous is the very high speed attainable with
Lattice's state-of-the-art PCMOS process. Lattice GAL
devices are as fast or faster than bipolar and UVCMOS
PLDs.
PROTOTYPING AND ERROR RECOVERY
Finally, E2CMOS gives the user instant erasabilitywith no
additional handling or special packages necessary. This
provides ideal products for prototyping because designs
can be revised instantly, with no waste and no waiting. On
the manufacturing floor instant erasability can also be a
big advantage for dealing with pattern changes or error
recovery. If a GAL device is accidentally programmed to
the wrong pattern, simply reprogram the device. No other
technology offers this advantage.
1-1
.J
~
I
I
I
Introduction to
Generic Array Logic
A LOOK AT OTHER TECHNOLOGIES
THE GAL ADVANTAGE
Here, the technologies that compete with E2CMOS bipolar and UVCMOS -are compared with the E2CMOS
approach.
BIPOLAR
Bipolar fuse-link technology was the first available for
programmable logic devices. Although it offers high
speed, it is saddled with high power dissipation. High
power dissipation increases your system power supply
and cooling requirements, and limits the functional density
of bipolar devices.
Another weakness of this technology is the one-timeprogrammable fuses. Complete testing of bipolar PLDs is
impossible because the fuse array cannot be tested
before programming. Bipolar PLD manufacturers must
rely on complex schemes using test rows and columns to
simulate and correlate their device's performance. The
result is programming failures at the customer location.
Any misprogrammed devices due to mistakes during
prototyping or errors on the production floor must be
discarded because bipolar PLDscannot be reprogrammed.
UVCMOS
UVCMOSaddresses many weaknesses of the bipolar
approach but introduces many shortcomings of its own.
This technology requires less power and is
reprogrammable, but reprogrammability comes at the
expense of slower speeds.
Testability is increased over bipolar since the "fuse" array
can be programmed and tested by the manufacturer. The
problem here ill the long (20 minutes) erase times coupled
with the requirement of exposing the devices to ultraviolet
light for erasing. This becomes a very expensive step in
themanLJfacturing process. Because ofthe time involved,
patterning and erasing is performed only once - a
compromised rather than complete functional test.
Additionally, the devices must be housed in expensive
windowed packages to allow users to erase them. Again,
programming these devices is time-consuming and
cumbersome due to the 20-minute UV exposure required
to erase them. As acost-cutting measure, UVCMOS PLD
manufacturers offertheirdevices in windowless packages.
Although windowless packages are less expensive, they
cannot be completely tested or reprogrammed. These
factors significantly detract from the desirability of this
technology.
GAL devices are ideal programmable logic devices
because, as the name implies, they are architecturally
generic. Lattice has employed the macrocell approach,
which allows users to define the architecture and
functionality of each output. The key benefit to the user is
the freedom from being restricted to any specific
architecture. This is advantageous at both the
manufacturing level and the design level.
DESIGN ADVANTAGES
Early programmable logic devices gave the user the
ability to specify a function, but limited them to specific,
predetermined output architectures. Comparing the GAL
device with fixed-architecture programmable logic devices
is much like comparing these same fixed PLDs with SSI/
MSI devices. The GAL family is the next generation in
simplified system design. The user does not have to
search for the architecture that best suits a particular
design. Instead, the GAL family's generic architecture lets
him configure as he goes.
MANUFACTURING ADVANTAGES
The one-device-does-all approach greatly simplifies
manufacturing flow . Inventorying one generic-architecture
GAL device type versus having to monitor and maintain
many different device types, saves money and minimizes
paperwork: Manufacturing flow is much smoother because
the handling process is greatly simplified. A generiC
architecture GAL device also reduces the risk of running
out of inventory and halting production, which can be very
expensive. Reduced chance of obsolete inventory and
easier QA tracking ate additional benefits of the generic
architecture.
THE IDEAL PACKAGE
Programmable logic devices are ideal fordesigningtoday's
systems. Lattice Semiconductor believes that the ideal
design approach should be supported with the ideal
products. It was on this premise that GAL devices were
invented. The ideal device-with a generic architecturefabricated with the ideal process technology, E2CMOS.
1-2
1
Section 1: Introduction to Generic Array Logic
Introduction to Generic Array Logic
1-1
Section 2: GAL Datasheets
Datasheet Levels
GAL16VSNB
GAL20VSNB
GAL1SV10
GAL22V10/B
GAL26CV12
GAL20RA10
GAL6001
ispGAL16ZS
2-ii
2-1
2-25
2-47
2-61
2-S1
2-95
2-109
2-121
Section 3: GAL Military Products
Military Program Overview
MIL-STD-S83C Flow
Military Ordering Information
GAL 16VSNB Military Datasheet
GAL20VSA Military Datasheet
GAL22V10/B Military Datasheet
GAL20RA 10 Military Datasheet
3-1
3-2
3-3
3-5
3-13
3-19
3-27
Section 4: Quality and Reliability
Quality Assurance Program
Qualification Program
FCMOS Testability Improves Quality
4-1
4-3
4-5
Section 5: Technical Notes
GAL Metastability Report
Latch-up Protection
5-1
5-17
at
3
4
5
Section 6: Article Reprints
Avoid the Pitfalls of High-Speed Logic Design
Extending the 22V1 0 EPLD
In-Circuit Logic Device Can be Reprogrammed on the Fly
Multiple Factors Define True Cost of PLDs
6-1
6-7
6-9
6-13
8
Section 7: General Information
Development Tools
Copying PAL, EPLD & PEEL Patterns into GAL Devices
GAL Product Line Cross Reference
Package Thermal Resistance
Package Diagrams
Tape-and-Reel Specifications
Sales Offices
2-i
7-1
7-3
7-5.
7-S
7-9
7-16
7-17
7
Definition of Datasheet Levels
DEFINITION OF DATASHEET LEVELS
Datasheet Identification
'PA""ii'F't
No Identification
Product Status
DeflnHlon
Sampling or
Pre-Production
This datasheet contains preliminary data and supplementary
data will be published at a later date. Lattice reserves the
right to make changes at any time without notice.
Full Production
This datasheet contains final specifications. Lattice reserves the
right to make changes at any time without notice.
2-ii
tatUce®
[JJ
~
GAL16V8B
GAL16V8A
SemioonducWr
Corporation
FEATURES
• HIGH PERFORMANCE ElCMOS· TECHNOLOGY
- 7.5 ns Maximum Propagation Delay
- Fmax =100 MHz
- 5 ns Maximum from Clock Input to Data Output
- TTL Compatible 24 mA Outputs
- UHraMOS· Advanced CMOS Technology
• 500/0 to 750/0 REDUCTION IN POWER FROM BIPOLAR
- 75mA TYP Icc on Low Power Device
- 45mA TYP Icc on Quarter Power Device
High Performance E2CMOS PLD
FUNCTIONAL BLOCK DIAGRAM
Vee.
20
J
19
2
18
3
• ACTIVE PULL-UPS ON ALL PINS (GAL16V8B)
• E2 CELL TECHNOLOGY
- Reconflgurable logic
- Reprogrammable Cells
-1000/0 Tested/Guaranteed 1000/0 Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum FlexlbllHy for Complex Logic Designs
- Programmable Output Polarity
- Also Emulates 2o-pln PAL· Devices with Full Functlon/Fuse Map/Parametric CompatlbllHy
17
4
16
15
6
14
7
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-1000/0 Functional Testability
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
13
8
12
9
11
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
PIN CONFIGURATION
The GAL16V8B, at 7.5 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E2) floating gate technology to provide the highest speed
performance available in the PlD market. High speed erase times
«100ms) allow the devices to be reprogrammed quickly and
efficiently.
DIP
PLCC
IICLK
l'CUC Veo
The generic architecture provides maximum design flexibility by
allowing the Output logic Macrocell (OlMC) to be configured by
the user. An important subset of the many architecture con·
figurations possible with the GAL 16V8A1B are the PAL architectures listed in the table of the macrocell description section.
GAL16V8AIB devices are capable of emulating any of these PAL
architectures with full function/fuse maplparametric compatibility.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 1000/0 field programmability and
functionality of all GAL· products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.
Vee
IIOJQ
roIO
20
11010
vOla
~OIO
vOla
GAL16VSAlB
vOla
Top View
VOla
11010
11010
IIOJQ
VO/Q
I
CIHO IIOi
11010
VOla vOla
11010
aND
~c5E
Copyright C1991 Lattice Semiconductor Corp. GAL. E'CMOS and UlltaMOS are regls..rod trademarks 01 lattice Semiconductor Corp. GonorIc "ray Logic Is a trademarl< of Lattlca SeRiconduc·
tor Corp. PAL Is a registered tradomar1< of Advanced Micro Dovlcoo. Inc. The specifications and Information heroin are subject to change without noflca.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118: 1-800-FASTGAL: FAX (503)681-3037
2-1
April 1991.Rev.A
'Lattice~
flJ.
~ Semiconductor
Specifications GAL 16V8B
GAL 16V8A·
Corporation
GAL 16V8A'B ORDERING INFORMATION
Commercial Grade Specifications
Tpd(n8)
T8U (n8)
Teo (ns)
Icc(mA)
7.5
7
5
115
GAL16V8B-7LP
20-Pin Plastic 01 P
115
GAL16V8B-7LJ
20-Lead PLCC
115
GAL16V8B-l0LP
20-Pin Plastic DIP
115
GAL16V8B-l0LJ
20-Lead PLCC
115
GAL 16V8A-l OLP
20-Pin Plastic DIP
115
GAL16V8A-l0LJ
20-Lead PLCC
55
GALI6V8A-I50P
20-Pin Plastic DIP
55
GAL16V8A-I50J
20-Lead PLCC
115
GAL 16V8A-15LP
20-Pin Plastic DIP
115
GAL16V8A-15LJ
20-Lead PLCC
55
GAL 16V8A-250P
20-Pin Plastic DIP
55
GAL 16V8A-25QJ
20-Lead PLCC
90
GAL 16V8A-25LP
20-Pin Plastic DIP
90
GAL 16V8A-25LJ
20-Lead PLCC
10
15
25
10
12
15
7
10
12
Ordering #
Package
Industrial Grade Specifications
Tpd (n8)
Tsu(ns)
Teo (ns)
Icc (mA)
10
10
7
130
GALI6V8B-l0LPI
2O-Pin Plastic DIP
130
GAL 16V8B-l0LJI
20-Lead PLCC
15
20
25
12
13
15
10
11
12
Ordering #
Package
130
GAL 16V8B-15LPI
20-Pin Plastic DIP
130
GAL16V8B-15LJI
20-Lead PLCC
130
GAL 16V8A-15LPI
20-Pin Plastic DIP
130
GALI6V8A-15LJI
20-Lead PLCC
65
GAL 16V8A-200PI
20-Pin Plastic DIP
65
GAL 16V8A-2OQJI
20-Lead PLCC
65
GAL 16V8A-250PI
20-Pin Plastic DIP
65
GAL 16V8A-25QJ1
20-Lead PLCC
130
GAL 16V8A-25LPI
20-Pin Plastic DIP
130
GAL 16V8A-25LJI
20-Lead PLCC
PART NUMBER DESCRIPTION
GAL16V8A
GAL16V8B
Blank =Commercial
I ~ Industrial
Speed (ns) _ _ _ _ _ _....J
L _ Low Power Power _ _ _ _ _ _ _ _....J
Q -1/4 Power
' - - - - - - Package
P = Plastic DIP
J. PLCC
2-2
4/91.Rev.A
Specifications GAL 16VBB
GAL 16VBA
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accomplished by development softwareJhardware and is completely
transparent to the user.
There are three global OlMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes is illustrated in the following pages. Two global bits, SYN
and ACO, control the mode configuration for all macrocells. The
XOR bit of each macrocell controls the polarity of the output in any
of the three modes, while the AC1 bit of each of the macrocells
controls the input/output configuration. These two global and 16
individual architecture bits define all possible configurations in a
GAL 16V8A1B. The information given on these architecture bits
is only to give a better understanding of the device. Compiler
software will transparently set these architecture bits from the pin
definitions, so the user should not need to directly manipulate
these architecture bits.
The following is a list of the PAL architectures that the GAL16V8A
and GAL 16V8B can emulate. It also shows the OlMC mode
under which the GAL16V8A1B emulates the PAL architecture.
PAL Architectures
Emulated by GAL16V8A1B
GALl6V8AlB
Global ollie Mode
16R8
16R6
16R4
16RP8
16RPB
16RP4
Registered
Registered
Raglstered
Raglstered
Raglstered
Raglstered
16La
18H8
16P8
Complex
Complex
Complex
lOLa
12L6
14L4
16L2
10H8
12H6
14H4
16H2
10P8
12P6
14P4
16P2
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OlMC
modes as different device types. These device types are listed
in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage
and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combinatorial outputs with OE controlled by the product term will force
the software to choose the complex mode. The software will
choose the simple mode only when all outputs are dedicated
combinatorial without OE control. The different device types listed
in the table can be used to override the automatic device selection
by the software. For further details, refer to the compiler software
manuals.
In registered mode pin 1 and pin 11 are permanently configured
as clock and output enable, respectively. These pins cannot be
configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 11 become dedicated inputs and
use the feedback paths of pin 19 and pin 12 respectively. Because
of this feedback path usage, pin 19 and pin 12 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
15 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.
ABEL
CUPL
LOG/IC
OrCAD-PLD
PLDeslgner
TANGO-PLD
Registered
Complex
Simple
Auto Mode Select
P16V8R
G16V8MS
GAl16V8 R
"Registered"'
P16V8R2
G16V8R
P16V8C
G16V8MA
GAl16V8 C7
"Complex"'
P16V8C2
G16V8C
P16V8AS
G16V8AS
GAl16V8 C8
"Simple"'
P16V8C2
G16V8AS3
P16V8
G16V8
GAL16V8
GAL16V8A
P16V8A
G16V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
2-3
4/91.Rev.A
Specifications GAL 16VBB
GAL 16VBA
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
mode. Dedicated input or output functions can be implemented
as subsets of the VO function.
Archkecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations
of polarity, VO and register placement.
Registered outputs have eight product terms per output. VO's
have seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the followihg page.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
VO. Up to eight registers or up to eight VO's are possible in this
ClK
f~
··
---____ .-------.. . . . . . . . -------.. . . . . . -- -----!
~--------.--.---
Registered Configuration for Registered Mode
-SYN=O.
-ACO.. 1.
- XOR",O defines Active Low Output.
- XOR..1 defines Active High Output.
- AC1 ",0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.
..
.. --------.---- . -. -----------.
OE
..... -- .. - .. _- ...... -- ........ -- ...... - ..... .
Combinatorial Configuration for Registered Mode
-SYN",O.
-ACO=1.
- XOR..Odefines Active Low Output.
- XOR..1 defines Active High Output.
- AC1 =1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
2-4
4191.Rev.A
Lattice~
[JJ
1.,.; Semiconductor
Specifications GAL 16V8S
GAL 16V8A
Corporation
II
REGISTERED MODE LOGIC DIAGRAM
DIP & PLCC Package Pinouts
.....
I
~
0
4
8
0000
12
"
20
24
2tI
J
!
pm
§:
OLMC 19
:§:
022'
XOR·2048
AC1·2120
0256
~
-
~
OLMC 18
XOR·2049
AC1·2121
0512
:g:
OLMC 17
:§:
073<
XOR·1050
AC1·2122
~
0768
~
OLMC 16
0992
XOR·1051
AC1·2123
D
1024
§:
.-....
OLMC 15
-
1248
XOR·1052
AC1·2124
1280
~
s:
::c
1504
OLMC 14
XOR·1053
AC1·2125
.If
D
,,3<
,..,.
§:
1760
OLMC 13
XOR·1054
AC1·2126
1792
-
.-....
~
2016
OLMC 12
I!S.:::;
XOR·1055
AC1·2127
~fF
1
~
1
"...,.,
19
~u
1
~n
1 n
~
1 .......
~-
18
17
16
15
1· .......
~
1 .......
13
1
12
~~
[J~
A
OE,....,
14
11
fI4.USEII ElECTRONIC SIGNAlURE FUSES
12068, 2057, ..•.
.... 211 ..
21181
Byte71Byte8 ....
SYN·2192
ACO·2193
M L
S
S
B B
2-5
4/91.Rev.A
.
Lattice[JJ
l.J
.
Specifications GAL 16V8B
GAL 16V8A
Semiconducwr
Corporation
.
COMPLEX MODE
In the Complex mode, macrocells are configured as output only
or 110 functions.
.
pability. Designs requiring eight I/O's can be implemented in the
Registered mode.
Architecture configurations available in this mode are similar to
the common 16L8 and 16P8 devices with programmable polarity
in each macrocell.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
11 are always available as data inputs into the AND array.
Up to six I/O's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the I/O function. The
two outer most macrocells (pins 12 & 19) do not have input ca-
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the iogic diagram on the following page.
·......................................................
,
·
..
Combinatorial 1/0 Configuration for Complex Mode
- SYN.1.
-ACO-1.
- XOR.O defines Active Low Output.
- XOR.1 defines Active High Output.
-AC1-1.
- Pin 13 through Pin 18 are configured to this function.
.
,
.....................................................
....................................................,
:
:
Combinatorial Output Configuration for Complex Mode
~IPr7R ·
- SYN.1.
-ACO-1.
- XOR.O defines Active Low Output.
- XOR.. 1 defines Active High Output.
- AC1-1.
- Pin 12 and Pin 19 are configured to this function.
~ ...............................................................:
Note: The development software configures all of the architecture control bitt; and checks for proper pin usage automatically.
2·6
4/91.Rev.A
Latuoo
[[J
.J.,,;
e
Specifications GAL 16VBB
GAL 16VBA
SemJoonducUJr
Corporation
COMPLEX MODE LQGIC DIAGRAM
DIP & PLCC Package Pinouts
...,
...
v
....
• •
a
12
11
20
24
2B
mJ
:i=t::=
=1::$
:B=
.224
D-
OLMC 19
.251
<= OLMC 18
~
-.
D<8O
D-0512
.-...
...,
OLMC 17
XOR·2050
AC1-2122
.788
.-...
...,
-
:R:::::=:
~
OLMC 16
XOR·2051
ACl·2123
1024
<= OLMC15
-0--;....
1241
Dl!SO
.-...
~
-0--;....
150.
'--'
XOR·2052
AC1·2124
OLMC 14
§=
-:
D-
OLMC 13
B==
-
~~
' --'
rr
....
':::1
OLMC 12
XOR·2055
AC1·2127
l
1~1
n
1
U
Il.
U
-01
Il..... J ~1
Il
v
J-G
n
,....,.
~
XOR·2054
AC1·2126
17112
2011
n
XOR·2053
AC1:2.125
1531
176.
~
XOR·2049
AC1·2121
:a=
~
.731
n
XOR·2048
AC1·2120
n
....
J-
14
13
-a 12
a
11
21"
II4-USER ELECTRONIC SIGNATURE RJ8fiS
12068,2067.....
By\! 7 IBy\! • ....
II
L
S
S
B
B
.... 2118.2"'1
.... By\!
2-7
11 By\! 0 .
SVN·2192
ACO-2193
4191.Rev.A
[JJ
'L tattiOO-
.
Specifications GAL 16V8B
GAL 16V8A
SemkxJnductor
Corporation
SIMPLE MODE
Pins 1 and 11 are always available as data inputs into the AND
array. The center two macrocells (pins 15 & 16) cannot be used
as input or I/O pins, and are only available as dedicated outputs.
In the Simple mode, macrooells are configured as dedicated inputs
or as dedicated, always active, combinatorial outputs.
Architecture configurations available in this mode are similar to
the common 10la and 12P6 deviCes with many permutations of
generic output polarity or input choices.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram.
All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has
programmable polarity.
r····································~·:~··"1
Combinatorial Output with Feedback Configuration
for Simple Mode
---+--\
-SYN=1.
-ACO.O.
- XOR.O defines Active Low Output.
- XOR.. 1 defines Active High Output.
- AC1 =0 defines this configuration.
- All OlMC except pins 15 & 16 can be configured to
this function.
t. __ ... __ ....... _............................... j
;._-
..........................................
Combinatorial Output Configuration for Simple Mode
Voo
- SYN=1.
-ACO.O.
- XOR=O defines Active Low Output.
- XOR.. 1 defines Active High Output.
- AC1-0 defines this configuration.
- Pins 15 & 16 are permanently configured to this
function.
... __ ................... _-
'............ _.............. _
Dedicated Input Configuration for Simple Mode
-SYN.1.
-ACO.O.
- XOR=O defines Active Low Output.
- XOR.. 1 defines Active High Output.
- AC1 .. 1 defines this configuration.
- All OlMC except pins 15 & 16 can be configured to
this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
2-8
4/91.Rev.A
Lattice~
!1J
1..1 Corporation
Semronductor
Specifications GAL 16V8B
GAL 16V8A
DIP & PLCC Package Pinouts
,.....,
v
...
...
, •
I
"
11
II
..
"
iI:a:::::::
~
""
-
-
H=
OLMC18
XOR·2Q.49
AC1·2121
:!3=
OLMC 17
:§=:
''''
XOR·2Q.48
AC1·2120
1<=
......----
'512
OLMC 19
XOR·2050
AC1·2122
IJ
-01
l
-01
v
J
~1
IJ
~1
11
- 0 15
I.l
- 0 14
IJ
- 0 13
~
''''
.---.
OLMC 16
~
"'"
,.,.
D
~
''''
'2!D
1<=
=c:::
,SOl
XOR·2051
AC1·2123
OLMC 15
XOR·2052
AC1·2124
OLMC 14
XOR·2053
AC1·2125
v
v
D
's:!6
-=-
:§::::::
IJ..
-:
.r--..
'102
-
OLMC 13
XOR·2054
AC1·2126
OLMC 12
=8=
,."
I!S~
XOR·2055
AC1·2127
84-USER El£CTRONIC SIONATURE FUIES
EIy!e 718y1e 8 .•.
hi L
S
I
••.• 2118, 211P
••• EIy!e 11 EIy!e 0 .
I.l -........
v
~
I'"
12056, 2057, •.••
v
12
11
SYN·2192
ACO·2193
S
B B
2-9
i
-
SIMPLE MODE LOGIC DIAGRAM
L..I
i
I
4/91.Rev.A
I
'LatUoo@
[JJ
.l..J
Specifications GAL 16V8B
Commercial
Semiconductor
Corporation
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDo
Commercial Devices:
Ambient Temperature (TAl ................................ 0 to 75°C
Supply voltage (Veel
with Respect to Ground ...................... +4.75 to +5.2SV
Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee +1 .OV
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming. follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.'
MAX.
UNITS
-
0.8
V
VCC+1
V
-100
~
VIL
Input Low Voltage
Vss-0.5
VIH
Input High Voltage
2.0
IlL'
Input or 1/0 Low Leakage Current
OV S VIN S VIL (MAX.)
-
Input or 1/0 High Leakage Current
3.SV S VIN S Vcc
VOL
Output Low Volt~e
IOL .. MAX. Vin .. VIL or VIH
-
VOH
Output High Voltage
IOH .. MAX. Yin = VIL or VIH
2.4
IIH
10L
-
-
Low Level Output Current
10H
High Level Output Current
los·
Output Short Circuit Current
Vcc=5V YOUTz O.SV
Icc
Operating Power Supply Current
VIL= 0.5V ViH =3.0V ftoggle .. 2SMHz
TA= 25°C
10
IlA
0.5
V
-
V
24
mA
-
-3.2
mA
-30
-
-150
mA
-
75
115
mA
Outputs Open (no load)
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout .. O.SV was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee .. 5V and TA= 25°C
CAPACITANCE (TA = 25°C, f
=1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vcc - 5.0V. V, .. 2.0V
C'iO
1/0 Capacitance
8
pF
Vcc =5.0V. VIIO -2.0V
'Guaranteed but not 100% tested.
2-10
4191.Rev.A
LatUCC
[JJ
J.J
Specifications GAL 16V8S
Commercial
Gl
SemiconduCUJr
CorporaUon
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
~ARAMETER
TEST
COND'.
tpd
tco
tcf'
tsu
th
fmax 3
twh4
twt'
ten
tdis
1
1
-
-7
-10
MIN. MAX.
MIN. MAX.
DESCRIPTION
I 8 outputs switching
Input or I/O to Combinational Output
J 1 output switching
UNITS
3
7.5
3
10
ns
-
7
-
-
ns
Clock to Output Delay
2
5
2
7
ns
Clock to Feedback Delay
-
3
-
6
ns
-
10
-
ns
Setup Time, Input or Feedback before Clock"
7
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + teo)
83.3
-
58.8
-
MHz
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
100
-
62.5
-
MHz
1
Maximum Clock Frequency with
No Feedback
100
-
62.5
-
MHz
Clock Pulse Duration, High
5
8
Clock Pulse Duration, Low
Hold Time, Input or Feedback after Clock"
0
0
ns
5
-
8
-
2
Input or I/O to Output
3
9
3
10
ns
2
OE.!. to Output
2
6
2
10
ns
3
Input or I/O to Output
2
9
2
10
ns
3
OE" to Output
1.5
6
1.5
10
ns
-
ns
ns
i) Refer to SWitching Test Conditions section.
!) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
I) Refer to fmax Descriptions section.
I) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
+5V
GNDto 3.0V
3ns 10%-90%
1.SV
1.SV
Output Load
See Figure
I-state levels are measured O.SV from steady-state active
eve I.
FROM OUTPUT (0/0)
UNDER TEST
- -.....- -....-TESTPOINT
)utput Load Conditions (see figure)
Test Condition
1
2
3
Active
Active
Active
Active
High
Low
High
Low
Rl
Rz
CL
200n
390n
3900
390n
3900
390n
SOoF
SOpF
SOpF
SpF
SpF
~
200n
~
200n
R2
C LINCLUDES JIG AND PROBE TOTAL CAPACITANCE
2-11
4191.Rev.A
'Lattice@
~C()IJXX'aUOIl
Semiconductor
'L
Specifications GAL 16V8A
Commercial
ABSOLUTE MAXIMUM RATINGS(l)
RECOMMENDED OPERATING CONDo
Commercial Devices:
Supply voltage Vee ....................................... -o.5to +7V
Input voltage applied ........................... -2.5to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ...•.................................... -55 to 125°C
Ambient Temperature (TA ) •••••••••••••••••••••••••••••••• 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.75 to +5.25V
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming. follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP}
-
VIL
Input Low Voltage
Vss-O.5
VIH
Input High Voltage
2.0
-
IlL
Input or 1/0 Low Leakage Current
OV S VIN S VIL (MAX.)
IIH
Input or 110 High Leakage Current
VIH S VIN S Vee
VOL
Output Low Voltage
10L=MAX. Yin = VIL or VIH
-
VOH
Output High Voltage
IOH = MAX. Yin = VILor VIH
2.4
10l
Low level Output Current
10H
High Level Output Current
los'
Output Short Circuit Current
Icc
-
Vcc=5V
Operating Power
VIL= 0.5V
VIH=3.0V
Supply Current
Outputs Open (no load)
TA=25·C
VOUT = 0.5V
ftoggle = 15M Hz
L -25
floggle = 25MHz
L-10/-15
ftoggle = 15MHz
Q -15/-25
I
-30
-
-
MAX.
UNITS
0.8
V
VcC+1
V
-10
I1A
10
I1A
0.5
V
-
V
24
mA
-3.2
mA
-150
mA
75
90
mA
75
115
mA
45
55
mA
1} One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc = 5V and TA = 25 ·C
CAPACITANCE (TA
=25°C, f =1_0 MHz)
SYMBOL
PARAMETER
MAXIMUM'
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vee =5.0V. V, = 2.0V
Coo
ilO Capacitance
10
pF
Vee = 5.0V. VIJO = 2.0V
'Guaranteed but not 100% tested.
2-12
4!91.Rev)
I
Specifications GAL 16VBA
Commercial
AC SWITCHING CHARACTERISTICS
I:
~
~
..•
OVer Recommended Operating Conditions
PARAMETER
TEST
COND'.
DESCRIPTION
-10
-15
-25
MlfIC )ftAx.
MIN. MAX.
MIN. MAX.
UNITS
tpd
1
Input or I/O to Combinational Output
3 •
10
3
15
3
25
ns
teo
1
Clock to Output Delay
2 ,;
7
2
10
2
12
ns
tcf2
Clock to Feedback Delay
-i
7
-
-
10
ns
tsu
-
Setup Time, Input or Feedback before Clocki
10
~
-
12
15
-
ns
th
1
fmax 3
twh4
tw"
ten
tdis
Hold Time, Input or Feedback after Clocki
Maximum Clock Frequency with
External Feedback, 1f(tsu + teo)
45.5
-
50
37
-
MHz
-
40
-
MHz
62.5
-
41.6
-
MHz
t ;-
8
-
12
-
ns
==-
o
58.8~ ~all
.
Si
1
Maximum Clock Frequency with
Internal Feedback, 1f(tsu + tcf)
58.84
1
Maximum Clock Frequency with
No Feedback
62.5~ ~-
-
8
0
0
ns
)
Clock Pulse Duration, High
8
Clock Pulse Duration, Low
8 'I
~-
8
-
12
-
ns
15
-
25
ns
20
ns
25
ns
20
ns
2
Input or I/O to Output Enabled
-SCI '10
-
2
OE.!. to Output Enabled
-~ )10
3
Input or I/O to Output Disabled
-~ ~10
3
OEi to Output Disabled
-
-:
)10
15
15
15
-
1) Aefer to Switching Test Conditions section.
2) Calculated from 'max with internal feedback. Aefer to 'max Descriptions section.
3) Aefer to 'max Descriptions section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
: Input Aise and Fall Times
, Input Timing Aeference Levels
Output Timing Aeference Levels
i
+5V
GNDt03.0V
3ns 10"04 - 90%
1.5V
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (0/0)
UNDER TEST
OUtput Load Conditions (see figure)
Test Condition
1
2
3
Active High
Active Low
Active High
Active Low
R2
R1
R2
CL
2000
3900
3900
3900
3900
3900
50pF
50pF
50pF
5pF
5pF
co
2000
co
2000
- - + - - ' - - T E S T POINT
CL
C LINCLUDES JIG AND PROBE TOTAL CAPACITANCE
2-13
4/91.Aev.A
'LattiOO*
[JJ
.l...I
Specifications GAL 16VBB
Industrial
SemJconductor·
Corporation
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDo
Industrial Devices:
Ambient Temperature (TAl ............................ -40 to 85°C
Supply voltage (Veel
with Respect to Ground ...................... +4.50 to +5.50V
Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature .........•....................... -65 to 150°C
Ambient Temperature with
Power Applied .......................................• -55to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
OVer Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
TYP.3
MAX.
UNITS
-
0.8
V
VCC+1
V
-
-100
~
-
10
~
0.5
V
-
V
-
-
24
mA
-3.2
mA
-30
-
-150
mA
-
75
130
mA
MIN.
VIL
Input Low Voltage
VIH
Input High Voltage
IlL'
Input or 110 Low Leakage Current
OV S VIN S VIL (MAX.)
IIH
Input or 1/0 High Leakage Current
3.5V S VIN S Vee
VOL
Output Low Voltage
10L .. MAX. Vin .. VIL or VIH
-
VOH
Output High Voltage
10H = MAX. Vin .. VIL or VIH
2.4
Vss-O.5
2.0
10L
Low Level Output Current
10H
High Level Output Current
los'
Output Short Circuit Current
Icc
Operating Power Supply Current
Vce=5V VOUT= 0.5V
TA=25°C
VIL= 0.5V VIH = 3.0V ftoggle = 25MHz
Outputs Open (no load)
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc .. 5V and TA = 25 °C
CAPACITANCE (TA = 25'C, f
= 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM·
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vee = 5.0V, V, = 2.0V
1/0 Capacitance
8
pF
Vcc =5.0V, VIJO=2.0V
C'iO
·Guaranteed but not 100% tested.
2-14
4191.Rev.A
/1.l..JlLattice"
Specifications GAL 16V8B
Industrial
Semiconductor
Corporation
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER
-15
MIN. MAX.
UNITS
1
Input or I/O to Combinational Output
3
10
3
15
tco
1
Clock to Output Delay
2
7
2
10
ns
tcf2
-
Clock to Feedback Delay
-
6
-
8
ns
Setup Time, Input or Feedback belore Clocki
10
12
-
ns
th
I
-10
MIN. MAX.
DESCRIPTION
tpd
tsu
I
TEST
COND'.
ns
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
58.8
-
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcl)
62.5
-
50
-
MHz
1
Maximum Clock Frequency with
No Feedback
62.5
-
62.5
-
MHz
Clock Pulse Duration, High
8
8
8
-
ns
Clock Pulse Duration, Low
-
Hold Time, Input or Feedback alter Clocki
0
0
-
ns
45.5
-
MHz
,
I
fmax'
twh4
twt'
ten
tdis
-
8
2
Input or I/O to Output
3
10
2
OEL to Output
2
10
3
Input or I/O to Output
2
10
-
3
OEi to Output
1.5
10
-
ns
15
ns
15
ns
15
ns
15
ns
1) Reier to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3} Refer to fmax Descriptions section.
4) Clock pulses 01 widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
input Timing Reference Levels
Output Timing Reference Levels
+5V
GND t03.0V
3ns 10%-90%
1.5V
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (010)
UNDER TEST
- -.....- -.....-TESTPOINT
Output Load Conditions (see figure)
Test Condition
1
2
3
Active High
Active Low
Active High
Active Low
Rl
R2
CL
2000
3900
3900
3900
3900
3900
50pF
50pF
50pF
5pF
5pF
co
2000
00
2000
R2
1J
~
-
C llNClUDES JIG AND PROBE TOTAL CAPACITANCE
2-15
4191.Rev.A
U
1..1 j;Lattioo'
Specifications GAL 16V8A
Industrial
Semicondllctor
Corporation
ABSOLUTE MAXIMUM RATINGS(l)
RECOMMENDED OPERATING CONDo
Industrial Devices:
Supply voltage Vce ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C
Ambient Temperature (TA) ............................ -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.50 to +5.50V
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.2
MAX.
UNITS
-
0.8
V
Vcc+1
V
·10
~A
10
~A
0.5
V
-
V
VIL
Input Low Voltage
Vss-O.5
VIH
Input High Voltage
2.0
IlL
Input or I/O Low Leakage Current
OV:s VIN:S Vil (MAX.)
IIH
Input or I/O High Leakage Current
VIH:S VIN :S Vec
VOL
Output Low Voltage
10l= MAX. Vin = VIL or VIH
VOH
Output High Voltage
IOH
= MAX.
Yin
= VIL or VIH
2.4
-
10l
Low Level Output Current
10H
High Level Output Current
los'
Output Short Circuit Current
Icc
Operating Power
VIL = 0.5V
Supply Current
Outputs Open (no load)
Vee
VIH
= 5V
= 3.0V
24
mA
-3.2
mA
-150
mA
VOUT = O.SV
TA= 25°C
-30
= 25M Hz
l ·15/-25
-
75
130
mA
f10991o = 15M Hz
a -20/·25
-
45
65
mA
floggl.
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vce = 5V and TA = 25°C
CAPACITANCE (TA
=25°C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM'
UNITS
C,
Input Capacitance
8
pF
Vee = 5.0V, V,
CliO
I/O Capacitance
10
pF
Vee = 5.0V: VIIO = 2.0V
TEST CONDITIONS
= 2.0V
"Guaranteed but not 100% tested.
2-16
4/91.Rev.A
/fILatUre"
1.J
Specifications GAL 16V8A
Industrial
Semiconductnr
Corporation
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
-15
-20
-25
Mlt{;.,. )v1AX.
MIN. MAX.
MIN. MAX.
'ARAMETER
TEST
COND'.
tpd
1
Input or I/O to Combinational Output
3
tco
1
Clock to Output Delay
2
DESCRIPTION
-
tct>
tsu
th
?
"'10
~'
Clock to Feedback Delay
Setup Time, Input or Feedback belore Clock!
Hold Time, Input or Feedback alter Clocki
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
1
&t
>I' ""15
==::.
- i" .J 8
12 C~o ~ ~Ij
45.5~ ~-
twh4
twl4
ten
tdis
50
-
25
ns
11
2
12
ns
9
-
10
ns
15
41.6
-
37
-
ns
0
-
MHz
45.4
-
40
-
MHz
50
-
41.6
-
MHz
10
12
12
-
ns
10
-
-
20
-
25
ns
-
18
-
20
ns
-
20
-
25
ns
18
-
20
ns
13
0
"', '"
<: l t
ns
.-
62.5(~ \ -
Maximum Clock Frequency with
No Feedback
1
2
-
3
.1l
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tet)
1
20
;§
fi;:~~
fmax 3
3
UNITS
5
C
8
Clock Pulse Duration, High
Clock Pulse Duration, Low
8
¢' ."
C)~.'"
~-
.*
:i
2
Input or 110 to Output
2
OEJ. to Output
-~ 15
_ to! f15
3
Input or I/O to Output
- ;>' ;15
3
OEi to Output
-
:.~
"" ,$15
l&~
ns
) Refer to Switching Test Conditions section.
') Calculated lrom fmax with internal feedback. Refer to Imax Descriptions section.
;) Refer to fmax Descriptions section.
) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
GNDt03.0V
3ns 10% - 90%
1.5V
1.5V
Output Load
+5V
See Figure
,-state levels are measured 0.5V from steady-state active
weI.
FROM OUTPUT (O/Q)
UNDER TEST
)utput Load Conditions (see figure)
Test Condition
1
2
3
Active
Active
Active
Active
High
Low
Hlgn
Low
R1
R2
CL
2000
3900
3900
3900
3900
3900
50pF
50pF
50pF
5pF
5pF
~
i
2000
~
2000
---+--~~-TEST
R2
POINT
CL
C L INCLUDES JIG AND PROBE TOTAL CAPACITANCE
2-17
4/91.Rev.A
IllLattioo'
Specifications GAL 16VBB
GAL 16VBA
.l..I Corporation
Semiconductor
SWITCHING WAVEFORMS
INPUT or
va FEEDBACK
elK
INPUT or
va FEEDBACK
REGISTERED
OUTPUT
COMBINATORIAL
OUTPUT
Combinatorial Output
Registered Output
INPUT or
va FEEDBACK
OE
OUTPUT
OUTPUT
Input or UO to Output Enable/Disable
OE to Output Enable/Disable
elK
Iwl
elK
REGISTERED
FEEDBACK
Clock Width
fmax with Feedback
2-18
4191.Rev.l
aJLattire'
Specifications GAL 16V8B
GAL 16V8A
.l..J CorporaUon
Semiconductor
fmax DESCRIPTIONS
elK
.......................................... _--_ ..
elK
~
lOGIC
_. _. _
•• -
_
• • • • • _. -
-
-
-
_. -
-
-
_. -
eo • • _
•• _
00 _ . _
• • • •,
REGISTER
A RRAV
REGISTER
1---lsu---+~....
i ..f - - - Ico~
/o
.
II1
.
fmax with External Feedback 1/(tsu+tco)
• • • • OM • • • • • _
•• __________ •
____ •• _______ •
____ •
___
!
r.-14------tcl ----l~~1
1HI
0.•
]t
II·····PTH~~
II--PTL..H
Supply Voltage (V)
••••. PTH..L I
..,
4.711
t.t
,!!
. ...... ............
.... ....
0 .•
t.3
,.2-1.1
--- -" .......
J 0.'
t---t--+.,--t---;
t .•
,I--FALL
..... ".:~
PTH..L
i---t---t-i
Normallzad Tsu vs Vee
o
~
/
1.1
1
~
t
~
0.'
t.3
.'
iii
~~
,.,..
t.t
Z
0.'
1
..
to
t ..
..
...
Temperature (deg. C)
0.1
t ..
to
..,
.e.,
~
c!'l
.t .•
g'
.'
.'
/
_-0.5
..s.
./
J!
V
••••• RISE}
--FALL
..
...
·t
~
..
'
t ..
'
./
/
..... RISJ
/"
c!'l .t.'
FALL
..
Delta Tpd vs Output Loading
Delta Teo VI Output loading
to
RISE
~ ••••. ~SE I
I
--FALLI
/,.
L
/50
to
pr""
.. .' . ~
.-'
.'
Number of Outputs SwUching
~
'
/"
Number of Outputs SwUching
j .....
.. ..
Delta Teo vs # of Outputs
Switching
i-"'"
~.
-.
......
....... . /
/'
/... ' .'
Temperature (deg. C)
:.:-
.. , .. ' ;;.:.. p
..
to
~
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
] : -0.5
/'
HI
t
0.'
L
I
--PTL..
0-
"i
0.'
0.1
••••. PTH..L
t ••
/
~.,
1--;':".,
/.
..
150
200
..'
~.,
.'
tOO
V
--FALLI
29
~
L
50
300
.'
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
2-22
4191.Rev.A
:Lattice~
!1J
.l.J Corporation
Semiconductor
Specifications GAL 16V8S
Typical Characteristics
Vol vs 101
Voh VI Ioh
Voh VI loh
....
/
0.75
,/'
,/
....
V
0.00
........
/
""-
---
....
20.00
40.00
10.00
'0.00
100.00
0.00
10.00
20.00
1.10
~
~
0.80
....
5.00
Supply
"il
.~
-----
0.80
4.75
5.25
Vo~age
I'-..
I'---
1.00
1....
....
1""- I'..
Z5
1'5
tOO
125
Temperature (deg. C)
4.00
3.00
1.10
~
L
1,·00
V
...
.A.
.
.......
L
V
.
.
...
Frequency (MHz)
Input Clamp (Vik)
.....
/
1/
I'-
..
/
/
60
70
1.50 2.00 2.50 3.00 3.50
.l;l
"2
0.80
~
Vin(V)
.... ....
Normalized Icc vs Fraq.
f'-,
(V)
/1\
1.00
I'-..
---r--10h(mA)
1.10
3D
0.00 0.50
0.00
u.
<-,40
.§. ..
.....
10.00
....
••
••
II
50.00
12.
Delta Icc vs Vin (1 input)
J \
CO.OO
Normalized Icc vs Temp
V
1.00
30.00
Ioh(mA)
12.
1
"'- r-.
'.75
Normalized Icc vs Vee
"il
r- r--
,/
101 (mA)
.~
42'
/
/
1/
• 00
4.00
·2.00
·1.$0
-1.00
-0.50
0.00
Vik(V)
2·23
4191.Rev.A
I'
~
'Lattice@
[J;J
.l..i
Specifications GAL 16V8A
Typical Characteristics
Semiconductor
CorporaUon
Normalized Tsu vs. Vee
Normalized Tpd VS. Vee
Oil
1-
al
.~
---
1
1
OJ
E
o
Z
0
Normalized Tco vs. Vee
"-
1.3
-
1.'
0
- r--
~
1.1
'0
1'"
1.0
~
0.'
-
0.'
t1'74-!:
. .~--.-!-.n~----:,':~----:,4-",:--~,
...
0.7
..
Normalized Tpd vs. Temperature
1.2
E
0
0.'
z
0.•
V
/
0.7
12
V
'"
1.1
a1
1.0
III
V
~
IV
§
Z
0.'
/
0.7
·25
25
50
75
100
'25
V
0.8
0.•
·so
V
V
0
·25
~
'iii
0.95
E
~
....
.92
,/
z
2S
50
7S
100
V
/
/
• of Outputs
~/
-'
12
100
so
V
Normalized Icc vs. Vcc
/
12
~
/
V
:?
E 0.'
a
·50
VOL (V)
200
...........
" ...............
•.SO
300
4.75
5.00
....
5.25
Supply Voltage (V)
Normalized Icc vs. Temperature
VOH
'.3
'" " ""'"
'2
~
........
.s
.Q
V
~
.!:i 1.0
'iii
Z
IOH VS.
::t
/
............
'.1
'0
8 -
2.
~
Vee
1/0/0
VOIQ
1/0/0
110/0
GAL20VSAlB
NC
110/0
IIO/Q
1/0/0
NC
Top View
110/0
110/0
UOIO
110/0
1I0/Q
0
z
"
!I11~
'"
-
1/0/0
"~
1/0/0
GND
IIOE
Copyright e1991 Lattice Semicondudor Corp. GAL. PCMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc·
tor Corp. PAl is a registered trademark of Advanced Micro Devices, Inc. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503) 681-3037
2-25
May 1991.Rev.A
!lJtattiOOGl
Specifications GAL20V8B
GAL20V8A
.l.J Corporation
Semironducwr
GAL20V8A/B ORDERING INFORMATION
Commercial Grade Specifications
Ordering #
Tpd (ns)
Tsu (n8)
Tco (ns)
Icc (mA)
7.5
7
5
115
GAL20V8B-7W
28-Lead PLCC
10
10
7
15
12
25
15
10
12
Package
115
GAL20V8B-l0W
28-Lead PLCC
115
GAL20VSA-l0LP
24-Pin Plastic DIP
115
GAL20V8A-l0LJ
28-Lead PLCC
55
GAL20VSA-15QP
24-Pin Plastic DIP
55
GAL20V8A-I5QJ
2B-Lead PLCC
115
GAL20V8A-15LP
24-Pin Plastic DIP
115
GAL20V8A-15LJ
28-Lead PLCC
55
GAL20V8A-25QP
24-Pin PlastK: DIP
55
GAL20V8A-25QJ
28-Lead PLCC
90
GAL20V8A-25LP
24-Pin Plastic DIP
90
GAL20V8A-25LJ
28-Lead PLCC
Industrial Grade Specifications
T5U (n5)
Tco (n5)
Icc (mA)
15
12
10
130
GAL20V8A-15LPI
24-Pin Plastic DIP
130
GAL20V8A-15WI
28-Lead PLCC
20
13
11
65
GAL20V8A-200PI
24-Pin Plastic DIP
65
GAL20V8A-200JI
28-Lead PLCC
65
GAL20V8A-25QPI
24-Pin Plastic DIP
65
GAL20V8A-25OJ1
28-Lead PLCC
130
GAL20V8A-25LPI
24-Pin Plastic DIP
130
GAL20V8A-25WI
28-Lead PLCC
25
15
12
Ordering
#
Tpd (n5)
Package
PART NUMBER DESCRIPTION
xxxxxxxx - xx X X X
GAL20V8A
GAL20V8B
Device N,me
~
' - - - - - Grade
Speed (n5)
L = Low Power Power
Q = Quarter Power
L -_ _ _ _
2-26
Blank = Commercial
I = Industrial
Package P =Plastic DIP
J = PLCC
4191.Rev.A
'Lattice@
~
~ Corporation
Serniconducwr
Specifications GAL20V8B
GAL20V8A
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accomplished by development soflwarelhardware and is completely
transparent to the user.
There are three global DLMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes is illustrated in the following pages. Two global bits, SYN
and ACO, control the mode configuration for all macrocells. The
XDR bit of each macrocell controls the polarity of the output in any
of the three modes, while the ACI bit of each of the macrocells
controls the input/output configuration. These two global and 16
individual architecture bits define all possible configurations in a
GAL20V8A1B. The information given on these architecture bits
is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin
definitions, so the user should not need to directly manipulate
these architecture bits.
The following is a list of the PAL architectures that the GAL20V8A
and GAL20V8B can emulate. It also shows the DLMC mode under which the devices emUlate the PAL architecture.
PAL Architectures
Emulated by GAL20V8A1B
GAL20V8A1B
Global OlMC Mode
20R8
20R6
20R4
20RP8
20RP6
20RP4
Registered
Registered
Registered
Registered
Registered
Registered
2018
20H8
20P8
Complex
Complex
Complex
l4l8
l6l6
l8l4
2012
l4H8
l6H6
l8H4
20H2
l4P8
l6P6
l8P4
20P2
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
COMPILER SUPPORT FOR OLMC
Software compilers support the three different global DLMC
modes as different device types. These device types are listed
in the table below. Most compilers have the ability to automatically select the device type, generally based on the register usage
and output enable (DE) usage. Register usage on the device
forces the software to choose the registered mode. All combinatorial outputs with DE controlled by the product term will force
the software to choose the complex mode. The software will
choose the simple mode only when all outputs are dedicated
combinatorial without DE control. The different device types listed
in the table can be used to override the automatic device selection
by the software. For further details, refer to the compiler software
manuals.
In registered mode pin 1 and pin 13 are permanently configured
as clock and output enable, respectively. These pins cannot be
configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 13 become dedicated inputs and
use the feedback paths of pin 22 and pin 15 respectively. Because
of this feedback path usage, pin 22 and pin 15 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
18 and 19) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each
mode.
ABEL
CUPL
LOG/IC
OrCAD-PLD
PLDeslgner
TANGO-PLD
Registered
Complex
Simple
Auto Mode Select
P20V8R
G20V8MS
GAL20V8 R
"Registered"'
P20V8R2
G20V8R
P20V8C
G20V8MA
GAL20V8 C7
"Complex"'
P20V8C2
G20V8C
P20V8AS
G20V8AS
GAL20V8 C8
"Simple"'
P20V8C2
G20V8AS3
P20V8
G20V8
GAL20V8
GAL20V8A
P20V8A
G20V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
2-27
4/91.Rev.A
LattiOO@
[JJ
1.J
Specifications GAL20V8B
GAL20V8A
Semironductor
Corporation
REGISTERED MODE
In the Registered mode, macrocells are configured as dedicated
registered outputs or as 110 functions.
mode. Dedicated input or output functions can be implemented
as subsets of the VO function.
Architecture configurations available in this mode are similar to
the common 20R8 and 20RP4 devices with various permutations
of polarity, I/O and register placement.
Registered outputs have eight product terms per output. I/O's
have seven product terms per output.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or
I/O. Up to eight registers or up to eight I/O's are possible in this
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.
elK
Registered Configuration for Registered Mode
'.. ... - ..
-SYN=O.
-ACO=1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 =0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 13 controls common OE for the registered outputs.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE.
,_._----------------------------------,
OE
Combinatorial Configuration for Registered Mode
- SYN=O.
-ACO:1.
- XOR=O defines Active low Output.
- XOR=1 defines Active High Output.
- AC1 =1 defines this output configuration.
- Pin 1 & Pin 13 are permanently configured as CLK &
OE.
'..----------------------.---------------------,
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
2-28
4/91.Rev.A
Specifications GAL20V8B
GAL20V8A
REGISTERED MODE LOGIC DIAGRAM
DIP (PLCC) Package Pinouts
1(2)
D
....
....
0
2(3)
•
B
,.
11
20
..
211
D
" "
".
Pro
-CJ23(27)
0000
~
0210
3(4)
D
03,.
~
~
06DO
4(5)
D
"'0
0920
5(6)
~
==
~
3=f
~
~
09S0
-01240
6(7)
~
~
~
1280
OLMC 22
XDR·2560
AC1·2632
OLMC 21
XOR·2561
AC1·2633
OLMC 20
OLMC 19
1600
.r,
3=f
"10
8(10)8
1920
OLMC 17
XDR·2565
AC1·2637
OLMC 16
XOR·2566
AC1·2638
22DO
9(11 )~
2240
-0
OLMC 15
XDR·2567
AC1·2639
2520
10{12) 0
0='
0='
rJ
9(23)
XDR·2563
AC1·2635
XOR·2564
AC1·2636
7(9)8
tr"
(25)
0(24)
XOR·2562
AC1·2634
OLMC 18
1560
rr'
2(26)
[J
~1 8(21)
rJ
~1 7(20)
11
16(19)
[J
[J
rJ
~
[J
11(13) 0
15(18)
-CJ 14(17)
DE
"03
~
13(16)
SYN·2704
ACO·2705
2-29
4/91.Rev.A
~attice·
!1J
.l..J Corporation
Semioonductor
Specifications GAL20VBB
GAL20VBA
COMPLEX MODE
In the Complex mode, macrocells are configured as output only
or 1/0 functions.
pability. Designs requiring eight IIO's can be implemented in the
Registered mode.
Architecture configurations available in this mode are similar to
the common 20L8 and 20P8 devices with programmable polarity
in each macrocell.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
13 are always available as data inputs into the AND array.
Up to six IIO's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the I/O function. The
two outer most macrocells (pins 15 & 22) do not have input ca-
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
................... _------_ ..... _............
~OR
Combinatorial 1/0 Configuration for Complex Mode
J
-SYN-1.
-ACO.. 1.
- XOR.O defines Active Low Output.
- XOR=1 defines Active High Output.
-AC1=1.
- Pin 16 through Pin 21 are configured to this function .
...... -............ -- ................................
po . . . - . . . . . . . . . . _ - . . . . - - • • - - . . . . . . . - - . - - - _ . . . - . . .
i;
P-r,D
XOR
Combinatorial Output Configuration for Complex Mode
Cl--o
-- .... ---.-.. _-_ ...... __ ._------------_ ...
-SYN=1.
-ACO.. 1.
- XOR..Odefines Active Low Output.
- XOR=1 defines Active High Output.
-AC1-1.
- Pin 15 and Pin 22 are config~red to this function.
Note: The development software configures all of the architecture control bits.and checks for proper pin usage automatically.
!
2-30
/
4191.Rev.A
!lJ
~
tBttice
®
Specifications GAL20V8B
GAL20V8A
Semironductor
Corporation
COMPLEX MODE LOGIC DIAGRAM
DIP (PLCC) Package Pinouts
1(2)
~
• • •
12
11
10
14
21
.. .. ....
.A
.,,,
3(4)
4(5)
~
a=
:a=
0280
'tj=
""
".,
"'--':
~
.--..
XOR-2560
ACl-2632
XOR-2561
ACl-2633
~
D
OLMC 22
OLMC 21
"40
5(6)
j
PlD
2(3) L.>---
:a= OLMC 20
~
""
XOR-2562
ACl-2634
,."
OLMC 19
6(7)
-
.---..
-=-
1240
OLMC 18
1580
XOR-2564
ACl-2636
~
7(9)0
""
.0-
1880
OLMC 17
8(10)D
""
OLMC 16
=8=
9(11 )8
10(12)
OLMC 15
.."
.....
11(13),--,.
J
,..r,21 (25)
~_J
=:l
--.::J
n
v
I
XOR-2567
ACl-2639
1113
02
J-G1
M
~v
~
v
XOR-2566
ACl-2638
2240
,--,.
-r122(26)
XOR-2565
ACl-2637
~
22"
0 ...
XOR-2563
ACl-2635
"80
23(27)
~
0(24)
9(23)
18(21)
-Y"'l1 7(20)
J
J~
16(19)
15(18)
-a 14(17)
-a 13(16)
fI4.U8EII B.fCIlIONIC 8IGNAlURE FU8EB
l&:7iC.·....
M
L
8
8
B
B
. . _,:01
2-31
SYN-2704
ACO-2705
4/91_Rev.A
Specifications GAL20VBB
GAL20VBA
SIMPLE MODE
In the Simple mode, pins are configured as dedicated inputs or
as dedicated, always active, combinatorial outputs.
Architecture configurations available in this mode are similar to
the common 14L8 and 16P6 devices with many permutations of
generic output polarity or input choices.
Pins 1 and 13 are always available as data inputs into the AND
array. The "center" two macrocells (pins 18 & 19) cannot be used
in the input configuration.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
All outputs in the simple mode have a maximum of eight product
terms that can control the logic. In addition, each output has
programmable polarity.
...... _--------------_. __ ._------.----------
Combinatorial Output with Feedback Configuration
for Simple Mode
Vee
- SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR.. 1 defines Active High Output.
- AC1 =0 defines this configuration.
- All OLMC except pins 18 & 19 can be configured to
this function.
Combinatorial Output Configuration for Simple Mode
- SYN=1.
-ACO=O.
- XOR=O defines Active Low Output.
- XOR= 1 defines Active High Output.
- AC1 =0 defines this configuration.
- Pins 18 & 19 are permanently configured to this
function.
.'-------._.---------------------------------_.:
Dedicated Input Configuration for Simple Mode
-SYN .. 1.
-ACO-O.
- XOR..Odefines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 =1 defines this configuration.
- All OLMC except pins 18 & 19 can be configured to
this function .
.._---------------------------.--------------,.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
2-32
4f91.Rev.A
I,
::j
flJ
~ Corporation
Semironductor
LattJce~
Specifications GAL20V8B
GAL20V8A
SIMPLE MODE LOGIC DIAGRAM
DIP (PlCC) Package Pinouts
1(2) LJ
, • • ,.
"
..
1M
211
.
....
0
j
II
.A
2(3) LJ
3(4)
....
"'~
OLMC 22
::a=:::t
....
~
OLMC 21
....
::::a=:::::::I
....
4(5) LJ
....
....
.0.
~
.....
5(6)L..J
....
XOR·2561
AC1·2633
OLMC 20
XOR·2562
AC1·2634
~
OLMC 19
::a=:::t
'240
::;,
D
7(9) L....J
b
J ...
-cl22(26)
J ..
n
-cl21 (25)
n
n20(24)
.A
"..
6(7)
XOR·2560
AC1·2632
rCJ23( 27)
'2"
~
"..
::::a=:::::::I
"..
-0~
"SO
XOR·2563
AC1-2635
OLMC18
XOR·2564
AC1·2636
OLMC 17
XOR·2565
AC1-2637
J
h
J
0 1 9(23)
Jb..
"""'1 8(21)
n
-C"] 17(20)
n
-nl 6(19)
J
8(10)
""
22,.
OLMC 16
==
~
~
9(1 1)
2240
XOR·2566
AC1-2638
OLMC 15
9::::::=1
25"
XOR·2567
AC1-2639
J ...
Jb,. . . .-
15(18)
.A
10(1 2)D
....
11(1 3)
I
-CJ 14(17)
~l
84-USER ElECI'RONIC SIGNATURE FUSSS
1:\=,··....
101
8
L
S
B
B
.. . &;i8if:~1
2-33
13(16)
2'"
SYN·2704
ACO·2705
4191.Rev.A
I.;
1.1
Ii
~
tattice®
[JJ
.l.I
Specifications GAL20V8B
Commercial
Semiconductor
Corporation
ABSOLUTE MAXIMUM RATINGS(l)
RECOMMENDED OPERATING CONDo
Commercial Devices:
Ambient Temperature (TA ) •••••••••••••••••••••••••••••••• 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.75 to +5.25V
Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee +1.0V
Off-state output voltage applied ........ ,. -2.5 to Vee +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................ -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP."
MAX.
UNITS
-
0.8
V
VCC+1
V
-100
!LA
10
!LA
0.5
V
-
V
VIL
Input Low Voltage
Vss-0.5
VIH
Input High Voltage
2.0
ilL'
Input or 1/0 Low Leakage Current
OV ~ VIN ~ VIL (MAX.)
IIH
Input or 1/0 High Leakage Current
3.5V ~ VIN ~ Vee
VOL
Output Low Voltage
10L=MAX. Yin = VIL or VIH
-
VOH
Output High Voltage
10H = MAX. Vin = VIL or VIH
2.4
-
-
-
24
mA
-3.2
mA
-30
-
-150
mA
-
75
115
mA
10L
Low Level Output Current
10H
High Level Output Current
los2
Output Short Circuit Current
Vcc=5V VOUT= 0.5V
Icc
Operating Power Supply Current
VIL= 0.5V VIH = 3.0V ftoggle = 25MHz
TA= 25°C
Outputs Open (no load)
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for moreJnformation.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C
CAPACITANCE (TA
=25°C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vee =5.0V, V, = 2.0V
CliO
1/0 Capacitance
8
pF
Vcc = 5.0V, V'iO = 2.0V
"Guaranteed but not 100% tested.
2-34
4/91.Rev.A
flJ
UJtticeGP
~ C0i'p(X'8t/01l
Specifications GAL20V8B
Commercial
Semironductor
AC SWITCHING CHARACTERISTICS
OVer Recommended Operating Conditions
PARAMETER
TEST
COND'.
1
tpd
1
tco
tcf2
-
-
tsu
th
fmax 3
·7
·10
MIN. MAX.
MIN. MAX.
DESCRIPTION
I 8 outputs switching 3
I 1 output switching -
Input or 110 to Combinational Output
UNITS
7.5
3
10
ns
7
-
-
ns
Clock to Output Delay
2
S
2
7
ns
Clock to Feedback Delay
-
3
-
6
ns
Setup lime, Input or Feedback before Clockt
7
10
-
ns
0
-
ns
S8.8
-
MHz
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + teo)
83.3
-
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
100
-
62.S
-
MHz
1
Maximum Clock Frequency with
No Feedback
100
-
62.S
-
MHz
-
8
-
ns
8
Hold lime, Input or Feedback after Clockt
0
twh4
-
Clock Pulse Duration, High
S
twt'
-
Clock Pulse Duration, Low
S
ten
2
Input or 110 to Output
3
9
3
10
ns
2
OE.!. to Output
2
6
2
10
ns
2
9
2
10
ns
1.S
6
1.S
10
ns
tdis
3
Input or 1/0 to Output
3
OEt to Output
ns
1) Refer to Switching Test Conditions sectIOn.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall limes
Input Timing Reference Levels
OutpU1liming Reference Levels
+5V
GNDt03.0V
3ns 10%-90%
1.SV
1.SV
Output Load
See Figure
3-state levels are measured O.SV from steady-state active
level.
FROM OUTPUT (010)
UNDER TEST
--+---..- TEST POINT
Output Load Conditions (see figure)
Test Condition
1
2
3
Active High
Active Low
Active High
Active Low
RI
R2
CL
2000
3900
3900
3900
3900
3900
SQpF
SOpF
50pF
SpF
5pF
00
-
2000
2000
R2
CL
C LlNCLUDESJIG AND PROBE TOTAL CAPACITANCE
2-35
4/91.Rev.A
Lattice~
!IJ
1£ Corporation
SemiconduGwr
Specifications GAL20V8A
Commercial
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDo
Supply voltage vee ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................-55 to 125°C
Commercial Devices:
Ambient Temperature (TA ) •••••••••••••••••••••••••••••••• 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.75 to +5.25V
1.Stresses above those listed under the· Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.2
MAX.
UNITS
-
0.8
V
VcC+1
V
-10
J.lA
10
J.lA
V
VIL
Input Low Voltage
Vss-O.5
VIH
Input High Voltage
2.0
IlL
input or 1/0 Low Leakage Current
OV ~ VIN ~ VIL (MAX.)
-
-
-
0.5
2.4
-
-
V
-
-
24
rnA
-3.2
rnA
-150
rnA
75
90
rnA
75
115
rnA
45
55
rnA
Input or 110 High leakage Current
VIH ~ VIN ~ Vee
VOL
Output Low Voltage
10L =MAX. Yin
VOH
Output High Voltage
IOH = MAX. Vin = VIL or VIH
IIH
10l
low Level Output Current
10H
High level Output Current
los'
Icc
Output Short Circuit Current
Vcc=5V
Operating Power
VIL = 0.5V
Supply Current
Outputs Open (no load)
VIH = 3.0V
=VIL or VIH
VOUT= 0.5V
TA = 25°C
f,oggl8 = 15MHz
L·25
flO9gl8 = 25MHz
L -101-15
f'099I8 = 15MHz
0·15/-25
-30
-
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc =5V and TA = 25 ·C
CAPACITANCE (TA
=25°C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM-
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vcc = 5.0V, V, = 2.0V
ClIO
1/0 Capacitance
10
pF
Vee = 5.0V, VIIO = 2.0V
'Guaranteed but not 100% tested.
2-36
4191.Rev.A
~atticee
!IJ
.lJ CorporaUon
SemioonducUJr
Specifications GAL20V8A
Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER
TEST
COND'.
-10
-15
-25
MIN. MAX.
MIN. MAX.
MIN. MAX.
DESCRIPTION
tpd
1
Input or
teo
1
va to Combinational Output
3
10
3
15
3
UNITS
25
ns
Clock to Output Delay
2
7
2
10
2
12
ns
tel2
Clock to Feedback Delay
-
7
-
8
-
10
ns
tsu
Setup Time, Input or Feedback before Clocki
10
-
12
-
15
-
ns
0
-
0
-
ns
Maximum Clock Frequency with
External Feedback, 1/(tsu + teo)
58.8
-
45.5
-
0
1
37
-
MHz
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tel)
58.8
-
50
-
40
-
MHz
1
Maximum Clock Frequency with
No Feedback
62.5
-
62.5
-
41.7
-
MHz
-
8
-
12
-
ns
8
12
-
ns
15
-
25
ns
20
ns
25
ns
20
ns
th
Hold Time, Input or Feedback after Clocki
fmax 3
twh4
Clock Pulse Duration, High
B
twl4
Clock Pulse Duration, Low
B
ten
tdis
-
va to Output Enabled
2
Input or
2
OE.!. to Output Enabled
va to Output Disabled
3
Input or
3
OEi to Output Disabled
10
10
10
10
-
15
15
15
-
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to Imax Descriptions llection.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
GNDto 3.0V
3ns 10%-90%
1.5V
1.5V
Output Load
+5V
See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition
1
2
3
Active
Active
Active
Active
High
Low
High
Low
R,
Rz
CL
2000
3900
3900
3900
3900
3900
500F
50pF
50pF
5pF
5pF
00
2000
00
2000
FROM OUTPUT (010)
UNDER TEST
---+----+--TEST POINT
Cl
CL INCLUDES JIG AND PROBE TOTAL CAPACITANCE
2-37
4191.Rev.A
:Lattice~
!1J
.l..J Corporation
Scmiconductnr
Specifications GAL20V8A
Industrial
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDo
Industrial Devices:
Ambient Temperature (TA) ............................ -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.50 to +5.50V
Supply voltage Vee ....................................... -{).5 to +7V
Input voltage applied ........................... -2.5 to vee + 1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................-55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
OVer Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
VIL
Input Low Voltage
VIH
Input High Voltage
CONDITION
MIN.
TYP."
MAX.
UNITS
Vss-O.S
-
0.8
V
2.0
-
VcC+1
V
-10
J-lA
10
J-lA
0.5
V
-
V
mA
-
IlL
Input or 110 Low Leakage Current
OV S VIN S Vil (MAX.)
IIH
Input or VO High Leakage Current
VIH S VIN S Vee
VOL
Output Low Voltage
101. - MAX. Yin - Vil or VIH
-
VOH
Output High Voltage
IOH .. MAX. Vin. VIL or VIH
2.4
-
-
10L
Low Level Output Current
-
-
24
10H
High Level Output Current
-
mA
los'
. Output Short Circuit Current
-
-3.2
-150
mA
75
130
mA
45
65
mA
Icc
TA- 25·C
-30
Operating Power
Vccz 5V YOUTz 0.5V
VIL= 0.5V VIH=3.0V
floggle = 25MHz
L ·15/-25
-
Supply Current
Outputs Open (no load) floggle .. 15M Hz
a -20/-25
-
1) One output at a time for a maximum duration of one second. Vout .. 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc - 5V and TA" 25 ·C
CAPACITANCE (TA
.
=25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM-
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vee = 5.0V, V, = 2.0V
110 Capacitance
10
pF
Coo
Vee = 5.0V, VIIO= 2.0V
Guaranteed but not 100% tested .
2-38
4/91.Rev.A
:Lattice
[JJ
.l..tI
Specifications GAL20V8A
Industrial
GD
Semiconductor
Corporation
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
~ARAMETER
TEST
CONO'.
·15
·20
-25
MIN. MAX.
MIN. MAX.
MIN. MAX.
OESCRIPnON
UNITS
tpd
1
Input or I/O to Combinational Output
3
15
3
20
3
25
ns
teo
1
Clock to Output Delay
2
10
2
11
2
12
ns
tcf2
Clock to Feedback Delay
-
8
-
9
-
10
ns
tsu
Setup lime, Input or Feedback before Clocki
12
15
-
ns
Hold lime, Input or Feedback after Clocki
0
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + teo)
45.5
-
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tel)
50
-
45.4
-
40
-
MHz
1
Maximum Clock Frequency with
External Feedback
62.5
-
50
-
41.6
-
MHz
th
fmax 3
0
-
ns
41.6
-
37
-
MHz
13
0
twh'
Clock Pulse Duration, High
8
-
10
-
12
-
ns
twt'
Clock Pulse Duration, Low
8
-
10
-
12
-
ns
15
20
-
25
ns
20
ns
25
ns
18
20
ns
ten
tdis
2
Input or I/O to Output
2
OEJ.to Output
-
3
Input or 110 to Output
-
15
-
3
OEi to Output
-
15
-
15
18
20
-
) Refer to Switching Test Conditions section.
~) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
i) Refer to fmax Descriptions section .
.) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input liming Reference Levels
Output liming Reference Levels
GNDt03.0V
3ns 10%-90%
1.5V
1.5V
Output Load
+5V
See Figure
i·state levels are measured O.SV from steady-state active
weI.
>utput Load Conditions (see figure)
Test Condition
1
2
3
Rl
R2
CL
..
3900
3900
3900
3900
3900
50DF
50pF
SOpF
5pF
5pF
2000
Active
Active
Active
Active
High
Low
High
Low
..
2000
2000
FROM OUTPUT (0/0)
UNDER TEST
- - - . . - - -......-
TEST POINT
CL
CL INCLUDES JIG AND PROBE TOTAL CAPACITANCE
2-39
4/91.Rev.A
!lJ:Lattice-
Specifications GAL20V8B
GAL20V8A
1.1 Corporation
Semiconducwr
SWITCHING WAVEFORMS
INPUT or
LIO FEEDBACK
INPUT or
LIO FEEDBACK
COMBINATORIAL
OUTPUT
\\\\\\\\\t:;~T
\\\\\\\\\\\\\\il==
ClK
REGISTERED
OUTPUT
Combinatorial Output
INPUT or
110 FEEDBACK
Registered Output
OE
OUTPUT
OE to Output Enable/Disable
- Input QrllOto $utput EioableJDlsable
elK
elK
Clock Width
REGISTERED
FEEDBACK
fmax with Feedback
4/91.Rev.A
flJ'Lattioo*
Specifications GAL20V8B
GAL20V8A
~ SemioonductlJr
Corporauon
fmax DESCRIPTIONS
elK
····
·
, • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • __
LOGIC
ARRAY
..
• • • _o __ o _ . _ _ _ ,
elK
REGISTER
·'.. ---_ ... __ ..................... _---_ ............ ..
I0Il1"1---10 u---."II4"f---- Ico---.t
fmax with External Feedback 1/(tsu+tco)
foII~I-----tcf----t.~1
Note: fmax with external feedback is calculated from measured
lsu and tco.
foII~I-----tPd-----I.~1
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf - 1lfmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
CLK
[................................. ·············1
·
.
LOGIC
REGISTER
ARRAY
~
• • • • • • • • 00 _
•• _
••••••••• _
• • • • • _. _____ •
_. _
••••• _.'
fmax Without Feedback
Note: fmax with no feedback may be less than 1ltwh + twl. This
is to allow for a clock duty cycle of other than 50%.
2-41
4191.Rev.A
VI:!!!!!/
~
horporatJon
Specifications GAL20V8B
GAL20V8A
ELECTRONIC SIGNATURE
An electronic signature (ES) is provided in every GAL20V8AIB
device. It contains 64 bits of reprogram mabie memory that can
contain user defined data. Some uses Include user 10 codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the securitycell.
NOTE: The ES is included in checksum calculations. Changing
the ES will alter checksum.
SECURITY CELL
The security cell is provided on all GAL20V8AIB devices to prevent unauthorized copying of the array patterns. Once programmed, the circuitry enabling array is disabled, preventing
further programming or verification of the array. The cell can only
be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. Signature data is always available to the user.
LATCH-UP PROTECTION
OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired
(i.e., illegal) state into the registers. Then the machine can be
sequenced and the outputs tested for correct next state conditions.
GAL20V8AIB devices include circuitry that allows each registered
output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If
necessary, approved GAL programmers capable of executing text
vectors perform output register preload automatically.
INPUT BUFFERS
GAL20V8A and GAL20V8B devices are designed with TTL level
compatible input buffers. These buffers have a characteristically
high impedance, and present a much lighter load to the driving
logic than bipolar TTL devices.
The GAL20V8B input and I/O pins have built-in active pull-ups.
As a result, unused inputs and I/O's will float to a TTL "high" (logical "1"). In contrast, the GAL20V8A does not have active pullups within their input structures. Lattice recommends that all unused inputs and tri-stated 110 pins for both devices be connected
to another active input, Vce' or Ground. Doing this will tend to improve noise immunity and reduce Ice for the device.
GAL20V8AIB devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the
circuitry to latch. Additionally, outputs are designed with n-<:hannel
pull-ups instead of the traditional p-<:hannel pull-ups to eliminate
any possibility of SCR induced latching.
DEVICE PROGRAMMING
"lYplcallnput Pull-up Characteristic
GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers. Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
.
.
~
./
·20
./
u
i
-40
.5
-60
----
o
L
./
1.0
2.0
Input Voltag' (Volts)
2-42
4191.Rev.A
Lattice~
!lJ
~ Corporation
Semironductor
Specifications GAL20V8B
GAL20V8A
POWER-UP RESET
Vee
OV
VIH
elK
...-......-+"',....-,-,--,.1,--------VALID CLOCK SIGNAL
VIL
INTERNAL
REGISTER
Q·OUTPUT
INTERNAL REGISTER
RESET TO LOGIC 0
FE EDBACK/EXTERNAl
OUTPUT REGISTER
EXTERNAL REGISTER
OUTPUT = LOGIC 1
Circuitry within the GAL20V8A and GAL20V8B provides a reset
signal to all registers during power-up. All internal registers will
have their outputs set low after a specified time (t RESET ' 45~
MAX). As a result, the state on the registered output pins (if they
are enabled through OE) will always be high on power-up, regardless of the programmed polarity of the output pins. This feature
can greatly simplify state machine design by providing a known
state on power-up.
a
The timing diagram for power-up is shown above. Because of
the asynchronous nature of system power-up, some conditions
must be met to guarantee a valid power-up reset of the
GAL20V8A and GAL20V8B. First, the Vee rise must be monotonic. Second, the clock input must become a proper TIL level
within the specified time (tpR ' 100ns MAX). The registers will reset
within a maximum of tRESET time. As in normal system operation,
avoid clocking the device until all input and feedback path setup
times have been met.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
.~P.
PIN
Feedback
Active Pull-up
Chait
(GAL20VSB only)
Vee
Tr~Slate
Control
: ESD
: Pro1ection
Cireu~
.i---------.-------.'.
Data
Output
PIN
Vee
.__y. __ __
l Vref l
I I
':._--- _eo!
PIN
: ESD
j Protection
: Cireu~
..
._-----------_.-
Feedback
(To Input Buffer)
Typ. Vref =3.2V
Typ. Vref • 3.2V
Typical Output
lYpicallnput
2-43
4/91.Rev.A
:LattiOO@
[JJ
~
Specifications GAL20V8B
Typical Characteristics
Semironductor
CH
I
tr-===::j::',;';;';,;"~,,:,,,,=~::::d
......
4.50
~
...
5.25
...
.~.
5.25
Normalized Teo vs Temp
Normalized Tsu vs Temp
~
I
V
1.4
~=:~::l
1.2
,;;:2"
o
~
/
1.1
-g
~
0.9
9.
~
12'
,.'
g
"
-,
13
~
./
,.'
V
V
~
V
-1.5
0.9
p
...
,.'
~"
I-'
.s.
25
.
12.
Temperature (deg. C)
Delta Teo vs # of Outputs
Switching
~
"
~
~sJ
.. ,
.'
] : -0.5
./
-1
~
0 _ 1.5
f/"
,.'
V
V
I-"""
c:.:- P
••••. RISE}
--FALL
-2
-2
Number of Outputs
Sw~ching
Number of Outputs Sw~ching
Delta Teo vs Output Loading
Delta Tpd vs Output Loading
£.6
...
. ........ . /
L
•.7
--FAeL
10
1
L
/ .." ,
--PTL.>HJ
Temperature (deg. C)
-0.5
~
~
125
Delta Tpd vs # of Outputs
Switching
"0
1.1
/
l
~
.
25
Temperature (deg. C)
_
1l
:z
.s.
......... PTH->L
~ 1.2
.,;.;- "
..•
•.7
2.
1.3
~ r--
1
§
~
0.7
·55
5.00
Normalized Tpd vs Temp
--PTL.>HI
",
4.75
4.50
5.50
Supply VoHage (V)
1
0.9
5.00
1.3
~1.1
~
4.75
Supply VoHage (V)
-g
.~
PTL·>H
Supply Voltage (V)
••••. PTH.>L
"0
~
PTH.>L}
•. 9
•.• +---f__---+---+----l
1.3
1.2
N
l'
..........
•.9
5~.
525
5.00
. ......
r-
~
•.• +--~f__---+---f----l
4.75
..........
II"""
Il
1.1
~
FAle
'" '"
:1€
+-----jf__--+---f----l
...
I·····
Rm~~
I
1.1
J!
]
", ",
•. 9
1.2
1.2
PTH·>L
--+--+-1
1.1 .......
Normalized Tsu vs Vee
Normalized Teo VB Vee
j.....
,.
~ ••••.
RISEl
--FALLI
V
/'
g6
~
I
/'
o
~
/ . ~"
/-
RISE
--FALLl
4
J;!
~
2
/.
"
/.
-:-;.,
~,
,
~
-2
-2
50
100
150
200
250
300
50
tOO
150
200
250
300
Output Loading (pF)
Output Loading (pF)
2-44
4/91.Rev.A
:LattiOO@
!JJ
.l.J
Specifications GAL20V8B
Typical Characteristics
Semiconductor
Corporation
,
at
Volvs 101
Vohvs loh
Vohvs Ioh
4~0
/
O.7e,
:E
~
0.5
0.25
,/
/'
./
..........
L
---
-
t-.
4.25
r-
---
:E 4.00
.J:
:fZ
3.75
L
0.00
40.00
60.00
80.00
100.00
10.00
0.00
20.00
]
1.00
0.90
40.00
50.00
60.00
0.00
1.10
V
~
]
"""- ..........
1.20
""-
0.80
4.75
4.50
5.00
5.25
5.50
25
Supply Vottage (V)
10
~
J \
'"
100
125
0.90
/r'
V
o~o
25
50
75
100
Frequency (MHz)
80
r--..
/
60
70
VineY)
1.00
/
.§."
1.50 2.00 2.50 3.00 3.50
~E
,,/'
L
/
<-40
I\
1.00
1.10
/
30
0.00 0.50
4.00
·Input Clamp (Vlk)
20
"-
75
'"C
:!i!
Temperature (deg. C)
Delta Icc vs Yin (1 input)
J
11
I""
1.00
0.90
,.0
3.00
1.30
al
~
2.00
Normalized Icc vs Freq.
1.20
--
1.00
10h(mA)
Normalized Icc vs Temp
1.20
al
30.00
10h(mA)
Normalized Icc vs Vee
1.10
---
3.50
20.00
101 (mA)
11
,-
90
/
1/
/
100
4.00
-2.00
-1.50
-1.00
-0.150
0.00
Vik(V)
2-45
4/91.Rev.A
LB.tuce
[JJ
.l.J
e
Specifications GAL20V8A
Typical Characteristics
Semlronductor
CorporaUon
-
-
.,...
4.75
&.00
..
o
Normalized Tpd VS. Temperature
.,..,....
~
I
1.0
O.t
0.8
/
/
0.7
:.
f!!.
E
0
u
0
-25
25
..
75
,00
/
..5()
0
"8.
V
I ....
§
~
0.12
V
,
-.E-..
.
X.
/
I-
V
~
/
100
)V
.§.
...
.2100
50
o
/
~
~
~
/
~
/
·'00
§
·10
~
~
~
~
~
'.2
!l
./
...
~
'0
i
~
'.0
~
D.t
V
Z
200
300
-
0.7
us
'.50
~
5.00
5.50
Supply Voltage (V)
Normalized Icc YS' Temperature
ICIt vs. VOH
-
.
Ambient Te"ll8rature (OC)
·.10
§.
13
~
u
.......
"-
.!l
i
~
~
o
VCIt(V)
2-46
1.1
..E ...
.........
V
VOL (V)
/'
Nonnalized Icc YS. Vee
Output Loading Capacitance (pI)
<"
/
...
L
0"
IOLVS. VOL
200
~
V
L
125
V"
100
'oIOUIPUlI
<" .50
/
/
Il
/'
~
250
u
Delta Tpd vs. Output Loading
/
./
....
~
Ambient Temperlllure (OC)
Normalized Tpd VI. , or OUlPU11 Swhchlng
l-
., .---
8 •.•
75
50
....
...
'.2
~
2S
..00
Supply Voltage (V)
I-
1.00
0.18
4.71
'.1
.a
Ambient Temperature (OC)
/
-
u
Normalized Teo YS. Te"ll8rature
/
0 ..
'25
~
/
0.6
-50
~
"'
/
0.7
0.6
'.0
.,..,....
...
'.0
Z
...
NonnaJized Tsu VB. Temperlllure
i.!::!
iii
~
!
....
..7$
1.00
6.25
Supply Voltage (V)
1.2
V "'
/
16
...
'.3
• .3
I-
-- ----.
~
.
IJIi
Supply Voltage (V)
"&. •.•
Normalized Tco YS. Vee
Normalized Tsu va. Vee
Nonnalized Tpd vs. Vee
1~
~
"-..
---r-. - -- r---.. . . .
:---.....
OJ
......
'.7
IH
50
7'$
100
12$
Ambient Temperature (OC)
4/91.Rev.A
tattice®
a;J
,lJ
GAL 18V10
Semiconductor
Corporation
High Performance EZCMOS PLD
Generic Array Logic™
FUNCTIONAL BLOCK DIAGRAM
FEATURES
• HIGH PERFORMANCE ElCMOS- TECHNOLOGY
- 15 ns Maximum Propagation Delay
- Fmax 62.5 MHz
-10ns Maximum from Clock Input to Data OUtput
- TIL Compatible 16 mA Outputs
- UHraMOS- Advanced CMOS Technology
IICLK
=
I/OIQ
INPUT
I/O/a
• LOW POWER CMOS
- 75 mA lYplcallcc
• ACTIVE PULL-UPS ON ALL PINS
I/OIQ
INPUT
• EI CELL TECHNOLOGY
- Reconflgurable logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure (SOms)
- 20 Year Data Retention
I/OIQ
INPUT
I/OIQ
• TEN OUTPUT LOGIC MACROCELLS
- Uses Standard 22V10 Macrocells
- Maximum FlexlbllHy for Complex logic Designs
I/OIQ
INPUT
110/0
• PRELOAD AND POWER-ON RESET OF REGISTERS
-100% Functional TestabllHy
INPUT
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
IIO/Q
INPUT
I/OIQ
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I/OIQ
INPUT
DESCRIPTION
PACKAGE DIAGRAMS
The GAL18V1 0, at 15 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (1:2) floating gate technology to provide the highest performance 20 pin PLD available on the market. CMOS circuitry allows the GAL18V1 0 to consume much less power when compared to its bipolar counterparts. The E2 technology offers high
speed (50ms) erase times, providing the ability to reprogram or
reconfigure the device quickly and efficiently.
Vee
I/CLK
I
WCLX
2
By building on the popular 22V1 0 architecture, the GAL 18V1 0
allows the designer to be immediately productive, eliminating the
learning curve. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC)
to be configured by the user. The GAL18V1 0 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V1 0 devices.
Unique test circuitry and reprogram mabie cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATIICE is able to guarantee 100% field programmability and
functionality of all GAL- products. LATIICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.
DIP
PLCC
v..
IiOIQ
I/OIQ
20
IiOIQ
IIO/Q
IIO/Q
I/O/Q
GAL18V10
IiOIQ
I/O/a
Top View
IiOIQ
IIO/Q
IIO/Q
IiOIQ
110/0
IiOIQ
CIIID IIO/Q IIO/Q IiOIQ
IIO/Q
I/O/a
aND
copyright 01991 Lattice Semiconductor Corp. GAL and UnraMOS are ragiltered trademarlca of Lattice Semiconductor Corp. Generic Array Logic and E'CMOS are tr&damar"" of Lattice
Semiconductor Corp. The opecllcatlons herein are subject to change wIthou1 notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. (503) 681-01180r 1-800-FASTGAL; FAX (503) 681-3037
2-47
April 1991.Rev.A
[jJ
'L Lattire
4D
Specifications GAL 18V1 0
Semironductor
Corporation
GAL18V10 ORDERING INFORMATION
Commercial Grade Specifications
Tpd (ns)
Tsu (ns)
10
15
12
20
Teo (ns)
Icc (mA)
10
115
GAL 18V10-15LP
20-Pin Plastic DIP
115
GAL 18V10-15LJ
20-Lead PLCC
115
GAL18V10-20LP
20-Pin Plastic DIP
115
GAL18V10-20LJ
20-Lead PLCC
12
Package
Ordering #
Industrial Grade Specifications
Tpd (ns)
Tsu (ns)
Teo (ns)
Icc (mA)
20
12
12
125
GAL18V10-20LPI
20-Pin Plastic DIP
125
GAL18V10-20LJI
20-Lead PLCC
Package
Ordering #
PART NUMBER DESCRIPTION
xxxxxxxx - xx.
GAL18V10
Device Name
~
X X X
Speed (ns)
L = Low Power Power
L...-_ _ _
--~------I
2-48
L...-_ _ _ _
Grade
Blank = Commercial
I = Industrial
Package P = Plastic DIP
J = PLCC
4J91.Rev.A
'LllttiooQP
[JJ
~
Specifications GAL 18V1 0
SeIIlironductor
Corporation
OUTPUT LOGIC MACROCELL (OLMC)
The GAL 18V1 0 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access
to ten product terms (pins 14 and 15), and the other eight OLMCs
have eight product terms each. In addition to the product terms
available for logic, each OLMC has an additional product-term
dedicated to output enable control.
The GAL18V1 0 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this
dedicated product term is asserted. The Synchronous Preset sets
all registers to a logic one on the rising edge of the next clock
pulse after this product term is asserted.
The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configgured as either active high or active low.
NOTE: The AR and SP product terms will force the Q output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
AR
o
4 TO 1
Q
MUX
SP
2 TO 1 I - - - - - - - - - - - - - l
MUX
GAL18V10 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
Each of the Macrocells of the GAL 18V1 0 has two primary functional modes: registered, and combinatorial 110. The modes and
the output polarity are set by two bits (SO and S 1), which are
normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are
described below and on the the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the 0 output of that OLMC's D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high)
or inverted (active low). Output tri-state control is available as
an individual product-term for each OLMC, and can therefore
be defined by a logic equation. The D flip-flop's /0 output is fed
back into the AND array, with both the true and complement of
the feedback available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /0 output
of the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
110, as can the combinatorial pins.
COMBINATORIAL //0
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either "on" (dedicated output), "off" (dedicated input), or "productterm driven" (dynamic 110). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.
2-49
4/91.Rev.A
[JJ
~ Lattice
GP
Specifications GAL 18V1 0
Semioonductor
Corporation
REGISTERED MODE
AR
AR
o
o
Q
SP
Q
SP
ACTIVE LOW
ACTIVE HIGH
So = 0
So = 1
~=o
~=o
COMBINATORIAL MODE
ACTIVE LOW
ACTIVE HIGH
So = 0
S, 1
So = 1
S, 1
=
=
2-50
4/91.Rev.A
tl1ttiOO®
[J
.l.t
Specifications GAL 18V1 0
Semiconductor
Corporation
GAL 18V10 LOGIC DIAGRAM / JEDEC FUSE MAP
0
4
•
'2
.
,
20
24
28
32
AS'lNCHRONOUS RESET
(TO.AU. REGISTERS)
0000
0036
=
0324
0360
:§:::t
~
0648
2
~I
OlMC 19
~
19
3457
-
J
OLMC '8
!LJ
18
'----0684
~
0972
4r}J
...,
=tiP
17
5'
3
'008
=.>-'296
-OLMC '8
J
16
J
15
1
14
J
13
J
12
J
11
J
9
~LJ
0-
5'
4
'332
~
'892
0-
5
'728
~
- ""'"
-OLMC '7
....
- *~
-0l.MC ,.
so
3488
:R:
2088
5'
. .67
6
2'"
=>--
~
-OLMC 13
.,50~
2412
..88
. .69
7
2448
=-
OLMC 12
.,
:,.~
:B:
2736
347'
8
2m
jW.4C11l
J::8""
3080
liP
3473
3096
OLMC.
t:l--I
3384
~
. .75
3420
SYNCHRONOUS PRESET
(TO Al..L REGISTERS)
3476,3477 ...
·· .,
Electronic Signature
... 3538,3539
~7~8~.~'~3~2~'~O
2-51
4191.Rev.A
'Lattlce
[JJ
1..1
Specifications GAL 18V1 0
Commercial
qp
Semironductor
Corporation
RECOMMENDED OPERATING COND_
ABSOLUTE MAXIMUM RATINGS(1)
Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (Vee)
with Respect to Ground ..................... +4.75 to +5.25V
Supply voltage Vee ........................................ -0.5 to +7V
Input voltage applied ............................ -2.5 to Vee +1.0V
Off-state output voltage applied ........... -2.5 to Vee +1.0V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings' may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP"
MAX.
UNITS
-
0.8
V
Vcc+1
V
-100
~A
-
10
~A
-
0.5
V
-
V
VIL
Input Low Voltage
Vss-O.5
VIH
Input High Voltage
2.0
IlL'
Inp'Jt or 1/0 Low Leakage Current
OV S Y,N S V,L (MAX.)
IiH
Input or 1/0 High Leakage Current
3.5V :;; Y,N :;; Vee
VOL
Output Low Voltage
10L~ MAX. Yin ., V,L or V,H
-
VOH
Output High Voltage
10H= MAX. Yin = V,L or V,H
2.4
-
10L
Low Level Output Current
-
-
10H
High Level Output Current
-
los2
Output Short Circuit Current
Vee
Icc
Operating Power Supply Current
V,L= 0.5V V,H=3.0V
ftoggle =15Mhz Outputs Open
=5V
VOUT = 0.5V TA = 25·C
-
16
mA
-
-3.2
mA
-50
-
-135
mA
-
75
115
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by
tester ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 ·C
CAPACITANCE (TA
=25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM'
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vcc = 5.0V, V, = 2.0V
ClIO
110 Capacitance
10
pF
Vee = 5.0V, VIJO - 2.0V
"Guaranteed but not 100% tested.
2-52
4/91.Rev.A
tattlce~
[JJ
~ Semiconductor
Specifications GAL 1 BV1 0
Commercial
Corporation
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER
TEST
COND.'
-15
-20
MIN. MAX.
MIN. MAX.
-
DESCRIPTION
tpd
1
Input or I/O to Combinatorial Output
-
tco
1
Clock to Output Delay
10
Clock to Feedback Delay
-
Setup Time, Input or Feedback before Clocki
10
50
-
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tet)
58.8
-
Maximum Clock Frequency with
62.5
tcf2
tsu
th
1
Hold Time, Input or Feedback after Clocki
0
Maximum Clock Frequency with
15
7
-
UNITS
20
ns
12
ns
10
ns
12
-
ns
0
-
ns
41.6
-
MHz
45.4
-
MHz
-
62.5
-
MHz
-
8
-
ns
8
-
ns
20
nli
20
ns
20
ns
External Feedback, 1/(tsu +tco)
fmax 3
1
1
No Feedback
Clock Pulse Duration, High
8
twl4
-
Clock Pulse Duration, Low
8
ten
2
Input or 110 to Output Enabled
-
15
tdis
3
Input or 110 to Output Disabled
tar
1
Input or 110 to Asynchronous Reset of Register
-
20
Asynchronous Reset Pulse Duration
10
Asynchronous Reset to Clocki Recovery Time
15
Synchronous Preset to Clocki Recovery Time
10
twh4
tarr
-
tspr
-
tarw
15
-
15
15
12
-
ns
ns
ns
) Refer to Switching Test Conditions section.
) Calculated from fmax with internal feedback. Refer to fmax Description section.
) Refer to fmax Description section.
) Clock pulses of widths less than the specification may be detected as valid clock signals.
2-53
4191.Rev.A
rIJ
Lature
Specifications GAL 18V1 0
Industrial
qp
SemiaHlducwr
CorporaUOn
RECOMMENDED OPERATING CONDo
ABSOLUTE MAXIMUM RATINGS(1)
Industrial Devices:
Supply voHage V co ........................................ -0.5 to + 7V
Input voltage applied .•.....•.......•........•.•. -2.5 to Vee +1.0V
Off·state output voltage applied .........•. -2.5 to Vee + 1.0V
Storage Temperature •................•.............•.. -65 to 150°C
Ambient Temperature (TA) ..........•..•.......•...... -40 to 85°C
Supply voltage (Vee)
with Respect to Ground .................•..•. +4.50 to +5.50V
Ambient Temperature with
Power Applied ................................•......•. -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming. follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
OVer Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.'
MAX.
UNITS
-
0.8
V
VIL
Input Low Voltage
Vss-O.5
VIH
Input High Voltage
2.0
IlL'
Input or 110 Low Leakage Current
OV S Y,N S V,l (MAX.)
IIH
Input or VO High Leakage Current
3.SV S Y,N S Vee
Output Low Voltage
10l .. MAX. Yin
Output High Voltage
10H= MAX. Yin = V,l or V,H
VOL
VOH
=V,l or V,H
2.4
-
10L
Low Level Output Current
10H
High Level Output Current
1052
Output Short Circuit Current
Vee = SV
Icc
Operating Power Supply Current
V,l= O.SV V,H = 3.0V
floggle =15Mhz Outputs Open
VOUT = O.SV TA= 25°C
-50
-
-
Vcc+1
V
-100
!LA
10
!LA
0.5
V
90
-
V
16
mA
-3.2
mA
-135
mA
125
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = O.SV was selected to avoid test problems caused by
tester ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = SV and TA = 25°C
CAPACITANCE (TA = 25°C, f
= 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
C,
ClIO
TEST CONDITIONS
Input Capacitance
8
pF
Vee = S.OV. V,
I/O Capacitance
10
pF
Vee = S.OV. Vue = 2.0V
=2.0V
*Guaranteed but not 100% tested.
2-54
4191.Re~
Lattice~
!IJ
~ Corporation
Semiconductor
Specifications GAL 18V1 0
Industrial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER
TEST
COND.'
-20
DESCRIPTION
MIN. MAX.
20
ns
12
ns
Clock to Feedback Delay
-
10
ns
Setup lime, Input or Feedback before Clocki
12
ns
MHz
tpd
1
Input or I/O to Combinatorial Output
tco
1
Clock to Output Delay
tcf2
tsu
th
fmax 3
-
UNITS
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
41.6
-
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
45.4
-
MHz
1
Maximum Clock Frequency with
No Feedback
62.5
-
MHz
Hold lime, Input or Feedback alter Clocki
0
ns
twh4
-
Clock Pulse Duration, High
8
-
ns
twl4
-
Clock Pulse Duration, Low
8
-
ns
20
ns
20
ns
ten
2
Input or I/O to Output Enabled
tdis
3
Input or 110 to Output Disabled
-
tar
1
Input or 110 to Asynchronous Reset of Register
-
25
ns
Asynchronous Reset Pulse Duration
15
ns
Asynchronous Reset to Clocki Recovery Time
15
Synchronous Preset to Clocki Recovery lime
12
-
tarw
tarr
tspr
-
ns
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
2-55
4/91.Rev.A
~
.l.J CorporaUon
SemioondU~
'Latli
GD
Specifications GAL 18V1 0
SWITCHING WAVEFORMS
INPUT 01
110 FEEDBACK
COMBINATORIAL
OUTPUT
\\\\\\\
\~t'uo
INPUT or
110 FEEDBACK
INNT
t~~
ClK
'&\\~~~\'J~= :
REGISTERED
OUTPUT
Combinatorial Output
Reg Istered Output
INPUT 01
110 FEEDBACK
OUTPUT
ClK
Input or I/O to Output Enable/Disable
REGISTERED
FEEDBACK
fmax with Feedback
twl
ClK
Clock Width
INPUT 01
110 FEEDBACK
DRIVING SP
INPUT or
VOFEEDBACK
DRIVINGAR
CLK
REGISTERED
OUTPUT
REGISTERED
OUTPUT
tc0m=
\~\\\\\\\\\\\\
Synchronous Preset
ClK
Asynchronous Reset
2-56
4/91.Rev.A
Lattice~
fIJ
J,.,J SemironduGtor
Specifications GAL 18V1 0
I
Corporation
-
fmax DESCRIPTIONS
elK
elK
, _____ . ___________ .. ___________ .... -0--------.-
r
oo
lOGIC
-------------------------------
------------:
REGISTER
ARRAY
REGISTER
1oI1..1----lou---+.I.....I - - - -
.,------------------ ... ---------------.-._----_ ...
teo~
IOIII~I------tcf ----I~~I
fmax with External Feedback 1/(1su+tco)
1OIII~1------tpd-----~.1
Note: fmax with external feedback is calculated from measured tsu and tco.
fmax with Internal Feedback 1/(1su+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal
feedback (tet = 1lfmax - tsu). The value of tet
is used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combinatorial output is equal to tet + tpd.
elK
,..
···
-------------------------------- ------------,.
..
lOGIC
ARRAY
REGISTER
f--+-"-'
·---------._._-------_ ... _---_._---------.-------.
fmax With No Feedback
Note: fmax with no feedback may be
less than 1ltwh + twl. This is to allow for
a clock duty cycle of other than 50%.
SWITCHING TEST CONDITIONS
Input Pulse Levels
+5V
GNDt03.0V
Input Rise and Fall Times
3ns 10%-90%
Input Timing Reference Levels
1.5V
Output Timing Reference Levels
1.5V
Output Load
FROM OUTPUT (O/Q)
UNDER TEST
See Figure
TEST POINT
Cl
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Rl
R2
CL
300n
390n
50pF
Active High
00
390n
50pF
Active Low
300n
390n
50pF
Active High
00
390n
5pF
Active Low
300n
390n
5pF
Test Condition
1
2
3
CL INCLUDES JIG AND PROBE TOTAL CAPACITANCE
2-57
4!91.Rev.A
I,
!
Specifications GAL 18V1 0
ELECTRONIC SIGNATURE
An electronic signature (ES) is provided in every GAL 18Vl0
device. It contains 64 bits of reprogram mabie memory that can
contain user-defined data. Some uses include user 10 codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the
security cell.
SECURITY CELL
A security cell is provided in every GAL18Vl 0 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.).
To test a design for proper treatment of these conditions, a way
must be provided to break the feedback paths, and force any
desired (i.e., illegal) state into the registers. Then the machine
can be sequenced and the outputs tested for correct next state
conditions.
The GAL 18Vl 0 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus,
any present state condition can be forced for test sequencing.
If necessary, approved GAL programmers capable of execut-·
ing test vectors perform output register preload automatically.
INPUT BUFFERS
LATCH-UP PROTECTION
GAL18Vl 0 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry to latch. Additionally, outputs are designed with n-channel
pullups instead of the traditional p-channel pullups to eliminate
any possibility of seR induced latching.
DEVICE PROGRAMMING
GAL18Vl 0 devices are designed with TIL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TIL devices.
The input and 110 pins also have built-in active pull-ups. As a
result, floating inputs will float to a TIL high (logic t). However,
Lattice recommends that all unused inputs and tri-stated 110 pins
be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the
device.
GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers (see the
the GAL Development Tools section). Complete programming
of the device takes only a few seconds. Erasing of the device
is transparent to the user, and is done automatically as part of
the programming cycle.
typical Input Current
~
.:!.
;;;
~
/'
./
·20
"
./
u
...
~
·40
=
·60
...o
/'
1.0
2.0
3.0
4.0
5.0
Input Valtage (Va Its)
2-58
4191.Rev.A
LaWOOQP
[JJ
'L
Specifications GAL 18V1 0
Semiconducwr
Corporation
..,
nJ.
i
POWER-UP RESET
.
Vee
i
OV
V IH t'"TT"T"mCT""T-rTT""\Ir--------ClK
VALID ClOCK SIGNAL
VIL
INTERNAL
REGISTER
Q·OUTPUT
INTERNAL REGISTER
RESET TO LOGIC 0
ACTIVE lOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Circuitry within the GAL 18V1 0 provides a reset signal to all
registers during power-up. All internal registers will have their
outputs set low after a specified time (t IIESET ' 45I1S MAX). This
feature can greatly simplify state machine design by providing
a known state on power-up.
a
The timing diagram for power-up is shown above. Because of
the asynchronous nature of system power-up, some conditions
must be met to guarantee a valid power-up reset of the
GAL18V1 o. First, the VIX rise must be monotonic. Second, the
clock input must become a proper TTL level within the specified
time (tpR ·, 100ns MAX). The registers will reset within a maximum of tRESET time. As in normal system operation, avoid clocking
the device until all input and feedback path setup times have been
met.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN~
outPut _ _ _
Dltl
~~
V
~
I
~
PIN
Feedblck ..
AClive Pull·up
Vee
Circuh
Tri·Stata
Control
..:r.....
i Vraf i
ll l;
:
Output
Dill
(VroITypicol.UV)
:
t..... j
PIN
PIN
Feedback
(To Input BuHe~
Input
Output
2-59
4191.Rev.A
'L
'Lattice~
[lJSem/conductor
Specifications GAL 18V1 0
Typical Characteristics
Corporation
Normalized Tsu vs. Vcr;
Normalized Tpd vs. Vcr;
•.3,....---r----.----r--....,
1.3
-+-__+ __-+__-i
1.2
1.2+-_ _
). =
X'''
F
1,
iil
1.1
..
~ 0.9-1---+--+---+----l
~--+---.J.f=:-;;;PT;::L:.•;Hlr
II·····PTH .• I
I·····
H·.L
PT
PT L->H
4,75
5
4.5
4.75
...
Normalized Tpd va. Temperalure
./V
5.25
0.1
0.7
4.5
5.5
L
{!
1·
1V
V
./
0.•
0.1 V
,..
V
V
/'
25
50
75
100
t25
·55
8 ,.•
lL
] ,
10.
z
-
71
tOO
125
......
.",--
V
-55
.zs
0
.V
.....
10'
/'
~
...
1 •
l
o 0.'
Z
/
100
1.2
200
300
-
·'50 ...-_ _-.-_'O_H_VS.-.V_O_H_-r_ _....,
~~
~
125
.US
4.5
5
525
5.5
Normalized Icc va. Tempereture
'.3
"-.
1
2-60
IL:
Supply VoRage (V)
·'00 i""~-+--+---+---;
•
VOH(V)
~
0.7
.....".........I.~
....
~
~
..
~
_"..T........
............
~+---~-~~---+---i
VOL (V)
100
0 ..
!
2
75
Normalized Ia: VI. Va:
OUlpui Loalng Capacitance (pf)
--
so
25
Ambient Temperature (OC)
'.3
./
200
/
V
10
DeRa Tpd vs. Output Lolding
.0
IOLVS. VOL
!.
oJ
25
/
/I 01 OIAputs
<.50
0
Ambient Temperalure (OC)
V
.......
...
v
V
......
V-
L
I
k--'"
V"
L
o.'7
-25
Della Tpd VI. II 01 Outputs Swilching
/
-'"
Normalized Teo vs. Temperature
0.1 V
Ambient Temperature (OC)
~
5.5
5.25
I-
0.7
0
5
'.2
0.1
.25
4.75
Supply VoI1age (V)
Normalized Tou VI. Temperalure
::::I 1.1
V
50
5
1
•
~ 0.'
Sl4JPly Voltage (V)
./
.2'"
,!!!
0.7L---l...--JL==4==::..J
5.25
'.2
.,
i
L
Supply Vollage (V)
0.7
-50
81.1
l-
O••
0.7
./
........ ......
..........
~
...
,..
-
:.r:---+----+---+---;
•••••••••
- - -- r
I-
) ,
b-
Normalized Teo VI. Voc
~
-
....
.....
0.7
.u
.zs
0
IS
10
71
100
U!&
Ambient Temperature (OC)
4J91.Rev.A
fIJ
J.."
Lattice
GAL22V10B
GAL22V10
®
Semiconductor
Corporation
High Performance E2CMOS PLD
FUNCTIONAL BLOCK DIAGRAM
FEATURES
• HIGH PERFORMANCE E2CMOS·TECHNOLOGY
- 10 ns Maximum Propagation Delay
- Fmax =105 MHz
- 7 ns Maximum from Clock Input to Data Output
- TTL Compatible 16 mA Outputs
- UHraMOS· Advanced CMOS Technology
IICLK
~
I
I'
1I0IO
INPUT
11010
INPUT
• ACTIVE PULL·UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
- Fully Function/Fuse·Map/Parametrlc Compatible
with Bipolar and UVCMOS 22V10 Devices
• 50% REDUCTION IN POWER VERSUS BIPOLAR
• E2 CELL TECHNOLOGY
- Reconflgurable Logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention
INPUT
1I0I0
INPUT
1/010
INPUT
1/010
INPUT
1/010
INPUT
11010
• TEN OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
INPUT
• PRELOAD AND POWER·ON RESET OF REGISTERS
- 100% Functional Testability
11010
INPUT
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
1/010
INPUT
1/010
INPUT
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
The GAL22V1 OB, at 10ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 22V10 device on the market. CMOS circuitry allows the GAL22V1 0 to consume much less power when
compared to bipolar 22Vl 0 devices. E2 technology offers high
speed «lOOms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user; The GAL22V1 0 is fully function"use map/parametric
compatible with standard bipolar and CMOS 22Vl0 devices.
Unique test circuitry and reprogram mabie cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL· products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.
PACKAGE DIAGRAMS
DIP
PLCC
Vcc
~
!!
Me
!d~
..
IIO/Q
0
~
IIO/Q
IIOIQ
GAL22V10/B
Top View
IIO/Q
IIOIQ
IIO/Q
Me
IIOIQ
~ ~
IIO/Q
IIOIQ
IIOIQ
K !1
IIO/Q
IIOIQ
IIO/Q
IIO/Q
IIO/Q
IIO/Q
Copyright CI991 Lattice Semiconductor Corp. GAL. E'CMOS and UhraMOS are registered trademarks of Lattice Semicor1ductor Corp. Generic Array logic Is a trademark of Lattice Seniconduc·
tor Corp. The apecllcationa herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. (503) 681'()118 or 1-800-FASTGAL; FAX (503) 681-3037
2·61
April 1991.Rev.A
tatticeGl
fJJ
1..J
Specifications GAL22V10B
GAL22V10
Semiconductor
Corporation
GAL22V10/B ORDERING INFORMATION
Commercial Grade Specifications
Ordering #
Tpd (ns)
Tsu (ns)
Teo (ns)
Icc (rnA)
10
7
7
130
GAL22V1 OB-1 OLP
24-Pin Plastic DIP
130
GAL22V10B-10W
28-Lead PLCC
130
GAL22Vl0B-15LP
24-Pin Plastic DIP
130
GAL22V10B-15W
28-Lead PLCC
130
GAL22V10-15LP
24-Pin Plastic DIP
130
GAL22V10-15W
28-Lead PLCC
130
GAL22V10-25LP
24-Pin Plastic DIP
130
GAL22V10-25W
28-Lead PLCC
15
8
10
15
8
12
25
15
15
Package
Industrial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (rnA)
15
10
8
150
GAL22V10B-15LPI
24-Pin Plastic DIP
150
GAL22V10B-15LJI
28-Lead PLCC
20
14
10
150
GAL22V10-20LPI
24-Pin Plastic DIP
150
GAL22V10-20LJI
28-Lead PLCC
150
GAL22V10-25LPI
24-Pin Plastic DIP
150
GAL22Vl0-25LJI
28-Lead PLCC
25
15
15
Ordering #
Package
PART NUMBER DESCRIPTION
xxxxxxxx - xx
GAL22V10
GAL22V10B
Device Name
~
X XX
-
' - - - - - - Grade
Speed (ns)
L = Low Power Power _ _ _ _ _ _ _ _---1
Blank = Commercial
I = Industrial
1...------ Package
P = Plastic DIP
= PLCC
J
2-62
4191.Rev.A
LatticeGD
[JJ
1.J
Specifications GAL22V10B
GAL22V10
Semiconducwr
Corporation
OUTPUT lOGIC MACROCEll (OlMC)
The GAL22V10 has a variable number of product terms per
OLMC. Of the ten available OLMes, two OLMCs have access to
eight product terms (pins 14 and 23), two have ten product terms
(pins 15 and 22), two have twelve product terms (pins 16 and 21),
two have fourteen product terms (pins 17 and 20), and two
OLMCs have sixteen product terms (pins 18 and 19). In addition
to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control.
The GAl22V1 0 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two
product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated
product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after
this product term is asserted.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either
active high or active low.
NOTE: The AR and SP product terms will force the a output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
AR
o
4 TO t
a
MUX
SP
2 TO t ( -_ _ _ _ _ _ _ _ _ _....1
MUX
GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT lOGIC MACROCEll CONFIGURATIONS
NOTE: In registered mode, the feedback is from the 10 output of
the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
110, as can the combinatorial pins.
Each of the Macrocells of the GAl22V10 has two primary
functional modes: registered, and combinatorialI/O. The modes
and the output polarity are set by two bits (SO and S1), which are
normally controlled by the logic compiler. Each of these two
primary modes, and the bit settings required to enable them, are
described below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the a output of that OLMC's Ootype flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control Is available as an
individual product-term for each OLMC, and can therefore be
defined by a logic equation. The 0 flip-flop's /Q output is fed back
into the AND array, with both the true and complement of the
feedback available as inputs to the AND array.
2-63
COMBINATORIAL 110
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either "on" (dedicated output), "off" (dedicated input), or "productterm driven" (dynamic I/O). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.
4191.Rev.A
U
..l..J lLatlioo°
Specifications GAL22V10S
GAL22V10
SemiconducUJr
Corporation
REGISTERED MODE
AR
o
AR
o
Q
Q
o
SP
SP
ACTIVE LOW
ACTIVE HIGH
5.=0
5,
5 0 =1
=0
5,
=0
COMBINATORIAL MODE
ACTIVE LOW
ACTIVE HIGH
50 = 0
50
5, = 1
=1
5, = 1
2-64
4/91.Rev.A
Lattice~
fJJ
~ Semiconductor
Corporation
Specifications GAL22V10B
GAL22V10
GAL22V10 LOGIC DIAGRAM / JEDEC FUSE MAP
DIP (PLCC) Package Pinouts
1 (2)
::
....
ASYNCHRONOUS RESET
ITO ALL AEQlSTERS)
~
!WI'
~
....
2 (3)
0124
~
1
23 (27)
~l
22 (26)
1
21 (25)
1
20(24)
J
19(23)
~
.."
~
~
...
~
..II
51
OIlS
1";
3 (4)
'-1416
ra:;o;o
..,.
:'LJ
~
51
2";!
4 (5)
5(6)
J-=
.
"
LJ
'--
~
:"U
51
58'7.~
1-~
~
:..'"' U1
18 (21)
51
6(7)
7 (9)
"'"
,,
.
~
~
"'.
8(10)
-
fi
5."
J
17 (20)
1
16 (19)
J
15(18)
1
14 (17)
U
a;c;;
so,
...
81
IIII
1111
...3
1111
lit
-
LJ
~
5'"
9 (11)
S1
-
43"
....
......,
i=1
~
....
-t!U
~
=I'B
".;
10(12)
11 (13)
~
."
~-
13(16)
2-65
4/91.Rev.A
jllLattJoo"
.l...I
Specifications GAL22V10B
Commercial
Semi(X)lJductor
Corporation
ABSOLUTE MAXIMUM RATINGS(l)
RECOMMENDED OPERATING CONDo
Commercial Devices:
Supply voltage Vee ........................................ -0.5 to +7V
Ambient Temperature (TA ) ••••.••••••••••••••••.••••••• 0 to +75°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.75 to +5.25V
Input voltage applied ............................ -2.5 to Vee + 1.0V
Off-state output voltage applied ........... -2.5 to Vee + 1.0V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stres:: only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming. follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.'
MAX.
UNITS
VIL
Input Low Voltage
Vss -0.5
-
0.8
V
VIH
Input High Voltage
2.0
Vcc+l
V
-100
J.lA
10
J.lA
0.5
V
-
V
Input or 1/0 Low Leakage Current
OV:s; V,N:S; V,L (MAX.)
-
Input or 110 High Leakage Current
3.5V:s; Y,N :s; Vcc
-
VOL
Output Low Voltage
10L = MAX. Yin = V,L or V,H
-
-
VOH
Output High Voltage
10H = MAX. Yin = V,L or V,H
2.4
-
-
-
16
mA
-
-3.2
mA
-30
-
-130
mA
130
mA
IlL'
I
IIH
Low Level Output Current
10L
10H
High Level Output Current
los2
Output Short Circuit Current
ICC
Operating Power Supply Current
Vcc = 5V
VOUT = 0.5V
VIL = 0.5V
TA = 25°C
-
VIH =3.0V
floggle = 25Mhz
90
Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 ·C
CAPACITANCE (TA
=25°C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vee = 5.0V. V, = 2.0V
ClIO
110 Capacitance
8
pF
Vee = 5.0V. V,/o = 2.0V
"Guaranteed but not 100% tested.
2-66
4/91.Rev.A
[JJ
1.J
LattiOO-
Specifications GAL22V1 DB
Commercial
Semironducwr
CorporaUon
AC SWITCHING CHARACTERISTICS
OVer Recommended Operating Conditions
TEST
PARAMETER
COND.'
-10
-15
MIN. MAX.
MIN. MAX.
DESCRIPTION
UNITS
tpd
1
Input or 110 to Combinatorial Output
3
10
3
15
ns
teo
1
Clock to Output Delay
2
7
2
8
ns
tcf2
-
Clock to Feedback Delay
-
2.5
-
2.5
ns
10
-
ns
tsu
tsu.
th
fmax 3
Setup Time, Input or Feedback before Clocki
7
Setup Time, SP before Clocki
10
Hold Time, Input or Feedback after Clocki
0
-
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + teo)
71.4
-
55.5
-
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
105
-
80
-
MHz
1
Maximum Clock Frequency with
No Feedback
105
-
83.3
-
MHz
ns
10
0
ns
ns
MHz
Clock Pulse Duration: High
4
-
6
twt'
-
Clock Pulse Duration, Low
4
-
6
-
ten
2
Input or VO to Output Enabled
3
10
3
15
ns
tdis
3
Input or VO to Output Disabled
3
9
3
15
ns
tar
1
Input or I/O to Asynchronous Reset of Register
3
13
3
20
ns
twh4
ns
tarw
-
Asynchronous Reset Pulse Duration
8
-
15
-
ns
tarr
-
Asynchronous Reset to Clocki Reeovery Time
8
10
-
ns
tspr
-
Synchronous Preset to Clocki Recovery Time
10
-
10
-
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
2-67
4/91.Rev.A
I
I
~
/lJ
.l..J Lattice·
Specifications GAL22V10
Commercial
SemiconducWi'
Corporation
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDo
Commercial Devices:
Supply voltage Vee ........................................ -0.5 to +7V
Input voltage applied ............................ -2.5 to Vee + 1.0V
Off-state output voltage applied ........... -2.5 to Vee + 1.0V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
Ambient Temperature (TA) ••••••••••••••••••••••••••••• 0 to +75°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.75 to +5.25V
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
CONDITION
PARAMETER
MIN.
TYP..
MAX.
UNITS
-
0.8
V
2.0
-
VcC+1
V
-
-150
~A
10
~A
0.5
V
-
V
16
mA
-
-3.2
mA
-so
-
-135
mA
-
90
130
mA
VIL
Input Low Voltage
VIH
Input High Voltage
IlL'
Input or 110 Low Leakage Current
OV:;; VIN :;; Vil (MAX.)
IiH
Input or 110 High Leakage Current
3.5V:;; VIN :;; Vcc
VOL
Output Low Voltage
10l= MAX. Yin = Vil or VIH
-
VOH
Output High Voltage
10H = MAX. Yin = Vilor VIH
2.4
IOL
Low Level Output Current
10H
High Level Output Current
los2
Output Short Circuit Current
ICC
Operating Power Supply Current
Vss - 0.5
Vcc = SV
VOUT = O.SV TA = 25°C
VIL = 0.5V
VIH =3.0V
ftoggle = 15Mhz
Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = O.SV was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25°C
CAPACITANCE (TA
=25 C, f =1.0 MHz)
SYMBOL
PARAMETER
C,
ClIO
TEST CONDITIONS
MAXIMUM"
UNITS
Input Capacitance
8
pF
Vcc = 5.0V. V, = 2.0V
110 Capacitance
10
pF
Vee = 5.0V, VI10 = 2.0V
·Guaranteed but not 100% tested.
2-68
4/91.Rev.A
:LatticeGl
[JJ
.I..J
Specifications GAL22V10
Commercial
Semioonductor
Corporation
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER
TEST
COND.'
·15
·25
MIN. MAX.
MIN. MAX.
DESCRIPTION
UNITS
tpd
1
Input or 110 to Combinatorial Output
3
15
3
25
ns
tco
1
Clock to Output Delay
2
8
2
15
ns
tcf2
-
Clock to Feedback Delay
-
5
-
13
ns
Setup Time, Input or Feedback before Clocki
12
15
-
ns
tsu
th
fmax 3
-
Hold Time, Input or Feedback after Clocki
0
-
0
-
ns
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
50
-
33.3
-
MHz
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
58.8
-
35.7
-
MHz
1
Maximum Clock Frequency with
No Feedback
62.5
-
38.5
-
MHz
twh'
-
Clock Pulse Duration, High
8
-
13
twl'
-
Clock Pulse Duration, Low
8
-
13
-
ten
2
Input or 110 to Output Enabled
3
15
3
25
tdis
3
Input or 110 to Output Disabled
3
15
3
25
ns
tar
1
Input or 110 to Asynchronous Reset of Register
3
20
3
25
ns
tarw
-
Asynchronous Reset Pulse Duration
15
25
-
ns
Asynchronous Reset to Clocki Recovery Time
15
Synchronous Preset to Clocki Recovery Time
12
-
tarr
tspr
25
15
-
ns
ns
ns
ns
ns
1).Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
2·69
4191.Rev.A
fM
~ Lattioo
Specifications GAL22V10B
Industrial
e
'Semiconductor
Corporation
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDo
Industrial Devices:
Ambient Temperature (TA) ............•...•.....•..•.. -40 to 85°C
Supply voltage (Vee)
with Respect to Ground •...............•..... +4.50 to +5.50V
Supply voltage Vee ........................................ -0.5 to +7V
Input voltage applied ....•.•....•••.••.••...•..•. -2.5 to Vee + 1.0V
Off-state output voltage applied ..•......•• -2.5 to Vee + 1.0V
Sto rage Temperature ...........••.•....•.••........... -65 to 150°C
Ambient Temperature with
Power Applied ..•.............•....•.•...•.•........... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specificatiol'1s).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.s
MAX.
UNITS
VIL
Input Low Voltage
Vss-O.5
-
0.8
V
VIH
Input High Voltage
2.0
VCC+1
V
IlL'
Input or 1/0 Low Leakage Current
OV::s; VIN::S; VIL (MAX.;
-100
IlA
IIH
Input or 110 High Leakage Current
3.5V::s; VIN : s; Vee
IlA
VOL
Output Low Voltage
-
10
10L .. MAX. Vin .. VIL or VIH
-
-
0.5
V
VOH
Output High Voltage
100 .. MAX. Vin = VIL or VIH
2.4
-
-
V
16
mA
-3.2
mA
-30
-
-130
mA
-
90
150
mA
lOll
Low Level Output Current
-
10H
High Level Output Current
-
los2
Output Short Circuit Current
Vee- SV VOUT = 0.5V
ICC
Operating Power Supply Current
VIL=0.5V VIH =3.0V
ftoggle = 25Mhz Outputs Open
TA = 25°C
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout =O.SV was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee .. 5V and TA .. 25°C
CAPACITANCE (TA
.
=25 C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM'
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vee = 5.0V, V, = 2.0V
ClIO
110 Capacitance
8
pF
Vcc = 5.0V, V'IO = 2.0V
Guaranteed but not 100% tested.
2-70
4191.Rev.A
'Lattice~
[Q
l..J Semloonductor
Specifications GAL22V10B
Industrial
Corporation
AC SWITCHING CHARACTERISTICS
OVer Recommended Operating Conditions
-15
PARAMETER
TEST
COND.'
tpd
1
Input or I/O to Combinatorial Output
3
15
ns
1
Clock to Output Delay
2
8
ns
Clock to Feedback Delay
-
5
ns
Setup lime, Input or Feedback before Clocki
10
Setup lime, SP before Clocki
12
tco
tcf2
tsu
tsu.
th
fmax 3
-
DESCRIPnON
MIN. MAX.
UNITS
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + teo)
55.5
-
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tel)
66.6
-
MHz
1
Maximum Clock Frequency with
No Feedback
66.6
-
MHz
ns
Hold lime, Input or Feedback after Clocki
0
ns
ns
ns
MHz
twh4
-
Clock Pulse Duration, High
6
twt'
-
Clock Pulse Duration, Low
6
-
ten
2
Input or 110 to Output Enabled
3
15
ns
tdis
3
Input or I/O to Output Disabled
3
15
ns
ns
Input or 1/0 to Asynchronous Reset of Register
3
20
ns
-
Asynchronous Reset Pulse Duration
15
-
ns
tarr
-
Asynchronous Reset to Clocki Recovery lime
10
-
ns
tspr
-
Synchronous Preset to Clocki Recovery lime
12
-
ns
tar
1
tarw
1) Refer to SWitching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
2-71
4191.Rev.A
i
I
'Lattioo*
[JJ
.J"J
Specifications GAL22V10
Industrial
Semiconducwr
CorporaUolJ
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDo
Industrial Devices:
Ambient Temperature (TA ) •••••••••••••••••••••••••••• -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.50 to +5.50V
Supply voltage Vee ........................................ -0.5 to +7V
Input voltage applied ......................... '" -2.5 to Vee +1.0V
Off-state output voltage applied ........... ·2.5 to Vee + 1.0V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
VIL
Input Low Voltage
Vss-O.S
VIH
Input High Voltage
2.0
tiL'
Input or 110 Low Leakage Current
OV S Y,N S V,L (MAX.)
TYP.'
-
Input or 110 High Leakage Current
3.5V s Y,N S Vee
VOL
Output Low Voltage
10L= MAX. Yin = V,L or V,H
-
VOH
Output High Voltage
IOH = MAX. Vin = V,L or V,H
2.4
-
ilH
-
tOL
Low Level Output Current
-
-
tOH
High Level Output Current
-
los2
Output Short Circuit Current
Vee=5V
-
ICC
Operating Power Supply Current
VIL=0.5V
90
VOUT
=0.5V
TA =25°C
-50
-
VIH =3.0V
MAX.
UNITS
0.8
V
VCC+1
V
-150
itA
10
itA
0.5
V
-
V
16
mA
-3.2
mA
-135
mA
150
mA
ftoggle = 15Mhz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) 'One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee = 5V and TA = 25 ·C
CAPACITANCE (TA
=25°C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vee - 5.0V, V, - 2.0V
Coo
1/0 Capacitance
10
pF
Vee = 5.0V, VIIO = 2.0V
'Guaranteed but not 100% tested.
2-72
4/91.Rev.A
'Lattice~
!IJ
l.J Corporation
SemiconducUJl'
Specifications GAL22V10
Industrial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER
tpd
tco
TEST
COND.'
-25
MIN. MAX.
-
1
Input or 110 to Combinatorial Output
1
Clock to Output Delay
-
14
tcf2
-
Clock to Feedback Delay
tsu
-
Setup lime, Input or Feedback before Clocki
th
-
Hold lime, Input or Feedback after Clocki
fmax 3
-20
MIN. MAX.
DESCRIPTION
10
8
-
25
ns
15
ns
13
ns
33.3
-
MHz
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
41.6
-
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tet)
45.4
-
35.7
-
MHz
1
Maximum Clock Frequency with
No Feedback
50
-
38.5
-
MHz
Clock Pulse Duration, High
10
10
-
13
Clock Pulse Duration, Low
20
25
-
0
twl"
-
ten
2
Input or 110 to Output Enabled
tdis
3
Inpu1 or 1/0 to Output Disabled
tar
1
Input or 1/0 to Asynchronous Reset of Register
-
twh"
20
UNITS
20
15
0
13
ns
ns
-
ns
ns
25
ns
25
ns
25
ns
tarw
-
Asynchronous Reset Pulse Duration
20
-
25
-
ns
tarr
-
Asynchronous Reset to Clocki Recovery lime
20
-
25
-
ns
tspr
-
Synchronous Preset to Clocki Recovery lime
14
-
15
-
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
2-73
4191.Rev.A
'Latlice
[jJ
1..;
~
Specifications GAL22V10B
GAL22V10
SemiconductJJr
Corporation
SWITCHING WAVEFORMS
INPUT Dr
VO FEEDBACK
COMBINATORIAL
OUTPUT
INPUT Dr
VOFEEDBACK
\\\\\\\\\{AW",,"
t.~
ClK
\~\i\~\\'J\\';= :
REGISTERED
OUTPUT
Combinatorial Output
Registered Output
INPUT Dr
VOFEEDBACK
OUTPUT
ClK
Input or 1/0 to Output Enable/Disable
REGISTERED
FEEDBACK
fmax with Feedback
twl
ClK
Clock Width
INPUT Dr
VOFEEDBACK
DRIVINGAR
INPUT or
VO FEEDBACK
DRIVING SP
ClK
REGISTERED
OUTPUT
REGISTERED
OUTPUT
tc~
\\\\\\\\\\\\\\
ClK
Synchronous Preset
Asynchronous Reset
2-74
4191.Rev.A
i
'Lattice
[JJ
.l.J
!
Specifications GAL22V10S
GAL22V10
e
Semironductor
Corporation
fmax DESCRIPTIONS
,._----------_ ..... _-
elK
ClK
--_ ... _-------
lOGIC
._._--.. ----
REGISTER
ARRAY
""I
..I----Isu ---1.~I!4~c----
tco~
I--f6=
~
I
~
PIN
Feedback ..
Adive Pull·up
Circuit
Vee
~
f
(Yror Typica' .3.2V)
PIN
T ri·State
Control
.. .Y. ....
Vee
~
vrel!
(Vref Typicat. 3.2V)
Output
PIN
Data
Feedback
(To Input Buffer)
Input
Output
2-77
4/91.Rev.A
I
!
~
tatUOOGl
[JJ
.l.J
Specifications GAL22V1 DB
Typical Characteristics
SemicondUCUJr
CorporatiOn
Normalized Tpd vs Vee
•., r--'---r-;::::==~
1.2r-T-I-;:::=I:=~
~
1.1
--
".
]'
I····· PTH·.L
......
1.1
".
I
". " .
ROlE
FALLJ
j
".
".
•.•
__I__--I----+----l
1.3
1.1
.-=:-'.
:-'.
'"
4.75
".50
....
5.00
Supply Voliage (V)
Supply Voliage (V)
Normalized Tpd vs Temp
Normalized Teo vs Temp
Normalized Tsu vs Temp
1.3
PTH·.L [H---+--..-l
11IL==~PT::L'~'H~'Irt-:::;:;:::t·
...··..;......-"'·1
~
•••••
'.2
~
1.1
~1
~~
~ •.• ,....-::;:~--+--+---I
~
•.• +---1---+---+---1
.. .. ...
•.7 - I - - - I - - - - 4 - - - I - - - - l
...
u.
5.00
l--PTL.•H
Supply Voliage (V)
rr==::r:::::::;;T-i-i
,g.
'.711
r---k·
I····· PTH"~~
...
~---I----I----I----I
u.
u.
5.00
.
...
l'...
".
•.•
4.75
.!!
] 'f=~~'-"~~~~~~
'" '"
•.• +---If---+--+---I
~-
'.2
1
•.• +---If---+---+----I
1.'
....
"&.
I·····
PTL->H
'"
u.
il
I
Normalized Tsu VI Vee
Normalized Teo vs Vee
..•
...
•.7
~""':~:I
~
..--
/,./"
.1 .•
~
~E
__
g
~.
~ .. '
o
~
!1·····Rlse}
II--FALL
.:."
+---If---o:::.of""'---+---l
_~
1
.. . ...
.•.
,/
"..-
II'"'' Rise}
II--FALL
.,
2
3
..
. ,.
a
5
Number of Outpuls Swhching
Defta Teo vs Output Loading
./
--FALL
,. t····~sel
./
./
V.
V
.
V
V
..
/.
·2
150
./
LV
--FALL,
..
/-"
100
~.
.~
12
..... Rise
50
Temperalure (deg. C)
.g
c!: .1.'
Delta Tpd vs Output Loading
:/
H
•.7 -1---11----4---1----1
~
., k-:' .' --::
• 1.
4
PTL.• ,H---.t-~
••'-7-"'-1
•.• +---If---+---+---I
_-0.5
.'
......- ~
3
.,
1.1
,.,---
Number of Oulpuls Swhching
"
il
Delta Teo vs # of Outputs
Switching
·2
1.
1.2
Temperalure (deg. C)
_.0.5
.g
c!:
.!!
:li! •.• +--,:,;:;:r---t--i--l
.. '
Delta Tpd vs # of Outpuis
Switching
.,
_ ....... PTH-:..L
1.3
. . ,..
...
TemperBlure (deg. C)
g
..2'"
rr==:r:::::::;;T-i-,
I
.,:;..
1.4
200
250
300
Outpul Loading (pF)
:/
L'
50
100
150
200
2SO
300
Output Loading (pF)
2-78
4191.Rev.A
flJ'Lattioo·
i
Specifications GAL22V10B
Typical Characteristics
.J..J Corporation
Semiconductor
Voh vs Ioh
Vol VB 101
v
• .5
I ' r--.....
V
....
....
.........
//
...
V
V ......
0,00
20.00
40.00
10.00
10.00
100.00
0.00
10.00
10.00
r----.
40.00
50.00
10.00
1.10
l!
/
il
./
0.10
1.10
/
il
~ 1.00
i
5.00
0.10
5.25
,.50
'" ""-
... ...
25
J
1.00
1.50 2.00
Vin(V)
125
u.
..
50
'00
Frequency (MHz)
/
!l!! eo
2.50 3.00 3.50 ··4.00
"
100
0.'0
/
~
, r-
1$
/v
/
'1"50
.....
........
/
V
/
30
/
4.00
f"'""
••
20
\
1.00
Input Clamp (Vlk)
Delta Ice vs Vin (1 Input)
\
2.00
Normalized Icc vs Freq.
./
Temperature (deg. C)
Supply Voltage (V)
2
1.00
--
~
.........
u.
0.50
:--
....
l!
./
4.75
0.00
Normalized Ice vs Tamp
0.10
4.50
......
loh(mA)
u.
] '.0.
\
loh(mA)
1.20
0.00
30.00
/
70
eo
..
to
,
L
-2.00
/
-1.50
-1.DO
-0.50
0.00
Vik(V)
2-79
~
I
....
Normalized Icc vs Vee
~
r--
I-'
101 (mA)
.9
Vohvsloh
I
4191.Rev.A
Latticedl
~
.l.J Corporation
SemiconducUJr
Specifications GAL22V10
Typical Characteristics
Normalized Tsu vs. Vee
Normalized Tpd vs Vee
13
12
1.2
"&. 1.1
~~
I-
],
E
l5 0.'
z
-I·····
0.8
..
0.7
04.75
fE"
- r---
15
,
PT H·,L
PT l·)oH
'fa
r
§
0
Z
1.1
-
-
..........
r-0.9
.........
--
I.....
PT t·,
4.5
4.75
5
5.25
1.2
V
./
./
~
,..,~
V
V
V
V
.. /
1.2
8
>-
100
125
Delta Tpd
-
v
-25
2
V
IOL VS. VOL
-'
.Q1oo
/
V
V
vs. Output
100
V
125
·55
75
:/
Normalized Icc YS. Vee
1.3
/
12
.ll
1.1
"0
.~
1
~o
0.9
~
~
Z
~
·100
~
L
0 .•
7
200
300
4.5
".75
.po.~-__ir_---t---f----;
1
5
5.5
525
Supply Voltage (V)
Normalized Icc vs. Temperature
.ISO . -_ _ _,--_IO_H_V_S , _V_O_H_--,,--_ _-,
T
--
125
100
Ambient Temperature (OC)
Loading
/
·25
tOe)
Output Loading Capacitance (pf)
250
.s
75
L
100
#of Outputs
".--
50
,/'
Max.' 4
:;(150
25
....
.s
....'!!
200
o
Delta Tpd
10
·2
. /V
j o.•
o. .V
~
"8.'
Max.·8
. /~
I
~
Ambient Temperature
~
I-'
o. 7
·55
vs.# of Outputs Switching
V
.-" V
,/
I. I
]
O. 7
0255075
Normalized Teo va. Temperature
1.3
./
Ambient Temperature (oG)
50
0.7'":-_ __:':::---"':---_:':::---:<
4.5
4.75
5
5.2S
5.5
Supply Voltage (V)
,/
•
o. 7
·25
0.9t_--_+---t_--_+--_;
O~t_--_+---t_--_+--_;
5.5
V"
I
~(; o.
z
o.
.V
.5O
./
1. I
~
./
~ 0.9
lI
NormaJized Tsu vs. Temperature
1.3
~ ,
I
~
Supply Voltage (V)
Normalized Tpd vs. Temperature
"8.1. I
H
PTH·, L
,,;---+---t---t----;
~ P=9---t----;;:;f;=:;;::;;J
O.7L--L_-t=:::r=:=J
Supply Voltage (V)
I-
~
....... ..........
0.8 t----t----H
,.,
5%1
t2t_--_+---t_--_+--_;
]
1.3
o.
Normalized
vs._
Va;
1.3,_ _- .
_ _ _.Teo
-_
- ._ _- - ,
1.3
o
IceVS.T ..........
."',
j-
U
-P'..,-.-t---+-..; .....
1.1
p-.c:t-""<:-t---+---i--t--+---t
.l.!
lab n. TM!peI"ature
•••••~~.
l
,··,
~ t--+-~~,,-r-+~~
~
·50
t----t--.-:~;!---_t----l
t. t--+--t--t--1r-..:.i-"':.!'.F.?''t---t
....
.....
O't----j----t---t--__ir_--t---f---,
,
VOL (V)
VOH (V)
2-80
0.7
+-_+-_-+_-+_......__1-_+-_-1
·5$
.2$
0
2S
50
7&
100
\25
Ambient Temperature (OC)
4/91.Rev.A
[JJLatUce®
~
GAL26CV12
Semiconductor
High Performance E2CMOS PLD
Generic Array Logic™
Corporation
FUNCTIONAL BLOCK DIAGRAM
FEATURES
"'-"
• HIGH PERFORMANCE ElCMOS· TECHNOLOGY
-15 ns Maximum Propagation Delay
- Fmax = 62.5 MHz
-10ns Maximum from Clock Input to Data Output
- TTL Compatible 8 mA Outputs
- UltraMOS· Advanced CMOS Technology
INPUT
.,.,
IFUT
.,.,
IFUT
.,.,
• ACTIVE PULL-UPS ON ALL PINS
N'UT
• LOW POWER CMOS
- 90 mA Typlcellcc
.,.,
N'UT
• E2 CELL TECHNOLOGY
- Reconflgurable logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure (50ms)
- 20 Year Data Retention
.,.,
N'UT
IIQQ
IFUT
.,.,
• TWELVE OUTPUT LOGIC MACROCELLS
- Uses Standard 22V10 Macrocells
- Maximum Flexibility for Complex Logic Designs
IFUT
.,.,
INPUT
• PRELOAD AND POWER-ON RESET OF REGISTERS
-100% Functional Testability
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
INPUT
"'"
....T
"'"
IIQQ
INPUT
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
"'"
INPUT
DESCRIPTION
The GAL26CV12, at 15 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E2) floating gate technology to provide the highest performance 28 pin PlD available on the market. E2 technology of·
fers high speed (50ms) erase times, providing the ability to repro·
gram or reconfigure the device quickly and efficiently.
By building on the popular 22V1 0 architecture, the GAL26CV12
allows the designer to be immediately productive, eliminating the
learning curve. The generic architecture provides maximum de·
sign flexibility by allowing the Output logic Macrocell (OlMC)
to be configured by the user. The GAl26CV12 OlMC is fully
compatible with the OlMC in standard bipolar and CMOS 22V1 0
devices.
Unique test circuitry and reprogram mabie cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL· products. LATTICE also guarantees 100
erase/rewrite cycles and data retention in excess of 20 years.
PACKAGE DIAGRAMS
DIP
PLCC
1/0/0
:s
Q Q
1/0/0
---g-gg
/
2
1/0/0
28
1/0/0
1/0/0
vcc
GAL26CV12
Top View
1/0/0
1/0/0
1/0/0
vo/O
vOla
Vee
GND
vo/O
vo/O
GNO
1/0/0
1/0/0
1/0/0
---QQQQ
vOla
gggg
1/0/0
" -_ _----T" 1/0/0
copyright C1991 Lattice Semlccnductor CCIp. GAL and UkraMOS are registered trademarks of lattice Semicondudor Corp. Generic Array Logic and E'CMOS are trademarks of lattice
SemlcondUdor Corp. The opecWlcatlons herein are subJOd to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. (503) 681-0118or 1-800-FASTGAL; FAX (503) 681-3037
2-81
April 1991.Rev.A
Ii
tatlioo"'
fIJ
.1J
Specifications GAL26CV12
SemiamqucWr
Corporation
GAL26CV12 ORDERING INFORMATION
Commercial Grade Specifications
Ordering #
Tpd (n5)
T5U (n5)
Tco (n5)
Icc (mA)
15
10
10
130
GAL26CV12-15LP
28-Pin Plastic DIP
Package
130
GAL26CV12-15LJ
28-Lead PLCC
20
12
12
130
GAL26CV12-20LP
28-Pin Plastic DIP
130
GAL26CV12-20LJ
28-Lead PLCC
Industrial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
20
12
12
150
GAL26CV 12-20LPI
28-Pin Plastic DIP
150
GAL26CV12-20lJI
28-lead PlCC
Ordering #
Package
PART NUMBER DESCRIPTION
xxxxxxxx - xx
GAL26CV12 Device Name
~
' - - - - - Grade
Speed (n5)
L = Low Power Power
Blank = Commercial
I = Industrial
' - - - - - - Package
P = Plastic DIP
= PLCC
J
2-82
4/91.Rev.A
Specifications GAL26CV12
OUTPUT LOGIC MACROCELL (OLMC)
The GAL26CV12 has a variable number of product terms per
OLMC. Of the twelve available OLMCs, two OLMCs have access to twelve product terms (pins 20 and 22), two have access
to ten product terms (pins 19 and 23), and the other six OLMCs
have eight product terms each. In addition to the product terms
available for logic, each OLMC has an additional product-term
dedicated to output enable control.
The GAL26CV12 has a product term for Asynchronous Reset
(AR) and a product term for Synchronous Preset (SP). These
two product terms are common to all registered OLMCs. The
Asynchronous Reset sets all registered outputs to zero any time
this dedicated product term is asserted. The Synchronous Preset
sets all registers to a logic one on the rising edge of the next clock
pulse after this product term is asserted.
The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configgured as either active high or active low.
NOTE: The AR and SP product terms will force the a output of
the flip-flop into the same state regardless of the polarity of the
output. Therefore, a reset operation, which sets the register output
to a zero, may result in either a high or low at the output pin,
depending on the pin polarity chosen.
AR
D
4 TO 1
Q
MUX
a
SP
2 TO 1
t-------------'
MUX
GAL26CV12 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
Each of the Macrocells of the GAL26CV12 has two primary functional modes: registered, and combinatorialI/O. The modes and
the output polarity are set by two bits (SO and S1), which are
normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are
described below and on the the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the a output of that OLMC's Ootype flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high)
or inverted (active low). Output tri-state control is available as
an individual product-term for each OLMC, and can therefore
be defined by a logic equation. The 0 flip-flop's 10 output is fed
back into the AND array, with both the true and complement of
the feedback available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output
of the register, and not from the pin; therefore, a pin defined as
registered is an output only, and cannot be used for dynamic
VO, as can the combinatorial pins.
COMBINATORIAL 1/0
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the
output buffer drive either true (active high) or inverted (active low).
Output tri-state control is available as an individual product-term
for each output, and may be individually set by the compiler as
either ·on" (dedicated output), "off" (dedicated input), or "productterm driven" (dynamic I/O). Feedback into the AND array is from
the pin side of the output enable buffer. Both polarities (true and
inverted) of the pin are fed back into the AND array.
2-83
4/91.Rev.A
..J
I~
i'\
'Lattice
flJ
.l.J
e
Specifications GAL26CV12
SemiconducUJr
Corporation
REGISTERED MODE
AR
o
AR
o
Q
SP
SP
ACTIVE LOW
So
Q
ACTIVE HIGH
=0
So
S, =0
=1
S, =0
COMBINATORIAL MODE
ACTIVE LOW
So
S,
ACTIVE HIGH
=0
=1
=
=
So 1
S, 1
2-84
4/91.Rev.A
[JJ
'L 'Lattice
oo
Specifications GAL26CV12
Semiconductor
Corporation
GAL26CV12 LOGIC DIAGRAM I JEDEC FUSE MAP
1I1I1I1I1I1I1I1I1I1I1I1I1I1I1I1IJ==t~~~f:d~----23
1III.=Jrrc--
20
9 _ _
••••••••!F=m~=:L--19
H:::lo-t---18
1I~1I11~1I1I1I1I1I1I1I1I~1I~f==t~~~~~---17
8282
-Itti-tttt-ttlt--tItt-IItt-#!t--t/tl--tttt-tttI-tlift-t1f1t--iffl--ttlt---<>-----
1I'I8,UU . .
EtectronicSi;na1ure
SVNCHRONOUSPRE8ET
(TOAlLREQlBTERSf
~.'43D.143'1
~ 11Br1tIIBr1rSIa,.419r1131a,. 21.".' tBraD
i :
2-85
4/91.Rev.A
~
~ CorporatiOn
SemiCXJndU~
1,aW
Specifications GAL26CV12
Commercial
e
RECOMMENDED OPERATING CONDo
ABSOLUTE MAXIMUM RATINGS(1)
Commercial Devices:
Supply voltage V cc ........................................ -0.5 to + 7V
Input voltage applied ...........•.•••.•.......... -2.5 to Vee + 1.0V
Off-state output voltage applied ..•........ -2.5 to Vee +1.0V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (Vee)
with Respect to Ground .......•............. +4.75 to +5.25V
Ambient Temperature with
Power Applied ........•..•..•........•......••...•..... -55 to 125°C
1. Stresses above those listed under the·Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming. follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
OVer Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
CONDITION
PARAMETER
MIN.
TYP."
MAX.
UNITS
-
0.8
V
Vcc+1
V
-100
J.LA
10
J.LA
0.5
V
-
V
VIL
Input Low Voltage
Vss-O.5
VIH
Input High Voltage
2.0
ilL'
Input or 110 Low Leakage Current
OV S VIN S VIL (MAX.)
IiH
Input or 110 High Leakage Current
3.5V S VIN S Vee
-
VOL
Output Low Voltage
10L= MAX. Yin = VIL or VIH
-
VOH
Output High Voltage
10H= MAX. Yin = VIL or VIH
2.4
10l
Low level Output Current
-
-
10H
High Level Output Current
los2
Output Short Circuit Current
Vcc =5V
ICC
Operating Power Supply Current
VIL=0.5V
ftoggle
VOUT = 0.5V TA = 25·C
=15Mhz
-50
-
VIH -3.0V
90
8
mA
-3.2
mA
-135
mA
130
mA
Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by
tester ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee = 5V and TA = 25 ·C
CAPACITANCE (TA
=2SoC, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vee = 5.0V. V, = 2.0V
C""
110 Capacitance
10
pF
Vee = 5.0V. VIlO = 2.0V
"Guaranteed but not 100% tested.
2-86
4/91.Rev.A
/llLattice·
.1..;
Specifications GAL26CV12
Commercial
Semiconductor
Corporation
AC SWITCHING CHARACTERISTICS
.
Over Recommended Operating Conditions
PARAMETER
tpd
tco
tcf2
tsu
th
fmax 3
TEST
COND.'
-15
-20
MIN. MAX.
MIN. MAX.
15
Clock to Feedback Delay
-
-
Setup lime, Input or Feedback before Clocki
10
DESCRIPTION
1
Input or 1/0 to Combinatorial Output
1
Clock to Output Delay
-
10
7
UNITS
20
ns
12
ns
10
ns
-
ns
41.6
-
MHz
Hold lime, Input or Feedback after Clocki
0
1
Maximum Clock Frequency with
External Feedback, 1/{tsu + tco)
50
-
1
Maximum Clock Frequency with
Internal Feedback, 1/{tsu + tcf)
58.8
-
45.4
-
MHz
1
Maximum Clock Frequency with
No Feedback
62.5
-
62.5
-
MHz
-
ns
12
0
ns
twh4
-
Clock Pulse Duration, High
8
-
8
twl4
-
Clock Pulse Duration, Low
8
-
8
ten
2
Input or I/O to Output Enabled
-
15
20
ns
tdis
3
Input or I/O to Output Disabled
20
ns
tar
1
Input or I/O to Asynchronous Reset of Register
-
20
ns
15
-
ns
-
tarw
-
Asynchronous Reset Pulse Duration
10
tarr
-
Asynchronous Reset to Clocki Recovery Time
15
tspr
-
Synchronous Preset to Clocki Recovery lime
10
15
20
-
15
12
ns
ns
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
I,
I
2-87
4/91.Rev.A
!IJ
tattJooe
~ Corporation
SemiconducUJr
Specifications GAL26CV12
Industrial
RECOMMENDED OPERATING CONDo
ABSOLUTE MAXIMUM RATINGS(1)
Industrial Devices:
Ambient Temperature (TA) ••••••••••••••••••••••••••• -40 to 85°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.50 to +5.50V
Supply voltage Vee ........................................ -0.5 to +7V
Input voltage applied ............................ -2.5 to Vee + 1.0V
Ott-state output voltage applied ........... -2.5 to Vee +1.0V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or' at any. pther conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
CONDITION
PARAMETER
MIN.
TYP."
MAX.
UNITS
Vss-O.5
-
0.8
V
Vcc+1
V
-100
~A
10
~A
-
0.5
V
-
V
VIL
Input Low Voltage
VIH
Input High Voliage
IlL'
Input or 110 Low Leakage Current
OV $ VIN $ VIL (MAX.)
IIH
Input or 1/0 High Leakage Current
3.5V $ VIN $ Vcc
VOL
Output Low Voltage
10L= MAX. Yin = VIL or VIH
-
VOH
Output High Voltage
10H= MAX. Yin = V'L or V'H
2.4
-
-
-
2.0
Low Level Output Current
10L
10H
High Level Output Current
los·
Output Short Circuit Current
ICC
Operating Power Supply Current
Vee =5V
VOUT = 0.5V TA = 25°C
VIL = O.SV
VIH =3.0V
ftoggle = 1SMhz
8
mA
-
-
-3.2
mA
-50
-
-135
mA
-
90
150
mA
Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = O.SV was selected to avoid test problems caused by
tester ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vcc = SV and TA = 25°C
CAPACITANCE (TA
=25°C, f =1.0 MHz)
SYMBOL
PARAMETER
C,
Coo
TEST CONDITIONS
MAXIMUM"
UNITS
Input Capacitance
8
pF
Vee = S.OV, V,
110 Capacitance
10
pF
Vee = 5.0V, V,/O
=2.0V
=2.0V
"Guaranteed but not 100% tested.
2-88
4191.Rev.A
[J;l
.l.J
lxlttiooe
Specifications GAL26CV12
Industrial
Semiconductor
Corporation
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER
TEST
COND.'
-20
DESCRIPTION
MIN. MAX.
UNITS
tpd
1
Input or I/O to Combinatorial Output
-
20
ns
tco
1
Clock to Output Delay
-
12
ns
Clock to Feedback Delay
-
10
ns
Setup lime, Input or Feedback before Clocki
12
-
ns
tcf2
tsu
th
fmax 3
-
-
0
-
ns
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
41.6
-
MHz
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
45.4
-
MHz
1
Maximum Clock Frequency with
No Feedback
62.5
-
MHz
ns
Hold lime, Input or Feedback after Clocki
twh4
-
Clock Pulse Duration, High
8
twt'
-
Clock Pulse Duration, Low
8
-
ten
2
Input or 110 to Output Enabled
-
20
ns
tdis
3
Input or 1/0 to Output Disabled
20
ns
tar
1
Input or VO to Asynchronous Reset of Register
-
25
ns
Asynchronous Reset Pulse Duration
15
ns
Asynchronous Reset to Clocki Recovery Time
15
-
Synchronous Preset to Clocki Recovery lime
12
-
tarw
tarr
tspr
-
ns
ns
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
2-89
4/91.Rev.A
Ii
!
Specifications GAL26CV12
SWITCHING WAVEFORMS
INPUT or
110 FEEDBACK
COMBINATORIAL
OUTPUT
INPUT or
110 FEEDBACK
\\\\\\\\\["'''"M
t~~
\\\\\\\\S\\S\-s= :
ClK
REGISTERED
OUTPUT
Combinatorial Output
Reg Istered Output
INPUT or
110 FEEDBACK
OUTPUT
ClK
11
Input or 1/0 to Output EnablelDlsable
fmax
(Internal fdbk)
~I--tsu
REGISTERED
FEEDBACK
fmax with Feedback
twl
ClK
Clock Width
INPUT or
VO FEEDBACK
DRIVING SP
INPUT 0/
VOFEEDBACK
DRIVINGAR
ClK
REGISTERED
OUTPUT
REGISTERED
OUTPUT
tc~
\\\\\\\\\\\\\\
Synchronous Preset
ClK
Asynchronous Resat
2-90
4/91.Rev.A
UJttice·
~
.1.J Corporation
SemioonducUJr
Specifications GAL26CV12
fmax SPECIFICATIONS
ClK
lOGIC
~
CLK
··................................ -_ ..._......... _...............
·
.
REGISTER
ARRAY
·................................................................... _...
141~'----
.. u---+~I/04I11I---I •• ~
... -...... -........................................................... .
1OIII~1-----tcl----I~~1
fmax with External Feedback 1/(tsu+tco)
IOIII~I----tpd----~~
Note: fmax with extemal feedback is calculated from measured tsu and teo.
fmax with Internal Feedback 1/(tsu+tcf)
ClK
................ _... __ ........................................... .
··
··
i.
Note: tef is a calculated value, derived by subtracting tsu from the period of fmax wlintemal
feedback (tef - 1lfmax - tsu). The value of tef
is used primarily when calculating the delay from
clocking a register to a combinatorial oUtput
(through registered feedback), as shown above•
.For example, the timing from clock to a combinatorial output is equal to tef + tpd.
.
LOGIC
ARRAY
REGISTER
..
....
i.
·.........................................................................
fmax With No Feedback
Note: fmax with no feedback may be
less than 1ltwh + twl. This is to allow for
a clock duty cycle of other than 50%.
SWITCHING TEST CONDITIONS
Input Pulse Levels
GNDt03.0V
Input Rise and Fall limes
3ns 10%-90%
Input liming Reference Levels
1.5V
Output liming Reference Levels
1.5V
Output Load
FROM OUTPUT (QlQ)
UNDER TEST
See Figure
TEST POINT
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition
1
2
3
R1
Rz
CL
4700
3900
50pF
Active High
00
3900
50pF
Active Low
4700
3900
50pF
Active High
00
3900
5pF
Active Low
4700
3900
5pF
Cl INCLUDES JIG AND PROBE TOTAL CAPACITANCE
2-91
.J
4191.Rev.A
/ll~·
.l..J
Specifications GAL26CV12
Corporation
ELECTRONIC SIGNATURE
OUTPUT REGISTER PRELOAD
An electronic signature (ES) is provided in every GAL26CV12
device. It contains 64 bits of reprogram mabie memory that can
contain user-defined data. Some uses include user 10 codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the
security cell.
SECURITY CELL
A security cell is provided in every GAL26CV12 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional
bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature
is always available to the user, regardless of the state of this
control cell.
LATCH-UP PROTECTION
GAL26CV12 devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch. Additionally, outputs are designed with nchannel pullups instead of the traditional p-channel pullups to
eliminate any possibility of SCA induced latching.
DEVICE PROGRAMMING
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may oocur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.).
To test a design for proper treatment of these conditions, a way
must be provided to break the feedback paths, and force any
desired (i.e., illegal) state into the registers. Then the machine
can be sequenced and the outputs tested for correct next state
conditions.
The GAL26CV12 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus,
any present state condition can be forced for test sequencing.
if necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically.
INPUT BUFFERS
GAL26CV12 devices are designed with TTl level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic much less
than bipolar TTL logic.
The input and I/O pins also have built-in active pull-ups. As a
result, floating inputs will float to a TTL high (logic 1). However,
Lattice recOmmends that all unused inputs and tri-stated 110 pins
be connected to an adjacent active input, Vee, or ground. Doing so will tend to improve noise immunity and reduce Icc for the
device.
GAL devices are programmed using a Lattice-approved Logic
Programmer, available from a number of manufacturers (see the
the GAL Development Tools section). Complete programming
of the device takes only a few seconds. EraSing of the device
is transparent to the user, and is done automatically as part of
the programming cycle.
Typical Input CUrrent
/"
./
/'
/"
~
-60
o
1.0
2.0
3.0
4.0
5.0
Input Voltag' (Voltl)
2-92
4191.Aev.A
:LaUiOOC
[JJ
.l.J
Specifications GAL26CV12
Semioonduewr
Corporation
POWER-UP RESET
Va:
OV
V IH
CLK
VIL
rT"T"T"rh'TT"T'T"......I I , . - - - - - - - -
VAUD CLOCK SIGNAL
...l...I...l..I-+'-'L...L.l.J..l..lI,'-_ _ _ _ _ _ __
INTERNAL
REGISTER
Q-OUTPUT
INTERNAL REGISTER
RESET TO LOGIC 0
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Circuitry within the GAL26CV12 provides a reset signal to all registers during power-up. All internal registers will have their Q
outputs set low after a specified time (t RESET' 45JLS MAX). This
feature can greatly simplify state machine design by providing
a known state on power-up.
The timing diagram for power-up is shown above. Because of
the asynchronous nature of system power-up. some conditions
must be met to guarantee a valid power-up reset of the
GAL26CV12. First. the Vcc rise must be monotonic. Second.
the clock input must become a proper TIL level within the specified time (tPR • 100ns MAX). The registers will reset within a maximum of!";sETtime.Asin normal system operation. avoid clocking
the device until all input and feedback path setup limes have been
met.
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN
e>----f6=
OUIPUI~PlN
0.1.
Flldb.ek
Acive Pull-up
Cicuit
Vee
(VroITypiell.3.2V)
~:~~;::e
........... .-.................
i
Vee:
:
:
i~_
:
:
:
i CIIcI*
: •• u
Vee
Y.....
•..
I I
::
i
:
Oulpul
::
~
:........::
~
Dill
.................... :
('Irel Typieli. 3.2V)
Viti
PIN
PIN
FIIcIIIck
(To InpuiBuIlar)
Input
Output
2-93
4191.Rev.A
[J;1
~ :LaWcc
Specifications GAL26CV12
Typical Characteristics
e
Semironductor
CorporaUon
YS. _
Vee
1.3 . ._ _Normalized
-,-_ _--rTsu
__
. -_ _,
NormaUzed Tpd YS Vee
1.2+----i---+---t---i
~~
-
0.1
I·····
'T H.,.L
PT L-:.oH
5
.•
~
~~
./
5
5.25
0.7
./
IV
..I
D.
o.7
V
0
2S
50
75
100
1.2
8 •.•
I~D.t·
Z
.. ,
----
.....
"8.4
I-
:
d
/
2
·2
-3
.... •••
V
IOl YS. VOL
100
125
-55
V
L
/
50
75
100
125
V
12
~
..,
.
~
1z o.
o
~
t
V
/
~
0.8
...
o.7
200
300
4.75
4 .•
i"'o,..---+----t---t----1
5.25
Normalized k::c VI. Temperature
"' ...
II ,.,
'
~,
-60+----+---""'d---t----1
5
Suppty Vohage (V)
., .. . -_ _--r_I_O_H_VS.,._V_O_H_..._ _- .
"00
25
Normalizad lee lIS. Vee
OutpoA Loading Capacitance (pi)
1§
...,,-
0
1.3
200
.
·25
Ambient Temperature (OC)
/'
100
Mo,.
• of Outputs
250
75
/'
!
M.... ••
so
25
Oehe Tpd VI. Output Loading
.0
~
V
L
,...
0.1
0
-25
Ambienl Temperature (OC)
Oeha Tpd ... 11 of Outputs s..nching
v
V
0.'
Ambient Temperalure (OC)
V V
.L.
~
V'
l-
l/
V
..ss
125
5.5
Normalized Teo VI. Temperalure
0.7
·25
5.25
1.3
:/
V
./
V
5
Supply Voltage (V)
1.2
V
-SO
4.75
4.5
5.5
Normalized Tsu lIS. Temperalura
'.3
./
o.t
0.8
S\4lPly Voltage (V)
..,. V
1'
4.75
4.5
Normalizad Tpd vs. Temperature
'.2
L.8
Il····· PTH·.L J
D.7L_-L_.-.J~=::t==~
3
"8. •.•
Z
••••••••••••••••
8 1.1
iJ:j 1
~
O.8+----+---+r=:-;;PT~L:HHlr
...
S.2!5
Supply Voltage (V)
..
1i
D.9+----+---f---i---i
••••••••
~
m
t-
12
-
m::-:---t---t---t-----j
1.1
1
"--
0.7
4.75
1 .........
I
....iil
Normalized TCD VI. Vee
1.3
.i"o..~
1
....
klc
va. T-,,*Mln ~
lab va. T.............
~
...........
~o.•
0.'
"
.... .....
•.7
2
VOL (V)
2
VOH(V)
2-94
·&5
-25
0
2S
so
75
100
125
Ambient Temperature (OC)
4191.Rev.A
!llLatUce
1..1
GAL20RA10
s
SemiconduGUJr
Corporation
High-Speed Asynchronous E2CMOS PLD
Generic Array Logic1'M
FUNCTIONAL BLOCK DIAGRAM
FEATURES
• HIGH PERFORMANCE ElCMOS· TECHNOLOGY
-12 ns Maximum Propagation Delay
- Fmax =71.4 MHz
- 12 ns Maximum from Clock Input to Data Output
- TTL Compatible 8 rnA Outputs
- UHraMOS- Advanced CMOS Technology
~O-----------------,
~
I
INPUT
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
- 75rnA Typ Icc
INPUT
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
- Reconflgurable logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «50 ms)
- 20 Year Data Retention
INPUT
I......'I-C!-..,.....O
INPUT
=l....IC~~OLQQ
LOIQ
INPUT
• TEN OUTPUT LOGIC MACROCELLS
-Independent Programmable Clocks
- Independent Asynchronous Reset and Preset
- Registered or Combinatorial wHh Polarity
- Full Function and Parametric Compatibility with
PAL20RA10
INPUT
INPUT
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional TestabllHy
INPUT
• APPUCATIONS INCLUDE:
- State Machine Control
- Standard logic Consolidation
- MuHlple Clock logic Designs
INPUT
1......'t-C'""r"iO
INPUT
IIOoQ
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
The GAL20RA10 combines a high performance CMOS process
with electrically erasable (f?) floati{lg gate technology to provide
the highest speed performance available in the PlD market.
Lattice's !?CMOS circuitry achieves power levels as low as 75mA
typical Icc which represents a substantial savings in power when
compared to bipolar counterparts. E2 technology offers high
speed (OLMC . 17 ~
2200
XOR • 3206
a=
2240
-
9 (11) .........
-=.J -.... 18 (21)
>OLMC·18 r.:1
1880
~
2520
OLMC . 16 r.:1
XOR ·3207
17 (20)
-=:J
-=:J
-a 16 (19)
2560
OLMC·15 r.:1
10 (12)
-........
2840
XOR • 3208
2880
OLMC·14
11 (13)
r>-
-
3160
XOR • 3209
~
A
'V
-=:J
-a 15 (18)
~-a
a
14 (17)
13 (16)
64-USER ELECllIONIC SIGNATURE FUSES
13210.3211 .....
Byte 71 Byte 6 ....
•... 3272, 32731
•... Byte 11 Byte 0
M L
S
S
B B
2-99
4/91.Rev.B
Specifications GAL20RA 10
Commercial
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDo
Commercial Devices:
Ambient Temperature (TA) ••••••••••••••••••••••••••••• 0 to +75°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.75 to +5.25V
Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee +1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings' may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming. follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYp.a
MAX.
UNITS
VIL
Input Low Voltage
Vss-O.5
-
0.8
V
VIH
Input High Voltage
2.0
-
VCC+1
V
IlL'
Input or 110 Low Leakage Current
-100
J.lA
10
J.tA
0.5
V
-
V
8
mA
Input or 110 High Leakage Current
3.5V S VIN S Vee
-
VOL
Output Low Voltage
lot. .. MAX. Vin .. VIL or VIH
-
-
VOH
Output High Voltage
IoH .. MAX. Vin .. VIL or VIH
2.4
-
IIH
10L
Low Level Output Current
10H
High Level Output Current
1052
ICC
OV S VIN S VIL (MAX.)
-
-
-
-
Output Short Circuit Current
Vee-5V VOUT .. 0.5V TA .. 25°C
-SO
Operating Power Supply Current
VIL-0.5V VIH -3.0V
ftoggle .. 15Mhz Outputs Open
-
-3.2
mA
-
-135
mA
75
100
mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout .. 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee .. 5V and TA .. 25°C
CAPACITANCE (TA = 25 C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
Vee - 5.0V. VI - 2.0V
CliO
VO Capacitance
10
pF
Vee" 5.0V. VIiO '" 2.0V
"Guaranteed but not 100% tested.
2-100
4J91.Rev.B
tattioo~
[]J
LJ Corporation
SemiwnductiJr
Specifications GAL20RA 10
Commercial
AC SWITCHING CHARACTERISTICS
OVer Recommended Operating Conditions
TEST
PARAMETER
COND.'
DESCRIPTION
1
Input or I/O to Combinatorial Output
tco
1
Clock to Output Delay
tsu
1
-
12
-
15
12
-
15
-
20
20
33.3
-
-
41.7
-
Setup Time, Input or Feedback before Clock
4
-
7
3
-
3
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
62.5
-
-
10
Hold Time, Input or Feedback after Clock
45.0
-
Maximum Clock Frequency without
71.4
-
50.0
-
10
12
12
-
fmax 2
1
-30
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
tpd
th
-20
-15
-12
UNITS
-
30
ns
30
ns
20
-
ns
20.0
-
MHz
-
25.0
-
MHz
12
-
20
12
-
20
3
10
ns
Feedback
twh 3
-
Clock Pulse Duration, High
7
twl3
-
Clock Pulse Duration, Low
7
ten / tdis
2,3
Input or I/O to Output Enabled / Disabled
ten / tdis
2,3
OE to Output Enabled / Disabled
-
tar/tap
1
Input or I/O to Asynchronous. Reset / Preset
-
Asynchronous Reset / Preset Pulse Duration
12
Asynchronous Reset / Preset Recovery Time
7
Preload Pulse Duration
12
twp
-
tsp
-
Preload Setup Time
7
thp
-
Preload Hold Time
7
tarw/tapw
tarr /tapr
9
-
10
15
10
15
10
10
15
-
-
20
15
12
-
20
15
20
15
-
15
-.
12
20
-
ns
30
ns
20
ns
30
ns
20
-
ns
20
-
ns
30
-
ns
25
-
ns
25
-
ns
-
ns
1) Refer to Switching Test Conditions sectIOn.
2) Refer to fmax Descriptions section.
3) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse. Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
GNDt03.0V
3ns 10%-90%
1.5V
1.5V
Output Load
+5V
See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition
1
2
3
Active High
Active Low
Active High
Active Low
R1
R2
CL
4700
3900
3900
3900
3900
3900
50DF
50pF
50pF
5pF
5pF
00
4700
00
4700
FROM OUTPUT (0/0)
UNDER TEST
- -.....- -.....-TESTPOINT
"'~
~
f'
-
CllNClUOES JIG AND PROBE TOTAL CAPACITANCE
2-101
4/91.Rev.B
I
.,
.J..
Specifications GAL20RA 10
Industrial
RECOMMENDED OPERATING CONDo
ABSOLUTE MAXIMUM RATINGS(1)
Industrial Devices:
Supply voltage Va; .......................................-o.5 to +7V
Input voltage applied ........................... -2.5 to Va; + 1.0V
Off-state output voltage applied .......... -2.5 to Va; + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
Ambient Temperature (TAl .......................... -40 to +85°C
Supply voltage (Va;l
with Respect to Ground ...................... +4.50 to +5.50V
DC ELECTRICAL CHARACTERISTICS
OVer Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP."
MAX.
UNITS
-
0.8
V
VCC+1
V
-100
VIL
Input Low Voltage
Vss-O.5
VIH
Input High Voltage
2.0
IlL'
Input or I/O Low Leakage Current
OV S VIN S VIL (MAX.)
-
Input or 110 High Leakage Current
3.5V s VIN S Vex;
VOL
Output Low Voltage
IoL '" MAX. Yin '" VIL or VIH
-
VOH
Output High Voltage
IoH =MAX. Vin =VIL or VIH
2.4
IIH
10L
Low Level Output Current
10H
High Level Output Current
los2
ICC
-
-
Output Short Circuit Current
Va;.5V VOUT - 0.5V TA _ 25·C
-50
Operating Power Supply Current
VIL.0.5V VIH=3.0V
ftoggle .. 15Mhz Outputs Open
-
-
10
IlA
IlA
-
0.5
V
-
-
V
8
mA
-3.2
mA
-135
mA
75
120
mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout .. 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vex; .. 5V and TA .. 25 ·C
CAPACITANCE (TA
=25 C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
Vcc '" 5.0V, VI" 2.0V
Coo
VO Capacitance
10
pF
Vcc .. 5.0V, V110 = 2.0V
"Guaranteed but not 100% tested.
2-102
4/91.Rev.B
Specifications GAL20RA 10
Industrial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER
TEST
COND.'
-20
DESCRIPTION
MIN. MAX.
UNITS
tpd
1
Input or I/O to Combinatorial Output
-
20
ns
teo
1
Clock to Output Delay
-
20
ns
Setup Time, Input or Feedback before Clock
10
ns
MHz
tsu
th
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
33.3
-
1
Maximum Clock Frequency without
Feedback
41.7
-
MHz
ns
-
Hold Time, Input or Feedback after Clock
3
fmax 2
ns
-
Clock Pulse Duration, High
12
Clock Pulse Duration, Low
12
-
ten/tdis
2,3
20
ns
2,3
Input or I/O to Output Enabled / Disabled
OE to Output Enabled / Disabled
-
ten / tdis
ns
tar/tap
1
Input or I/O to Asynchronous Reset / Preset
-
15
20
ns
-
Asynchronous Reset / Preset Pulse Duration
20
ns
Asynchronous Reset / Preset Recovery Time
12
-
Preload Pulse Duration
20
-
Preload Setup Time
15
ns
Preload Hold Time
15
-
twh 3
twl3
tarw/tapw
tarr /tapr
twp
tsp
thp
ns
ns
ns
ns
1) Refer to Switching Teat Conditions sectIOn.
2) Refer to 'max Descriptions section.
3) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
GNDto 3.0V
3ns 10"10 - 90%
1.5V
1.5V
Output Load
+5V
See Figure
3·state levels are measured 0.5V from steady·state active
level.
Output Load Conditions (see figure)
Teat Condition
1
2
3
Active High
Active Low
Active High
Active Low
R1
Fb
CL
4700
3900
3900
3900
3900
3900
50pF
50pF
50pF
5pF
5pF
00
4700
00
4700
FROM OUTPUT (010)
UNDER TEST
--+---~-TEST POINT
R.
~
~
f'
-
CLlNCLUOESJIG AND PROBE TOTAL CAPACITANCE
2-103
4191.Rev.B
I
~
'Ll1ttiOO
[JJ
1..J
4D
Specifications GAL20RA 10
Semironductor
CorporaUon
SWITCHING WAVEFORMS
Input or
110 Feedback
Input or
I/O Feedback
Combinatorial
Output
Clock
Registered
Output
CombinatorIal Output
Registered Output
Input or
I/O Feedback
Asserting Preset
Input or
110 Feedback
Asserting Reset
Regis tered
Output
Registered
Output
___XXXX1=
Clock
___XXX5H
J!
".
j
0.8
+---11---+--+---1
0.8
+---'I----l----I-----l
uo
4.75
5.00
j
1
~
0.9
V
0.8
'.00
••75
4 ..0
' ..0
4.50
5.50
5.25
'.00
5.50
Normalized Teo vs Temp
Normalized Tsu vs Temp
I
...
..• ~ ..... RISE I
;;:/
V'
--FALL I
/
.... . V
'.4
/
V
~
~'
.
,.
0.7
.,.
]
1.1
Z
...
.'V' 1/ ;.,
"
-0.5
,'V
..5.
.
,.
0.7
• 20
.
..
"
",
_
-0.5
, ," /V
..5.
~
c
.
• .0
34'
-1.5
"
.' ./ .......
V
V
I·····~SE}
1/
[--FALL
..
2
3
"
5
•
7
•
,
Number of Outputs Swkching
Number of Outputs Sw~ching
Delta Tpd vs Output Loading
Delta Teo vs Output Loading
./
~""'RISE I
--FALLI
./
./
/
,/
v.'
.y'
.
. ...
Temperature (deg. C)
.....
II·····RISE}
Il--FALL
,
,/"
k""
Delta Teo VI # of Outputs
Switching
J! .•
./V
..
0.8
Temperature (deg. C)
Delta Tpd vs # of Outputs
Switching
".0
---
l'
0.'
Temperature (deg. C)
_
./
~ 1.2
0.'
...
4.75
Normalized Tpc! vs Temp
0.8
0.7
0.'
f-'"'
Supply Voltage (V)
11
~
0.'
Supply Voltage (V)
--m.J
~1.1
'" "
0.8
. .
10
'2
•• l····~SEI
--FALL I
./
"
"
,
V"
'/'
·2
·4
'-/
·4
so
100
150
200
250
300
Output Loading (pF)
50
100
150
200
UO
300
Output Loading (pF)
2-107
.,
I
....--V
Supply Voltage (V)
••••• PTH••L
"0
'"
--
).
".
j
1.3
I.'
FALL
r:.:.::...
~1
'" '"
..•
I·····
RSEl
I
I.,
11
'f===~~~~~
..~.~~~
~
Normallzad Tsu vs Vee
Normalized Teo vs Vee
4/91.Rev.B
Specifications GAL20RA 1 ()
Typical Characteristics
Volvslol
...
o
~
...
:;s
"- r--...
/
1.5
...........
/v
...
V
Voh vsloh
Voh VB Ioh
r- r-..
-
/'
V
0.00
20,00
40.00
eo.OO
10.00
0.00
10.00
20.00
lol(mA)
1.10
j ..
~
0.'0
10.00
- --s.oo
'-....
I'---
....
10.00
0.00
t.OO
2.00
........
....
l!
11
r-.....
1.10
~I.oo
I
Jt
"
..
0.'0
~
5.21
r-.........
IS
71
100
125
V
........
uo
~
/"
I.
3D
.
Frequency (MHz)
Temperature (dag. C)
Delta Icc VB Vln (1 Input)
4.00
./
1J!0
~ 1.10
I
""'r-.....
$.$0
3.00
Normalized Icc VB Freq.
11
I..........
Supply Voltage (V)
---
loh(mA)
u.
4.7&
\
3.75
Normalized icc VB Tamp
u.
4.50
40.00
...:is ....
Ioh(mA)
Normalized Icc VB Vee
....
10.00
~
Input Clamp (Vlk)
• .00
/'
0.00
1/
4.00
,1\
J "V
!.
dl
..........
.........
-
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
'.00
'.00
10.00
12.00
.....
j
/
/
'I
•• .00
·2.00
....
Vik (V)
Vin (V)
2-108
4/91.Rev.E
:LB.ttiOO®
[JJ
.l..J
GAL6001
Semiconductor
High Performance E2CMOS FPLA
Generic Array Logic™
Corporation
FEATURES
FUNCTIONAL BLOCK DIAGRAM
• ELECTRICALLY ERASABLE CELL TECHNOLOGY
- Instantly Reconflgurable Logic
- Instantly Reprogrammable Cells
- Guaranteed 100% Yields
• HIGH PERFORMANCE E·CMOS· TECHNOLOGY
- Low Power: 90mA'TYplcal
- High Speed: 12ns Max. Clock to Output Delay
25ns Min. Setup TIme
30ns Max. Propagation Delay
• UNPRECEDENTED FUNCTIONAL DENSITY
- 78 x 64 x 36 FPLA Architecture
- 10 Output Logic Macrocells
- 8 Burled Logic Macrocells
- 20 Input and 1/0 logic Macrocells
• HIGH-LEVEL DESIGN FLEXIBILITY
- Asynchronous or Synchronous Clocking
- Separate State Register and Input Clock Pins
- Functionally Supersets Existing 24-pln PAL·
and IFL~ Devices
• TTL COMPATIBLE INPUTS AND OUTPUTS
• SPACE SAVING 24-PIN, 300-MIL DIP
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~~
______
~
MACROCELL NAMES
ILMC
INPUT LOGIC MACROCELL
10LMC VO LOGIC MACROCELL
• HIGH SPEED PROGRAMMING ALGORITHM
BLMC
BURIED LOGIC MACROCELL
• APPLICATIONS INCLUDE:
-Sequencer
- State Machine Control
....,.. Multiple PLD Device Integration
OLMC
OUTPUT LOGIC MACROCELL
PIN NAMES
DESCRIPTION
Using a high performance PCMOS technology, Lattice
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers the highest degree of functional integration, flexibility, and
speed currently available in a 24-pin, 300-mil package.
INPUT
INPUT CLOCK
Vee
POWER (+5)
OCLK
OUTPUT CLOCK
GND
GROUND
Programming is accomplished using standard hardware and
software tools. In addition, an Electronic Signature is available
for storage of user specified data, and a security cell is provided
to protect proprietary designs.
1/010
PIN CONFIGURATION
The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC).
In addition, there are 10 Input Logic Macrocel!s (ILMC) and 10
110 Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
Advanced features that simplify programming and reduce test
lime, coupled with E2CMOS reprogram mabie ceHs, enable 100%
AC, DC, programmability, and functionality testing of each
GAL6001during manufacture. This allows Lattice to guarantee
100% performance to specifications. In addition, data retention
of 20 years and a minimum of 100 eraselwrite cycles are
guaranteed.
.
BIDIRECTIONAL
I. - I,.
ICLK
DIP
PLCC
IIICLK
!5u
--"
.
l!
!
0
~
0
.~
I
vOla
IIOIQ
Top View
vOla
vOla
IIOIQ
GAL6001
Vee
vOla
28
IIOIQ
NC
1
UOIQ
Me
IIOIQ
vOla
IIOIQ
vOla
IIOIQ
uO/a
-
-
D
i§
l!
~ ~ ~
vOla
uO/a
GND
OCLK
Copyright Cl991 Lattice Semiconductor Corp. GAL. E'CMOS and UhraMOS are registered trademarks of Lattice Semiconductor Corp. Go....ie Array logic is a Irade_k of Lattice SerriconduclOr Corp. PAL is a registered trademark of Advanced Micro Devices. inc. iFL is a trademark of Slgnetics. The speeWlcations and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon U.SA
Tel. (503)681-0118 or 1-800-FASTGAL; FAX (503)681-3037
2-109
April 1991.Rev.A
'LatliOO[JJ
~
Specifications GAL6001
Semironductor
Corporation
GAl6001 ORDERING INFORMATION
Commercial Grade Specifications
Package
Tpd (n8)
Fclk(MHz)
Icc (mA)
30
27
150
GAL6001-30P
24-Pin Plastic DIP
150
GAL6001-30J
28-Lead PLCC
150
GAL6001-35P
24-Pin Plastic DIP
150
GAL6001-35J
28-Lead PLCC
35
22.9
Ordering #
GAl6001 ORDERING INFORMATION
xxxxxxx - XX
GAL6001
X X
DeVlceN.me~
L
Speed (ns)
Grade
Package
Blank
= Commercial
P = Plastic DIP
= PLCC
J
2-110
4/91.Rev.A
Lattlce*
[JJ
.l.J
Specifications GAL6001
Semironductor
Corporation
INPUT LOGIC MACROCELL (ILMC) AND 1/0 LOGIC MACROCELL (IOLMC)
rile GAL6001 features two configurable input sections. The ILMC
lection corresponds to the dedicated input pins (2-11) and the
OLMC to the I/O pins (14-23). Each input section is configurable
IS a block for asynchronous, latched, or registered inputs. Pin
I (ICLK) is used as an enable input for latched macrocells or as
I clock input for registered macrocells. Configurable input blocks
)rovide systems designers with unparalled design flexibility. With
the GAL6001 , external registers and latches are not necessary.
Both the ILMC and thelOLMC are block configurable. However,
the ILMC can be configured independently of the 10LMC. The
three valid macrocell configurations are shown in the macrocell
equivalent diagrams on the following pages.
OUTPUT LOGIC MACROCELL (OLMC) AND BURIED LOGIC MACROCELL (BLMC)
rhe outputs of the OR array feed two groups of macrocells. One
Iroup of eight macrocells is buried; its outputs feed back directly
nto the AND array rather than to device pins. These cells are
:alled the Buried Logic Macrocells (BLMC), and are useful for
)uilding state machines. The second group of macrocells conlists of 10 cells whose outputs, in addition to feeding back into
he AND array, are available at the device pins. Cells in this group
ue known as Output Logic Macrocells (OLMC).
rhe Output and Buried Logic Macrocells are configurable on a
nacrocell by macrocell basis. Buried and Output Logic Macrocells
nay be set to one of three configurations: combinational, "O-type
egister with sum term (asynchronous) clock", or "DIE-type
egister." Output macrocells always have 110 capability, with
lirectional control provided by the 10 output enable (OE) prodIct terms. Additionally, the polarity of each OLMC output' is
lelected through the "0" XOR. Polarity selection is available for
3LMCs, since both the true and complemented forms of their
)utputs are available in the AND array. Polarity of all "E" sum
erms is selected through the "E" XOR.
IVhen the macrocell is configured as a "DIE type registered", the
egister is clocked from the common OCLK and the register clock
mabie input is controlled by the associated "E" sum term. This
:onfiguration is useful for building counters and state-machines
vith state hold functions.
2-111
When the macrocell is configured as a "D type register with a sum
term clock", the register is always enabled and its "E" sum term
is routed directly to the clock input. This permits asynchronous
programmable clocking, selected on a register-by-register basis.
Registers in both the Output and Buried Logic Macrocells feature
a common RESET product term. This active high product term
allows the registers to be asynchronously reset. Registers are
reset to a logic zero. If connected to an output pin, a logic one
will occur because of the inverting output buffer.
There are two possible feedback paths from each OLMC. The
first path is directly from the OLMC (this feedback is before the
output buffer and always present). When the OLMC is used as
an output, the second feedback path is through the 10LMC. With
this dual feedback arrangement, the OLMC can be permanently
buried (the associated OLMC pin is an input), or dynamically
buried with the use of the output enable product term.
The DIE registers used in this device offer the designer the ultimate in flexibility and utility. The DIE register architecture can
e!T1ulate RS-, JK-, and T-type registers with the same efficiency
as a dedicated RS-, JK-, or T-register.
The three macrocell configurations are shown in the macrocell
equivalent diagrams on the following pages.
4/91.Rev.A
1xJttiOO~
!JJ
.J"", SemironductlJr
Corporation
Specifications GAL6001
ILMC AND IOLMC CONFIGURATIONS
:__ ________________
I
------------------IClK
I
E
I~~K
~
NC
I
Q
LATCH
INPUT
PINS 2-11
OR
IJOPINS
D
I
10
--.+t-r-;:::==:::::;-,
I
MUX
14-23
TO
AND
ARRAY
Q
REGISTER
INPUT
PINS 2·11
OR
\lOPINS
14·23
.
10
I
I
I
I
'
I:L
TO
AND
ARRAY
D
L
1~
__________________ I
Asynchronous Input
ILMC/IOLMC
Generic Block Diagram
LATCH
IClK
INPUT
PINS 2·11
OR
\10 PINS
14·23
IClK
Q
I
10
SYN
10
REGISTER
D
I
I
TO
AND
ARRAY
INPUT
PINS 2-11
OR
IJOPINS
14-23
I
I
10
LATCH
10
I
TO
AND
ARRAY
D
Latched Input
Registered Input
LATCH
Q
E
I
SYN
LATCH
SYN
o
o
o
2-112
4191.Rev.A
'LattiOO~
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L.. Corporation
Semiconductor
Specifications GAL6001
OLMC AND BLMC CONFIGURATIONS
RES'"
f--I~-:-1.[)o-';-'&-IO
FROM
OR
IUlRAY
D
t ...... !I... ~~!
E ......._
FROM
OR
ARRAY
......../
CUll
-----------------~
,_
OCU<
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
OCLII
DIE Type Registered
OLMC/BLMC
Generic Block Diagram
TOAND ............... "
Ran
I -
I
-
-
-
-
-
-
-
-
-
-
-
OUIC"
ONLY
OR
_1- - - -
'"""" .. ,,,,,,,,,,,,,,
I
IOLMC
.
- ~- - .
.
~
Q
"'I
ARRAY
RES1~
I ____________
__
:'~~""""''''
ti _~"
r.l"""'II'.I,,.I,
I"
I: lOR
IOLUe
,
OLMC"
ONLY :
,
He
~
D~';~~I~~~------~>-~:~~~~.O
~
'~
.................. ........................................ ~
..
~""",,.,,,,.,l
I
~ ............ I..~~~~~y..
FROM
OR
Vee
lCOR
OLMC ONLY
o
TO AND
:
..........~L-IIO
1
~
~
r-'>-~.~
R
OUTSYN(i)
~
,
,
~
D_'~;~~~~~--~D
ARRAY
~ PT
~",;I ... , I " ' ... "''''''''',
I"
I: XOR
FROM
ARRAY: OE
CKS(i)
I
ARRAY
I
E-,I
'-
NC
He
-- ---
- - ~
He
- - - - - - - - - - - - - -'
~-------t-------------~
OCLK
OCLII
D Type Register
with Sum Term
Asynchronous Clock
Combinational
CKS(i)
OUTSYN(i)
CKS(i)
o
o
o
2-113
OUTSYN(i)
4191.Rev.A
'Lattice·
~Corporation
Semiconductor
Specifications GAL6001
GAL6001 LOGIC DIAGRAM
lelK
1
[J3
,,.
...
,
~~
~
~
.
~"
"
"
."
..
,7
:w-
::
,,-
,.
roJ-
10
23
22
21
20
"
18
17
16
"
"
RESET
,.
OCLK
2-114
4/91.Rev.J
'LattiOO$
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f
Specifications GAL6001
Commercial
Semironductor
CorporaUon
ABSOLUTE MAXIMUM RATINGS(l)
RECOMMENDED OPERATING CONDo
Supply voltage Vee ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee + 1.0V
Storage Temperature ................................. -65 to 150°C
Ambient Temperature with
Power Applied ........................................-55 to 125°C
Commercial Devices:
Ambient Temperature (TA ) •••••••••••••••••••••••••••••••• 0 to 75°C
Supply voltage (Vee)
with Respect to Ground ...................... +4.75 to +5.25V
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP."
-
VIL
Input Low Voltage
Vss -0.5
VIH
Input High Voltage
2.0
IlL
Input or 110 Low Leakage Current
OV S Y,N S V,L (MAX.)
IIH
Input or 110 High Leakage Current
V,H S V,N S Vee
VOL
Output Low Voltage
10L. MAX. Yin - V,L or V,H
-
VOH
Output High Voltage
IOH = MAX. Yin = V,L or V,H
2.4
Low Level Output Current
10H
High Level Output Current
los'
Output Short Circuit Current
Vcc=5V
Icc
Operating Power Supply Current
V,L = 0.5V V,H = 3.0V ftoggle = 15MHz
VOUT = 0.5V
UNITS
0.8
V
VcC+1
V
·10
~A
10
~
0.5
V
-
V
16
mA
-3.2
mA
-30
-
-130
mA
-
90
150
mA
-
10L
MAX.
Outputs Open (no load)
1) One output at a time for a maximum duration of one second. Vout =0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc - 5V and TA = 25 ·C
CAPACITANCE (TA
=25°C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
C,
Input Capacitance
8
pF
Vcc = 5.0V, V, • 2.0V
110 Capacitance
10
pF
Vee = 5.0V, VI/O = 2.0V
C .
I/O
'Guaranteed but not 100% tested.
2-115
4/91.Rev.A
Specifications GAL6001
Commercial
AC SWITCHING CHARACTERISTICS
OVer Recommended Operating Conditions
PARAMETER
TEST
COND'.
-30
-35
MIN. MAX.
MIN. MAX.
30
-
30
35
DESCRIPTION
tpd1
1
tpd2
1
Feedback or 1/0 to Combinational Output
tpd3
1
Transparent Latch Input to Combinatorial Output
tco1
1
Input latch IClKi to Combinatorial Output Delay
tco2
1
Input Reg. IClKi to Combinatorial Output Delay
-
tc03
1
Output DIE Reg. OClKi to Output Delay
-
12
tc04
1
Outout 0 Rea. Sum Term ClK"t to Outout Delav
-
35
-
Setup Time, Input before Input Latch IClK.!.
2.5
-
3.5
tsu2
-
Setup Time, Input before Input Reg. IClKi
2.5
-
3.5
tsu3
-
Setup Time, Input or Feedback before DIE Reg. OClKi
25
-
30
-
Setup Time, Input or Feedback before 0 Reg. Sum Term ClKi
7.5
-
10
tsu5
Setup Time, Input Reg. IClKi before DIE Reg. OClKi
30
-
35
-
tsu6
-
Setup Time, Input Reg. IClK"t before 0 Reg. Sum Term ClKi
15
-
17
-
th1
-
Hold Time, Input after Input latch IClK.!.
5
-
5
th2
-
Hold Time, Input after Input Reg. IClKi
5
tsu1
tsu4
th3
th4
fmax
twh12
twh22
-
-
Combinatoriallnpurto Combinatorial Output
35
35
35
ns
-
35
ns
-
40
ns
40
ns
40
ns
13.5
ns
40
ns
-
ns
-
ns
-
-5
10
-
12.5
Maximum Clock Frequency, OClK
27
-
22.9
IClK or OClK Pulse Duration, High
10
10
-
ns
Sum Term ClK Pulse Duration, High
15
15
-
ns
IClK or OClK Pulse Duration, Low
10
10
-
ns
-
tarw
-
Reset Pulse Duration
15
ten
2
Input or I/O to Output Enabled
-
25
tdis
3
Input or I/O to Output Disabled
-
25
-
35
-
tarr2
ns
Hold Time, Input or Feedback after 0 Rea. Sum Term ClKi
-
1
ns
-
15
-
ns
5
DIE Reg. OClK"t
Sum Term ClK Pulse Duration, low
tar
ns
-5
Hold Time, Input or Feedback after
-
tarr1
-
-
twl22
twl12
UNITS
Input or I/O to Asynchronous Reg. Reset
-
Asynchronous Reset to OClK Recovery Time
20
Asynchronous Reset to Sum Term ClK Recovery Time
10
-
15
15
20
10
-
ns
ns
ns
ns
MHz
ns
ns
30
ns
30
ns
35
ns
-
ns
ns
1) Refer to Switching Test Conditions section.
2) Clock pulses of widths less than the specification may be detected as valid clock signals.
2-116
4191.Rev.A
Lattice~
!JJ
L1III Corporation
SemJronductor
Specifications GAL6001
SWITCHING WAVEFORMS
\\\\\\\ r-
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
l~tpd,.2~,
COMBINATORIAL
OUTPUT
\\\\\\\\\\\\\\\U~
Combinatorial Output
\ \\ \ \ \ rVAlID INPUT
'~lsu2
~\\\\\\
h2~U
roo-'-------
ICLK (REGISTER)
COMBINATORIAL
OUTPUT
INPUT or
110 FEEDBACK
OCLK
ICLK (LATCH)
100'1=
COMBINATORIAL
OUTPUT
Sum Term CLK
~-Registered Input
~-----
latched Input
\'\\\r
INPUT or
I/O FEEDBACK
. t ._t.:'_
VAliD INPUT
_-=>J~t
SumTermCLK
I \\\\\\
\\\\~~\\\\\\\\\\~'----
REGISTERED
OUTPUT
INPUT or
VO FEEDBACK
OCLK
REGISTERED
OUTPUT
Registered Output (Sum Term ClK)
Registered Output (OClK)
INPUT 01
I/O FEEDBACK
INPUT or
110 FEEDBACK
DRIVINGAR
OUTPUT
Input or I/O to Output Enable/Disable
REGISTERED
OUTPUT
SumTermCLK
ICLKor
OCLK
OCLK
SumTermCLK
Asynchronous Reset
Clock Width
2-117
4191.Rev.A
/ll~'
.l..J
Specifications GAL6001
('nporation
SWITCHING TEST CONDITIONS
.
GNDto 3.0V
Input Pulse Levels
3ns 10%-90%
Input Rise and Fall Times
1.SV
Input Timing Reference Levels
1.SV
Output Timing Reference Levels
Output Load
See Figure
3-state levels are measured O.SV from steady-state active
level.
FROM OUTPUT (0/0)
UNDER TEST
Output Load Conditions (see figure)
Test Condition
1
2
3
- -......- - - - TEST POINT
R2
R1
Fb
CL
300n
3900
SOpF
Active High
00
3900
SOpF
Active Low
300n
3900
SOpF
Active High
00
390n
SpF
Active Low
300n
3900
SpF
Cl
CL INCLUDES JIG AND PROBE TOTAL CAPACITANCE
2-118
4191.Rev)
I,
'Lattice~
fJJSemironductor
Specifications GAL6001
Corporation
I
ARRAY DESCRIPTION
The GAl6001 contains two E2 reprogram mabie arrays. The first
is an AND array and the second is an OR array. These arrays are
described in detail below.
BULK ERASE
Before writing a new pattern into a previously programmed part,
the old pattern must first be erased. This erasure is done
automatically by the programming hardware as part of the programming cycle and takes only 50 milliseconds.
ANDARRAY
The AND array is organized as 78 inputs by 75 product term
outputs. The 10 IlMCs, 10 IOlMCs, 8 BlMCfeedbacks, 10
OlMC feedbacks, and IClK comprise the 39 inputs to this array
(each available in true and complement forms). 64 product terms
serve as inputs to the OR array. The RESET product term
generates the RESET signal described in the Output and Buried
logic Macrocells section. There are 10 output enable product
terms which allow device pins 14-23 to be bi-directional or tri-state.
ORARRAY
The OR array is organized as 64 inputs by 36 sum term outputs.
64 product terms from the AND array serve as the inputs to the
OR array. Of the 36 sum term outputs, 18 are data ("0") terms
and 18 are enablelclock ("E") terms. These terms feed into the
10 OlMCs and 8 BlMCs, one "0" term and one "E" term to each.
The programmable OR array offers unparalleled versatility in
product term usage. This programmabili1Y allows from 1 to 64
product terms to be connected to a single sum term. A programmable OR array is more flexible than a fixed, shared, or
variable product term architecture.
ELECTRONIC SIGNATURE WORD
An electronic signature (ES) is provided with every GAl6001
device. It contains 72 bits of reprogram mabie memory that can
contain user defined data. Some uses include user 10 codes,
revision numbers, or inventory control. The signature data is
always available to the user independent of the state of the securitycell.
NOTE: The ES is included in checksum calculations. Changing
the ES will alter the checksum.
SECURITY CELL
A security cell is provided with every GAl6001 device as a deterrent to unauthorized copying of the array patterns. Once
programmed, this cell prevents further read access to the AND
and OR arrays. This cell can be erased only during a bulk erase
cycle, so the original configuration can never be examined once
this cell is programmed. The Electronic Signature is always
available to the user, regardless of the state of this control cell.
REGISTER PRELOAD
When testing state machine designs, all possible states and state
transitions must be verified, not just those required during normal
operations. This is because in system operation, certain events
may occur that cause the logic to assume an illegal state: powerup, brown out, line voltage glitches, etc. To test a design for proper
treatment of these conditions, a method must be provided to break
the feedback paths and force any desired state (Le., illegal) into
the registers. Then the machine can be sequenced and the
outputs tested for correct next state generation.
All of the registers in the GAl6001 can be preloaded, including
the IlMC, 10lMC, OlMC, and BlMC registers. In addition, the
contents of the state and output registers can be examined in a
special diagnostics mode. Programming hardware takes care of
all preload timing and voltage requirements.
LATCH-UP PROTECTION
GAl6001 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pull-ups to eliminate any
possibility of SCR induced latching.
INPUT BUFFERS
GAL devices are designed with m level compatible input buffers.
These buffers, with their characteristically high impedance, load
driving logic much less than traditional bipolar devices. This
allows for a greater fan out from the driving logic.
GAl6001 devices do not possess active pull-ups within their input
structures. As a result, lattice recommends that all unused inputs and tri-stated 1/0 pins be connected to another active input,
VCC' or GND. Doing this will tend to improve noise immunity and
reduce Icc forthe device.
2-119
4/91.Rev.A
~
flJ'Lattioo
e
Specifications GAL6001
SemkxJnducUJr
Corporation
POWER-UP RESET
Va;
IC~
OCLK
STC~
0"---~H~~~~~~~~~ / - - - - - - - - - - - - - - - - VALID CLOCK SIGNAL
VIL ~~"'-~...~"'-~~
INTERNAL REGISTER
RESET TO lOGIC 0
INTERNAL
REG. 0
FEEDBACK/EXTERNAL
REG. 0
OUTPUT
Circu~ry within the GAL6001 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs
set low after a specified time (tRESET , 45I1S). As a result, the state
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polar~ of the
output pins. This feature can greatly simplify state ·machine design
by providing a known state on power-up.
The timing diagram for power-up is shown above. Because of the
asynchronous nature of system power-up, some cond~ions must
be met to guarantee a valid power-up reset of the GAL6001. First,
the Vee rise must be monotonic. Second, the clock inputs must
become a proper TTL level within the specified time (tpR , 1001LS).
The registers will reset within a maximum of tREsET time. As in
normal system operation, avoid clocking the device until all input
and feedback path setup times have been met.
DIFFERENTIAL PRODUCT TERM SWITCHING (OPTS) APPLICATIONS
The number of Differential Product Term Switching (OPTS) for
a given design is calculated by subtracting the total number of
product terms that are switching from a logical HI to a Logical LO
from those switching from a logical LO to a logical HI within a
5ns period. After subtracting take the absolute value.
OPTS -
I(P-Terms)LH - (P-Terms)HL I
OPTS restricts the number of product terms that can be switched
2-120
simultaneously - there is no limit on the number of product terms
that can be used.
A software util~ is aV!lilable from Lattice Applications Engineering
that will perform this calculation on any GAL6001 JEOEC file. This
program, OPTS, and add~ional information may be obtained from
your local Lattice representative or by contacting Lattice
Applications Engineering Oept. (Tel: 503-681-0118 or 800FASTGAL; FAX: 681-3037).
4191.Rev.A
:LatUoo®
[JJ
~
ispGAL16Z8
SemiaJnducWr
Corporation
FEATURES
In-System Programmable
High Performance E2CMOS PlD
FUNCTIONAL BLOCK DIAGRAM
IN·SYSTEM·PROGRAMMABLE - 5·VOLTONLY
- Change Logic "On The Fly" In Seconds
- Non·volatlle E2 Technology
MINIMUM 10,000 ERASE/WRITE CYCLES
DIAGNOSTIC MODE FOR CONTROLUNG AND
OBSERVING SYSTEM LOGIC
HIGH PERFORMANCE E2CMOS- TECHNOLOGY
- 20 ns Maximum Propagation Delay
- Fmax = 41.6 MHz
- 90 mA MAX Icc
E2 CELL TECHNOLOGY
-100% Tested/Guaranteed 100% Yields
- 20 Year Data Retention
EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Also Emulates 2D-pin PAL- Devices with Full Func·
tlon/Fuse Map/Parametric Compatibility
PRELOAD AND POWER·ON RESET OF REGISTERS
- 100% Functional Testability
APPUCATIONS INCLUDE:
- Reconflgurable Interfaces and Decoders
- "Soft" Hardware (Generic Systems)
- Copy Protection and Security Schemes
- Reconflgurlng Systems for Testing
ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
PIN CONFIGURATION
rile Lattice ispGAL-16Z8 is a revolutionary programmable logic
levice featuring 5-volt only in-system programmability and in;ystem diagnostic capabilities. This is made possible by on-chip
:ircuitry which generates and shapes the necessary high voltIge programming signals. Using Lattice's proprietary UltraMOSechnology, this device provides true bipolar performance at
;ignificantly reduced power levels.
DIP
PLCC
_ 8~ "...g
u
z
..
24
! ~ ~
1/0/0
28
rhe 24-pin ispGAL 16Z8 is architecturally and parametrically
dentical to the 20-pin GAL 16V8, but includes 4 extra pins to
:ontrol in-system programming. These pins are not associated
'lith normal logic functions and are used only during programning and diagnostic operations. This 4-pin interface allows an
mlimited number of devices to be cascaded to form a serial
)rogramming and diagnostics loop.
1/0/0
UO/Q
1/0/0
UO/Q
NC
ispGAL16Z8
Top View
Vee
MODE
DClK
ispGAL
16Z8
UO/Q
NC
UO/Q
1/0/0
1/0/0
110/0
WO/Q
UO/O
WO/Q
00/0
SDO
SOl
Jnique test circuitry and reprogrammable cells allow complete
~C, DC, and functional testing during manufacture. Therefore,
-ATTICE is able to guarantee 100% field programmability and
unctionalily of all GAL- products.
GND
12
13
I/oE
:opyright CI991 Lattice Semiconductor Corp. GAL. E'CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Goneric Array Logic Is a trademark of Lanico Semlconduc·
"Corp. PAL Is a registerod trademark of Advanced Micro Dovlcos. Inc. The specifications and Information heroin are subject to change without notice.
.ATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro. Oregon 97124, U.S.A.
reI. (503) 681-0118 or 1-800-FASTGAL; FAX (503) 681-3037
2-121
April 1991.Rev.A
~tlice~
!IJCorporaUon
Semiconductor
Specifications ispGAL 16Z8
ispGAL 16Z8 ORDERING INFORMATION
Commercial Grade Specifications
Package
Tpd (na)
Tau (n8)
Tco (na)
lcc(mA)
20
15
15
90
ispGAL16Z8-20LP
24-Pin Plastic DIP
90
ispGAL16Z8-20LJ
28-Lead PLCC
90
ispGAL16Z8-25LP
24-Pin Plastic DIP
90
IspGAL16Z8-25LJ
28-Lead PLCC
25
20
15
Ordering'
PART NUMBER DESCRIPTION
xxxxxxxx - xx X X X
ispGAL16Z8
DevIce Name
~
1...-_ _ _
Speed (ns)
L = Low Power Power - - - - - - - - - '
2-122
Grade
Blank = Commercial
Package P = Plastic DIP
J = PLCC
4/91.Rev.A
Lattice
[jJ
1.J
Gl
Specifications ispGAL 16Z8
Semironducwr
Corporation
!
OUTPUT LOGIC MACROCELL (OLMC)
The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is
accomplished by development softwarelhardware and is completely transparent to the user.
There are three global OlMC configuration modes possible:
simple, complex, and registered. Details of each of these
modes is illustrated in the following pages. Two global bits, SYN
and ACO, control the mode configuration for all macrocells, the
XOR bit of each macrocell controls the polarity of the output in
any of the three modes, and the AC1 bit of each of the macrocells controls the inpuUoutput configuration. These two global
and 16 individual architecture bits define all possible configurations in an ispGAl16Z8. The information given on these architecture bits is only to give a better understanding of the device.
Compiler software will transparently set these architecture bits
from the pin definitions, so the user should not need to directly
manipulate these architecture bits.
The following is a list of the PAL architectures that the GAL16V8,
and therefore the ispGAl16Z8, can emulate. It also shows the
OlMC mode under which the ispGAl16Z8 emulates the PAL
architecture.
PAL Archltactur..
Emulated by IspGALl6Z8
IspGAL16Z8
Global OLMC Mode
16R8
16R6
16R4
l6RP8
16RP6
l6RP4
Reglstared
Reglslared
Reglslared
Reglalared
Reglstared
Registered
l61.8
l6HS
16P8
Complex
Complex
Complex
101.8
l2L6
l4L4
l6U
10HS
l2H6
l4H4
16H2
10P8
l2P6
l4P4
16P2
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
COMPILER SUPPORT FOR OLMC
Software compilers support the three different global OlMC
modes as different device types. These device types are listed
in the table below. Most compilers have the ability to automatically
select the device type, generally based on the register usage and
output enable (OE) usage. Register usage on the device forces
the software to choose the registered mode. All combinatorial
outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial without OE control. The different device types listed in the
table can be used to override the automatic device selection by
the software. For further details, refer to the compiler software
manuals.
The ispGAl16Z8 can be treated as a GAL16V8, and tools are
provided by lattice to use GAL 16V8 JEDEC files to program
ispGAl 16Z8 devices.
ABEL
CUPL
LOG/IC
OrCAD-PLD
PLDeslgner
TANGo.PLD
When using compiler software to configure the device, the user
must pay special attention to the following restrictions:
In registered mode pin'1 and pin 13 are permanently configured as clock and output enable, respectively. These pins cannot
be configured as dedicated inputs in the registered mode.
In complex mode pin 1 and pin 13 become dedicated inputs and
use the feedback paths of pin 22 and pin 15 respectively. Because of this feedback path usage, pin 18 and pin 19 do not have
the feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner-most pins ( pins
18 and 19) will not have feedback, as these pins are always
configured as dedicated combinatorial output. All macroceUs are
always either dedicated inputs or dedicated outputs in this mode.
Registered
Complex
Simple
Auto Mode Select
P16V8R
G16V8MS
GAL16V8 R
"Registered"'
P16V8R2
G16V8R
P16V8C
G16V8MA
GAl16V8 C7
"Complex"'
P16V8C2
G16V8C
P16V8S
G16V8S
GAL16V8 C8
"Simple"'
P16V8C2
G16V8AS3
P16V8
G16V8
GAl16V8
GAL16V8A
P16V8A
G16V8
1) Used with Configuration keyword.
2) Prior to Version 2.0 support.
3) Supported on Version 1.20 or later.
2-123
4191.Rev.A
~
!IJLattiOO1.J Corporation
SemironducWr
Specifications ispGAL 16ZB
REGISTERED MODE
In the Registered mode, macroceUs are configured as dedicated
registered outputs or as 1/0 functions.
this mode. Dedicated input or output functions can be Implemented as subsets of the I/O function.
Architecture configurations available in this mode are similar to
the common 16R8 and 16RP4 devices with various permutations of polarity, 110 and register placement.
Registered outputs have eight product terms per output. 1I0's
have seven product terms per output.
All registered macrocells share common clock and output enable control pins. Any macroceU can be configured as registered
or I/O. Up to eight registers or up to eight I/O's are possible in
The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are
shown on the logic diagram on the following page.
elK
Registered Configuration for Registered Mode
-SYN-O.
-ACO.1.
- XOR-O defines Active Low Output.
- XOR.1 defines Active High Output.
- AC1-0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 13 controls common OE for the registered outputs.
- Pin 1 & Pin 13 are permanently configured as CLK
and OE.
:. .....................................................
OE
_- .................................
·...........
·
..
Combinatorial Configuration for Registered Mode
-SYN-O.
-ACO.1.
- XOR.O defines Active Low Output.
- XOR",1 defines Active High Output.
- AC1.1 defines this output configuration.
- Pin 1 & Pin 13 are permanently configured as ClK
and OE.
~
....... -...............................................
Note: The development software configures aU of the architecture control bits and checks for proper pin usage automaticaUy.
2-124
4191.Rev.A
Lattice~
(jJ
~ Semiconductor
Specifications ispGAL 16Z8
Corporation
REGISTERED MODE LOGIC DIAGRAM
DIP (PLCC) Package Pinouts
1 (2)
.--..
......,
.......
0
4
8
12
16
20
24
28
PI~28
0000
~
3 (4)
.--..
'--"
...
-=-
0224
OLMC
22
XOR-2048
ACl-2120
0256
OLMC
4 (5)
=B=
0480
.--..
......,
21
XOR-2049
ACI-2121
0512
OLMC
5 (6)
.--..
'--'
...
0736
~
0768
6 (7)
-
20
I=E
......
-,..,
0992
~
XOR-2050
ACl-2122
OLMC
19
XOR-2051
ACI-2123
1024
OLMC
7 (9)
-c;,-
1248
.--..
'--"
18
XOR-2052
ACI-2124
1280
OLMC
8 (10)
-
1504
17
XOR-2053
ACI-2125
h
1536
-=go
9 (11)
a=
1760
.--..
......,
OLMC
16
XOR-2054
ACI-2126
1792
:Q::
10 (12)
.--..
'--'
..
go
~~
2016
I-FfR
64 USER SIGNATURE FUSES
M
S
B
OLMC
15
XOA-2055
ACl-2127
21 91
rJ D~
1
O~
IJ O~
l
0IJ 0"] 0IJ
01 0-........ OE
'-'
22 (26)
21 (25)
20 (24)
19 (22)
18 (21)
17 (20)
16 (19)
15 (18)
13 (16)
SYN-2192
ACO-2193
TC - 2194
l
S
B
2·125
4191_Rev_A
LatUce
[JJ
1...1
GP
Specifications ispGAL 16ZB
Semiconductor
Corporation
COMPLEX MODE
In the Complex mode, macrocells are configured as output only
or 1/0 functions.
pability. Designs requiring eight liO's can be implemented in the
Registered mode.
Architecture configurations available in this mode are similar to
the common 16L8 and 16P8 devices with programmable polarity
in each macrocell.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
13 are always available as data inputs into the AND array.
Up to six I/O's are possible in this mode. Dedicated inputs or
outputs can be implemented as subsets of the I/O function. The
two outer most macrocells (pins 15 & 22) do not have input ca-
The JEDEC fuse numbers including the UES fuses and PTD
fuses are shown on the logic diagram on the following page.
...............................................
'
,
Combinatorial 110 Configuration for Complex Mode
,,,
,,,
rl
~OA
- SYN=1.
-ACO.1.
- XOR ..Odefines Active Low Output.
- XOR-1 defines Active High Output.
-AC1=1.
- Pins 16 through Pin 21 are configured to this function.
........................................................,
,
f .... ·........ ······· . ·· . ·········· . ······ ......:
!
;
PeD
·
Combinatorial Output Configuration for Complex Mode
tL-o
XOR
t ...............................................!
- SYN-1.
-ACO.1.
- XOR=O defines Active Low Output.
- XOR=1 defines Active High Output.
-AC1=1.
- Pins 15 and Pin 22 are configured to this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
2-126
4191.Rev.A
tattice~
[JJ
..LJ Semiconducwr
Specifications ispGAL 16Z8
CorporaUon
COMPLEX MODE LOGIC DIAGRAM
DIP (PLCC) Package Pinouts
1 (2)
--
...
4
0
8
12
t6
20
24
28
p~2121
0000 _
3 (4)
--
0224
OLMC 22
==
~
=
ouo==
::8::::::
0512
.;:;
'-"
-
OLMC 21
XOR-20H
AC1- 212'
=
=
5 (6)
0736~
=
OLMC 20
XOR·20S0
AC,·2'22
0768
6 (7)
--
~
OLMC
0992=
-c-
,024 _
.n-
~
1248
719)
~
~
19
OLMC
18
XOR-2052
AC1-2'24
'-"
::
OLMC 17
=
, 504=
XOR·2053
AC'·2'25
D
1536
=
~
.....
1760 ::
9 (11)
~
'-'
OLMC 16
XOR-20S.
AC,·2126
1792
OLMC
2016
10 (12)
22 (26)
I.l.
.......
2, (25)
I!i::'
Ifl
D
15
XOR· 2055
AC'·2127
-
J-
n. .......I.l....
XOR·205'
AC,·2,23
'280 ....
8110)
.......
.'''0
0256
415)
I.l...
XOR-2048
AC
...........
h
U-
h ...
I.l...
I.l...
20 (24)
19 (22)
'8 (2')
--......
17 (20)
-C
'6(18)
-.......
15 (18)
.,....,
~
'3 (16)
2'91
U
USER SIGNATURE FUSES
··• .•
SYN-2192
ACO·2193
TC • 2194
,
2-127
4/91.Rev.A
[JJLattiOO*
.J..j
Specifications ispGAL 16Z8
Semiconductor
CorporaUon
SIMPLE MODE
In the Simple mode, macrocells are configured as dedicated inputs or as dedicated, always active, combinatorial outputs.
Architecture configurations available in this mode are similar to
the common 10L8 and 12P6 devices with many permutations
of generic output polarity or input choices.
Pins 1 and 13 are always available as data inputs into the AND
array. The center two macrocells (pins 18 & 19) cannot be used
in the input configuration.
The JEDEC fuse numbers including the UES fuses and PTD
fuses are shown on the logic diagram.
All outputs in the simple mode have a maximum of eight product terms that can control the logic. In addition, each output has
programmable polarity.
l·································· __ ····· __ ··
Combinatorial Output Configuration for Simple Mode
Vee
.
- SYN-1.
-ACO.O.
- XOR.O defines Active Low Output.
- XOR.1 defines Active High Output.
- AC1.0 defines this configuration.
- All OLMCs can be configured to this configuration.
- Pins 18 & 19 are permanently configured to this
function.
.
=---............................................................. .:
..- ............ ---- ............................
Dedicated Input Configuration for Simple Mode
- SYN.1.
-ACO.O.
- XOR.O defines Active Low Output.
- XOR.1 defines Active High Output.
- AC1.1 defines this configuration.
- All OLMCs except pins 18 & 19 can be configured to
this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
2-128
4/91.Rev.A
Lattice~
[J;j
.l.J Corporation
Semiconductor
Specifications ispGAL 16Z8
~
SIMPLE MODE LOGIC DIAGRAM
DIP (PLCC) Package Pinouts
1 (2)
.......
~
...
v
0
4
8
12162024
28
P~2128
0000
~
OLMC 21
0480
....
0512
;::;.
13=
D
XOR-2051
ACl-2123
0
1024
OLMC 18
1248
't:J=
1280
=
XOR-2052
ACl-2124
OLMC 17
XOR-2053
ACl-2125
rO
21 (25)
-
20 (24)
I.l -
19 (22)
IJ...
1-
v
IJ... -
18 (21)
IJ... .....
17 (20)
0
1536
OLMC 16
XOR-2054
ACl-2126
1760
9 (11)
1792
OLMC 15
XOR-2055
ACl-2127
2016
10 (12)
h...
0
1504
8 (10)
OLMC 20
OLMC 19
0992
7 (9)
22 (26)
0
0768
6 (7)
XOR-2049
ACl-2121
XOR-2050
ACl-2122
0736
5 (6)
IJ -
D0256
4 (5)
OLMC 22
XOR-2048
ACl-2120
0224
3 (4)
I
--
IJ... -
11... -.....
16 (19)
15 (18)
~
I".:)
I-
'--' 13 (16)
~
2191
64 USER SIGNATURE FUSES
., .,
•
SYN-2192
ACO-2193
TC - 2194
L
2-129
4/91_Rev_A
Latfice~
!lJ
.J"J CorporaUon
Semironductor
Specifications ispGAL 16Z8
Commercial
RECOMMENDED OPERATING CONDo
ABSOLUTE MAXIMUM RATINGS(1)
Ambient Temperature (TAl ............................. 0 to +75°C
Supply voltage (Veel
with Respect to Ground ..................... +4.75 to +5.25V
Supply voltage Voo ........................................ -0.5 to +7V
Input voltage applied ....................... -2.5 to Vee +1.0V
Off-state output voltage applied ........... -2.5 to Vee +1.0V
Storage Temperature .................................. -65 to 150°C
Ambient Temperature with
Power Applied ......................................... -55 to 125°C
1 . Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP."
MAX.
UNITS
-
0.8
V
Vee+1
V
-10
IlA
10
IlA
O.S
V
-
V
24
mA
VIL
Input Low Voltage
Vss-O.5
VIH
Input High Voltage
2.0
IlL
Input or 110 Low Leakage Current
OV S Y,N S V,l (MAX.)
-
-
IIH
Input or VO High Leakage Current
V,H S Y,N s Vee
-
-
VOL
Output Low Voltage
10L- MAX. Yin .. V,L or V,H
-
VOH
Output High Voltage
10H-.MAX. Yin
-
10L
=V,L or V,H
Low Level Output Current
10H
High Level Output Current
los'
Output Short Circuit Current
ICC
Operating Power Supply Current
Vee =SV
VOUT
VIL.O.SV
=O.SV
TA = 2S·C
-
-
-3.2
mA
-30
-
-1S0
mA
90
mA
-
VIH -3.0V
ftoggle .. 1SMhz
2.4
7S
Outputs Open
1) One output at a time for a maximum duration of one second. Vout .. O.SV was selected to avoid test problems caused by
tester ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vee .. SV and TA - 2S ·C
CAPACITANCE (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
Vee = S.OV, V, = 2.0V
ClIO
1/0 Capacitance
10
pF
Vee = S.OV. VIIO = 2.0V
"Guaranteed but not 100% tested.
2-130
4191.Rev.A
~tticeQD
!IJ
'L Corporation
Semironductor
Specifications ispGAL 16Z8
Commercial
AC SWITCHING CHARACTERISTICS
OVer Recommended Operating Conditions
PARAMETER
TEST
COND.'
·20
·25
MIN. MAX.
MIN. MAX.
DESCRIPTION
UNITS
tpd
1
Input or I/O to Combinational Output
3
20
3
25
ns
teo
1
Clock to Output Delay
2
15
2
15
ns
Setup lime, Input or Feedback before Clocki
15
20
33.3
-
41.6
-
tsu
th
1
Hold lime, Input or Feedback after Clocki
0
Maximum Clock Frequency with
1
Maximum Clock Frequency with
No Feedback
-
Clock Pulse Duration, High
12
twl3
Clock Pulse Duration, Low
ten
2
Input or 110 to Output Enabled
2
OE! to Output Enabled
3
Input or I/O to Output Disabled
3
OEi to Output Disabled
-
tdis
MHz
33.3
-
MHz
0
ns
ns
External Feedback, 1/(tsu + teo)
fmax 2
twh 3
28.5
-
15
12
-
-
20
20
-
18
-
18
-
15
ns
ns
25
ns
20
ns
25
ns
20
ns
I) Refer to Switching Test Conditions section.
2) Refer to fmax Description section.
3) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
GNDto3.0V
Input Rise and Fall limes
3ns 10%-90%
Input liming Reference Levels
+5V
1.5V
Output liming Reference Levels
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
eve!.
FROM OUTPUT (0/0)
UNDER TEST
:>utput Load Conditions (see figure)
Test Condition
1
2
200n
Active High
Active Low
3
RI
Active High
Active Low
R2
Rz
CL
-
390n
50pF
390n
50pF
-
390n
50pF
390n
5pF
390n
5pF
200n
200n
--+---......-
TEST POINT
Cl
CllNCLUDES JIG AND PR08E TOTAL CAPACITANCE
2·131
4/91.Rev.A
'Latlice~
~
.l..i Corporation
Semironductnr
Specifications ispGAL 16Z8
SWITCHING WAVEFORMS
\\\\\\\\\r;~
INPUT or
110 FEEDBACK
INPUT or
110 FEEDBACK
\\M""t"T\\\"'I""rT"'t:~\\il==
COMBINATORIAL
OUTPUT
CLK
t"T"'I'""T\\
\\""I"T"'<""S\
REGISTERED
OUTPUT
Combinatorial Output
Reg Istered Output
INPUT or
I/O FEEDBACK
OE
OUTPUT
Input or 110 to Output Enable/Disable
OUTPUT
OE to Output Enable/Disable
twl
ClK
Clock Width
fmax
DESCRIPTIONS
ClK
................................................................
LOGIC
ARRAY
REGISTER
LOGIC
ARRAY
10IIII/00II1---- to u ---t.~I04~-- leo--+l
fmax With No Feedback
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is cal·
culated from measured tsu and teo.
2-132
4/91.Rev.A
LattiOO~
[JJ
.l.J Semiconductor
Specifications ispGAL 16Z8
Corporation
I
ELECTRONIC SIGNATURE
OUTPUT REGISTER PRELOAD
An electronic signature (ES) is provided as part of the
ispGAL 16Z8 device. It contains 64 bits of reprogrammable memory that can contain user defined data. Some uses include user
10 codes, revision numbers, or inventory control. The signature
data is always available to the user independent of the state of
the security cell.
NOTE: The ES is included in checksum calculations. Changing the ES will alter the checksum.
SECURITY CELL
The security cell is provided on the ispGAL16Z8 device to prevent
unauthorized copying of the logic pattern. Once programmed,
this cell prevents further read access to the functional bits in the
device. The cell can only be erased by re-programming the
device, so the original configuration can never be examined once
this cell is programmed. Signature data is always available to
the user.
LATCH-UP PROTECTION
The ispGAL16Z8 devices are designed with an on-board charge
pump to negatively bias the substrate. The negative bias is of
sufficient magnitude to prevent input undershoots from causing
the circuitry to latch. Additionally, outputs are designed with nchannel pullups instead of the traditional p-channel pullups to
eliminate any possibility of SCR induced latching.
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because, in system
operation, certain events occur that may throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.).
To test a design for proper treatment of these conditions, a way
must be provided to break the feedback paths, and force any
desired (Le., illegal) state into the registers. Then the machine
can be sequenced and the outputs tested for correct next state
conditions.
The ispGAL 16Z8 devices include circuitry that allows each registered output to be synchronously set either high or low. Thus,
any state condition can be forced for test sequencing.
INPUT BUFFERS
The ispGAL16Z8 devices are designed with TIL level compatible
input buffers. These buffers, with their characteristically high impedance, load the driving logic much less than traditional bipolar
devices. Because the inputs are connected to a CMOS gate,
there is no inherent pull-up structure, as there is with bipolar devices. Therefore, they cannot be depended on to float high (or
to any particular state), and must be tied to the desired logic state.
Unused inputs and tri-stated I/Os should no.t be left floating.
Lattice recommends that they be connected to Vee, Ground, or
another driven input. Doing so will tend to increase noise immunity
and reduce Icc for the device.
TCCELL
The ispGAL16Z8 devices are equipped with a TC (Tri-State
Control) cell which controls the state of the outputs when the
device is being programmed. Since the device is programmed
while on the circuit board, and connected to other devices, the
state of the outputs is very important. Depending on how the TC
cell is programmed, the outputs will either be tri-stated or latched
upon entering the programming/diagnostic mode.
2-133
4/91.Rev.A
~
LattiOO~
[JJ
~ Semiconductor
Specifications ispGAL 16Z8
Corporation
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN~
Tri-S1ale
Control
I·~·;;·I
:CIr....
:
i................. .l
u
PIN
••
PIN
Feedback
(To Input BuHer)
Input
Output
POWER-UP RESET
Vee
ov
eLK
VIH
VALID CLOCK SIGNAl
VIL
INTERNAL
REGISTER
Q-OUTPUT
INTERNAL REGISTER
RESET TO LOGIC 0
OUTPUT PIN
Circuitry within the ispGAL 16Z8 provides a reset signal to all
registers during power-up. All internal registers will have their
Q outputs set low after a specified time (t AESIiT ' 45I1S MAX). As
a result, the state on the registered output PinS (if they are en-'
abled through OE) will always be high on power-up, regardless
of the programmed polarity 01 the output pins. This feature can
greatly simplify state machine design by providing a known state
on power-up.
2-134
The timing diagram for power-up is shown above. Because of
asynchronous nature 01 system power-up, some conditions must
be met to guarantee a valid power-up reset. First, the Vex; rise
must be monotonic. Second, the clock input must become a
proper TTL level within the specified time (~, 100ns MAX). The
registers will reset within a maximum 01 tRE~ET time. As in normal system operation, avoid clocking the device until all input
and feedback path setup times have been met.
4191.Rev.A
Section 1: Introduction to Generic Array Logic
Introduction to Generic Array Logic
1
1-1
Section 2: GAL Datasheets
Datasheet Levels
GAL16V8A1B
GAL20V8A1B
GAL18V10
GAL22V10/B
GAL26CV12
GAL20RA10
GAL6001
ispGAL16Z8
2
2-ii
2-1
2-25
2-47
2-61
2-81
2-95
2-109
2-121
Section 3: GAL Military Products
Military Program Overview
MIL-STD-883C Flow
Military Ordering Information
GAL 16V8A1B Military Datasheet
GAL20V8A Military Datasheet
GAL22V10/B Military Datasheet
GAL20RA 10 Military Datasheet
3-1
3-2
3-3
3-5
3-13
3-19
3-27
Section 4: Quality and Reliability
Quality Assurance Program
Qualification Program
FCMOS Testability Improves Quality
4-1
4-3
4-5
..
I
4
Section 5: Technical Notes
GAL Metastability Report
Latch-up Protection
5-1
5-17
5
6-1
6-7
6-9
6-13
6
7-1
7-3
7-5
7-8
7-9
7-16
7-17
7
Section 6: Article Reprints
Avoid the Pitfalls of High-Speed Logic Design
Extending the 22V1 0 EPLD
In-Circuit Logic Device Can be Reprogrammed on the Fly
Multiple Factors Define True Cost of PLDs
Section 7: General Information
Development Tools
Copyil\lg PAL, EPLD & PEEL Patterns into GAL Devices
GAL Product Line Cross Reference
Package Thermal Resistance
Package Diagrams
Tape-and-Reel Specifications
Sales Offices
3-i
3-ii
Military Program
OvelView
CORPORATE PHILOSOPHY
Lattice Semiconductor is committed to leadership in
performance and quality. Our family of military GAL
devices is consistent with this philosophy. Lattice
manufactures all devices under strict Quality Assurance
guidelines. All grades, Commercial through Military 883C,
are monitored under a quality program conformant to M ILM-3851 0 Appendix A with inspections conformant to MIL1-45208.
MIL-STD-883C COMPLIANCE
MIL-STD-883C provides a uniform and precise method
for environmental, mechanical and electrical testing which
ensures the suitability of microelectronic devices for use
in military and aerospace systems. Table I summarizes
the MIL-STD-883C, Class B flow. Table /I summarizes
the conformance testing required by MIL-STD-883C,
Method 5005, for quality conformance testing of Lattice
military microcircuits.
Lattice Semiconductor has been manufacturing GAL
devices since 1984. The engineering analysis and
characterization during this time has been focused into
our current design, process and manufacturing test
procedures to assure superior product which meet all
datasheet and quality goals.
MIL-M-38510
MIL-M-3851 0, when used in conjunction with MIL-STD883C, defines design, packaging, material, marking,
sampling, qualification and quality system requirements
for military devices.
Complete review of the procedures and technical data
can be arranged at our facility near Portland, Oregon.
Factory audits of our documentation and processes are
also welcomed.
QUALITY AND TESTABILITY
Lattice Semiconductor processes its GAL devices to strict
conformance with MIL-STD-883C Class B. In conjunction
with the military flow, the inherent testability of E2CMOS
technology allows Lattice to achieve a quality level superior
to other PLD technologies.
All GAL devices are patterned and tested dozens of times
throughout the manufacturing flow. Every GAL device is
tested under worst case configurations to assure
customers achieve 100% yields. Tests are performed
using the same E2 cell array that will be used for the final
patterning of the devices. This 100% "actual test"
philosophy does away with the correlated and simulated
testing that is necessary with bipolar and UV (EPROM)
based PLD devices.
RELIABILITY
Lattice Semiconductor performs extensive reliability testing
prior to product release. This testing continues in the form
of Reliability Monitors that are run on an ongoing basis to
assure continued process integrity. A formal, written
report of these test results is updated regularly and can be
obtained from your local Lattice Sales Representative.
The reliability testing performed includes extensive analysis
of fundamental design and process integrity. The
reprogrammable nature of GAL devices allows for an
inherently more thorough reliability evaluation than other
programmable alternatives.
3-1
III
I
GROUP DATA
Group A and B data is taken on every inspection lot per
MIL-STD-883C, Class B requirements. This data, along
with Generic Group C and D data can be supplied, upon
written request, with your device shipment. Your Lattice
sales representative can advise you of charges and
leadtime necessary for providing this data.
STANDARD MILITARY DRAWINGS
Lattice actively supports the DESC Standard Military
Drawing (SMD) Program. The SMD Program offers a cost
effective alternative to source control drawings and
provides standardized MIL-STD~883C product
specifications to simplify military procurement.
Lattice recognizes the growing demand for SMD qualified
devices, and in response, all new 883C product released
by Lattice will be submitted to DESC for SMD qualification.
Customers may facilitate this process by submitting a
"Nonstandard Part Approval Request", DD Form 2052, to
DESC. This form allows you to recommend to DESC the
qualification of Lattice devices to SMD status.
A list of currently available SMD qualified devices is
provided (see Military Ordering Information). Contact
your local Lattice sales representative forthe latest status
of SMD qualifications in process with DESC.
Military Program Overview
MILITARY QUALITY CONFORMANCE
INSPECTIONS (TABLE II)
MILIT ARY SCREENING FLOW
(TABLE I)
I
Screen
Method
Requirement
Internal Visual
Temp. Cycling
Constant Acceleration
Hermeucity
Fine
Gross
Endurance Test
Retention Test
2010 Cond. B
1010Cond. C
2001 Condo E
1014
Cond.AorB
Cond.C
1033
Unbiased Bake
48 HRS.
TA= 150°C
Applicable Device
Specification
Tc= 2500
1015Cond. D
Applicable Device
Specification
Tc = 2500
PDA=5%
Applicable Device
Specification
Tc= 125°C
Applicable Device
Specification
Tc = -5500
2009
MIL-M-38510H
Sec. 4.5 and
MIL-STD-883C
Sec. 1.2
100%
100%
100%
100%
Pre Bum-In Electrical
Dynamic Bum-In
Post Bum-In Electrical
Final Electrical Test
Final Electrical Test
External Visual
CCI Sample Selection
Subgroup
Subgroups " 7, 9
Electricel Test
Subgroups 2, 8A, 10
Electrical Test
Subgroups 3, 88, 11
Electrical Test
100%
100%
I
Sample
Applicable Device Spec.
25°C
Applicable Device Spec.
Max. Operating Temp.
Applicable Device Spec.
Min. Operating Temp.
LTPD = 2
LTPD= 2
LTPD=2
GROUP B: Mechanical Tests
Subgroup 2
Solvent Resistance
Subgroup 3
Solderability
Subgroup 5
Bond Strength
100%
100%
100%
Method
I GROUP A: Electrical ests
4(0)
2015
LTPD=10
2003
LTPD= 15
2011
I GROUP C: Chip Integrity Tests
Subgroup 1
Dynamic Ufe Test
End Point Electrical
Subgroup 2
Unbiased Retention
End Point Electrical
100%
1005,1,000 HRS. 12500
Applicable Device Spec.
LTPD=5
1,000 HRS. 150·C
Applicable Device Spec.
LTPD=5
GROUP D: EnvironmentallntearHv
100%
Subgroup 1
Physical Dimensions
Subgroup 2
Lead Integrity
Hermeticity
Subgroup 3
Thermal Shock
Temp. Cycle
Moisture Resistance
Hermeticity
Visual Examination
Endpoint Electrical
Subgroup 4
Mechanical Shock
Vibration
Constant Acceleration
Hermeticity
Visual Examination
Endpoint Electrical
Subgroup 5
Salt Atmosphere
Hermeticity
Visual Examination
SubgroupS
Intemal Water Vapor
Subgroup 7
Lead Finish Adhesion
Subgroup 8
Lid Torque
100%
Sample
3-2
LTPD= 15
2016
LTPD=5
2004, Condo B
1014
LTPD= 15
1011, Condo B, 15 Cycles
1010, Condo C, 100 Cycles
1004
1014
1004, 1010
Applicable Device Spec.
LTPD = 15
2002,Cond.B
2007,Cond.A
2001, Cond. E
1014
1010, 1011
Applicable Device Spec.
LTPD = 15
l009,Cond.A
1014
1009
3(0)
1018 < 5,000 PPM, loo·C
LTPD=15
2025
5(0)
2024
Military Ordering
InfolJnation
Lattice offers the most comprehensive line of military
E2CMOS Programmable Logic Devices. Lattice
,ecognizes the trend in militarydeviceprocurementtowards
JsingSMDcompliantdevicesandencouragescustomers
to use the SMD number, where it exists, when ordering
parts. Listed below are Lattice's military qualified devices
and their corresponding SMD numbers. Please contact
your local Lattice representative for the latest product
listing.
Military Products Selector Guide
DEVICE TYPE
(mA)
10
130
15
20
GAL16V8
25
30
15
20
GAL20V8
25
30
15
20
GAL22V10
25
30
20
GAL20RA10
Icc
Tpd
(n8)
25
PACKAGE
LATTICE PART #
SMD#
20-Pin CEROIP
GAL 16V8B-l OLOI883C
5962-8983904RA
130
20-Pin LCC
GAL16V8B-l OLRl883C
5962-89839042A
130
2O-Pin CEROIP
GAL 16V8A-15LOI883C
5962-8983903RA
130
20-Pin LCC
GAL 16V8A-15LRI883C
5962-89839032A
65
20-Pin CEROIP
GAL 16VBA-2000/BB3C
5962-8983906RA
65
20-Pin LCC
GAL 16VBA-200Rl883C
5962-89839062A
130
20-Pin CEROIP
GAL 16VBA-20LOI883C
5962-8983902RA
130
20-Pin LCC
GAL 16V8A-20LRl883C
5962-89839022A
65
20-Pin CERDIP
GAL 16V8A-25001883C
5962-8983905RA
65
2O-Pin LCC
GAL 16V8A-250Rl883C
5962-89839052A
130
20-Pin CERDIP
GAL 16V8A-30LOI883C
5962-8983901RA
130
20-Pin LCC
GAL 16V8A-30LRl883C
5962-89839012A
130
24-Pin CERDIP
GAL2OV8A-15LOI883C
5962-8984003LA
130
28-Pin LCC
GAL20VBA-15LRlB83C
5962-89840033A
65
24-Pin CERDIP
GAL2OVBA-2000/883C
Contact Factory
65
28-Pin LCC
GAL2OVBA-200RlBB3C
Contact Factory
130
24-Pin CERDIP
GAL2OV8A-20LD/B83C
5962-8984002LA
130
28-Pin LCC
GAL2OVBA-20LRlB83C
5962-89840023A
65
24-Pin CEROIP
GAL2OVBA-2500/BB3C
Contact Factory
65
28-Pin LCC
GAL2OV8A-250RI8B3C
Contact Factory
130
24-Pin CEROIP
GAL2OV8A-30LD/B83C
5962-8984001 LA
130
28-Pin LCC
GAL2OV8A-30LRl883C
5962-89840013A
150
24-Pin CERDIP
GAL22Vl0B-15LO/BB3C
5962-8984103LA
150
28-Pin LCC
GAL22V10B-15LR1883C
5962-89841033A
150
24-Pin CEROIP
GAL22V10-20L01883C
5962-8984102LA
150
28-Pin LCC
GAL22V10-20LRI883C
5962-89841023A
150
24-Pin CEROIP
GAL22V10-25LDI883C
5962-8984104LA
150
28-Pin LCC
GAL22V10-25LRlB83C
5962-89841043A
150
24-Pin CEROIP
GAL22Vl0-30LOI883C
5962-B984101 LA
150
28-Pin LCC
GAL22Vl0-30LRlB83C
5962-89841013A
120
24-Pin CEROIP
GAL20RA 10-20L0/883C
Contact Factory
120
28-Pin LCC
GAL20RA 10-20LRlB83C
Contact Factory
120
24-Pin CEROIP
GAL20RA 10-25LO/B83C
Contact Factory
120
2B-Pin LCC
GAL20RA 10-25LRI883C
Contact Factory
3-3
I:
Military Ordering Infonnation
DESC Standard Military Drawing Listing
SMD#
LATTICE PART #
5962-89839012A
~L16VSA~LRV883C
5962-8983901 RA
5962-89839022A
LATTICE PART,
SMD#
5962-8984001 LA
~l2OVaA~LDI883C
~L 16VSA~LD1883C
5962-89840023A
~l2OVSA-20LRI883C
~L 16VaA-20LRV883C
5962-8984002LA
~l2OVSA-20LD1883C
5962-8983902RA
~L 16VSA-20LD1883C
5962-8984OO33A
~l2OVSA-15LRI883C
5962-89839032A
~L 16VaA-15LRI883C
5962-8984003LA
~l2OVSA-15LDI883C
5962-8983903RA
~L 16VSA-.15LD1883C
5962-89841013A
~l22V1 0-30LRI883C
5962-89839042A
~L 16VSB-10LRl883C
5962-8984101 LA
~L22V1 O-30LDI883C
5962-8983904RA
~L16VSB-10LD1883C
5962-89841023A
~L22V1 O-20LRI883C
5962-S9839052A
~L 16VaA-25QRV883C
5962-8984102LA
~l22V1 O-20LDI883C
5962-8983905RA
~L 16VaA-25QDI883C
5962-89841033A
~L22V10B-15LR1SS3C
5962-S9839062A
~L 16VSA-2OQRV883C
5962-8984103LA
GAL22V10B-15LDI8S3C
5962-8983906RA
~L 16VaA-2OQD1883C
5962-89841043A
~L22V1 0-25LRI883C
5962-89840013A
~L20VSA~LRI883C
5962-8984104LA
~L22V1 0-25LD1883C
Standard Military Drawing Number Description
f
Lead Finish
• A = Solder dipped
Package Type
R = 2O-1ead CERDIP
L ~ 24-lead CERDIP
2 - 2O-pin LCC
3 = 28-pin LCC
Device Type
Drawing Number
• no other lead finish aJrrently available.
3-4
!IJ
l.J
:Lattice®
GAL 16V8BI883C
GAL 16V8AI883C
Semiconductor
Corporation
High Performance E2CMOS PLD
FUNCTIONAL BLOCK DIAGRAM
FEATURES
v~
• HIGH PERFORMANCE EICMOS- TECHNOLOGY
-10 ns Maximum Propagation Delay
- Fmax =62.5 MHz
- 7 ns Maximum from Clock Input to Data Output
- TTL Compatible 24 mA Outputs
- UltraMOS- Advanced CMOS Technology
20
J
19
2
18
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
- 7SmA 1\'p Icc on Low Power Device
- 4SmA Typ Icc on Quarter Power Device
3
..
17
• ACTIVE PULL·UPS ON ALL PINS (GAL16V8B)
4
• EI CELL TECHNOLOGY
- Reconflgurable Logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention
16
15
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum FlexlbllHy for Complex logic Designs
- Programmable Output Polarity
- Also Emulates 2()..pln PAL- Devices with Full Func·
tlon/Fuse Map/Parametric Compatibility
14
7
13
• PRELOAD AND POWER·ON RESET OF ALLREGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Stand,ard Logic Speed Upgrade
12
11
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
PIN CONFIGURATION
The GAL16V8B1883C and GAL16V8A1883C are high performance E2CMOS programmable logic devices processed in full
compliance to MIL-STD-883C. These military grade devices
combine a high performance CMOS process with Electrically
Erasable (E2) floating gate technology to provide the highest
speed/power performance available in the 883C qualified PLD
market. The GAL16V8B1883C, at 1Ons maximum propagation
delay time, is the world's fastest military qualified CMOS PLD.
CMOS circuitry allows the GAL 16V8A quarter power devices to
consume just 45mA typical Icc, which represents a 75% savings
in power when compared to bipolar counterparts.
CERDIP
LCC
IICLK
Vee
IIOIQ
I
K:LK Voo
rotQ
1/010
10
rotQ
Generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL 16V8A1883C and GAL16V8B/883C are
capable of emulating all standard 20-pin PAL- devices with full
functionlfuse map/parametric compatibility.
I
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. Therefore,
Lattice guarantees 100% field programmability and functionality
of all GAL products. Lattice also guarantees 100 erase/rewrite
cycles and that data retention exceeds 20 years.
IIOIQ
VOIQ
IIOIQ
GAL16V8A1B
VOIQ
110/0
Top View
rotQ
IIOIQ
VOIQ
IIOIQ
IIOIQ
GND rOE VOIQ VOIQ
GND
v6E
Copyright CI991 Lattice Semiconductor Corp, GAl, E'CMOS and UhraMOS are registered trademarks 01 Lattice SemiconduC1or Corp. Generic Array Logic is a trademark 01 Lattice Semiconduc·
tor Corp. PAL Is a registered trademark 01 Advanced Micro Devices. Inc. The specifications and Information herein are subject to chango wtthout notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503)681-3037
3·5
April 1991.Rev.A
tatUoo*
[lJ
LJ
Specifications GAL 16V8B 1883C
Semironductor
Corporation
RECOMMENDED OPERATING CONDo
ABSOLUTE MAXIMUM RATINGS(1)
Case Temperature (Tc> .............................. -55 to 125°C
Supply voltage (Vex;l
with Respect to Ground ...................... +4.50 to +5.50V
Supply voltage Vex; .......................................-0.5 to +7V
Input voltage applied .•............•..•......... -2.5 to Vex; +1.0V
Off-state output voltage applied .......... -2.5 to Vex; +1.0V
Storage Temperature ................................. -65 to 150°C
Case Temperature with
Power Applied ........................................-55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming. follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
VIL
Input Low Voltage
Vss-O.5
VIH
Input High Voltage
2.0
IlL'
Input or 110 Low Leakage Current
OV S VIN S VIL (MAX.)
IIH
Input or 110 High Leakage Current
3.SV S VIN S Vee
VOL
Output Low Voltage
1oL= MAX. Yin = VIL or VIH
VOH
Output High Voltage
10H = MAX. Yin = VIL or VIH
10L
Low Level Output Current
10H
High Level Output Current
los2
Output Short Circuit Current
Icc
Operating Power Supply Current
MIN.
CONDITION
Vee-SV VOUT .. O.SV
TYP.·
MAX.
UNITS
-
0.8
V
VCC+1
V
-
-100
~
10
~
-
-
0.5
V
2.4
-
-
V
-
-
12.
mA
-
-
-2
mA
-30
-
-150
mA
-
75
130
mA
-
T,,_2So C
VIL= O.SV VIH =3.0V ftoggle = 25 MHz
Outputs Open (no load)
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = O.SV was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee .. SV and TA .. 25 °C
CAPACITANCE (TA
=25°C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
CI
Input Capacitance
10
pF
Vcc. S.OV. VI = 2.0V
Coo
110 Capacitance
10
pF
Vcc =S.OV. V110 .. 2.0V
'Guaranteed but not 100% tested.
3-6
4191.Rev.A
tattiooGP
[IJ
'L
Specifications GAL 16VBB I883C
Semironductor
Caporat/oo
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER
TEST
COND'.
·10
DESCRIPTION
MIN. MAX.
UNITS
tpd
1
Input or 110 to Combinational Output
2
,0
ns
teo
1
Clock to Output Delay
1
7
ns
tcf2
-
tsu
th
fmax 3
Clock to Feedback Delay
-
7
ns
Setup 1ime, Input or Feedback before Clockt
10
-
ns
Hold 1ime, Input or Feedback after Clockt
ns
Maximum Clock Frequency with
External Feedback, 1/(tsu + teo)
58.8
-
MHz
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tel)
58.8
-
MHz
1
Maximum Clock Frequency with
No Feedback
62.5
-
MHz
twh4
-
Clock Pulse Duration, High
8
twl'
-
Clock Pulse Duratioo, Low
8
ten
2
Input or 110 to Output
2
OEJ.. to Output
tdis
-
0
1
3
Input or 110 to Output
3
OEt to Output
-
-
-
ns
ns
10
ns
10
ns
10
ns
10
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall1imes
Input 1iming Reference Levels
Output 1iming Reference Levels
+5V
GNDto 3.0V
3ns 10%-90%
1.5V
1.5V
Output Load
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (0/0)
UNDER TEST
- - - + - - - + - TEST POINT
Output Load Conditions (see figure)
Test Condition
1
2
3
Active
Active
Active
Active
High
Low
High
Low
Rl
R2
CL
3900
7500
7500
7500
7500
7500
50pF
50pF
50pF
5pF
5pF
co
3900
co
3900
R2
~
....L.
-
Cl
T
CllNClUOES JIG AND PROSE TOTAL CAPACITANCE
3-7
4/91.Rev.A
!IJ
'Lattice
l..I Semlconductnr
GD
Specifications GAL 16VBA 1883C
Corporation
RECOMMENDED OPERATING CONDo
ABSOLUTE MAXIMUM RATINGS(1)
CaseTemperature (Tc) ............................... ~55 to 125°C
Supply vohage (Vee)
with Respect to Ground ...................... +4.50 to +5.50V
Supply vohage Vee ....................................... -0.5 to +7V
Input vohage applied ........................... -2.5 to Vee +1.0V
Off-state output voltage applied .......... -2.5 to Vee +1.0V
Storage Temperature .................................-65 to 150°C
Case Temperature with
Power Applied '" ..................................... -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specHications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
VIL
Input Low Voltage
VIH
Input High
CONDITION
MIN.
TYP.2
MAX.
UNITS
Vss-O.5
-
0.8
V
VcC+1
V
-10
IlA
10
J.LA
IlL
Input or VO Low Leakage Current
OV S VIN S Vil (MAX.)
-
IIH
Input or VO High Leakage Current
VIH S VIN s Vee
-
-
VOL
Output Low Voltage
10l = MAX. Vin .. Vil or VIH
-
-
0.5
V
VOH
Output High Voltage
10H '" MAX. Vin = Vilor VIH
2.4
-
V
12
mA
-2.0
mA
mA
Vo~age
2.0
10H
High Level Output Current
-
-
los'
Output Short Circuit Current
Vcc=5V VOUT = 0.5V TA= 25'C
-30
-
-150
Icc
Operating Power Supply Current
Vll .. 0.5V VIH= 3.0V
-
75
130
mA
-
45
65
mA
10L
-
Low Level Output Current
L -15/-201-30
Outputs Open (no load) Q -201-25
ftoggle = 25MHz
1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground
degradation. Guaranteed but not 100% tested.
2) Typical values are at Vcc .. 5V and TA'" 25 ·C
CAPACITANCE (TA
=25°C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM"
UNITS
TEST CONDITIONS
C,
Input Capacitance
10
pF
Vee'" 5.0V, V," 2.0V
ClIO
1/0 Capacitance
10
pF
Vee" 5.0V, VIIO " 2.0V
"Guaranteed but not 100% tested.
3-8
4/91.Rev.A
tattiOOs
fjJ
L.;
Specifications GAL 16VBA 1883C
Semironducwr
Corporation
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
'ARAMETER
-20
-15
TEST DESCRIPnON
COND'.
-25
-30
MIN. MAX MIN. MAX. MIN. MAX. MIN. MAX.
3
15
Clock to Output Delay
2
-
tsu
-
Clock to Feedback Delay
Setup lime, Input or Feedback before Clocki
12
th
-
Hold lime, Input or Feedback after Clocki
0
tpd
1
Input or I/O to Combinational Output
teo
1
tcf2
3
20
12
2
15
12
-
15
-
15
20
33.3
-
UNITS
3
25
3
30
ns
2
15
2
20
ns
15
-
20
ns
25
22.2
-
ns
28.5
-
MHz
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + teo)
41.6
-
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tet)
41.6
-
33.3
-
28.5
-
22.2
-
MHz
1
Maximum Clock Frequency with
No Feedback
50
-
41.6
-
33.3
-
33.3
-
MHz
-
Clock Pulse Duration, High
10
-
15
15
-
15
-
ns
10
-
15
Clock Pulse Duration, Low
-
12
twl'
ten
2
Input or I/O to Output
-
15
20
-
25
-
30
ns
2
OE.!. to Output
-
15
-
18
-
20
25
ns
25
-
30
ns
20
-
25
ns
fmax 3
twh4
tdis
3
Input or 110 to Output
3
OEi to Output
0
15
15
12
0
20
18
0
ns
ns
I Refer to Switching Test Conditions section.
I Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
I Refer to fmax Descriptions section.
I Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall limes
Input liming Reference Levels
Output liming Reference Levels
GNDto 3.0V
3ns 10%-90%
1.5V
1.5V
Output Load
+5V
See Figure
·state levels are m~asured 0.5V from steady·state active
vel.
'utput Load CondHlons (see figure)
Test Condition
1
2
3
Active High
Active Low
Active High
Active Low
RI
R2
CL
3900
750.Cl
7500
750.Cl
750.Cl
750.Cl
50pF
50pF
50pF
5pF
5pF
00
3900
00
390.Cl
FROM OUTPUT (010)
UNDER TEST
---+----+-TEST POINT
R2
CL
CLlNCLUOES JIG AND PROBE TOTAL CAPACITANCE
3-9
4191.Rev.A
tattiooGP
[JJ
.lJ
SemJronductor
Corporation
Specifications GAL 16V8BI883C
GAL 16VBA 1883C
SWITCHING WAVEFORMS
INPUT or
VOFEEDBACK
ClK
INPUT or
VOFEEDBACK
REGISTERED
OUTPUT
COMBINATORIAL
OUTPUT
Combinatorial Output
Registered Output
INPUT or
VOFEEDBACK
OE
OUTPUT
OUTPUT
OE to Output Enable/Disable
Input or 110 to Output Enable/Disable
ClK
ClK
REGISTERED
FEEDBACK
Clock Width
fmax with Feedback
3-10
4191.Rev.
~ttice4D
[JJ
.l..J Semironductor
Specifications GAL 16V8B 1883C
GAL 16VBA I883C
Corporation
fmax DESCRIPTIONS
r· . · ·. ··········. .·········. .· . · . . . . . . . . ..
ClK
elK
.........................................................
,
,
lOGIC
ARRAY
;
I
REGISTER
REGISTER
I
1<11.....---- hu--....,.~I......i - - - - Ico~
D
,
,
.....................................................
fmax with External Feedback 1/(1su+tco)
i'I~I----- lei ------1~~1
Note: fmax with external feedback is calculated from measured
tsu and tco,
!
,..141-----lpd-------1~~1
fmax with Inlernal Feedback 1/(1su+tcf)
Note: tel is a calculated value, derived by
subtracting tsu from the period of fmax wI
internal feedback (tcf - 1/fmax - tsu), The
value of tcf is used primarily when calculating the
delay from clocking a register to a combinatorial output (through registered feedback), as
shown above. For example, the timing from
clock to a combinatorial output is equal to tel +
tpd.
ClK
I······~~~~:,·············~,..,,~,~······I
~
........... _.......... -.......... -..... _- ............................. _.........'
fmax Without Feedback
Note: fmax with no feedback may be less than 111wh + twl this
is to allow for a clock duty cycle of other than 50%.
3-11
4/91.Rev.A
'LattJce~
[j:J
L.J Semironductor
Specifications GAL 16V8B 1883C
GAL 16VSA I883C
Corporation
GAL 16V8A/B ORDERING INFORMATION (MIL-STD-883C and SMD)
Ordering #
Tpd
(ns)
Tsu
(ns)
Teo
(ns)
10
10
7
15
20
25
30
12
15
20
25
12
15
15
20
Icc
(rnA)
MIL-STD-883C
Package
SMD#
130
2O-Pin CERDIP
GAL16VSB-l0LD/883C
5962-8983904RA
130
2O-Pin LCC
GAL 16VSB-l0LRI883C
5962-89839042A
130
2O-Pin CERDIP
GAL 16VSA-15LDl883C
5962-8983903RA
130
2O-Pin LCC
GAL 16VSA-15LRl883C
5962-89839032A
65
2O-Pin CERDIP
GAL 16VSA-200D/S83C
5962-8983906RA
65
2O-Pin LCC
GAL 16VSA-2OQR/883C
5962-89839062A
130
2O-Pin CERDIP
GAL 16VSA-20LDi883C
5962-8983902RA
130
2D-Pin LCC
GAL 16VSA-20LRI883C
5962-89839022A
65
2D-Pin CERDIP
GAL 16VSA-250D/S83C
5962-8983905RA
65
2D-Pin LCC
GAL 16VSA-250Rl883C
5962-S9839052A
130
2D-Pin CERDIP
GAL 16VSA-3OLD/883C
5962-S983901 RA
130
2D-Pin LCC
GAL 16VSA-3OLRl883C
5962-89839012A
Note: Lattice recognizes the trend in military device procurement towards using SMD
compliant devices, as such, ordering by this number where it exists is recommended.
PART NUMBER DESCRIPTION
xxxxxxxx - xx X X X
GAL16V8A
GAL16V8B
Dov"'N.me~
L..-___
Speed (n8) _ _ _ _ _ _...J
L = Low Power Power - - - - - - - - - - - '
Q = Quarter Power
3-12
MIL Process 1883C = 883C Process
' - - - - - - Package
D = CERDIP
R=LCC
4/91.Rev.A
Lattice~
!JJ
.l.J Corporation
Semiconductor
FEATURES
GAL20V8AI883C
High Performance E2CMOS PLD
Generic Array Loglc™
FUNCTIONAL BLOCK DIAGRAM
• HIGH PERFORMANCE EICMOS· TECHNOLOGY
- 1S ns Maximum Propagation Delay
- Fmax =SO MHz
- 12 ns Maximum from Clock Input to Data Output
- TTL Compatible 24 mA Outputs
- UltraMOS· Advanced CMOS Technology
• SO% to 7S% REDUCTION IN POWER FROM BIPOLAR
- 7SmA Typ I..on Low Power Device
- 4SmA Typ I..on Quarter Power Device
• EI CELL TECHNOLOGY
-
Reconflgurable Logic
Reprogrammable Cells
100% Tested/Guaranteed 100% Yields
High Speed Electrical Erasure «SOms)
20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Also Emulates 24-pln PAL· Devices with Full Function/Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
PIN CONFIGURATION
DESCRIPTION
The GAL20V8A1883C is a high performance E2CMOS programmable logic device processed in full compliance to MIL-STD883C. The GAL20V8A1883C, at 15ns maximum propagation
delay time, is the world's fastest military qualified 24-pin CMOS
PLD. CMOS circuitry allows the GAL20V8A quarter power
device to consume just 45mA typical Icc, which represents a
75% savings in power when compared to bipolar counterparts.
Generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL20V8A1883C is capable of emulating all
standard 24-pin PAL· devices with full functionlfuse map/parametric compatibility.
CERDIP
LCC
Vee
!S
~
!l
Z
UH
II
> _
;
IIOIQ
~OIO
IIOIQ
~OIO
GAL20V8A
NC
Unique test circuitry and reprogram mabie cells allow complete
AC, DC, and functional testing during manufacture. Therefore,
Latticeguarantees 100% field programmability and functionality
Jf all GAL products. Lattice also guarantees 100 erase/rewrite
::yeles and that data retention exceeds 20 years.
Top View
IIO/Q
WOIO
NC
IIO/Q
WOIO
IIOIQ
WOIO
IIOIQ
~o(Q
IIO/Q
Ii"
!llg - ;
IIO/Q
GND
::cpyright Cll991 Lanice SemioonduClor Corp. GAL. E'CMOS and UhraMOS are registered trademarks of Lani.. Semiconductor Corp. Generic Alrar logic is a trademark of Lanice Senioonduc·
or Corp. PAL is a registered trademark of Advanced Micfo Devlcas. inc. The specifications and informetion heroin are subject to change without notice.,
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-800-FASTGAL; FAX (503)681-3037
3-13
April 1991.Rev.A
Specifications GAL20V8AI883C
RECOMMENDED OPERATING CONDo
ABSOLUTE MAXIMUM RATINGS(1)
CaseTemperature (Te) ............................... -55 to 125°C
Supply voltage (V00)
with Respect to Ground ...................... +4.50 to +5.50V
Supply voltage V00 ....................................... -0.5 to +7V
Input voltage applied ........................... -2.5 to V00 +1.0V
Off-state output voltage applied .......... -2.5 to V00 +1.0V
Storage Temperature ................................. -65 to 150°C
Case Temperature with
Power Applied •....................................... -55 to 125°C
1.Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming. follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
PARAMETER
CONDITION
MIN.
TYP}
MAX.
UNITS
0.8
V
VcC+1
V
-10
IlA
VIL
Input Low Voltage
Vss-O.5
VIH
Input High Voltage
2.0
-
ilL
Input or I/O Low Leakage Current
OV S Y,N S V,L (MAX.)
-
-
Input or I/O High Leakage Current
V,H S Y,N S Voo
-
-
10
IlA
VOL
Output Low Voltage
10L-MAX. Yin .. V,L or V,H
-
V
VOH
Output High Voltage
IOH -MAX. Yin = V,L or V,H
2.4
-
O.S
-
V
-
-
12
mA
-
-2.0
mA
-30
-
-150
mA
-
7S
130
mA
45
65
mA
IIH
10L
Low Level Output Current
10H
High Level Output Current
105 '
Output Short Circuit Current
Voo .. SV Your - O.SV TA=2S·C
Icc
Operating Power Supply Current
V,L- O.SV V,H=3.0V
L -1S/-20/-30
Outputs Open (no load) Q ·20/-25
f'099I8 = 25MHz
1) One output at a time for a maximum duration of one second. Vout .. O.SV was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
2) Typical values are at Vee =5V and TA" 25 ·C
CAPACITANCE (TA
=25°C, f =1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM'
UNITS
TEST CONDITIONS
C,
Input Capacitance
10
pF
Vee = S.OV. V, .. 2.0V
Coo
110 Capacitance
10
pF
Vee = S.OV. VIIO - 2.0V
"Guaranteed but not 100% tested.
3-14
4/91.Rev.A
tattiOO!lJ
1..
Specifications GAL20V8AI883C
Semioonductor
CaporatkJn
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAMETER
-15
TEST DESCRIPTION
pOND'.
-20
-25
-30
MIN. MAX MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
tpd
1
Input or I/O to Combinational Output
3
15
3
20
3
25
3
30
ns
tco
1
Clock to Output Delay
2
12
2
15
2
15
2
20
ns
Clock to Feedback Delay
-
12
-
15
-
15
-
20
ns
Setup l)me, Input or Feedback before Clocki
12
-
15
ns
MHz
tcf2
tsu
-
1
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
41.6
-
33.3
-
1
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tet)
41.6
-
33.3
-
28.5
-
22.2
-
MHz
1
Maximum Clock Frequency with
No Feedback
50
-
41.6
-
33.3
-
33.3
-
MHz
Clock Pulse Duration, High
10
15
10
-
ns
Clock Pulse Duration, Low
-
-
-
th
fmax 3
Hold Time, Input or Feedback after Clocki
twt'
-
ten
2
Input or 110 to Output
2
OEL to Output
3
Input or 110 to Output
3
OEi to Output
twh'
tdis
0
-
0
28.5
-
22.2
-
20
0
12
-
15
-
20
15
-
18
15
-
20
-
15
-
18
-
12
15
-
-
25
15
20
25
20
25
0
15
-
-
ns
ns
30
ns
25
ns
30
ns
25
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax i;)escrlptions section.
3) Refer to fmax Descriptions section.
4) Clock pulses of widths less than the specification may be detected as valid clock signals.
SWITCHING TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
GNDto 3.0V
3ns 10%-90%
1.5V
1.5V
Output Load
+5V
See Figure
3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Test Condition
1
2
3
Active
Active
Active
Active
High
Low
High
Low
R1
R2
CL
3900
7500
7500·
7500
7500
7500
50pF
50pF
50pF
5pF
5pF
GO
3900
GO
3900
FROM OUTPUT (010)
UNDER TEST
--+---'--TEST POINT
R2
CLINCLUDES JIG AND PROBE TOTAL CAPACITANCE
3-15
4191.Rev.A
•
'Lattioo
fL]
.l.J
GP
Specifications GAL20V8AI883C
SemiCXJnducwr
Corporation
SWITCHING WAVEFORMS
INPUT or
110 FEEDBACK
eLK
INPUT or
110 FEEDBACK
REGISTERED
OUTPUT
COMBINATORiAl
OUTPUT
Combinatorial Output
Registered Output
INPUT or
110 FEEDBACK
OE
OUTPUT
OUTPUT
OE to Output Enable/Disable
Input or 110 to Output Enable/Disable
CLK
twl
CLK
REGISTERED
FEEDBACK
Clock Width
fmax with Feedback
3-16
4/91.Rev.A
Specifications GAL20 V8AI883C
fmax DESCRIPTIONS
ClK
.--_ ... ..................................................................
··
...
_
lOGIC
ARRAY
elK
REGISTER
·..............................................................................
lio..
oII~--lou ---~
..lio..
oIII----lcD----.t
fmax wHh External Feedback 1/(tsu+tco)
iooII~I-----lcf----l~~1
Note: fmax with external feedback is calculated from measured
tsu and tco.
...
~I------tPd-----I~~1
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax wlinternal feedback (tcf - 1lfmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
ClK
r............ _............ •.... •............ •.... •....................................:
··
:
i
~
~~~~CY
..
:
REGISTER
i
................................................................ _........................,
fmax Without Feedback
Note: fmax with no feedback may be less than 1ltwh + twl. This
is to allow for a clock duty cycle of other than 50%.
3-17
4/91.Rev.A
v~·
LM
borporation
Specifications GAL20V8AI883C
GAL20V8A ORDERING INFORMATION (MIL-STD-883C and SMD)
Ordering #
Tpd
(n8)
15
20
Tau
(n8)
12
15
Teo
(n8)
12
15
Icc
(mA)
Package
MlL-8TD-883C
SMD#
130
24-Pin CERDIP
GAL20VSA-15LD1883C
5962-8984003LA
130
28-Pin LCC
GAL20VSA-15LRI883C
5962-89840033A
65
24-Pin CERDIP
GAL20VSA-2OQD1883C
Contact Factory
65
28-Pin LCC
GAL2OVSA-2OQRI883C
Contact Factory
130
24-Pin CERDIP
GAL20VSA-2OLD1883~
5962-8984002LA
130
28-Pin LCC
GAL2OVSA-20LRI883C
5962-89840023A
Contact Factory
25
20
15
65
24-Pin CERDIP
GAL2OVSA-25Q01883C
65
28-Pin LCC
GAL20VSA-25QRI883C
Contact Factory
30
25
20
130
24-Pin CERDIP
GAL20VSA~LD1883C
5962-8984001 LA
130
28-Pin LCC
GAL20VSA~LRI883C
5962-89840013A
Note: Lattice recognizes the trend in military device procurement towards using SMD
compliant devices, as such, ordering by this number where it exists is recommended.
PART NUMBER DESCRIPTION
xxxxxxxx-n
GAL20V8A
DOV~Na"~
Speed (ns) - - - - - - - '
1883C - 883C Process
L - Low Power Power - - - - - - - - - - '
a = Quarter Power
' - - - - - - Package
0 - CERDIP
R-LCC
3-18
4/91.Rev.A
.l.J LaWOO"
ill
GAL22V10B/BB3C
GAL22V10/BB3C
Semiconductor
Corporation
High Performance E2CMOS PLD
FUNCTIONAL BLOCK DIAGRAM
FEATURES
• HIGH PERFORMANCE E'CMOS* TECHNOLOGY
- 15 ns Maximum Propagation Delay
- Fmax = 62.5 MHz
- 8ns Maximum from Clock Input to Data Output
- TTL Compatible 12 mA Outputs
- UltraMOS* Advanced CMOS Technology
I/eu<
I/OIQ
INPUT
I/OIQ
INPUT
• ACTIVE PULL·UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
- Fully Function/Fuse·Map/Parametrlc Compatible
with Bipolar and UVCMOS 22V10 Devices
• 50% REDUCTION IN POWER VERSUS BIPOLAR
• E' CELL TECHNOLOGY
- Reconflgurable Logic
- Reprogrammable Cells
-100% Tested/Guaranteed 100% Yields
- High Speed Electrical Erasure «100ms)
- 20 Year Data Retention
INPUT
UOIQ
INPUT
IIOIQ
INPUT
I/OIQ
INPUT
I/OIQ
INPUT
I/OIQ
• TEN OUTPUT LOGIC MACRO CELLS
- Maximum Flexibility for Complex Logic Designs
INPUT
• PRELOAD AND POWER· ON RESET OF REGISTERS
- 100% Functional Testability
I/OIQ
INPUT
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
I/OIQ
INPUT
I/OIQ
INPUT
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
DESCRIPTION
PACKAGE DIAGRAMS
The GAL22V1 OB/883C and GAl22V1 0/883C are high perfor·
mance PCMOS programmable logic devices processed in full
compliance to MIL-STD-883C. These military grade devices
combine a high performance CMOS process with Electrically
Erasable (EO) floating gate technology to provide the highest
speed performance available of any military qualified 22V10
device. CMOS circuitry allows the GAL22V10/B to consume
much less power when compared to bipolar 22V1 0 devices. P
technology offers high speed «1 OOms) erase times, providing the
ability to reprogram or reconfigure the device quickly and efficiently.
CERDIP
LCC
Vee
~
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V1 OB and GAL22V1 0 are fully functiontfuse
map/parametric compatible with standard bipolar and CMOS
22Vl0 devices.
NC
g
0
Z
2
U 28
0
~
C!
51 51
GAL22V10/B
Top View
c
z
Unique test circuitry and reprogram mabie cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GALl» products.
"
110/0
Q
"z - § §
110/0
IIOIQ
110/0
IIOIQ
110/0
IIOIQ
110/0
NC
110/0
IIOIQ
110/0
11010
110/0
11010
110/0
110/0
Copyright 10199 I Lanice Semiconductor Corp. GAL. E'CMOS and UHraMOS ",e registerod trademarks 01 Lanico Semiconductor Corp. Generic Array Logic is a trademark of Lank:e Se_uctor Corp. The specifications herein are subject to change without notioe.
LATIICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. (503) 681-0118 or 1-800-FASTGAL; FAX (503) 681-3037
3-19
April 1991.Rev.A
..
LaWOOaD
[JJ
.l.J
Specifications GAL22V10BI883C
SemkxJnductor
Corporation
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING CONDo
Case Temperature (Te) .............................. -55 to 125°C
Supply Voltage (Vee)
with Respect to Ground ...................... +4.50 to +5.50V
Supply voltage Vee ........................................ -0.5 to +7V
Input voltage applied ............................ -2.5 to Vee +1.0V
Off"state output voltage applied ........... -2.5 to Vee +1.0V
Storage Temperature .................................. -65 to 150°C
Case Temperature with
Power Applied ......................................... -55 to 125°C
1. Stresses above those listed under the "Absolute Maximum
Ratings· may cause permanent damage to the device. These
are stress only ratings and functional operation of the device
at these or at any other conditions above those indicated in
the operational sections of this specification is not implied
(while programming, follow the programming specifications).
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified)
MIN.
TYP.3
MAX.
UNITS
Input Low Voltage
Vss-O.5
0.8
V
Input High Voltage
2.0
-
VcC+1
V
-100
itA
10
itA
0.5
V
-
V
SYMBOL
PARAMETER
VIL
VIH
CONDITION
IlL'
Input or 1/0 Low Leakage Current
OV S VIN S VIL (MAX.)
IIH
Input or 1/0 High Leakage Current
3.5V s VIN S Vee
-
VOL
Output Low Voltage
1oL= MAX. Yin = VILor VIH
-
VOH
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
12
rnA
-2.0
rnA
-50
-
-135
rnA
-
90
150
rnA
10L
Low Level Output Current
-
10H
High Level Output Current
-
los2
Output Short Circuit Current
ICC
Operating Power Supply Current
Vee .. 5V VOUT = 0.5V TA = 25°C
VIL=0.5V VIH =3.0V
ftoggle = 15Mhz Outputs Open
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Guaranteed but not 100% tested.
3) Typical values are at Vee = 5Vand TA= 25°C
CAPACITANCE (TA
=25"C, f =1.0 MHz)
SYMBOL
PARAMETER
CI
CliO
MAXIMUM"
UNITS
TEST CONDITIONS
Input Capacitance
8
pF
Vcc = 5.0V, VI - 2.0V
110 Capacitance
10
pF
Vcc .. 5.0V, VIiO= 2.0V
3% or
the "acceptable" post-programming test vector & board
yield fallout of 0.5 -> 2% to know that this correlation is
weak. The quality systems of today are measuring
defects in the parts per million (PPM). A six sigma
program requires less than 3.4 PPM, iQu[ orders of
magnitude less than that achievable with non-testable
PLDs.
ACTUAL MATRIX PATTERNING
The unique capability of PCMOS devices to be instantly
electrically erased allows these devices to be patterned
multiple times during Lattice's manufacturing test. Normal
array cells in the programmable matrix are patterned,
erased & tested again and again. The test rows or
columns, phantom arrays, etc., that are used with other
technologies are not necessary with E2CMOS devices.
Programmability of every cell is checked dozens of times.
Historically, the checking of a successful programming
operation consisted of no more than a passlfail verHication
step. This digital, blacklwhite style check is not adequate
to assure that the cell is programmed properly with
sufficient margin to guarantee long-term reliable
performance of the device. PCMOS devices have an
additional cell verHication step that conSists of an analog
measure (to millivolt accuracy) ofthe actual charge stored
on the cell. This data is used for extensive reliability and
quality measurements and testing.
WORST CASE AC/DC TESTING
A PLD does not have a defined function until the engineer
patterns the device with his custom pattern. The
manufacturer, when considering the testing of a PLD,
must consider the hundreds of different architecture and
functional variations that can be created by the end user.
Each configuration of architecture brings on a dHferent set
of worst case pattern and stimulus conditions. Quick
E2CMOS Testability Improves Quality
application of a series of worst case patterns that cover all
of the permutations of input combinations, array load &
switching, and output configuration is required.
E2CMOS devices offer instant erasability to address this
reconfiguration & test problem. Testing each additional
worst case configuration takes fractions of a second,
allowing dozens of patterns to be checked to assure
performanCe to rated speeds even underthe most grueling
AC pattel1'!. The firial result is· a device with defects
reduced from PPJ:I. (parts per hundred) to PPM (parts per
million) .•
4-6
I
I
Section 1: Introduction to Generic Array Logic
1
I
Introduction to Generic Array Logic _ _ _ _ _ _ _ _ _ _ _ 1-1
Section 2: GAL Datasheets
2
Datasheet Levels _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 2-ii
2-1
GAL 16V8A1B
GAL20V8A1B
2-25
GAL18V10
2-47
GAL22V10/B
2-61
GAL26CV12
2-81
GAL20RA 10
2-95
GAL6001
2-109
ispGAL 16Z8
2-121
Section 3: GAL Military Products
3
Military Program Overview _ _ _ _ _ _ _ _ _ _ _ _ _ 3-1
MIL-STD-883C Flow
3-2
Military Ordering Information
3-3
GAL 16V8A/B Military Datasheet
3-5
GAL20V8A Military Datasheet
3-13
GAL22V10/B Military Datasheet
3-19
GAL20RA 10 Military Datasheet
3-27
Section 4: Quality and Reliability
Quality Assurance Program _ _ _ _ _ _ _ _ _ _ _ _ _ 4-1
Qualification Program
4-3
PCMOS Testability Improves Quality
4-5
Section 5: Technical Notes
GAL Metastability Report _ _ _ _ _ _ _ _ _ _ _ _ _ _ 5-1
Latch-up Protection
5-17
Section 6: Article Reprints
Avoid the Pitfalls of High-Speed Logic Design _ _ _ _ _ _ _ 6-1
Extending the 22V1 0 EPLD
6-7
In-Circuit Logic Device Can be Reprogrammed on the Fly
6-9
Multiple Factors Define True Cost of PLDs
6-13
Section 7: General Information
Development Tools _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 7-1
Copying PAL, EPLD & PEEL Patterns into GAL Devices
7-3
GAL Product Line Cross Reference
7-5
Package Thermal Resistance
7-8
Package Diagrams
7-9
Tape-and-Reel Specifications
7-16
Sales Offices
7-17
5-i
4
I
I
~
6
7
5-ii
GAL Metastability
Report
It is accepted [1) that metastable failures can be accurately
modeled by the equation:
INTRODUCTION
The dictionary definition of metastability is "a situation that is
characterized by a slight margin of stability: When applied to
bi-stable (digital) logic, the term refers to an undesirable
marginally stable output state between VIL max and VIH min.
log Failure ~ log MAX-b(A - AO)
(1)
In this equation, MAX represents the maximum failure rate
for a particular environment, A is the time delayed before
sampling the OUT (Device Under Test) output, and A 0 is the
time at which the number of failures starts to decrease. On
a failure frequency plot (such as the one in Figure 2), AO
represents the knee of the curve. The constant b is rate at
which the frequency of failures decreases after the knee is
reached.
Metastability can occur in bi-stable storage elements (registers,
latches, memories, etc.) when setup andlor hold times are
violated. Since setup and hold times vary with temperature and
operating voltage, among other factors, the times referred to
here are not the minImax numbers printed in data sheets, but
rather the actual times for the given set of operating conditions.
Typical applications where such times are likely to be violated
include bus & memory arbiters, interfaces, synchronizers, and
other state machines employing asynchronous inputs or
asynchronous clocks.
Recall that:
log X" a In (X), where a - log (e)
Substituting this into (1):
Metastability manifests itself in a number of different ways.
Common responses are (shown as they might be captured on
a digital oscilloscope in Figure 1): runt pulse (1 a), decreased
output slew rate (1b), output oscillation (1c), and increased
clock-to-output time (1d). By definition, the phenomenon of
metastability is statistical in nature. Not only is entry into the
state uncertain, but the time spent there is also variable.
(2)
a· In Failure" a· In MAX - b(A - AO)
MAX is related to the clock frequency (fCLOCK) and data
frequency (fDATA). That is,
MAX = (k1 • fCLOCK· fDATA)
Because PLDs are commonplace in today's designs, a thorough understanding oftheir metastable behavior is crucial. In
some applications, output anomalies shorter than one clock
cycle may be acceptable, but in applications where the
register output is used as a control signal (clock, bus grant,
chip select, etc.) for other circuitry, faults such as runt pulses
and oscillation cannot be tolerated.
(3)
Substituting (3) into (2) and applying some algebra:
a· In Failure .. a· In (k1 • fCLOCK • fDATA) - b(A - AO)
In Failure - In (k1 • fCLOCK • fDATA) .. -bla(A - AO)
Setting k2 .. bla and rearranging the equation yields:
This report will not study the causes or characteristics of
metastability in great detail; excellent material has already
been prepared on this subject [1-5). Rather, this report will
introduce a mathematical model for the metastable phenomenon, discuss potential test methodologies, present and
compare test results from various bipolar and CMOS PLDs
and discuss how to interpret the data. This report will clos~
with suggestions on how to design metastable tolerant
systems.
Failure .. (k1 • fCLOCK· fDATA)e-l<2(a.aO)
(4)
When used with equation (4), the constants k1, k2, and AD,
completely describe a particular device's metastable characteristics; they indicate how quickly a device can resolve the
metastable condition. Devices which transition out of the
metastable region quickly are characterized by a small AO
and a large k2.
The constant k1 is peculiar to the test apparatus (it can be
thought of as a "scaling factorj. The maximum metastable
failure rate (MAX) is limited by fCLOCK; a failure cannot
occur if the device isn't clocked. Ukewise, it is true that a
metastable failure cannot occur unless data has changed.
So, if fDATA < fCLOCK, then MAX .. fDATA. This was the
case in the test fixture Lattice used (fCLOCK=10MHZ,
fDATA=2.5MHz). Substituting MAX = fDATA back into equation (3) yields: k1 " 1lfCLOCK, so k1 .. 1DOns for our tests.
PERIVATION OF CONSTANTS
The basic premise of all metastability models is that a
device's output is more likely to have settled to a valid state
i~ ti~e(!l than in time(t-n). In fact, the failure probability
distribution follows an exponential curve. Figure 2 shows a
typical failure frequency plot.
5-1
4191.Rev.C
GAL Metastability Report
it is in the metastable region (between VIL max and VIH min).
The comparator output can be sampled periodically and
used to increment an event counter.
TEST FIXTURE
The goal of testing a particular device's metastable characteristics is to generate real numbers forthe constants k2 and
Ao. To do this, the device must first be forced into the
metastable state. This is done by intentionally violating setup
and/or hold times. Once metastable, the output can be
observed on an oscilloscope or used to increment an event
counter.
This method of testing, though it directly yields MTBF
numbers, has some drawbacks. The first is that it does not
distinguish between the different types of metastable behavior (runt pulse, oscillation, slow risellall time, delayed transition), and it may have difficulty detecting every type. Also, the
registers used in the detector circuit itself may become
metastable, which would adversely affect the results.
Traditional Approach
One approach to characterizing a device's metastable behavior employs a test fixture similar to that shown in Figure
3a. In such a fixture, data to the device includes a "jitter band"
so that the device sees changing data as it is clocked. The
OUT output is fed to a window comparator to determine when
A New Approach
The test method used to gather data for this report used the
circuit shown in Figure 3b. The tester employed an "infinite
precision" variable delay circuit to control clock placement
y
y
VIH
VIL
clock
1 b. Decreased Slew Rate
1a. Runt Pulse
output
II
v
Teo
clock
Teo
output
.:.'
".
""
""
V IH
V IL
. ::...
t
t
clock
Teo
clock
1 c. Output Oscillation
Teo
1d. Increased Teo
'U
(ll
.....
~
lOB
__
MAX ••••••_••••_•••••••••••_.
g
10 6
--
~
10 4
-I-
~
10 2
-I-
~
iI
r:
I
i
0::
~o
'0
u.
10
20
30
~
40
50
60
70
80
time (ns)
Figure 2. Typical Failure Frequency Plot
5-2
GAL Metastability Repotf
with respect to data. This arrangement allowed exact worst
case placement of the clock, so as to induce metastability
with nearly every clock pulse.
time (although, in the case of the scattered points, the
probability is low that a single isolated point represents more
than one sample).
Using a digital oscilloscope (Tektronix 11403A) in point
accumulate mode, metastable failures were recorded over a
lengthy period of time. A hardcopy was then made and the
constants empirically obtained (details below).
To generate values for k2 and AO, it was necessary to refer
to previous metastability studies [1]. By studying the output
plots of devices with known constants, certain relationships
were established. For example, it was determined that AO
represents the time from the leading edge of the output until
the "dot density" starts to decrease measurably. It should be
noted that AO in previous studies included device propagation delays, whereas in our test it does not.
The oscilloscope approach, being visual in nature, enables
the designer to make educated decisions regarding maximum clock and data rates, as well as the suitability of using
the output to drive other circuitry. The five minute sample
period used in our tests contained approximately 750 million
failures. Much longer sample periods were evaluated, but
they provided no perceptible gain in usable information.
The time from t\O until the dot density equals zero was
defined to be the ''time to metastable release" or simply
time(r). The relationship between k2 and time(r) is given
below in (5), and shown graphically in Figure 4. Recall that
MAX=2.5x10"6 and a=log(e).
A slight disadvantage of this approach is that extracting k2
and t\O values from the hardcopies is not straightforward.
Because each point on the hardcopy can represent any
numberof actual samples (between one and 1.5 million), one
cannot simply count the points at time(t) for the MTBF at that
k2 = 10g(MAX) I (time(r) • a) ., 14.73/time(r)
(5)
VARIABLE DELAY
VIH
I---ID
D
0
DUT
TO
COUNTER
0
'373
VIL
Figure 3a. Traditional Metastability Test Circuit
TO DIGITAL
OSCILLOSCOPE
Osc.
D
Ol---rl
DUT
Figure 3b. Lattice Mestability Test Circuit
5-3
GAL Metastability Report
INTERPRETING THE RESULTS
gathered on similar devices by the manufacturer [1]). The
absence of a secondary trace along ground indicates that the
output always starts to transition to a high level, even when it
finally settles to a low level. This characteristic makes the
device unsuitable for use in control path applications (when
metastability is possible). All of the bipolar parts examined
showed similar results.
In addition to examining E2CMOS GAL devices, this study
also tested several bipolar PAL devices as well as other
CMOS PLDs. To insure that the results of this study would
be relevant, all necessary precautions were observed: the
devices were of recent vintage and were acquired blindly
through distributors; multiple samples of each device were
tested and the results combined; all devices had either fixed
16R8 architectures or were configured to emulate the 16R8
architecture; the devices were programmed from the same
JEDEC fuse map file (the source equations and the JEDEC
fuse map file are presented in Listing 1).
Plot 1, 2 and 3 are from GAL16V8B-7, GAL22V10B-10 and
GAL6001-30, respectively. Aside from the fact that setup
time violations may cause leo to increase by a small (but
random) amount, the outputs are very clean and well behaved. The fact that there are no runt pulses or other
anomalies is extremely significant, as the GAL6001 not only
allows asynchronous clocking, but encourages that activity.
Although GAL6001 is a much slower device as compared to
GAL 16V8 and GAL22V1 0, the similar metastable characteristics of the GAL6001 to the much faster GAL devices
indicate that the inherent metastable characteristics of all the
GAL devices have consistently desirable characteristics
across all speed grades. Comparing Plot 1, 2 and 3 with Plot
4 and 5 shows that characteristics of the GAL devices are
superior to those of bipolar PLDs. Plot 6 illustrates metastable characteristics of the TTL flip-flop (TISN74AS74).
Plots 1 through 6 on the following pages are some of the
oscilloscope plots generated for this study. The top waveform in each plot is the clock signal, the middle trace is the
metastable data output and the bottom trace is the histogram
of the accumulated samples between 1V and 2V of the output
signal. The horizontal scale is 2ns per division, so the exact
clock to output time of the metastable output condition can
be read directly. The vertical scale is 2V per division for the
top trace, and 1V per division for the middle trace.
The middle waveform in each plot is the metastable device
output which is the only signal captured in point accumulate
mode. In every case, the output signal plot shows two stable
levels after the transition. This is a direct result of the
"indecision" caused by metastability; on some cycles the
output settled to a high level, while on others it settled to a low
level.
For reference purposes, Plots 7 through 9 are included. Plot
7 shows a normal (ie. non-metastable) GAL16V8B-7 transition; and Plot 8 a normal PAL 16R8-7 transition. Plot 9 is the
normal transition of the TTL flip-flop (TI SN74AS74). For
consistency, only rising edges have been shown. Our tests
also covered falling edges which, in general, were interesting
but did not provide any additional information.
Plot 4 shows the response of a bipolar PAL16R8-7. Noticethe
very well defined runt pulse (this correlates with previous data
15
12.5
I
10
k2in
1/ns1\2
7.5
.5
"-
2.5
......
""-
0
2
4
6
-- -
r-- :-- i--
i--
-
8 10 12 14 16 18 20 20 24 26 28 30
time (r)
FIgure 4. K2 Constant
5-4
GAL Metastability Report
I
I
i
For a more quantitative look at the phenomenon of metastability, refer to the table beneath each plot. These tables listthe
measured values of the constants Ao and k2 for the device
whose plot is shown, and for similar devices. Recall that large
k2 and small Ao values are desirable. The numbers in the
tables correlate closely with the results of earlier tests [1,5],
confirming the validity of our test method.
tion, though also the result of a setup time violation, should not
be confused with metastability (the "incorrect" data that is
captured has normal output characteristics); it is, pura and
simply, the result of a violation of specifications.
Example
To determine the maximum clock rate (given an acceptable
error rate) that a particular device will allow in an asynchronous environment, equation (4) is used. For example, the
system shown in Figure 6 utilizes a 9600 baud (bits/sec)
asynchronous data stream. The system clock period is
tCO+tPD+tSU+A. For one failure per year:
Since all current GAL devices possess very similar register
and output buffer circuitry, and all are fabricated using the
same basic process, the data shown in Table 1 for the
GAL 16V8 is considered applicable to all devices and speed
grades in the GAL family.
3.2x10-8 - [(1 x1o-7)(1/(A+22»(9600)]eo(4(Ao....1I
USING THE RESULTS
H a register enters the metastable state in a system, then
data was obviously unstable as the register was being
clocked. The argument over which data should have been
captured (old or new) is academic as the register will
randomly pick one or the other. Signals in most asynchronous systems are active for more than one clock cycle, so if
they are missed initially, they could be captured on a
subsequent clock cycle.
It is the task of the state machine deSigner to take adequate
precautions against metastability causing illegal states to be
entered. One way to do this is by using "gray codes· when
ordering states. Gray code state equations allow only one
state bit to change during a state .transition. Thus, the worst
metastability could do would be to delay a state transition by
one clock cycle. Hmore than one bit were allowed to change,
the outcome would be purely random, and probably illegal.
FigureS shows examples of both cases.
Solving for A yields A-2.22ns, or about 2ns, for a cycle time
of 24ns. Referring back to Plot 1, the additional delay of 2ns
intuitively makes sense. Remember, in terms of setup and
hold time violations, the oscilloscope plots were made under
worst case failure conditions; the scattered dots could represent MTBFs of days, years, or even millenniums in a typical
asynchronous environment.
Due to the extremely quick metastable settling times of GAL
devices, a relatively small increase in the cycle time will
produce a dramatic improvement in reliability.
BIBLIOGRAPHY
1. D.M.Tavana (MMI), "Metastability - A study of the Anomalous Behavior of Synchronizer Circuits," in: Programmable
Array Logic Handbook, Monolithic Memories Inc., 1986, pp
11-13-11-16.
Other solutions are to externally (or internally) synchronize
the asynchronous signals, or to increase cycle times to allow
time for metastable outputs to settle. An example of the latter
solution is given below.
It is worth noting at this point that state machines (synchronous or asynchronous) can fail for reasons other than
metastability. A not insignificant component of a PLD's
specified setup time is directly attributable to internal data
skewing [2]. Data skewing is the inevitable result of differing
signal path lengths, loading conditions, and gate delays.
Stated another way, each input to output path has its own set
of actual AC specifications. H insufficient setup time has
passed, different "versions· of the same data may be present
at the inputs of different registers as they are clocked. A good
example of this is:
OutpuCPin19 :- Input_Pin2;
OutpuCPin15 :- IInput_Pin2;
If clocked at precisely the right moment after an input
transition, one register will capture old data while the other
captures new data, resulting in a system failure. This condi-
5-5
2. K.Rubin (Force Computers), "Metastability Testing in
PALs," Wescon187 Conference Record (San Francisco,
November 17-19, 1987). Los Angeles: Electronics Conventions Management, Inc, 1987, pp 1611 1-10.
3. K.Nootbaar (Applied Microcircuits Corp.), "Design, Testing, and Application of a Metastable Hardened Flip-Flop,"
ibid., pp 1612 1-9.
4. J.Birkner (MMI), "Understanding Metastability," ibid., pp
1613 1-3.
5. R.K.Breuninger, K.Frank, "Metastable Characteristics of
Texas Instruments Advanced Bipolar Logic Families," application note SDAA004, Texas Instruments, 1985.
.,
!
GAL Metastability Report
SEQUENTIAL STATE ORDERING
GRAY CODE STATE ORDERING
H metastability
occurs while
transitioning from 01,
the possible next
states are 01 and 11.
H metastability occurs
while transitioning from
01, every state is a
possible next state.
Figure 5.
DATA
-.......
GAL16V8
GAL16V8
-D
Tpd = 10ns
CLOCK
Teo =5ns
Tsu =7ns
A.
A.
I
I
D
OUTPUT
Figure 6.
MODULE metastable
TITLE 'Metastable Test
Pattern'
JEDEC file for: P16R8
Metastability Test Pattern*
QP20* QF2048* FO*
LOOOO 101111111111111111111111111111*
L1792 101111111111111111111111111111*
C07F4*
uOO Device 'P16R8';
d
q1,q2
PIN 2;
PIN 12,19;
EQUATIONS
q1 := d;
q2 .= d;
End metastable
Listing
1a. Source equations
Listing 1b. JEDEC file
5-6
GAL Metastability Report
2V/dlv
....................
..
···
..
···
...
··
.
·
.
.............................
··
..
..
·
.
~
.......................................................
··
..
..
·
.
...
···
...
.
·
.
...
..
Output-t
·
.
..................................
!.; ,'" .............. :.................. : ........ .
.
·
1V/dlv
·
.
.
...............................
,
..........................................................
.
..
···
...
..
··
.
..
.
··
.
...
·
.
·
.
.
.......................................................
II
I,
2n5/dlv
Plot 1. GAL16V8B-7 Metastable Output
Part #
Manufacturer
.t.o (n5)
k2 (1/n52)
GAL16V8B-7
Lattice
.44
5.0
5-7
GAL Metastability Report
.
·· ...................
.. .
. ... ... ..·. ..
2V1dlv
~
...........................................................................
.
..
.
···
...
...
...
...
.
..
···
..
...
...
...
...
...
.
..
..
..
.·
.
.. • •••• .:. •••••••••
""I'
••.••.. ; ••••••••• ; ••••••••• ; .•••.•••• ;....
. •
..
···
...
..
··
..
..
...
.
··
..
.
...
.
.
·
.
.
.................................................
..:...............................
.
.·
..
··
..
··
..
··
·
...
~~~~
1V/dlv
...
....""""....
~.~
....~
.. ~
.............. ~
....~
...~
... ~.~~~
·
.
.
.
..............................................
·
.
.
.
.............................................
......... ,.........................
: ........ .
··
...
···
..
·
···
....
.0
••••••••••• ,•••••••••••••••••••••••••••
2ns/div
Plot 2. GAL22V10B·10 Metastable Output
Part #
Manufacturer
6.0 (ns)
k2 (1/ns2)
GAL22V10B-10
Lattice
.51
5.2
5-8
~
GAL Metastability Report
............................................................................................
··
...
··
··
...
.
·................
..
···
..
.
···
...
·
2V/dlv
·
.
............................................
.....................
.
...
·.·
.
···
...
··
..
·
.
.
............................................
Output -+
1V/dlv
·
..
....................................
..................
··
·
···
··
·
~
... . . . . . . .. . ... . . ...
..
..
...
...
.
.
.
.
. , .
.........................................................
.
..
.
.... ............ .. .. ......................................
.
.
2ns/dlv
Plot 3. GAL6001-30 Metastable Output
Part #
Manufacturer
l!.O (n5)
k2 (1/n5 2)
GAL6001-30
Lattice
.22
7.3
5-9
GAL Metastability Report
.............................................................................................
···
..
..
..
.
··
.
..
·
.
:
:
..............
.
~:~~
~
.
.
.
....................
......... .............................
.................. .
::
.
~
~
: :.
2V/dlv
::
:
~
~
~
:
. :
. :
,
.........................................
..
..
: I.'
.
· ..l'.·..
···1···············
..................
.
'0:
It.
:
:
·
.
...................................
.,.
1V/div
~
':':<:' .j
Output -+
............................................
·
..
····
.
...
···
.
.
·
.
.............................
.
··
..
··
..
··
..
··
...
·
.............................
.
,
.
'.
.'
..
...... ,... : .......................... .
2ns/dlv
Plot 4. PAL16R8-7 Metastable Output
Part #
Manufacturer
AO (ns)
k2 (1/ns2)
PAL16R8-7
AMD
1.2
2.5
5-10
GAL Metastability Report
........................................................................ : ......... : ........ .
..
..
Clock;
·
.
.
.
.......................................
......... ......... ......... ............................
.
2V/dlv
........ 1
Output -+
.
.
..................................
..
•
• !.',
1V/dlv
·
.
.............................
.
~
·
.
............................
I
2ns/div
Plot 5. TIBPAL16R6-7 Metastable Output
Part #
Manufacturer
~o
TIBPAl16R6-7
TI
1.5
5-11
(ns)
k2 (1/ns2)
1.5
GAL Metastability Report
2V/dlv
........ : ............................... .: ......... : ......... : ......... ; ......... .: ........ .
.
..
..
.
..
···
.
..
..
..
.
..
·
.
.
:·
::
'
:
:
:
.
.
.
.
..
..
.
.
.
.............................
W/dlv
...................
................................................................
2ns/div
Plot 6. SN74AS74 Metastable Output
Part #
Manufacturer
Il.o (ns)
k2 (1/ns2)
SN74AS74
TI
.91
3.5
5-12 '
GAL Metastability Report
..................................................................................: ......... :
....
·····
.....
.
·
.
.
:
:;;",r.~~
:
.
____ .. .. .... ......... ......... .. ................ ..
. ...................
...
...................
......... ......... ...................
. .
.
.
: :
2V/dlv
: .
:
.
:
:
::
::
.
.
.............................. :......... :
Output-+
H.HH ... H....... ...Hi H ·.. H... · ............
L-_..:......_~#-_:--_-:-_---:-
1V/dlv
TJ
_ _-;--_-:-_~ ........ ..
................... !............................................. !
.
.
..............................
... .. ......... ~ . .. .... .. ......... ......... .......... . ........ ~
····
...
.
.
.
..............................
.............. :··............................................. ..:
:
:
·
.
···
...
··
..
2ns/dlv
Plot 7. Nonnal GAL16V8B-7 Transition
5-13
GAL Metastability Report
.. ....... : ......... : ......... : .........
...
···
...
~
···
·
...
.
......... ......... ......... ......... ......... . ........ .
..
.
~.~~.~
..............~
.................~
.... ~
..... ~.~
....... : .................. : ............................................ .
··
..
2V/dlv
··
..
. .................................. .
~
Output ~
·
.
.............................
.....
1V/dlv
.: ........................... .: ............................................ .
..........
: .........
..
.
.
...
.
.
.
.
.
.
...
..
.
.
.
..
.
..............................
··
..
··
...
···
...
··
.
.............................
. ............ : ............................................ .
2ns/dlv
Plot S. Normal PAL16RS-7 Transition
5-14
GAL Metastability Repolf
2V1dlv
..
......... : ......... : ......... : ......... :.....
.
..
.
·
-'~
:
·
:
.
Output
~
·.
..
·
.
..................................................
··
..
..
.
··
..
..
...
·
..
..
..
···
.
.
.
.
.
.
·
.
.
.
1V/dlv
. ......................... .
. ........................................ .
........__..."
...................................................... .
·
.
.............................
......... ...
. ............................................. .
............................. ......... ..
.............................................. .
2ns/div
Plot 9. Nonnal SN74AS74 Transition
END
5-15
Notes
5-16
Latch-up Protection
INTRODUCTION
The Lattice GAL family has been developed using a highperformance E2CMOS process. CMOS processing was
chosen for the GAL family to provide maximum AC
performance with minimal power consumption. A
drawback common to all CMOS technologies is the
destructive agent, latch-up.
This brief defines the phenomenon of latch-up, how it
manifests itself, and what techniques have been used to
control it. Also described are three device features
employed in the GAL family to eliminate the occurrence of
latch-up as well as the results of an intensive investigation
conducted to reveal the GAL family's tolerance to latchup.
Latch-up is destructive bipolar device action that can
potentially occur in any CMOS processed device. It is
characterized by extreme runaway supply current and
consequential smoking plastic packages. Latch-up is
peculiar to CMOS technology, which integrates both P
and N channel transistors on one chip.
In the doping profile of a CMOS inverter, parasitic bipolar
(PNPN) silicon-controlled-rectifier (SCR) structures are
formed. Figure 1 shows the process cross section of a
CMOS inverter, as well as the bipolar components to the
parasitic SCR structure. In steady-state conditions, the
SCR structure remains off. Destruction results when stray
current injects in to the base of either 0, or 02 in Figure 1.
The current is amplified with regenerative feedback
(assuming that the beta product of 0, and 02 is greater
than unity), driving both 0, and 02 into saturation and
effectively turning on the SCR structure between the
device supply and ground. With the parasitic SCR on, the
CMOS inverter quickly becomes a nonrecoverable short
circuit; metal trace lines melt and the device becomes
permanently damaged.
CAUSES OF LATCH-UP
It has been explained that paraSitic bipolar SCR structures
are inherent in CMOS processing. If triggered, the SCR
forms a very low-impedance path from the device supply
to the substrate, resulting in the destructive event. Two
conditions are necessaryforthe SCR to turn on: The beta
product of 0, and 02 must be greater than unity, which,
although minimized, is usually the case; and a trigger
current must be present. The cause of latch-up is best
understood by examining the mechanisms that produce
the initial injection current to trigger the SCR network.
Figure 2 is a schematic of the parasitic bipolar network
present in a CMOS inverter, where node "b" is the inverter
output. It can be seen that two events might trigger latchup: 1) the inverter output could overshoot the device
supply, thereby turning on 0 3 and injecting-currentdirectly
into the base of 02; and 2) the inverter output could
undershoot the device ground, turning on 02 immediately.
However, a third condition could also trigger latch-up; if
the supply voltage to the P+ diffusion were to rise more
quickly than the N-well bias, 0, could tum on. Within the
device circuitry, overshoot and undershoot can be
controlled by design. A problem area exists at the device
Figura 1. CMOS Invartar Cross-Section
5-17
Latch-up Protection
inputs, outputs and I/Os because external conditions are
not always perfect. Powering up can also be a potential
problem because of unknown bias conditions that may
arise.
With CMOS processing the possibility of latch-up is always
present. The major causes of latch-up are understood
and it is clear that if CMOS is to be used, solutions to latchup will have to be created. As the technology evolves,
solutions to latch-up are becoming more creative. Two of
the more straightforward solutions are presented here.
One direct way to reduce the threat of latch-up is to inhibit
02 (Figure 1) from turning on. This has been accomplished
by grounding the substrate and reducing the magnitude of
Rsub through the use of wafers with a highly conductive
epitaxial layer. While the technique is successful, the
wafers are more expensive to manufacture, due to the
extra processing required to form the epitaxial layers.
The extensive use of "guard rings" helps to collect stray
currents which may inadvertently trigger an SCR structure.
A disadvantage to heavy use of guard rings is the
constraints placed on circuit design and topological layout,
and the resulting increase in die size and cost.
THE LATCH· LOCK APPROACH
The intent of the GAL family was to implement costeffective solutions to each major cause of latCh-Up. The
goal was met through three device features.
The most susceptible areas for latch-up are the device
inputs, outputs and I/0s. Extreme externally applied
voltages may cause a P+N junction to forward-bias,
leading to latch-up. The inputs, by design, are safe; but
outputs and I/Os present a danger.
To prevent latch-up by large positive swings onthe device
outputs or 1/0 pins, NMOS output drivers were used. This
eliminates the possibility of turning on 03 (Figure 2) with
an output bias in excess of the device supply voltage.
Figure 3 contains the effective NMOS output driver and its
switching characteristics. Note that the output does not
fully reach the supply voltage, but still provides adequate
V011 margin for TTL compatibility.
To prevent negative swings on device output and I/O pins
from forward-biasing the base-emitter junction of 2 , a
substrate- bias generator was employed. By producing a
V•.., of approximately -2.5v, undershoot margin is increased
to about -3V.
°
To insure that no undesired bias conditions occur with P+
diffusions, Lattice Semiconductor has developed
proprietary Latch-Lock power-up circuitry, illustrated in
Figure 4. In short, the drain of all P channel devices
normally connected to the device supply is now connected
to an alternate supply that powers up after the device Nwells have been biased and the substrate has reached its
negative clamp value. This prevents any hazardous bias
conditions from developing in the power-up sequence.
After power-up is complete, the Latch-Lock circuitry
becomes dormant until a full power-down has occurred;
this eliminates the chance of an unwanted P channel
power-down during device operation.
To determine the amount of latch-up immunity achieved
with the three device features utilized in the GAL family,
an intensive investigation was carried out. Each step was
Vee
Vee
Input
RWELL
Q1
L..-_ _ _ _
b output
Figure 2. Parasitic SCR Schematic
Figure 3. NMOS Output Driver
5-18
Latch-up Protection
conducted at 25° and 100°C; inputs, outputs, and VOS
were sequentially forced to -8V and +12V while the device
underwent fast and slow power-ups; devices were
repeatedly "hot socket" SWitched with up to 7.0V.
Even under the extreme conditions specified, no instance
of latch-up occurred. In an attempt to provoke latch-up, ±
50mA was forced into each output and 110 pin. The device
output drivers were damaged in the battle, and still latchup was not Induced.
Based on the data, it is evident that the GAL family is
completely immune to latch-up, even when subjected to
a wide variety of extreme conditions, including current at
inputs, outputs, and VOs, power-supply rise time, hotsocket power-up and temperature .•
Vee
LLC
VLL
• • •
v'
i
!
~
Figure 4. Latch-Lock Power-Up Circuitry
5-19
Notes
5-20
1
Section 1: Introduction to Generic Array Logic
Introduction to Generic Array Logic
1-1
2
Section 2: GAL Datasheets
2-ii
2-1
2-25
2-47
2-61
2-S1
2-95
2-109
2-121
Datasheet Levels
GAL16VSNB
GAL20VSNB
GAL1SV10
GAL22V10/B
GAL26CV12
GAL20RA10
GAL6001
ispGAL16ZS
3
Section 3: GAL Military Products
Military Program Overview
MIL-STD-SS3C Flow
Military Ordering Information
GAL 16VSNB Military Datasheet
GAL2QVSA Military Datasheet
GAL22V10/B Military Datasheet
GAL20RA 10 Military Datasheet
3-1
3-2
3-3
3-5
3-13
3-19
3-27
Section 4: Quality and Reliability
Quality Assurance Program
Qualification Program
PCMOS Testability Improves Quality
4
4-1
4-3
4-5
Section 5: Technical Notes
GAL Metastability Report
LatCh-up Protectio(l
5-1
5-17
Section 6: Article Reprints
Avoid the Pitfalls of High-Speed Logic Design
Extending the 22V1 0 EPLD
In-Circuit Logic Device Can be Reprogrammed on the Fly
Multiple Factors Define True Cost of PLDs
6-1
6-7
6-9
6-13
Section 7: General Information
Development Tools
Copying PAL, EPLD & PEEL Patterns into GAL Devices
GAL Product Line Cross Reference
Package Thermal Resistance
Package Diagrams
Tape-and-Reel Specifications
Sales Offices
6-i
7-1
7-3
7-5
7-S
7-9
7-16
7-17
5
.7
6-ii
Ut~lliN
AtJtJLlCA IIUI\J~
MAKE SURE THAT YOUR TURBO-CHARGED LOGIC
SYSTEM WORKS By PAYING As MUCH ATTENTION
To PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES
As To LOGIC DESIGN CONSIDERATIONS.
AVOID THE PITFALLS OF
HIGH-SPEED LOGIC DESIGN
odern high-speed systems demand modern highspeed logic families. Consequently, semiconductor houses have developed such product lines as
ACT, FACT, and AS. But these systems also demand that the lay-out of their boards conform
with the results of distributed-element theory,
otherwise ringing, crosstalk, and other transmission-line phenomena render
those systems inoperative. Meeting this second requirement necessitates something more than a: new product introduction-it insists on a change in the way
logic boards are engineered. The logic-systems designer and the board-layout
designer must work hand-in-hand if a viable high-speed board or system is to be
produced.
In the past, logic design and board layout were usually regarded as separate
parts of the design process. First the system designer configured the logic, then
the board engineer laid it out. That approach worked because slew rates were so
low (0.3 to 0.5 VIns) that crosstalk wasn't much of a problem; rise times were so
long (4 to 6 ns) that ringing
could settle down before a klgic
element could change state;
High·current
and in general, the assumpLogiccircuH
SWitching device
tions of lumped-element circuit
ground plane
ground plane
theory usually worked out
pretty well.
For systems designed with
today's high-speed logic. cir.",- Gap", 1/8 in.
cuitry, those underlying assumptions no longer hold true.
Today's slew rates are on the
TO MINIMIZE NOISE, THE ground
order of 2 to 3 VI ns, rise times
plane should be fragmented into separate areas for
are below 2 ns (frequently, benoisy high-eurrent devices and for sensitive logic
low 1 ns), and transmission-line
circuits. For best results, the number of signalUnes
phenomena, such as ringing,
that cross the gap between the fragments should be
can be a problem for trace
minimized.
1\
11.
JOCK TOMLINSON
Lattice Semiconductor Corp., P.O. Box 2500, Portland, OR 97208; (503) 681-0118.
Reprinted with permission from ELECTRONIC DESIGN - November 9.1989
6-1
1,I£im:"taullij"jm$'
DESIGNING WITH
HIGH·SPEED LOGIC
lengths as short as 7 in. As a result,
logic designers must take certain
steps:
Central system ground
• Use ground and power planes.
• Control conductor spacings to eliminate crosstalk.
• Make extensive use of decoupling
capacitors.
• Pay attention to ac loading.
• Terminate lines properly to minimize reflections.
PLANE ADVICE
For high-speed logic, ground
planes aren't simply suggested for
reliable board performance-they
are absolutely necessary. It's essential that one layer of the board be assigned for a ground plane and that it
cover as large an area as possible. A
solid ground plane lowers the
ground-return-path impedance as
well as the device-to-device ground
pin impedance.
But a common ground plane for all
of the circuitry in a system can cause
problems by coupling noise from
high-current switching devices into
sensitive logic inputs. Therefore, the
ground plane for such high-current
F
grounds should be supplied for the logic
circuitry, noisy high-current devices, and
the chassis. The three should come
together at one point, the central system
ground, which is usually located near the
power supply.
devices as relays, lamps, motors, and
hard drives should be separated
from' the logic ground. This can be
accomplished by fragmenting the
ground plane into discrete areas
(Fig.i) ..
But fragmentation causes problems of its own-it creates discontinuities in the characteristic imped-
ance of any transmission line that
crosses the separation between fragments. Therefore, for best results,
boards shouqd be laid out so that only
two fragments are needed. The gap
between those fragments should be
kept as narrow as possible (an eighth
of an inch works well in most applications), and the number of signal lines
that cross the gap should be minimized. Designers should also bear in
mind that through-holes and vias
subtract from the effective area of
the plane, increasing its effective impedance.
As with grounding, an entire layer
of the board should be designated as
a power plane. Even though it is at a
different potential, the power plane
should be implemented in accordance with the same concepts as the
ground plane. Therefore, it should be
fragmented when necessary to isolate noisy components from delicate
logic circuits.
A WELL-GROUNDED SYSTEM
In addition to properly designed
power and ground planes, highspeed logic systems require the establishment of a good, clean (low-
SIGNAL LINES BECOME TRANSMISSION LINES
or the transmission line
model illustrated in the diagram, the rise time (to is
less than the line propagation delay (TD). In other words, a
complete TTL level transition will
occur before the pulse is received
at the receiving end of the line and
reflections (ringing) will result.
The voltage change at point A on
the line is expressed in Eq.1:
AVA = AVint(Zo / (Ro + Zo»
Because Ro is so small when
compared to the line impedance,
the change in voltage at point A
(AVA) will approximately equal
the change in internal voltage
(A Vint). This voltage transition
propagates down the line and is
seen at point B after the line propagationdelay, TD•
At point B, a portion of the
wave will be reflected back towards point A in accordance with
Where: Vint = internal voltage on
the output of the driver;
Ro = output impedance of the
driving gate;
RL = load impedance;
Zo = the characteristic line
impedance;
and VA= the source voltage at the
sending end of the line.
the formula (Eq. 2):
Eq.2
PL = (R L-Zo) / (R L+ Zo)
where PL' called the voltage reflection coefficient (rho), is the ratio of the reflected voltage to the
incident voltage.
After examining Eq. 2, it should
be evident that -1 :5: P :5: +1. It
should also be evident that there
will be no reflected wave if RL =
Zo-if the line is terminated in its
characteristic impedance. Note
that the reflected wave can, in
principle, be as large as the incident voltage and of either positive
or negative polarity.
This analysis holds true for the
sending end of the line, as well as
the receiving end. That is,
Eq.3
Ps = (Ro - Zo) / (Ro + Zol
6-2
lu\1iH:"!44IiR,ilili$1
DESIGNING WITH
HIGH-SPEED LOGIC
creating a stub or a high-frequency
antenna.
Another step that can be taken to
reduce crosstalk is to lower the impedance of those traces into which
crosstalk is especially to be avoided.
The lower the impedance that a trace
presents, the harder it will be to
cross-couple a signal into it.
Even with the use of power and
ground planes on a pc board, decoupiing capacitors must be
used on the Vee pins of evB
ery high-speed device.
Those devices demand a
nearly
instantaneous
change in current whenever they switch states. Because the power plane
can't meet that demand, a
high-quality decoupling
capacitor is required, otherwise the switching will
cause noise on the Vee
plane.
A O.l-/LF multilayer ceramic (MLC) or other RF
quality (low-inductance)
capacitor should be placed
on every fast-slew-rate device as close to the Vee pin
as possible. The commercially available DIP sockets with built-in decoupiing capacitors also work
well in this application.
Most designers, when
they think of loading at all,
think in terms of dc load3. WA VE PROPAGATION along a transmission line
ing-traditionally
reTAMING CROSSTALK
occursas follows: Prior to time zero, there is a steady-state voltage
ferred to as fan-out and
Crosstalk-the undesirof 2.5 Vde on the line (a). At t = 0, the vollage at point A drops to
fan-in. But that type of
able coupling of a signal on
0.5 V, sending a negative pulse of -2 Vtoward point B(b). At t =
loading rarely presents a
one conductor to one on a
To, that negative pulse is reflected from point B. It adds
problem with today's
nearby cond uctor-bealgebraically to the 0.5 Von the line and sends a -Ui-V pulse back
state-of-the-art logic decomes an increasingly seritoward point A(c). The reflections then continue as in (d) and (e).
vices. Much more signifious problem as slew rates go up. This its the possible separation to an inad- cant when designing with highsignal coupling is made worse if the equate amount.
speed logic are input and output ac
second trace has a high impedance or
Ground striping, or shielding, is an loading.
if the traces run parallel to one an- effective way to reduce crosstalk
other for more than a few inches and and it makes better use of available INPUT CAPACITANCE
are spaced less than 100 to 150 mils board area. With ground striping, a
Because the input capacitance of a
apart.
ground trace (the stripe) is run be- device impacts the overall perforCrosstalk can be catastrophic to a tween the two parallel traces to act mance of the logic circuit, it should
logic board, sabotaging a conceptu- as a shield. If ground striping is be examined before a particular deally flawless piece of logic design. used, through holes to the ground vice is selected for a design. To enFor example, if a clock line and a data plane should be placed every 1 to 1.5 sure specified performance, the total
line run parallel to each other for inches along the ground strip to elim- load capacitance that a device
more than several inches, and if the inate the possibility of inadvertently drives-including the distributed canoise) system ground for reliable data line cross-couples or superimperformance. A clean system poses its signal onto the clock line,
ground ensures less noise within the the device that the clock is driving
system, and thus ensures good, may detect an illegal level transition.
strong transistor margins. At least
Methods to reduce crosstalk are
10% of the ground connections on the straightforward, though not particpc card should be connected to the ularly elegant. The coupling can be
system ground to reduce card-to- attenuated by separating the adjaground impedance.
cent traces as much as possible. The
Like the ground and power planes trouble with this approach is that
of the individual boards, the overall available board real estate often limgrounding scheme should
be fragmented with sepaA
rate conductors provided
for the various sections of
+2
the system. For example,
all relays, lamps, hard (a)
td
drives, and other noise-2
generating devices should
have their own separate
+2
ground path. The system's
mechanical package (chas- (b)'
t= 0+
sis, panels, and cabinet
2~
doors) should have a dedicated ground. And, of
+2
course, the logic circuitry (e)
0
should have a ground of its
I=To +
own.
-2
~
Those three grounds
+2
should then come together
at the central system (d) 0
1= 1.5 To
ground point, which will
-I---2
usually be located near the
power supply (Fig. 2). This
+2
common-point grounding
I--.
(e)
technique can also be very
--Ieffective in reducing radi-2 1=2T +
ated interference (EMI
andRFI).
-t-
---L-
6-3
DESIGNING WITH
HIGH-SPEED LOGIC
+2.5
u-r-----r--T---r--1.5
(al
(bl
1 4. IDEALLY, THE VOLTAGE
at point B oscillates forever between +2.5Vand1.5 V(a). In reality, it will be a damped ringing (b).
pacitance of the trace-shouldn't exceed the device's specified capacitive
load. Most high-speed logic devices
have a maximum loading of 50 pF. As
a rule of thumb, the maximum load
on any logic element should be no
more than four to six devices for best
speedlload performance. However,
there are some high-slew-rate devices on the market that have higher
output drive capabilities.
BEWARE OF AUTOROUTER
The most common reason for not
following the board-layout principles mentioned so far is having an
autorouter do the layout. Autorouters do what they were designed
to do very well: They place traces so
as to make the most efficient use of
the pc-board real estate. But most
autorouters don't have the capability
to determine which devices are highspeed and which are not. This is
where the logic designer must step in
T
he following ten rules
summarize everything
the logic designer needs
to know when designing
with high-speed CMOS.
1) Keep signal interconnections as
short as possible.
2) Use a multilayer PCB.
.3) Provide ground and power
planes. Discontinuities in the
planes should be avoided because
reflections can occur from abrupt
changes in the characteristic impedance.
and layout sections, or islands, of
high-speed logic by hand in order to
avoid the pitfalls of designing with
high-speed logic.
TRANSMISSION LINES
In addition to the common-sense
layout considerations discussed so
far, designers of high-speed systems
must have at least a basic understanding of transmission lines and
proper termination techniques (see
"Signal Lines Become Transmission Lines, .. p. 76). The reason: As
frequencies go up, wavelengths
come down to the point where they
are of the same order as circuitboard dimensions. Once that happens, any connection between devices should be considered a transmission line. The lumped-element assumption is simply invalid above that
point.
The most common consequence of
failing to consider the distributed na-
ture of a high-speed logic board is
ringing, which is caused by multiple
reflections from the ends of unterminated transmission lines. An unterminated line has no load impedance (R L= 00) and is therefore an impedance-mismatched line. The behavior of this line when connected to
a device with a fast slew rate can be
understood from the following example: Prior to time zero, there's a
steady-state voltage of 2.5 V dc at all
points on the line (Fig. 3a). At t = 0,
an initial TTL voltage transition
from 2.5 V to 0.5 V occurs at point A
(Fig. 3b). Time TD later, the signal
reaches point B and is reflected by
the load reflection coefficient, PL'
The input impedance of the device
at point B is very high with respect to
Zo; RL can be approximated by infinity. By plugging into Eq. 2 from the
box (p. 76), the reflection coefficient
approximately equals +1. In other
words, the voltage reflected by the
load is equal to the incident voltage
(Fig. 3c) . The reflected wave passes
back along the signal path toward
point A (Fig. 3d).
Repeating the calculations for the
sending end of the line (point A),
where Ro;:::: 0, you geta value for the
source reflection coefficient, Ps, of
-1. In other words, there are reflections from the source as well as the
load" but the source reflects the inversion of the wave that is incident
upon.it (Fig. 3e).
Looking just at the behavior of the
signal at point B, the single-step volt-
RUlES TO REMEMBER
4) Fragment the ground and power planes to supply separate sections for high-current switching
devices.
5) Use decoupling capacitors on
every high-speed logic device (0.1
,...F MLC type) located as close to
the Vee pin as possible.
6) Provide the maximum possible
spacing among all high-speed parallel signal leads.
7) Terminate high-speed signal
lines where tR < 2To.
6-4
8) Beware of ac loading conditions
within the design. Exceeding the
manufacturer's recommended operating conditions, especially for
capacitance, can cause problems.
9) When using parallel termination, put bends in all high-speed
signal runs that go to more than
one load. Use a termination load
at the absolute end of the line.
10) Create islands of high-speed
devices on the pc board. This simplifies board layout and ropes-off
the high-speed areas.
111"1H:'IIQQllij,jlm:~'
DESIGNING WITH
HIGH·SPEED LOGIC
~
10
RL =Zo 1+3.Dvdc
[>
I
Zo
5/310
5. THE BASIC PARALLEL
termination scheme works well but
requires a separate 3-V supply (a). The
Thevenin equivalent eliminates the need
for a separate supply. bnt dissipates
extra power from the regular 5-V supply
(b). The use of a capacitor cuts de
dissipation altogether while supplying ac
termination (e).
age transition at t = 0 leads to an endlessly oscillating signal with a total
voltage swing of 4.0 V-twice the
original level transition. The voltage
doubling comes about because the
voltage at point B is the sum of the incident and reflected waves at that
point (Fig. ,4a). Actually, because of
the non-ideal nature of a real circuit
board (finite input and output impedances, losses in the transmission
lines, and so forth), PL will be less
than +1, and Ps will be greater than1. As a result, the reflections will become successively smaller, causing
the famiiiar damped ringing condition (Fig. ,4b).
If the ringing amplitude is large
enough, it can cause the receiving device to see an illegal level transition
and possibly result in spurious logic
states occupying the logic design. In
some cases, the amplitude of the
ringing can actually be large enough
to damage the input of the receiving
device.
I
TERMINATE YOUR TROUBLES
The way to eliminate ringing on a
transmission line is to terminate the
line in its characteristic impedance at
either the sending or receiving end.
The most common way to terminate
a line is with a parallel termination at
the receiving end (Fig. 5).
In the configuration (Fig. 5a), RL
. = Zo and RL is pulled up to 3 V dc. In
principle, RL could be tied to ground,
but TTL-compatible devices could
not then supply the necessary drive.
Solving for PL (Eq. 2), it can be seen
that PL = O. Terminating a line in its
characteristic impedance results in a
reflection coefficient of zero, which
means that there will be no reflections or distortions on the line. Other
than the time delay, TD, the line will
act as if it were a dc circuit. It's important to note that even though devices or gates may be placed at any
location on the line, the terminating
resistor should be placed at the end
of the line. In no case should the line
be split like a Tee to feed several devices in parallel (Fig. 6a). Instead, it
should be serpentined to feed them
sequentially (Fig. 6b).
The 3-V power source shown (Fig.
5a) appears at first to be a major
drawback, but RL and the power supply can be expressed as a Thevenin
equivalent running off the system
power supply of 5 V dc (Fig. 5b). This
variant works well, but the designer
should bear in mind that it dissipates
additional power.
characteristic impedance of the
line-that is, Rs + Ro = ZOL'
Making Rs + Ro equal to ZOL, of
course, creates a voltage divider,
which puts half of the signal amplitude across the line and half across
the series combination of Rs and Ro.
Therefore, with the series termination, the amplitude of the transmitted wave is half of what it would be
without the termination.
Interestingly enougl), the unterminated receiving end of the line precisely compensates for this halving
of the amplitude. The reason is as follows: At the receiving end, the halfamplitude wave is received and a
half-amplitude wave is reflected.
But bear in mind that those are two
separate waves whose amplitudes
add at the point of reflection. As a
result of this addition, the only thing
seen at the receiving end of the line is
a full-size pulse.
The main disadvantage of a series
termination is that the receiving
gate or gates must be at the end of
the line-no distributed loading is
possible. The obvious advantage of a
series termination over a parallel one
is that a series termination doesn't
REDUCING DISSIPATION
A solution that dissipates less
power than either of the others uses
a capacitor to cut the dc dissipation
to zero (Fig. 5c). The recommended
capacitor is a O.I-JA-F MLC type. Several manufacturers produce both capacitor-resistor and pull-up/pulldown termination packs. The pullup/pull-down packs usually come in
a single in-line package (SIP) with
pins on O.I-in. centers, while the capacitor-resistor combination comes
in a standard 16-pin DIP. The most
common SIP pull-up/pull-down resistor values are 2200/3300, 3300/
4700 combinations.
An alternative to a parallel termination at the receiving end is a series
termination at the sending end (Fig.
7). The idea behind serial termination
is to make Ps = 0 and PL = +1. To do
so, RL is made equal to infinity (left
unterminated) and a series resistor is
added at the source to make the overall source impedance equal to the
6-5
.-
(I)
I
(b)
1
6. SERPENTINING ISessenlial
when terminating a line. Never split the
line to feed parallel devices (a). Rather.
feed them sequentially with a serpentined
line (b).
DESIGNING WITH
HIGH-SPEED LOGIC
require any connection to a power
supply.
Transmission-line effects must be
taken into consideration whenever
line propagation delays get up to the
point where a signal transition can
be completed before that signal can
travel down a line, be reflected, and
travel back to its starting point. In
1
7. THE SERIES termination needs
no pulkp supply. Ita main disadvantage
is that it can't handle distributed loads.
other words. lines must be terminatedwhen,
2TD=TR•
CALCULATING DELAY
Taking 2 ns as a typical rise time for a
state-of-the-art high-speed logic device, how long can a board trace get
before its propagation delay gets to
be 1-ns long? For a pc board with a
continuous ground plane and a signal trace on the adjacent layer, the
propagation delay depends on only
one variable, the dielectric constant
of the board material. That delay
time is given by:
t pD = 1.017 (0.475eR + 0.67)112 ns/ft
6-6
For a typical board constructed of
FR4 material, eR (the dielectric constant) is 4.7 to 4.9. If an average eR of
4.8 is used in the equation, then t pD
turns out to be 1.75 ns/ft, which
works out to 6.86 in.lns. As a rule of
thumb, then, any line that is over 7 in.
long should be considered a transmission line and approached accordingly.D
Jock Tomlinson, senior applications engineer at Lattice, holds a
BSEE from Colorado State University.
arcbiteC/llre.1
I'
r
Extending the
..................................................................•...........
22V10 EPLD
......•.........•.............................•........••..•..........•......
T
•
An extelldable
he 22V 10 device architecture is now one of the industry standards in
programmable logic devices. The 22V1O owes its popularity to a number of
architectural features that bring versatility and flexibility to system design. The
Output Logic Macro-Cell (OLMC) 'is perhaps the most revolutionary feature of the
22VIO architecture. OLMCs eliminate such architectural constraints as insufficient
devlce ....11y
product-term access, fixed output polarity, limited three-state control, and poor
_llows,...
_nd 110 counts
tobeboHted
wIIhoat .....or
eIIe..... I..
•
1990
control of registered outputs. The OLMC at any device I/O pin is functionally identical
to any other. Additionally, any 110
can be used as a feedback path into
the AND array.
Asynchronous reset is another
attractive feature of the 22VlO.
One reset signal is common to all
registered OLMCS and operates independently of the dedicated clock
input. This signal is taken from
the AND array and may be generated via a product term. Registered
OLMCS respond immediately to a
reset signal. In addition, one preset signal is common to all registered OLMCS and operates on the
arrival of a valid clock input. This
signal is taken from the AND atray
and may be generated by a product
term. Registered OLMCS respond
only on the atrival of a valid clock
input.
Along with a minimum of eight
product terms per OLMC in all
modes, two outputs have access to
10 product terms per OLMC in all
modes, another two have access to
14 product terms, and the center
twO outputs have access to 16
product terms. Each OLMC's output driver has a unique enable/disable signal that is taken from the
AND array and that may be generated via a product term. AllOLMCS
respond immediately to the arrival
of a valid enable signal generated
externally or internally.
The three members of Lattice's
GAL22VI0 series--the GAL18VlO,
GAL22VlO, and GAL26CV12-ere
high-speed, EECMOS PI.I>5. Each is
based on the standard 22VI0 architecture; their di/lerences involve the
number of 1I00, pins, and product
terms offered. The GAL18VlO is a
20-pin version of the 24-pin
GAL22VlO. It contains eight dedicated input pins (four less than the
22V 10) and 10 I/O (the same as the
22VI0). The 28-pin GAL26CV12
has two more dedicated input pins
and two more 110 pins than the
GAL22VI0. The GAL26CVI2 in a
PLCC package requires no more
space than many lower-density
PLDs.
The EECMOS GAL18VlO and
GAL26CV12 consume just 75 rnA
and 90 rnA typical Icc, respectively-50 percent less power than
bipolar alternatives. The programmable AND arrays are proportional
ro the pin count of each device. The
arrays are 96 X 36, 132 X 44, and
122 X 52 for the GAL18VlO,
GAL22VI0, and GAL26CV12,
respectively.
Reprinted from the 1990 PLD Design Guide - with permission from CMP Publications.
6-7
DESIGN GUIDI!,
The first job that a designer has in
selecting the right 22V 10 device for a
system is to evaluate the size and complexity of the design as well as system speed
and power requirements. PLDs excel in
applications that have a number of SSI
parts with low gate counts and combinational logic that optimally fit into a single device.
The GAL 18V 10 features an equivalent
gate count of 450 to 550 gates, along
with eight to 18 inputs and one to 10
outputs. The GAL22VIO's equivalent
gate count is 550 to 750 gates; it offers
12 to 22 inputs and one to 10 outputs.
The GAL26CVI2 has an equivalent gate
count of 650 to 850, 14 to 26 inputs,
and one to 12 outputs. If a design has a
fairly low gate count and relatively small
1/0 requirements, the GALI8VIO is the
beSt choice. Should additional inputs be
required without any additional output
requirements, the best place to start is
the GAL22V 10. If gate count, input, and
output requirements are large, the
GAL26CV12 is recommended. For designs with larger requirements, some
combination of the three devices will
meet design needs.
The final stages of the evaluation cycle
often reveal problems with a design.
Typically, such problems include the
omission of a critical input signal or a
need for more. Output signals. Such adjustments are best accomplished by repatterning the fuse map of the PLD. This
type of design fix is limited by the number of unused PLD pins available and by
the flexibility of the PLD's internal fusemap array. If the PLD has not been fully
used, a new fuse-map pattern can often
be implemented without any board-level
redesign. If additional 1/0 is necessary,
however, additional parts usually are
needed.
The GAL22V 10 family is well suited for
situations in which greater overall complexity and lower power consumption
must be achieved without a corresponding
increase in device count or real estate use.
With an extendable family, gate and 110
count can be boosted without major
changes in board layout.
When designers are under pressure to
produce a design quickly, the design
cycle is much more chaotic. Many times,
a designer will simply grab the closest
part and use either single parts or multiple parts to build the circuit. When the
final product has been in production for
a few months, the manufacturing-engineering group then must come to grips
with the challenge of cost reduction. In
some cases, these cost-reduction efforts
can also result in reliability gains
PROGRAMMABLE LOGIC
RAW DATA
16
INPUT -.,.......~
(2 BYTES)
~
MULTlPLl!XI!D
CONTROL
INPUTS
2
MULTlPLllXED INTERMI!J)IATE
CONTROL SIGNALS
§
::I :J
I-''--.J
4
'-_~'--_ _~
~
§
::I:J
1-~8_. . PItOCl!SSID DATA
OUTPUT
(I
BYTI!)
Filllre 1. Inlhis eumpl., twa 22¥10 deYices are needed to pnnide Illl!UP ilputs Ind IIIIpId$ fer • state lIIICIIiII.
and performance enhancements.
For example, suppose a designer, in a
rush to build a state machine for control
in a pipeline application, used two
22V lOs ro implement the function (Figure I). The objective of the design is to
take 16 data-input bits and two control
bits to generate eight data-output bits.
In the first device, 16 data inputs and
two control inputs were used to generate
four encoded outputs. Since the first
device was output-bound, only four of
the eight required data bits could be
generated. The second device was used
to take the four encoded outputs from
the first device and the two control inputs to generate the required eight data
output bits.
The above design can be implemented
in a single 26-pin device (Figure 2). The
16 data-input bits and the two control
bits are fed directfy into the
GAL26CVI2, and the remaining two
pins can be used for the required eight
data-output bits. Not only does this approach offer the obvious advantage of
reduced board space, it also saves more
than 0.5 w of power and removes an
entire package delay. Enough power reduction can mean power-supply cost savings and an indirect increase in board
reliability. Performance enhancement results in an extension of the life of an
already mature system.
identify up to 1,024 sequential edge-identified events.
These counters generally are implemented in one of two ways-with multiple 20V8 devices or with a single 22VlO
device. If a 22VIO is used, enough inherent flexibility remains for the implementation of asynchronous reset and
synchronous preset functions. For a 10bit counter built with a 22VlO that
generates an output for every clock
phase, which is appropriate for the implementation of a "watchdog" timer
function for real-time activities, eight
dedicated inputs remain unused. If that
same counter were built with a 20-pin
GALI8VIO, four pins of real estate could
be saved and power use cut by o.fw.
Suppose that same IO-bit counter is
used to signal the "half-full" and "threequarter full" points of a 1,024-location
circular buffer. Two independent event
codes will be needed to decode and generate single clock-width pulses at these two
points in the buffer.
Such a part requires 12 outputs. Previously, multiple 22VI0 devices or the
combination of a 22VI0 component and
another PLD have been used for the task.
Now, the part can be built with a single
28-pin GAL26CVI2, yielding a power
savings of about 1 wand eliminating one
•
package delay.
• A lO-BIT COUNTER DESIGN
A second design example involves a
standard IO-bit counter. A lO-bit counter
can be used to provide location-by-Iocation access of up to 1,024 addresses or to
provide divide-by-two to divide-by-l,024
clock frequency reduction and distribution. A IO-bit counter can also be used to
rIPre 2. Here, a sinale HeY12 replaces twa mlOs lid reduces deIIJS aid .......·suppIJ reqtlire.llb.
6~8
1990
DESIGN ENTRY
ELECTRONIC DESIGN EXCLUSIVE
In-circuit logic device can be
reprogrammed on the fly
Of the multitude of ways available for reconfiguring logic systems on circuit boards, none has
ever proved entirely satisfactory. Changing dozens
of DIP switches or jumper settings manually can be
a nightmare. Electrically erasable or batterybacked memory can do the job at least in part, but
the use of memory bits is limited in most cases to
controlling signal flow in the parts of a system
where speed is not critical.
Memory bits do have their place in controlling
such tasks as decoding
I/O ports, enabling and
disabling features, and
':ompatible with 5- V
selecting a memory
,¥stems, an EEPROMbank, but those jobs are
)ased chip allows
mutually exclusive: De1esigners to update
signers have to decide
which one they want to
,¥stems in situ,
control through the use
vith 100% testing
of memory.
Jnd observability.
The few logic devices
now using UV EPROM
cells cannot be reprogrammed without being removed from the system. Nor, if sealed in windowless plastic packages, are such chips 100% testable.
Even with windows, they usually have to be
removed from the board for erasing and reprogramming, because the 12- to 21-V programming
voltage risks damage to other components on the
board. Other difficulties can arise too with these
techniques, such as mechanical switch failures, wire
breaks or shorts, dead batteries, and mishaps that
occur when technically unskilled users try their
hand at reconfiguring or fixing circuitry.
A new 24-pin chip does away with all those pitfalls. By combining programmable logic circuits
with 5-V electrically erasable CMOS memory, it
opens up all kinds of options in reconfiguring a system. The ispGAL16Z8 not only is reprogrammable
in circuit but also is 100% testable-a big plus.
Propagation delays of a mere 25 to 35 ns mean that
the reprogrammable device can be used in data
ReprInted from ELECTRONIC OESIGN - August 7, 1986
6-9
paths where speed is critical, so that even the system's basic logic flow can be altered in an instant.
The chip is the first in a planned family of insystem reprogrammable devices, and its flexibility
is limited only by the designer's imagination. Logic
designers need not be restricted to that last etch on
the board, and final testing no longer presents so
many problems.
Because the new chip combines CMOS with electrically erasable floating-gate and high-speed logic,
it runs at speeds associated with bipolar chips, but
consumes significantly less power-450 mW maximum and 350 mW on standby-than do most bipolar chips. The 16Z8 is similar to the company's
earlier programmable logic device, the 20-pin
GAL16V8. Four additional pins in the 16Z8 control in-system programming and diagnostic testing
(Fig. I). A proprietary state-machine-based interface controller on the chip handles all programming
and testing. It also makes possible, through the four
pins, the in-system observability and controllability
I
I
that are such powerful diagnostic aids.
Like the 16V8, the new chip has a core consisting of a
standard AND array plane and eight programmable output logic macrocells; it adds 5-V E 2CMOS programming
circuitry. Each programmable output macrocell gives the
designer five configuration options, among them output
polarity (active high or active low), feedback, combinatoriallogic, registered outputs and input selection. Either
all the outputs are connected to one Output Enable signal,
or separate product terms provide individual enabling
controls.
The new chip also emulates all common 20-pin architectures similar to Monolithic Memories' programmable
array logic. Its programming software and hardware support come through the standard PLD development packages. Because its fuse map is compatible with that of the
older chip, the new chip accommodates the latter's software. (Data I/O is the first third-party vendor to offer updated programming; other companies are expected to follow suit shortly.)
state to prevent unwanted writes at power-up. A usercontrolled Reset signal makes the state machine move to
the normal state from any state when the Mode pin is a
logic 1, SOl is a logic 0, and DCLK has a rising edge.
The four interface signals are relatively simple to gen-
Typical write programming sequence
Enter progral'Y1"klg states from the normal state
Step 1 Mode is
Hg'1; SOl is
Hg'1; DCLK is clock
DIag'1ostlc: Preload state (just passI'\g thrClU\tl)
m
m
m
m Hg'1; DClK is clock
Step 2
Mode is
Step 3
Mode is TIL low; SOl is adcI"ess a1d data bits;
DCLK is clock
Program: Shift state
(Load shft regster latch with 82 data bits
a1d 6 adctess bits)
(Note: SDO data field is 'don't care')
SteP 4
Mode is
high; SDlls
Hg'1; DCLK is clock
Program: Read state (just passi1g 1hrClU\tl)
Step 5
Mode is
high; SOl is
Hgh; DCLK is clock
Progrcrn: Write state
(Write beghs irrmedately cpon entering
Progrcrn: write state)
(TIne-out write pulse)
Step 6
Mode is m low; SOl is m high; DCLK is clock
SERIAL PORT SIMPLIFIES INTERFACE
Hg'1; SOIls
Program: Shift state
m
m
m
m
The new chip can be programmed over a - 55°C to
Progrcrn: Read state
(End wr~e)
- 125 ° C operating range and can undergo at least 10,000
Step 7 Mode is m low; SOl is 'don't cae'; clock is DCLK
erase-write cycles. Given its 100% reprogrammability,
Progrcrn: Shift state
yields of 100% in ac and dc parameters are guaranteed, as
(Read address; execution of v~y; shft regster latch
is loaded)
is a programming time of less than I second. The 5-V proStep 8 Mode is m low; SOIls next 88-bit word; clock Is DC\.K,
gramming circuitry generates the necessary higher'voltProgrcrn: Shift state
ages internally and also shapes waveforms so that the de(Shift out 82 data bits a1d 6 address bits; observe SDO)
vice can be programmed through the four-pin interface
Step 9 Repeat steps 4-6 for each row address of v~
without high-cost, high-voltage external hardware.
The four-pin interface controlling programming and diagnostics is compatible with
Monolithic Memories' JEDECstandard ~diagnostics on chip."
By eliminating multiplexed
Internal connection
from SOl pin
data paths, the interface optimizes data propagation. It has
four basic functions: diagnostic
preload, program shift, pro22
gram read, and program write.
E'CMOS
The chip's state machine con64 by 32 programmable
ANOarray
troIs the sequence with infor(ispGAL 16ZS)
mation from three of the four
signal pins: Serial Data In
(SOl) for programming; Mode
15
for loading; and Diagnostic
Clock (DCLK) for diagnostics.
The fourth pin, Serial Data Out
(SOO), for data shifting, comes
Internal connection
into play when the serial scan
from DCLK input pin
data has to be expanded into a
loop (Fig. 2).
When,the chip receives a
1, The 24-pln IspGAL16Z8 starts with an E2CMOS programmable AND array
Power on Reset signal, the state
at Its core and eight output macrocells, Then It adds a serial diagnostic
and programming port and 5-V programming circuitry,
machine resets to the normal
6-10
erate, needing only the output ports of a standard singlechip microprocessor and a little support software. A typical serial scan programming-and-diagnostic control loop
can take on a system with several devices (Fig. 3). In its
normal state, the 16Z8 works like a standard PLD, remembering the last update to the E"CMOS logic and
functioning in the system as programmed. In the diagnos
tic preload state, the chip latches the macrocells' presen
condition and, with DCLK, lets diagnostic test informa
tion move from SDI to SDO. SDI is loaded into the least
significant output register on DCLK's rising edge. Most
significant register data is shifted out through SDO.
When the chip returns to normal, its outputs resume their
preload state.
SHIFT, READ, AND WRITE
In the program shift state, one row of data in the array
is shifted into SDI, with the appropriate array data moving first, followed by the row address field. To configure a
device completely, each array location must be filled with
the appropriate data. Any data already in the serial shift
register is shifted out through SDO for cascading or for
verifying a device.
In the program read state, one row of the array is transferred in parallel into the serial shift register, whose contents are transferred out of the selected row, in the array.
Returning the chip to the program shift state loads the
shift register and lets the user verify the device. However,
if the chip goes to the program write state, the register's
data is programmed to the selected row in the array and
its contents remain unchanged.
In the program write state, one row of the array is programmed with data from the serial shift register. Programming begins on one leading edge of the DCLK signal
'l:itiJ
\
SOl
'tl&l
~
soo
st&J
Mode
SOl
Valid data
and ends on the next; the user must maintain the correct
IO-ms programming timing (see the programming sequence, p. 95).
The chip's in-circuit reprogrammability makes possible the design and programming of generic hardware for
specific applications. Small-volume system manufacturers can blend several lines of hardware into one, simply by
updating the firmware. The fast system upgrades can
even be predesigned into a system and enabled later by reprogramming.
ACHIEVING flEXIBILITY
On-the-spot reprogramming maintains the integrity of
'a system's hardware, eliminating the need for field service
or for returning the chip to the maker for upgrading or replacement. Upgrading can be done in the field by software delivered electronically or by mail, whichever is
more convenient. Furthermore, the chip is programmed
through the serial scan path, so that system diagnostics
are easy to do, either locally or from a remote host system.
Repair time and costs can be cut without significant impact on the system's cost or complexity. Since the chip's
serial scan path is compatible with the ports in other commercial ICs, a complete system, including logic, can use
these powerful and flexible diagnostic techniques.
Two design examples-a programmable two-output,
16-bit input selection decoder and a programmable output port-show off the 16Z8 chip's best points. Normally
rr-l
\~--------lfJ
::J
~~_______Va_lid_d_at_a__~::==r__
~m
SOl
\XXXX"-",,-,,-,,,,->--v_a_lid_d_a_ta_ _
-t~:==r__SDI
N
OCLK
+r<-----7b----j
- - 1 - + 2 + 3 a ....· + I · - - - - - - 3 b - - - - - t -
Normal
Diagnostic: Preload
3a Program: Shift
3b Shift In 82 data and 6 row address bits
4 Program: Read
5
Program: Write (time-out write pulse)
6
Program: Read
78
Program: Shift (parallel shift register loads on
read-ta-shift transition)
7b Shift in 88 bits; verify BB bits
2. During chip programming, just four lines transfer all data and perform diagnostiCS, ensuring that bit
patterns are properly loaded.
6-11
a decoder's circuitry includes such standard logic as address comparators, DIP switches, and pull-up resistors.
The pull-up resistors guarantee noise immunity at the
comparator when a switch is off.
The decoder compares a 16-bit address from a microprocessor with a preset address held in the set of DIP
switches. Decoding the two oUlputs requires four comparators, four octal DIP switches, and four octal resistor
packs. In addition, the circuit needs 104 solder connections and 32 switch contacts, all subject to mechanical
wear and tear.
A single 16Z8 can implement the same decoder.
Switches controlling the address selection functions are
internal and, in fact, are the product terms in the AND
array. All programming occurs through the four-pin
serial interface, and address selection updates are handled
through reliable interactive software, rather than through
a production-line assembler that uses a factory-standard
DIP-switch programming pencil. Moreover, there are
only 24 solder connections and no switch contacts, which
substantially improves reliability and calls for a much
smaller board area.
WORKING TOGETHER
The second application, a reconfigurable output port,
gives systems wide flexibility and can be put together easily. In this setup, two chips work together, one for the output data path and the other for the. microprocessor bus
and output-port control paths (Fig. 4). The data path can
be configured for registered, combinatorial, or latched
outputs, and each output bit can be either active high or
active low. Other Boolean logic manipulations are possible with the logic in the chip's AND array.
The control-path device handles the other chip's Clock
and Output Enable signals, and its inherent logic can implement virtually any microprocessor or output port interface protocol. Interfaces may be synchronous or asynchronous, and each signal set up individually as a
registered or combinatorial output, active high or active
low. The interface can be programmed through the serial
scan programming interface ICs. Thus a single interface
is all that is necessary to tie into many different kinds of
peripherals. 0
Diagnostic
controller
Serial Data In
1
Mode
Single-chip
microcd'1nputer
501
~ Mode
ispGal16ZB
DCLK
I--
500
I
501
~ Mode
ispGal16ZB
DCLK
0
500
r
501
'--Diagnostic Clock - - -
/
Mode
ispGAL 16ZB
DCLK
500
Serial control loop
1
Serial Data Out (500)
3. Through the four-line serial port, several logic
chips can tie into one diagnostic controller for
board-level troubleshooting. Preloading the output registers affords rapid tesllng of programmable devices, since the logic-based circuit can
be made to start at any desired state.
SOl
Mode
DCLK
Data busO
Data bus 7
1
DCLK 501
1
Mode
out~utO
Output 7
ispGAL 16ZB
SDO
A
DE I--
~
1
1-
DCLK 501 Mode
Ao
Bus control outputs
2
A,
-
WR
Interrupt
Acknowledge
Interrupt
State Control
Clock
2
ispGAL 16ZB
Bus control inputs
SDO
I
~
SO o
4. A programmable output port can be readily
formed using two ispGAl16Z8s. The top one sets
up the data path, the bottom one handles interface control and external handshaking. The output situation is very flexible; data can be configured in several ways.
6-12
INTEGRATED CIRCUfI'S
Multiple factors define
true cost of PLDs
By DEAN SUHR
D
esigners using PLDs (programmable logic devices) for system design and manufacturing
traditionally think of piece price as the key
consideration in the PLD selection process.
Thanks to recent advances in technology, however,
the system cost of using PLDs is influenced by factors such as fabrication technology, device quality,
reliability and yield.
System cost is quite different from the sum of the
component costs. The price paid for a device or
component represents only one part of the system
cost of a PLD; the systems team also has to consider
the costs hidden in the programming, handling,
quality control, throughput and overhead that's
necessary to get a "raw" PLD to a functional state
on a board.
Because the true system cost of a PLD is the sum
of the piece price and all of these hidden costs, and
is spread over several functions and departments,
it's often difficult to define and measure. In most
companies, for example, purchasing and engineering define the parts list and acquire the parts.
These departments are often under pressure to reduce absolute unit cost and to purchase the leastexpensive part available.
But the profitability of both the product line and
the company is based not on device acquisition cost
but on total system cost. Buying the least-expensive
part may not provide the lowest t.otal system cost.
l
lao
i
150
§
120
i
140
130
110
100
--
casr
USING
Programmability can playa significant role in the total cost of PlDs. The
exampte above was taken from a system that used 100,000 bipotar PlDs per
ye~r. Moving to E'CMDS GAls cim reduce total cost by up to 34 percent.
DECEMBER 11, 1989
Hidden cast factors
To calculate the system cost of using a particular
PLD type, vendor and technology, managers must
also take into consideration the additional costs of
purchasing overhead, inventory management, prototype inventory and quality assurance (QA). Purchasing overhead can add 2 percent to the actual device
cost. As the number of inventory line items rises,
the overhead needed to purchase those items increases. PLDs with generic architectures can minimize the number of different devices a company
must purchase, and' therefore reduce purchasing
costs.
As much as 10 percent .of a device's cost can be
attributed to inventory management overhead, including shelf space, depreciation, cO\lnt management, obsolete write-offs, and safety stock. Reducing inventory line items simplifies the management
overhead, in turn cutting costs.
BY ELIMINATING YIELD AND HANDLING LOSS,
IMPROVING qlJAI.ITY, AND SlMPLlF'lJNG INVENTORY
MANAGEMENT, DESIGNERS .CAN CUT THE 1'AUE
COST OF USING PlDS
PLDs are particularly adaptable to just-in-time
(JIT) inventory management systems, which minimize inventory py increasing throughput. Using a
JIT system constrains a company's flexibility because the company must carrY fewer items. But
adding PLDs to the inventory will let the same
narrow range of products provide a wide variety of
functions.
Macrocell-based PLDs also have increased the
flexibility of c.ompanies that use them and reduced
stocking requirements. In the past, designers using
fixed-architecture PLDs had to keep in stock every
PLD architecture required for a design. Macrocellbased devices; on the other hand, can be configured
to emulate dozens of old architectures and many
new configurati.ons.
The macr.ocell uS.ed in E'CMOS generic array
logic (GAL) devices goes one step further. These
devices also .offer 100 percent socket cOl'l):patibility
with older programmable array logic (PAL) architectures, so designers can simply substitute the
GAL device fer the old PLD architecture. No redesign is necessary. Existing JEUEC files and master devices can be used, reducing system cost.
Reprinted with permission from PennWell Publications.
6-13
COMPUTER QESIGNS/NEWS EDITION
INTEGRATED CIRCUITS
No longer a simple calculation, the system cost of using
programmable logic devices is affected by their fabrication
technology, testability 'and impact on inventory management.
The cost of the prototype inventory also influences total system cost. Although engineering labs
are stocked with devices for building and debugging prototypes, many companies meet engineering
lab shortages by borrowing from manufacturing
stock. This policy can shrink manufacturing inventories and, by doing so, can increase the system cost
.of the remaining manufacturing units by as much as
1 percent when units are ordered to restock the
shelves.
All PLDs have a programmable element that determines their functionality and ac/dc performance.
These programmable elements can be fabricated
from metal-link fuses, programmable diodes or
transistors, volatile static RAM cells, UV EPROM
cells or EEPROM cells. Each of these technologies
,varies in programmability and has a different impact on device performance and reliability.
Each programmable element also offers a different erase capability. Metal-link and one-time-programmable devices, for instance, can't be erased.
UV EPROM devices can be erased, but this process
requires an expensive windowed package and takes
20 to 30 minutes. EEPROM devices offer instant
erasability in as little as 50 ms. Technologies that
aren't erasable or that have lengthy erase times
constrain test flexibility and may add to the total
system cost.
Finally, PLDs are usually subjected to a complete, electrical QA test upon receipt, which typically adds 7 percent.to the device cost. This additional cost is based on test engineering and manufacturing resources, yield and equipment utilization. Manufacturers can avoid this additional expense without degrading device quality, by using
E'CMOS devices. These devices are 100 percent pretested by the manufacturer, and require no incoming test. And their instant erasability lets IC manufacturers perform extensive tests at the manufacturing stage, prior to shipment to end-users.
Some companies, however, have extensive incoming QA operations that can't be eliminated. Reusable E'CMOS devices are ideal for these operations
because they can be returned to manufacturing inventory after QA testing,: instantly reprogrammed,
and reused in production boards. This flexibility
also lets QA engineers perform their inspection at
any step in the process.
QA engineers can also simplifY their testing by
using generic-architecture, macrocell-based de-
COMPUTER DESIGNS/NEWS EDITION
vices. These devices can be tested with one common test program and then configure in many ways
during the programming operation. This step eliminates the generation and maintenance of multiple
test programs and fixtures, one for each fixed
architecture.
Analyzing the system cost
Managers can reduce these overhead costs to a
formula based on a simple approach that assumes a
percentage cost adder and yield factor for each
The Factor
of Ten rule
It's crucial that managers keep in mind the cost of
detecting and repairing defective PLDs during manufacturing - and the importance of early detection. A common guideline for determining this cost is the Factor of
Ten rule.
This rule states that the cost of detecting and repairing
a defective PLD grows by a factor of ten at each subsequent stage in the manufacturing process. This dramatic
growth rate is possible because other symptoms mask
the PLD's faulty functionality as the device is buried
deeper in the system.
The Factor of Ten rule implies that the earlier defective
devioes are caught, the lower the repair cost. If defects
aren't found early, a very small yield loss can be greatly
magnified by the quantity of devices on a board or in a
system. Even a yield loss as small as 0.5 percent can
result in a 5 percent system failure rate with only five
PLDs per system. A loss of 0.5 percent translates to a
defect rate of 5,000 ppm, a high defect rate.
operation: Costn=Cost n-1+(Costn_1IYield n). This formula is· generic, so managers can tailor the factors
to their specific environment and then analyze the
actual system cost of using a particular PLD.
E'CMOS PLDs offer performance, quality, reliability and, most important, cost advantages over alternative solutions. By eliminating yield and handling
loss, improving quality, and simplifYing inventory
management, designers can significantly reduce the
true cost of using PLDs.
Dean Suhr is product marketing manager at Lattice
Semiconductor, Hillsboro, OR.
Reprinted with permission from PennWell Publications.
6-14
DECEMBER 11, 1989
I'
1
Section 1: Introduction to Generic Array Logic
Introduction to Generic Array Logic
1-1
2
Section 2: GAL Datasheets
Datasheet Levels
GAL16V8A1B
GAL20V8A1B
GAL18V10
GAL22V10/B
GAL26CV12
GAL20RA10
GAL6001
ispGAL16Z8
2-ii
2-1
2-25
2-47
2-61
2-81
2-95
2-109
2-121
Section 3: GAL Military Products
Military Program Overview
MIL-STD-883C Flow
Military Ordering Information
GAL 16V8A1B Military Datasheet
GAL20V8A Military Datasheet
GAL22V10/B Military Datasheet
GAL20RA 10 Military Datasheet
3
3-1
3-2
3-3
3-5
3-13
3-19
3-27
Section 4: Quality and Reliability
Quality Assurance Program
Qualification Program
PCMOS Testability Improves Quality
4-1
4-3
4-5
Section 5,: Technical Notes
GAL Metastability Report
Latch-up Protection
5-1
5-17
Section 6: Article Reprints
Avoid the Pitfalls of High-Speed Logic Design
Extending the 22V1 0 EPLD
In-Circuit Logic Device Can be Reprogrammed on the Fly
Multiple Factors Define True Cost of PLDs
6-1
6-7
6-9
6-13
Section 7: General Information
Development Tools
Copying PAL, EPLD & PEEL Patterns into GAL Devices
GAL Product Line Cross Reference
Package Thermal Resistance
Pack~fJe Diagrams
Tape'::~nd-Reel Specifications
Sales Offices
7-i
7-1
7-3
7-5
7-8
7-9
7-16
7-17
4
5
6
7-ii
DeveloplfJent
Tools
Lattice Semiconductor recommends that customers use
only Lattice qualified programming equipment. Lattice
guarantees 100% programming yield to customers using
qualified programming tools. Below is a matrix that
provides the third-party programmers which are qualified
to program Lattice GAL devices.
Lattice works closely with third-party programming
equipment manufacturers to ensure that customers
achieve the highest programming yields and quality levels.
Lattice's stringent qualification program includes an
evaluation of algorithms, verification of timing and voltage
levels, and a complete yield analysis.
For a current listing of Lattice qualified GAL programmers,
please call Lattice's Literature Distribution Department
(Tel: 503-693-0287; FAX: 503-681-3037) and request a
GAL Qualified programming Hardware List. This
document contains information regarding programmer
revision levels, adapters, and features.
LATTICE QUALIFED PROGRAMMERS (as of May 1991)
Lattice GAL Device Type
Vendor
Programmer
Unisite
2900
DatalJO
29B
60AIH
A1lpro 40
Logical Davlces
PALPR02X
System 3000
Stag
ZL30/A
TURPR0-1
System Genaral
SGUP-85A
SGUP-85
SMS
Mlcrocomputar
Digelec
Sprint Expert
Sprint Plus
Model 860
BP-Mlcrosystems PLD-1100
Prog. Logic Tech. Logic Lab
Advln
Pilot-GL
16V8A
16V8B
2OV8A
2OV8B
18V10
22V10
22V10B
26CV12
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
•
•
•
•
•
20RA10
6001
•
•
0
•
•
•
•
•
0
0
•
•
... Programmer is qualified, refer to the GAL Qualified Programming Hardware list for additional information.
Q .. Programmer was not qualified as of 5191. Contact Lattice or programmer vendor for latest information.
0= Programmer does not support 28-pin devices.
7-1
•
•
•
•
•
•
•
•
•
•
Development Tools
LOGIC COMPILER SUPPORT (as of May 1991)
Lattice GAL Device Type
Vendor
AccelTech.
Programmer
16VSAlB
2OV8A1B
18V10
22V101B
26CV12
20RA10
6001
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
TangoPLD
Data 110
ABEL
ISDATA
LOGliC
Logical Devices CUPL
Mine
PLDesigner
OreAD
OrCADPLD
Omalion
Schema-PLD
• =Compiler supports GAL device type.
o = Contact vendor for support date.
•
•
•
•
•
0
•
Contact vendor or Lattice for the current revision level.
PROGRAMMER/COMPILER VENDORS
Accel Technologies
6825 Flanders Dr.
San Diego, CA 92121
Phone: (619) 554-1000
FAX: (619) 554-1019
Advln Systems
1050-L Duane Ave
Sunnyvale, CA 94086
Phone: (408) 243-7000
Fax: (408) 736-2503
BP Microsystems
10681 Haddington
Suite #190
Houston, TX 77043
Tel: (713) 461-9430
Fax: (713) 461-7431
SSS: (713) 461-4958
Data 110 Corp.
10525 Willows Road N.E.
P.O. Box 97046
Redmond, WA 98073-9746
Phone: (206) 881-6444
FAX: (206) 882-1043
In Europe contact:
Corp.
Data
Phone: +31 (0)20-6622866
In Japan contact:
Corp.
Data
Phone: (03) 432-6991
va
Dlgltronlcs Israel Ltd.
25 Galgaley Haplada St.
Herzliya B 46722
Israel
Tel: 052-559615
fax: 052-555240
In the U.S. contact
Digelec
20144 Plummer st.
Chatsworth, CA 91311
Tel: (818) 701-96n
Fax: (818) 701-5040
Mlnc Incorporated
1575 York Rd.
Colorado Springs, CO 80918
Phone: (719) 590-1155
FAX: (719) 594-4708
Omatlon
801 Presidential
Richardson, TX 75081
Phone: (214) 231-5167
FAX: (214) 783-9072
DrCAD Systems Corp.
3175 N.W. Aloclek Dr.
Hillsboro, OR 97124
Phone: (503) 690-9881
FAX: (503) 690-9891
ISDATAGmbH
Haid-und-Neu-StraBe 7
7500 Karlsruhe 1
West Germany
Phone: 0721-693092
FAX: 0721-174263
In the U.S. contact
ISDATA Inc.
Phone: (408) 373-7359
FAX: (408) 373-3622
Programmable Logic Tech
P.O. Box 1567
Longmont, CO 80501
Tel: (303) 772-9059
Fax: (303) 772-5617
SMS Micro Systems
1M Morgenthal
0-8994 Hergatz
Scwarzenberg
W.Germany
In the U.S. contact:
Encore Technology Corp.
13720 Midway Suite 105
Dallas, TX 75244
Tel: (214) 233-2614
Fax: (214) 233-3122
Logical Devices
1321 N.W. 65th Place.
Fort Lauderdale, FL 33309
Phone: (305) 974-0967
FAX: (305) 974-8531
va
7-2
Stag Mlcrosystems
Martinfield
Welwyn Garden City
Hertz. AL715T
United Kingdom
Phone: 011-44-707-332148
FAX: 011-44-707-371503
In the U.S. contact:
Stag Microsystems
1600 Wyatt Dr.
Santa Clara, CA 95054
Phone: (408) 988-1118
FAX: (408) 988-1232
System General
3FI., No.6, Lane 4
Tun Hwa N. Rd.
P.O. Box: 53-591
Taipei, Taiwan R.O.C.
Phone: 886-2-7212613
FAX: 886-2-7212615
In the U.S. contact:
System General
244 S. Hillview Dr.
Milpitas, CA 95035
Phone: (408) 263-6667
FAX: (408) 262-9220
Copying PAL, EPLD & PEEL
PaffelTJs Into GAL Devices
INTRODUCTION
The generic/universal architectures of Lattice GAL devices
are able to emulate a wide variety of PAL, EPLD and
PEEL devices. GAL devices are direct functional and
parametric replacements for most PLD device
architectures. To use GAL devices in place of other PLD
types, some conversion of the original device pattern may
be needed. This conversion is not difficult, and can be
accomplished at either the design or manufacturing level.
The following sections describe several techniques
available to convert PAL, EPLD and PEEL device patterns
to Lattice GAL device patterns. The following table lists
PLD devices that can be replaced by Lattice GAL devices.
CROSS PROGRAMMING: GAL16V8 AND GAL20V8
The GAL 16V8 and GAL20V8 devices replace most
standard 20-pin and 24-pin PAL devices. To simplify the
conversion process, Lattice has worked with programmer
hardware manufacturers to provide the ability to program
GAL devices directly from existing PAL JEDEC files, or
master PAL devices. Lattice qualified programmers can
automatically configure the architecture of a GAL device
to emulate the source PAL device.
To provide a conceptual framework for the conversion
from PAL devices to GAL devices, a mythical device
known as a RAL device was created. A RAL device is
simply a GAL device configured to emulate a PAL. There
is a one-to-one correspondence between the name of a
PAL device and that .of a RAL device. For example, a
RAL16L8 is simply a GAL16L8 configured as a PAL 16L8.
Some programmers list the RAL device types as choices
for cross-programming, while others specifically state
that a cross-programming operation is to be performed
using a PAL device type as the architecture type.
To program a GAL16V8 or GAL20V8 device from an
existing PAL JEDEC file, simply select the appropriate
device code (either RAL type, or PAL type to crossprogram from), then download the PAL JEDEC file to the
programmer. Insert the appropriate GAL device that can
directly emulate the PAL device (according to the chart on
the following page). The programmer will automatically
configure the GAL device to emulate the PAL device
during programming. The resulting GAL device is 100%
compatible with the original PAL device.
A GAL device may also be programmed from a master
PAL device by reading the pattem of the master PAL into
the programmer memory, then selecting the appropriate
RAL device or PAL type to cross-program from. The GAL
device can then be programmed from the programmer
memory.
CROSS PROGRAMMING: GAL22V10/GAL20RA10
The GAL22V1 0 and GAL20RA10 are direct replacements
for bipolar PAL devices, and are JEDEC fuse map
compatible with these industry standard devices. To
program a GAL22V10 or GAL20RA10 device from an
existing PAL JEDEC file, simply select the appropriate
GAL device code, then download the PAL JEDEC file to
the programmer. The resulting GAL device is 100%
compatible with the original PAL.
GAL devices also may be programmed from Master PAL
devices by reading the pattern of the Master PAL into the
programmer memory, then selecting the appropriate GAL
device code. The GAL device can then be programmed
from the programmer memory.
The GAL22V10 and GAL20RA10 also can store a User
ElectronicSignature (seethe datasheets onthese devices
for more information). To use this feature, the JEDEC file
must contain this information. To add the signature data
to the JEDEC map, use the PALtoGAL conversion utility
(see next section) or recompile the source equations for
a Lattice GAL device instead of a generic 22V10 type.
Many programmers list two device types to differentiate
between the two types of JEDEC files, and list both a
GAL22V10 and a name such as GAL22V10UES or
GAL22V10ES. Other programmers allow both types of
JEDEC files to be accepted, and simply don't program the
Signature fuses if they are not present in the file.
PALTOGAL CONVERSION UTILITY SOFTWARE
Lattice has created a software utility that will convert an
existing PAL device JEDEC file to the appropriate GAL
device JEDEC format. Called PALtoGAL, this software
utility can be used to convert PAL device files to GAL
device files, add or change the User Electronic Signature
without changing device functionality, and reformat existing
GAL JEDEC files for readability.
Since a few programmable logiC devices have features
that a GAL device cannot exactly emulate, the PALtoGAL
utility will clearly describe the incompatibility but will not
create an output file. GAL devices programmed using
files converted by PALtoGAL will be 100% compatible
with the original logic device. PALtoGAL is just another
method of cross-programming, and shoulcJ produce the
same results as using a programmer. The advantage is
that a full GAL device JEDEC map is created, meaning
7-3
COpying PAL Patterns
Into GAL Devices
that the appropriate GAL device may then be selected on
the programmer, which may simplify the manufacturing
flow.
A copy ofthe PALtoGAL conversion utility software can be
obtained through your local Lattice representative, or by
contacting the GAL Applications Hotline at 1-800FASTGAL (327-8425) or (503) 693-0201. The software
alsomaybedownloadedfromLattice'sElectronicBulletin
Board at (503) 693-0215; the file name is
·PALTOGAL.EXE".
SOFTWARE COMPILER CONVERSION
If the equation source file is available for the PAL device,
it can be converted by re-compiling using a suitable logic
compiler that supports GAL devices. If there are any
device incompatibilities (there shouldn't be in most cases),
the compiler will describe the errors. The output of the
compiler will be a GAL JEDEC file that can be used to
program a GAL device directly. The resulting GAL device
will be 100% functionally compatible with the original
device.
Suitable logic compilers are listed in the Development
Tools section. If additional questions arise, contact your
compiler manufacturer or a Lattice Applications Engineer
by calling the GAL Applications Hotline at 1-800-FASTGAL
or (503) 693-0201.
COPYING PAL, EPLD AND PEEL PATTERNS INTO GAL DEVICES
PAll0H8
PAllOl8
PAll0P8
PAlI2H6
PAl12L6
PAlI2P6
PAl14H4
PAlI4H8
PAl14L4
PAlI4L6
PAlI4P4
PAL14P8
PALI6H2
PALI6H6
PALI6H8
PAlI6L2
PALI616
PAlI6L8
PAlI6P2
PAlI6P6
PAlI6P8
, PAlI6R4
PALI6R6
PAlI6R8
PAl16RP4
PAlI6RP6
PAlI6RP8
PAllSH4
PAlI8L4
PAl18P4
~
•
GAL1&Y8AIB
GAl.2GV8AIB
GAll8Vl0
GAL22Y10IB
GAL26CV12
GAL2ORA10
ED
ED
CD
CD
•••
••
•
• ••
•
• ••
•
••
•
••
•
•
••
••
•
••• ••
PAlI8P8
PAL18U8
PAl.2OH2
PAl2OH8
PAL2Ol2
PAL2OL8
PAL20P8
PAl2OR4
PAl2OR6
PAl2OR8
PAl2ORP4
PAl2ORP6
PAL2ORP8
PAL20RA10
PAL22Vl0
PALCE16V8
PALCE20V8
PALCE22Vl0
PAlCE2&V12
PEELI8CV8
EP320
85C220
85C224
GALI6V8AIB
GAL20V8AIB
Ci)
G
CD
Ell
CD
Ell
0
0
CD
Ell
0
0
Ell
CD
ED
Ell
CD
(9
t9
t9
t9
CD
G
Q)
~
0
0
••
•••
••
••
••
••
0
0
0
e
e
GAl1&V8AIB
GAL2OV8AIB
GAl18Vl0
GAL22V101B
GAL26CVI2
GAL20RA10
e
e
e
e
e
e
e
0
e
e
0
•
•
e
0
•
0
0
e
e
0
e
e
e
• Direct Replacement. with Cross ProgralMing Available.
(!) Direct Replacemem. no Cross ProgralMing Availiable.
o Direct Replacement. wtth same Function Restrictions.
7-4
GAL Product Line
Cross Reference
MANUFACTURER PART #
ALTERA
AMD
EP310
EP320
EP330
MANUFACTURER PART #
LATTICE PART #
AMD
GAl16V8A1B'
or... GAl18V1 0
PAl10H8
PAl10l8
PAl12H6
PAl12l6
PAl14H4
PAl14l4
PAl16H2
PAl16l2
GAl16V8A1B
PAl16l8
PAl16R4
PAl16R6
PAl16R8
PAlC16l8
PAlC16R4
PAlC16R6
PAlC16R8
AmPAl16L8
AmPAl16R4
AmPAl16R6
AmPAl16R8
PAl16P8
PAl16RP4
PAl16RP6
PAl16RP8
GAl16V8AIB
PAlCE16V8
GAl16V8AIB
AmPAl18P8
PAlC18U8
GAl16V8A1B'
or... GAl18V1 0
PAl14l8
PAl16l6
PAl18l4
PAl20l2
GAL20V8AIB
PAl20L8
PAL20R4
PAl20R6
PAL20R8
AmPAL20RP4
AmPAL20RP6
AmPAL20RP8
GAl20V8AIB
PALCE20V8
GAL20V8A1B
PAl20RA10
GAL20RA10
LATTICE PART #
AmPAl20RP10
GAL22V10/8
PAl20S10
PAl20RS4
PAl20RS8
PAl20RS10
GAl22V10/8
AmPAl20L10
PAL20L10
PA!-20X4
PAl20X8
PAL20X10
GAl22V10/B'
AmPAL22V10
PAl22V10
PAlC22V10
PAlCE22V10
GAl22V10/8
PAlCE24V10
PAlCE26V12
GAl26CV12'
ATMEL
AT22V10
GAl22V10/8
CYPRESS
PALC16L8
PALC16R4
PALC16R6
PALC16R8
GAL16V8AIB
PLDC18G8
GAL 16V8A1B'
or... GAl18V1 0
PALC20CG10
PALC22V10
PAl22V10
GAl20V8A1B'
or... GAL22V10/8
PlD20RA10
GAl20RA10
HARRIS
HPl16LC8
HPl16RC4
HPl16RC6
HPL16RC8
GAl16V8AIB
ICT
PEEL18CV8
GAL16V8A1B'
or... GAl18V1 0
PEEl153
PEEL253
GAl16V8A18'
or... GAl18V1 0'
PEEL20CG10
GAl20V8A18'
PEEL22CV10A or... GAl22V10/8
1) Possible conversion but not 100% compatible to this device.
7-5
GAL Product Une
Cmss Reference
MANUFACTURER PART #
INTEL
NATIONAL
MANUFACTURER PART #
LArnCE PART #
5C031
5C032
S5C220
GAL16VSAIB'
or... GAL 1SV1 0
S5C224
GAL20VSAlB'
or... GAL22V101B
PAL 10HS
GAL16VSAIB
PAL10LS
PAL12H6
PAL12L6
PAL14H4
PAL14L4
PAL16H2
PAL16L2
GAL16VSAIB
PAL16LS
PAL16R4
PAL16R6
PAL16RS
GAL16VSAIB
GAL16VS
GAL16VSA
GAL16VSAlB
GAL1SV10
GAL1SV10
PAL14LS
PAL16L6
PAL1SL4
PAL20L2
GAL20VSAIB
PAL20LS
PAL20PS
pAL20R4
PAL20RP4
PAL20R6
PAL20RP6
PAL20RS
PAL20RPS
GAL20VSAIB
PAL20RA10
GAL20RA10
PAL20L10
PAL20X4·
PAL20XS
PAL20X10
GAL22V101B'
GAL22V10
GAL22V101B
GAL26CV12
GAL26CV12
GAL6001
GAL6001
RICOH
SAMSUNG
SG5-THOMSON
SIGNETICS
SPRAGUE
1) Possible conversion but not 100% compatible to this device.
7-6
LArnCE PART #
EPL10PS
EPL12P6
EPL14P4
EPL16P2
GAL16VSAIB
EPL16PS
EPL16RP4
EPL16RP6
EPL16RPS
GAL16VSAlB
CPL16LS
CPL16R4
CPL16R6
CPL16RS
GAL16VSAlB
CPL20LS
CPL20R4
CPL20R6
CPL20RS
GAL20VSAIB
CPL22V10
GAL22V10/B
GAL16VS
GAL16VSAIB
GAL20VS
GAL20VSAlB
GAL39V1S
GAL6001
GAL16ZS
ispGAL16ZS
PLHS16LS
PLUS16Ls
PLUS16R4
PLUS16R6
PLUS16RS
GAL16VSAIB
PLHS1SPS
GAL 16VSAlB'
or... GAL1SV1 0
PLS153
PHD16NS
GAL16VSAlB'
or... GALlSV10'
PLUS20LS
PLUS20R4
PLUS20R6
PLUS20RS
GAL20VSAIB
SPL14LCS
SPL16LCS
SPL16RC4
SPL16RC6
SPL16RCS
GAL16VSAlB
GAL Product Une
Cross Reference
MANUFACTURER PART #
SPRAGUE
n
LATTICE PART #
SPL18LC4
SPL20LC2
GAL20V8AIB
SPL20LC8
SPL20RC4
SPL20RC6
SPL20RC8
GAL20V8A1B
TIBPAL16L8
TIBPAL16R4
TIBPAL16R6
TIBPAL16R8
GAL16V8A1B
TICPAL16L8
TICPAL1.6R4
TICPAL16R6
TICPAL16R8
GAL16V8A1B
GAL16V8A1B
EP330
TIBPAD16N8
GAL16V8A1B'
or... GAL18V1 0'
TIBPAL20L8
TIBPAL20R4
TIBPAL20R6
TIBPAL20R8
GAL20V8A1B
TIBPAL22V10
TICPAL22V10
GAL22V10!B
1) Possible conversion but not 100% compatible to this device.
7-7
Package Thel,nal
Resistance
The following table provides information on the package
thermal resistance of Lattice commercial and industrial
grade devices. For information on the package thermal
resistance of Lattice military grade devices, please refer
to "MIL-M-38510, Appendix Co.
mounted on a thermal test board conforming to SEMI
SPECIFICATION G42-88: "Thermal Test Board
Standardization for Measuring Junction-to-Ambient
Thermal Resistance of Semiconductor Packages".
Test Conditions
Testing was performed per SEMI TEST METHOD G3887: "Still and Forced-Air Junction-to-Ambient Thermal
Resistance Measurements of IC Packages· with devices
Power Dissipation = O~5watts (IC chip reverse biased)
Ambient Air Velocity =Zero (still air)
Ambient Temperature =65°C
Measuring Current =3mA
PACKAGE THERMAL RESISTANCE
Commercial/Industrial Grade Devices
Package Type:
Device Type:
20-Pin Plastic DIP
°JA
°JC
GAL16V8A1B
GAL18V10
59°C/W
39°C/W
24-Pin Plastic DIP
GAL20V8A1B
GAL22V10/B
GAL20RA10
GAL6001
ispGAL16Z8
57°C/W
36°CIW
28-Pin Plastic DIP
GAL26CV12
55°CIW
33°CIW
20-Pin Plastic LCC
GAL16V8A1B
GAL18V10
46°CIW
32°CIW
28-Pin Plastic LCC
GAL20V8A1B
GAL22V101B
GAL20RA10
GAL26CV12
GAL6001
45°CIW
29°CIW
7-8
Package Diagrams
20-Pin plastic DIP
Dimensions In Inches MIN. I MAX.
(:::::::: :I=r
I'
.--
-I
~.o15MIN
1
I:
.055 I
-I~ ~ \-
.000 1.015
~~~
r- --i r-
.0lI0
E
ii
~~
.0lI0 I .110
:::
24-pin plastic DIP
Dimensions In Inches MIN. I MAX.
1.270 MAX
l~
~m1~015MIN
~ r- ~ ~ ~~::;.oSS I .090
.090 I .110
7-9
.0081.016
0-11"
Package Diagrams
28-Pin plastic DIP
Dimensions In Inches MIN. I MAX.
a
-II- ~ \-
1.355 MAX
.009/.015
.015 MIN
.020 1.030
.090/.110
7-10
0·15"
Package Diagrams
20-Pio PLCC Package
Dimensions In Inches MIN. I MAX.
.Il42 /.048 X 45°
.042 /.048 X 45°
.G13 / .1121
.385/ .385
Top View
.280 /.330
I---~,_:::jl
~
til f-:~:
I-----,-~'H....
I r=
·-n
28-Pio PLCC package
Dimensions In Inches MIN. I MAX.
•042 / .048 X 45°
.013/.021
.390/ A30
I - - - - - - _,_
1---~--
ASS/ADS
~
~I
~
7-11
.165/.180
~11 ~
.025MIN
.090/.120
Package Diagrams
20-Pin (300 MIL) CERDIP
Dimensions in Inches MIN. I MAX.
w
fl
.0OB/.015
.080 MAX
.080/.110
7-12
0.15"
Package Diagrams
24-pin (300 MIL) CEBDIP
Dimension. In Inche. MIN. I MAX.
'-/.1115
.GIll MAX
'-1.110
7-13
..." •
Package Diagrams
20-Pin LCC
Dimensions in Inches MlN.t MAX•
.030 I .050 X 45· (t, 0")
.00sl.030 X 4S· (t,O")
.0SOlYP.
f..-..I.0581.072
7-14
Package Diagrams
28-Pin LCC
Dimensions In Inches MIN. I MAX•
l
•0351 .045 X 45° (± 0.5°)
rr--"","",rvr~~IlIr"1VT,"",""".-r-'lVr_·O_~ .o~
.........
1
X 45° (± 0.5°)
.050 TYP.
BoltomVI_
.075 TYP.
.050TYP.
H
.0631.077
Top View
.44 1.458
1--/.0541 .066
7-15
Tape and Reel
Specifications
A tape-and-reel packing container is available for plastic
leaded chip carriers to protect the product from mechanicaV
electrical damage and to provide an efficient method for
handling. Lattice's tape-and-reel containers are shipped
in full compliance to Electronics Industry Association
Standard EIA-RS481.
The tape-and-reel packing system consists of a pocketed
carriertape loaded with one device per pocket. Aprotective
cover tape seals the carrier tape and holds the devices in
the pockets. A full reel holds a maximum quantity of
devices depending on the package size. Lattice requires
ordering in full reel quantities. Once loaded, the tape is
wound onto a plastic reel for labeling and packing.
Devices packaged in tape-and-reel containers must be
factory programmed (pre-pattemed). Custom marking of
devices prior to mounting on tape-and-reel is available
upon request. Contact your local Lattice sales office for
more details on Lattice's tape-and reel packing system.
TAPE·AND-REEL QUANTITIES AND DIMENSIONS
Package
PLCC
Pin Count
Carrier Tape Dimensions
Width
Pitch
Quantity Per
13 Inch Reel
20-pin
16mm
12mm
1000
28-pin
24mm
16mm
750
7-16
Sales Offices
DIRECT SALES OFFICES
FRANCE
Lattice Semiconductor
Les Bureaux de Sevres
72-78, Grand Rue
92310 Sevres
France
TEL: 1-45 341010
FAX: 1-462671 36
~EBMAtiX
Lattice Semiconductor
Stahlgruberring 12
8000 Munich 82
West Germany
TEL: (089) 42 01 107
FAX: (089) 422 731
~
Lattice Semiconductor
Peony Kikuchi 201
1-8-4, Botan
Koto-ku, Tokyo
Japan 135
TEL: 03-642-0621
FAX: 03-642-0629
tlQBltf AMEBI~A
MAIZIZA~I::I!.!lZETTS
Lattice Semiconductor
67 S. Bedford St.
Suite 400 West
Burlington, MA 01803
TEL: (617) 229-5819
FAX: (617) 272-3213
QLlFOBNIA
Lattice Semiconductor
1731 Technology Dr.
Suite 590
San Jose, CA 95110
TEL: (408) 441-0196
FAX: (408) 441-0739
QBEGQtI
Lattice Semiconductor
5555 N.E. Moore Ct.
Hillsboro, OR 97124
TEL: (503) 780-6771
FAX: (503) 681-3037
mA!Z
MltltlEIZCITA
Lattice Semiconductor
13664 Hannibal Circle
Apple Valley, MN 55124
TEL: (612) 891-5200
FAX: (612) 891-5205
Lattice Semiconductor
Carlsbad Pacific Ctr. One
701 Palomar Airport Rd.
3rd Floor
Carlsbad, CA 92009
TEL: (619) 931-4751
FAX: (619) 431-1821
Lattice Semiconductor
100 Decker Ct. Ste. 280
Irving, TX 75062
TEL: (214) 650-1236
FAX: (214) 650-1237
tlEW JERIZEX
Lattice Semiconductor
175-3C Fairfield Rd.
West Caldwell, NJ 07006
TEL: (201) 744-5908
FAX: (201) 509-9309
GEQBGlA
Lattice Semiconductor
3105 Medlock Bridge Rd.
Norcross, GA 30071
TEL: (404) 446-2930
FAX: (404) 416-7404
NORTH AMERICAN SALES REPRESENTATIVES
ALABAMA
The Novus Group
2905 Westcorp Blvd. #120
Huntsville, AL 35805
(205) 534-0044
ARIZQNA
Summit Sales
7802 E. Gray Rd. #600
Scottsdale, AZ 85260
(602) 998-4850
QLlEQBNIA
Bager Electronics
17220 Newhope St. #209
Fountain Valley, CA 92708
(714) 957-3367
Earle Associates
7585 Ronson Rd. #200
San Diego, CA 92111
(619) 278-5441
GEQBGlA
The Novus Group
6115A Oakbrook Pkwy.
Norcross, GA 30093
(404) 263-0320
c()LQBADQ
Waugaman Associates
4800 Van Gordon
Wheat Ridge, CO 80033
(303) 423-1020
IlLltlQl1Z
Omni Electronics
328 E. Main
Barrington, IL 60010
(708) 381-9087
~QtltlEIm~!.!I
Comp Rep Associates
117 Church St.
Yalesville, CT 06492
(203) 269-1145
KAtllZAlZ
Stan Clothier Company
805 Clairborne
Olathe, Kansas 66062
(913) 829-0073
Bager Electronics
6324 Variel Ave. #314
Woodland Hills, CA 91367
(818) 712-0011
ElQRIDA
Sales Engineering Concepts
776 S. Military Trail
Deerfield Beach, FL 33442
(305) 426-4601
Criterion Sales
3350 Scott Blvd, Bldg.44
Santa Clara, CA 95054
(408) 988-6300
Sales Engineering Concepts
600 S. Norhtlake Blvd. #230
Altamonte Spgs, FL 32701
(407) 830-8444
MABXLAtiD
Deltatronics
24048 Sugar Cane Ln.
Gaithersburg, MD 20882
(301) 253-0615
7-17
MAlZlZA~I::I!.!IZETTS
Comp Rep Associates
100 Everett Street
Westwood, MA 02090
(617) 329-3454
MICl::IlGAti
Greiner & Associates
15324 E. Jefferson Ave.
Grosse Pointe Park, MI
48230
(313) 499-0188
MltltlElZQIA.
Stan Clothier Company
10000 W. 76th St #0
Eden Prairie, MN 55344
(612) 944-3456
MIIZIZQ!.!BI
Stan Clothier Company
3910 Old Highway 94 South
St. Charles, MO 63303
(314) 928-8078
Effective: April 1991
North American
Sales Representatives
NEW JERSEY
Technical Marketing Group
175-3C Fairfield Rd.
West Caldwell, NJ 07006
(201) 226-3300
QI:IlQ
I.EXM
Makin & Associates
3165 Lynwood Rd.
Cincinnati, OH 45208
(513) 871-2424
West Associates
4615 Southwest Fwy #720
Houston, TX 77027
(713) 621-5983
NEW MEXICO
Summit Sales
2651 K Pan American N.E.
Albuquerque, NM 87107
(505) 345-5003
Makin & Associates
6400 Riverside Dr. Bldg. A
Dublin, OH 43017
(614) 793-9545
West Associates
9171 Capital of Texas
North Houston Bldg. #120
Austin, TX 78759
(512) 343-1199
NEW YORK
Technical Marketing Group
20 Broad Hollow Rd.
Melville, NY 11747
(516) 351-8833
Tri-Tech Electronics
300 Main S!.
E. Rochester, NY 14445
(716) 385-6500
Tri-Tech Electronics
14 Westview Dr.
Fishkill, NY 12524
(914) 897-5611
Tri-Tech Electronics
6836 E. Genesee S!.
Fayetteville, NY 13066
(315) 446-2881
NORTH CAROLINA
The Novus Group
102L Commonwealth Ct.
Cary, NC 27511
(919) 460-7771
Makin & Associates
32915 Aurora Ave. #270
Solon, OH 44139
(216) 248-7370
OKLAHOMA
West Associates
9717 E. 42nd St. #125
Tulsa, OK 74146
(918) 665-3465
West Associates
801 E. Campbell Rd. #350
Richardson, TX 75081
(214) 680-2800
YIAI:t
Waugaman Associates
876 East Vine St.
Murray, UT 84107
(801) 261-0802
OREGON
Northwest Marketing
6975 SW Sandburg Rd.
#330
Portland, OR 97223
(503) 620-0441
VIRGINIA
Deltatronics
1439 Gills Rd.
Powhatan, VA 23139
(804) 492-9027
PENNSYLVANIA
Deltatronics
921 Penllyn Pike
Blue Bell, PA 19422
(215) 641-9930
WASHINGTON
Northwest Marketing
12835 Bel-Red Rd. #330N
Bellevue, WA 98005
(206) 455-5846
CANAPA
ALBERTA
Dynasty Components
Calgary, Alberta
(403) 560-1212
BRITISH COLUMBIA
Dynasty Components
Vancouver, British Columbia
(604) 597-0068
ONTARIO
Dynasty Components
174 Colonade Rd. S.
Unit 21
Nepean, Ontario
Canada, K2E 7J5
(613) 723-0671
Dynasty Components
Toronto, Ontario
(416) 672-5977
QUEBEC
Dynasty Components
Montreal, Quebec
(514) 694-0275
INTERNATIONAL SALES REPRESENTATIVES AND DISTRIBUTORS
AUSTRALIA
Zatek Components
Level 2, 96 Phillip S!.
Paramatta 2150
Australia
TEL: (02) 895-5534
FAX: (02) 895-5535
BELGIUM
A.leom Electronics B. V.BA
Singel3
2550 Kontich
Belgium
TEL: 03-458 30 33
FAX: 03-458 31 26
AUSTRIA
Ing. E. Steiner GmbH.
Hummelgasse 14
A-1130 Wien
Austria
TEL: (43) 222-827-4740
FAX: (43) 222·828-5617
PENMARK
Ditz Schweitzer
Vallensbaekvej 41
Postboks 5,
DK-2605 Brendby
Denmark
TEL: (45) 42 45 30 44
FAX: (45) 42 45 92 06
TLX: 85533257
FINLANP
TelercasOY
Luomannotko 6
02200 Espoo
Finland
TEL: (358) 0-452·1622
FAX: (358) 0-452-3337
TLX: 857123212
Franelee
ZI Les Glaises
6·8 Rue A. Ctoizat
91124 Palaiseau Cedex
France
TEL: (33) 16 9202002
FAX: (33) 169207469
TLX: 842250067
FRANCE
Aquitech
2 Rue Alexis De Tocqueville
92138 Antony Cedex
France
TEL: (33) 140969494
FAX: (33) 140969300
DataDis
3 Bis Rue Rene Cassin
B.P84
91303 Massey Cedex
France
TEL: (33) 69-20 4141
FAX: (33) 69-204900
7-18
Effective: April 1991
International Sales Representatives
and Distributors
W.GERMANY
Alfatron GmbH.
Stahlgruberring 12
8000 Munich 82
West Germany
TEL: (49) 894204 910
FAX: (49) 8942049159
TLX: 5216935
HONG KONG
RTI Industries Co. Ltd.
A19, 10th Floor
Proficient Ind. Centre
6, Wang Kwan Rd.
Kowloon, Hong Kong
TEL: (852) 795 7421
FAX: (852) 795 7839
IHI21A
Hindetron
33/44A, 8th Main Road
Rajmahal Vilas Ext.
Bangaore, India 560-080
TEL: (91) 812 348 266
FAX: (91) 812345 022
IRELAND
Silicon Concepts
3 Mills View Close
Dukesmeadow, Kilkenny
Kilkenny County
Ireland
TEL: (353) 566 4002
~
Unitec
Rechov Maskit 1
Herzlia B, PO Box 2123
Israel 46120
TEL: (972) 52 576006
FAX: (972) 52 576790
TLX: 922341990
lIALY.
Comprel Rep
Viale F. Testi, 115
20092 Cinosello B. Milano
Italy
TEL: (39) 2-61206415
FAX: (39) 2-61280526
IlAfAH
Ado Electronic Indust. Co.
4th Floor, Fukui Building
No. 2-12 Sotokanda
2-Chome, Chiyoda-ku
Tokyo 101
Japan
TEL: (81) 3-3257-2600
FAX: (81) 3-3251-6796
TLX: 7812224754
Japan Macnics Corp.
Hakusan High-Tech Park
1-22-2 Hakusan-cho,
Midori-ku
Yokohama, 226
Japan
TEL: (81) 45-939-6140
FAX: (81) 45-939-6141
TLX: 78128988
Hakuto Company, Ltd.
2-29, Toranomon, 1 chome
Minato-Ku, Tokyo 105
Japan
TEL: (81) 3-3597-8910
FAX: (81) 3-3597-8975
TLX: J22912BRAPAN
Hoei Denki
6-60, 2-Chome, Niitaka
Chiyoda-Ku,
Osaka 532, Japan
TEL: (81)63941113
FAX: (81) 63965647
TLX: 5233694HOEIDK J
~
Ellen & Company
Suite #302 IlOOk Bldg.
1602-4 Seocho-Dong
Seocho-ku, Seoul
Republic of South Korea
TEL: (82) 02 587 5724
FAX: (82) 02 5851519
NETHERLANDS
Alcom Electronics B.V.
Essebaan 1
2908 W Capelle Aan
Den Ijssel
The Netherlands
TEL: (31) 104519533
FAX: (31) 104586482
TLX: 26160
NORWAY
Henaco AIS
Trondheimsveien 436
Ammerud
Oslo 9 Norway
TEL: (47) 2162110
FAX: (47) 2257780
TLX: 76716
SINGApORE
Technology Distribution
14 Sungei Kadut Ave.
#03-00
Singapore 2572
TEL: (65) 368 6065
FAX: (65) 368 0182
SOUTH AFRICA
Multikomponent
Cnr. Vanacht & Gewel St.
Isando 1600, P.O Box 695
Republic of South Africa
TEL: (27) 11 974 1525
FAX: (27) 11 3922463
TLX: 960426905
SWEDEN
Pelcon Electronics
Fagerstagatan 6-8
S-163 08 Spanga
Sweden
TEL: (46) 8 795 9870
FAX: (46) 8 760 7685
SWITZERLAND
Ascom Primotec AG
Tafernstrasse 37
CH-5405 Baden-Dattwil
Switzerland
TEL: (41) 5684-0171
FAX: (41) 5683-3454
TLX: 828 221 apri ch
Lite-On Inc.
9F NO 3 Tunghua South Rd.
Taipei, Taiwan
Republic of China
TEL: (886) 2-7769-950
FAX: (886) 2-7712-344
TLX: 785-15283
UNITED KINGDOM
Macro Marketing
Burnham Lane
Slough SL 1 6LN
England
TEL: (44) 628 604383
FAX: (44) 628 666873
TLX: 851847945
Micro Call
17 Thame Park Rd.
Thame, Oxon OX9 3XD
England
TEL: (44) 84426-1939
FAX: (44) 84 426-1678
Silicon Concepts
PEC LynchOOrough Rd.
Passfield, Liphook
Hampshire GU30 7SB
England
TEL: (44) 428 77617
FAX: (44) 428 77603
Silicon Concepts
The Green
Painshawfield Road
Stocksfield
Northumberland NE43 7PX
Scotland
TEL: (44) 661-843955
FAX: (44) 661-843955
TAIWAN
Master Electronics Corp.
16F
#810 Tunghua South Rd.
Taipei, Taiwan
Republic of China
TEL: (886) 02-735-7316
FAX: (886) 02-735-0902
•
Effective: April 1991
North American Distributors
NORTH AMERICAN DISTRIBUTORS
ALABAMA
Arrow Electronics
1015 Henderson Rd.
Huntsville, AL 35816
(205) 837-6955
Marshall Industries
3039 Kilgore Ave. #140
Rancho Cordova, CA 95670
(916j 635-9700
Marshall Industries
26637 Agoura Rd.
Calabasas, CA 91302-1959
(818) 878-7000
Merit Electronics
2070 Ringwood Ave.
San Jose, CA 95131
(408) 434-0800
Marshall Industries
9320 Telstar Ave.
EI Monte, CA 91731-3004
(818) 307-6000
ARIZONA
Arrow Electronics
4134 E. Wood St.
Phoenix, /liZ. 85040
(602) 437-0750
SOUTHERN
CALIFORNIA
Arrow Electronics
19748 Dearborn St.
Chatsworth, CA 91311
(818) 701-7500
Marshall Industries
One Morgan
Irvine, CA 92718
(714) 458-5301
Bell Industries
140 S. Lindon Ln. #102
Tempe, /liZ. 85281
(602) 267-7774
Arrow Electronics
2961 Dow Ave.
Tustin, CA 92680
(714) 838-5422
Insight Electronics
1525 W. University Dr.
Suite #105
Tempe, /liZ. 85281
(602) 829-1800
Arrow Electronics
9511 Ridgehaven Ct.
San Diego, CA 92123
(619) 565-4800
Marshall Industries
3313 Memorial Pkwy S.
Huntsville, AL 35801
(205) 881-9235
Marshall Industries
9830 S. 51st St. #B121
Phoenix, /liZ. 85044
(602) 496-0290
NORTHERN
CALIFORNIA
Arrow Electronics
Kitting Services Division
1180 Murphy Ave.
San Jose, CA 95131
(408) 452-3550
Bell Industries
4311 Anthony Ct. #100
Rocklin, CA 95677
(916) 367-2095
Bell Industries
1161 N. Fairoaks Ave.
Sunnyvale, CA 94089
(408) 734-8570
Insight Electronics
1295 Oakmead Pkwy.
Sunnyvale, CA 94086
(408)720-9222
Marshall Industries
336 Los Cocbes St.
Milpitas, CA 95035
(408) 942-4600
Bell Industries
30101 Agoura Ct. #118
Agoura Hills, CA 91301
(818) 706-2608
Bell Industries
11812 San Vicente #300
Los Angeles, CA 90049
(213) 826-6778
Bell Industries
11095 Knott Ave. #E
Cypress, CA 90630
(714) 895-7801
Bell Industries
7827 Convoy Ct. #403
San Diego, CA 92111
(619) 268-1277
Insight Electronics
28038 Dorothy Dr. #2
Aquora, CA 91301
(818) 707- 2100
Insight Electronics
6885 Flanders Dr. #C
San Diego, CA 92121
(619) 587-0471
Insight Electronics
15635 Alton Pkwy. #120
Irvine, CA 92718
(714) 727-3291
Marshall Industries
10105 Carroll Canyon Rd.
San Diego, CA 92131
(619) 578-9600
Sterling Electronics
9340 Hazard Way #3A
San Diego, CA 92123
(619) 560-8097
Sterling Electronics
1342 Bell Ave.
Tustin, CA 92680
(714) 259-0900
Sterling Electronics
9410 Topanga Canyon #103
Chatsworth, CA 91311
(818) 407-8850
COLOBAOO
Arrow Electronics
3254C Fraser St.
Aurora, CO 80011
(303) 373-5616
AVED
4090 Youngfield St.
Wheat Ridge, CO 80033
(303) 422-1701
Bell Industries
12421 W. 49th Ave.
Wheat Ridge, CO 80033
(303) 424-1985
Marshall Industries
12351 N. Grant
Thornton, CO 80241
(303) 451-8383
!:;QHHECTIC!.II
Arrow Electronics
12 Beaumont Rd.
Wallingford, CT 06492
(203) 265-7741
7-20
Marshall Industries
20 Sterling Dr.
PO Box 200
Wallingford, CT 06492-0200
(203) 265-3822
FLORIDA
Arrow Electronics
400 Fairway Dr.
Deerfield Beach, FL 33441
(305) 429-8200
Arrow Electronics
37 Skyline Dr.
Bldg. 0, Suite 3101
Lake Mary, FL32746
(407) 333-9300
Bell Industries
600 S. Norhtlake Blvd. #100
Altamonte Springs, FL 32701
(407) 339-0078
Marshall Industries
380 S. Northlake Rd. #1024
Altamonte Springs, FL 32701
(407) 767-8585
Marshall Industries
2700 Cypress Ck. Rd. #0114
Ft. Lauderdale, FL 33309
(305) 977-4880
Marshall Industries
2840 Scherer Dr. #410
St. Petersburg, FL 33716
(813) 573-1399
Vantage Components
1110 Douglas Ave. #2050
Altamonte Springs, FL 32714
(407) 682-1199
Vantage Components
1761 W. Hillsboro #318
Deerfield Beach, FL 33441
(305) 429-1001
GEORGIA
Arrow Electronics
4205E River Green Pkwy.
Duluth, GA 30136
(404) 497-1300
JACO
6035 Atlantic Blvd. #J
Norcross, GA 30071
(404) 449-9508
Effective: April 1991
North American Distributors
MARYLAND
Arrow Electronics
8300 Guilford Dr.
Columbia, MD 21046
(301) 995-6002
MISSOURI
Arrow Electronics
2380 Schuetz Rd.
St. Louis, MO 63146
(314) 567-6888
Arrow Electronics
375 Collins Rd. NE
Cedar Rapids, IA 52402
(319) 395-7230
Marshall Industries
2221 Broadbirch Dr.
Silver Springs, MD 20904
(301) 622-1118
Marshall Industries
3377 Hollenberg Dr.
Bridgeton, MO 63044
(314) 291-4650
ILUNOIS
Arrow Electronics
1140 W. Thorndale Ave.
ltasca,lL 60143
(312) 250-0500
Vantage Components
6925 Oakland Mills Rd.
Columbia, MD 21045
(301) 720-5100
NEW JERSEY
Arrow Electronics
4 East Stow Rd. Unit 11
Marlton,NJ 08053
(609) 596-8000
Marshallindustries
5300 Oakbrook Pkwy #140
Norcross, GA 30093
(404) 923-5750
IQWA
Bellindustries
870 Cambridge Dr.
Elk Grove Village, IL 60007
(312) 640-1910
MA§§ACt:l!.!§ETTS
Arrow Electronics
25 Upton Dr.
Wilmington, MA 01887
(508) 658-0900
Marshallindustries
50 E. Commerce Dr. Unit 1
Schaumberg,lL 60173
(708) 490-0155
Interface Electronic Corp.
228 South Street
Hopkinton, MA 01748
(508) 435-9521
INPIANA
Arrow Electronics
7108 Lakeview Pkwy. W. Dr.
Indianapolis, IN 46268
(317) 299-2071
Marshall Industries
33 Upton Dr.
Wilmington, MA 01887
(508) 658-0810
Bellindustries
5230 W. 79th St.
Indianapolis, IN 46268
(317) 875-8200
Custom Service Electronics
8730 Commerce Park PI. #A
Indianapolis, IN 46268
(317) 879-9119
Marshallindustries
6990 Corporate Dr.
Indianapolis, IN 46278
(317) 297·0483
MICt:llGAN
Arrow Electronics
3510 Roger Chaffee Mem.
Blvd. SE
Grand Rapids, MI
(616) 243-0914
Arrow Electronics
19880 Haggerty Rd.
Uvonia. MI48152
(313) 462·2290
Bell Industries
28003 Center Oaks Ct. #B1
Wixon, MI 48393
(313) 347-6633
KAN§A§
Arrow Electronics
8208 Melrose Dr. #210
Lenexa, KS 66214
(913) 541-9542
Marshall Industries
31067 Schoolcraft
Uvonia, MI48150
(313) 525-5850
Marshallindustries
10413 W. 84th Terr.
Pine Ridge Business Park
Lenexa, KS 66214
(913) 492-3121
MINNE§OTA
Arrow Electronics
10120A West 76th Street
Eden Prairie, MN 55344
(612) 829-5588
Arrow Electronics
6 Century Dr.
Parsippany-Trow Hills, NJ
07054
(201) 538-0900
Marshall Industries
101 Fairfield Rd.
Fairfield, NJ 07006
(201) 882-0320
Marshall Industries
158 Gaither Dr.
Mt. Laurel, NJ 08054
(609) 234-9100
Vantage Components
23 Sebago St.
Clifton, NJ 07013
(201) m-4100
NEW MEXICO
Bell Industries
11728 Unn NE
Albuquerque, NM 87123
(505) 292·2700
NEW YORK
Arrow Electronics
25 Hub Drive
Melville, NY 11747
(516) 391-1300
Arrow Electronics
200serAve.
Hauppauge, NY 11788
(516) 231-1000
Arrow Electronics
3375 Brighton-Henrietta
Townline Rd.
Rochester, NY 14623
(716) 427-0300
Marshall Industries
3955 Annapolis Lane
Plymouth, MN 55447
(612) 559·2211
7-21
JACO
145 Oser Ave.
Hauppauge, NY 11788
(516)273-5500
Marshall Industries
275 Oser Ave.
Hauppauge, NY 11788
(516) 273-2424
Marshall Industries
1250 Scottsville Rd.
Rochester, NY 14624
(716) 235-7620
Marshall Industries
100 Marshall Drive
Endicott, NY 13790
(607) 785-2345
Vantage Components
1056 Jericho Turnpike
Smithtown, NY 11787
(516) 543-2000
NOW CAROLINA
Arrow Electronics
5240 Greens Dairy Rd.
Raleigh, NC 27604
(919) 876-3132
Marshall Industries
5224 Greens Dairy Rd.
Raleigh, NC 27604
(919) 878-9882
JACO
3029·105 Stonybrook Dr.
Raleigh, NC 27604
(919) 876·7767
QJ:II.Q
Arrow Electronics
6573E Cochran Rd.
Solon, OH 44139
(216) 248-3990
Arrow Electronics
8200 Washington Village Dr.
#A
Centerville, OH 45458
(513) 435-5563
Bell Industries
444 Windsor Park Dr.
Dayton, OH 45459
(513) 435-8660
Marshall Industries
3520 Park Center Dr.
Dayton, OH 45414
(513) 898-4480
Effective: April 1991
I:
Nolth American DistributolS
Marshall Industries
30700 Bainbridge Rd. Unit A
Solon, OH 44139
(216) 248-1788
Insight Electronics
15437 McKaslde
Sugarland, TX n478-1311
(713) 448-0800
Insight Electronics
12002115th Ave. NE
Kirkland, WA 98034
(206) 820-8100
OKLAHOMA
Arrow Electronics
12111 East 51st St. #101
Tulsa, OK 74146
(918) 252-7537
JACO
4251-A Kellway Circle
Addison, TX 75244
(512) 835-0220
Marshall Industries
11715 N. Creek Pkwy. S.
Suite 112
Bothell, WA 98011
(206) 486-5747
OREGON
Arrow Electronics
9275 S.W. Nimbus Ave.
Beaverton, OR 97005
(503) 627-7667
Bell Industries
6024 S.W. Jean Rd.
Lake Oswego, OR 97035
(503) 635-6500
Insight Electronics
8705 SW Nimbus #200
Tigard, OR 97005
(503) 644-3300
Marshall Industries
9705 SW Gemini Dr.
Beaverton, OR 97005
(503) 644-5050
E!EHH§XllAHIA
Marshall Industries
401 Parkway View Dr.
Pittsburgh, PA 15205
(412) 788-0441
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Arrow Electronics
2227 West Braker Lane
Austin, TX 78758
(512) 835-4180
Arrow Electronics
3220 Commander Dr.
Carrollton, TX 75006
(214) 380-6464
Arrow Electronics
10899 Kingflurst Dr. #100
Houston, TX n099
(713) 530-4700
Insight Electronics
12703-A Research Blvd. #1
Austin, TX 78759
(512) 467-0800
Insight Electronics
1n8 Plano Rd. #320
Richardson, TX 75081
(214) 783-0800
JACO
2120 M. Bracker Lane
Austin, TX 78758
(512) 835-0220
JACO
1005 Industrial Blvd.
Sugarland, TX n478
(713) 240-2255
Marshall Industries
8504 Cross Park Dr.
Austin, TX 78754
(512) 837-1991
Marshall Industries
7250 Langtry
Houston, TX n040
(713) 895-9200
Marshall Industries
2045 Chenault Street
Carrollton, TX 75006
(214) 233-5200
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Arrow Electronics
1946 West Parkway Blvd.
Salt Lake City, UT 84119
(801) 973-6913
Bell Industries
6912 S. 185th West #B
Midvale, UT 84047
(801) 255-9611
Marshall Industries
2355 South 1070 West
Salt Lake City, UT 84119
(801) 973-2288
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Arrow Electronics
14320 NE 21st St.
Bellevue, WA 98007
(206) 643-4800
Bell Industries
16650 NE 79th, Suite 103
Redmond, WA 98052
(206) 867-5410
WISCONSIN
Arrow Electronics
200 North Patrick Blvd.
Brookfield, WI 53005
(414) 792-0150
Bell Industries
W226 N. 900 Eastmound Dr.
Waukesha, WI 53186
(414) 547-8879
Marshall Industries
20900 Swenson Dr. #150
Waukesha, WI 53186
(414) 797-8400
CANADA
ALBERTA
Future Electron·ics
3833-29th Street
Calgary, Alberta
Canada, T2A 5Nl
(403) 250-5550
Future Electronics
4606-97th Street
Edmonton, Alberta
Canada, T6E 5N9
(403) 438-2858
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Arrow Electronics
8544 Baxter Place
Burnaby, British Columbia
Canada, V5A 4T8
Future Electronics
1695 Boundary Road
Vancouver, British Columbia
Canada, V5K 4X7
(604) 294-1166
MAHIIQ&A
Future Electronics
lOOKing Edward
Winnipeg, Manitoba
Canada, R3H ON8
(204) 786-n11
7-22
ONTARIO
Arrow Electronics
36 Antares Dr. Unit 100
Nepean, Ontario
Canada, K2E 7W5
(613) 226-6903
Arrow Electronics
1093. Meyerside Dr.
Mississauga, Ontario
Canada, 15P 1M4
(416) 670-n69
Future Electronics
1050 Baxter Road
Ottawa, Ontario
Canada, K2C 3P2
(613) 820-8313
Future Electronics
5935 Airport Rd., #200
Mississauga, Ontario
Canada, L4 V 1W5
(416) 612-9200
Marshall Industries
4 Paget Rd.
Bldg. 1112, Unit 10
Brampton, Ontario
Canada, L6T 5G3
(416) 458-8046
QUEBEC
Arrow Electronics
1100 St. Regis Blvd.
Dorval, Quebec
Canada, H4P 2T5
(514) 421-7411
Future Electronics
237 Hymus Blvd.
Pointe Claire, Quebec
Canada, H9R 5C7
(514) 694-n10
Future Electronics
1000 St.Jean Babtiste #100
Quebec City, Quebec
Canada, G2E 5G5
(418) 8n-6666
Marshall Industries
148 Brunswick Blvd.
Pointe Claire, Quebec
Canada, H9R 5B9
(514) 694-8142
Effective: April 1991
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