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MICROCOMMUNICATIONS

1991

About Our Cover:
Thinkers, inventors, and artists throughout history have breathed
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Local Area Networks

Wide Area Networks

Other Components

Modem Products
PCM Codec/Filter
and Combo

Table of Contents
Alphanumeric Index .......................................................
AP-302 Microcommunications Overview .....................................

xi
xii

SECTION ONE-DATA COMMUNICATIONS COMPONENTS
CHAPTER 1
Local Area Networks
CSMA/CD Access Method
DATA SHEETS
82586 IEEE 802.3 Ethernet LAN Coprocessor. . . . . . . . .. . .. . . . . . . . . . . . . . . . . . . .
82596CA High-Performance 32-Bit Local Area Network Coprocessor . . . . . . . . . . . .
82596DX and 82596SX High-Performance 32-Bit Local Area Network
Coprocessor ...........................................................
82588 High Integration Local Area Network Controller .........................
82590 Advanced CSMAlCD LAN Controller with 8-Bit Data Path .. . . . . . . . . . . . . ..
82C501 AD Ethernet Serial Interface . .. . . .. . . . . . .. . . .. . . . . . . . . . . . . . . .. . . . . . ..
82521TB Twisted Pair Ethernet Serial Supercomponent. . . . . . . . . .. . . . . . .. . . . . ..
82504TA Transceiver Serial Interface (TSI) . . . .. .. . . . . . . . . . . . . . . . . . . . . .... . . ..
82505TA Multiport Repeater Controller (MPR) ................................
82506TB Twisted Pair Medium Attachment Unit (TP MAU) . . . . . . . . . . . . . . . . . . . . ..
APPLICATION NOTES
AP-235 An 82586 Data Link Driver .................................•........
AP-236 Implementing StarLAN with the Intel 82588 . . .. . . . . . . . . . . . . . . . . . . .. . . ..
AP-344 Interfacing Intel 82596 LAN Coprocessors with M68000 Family
Microprocessors ...................... : ............. ; . . . . . . . . . . . . . . . . . ..
AP-345 Implementing 1OBASE-T Networks with Intel's Twisted Pair Ethernet
Components and Supercomponents ......................... ~ . . . . . . . . . . . ..

1-1
1-38
1-110
1-186
1-212
1-245
1-263
1-283
1-300
1-321
1-337
1-418
1-494
1-570

CSMA/CD Access Method Evaluation Tools
PC586E CSMAlCD LAN Evaluation Board ................................... 1-594

CHAPTER 2
Wide Area Networks
DATA SHEETS
8251A Programmable Communication Interface .... , .......... '" . .. . ... . . . . . .
82050 Asynchronous Communications Controller .............................
82510 Asynchronous Serial Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
8273 Programmable HDLC/SDLC Protocol Controller. . . . . . . . . . . . . . . . . . . . . . . . . .
8274 Multi-Protocol Serial Controller (MPSC) .................................
82530/82530-6 Serial Communications Controller (SCC) ............. : . . . . . . . .•
APPLICATION NOTES
AP-401 Designing With the 82510 Asynchronous Serial Controller. . . . . . . .. . . . . ..
AP-310 High Performance Driver for 82510 .. . .. . . . . . . . . . . . . . . . . . . .. . . .. .. . . ..
AP-36 Using the 8273 SDLC/HDLC Protocol Controller . . . . . . . .. . . . . . . . . . . . . . ..
AP-134 Asynchronous Communication with the 8274 Multiple-Protocol Serial
Controller ............................................................. ,
AP-145 Synchronous Communication with the 8274 Multiple Protocol Serial
Controller ........................................................ ; . . . ..
AP-222 Asynchronous and SDLC Communications with 82530 ................. ,

2-1
2-26
2-40
2-80
2-112
2-150
2-182
2-263
2-295
2-348
2-387
2-426

CHAPTER 3
Other Components
DATA SHEETS
8291A GPIB Talker/Listener ......................................... ' . . . . . .
8292 GPIB Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1
3-33

Table of Contents (Continued)
8294A Data Encryption/Decryption Unit. . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . .
APPLICATION NOTES
AP-166 Using the 8291A GPIB Talker/Listener .... , . . . . . .. ... . ... . .. . .. ... .. . .
AP-66 Using the 8292 GPIB Controller. . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . .

3-52
3-65
3-96

SECTION TWO-TELECOMMUNICATION COMPONENTS
CHAPTER 4
Modem Products
DATA SHEETS
89024 2400 BPS Intelligent Modem Chip Set ..•................ ;.............
89C024LT Error Correcting Laptop Modem Chip-Set .......... ; • . . . . . . . . . . . . . . .
89C024FT V.42/42bis Modem Chip Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EVALUATION KITS
'
MD024LT Modem Demo Board .... : ....................................... ;
MD024FT Modem Demo Board.............................................
89024 MEK2 89024 Enhanced Modem Evaluation Kit ......... ; ..• . . . . . . . .. ... .
MEK3 Modem Evaluation Kit...............................................
APPLICATION BRIEF
AB-24 89024 Modem Customization for V.23 Data Transmission ................

4-1
4-23
4-46
4-69
4-70
4-71
4-73
4-75

CHAPTERS
PCM Codec/Filter and Combo
DATA SHEETS
2910A PCM Codec-micro Law 8-Bit Companded AID and 0/ A Converter. . . . . . . . .
2911A-1 PCM Codec-A Law8-Bit Companded AID and D/A Converter..........
2912A PCM Transmit/Receive Filter. . . . . . . . . . . . . . . . . . . . . • . . . • . . . . . . . . . . . . . . .
2913 and 2914 Combined Single-Chip PCM Codec and Filter ...................
2916/2917 HMOS Combined Single Chip PCM Codec and Filter ................
APPLICATION NOTES
Applications Information 2910Al2911A12912A ...............................
AP-142 Designing Second-Generation Digital Telephony Systems Using the Intel
2913/14 Codec/Filter Combochip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .

5-1
5-19
5-34
5-46
5-67
5-85
5-88

Alphanumeric Index
2910A PCM Codec-micro Law 8-Bit Companded AID and D/ A Converter ..... . . . . . . . . . .
2911A-1 PCM Codec-A Law 8-Bit Companded AID and D/A Converter.................
2912A PCM Transmit/Receive Filter ...............................................
2913 and 2914 Combined Single-Chip PCM Codec and Filter. . . . . . . . . . . . . . . . . . . . . . . . . .
2916/2917 HMOS Combined Single Chip PCM Codec and Filter. . . . . . . . . . . . . . . . . . . . . . .
82050 Asynchronous Communications Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82504TA Transceiver Serial Interface (TSI).. .. . . . . . . . .. . .. . . . . .. . .. . . . . .. . . ... . . . . ..
82505TA Multiport Repeater Controller (MPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82506TB Twisted Pair Medium Attachment Unit (TP MAU) ............................
8251 0 Asynchronous Serial Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8251A Programmable Communication Interface.....................................
82521TB Twisted Pair Ethernet Serial Supercomponent ..............................
82530/82530-6 Serial Communications Controller (SCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
82586 IEEE 802.3 Ethernet LAN Coprocessor. . . . . . . . .. . . . . .. . . . . . . . . . . . .. .. . . . . . . . .
82588 High Integration Local Area Network Controller. .. . . . . . . . . . . . . . . . . . . . . . ... . .. ..
82590 Advanced CSMAlCD LAN Controller with 8-Bit Data Path. . . . . . . . . . . . . . . . . . . . . ..
82596CA High-Performance 32-Bit Local Area Network Coprocessor. . . . . . . . . . . . . . . . . . .
82596DX and 82596SX High-Performance 32-Bit Local Area Network Coprocessor ......
8273 Programmable HDLC/SDLC Protocol Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8274 Multi-Protocol Serial Controller (MPSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8291A GPIB Talker/Listener. . . . .. . . . . .. .. .. . .. . . . . . . . . . . . . . .. . .. . .. . . . . .•... . ... .
8292 GPIB Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
8294A Data Encryption/Decryption Unit. . .. .. . . . . .. . .. . . . .. . . . . . .. . . .. . . . .. . . . . . . . .
82C501AD Ethernet Serial Interface . . . . . . .. . . .. . . .. . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . ..
89024 2400 BPS Intelligent Modem Chip Set .....................................' . . .
89024 MEK2 89024 Enhanced Modem Evaluation Kit................................
89C024FT V.42/42bis Modem Chip Set ............................................
89C024LT Error Correcting Laptop Modem Chip-Set .................................
AB-24 89024 Modem Customization for V.23 Data Transmission .................... ; . .
AP-134 Asynchronous Communication with the 8274 Multiple-Protocol Serial Controller. ..
AP-142 Designing Second-Generation Digital Telephony Systems Using the Intel 2913/14
Codec/Filter Combochip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AP-145 Synchronous Communication with the 8274 Multiple Protocol Serial Controller. . ..
AP-166 Using the 8291 A GPIB Talker/Listener . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AP-222 Asynchronous and SDLC Communications with 82530. . . . . . . . . . . . . . . . . . . . . . . ..
AP-235 An 82586 Data Link Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-236 Implementing StarLAN with the Irite I 82588 ..................................
AP-302 Microcommunications Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AP-310 High Performance Driver for 82510. . .. . .. . . . . . . . . . . . . . . . . . . .. .. . . .. ... . .. ...
AP-344 Interfacing Intel 82596 LAN Coprocessors with M68000 Family Microprocessors..
AP-345 Implementing 10BASE-T Networks with Intel's Twisted Pair Ethernet Components
and Supercomponents .........................................................
AP-36 Using the 8273 SDLC/HDLC Protocol Controller .. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-401 Designing With the 82510 Asynchronous Serial Controller. . . . . . . . . . . . . . . ... . . . ..
AP-66 Using the 8292 GPIB Controller ............................ : . . . . . . . . . . . . . . . . .
Applications Information 291 OAl2911 Al2912A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MD024FT Modem Demo Board....................................................
MD024LT Modem Demo Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEK3 Modem Evaluation Kit..................................................... .
PC586E CSMAlCD LAN Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5-1
5-19
5-34
5-46
5-67
2-26
1-283
1-300
1-321
2-40
2-1
1-263
2-150
1-1
1-186
1-212
1-38
1-110
2-80
2-112
3-1
3-33
3-52
1-245
4-1
4-71
4-46
4-23
4-75
2-348
5-88
2-387
3-65
2-426
1-337
1-418
xii
2-263
1-494
1-570
2-295
2-182
3-96
5-85
4-70
4-69
4-73
1-594

inter

AP-302

Kobayashi's macro vision hints at the obstacles confronting the future of C&C. When taken to the micro
level, to silicon itself, one begins to understand the
complexities that are involved. When Intel invented the
microprocessor fifteen years ago, the first seeds ofthe
personal computer revolution were sown, marking an
era that over the last decade has dramatically influenced the way people work and live. PCs now proliferate in the office, in factories, and throughout laboratory
environments. And their "intimidation" factor has lessened to where they are also becoming more and more
prevalent in the home, beginning to penetrate a market
that to date has remained relatively untapped.

OVERVIEW
Imagine for a moment a world where all electronic
communications were instantaneous. A world where
voice, data, and graphics could all be transported via
telephone lines to a variety of computers and receiving
systems. A world where the touch of a finger could
summon information ranging from stock reports to
classical literature and bring it into environments as
diverse as offices and labs, factories and living rooms.
Unfortunately, these promises of the Information Age
still remain largely unfulfilled. While computer technology has accelerated rapidly over the last twenty
years, the communications methods used to tie the wide
variety of electronic systems in the world together have,
by comparison, failed to keep pace. Faced with a tangle
of proprietary offerings, high costs, evolving standards,
and incomplete technologies, the world is still waiting
for networks that are truly all-encompassing, the missing links to today's communications puzzle.

Thanks to semiconductor technology, the personal
computer has raised the level of productivity in our
society. But most of that productivity has been gained
by individuals at isolated workstations. Group productivity, meanwhile, still leaves much to be desired. The
collective productivity of organizations can only be enhanced through more sophisticated networking
technology. We are now faced with isolated "islands
of automation" that must somehow be developed
into networks of productivity.

Enter microcommunications-microchip-based digital
communications products and services. A migration of
t he key electronics communications functions into silicon is now taking place, providing the vital interfaces
that have been lacking among the various networks
now employed throughout the world. Through the evolution ofVLSI (Very Large Scale Integration) technology, microcommunications now can offer the performance required to effect these communications interfaces
at affordable costs, spanning the globe with silicon to
. eradicate the troublesome bottleneck that has plagued
information transfer during recent years.

But no amount of computing can meet these challenges
if the corresponding communications technology is not
sufficiently in step. The Information Age can only grow
as fast as the lowest common denominator-which in
this case is the aggregate communications bandwidth
that continues to lag behind our increased computing
power. Such is the nature of the communications bottleneck, where the growing amounts of information we
are capable of generating can only flow as fast as the
limited and incompatible communications capabilities
now in place. Clearly, a crisis is at hand.

"There are three parts to the communications puzzle,"
says Gordon Moore, Intel Chairman and CEO. "The
first'incorporates the actual systems that communicate
with each other, and the second is the physical means
to connect them-such as cables, microwave technology, or fiber optics. It is the third area, the interfaces
between the systems and the physical links, where silicon will act as the linchpin. That, in essence, is what
microcommunications is all about."

BREAKING UP THE BOTTLENECK
Three factors have contributed to this logjam: lack of
industry standards, an insufficient cost/performance
ratio, and the incomplete status of available communications technology to date.
• Standards-One look at the tangle of proprietary
systems now populating office, factory, and laboratory environments gives a good indication of the
inherent difficulty in hooking these diverse systems
together. And these systems do not merely feature
different architectures-they also represent completely different levels of computing, ranging from
giant mainframes at one end of the scale down to
individual microcontrollers on the other.
The market has simply grown too fast to effectively
accommodate the changes that have occurred. Suppliers face the dilemma of meshing product differentiation issues with industry-wide compatibility as

THE COMMUNICATIONS
BOTTLENECK
Visions of global networks are not new. Perhaps one of
the most noteworthy of these has been espoused by Dr.
Koji Kobayashi, chairman of NEC Corporation. His
view of the future, developed over the nearly fifty years
of his association with NEC, is known as C&C (COlllputers and Communications). It defines the marriage of
passive communications systems and computers as
processors and manipulators of information, providing
the foundation for a discipline that is changing the basic character of modem society.

xii

inter

•

AP-302

they develop their strategies; opting for one in the
past often meant forsaking the other. And while
some standards have coalesced, the industry still
faces a technological Tower of Babel, with many
proprietary solutions vying to be recognized in leadership positions.
Cost/Performance Ratio-While various communications technologies struggle toward maturity,
the industry has had to cope with tremendous costs
associated with interconnectivity and interoperation. Before the shift to microelectronic interfaces
began to occur, these connections often were prohibitively expensive.
Says Ron Whittier, Intel Vice President and Director of Marketing: "Mainframes offer significant
computing and communications power, but at a
price that limits the number of users. What is needed is cost-effective communications solutions to
hook together the roughly 16 million installed PCs
in the market, as well as the soon-to-exist voice/
data terminals. That's the role of microcommunications-bringing cost-effective communications solutions to the microcomputer world."
Incomplete Technology-Different suppliers have
developed many networking schemes, but virtually
all have been fragmented and unable to meet the
wide range of needs in the marketplace. Some of
these approaches have only served to create additional problems, making OEMs and systems houses
loathe to commit to suppliers who they fear cannot
provide answers at all of the levels of communications that are now funneled into the bottleneck.

The distances over which information may be transmitted via a WAN are essentially unlimited. The goal of
ISDN is to take what is largely an analog global system
and transform it into a digital network by defining the
standard interfaces that will provide connections at
each node.
These interfaces will allow basic digital communications to occur via the existing twisted pair of wires that
comprise the telephone lines in place today. This would
bypass the unfeasible alternative of installing completely new lines, which would be at cross purposes with the
charter of ISDN: to reduce costs and boost performance through realization of an all-digital network.
The second category, Local Area Networks, represents
the most talked-about link provided by microcommunications. In their most common form, LANs are comprised of-but not limited to-PC-to-PC connections.
They incorporate information exchange over limited
distances, usually not exceeding five kilometers, which
often takes place within the same building or between
adjacent work areas. The whole phenomenon surrounding LAN development, personal computing, and distributed processing essentially owes its existence to microcomputer technology, so it is not surprising that this
segment of networking has garnered the attentioll it has
in microelectronic circles.
Because of that, progress is being made in this area.
The most prominent standard-which also applies to
WANs and SANs-is the seven-layer Open Systems Interconnectiou (OSI) Model, established by the International Standards Organization (ISO). The model provides the foundation to which all LAN configurations
must adhere if they hope to have any success in the
marketplace. Interconnection protocols determining
how systems are tied together are defined in the first
five layers. Interoperation concepts are covered in the
upper two layers, defining how systems can communicate with each other once they are tied together.

THE NETWORK TRINITY
Three principal types of networks now comprise the
electronic communications marketplace: Wide Area
Networks (WANs), Local Area Networks (LANs), and
Small Area Networks (SANs). Each in its own fashion
is turning to microcommunications for answers to its
networking problems.

In the LAN marketplace, a large number of networking
products and philosophies are available today, offering
solutions at various price/performance points. Diverse
approaches such as Star LAN, Token Bus and Token
Ring, Ethernet, and PC-NET, to name a few of the
more popular office LAN architectures, point to many
choices for OEMs and end users.

W ANs-known by some as Global Area Networks
(GANs)-are most commonly associated with the
worldwide analog telephone system. The category also
includes a number of other segments, such as satellite
and microwave communications, traditional networks
(like mainframe-to-mainframe connections), modems,
statistical multiplexers, and front-end communications
processors. The lion's share of nodes--electronic network connections-in the WAN arena, however, resides in the telecommunications segment. This is where
the emerging ISDN (Integrated Services Digital Network) standard comes into focus as the most visible
portion of the WAN marketplace.

A similar situation exists in the factory. While the
Manufacturing Automation Protocol (MAP) standard
is coalescing around the leadership of General Motors,

xiii

AP-302

Boeing, and others, a variety of proprietary solutions
also abound. The challenge is for a complete set of interfaces to emerge that can potentially tie all of these
networks together in-and among-the office, factory,
and lab environments.

the LAN segment, which should grow from 34.5% of
the total silicon microcommunications market in 1985
to 44.5%of the expanded pie in 1989.
Opportunities abound for microcommunications suppliers as the migration to silicon continues. And
perhaps no VLSI supplier is as well-positioned in this
marketplace as Intel, which predicts that 50% of its
products will be microcommunications-related by 1990.
The key here is the corporation's ability to bridge the
three issues that contribute to the communications bottleneck: standards, cost-performance considerations,
and the completeness of microcomputer and microcommunications product offerings.

The final third of the network trinity is the Small Area
Network (SAN). This category is concerned with communications over very short distances, usually not exceeding 100 meters. SANs most often deal with chip-tochip or chip-to-system transfer of information; they are
optimized to deal with real-time applications generally
managed by microcontrollers, such as those that take
place on the factory floor among robots at various
workstations.

INTEL AND VLSI: THE
MICROCOMMUNICATIONS MATCH

SANs incorporate communications functions that are
undertaken via serial backplanes in microelectronic
equipment. While they represent a relatively small market in 1986 when compared to WANs and LANs, a
tenfold increase is expected through 1990. SANs will
have the greatest number of nodes among network applications by the next decade, thanks to their prepone
derance in many consumer products.

Intel innovations helped make the microcomputer revolution possible. Such industry "firsts" include the
microprocessor, the EPROM, the E2PROM, the
microcontroller, development systems, and single board
computers. Given this legacy, it is not surprising that
the corporation should come to the microcommunications marketplace already equipped with a potent arsenal of tools and capabilities.

While factory applications will make up a large part of
the SAN marketplace probably the greatest contributor
to growth will be in automotive applications. Microcontrollers are now used in many dashboards to control
a variety of engine tasks electronically, but they do not
yet work together in organized and efficient networks.
As Intel's Gordon Moore commented earlier this year
to the New York Society of Security Analysts, when
this technology shifts into full gear during the next decade, the total automobile electronics market will be
larger than the entire semiconductor market was in
1985.

The first area centers on industry standards. As a VLSI
microelectronic leader, Intel has been responsible for
driving many of the standards that are accepted by the
industry today. And when not actually initiating these
standards, Intel has supported other existing and
emerging standards through its longtime "open systems" philosophy. This approach protects substantial
customer investments and ensures easy upgradability
by observing compatibility with previous architectures
and industry-leading standards.

MARKET OPPORTUNITIES

Such a position is accentuated by Intel's technology relationships and alliances with many significant names
in the microcommunications field. Giants like AT&T
in the ISDN arena, General Motors in factory networking, and IBM in office automation all are working
closely with Intel to further the standardization of the
communications interfaces that are so vital to the
world's networking future.

Such growth is· also mirrored in the projections for the
WAN and LAN segments, which, when combined with
SANs, make up the microcommunications market pie.
According to Intel analysts, the total silicon microcommunications market in 1985 amounted to $522 million.
By 1989, Intel predicts this figure will have expanded to
$1290 million, representing a compounded annual
growth rate of 25%.

Cost/performance considerations also point to Intel's
strengths. As a pioneer in VLSI technology, Intel has
been at the forefront of achieving greater circuit densities and performance on single pieces of silicon: witness
the 275,000 transistors housed on the 32-bit 80386, the
highest performance commercial microprocessor ever
built. As integration has increased, cost-per-bit has decreased steadily, marking a trend that remains consistent in the semiconductor industry. And one thing is

And although the WAN market will continue to grow
at a comfortable rate, the SAN and LAN pieces of the
pie will increase the most dramatically. Whereas SANs
represented only about 12.5% ($65 million) in 1985,
they could explode to 22.5% ($290 million) of the larger pie by 1989. This growth is paralleled by increases in

xiv

inter

AP-302

certain: microcommunications has a healthy appetite
for transistors, placing it squarely in the center of the
VLSI explosion.

That leadership extends beyond products. Along with
its own application software, Intel is promoting expansion through partnerships with many different independent software vendors (ISV s), ensuring that the necessary application programs will be in place to fuel the
gains provided by the silicon "engines" residing at the
interface level. And finally, the corporation's commitment to technical support training, service, and its
strong force of field applications engineers guarantees
that it will back up its position and serve the needs that
will continue to spring up as the microcommunications
evolution becomes a reality.

But it is in the final area-completeness of technology
and products-where Intel is perhaps the strongest. No
other microelectronic vendor can point to as wide an
array of products positioned across the various segments that comprise the microelectronic marketplace.
Whether it be leadership in the WAN marketplace as
the number one supplier of merchant telecommunications components, strength in SANs with world leadership in microcontrollers, or overall presence in the
LAN arena with complete solutions in components,
boards, software, and systems, Intel is a vital presence
in the growing microcommunications arena.

Together, all the market segment alluded to in this article comprise the world of microcommunications, a
world coming closer together every day as the web of
networking solutions expands-all thanks to the technological ties that bind, reaching out to span the globe
with silicon.

Local Area Networks

82586
IEEE 802.3 ETHERNET LAN COPROCESSOR
• Performs Complete CSMA/CD Medium
Access Control Functions
Independently of CPU
- High-Level Command Interface

• Supports Minimum Component
Systems
- Shared Bus Configuration
. -Interface to 80186 and 80188
Microprocessors Without Glue

• Supports Established and Emerging
LAN Standards
-IEEE 802.3/Ethernet (10BASE5)
-IEEE 802.3/Cheapernet (10BASE2)
-IEEE 802.3/StarLAN (1BASE5)
-Proposed 10BASE-T
- Proposed 10BASE-F
- Proprietary CSMA/CD Networks up
to 10 Mb/s
•

•

Supports High-Performance Systems
- Bus Master, with On-Chip DMA
- 5-MB/s Bus Bandwidth
- Compatible with Dual-Port Memory
- Back-to-Back Frame Reception at
10 Nlb/s

• Network Management
- CRC Error Tally
- Alignment Error Tally
- Location of Cable Faults

On-Chip Memory Management
- Automatic Buffer Chaining
- Buffer Reclaim After Receipt of Bad
Frames
- Save Bad Frames, Optionally

• Self-Test Diagnostics
-Internal Loopback
- External Loopback
-Internal Register Dump
- Backoff Timer Check

Interfaces to 8-Bit and 16-Bit
Microprocessors

• 48-Pin DIP and 68-Pin PLCC
(see "Inlel Packaging" Documenl, Order Number: 231369-001)

II'ISTEMINT1!RFACE

SYSTEM CLOCK
AND CDNTROL SIGNALS

BUS
INTERFACE
UNIT

SERIAL INTERFACE

~
RXD

IIlIe
TXD

231246-1

Figure 1.82586 Functional Block Diagram

·IBM is a trademark of International Business Machines Corporation.

1-1

September 1990
Order Number: 231246-007

intJ

82586

A20

.19/58
A18
Al1
A18
AD1,
ADI'
AD13
AD12

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(
l
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[
[
[
[
[

P
P
P
p!ll
P
3. P AEADY

AD11 [ 10

,,010 ~ 11
Vss
AD.
ADa
AD7
ADO
AD.
AD4
AD3
AD2
AD1
ADO

RiC
Yss

[
[
[
[
[
[
,

Vee

47 J .21
4. ~ A22 fRO)
••
A23 (WiI)
..
SHE
.3
HDLD
.2
HLDA
"
(DTI];)
••
Sa (iiEIl)

2
3
•
•
•
7
•
9

(ALE)

3. piNT

12
13
,.
15
16
17
18
11
2.
21
22
23
24

37
AROY/SRDY
36
Vee
3. J CA
34 J RESET
33
MNlliX
32 ~ CLK
31
CAS
3.
CllT
2.
C'B
21
RTS
27
TID
2. ~ fif
25
RID

2
p'

P
P
P

e
P

231246-2

NOTE:
The symbols in parentheses correspond to minimum mode.

Plastic Leaded Chip Carrier
Top
~ ~ ~ ~ ~ § I~ >~ Jl ~ ~ l~

Bottom

3 I~ I~ 18 15

ADS

AD6

elK

AD7

~N/i.iX

ADS

RESET

AD9

v,,
Vss
v,,

N82586

BBl PLCC
(TOP VIEW)

V"
AD10

Vee

Vee
Vee

;:;

'"'" '"

.'It

III

co
N

'"'"

:>l ;;; .,
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.,.,

ARDY/SRDY

INT

READY(AlE)

AD11

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A012

Si(DT/R)

AD13

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u
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oc(

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on

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231246-41

Figure 2. 82586 Pinout Diagrams

1-2

82586

The 82586 provides two independent 16-byte FIFOs, one for receiving and one for transmitting. The
threshold for block transfer to/from memory is programmable, enabling the user to optimize bus overhead for a given worst case bus latency.

The 82586 is an intelligent, high-performance Local
Area Network coprocessor, implementing the
CSMA/CD .access method (Carrier Sense Multiple
Access with Collision Detection). It performs all timecritical functions independently of the host processor, which maximizes performance and network
efficiency.

The 82586 provides a rich set of diagnostic and network management functions including: internal and
external loopbacks, exception condition tallies,
channel activity indicators, optional capture of all
frames regardless of destination address, optional
capture of errored or collided frames, and time domain reflectometry for locating faults in the cable.

The 82586 performs the full set of IEEE 802.3
CSMAlCD Medium Access Control and channel interface functions including: framing, preamble generation and stripping, source address generation,
destination address checking, CRC generation and
checking, short frame detection. Any data rate up to
10 Mb/s can be used.

The 82586 can be used in either baseband or broadband networks. It can be configured for maximum
network efficiency (minimum contention overhead)
for any length network operating at any data rate up
to 10 Mb/s. The controller supports address field
lengths of 1, 2, 3, 4, 5, or 6 bytes. It can be configured for either the IEEE 802.3/Ethernet or HDLC
method of frame delineation. Both 16-bit and 32-bit
CRCs are supported.

The 82586 features a powerful host system interface. It automatically manages memory structures
with command chaining and bidirectional data chaining. An on-chip DMA controller manages four channels transparently to the user. Buffers containing errored or collided frames can be automatically recovered. The 82586 can be configured for 8-bit or 16-bit
data path, with maximum burst transfer rate of 2 or
4 MB/s respectively. Memory address space is
16 megabytes maximum.

The 82586 is fabricated in Intel's reliable HMOS II
5-V technology and is available in a 48-pin DIP or
68-pin PLCC package.

Table 1. 82586 Pin Description
Symbol

48 Pin DIP
Pin No.

68 Pin PLCC
Pin No.

Type
Level

Vcc,Vcc

48,36

8,9,10, 11,
61,62

System Power:

Vss, Vss

12,24

26,27,41,
42,43,44

System Ground.

RESET

I
TTL

RESET is an active HIGH internally synchronized signal,
causing the 82586 to terminate present activity
immediately. The signal must be HIGH for at least four
clock cycles. The 82586 will execute RESET within ten
system clock cycles starting from RESET HIGH. When
RESET returns LOW, the 82586 waits for the first CA to
begin the initialization sequence.

TxD

0
TTL

Transmitted Serial Data output sig~al. This signal is HIGH
when not transmitting.

TxC

Transmit Data Clock. This signal provides timing
information to the internal serial logic, depending upon the
mode of data transfer. For NRZ mode of operation, data is
transferred to the TxD pin on the HIGH to LOW clock
transition.

RxD

RxC

•

I
TTL
I

•

Name and Function

+ 5V Power Supply.

Received Data Input Signal.
Received Data Clock. This signal provides timing
information to the internal shifting logic depending upon the
mode of data transfer. For NRZ data, the state of the RxD
pin is sampled on the HIGH to LOW clock transition.

'See D.C. CharacteristiCS.

1-3

intJ

82586

Table 1.82586 Pin Description (Continued)
Symbol

48 Pin DIP 68 Pin PLCC
Pin No.
Pin No.

Type
Level

Name and Functio!1

RTS

0
TTL

Request To Send signal. When LOW, notifies an external
interface that the 82586 has data to transmit. It is forced
HIGH after a Reset and while the Transmit Serial Unit is
not sending data.

CTS

I
TTL

Active LOW Clear To Send input enables the 82586
transmitter to actually send data. It is normally used as an
interface handshake to RTS. This signal going inactive
stops transmission. It is internally synchronized. If CTS
goes inactive, meeting the setup time to TxC negative
edge, transmission is stopped and RTS goes inactive
within, at most, two TxC cycles.

CRS

I
TTL

Active LOW Carrier Sense input used to notify the 82586
that there is traffic on the serial link. It is used only if the
82586 is configured for external Carrier Sense. When so
configured, external circuitry is required for detecting serial
link traffic. It is internally synchronized. To be accepted,
the signal must stay active for at least two serial clock
cycles.

CDT

I
TTL

Active LOW Collision Detect input is used to notify the
82586 that a collision has occurred. It is used only if the
82586 is configured for external Collision Detect. External
circuitry is required for detecting the collision. It is internally
synchronized. To be accepted, the signal must stay active
for at least two.serial clock cycles. During transmission, the
82586 is able to recognize a collision one bit time after
preamble transmission has begun.

INT

0
TTL

Active HIGH Interrupt request signal.

CLK

I
MOS

The system clock input from the 80186 or another
symmetrical clock generator.

MN/MX

I
TTL

When HIGH, MN/MX selects RD, WR, ALE DEN, DT IR
(Minimum Mode). When LOW, MN/MX selects A22, A23,
READY, SO, S1 (Maximum Mode). Note: This pin should be
static during 82586 operation.

ADO-AD15

6-11,
13-22

29-33,3640,45,48,
49,50,53,
54

1/0
TTL

These lines form the time multiplexed memory address (t1)
and data (t2, t3, tW, t4) bus. When operating with an 8-bit
bus, the high byte will output the address only during T1.
ADO-AD15 are floated after a RESET or when the bus is
not acquired.

A16-A18
A20-A23

1,3-5
45-47

55-57,59,
63-65

0
TTL

These lines constitute 7 out of 8 most significant address
bits for memory operation. They switch during t1 and stay
valid during the entire memory cycle. The lines are floated
after RESET or when the.bus is not acquired. Address
lines A22 and A23 are not available for use in minimum
mode.

0
TTL

During t1 it forms line 19 of the memory address. During t2
through t4 it is used as a status indicating that this is a
Master peripheral cycle, and is HIGH. Its timing is identical
to that of ADO-AD15 during write operation.

A19/S6

1-4

82586

Table 1. 82586 Pin Description (Continued)
Symbol

48 Pin DIP 68 Pin PLCC
Pin No.
Pin No.

Type
Level

Name and Function

HOLD

0
TTL

HOLD is an active HIGH signal used by the 82586 to
request local bus mastership at the end of the current
CPU bus transfer cycle, or at the end of the current DMA
burst transfer cycle. In normal operation, HOLD goes
inactive before HLDA. The 82586 can be forced off the
bus by HLDA going inactive. In this case, HOLD goes
inactive within four clock cycles in word mode and eight
clock cycles in byte mode.

HLDA

I
TTL

HLDA is an active HIGH Hold Acknowledge signal
indicating that the CPU has received the HOLD request
and that bus control has been relinquished to the 82586. It
is internally synchronized. After HOLD is detected as
LOW, the processor drives HLDA LOW. Note,
CONNECTING Vee TO HLDA IS NOT ALLOWED
because it will cause a deadlock. Users wanting to give
permanent bus access to the 82586 should connect
HLDA with HOLD.

I
TTL

The CA pin is a Channel Attention input used by the CPU
to initiate the 82586 execution of memory resident
Command Blocks. The CA signal is synchronized
internally. The signal must be HIGH for at least one
!iystem clock period. It is latched internally on HIGH to
LOW edge and then detected by the 82586.

BHE

0
TTL

The Bus High Enable signal (BHE) is used to enable data
onto the most significant half of the data bus. Its timing is
identical to that of A 16-A23. With a 16-bit bus it is LOW
and with an 8-bit bus it is HIGH. Note: after RESET, the
82586 is configured to 8-bit bus.

READY

I
TTL

This active HIGH signal is the acknowledgement from the
addressed memory that the transfer cycle can be
completed. While LOW, it causes wait states to be
inserted. This signal must be externally synchronized with
the system clock. The Ready signal internal to the 82586
is a logical OR between READY and SRDY / ARDY.

ARDY/SRDY

I
TTL

This active HIGH signal performs the same function as
READY. If it is programmed at configure time to SRDY, it
is identical to READY. If it is programmed to ARDY, the
positive edge of the Ready signal is internally
synchronized. Note, the negative edge must still meet
setup and hold time specifications, when in ARDY mode.
The ARDY signal must be active for at least one system
clock HIGH period for proper strobing. The Ready signal
internal to the 82586 is a logical OR between READY (in
Maximum Mode only) and SRDY / ARDY. Note that
following RESET, this pin assumes ARDY mode.

1-5

82586

Table 1.82586 Pin Description (Continued)
48 Pin·DIP
Pin No.

68 Pin PLCC
Pin No.

Type
Level

40,41

4,3

0
TTL

Maximum mode only. These status pins define the type of
DMA transfer during the current memory cycle. T.hey are
encoded as follows:
S1
SO
0
0
Not Used
1
Read Memory
0
1
0
Write Memory
Passive
1
1
Status is active from the middle of t4 to the end of t2. They
return to the passive state during t3 or during tW when
READY or ARDY is HIGH. These signals can be used by
the 8288 Bus Controller to generate all memory control and
timing signals.' Any change from the passive state, signals
the 8288 to start the next t1 to t4 bus cycle. These pins are
pulled HIGH and floated after a system RESET and when
the bus is not acquired.

0
TTL

Used in minimum mode only. The read strobe indicates that
the 82586 is performing a memory read cycle. RD is active
LOW during t2, t3 and tW of any read cycle. This signal is
pulled HIGH and floated after a RESET and when the bus is
not acquired.

0
TTL

Used in minimum mode only. The write strobe indicates that
the 82586 is performing a write memory cycle. WR is active
LOW during t2, t3 and tW of any write cycle. It is pulled
HIGH and floats after RESET and when the bus is not
acquired.

ALE

0
TTL

Used in minimum mode only. Address Latch Enable is
provided by the 82586 to latch the address into the
8282/8283 address latch. It is a HIGH pulse, during t1
('clock low') of any bus cycle. Note that ALE is never
floated.

Symbol
SO, S1

Name and Function

DEN

0
TTL

Used in minimum mode only. Data ENable is provided as
output enable for the 8286/8287 transceivers in a stand·
alone (no 8288) system. DEN is active LOW during each
memory access. For a read cycle, it is active from the
middle of t2 until the beginning of t4. For a write cycle, it is
active from the beginning of t2 until the middle of t4. It is
pulled HIGH and floats after a system RESET or when the
bus is not acquired.

DTIR

0
TTL

Used in minimum mode only. DT IR is used in non·8288
systems using an 8286/8287 data bus transceiver. Itcontrols the direction of data flow through the Transceiver.
Logically, DT IA is equivalent to S1. It becomes valid in the
t4 preceding a bus cycle and remains valid until the final t4
of the cycle. This signal is pulled HIGH and floated after a
RESET or when the bus is not acquired.

NOTE:
*8288 does not support 10 MHz operation.

1·6

inter
82586/HOST CPU

82586

Command List, and Receive Frame Area (RFA) (see
Figure 4).

I~TERACTION

Communication between the 82586 and the host is
carried out via shared memory. The 82586's on-chip
DMA capability allows autonomous transfer of data
blocks (buffers, frames) and relieves the CPU of
byte transfer overhead. The 82586 is optimized to
interface the iAPX 186, but due to the small number
of hardware signals between the 82586 and the
CPU, the 82586 can operate easily with other processors. The 82586/host interaction is explained
separately in terms of the logical interface and the
hardware bus interface.

The Initialization Root is at a predetermined location
in the memory space, (OFFFFF6H), known to both
the host CPU and the 82586. The root is accessed
at initialization and points to the System Control
Block.
The System Control Block (SCB) functions as a bidirectional mail drop between the host CPU, CU and
RU. It is the central element through which the CPU
and the 82586 exchange control and status information. The SCB consists of two parts, the first of
which entails instructions from the CPU to the
82586. these include: control of the CU and RU
(START, ABORT, SUSPEND, RESUME), a pointer
to the list of commands for the CU, a pointer to the
receive frame area, and a set of Interrupt acknowledge bits. The second entails status information
keyed by the 82586 to the CPU, including: state of
the CU and RU (e.g. IDLE, ACTIVE READY, SUSPENDED, NO RECEIVE RESOURCES), interrupts
bits (command completed, frame received, CU not
ready, RU not ready), and statistics (see Figure 4).

The 82586 consists of two independent units: Command Unit (CU) and Receive Unit (RU). The CU executes commands from shared memory. The RU
handles all activities related to frame reception. The
CU and RU enable the 82586 to engage in the two
types of activities simultaneously: the CU may be
fetching and executing commands out of memory,
and the RU may be storing received frames in memory. CPU intervention is only required after the CU
executes a sequence of commands or the RU stores
a sequence of frames.
The only hardware Signals that connect the CPU and
the 82586 are INTERRUPT and CHANNEL ATTENTION (see Figure 3). Interrupt is used by the 82586
to draw the CPU's attention to a change in the contents of the SCB. Channel Attention is used by the
CPU to draw the 82586's attention.

The Command List serves as a program for the CU.
Individual commands are placed in memory units
called a Command Block, or CB. CB's contain command specific parameters and command specific
statuses. Specifically, these high level commands
are called Action Commands (e.g. Transmit, Configure).

82586 SYSTEM MEMORY
STRUCTURE

A specific command, Transmit, causes transmission
of a frame by the 82586. The Transmit command
block includes Destination Address, Length Field,
and a pointer to a list of linked buffers that holds the
frame to be constructed from several buffers scattered in memory. The 90mmand Unit performs with-

The Shared Memory structure consists of four parts:
Initialization Root, System Control Block (SCB),

CHANNEL ATTENTION
INTERRUPT

SHARED MEMORY

Ir.. ITIALIZATION
ROOT

231246-3

Figure 3. 82586/Host CPU Interaction

1-7

inter

82586

INITIALIZATION ROOT

SYSTEM CONTROL

BLOCK (SCB)

STATUS

-30M~ LlST~L)

COMMAND
COMMAND LIST
POINTER

RECEIVE FRAME
POINTER

STATISTICS

-,
________~,rID-E7.;~~,=~~R'1 I
•

(FD)

.(N)

231246-4

Figure 4. 82586 Shared Memory Structure

out the CPU intervention, the DMA of each buffer
and the prefetching of references to new buffers in
parallel. The CPU is notified only after successful
transmission or retransmission.

Receive buffer chaining (Le. storing incoming frames
in a linked ~list of buffers) improves memory utilization significantly. Without buffer chaining, the user
must allocate consecutive blocks of the maximum
frame size (1518 bytes in Ethernet) for each frame.
Taking into account that a typical frame size may be
about 100 bytes, this practice is very inefficient. With
buffer chaining, the user can allocate small buffers
and the 82586 uses only as many as needed.

The Receive Frame Area is a list of Free Frame Descriptors (Descriptors not yet used) and a list of buffers prepared by the user. It is conceptually distinct
from the Command List. Frames arrive without being
solicited by the 82586. The 82586 must be prepared
to receive them even if it is engaged in other activities and to store them in the Free Frame Area. The
Receive Unit fills the buffers upon frame reception
and reformats the Free Buffer List into received
frame structures. The frame structure is virtually
identical to the format of the frame to be transmitted.
The first frame descriptor is referenced by SCB. A
Frame Descriptor and the associated Buffer Descriptor wasted upon receiving a Bad Frame (CRC
or Alignment errored, Receive DMA overrun errored,
or Collision fragmented frame) are automatically reclaimed and returned to the Free Buffer List, unless
the chip is configured to Save Bad Frames.

In the past, the drawback of buffer chaining was the
CPU processing overhead and the time involved in
the buffer switching (especially at 10 Mb/s). The
82586 overcomes this drawback by performing buffer management on its own for both transmission and
reception (completely transparent to the user).
The 82586 has a 22-bit memory address range in
minimum mode and 24-bit memory address range in
maximum mode. All memory structures, the System
Control Block,· Command List, Receive Descriptor
List, and all buffer descriptors must reside within one
64K-byte memory segment. The Data Buffers can
be located anywhere in the memory space.

1-8

infef

82586

TRANSMITTING

~RAMES

TRANSMIT (80)

The 82586 executes high level action commands
from the Command List in external memory. Action
commands are fetched and executed in parallel with
the host CPU's operation, thereby significantly improving system performance. The general action
commands format is shown in Figure 5.

CONTROL
FIELDS

I
I

ACTUAL COUNT
Lr'NEXTBUFFEA DESCRIPTOR
LINK FIELD

DBADDAESS

(24 BITS)

f--

DATA
BUFFER (DB)

COMMAND STATUS
COMMAND

LINK FIELD
(POINTER TO NEXT COMMAND)

231246-6
NEXT
COMMAND

Figure 6. Data Buffer Descriptor
and Data Buffer Structure

MRAMETER FIELD
(CDMMANO·SPECIAC

PARAMETERS)

buffers pointed to by the Transmit command, and
computes and appends the CRC at the end of the
frame. See Figure 7.

231246-5

Figure 5_ Action Command Format

The 82586 can be configured to generate either the
Ethernet or HDLC start and end frame delimiters. In
the Ethernet mode, the start frame delimiter is
10101011 and the end frame delimiter indicated by
the lack of a signal after transmitting the last bit of
the frame check sequence field. When in the HDLC
mode, the 82586 will generate the 01111110 'flag'
for the start and end frame delimiters and perform
the standard 'bit stuffing/stripping'. In addition, the
82586 will optionally pad frames that are shorter
than the specified minimum frame length by appending the appropriate number of flags to the end of the
frame.

Message transmission is accomplished by using the
Transmit command. A single -Transmit command
contains, as part of the command-specific parameters, the destination address and length field for the
transmitted frame along with a pointer to a buffer
area in memory containing the data portion of the
frame. (See Figure 15.) The data field is contained in
a memory data structure consisting of a Buffer Descriptor (BD) and Data Buffer (or a linked list of buffer descriptors and buffers) as shown in Figure 6. The
BD contains a Link Field which points to the next BD
on the list and a 24-bit address pointing to the Data
Buffer itself. The length of the Data Buffer is specified by the Actual Count field of the BD.

In the event of a collision (or collisions), the 82586
manages the entire jam, random wait, and retry process, reinitializing DMA pointers without CPU intervention. Multiple frames can be sent by linking the
appropriate number of Transmit commands together. This is particularly useful when transmitting a
message that is larger than the maximum frame size
(1518 bytes for Ethernet).

Using the BD's and Data Buffers, multiple Data Buffers can be 'chained' together. Thus, a frame with a
long Data Field can be transmitted using multiple
(shorter) Data buffers chained together. This chaining technique allows the system designer to develop
efficient buffer management policies.
The 82586 automatically generates the preamble
(alternating 1's and O's) and start frame delimiter,
fetches the destination address and length field from
the Transmit command, inserts its unique address
as the source address, fetches the data field from

PREAMBLE

START
FRAME
DELIMITER

DEST
ADDR

RECEIVING FRAMES
In order to minimize CPU overhead, the 82586 is
designed to receive frames without CPU supervision. The host CPU first sets aside an adequate

LENGTH
FIELD

SOURCE
AD DR

Figure 7. Frame Format

1-9

DATA
FIELD

FRAME
END
CHECK
FRAME
SEQUENCE DELIMITER

82586

SYSTEM
CONTROL
BLOCK

of-

r -

- -

-- -

DESC:I~~~(RFD) ~ ~

FREE BUFFER LIST(FBL)
RECEIVE
BUFFER
~DESCRIPTOR (RBD)

RBD

DATA
BUFFER (DB)

0-.

••

RBD

231246-7

Figure 8. Receive Frame Area Diagram
amount of receive buffer space and then enables
the 82586's Receive Unit. Once enabled, the RU
'watches' for any of its frames which it automatically
stores in the Receive Frame Area (RFA). The RFA
consists of a Receive Descriptor List (RDl) and a list
of free buffers called the Free Buffer List (FBl) as
shown in Figure 8. The individual Receive Frame
Descriptors that make up the RDl are used by the
82586 to store the destination and source address,
length field and status of each frame that is received. (Figure 9.)

RECEIVE FRAME STATUS

LINK FIELD

BUFFER DESCRIPTOR
LINK FIELD

or--

NEXT RECEIVE
FRAME DESCRIPTOR

0 -.

BUFFER DESCRIPTOR

DESTINATION ADDRESS

The 82586, once enabled, checks each passing
frame for an address match. The 82586 will recognize its own unique address, one or more multicast
addresses or the broadcast address. If a match occurs, it stores the destination and source address
and length field in the next available RFD. It then
begins filling the next free Data Buffer on the FBl
(which is pointed to by the current RFD) with the
data portion of the incoming frame. As one DB is
filled, the 82586 automatically fetches the next DB
on the FBl until the entire frame is received. This
buffer chaining technique is particularly memory efficient because it allows the system designer to set
aside buffers that fit a frame size that may be much
shorter than the maximum allowable frame.

SOURCE ADDRESS

LENGTH FIELD

231246-8

Figure 9. Receive Frame Descriptor
Once the entire frame is received without error, the
82586 performs the following housekeeping tasks:
• Updates the Actual Count field of the last Buffer
Descriptor used to hold the frame just received
with the number of bytes stored in its associated
Data' Buffer.
1-10

intJ

82586

• Fetches the address of the next free Receive
Frame Descriptor.

NETWORK PLANNING AND
MAINTENANCE

• Writes the address of the next free Buffer Descriptor into the next free Receive Frame Descriptor.

To perform proper planning, operation, and maintenance of a communication network, the network
management entity must accumulate information on
network behavior. The 82586 provides a rich set of
network-wide diagnostics that can serve as the basis for a network management entity.

• Posts a 'Frame Received' interrupt status bit in
the SCB.
• Interrupts the CPU.
In the event of a frame error, such as a CRC error,
the 82586 automatically reinitializes its DMA pointers and reclaims any data buffers containing the bad
frame. As long as Receive Frame Descriptors and
data buffers are available, the 82586 will continue to
receive frames without further CPU help.

Network Activity information is provided in the status
of each frame transmitted. The activity indicators
are:
• Number of collisions: number of collisions the
82586 experienced in attempting to transmit this
frame.
• Deferred transmission: indicates if the 82586 had
to· defer to traffic on the link during the first transmission attempt.

82586 NETWORK MANAGEMENT AND
.DIAGNOSTIC FUNCTIONS

Statistics registers are updated after each received
frame that passes the address filtering, and is longer
than the Minimum Frame Length configuration parameter.

The behavior of data communication networks is
typically very complex due to their distributed and
asynchronous nature. It is particularly difficult to pinpoint a failure when it occurs. The 82586 was designed in anticipation of these problems and
includes a set of features for improving reliability and
testability.

• CRC errors: number of frames that experienced a
CRC error and were properly aligned.
• Alignment errors: number of frames that experienced a CRC error and were misaligned ..

The 82586 reports on the following events after
each frame transmitted:

• No-resources: number of correct frames lost due
to lack of memory resources.

• Transmission successful.
.• Transmission unsuccessful; lost Carrier Sense.

• Overrun errors: number of frame sequences lost
due to DMA overrun.

• Transmission unsuccessful; lost Clear-to-Send.

The 82586 can be configured to Promiscuous Mode.
In this mode it captures all frames transmitted on the
Network without checking the Destination Address.
This is useful in implementing a monitoring station to
capture all frames for analysis.

• Transmission unsuccessful; DMA underrun because the system bus did not keep up with the
transmission.
• Transmission unsuccessful; number of collisions
exceeded the maximum allowed.

The 82586 is capable of determining if there is a
short or open circuit anywhere in the Network using
the built in Time Domain Reflectometer (TDR) mechanism.

The 82586 checks each incoming frame and reports
on the following errors, (if configured to 'Save Bad
.
Frame'):
• CRC error: incorrect CRC in a well aligned frame.
• Alignment error: incorrect CRC in a misaligned
frame.

STATION DIAGNOSTICS

• Frame too short: the frame is shorter than the
configured value for minimum frame length.

The chip can be configured to External Loopback.
The transmitter to receiver interconnection can be
placed anywhere between the 82586 and the link to
locate faults, for example: the 82586 output pins, the
Serial Interface Unit, the Transceiver cable, or in the
Transceiver.

• Overrun: the frame was not completely placed in
memory because the system bus did not keep up
with incoming data.
• Out of buffers: no memory resources to store the
frame, so part of the frame was discarded.

1-11

intJ

82586

The 82586 has a mechanism recognizing the transceiver 'heart beat' Signal for verifying the correct operation of the Transceiver's collision detection circuitry.

The CU can be modeled as a logical machine that
takes, at any given time, one of the following states:
• IDLE-CU is not executing' a command and is not
associated with a CB on the list. This is the initial
state.
• SUSPENDED--CU is not executing a command
but (different from IDLE) is associated with a CB
on the list.
.

82586 SELF TESTING
The 82586 can be configured to Internal Loopback.
It disconnects itself from the Serial Interface Unit,
and any frame transmitted is received immediately.
The 82586 connects the Transmit Data to the Receive Data signal and the Transmit Clock to the Receive Clock.

• ACTIVE-CU is currently executing an Action
Command, and points to its CB.
The CPU may affect the CU operation in two ways:
issuing a CU control Command or setting bits in the
COMMAND word of the Action Command.

The Dump Command causes the chip to write over
100 bytes of its internal registers to memory.

THE RECEIVE UNIT (RU)

The Diagnose command checks the exponential
Backoff random number generator internal to the
.
82586.

The Receive Unit is the logical unit that receives
frames and stores them in memory.
The RU is modeled as a logical machine that takes,
at any given time, one of the following states:

CONTROLLING THE 82586

• IDLE-RU has no memory resources and is dis- '
carding incoming frames. This is the, initial RU
state. .

. The CPU controls operation of the 82586's Command Unit (CU) and Receive Unit (RU) of the 82586
via the System Control Block.

• NO-RESOURCE5-RU has no memory resources and is discarding incoming frames. This state
differs from the IDLE state in that RUaccumulates statistics on the number of frames it had to
discard.

THE COMMAND UNIT (CU)
The Command Unit is the logical unit that executes
Action Commands from a list of commands very
similar to a CPU' program. A Command Block (CS) is
associated with each Action Command.
.

15 ODD BYTE

STAT

CUS

RUS

.
.

EVEN BVTE

ACK
I

• SUSPENDED-RU has free memory resources'
to store incoming frames but discard them anyway.

CUC

R
E
S

RUC

CBLOFFSET

SCB
(STATUS)
SCB+2
(COMMAND)
SCB+4

RFAOFFSET

Sc:8+6

CRCERRS

SCB+8

ALNERRS

SCB+ 10

RSCERRS

SCB+ 12

OVRNERRS

SCB+ 14,
231246-9

Figure 10. System Control Block (SCB) Format
1-12

inter

82586

• READY-RU has free memory resources and
stores incoming frames.

COMMAND word: Specifies the action to be performed as a result of the CA. This word is set by the
CPU and cleared by the 82586. Defined bits are:

The CPU may affect RU operation in three ways:
issuing an RU Control Command, setting bits in
Frame Descriptor, FD, COMMAND word of the
frame currently being received, or setting El bit of
Buffer Descriptor, BD, of the buffer currently being
filled.

ACK-CX

(Bit 15)

ACK-FR

(Bit 14)

ACK-CNA (Bit 13)
ACK-RNR (Bit 12)

SYSTEM CONTROL BLOCK (SCB)
The System Control Block is the communication
mail-box between the 82586 and the host CPU. The
SCB format is shown in Figure 10.

CUC

(Bits 8-10)
0

The host CPU issues Control Commands to the
82586 via the SCB. These commands may appear
at any time during routine operation, as determined
by the host CPU. After the required Control Command is setup, the CPU sends a CA signal to the
82586.

SCB is also used by the 82586 to return status information to the host CPU. After inserting the required
status bits into SCB, the 82586 issues an Interrupt to
the CPU.

The format is as follows:
3

STATUS word: Indicates the status of the 82586.
This word is modified only by the 82586. Defined bits
are:
CX

(Bit 15)

FR
CNR

(Bit 14)
(Bit 13)

RNR

(Bit 12)

CUS

(Bits 8-10)

RUS

(Bits 4-6)

• A command in the CBl
having its 'I' (interrupt) bit
set has been executed.
• A frame has been received.
• The Command Unit left the
Active state.
• The Receive Unit left the
Ready state.
• (3 bits) this field contains
the status of the Command
Unit.
Valid values are:
0
-Idle
1
-Suspended
2
-Active
3-7 - Not Used
• (3 bits) this field contains
the status of the Receive
Unit. Valid values are:
0
-Idle
1
-Suspended
2
- No Resources
3
-Not Used
4
-Ready
5-7 -Not Used

RUC

5-7
(Bits 4-6)

0
1

2
3

4
RESET

1-13

5-7
(Bit 7)

• Acknowledges the
command executed event.
• Acknowledges the frame
received event.
• Acknowledes that the
Command Unit became not
ready.
• Acknowledges that the
Receive Unit became not
ready.
• (3 bits) this field contains
the command to the
Command Unit.
• NOP (doesn't affect current
state of the unit).
• Start execution of the first
command on the CBL. If a
command is in execution,
then complete it before
starting the new CBL. The
beginning of the CBl is in
CBlOFFSET.
• Resume the operation of
the command unit by
executing the next
command. This operation
assumes that the
command unit has been
previously suspended.
• Suspend execution of
commands on CBl after
current command is
complete.
• Abort execution of
commands immediately.
• Reserved, illegal for use.
• (3 bits) This field contains
the command to the
receive unit. Valid values
are:
• NCP (does not alter current
state of unit).
• Start reception of frames. If
a frame is being received,
then complete reception
before starting. The
beginning of the RFA is'
contained in the RFA
OFFSET.
• Resume frame receiving
(only when in suspended
state.)
• Suspend frame receiving. If
a frame is being received,
then complete its reception
before suspending.
• Abort receiver operation
immediately.
• Reserved, illegal for use.
• Reset chip (logically the
same as hardware
RESET).

inter

82586
Figure 5, each command contains the command
field, status and control fields, link to the next action
command in the CL, and any command-specific parameters. This command format is called the Command Block.

CBl-OFFSET:
Gives the 16-bit offset address of the first command
(Action Command) in the command list to be executed following CU-START. Thus, the 82586 reads this
word only if the CUC field contained a CU-START
Control Command.

The 82586 has a repertoire of 8 commands:
NOP
Setup Individual Address
Configure
Setup Multicast Address
Transmit
TOR
Diagnose
Dump

RFA-OFFSET:
Points to the first Receive Frame Descriptor in the
Receive Frame Area.
CRCERRS:
CRC Errors - contains the number of properly
aligned frames received with a CRC error.

NOP

AlNERRS:

This command results in no action by the 82586,
except as performed in normal command processing. It is present to aid in Command List manipulation.

Alignment Errors - contains the number of misaligned frames received with a CRC error.

NOP command includes the following fields:

RSCERRS:
Resource Errors - records the number of correct incoming frames discarded due to lack of memory
resources (buffer space or received frame descriptors).

STATUS word (written by 82586):

OVRNERRS:
Overrun Errors - counts the number of received
frame sequences lost because the memory bus was
not available in time to transfer them.

COMMAND word:
(Bit 15)
EL
S
(Bit 14)
(Bit 13)
I
CMD (Bits 0-2)

ACTION COMMANDS

liNK OFFSET: Address of next Command Block

C
B
OK

(Bit 15)
(Bit 14)
(Bit 13)

• Command Completed
• Busy Executing Command
• Error Free Completion

•
•
•
•

End of Command List
Suspend After Completion
Interrupt After Completion
NOP = 0

The 82586 executes a 'program' that is made up of
action commands in the Command List. As shown in

EVEN BYTE

15 ODD BYTE

(STATUS)

CMD

~~~~__~~~~~~~~~~~~~~~~~~~~~__~__~~(COMMAND)
LINK OFFSET
231246-10

Figure 11. The NOP Command Block

1-14

inter

82586

ognition of Destination Address during reception and
insertion of Source Address during transmission.

lA-SETUP
This command loads the 82586 with the Individual
Address. This address is used by the 82586 for rec-

The lA-SETUP command includes the following
fields:

ODD BYTE

EVEN BYTE

ZEROS

(STATUS)

CMD= 1

(COMMAND)

LINK OFFSET
I
I
I
I
INDIVIDUAL ADDRESS

2ND BYTE

- --

-- -

1ST BYTE

---

I
I
I

NTH BYTE

231246-11

Figure 12. The lA-SETUP Command Block
STATUS word (written by 82586).
C
B
OK
A

(Bit 15)
(Bit 14)
(Bit 13)
(Bit 12)

COMMAND word:
(Bit 15)
EL
(Bit 14)
S
(Bit 13)
I
CMD (Bits 0:-2)

•
•
•
•

The CONFIGURE command includes the following
fields:

Command Completed
Busy Executing Command
Error Free Completion
Command Aborted

STATUS word (written by 82586):
C
B
OK
A

End of Command List
Suspend After Completion
Interrupt After Completion
lA-SETUP = 1

(Bit 15)
(Bit 14)
(Bit 13)
(Bit 12)

•
•
•
•

Command Completed
Busy Executing Command
Error Free Completion
Command Aborted

COMMAND word:
EL
S
I
CMD

LINK OFFSET: Address of next Command Block
INDIVIDUAL ADDRESS: Individual Address parameter
The least significant bit of the Individual Address parameter must be zero for IEEE 802.3/Ethernet.
However, no enforcement of 0 is provided by the
82586. Thus, an Individual Address with least significant bit 1, is possible.

(Bit 15)
(Bit 14)
(Bit 13)
(Bits 0-2)

•
•
•
•

End of Command List
Suspend After Completion
Interrupt After Completion
Configure = 2

LINK OFFSET: Address of next Command Block
Byte 6-7:
BYTECNT (Bits 0-3) • Byte Count, Number of
bytes including this one,
holding the parameters to
be configured. A number
smaller than 4 is
interpreted as 4. A
number greater than 12 is
interpreted as 12.

CONFIGURE
The CONFIGURE command is used to update the
82586 operating parameters.

1-15

82586

EVEN BVTE

ODD BYTE
C

ZEROS

CMD"2

LINK OFFSET

FIFO LIM
EXT
lP
BCK

INT
lP
BCk

PREAM

lEN

Al
lOC

ADDRLEN

INTERFAAME SPACING

RETRYNUM
CDT
SRC

CDTF

SAY
BF

SRD~'

CRSF

BYTECNT

ACR

LIN PAlO

SLOT TIME (ll

PAD

ARCY

BOF
MET

SlTTM(HI
CRS
SRC

BT
STF

CRC
16

INCRCFc:~
INS CRS ~N
~ I

MIN

BC IIPRM
DIS

FRM LEN

231246-13

Figure 13. The CONFIGURE Command Block

• Value of FIFO
Threshold.
Eiyte8-9:

SRDY/ARDY (Bit 6)
0

SAV-BF

ADD-LEN
AL-LOC

• SRDYI ARDY pin
operates as ARDY
(internal
synchronization).
• SRDYI ARDY pin
operates as SRDY .
(external
synchronization) ..

PREAMLEN

(Bit7)
0

• Received bad
frames are not saved
in memory.
1
• Received bad
frames are saved in
memory.
(Bits 8-10) • Number of address
byes. NOTE: 7 is
interpreted as O..
(Bit 11)
0
• Address and Length
Fields separated
fr9m data and
associated with
Transmit Command
Block or Receive
I
Frame Descriptor.
For transmitted
Frame, Source
Address is inserted
by the 82586.

(Bits
12-13)

INT-LPBCK (Bit 14)
EXT-LPBCK (Bit 15)
-

Address and Length
Fields are part of the
Transmit/Receive data
buffers, including
Source Address (which
is not inserted by the
82586).
• Preamble Length
including Beginning of
Frame indicator:
00 - 2 bytes
01 - 4 bytes
10 - 8 bytes
11 -16 bytes
• .Internal Loopback
• External LClopback. .
NOTE: Bits 14 and 15
configured to 1, cause
Internal Loopback.
~

Byte 10-11:

LlN-PRIO
ACR
BOF-MET

1-16

(Bits 0-2) • Linear Priority
(Bits 4-6) • Accelerated Contention
Resolution (Exponential
Priority)
(Bit 7)
• ExpOnential Backoff
Method
o- IEEE 802.3/Ethernet
1 - Alternate Method .

82586

INTER
FRAME
SPACING

(Bits 8-15)

CDTF

• Number indicating
the Interframe
Spacing in TxC
period units.

CDT-SRC

0
1

Byte 12-13:
SLOTTIME (L)
SLT-TM (H)

(Bits 0-7)

RETRYNUM

(Bits
12-15)

(Bits 8-10)

• Slot Time Number,
Low Byte
• Slot Time Number,
High Bits
• Maximum Number of
Transmission Retries
on' Collisions

(Bit 0)
(Bit 1)
(Bit 2)

0
1
TONO-CRS (Bit 3)

NCRC-INS
CRC-16

BT-STF

PAD

•
•
•
•
•
•
•

•

(Bit 4)
(Bit 5)
0

•
•
•

•

(Bit 6)
0

•
•

•

(Bit 7)
0
1

•
•
•

CRSF

(Bits 8-9)

•

CRS-SRC

(Bit 11)

•

0
1

•
co

• Collision Detect
Filter in Bit Times
• Collision Detect
Source
• External
• Internal

• Minimum Number of
Bytes in a Frame'

CONFIGURATION DEFAULTS

Byte 14-15:
PRM
BC-DIS
MANCH/
NRZ

(Bits
12-14
(Bit 15)

The default values of the configuration parameters
are compatible with the IEEE 802.3/Ethernet Standards. RESET configures the 82586 according to
the defaults shown in Table 2.

Promiscuous Mode
Broadcast Disable
Manchester or NRZ
Encoding/Decoding
NRZ
Manchester
Transmit on No
Carrier Sense
Cease Transmission
if CRS Goes Inactive
During Frame
Transmission
Continue
Transmission Even if
no Carrier Sense
No CRC Insertion
CRCType:
32 bit Autodin II CRC
Polynomial
16 bit CCITT CRG
Polynomial
Bitstuffing:
End of Carrier Mode
(Ethernet)
HDLC like Bitstuffing
Mode
Padding
No Padding
Perform Padding by
Transmitting Flags
for Remainder of
Slot Time
Carrier Sense Filter
in Bit Times
Carrier Sense
Source
External
Internal

Table 2. 82586 Default Values
Preamble Length (Bytes)
Address Length (Bytes)
Broadcast Disable
CRC-16/CRC-32
No CRC Insertion
Bitstuffing/EOC
Padding
Min-Frame-Length (Bytes)
Interframe Spacing (Bits)
Slot Time (Bits)
Number of Retries
Linear Priority
Accelerated Contention Resolution
Exponential Backoff Method
Manchester/NRZ
Internal CRS
CRSFilter
Internal COT
CDT Filter
Transmit On No CRS
FIFO THRESHOLD
SRDY/ARDY
Save Bad Frame
Address/Length Location
INT Loopback
EXT Loopback
Promiscuous Mode

1-17

8
6
0
0
0
0
0
64
96
512
15
0
0
0
0
0
0
0
0
0
8
0
0
0

0
0
0

inter
15

82586

EVEN BYTE

ODD BYTE

(STATUS)

CMD=3

LINK OFFSET

(COMMAND)

MC-CNT

MCLIST
1ST BYTE
I
MC~D

NTH BYTE
ADDITIONAL MC-ID'S

231246-14

Figure 14_ The MC-SETUP Command Block

Me-SETUP
This command sets up the 82586 with a set of Multicast Addresses. Subsequently, incoming frames
with Destination Addresses from this set are accepted.
The MC-SETUP command includes the following
fields:
STATUS word (written by 82586):
C
B

(Bit 15)
(Bit 14)

OK
A

(Bit 13)
(Bit 12)

• Command Completed
• Busy Executing
Command
• Error Free Completion
• Command Aborted

Issuing a MC-SETUP command with MC-CNT = 0
disables reception of any incoming frame with a Multicast Address.
MC-LlST: A list of Multicast Addresses to be accepted by the 82586. Note that the most significant byte
of an address is followed immediately by the least
significant byte of the next address. Note also that
the least significant bit of each Multicast Address in
the set must be a one.
The Transmit-Byte-Machine maintains a 64-bit
HASH table used for checking Multicast Addresses
during reception .
An incoming frame is accepted if it has a Destination
Address whose least significant bit is a one, and after hashing points to a bit in the HASH table whose
value is one. Thehash function is selecting'bits 2 to
7 of the CRC register. RESET causes the HASH table to become all zeros.

COMMAND word:
EL
S

(Bit 15)
(Bit 14)

(Bit 13)

CMD

(Bits 0-2)

• End of Command List
• Suspend After
Completion
• Interrupt After
Completion
• MC-SETUP = 3

After the Transmit-Byte-Machine reads a MC-SETUP command from TX-FIFO, it clears the HASH table and reads the bytes in groups whose length is
determined by the ADDRESS length. Each group is
hashed using CRC logic and the bit in the HASH
table to which bits 2-7 of the CRC register point is
set to one. A group that is not complete has no effect on the HASH table. Transmit-Byte-Machine notifies CU after completion.

LINK OFFSET: Address of next Command Block
MC-CNT: A 14-bit field indicating the number of
bytes in the MC-LlST field. MC-CNT is truncated to
the nearest multiple of Address Length (in bytes).

1-18

82586

ODD BYTE

EVEN BYTE

LINK OFFSET

~----------~--------------------------~

NEXT BD OFFSET

~------------------.-----------------.-~
2ND BYTE

1ST BYTE

I
DESTINATION ADDRESS
~

8
A

__~NT~H~B~Y~T~E____________________L -____________________________-1C

L-____________________________________________________
~E
LENGTH FIELD
231246-15

Figure 15. The Transmit Command Block

TRANSMIT

(Bit 6)

(Bit S)

MAXCOll

(Bits 3-0)

The TRANSMIT command. causes transmission
(and if necessary retransmission) of a frame.
TRANSMIT CB includes the following fields:
STATUS word (written by 82586):
C
B

(Bit 1S)
(Bit 14)

OK
A
S10

(Bit 13)
(Bit 12)
(Bit 10)

(Bit 9)

(Bit 8)

(Bit 7)

• Command Completed
• Busy Executing
Command
• Error Free Completion
• Command Aborted
• No Carrier Sense signal
during transmission
(between beginning of
Destination Address and
end of Frame Check
Sequence).
• Transmission
unsuccessful (stopped)
due to loss of Clear-toSend signal.
• Transmission
unsuccessful (stopped)
due to DMA underrun,
(Le. data not supplied
from the sytem for
transmission).
• Transmission had to
Defer to traffic on the link.

• Heart Beat, indicates that
during Interframe
Spacing period after the
previous transmission, a
pulse was detected on
the Collision Detect pin.
• Transmission attempt
stopped due to number of
collisions exceeding the
maximum number c~
retries.
• Number of Collisions
experienced by this
frame. SS = 1 and MAXCOll = 0 indicates that
there were 16 collisions.

COMMAND word:
El
S

(Bit 15)
(Bit 14)

(Bit 13)

CMD

(Bits 0-2)

• End of Command List
• Suspend After
Completion
• Interrupt After
Completion
• TRANSMIT = 4

LINK OFFSET: Address of next Command Block
TBD OFFSET: Address of list of buffers holding the
information field. TBD-OFFSET = OFFFFH indicates that there is no Information field.
DESTINATION ADDRESS: Destination Address of
the frame.
LENGTH FIELD: length field of the frame.
1-19

inter

82586
er measures the time' elapsed from transmission
start until 'echo' is obtained. 'Echo' is indicated by
Collision Detect going active or Carrier Sense signal
drop.

STATUS word:
EOF

(Bits 0-13)
ACTCOUNT

• Indicates that this is the
Buffer Descriptor of the
last buffer of this frame's
Information Field.
• Actual' number of data
bytes in buffer (can be
even or odd).

TDR command includes the following fields:
STATUS word (written by 82586):
C
B
OK

NEXT BD OFFSET: points to next Buffer Descriptor
in list. If EOF is set, this field is meaningless.
BUFFER ADDRESS: 24-bit absolute address of
buffer.

(Bit 15)
(Bit 14)
(Bit 13)

• Command Completed
• Busy Executing Command
• Error Free Completion

COMMAND word:
EL
S
I
CMD

TIME DOMAIN REFLECTOMETER TDR

(Bit 15)
(Bit 14)
(Bit 13)
(Bits 0-2)

• End of Command List
• Suspend After Completion
• Interrupt After Completion
.TDR = 5

This command performs a Time Domain Reflectometer test on the serial link. By performing the command, the user is able to identify shorts or opens
and their location. Along with transmission of 'All
Ones,' the 82586 triggers an internal timer. The tim-

EVEN BYTE
eOF

ACT COUNT

r-~~~--~---L---L

__~__~__L-~~~~~__-L__~__~__L-~ (SnTUS)
NEXT BD OFFSET

~------------------

____________________________________

BUFFER ADDRESS

231246-16

Figure 16. The Transmit Buffer D.scriptlon

ODD BYTE

EVEN BYTE

~---l~-+---Ir~~'7"">""""'7""7""""'J""7""7"'"......,.~...-r"T"':l""7"'T"7""""'T'7-r-......,....---r--.,..---I (STATUS)
EL
S
CMD=5
2
I-~'--~__""""'-L...L...I.""""L..L..L-L...L..L..<'-'-..L...I.'-L...L...I.""""L..L..L-L...L..L..<'-'-..L...I.:L-_ _L-~'---I(COMMAND)
LINK OFFSET

r--.~~---r--~r7r----------------------------------------i4
LN!<
OK

~~'--~

__""""__

~~L-

TIME
______________________________________

231246-17

Figure 17. The.TDR Command Block

1-20

82586

LINK OFFSET: Address of next Command Block

STATUS word (written by 82586):
C
B
OK

RESULT word:
LNK-OK

(Bit 15)

• No Link Problem
. Identified
XCVR-PRB (Bit 14)
• Transceiver Cable
Problem identified (valid
only in the case of a
Transceiver that does not
return Carrier Sense
during transmission).
ET-OPN
(Bit 13)
• Open on the link
identified (valid only in
the case of a Transceiver
that returns Carrier Sense
during transmission).
• Short on the link
ET-SRT
(Bit 12)
identified (valid only in
the case of a Transceiver
that returns Carrier Sense
during transmission).
(Bits 0-10) • Specifying the distance to
TIME
a problem on the link (if
one exists) in transmit
clock cycles.

(Bit 15)
(Bit 14)
(Bit 13)

• Command Completed
• Busy Executing Command
• Error Free Completion

COMMAND word:
EL
S
I
CMD

(Bit 15)
(Bit 14)
(Bit 13)
(Bits 0-2)

•
•
•
•

End of Command List
Suspend After Completion
Interrupt After Completion
DUMP = 6

LINK OFFSET: Address of next Command Block
BUFFER OFFSET: This word specifies the offset
portion of the memory address which points to the
top of the buffer allocated for the dumped registers
contents. The length of the buffer is 170 bytes.

DUMP AREA FORMAT
Figure 18 shows the format of the DUMP area. The
fields are as follows:
Bytes OOH to OAH: These bytes correspond to the
82586 CONFIGURE command field.

DUMP
Bytes OCH to 11 H: The Individual Address Register
content. IARO is the Individual Address least significant byte.

This command causes the contents of over a hundred bytes of internal registers to be placed in memory. It is supplied as a self diagnostic tool, as well as
to supply registers of intere!>t to the user.

Bytes 12H to 13H: Status word of last command
block (only bits 0-13).

DUMP command includes the following fields:

15
C

I--I--f--i-::::......."::::>""-::::-"::::>""-::::-"::::>""-::::-"::::>""-::::-"::::>""-::::-"::::>""--:;;;,.,--,--,---i (STATUS)
EL

CMD=6

~_L-~_~~~~~~~~~~~~~~~~~~~~~-~_~--;(COMMAND)
LINK OFFSET

1------____________- - - - - - - - - - - - - - i 4
BUFFER OFFSET

231246-18

Figure 18. The DUMP Command Block

1-21

82586
Bytes 14H to 17H; Content of the Transmit CRC
generator. TXCRCRO is the least significant byte.
The contents are dependent on the activity before
the DUMP command:

15 14

13 12 11 10

•

'(II I I II I I I 1IIIIIIl

..••

NXT Ae ADA (HIGH)

NXT AS ADA (LOW)

ELJXI

After RESET - 'All Ones.'

CUR AI SIZE

LA ABO ADA

•
•

NXTABD ADA

After successful transmission - 'All Zeros'.

CUR ABO ADA

After unsuccessful transmission, depends on where
it stopped.

•

CUR RS EBC

After MC-SETUP command - Generated CRC value
of the last MC address, on MC-LlST.
(O~

I><: i;><;

ex FR c....

RNR

HASHRS

HASHA 4

HASHR 6

IX }II I.J" I)<; I)<; I)<; IX IX I)<; I)<; I)<;
1 X X I}II }II X
I2S I2S ~ I2S ~
0

IX X IX X x x X .J" /\ IX IX 1)\ IA /<.. /<.. X

NXTRB SIZE

BUF

IX X IX,
0

ADR LEN

RU
lOt

'"'

, ••

~.c.

RU
ROW

...

(

.u"

/\ 1/\ 1/\ IX IXC><:
0

)<,12';
)<,12';

0
AOR

PRT

01 0 1 0 1 0 1 0

oI0

BUF ADA PTR (HIGH)

(LOW)

ADA. H

8'
8A

Rev DMA AOR H

Rev OMA AoR l

IX [2<: 12<:
IX IX IX

)< )<

BA· BUF

,
,

RCYDMABC

012<:

x;x

HASHA 7

)<,

X-

X X

IX IX IX IX IX X- IX I/'- 1/\ 1/\
0 0 0 0
0
0
0 0
0
0
IX
X- X
X

)<,

lA'

:~~ l~ 0

•
•,

x IX IX IX X [2<: [2<: 2S 2S 1,0 X IX'C

HA5HR 2

ELIX

HASHA 3

'"1

HASHR 0

)<, )<, )<,

°IX

LIM

HASHR 1

FIFO

20
1

)<,

IX X X X

AXCRCR 2

TEMPR 1

)<, )<,

TXCRCA 1

X X )<,
IX !A X )<, 1)<, IX IX /\ 'J',
)<,

•
6

tAR 2

SeB ADR

IAR 0

lST

I}II

IX XIX

O•

IAR 3

CUR CB ADR

IAR 1

RXCReR 3

3
0

SLOT TIME (LOW)

tAR 5

ACR

1 [sLT TM [HI

~~~

•

XL 0] 0

. .0

INTERFRAME SPACING
AETRY

FIFO LIM

IXIXIX\.X.l

$'(1)'

.....

231246-20

231246-19

Figure 19. The DUMP Area

1-22

inter

82586

Bytes iSH to iBH: Contents of Receive CRC
Checker. RXCRCRO is the least significant byte.
The contents are dependent on the activity performed before the DUMP command:

CUR-RB-EBC: Current Receive Buffer Empty Byte
Count Let N be the currently used Receive Buffer.
Then CUR-RB-EBC indicates the Empty part of the
buffer, i.e. the ACT-COUNT of buffer N is given by
the difference between its SIZE and the CUR-RBEBC.

After RESET - 'All Ones.'

NXT-FD-ADR: Next Frame Descriptor Address. Define N as the last Receive Frame Descriptor with bits
C = 1 and B = 0, then NXT-FD-ADR is the address
of N + 2 Receive Frame Descriptor (with B = C =
0) and is equal to the LINK-ADDRESS field in N + 1
Receive Frame Descriptor.

After good frame reception1. For CRC-CCITT - OIDOFH
2. For CRC-Autodin-II - C704DD7BH
After Bad Frame reception - corresponds to the received information.

CUR-FD-ADR: Current Frame Descriptor Address.
Similar to next NXT-FD-ADR but refers to N + 1
Receive Frame Descriptor (with B = 1, C = 0).

After reception attempt, i.e. unsuccessful check for
address match, corresponds to the CRC performed
on the frame address.

Bytes 54H to 55H: Temporary register.
NOTE:
Any frame on the serial link modifies this register
contents.

NXT-TB-CNT: Next Transmit Buffer Count. Let N be
the last transmitted buffer of the TRANSMIT command executed recently, the NXT-TB-CNT is the
ACT-COUNT field in the Nth Transmit Buffer Descriptor. EOF - Corresponds to the EOF bit of the
Nth Transmit Buffer Descriptor. EOF = 1 indicates
that the last buffer accessed by the 82586 during
Transmit was the last Transmit Buffer in the data
buffer chain associated with the Transmit Command.

Bytes 1CH to 21H: Temporary Registers.
Bytes 22H to 23H: Receive Status Register. Bits 6,
7, 8, 10, 11 and 13 assume the same meaning as
corresponding bits in the Receive Frame Descriptor
Status field.
Bytes 24H to 2BH: HASH TABLE.

BUF-ADR: Buffer Address. The BUF-PTR field in the
DUMP-STATUS Command Block. '

Bytes 2CH to 2DH: Status bits of the last time TOR
I command that was performed.

NXT-TB-AD-L: Next Transmit Buffer Address Low.
Let N be the last Transmit Buffer in the transmit buffer chain of the TRANSMIT Command performed
recently, then NXT-TB-AD-L are the two least significant bytes of the Nth buffer address.

NXT-RB-SIZE: Let N be the last buffer of the last
received frame, then NXT-RB-SIZE is the number of
bytes of available in the N + 1 buffer. EL - The EL
bit of the Receive Buffer Descriptor.

LA-TB-ADR: Look Ahead Transmit Buffer Descriptor Address. Let N be the last Transmit Buffer in the
transmit buffer chain of the TRANSMIT Command
performed recently, then LA-TBD-ADR is the NEXTBD-ADDRESS field of the Nth Buffer Descriptor.

NXT-RB-ADR: Let N be the last Receive Buffer
used, then NXT-RB-ADR is the BUFFER-ADDRESS
field in the N + 1 Receive-Buffer Descriptor, i.e. the
pointer to the N + 1 Receive Buffer.
CUR-RB-SIZE: The number of bytes in the last buffer of the last received frame. EL - The EL bit of the
last buffer in the last received frame.

NXT-TBD-ADR: Next Transmit Buffer Descriptor
Address. Similar in function to LA-TBD-ADR but related to Transmit Buffer Descriptor N-1. Actually, it is
the address of Transmit Buffer Descriptor N.

LA-RBD-ADR: Look Ahead Buffer Descriptor, i.e.
the pointer to N + 2 Receiver Buffer Descriptor.

Bytes 60H, 61H: This is a copy of the 2nd word in
the DUMP-STATUS command presently executing.

NXT-RBD-ADR: Next Receive Buffer Descriptor Address. Similar to LA-RBD-ADR but points to N + 1
Receive Buffer Descriptor. .

NXT-CB-ADR: Next Command Block Address. The
LINK-ADDRESS field in the DUMP Command Block
presently executing. Points to the next command.

CUR-RBD-ADR: Current Receive Buffer Descriptor
Address. Similar to LA-RBD-ADR, but point to Nth
Receive Buffer Descriptor.

CUR-CB-ADR: Current Command Block Address.
The address of the DUMP Command Block currently
executing.

1-23

intJ

82586

SCB-ADR: Offset of the System Control Block
(SCB).
Bytes 7EH, 7FH:

RU-SUS-RQ (Bit 4) - Receive Unit Suspend Request.
Bytes 80H, 81H:

CU-SUS-RQ (Bit 4) - Command Unit Suspend Request.
END-OF-CBL (Bit 5) - End of Command Block List. If
"1" indicates that DUMP-STATUS is the last command in the command chain.
ABRT-IN-PROG (Bit 6) - Command Unit Abort Request.

1. If AL-LOCation = 0 then RCV-DMA-BC = (2
times ADDR-LEN plus 2) if the next Receive
Frame Descriptor has already been fetched.
2. If AL-LOCatidn = 1 then it contains the size of
the next Receive Buffer.
BR + BUF - PTR + 96H - Sum of Base Address plus
BUF - PTR field and 96H.
RCV-DMA-ADR - Receive DMA absolute Address.
This is the next RCV-DMA start address. The value
depends on AL~LOCation configuration bit.
1. If AL-LOCation = 0, then RCV-DMA-ADR is the
Destination Address field located in the next Receive Frame Descriptor.
2. If AL-LOCation = 1, then RCV-DMA-ADR is the
next Receive Data Buffer Address.
The following nomenclature has been used in the
DUMP table:

RU-SUS-FD (Bit 12) - Receive Unit Suspend Frame
Descriptor Bit. Assume N is the Receive Frame Descriptor used recently, then RU-SUS-FD is equivalent to the S bit of N + 1 Receive Frame Descriptor.

• The 82586 writes zero in this location.

1
X

• The 82586 writes one in this location.
• The 82586 writes zero or one in this
location.
• The 82586 copies this location from the
corresponding position in the memory
structure.

III

Bytes 82H, 83H:

RU-SUS (Bit 4) - Receive Unit in SUSPENDED state.
RU-NRSRC (Bit 5) - Receive Unit in NO RESOURCES state.

DIAGNOSE

RU-RDY (Bit 6) - Receive Unit in READY state.

The DIAGNOSE Command triggers an internal self
test procedure of backoff related registers and counters.

RU-IDL (Bit 7) - Receive Unit in IDLE state.
RNR (Bit 12) - RNR Interrupt in Service bit.
CNA (Bit 13) - CNA Interrupt in Service bit.

The DIAGNOSE command includes the following:
STATUS word (written by 82586):

FR (Bit 14) - FR Interrupt in Service bit.
CX (Bit 15) - CX Interrupt in Service bit.

C
B

(Bit 15)
(Bit 14)

OK
FAIL

(Bit 13)
(Bit 11)

Bytes 90H to 93H:

BUF-ADR-PTR - Buffer pointer is the absolute address of the bytes following the DUMP Command
block.

• Command Completed
• Busy Executing
Command
• Error Free Completion
• Indicates that the Self
Test Procedured Failed

COMMAND word:

EL
S

(Bit 15)
(Bit 14)

(Bit 13)

CMD

(Bits 0-2)

Bytes 94H to 95H:

RCV-DMA-BC - Receive DMA Byte Count. This field
contains number of bytes to be transferred during
the .next Receive DMA operation. The value depends on AL-LOCation configuration bit.

• End of Command List
• Suspend After
Completion
• Interrupt After
Completion
• DIAGNOSE = 7

LINK OFFSET: Address of next Command Block.

1-24

inter

82586

15
C

1--t-+-i---7'-:::~~~""?'----:::::""-::~"7'-:::;::O----:::::~'7"-:;::;>-:::;::o,..,.--'-_-r---;(STATUS)
EL

CMD=7

1---L_....L._....::;......::~.:::.-..::;.......::;......::::;.......:::.-..::;;........::;......::::.......::;.......e::;.......::~~_....L._-'---i (COMMAND)

LINK OFFSET

231246-21

Figure 20. The DIAGNOSE Command Block

COMMAND
BLOCK
LIST
RECEIVE FRAME AREA

RECEIVE
FRAME
DESCRIPTORS

RECEIVE
BUFFER
DESCRIPTORS

RECEIVE
BUFFERS
BUFFER 1
,_

BUFFER 2

RECEIVE FRAME LIST

BUFFER 4 '

BUFFER 3

-.1'4._ __

FREE FRAME LIST

231246-22

Figure 21. The Receive Frame Area

RECEIVE FRAME AREA (RFA)

FRAME DESCRIPTOR (FD) FORMAT

The Receive Frame Area, RFA, is prepared by the
host CPU, data is placed into the RFA by the 82586
as frames are received. RFA consists of a list of
Receive Frame Descriptors (FD), each of which is
associated with a frame. RFA·OFFSET field of SCB
points to the first FD of the chain; the last FD is
identified by the End-of-Listing flag (EL). See Figure
'
21.

The FD includes the following fields:
STATUS word (set by the 82586);

1-25

(Bit 15)

(Bit 14)

• Completed Storing
Frame.
• FD was Consumed by
RU.

Intel

82586

EVEN BYTE

C
~-t

ZEROS

__-+~~~~~~~~~~~~~__~~~~__~~~~__~(STATUS)

S
LINK OFFSET

RBD-OFFSET
2ND BYTE

1ST BYTE

DESTINATION ADDRESS

10
r-~N~T_H~BY_T~E

__________________~r-__________________________~12

2ND BYTE

1ST BYTE
14
SOURCE ADDRESS

~~N~T~H~BY~T~E

2ND BYTE

____________________

________________________

~~18

1ST BYTE

LENGTH FIELD

231246-23

Figure 22. The Frame Descriptor (FD) Format
OK

(Bit 13)

S11

(Bit 11)

S10

(Bit 10)

(Bit 9)

S8
S7

(Bit 8)
(Bit 7)

(Bit 6)

• Frame received
successfully. If this bit is
set, then all others will be
reset; if it is reset, then
the other bits will indicate
the nature of the error.
• Received Frame
Experienced CRC Error.
• Received Frame
Experienced an
Alignment Error.
• RU ran out of resources
during reception of this
. frame.
• RCV-DMA Overrun.
• Received frame had
fewer bits than
configured Minimum
Frame Length.
• No EOF flag detected
(only when configured to
Bitstuffing).

LINK OFFSET: Address of next FD in list.
RBD-OFFSET: (initially prepared by the CPU and later may be updated by 82586): Address of the first
RBO that represents the Information Field. ABOOFFSET = OFFFFH means there is no Information
Field.
DESTINATION ADDRESS (written by 82586):
Contains Destination Address of received frame.
The length in bytes, it is determined by the Address
Length configuration parameter.
SOURCE ADDRESS (written by 82586): Contains
Source Address of received frame. Its length is the
same as DESTINATION ADDRESS.
LENGTH FIELD (written by 82586):.Contains the 2
byte Length or Type Field of received frame.

RECEIVE BUFFER DESCRIPTOR
FORMAT
The Receive Buffer Descriptor (RBD) holds information about a buffer; size and location, and the means
for forming a chain of RBOs, (forward pointer and
end·of-frame indication).

COMMAND word:
EL
S

(Bit 15)
(Bit 14)

• Last FD in the List.
• RU should be suspended
after receiving this frame.

The Buffer Descriptor contains the following fields.

1-26

82586

15
EOF

ACT COUNT
o
~--l._-'-_..L...-----JI...----L_....I-_.L.-----JI...----L_....I-_"'--......I......-..L..-.---L_-'---I (STATUS)
NEXT BO OFFSET

BUFFER ADDRESS

4
6

A23

SIZE

231246-24

Figure 23. The Receive Buffer Descriptor (RBD) Format
BUFFER ADDRESS: 24·bit absolute address of
buffer.

STATUS word (written by the 82586).

EOF

(Bit 15)

(Bit 14)
F
ACT
(Bits 0-13)
COUNT

• Last buffer in received
frame.
• ACT COUNT fi~ld is valid.
• Number of bytes in the
buffer that are actually
occupied.

EL/SIZE:

EL
SIZE

NEXT RBD OFFSET: Address of next BO in list of
BO's.

1·27

(BIT 15)
(Bits 0-13)

• Last BO in list.
• Number of bytes the
buffer is capable of
holding.

Intel

82586

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Ambient Temperature Under Bias ...... O·C to 70·C

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress· ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

Storage Temperature ............. - 65·C to 150·C
Voltage on Any Pin with
Respect to Ground .............. -1.0V to + 7V
Power Dissipation ...................... 3.0 Watts

D.C. CHARACTERISTICS
TA = O·C to 70·C, Te = O·C to 105·C, Vee = 5V ± 10%, CLK has MOS levels (See VMIL, VMIH, VMOL,
VMOH). TxC and RxC have 82C501 compatible levels (VMIL' VTIH, VRIH). All other signals have TTL levels (see
VIL, VIH, VOL, OH)·

Symbol

Min

Max

Units

VIL

Input Low Voltage (TTL)

Parameter

-0.5

+0.8

VIH

Input High Voltage (TTL)

2.0

Vee'+ 0.5

VOL

Output Low Voltage (TTL)

VOH

Output High Voltage (TTL)

2.4

VMIL

Input Low Voltage (MOS)

-0.5

0.6

VMIH

Input High Voltage (MOS)

3.9

Vee + 0.5

VTIH

Input High Voltage (TxC)

3.3

Vee + 0.5

3.0

Vee + 0.5

0.45

Test Conditions

V,
V

IOL = 2.5mA

IOH - 400 /LA

VRIH

Input High Voltage (RxC)

VMOL'

Output Low Voltage (MOS)

VMOH

Output High Voltage (MOS)

IOH - 400 /LA

III

Input Leakage Current

±10

/J- A

0:::;; VIN:::;; Vee
0.45 :::;; VOUT :::;; Vee

Vee - 0.5

IOL2.5 mA

ILO

Output Leakage Current

±10

/J- A

CIN

Capacitance of Input Buffer

FC = 1 MHz

COUT

Capacitance of Output Buffer

FC = 1 MHz

lee

Power Supply Current

550
450

TA = O·C
TA = 70·C

1-28

82586

SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS
T A = O·G to 70·G, T e = O·G to 105·G, Vee = 5V ± 10%. Figures 24 and 25 define how the measurements
should be done.
'

INPUT AND OUTPUT WAVEFORMS FOR A.C. TESTS
2.4==><:1.5 _ _ TEST POINTS - - 1 . 5
0.45

231246-25
AC Testing Inputs are Driven at 2.4V for a Logic 1 and 0.45 for a Logic O. Timing measurements are made at 1.5V for both a Logic 1 and 0

Figure 24. TTL Input/Output Voltage Levels for Timing Measurements

231246-26
MOS 110 measurements are taken at 0.1 and 0.9 of the voltage swing

Figure 25. System Clock CMOS Input Voltage Levels for Timing Measurements

1-29

82586

INPUT TIMING REQUIREMENTS'
Parameter

Symbol

82586·6
(6 MHz)

82586
(8 MHz)

82586·10
(10 MHz)

Min

Max

Min

Max

Min

Max

125

2000

100

200

1000

42.5

1000

42.5

1000

Comments

ClK Cycle Period

166

2000

ClK low Time at 1.5V

1000

ClK low Time at 0.9V

ClK High Time at 1.5V .

ClK High Time at 3.6V

ClK Rise Time

Note 1

ClKFaliTime

Note 2

Data in Setup Time

Data in Hold Time

T10

Async RDY Active Setup Time

T11

Async RDY Inactive Setup Time

Note 3

T12

Async RDY Hold Time

Note 3

T13

Synchronous ReadyLActive Setup

T14

Synchronous Ready Hold Time

T15

HlDA Setup Time

Note 3

T16

HlDA Hold Time

Note 3

T17

Reset Setup Time

Note 3

T18

Reset Hold Time

Note 3

1 T1

42.5

,
Note 3

T19

CA Pulse Width

1 T1

T20

CA Setup Time

Note 3

T21

CA Hold Time

Note 3

OUTPUT TIMINGS"
Symbol

Parameter

Min

Max

Min

Max

Min

Max

T22

DT fR Valid Delay

T23

WR, DEN Active Delay

Comments

T24

WR, DEN Inactive Delay

T25

Int. Active Delay

85.

Note 4

T26

Int. Inactive Delay

Note 4

T27

Hold Active Delay

Note 4

T28

Hold Inactive Delay

Note 4

T29

Address Valid Delay

T30

Address Float Delay

T31

Data Valid Delay

T32

Data Hold Time

T33

Status Active Delay

1-30

Note 7

intJ

82586

(Continued)

OUTPUT TIMINGS"

82582-6
(6 MHz)

Parameter

Symbol

82586-10
(10 MHz)

82586
(8 MHz)

Min

Max

Min

Max

Min

Max

Comments

T34

Status Inactive Delay

Note 8

T35

ALE Active Delay

Note 5

T36

ALE Inactive Delay

Note 5

T37

ALE Width

T2-10

T38

Address Valid to ALE Low

T2-40

T2-30

T2-25

T39

Address Hold to ALE Inactive

T4-10

T40

RD Active Delay

T41

RD Inactive Delay

T42

RDWidth

T43

Address Float to RD Active

T44

RD Inactive to Address Active

T1-40

T1-34

T45

WRWidth

2T1-40

2T1-34

T46

Data Hold After WR

T2-25

T47

Control Inactive After Reset

2T1-50

Note 5

2T1-46

T2-25
60

Note 6

• All units are In ns.
• 'CL on all outputs is 20-200 pF unless otherwise specified.
NOTES:
1. 1.0V to 3.5V
2. 3.5V to 1.0V
3. To guarantee recogniti6n at next clock
4. CL = 50 pF
5. CL = 100 pF

6. Affects:
MIN MODE: RD, WR, DT lA", DEN
MAX MODE: SO, S1
7. High address lines (A16-A24, SHE) become valid one
clock before T1 only on first memory cycle after the 62566
acquired the bus.
6. S1, SO go inactive just prior to T4.

CLK

T26

T25

INT _ _\--J

231246-27

231246-28

Figure 26. INT Output Timing

Figure 27. CA Input Timing

ClK
_T17

RESET

T47

RD. WH. DEN.DT/A.

-------...;..-----h---

so. 51
231246-29

Figure 28. RESET Timing

1-31

Intel

82586

READY SIGNAL

ARDY
82586
INPUT

SRDY

OR
READY
82586 INPUTS

231246-30

Figure 29. ARDY and SRDY Timings Relative to ClK

~
LK.

(~ ~
~
.. ~

HOLD

...

-T27

HLDA
SHE ADO-AI1U

A::T7lf~~
CPU- MASTER

T28

T164

I~~

82586-MASTER

TaO

Figure 30. HOlD/HlDA Timing Relative to ClK

1-32

, 231246-31

82586

vel

r-T4

scSi

-- ~ U-L I'----'~~

.!!

I 1 I
HT34

T29_

A16-A1S A20-A23

A 19156

r--

1:=- ,'--

A19

T32-

} r--

AlE
T3S-

ADO -AD15

T29--

iiEN

---

1-T36
T3S
~
AO-A1S

DTIR

,,- - -

iE2

DATA IN

T39

l::::::.1
'"

_ T43

I
T42

T40

- II

T23

T44

T41 _

-V

T22

~T24

231246-32

Figure 31. Read Cycle Timing

¥.-'----J
VCl

SlI ~

r-r
TW

T1
VCH

,r-=--.

tr----\

T6_

r--

~
~

"----'
---"'--

I--

I
T34

)(1--

A19156

A19

ALE
T35-

i" r--I-

-T31

T32-

_T31

T32

WI\

CiVl

T23_

-T39

DATA OUT

I-- no

~ r-

T45

~T23

T24-

1'-

f-f--

AO-A15

T29-

---<\

-T36

ADO-AD15

T29-

Iffi£ A16-A1S A20-A23

r- -

---

~-C

I-

T24

231246-33

Figure 32. Write Cycle Timing

1-33

Intel

82586

for Manchester:

SERIAL INTERFACE A.C. TIMING
. CHARACTERISTICS

f min = 500 kHz± 100 ppm
f max = 10 MHz ± 100 ppm

CLOCK SPECIFICATION
Applies for

for Manchester, symmetry is needed:

TxC, RxC for NRZ:

f min = 100 kHz ± 100 ppm

T51 , T52 = 2.
2f ±5%

f max = 10 MHz ± 100 ppm

A.C. CHARACTERISTICS
TRANSMit AND RECEIVE TIMING PARAMETER SPECIFICATION'
Min

Max

Comments

TxCCycle

100

1000

Notes 14, 2

T48

TxCCycie

100

T49

TxC Rise Time

Symbol

Parameter

TRANSMIT CLOCK PARAMETERS
T48

T50

TxCFallTime

T51

TxC High Time @ 3.0V

T52

TxC Low Time @0.9V

Notes 14, 3
5

Note 14

1000

Note 14
Notes 14, 4

TRANSMIT DATA PARAMETERS

T53

TxD Rise Time

T54

TxD Fall Time

T55

TxD Transition-Transition

T56

TxC Low to TxD Valid

Notes 3, 5

T57

TxC Low to TxD Transition

Notes 2, 5

T58

TxC High to TxD Transition

Notes 2, 5

T59

TxC Low to TxD High at the Transmission End

Note 5

Note 6

Notes5,13

,10

Notes5,13

Min (T51,
T52) - 7

Notes 2, 5

REQUEST TO SEND/CLEAR TO SEND PARAMETERS
T60

TxC Low to RTS Low. Time-to Activate RTS

T61

CTS Valid to TxC Low. CTS Setup Time

T62

TxC Low to CTS Invalid. CTS Hold Time

T63

TxC Low to RTS High, time to Deactivate RTS

Note 7
40

Note 6

RECEIVE CLOCK PARAMETERS
T64

RxC Clock Cycle

100

Notes 15,3

T65

Rxe Rise Time

Note 15

T66

RxCFallTime

Note 15

T67

RxC High Time

1000

Note 15

T68

RxC Low Time @0.9V

2.7V

36
40

• All units are in ns.

1-34

Note 15

inter

82586

A.C. CHARACTERISTICS (Continued)
TRANSMIT AND RECEIVE TIMING PARAMETER SPECIFICATION' (Continued)
Symbol

Parameter

Min

Max

Comments

RECEIVE DATA PARAMETERS
T69

RxD Setup Time

Note 1

T70

RxD Hold Time

Note 1

T71

RxD Rise Time

Note 1

T72

RxD Fall Time

Note 1

CARRIER SENSE/COLLISION DETECT PARAMETERS
T73

CDT Valid to TxC High Ext. Collision
Detect Setup Time

Note 12

T74

TxC High to CDT Inactive. CDT Hold Time

Note 12

T75

CDT Low to Jamming Start

Note 8

T76

CRS Valid to TxC High Ext. Carrier Sense Setup Time

Note 12

T77

TxC High to CRS Inactive. CRS Hold Time

Note 12

T78

CRS Low to Jamming Start

Note 9

T79

Jamming Period

Note 10

T80

CRS Inactive Setup Time to RxC High
End of Receive Frame

T81

CRS Active Hold Time from RxC High

INTERFRAME SPACING PARAMETER
T82

Inter Frame Delay

Note 11

* All Units are In ns.
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.

TTL levels
Manchester only
NRZ only
Manchester requires 50% duty cycle
1 TTL load + 50 pF
1 TTL load + 100 pF
Abnormal end of transmission. CTS expires before RTS
Programmable value:
T75 = NCDF x T48 + (12.5 to 23.5) x T 48 if collision occurs after preamble
NCDF-The collision detection filter configuration value
9. Programmable value:
T78 = NCSF x T48 + (12.5 to 23.5) x T48
NCSF-The carrier sense filter configuration value
TBD is a function of internal/ external carrier sense bit
10. T79 = 32 x T48
11. Programmable value:
T82 = NIFS x T48
NIFS-the IFS configuration value
* 12. To guarantee recognition on the next clock
13. Applies to TTL levels
14. 82C501 compatible levels, see Figure 34
15. 82C501 compatible levels, see Figure 35

1-35

82586

A.C. TIMING CHARACTERISTICS
Input and Output Waveforms for AC Tests

o::~'J --TEST POINTS - - ~.5

231246-34
AC testing inpuis are driven at 2.4V for a Logic 1 and 0.45 for a Logic O. TIming measurements are ma~e at 1.5V for both a Logic 1 and O.

Figure 33. TTL Input/Output Voltage Levels for Timing Measurements

\ - - - - T. .

-----

'\
II
a.tv -- ----- a.lv

WITH Vee

,-r

L-'::~~

3.3V ~

•.ov --'

HIGH LEVELS MAY VARY

----I

-----

--------

I-- TS2- I-- TS'T........

I-- TSO
231246-35

Figure 34. TxC Input Voltage Levels for Timing Measurements

1---- T14 ---~

,-----,

HIGH LEVELS MAY VARY
WITH Vee

I-----~

231246-36

Figure 35. RxC Input Voltage Levels for Timing Measurements

1-36

inter

82586

~----~+-+-~-------++---------~~
CR.i------4-4--r-------++---------~~

--:!::-t~
T51

TSI

T53

T54

231246-37

T~
iiTlI-------

m----------

cDT------~l=!

T16

T55

TX~=~~=.r---~ =~~

(MANCHESTER)

231246-38

Figure 36. Transmit and Control and Data Timing

R.D

231246-39

Figure 37. RxD Timing Relative to RxC

231246-40

Figure 38. CRS Timing Relative to RxC

1-37

82596CA
HIGH-PERFORMANCE 32-BIT LOCAL
AREA NETWORK COPROCESSOR
• Performs Complete CSMA/CD Medium
Access Control (MAC) FunctionsIndependently of CPU
-IEEE 802.3 (EOC) Frame Delimiting
- HDLC Frame Delimiting

• Optimized CPU Interface
- Optimized Bus Interface to Intel's
i486™ and 80960CA Processors
- Supports Big Endian and Little
Endian Byte Ordering

• Supports Industry Standard LANs
-IEEE TYPE 10BASE5 (Ethernet*),
IEEE TYPE 10BASE2 (Cheapernet),
IEEE TYPE 1BASE5 (StarLAN),
and the Proposed Standards
TYPE 10BASE-T and 10BASE-F
- Proprietary CSMA/CD Networks Up
to 20 Mb/s

•

32-Bit Bus Master Interface
-106 MB/s Bus Bandwidth
- Burst Bus Transfers
- Bus Throttle Timers
- Transfers Data at 100% of Serial
Bandwidth
-128-Byte Receive FIFO, 64-Byte
Transmit FIFO

• On-Chip Memory Management
- Automatic Buffer Chaining
- Buffer Reclamation after Receipt of
Bad Frames; Optional Save Bad
Frames
- 32-Bit Segmented or Linear (Flat)
Memory Addressing Formats

•

Self-Test Diagnostics

• Configurable Initialization Root for Data
Structures
•

High-Speed, 5V, CHMOS** IV
Technology·

•

132-Pin Plastic Quad Flat Pack (PQFP)
and PGA Package

• Network Management and Diagnostics
- Monitor Mode
- 32-Bit Statistical Counters

(See Packaging Spec Order No. 231369)
i486 is a trademark of Intel Corporation.
'Ethernet is a registered trademark of Xerox Corporation.
"CHMOS is a patented process of Intel Corporation.

.• 82586 Software Compatible
~

- - - - - - - - -

~e~a~

- - - - - - -

TxC
TxD

CRS

I
I

Transmit
Bit
Machine

Transmit
Byt.
Machine

RxD
RxC

I
I
I
I
I

I
I
I
I
IL

logic

Exponential

Receive
Bit
Machine

FIFO

Switch

Receive
Byt.
Machine

I
I
I
I
I
I
I
I

;0-

32 Bit DBus

f---+

_____________________

"
~

32 Bit DBus
I
I
I
I
I

jj:ntrol

I I
I I
I I
I I
I I
.I. .I.

~
~
,
'"
0

Bus

-I\,

Control

"I
I
I
I
I
I
I
I

Data Bus

I
I
I
I
I

Interface
Unit
(BtU)

PORT

Micro'
Machine

________

I
I

Data
Interface
Unit
(DIU)

-YI~

I LEISE

. ------ .

I
I
I
I
I
I I

Control

Collision

Timer

I I
I

~
I
I
8 I
I
---..I
--I

Carrier

Backoff

Parallel

Subsystem

Detect
I
I
I
I
I
I
I
I
I

1"'-------------,

Sense
COT

Subsystem

LPBK I
RTS I
CTS

FU?O - - -

r - -

Subsystem

D~A

L-.y'
:... _ _ _ _ _ _ _ _ _ _ _ _ _

Address

")
~

I Byte Enable )
..I

290218-1

Figure 1. 82596CA Block Diagram

1-38

October 1990
Order Number: 2902.18-003

82596CA

82596CA High-Performance 32-Bit
local Area Network Coprocessor
CONTENTS

CONTENTS

PAGE

INTRODUCTION ........................ 1-40

RECEIVE UNIT (RU) .................... 1-63

PIN DESCRiPTIONS .................... 1-44

SYSTEM CONTROL BLOCK (SCB) ..... 1-63

82596 AND HOST CPU
INTERACTION ....................... 1-48

SCB OFFSET ADDRESSES ............. 1-66
CBL Offset (Address) .................... 1-66

82596 BUS INTERFACE ................ 1-48

RFA Offset (Address) ................... 1-66

82596 MEMORY ADDRESSING ........ 1-48

SCB STATISTICAL COUNTERS ........ 1-67

82596 SYSTEM MEMORY
STRUCTURE ......................... 1-50

Statistical Counter Operation ............ 1-67
ACTION COMMANDS AND
OPERATING MODES ................. 1-68
NOP .................................... 1-69

TRANSMIT AND RECEIVE MEMORY
STRUCTURES ........................ 1-51

Individual Address Setup ................ 1-69
Configure ............................... 1-70

TRANSMITTING FRAMES .............. 1-54
RECEIVING FRAMES ................... 1-55

Multicast-Setup ......................... 1-76

82596 NETWORK MANAGEMENT AND
DIAGNOSTICS ....................... 1-55

Transmit ................................ 1-77
Jamming Rules .......................... 1-79

NETWORK PLANNING AND
MAINTENANCE ...................... 1-57

TDR .................................... 1-80

STATION DIAGNOSTICS AND SELFTEST ................................. 1-58

Diagnose ................................ 1-85

Dump ................................... 1-82

RECEIVE FRAME DESCRIPTOR ....... 1-86
82586 SOFTWARE COMPATIBILITY ... 1-58

Simplified Memory Structure ............. 1-86

INITIALIZING THE 82596 ............... 1-58

Flexible Memory Structure ............... 1-87

SYSTEM CONFIGURATION POINTER
(SCP) ................................. 1-58

Receive Buffer Descriptor (RBD) ......... 1-88
ELECTRICAL AND TIMING
CHARACTERISTICS ................. 1-93
DC Characteristics ...................... 1-93

Writing the Sysbus ...................... 1-59
INTERMEDIATE SYSTEM
CONFIGURATION POINTER
(ISCP) ................................ 1-60

AC Characteristics ...................... 1-94
82596CA Input/Output System
Timings ........ : ...................... 1-94

INITIALIZATION PROCESS ............ 1-60
CONTROLLING THE 82596CA ......... 1-61

Transmit/Receive Clock Parameters ..... 1-96
82596CA BUS Operation ................ 1-99

82596 CPU ACCESS INTERFACE
(PORT) ............................... 1-61

System Interface AC Timing
Characteristics ........ . . . . . . . . . . . . . . . 1-1 00

MEMORY ADDRESSING FORMATS . ... 1-62

Input Waveforms ....................... 1-101
Serial AC Timing Characteristics ........ 1-103

LITTLE ENDIAN AND BIG ENDIAN
BYTE ORDERING .................... 1-62

OUTLINE DIAGRAM ................... 1-105

COMMAND UNIT (CU) .................. 1-62

REVISION HISTORY .................. 1-109
1-39

intJ

82596CA

INTRODUCTION
The 82596CA is an intelligent, high-performance
32-bit Local Area Network coprocessor. The
82596CA implements the CSMAlCD access method
and can be configured to support all existing IEEE
802.3 standards-TYPEs 10BASE5, 10BASE2,
1BASE5, and 10BROAD36. It can also be used to
implement the proposed standards TYPE 1OBASE-T
and 10BASE-F. The 82596CA performs high-level
commands, command chaining, and interprocessor
communications via shared memory, thus reljeving
the host CPU of many tasks associated with network
control. All time-critical functions are performed independently of the CPU, this increases network performance and efficiency. The 82596CA bus interfaces is optimized for Intel's i486™, 80960CA, and
80960KB processors.
The 82596CA implements all IEEE. 802.3 Medium
Access Control and channel interface functions,
these include framing, preamble generation and
stripping, source address generation, destination address checking, short-frame detection, and automatic length-field handling. Data rates up to 20 Mb/s ar(;l
supported.
The 82596CA provides a powerful host system interface. It manages memory structures automatically,
with command chaining and bidirectional data chaining. An on-chip DMA controller manages four channels, this allows autonomous transfer of data blocks
(buffers and frames) and relieves the CPU of byte
transfer overhead. Buffers containing errored or collided frames can be automatically recovered without
CPU intervention. The 82596CA provides an upgrade path for, existing 82586 software drivers by
providing an 82586-software-compatible mode that
supports the current 82586 memory structure. The
82586CA also has a Flexible memory structure and
a Simplified memory structure. The 82596CA can
address up to 4 gigabytes of memory. The 82596CA
supports Little Endian and Big Endian byte ordering.
The 82596CA bus interface can achieve a burst
transfer rate of 106 MB/s at 33 MHz. The bus inter-

face employs bus throttle timers to regulate
82596CA bus use. Two large, independent FIFOs128 bytes for Receive and 64 bytes for Transmittolerate long bus latencies and provide programmable thresholds that allow the user to optimize bus
overhead for any worst-case bus latency. The highperformance bus is capable of back-to-back transmission and reception during the IEEE 802.3 9.6-p.s
Interframe Spacing (IFS) period.
The 82596CA provides a wide range of diagnostics
and network management functions, these include
internal and external loopback, exception condition
tallies, channel activity indicators, optional capture
of all frames regardless of destination address
(promiscuous mode), .optional capture of errored or
collided frames, and time domain reflectometry for
locating fault points on the network cable. The statistical counters, in 32-bit segmented and linear
modes, are 32-bits each and include CRC errors,
alignment errors, overrun errors, resource errors,
short frames, and received collisions. The 82596CA
also features a monitor mode for network analysis.
In this mode the 82596CA can capture status bytes,
and update statistical counters, of frames monitored
on the link without transferring' the contents of the
frames to memory. This can be done concurrently
while transmitting and receiving frames destined for
that station.
The 82596CA can be used in both baseband and
broadband networks. It can be configured for maximum network efficiency (minimum contention overhead) with networks of any length. Its highly flexible
CSMAlCD unit supports address field lengths of
zero through six bytes-configurable to either IEEE
802.3/Ethernet or HDLC frame delimitation. It also
supports 16- or 32-bit cyclic redundancy checks.
The CRC can be transferred directly to memory for
receive operations, or dynamically inserted for transmit operations. The CSMAlCD unit can also be configured for full duplex operation for high throughput
in point-to-point connections.
The 82596CA is fabricated with Intel's reliable, 5-V,
CHMOS IV technology. It is available in a 132-pin
PQFP or PGA package.

1-40

82596CA

(Top View)

290218'-2

Figure 2. 82596CA PQFP Pin Configuration

1-41

intJ

82596CA

01/0

015

013

Vss

01B,

012

Vee

Vss

OP2

BROY

BS16

PCHK

Vee

OPO

PORT

BLAST

HOLD

020

016

014

011

010

ClK

OP3

' OPI

READY·

INT

022

021

017

lOCK

026

024

019

METAL LID

W/R

ADS

AHOlO

BEl

Vee

023

HlOA

BOFF

Vss

Vee

025

Vss

027

02B

(82596CA Pin View)

BREQ

Vss

029

031

030

BE3

RTS

TxD

RxC

CTS

lPBK

RxO

TxC

A30

A2B

A25

A23

A21

AlB

COT

RESET

Vee

A29

Vee

A26

Vee

A12

Al0

A19

CRS

lE/SE

A31

A27

Vss

A24

Vss

A16

A13

All

A22

Vss

A20

A17

A15

290218-3

Figure 3. 82596CA PGA Pinout

1-42

intJ

82596CA

82596CA PGA Cross Reference by Pin Name
Address

Data

Control

Serial
Interface

Vee

Vss

Signal

PinNo.

Signal

PlnNo.

Signal

PinNo.

Signal

Pin No.

A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31

N9
M9
M10
P11
N11
P12
M11
N12
M12
P13
l12
N13
M13
P14
K12
N14
J12
K13
M14
H12
K14
G12
F14
F12
F13
014
E12
013
012
C14

00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
023
024
025
026
027
028
029
030
031

J2
H3
G2
G3
G1
01
C1
F3
02
C2
E3
03
B2
B1
C3
A1
B3
C4
A2
C5
A3
B4
A4
C6
Bp
C7
A5
B8
C8
A9
C9
B9

AOS
AHOlO
BEO
BE1
BE2
BE3
BLAST
BOFF
BROY
BREQ
BS16
CA
ClK
OPO
OP1
OP2
OP3
HlOA
HOlO
INTIINT
lE/BE
lOCK
PCHK
PORT
REAOY
RESET

M5
N5
M7
P5
M8
P9
N2
N6
M1
P4
N1
P3
J3

COT
CRS
CTS
lPBK
RTS
RxC
RxO
TxC
TxO

A13
A14
C11
A12
C10
B11
B12
C12
A11

B6
B7
B10
C13
E2
E13
F2
G13
H2
H13
J13
K2
L13
N7
N8
N10

A6
A7
A8
A10
E1
E14
F1
G14
H1
H14
J1
J14
K1
l14
P6
P7
P8
P10

W/'R

l3
L1
K3
M6
P2
N3
B14
M4
P1
M2
M3
B13
N4

1-43

82596CA

PIN DESCRIPTIONS
Symbol
ClK

00-031

PQFP
Pin No.

Type

14-53

I/O

Name and Function
CLOCK. The system clock input provides the fundamental timing for
the 82596. It is a 1X ClK input used to generate the 82596 clock and
requires TIL levels. All external timing parameters are specified in
reference to the risi,ng edge of ClK.
DATA BUS. The 32 Data Bus lines are bidirectional, tri-state lines that
provide the general purpose data path between the 82596 and
memory. With the 82596 the bus can be either 16 or 32 bits wide; this
is determined by the BS 16 signal. The 82596 always drives all 32 data
lines during Write operations, even with a 16-bit bus. 031- DO are
floated after aReset or when the bus is not acquired.
These lines are inputs during a CPU Port access; in this mode the CPU
writes the next address to the 82596 through the data lines. During
PORT commands (Relocatable SCP, Self-Test, Reset and Dump) the
address must be aligned to a 16-byte boundary. This frees the 03- Do
lines so they can be used to distinguish the commands. The following
is a summary of the decoding data.
DO

D31-D4

Function

0
0
1
1

0
1
0
1

0
0
0
0

0000
AOOR
AOOR
AOOR

Reset
Relocatable SCP
Self·Test
Dump Command

OPO-OP3

4-7

I/O

DATA PARITY. These are tri-stated data parity pins. There is one
parity line for each byte of the data bus. The 82596 drives them with
, even-parity information during write operations having the same timing
as data writes. Likewise, even-parity information, with the same timing
as read information, must be driven back to the 82596 over these pins
to ensure that the correct parity check status is indicated by the
82596.

PCHK

127

PARITY CHECK. This pin is driven high one clock after ROY to inform
Read operations of the parity status of data sampled at the end of the
previous clock cycle. When driven low it indicates that incorrect parity
data has been sampled. It only checks the parity status of enabled
bytes, which are indicated by the Byte Enable and Bus Size Signals.
PCHK is only valid for one clock time after data read is returned to the
82596; I.e., it is inactive (high) at all other times.

7008

ADDRESS LINES. These 30 tri-stated Address lines output the
address bits required for memory operation. These lines are floated
after a Reset or when the bus is not acquired.

BYTE ENABLE. These tri-stated signals are used to indicate which
bytes are involved with the current memory access. The number of
Byte Enable signals asserted indicates the physical size of the data
being transferred (1, 2, 3, or 4 bytes).
• BEO indicates 07-00
• BE1 indicates 015-08
• BE2 indicates 023-016
• BE3indicates 031-024
These lines are floated after a Reset or when the bus is not acquired.

WRITE/READ. This dual function pin is used, to distinguish Write and
Read cycles. This line is floated after a Reset or when the bus is not
acquired.
'

A31-A2

BE3-BEO

109-114
,

W/R

120

1-44

intJ

82596CA

PIN DESCRIPTIONS (Continued)
PQFP
Pin No.

Type

Name and Function

ADS

124

ADDRESS STATUS. The 82596 uses this tri-state pin to indicate to
indicate that a valid bus cycle has begun and that A31-A2, BE3-BEO,
and W/R are being driven. It is asserted during t1 bus states. This line
is floated after a Reset or when the bus is not acquired.

RDY

130

READY. Active low. This signal is the acknowledgment from
addressed memory that the transfer cycle can be completed. When
high, it causes wait states to be inserted. It is ignored at the end of the
first clock of the bus cycle's data cycle. This active-low signal does not
have an internal pull-up resistor. This signal must meet the setup and
hold times to operate correctly.

BURST READY. Active low. Burst Ready, like RDY, indicates that the
external system has presented valid data on the data pins in response
to a Read, or that the external system has accepted the 82596 data in
response to Write request. Also, like RDY, this signal is ignored at
the end of the first clock in a bus cycle. If the 82596 can still receive
data from the previous cycle, ADS will not be asserted in the next
clock cycle; however, Address and Byte Enable will change to reflect
the next data item expected by the 82596. BRDY will be sampled
during each succeeding clock and if active, the data on the pins will be
strobed to the 82596 or to external memory (read/write). BRDY
operates exactly like READY during the last data cycle of a burst
sequence and during nonburstable cycles.

Symbol

BRDY

BLAST

128

BURST LAST. A signal (active low) on this tri-state pin indicates that
the burst cycle is finished and when BRDY is next returned it will be
treated as a normal ready; Le., another set of addresses will be driven
with ADS or the bus will go idle. BLAST is not asserted if the bus is not
acquired.

AHOLD

117

ADDRESS HOLD. This hold signal is active high, it allows another bus
master to access the 82596 address bus. In a system where an 82596
and an i486 processor share the local bus, AHOLD allows the cache
controller to make a cache invalidation cycle while the 82596 holds the
address lines. In response to a signal on this pin, the 82596
immediately (Le. during the next clock) stops driving the entire address
bus (A31-A2); the rest of the bus can remain active. For example,
data can be returned for a previously specified bus cycle during
Address Hold. The 82596 will not begin another bus cycle while
AHOLD is active.

BOFF

116

BACKOFF. This signal is active low, it informs the 82596 that another
bus master requires access to the bus before the 82596 bus cycle
completes. The 82596 immediately (Le. during the next clock) floats its
bus. Any data returned to the 82596 while BOFF is asserted is ignored.
BOFF has higher priority than RDY or BRDY; if two such signals are
returned in the same clock period, BOFF is given preference. The
82596 remains in Hold until BOFF goes high, then the 82596 resumes
its bus cycle by driving out the address and status, and asserting ADS.

LOCK

126

LOCK. This tri-state pin is used to distinguish locked and unlocked bus
cycles. LOCK generates a semaphore handshake to the CPU. LOCK
can be active for several memory cycles, it goes active during the first
locked memory cycle (t1) and goes inactive at the last locked cycle
(t2). This line is floated after a Reset or when the bus is not acquired.
LOCK can be disabled via the sysbus byte in software.

1-45

82596CA

PIN DESCRIPTIONS (Continued)
PQFP
Pin No.

Type

BS16

129

BUS SIZE. This signal allows the 82596CA to work with either 16- or
32-bit bytes. Inserting BS16 low causes the 82596 to perform two 16bit memory accesses when transferring 32-bit data. In little endian
mode the 015-00 lines are driven when 8S16 is inserted, in Big
Endian mode the 031-016 lines are driven.

HOLD

123

HOLD. The HOLD signal is active high, the 82596 uses it to request
local bus mastership. In normal operation HOLD goes inactive before
HLOA. The 82596 can be forced off the bus by deasserting HLOA or if
the bus throttle timers expire.

HLOA

118

HOLD ACKNOWLEDGE. The HLOA signal is active high, it indicates
that bus mastership has been given to the 82596. HLOA is internally
synchronized; after HOLD is detected low, the CPU drives HLOA low.
NOTE
Do not connect HLDA to Vc~t will cause a deadlock. A user wanting
to give the 82596 permanent access to the bus should connect HLDA
to HOLD. If HLOA goes inactive before HOLD, the 82596 will release
the bus (by deasserting HOLD) within a maximum of within a specified
number of bus cycles as specified in the 82596 User's Manual.

BREQ

115

BUS REQUEST. This signal, when configured to an externally
activated mode, is used to trigger the bus throttle timers.

PORT

PORT. When this signal is received, the 82596 latches the data on the
data bus into an internal 32-bit register. When the CPU is asserting this
signal it can write into the 82596 (via the data bus). This pin must be
activated twice during all CPU Port access commands.

RESET

RESET. This active high, internally synchronized signal causes the
82596 to terminate current activity. The signal must be high for at least
five system clock cycles. After five system clock cycles and four TxC
clock cycles the 82596 will execute a Reset when it receives a high
RESET signal. When RESET returns to low the 82596. waits for the
first CA signal and then begins the initialization sequence.

LE/BE

LITTLE ENDIAN/BIG ENDIAN. This dual-function pin is used to
select byte ordering. When LE/BE is high, little end ian byte ordering is
used; when low, big end ian byte ordering is used for data in frames
(bytes) and for control (SCB, RFO, CBL, etc).

119

CHANNEL ATTENTION. The CPU uses this pin to force the 82596 to
begin executing memory resident Command blocks. The CA signal is
internally synchronized. The signal must be high for at least one
system clock. It is latched internally on the high to low edge and then
detected by the 82596.
The first CA after a Reset forces the 82596 into the initialization
sequence beginning at location 00FFFFF6h or an SCP address written
to the 82596 using CPU Port access. All subsequent CA signals cause
the 82596 to begin executing new command sequences from the SCB.

INT/INT

125

INTERRUPT. A high signal on this pin notifies the CPU that the 82596
is requesting an interrupt. This signal is an edge triggered interrupt
signal, and can be configured to be active high or low.

Symbol

Name and Function

1-46

inter

82596CA

PIN DESCRIPTIONS (Continued)
Symbol

PQFP
Pin No.

Type

Name and Function

Vee

18 Pins

POWER. +5V ±10%.

Vss

18 Pins

GROUND.OV.

TxD

TRANSMIT DATA. This pin transmits data to the serial link. It is high
when not transmitting.

TxC

TRANSMIT CLOCK. This signal provides the fundamental timing for
the serial subsystem. The clock is also used to transmit data
synchronously on the TxD pin. For NRZ encoding, data is transferred
to the TxD pin on the high to low clock transition. For Manchester
encoding, the transmitted bit center is aligned with the low to high
transition. Transmit clock must always be running for proper device
operation.

LPBK

LOOPBACK. This TTL-level control signal enables the loopback
mode. In this mode serial data on the TxD input is routed through the
82C501 internal circuits and back to the RxD output without driving the
transceiver cable. To enable this signal, both internal and external
loopback need to be set with the Configure command.

RxD

RECEIVE DATA. This pin receives NRZ serial data only. It must be
high when not receiving.

RxC

RECEIVE CLOCK. This signal provides timing information to the
internal shifting logic. For NRZ data the state of the RxD pin is
sampled on the high to low transition of the clock.

RTS

REQUEST TO SEND. When this signal is low the 82596 informs the
external interface that it has data to transmit. It is forced high after a
Reset or when transmission is stopped.

CTS

CLEAR TO SEND. An active-low signal that enables the 82596 to
send data. It is normally used as an interface handshake to RTS.
Asserting CTS high stops transmission. CTS is internally synchronized.
If CTS goes inactive ,meeting the setup time to the TxC negative edge,
the transmission will stop and RTS will go inactive within, at most, two
TxC cycles.

CRS

CARRIER SENSE. This signal is active low, it is used to notify the
82596 that traffic is on the serial link. It is only used if the 82596 is
configured for external Carrier Sense. In this configuration external
circuitry is required for detecting traffic on the serial link. CRS is
internally synchronized. To be accepted, the signal must remain active
for at least two serial clock cycles (for CRSF = 0).

COT

COLLISION DETECT. This active-low signal informs the 82596 that a
collision has occurred. It is only used if the 82596 is configured for
external Collision Detect. External circuitry is required for collision
detection. COT is internally synchronized. To be accepted, the signal
must remain active for at least two serial clock cycles (for CDTF = 0).

1-47

82596CA

82596 AND HOST CPU INTERACTION

82596 BUS INTERFACE

The 82596CA and the host CPU communicate
through shared memory. Because of its on-chip
DMA capability, the 82596 can make data block
transfers (buffers and frames) independently of the
CPU; this greatly reduces the CPU byte transfer
overhead.

The 82596CA has bus interface timings and pin definitions that are compatible with Intel's 32-bit i486
microprocessor. This eliminates the need for additional bus interface logic. Operating at 33 MHz, the
82596's bus bandwidth can be as high as 106 MB/s.
Since Ethernet only requires 1.25 MB/s, this leaves
a considerable amount of bandwidth for the CPU.
The 82596 also has a bus throttle to regulate its use
of the bus. Two timers can be programmed through
the SCB: one controls the maximum time the 82596
can remain on the bus, the other controls the time
the 82596 must stay off the bus (see Figure 5). The
bus throttle can be programmed to trigger internally
with HLDA or externally with BREQ. These timers
can restrict the 82596 HOLD activation time and improve bus utilization.

The 82596 is a multitasking coprocessor that comprises two independent logical units-the Command
Unit (CU) and the Receive Unit (RU). The CU executes commands from shared memory. The RU handles all activities related to frame reception. The in-'
dependence of the CU and RU enables the 82596 to
engage in both activities simultaneously-the CU
can fetch and execute commands from memory
while the RU is storing received frames in memory.
The CPU is only involved with this process after the
CU has executed a sequence of commands or the
RU has finished storing a sequence of frames.
The CPU and the 82596 use the hardware signals
Interrupt (INT) and Channel Attention (CA) to initiate
communication with the System Control Block
(SCB), see Figure 4. The 82596 uses INT to alert the
CPU of a change in the contents of the SCB, the
CPU uses CA to alert the 82596.
The 82596 has a CPU Port Access state that allows
the CPU to execute certain functions without accessing memory. The 82596 PORT pin and data bus
pins are used to enable this feature. The CPU can
directly activate four operations when the 82596 is in
this state.
• Write an alternative System Configuration Pointer
(SCP). This can be used when the 82596 cannot
use the default SCP address space.
• Write a different Dump Command Pointer and execute Dump. This can be used for troubleshooting No Response problems.
• The CPU can reset the 82596 via software without disturbing the rest of the system .
• A self-test can be used for board testing; the
82596 will execute a self-test and write the results to memory.

82596 MEMORY ADDRESSING
The 82596 has a 32-bit memory address range,
which allows addressing up to four gigabytes of
memory. The 82596 has three memory addressing
modes (see Table 1).
• 82586 Mode. The 82596 has a 24-bit memory
address range. The System Control Block, Command List, Receive Descriptor List, and Buffer
Descriptors must reside in one 64-KB memory
segment. Transmit and Receive buffers can reside in a 24-bit address space.
• 32-Bit Segmented Mode. The 82596 has a 32bit memory address range. The System Control
Block, Command List, Receive Descriptor List,
and Buffer Descriptors must reside in one 64-KB
memory segment. Transmit and Receive buffers
can reside in a 32-bit address space.
• Linear Mode. The 82596 has a 32-bit memory
address range. Any memory structure can reside
anywhere within the 32-bit memory address
range.

1-48

infef

82596CA

CHANNEL AlTENTION

CPU

INT

I 82596

INTERRUPT

'" r-

SHARED MEMORY
INITIALIZATION
ROOT

SYSTEM CONTROL
BLOCK (SCB).
"MAILBOX"

-----...tv

RECEIVE
FRAME
AREA

COMMAND
LIST

290218-4

Figure 4. 82596 and Host CPU Intervention

82596 Bus Use
without Bus
Throttle TImers

82596 Bus Use
with Bus Throttle

·1

T-ON

IT-OFF

rr:c>Nl

Timers

tl =t2+ t3

290218-5

Figure 5. Bus Throttle Timers
Table 1. 82596 Memory Addressing Formats
Operation Mode
Pointer or Offset

32-Bit
Segmented

82586

ISCP Address

24-Bit Linear

SCBAddress

Base (24)

Command Block Pointers

Base (24)

Rx Frame Descriptors

Base (24)

32-Bit Linear

+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)

Base (32)
Base (32)
Base (32)

32-Bit Linear
32-Bit Linear
32-Bit Linear
32-Bit Linear

Tx Frame Descriptors

Base (24)

Rx Buffer Descriptors

Base (24)

Tx Buffer Descriptors

Base (24)

Rx Buffers

24-Bit Linear

32-Bit Linear

Tx Buffers

24-Bit Linear

32-Bit Linear

1-49

Base (32)

+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)
+ Offset (16)

Linear

Base (32)
Base (32)

32-Bit Linear
32-Bit Linear
32-Bit Linear

inter

82596CA

INITIALIZATION ROOT

SYSTEM CONTROL

BLOCK (SCB)
COMMAND LIST (Cl)

r-----.-------------------------------.

STATUS
COMMAND

CO~~~:T~r!"IST

1--_-..;...-+1

RECEIVE rRAME
POINTER

' -_ _ _-' (N)

STATISTICS

BUS
THROTTLE

TRANSMIT
BurrER
DESCRIPTOR
(TBD)

I
I
I
I

._--------_.

T
RECEIVE rRAME AREA (RrA)

1...._ _ _.... (N)

El" 1
RECEIVE
BurrER
DESCRIPTOR
(RBD)

RECEIVE
BurrER
DESCRIPTOR
(RBD)

....._..,..._..... (N)

T......_ ......T T......
~ _ ......T T

T
290218-6

Figure 6. 82596 Shared Memory Structure

82596 SYSTEM MEMORY STRUCTURE
The Shared Memory structure consists of four parts:
the Initialization Root, the System Control Block, the
Command List, and the Receive Frame Area (see
Figure 6).
The Initialization Root is in an established location
known to the host CPU and the 82596 (00FFFFF6h).
However, the CPU can establish the Initialization
Root in another location by using the CPU Port access. This root is accessed during initialization, and
points to the System Control Block.

The System Control Block serves as a bidirectional
mail drop for the host CPU and the 82596 CU and
RU. It is the central point through which the CPU and
the 82596 exchange control and status information.
The SCB has two areas. The first contains· instructions from the CPU to the 82596. These include:
control of the CU and RU (Start, Abort, Suspend,
and Resume), a pointer to the list of CU commands,
a pointer to the Receive Frame Area, a set of Interrupt Acknowledge bits, and the T-ON and T-OFF
timers for the bus throttle. The second area contains
status information the 82596 is sending to the CPU.
Such as, the CU and RU states (Idle, Active

1-50

82596CA

Ready, Suspended, No Receive Resources, etc.), interrupt bits (Command Completed, Frame Received,
CU Not Ready, and RU Not Ready), and statistical
counters.

ing this frame the 82596 sets the next Free Frame
Descriptor RBD pointer to the next Free RBD. Figure
7C shows the RFA after receiving a second frame.
In this example the second frame occupies only one
Receive Buffer and one RFD. The 82596 again sets
the RBD pointer. This process is repeated again in
Figure 7D,showing the reception of another frame
using one Receive Buffer; in this example there is an
extra Frame Descriptor.

The Command List functions as a program for the
CU; individual commands are placed in memory
units called Command Blocks (CBs). These CBs
contain the parameters and status of specific highlevel commands called Action Commands; e.g.,
Transmit or Configure.

TRANSMIT AND RECEIVE MEMORY
STRUCTURES

Transmit causes the 82596 to transmit a frame. The
Transmit CB contains the destination address, the
length field, and a pointer to a list of linked buffers
holding the frame that is to be constructed from several buffers scattered throughout memory. The
Command Unit operates without CPU intervention;
the DMA for each buffer, and the prefetching of references to new buffers, is performed in parallel. The
CPU is notified only after a transmission is complete.

There are three memory structures for reception and
transmission. The 82586 memory structure, the
Flexible memory structure, and the Simplified memory structure. The 82586 mode is selected by configuring the 82596 during initialization. In this mode all
the 82596 memory structures are compatible with
the 82586 memory structures.

The Receive Frame Area is a list of Free Frame Descriptors (descriptors not yet used) and a list of userprepared buffers. Frames arrive at the 82596 unsolicited; the 82596 must always be ready to receive
.and store them in the Free Frame Area. The Receive Unit fills the buffers when it receives frames,
and reformats the Free Buffer List into receivedframe structures. The frame structure is, for all practical purposes, identical to the format of the frame to
be transmitted. The first Frame descriptor is referenced by the SCB. Unless the 82596 is configured
to Save Bad Frames, the frame descriptor, and the
associated buffer descriptor, which is wasted when
a bad frame is received, are automatically reclaimed
and returned to the Free Buffer List.

When the 82596 is not configured to the 82586
mode, the other two memory structures, Simplified
and Flexible, are available for transmitting and receiving. These structures can be selected on a
frame-by-frame basis by setting the S/F bit in the
Transmit Command and the Receive Frame Descriptor (see Figures 29, 30, 41, and 42). The Simplified memory structure offers a simple structure for
ease of programming (see Figure 8). All information
about a frame is contained in one structure; for example, during reception the RFD and data field are
contained in one structure.
The Flexible memory structure (see Figure 9) has a
control field that allows the programmer to specify
the amount of receive data the RFD will contain for
receive operations and the amount of transmit data
the Transmit Command Block will contain for transmit operations. For example, when the control field
in the RFD is set to 20 bytes during a reception, the
first 20 bytes of the data field are stored in the RFD
(6 bytes of destination address, 6 bytes of source
address, 2 bytes of length field, and 6 bytes of data)
and the remainder of the data field is stored in the
Receive Data Buffers. This is useful for capturing
frame headers when header information is contained in the data field. The header information can
then be automatically stored in the RFD partitioned
from the Receive Data Buffer.

Receive buffer chaining (storing incoming frames in
a linked buffer list) significantly improves memory
utilization. Without buffer chaining, the user must allocate consecutive blocks of memory, each capable
of containing a maximum frame (for Ethernet, 1518
bytes). Since an average frame is about 200 bytes,
this is very inefficient. With buffer chaining, the user
can allocate small buffers and the 82596 will only
use those that are needed.
Figure 7 A-D illustrates how the 82596 uses the
Receive Frame Area. Figure 7A shows an unused
Receive Frame Area composed of Free Frame Descriptors and Free Receive Buffers prepared by the
user. The SCB points to the first Frame Descriptor of
the Frame Descriptor List. Figure 7B shows the
same Receive Frame Area after receiving one
frame. This first frame occupies two Receive Buffers
and one Frame Descriptor-a valid received frame
will only occupy one Frame Descriptor. After receiv-

The control field can also be used for the Transmit
Command when the Flexible memory structure is
used. The quantity of data field bytes to be transmitted from the Transmit Command Block is specified
by the variable control field.

1-51

82596CA

}

"'..,
..,.,
o·
01 •

·.·.··.~~A.~·t.·.·.l • .•·• ·•·

290218-7

Figure 7. Frame Reception in the RFA

1-52

inter

82596CA

SCB
STATUS

TO COMMAND LIST

4
FDl

FD2

STATUS

I
BUS
THROTILE II

._-----_.
VARIABLE
DATA
FIELD

FD3

FD4

STATUS

EMPTY

- -lJ -f:

STATUS

STATISTICS
I
I
I

•

RECEIVE FRAME AREA

FD
POINTER

EMPTY

RECEIVE
FRAME
DESCRIPTORS

:+--

RECEIVE FRAME LIST - -.......
:4
....- - - - - - - FREE FRAME LIST - - - - - - - -........,

290218-8

Figure 8. Simplified Memory Structure
SCB

TO COMMAND LIST

••

STATUS

POINTER

FD2
STATUS

STATUS

EMPTY

RBD3

RBD4

RBDS

CONTROL
FIELD

.------_.

VARIABLE
DATA
FIELD

RECEIVE
FRAME
DESCRIPTORS

RBDl

RECEIVE
BUFFER
DESCRIPTORS

RECEIVE
BUFFERS

----f

I
BUS
THROTILE II

FD3

FDl
STATUS

STATISTICS
I
I
I

RECEIVE FRAME AREA

RBD2

FD4

-r -..t:

-f -Uf -Lr -r -r:

--L

DATA
FIELD

EMPTY

"--

BUFFER 2

BUFFER 3

BUFFER 4

BUFFER 5

BUFFER 1

:+-- RECEIVE FRAME LIST

_:4

T
~'

~',

FREE FRAME LIST

290218-9

Figure 9. Flexible Memory Structure

1-53

82596CA

TRANSMITTING FRAMES
The 82596 executes high-level Action Commands
from the Command List in. system memory. Action
Commands are fetched and executed in parallel with
the host CPU operation, thereby significantly improving system performance. The format of the Action
Commands is shown in Figure 10. Figure 28 shows
the 82586 mode,and Figures 29 and 30 show the
command formats of the Linear and 32-bit Segmented modes.
A single Transmit command contains, as part of the
command-specific parameters, the destination address and length field of the transmitted frame and a
pointer to buffer area in memory containing the data
portion of the frame. The data field is contained in a
memory data structure consisting of a buffer descriptor (BO) and a data buffer-or a linked list of
buffer descriptors and buffers-as shown in Figure
11.

cated by the lack of a signal after the last bit of the
frame check sequence field has been transmitted. In
EOC mode the 82596 can be configured to extend
short frames by adding pad bytes (7Eh) during transmission, according to the length field. In HOLC mode
the 82596 will generate the 01111110 flag for the
start and end frame delimiters, and do standard bit
stuffirig and stripping. Furthermore, the 82596 can
be configured to pad frames shorter than the specified minimum frame length by appending the appropriate number of flags to the end of the frame.
When a collision occurs, the 82596 manages the
jam, random wait, and retry processes, reinitializing
OMA pointers without CPU intervention. Multiple
frames can be sent by linking the appropriate number of Transmit commands together. This is particularly useful when transmitting a message larger than
the maximum frame size (1518 bytes for Ethernet).

Multiple data buffers can .be chained together using
the BOs. Thus, a frame with a long data field can be
transmitted using several (shorter) data buffers
chained together. This chaining technique allows the
system designer to develop efficient buffer management.

CONTROL
rlELDS

I
I

(POINTER

~~~~TL~OMMAND) •

COMMAND STATUS
COMMAND

PARAMETER rlELD
(COMMAND-SPEClriC
PARAMETERS)

NEXT
COMMAND

290218-10

The 82596 automatically generates the preamble
(alternating 1s and Os) and start frame delimiter,
fetches the destination address and length field from
the Transmit command, inserts its unique address
as the source address, fetches the data field specified by the Transmit command, and computes and
appends the CRC to the end of the frame (see Figure 12). In the Linear and 32-bit Segmented mode
the CRC can be optionally inserted on a frame-byframe basis by setting the NC bit in the Transmit
Command Block (see Figures 29 and 30).

Figure 10. Action Command Format

TRANSMITBD
ACTUAL COUNT
LINK FIELD

START
FRAME
DELIMITER

DESTINATION
ADDRESS

DB ADDRESS.
~
(24 BITS)

The 82596 can be configured to generate two types
of start and end frame delimiters-End of Carrier
(EOC) or HOLC. In EOC mode the start frame delimiter is 10101011 and the end frame delimiter is indi-

PREAMBLE

•

NEXT BUFFER DES CRIPTOR

DATA
BUFFER
(DB)
290218-11

Figure 11. Data Buffer Descriptor and
Data Buffer Structure
LENGTH
FIELD

SOURCE
ADDRESS

Figure 12. Frame Format

1-54

DATA
FIELD

FRAME
CHECK
SEQUENCE

END
FRAME
DELIMITER

inter

82596CA

RECEIVING FRAMES

frame. The 82596 will continue to receive frames
without CPU help as long as Receive Frame Descriptors and Data Buffers are available.

To reduce CPU overhead, the 82596 is designed to
receive frames without CPU supervision. The host
CPU first sets aside an adequate receive buffer
space and then enables the 82596 Receive Unit.
Once enabled, the RU watches for arriving frames
and automatically stores them in the Receive Frame
Area (RFA). The RFA contains Receive Frame Descriptors, Receive Buffer Descriptors, and Data Buffers (see Figure 13). The individual Receive Frame
Descriptors make up a Receive Descriptor List
(RDL) used by the 82596 to store the destination
and source addresses, the length field, and the
status of each frame received (see Figure 14).

82596 NETWORK MANAGEMENT
AND DIAGNOSTICS
The behavior of data communication networks is
normally very complex because of their distributed
and asynchronous nature. It is particularly difficult to
pinpoint a failure when it occurs. The 82596 has extensive diagnostic and network management functions that help improve reliability and testability. The
82596 reports on the following events after each
frame is transmitted.

Once enabled, the 82596 checks each passing
frame for an address match. The 82596 will recognize its own unique address, one or more multicast
addresses, or the broadcast address. If a match is
found the 82596 stores the destination and source
addresses and the length field in the next available
RFD. It then begins filling the next available Data
Buffer on the FBL, which is pointed to by the current
RFD, with the data portion of the incoming frame. As
one Data Buffer is filled, the 82596 automatically
fetches the next DB on the FBL until the entire frame
is received. This buffer chaining technique is particularly memory efficient because it allows the system
designer to set aside buffers to fit frames much
shorter than the maximum allowable frame length. If
AL-LOC = 1, or if the flexible memory structure is
used, the addresses and length field can be placed
in the Receive Buffer.

•
•
•
•

Transmission successful.
Transmission unsuccessful. Lost Carrier Sense.
Transmission unsuccessful. Lost Clear to Send.
Transmission unsuccessful. A DMA underrun occurred because the system bus did not keep up
with the transmission.
• Transmission unsuccessful. The number of collisions exceeded the maximum allowed.
• Number of Collisions. The number of collisions
experienced during the frame.
• Heartbeat Indicator. This indicates the presence
of a heartbeat during the last Interframe Spacing
(IFS) after transmission.
When configured to Save Bad Frames the 82596
checks each incoming frame and reports the following errors.

Once the entire frame is received without error, the
82596 does the following housekeeping tasks.

• CRC error. Incorrect CRC in a properly aligned
frame.

• The actual count field of the last Buffer Descriptor used to hold the frame just received is updated with the number of bytes stored in the associated Data Buffer.

• Alignment error. Incorrect CRC in a misaligned
frame.
• Frame too short. The frame is shorter than the
value configured for minimum frame length.
• Overrun. Part of the frame was not placed in
memory because the system bus did not keep up
with incoming data.

• Out of buffer. Part of the frame was discarded
because of insufficient memory storage space.
• Receive collision. A collision was detected during
reception .
• Length error. A frame not matching the frame
length parameter was detected.

If a frame error occurs, for example a CRC error, the
82596 automatically reinitializes its DMA pointers
and reclaims any data buffers containing the bad

1-55

inter

82596CA

RECEIVER FRAME AREA (RFA)

FREE BUFFER LIST (FBL)
RECEIVE
BUFFER
DESCRIPTOR(RBD)

RBD

DATA
BUFFER (DB)

290218-12

Figure 13. Receive Frame Area Diagram

RECEIVE FRAME STATUS
L.INK FIELD
BUFFER DESCRIPTOR
LINK FIELD

.. f-+
..
~

NEXT RECEIVE
FRAME DESCRIPTOR
BUFFER DESCRIPTOR

DESTINATION ADDRESS
SOURCE ADDRESS
LENGTH FIELD
290218-13

Figure 14. Receive Frame Descriptor

1-56

82596CA

NETWORK PLANNING AND
MAINTENANCE
To properly plan, operate, and maintain a communication network, the' network management entity
must accumulate information on network behavior.
The 82596 provides a rich· set of network-wide diagnostics that can serve as the basis for a network
management entity.

The 82596 will receive all frames and put them in the
RFD. Frames that exceed the available space in the
RFD will be truncated, the status will be updated,
and the 82596 will retrieve the next RFD. This allows
the user to capture the initial data bytes of each
frame (for instance, the header) and discard the remainder of the frame.
The 82596 also has a monitor mode for network
analysis. During normal operation the receive function enables the 82596 to receive frames that pass
address filtering. These frames must have the Start
of Frame Delimiter (SFD) field and must be longer
than the absolute minimum frame length of 5 bytes
(6 bytes in case of Multicast address filtering). Contents and status of the received. frames are transferred to memory. The monitor function enables the
82596 to simply evaluate the incoming frames. The
82596 can monitor the frames that pass or do not
pass the address filtering. It can also monitor frames
which do not have the SFD fields. The 82596 can be
configured to only keep statistical information about
monitor frames. Three options are available in the
Monitor mode. These options are selected by the
two monitor mode configuration bits available in the
configuration command.

Information on network activity is provided in the
status of each frame transmitted. The 82596 reports
the following activity indicators after each frame.
• Number of collisions. The number of collisions
the 82596 experienced while attempting to transmit the frame.
• Deferred transmission. During the first transmission attempt the 82596 had to defer to traffic on
the link.
The 82596 updates its 32-bit statistical counters after each received frame that both passes address
filtering and is longer than the Minimum Frame
Length configuration parameter. The 82596 reports
the following statistics.
• CRC errors. The number of well-aligned frames
that experienced a CRC error.
• Alignment errors. The number of misaligned
frames that experienced a CRC error.

When the first option is selected, the 82596 receives
good frames that pass address filtering and transfers them to memory while monitoring frames that
do not pass address filtering or are shorter than the
minimum frame size (these frames are not transferred to memory). When this option is used the
82596 updates six counters: CRC errors, alignment
errors, no resource errors, overrun errors, short
frames and total good frames received.

• No resources. The number of frames that were
discarded because of insufficient resources for
reception.
• Overrun errors. The number of frames that were
not completely stored in memory because the
system bus did not keep up with incoming data.

• Receive Collision counter. The number of collisions detected during receive.
• Short Frame counter. The number of frames that
were discarded because they were shorter than
the configured minimum frame length.
The 82596 can be configured to Promiscuous mode.
In this mode it captures all frames transmitted on the
network without checking the Destination Address.
This is useful when implementing a monitoring station to capture all frames for analysis.

When the third option is selected, the receive function is completely disabled. The 82596 monitors all
frames, including frames that do not have a Start
Frame Delimiter. When this option is used the 82596
updates six counters: CRC errors, alignment errors,
total frames (good and bad), short frames, collisions'
detected and total good frames.

A useful method of capturing frame headers is to
use the Simplified memory mode, configure the
82596 to Save Bad Frames, and configure the
82596 to Promiscuous mode with space in the RFD
allocated for specific number of receive data bytes.

1-57

lme

82596CA

STATION DIAGNOSTICS
AND SELF-TEST
The 82596 provides a large set of diagnostic and
network management functions. These include inter'nal and external loopback and time domain reflectometry for locating fault points in the network cable.
The 82596 ensures software reliability by dumping
the contents of the 82596 internal registers into system memory. The 82596 has' a self-test mode that
enables it to run an internal self-test and place the
results in system memory.

82586 SOFTWARE COMPATIBILITY
The 82596 has a software-compatible state in which
all its memory structures are compatible with the
82586 memory structure. This includes all the Action
Commands, the Receive Frame Area (including the
RFD, Buffer Descriptors, and Data Buffers), the System Control Block, anc,l the initialization procedures.
There are two minor differences between the 82596
in the 82586-Compatible memory structure and the
82586.
• When the internal and external loopback bits in
the Configure command are set to 11 the 82596
is in external loopback and the LPBK pin is activated; in the 82586 this situation would. produce
internal loopback.
• During a Dump command both the 82596 and .
82586 dump the same number of bytes; however,
the data format is different.

INITIALIZING THE 82596
A Reset command is issued to the 82596 to prepare
it for normal operation. The 82596 is initialized
through two data structures that are addressed by
two pOinters, .the System Configuration. Pointer.
(SCP) and. the Intermediate System Configuration
Pointer (ISCP). The initialization procedure begins
when a Channel Attention signal is asserted after
RESET. The 82596 uses the address of the double
word that contains the SCP as a default00FFFFF4h. Before the CA signal is asserted this
default address can be changed to any other available address by asserting the PORT pin and providing the desired address over the 031-04 pins of the
address bus. Pins 03-00 must be 0010; i.e., any
alternative address must be aligned to 16-byte
boundaries. All addresses sent to the 82596 must be
word aligned, which means that all pointers and
memory structures must start on an even address,
(Ao=zero).

SYSTEM CONFIGURATION POINTER
(SCP)
The SCP contains the sysbus byte and the location
of the next structure of the initialization process, the
ISCP. The following parameters are selected in the
SYSBUS.
• The 82596 operation mode.
• The Bus Throttle timer triggering method.
• Lock enabled.
• Interrupt polarity.
Byte ordering is determined by the LEIBE pin.
LE/BE= 1 selects Little Endian byte ordering and
LEIBE = 0 selects Big Endian byte ordering.

NOTE:
In the following, X indicates a bit not checked
82586 mode. This bit must be set toO in all other
modes.

intJ

82596CA

The following diagram illustrates the format of the sCPo
31

ODD WORD

16 15

X X X X X X X X

EVEN WORD

10 0 0 0 0 0 0 010 0 0 0 0 0 0

SYSBUS

OFFFFF4h

X X X X X X X X X X X X X X X XJXX X X X X X XiX X X X X X X X OFFFFF8h
A31 ................ A24 A23

ISCP ADDRESS

AO OFFFFFCh

A31 ................ A24 are not checked in 82586 mode
X .................... X areas are not checked in 82586 mode; they must be 0 in all other modes.
23
SYSBUS

I I
0

1 liNT

I I I I I I
LOCK

1.11

TRG

1.10

L"o,~="

o0
o1

:
:
1 0 :
1 1:

82586 mode
32-Bit Segmented mode
Linear mode
Reserved

o : internal triggering

Interrupt polarity
o - Interrupt pin is active
high
1 - Interrupt pin is active
low

of the
Bus Throttle timers
1 : external triggering of the
Bus Throttle timers

o : Lock function enabled
1 : Lock function disabled

290218-14

ISCP ADDRESS- The physical address of the ISCP. In the 82586 mode, bits A31-A24 are considered
to be zero.

Figure 15. The System Configuration Pointer

Writing the Sysbus
When writing the sysbus byte it is important to pay attention to the byte order.
• When a Little Endian processor is used, the sysbus byte is located at byte address OOFFFFF6h (or address
n+ 2 if an alternative SCP address n was programmed).
• When a processor using Big Endian byte ordering is used, the sysbus, alternative SCP, and ISCP addresses
will be different.
• The sysbus byte is located at OOFFFFF5h.

• If an alternative SCP address is programmed, the sysbus byte should be at byte address

1-59

n+ 1.

inter

82596CA

INTERMEDIATE SYSTEM CONFIGURATION POINTER (ISCP)
The ISCP indicates the location of the System Control Block. Often the SCP is in ROM and the ISCP is in RAM.
The CPU loads the SCB address (or an equivalent data structure) into the ISCP and asserts CA. This Channel
Attention signal causes the 82596 to begin its initialization procedure and to get the SCB address from the
ISCP and SCPo In 82586 and 32-bit Segmented modes the SCP base address is also the base address of all
Command Blocks, Frame Descriptors, and Buffer Descriptors (but not buffers). All these data structures must
reside in one 64-KB segment; however, in Linear mode no such limitation is imposed.
The following diagram illustrates the ISCP format.

ODD WORD

EVEN WORD
16 15
87
0
~A~1~5________~S~C~B~OrF~FS~E~T__________~A~O~______________~____~BU~S~Y~____~ISCP
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ A23
_________________
___
_ _ _ADDRESS
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _AO
_
SCB
BASE
ISCP + 4
31

o 0 0 0 0 0 0 0 A31 ................ A24 BUSY

in 82586 mode
in all other modes

Indicates that the 82596 is being initialized. The CPU sets the ISCP to 01 h before it gives
the first CA to the 82596. The ISCP is cleared by the 82596 after the SCB base and offset
are read. Note that the most significant byte of the first word of the ISCP is not modified
when BUSY is cleared.

SCB OFFSET-This 16-bit quantity specifies the offset portion of the address of the SCB.
SCB BASE

Specifies the base portion of the address of the SCB. The base of SCB is also the base of
all .82596 Command Blocks, Frame Descriptors and Buffer Descriptors. In the 82586
mode, bits A31-A24 are considered to be zero.

Figure 16. The Intermediate System Configuration Pointer-82586 and 32-Bit Segmented Modes

EVEN WORD
87

ODD WORD
31

16 15

~O~O~O~.~.~
..~.~
..~.~
..~.~
..~.~
..~.~
.. ~.~
.. ~.~
.. ~..~.~.~
.. ~..~.~..~.~..~.~..~.~..~.~..~.~
..~.~
..~O~O~O~____~BU~S~Y~__~ISCP
LA~3_1

______________________S_C~B_A_BS_O_L_U_T_E_A_D_D_R_E_SS_______________________A~O ISCP+4

BUSY

Indicates that the 82596 is being initialized. The ISCP is set to 01 h by the CPU before its
first CA to the 82596. It is cleared by the 82596 after the SCB address is read.

SCB ADDRESS- This 32-bit quantity specifies the physical address of the SCB .
. Figure 17. The Intermediate System Configuration POinter-Linear Mode.

INITIALIZATION PROCESS
The CPU sets up the SCP, ISCP, and the SCB structures, and, if desired, an alternative SCP address. It also
sets BUSY to 01 h. The 82596 is initialized when a Channel Attention signal follows a Reset signal, causing the
82596 to access the System Configuration Pointer. The sysbus byte, the operational mode, the bus throttle
timer triggering method, the interrupt polarity, and the state of LOCK are read. After reset the Bus Throttle
timers are essentially disabled-the T-ON value is infinite, the T-OFF value is zero. After the SCP is read, the
82596 reads the ISCP and saves the SCB address. In 82586 and 32-bit Segmented modes this address is
represented as a base address plus the offset (this base address is also the base address of all the control
blocks). In Linear mode the base address is also an absolute address. The 82596 clears BUSY, sets CX and
CNR to equal 1 in the SCB. clears the SCB command word, sends an interrupt to the CPU, and awaits another
Channel Attention signal. RESET configures the 82596 to its default state before CA is asserted.

1-60

inter

82596CA

CONTROLLING THE 82596CA
The host CPU controls the 82596 with the commands, data structures, and methods described in this section.
The CPU and the 82596 communicate through shared memory structures. The 82596 contains two independent units: the Command Unit and the Receive Unit. The Command Unit executes commands from the CPU,
and the Receive Unit handles frame reception. These two units are controlled and monitored by the CPU
through a shared memory structure called the System Control Block (SCB). The CPU and the 82596 use the
CA and INT signals to communicate with the SCB.

82596 CPU ACCESS INTERFACE (PORT)
The 82596 has a CPU access interface that allows the host CPU to do four things.
• Write an alternative System Configuration Pointer address.
• Write an alternative Dump area pointer and perform Dump.
• Execute a software reset.
• Execute a self-test.
The following events initiate the CPU access state.
• Presence of an address on the 031-04 data bus pins.
• The 03-00 pins are used to select one of the four functions.
• The PORT input pin is asserted, as in a regular write cycle.
NOTE.
The SCP Dump and Self-Test addresses must be 16-byte aligned.

The 82596 requires two 16-bit write cycles for a port command. The first write holds the internal machines and
reads the first 16 bits; the second activates the PORT command and reads the second 16 bits.
The PORT Reset is useful when only the 82596 needs to be reset. The CPU must wait for 1a-system and 5-serial clocks before issuing another CA to the 82596; this new CA begins a new initialization process.
The Dump function is useful for troubleshooting No Response problems. If the chip is in a No Response state,
the PORT Dump operation can be executed and a PORT Reset can be used to reinitialize the 82596 without
disturbing the rest of the system.
The Self-Test function can be used for board testing; the 82596 will execute a self-test and write the results to
memory.
Table 2. PORT Function Selection

031 .................................. 04 ............................. 00

Reset

A31

Don't Care

Self-Test

A31

Self-Test Results Address

SCP

A31

Alternative SCP Address

Dump

A31

Dump Area Pointer

Function

Addresses and Results

1-61

Intel

82596CA

• A Segmented address uses a 32-bit base and a 16-bit offset.
NOTE
In the previous two memory addressing modes, each command header (CB, TBD, RFD, RBD, and SCB)
must wholly reside within one segment. If the 82596 encounters a melTlory structure.that does not follow this
restriction, the 82596 will fetch the next contiguous location in memory (beyond the segment).

• Linear Mode
• A Linear address is a single 32-bit entity.
• There are no Segmented addresses.
Linear addresses are primarily used to address transmit and receive data buffers. In the 82586 and 32-bit
Segmented modes, segmented addresses (base plus offset) are used for all Command Blocks, Buffer Descriptors, Frame Descriptors, and System Control Blocks. When using Segmented ad.dresses, only the offset
portion of the entity being addressed is specified in the block. The base for all offsets is the same-that of the
SCB. See Table 1.

LITTLE ENDIAN AND BIG ENDIAN BYTE ORDERING
The 82596 supports both Little Endian and Big Endian byte ordering for its memory structures.
The 82596 supports Big Endian byte ordering for word and byte entities. Dword entities are not supported with
Big Endian byte ordering. This results in slightly different 82596 memory structures for Big Endian operation.
These structures are defined in the 82596 User's Manual.
NOTE
All 82596 memory entities must be word or dword aligned.

An example of a dword entity is a frame descriptor command/status dword, whereas the raw data of the frame
are byte entities..Both 32- and 16-bit buses are supported. When a 16-bit bus is used with Big Endian memory
organization, data lines D15-DO are used. The 82596 has an internal crossover that handles these swap
operations.
.

COMMAND UNIT (CU)
The Command Unit is the logical unit that executes Action Commands from a list of commands very similar to
a CPU program. A Command Block is associated with each Action Command. The CU is modeled as a logical
machine that takes, at any given time, one of the following states.
• Idle. The CU is not executing a command and is not associated with a CB on the list. This is the initial state.
• Suspended. The CU is not executing a command; however, it is associated with a CB on the list.

• Active. The CU is executing an Action Command and pointing to its CB.
The CPU can affect CU operation in two ways: by i.ssuing a CU Control Command or by setting bits in the
Command word of the Action Command.

1-62

intJ

82596CA

RECEIVE UNIT (RU)
The Receive Unit is the logical unit that receives frames and stores them in memory. The RU is modeled as a
logical machine that takes, at any given time, one of the following states.
• Idle. The RU has no memory resources and is discarding incoming frames. This is the initial state.
• No Resources. The RU has no memory resources and is discarding incoming frames. This state differs
from Idle in that the RU accumulates statistics on the number of discarded frames.
• Suspended. The RU has memory available for storing frames, but is discarding them. The suspend state
can only be reached if the CPU forces this through the SCB or sets the suspend bit in the RFD.
• Ready. The RU has memory available and is storing incoming frames.

The CPU can affect RU operation in three ways: by issuing an RU Control Command, by setting bits in the
Frame Descriptor Command word of the frame being received, or by setting the EL bit of the current buffer's
Buffer Descriptor.

SYSTEM CONTROL BLOCK (SCB)
The SCB is a memory block that plays a major role in communications between the CPU and the 82596. Such
communications include the following.
• Commands issued by the CPU·
• Status reported by the 82596
Control commands are sent to the 82596 by writing them into the SCB and then asserting CA.· The 82596
examines the command, performs the required action, and then clears the SCB command word. Control
commands perform the following types of tasks.
• Operation of the Command Unit (CU). The SCB controls the CU by specifying the address of the Command
Block List (CBL) and by starting, suspending, resuming, or aborting execution of CBL commands.
• Operation of the Bus Throttle. The SCB controls the Bus Throttle timers by providing them with new values
and sending the Load and Start timer commands. The timers can be operated in both the 32-bit Segmented
and Linear modes.
• Reception of frames by the Receive Unit (RU). The SCB controls the RU by specifying the address of the
Receive Frame Area and by starting, suspending, resuming, or aborting frame reception.
• Acknowledgment of events that cause interrupts.
• Resetting the chip.
The 82596 sends status reports to the CPU via the System Control Block. The SCB contains four types of
status reports.
• The cause of the current interrupts. These interrupts are caused by one or more of the following 82596
events.
.. The Command Unit completes an Action Command that has its I bit set.
• The Receive Unit receives a frame.
• The Command Unit becomes inactive.
• The Receive Unit becomes not ready.
• The status of the Command Unit.
• The status of the Receive Unit.
• Status reports from the 82596 regarding reception of corrupted frames.

1-63

·lnteI

82596CA

Events can be cleared only by CPU acknowledgment. If some events are not acknowledged by the ACK field
the Interrupt signal (I NT) will be reissued after Channel Attention (CA) is processed. Furthermore, if a new
event occurs while an interrupt is set, the interrupt is temporarily cleared to trigger edge-triggered interrupt
controllers.
The CPU uses the Channel Attention line to cause the 82596 to examine the SCB. This signal is trailing-edge
triggered-the 82596 latches CA on the trailing edge. The latch is cleared by the 82596 before the SCB .
control command is read.
31

16 15-

ODD WORD
ACK

Ixi

cuc

IRI

RUC

X X X

EVEN WORD

STAT

I0 I

cus

I0I

RUS

0 0 0 SCB

RFAOFFSET

CBLOFFSET

SCB + 4

ALIGNMENT ERRORS

CRCERRORS

SCB + 8

OVERRUN ERRORS

RESOURCE. ERRORS

SCB + 12

Figure 18. SCB-82586 Mode
31

ODD WORD
ACK

I0I

cuc

16 15

JR1 RUC J 0

0 o 01

RFAOFFSET

EVEN WORD
STAT

101

cus

RUS

CBLOFFSET

I
CRCERRORS

I TI 0 0 0 SCB
SCB+ 4
SCB+ 8

ALIGNMENT ERRORS

SCB +12

RESOURCE ERRORS (*)

SCB + 16

OVERRUN ERRORS (*)

SCB + 20

RCVCDT ERRORS (*)

SCB + 24

SHORT FRAME ERRORS
T-ONTIMER

SCB + 28
T-OFFTIMER

SCB + 32

*In monitor mode these counters change function

Figure 19. SCB-32·Bit Segmented Mode
31

ODD WORD
ACK

I0I

cuc

1RJ

16 .15
RUC

o 01

EVEN WORD
STAT

101

CUS

RUS

0
ITloo 0 SCB

COMMAND BLOCK ADDRESS

SCB +4

RECEIVE FRAME AREA ADDRESS

SCB + 8

CRCERRORS

SCB + 12

ALIGNMENT ERRORS

SCB + 16

RESOURCE EF.lRORS (*) ,

SCB + 20

OVERRUN ERRORS (*)

SCB + 24

RCVCDT ERRORS (*)

SCB + 28

SHORT FRAME ERRORS
T-ONTIMER

SCB + 32
T-OFFTIMER

*In MONITOR mode these counters change function

Figure 20. SCB-Llnear Mode

1-64

SCB + 36

82596CA

Command Word
16

ACK

CUC

RUC

8CB

These bits specify the action to be performed as a result of a CA. This word is set by,the CPU and cleared by
the 82596. Defined bits are:
Bit 31 ACK-CX

Acknowledges that the CU completed an Action Command.

Bit 30 ACK-FR

Acknowledges that the RU received a frame.

Bit 29 ACK-CNA

Acknowledges that the Command Unit became not active.

Bit 28 ACK-RNR

Acknowledges that the Receive Unit became not ready.

Bits 24-26 CUC

(3 bits) This field contains the command to the Command Unit. Valid values are:

o -

Bit 23 RESET

Bits 20-22 RUC

NOP (does not affect current state of the unit).

Start execution of the first command on the CBL. If a command is executing,
complete it before starting the new CBL. The beginning of the CBL is in CBL
OFFSET (address).

Resume the operation of the Command Unit by executing the next command.
This operation assumes that the Command Unit has been previously suspended.

Suspend execution of commands on CBL after current command is complete.

Abort current command immediately.

Loads the Bus Throttle timers so they will be initialized with their new values
after the active timer (T-ON or T-OFF) reaches Terminal Count. If no timer is
active new values will be loaded immediately. This command is not valid in
82586 mode.

Loads and immediately restarts the Bus Throttle timers with their new values.
This command is not valid in 82586 mode.

Reserved.

Reset chip (logically the same as hardware RESET).
(3 bits) This field contains the command to the Receive Unit. Valid values are:

o -

NOP (does not alter current state of unit).
Start reception of frames. The beginning of the RFA is contained in the RFA
OFFSET (address). If a frame is being received complete reception before
starting.

Resume frame reception (only when in suspended state).

Suspend frame reception. If a frame is being received complete its reception
before suspending.

Abort receiver operation immediately.

5-7 - Reserved.

1-65

82596CA

Status Word
15

____o___o___o~1

~~__~~~_T~__~_O~__~:C_U_S~:__~_O~__L:R_U_S~:__~I_o

SCB

82586 mode

~~~~~~_T~~~_O~~~:C_U_S~:__~~:~_RUL:S~·~__~T~l__o___o__~o~1

SCB

32-Bit Segmented and Linear mode.
Indicates the status of
Bit 15 CX
Bit 14 FR
Bit13CNA
Bit12 RNR
Bits 8-10 CUS

the 82596. This word is modified only by the 82596. Defined bits are:
The CU finished executing a command with its I (interrupt) bit. set.
The RU finished receiving a frame.
The Command Unit left the Active state.
The Receive Unit left the Ready state.
(3 bits) This field contains th~ status of the command unit. Valid values are:

-Idle
-Suspended

-Active

3-7 Bits 4-7 RUS

Not used

This field contains the status of the receive unit. Valid values are:
Oh (0000) - Idle
1h (0001) -

Suspended

2h (0010) .,- No Resources. This bit indicates both no resources due to lack of
RFDs in the RDL and no resources due to lack ofRBDs in the FBL.
4h (0100) - Ready
8h (1000) -

No more RBDs (not in the 82586 mode)

Ah (1010) - No resources due to no more RBDs (not in the 82586 mode).
No other combinations are allowed
Bit3T

Bus Throttle timers loaded (not in 82586 mode).

SCB OFFSET AOOF,lESSES
CBL Offset (Address)
In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the
first Command Block on the CBL. In Linear mode it is a 32-bit linear address for the first Command Block on
.
.
the CBL. It is accessed only if CUC equals Start.

RFA·Offset (Address)
In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the
Receive Frame Area. In Linear mode it is a 32-bit linear address for the Receive Frame Area. It is accessed
only if RUC equals Start.
.

1-66

intJ

82596CA

SCB STATISTICAL COUNTERS
Statistical Counter Operation
• The CPU is responsible for clearing all error counters before initializing the 82596. The 82596 updates
these counters by reading them, adding 1, and then writing them back to the SCB.
• The counters are wraparound counters. After reaching FFFFFFFFh the counters wrap around to zero.
• The 82596 updates the required counters for each frame. It is possible for more than one counter to be
updated; multiple errors will result in all affected counters being updated.
• The 82596 executes the read-counter/incrementlwrite-counter operation without relinquishing the bus
(locked operation). This is to ensure that no logical contention exists between the 82596 and the CPU due
to both attempting to write to the counters simultaneously. In the dual-port memory configuration the CPU
should not execute any write operation to a counter if LOCK is asserted.
• The counters are 32-bits wide and their behavior is fully compatible with the IEEE 802.3 standard. The
82596 supports all relevant statistics (mandatory, optional, and desired) through the status of the transmit
and receive header and directly through SCB statistics.

CRCERRS
This 32-bit quantity contains the number of aligned frames discarded because of a CRC error. This counter is
updated, if needed, regardless of the RU state.

ALNERRS
This 32-bit quantity contains the number of frames that both are misaligned (Le., where CRS deasserts on a
nonoctet boundary) and contain a CRC error. The counter is updated, if needed, regardless of the RU state;

SHRTFRM
This 327bit quantity contains the number of received frames shorter than the minimum frame length.
The last three counters change function in monitor mode.

RSCERRS
This 32-bit quantity contains the number of good frames discarded because there were no resources to
contain them. Frames intended for a host whose RU is in the No Receive Resources state, fall into this
category. This counter is updated only if the RU is in the No Resources state. When in Monitor mode this
counter counts the total number of frames-good and bad.

1-67

Intel

82596CA

OVRNERRS
This 32-bit quantity contains the number of frames known to be lost because the local system bus was not
available. If the traffic problem lasts longer than the duration of one frame, the frames that follow the first are
lost without an indicator, and they are not counted. This counter is updated, if needed, regardless of the RU
state.

RCVCDT
This 32-bit quantity contains the number of collisions detected during frame reception. In Monitor mode this
counter counts the total number of good frames.

ACTION COMMANDS AND OPERATING MODES
This section lists all the Action Commands of the Command Unit Command Block List (CBl). Each command
contains the Command field, the Status and Control fields, the link to the next Action Command, and any
command-specific parameters. There are three basic types of action commands: 82596 Configuration and
Setup, Transmission, and Diagnostics. The following is a list of the actual commands.
• NOP
• Individual Address Setup
• Configure

• Transmit
• TDR
• Dump

• MC Setup

• Diagnose

The 82596 has three addressing modes. In the 82586 mode all the Action Commands look exactly like those
of the 82586,
• 82586 Mode. The 82596 software and memory structure is compatible with the 82586.
• 32-Bit Segmented Mode. The 82596 can access the entire system memory and use the two new memory
structures-Simplified and Flexible.,.-while still using the segmented approach. This does not require any
significant changes to existing software.
• Linear Mode. The 82596 operates in a flat, linear, 4 gigabyte memory space without segmentation. It can
also use the two new memory structures.
In the 32-bit Segmented mode there are some differences between the 82596 and 82586 action commands,
mainly in programming and activating new 82596 features. Those bits marked "don't care" in the compatible
mode are not checked; however, we strongly recommend that those bits all be zeroes; this will allow future
enchancements and extensions.
In the Linear mode all of the address offsets become 32-bit address pointers. All new 82596 features are
accessible in this mode, and all bits previously marked "don't care" must be zeroes.
The Action Commands, and all other 825!)6 memory structures, must begin on even byte boundaries, Le., they
must be word aligned.

1-68

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82596CA

NOP
This command results in no action by the 82596 except .for those performed in the normal command processing. It is used to manipulate the CBl manipulation. The format of the NOP command is shown in Figure 21.

NOP-82586 and 32-Bit Segmented Modes
ODD WORD

EVEN WORD

X X X X X X X X X X

LINK OFFSET

AO 4

NOP-Linear Mode
ODD WORD

EVEN WORD

LINK ADDRESS

AO 4

Figure 21
where:
LINK POINTER

In the 82586 or 32-bit Segmented modes this is a 16-bit offset to the next Command
Block. In the Linear mode this is the 32-bit address of the next Command Block.

If set, this bit indicates that this command block is the last on the CBL.

...:... If set to one, suspend the CU upon completion of this CB.
-

CMD (bits 16-18) -

If set to one, the 82596 will generate an interrupt after execution of the command is
complete. If I is not set to one, the CX bit will not be sel
The NOP command. Value: Oh.

Bits 19-28

Reserved (zero in the 32-bit Segmented and Linear modes).

This bit indicates the execution status of the command. The CPU initially resets it to zero
when the Command Block is placed on the CBL. Following a command Completion, the
82596 will set it to one,

This bit indicates that the 82596 is currently executing the NOP command. It is initially
reset to zero by the CPU. The 82596 sets it to one when execution begins and to zero
when execution is completed. This bit is also set when the 82596 prefetches the command.

NOTE:
The Cand B bits are modified in one operation.
OK

Indicates that the command was executed without error. If set to one no error occurred
(command executed OK). If zero an error occured.

Individual Address Setup
This command is used to load the 82596 with the Individual Address. This address is used by the 82596 for
inserting the Source Address during transmission and recognizing the Destination Address during reception.
After RESET, and prior to Individual Address Setup Command execution, the 82596 assumes the Broadcast
Address is the Individual Address in all aspects, Le.:
• This will be the Individual Address Match reference.
• This will be the Source Address of a transmitted frame (for Al-lOC=O mode only).

1-69

82596CA

The format of the Individual Address Setup command is shown in Figure 22.

IA Setup-82586 and 32·Bit Segmented Modes
ODD WORD

31
ELI S II I X

16 15
X

xlo

INDIVIDUAL ADDRESS

1st byte A15

6th byte

EVEN WORD

c I B lOKI A 10

5th byte

LINK OFFSET

o 0
AO 4

4th byte

3rd byte

JA Setup-Linear Mode
31

ODD WORD

ELI s l l 10

EVEN WORD

16 15

0100

A31

c I B lOKI A 10

0
0

LINK ADDRESS
4th byte

3rd byte

o 0
AO 4

INDIVIDUAL ADDRESS

15t byte

6th byte

5th byte

Figure 22
where:
LINK ADDRESS,
EL, B, C, I,S

As per standard Command Block (see the NOP command for details)

Indicates that the command was abnormally terminated due to CU Abort control
command. If one, then the command was aborted, and if necessary it should be
repeated. If this bit is zero, the command was not aborted.

Bits 19-28
CMD(bits 16-18)

Reserved (zero in the 32-bit Segmented and Linear modes).
The. Address Setup command. Value: 1h.

INDIVIDUAL ADDRESS -

The individual address of the node, 0 to 6 bytes long.

The least significant bit of the Individual Address must be zero for Ethernet (see the Command Structure).
However, no enforcement of 0 is provided'by the 82596. Thus, an Individual Address with 1 as its least
significant bit is a valid Individual Address in all aspects.
The default address length is 6 bytes long, as in 802.3. If a different length is used the IA Setup command
should be executed after the Configure command.

Configure
The Configure command loads the 82596 with its operating parameters. It allows changing some of the
parameters by specifying a byte count less than the maximum number of configuration bytes (12 in the 82586
mode, 16 in the 32-Bit Segmented and Linear modes). The 82596 configuration depends on its mode of
operation.
• In the 82586 mode the maximum number of configuration bytes is 12. Any number larger than 12 will be
reduced to 12 and any number less than 4 will be increased to 4.
• The additional features of the serial side are disabled in the 82586 mode.
• In both the 32-Bit Segmented and Linear modes there are four additional configuration bytes, which hold
parameters for additional 82596 features. If these parameters are not accessed, the 82596 will follow their
default values.
• For more detailed information refer to the 32-Bit LAN Components User's Manual.

1-70

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82596CA

The format of the Configure command is shown in Figure 23, 24 and 25.
31

ODD WORD

ELI S II I X X X

X X

1615

X X

X xlo

EVEN WORD

c I B lOKI

AI0

0
0

Byte 0

Byte 5

Byte 4

Byte 3

Byte 2

Byte 9

Byt'e 8

Byte?

Byte 6

Byte 10

X X

X X X

X X

LINK OFFSET

o 0

Byte 1

X X X X X

A15

AO 4

Figure 23. CONFIGURE-82586 Mode
31

ODD WORD

ELI S II 10

1615
0

010

Byte 1

Byte 0

EVEN WORD

c I B lOKI A 10

LINK OFFSET

A15

AO 4

Byte 5

Byte 4

Byte 3

Byte 2

Byte 9

Byte. 8

Byte?

Byte 6

Byte 13

Byte 12

Byte 11

Byte 10

Figure 24. CONFIGURE-32-Bit Segmented Mode
31

ODD WORD

ELI S I I I 0

1615
0

010

EVEN WORD

c I B lOKI A I 0

0
0

LINK ADDRESS

A31

X X

o 0
AO 4

Byte 3

Byte 2

Byte 1

Byte 0

Byte?

Byte 6

Byte 5

Byte 4

Byte 11

Byte 10

Byte 9

Byte 8

Byte 13

Byte 12

X X X

X X

X X X

Figure 25. CONFIGURE-Linear Mode
LINK ADDRESS, EL, B,C, I,S
-

Bits 19-28
CMD (bits 16-18) -

As per standard Command Block (see the NOP command for details)
Indicates that the command was abnormally terminated due to a CU Abort control command. If 1, then the command was aborted and if necessary it should be repeated. If this
bit is 0, the command was not aborted.
Reserved (zero in the 32-Bit Segmented and Linear Modes)
The CONFIGURE command. Value: 2h.

The interpretation of the fields follows:
?

BYTE?OUNT

BYTE 0
BYTE CNT (Bits 0-3)
PREFETCHED (Bit 7)

Byte Count. Number of bytes, including this one, that hold parameters to be configured.
Enable the 82596 to write the prefetched bit in all prefetch
RBDs.

1-71

inter

82596CA

NOTE:
The P bit is valid only in the new memory structure modes. In 82586 mode this bit is disabled (Le., no
prefetched mark).

x
BYTE 1
FIFO Limit (Bits 0-3)

FIFO:UMIT

FIFO limit.
Receive monitor options. If the Byte Count of the configure
command is less than 12 bytes then these Mohitor bits are ignored.

MONITOR# (Bits 6-7)
DEFAULT: C8h
7

SAVBF

BYTE 2
SAY BF (Bit 7)

O-Received bad frames are not saved in the memory.
1-Received bad frames are saved in the memory.

DEFAULT: 40h
LOOP BACK
MODE

o
PREAMBLE LENGTH

ADDRESS LENGTH

BYTE 3
ADR LEN (Bits 0-2)
NO SCR ADD INS (Bit 3)

Address length (any kind).

PREAM LEN (Bits 4-5)
LP BCK MODE (Bits 6-7)

Preamble length.

No Source Address Insertion.
In the 82586 this bit is called AL LOC.
Loopback mode.

DEFAULT: 26h
7

BOFMETD

BYTE 4
LIN PRIO (Bits 0-2)
EXP PRIO (Bits 4-6)
BOF METD (Bit 7)

U~EAR PRIORI;rv

Linear Priority.
Exponential Priority.
Exponential Backoff method.

DEFAULT: OOh

7
: INTER FRA¥E SPACING :

BYTE 5
INTERFRAME SPACING

Interframe spacing.

DEFAULT: 60h

1-72

infef

82596CA

7
SLOTTI¥E - LOW

BYTE 6
SLOT TIME (L)

Slot time, low byte.

DEFAULT: OOh

~AXIMUM RE!RY NUMBE~

S~OT TIME - HI~H

BYTE 7
SLOT TIME (H)
(Bits 0-2)

Slot time, high part.

RETRY NUM (Bits 4-7)

Number of transmission retries on collision.

DEFAULT: F2h

BYTE 8
PRM (Bit 0)

Promiscuous mode.
Broadcast disable.

BC DIS (Bit 1)
MANCHINRZ (Bit 2)

Manchester or NRZ encoding. See specific timing requirements for TXC in Manchester mode.

TONO CRS (Bit 3)

Transmit on no CRS.

NOCRC INS (Bit 4)

No CRC insertiori.

CRC-16/CRC-32 (Bit 5)

CRC type.

BIT STF (Bit 6)

Bit stuffing.

PAD (Bit 7)

Padding.

DEFAULT: OOh

I CDTSRC I

COLLI~ION DETECT:FILTER

CRSSRC

BYTE 9
CRSF (Bits 0-2)

Carrier Sense filter (length).

CRS SRC (Bit 3)

Carrier Sense source.

CDTF (Bits 4-6)

Collision Detect filter (length).

COT SRC (Bit 7)

Collision Detect source.

DEFAULT: OOh

1-73

82596CA

~INIMUM FRfME LENGT~
BYTE 10
MIN FRAME LEN

Minimum frame length.

DEFAULT: 40h

MCJLL

COBSAC

AUTOTX

CRCINM

LNGFLO

PRECRS

BYTE 11
PRECRS (Bit 0)

Preamble until Carrier. Sense

LNG FLO (Bit 1)

Length field. Enables padding at the End-of-Carrier framing (802.3).

CRCINM (Bit 2)

Rx CRC appended to the frame in memory.

AUTOTX (Bit 3)

Auto retransmit when a collision occurs during the preamble.

CDBSAC (Bit 4)

Collision Detect by source address recognition.

MCJLL (Bit 5)

Enable to receive all MC frames.

MONITOR (Bits 6-1)

Receive monitor options.

DEFAULT:FFH

IOCR

FOX

OCR

SLO~AODRESS

BYTE 12
OCR SLOT ADDRESS
(Bits 0-5)

Station index in OCR mode.

FOX (Bit 6)

Enables Full Duplex operation.

OCR (Bit 7)

Enables Deterministic collision resolution.

DEFAULT: OOh

BYTE 13
OCR NUMBER OF
STATIONS (Bits 0-5)

Number of stations in OCR mode.

MULT_IA (Bit 6)

Multiple individual address.

DIS_BOF (Bit 7)

Disable the backoff algorithm.

DEFAULT: 3Fh

1-74

inter

82596CA

A reset (hardware or software) configures the 82596 according to the following defaults.

Table 4. Configuration Defaults
Parameter

·
•

·
•
•
•
•

•

•
,

•

Default Value

ADDRESS LENGTH
AIL FIELD LOCATION
AUTO RETRANSMIT
BITSTUFFING/EOC
BROADCAST DiSABLE
CDBSAC
COT FILTER
CDTSRC
CRC IN MEMORY
CRC-16/CRC-32
CRSFILTER
CRSSRC
OCR
OCR Slot Number
OCR Number of Stations
DISBOF
EXT LOOPBACK
EXPONENTIAL PRIORITY
EXPONENTIAL BACKOFF METHOD
FULL DUPLEX (FOX)
FIFO THRESHOLD
INT LOOPBACK
INTERFRAME SPACING
LINEAR PRIORITY
LENGTH FIELD
MIN FRAME LENGTH
MCALL
MONITOR
MANCHESTER/NRZ
MULTI IA
NUMBER OF RETRIES
NO CRC INSERTION
PRE FETCH BIT IN RBD
PREAMBLE LENGTH
Preamble Until CRS
PROMISCUOUS MODE
PADDING
SLOT TIME
SAVE BAD FRAME
TRANSMIT ON NO CRS

Units/Meaning

Bytes
Located in FD
Auto Retransmit Enable
EOC
Broadcast Reception Enabled
Disabled
Bit Times
External Collision Detection
CRC Not Transferred to Memory
CRC-32
"0
Bit Times
0
0
External CRS
0
Disable OCR Protocol
0
OCR Disabled
63 Stations
Backoff Enabled
0
Disabled
0
802.3 Algorithm
"0
802.3 Algorithm
"0
CSMAlCD Protocol (No FOX)
0
8
TX: 32 Bytes, RX: 64 Bytes
Disabled
0
"96 Bit Times
802.3 Algorithm
"0
Padding Disabled
"64 Bytes
1
Disabled
11 Disabled
0
NRZ
0
Disabled
"15 Maximum Number of Retries
CRC Appended to Frame
0
0
Disabled (Valid Only in New Modes)
"7
Bytes
1
Disabled
0
Address Filter On
0
No Padding
"512 Bit Times
Discards Bad Frames
0
0
Disabled
"6
0
1
0
0
1
0
0

NOTES
1. This configuration setup is compatible with the IEEE 802.3 specification.
2. The Asterisk ... " signifies a new configuration parameter not available in the 82586.
3. The default value of the Auto retransmit configuration parameter is enabled(1).
4. Double Asterisk .... " signifies IEEE 802.3 requirements.

1-75

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82596CA

Multicast-Setup
This command is used to load the 82596 with the Multicast-IDs that should be accepted. As noted previously,
the filtering done on the Multicast-IDs is not perfect and some unwanted frames may be accepted. This
command resets the current filter and reloads it with the specified Multicast-IDs. The format of the Multicastaddresses setup command is:
ODD WORD

31
ELI S II I X

16 15
X

xlo

C I B lOKI A 10

. EVEN WORD

0 o 0 0 0 0 0 0

A15

MCCOUNT

xlxl

LINK OFFSET

0
0 0 0
AO
1st byte

4th byte
MULTICAST ArRESSES LIST
Nth byte

Figure 26. MC Setup-82586 and 32-Bit Segmented Modes
31
ELI S II 10

ODD WORD

EVEN WORD

16 15

0 o 0 0 0 o 0 010

1 I C I B lOKI A I 0

0 000

0
0 o 0 0 0 0

LINK ADDRESS

A31
2nd byte

1st byte I X I X I

AO
MCCOUNT

MULTICAST ArRESSES LIST
Nth byte

Figure 27. MC Setup-Linear Mode

where:
LINK ADDRESS,
EL, B,C,I,S

As per standard Command Block (see the NOP command for details)

Bits 19-28
CMD (bits 16-18)

Indicates that the command was abnormally terminated due to a CU Abort control
command. If one, then the command was aborted and if necessary it should be
repeated. If this bit is zero, the command was not aborted.
Reserved (0 in both the 32-Bit Segmented and Linear Modes).

The MC SETUP command value: 3h.

MC-CNT

MC LIST

This 14-bit field indicates the number of bytes in the MC LIST field. The MC CNT
must be a multiple of the ADDR LEN; otherwise, the 82596 reduces. the MC CNT to
the nearest ADDR LEN multiple. MC CNT = 0 implies resetting the Hash table
which is equivalent to disabling the Multicast filtering mechanism~
-

A list of Multicast Addresses to be accepted by the 82596. The least significant bit
of each MC address must be 1.

NOTE:
The list is sequential; i.e., the most significant byte of an address is immediately followed by the least significant byte of the next address.
- When the 82596 is configured to recognize multiple Individual Address (Multi-IA),
the MC-Setup command is also used to set up the Hash table for the individual
address.
The least significant bit in the first bYte of each IAaddress must be O.

1-76

inter

82596CA

Transmit
This command is used to transmit a frame of user data onto the serial link. The format of a Transmit command
is as follows.
31

ODD WORD

ELI S II I X X

A15

X X X

1615
X

X X 11

TBDOFFSET

clBI

AO A15

4th byte

EVEN WORD
STATUS BITS

I
LINK OFFSET

0
AO 4

1st byte B

DESTINATION ADDRESS
LENGTH FIELD

0
MAXCOLL

6th byte

Figure 28. TRANSMIT-82586 Mode
31

ODD WORD

I Jo

A15
o

1615

L Nc.1

SF I 1

C I BI

AD A15

TBDOFFSET
0

EVEN WORD
STATUS BITS

I
LINK OFFSET

DESTINATION ADDRESS
LENGTH FIELD

0
AO 4

TCBCOUNT

o EOFI 0 I

4th byte

0
MAXCOLL

8
1st byte 12
16

6th byte
OPTIONAL DATA

Figure 29. TRANSMIT-32-Bit Segmented Mode
31

ODD WORD

EL I

010

1615

01 NC I SF 11

A31

C IBI

4th byte

0 EOFloJ
DESTINATION ADDRESS

LENGTH FIELD

6th byte
OPTIONAL DATA

Figure 30. TRANSMIT-Linear Mode
31

COMMAND WORD

i i
0: No CRC Insertion disable; when the
0: Simplified Mode, all the Tx data is in
configure command is configured to
the Transmit Command Block. The
not insert the CRC during
Transmit Buffer Descriptor Address
transmission the NC bit has no effect.
field is all 1s.
1; No CRC Insertion enable; when the
1: Flexible Mode. Data is in the TCB
configure command is configured to
and in a linked list of TBDs.
insert the CRC during transmission
the CRC will not be inserted when
NC = 1.

1-77

MAXCOLL

0
AO 4

TRANSMIT BUFFER DESCRIPTOR ADDRESS
0

EVEN WORD
STATUS BITS

LINK ADDRESS

A31
0

AO 8
TCBCOUNT

12
1st byte 16
20

intJ

82596CA

where:
EL, B, C, I, S

OK (Bit 13)

Error free completion.

A (Bit 12)

Indicates that the command was abnormally terminated due to CU Abort control
command. If 1, then the command was aborted, and if necessary it should be
repeated. If this bit is 0, the command was not aborted.

As per standard Command Block (see the NOP command for detailS).

Bits 19-28

Reserved (0 in the 32-bit Segmented and Linear modes).

CMD (Bits 16-18)

The transmit command: 4h.

Status Bit 11

Late collision. A late collision (a collision after the slot time is elapsed) is detected.

Status Bit 10

No Carrier Sense signal during transmission. Carrier Sense signal is monitored
from the end of Preamble transmission until the end of the Frame Check Sequence
for TONOCRS= 1 (Transmit On No Carrier Sense mode) it indicates that transmission has been executed .despite a lack of CRS. For TONOCRS = 0 (Ethernet
mode), this bit also indicates unsuccessful transmission (transmission stopped
when lack of Carrier Sense has been detected).

Status Bit 9

- Transmission unsuccessful (stopped) due to Loss of CTS.

Status Bit 8

- Transmission unsuccessful (stopped) due to DMA Underrun; i.e., the system did
not supply data for transmission.

Status Bit 7

Transmission Deferred, i.e., transmission was not immediate due to previous link
activity.

Status Bit 6

Heartbeat Indicator, Indicates that after a previously performed transmission, and
before the most recently performed transmission, (Interframe Spacing) the COT
signal was monitored as active. This indicates tnat the Ethernet Transceiver Collision Detect logic is performing properly. The Heartbeat is monitored during the
Interframe Spacing period.

Status Bit 5

Transmission attempt was stopped because the number of collisions exceeded the
maximum allowable number of retries.

MAX-COL
(Bits 3-0)

The number of Collisions experienced during this frame. Max Col = 0 plus S5 = 1
indicates 16 collisions.

LINK OFFSET

As per standard Command Block (see the NOP Command for details)

TBD POINTER

DEST ADDRESS

Contains the Destination Address of the frame: The least significant bit (MC) indicates the address type.
MC = 0: Individual Address.
MC = 1: Multicast or Broadcast Address.
If the Destination Address bits are all 1s this is a Broadcast Address.

LENGTH FIELD

- The contents of this 2-byte field are user defined. In 802.3 it contains the length of
the data field. It is placed in memory in the same order it is transmitted; i.e., most
significant byte first, least significant byte second.

TCBCOUNT

This 14-bit counter indicates the number of bytes that will be transmitted from the
Transmit Command Block, starting from the third byte after the TCB COUNT field
(address n+12 in the 32-bit Segmented mode, N+16 in the Linear mode). The
TCB COUNT field can be any number of bytes (including an odd byte), this allows
the user to transmit a frame with a header having an odd number of bytes. The
TCB COUNT field is not used in the 82586 mode.

EOF Bit

Indicates that the whole frame is kept in the Transmit Command Block. In the
Simplified memory model it must be always asserted.

1-78

inter

82596CA

The interpretation of what is transmitted depends on the No Source Address insertion configuration bit and the
memory model being used.
NOTES
1. The Destination Address and the Length Field are sequential. The Length Field immediately follows the
most significant byte of the Destination Address.
2. In case the 82596 is configured with No Source Address insertion bit equal to 0, the 82596 inserts its
configured Source Address in the transmitted frame.

• In the 82586 mode, or when the Simplified memory model is used, the Destination and Length fields of the
transmitted frame are taken from the Transmit Command Block.
• If the FLEXIBLE memory model is used, the Destination and Length fields of the transmitted frame can be
found either in the TCB or TBD, depending on the TCB COUNT.
3. If the 82596 is configured with the Address/Length Field Location equal to 1, the 82596 does not insert its
configured Source Address in the transmitted frame. The first (2 x Address Length) + 2 bytes of the
transmitted frame are interpreted as Destination Address, Source Address, and Length fields respectively.
The location of the first transmitted byte depends on the operational mode of the 82596:
• In the 82586 mode, it is always the first byte of the first Tx Buffer.
• In both the 32-bit Segmented and Linear modes it depends on the SF bit and TCB COUNT:
-

In the Simplified memory mode the first transmitted byte is always the third byte after the TCB COUNT
field.
In the Flexible mode, if the TCB COUNT is greater than 0 then it is the third byte after the TCB COUNT
field. If TCB COUNT equals 0 then it is first byte of the first Tx Buffer.

• Transmit frames shorter than six bytes are invalid. The transmission will be aborted (only in 82586 mode)
because of a DMA Underrun.
4. Frames which are aborted during transmission are jammed. Such an interruption of transmission can be
caused by any reason indicated by any of the status bits 8, 9, 10 and 12.

Jamming Rules
1. Jamming will not start before completion of preamble transmission.
2. Collisions detected during transmission of the last 11 bits will not result in jamming.
The format of a Transmit Buffer Descriptor is:
82586 Mode
ODD WORD

NEXT TBD OFFSET
X

EVEN WORD

SIZE (ACT COUNT)

TRANSMIT BUFFER ADDRESS

32-Bit Segmented Mode
31

1615

ODD WORD

NEXT TBD OFFSET

EVEN WORD

SIZE (ACT COUNT)

TRANSMIT BUFFER ADDRESS

Linear Mode
31
a

16 15

ODD WORD
a

010

alEoFI

EVEN WORD
SIZE (ACT COUNT)

NEXT TBD ADDRESS

TRANSMIT BUFFER ADDRESS

Figure 31

1-79

Intel

82596CA

where:
EOF

This bit indicates that this TBD is the last one associated with the frame being
transmitted. It is set by the CPU before transmit.

SIZE (ACT COUNT)

This 14-bit quantity specifies the number of bytes that hold information for the
current buffer. It is set by the CPU before transmission.

NEXT TBD ADDRESS -

In the 82586 and 32-bit Segmented modes, it is the offset of the next TBD on the
list. In the Linear mode this is the 32-bit address of the next TBD on the list. It is
meaningless if EOF = 1.
.

BUFFER ADDRESS

The starting address of the memory area that contains the data to be sent. In the
82586 mode, this is a 24-bit address (A31-A24 are considered to be zero). In the
32-bit Segmented and Linear modes this is a 32-bit address.

TOR
This operation activates Time Domain Reflectomet, which is a mechanism to detect open or short circuits on
the link and their distance from the diagnosing station. The TOR command has no parameters. The TOR
transmit sequence was changed, compared to the 82586, to form a regular transmission. The TOR bit stream
is as follows.
-

Preamble

Source address

Another Source address (the TOR frame is transmitted back to the sending station,
so DEST ADR = SRC ADR).

Data field containing 7Eh patterns.

Jam Pattern, which is the inverse CRC of the transmitted frame.

Maximum length of the TOR frame is 2048 bits. If the 82596 senses collision while transmitting the TOR frame
it transmits the jam pattern and stops the transmission. The 82596 then triggers an internal timer (STC); the
timer is reset at the beginning of transmission and reset if CRS is returned. The timer measures the time
elapsed from the start of transmission until an echo is returned. The echo is indicated by Collision Detect going
active or a drop in the Carrier Sense signal. The following table lists the possible cases that the 82596 is able
to analyze.
Conditions of TDR as Interpreted by the 82596
Transceiver Type

Ethernet

Condition

. Non Ethernet

Carrier Sense was inactive for 2048-bit-time
periods

Short or Open on the
Transceiver Cable

Carrier Sense signal dropped

Short on the Ethernet cable

Collision Detect went active

Open on the Ethernet cable

Open on the Serial Link

The Carrier Sense Signal did not drop or the
Collision Detect did not go active within
2048-bit time period

No Problem

An Ethernet transceiver is defined as one that returns transmitted data on the receive pair and activates the
Carrier Sense Signal while transmitting. A Non~Ethernet Transceiver is defined as one that does not do so.

1-80

intJ

82596CA

The format of the Time Domain Reflectometer command is:
82586 and 32-81t Segmented Modes
31

ODD WORD
S

1615

X X X X X X X X X 11

LNK XVR ET
ETrl
OK PRS OPN SRT

EVEN WORD
0

1 cl S lOKI 0

TIME
(11 bits)

A15

000

0
0 o

o. 0

0
AO

LINK OFFSET

Linear Mode
31

ODD WORD

ELI S II 10

A31
o

EVEN WORD

16 15
0

011

1 Ie

S lOKI 0

0
0

000

LINK ADDRESS
0

000

I I I I II
LNK
OK

XVR
PRS

ET
OPN

ET
SRT

0
AO

TIME
(11 bits)

Figure 32. TDR

where:
LINK ADDRESS,
EL, B,C,I,S

As per standard Command Block (see the NOP command for details).

Bits 19-28

Reserved (0 in the 32-bit Segmented and Linear Modes).

CMD (Bits 16-18)

The TOR command. Value: 5h.

TIME

An ii-bit field that specifies the number of TxC cycles that elapsed before an echo
was observed. No echo is indicated by a reception consisting of "is" only. Because the network contairis various elements such as transceiver links, transceivers, Ethernet, repeaters etc., the TIME is not exactly proportional to the problems
.
distance.

LNKOK (Bit 15)

No link problem identified. TIME = 7FFh.

XCVR PRB (Bit 14)

Indicates a Transceiver problem. Carrier Sense was inactive for 2048-bit time period. LNK OK=O. TIME,;=7FFh.

ET OPN (Bit 13)

The transmission line is not properly terminated. Collision Detect went active and
LNK OK=O.

ET SRT (Bit 12)

There is a short circuit on the transmission line. Carrier Sense Signal dropped and
LNK OK=O.

1-81

intJ

82596CA

DUMP
This command causes the contents of various 82596 registers to be placed in a memory area specified by the
user. It is supplied as a 82596 self-diagnostic tool, and to provide registers of interest to the user. The format
of the DUMP command is:

,
82586 and 32-Bit Segmented Modes
31
ELI S II I X

ODD WORD
x

A15

16 15
x

X 11

BUFFER OFFSET

ole I B lOKI 0

EVEN WORD
0

0
0

LINK OFFSET

AOIA15

0
AO

Linear Mode
31
ELI S II I X

ODD WORD
x

16 15
x

X 11

ole I B lOKI 0

EVEN WORD
0

0
0

A31

LINK ADDRESS

A31

BUFFER ADDRESS

Figure 33. Dump

where:
LINK ADDRESS,
EL, B, C, I, S
OK
Bits 19-28
CMD (Bits 16-18)
BUFFER POINTER

As per standard Command Block (see the NOP command for details).

Indicates error free completion.

Reserved (0 in the 32-bit Segmented and Linear Modes).

The Dump command. Value: 6h.

In the 82586 and 32-bit Segmented modes this is the 16-bit-offset portion of the
dump area address. In the Linear mode this is the 32-bit linear address of the dump
area.

Dump Area Information Format

• The 82596 is not Dump compatible with the 82586 because of the 32-bit internal architecture. In 82586
mode the 82596 will dump the same number of bytes as the 82586. The compatible data will be marked
with an asterisk.
• In 82586 mode the dump area is 170 bytes.
• The DUMP area format of the 32-bit Segmented and Linear modes is described in Figure 35.
• The size of the dump area of the 32-bit Segmented and Linear modes is 304 bytes.
• When the Dump is executed by the Port command an extra word will be appended to the Dump Area. The
extra word is a copy of the Dump Area status word (containing the C, B, and OK Bits). The C and OK Bits
are set when the 82596 has completed the Port Dump command.

1-82

82596CA

15 14 13 12 11

DMA CONTROL REGISTER

CONFIGURE BYTES' 3, 2

CONFIGURE BYTES' 5, 4
CONFIGURE BYTES' 7, 6

04
06

CONFIGURE BYTES' 9, 8

CONFIGURE BYTES' 10

LA. BYTES 1, 0'

LA. BYTES 3, 2'

LA. BYTES 5, 4'
LAST T.X. STATUS'

'The 82596 is not Dump compatible with
the 82586 because of the 32-bit internal architecture. In 82586 mode the 82596 will
dump the same number of bytes as the
82586.
"'These bytes are not user defined, results
may vary from Dump command to Dump
command.

T.X. CRC BYTES 1, 0'

T.X. CRC BYTES 3, 2'

R.X. CRC BYTES 1, 0'

R.X. CRC BYTES 3,2'

R.X. TEMP MEMORY 1, 0'
R.X. TEMP MEMORY 3, 2'

1C
1E

R.X. TEMP MEMORY 5, 4'

LAST RECEIVED STATUS'

HASH REGISTER BYTES 1, 0'

HASH REGISTER BYTES 3, 2'

HASH REGISTER BYTES 5, 4'

HASH REGISTER BYTES 7, 6'

SLOT TIME COUNTER'

WAIT TIME COUNTER'

MICRO MACHINE"

6A
6C

MICRO MACHINE"

FLAG ARRAY
14 BYTES

QUEUE MEMORY"

CUPORT
8 BYTES

MICRO MACHINE ALU"

RESERVED"

M.M. TEMP A ROTATE R"

M.M. TEMPA"

T.X. DMA BYTE COUNT"

M.M. INPUT PORT ADDRESS"

T.X. DMA ADDRESS

M.M. OUTPUT PORT"

R.X. DMA BYTE COUNT"

R.U. DMA ADDRESS"
M.M. OUTPUT PORT ADDRESS REGISTER"

96
98

RESERVED"

BUS THROTILE TIMERS

DIU CONTROL REGISTER"

RESERVED"

DMA CONTROL REGISTER"

BIU CONTROL REGISTER"

A4
A6
A8

M.M. DISPATCHER REG."
M.M. STATUS REGISTER"

Figure 34. Dump Area Format-82586 Mode

1-83

intJ

82596CA

CONFIGURE BYTES 5, 4, 3, 2

CONFIGURE BYTES 9, 8, 7, 6

CONFIGURE BYTES 13,12,11,10
I.A. BYTES I, 0

08
X

X OC

I.A. BYTES 5, 2

TX CRC BYTES 0, 1

LAST T.X. STATUS

RX CRC BYTES 0, 1

TX CRC BYTES 3, 2

RX TEMP MEMORY I, 0

RX CRC BYTES 3, 2

R.X. TEMP MEMORY 5, 2
HASH REGISTERS 1,0

LAST R.X. STATUS

HASH REGISTER BYTES 5, 2
SLOT TIME COUNTER
RECEIVE FRAME LENGTH

HASH REGISTERS 7, 6

WAIT-TIME COUNTER

MICRO MACHINE"

'The 82596 is not Dump compatible with
the· 82586 because of the 32-bit internal archRecture. In 82586 mode the 82596 will
dump the same number of bytes as the
82586.
"These bytes are not user defined, results
may vary from Dump command to Dump
command.

MICRO MACHINE LFSR"

MICRO MACHINE"

FLAG ARRAY
28 BYTES

M.M. INPUT PORT"
16 BYTES

MICRO MACHINE ALU"

RESERVED"

M.M. TEMP A ROTATE R.··

M.M.TEMPA"

T.X. DMA BYTE COUNT"

M.M. INPUT PORT ADDRESS REGISTER"

T.X. DMA ADDRESS"
M.M. OUTPUT PORT REGISTER"
R.x. DMA BYTE COUNT"

FC
.

100
104

M.M. OUTPUT PORT ADDRESS REGISTER"

108

R.X. DMA ADDRESS REGISTER"

10C

RESERVED"

110

BUS THROTILE TIMERS

114

DIU CONTROL REGISTER"

118

RESERVED"

llC

DMA CONTROL REGISTER~'

120

BIU CONTROL REGISTER"

124

M.M. DISPATCHER REG."

128

M.M. STATUS REGISTER"

12C

Figure 35. Dump Area Format-Linear and 32·Bit Segmented Mode.

1-84

82596CA

Diagnose
The Diagnose Command triggers an internal self-test procedure that checks internal 82596 hardware" which
includes:
• Exponential Backoff Random Number Generator (Linear Feedback C::hift Register).
• Exponential Backoff Timeout Counter.
• Slot Time Period Counter.
• Collision Number Counter.
• Exponential Backoff Shift Register.
• Exponential Backoff Mask Logic.
• Timer Trigger Logic.
This procedure checks the operation of the Backoff block, which resides in the serial side and is not easily
controlled. The Diagnose command is performed in two phases.
The format of the 82596 Diagnose command is:
82586 and 32-Bit Segmented Modes
ODD WORD

1615

X X X X X X X X X X
x X X X X X X X X X

EVEN WORD

LINK OFFSET

Linear Mode
ODD WORD

16 15

EVEN WORD

000

AO
Figure 36. Diagnose

where:
LINK ADDRESS,
EL, B, C,I,S

As per standard C0mmand Block (see the NOP command for details).

Bits 19-28

Reserved (0 in the 32-bit Segmented and Linear Modes).

CMD (bits 16-18)

The Diagnose command. Value: 7h.

OK (bit 13)

Indicates error free completion.

F(bit11)

Indicates that the self-test procedure has failed.

1-85

Inter

82596CA

RECEIVE FRAME DESCRIPTOR
Each received frame is described by one Receive Frame Descriptor (see Figure 37). Two new memory
structures are available for the received frames. The structures are available only in the Linear and 32-bit
Segmented modes.

Simplified Memory Structure
The first is the Simplified memory structure, the data section of the received frame is part of the RFD and is
located immediately after the Length Field. Receive Buffer Descriptors are not used with the Simplified structure, it is primarily used to make programming easier. If the length of the data area described in the Size Field
is smaller than the incoming frame, the following happens.
1. The received frame is truncated.
2. The No Resource error counter is updated.
3. If the 82596 is configured to Save Bad Frames the RFD is not reused; otherwise, the same RFD is used to
hold the next received frame, and the only action taken regarding the truncated frame is to update the
counter.
4. The 82596 continues to receive the next frame in the next RFD.

L
-

SCB

RECEIVE FRAME AREA
RFD 1

RFA
POINTER

STATUS

STATISTICS

STATUS

....,....

TO
OMMAND
BLOCK
LIST

RBDI

EMPTY

RECEIVE
BUFF'ERS

If
,

ACT-cnt

VALID
DATA,

BUFFER 1

RBD2

oj A C T - : S I j
RECEIVE
BUFFER
DESCRIPTORS

-r

----

BUFFER 2

RBD3

STATUS

EMPTY

VALID,
PARAMETERS

RECEIVE
FRAME
DESCRIPTORS

RBD4

RBD5

lJ -U- -y
,
,
,

ACT-cnt

DjAcT-cnt

OJACT-cnt

J-

'---

BUFFER 3

RECEIVE FRAME LIST

BUFFER 4

------

BUFFER 5

FREE FRAME LIST

290218-15

Figure 37. The Receive Frame Area

1-86

inter

82596CA

Note that this sequence is very useful for monitoring. If the 82596 is configured to Save Bad Frames, to
receive in Promiscuous m0ge, and to use the Simplified memory structure, any programmed length of received
data can be saved in memory.
The Simplified memory structure is shown in Figure 38.

SCB
STATUS
CBL
POINTER
RrA
POINTER

~ TO COMMAND LIST

RECEIVE rRAt.lE AREA

rD2

STATUS

STATISTICS
I
I
I

I
BUS
THROTILE II

._-----_.
RECEIVE
rRAME
DESCRIPTORS

I
I

rol

I
I
I
I
I
I
I
I

VARIABLE
DATA
rlELD

rD3

rD4

-wi~

EMPTY

I
I
I
I
I
I
I
I

I
I
I
I
I
I
I

EMPTY

._----_.

Et.tPTY

I
I
I
I
I
I
I

~ RECEIVE rRAt.tE LIST ---1.~:.4------- rREE rRAME LIST --------i.~:

290218-16

Figure 38. RFA Simplified Memory Structure

Flexible Memory Structure
The second structure is the Flexible memory structure, the data structure of the received frame is stored in
both the RFD and in a linked list of Receive Buffers-Receive Buffer Descriptors. The received frame is placed
in the RFD as configured in the Size field. Any remaining data is placed in a linked list of RBDs.
The Flexible memory structure is shown in Figure 39.

1·87

82596CA

SCB
STATUS

CO~~AND

RECEIVE

I
I
I

CBl
POINTER

LIST

14
FD1

RFA
POINTER

STATUS

BUS
THROTTLE

CONTROL
FIELD

RECEIVE

VARIABLE
DATA
FIELD

._------.
FRA~E

DESCRIPTORS

RBD2

-Lr
T

E~PTY

-.L

VALID
DATA

,+-- RECEIVE FRA~E

'-Lr

STATUS

I
I
I

I
I
I
I

I
I
I

E~PTY

I
I

._----_ .

.. ----_ .

RBD4

RBD5

-.L

E~PTY

'--

BUFFER 2

BUFFER 3

LIST

-Lt:

I
E~PTY

STATUS

RBD3

'--

BUFFER 1

FD4

-Uf -f -Lr ---n

-.L
RECEIVE
BUFFERS

I
I
I
I
I
I
I
I

RBD1

RECEIVE
BUFFER
DESCRIPTORS

FD3

._----_.

AREA

r--

STATUS

STATISTICS
I
I
I

FRA~E

FD2

.: 4

'--

BUFFER 4

FREE

FRA~E

BUFFER 5

LIST

290218-17

Figure 39. RFA Flexible Memory Structure

Buffers on the receive side can be different lengths. The 82596 will not place more bytes into a buffer than
indicated in the associated RBD. The 82596 will fetch the next RBD before it is needed. The 82596 will
attempt to receive frames as long as the FBL is not exhausted. If there are no more buffers, the 82596
Receive Unit will enter the No Resources state. Before starting the RU, the CPU must place the FBL pointer in
the RBD pointer field of the first RFD. All remaining RBD pointer fields for subsequent RFDs should be "1 s." If
the Reqeive Frame Descriptor and the associated Receive Buffers are not reused (e.g., the frame is properly
received or the 82596 is configured to Save Bad Frames), the 82596 writes the address of the next free RBD
to the RBD pointer field of the next RFD.

Receive Buffer Descriptor (RBD)
The RBDs are used to store received data in a flexible set of linked buffers. The portion of the frame's data
field that is outside the RFD is placed in a set of buffers chained by a sequence of RBDs. The RFD points to
the first RBD, and the last RBD is flagged with an EOF bit set to 1. Each buffer in the linked list of buffers
related to a particular frame can be any size up to 214 bytes but must be word aligned (begin on an even
numbered byte). This ensures optimum use of the memory resources while maintaining low overhead. All
buffers in a frame are filled with the received data except for the last, in which the actual count can be smaller
than the allocated buffer space.
'

1-88

tptro lS lb Ulk'AJ UlRI~ll\H{

82596CA

ODD WORD

. ELI S I

16 15

x x x x x x x x x x x x x x
RBDOFFSET

A15

EVEN WORD

C I B lOKI 0 I

0
10

LINK OFFSET

AO A15

4th byte

STATUS BITS

DESTINATION ADDRESS

SOURCE ADDRESS

o 0
A04

1st byte 8

1st byte 6th byte

4th byte

6th byte

X X X X XX X X X X X X X X X X

16
LENGTH FIELD

Figure 40. Receive Frame Descriptor-82586 Mode
31

1615

ODD WORD

ELI S 10

A15

000

o ISFI 0

RBDOFFSET

EOFI F

SOURCE ADDRESS

0
AO 4

ACTUAL COUNT

DESTINATION ADDRESS

4th byte

STATUS BITS
LINK OFFSET

AO A15

SIZE

0101

EVEN WORD

C I B lOKI

8
1st byte 12

1st byte 6th byte

4th byte

6th byte

LENGTH FIELD

OPTIONAL DATA AREA

Figure 41. Receive Frame Descriptor.;.....32-Bit Segmented Mode
31

1615

ODD WORD

ELI S 10

A31

olsFlo

6th byte

STATUS BITS

EOFI FJ
6th byte

12
1st byte 16
20

4th byte

24
LENGTH FIELD

OPTIONAL DATA AREA

Figure 42. Receive Frame Descriptor-Linear Mode

1-89

AO 8
ACTUAL COUNT

DESTINATION ADDRESS
1st byte

AO 4

RECEIVE BUFFER DESCRIPTOR ADDRESS
SIZE

4th byte
SOURCE ADDRESS

EVEN WORD

C I B lOKI

LINK ADDRESS

A31
oj 01

82596CA

where:
EL

S
SF

- When set, this bit indicates that this RFD is the last one on the RDL.
- When set, this bit suspends the RU after receiving the frame.
- This bit selects between the Simplified or the Flexible mode.
0- Simplified mode, all the RX data is in the RFD. RBD ADDRESS field is all
"1 s,"
1-

OK (bit 13)

STATUS

LINK ADDRESS
RBD POINTER
EOF
F
SIZE
ACT COUNT
MC
DESTINATION
ADDRESS
SOURCE ADDRESS
LENGTH FIELD

Flexible mode. Data is in the RFD and in a. linked list of Receive Buffer Descriptors.

- This bit i~dicates the completion of frame reception. It is set by the 82596.
- This bit indicates that the 82596 is currently receiving this frame, or that the 82596
is ready to rece.ive the frame. It is initially set to 0 by the CPU. The 82596 sets it to
1 when reception set up begins, and to 0 upon completion. The C and B bits are
set during the same operation.
-' Frame received successfully, without errors. RFDs with bit 13 equal to 0 are possible only if the save bad frames, configuration option is selected. Otherwise all
frames with errors will be discarded, although statistics will be collected on them.
- The results of the Receive operation. Defined bits are,
Bit 12:
Length error if configured to check length
Bit 11:
CRG error in an aligned frame
Bit 10:
Alignment error (CRC error in misaligned frame)
Bit9:
Ran out of buffer space-no resources
Bit8:
DMA Overrun failure to acquire the system bus.
Bit 7:
Frame too short.
Bit 6:
No EOP flag (for Bit stuffing only)
Bit 5:
When the SF bit equals zero, and the 82596 is configured to save bad
frames, this bit signals that the receive frame was truncated. Otherwise it
is zero.
Bits 2-4: Zeros
Bit 1:
When it is zero, the destination address of the received frame matches
the IA address. When it is a 1, the destination address of the received
frame did not match the individual address. For example, a multicast
address or broadcast address will set this bit to a 1.
Bit 0:
Receive collision, a collision is detected during reception.
- A 16-bit offset (32-bit address in the Linear mode) to the nex1 Receive Frame
Descriptor. The Link Address of the last frame can be used to form a cyclical list.
- The offset (address in the Linear mode) of the first RBD containing the received
frame data. An RBD pointer of all ones indicates no RBD.
.
- These fields are for the Simplified and Flexible memory models. They are exactly
the same as the respective fields in' the Receive Buffer Descriptor. See the next
section for detailed explanation of their functions.
-

Multicast bit.
The contents of the destination address of the receive frame. The field is 0 to 6
bytes long.
- The contents of the Source Address field of the received frame. It is 0 to 6 bytes
long.
- The contents of this 2-byte field are user defined. In 802.3 it contains the length of
the data field. It is placed in memory in the same order it is received, i.e., most
significant byte first, least significant byte second.

1-90

inter

82596CA

NOTES
1. The Destination address, Source address and Length fields are packed, i.e., one field immediately follows
the next.
2. The affect of Address/Length Location (No Source Address Insertion) configuration parameter while receiving is as follows:
-

82586 Mode: The Destination address, Source address and Length field are not used, they are placed in
the RX data buffers.

32-Bit Segmented and Linear Modes: when the Simplified memory model is used, the Destination address,
Source address and Length fields reside in their respective fields in the RFD. When the Flexible memory
strucrture is used the Destination address, Source address, and Length field locations depend on the SIZE
field of the RFD. They can be placed in the RFD, in the RX data buffers, or partially in the RFD and the rest
in the RX data buffers, depending on the SIZE field value.
82586 Mode
31

ODD WORD

A15
X

X IA23

EVEN WORD

1615

NEXT RBD OFFSET

RECEIVE BUFFER ADDRESS
X

0
0

ACTUAL COUNT

AolEOFI F I

AO 4
SIZE

X I EL I X I

32-Bit Segmented Mode
ODD WORD

16 15

NEXT RBD OFFSET

A15
A31

EVEN WORD

0 0 I EL I

0
AO 4

RECEIVE BUFFER ADDRESS

ACTUAL COUNT

AolEOFI F I

SIZE

Linear Mode
31

ODD WORD

OIEOFI FI

ACTUAL COUNT

NEXT RBD ADDRESS

A31
A31

EVEN WORD

16 15

01 EL I

Figure 43. Receive Buffer Descriptor

1-91

0
AO 4
AO 8

RECEIVE BUFFER ADDRESS

SIZE

Intel

82596CA

where:
EOF

Indicates that this is the last buffer related to the frame. It is cleared by the CPU
before starting the RU, and is written by the 82596 at the end of reception of the
.
frame.

Indicates that this buffer has already been used. The Actual Count has no meaning
unless the F bit equals one. This bit is cleared by the CPU before starting the RU,
and is set by the 82596 after the associated puffer has been. This bit has the same
meaning as the Complete bit in the RFD and CB.

ACT COUNT

This 14-bit quantity indicates the number of meaningful bytes in the buffer. It is
cleared by the CPU before starting the RU, and is written by the 82596 after the
associated buffer has already been used. In general, after the buffer is full, the
Actual Count value equals the size field of the same buffer. For the last buffer of
the frame, Actual Count can be less than the buffer size.

NEXT BD ADDRESS

The offset (absolute address in the Linear mode) of the next RBD on the list. It is
meaningless if EL=1.

BUFFER ADDRESS

The starting address of the memory area that contains.the received data. In the
82586 mode, this is a 24-bitaddress (with pins A24-A31 =0). In the 32-bit Segmented and Linear modes this is a 32-bit address.
.
.

Indicates that the buffer associated with this RBD is last in the FBL.

This bit indicates that the 82596 has already prefetched the RBDs and any change
in the RBD data will be ignored. This bit is valid only in the new 82596 memory
modes, and if this feature has been enabled during .configure command. The
82596 Prefetches the RBDs in locked cycles; after prefetching·the RBD the 82596·
performs a write cycle where the P bit is set to one and the rest of the data remains
unchanged. The CPU is responsible for resetting it in all RBDs. The 82596 will not
check this bit before setting it.

SIZE

This 14-bit quantity indicates the size, in bytes, of the associated buffer. This quantity must be an even number. .

1-92

inter

82596CA

. ELECTRICAL AND TIMING CHARACTERISTICS

DC Characteristics,
Tc = 0·C-85·C, vcc = 5V ± 10% LE/BE have MOS levels (see VMll, VMIH).
All other signals have TTL levels (see Vll, VIH, VOL, VOH).

Symbol

Parameter

Min

Max

Units

Notes

Vil

Input Low Voltage (TTL)

-0.3

+0.8

VIH

Input High Voltage (TTL)

2.0

VCC + 0.3

VMll

Input Low Voltage (MOS)

-0.3

.' +0.8

VMIH

Input High Voltage (MOS)

3.7

VOL

Output Low Voltage (TTL)

VCll

RXC, TXC Input Low Voltage

VCIH

RXC, TXC Input High Voltage

VOH

Output High Voltage (TTL) ,

204'

III

Input Leakage Current

±15

/LA

Os VIN s Vcc

IlO

Output Leakage Current

±15

p.A

0.45

CIN

Capacitance of Input Buffer

FC = 1 MHz

COUT

Capacitance of Input/Output
Buffer

FC = 1 ~Hz

CclK

CLK Capacitance

FC = 1 MHz

Icc

Power Supply

200

rnA

At 25 MHz

Icc

Power Supply

300

rnA

At 33 MHz

Vcc

:f- 0.3

0.45

.... 0.5

0.6

3~3

"cc+ 0 .5

1-93

IOl = 4.0 rnA(1)

IOH = 0.9rnA-1 rnA(1)

< VOUT < Vcc

Intel

82596CA

AC Characteristics
82596CA INPUT/OUTPUT SYSTEM TIMINGS
Te = 0·C-85·C, Vee = 5V ±10%. These timing assume the CL on all outputs is 50 pF unless otherwise
specified. CL can be 20 pF to 120 pF however timings must be derated. All timing requirements are given in
. .
nanoseconds.

Symbol

25 MHz

Parameter
Operating Frequency

Min

Max

12.5 MHz

25 MHz

ClKPeriod

T1a

ClK Period Stability

ClK High

ClKlow

ClK Rise Time

. ,,:"<:,'

,<"{:,:;"
'1'$,":4')
':":;

ClKFaliTime

BEn, lOCK, and A2-A31 Villid Oelay ,,;C:: '

T6a

BLAST, PCHK Valid Oelay

BEn, lOCK, BLAST, A2-A31 FI~tQ.e1ay

T8
T9

W/P. and AOS Valid Oelay:<,;'j ,
W/R and AOS Float Oelay "", .
.::)

T10

00-031, OPn Write Datayalid Oel~Y.

T11

00-031, OPn W~it~l)ata Float ~1ay'

T12

HOlO Valid Oelay?

. . ',\::3

'. !?'

" ';:.::>

0.8Vt02.0V
2.0VtoO.8V

30
22

.,/3'

-,.,"<".

2.0V
0.8V

. ;~/ ;3:~"~
,

Adjacent ClK 11

3 :"
.~',

<;;)'>'

1XClK Input

80,
0.1%

Notes.

'/';

1,2

.::.""."
'}:':'

1,2

2
2

T13

CA and BREQ Setup Tirnl9

T14

CA and BREQ HOld.liqte

T15

BS16 Setup Timl3:;'/:" .

T16

BS16 Hold Time';'

T17

BROY, ~P";,s$tup Time

T18

BROY:i~Hold Time

T19

00-031\ OPn REAO Setup Time

T20

00-03t, OPn REAO Hoid Time

T21

AHOlO and HlOA Setup Time

1,2

T22

AHOlO Hold Time

1,2

T22a

HlOA Hold Time

1,2

T23

RESET Setup Time

1,2

T24

RESET Hold Time

1,2

T25

INTliNT Valid Oelay

T26

CA and BREQ, PORT Pulse Width

T27

00-031 CPU PORT Access Setup Time

T28

00-031 CPU PORT Access Hold Time

T29

PORT Setup Time

T30

PORT Hold Time

T31

BOFF Setup Time

T32

BOFF Hold Time

1
2T1 '

1-94

26
;

1,2,3

inter

82596CA

AC Characteristics (Continued)
82596CA INPUT/OUTPUT SYSTEM TIMINGS
Te = 0·C-85·C, Vee = 5V ±5%. These timing assume the CL on all outputs is 50 pF unless otherwise
specified. CL can be 20 pF to 120 pF, however timings must be derated. All timing requirements are given in
nanoseconds.

Symbol

33 MHz

Parameter
Operating Frequency

Min

Max

12.5 MHz

33 MHz

Notes
1X CLK Input

CLK Period

T1a

CLK Period Stability

CLKHigh

2.0V

CLK Low

O.BV

CLK Rise Time

0.8Vto 2.0V

CLK Fall Time

2.0Vto O.BV

BEn, LOCK, and A2-A31 Valid Delay'

T6a

BLAST. PCHK Valid Delay

BEn. LOCK. BLAST, A2-A31 Float Delay

W/R and ADS Valid Delay

W/R and ADS Float Delay

T10

DO-D31, DPn Write Data Valid Delay

T11

00-031, DPn Write Data Float Delay

T12

HOLD Valid Delay

T13

CA and BREQ Setup Time

1,2

T14

CA and BREQ Hold Time

1,2

T15

BS16 Setup Time

T16

BS16 Hold Time

T17

BROY. ROY Setup Time

T1B

BROY. ROY Hold Time

T19

00-031, OPn READ Setup Time

0.1%

Adjacent CLK A

. T20

00-D31. OPn READ Hold Time

T21

AHOLO and HLDA Setup Time

1.2

T22

AHOLD Hold Time

1.2

1-95

lme

82596CA

AC Characteristics (Continued)
82596CA INPUT/OUTPUT SYSTEM TIMINGS

CL on all outputs is 50 pF unless otherwise specified.
All timing requirements are given in nanoseconds.
Symbol

33 MHz
"/,~,,
" ;;;",,"'Min
Max

Parameter

E"~''''''

;'::;

Notes

T22a

HLOA Hold Time

T23

RESET Setup Time

T24

RESET Hold Time

T25
T27

.', !:l'..,z:~;!;r;,
CAandBRE~
00-031 CPU
:<"i) Time

T28

00-031 CPU PQF!.lZ~q~:Plold Time

T29

PORT Setup Tilfl~:'''''J:::,'[:Y

T30

PORT Hold;:,\ims'

T31

BOFF ~~'Time

T32

BOFF Hold Time

T26

, ,::;':::C'
,....:;

.....

A~~"":":

,:1:;;: "i':.

1,2

INT/INT Valid Oelay,;§';;'

1,2

2T1

1,2,3

NOTES:
1. RESET, HLDA, and CA are internally synchronized. This timing is to guarantee recognition at next clock for RESET, HLDA
and CA.
2. All set-up, hold and delay timings are at maximum frequency specification Fmax, and must be derated according to the
following equation for operation at lower frequencies:
Tderated = (Fmax/Fopr) x T
where:
Tderate = Specifies the value to derate the specification.
Fma>i = Maximum operating frequency.
Fopr ,; Actual operating frequency.
T = Specification at maximum frequency.
This calculation only provides a rough estimate for derating the frequency. For more detailed information, contact your
Intel Sales Office for the data sheet supplement.
.
3. CA pulse width need only be 1 T1 wide if the set up and hold times are met; BREQ must meet setup and hold times and
need only be 1 T1 wide.

TRANSMIT/RECEIVE CLOCK PARAMETERS
Symbol

T36

:t'l,

Parameter

,;;::J.fin

TxCCycle

T38

TxC Rise Time

T39

TxC Fall Time

T40

TxC High Time

T41

TxCLowTime

T42

TxO Rise Time

T43

TxOFaliTime

T44

TxO Transition

3('\'f

,:::::;,: .

:'F: Q~'1;o

;,;;~~:~It·

7:<0;':'

:;;;,;;;:2'

1
1

1,3

A>:;~,

Notes.
Max

,;:;;:;: . ;;,>,!
",";1,:

20 MHz

10
20

4
4
2,4

T45

he Low to~~1li'

4,6

T46

TxC Low to

ransition

2,4

T47

TxC High tolcO Transition

2,4

T48

TxC Low to TxO High (At End of Transition)

1-96

82596CA

TRANSMIT/RECEIVE CLOCK PARAMETERS (Continued)
Symbol

20 MHz

Parameter
Min

Notes
Max

RTS AND CTS PARAMETERS
T49

TxC Low to RTS Low,
Time to Activate RTS

T50

CTS Low to TxC Low, CTS Setup Time

T51

TxC Low to CTS Invalid, CTS Hold Time

T52

TxC Low to RTS High

7
25

RECEIVE CLOCK PARAMETERS
T53

RXCCycle

1,3

T54

RXC Rise Time

T55

RXCFaliTime

T56

RXC High Time

T57

RXC Low Time

RECEIVED DATA PARAMETERS
T58

RXD Setup Time

....

T59

RXD Hold Time

T60

RXD Rise Time

T61

RXD Fall Time

CRS AND CDT PARAMETERS
T62

CDTlow to TXC HIGH
External Collision Detect Setup Time

T63

fXC High to COT Inactive, COT Hold Time

T64

COT Low to Jam Start

T65

CRS Low to TXC High,
Carrier Sense Setup Time

T66

TXC High to CRS Inactive, CRS Hold Time
(Internal Collision Detect)

T67

CRS High to Jamming Start,

12
11

T68

Jamming Period

T69

CRS High to RXC High,
CRS Inactive Setup Time .

T70

RXC High to CRS High,
CRS Inactive Hold Time

1-97

lme

82596CA

TRANSMIT/RECEIVE CLOCK PARAMETERS (Continued)
Symbol

Parameter

Notes

INTERFRAME SPACING PARAMETERS
T71

Interframe Delay

EXTERNAL LOOPBACK-PIN PARAMET
T72
T73

TXC Low to L

NOTES:
1. Special MOS levels. Veil = 0.9V and Vel
2. Manchester-only.
3. Manchester. Needs 50% duty cycle. .tfa ~
4. 1 TIL load + 50 pF.
:~?
5: 1 TIL load + 100 pF.
e'~
6. NRZ only.
;~
7. Abnormal end 'of transmission-CTS expires before RTS.
8. Normal end to transmission.
9. Programmable value:
T7t "" NIFS. T36
where:, NIFS "" the IFS configuration valu~
(if NIFS is less than 12 then NIFS is forced to 12).
10. Programmable value:
,
T64 "" (NeDF. T36) + x. T36
(If the collision occurs after the preamble)
where:
NeDF ;= the collision detect filter configuration value,
and
X"" 12,13, 14, or 15
11. T68 = 32.T~6
12. Programmable value:
T67 "" (NeSF. T36) + X. T36
where: NCSF = the Carrier Sense Filter configuration
value, and
x = 12,13,14, or 15
13. To guarantee recognition on the neXt clock.

1-98

82596CA

82596CA BUS OPERATION
The following figures show the 82596CA basic bus cycle and basic burst cycle.
Please refer to the 32-8it LAN Components Manual.

tlDlE

ClK

ADS

A31-A2
BEO-3

W/R

I
I

ROY
I

BLAST

I : \

: \

I : \

DATA

PCHK
READ

OJ
READ

WRITE

WRITE
290218-40

Figure 44. Basic 82596CA Bus Cycle

IDLE

tlDlE

ClK

ADS
A31-A2
W/R
BEO-3
ROY

BRDY

BLAST

DATA

PCHK
290218-41

Figure 45. Basic 82596CA Burst Cycle
1-99

Intel

82596CA

SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS
The measurements should be done at:
• Te

0'C-85'C, Vee

5V ±10%, C

50 pF unless otherwise specified .

• A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0" .
• Timing measurements are made at 1.5V for both logic "1" and "0".
• Rise and Fall time of inputs and outputs signals are measured between 0.8Y and 2.0V respectively unless
.
otherwise specified.
• All timings are relative to CLK crossing the 1.5V level.
• All A.C. parameters are valid only after 100 /Ls from power up.

. 2.4V
0.45V

=x:

1.5V Test Point

:x:::=
290218-18

290218-19

Figure 46. ClK Timings
Two types of timing specifications are presented below:
1. Input Timing-minimum setup and l;Iold times.
2. Output Timing8-e::X

RXO _ _.....

I-T60. T61

)(

Figure 59. Receive Data Waveforms

290218-32

(N~Z)

290218-33

Figure 60. Receive Data Waveforms (CRS)

1-104

inter

82596CA

OUTLINE DIAGRAMS
132 LEAD CERAMIC PIN GRID ARRAY PACKAGE INTEL TYPE A
SEATING
PLANE

(2)1.65 E D ?
REF.

I
IIr~::·ill!

SEATIN~
PLANE

••••••••••••• G

•••• ".e8e •••••

PIN C3

•••

:=:

cts.

e.0EH9.e.eE)(J~

U~REF.

~ c::::::D1]

\,_~I iii~

::.:::::::: -:e

r .

(2) B (ALL PINS)
0

I
----1.

SWAGGED
PIN
DETAIL

SWAGGE

(:I~L)

6:~~REF.
45°(CHA~FER

45 0 CHAMFER
(INDEX CORNER)

3 PL)

mm (inch)

BASE
PLANE

290218-34

Family: Ceramic Pin Grid Array Package
Millimeters

Symbol

Inches

Min

Max

Notes

3.56

4.57

0.76

1.27

Solid Lid

2.67

3.43

Solid Lid

,1.14

1.40

Min

Max

0.140

0.180

0.030

0.050

Solid Lid

0.105

0.135

Solid Lid

0.045

0.055

0.43

0.51

0.017

0.020

36.45

37.21

1.435

1.465

32.89

33.15

1.295

1.305

2.29

2.79

0.090

0.110

. 2.54

3.30

0.100

0.130

N
S1
ISSUE

132
1.27
IWS

132

2.54

0.050

10/12/88

1-105

0.100

Notes

intJ

82596CA

Intel Case Outline Drawings
Plastic Quad Flat Pack (PQFP)
0.025 Inch (0.635mm) Pitch
Symbol

Description

Min

Leadcount

Max

Min

Max

Min

Max

100

Min

Max

132

Min
I

Max

164

Min

Max

196

Package Height

0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170

Standoff

0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030

D,E

Terminal Dimension

0.675 0.685 0.775 0.785 0.875 0.885 1.075 1.085 1.275 1.285 1.475 1.485

01, E1

Package Body

0.547 0.553 0.647 0.653 0.747 0.753 0.947 0.953 1.147 1.153 1.347 1.353

D2,E2

Bumper Distance

0.697 0.703 0.797 0.803 0.897 0.903 1.097 1.103 1.297 1.303 1.497 1.503

D3,E3

Lead Dimension

D4,E4

Foot Radius Location 0.623 0.637 0.723 0.737 0.823 0.837 1.023 1.037 1.223 1.237 1.423 1.437

0.400 REF

Foot Length

Issue

IWS Preliminary 12/12/88

Description

0.600 REF

0.800 REF

1.000 REF

1.200 REF

0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030

Symbol

0.500 REF

INCH

Min

Leadcount

Max

Min

Max

Min

Max

100 .

Min

Max

132

Min

Max

164

Min

Max

196

Package Height

4.06

4.32

4.06

4.32

4.06

4.32

4.06

4.32

4.06

4.32 ·4.06

4.32

Standoff

0.51

0.76

0.51

0.76

0.51

0.76

0.51

0.76

0.51

0.76

D,E

Terminal Dimension

17.15 17.40 19.69 19.94 22.23 22.48 27.31 27.56 32.39 32.64 37.47 37.72

01, E1

Package Body

13.89 14.05 16.43 16.59 18.97 19.13 24.05 24.21 29.13 29.29 34.21 34.37

02, E2

Bumper Distance

17.70 17.85 20.24 20.39 22.78 22.93 27.86 28.01 32.94 33.09 38.02 38.18

D3, E3

Lead Dimension

D4,E4

Foot Radius Location 15.82 16.17 18.36 18.71 21.25 21.25 25.89 26.33 31.06 31.41 36.14 36.49

Foot Length

Issue

IWS Preliminary 12/12/88

10.16 REF

0.51

0.76

12.70 REF

0.51

0.76

15.24 REF

0.51

0.76

20.32 REF

0.51

0.76

25.40 REF

0.51

0.76

0.51

30.48 REF

0.51

0.76
mm

1-106

82596CA

2 -H- ,BASE

PLANE

I-- Al

mm (inch)
290216-35

Figure 61. Principal Dimensions and Datums

IT -~
E2

1-$-10.25 (.010)@ICIA®-B®ID®l&
1..L1.002 MM/MM CIN/IN)JA-BJ

DI __~~~I-$-~lr0~.2=5~(~.0~1~0~)@~M~I7.C~IA~®~-B~®~s~I~D®~S~l&=
I..LI .002 MM/MM (IN/IN)IA-BI

k'
&I

'.8'

u+ ""

~SEE

DETAIL M

L----=~H<6'1Innm.mn~,~)
-

1. 91

(. 075)

MAX

TYP

-$-10.25 (.010)@lcIA®-B®ID®1
..LJ.002 MM/MM (IN/IN) IDI
mm (inch)

-$-10.25 (.010)@ IcIA®-B® ID® 1&
..LI .002 MM/MM (IN/IN)IDI
290216-36

Figure 62. Molded Details

1-107

intJ

82596CA

r-11l.b35 (11.1125)1

SEE DETAIL L
4--4-1-- SEE DETAIL J

I---- D3/E3 ------l
' - - - - - D4/E4 - - - - I

mm (inch)

1 - - - - - DIE - - - 290218-37

Figure 63. Terminal Details

1$10.13 (.005)@ICIA®-B®lo®lA
0.41 (.01b)
.0 • 20 (.008)
0.20 (.008)
1L. _ _r-~

0.31 (.012)--110.20 (.008)

....

.14 (. H95)

04/E4 - - - - I

1 $10.20 (.008)@ IcIA®-B® lo®

1&\

8 DEG.
o DEG.
290218-38

mm (inch)

Detail J

Detail L
Figure 64. Typical Lead

1-108

82596CA

1.32 (.052)
1.22 (.048)
~
0.90 <'035) MIN.
2.33 (.380)
1. 93 <. 0lb)
-------D2----~

290218-39

mm (inch)
Figure 65. Detail M

REVISION HISTORY
The 82596 LAN Coprocessor data sheet version :"003 contains updates and improvements to previous versions.
1. Added Pin Cross Reference table.
2. Added Bus Cycle figures.

1-109

82596DX AND 82596SX
HIGH-PERFORMANCE 32-BIT LOCAL
AREA NETWORK COPROCESSOR

•
•

High-Performance 32-Bit Bus Master
• Interface

Performs Complete CSMA/CD Medium
Access Control (MAC) FunctionsIndependently of CPU
-IEEE 802.3 (EOC) Frame Delimiting
- HDLC Frame Delimiting

- 66-MB/s Bus Bandwidth
- 33~MHz Clock, Two Clocks .Per
Transfer
. - Bus Throttle Timers
- Transfers Data at 100% of Serial
Bandwidth
-128-Byte Receive FIFO, 64-Byte
Transmit FIFO

Supports Industry Standard LANs
-IEEE TYPE 10BASE5 (Ethernet*),
IEEE TYPE 10BASE2 (Cheapernet),
IEEE TYPE 1BASE5 (StarLAN),
and the Proposed Standards
TYPE 10BASE-T and 10BASE-F
- Proprietary CSMAlCD Networks Up
to 20 Mb/s

Management and Diagnostics
• -Network
Monitor Mode
- 32-Bit Statistical Counters
Diagnostics
• Self-Test
Configurable Initialization Root for Data
• Structures

Memory Management
• -On-Chip
Automatic Buffer Chaining
- Buffer Reclamation after Receipt of
Bad Frames; Optional Save Bad
Frames
- 32-Bit Segmented or Linear (Flat)
Memory Addressing Formats

High-Speed, 5-V, CHMOS** IV
• Technology
132-Pin Plastic Quad Flat Pack (PQFP)
• and
PGA Package

• Optimized CPU Interface

82586 Software Compatible

•

(See Packaging Spe. Order No. 231369)

- Optimized Bus Interface to Intel's
32-Bit 386TMDX and 16-Bit 386™SX
and 376TM Microprocessors
- Supports Big Endian and Little'
Endian Byte Ordering

386TM is a trademark of Intel Corporation
'Ethernet is a registered trademark of Xerox Corporation.
"CHMOS is a patented proces~ of Intel Corporation.

r-------------. . ------, ,.-------,
r-------------,
Serial
FIFO
I I
Parollel
Subsystem

Subsystem

RTS

CTS

TxC

Transmit
Bit
Machine

TxD

CRS

1
1

Corrler

Sense
Collision

COT

1
1

8
I
1
I
1 r
1
1
1

Logic

TImer

RxD
Receive

Bit
Machine

SWIIC

ReceIve
Byte
Machine

FIFO

-M-

------

jf'OI
+-

I
I

Micro
Maehlne

1
1
1

"--

Control

32-Bit DBus

-J---~

Subsystem

1 I·
1

Detect

Exponential
Backo!!

RxC

I-

Transmit
Byte
Machine

• I

. LPBK 1

32-BIIDBus

~
~

..'".
~

1 LE/BE

Doto

Interface
Unit
(DIU)

~
v

1
1 PORT
1
1

.1\
Data Bus

I~~
Bus

1
1
1
1
1
1

Interlace
Unit
(BIU)

iii1

'"'"

DMA

.1\

Control
1
1
1
1
1 Address
1
1
I Byte Enoble
1

290219-1

Figure 1. 82596DX/SX Block Diagram

1·110

October 1990
Order Number: 290219·003

82596DX/SX

82596DX AND 82596SX HIGH-PERFORMANCE
32-BIT LOCAL AREA NETWORK COPROCESSOR
CONTENTS

CONTENTS

PAGE

INTRODUCTION ....................... 1-112

SYSTEM CONTROL BLOCK (SCB) .... 1-138

PIN DESCRiPTIONS .... ............... 1-119

SCB OFFSET ADDRESS .............. 1-141
CBl Offset (Address) ................... 1-141
RFA Offset (Address) .................. 1-142

82596 AND HOST CPU
INTERACTION ...................... 1-123
82596 BUS INTERFACE ........ ....... 1-123

SCB STATISTICAL COUNTERS., ..... 1-142
Statistical Counter Operation ........... 1-142

82596 MEMORY ADDRESSiNG ....... 1-123
82596 SYSTEM MEMORY
STRUCTURE ........................ 1-125
TRANSMIT AND RECEIVE MEMORY
STRUCTURES ...................... 1-126
TRANSMITTING fRAMES ............. 1-129
RECEIVING FRAMES ................. 1-130
82596 NETWORK MANAGEMENT AND
DIAGNOSTICS ...................... 1-130
NETWORK PLANNING AND
MAINTENANCE ..................... 1-132
STATION DIAGNOSTICS AND SELFTEST ........ ........................ 1-133
82586 SOFTWARE COMPATIBILITY .. 1-133
INITIALIZING THE 82596 .............. 1-133
SYSTEM CONFIGURATION POINTER
(SCP) ................................ 1-133
Writing the Sysbus ..................... 1-134
INTERMEDIATE SYSTEM
CONFIGURATION POINTER
(ISCP) : .............................. 1-135
INITIALIZATION PROCESS ........... 1-135
CONTROLLING THE 82596DX/SX .... 1-136
82596 CPU ACCESS INTERFACE
(PORT#) ............................ 1-136
MEMORY ADDRESSING FORMATS ... 1-137
LITTLE ENDIAN AND BIG EN DIAN
BYTE ORDERING ................... 1-138
COMMAND UNIT (CU) ................. 1-138
RECEIVE UNIT (RU) ................... 1-138

ACTION COMMANDS AND
OPERATING MODES ................ 1-143
NOP ................................... 1-143 '
Individual Address Setup ...............
Configure ..............................
Multicast-Setup ........................
Transmit ...............................
Jamming Rules .........................
TOR ....................................
Dump ..................................
Diagnose ..............................

1-144

RECEIVE FRAME DESCRiPTOR ......
Simplified Memory Structure ............
Flexible Memory Structure ..............
Receive Buffer Descriptor (RBD) ....

1-160

ELECTRICAL AND TIMING
CHARACTERISTICS ................
DC Characteristics .....................
AC Characteristics .....................
82596DX Input/Output System
Timings ...........................
825.96.SX Input/Output System
Timings ...........................
Transmit/Receive Clock
Parameters ........................

1-145
1-151
1-152
1-154
1-155
1-157
1-160

1-161
1-162
1-163
1-168
1-168
1-169
1-169
1-171
1-173

82596DX/SX BUS OPERATION ....... 1-175

System InterfaceA.C. Timing
Characteristics ....................... 1-176
Input Waveforms ....................... 1-177
Serial A.C. Timing Characteristics ....... 1-179
OUTLINE DIAGRAMS ................. 1-181
REVISION HISTORY .................. 1-185

1-111

inter

82596DX/SX

INTRODUCTION
The 82596DX/SX is an intelligent, high-performance
32-bit Local Area Network coprocessor. The
82596DX/SX implements the CSMAlCD access
method and can be configured to support all existing IEEE 802.3 standards-TYPEs 10BASE5,
10BASE2, 1BASE5, and 10BROAD36. It can also be
used to implement the proposed standards. TYPE
10BASE-T and 10BASE-F. The 82596DX/SX performs high-level commands, command chaining,
and interprocessor communications via shared
memory, thus relieving the host CPU of many tasks
associated with network control. All time-critical
functions are performed independently of the CPU,
this increases network performance and efficiency.
The 82596DX/SX bus interface is optimized for Intel's 386TM OX, 386 SX and 376TM microprocessors.
The 82596DX/SX implements all IEEE 802.3 Medium Access Control and channel interface functions,
these include framing, preamble generation and
stripping, source address generation, destination address checking, short-frame detection, and automatic length-field handling. Data rates up to 20 Mb/s are
supported.
The 82596DX/SX provides a powerful host system
interface. It manages memory structures automatically, with command chaining and bidirectional data
chaining. An on-chip DMA controller manages four
channels, this allows autonomous transfer of data
blocks (buffers and frames) and relieves the CPU of
byte transfer overhead. Buffers containing errored or
collided frames can be automatically recovered without CPU intervention. The 82596DX/SX provides an
upgrade path for existing 82586 software drivers by
providing an 82586-software-compatible mode that
supports the current 82586 memory structure. The
82596DX/SX also has a Flexible memory structure
and a Simplified memory structure. The 82596DXI
SX can address up to 4 gigabytes of memory. The
82596DX/SX supports Little Endian and Big Endian
byte ordering.

The 82596DX/SX bus interface is optimized to
Intel's 386 OX, 386· SX, and 376 microprocessors, providing a bus transfer rate of up to 66 MB/s
at 33 MHz. The bus interface employs bus throttle
timers to regulate 82596DX/SX bus use. Two large,
independent FIFOs-128 bytes for Receive and 64
bytes for Transmit-tolerate long bus latencies and
provide programmable thresholds that allow the
user to optimize bus overhead for any worst-case
bus latency.
The 82596DX/SX provides a wide range of diagnostics and network management functions, these include internal and external loopback, exception condition tallies, channel activity indicators, optional
capture of all frames regardless of destination address (promiscuous mode), optional capture of
errored or collided frames, and time domain reflectometry for locating fault points on the network
cable. The statistical counters, in 32-bit segmented
and linear modes, are 32-bits each and include
CRC errors, alignment errors, overrun errors, resource errors, short frames, and received collisions. The 82596DX/SX also features a monitor
mode for network analysis. In this mode the
82596DX/SX can capture status bytes, and update
statistical counters, of frames monitored on the link
without transferring the contents of the frames to
memory. This can be done concurrently while transmitting and receiving frames destined for that station.
.
The 82596DX/SX can be used in both baseband
and broadband networks. It can be configured for
maximum network efficiency (minimum contention
overhead) with networks of any length. Its highly
flexible CSMAlCD unit supports address field
lengths of zero through six bytes-configurable to
either IEEE 802.3/Ethernet or HDLC frame delimitation. It also supports 16- or 32-bit cyclic redundancy
checks. The CRC can be transferred directly to
memory for receive,operations or dynamically inserted for transmit operations. The CSMAlCD unit
can also be configured for full duplex operation for
high throughput in point-to-point connections.
The 82596DX/SX is fabricated with Intel's reliable,
5-V, CHMOS IV technology. It is available in a 132pin PQFP or PGA package.

1-112

inter

82596DX/SX

Vee
NC
NC
NC
NC

Vss
Vee
Vss
Vee

01
02
03
04
05

82596DX
(Top View)

06
07

Vee
Vss
Vss
08
09
010
011
012
013
014
015

Vee

290219-2

Figure 2a. 82596DX PQFP Pin Configuration

1-113

82596DX/SX

as
-

(5 g
-

- 99
98

Vee
Vss
AtO
Att
At2
At3
At4
At5
At6
At7

Vss
Vee
At8

Vee
At9
A20

82596SX

A2t

(Top View)

A23

A22
A24
A25

Vss
Vee
A26

Vss
A27
A2B
A29
A3'o
A3t

RESET

Vss
Vss

290219-34

Figure 2b. 82596SX PQFP Pin Configuration

1-114

82596DX/SX

A
01

~O
015

012

Vee

PORT

HOLD

000

020

016

014

011

010

CLK2

READY

INT

022

021

017

LOCK

W/R

BREQ

026

024

019
06

METAL LID

Vss

Vee

023

HLDA

Vee

Vss

82596DX

¥ss

Vee

025

(Pin View)

BEo

Vee

Vss

027

02B

ill

Vee

¥ss

029

031

030

Vee

ffi

Vee

Vss

TxD

RxC

CTS

0
0

0
CRS

RxD

TxC

A30

A2B

A25

A23

A2l

AlB

A16

A12

A10

RESET

Vss

A29

Vee

A26

Vee

A19

Vee

A13

All

000
LEISE

A31

A27

¥ss

8E3

Vss

COT

14.

LPBK

000
06

018

¥ss
09

o
013

AZ4

Vss

A22

Vss

A2Q

A17

A15

290219-3

Figure 3a. 82596DX PGA Pin View Side

1·115

82596DX/SX

82596DXPGA Cross Reference by Pin Name
Serial
Address
Data
Control
N/C
Interface
Signal Pin No. Signal Pin No. Signal Pin No. Signal Pin No. Pin No.
N9
J2
ADS
A2
M5
COT
Do
A13
K3
M9
H3
A3
8EO
M7
CRS
A14
L1
.01
M10
G2
8E1
P5
.CTS
02
C11
L2
~
P11
G3
8E2
A5
M8
LP8K
A12
03'
L3
N11
G1
A6
8E3
P9
RTS
04
C10
N2
P12
01
8REQ
A7
P4
05
RxC
811
P1
M11
C1
8S16
A8
N1
RxO
06
812
N12
F3
A9
CA
P3
TxC
07
C12
M12
02
CLK2
J3
TxO
A11
A10
08
09 .
P13
C2
HLOA
M6
A11
L12
E3
HOLD
P2
A12
010
N13
03
INTIINT
N3
A13
011
M13
82
LE/8E
M4
A14
012
P14
\
81
LOCK
M3
A15
013
K12
C3
PORT
813
A16
014
N14
A1
READY
A17
N04
015
J12
83
RESET
M2
A18
016
K13
C4
W/R
814
A19
017
M14
A2
A20
018
H12
C5
A21
019
K14
A3
A22
020
G12
84
A23
021
F14
A4
A24
022
F12
C6
A25
023
F13
85
A26
024
014
C7
A27
025
E12
A5
026
013
88
027
-......z9
012
C8
A30
028
C14
A9
A31
029
C9
030
89
031

1-116

Vee

Vss

Pin No.
86
87
810
E2
E13
F2
G13
H2
H13
J13
K2
L13
M1
N5
N6
N7
NB
N10

Pin No.
A6
A7
A8
A10
C13
E1
E14
F1
G14
H1
H14
J1
J14
K1
L14
N5
P6
P7
P8
P10

inter
A

/
01

013

Vss

Vee

Vss

012

Vee

PORT

HOLD

014

011

010

ClK2

READY

INT

lOCK

W/R

BREQ

NC
06

METAL LID

Vss

Vee

HlOA

Vee

Vss

Vee

82596SX
(Pin View)

000
BlE

Vee

Vss

BON

Vss

Vee

RTS

Vee

Vss

TxO

RxC

CTS

RxO

TxC

A30

A28

A25

A23

A21

RESET

Vss

A29

Vee

A26

Vee

A18

A16

A12

Al0

Vee

A14

A13

All

lE/SE

A31

A27

Vss

A24

Vss

A22

Vss

A20

A17

A15

P
290219-35

Figure 3b. 82596SX PGA Pin View Side

1-117

CRS

Vee

A19

Vss

COT
14

015

lPBK
13

82596DX/SX

infef

82596DX/SX

82596SX PGA Cross Reference by Pin Name
Address
Signal

A2
A3
A4
A5
A6
A7
As
A9
AlO
A11
A12
A13
A14
A15
A16
A17
A1S
A19
A;W
A21
A22
A23
A24
A25
A26
A27
A2S
A29
A30
A31

Data

Control

Pin No. Signal Pin No.

N9
M9
M10
P11
N11
P12
M11
N12
M12
P13
L12
N13
M13
P14
K12
N14
J12
K13
M14
H12
K14
G12
F14
F12
F13
014
E12
013
012
C14

00
01
02
03
04
05
06
07
Os
09
010
011
012
013
014
015

J2
H3
G2
G3
G1
01
C1
F3
02
C2
E3
03
B2
B1
C3
A1

Serial
Interface

Signal

Pin No.

Signal

AOS
BLE
BHE
BON
BREQ
CA
CLK2
HLOA
HOLO
INT/INT
LE/BE
LOCK
PORT
ROY
RESET

M5
M7
P5
P9
P4
P3
J3
M6
P2
N3
B14
M4
M2
M3 (REAOY)
B13
N04

COT
CRS
CTS
LPBK
RTS
RxC
RxO
TxC
TxO

W/Fi.

1·118

N/C

Vee

Vss

Pin No. Pin No. Pin No. Pin No.

A13
A14
C11
A12
C10
B11
B12
C12
A11

A2
A3
A4

A5
A9
B3
B4
B5
B8
B9
C4
C5
C6
C7
C8
C9
K3
L1
L2
.L3
N2
P1

B6
B7
B10
E2
E13
F2
G13
H2
H13
J13
K2
L13
M1
N5
N6
N7
N8
N10

A6
A7
A8
A10
C13
E1
E14
F1
G14
H1
H14
J1
J14
K1
L14
N1
P6
P7
P8
P10

intJ

82596DX/SX

PIN DESCRIPTIONS
Symbol

CLK2

031-00

PQFP
Pin No.

Type

14-53

I/O

(D15-DO)

Name and Function
CLOCK. The system clock input provides the fundamental timing for
the 82596. It is internally divided by two to generate the 82596 clock.
All external timing parameters are specified in reference to the rising
edge of CLK2. For clock levels see O.C. Characteristics.
DATA BUS. The 32 Data Bus lines are bidirectional, tri·state lines that
provide the general purpose data path between the 82596 and
memory. With the 82596DX the bus can be either 16 or 32 bits wide;
this is determined by the BS 16 signal which is static. The 82596
always drives all 32 data lines during Write operations, even with a
16·bit bus. DO-D31 are floated after a Reset or when the bus is not
acquired.
These lines are inputs during a CPU Port access; in this mode the CPU
writes the next address to the 82596 through the Data lines. During
PORT commands (Relocatable SCP, Self-Test, and Dump) the
address must be aligned to a 16 byte boundary. This frees the 03-00
lines so they can be used to distinguish the commands. The following
is a summary of the decoding data.
DO

D4-D31

Function

0
0
1
1

0
1
0
1

0
0
0
0

0000
AD DR
ADDR
ADDR

Reset
Relocatable SCP
Self-Test
Dump Command

These 16 Data Bus lines are bidirectional, tri-state lines that provide
the entire data path for the 82596SX. In the 82596SX D16-D31 are
not connected (NC).
70-108

ADDRESS LINES. These 30 tri-stated Address lines output the
address bits required for memory operation. These lines are floated
after a Reset or when the bus is not acquired.

112

The 82596SX requires this additional address line to output the
address bits required for memory operation.

BE3-BEO

109-114

BYTE ENABLE. (82596DX only.) These tri-stated signals are used to
indicate which bytes are involved with the current memory access. The
number of Byte Enable signals asserted indicates the physical size of
the data being transferred (1, 2,3, or 4 bytes).
• BEO indicates DO-07
• BE1 indicates D8-D15
• BE2 indicates D16-D23
• BE3 indicates D24-D31
These lines are floated after a Reset or when the bus is not acquired.

BHE, BLE

109-114

(82596SX only.) These signals are the Byte High Enable and Byte Low
Enable signals for the 82596SX.

109

BUS ON. (82596SX only.)This signal is driven high when the a2596 is
holding the bus. This signal is tri-stated when the bus is relinquished.
BON has the same timing as the8yte Enables.

A31-A2

BON

1-119

intJ

82596DX/SX

PIN DESCRIPTIONS (Continued)
PQFP
PlnNo.

Type

W/R

120

WRITE/READ. This dual-function pin is used to distinguish Write and
Read cycles. This line is floated after a Reset or when the bus is not
acquired.

ADS

124

ADDRESS STATUS. This tri-state pin is used by the 82596 to indicate
tha~ valid bus cycle has begun and that A31-A2, BE3-BEO, and
W/R are being driven. It is asserted during t1 bus states. This line is
floated after a Reset or when the bus is not acquired.

RDY

130

LOCK

126

LOCK_ This tri-state pin is used to distinguish locked and unlocked bus
cycles. LOCK generates a semaphore handshake to the CPU. LOCK
can be active for several memory cycles, it goes active during the first
locked memory cycle (t1) and goes inactive at the last locked cycle
(t2). This line is floated after a Reset or when the bus is not acquired.
LOCK can be disabled via the sysbus byte in software.

BS16

129

BUS SIZE. This signal allows the 82596DX to work with either 16- or
32-bit bytes. This signal is static and should be tied high for 32-bit
operation or low for 16-bit operation. In Little Endian mode the DOD15 lines are driven when BS 16 is inserted, in Big Endian mode the
D16-D31 lines are driven.

HOLD

123

HOLD. The HOLD signal is active high, the 82596 uses it to request
local bus mastership. In normal operation HOLD goes inactive before
HLDA. The 82596 can be forced off the bus by deasserting HLDA or if
the bus throttle timers expire.

HLDA

118

HOLD ACKNOWLEDGE_ The HLDA signal is active high, it indicates
that bus mastership has been given to the 82596. HLDA is internally
synchronized; after HOLD is detected low, the CPU drives HLDA low.
NOTE
Do not connect HLDA to Vcc-it will cause a deadlock. A user wanting
to give the 82596 permanent access to the bus should connect HLDA
to HOLD. If HLDA goes inactive before HOLD, the 82596 will release
the bus (by deasserting HOLD) within a specified number of system
clocks.

BREQ

115

BUS REQUEST. This signal, when configured to an externally
activated mode, is used to trigger the bus throttle timers.

Symbol

Name and Function

1-120

intJ

82596DX/SX

PIN DESCRIPTIONS (Continued)
PQFP
Pin No.

Type.

Name and Function

PORT

RESET

I _

RESET. This active high, internally synchronized signal causes the
82596 to terminate current activity. The signal must be high for at least
five system clock cycles. After five system clock cycles and four TxC
clock cycles the 82596 will execute a Reset when it receives a high
RESET signal. When RESET returns to low, the 82596 waits for the
first CA signal and then begins the initialization sequence.

lE/BE

LITTLE ENDIAN/BIG ENDIAN. This dual-function pin is used to
select byte ordering. When lE/BE is high, little endian byte ordering is
used; when low, big endian byte ordering is used for data in frames
(bytes) and for control (SCB, RFD, CBl, etc.).

119

CHANNEL ATTENTION. The CPU uses this pin to force the 82596 to
begin executing memory resident Command blocks. The CA signal is
internally synchronized. The signal must be high for at least one
system clock. It is latched internally on the high to low edge and then
detected by the 82596.
The first CA after a Reset forces the 82596 into the initialization
sequence beginning at location 00FFFFF6h or an SCP address written
to the.82596 using CPU Port access. All subsequent CA signals cause
the 82596 to begin executing new command sequences from the SCB.

INT/INT

125

INTERRUPT. A high signal on this pin notifies the CPU that the 82596
is requesting an interrupt. This signal is an edge triggered interrupt
signal, and can be configured to be active high or low.

Symbol

Vee

18 Pins

Vss

' 18 Pins

POWER.

+ 5V ± 10%.

GROUND.OV.

TxD

TRANSMIT DATA. This pin transmits data to the serial link. It is high
when not transmitting.

TxC

TRANSMIT CLOCK. This signal provides the fundamental timing for
the serial subsystem. The clock is also used to transmit data
synchronously on the TxD pin. For NRZ encoding, data is transferred
to the TxD pin on the high to low clock transition. For Manchester
encoding, the transmitted bit center is aligned with the low to high
transition. Transmit clock should always be running for proper device
operation.

1-121

82596DX/SX

PIN DESCRIPTIONS (Continued)
PQFP
Pin No.

Type

Name and Function

LPBK

RxD

RECEIVE DATA. This pin receives NRZ serial data only. It must be
high when not receiving.

RxC

RECEIVE CLOCK. This signal provides timing information to the
internal shifting logic. For NRZ data the state of the RxD pin is
sampled on the high to low transition of the clock.

RTS

REQUEST TO SEND. When this signal is low the 82596 informs the
external interface that it has data to transmit. It is forced high after a
Reset or when transmission is stopped.

CTS

CLEAR TO SEND. An active-low signal that enables the 82596 to
send data. It is normally used as an interface handshake to RTS.
Asserting CTS high stops transmission. CTS is internally synchronized.
If CTS goes inactive, meeting the setup time to the TxC negative edge,
the transmission will stop and RTS will go inactive within, at most, two
TxC cycles.

CRS

CDT

COLLISION DETECT. This active-low signal informs the 82596 that a
collision has occurred. It is only used if the 82596 is configured for,
external Collision Detect. External circuitry is required for collision
detection. CDT is internally synchronized. To be accepted, the signal
must remain active for at least two serial clock cycles (for CDTF = 0).

Symbol

1-122

inter

82596DX/SX

82596 AND HOST CPU INTERACTION

• The CPU can reset the 82596 via software without disturbing the rest of the system.

The 82596DX/SX and the host CPU communicate
through shared memory. Because of its on-chip
DMA capability, the 82596 can make data block
transfers (buffers and frames) independently of the
CPU; this greatly reduces the CPU byte transfer
overhead.

• A self-test can be used for board testing; the
82596 will execute a self-test and write the results to memory.

82596 BUS INTERFACE

NOTE:
The 82596DX and 82596SX differ in their address
pin definitions and their data bus sizes. Information
in this data sheet applies to both versions unless
otherwise stated.

The 82596 is multitasking coprocessor that comprises two independent logical units-the Command
Unit (CU) and the Receive Unit (RU). The CU executes commands from shared memory. The RU handles all activities related to frame reception. The independence of the CU and RU enables the 82596 to
engage in both activities simultaneously-the CU
can fetch and execute commands from memory
while the RU is storing received frames in memory.
The CPU is only involved with this process after the
CU has executed a sequence of commands or the
RU has finished storing a sequence of frames.
The CPU and the 82596 use the hardware signals
Interrupt (INT) and Channel Attention (CA) to initiate
communication with the System Control Block
(SCB), see Figure 4. The 82596 uses INT to alert the
CPU of a change in the contents of the SCB, the
CPU uses CA to alert the 82596.

The 82596DX/SX has bus interface timings and pin
definitions that are compatible with Intel's 32-bit 386
DX, 386 SX, and 376 microprocessors. This eliminates the need for additional bus interface logic. Operating at 33 MHz, the 82596's bus bandwidth can
be as high as 66 MB/s. Since Ethernet only requires
1.25 MB/s, this leaves a considerable amount of
bandwidth for the CPU. The 82596 also has a bus
throttle to regulate its use of the bus. Two timers can
be programmed through the SCB: one controls the
maximum time the 82596 can remain on the bus, the
other controls the time the 82596 must stay off the
bus (see Figure 5). The bus throttle can be programmed to trigger internally with HLDA or externally with BREQ. These timers can restrict the 82596
HOLD activation time and improve bus utilization.

82596 MEMORY ADDRESSING
The 82596 .has a 32-bit memory address range,
which allows addressing up to four gigabytes of
memory. The 82596 has three memory addressing
modes (see Table 1).

The 82596 has a CPU Port Access state that allows
the CPU to execute certain functions without accessing memory. The 82596 PORT pin and data bus
pins are used to enable this feature. The CPU can
directly activate four operations when the 82596 is in
this state.
• Write an alternative System Configuration Pointer
(SCP). This can be used when the 82596 cannot
use the default SCP address space.
• Write a different Dump Command Pointer and execute Dump. This can be used for troubleshooting No Response problems.

1-123

• 82586 Mode. The 82596 has a 24-bit memory
address range. The System Control Block, Command List, Receive Descriptor List, and Buffer
Descriptors must reside in one 64-kB memory
segment. Transmit and Receive buffers can reside in a 24-bit address space.
• 32-Bit Segmented Mode. The 82596 has a 32bit memory address range. The System Control
Block, Command List, Receive Descriptor List,
and Buffer Descriptors must reside in one 64-kB
memory segment. Transmit and Receive buffers
can reside in a 32-bit address space.
• Linear Mode. The 82596 has a 32-bit memory
address range. Any memory structure can reside
anywhere within the 32-bit memory address
range.

inter

82596DX/SX

CHANNEL ATIENTION

CPU
INT

·1

INTERRUPT

CA
82596

:..

SHARED MEMORY
INITIALIZATION
ROOT

+
SYSTEM CONTROL
BLOCK (SCB)
"MAILBOX"

"
y

A
'I

-l

RECEIVE
FRAME
AREA

COMMAND
LIST

290219-4

Figure 4. 82596 and Host CPU Intervention

82596 Bus Use
without Bus
Throttle Timers

82596 Bus Use
with Bus Throttle
Timers

·1

T-ON

IT-OFF

IT-ONl

t1 =t2+t3

290219-5

Figure 5. Bus Throttle Timers
Table 1.82596 Memory Addressing Formats
Operation Mode
Pointer or Offset

32-Bit
Segmented

82586

Linear

ISCP ADDRESS

24·Bit Linear

32-Bit Linear

SCBADDRESS

Base (24)

Base (32)

+ Offset (16)
Base (32) + Offset (16)
Base (32) + Offset(16)
Base (32) + Offset (16)
Base (32) + Offset (16)
Base (32) + Offset (16)

32-Bit Linear

Tx Buffer Descriptors

+ Offset (16)
Base (24) + Offset (16)
Base (24) + Offset (16)
Base (24) + Offset (16)
Base (24) + Offset (16)
Base (24) .+ Offset (16)

Rx Buffers

24-Bit Linear

32-Bit Linear

Tx Buffers

24·Bit Linear

32·Bit Linear

32-Bit Linear

Command Block Pointers
Rx Frame Descriptors
Tx Frame Descriptors
Rx Buffer Descriptors

1-124

32-Bit Linear
32-Bit Linear
32-Bit Linear
32-Bit Linear
32-Bit Linear

inter

82596DX/SX

INITIALIZATION ROOT

see OHSET

BLOCK (SCB)
COMMAND LIST (eL)

COt.lMAND

CO~~~:T~;IST 1--_.....;.......,
RECEIVE fRAME

I--_ _ _..J (N)

POINTER
STATISTICS
TRANSMIT
BUFFER
DESCRIPTOR
(TBO)

BUS
THROTTLE

I
I

.--------_.
I

T
RECEIVE FRAME AREA (RFA)

' - -_ _- - ' (N)

' - - _ , . - _ - ' (1)

EL::;: 1

RECEIVE
BUFFER
DESCRIPTOR

RECEIVE
BUFFER

(RBO)

L..._..-_.J (N)

T'--_--'T T,------,T T

T
I

--------------------------------------------~

290219-6

Figure 6. 82596 Shared Memory Structure

82596 SYSTEM MEMORY
STRUCTURE
The Shared Memory structure consists of four parts:
the Initialization Root, the System Control Block, the
Command List, and the Receive Frame Area (see
Figure 6).
The Initialization Root is in an established location
known to the host CPU and the 82596 (OOFFFFF6h).
However, the CPU can establish the Initialization
Root in another location by using the CPU Port access. This root is accessed during initialization, and
points to the System Control Block.

The System Control Block serves as a bidirectional
mail drop for the host CPU and the 82596 CU and
RU. It is the central point through which the CPU and
the 82596 exchange control and status information.
The SCB has two areas. The first contains instructions from the CPU to the 82596. These include:
control of the CU and RU (Start, Abort, Suspend,
and Resume), a pointer to the list of CU commands,
a pointer to the Receive Frame Area, a set of Interrupt Acknowledge bits, and the T·ON and T-OFF
timers for the bus throttle. The second area contains
status information the 82596 is sending to the CPU.
Such as, the CU and RU states (Idle, Active

1-125

Iniei

82596DX/SX

Ready, Suspended, No Receive Resources, etc.), interrupt bits (Command Completed, Frame Received,
CU Not Ready, and RU Not Ready), and statistical
counters.

will only occupy one Frame Descriptor. After receiving thi~ frame the 82596 sets the next Free Frame
Descriptor RBD pointer to the next Free RBD. Figure
7C shows the RFA after receiving a second frame.
In this example the second frame occupies only one
Receive Buffer and one RFD. The 82596 again sets
the RBD pointer. Thi's process is repeated again in
Figure 7D, showing the reception of another frame
using one Receive Buffer; in this example there is an
extra Frame Descriptor.
'

The Command List functions as program for the
CU; individual commands are placed in memory
units called Command Blocks (CBs). These CBs
contain, the parameters and status .of specific highlevel commands called Action Commands; e.g.,
Transmit or Configure.
'

TRANSMIT AND RECEIVE MEMORY
STRUCTURES

Transmit causes the 82596 to transmit a frame. The
Transmit CB contains the destination address, the
length field, and a pointer to a list of linked buffers
holding the frame that is to be constructed from several buffers scattered throughout memory. The
Command Unit operates without CPU intervention;
the DMAfor each buffer, and the prefetching of references to new buffers, is performed in parallel. The
CPU is notified only after a transmission is complete.

There are three memory structures for reception and
transmission. The 82586 memory structure, the
Flexible meniory structure, and the Simplified memory structure. The 82586 mode is selected by configuring the 82596 during initialization. In this mode all
the 82596 memory structures are compatible with
the 82586 memory structures ..

The Receive Frame Area is a list of Free Frame Descriptors (descriptors not yet used) and a list of userprepared buffers. Frames arrive at the 82596 unsolicited; the 82596 must always be ready to receive
and store them in the Free Frame Area. The Receive Unit fills the buffers when it receives frames,
and reformats the Free Buffer List into receivedframe structures. The frame structure is, for all practical purposes, identical to the format of the frame to
be transmitted. The first Frame descriptor is referenced by the SCB. Unless the 82596 is configured
to Save Bad Frames, the frame descriptor, and the
associated buffer descriptor, which is wasted when
a bad frame is received, are automatically reclaimed
and returned to the Free Buffer List.

When the, 82596 is not configured to the 82586.
mode, the other two memory structures, Simplified
and Flexible, are available for transmitting and receiving. These structures can be selected on ,a
frame~by-frame basis by setting the S/F bit in the
Transmit Command and the Receive Frame Descriptor (see Figures 29, 30, 41, and 42). The Simplified memory structure offers a simple structure for
ease of programming (see Figure 8). All information
about a frame is contained in one structure; for example, during reception the RFD and data field are
contained in one structure.

Receive buffer chaining (storing incoming.frames in
a linked buffer list) significantly improves memory
utilization. Without buffer chaining,·the user must allocate consecutive blocks of memory, each capable
of containing a maximum frame (for Ethernet, 1518
bytes). Since an average frame is about 200 bytes,
this is very inefficient. With buffer chaining, the user
can allocate small buffers and the 82596, will only
use those that are needed.
Figure 7 A-D illustrates how the 82596 uses the
Receive Frame Area. Figure 7A shows an unused
Receive Frame Area composed of Free Frame Descriptors and Free Receive Buffers prepared by the
user. The SCBpoints to the first Frame Descriptor of
the Frame Descriptor List. Figure 7B shows the
same Receive Frame Area after receiving one
frame. This first frame occupies two Receive Buffers
and one Frame Descriptor-a valid received frame'

The Flexible memory structure (see Figure 9) has a
control field that allows the programmer to specify
the amount of receive data the RFD will contain for
receive operations and the amount of transmit data
the Transmit Command Block will contain for tranS"
mit operations. For example, when the control field
in the RFD is set to 20 bytes during a reception, the
first 20 bytes of the data field are stored in the RFD
(6 Bytes of Destination Address, 6 Bytes of Source
Address, 2 Bytes of Length Fi~ld, and 6 Bytes of
Data), and the remainder of the data field is stored in
the Receive Data Buffers. This is useful for capturing
frame headers when header infOrmation is con,tained in the data field. The header information can
then be automatically stored in the RFD partitioned
from the Receive Data Buffer.
The control field can also be used for the Transmit
Command when the Flexible memory structure is
used. The quantity of data field bytes to be transmitted from the Transmit Command Block is specified
by the variable control field.

1-126

infef

82596DX/SX

",""

""iil
~

290219-7

Figure 7. Frame Reception in the RFA

1·127

1"'eI

82596DX/SX

SCB
STATUS

TO COMMAND LIST

••

FD
POINTER

FDI

FD2

STATUS

STATISTICS

I
I
I

BUS
THROTILE

RECEIVE FRAME AREA

._-----_.
VARIABLE
DATA
FIELD

FD3

-lJ

-r

FD4

-s:

STATUS

EMPTY

RECEIVE
FRAME
DESCRIPTORS

:44--------

~ RECEIVE FRAME LIST - -......

..,

FREE FRAME LIST ---------t~

290219-8

Figure 8. Simplified Memory Structure
SCB

TO COMMAND LIST

STATUS

tit

FD
POINTER

I
I
I

BUS
THROTILE

r--

I
I
I

._----- ..

STATUS

EMPTY

RBD'

RBD3

RBD4

RBD5

--lr -LJ -r:
l-

VARIABLE
DATA
FIELD

RECEIVE
BUFFERS

STATUS

I
I
I
I
I

CONTROL
FIELD

RECEIVE
FRAME
DESCRIPTORS

RECEIVE
BUFFER
DESCRIPTORS

FD4

STATUS

STATISTICS

FD3

FD2

STATUS

-I

RBD2

•

RECEIVE FRAME ARE.A

,
FD,

-lr -it -f -Y -r:

J-

DATA
FIELD

EMPTY

'---

BUFFER,

BUFFER 2

BUFFER 3

BUFFER 4

, . - - RECEIVE FRAME LIST

----I.~::~~r--------

BUFFER 5

FREE FRAME LIST - - - - - - - -••::

290219-9

Figure 9. Flexible Memory Structure

1-128

82596DX/SX

frame check sequence field has been transmitted. In
EOC mode the 82596 can be configured to extend
short frames by adding pad bytes (7Eh) during transmission, according to the length field. In HOLC mode
the 82596 will generate the 01111110 flag for the
start and end frame delimiters, and do standard bit
stuffing and stripping. Furthermore, the 82596 can
be configured to pad frames shorter than the specified minimum frame length by appending the appropriate number of flags to the end of the frame.

TRANSMITTING FRAMES
The 82596 executes high-level Action Commands
from the Command List in system memory. Action
Commands are fetched and executed in parallel with
the host CPU operation, thereby significantly improving system performance. The format of the Action
Commands is shown in Figure 10. Figure 28 shows
the 82586 mode, and Figures 29 and 30 shows the
command formats of the Linear and 32-bit Segmented modes.
A single Transmit command contains, as part of the
command-specific parameters, the destination address and length field of the transmitted frame and a
pointer to buffer area in memory containing the data
portion of the frame. The data field is contained in a
memory data structure consisting of a buffer descriptor (BO) and a data buffer-or a linked list of
buffer descriptors and buffers-as shown iri Figure
11.

When a collision occurs, the 82596 manages the
jam, random wait, and retry processes, reinitializing
DMA pointers without CPU intervention. Multiple
frames can be sent by linking the appropriate number of Transmit commands together. This is particularly useful when transmitting a message larger than
the maximum frame size (1518 bytes for Ethernet).

Multiple data buffers can be chained together using
the BOs. Thus, a frame with a long data field can be
transmitted using several (shorter) data buffers
chained together. This chaining technique allows the
system designer to develop efficient buffer management.
The 82596 automatically generates the preamble
(alternating 1s and Os) and start frame delimiter,
fetches the destination address and length field from
the Transmit command, inserts its unique address
as the source address, fetches the data field specified by the Transmit command, and computes and
appends the CRC to the end of the frame (see Figure 12). In the Linear and 32-bit Segmented mode
the CRC can be optionally inserted on a frame-byframe basis by setting the NC bit in the Transmit
Command Block (see Figures 29 and 30).
The 82596 can be configured to generate two types
of start and end frame delimiters-End of Carrier
(EOG) or HOLC. In EOC mode the start frame delimiter is 10101011 and the end frame delimiter is indicated by the lack of a signal after the last bit of the

1-129

CONTROL
FIELDS

I COMMAND STATUS
I COMMAND

LINK FIELD
•
(POINTER TO NEXT COMMAND)

f-+

NEXT
COMMAND

PARAMETER FIELD
(COMMAND-SPECIFIC
PARAMETERS)
290219-10

Figure 10. Action Command Format

TRANSMIT BD
ACTUAL COUNT
LINK FIELD

•

DB ADDRESS.
(24 BITS)

~ NEXT BUFFER DES CRIPTOR

f-+

DATA
BUFFER
(DB)
290219-11

Figure 11. Data Buffer Descriptor and
Data Buffer Structure

Intel
PREAMBLE

82596DX/SX

START
FRAME
DELIMITER

DESTINATION
ADDRESS

LENGTH
FIELD

SOURCE
ADDRESS

DATA
FIELD

FRAME
CHECK
SEQUENCE

END
FRAME
DELIMITER

Figure 12. Frame Format

frame. The 82596 will continue to receive frames
without CPU help as long as Receive Frame Descriptors and Data Buffers are available.

RECEIVING FRAMES
To reduce CPU overhead, the 82596 is designed to
receive frames without CPU supervision. The host
CPU first sets aside an adequate receive buffer
space and then enables the 82596 Receive Unit.
Once enabled, the RU watches for arriving frames
and automatically stores them in the Receive Frame
Area (RFA). The RFA contains Receive Frame Descriptors, Receive Buffer Descriptors, and Data Buffers (see Figure 13). The individual Receive Frame
Descriptors make up a Receive Descriptor List
(RDL) used by the 82596 to store the destination
and source addresses, the length field, and the
status of each frame received (see Figure 14).

Once enabled, the 82596 checks each passing
frame for an address match. The 82596 will recognize its own unique address, one or more multicast
addresses, or the broadcast address. If a match is
found the 82596 stores the destination and source
addresses and the length field in the next available
RFD. It then begins filling. the next available Data
Buffer on the FBL, which is pointed to by the current
RFD, with the data portion of the incoming frame. As
one Data Buffer is filled, the 82596 automatically
fetches the next DB on the FBL until the entire frame
is received. This buffer chaining technique is particu·
larly memory efficient because it allows the system
designer to set aside buffers to fit frames much
shorter than the maximum allowable frame length. If
AL-LOC = 1, or if the flexible memory structure is
used, the addresses and length field can be placed
in the receive buffer.
Once the entire frame is received without error, the
82596 does the following housekeeping tasks.
• The actual count field of the last Buffer Descriptor used to hold the frame just received isupdated with the number of bytes stored in the associated Data Buffer.

•
•
•
•

Heartbe~t Indicator. This indicates the presence
of a heartbeat during the last Interframe Spacing
(IFS) after transmission.

When configured to Save Bad Frames the 82596
checks each incoming frame and reports the following errors.
• CRC error. Incorrect CRC in a properly aligned
frame.
• Alignment error. Incorrect CRC in a misaligned
frame.

• The next available Receive Frame Descriptor is
fetched.
• The address of the next available Buffer Descriptor is written to the next available Receive Frame
Descriptor.
• A frame received interrupt status bit is posted in
the SCB.
• An interrupt is sent to the CPU.
If a frame error occurs, for example a CRC error, the
82596 automatically reinitializes its DMA pointers
and reclaims any data buffers containing the bad
1-130

• Frame too short. The frame is shorter than the
value configured for minimum frame length.
• Overrun. Part of the frame was not placed in
memory because the system bus did not keep up
with incoming data.
• Out of buffer. Part of the frame was discarded
because of insufficient memory storage space.
• Receive collision. A collision was detected during
reception:
• Length error. A frame not matching the. frame
length parameter was detected.

infef

82596DX/SX

.RECEIVER FRAIAE AREA (RFA)

r-,------

FD
FREE BUFFER LIST (FBL)

RECEIVE
BUFFER
DESCRIPTOR(RBD)

RBD

DATA
BUFFER (DB)

RBD

------------------------------------------------~-~
290219-12
Figure 13. Receive Frame Area Diagram

RECEIVE FRAIAE STATUS
LINK FIELD
BUFFER DESCRIPTOR
LINK FIELD

NEXT RECEIVE
• -+ FRAIAE
DESCRIPTOR
BUFFER
DESCRIPTOR
• -+

DESTINATION ADDRESS
SOURCE ADDRESS
LENGTH FIELD
290219-13

Figure 14. Receive Frame Descriptor

1·131

82596DX/SX

allocated for specific number of receive data bytes.
The 82596 will receive all frames and put them in the
RFD. Frames that exceed the available space in the
RFD will be truncated, the status will be updated,
and the 82596 will retrieve the next RFD. This allows
the user to capture the initial data bytes of each
frame (for instance, the header) and discard the remainder of the frame.

NETWORK PLANNING AND
MAINTENANCE
To properly plan, operate, and maintain a communication network, the network management entity
must accumulate information on network behavior.
The 82596 provides a rich set of network-wide diagnostics that can serve as the basis for a network
management entity.

The 82596 also has a monitor mode for network
analysis. During normal operation the receive function enables the 82596 to receive frames which pass
address filtering. These frames must have the Start
of Frame Delimiter (SFD) field and must be longer
than the absolute minimum frame length of 5 bytes
(6 bytes in case of Multicast address filtering). Contents and status of the received frames are transferred to memory. The monitor function enables the
82596 to simply evaluate the incoming frames. The
82596 can monitor the frames that pass or do not
pass the address filtering. It can also monitorframes
which do not have the SFD fields. The 82596 can be
configured to only keep statistical information about
monitor frames. Three options are available in the
Monitor mode. These modes are selectable by the
two monitor mode configuration bits available in the
configuration command.

Information on network activity is provided in the
status of each frame transmitted; The 82596 reports
the following activity indicators after each frame.
• Number of collisions. The number of collisions
the 82596 experienced while attempting to transmit the frame.
• Deferred transmission. During the first transmission attempt the 82596 had to defer to traffic on
, the link.
The 82596 updates its 32-bit statistical counters after each received frame that both passes address
filtering and is longer than the Minimum Frame
Length configuration parameter. The 82596 reports
the following statistics.
• CRC errors. The number of well-aligned frames
that experienced a CRC error.

• Alignment errors. The number of misaligned
frames that experienced a CRC error.
• No resources. The number of frames that were
discarded because of insufficient resources for
reception.
• Overrun errors. The number of frames that were
not completely stored in memory because the
system bus did not keep up with incoming data.
• Receive Collision counter. The number of collisions detected during receive.
• Short Frame counter. The number of frames that
were discarded because they were shorter than
the configured minimum frame length.
The 82596 can be configured to Promiscuous mode.
In this mode it captures all frames transmitted on the
network without checking the Destination Address.
This is useful when implementing a monitoring station to capture all frames for analysis.
A useful method of capturing frame headers is to
use the Simplified memory mode, configure the
82596 to Save Bad Frames, and configure the
82596 to Promiscuous mode with space in the RFD

When the second option is selected, the receive
function is completely disabled. The 82596 monitors
only those frames that pass address filterings and
meet the minimum frame length requirement. When
this option is used the 82596 updates six counters:
CRC errors, alignment errors, total frames (good and
bad), short frames, collisions detected, and total
good frames.
When the third option is selected, the receive function is completely disabled. The 82596 monitors all
frames, including frames that do not have a Start
Frame Delimiter. When this option is used the 82596
updates six counter (CRC errors, alignment errors,
total frames (good and bad), short frames, collisions
detected, and total good frames.

1-132

inter

82596DX/SX

STATION DIAGNOSTICS
AND SELF-TEST

INITIALIZING THE 82596

The 82596 provides a large set of diagnostic and
network management functions. These include internal and external loopback and time domain reflectometry for locating fault points in the network cable.
The 82596 ensures software reliability by dumping
the contents of the 82596 internal registers into system memory. The 82596 has a self-test mode that
enables it to run an internal self-test and place the
results in system memory.

82586 SOFTWARE COMPATIBILITY
The 82596 has a software-compatible state in which
all its memory structures are compatible with the
82586 memory structure. This includes all the Action
Commands, the Receive Frame Area (including the
RFD, Buffer Descriptors, and Data Buffers), the System Control Block, and the initialization procedures.
There are two minor differences between the 82596
in the 82586-Compatible memory structure and the
82586.
• When the internal and external loopback bits in
the Configure command are set to 11 the 82596
is in exti?rnal loopback and the LPBK pin is activated; in the 82586 this situation would produce
internal loopback.
• During a Dump command both the 82596 and
82586 dump the same number of bytes; however,
the data format is different.

A Reset command is issued to the 82596 to prepare
it for normal operation. The 82596 is initialized
through two data structures that are addressed by
two pointers, the System Configuration Pointer
(SCP) and the Intermediate System Configuration
Pointer (ISCP). The initialization procedure begins
when a Channel Attention signal is asserted after
RESET. The 82596 uses the address of the double
word that contains the SCP as a default00FFFFF4h. Before the CA signal is asserted this
default address can be changed to any other available address by asserting the PORT pin and providing the desired address over the 031-04 pins of the
address bus. Pins 03-00 must be 0010; Le., any
alternative address must be aligned to 16 byte
boundaries. All addresses sent to the 82596 must be
word aligned, which means that all pOinters and
memory structures must start on an even address
(AO = zero).

SYSTEM CONFIGURATION POINTER
(SCP)
The SCP contains the SYSBUS byte and the location of the next structure of the initialization process,
the ISCP. The following parameters are selected in
the SYSBUS.
• The 82596 operation mode.
• The Bus Throttle timer triggering method.
• Lock enabled.
• Interrupt polarity.
Byte ordering is determined by the LEIBE pin.
LEI BE = 1 selects little endian byte ordering and
LEIBE = 0 selects big endian byte ordering.

NOTE:
In the following, X indicates a bit not checked in
82586 mode. This bit must be set to 0 in all other
modes.

1-133

82596DX/SX

The following diagram illustrates the format of the SCPo
31

ODD WORD

16 15

xxxxxxx

X
X X X X X X X X

-x

EVEN WORD

10 0 0 0 0 0 0 010 0 0 0 0 0 0 0 OFFFFF4h

SYSBUS

X X X X 'X X

xix

A31 ................ A24 A23

X X X X X X

xix

ISCP ADDRESS

X X X X X X'X OFFFFF8h·'
AO OFFFFFCh

A31 ................ A24 are not checked in 82586 mode.
areas are not checked in 82586 mode; they must be 0 in all other modes.
X .................. X
16

23
SYSBUS

1 liNT

I I I I I I
LOCK

TRG

1.41

1.40

L : NOT CHECKED
0 0 : 82586 mode
o 1 : 32-Blt Segmented mode
1 0 : Linear mode
1 1 : Reserved

o : Internal triggering

. Interrupt polarity
o - Interrupt pin Is active
high
'1 - Interrupt pin Is active
low

of the
Bus Throttle timers
1 : external triggering of the
Bus Throttle timers
' - - - - 0 : LOCK function enabled
1 : LOCK function disabled

290219-14

ISCP ADDRESS- The physical address of the ISCP. In the 82586 mode, bits A31-A24 are considered to
be zero.
.

Figure 15. The System Configuration Pointer

Writing the Sysbus
When writing the Sysbus byte it is important to pay attention to the byte order.
• When a Little Endian processor is used, the Sysbus byte is located at byte address OOFFFFF6h (or address
n+ 2 if an alternative SCP address n was programmed) .
• When a processor using Big Endian byte ordering is used, the SYSBUS, alternative SCP, and ISCP addresses will be different.
.
• The Sysbus byte is located at OOFFFFF5h .
• If an alternative SCP address is programmed, the SYSBUS byte should be at byte address

1-134

n+ 1.

inter

82596DX/SX

INTERMEDIATE SYSTEM CONFIGURATION POINTER (lSCP)
The ISCP indicates the location of the System Control Block. Often the SCP is in ROM and the ISCP is in RAM.
The CPU loads the SCB address (or an equivalent data structure) into the ISCP and asserts CA. This Channel
Attention signal causes the 82596 to begin its initialization procedure and to get the SCB address from the
ISCP and SCPo In 82586 and 32-bit Segmented modes the SCP base address is also the base address of all
Command Blocks, Frame Descriptors, and Buffer Descriptors (but not buffers). All these data structures must
reside in one 64-kB segment; however, in Linear mode no such limitation is imposed.
The following diagram illustrates the ISCP format.
ODD WORD
31

16 15

_ _ _ _ _ _ _ _ _ _ _SCB
_ _ _._ _ _ _ _ _ _ _ _ _ _ _ _ _ AO
A 15
OFFSET

EVEN WORD
8 7

0
BUSY

_ _ _ _ _ _ _ _ _ _ _ _ _ _- L_ _ _ _ _ _ _ _ _ _ _ _ _ _

L-______________-L.A.:::2:.::.3________________s::...C:....B_B::..:A_s:...:E::..:A...co::...o::...R_E_s'-_________________
s
A_O-'

ISCP
ISCP + 4

0 0 0 0 0 0 0 - in 82586 mode
A31 ................ A24 - in all other modes

BUSY

SCB OFFSET-This 16-bit quantity specifies the offset portion of the address of the SCB.
SCB BASE

Specifies the base portion of the address of the SCB. The base of SCB is also the base of
all 82596 Command Blocks, Frame Descriptors and Buffer Descriptors. In the 82586
mode, bits A31-A24 are considered to be zero.

Figure 16. The Intermediate System Configuration Pointer-82586 and 32·81t Segmented Modes
ODD WORD
31
o 0

16 15
0

EVEN WORD
8 7

....................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 0

o
BUSY

~-------------------------------------------------'---------------~

ISCP

LA.:::3:.::.1______-"-______________.:::S.:::C.:::B:.::.A.:::B.:::S.:::0.:::L.:::UT...cE~A~0.:::0:....R:....ES::..:S"________________________A_O~ISCP+4

BUSY

Indicates that the 82596 is being initialized. The ISCP is set to 01 h by the CPU before its
first CA to the 82596. It is cleared by the 82596 after the SCB address is read.

SCB ADDRESS- This 32-bit quantity specifies the physical address of the SCB.
Figure 17. The Intermediate System Configuration Pointer-Linear Mode.

1-135

82596DX/SX

timers are essentially disabled-the T-ON value is infinite, the T-OFF value is zero. After the SCP is read, the
82596 reads the ISCP and saves the SCB address. In 82586 and 32-bit Segmented modes this address is
represented as a base address plus the offset (this base address is also the base address of all the control
blocks). In Linear mode the base address is also an absolute address. The 82596 clears BUSY, sets CX and
CNR to equal 1 in the SCB, clears the SCB command word, sends an interrupt to the CPU, and awaits another
Channel Attention signal. RESET configures the 82596 to its default state before CA is asserted.

CONTROlLING THE 82596DX/SX
The host CPU controls the 82596 with the commands, data structures, and methods described in this section.
The CPU and the 82596 communicate through shared memory structures. The 82596 contains two independent units: the Command Unit and the Receive Unit. The Command Unit executes commands from the CPU,
and the Receive Unit handles frame reception. These two units are controlled and monitored by the CPU
through a shared memory structure called the System Control Block (SCB). The CPU and the 82596 use the
CA and INT signals to communicate with the SCB.

82596 CPU ACCESS INTERFACE (PORT)
The 82596 has a CPU access interface that allows the host CPU to do four things.
• Write an alternative System Configuration Pointer address.
• Write an alternative Dump. area pointer ·and perform Dump.
• Execute a software reset.
• Execute a self-test.
The following events initiate the CPU access state.
• Presence of an address on the 031- 04 data bus pins.
• The 03-00 pins are used to select one of the four functions.
• The PORT input pin is asserted, as in a regular write cycle.
NOTE
The SCP Dump and Self-Test addresses must be 16-byte aligned.

The 82596 requires two 16-bit write cycles for a port command. The first write holds the internal machines and
reads the first 16 bits, the second activates the PORT command and reads the second 16 bits.
The PORT Reset is useful when only the 82596 needs to be reset. The CPU must wait for 1a-system and 5-serial clocks before issuing another CA to the 82596; this new CA begins a new initialization process.
The Dump function is useful for troubleshooting No Response problems. If the chip is in a No Response state,
the PORT Dump operation can be executed and a PORT Reset can be used to reinitialize the 82596 without
disturbing the rest of the system.
The Self-Test function can be used for board testing; the 82596 will execute a self-test and write the results to
memory.
Table 2. PORT Function Selection
031 .................................. 04 .......... , ....... , ......... . 00

Addresses and Results

Function

Reset

A31

Don't Care

Self-Test

A31

Self-Test Results Address

SCP

A31

Alternative SCP Address

Dump

A31

Dump Area Pointer

1-136

inter

82596DX/SX

MEMORY ADDRESSING FORMATS
The 82596 accesses memory by 32-bit addresses. There are two types of 32-bit addresses: linear and segmented. The type of address used depends on the 82596 operating mode and the type of memory structure it
is addressing. The 82596 has three operating modes.
• 82586 Mode
• A Linear address is a single 24-bit entity. Address pins A31-A24 are always zero.
• A Segmented address uses a 24~bit base and a 16-bit offset.
• 32-bit Segmented Mode
• A Linear address is a single 32-bit entity.
• A Segmented address uses a 32-bit base and a 16-bit offset.
NOTE
In the previous two memory addressing modes, each command header (CB, TBD, RFD, RBD, and SCB)
must wholly reside within one segment. If the 82596 encounters a memory structure that does not follow this
restriction, the 82596 will fetch the next contiguous location in memory (beyond the segment).

• Linear Mode
• A Linear address is a single 32-bit entity.
• There are no Segmented addresses.
Linear addresses are primarily used to address transmit and receive data buffers. In the 82586 and 32-bit
Segmented modes, segmented addresses (base plus offset) are used for all Command Blocks, Buffer Descriptors, Frame Descriptors, and System Control Blocks. When using Segmented addresses, only the offset
portion of the entity being addressed is specified in the block. The base for all offsets is the same-that of the
SCB.

1-137

inter

82596DX/SX

LITTLE ENDIAN AND BIG ENDIAN BYTE ORDERING
The 82596 supports both Little Endian and Big Endian byte ordering for its memory structures.
The 82596 supports Big Endian byte ordering for word and byte entities. Dword entities are not supported with
Big Endian byte ordering. This results in slightly different 82596 memory structures for Big Endian operation.
These structures are defined in the 32-Bit LAN Components User's Manual.
NOTE
All 82596 memory entities must be word or dword aligned.

An example of a double word entity is a frame descriptor command/status dword, whereas the raw data of the
frame are byte entities. Both 32- and 16-bit buses are supported. When a 16-bit bus is used with -Big Endian
memory organization, data lines D15-DO are used. The 82596 has an internal crossover that handles these
swap operations.

• Suspended. The CU is not executing a command; however, it is associated with a CB on the list. The
suspend state can only be reached if the CPU forces it through theSCB or sets the suspend bit in the RFD.
• Active. The CU is executing an Action Command and pointing to its CB.

The CPU can affect CU operation in two ways: by.issuing a CU Control Command or by setting bits in the
Command word of the Action Command.

RECEIVE UNIT (RU)
The Receive Unit is the logical unit that receives frames and stores them in memory. The RU is modeled as a
logical machine that takes, at any given time, one of the following states.
• Idle. The RU has no memory resources and is discarding incoming frames. This is the initial state.
• No Resources. The RU has no memory resources and is discarding incoming frames. This state differs
from Idle in that the RU accumulates statistics on the number of discarded frames.
• Suspended. The RU has memory available for storing frames, but is discarding them. The suspend state
can only be reached if the CPU forces it through the SCB or sets the suspend bit in the RFD.

• Ready. The RU has memory available and is storing incoming frames.
The CPU can affect RU operation in three ways: by issuing an RU Control Command, by setting bits in the
Frame Descriptor Command word of the frame being received, or by setting the El bit of the current buffer's
Buffer Descriptor.

infef

82596DX/SX

• Operation of the Bus Throttle. The SCB controls the Bus Throttle timers by providing them with new values
and sending the Load and Start timer commands. The timers can be operated in both the 32-bit Segmented
and Linear modes.
• Reception of frames by the Receive Unit (RU). The SCB controls the RU by specifying the address of the
Receive Frame Area and by starting, suspending, resuming, or aborting frame reception.
• Acknowledgment of events that cause interrupts.
• Resetting the chip.
The 82596 sends status reports to the CPU via the System Control Block. The SCB contains four types of
status reports.
• The cause of the current interrupts. These interrupts are caused by one or more of the following 82596
events.
• The Command Unit completes an Action Command that has its I bit set.
• The Receive Unit receives a frame.
• The Command Unit becomes inactive.
• The Receive Unit becomes not ready.
• The status of the Command Unit.
• The status of the Receive Unit.
• Status reports from the 82596 regarding reception of corrupted frames.
Events can be cleared only by CPU acknowledgment. If some events are not acknowledged by the ACK field
the Interrupt signal (INT) will be reissued after Channel Attention (CA) is processed. Furthermore, if a new
event occurs while an interrupt is set, the interrupt is temporarily cleared to trigger edge-triggered interrupt
controllers.
The CPU uses the Channel Attention line to cause the 82596 to examine the SCB. This signal is trailing-edge
triggered-the 82596 latches CA on the trailing edge. The latch is cleared by the 82596 before the SCB
. control command is read.

16 15

ODD WORD
ACK

1X 1 cuc 1R 1

RUC

EVEN WORD
STAT

X X X

101

CUS

10 1

RUS

0
10 0 0 0

SCB

RFAOFFSET

CBLOFFSET

SCB

ALIGNMENT ERRORS

CRC ERRORS

SCB

OVERRUN ERRORS

RESOURCE ERRORS

SCB

+4
+8
+ 12

Figure 18. SCB-82586 Mode

16 15

ODD WORD
ACK

10 1 cuc 1R 1

RUC

10 o 0 01

EVEN WORD
STAT

RFAOFFSET

101 ~US 1T 1
CBLOFFSET

CRCERRORS
ALIGNMENT ERRORS

OVERRUN ERRORS (*)
RCVCDT ERRORS (0)
SHORT FRAME ERRORS

T-OFFTIMER

··In MONITOR mode these counters change function

Figure 19. SCB-32-Bit Segmented Mode

1-139

0
10 0 0

SCB

+4
+8
SCB + 12
SCB + 16
SCB + 20
SCB + 24
SCB + 28
SCB + 32

SCB
SCB

RESOURCE ERRORS (*)

T-ONTIMER

RUS

inter

82596DX/SX

ODD WORD

31
ACK

10 1

cuc

EVEN WORD

16 15

1 R 1 RUC

STAT

10 0 0 01

1 0 1 CUS

1T 1

0
RUS

10 0 0 SCB

+4
+8
SCB + 12
SCB + 16
SCB + 20
SCB + 24
SGB + 28
SGB + 32
SGB + 36

COMMAND BLOCK ADDRESS

SCB

RECEIVE FRAME AREA ADDRESS

SCB

CRCERRORS
ALIGNMENT ERRORS
RESOURCE ERRORS (*)
OVERRUN ERRORS (*)
RCVCDT ERRORS (*)
SHORT FRAME ERRORS
T-ONTIMER
*In MONITOR mode these counters change function

T-OFFTIMER

Figure 20. SCe-Linear Mode
Command Word
16

AGK

GUG

RUC

SCB + 2

These bits specifiy the action to be performed as a result of a CA. This word is set by the CPU and cleared by
the 82596. Defined bits are:
Bit 31 ACK-CX

Acknowledges that the CU completed an Action Command.

Bit 30 ACK-FR

Acknowledges that the RU received a frame.

Bit 29 ACK-CNA

Acknowledges that the Command Unit became not active.

Bit 28 ACK-RNR

Acknowledges that the Receive Unit became not ready.

Bits 24-26 CUC

(3 bits) This field contains the command to the Command Unit. Valid values are:

o -

NOP (does not affect current state of the unit).

Start execution of the first command on the CBL. If a command is executing,
complete it before starting the new CBL. The beginning of the CBl is in CBl
OFFSET (address).

Resume the operation of the Command Unit by executing the next command.
This operation assumes that the Command Unit has been previously suspended.

Suspend execution of commands on CBl after current command is complete.

Abort current command immediately.

loads the Bus Throttle timers so they will be initialized with their new values
after the active timer (T-ON or T-OFF) reaches Terminal Count. If no timer is
active new values will be loaded immediately. This command is not valid in
82586 mode.

loads and immediately restarts the Bus Throttle timers with their new values.
This command is not valid in 82586 mode.

Reserved.

1-140

intJ

82596DX/SX

Bits 20-22 RUC

(3 bits) This field contains the command to the Receive Unit. Valid values are:

o -

Start reception of frames. The beginning of the RFA is contained in the RFA
OFFSET (address). If a frame is being received complete reception before
starting.

stat~).

Resume frame reception (only when in suspended

Suspend frame reception. If a frame is being received complete its reception
before suspending.

Abort receiver operation immediately.

5-7 Bit 23 RESET

NOP (does not alter current state of unit).

Reserved.

Reset chip (logically the same as hardware RESEn.

Status Word
15

S~AT

82586 Mode

: GUS:

: RUS:

I SGB

S~AT

RyS

: GUS:

SGB

32-Bit Segmented and Linear Modes
Indicates the status of the 82596. This word is modified only by the 82596. Defined bits are:
Bit 15 CX

- The CU finished executing a command with its I (interrupt) bit set.

Bit 14 FR

Bit 13 CNA

- The Command Unit left the Active state.

Bit 12 RNR

- The Receive Unit left the Ready state.

Bits 8-10 CUS

The RU finished receiving a frame.

(3 bits) This field contains the status of the command unit. Valid values are:

-Idle

-Active

3-7 Bits 4-7 RUS

Suspended
Not used

This field contains the status of the receive unit. Valid values are:
Oh (0000) -

Idle

1h (0001) -

Suspended

2h (0010) -

No resources. This bit indicates both nO resources due to lack of RFDs
in the RDL and no resources due to lack of RBDs in the FBL.

4h (0100) -

Ready

8h (1000) -

No more RBDs (not in the 82586 mode).

Ah (1010) -

No resources due to no more RBDs. (Not in the 82586 mode.)

No other combinations are
Bit3T

allowed~

Bus Throttle timers loaded (not in 82586 mode).

SCB OFFSET ADDRESSES
CBl Offset (Address)
In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the
first Command Block on the CBL. In' Linear mode it is a 32-bit linear address for the first Command Block on
the CBL. It is accessed only if CUC equals Start.
1-141

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82596DX/SX

RFA Offset (Address)
In 82586 and 32-bit Segmented modes this 16-bit quantity indicates the offset portion of the address for the
Receive Frame Area. In Linear mode it is a 32-bit linear address for the Receive Frame Area. It is accessed
only if RUC equals Start.

SCB STATISTICAL COUNTERS
Statistical Counter Operation
• The CPU is responsible for clearing all error counters before initializing the 82596. The 82596 updates
these counters by reading them, adding 1, and then writing them back to the SCB .
• The counters are wraparound counters. After reaching FFFFFFFFh the counters wrap around to zero.
• The 82596. updates the required counters for each frame. It is possible for more than one counter to be
updated; multiple errors will result in all affected counters being updated.
• The 82596 executes the read-counter/incrementlwrite-counter operation without relinquishing the bus
(locked operation). This is to ensure that no logical contention exists between the 82596 and the CPU due
to both attempting to write to the counters simultaneously. In the dual-port memory configuration the CPU
should not execute any write operation to a counter if LOCK is asserted.
• The counters are 32-bits wide and their behavior is fully compatible with the IEEE 802.3 standard. The
82596 supports all relevant statistics (mandatory, optional, and desired) through the status of the transmit
and receive header and directly through SCB statistics ..

CRCE~RS
This 32-bit quantity contains the number of aligned frames discarded because of a CRC error. This counter is ,
updated, if needed, regardless of the RU state.

ALNERRS
This 32-bit quantity contains the number of frames that both are misaligned (Le., where CRS deasserts on a
nonoctet boundary) and coritain a CRC error. The counter is updated, if needed, regardless of the RU state.

SHRTFRM
This 32-bit quantity contains the number of received frames shorter than the minimum frame length.
The last three counters changefunc::tion in mo~itor mode.

RSCERRS
This 32~bit quantity contains the number of good frames discarded because there were no resources to
contain them. Frames intended for a host whose RU is in the No Receive Resources state, fall into this
category. This counter is updated only if the RU is in the No Resources state. When in Moniitor mode, this
.
counter counts the total number of frames.

RCVCDT
This 32-bit quantity contains the number of collisions detected during frame reception. In Monitor mode this
counter counts the total number of good frames.

1-142

82596DX/SX

• Transmit

• Individual Address Setup

• TDR

• Configure

• Dump
• Diagnose

• MC Setup

The 82596 has three addressing modes. In the 82586 mode all the Action Commands look exactly like those
of the 82586.

• 82586 Mode. The 82596 software and memory structure is compatible with the 82586.
• 32-81t Segmented Mode. The 82596 can access the entire system memory and use the two new memory
structures-Simplified and Flexible-while still using the segmented approach. This does not require any
significant changes to existing software.
• Linear Mode. The 82596 operates in a flat, linear, 4 gigabyte memory space without segmentation. It can
also use the two new memory structures.
In the 32-bit Segmented mode there are some differences between the 82596 and 82586 action commands;
mainly in programming and activating new 82596 features. Those bits marked "don't care" in the compatible
mode are not checked; however, we strongly recommend that those bits all be zeroes; this will allow future
enchancements and extensions.
In the Linear mode all of the address offsets become 32-bit address pointers. All new 82596 features are
accessible in this mode, and all bits previously marked "don't care" must be zeroes.
The Action Commands, and all other 82596 memory structures, must begin on even byte boundaries, i.e., they
must be word aligned.

NOP
This command results in no action by the 82596 except for those performed in the normal command processing.lt is used to manipulate the CBl manipulation. The format of the NOP command is shown in Figure 21.

N0P-82586 and 32-81t Segmented Modes
EVEN WORD

ODD WORD·

X X X X X X X X X X

0
0

LINK OFFSET

AO 4

NOP-Linear Mode
16 15

ODD WORD

EVEN WORD

AO 4

Figure 21

1-143

82596DX/SX

where:
LINK POINTER

-In the 82586 or 32-bit Segmented modes this is a 16-bit offset to the next Command
Block. In the Linear mode this is the 32-bit address of the next Command Block.

If set, this bit indicates that this command block is the last on the CBL.

If set to one, suspend the CU upon completion of this CB.

If set to one, the 82596 will generate an interrupt after execution of the command is
complete. If I is not set to one, the CX bit will not be set.

CMD (bits 16-18) -

The NOP command. Value: Oh.

Bits 19-28

Reserved (zero in the 32-bit Segmented and Linear modes).

This bit indicates the execution status of the command. The CPU initially resets it to zero
when the Command Block is placed on the CBL. Following a command Completion, the
82596 will set it to one.

NOTE:
The C and B bits are modified in one operation.
OK

Indicates that the command was executed without error. If set to one no error occurred
(command executed OK). If zero an error occur.

INDIVIDUAL ADDRESS SETUP
This command is used to load the 82596 with the Individual Address. This address is used by the 82596 for
inserting the Source Address during transmission and recognizing the Destination Address during reception.
After RESET, and prior to Individual Address Setup Command execution, the 82596 assumes the Broadcast
Address is the Individual Address in all aspects, Le.:
• This will be the Individual Address Match reference .
• This will be the Source Address of a transmitted frame (for AL-LOC=O mode only).
The format of the Individual Address Setup command is shown in Figure 22.

IA Setup-82586 and 32-BitSegmented Modes .
31

ODD WORD

ELI S II I X

16 15
X

xlo

1st byte A15

INDIVIDUAL ADDRESS
5th byte

6th byte

EVEN WORD

c I B lOKI A 10

LINK OFFSET

o 0
AO 4

4th byte

3rd byte

IA Setup-Linear Mode
31

1615 _

ODD WORD

ELI S II 10

010

A31

EVEN WORD

c I B lOKI A I 0

LINK ADDRESS
4th byte

3rd byte

o 0
AO 4

INDIVIDUAL ADDRESS

1st byte

6th byte

5th byte

Figure 22
where:
LINK ADDRESS,
EL, B,C,I,S

As per standard Command Block (see the NOP command for details)

inter

82596DX/SX

Bits 19-28
- Reserved (zero in the 32-bit Segmented and Linear modes).
CMD (bits 16-18)
-' The Address Setup command. Value: 1h.
INDIVIDUAL ADDRESS - The individual address of the node, 0 to 6 bytes long.
The least significant bit of the Individual Address must be zero for Ethernet (see the Command Structure).
However, no enforcement of 0 is provided by the 82596. Thus, an Individual Address with 1 as its least
significant bit is a valid Individual Address in all aspects.
.
The default address length is 6 bytes long, as in 802.3. If a different length is used the IA Setup command
should be executed after the Configure command.
CONFIGURE

The Configure command loads the 82596 with its operating parameters. It allows changing some of the
parameters by specifying a byte count less than the maximum number of configuration bytes (12 in the 82586
mode, 16 in the 32-Bit Segmented and Linear modes). The 82596 configuration depends on its mode of
operation.
• In the 82586 mode the maximum number of configuration bytes is 12. Any number larger than 12 will be
reduced to 12 and any number less than 4 will be increased to 4.
• The additional features of the serial side are disabled in the 82586 mode.
• In both the 32-Bit Segmented and Linear modes there are four additional configuration bytes, which hold
parameters for additional 82596 features. If these parameters are not accessed, the 82596. will follow their
default values.
• For more detailed information refer to the 82596 User's Manual.
The format of the Configure command is shown in Figures 23, 24, and 25.
EVEN WORD
0
16 15
1 0 c I B lOKI A 10 0 0 0 0 0 0 0 0 0 0 o 0
AO 4
Byte 1
Byte 0
A15
LINK OFFSET
Byte
2
S
Byte 5
Byte 4
Byte 3
Byte 9
ByteS
Byte 7
Byte 6
1
Byte
10
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X X X X X
X X

ELI S II I X

ODD WORD

X X

X xlo

Figure 23. CONFIGURE-82586 Mode

ODD WORD

ELI S II 10 0 0 0 0 0 0 0 0 010
Byte 1
Byte 0
Byte 4
Byte 5
Byte 9
ByteS
Byte 13
Byte 12

0
1615
EVEN WORD
1 0 c I B lOKI A 10 0 0 0 0 0 0 0 0 0 0 o 0
LINK OFFSET
AO 4
A15
Byte 3
Byte 2
S
Byte 7
Byte 6
12
Byte 11
Byte10
16

Figure 24. CONFIGURE-;-32-Bit Segmented Mode

1-145

82596DX/SX

ODD WORD

31
ELI s i l l 0

1615
0

010

A31

EVEN WORD

o c I B lOKI

AI0

0
0

LINK ADDRESS

AO 4

Byte 3

Byte 2

Byte 1

Byte 0

Byte 7

Byte 6

ByteS

Byte 4

Byte 11

Byte 10

Byte 9

Byte 8

Byte 13

Byte 12

X X X X X X X X X X X X X X X X

LINK ADDRESS, EL,B,C,I,S

Bits 19-28
CMD (bits 16-18) -

Figure 25. CON.FIGURE-Linear Mode
As per standard Command Block (see the NOP command for details) .

Indicates that the command was abnormally terminated due to a CU Abort control com·
mand. If 1, then the command was aborted and if necessary it should be repeated. If this
bit is 0, the command was not aborted.
Reserved (zero in the 32·Bit Segmented and Linear Modes)
The CONFIGURE command. Value: 2h.

The interpretation of the fields follows:
765
L -_ P
___

432

~__X__- L_ _ _
X__J -_ _X
__- L_ _ _ _~~_ _
BTI
__
E~¢O_U_N_T_'__~:____~I

BYTE 0
BYTE CNT (Bits 0-3)

Byte Count. Number of bytes, including this one, that hold pa·
rameters to be configured.

PREFETCHED (Bit 7)

Enable the 82596 to write the prefetched bit in all prefetch
RBDs.

NOTE:
The P bit is valid only in the new memory structure modes. In 82586 mode this bit is disabled
(i.e., no prefetched mark).

BYTE 1
FIFO Limit (Bits 0-3)

FIFO:LlMIT

FIFO limit.

MONITOR # (Bits 6-7)

Receive monitor options. If the Byte Count of the configure
is less than 12 bytes then thes~ Monitor bits are
Ignored.

~ommand

DEFAULT: C8h

I SAVBF
BYTE 2
SAV BF (Bit 7)

O-Received bad frames are not saved in the memory.
1"'-Received bad frames are saved in the memory.

DEFAULT: 40h

1·146

82596DX/SX

7
LOOP BACK
MODE

BYTE

PREAMBLE LENGTH

ADDRESS LENGTH

ADR LEN (Bits 0-2)

Address length (any kind).

NO SCR ADD INS (Bit 3)

No Source Address Insertion.
In the 82586 this bit is called AL LOC.

PREAM LEN (Bits 4-5)

Preamble length.

LP BCK MODE (Bits 6-7)

Loopback mode.

DEFAULT: 26h

IBOFMETD I

LI~EAR PRIORI~Y

BYTE 4
LIN PRIO (Bits 0-2)

Linear Priority.

EXP PRIO (Bits 4-6)

Exponential Priority.

BOF METD (Bit 7)

Exponential Backoff method.

DEFAULT: OOh

7
: INTER FRA¥E SPACING :

BYTE 5
INTERFRAME SPACING

Interframe spacing.

DEFAULT: 60h

7
SLOT TI¥E - LOW

BYTE 6
SLOT TIME (L)

Slot time, low byte.

DEFAULT: OOh

7
¥AXIMUM

RE~RY NUMBE~

BYTE 7
SLOT TIME (H)
(Bits 0-2)

Slot time, high part.

RETRY NUM (Bits 4-7)

Number of transmission retries on collision.

DEFAULT: F2h

1-147

intJ

82596DX/SX

BYTE 8
PRM (Bit 0)

Promiscuous mode.

BC DIS (Bit 1)

Broadcast disable.

MANCH/NRZ (Bit 2)

Manchester or NRZ encoding. See specific timing requirements for TxC in Manchester mode.

TONO CRS (Bit 3)

Transmit on no CRS.

NOCRC INS (Bit 4)

No CRC insertion.

CRC-16/CRC-32 (Bit 5)

CRC type.

BIT STF (Bit 6)

Bit stuffing.

PAD (Bit 7)

Padding.

DEFAULT: OOh
7

I GDT SRC I

I CRSSRC I

COLLl~ION DETECT:FILTER

BYTE 9
CRSF (Bits 0-2)

Carrier Sense filter (length).

CRS SRC (Bit 3)

Carrier Sense source.

CDTF (Bits 4-6)

Collision Detect filter (length).

COT SRC (Bit 7)

Collision Detect source.

DEFAULT: OOh

7
. ~INIMUM

FR~ME LENGT~

BYTE 10
MIN FRAME LEN.

Minimum frame length.

DEFAULT: 40h
7
MC.....ALL

CDBSAC

AUTOTX

I .CRCINM

o
LNGFLD

PRECRS

BYTE 11
PRECRS (Bit 0)

Preamble until Carrier Sense

LNGFLD (Bit 1)

Length field. Enables padding at the End-of-Carrier framing
(802.3).

CRCINM (Bit 2)

Rx CRC appended to the frame in memory.

AUTOTX (Bit 3)

Auto retransmit.

CDBSAC (Bit 4)

Collision Detect by source address recognition.

MCJLL (Bit 5)

Enable to receive all MC frames.

MONITOR (Bits 6-7)

Receive monitor options.

DEFAULT: FFH

1-148

inter

82596DX/SX

DCR

FDX

DCR SLO~ ADDRESS

BYTE 12
DCR SLOT ADDRESS
(Bits 0-5)

Station index in DCR mode.

FDX (Bit 6)

Enables Full Duplex operation.

DCR (Bit 7)

Enables Deterministic collision resolution.

DEFAULT: OOh

7
qcR NUMBER:OF STATION~

BYTE 13 "
DCR NUMBER OF
STATIONS (Bits 0-5)

Number of stations in DCR mode.

MULT_IA (Bit 6)

Multiple individual address.

DIS_BOF (Bit 7)

Disable the backoff algorithm.

DEFAULT: 3Fh

1-149

inter

82596DX/SX

A reset (hardware or software) configures the 82596 according to the following defaults.

Table 4. Configuration Defaults
Parameter

•
•
•

•
•

•

,*
*

Default Value

ADDRESS LENGTH
AIL FIELD LOCATION
AUTO RETRANSMIT
BITSTUFFING/EOC
BROADCAST DISABLE
CDBSAC
COT FILTER
CDTSRC
CRC IN MEMORY
CRC-16/CRC-32
CRS FILTER
CRSSRC
OCR
OCR Slot Number
OCR Number of Stations
DISBOF
EXT LOOPBACK
EXPONENTIAL PRIORITY
EXPONENTIAL BACKOFF METHOD
FULL DUPLEX (FOX)
FIFO THRESHOLD
INT LOOPBACK
INTERFRAME SPACING
LINEAR PRIORITY
LENGTH FIELD
MIN FRAME LENGTH
MCALL
MONITOR
MANCHESTERINRZ
MULTI IA
NUMBER OF RETRIES
NO CRC INSERTION
PREFETCH BIT IN RBD
PREAMBLE LENGTH
Preamble Until CRS
PROMISCUOUS MODE
PADDING
SLOT TIME
SAVE BAD FRAME
TRANSMIT ON NO CRS

Units/Meaning

Bytes
Located in FD
Auto Retransmit Enable
EOC
Broadcast Reception Enabled
Disabled
Bit Times
External Collision Detection
CRC Not Transferred to Memory
CRC-32
"0
o Bit Times
0
External CRS
0
0
Disable OCR Protocol
OCR Disabled
0
63 Stations
Backoff Enabled
0
0
Disabled
802.3 Algorithm
"0
802.3 Algorithm
'*0
CSMAlCD Protocol (No FOX)
0
8
TX: 32 Bytes, RX: 64 Bytes
0
Disabled
*'96 Bit Times
802.3 Algorithm
*'0
Padding Disabled
*'64 Bytes
1
Disabled
11
Disabled
NRZ
0
0
Disabled
**15 Maximum Number of Retries
0
CRC Appended to Frame
Disabled (Valid Only in New Modes)
0
**7
Bytes
1
Disabled
Address Filter On
0
0
No Padding
'*512 Bit Times
0
Discards Bad Frames
0
Disabled

"6
0
1
0
0
1
0
0

NOTES:
1. This configuration setup is compatible with the IEEE 802.3 specification.
2. The Asterisk ... " signifies a new configuration parameter not available in the 82586.
3. The default value of the Auto retransmit configuration parameter is enabled (1).
4. Double Asterisk .... " signifies IEEE 802.3 requirements.

1-150

intJ

82596DX/SX

MULTICAST-SETUP
This command is used to load the 82596 with the Multicast-IDs that should be accepted. As noted previously,
the filtering done on the Multicast-IDs is not perfect and some unwanted frames may be accepted. This
command resets the current filter and reloads it with the specified Multicast-IDs. The format of the Multicastaddresses setup command is:
31
ELI S I I Lx

ODD WORD
X

16 15
X

xlo

MCCOUNT

xlxl

C I B lOKI A 10

EVEN WORD

A15

0
0

LINK OFFSET

0
AO

4th byte

1st byte
MULTICAST ArRESSES LIST

Nth byte

Figure 26. MC Setup-82586 and 32-Bit Segmented Modes
31
ELI S II 10

ODD WORD
o

A31

1615
o

010

1 I C I B lOKI A I 0

EVEN WORD
o

o .0

0
0

000

LINK ADDRESS

2nd byte

1st bytel X I X I

0
AO

MCCOUNT

MULTICAST A,DRESSES LIST
Nth byte

Figure 27. MC Setup-Linear Mode
where:
LINK ADDRESS,
EL, B,C,I,S

As per standard Command Block (see the NOP command for details)

Bits 19-28
CMD (bits 16-18)

Reserved (0 in both the 32-Bit Segmented and Linear Modes).

The MC SETUP command value: 3h.

MC-CNT

MCLlST

This 14-bit field indicates the number of bytes in the MC LIST field. The MC CNT
must be a multiple of the ADDR LEN; otherwise, the 82596 reduces the MC CNT to
the nearest AD DR LEN multiple. MC CNT = 0 implies resetting the Hash table
which is equivalent to disabling the Multicast filtering mechanism.
-

A list of Multicast Addresses to be accepted by the 82596. The least significant bit
of each MC address must be 1.

NOTE:
The list is sequential; i.e., the most significant byte of an address is immediately followed by the least significant byte of the next address.
When the 82596 is configured to recognize multiple Individual Address (Multi-IA), .
the MC-Setup command is also used to set up the Hash table for the individual
address.
The least significant bit in the first byte of each IA address must be O.
-

1-151

82596DX/SX

TRANSMIT
This command is used to transmit a frame of user data onto the serial link. The format of a Transmit command
is as follows.
31

ODD WORD

ELL S

JI IX

X X

A15

X X

16 15

X X

X X 11

TBDOFFSET

CIBI

AO A15

4th byte

EVEN WORD
STATUS BITS

I
LINK OFFSET

MAXCOLL

1st byte 8

DESTINATION ADDRESS
LENGTH FIELD

0
AO 4

6th byte

Figure 28. TRANSMIT-82586 Mode
31

ODD WORD

EL 1 S

A15

1615

00lNCIsFI1

TBDOFFSET
0

0·0

C 1B 1

AO A15
0

000

EVEN WORD
STATUS BITS

1
LINK OFFSET

0
MAXCOLL

TCBCOUNT

EOFI 0 I

DESTINATION ADDRESS

4th byte
LENGTH FIELD

0
A04

1st byte 12

6th byte

OPTIONAL DATA

Figure 29. TRANSMIT-32·Bit Segmented Mode

ODD WORD

EL I

oI 0

1615

A31

C I BI

EVEN WORD
STATUS BITS

0
MAXCOLL

0 EOFI 0 I

AO
TCBCOUNT

6th byte
OPTIONAL DATA

Figure 30. TRANSMIT-Linear Mode
COMMAND WORD

IELI S II I 0 I 0 I 0 I 0 I 0 I 0 I 0 I 0 INCIsFI1

0 12

t t
0: No CRC Insertion disable; when the
configure command is configured to
not insert the CRC during
transmission the NC has no effect.
1: No CRC Insertion enable; when the
configure command is configured to
insert the CRC during transmission
the CRC will not be inserted when
NC = 1.

0: Simplified Mode, all the Tx data is in
the Transmit Command Block. The
Transmit Buffer Descriptor Address
field is all 1s.
1: Flexible Mode. Data is in the TCB
and in a linked list of TBDs.

1-152

1st byte 16

DESTINATION ADDRESS

LENGTH FIELD

0
AO 4

TRANSMIT BUFFER DESCRIPTOR ADDRESS
0

4th byte

LINK ADDRESS

A31

0 I NC I SF 11

infef

82596DX/SX

where:
EL, B, C, I, S

As per standard Command Block (see the Nap command for details).

OK (Bit 13)
A (Bit 12)

Error free completion.
Indicates that the command was abnormally terminated due to CU Abort control
command. If 1, then the command was aborted, and if necessary it should be
repeated. If this bit is 0, the command was not aborted.

Bits 19-28

Reserved (O in the 32-bit Segmented and Linear modes).

CMD (Bits 16-18)
Status Bit 11
Status Bit 10

Status Bit 9

The transmit command: 4h.
Late collision. A late collision (a collision after the slot time is elapsed) is detected.
No Carrier Sense signal during transmission. Carrier Sense signal is monitored
from the end of Preamble transmission until the end of the Frame Check Sequence
for TONOCRS = 1 (Transmit On No Carrier Sense mode) it indicates that transmission has been executed despite a lack of CRS. For TONOCRS=O (Ethernet
mode), this bit also indicates unsuccessful transmission (transmission stopped
when lack of Carrier Sense has been detected).
Transmission unsuccessful (stopped) due to Loss cif CTS.

Status Bit 8

Status Bit 7

Transmission unsuccessful (stopped) due to DMA Underrun; i.e., the system did
not supply data for transmission.

LINK OFFSET

- Transmission Deferred, i.e., transmission was not immediate due to previous link
activity.
- Heartbeat Indicator, Indicates that after a previously performed transmission, and
before the most recently performed transmission, (Interframe Spacing) the COT
signal was monitored as active. This indicates that the Ethernet Transceiver Colli. sion Detect logic is performing properly. The Heartbeat is monitored during the
Interframe Spacing period.
- Transmission attempt was stopped because the number of collisions exceeded the
maximum allowable number of retries.
- The number of Collisions experienced during this frame. Max Col = 0 plus S5 = 1
indicates 16 collisions.
- As per standard Command Block (see the NOP for details).

TBDPOINTER

DEST ADDRESS

Status Bit 6

Status Bit 5
MAX-COL
(Bits 3-0)

In the 82586 and 32-bit Segmented modes this is the offset of the first Tx Buffer
Descriptor containing the data to be transmitted. In the Linear mode this is the 32bit address of the first Tx Buffer Descriptor on the list. If the TBD POINTER is all 1s
it indicates that no TBD is used.
Contains the Destination Address of the frame. The least significant bit (MC) indicates the address type.
MC=O: Individual Address.
MC = 1: Multicast or Broadcast Address.
If the Destination Address bits are all 1s this is a Broadcast Address.

LENGTH FIELD

TCBCOUNT

EOF Bit

The contents of this 2-byte field are user defined. In 802.3 it contains the length of
the data field. It is placed in memory in the same order it is transmitted; i.e., most
significant byte first, least significant byte second.
- This 14-bit counter indicates the number of bytes that will be transmitted from the
Transmit Command Block, starting from the third byte after the TCB COUNT field
(address n+ 12 in the 32-bit Segmented mode, N+ 16 in the Linear mode). The
TCB COUNT field can be any number of bytes (including an odd byte), this allows
the user to transmit a frame with a header having an odd number of bytes. The
TCB COUNT field is not used in the 82586 mode.
- Indicates that the whole frame is kept in the Transmit Command Block. In the
Simplified memory model it must be always asserted.

1-153

82596DX/SX

The interpretation of what is transmitted depends on the No Source Address insertion configuration bit and the
memory model being used.
NOTES

1. The Destination Address·and the Length Field are sequential of the Length Field immediately follows the
most significant byte of the Destination Address.
2. In case the 82596 is configured with No Source Address insertion bit equal to 0, the 82596 inserts its
configured Source Address in the transmitted frame.
• In the 82586 mode, or when the Simplified memory model is used, the Destination and Length fields of the
transmitted frame are taken from the Transmit Command Block.
• If the FLEXIBLE memory model is used, the Destination and Length fields of the transmitted frame can be
found either in the TCB or TBD, depending on the TCB COUNT.
3. If the 82596 is configured with the Address/Length Field Location equal to 1, the 82596 does not insert its
configured Source Address in the transmitted frame. The first (2 X Address Length) + 2 bytes of the
transmitted frame are interpreted as Destination Address, Source Address, and Length fields respectively.
The location of the first transmitted byte depends on the operational mode of the 82596:
• In the 82586 mode, it is always the first byte of the first Tx Buffer.
• In both the 32-bit Segmented and Linear modes it depends on the SF bit and TCB COUNT:
-

In the Simplified memory mode the first transmitted byte is always the third byte after the TCB COUNT
field.

In the Flexible mode, if the TCB COUNT is greater than 0 then it is the third byte after the TCB COUNT
field. If TCB COUNT equals 0 then it is first byte of the first Tx Buffer.

• Transmit frames shorter than six bytes are invalid. The transmission will be aborted (only in 82586 mode)
because of a DMA Underrun.

4. Frames which are aborted during transmission are jammed. Such an interruption of transmission can be
caused by any reason indicated by any of the status bits 8, 9, 10 and 12.
JAMMING RULES

1. Jamming will not start before completion of preamble transmission.
2. Collisions detected during. transmission of the last 11 bits will not result in jamming.
The format of a Transmit Buffer Descriptor is:

82586 Mode
31

ODD WORD
NEXT TBD OFFSET

1615
IEOFI

EVEN WORD

a
4

TRANSMIT BUFFER ADDRESS

32·Bit Segmented Mode
31

SIZE (ACT COUNT)

ODD WORD
NEXT TBD OFFSET

1615
IEOFI

EVEN WORD

a
a

SIZE (ACT COUNT)

TRANSMIT BUFFER ADDRESS

Linear Mode
31

ODD WORD

a a a a a a a

010

1615

a a a a a a aJEOF] 01

EVEN WORD
SIZE (ACT COUNT)

a
a

NEXT TBD ADDRESS

TRANSMIT BUFFER ADDRESS

Figure 31

1-154

82596DX/SX

where:
EOF

This bit indicates that this TBD is the last one associated with the frame being
transmitted. It is set by the CPU before transmit.

SIZE (ACT COUNT)

This 14-bit quantity specifies the number of bytes that hold information for the
current buffer. It is set by the CPU before transmission.

NEXT TBD ADDRESS -

In the 82586 and 32-bit Segmented modes, it is the offset of the next TBD on the
list. In the Linear mode this is the 32-bit address of the next TBD on the list. It is
meaningless if EOF = 1.

BUFFER ADDRESS

- The starting address of the memory area that contains the data to be sent. In the
82586 mode, this is a 24-bit address (A31-A24 are considered to be zero). In the
32-bit Segmented and Linear modes this is a 32-bit address.

TOR

This operation activates Time Domain Refiectometry, which is a mechanism to detect open or short circuits on
the link and their distance from the diagnosing station. The TDR command has no parameters. The TDR
transmit sequence was changed, compared to the 82586, to form a regular transmission. The TDR bit stream
is as follows.
-

Preamble

Source address

Another Source address (the TDR frame is transmitted back to the sending station,
so DEST ADR = SRC ADR).

Data field containing 7Eh patterns.

Jam Pattern, which is the inverse CRC of the transmitted frame.

Maximum length of the TDR frame is 2048 bits. If the 82596 senses collision while transmitting the TDR frame
it transmits the jam pattern and stops the transmission. The 82596 then triggers an internal timer (STC); the
timer is reset at the beginning of transmission and reset if CRS is returned. The timer measures the time
elapsed from the start of transmission until an echo is returned. The echo is indicated by Collision Detect going
active or a drop in the Carrier Sense signal. The following table lists the possible cases that the 82596 is able
to analyze.
Conditions of TOR as Interpreted by the 82596
Transceiver Type

Ethernet

Condition

Carrier Sense was inactive for 2048-bit-time
periods

Short or Open on the
Transceiver Cable

Non Ethernet

Carrier Sense signal dropped

Short on the Ethernet cable

Collision Detect went active

Open on the Ethernet cable

Open on the Serial Link

The Carrier Sense Signal did not drop or the
Collision Detect did not go active within
2048~bit time period

No Problem

An Ethernet transceiver is defined as one that returns transmitted data on the receive pair and activates the
Carrier Sense Signal while transmitting. A Non-Ethernet Transceiver is defined as one that does not do so.

1-155

inter

82596DX/SX

The format of the Time Domain Reflectometer command is:
82586 and 32-Bit Segmented Modes
31

ODD WORD

1615

X X X X X X X X X 11

LNK XVR ET
ETr] X
OK PRB OPN SRT

ODD WORD

EVEN WORD

1 clsloKlo

TIME
(11 bits)

A15

0
0

LINK OFFSET

0
AO

Linear Mode '
ELl

011

A31
o

EVEN WORD

16 15

sJ 110

1 Ie B lOKI 0

0
0

000

LINK ADDRESS
0

I LNK
I XVR
I ET I ET IX I
OK
PRB OPN SRT

0
AO

TIME
(11 bits)

Figure 32. TOR

where:
LINK ADDRESS,
EL, B,C, I,S

As per standard Command Block (see the NOP command for details).

Indicates that the command was abnormally terminated due toCU Abort control
command. If one, then the command was aborted, and if necessary it should be
repeated. If this bit is zero, the command was not aborted.

Bits 19-28

Reserved (0 in the 32-bit Segmented and Linear Modes).

CMD (Bits 16-18)

The TOR command. Value: 5h.

TIME

An 11-bit field that specifies the number of TxC cycles that elapsed before an echo
was observed. No echo is indicated by a reception consisting ,of "1 s" only. Because the network contains various elements such as transceiver links, transceivers, Ethernet, repeaters etc., the TIME is (lot exactly proportional to the problems
distance.

LNK OK (Bit 15)

No link problem identified. TIME=7FFh.

XCVR PRB (Bit 14)

Indicates a Transceiver problem. Carrier Sense was inactive for 2048-bit time period. LNK OK = O. TIME = 7FFh.

ET OPN (Bit 13)

The transmission line is not properly terminated. Collision Detect went active and
LNK OK=O.

ET SRT (Bit 12)

There is a short circuit on the transmission line. Carrier Sense Signal dropped and
LNK OK=O.

1-156

intJ

82596DX/SX

DUMP

This command causes the contents of various 82596 registers to be placed in a memory area specified by the
user. It is supplied as a 82596 self-diagnostic tool, and to provide registers of interest to the user. The format
of the DUMP command is:
82586 and 32-Bit Segmented Modes
31
IELI S II I X

ODD WORD
X

16 15
X

IA15

BUFFER OFFSET

ODD WORD

X 11

ole I B lOKI 0

EVEN WORD
0

0
0

0.0

UNKOFFSET

AoIA15

0
Aol

Linear Mode
ELI S II I X

16 15
XX

X 11

ole I B lOKI 0

EVEN WORD
0

0
0

A31

UNKADDRESS

A31

BUFFER ADDRESS

Figure 33. Dump

where:
LINK ADDRESS,
EL, B,C, I, S

As per standard Command Block (see the Nap command for details).

Indicates error free completion.

Bits 19-28

Reserved (0 in the 32-bit Segmented and Linear Modes).

CMD (Bits 16-18)

The Dump command. Value: 6h.

BUFFER POINTER

In the 82586 and 32-bit Segmented modes this is the 16-bit-offset portion of the
dump area address. In the Linear mode this is the 32-bit linear address of the dump
area.

Dump Area Information Format

• The 82596 is not Dump compatible with the 82586 because of the 32-bit internal architecture. In 82586
mode the 82596 will dump the same number of bytes as the 82586. The compatible data will be marked
with an asterisk.
• In 82586 mode the dump area is 170 bytes.
• The dump area format of the 32-bit Segmented and Linear modes is described in Figure 35.
• The size of the dump area of the 32-bit Segmented and Linear modes is 304 bytes.
• When the dump is executed by the Port command an extra word will be appended to the Dump Area. The
extra word is a copy of the Dump Area status word (containing the C, 8, and OK bits). The C and OK bits
are set when the 82596 has completed the Port Dump command.

1-157

If1IeI·

82596DX/SX

15 14 13 12 11

0
00
02
04
06
08

DMA CONTROL REGISTER'
CONFIGURE BYTES 3, 2
CONFIGURE BYTES 5, 4
CONFIGURE BYTES 7, 6
CONFIGURE BYTES 9, 8
CONFIGURE BYTES 10

I.A. BYTES 1, 0'

IA BYTES 3, 2'

IA BYTES 5, 4'

1o
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
2C
2E
30

LAST T.X. STATUS'
TX CRC BYTES 1,0'
TX CRC BYTES 3, 2'
RX CRC BYTES 1, 0'
RX CRC BYTES 3, 2'
RX TEMP MEMORY 1, 0'
RX TEMP MEMORY 3, 2'
R.X. TEMP MEMORY 5, 4'
LAST RECEIVED STATUS'
HASH REGISTER BYTES 1, 0'
HASH REGISTER BYTES 3, 2'
HASH REGISTER BYTES 5, 4'
HASH REGISTER BYTES 7, 6'
SLOT TIME COUNTER'
WAIT TIME COUNTER'
MICRO MACHINE"

NOTE:
'The 82596 is not Dump compatible
with the 82586 because of the 32-bit
internal architecture. In 82586 mode
the 82596 will dump the same number
of bytes as the 82586. The compatible data will be marked with an asterisk.
• 'These bytes are not user defined,
results may vary from Dump command to Dump command.

60 BYTES

MICRO MACHINE LFSR"
MICRO MACHINE

6C
6E

FLAG ARRAY

14 BYTES

QUEUE MEMORY"

CUPORT
8 BYTES

82
84
86
88
8A
8C

MICRO MACHINE ALU"
RESERVED"
M.M. TEMP A ROTATE R"
M.M. TEMPA"
TX DMA BYTE COUNT"
M.M. INPUT PORT ADDRESS"

M.M. OUTPUT PORT ADDRESS REGISTER"

90
92
94
96
98

RESERVED"

BUS THROTILE TIMERS

TX DMA ADDRESS"
M.M. OUTPUT PORT"
R.X. DMA BYTE COUNT"
R.U. DMA ADDRESS"

DIU CONTROL REGISTER"

RESERVED"

DMA CONTROL REGISTER"

BIU CONTROL REGISTER"

M.M. DISPATCHER REGISTER"

M.M. STATUS REGISTER"

Figure 34_ Dump Area Format-82586 Mode

1-158

82596DX/SX

31
CONFIGURE BYTES 5, 4, 3, 2

CONFIGURE BYTES 9,8,7,6

CONFIGURE BYTES 13, 12, 11, 10
I.A. BYTES 1, 0

08
X

OC
10

I.A. BYTES 5, 2
TX CRC BYTES 0, 1

LASTT.X. STATUS

RX CRC BYTES 0, 1

TX CRC BYTES 3, 2

RX TEMP MEMORY 1, 0

RX CRC BYTES 3, 2

R.X. TEMP MEMORY 5, 2
HASH REGISTERS 1,0

LAST R.X. STATUS

24
28

HASH REGISTER BYTES 5, 2
SLOT TIME COUNTER

HASH REGISTERS 7, 6

RECEIVE FRAME LENGTH

WAIT-TIME COUNTER

MICRO MACHINE"

NOTE:

MICRO MACHINE LFSR"

MICRO MACHINE"

FLAG ARRAY
28 BYTES

M.M. INPUT PORT"
16 BYTES

MICRO MACHINE ALU"

RESERVED"

M.M. TEMP A ROTATE R."

'The 82596 is not Dump compatible
with the 82586 because of the 32-bit
internal architecture. In 82586 mode
the 82596 will dump the same number
of bytes as the 82586. The compatible data will be marked with an asterisk.
.
"These bytes are not user defined,
results may vary from Dump command to Dump command.

M.M. TEMP A"

T.X. DMA BYTE COUNT"

M.M. INPUT PORT ADDRESS REGISTER"

T.X. DMAADDRESS"

M.M. OUTPUT PORT REGISTER"

100

R.X. DMA BYTE COUNT"

104

M.M. OUTPUT PORT ADDRESS REGISTER"

108

R.X. DMA ADDRESS REGISTER"

10C

RESERVED"

110

BUS THROTTLE TIMERS

114

DIU CONTROL REGISTER"

118

RESERVED"

11C

DMA CONTROL REGISTER"

120

BIU CONTROL REGISTER"

124

M.M. DISPATCHER REG."

128

M.M. STATUS REGISTER"

12C

Figure 35. Dump Area Format-Linear and 32-Bit Segmented Mode

1-159

Intel

82596DX/SX

DIAGNOSE
The Diagnose Command triggers an internal self-test procedure that checks internal 82596 hardware, which
includes:
• Exponential Backoff Random Number Generator (Linear Feedback Shift Register).
• Exponential Backoff Timeout Counter.
• Slot Time Period Counter.
• Collision Number Counter.
• Exponential Backoff Shift Register.
• Exponential Backoff Mask Logic.
• Timer Trigger Logic.
This procedure checks the operation of the Backoff block, which resides in the serial side and is not easily
controlled. The Diagnose command is performed in two phases.
The format of the 82596 Diagnose command is:
82586 and 32-Bit Segmented Modes
ODD WORD

X X X X X X X X X
X X X X X X X X X X

16 15

EVEN WORD

1 C B O O 0 0 0 0 0 000
liNK OFFSET
AO
EVEN WORD
o
o 0 O' 0 0 0 0 0 0 0 0

ODD WORD

o 0 0 0 0 0 0

Figure 36. Diagnose
where:
LINK ADDRESS; .
EL, B,C,I,S
Bits 19-28
CMD (bits 16-18)
OK (bit 13)
F(bit11)

As per standard Command Block (see the NOP command for details).

Reserved (0 in the 32-bit Segmented and Linear Modes).

The Diagnose command. Value: 7h.

Indicates error free completion.

Indicates that the self-test procedure has failed.

1-160

inter

82596DX/SX

L
roo--

SCB

RECEIVE FRAME AREA

r--

RFD 1

RFA
POINTER

STATUS

-Lr

STATUS

STATISTICS

I--

COMMAND
BLOCK
LIST

' RECEIVE
FRAME
DESCRIPTORS

EMPTY

r -Lr -W
,
,
,
,

RBDI

ACT-cnt

RECEIVE
BUFFER
DESCRIPTORS

RECEIVE
BUFFERS

EMPTY

-.J

STATUS

VALID
PARAMETERS

l 01

-r

STATUS

RBD2

lJACT-cnt

-.L

J-

VALID
DATA

BUFFER 1

RBD3

ACT-cnt

J-

RBD4

ACT-ent

J-

---- ---- ---BUFFER 2

BUFFER 3

I - RECEIVE FRAME LIST

BurFER 4

RBD5

.J
,

ACT-ent

-.L
-

BUFFER 5

FREE FRAME LIST

290219-15

Figure 37. The Receive Frame Area

Simplified Memory Structure
The first is the Simplified memory structure, the data section of the received frame is part of the RFD and is
located immediately after the Length Field. Receive Buffer Descriptors are not used with the Simplified structure, it is primarily used to make programming easier. If the length of the data area described in the Size Field
is smaller than the i~coming frame, the following happens.
1. The received frame is truncated.
2. The No Resource error counter is updated.
3. If the 82596 is configured to Save Bad Frames the RFD is not reused; otherwise, the same RFD is used to
hold the next received frame, and the only action taken regarding the truncated frame is to update the
counter.
4. The 8.2596 continues to receive the next frame in the next RFD.

1-161

intJ

82596DX/SX

Note that this sequence is very useful for monitoring. If the 82596 is configured to Save Bad Frames, to
receive in Promiscuous mode, and to use the Simplified memory structure, any programmed length of received
data can be saved in memory.
The Simplified memory structure is shown in Figure 38.

SCB
STATUS

CBl
POINTER
RFA
POINTER

TO COMMAND LIST

lei

FDI

FD2

STATUS

STATISTICS
I
I
I

BUS
THROTTLE

FD3

-Lr

I
I
I

._-----_.
RECEIVE
FRAME
DESCRIPTORS

...

RECEIVE mAME AREA

I
I
I
I
I
I
I
I

VARIABLE
DATA
FIELD

EMPTY

I
I
I
I
I
I
I
I

FD4

-r -u:

STATUS

I
I
I
I
I
I
I
I

EMPTY

STATUS

I
I
I
I
I
I
I
I

._----_. ._----_ .

••----:""--

: . - - RECEIVE FRAME LIST ---I~~:

I
I
I
I
I
I
I
I

EMPTY

I
I
I
I
I
I
I
I

._----_ .

FREE FRAME LIST --------I~~,

290219-16

Figure 38. RFA Simplified Memory Structure

Flexible Memory Structure
The second structure is the Flexible memory structure, the data structure of the received frame is stored in
both the RFD and in a linked list of Receive Buffers-Receive Buffer Descriptors. The received frame is placed
in the RFD as configured in the Size field. Any remaining data is placed in a: linked list of RBDs.
The Flexible memory structure is shown in Figure 39.

1-162

inter

82596DX/SX

Buffers on the receive side can be different lengths. The 82596 will not place more bytes into a buffer than
indicated in the associated RBD. The 82596 will fetch the next RBD before it is needed. The 82596 will
attempt to receive frames as long as the FBL is not exhausted. If there are no more buffers, the 82596
Receive Unit will enter the No Resources state. Before starting the RU, the CPU must place the FBL pointer in
the RBD pointer field of the first RFD. All remaining RBD pointer fields for subsequent RFDs should be "1s." If
the Receive Frame Descriptor and the associated Receive Buffers are not reused (e.g., the frame is properly
received or the 82596 is configured to Save Bad Frames), the 82596 writes the address of the next free RBD
to the RBD pointer field of the next RFD.
RECEIVE BUFFER DESCRiPTOR (RBD)

The RBDs are used to store received data in a flexible set of linked buffers. The portion of the frame's data
field that is outside the RFD is placed in a set of buffers chained by a sequence of RBDs. The RFD points to
the first RBD, and the last RBD is flagged with an EOF bit set to 1. Each buffer in the linked list of buffers
related to a particular frame can be any size up to 214 bytes but must be word aligned (begin on an even
numbered byte). This ensures optimum use of the memory resources while maintaining low overhead. All
buffers in a frame are filled with the received data except for the last, in which the actual count can be smaller
than the allocated buffer space.

SCB
STATUS

TO COMMAND LIST

4
FDI

RFA
POINTER

FD2

STATUS

BUS
THROTTLE

I
I
I

r--

CONTROL
FIELD

.------_.

RECEIVE
FRAME
DESCRIPTORS

FD3

STATUS

STATISTICS
I
I
I

I
I
I
I
I
I

VARIABLE
DATA
FIELD

EMPTY

Lr
r-

I
I
I
I
I
I
I
I

._----_.

FD'

STATUS
0-

I
I
I
I
I
I

I
I
I
I
I
I
I
011

,
•

EMPTY

______

RBD2

~
BUFFER I

,+-- RECEIVE

BUFFER 2

RBD4

VALID
DATA

RBD3

FRAME LIST - -____ ..

-~:'

290219-17

Figure 39. RFA Flexible Memory Structure

,,
,
,,

RBDS

BUFFER 4

._----_ .

...L

BUFFER 3

Lf:,,
I
I
I
I
I
I
I
I

...L
~: 4------I

STATUS

,,
,
,

-lJ -ur -lJ -Lr

RBDI

RECEIVE
BUFFER
DESCRIPTORS

RECEIVE
BUFFERS

,,
,

1>--

RECEIVE FRAME AREA

CBl
POINTER

inter

82596DX/SX

ODD WORD

31
ELI S

A15

1615
x

RBDOFFSET

AO A15.

4th byte

EVEN WORD

C I B lOKI 0 I

STATUS BITS

LINK OFFSET

1st byte 8

DESTINATION ADDRESS
1st byte 6th byte

SOURCE ADDRESS
6th byte

12
16

4th byte

X X X X X X X X X X X X X X X X

AO 4

LENGTH FIELD

Figure 40. Receive Frame Descrlptor-82586 Mode
31

ODD WORD

ELI sl 0

A15

o ISFI

RBDOFFSET

I BloKI

AO A15

SIZE

0101

EVEN WORD

1615
0

LINK OFFSET

8
1st byte 12

DESTINATION ADDRESS

SOURCE ADDRESS

o
AO 4

ACTUAL COUNT

EOFI FI

4th byte

STATUS BITS

1st byte 6th byte

4th byte

6th byte

LENGTH FIELD

OPTIONAL DATA AREA

Figure 41. Receive Frame Descrlptor-32-Blt Segmented Mode
ODD WORD

31
ELL S

000

A31

0 ISFI 0

6th byte

STATUS BITS

EOFI F I

12
1st byte 16
20

6th byte
4th byte

24
LENGTH FIELD

OPTIONAL DATA AREA

Figure 42. Receive Frame Descriptor~Llnear Mode

1·164

AO 8
ACTUAL COUNT

DESTINATION ADDRESS
1st byte

A04

RECEIVE BUFFER DESCRIPTOR ADDRESS
SIZE

4th byte
SOURCE ADDRESS

EVEN WORD

C I B lOKI

LINK ADDRESS

A31
0101

1615
0

infef
where:
EL

S
SF

82596DX/SX

OK (bit 13)

STATUS

1 - Flexible mode. Data is in the RFD and in a linked list of Receive Buffer Descriptors.
This bit indicates the completion of frame reception. It is set by the 82596.
This bit indicates that the 82596 is currently receiving this frame, or that the 82596
is ready to receive the frame. It is initially set to 0 by the CPU. The 82596 sets it to
1 when reception set up begins, and to 0 upon completion. The C and B bits are
set during the same operation.
Frame received successfully, without errors. RFDs with bit 13 equal to 0 are possible only if the save bad frames configuration option is selected. Otherwise all
frames with errors will be discarded, although statistics will be collected on them.
The results of the Receive operation. Defined bits are,
Bit 12:
Length error if configured to check length
Bit 11:
CRC error in an aligned frame
Bit 10:
Alignment error (CRC error in misaligned frame)
Ran out of buffer space-no resources
Bit 9:
Bit 8:
DMA Overrun failure to acquire the system bus.
Bit 7:
Frame too short.
No EOP flag (for Bit stuffing only)
Bit 6:
Bit 5:
When the SF bit equals zero, and the 82596 is configured to save bad
frames, this bit signals that the received frame was truncated. Otherwise
it is zero.
_ Bits 2-4: Zeros
Bit 1:

LINK ADDRESS
RBD POINTER
EOF
F
SIZE
ACT COUNT
MC
DESTINATION
ADDRESS
SOURCE ADDRESS

When it is zero, the destination address of the received frame matches
the IA address. When it is 1, the destination address of the received
frame does not match the individual address. For example, a multicast
address or broadcast address will set this bit to a 1.
Bit 0:
Receive collision, a collision is detected during reception.
- A 16-bit offset (32-bit address in the Linear mode) to the next Receive Frame
Descriptor. The Link Address of the last frame can be used to form a cyclical list.
- The offset (address in the Linear mode) of the first RBD containing the received
frame data. An RBD pointer of all ones indicates no RBD.
- These fields are for the Simplified and Flexible memory models. They are exactly
the same as the respective fields in the Receive Buffer Descriptor. See the next
section for detailed explanation of their functions.
- Multicast bit.
- The contents of the destination address of the receive frame. The field is 0 to 6
bytes long.
- The contents of the Source Address field of the received frame. It is 0 to 6 bytes
long.

1-165

82596DX/SX

- The contents of this 2-byte field are user defined. In 802.3 it contains the length of
. the data field. It is placed in memory in the same order it is received, i.e., most
. significant byte first, least significant byte second.

LENGTH FIELD

NOTES
1. The Destination address, Source address and Length fields are packed, Le., one field immediately follows
the next.
2. The affect of Address/Length Location (No Source Address Insertion) configuration parameter while receiving is as follows:
-

82586 Mode: The Destination address, Source address and Length field are not used, they are placed in
the RX data buffers.
32-Bit Segmented and Linear Modes: when the Simplified memory model is used, the Destination address,
Source address and Length fields reside in their respective fields in the RFD. When the Flexible memory
strucrture is used the Destination address, Source address, and Length field locations depend on the SIZE
field of the RFD. They can be placed in the RFD, in the RX data buffers, or partially in the RFD and the rest
in the RX data buffers, depending on the SIZE field value.

82586 Mode
31

ODD WORD

A15
X

X X X

X X IA23

X X

EVEN WORD

1615

NEXT RBD OFFSET

X X

X X X

0
AO 4

RECEIVE BUFFER ADDRESS

X X

ACTUAL COUNT

AolEOFI Fj

I EL I X I

SIZE

32-Blt Segmented Mode
31

ODD WORD

AOIEOFI

0
0

ACTUAL COUNT

AO 4

RECEIVE BUFFER ADDRESS

f6.31

EVEN WORD

1615

NEXT RBD OFFSET

A15

SIZE

01 EL I pi

Linear Mode
. 31

1615

ODD WORD

0 '0 0

0 00

0 p o 0

EVEN WORD

OlEOFjFJ

ACTUAL COUNT

NEXT RBD ADDRESS

A31
A31
o

0 0 0 QIELlpl

Figure 43. Receive Buffer Descriptor

1-166

0
AO 4
AO 8

RECEIVE BUFFER ADDRESS

SIZE

82596DX/SX

where:
EOF

ACT COUNT

This 14-bit quantity indicates the number of meaningful bytes in the buffer. It is
cleared by the CPU before starting the RU, and is written by the 82596 after the
associated buffer has already been used. In general, after the buffer is full, the
Actual Count value equals the size field of the same. buffer. For the last buffer of
the frame, Actual Count can be less than the buffer size.

NEXT BD ADDRESS

BUFFER ADDRESS

The offset (absolute address in the Linear mode) of the next RBD on the list. It is
meaningless if EL = 1.
The starting address of the memory area that contains the received data. In the
82586 mode, this isa 24-bit address (with pins A24-A31 = 0). In the 32-bit Segmented and Linear modes this is a 32-bit address.

EL
P

SIZE

Indicates that this is the last buffer related to the frame. It is cleared by the CPU
before starting the RU, and is written by the 82596 at the end of reception of the
frame.
Indicates that this buffer has already been used. The Actual Count has no meaning
unless the F bit equals one. This bit is cleared by the CPU before starting the RU,
and is set by the 82596 after the associated buffer has been. This bit has the same
meaning as the Complete bit in the RFD and CB.

Indicates that the buffer associated with this RBD is last in the FBL.
This bit indicates that the 82596 has already prefetched the RBDs and any change
in the RBD data will be ignored. This bit is valid only in the new 82596 memory
modes, and if this feature has been enabled during configure command. The
82596 Prefetches the RBDs in locked cycles; after prefetching the RBD the 82596
performs a write cycle where the P bit is set to one and the rest of the data remains
unchanged. The CPU is responsible for resetting it in all RBDs. The 82596 will not
check this bit before setting it.
- This 14-bit quantity indicates the size, in bytes, of the associated buffer. This quantity must be an even number.

1-167

82596DX/SX

ELECTRICAL AND TIMING CHARACTERISTICS
D.C. CHARACTERISTICS
TC = 0·C-85·C, VCC = 5V ±10% CLK2 and LEISE have MOS levels (see VMll, VMIH).
All other signals have TTL levels (see Vll, VIH, Val, VOH).
Symbol

Parameter

Min

Max

Units

VIL

Input Low Voltage (TTL)

-0.3

+0.8

VIH

Input High Voltage (TTL)

2.0

Vcc + 0.3

VMll

Input Low Voltage (MOS)

-0.3

VMIH

Input High Voltage (MOS)

3.7

Val

Output Low Voltage (TTL)

VCll

RxC, TxC Input Low Voltage

-O.~~ V

VCIH

RxC, TxC Input High Voltage

.~~

VOH

Output High Voltage (TTL)

+0.8

Notes

,,'1"V

Vcc + O.~,:.: ~.;' V

v'S.;
.~~'~""
0.45.
..'~tr

.•. ~ ...•
;:;' .4 ':~" r·

.4¥.

'",

IOL

= 4.0 mA(1)

IOH

= 0.9mA-1 mA(1)

&"~

.;\lCC . i+;.g·5
.;~i·::·;~

V
V

ILO

'?I~;'t I'~i;i:' ± 15
Input Leakage Current.;;:t.'
±15
0"",", Leakage Cum"'~· ~ r'i'

CIN
COUT
CCLK

CLK Capacitance

Icc

Power Supply

150

At 16 MHz
for the 82596SX

IcC

Power Supply

200

At 25 MHz

IcC

Power Supply

300

At 33 MHz

III

p.A

0::;; VIN::;; Vcc

p,A

0.45

Capacitance of Input SUff~r.'';'

Capacitance of Input/Qutput
Suffer
..•~;~~'i:)

;}ii"

1-168

< VOUT < Vcc
= 1 MHz
FC = 1 MHz
= 1 MHz

intJ

82596DX/SX

A.C. CHARACTERISTICS
82596DX INPUT/OUTPUT SYSTEM TIMINGS Te = O°Cto +S5°, Vee = 5V ±10%

These timings assume the CL on all outputs is 50 pF unless otherwise specified. CL can be 20 pF to 120 pF,
however, timings must be derated.
All timing requirements are given in nanoseconds.
25 MHz

Parameter

Symbol

Operating Frequency

Notes

Min

Max

12 MHz

25 MHz
40

CLK2/2

CLK2 Period

CLK2 High

CLK2 Low

CLK2 Rise Time

CLK2 Fall Time

T13

CA and BREQ Setup Time

1,2,3

T14

CA and BREQ Hold Time

1,2,3

T26

CA and BREQ, PORT Pulse Width

4T1

T25

INT Valid Delay

BEx, LOCK, and A2-A31 Valid Delay

22
22

BEx, LOCK, and A2-A31 FloatDelay

W/R and ADS Valid Delay

W/R and ADS Float belay

T10

00-031 Write'Data Valid Delay

T11

00-031 Write Data Float Delay .....

T27

00-031 CPU PORTAccess Setup Time

T2S

00-031 CPU Po.ATAccessHold Time

T29

PORT Setup ti~'·

T30

PORT

H~1d Time

3.7V
O.SV
7

O.SVto 3.7V

3.7V to O.SV

T17

ROY SetUp Time

T1S

ROYHbld Time

T19

00-031 READ Setup Time

T20

00-031 READ Hold Time

T12

HOLD Valid Delay

T21

HLOA Setup Time

1,2

T22a

HLOA Hold Time

1,2

T23

RESET Setup Time

T24

RESET Hold Time

1-169

intJ

82596DX/SX

A.C. CHARACTERISTICS (Continued)
82596DX INPUT/OUTPUT SYSTEM TIMINGS Te

O·Cto

+ 85·C, Vee

= 5V

±5%

These timings assume the CL on all outputs is 50 pF unless otherwise specified. CL can be 20 pF to 120 pF,
however, timings must be derated.
All timing requirements are given in nanoseconds.

Symbol

33 MHz

Parameter
Operating Frequency

Notes

Min

Max

12.5 MHz

33 MHz

CLK2 Period

CLK2/2

CLK2 High

4.5

3.7V

CLK2 Low

4.5

0.8V

CLK2 Rise Time

CLK2 Fall Time

T13

CA and BREQ Setup Time

1,2,3

T14

CA and BREQ Hold Time

1,2,3

T26

CA and BREQ, PORT PulseWidth

T25

INT Valid Delay

3.7Vto 0.8V

0.8V to 3.7V

4T1
20

BEx, LOCK, and A2-A31 Valid Delay

BEx, LOCK, and A2-A31 Float Delay

WfR and ADS Valid Delay

WfR and ADS Float Delay

T10

DO-D31 Write Data Valid Delay

T11

DO-D31 Write Data Float Delay

T27

DO-D31 CPU PORT Access Setup Time

T28

DO-D31 CPU PORT Access Hold Time

T29

PORT Setup Time

T30

PORT Hold Time

T17

RDY Setup Time

T18

RDY Hold Time

T19

DO-D31 READ Setup Time

T20

DO-D31 READ Hold Time

T12

HOLD Valid Delay

T21

HLDA Setup Time

1,2

T22a

HLDA Hold Time

1,2

T23

RESET Setup Time

T24

RESET Hold Time

1-170

82596DX/SX

A.C. CHARACTERISTICS (Continued)
82596SX INPUT/OUTPUT SYSTEM TIMINGS Te = O'Cto

+ 85'C, Vee

5V ±10%

These timings assume the CL on all outputs is 50 pF unless otherwise specified. CL can be 20 pF to 120 pF,
however, timings must be derated.
All timing requirements are given in nanoseconds.
Symbol

20 MHz

Parameter

Operating Frequency

Notes

Min

Max

12.5 MHz

20 MHz

CLK2 Period

CLK2 High

CLK2 Low

CLK2 Rise Time

CLK2 Fall Time

T13

CA and SREQ Setup Time

1,2,3

T14

CA and SREQ Hold Time

1,2,3

T26

CA and SREQ, PORT Pulse Width

4 T1

CLK2/2
at 2.0V
at 2.0V

0.8Vto 3.7V

3.7Vto 0.8V

T25

INT Valid Delay

SHE, SLE, LOCK, SON, and A1-A31
Valid Delay

SHE, SLE, LOCK, SON, and A hA31
Float Delay

W/R and ADS Valid Delay

W/R and ADS Float Delay

T10

00-015 Write Data Valid Delay

T11

00-015 Write Data Float Delay

T27

00-015 CPU PORT Access SetupTime

T28

00- 015 CPU PORT Access Hold Time

T29

PORT Setup Time

T30

PORT Hold Time

2
2

T17

ROY Setup Time

T18

ROY Hold Time

5.5

T19

00-015 READ Setup Time

T20

00-015 READ Hold Time

T12

HOLD Valid Delay

T21

HLDA Setup Time

1,2

T22a

HLDA Hold Time

1,2

T23

RESET Setup Time

1,2

T24

RESET Hold Time

1,2

1-171

82596DX/SX

A.C. CHARACTERISTICS (Continued)
82596SX INPUT/OUTPUT SYSTEM TIMINGS TC

O°Cto

+ 85°C, Vcc =

5V ±10%

These timings assume the CL on all outputs is 50 pF unless otherwise specified. CL can be 20 pF to 120 pF,
however, timings must be derated.
All timing requirements are given in nanoseconds.
Symbol

T1
T2
T3
T4
T5
T13
T14
T26
T25
T6
T7
T8
T9
T10
T11
T27
T28
T29
T30
T17
T18
T19
T20
T12
T21
T22a
T23
T24

16MHz
Min
Max
12.5 MHz
16 MHz
31
40
9
9
",,8

Parameter

Operating Frequency
CLK2 Period
CLK2 High
CLK2 Low
CLK2 Rise Time
CLK2 Fall Time
/J,B
CA and BREQ Setup Time
11
./1"'"
CA and BREQ Hold Time
8 '.'
4:T.1 ,.i,.) '.
CA and BREQ, PORT Pulse Width
";2';".
,;~:! l:.!.
INT Valid Delay
40
.>.J;~:
36,
BHE, BLE, LOCK, BON, and A 1-A31 Va~tn~lay I,:: "}:':/f
BHE, BLE, LOCK, BON, and A 1-A3ftFl", 4
00-015 Write Data Valid Delay:
/.
40
00-015 Write Data Floatrlelay
4
35
·;',·t·'}'
00-015 CPU PORT,~S Setup,time ' if; ..',:,:;:
9
6
00-015 CPU PORT:4.ccess HoldJ"ime •
. 'F··c·
PORT Setup Time:·~
11
;,.",:./'
PORT Hold Time
8
';,:~,
ROY Setup Time
19
. f"':'
';",'.: l";'···.>'
ROY HoldTime
6
9
00-015 READ S~~'Time . c>
00-015 RE~ HoJdTime
6
4'
HOLD ValiEtOel$y
33
15
HLOA S.e\ilJ:i<'frme
HLOAHOfd Time
8
RESET Setup Time
13
RESET Hold Time
4

Notes
CLK2/2
2.0V
2.0V
0.8Vto 3.7V
3.7Vto 0.8V
1,2,3
1,2,3
3

2
2
2
2
2
2
2
2

".""

...

1,2
1,2
1,2
1,2

NOTES:
1. RESET, HLDA, and CA are internally synchronized. This timing is to guarantee recognition at next clock for RESET,
HLDA, and CA.
2. All set-up, hold, and delay timings are at·the maximum frequency specification Fmax, and must be derated according to
the following equation for operation at lower frequencies:
Tderated = (Fmax/Fopr) x T
where:
Tderated = Specifies the value to derate the specification.
Fmax = Maximum operating frequency.
Fopr = Actual operating frequency.
T = Specification at .maximum frequency.
This calculation only provides a rough estimate for derating the frequency. For more detailed information contact your Intel
sales office for the data sheet supplement.
3. CA is internally synchronized; if the setup and hold times are met then CA needs to be only 2 T1. BREQ and PORT are
not internally synchronized. BREQ must meet setup and hold times and need only be 2 T1 wide.

1-172

82596DX/SX

TRANSMIT/RECEIVE CLOCK PARAMETERS
Symbol

20 MHz

Parameter
Min

Notes
Max
1,3

T36

TxCCycle

T38

TxC Rise Time

T39

TxC Fall Time

1,3

T40

TxC High Time

T41

TxC Low Time

T42

TxD Rise Time

T43

TxD Fall Time

T44

TxD Transition

T45

TxC Low to TxD Valid

4,6

T46

TxC Low to TxD Transition

2,4

T47

TxC High to TxD Transition

2,4

T48

TxC Low to TxD High (At End ofTransition)

1,3
10
10

.
,

4
4
2,4

RTS AND CTS PARAMETERS
T49

TxC Low to RTSLow,
Time to Activate RTS

T50

CTS L,ow to TxC Low,CTSSetup Time

T51

TxC Low to CTS Invalid,CTSHold Time

T52

TxC Low toRTS High

10
25

RECEIVE CLOCK PARAMETERS
T53

1,3

Ri1 14>2

4>1 14>2

4>1

CLK2
(INPUT)
BE3-BEO. A31-A2,
WjR
(OUTPUTS)
AOS
(OUTPUT)
RDY
(INPUT)
LOCK
(OUTPUT)
D31"'DO
(INPUT DURING READ)
D31-DO
(OUTPUT DURING WRITE)
290219-42

Figure 44. Basic 82596DX Bus Cycles

CYCLE 1

CYCLE 2

CYCLE 3

4>1 14>2

4>1 1 4>2

4>1

CLK2
(INPUT)
BHE-BLE,A31-A1,
BON,WjR
(OUTPUTS)
ADS
(OUTPUT)
RDY
(INPUT)
LOCK
(OUTPUT)
D15-DO
(INPUT DURING READ)
D15-DO
(OUTPUT DURING WRITE)
290219-43

Figure 45. Basic 82596SX Bus Cycles

1-175

infef

82596DX/SX

SYSTEM INTERFACE A.C. TIMING CHARACTERISTICS

The measurements should be done at:
• TC = 0·C-8S·C, Vee = SV ±10%, C = SO pF unless otherwise specified.
• A.C. testing inputs are driven at 2.4V for a logic "1" and O.4SV for a logic "0" .
• Timing measurements are made at 1.SV for both logic "1" and "0".
• Rise and Fall time of inputs and outputs signals are measured between 0.8V and 2.0V respectively unless
otherwise specified.
• All timings are relative to CLK2 crossing the 1.SV level.
,; All A.C. parameters are valid only after 100

2.4V
O.45V

'"'S from power up.

~1.5vTestpolnt~

-A:.

~
290219-18

1 - - - - T1 - - - - + I
290219-19

Figure 46. CLK2 Timings

Two types of timing specifications are presented below:
1. Input Timing-minimum setup and hold times.

2. Output Timings-output delays and float times from CLK2 rising edge.
Figure 4S defines how the measurements should be done:

1.5V
290219-20

LEGEND:
T5 = Input Setup Time
Th = Input Hold TIme
Tn = Minimum output delay or Mininum float delay
Tx = Maximum output delay or Maximum float delay

Figure 47. Drive Levels.and Measurements Points for A.C. Specifications

1-176

intJ

82596DX/SX

INPUT WAVEFORMS

Ts
Th

=
=

T13, T15, T17, T19, T21, T23, T27, T29, T31
T14, T16, T18, T20, T22, T22a, T24, T28, T30, T32
(PHI 2)

(PHil)

ClK2
BREQ

----'~---------J'I'---290219-21

Figure 48. CA and BREQ Input Timing

(PHil)

'w~~
INT/INT

290219-22

Figure 49. INTliNT Output Timing

ClK

HOLD _______

HlOA _______________- J

'__ _ _ _oJ '-_ __

290219-23

Figure 50. HOLD/HLDA Timings

(PHI 2)

(PHil)

CLK2

031-00
290219-24

Figure 51. Input Setup and Hold Time

1-177

Intel

82596DX/SX

--+

CLK2
.
A31-A2,BEn,
BHE, BLE, BON,LOCK (TS)

T1 . (PHI1)

r·.

(P. H12)

.
"
.
TTsSal;:j1
,I
MIN
MAX
~

VALID n ~ n+1

I·\-TB

'I . 'I
MIN

MAX

VALlOn~n+1

W!R, ADS

r-T10~MAX
- - - - ~IO DATA

031-00
(OUTPUT)

290219-25

Figure 52. Output Valid Delay Timing

(PHil )
CLK2

PHI2)

'f-

MIN
A31-A2,BEn
BHE,BLE,BON,LOCK

MAX.
FLOAT

VALID n,

I MAX

MIN
VALID

FLOAT

MIN
031-00
(OUTPUT)

VALID n

MAX
FLOAT

290219:-26

Figure 53. Output Float Delay Timing

CLK2

031-00
290219-27

Figure 54. PORT Setup and Hold Time

1·178

inter

82596DX/SX

RESET
290219-28

Figure 55. RESET Input Timing
SERIAL A.C. TIMING CHARACTERISTICS

3.0V

0.9V

f.-- T57_
T41j
I------m------I
290219-29

Figure 56. Serial Input Clock Timing

TxC

RTS

CTS

CDT

TxD

T62

-'--or --- -l!~-~t.- __T~~ ___:.;,.I_ _ _ _ _ _ _T_6_7==1
_ _. -+vr-----------~---

(NRZ) - _ .." •• - - - - -~ - ••" ... _ - _ - - - -'

"1 •.• r-

'. - - - - - - - - - - - - - _ ..

T44
TxD .-~\I
v.- ..v,.- - - - - .',,'.",,". - - - - . , : - - - - - - - - - - - - - - - - - - - (MANCHESTER) _..." ....." •••" ... ____ .,/'....." ... ____'
290219-30

Figure 57. Transmit Data Waveforms

1-179

Inter

82596DX/SX

CDT---------l----~----r_-----1-r---=~~~-------------------------CRS----------~~------t--------t---------+--------------------------

TxD -----....;.-..i..
(NRZ)
H

T47

--.''(......'r.'. - - - - t-......+-------------------•••••• 0 . _ _ _ _

(MANCHEST::~~
. L
t·--···;~,......---------T42J

··---t~

290219-31

Figure 58. Transmit Data Waveforms
r-------------------~

290219-33
RxD ______

290219-32

Figure 60. Receive Data Waveforms (CRS)
Figure 59. Receive Data Waveforms (NRZ)

1-180

82596DX/SX

OUTLINE DIAGRAMS
132 LEAD CERAMIC PIN GRID ARRAY PACKAGE INTEL TYPE A

1211 .. 65
REF.

:::.[J
.......::: ,

SEATING
PLANE

ED?
..............rS'---j

SEATIN~
PLANE

••••••••••••••

PIN C3

...

...
~I ...
:::~
.••••••••••••
---.l
••••••••••• •
/'

•••

.::

-- ,

•••

121 B (ALL PINS)

••••••••••• •
SWAGGE

~:;~ REF.
(:I~L)
45° CHAMFER
(INDEX CORNER)

SWAGGED
PIN
DETAIL

~:~; REF.
45° CHA¥FER
(3 PL)

290219-36

Family: Ceramic Pin Grid Array Package
Millimeters

Symbol

Inches

Min

Max

Notes

3.56

4.57

0.76

1.27

Solid Lid

2.67

3.43

Solid Lid

1.14

1.40

Min

Max

0.140

0.180

0.030

0.050

Solid Lid

0.105

0.135

Solid Lid

0.045

0.055

0.43

0.51

0.017

0.020

36.45

37.21

1.435

1.465

32.89

33.15

1.295

1.305

61
L

2.29

2.79

0.090

0.110

2.54

3.30

0.100

0.130

N
Sl
ISSUE

132
1.27
IWS

132

2.54

0.050

10/12/88

1-181

0.100

Notes

inter

82596DX/SX

Intel Case Outline Drawings
Plastic Quad Flat Pack (PQFP)
0.025 Inch (0.635mm) Pitch
Symbol

Description

Min

Max

Min

Max
84

Min

Max

Min

Max

Min

Max

Leadcount

Package Height

0:160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170 0.160 0.170

Standoff

0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030

D,E

Terminal Dimension

0.675 0.685 0.775 0.785 0.875 0.88.5 1.075 1.085 1.275 1.285 1.475 1.485

100

Min

132

164

196

01, E1

Package Body

0.547 0.553 0.647 0.653 0.747 0.753 0.947 0.953 1.147 1.153 1.347 1.353

D2,E2

Bumper Distance

0.697 0.703 0.797 0.803 0.897 0.903 1.097 1.103 1.297 1.303 1.497 1.503

D3,E3

Lead Dimension

D4,E4

Foot Radius Location 0.6230 ..637 0.723 0.737 0:8230.837 1.023 .1 .. 037 1.223 1.. 237 1.423 1.437

L1 .

Foot Length

Issue

IWS Preliminary 12/12/88

Symbol
N
A

Description

0.400 REF 0.500 REF

1.000 REF

1.200 REF

0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030 0.020 0.030

Min

- Leadcourit
Package Height'

0.600 REF· 9.800 REF

INCH

Max

Min

Max

Min

Max

100

Min

Max

132

Min

Max

164

Min

Max

196

4.06 4.32

4.06

4.32 4.06

4.32

4.06 4.32 4.06 4.32 4.06

4.32

0.51

0.76 0.51

0.76

0.51

0.76

Standoff

0.51

D,E

Terminal Dimension

17.15 17.40 19.69 19.94 22.23 ,22.48 27.31 27.56

01, E1

Package Body

13.89 14.05 16.43 16.59 18.97 19.13 24.05 24.21 29.13 29.29 34.2,1 34.37

D2,E2 . Bumper Distance

0.76

0.76 0.51
~2.39

0.76 0.51

32.64 37-47 37.72

17.70 17.85 20.24 20.39 22:78 22.93 27.86 28.01 32.94 33.09 38.02 38.18

D3,E3

Lead Dimension

D4,E4

Foot Radius Location 15.8216.17 18.36 18.71 21.25 21.25 25.89 26.33 31.06 31.41 36.14 36.49,

10.16 REF

Foot Length

Issue

IWS Preliminary 12/12/88

0:51

0.76

12.70 REF

0.51

15.24 REF

0.76 0.51

0.76

20.32.REF

0.51

25.40 REF

0.76 0.51

30.48 REF

0.76 0.5r 0.76
mm

1·182

inter

82596DX/SX

,BASE PLANE
i-- Ai

mm (inch)

290219-37

Figure 61. Principal Dimensions and Datums

1$10.25 (.0i0)@ICIA®-B®ID®l&
II-.LI .002 MM/MM <1

4
TiC

EV~NT

I
I

STATUS 0

TIMER/COUNTER STATUS

STATUS 1

TIMER/COUNTER CONFIGURATION

STATUS 2

PORT 1 COMMAND
STATUS

TlMER/COUNTER
CONFIGVRATION

STATUS 3

290147-9

Timer/Counter Events
(T/C = 1)
Timer Expired

BitO

Counter 1 Expired

Bit 1

Counter 2 Expired

Bit2

Counter 3 Expired

Bit 3

'The 82590 may have more than one EVENT bit set by the time the CPU reads the status register.

1-221

=
=
=
=

1
1
1
1

General Purpose Event
Value'
(GP = 1)
(Status 0)
REM-PWR-UP

Figure 8. Port 1 Status Registers

Value'
(Status 0)

Intel

82590

290147-10

Figure 9. 825901Host CPU Interaction
To initiate an operation such as Transmit or Configure (see Figure 5), the command from the CPU must
first be written to the 82590. Any parameters or data
associated with the command are transferred from
memory to the 82590 using DMA. Upon completion
of the operation, the 82590 updates the appropriate
status registers and sends an interrupt to the CPU.

Table 2. Data Bus Control Signals and Functions
Pin Name
CSO
CS1*
1
0

Function
No Transfer To/From
Command/Status

Illegal

Read from Status
Register

Write to Command
Register

DACKO
DACK1*

Illegal

Data Read from DMA
Channel 0 (or 1)

Data Write to DMA
Channel 0 (or 1)

1
0

FRAME TRANSMISSION
To transmit a frame, the CPU prepares a Transmit
Data Block in memory as shown in Figure 10. Its first
two bytes specify the length of the rest of the block.
The next few bytes (up to six) contain the destination
address of the station the frame is being sent to.
The rest of the block is the data field. The CPU programs the DMA controller with the start address of
the block, length of the block, and other control in·
formation and then issues a Transmit command to
the 82590. Upon receiving this command, the 82590
fetches the first two bytes of the block to determine
its length. If the link is free and the first data byte
was fetched, the 82590 begins transmitting the preamble and concurrently fetches more bytes from the
Transmit Data Block and loads them into the transmit FIFO to keep them ready for transmission.

No DMA Transfer

'Only one of CSO, CS1, DACKO, or DACK1 may be active
at any time.

1-222

82590

PREAMBLE
BLOCK BYTE COUNT

SFD (BOF FLAG)

DESTINATION ADDRESS

DATA FIELD

SOURCE ADDRESS

CPU GENERATED
DATA STRUCTURE IN MEMORY
(TRANSMIT DATA BLOCK)

LENGTH FIELD

[

}

GENERATED BY 82590
FROM 82590

+- INDIVIDUAL
ADDRESS

INFORMATION FIELD
PADDING (OPTIONAL)
FRAME CHECK SEQUENCE
EOF FLAG (OPTIONAL)
PADDING (OPTIONAL)
290147-11

Figure 10. The 82590 Frame Structure.and Location of Data Element in System Memory

The destination address is transmitted after the preamble. This is followed by the source or the station
individual address, which was previously stored in
the 82590 by the lA-Setup command. After this, the
entire information field is transmitted, followed by a
CRC field calculated by the 82590. If a collision is
encountered during transmission of the frame, then
the transmission is aborted after a jam pattern is
sent. If the collision is detected during preamble or
SFD (Start Frame Delimiter) transmission, the 82590
transmits the jam pattern after the SFD is transmitted. An interrupt is then generated to inform the CPU
of the unsuccessful transmission due to a collision.
The CPU reinitializes the DMA controller and issues
a Retransmit command to the 82590. Retransmission is done by the CPU exactly as the Transmit
command is done, except the Retransmit command
keeps track of the number of collisions encountered.
When the 82590 gets the Retransmit command and
the backoff timer is expired, it transmits the frame
again. Retransmission is repeated until the attempt
is successful, or until the preprogrammed retry number expires.
If the 82590 is programmed to generate the EOP
signal to the 8237 or 82380 DMA controller, or if it is
used with a DMA controller which implements the

Tightly Coupled Interface, retransmission is performed without CPU intervention.

FRAME RECEPTION
The 82590 can receive frames when its receiver has
been enabled. The 82590 checks for an address
match for an Individual address, a Multicast address,
or a Broadcast address. In the Promiscuous mode
the 82590 receives all frames. When the address
match is successful, the 82590 transfers the frame
to memory using the DMA controller. Before enabling the receiver, it is the CPU's responsibility to
make a memory buffer area available to the receiver
and to properly program the starting address of the
DMA controller. The received frame is transferred to
the memory buffer in the format shown in Figure 11.
This method of reception is called Single Buffer reception; the entire frame is contained in one continuous buffer. Upon completion of reception, the status
of the reception is appended at the end of the received frame in the memory buffer, and the total
number of bytes transferred to the memory buffer is
loaded into the internal status registers 1 and 2. An
interrupt is then generated to inform the CPU of the
frame reception.

1-223

82590

BLOCK
LENGTH

BLOCK LENGTH
BL

DESTINATION
ADDRESS

SOURCE
ADDRESS

INFORIAATION

DATA BLOCK IN MEMORY FOR
TRANSMISSION

INFORIAATlON

FRAME STATUS

SINGLE BUFFER RECEPTION

290147-12

Figure 11. Single Buffer Reception
If the frame size is unknown, memory usage can be
optimized by using Multiple Buffer reception. In this
mode of operation, the CPU and DMA Controller can
dynamically allocate memory space as it receives
frames. This method requires both DMA channels to
receive the frame alternately. As frame reception begins, the 82590 interrupts the CPU and automatically
requests assignment of the next available· buffer.
The CPU does this and loads the second DMA
channel with the next buffers information so the
82590 can immediately switch to the other channel
when the current buffer is full. When the 82590
switches from the first to the second buffer it again
interrupts the CPU and requests another buffer to be
allocated on the previous channel. This process
continues until the entire frame is received. The received frame is spread over multiple memory buffers. The link between the buffers is easily maintained by the CPU, using a buffer chain descriptor
structure in memory as shown in Figure 12. This dynamic allocation of memory buffers results in efficient use of available storage when handling frames
of widely differing sizes.
If the 82590 is programmed to generate the EOP
signal to the 8237 or 82380 DMA controller, or if it is
used with a DMA controller which implements the
Tightly Coupled Interface, buffer recla~ation and

more advanced data structures for the buffer area
can significantly improve system performance.

EOP SIGNAL TO THE DMA
CONTROLLER
The 82590 can be programmed to assert the EOP
signal to the 8237 or 82380 DMA controller when
one or more of the following occurs:
e A collision during transmission
e An error (CRC or alignment) during reception
eA good frame reception
If the 8237 or 82380 is programmed for Auto-initialize mode and if the 82590 is programmed to assert
the EOP signal on a collision during transmission,
the retransmission following a collision is done automatically by the 8237 and the 82590. The 8237 will
reinitialize itself automatically and the 82590 will retransmit the same frame from the same memory
area without CPU intervention. When the 82590 is
programmed for this mode it does not interrupt the
CPU upon a collision, and the CPU does not need to
issue a Retransmit command to the 82590. The CPU
is interrupted only after a successful transmission or
retransmission, or after a transmission failure, such
as DMA underrun.

1-224

intJ

82590

DEST ADDR

BUFFER 1

BUFFER 2

•••
@

BUFFER

BUFFER N

••
•

BUFFER CHAIN DESCRIPTION
(MANAGED BY CPU)

1 - - - - - 1 BUFFER

STATUS
290147-13

Figure 12. Multiple Buffer Reception

If the 82590 is programmed to assert the EOP signal
when an error occurs during reception, the 8237 or
the 82380 in Auto-initialize mode will be able to reclaim the memory area which would otherwise be
wasted for the errored frame reception. If the 82590
is programmed to assert EOP at the end of a frame
reception, automatic buffer switching can be accomplished by alternating the DMA channels with the
8237 or the 82380. When the 82380 is used, the
buffer switching can be done with only one DMA
channel.
The EOP signal must be derived from the DACK1 I
CS1/EOP pin using external logic (see Figure 13).

82590/82560 TIGHTLY COUPLED
INTERFACE
The 82590 has a mode of operation called "Tightly
Coupled Interface." In this mode the 82590 provides
a tightly coupled interface to a DMA controller in order to execute some of the time-critical processes of
the CSMAlCD protocol without any CPU intervention. By using the 82590's companion. chip, the
82560, or by implementing the Tightly Coupled Interface in a· DMA controller, operations such as automatic retransmission, continuous back-to-back
frame reception, and transmit andlOr receive buffer
chaining can be accomplished.
The 82590 provides the status of the current active
transmission or reception to the DMA controller by
using the DRO and EOP signals at the end of every
DMA cycle. The status is encoded according to Ta-

ble 3. As long as the 82590 generates DRO High
and EOP Floating at the rising edge of RD or WR,
the DMA controller repeats DMA transfers. If the
transmission is completed without collisions or if the
reception is good (no collision, no CRC, or no Alignment error), then DRO and EOP both become Low
at the end of a DMA transfer which follows the last
DMA data transfer. If the transmission encountered
a collision or if the reception hadan error, DRO becomes High and EOP becomes Low. The DMA controller must decode these signals appropriately and
must reinitialize the DMA channel so it can retransmit the same frame or reclaim the otherwise wasted
buffer. It is the DMA controller's responsibility to reprogram itself for the next appropriate operation.
The 82560 fully implements the Tightly Coupled Interface and provides very high-performance DMA
services for the 82590 with minimal CPU involvement.

NETWORK MANAGEMENT AND
DIAGNOSTICS
The 82590 provides a large set of diagnostic and
network management functions including: internal
and external loopback, monitor mode, optional capture of all frames regardless of destination address
(Promiscuous mode), and time domain refiectometry
for locating fault points in the network cable. The
82590 Dump command ensures software reliability
by dumping the contents of the 82590 internal registers into the system memory.

1-225

inter

82590

EOP
82590

CSI

OACK1/CS1/EOP
OACKO
OACKI

DACKO

OROO

OROI

CSO

CSO
290147-14
Figure 13. Demultiplexing DACK/CS1/EOP Pin

Table 3. Transmit/Receive Status Encoding on ORO and EOP
ORO

EOP

Hi-Z

Status Information

Idle
DMA Transfer

Hi-Z

Transmission or Reception Terminated OK

Transmission or Reception Aborted

OTHER ENHANCEMENTS
Compared to the 82588 the 82590 has a number of
functional and performance enhancements. This
section lists some of these enhancements which are
not covered in other sections.

It)

I+- "

"
aXI ~ i~

•

~
I
I
I

f ~
.......
"-

ti
"" ..,'"
...J

'"
f

'"~N

:5~

::10

L'"
Figure 15.82590/82560 High-Integration Adapter

1-228

ax~

J
'IIIl

0>
C'l
C
290147-22

NOTE:
DACKO or DACK1 may remain active continuously for consecutive DMA cycles.

READ TIMING

iW---_1

T21~L
°0-7

------

VALID

-t____--'X""__

VA_L_IO____

290147-23

NOTE:
DACKO or DACK1 may remain active continuously for consecutive DMA cycles.

1-233

inter

82590

DMA Request (Going Active)

CL.K

-+_.1

OROD OROl _ _ _ _ _ _ _ _

2~0147-24

DMA Request (Going ,Inactive)
OROD OROl

T23

290147-25

Tightly Coupled Interface
,""'·H

OROD.~

OROl
OACKD
DACKI

WR.

I-TZ3

i-T104

RD
, I

~
-- T,051=

1-234

.1
-

T,os

290147-26

82590

SERIAL INTERFACE A.C. TIMING CHARACTERISTICS
TFC is the Crystal or Serial Clock Input at X1.

X8Sampiing

X10Sampiing

X16 Sampling

X18 Sampling

High Integration Mode
For TFC Frequency = 1 MHz to 32 MHz (High)
0.125 MHz-4 MHz

100 kHz-3.2MHz

62.5 kHz-2 MHz

55.6 kHz-1.78 MHz

t29 = TCLK
Cycle Time

8 X t24

10 X t24

16 X t24

18 X t24

t30 = TCLK
High Time

t24 (Typically)

124 (Typically)

131 = TCLK
Low Time

7 X t24 (Typically)

9 X 124 (Typically)

15 X t24 (Typically)

17 X t24 (Typically)

TCLK Frequency

For TFC Frequency = 0 MHz to 1 MHz (Low)
0-0.125 MHz

0-100 kHz

0-62.5 kHz

0-55.6 kHz

t29 = TCLK
Cycle Time

8 X t24

10 X t24

16 X t24

18 X t24

t30 = TCLK
High Time

t25 (Typically)

125 (Typically)

t31 = TCLK
Low Time

7 X t24 + t26
(Typically)

9 X 124

15 X t24 + t26
(Typically)

17 X t24 + t26
(Typically)

TCLK Frequency

+ t26
(Typically)

NOTES:
X10 and X18 are available only for Manchester or Differential Manchester encoding/decoding
t24 = Serial Clock Cycle Time
t25 = Serial Clock High Time
t26 = Serial Clock Low Time

HIGH SPEED MODE
• Applies for TxC, RxC

• f max = 20 MHz ±100 ppm
• For Manchester, symmetry is required: t64, t64 =

2t1 ± 5%

1-235

82590

HIGH INTEGRATION MODE
I
Parameter

I Symbol

Min

Max

Units

Test Conditions

EXTERNAL (FAST) CLOCK PARAMETERS
t24

Fast Clock (TFC) Cycle Time

31.25

(Notes 1, 16)

t25

TFC High Time

(Note 13)

(Notes 1,7)

t26.

TFCLowTime

(Notes 1, 17)

t27

TFC Rise Time

. ns

(Note 1)

t28

TFCFaliTime

(Note 1)

TRANSMIT CLOCK PARAMETERS
t29

Transmit Clock (TCLK)
Cycle Time

(Note 13)

(Note 2)

t30

TCLK High Time

(Note 7)

(Note 2)

t31

TCLK Low Time

(Note 8)

(Note 2)

t32

TCLK Rise Time

(Note 2)

t33

TCLK Fall Time

(Note 2)

TRANSMIT DATA PARAMETERS (MANCHESTER, DIFFERENTIAL MANCHESTER)
t34

TxD Transition-Transition

(Note 14)

t35

TCLK Low to TxD
Mid Bit Cell Transition

(Note 10)

(Note 2)

t36

TCLK Low to TxD
Bit Cell Boundary Transition

(Note 9)

(Note 2)

t37

TxD Rise Time

(Note 2)

t38

TxD Fall Time

(Note 2)

TRANSMIT DATA PARAMETERS (NRZI)
t39

TxD Transition-Transition

t40

TCLK Low to TxD Transition

t41

(Note 15)

ns
(Note 9)

(Note 2)

TxD Rise Time

(Note 2)

t42

TxD Fall Time

(Note 2)

t43

TCLK Low to RTS Low

(Note 9)

(Note 2)

RTS, CTS PARAMETERS
t44

CTS Low to TCLK Low

t45

TCLK Low to RTS High

t46

TCLK Low to CTS Invalid
CTS Hold Time

t47

CTS High to TCLK Low;
CTS Setup Time to Stop
Transmission

(Note 2)

(Notes 3, 12)

(Note 3)

(Note 9)

IFS PARAMETERS
Interframe Delay

(Note 4)

1-236

82590

HIGH INTEGRATION MODE (Continued)
Parameter

Test Conditions

t49

COT Low to TCLK High
External Collision Detect
Setup Time

(Note 12)

t50

COT High to TCLK High

(Note 12)

t51

TCLK High to COT Inactive
COT Hold Time

(Note 12)

t52

COT Low to Jamming Start

t53

Jamming Period

(Note 5)
(Note 6)

ns
ns

RECEIVED DATA PARAMETERS (MANCHESTER, DIFFERENTIAL MANCHESTER)
t54

RxD Transition-Transition

t55

RxD Rise Time

t56

RxD Fall Time

115

(Note 14)

RECEIVED DATA PARAMETERS (NRZI)
ns

t57

RxD Transition-Transition

t58

RxD Rise Time

240
10

t59

RxD Fall Time

(Note 11)

EXTERNAL LOOPBACK PARAMETERS
TCLK Low to LPBK High

(Note 2)

TCLK Low to LPBK Float

(Note 2)

NOTES:

1. MOS Levels.
2. 1 TTL Load + 50 pF.
3. Abnormal End of Transmission: CTS expires before
RTS.
4. Programmable value: t28 = NIFS X t29 (ns)
NIFS: the IFS configuration value.
If NIFS is less than 12 then it is enforced to 12.
5. Programmable Values:
t52 = NCDF X t29 + (12 to 15) X t29 (if collision occurs
after preamble).
NCDF: The Collision Detect Filter Configuration Value.
6. t53 = 32 X t29
7. Depends on frequency range:
High Range: t24 - 10 ns
Low Range: t25 - 10 ns
a. t31 = t29 - t30 - t32 - t33
9. 2 X t24 + 40 ns for ax or lOX
4 X t24 + 40 ns for 16X

10. 6 X t24 + 40 ns for ax
12 X t24 + 40 ns for 16X
7 X t24 + 40 ns for lOX
13 X t24 + 40 ns for laX
11. a X t24 - 10 ns for ax
10 X t24 - 10 ns for lOX
16 x t24 - 10 ns for 16X
la X t24 - 10 ns for laX
12. To Guarantee recognition on the next clock.
13. 10 ns for High Range
30 ns for Low Range
14.4 X t24 - 10 ns for ax
5 X t24 - 10 ns for lOX
a X t24 ~ 10 ns for 16X'
9 X t24 - 10 ns for laX
15. t29 - 10 ns
16. See Figure "CRYSTAL CONNECTION."
17. Maximum capacitance load on the X2 pin when an
external MOS clock is connected to Xl:
15 pF for DC to 16 MHz
5 pF for 16 MHz to 32 MHz

1-237

intJ

82590

CRYSTAL CONNECTION

82590

290147-27
NOTES:
1. High-quality, parallel resonant, fundamental-mode crystals are recommended for maximum accuracy.
2. C1, C2, and stray capacitance of the board should be adjusted so the total capacitance load on the crystal is approx.
15 pF.
3. For IEEE 802.3 applications, the crystal must be accurate to ± 35 PPM over a range of O'C to 70'C.

TRANSMIT TIMING5-CLOCKS RTS AND CTS

cTs--------------------~1-~~--~--------------

CDT------------------------------------~~------------------

~D------------------------------~:==:====--lS/:-B-IT-C-E-LL----------_-_-_-~.II

TFC

T:~:==~~~~_~_C:~~T~4:5_:{::r--~------:~:r:l-t~~-----

5. .t._: 3!-!:~ J:T:r.:i~ 7T.T44e6r--

CTS __________________________

CDT-------------------------~-------------

TxD ~HALF BIT CELLJ

290147-26

TRANSMIT TIMING5--MANCHESTER DATA ENCODING

CTS
COT
TxD

-T35f--

T36

T34----1
I
---:~-±T37
T38
DATA BIT CELL - - DATA BIT CELL-I
. 1-238

290147-29

infef

82590

TRANSMIT TIMINGS-LOST CTS
TFC

':31:",
CTS=R

cw----------------------------------------TxD::::::::::::)z:::::::::::::::::::::J7~----

290147-30

TRANSMIT TIMINGS-NRZIDATA ENCODING

--f'
i--T4Q---<>

T42

--tt-

T41-Jt-"

I
DATA BIT CELL

DATA BIT CELL
290147-31

TRANSMIT TIMINGS-LOST CTS

TFC
TCLK

* e-r-

- - - f \__________..;..______-+..J

T45-1
I

RTS ________________________~ T7j

CTS

CDT--------------------~------------------

TxD

J,.----------\'_________

j~-------------

290147-32

RECEIVE DATA TIMINGS (MANCHESTER)

290147-33

1-239

inter

82590

RECEIVE DATA TIMINGS (NRZI)
TFC

RxD

J. .F8

=9E. ._

T5 9
_ _ _ _ _ T57 _ _ _ _

290147-34

TRANSMIT TIMINGS-INTERFRAME SPACING

RTS
CTS
COT
TxD

:::::JC

I
FIRST DATA BIT
FROt.! HERE TO
THE RIGHT
290147-35

TRANSMIT TIMINGS-COLLISION DETECT AND JAMMING
TfC ~sf\../VV'\.s,

~LK

sr--l'---------------Jr\~-------

~~~--------~~--------__~~-------------------------------Jr--

290147-36

LOOPBACK OUTPUT SIGNAL TIMINGS

LPBK

---+---'1
290147-37

1-240

82590

HIGH SPEED MODE
Symbol I
Parameter

Min

Max

Units

Test Conditions

TRANSMIT/RECEIVE CLOCK PARAMETERS
50

t60

RxC, TxC Cycle Time

t61

TxC Rise Time

t62

TxCFallTime

t63

TxC High Time

t64

TxCLowTime

(Notes 1,3)

(Note 1)

(Notes 1,3)

TRANSMIT DATA PARAMETERS
t65

TxD Rise Time

(Note 4)

t66

TxDFallTime

(Note 4)

t67

TxC Low to TxD Valid

(Notes 4,5)

t68

TxC Low to TxD Transition

(Notes 2,4)

t69

TxC High to TxD Transition

(Notes 2,4)

t70

TxD Transition-Transition

(Notes 2,4)

t71

TxC Low to TxD High
(At the Transmission End)

(Note 4)

RTS, CTS PARAMETERS
t72

TxC Low to RTS Low
Time to Activate RTS

t73

CTS Low to TxC Low
CTS Setup Time

t74

TxC Low to RTS High

(Note 4)

t75

TxC Low to CTS Invalid.
CTS Hold Time

(Note 6)

t75a

CTS High to TxC Low. CTS
Setup Time to Stop
Transmission

(Note 6)

(Note 8)

INTERFRAME SPACING PARAMETER
Inter Frame Delay

1-241

82590

lll'e

HIGH SPEED MODE (Continued)
Parameter

Test Conditions

t77

CDT Low to TxC High;
External Collision Detect
Setup Time

t7s

TxC High to CDT Inactive;
CDT Hold Time

ns
(Note 9)

(Note 10)

t79

CDT Low to Jam Start

tso

Jamming Period

tS1

CRS Low to TxC High;
Carrier Sense Setup Time

tS2

TxC High to CRS Inactive;
CRS Hold Time

tS3

CRS High to Jamming Start
(Internal Collision Detect)

tS4

CRS High to RxC High;
CRS Inactive Setup Time

tS5

RxC High to CRS High;
CRS Inactive Hold Time

(Note 11)

(Note 12)

RECEIVE CLOCK PARAMETERS
tS6

RxC Rise Time

(Note 1)

tS7

RxC Fall Time

(Note 1)

tss

RxC High Time

(Note 1)

tS9

RxC Low Time

(Note 1)

(Note 5)

RECEIVED DATA PARAMETERS
t90

RxD Setup Time

t91

RxD Hold Time

t92

RxD Rise Time

t93

RxD Fall Time

EXTERNAL LOOPBACK PARAMETERS
TxC Low to LPBK High

t60

(Note 4)

TxC Low to LPBK High

t60

(Note 4)

NOTES:

1. MOS Levels.
2. Manchester Only.
3. Manchester. Needs 50% duty cycle.
4. 1 TIL Load + 50 pF.
5. NRZ only.
6. Abnormal End of Transmission: CTS expires before
RTS.
7. Normal End of Transmission.
S. Programmable value:
t76 = NIFS X t60
NlFs: the IFS configuration value.
If NIFS is less than 12 then NIFS is enforced to 12.

9. Programmable Value:
t79 = NCDF X t60 + (12 to 15) x t60 (if collision occurs
after preamble).
NCDF: The collision detect filter configuration value.
10. tso = 32 X t60
11. Programmable Value:
tS3 = NCDF X t60 + (12to 15) X Iso
12. To guarantee recognition on the next clock.

1-242

82590

TRANSMIT DATA WAVEFORMS

CTS
COT

~~~_7_ _ _ _ •
T81

CRS ~ •• _ _ _ _ .-""-'~

TxD

-=::t...•••...r--.-..

(NRZ)~;:::
TxD

~___ ••V

...._

....r-

.....

::::.

....V

(MANCHESTER)

290147-38

t: ..XIT71-~
fF.

T6
__

TxD
(NRZ)

T69

--~

p::x::

TxD
(MANCHESTER)
T68

T68

1·243

"\..-J'

T71

T65

T66

290147-39

InIeI

82590

RECEIVE DATA WAVEFORMS (NRZ)

TB7
RxD

290147-40

RECEIVE DATA WAVEFORMS

"'==Rf=
-~~

CRS

TB4

290147-41

LOOPBACK OUTPUT SIGNAL TIMINGS

LPBK

---+---'1
290147-42

1-244

82C501AD
ETHERNET SERIAL INTERFACE
Manchester Encoding/Decoding and
• Receive
Clock Recovery
10-MHz Transmit Clock Generator
• Drives/Receives
802.3 AUI Cables
• Defeatable Watchdog
Timer Circuit to
• Prevent Continuous Transmission
Diagnostic Loopback for Network Node
• Fault
Detection and Isolation

Replacement for Intel 82C501,
• CHMOS
82501, or SEEQ8023A
Conforms to IEEE 802.3 10BASE5
• (Ethernet)
and 10BASE2 (Cheapernet)
Specifications
Direct Interface to Intel LAN
• Controllers
and the Attachment Unit
Interface (Transceiver) Cable
• 10-Mb/s Operation

The 82C501 AD Ethernet Serial Interface (ESI) chip is designed to work directly with Intel LAN Controllers
(82586,82590, and 82596) in IEEE 802.3 (10BASE5 and 10BASE2), 10-Mb/s, Local Area Network applications. The major functions of the 82C501AD are to generate the 10-MHz transmit clock for the Intel LAN
Controller, perform Manchester encoding/decoding of the transmitted/received frames, and provide the electrical interface to the Ethernet transceiver cable (AUI). Diagnostic loopback control enables the 82C501AD to
route the signal to be transmitted from the Intel LAN Controller through its Manchester encoding and decoding
circuitry and back to the Intel LAN Controller. The combined loopback capabilities of the Intel LAN Controller
and 82C501 AD result in highly effective fault detection and isolation through sequential testing of the communications interface. A (defeatable) on-chip watchdog timer circuit prevents the station from locking up in a
continuous transmit mode. The 82C501AD is pin compatible with the 82C501 and functionally compatible with
the 82501 and SEEQ 8023A.
PLCC
cotmIOUER
INTERFACE

GND

CDW~DN· ~

PRESENCE
GENERATION

-XCYRCABLE
INTERFACE ..
NOtSE FILTER

CLSN

-,-

CARRIER-PRESENCE GENERATION

AXD

MANCHESTER
DECODER AND
CLDa<
RECOIIERY

18Z I~

TRANSCEIVER CABLE
INTERFACE

,"-',

XCYRUS"
INTERFACE
AND
NOISEFIlJ'£A

RCV

LaJ

lPBK/WDTD

RCV

82C501AD
28l PlCC

TXC

CDT

TEN

RXC

X
0:

MANCHESTER
ENCODER
TEN

x,
~ f--.¥.CR

I
WATCHDOG TIMER

C
Z

If)

Z
V)

d d
231926-19

YSYAL

, ". ,,TAMT
,
!\ ,,

TRANSCEIVER
CABLE DRIVER

Ctl ~ !!=

TAMT

DIP

LPBKIWDTD

RCV
RCV
CRS

vcc

ENETYI
NOOA

AXC
RXD

•

TXD
TXC
Xl
X2
CLSN

231926-1

Figure 1. 82C501AD Functional Block Diagram

231926-2

Figure 2. Pin Configurations
(PLCC and DIP)

1-245

OctDber 1990
Order Number: 231926-007

inter

82C501AD ETHERNET

Table 1. Pin Description
Symbol

DIP
Pin
No.

PLCC
Pin
No.

Type

Name and Function

ENETV1

ETHERNET VERSION 1.0: An active low, MOS-Ievel input intended
for use as a strapping option. When ENETV1 is asserted, the TRMT I
TRMT pair remains at high differential voltage at the end of
transmission. This operation is compatible with the Ethernet Version
1.0 specification. If the EN!=TV1 pin is left floating, an internal pull-up
resistor biases the input inactive high. When ENETV1 is high, the
TRMTITRMT differential voltage gradually approaches OV at the end
of transmission.

NOOR

CRS 'OR': An active low, MOS-Ievel input intended for use as a
strapping option. When NOOR is low, only the pr~sence of a valid
signal on the RCVIRCV pair will force CRS active. If the NOOR pin is
floatinti, an internal pull-up resistor biases the input inactive high.
When NOOR is inactive high, either the presence of a valid signal on
CLSN/CLSN or on RCV IRCV will force CRSactive.

LPBKI
WDTD

LOOPBACK/WATCHDOG TIMER DISABLE: An active low, TTLlevel control signal that enables the loopback mode. In loopback
mode serial data on the TXD input is routed through the 82C501AD
internal circuits and back to the RXD output without driving the
TRMT ITRMT output pair to the transceiver cable. Duting loopback
CDT is asserted at the end of each transmission to simulate the SQE
test. The LPBK signal should be driven high once Vee is stabilized.
WATCHDOG TIMER DISABLE: An input voltage of 10 to 16 V
through a 1 kO resistor will disable the on-chip watchdog timer.

RCV
RCV

4
5

6
7

I
I

RECEIVE PAIR: A differentially driven input pair which is tied to the
receive pair of the Ethernet transceiver cable. The first transition on
RCV is negative-going to indicate the beginning of a frame. The last
transition is positive-going to indicate the end of the frame. The
received bit stream is assumed to be Manchester encoded.

CRS

CARRIER SENSE: An active low, MOS-Ievel output which notifies the
Intel LAN Controller that there is activity on the coaxial cable. The
signal is asserted when a valid signal on RCV IRCV is present. If the
NOOR input is inactive high, then CRS is also asserted when a valid
signal on CLSN/CLSN is present. It is deasserted at the end of a
frame or when the end of the collision-presence signal is detected,
synchronous to RXC. After transmission, when NOOR = 1, CRS is
inhibited for a period of 5 J-Ls minimum to 7 J-Ls maximum, regardless
of any activity on the collision-presence Signal (CLSN/CLSN) and
RCVIRCV inputs. When NOOR = 0, CRS is not inhibited.

CDT

COLLISION DETECT: An active-low, MOS-Ievel signal which drives
the CDT input of the Intel LAN Controller. It is asserted as long as
there is activity on the collision pair (CLSN/CLSN), and during SQE
(heartbeat) test in loopback.

RXC

RECEIVE CLOCK: A 1O-MHz MOS level clock output with 5-ns rise
and fall times. This output is connected to the Intel LAN Controller
receive clock input RXC. There is a maximum 1.4-J-Ls delay at the
beginning of a frame reception before the clock recovery circuit gains
lock, During idle (no incoming frames) RXC is forced low.

RXD

RECEIVE DATA: A MOS-Ievel output tied directly to the RXD input of
the Intel LAN Controller and sampled by the Intel LAN Controller at
the negative edge of RXC. The bit stream received from the
transceiver cable is Manchester decoded prior to being transferred to
the controller. This output remains high during idle.
1-246

intJ

82C501AD ETHERNET

Table 1. Pin Description (Continued)
Symbol

DIP PLCC
Pin
Pin
Type
No. No.

GND

14
15

CLSN
CLSN

12
11

17
16

I
I

COLLISION PAIR: A differentially driven input pair tied to the collisionpresence pair of the Ethernet transceiver cable. The collision-presence
signal is a 1O-MHz square wave. The first transition at CLSN is negativegoing to indicate the beginning of the signal; the last transition is positivegoing.

X1
X2

14
13

19
18

I
I

CLOCK CRYSTAL: 20cMHz crystal inputs. When X2 is floated, X1 can be
driven by an external MOS level input clock.

TEN

TRANSMIT ENABLE: An active low, TTL level signal synchronous to TXC
that enables data transmission to the transceiver cable and starts the
watchdog timer. TEN can be driven by the RTS signalfrom the Intel LAN
Controller.

TXC

TRANSMIT CLOCK: A 1O-MHz MOS level clock output with 5-ns rise and fall
times. This clock is connected directly to the TXC input of the Intel LAN
Controller.

TXD

TRANSMIT DATA: A TTL-level input signal that is directly connected to the
serial data output, TXD, of the Intel LAN Controller.

TRMT
TRMT

19
18

28
27

0
0

TRANSMIT PAIR: A differential output driver pair that drives the transmit pair
of the transceiver cable. The output bit stream is Manchester encoded.
Following the last transmission, which is always positive at TRMT, the
differential voltage is slowly reduced to zero volts in a series of steps. If
ENETV1 is asserted this voltage stepping is disabled.

Vee

Name and Function
GROUND

POWER: 5V ±10%.
2. Crystek Corporation
100 Crystal Drive
Ft Myers, FL 33907

FUNCTIONAL DESCRIPTION
Clock Generation
A 20 MHz parallel resonant crystal is used to control
the clock generation oscillator, which provides the
basic 20 MHz clock source. An internal divide-bytwo counter generates the 10 MHz ± 0.01 % clocl<
required by the IEEE 802.3 specification.
It is recommended that a crystal meeting the following specifications be used:
• Quartz Crystal
• 20.00 MHz ± 0.002% at 25°C
• Accuracy ±0.005% Over Full Operating Temperature, 0 to 70°C
• Parallel Resonant with 20-pF Load Fundamental
Mode
Several vendors have these crystals available; either
off the shelf or custom made. Two possible vendors
are:
1. M-Tron Industries, Inc
Yankton, SO 57078

The accuracy of the Crystal Oscillator frequency depends on the PC board characteristics, therefore it is
advised to keep the X1 and X2 traces as short as
possible. The optimum value of C1 and C2 should
be determined experimentally under nominal operating conditions. The typical value of C1 and C2 is
between 22 and 35 pF.
An external, 20 MHz, MOS-Ievel clock may be applied to pin X1 while pin X2 is left floating .

TRANSMIT SECTION
Manchester Encoder and Transceiver
Cable Driver
The 20-MHz clock is used to Manchester encode
data on the TXD input line. The clock is also divided
by two to produce the 10-MHz clock required by the

1-247

82C501AD ETHERNET

20 MHz INTERNAL CLOCK

TXD

"0"

------~'

"1"

"I"

"0"

TRMT DIFFERENTIAL SIGNAL

(MANCHESTER-ENCODED DATA)
231926-3

Figure 3. Start of Transmission and Manchester Encoding
Intel LAN Controller for synchronizing its RTS and
TXD signals. See Figure 3. (Note that the Intel LAN
Controller RTS is tied to the 82C501 AD TEN input
as shown in Figure 4.)
Data encoding and transmission begins with TEN
going low. Since the first bit is a '1', the first transition on the transmit output TRMT is always negative. Transmission ends with the TEN going high.
The last transition is always positive at TRMT and
can occur at the center of the bit cell (last bit = 1) or
at the boundary of the bit cell (last bit = 0). A 1.5-bit
delay is introduced by the 82C501 AD between its
TXD input and TRMTITRMT output as shown in Figure 3. If the signal applied to the ENETV1 input is
inactive high, the TRMT differential output is kept at
high differential for 200 ns, after the last transmit
data transition, then it is gradually reduced. The
TRMTITRMT differential voltage will become less
than 40 mV within t18 after the last positive transition. The undershoot for return to idle is less than
100 mV differentially. This mode of operation is compatible with the IEEE 802.3 transceiver specifications.

If an active signal is present at the ENETV1 input at
the end of transmission, the TRMTITRMT pair output will. remain at a high differential voltage. As a
result there is a positive differential voltage during
the entire transmit idle time. This mode of operation
is compatible with the Ethernet Version 1.0 specification.
Immediately after the end of a transmission all signals on the receive pair are inhibited for 5 J.l-s minimum to 7 J.l-s maximum (when NOOR = 1). This
dead time is required for proper operation of the
SQE (heartbeat) test.
An internal watchdog timer is started when TEN is
asserted low at the beginning of the frame. The duration of the watchdog timer is 25 ms ± 15%. If the
transmission terminates (by deasserting the TEN)
before the timer expires, the timer is reset (and
ready for the next transmission). If the timer expires
before the transmission ends, the frame is aborted.
The frame is aborted by disabling the output driver
for the TRMTITRMT pair. RXD and RXC are not
affected. The watchdog timer is reset only when the
TEN is deasserted.

1-248

intJ

82C501AD ETHERNET

The cable driver is a differential circuit requiring external pulldown resistors of 240n ± 5%. In addition,
high-voltage protection to + 10V maximum, and
short circuit protection to ground is provided.
To provide additional high voltage protection if the
cable is shorted, an isolation transformer can be
used to isolate the TRMT and TRMT outputs from
the transceiver cable. Transmit circuit inductance
(including the IEEE 802.3 transceiver transformers)
should be a minimum of 27 ,...H. We recommend that
the transformer at the 82C501AD end have a minimum inductance of 75 ,...H.

+5V

_vee
TXC
TEN
TXD
ENETVI

TXC
RTS
TXD
CTS

RECEIVE SECTION
Cable Interface
The 82C501AD input circuits can be driven directly
from the Ethernet transceiver cable receive pair. In
this case the cable is terminated with a resistor of
78n ± 6% for proper impedance matching. See Figure 4.
The signal received on the RCV/RCV pair from the
transceiver defines both the RXC and RXD outputs
to the Intel LAN Controller. The RXC and RXD signals are recovered from the encoded RCV /RCV pair
signal by the Manchester decode circuitry.

GND
TRMT

TRMT
NOOR
RXC
CRS
RXD
CDT

RXC
CRS
RXD
CDT
INTEL
LAN
CONTROLLER

RCV

s
c
e

82C501AD
ESI

I
y

e
r

LOOP BACK
INPUT FROM PROCESSOR

n
t

a
c
e

COLLISION PAIR

231926-4

NOTE:

Cl = C2 = 22 pF to 35 pF.
For best operation, a decoupling capac;itor should be used between Vee and GND.

Figure 4. LAN Controlier/82C501AD/Transceiver Interface

1-249

intJ

82C501AD ETHERNET

The input circuits can also be driven with ECl voltage levels. In either case, the input common mode
voltage must be in the range of O-Vee volts to allow
for wide driver supply variation at the transceiver. To
provide additional high voltage protection, if the cable is shorted, an isolation transformer can be used
to isolate the RCV and RCV inputs from the cable.

Manchester Decoder and Clock
Recovery
The Manchester-encoded data stream is decoded to
separate the Receive Clock (RXC) and the Receive
Data (RXD) from the stream. The 82C501 AD uses
an advanced digital technique to perform the decoding function. The use of digital circuitry instead of
analog circuitry (e.g., a phase-lock loop) to perform
the decoding ensures that the decoding function is
less sensitive to variations in operating conditions.
A simplified diagram of the decoder appears in Figure 5. A high-resolution phase reference is used to
digitize the phase of the incoming data bit-center
transition. The digitizer has a phase resolution of
1/32 bit time.
The digitized phase is filtered by a digital low-pass
filter to remove rapid phase variations; i.e., phase

10 MHz

O~C:.::;LO::..:C~K,--_~

MANCHESTER
ENCODED
DATA

HIGH RESOLUTION
PHASE
REFERENCE

jitter. Slow phase variations, such as those caused
by small differences between the data frequency
and the clock frequency, are passed unfiltered by
the low-pass filter.
The RXC generator digitally sets the phases of the
two RXC transitions to respectively lead and lag the
bit-center transition by 1/4 bit time. RXC is used to
recover RXD by sampling the incoming data with an
edge-triggered flip-flop.
The Frame_Detect signal informs the decoder that
the first valid negative transition of a new frame has
been detected. This signal is used to initiate the
lock-on sequence of the decoder. lock is achieved
by reducing the time constant of the digital filter to
zero at the start of a new frame. With a· time constant of zero, the filter immediately outputs the
phase of the second bit-center transition. Any uncertainty in the bit-center phase of the first transition
that is caused by jitter is subsequently removed by
gradually increasing the filter time constant during
the following preamble. By that time, the exact
phase of the bit center is output by the filter,and the
lock is achieved. lock is achieved within the first 14
bit times as seen by the RCV /RCV inputs. The maximum bit-cell timing distortion ijitter) tolerated by the
Manchester Decoder Circuitry is ± 12 ns for the preamble and ± 18 ns for the data.

t---------,

,...........l"-....,

RXD

~---------~--~~D
FRAME
DETECT O

----------4I.------......J
Figure 5. Manchester Decoder

1-250

231926-11

inter

82C501AD ETHERNET

• The filter is turned on again when no positive
transition is observed on the RCV or CLSN pair
for 160 ns;

COLLISION-PRESENCE SECTION
The CLSN/CLSN input signal is a 10 MHz +25%1
-15% square-wave generated by the transceiver
whenever two or more data frames are superimposed on the coaxial cable. The pulse width of the
CLSN/CLSN signal can be no less than 35 ns and
no greater than 70 ns measured at the O-V crossing.
The common-mode voltage and external termination
are identical to the RCV /RCV input. (See Figure 4.)
A valid collision presence signal will assert the
82C501AD COT output, which can be directly tied to
the· COT input of the Intel LAN Controller. During
normal operation the 82C501 AD logically "ORs" the
collision presence signal with an internal signal, indicating valid data reception on the RCV/RCV pair, to
generate CRS output. If, however, the NOOR input
is asserted low, this "OR" function is removed and
CRS is only asserted by the presence of valid data
on the RCV IRCV pair. This mode of operation is
required for repeater design.
During the time that valid collision-presence transitions are present on the CLSN/CLSN input, invalid
data transitions may be present on the receive data
pair due to the superposition of signals from two or
more stations transmitting simultaneously. It is possible for RCV IRCV to lose transitions for a few bit
times due to perfect cancellation of the signals; this
may cause the 82C501 AD to abort the reception.
The CRS signal is asserted low (along with COT)
whenever a valid collision-presence signal is present
and NOOR = 1. If this collision-presence signal arrives within 5 JLs to 7 JLs after the last transmission,
only COT is generated. This ensures that the LAN
Controller recognizes the active COT as a valid SOE
(heartbeat) test Signal.

Internal Loopback
When asserted, LPBK causes the 82C501AD to
route serial data from its TXD input through its transmit logic (retiming and Manchester encoding); returning it through the receive logic (Manchester decoding and receive clock generation) to RXD output.
The internal routing prevents the data from passing
through the output drivers and onto the transmit output pair TRMT ITRMT. When in loop back mode all of
the transmit and receive circuits, are tested except
for the transceiver cable output driver and input receivers. Also, at the end of each frame transmitted
in loopback mode the 82C501AD generates the
SOE test (heartbeat) signal within 1 JLs after the end
of the frame. Thus, the collision circuits are also
tested in loopback mode. During loop back, as in any
normal reception, the 82C501AD receive circuitry
uses 14 bit times while the Manchester Decoder
locks on the data. As a result, the first 14 bits are
lost and RXC is held low during that time.
The watchdog timer remains enabled in loopback
mode, terminating test frames that exceed its timeout period. The watchdog timer can be inhibited by
connecting LPBK to a 1 k.!1 resistor connected to 10
to 16V. The loopback feature can still be used to test
the integrity of the 82C501 AD by using the circuit
shown in Figure 6.

+10Vto+16V

Vee
82C501AD

.--_-1

NOISE FILTERING ON RCV AND
CLSN PAIRS

WDTD

Both the receive and collision pairs have the following characteristics.

LPBK

LPBK/WDTD

231926-6

• At idle, the noise filter is turned on.

• ~ Open Collector

• A pulse is rejected if:
a. Its peak voltage is more positive than -150 mY,
with no restriction on width, or:

LPBK

WDTD

b. Its peak voltage is more positive than -600 mV
and its width is less than 5 ns (measured at a reference level of - 285 mY).

LPBK mode

Normal mode

Normal mode with
watchdog timer disabled

• The filter is turned off by the first valid negative
pulse on the RCV or CLSN pair. A pulse whose
peak voltage is more negative than -300 mV
and whose width is greater than 30 ns (measured
at - 285 mY) is considered valid.

Function

Figure 6. Watchdog Timer Disable
The 82C501AD operates as a full-duplex device, being able to transmit and receive simultaneously. By

1-251

82C501AD ETHERNET

combining the internal and external loop back modes
of the Intel LAN Controller, and the internal loopback and normal modes of the 82C501AD, incremental testing of an Intel LAN Controller/
82C501AD-based interface can be performed under
program control for systematic fault detection and
fault isolation.

If additional high voltage protection is desired, a
pulse transformer should be included for Ethernet
applications. IEEE 802.3 10BASE5 (Ethernet) specifications require at least 16V protection for the
Transmit, Receive, and Collision pairs. In 10BASE2
(Cheapernet) a pulse transformer is required to be
inserted between the DTE (Intel LAN Controller/
82C501AD) and the transceiver. In an Ethernet!
Cheapernet design, a single transformer can be
used for both connections at minimal additional cost.

Interface Example
The 82C501 AD is designed to work directly with the
Intel LAN Controller in IEEE 802.3 10 Mb/s, as well
as other 10 Mb/s LAN applications. The control and
data signals connect directly between the two devices without the need for additional external logic. The
complete Intel LAN Controller/82C501AD Ethernet
Transceiver interface is shown in Figure 4. The
82C501AD provides the driver and receivers needed
to directly connect to the transceiver cable or requiring only terminating resistors on each input signal
pair and 2400 pull-down resistors.

The pulse transformer should have the following
characteristics:
1. A minimum inductance of 75 pH
2. 2000V isolation between primary and secondary
windings.
3. 2000V isolation between primaries of separate
transformers.
Since Ethernet Version 1.0 transceivers can require
a positive differential on the TRMT pair during idle,
check with the transceiver vendor before including
the pulse transformer.

It is recommended that a decoupling capacitor be
used between Vee and GND.
The Transmit, Receive, and Collision pairs have a
maximum 10V overvoltage protection.

1-252

intJ

82C501AD ETHERNET

ABSOLUTE MAXIMUM RATING*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

+ 85·C
+ 140·C

Case Temperature Under Bias ....... O·C to
Storage Temperature .......... -65·C to

All Output and Supply Voltages ..... - 0.5V to
All Input Voltages ............. -1.0V to

• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

+ 7V .

+ 6.0V(1)

Operating Power Dissipation ............... 0.75W

D.C. CHARACTERISTICS

Tc = O·Cto

. Symbol

+ 85·C, Vcc =

5V ±10%
Min

Max

VIL

Input Low Voltage

Parameter
TTL
MOS

-0.5V
-0.5V

0.8V
0.6V

VIH

Input High Voltage

TTL
MOS

2.0V
3.9V

VACCEPT

Differential Input Accept Voltage

VREJECT

Differential Input Reject Voltage

VCM

Input Common Mode Voltage

VOCM

Common Mode Output Voltage(2)

VOL

Output Low Voltage

VOH

Output High Voltage (MOS)

IOL

IOH

+ 0.5V
+ 0.5V

±285 mV
±150 mV
OV

VCC

0.5V

5.0V
0.45V

4 mA

Vcc
Vcc

-500,...A

3.9V
±0.45V

±1.2V

VOOF

Differential Output Voltage(2)

TRMT Pair Differential Return to
Zero Undershoot(2)

-100 mV

VOl

TRMT Pair Differential Idle Voltage(2)

±40 mV(5)

= OV to VCC<3)
= 85·C(4)

III

Input Leakage Current @ VIN

±10,...A

Icc

Power Supply Current

135mA

ISp

Short Protection Activation Current

Input Load Current(6)

CIN

Input Capacitance

60mA

150mA
±1mA

1 MHz(7)

NOTES:

10pF

1. The voltage levels for CLSN/CLSN, RCV/RCV inputs are -0.75V to + 10V.
2. The testing load is a 780 ± 1% resistor in parallel with a 27 ",H ± 1% inductor and two 2400 ± 5% pulldown resistors.
3. Applies to TXD and TEN pins.
4. Part of the power is dissipated through the pulldown resistors connected to the TRMT /TRMT outputs.
5. Measured after t18 has expired.
.
6. Applies to RCV/RCV, X1, CLSN/CLSN, LPBK/WOTO, NOOR, and ENETVl inputs for input voltages from OV to Vee.
7. Characterized, not tested.

1-253

Intel

82C501AD ETHERNET

Clock Timing(1)

A.C. MEASUREMENT CONDITIONS
1. TC = p·Cto

+ 85·C, VCC

SYlllbol

= 5V ±10%.

2. The AC MaS, TTL and differential signals are referred to in Figures 7, 8, 9, 10 and 10A.
3. AC Loads:
a) MaS: a 20 pF total capacitance to ground.
b) Differential: a 10 pF total capacitance from
each terminal to ground, two 240.0. ±5% pull
down resistors, and a load resistor of 78.0.
± 1% in parallel with a 27 p.H ± 1% inductor
.between terminals.

Parameter

Min

Max

Unit

49.995

50.005

Xl Cycle Time

Xl Fall Time(2)

Xl Rise Time(2)

Xl Low Time(2)

Xl High Time(2)

NOTES:

1. Refer to Figure g.
2. Applies to external clock inputs.

4. All AC Parameters become valid 100 P.s after the
supply voltage has stabilized.

TRANSMIT TIMING(1)
Symbol

Parameter

Min

Max

Unit

99.99

100.Q1

TXC Cycle Time(2)

TXC Rise/Fall Time

TXD Rise/Fall Time

TXC Low Time

t10

TXC High Time

Transmit Enable/Disable to TXC Low

t12

TXD Stable to TXC Low

45
45 ;.,

t13

Bit Cell Center to Bit Cell Center of Transmit Pair Data(3)

t14
t15
t16
t17
tlB

ns
100.5

TEN Rise/Fall Time

Transmit Differential Signal Rise/Fall Time

5.0

50.5

Bit Cell Center to Bit Cell Boundary of Transmit Pair Data(3)
TRMT held low from Last Positive Transition of the
. Transmit Pair at the End of Frame
From Last Positive Transition of Transmit Pair Differential
Output Approaches Within 40 mV of zero volts.

NOTES:

1. Refer to Figure 11.
2. This parameter is exactly twice tl'
3. Characterized, not tested.
.

1-254

99.5

49.5
200

ns
8000

82C501AD ETHERNET

RECEIVE TIMING(1)
Symbol

Parameter

Max

Unit

1400

Receive Pair Bit Cell Center Jitter in Preamble(2)

±12

t22

Receive Pair Bit Cell Center Jitter in Data(2)

±18

t23

Receive Idle Time after Transmission in a Transmitting Station

t24

Receive Pair Signal Return to Zero Level from Last Valid
Positive Transition

t25

CRS Assertion Delay from the First Received Valid Negative Transition
of Receive Pair Signal

100

t26

CRS Deassertion Delay from the Last Valid Positive Transition Received
(when no Collision-Presence Signal Exists on the Transceiver Cable)(3)

300

t27

RXC Cycle Time

104

t2B

RXC Rise/Fall Time

5.0

t29

RXC Low Time

t30

RXC High Time

t31

Receive Data Stable Before the Negative Edge of RXC

t32

Receive Data Held Valid Past the Negative Edge of RXC

t33

Carrier Sense Active

t34

Receive DaIa Rise/Fall Time(5)

t35

CRS Inhibit Time After Frame Transmission(4)

t19

Duration which the RXC is held at Low State at the Start of a Packet

t20

Receive Pair Signal Rise/Fall Time(5)

t21

Min

/Ls

160

Inactive Hold Time from RXC High

10
5

fJ-s

NOTES:
1. Refer to Figures 12 and 13.
2. Measured per B02.3 Para B1.1.4.2 recommendations.
3. CRS is deasserted synchronously with the RXC. This condition is not specified in .the IEEE B02.3 specification.
4. Required for SQE test. Applies when NOOR = 1. For NOOR = 0 there is no inhibit of CRS.
5. Characterized, not tested.

1-255

82C501AD ETHERNET

COLLISION TIMING(1)
Symbol

Parameter

Min

Max

Unit

118

t36

CLSN/CLSN Cycle Time

t37

CLSN/CLSN Rise/Fall Time(2)

t38

CLSN/CLSN High/Low Time

t39

CLSN Pair Return to Zero from Last Positive Transition

160

t40

COT Assertion from the First Valid Negative Edge of Collision Pair Signal

t41

COT Deassertion from the Last Positive Edge of CLSN/CLSN Signal

300

CRS Deassertion from the Last Positive Edge of CLSN/CLSN Signal (if no
Post·Collision Signal Remains on the Receive Pair)

450

Max

Unit

NOTE:
1. Refer to Figure 14.
2. Characterized, not tested.

LOOPBACK TIMING(1)
Symbol

Parameter

Min

LPBK asserted before the first attempted transmission (2)

500

Simulated collision test delay from the end of each attempted transmission

0.5

1.5

J.Ls

Simulated collision test duration(3)

0.6

1.6

J.Ls

LPBK deasserted after the last attempted transmission

J.Ls

NOTES:
1. Refer to Figure 15.
2. In Loopback mode, RXC and CRS function in the same manner as a normal Receive.
'
3. SQE test (heartbeat) signal

NOISE FILTER(1)
Symbol
t47

Parameter

Min

RCVIRCV Noise Filter Pulse Width Rejected

RCV I RCV Noise Filter Pulse Width Accepted

CLSN/CLSN Noise Filter Pulse Width Rejected

t50

CLSN/CLSN Noise Filter Pulse Width Accepted

NOTE:
1. Refer to Figure 16.

1·256

Max

Unit

5
25

ns
ns

intJ

82C501AD ETHERNET

A.C. TIMING CHARACTERISTICS
2.4V

,--_ _

-X. .

2.0V· - - - 1.5V· - - - - -, •
O.BV • - - - - - !
O.45V
•••' - - - -

3.0V· - - - -

...

-X-

O.9V • - - - - -. -

10.._ __

DELAY/WIDTH MEASUREMENT-,- •
RISE/FALL MEASUREMENT-

231926-13
231926-12

Figure 7. TTL Input Voltage Levels for Timing
Measurements (TEN, TXD, LPBK/WDTD).

Figure 8. Voltage Levels for MOS Level
Output-Timing Measurements
(TXC, RXC, CRS, CDT, and RXD).

3.9V· - - - -,..---...,.
3.0V, - - - -

2B~mV
t ____ _

O.9V· - O.45V

----·OV

DELAY/WIDTH MEASUREMENTRISE/FALL MEASUREMENT .....

231926-14

231926-15

Figure 9. X11nput Voltage Levels
for Timing Measurements

Figure 10. Voltage Levels for
Differential-Input Timing Measurements
(RCVIRCV and CLSN/CLSN).

----·OV

DELAY/WIDTH MEASUREMENT-~
RISE/FALL MEASUREMENT-

231926-16

Figure 10A. Voltage Levels for TRMTITRMT
Output-Timing Measurements

1-257

intJ

82C501AD ETHERNET

TRANSMIT TIMING

L["J J-:~-----TXD

'\i:§ij

I--.....--O-J~

1/0

~~+
1·\16T\~6T \~'I
_~-----+1'1

T R M T - - - - - -.....
TRMT(LAST BIT= 1)

+
1

1~l!L5 ~l!L5~

0 II

E~\18----....1

. ~).
- C~)(::x:::::~:::;=::;=:::::r---l
+ - -+1

_
TRMT
(LAST BITTRMT,
= 0) _

231926-5

Figure 11

RECEIVE TIMING: START OF FRAME

RCV~+
RCV

t20

t19----t25---1

-+--""' i

~--~l--------~------------~--------

RXD

231926-7

Figure 12

1-258

82C501AD ETHERNET

RECEIVE TIMING: END OF FRAME

01
-

~\oT----------1(:f

RCV(LAST 8IT=0)
RCV

~g~ (LAST

==x

I
+

81T = 1)

0 +

I-

+
CRS

1 +
+

E~4

1------\23

HH---

C\24::j

t 26

••

_ _ _ _ _ _ _ _ _ _JI

1------ t 35

o
RXD

----IJ -------

1 t33

~ ___ ~_/
231926-8

Figure 13

COLLISION TIMING
1--+---\39---+1'.1

---

CLSN
CLSN

\42-----j

CRS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~\~r----231926-9

Figure 14

1-259

82C501AD ETHERNET

LOOPBACK TIMING

"1"

"0"

"1"

"0"

"1"

__n_J--i?:---::-:-:=:+-t----

TXD

--~-F""-'\

COT

------------------------------~----------~~~

- -__________________

~~-.J

\~----------~n---------JI
I "1" I "0" I "1" I
I "1"
~D------------------~~~~r-~-231926-10

Figure 15

NOISE FILTER TIMING
Rejected Pulse

Accepted Pulse
300 mY
- - - 285 mY

OY
-.600mY---

231926-17

Figure 16. Noise Filter Characteristics

1-260

231926-18

82C501AD ETHERNET

20 LEAD CERDIP DUAL IN-LINE PACKAGE INTEL TYPE D

BASE
PLANE
SEATING

,PLANE

231926-20

Family: CerDIP Dual-In-Line Package

Max

Min

Inches

Millimeters

Symbol

O·

Notes

Min

O·

10·

5.08

A
A1

0.38

3.56

0.200
0.Q15

4.24

0.140

0.167

3.56

4.24

0.140

0.167

0.41

0.51

0.Q16

0.020

1.52

0.23

24.38

0.060

Typical

0.30

Typical

0.009

25.27

Reference

0.960

22.86

Typical

0.012
0.995

' Reference

7.62

8.13

0.300

0.320

7.11

7.90

0.280

0.31

2.29

0.090

2.79
7.87

0.110
0.310

Reference

8.13

10.16

0.320

0.400

3.18

3.81

0.125

0.150

0.38

0.13

ISSUE

% Leads

N
S

0.005

IWS 1/15/87

1-261

% Leads

20
0.Q15

1.78

Typical

0.900

Reference

Notes

Max

0.070

82C501AD ETHERNET

PLASTIC LEADED CHIP CARRIER RECTANGULAR

(ALL FOUR SIDES)

_rA
Ne

t~['

-A--

MM(INCH)

SEATING PLANE

-C-

231926-21

Dimension

28 Lead (Inch)

28 Lead (mm)

Min

Max

Min

Max

Overall Height (A)

0.126

0.140

3.20

3.56

Shoulder to Board Height (A1)

0.076

0.090

1.93

2.29

Outside Dimension (D)

0.385

0.396

9.78

10.0

Plastic Body Oimension (01) .

0.347

0.353

8.81

8.97

FootPrint (02)

0.290

0.330

7.37

8.38

0.200 Ref.

Foot Print (Os)

5.08 Ref.

Outside Dimension (E)

0.585

0.595

14.9

15.1

PlaticBody Dimension (E1)

0.547

0.553

13.9

14.0

Foot Print (E2)

0.490

0.530

12.4

13.5

Foot Print (Es)

0.400 Ref.

10.2 Ref.

# of Leads (N)

# of Leads on Short Side (Nd)

# of Leads on Long Side (N e)

Seating Plane Coplanarity (CP)

0.000

0.004

0.00

0.10·

Tweezing Coplanarity (TCP)

0.000

0.004

0.000

0.10

Lead Thickness (LT)

0.009

0.015

0.23

0.38

Issue

IWS 1/15/87

1-262

82521TB
TWISTED PAIR ETHERNET* SERIAL SUPERCOMPONENT
Provides Complete Serial and Analog
• Twisted
Pair Ethernet Interface
-

Analog Filters
Serial Interface and Transceiver
Manchester Encoder and Decoder
Link Integrity
Line Drivers and Receivers
Jabber Protection
Isolation Transformers and
Protection Circuitry

Designed to IEEE 802.3 Draft
• Supplement,
Type 10BASE-T
(P802.3I1D 10)

•
•

10-Mb/s Operation
Directly Interfaces Intel Ethernet LAN
Controllers and Coprocessors
-82586
- 82590 and 82592
- 82596CA, 82596DX, and 82596SX

Compatible with the 82521TA
• Socket
No Configuration Required
• Allows
• StandardDesign to Meet FCC Class A
• All Circuitry in a Single 36-Pin Package

The Twisted Pair Ethernet Serial Supercomponent (SSG) provides the complete serial and analog Twisted Pair
Ethernet interface required to connect the Ethernet LAN controller directly to a 10BASE-T connector. It is
designed for node applications in 10-Mb/s, CSMAlCD networks as defined by the IEEE 802.3-1985 standard;
for example, PCs, workstations, and fileservers. The SSC includes the serial interface, transceiver, Manchester encoder, Manchester decoder, 10BASE-T functionality, line drivers, line receivers, analog filters, protection
circuitry and isolation transformers in a single package. It provides all the required circuitry to give the LAN
designer immediate access to the twisted pair Ethernet environment (10BASE-T).
Existing EthernetiCheapernet designs can be easily modified to take advantage of cost-effective twisted pair
wire. The SSC can be soldered or socketed onto a host adapter card or motherboard without any adjustments
or configuration. It is compatible with the pending IEEE 802.3 draft standard 10BASE-T, and can be used with
non-Intel LAN controllers. The SSC is designed to satisfy FCC class A test requirements and to meet all
standard host-system size and power requirements.

Jobber
Protection

Link
Integrity

TxD

TD+
Line

TxC

Drivers

EMI
Filter

TD-

EMI
Filter

RD+

RTS

RxC

RxD
CRS

Manchester
Decoder and
Clock Recovery

Line
Drivers

RD-

CDT

ECLK
ICLK
290259-1

Figure 1. 82521TB Block Diagram
'Ethernet is a registered trademark of Xerox Corporation.

1-263

September 1990
Order Number: 290259-003

82521TB

CRS
RxO
CTS

Vss
TxO
Vss
TxC
Vss
VEE
RxC
Vss
EClK
IClK
1.I0/WOTD·
MENC·
lPBK2
WO~

Vss

36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19

2
3
4
5
6
7
8
9

82521TB

10
11
12
13
14
15
16
17
18

VCC2
Vec1
COT
N/C*
N/cf
t

RORD+
TOTO*
t
LI

RESET
Vss
TEST
N/C
lPBKl
RTS
290259-2

·Pins 14, 15, and 17 have been enhanced since the 82521TA. This does not affect compatibility with the 82521TA.
tPins 26 and 31 have been removed for improved electrical isolation. This does not affect compatibility with the
82521TA.
+The 12·V power requirement of the 82521 has been removed on the 82521TB. To maintain socket compatibility these
pins are not connected internally; they can be connected to a power supply on the host card or left floating.

Figure 2. 82521T8 Pin Configuration
Pin

Symbol

Type

CRS

CARRIE.R SENSE: Active low output that alerts the Ethernet
controller or coprocessor (82586, 82590, 82592, or 82596) that
activity is present on the twisted pair link. This pin is directly
connected to the CRS input of the controller.

RxD

RECEIVE DATA: NRZ data passed to the Ethernet controller. This
pin is directly connected to the RxD pin on the controller.

CTS

CLEAR TO SEND: An active low output that alerts the Ethernet
controller that the device is ready to accept data. This function is
optional. This pin can be tied directly to the controller's CTS pin or
left floating.

Vss

TxD

Name and Function

GROUND.

TRANSMIT DATA: NRZ or Manchester encoded serial data is
clocked in on TxD from the Ethernet controller. This pin is directly
connected to the TxD pin of the controller. The state of the MENC
pin determines NRZ or Manchester encoded input.

1·264

82521TB

Symbol

Name and Function

Type
GROUND.

VSS

TxC

Vss

GROUND.

VEE

VEE: A - 5 V ± 10% power supply.

RxC

TRANSMIT CLOCK: A 1O-MHz clock output tied directly to the
TxC pin of the Ethernet controller.

RECEIVE CLOCK: A 1O-MHz clock connected directly to the RxC
input of the Ethernet controller. This clock is the recovered clock
from the incoming data on the twisted pair.
GROUND.

Vss

ECLK

ICLK

INTERNAL CLOCK: A 20-MHz ± 0.01 %, TTL-level output clock
with a 40/60 duty cycle. For normal asynchronous operation this
pin is directly connected to ECLK. ICLK can be used for
synchronous operation of interface circuitry.

L1D/WDTD

LINK INTEGRITY DISABLE, WATCHDOG TIMER DISABLE:
When connected to VCC1, this pin disables the link integrity
processor, linkbeat generator, and watchdog timer. This ensures
compatibility with the 82521TA. When connected to Vss, or not
connected, these functions are enabled and the device is
compatible with 10BASE-T.

MENC

MANCHESTER ENCODING: When tied to Vss, or not connected,
this pin enables internal Manchester encoding of the NRZ data on
TxD. When tied to VCC1, Manchester encoded data is expected on
TxD.

LPBK2

LOOPBACK 2: An active high input signal that causes the
82521TB to enter diagnostic loopback mode. The twisted pair
medium will be removed from the Circuit, thus isolating the node
from the network. When not connected this pin assumes the
inactive (normal) state. Diagnostic loopback mode does not affect
the operation of the link integrity processor or linkbeat generator.
The watchdog timer will not operate in diagnostic loop back mode.

WDT

WATCHDOG TIMER: An active high output that indicates
expiration of the watchdog timer (jabber protection) in the supercomponent. The output de asserts when the jabber function is
reset.

EXTERNAL CLOCK: A 20-MHz ± 0.01 %, TTL-level input clock
with a 40/60 duty cycle. ECLK attaches to ICLK for normal
asynchronous operation. Synchronous operation of the device can
be obtained by connecting an external clock to ECLK.

Vss

RTS

REQUEST TO SEND: An active low input signal synchronous to
TxC; it enables data transmission on the twisted pair link segment.

LPBK1

LOOPBACK 1: An active low input signal that causes the 82521TB
to enter diagnostic loopback mode. The twisted pair medium will
be removed from the circuit, thus isolating the node from the
network. When not connected this pin assumes the inactive
(normal) state. Diagnostic loopback mode does not affect the
operation of the link integrity processor, or linkbeat generator. The
watchdog timer will not operate in diagnostic loopback mode.

GROUND.

1-265

InIeI
Pin

82521TB

Symbol

N/C

Reserved

Type

Name and Function
This pin is not connected.

This pin is used for testing purposes. It should be left floating or
connected to VSS.

VSS

Reset

GROUND.
RESET: An active high input that brings the device into a known
state. It must be asserted for 1 ms while the clock is running.

LINK INTEGRITY: An active. high output used to indicate the
presence of link integrity faults.

TD+

TWISTED PAIR TRANSMIT DATA: This pin transmits outgoing
Manchester data to the twisted pair link segment. It is connected
directly to the Medium Dependent Interface Connector (RJ-45) pin
1. This pin, and the trace leading to it, must withstand 2250 V dc to
ground without damage.

TO-

TWISTED PAIR TRANSMIT DATA COMPLEMENT: This pin
transmits outgoing inverted Manchester data to the twisted pair
link segment. It is connected directly to the Medium Dependent
Interface Connector (RJ-45) pin 2. This pin, and the trace leading
to it, must withstand 2250 V dc to ground without damage.

RD+

TWISTED PAIR RECEIVE DATA: This pin receives incoming
Manchesterdata from the twisted pair link segment. It is
connected directly to the Medium Dependent Interface Connector
(RJ-45) pin 3: This pin, and the trace leading to it, must withstand
2250 V dc to ground without damage.

RD-

TWISTED PAIR RECEIVE DATA COMPLEMENT: This pin
receives incoming inverted Manchester data from the twisted pair
link segment. It is connected directly to the Medium Dependent
. Interface Connector (RJ-45) pin 6. This pin, and the trace leading
to it, must withstand 2250 V dc to ground without damage.

32
33

N/C
N/C

CDT

VCCl

VCC1:A5V ±5% power supply.

VCC2

VCC2: A 5 V ± 10% power supply. This pin can be connected to
pin 35 (VCC1) if a single power supply can reliably supply the
combined requirements of ICCl and ICC2 (see DC Characteristics).

This pin is not connected ..
This pin is not connected.

COLLISION DETECT: An active low signal that indicates the
presence of a collision to the controller.

1-266

Intel

82521TB

FUNCTIONAL DESCRIPTION
Overview
The 82521TB provides the functions required for operating Data Terminal Equipment on a 10-Mb/s,
CSMAlCD, local Area Network (LAN) using standard telephone building wiring. The 82521TB design
is based on the Twisted Pair Ethernet draft standard
supplement to IEEE Std. 802.3 (type 10BASE-T,
P802.31/D8).

Clock Generation
The 82521 TB supports internal and external sources
for the precision clock (20 MHz ± 0.01 %) required in
an Ethernet environment. The clock is used to retime the transmitted Manchester data, to generate
the 1O-MHz TxC signal, and as a precision reference
for Manchester decoding and clock recovery of received data.
If IClK (Pin 13) is strapped to EClK (Pin 12) an
onboard clock oscillator generates the precision
clock. This clock can be used for synchronous operation of circuits on the host board; however, care
must be taken to minimize the load on the clock. The
supercomponent can be operated synchronous to
the host by providing EClK with a 20-MHz ± 0.01 %,
TIL-level clock with a duty cycle of 40/60 or better.

Transmit Section
The transmit section of the 82521TB is controlled by
the RTS signal generated by the Ethernet lAN controller (Intel's 82586, 82592, etc). When RTS asserts, the 82521TB begins clocking in data from the

\f"li\1LSlbUlKAJUlKl~li\1 U

controller on the TxD input. The TxD level is sampled on the falling edge of the 1O-MHz TxC signal (or
every edge if Manchester encoding is not enabled).
The data is then encoded using the precision
20-MHz clock, and then sent to the twisted pair line
drivers.
The line drivers begin transmitting the serial Manchester bit stream two bit times after the assertion of
RTS. A predistortion algorithm is used by the line
drivers to improve jitter performance on the twisted
pair. The line drivers reduce their drive level during
the second half of "fat" (100 ns) Manchester pulses,
and maintain full drive level during all "thin" (50 ns)
pulses. During the "fat" pulses, this reduces line
overcharge, which is a major source of jitter.
Figure 3 shows the difference between the familiar
coax cable waveform and the predistorted waveform
generated by the 82521TB. The line drivers maintain
a characteristic impedance of 96 n typical throughout data packet transmission and the idle state.
The predistorted output of the line drivers is then
passed through the transmit EMI filter to reduce the
high frequency harmonics of the transmitted signal.
This reduces noise, Near End Cross Talk (NEXT) in
bundled twisted pair cables, and unwanted Radio
Frequency (RF) interference. The filter maintains the
96 n (typical) characteristic impedance. The filtered
signal then passes through an isolation transformer
and common mode choke. These provide high voltage protection, dc isolation, and common mode
noise rejection. The output of the common mode
choke is directly connected to the TD+ and TDpins. These can be connected to pins 1 and 2 of an
ISO 8877 (RJ-45) connector.
After a successful transmission, the Signal_qualify_error test (heartbeat) function is executed in accordance with the 802.3 10BASE-T draft specification.

290259-3

Figure 3. Effects of Predistortion

1-267

Irl'el

82521T8

The link integrity function continuously monitors activity on the receive circuit. If neither valid data or link
test pulses are received for a period of time, the link
integrity processor declares the link bad, and disables transmission and reception on the medium.
Transmission of link test pulses and monitoring of
receive activity are not affected. The idle time required for the link integrity processor to determine if
the link is bad is between 50 and 150 ms.

Receive Section
The receive section of the 82521 TB processes incoming Manchester data from the twisted pair link
segment, converts it to NRZ data, and recovers the
embedded clock. It contains a squelch circuit· that
distinguishes noise from incoming data. Valid data
passes through the input protection and common
mode rejection of the 82521TB and the receive EMI
filter, and trips the squelch circuit. The twisted pair
line receiver is then enabled, and converts the signal
to digital voltage levels.

Once a frame, or a sequence of 2 to 10 consecutive
link test pulses, are detected, the link integrity processor declares the link good and reconnects the
transmitte~ and receiver.

The signal then passes to the Manchester decoder
and clock recovery circuit. CRS asserts within nine
bit times of the arrival of the data packet to indicate
the presence of activity on the network. Fourteen bit
times later Axe and RxD activate, passing the remaining preamble and data to the controller in NRZ
format.

Jabber Function.
The 82521TB has anonboard watchdog timer to implement the jabber function. If a transmission continues beyond the limits specified by the 10BASE~T
draft standard (between 20 and 150 ms), the jabber
function inhibits further transmission and asserts the
collision indicator COT. The transmission inhibit period extends until the 82521TB detects sufficient idle
time (between 250 and 750 ms) on the RTS signal.
Link test pulses continue to be sent during the period when the transmitter is disabled.
-

The 82521TB detects the Start-Of-Idle (SOl) signal
at the end of a packet. CRS will be synchronously
deasserted with RxC within four bit times from the
beginning of the SOL RxC and RxD then return to
their idle state.

Collision Detect
Diagnostic Loopback Mode

Collision detection in the twisted pair environment is
indicated by simultaneous transmission and reception on the twisted pair link segment. The COT signal
is asserted for the duration of both RTS and the
presence of received data; CRS is asserted for the
duration of either RTS or the presence of received
data.

The 82521TB supports a diagnostic loopback mode
in addition to the normal DO to 01 loopback mode.
When either LPBK1 or LPBK2 are asserted, data
transmission and reception on the twisted pair link is
disabled, thus removing the DTE from the network.
Any· transmissions made in this mode are fed back
into the receive circuits and subsequently passed
back to the controller. Diagnostic loopback mode
does not affect the link integrity function. Link test
pulses are still transmitted and the twisted pair link is
monitored for frames and link test pulse reception.

DO to 01 Loopback
When the 82521TB is transmitting on the TO circuit,
and not receiving on the RD circuit, it also routes the
transmitted data to the receive circuitry. It returns to
the controller via the CRS, RxC, and RxD signals.

State Diagrams
Link Integrity
The 82521TB supports the link integrity function as
defined in the 10BASE-T draft. During long periods
of idle on the transmitter, link test pulses will be
transmitted on to the twisted pair medium as an indication to the receiving MAU that the link is good.
These pulses will be transmitted between 8 and
24 ms after the end of the last transmission or link
test pulse.

The 82521TB operation is described in the following
four state diagrams: Transmit-Receive, SQE Test,
Jabber, and Link Integrity. They are based on the
state diagrams of the 1OBASE-T draft. These state
diagrams differ from those of the draft standard because the 10BASE-T specification addresses an external MAU with AUI cable, whereas the 82521TB
eliminates the AUI cable. Therefore, the state diagrams for the 82521TB reference its own interface
signals, not the AUI signals. Operation of the device
at the MOl connector (RJ-45) is identical.

1-268

inter

82521TB

FUNCTIONAL. DESCRIPTION (Continued)

IDLE

RTS = active
* RD = Idle

RD = active
* Isolate = false

*xmlt=en~

j.
OUTPUT

INPUT
RxD= RD

TD=TxD
RxD=TxD

RTS=I~~:l

RTS = active
t T S = Idle
• RD = active
+ xmit = disable
* Ipbk = false
* xmlt = enable
A

+ isolate = t r ' 0

RTS = active
• RD = active
* Isolate = false
* xmlt = enable

COLLISION
TD=TxD
RxD= RD
COT = SQE

I
RD = active * Isolate = false * RTS = Idle

RTS = active
* (RD = Idle + Isolate = true)

RTS=ldle
* (RD = Idle + Isolate = true)

A
290259-4

Figure 4. Transmit Receive State Diagram

1-269

inter

82521TB

FUNCTIONAL DESCRIPTION (Continued)
Power On

OUTPUT IDLE

RTS = active

OUTPUT DETECTED

RTS =idle

SQE TEST WAIT

StarLSQE_tesLwalLtimer

I
xmit = disable
• isolate = idle

SQLtesLwalt_timer_done
• (xmit = enabl e + isolate = active)

SQE TEST

StarLSQE_tesLtimer
SQE

I
290259-5

Figure 5. SQE Test State Diagram

1-270

inter

82521TB

FUNCTIONAL DESCRIPTION (Continued)
Power On

NO OUTPUT

RTS = active· Isolate = false
• WDTD = false

NON-JABBER OUTPUT

StarLxmiLmax_timer

RTS = idle

RTS = active· xmlLmax_timer_done
• WDTD = false· isolate = f olse

JAB
xmit = disable
Ipbk = disable
SOE

RTS = idle

UNJAB WAIT
starLunJab_timer
xmit = disable
Ipbk = disable
SOE

I
unjab_timer_done
+WDTD=true
+ isolate = true

I
RTS = active· unjab_tlmer_noLdone
·WDTD = false •
• isolate = false

Figure 6. Jabber Function State Diagram

1-271

290259-6

82521T8

FUNCTIONAL DESCRIPTION (Continued)
Power On

IDLE TEST
StarLilnk_loslLtlmer
StorLllnk_test-mln;;.tlmer
RD=octlve+
IInk_test-rcvd = true
°llnk_test-mln_tlmer_done

link_loss_timer_done ° LID = false

-"
LIN K TEST FAIL RESET

LINK TEST FAIL WAIT

IInk;;.count 0
xmlt = disable
rcv = disable
Ipbk = disable
RD = active

+ LID = true

IInk_test-rcvd - true
°LlD=false

xmlt - disable
rcv = disable
Ipbk = disable

RD = active
+ LID = true

IInk_test-rcvd = folie
LINK TEST FAIL
link_count = link_count + 1
storLllnk_test-mln_tlmer
storLllnk_teILmox_t1mer
xmlt disable
rev = disable
IInk.:..tesLmln_tlmer_done
Ipbk = disable
°llnk_test-rcvd = true
° LID =fol..

RD = active + UD = true
+ (IInLcount = Ic_max)
LINK TEST FAILEXTEND

(nnLtesLn'lClX.-timeLdone +
nnk.:..test-mln_tlmer_naLdone
°nnLtesLrcvd = true)
°UD=folse

xmlt = disable
rcv = disable
Ipbk = disable
.RD - Idle

RTS - Idle
290259-7

Figure 7. Link Integrity State Diagram

1-272

Intel

82521TB

The variable definitions contain a description of the
function they control as well as the possible values
for that variable. Many of the variables have a default value; when none of the state machines explicitlyassigns a particular variable a value, then that
variable implicitly takes on the default value. Several
constants are used and defined by either the 802.3
standard or the 1OBASE-T draft, these constants are
printed italic.

RxD

COT

UUL.::::IL=:IUUUUU,,'-IU""'\IIoI" "

Indicates the presence of an input
data stream from the network on
the RD circuit.
RD = active. Data is present on
the RD circuit.
RD = idle. Data is not present on
the RD circuit.
IinLtesLrcvd Indicates the presence of a link
test pulse on the RD circuit.
IinLtesLrcvd = true. A link
test pulse is present on the RD circuit.
IinLtesLrcvd = false. Silence or data is present on the RD
circuit.
IinLcount
Indicates the number of consecutive link test pulses received while
in a link-fail-state.
The maximum number of consecutive link test pulses required before reconnection is allowed.
xmit
Communication path between
state machines. This variable relates the status of certain fault
conditions that require the transmit and SOE functions to be disabled.
xmit = disable. A condition exists that dictates the transmit and
SOE test functions to be disabled.
xmit =; enable. Default. The
transmit and SOE test functions
operate normally.
rcv
Communication path between
state machines. This variable relates the status of certain fault
conditions that require the receive
function to be disabled.

State Diagram Variables

RTS

Indicates the presence of a data
stream being received from the
DTE on the TxD signal.
RTS = active. Data is present on
the TxD circuit.
RTS = idle. Data is not present on
the TxD circuit.
Controls the source of data transmitted to the DTE on the RxD circuit.
RxD = RD. Data on the RxD circuit
is sourced by the RD circuit input
from the twisted pair. The condition
"rcv = disable" overrides and disables this activity.
RxD = DO. Data on the RxD circuit
is sourced by the TxD circuit from
the DTE. This is the loopback function. The condition "Ioopback =
disable" overrides and disables this
activity.
RxD = idle. Default. There is no
data being transmitted on the RxD
circuit, it contains the input~dle
message.
Controls the message the 82521TB
sends to the DTE on the CDT signal.
COT = SQE. The MAU is sending
the signal_quality_error message
to the DTE on the CDT signal.
COT = idle. Default. the MAU is
sending the MAU--'1vailable message to the DTE on the CDT signal.
Controls the source of data transmitted to the network on the TD circuit.
TO = TxD. The TD circuit is
sourced by the TxD signal. The
conditions "xmit = disable" or
"isolate = true" overrides and disables this activity.

Ipbk

1-273

rcv = disable. A condition exists
that dictates that the receive function be disabled.
rcv = enable. Default. The receive function should operate normally.
Communication path between
state machines. This variable relates the status of certain fault
conditions that require the DO to
DI loopback function to be disabled.
Ipbk = disable. A condition exists that dictates that the loopback .
function be disabled.

82521TB

II I - e -

State Diagram T'imers

Ipbk
(continued)

Ipbk = enable. Default. The DO to
DI loopback function should oper·
ate normally.
.

Isolate

Indicates the status of the diagnos·
tic loopback mode of the 82521TB.
isolate = false. Device is not in di· .
agnostic loopback mode. Input
LPBK1 = 1 and LPBK2 = O.
Isolate = . true. Device is in diag· '
nostic loopback mode. Input LPBK1
= 0 or LPBK2 = 1.
Indicates the status of the watch·
dog timer disable mode of the

WDTD

82521TB.

LID

WDTD = true. Watchdog timer
(Jabber function) is disabled. Input
LlD/WDTD = 1.
WDTD = false. Watchdog timer is
enabled. Input LlD/WDTD =0.
Indicates the status of the link in·
tegrity disable mode of the

IIl1U LSl!:.UIKA.IUlKIC'.\li\l YI

IinLloss-tlmer. Time to wait to declare a bad reo
ceive link.
Iink...;.tesLmill-timer. Minimum time allowed be·
tween consecutive link test pulses.
'IinLtesL.max-timer. Maximum time allowed
between consecutive link pulses.
SQE_tesLwaiLtimer. Time to wait before exe·
cuting the ,SQE_test function.
SQE_tesLtlmer. Time to wait for completing the
SQE_test function.
xmILmax-tlmer. Time to wait to interrupt jabbering transmission.
unjab_tlmer. 'Time to wait before resetting jabber
function.

82521TB.

LID == true. Link integrity process
is disabled. Input LlD/WDTD = 1.
LID = 'false. Link integrity process
is enabled. Input LlD/WDTD = O.

1·274

Intel

82521TB

ABSOLUTE MAXIMUM RATINGS
Ambient Temperature Under Bias ..... 0° to
Storage Temperature ............ -65° to

+ 70°C

+ 140°C

All Output and Supply Voltages(1) .... -0.5 to
All Input Voltages(2) ........... -0.5 to VCC1

D.C. CHARACTERISTICS
Symbol

NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice.

+ 7V

+ 0.5V

* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

TA = 0° to 70°C, VCC1 = 5 V ±5%, VCC2 = 5 V ±10%

Min

Max

Units

Vil

Input Low Voltage (3)

Parameter

-0.3

0.8

Test Conditions

VIH

Input High Voltage (3)

2.0

VCC

III

Input Leakage Current

±400

/J- A

0.45

IOl = 4mA

10H= -500/J-A

-0.3 V s::: VI s::: VCC1

Val

Output Low Voltage (4)

VOH

Output High Voltage (4)

ICC1

Power Supply Current

410

VCC = 5.25 V

ICC2

Power Supply Current

105

VCC = 5.5 V

lEE

Power Supply Current

-40

VEE = -5.5 V

Power Dissipation

VCC = 5.0V

3.9

NOTES:

1.
2.
3.
4.

The voltage levels for TO + and TO - are ± 2250 V with respect to ground.
The voltage levels for RD + and RD - are ± 2250 V with respect to ground.
Digital Inputs, TxD, EClK, MENC, LlD/WDTD,lPBK2, RTS, lPBK1, TEST, arid RESET.
Digital Outputs, CRS, RxD, CTS, TxC, RxC, IClK, WDT, LI, and COT.

ANALOG CHARACTERISTICS
Symbol

T A = 0° to 70°C, VCC1 = 5 V

Parameter

= 5V

± 10%

Min

Max

Units

Characteristic Impedance(1 ,2)

115

5 MHz to 10 MHz

Return Loss(1, 2) (5 MHz to 10 MHz)

850 s::: RLOAD oS: 1110

300

Squelch Reject Level(2)
Squelch Accept Level(2)
CMR

± 5%, VCC2

Common Mode Rejection(1, 2)

VIDF

Input Peak Differential

VODF1

Output Peak Differential

450

0.500
2.2

1-275

Test Conditions

At 10 MHz

V
2.8

960 Load

••• 'eII

82521T8

ANALOG CHARACTERISTICS (Continued)
TA = 0° to 70°C, VCC1 = 5 V ±5%, VCC2 = 5 V ±10%
Symbol

Parameter

Min

Output Peak Differential

VODF2

Max

0.585

Maximum Overshoot

50
29

Transmitter Impedance Balance
Output Common Mode

VOCM

Harmonic Content

Units

Test Conditions

With Cable Model(3)

Start of Idle

At 10 MHz

>30 kHz

-27

:<:30 MHz

NOTES:
1. Pin 27 and 28 (TD+ and TD-).
2. Pins 29 and 30 (RD + and RD - ).
3. Cable Mode defined in 10BASE-T draft.

134.0n

2.32kn

14.0n

5.6pH

95.3n

14kn

1.0n

0.68pH

1.0n

95.3n

22.6 kn

95.3n
1.0n

560pF

649n

68 pF

11.3 kn 82 pF

+
96n Vo
10kn

82pF

TD-.-------4--------------4--------------~------------~------~

290259-8

A.C. Timing Conditions
1. TA = 0° to 70°C, VCC1 = 5 V ±5%, VCC2 = 5 V ±10%.
2. Digitial outputs timing measurement points are 0.9 V and 3.0 V unless otherwise noted.
3. Digitial input timing measurements paints are 0.8 V and 2.0 V unless otherwise noted.
4. TD Pair and RDPair timing measurements are 0 V unless otherwise noted.
5. Digital ac loads: 20 pF to ground.
6. TD+ and TD- load: 96

.n differential load.

CLOCK TIMING CHARACTERISTICS
Symbol

Parameter

ECLK/ICLK Cycle Time

ECLK/ICLK Rise and Fall Time

ECLK/ICLK High and Low Time

1-276

Min

Max

Units

49.995

50.005

intJ

82521TB

Decoder Timing Characteristics
Symbol

Parameter

Min

Max

Units

104

RXCPeriod

RxC High Time

RxCLowTime

RxC Rise and Fall Time(2)

RxD Setup Time to RxC Falling Edge

RxD Hold Time from RxC Falling Edge

ns
ns

tlO

RxD Rise and Fall Time(2)

tl1

Receiver Steady State Delay

t12
t13
t14

CRS Deassertion Delay from Last Valid RD Pair Edge(1)

t15

CRS Deassertion Hold Time from RxC High(1)

300

CRS Assertion Delay from First Valid RD Pair Edge(1)

600

Duration RxC is Held Low at Start of Packet

1900

350

t16

RD Pair Bit Ceil Center Jitter in Preamble

±12

t17

RD Pair Bit Cell Center Jitter in Data

.±18

t18

RD Pair Return to Zero from Last Valid Positive Transition

t19

RD Idle Time After Transmission

235

,...s

NOTES:
1. RTS inactive.
2. Characterized, not tested.

i------T1-----+I
3.0 V - - - - - - 2.0 V - - - - - - -

0.0 V

290259-9

Figure 8. Clock Timing Measurement Points

1-277

82521TB

RxC

------------~~----~

290259-10

Figure 9. Receive Timing: Start of Frame

- - 1 - - - - - t 19

CRS

--------------------~

290259-11

Figure 10. Receive Timing: End of Frame

1-278

inter

82521TB

Encoder Timing Characteristics
Symbol

Parameter

Min

Max

Units

99.99

100.Q1

t20

TxC Period

t21

TxC Rise and Fall Time(2)

t22

TxC High Time

t23

TxCLowTime

t24

RTS Assertion to TD Pair Active

40
250

470

t25

Transmitter Steady State Delay

100

270

ns·
ns

TxD Hold Time from TxC Low

5
10

t27
t28

TxD Setup Time from TxC High(1)

t29

TxD Hold Time from TxC High(1)

t30

TxD Rise and Fall Time(2)

t31

RTS Setup Time to TxC Low

t32

RTS Hold Time from TxC Low

t33

RTS Rise and Fall Time(2)

t34

TD Pair Output Jitter

. TxD Setup Time to TxC Low

t26

ns
ns
ns

10
±4

ns
ns

350
250

520

400

ns
ns

RTS Deasserted to CDT Asserted (Heartbeat)

600

4500
1"600

CDT Assertion Pulse Width (Heartbeat)

500

1500

t35

RTS Deasserted to TD Pair Inactive

t36

TD Pair Held at Positive Differential at SOl

t37

TD Pair Return to ± 50 mV after Transmission

t38
t39

NOTES:
1. Manchester Encoder Disabled.
2. Characterized, not tested.

t33J 1~1-------1I--5~------+----t
TxO

---------r--_

TO PAIR
(LAST BIT = 1)

TO PAIR

(LAST BIT = 0)

290259-12

Figure 11. Transmit Timing: Manchester Encoding

1-279

82521TB

TxO
Figure 12. Transmit Timing: Non-Manchester Encoding

COLLISION TIMING CHARACTERISTICS
Symbol

Parameter

Min

Max

Units

COT Assertion from Onset of Collision

900

COT Deassei"tion from End of Collision

900

CRS Deassertion from End of Collision(1)

900

NOTE:
1. Both R'i'S and RD Pair Idle.

MODAL TIMING CHARACTERISTICS
Symbol

Pa...meter

Min

Max

.Units

RESET Pulse Width after Vee Stable

LlD/WDTD, MENC, LPBK2, LPBK1 Setup to RTS Assert

/Ls

LlD/WDTD, MENC, LPBK2, LPBK1 Hold from RTS Deas~rt

/Ls

LlD/WDTD, ~, LPBK2, [PBK1 Setup to RD Active(1)

/Ls

LlD/WDTD, MENC, LPBK2, [PBK1 Hold from Rd Inactive(1)

/Ls

. NOTE:
1. Violation of this specification can result in corrupted data presented to the LAN controller. No other adverse affects will
occur.

. JABBER TIMING CHARACTERISTICS
Symbol

Min

Max

Units

RTS Assert to WDT Assert (TO Disabled)

Parameter

150

t50

Last RTS Deassert to WDT Deassert (TO Enabled)

250

750

1-280

82521TB

RD PAIR - - - - COT

-------i

290259-14

Figure 13. Collision Timing

LlD/WDTO

LPBK2

=:::x

---

r- t46---

r---t45~

I
--t 47 --I

RD PAIR

I- t48.-

-----------------_f----290259-15

Figure 14. Modal Timing

LINK INTEGRITY TIMING CHARACTERISTICS
Symbol

Min

Parameter

Max

Units

tS1

Last TO Edge to Link Test Pulse Transmission

tS2

Link Test Pulse Width

120

tS3

Last RD Edge to Link Fail (U Assert)

150

tS4

Minimum Idle Time between Consecutive Leakbeat Reception

tss

Maximum Idle Time between Consecutive Leakbeat Reception

150

'--_ _ _ _1lJ
__

TO PAIR

~_I~

~1.---t50---+l·1

1---------------:.1---

___

WDT-----------~

290259-16

Figure 15. Jabber Timing

1-281

inter

82521TB

_11_\52
TO PAIR _ _ _ _-"'n,~..,....

11-;----\51------1·1

_______"n......_________'"__

r--- \54---1-1---\55-----j

n......,..__......nL..-__- - In...____

RO PAIR....J1I.I...-------.-1_ _....

t----\53---~....;.~--------__,

LI _ _ _ _ _ _ _...

290259-17

Figure 16.. Link Integrity Timing

1-1·----l.96In.(50mm)

------II

"t~~~~~~~~~:~~~~~~~~~I~
136
.19

·2.36 In.
(60mm)

0.125In.
(3.1i:mm)

· 0.110In.
...11(0.254mm)

0.40 In .

. L _ ( 1 0

-----,i

,-----------.

, - - - - - - . -----I~
m)

~I-

0.100In.
(2.54mm)

. 2.36In,(60mm)

290259-18

Figure 17, 82521TB Form Factor

1·282

82504TA
Transceiver Serial Interface (TSI)

•

Designed for Twisted Pair Ethernet
Applications
- Client Stations
- File Servers
-Bridges
- Twisted Pair Rep,aters

Recovers Data and Clock Signal from
Incoming Manchester Data

End-of-Packet Delimiter (IDL)
• Detects
Informs LAN Controller of Data
• Collisions
and Loss of Signal
10 MHz Transmit Clock
• Generates
Single 5V Supply, and Low-Power
• CMOS Processing

10 Mb/s Operation
• Interfaces
Ethernet LAN
• ControllersIntel
to Twisted Pair Link

•

Segment

Pin Compatible with AT&T T7210

The Intel 82504TA Transceiver Serial Interface component (TSI) is intended for Twisted Pair Ethernet LAN
applications using 10 Mb/ s, Manchester coded data; for example, client stations, file servers, and repeaters.
The 82504TA reduces design time by providing the serial-interface functions required to connect the twisted
pair interface circuitry to any of Intel's Ethernet LAN controllers, including the 82586, 82590, and 82592. It
offers LAN system designers an easy way to upgrade existing. EthernetiCheapernet products to take advantage of low-cost twisted pair wire. The TSI chip performs clock recovery and Manchester decoding of 10 Mb/s
data, and produces NRZ data and clock signals for the LAN controller. The TSI also supports a predistortion
method to prevent line overcharge, improving jitter performance. The 82504TA is pin compatible with the
AT&T T7210. It is fabricated using low-power CMOS processing technology, and is available in 24-lead plastic
DIP and 28-lead SOJ packages.
.

82504TA Block Diagram
DTE

=High

RxD

1+-------1

RxC

1+-------1

82586 CRS
LAN

ClK (20 MHz)

TRxD
Timing
Recovery
and
Manchester
Decoding

TPS
TRMT

Controiler

t----"--'......
TxC I+------!H
RTS t - - - - - t - + l
TxD

TRMT
Transmitter
Control

TPEN
POC

COT

(II

00-

Vee
290212-1

Manufac1ured and 1es1ed fer In1el by AT&T in accordance wi1h AT&T in1ernal s1andards.
@lln1eICorporation. 1989
@lAT&T, 1989

1-283

November 1989
Order Number: 290212-001

inter

82504TA

24-Pin Plastic DIP and 28-Pin'Plastlc SOJ Pin Configurations
VCCA
RSVI
TPS
RESET
TRxO
RSV2
TxO

VCCA
RSVI
TPS
NC
RESET
TRxO
RSV2
TxO

VSSA
NC
MCV
CRS
RxO
RxC'
TPEN
TRMT
TRMT
POC
TxC
VSSA

RTS

RSV3
OTE
ClK
Vcco

RSV3
NC
OTE
ClK

VSSA
NC
MCV
NC
CRS
RxO
RxC
TPEN
TRMT
TRMT
NC
POC
TxC

Vcco

:-'SSA

RTS

290212-2

290212-3

Table 1. Pin Description
Symbol

Pin No.

Type

Name and Function
Analog Vee.

+ 5V power supply.

VeeA

RSV1

TPS

RESET

Reset. Active High. This pin IS asserted to bring the TSI into a
known state. It must be asserted for 1 ms while the clock is
running.

TRxD

Twisted Pair Receive Data. Asynchronous Manchester data from
the twisted pair line receiver.

RSV2

Reserved. This pin is reserved and must be connected to VSSD for
proper operation.

Reserved.This pin is r~served and must be connected to VSSD for
proper operation.
' Twisted Pair Sense. Active high. This pin is asserted when data is
valid on TRxD (Twisted Pair Receive Data).

NOTES:

I = Input
0= Output

1-284

82504TA

Table 1. Pin Description (Continued)
Pin No.

Type

Name and Function

TxD

Transmit Data. Manchester encoded data from the 82586 (or other
Ethernet controller). This pin is directly connected to the TxD
controller output.

RTS

Request to Send. Active low. This signal is synchronous to TxC,
and enables data transmission on the twisted pair link segment.

RSV3

Reserved. This pin is reserved and must be connected to VCCD for
proper operation.

DTE

Data Terminal Equipment. This pin should be connected to VCCD if
the TSI is used in a DTE, or to VSSD if used in a repeater.

ClK

Clock. A 20 MHz ± 0.01 % input clock used for precision timing and
encoded data transmission.

VCCD

Symbol

Digital Vee.

+ 5V Power Supply.

VSSD

TxC

Transmit Clock. A 10 MHz clock output tied directly to the TxC pin
of the Intel Ethernet LAN Controller.

Digital Ground.

PDC

Predistortion Control. This signal is used to reduce jitter in a
twisted pair environment by preventing line overcharge. This pin is
asserted for the first 50 ns of any pulse on the TRMT pair. This
allows the TP line drivers to reduce their output voltage during the
last 50 ns of 100 ns Manchester pulses. PDC will not produce
glitches during consecutive 50 ns pulses.

TRMT
TRMT

16
17

0
0

Twisted Pair Transmit Pair. Serial Manchester encoded data
generated for the twisted pair line drivers.

TPEN

Twisted Pair Enable. Active low. This pin enables the line drivers.

RxC

Receive Clock. A 10 MHz clock connected directly to the RxC
input of the Intel Ethernet LAN Controller. This clock is the
recovered clock from TRxD.

RxD

Receive Data. NRZ data passed to the Intel Ethernet LAN
Controller. This pin is directly connected to the RxD pin on the
controller.

CRS

Carrier Sense. Active low. A signal that alerts the Intel Ethernet
LAN Controller that the twisted pair link is active. This pin is directly
connected to the CRS input of the controller.,

MCV.

Manchester Code Violation. Active low. This signal indicates the
presence of Manchester code violations.

Not Connected.

VSSA

Analog Ground.

1-285

Intel

82504TA

FUNCTIONAL DESCRIPTION

APPLICATION EXAMPLE

The twisted-pair line driver (74ACT244) shown in
Figure 1 is a rail-to-rail CMOS line driver. A resistive,
voltage summing network is used to combine the
individual line driver outputs into a differential signal
having the required degree of predistortion. This signal is then fed through a protection circuit and an
electromagnetic interference (EMI) filter. This reduces interference from the system and the TP wire,
and to reduce crosstalk in bundled cables. Finally,
isolation transformers and a common-mode choke
are included for DC isolation and noise reduction.

DTE MODE
Clock Generator
To clock the 82504TA TSI chip and provide the precision timings required in an IEEE 802.3 environment, a 20 MHz ± 0.01 % clock is required. An internal divide-by-two counter generates the 10 MHz TxC
signal. Several commercially available quartz crystal
based clock oscillators meet these requirements.
The following are two possible vendors.
• Fox Electronics
5842 Corporation Circle
Fort Myers, FL 33905
• M-Tron Industries, Inc.
Yankton, SO 57078

Receive Section
MANCHESTER DECODING AND CLOCK
RECOVERY

The Receive section of the 82504TA is enabled
when incoming data from the .twisted pair asserts
the Twisted Pair Sense (TPS) signal. Manchester
data decoding and clock recovery begin on the serial data from the Twisted Pair Receive Data (TRxO)
input. RxC changes from its free running state to its
locked state during the first two bit-times. CRS goes
active after two bit. times to guarantee reception of
valid data after RxC clock stabilization. The decoded
NRZ data is sent to the LAN controller on the RxO
line along with the recovered clock signal. RxC.

An external TIL-compatible 20 MHz ± 0.01 % clock
with a duty cycle of 40/60 or better can also be
used.

Transmit Section
MANCHESTER RETIMING AND
PREDISTORTION

The transmit section ()f the 82504TA is controlled by
the RTS signal generated by the Ethernet LAN con, troller (Intel's 82586, 82592, etc). When RTS is asserted, the 82504TA begins clocking in Manchester
data from the controller on the TxO input. The TxO
~al is sampled on every transition of the 10 MHz
TxC signaL The serial data is then retimed by the
20 MHz input clock, and sent to the line drivers via
the TRMT and TRMT pins. The enable signal for the
line drivers, TPEN, asserts two bit times after the
assertion of RTS to allow the input Manchester data
to settle. At the end of the packet, TPEN remains
asserted for three bit times to make allowance for
device latency, and to append the end of packet
symbol (IOL) to the data packet.
Another signal, Predistortion Control (POC), is also
generated by the transmit section. Predistortion is a
technique for reducing jitter by preventing line overcharging during "fat" (100 ns) Manchester pulses.
POC is asserted during the first 50 ns of any pulse
on the TRMT outputs; i.e., it is asserted throughout
"thin" (50 ns) pulses and during the first half of "fat"
pulses. This permits the twisted pair line driver to
reduce its output drive during the second half of
"fat" pulses. Internal circuitry prevents glitches on
POCo

The end of packet is detected by the presence of
the IOL symbol or by the deassertion of TPS. After
three bit times CRS will be deasserted synchronously with RxC, then RxC returns to its free running
state.
To interface with a LAN controller that expects CRS
to be asserted in response to its own transmissionIntel controllers are software configurable either
way-the CRS signal from the TSI should be ANO'd
with the RTS signal from the controller (as shown in
Figure 2); this way, CRS to the controller will assert
during both transmission or reception. This is the
normal mode of operation for coaxial Ethernet environments.
APPLICATION EXAMPLE

A typical OTE receiver design is shown in Figure 2.
The incoming signal from the twisted pair wire passes through a common-mode choke and an isolation
transformer for noise, reduction. This signal runs
through another filter. The filter output runs directly
to a line receiver to establish a data channel, and
through a DC offset to another line receiver for a
squelch channel. The squelch channel is used for
noise rejection, and detecting valid incoming

1-286

inter

82504TA

data. The line receivers on both the data channel
and squelch channel convert the differential signal
to TTL-compatible signals.
When the incoming signal level is above the comparator's preset threshold, the comparator output
triggers a Retriggerable Monostable Multivibrator.
The multivibrator then asserts the TPS signal for the
82504TA. The TPS signal remains asserted for two
bit times past the last input transition.
The TPS signal is used to gate the data-channel line
driver from the TRxD signal to ensure proper operation. Further, the VIH level of TRxD should be held
between 1.8V and 2.4V. In the example shown in
Figure 2 this is accomplished by using a 1000. pulldown resistor on the output of the AND gate
(74F08), which is used to gate the data channel with
TPS.

Interface Example
Figure 3 shows a typical DTE implementation circuit.
When designing this type of circuit, considerable attention must be paid to power supply noise reduction, capacitive decoupling, and the layout of the line
driver/receiver to the interface connector (RJ-45).

REPEATER MODE
Operation in Repeater Mode
The 82504TA can be used when the DTE pin is not
asserted. There are two principal differences in this
mode of operation. First, the cleassertion of CRS is
not synchronized to RxC-this, on the average, allows CRS to deassert one bit time earlier. Second,
TPEN assertion occurs two bit times earlier than in
DTE mode.

Collision Detect
Collision detection in the twisted pair environment
occurs from simultaneous transmission and reception on the twisted pair wires. This is indicated by the
assertion of both TPS and RTS. The simple logic
circuit shown in Figure 2 can detect such collisions.

Application Example
A repeater design using the 82505TA Multiport Repeater controller (MPR) requires the services of an
82504 TSI. The TSI provides the Manchester decoder and clock recovery for the MPR. Figure 4 shows
the appropriate interface circuitry.

1-287

82504TA

PREDISTORTION
CONTROL

82504TA

LINE
DRIVER
ANALOG SUBSECTION

TR~T

1-.--4-n

TR~T

1-+-.-4-11

PDC

1-.-+-4-11

RJ45

TPENI-------------------~~~

290212-4

Figure 1. Transmit Section

82504TA

74F08

ANALOG SUBSECTION

RJ-45

TRDn

TCSn 1 - - - - -.....
DC
THRESHOLD
RETRIGGERABLE
ONE SHOT

290212-6

Figure 2. Receive Section

1·288

inter

82504TA

DTE

=High

------4
RxC ....------4

RxD ....

82586 CRS

ClK (20 MHz)

TRxD
Timing
Recovery
and
Manchester
Decoding

LAN

TPS
TRMT

Controller
TxD t-----+l~

TRMT
Transmitter
Control

TPEN
PDC

til
D-

....

Vss
290212-8

Figure 3. DTE Interface Application Diagram

82504TA
TSI
DTE

TPDIO
TPCIO

82505TA
Multiport
Repeater
(MPR)

TRMT
TRMT
TEN
PDC

AUlD

PD3-PDO

AUIC

PDCTl

AUICDT

290212-9

Figure 4. Repeater Interface Application Diagram

1-289

inter

82504TA

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. .

Ambient Operating
Temperature (TA) .... , ........... ODC to + 70DC
Storage Temperature ........... -40DC to +125DC

Power Dissipation ....................... 400 mW
Voltage on any Pin
with Respect to Ground .... - 0.5V to Vee + 0.5':'

CHARACTERISTICS
DC Characteristics
= ODC to +70DC, vee =

Symbol

5V ±10%, vss

Parameter

o.ov

Max

Units

-0.5

Min

0.6

2.0

VDD +0.5

0.5

Test Conditions

VIL

Input Low Voltage

VIH

Input High Voltage . .

VOL

Output Low Voltage

VOH

Output High Voltage

lee

Power Supply Current
(No Load)'

= 25mA
= -25mA
Vee = 5.0V

lee

Power Supply Current
(Load)

Vee

III

Input Leakage Current

/LA

Power Dissipation
(No Load)'

0.20

= 5.5V
Vee = 5.0V

Power Dissipation
(Load)'

0.4

Vee

5
5

ns
ns

CLOAD
CLOAD

2.4

Output Rise and
tr
Fall Time
tf
• Not including excessive output buffer loads.

1-290

IOL

IOH

5.0V

VIH

5.0V

=
=

20 pF
20 pF

82504TA

DECODER TIMING CHARACTERISTICS
(Measurements are from 50% points, unless otherwise noted.)

Symbol

Min

Max

Units

RxC High to CRS Asserted

Parameter

CRS Asserted to RxC Low

OTE: RxC High to CRS Oeasserted

OTE: CRS Oeasserted to RxC Low

OTE: CRS Oeasserted to RxC High

195

345

RxC High Pulse Width as Captured Data Clock

RxC Low Pulse Width as Captured Data Clock

RxC Period as Captured Data Clock

124

RxC High Pulse Width as Free Oscillating Clock

t10

RxC Low Pulse Width as Free Oscillating Clock

172

276

t11

RxC Period as Free Oscillating Clock

215

349

t12

RxO Transition to RxC High

-5

t13

RxC Low to RxO Transition

t14

RxO Transition to RxC Low

t15

TRxO Midbit Transition to RxC Low

130

t16

TPS Asserted to TRxO Sampled

-5

t17

TRxO Preamble Transition to CRS Asserted

t18

OTE: Beginning of IOL to CRS Oeasserted (Last Bit = 0)
OTE: Beginning of IOL to CRS Oeasserted (Last Bit = 1)

230
280

320
390

ns
ns

t19

Repeater: Beginning of IOL to CRS Oeasserted (Last Bit = 0)
Repeater: Beginning of IOL to CRS Oeasserted (Last Bit = 1)

180
170

220
220

ns
ns

t20

Midbit to Midbit Transition on TRxO

120

t21

Boundary to Midbit Transition on TRxO

Negative-Transition CRS Timing Relative to Rxe

I·
RXC

CRS

290212-10

1-291

•

82504TA

DTE Positive-Transition CRS Timing Relative to RxC

r--

~-------t5--------~

290212-11

RxC Timing Measurements (Captured Data Clock) .

t ~ 1,.....---,.·, ___
~t7::1

290212-12

RxC Timing Measurements (Free Oscillating Clock)
t11
-t9-

-J

,,
,

,"
,,,

,,
,

:,
,
,,

,,,

- I.

RXD

---,

290212-13

RxD Timing Relative to RxC
t12

I
I

I
I
I

I
I
I
I
I
I

I
I
I

I
I
I
I
I
I

t14

t13

1-292

I
I
I

290212-14

inter

82504TA

Latency-Definition Timing Measurements

TRXD

RXC

tIS

,
/

RXD

L
290212-15

Start-of-Packet Timing Measurements

TPS

;.- t16

--~~I+----------------------BLIND

TRXD
ELREGARD.

BLIND

ST PREAMBLE

< t16

RXD

I-t17

------------------~I

_________
290212-16

DTE End-of-Normal-Packet Timing Measurements
f - - - - - - t18 - - - - - I
I

TRXD'J

eRS

290212-17

,'---~__')t~--------------

Repeater CRS Timing Relative to IDL
TRXD

~
_____
---

:~~~~~~~~

__t_19____

290212-18

1-293

inter

82504TA

Encoder Timing Characteristics
(Measurements are from 50% points, unless otherwise noted .. The input duty cycle requirement for ClK is
60%/40%.)
Symbol

Parameter

Min

Max

Units

Data Clocked toTxD to Data
at Output TRMT (latency)

100

190

t23

RTS Assertion Clocked to TPEN Assertion'

340

440

t24

TxD Setup Time with Respect
to TxC Transition

t25

RTS Setup Time with Respect
to TxC Transition

t26

TxD Hold Time with Respect
to TxC Transition

t27

RTS Hold Time with Respect
to TxC Transition

t28

RTS Deassertion Clocked
to TPEN Deassertiont

340

440

t29

Data Clocked to TxD to Data
at Output TRMT (latency)

100

210

t30

RTS Assertion Clocked to
TPEN Assertion:j:

140

260

t31

TxD Setup Time with Respect
to ClK High

t32

RTS Setup Time with Respect
to ClK High

ns·

t33

TxD Hold Time with Respect
to ClK High

t34

RTS Hold Time with Respect
to ClK High

t35

RTS Deassertion Clocked to
TPEN Deassertiont

340

DTE TRANSMISSION

t22

REPEATER

460

1.5

OUTPUT CHARACTERISTICS

t36

Maximum Deviation from the Ideal 50 ns
Strobe Point for TPEN, TRMTITRMT, and PDC

t37-t38

TRMTITRMT Worst Case Duty Cycle
Mismatch, 10 pF load

-3

t39

TxC High Time

t40

TxC low Time

NOTES:
• DTE start-aI-packet delay: 2.5 bit times 01 data are masked after RTS is asserted by delaying TEN assertion.
tEnd 01 Packet: 2.5 bit times 01 data are transmitted beyond RTS deassertion by allowing TEN to remain asserted.
:j: Repeater start-aI-packet delay: 0.5 bit times 01 data are masked after RTS is asserted, by delaying TEN assertion.

1-294

inter

[FJ[fJ[gIbOIK-AlOOO~[fJW

82504TA

TXC

RTS

-n

DTE Start-of-Packet
RTS DE-ASSERTION CLOCKED

J '" ,,-"''''''''

IL ,m " "oo'"
1

TXD

t23

TPEN
t22

TRMT

DATA IN

LJ
.
i
·1

DATA OUT

I
I

TRMT

PDC
290212-19

DTE TxD and RTS Setup Time
TXC

TXD

t271'
RTS

~ t26~

=1
'I

j.-

t25

~t24

290212-20

1-295

82504TA

DTE End-of-Packet
RTS DE-ASSERTION CLOCKED

f.....,

RTS

------'

RTS DE-ASSERTED

TXD

II-'- - - TPEN

t28

-----0,1,1

-----------------------j-~---------_

TRt.4T

290212-21

Repeater Start-of-Packet

ClK

rDATA.IN

TXD

: - t30
TRt.4T

-----l

'I
I

I
t29
r

DATA OUT

~---~----P~·---~I---~~---~--

290212-22

1-296

Intel

82504TA

Repeater TxO and RTS Setup Time

CLK

-.JI

I-- t33

·1'

TXD

I-- t34

'1'

RTS

·1

t32

·1

t31

290212-23

Repeater End-of-Packet

CLK

:lL

__________. .________~'I

iII

RTS DE-ASSERTED :

TXD
t35

--------~--------~--------~--------~--------~------~
TRt.lT

j - :I

--------~.:--------------------~--------~!---------------I
I

I
I

--------~::====:====:.:===~:=======
I

290212-24

1-297

82504TA

111ae-

Maximum Deviation ~rom Ideal. 50 ns Strobe Point

...;..;"-

)

TRMT

I-

'f---o I-

)
t36 -

)

so ns

STROBE POINT

t36

K':: K:: k:'
I--

K) K) K
290212-25

.Worst-Case Duty Cycle Mismatch

TRMT/fRMT
290212-26

TxC Pulse Width

1 i

t39

t4lAX - - - - - - - . j

I 24

-1

INDEX
>lARK

0.555
(14.10)
>lAX

INDEX
AREA

0.065 (1.65) >lAX

r--+-r-----------..., - - I
0.165 (4.19)
>lAX

SEATING
PLANE

......Li

-.!

tt:
I

0.100 (2.54)

0.032 (0.81) >lAX

REF

i--j
+--l

0.Q10 (0.254)

0.600 (15.24) SSC

0.700 (17.78) MAX

290212-26

28-Pin Plastic SOJ
Dimensions are in inches and (millimeters)
CODE MARK ON TOP SURFACE
CODING IS RIGHT SIDE UP WHEN
LEAD 1 IS IN LOWER LEFT SIDE

0.710 (18.03)

ENLARGED DETAIL

-------1

5° to 7 0 TYP

0.094

~~~~(~;~)O'125

~
,

(3.18)

>lAX

I I
--I I-- 0.50

(1.27)

SEE ENLARGED
DETAIL

290212-29

1-299

,inter

82505TA
MULTIPORT REPEATER CONTROLLER (MPR)

•
•
•
•
•
•
•
•

Complies with IEEE 802.3 CSMAlCD
Standard for Repeaters (Std ANSI/IEEE
802.3c-1988)
10-Mb/s Operation
Allows Up to Eleven Twisted Pair Ports
and One AUI Port

•
•
•
•

Supports Up to Four Cascaded
Repeaters
Automatic Preamble Regeneration
Auto-Partitioning for System Fault
Isolation
Minimum Frame-Length Enforcement
(96 bits)

•
•

Pin-Selectable FIFO Fill Level
Jam Signal Generation
Eight-Bit Blinding Timer at End of
Transmission
LED Output Control of Critical Network
Parameters
- Traffic Status
-Jam Status
- Per-Port Jabber Status
- FIFO Error Status
Single S-V Supply, and Low-Power
CMOS Processing
Pin Compatible with the AT&T T7200

Performs Manchester Encoding of
Transmitted Data

The 82505TA Multiport Repeater controller (MPR) is a VLSI device designed for use in10-Mb/s CSMAlCD
Twisted Pair Ethernet repeaters. The 82505TA combines with a single 82504TA Transceiver Serial Interface
(TSI) chip to handle all necessary multi port repeater functions. The MPR controller provides automatic preamble regeneration to minimize bit loss, Manchester encoding of transmitted data, jam signal generation, and
minimum frame length enforcement (96 bits). The MPR supports fault isolation by providing lockup control and
auto·partitioning jabber timing. The MPR/TSI combination supports up to eleven twisted pair ports for direct
connection to twisted pair client stations, file servers, repeaters, bridges, and gateways. In addition, the set
supports one AUI port for interfacing twisted pair networks to existing Ethernet (IEEE 802.3 TYPE 10BASE5)
or Cheapernet (IEEE 802.3 TYPE 10BASE2) networks. The MPR offers pin selectable FIFO fill levels and LED
output control of traffic status, jam status, per-port jabber status, and FIFO error status for simplified network
management and diagnostics. The 82505TA Multiport Repeater controller is fabricated using low-power
CMOS technology, and is available in a 68-lead plastic leaded chip carrier package (PL(X).

Manufactured and tested for Intel by AT&T in accordance with AT&T internal standards.

® Intel Corporation. 1989
®AT&T.1989

1-300

April 1989
Order Number: 290213-001

82505TA

290213-1

82505TA Multiport Repeater Block Diagram

TR09

FILL

TR010

AUIRxO

AUICOT

TCS0

TCSl

TCS2

TEST00

TCS3

TESTOl

TCS4

Vss

TCSS

P00

TCS6

001

TCS7

P02

TCS8

P03

TCS9

POCTL

TCS10
AUICRS

RESET

Vee

290213-2

S8-Pin PLCC Pin Configuration (Top View)

1-301

infef

82505TA

PIN DESCRIPTIONS
Symbol

Pin No.

Type

FILL

3-7

Not Connected.

TESTOO
TEST01

0
0

Device Test Outputs: These pins are used in conjunction with
TESTO and TEST1 to facilitate device testing. During normal
operation these pins are not connected.

VSS

Ground: O.OV. All ground pins must be connected together.

PDO-PD3

11-14

Port to Disable: Address of port to disable when traffic is received.

PDCTL

Port Disable Control: When low it indicates that the port selected
by PDO-PD3 is to be disabled. When high it indicates that all ports
should be enabled. The Port Disable address is invalid when PDCTL
is high. This pin remains low as long as the Port Disable address
pins are valid.

LED Status Indicator: Part of address bus for LED status
indicators.

Name and Function
Not Connected.
FIFO Fill Level: This pin controls the number of bits loaded into the
internal or external FIFO before the bits are unloaded. When low,
the fill level is seven. When high, the fill level is eight. This pin is
connected to an internal pull-up device.

VCC

5-V Supply: All VCC pins must be connected together.

L1-L3

18-20

LED Status Indicators: Part of Address bus for LED Status
Indicators.

LEDCTL

LED Control: When low it indicates that the LED selected by LO-L3
is turned on. When high it indicates that the LED is turned off.

LEDSTRB

LED Strobe: This pin pulses low when the LED address and control
pins are valid and an LED status is updated.

CLKOUT

20-MHz TTL Clock Output: This pin is a buffered version of CLK.

VSS

Ground: 0.0 V. All ground pins must be connected together.

TPS

Twisted Pair Sense: This pin indicates presence of carrier to the
TSI. It is high while valid Manchester data is being received. If the
repeater is sending jam, or is blinding inputs, this pin is driven low.

TRxD

26'

TSI Received Data: Manchester data from the repeater front-end
to the Manchester decoder.

TRMT

Transmit Output: Retimed Manchester complement to all ports
(including the AUI port).

TRMT

Transmit Output: Retimed Manchester data to all ports (including
the AUI port).

PDC

Predistortion Control: Active low. This signal is used to reduce
jitter in a twisted pair environment by preventing overcharge. This
pin is asserted for the first 50 ns of any pulse on the TRMT pair.
This allows the T-P line drivers to reduce their output voltage during
the last 50 ns of 100-ns Manchester pulses. PDC will not produce
glitches during consecutive 50 ens pulses.

1-302

inter

82505TA

PIN DESCRIPTIONS

(Continued)

Symbol

Pin No.

Type

TPEN

Transmit Port Enable: TPEN is low when TRMT and TRMT
contain valid data, jam, or IOL.

VSS

Ground: 0.0 V. All ground pins must be connected together.

ClK

System Clock: 20-MHz ±0.01 %,50% nominal, 40/60% worstcase duty cycle.

TESTO
TEST1

33
34

I
I

Device Test Control: If either pin is low, internal test circuitry is
enabled to facilitate device testing. If both pins are high the repeater
operates normally. These pins are connected to internal pull-up
devices.

RESET

Device Reset (Schmitt Input): A high on the pin causes the device
to reset. RESET must be low for normal operation.

AUICRS

AUI Carrier Sense (Schmitt input): A high on this pin indicates the
presence of a carrier on the AUI port. AUICRS must be active high
for at least 2.5 ± 0.5 successive 2X clock samples (1 to 1.5 bits) for
the repeater to recognize valid AUI carrier.

TCSO-TCS10

37-47

Twisted Pair Carrier Sense (Schmitt input): A high on any of
these pins indicates the presence of carrier on that port. TCSn must
be active high for at least 2.5 ±0.5 successive 2X clock samples (1
to 1.5 bits) for the repeater to recognize valid T-P carrier.

AUICOT

AUI Collision Detected: A low on this pin indicates the presence of
a collision at the AUI port. AUICOT must be active low for at least
1.5 ± 0.5 successive 2X clock samples (0.5 to 1.0 bits) for the
repeater to recognize valid AUI collision.

AUIRxO

AUI Receive Data: Received Manchester data from the AUIline
receiver.

TR09-: TR01 0

50-51

Twisted Pair Receive Data: Received Manchester data from the
twisted pair line receivers.

VOO

TROO-TR08

53-61

VSS

CRS

Carrier Sense: A low on this pin indicates that the Manchester
decoder (TSI).is receiving a valid packet.

Name and Function

5-V Supply: Pin 17 must be connected to this pin.
Twisted Pair Receive Data: Received Manchester data from the
twisted pair line receivers.
Ground: 0.0 V. All ground pins must be connected together.

RxC

Receive Clock: Recovered clock from the TSI decoder.

RxO

Receive Data: Recovered NRZ data from the TSI.

MCV

Manchester Code Violation: A low on this pin indicates that a
Manchester violation was detected by the TSI. COT must be active
low for at least 1.5 ± 0.5 successive 2X clock samples (0.5 to 1.0
bits) for the repeater to recognize collision. The repeater enters the
transmit collision global state when a violation is detected.

67-68

Not Connected.

1-303

Intel

82505TA

82505 MPR
82504 TSI

AUI INTERFACE

AUIRxD
AUICRS

TRxD

TPS

TRMT

MCV

TRMT

CRS

TPEN

RxC

RxD

AUI

AUICDT

3
PDC
TROll
TCSII

LII-L2
LEDCTL
L3
LEDSTRB

fQ7~:rt~----l LII-L2
1+----4

PDCI----+--~

LEDCTL

TRDI II 1+---1---1

TCS1111+---I-.,.--I

LEDSTRB

,.::r,! "A~,~B,~C~,~D"'G~I---"
74L154 4-TO-16 DECODER

290213-3

Typical System Configuration

82504TA

PREDISTORTION
CONTROL

LINE
DRIVER
ANALOG SUBSECTION

TRMT I-_-~-l'

RJ45

1
2

TRMT

1-+-_4.:..11

TPEN~----------~-~

290213-4

Transmit Section

1-304

82505TA

825D4TA

74F08

ANALOG SUBSECTION

RJ-45

TRDn

TCSn

t-------.
DC
THRESHOLD
RETRIGGERABLE
ONE SHOT

290213-6

Receive Section: Port n
Timer Tw1_ Tw1 is the wait timer for the end-oftransmit recovery time (blinding timer), its duration is
eight bit times. When the repeater finishes transmitting a packet, Tw1 prevents the repeater from receiving that transmission as a new activity.

FUNCTIONAL DESCRIPTION
The Use of State Diagrams
State diagrams are used throughout the Functional
Description section of this data sheet to facilitate
concise descriptions. The state diagrams are modelled after-and use the same terminology-those
used in the CSMAlCD repeater standard (ANSI/
IEEE Std 802.3c-1988). Each state diagram is assumed to represent an independent process; each
process communicates by using interprocess flags.
Furthermore, the state diagrams are intended to
convey the external operation of the MPR, they do
not necessarily describe the internal circuitry. For
example, the state diagrams imply independent
Transmit timers for each port, while in fact, only one
timer is used.
The 82505TA state diagrams adhere to the IEEE
standard as closely as possible; however, several
departures from the standard have been made to
account for the inclusion of some of the Twisted Pair
MAU's internal functions. Should the state diagrams
conflict with the text in this section, the state diagrams should be given preference.
TIMERS
Several timers and counters are implemented in the
82505TA MPR, they are described in the following
two sections.

Timer Tw2_ Tw2 is the wait timer for the end-of-carrier recovery time, its duration is three bit times.
When AUICDT is detected making a positive transition, Tw2 prevents the repeater from prematurely
detecting the real end-of-collision signal.
Timer Tw3_ Tw3 is the wait timer for length of continuous output, its duration is 65,536 bit times. It is
started when transmission of a packet begins. If Tw3
expires before transmission of the packet is completed the repeater enters the MAU jabber lockupprotection condition, and interrupts the transmission
for a period equal to Tw4.
Timer Tw4. Tw4 is the wait timer for time to disable
output for jabber lockup protection, its duration is 96
bit times. When Tw4 is active, transmission to all
ports is suspended until the timer expires. The MAU
lockup LED is turned on at the next LED counter
interval, this indicates that transmission is suspended.
Timer TwS. Tw5 is the wait timer for length of packet without collision, its duration is 512 bit times. It is·
started when a port becomes active. If a collision is
detected before Tw5 expires, the collision count for
that port is augmented, and the.port Tw6 is begun. A
separate Tw5 is implemented for each port, including the AUI port.

1-305

82505TA

Timer Tw6. Tw6 is the wait timer for excessive
length of collision, its duration is 1024 bit times. It is
begun if a collision is detected before Tw5 expires. If
the collision condition still exists when Tw6 expires,
the port on which the violation occurred is parti. tioned (the receiver is disabled). A separate Tw6 is
implemented for each port, including the AUI port.

lamp test by cycling through each lED address with
lEOCTl low. All LEOs will remain on (lamp test
state) for as long as RESET is held high. Minimum
RESET high is 2 fJ-s (40 ClK cycles), to ensure a
device reset. The 2 fJ-s also allow the repeater unit to
cycle through each lED address at least once.
. At the end of a reset (RESET goes low), all jabber,
collision, and FIFO error indicators are turned off,
but the traffic status indicator is left on (it blinks
when packets arrive).

COUNTERS
Counter CC. CC, the collision counter,maintains a
record of the number of consecutive collisions for a
particular port. If the collision limit is reached on a
port, that port is partitioned (the receiver is disabled).
A separate CC, with a limit of 31, is implemented on
each port, including the AUI port.

The repeater unit is fully operational when it exits
reset.

Automatic Preamble Generation

Counter TT. TT, the transmit timer counter, maintains a record of the number of bits transmitted to
any given port; its duration is 96 bit times. If the total
number of bits transmitted to a port is less than 96
(due to the reception of a fragmented packet). the
repeater will enter the receive collision global state
and will transmit jam until TT expires, thus extending
the frame to 2 96 bits.

Automatic Preamble Generation (APG) prevents the
preamble from shrinking as a frame is passed from
repeater to repeater. This shrinking. or loss of bits, is
due to the bit cost of determining the presence of a
carrier and synchronizing the Manchester data for
NRZ data and clock recovery.
The APG circuit compensates for the bit loss by beginning transmission of new preamble bits before
the FIFO limit is reached. When bits from the incoming frame reach the FIFO limit they are synchronously switched into the awaiting pretransmitted preamble. If the logic polarity of the first bit out of the FIFO
is not the value expected, an extra preamble bit is
transmitted. This prevents corruption of the preamble pattern when the· transmitted bit stream is
switched from the APG generator to the FIFO data.

The TT counter is cleared when the repeater enters
the transmit collision global state. This ensures that
at least 96 bits of jam are transmitted to all ports
before the repeater enters the one remaining port,or
blind states from the transmit collision state.

Global State Machine
A single global state machine is implemented for the
MPR. The state diagram assumes multiple twisted
pair ports and one AUI port.

The delay between carrier detection and start of
APG depends on the FIFO fill level selected, and the
type of active port.

Auto-Partition and Reconnection
T!1e optional auto-partition and reconnection algorithm described in SC. 9.6.6.2 of the ANSI/IEEE Std
802.3c-1988is implemented in the 82505TA MPR
chip. Each port, including the AUI port, is provided
with an individual partition state machine. The state
machine for the AUI port corresponds to that described in the standard. The machines for the T-P
ports have been modified to reflect the inclusion of
several MAU functions; the operation of the machine
at the MOl interface remains unchanged.

RESET
The repeater unit is reset when RESET (pin 35) is
asserted high. When the 82505TA is reset,· the re- peater unit disconnects all ports and performs a

The delay for a T-P port is such that the number of
preamble bits added by the repeater is equal to the
number of bits (± 1 bit) lost while detecting the
frame. That is, the latency of bits through the repeater equals the delay of preamble start introduced by
the repeater. If the FIFO fill level (Fill) is changed,
the delay for start of APG is automatically changed
to compensate for the new latency of the FIFO.
For the AUI port, the bit loss in detecting the frame
can range from one to eight bits. Therefore, the beginning of APG caused by the AUI port is dependent
only a a carrier detection, and is not delayed. This
allows the repeater unit to recover a maximum of
three bits lost by the attached MAU in frame detection.
The leading edge of the first preamble bit transmitted by the repeater (as seen on the line) indicates
the beginning of a 100-ns positive voltage (TTl
logic 1).

1-306

inter

82505TA

LED STATUS INDICATOR ADDRESSES
L3 L2 L1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Description

Asserted
LED State

TPP 0 Partition Jabber
TPP 1 Partition Jabber
TPP 2 Partition Jabber
TPP 3 Partition Jabber
TPP 4 Partition Jabber
TPP 5 Partition Jabber
TPP 6 Partition Jabber
TPP 7 Partition Jabber
TPP 8 Partition Jabber
TPP 9 Partition Jabber
TPP 10 Partition Jabber
AUI Partition Jabber
FIFO Error
Traffic
Jam'
MAU Lockup Protection

On
On
On
On
On
On
On
On
On
On
On
On
On
Off
On
On

LO Address

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F

• This indicates the transmission of jam for collision, packet fragments, and FIFO errors.

LED Controller

Port Disable Controller

The LED controller contains a 21-bit counter (105
ms at 20 MHz). At each 105-ms interval, the controller loads the status of each event into a shift register
and shifts the status out as LEDCTL. If the port indicates a change in status from the previous interval,
the appropriate LED is toggled. Thus, for each
event, the minimum time an LED is on or off is 105
ms, and the LED will not change state until an additional 105 ms have elapsed.

The Port Disable Controller determines which port is
receiving valid data, and outputs an address associated with that port. External circuitry uses this address to disable outgoing traffic on that port.

The status indicators, with the exception of the jabber indicators (address 0 to 11), have a 50% duty
cycle when they are asserted (105 ms on, 105 ms
off). The jabber indicators will remain on for as long
as the affected ports are partitioned (Receive disabled).
The following table shows the addressing used for
the LED status indicators. An LED is turned on by a
negative pulse on LEDSTRB when LEDCTL is low.
An LED is turned off by a negative pulse on
LEDSTRB when LEDCTL is high.

The controller is designed to be used with a 4-to-16
line decoder, with the address pins connected !.:; the
address inputs, and PDCTL and TPEN connected to
the gating inputs.
If PDCTL is high the address is not valid and all ports
should be enabled. PDCTL goes active low after the
repeater unit outputs a valid port address, and remains low for as long as that port address is valid.
If the repeater is sending jam to all ports but one,
and then must send jam to all the ports, the positivegoing edge of PDCTL will coincide with the beginning of a 100-ns positive voltage (TTL logic 1) at the
TRMT output pin. The following table shows the address associated with each port.

A status LED interface using two 74LS259 addressable latches is shown in the following figure.
The upper LED address bit (L3) is gated with
LEDSTRB to provide the strobe signal to each
74LS259 device. The CLEAR input is tied high since
the repeater will initialize the latches during the LED
lamp test.

1-307

82505TA

PORT DISABLE ADDRESSES
PD3

PD2

PD1

PD~

Address

Description

0
0

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1
2
3
4
5
6

Disable T-P Port 0
Disable T-P Port 1
Disable T-P Port 2
Disable T-P Port 3
Disable T-P Port 4
Disable T-P Port 5
Disable T-P Port 6
Disable T-P Port?
Disable T-P Port 8
Disable T-P Port 9
Disable T-P Port 10
Disable AUI Port
Not Assigned
Not Assigned
Not Assigned
Not Assigned

o.
0
0
0
0
0
1
1
1
1
1
1
1
1

7
8·
9
A

B
C
D

E
F

+5V

+f
~r~~

CLEAR

....

-0

01
02
'LS259 03
04

TPO JAB

-·.
·
· ~~
•

+5V
(

TP7 JAB

+5V

82505TA
MPR

+5V

J~~

CLEAR

LEDSTRB
D

LEDCTL

L[>-----c'

00
01
02
'LS259 03
04

---

TP8 JAB

'-- B

•

+5V

·
··

~,~
t--

MAU LOCK

290213-8

LED Interface Using Two 'LS259 Addressable Latches

1-308

intJ

82505TA

RESET

!~------------~

Idle-O
OUT(ALL)

=Idle

=
=

Dataln(>1 ) Active *
Collin(AUI} SOE

Collin(AUI}

Dataln( ONLYl ) Active *
Collln(AUI} SOE
:IN - Port(Dataln Active»)

=SOE

:IN - Port(AUI})

SEND DATA-l
OUT(ALLXN)

=Data

I
=

TPDataln(ANYXN) Active +
ICollln(AUI} SOE *
Port(AUI) .p N)
TP Manchester Violation +
Delayed AUI Manchester Violation +
FIFO Error

TPDataln(ALL) = Idle *
Dataln(N) Idle *
Collln(AUI} SOE *
TI(ALLXN) ~ 96 *
AIiDataSent

=
=

ICollin(AUI) SOE*
Port(AUI} N) +
IDataln(N) Idle *
Collln(AUI} SOE *
TI(ANYXN) < 96)

TRANSMIT COLLISION - 3
OUT(ALL)

=Jam

OUT(ALLXN)

([TPDataln(ONLY1) Active *
Collln(AUI} SOE) +
ITPDataln(ALL) Idle *
Collln(AUI} SOE)) *

RECEIVE COLLISION - 2

TPDataln(Any) Active +
ICollln(AUI} SOE *
Port(AUI} .p N)

TI(ALL)~96

:IM - porte Collin = SOE ..:
TPDatain( ONLYl Active)})

TPDotoln(ALL) = Idle *
Collln(AUI} SOE *

=Jam
=
=

~ne

TI(ALL)~96*

Tw2Done

ONE PORT LEFT - 4

BLIND - 5

OUT(ALLXM) = Jam

OUT(ALL) = Idle
EnobleTwl

ICollln(AUI} SOE *
{Collin(AUI) .p M) +
.....:...... TPDatain(ANYXM) Active

TPDotolri(ALL) Idle *
Dataln(N) Idle *
Collln(AUI} SOE *
TI(ALLXN) ~ 96 *

TPDataln(ALL) = Idle *, Collln(AUI} = SOE *
Dataln(M) Idle *, Tw2Done

TwlDone

290213-9

Global State Diagram for Multiple TP Ports and One AUI Port

1-309

inter

82505TA

RESET

l
COUNT CLEAR - 0

-----------------CC(AUI) =0
Dotoin(AUI) = DIPresent(AUI)
Collin(AUI) = CIPresent(AUI)

--------------------Dotoin(AUI) = DIPresent(AUI)
Collin(AUI) = CIPresent(AUI)

DIPresent(AUI} = Idle'
CIPresent(AUI) = SOE

DIPresent(AUI) = Idle +
CiPresent(AUI) = SOE

•

COLLISION COUNT IDLE - 1

WATCH FOR COLLISiON - 2
--------------------Dotoln(AUI) = DIPresent(AUI)
Collin(AUI) = CIPresent(AUI)
EnobleTw5

PARTITiON WAIT- 4

---------------Dotoln(AUI) = Idle
Collin(AUi) = SOE

DIPresent(AUI) = Idie'
CIPresent(AUI) = SOE'

DIPresent(AUI) = Idle"
CIPresent(AUI) = SOE

.!
--------------Dotln(AUI) = Idle

CIPresent(AUI)
DIPresent(AUI) = Idle'

PARTITION HOLD - 5

= SQE

CIPresent(AUI) = SOE'
TW5Done

Collin(AUI) = SOE
DIPresent(AUI) = Idle +
CIPresent(AUI) = SQE

COLLISION COUNT INCREMENT- 3

-------------------------CC(AUI) = CC(AUI) + 1
Dotoin(AUI) = DIPresent(AUi)

PARTITION COLLISION WATCH - 6

------~---'--------------Dotoin(AUI) = Idle
Collin(AUI} = SQE

Collin(AUI) = CIPresent(AUI)
EnobleTw6

EnobleTw5
CC(AUI)~31

CIPresent(AUI) = SOE

(CIPresent(AUI) = SQE"
Tw6Done)

DIPresent(AUI) = Idle'
CIPresent(AUI) = SQE

DIPresent(AUI) = Idle 0
CIPresent(AUI) = SQE'
CC(AUI) < 31"
Tw6Done

Tw5Done', DIPresent(AUI) = Idle'
CIPresent(AUI) = SQE
WAIT TO RESTORE PORT - 7

----------------------Dotoln(AUI) = Idle
Collin(AUI) = SQE
CC(AUI) = 0
DIPresent(AUI) = Idle', CIPresent(AUI) = SQE
290213-10

Partitioning State Diagram for AUI Port

1-310

inter

82505TA

RESET

+ 1

COUNT CLEAR - 0

COLLISION COUNT - 1

CC(X) = 0

--------------------

Dotoin(X) = DIPresent(X)

Dotoin(X) = DIPresent(X)
DIPresent(X) = Idle
DIPresent(X) = Idle

....

WATCH FOR COLLISION - 2

---------------------

....

Dotoin(X) = DIPresent(X)

PARTITION WAIT- 4

----------------

EnobleTw5

Dotoin(X) = Idle
DIPresent(X) = Idle
DIPresent(X) = Idle

TPEN(X) = Active •
DlPresent(X) = Idle

Tw5Done

PARTITION HOLD - 5

---------------Dotoln(X) = Idle

COLLISION COUNT INCREMENT - 3

-------------------------CC(X) = CC(X) + 1
Dotoln(X) = DIPresent(X)
EnobleTw6

DIPresent(X) = Idle

PARTITION COLLISION WATCH - 6

------------------------Dotoin(X) = Idle
EnobleTw5

CC(X)~31

Tw6Done
TPEN(X) = Active •
DlPresent(X) = Idle

DlPresent(X) = Idle·
CC(X)<31

DIPresent(X) = Idle

Tw5Done

WAIT TO RESTORE-7

----------------------Dotain(X) = Idle
CC(X) =0
DIPresent(X) = Idle
290213-11

Partitioning State Diagram for T -P Port x

1-311

82505TA

RESET
RESET

IDLE

---------------

IDLE
---------------

D1sobleOut = ON

Tw2S0E=ON

lOUT(ANY) = Idle
Collln(AUI) = SOE

ARIA

TIIAE OUTPUT
----------------

Tw2S0E=ON

D1sobleOut = ON
EnobleTw3

---------------

Collln(AUI) = SOE

OUT(ALL) = Idle

Tw3Done·, OUT(ANY) = Idle

TIIAING

----------------

DISABLE OUTPUT

----------------

Tw2S0E=ON
EnobleTw2

DisobleOut = ON
EnobleTw4

Tw2Done

290213-12

Tw4Done
290213-13

MAU Jabber Lockup Protection State Diagram
Tw2 State Diagram

RESET

TT IDLE

--------------TT(X) = 0

lout(X) = Idle ., Bit Transmitted
COUNTING

--------------TT(X) = TT(X) + 1

!
HOLD

--------------TT(X)

Bit Transmitted

. Out(X) = Idle +

Global State X - Teollsn

Transmit Timer State Diagram

1-312

290213-14

intJ

82505TA

CHARACTERISTICS
DC Characteristics
Symbol

Min

Max

Units

VIL

Input Low Voltage

Parameter

-0.5

0.8

2.0

+ 0.5

VIH

Input High Voltage

VOL

Output Low Voltage

0.5

VOH

Output High Voltage

2.4

Icc

Power Supply Current

III

Input Leakage Current (TTL)

III

Schmitt Inputs

III

Inputs with Pull-Up

Power Dissipation (25°C)

Power Dissipation (O°C)

VDD

ABSOLUTE MAXIMUM RATING*

+ 125°C

Power Dissipation .•.................... 400 mW
Voltage On Any Pin
with Respectto Ground ..... -0.5V, Vee

+ 0.5V

V
V

IOL = 1.6 mA

IOH = -0.4 mA

Vee = 5.5V

/lA

VIH = 5.5V

/lA

VIH = 5.5V

500

/lA

VIH = 5.5V

0.33

Vee = 5.0V

0.4

Vee = 5.0V

NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice.

Ambient Operating Temperature (Ta) ..... O°C, 70°C
Storage Temperature •........... - 40°C,

Test Conditions

CLOCK AND RESET TIMINGS
Symbol

Description

Min

Max

Unit

t1
t2
t3
t4
t5
t6
17

Clock period
Clock high
Clock low
Clock rise time
Clock fall time
CLKOUT propagation delay
RESET pulse width

49.995
20
20

50.005
30
30
10
10
1'6

ns
• ns
ns
ns
ns
ns
CLK

10
40

ClK _ _J

CLKOUT

R~rr ---11-,-----t7-------I)Clock and Reset Timing

1-313

290213-15

Intel

82505TA

TRANSMIT TIMINGS
Symbol

Description

Min

Delay from CRS low to TPEN low.
T-P Port, FILL = 0 (FIFO fill = .7 bits)
T-P Port FILL = 1, (FIFO fill = 8 bits)
AUI Port, FILL = x (FIFO fill = don't care)
AUICDT low to TPEN low
Multiple Carrier' to TPEN low

5
6
4.5
4
5

t9
t10

Max

Unit

bits
bits
bits
bits
bits

5
5
6

* Carrieris any of TCSX or AUICRS

Normal Packet
SINGLE
CARRIER

~~
STATE _ _ _ _ _ @

-=_________~
I..Y;;;..._ __
290213-16

GLOBAL MACHINE STATES:
O. Idle
1. Send Data

Start of Transmission Timing (Normal Packet)
Receive Collision (RC)
AUICDT
19
TPEN

.!@!L_::::::=:L__~®L__

GLOBAL _ _ _ _ _
STATE

290213-17

Transmit Collision (TC)
MULTIPLE
CARRIER _ _ _ _ _"..,
i-----ll0----I
TPEN

GLOBAL _ _ _ _ _J@~_=:::::=z..
STATE

__~'3'~_ _
'B-1

GLOBAL MACHINE STATES:
O.ldle
1. Receive Collision
2. Transmit Collision

Start of Transmission Timing (Collision Conditions)

1-314

290213-18

inter

82505TA

Manchester Encoder Timing
Symbol

Description

Min

Max

Unit

t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22

Clock high to TPEN low
Clock high to TPEN high
Clock high to POC low
Clock high to POC high
Clock high to TRMT high
Clock high to TRMT low
TRMT rise time
TRMT fall time
Clock high to TRMT low
Clock high to TRMT high
TRMT fall time
TRMT rise time

4
4
4
4
4
4
1
1
4
4
1
1

22
22
22
22
22
22

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

7
7
22
22

7
7

elK

+.JfJ

TRMT _ _ _ _ _ _

290213-19

Manchester Encoder Timing

1-315

82505TA

Manchester Encoder Timing Relationships
Symbol

Description

Min

Max

Unit

t23
t24
t25
t26

TPEN low to TRMT low
TRMT high to TPEN high
TRMT high to TRMT low
TRMT low to TRMT high

1
2.5
0
0

-3.0
5
5

bits
bits
ns
ns

~:~M
~
:f
TRMT

-----'
BIT

,.---

BIT

\....J

I-t25

BIT

-.l~
BIT

J:I--_1_ t24

_---If

\....J'

BIT

BIT,
290213-20

Manchester Encoder Timing Relationship
RECEIVER AND TSI INTERFACE TIMINGS
Carrier and Energy Timings (No Errors)
Symbol

Description

Min

Max

Unit

t27
128
t29
t30
t31
132

Carrier hold time
Carrier setup time
Clock high to TPS high
Clock high to TPS low
Carrier high to TPS high
Carrier low to TPS low

14
10
20
20
4
2

---

ns
ns
ns
ns
ClK
ClK

30
30

5
3

ClK
SINGLE
CARRIER _ _ _ _--'

t31=)=t29
TPS ____________-'

~------~I,r\------------290213-21

Carrier and Energy Timing (No Errors)

1-316

infef

82505TA

Data and TRMT Timings
Symbol

Description

Min

Max

Unit

t33
t34
t35
t36
t37

TPS high to TRXD valid
TPS low to TRXD high
Datat to TRSD delay
TRXD rise time
TRXD fall time

5
5
5
1
1

12
12
35
7
7

ns
ns
ns
ns
ns

tData refers to the data signal (either TRDx or AUIRxD) from the active receiving port.

DATA· ________-"~_____ J ' ' _____~'I~--~
TPS

------'

TRxD
290213-22

'Data refers to the data signal (either TRDx or AUIRXD) from the active port.

Data and MRXD Timing
Decoded NRZ Data Timings
Symbol

Description

Min

Max

Unit

t38
t39
t40
t41
t42
t43
t44
t45

RxC high to CRs low
RxC high to CRS high
Time between CRS low
RxC period
RxClow
RxChigh
RXD setup time
RXD hold time

5
5
16
78
30
36
40
30

19
19

ns
sn
bits
ns
ns
. ns
ns
ns

.~--------------~r---------~~~~I_____ t40~

-"'----'r

RxC _ _- J

RxD

------'

F;.;.....;~.;.;.;..--''--_ _~:Sl-;_ _
290213-23

Decoded NRZ Data Timing

1-317

82505TA

AUI COLLISION INTERFACE
COT and AUICDT Timing Relationship for AUI Port
Symbol

Description

Min

Max

Unit

t46
t47
t48

Delay for MCV low
MCV low to AUICDT low for T"COllSN
MCV low to AUICDT low for R-COllSN

10.5
9.5

bits
bits
bits

INTERNAL
DELAYED
MCV

,~--------~----------t4~
X

r.t47r::.

TRANSMIT COLLISION (TC)

AUICDT

ill '----_
y
fi\
__'
~~--"';;;~'--_

GLOBAL
STATE _ _ _ _ _ _ _I--_ _ _ _....;;I~_

RECEIVE COLLISION (RC)

I--t48~'--_.--------ill

'=--,.--~'2'~---

GLOBAL
STATE _ _ _ _ _ _ _ _ _--.;;;;.-~
_
__J
_ \00._ _....;;\6J~_ _' - -

290213-24

GLOBAL MACHINE STATES:
1. Send Data
2. Receive Collision
. 3. Transmit Collision

MCV, AUICDT Timing Relationship for AUI Port
Port Disable Control Timings
Symbol

Description

Min

Max

Unit

t49
t50
t51
t52
t53
t54
t55
t56

Clock high to port address valid
Clock high to port address invalid
Clock high to PDCTl low
Clock high to PDCTl high
Port address valid to PDCTl low
POCTl high to port address invalid
POCTl low to TPEN low
TPEN high to POCTI high

20
20
20
20
2
1
4
19

30
30
30
30

ns
ns
ns
ns
ClK
ClK
ClK
ClK

CLK

PD3-PDO _ __'I'-~_+~;;;;.;...-'--!r---+_.;.;.;;;;~-_'I'--

290213-25

Port Disable Control Timing

1-318

inter

82505TA

Port Disable Timing (One Port Left)
Symbol

Description

Min

Max

Unit

t57
t58
t59

POCTL high to port address invalid
Port address valid to POCTl low
POCTI high to TRMT low

1
2
1

ClK
ClK
bits

PD3-PDO

-----'
@

290213-26

GLOBAL MACHINE STATES:
O. Idle
1. Send Data
3. Transmit Collision
4. One Port Left
5. Blind

Port Disable Timing (One Port Left)
LED Control Timing
Symbol

Description

Min

Max

Unit

t60
t61
t62
t63
t64
t65
t66
t67

Clock high to address valid
Clock high to address invalid
Clock high to lEOCTl valid
Clock high to lEDCTl invalid
Clock low to lEDSTRB low
Clock low to lEDSTRB high
lEDSTRB low
Time between strobes

20
20
20
20
20
20
1
1

30
30
30
30
30
30

ns
ns
ns
ns
ns
ns
ClK
ClK

ClK
l3-l0
lEDCTl

--------------~~I'~--------~----~'.I~------

--------------~~I'~--------~----~'-I

290213-27

LED Control Timing

1-31-9

82505TA

LED Timing Relationship
Symbol

Description

Min

Max

Unit

t6B
t69

LED update duration
Interoperation time

1.6
105

IL s
ms

---------+-t69-----1-.-

sr,--Z.290213-28

LED Timing Relationship

OUTLINE DIAGRAM
Dimensions are in Inches
' \ 0.003R TYP.
\

PIN1\

2 \1
.,.;;.,
,;.;.,.

17 p.;.,.
16
p.;.,

I'.
18
19

]S8

33
34

O.OOSR

~S7

I
i

i
i

I
I

I
i

O.OSO
MIN. FLAT

0.99 o
TYP
0.953
TYP.

L o.oos ~AX.
0.03SR

P53
PS2

..........
35 3S

.....
50

~L~,~,~,~'alh.~~~,,,.

o·L~
I~

i- o.oso

-WJJ~4

0.013/0.021-11-

0.920 R E F . - - - - - + t
290213-29

1-320

82506TB
TWISTED PAIR MEDIUM ATTACHMENT UNIT (TP MAU)

•
•
•
•

Jabber Function
• Resetable
Selectable Link Integrity (L1) Function
• Selectable Signal Quality Error (SQE)
• Function
Low-Power CMOS Technology
• Single
Supply
• 28-Lead5-VPlastic
DIP and SOJ Packages

Complies with IEEE 802.3 10BASE-T
Draft 11 for Twisted Pair Interface
Conforms to IEEE 802.3 Standard for
Attachment Unit Interface (AU I)
Direct Interface to AUI and Twisted
Pair Isolation Transformers
On-Chip Line Drivers and Receivers

•

LED Drivers for Transmit, Receive,
• COllision,
and Jabber Status
Generates Internal Predistortion Signal
•

(See Packaging Spec Order No. 231369)

The 82506TB Twisted Pair Medium Attachment Unit (TP MAU) is intended for local area network (LAN)
designs that interface the IEEE 802.3-1988 AUI cable to the twisted pair wire (10BASE-T). It offers LAN
designers a cost-effective, integrated solution to the problem of upgrading existing standard Ethernet' networks to twisted pair. The 82506TB complies with IEEE 802.3 AUI specifications and IEEE 802.3 10BASE-T
Draft 11 specifications. The device incorporates the interface circuitry and both the AUI and twisted pair line
drivers and receivers in a low-power CMOS package. The 82506TB TP MAU internally generates predistortion
signals to eliminate line overcharge and improve jitter performance. It provides selectable 10BASE-T features
for simplified network management, including selectable signal quality error (SQE) test,link integrity test, and
jabber protection. In addition, the 82506TB TP MAU supports LED status indicators for transmit, receive,
jabber, and collision. It is fabricated using CMOS-pro'cess technology and is available in 28-lead plastic DIP
and 28-lead SOJ packages.

TRMT
TRMT

RCV

AUI
RECEIVER
AND
SQUELCH

HDAT
HDAT
LDAT

ACTIVITY

LDAT

AUI
DRIVER

RCV

RD
LTTE

CLSN
CLSN

AUI
COLLISION

LID

XTAL

DTE

XLED
CLEO
RLEO
JLED

290260-13

Figure 1_ 8250GTB TP MAU Block Diagram
Manufactured and tested for Intel by AT&T in accordance with AT&T internal standards.
*Ethernet® is a registered trademark of Xerox Corporation.
© INTEL CORPORATION, 1990
© AT&T, 1990

1-321

September 1990
Order Number: 290260-002

inter

82506TB

Vss
TRMT
TRMT
oTE
LID
RCV
RCV

Vee
Ro

RD
TEST
LITE
Vss
HoAT
LoAT
LoAT
HoAT

CLSN
CLSN
Vee

Vee
XL ED
RLEo
CLEO

Vss
JLEO
XTAL
Vss

290260-1

Figure 2. 82506TB Pinout
TABLE 1 82506TB Pinout Description
Symbol
Vss

Pin No.

Type

Name and Function
Analog Ground.

2,3

Transmit Data. A differentially driven input tied to the DO. pair
of the transceiver cable. The transmit pair of the transceiver
cable supplies 1O-Mb/s Manchester encoded data. These
pins must be isolated with a pulse transformer. End of Packet
(EOP) is detected when a positive transition has not occurred
for 200 ns.

DTE

Data Terminal Equipment. A strapping option, which when
tied high (Vecl enables generating a SQE-test signal at the
end of each packet (as required for DTE applications). When
DTE is tied low (Vss) the SQE test is disabled, but the collision
circuit remains enabled for use in repeater applications. When
the DTE is floated, an internal pull-up biases the signal high.

LID

Link Integrity Disable. A strapping option, which when tied
high (Vecl disables the link integrity function of the TPMAU.
When link integrity is enabled, the receive traffic indicator
remains on when the receive twisted pair link is present.

RCV,RCV

6,7

Receive Data Pair. A differential output pair that drives the 01
pair of the AUI cable with 10-Mb/s Manchester encoded data.
These pins must be isolated from the AUI transceiver cable
with a pulse transformer.

CLSN,CLSN

8,9

Collision Presence Pair. A differential output pair that drives
the CI pair of the AUI cable with a 10-MHz (± 15%) signal
when simultaneous activity exists on the TRMT and RD pairs.
These pins must be isolated from the AUI-transceiver cable
with a pulse transformer.

Power. Digital, 5 V.

Jabber Indicator. Indicates that the watchdog timer has
timed out and the twisted pair drivers have been disabled.

TRMT, TRMT

Vss

JLED

Vee

Ground.

1-322

infef

82506TB

TABLE 1. 82506TB Pinout DeEcription (Continued)
Pin No.

Type

Name and Function

XTAL

Symbol

Crystal In. A 20-MHz clock input. This signal can be driven by
a 20-MHz, parallel-resonant crystal or a MOS level clock with
a 60/40 duty cycle.

VSS

Ground. For XTAL (Pin 13) and indicator output drivers.

CLED

Collision Indicator. Indicates that a collision has been
detected by the TP medium attachment unit.

RLED

Receive Indicator. Indicates that a reception from the
network is in progress.

XLED

Transmit Indicator. Indicates that a transmission onto the
network is in progress.

Power. 5 V.

19,22
20,21

TP Transmit Pair Drivers. These four outputs constitute the
twisted-pair drivers, which have predistortion capabilities. The
HDAT IHDAT outputs generate the 1O-Mb/s Manchester
encoded data. The LDAT ILDAT outputs mirror the HDAT1
HDAT outputs except for "fat" bit occurrences. During the
second half of a "fat" bit (either high or low), the LDAT ILDAT
outputs are inverted with respect to HDAT IHDAT outputs.
This signal behavior reduces the amount of jitter by preventing
overcharge on the twisted-pair medium.

LTTE

Lower TP Threshold Enable (Active LOw). For 1OBASE-T
compatible operation this pin must be left open. But, if this pin
is grounded, the TP receiver threshold is lowered by
approximately 4.5 db from the nominal 1OBASE-T required
specification. By using this lower-threshold option and by
selecting different compensation resistor values for waveconstruction circuits, a customized interface is possible for
non-10BASE-T applications. However, once this lower
threshold is invoked, the wiring used must not be a bundled
system (e.g., 25 pair) where other services reside (e.g., voice,
other 10BASE-T users, etc.).

TEST

Test. This pin is used for testing; it should be connected to
VSS during normal operation.

26,27

TP Receive Pair. The differential twisted pair receiver. The
reqeive pair is connected to the twisted pair medium and is
driven with 1O-Mb/s Manchester encoded data.

Vee
HDAT, HDAT
LDAT, LDAT

RD,RD

Vee

Analog Power. 5 V.

1-323

Intel

82506TB

TRMT

HOAT

WAVE
CONSTRUCT
AND
FILTERS

HOAT
LOAT

TRMT

LOAT

VeOM

RCV

AUI

RJ-45

RCV
VeOM
CLSN

CLSN
(PIN 10)
Vee
(PIN 11)

vss

(PIN 28)
Vec
Vss
Vee
(PIN 23)

8
2
5
0
6
T
B

RO
FILTERS

OTE

+5V

LID

+5V

XLEO

"
"
"
"

RLEO

Vss
XTAL

CLEO

10pF
(PIN 14) .

Vss

JLEO

+5V

290260-14

Figure 3. Typical System Configuration

RCV

:::"•. "1]II[ £'"' :
CLSN

IEEE 802.3
COMPATIBLE PULSE
TRANSFORMER·

100pF

290260-17

-Required transformers are the Pulse Engineering Inc. (PE64503), TDK Corp.
(TLA-100-3E), Coilcraft (LAXET304 or L0323-A), or equivalents.

Figure 4. Typical Load Output on the Outputs of ReVIRCV and CLSN/CLSN

1-324

inlef

82506TB

FUNCTIONAL DESCRIPTION
Overview
The 82506T8 provides the transmit, receive, and
collision detection functions specified by the IEEE
802.3 committee for the 108ASE-T Draft 11
(P802.31/D11) specification for a 10-Mb/s, CSMAI
CD, twisted-pair Ethernet. The 82506T8 is used as
the interface between the attachment unit interface
(AUI) signals and the twisted pair. Two strapping options are available.
• Link Integrity Disable (LID). When the LID
strapping option is enabled (driven high), the link
integrity function is disabled. When driven low
link pulses are transmitted on the twisted pair me~
dium in the absence of data transmissions. In addition, the receiver expects to see link pulses in
the absence of receive data. If no receive data or
link pulses are received within 100 ms ± 50 ms
the 82506T8 will enter a link fail state. When LID
is floated an internal pull-up biases the signal
high.
• Data Terminal Equipment (DTE). When the
DTE strapping option is enabled (driven high) the
SQE test sequence is.transmitted to the DTE after every successful transmission on the twisted
pair network.
The 82506T8 simplifies network management and
troubleshooting by providing four status indicator
LED drivers that monitor traffic on a node and report
transmit, receive, collision, and jabber conditions.
Figure 3 is an example of a typical system configuration.

TransmitPath (AUI to TP)
The transmit portion of this component transfers
data from the AUI to the twisted-pair analog filters. It
also loops back the data to the RCV pair.
• AUI Receiver. The TP MAU receives transmit
data from the data terminal equipment on the
transmit pins(TRMT ITRMT) of the AUI-DO circuit
(as defined by the IEEE802.3-1988 specification).
The 82506T8 then transmits the data onto the
twisted-pair cable via the twisted-pair drivers. The
AUI transmit inputs must be transformer coupled
to the TRMT ITRMT pins. For best operation, the
AUI signal should be dc biased to a common
mode voltage of Vee/2.
The squelch circuit rejects (filters) all signals with
an amplitude less than 160 mV or a pulse width
less than 20 ns. A signal with an amplitude greater than 300 mV and a pulse width greater than 75
ns is accepted and turns off the squelch filter.

The squelch filter remains off until an IDL pulse is
detected or until the input does not exceed the detection threshold for 500 ± 100 ns.
• AUI Receive Signal Levels. The receiver
(TRMT ITRMT) is able to recognize differential
signals as small as 300-mV peak. Internal circuitry samples the common mode voltage to provide
full differential signal detection.
• TP Driver Characteristics. The drivers (HDAT I
HDAT and LDAT/LDAT) output CMOS logic levels with a source resistance less than 10 0 and
maximum current rating of 25 mA dc. All TP output driver pins are driven low as a result of any of
the following.
• Reception of an IDL signal.
• A jabber condition is detected.
• Activation of a link failure.
• TRMT pair input fails to cross the detection
threshold for 500 ± 100 ns.
When the driver detects the end of an IDL pulse on
the TRMT pair, a timer of not more than 5 bit times
(8T) is started. Activity on the TRMT pair is ignored
until this timer expires.

Receive Path (TP to AUI)
When aRD signal is present, the receive circuit of
the 82506T8 transfers data from the RD pair input to
the RCV pair output.
• AUI Driver Characteristics. This driver differentially drives a current onto the load connected between the RCV and RCV pins. The current
through the load results in an output voltage between ± 0.6 V and ± 1.2 V measured differentially between the two ·pins. An external resistor
(780) and capacitor (100 pF) must be connected
for proper termination, as shown in Figure 4. This
output is in accordance with the IEEE Spec 802.3
Sec.7.4.1 for MAUs. When the driver detects that
it has finished sending an IDL pulse to the AUI it
starts a timer of not more than 5 8T. Activity on
the RD pair is ignored when this timer is functioning.
• TP Receiver Threshold. The TP receiver is connected to the output of a band limiting filter. The
filter's input is transformer coupled to the twisted
pair. The receiver is able to recognize differential
signals as small as 350 mV peak. An external
biasing circuit must provide a common mode voltage of Veel 2. The differential input impedance of
the RD pair is 20 kO ± 20%. Internal circuitry
generates a dual-level bias voltage to determine
proper signal level thresholds and prevent reception of spurious signals from the network (this is
similar to a squelch function).

1-325

inter

82506TB

When the signal level at the RD input falls below
-500 mV, with respect to the common mode
voltage ± 10%, the data path is activated and
the received signal is passed to the AUI cable.
At the beginning of a reception the bias level at
the RD input is reduced to -350 mV with respect to the common mode voltage ± 10%

saE Test (Heartbeat)
The SQE test begins within 11 ± 5 bit times after
the TRMT pair detects the IDL signal. The SQE test
duration is 10 ± 5 bit times. When the AUI-DO circuit has gone idle after a successful transmission
(without a collision), and the DTE input is high, the
82506TB activates the CLSN pair to simulate a collision.

Collision
The collision detection portion of the 82506TB senses the simultaneous presence of data on the TRMT
and RD pins. It reacts by transmitting a 10-MHz
square wave on the CLSN pair of the AUI cable. This
signal is a periodic waveform of 10 MHz ± 15%,
with a duty cycle no worse than 40/60 or 60/40. It is
transmitted within 9 bit times after the component
detects a collision (as specified by 10BASE-T Draft
11, Sec.14.2.1.3). If the receive pair becomes active
while the transmit pair is active, the loopback data
on the RCV pair switches from transmit data to receive data within 13 ± 3 BT from the assertion of
the CLSN pair. If the RD pair goes active while the
TRMT pair is active a collision condition will be detected and the SQE will continue for 7 ± 2 BT. If a
collision condition exists where the TRMT pair has
gone idle while the RD pair is still active, SQE can
continue for up to 9 BT.

Link Integrity
The link integrity function determines if the receive
twisted-pair link is faulty. Enabling the function (LID
tied to Vss) causes the RLED receive traffic indicator to display the status of the receive twisted-pair
link. The link integrity function permits the active disabling of the transmit and loopback paths within the
TP MAU component in response to a link integrity
fault. The link integrity function monitors the RD pair
for either data or link test pulses by providing a 100
ms ± 50 ms window during which data Or a link test
pulse is expected. If this timer expires and the LID is
off, the RLED indicator is turned off and the component's transmit and loopback capabilities are disabled. The 82506TB remains in a link fail state until
after a data packet is received, or until after a sequence of consecutive link test pulses are received.
The sequence length is between two and ten pulses.
If a pulse or receive traffic is detected within this
window, the timer is reset and the RLED indicator
remains on.

The collision AUI driver differentially drives a signal
onto the load connected between the CLSN pair.
This driver differentially drives a current onto the
load connected between the CLSN and CLSN· pins.
The current through the load results in an output
voltage between ± 0.6 V and ± 1.2 V measured differentially between the two pins. An external resistor
(78 .0) and capacitor (100 pF) must be connected
for proper termination, as shown in Figure 4. The
output is in accordancewith IEEE 802.3-1988 Sec.
7.4.1 for the AUI.

The TP MAU also transmits link test pulses onto the
transmit twisted pair link when link integrity is enabled: In the absence of transmit traffic, a link test
pulse is transmitted at a nominal rate of one pulse
each 16 ms ± 8 ms. If the link integrity is disabled,
the RLED indicator remains on in the absence of
receive traffic, (data and link pulses). Received link
test pulses are also ignored at the RD pair input.

Jabber (Watchdog Timer)
The 82506TB supports a self-interrupt function that
protects the network from a jabbering node (Le.,
continuous transmission). The component provides
a nominal window of 50 ms during the time a normal
data link frame can be transmitted. If the frame
length exceeds this duration, the component immediately inhibits all further transmission of that frame
and activates the CLSN pair (as specified by IEEE
802.3-1988 Sec. 8.2.1.5). When activity on the
TRMT pair has ceased, the component continues to
present the CSO signal to the CLSN pair for 0.5 s ±
50%. The component then resets. itself and returns
to the idle state (as specified by the 10BASE-T Draft
11 14.2.1.5). The transmission of link integrity pulses
from the TP drivers is not inhibited when the TP
MAU jabber is activated and link integrity is enabled.

LED Status
Four light-emitting diodes (LEOs) give the user a visual .indication of the MAU's status. The 82506TB
provides the logic signals needed to drive the LEOs.
• XLED. The following LED values (on or off) are
used to indicate transmission (AUI) status.
• The LED is normally on, which indicates no
transmission is in progress.
• The LED is off when a valid packet is transmitted. The duration of the off period is 100 ms ±
10 ms. The minimum duration of the on period is
4 ms while waiting for next valid packet transmission.
.

1-326

inter

82506TB

• RLEO-With LID Disabled. The following LED
values (on or off) are used to indicate reception
(TP) status.
• The LED is normally on, which indicates there is
no receive traffic.
• The LED is off when a valid packet is received.
The duration of the off period is 100 ms ± 10
ms. The minimum duration of the on period is 4
ms while waiting for next valid packet receive.
• RLEO-With LID Enabled. The following LED values (on or off) are used to indicate reception (TP)
status.

The LED driver pulls the pin low to turn the LED on.
Each LED driver can sink up to 15 mA of current,
with an output impedance of less than 50 !l.

Clock Generation
A 20-MHz, parallel-resonant crystal is used to control the clock generation oscillator of the TP MAU.
We recommend that the crystal meet the following
specifications.
• Quartz crystal
• 20 MHz ± 0.01%
• Parallel resonant with a 20-pF load fundamental
mode with a maximum series resistance of 25 !l.

• The LED is normally on, which indicates no receive traffic and successful reception of the link
test pulse.
• The LED turns off if no receive traffic or link integrity signals have been received for more than
0.5 s. This visually indicates a failure of a link
segment. The LED remains off until a link test
pulse, or receive traffic, is successfully detected,
after which the LED is turned on with a minimum
on time of 0.5 s.
• If the link is working, the LED will be turned off
when a valid data packet is received from the
twisted pair. When a packet is received, the LED
is turned off for a duration of 100 ms ± 10 ms,
then the LED is turned back on.
• The LED remains on for a minimum of 4 ms; it is
turned off when the next packet is received.

• CLEO. The following LED values indicate collision status.
• The LED is normally off, which indicates no collision.
• The LED is turned on when a collision is detected. It remains on for a nominal time of 15 ms ±
5 ms, after which it is turned off.
• The LED may be turned back on immediately
upon detection of another collision. There is no
minimum off time.
• If a collision occurs while the LED is on, the LED
remains on for the nominal time following the
last detected collision.

• JLED. The following LED values indicate the jab-

The crystal shunt and external capacitance should
be less than 10 pF. The crystal should be connected
adjacent to the 82506T8 to the XTAL and Vss pins.
The crystal shunt capacitance (CO) should not exceed 5 pF.
An external MaS-level clock can be applied to the
crystal oscillator input. A resistor should be added in
series with the clock source to limit the amplitude of
the voltage swing seen by the pin. A 500-!l resistor
works well in most cases. If users are concerned
about the duty-cycle variation caused by driving the
TPMAU with a clock source, the following test can
be done on the bench to empirically determine the
best resistor value for the user's application.
co Place the part in dc test mode, as described in
the Test Mode section of this document.
.. Attach an oscilloscope to the JLED pin. This pin
outputs the internal clock source.
.. Alter the resistor value to obtain an optimal dutycycle ratio. Experiments have shown that a
500-!l resistor works well for LS TTL logic levels;
CMOS logic levels need a 1-k!l resistor.
Under no circumstances should the clock be driven
straight into the TPMAU. Also, under no circumstances should the clock stop, not even briefly, once
power is applied to the TPMAU. If the clock to the
TPMAU is stopped, power to the TPMAU must be
removed to ensure proper behavior of the TPMAU.

ber status.
• The LED is normally off, which indicates a no
jabber condition.

Strapping Options

• The LED is turned on when the watchdog timer
times out, and the TP drivers are disabled. It remains on until the jabber condition is corrected.

All strapping options are connected to internal pullup resistors, (nominally 100 k!l). A resistor tying a
strapping option low must be able to sink 70 pA

• The LED is turned off after the watchdog timer
counts out the 0.5 s ± 0.25 s reset time.

Test Mode

LED Drivers
The typical LED circuit consists of an external resistor in series with the LED and connected the Vee.

The 82506T8 enters the ac or dc test mode when
the test pin (TEST) is held high. The ac test mode is
activated by also holding the DTE pin high; the internal clock speeds are increased by three to reduce

1-327

inter

82506TB

the ac test time. The dc test is activated by holding
the DTE pin low while TEST is held high. During the
dc test the oscillator frequency and duty cycle can
be tested on the JLED pin and the three internal
clocks (ACK, BCK, and CCK) can be tested on the
XLED, RLED,and CLED pins respectively. The AUI
driver current can be measured with a 39-n resistor
between the receive pair pins.

ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Ambient Operating Temperature (TA)
Storage Temperature

Power Considerations
There are seven power connections to the TP
MAU-three pairs of Vee and Vss connections and
a fourth VSS pin for the XTAL oscillator. Table 2 describes which internal circuits are powered by each
VeelVss pair.
Table 2. INTERNAL CIRCUIT
Pin No.

Analog Supplies. Analog signal
receivers, energy detection circuits, delay
lock loop, and band gap reference.

10,11

AUI Output Drivers. Digital polycells,
XTAL oscillator (Vee only), and LED
drivers (Vee only).

GND only for XTAL oscillator and pins 15,
16, and 17.

18,23

TP CMOS output drivers only.

DC Characteristics TA =
Symbol

0 to 70°C, Vee

All Output and Supply
Voltages

-0.5 V to Vee + 0.5V

All Input Voltages

-0.5 V to Vee +0.5V

NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
.

Internal Circuits

1,28

0 to + 70°C

- 40 to· + 125°C

5 V -+ 5%

Parameter

Min

Max

Units

VAID

Input Differential Voltage (AUI)

VTID

Input Differential Voltage (TP)

0.300

1.3

0.350

2.0

VXTL

XTAL Input Low Voltage

VxeH

XTAL Input High Voltage

VIL

Input Low Voltage

3.9

Test Conditions

V
0.2

1.2

0.1

Vee = 5.0 V, RL = 500 n

Vee = 5.0 V, RL = .2000 n

Vee = 5.0 V, RL = 2000 n

VIH

Input High Voltage

VAOD

Output Differential Voltae (AUI)

4.0

VTOL

Output Voltage Low (TP)

VTOH

Output Voltage High (TP)

VOL

Output Voltage Low

VOH

Output Voltage High

TP Driver Series Impedance

ICC

Power Supply Current
with a Traffic Load

145

Vee = 5.00 V

Power Dissipation
with a Traffic Load

0.6

Vee = 5.0V

0.600

4.9
0.13
4.87

1-328

Vee = 4.5 V, I = 25 mA (max)

infef

82506TB

AC Timing Conditions
1.TA = Ot070·C, vee = 5V ±

5%.

2. Timing measurement points are 50% points unless otherwise noted.

Clock Timing
Symbol

Parameter

XTAL (or Oscillator) Frequency

XTAL High and Low Times

Max

Units

MHz

22.5

27.5

Min

Clock Timing

XTAL
290260-2

Transmit Timing
Symbol

Parameter

Min

Max

Units

DTE Setup and Hold Time to TRMT Pair Active

ILs

Transmit Start-up Delay

bits

Transmit Steady State Delay

bits

Transmit Start-up Delay Variability

bits

Loopback Start-up Delay

bits

Loopback Steady State Delay

bits

250

350

3.5

TO' Held High at End of Packet

t10

Incremental Transmit Jitter

t11

TRMT Pair Return to Idle to SQE Test

600

1600

t12

SQE Test Duration

500

1500

'TO represents the differential voltage between the signals HOAT and HOAT

1-329

intJ

82506TB

Transmit Timing: Start of Packet

---+---_4

RCV - - - - -.....

. 290260-3

Transmit Timing: End of Packet
OTE
1 + - - - - - - t3

TRMT
t 10

RCV

L
-----·1

r r- -1
tg

~-----il-------_
1. . .-

t11

CLSN - - - - - - - - - - - ,
290260-4

1-330

inter

82506TB

Receive Timing
Symbol

Parameter

Min

Max

Units

t13

Receive Start-up Delay

bits

t14

Receive Steady State Delay

bits

t15

Receive Start-up Delay Variability

bits

t16

Incremental Receive Jitter

1.5

t17

RD Pair Held High at End of Packet

300

Receive Timing: Start of Packet
RD

RCV

-------+
290260-5

Receive Timing: End of Packet

RCV
290260-6

Collision Timing
Symbol

Min

Max

Units

t18

Onset of Collision to CLSN Pair Assertion

Parameter

900

t19

RCV Pair Source to RD after CLSN Assert

900

t20

End of Collision to CLSN Pair Return to Idle

900

t21

CLSN Pair High/Low Time

t22

CLSN Pair Frequency

8.5

11.5

MHz

1-331

intef

82506TB

Collision Timing

(XXXXXXXXXXXXXXXX)
I
(XXXXXXXXXXXXXXX)

TRMT

-1 t

(o;;p I

SSAP

DATA

TAIL
< .......

I CONTROL I ~~:rl
231421-14

Figure 16. IEEE 802.2 Class 1 Frame Format

From Figure 15 it can be seen that there are no LLC
class 1 VI responses because information frames are not
acknowledged at the data link level. The only command frames that may require responses are XID and
TEST. If a command frame is addressed to the Station
Component, it checks the control field to see what type
offrame it is. If it's an XID frame, the Station Component responds with a class 1 XID response frame. If it's
a TEST frame, the Station Component responds with a
TEST frame, echoing back the data it received. In both
cases, the resporise frame is addressed to the source of
the command frame.
'

Any frames addressed to active SAPs are passed directly to, them. The Station Component will not respond to
SAP addressed frames. Therefore it is the responsibility
of the SAPs to recognize and respond to frames addressed to them. When a SAP transmits a frame, it
builds the IEEE 802.2 frame itself and calls the Handler's Send_Frame() function directly. The LLC
module is not used for SAP frame transmission. The
only functions which the LLC module implement are
the dynamic addition and deletion of DSAPs, multiplexing the frames to user SAPs, and the Station Component command recognition and responses. This is
one implementation of the IEEE 802.2 standard. Other
implementations may have the LLC module do more
functions, such as SAP command recognitions and responses. A list of the functions included in the LLC
module is as follows:
LLC Functions
IniLLlc()

Description

Initializes the DSAP
address table and calls
IniL586()
Add_Dsap_
Add a DSAP address to
Address (dsap, pfunc) the active list
dsap - DSAP address
pfunc - pointer to the
SAP function
Delete-DsapDelete a DSAP address
Address (dsap)
dsap - DSAP address
Receives a frame from
Recv-Frame (pfd)
the 82586 Handler
pfd - Frame Descriptor
Pointer
Station-Component- Generates a response to
Response (pfd)
a frame addressed to the
Station Component
pfd - Frame Descriptor
Pointer

AP-235

4.1 Adding and Deleting LSAPs

Terminal Mode - implements a virtual terminal with
datagram capability (connectionless "class 1" service).
This mode can also be thought of as an async to IEEE
802.2/802.3 protocol converter.

When a user process wants to add a LSAP to the active
list, the process calls Add-Dsap-Address(dsap,
pfunc). The dsap parameter is the actual DSAP address, and the pfunc parameter is the address of the
function to be called when a frame with the associated
DSAP address is received ..
The LLC ~odule maintains a table of active dsaps
which consists of an array of structures. Each structure
contains two members: stat - indicates whether the address is free or inuse, and (·p~pJunc)() contains
the address of the function to call. The index into the
array of structures is the DSAP address. This speeds up
processing by eliminating a linear search. Delete_
Dsap-Address (dsap) simply uses the DSAP index to
mark the stat field FREE.

5.0 APPLICATION LAYER
For most networks the application layer resides on top
of several other layers referred to here as ULCS. These
other layers in the OSI model run from the network
layer through the presentation layer. The implementation of the ULCS layers is beyond the scope of this
application note, however Intel provides these layers as
well as the data link layer with the OpenNET product
line. For the purpose of this application note the application layer resides on top of the data link layer and its
use is to demonstrate, exercise and test the data link
layer design example.
There can be several processes sitting on top of the data
link layer. Each process appears as a SAP to the data
link. The UAP module, which implements the application layer, is the only SAP residing on top of the data
link layer in this application example. Other SAPs
could certainly be added such as additional "connectionless" terminals, a networking gateway, or a transport layer, however in the interest of time this was not
done.

Monitor Mode - allows the station to repeatedly transmit any size frame to the cable. While in .the Monitor
Mode, the terminal provides a dynamic update of 6
station related parameters.
High Speed Transmit Mode - sends frames to the cable
as fast as the software possibly can. 'This mode demonstrates the throughput performance of the Data Link
Driver.
Change Transmit Statistics - When Transmit Statistics
is on several transmit statistics are $athered during
transmission .. If TranSmit Statistics is off, statistics are
not gathered and the program jumps over the section of
code in the interrupt routine which gathers these statistics. The transmission rate is slightly increase when
Transmit Statistics is off.
Print All Counters - Provides current information on
the following counters.
Good frames transmitted:
Good frames received:
CRC errors received:
Alignment errors received:
Out of Resource frames:
Receiver overrun frames:

Each time a frame has been successfully transmitted the
Good frames transmitted count is incremented. The
same holds true for reception.CRC, Alignment, Out of
Resources, and Overrun Errors are all obtained from
the SCB. Underrun, lost CRS, SQE error, Max retry,
and Frames that deferred are all transmit statistics that
are obtained from the Transmit cOmmand status word.
82586 Reset is a count which is incremented each time
the 82586 locks up. This count has never normally been
incremented.
.

5.1 Application Layer Human Interface
The UAP provides a menu driven human interface via
an async terminal connected to port. B .on the iSBC
186/51 board. The menu of the commands is listed in
Figure 17 along with a description that follows:

T - Terminal Mode
X - High Speed Transmit Mode
P - Print All Counters
A - Add a Multicast Address
S - Change the SSAP Address
N - Change Destination Node Address
R - Re-Initialize the Data Link

M - Monitor Mode'
V - Change Transmit Statistics
C - Clear All Counters
Z - Delete a Multicast Address
D - Change the DSAP Address
L - Print All Addresses
B - Change the Number Base

FlgU\"8 17. Menu of Data Link Driver Commands
1-352

inter

AP-235

Clear All Counters - Resets all of the counters.
AddlDelete Multicast Address - Adds and Deletes
Multicast Addresses.

reinitialized, and the selftest diagnostic and loopback
tests are executed. The results of the diagnostics are
printed on the terminal. The possible output messages
from the 82586 selftest diagnostics are:

Change SSAP Address - Deletes the previous SSAP
and adds a new one to the active list. The SSAP in this
case is this stations LSAP. When a frame is received,
the DSAP address in the frame received is compared
with any active LSAPs on the list. The SSAP is also
used in the SSAP field of all transmitted frames.

Passed Diagnostic Self Tests
Failed: Self Test Diagnose Command
Failed: Internal Loopback Self Test
Failed: External Loopback Self Test
Failed: External Loopback Through Transceiver Self

Change DSAP Address - Delete the old DSAP and add
a new one. The DSAP is the address of the LSAP
which all transmit frames are sent to.
Change Destination Node Address - Address a new
node.
Print All Addresses - Display on the terminal the station address, destination address, SSAP, DSAP, and all
multicast addresses.
'
Re-initialize Data Link - This causes the Data LiIik to
completely reinitialize itself. The 82586 is reset and

T~t

Change Base - Allows all numbers to be displayed in
Hex or Decimal.

5.2 A Sample Session
The following text was taken directly from running the
Data Link software on a 186/51 board. It begins with
the iSDM monitor signing on and continues into executing the Data Link Driver software.

iSDM 86 Monitor, Vl.O
Copyright 1983 Intel Corporation
.G DOOO:6
•• *** ••••• *****.*** •• **** •••• ** •• ** ............................. .

• 82586 IEEE 802.2/802.3 Compatible Data Link Driver •

•

•• ** •••••••••••••••••••••• ** •••••••••••••••••••••••••• ***** •••••

Passed Diagnostic Self Tests
Enter the Address of the Destination Node in Hex -> 00AA0000179E
Enter this Station's LSAP in Hex - > 20
Enter the Destination Node's LSAP in Hex - > 20
Do you want to Load any Multicast Addresses? (Y or N) -> Y
Enter the Multicast Address in Hex -> OOAAOOllllll
Would you like to add another Multicast Address? (Y or N) -> N
This Station's Host Address is: 00AA00001868
The Address of the Destination Node is: 00AA0000179E
This Station's LSAP Address is: 20
The Address of the Destination LSAP is: 20
The following Multicast Addresses are enabled: OOAAOOllllll
1-353

AP-235

Commands are:
T - Terminal Mode

M - Monitor Mode

v - Change Transmit Statistics

High Speed Transmit Mode

P - Print All Counters

C - Clear All Counters

A - Add a Multicast Address

Z - Dele.te a Multicast Address

S - Change the SSAP Address

D - Change the DSAP Address

N - Change Destination Node Address

L - Print All Addresses

R - Re-Initialize the Data Link

B - Change the number Base

Enter a command, type H for Help - > P
Good frames transmitted:

o
o
o
o
o

CRC errors received:
Out of Resource frames:
82586 Reset:

Lost CRS:
Maximum retry:

Good frames received:

Alignment errors received:

Receiver overrun frames:

Transmit underrun frames:

SQE errors:

Frames that deferred:

Enter a command, type H for Help --> T
Would you like the local echo on? (Y or Nl --> Y
This program will now enter the terminal mode.
Press 'C then CR to return back to the menu
Hello this is a test.

,"C CR
Enter a command, type H for Help --> M
Do you want this station to transmit? (Y or Nl --> Y
Enter the number of data bytes in the frame --> 1500
Hit any key to exit Monitor Mode.
of Good
Frames
Transmitted
#

of Good
Frames
Received

CRC
Errors

Alignment
Errors

00000

r CR
Enter a command, type H for Help --> X
Hit any key to exit High Speed Transmit Mode.

r CR
Enter a command, type H for Help --> R
Passed Diagnostic Self Tests
1-354

00000

No
Receive
Resource Overrun
Errors Errors
00000

00000

intJ

AP-235

5.3 Terminal Mode
The Terminal mode buffers characters received from
the terminal and sends them in a frame to the cable.
When a frame is received from the cable, data is extracted and sent to the terminal. One of three events
initiate the UAP to send a frame providing there is data
to send: buffering more than 1500 bytes, receiving a
Carriage Return from the terminal, or receiving an interrupt from the virtual terminal timer.
The virtual terminal timer employs timer I in the 80130
to cause an interrupt every .125 seconds. Each time the
interrupt occurs the software checks to see if it received
one or more characters from the terminal. If it did, then
it sends the characters in a frame.
The interface to the async terminal is a 256 byte software FIFO. Since the terminal communication is full
duplex, there are two half duplex FIFOs: a Transmit
FIFO and a Receive FIFO. Each FIFO uses two functions for I/O: Fifo_ln() and Fifo_Out(). A block
diagram is displayed in Figure 18.
The serial I/O for the async terminal interface is always
polled except in the Terminal mode where it is interrupt driven. The Terminal mode begins by enabling the
8274 receive interrupt but leaves the 8274 transmit interrupt disabled. This way any characters received from
the terminal will cause an interrupt. These characters
are then placed in the Transmit FIFO. The only time
the 8274 transmit interrupt is enabled is when the ReFunction
FIFO_T_INO

FIFO_T_OUT{)
FIFO_R_IN{ )
FIFO_R_OUT{ )

ceive FIFO has data in it. The receive FIFO is filled
from frames being received from the cable. Each time a
transmit interrupt occurs a byte is removed from the
Receive FIFO and written to the 8274. When the Receive FIFO empties, the 8274 transmit interrupt is disabled.
The flow control implemented for the terminal interface is via RTS and CTS. When the Transmit FIFO is
full, RTS goes inactive preventing further reception of
characters (see Table I). If the Receive FIFO is full,
receive frames are lost because there is no way for the
data link using class I service to communicate to the
remote station that the buffers are full. Lost receive
frames are accounted for by .the Out of Resources
Frame counter.
The Async Terminal bit rate sets the throughput capability of the station in the terminal mode because the
bottle neck for this network is the RS232 interface. Using this fact a simple test was conducted to verify the
data link driver's capability of switching between the
receiver's No Resource state and the Ready State. For
example if station B is sending frames in the High
Speed Transmit mode to station A which is in the Terminal mode, frames will be lost in station A. Under
these circumstances station A's receiver will be switching from Ready state to Out of Resources state. The
sum of Good frames received plus Out of Resource
frames from station A should equal Good frames transmitted from station B; unless there were any underruns
or overruns.

Table 1 FIFO State Table
Action
Present State
Next State
EMPTY
IN USE
Start Filling Transmit Buffer
FULL
ShutOff RTS
IN USE
IN USE
FULL
Enable RTS
EMPTY
IN USE
Stop Filling Transmit Buffer
IN USE
Turn on Txlnt
EMPTY
FULL
IN USE
Stop Filling FIFO from Receive Buffer
IN USE
FULL
Start Filling FIFO from Receive Buffer
EMPTY
Turn Off Txlnt
IN USE

SEND FRAMES

RECEIVE FRAMES

ASYNC
TERMINAL'

231421-15

Figure 18

1-355

AP·235

Recv_Data_l() will discard any UI frames received
unless it is in the Terminal Mode. When in the Terminal Mode, Recv_Data_l() skips over the IEEE 802.2
header information and uses the length field to determine the number of bytes to place in the.Receive FIFO.'
Before a byte is placed in the FIFO, the FIFO status is
checked to make sure it is not full. Recv_Data_l0
will move all of the data from the frame into the ReceiveFIFO before returning.

5.3.1 SENDING FRAMES

The Terminal Mode is entered when the TerminaL
Mode() function is called from the Menu interface.
The TerminaLMode() function is one big loop, where
each pass sends a frame. Receiving frames in the Terminal Mode is handled on an interrupt driven basis
which will be discussed next.
The loop begins by getting a TBD from the 82586 handler. The first three bytes of the first buffer are loaded
with the IEEE 802.2 header information. The loop then
waits for the Transmit FIFO to become not EMPTY,
at which point· a byte is removed from the Transmit
FIFO and placed in the TBD. After each byte is removed from the Transmit FIFO several conditions are
tested to determine whether the frame needs to be
transmitted, or whether a new buffer must be obtained.
A frame needs to be transmitted if: a Carriage Return is
received, the maximum frame length is reached, or the
send3rame flag is set by the virtual terminal timer. A
new buffer must be obtained if none of the above is true
and the max buffer size is reached.

When a frame is received by the 82586 handler an interrupt is generated. While in the 82586 interrupt rou. tine the receive frame is passed to the LLC layer and
then to the UAP layer where the data is placed in the
Receive FIFO by Recv_OctaLData_l(). Since
Recv_Data_l() will not return until all of the data
from the frame has been moved into the Receive FIFO,
the 8274 transmit interrupt must be nested at a higher
priority than the 82586 interrupt to prevent a software
lock. For example if a frame is received which has more
than 256 bytes of data, the Receive FIFO will fill up.
The only way it can empty is if the 8274 interrupt can
nest the 82586 interrupt service routine. If the 8274
could not interrupt the 82586 ISR then the software
would be stuck in. Recv_Data_lO waiting for the
FIFO to empty.

If a frame needs to be sent the last TBD's EOP bit is set
and its buffer count is updated. The 82586 Handler's
Send~rame() function is called to transmit the
frame, and continues to be called until the function returns TRUE.

5.4 Monitor Mode
The Monitor Mode dynamically updates 6 station related parameters on the terminal as shown below.

The loop is repeated until aAC followed by a Carriage
Return is recieved.

The Monitor_Mode() function consists of one loop.
During each pass through the, loop the counters are
updated, and a frame. is sent. Any size frame can be
transmitted up to a size of the maximum number of
transmit buffers available. Frame sizes less than the
minimum frame length are automatically padded by the
82586 Handler.

5.3.2 RECEIVING FRAMES

Vpon initialization the VAP module calls the Add_
Dsap_Address(dsap, pfunc) function in the LLC module. This function adds the VAP's LSAP to the active
list. The pfunc parameter is the address of the function
to call when a frame has been received with the VAP's
LSAP address. This function is Recv_Data_I().
Recv_DatlL-l() looks at the control field of the
frame received and determines the action required.
The commands and responses handled by Recv_
Data_l() are the same as the Station Component's
commands and responses given in Figure 15. One difference is that Recv_Data_l() will process a VI
command while the Station Component will ignore a
VI command addressed to it.

The data in the frames transmitted in the Monitor
Mode are loaded with all the printable ASCII characters. This way when one station is in the Monitor Mode
transmitting to another station in the Terminal Mode,
the Terminal Mode station will display a marching pattern of ASCII characters.

# of Good
Frames
Transmitted

# of Good
Frames
Received

CRC
Errors

Alignment
Errors

No
Resource
Errors

Receive
Overrun
Errors

00000

1-356

inter

AP-235

5.5 High Speed Transmit Mode
The High Speed Transmit Mode demonstrates the
throughput performance of the 82586 Handler. The
Hs~it_Mode() function operates in a tight loop
which gets a TBD, sets the EOF bit, and calls Send_
'Frame(). The flow chart for this loop is shown in Figure 19.
The loop is exited when a character is received from the
terminal. Rather than polling the 8274 for a receive

buffer full status, the 8274's receive interrupt is used.
When the Hs_Xmit_Mode( ) function is entered, the
hs_stat flag is set true. If the 8274 receive interrupt
occurs, the hs_stat flag is set false. This way the loop
only has to test the hs~tat flag rather than calling
inb( ) function each pass through the loop to determine
whether a character has been received.
The performance measured on an 8 MHz 186/51 board
is 593 frames per second. The bottle neck in the
throughput is the software and not the 82586. The size
of the buffer is not relevant to the transmit frame rate.
Whether the buffer size is 128 bytes or 1500 bytes,
linked or not, the frame rate is still the same. Therefore
assuming a 1500 byte buffer at 593 frames per second,
the effective data rate is 889,500 bytes per second.
This can easily be demonstrated by using two 186/51
boards running the Data Link software. The receiving
stations counters should be cleared then placed in the
Monitor mode. When placing it in the monitor mode,
transmission should not be enabled. When the other
station is placed in the High Speed Transmit Mode a
timer should be started. One can use a stop watch to
determine the time interval for transmission. The frame
rate is determined by dividing the number of frames
received in the Monitor station by the time interval of
transmission.

231421-16

Figure 19. High Speed Transmit Mode
FlowChart

1-357

inter

AP-235

APPENDIX A
COMPILING,LINKING, LOCATING, AND RUNNING THE
SOFTWARE ON THE 186/51 BOARD
*********

Instructions for using the 186/51 board

***.****.

Use 27128A for no wait state operation. 27128s can be used but wait states will have to

added.

Copy HI.BYT and LO.BYT files into EPROMs
PROMs go into U34 - HI.BYT and U39 - LO.BYT on the 186/51 board

JUMPERS REQUIRED

WIRE WRAP

Jumper the 186/51 board for 16K byte PROMs in U34
and U39 Table 2-5 in 186/51 HARDWARE REFERENCE MANUAL (Rev-001)

E36-E47IN
E39-E44IN
E79-E45IN

186/51(E8)
E151-E1520UT
E152-E150 IN
E94-E95IN
E100-E1061N
E107-E113IN
E133-E134 IN

186/51 (8)/186/51
E199':"E203 OUT
E203-E191 IN
E120-E119IN
E116-E112 IN
E111-E1071N
E94-E93IN

USE SDM MONITOR
The SDM Monitor should have the 82586's SCP
burned into ROM. The ISCP is located at OFFFOH.
Therefore for the SCP the value in the SDM ROM
should be:

also change interrupt priority jumpers - switch 8274
and 82586 interrupt priorities
E36-E44 OUT
E39-E47 OUT
E37-E45 OUT

E43-E50 IN
E46-E47IN
E90-E48IN

E43-E47 OUT
E46-ESOOUT
E44-E48 OUT

. ADDRESS
FFFF6H
FFFF8H
FFFFAH
FFFFCH
FFFFEH

DATA
XXOOH
XXXXH
XXXXH
FFFOH
. XXOOH

To run the program begin execution at ODOOO:6H

1-358

inter

AP-235

I.E. G DOOO:6
GOOD LUCK!
** •• *.***.

submit file for compiling one module:

***** •• *.*

run
cc86.86

:F6:%O LARGE ROM DEBUG DEFINE(DEBUG) include(:F6:)

exit
submit file for linking and locating:

**********

run
link86

:F6:assy.obj, :F6:dld.obj, :F6:11c.obj, &:

:F6:uap.obj, lclib.lib to :F6:dld.lnk segsize(stack(4000h)) notype
10c86 :F6:dld.lnk to :F6:dld.loc&:
initcode (ODOOOOH) start (begin) order(classes(data, stack, code)) &:
addresses(classes(data(3000H), stack(OCBOOH), code(OD0020H)))
·oh86 :F6:dld.loc to :F6:dld.rom
exit
*.***.****

submit file for burning EPROMs using IPPS:

ipps
i 86

f :F6:dld.rom (OdOOOOh)
3
2
1

to :F6:10.byt

1 to :F6 :hi. byt
y

t 27128
9

c :F6:10.byt t p
n

C :F6:hi.byt t p
n

exit

1-359

••••••••••

inter

AP·235

IPCO/VSR/CHUCIVCSRC/DLD. H

.•
I

.•

**************************••• ***.**************************.********.***
821586 Structure. and Constant •

*.***.*********************.****.****************************•••****•••** I
.d.'ine INUSE
.CI.fine EMPTY
ede'ine FULL

.d.flne FREE
.d.'ln. TRUE
.d.fline FALSE
.d.'ine NULL

o
1
2
1
1

o
O.FFFF

.d.flno RBUF _SIZE
.d.'in. TBUF _SIZE
.d.fln. ADD_LEN
.d.fine mJLTI_ADDR_CNT

.d.fin.
.d.fin.
.d.fin.
.ddtn.
*d.ftn.

128 I . ,..ceive buffe" .ize *1
12B 1* trans.it buffe" size *1
6
16

PASSED
FAlLEDJlIAQNOSE
FAILED_LPBK_INTERNAL
FAILED_LPBK.-EXTERNAL
FAILED_LPBK_TRANSCEIYER

'* Exchang.
UnnuMb.r.d 111'OT' ... ation F,. •• e
Identification

1* F ...... Co. . . nd. *1
VI
0.03
KID
O.AF
TEST
0.E3
.d.fin*
P J" JIlT 0.10
C_R_BIT 0.01
.d.'ine

.d.fin*
.d.'in.
ed.fine

0
1
2
3
4

1* Rellot. Loopbac It r •• t *1
1* Poll/Final Bit Position

COlMland/R •• panse bit in aSAP *1

DSAP_CNT

1* Numb." Df .110 ... b1. DSAP., MU.t b • • • uttipt.
Df! 2**N. And DSAP .dd" •••••••• igned Must b.
divisibl_ bU ~**(B-N).
(i... the N LSBs mu.t b. 0) *1

DSAP _SHIFT

1* DSAP _SHIFTS must ellu.l B-N *1

XID_LENQTH

1* Numb." of Info but.s fo" XJD Re.pon.e '1" •• e */

Svstem Configu .... tion Point." SCP *1

It"uct SCP

u_sh01"t s".buIJ
82586 bu. width. 0 I-Bbits-'

16 bit.

231421-17

1-360

inter

AP-235

IPCD/USR/CHUCII/CBRC/DLD. H
U_ShOTt Junk tall

u_shOT't iscp11

u_sho1't iscphJ

1* IOllle" 16 bit. of isep .dd,. ••• *1
1* upper B bit.
isep add" •• s *1

'* Int.,..ediat. S,stem Con'igu.... tian Paint.,. JSep
Jsep
u_sho'l"t bus,;
,*•• t to 1 bV cpu b.'ol'.
*1

stT'uct

its first CA.
cl •• r.d b\l 82586 .fte" ..... ding
J
1* of, •• t of .vst ... control block *1
u_lho1"t b ••• l J 1* b ••• 0' IVlte .. control blocl!
u_shol't b ••• ;: J

u_sho1"t of" •• '

)

1* Svstam Cont1"ol Block

sca *1

_truct SeB
u_shOl't
u_sha ... t
u_sha ... t
u_.ha ... t
u_sha,.t
u_sha,.t
u_sha,.t
u_sho,.t

'*'*'* Ca ••and a.wordfi,.s,*'
'* CRt ."1'0,.
t of
'"am.
'*'* Alignr..nt ...ceu_ul.t.d
Ov.,.,.un

St.t,
cllld.
cbl_affs.t,
,. •• _o •••• t.
c,.C_.,.,.SI
1*

St.tus IAIOT'd *1

,.IC_8,.,.I,

Fl"am •• lost beCAU •• of no R•• ources *1
.I"TOrS *1

.1"_.,..,.1.
OV" _81'1'1'

Off •• t
Of, ••

ca_and block in CBL *1
d •• c:riptoT' in RFA *1
*1
.'1"1'0 .... *1

"11-st

Comm.and Block

struct

u_Ihort
u_short
u_lhort
u_short
u_Ihart
u_lhort
u_short
u_shol't
u_.h o,.t

It.t,
cllld,
11nlIJ

p.,..I,
pa,..2,

1* StatuI of Cam... nd *1
1* Co . .and *1
1* 11nll 'ield *1
1*
t ..... *1

P.,. ....

p.,..3,
p.,.",4,
p ...... "

pa,.1I6,.

Multicast Add,. ••• COIIIII.. nd Black t1A_C8 *1
.t,.uct "A_C8(

u_Ihart st .. t,
u_Iho1"t c.d,

1* St .. tus of ComlR .. nd *1
1* COIII... nd *1
1* Lint fi.ld *1
1* Number of t«: .dd,. ••••• *1
cha,. mc_add ... [ADD~EN*t1ULTJ_ADDR_CNTlJ 1* MC add,..ss ar.a *1

u_sho,.t l1nll.
U_lhD1"t IIIc_cnt.
),

struct TID

231421-18

1-361

inter

AP-235

IPCD/USR/CHUCK/CSRC/DLD. H

u_short act_cnt;

1* Number of bvte. in buffer *1
1* offset to next TBD *1
1* low.,. 16 bits of bUffer address *1
u_sho,.t buff_h.
1* uppe"f a bits of buffer address *1
.truct TB .buff J t r i
1* not used by the 586: used by the

u_short link.

u_short buf!f_Ii

soft",.". to save address translation
routine.

1* Transmit Buffers *1
.truct TB
char data CTBUF _SIZE];
},

1* Frame Descriptor FD *1
struct

{
1* Status Word of FD *1
1* EL and S bits *1
1* link to next FD *1
v_short rbd_offseti
1* Receive buffer descriptor offset *1
char d.st_addrCADD_LEN]; I*Destination address *1
char src_addr[ADD_LEN]; 1* Source address *1
u_short length;
1* Length field *1
U_shOTt stat;

u_shoTt el_51
u_short link;

1* Receive Buffer Descriptor RBD *1
struct RBD {
u short act_cnt;
u=shoT't link;
u_short buff_I;
u_short buf' _hi
u short si lei
struct RS *buffJtri

1* Actual number of bytes received *1
1* Offset to next R8D *1
1* Lower 16 bits of buffer address *1
1* upper B bit5 of buffer address *1
1* size of buffer *1
1* not used b\l the 586: used by the

software to save address translation
routine.

1* Receive Buffers *1
.truct RB
char d.taCRBUF _SIZEJ.
},

struct

FRAME_STRUCT

unsigned c·har
unsigned char
unsigned char

d5apl
55aP.i
cmd;

1* Dl"stination Service Access Point *1
1* Source Service Access Point *1
1* ISO Data Link Command *1

1* LSAP Address Table *1
stT'uct LAT {
stat;
char

1* INUSE or FREE *1

231421-19

1-362

AP-235

IPCO/USR/CHUCII/CSRC/DLD. H

lnt

(*p_s.p_func) C)J 1* Pointe,. to LSAP function;
wi th d •• p addr ••• *1

•• sociat.d

);

.tT'uct MAT {
char
char

.tat,

1* l'1ulti, ... t Add,. ••• Tabl. *1
1* lNUSE, 01" FREE *1

ad d,..tADD_LENlJ

1* actual me addr ••• *1

};

.truct FLACS {
unsigned diatl_done

unsigned stat_an :
unsigned " ••• t_s.m. 1,
unsigned r ••• tJend 'I ,
unsigned Ipbk_t •• t: 1 ;
unsigned Ipblc_lIod.:

diagno •• co.mand complete *1
netwDl"k diagnostic .t .. ti.tics anloff *1
don 't 1" ••• t when this bit i . set *1
T ••• t when this bit i • • • t *1

loopback t •• t flag
1* loopbole II mod. anI off *1

_d.Hn. ELBIT
_d.fine
.d.fine
.d.fine
.d.,ine
.d.fine
Itd.,ine

1 ,

1*
1*
1*
1*

EOFBIT
581T
181T
CDIT
BOlT
OKBIT

018000
018000
014000
012000
019000
0114000

012000

sea patterns *1

ede,ine
.d.fine
edefine
.de'ine
.d.Hn.

ex
FR
CNA

RNR
RESET
.d.fin. CU_START
.de'in. RU_START
"define RU_ABORT
_d.fin. CU_t1ASK
.. d.fine RU_MASK
.define RU_READY

.de'ine NOP
ed_fine IA
_d.Hn. CONFIGURE
.define Me_SETUP
.define' TRANSMIT

.define TDR
ed.fine DUMP
.dofin. DIAGNOSE

019000
014000
01:1000
011000
010090
010100
0.0010
0.0040
010700
010070
010040

010000
010001
010002
Ox0003

010004
010005
010006
010007

231421-20

1-363

Intel

AP-235

IPCD/USR/CHUCIVCaRC/DLD. H

B2S86 Co. . .·"d anti at.tua ...... .,

•• 0Uno
•• 0Uno
.doftno
Id.Uno
Id.Uno
"oftno
ldoUno
Idoflno
ldoUn.

•• 0Un.
',o.lno
Ido.ln.
••• fln.
.'.'in.
••• fin.
••• flno
Id.fln.
".fin.
••• fin.
••• fin.
••• fin.
•••• Ino
••• fin.
•• ofin.
1d.'ln.
••• fin.
••• Un.
••• Un.
Id.Un.
••• fln.
••• fln.
1 •• Un.
1 •• Un.
".fln.
I •• fln.
I •• fln.
1 •• Un.
I •• fin.

CIID__
_RaIT
CILL_
DEFER_
NDCR_

010007
012000
01000F

Olooeo
010400
010100
_
010040
I'IAXCILI'II\BI\
010020
OUT_OFJlElIOURCEB DIDaOO
UNDERR~SK

FIFD_LI"
BVTE_CNT
BRDV
BAV..JIF

010B00
01000.

DIOO4D
Olooeo
010600
AC_LDC
010B00
PR~J.EN
012000
INTJ.PBCK
014000
EXTJ.PBCK
01_
,.
LINJRID
010000
ACR
010000
BOFJ£T
Olooao
IFB
016000
BLOT_TIlE
Oloaoo
I •
RETRV.-NUII
OIFOOO
PR"
·010001
aeJlIB
01_
_lESTER 010004
TONII_CRB
010008
NCRC_INS
010010
CRC_I.
010020
aT_STUFF
010040
PAD
Dlooeo
CRBF
010000
CRB_SAC
010B00
CDTF
010000
/.
CDT_aRC
01_
"IN..FR"J.EN 010040
1*
"INJIATAJ.EN "INJ'II"J.EN ADDR~N

no p .. iol"1 tv . /
IFS ti •• 9.6 u •• e . /
•

lot t:l •• 51.2 u •• e ./

/..... t,...

nUld•• "

no col11.ian .etect "lit."
64
IB

~,t

*1
1* . . . u. . .

t..

Et~ ...n.tIlEEE

• .,.•••••1til 6

It,

802.3

of •• d......

*'
231421-21

1-364

AP-235

IPCO/U9R/CHUCK/CSRC/DLD. C

.•

1**•••••** •••••••••••••••••••••••••••••••••••••••••••••• ***********.*.***

••••••••••••••••••••••••••••••••••••••••••••••••••••••·····*****···**·***1

D.fine constanta fpr .to.... g.

tlde'ine CB_CNT

tld.'ine FD_CNT
tld.fine RBD_CNT
*d.'ine TBD_CNT

I.
I.
I.
I.

B
16
64
16

_1' ••

IIdofin. INTERNALJ-OOPBACK
IIdofine EXTERNAL_LOOPBACK
IIdofino NOJ-OOPBACK

0.4000
0.9000

.include "dId. hlf

1* 186 Timer Add,. •••••
IIdefino
IIdefino
IId"ino
IIdofino

1* 110
int

T1I1ER1_CTL
T1I1ER1_CNT
T1I1ERO!_CTL
T1I1ER0!3NT

inw()s

NUllbe .... pf Avat lab Ie COlMland Blocks *1
Nu.be", pf available Fr.".. D•• criptoT's *1
NUlnber pf ilvail .. bl. Receive Buffer descriptors *1
NUllbe ... pf availabl. Transmi t Bu"." d.scriptors *1

0.0000
~b

Datil Structur •• *1

O.FF~E
O.FF~B

0.FF66
0.FF60

input !IIord :

'*1* output word:

inlll(.ddl' •• ' )

void

out"'()J

void
void
void

init_intv()J
initi.liz. the interrupt vector tab I., */
enable()J
/* en.ble 80186 interrupt. */
di.abl.,();
/* disable 80186 interrupts */

9EQI1TI

*pNlA..Li

tlde'ine CA

outIllCOICS,O)

outlll(.ddre.s, value) *1

1* Dat. . . egment. value */
NULL point.,. */

1* the command to issue

Chilnnel Attention */

.d •• ine ESI_LDDPBACK out ... (OICB,O) /* put the ESI in Loopbeck */
Idefine NO_ESI_LOOPBACK outlllCOICB,8) /* t.k. the ESI out of Loopback *1

Idefine EOI_80130
outb (OlEO, 0163)
/* End Of Interrupt
ede,ine Tlt'lERl_EOI_80186 out ... (OIFF.ii!.ii!, 0104)
EOI for Ti",er 1 on the lBb */
.d.'ine TI"ER1_EDI_B0130 outb (O.EO, 0.64) /*E01 for 186 's Timer1 on the 130 */

231421-22

1-365

AP-235

IPCO/USR/CHUCK/CSRC/DLD. C

, ••• *****

memorv

******.* ••••****1

.11,De.-tio"

1* used '01' diagnostic purpoilel *1
1* t •• po,.."" .torage *1

,i.nt Self_Te.tJ
u_Ihot't tempI

_define LPBKjRAI'IE_6IZE
4
ch.r
lpbk_'r.... [LPBKjRAI'IE_SIZEl = {
Ox55,

O.AA, 0.55, OxAA)-,

.d.,U.n. IIIho.mi_io_add
char

O.OOFO

IIIhoamitADD_LENll

unsigned long

IJDod_xmit_cntl

u_sh01't
u_IhDl't

und.1',-u"_cntJ
no_erl_cntl
d.f .... _cnt;

unsigned long
u_Ihol't
u_shoT't

unsigned lang

u_Ihort

1* 110 add,. ••• of HOlt Add,.. .... Prom *1
1* Ram a" .... V whe,.e host add,. •• s is stored *1

Sq __OTt" _cnt;

mill_col_cnt;
".cv_frame_cnt,
r ••• t_cnt.

Allocate .. torag. fo1' structure. and buffers *1

struct FLAQS flag5'

1* SlJltem Configur.tion Pointer: Rom Initialilation *1
1* struct SCP ICp • {O.OOOO. OxOOOO. 0.0000. 0.lFF6. 0.0000)1

struct sce scbl

1* Svstem ContT"ol Block *1

struct CD cbCCB_CNTJ,
1* Com ... nd Blocks *1
*cb_tas. *begin_cbl. *end_cbll
1* pointer to the beginning of the fre.
camm.nd block list ,
QutbCO.E2, O.OOF7. e),

'*'* wl'it.

r •• d the 80130 int.,.,.upt ••• k registe", *1
to the 80130 lnt.,.rupt tunk Tegt.t.,.

Di •• bl*_SB6_1nt( )

tnt

c •

InbeO.E.!),

Qutb(OxE2.

0.0008 f e).

outwCTlf1ERl_CNT. 0),
Dutw(O.FFSE, OxEOO9)I

WY-it • • 0 to T1111.1"1 count r.giater */
1* S.t EN.bl. blt in Ti •• rl Hade/Control ,..giat.r */

)

R••• t_Till.out( )

outwCO.FFSE, 0.6009),

/. R••• t EN.bl. bit in Tillle,,1 Hode/Control ,.egist.r *1

lnit_Tiller() /* 186'. Tt •• r til: i • • pre.c.l.r for Ti ... r 1. It clock., Ti ... ,. 1
.v.,. .. 32.7 .... c. The d •• d... n tt .... out i • • • t fa,. 1. 25 •• c *1

outlll(O.FF38, O.OOOC) 1
/* Set Timer1 Inte,.rupt Cont,.ol ,..01.t.1'
outw(O.FF62, O.FFFF);
/* .et .... count re.i.t.,. '01" ti •• r2 to OFFFFH *1
out..,(O.FFSA,
38);
/* •• t ••• count regi.ter ,A for timer',1
autw(O.FF66, OICOO1),
/* Set Ti.er2 Hade/Contral registel'
Dut..,CO.FF:5E, 016009),
/* Set Ti ... rl Hade/Contf'ol register *1
aut..,(O.FF2B, CinwCOIFF28) .OIFFEF»1 1* En.ble 186 Timer1 intel'rupt *1
outbC01E2, (1nll(0IE2) .0100EF»,
1* en.bl. 90130 inteT'rupt from 8018b *1

*' *'

)

1* .nd hilrdw.re .upport function.

*'
231421-24

1-367

lme

AP-235

IPCD/USR/CHUCIVCSRC/DLD. C

.eb.

(1"C_8"" • •

O•

• eb .• 1"_e"" • • 01
leb. "'C_8""" • 0,
leb. ovr _eT''' , - 01

IDOd_Illi t_cnt - O.
undel"'I'u"_cnt • O.
riD_CI",_cnt -, OJ

de'.", _ent • OJ

.,e_.".,._ent •

O•

•• x_col_ent • 0.

~:~:t:=::~=C~~

- o•

• tl'uet ISCP .pi.c,.
u_lhoT't Ij
.t,-uet MAT .p•• t,

NO_ESI_LOOPIACK.

Don. '01'

82~1.

in 100p"acll

Inactivat •• CRS 1f pow.red up

1* Inlti.1:I,18tlon DLD. inte"T'upt veeto1'"

'1 •••. " ••• t_. . . . . OJ

,1a,l. ,. ••• t.;.Jt.nd .. 0;
'1 •••. stat_on - 1,

p~:,cp.

OIOOOOFFFO,

pi.cp->bu'lj .. I.

Initialile the

pile ,->b ••• 1
p1.cp->b ••• 2

O" •• tC •• cld,
- BEOfifr « 4.
iii, (SEGt1T ». 12) •

Jeep point ..... ,

,1.c,->o" •• ' -

O.OOOF

*' *'

,NULL - Build_Pt,.(N\JLL),
'e build .. NULL point.,. - 80S6 tvp.: 32 bit,
Build_R'aC),
1* init Receiv. F" ••• A.....
Build_CbC)I,
:f.nit Co __ nd Bloc. l:f..t
~-_cb. Cll'ld - OJ
Multic •• t .dd,. ••••••• pllo,.. :f.n:f.t *1

'or

- OJ

OxFFOOJ

:f. ++)

231421-25

1-368

inter

AP-235

/PCO/USR/CHUCK/CSRC/DLD. C
if Cscb •• t.t _. (eX I CNA»
br •• I"

If (i >OxFFOO)
F .. t.l("DL.D: tn1t - Old not get an interrupt .1ft." R••• t/CA\n");

1* Acll the r ••• t Int.,.rupt *1
leb. cMd '. (eX I CNA)J

CAl
Wait_6cb( ),

Enab 1._~86_Int(),

scb. cbl_off •• t • Off •• t(.cbCO]),
acb. ",'a_of, •• t • Of, •• t(.'dCOl),

'or

0,- 1 "ADDJ-ENI

who ... iC(ADD_LEN -

linll: leb to tb and f1d lilts *1

1++)
-

tl •

inbCwho .... i_io_.dd + 1*2),

Initia11zatlon the l'1u1tlcast· Add,.. ••• Table *1

'or (pm.t . . . . tCOll p ... t
p •• t->.t.t • FREEl

""'atCtwLTl_ADDR_CNT -

CanH gu,.. (INTERNALJ-OOI'BACKIl

T. . tJ-ink(

III

pm_t++)

Put '86 1n internal loopback *1

if (S.I'_T •• t

!- PASSED)

".turn (S.l f _T •• t) J

)

Build~"(
{

)

struct

*p.dl

ItT'Uct

RDD

.p"bd,
.pbu'l
badd,

,t,.uct

RB
unl1 gned 1 Dng

Build .. lin •• r

for (pfd - .fdCO]1

linked
pfd

.r...

deacriptor list *1

.fdCFD_CNT -

ill

pfd++)

pfd->.t.t • pfd->.l_• • 0;
pfd->lInk - O" . . tlp'd+Uj
pfd->rbd_off •• t • NULLI

231421-26

1-369

.AP-235

IPCO/USR/CHUCK/CSRC/DLD. C

end_fd - --p'd;
point to .'dCFD_CNT - 1) *1
,'d-:>11nll - NULL,
1* 1•• 10 'd l1nll ia NULL *1
,'d-:>el_, - ELBITJ
1* 1 •• 10 'd h •• EL bit •• 10 *1
begin_'d - pfld • • 'd[O];
paint to fir.t 'd *1
,'d-:>1"bd_o" •• t - O" •• 1o(.,.bd[O])" 1* link '1"110 'd to 'Ir.t "bd *1

1* Build. lin •• ,. linked receive bu,fe,. d •• criptol' list

'or (pt'bd - ..... bdCOl,
badd - SEO"T

IUtu' - .,-bu'[OlJ prbd

It'rbdtRBD eNT - lJ ..
prbd++. pbuf++) -(

« .,

b.add +- O" •• t(pbu').

,,.bd-)bu" _1 - badd,
prbd->bu'f _h •

badd

161

p1'bd->bu" -p1or • pbu',

prbd->.ct_cnt.

,,.bd->linll - O., •• t(p'I'bd +
,1'bd-:>,11 • • RBUF _BIZEs
end_"bd .. --p'I"tld.

'*'*

,1'bd->1 inlr - NULL,
,,.bd->.11. :- ELBITi

Build_Cb()
(

.'.t *'*'

1 •• 10 l'bd paints to NUL.L
1 •• 10 1'bd h •• el bit

Build. stAck 0' ,,. •• COMMAnd block. *1

.t,.uct
.tl'uct

CB .pcbl
TBD *ptbdl

,t,.uct

un.igned

1);

.pbufl
IDng

bAcldJ

,"0,. (pcb - IccbtOlJ pcb <- IccbtC8_CNT pcb->st.t • OJ
pcb->cllld - ELBITJ
pcb->linll - O'f •• t(pcb + l)J

III

pcb++) (

--pcb;
begi"_cbl ... end_cbl • pNULLI
pcb->11nk • NULL;
Cb_tD5 •

,O~

IItcbtOl;

(ptbd • Ubd[Ol.

pbu' - .. tbuf[Ol,

ptbd

"tbd[T8D3NT -

Il.

ptbd++.

pbufl++)

ptbd->Act_cnt

• TBUF_SIZE,
ptbd->lInk - Ofhot(ptbd + II.
b.dd • SEOI'IT

231421-27.

1-370

inter

AP-235

IPCD/USR/CHUC~/CSRC/DLD.

hdd _

D' . . . U,bu'),

ptbd->bu" _1 - "add,

ptbd->bu •• _h - badd »
ptbd->buf' .."tl" • pbu',

--ptbd.
p1obd->11nl& • NULL'
1:bd_t05 • •1obd[O],

161

1* 1 •• 10 tbd link t. NULL *1
Set the Top Of the Staclr

>
.true1o

.Oet_CIIO

{

.1o'l"uet

return. point.,. to ....... co ••• nd black *1

CB .pcb.

if (O., •• 1;(p,b - ell tos) •• NULL)
,.etu1'nCpNULL)J
eb t05 • (.1o,.uc1o CB .) Build_PtrCpcb->.linkh
pCb->linll: ... NULL,
... etuI'nCpcb),

'* Put. Co......nd Block back
s101"Uc1o

onto th. 'r •• list

CB .pCDI

pcll->.t.1: • 0,
pcb->link - O•••• 1o(cb_1:os),

eb_to. - pcb,

>
.truet TID

.g.t_Tltd()

'* return a point.,..
*'

to •

'1" ••

tran •• it buffer

d •• '1'1pto"

.1;"uc1o

TBD

.1a.s. r ••• t_s.m• • 1,
Di •• bl._~86_lnt( ),
i f CCptbd - tbd_tos) !- ,NULL) {
1olld_1005 • (.1o,.uc1; TID .) BuildJt,.Cptbd->link);
ptbd->l ink = NULL;

Enabl._586_JntC );
f 1.11 •. ,. ••• t_••••• OJ
if Cfl •••. ,. ••• t...".nd
R ••• t_586C )J
-r.tu-rn(ptbdu

231421-28

1-371

AP-235

IPCD/USR/CHVCK/CSRC/DLD. C

.. truct

T80

*ptbdJ

{

.truct
j.

TBD

find the end of the tbd list retU1'ned.

for (p

ptbdJ

ptbd is the b.ginning *1

,->11n. !- NUL..:L p " (.truct T8D.) 8utld_PtrCp-)linlc»

p->.ct_cnt • TBUF_SIZEI

1* cl •• ,. EOFBIT and update slz. on l.st tbd *1

p->11nlc • O" •• tCtbd_ta.),
tbd_tos .. ptbdJ

.t,.uct

:. f

.pcb,

pcb -

O.t_Cb (»

pNULL.)

F.t.lC lO dld. c - S.tAdd" ••• - couldn't get. CB\n"),

pcb • O.t_Cb ();
".ndif

1* DEBUQ *1

bcoPV«ch.,. .)lrpcb->parlftl,

hhoa.i[O],

ADD_LEN),

'* addr ••• to

IIIIDve the p-rOll

I" cmd *1

pcb->ctld • IA I ELBITJ
t •• u._CU_'md (II cb» J

'or <.t.t - FALSE, .tat •• FALSE,
faT"

) <

(1=0; i<=O.FFOOJ 1+"')
if Cscb. enid
0)
br •• k;

i f (i

O.FFOO) {

Bug ("DLD:
CAl'

Seb cOMMand nat cl •• ,.\"N),

.1 ••

st.t • TRUE.
231421-29

1-372

inter

Ap·235

IPCO/USR/CHUCK/CSRC/DLO.C

I •• ue_CU_Cmdlpcbl 1* Gueue up • co••• nd and issue. start CU com.and if no
other co ••• nd • •re tueued *1
.truct CB *pcbl
-(

Ois.ble_'S6_1ntCII
if Cbegin_cbl •• pNULLI -(
1* if the li.t i. in.ctive .tart CU *1
begin_cbl • end_cbl
pcb 1
.cb.cbl_offs.t
tCpcbll
W.it_ScbC II
.cb. cmd • CU_STARTI
Set_T·jm.outC II
1* .et. deadman tim.r for CU *1
CAl

.0" ••

.1 •• -(

end_cbl->link • O'f •• tCpcbll
.nd_cb 1 - pcbl
}

En.b 1._'S6_Int CII
hr7CI
-(

outbCO.EO. 0.6711

1* EOI 80130 *1

}

Isr6CI
-(

Writ.C"\nInt.rrupt 6\n"11
outbCO.EO. 0.6611
1* EOI S0130 *1
I.r"

Writ.C"\nInt.rrupt '\n"ll
outbCOIEO. 0.6'11
1* EOI 80130 *1

Isr _Tim.outC I

1* Int.rrupt 4 *1

R••• t_Tim.out CII
if Cfl.g •. r ••• t_•••••• 11
'lags.r ••• t-p.nd • 11
el.e
R... t_'S6CII
TlMER1jEOI_801B61
TIMERljEOI_801301
1* Int.rrupt 0 i. U.rt in UAP Modul. *1
1* Interrupt 2 i. Ti •• r in UAP Modul. *1
231421-30

1-373

AP-235

IPCO/USR/CHUCIVCSRC/OL.D. C

Is,..U)
(

W"tte("\nlnt.,.,.upt 1\n-).
Dutb (OxEO,

0.61) I

EOI 80130

1* 586 Int.rrupt ••,.vice routine:

u_'ho"t
• truct CB

*'
.i

Interrupt 3

,tat_Ieb •
.pcb;

w.t t_Scb () I
leb. cfltd •
CAl

(Itat_Ieb • leb. stat) " (eX I CNA I FA I RNR)I

i f (st.t_scb .. (FA I ANRI)

Recv_lni:_Proc ••• ing () J

R.I.t_Ti •• outC),

'* cl •• ,.

d •• dman t1 •• "

pcb - BuildJtT"lcb. cbl_o.f •• t),

if (be,1n_cbl •• pNULL)(
BugC"DLD: be.ln_cbl •• NI.A..L in int.,.rupt: "'Gutin.'""),

,..turn,

if «pcb->_t.t .. O.COOO> !- 019000)
FetalCuDLD: C bit: not: •• t OT' B bit .et in int.l'rupt rGutine'""',

•• nd i f /* DEBUQ */
s .. ltch (pcb->clOd .. CI'ID_I'IASII)

c ••• TRANSt1JT:

'* this

0 and th.,.. .... e",e no collilionl -> sq. • • ,.,.01'
condition w111 OCCUT on the fi,..t 'tranllli •• lon If

if . , . bit -

th.,.. . . . .,.. no col1i.ion.~ 01" l ' th'e p1"eviou. t1"_n •• tt
cOIIHR_nd 1"e.ched the
collision count. and the CU1"1"ent
t1".nlmls.1on h.d no colli.lonl */

,.A.

I f «pcb->st.t .. (BOEI'IABII I I'IAXCDL./'IABI\ I COL.L.I'IASII))

++511.._e,.1' _cnti
I f (pcb->.Ut .. DEFEAI'IABI\)

++d.fe,. _cntJ

231421-31

1-374

intJ

AP-235

/PCD/USA /CHUCK/CBRC/OLD. C

if (pcb-:>.t.t • NOERRBIT!
++gaod_".i t_cnia
el •• (

if (pcb->.t.t • NOCRSI1ABKI

++no_c .... _cnt.
i f (pcb-:>.t.t • UNDERRUNI1ABKI

++und.,.,.U"_cnti
i f (pcb-:>.td • ""'XCDL ......SKI

++•• I_col_cnt.
}

. if Cpcb-:>p ..... l

!- NULL)

Put_TU(Bui1dJ't~(pcb-:>p.~.III'

c...

b,. •• k.

DIACINOSE:
flag •. dial_don • • 1.
i f «pcb-:>.t.t • NOERRBlT! •• 01
S.1f _T•• t • FAILEDJlIAClNDSE,
11,. •• 111

'* check
if

to •••

anothe,. co_and is queued

(pcb-:>Iln~

- NULLI
be. in_cit 1 - pNULL.

be. in_cbl - Bui Id-Pt'l' (pcb-:>1 inlc) J

seb. cbl_D" •• t • pcb-:>11n.;
W.it_Scbll'
seb.

c.d • CU_BTARTi

CA,
Woit_Scb II,
/ . START d •• d •• n ·t1111 ....

Set_Ti •• outC)1

*/.

}

i f « pcb-:>c.d • CI'IDJ1ABKI •• I'IC_SETUP 1

pcb->clld • O. /. cl •• 1" "C_SETUP clld wOl'd.

this \11111 implement ..

lock •••• pho .... so that it won't be Tlfused until
it t. CDlllpleted *1

.1 ••
put_eIlCpcb).

dis.bleC)i
EDI_BOI30,

~-.sETUP cmd bloCIl.
It's not iJ
.en.,..1 put-po •• ca ....... nd block "T'DIII fr •• CB list *1

Don't .... tu1"n

'* 'U •• b1. cpu

int so th.t the ~86 is ... l8Iill not nest *1

231421-32

1-375

AP-235

IPCO/USR/CHUCK/CBRC/DLD. C

R.Cv_J"~J"Dc:e •• in8(

)

-C
.tT'U~t

.pfdJ

.truet

ROD

*11.'

point. to the Fra ... D.,cT'iptof' *1
1* pointl to the l.,t ,"bd for the , ......
.p".ltd; 1* p,ointa to the firat "bd fa,. the ,,.. ••• *1

for (pfd - '_111"_'dl pl. !- pNULLI
i f (pfd->.t.t .. CIIT) -(

pld -

begln_fd)

begin_' • • <,truet FD .) BuildJt1"Cpfd->link)J
prbd • (strut't RBD .) lu:t.ld~t'l"(pfd->"bd_off •• t)J
i ' (p,..bd !- pNULL) ( 1* check to ••• if • bu',." t, .ttached *1

•• ndl'

if (p,..bd !- be.l"_"bd)
F.t.l(~DLD: p"bd !- begln_Tbd in Recv_lnt'yroc ••• ing\n")J

DEBUg

*'for

(q, •

prbd,

(Il->act_cnt Ie EOFBIT) !- EDFBITi
, - (,t.,.uet RBD .> 8ui·ld_PtrCIl-:>link».

b •• in_1"bd • (,truet RID .) luild_Pt"CII.->link),
,->11n • • NULL.
~

i f (pfd->.t.t .. OUT_OF _RESOURCES)
Putj''' •• _RFACpfd) I

el •• (
1* if the DLD i. in a 100pb.ck te.t,

if ('l •• s. lpbk __ od • • • 1)
Loopb.c k_Chee k (pfd) J
e1 ••

check the flra ..e recv *1

1* i. it'. _ .ultic •• t add" ••• ch.ck to ••• if it'.in the Multic •• t add" ••• tab I •• if not disc.rd the flr •• e *1

if ( «p'd->de.t_.ddrCOJ

II: 01) -

01) ••

(!Ch.ck_"ultlc •• t(pfd»)

Put..Fno.JIFA( p fd) I

.1 ••

(

R.cv_Fr ••• (pfd),
++recy_'" •• e_cnt,

e1.e (

Ru_St.rt<), 1* I' RU has .one into no- ..... ourc ••• r •• t."t it *1
br •• k,

1* C.ll.d b\l R.cv_lnt"p"oc ••• ings checks .ddr •••
and d.t.
pat.ntial laopback fI ...... *1
.truct

.truct RBD
.tl'UC t RB

*p'df

*prbd,
.pbu',

231421-33

1-376

~P·235

IPCO/USR/CHUCK/CSRC/DLD. C
if C be.pHehA,. .) 'p'd->.,.c_addrCOl, lI.ho.raiCOl, ADD_LEN) !- 0 ) -(
Putju • ....RFACpfd II

,..tur"J
)

,l"bd •

CstT'uct RBD .) Build_ptrCpfd->,.bd_of, •• t ) ;

point to

,..t.iv.

buff.,. d.scriptor *1
,bu' • cst,.uct RS .) prbd->bu"J'I;rJ /. point to ,..cetve buff.r *1
If C bClOp((ch ... *) pbu', .. lpbk_f ...... tOl. L.PBKjRA"E_SIZEI != 01 (
Putj........RFACpfd)1

r.turn,
'leg', Ipbk_t •• t - II.
Putj .... ....RFACpfd)1

p •••• d loopb.cl! t •• t

'* 'l'etu1"'ns t,.ue

Check-"ulticastCp'd)
.truct
FD .p'd,

if multica.t .dd,. ••• ts i!" "AT *1

st,-uct
'ar (p •• t • , •• teOl. p •• t <- .... tCMULTl-"DDR_CNT - III
if « pmat-).tat •• INUSE ••
(berl,C (ch.,. .> 'pfd-:>d •• t_add'l"COJ'• • p.at->.ddrCOJ,

pm.~++)

ADD_LEN)

_iii:

0»

bre.k,
If Cp ..et > "1I.UI!UL.TlJlDDR_CNT ,..turnCFALSE),

III

,..turnCTRUE),

Sel f _T •• t - PASSED,
Diilgno •• C).
If _c t_cnt - EDFBIT I L.PBKJRAIIE_SIZE.
bcoP\! «chA" .> ptbd->bu'f JtT' • • lpbk_',. .... [O],

.... hil.' !S.ndJ"••• Cptbd,

stT'uct

*ifd." DEBUQ
i f «pcb -

LP8K_FRAt1E_SIZE) •

•• ho •• i[Ol»;

.pcbJ
g.t_CbO)

pNUL.L.)

F .. t.l("dld - D1.gno •• - couldn't get .. CB\""'>;

•• nd1, 1* DEBUQ *1

fle.s. d 1•• _dane • 0,
S .. lf _T •• t • FALSE,
pcb-)oemd • DIAgNOSE I ELBITJ

Issu._CU_C.d (pcb) J
",hil. (-n_gl. d1.I_done · · 0 )

1* ",.it for 01 •• c",d to finish .*1

231421-35

1-378

AP-235

IPCO/U9ll/CHUCK/CBRC/DLD. C

.ifd., DEBUO
i f ((pcb -

g.'_Cb 0) -- pNULL)

Fat.IC-dld - Can.t.u .... - couldn't •• t • C8\n")J
•• J ••
pcb. eat_Clte)J

•• ndlf 1* DEIUQ *1

PCb->P81".1 - o.OSOC,
pcb->p.T'~ • 0.2600 I 100p'1."
pcb->pa".:J • 0.60001
,cb->pe,," - OIFaooJ

,cb->p.".' •

OXooool

if (1oopfl ... -- NO.J..OOPIACK)
pcb->paT'ah • 0_0040,

.1 ••
/* loo,.aell fir ••• t. 1 ••• but •• than

pcll->p .....6 - 0.0006.

the _tni.ua ,,, ••• l.nlth *1
- COfFIQURE

ELI IT.

/* Send a ."••• to th. cabl., p ••• ,. point." to the d •• tin.tton add,. •••
and. pointe ... to the fh·.t t",.n •• it' buff .......,r.,to1".
SendJ1" ••• Cptbd.

.'ruc'
ch.,.

pad')

TID

'* ,..tuT'na

f.1 ••

*p'bd.

it can't get. Co. . .nd blocl! */

.padd.

(

.pclu

lenlt'"

if ((pcb - g.'_CbO) pNULL) (
'1 •••. " ••• t_. . . . . OJ

(.1 •••. " ••• tJend R ••• t_~()1

,...turnCFALBE),

231421-36

1-379

AP-235

IPCO/UBR/CHUCK/CBRC/DLD. C

/ • • ave cI •• tin.tiDn .dd,. ••• to co_and blocll ./
bcopUe (ch.,. .).pcll-:>p ....II2,

(ch.,. .)p.dd, ADDJ.EN) ,

/. calculat. the 1.nlth .1.1d ltV lu_in. up all the buf'.". *1.
fo,. l1.nl'h - 0, ptU-:>lln. !- NULL, ptbd .. luildJ't,.Cptbd-:>llnU)
11n,th . . p.b"->act_cnt,

l.nlth +- CpUd-:>.c'_cn' .. OI3FFF),

1* .dd the 1 •• ,

bu'"'' .,

chIck to ••• If ,.4111nl il .... Ilu:l ...... , do nat do paddina. on lao,lI.cll

I . thio .,U not ...,..", "IN-P/OTAJ.EN :> TlUF_8IZE . ,

< "IN-P/OTAJ.EN).... I • . . .u. . . . 4 bUh CRC . ,
Cbc.pChho•• H01. Cch.,. .)p.dd. ADDJ.EN) !- 0»

i f Cl1enlth

pUd-:>.ct_cnt - "INJ)ATAJ.EN I EOFIIT,
pcb-:>' .... 5 .. l.nlth,

I. l.nlth 'hld . ,

h.u._CU_C.dC,cb),

.1 •••. ,. ••• t_. . . . .

II Cfl •••. ,. •• etJ.nd

. R••• t_5860,
,..tul'nCTAUE) I
)

AddJlultic •• t_Ad.,. ••• Cp . . )
ch.,.
*p •• '

Itruet

'* th.n
l' thl .ultic ••
.,..tuI"n *'

/. Plll8 - palnt.,. to ..ultic •• ' .dd,. •••
/. ,..tu,.n!n, •• 1•••••n. the "ultic •• t .• dd" •••
t.U. is .ull .,

., •• t,

t, .d' ...... :II •

duplicate of ane 81" •• IIU in thl tMT.

p . . t <- .... UItULTI....ADDR_CNT - I I' p. . t •• )
C p_at-:>.,.t - INUBE .....
Cbe.pC .. , . .t-:>.dd,,[OI. Cch.,..) p... ADDJ.EN) -- 0» (

for Cp.at - . . "

retu1"nCTRUE),

'0"

<- .... ttIlULTJ....ADDR_CNT - 11. p. . '++)
FREE) (.
p. . t-:>.tat - INUBE,
bco,,( "p. .t-:>.dd,.[Ol. Cch.,..) , ... ADDJ.EN) ,

Cp ... ' - . . t, p. . t

i f Cp . . t-:>.t.t -

...... ,

231421-37

1-380

inter

Ap·235

IPCO/USR/CHUCIVCSRC/DLD. C

:> ••• ttl'tUt..TI_ADDR_CNT flag5. r.s.t_..... - 0,
if (flags. r ••• tJ.nd •• 1)
R••• t_~e6( )1
,..turri(FALSE)J

(pmat

lJ) "

S.t_Multic •• t_Addr ••• ' );
flag •. r ••• t_•••• - 0,
if (fllag •. T' • • • tJl.nd _. 1)
R ••• t_:tBbC ) J

T'.turnCTRUE),

D.I.t._"ultica.t_Addr ••• Cp •• )

1* r.tuT"ning f.l •• ",.an. the lIultic •• t add" •••
..... not found' *1

u t , p •• t <- ••• tCI"tUlTI_ADDR_CNT - III p •• t++)
if ( pmat->.t.t .- INUSE ••
(be.pC .p •• t->add,,[Ol, (ch.,. *) p.", ADD_L.EN) -- 0»
p.at->.t.t • FREEl

for (put -

br.ak;
i f (p ... t

:> .... UIIULT1_"'DDR_CNT - 1])

flag •. r ••• t_•••• - 01
if (fhll •. r ••• tJ.nd •• 1)
R ••• t_'B6~) I

r.turnCFALSE),
S.t_r1ultic •• t_Addr ••• Ch
flag •. r ••• t_••••• OJ
1f (flag •. r ••• tJ.nd . - :1)
R ••• t_~~6( ),

".tuT'nCTRUE),

S.t_"ultic •• t_Add,. ••• <)

.t,.uct
.t,.uct
u_.hoT't

"AT
"A_CB

.p . . tJ
*p •• _c b J

i • 01
pm._cb • ac.... _cb'
while Cp •• _cb-:>c.d !- 0)
p •• _cb-:>lln • • NULL,

1* if the "A_CB i. inu •• , ... it until i t ' . f .....

*'
231421-38

1-381

AP-235

IPCO/USR/CHUCIVCSRC/DYI. C

<- ... 'UIULTJ_ADDR_CNT - ill , •• t++)
•• INURE) (
bcapU ( .p••_cb->toc_.ddl'C n. .p •• t-:>.ddl'COl. ADD_LEN).

. fo,. Cput· ••• t, put
if C· p •• t->.tat

:l +- ADD-.LEN'

pM_cb-).c_cnt • i,
p... _cb-:>c.d - ItCJlETI.'P I ELBITI

)

PutJ1' ••..RFACpfd)

'* R.tu
... " For••• D.,cl"ipto1' and Receiv. Bu'f.,.
D•• c1'ipta .... to tb. F,. •• Receive F...... ",. • • • /

FD
.truet

'*'*
!".tu,." ••.
*'
'* indic.t....heth.,. to ....,te...t RU ./

....'

RBD

.p,.. .... ,

1"U_It.,.'_.l •• _fd.
1'U_It.,.t_.I.,_,obd,

point. to "eginning of
RID li.t
paint. to end of 1'etul'ned RBD U.lt ./

'1 .......... t_. . . . . I,
ru_.'
.... '_.l ••_fd • 1'U_It.,.'_'I.g_... b• • FALSE,
p'd-:>.I_o - ELIIT.
pfd->.t.t - OJ

p1'bd - (ot1'uct RID fI) .uild....Pt1'lpfd-:>1'bd..:. . . . . tI./. pi . . up t.h. link to the 1'bd . ,
pfd-:>lInk - p'd-:>l'bd_." . . t - NULL.

'n.

/. Di .... 1._586_Jnt 0 , thli co.and i . only n.e •••• "u in .. multit •••
P1'ol"' ••. Ho... v.,.
til' • • inl1. :t.....nvh"on ••nt th~ .... outin. i. 0 ... 1gin.ll,..
c.ll.d ,,.011 1.,._586(), tll.r.'o,..
upt • •,.• • 1,. •• dU d1 •• lIl.d

,,,t.,.. .

(b.gln_.d -- pNULL)
"eg1n_.d • • nll_'d • p.d,

el ••

.nd_fd-:>lInk - O. . . . tepfdll

.nll_.d-:>el_• • O.
end_'• • ,.d •
... u_.t.,.t_.l •• _.d • TRUE.
)

1. tb.,.. i . a ,.bd .tt.ch.d to til • • d then
find the ".ginninl and end of the ... bd 1S,.t

••1' (II • p1'bd. 1I-:>lInk !- NULL. II • BulJd....pt1'lq-:>lInkl)
,-:>.ct_cn~

• 0,

'* no. prbel paint. to the0' .... lnn1n. D' the ,.bd
,

II point. to the end

li.t .nd

the 1i.t *1

11-:>01 . . - R.UFJlIZE I ELBITI

,->.ct_cnt • 01

231421-39

1-382

intJ

Ap·235

IPCO/USR/CHUCK/CSRC/DLO. C

/* if th.",. i . nothing on the list
cr •• t . . . n .... 1 tat

begin_",bd - prbdl
.nd_"bd • '1.1
if (prbd !- q)

ru_start_'la'_T'bd - TRUE;

1* if there i . mar. than on. rbd

",eturned .tart the RU

end_rbd-:>link •

1* if the rbd list alreild" •• ist. add
the n •• ",eturned l'b d. *1
O'f •• tCprbd)1

end_rbd-:>sile • R8UF _SIZE,
end_Tbd • It;

ru_stilT't_fla,_rbd • TRUE;
}

if (ru_start_'la,_fd ••. Tu_st.,.t_'hll_",bd)
Ru_Start C) J

En.bl._~8o_lnt(

flag •. "' ••• t_...... OJ
if ('lags ....... tJ.nd -

if Di •• bl._~B6_Int()

is used .bov. *1

R••• t_5ShC );

Ru_Still't< )
if «"cb. stat., RU_I'1ASlU . - RU.-READY)

'* then r.tUT" *'

if the RU is alT- •• d"

'r.ad,,·

if «begin_fd->stat II eBIT) •• CIIT)

return;
begin_'d-:>l'bd_off •• t - O'f •• tCb."in_"bd);

1* link the bl'ginning of the l"bd
list to the fil"st fd *1

scb.l"f._offsl't • Off •• t(begin_fd)J
W.it_SebC )J
seb. emd 1111 RU_STARTi
CAj

Soft"'.l'e_Reset ()
{

web. emd -

RESETJ

CA,
W.it_ScbC ),

I.sue_Res.t_ClftdsC)
{

Wait_Seb(
seb. emd -

CU_STARTI

CA,

231421-40

1-383

AP-235

IPCO/!lll"/CHUCK/CBRC/DLD. C
llaUJlebCI,
DUtIlllCOIFF5E, 0) J

out.. CTIt1ER1_CNT, 0),
.u'.COIFF,... 01COO91,
..UIe. CUn.. COIFF,..1 • 0100201 -- 01
i f CCseb .• , . , • CHAI -

b,. ••• ,

'* t ••••
".1',
if

Cn' bU is . . , b ...... CHA
586 C.cI d •• dlocke. *1

CHAI

C.eb .• , . , • CNA !- CHA)
Fetal (-DLD: I •• u.JI •••• _C __d. - Co_and d.adlock du,.in. r ••• t p,.ocedu1"'e\,,"),

R, •• '_Ti •• autC

1* Acll"olllllle ••• , CNA inte-r"upt . /

leb. c.d • CHAI
CA,
"'U_BebCII

, . E •• cut • • ,. ••• t, Con.i.v .... , S.tAdd,. •••• and "CJi.tup, "hen
. R.coOv. UnU and 'ha C._.nd Unit . ,
R. . . '_IIB!>C)

'r • • ta .... t

the

(

I'IIIT
I,

••,.••·.,_,l'It.

Dhabl._!IB6_lntc I,
EBI.J.OOPBACK,

So,t••,,·._R ••• t () J
Icb .• tat • OJ

'0,. ( t - 0, :l <- O.FFOO. :1.++)
if (Ieb •• tat •• (ex I CNA) J
br.~.,

CI >OIFFOO)

Fatal (-DLD: int" - Did not •• t an interrupt after'So.t ... ,.. R••• t\n"),

'* ttt. ,. •••
Wal'_BebCl,
Aclt

Jntel'rupt . ,

.eb. e.d - CCX I CHAII
CA,
llaitJlebCl,
Ilfd.. DElUO
I. C h.in_ebl -- pNULL)
FatalC-DLD: b •• in_ebl - NULL on R. . . t_IIB!>"),
I.ndif I. DEBUO . ,

231421-41

1·384

inter

AP-235

IPCO/UBR/CHUCK/CBRC/DLD. C

1* Configurl thl 586 *1
1* £thl,.nlt def.ult

p.,. ••• t."'.J

d.fault p."a.lt.".

r.,_cb. p.,..l •

Configu,.. il nat nlc •• ".T\I

wh~n

using

o.osoe,

".,_cb. pI",M2 • 012600.
r.,_cb. p,,,-.3 III OlbOOOJ

"I,_cb.

p.,,"

T".,_cb. pI"'.&

r.,_cII.

p.,. ..6

.... ,_cb. Clld

III

O.F200J

III

0.0000,

• 0.0040,
III CONFIQURE I ELIITI

leb. cbl_o" •• t • Off •• tCIe".,_cb. ,tat),

beapv( (cha,.

,.,,_cb. cmd -

I,,·.,_cll. parlftl, .1IIIha •• itOl~ ADD-.LEN),

1* tlDV. the prOIR
edd,.. ••• to I" (lid

IA I ELBJT,

i • rl'.JIIA_cb .• t.t III 0,
""_IRI_cb. 1inll. - NULL,

'a,. (pmat

III

" ••

ttOl, p •• t (- ••• teJ1ULTI-"ODR_CNT - 111 ,,,,.t++)

if ( P.... t->.t.t •• JNUSE ) (
bcap"C &c,. •• __ ._cb.llc_.d~T'[il,
I +- ADDJ.ENI

""_Inl_cb. fIIe_ent

III

.plII.t->addt:'CO],

~DD_LEN)J

1""-"I_cll. uld III I'IC_SETUP J ELBITJ
leb. cbl_of, •• t - O'f ••
_cb .• t .. tlj

"a." •• _",..

X...... _R.5.t_C.d.( );
1* R •• t .. ,., the Ca . . . nd Unit .. nd the R.ceive Uni,t *1

fl_, •. " ••• 10_. . . . . . OJ
fl .. g •. " ••• tJend • 0;

Recv_lnt-P"Dce •• ing () i
scb. c"l_offs.t - begin_cblJ
Walt_ScbOI

231421-42

1·385

AP·235

'''CD/UIIII'CHUCK'CIIIC/IIUI. C

we •. c., •

CU~NlT'

a.,_n •• Dutll,

, ••• ,

D•• '_n

CA,
EneU. ___lnt II ,

n ••,.

n - .,to CD" ,..utin• •,
Itco",(d •••• pc ... ltV •• ')
ch.,.
~II."

'0 ' . .

it.,

(

"IItV'."

_,,.I:J

.,t.

10 be., -c • .,.,.. 0'
Ite., ( •• ' 12,· nltvt •• )
e ... ,.
•• 1• • •a.

int

nbvt •• ,

(

.... 1. (nltv' •• - ........ 1•• 'I".tu .."te--Il - _ ....2)'

-,2++),

)

-1·386

inter

AP-235

IPCD/USR/CHUCK/CSRC/LLC. C

**.·.···****·········.·····························.......................,.

•..1••

IEEE 802.;: L.ogical L.ink Cantoro! La"e...
(St.tion Component)

*.'

••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• ** •• *** •••

**.,..

4Unclude "dId. htl

eltern

chaT

*pNULLJ

exte,."
ext.","

.tl'uct
char

TBD *get_TbdC)1

,. •• don1u char

DSAP, SSAP,

*SuildJlt1"C),;
lid_.,. ••• tXID.,:LENQTHl. ( 0. O.
XID, lid c1 ••• 1 ,. •• pon •• *1

XID.

O.el.

OxOL 0);

struct LAY lattDSAP _CNTl,

.tTuct

.plat;

LAY

fol' (plat • • 1attOll

plat

.1.tCDSAP _CNT -

ll;

pl.t++)

pl.t->stat • FREE.
T.turn( Init_:tB6(»1

'* Function

fOT

adding,. n ... DSAP

Add.j) •• p.-Addr ••• Cd •• p,

p'unc) / . DSAP .ust b. divisible b~ 2 •• CS-N), IIIhe ... e
:Z*.N. nSAP_CNT. (i.e. N.LSBs must be 0).
The function lIIill ... etu ... n FALSE if, doe. nat

meet the Above ... equi ... 8I1lent •• a ... the .Lsap
Add ... e •• TAble i . full, a ... the add ...... has
.1 ... e.d .. been u.ed. NULL DSAP add ..... s is
,.e.e",ved 'or the Station Component *1
int d •• p.

(*pfunc)

()J

{

.truet

LAT

« (8-DSAP SHIFT) Ie OxOOFF)
... eturn (FALSE),

if (U •• p

!- 0

d •• p -- 0)

1* Check fa ... duplic.te d •• ps. *1
i f ( (plat - 1<1atU ... p » OSAP_SHIFTlI->.t.t == FREEl {
pl.t->.t.t • IHOSEI
pl.t->p_•• p_'unc • p'unci
"'8tu ... n (TRUE);
el ••

... etu ...nCFALSE)J
1* Function fo ... deleting DSAP. *1
DeleteJ) •• p_Add ...... Cd •• p) 1* If the .pecified connection exi.t •• it is .eve ... ed.
If .the connection doe. not exist, the command is igno ... ed. *1

231421-44

1-387

inter

AP-235

IPCQ/USR/CHUCK/CSRC/LLC. C
int d•• pl
{

R.cv_Fl"·••• Cpfd)
ItT"Uct FD

ItNJct
.truct
ItT'Uct

*p.dJ

FR~_STRUCT

.prb.d;
.pf.,

LAT

.plet'

RID

pt'bd •

C.t1'uct RID .) luildJii.,.(pfd->rbd_o'f •• t ) ;

pfl • • 'Itl"Uct FRAfIIE_STRUCT . ) prbd-:>bu'f-ptl"

if (pfd->~bd_Dff ••.t

!- NUL.L) ( 1* The.,.e h •• to be e' "bd iltt.,hed
to the 'd. or else the fT·.me is
toe Ibot't. *1
if (p'.->d •• p .- 0) (
1* if the 'ram. i , ,.dd,. ..... d to the Station
Component, then,. ".'pon,. meu b. required *1
if ( ! (p'.-> •••,p • C.ft_SIT)

'''.''1'

) (/* if the
received is a r.spon •• ,
inat ••.d of ,. commend. then reJect it.

aecau •• this software do •• not implement
DUPL.ICATE_ADDRESS_CHECK.

no ..... sponse

fra". •• should b. rl'cv'd *1

Sta.tion_C.",po.nent_Re.pcu:r•• C.pfd) j

,*'*
.Is.

not .ddTI"' •.d to Station CDmpDn.nt~
check to ••• if th. da.p .ddr •••• d is .t;:ttve

i f CCph-)d •• p
CII~DBN'_SHIFn .. O.OOFF>
0 U
(pl.t - .l.t[(pf.-)d •• p)
DSAP_SHIFTl)->stat -- INUSE ) {
(*plet->p~.ep_ftunc )(..,ftf),
,_ cell the 4Iunction ••• ociillted
.
u.ith the d •• p T'ec:eived *1

Put_Free.-RFA(p4ldh 1* return the p:4Id if not given to the us.,.. "ap"

.tT'uct

.pH •

• truct FRAME_STRUCT

*pT'f.~

.pt, .. ,

.tl'uct TID

*ptbd,
*prbd,

*b.g~n-ptbd,

sf;T'uct RBD
pl'bd •

p1'f.

•

*q,'

(.tl'uct RBD .) B.uil.dJt,..Cpfd->T'ltd_off •• tb
C.tl'uct FRItI'IE_STRUCT *) prbd->buff JltrJ

... itch· Cprh-)clOd .. ""'..1'..,IT..>
{

ce..

XID:

231421-45

1-388

inter

AP-235

IPCO/USR/CHUCK/CSRC/LLC. C

wh H. « ptcbd • O.t_Tb d (»
. - pNULL) J
ptbd->act_cnt • EOFBIT I XID_LENCTHi
beo, ... «ch." *) ptbd-:>buff,Jtr. aclid_',..,meCOJ.
ptl • • (.truct FRAI'£_STRUCT .> ptbd-:>buff Jltri
ptfs->cmd • pT'a->cllldi

XIDJ.ENOTH)J

pt'a-:>d •• p • pr'.-:> .... p I C_R_BITi 1* ,.eturn the 'Ta",.
t~ thr umdl'r *1
ptfa-> ••• p -

whil.C !S.nd_F,..m.(ptbd. Build_Ptr(pfd-:>src .. addr»)1

c....

b,. •• kJ
TEST:

'or (prbd -

(atruct RHO
Il -

tIIhil. rbd_ofk.t),
pNULL. prbd !- pNULL.
prbd • Build_Ptl'Cprbd->link»

b.ginJtbd -

O.t_Tbd(»

•• pNULL)J

If (q !- pNULL)
q->link • O" •• t(ptbd);
.1 ••
b.ginJtbd :a ptbdi

ptbd->act_cnt - prbd->.ct_cnt;
bcopy«ch.,.
'l

ptbd->buff..,ptr.

(choir

prbd->buff-ptr.
ptbd-:>act_cnt ~ Oll3FFFL

ptbdi

ptf5 - Cstruct FRAHE_STRUCT
ptfs-:>clllld - p",'s->cllld.

begin-ptbd->buff .. ptr;

ptf.->d •• p • prfs-> ••• p I C_R_BITi
ptf,,->ss.p

101

1* ,.eturn th~ frame to
the sender *1

whileC !Sendjr.meCbegin..,ptbd, Build_PtrCpfd-:>.rc_addr»),
br •• ki

231421-46

1·389

inter

AP-235

IPCO/USR/CHUCK/CSRC/UAP. C

1*******.**.**•••• *** ••••••••••••••••••••••••••••••• ** ••• *••• ** ••• ***********
*
Us I" Applic .. tion Progr.m

*
ASlJnc to IEEE B02. 2/802.:3 Protocol ConverteT'
*••*.***••*.*.*.*.*••*••***•••****••~.** •••••**.* ••**.********.*.****.********1
.include "did. hOI
1* ASCII Ch • .,..c:te"s *1
.d.fine ESC
OxlB
_define LF
OIOA
.dlfin. CR
0.00
.d.fine 88
0.08
.. d.Fine BEL
0.07
.de'ine BP
0)120
.define DEL
Ox7F

0.03

.de#in, CTL_C

1* ~rdw.T"
.define CH_B_CTL

O.OODE
O.OODC

_doftno CH_A_CTL
.define CH_B_DAT

OxOODA
_dofino CH_A_DAT
0.0008
.d.fine UART_STAT_MSK
0170

1* Intll'T'upt ca ••• for B274 , *1
0

.dofino UART_TX_B.
_do'ino UART _RECV_B
_doflno UART_RECV_ERR_B
_dofino EXT_STAT _I NT_8
.d.fine
char
cha,..
cha"

0.08

O.oe
0.04
EXT_STAT_INT_A Ox14

fifo_t[2~6ll

'ifo_,,[256J;

ld'rantJ. wrb[5l;
unsigned
char
1 n_fi fo_t. Dut_f i fo_t.
u_short
t_bul _stat. T _buf _stat;
CbuH80],
1 In.CB1],

out_, 1 fo_r. ac tual,

1* Com...nd line buffeT *1
1* Monitor "'ode displa\l lin. *1

unsigned
cha"
d~ap,
.sap.
cha.,.
D.st_AddrCADD_LEN1,
chilr.

in_'i fO_".

send_flag,

local_echo,

l'tultl_AddT'CADD_LENli

int tmstat. 1* terminal mode .t.tus: for l •• ving t.rminal mode *1
int dhex, monitoT_flag, hs_"t.t;
1* flags *1
•• t.rn
•• t.rn

.true t TBD
cha-r

•• tern

.true t FLAQS

•• t.T'n
•• tern

char
char

*t;.t_Tbd();
*Suild_Ptr(),
flags;

xid_fra •• C].
whoami[l,

231421-47

1-390

AP-235

IPCO/USR/CHUCK/CSRC/UAP. C

e.tern

struct
struct

8.t.1"n
e.t.,.n

ch.,.

e.t.,."

_Ul.
IlAT
leUl.
WIT
*pNULL.,

unsigned long
u_Ihort
u_'hol't
unsigned long

e.t."n

eat."n
•• t.l'"
•• teTn

U_,hOTt

•• t .... n

gODd_lllit_ent;

unde"TU"_cntl
no_c,.,_cntJ
d.f.T_en'l,

_", __."'1' _en'll

.a._cal_entl
1".Cy_," .... _cnti

e.t."n
•• tern

u_Iho1't
unsigned long
u_Iho,.t

".'."_I:ntl

e.t.,.n

.true t

Icb,

SCB

1* MecT'a 't\lp.' of definitions *1
.deflu
.deflne
.define
.deflne
.define
.deflne
.dofino
.deflno
.defl ne
.doflne
IIdefino
IIdofino

RTB_DNB Dutb ICHJI_CTL.. OIOll). DutbICH_B_CTL. ...rbUl-..rb[SlIOI02)
RTB_DFFB DutbICHJI_CTL.. OIOS). DutbICHJI_CTL.. wrb[Sl"'rb[SlI 0) (
--il
CoCBS), coeSP), CoCBS)J

"Ie

198);

) (

}

else
if

>,. SP)
CoCe ).
bufti++] ..

else
if «c

CR)

(c -- LF»

(

buf![i++] • CAl
buftj++J s LFI

else CaeBEL),
}

Co'CR); Co(L.Fb
if

cnt)

*pillet :: ent.

el ••
'01'

*pact • f.
(i ,. 0; i < *pact ;
*PIUI++ .. buf[ilJ

i++)

231421-49

1-392

AP-235

IPCOIUBR/CHUCK/CBRC/UAP. C

R.ad (I,cbufCOJ. eo. &t.ctual)1
i - SlIlp(llcbuf[O]),
return( cbuf[ i],.
Wrtte(p .. sg)

char

"p •• gJ

IIIhil.

(*pm.g !- '\0') (

-= '\"')

if (*PMSII
Co(CRlJ

Co(*p",.g++);

F.talCpmlg)

'* . .rit . . . . . . . . .g. to the

Icr •• n then ,top *1

.pM.g.

chtn'

Wl'"ite("Fat.l:
W,.iteCp.IISg).
'or(!

.. );

Bug (pmsg)

chil,.

'* ",rit. . . m••••

g. to the Ic,. •• n then continue

.p.l5gl

Writ.("Bug:
Write

.1,.

a..

1 ••• than

6~~3b.

\n"),

M),

Write(" 111 ••• 1 Ch ...... ct.,.\" Ent.,. a

nu,.~.,.

__>II)J

1f (h •• )
l'eturnCwh )J

".tu"nC ... d);

Jnt_To_Alel!(v.lu . . . . . . . ~ 111. chi width) /. con".,.t an 1"t ••• ,. to an ASCII string
unltgne" IDn.
"a1u.,

u_'hor'
b ....... idth;
char
cht]. 111,

for U • OJ i < width,
J • value X b ••• ,

i++)

I:h[i]· J + 0_30,
J + 0.37 •

10)

.1 ... cheil •
. . . a1u. a valu. / " ••• ,

( i - width - 1, chCil •• '0' &c •
chtil • ld.!
cht.idth] - '\0',

for

Wrtte_Lonl_lntCdw.

u_'hort
eh.,.
"

> 0,

i--)

unsigned Ion.

u_,hort

IIwl

chC1111

(dhe.)

_I,. Int_To_Alel1(d'I"

16.

In'_To_l.lc 11< dill. 10. I
faT' (J • O. ch(Jl !- '\0',

'ch(O]. 8)1

.ch[Ol,

i--, J++)

10»)

lin.Cl.l • chCJ1,
Writ._Sho.,.t_lnthh
u_ahort w, i i
u_ahort JJ
char
ch[bl,
una iln.d lone

dWj

d. . . WI
if ~

2.cnt - II

br •• _'

fot'

•

cnt - 1J 1++)

ad.[lcnt - II - I] • cb,Ht2*1] « 4

tbuf[;Z*i + I],

IWrit_.-Alld"Cp.dd. tnt)
ch.,.
p.ddt]. entJ
i.

for (

cnt >0

ct3li

cnt ... -) <,

231421-53

1·396

inter

Ap·235

IPCD/UBR/CHUCK/CSRC/UAP. C
i - paddtcnt-llJ
Char_To_AsciiT'bd_off •• t),
prl • • (struet FRNE_STRUCT .) BUild_Ptl" (prbd->buFfJtr);

swi tch (pr'I->cMd " ""P J' _BIT)
ca..
UJ:

if (a'Gnital" _'la,)
breakl
Don't put data in fifo unless in t.",minal mod. *1
prbuf • Ccha,. .) pl.... ,
p,.bu' ._ 31
skip Dve" the h •• de,. in'o and point tD the d~t~ *1
cnt • 3,
pfd->length -- 3;
for (, prbd !- pNULLI cnt • O. pT'bu' - (ch • .,. .) prbd->buf''--ptr){

fa,.

(

cnt

<: (prbd->act_cnt

Ie OJ03FFF) II&!: pfd->l.ngth

ent++.
aihile(1"_bu'_wt .. t _. FULL).
F:I. fo_A_In (*prbuf)J

p.,.bu'++,

:> 0;

p'd->length--) {

prbd - Build_Pt.,.Cprbd-jlink),

*ifdof DEBUg

(pfd->length
0 •• pT"bd !- pNULL.)
F.t.U"U .. p: Aecv_O.t._1(p'd) M)J

•• ndi' 1* DEBUG *1
}

c...

bT" ... ks

XID:

.. hill' «ptbd • Oet_Tbd(»
pNULL),
ptbd->.ct_cnt • EOFBIT I XID_LENOTHI
bcopV «(ch.r .) ptbd->bU"Jtr, Iclid_'r.me[Ol,
pt, • • (.truct FRAt1E_STRUCT .) ptbd->buff...ptri
pt'.->cmd - pT'fI.-:>c:lftdJ
ptfs->d •• p ... pr'.->.slIp I C_R_BITs
ptls->aw.p • W'Iilp'
whil.C !S.ndjrilm.Cptbd.

XID_LENOTH)j

1* return ~h .. fr.me
to theo sender *1

Build_PtrCpfd->src_addr»),

231421-54

1-397

AP-235

IPCO/USR/CHUCK/CSRC/UA!'. C

for Cp,." • • C,''''uet RID .) 8uild-PtTCpfd-:>rbd_off"et),
q &II Itegin-ptbd • ,NULL, p1"bd !- ,NULLi
p,.bd - Bvild_Pt"Cprbd-)link») (
.hil. «,tbd • a.t_TbdO) •• ,NULL),
i f (q !- pNULLI
.q->link - O" . . tlptbd I,

e1s.
begln..JItbd - ptbd.

ptbd->act_cnt • p,..bd->act_cnt.
bcapilC (ch.,. *J ,ptbd->bu'" -,tTl

(char .) p,..bd->bu"

_,t,.,

ptbd->.. CMd - p",'.-:>clld,

.,t,.->•••p .. p,,'s-) ••• p

hgln..JItbd->bu"..JIt~)

I C-.RJUTJ

pt,s-> ••• p - ••• p,

,* "etv"" the *''r••• to
the •• nd.,.

",hi1e( !Sendjl"••• Cbegin-ptbd, Build_Ptr(pfd->.,..c_addr»)J

",..alu
)

PutJr.e_RFACp'd'J

Fifo_T_DutC)
(

r.tv,."

the fr .... ·.,

calle. b ...... 1n program *1

~ • fifD_ttout_fiflo_t++ll

Di •• ble_Uart_lntC) I
if (out_Ufo_t •• In_'I'o_')
1* if the fifo il .mpt" *1
t_buf_st.t • EIfl'TVI 1* .top filling 1,..." •• lt Buff • .,. Desc,.iptors *1
II..
1* tf the fifo w•• 'ull, and is now draininl *1
i' Ct_bu'_stat •• FULL ... out_t"ifo_' - 80 - in_fi'o_t) 1* turn an
thl spigat *1
RTS_DNa.
t_bu. _.tat • INUSE;
Enabll_Ua,.t_lntC );
,.ltu,.nCc)J
1* call.d b\l v.rt r.c.tvI intl","upt *1

Fifo_T_lnCc)

char

fi'D_t[ In_'110_t++1 =

if (t_buf _stat •• EMPTY)

231421-55

1-398

AP-235

IPCO/USR/CHUCIVCSRC/UAP. C

t_bU._st.t • lNUSE,
.tart '11ling Tl"ans .. it 8uff.T D•• criptor *1
if there .1"1 anI" 20 loca'tiona
tUrn of' the .pilot
if (t_bu'_stat _. JNUSE •• in_fifo_t + 20 .- out_'1'o_t) (
RTS_OFFaI

,I..

l,'t.

t_buf _stat • FULL,

Fifo_R_Out()

char

called b", tT." •• i t interrupt

if (out_'l'o_" _. 1n_'1fo_,,)

r _buf _stat • E""TVi
,I..

if the ':Lfo t • • •,tv *1

1* if the 'i'o ••• full and :La now dralnlng . /

if (",_bu"_stat -

FULL •• out_'I'o_1" - 91 -- 1"_'1'0_1")
r _bu' _stat • lNUBE.

r.turn(e);

FifD_R_InCc)
ChIT

1* called blal Racy_Data_l0 */
CI

fi'o_",[in_,t'D_"++] -

Di •• b 1 ,_U.,..t..:..lnt ( ),
if C,. _bu'_stat - a.TY)
UNIT _TX_EI_8.
CoCO);
r _bu' _stat -

,I..

lNUSEI

pT'i .... the intlrl"upt

*'
*'

1* if the buffe" i . 'ull, indicat. i t
if c,'_bu,_.t.t •• lNUBE •• in_.l'o_1' out_ilifo.:.:r)
l' _bu' _.t.t

• FULL.

En.b le_U.1't_lnt C);

int
ch.1'

st.t;:
Ci

outbCCHJ_CTL. 2).

point to RR2 in 827'"

n.itchUnbCCHJI_CTL) " OWilCH

'* .....d 8274

*'
in,t.1'T"upt v.etoT" .nd •• T"vic. it

if (T"_buf_st.t •• EfiIITV)
UIIRT_TX_DIJh
RESET _ TX_INT •
• 15.

outb CCHJ_DAT, Fi'D_R_OutC»,
b" .... ;:

231421-56

1-399

AP-235

II'CO/UIlA/CHUCIVCIlAC/UAP. C
. . . . UMTJlECy.......RJI:
ouUICHJI_CTL. II. /. pain' to RRI In 8274 . ,
.,., - InUCHJI_CTLI.
allU !CHJI_CTL. 0030"
i f 1.'0' • 000010 I
.... ,t.C .. '''P.1'lt' £" ... 0,. D.'lc'.4I\n")j
If
010020
if

I.,.,
• I
.""t.,,,,nOv.,.,..,,,
I.,.,
•

E,.,.o1" oe.t.cted\n"),

...

0100401
Writ.C·\nF.... in. £,."01' 0.'.ct.4\"II),'

.. ., ,

c ••• UMT.JIECYJI:
in~ICHJI.J)oIIT"

c -

....

If lbo_.'.' -

TRUEI (
... _st ••• Ftt.LBEa

..,.

)

If 1I0C.l_.cbol
Cofe)'
... (c • •

'* Fl•• t. ' ..... in.'. Hilh S,.~.

/* .cho the cit ....

• ,,.an •• it

beell

0"."1'''''

T,..nl.it" aoel"

t. th. ' ..... In.l' could caul.

rl int.,.. ..."pt il .n•• l.d

CTL_C)

, ••, . , - FM.SE•
• 1••

."...,

FI"'_T_lnlc"

cu. EXT_BTIIT_INTJI:
ouUICHJI_CTL. 01101 •
....... 11'

c ••• EXT_BTIIT_INT-'"
auUICH-,,_CTL. 01101.
b" •• lu
Ii.f.lilt:
)

EOI_1013OJI274.
EOI_8274,
)

••nd_'l • • • TllUE,
outbfChEA, lft)J
outitCOIEA, 0.00)1
autblOIEO. 016211

Till••,.. 1 ,n,.pru,t • •
EOI 10130 . ,

v.,.,- . in •• e ./
231421-57

1-400

Ap·235

IPCO/UBR/CHUCK/CSRC/UAP. C

L.a.'.J,.'.pC I

RecyJ)ata_l (J I

tnt:

forC, J) (
R•• d_Adtl1'C"\n\nEnt.1' thie Station'. LBAP in Ha. --> tI, •••• p. 1';
if (!AlhlJ) •• p..Ad.,. ••• C••• ,. Racy_Data_l)) (
..... ,t.C·'"\nE,. ... o1': LeAP Add", ••• lIuet b. on. o' the fo110llling: \n"',
""'taC"'"
20H, 4OH. 6OH. SOH. AOH. COH. EOH \nfl)i

L.a.dJlulUcutC I

'or (

J ;
» (
R•• d...A'."'C ·'nEnt .... the "vlttc•• t Add1' ••• in Ha. --)." ,

MlulUJoddr[Ol, /lDD_l.ENI'
i f CC"ulUJoddl'[Ol • 0.01 I -

.".,t.' . '''80... the LSI of01",. "vltic •• ' Add.,. ••• Muat:
.10. < I. C!/lddJlulUc."Joddr. . . C."ultiJoddr[Ol)) (
1' ... ,

Ita 1\"1",

Wr:l.taC"'n\nS01'T", Multic •• t Add,. ••• Tabl. ta full !\n").
b ...... J

.1 •• (,

WT'tteC"'n\nWould ,au lUI. to add anoth.1' "ulttc •• t Add.,. ••• ?")!
Writ.C" tV or H) --) ")J
i ' (!V •• C»
It" •• "

)

R•• oylt-"ulticast;C)

far C , I I <
R•• d_Add,.CII\nEnta.,. the ""ultic •• t Add,. ••• that 1jDU ...ant: to del.t. in He. __ >11,
MlulttJoddr[Ol, ADD.J,.EN),
I f (("ulUJoddr[Ol • 0,011 •• 01
.
W,.it.( •
_he LBB of the "ult1c •• t Add,. ••• IIU.t b. 1 \n".'
el •• ( If C!D.lohJlultlc. . t_/lddr . . . CMlultIJoddr[Ol) I <
..,.1t.C"\n\n90,,'I"", that "ult:il!; •• t Add" ••• da •• n~t .li.t!,\nDh
In' •• lu

'nSo,..,.., ,

el ••

W1"11;.C"'n\nWould .,ou "lill. ta d.l.te .nath." "ulticast Add" ••• ?"),
W1"1teC· CY

If C!V •• OI

tI),

b,. •• 111
)

)

231421-58

1-401

AP-235

IPCO/USR/CHUCIVCSRC/UN'. C

P"'int.J\ddr ••••• C)

.t'ruet:
int

*,st.t,
..at,

.".it.C I' \ " This Stations HOlt Addr ••• is: H) •
.... i t • ..J\dd~ l ... h ....itOl, ADDJ.EN).
""it.C"'" The Addr ••• of the .D•• 'tin.tio" Node is:
.... i h..J\dd"I.D. . t..J\dd~COl, ADD_~EN II
W"iteCU'n This St.tions LSN- Add" ••• il: II);
W... i t • .J\ddl'C •••• p, 1),
'

..,.It.("\" The Add", ••• of the D•• tination LSAP is:

II),

"),

W... tt.,..Add,.C ...... ,· Ih

.t.t • FALSE.
for (pMAt'lII ••• t[Ol,

if Ip ... t-).t.t -

p •• t

& ... tCI'1Ul.TI_ADDR_CNT -

1], p ...et++)

INUSEI (

stat. TRUE.
)

lOt."

W,.tte(tI\" The '01101111nl ~ultic •• t Add.,. ••••••,.. enaltled: ");
,.~ Ip •• ' _ ..... COl' p. . t c- ... tCI1ULTI_ADDR_CNT - Il' p... t,++1
if (plII.t-:>.,., •• lNUSE) 0(
W,.ih..J\ddrl.pIN'->.dd,.COl, ADDJ.ENII
Write("
"h

.1 •.•
""it.P'\" Th." • • r. no Multica.t Add,. ••••• en.bled. \n")'
)

Ini t_D.hLlnk II
(

tnt

st.ti

if (I.ht

InltJ.lcClI -

PASSED I

Wri tee "\n\nP••••• Diegnostic S.l f T•• t.\n\n\n")J
.1 ••
ifl.t., -- FAILEDJlII\ONIISEI
writ.C"\n\nF.iled: Sel' T•• t Di.gno •• Cc.~nd\"")J
.1 ••
ill.ht -- FAIL.EDJ.P8K_INTER__ '
Write("\n\nF.iled; Int."n.1 Loopb.cll Self T.st\n");

.1 ••
i " . , . t -- FAIL.EDY8K..EXTERNl\L.I
Writ.("\n\nF.iled: .Elt .... n.1 Laopbacll S.lf T •• 1;\nM);
el ••
jflsht .- FAIL.EDJ.PBK_TRANBCEIYERI
W... itl("\n\nF.il.d: Eat .... n.1 Loopb.cll Thl'oUlh T.... n.c.iv .... S.lf Test'n");

Dutil (OlEO, 0,31);
outbCO,E2, 0,20),

I.inlhll . . 90130 pit -

ICWI . ,

I . ·ICW2 . ,

231421-59

1-402

inter

AP-235

IPCO/USR/CHUCK'CSRC/UAP. C

outb (OxE2.

.,
,.,. ICW3
ICW4 .,

Oxl0);

outb (0.E2. OxOD).
outb fOJtE2~ OJllO),
outb (OxE2. OxFF);

I · ICWb .1
",.sk all interrupts

Dutw(OIlFF20. 0.0020);

..t 80186 v.eto1' bas •

Initialil. the 60130 timers 'or T.rminal Mode

Ox34);
0.88)1
OxOS);
0.70).
1:15);
DutbCO.EA. 0.00),

..,,

Dutb(OxEE.

Dutb(OxE8.
Dutb(O.ES.
outb(OxEE.
DutbCOxEA,

I- SYSneK •• t

for 1 ",sec

I- Tim.,. 1 int."Tupts ever" . 125 sec *1

1* Initial!le the 8274 *1
outbCCHJ_CTL. 0.10>. DutbCCH_B_CTL.

O.:2B») outb(CH_B_CTL.
Dutb (CH.J\_CTL. 0.39)1
outb (CH_B_CTL, 2) i· Dutb (CH_8_CTL~, IIIrb [2] • 0.14);
outbCCH_B_CTL. 1); outbCCH_B_CTL. wrb[ll • 0.1'),
Dutb CCHJI_CTL,

5).

Dutb (CH_B_CTL.

w"bC'] •

0.30),

OlEA) I

Wri t. (lI\n\n\n\n\n\n\n\n\n\n\n\n");

W,.t t. ("

**************.*•• *.***.*****••• *.************ •• *.***.\n").

W,.it.("

IEEE 902.2/902.3 Compatibl. Dat. Link Driv.,. .\n");

* 82:586
.*•••

WT' i t. ("
****••••
WT' i t. (lI\n\n\n\n\n\n\n") J

dh.x -

*••*.*.****.**********.***.**************\n");

FALSEI

monitor_flag =- TRUE.
R •• d_Addr("\n\nEntu' the Add,. ••• of the D•• tination Nod. in Hex --> ",
&Dest_Addr[Ol, ADD_LEN);

W,.ite( "'n'nDo \Iou .. ant to Lo.d ,an", Multiell.t Addr.ss.s? (V aT' N)

--)-");

if (V •• C»
LOlld_Multic •• t( ),
Print_AddreSBes( );
Te1'minill_Mode( )
{

int
stl'uct
chtJ'"

fra.e_cnt. bu' _cnt.
TBD
*ptbd. *q. *b.ginJtbdi
.pbuf. c;

W... it.(~I\n Would \Iou lill. the 10clll echo on? (Y aT'
if(V.~()

N)--jll);

)

231421-60

1-403

intJ

AP-235

IPCO/USR/CHUCK/CSRC/UAP. C

.. I,. J Dc.l_echo

- TRUEJ

local_echo. FALSE.

Write("'" This PT'og"." will no~ enter the t.rll1ne1 mode. \"'nOl);
Writ.("," Pre ......C then CR to return back to the menu\"\"");

out:'.J"ifD_t

= in_fifo_\:

t_buf _stat • EMPTY.

• aut_'ifo_1" •

1" _bu' _.t.t

• Et'lPTY.

'l.,o_"

l1li

EOI..8013O_8274,

Enable_Uart_Jnt () J
Enable_Ti ..... _lnt«)J
Monitor _'la • • FALSE.
1;",.t.t - TRUE.
while (tlll.tat)
for ('ra ... e_cnt • OJ ,.,. .... _cnt

MAXjRAME_SIZEJ

whil. «ptbd - Q.t_TbdO) _. pNULL),

II. -

ptbd) {

1* get. Jlmit buffeT' 91'0111 the
d.ta 1 ink */

pbu" • (ch.,. .) ptbd-:>buff....,ptrJ
bu' _cnt • 0;
iF ('"a.e_cnt •• 0) (
begin-ptbd -

1* point to the buffer *1

1f this is the fi".t buffeT'1 add an IEEE 802.2
h •• d.,. infoT''''.tian *1

ptbd •

• pbu'++ • d,.p.
*pbuf++ • • • • pl
*pbuf++ - UI,
buf_cnt - 3,

a1 ••

,-)11nk. Off •• tCptbd)J 1* i' this isn't the 'irst bufler
link the pl"evioul bu"er with the n .... one *1
1* fill up • d.t. link .mit buff." ''rOflll .Iljnc tranlmit fiflo *1
for ( J bu' _cnt < T8UF _SIZE &lilt frame_cnt <: HAX_FRAME_SIZEJ
bu' _cnt++, pbuf++. frame_cnt++) {
if (frame_cnt !- 0 lele lend_flag)
b'r •• kJ
while (t_buf_lttllt
if «c • •,bul -

++buf _cnt
bre.k,

_:a

EMPTV);
1* lIIait until lifo has data *1
Fifo_T_Dut(» -- CR) "
++pbufl ++Irame_cntl

if (c == CR I: bu'_tnt < TBUF_SIZE II I.nd_flag) -( I . last buffer in list *1
ptbd->.ct_cnt - bu' _cnt I EOFBITJ
.end_fl.g - FALSE;
h· ••• ,
}

while(!Send_Fl'lIflle(beginJtbd. &:De.t_AddrCO]);

1* k.ep t'rljing until
successful *1

231421-61

1-404

AP-235

IPCO/UBR/CHUCK/CSRC/UAP. C

01 •• b 1._UaT't_Int (h
Oi •• ble_TimeT _lnt(),
monitor _fla, I:e TRUEs

*BuildJr.,..(cnt)

struct TOO
u_.hort

cntJ

buf _cnt. fr .... _cnt. ii
_fl' *b.ginJtbdl

u_short

stl'uct

.ptbd.

TOO

.pbu';

chaT'

for ( ;

; I I . ptbd) {

. ",hil. «(ptbd •

O.t_Tbd<»

-- pNULL)!

pbuf = (char .) ptbd-)buf'Jtl';

bu' _cnt - 01
if ('Ta.e_cnt _. 0)

1* get • • ,.it buff .... frolQ the
data link

point to the buffer *1

if this i . the first buffer,

add on IEEE 802 . .:i!

beginJtbtl - ptbdl
*pbuf++ • d •• pl
.pbu'++ - ••• p;

*pbuf++ := Uti
bu' _cnt - 3;

'*for

q-)link a Offset(ptbd);
if thi. i,n't the first buff ....
link the previous buff.r lIIith th. ne", one
fill up • datA link xmit buffer !&lith ASCII character. *1
'

else

buf _cnt

TBUF _SIZE &cit cnt

> 0;

*p buf
ii
i f (i ) Ol7El
i = OxlFi

l •• t buff.T' in list *1
ptbd-:>act_cnt • bu' _cnt : EOFBIT;

if (ent _1:11:: 0) -(

bre •• ;

u_short
xmi t. cnt, i;
struct TBD
*Build_Fl'affle(), *ptbd.
Writ.C" Do 'IOU I,IIAnt this st.tion to tranulit? (Y or N)
if

--> ");

(y~s(»

231421-62

1-405

AP-235

/PCO/USR/CHUCK/CSRC/UAP. C
'OT' (.",i t • FALSEJ •• 1 t FALSE, ) (
Writ.C"'" Ent .... the nUll'.,. 0' data bvt •• in the ,,.ame
cnt • Rctad_Int<);

1f (cnt

to»)

iZ04~)

Wt-tt. ("\" SarI'", the numbe,.. ha. to be 1 ••• than 2046!\n");

.1, •

.., i t . TRUE;

.1 •• xmit • FALSE)

Writee"\" Hit An .. ke, to .xit Manttol" Mod •. \n\n")1
Writ.C"

Writee"

• of Qood

Fr ••••

• Fram
0' ••

Writ.< .. r,.ans.ttted

CRC
Er'T'ors

Qood

Received

Racl!'ivIP\n")J

No
Resoul'ctt

Overr'un\n l ' ) ;

ErT'Ol'.

Errors'n");

1* "0123456799012345679901234567890123456799012345678901234567890123456789012345679
.:1 ••
• xx.
•• X • • • • I ••
.IXI
X.I.IX.I.I
• 1.1.:1 I .

1.1 • • • • •

11
«i • 01 i < 79.
l' lnl'[ t ] = 0.20,
1 i ".[79] :z CRJ
lin.[SOl !!II '\O'i

'01'

71 *1

i ++)

while «inbCCH_B_CTL.) .. 1) ""'·0) .(
'or Ci OIl 0; i < 72; i++)
line[il !!II 0.20;
W,.i tIP_Long_lntC good_.... i t_cnt, 11);

Writ __Long_lntCr.ev_fr ••e_cnt, 2');
WTit._ShDTt_tnt(~eb. ere_errs, 33),
Wri ta_ShoTt_Int (seb .• In_el'''1''w, 44)J
WTi te_Short_Int (loeb. ,"wc::_a,.r,. '7) I
Wri ta_Short_Int (.c::b. OV1" _err., 71);
Writ_ (&1 1n.[0]);
if (x.it) (
ptbd - Build_Fr.,.a(c::nt)1
wh i lee !S.ndJrA.eC ptbd, ItD.wt_AddT"[Ol») I

Hs_Xllli t_Mod. C)
(

.. t1"uc::t

TBD

*ptbd;

WriteC"'" Hit An .. 'av to exit High Sp.ed T".n •• i t "'ode. '"'n

);

h ,,_ct.t :II: -TRUE;
EOI_BOI30_B274.
EnAble_U."t_IntC );

'* Execute

this loop until. recv th.r int.r1"upt h.ppend • • t UArt *1

231421-63

1-406

inter

AP-235

IPCO/USR/CHUCK/CSRC/UAP. C
IIIhU.

(hS_Stilt)

'*
'* ••

{

\,!jIhil. «ptbd • Qet_TbdO) _. pNULL),

ptbd-".ct_cnt

Get .. I.mlt

",hile< !Send_F'ra.eCptbd. "O •• t_AddrCOJ»1

char

chtll],

unsigned

b ••••

bu,f.,.

from

the data 1 ink *1
t the End O. FT'am. bit *1

EDFBITi

dwidth.

lIIidth.

1* Send F,. .. ".

t .... p,

loni

(dhe,) (
dwidth ~ ;:),
.... idth = 41
b ••• a; 161

.1 •• .(
b ••• :. 10,
"width. 10,
wJ.dth ..;..

Wr i

t. ("\n\" Qood ,,. .....

'or (i -

tr41nrurl1 tted·
dlilidth, i++)

11 -

01) i

CoCSP)J

Int_To_AsciiCgood_lllit_cnt.
; o.

i ~ oi'-1idth Co('hLl. ... l,

Writ.("
foT' ( i -

ba.e.
i--)

Ooad 'Ta"'ls received:"

IIchtOl,

dlllidth)i

")1

1; i <- 1~ - dwidth; J.~'"
Ca(SP),
Int_To_Asc i i (T'ICV_'T .. ",,_cnt. b ••••
,ct)T'
(1 III dlllidth - 1, i )- 0; i--)
.:..; (;:~[ i l)J

WT'it.C"\n\n ":"t'C !,,,,,.o,,s "wcwived: ");
fo" ( i = i. i <= 15 - ~i~":"; i++)
CO(SP)I

c",_."".,

t.mp - .cb.
Int_To_A.ciitt.lPlp, ba!le. ' I, Icch[O]. width);
-n1' Ci-width - 11 i >- 0; i--)
.:- .:.1 f;hr i J) i
W,.ite'" Al11inment .,.,.0,.. "'.c.lved: ")1
fa" (:i. • 11 i <- 10 - ... itt .. ; i++)
CotSPl,

temp. 5cb. aln_e""s;
Int_To_Ascii(t •• p, base,

I
,
.:.c",hLOJ. width))
( i = width - ! r
'" J= 01 i--)
Co (ch r i.:';';
"'n\n Out of R.sour,. f,.ames: ");
fo,. (i • 1; i <- 12 - width; i++)
Co(BP);
tellllp - scb. ,. .. ,_.,.,. .. ,
Int_To_As, i i ( t • •p, basI!'

foT'

.. , .1.1..,

231421-64

1-407

AP·235

flDT' Ci • width CoCch£tl);

Write("
for

i :>- 0.1

i--)

Receive" overrun flr.Ift •• ·
I, i <- 12 - l.,~"t;: .. ,l"'+)

"!,.

Co(SP).
t.mt' .: !O;:;~. (lvl' _.,.".,
.a.nt_TD ___ s.C i i (t ••"
b....

'0,.

( i . . . telth

- I.

Icch [0]. width).I
i--)

i :>- 01

Co(ch£il)i

Writ.("\n'" B;!~B6 R••• t: .. ,.
foT' (i • 1; i (c 21
wad""1

i++)

CcCSP);

t_cnt'
Int_To..Alc i i (t.m,. b.... ' " .cheO], width).I
flor U • width - lJ i )0= OJ i--)
CoCch[IJ),
W,.jte(OI
Transmit. undlll'l"un .......... : "),
In'" (i :: ,; 1 ..... 11 - width; i++)
t-IlIllP

£.

•••

Co(SP),

tell, • und • .,. ... un_cntl
tnt_To_Ase t i ( t • • p. base, I
fin· ( i • width - 1, i >- 0;:

tech tOJ. ..ddt., ~;

i--'

Co(chUl)J
Wl"it.("\n\n LD~t' eRS: .);
~>4r ;i .. 1; i <.. 26 - width;

t++)

CoCSP),

te.p ,. no_nos_cntl
Int_To_Asciict •• p. b ••• ,

, " &chtOJ. width).
width - 1. i J- 1'- &-~,
Co(ch[ll),
W.,.itlf' " SOE
H);
to" <1 = 1; i <- 2:f-- -..idth .. i+"')
Co(SP);
t ••P - sq._."r _cnti
~nt_To_Asc 1 i (te .. p, b....
' '. ~ch COl, \Uidth);
for (1 = width - 1; i )= v. i--)
CoCchtil);
illfrlteC"'n\n 1'1.lIi1lUII ",.tr,,: n),
for (i .,1. i <- 21 - width. i++)
CoCSP),
t •• p ....ax_col_cntl
Int_To-""c ii Ctemp, b.ne. ' '. &ch[OJ. width);
for (i • width - Ii i >- 0, i--)
Co(chCil)1
Writ.C Ol Fr •••• th.t def.rrld: ");
for (i .. I. i <- 15 - dlltidth; i++)
for ( i •

.""0".:

Co(SP).

Int_To_Asc ii (d.feT' _cnt.
faT' (i ... dlddth - 1; i
CDC th[!J);

b.... ' '.

&ch[OJ.- dwidth) .

i--)

WT-ite ("\n\n COIII•• nd. ~T": \h\n");
Writ, C" T - Tlreihal Mode

M - Monitor Mod.'n");

1-408

231421-65

Ap·235

IPCD/USR/CHUCK/CBRC/UAP. C

T,.." ...

W,.it. C" x Write (N P W,.tte (" A Wto.ite CD S Write ('I N WT'ite (" R -

High Sp •• d
lt Made
Print All Caunters
Add ill Multil::,a.t Add" .....
Change the SSAP Addr...
.
Ch.nle D•• tination Nod. Add,.."
R.-Initiali,ze the Data L.ink

v - Change Trens.it Statistic"\"")J
C - Cl •• ,. All Caunt.,..\"")J
Z - Del.t'. ill Multica.t Add" •• s\""h
D - Change thl DSAP Add" •• 5\n"),

L - Print All Add,. ••••• 'n .. ).
B -

Change the numb.,. Billie\"");

l'1ain( )
(

tnt

Ini t_U.p ();
PrintjielpC),

far

(I)

WTit.

n ,"\"

Enter .. com.and. tliP. H

'01'

HIlp

--> ");

c
R•• d_ChaT () I
switch (Lo•• " _C •• eCc»

ca •• 'h':
Print_Help C);
b ..... k,
ca ... 'm':
Mani tar -"ode ()j
b,. •• Ic,

c8s. 't':
T."III~n.l_"odeC

br •• ki

ca •• '.':
Hs_Xmit_HodeC

bT' •• k.

'v':

CilS.

a,..

W'rite("\n Transmit Statistics
nalll ")i
if (fllags. stat_an = 1)
W,.it.C'"on. \n Would \IOU like to change it ? (Va,. N) --> ");
else

WTiteCltoff. \n Would lJou like to ch.nge it ? (V aT N)

i f (VesO) (

if (flags. stat_on

--)0

II);

1)
flags. stat_on· 0;
el •• flags. stat_an = 1;
break;
Calia 'p ':
PTint_Cnt( );
break.

cas. Ie:.':
CleaT _tntC);
break i

cas. 'il':
Load_MulticastC
ca ••

Z ':

RemoveJ1ulticast< );
CiiS.

b"e.k.
's':

231421-66

1-409

AP-235

IPCO/USR/CHUCK/CSRC/UN'. C
D.l.t.J) •• pJ'dd ...... C••• p),
L.oad_L •• p( JJ
b,. •• II,

ca •• '41 ':
R•• d-"ddT'C"\n\nEnt.,. the D•• tination Nod.'. LSAP in He.

--> -".

Ird;.p,

1);,

b'l" ••• J

c ••• 'n':

R•• d_Add ... C.'n\nEnt ..... the Addr ••• of the D•• tination Node in He. --)0
IoDnt_Addr[OJ, ADD_LEN);

ca •• '1':
P,..ln'_Add'l' ••••• ( ),
b,. ••• ,
ca •• 'T":

Saftw.,..._R ••• t,) i

InitJ)ataLinkl ).
Add.P •• p_Add,. ••• C••• p. Recv>ta_l),
b,. ••• ,

ca •• 'b ':
.... it.C·'" Tile cur,..ftt ba •• t • • "
if (dll.1 _. TRUE)
W'l"it.C"Hes. \n Would Ijou like to change it ?

el ••
if

(Y at" N)

W... tteC"Deci •• l. \n Would .. au lillie to chang. i t ? CY

Iv .. eII {
i. Cdhe.

--> ");
N)

--> ""

TRUE)
dhe • • FALSEJ

.1 •• dhe • • TRUE'

•••• ult:
.".it. C"'" UnllnDllln co_and\""),
,,. •• 11.,

231421-67

1-410

AP-235

IPCO/USR/CHUC~/CSRC/ASSV.

n ..

Ift.

stack
.tktop
.t.e If

c ••• y support

'stack'

segment .tack
label
""ard
ends

•• g",.nt II ub 1 i c

OLD_DATA

.xtrn

ASH

SEGHT_: I,IIOT'd

'DATA I
data segment addl"ess

ends

OLD_DATA

segment public
ends

UAP _DATA
UAP _DATA
OLD_CODE

extrn
ext"n

'DATA'

segment public
'CODE'
1ST _Tim'Dut_: f~,... hiT' _'586_: fa,.. 1,,.7_, far
15,.6_: fa,... 15".5_: fol,.. 1.,,1_: fa,.
ends

OLD_CODE

UAP _CODE

ext,.n
UAP _CODE

s.gment pub 1 ic
'CODE'
I .... U.rt : far, 15,.2_: fa,..
end';segment pub lie

DO_CODE

public
public

inw •

out~

Of,;.t_,
[ap + bJ
tBP + 8]

iI!i!ium.

CS: DO_CODE
DS: DLD_DATA

assume

'CODE'

• init intv • enabl_ • disable_,

begin,

equ
equ

Main_: fa,.

i;;-b_, Gutb

Build._ptr

;+
initialilation program foT' the 82586 data link driver

sti
.. x. OLD_DATA; get bas. of dgl'oup and
SEGHT _, ax
; p.!iS the ~.glR.nt value to the c program
moy
ds.
• go to the c program
call Main
hlt

,nb

proc
push
push
mov

pop
mov

far
DP

BP,
DX
OX,
AL,
OX

SP,

arg 1
OX

231421-68

1-411

Inter

AP-235

IPCO/UBR/CHUCK/CBRC/ASSY. AS"

pop
... t

inb_

.ndp

outb

proc

outb_

push
mov
push
push
mDV
mov
out
pop
pop
mov
pop
rot
endp

in..,_

proc
push'
mDV
push
mov

i"lII_

out"'_

pOp
mDV
pop
rot
endp
prDC
push
mDV

push
push
mDV
mDV
out
pop
pop
mDV
pop

,...

BP
BP.
OX
AX
OX •
AX •
OX.
AX
OX
SP.
BP

SP
• rgl
• -rg.:!
AL

'ar

BP
BP. SP
DX
OX.
AX. OX
OX
SP. BP
BP

•.,.,1

,...
DP
BP. SP
DX
AX
DX • • "0 1
AX. ·1"12
OX. AX
AX
OX
SP. BP
BP

rot
outw_

endp

BuildJtl' _
push
mDV
,mov
mDV
mDV
pop

proc

fa.

BP
BP. SP
OX. DLOJIATA
AX. AT'11
SP. BP

•• t
Duild_Ptr _

endp

Off •• t_ proc

fa.

231421-69

1-412

IPCD/UBR/CHUCK/CBRC/ABBV. ,.S"
push
lOav
may
lOaY
pap

BP
BP. ap
"X • • "IS
ap. IP

rot
DH . . t_ .ndp

..... ve_lnt_i.Y"
pUlh

PUI"
PUI"

push

PUI"

P"roc
,.X

'.1"

ax
CX
DX
51
DI

pUlh
pUlh
pUlh

.ay
.OY
May

,.X. OLD_D,.T,.
DB. ,.X
ES. ,.X

c .. 11

h1"_5116_

pap
pap
pap
pap
pop
pap
pop
pop

ES
l!5
DI
51
DX
CX

,.x

t .... ,

..... v._in'_i.'"
•• "ve_int_G74
pUlh
push
pUlh
PUI"
pUlh
lUI."

endp

proc
,.X
IX
CX
DX
51
DI

"1"

pUlh

push

• ay
• av
aov

"X • lIN' .J)IIT ,.
DB • ,.X
E5. ,.X

c~ll

1.T'_~"'_

pap
pap
pop
PDP
PDP

DB
DI
51
DX

231421-70

1·413

AP-235

IPCO/U&R/CHUCK/CSRC/ABSV. 110&11
pDp
pDp
pDp

ex
IX
AX

i,..t
•• "ve_int_B27-4

endp
p,..DC

•• "ve_int_tilllleout
push

push
push

IX
ex

·push
push
push

DX
51
DJ

push

IODV

AX.

mov

OS, AX

mav

ES.

pDp

pop

pDp
pOP
pDP
PDP
pDp
PDP

DI
81
OX

DLD..Pt\TA
AX

ex
IX
AX

fret
•• ,.ve_int_ti •• out
".'rve_int? _i5,.
push
pU!lh
push
push
push

end,

proc
AX
IX

ex
OX

push

91
01

push
push

IODV
mDV
MDV

09. AX
ES. AX

DB
AX.

DLD..Pt\TA

call

1.,..7_

,ap
pap
pap
pap
pDP
pDp
pap
pap

ES
OS
DI
&1
DX

IX
AX

231421-71

1-414

inter

AP-235

IPCO/USR/CHUCK/CSRC/ASBV. AS"

h·.t
•• "ve_int7 _i.,.
s .... ve_i nt6_isr
pu.h
push
push

push
push
push

push
push
mDV
mDV
mDV

endp

far

P1"OC

AX
BX
CX
OX
51
01
DB
ES
AX.
OS.
ES.

DLO_DATA
AX
AX

call

151"0_

pop
pop
pop
pop
pop
pop
pop
pop

E5
05
01
SI
OX
CX
OX
AX

iret
serve_into_i 51"

endp

•• ,.ve_ int5_isr

proc

push
push
push

push
pU1iih

push
pU'Ih

ex
ox
51
01

push

mDV
IIIDV

AX.
05.
ES.

mDV

far

AX
OX

OLD_DATA
AX
AX

call

15r5_

pop
pop
pop
pop
pop
pop
pop
pop

E5
DS
Dl
51
DX
CX
OX
AX

iT'et
!I.rve _int5_is"

endp

231421-72

1-415

AP-235

IPCD/usR/CHUCK/CSRC/ASSY. ASH

•• "ve_int2_i ....
p~.b

push
p~.h

p".h
~ulh

push
push

,.,.

proc:
...X
IX
CX
OX
SI

push

OS
ES

/I.V
/lDV
OIDV

AX. UAP..P...T ... ·
~S • ... X
ES. "'X

c.l1

2&1"2_

pop
pop
pop
pop
pop
pop
pop
pOp

ES
DS
DI
SI
DX
CX
IX
"'X

i,..t
••"'v._int2_isr

•• ,.ve_int1_'.,..
push
push
push
push
push
push
puah
push
OIOV
tiDy
.DV

endp
In

P'I"OC

... X

.ax
CX
DX

91
01
DS
EB

"'X.

OLD_DAT'"

OS • ... X
ES • ... X

call

IS1"1

pop
pop
pop
pop
pop
pop
pop
pop

DS
01
SI

... x

i,..t
~erv .. _int

1_1 sr

enabl._ proc

endp

far

231421-73

1-416

intJ

Ap·235

IPCO/USR/CHUCIVCSRC/ASSV. ABH

nt
en_b 18_ endp

for

proc

dlS.bl.
eli

ret
dis.ble_

endp

init_intv

proc

p~tih

far

pUGh

DS
AX

,or
mov

AX. AX
DS. AX

;

Interrupt

. mav

mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
mov
pop
pop
nt
init_intv_

tvP.'

for the IB6/l51 COMMpute,.

DS:tllol'd ptr

DS:word ptr
OS: IIIOT'd ptr
DS:lIIord ptr
DS:lllord ptr

D9:word ptr
DS:word ptr
DS:wOT'd pt.
DS:wol'd ptr
DS:IIJDT'd ptr
DS:word pt.
DS:wOT'd pt.
DS:l&lord pt.
DS:u.ord pt.
DS:wDrd pt.
DS:word pt.

BOh.
B2h.
84h,
Bl>h.
BBh.
BAh.
BCh.
BEh.
'10h.
'12h.
94h,
'1l>h.
'18h.
'1Ah.
'1Ch.
'1Eh.

offset serve_int_B274

tnt 0

DO_CODE
offset .8rV8 intI _is'r
DO_CODE

tnt

off&.t •• rv8_ tnt:! isr

int 2

DO_CODE

offset serve_lnt_ist'

int 3

DO_CODE
offset 5.'-""8_i nt_timeout
DO_CODE

tnt 4

offs.t s.r"e_lnt5_isr

int 5

DO_CODE

offset 5e1'''''8_i ntb_i til'
DO_CODE
off •• t •• ,."e_ int7 _isT'
DO_CODE

int I>

tnt 7

AX
DB
endp

DO_CODE ends

• nd

b~in,'

If.. : dld_d .. t ••

·.. s: .t.ek: stktop

231421-74

1-417

APPLICATION
NOTE

AP";236

November 1986

Implementing StarLAN with
the Intel 82588

ADIGOLBERT
DATA COMMUNICATIONS OPERATION
SHARAD GANDHI
FIELD APPLICATIONS-EUROPE

Order Number: 231422-003
1-418

IMPLEMENTING StarLAN
WITH THE INTEL 82588

CONTENTS

PAGE

1.0 INTRODUCTION ................... 1-421
1.1 StarLAN ......................... 1-421
1.2 The 82588 ...................... 1-421
1.3 Organization of the Application
Note .............. , ............... 1-421
1.4 References ...................... 1-421
2.0 StarLAN ...........................
2.1 StarLAN Topology ...............
2.1.1 Telephone Network .........
2.1.2 Star LAN and the Telephone
Network .......................
2.1.3 StarLAN and Ethernet ......
2.2 Basic Star LAN Components .....
2.2.1 A StarLAN Node Interface ..
2.2.2 StarLAN HUB ...............
2.2.3 Star LAN Cable .............
2.3 Framing .........................
2.4 Signal Propagation and
Collision ..........................
2.4.1 Situation # 1 ................
2.4.2 Situation #2 ................
2.4.3 Situation #3 ................
2.5 StarLAN System And Network
Parameters .......................

1-421
1-422
1-422
1-423
1-425
1-425
1-426
1-426
1-428
1-428
1-429
1-431
1-431
1-431
1-431

3.0 LAN CONTROLLER FOR
StarLAN ............................. 1-431
3.1 IEEE 802.3 Compatibility ......... 1-431
3.2 Configurability of the 82588 ...... 1-431
3.3 Clocks and Timers ............... 1-433
3.4 Manchester Data Encoding and
Decoding ......................... 1-433
3.5 Detection of the Collision Presence
Signal ............................ 1-434
3.5.1 Collision Detection by Code
Violation ....................... 1-435
3.5.2 Collision Detection by
Signature (or Bit) Comparison .. 1-435
3.5.3 Additional Collision Detection
Mechanisms ................... 1-436

1-419

CONTENTS

PAGE
3.6 Carrier Sensing .................. 1-436
3.7 Squelching the Input ............. 1-437
3.8 System Bus Interface ............ 1-438
3.9 Debug and Diagnostic Aids ...... 1-439
3.10 Jitter Performance .............. 1-440

4.0 THE 82588 .........................
4.1 Transmit and Retransmit
Operations . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Configuring the 82588 ...........
4.3 Frame Reception ................
4.3.1 Multiple Buffer Frame
Reception .....................
4.4 Memory Dump of Registers ......
4.5 Other Operations ................

CONTENTS

PAGE
6.1.1 HUB Input Ports ............ 1-465
6.1.2 Collision Detection .......... 1-466
6.1.3 The Local 82588 ............ 1-467
6.1.4 The Collision Presence
Signal ......................... 1-467
6.1.5 Signal Retiming ............. 1-468
6.1.6 Retiming Circuit, Theory of
Operation ...................... 1-468

1-440
1-441

6.1.7 Retiming Circuit
Implementation ................
6.1.8 Driver Circuits ..............
6.1.9 Header/lntermediate HUB
Switch .........................
6.1.10 Jabber Function ...........
6.1.11 HUB Receiver Protection
Timer ..........................
6.1.12 HUB Reliability: ...........

1-441
1-441
1-442
1-444
1-444

5.0 StarLAN NODE FOR IBM PC ...... 1-444
5.1 Interfacing to the IBM PC I/O
Channel .......................... 1·447
5.1.1 Register Access and Data Bus
Interface ....................... 1-447
5.1.2 Control Port ................ 1-448
5.1.3 Clock Generation ........... 1-449
5.1.4 DMA Interface .............. 1-449
5.1.5 Interrupt Controller .......... 1-450
5.2 Serial Link Interface ............. 1-451
5.2.1 Transmit Path .............. 1-451
5.2.2 Idle Pattern Generation ..... 1-451
5.3 Receive Path .................... 1-452
5.4 80188 Interface to 82588 ........ 1-454
5.5 iSBX Interface to StarLAN ....... 1-454
6.0 THE StarLAN HUB ................ 1-457
6.1 A StarLAN HUB for the IBM/PC .. 1-457

7.0 SOFTWARE DRiVER ..............
7.1 Interfacing to IBM PC ............
7.1.1 Doing I/O on IBM PC .......
7.2 Initialization and Declarations ....
7.3 General Commands .............
7.4 DMA Routines ...................
7.5 Interrupt Routines ...............

1-469
1-471
1-471
1~471
1-472
1-472
1-473
1-473
1-473
1-475
1-477
1-480
1-482

APPENDIX A: StarLAN SIGNALS ..... 1-485
APPENDIX B: 802.3 1BASE5 MULTI·
POINT EXTENSION (MPE) .......... 1-488
APPENDIX C: SINGLE DMA CHANNEL
INTERFACE ......................... 1-490
APPENDIX D: MEASURING NETWORK
DELAYS WITH THE 82588 .......... 1-492

1-420

intJ

AP-236

1.0 INTRODUCTION
Personal computers have become the most prolific
workstation in the office, serving a wide range of needs
such as word processing, spreadsheets, and data bases.
The need to interconnect PCs in a local environment
has clearly emerged, for purposes such as the sharing of
file, print, and communication servers; downline loading of files and application programs; electronic mail;
etc. Proliferation of the' PC makes it the workstation of
choice for accessing the corporate mainframe/s; this
function can be performed much more efficiently and
economically when clusters of PCs are already interconnected through Local Area Networks (LANs). According to market surveys, the installed base of PCs in
business environments reached about 10 million units
year-end '85, with only a small fraction connected via
LANs. The installed base is expected to double by
1990. There is clearly a great need for locally interconnecting these machines; furthermore, end users expect
interconnectability across vendors. Thus, there is an urgent need for industry standards to promote cost effective PC LANs.
A large number of proprietary PC LANs have become
available for the office environment over the past several years. Many of these suffer from high installed cost,
technical deficiencies, non-conformance to industry
standards, and general lack of industry backing. StarLAN, in Intel's opinion, is one of the few networks
which will emerge as a standard. It utilizes a proven
network access method, it is implemented with proven
VLSI components; it is cost effective, easily installable
and reconfigurable; it is technically competent; and it
enjoys the backing of a large cross section of the industry which is collaborating to develop a standard (IEEE
802.3, type !BASES).

1.1 StarLAN
StarLAN is a 1 Mb/s network based on the CSMA/
CD access method (Carrier Sense, Multiple Access
with Collision Detection). It works over standard,
unshielded, twisted pair telephone wiring. Typically,
the wiring connects each desk to a wiring closet in a
star topology (from which the IEEE Task Force working on the standard derived the name StarLAN in
1984). In fact, telephone and StarLAN wiring can coexist in the same twisted pair bundle connecting a desk to
the wiring closet. Abundant quantities of unused phone
wiring exist in most office environments, particularly in
the U.S. The StarLAN concept of wiring and networking concepts was originated by AT&T Information Systems.

tions needed for such networks. Besides inplementing
the standard CSMA/CD functions like framing, deferring, backing off and retrying on collisions, transmitting and receiving frames, it performs data encoding
and decoding in Manshester or NRZI format, carrier
sensing and collision detection, all up to a speed of 2
Mb/s (independent of the chosen encoding scheme).
These functions make it an optimum controller for a
Star LAN node. The 82588 has a very conventional microcomputer bus interface, easing the job of interfacing
it to any processor.

1.3 Organization of the Application
Note
This application note has two objectives. One is to describe StarLAN in practical terms to prospective imp lementers. The other is to illustrate designing, with 82588,
particularly as related to StarLAN which is expected to
emerge as its largest application area.
Section 2 of this Application Note describes the StarLAN network, its basic components, collision detection, signal propagation and network parameters. Sections 3 and 4 describe the 82588 LAN controller and its
role in the StarLAN network. Section 5 goes into the
details of designing a StarLAN node for the IBM PC.
Section 6 describes the design of the HUB. Both these
designs have been implemented and operated in an actual StarLAN environment. Section 7 documents the
software used to drive the 82588. It gives the actual
procedures used to do operations like, configure, transmit and receive frames. It also shows how to use the
DMA controller and interrupt controller in the IBM
PC and goes into the details of doing' I/O on the PC
using DOS calls. Appendix A shows oscilloscope traces,
of the signals at various points in the network. Appendix B describes the multiple point extension (MPE) being considered by IEEE. Appendixes C and D talk
about advanced usages of the 82588; working with only
one DMA channel, and measuring network delays with
the 82588.

1.4 References
For additional information on the 82588, see the Intel
Microcommunications Handbook. StarLAN specification are currently available in draft standard form
through the IEEE 802.3 Working Group.

1.2 The 82588
The 82588 is a single-chip LAN controller designed for
CSMA/CD networks. It integrates in one chip' all func1-421

2.0 StarLAN
Star LAN is a low cost 1 Mb/s networking solution
aimed at office automation applications. It uses a star

intJ

Ap·236

5) Off-the-shelf, Low cost RS-422, RS-485 drivers/receivers compatible with the StarLAN analog interface requirements. "

topology with the nodes connected in a point-to-point
fashion to a central HUB. HUBs can be connected in a
hierarchical fashion. Up to 5 levels are supported. The
maximum distance between a node and the adjacent
HUB or between two adjacent HUBs is 800 ft. (about
250 meters) for 24 gauge wire and 600 ft. (about 200
meters) for 26 gauge wire. Maximu!1l node-to-node distance with one HUB is 0.5 km, hence IEEE 802.3 designation of type IBASE5. 1 stands for 1 Mb/s and
BASE for baseband. (StarLAN doesn't preclude the use
of more than 800 ft wiring provided 6.5 dB maximum
attenuation is met, and cable propagation delay is no
"
more than 4 bit times).

2.1 StarLAN Topology

One of the most attractive features of StarLAN is that
it uses telephone grade twisted pair wire for the transmission medium. In fact, existing installed telephone
wiring can also be used for StarLAN. Tclephone wiring
is very economical to buy and install Although use of
telephone wiring is an obvious advantage, for small
clusters of nodes, it is possible to work around the use
of building wiring.
Factors contributing to low cost are:
1) Use of telephone' grade, unshielded, 24 or 26 gauge
twisted pair wire transmission media.
2) Installed base of redundant telephone wiring in" most
buildings.
3) Buildings are designed for star topology wiring.
They have conduits leading" to a central location.
4) Availability of low cost VLSI LAN controllers like
the 82588 for low cost applications and the 82586 for
high performance applications.

StarLAN, as the name suggests, uses a star topology.
The nodes are at the extremities of a star and the cen~
tral point is called a HUB. There can be more than one
HUB in a network. The HUBs are connected iIi a hierarchical fashion resembling an inverted tree, as shown
in Figure 1, where nodes are shown as PCS. The HUB
at the base (at level 3) of the tree is called the Header
Hub (HHUB) and others are called Intermediate HUBs
(IHUB). It will become apparent, later in this section,
that topologically, this entire network of nodes and
HUBs is equivalent to one where all the nodes are connected to a single HUB. Also StarLAN doesn't limit
the number of nodes or HUBS at any given level. "
2.1.1 TELEPHONE NETWORK

StarLAN is structured to run parallel to the telephone
network in a building. The telephone network has, in
fact, exactly the same star topology as StarLAN.Let us
now examine how the telephone system is typically laid
out in a building in the USA. Figure 2 shows how a
typical building is wired for telephones. 24 gauge
unshielded twisted pair wires emanate from a Wiring
Closet. The wires are in bundles of 25 or 50 pairs. The
bundle is called D inside wiring (DIW). The wires in
these cables end up at modular telephone jacks in the
wall. The telephone set is either connected directly to

HUB LEVEL 3

HUB LEVEL 2

HUB LEVEL 1

231422-2
'Maximum of 5 HUB levels.
'PCs or OTEs can connect directly at any level.

Figure 1. StarLAN Topology

1-422

inter

AP-236

the jack or through an extension cable. Each telephone
generally needs one twisted pair for voice and another
for auxilliary power. Thus, each modular jack has 2
twisted pairs (4 wires) connected to it. A 25 pair DIW
cable can thus be used for up to 12 telephone connections. In most buildings, not all pairs in the bundle are
used. Typically, a cable is used for only 4 to 8 telephone
connections. This practice is followed by telephone
companies because it is cheaper to install extra wires
initially, rather than retrofitting to expand the existing
number of connections. As a result, a lot of extra, unused wiring exists in a building. The stretch of cable
between the wiring closet and the telephone jack is typically less than 800 ft. (250 meters). In the wiring closet
the incoming wires from the telephones are routed to
another wiring closet, a P ABX or to the central office
through an interconnect matrix. Thus, the wiring closet
is a concentration point in the telephone network.
There is also a redundancy of wires between the wiring
closets.

2.1.2 StarLAN AND THE TELEPHONE
NETWORK

Star LAN does not have to run on building wiring, but
the fact that it can significantly adds to its attractiveness. Figure 3 shows how StarLAN piggybacks on telephone wiring. Each node needs two twisted pair wires
to connect to the HUB. The unused wires in the 25 pair
DIW cables· provide an electrical path to the wiring
closet, where the HUB is located. Note that the telephone and StarLAN are electrically isolated. They only
use the wires in the same bundle cable to connect to the
wiring closet. Within the wiring closet, StarLAN wires
connect to a HUB and telephone wires are routed to a
different path. Similar cable sharing can occur in connecting HUBs to one another. See Figure 4 for a typical
office wired for StarLAN through telephone wiring.

231422-3

Figure 2. Telephone Wiring in a Building

" - - BUNDLES OF
25 - 50 PAIRS
-------2 lWlSTED PAIRS

----.!

24 GAUGE, UNSHIELDED

231422-4
'SlarLAN and telephones share the same bundle, but are electrically isolated.
'StarLAN uses the unused wires in existing bundles.

Figure 3. Coexistence of Telephone and StarLAN

1-423

AP-236

WIRING CLOSET
IHUB

WIRING CLOSET

ROOM

WIRING CLOSET

TELEPHONE
WIRES TO PBX

WIRING CLOSET

231422-5

Figure 4. A Typical Office Using Telephone Wiring for StarLAN

1-42~

AP-236

2.1.3 Star LAN AND Ethernet

StarLAN and Ethernet are similar CSMA/CD networks. Since Ethernet has existed longer and is better
understood, a comparison of Ethernet with StarLAN is
worthwhile.
\. The data rate of Ethernet is lOMb/s and that of StarLAN is 1 Mb/s.
2. Ethernet uses a bus topology with each node connected to a coaxial cable bus via a 50 meter transceiver cable containing four shielded twisted pair
wires. StarLAN uses a star topology, with each node
connected to a central HUB by a point to point link
through two pairs of unshielded twisted pair wires.
3. Collision detection in Ethernet is done by the transceiver connected to the coaxial cable. Electrically, it
is done by sensing the energy level on the coax cable.
Collision detection in StarLAN is done in the HUB
by sensing activity on more than one input line connected to the HUB.

4. In Ethernet, the presence of collision is signalled by
the transceiver to the node by a special collision detect signal. In StarLAN, it is signalled by the HUB
using a special collision presence signal on the receive data line to the node.
5. Ethernet cable segments are interconnected using repeaters in a non-hierarchical fashion so that the distance between any two nodes does not exceed 2.8
kilometers. In StarLAN, the maximum distance between any two nodes is 2.5 kilometers. This is
achieved by wiring a maximum of five levels of
HUBs in a hierarchical fashion.

2.2 Basic Star LAN Components
A
\.
2.
3.

StarLAN network has three basic components:
StarLAN node interface
StarLAN HUB
Cable

SEGMENT 1

+-------L-------ETHERNET

STAR LAN
231422-6

Figure 5. Ethernet and StarLAN Similarities

1-425

inter

AP-236

2.2.1 A StarLAN NODE INTERFACE

Figure 6 shows a typical StarLAN node interface. It
interfaces to a processor on the system side. The processor runs the networking software. The heart of the
node interface is the LAN controller which does the job
of receiving and transmitting the frames in adherence
to the IEEE 802.3 standard protocol. It maintains all
the timings-like the slot time, interframe spacing
etc.-required by the network. It performs the functions of framing, deferring, backing-off, collision detection which are necessary in a CSMA/CD network. It
also does Manchester encoding of data to be transmitted and clock separation-or decoding-of the Manchester encoded data that is received. These signals before going to the unshielded twist pair wire, may undergo pulse shaping (optional) pulse shaping basically
slows down the fall/rise times of the signal. The purpose of that is to diminish the effects of cross-talk and
radiation on adjacent pairs sharing the same bundle
(digital voice, TI trunks, etc). The shaped signal is sent
on to the twisted pair wire through a pulse transformer
for DC isolation. The signals on the wire are thus differential, DC isolated from the node and almost sinusoidal (due to shaping and the capacitance of the wire).
NOTE:
Work done by the IEEE 802.3 committee has shown
that no slew rate control on the drivers is required.
Shaping by the transformer and the cable is sufficient
to avoid excessive EMI radiation and crosstalk.
The squelch circuit prevents idle line noise from affecting the receiver circuits in the LAN controller. The
squelch circuit has a 600 mv threshold for that purpose.
Also as part of the squelch circuitry an envelope detector is implemented. Its purpose is to generate an envelope of the transitions of the RXD line. Its output serve

as a carrier sense signal. The differential signal from the
HUB is received.using a zero-crossing RS-422 receiver.
Output of the receiver, qualified by the squelch circuit,
is fed to the RxD pin of the LAN controller. The RxD
signal provides three kinds of information:
I) Normal received data, when receiving the frame.
2) Collision information in the form of the collision
presence signal from the HUB.
3) Carrier sense information, indicating the beginning
and the end of frame. This is useful during transmit
and receive operations.
2.2.2 StarLAN HUB

HUB is the point of concentration in StarLAN. All the
nodes transmit to the HUB and receive from the HUB.
Figure 7 shows an abstract representation of the HUB.
It has an upstream and a downstream signal processing
unit. The upstream unit has N signal inputs and I signal output. And the downstream unit has I input and
N output signals. The inputs to the upstream unit come
from the nodes or from the intermediate HUBs
(IHUBs) and its output goes to a higher level HUB.
The downstream unit is connected the other way
around; input from an upper level HUB and the outputs to nodes or lower level IHUBs. Physically each
input and output consist of one twisted pair wire carrying a differential signal. The downstream unit essentially just re-times the signal received at the input, and
sends it to all its outputs. The functions performed by
the upstream unit are:
1. Collision detection
2. Collision Presence signal generation
3. Signal Retiming
4. Jabber Function
5. Start of Idle protection timer

PULSE
TRANSFORMER
8 BIT BUS
82588

TxD
~

TELEPHONE
JACK

PULSE
SHAPING
_ _ (OPTIONAL)

CONTROL

< >

RxD

SYS elK

SQUELCH

+
ENABLE
CIRCUITS

231422-7

Figure 6. 82588 Based StarLAN Node

1-426

Ap·236

the HUB associated with this function and their operation is described in section 6.
The last function implemented by the HUB is the start
of Idle prot~tion timer. During the end of reception,
the HUB Will see a long undershoot at its input port.
This undershoot is a consequence of the transformer
discharging accumulated charge during the 2 microseconds of high of the idle pattern. The HUB should implement a protection mechanism to avoid the undesirable effects of that undershoot.

231422-8

Figure 7. A StarLAN HUB

The collision detection i~ the HUB is done by sensing
t?~ activity on the inputs. If there is activity (or tran·
slt!ons) on more than one input, it is assumed that more
than one node is transmitting. This is a collision. If a
collision is detected, a special signal called the Collision
Presence Signal is generated. This signal is generated
and sent out as long as activity is sensed on any of the
input lines. This signal is interpreted by every node as
an occurrence of collision. If there is activity only on
one input, that signal is re·timed---or cleaned up of any
accumulated jitter-and sent out. Figure 8 shows the
input to output relations of the HUB as a black box.
If a node transmits for too long the HUB exercises a
J~bber

function to disable the node from interfering
with traffic from other nodes. There are two timers in

IDLE
IDLE
IDLE

VALID
MANCHESTER

Figure 9 shows a block diagram of the HUB. A switch
position determines whether the HUB is an IHUB or a
HHUB (Header HUB). If the HUB is an IHUB the
switch decouples the upstream and the downst;eam
units. HHUB is the highest level HUB; it has no place
to send its output signal, so it returns its output signal
(through the switch) to the outputs of the downstream
unit. There is one and only one HHUB in a StarLAN
network and it- is always at the base of the tree. The
returned signal eventually reaches every node in the
network through the intermediate nodes (if any). StarLAN specifications do not put any restrictions on the
number of IHUBS at any level or on number of inputs
to any HUB. The number of inputs per HUB are typically 6 to 12 and is dictated by the typical size of clusters in a given networking environment.

COLLISION PRESENCE
'IDLE
IDLE

VALID MANCHESTER

IDLE

VALID MANCHESTER
IDLE
VALID MANCHESTER

COLLISION PRESENCE
IDLE
IDLE

COLLISION
PRESENCE

IDLE

COLLISION
PRESENCE

VALID MANCHESTER
231422-9

Figure 8. HUB as a Black Box

1-427

intJ

AP-236

TRANSMIT PAIR /I 1

:311

·II~
+

TO HIGHER
LEVEL HUB

JABBER

+
TRANSMIT PAIR

RECEIVE PAIR

II N

PROTECTION
TIMER

HHUB

+-)11

0----1
IHUB

SIGNAL
RETIMING

~11r.:.
~

+-)11
RECEIVE PAIR

N
231422-10

Figure 9. StarLAN HUB Block Diagram
Although it is outside the scope of the IEEE 802.3
IBASE5 standard, there is considerable interest in using fiber optics and coaxial cable for node to HUB or
HUB to HUB links especially in noisy and factory environments. Both these types of cables are particularly
suited for point-to-point connections. Even mixing of
different types of cables is possible (this kind of environments are not precluded).

2.2.3 StarLAN CABLE
Unshielded telephone grade twisted pair wires are used
to connect a node to a HUB or to connect two HUBs.
This is one of the cheapest types of wire and an important factor in bringing down the cost of StarLAN.
Although the 24 gauge wire is used for long stretches,
the actual connection between the node and the telephone jack in the wall is done using extension cable,
just like connecting a telephone to a jack. For very
short StarLAN configurations, where all the nodes and
the HUB are in the same room, the extension cable
with plugs at both ends may itself be sufficient for all
the wiring. (Extension cables must be of the twisted
pair kind, no flat cables are allowed).

NOTE:
StarLAN IEEE 802.3 IBASE5 draft calls for a maximum attenuation of 6.5 dB between the transmitter
and the corresponding receiver at all frequencies between 500 KHz to 1 MHz. Also the maximum allowed cable propagation delay is 4 microseconds.

The telephone twisted pair wire of 24 gauge has the
following characteristics:
Attenuation
DC Resistance
Inductance
Capacitance
Impedance

:
:
:
:
:

42.55 db/mile @ 1 MHz
823.69 O/mile
0.84 mH/mile
0.1 p.F/mile
92.60, :--4 degrees @ I MHz

Experiments have shown that the sharing of the telephone cable with other voice and data services does not
cause any mutual harm due to cross-talk and radiation,
provided every service meets the FCC limits.

2.3 Framing
Figure 10 shows the format of a 802.3 frame. The beginning of the frame is marked by the carrier going
active and the end marked by carrier going inactive.
The preamble has a 56 bit sequence of 101010 ....
ending in a O. This is followed by 8 bits of start of frame
delimiter (sfd) - 10101011. These bits are transmitted
with the MSB (leftmost bit) transmitted first. Source
and destination fields are 6 bytes long. The first byte is
the least significant byte. These fields are transmitted
with LSB first. The length field is 2 bytes long and gives
the length of data in the Information field. The entire
information field is a minimum of 46 bytes and a maximum of 1500 bytes. If the data content of the Informa-

1-428

AP-236

tion field is less than 46, padding bytes are used to
make the field 46 bytes long. The Length field indicates
how much real data is in the Information field. The last
32 bits of the frame is the Frame Check Sequence
(FCS) and contains the CRC for the frame. The CRC is
calculated from the beginning of the destination address to the end of the Information field. The generating polynomial (Autodin II) used for CRC is:
X32

Xl0

The frames can be directed to a specific node (LSB of
address must be 0), to a group of nodes (multicast or
group-LSB of address must be 1) or all nodes (broadcast-all address bits must be 1).

2.4 Signal Propagation and Collision
Figure 11 will be used to illustrate three typical .situations in a StarLAN with two IHUBs and one HHUB.
Nodes A and B are connected to HUB1, nodes C and D
to HUB2 and node E to HUB3.

+ X23 + X22 + X16 + X12 + XII +
+ X8 + X7 + X5 + X4 + X2 + X + 1
X26

No need for Figure N.

CARRIER ON

=
=

MAX 1500
MIN 46

CARRIER OFF

4 ..

IPREAMBLE Ism IDA ISA ILEN IINFORMATION IFCS I
,.

FRAME LENGTH----I
MAX=1518
MIN=64

SFD = Start of Frame Delimiter
DA = Destination Address
SA = Source Address
LEN = Length
FCS = Frame Check Sequence
All numbers indicate field length in octets.

Figure 10. Framing

1-429

231422-11

inter

AP-236

231422-12

Situation #1. A Transmitting

231422-13

Situation '" 2. A & B Transmitting

231422-14

Situation # 3. A, B & C Transmitting
HUB1, HUB2 are IHUBs
HUB3 is the HHUB
Fa, Fb, Fo-Frames from nodes A, B & C
Fx-Collision Presence Signal

Figure 11. Signal Propagation and Collisions

1-430

inter

AP-236

Backoff method ......... Truncated binary exponential
Encoding ............................ Manchester

2.4.1 Situation # 1
Whenever node A transmits a frame Fa, it will reach
HUB 1. If node B is silent, there is no collision. HUB 1
will send Fa to HUB3 after re-timing the signal. If
nodes C, D and E are also silent, there is no collision at
HUB2 or HUB3. Since HUB3 is the HHUB, it sends
the frame Fa to HUBl, HUB2 and to node E after retiming. HUBI and HUB2 send the frame Fa to nodes
A, Band C, D. Thus, Fa reaches all the nodes on the
network including the originator node A. If the signal
received by node A is a valid Manchester signal and not
the Collision Presence Signal (CPS) for the entire duration of the slot time, then the node A aSSllmes that it
was a successful transmission.
2.4.2 Situation # 2
If both nodes A and B were to transmit, HUB 1 will
detect it as a collision and will send signal Fx (the Collision Presence Signal) to the HUB3-Note that HUBI
does not send Fx to nodes A and B yet. HUB 3 receives
a signal from HUB 1 but nothing from node E or
HUB2, thus it does not detect the situation as a collision and simply re-times the signal Fx and sends it to
node E, HUB2 and HUB1. Fx ultimately reach all the
nodes. Nodes A and B detect this signal as CPS and
call it a collision.

Clock tolerance ................ ±0.01% (100 ppm)
Maximum jitter per segment .............. ± 62.5 ns

3.0 LAN CONTROLLER FOR StarLAN
One of the attractive features of StarLAN is the availability of the 82588, a VLSI LAN controller, designed
to meet the needs of a StarLAN node. The main requirements of a StarLAN node controller are:
1. IEEE 802.3 compatible CSMA/CD controller.
2. Configurable to StarLAN network and system parameters.
3. Generation of all necessary clocks and timings.
4. Manchester data encoding and decoding.
5. Detection of the Collision Presence Signal.
6. Carrier Sensing.
7. Squelch or bad signal filtering.
8. Fast and easy interface to the processor.
82588 performs all these functions in silicon, providing
a minimal hardware interface between the system processor and the Star LAN physical link. It also reduces
the software needed to run the node, since a lot of functions, like deferring, back off, counting the number of
collisions etc., are done in silicon.

2.4.3 Situation # 3
In addition to nodes A and B, if node C were also to
transmit, the situation at HUBI will be the same as in
situation #2. HUB2 will propagate Fc from C towards
HUB3. HUB3 now sees two of its inputs active and
hence generates its own Fx signal and sends it towards
each node.
These situations should also illustrate the point made
earlier in the chapter that, the StarLAN network, with
nodes connected to multiple HUBs is, logically, equivalent to all the nodes connected to a single HUB (Yet
there are some differences between stations connected
at different HUB levels, those are due to different delays to the header hub HHUB).

3.1 IEEE 802.3 Compatibility
The CSMA/CD control unit on the 82588 performs the
functions of deferring, maintaining the Interframe
Space (IFS) timing, reacting to collision by generating a
jam pattern, calculating the back-off time based on the
number of collisions and a random number, decoding
the address of the incoming frame, discarding a frame
that is too short, etc. All these are performed by the
82588 in accordance to the IEEE 802.3 standards. For
inter-operability of different nodes on the Star LAN network it is very important to have the controllers strictly
adhere to the same standards.

3.2 Configurability of the 82588
2.5 Star LAN System and Network
Parameters
Preamble length (incl. sfd) .................. 64 bits
Address length ............................ 6 bytes
FCS length CRC (Autodin II) ............... 32 bits
Maximum frame length ................. 1518 bytes
Minimum frame length .................... 64 bytes
Slot time ............................ 512 bittimes
Interframe spacing ..................... 96 bit times
Minimum jam timing .................. 32 bit times
Maximum number of collisions .................. 16
Backofflimit .............................. ~ .. 10

Almost all the networking parameters are programmable over a wide range. This means that the StarLAN
parameters form a subset of the total potential of the
82588. This is a major advantage for networks whose
standards are being defined and are in a flux. It is also
an advantage when carrying over the experience gained
with the component in one network to other applications, with differing parameters (leveraging the design).
The 82588 is initialized or configured to its working
environment by the CONFIGURE command. After
the execution of this command, the 82588 knows its
system and network parameters. A configure block in

1-431

AP-236

memory is loaded into the 82588 by DMA. This block
contains all the parameters to be programmed as shown
in Figure 12. Following is a partial list of the parameters with the programmable range and the StarLAN
value:
StarLAN
Parameter
Range
Value
Preamble length 2,4,8,16 bytes
8
Address length
o to 6 bytes
6
CRCtype
16, 32 bit
32
Minimum frame
6 to 255 bytes
length
64
Interframe
12 to 255 bit times
spacing
96
Slot time
1 to 2047 bit times
512
Number of
retries
o to 15
15

StarLAN
Value

Parameter

Range

Data encoding

NRZI,Man.,
Diff. Man.
Code viol.,
Bit compo

Collision
detection

Manch..
Code Viol.

Beside these, there are many other .options available,
which mayor may not apply to StarLAN:
Data sampling rate of 8 or 16
Operating in Promiscuous mode
Reception of Broadcast frames
Internal loopback operation
External loopback operation
Transmit without CRC
HDLC Framing

BIT
BYTE

..1

I BYTE

COU~T (L.S.B)

..1

I
I
BYTE COUNT (M.S.B)

..1
2

SERIAL
MODE

CHNG

SMPLG
RATE

I
I
LENGTH

BUFFER

BOF
METD

I
PREAM LEN

INT
LP.BCK·

6
3,
I

I
SLOT TIME (L)

PAD

COT
SRC

BIT
STUFF

I
MINIMUM

NCRC
INS

I LIN PRIO I

..1

MAN
/NRZ'

CRS
SRC

PRM

CRSF

LENGTH

BC
DIS

FRAME

SLOT TIME (H)

TON
NCRS

1
~

CDTF

ADD LEN

CDBBC

CRC16

RETRY NUMBER

SPACING
3,

I
I

I FRAME
3,'

DIF.MAN
/MAN

..1

I
INTER

..1

.1.

NO SRC
ADD INS

P~IO

EXP

I
I
I
I

I
EXT
LP.BCK

FIFO LIMIT
I
I

OSC
RANGE

..1

1
I

CON FIG PARAMETER FORMAT
231422-15

Figure 12. Configuration Block

1-432

inter

AP-236

time, Back off time, Number of collisions, Minimum
frame length, etc. These timers are started and stopped
automatically by the 82588.

3.3 Clocks and Timers
The 82588 requires two clocks; one for the operation of
the system interface and another for the serial side.
Both clocks are totally asynchronous to each other.
This permits transmitting and receiving frames at data
rates that are virtually independent of the speed at
which the system interface operates.

3.4 Manchester Data Encoding and
Decoding
In StarLAN the data transmitted by the node must be
encoded in Manchester format. The node should also
be able to decode Manchester encoded data when receiving a frame-a process also known as clock recovery. The 82588 does the encoding and decoding of data
bits on chip for data rates up to 2 Mb/s.

The serial clock can be generated on chip using just an
external crystal of a value 8 or 16 times the desired bit
rate. An external clock may also be used.
The 82588 has a set of timers to maintain various timings necessary to run the CSMA/CD control unit.
These are timings for the Slot time, Interframe spacing

DATA

I0 I

Besides Manchester, the 82588 can also do encoding
and decoding in NRZI and Differential Manchester
formats. Figure 13 shows samples of encoding in

I0 I

NRZ
NRZI
MANCHESTER
DIFFERENTIAL
MANCHESTER

Encoding
Method

231422-16

Mid Bit Cell
Transitions

Bit Cell Boundary
Transitions

NRZ

Do not exist.

Identical to original data.

NRZI

Do not exist.

Exist only if original data
bit equals o.
Dependent on present
encoded signal level:
to 0 if 1
to 1 if 0

Manchester

Exist for every bit of
the original data:
from 0 to 1 for 1
from 1 to 0 for 0

Exist for consequent equal
bits of original data:
from 1 to 0 for 1 1
from 0 to 1 for 0 0

Differential
Manchester

Exist for every bit of
the original data.
Dependent on present
Encoded signal level:
to 0 if 1
to 1if 0

Exist only if original data
bit equals o.
Dependent on present
Encoded signal level:
to 0 if 1
to 1 if 0

Figure 13.82588 Data Encoding Rules

1-433

AP-236

periodic intervals. When the 82588 decodes tlds signal,
it fails to see nIid-cell transitions repeatedly at intervals
of 2.5 bit times and hence calls it a code violation. The
edges of CPS are marked for illustration as a, b, c,
d, ... 1. Let us see how the 82588 interprets the signal if
it starts calling the edge 'a' as the mid-cell transition for
'I'. Then edge at 'b' is '0'. Now the 82588 expects to see
an edge at ,., but since there is none, it is a Manchester
code violation. The edge that eventually does occur at
'd' is then used to re-synchronize and, since it is a falling edge, it is taken as a nIid-cell transition for '0'. The
edge at 'e' is for a '1' and then again there is no; edge at
'·'.This goes on, with the 82588 flagging code violation
and re'synchronizing again every 2.5 bit times. When a
transmitting node sees this CPS signal being returned
by the HUB (instead of a valid Manchester signal it
transmitted), it assumes that a collision occurred. The
82588 has two built-in mechanisms to detect collisions.
These mechanisms are very general and can be used for
a very broad class of applications to detect collisions in
a CSMA/CD network. Using these mechanisms, the
82588 can detect collisions (two or more nodes transmitting simultaneously) by just receiving the collided
signal during transmission, even if there was no HUB
generating the CPS sign8I.

these three formats. The main advantage of NRZI over
the other two is that NRZIrequires half the channel
bandwidth, for any given data rate. On the other hand,
since the NRZI signal does not have as many transitions as the other two, clock recovery from it is more
difficult; The main advantage of Differential Manchester over straight Manchester is that for a signal that is
differentially driven (as in RS 422), crossing of the two
wires carrying the data does not change the data received at the receiver. In other words, NRZI and Differentia.l: Manchester encoding methods are polarity insensitive (Even though NRZI, Differential Manchester
are polarity insensitive, the 82588 expects a high level
in the RXD line to detect' carrier inactive at the end of
frames).

3.5 Detection of the Collision
Presence Signal
In a StarLAN network, HUB informs the nodes that a
collision has occurred by sending the Collision Presence Signal (CPS) to the nodes. The CPS signal is a
special signal which contains violations in Manchester
encoding. Figure 14 shows the CPS signal. It has a 5 ms
period, looking very much like a valid Manchester signal except for missing transitions (or violations) at

ENCODING
CPS
EDGES:

abc
d
i--S},s PERIOD-j

I 2t I t i t = 0.5 }'S
• MISSING MID-CELL TRANSITION

82588
DECODING

10.

.r-u-t
abc

LJLI
d

10·

rLrl
)

kIm

1.J1..J"
)
kIm
Figure 14.82588 Decoding the Collision Presence Signal

1-434

231422-17

Ap·236

Collision also if:
RxD stays low for 25 samples or more
A mid cell transition is missing

3.5.1 COLLISION DETECTION BY CODE
VIOLATION

If during transmission, the 82588 sees a violation in the
encoding (Manchester, NRZI or Differential Manchester) used, then it calls it a collision by aborting the
transmission and transmitting a 32 bit jam pattern. The
algorithm used to detect collisions, and to do the data
decoding, is based on finding the number of sampling
clocks between an edge to the next one. Suppose an
edge occurred at time 0, the sampling instant of the
next edge determines whether it was a collision (C), a
long pulse (L)-with a nominal width of 1 bit time-, or
a short pulse (S)-nominal width of half a bit time. The
following two charts show the decoding and collision
detection algorithm for sampling rates of 8 and 16
when using Manchester encoding. The numbers at the
bottom of the line indicate sampling instances after the
occurrence of the last edge (at 0). The alphabets on the
top show what would be inferred by the 82588 if the
next edge were to be there.
Sampling rate

8 (clock is 8x bit rate)

,,
C

, L,

, C,

9 10 11 12 13

Collision also if:
RxD stays low for 13 samples or more
A mid cell transition is missing
Sampling rate = 16 (clock is l6x bit rate)
CCCCCSSSSSCLLLLLLLLLCCCC

A single instance of code violation can qualify as collision. The 82588 has a parameter called collision detect
filter (CDT Filter) that can be configured from 0 to 7.
This parameter determines for how many bit times the
violation must remain active to be flagged as a collision.
For StarLAN CDT Filter must be configured to Gthat is disabled.
3.5.2 COLLISION DETECTION BY SIGNATURE
(OR BIT) COMPARISON

This method of collision detection compares a signature
of the transmitted data with that of the data received on
the RxD pin while transmitting. Figure 15 shows a
block diagram ofthe logic. As the frame is transmitted
it flows through the CRC generation logic. A timer,
called the Tx slot timer, is started at the same time that
the CRC generation starts. When the count in the timer
reaches the slot time value, the current value of the
CRC generator is latched in as the transmit signature.
As the frame is returned back (through the HUB) it
flows through the CRC checker. Another timer-Rx
slot timer-is started at the same time as the CRC
checker starts checking. When this timer reaches the
slot time value, the current value of the CRC checker is
latched in as the receive signature. If the received signature matches the transmitted one, then it is assumed
that there was no collision. Whereas, if the signatures
do not match, a collision is assumed to have oC~llrred.

10 12 14 16 18 20 22 24 26

""""""""

""""'"

TRANSMITTED
FRAME

TX CRC

Tx SLOT
TIMER

TX SIGNATURE
LATCH

TRA NSMIT CHANNEL

+
+
Rx SLOT
TIMER

COMPARE·

RX SIGNATURE
LATCH

t
RECEIVED
FRAME

RX CRC

RE CEIVE CHANNEL
• MATCH = NO COLLISION
NO MATCH = COLLISION

Figure 15. Collision Detection by Signature Comparison

1-435

231422-18

inter

AP-236

Note that, even if the collision were to occur in the first
few bits of the frame, a slot time must elapse before it is
detected. In the code violation method, collision is detected within a few bit times. However, since the signature method compares the signatures, which are characteristic of the frame being transmitted, it is more robust. The code violation method can be fooled by returning a signal to the 82588 which is not the same as
the transmitted signal but is a valid Manchester signal-like a I MHz signal. Both methods can be used
simultaneously giving a combination of speed and robustness.
NOTE:
In order to reliably detect a collision using the collision by bit comparison mode, the transmitter must
still be transmitting up to the point where the receiver
has seen enough bits to complete its signature. Otherwise, the transmitter may be done before the RX signature is completed resulting in an undetected collision. A sufficient condition to avoid this situation is to
transmit frames with a minimum length of 1.5 • slottime (see Figure 16).
3.5.3 ADDITIONAL COLLISION DETECTION
MECHANISM

In addition to the collision detection mechanisms described in the preceding sections, the 82588 also flags
collision when after starting a transmission any of the
following conditions become valid:
a) Half a slot time elapses and the carrier sense of
82588 is not active.

b) Half a slot time + 16 bit times elapse and the opening flag (sfd) is not detected.
c) Carrier sense goes inactive after an opening flag is
received with transmitter still active.
These mechanisms add a further robustness to the collision detection mechanism of the 82588. It is also possible to OR an externally generated collision detect signal
to the internally generated condition by bit comparison
(see Figure 17).

3.6 Carrier Sensing
A StarLAN network is considered to be busy if there
are transitions on the cable. Carrier is supposed to be
active if there are transitions. Every node controller
needs to know when the carrier is active and when not.
This is done by the carrier sensing circuitry. On the
82588 this circuit is on chip. It looks at the RxD (receive data) pin and if there are transitions, it turns on
an internal carrier sense signal. It turns off the carrier
sense signal if RxD remains in idle (high) state for 13/8
bit times. This carrier sense information is used to mark
the start of the interframe space time and the back off
time. The 82588 also defers transmission when the carrier sense is active.
When operating in the NRZI encoded mode, carrier
sense is turned off if RxD pin is in the idle state for 8 bit
times or more (see Figure 18).

82588

HEAOENO
PO

CONDITION FOR RELIABLE COBBC
TLt.4INJRAt.4E-.LENGTH > SLOLTIt.4E + 2 * PO

t SLOLTIIAE ~ 2*PO

TLt.4INJRAt.4E_LENGTH

> 1.5*SLOLTIt.4E
231422-75

Figure 16. Limitation of CDBBC Mechanism

·1-436

inter

AP-236

COLLISION DETECTION BY BIT COMPARISON (CDBBC)
(CONfiGURE BYTE B, BIT 3)
.
COLLISION DETECTION SOURCE (INTERNAL, EXTERNAL)
(CONfiGURE BYTE 10, BIT 7)
231422-76

Figure 17. Mode 0, Collision Detection

3.7 Squelching the Input
Squelch circuit is used to filter idle noise on the receiver
input. Basically two types of squelch may be used: Voltage and time. Voltage squelch is done to filter out signals whose strength is below a defined voltage threshold (0.6 volts for Star LAN). It prevents idle line noise
from disturbing the receive circuits on the controller.
The voltage squelch circuit is placed right after the receiving pulse transformer. It enables the input to the
RxD pin of the 82588 only when the signal strength is
above the threshold.

If the signal received has the proper level but not the
proper timing, it should not bother the receiver. This is
accomplished by the time squelch circuit on the 82588.
Time squelching is essential to weed out spikes, glitches
and bad signal especially at the beginning of a frame.
The 82588 does not turn on its carrier sense (or receive
enable) signal until it receives three consecutive edges,
each separated by time periods greater than the fast
time clock high time but less than 13/8 bit-times as
shown in Figure 18.

MANCHESTER

DATA~
CARRIER

.1'---1

13/BBTxB

25/16BTx 16

NRZI

--u--

DATA~
CARRIER

II
ED~ESj

1:'';;'

,',o~1

L- - -

231422-77

Figure 18. Carrie.r Sensing

1-437

AP-236

The carrier sense activation can be programmed for a
further delay by up to 7 bit times by a configuration
parameter called carrier sense filter.

shows that it has an 8 bit data bus, read, write, chip
select, interrupt and reset pins going to the processor
bus. It also needs an external DMA controller for data
transfer. A system clock of up to 8 MHz is needed. The
read and write access times of the 82588 are very
short-95 ns-as shown by Figure 20. This further facilitates interfacing the controller to almost any processor.

3.8 System Bus Interface
The 82588 has a conventional bus interface making it
very easy to interface to any processor bus. Figure 19

SERIAL CLOCK
X2/RxC
RESET

RTS

DO-7
STANDARD
BUS
INTERFACE

CTS SERIAL
Tx D INTERFACE

Rli
WR

82588

28 PIN
PLASnC/CERAt.tIC

INT

~RxD

TClK
DROO
Dt.tA [ DACKO
INTERFACE DRO 1
DACK1

(t.tODE 0)

CRS} CSt.tA/CD
INTERFACE
CDT

ClK

SYSTEt.t CLOCK

231422-20

Figure 19. Chip Interface

80ns
(t.tIN)

95ns
(t.tIN)

55 ns----l
(t.tAX)

DATA

f-----75 n s - (t.tIN)

95ns
(t.tIN)
-Ons(t.tIN)

DATA
231422-21

Figure 20. Access Times
1-438

intJ

AP-236

The 82588 has over 50 bytes of registers, and most are
accessed only indirectly. Figure 21 shows the register
access mechanism of the 82588. It has one I/O port ;md
2 DMA channel ports. These are the windows into the
82588 for the CPU and the DMA controller. An external CPU can write into the Command register and read
from the Status registers using I/O instructions and
asserting chip select and write or read lines. Although
there is just one I/O port and 4 status registers, they
can be read out in a round robin fashion through the
same port as shown in Figure 22. Other registers like
the Configuration, Individual Address registers can be

accessed only through DMA. All the internal registers
can be dumped into memory by DMA using the Dump
command. The execution of some of the commands is
described in section 4. See the 82588 Reference Manual
for details on these commands.

3.9 Debug and DiagnostiC Aids
Besides the standard functions that can be used directly
for StarLAN, the 82588 offers many debug and diag-

8258B REGISTER SET

COMMAND

_-.. . -~9---f----L-.:::;.....-- ~

STATUS

WRITE ONLY

~. READ ONLY

CONFIGURATION
IA
MULTICAST

READ
&:

WRITE

Tx CRC
Rx CRC

IMPLICIT REGISTERS
(OVER 50 BYTES)
231422-22

Figure 21_ Register Acc.ess

1-439

AP-236

4 Status registers are accessed through one read port
POINTER

STATUS 0
t----.,----i
STATUS 1

--+

STATUS 2

I READ PORT

STATUS 3
231422-23

The pointer can be changed using a command or can be automatically incremented.

READ_STATUS_588: PROCEDURE;
OUTPUT (CS_588) = 15;
STATUS_588(O)=INPUT (CS_588);
STATUS_588(l)=INPUT (CS_588);
STATUS_588(2)=INPUT (CS_588);
STATUS_588(3)=INPUT (CS_588);
RETURN
END READ_STATUS_588;

/* COMMAND 15 "/

/" RELEASE. POINTER, INITIAL = 00 "/
/" REFRESH STATUS REGISTER IMAGE ./

/* IN MEMORY.

READING 4 STATUS REGISTERS
Figure 22. Reading the Status Register

nostics functions. The DIAGNOSE command of the
82588 does a self-test of most of the counters and timers
in the 82588 serial unit. Using the DUMP. command,
all the internal registers of the 82588 can be dumped
into the memory. The TDR command does Time Domain Reflectometery on the network. The 82588 has
two loopback modes of operation. In the internal loopback mode, the TXD line is internally connected to the
RXD one. No data appears outside the chip, and the
82588 is isolated from the link. This mode enables
checking of the receive and transmit machines without
link interference. In the external loopback mode, the
82588 becomes a full duplex device, being able to receive its own transmitted frames. In this mode data
goes through the link and all CSMA/CD mechanisms
are involved.

± 62.5 ns at I Mbs for both 8X, 16X Manchester enC
coded data.
Jitter = ± variation of an edge from its nominal posHion.
Jitter can occur on every edge.

I dW I dW I

::F>:

r-=F :

--~------~---.

.---~-----~---

~--W-----l.1

11-.

231422-78
x8

x16

±Y,6

±1I16

NRZI
(Code Violations Enabled)

± 1116 8T

±3/328T

NRZI
(Code Violations Disabled)

±31168T

Manchester

3.10 Jitter Performance
When the 82588 receives a frame from the HUB, the
signal has jitter. Jitter is the shifting of the edges of the
signal from their nominal position due to the transmission over a length of cable. Many factors like, intersymbol interference (pulses of different widths have different delays through the transmission media), rise and
fall times of drivers and receivers, cross talk etc., contribute to the jitter. StarLAN specifies a maximum jitter of ± 62.5 ns whenever the signal goes from a
NODE/HUB or HUB/HUB. Figure 23 shows that the
jitter tolerance of the 82588 is exactly the required

I dW I dW I

Figure 23. 82588 Jitter Performance

4.0 THE 82588
This chapter describes the basic 82588 operations.
Please refer to the 82588 reference manual in Intel Microcommunications Handbook for a detailed description. Basic operations like transmitting a frame, receiving a frame, configuring the 82588 and dumping the
register contents are discussed here to give a feel for
how the 82588 works.

1-440

inter

AP-236

4.1 Transmit and Retransmit
Operations
To transmit a frame, the CPU prepares a block in the
memory called the transmit data block. As shown in
Figure 24, this block starts with a byte count field, indicating how long the rest of the block is. The destination
address field contains the node address of the destination. The rest of the block contains the information or
the data field of the frame. The CPU also programs the
DMA controller with the start address of the transmit
data block. The DMA byte count must be equal to or
greater than the block length. The 82588 is then issued
a TRANSMIT command-an OUT instruction to the
command port of the 82588. The 82588 starts generating DMA requests to read in the transmit data block by
DMA. It also determines whether and how long it must
defer on the link and after that, it starts transmitting
the preamble. The 82588 constructs the frame on the
fly. It takes the destination address from the memory,
source address from its own individual address memory
(previously programmed), data field from the memory
and the eRC, is generated on chip, at the end of the
frame.

BYTE
COUNT

INFORMAnON

To re-attempt transmission, the CPU must reinitialize
the DMA controller 7to the start of the transmit data
block and issue a RETRANSMIT command to the
82588. When the 82588 receives the retransmit command and the back-off timer has expired, it transmits
again. Interrupt and the status register contents again
indicate the success or failure of the (re)transmit attempt.
The main difference between transmit and retransmit
commands is that retransmit does not clear the internal
count for the number of collisions occurred, whereas
transmit does. Moreoever, retransmit takes effect only
when the back-off timer has expired.

4.2 Configuring the 82588
To initialize the 82588 and program its network and
system parameters, a configure operation is performed.
It is very similar to the transmit operation. Instead of a
transmit data block as in transmit command, a configure data block-shown in Figure 12-is prepared by
the CPU in the memory. The first two bytes of the
block specify the length of the rest of the block, which
specify the network and system parameters for the
82588. The DMA controller is then programmed by
the CPU to the beginning of this block and a CONFIGURE command is issued to the 82588. The 82588 reads
in the parameters by DMA and loads the parameters in
the on-chip registers.

I. Prepare Transmit Data-Block in Memory
2. Program DMA Controller
3. Issue Transmit Command on the Desired
Channel

DESTIN.
ADDRESS

status registers to find out if the transmission was successful. If a collision occurs during transmission, the
82588 aborts transmission and generates the jam sequence, as required by IEEE 802.3, and informs the
CPU through interrupt and the status registers. It also
starts the back-off algorithm.

Similarly, for programming the INDIVIDUAL ADDRESS and MULTICAST ADDRESSes, the DMA
controller is used to load the 82588 registers.

231422-25

Transmit Data Block

4.3 Frame Reception

4. Interrupt is received on completion of command or if· the command was aborted or
there was a collision. The status bytes 1 and
2 indicate the result of the operation.
4

TX
DEF
caLL

HRT MAX
BEAT call
TX
OK

STATUS 1

NUM. OF COLLISIONS

I Las~ I LOST IUNDER
CRS
CTS RUN STATUS 2

231422-26

Transmit & Retransmit Results Format
Figure 24. Transmit Operation

At the conclusion of transmission the 82588 generates
an interrupt to the CPU. The CPU can then read the

Before enabling the 82588 for reception the CPU must
make a buffer available for the frame to be received.
The CPU must program the DMA controller with the
starting address of the buffer and then issue the ~
ENABLE command to the 82588. When a frame arrives at the RxD pin of the 82588, it starts being received. Only if the address in the destination address
matches either the Individual address, Multicast address or if it is a broadcast address, is the frame deposited into memory by the 82588 using DMA. The format
of storage in the memory is shown in Figure 25. At the
end, a two byte field is attached which shows the status
of the received frame. If CRC, alignment or overrun
errors· are encountered, they are reported. An inter-

1-441

infef

AP-236

RECEIVED FRAME

I. Prepare a Buffer for Reception

2. Program DMA Controller
3. Issue Receiver Enable Command
When a frame is received, it is deposited in the
memory. Receive status bytes (2) are appended to
the frame in the memory, byte count written in the
status registers I, 2,and an interrupt is generated.
RECEIVE
STATUS

SRT
FRM

DESTIN.
ADDRESS

SOURCE
ADDRESS

NO
EOF
RCV
O.K.

CRC
ERR

ALG
ERR

STATUS REG. 1
STATUS REG. 2

=~
BYTE

INFORMATION

RECEIVE
STATUS

COUNT
231422-27

Figure 25. Receive Operation (Single Buffer)

rupt from 82588 occurs when all the bytes have been
transferred to the memory. This informs the CPU that
a new frame has been received.
If the received frame has errors, the CPU must recover
(or re-use) the buffer. Note that the entire frame is deposited into one buffer. The 82588 when NOT configured for the external·loopback mode, will detect collisions (code violations) during receptions. Ifa collision
is detected, the reception is aborted and status updated.
CPU is then informed by an interrupt (if the collided
frame fragment is shorter than the address length, no
reception will be started), and no interrupt will happen.

@BUFFER 1
@BUFFER2

4.3.1 Multiple Buffer Frame Reception
It is also possible to receive a frame into a number of
fixed size buffers. This is particularly economical if the
received frames vary widely in size. If the single buffer
scheme were used as described above, the buffer required would have to be bigger than the longest expected frame and would be very wasteful for very short
(typically acknowledge or control) frames. The multiple buffer reception is illustrated in Figure 26. It uses
two DMA channels for reception.

)'~ '""'"

@BUFFER 3

·
·
·

@BUFFER N

Buffer
Pointer
Table
(Managed by CPU)

231422-28

Figure 26. Multiple Buffer Reception

1-442

inter

AP-236

As in single buffer reception, the one channel, say channel 0, of the DMA controller is programmed to the
start of buffer 1, and the 82588 is enabled for reception
with the chaining bit set. As soon as the first byte is
read out of the 82588 by the DMA controller and written into the first location of buffer 1, the 82588 generates an interrupt, saying that it is filling up its last available buffer and one more buffer must be allocated. The
filling up of the buffer 1 continues. The CPU responds
to the interrupt by programming the other DMA channel--channel I-with the start address of the second
buffer and issuing an ASSIGN ALTERNATE buffer
command with an INTACK (interrupt acknowledge).
This informs the 82588 that one more buffer is available on the other channel. When buffer 1 is filled up
(the 82588 knows the size of buffers from the configuration command), the 82588 starts generating the DMA
requests on the other channel. This automatically starts
filling up buffer 2. As soon as the first byte is written
into buffer 2, the 82588 interrupts the CPU again asking for one more buffer. The CPU programs the channel 0 of the DMA controller with the start address of
buffer 3, issues an ASSIGN ALTERNATE buffer command with INT ACK. This keeps the buffer 3 ready for
the 82588. This switching of channels continues until
the entire frame is received generating an end of frame
interrupt. The CPU maintains the list of pointers to the
buffers used.
Since a new buffer is allocated at the time of filling up
of the last buffer, the 82588 automatically switches to
the new buffer to receive the next frame as soon as the
last frame is completely received. It can start receiving
the new frame almost immediately, even before the end
of frame interrupt is serviced and acknowledged by the
CPU. If a new frame comes in, and the previous frame

interrupt is not yet acknowledged, another interrupt
needed for new buffer allocation is buffered (and not
lost). As soon as the first one is acknowledged, the interrupt line goes active again for the buffered one.
If by the time a buffer fills up no new buffer is available,
the 82588 keeps on receiving. An overrun will occur
and will be reported in the received frame status. However, ample time is available for the allocation of a new
buffer. It is roughly equal to the time to fill up a buffer.
For 128 byte buffers it is 128 X 8 = \024 ms or approximately 1 millisec. You get I ms to assign a new
buffer after getting the interrupt for it. Hence the process of multiple buffer reception is not time critical for
the system performance.
This method of reception is particularly useful to guarantee the reception of back-to-back frames separated by
IFS time. This is because a new buffer is always available for the new frame after the current frame is received.
Although both the DMA channels get used up in receiving, only one channel is kept ready for reception
and the other one can be used for other commands until
the reception starts. If an execution command like
transmit or dump command is being executed on a
channel which must be allocated for reception, the
command gets automatically aborted when the ASSIGN ALTERNATE BUFFER command is issued to
the channel used for the execution command. The interrupt for command abortion occurs after the end of
frame interrupt.

1-443

inter

AP-236

the 82588 command register and knowing the results (if
any) through the status registers.

4.4 Memory Dump of Registers
All the 82588 internal registers can be duIitped in the
memory by the DUMP command. A DMA channel is
used to transfer the register contents to the memory. It
is very similar to reception of a frame; instead of data
from the serial link, the data from the registers gets
written into the memory. This provides a software debugging and diagnostic tool.

4.5 Other Operations
Other 82588 operations like DIAGNOSE, TDR,
ABORT, etc. do not require any parameter or data
transfer. They are executed by writing a command to

5.0 StarLAN NODE FOR IBM PC
This chapter deals with the hardware-the. StarLAN
board-to interface the IBM PC to a StarLAN Network. This is a slave board which takes up one slot on
the I/O channel of the IBM PC. Figure 27. shows an
abstract· block diagram of the board. It requires the
IBM PC resources of the CPU, memory, DMA and
interrupt controller on the system board to run it. Such
a board has two interfaces. The IBM PC I/O Channel
on the system or the parallel side and the. telephone
grade twisted pair wire on the serial side. Figures 28, 29
show the circuit diagram of the board.

PULSE
TRANSFORMER

TELEPHONE
JACK

8 BIT BUS
8258B

PULSE

~"--_"'" SHAPING
SYSTEM
BUS

CONTROL
RxD

SYS CLK
SQUELCH

+
ENABLE
CIRCUITS
231422-29

Figure 27. 82588 Based StarLAN Node

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DCO 'I1IICHIIICAL -.:TIHG. IH'IEL

TITLE

PC - STAIIIMI - II2S88
FILE
NODE2.DIoI.

2'"lIi'2
231422-80

:.
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intJ

AP-236

5.1 Interfacing to the IBM PC 1/0
Channel
IBM PC has 8 slots on the system board to allow expansion of the basic system. All of them are electrically
identical and the I/O channel is the bus that links them
all to the 8088 system bus. The I/O channel contains
an 8 bit bidirectional data bus, 20 address lines, 6 levels
of interrupt, 3 channels ofDMA control lines and other
control lines to do 1/0 and memory readlwrite operations. Figure 30 shows the signals and the pin assignment for the I/O Channel.

to 82588 for commands and status, address 301H accesses an on board control port that enables the various
interrupt and DMA lines. Even though only two addresses are needed, the card uses all the 16 addresses
spaces from 300H to 30FH. This was done to keep simplicity and minimum component count. Registers address decoding is done using a PAL (16L8) and an external NAND gate (U8).
Hex Range

OOO-OOF
020-021
040-043
060-063
080-083
OAX'
OCX
OEX
200-20F
210-217
220-24F
278-27F
2FO-2F7
2F8-2FF

Rear Panel
SIGNAL NAME

GNO

..."..

...,.. I\.

Sl GNAL NAME
1/0 CH CK

+07

+RESET DRV
+5V

+06

+IRQ2

+05

-SVDC

+04

+DRQ2

+03

-12V

+02

-CARD SLcrD

+01

+12V

+00
810 AID

GNO

+1/0 CH ROY

-MEMW

+AEN

-MEMR

+A19

-lOW

+A18

-lOR

+A17

-DACK3

+A16

+DRQ3

+A1S

-OACKl

+A14

+DRQl

+A13

-OACKO

+A12

CLOCK

+Al0

+IRQ7

+A9

+lRQ5

+AS

+IRQ4

+A7

+IRQ3

+A6

-OACK2

+AS

+T/C

+ALE

+A3

+SV

+A2

+osc

+Al

831 A31

3AO-3A9
SBO-3BF
SCO-SCF
3DO-3DF
3EO-SE7
3FO-3F7
3F8-3FF

+Al1

820 A20

+IRQ6

GNO

300-31 F
320-32F
378-37F
380-38C**
380-389**

* At power-on time, the Non Mask Interrupt into the

8088 is masked off.
This mask bit can be set and reset through
system software as follows:
Set mask: Write hex 80 to I/O Address hex AO
(enable NMI)
Clear mask: Write hex 00 to I/O Address hex AO
(disable NMI)
•• SDLC Communications and Secondary Binary
Synchronous Communications cannot be used
together because their hex addresses overlap.

+AO

'"'-

Usage

DMA Chip 8237 A-5
Interrupt 8259A
Timer 8253-5
PP18255A-5
DMA Page Registers
NMI Mask Register
Reserved
Reserved
Game Control
Expansion Unit
Reserved
Reserved
Reserved
Asynchronous Communications
(Secondary)
Prototype Card
Fixed Disk
Printer
SDLC Communications
Binary Synchronous Communications
(Secondary)
Binary Synchronous Communications
(Primary)
IBM Monochrome Display/Printer
Reserved
Color/Graphics
Reserved
Diskette
Asynchronous Communications
(Primary)

COMPONENT SIDE

231422-31

Figure 30. 1/0 Channel Diagram

5.1.1 REGISTER ACCESS AND DATA BUS
INTERFACE

Figure 31.110 Address Map

The CPU accesses the StarLAN adapter card through 2
1/0 address windows. Address 300H is used to access

1-447

inter

AP-236

CS_ (to SB8)

LOGIC
U2. U8

LDPRL (to DMA. INTERRUPT enable lines)

231422-56.

Format of Following Equations Will Be According To
The Following Specifications:
. INVERT
SIGNAL ACTIVE LOW
&:

LOGIC AND

LOGIC OR

A9NANDA8 = ! (A9 &: A8)
CS_ =!

!AEN &: !A9NANDA8 &: !A 7 &: !A6 &:, !A5 &: !A4 &: !AO

LDPORT_ = ! ( !AEN &: !A9NANDA8 &: !A7 &: !A6 &: !A5 &: !A4 &: AO &: !IOWR_
BUSEN_ = DACKl_ &: DACK2_ &: (! ( !AEN &: !A9NANDA8 &: IA7 &: IA6 &: IA5 &: IA4));
The signal CS_ decodes address 300H, it is only active
when AEN is inactive meaning CPU and not DMA .
cycles. LDPORT_ has exactly the same logic for address 30tH, but it is only active during I/O write cycles. The I/O port sitting on address 301H is write
only. The data BUS lines DO to D7 are buffered from
the 82588 to the PC bus using an 74LS245 transceiver
chip.

The Bus transceiver is enabled if: A DMA access is
taking place, or I/O ports 300H to 30FH are being
accessed.
5.1.2 Control Port

As mentioned the StarLAN adapter port has a 4-bit
write only control port. The purpose of this port is to
selectively enable the DMA and INTERRUPT request
lines. Also it can completely disable the transniitter.
Control Port Definition

I ENDRQ1 I ENDRQ3 I ENINTER I TXEN
TO SBB

231422-57

Data Bus Interface

ENDRQl, ENDRQ2 : "1" Enable DMA requests.
ENINTER
: "1" Enable INTERRUPT
request.
: "t" Enable the transmitter.
TXEN
On power up all bits default to "0".

1-448

AP-236

5.1.3 CLOCK GENERATION
The 82588 requires two clocks for operation. The system clock and the serial clock. The serial clock can be
generated on chip by putting a crystal across Xl and
X2 pins. Alternatively, an externally generated clock
can be fed in at pin Xl (with X2 left open). In both
cases, the frequency must be either 8 or 16 times (sampling factor) the desired bit rate. For StarLAN, 8 or 16
MHz are the correct values to generate 1 Mb/s data
rate. A configuration parameter is used to tell the
82588 what the sampling factor is. An externally supplied clock must have MOS leve!s (~.6V -3.9V). ~pec~
cations for the crystal and the CircUIt are shown m Figure 32.
The system clock has to be supplied externally. It can
be up to 8 MHz. This clock runs the parallel side ofthe
82588. Its frequency does not have any impact on the
read and write access times but on the rate at which
data can be transferred to and from the 82588 (Maximum DMA data rate is one byte every two system
clocks). This clock doesn't require MOS levels.
The I/O channel of the IBM PC supplies a 4.77 MHz
signal of 33% duty cycle. This signal could be used as a
system clock. It was decided, however, to generate a
separate clock on the StarLAN board to be independent of the I/O channel clock so that this board can
also be used in other IBM PCs and also in some other
compatibles. The 8 MHz system clock is generated us-

ing a DIP OSCILLATOR which have the required 50
ppm tolerance to meet StarLAN. This clock is converted to MOS levels by 74HCTOO and fed into both the
system and serial clock inputs.

5.1.4 DMA INTERFACE
The 82588 requires either one or two DMA channels
for full operation. In this application, one channel is
dedicated for reception and the other is used for transmissions 'and the other commands. Use of only one
DMA channel is possible but may require more com"
plex software, also some RX frames may be lost during
switches of the DMA channel from the receiver to the
transmitter (Those frames will be recovered by higher
layers of the protocol). Also using only one DMA
channel will limit the 82588 loopback functionality. So
the recommendation is to operate with two DMA channels if available. Appendix C describes a method of operating with only one DMA channel without loosing
'
RX frames.
The IBM PC system board has one 8237A DMA controller. Channel 0 is used for doing the refresh of
DRAMs. Channels 1,2 and 3 are available for add-on
boards on the I/O Channel. The floppy disk controller
board uses the DMA channel 2 leaving' exactly two
channels (I and 3) for the 82588. The'situation is worse
if the IBM PC/XT is used, since it uses channel 3 for
the Winchester hard disk leaving just the channel 1 for

Sc:ri,es Resonance
-Frequency Will Drift by About 400 PPM from Nominal
-No Capacitors Needed
-Doesn't Meet StarLAN Requirements

.d:.
0 T

YC1

CRYSTAL

82588

Meeting StarLAN 100 PPM Requirements
YC2

-Use Parallel Resonance Crystal
-Recommended For Precise Frequencies
-82588 X-TAL Oscillator Stability ±35 PPM (0-70"C)

Crystal: Load Capacitance
= 20pF
Shunt Capacitance = 7 pF Maximum
Series Resistance = 30n Maximum
Frequency Tolerance = 50 PPM (0-70°C)
CI, C2 -+ 27 pF or 39 pF, 5%

Figure 32. Crystal Specifications

1-449

231422-81

AP-236

5.1.5 INTERRUPT CONTROLLER

the 82588. On the other hand, the IBM PC/AT has 5
free DMA channels. We will' assume that 8237 A DMA
channels I and 3 are available for the 82588 as in the
case of the IBM PC.
Since the channel 0 of 8237A is used to do refresh of
DRAMs all the channels should be operated in single
byte transfer mode. In this mode, after every transfer
for any channel the bus is granted to the current highest priority channel. In this way, no channel can hog
the bus bandwidth and, more important, the refresh of
DRAMs is assured every 15 microseconds since the refresh channel (number 0) has the highest priority. This
mode of operation is very slow since the HOLD is
dropped by the 8237A and then asserted again after
every transfer. Demand mode of operation is a lot more
suitable to 82588 but it cannot be used because of the
refresh requirements.

The 82588 interrupts the CPU after the execution of a
command or on reception of a frame. It uses the 8259A
interrupt controller on the system board to interrupt
the CPU. There are 6 interrupt request lines, IRQ2 to
IRQ7, on the I/O channel. Figure 34shows the assignment of the lines. In fact, none of the lines are completely free for use. To add any new peripheral which
uses a system board interrupt, this interrupt needs to
have the capability to share the specific line, by driving
the line with a tri-state driver. The 82588 StarLAN
adapter board can optionally drive interrupt lines
IRQ3, IRQ4 or IRQ5 (An 74LS125 driver is used).
Number

Usage

NMI

Parity
Timer
Keyboard
Reserved
Asynchronous Communications
(Secondary)
SDLC ~ommunications
BSC (Secondary)
Asynchronous Communications
(Primary)
SDLC Communications
BSC (Primary)
Fixed Disk
Diskette
Printer

0
1

Whenever the 82588 interfaces to the 8237A in the single transfer mode, there is a potential 8237A lock-up
problem. The 82588 may deactivate its DMA request
line (DREQ) before receiving an acknowledge from the
DMA controller. This situation may happen during
command abortions, or aborted receptions. The 8237A
under those circumstances may lock-up. In order to
solve this potential problem, an external logic must be
used to insure that DREQ to the DMA controller is
never deactivated before the acknowledge is received.
Figure 33 shows the logic to implement this function.
This logic is implemented in the 16L8 PAL.

2
3

The 82588 DREQ lines are connected to the IBM/PC
bus through tri-state buffers which are enabled by writing to I/O port 301H. This function enables the use of
either one or two DMA channels and also the sharing
of DMA channels with other adapter boards.

5
6
7

Figure 34. IBM PC Hardware Interrupt Listing

588REO~. DREO .
DACK

RESET----------'

588 REO---.J

DREO---.J
231422-82

Figure 33. DMA Request Logic

1-450

inter

AP-236

5.2 Serial Link Interface

5.2.1 TRANSMIT PATH

A typical StarLAN adapter board is connected to the
twisted pair wiring using an extension cable (typically
up to 8 meters-25 ft.). See Figure 35. One end of the
cable plugs into the telephone modular jack on the StarLAN board and the other end into a modular jack in
the wall. The twisted pair wiring starts at the modular
jack in the wall and goes to the wiring closet. In the
wiring closet, another telephone extension cable is used
to connect to a StarLAN HUB. The transmitted signal
from the 82588 reach the on-board telephone jack
through a RS-422 driver with pulse shaping and a pulse
transformer. The received signals from the telephone
jack to the 82588 come through a pulse transformer,
squelch circuit and a receive enable circuit.

The single ended transmit signal on the TxD pin is
converted to a differential signal and the rise and fall
times are increased to 150 to 200 ns before feeding it to
the pulse transformer (this pulse shaping is not a requirement, but proves to give good results). Am26LS30
is a RS-422 driver which converts the TxD signal to a
differential signal. It also has slew rate control pins to
increase to rise and fall times. A large rise and fall time
reduces the possibility of crosstalk, interference and radiation. By the other hand a slower edge rate increases
the jitter. In the StarLAN adapter card, the first approach was used. The 26LS30 converts a square pulse
to a trapezoidal one-see Figure 36. The filtering effect
of the cable further adds to reduce the higher frequency
components from the waveform so that on the cable the
signal is almost sinusoidal. The pulse transformer is for
DC isolation. The pulse transformers from Pulse Engineering-type PE 64382-was used in this design. This
is a dual transformer package which introduces an additional rise and fall time of about 70-100 ns on the
signal, helping the former discussed waveshaping.

•

'----II-,.~~~~

EXTENSION
CABLE

5.2.2 IDLE PATTERN GENERATION

INTO IBM PC

WIRING
PANEL

IN THE WIRING CLOSET

StarLAN requires transmitters to generate an IDLE
pattern after the last transmitted data bit. The IDLE
pattern is defined to be a constant high level for 2 - 3
microseconds. The purpose of this pattern is to insure
that receivers will decode properly the last transmitted
data bits before signal decay. Currently the 82588 needs
one external component to generate the IDLE. The operation principle is to have an external shift register
(74LSI64) that will kind of act as an envelope detector
of the TXD line. Whenever the TXD line goes low

231422-33

Figure 35. Path from StarLAN Board to HUB

82588

I-T;.;;x::D....._ _....::.:.=::~

150 ns
RISE/FALL
TIMES

231422-34

Figure 3S. Wave Shaping

1-451

inter

AP-236

(first preamble bit), the output of the shift register
(third cell) will immediately go low, enabling the RS422 driver, the shift register being clocked by TCLKwill time the duration of the TXD high times. If the
high time is more than 2 microseconds, meaning that
the 82588 has gone idle, the transmitter will be disabled
(See Figure 37). Another piece of this logic is the ORing of the output of the shift register with TXEN-signal which comes from the board control port. This signal completely disables the transmitter. The other purpose of this enable signal, is to make sure that after
power-up, before the 82588 is configured, the RS-422
drivers won't be enabled (TCLK_ is not active before
the configure command). See Figures 28, 29 for the
complete circuit.

5.3 RECEIVE PATH
The signal coming from the HUB over the twisted pair
wire is received on the StarLAN board through a 1000.
line termination resistor and a pulse transformer. The
pulse transformer is of the same type as for the transmit
side and its function is dc isolation. The received signal
which is differential and almost sinusoidal is fed to the
Am26LS32 RS-422 receiver. As seen from Figure 38
the pulse transformer feeds two RS-422 receivers. The
one on the bottom is for squelch filtering and the one
above is the real receiver which does real zero crossing
detection on the signal and regenerates a square digital
waveform from
the sinusoidal signal that

~0-uuu-

is received. Proper zero crossing detection is very essential; if the edges of the regenerated signal are not at zero
crossings, the resulting signal may not be a proper
Manchester encoded signal (self introduced jitter) even
if the original signal is valid Manchester. The resistors
in the lower receiver keep its differential inputs at a
voltage difference of 600 mY. These bias resistors ensure that the output remains high as long as the input
signal is more than -600 mY. It is very important that
the RxD pin remains HIGH (not LOW or floating)
whenever the receive line is idle. A violation of this may
cause the 82588 to lock-up on transmitting. Remember,
that based on the signal on the RxD pin, the 82588
extracts information on the data being received, Carrier
Sense and Collision Detect. This squelch of 600 mY
keeps the idle line noise from getting to the 82588. Figure 39 shows that when the differential input of the
receiver crosses zero, a transition occurs at the output.
It also shows that if the signal strength is higher than
-600 mY, the output does not change. (This kind of
squelching is called negative squelching, and it is done
due to the fact that the preamble pattern starts with a
going low transition). Note that the differential voltage
at the upper receiver input is zero when the line is idle.
The output of the squelch goes to a pulse stretcher
which generates an envelope of the received frame. The
envelope is a receive enable signal and is used to AND
the signal from the real zero crossing receiver before
feeding it to the RxD pin of the 82588.

-----------uY.>L
18-22
TX - FAST CLOCKS

RS-422ENABLE------,~)___· ____________________________________C_EL_L__~!

231422-83

Figure 37. Idle Generation

1-452

AP-236

FILTERING OF
HIGH FREQUENCY NOISE

:1]ll y· ~-r---t----------------.

DATA

TERMINATION

300.(1

300.(1
TIME
SQUELCH

ENVELOPE
IDLE
DETECT

CARRIER

(OPTIONAL)

--------~

INPUT-""'="I
DATA

CARRIER -

_ _ _ _ _ _....
3 EDGES

1 .6 JLs

Figure 38. Input Ports

600
400

«--'
>=
z
W

200
mV

....

I>:

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0
-200

-400

........
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I>:

-600

WQ.

....I>: -

FILTERED-OUT
BY SQUELCH

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VOL~!

LfU

_ _ _ _ _ _ _ _ _ _ ___

....

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Figure 39. Squelch Circuit Output

1-453

231422-35

231422-84

intJ

AP-236

5.4 80188 Interface to 82588

5.5 iSBX Interface to StarLAN

Although the 82588 interfaces easily to almost any
processor, no processor offers as much of the needed
functionality as the 80186 or its 8 bit cousin, the 80188.
The 80188 is 8088 object code compatible processor
with DMA, timers, interrupt controller, chip select logic, wait state generator, ready logic and clock generator
functions on chip. Figure 40 shows how the 82588, in a
StarLAN environment interfaces to the 80188. It uses
the clock, chip select logic, DMA channels, interrupt
controller directly from the 80188. The interface components' between the CPU and the 82588 are totally
eliminated.

Figure 41 shows how to interface the 82588 in a StarLAN environment to the iSBX bus. It uses 2 DMA
channels-tapping the second DMA channel from a
neighboring iSBX connector. Such a board can be used
to make a StarLAN to an Ethernet or a SNA or DECNET gateway when it is placed on an appropriate SBC
board. It may also be used to give a StarLAN access to
any SBC board (with an iSBX connector) independent
of the type of processor on the board.

1-454

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231422-86

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AP-236

6.0 THE Star LAN HUB

6.1 A StarLAN Hub for the IBM/PC

The function of a StarLAN HUB is described in section
2.0. Figure 42 shows a block diagram of a HUB. It
receives signals from the nodes (or lower level HUBs)
detects if there is a collision, generates the collision
presence signal, re-times the signal and sends it out to
the higher level HUB. It also receives signals from the
higher level HUB, re-times it and sends it to all the
nodes and lower level HUBs connected to it. If there is
no higher level HUB, a switch on the HUB routes the
upstream received signal down to all the lower nodes.
The functions performed by a HUB are:

Figure 43 shows the implemention of a 5/6 port HUB
for the IBM/PC.
The idea of the following design is to show a HUB that
plugs into the IBM/PC backplane. This HUB not only
gets its power from the backplane, but also enables the
host PC to be one NODE into the StarLAN network.
This embedded node scheme enables further savings
due to the fact that all the analog interface for this port
is saved (receiver, transmitter, transformer, etc).
This kind of board would suit very much a small cluster topology (very typical in departments and small offices) where the HUB board would be plugged into the
FILE SERVER PC (PC/XT, PC/AT).

'Receiving signals, squelch
• Carrier Sensing
'Collision Detection
'Collision Presence Signal Generation
'Signal Retiming
'Driving signals on to the cable
'Jabber Function
'Receive protection Timer

The HUB design doesn't implement the Jabber and the
protection timers as called by the !BASES draft standard. Those functions are optional and were not closed
during the writing of this AP-NOTE. This HUB does
implement the RETIMING circuit which is an essential requirement of StarLAN.
Figures 44 to 49 show a complete set of schematics for
the HUB design.

TRANSMIT PAIR

~II

SQUELCH

+
CARRIER
SENSE

~II
TRANSMIT PAIR

RECEIVE PAIR

COLL.oET.

+
+

RECEIVE PAIR

PROTECTION
TIMER

HHUB

IH~""B----IL..-R_h_IG_I~_~;_G_KJ:JII~·

~II
~II

TO HIGHER
LEVEL HUB

JABBER

#N
231422-40

Figure 42. StarLAN HUB

1-457

inter

AP-236

PHONE JACKS

231422-87
• Low Cost HUB, Uses IBM/PC Power Supply
• 82588, Embedded Port Savings

Transformers
422 Drivers
• Functional StarLAN Cluster, For Low CoslISmall Topologies

Figure 43. IBM/PC Resident HUB

1-458

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231422-90

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231422-93

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AP-236

The time squelch for the NODE board is implemented
by the 82588 (see section 3.7) this circuit makes sure
that pulses that are shorter than a specified duration
will be filtered out.

6.1.1 HUB INPUT PORTS

Figure 38 shows a block diagram of an input port. Differently than the implementation in Figure 29 the HUB
input port is potentially more complex than the NODE
input port. The reason being that the HUB is a central
resource and much more sensitive to noise. For example, if the NODE input port would falsely interpret
noise on an IDLE line as valid signal, the worst case
situation would be that this noise would be filtered out
by the 82588 time squelch circuitry, on the HUB by the
other hand, this false carrier sense could trigger a COLLISION and a good frame (on another input) potentially discarded.

The other components of the block diagram were explained in section 3.0.

As shown in Figure 38 immediately after the termination resistor, there is a HIGH FREQUENCY FILTER
circuit. The purpose of this circuit is to eliminate high
frequency noise components keeping noise jitter into
the allocated budget (about ± 30 ns). A 4 MHz two
pole butterworth filter is being recommended by the
IEEE 802.3 lBASE5 task force (see Figure 50).

The HUB design doesn't implement the HIGH FREQUENCY FILTER and TIME SQUELCH. In the
HUB design as an output of each input port, two signals are available: Rn, En, (RA, RB ... , EA, EB ... ).
The Rn signals are the receive data after the zero crossing receivers. The En lines are CARRIER SENSE signals. The HUB design supports either 5 or 6 input
ports, dependent upon if it is configured as IHUB or
HHUB. Port RE, EE (Figure 49) is bidirectional, configurable for either input or output. Port RF, EF_ is
the embedded 82588 port, and doesn't require the analog circuitry (EF is inverted, being generated from the
RTS_ signal).

RXVE~R_ _......_ _ _ _ _ _ _ _·..,11f

i 110~ XX ~:~TED
231422-94

Figure 50. Receiver High Frequency Filter

1-465

AP-236

6.1.2 COLLISION DETECTION

Rn and En signals from each channel are fed to a .16L8
PAL, where the collision detection function is performed.

Collision Detection in the StarLAN HUB is performed
by detecting the presence of activity on more than one
input channels. This means if the signal En is active for
more than one channel, a collision is said to occur. This
translates to the PAL equations:

COLLISION DETECTION:
CDT

.! (EA & IEB & lEC & lED & lEE & EF_ #
! EA & EB & !EC & lED & lEE & EF_ #
! EA & IEB & EC & lED & !EE & EF_ #
I EA& IEB& IEC& ED & !EE& EF_ #
! EA& IEB& !EC&lED&EE&EF_ #
! EA & !EB & !EC& lED & lEE & !EF_ #
lEA & IEB& !EC & lED & lEE & EF_);

(only EA active)
(only EB active)
(only Ee active)
(only ED active)
(only EE active)
(only EF active)
(none of the inputs active)

COLLISION DETECTION SR-FF:
COLLEN_

! (CDT # COLLEN );

COLLEN_

! ( RESET_ # COLLEN_ #
.
( ICDT & lEA & !EB & !EC & !ED & !EE & EF_);

(set with collision)

( reset when all inputs inactive)
RECEIVE DATA OUTPUT:
RCVDAT

(

(RA#!EA)&(RB # IEB)&(RC # !EC)&
(RD # IED)&(RE # lEE) & (RF # EF_»;
( output is high if no active input)

1-466

AP-236

Manchester encoding. Section 3.5 shows that the CPS
has missing mid-cell transitions occurring every two
and a half bit cells. These are detected as Manchester
code violations. Thus, the StarLAN node is presented
with collision detection indications every two and a half
ms. This results in fast and reliable detection of collisions. CPS has a period of 5 ms.

The COLLEN signal once triggered will stay active until all inputs go quiet. This signal is used externally to
either enable passing RCVDAT or the collision presence signal (CPS) to the retiming logic. An external
multiplexer using 3 nand gates is used for this function.
Note that in this specific implementation the CPS/
RCVDAT multiplexer is before the retiming logic,
which is different from Figure 42 diagram. StarLAN
provides enough BIT-BUDGET delay to allow the CPS
signal to be generated through the retiming FIFO. In
this HUB implementation it was decided to use this
option to make sure that the CPS startup is synchronized with the previously transmitted bit as required by
the !BASES draft.

One may wonder why such a strange looking signal was
selected for CPS. The rationale is that this CPS looks
very much like a valid Manchester signal----edges are
0.5 or 1.0 microsec. apart-resulting in identical radiation, cross-talk and jitter characteristics as a true Manchester. This also makes the re-timing logic for the signals simpler-it need not distinguish between valid
Manchester and CPS. Moreover, this signal is easy to
generate.

6.1.3 THE LOCAL 82588
As described before, the purpose of the local 82588 is to
enable the Host IBM/PC to also be anode into the
StarLAN network. The interface of this 82588 is exactly similar to the one explained in section 5. The RTS_
signal serves as the carrier EF_ signal, and TXD as
RF signal. This local node interfaces to the HUB without any analog interface which is a significant saving.

6.1.4 THE COLLISION PRESENCE SIGNAL
The Collision Presence Signal (CPS) is generated by the
HUB whenever the HUB detects a collision. It then
propagates the CPS to the higher level HUB. The CPS
signal pattern is shown in Figure 51. Whenever a StarLAN node receives this signal, it should be able
to detect within a very few bit times that a collision
occurred. Since the nodes detect the occurrence of a
collision by detecting violations in Manchester encoding, the CPS must obviously be a signal which violates

A few important requirements for CPS signal are: a) it
should be generated starting synchronized with the last
transmitted bit cell. CPS is allowed to start either low
or high, but no bit cell of more than I microsecond is
allowed (Avoid false idles, very long "low" bits). b)
once it starts, it should continue until all the input lines
to the HUB die out. Typically, when the collision occurs, the multiplexor in the HUB switches from RCV
signal to the CPS. This switch is completely asynchronous to the currently being transmitted data, and by
such may violate the requirement of not having bit cells
longer than I p.s. In order to avoid those long pulses,
the output of the CPS/RCVDAT multiplexer is passed
through the retiming circuitry which will correct those
long pulses to their nominal value. The reason for restriction b) is to ensure that the CPS is seen by ali Hodes
on the network since it is generated up.til every node
has finished generating the Jam pattern.

2t I t I 2t I 2t I t i t = 0.5 j.LS
r--5j.Ls PERIOD-i
• MISSING MID-CELL TRANSITION

231422-42

• Collision Presence Signal (CPS) is generated by the HUB when it detects more than one input line active.
• CPS violates Manchester encoding rules-due to missing mid-cell transitions-hence is detected as a collision by the DTE (82588).
Choice of Collision Presence Signal
• It is a Manchester look-alike signal----edges are 0.5 or 1.0 p.s apart.
- Identical radiation, crosstalk and jitter characteristics
- Eases retiming of the signal in the HUB
• It is easy to generate-1.5 TTL pack, or in a PAL
Figure 51. Collision Presence Signal

1-467

inter

AP-236

a result of jitter, may no longer be decodable. The process of either re-aligning the edges or reconstructing the
signal or even re~generating the signal so that it once
again "looks new" is called re-timing. StarLAN requires for the signal to be re-timed after it has travelled
on a segment of cable. In a typical HUB two re-timing
circuits are necessary; one for the signals· going upstream towards the higher level HUB and the other for
signals going downstream towards the nodes.

CPS is generated using a 4-bit shift register and a flipflop as shown in Figure 52. It works off a 2 MHz clock.
A closer look at the CPS waveform shows that it is
inverse symmetric within the 5 J.l.s period. The circuit is
a 5-bit shift register with a complementary feedback
from the last to the first bit. The bits remain in defined
states (01100) till collision occurs. On collision the bits
start rotating around generating the pattern of
001l011001, 0011011001, 00110 ... with each state
lasting for 0.5 J.l.s.

6.1.6 RETIMING CIRCUIT, THEORY OF
OPERATION

o
COLLISION
r-......- " ' I PRESENCE
SIGNAL
Q

COLLISION

231422-43

Figure 52. Collision Presence
Signal Generation
6.1.5 SIGNAL RETIMING
Whenever the signal goes over a cable it suffers jitter.
This means that the edges are no longer separated by
the same 0.5 or 1.0 J.l.S as at the point of origin. There
are various causes of jitter. Drivers, receivers introduce
some shifting of edges because of differing rise and fall
times and thresholds. A random sequence of bits also
produces a jitter which is called intersymbol interference, which is a consequence of different propagation
delays for different frequency harmonics in the cable.
Meaning short pulses have a longer delay than long
ones. A maximum of 62.5 ns of jitter can accumulate in
a StarLAN network from anode to a HUB or from a
HUB to another HUB. The following values show what
are the jitter components:
Transmitter skew
Cable Intersymbol interference
Cable Reflections
Reflections due to receiver
termination mismatch
HUB fan-in, fan-out
Noise
Total

± 10 ns
±9 ns
± 8 ns

±5 ns
±5 ns
±25.5
±62.5 ns

It is important for the signal to be cleaned up of this
jitter before it is sent on the next stretch of cable because if too much jitter accumulates, the signal is no
longer meaningful. A valid Manchester signal would, as

This section will discuss the principles of designing a
re-timing circuit. Figure 53 shows the block diagram of
a re-timing circuit. The data corning in is synchronized
using an 8 MHz sampling clock. Edges in the waveform
are detected doing an XOR of two consecutive samples.
A counter counts the number of 8 MHz clocks between
two edges. This gives an indication of long (6 to 10
clocks) or short (3 to 5 clocks) pulses in the received
waveform. Pulses shorter than 3 clocks are filtered out.
Every time an edge occurs, the length-(S)hort or
(L)ong-of the pulse is fed into the FIFO. Retiming of
the waveform is done by actually generating a new
waveform based on the information being pumped into
the FIFO. The signal regeneration unit reads the FIFO
and generates the output waveform out of 8 MHz clock
pulses based on what it reads, either short or longs. In
summary every time a bit is read from the fifo, it indicates that a transition needs to occur, and when to fetch
the next bit. When idle the output of the retiming logic
starts with a "high" level.
FIFO
empty

S
S
L
L

Output
...... 1111
0000
1111
00000000
11111111

It can be seen that the output always has edges separated by 4 or 8 clock pulses--{).5 or 1.0 J.l.s.

The FIFO is primarily needed to account for a difference of clock frequencies at the source and regeneration
end. Due to this difference, data can corne in faster or
slower than the regeneration circuit expects. A 16 deep
FIFO can handle frequency deviations of up to 200
ppm for frame lengths up to 1600 bytes. The FIFO also
overcomes short term variations in edge separation. It
is essential that the FIFO fills in up to about half before
the process of regeneration is started. Thus, if the regeneration is done at a clock slightly faster than the
source clock, there is always data in the FIFO to work
from. That is why the FIFO threshold detect logic is
necessary, which counts 8 edges and then enables the
signal regeneration logic.

1-468

inter

AP-236

Example:
Input Waveform

... 11110001111000000011111111110001111100 ...

Input into
the FIFO

<5> <5>

<5>

Regenerated Output:
... 111110000111100000000111111110000111 ...
Output:
FIFO:
I
I
I
I
I
I

<5> <5>

INPUT
DATA

INCREMENT EDGE !
COUNTER

• 1'11'o ACCOMMODATES FOR FREQ •
OR1m (SPEC 100 PPM)
• lolAX DRIFT:
(1 500 BYTES x B) x 200 PPM

<5> <5>

EDGE
DETECTOR

SYNCHRONIZER

BMHztLOCK

PULSE WIDTH
DISCRIMINATOR

LOAD!
FIFO

FIFO
THRESHOLD
DETECT

=2.43 BT

SHORT/LONG
INFO

FIFO

FIFO OUTPUT
ENABLE SIGNAL
REGENERATION

SIGNAL
REGENERATION

~ OUTPUT
231422-95

Figure 53. Retiming Block Diagram

6.1.7 RETIMING CIRCUIT IMPLEMENTATION
The retiming circuit implementation can be seen in Figures 47, 48. Both figures implement exactly the same
function, one for the upstream, and the other for the
doWnstream. The retiming circuit was implemented using about 8 SSI, MSI TTL components, one fifo chip
and one PAL. The purpose of implementing this function with discrete components was to show the implementation details. The discussion of the implementation will refer to Figure 47 for uni~ numbers.
The signal UPIMP which is an output of the HUB
multiplexing logic, is asynchronous to the local clock.
This signal is synchronized by two flip-flops and fed
into an edge generation logic (basically an XOR gate
that compares the present sample with the previous
one). On every input transition a 125 ns pulse will be

generated at the output of the edge detector (U28). This
pulse will reset the 74LS161 counter that is responsible
for measuring pulse widths (in X8 clock increments);
The output of the pulse discriminator will reflect the
previous pulse width every time a new edge is detected.
The following events will take place on every detected
edge:
1. U26 which is the threshold detector will shift one
"I" in. The outputs of U26 will be used by the control PAL to start the reconstruction process.
2. The output of U23 which specifies the last pulse
width will be input into the control PAL for determining if it was a long or short pulse. The result of
this evaluation will be the LSIN signal which will be
loaded into the fifo (U22).
U22 is the retiming FIFO, it is 16x4 fifo, but only one
bit is necessary to store the SHORT/LONG informa~
tion.

1-469

AP-236

CONTROL LOGIC PAL functions (U25):

CNTTC:

Signals definition:
INPUTS:
PDO.. PD3:

EDD_:

THRESH:
CNTEN:

CNTEND:
OUTDAT:

OR:
Outputs of the pulse descriminator, indicate the width of the last measured
pulse.
Output of the edge detector, pulse of 125
ns width, indicates the occurrence of an
edge in the input data.
Output of the threshold logic, indicates
at least one bit was already received.
Output of the Threshold logic, indicates
7 bits have been loaded into the FIFO,
and that signal reconstruction can begin.
The same signal as before delayed by one
clock.
Output of the retiming logic, is feedback
into the PAL to implement a clocked
T-FF.
Resets the retiming logic.

LDFIFO_

OUTPUTS:
LDFIFO_:

ODAT:

Terminal count of the reconstruction
counter, indicating that reconstruction
of a new bit will get started.
Output of the FIFO indicating, that the
FIFO is empty and that IDLE generation can get started.
Loads SHORT/LONG indications into
the FIFO.
Indicates SHORT/LONG
Loads FIFO SHORT/LONG output
into the reconstruction counter.
Together with the external U21 flill-flop
and OUTDAT implement a clocked
T-FF.

Loading the FIFO will be done every time there is an
edge, we have passed the one bit filter threshold level,
and the pulse width is longer than two 8X clocks. This
one bit threshold level serves as a time domain filter
discarding the first received preamble bit.

( PDl # PD2 # PD3 ) &:

!EDD_ &: THRESH ) ;

Whenever there is an edge, we are above the first received bi t threshold
and the pulse width is longer than "1" the fifo is loaded.

LSIN,

(PD2 &:

! (PD3 #

PD~)

(PD2 &: PD1))

Every pulse longer than 6 is oonsidered to be a long pulse.

CNTPE_

((CNTEN &:

!CNTEND)

CNTTC);

The reconstruction counter is loaded in two conditions:

Whenever CNTEN oomes aoti ve. meaning the FIFO threshold ~f seven was exoeeded.
Whenever the terminal oount of U24is aotive meaning a new pulse is going to be reoonstructed.

ODAT

= !RESET_

#
#

iff

(!CNTPE_ &:
( CNTPE_ &:
(!CNTPE_ &:

!OUTDAT)
OUTDAT)
lOR)

(A)
(B)

(Cl

Minterm (A) and (B) implement a T-FF. whenever CNTPE, is "low"
ODAT will toggle. The external U2l is part of this flip-flop.
Minterm (C) insures the output o,f the flip-flop will go inaotive
"high' when the FIFO is empty. RESET, oauses the output to go
"high' on ini tialization.

1-470

inter

AP-236

U24 as mentioned is the reconstruction counter. This
counter is loaded by the control logic with either 8 or
12, it counts up and is reloaded on terminal count. Essentially generating at the output nominal length longs
and shorts.
U22 is the retiming FIFO, and its function as mentioned is to accommodate frequency skews between the
incoming and outgoing signal.
U27 is the IDLE generation logic. The purpose of this
logic is to detect when the FIFO is empty, meaning that
no more data needs to be transmitted. On detection of
this event this component will generate 2 ms of IDLE
time. On the end of IDLE the whole retiming logic will
be reset.
6.1.8 DRIVER CIRCUITS

The signal coming out of the RETIMING LOGIC is
fed into 26LS30s and pulse transformers to drive the
twisted pair lines (See section 5.0 for details).
6.1.9 HEADER/INTERMEDIATE HUB SWITCH

As seen on Figure 43 this hub can be configured as
either an intermediate hub, or a Header one. One of the
phone jacks, more specifically JACK #5 is either an
input port or an output one. In order to implement this
function, an 8 position DIP SWITCH (SWl) is used.
The phone jacks are marked with UD, DO notation,
meaning upstream data, and downstream data respectively. As specified in the StarLAN !BASES draft
NODES transmit data on UD pair, and HUBS on the
DO pair. Switch SWI has the function to invert UD,
DO in PHONE JACK # 5 to enable it to be either
input or oiltput port.

will be started, and Tl will time out after 25 to 50 ms.
T2 will time-out after 51 to 100 ms. During T2 time,
after T1 expired, the HUB will send the CP-PATTERN informing any jamming stations to quit their
transmissions. If on T2 time-out there are still jamming
ports, their input is going to be disabled. A disabled
port, will be reenabled whenever its input becomes
again active and the downward side is idle.
The following is an .explanation of the requirement that
the downward side be idle to reenable an input port.
Consider the case of Figure 54. The figure shows a two
port HUB. Port A has two wires Au, Ad for the up and
down paths. Port B has Bu, Bd respectively. Port C is
the output port, that broadcasts to the other HUBs
higher in the hierarchy. Consider the case as shown,
where Bu and Bd are shorted together. Suppose the case
that port Au is active. Its signal will propagate up in the
hierarchy through Cu and come down from Cd to Ad,
and Bd. Due to the short between Bd and Bu the signal
will start a loop, that will first cause a collision and jam
the network forever. This kind of fault is taken care of
by the jabber circuitry. T1 and T2 will expire, causing
the jabber logic to disable Bu input. Upon this disabling
Bu is going to go Idle and be a candidate for future
enabling. Suppose now that Au is once again active. If
the reenable condition would not require Cd to be
IDLE, Bu would be reenabled causing the same loop to
happen once again. Note that in this case Cd will be
active before Bu causing this port to continue to be
disabled and avoiding the jamming situation (Figure
55) gives a formal specification of the jabber function).

6.1.10 JABBER FUNCTION

This design does not implement the jabber unit but it is
described here for completeness. IEEE 802.3 does not
mandate this feature, but it is "Strongly Recommended". The jabber function in the HUB protects the network from abnormally long transmissions by any node.
Two timers Tl, T2 are used by the JABBER function.
They may be implemented either as local timers (one
for each HUB port) or as global timers shared by all
ports. Mter detecting an input active, timers Tl, T2

1-471

231422-96

Figure 54. Jabber Function

AP-236

Power On

.J,
_____ ~~B.fI!.IE~ _____

+- Walt for Input active.
INPUT (X) ; actlv.

I
-l~

____

1A..B~E!l ~~TEI!

____

_ starLJobberTime 1

+- Input Is active, activate timers Tl, T2 .

• start_Jobber Time 2

INPUT (X) ; Idl.

If Input goes Idle. then It was a
normal transmission. Otherwise If
jobber Timer 1 expires. the transmission
Is Illegal. Start generating collision
pattern In stote JABBER JA~.

Jabber Time Ldone • INPUT (X) ; active

_____ ~~B..E~ -loA!:! _____
• jobber_collision

---, probatlon_olternotlve

.INPUT (X) ; Idle

+- Varlobl. probatlon_olternotlve Indicates

two possible ways of Implementing the function.
Implementation of either one is allowed.

«(jabb.rTIm. 2-don. + INPUT(UPPER); Idle)
.INPUT(X) ; active
+ (probation alternatlv. * INPUT (X); Idl.)

Conditions for going to state JABBER SHUTOFF
..;. T2 expires.

JABBER SHUTOFF
;db;bi..:in-p~t (xi - - - - - - -

INPUT (X) = act Iv•• INPUT(UPPER); active

-INPUT(UPPER) = Idl•• INPUT (X) = activo
It means thot the current HUB was
SHUTOFF by a higher hierarchy one.
This one will also SHUTOFF with the
purpo~e that a Jammi!'19 Input be
DISABLED at the lowest possible level.

INPUT (X) ; Idle

-INPUT(X)

JABBER PROBATION

=Idle

Two alternatives are allowed:

;dba-bi..:in-p~t (Xi - - - - - - -

Go bock to JABBER IDLE. or

go to the SHUTOFF .tat••

I INPUT (x) =active .INPUT(UPPER) =Idl.

On state JABBER SHUTOFF. the
Input Is disabled.

' - - - Input

will be reenabled If Input Is active.
and the upper port Is quiet.

231422-99

Figure 55. Jabber State Diagram
6.1.11 HUB RECEIVER PROTECTION TIMER

On the end of a transmission, during the transition
from IDLE to high impedance state, the transmitter
will exhibit an undershoot and/or ringing, as a consequence of transformer discharge. This undershoot!
ringing will be transmitted to the receiver which needs
to protect itself from false carriers due to this effect.
One way of implementing this protection mechanism is
to implement a blind timer, which upon IDLE detection will "blind" the receiver for a few microseconds.
Causes of the transmitter undershoot/ringing:
1. Difference in the magnitudes of the differential output voltage between the high and the low output
stages.
2. Waveform assymmetry due to transmitter jitter.
3. Transmitter and receiver inductance (transformer
L).

All the describ~d elements will contribute to energy
storage into the transformer inductor, which will discharge during the transition of the driver to high impedance.
The blinding timer is currently defined to be from 20 to
30 microseconds for the HUBs, being from 0 to 30 microseconds for the nodes (optional). The 82588 has
built-in this function. It won't receive any frames for an
inter-frame-spacing (IFS) from the idle detection.
6,1.12 HUB RELIABILITY

Since the StarLAN HUBs form focal points in the network, it is important for them to be very reliable, since
they are single points of failure which can affect it number of nodes or can even bring down the whole network. StarLAN lBASE5 draft requires HUBs to have
a mean time between failures (MTBF) of at least 5
years of continuous operation.

4. Two to three microseconds of IDLE pattern.

1-472

inter

AP-236

7.0 SOFTWARE DRIVER

7.1.1 DOING I/O ON IBM PC

The software needed to drive the 82588 in a StarLAN
environment is not different from that needed in a generic CSMAlCD environment. This section goes into
specific procedures used for operations like TRANSMIT, RECEIVE, CONFIGURE, DUMP, ADDRESS
SET-UP, etc. A special treatment will be given to interfacing with the IBM PC-DMA, interrupt and I/O.

The safest way to use the PC monitor as an output
device and the keyboard as the input device is to use
them through DOS system calls. The following is a set
of routines which are handy to do most of the I/O:
key$stat
-to find out if a new key has been
pressed
keyin$noecho -to read a key from the keyboard
char$out
-to display a character on the screen
msg$out
-to display a character string on the
screen
line$in
-to read in a character string from the
keyboard

Since all the routines were written and tried out in
PLM-86 and ASM-86, all illustrations are in these languages.
The following software examples are pieces of an 82588
exerciser program. This program's main purpose was to
exercise the 82588 functionality and provide the functions of traffic generation and monitoring. By such the
emphasis was on speed and accuracy of statistics gathering.

7.1 Interfacing to IBM PC
The StarLAN board interfaces to the CPU, DMA controller and the interrupt controller on the IBM PC system board. The software to operate the 82588 runs on
the system board CPU. The illustrated routines in this
section show exactly how the software interface works
between the system resources on the IBM PC and the
StarLAN board.

lds dX,STRING_POINTER
mov ah,09h
int 2lh

The exact semantics and the protocol for doing these
functions through DOS system calls is shown in the
listing in Figure 56. Refer to the DOS Manual for a
more detailed description. To make a DOS system call,
register AH of 8088 is loaded with the call Function
Number and then, a software interrupt (or trap) 21 hex
is executed. Other 8088 registers are used to transfer
any parameters between DOS and the calling program.
The code is written in Assembly language for register
access. Let us see an example of the 'msg$out' routine:

load pointer to string in reg. ds:dx
9 = function number for string o'p
DOS System Call

These procedures are called from another module, written in a higher level language like PLM-86. The parameters
are transferred to the ASM-86 routines on the stack.
Examples of using the I/O routines:

*'*'*'
"'*'

INQUIRE KEYBOARD STATUS
INPUT NEW KEY
STRING INPUT
TO OUTPUT CHAR_OUT ON SCREEN",
OUTPUT STRING
/* NOTE $ TERMINATOR

KEY_STATUS
key$stat;
"
NEW_KEY = keyin$noecho;
/*
call line$in(@LINE_BUFFER) ;
call char$out(CHAR_OUT) ;
call msg$out(@('THIS IS A MESSAGE.$')); /*

,*,*

1-473

inter

AP-236

/ ------ --------- ---------- --------------- ---------------------------------_ /
1*
Declarations for external IBM PC 110 routines
*/

I" --------------------------- ______ .;.. _________ . . :. ______________________________ .. /

keySstat: prooedure byte external:
end keySstat:

/.. key status routine .. /

~~aSi:~s~~~~~~c~~~oedure byte external:
charSout: procedure(ohar) external:
deolare char byte:
end charS out:

/$ oonsole input routine .. I

I' oonsole output routine ' I

msgSout: procedure(msgSptr) external:
declare msgSptr pOinter:
end msgSout:

/' oonsole string output routine

l1neSin: procedure(lineSptr) external:
deolare l1neSptr pOinter:
end l1neSin:

I' console string input routine

Assembly Language implementation of the routines
STITLB(IBlI/PC

DOS CALLS PROCEDURES)

NAIIE

OOROUP

DOSPROCS

CGROUP

GROUP
GROUP

DATA
DATA

SEGIlENT WORD PUBLIC 'DATA'
ENDS

Dos

EQU

CoDE

DATA
CODE

21H

SEGIIENT WORD PUBLIC 'CODE'
ASSOIIE CS: CGROUP, DS :DGROUP

231422-58

CHAR$OUT: PROGEDURE(CHAR) EXTERNAL;
DECLARE CHAR BYTE:
END CHAR$OUT;
Outputs character to the screen,
DOS system call 2
EQU
CHAROUT

CHAROUT

PUBLIC
PUSH
MOV
MOV
MOV
INT
POP
RET

[BP+41

PROG
NEAR
CHAROUT
BP
BP,SP
DL,CHAR

AH,2

DOS
BP

STACK
+------+
! CHAR ! X
+------+

lIP 10 ! x-I
+------+
! IP hi ! x-2
+------+

IBP 10 ! x-3

+------+

!BP hi I x-4

ENDP

<--SP

+------+

'KEYIN$NOECHO: PROCEDURE BYTE EXTERNAL;
END KEYIN$NOECHO;
Reads character without echoing to display
KEYINNOECHO PROG
PUBLIC
MOV
INT
RET
KEYINNOECHO ENDP

NEAR
KEYINNOECHO

AH,a
DOS

(DOS call a)

Figure 7-56. I/O Routines for IBM/PC

(continued)
231422-59

Figure 56. 1/0 Routines for IBMIPC

1-474

inter

AP-236

MSGSOUT: PROCEDURE(MSGSPTR) EXTERNAL,
DBCLARE MSGSPTR POINTBR,
END MSGSOUT,
f' NOTB: MESSAGB IS TERMINATED WITB A DOLLAR SIGN ' f
MSGSPTR :1.s double word painter SEG;OFFSET

PUBLIC

EQU
EQU

[BP+41
[BP+61

PROC
MSGOUT

NEAR

PUSH
MOV
MOV
PUSH
MOV
MOV
MOV
INT
POP
POP
RBT

BP
BP.SP
DX.MSG_L
DS
AX. MSG_H
DS.AX
AH.9
DOS
DS
BP

(DOS call 9)

MSGOUT

ENDP

LINE$IN: PROCBDURE(LlNESPTR) EXTERNAL,
DECLARB LINE S PTa POINTER,
END LINE $IN
LINE_L
LINE_H

EQU
BQU

I.INEIN
PUBLIC
FUSH
MOV
FUSH
MOV
MOV
MOV
MOV
INT
POP
POP
RET
LINEIN

[BP+41
[BP+61

PROC
NEAR
LINEIN
BP
BP.SP
DS
AX.LINE_H
DS.AX
DX.LINE_L
AH.10
DOS
DS
BP

(DOS call 10)

BNDP

231422-60

KEYS STAT; PROCEDURE BYTE EXTERNAL,
END KllYSSTAT,

Indioates whether any keyboard key was pressed.
KllYSTAT
PUBLIC
MOV

INT
RET
XBYSTAT

PROC
NEAR
XBYSTAT
AH.ll
DOS

(DOS oall 11)

ENDP

ConB

ENDS
END

231422-61

Figure 56. 1/0 Routines for IBMIPC (Continued)

7.2 Initialization and Declarations
Figure 57 shows some declarations describing what addresses the devices have and also some literals to help
understand the other routines in this section.

Figure 58 shows the initialization routines for the IBM
PC and for the 82588. It also shows some of the typical
values taken by the memory buffers for Configure,
lA_Set, Multicast and transmit buffers.

1-475

AP-236

Following are some literal declarations that are used in the procedure examples
Following are some 11teral
prooedure sZlLIIlples
deolare

declarations

that

are

used

the

l1ter&l.ly '0300h' , ,. 82588 OOXIIAlID'B'rA'l'11S
.,
l1ter&l.ly '0301h'
,. DIIA'IIiTliRUPT DAlILB PORT
.,
l1ter&l.ly '021h'
,. 82aBA 1lASB: RllGISTBR
.,
11ter&l.ly '02Ch'
,. 825BA 00XIIAlID WOlIIl 2
.,
11ter&l.ly 'Oab.'
,. 8237A IlASB: RllGISTBR'
.,
11ter&l.ly 'Obh'
,. 8237A IIODl! RllGISTBR
.,
l1ter&l.ly 'Coh'
,. 8237A lST'2ND BYTB PLOl'
.,
l1ter&l.ly 'OSh'
,. 8237A ClIAlIlII!Io 1 AIlIlR; RIIG • • ,
l1ter&l.ly 'OISh'
,. 8237A 'CIIAlIIIBI. 1 BYTB C01llIT .,
11ter&l.ly '081Sh'
,. CIL\lIlIBL 1 PAG!! RBGIS'l'BIl
.,
l1ter&l.ly '08h'
8237A CIIAlIIIBI. 3 AIlIlR. RIIG • • ,
11ter&l.ly '07h'
,. 8237A CIL\lIlIBL 3 BYTB C01llIT .,
11ter&l.ly ,'08Sh'
,'* CIIAlIIIBI. 3 PAGB RllGIS'l'BIl
.,
11ter&l.ly 'Olh'
START CIL\lIlIBL 1
l1ter&l.ly 'OISh'
START CIIAlIIIBI. 3
11ter&l.ly 'OSh'
STOP CIL\lIlIBL 1
11ter&l.ly '07h'
STOP CIIAlIIIBI. 3
11ter&l.ly 'Odfh'
UlIIIASIt IIITBRItUPT LBVIL II
11ter&l.ly '065h'
SPBCIFIC 101 LBVIL II
11ter&l.ly
'1 '
IIBIIOIIY TO 82888
11ter&l.ly
'0 '
82588 TO IIBIIORY
11ter&l.ly '045h'
,'0!IX 011 CIIAlIIIBI. t 1
°f
l1ter&l.ly '047h'
,0 !IX 011 CIIAlIIIBI.t 15
0,
11ter&l.ly '049h'
'l'l: 011 CIIAlIIIBI. t 1
11ter&l.ly '04IIh'
'l'l: 011 CIIAlIIIBI. t 3

'*
,0,0
,0

,0,0
,0
,0,0

0,0,
0,0,
0,0,0,
0,

,0,0

0,0,

231422-62

Figure 57. Uteral Declarations
Initialization Routines
Initialization routines

,0 SISTIII INITIALIZE 0,

sys_1nit: prooedure;
0&l.1 aetSinterrupt 03,intr_888);
output(p1o-,,&slt) - input(p1o-'"&8lt) aDd enable_588;
output(piCL00w2) seol-Pioo;

'*,0,0

,0
...................................................
,
,0,,0....................................................0,,

Wl'-ptr. r4..l>tr, fUoont-o;

BASE 8, LBVIL II
BNABLB 588 INTERR.
ACItS PENDING IIITBRIt
RESET STA'l'11S FIPO

*'0,
0,
*'

COlIVBRT SBG: OFl'SII'l! 1'OIIIIA'r TO 20 BIT ADI1R118SE8
FOR ALL TIll B\JFFBRS

output (brd...port)-Offh;

,0 BNABLB DIIA AND INTERRUPT DRIVERS 0,

eDd sys_init ;
821188 1D1U&l.izaUon
1nit_888: ,prooedure;
oonfig_1I88(00)
oonfill_1I88(01)
oonfil1-1188(02
oonfiIl-888(03)
OOD:!'il1_I188(04)
OOD:!'1I1_888(05)
oonfiI1-588(08)
oOD:!'iI1-588(07)
ooDf111_588(05)
o0D:!'1II-1188(09)
o0D:!'111_1188(10)
oonfill_888(11)

- 10;
- 00;
- 0000100Ob;
- bu:!':!'Jen'4;
- 0010011Ob;
- OOOOOOOOb;
- 96;
- 0;
- l1110010b;
- 000001001:>;
- 1000100Ob;
-.64;

,0 TO COlIFIGURI!, ALL 10 PARAIIETBRS

'*,0
'*,0
,0
,0,0
,0

11HZ CLOCIt. 1 1IB'8
RBCBIVB BUFFER LllNGTII
NO LOOPBACIt. AIlIlR LEN - 6, PRI!AIIBLE - 8
DIFFERENTIAL IlANCllBSTBR - OFF
fO IFS - 96 TCLIt
SLOT 'l'IJIB - 1112 TCLIt
,. IIAX. NO. 1III'l!RIES - 18
IlANCllBSTBR BNCODING
IIiTliRNAL cas AND CD'r, CRSF - 0
HIlI FRAIIII LIINGTII - 64 BYTBS - 812 BITS
IIODl! 0, 8

Figure 58. Initialization Routines
1-476

0,
0,0,
0,0,
*'
.0,0,
*'0,
0,

231422-63

inter

AP-236

j.a.set.bufC588(O)
j.a...set_buff.5880)
j.a...setJ>uff.588(2)
j.a...set_buff_588(3)
ia_set.bufC558(4)
ia_setJ>ufC588(5)
1o._set_ufC588(6)
ia...set.bufC558(7)

•
•
-

6;
0;
OOOh
041h
OOOh
OOOh
OOOh
OOOh

IDUl.tioast.bufC588(OO)
mult1oast_buff.588(Ol)
multioastJ>ufC588(02)
mult1cast_bufCBBB(03)
multioast_bufC58B(04)
multioastJ>ufCB8B(05)
mult1oast_buff_BBB(06)
multioast_bufC68B(07)
multioast_bufC5B8(OB)
multioast.bufC5BB(09)
mult1oastJ>ufC5B8(0)
mult1oast_bufC5BB(l1)
mult1oast_bufCBBB(12)
mult1oastJ>ufC5BB(l3)
txJ>uffer_BBB(OO)
txJ>uffer_5BB(Ol)
txJ>uffer_5BB(02)
tx....buffer_5B8(03)
txJ>uffer_5BB(04)
tx.buffer_5BB(05)
tx....buffer_5BB(06)
txJ>uffer_588(07)
eOO

- 12;
- OOh;
- llh;
- 12h;
- 13h;
- 14h;
- 15h;
- 16h;
- 21h;
- 22h;
- 23h;
-24h;
- 25h;
- 26h;

tx....frame.len mod 256;
tX.frame_len / 256;
Ollh;
/" INITIAL DESTINATION ADDRESS - IICO) "/
012h;
013h;
Ol4h;
015h;
016h;

inj. t_588;

231422·64

Figure 58. Initialization Routines (Continued)

7.3 General Commands
Operations like Transmit, Receive, Configure, etc. are
done by a simple sequence of loading the DMA con·
troller with the necessary parameters and then writing
the command to the 82588.
Example: Configure Command
To configure the operating environment of the 82588.
This command must be the first one to be executed
after a RESET.

call
DMA_LOAD(1,1,12,@CONFIG_588_ADDR)
output (CS_588) = 12h;
The first statement is the prologue to the configure
command to the 82588 which calls a routine to load
and initialize the DMA controller for the desired operation. This routine is described in section 7.4. The parameters for DM~LOAD are:

first parameter

= 82588 channel
number ( = 1)
second parameter = direction ( = 1,
memory > > 82588)
third parameter = length of DMA
transfer ( = 12)

fourth parameter = pointer to a 20 bit
address of the
memory buffer
(=@CONFIG_588_ADDR)
The second statement writes 12h to the command register of the 82588 to execute a Configure command on
channel I.
When the command execution is complete (successfully
or not), 82588 interrupts the 8088 CPU through the
8259A, on the system board. This executes the interrupt service routine, described in section 7.5, which
takes the epilogue action for the command.
Most operations are very similar in structure to Configure. The 82588 Reference Manual describes them in
detail. Figure 59 shows a listing of the most commonly
used operations like:

CONFIGURE
TRANSMIT
DIAGNOSE
DUMP
TDR.
RETRANSMIT

1-477

INDIVIDUAL-ADDRESS (IA)
SET-UP
MULTICAST-ADDRESS (MC)
SET-UP
RECEIVE (RCV)-ENABLE
RECEIVE (RCV)-DISABLE
RECEIVE (RCV)-STOP
READ-STATUS

Intel

AP-236

1&_set: prooedure pW>l10:

,. COIIIIAND.-- 01 .,

oall dma.J.oa4( OIIICLohaImel, tz..dir ,8 ,01&Bet_dmlLlIddr) :
,. SlIT D!!A CIIA1I1IBL 0 OR 1 ro TRANSFER nOx IIBIIORY
ro TIlE 811588. 1aset_dmlLlI44r VARIABLB S'l'OIUIS TIlE
110 BIT POIIITIIR ro TIlE IIIDIVIDt1AL AllDRBSS BUFFER ."
i f OIIICLohannel then output (OB_588) - llh:
else output(os_668) - Olh:

*'
/. -----------------------------------------------.:..--------------------------*'
,. BVBRY COIIIIAND CAN' III! BDCOTI!D IB BITIIl!R DIIA CIIA1I1IBL 0 OR 1.
TIlE VARIABLB OIIICLohaImel 11IDICATBS TllEIU!Q11IRBD ClWIBI!L

aDd 1&-.8Bt;

i·

oonf1g: procedure publ1o:

COIIIIAND - OR .,

call dmlLloa4(OIId..ohaI1I1ei, tlLdir,12,OOI1f_dmlLlIddr):
i f OIIICLohannel then output (oB_588) - lllh:
elBe output(OB_588) - Ollh:
elld ool1f1g:

/. ---------------':"'"------------..:.---7'----------~------------~~-.;..--------------.I
,. COIIIIAml - 03 .,

mUlt1oast: procedure publ1o:

call dmlLloa4(OIIICLohaImel, tz..dir,14,IImO_dmlLa4dr):
if ~ohannel then output (OB_588) - 13h:
else output (OB_588) - OSh:
elld mUl t10&Bt :
1 ..-----...:_-----------... ---------------------------------______________________ * /
tranBmit: prOoedure(buffe~-len) pUbl1o:
,

,. COIIIIAND - 04 .,

deolare buffer_len WO:rd:
tlLbuffer_588(00) - low(buffer_len):
tZ-buffer_B88(01) - high(huffer_len):
call dma.J.oa4(OIIICLohaI1I1el, tlLdir, 1636 ,otlLdmlLlIddr):
if OIIICLohaI1I1el then output (OB_588) -14b::
else output (os_588) ,- 04b::
slid tranBmi t :

231422-65

Figure 59; General Commands

1-478

AP-236.

tdr: prooedure publio:

/' COIIIIAIiD -

i f OlIId.-ohannel then output (os_58B) - 15h:

slse output(os_5BB) - 05h:

end tdr:

'* -------------------------------------------------------------------------_.,

dump_B88: prooedure publ1o:

/' COIIIIAIiD - 08 '/

oall dma....load( om_ohannel. l'Z_dir. 64 .lIdmp_dma....addr) :
i f Omd..ohannel then output (os_5B8) - lBh:
else output(os_BBB) - OSh:
enci

d~p_SB8:

,. --------------------------------------------------------------------------"
diagnose: prooedure publio:

/ ' COIIIIAIiD - 07 '/

if OlIId.-ohannel then output (os_BBB) - 17h:
else output(os_B8B) - 07h:
end diagnose:

'*--------------------------------------------------------------------------* /
rov_ena.ble: prooedure(oIu!.nnel.l>uffer_no.len) publio:

/' COIIIIAIiD -. OB '/

deolare ohannel byte:
deolare len word:
deolare l>uffer_no byte:
oall dma....load(oIu!.nnel. l'Z_dir .len. ~dmlLaddr(l>uffer_no» :
i f rz...ohannel then output (os_BBS) - lBh:
else output(os_5B8) - OBh:
end rov_ena.ble:

"-------------------------------------------------------------------------_./.
rov_disa.ble" prooedure publ1o:

/ ' COIIIIAIiD - 10 '/

ena.ble_rov-O:
output (os:"SBS)-OIlh:

231422-66

end rov_disa.ble:
I

* --------------------------------------------------------------------------. /
/' COIIIIAIiD - 11 ,/-

rov_stop: prooedure publio:
ena.ble_rov-O:
output(os_B8B)- Obh:
end rovJtop:

"----------------------------------------:...---------------------------------*'
retr&llSlll1t: prooedure publ1o:

/' COIIIIAIiD - 12 '/

oall dma....load(omd_olwmel. t~dir.1536 • Ot"_dma_addr) :
if lIIIlILohannel then output (os_BBB) - loh:
else output (os_588) - Ooh:
end retrcsJD1t:
I

* --------------------------------------------------------------------------. /

a.bort: prooedure publio:

/' COIIIIAIiD - 13 '/

:ir~~~~~:~~;( if':
end a.bort:

,.--------------------------------------------------------------------------* I
reset_SBB: prooedure publ1o:

/' COIlllAliD. - 14 '/

ena.ble..rov-O:
output(os_58B) - leh:
oall oonfig:
end reset_BBB:

231422-67

Figure 59. General Commands (Continued)

1-479

Infel

AP-236

the listing of this procedure. It accepts 4 parameters
from the calling routine to decide the programming
configuration for the 8237A. The parameters for
DMA_LOAD are: Channel, direCtion, buff_len, and
buff_addr.

7.4 DMA Routines
DMA-LOAD procedure is used to program the
8237A DMA controller for all the operations requiring
DMA service. It also starts or enables the programmed
DMA channel after programming it. Figure 60 shows

converting a pOinter SEG: OFFSET to a 20 hit address
oonvert_20h:it_addr: prooedure{ptr) dword publ1o;

deolare

ptr

ptr_addr

po1nter,

pOinter.

t;~d20~!e~W~~L'ddr) (2)

wOrd;

ptr_e.ddr-Gptr ;
ptr_20h1t-shl{ (ptr_20h1t: -wrd{l)) .4)+Wrd{0);
return{ptr_20h1t) ;
end oonvert_20h1t_addr;
IBli/PC DlIA lOading prooedure

dmILload: prooedure{channel. d1reot1on. huff_len. hufCe.ddr) reentrant publ1o;
deolare . channel byte;
deolare d1reot1on hyte;
deolare huff_len wOrd;

/' ClIANNEL

.~:~i:: ~;!-~~~P~~:~~r){2)
channel-channel and 1;

/' o-ax.aaa

0 or 1

-'III!II; l-TX. III!II -, 688 ,/

/, BYTE COOllT
/' BUFFER ADDR IN 20 BITS

'/
FORI(

ward;
/' GET LEAST SIGNIFICANT BIT

:if channel-O then
/' EXECUTE COIlllAllll ON ClIA1IlIl!L 1
do;
output (c1lI!ILflff) - 0;
/' CLEAR FIRST/LAST FLIP-FLOP
if d1reot1on-O
then output{dma_mode) -dmILrltJllode_l; /' DIRECTION BIT. TELLS
else output{dmILmode)-dmILtlLmode_l;
/' TRAllSIIIT OR RECEIVE
output (c1lI!ILe.ddr_l) - low (Wrd{O));
/ ' LOAD LSB ADDRESS BYTE
output (dma._addr_l) - h1gh(wrd{O));
/ ' LOAD IISB ADDRBSS BYTE
outPUt{dmILaddrh.-l) - low (Wrd{l));
/ ' LOAD PAGE REGISTER
output (c1lI!ILbo_l)
- low (huff_len);
/ ' LOAD LSB BYTECOOllT
output (dmILbo_l)
- h1gh{hufClen);
/ ' LOAD IISB BYTE COtmT
output{dmILmask) - dmILon_l;
/' START ClIA1IlIl!L 1
end;
else do;
/' SAIm AS BEFORE FOR ClIA1IlIl!L 3
output{c1lI!ILflff) - 0;
if d1reot1on-O
then output (dmILmode) -dmILrlLmode_3;
. else output{dma.JIlode)-dma._tx_mode 3;
output (c1lI!ILaddr_3) - low (Wrd{O));
output (dmILaddr_3) - high{Wrd{O));
output{dma._e.ddrh_3) - low (wrd(l)):
output (dma.J>o:"3)
- low (huff_len):
output (dma._bo_3)
- h1gh{huff_len):
output{dmILmask) - c1lI!ILon_3:
end;
end

~load:

'/
'/
'/

,/
'/
,/
'/
'/
'/

,/
'/
,/

231422-68

Figure 60. DMA Routine

1-480

intJ

AP-236

One peculiarity about this procedure is that in order to
speed up the DMA step-up, this procedure doesn't get a
pointer to the butTer, but a pointer to a 20 bit address in
the 8237 format. The 8088/8086 architecture define
pointers as 32 bits seg:otTset entities, where seg and otTset are 16 bit operands. By the other hand the IBM/PC
uses an 8237A and a page register, requiring a memory
address to be a 20 bit entity. The process of converting
a seg:otTset pointer to a 20 bit address is time

consuming and could negatively atTect the performance
of the 82588 driver software. The decision was to make
the pointer/address conversions during initialization,
considering that the butTers are static in memory (essentially removing this calculation from the real time
response loops).
Figure 61 is a listing of the DMA_LOAD procedure
for the 80188 or 80188 on-chip DMA controller. It has
the same caller interface as the 8237 A based one.

dma_load: procedure(channel,direction,trans_len,buff_addr) reentrant;
j* To

load and start the

80186 r:MA controller foor the desired operation *j

declare dma_rx~ode
literally '1010001001000000b'; j* rx channel *j
j* src=IO, dest=M(inc), sync=src, TC, noint, priority, byte *j
declare dma_t~ode
literally '000011010000000b'; j* tx channel *j
j* src=M(inc), dest~IO, sync=dest, TC, noint, noprior, byte *j
declare
!leclare
declare
declare

channel byte;
j* channel
direction byte;
ja o - rx, 588
mem; 1 - tx, mem -> 588
trans_len word;
j* byte count
buff_addr pointer; j* buffer pointer in 20 bit addr. form

*j
*j
oj
oj

declare (wrd based buff_addr)(2) word;
do case channel and OOOOOOOlb;
do case direction and OOOOOOOlb;
do;
jo channel 0, 588 to memory
oj
output(dma_O_dpl) - wrd(O);
output (dma_O_dph) - wrd(l);
output (dma_O_spl) - cLa_588;
output (dma_O_sph)
0;
output (dma_O_tc)
- trans_len;
output (dma_O_cw)
D
dma_r~ode or 0006h; f* Start
end;
g

do;
j* channel 0, memory to 588 Of
output (dma_O_dpl) = cLa_588;
out pu t ( dma_O_d ph)
0;
output (dma_O_spl) = wrd(O);
output(dma_O~ph)
=wrd(l);
ou tpu t (dma_O_t c)
= trans_len;
output (dma_O_cw)
= dma_t~ode or 0006h; f* Start
end;
end;

DMA chl 0 *f

DMA chl 0 *f
231422-69

Figure 61.80186 DMA Routines

1-481

inter

Ap·236

do case direction and OOOOOOOlb;
do;
1* channell
588 to memory *f
ou tpu t Cdma_1_dpI) - wrd( 0); ,
output (dma_1_dph) = wrd(l);
output(dma_1_spI) - cLb_588;
output (dma_1_sph) - 0;
output(dma_1_tc)
= trans len;
outptit(dma_1_cw)
- dma_r~ode or 0006h; 1* Start DMA chI 1 *f
end;
do;
ou tpu t
ou tpu t
ou t pu t
ou tpu t
oU tpu t
ou t pu t
end;
end;

1*
(dma_1_dpl)
(dma_1_dph)
(dma_1_spl)
(dina_l_sph)
Cdma_1_t c)
Cdma_l_cw)

channel I, memory to 588 *f
- cLb_588;
- 0;
- wrd(O);
- wrdCl);
= trans_len;
= dma_t~ode or 0006h; 1* Star~ DMA chI 1 *f

end;

end dma-'.-l 0 ad;
231422-70

Figure 61. 80186 DMA Routines (Continued)

7.5 Interrupt Routine
The interrupt service routine, 'intr_588', shown in
Figure 62, is invoked whenever the 82588 interrupts.
The main difficulty in designing this interrupt routine
was to speed its performance. Fast status processing
was a basic requirement to be able to handle back to
back frames.

The interrupt handler will read 82588 status, and put
them into a 64 byte long EVENT-,-FIFO. Those
statuses are going to be used in the main loop for updating screen counters. All the statistics are updated as fast
as possible in the interrupt handler to fulfill the backto-back frame processing requirement.
The interrupt handler is not reeritrant, interrupts are
disabled at the beginning and reenabled on exit.

1·482

inter

AP-236

Interrupt service routi.ne
1ntx_568 :procedure i.nterrupt 13;
deolare sta.t
event
i
(stO,st1,st2,st3)
rx_stC
xx_stl

byte.
byte.
byte,
byte,
byte.
byte;

/" FOLLOWING LITERALS HAVE THE PURPOSE OF ENABLE ACTING
ON EITHER CHANNEL 1 OR 3 SELECTIVELY

•/

declare
literally 'if oM_Ohannel.
then output(dma_mask)-d..ma_off_3;
else output(dma_mask)-dma_off_l'.
literally . if rx_channel
then output(d.ma._mask)-dlna_of:f_3;
else output(dmlLmask)-dmfLoff_l'
I

'1:£' cmd_ohannel

then output(os_688)-lCh;
else output(os_6SB)-Ooh',
'if eM_channel
then outPUt(OB_66B)-14b:

else output(os_68S)-04h';
disable;

/' DISABLE INTERRUPTS
/. NO INTERR. NESTING

outputCCS_58B)

-Ofh;

•/
•/

1* RLS 588 PTR. START 0 ./

event_:f'ifo(wr-ptr). stD. stO-input(oS_588); /' READ 82588 STATUS
event_f1fo(wr_ptr). stl. stl-1nput(cs_668); I' REGISTERS. PASSING
event_:fl:fo(wr_ptr). st2. st2-1nput(cs_68B); I' THEM TO THE MAIN
event_f1:fo(wr_ptr). ot3. st3-1nput(cs_5BB); I' PROGRAM ON THE FIFO

'I
'I
'I

•/

wr_ptr-(wr_ptr+1) and Ofh:
f1foont-(f1focnt+l) and Ofh;

I' INCREMENT FIFO

I' COUNTERS

"0//

event-stO and Ofh;

I' GET EVENT· FIELD

output (oS_588 )-80h;

/" ACKNOWLEDGE 82688
I' INTERRUPT

231422-71

do case event;

:~::::g~ ~top_Omd_dma:

ev_02
eV_03
ev_04

stop_omd_dma:
stop_omcLdma;

do;

stop_omd_dma;

NOP COMMAND
lA_SETUP, STOP DMA
CONFIGURE. STOP DMA
MULTICAST. STOP DMA
I' TRANSMIT DONE
I'
I'
I'
I'

/" CHECK IF THERE WAS A COLLISION AND IS NOT THE
MAX COLLISION

'1
'1
'1
'1

st ..t-(st2 e.nd 10000000b) or (st1 e.nd 00100000»);
i f (stat-80h)
then do:
,
/' RETRANSMIT
'1
call dma_loB.d.( cro_channel. tx_d1r, 1536.@tx_dma_e.ddr) ;
1SSu8_rt'lCcmd;
I' UPDATE STATISTICS
'I
total_t:Lcount-total_tx_oount+l:
ooll_ont(17) - ooll_cnt(17) + 1; I'TOTAL COLL'I
bat:Ltx_count .. ba.d_tx_count + 1;
end.;

else do;
if in_loop
then do;

/" EXECUTING TRANSMISSIONS IN LOOP

/, RE ISSUE TRANSMIT COMMAND
'I
ca1.1 dma._l.oa.d(cro_channel.. tx_d1r. 1636. @tx_dm~e.d.dr

issue_tx_cmc1;
tote.l_t~count-total._tx_count+1 ;
end;
if (st2 e.nd 00100000b) - 0
/0 BAD TRANSMIT"/
then do;
ba.cLtx_count - b~tx_oount + 1:
/ 0 INCREMENT UNDERRUN COUNTER
"/
tmp-sor(tmp: -st2. 1);
tx_under-tx_under plus 0;
I' INCREMENT LOST CTS COUNTER
'1
tmp-scr( tmp. 1) ;
lost_cts-lost_ots plus 0;
/" INCREMENT LOST CRS COUNTER
0/
tmp-sor(tmp,l) ;
lOBt_crs-loBt_Cl'S plus 0;
if (stat-OAOh) /0 INC COLLISIONS COUNTER "/
then coll_ont(l7) - coll_ont(l7) + 1;
end;
end;
/" INCREMENT DEFER COUNTER
tmp-scl«tmp' -stl) , 1);
tx_defer-tJLdefer plus 0;

end.;

"/
231422-72

Figure 62. Interrupt Routine

1-483

AP-236

ev.OS:

stop.o~dma,

/'
/'
/,
/'

ev_06: stop.omd.dma,

ev.07: stop.omd.dma,
ev.OS:
dO,

~~~~:e~ff+l)

TDR COIIIIAlm, STOP DNA
DOIIP COIlllAND, STOP DMA
DIAGNOSB CIID, STOP DNA
RECBlVED FRAIIB

'/
'/
'/
'/

and OOOOOlllb, /, INC BUFFER NO. IIOD S'/
>
IF RBCElVER IS ON
'/
then do,
/' PREPARB IIBXT BUFFER '/
oall dma.load(l'Z.-ohannel, r,ul1r ,1632,lIIr:lLdmILaddr(i»,
!i~"o=~~s~~~~)~~:r:-t(OUSS)- lSh,
rx.buffer(i) .ohain.ont-O,
end,
else call rov.disable,
/, DISABLE RECEIVER
'/
i f enable.rov,

/, FIND, ADORBSS OF END OF CURRBNTLY RECEIVED BUFFER
/' BY CALCtlLATING IT WITH TI!B 82688 BYTE COUNT REGS.
rzJ>ufCoff-(shl(double(st2) ,8) or double(stl»,
/' READ STATeS BYTBS FRail IIEIIORY
rx.J3tO-rx..buffer( ourrent..buff) . buff(rx.buff.off·2) ,
r~stl-rx.buffer(ourrent..buff) . buff(rzJ>uff.off·l) ,
/' UPDATE ACTOAL BUFFER SIZB
r~ffer( ourrent.buff) • aotual-size-rx.buff.off,
r~ffer( ourrent.buff) • stO-l'Z.-stO,
r%.buffer(ourrent.buff). stl-l'Z.-stl,
current.buff-i,
/' UPDATE TOTAL RECEIVBD BUFFERS
total.rov.oount-total.rov.oount+ 1,
/, UPDATE STATISTICS
if (~stl and 00100000b)-0
then do,
bacLrov_oount-had_rev_OOllDt+ 1 ;
/, INCREIIENT NO lIND OF FRAIIB COUNTER
tmp-sor(tmp: -l'Z.-stO, 7),
no_eof-no_sof plus 0;
/' INCRBIIENT SlroRT FRAIIB COUNTER

;~=~~~~;~U;~

plus 0,
/, INCRBIIENT ax OVERRUN COUNTER
tmp-sor(tmp:-l'Z.-stl,l), .

~~~~ve~~~··ERROR

COUNTER

tmp-sor(tmp, 2),

,;gI~er~l::a~

COUNTER

tmp-sor(tmp,1) ,

end;

eV.09
eV.l0
ev_ll
ev.12

'/
'/
'/

'/
'/
'/
'/

oro_err-oro_srr plus 0 i
end,
231422·73
/' BV.09 RB~UBSTS ASSIGNIIENT OF A NEW BUFFER
'/
oall allooate.new..l>uffer(not(rol(st3,l» and 00000001b),
stop.r~dma:
/, RECEIVE DISABLE
'/
stop.rx.dma:
/' STOP RECEIVE
'/
do :
/' RE·TRANSIiIT DONE
'/
stat-(st2 and 10000000b) or (stl and 00100000b):
if (stat-80h)
then do:
/' RlITRAlISliIT
'/
oall dmILloadO, tx.d1r, 1536 ,ot',-dmlLaddr):

1ssue_rtx-omd. i

001l.OIlt(17) - 0011.ontCl7) + 1:
total.t~oount-total.t~oount+ 1:
+1:

bad.t~oount-bad.t~oount

end:
else do:

if ilLloop
then do:
/, LOOP RBTRANSIIISSIONS
'/
oall dmaJoad(omd.ohannel, t~d1r ,1536,ot".dmILa
1SBue_tx-omd :
total.tx.oount-total.t~oOUllt+l :
end:
if (stat-OAOh) /' MAX COLLISION
'/
then do:
coll.ont(6) - 001l.OIlt(6)+1:
0011.OIlt(17) - 001l.OIlt(17)+1:
bad.t~ooUllt-blSd.t~oount +1:
end;

/, UPDATE SPECIFIC COLLISION COUNTER
else 001l.ont(st1 and Ofh)
- 001l.ont(st1 ""d Ofh) + 1:
ev.13:

~.~:;
end:

end:

stop.o~dma:

stop.omd.dma,

/' EXBCUTION ABORTBD

/' DIAGNOSE FAILED

/' AClOIOWLBDGE 8259A INTERRUPT
output(pio.oow2)- seoi.pioo:
/' SPECIFIC EOI FOR 82B9

,/
,/

231422·74

Figure 62. Interrupt Routine (Continued)

1-484

intJ

AP-236

APPENDIX A .
STAR LAN SIGNALS

1-485

inter

AP-236

82588
TXD RTS

(1)-----

5pF

(2)----

24 GAUGE
800 IT lWlSTED PAIR WIRE
IN 25 PAIR BUNDLE

(')~

231422-47
231422-55

Figure 63. StarLAN Signals

1-486

AP-236

Eye Diagram (5 Bits), DIW Cable
Manchester Encoded Signal
Transmission Distance ~ 0.8 KIt.
0
0
0

'"
0
0

'"
0
0
0

5'"
...
III

Z
0

:J;o
...
...'"
C>

-'0
0",
>.

..
0
0

•

'"•

0.0

0.2

0.6

0.4

0.8

1.0

TIME u,.SEC)
231422-48

Figure 64. Received Signal Eye Diagram

1-487

inter

AP-236

APPENDIX B
802.3 1BASE5 MULTI-POINT EXTENSION (MPE)
As previously stated, one of the most important advantages of StarLAN is being able to work on already installed phone wires. This advantage is considerably diminished in Europe where numerous constraints exist
to the using of those wires:

Recently the StarLAN 802.3 lBASES task force has
been considering the extension of the StarLAN base
topology. This extension called MULTI POINT EXTENSION (MPE) is going to be developed to address
the previously described marketing requirements.

I. Wire belongs to local PTTs.
2. Not enough spare wires.

Currently no agreement has been reached by the
StarLAN task force on the MPE exact topology and
implementation. Multiple approaches have been presented, but no consensus met. It was decided though
that the MPE is going to be an addendum to the STAR
topology, and that its final specification will happen
after the approval of the current lBASES STAR topology (July 1986).

This same issue is raised when talking about small businesses where in a lot of cases no wiring closets and/or
spare wires are available.
In summary, in a lot of cases rewiring will be necessary,
in which case the STAR topology may not be the most
economical one.

1-488

__,,,,,--- THROUGH A HUB UPGRADABLE
TO THE FULL STARLAN TOPOLOGY
(2500 m. MAX END-TO-END)
HUB COST ELIMINATED
IN SMALL TOPOLOGIES.
LOWER COST PER PORT
(UP TO 8 STATIONS PER PORT)

HUB
CONNECTION OPTIONAL,
NOT NEEDED FOR SMALL
TOPOLOGIES

"11

...

!'"

;:
,

(Xl

c
::+

»
"U

W
aI

~
j

LOWER COST.
TERMINALS ATIRACTIVE

III

0"
j

FEWER CONNECTIONS TO
WIRING CLOSETS
231422-97

inter

AP-236

APPENDIX C
SINGLE DMA CHANNEL INTERFACE
In a typical system, the 82588 needs 2 DMA channels
to operate in :a manner that no received frames 'are lost
as discussed in section 5.1.3. If an existing system has
only one DMA channel available, it is still possible to
operate the 82588 in a way that no frames are lost. This
method is recommended only in situations where a second DMA channel is impossible to get.
Figure 66 shows how the 82588 DMA logic is interfaced to one channel of a DMA controller. Two DRQ
lines are ORed and go to the DMA controller DRQ
line and the DACK line from the DMA controller is
connected to DACKO and DACK1 of the 82588. The
82588 is configured for mUltiple buffer reception
(chaining), although the entire frame is received in a
single buffer. Let us assume that channel CH-O is used
as the first channel for reception. After the ENAble
RECeive command, CH-O is dedicated to reception. As
long as no frame is received, the other channel, CH-1;
can be used for executing any commands like transmit,
multicast address, dump, etc., by programming the
DMA channel for the execution command. The status
register should be checked for any ongoing reception,
to avoid issuing an execution command when reception
is active.
,

OROO
OROI
OACKO
OACKI 1
82588

OROn

Iished, as shown in Figure 67. After this, the received
bytes start filling up the on-chip FIFO. The 82588 activates the DRQ line after l5-:-FIFO LIMIT + 3 bytes
are ready for transfer in the FIFO (about 80 microseconds after the interrupt). The CPU should react to the
interrupt within 80 ,""S and disable the DMA controller.
It should also issue an ASSIGN ALTERNATE BUFFER command with INTACK to abort any execution
command that may be active. The FIFO fills up in
about 160 ,""S after interrupt. To prevent an underrun,
the CPU must reprogram the DMA controller for
frame reception and re-enable the DMA controller
,within 160 ,""S after the interrupt (time to receive about
21 bytes). No buffer switching actually takes place, although the 82588 generates request for alternate buffer
every time it has no additional buffer. The CPU must
respond to these interrupts with an ASSIGN ALTERNATE BUFFER command with INTACK. To keep
the CPU overhead to a minimum, the buffer size must
be configured to the maximum value of 1 kbyte.
If a frame transmission starts deferring due to the reception occurring just prior to an issued transmit command, the transmission can start once the link is free
after reception. A maximum of 19 bytes are transmitted
(stored in the FIFO and internal registers) followed by
a jam pattern and then an execution aborted interrupt
occurs. The aborted frame can be transmitted again"

If the transmit command is issued imd the 82588 starts
transmitting just prior to receiving a frame then transmit wins over receive-but this will obviously lead to a
collision.

OACKn
OMA
CONTROLLER
231422-49

Figure 66. 82588 Using One DMA Channel'
If a frame is received, an interrupt for additional buffer
occurs immediately after an address match is estab-

Note that the interrupt for additional buffer is used to
abort an ongoing execution command and to program
the DMA channel for reception just when a frame is
received. This scheme imposes real time interrupt handling requirements on the CPU and is recommended
oniy when a second DMA channel is not available.

1-490

inter

AP-236

REQUEST
ALT BUff
INTERRUPT

ASSIGN
ALT BUff
WITH INTACK

1
82588 --1

82~1;;

1
I

::========_~_8_0_~_s_________'~I____________

ADDRESS MATCH
ON fRAME
RECEPTION

DMA CONTROLLER
MUST BE DISABLED
PRIOR TO THIS

rFIFO fULL

•
~ 1 60 ~S -----------o·~1

DMA CONTROLLER
MUST BE PROGRAMMED
fOR RECEPTION AND
ENABLED PRIOR TO THIS
231422-50

Figure 67. Timing at the Beginning of Frame Reception for Single DMAChannel Operation

1-491

inter

AP-236

APPENDIX D
MEASURING NETWORK DELAYS WITH THE 82588
Knowing networks round-trip delays in local area networks is an important capability. The round-trip delay
very much defines the slot time parameter which by
itself has a direct relationship to network efficiency and
throughput. Very often the slot-time parameter is not
flexible, due to standards requirements. Whenever it is
flexible, optimization of this number may lead to significant improvement in network performance.
Another possible usage of the network delay knowledge
is in balancing the inter-frame -spacing (IFS) on broadband networks. On those networks, stations nearer to
the HEAD-END hear themselves faster than farther
ones. Effectively hll-ving a shorter IFS than stations far
from the HEAD-END. This difference causes an inbalance in network access time for different stations at
different distances from the HEAD-END. Knowing
the STATION/HEAD-END delay allows the user to
reprogram the 82588 IFS accordingly, and by that balance the effective IFS for all the stations.

The 82588 has an internal mechanism that allows the
user to measure this delay in BIT-TIME units. The
method is based on theCact that the 82588 when configured for internal collision detection, requires that the
carrier sense be active within half a slot-time after
transmission has started. If this requirement is not ful~
filled the 82588 notifies that a collision has occurred.
Thus it is possible to configure the 82588 to different
slot time values, then transmit a long frame (of at least
half a slot-time). If the transmission succeeds, the network round-trip delay is less than half the programmed
slot-time. If a collision is reported, the delay is longer.
The value of the round-trip delay can be found by repeating this experiment process while scanning the slottime configuration parameter value and searching the
threshold. A binary search algorithm is used for that
purpose. First the slot-time is configured for the maximum (2048 bits) and according if there was a collision
or not, the number changed for the next try. (See Figure 68)

1-492

infef

AP-236

2
5
8
8

PROPAGATION DELAY

HEADEND
RX

• SCHEt.lE IS BASED ON THE FACT THAT THE 82588 EXPECTS RX CARRIER
TO BE ACTIVE AFTER 1/2 SLOT TIt.lE

K = APPROXIt.lATION FACTOR

231422-98

Figure 68. Network Delay Measurement using the 82588

1-493

APPLICATION
NOTE

AP-344

October 1990

Interfacing Intel 82596 LAN
Coprocessors with
M68000 Family Microprocessors

Some portions of this document were provided by
Dr. Design of San Diego, CA

Order Number: 292076-001
1-494

Interfacing Intel 82596 LAN Coprocessors with
M68000 Family Microprocessors
CONTENTS

PAGE

CONTENTS

PAGE

1.0 INTRODUCTION ................... 1-497
1.1 Scope· ........................... 1-497

4.0 M68000/82596DX INTERFACE .... 1-509
4.1 Design Specifications ............ 1-509

1.2 Fundamental Assumptions ....... 1-497

4.2 Clocking .. ~ ............. : ........ 1-509
4.3 Reset Timing .................... 1-509

2.0 GENERIC IMPLEMENTATION
ISSUES ..............................
2.1 Block Definitions ................
2.2 Clocking .........................
2.3 Reset Retiming ..................
2.4 CA and PORT Generation .......
2.5 Arbitration .......................
2.5.1 Refresh Requests ..........
2.5.282596 Requests ............
2.5.3 Arbiter Implementation ......
2.6 Signal Conversion ...............
2.7 Wait State and Burst Generator ..
2.7.1 General Information ........
2.7.2 Single Cycle Bus
Transfers : .....................
2.7.3 Burst-Cycle and MultipleCycle Bus Transfers ............
3.0 MC68030/82596CA INTERFACE ..
3.1 Design Specifications ............
3.2 Clocking .........................
3.3 Reset Retiming ..................
3.4 CA and PORT Generator ........
3.5 Bus Arbiter ......................
3.6 Memory Signal Conversion ......
3.7 Wait State and Burst Generator ..
3.7.1 General Information ........
3.7.2 Single Cycle Transfers ......
3.7.3 Burst Cycle Bus Transfers ..

4.4 CA and PORT Generator ........
4.5 Bus Arbiter ......................
4.6 Memory Signal Conversion ......
4.7 Wait State Generator ............

1-497
1-497
1-499
1-499
1-500
1-501
1-501
1-501
1-502
1-504

5.0 MC68000/82596SX INTERFACE ..
5.1 Design Specifications ............
5.2 Clocking .........................
5.3 Reset Retiming ..................
5.4 CA and PORT Generator ........
5.5 Bus Arbiter ......................

1-505
1-505

1-510
1-510
1-510
1-511
1-511
1-511
1-512
1-512
1-512
1-512

5.6 Memory Signal Conversion ...... 1-512
5.7 Wait State Generator ............ 1-513
APPENDIX A SCHEMATICS ...........
A.1 MC68030/82596CA .............
A.2 MC68020/82596DX .............
A.3 MC68000/82596SX .............

1-514
1-515

APPENDIX B PLD EQUATIONS .......
B.1 MC68030/82596CA .............
B.2 MC68020/82596DX .............
B.3 MC68000/82596SX .............

1-518

1-545

1-508
1-508

APPENDIX C TIMING DIAGRAMS .....
C.1 MC68030/82596CA .............
C.2 MC68020/82596DX .............
C.3 MC68000/82596SX .............

1-508

APPENDIX D PARTS LIST ............ 1-569

1-505
1-505
1-506
1-506
1-506
1-506
1-506
1-507
1-507
1-508

Throughout this document, M68000 is used as a general reference to a family of
microprocessors, which includes the MC68000, MC68020, MC68030. A reference
to a particular member of the family will use the MC prefix followed by the specific
number. 82596 is used as a general reference to a family of LAN coprocessors-the
82596CA, 82596DX, and 82596SX. A reference to a particular member of the family will use 82596 followed by the two letter suffix.

1-495

1-516
1-517

1-519
1-530
1-539

1-546
1-555
1-562

Table of Figures.and Tables
CONTENTS

PAGE

FIGURES
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
F'igure 9
Figure 10
Figure 11

M68000 Family and 82596 Family Interface Generic Block Diagram .............. 1-498
Clock Timing Relationships .........•............................................ 1-498
Reset Retiming Block Diagram .................................................. ~ -499
CA and PORT BlockDiagram .................................................... 1-500
CA and P,?RT State Transition Diagram ......................................... 1-500
Arbiter State Transition Diagram ................................................ 1-503
Arbiter Signal Timings ............................................................ 1-503
Memory Signal Conversion Block Diagram ...................................... 1-504
Memory Cycles for M68000 Family and 82596 Family ........................... 1-504
Wait-State and Burst Generation Block Diagram ................................. 1-505
82596DX and 82596SX Reset Retiming Circuit .................................. 1-509

TABLES
Table 1
Table 2
Table 3
Table 4
Table 5
. Table 6
Table 7

82596-Family Parallel Bus Comparison ............................... ; ............ 1-497
Clocking Specifications ........................................................... 1-499.
Reset Specifications .............................................................. 1-500
Arbitration SignallnputTimings ................................................... 1-501
Arbitration Signal Output Timings ................................................. 1-502
82596CA Worst-Case Reset Timing Margin .......................... ; .•.......... 1-506
82596DX/SX Worst-Case Reset Timing Margins .................................. 1-509

1-496

AP-344

1.0 INTRODUCTION

2.0 GENERIC IMPLEMENTATION
ISSUES

1.1 Scope
2.1 Block Definitions

The 82596 family of LAN coprocessors provide IEEE
802.3 MAC functions for use with lOBASE5 (Ethernet), lOBASE2 (Cheapernet), 10BASE-T (Twisted Pair
Ethernet), lBASE5 (StarLAN), and other CSMA/CD
LANs with serial bit rates up to 20 Mb/s. The three
members of the 82596 family differ only in the characteristics of their parallel interfaces; the FIFO and serial
functions are identical. Table 1 shows the parallel bus
differences.

Each design is broken into functional blocks. The generic block diagram is shown in Figure 1. The M68000
family and 82596 family are fixed from a functional
standpoint. The designer has almost no flexibility in
their connection or timing. For the purpose of these
designs, the memory control block is also assumed to be
fixed. It is set up only for M68000-type signals and
timings. The blocks for which there is some design flexibility are grouped under the name control logic. These
blocks include the following.

This document describes the circuits required to interface the Intel 82596 family of LAN coprocessors with
the M68000 family of microprocessors. First, general
interface issues are identified and then three specific
designs are provided-including the PLD equations,
timing diagrams, and schematics.

.. Clocking_ Provides the proper clock phases to the
82596 and M68000. It also provides the clock for
the other blocks.
• Reset Retiming. Takes the active low RESET signal
that goes to the M68000 and adjusts its timing and
level to be compatible with the active high RESET
for the 82596.

.. 82596CA and MC68030
• 82596DX and MC68020
• 82596SX and MC68000

• CA and PORT Generation. Decodes the address
lines and generates the Channel Attention (CA) and
CPU Port (PORT) signals to the 82596. The system
designer selects the memory addresses to be decoded
to activate these signals. The amount of decode logic
will vary greatly depending on the system memory
map.
.. Arbitration. Determines which of the three master
devices has control of the local bus: the M68000, the
82596, or the refresh controller. The refresh controller has the highest priority, followed by the 82596
and then the M68000. Additional master devices are
supported through simple changes to the PLD equations in this block.

. 1.2 Fundamental Assumptions
Each design is based on several fundamental assumptions about the memory subsystem. The circuits required to support these features are implemented in a
few programmable components. If the 82596 is added
to existing designs in which the required circuits are
already implemented, these circuits do not have to be
duplicated.
The following assumptions are made about the designs.
• The memory subsystem uses DRAM.
• Refresh request signals are asynchronous to the system clock.
• Interface logic is implemented in PLDs where possible.
• 82596 family type signals will be converted to
M68000 family type signals.

• Memory Signal Conversion. Takes the 82596 control signals, such as ADS and W /it, and converts
them to M68000-type control signals, such as AS,
DS, and R/W.
.. Wait State and Burst Generation. Generates the
RDY signal to the 82596 (and BRDY for the
82596CA). It also asserts the burst request
(CBREQ) to the memory controller.

Table 1. 82596-Family Parallel Bus Comparison
82596
Version

Address
Bits

Data
Bits

Parallel
Clocking

Burst
Access

Parity
Pins

82596CA
82596DX
82596SX

32
32

32
32
16

x1
x2
x2

Yes

No
No

1-497

Maximum
Frequency
(MHz)

33
33
20

AP-344

REFRESH REO·
1.468000

82596

BR·
BG·
BGACK·.

..
~

...

ClK

031-00

CA
PORT*

CA &: PORT· DECODE

CLOCKING

ClK1 OR ClK2

RESET

RESET*

A31-AO

HlDA
lOCK·

ARBITER

WAIT STATE

GENERATOR

RESET
ROY··
BLAST*
BROY·

...

....

::...

....

AS·, OS·, R/W·
SIZO,SIZ1,DBEN·
DSACKO· ,DSACK1·
CBREO·

MEMORY
SIGNAL
CONVERSION

I:f----+

A31-AO
031-00
BE3·-BEO·
AOS·,W/R·
BOFF·

Al,AO

1.4
U

X
MA(O-X)T

I
,~

MEMORY CONTROllER

RAS CAS

OE(HI,lO) WE(0-3)

MEMORY

I
292076-1

Figure 1. General Block Diagram

292076-2

Figure 2. Clock Timing Relationships

1·498

AP-344

2.2 Clocking

2.3 Reset Retiming

The 82596 family uses different types of clocking. The
82596DX and 82596SX use CLK2, which is twice as
fast as the internal operating frequency. The two different phases of CLK2 for every CLKl are defined as 4> 1
and 4>2. The rising edge of CLKl corresponds to the
rising edge of CLK2 at the beginning of 4> 1. The
82596CA uses CLKI, which is identical to the internal
operating frequency. The 82596 clock timing relationships are shown in Figure 2.

Because the 82596DX and 82596SX use CLK2, the setup and hold time specifications for the reset signal are
very important. The deactivation of RESET is the only
means by which the 82596DX and 82596SX determine
which phases of CLK2 correspond to 4> I and 4>2. Since
many of the control signals are only valid at the beginning of certain phases, it is crucial that the arbitration,
signal conversion, and wait state generation logic know
the current phase of the clock. Failure to meet these
specifications can cause improper memory accesses by
the 82596. Figure 3 is the reset retiming block schematic.

In many cases the control logic is simplified by clocking
it with CLK2, even if the CPU and 82596CA are
clocked by CLK 1 . In some other cases it is advantageous to invert the clocking signal to the 82596, which
introduces a phase shift between the devices. The clocking specifications of the 82596 and M68000 are shown
in Table 2.

RESET

All the designs use 74F74 flip-flops because of their
high operating frequency, low propagation delay, and
CLK1--~----------~
wide availability. If another type of flip-flop is used the
292076-3
timing analysis must be modified to reflect the different
Figure 3. Reset Retiming Block
specifications.
.
Table 2. Clocking SpeCifications

Component

Freq
(MHz)

Max
Rise

Clock

Max
Fall

Min
High

Min
Low

(nanoseconds)

82596CA

ClK

3.0

14.0

82596CA

ClK

3.0

11.0

82596DX

ClK2

7.0

4.0

5.0

82596DX

ClK2

4.0

3.0

4.5

82596SX

ClK2

8.0

5.0

7.0

MC68030

ClK

4.0

19.0

MC68030

ClK

3.0

14.0

MC68020

ClK

4.0

19.0

MC68020

ClK

3.0

14.0

MC68000

ClK

5.0

27.0

1-499

AP·344

The timings for the M68000 active low signal RESET
are not compatible with the 82596 active high signal
RESET. To prevent possible metastable conditions, the
M68000 RESET passes through a two-stage synchronizer before going to the 82596. This will usually require
two 74F74 flip-flops. Using two stages, rather than one,
greatly reduces the probability of metastable conditions
in the 82596. One of the stages is also used to invert the
signal. Table 3 lists the relevant specifications for RESET and RESET.

functions. Only four functions are defined (functions 4
through 15 are reserved and should not be used).
o Do an internal reset (pins D31-D4 are ignored).
Do a self test (the results are placed at the location
specified by pins D31-D4).

Table 3. Reset Specifications

PORT has more stringent requirements for setup and
hold. times than CA does. PORT must meet specific
setup and hold times with respect to the clock and must
also be active for at least two consecutive clocks. CA is
only required to be active for two clocks without meeting specific setup or hold times; however, CA only has
to be active for one clock if the setup and hold times are
met.

Component

Freq
(MHz)

Setup
(ns)

Hold
(ns)

82596CA

8.0

3.0

92596CA

10.0

3.0

825960X

10.0

3.0

825960X

8.0

3.0

82596SX

13.0

4.0

MC68030

NO
NO
NO
NO
NO

MC68020

MC68000

ND = Not Defined by Motorola

2.4 CA and PORT Generation
The 82596 has two inputs that do not correspond to
any signals generated by the CPU: Channel Attention
(CA) and CPU Port (PORT). Channel Attention is always monitored by the 82596, and the falling edge is
internally latched. The 82596 responds to Channel Attention by reading the system control block command
word, which is stored in memory. Several fields in this
command word tell the 82596 what to do; e.g., acknowledge interrnpts, change the state of the command
unit, change the state of the receive unit, or load the
bus throttle timers.
When the 82596 does not have the bus, it examines
PORT. If it is active the value on the data bus is stored
in the 82596 in a special register. The value on the 4
least significant bits (D3-DO) indicates one of sixteen

2 Execute a Dump command (the results are placed at
the location specified by pins D31-D4).
3 Move the system configuration pointer to the location specified on pins D31-D4.

Because the M68000 family does not support a separate
I/O address space, all I/O functions must be memorymapped. The addresses for CA and PORT can be selected by the designer. In the design examples, Section
3 through 5, part of one PLD is used to generate both
signals. The number of input pins on the PLD will determine the address range limitations. If the PLD has
fewer inpuf pins than the number of address lines to be
decoded, one of the PLD inputs should be connected to
the output of a secondary decoder. This secondary decoder must meet a worst-case propagation delay, which
is listed in the comment fields of the PLD equations for
each design.
Implementing CA and PORT will usually require four
macro-cells, which is about one-half of a standard
PLD. Two are used for the actual output signals and
two are used as a state machine to control the timing of
the output signals. Figure 4 is the CA and PORT generator block diagram and Figure 5 is the state transition
diagram.

CLKUCA
AS

pLD

PORT

ADDRESS

HIADDR
292076-4

Figure 4. CA and PORT Block Diagram

&=e/---~.~
Figure 5. CA and PORT State Transition Diagram
1-500

292076-5

intJ

AP-344

2.5 Arbitration
All the design examples assume that the memory will
use DRAMs. This means there will be at least three
master devices attempting to gain access to memory:
the M68000 CPU, the 82596 LAN coprocessor, and the
refresh controller. The requests from the refresh controller must be given highest priority to avoid corrupting data in the DRAMs. The 82596 is given the second
highest priority, so it is not forced to wait and eventually overrun or underrun. The M68000 has the lowest
priority because of its internal Bus RequestlBus Grant
mechanism. Because some of the M68000 family CPUs
have an internal cache or instruction pipeline, they can
fetch code or data internally while the 82596 or the
refresh controller are using the local bus.
The M68000 family uses a three-signal arbitration
scheme. A master device makes a bus request by asserting BR and waiting for the M68000 to assert BG. The
master device then drives BGACK while it is using the
bus. When the master device no longer needs the bus it
brings BR inactive, then the M68000 drives BG inactive. Finally the master device drives BGACK inactive.
2.5.1 REFRESH REQUESTS

Refresh requests are assumed to be asynchronous with
the arbitration clock; therefore, the refresh signal must
be synchronized-typically with a 74F74 flip-flop. At
the completion of the refresh cycle the local bus will be
released to .the requestor having highest priority. The
flip-flop is not needed if the refresh request timing is
synchronous with the arbitration clock and meets the
setup and hold times of the PLD.

There are several transparent DRAM refresh techniques. The most common method hides the refresh
cycle as extra wait states in the normal CPU or 82596
accesses. This tec~u'e eliminates the arbitration overhead of the BRlBG (HOLD/HLDA) protocol and
simplifies the arbiter logic. The main disadvantage is
that the wait state generator becomes more complex.
2.5.2 82596 REQUESTS

The 82596 acquires and holds the system bus via the
HOLD/HLDA handshake. It requests the bus by activating HOLD. When the arbiter gives the local bus to
the 82596 it asserts the HLDA signal, which is the inverted LANCYC signal from the arbiter. Overrun conditions can occur in some external devices if the 82596
holds the bus too long. The 82596's bus throttle timers
can be used to regulate bus use; the timer can be activated two ways.
• Externally. A high state on the BREQ pin starts the
timer.
• Internally. A high state on the HLDA pin starts the
timer.
Instead of using bus arbitration schemes, the 82596CA
can be forced off the bus by activating the backoff pin
(BOFF). This provides higher performance and faster
refresh- cycles. (The 82596DX and 82596SX do not
have this backoff feature.)
Because the 82596 HOLD and HLDA signals are active high and the M68000 BR and BG are active low,
the arbiter must invert the logic. In addition, the timings are not compatible. The arbitration signal timings
are shown in Tables 4 and 5.

If a refresh request arrives while the M68000 is the
active bus master, the Bus Request signal (BR) to the
M68000 will be asserted. When the M68000 forces BG
active the arbitration logic brings BGACK active and
the refresh..E¥cle begins. When the refresh has been
completed BR goes inactive. If the 82596 is the active
bus master when the refresh request arrives, the refresh'
cycle will not start until the 82596 has completed its
transfers. BR to the M68000 will remain active until
the refresh cycle has completed; BR will not deassert
when the 82596 completes its transfers. If another
82596 request arrives during the refresh cycle, BR will
remain active until both the refresh controller and the
82596 complete their transfers.
The designer is responsible for ensuring that enough
refresh requests are made to avoid corrupting data in
the DRAM. These designs assume that a "refresh cycle
signal goes into the memory controller and indicates "
that a refresh cycle is in progress. If a transparent technique is used for refreshing the DRAM, or if SRAM is
used, then the arbiter can be greatly simplified.

1-501

Table 4. Arbitration Signal Input Timings
Component

Frequency
(MHz)

Signal

Output Valid
Delay (ns)

82596CA

HOLD

3to22

82596CA

HOLD

3 to19

82596DX

HOLD

4to22

82596DX

HOLD

3 to 19

82596SX

HOLD

4to32

MC68030

Oto20

MC68030

Oto20

MC68020

Oto20

MC68020

Oto20

MC68000

Oto40

AP·344

2.5.3 ARBITER IMPLEMENTATION
Local bus arbitration is mostly implemented in asynchronous PLD that uses the inverted CPU clock
(CLKl) as the arbitration clock. The arbiter has fixed
priorities and responds to bus requests from the 82596
and the refresh controller by requesting the local bus
from the M68000. The arbiter asserts the Bus Request
(BR) and Bus Grant Acknowledge (BGACK) signals
to the M68000, and enforces the bus arbitration protocol.
'

The arbiter .does not immediately give the bus to the
requestor. The arbiter is usually required to provide an
adequate DRAM precharge time and will not release
the bus until the precharge time has expired. The arbiter can be greatly simplified if other logic is used to
control the precharge time. Figure 6 is the arbiter state
transition diagram and the signal timings are shown in
Figure 7.

Table 5. Arbitration Signal Output Timings
Component

Frequency
(MHz)

Signal

Minimum
Setup (ns)

82596CA
82596CA
82596DX
82596DX
82596SX
MC68030
MC68030
MC68030
MC68030
MC68020
MC68020
MC68020
MC68020
MC68000
MC68000

25
33
25
33
16
25
25
33
33
25
25
33
33
16
16

HLDA
HLDA
HLDA
HLDA
HLDA
BR
BGACK
BR
BGACK
BR
BGACK
BR
BGACK
BR
BGACK

10
8
10
8
11
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA

1-502

Minimum
Hold (ns)

3
3
3
3
8
NA
NA
NA
NA
NA
NA
NA
NA '.
NA
NA

Ap·344

292076-6

Figure 6. Arbiter State Transition Diagram

82596 Cycle

LANCYC
(596 HLDA)

Refresh Cycle

292076-7

Figure 7. Arbiter Signal Timings

1-503

intJ

AP·344

2.6 Signal Conversion
The memory signal conversion block modifies the
82596 bus signals to simulate M68000 signals. The new
bus control signals are connected directly to the
M68000's control signals and are tri-stated when the
82596 is not the bus master.. This block will vary depending on which M68000 and 82596 combination is
used. This block can be greatly simplified if the memory controller is capable of using both M68000 and
82596 signals and timings. The memory signal conversion block diagram is shown in Figure 8.

A single PLD generates the signals Address Strobe
(AS), Data Strobe (DS), ReadlWrite (RIW), and Data
Bus.1!:nable (DBEN) from the 82596's signals ADS and
W/R. In 32-bit designs this PLD aI~nerates SIZO,
SIZl, AO, and Al from the 82596's BEO-BE3. In 16bit designs it generates UDS and LDS from the
82596SX's AI, BHE,. and BLE signals. The External
Cycle Start (ECS) and Operating Cycle Start (OCS)
signals are emulated with a tri-state buffer (e.g., a
74F244) enabled by LANCYC. The input that corresponds to the ECS and OCS signals is ADS from the
. 82596. Figure 9 shows the different types of cycles for
the M68000 and 82596.

AS,OS

ADS

R/W,OBEN
Sill-SilO (UDS,lDS)
AI,AO
ECS,OCS

W/R
(BHE,BlE) BE3-BEO
ROY

292076-8

Figure 8. Memory Signal Conversion Block Diagram

ClKI

As,Os

DSACKx (Asynch)
STERM (Synch)

W/R

292076-9

Figure 9. M68000 and 82596 Cycles

1-504

inter

AP-344

2.7 Wait State and Burst Generator
2.7.1 GENERAL INFORMATION

The 82596 and M68000 combinations can use three
types of bus transfers (the 82596DX and 82596SX support only a basic single-cycle transfer). More than one
single transfer can occur without interruption. Each
transfer requires at least two clocks and begins with
ADS going active during the first clock cycle and then
RDY goes active in the last clock. Wait states are inserted by keeping RDY inactive. Figure 10 shows the
wait state and burst generator block diagram.

ROY
-@ROY

-BLAST
STERM
CBACK

PlO

The wait state generator delays the RDY signal to the
82596 from going active. This provides time to meet the
data setup and hold specifications. The 82596 requires
that data be set up a few nanoseconds before the rising
edge of its clock. The M68000 also requires a setup
time; however, it is usually only one nanosecond. The
system designer will need to make provision for, at the
least, the 82596 data setup time plus an addition~l 2 ns
for clock skew. If this cannot be met another walt state
will be needed for all 82596 memory read cycles. This
can be provided by modifying the PLD equations to
delay the assertion of RDY by one or more clocks at
the end of a read cycle. The 82596CA asserts Burst
Last (BLAST) during the second clock of the first cycle, which indicates that the transfer is complete after a
single cycle (the 82596DX and 82596SX do not use
BLAST).

BROY
NEWCBREEQ

2.7.3 BURST-CYCLE AND MULTIPLE-CYCLE
BUS TRANSFERS
292076-10

Figure 10. Wait-State and Burst
Generator Block Diagram
The 82596CA supports all three types of transfers: single cycle, multiple cycle, and burst. The multiple cycle
is simply several uninterrupted single-cycle transfers,
with each bus cycle beginning with ADS going active
during the first clock and then RDY going active in the
last clock. Burst cycles can contain as many as four
consecutive data transfers to four consecutive locations;
however, ADS is only generated before the first data
transfer. The maximum amount of data moved during a
burst is 16 bytes (four 4-byte transfers). The wait state
and burst generation block inserts the appropriate number of wait states during the bus cycle by driving RDY
and BRDY active at the appropriate time.
The M68000 family supports a 3-clock asynchronous
cycle. The MC68030 also supports a 2-clock synchronous cycle that is similar to the 82596CA burst access.
2.7.2 SINGLE-CYCLE BUS TRANSFERS

The 82596 begins a cycle after the rising edge of CLK2
(CLK for the 82596CA) by asserting ADS and driving
W/R: and the address lines (A31-A2) valid. The conversion PLD synchronizes ADS to the clock and generates an address strobe (NEWAS). NEW AS is asserted
during the same phase of the clock that a M68000
would assert AS. NEWAS is also asserted during the
second clock of the 82596 transfer.

The 82596CA tries to burst cycles for any bus request
that requires more than a single data cycle to consecutive addresses. The starting address must begin on an 8byte boundary (xxxxxxxOh or xxxxxxx8h). The fastest
burst cycle for this design assumes that 80 ns interleaved DRAMs are being used, which are fast enough
to allow new data to be strobed into the 82596CA on
each clock. The burst cycle requires 4 clocks for the
first data strobe; however, subsequent data strobes are
returned with each clock.
Burst cycles begin with the 82596CA driving a valid
address and asserting ADS in the same manner as nonburst cycles. The 82596CA indicates that it is willing to
enter a burst cycle by holding BLAST inactive during
the second clock of the cycle. The ready logic then generates a Cache Burst Request (NEWCBREQ) signal to
the memory controller. If Cache Burst Acknowledge
(CBACK) is returned active it indicates that the mem?ry can operate in burst mode. Then the ready logIC
waits for the Synchronous Termination (STERM) bus
handshake signal, which indicates that the correct
number of wait states has occurred and data is valid.
When STERM· is received the ready logic activates
BRDY to the 82596CA, which indicates its willingness
to allow a burst cycle. The 82596CA drives BLAST
inactive for all but the last cycle in a burst. BLAST is
driven active in the last cycle of the transfer to indicate
that when either BRDY or RDY is next returned the
transfer is complete. RDY is always returned in response to BLAST going active.

1-505

AP-344

If the memory controller cannot perform a burst cycle
CBACK will not go active and the ready logic will
return RDY to the 82596CA, which indicates a nonburst multiple-cycle transfer will take place. Unlike the
burst cycle, ADS will go active at the beginning of the
second and all subsequent transfers in the multicycle
transfer and RDY is used to end the cycle rather than
BRDY.

3.2 Clocking
This design uses a clock operating at 66 MHz. It is
divided by a 74F74 flip-flop to generate two 33 MHz
clocks from the Q and Q outputs: CLKI and CLK!.
The MC68030 uses CLKI, but the 82596CA and arbitration logic use CLK!. The clock-to-output-valid delay of the 74F74 is 3.8 to 7.8 ns.

The two data acknowledge signals for the MC68030
(DSACKO and DSACKI) can be combined because the
82596CA only needs one RDY signal. Both DSACK
signals connect to the inputs of an 74F08 AND gate.

3.3 Reset Retiming
The 82596CA reset retiming block is the same as that
shown in Figure 2. The synchronizing flip-flops are
clocked by CLK!. There are two 82596CA specifications for RESET that must be met: the setup time (T23)
and the hold time (T24). The worst-case margin is
shown in Table 6 (all times are in nanoseconds).

3.0 MC68030/82596CA INTERFACE
3.1 Design Specifications
This interface example is based on the following assumptions.
•
•
•
•
•
•

3.4 CA and PORT Generator
The CA and PORT generation block is the same as that
shown in Figure 4 and is based on a 20R4 PLD (10 ns
delay at 33 MHz, 15 ns delay at 25 MHz). At either
speed it is clocked by CLK!. AS, the address lines, and
HIADDR are examined at the rising edge of CLK!.
The worst-case margin to this rising edge limits the
maximum propagation delay of the secondary decoder.
Each margin is calculated separately.

MC68030 CPU.
82596CA LAN coprocessor.
32-bit DRAM memory with burst capability.
DRAM refresh using CAS-before-RAS technique.
33 and 25 MHz operating frequencies.
Interface logic implemented in PLDs where possible.

Because AS is generated later than the address, it is
checked first. The setup time margin to the PLD's flipflop is calculated as follows (all times are in nanoseconds).

• 82596CA signals converted to MC68030 signal
types.
• Refresh request signal asynchronous to 33 MHz
clock.
• Burst accesses attempted whenever possible.

CLKI cycle - max MC68030 AS valid delay
- max CLKlto CLKI skew
- min PLD setup

NOTE:
Many of the circuit elements (e.g., PLDs and flipflops) in this design probably already exist in designs
presently using the MC68030. The extra elements are
provided only for completeness. The final design will
probably require fewer circuit elements.

At 33 MHz = 30 - 15 - 2 - 10
(with 10 ns PLD)
At 25 MHz

(3.1)

3 ns

= 40 - 18 - 2 - 15 = 5 ns
(with 15 ns PLD)

Table 6. 82596CA Worst-Case Reset Timing Margin
82596CA
Frequency
(MHz)

Clock-to·Output Delay
Minimum
Minimum

Minimum
Setup

Minimum
Hold

Margin
Setup
Hold

(nanoseconds)

3.8

I
I

7.8
7.8

I
I

1-506

8.0
10.0

I
I

3.0
3.0

I
I

14.2

0.8

22.2

0.8

inter

AP-344

The address has an additional margin because it is generated almost one-half clock earlier. This additional
margin is calculated as follows.
CLK! cycle

+ CLKl high time
- max MC68030 address valid delay
- max CLK! to CLK! skew
(3.2)
- min PLD setup

At 33 MHz

At 25 MHz

30 + 15 - 21 - 2 - 10
(with 10 ns PLD)
40 + 20 - 25 - 2 - 15
(with 15 ns PLD)

12 ns
18 ns

Next, the worst-case setup and hold times to the
82596CA are calculated for CA and PORT, which
have identical timings. They go active based on the rising edge of CLKI. The setup margins are calculated as
follows.
CLKI cycle

- max PLD output valid delay (3.3)
- min 82596CA input setup

At 33 MHz

30 - 7 - 7 = 16 ns
(with 10 ns PLD)

At 25 MHz

= 40 - 12 -

7 = 21 ns
(with 15 ns PLD)

The hold margins are calculated as follows.
min PLD output valid delay min 82596CA input hold
. = 4 - 3 = 1 ns (at 33 and 25 MHz)

(3.4)

3.5 Bus Arbiter
The bus arbiter is implemented with a 20R8 PLD (10
ns delay at 33 MHz, 15 ns delay at 25 MHz). At either·
speed, it is clocked by CLK 1. The worst-case flip-flop
setup margins to this rising edge is calculated as follows.
CLKI cycle - max 82596CA HOLD
output valid
- min PLD input setup
At 33 MHz

falling edge of CLK I, and because there can be up to
2 ns of skew between CLKI and CLKl, it is not completely safe to directly use BG in the arbiter PLD. Instead it is run through one of the flip-flops in the PLD
to fully synchronize the signal. In the worst case, BG
can go active about the same time as CLKI goes high.
Because the PLD will not be clocked until the next
rising edge of CLK I, there will be at least one full clock
cycle minus the PLD feedback delay for the output to
reach a valid state.
The unused macro-cell in the 20R8 can be used to invert LANCYC to create HLDA to the 82596CA. The
outputs of the arbiter, HLDA and REFCYC, are internally synchronized at their destination, so no output
timing analysis is required.

3.6 Memory Signal Conversion
The memory signal conversion block is implemented as
shown in Section 2.6. A 20R4 PLD (10 ns delay at
33 MHz, 15 ns delay at 25 MHz) is used to convert the
82596CA-type control signals to MC68030-type control signals. When the 82596CA does not have the bus
all the outputs go to a high-impedance state.
The signals SIZI, SIZO, AI, and AO are generated by
using simple combinatorial decodes of BE3, BE2, BEl,
and BEO. The delay will be identical to the PLD propagation delay. The signals NEWAS, NEWDS,
NEWDBEN, and NEWR/W are generated by using
the PLD's registered outputs, which are clocked by
CLK 1. Their states are determined by the state of the
82596CA's signals ADS, W /R, and RDY .
An 82596CA read or write cycle starts with ADS going
active based on the rising edge of CLK 1. NEWAS and
NEWDBEN will go active on the next rising edge of
CLKI. If the cycle is a read cycle NEWDS will also go
active. If it is a write cycle NEWDS will go active one
clock later. In general, the signals go inactive based on
RDY going active. To meet the data hold times
NEWDBEN stays active one extra clock during a write
cycle. NEWR/W is simply the inverted and registered
W/R.

(3.5)
The timing of the PLD is checked next. The 82596CA
control signals must be valid in time to meet the setup
requirements of the PLD's flip-flops. The margin is calculated as follows.

30 - 19 - 10 = 1 ns
(with 10 ns PLD)

At 25 MHz = 40 - 22 - 15 = 3 ns
(with 15 ns PLD)

CLKI cycle - max 82596CA output delay
- PLD input setup

The signal BR does not need to meet any setup or hold
times because it is internally synchronized by the
MC68030. The PLD !!iJ2.-flop setup time for BG is
checked next. BecauseBG can go active 0 ns after the

1-507

At 33 MHz

= 30 - 19 - 10 = 1 ns
(with 10 ns PLD)

At 25 MHz = 40 - 22 - 15 = 3 ns
(with 15 ns PLD)

(3.6)

AP-344

NEWAS goes active based on the rising edge of CLK 1,
which is the same as the falling edge of CLK!. The
PLD clock to output valid delay is 3 to 7 ns maximum
at 33 MHz and 4 to 12 ns maximum at 25 MHz. The
skew between the clocks will be - 2 to + 2 ns. This
translates to a 1 to 5 ns delay at 33 MHz and 2 to 10 ns
delay at 25 MHz, which is within the MC68030 specifications of 2 to 10 ns.

the 82596CA has at least a 5 ns data setup to this edge,
plus 2 ns for the. clock skew. If this cannot be met,
another wait state will be needed for all 82596 memory
read cycles. This can be done by modifying the PLD
equations to delay the assertion of RDY by one or more
clocks. The 82596CA asserts Burst Last (BLAST) during the second clock of the first cycle, which indicates
that the transfer is complete after a single cycle.

ECS and OCS are generated by taking ADS and running it through a tri-state buffer (74F244) that is enabled by HLDA. When the 82596CA has the bus ECS
and OCS will go active about 4 to 8 ns after ADS goes
active.

3.7.3 BURST CYCLE BUS TRANSFERS

The 82596CA attempts burst cycles for any bus request
that requires more than a single data cycle toconsecutive addresses. The starting address must begin on an 8byte boundary (xxxxxxxOh or xxxxxxx8h). The fastest
burst cycle for this design assumes 80 ns interleaved
DRAMs, which allow new data to be strobed into the
82596CA on each clock. The burst cycle requires four
clocks for the first data strobe, but subsequent data
strobes are returned with each clock.

3.7 Wait State and Burst Generator
3.7.1 GENERAL INFORMATION

The 82596CA supports three types of bus transfers: single cycle, multiple cycle, and burst. Each bus cycle is at
least two clocks long and begins with ADS going active
during the first clock and RDY active in the last clock.
A bus cycle contains one or more data transfers, each of
which can be up to 32 bits. Burst cycles can contain as
many as four data transfers, thus, the maximum
amount of data moved during a burst is 16 bytes (4
transfers of 4 bytes each). The wait state and burst generation block inserts the proper number of wait states
during the. bus cycle. For this design it was assumed
that the DRAM would allow for zero wait state accesses for the second through fourth data transfers during a
burst cycle. If slower DRAMs are used, wait states will
need to be inserted in the DSACK and RDY generation circuits.
3.7.2 SINGLE CYCLE TRANSFERS

The fastest single cycle transfer in this design requires
three clocks for the 82596CA. The 82596CA initiates a
cycle after the rising edge of CLK 1 by asserting ADS
and driving W/R: and the address lines (A31-A2) valid. The conversion PLD synchronizes ADS and generates an address strobe (NEWAS). NEWAS is asserted
during the same phase of the clock that a MC68030
would assert AS. NEWAS is also asserted during the
second clock of the 82596CA transfer.
The wait state generator delays the RDY signal to the
82596CA. This provides enough time to meet the data
setup and hold specifications. The 82596CA requires
that data be valid at least 5 ns before the rising edge of
its clock. The MC68030 requires only a I ns setup to its
clock. The system designer will need to guarantee that

Burst cycles begin with the 82596CA driving a valid
address and asserting ADS in the same manner as nonburst cycles. The 82596CA indicates that it is willing to
enter a burst cycle by holding BLAST inactive in the
second clock of the cycle. The ready logic then generates a cache burst request (NEWCBREQ) signal to the
memory controller. If the cache burst acknowledge signal (CBACK) is returned active it indicates that the
memory can operate in burst mode. The ready logic
then waits for the synchronous termination (STERM)
bus handshake signal, which indicates that the correct
number of wait states has occurred and data is valid.
The ready logic then activates BRDY to the 82596CA
to indicate its willingness to permit a burst cycle. The
82596CA drives BLAST inactive for all but the last
cycle in a burst. BLAST is driven active in the last
cycle of the transfer to indicate that when RDY or
BRDY is next returned the transfer is complete. RDY
is always returned in response to BLAST going active.
If the memory controller cannot perform a burst cycle
CBACK will not go active and the ready logic will
return RDY to the 82596CA'to indicate a nonburst
multiple-cycle transfer will take place. This bus transfer
is simply a sequence of two or more single cycle transfers. Unlike the burst cycles, ADS goes active during
the first clock of the second through fourth data transfers. The timing margins for these cycles are identical
to those for nonburst single cycle transfers.
Because the 82596CA requires only one RDY signal,
the two data acknowledge signals for the MC68030
(DSACKO and DSACKl) can be combined. Both
DSACK signals connect to the inputs of an 74F08
AND gate.

1-508

inter

AP-344

4.0 MC68020/82596DX INTERFACE

4.2 Clocking

4.1 Design Specifications
This interface example is based on the following assumptions.
"
•
•
•
•
•
•

MC68020 CPU.
82596DX LAN coprocessor.
32-bit DRAM memory without burst capability.
DRAM refresh using CAS-before-RAS technique.
33 MHz operating frequency.
Interface logic implemented in PLDs where possible.
• 82596DX signals converted to MC68020 signal
types.
• Refresh request signal asynchronous to 33 MHz
clock.

This design uses a clock operating at 66 MHz. The
66 MHz clock, CLK2, is directly by the 82596DX. It is
divided by a 74F74 flip-flop to generate two 33 MHz
clocks from the Q and Q outputs: CLKI and CLK1.
The MC68020 uses CLKl, but the arbitration logic
uses CLK1. The clock-to-output-valid delay of the
74F74 is 3.8 to 7.8 ns. The rising edge of CLKI corresponds to the rising edge of CLK2 at the beginning of
1.

4.3 Reset Retiming
The 82596DX reset retiming block is shown in Figure
11. The synchronizing flip-flops are clocked by CLK2.
There are two 82596DX specifications for RESET that
must be met: the setup time (T23) and the hold time
(T24). The worst-case margin is shown in Table 7.

NOTE:
Many of the circuit elements (e.g., PLDs and flipflops) in this design probably already exist in designs
presently using the MC68020. The extra elements are
provided only for completeness. The final design will
probably require fewer circuit elements.
"

RESET

CLK2-.......- - - - - - '
292076-11

Figure 11. Reset Retiming Block
Table 7. 82596DX/SX Worst-Case Reset Timing Margin
Clock-to-Output Delay
Minimum
Maximum

82596
Frequency
(MHz)
33

Minimum
Setup

Minimum
Hold

Margin
Setup
Hold

(nanoseconds)
3.8

7.8

8.0

3.0

14.2

0.8

3.8

7.8

10.0

3.0

22.2

0.8

3.8

7.8

13.0

4.0

45.2

-0.2

1-509

lme

AP-344

The hold margins are calculated as ,follows.

4.4 CA and PORT Generator
The CA and PORT generation block is the same as that
shown in Figure 4 and is based on a 20R4PLD (IOns
delay a~ MHz, 15 ns delay at 25 MHz) clocked by
CLKl. AS, the address lines, and HIADDR are examined~t t~~ rising e~ge.ofCLKl. The worst-case margin
to this nsmg edge limits the maximum propagation delay of the secondary decoder. Elich margin is calculated
,
separately.

PLD.output valid delay - min 82596DX input hold
+ mm CLK2 to CLKI skew
'(4.4)
= 4 - 3 + 3.S = 4.8 ns (at 33, and 25 MHz)

4.5 Bus Arbiter
The bus arbiter is implemented with a 20RS PLD
(10 ns delay at 33 MHz, 15 ns delay at 25 MHz)
clocked by CLKl. The worst-case margins to this rising
edge is calculated as follows.

Because AS is generated later than the address, it is
chec~ed first. The setup time margin to the PLD's flipflop IS calculated as follows (all times are in nanoseconds).
CLKI cycle - max MC68020 AS valid delay
- max CLKI to CLKI skew
~ min PLD setup

CLKI cycle

- max 82596DX HOLD output
valid
- min PLD input Setup

(4.1)
At 33 MHz

At 33 MHz = 30 - 15 - 2 -10 = 3 ns
(with 10 ns PLD)

The address has an additional margin because it is generated almost one-half clock earlier. This additional
margin is calculated as follows.

+ CLKllow time
- max MC68020 address valid
,
delay
~ max CLKI to.CLKI skew
- min PLD setup

(4.2)

At 33 MHz = 30 + 15 - 21 - 2 .:... 10 = 12 ns
(with 10 ns PLD)
At 25 MHz = 40 + 20 - 25 - 2 .:... 15 = 18 ns
(with 15 ns PLD)
Next, the worst-case setup and hold times to the
82596DX are calculated for CA and PORT, which
have identical timings. They go active based on the rising edge ofCLKl. The setup margins are calculated as
follows.
CLKI cycle - max PLD output valid delay
- min 82596DX input setup
(4.3)
- max CLK2 to CLK I clock skew
At 33 MHz = 30 - 7 - 7 - 7.8 = 8.2 ns
(with 10 nsPLD)
At 25 MHz = 40 - 12 - 7 - 7.S = 13.2 ns
(with 15 ns PLD)

30 + 3.8 - 19 - 10
(with 10 ns PLD)

(4.5)

4.8ns

At 25 MHz = 40 + 3.8 - 22 - 15 = 7.8 ns
(with 15 ns PLD)

At 25 MHz = 40 - 18 - 2 - 15'= 5 ns
(with 15 ns PLD)

CLKI cycle

+ min CLK2 to CLKI skew

The signal BR does not need to meet any setup or hold
times because it is internally synchronized by' the
MC68020. The PLD !!!E.-flop setup time for BO is
checked next. Because BO can go active 0 us after the
falling edge ofCLKI, and because there can be up to 2
ns of skew. between CLKI and CLKI, it is not completely safe to directly use BO in the arbiter PLD. Instead it is
through one of the flip-flops in the PLD
to fully synchronize the signal. In the worst caSe, BO
can go active about the same time as CLK I goes high.
Because the arbiter's flip-flop will not be clocked until
the next rising edge of CLKI, there will be a full clock
cycle minus the PLD feedback delay for the output'to
reach a valid state.

run

The outputs of the arbiter, LANCYC and REFCYC
are internally synchronized at their destination, son~
output timing analysis is required. An external inverter
is required for LANCYC to create HLDA to the
82596DX. If the PLD has an internal inverter then this
will liot be required.

4.6 Memory Signal Conversion
The memory signal conversion block is implemented as
shown in Section 2.6. A 20R4 PLD (10 ns delay at
33 MHz, 15 ns delay at 25 MHz) is used to convert the
82596DX-type control signals to MC68020-type control signals. When the 82596DX does not have the bus
all the outputs go to a high-impedance state.

1-510

intJ

AP-344

The signals SIZI, SIZO, AI, and AO are generated by
using simple combinatorial decodes of BE3, BE2, BEl,
and BEO. The delay will be identical to the PLD propagation delay. The signals NEWAS, NEWDS,
NEWDBEN, and NEWR/W are generated by using
the PLD's registered outputs, which are clocked by
CLK1. Their states are determined by the state of the
82596DX's signals ADS, wIR, and RDY.
An 82596DX read or write cycle starts with ADS going
active based on the rising edge of CLK 1. NEW AS and
NEWDBEN will go active on the next rising edge of
CLK1. If the cycle is a read cycle NEWDS will also go
active. If it is a write cycle NEWDS will go active one
clock later. In general, the signals go inactive based on
RDY going active. To meet the data hold times
NEWDBEN stays active one extra clock during a write
cycle. NEWR/W is simply the inverted and registered

WiR.

The timing of the PLD is checked next. The 82596DX
control signals must be valid in time to meet the setup
requirements of the PLD's flip-flops. The margin is calculated as follows.
CLKI cycle

+ min CLK2 to CLKI skew
- max 82596DX output delay
- PLD input setup

At 33 MHz
At 25 MHz

30 + 3.8 - 19 - 10
(with 10 ns PLD)
40 + 3.8 - 22 - IS
(with IS ns PLD)

(4.6)

RDY active in the last clock. The wait state block inserts the proper number of wait states during the bus
cycle by delaying the RDY signal to the 82596DX. The
fastest single transfer in this design requires three
clocks for the 82596DX. This provides enough time to
meet the data setup and hold specifications. The
82596DX requires that data be valid at least 5 ns before
the rising edge of its clock. The MC68020 requires only
a I ns setup to its clock. The system designer will need
to guarantee that the 82596DX has at least a 5 ns data
setup to this edge, plus 2 ns for the clock skew. If this
cannot be met, another wait state will be needed for all
82596DX memory read cycles. This can be done by
modifying the PLD equations to delay the assertion of
RDY by one or more clocks.
Because the 82596DX requires only one RDY signal,
the two data acknowledge signals for the MC68020
(DSACKO and DSACKI) can be combined. Both
DSACK signals connect to the inputs of an 74F08
AND gate.

5.0 MC68000/82596SX INTERFACE
5.1 Design Specifications
This interface example is based on the following assumptions.

4.8 ns
•
•
•
•

7.8 ns

NEWAS goes active based on the rising edge of CLKI,
which is the same as the falling edge of CLK1. The
PLD clock to output valid delay is 2 to 7 ns maximum.
The skew between the clocks will be - 2 to + 2 ns. This
translates to a 0- to 5 ns delay, which is within the
MC68020 specifications of 2 to 10 ns.
ECS and OCS are generated by taking ADS and running it through a tri-state buffer (74F244) that is enabled by HLDA. When the 82596DX has the bus ECS
and OCS will go active about 8 ns after ADS.

4.7 Wait State Generator
Each 82596DX bus cycle is at least two clocks long and
begins with ADS going active during the first clock and

MC68000 CPU.
82596SX LAN coprocessor.
16-bit DRAM memory without burst capability.
DRAM refresh using CAS-before-RAS technique.

• 16 MHz operating frequency.
• Interface logic implemented in PLDs where possible.
• 82596SX signals converted to MC68000 signal
types.
• Refresh request signal asynchronous to 16 MHz
clock.
NOTE:
Many of the circuit elements (e.g., PLDs and flipflops) in this design probably already exist in designs
presently using the MC68000. The extra elements are
provided only for completeness. The final design will
probably require fewer circuit elements.

1-511

Intel

AP-344

5.2 Clocking

5.5 Bus Arbiter

This design uses a clock operating at 32 MHz. The
32 MHz clock, CLK2, is used directly by the 82596SX.
It is divided by a 74F74 flip-flop to generate two
16 MHz clocks from the Q and Q outputs: CLKI and
CLK1. The'MC68000 uses CLK!, but the arbitration
logic uses CLK1. The clock-to-output-valid delay of
the 74F)4 is 3:8 to 7.8 ns. The rising edge of CLK!
corresponds to the rising edge of CLK2 at the beginning ofep1.

The bus arbiter is implemented with a 20R8-15 PLD
clocked by CLK1. The worst-case margins to this rising
edge is calculated as follows.

5.3 Reset Retiming
The 82596SX reset retiming block is shown in Figure
11. The synchronizing flip-flops are clocked by CLK2.
There are two 82596SX specifications for RESET that
must be met: the setup time (T23) and the hold time
(T24). The worst-case margin is shown in Table 7 (all
times are in nanoseconds).

5.4 CA and PORT Generator
The CA and PORT generation block is the same as that
shown in Figure 4 and is based on a 20R4-!5 PLD
clocked by CLK!. AS, the address lines, HIADDR,
LDS, and CLK! are decoded in a combinatoriai'macro-cell of the 20R4. The macro-cell output is sent to the
input of one of the registered macro-cells, which is
clocked at the rising edge of CLK1. Since propagation
delay through the PLD is much less than the CLK!
cycle time, there will be a large margin on the flip-flop
setup time.

CLK! cycle - max 82596SXoutput
- min PLD input setup
(5.3)
+ min CLK2 to CLK! skew
= 66 - 32 -,- !5 + 3.8 = 22.8 ns
The signal BR does not need to meet any setup or hold
times because it is internally synchronized by the
MC68000. The PLD ~flop setup time for BG is
checked next. Because BG can go active 0 ns after the
falling edge ofCLK!, and because there can be up to.2
ns of skew between CLKl and CLK!, it is not completely safe to directly use BG in the arbiter PLD. Instead it is run through one of the flip·flops in the PLD
to fully synchronize the signal. In the worst case, BG
can go active about the same time as CLK! goes high.
Because the arbiter's flip-flop will not be clocked until
the next rising edge of CLK!, there will be almost 60 ns
for the output to reach a valid state.
The outputs of the arbiter, LANCYC and REFCYC,
are internally synchronized at their destination, so no
output timing analysis is required. An inverter is required for LANCYC to create HLDA to the 82596SX.
If the PLD has an internal inverter then this will not be
required. If not, one of the unused macrocells in the
20R8 can be used to perform the inversion.

'5.6 Memory Signal Conversion
Next, the worst-case setup and hold times to the
82596SX are calculated. The 82596SX timings are identical for both CA and PORT. They go active based on
the rising edge of CLK1. The setup margins are calculated as follows.
CLKI cycle - max PLD output
- min 82596SX input setup
(5.1)
- max CLK2 to CLK! skew
= 66 - !2 - 11 - 7.8 = 35.2 ns
Margins are calculated as follows.
- min PLD output valid delay
- min 82596SX input hold
+ max CLK2 to CLK! skew
= 4 - 6 + 3.8 = 1.8 ns

(5.2)

The memory signal conversion block is implemented as
shown in Section 2.6. A 20R4-15 PLD is used to convert the 82596SX-type control signals to MC68000type control signals. When the 82596SX does not have
the bus all the outputs go to a high-impedance state.
The signals DDS, LDS, and Al are generated by using
simple combinatorial decodes of BHE and BLE. The
delay will be identical to the PLD propagation delay,
which is 15 ns maximum. The signals NEWAS,
NEWDS, NEWDBEN, and NEWR/W are generated
by using the PLD's registered outputs, which are
clocked by CLK1. Their states are determined by the
state of the 82596SX's signals ADS, .ROY, and W/R:.
An 82596SX read or write cycle starts with ADS going
active based on the rising edge of CLK2. NEWAS and
NEWDBEN will go active on the next rising edge of

1-512

intJ

Ap·344

CLK!. If the cycle is a read cycle NEWDS will also go
active. If it is a write cycle NEWDS will go active one
clock later. In general, the signals go inactive based on
ROY going active. To meet the data hold times
NEWDBEN stays active one extra clock during a write
cycle. NEWR/W is simply the inverted and registered
W;R.
.
The timing of the PLD is checked next. The 82596SX
control signals must be valid in time to meet the setup
requirements of the PLD's flip-flops. The margin is calculated as follows.
CLKI cycle

+ min CLK2 to CLKI skew
- max 82596SX output delay
(5.4)
- PLD input setup
= 66 + 3.8 - 36 - 15 = 18.8 ns

NEWAS goes active based on the falling edge of CLK 1,
which is the same as the rising edge of CLK!. The PLD
clock to output valid delay is 5 to 12 ns maximum. The
skew between the clocks will be - 2 to + 2 ns. This
translates to a 3 to 14 ns delay, which is within the
MC68000 specifications of 3 to 40 ns.

5.7 Wait State Generator
The 82596SX bus cycle is at least two clocks long and
begins with ADS going active during the first clock and
RDY active in the last clock. The wait state generation
block inserts the proper number of wait states during
the bus cycle. For this design it was assumed that the
DRAM would allow for zero wait state accesses. If
slower DRAMs are used, wait states will need to be
inserted in the DSACK and RDY generation circuits.
The fastest single cycle transfer in this design requires
three clocks for the 82596SX. The wait state generator
delays the ROY signal to the 82596SX. This provides
enough time to meet the data setup and hold specifications. The 82596SX requires that data be valid at least
5 ns before the rising edge of its clock. The MC68000.
requires only a 1 ns setup to its clock. The system designer will need to guarantee that the 82596SX has at
least a 5 ns data setup to this edge, plus 2 ns for the
clock skew. If this cannot be met, another wait state
will be needed for all 82596 memory read cycles. This
can be done by modifying the PLD equations to delay
the assertion of RDY by one or more clocks.

ECS and OCS are generated by taking ADS and running it through a tri-state buffer (74F244) that is enabled by HLDA. When the 82596SX has the bus ECS
and OCS will go active about 8 ns after ADS.

1-513

inter

AP~344

APPENDIX A
SCHEMATICS
Each schematic includes only the logic needed to interface the 82596 to the M68000. The address and data bus
connections between the two are not currently shown.

1-514

AP-344

A.1 MC68030/82596CA

PAL20R4S

He,

OflAy,u'

'[()'

'[2'

UNCYO'

RErOES-US

ClJ('

ClJ(,.

AS'

Net

He'
HC3

NC4

os·

PORI'

'""'"'
DB'"

1"""1
OR AI2

OR AU

OR AI.

!.OS'

CBJ.C1('

HWIIlR

<><0

HO'
REFDES-U.4

~Il
AS·
HOU>
LOCK

,.
NO'

H02
'FRO'
H03

.ESET
He<
H05

<><0

05'

06'

07'

UNCYC'

"2
0['

RESET

SO,,

suo
su,

ROY'

AS·
AO'
AD2
AD3
AO'
AOS
AO.
AD7
A08
AD'
(OR AID) NSS

DB'"

H03
CSREQ'

PlliOR4S

os-

""
,.

WO'
H02

ClJ('.

AS'

BEl'

''''
SYSRES~

...

ClJ(

ClJ('

,
L..:..
3

•
5

PAL20R4S

ClK

OQO

01'
D
U

0"
03'

H03

caRW

•"
• "
•
~

"
"

KlO'

~"
m'

.O\'

BR'"

0ElAlDY'

He<

'"DE'
U7

BR'

'OS'
ocs'

BGACK"

80fT'
RFCYC"
HlDA

UNCYC' ...._ _ _..J

•
"0

'"
"2
0['

292076-12

1·515

AP-344

A.2 MC68020/82596DX
21
PA120R4B
eLKI

elK'

eLK1'

Hel
ADS'
BED'

CLK2

RW'
AS'
DS'
DBEN'

BEl'
8E2'
BE3'

AO
SIZO
SIZI
AI

WR'
He2
He3
He.
12

srsRESW
elK1'

ROY'
LANcye'

REroES-U6

RESET

PAl20R"B
eLK1'
AS'
AOI
A02
A03
AD.
A05
ADS
A07
A08
AD.
AID

sal'

51'

704f24

PORrHel
He2
Hc.J
HC4

ADS'

OR A12
OR A13
OR A14

1"RA111

18
Yl
16
Y2
14
Y3
12
Y4

AI
A2
A3

[CS'
OCS'

HIAODR

LAHCYC'

GND

U.
1

REFDES-U4
PAL20R6;.

elKI'

AS'

HOLD
LOCK

~Il
3

•
5
S
7

00'

•
•

Nel
Ne2
Hc.J
NC4
GNO

ClK

00'

01'

02'

03'

04'

05'

11
23

"I.
17
16

BREO
LANeye'

20
8R'

HlDA

74F04

BGACK'
RFCYC'
S8G'

100'

101'

22
15

DELAYROY"
ROY'

110
111
112
0['
U5

292076-13

1-516

PAL20R4B
CLK'

ClKI

CLK2

CLI(1'

IS'

BHE'

BLE'

•

WR'

NCI

NC2

ADS'

CLK1'

NC3

SYSRESEI'

RESET

NC4

NCS
LANcye'

!!:

n
G)

~
23

PCLK
11

00'
12
01'

13
02'
14
03'

20
19
18
17

C»

OElAYROY'
SO'

C»
~

DELAYAS'

U'I
cg

,.
100'

17
101'

102'
19
103'

RW'

AS'

UDS'

LDS'

110
111
112
OE'

REfDES-U6

PAL20R8B
a.K1'

RESET

1
2
3

IS'
4
HOLD

LOCK

S
6

NCI
7
BG'
NC2

8
9

RFRCI*
10
NC3
Nt(

11
14

HCS
23
HC6

GNO

PAL20R4B

CLK

CLKI

00'

01'

13
14

02'
03'

04'

OS'

06'

07'

22
21
20
19
18

17
16
IS

BRED
HLOA

UNCYC'
BR'

.A02
A03

SBG'

A04

BGACK'

ADS

RFCYC'

AD6

NC7

~11
3

A07

AD8

110

AD9

111

LOS'

112

HIAOOR

OE'

GHD

4
S
6
7
8
9
10
11
14
23
13

~
~

AOI

CLK

00'

12
01'
13
02'
14
03'

20
19
18
17

NC2
SO'
51'
NC3

15
16
100'

17
101'

18
102'

19
103'
110

22
21
16

NCI (OR Al0)
eA

PORT'

111
112
DE'
REFDES-U4

US
AS'

o
o
o
.....

ROY'

292076-14

inter

Ap·344

APPENDIX B
PLD EQUATIONS
Several conventions are used in the PLO equations.
These are designed to make the. equations easier to understand. In general the equations are designed for
PLO's with fixed macro-cells. If programmable macrocells are available, then some reduction will be possible.

Logical operators are defined as:

Pin signal name assignments are· followed by a comment indicating the pin type:

Where possible, state and truth table formats are used.

• Input = I
• Combinatorial input/output = I/O
• Registered input/output = R, I/O

General comments start with a " in the left-most column.Specific Comments appear on the same line as the
individual equations or terms within the equation. If
there is not room on the right side for the comment to
fit on the same line, then it will be indented on the
following line.

Names for active low signals are followed by an underscore. For example, AS_ is an active low signal and
BREQ is an active high signal.

• Logical ANO = &
• Logical OR = #
• Logical NOT = !

1-518

inter

AP-344

B.1 MC68030/82S9(iCA
Module ARB FLAG' -R3' ;
Title , 82596CA Arbitration for Local Bus
DOCTOR DESIGN, San Diego, CA
pLD20R8-10';
n

************************

Descrption

Rev. B

02/20/90

***********************

FOR:

82596CA / 68030 Interface

.
.

Requestors are granted the bus by using the inverted CPU clock
(CLK1_1. Since CLKl is also used in the equations, it must
connected with a separate pin with a separate name (CCLK1_) •

The refresh request (RFRQ_) is assumed to be an active low
signal having the required 12 ns set-up to the inverted clock
(CLK1). If this set-up cannot be guaranteed, the request
must ~ synchronized through an external flip-flop, clocked
with CLK1_.

SBG_ is the synchronized 68030 Bus Grant (BG_) signal.

This pLD arbitrates between the CPU, the LAN Controller and
the Refresh requestor for the local bus. Refresh requests are
given highest priority, and the 82596 requests given second
highest priority. The CPU no~lly controls the local bus
when no requests are pending.

HLDA is the inverted LANCYC*. Due to a lack of p-terms, HLDA
will be delayed by 1 clock. If a pLD with inverter outputs is
available, then LANCYC* can be inverted and used directly as
HLDA.
n

The Bus Request signal, BREQ, and Backoff, BOFF, are used to
acti~iate the Bus Throttle Timers and backoff function. The
equations are included but the outputs are always set
inactive. It is left to the system designer to define input
conditions for this signal.

The two states LAN OFF and LAN RF can be used if the external
circuitry cannot q;arantee that the 82596 will get off the bus
in time to do refresh cycles. If these states are used, a
larger pLD will be needed to generate the BGACK to the 68030.
UNUSED INPUT PINS
UNUSED OUTPUT PINS (REGISTERED I
UNUSED OUTPUT PINS (COMBINATORIAL)

o
o

n****************************************************************
292076-35

1-519

inter

Ap·344

arb Device 'P20R8';
CLK1_
CCLK1_
AS_
HOLD
LOCK
NCl
BG_
NC2
RFRQ_
NC3
RESET

Pin
Pin
pin
Pin
Pin
Pin
Pin
pin
Pin
Pin
Pin
Pin

GND

1; "I"
2; "I"

VCC
NC5
SBG_
BREQ
LANCYC_

3; "I"

4;
5;
6;
7;
8;
9;
10;
11;
12;

"I"
"I"
"I"
"I"

BGACK_
BOFF_
RFCYC_
HLDA
NC4
OE_

"I"
"I"
"I"
"I"

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24;
23;
22;
21;
20;
19;
18;
17;
16;
15;
14;
13;

"I"
"R,
"R,
"R,
"R,
"R,
"R,
"R,
"R,
"I"
"I"

I/O"
I/O"
I/O"
I/O"
I/O"
I/O"'
I/O"
I/O"

MODE
IDLE
REQ
RF_CYC
LAN_CYC
PRE_CHG
"

[1,1,1,1,1];
[0,1,1,1,1];
[1,0,0,1,1];
[1,0,1,0,1];
[1,0,1,1,1];

"
"
"
"

Generic request to CPU for local bus.
Refresh request has been granted.
LAN request has been granted.
Required for back-to-back cycles.

The following two lines are used only if the 82596 is required to
be kicked off the bus. Most designs will not require these states.

.. LAN_OFF - [1,0,1,0,0];
.. LAN_ON - [1,0,0,1,0];

Refresh Request forces 82596 off bus •
Refresh Request returns control to 82596

Equations
BREQ

•• 0;

t !SBG_

& !BG_
f !SBG_ & !CCLK1_

HLDA :- !LANCYC_;

" Bus Throttle conditions will need to be
" defined by the system designer.
" Set synchronized bus grant during high clock
to phase meet setup to ARB PLD •.
" Hold until processor bus grant goes away.
.. Hold through low clock phase to met setup.
" Create HLDA from inverted LANCYC_.
292076-36

1-520

inter
MODE

AP-344

:= RESET & IDLE;

Initialize state machine to IDLE State on reset.

State_Diagram IN arb MODE
state IDLE

IF (!RFRQ_ t HOLD) THEN REO
ELSE IDLE;

state REO

CASE (!RFRO_ & ! SBG )
(HOLD & RFRO_ & ! SBG_I
(! «( !RFRO_ & !SBG_)
t (HOLD & RFRQ_ & SBG_»)
ENDCASE;

:RF_CYC;
:LAN_CYC;

CASE (RFRQ_ & ! HOLD , SBG_)
(RFRO_ & HOLD)
(!RFRQ_)
ENDCASE;

: IDLE;
:E'RE_CHG;
:RF_CYC;

CASE (!HOLD
( !HOLD
( HOLD
( HOLD
ENDCASE;

: IDLE;
:E'RE_CHG;
: LAN_Off;
:LAN_CYC;

state LAN_CYC

&
&
&
&

RFRO_ & !LOCK & SBG_)
!RFRO_ & !LOCK)
!RFRO_ & !LOCK)
RFRtU

CASE ( RFRO_ , !HOLD & !LOCK , SBG_)
( ! RFRO_ , ! LOCK)
( RFRO_ & HOLD)
( RFR(L , ! HOLD , ! LOCK , ! SBG_)
ENDCASE;
n

state LAN_OFF

: REO;

: IDLE;
:RF_CYC;
:LAN_CYC;
:E'RE_CHG;

IF (!HOLD) THEN LAN_RF
ELSE LAN_OFF;
IF (RFRQ_) THEN LAN_CYC
ELSE LAN_RF;

.
II

******************* Revision History ************************
Rev. A 01/03/90 - KKP - First Version
Rev. B 02/20/90 - KKP - E'ut BG_ Synchroniziation into E'LD •

***************************************************************

end ARB
292076-37

1-521

inter

AP·344

Module CAPORT FLAG '-R3';
Title '82596CA Channel Attention and Port
DOCTOR DESIGN, San Diego, CA
PLD20R4-15' ;
n

************************

FOR:

Descrption

Rev. A

01/03/90

***********************

82596CA / 68030 Interface

This PLO decodes the 68030 address lines and generates the
Channel 'Attention and PORT signals to the 82596. The choice
of address is of address is left to the system designer.
Nine address decode lines are available. They could be
connected to A31-A23. NC1, NC2, NC3, and NC4 are
combinatorial outputs. They can be used as extra address
inputs. NC5 is a standard input that is also available as
an extra address term. If even more decode lines are required,
then the HIADDR input is for the output of the external
decoder. This decode must be done in less than 16 ns.
In the line ADDR = [A09,A08, .•.• ], the values for A09-A01
should be set high or low (inverted) for the desired range.
The decode values for CA_ACC and PORT_ACC (110 and 220) are
arbitrary and can be modified as needed.
SO_ and Sl_ are state bits used for generating wait states for
PORT_ assertion.

~SED

~SED
~SED

INPUT PINS
OUTPUT PINS (REGISTERED)
OUTPUT PINS (COMBINATORIAL)

1
0
4

***************************************************************

caport Device 'P20R4';
CLK1_

A01
AS

A02
A03
A04
A05
A06
A07
A08
A09
GND

Pin
Pin
pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

1;
2;
3;
4;
5;
6;
7;
8;
9;
10;

"I"
"I"
"I"
"I"
"I"

"I"
"I"
"I"
"I"
III"

11; "I"

12;

VCC
HIADDR
NC1
NC2
CA
SOSlPORT_
NC3
NC4
NC5
OE-

Pin
Pin
Pin
Pin
pin
Pin
Pin
Pin
Pin
Pin
pin
Pin

24;
23;
22;
21;
20;
19;
18;
17;
16;
15;
14;
13;

"I"
"I/O"
"I/O"
"R,I/O"

"R,I/O"
"R,I/O"
"R,I/O"
"I/O"
"I/O"
'II"

"I"
292076-38

1-522

intJ

AP-344

"Declarations

x,C

- .x., .c.;

ADDR

- [A09,A08,A07,A06,A05,A04,A03,A02,A01,X,X,X];

CA-ACC
I

(ADDR -- "hllO) , HIADDR' !AS_ I;

MACRO

(ADDR -- "h220)
MODE

IDLE
PORT_SET
PORT_HLD1 PORT_HLD2 ACCESS_OFFCA_SET
=
CA_HLD1
CA_HLD2

" User defined address.

HIADDR , !AS_ I;

[CA,PORT_,SO_, Sl_l';
[
[
[
[
[
[
[
[

1,
1,
1,
1,
1,
0,
0,
0, .

1,
0,
0,
0,
1,
1,
1,
1,

1 , 1
1
1
1
0
0
0
0
0
1
1
1
0
0
0

]
]
]
]
]
]
]
]

;
;

;

;
;

;

;
;

Set PORT_ to 82596.
Hold for one clock state.
II Hold for a second clock state.
II Deassert PORT_ and CA.
" Set CA to 82596.
II Hold for one clock state.
II Hold for a second clock state.

Equations
State-Piagram IN caport MODE
: CASE

(PORT_ACC)
(CA_ACC)
(!(PORT_ACC t CA_ACC»
ENDCASE;

state IDLE

: PORT_SET;
:CA_SET;
: IDLE;

state PORT_SET
state PORT_HLDl
state PORT_HLD2

GOTO ACCESS_OFF;

state ACCESS_OFF

IF AS_ THEN IDLE
ELSE ACCESS_OFF;

state CA_SET
state CA_HLD1
state CA_HLD2

**************** Revision History ***************************

Rev. A

1/3/90 - KKP - First Version.

***************************************************************

end CAPORT
292076-39

1-523

AP~344

Module CNVRT FLAG '-R3';
Title '82596CA Signal Conversion
DOCTOR DESIGN, San Diego, CA
PL020R4-10';
n

************************
FOR:

Rev. A

Descrption

01/03/90

***********************

82596CA / 68030 Interface

This PLO converts the 82596 signals to 68030 type signals.

DELAYAS_ is generated in the ROY PLO to delay AS_ until it is
known-whether a multiple or burst transfer is to take place.

"
"

A PLO 20R4 was used in this example, requiring seperate
output enables (LANCYC_ and LANCYC2_, connected external to
the PLO) for the registered and latched outputs.
NEWRW , NEWAS , NEWDS , and NEWDBEN are registered outputs.
NEWSIZO, NEWSIZ1, NEWAO, and NEWA1 are combinatorial outputs.
All of these signals will be enabled when the 82596 has
control of the local bus, otherwise they will be tri-stated.

The combinatorial outputs are generated using a truth table.
For completeness, default settings are included for the
impossible BEt input combinations.
UNUSED INPUT PINS
UNUSED OUTPUT PINS (REGISTERED)
UNUSED OUTPUT PINS (COMBINATORIAL)

3
0
0

" ***************************************************************
cnvrt Device 'P20R4';
CLKl
NC1
DELAYAS_
BEO
BE 1_
BE2_
BE3_
WR_
NC2
NC3
NEWCBRQ_
GND

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

1;
2;
3;
4;
5;
6;
7;
8;
9;
10;

"I"
"I"
"I"

"I"
nl n
"In
"I"
"I"
"I"
"In
11; "I"
12;

VCC
Pin 24;
ROY_
Pin 23; "I"
Pin 22; nI/O"
NEwAO
Pin 21; "I/on
NEWSIZO
Pin 20; nR,I/o n
NEWRW_
NEWAS_
Pin 19; "R,I/on
NEWDS_
Pin 18; "R,I/O"
NEWDBEN_ Pin 17; "R,I/O"
Pin 16; nI/O"
NEWSIZ1
Pin 15; nI/O"
NEWA1
14; nl n
LANCYC2
- Pin
LANCYC_
Pin 13; nI"
292076-40

1-524

inter

AP-344

Equations
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE

NEWAS_
NEWDS_
NEWDBEN_
NEWRW_
NEWSIZO
NEWSIZl
NEWAO
NEWAl

!NEWAS_

!LANCYC_;
!LANCYC_;
!LANCYC_;
!LANCYC_;
!LANCYC2_;
!LANCYC2_;
!LANCYC2_;
!LANCYC2_;

••

!DELAYAS_
f !NEWAS_ & !NEWCBRQ_;

f
f

n Start after BLAST valid.
n Hold through multiple/burst transfer.

!WR_ & !DELAYAS_
WR_ & !NEWDBEN_ & RDY_
!NEWDS_ & !NEWCBRQ_;

n Start DS_ with AS_ during read cycle.
n Delay DS_ by 1 clock during a write cycle.
n Hold until clock following RDY_ set.

! NEWDBEN_ :!DELAYAS_
f !WR_
f WR_

&
&

!NEWDBEN_
!NEWDBEN_

&
&

n Enable data transceivers as soon as 82596
begins its cycle.
n Hold as long as AS_ during read.
n Longer data hold during a write.

RDY_
!NEWAS_;

ninvert WR to match processor
n The following truth table converts the byte enable signals from
n the 82596 into the 68030 SIZ signals and address lines AO and
n Al.
Truth_Table
[BE3_,BE2_,BE1_,BEO_,LANCYC2_J -> [NEWSIZ1,NEWSIZO,NEWA1,NEWAOJ
X

1
1
1
1
0
1
1
0
1
0
0

,
,
,

,
,

,
,
,

,
,

1
1
1
0
0

1
0
0
0
0

,
,
,
,

1
1

,
,

0
0
0
0

,
,

0
0
1
1
1

,
,
,

,
,
,
,

0
0
0

0
0
0
, 0

,
,

,
,
,
,

1
1
1
1
1
1

0
0
0

0
0
0
0
0

J
'J
J
J
J
J
J
J
J
J
J
J

->
->
->
->
->
->
->
->
->
->
->
->

[
[
[
[
[
[
[
[
[
[
[

1
1

[

1
1
0
0

1
1

1
1
1
0

1
0

1
1

1-525

1
1
1
1

1
1
1

0
0

1
0
0
0
0
0

0
0
0

1
0

°°

)

J;
J;
J;
J;
J;
J;
J;
J;
J;
J;
J;
J;
292076-41

intJ
"

The following BE' input combinations are illegal and will
result in erroneous data transfers.
[X
[0
[0

AP-344

, 0
, 1
1

, 1

, 0

-> [

, 0

, X

-> t

->[

1
1
1

1
1

] ;
] ;
] ;

**************** Revision History ***************************

Rev. A

1/3/90 - KKP - First version.

" ***************************************************************

end CNVRT
292076-42

1-526

AP-344

Module RDY FLAG' -R3' ;
Title , 82596CA Ready and Burst Cycle Logic
DOCTOR DESIGN, San Diego, CA
PLD20R4-10' ;
" ************************

.
"

Descrption

Rev. A

01/03/90

***********************

This PLD generates the RDY_ and BRDY_ signals to the 82596.
It also generates the Burst Request (CBREO_) signal to the
memory controller. It uses the 68030 signals Address Strobe
(AS_), Data Strobe (DS_), Data Bus Enable (DBEN_), Data
Acknowledge (DSACK_) and Synchronous Termination (STERM_). It
also uses Cache Burst Acknowledge (CBACK_) from the memory
controller and Burst Last (BLAST_) from the 82596. The
DELAYAS signal is used to delay the generation of AS to the
memory controller in order to determine whether a bur;t transfer
is about to take place. Because CLK1_ is needed for both the
flip-flop registers and in the combinatorial equations, it
is connected to both pins 1 and 2. Two separate names are
required in the equations (CLK1_ and CCLK1_) .
The first three burst data transfers between the 82596 and the
memory will be acknowledged with the BRDY_ signal. The last
(fourth) burst data transfer cycle will be acknowledged with a
RDY_.
This PLD mU8t be 10 ns or faster to meet BRDY set-up to CLK1_
on 82596.
The output DELAYRDY_ is only used inside this PLD to generate
a delay for the RDY_ signal to the 82596.
UNUSED INPUT PINS
UNUSED OUTPUT PINS (REGISTERED)
UNUSED OUTPUT PINS (COMBINATORIAL)

2
1
1

***************************************************************

rdy Device 'P20R4';
CLK1_
CCLK1AS
DS_
STERM_
DBEN_
ADS_
CBACK_
NC1
DSACK_
BLAST_
GND

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

1;
2;
3;
4;
5;
6;

til"
III"

"I"
"I"
"I"
"I"
7; "I"
8; "I"
9; "I"
10; "I"
11; "I"
12;

VCC
NC2
RDY_
BRDY_
DELAYAS_
SO
NEWCBREO_
NC3
DELAYRDY_
NC4
LANCYC_
OE_

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24;
23;
22;
21;
20;
19;
18;
17;
16;
15;
14;
13;

"I"
"I/O"
"I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"I/O"
"I/O"
"In

"I"
292076-43

1·527

AP-344

"Declarations

IDLE
BLST_WT
NO_BURST
BRST_CYC
STERM_1
STERM~2

STERM_3

[1,1,1];
[0,1,1];
[1,0,1];
[0,0,1];
[0,0,0];
[0,1,0];
[1,1,0];

" Wait for BLAST to determine if burst data transfer.
" BLAST_ active so no burst transfer.
"BLAST not active so multiple or burst transfer.
n Wait for acknowledge.
n Wait for acknowledge.
n Wait for acknowledge.

Equations
!ROY_

- !BLAST_ & !DELAYROY_ & CCLK1_ & !AS_ & CBACK_
n Return ROY_ whenever BLAST_ asse.rted.
j
!STERM & NEWCBREQ
n Fou~th burst transfer or synchronous transfer.
# !ROY_ & !DBEN_;
n Hold ROY_ until data requirement met.
- !STERM_ & !NEWCBREQ & !CBACK
n Assert BROY_ durIng burst oycles
j !BROY
& !CCLK1 ;
n Hold so recognized on rising edge of CLK1_ to 82596.

!DS_ & !LANCYC_ & !CCLK1_
# !DELAYRDY_ & !AS_;

Delay ROY for data setup •
.. Hold until end of data cycle.
II

State_Diagram IN rdy MODE
state IDLE

IF !ADS_ THEN BLST_WT
,ELSE IDLE;
IF !BLAST_ THEN NO_BURST
ELSE BRST_CYC;
GOTO IDLE;
CASE (!BROY & !CBACK_)
« !BROY_ & CBACK_) # !BLAST_)
(BRDY_ & BLAST_)
ENDCASE;

STERM_1;
IDLE;
BRST_CYC;

CASE (!BROY_ & !CBACK_)
«!BROY_ & CBACK_)
(BROY_ & BLAST_)
ENDCASE;

STERM_2;
IDLE;
STERM_1;

!BLAST_)

292076-44

1·528

intJ

AP-344

CASE (!BRDY_ & !CBACK_)
«!BRDY_ & CBACK_) t !BLAST_}
(BRDY_ & BLAST_)
ENDCASE;

STERM_3;
IDLE;
STERM_2;

IF (!BRDY_ • !BLAST_) THEN IDLE
ELSE STERM_3;

.. ****************
Rev. A

Revision History

***************************

1/20/90 - KKP - First Version.

.. ***************************************************************

end RDY
292076-45

1-529

inter

AP-344

8.2 MC6802Ol82596DX
Moelule ARB FLAG '-R3';
Title '82596~X Arbitration for Local Bus
DOCTOR DESIGN, San Diego, CA
PLD20R6-l0';
n

************************
FOR:

Descrption

Rev. A

01/12/90

***********************

82596DX / 68020 Interface

n
II
II

.
.
.
.

This PLD arbitrates between the CPU, the LAN Controller anel
the Refresh reqgestor for the local bus. Refresh reqgests are
given highest priority, anel the 82596DX reqgests given seconel
highest priority. The CPU normally controls the local bus
when no requests are pending. The RDY_ acknowleclge signal to
the 82596DX is also generated in this PLD. The signal
DELAYRDY_ is an embeclcleel signal useel only in this PLD to
generate RDY_ •
Requestors are granteel the bus by using the inverteel CPU clock
(CLK1). Because is requireel for both the registereel anel'
combinatorial terms, CLK1is connected to both the clock anel a
combinatorial input. The combinatorial teen is calleel CCLK1.
The refresh request (RFRQ_) is assumeel to be an active low
signal having the requirecl 12 ns set-up to CLK1. If this
set-up cannot be guaranteeel, the request must be synchronizeel
through an external flip-flop, clockeel with CLK1.
The SBG_ signal is the synchronizeel 68020 Bus Grant (BG_)
signal.
Because the 82596 uses anel active-high HOLD, LANCYC_ is
inverteel with an external 74F04;

.
..
II

The eqgations anel marco-cells are allocateel for the Bus
Request (BREQ) signal, which is useel to activiate the 82596DX
Bus Throttle Timers. In these equations it is set inactive •
It is left to the system clesigner to clefine input conelitions
for this signal.

UNUSED INPUT PINS
UNUSED OUTPUT PINS (COMBINATORIAL)
UNUSED OUTPUT PINS (REGISTERED)

o
o

***************************************************************
292076-46

1-530

intJ

AP-344

arb Device 'P20R6'i
CLKl
CCLKl
AS_
HOLD
LOCK
DS_
BG_
DBEN_
RFRQ_
NCl
NC2
GND

Pin
Pin
Pin
Pin
Pin
Pin
pin
Pin
Pin
Pin
Pin
Pin

VCC
NC3
DELAYRDY_
BREQ
LANCYC_
BR_
BGACK_
RFCYC_
SBG_
RDY_
NC4
OE_

"I"
"I"
"I"
"I"
"I"
"I"
"I"
"I"
"I"
"I"
11; "I"
12i
li
2i
3i
4i
5i
6i
7i
8;
9;
10;

MODE

[BR_,BGACK_,RFCYC_,LANCYC_];

IDLE
REQ
RF_CYC
LAN_CYC
PRE_CHG

[1,1,1,1];
[0,1,1,1];
[1,0,0,1];
[l,O,l,O]i
[1,0,1,1];

"
"
"
"

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24i
23i
22i
21i
20i
19i
18i
17;
16;
15;
14;
13;

"I"
"1/0"

"R,I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"1/0"

"I"
"I"

Generic request to CPU for local bus.
Refresh request has been granted.
LAN request has been granted.
Required for back-to-back cycles.

Equations
BREQ

:= 0;

!SBG_ = !BG_ , CCLKl
f !SBG_' !BG_
f !SBG_' !CCLK1;

" Bus Throttle conditions will need
" to be defined by the system designer.
" Set· during high phase of ARB clock to
meet setup time into PLD.
n Hold with processor bus grant.
n Hold through low phase of clock to meet setup time.

!DS_' !LANCYC_, !CCLKl
I !DELAYRDY_' !AS_;

!DELAYRDY_ , CCLKl '!AS_

t !RDY_ , !DBEN_;

" Delay RDY_ for data set-up.
" Hold until end of data cycle.

Return RDY_ after delay while
data cycle still in progress.
.. Hold until end of data cycle.

292076-47

1-531

intJ

AP-344

State_Diagram IN arb MODE
state IDLE

IF (! RFRO_

f HOLD) THEN REO
ELSE IDLE;

state REO

"
"

CASE (! RFRO_ & ! SBG )
( HOLD & RFRO_)
(! « !RFRO & !SBG_)
f (HOLD"& RFRO_ & SBG_»)
ENDCASE;

:RF_CYC;
:LAN_CYC;

CASE (RFRQ_ & !HOLD)
(RFRO_ & HOLD)
(!RFRO_)
ENDCASE;

: IDLE;
:PRE_CHG;
:RF_CYC;

CASE (!HOLD & RFRO_ 6i !LOCK)
( ! HOLD & ! RFRO_ & ! LOCK)
(HOLD)
ENDCASE;

: IDLE;
:PRE_CHG;
:LAN_CYC;

CASE (RFRO_ & !.HOLD & ! LOCK)
(RFRQ_ & HOLD)
( ! RFRO_ & ! LOCK)
( ! SBG_ & RFRO_ & ! HOLD & ! LOCK)
ENDCASE;

: IDLE;
:LAN_CYC;
:RF_CYC;
:PRE_CHG;

*******************
Rev. A
Rev. B

:REO;

Revision History

************************

01/12/90 - KKP - First Version
02/20/90 - KKP - Moved BG_ synchronization into PLD.

******~*********************************************** *********

end ARB
292076-48

1-532

inter

AP-344

Module CAPORT FLAG '-R3';
Title '82596DX Channel Attention and Port
DOCTOR DESIGN, San Diego, CA
PL020R4-15';
************************

FOR:

Rev. A

Descrption

01/12/90

***********************

82596DX / 68020 Interface

This PLO decodes the 68020 address lines and generates the
Channel Attention and PORT_ to the 82596DX. The choice of
address is left to the system designer.
Nine address decode lines are available. They could be
connected to A31-A23. NC1, NC2, NC3, and NC4 are
combinatorial outputs. They can be used as extra address
inputs. NC5 is a standard input that is also available as
an extra address term. If even more decode lines are required,
then the HIADDR input is for the output of the external
decoder. This decode must be done in less than 22 ns.
In the line ADDR = [A09,A08, .•.. ], the values for A09-A01
should be set high or low (inverted) for the desired range.
The decode values for CA_ACC and PORT_ACC (110 and 220) are
arbitrary and can be modified as needed.
SO_ AND Sl are state bits used for generating wait states for
PORT_ asse;tion.
UNUSED INPUT PINS
UNUSE~ OUTPUT PINS (REGISTERED)
UNUSED OUTPUT PINS (COMBINATORIAL)

1
0
4

" ***************************************************************

caport Device 'P20R4';
CLK1_
AS_
A01
AD2
AD3
A04
AD5
A06
A07
AD8
A09
GND

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

1;
2;
3;
4;
5;
6;
7;
8;
9;
10;
11;
12;

ifI"

"I"
"I"
"lit
"I"

ur"
"I"
"In

"I"
"In
III"

VCC
HIADDR
NC1
NC2
CA
SO
51
PORT_
NC3
NC4
NC5
OE

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24;
23;
22;
21;
20;
19;
18;
17;
16;
15;
14;
13;

"I"

"I/O"
"I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"I/O"
"I/O"

"I"
"I"
292076-49

1-533

AP-344

Declarations

x,c

- .x.,.c.;

ADDR

[A09,A08,A07,A06,A05,A04,A03,A02,A01,X,X,X];

CA_ACC

MACRO

(ADDR -- "hllO) , HIADDR ,

!AS_ I;

PORT_ACC

MACRO

(ADDR-- "h220) , HIADDR ,

!AS_ I;

User defined address.

292076-50

1-534

inter

Ap·344

MODE

[CA,PORT_,SO_,Sl_];

m
[ 1,
IDLE
PORT_SET
[ 1,
[ 1,
PORT_HLD1
[ 1,
PORT_HLD2
ACCESS_OFF - [ 1,
CA_SET
[ 0,
[ 0,
CA_HLD1
[ 0,
CA_HLD2

1,
0,
0,
0,
1,
1,
1,
1,

1
1
0
0
0
1
0
0

1 ];
1 1;
1 ];
0 ];
0 ];
1 1;
1 ];
0 ];

n
n

..
•
..
..
..

Set PORT_ to 82596DX.
Hold for one clock state.
Hold for a second clock state.
Deassert PORT_ and CA •
Set CA to 82596DX.
Hold for one clock state.
Hold for a second clock state.

Equations
State_Diagram IN caport MODE
state IDLE

: CASE

(PORT_ACC)
(CA_ACC)
(! (PORT_ACC i CA_ACC»
ENDCASE;

: PORT_SET;
:CA_SET;
: IDLE;

state PORT_SET
state PORT_HLD1
state PORT_HLD2

GOTO ACCESS_OFF;

state ACCESS_OFF

IF AS_ THEN IDLE
ELSE ACCESS_OFF;

state CA_SET
state CA_HLD1

GOTO CA_HLD2;

state CA_HLD2

GOTO ACCESS_OFF;

****************' Revision History ***************************
Rev. A

1/3/90 - KKP - First Version.

***************************************************************

end CAPORT
292076-51

1·535

inter

AP·344

Module CNVRT FLAG '-R3';
Title '82596DX Signal Conversion
DOCTOR DESIGN, San Diego, CA
PLD20R4-10';

" ************************
FOR:

Rev. A

Descrption

.1/12/90

.***********************

82596DX / 68020 Interface

This PLO converts the 82596DX signals to 68020 type signals.
These signals will be enabled when the 82596DX has control of
the local bus (LANCYC_ is low), otherwise they will be
tri-stated.

A PLO 20R4 was used in this example, requiring seperate
enables, LANCYC_ and LANCYC2_, which are the same signal
external to the PLO. If the PLO does not require separate
output enables for registered and latched outputs then this is
not required •
NEWRW_, NEWAS_, NEWDS_, and NEWDBEN_ are registered outputs.
NEWSIZO, NEWSIZ1, NEWAO, and NEWA1 are combinatorial outputs.

.
.
.
n

The combinatorial outputs are generated using a truth table •
For completeness, default settings are included for the
impossible BEt input combinations •
UNUSED INPUT PINS
UNUSED OUTPUT PINS (COMBINATORIAL)
UNUSED OUTPUT PINS (REGISTERED)

4
0
0

***************************************************************

cnvrt Device 'P20R4';
CLK1_
NC1
ADS_
BEO
BE 1_
BE2
BE3_
WR_
NC2
NC3
NC4
GND

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

1;
2;
3;
4;
5;
6;
7;
8;
9;
10;
11;

12;

"I"
"I"

"I"
"1"

"I"
"I"

"I"
nI"

"I"
"In

"I"

VCC
RDY_
NEWAO
NEWSIZO
NEWRW_
NEWAS
NEWDS
NEWDBEN_
NEWSIZ1
NEWAl
LANCYC2
LANCYC_

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24;
23;
22;
21;
20;
19;
18;
17;
16;
15;
14;
13;

"I"

"I/O"
"I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"I/O"
"I/O"
"In
"I"

"Declarations

x - .X. ;
292076-52

1-536

inter

AP-344

Equations
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE

NEWAS_
NEWDS_
NEWDBEN_
NEWRW_
NEWSIZO
NEWSIZl
NEWAO
NEWAl

- ! LANCYC_i
- !LANCYC_i
- !LANCYC_i
a
!LANCYC_i
'" ! LANCYC2_i
- !LANCYC2_i
- !LANCYC2_i
• ! LANCYC2_i

!NEWAS_ ••
!ADS_

t !NEWAS_

RDY_i

Start AS_ during 68020 clock low cycle.
Hold until clock following RDY_ set.

!NEWDS_ ••
!WR_ & !ADS_
WR_ & !NEWDBEN_
t !NEWDS_ & RDY_i

Start DS with AS during read.
Delay DS: by 1 clock during write.
Hold until clock following RDY_ set.

RDY_

n
n

!NEWDBEN_ :!ADS_

Enable data transceivers as soon
as 82596DX begins its cycle.
n Hold as long as AS_ during read.
.. Longer data hold during a write.
n
n

t !WR_
t WR_

&
&

!NEWDBEN_
!NEWDBEN_

&
&

RDY_
!NEWAS_ i

n
n

Invert W/R_ to match processor.

The following truth table converts the byte enable signals from
the 82596DX into the 68020 SIZE signals and address lines AO
and Al.

Truth_Table
[BE3_,BE2_,BE1_,BEO_,LANCYC2_] -> [NEWSIZ1,NEWSIZO,NEWA1,NEWAO]
X , X
1 , 1
1 , 1
1 , 1
[ 1 , 0
[ 0 , 0
[ 1
, 1
[ 1 , 0

[
[
[
[

[ 0

[ 1
[

[ 0

,
,
,
,

0
0
0

,
,

,
,
,

,
,
,
,
,

1
1

0
0
0
0
0
0

1
1

,
,

,
,
,
,

,
,

X
1

0
0
0
0
1

1
1
1

1
1

1
0
0
0
0
0
0
0
0
0
0
0

]
]
]
]
]
]

J
]
]

]

1
1

->
->
->
->
->
->
->
->
->
->
->
->

1
1
0
1

1
0
0
1
1

1
1
1
0
1

0
1
0

1
1

1
1
0
0
1

1
1

0
0
0
0

1
1
1
0
1

0
0
1
0

1
0

)

] i
] i
] i
1i
] i
1i
]i
]i
]i
]i
]i
] ;
292076-53

1-537

lme

AP-344

The following BEt input combinations are illegal and will
result in erroneous data trans·fers.

x ,
0
0

0
1

,
,

0
1

,
,

0
X

1
1
1

->
->
->

1
1
1

] ;
] ;
];

**************** Revision History *********************.*.*****

Rev.
II

01/12/90 - KKP - First Version.

***************************************************************

end CNVRT
292076-54

1·538

inter

Ap·344

B.3 MC68OOOI82596SX
Module ARB FLAG '-R3';
Title , 82596SX Arbitration for Local Bus
DOCTOR DESIGN, San Diego, CA
PLD20R8-15';
" ************************

.
.

.
..

."
"

.
.

Rev. A

Descrption

01/20/90

***********************

This PLD arbitrates between the CPU, the LAN COntroller and
the Refresh reqQestor for the local bus. Refresh reqQests are
given highest priority, and the 82596sx reqQests given second
highest priority. The CPU normally controls the local bus
when no reqQests are pending •
ReqQestors are granted the bus by using the 82596SX clock,
CLK1 •
The refresh reqQest (RFRQ_) is assumed to be an active low
signal having the reqQired 12 ns set-up to the clock (CLK1).
If this set-up cannot be guaranteed, the reqQest must be
synchronized through an external flip-flop, clocked with CLK1.
The SBG_ signal is the synchronized 68000 Bus Grant (BG__)
signal. It is be synchronized internally using a flip-flop
clocked with CLK1. Because the 82596SX uses an active high
HLDA, LANCYC_ is inverted using one of the macro-cells.
The eqQations and macro-cells are allocated for the Bus
ReqQest signal, which is used to activiate the Bus Throttle
Timers. It is left to the system designer to define input
conditions for this signal •
UNUSED INPUT PINS
UNUSED OUTPUT PINS (COMBINATORIAL)
UNUSED OUTPUT PINS (REGISTERED)

6
0
1

" ***************************************************************

1-539

AP-344

MODE
IDLE
•
REO
•
RF_CYC •
LAN_CYC·
PRE_CHG

[1,1,1,1];
[0,1,1,1];
[1,0,0,1];
[1,0,1,0];
[1,0,1,1]1

" Generic request to CPU for local bus.
" Refresh request has been granted.
R LAN request has been granted.
R Required for back-to-back cycles.

Equations
BREQ

.. 0;

HLDA

SBG_
MODE

" Bus Throttle conditions will need to be
defined by the sYstem designer.

!LANCYC_ ;

.. BG_

;

.. RESET , IDLE;

" 82596SX requires active-high HLDA.
" Synchronized Bus Grant.
" Initi~lize state machine to IDLE State on reset

State_Diagram IN arb MODE
state IDLE

IF (!RFRQ_ f HOLD I THEN REQ
ELSE IDLE;

state REQ

CASE (! RFRQ_ , ! SBG I
(HOLD & RFRQ_I
(! « !RFRQ_ & !SBG_I
t (HOLD , RFRO_ & SBG_I I I

:RF_CYC;
:LAN_CYC;
:REQ;

ENDCASE;

CASE (RFRQ.. & !HOLD)
(RFRQ.. , HOLD I
( !RFRQ_I
ENOCASE;

: IDLE;
:PRE_CHG;
:RF_CYC;

CASE (! HOLD & RFRO_ ' ! LOCK)
( ! HOLD & ! RFRQ_ & ! LOCK)
(HOLD)
ENOCASE;

: IDLE;
:PRE_CHG;
:LAN_CYC;

CASE (RFRQ_ & ! HOLD & ! LOCKI
(RFRQ.. , HOLD)
( ! RFRQ_ , ! LOCK)
(!SBG_ , RFRQ_' !HOLD & !LOCK)
ENOCASE;

: IDLE;
:LAN_CYC;
:RF_CYC;
:PRE_CHG;

*******************

Revision History

************************

Rev. A 1/20/90 - KKP - First Version
n
n

***************************************************************

end ARB
292076-56

1-540

inter

AP-344

Module CAPORT FLAG' -R3' ;
Title '82596SX Channel Attention and Port
DOCTOR DESIGN, San Diego, CA
PLD20R4-15';
" ************************

Descrption

Rev. A

1/20/90

***********************

FOR:

This PLD decodes the 68000 address lines and generates Channel
Attention and PORT_ to the 82596. The choice of address is
left to the system designer.

"
"
..

..
n ••

82596SX / 68000 Interface

Nine address decode lines are available. They could be
connected to A23-A14. NC1 is a combinatorial outputs and
could be used as extra address input. If even more decode
lines are re~ired, then the HIADDR input is for the output
of the external decoder. This decode must be done in less
than 60 ns.
In the line ADDR - [A09,A08, •••• ], the values for A09-A01
should be set high or low (inverted) for the desired range.
The decode values for CA ACC and PORT ACC (110 and 220) are
arbitrary and can be modified as needed.
50_ AND Sl_ are state bits used for generating wait states for
PORT_ asselition.
UNUSED INPUT PINS
UNUSED OUTPUT PINS (COMBINATORIAL)
UNUSED OUTPUT PINS (REGISTERED)

0
1
2

**.****.****.* •• *.*.*.**.****.*.****.**.*.********************************

caport Device 'P20R4';
CLK1
CCLK1
A01
A02
A03
A04
A05
A06
A07
A08
A09
GND

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

1;
2;
3;
4;
5;
6;
7;
8;
9;
10;

"I"
"I"
III"

"I"

"I"
"I"

"I"
"In

"I"
"I"
11; "I"
12;

VCC
HIADDR
NC1
CA
NC2
SO51_
NC3
PORT_
AS
LDS_
OE_

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24;
23;
22;
21;
20;
19;
18;
17;
16;
15;
14;
13;

"I"
"I/O"
"I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"I/O"
"I/O"
"I"
"I"
292076-57

1-541

AP-344

"Declarations
X,C

- .X., .C.;

ADDR

[A09,A08,A07,A06,A05,A04,A03,A02,A01,X,X,X];
(ADDR

MACRO

"hllO)

HIADDR

User d.efined. address.

!AS_ I;

(ADDR -- "h220) & HIADDR & !AS_ I;
[SO_,Sl_] ;

MODE
IDLE
S'l'll._CN'l

CN'l_1
CN'l_2

[
[
[
[

!AS

1 ];
1 ];
0 ];
0 ];

0,
1,

.. PORT_ or CA has been sent to 82596.
.. Hold for one clock state.
" Hold for a second clock· state.

Equations
lCA

!LDS_

CCLKl

CA_ACC

t ICA & ! (SO_ & !Sl_)
t !CA & CCLK1;

·n

Start when dRta valid on bus.
Hold for at least 2 cloCKs.
Guarantee CA hold time to 82596.

!PORT_ - !LDS_ & !AS_ & ~LKl & PORT_ACC
t !PORT_ & !(SO_ & !Sl_)
t !PORT_ & CCLK1;

" Start when data valid on bus.
n Hold for at least 2 clocks.
n Guarantee PORT_ hold-time 'to 82596.

State_Diagram IN caport MODE
state IDLE

: IF (!POR'l'_ t CA) 'l'HEN STR_CN'l'
ELSE IDLE;

state S'l'ILCNT

IF AS_ THEN IDLE
ELSE CNT_2;

n
n

**************** Revision History ***************************

" Rev. A

1/20/90 - KKP - First Version.

" ***************************************************************

end CAPORT
292076-58

1-542

infef

AP·344

Module ROY FLAG' -R3' ;
Title '82596SX Ready and Signal Conversion
DOCTOR DESIGN, San Diego, CA
PLD20R4-15' ;
************************

Descrption

Rev. A

01/20/90

***********************

This PLO generates the ROY_ signal to the 82596SX. It also
converts the 82596SX signals BHE , BLE , ADS and WR to the
68000 equivalents, UDS, LOS, AS_; and RW_ and mimics-their
timing to the memory controller.
The output DELAYRDY_ is only used inside this PLO to generate
a delay for the ROY_ signal to the 82596SX.
A 20R4 was used for this example requiring a separate input
for the combinatorial enable.
UNUSED INPUT PINS
UNUSED OUTPUT PINS (COMBINATORIAL)
UNUSED OUTPUT PINS (REGISTERED)

5
0
0

"****************************************************************

rdy Device 'P20R4';
CLK1
CCLK1
ASBHE_
BLE_
WR_
NC1
NC2
NC3
ADS_
NC4
GND

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

MODE
IDLE
STR_AS
DLY_ROY
DLY_DS
STR_RDY

1;
2;
3;
4;
5;
6;
7;
8;
9;

"I"
"I"
"III

"II'
"III

"I"
"I"
"III
"111

10; "I"
11;

"I"

12;

VCC
NC5
NEWRW_
NEWAS_
ROY_
DELAYROY_
SODELAYAS
NEWUDS_
NEWLDS_
LANCYC2
LANCYC_

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

24;
23;
22;
21;
20;
19;
18;
17;
16;
15;
14;
13;

"In

"I/O"
"I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"R,I/O"
"I/O"
"I/O"
"I"

"I"

[DELAYAS_,DELAYROY_,ROY_,SO_];

[1,1,1,1] ;
[0,1,1,1] ;
[0,0,1,1];
[0,0,1,0];
[0,0,0,1];

.. Delay AS_ until clock phase of 68000 S2.
.. Delay ROY_ by 1 82596 clock state.
.. Delay UDS_,LOS_ during write cycle.
" Initiate RDY_ for 68000 type 0 wait cycle.
292076-59

1-543

AP-344

Equations
ENABLE
ENABLE
ENABLE
ENABLE

NEWRW_
!LANCYC2_,
NEWUDS_
! LANCYC2_,
NEWLDS_ - ! LANCYC2_1
NEWAS_ - ! LANCYC2_1
WR_,
t !NEWR1C

!NEWAS_,

Invert 82596SX signal
Hold write until AS_ negated

IWR_ & IDELAYAS_ & !BHE_ & !CCLKl & !AS_
I WR_ & !SO_ & IBHE & ICCLKl & IAS_
I !NEWUDS & IWR_ & !DELAYAS_
t !NEWUDS: & WR_ & ROY,

IWR_ & IDELAYAS_ & IBLE_ & !CCLKl & !AS_
t WR_ & !SO_ & !BLE_ & ICCLKl & !AS_
t !NEWUDS & !WR_ & IDELAYAS
t !NEWUDS & WR_ & ROY,

a
a

Start ODS_ with AS_ on read.
Delay ODS on a write.
Hold thru data cycle.

Start LOS with AS on read.
Delay LOS_ on a write.
Hold thru data cycle.

- !DELAYAS_ & !CCLKl"
I !NEWAS_ & IWR_ & IDELAYAS_
t lNEWAS_" WR_ & ROY,
State_Diagram IN rdy MODE
state IDLE

: II!' !ADS_ THEN STR_AS

ELSE IDLE,
state STR_AS

II!' IWR_ THEN DLY_ROY
ELSE DLY_DS;

state DLY_DS

GOTO DLY_ROYI

state DLY_ROY

GOTO STR_ROYI

state STR.-ROY

GOTO roLE I

**************** Revision History ***************************

n
n
n

Rev. A
1/20/90 - KKP - First Version.
*************************.*************************************

end ROY
292076-60

1-544

AP-344

APPENDIX C
TIMING DIAGRAMS
The following section includes the timing diagram for
each specific design. A summary of the timing specifications is also included.

C.2 MC68020/82596DX
•
•
•
•
•
•

C.1 MC68030/82596CA
•
•
•
•
•

Block Diagram
MC68030 arid 82596CA Clock Synchronization
MC68030 and 82596CA CA and PORT Access
MC68030 Local Arbitration (1 page)
82596CA Memory Access (2 pages)

Block Diagram
MC68020 and 82596DX Clock Synchronization
MC68020 and 82596DX CA and PORT Access
MC68020 Local Arbitration (2 pages)
82596DX Memory Access
Timing Summary

C.3 MC68000/82596SX

• Timing Summary

•
•
•
•
•

Block Diagram
MC68000 and 82596SX Clock Synchronization
MC68000 and 82596SX CA and PORT Access
MC68000 Local Arbitration (I page)
82596SX Memory Access (2 pages)

• Timing Summary

1-545

AP-344

111'eI

INTERFACE BETWEEN 68030 AND 82596CA LAN CONTROLLER
Ct l

ClKI*
AS*

Clr

DEC
PAL

68030

82596CA

-fr--+

CA
PORT*

A(0-31)

A(2,31)
0(0-31)

RrRO*

~
~

lOCK*

!
ARB

"'"

LANCYC*a-. HloA

PAL

HOLD

BG*

BGACK*,BR*
oSACKO, 1*

AS*,oS*
R/W*;oBEN*
SIZO, I
CBREO*

BRoYRoy*

l....

MEMORY
SIGNAL
CONVERSION

---M

MA(O-X)T

I:r-----.

BE(0-3)*
AoS*W/R*
BLAST*
Borr*

AI,AO

MEMORY CONTROL

! 1
RAS CAS

OE(HI,lO) WE(0-3)

MEMORY

INT

I'
292076-15

1-546

l
On.

CLK2(66WHz)
CLKI(33WHN )

CLKI'(33WHz)

SYSRESET

:!j

15ns
.........

r,~
~~
.1.74F" ~:~87m.
~

...

..........

-V' - -,-J

:.~
~

S8030

-Vl

121
''''''''''

I...

'-.../

.' -

152
, ....... ,...

"-Jl

~~30

" - '\

S8030

2.2"'n"

... , ... ,,"

273
_._ ..

.....

,-.-r-,

'-~",>-~",--f-/

"-~

,,-.J

J
2- f 0 68030

0-1 0 68030

AS' ~-+-~~

212

182
IU"'''''

Y~.I---+~-+--~--4---+---+---~--H
)5-12 bpal

"P
Co)

5-12 bpal

CA,PORT*

CD
D-l-C 68030

2-2 68030

0(0:31)

1-__+ __-+___1-_-++__-1-+_,,5-12 bpal
~

SO
~

5-12 bpal

__+ __-+___

DOCTOR DESIGN

~3~'&:~RT ACCESS

1/3/90 KKP 030-POrt-CA

~_-++

-+-r_~~

~~.-~

___

~~I~-r--+---r--+---r--~

-+___ __+ __-I-__

,r5~-1~2~b~~I+_ _

+-_~~12bP"

ICA and PORT
I I
~r~ ~~: 113.29 1

5.0

I T1~.30

CA and PORT hold tilTlf
require 4ns

l i T h e 68030 runs off CU.
Zc~~~~;..

The 82596

r::::: :~..

292076-17

(
On.

30ns

60ns

120ns

90ns

T1
SW

150ns

180ns

210 ns

2-40n5

270n8

V- ~ V- ~ ...r- ' -~' -~ ~ V- I\- V- ~ V- I\- ~ ~

f\-

r\\

"-V

"-- J

"-- iJ

"-- J

'L. Vl

\..... Vl

\.....

V- "'

;.-~

r.
r--

3-1982596

"U
I

(,)

5-15bpol

""""

J
5-12bpal

5-12bpol

~12bPOI

DOCTOR DESIGN
Son Diego, CA

68030 Local Bus ArbItration
1/3/90 kkp orb
pg 1 of 2

NOT SHOWN SCALE...
,
Actual cycles will be longer

thon shown.

I
292076-18

(
300ns

270ns

T-State
CLK(33MHZ)

CLK1'(33MHZ)

330nl

360ns

390nl

420ns

450"5

480"1

510ns

5.40"s

- - ' -Lr

V- """"'- ~ ~V- ~V- ' - ~ ' - ..../
~ ./l
~V
L
'---V
' -V
"-- J

5-15 bpal

AS'
:\-1982596

HOLD

RrRO'

U,
(11
a

BR'

»
-a

SBG'(sysnc'd)

Co)
~
~

RrCYC'
5-12 bpol

/-1

LANCYC'(hlda')

BREO'

BOFfDOCTOR DESIGN

Son Diego, CA
68030 Locol Bus Arbitration

1/3/90 kk. "'"
pg2of2

I
292076-19

Stat.

CLK(33WHZ)

CLK1'(33WHZ)

A(D:31 ),BE,LOCK

NEWSIZ,NEWAC.l

ADS',W/R'

..61.....

'""

. . . . I I ..

T2
50

.... ..

.....
T2

"---- V-

"----

T2
50

T2
52

oc-;
/

...

... ..... 11 ..

\..... 1-/
\.... +-"
'--- V- ~ I.J
L 1-/~"---- ~'--- V-l.-

3-1

1-:

opal

'-)-'

jLX

r--

0-082 96CA

X
3-

'---,

3 8 apal

aDal

f7
3 8 opal

cJ,

3 8 apal

3 8opol

L'\,

"tI
I

apal

c,,)

'\,

):0

3 8 apal

3 8 opal

NEWDS·

8 apal

1-/

L\.

'\,

NEWAS·

3-19 82 .6CA

0(0:31)
3 8 opal

3 8 apal

/-~

NEWDBEN'

L'\,
3-228

MS~

t-/

oocrOR
San
Diego. CA
8596 ...mory Acc.ss
1/3/90 kkp IarungLasync-c&

15-308259

15-30825 6CA

.6CA

'\,

BLAST'

3 10 (lpol

3-10 pol

3 10 (lP

ROY

DSACK·

T2
54

3-19825 6CA

apal

3 8 apal

...........

'Q;<'''''

T2
5W

T7~

DELAYAS'

I.-

15
'

~ ~ ~ ~ j..../

L
"---- ~
I\-j.I- "---- V
~

13-1
L-X

.........

121,,,

91
"'

82596 Single Reed Cyclt

'\,

1--7.3n

Dota Road ..L,p - T19-5n. + 2
na(sIcew)=7.bs r.qulred before rblng
edge of 1. 68030 only nMds 1ns.
System designer wnl need to guarant".

82596 Single wrae Cycle

I
292076-20

""""

...30n9
"'

On.

State
CLK(33~HZ)

CLK1'(33UHZ)

A(2:31 ).BE.LOCK

... ,
121

91 ns

.. .....

61
v . .ns
..

12
SW

'-- ~ I""LV

V- "--V- "-- V-- ~ -'

~-1

,.2
,..... ,.'"

.......

152 ,,"

\ .__ ...J

...212
,... ,,.,

'-- r-'

'-- ....I-

242 ,,'"
........

273
LI,oo"",

510

'"'--~
\... ......Il r...

\...-. ~

'-- ..../

ADS'

.......:::7t.

3-10 apol

"""L ./
3-8 opal

3-8 opal

-\.

DELAYAS'

'-/
3-8 opal

3-8 opal

NEWAS'

~-Ioapai

NEWSlZ.NEWAC.l

0(0:31)

(J'I
I\)

O-;!!~

r-r---"

r---'

- - - : 6 1 . 68030

'U
I

r-----'

Co)

",.

6-668030

~-10.P.' r ~

STERt.I'

BRDY'

\..../
/
31'0 ap~/3-IO opal

_\.

ROY'
3-22 82596CA

3-22

3-10 opal

CBACK'

I 82596 BURST READ I

DOCTOR
O£SIGH
Diego.
CA
San
8596 Memory Access
1/3/90 kkp Ian_brsLrcLca

3-8 opal

NEWCBREQ

82~6CA

"-- f..I-'

BLAST'

",.

/
5.9ns -

Data Set-up to the 68030 Is 1 ns. The 82596 requires a 5 ns
set-up to T2. The violates 68030 timing by 5 ns + ns
(clock skew) = 7 n9. The memory controller must guorantee
this tllng or a walt stat will need to be Inserted.

BRDY set-up = t 7 ns from lat,st
STERM acUve to clock rising
edge-PLO delay (10ns)=7ns2ns (skew)=5ns. Need 6ns.
Use faster PLD or Insert a walt
state If STERW cannot be
guaranteed 1 ns tarller.

lit Is assumed that the value _I
of A3:A2 Is Incremented by
the system hardware.

This design assumed Interieaved
memory for burst filling with zero

292076-21

.,,'"
Stat.

CLK(33WHZ)

CLK1'(33WHZ)

A(2:31 ),BE,LOCK

"'u,,~

.,;a

"""'"

T2
52

......'"
5W

"',,,,,,.

'''''''''::'

,~",,;a

" ..",n,.

iLr~",.

510

~ ~ ...r- '--..r-'-- V- ~ ~ ~ V-i'- ....r-"""""\.... -.r- "\.... ~ ~

I\1L -1

..r-'--- ~ l"\..-V- '"""'---fJ

"-- V- ' -~ ~ J l ""'\

ADS'

~
3-8 opal

3-8 opal

L'\,

'7
3-8 apal

3-8 apal

'\,

NEWAS'

3-1982596CA

3-19 82S96CA

3-1982596CA

»
"U

3-1982S96CA

0(0:31)

3-10 opal

ILI-'

OELAYAS·

cJ,

x-,

L-U..-10 opal

NEWSIZ,NEWAC,I

6!668030

STERW'
i Y - . ' 0 epel

BROY'

~ j"

H: H:
/

L'-

ROY'
3-22 82596CA.

3-22

BLAST'

3-10 opal

82~6CA.l

I 82596 BURST WRITEI

I-/-.J

CBACK'

OOCTOR
DES,,"
San
Diego,
CA.
82596 .. emory Aecess
1/3/90 kkp IenJll"ILwr_C&

opal

3-8 opal

'\,

:ro a~~3-10

NEWCBREQ

"'"'""

\:~

This design assumed Interteoved
memory for burst filling with zero
walt states between accesse •.

-'r

BROYMt-up=17 n.fromlatnt.
STERW active to dock rising
edge-PLD delay (10n.)=7n.2n. (lkew);5ns. Nnd tins.
UN fe.star PLD or InNrt a walt
state If STERt.I cannot be
guaranteed 1 ns earler.

lit

Is assumed that the value
of A3:A2 Is Incremented by
the .ystem hardware.

1 1 J

I
292076-22

AP-344

34
35
37
37A
40

MC68030 AND 82596CA TIMING
SUMMARY FOR 33 MHz
MC68030 PARAMETERS
6

82596 puts address out 1 clock phase before
68030 SO.
6A ADS used to generate ECS and OCS before AS
asserted.
7
LANCYC off + buffer off = 15 + 10 = 25 ns.
9
Derived from PLD with clock to Q delay of 8 ns.
12 Derived from PLD with clock to Q delay of 8 ns.
12A Worst case could hold ECS and OCS as long as
20 ns (82596) + delay through buffer. Note to
system designer.
13 Could be a violation for AS, DS to address hold
of 4 ns (82596) = 8 ns (PLD) - 2 ns (skew) =
- 6 ns. System designer must guarantee address
hold.
14 30 ns + 30 ns - 3 ns (common path through
PLD) = 57 ns.
15 30 ns - 2 ns (skew) = 28 ns.
16

41
42
43
44
45
46
53

Latched in ARB PLD
30 ns + 15 ns = 45 ns (1.5 clocks).
30 ns + 15 ns = 45 ns (1.5 clocks).
30 ns in ARB PLD = 1 clock
Asserted with AS, maximum of 8 ns into clock
low cycle. This should meet requirements, system
designer should verify.
Negated in PLD, maximum 8 ns.
Asserted in PLD, maximum 8 ns.
Negated in PLD, maximum 8 ns.
I clock cycle = 30 ns.
Read = 60 ns - 2 ns (skew) = 58 ns. Write =
90 ns ..::. 2 ns = 88 ns.
90 ns - 2 ns = 88 ns.
Data out from 82596 held valid for extra clock
cycle to guarantee.

82596CA PARAMETERS

Floated with LANCYC going high. Minimum
30 ns to next cycle.
17 R/W invalid 1 clock cycle after AS/DS negated.
18 Set with addresses from 82596.
20 Set with addresses from 82596.
21 R/W set 1 clock cycle before AS = 30 ns.
22 Write cycle minimum setup to DS = 30 ns +
30 ns - 8 ns (R/W through PLD) + 5 ns (DS
through common PLD) = 57 ns.
23 82596 provides required time.
25 Minimum time = 30 ns (clock)
8 ns (AS
through PLD) + 4 ns (82596) = 26 ns.
25A 30 ns - 2 ns (skew) = 28 ns.
26 30 ns + 30 ns - 19 ns (82596) + 3 ns (PLD) =
44 ns.
27 Memory controller must guarantee 1 ns.
28 N/A
29 30 ns + 4 ns (82596) - 8 ns (AS through PLD)
= 26 ns.
31 N/A
32 Plenty of time
33 Latched in ARB PLD

T13

30 ns - 12 ns (PLD) = 18 ns.

TI4
TI7
TI8

5 ns through PLD for PORT.
30 ns - 10 ns (PLD) = 20 ns.
3 ns (DBEN through PLD) + 3 ns (PLD) =
6 ns.
May violate by 5 ns + 2 ns (skew) - I ns
(memory controller) = 6 ns. System designer
will need to guarantee extra 2 ns setup time.
3 ns (DS from PLD) + delay through memory controller.
30 ns - 8 ns = 22 ns.
30 ns - 9 ns - 2 ns skew = 19 ns.
4 ns minimum through flip-flop.
3 CLK2 cycles.
30 ns + 15 ns - 18 ns (68030) = 27 ns
15 ns - 12 ns (PLD) + 2 ns (68030) - 2 ns
(skew) = 3 ns
30 ns - 12 ns = 18 ns.
Minimum 3 ns through 10, 12, or 15 ns PLD.

TI9

T20
T21
T23
T24
T26
T27
T28
T29
T30

N/A = Not Applicable
15 ns = '/2 clock period
30 ns = 1 clock period

1-554

inter

AP·344

INTERFACE BETWEEN 68020 AND 82596DX LAN CONTROLLER

CLK1·

C~l

DEC

AS·

PAL

68030

82596CA

~
-+

A(0-31)

CA
PORT·

A(2, 31)
0(0-31 )

RFRQ·

LOCK·

+ "L.....+

LANCYC.a-.

ARB

---+

PAL

HLOA
HOLD

BG·

BGACK·,BR·
DSACKO, 1·

...

AS·,DS·
MEMORY
SIGNAL
CONVERSION

R/W·,DBEN·
SIZO, 1

~:..

MA(O-X)T

~
~

BE(0-3)·
ADS·, W/R

Al,AO

MEMORY CONTROL

ROY·

RAS CAS

OE(HI,LO)

WE(O-3)

1
INT

MEMORY
292076-23

1-555

l
..30nl
.......

.......

On.

15ns

...

.......

...61.....
ns

45n.

I~~F
[~
.1. 7.n.

r---

I---

.... 87...F74

ClK.

ClK'

&.
0'1
m

..........

n.
....

........

, n
121

106ns

,
'36

PHil

I---

ClK2

76n.

Sial.

~;87.m

/J%0
60ns

"'~

f@'H

SYSRESEl*

Lj"

Sync_SYSRESEl*

.n.

~
I

t---I-/

f40.

\'
\

t----

r---

I--I---

"""\

r---

/
~

l'
Co)

.j:Io.
.j:Io.

4-97","4

L,\

RESET

DOCrofI DESIGN

San DJevo. CA
68020 and 825960X Clock Sync
1/12/90 kkp clluync_dx

~
SynchronizatIon circuit Is required
for 68020 SYSRESn- to prevent
m.tost,abfe on RESET to 82596.

6.0n. -

RESET at-up time
123 requires 5 ns.

-I
292076-24

cf
...
State
CLK1'(33~HZ)

CLK(33~HZ)

9'
~I

UI II'"

11
SI

11
S3

"'"

T1
W2

121
ILl"'"

.52
IJL""

TW
W'

T2
S5

~~f- ~ ~ ~ '-- -.r-' -v--\-

---+..
A(0:31).FCO:2.S

30
..,,"'"

'--

"-- -h

0-21 .8020

'--X

"--fI

3-1568020

U,
O!

2.2

L ... LII,.

"--~ ~ ~
f../l

0-30 68020

' - f../

273

2'2

LILnli

LI.;JII:O

'- ~

()0015 68020

V_I

L\.

AS'

182
IClL""

5-12 bpal

5-12 bpel

CA.PORT'

(0)

"..
"..

-..j

()0018 68020

0-0 68020

0(0:31)
5-12 bpal

5-12 bpal

L/I

u.,

5-12 bpel

DOCTOR DESIGN
San
DIego. CA.
68020 CA a: PORT ACCESS
1/12/90 kkp 020_porLDX

r--,u"-r-

CA and Ume
PORTT13.29,
set-up
require 7ns

5-12 bpal

5.0ns

/
CA and PORT hold tlfnl
Tl4,30 requlrl 3ns

1 Th, 68020 runs off ClI·. Th'825961_
runs off ClK1. CA and PORT
aCCIS$8S require 2 walt statlS.

I
292076-25

(
T-State
CLK1'(33WHZ)

CLK(33WHZ)

AS'

__ n::o
30

.... .

<3. " .
........

,,~

r-t-~ r L r-t-r-t-r-t- rL- ~ r-t-r-t-r-t-r-t- ~ ~rL r-t- r-

0-50 68000

A(0:23)

):0
"CJ
I

5-15 bpol

5-15 bpal

Co)
~
~

CA,PORl'
0-5068000

0-0 68000

0(0:15)
5-12 bpol

5-12 bpal

~5-12 bpol

r- 32.8".-

_7.1ns

CA and PORT set-up
t13,29 require 19ns.

tilnll

CA and PORT hold time
T14,3O requlre8ns

-42.1ns-

I 82596

Write Cycle

DOD15 CPU PORT acctss
hold tim. T28 requires 6ns.

oocrOR
San
DIego, CA
68000 CA a: PORT ACCESSS
1/17/90 kkp OOO_porLSX

The 68000 runs off CLfC1'. Th.82592
runs off CLIO. CA and PORT
accnsh require 3 we.H states.

I·

I
292076-31

l
n.
T-Stat.

62
"' ...

.......

248
.....u".

u,un,.
310

.;;1,,<,,,.
372

......"'.
"4

4.6
.."''''.UI

T1
SW

,
186

124
'

558
wJU'"'

!"L-V-- ' - r -IL-V- I\.--V- ' -V- I\-V- "'-V- ~ ..r-"'-V
ClK(33WHZ)
V-l ~ ~ "'-- :~ l\.-v,-IL- .Il ""- r-:- ~ V- i'-- v-J '-- ~ r"\

CLK1'(33WHZ)

S-15bpol

AS'

I-- f--...

3-1982596

HOLD

RfRQ'

m
a>
U1

5- 2bpol

5-12bpal

BR'

(0)
~
~

5-15 bpol

SBG'(.ysn,'d)

RFCYC'

~'2

lANCYC'(hld.,)

BREO'

ocaOROB~
San Dt.go. CA
68030 Locol Bus Arbitration

5-12

~poI

-/-'

HOT SHOWl! SCAlE...
Actuol cyeln will btl Iong.r
than shown.

1/20/90 kkp orbJX

pol

...

- -----

292076-32

State

ClK

ClK1'(16 ~Hl}

.2
.."' ....

"'250
.. "'

188
..........

... ., ...
125
T2

.-J 825~.SX

AOS'.W!R'

r--3

... ..",.,,,

(

11f't-

<4-30 82596SX

4-33 8259.i)

X
5-12 bpol

5-12 bpol

5-15 bpol

5-15 bpoJ

5-12 bpol

5-15 bpol

L,\

f-/

1--,\

NEWAS'

LX
L\.

L,\

OELAYAS'

.,.,..",

t\..-V- t\- V- l\-V- I\-V-l\-V- I\.-- V- i'-V- I\-V- 1\
l.,Il- ~ V- I\-V-I\- ~
Vl ~ Vl tL- Vl ~1Il1\~18J~
LX
\'-X
1-36 82596SX

A( 1:23}.BE.lOCK

438
.......
.. "..

IL-h-IL- h- tL-IL-IL-h-h-h- h- tL- tL-IL-IL-lL~
l-9 7

Co)

_______

c=:)L'L'~

82C501AD

+ 82506T8 + AFE

c=:)L'L'________~
82C501AD

292080-1

lmet

AP·345

bit, resulting in greater induced jitter. Figure 2 shows
the idealized output waveform for the preconditioned
signal at the transmitter. Preconditioning the signal
limits the jitter added by the MAU and a loo-m twisted
pair cable to 3.5 ns (8.0 ns when the MAU is directly
attached to a 100-0 load).

2.0 SYSTEM DESCRIPTION
2.1 Network Description
Table I compares the IOBASE-T network features with
the older standards IOBASE5 and IOBASE2.

The common mode to differential impedance balance of
the tran~mitter must exceed 29 - (17 X log f/lO) db,
where f IS the frequency in megahertz. The magnitude
of the total common output voltage will be less than 50
mVpeak. A~ditionally, ~he application of a 15-Vpeak>
10.I-Mhz SIne wave Will not change the differential
voltage by morethan 100 mV or add more than 1.0 ns
edge jitter for all data sequences.

2.1.1 MEDIUM ATTACHMENT UNIT

The MAU, or transceiver, provides the circuits required to interface to the twisted pair wire. It performs
the following functions: line driving with preconditioning, line receiving, collision detection, linkbeat transmission, link integrity processing, jabber protection,
and signal_quality_error test.
MAU Line Drivers. The transmitter is designed to
drive a 96-0 ± 20% load (76 to 115 0) and must meet
all the specifications when connected to a 100-0 resistive load. It is dc isolated from the twisted pair by a
transformer, and has a matched source impedance of96
o ± 20%. It will achieve a drive level of 2.2- to 2.8-V
peak differential when driving a 100-0 load. When the
driver is sending a IO-MHz data pattern all harmonics
must be 27 db below the fundamental. The signal is
Manchester encoded. The return loss of the transmitter
shall be 15 db below the incident signal in the 5- to 10Mhz range whenever the source impedance of the measuring device is between 85 and III O. These specifications applies whenever power is applied to the MAU.
A preconditioning algorithm is incorporated into the
tran~~it circuitry. This algorithm improves overall sys~em Jitter performance by reducing the amount of jitter
Induced by the twisted pair. The line drivers will drive
full amplitude during "thin" (50 ns) pulses and the first
half of "fat" (100 ns) pulses. They will reduce their
drive level to approximately 33% during the second
half of "fat" Manchester pulses. This prevents the
tw~sted pair from overcharging during the fat pulses.
Without this preconditioning, the overcharge would
cause a delay in the zero crossing following the "fat"

MAU Line Receivers. The MAU line receivers are also
dc isolated by a transformer. They must have a
matched differential impedance such that the return
loss is at least 15 db below the incident signal in the
range from 5 to 10 MHz whenever the source impedance of the measuring device is between 85 and III O.
It must operate properly in the presence of any valid
Manchester signal with a magnitude of 0.585 to 3.l-V
differential and up to ± 13.5 ns of edge jitter. It detects
the End of Packet (IDL signal) within 2.3 bit times.
'I.'he sque~ch circuit rejects as noise any of the following
s~gnals: Signals less than 300 mVpeak in magnitude, all
slgn.als less than 2 Mhz and 6.2 Vp_p' and any sinusoid
of SIngle cycle duration starting at either zero crossing
and between 2 and IS Mhz and less than 6.2 Vp _p ' It
can tolerate a 25- Vp_p' 500-kHz square wave and add
no more than 2.5 ns of edge jitter to the signal.
C:olIision Detect. The MAU detects collisions by the
simultaneous occurrence of activity on transmit and re- .
c.eive pair. Collisions are detected by transmitting statIons and repeaters. When a transmitting station detects
a collision it begins the normal 802.3 collision sequence
of jam, random back off, and retransmit. When a repeater detects a collision it also begins a jam on all
ports and it enforces the minimum frame length of 96
bits.

Table 1 Comparison of Network Features
FEATURE

10BASE·T

10BASE5

10BASE2

Access Method
Data Rate
Controller

CSMAlCD
10 Mb/s
82586/82596

82590/82592

Existing
100 m
Star
Unshielded TP
960
RJ-45

Existing
500m
Bus
Yellow Coax
500
N or Piercing

CSMAlCD
10 Mb/s
82586/82596
82590/82592
Existing
185 m
Bus
Thin Coax
500
BNC

Software
Segment Length
Topology
Wire
Impedance
Connector

1-574

Ap·345

Yellow Cable
Tx Waveform

TPE
Tx Waveform

292080-2

Figure 2. Preconditioned Waveform

Loopback. During transmission without collisi~n, the
loopback function of the 10BASE-T MAU will also
route the transmitted data back to the DTE on the
receive circuit. This function mimics the natural data
loopback which occurs in coax MAUs.
Link Integrity. The link integrity function is a process
by which the IOBASE-T MAU can det~rmine if its r~
ceiver is properly connected to a compattble MAU. If1t
is not it disables its transmitter, receiver, and loopback
functions. This prevents a one-way link failure from
indefinitely disrupting the network, since the carrier
sense function is dependent on the receiver. When a bad
link disables a MAU's carrier sense function, it removes
itself from the network.
The link integrity function is accomplished by two independent and asynchronous activities--one for the
transmitter and one for the receiver. The transmitter
will fill long periods of idle with link test pulses Oink
beats). A link beat is transmitted after every 8 to 24 ms
of silence. This defines a maximum period of silence the
remote receiver Will experience regardless of network
traffic.
The receiver monitors its circuit for data packet and
link beat reception from the remote MAU transmitter.
If an excessively long period of silence occurs, the
MAU will disable its receiver, transmitter, and loopback functions. Link beats are still transmitted in this
mode. Once data or link beat reception resumes, the
MAU reenables all its functions.

2.1.2 MULTIPLE PORT REPEATER
The repeater is the central point in the star configured
network. It is usually located in a telephone closet or
other central wiring point. The link segments (repeater
to node or repeater to repeater connections) are then
made by using available twisted pairs in the existing
telephone cable plant or a dedicated cable plant. The
repeater must conform to the ANSI/IEEE 802.3c-1988
standard for repeaters. It can have any number of dedicated IOBASE-T, 10BASE2, FOIRL, or 10BASE5
ports, and it can have. any number of attachment unit
interface (AUI) ports. The AUI ports are DTE type
(DB-IS female receptacle) and can be connected to any
valid 802.3 MAU. All dedicated 10BASE-T ports must
support the same functions as the 10BASE-T MAU
and normal repeater port functions.
The repeater supports autopartitioning and jabber protection. These two features prevent faulty. nodes from
taking down the entire network. The autopartition algorithm monitors ports for consecutive collisions such
as would happen if a coax segment (IOBASES or
IOBASE2) were left unterminated or if the Tx and Rx
twisted pairs were shorted together on a 10BASE-T
segment. Once identified, that port is removed from the.
network until the fault condition is removed; this allows the remainder of the network to operate normally.

1-575

inter

AP-345

the remote MAU. That is, pin 1 (TD+) on a MAU
with an embedded crossover is connected to the Transmit Data (+) of the remote MAU and to its own Receive Data (+). The crossover function is defined by
the following connections between MAU A and MAU
B shown in Table 3.
TABLE 3. MAU A AND MAU B CONNECTIONS

The jabber function of the repeater monitors the length
of incoming data. If it detects an abnormally long frame
it breaks it into legal lengths by inserting minimum interframe spaces on its transmitted signal. This prevents
any jabber condition from being repeated onto other
segments. Repetition of the jabber condition would allow its own, and other MAUs, to enter, a fail state due
to faults at a remote location, thus preventing normal
operation of the network after the fault condition is
removed. With the repeater's jabber protection, network operation resumes after the fault is removed.

MAUB

Signal

TD+(A)
TD-(A)
RD+(A)
RD-(A)

RD+(B)
RD-(B)
TD+(B)
TD-(B)

3
6
1
2

When an embedded crossover function is used in a
DTE-to-repeater connection the crossover is usually
embedded in the repeater MAU. In general, repeater
MAUs have an embedded crossover and DTE MAUs
do not. With proper use of the crossover function, repeaters can be cascaded through twisted pair ports and
two DTEs can be connected in a point-to-point network. Repeaters can be cascaded two ways. First, one
or more twisted pair ports on a repeater can be designed to have a switched (optional) crossover function.
This allows a DTE connection on that port when the
crossover is active; or a repeater connection, when the
crossover is disabled. Secondly, two twisted pair ports
with embedded crossovers can be connected by using a
third external crossover.

2.2 Integrating with Existing 802.3
Networks.

2.1.4 LINK SEGMENTS

A lOBASE-T link segment connects two twisted pair
MAUs; it comprises two medium dependent interface
connectors (RJ-45 and 8-pin, standard telephone
plugs), two pairs of twisted pair wire (not to exceed 100
m), and a crossover. The connector's pin assignments
are shown in Table 2.
TABLE 2. MDI CONNECTOR PIN ASSIGNMENTS
Pin

Signal

1
2
3

Transmit Data + (TD+)
Transmit Data - (TD -)
Receive Data + (RD + )
Not Used
Not Used
Receive Data - (RD-)
Not Used
Not Used

4
5
6
7
8

MAUA

2
3
6

2.1.3 DATA TERMINAL EQUIPMENT

DTEs include the user nodes, file servers, bridges, and
other entities that can originate and accept data packets
on the network. DTEs contain the medium access control (MAC) and physical layer signaling (PLS) sublay- .
ers. A DTE can also contain an embedded MAU.
DTEs that do not have an embedded MAU have im
AUI connector. DTEs with embedded MAUs have the
medium dependent interface connector for that particular MAU (RJ-45 for lOBASE-T and BNC for
lOBASE2). The MAC functions are handled. by the
LAN controller (intel's 82586, 82590, 82592; or the
82596 family). ThePLSfunctions are handled by the
serial interface component (82C501AD) or a combination PLS/MAU device (82504TA and 82521TB). This
architecture represents a continuity of design for migration from Ethernet/Cheapernet designs to Twisted Pair
Ethernet. Only the MAU part of the design needs to be
updated. This is 100% software independent.

The crossover function connects the TD outputs of one
MAU to the RD inputs of the other. This function can
be external or embedded within a MAU. If the function
is embedded the signal names on the connector refer to

Because lOBASE-T networks are fully compatible with
existing 802.3 networks at the medium access control
and physical layer signaling sublayers, lOBASE-T networks can be integrated with existing 802.3 networks to
form one large network. The IEEE standard for repeaters allows connecting different wire types in lO-Mb/s
baseband networks. This is because the repeater definition stops at the AUI connection (DTE sex). The wire
type is determined by the MAU attached to the AUI
connector, and can vary from port to port. Optionally,
a repeater can have embedded MAUs on any of its
ports. The only requirement for an embedded MAU is
that functionality at the medium dependent interface
point (e.g., coax tap or. twisted pair connector) be maintained as if the MAU were external.
The 82505TA Multiport Repeater Controller provides
embedded MAUs on 11 of its 12 ports, and an AUI
connection on the remaining port. This allows creating
local twisted pair subnetworks connected to an Ethernet backbone. Care must be taken not to violate the
following system topology rules of 802.3 networks.

1-576

inter

Ap·345

The layout of the 82521TB and the RJ-45 connector
s~lOuld keep the TD +, TD -, RD +, and RD - signal
hnes as short as possible. The width of these signals
should be at least twice the spacing between the signal
trace layer and the ground plane. The power supply
traces (Vee, VEE, and ground) should be as thick as
possible, and bypass capacitors should be placed between each power supply and ground. An alternating
strategy of 0.1- and O.OOl-/-LF decoupling capacitors
should be used throughout the host circuit board. We
also recommend laying out the 82521TB on a ground
plane and connecting logic ground to chassis ground.

• Only one active signal path is allowed between any
two stations on the network.
• No more than four repeaters are allowed in the signal path between any two stations on the network.
• There is an overall limit of 1024 stations on a network (repeaters do not count as stations).

2.3 Software Compatibility
Because the IOBASE-T definition is restricted to the
MAU, software is not affected. Twisted pair networks
use the same LAN controller chips (82586, 82590,
82592, and the 82596 family) as current Ethernet and
Cheapernet networks and are fully software compatible.

3.2 Designing a DTE Node Based on
the 82506TB Twisted Pair MAU
Chip

3.0 NETWORK SYSTEM COMPONENT
DESIGN
The design of various IOBASE-T network system components is presented in this section.. First, DTEs with
embedded MAUs, then external MAUs, and lastly repeater designs.

3.1 Designing a DTE Node Based on
the 82521TB Serial
Supercomponent.
A design for an 82521 TB based DTE node with an
embedded MAU is shown in Figure 3. It includes all of
the functions described in Section 2.1.1, thereby relieving the d~signer of those responsibilities. It is simple to
use and It does not require mastering pole-zero diagrams. It is a direct interface from the Ethernet controller to the RJ-45 connector. Implementation of the
Clear to Send (CTS) signal is optional.

Figure 4 shows a DTE node with an embedded MAU
based on the 82506TB. It shows the Ethernet LAN
controller, the 82C50lAD, an AUI transformer, the
82506TB, the analog front-end, and the connector. As
i~ previous Ethernet designs, the LAN controller proVides the MAC services such as transmission deferral
collision backoff and retransmission, CRC generatio~
and checking, and address checking. It also provides
the host interface. The 82C50 lAD provides the serial
interface function of Manchester encoding and decoding and clock recovery. The 82506TB provides the
MAU functions, which include carrier sense, collision
de~e?t link int~grity, jabber protection, twisted pair line
dnvmg, and hne receiving. The analog front-end handles the preconditioning summation, filtering, balancing, and isolation requirements of 10BASE-T.

1-577

inter

AP-345

Power Supplies
VCC ·+5V

RTS

CTS

..J1t')

ON
",,,,,
•

TxC

I-

TxO

RxC

zU)

W«!.

RxO

RxD

"'''''
I£JIt')

CRS

W""

COT

zO
0'"
ult')

:J:N

r-TO+

TO+

TO-

TO- .

82521TB

----

RO+

RD-

'"0

'!'z
",z
0
u

292080-3

Figure 3. 82521TB sse Interface

c::
0

•
'"
I

TRMT

RiC

TRMT
RxD

.... '"

..J1t')

CRS

~""•

TxD

..I N

I-

0'"

.''"iC::.'"

"'co

1"7

RCV

82C501AD

~ fReY

011')
N

TxC

",co

t;:;""
Z •

RTS

:J:II')
I-N

.... ""

CDT

CLSN

LPBK

~ f em

.... ""

TRMT

HDAT

TRMT

LDAT

HiiAr

en
Z

..,

r--

...
'Ii 7

c::
0>

..,

RxCOIl

TRIIT

HDAT

TRIIT

,....,

LDAT

10
IX:

:::E

Q
......

......

100 PF

u
CD
r:::
r:::

IX:

RCV

L....

It)

Vl00PF"l

0
0

&,
CD

150

47..1.

33~

18~

24~

w..

L~~•

0.01J'~

•- - -

LDAT

DI
0
Ul

...

."
0
~

':"

II
RD

rn
~

TD+

»
'U

RD+

~ RD-:

Co)

I I """c.n

,,;
en

0.39

Rx COM

..1v

r---- ..1. "--127r---- ..1.
24~
18~

..1. "--1
110

11~

0.56

R in Ohms (1/4 W +1%)
(NPO +5%)
C in pF
(+5%)
Lin uH
SANYO SB05·05CP or equiv.
D
All component values should be valid over the frequency range
from 1 to 100 MHz .
T1, T2, and T3 are commercially available from Sprague,
Valor, Pulse Engineering and others.

292080-11

inter

AP-345

56.2fl
HOAT

221fl

LOAT

OUT
FILTER"

221n

r-----'
I

I!--!-

I
I
IN

LOAT

TD+

~ _____ ~ 0.047 JLF

FILTER"

1:1
2 kV ISOLATIONt

56.2fl
HOAT
TRANSMIT

u:;
RD+

OUT

FILTER"

93.1fl
IN

+----......----1

FILTER"

~ _____ ~ 0.047 JLF

1:1
2 kV ISOLATIONt

RECEIVE

292080-12

'Possible filters are the Pulse Engineering Inc. (PE32101), TDK Corp. (0921 ES), CTS Corp.-Knight Div. (9561928-01),
Coilcraft (K9686-B), or equivalents.
fRequired transformers are the AT&T (2759A), Pulse Engineering (PE65263), Coilcraft (LAXIOT-200), or equivalents.

Figure 12. Filter Pack Front End

The common mode choke rejects common mode radio
frequency and electromagnetic interference picked up
from the unshielded telephone lines. It should provide
1000-Vde isolation between the windings. The common
mode choke has four windings, each connected with
proper polarity, in series with the receive and transmit
twisted pairs. The balance of the choke is very important for providing proper noise cancellation while passing through the differential signal unaffected. We recommend a common mode to differential balance of 30
db (measured according to the lOBASE-T draft specifications) at all frequencies up to 20 MHz.

• Clock traces, and other high-frequency traces,
should be have a width of at least twice the separation between the trace and the nearest ground plane.
• Connect logic and chassis ground together.
• Separate and decouple all of the analog and digital
power supply lines.

4.5 Layout Considerations

• Use high-loss magnetic beads on power supply distribution lines.
• Group each of the receive and transmit circuits, but
keep them separate from each other. Separate their
grounds.
• Layout all differential circuits symmetrically so
parasitic effects are also symmetrical.
• Layout the circuitry from the line connector to the
active circuitry (especially the EMI filter) on a
ground plane to prevent undesirable EMI effects.

The power and ground wiring should conform to good
high- frequency practice and standards to minimize
switching transients and parasitic interaction between
various circuits. To achieve this, the following guidelines are presented.
• Place bypass capacitors (0.1 and 0.001 /LF should be
interspersed) on each IC between Vee and ground.
They should be located close to the Vee pins.
• Make power supply and ground traces as thick as
possible. This will reduce high-frequency cross coupling caused by the inductance of thin traces.
1-586

• Close signal paths to ground as close as possible to
their sources to avoid ground loops and noise cross
coupling.
• Connect all unused IC inputs (except as directed by
the manufacturer) to ground or Vee to avoid noise
injection or parasitic oscillations of unused circuits.

inter

AP-345

5.0 SUMMARY
This application note presented several designs meeting
the IEEE 802.3 10BASE-T draft standard lOBASE-T.
They use standard telephone twisted pair wiring and a
star configuration for cost savings and flexibility. They
use the same IEEE 802.3 standard for CSMA/CD medium access control and, where applicable, the physical
layer signaling. This network type is fully software
compatible with, and can connect to present Ethernet
or Cheapernet networks. The hardware connection is
made through an 802.3 defined AUI port and by complying with the repeater standard ANSI/IEEE 802.3c1988.

Intel has introduced four products for designing network components (DTEs and repeaters). DTE design
can be done with either the 82521TA Serial Supercomponent or the 82506TB TP Transceiver Chip. The supercomponent contains all the circuitry required between the Ethernet controller and the RJ-45 connector.
DTEs that support the AUI can be instantly connected
to lOBASE-T networks using the 82523TB MAU supercomponent. Multiple port repeaters can be designed
using the 82505TA with an 82504TA. It allows for 11
twisted pair ports and 1 A UI port.

1-587

Ap·345

APPENDIX A
The following set of equations for programming the 5C 180 for the 1OBASE-T port design of a multiple-port repeater
were generated from a proven lOBASE-T design. However, they were not verified in their present state. They are
intended to serve as an example to aid in the development of a complete design.
They are written in iSTATE format, a state machine compiler to be used in conjunction with IPLSII.

Thorn BOWDs/Bill Wager
Intel
Feb. 20, 1990
Repeater lBO
Rev 0
SCIBO
SCIBO for Multiple Port RepeaterOPTIONS: TURBO=ON
PART:

Counters, State machines, etc.

SCIBO

INPUTS:
OUTPUTS:

TXC', LID, WDTD, TPEN', PEx,
TEST, CARR, LINK, RESET
TCSx, LKBTt, TXE, WDT,
SLOCLK, LI
JT14 RESET, JTS8_RESET, LT_RESET~ SCQOl, SCQ02,
SCQ03, SCQ04,
SCQOS, SCQ06, SCQ07, SCQ08, SCQ09, SCQlO,
SCQll, SCQ12, SCQ13, DLINK, JTQl, JTQ2,
JTQ3, JTQ4, JTQS, JTQ6, JTQ7, JTQB,
LTQl, LTQ2, LTQ3, LTQ4, LTQ5, LCQl, LCQ2,
JFQl, LIFQl, LIFQ2

NETWORK:
TXCn
INP (TXC')
INP(LID)
LID
= INP (WDTD)
WDTD
INP(TPENt)
TPENn
INP(TEST)
TEST
CARRIER
INP (CARR)
INP (LINK)
SLINK
INP (RESET)
RESET
INP (PEx)
PEx
TCSx
LKBTt
LKBTI
TXE

CONF(TCSx,VCC)
RONF(LBEATn,TXCn,GND,GND,VCC)
NORF(ILBEAT,TXCn,GND,GND)
CONF(TXE,VCC)
292080-13

1-588

AP-345

% Timer reset feedback macrocells %
JT14_RESET
NOCF(JT14_RESETd)
JT58_RESET = NOCF(JT58_RESETd)
LT RESET
NORF(LT_RESETd,TXCn,GND,GND)
% SLOCLK macrocells %
SCQOl
NOTF(SCT01,TXCn,RESET,GND)
SCQ02
NOTF(SCT02,TXCn,RESET,GND)
SCQ03 = NOTF(SCT03,TXCn,RESET,GND)
SCQ04
NOTF(SCT04,TXCn,RESET,GND)
SCQ05 ~ NOTF(SCT05,TXCn,RESET,GND)
SCQ06
NOTF(SCT06,TXCn,RESET,GND)
SCQ07
NOTF(SCT07,TXCn,RESET,GND)
SCQ08
NOTF(SCT08,TXCn,RESET,GND)
SCQ09
NOTF(SCT09,TXCn,RESET,GND)
SCQ10
NOTF(SCT10,TXCn,RESET,GND)
SCQll = NOTF(SCTll,TXCn,RESET,GND)
SCQ12
NOTF(SCT12,TXCn,RESET,GND)
SCQ13 = NOTF(SCT13,TXCn,RESET,GND)
SLOCLK,SCQ14 = TOTF(SCT14,TXCn,RESET,GND,VCC)
SLOCK
CLKB(SCQ14)
DLINK - NORF(SLINK,TXCn,RESET,GND)
% Jabber timer macrocells %
JTQl = NOTF(JTT1,SLOCK,JT14_RESET,GND)
JTQ2 = NOTF(JTT2,SLOCK,JT14_RESET,GND)
JTQ3 - NOTF(JTT3,SLOCK,JT14_RESET,GND)
JTQ4 a NOTF(JTT4,SLOCK,JT58_RESET,GND)
JTQ5
NOTF(JTT5,SLOCK,JT58_RESET,GND)
JTQ6
NOTF(JTT6,SLOCK,JT58_RESET,GND)
JTQ7 - NOTF(JTT7,SLOCK,JT58_RESET,GND)
JTQ8
NOTF(JTT8,SLOCK,JT58_RESET,GND)

% Link test timer macrocells %
LTQl - NOTF(LTT1,SLOCK,LT_RESET,GND)
::OTF {LTT2, SLeCK, LT_RESET,GNDj
LTQ3 = NOTF(LTT3,SLOCK,LT_RESET,GND)
LTQ4 = NOTF(LTT4,SLOCK,LT_RESET,GND)
LTQ5
NOTF(LTT5,SLOCK,LT_RESET,GND)

% Link count macrocells %
LCQl
NOTF(LCT1,TXCn,RESET,GND)
LCQ2 = NOTF(LCT2,TXCn,RESET,GND)
292080-14

1-589

inter

AP-345

EQUATIONS:
% Input controlled variables %
output_active - ! (TPENn + !PEx);
output_idle - TPENn + !PEx;
input_active - CARRIER;
input_idle = !CARRIER;
link_test_rcvd = SLINK*!DLINK;
% Output equations %
TCSx = input_active * !disable_receiver;
ILBEAT - linkbeat_timer_done;
LBEATn - !(ILBEAT * !LKBTI);
TXE = !disable_driver- * output_active;
disable_driver ~ disable_driver_3 + disable_driver 4;
% Miscellaneous equations %
link_count_is_3 = LCQ2 * LCQl;
LCRESET
LINK_TEST_FAIL_RESET * !link_test_rcvd;
LCCOUNT = LINK_TEST_FAIL_RESET * link_test_rcvd +
LINK TEST FAIL *
link test_min_timer_done;
LCTl = LCCOUNT + LCRESET * LCQl;
LCT2 = LCCOUNT * LCQl + LCRESET * LCQ2;

link~test_rcvd

% ------------------------------------------------------- %
% SLOCLK counter equations %

VCC;
SCTOl
SCQOl;
SCT02
SCT02 * SCQ02;
SCT03
SCT04 = SCT03 * SCQ03;
SCT04 * SCQ04;
SCT05
SCT05 * SCQ05;
SCT06
SCT07 = SCT06 * SCQ06;
SCT08 = SCT07 * SCQ07;
SCT08 * SCQ08;
SCT09
c,..,...nn
..
SCTC9 <6- .........
SeTl!}
\lv."
SCTlO * SCQlO;
SCTll
TEST + !TEST * SCTll * SCQll;
SCTl2
SCTl3 ~ SCTl2 * SCQl2;
SCTl4
SCTl3 * SCQl3;
% JABBER timer equations %
transmit timer done = JTQ5 * NON JABBER OUTPUT;
unjab_t~r_do~e - JTQ8 * JTQ7 *-UNJAB_WAIT;
unjab_timer_not_done = !unjab_timer_done;
linkbeat_timer_done = JTQ3 * !NON_JABBER_OUTPUT
JTl4_RESETd = RESET + NO_OUTPUT * output_active
+ NON JABBER OUTPUT * output idle;
JT58_RESETd = JTl4_RESETd
+ JAB * output_idle;

!LID;

292080-15

1-590

AP-345

VCC;
JTTl
JTT2
JTTl
JTT2
JTT3
JTT3
JTT4
JTT4
JTT5
JTT5
JTT6
JTT6
JTT7
JTT7
JTTB
JTCOUNT = !

*
*
*
*
*
*
*

JTQ1;
JTQ2;
JTQ3;
JTQ4 * JTCOUNT;
JTQ5;
JTQG;
JTQ7;
(JTQ5 * JTQ6 * JTQ7 * JTQB);

% LINK timer equations %

link_loss_timer_done -LTQ5 *LTQ4 *LTQ3 *LTQ2 *LTQl * IDLE_TEST;
link_test_min_timer_done =
(LTQ3 + LTQ4 + LTQ5) * «IDLE_TEST) + (LINK_TEST_FAIL»;
link_test_min_timer_not_done = !link_test_min_timer_done;
link_test_max_timer_done = LTQ5 * LINK_TEST_FAIL;
LT RESETd
IDLE_TEST * (input_active
+ (link_test_rcvd * link_test_min_timer_done»
+ LINK TEST FAIL RESET
+ LINK_TEST_FAIL * link_test_min_timer_done
* link- test- rcvd
+ LINK_TEST_FAIL_EXTEND;

LTTl
LTCOUNT;
LTCOUNT *
LTT2
LTT3
LTCOUNT *
LTT4
LTCOUNT *
LTT5
LTCOUNT *
LTCOUNT = !(LTQl

LTQ1;
LTQl *
LTQl *
LTQl *
* LTQ2

LTQ2;
LTQ2 * LTQ3;
LTQ2 * LTQ3 * LTQ4;
* LTQ3 * LTQ4 * LTQ5)i
292080-16

1-591

inter

AP·345

% ------------------------------------------------------- %

MACHINE: JABBER_FUNCTION
TXCn
CLOCK:
RESET
CLEAR:
STATES:
NO_OUTPUT
NON_JABBER_OUTPUT
JAB
UNJAB_WAIT

NON_JABBER_OUTPUT:

WDT .JFQl
0
0
1
1

% JFQ2 is WDT also %

]

1
1

]
]
]

% start_transmit_timer %
IF (output_active * transmit_timer done
THE:N JAB
IF output_idle
THEN NO_OUTPUT

JAB: IF output_idle
IF output_active * WDTD
ASSERT: disable_driver_3
UNJAB WAIT:

!WDTD)

THEN UNJAB_WAIT
THEN NO_OUTPUT
% ASSERT WDT here %

% start_un j ab_timer %
IF output_active * unjab_timer~not_done * !WDTD
THE:N JAB
IF unjab_timer_done + WDTD
THEN NO_OUTPUT
ASSERT: disable_driver_3
% ASSERT WDT here .%
292080-17

1-592

AP-345

% ------------------------------------------------------- %
MACHINE: LINK_INTEGRITY~FUNCTION
CLOCK: TXCn
CLEAR: RESET

STATES:
IDLE TEST
LINK TEST_FAlL_RESET
LINK_TEST_FAIL
LINK_TEST_FAIL_EXTEND
ALIA
ALIB
ALIC
ALID

LI
0
1
1
0
0
0
1
1

LIFOl
0
1
0
0
1
1
0
1

LIF02
0
0
0
1
1
0
1
1

]
]
]
]
]
]
]
]
]

start_link_loss_timer %
start_link_test_min_timer %
IF link_loss_timer_done.* !LID THEN LINK_TEST_FAIL_RESET
%

LINK_TEST_FAIL_RESET:

LINK_TEST_FAIL:

IF link_test_rcvd * !LID * input_idle
THEN LINK_TEST_FAIL
IF input_active + LID THEN LINK TEST FAIL_EXTEND
ASSERT: disable_receiver
disable_driver_4

% start_link_test min timer %
% start_link_test_max_timer %
IF input_active + link_count_is_3 + LID
THEN LINK_TEST_FAIL_EXTEND
IF (link_test_max_timer_done
+ (link_test_min_timer_not_done
* link_test_rcvd»
* !LID * input_idle
THEN LINK TEST FAIL RESET
disable_receiver

LINK_TEST_FAIL_EXTEND:

ALIA:
ALIB:
ALIC:
ALID:

IF input_idle * output_idle THEN IDLE_TEST
ASSERT: disable_driver_4
disable_receiver

IDLE_TEST
IDLE_TEST
IDLE_TEST
IDLE_TEST

. END$
292080-18

1-593

PC586E
CSMA/CD LAN EVALUATION BOARD

•

Pipelined' Access in 8-Bit Mode
• Increase
Performance through
Reduced Wait-States
16 Kbytes of Shar.ed Memory-Mapped
• SRAM
Enables Higher Performance
Network Operation
Design Complexity because
• Reduces
No I/O Address or DMA Channels
Required
High Efficiency Interleaved Memory
• Access Permits Zero Wait-State Access
by Host CPU for Most Cycles
8 Kbytes of "Remote Boot" EPROM
• (Optional)
Eliminates Need for Disk
Drives
LAN Designer with a
• Provides
Complete, High-Performance CSMA/CD

Supports Established CSMA/CD LAN
Standards:
- Ethernet (IEEE 802.3 10BASE5)
- Cheapernet (IEEE 802.3 10BASE2)

• Interfaces to Popular IBM and IBM
Compatible PC Systems:
-IBM PC, PC-XT, PC-AT (8-Bit Data
Transfer)
-IBM PC-AT (16-Bit Data Transfer)

•

Jumper Selection Offers High Degree
of Flexibility in System Configuration:
- Up to 8 Address Decode Ranges
- Up to 8 Interrupt Lines
- Ethernet (IEEE 802.3 10BASE5)
- Cheapernet (IEEE 802.3 ~OBASE2)
- Number of Wait-States

•
•

Auto-Configuring for either 8-Bit or
16-Bit Bus Systems

EthernetlCheapernet Solution

On-Board Transceiver Provides Direct
Coaxial Connection for Cost-Effective
Cheapernet Applications

The PC586E evaluation board is a non-intelligent, buffered CSMAlCD LAN adapter card designed to demonstrate Intel's high-performance EthernetiCheapernet chip set. It provides IEEE 802.3 TYPE 10BASE5 (Ethernet) and TYPE 10BASE2 (Cheapernet or thinwire Ethernet) connections for IBM PC, PC-XT, PC-AT and"
compatible systems. The PC586E combines the Intel 82586 LAN Coprocessor and the Intel 82C50l Ethernet
Serial Interface with an on-board Ethernet Transceiver into a total Ethernet/Cheapernet solution. The card is
easily installed in either an 8-bit or l6-bit PC expansion slot and then automatically configures itself for 8-bit or
l6-bit data transfers. Its jumpers offer a high degree of flexibility for system-dependent configuration. For
Ethernet applications, the 82586/82C50l pair provide the complete transceiver cable interface required by the
IEEE 802.3 standard. In addition, the PC586E's on-board transceiver provides the entire coaxial cable interface for convenient, cost-effective Cheapernet systems.

[PROM
(optional)
8k x 8

PROt.!
32 BYTES

SRAt.!
S.K x, 16

Command

Control
LogIc

82586-6

I+-t

Analog

Int.rface
82C501
82502

Bus Interface Logic
Word Assembly/Disassembly

L
. 290196-1

Figure 1. PC586E Block Diagram
The PC586E is provided solely as an evaluation tool for use in designing with Intel's 82586 chip set. It has not been tested for compliance to FCC
requirements fo~ EMI (Part 15. subpart j). Intel is not responsible for any misuse of this evaluation board.

1-594

October 1988
Order Number: 290196.(101

inter

PC586E

The PC586E is part of Intel's LAN Evaluation Board
program. The board is intended to demonstrate the
high-performance characteristics of the 82586 chip
set in an adapter card application. The PC586E
gives LAN engineers a head start in finding the best
solution for their specific network problem. PC586E
boards are shipped with detailed design documentation (artwork and PAL equations also available).

which the 82586 is never given wait-states. This precludes the need for wait-state logic for the 82586
and allows the 82586 to run at 6 MHz.
When the 82586 is inactive, the interleaving logic
becomes transparent and the Host System may access the Local Memory with no wait-states (16-bit
buses only). This provides about a 15% to 20%
boost in bus performance.

The PC586E is based on an Interleaved Local Memory Access scheme with Static RAM dual-ported between the 82586 LAN Coprocessor and the Host
System CPU. Access to the board is purely MemoryMapped, and therefore, no I/O ports or DMA channels are required. In addition to the shared SRAM,
the system supports a "Remote-Boot" EPROM and
32 bytes of Address PROM. The 82586 has access
only to the Static RAM.

DESCRIPTION OF INTERLEAVE
LOGIC
Since the 82586's READY and HOLD ACKNOWLEDGE signals are always active, only a simple arbiter is required. The Control Logic merely interleaves
Host System accesses with 82586 accesses. When
the 82586 is active, the Host System access will occur during the first half of the 82586 "read/write"
cycle. When the 82586 is inactive, the Host System
access will occur at the speed of the Host Bus.

MEMORY
The Local Memory consists of 16 Kbytes of Static
RAM, 32 bytes of Address PROM, 16 Command
Registers, and up to 8 Kbytes of "Remote Boot"
EPROM (Optional). All of the Local Memory is
mapped into unused memory space of the Host System. Commands are issued to the PC586E by transferring the instruction to a Command Register. The
Command Registers are used for issuing the Reset
and Channel Attention signals to the 82586, enabling interrupts and configuring the board.

If the Host System initiates access to the static RAM
during T1 or T2 of the 82586 "read/write" cycle, it
will complete operation without any additional waitstates. If the Host System should initiate access during T2 or T3 of the 82586 "read/write" cycle, a maximum of three wait-states will be inserted for an
8 MHz AT system. The maximum number of waitstates depends on the width and frequency of the
Host System.

CONFIGURATION

WORD ASSEMBLY IDISASSEMBLY

There are up to 8 jumper-selectable locations for the
Local Memory and the Command Registers (four of
these locations are mapped ·above the 1 Mbyte
boundary, FFFFh). In addition, the jumpers are used
for the Interrupt Request Signal which may be assigned to anyone of eight Interrupt Request lines.

For systems with 8-bit data buses, the PC586E has
a special Word Assembly/Disassembly function. Access to the Static RAM may be made either as 8-bit
or 16-bit operations. If 8-bit transfers are made, the
Word Assembly/Disassembly logic is used to increase performance.

The PC586E automatically detects if it is placed in
an 8-bit or 16-bit expansion slot. When the PC586E
is in a 16-bit slot, a Command Register is used to
program the PC586E for either 8-bit or 16-bit data
transfers. One of the Command Registers can also
be used to disable the interrupt signal.

INTERLEAVED MEMORY ACCESS
The PC586E uses Interleaved Memory Access between the 82586 LAN Coprocessor and the Host
System CPU to increase system performance. One
read or write access is allowed by the Host System
for every read or write access by the 82586. In this
way, high utilization of local memory is achieved.
The logic used is a "cycle-stealing" approach in

WORD DISASSEMBLY
An 8-bit "read" operation to an even address causes 16 bits of data to be read from the Static RAM.
The first 8 bits are transferred onto the Host bus and
the second 8 bits (corresponding to the odd address) are temporarily stored in a latch. When the
subsequent "read" is made to the odd address, the'
data stored in the latch is copied onto the Host Bus.
In this way, access to the Static RAM by the Host
CPU is reduced by 50%.

WORD ASSEMBLY
An 8-bit "write" operation to an even address causes the data stored at this location to be temporarily

1-595

_ PC586E

transferred to a latch. When the subsequent 8-bit
"write" operation is made (corresponding to the odd
address), the two 8-bit bytes are combined into a
16-bit word which is then transferred to the Static
RAM.
.
In order to take advantage of this scheme, all access to the Static RAM must be made on a 16-bit
word basis to even addresses. Since the 82586 data
structures are naturally designed to be 16-bits wide,
this requirement has little or no impact on software. .
The bus interface of systems with 8-bit data buses
will automatically break 16-bit operations into two
8-bit operations. The same software can thus be
used for .both 8-bit and 16-bit systems.
. .
The Word Assembly/Disassembly function is only
used for access to the Static RAM. All accesses to
the Address PROM, Remote Boot EPROM and
Command Registers are made as 8-bit transfers
only.

Manchester encoding/decoding of transmit and receive data,generation of the transmit and receive
clock and interface to the AUI/Transceiver cable. In
addition, the 82C501 has a built in watchdog 'timer,
internal loopback diagnostics and collision detection
circuitry. The 82586/82C501 thus provide the complete transceiver cable interface required by IEEE
802.3.

CHEAPERNET
In Cheapernet mode, the Ethernet Transceiver is located on-board. The transceiver works in conjunction with the 82586 and 82C501 to provide the com. plete, on-board, coaxial cable interface.

COMPONENT DESCRIPTION

REMOTE BOOT EPROM
.An optional 8192 byte EPROM may be installed for
either "Remote Boot" operation or general purpose
ROM. Upon booting the system, the Host CPU
searches for a 55AAh data pattern starting at address C8000h. If the pattern is not found, additional
attempts will be made at subsequent addresses in .
2 Kbyte increments. If the pattern is found, the Host
will then search for a jump instruction and a Cyclic .
Redundancy Check (CRC). If these are found, the
CPU will begin executing the code at the location
specified by the jump instruction. In order to take
advantage of the "Remote Boot" option,. the software on th~ EPROM must be able to configure the
PC586E and copy the operating system through the
network. This ability removes the need for disk
drives. The EPROM may be used for general purpose storage instead of remote booting. In either
case, only 8-bit "read" operations are permitted
from this device.

ETHERNET/CHEAPERNET
SELECTION
The PC586E Board is jumper-selectable to operate
in either Ethernet (IEEE 802.3 10BASE5) or Cheapernet (IEEE 802.3 10BASE2) mode.

ETHERNET
In Ethernet mode, the 82586 LAN Coprocessor is
used in conjunction with the Intel 82C501 Ethernet
. Sedal Interface. Functions of the 82C501 include

82586 LAN Coprocessor
- Implements a Complete CSMAlCD Data Link
- Incorporates all Logic for Executing Time Critical
Functions Independently of Host System
- High-Level Command Interface Simplifies Software Programming
' .
- Supporting Industry CSMAlCD. LAN .Standards
Ethernet (IEEE 802.3 10BASE5)
Cheapernet (IEEE 802.3 10BASE2)
- Provides On-Chip Memory Management with Automatic Buffer Chaining and Reclaiming
....,.. Interfaces to Industry Standard 8"Bit and 16-Bit
Microprocessors
- Powerful System Interface
On-Chip DMA Control Allows Up to
5 Mbytes/Sec Bus Capacity
8-Bit or 16-Bit-Data Bus
Back-to-Back Frame Reception at 10 Mb/s
- Built-In Network Management and Diagnostics
Transmission/Reception Error Reporting
Network Activity and Error Statistics
Station Diagnostics (External Loopback)
Self Test Diagnostics
. The 82686 is an intelligent peripheral that completely manages the. processe~ of transmitting and
receiving frames of data over the network, thus offloading the Host CPU of communication management tasks. The 82586 features an on-chip DMA
controller which allows ino access the local memory
though an efficient buffer chaining mechanism. Other features of the 82586 are the ability to perform
network management activities including error and
collision tallies and diagnostic capabilities via the internal and external loopback function. Control of the
82586 is throLigh high level commands such as
TRANSMIT and CONFIGURE.
.

1-596

inter

PC586E

All information passed between the 82586 and the Host board is made through shared local memory.
The Host may load the memory with a command
and prompt the 82586 to execute. While receiving a
packet, the 82586 loads receive buffers in local
memory and, after completing the reception, interrupts the Host board to indicate that a packet has
been received.

Cable
Connections:

- Intel 82586 LAN Coprocessor
- Intel 82C501 Ethernet Serial
Interface
Memory Capacity: - Static RAM
16 Kbytes
-

Direct Interface to the 82586 LAN Coprocessor
and Ethernet Transceiver
- Conforms to IEEE 802.3 10BASE5 (Ethernet)
and IEEE 802.3 10BASE2 (Cheapernet) Specifications
- 10 Mb/s Serial Data Rate
- Manchester Encoding/Decoding and Receive
Clock Recovery
- 10 MHz Transmit Clock Generation
- Drives and Receives IEEE 802.3 AUI (Transceiver) Cable
- Optional Watchdog Timer Prevents Babbling
- . Internal Diagnostic Loopback for Fault Detection
and Isolation
- Functionally Compatible with the SEEQ 8023A
The 82C501 provides the Ethernet (IEEE 802.3
10BASE5) or Cheapernet (IEEE 802.3 10BASE2)
Serial Interface for the 82586 LAN Coprocessor.
Major functions of the 82C501 include generation of
the transmit and receive clock (10 MHz for Ethernet
and Cheapernet), Manchester encoding/decoding
of transmit and receive data, and interfacing the
10BASE5 Access Unit Interlace (AUI/Transceiver)
cable. In addition, the 82C501 provides for fault isolation with internal diagnostic loopback. An on-chip
watchdog timer prevents the station from locking up
in the continuous transmit mode Gabber control).

Hardware:

Memory Address
Ranges:

Frequency:

General Address
PROM
Bootable EPROM

Network Software Drives are
Currently Available for the Following Applications:
UNIX/TCP-IP
Novell/Netware
(Additional Drivers to be Announced)
IBM PC, PC-XT, PC-AT and
Compatible Systems

32 bytes
8 Kbytes

1.0COOOOh-OC7FFFh
2.0C8000h-OCFFFFh
3.0DOOOOh-OD7FFFh
4.0D8000h-ODFFFFh
5. FOOOOOh-F3FFFFh
6.F40000h-F7FFFFh
7.F80000h-FBFFFFh
8. FCOOOOh-FFFFFFh
- Board Master Clock
24 MHz
- 82586-6
6 MHz

8-Bit PC Bus
Frequency (Max.): - 4.77 MHz

o Additional
Wait-States

-8MHz
-

>8MHz

16-Bit AT Bus
Frequency (Max.): - 8 MHz

oAdditional
Wait-States
Not Supported

o Additional
Wait-States

-10MHz

o Additional

Wait-States
1 Additional
Wait-States
Not Supported
>12 MHz
+5V Input ±5%
+12V Input ±5%

-12MHz

Voltage Limits:

Current
Requirements:

. PC586E Specifications*
-

DB-15 Connector (Ethernet)
BNC Connector (Cheapernet)

System
Components:

82C501 ETHERNET SERIAL
INTERFACE

Software:

- + 5V Input
- +12V Input
Power Dissipation:- Maximum
Temperature
Range:
- Operating
- Storage

3.0A·
300 rnA'
18.6W·
O·Cto +55°C
O·Cto +70·C

DIMENSIONS (Not Including Mounting Bracket)

Length: 8.2 in. (20.8 cm)
Height: 4.2 in. (10.7 cm)
Width: 0.7 in. (1.8 cm)
'Preliminary, subject to change
1-597

Wide Area Networks

8251A
PROGRAMMABLE COMMUNICATION INTERFACE
Synchronous and Asynchronous
• Operation

Baud Rate-DC to 19.2K
• Asynchronous
Baud

•

Synchronous 5-8 Bit Characters;
Internal or External Character
Synchronization; Automatic Sync
Insertion

Full-Duplex, Double-Buffered
Transmitter and Receiver

Error Detection-Parity, Overrun and
• Framing

II Asynchronous 5-8 Bit Characters;

•

Clock Rate-i, 16 or 64 Times Baud
Rate; Break Character Generation; 1,
1%, or 2 Stop Bits; False Start Bit
Detection; Automatic Break Detect and
Handling

Compatible with an Extended Range of
Intel.Microprocessors

DIP Package
• All28-Pin
Inputs and Outputs are TTL
III

Compatible

II Synchronous Baud Rate-DC to 64K

Ill! Available in EXPRESS and Military

Baud

Versions

The Intel® 8251A is the industry standard Universal Synchronous/Asynchronous Receiver/Transmitter
(USART), designed for data communications with Intel's microprocessor families such as MCS-48, 80, 85, and
iAPX-86, 88. The 8251A is used as a peripheral device and is programmed by the CPU to operate using
virtually any serial data transmission technique presently in use (including IBM "bi-sync"). The USART accepts
data characters from the CPU in parallel format and then converts them into a continuous serial data stream
for transmission. Simultaneously, it can receive serial data streams and convert them into parallel data characters for the CPU. The USART will signal the CPU whenever it can accept a new character for transmission or
whenever it has received a character for the CPU. The CPU can read the complete status of the USART at any
time. These include data transmission errors and control signals such as SYNDET, TxEMPTY. The chip is
fabricated using Intel's high performance HMOS technology.

TxD

TxADY

TxE

RECEIVE
BUFFER

RxD

Vee.;

GND

Rxe

DTR

RTS

OSR

RESET

Txe

elK

IS 'PI

CID

INTERNAL
DATA BUS

R)lRDY

A.ROY
RECEIVE
CONTROL

Axe

hEMPTY
eTS
SYNDET/BD

TxRDY

205222-2

Figure 2. Pin Configuration

_SYNDET

205222-1

Figure 1_ Block Diagram

2-1

November 1986
Order Number: 205222-002

111'eII

8251A

FEATURES AND ENHANCEMENTS

FUNCTIONAL DESCRIPTION

The 8251A is an advanced design of the industry
standard USART, the Intel® 8251. The 8251A operates with an extended range of Intel microprocessors and maintains compatibility with the 8251. Fa. miliarization time is minimal because of compatibility
and involves only knowing the additional features
. and enhancements, and reviewing the AC and DC
specifications of the 8251A.

General
The 8251 A is a Universal Synchronous/ Asynchronous Receiver/Transmitter designed for a wide
range of Intel microcomputers such as 8048, 8080,
8085, 8086 and 8088. Like other I/O devices in a
-microcomputer system, its functional configuration is
programmed by the system's software for maximum
flexibility. The 8251A can sLipport most serial data
techniques in use, including IBM "bi-sync".

The 8251A incorporates all the key features of the
8251 and has the following additional features and
enhancements:
• 8251A has double-buffered data paths with separate I/O registers for control, status, Data In, and
Data Out, which considerably simplifies control
programming and minimizes CPU overhead.
• In asynchronous operations, the Receiver detects and handles "break" automatically, relieving the CPU of this task.
• A refined Rx initialization prevents the Receiver
from starting when in "break" state, preventing
unwanted interrupts from a disconnected'
USART.
.
• At the conclusion of a transmission, TxD line will
always return to the marking state unless SBRK
is programmed.

Data Bus Buffer
This 3-state bidirectional, 8-bit buffer is used to interface the 8251A to the system Data Bus. Data is
transmitted or received by the buffer upon execution
of INput or OUTput instructions of the CPU. Control
words, Command words and Status information are
also transferred through the Data Bus Buffer. The
Command Status, Data-In and Data-Out registers
are separate, 8-bit registers communicating with the
system bus through the Data Bus Buffer.

• Tx Enable logic enhancement prevents a Tx Disable command from halting transmission until all
data previously written has been 'transmitted. The
logic also prevents the transmitter from turning
off in the middle of a word.
• When
ternal
Sync
which

In a communication environment an interface device
must convert parallel format system. data into serial
format for transmission and convert incoming serial
format data into parallel system data for reception.
The interface device must also delete or insert bits
or characters that are functionally unique to the
communication technique. In essence, the interface
should appear "transparent" to the CPU, a simple
input or output of byte-oriented system data.

External Sync Detect is programmed, InSync Detect is disabled, and an External
Detect status is provided via a flip-flop
clears· itself upon astatus read.

This functional block accepts inputs from the system
Control bus and generates control Signals for overall
device operation. It contains the Control Word Register and Command Word Register that store the
various control formats for the device functional defi~
nition.

• Possibility of false sync detect is minimized by
ensuring that if double character sync is programmed, the characters be contiguously detected and also by clearing the Rx register to all ones
whenever Enter Hunt command is issued in Sync
mode.

RESET (Reset)

• As long as the 8251A is not selected, the RD and
WR do· not affect the internal operation of the
device.

A "high" on this input forces the 8251A into an
"Idle" mode. The device will remain at "Idle" until a
new set of control words is written into the 8251A to
program its functional definition. Minimum RESET
p.ulse width is 6 tey (clock must be running).

• The 8251 A Status can be read at any time but the
status update will be inhibited during status read.
• The 8251A is free from extraneous glitches and
has enhanced ACand DC characteristics, providing higher speed and better operating margins.

A command reset operation also puts the device
into the "Idle" state.

• Synchronous Baud rate from DC to 64K.

2-2

intJ

8251A

TRANSMIT
BUFFER
(P ·SI

INTERNAL
DATA BUS

205222-3

Figure 3. 8251A Block Diagram Showing Data Bus Buffer and Read/Write Logic Functions

CLK(Clock)

C/O RD WR ·CS

The ClK input is used to generate internal device
timing and is normally connected to the Phase 2
(TTL) output of the Clock Generator. No external inputs or outputs are referenced to ClK but the frequency of ClK must be greater than 30 times the
Receiver or Transmitter data bit rates.

0
0
1
1

X
X

WR (Write)

0
1
0
1
1

1
0
1
0
1

0
0
0
0
0
1

8251A DATA ~ DATA BUS
DATA BUS ~ 8251A DATA
STATUS ~ DATA BUS
DATA BUS ~ CONTROL
DATA BUS ~ 3-STATE
DATA BUS ~ 3-STATE

c/o (Control/Data)

A "low" on this input informs the 8251A that the
CPU is writing data or control words to the 8251A.

This input, in conjunction with the WR and RD inputs, informs the 8251A that the word on the Data
Bus is either a data character, control word or status
information.

RD (Read)
A "low" on this input informs the 8251A that the
CPU is reading data or status information from the
8251A.

1 = CONTROL/STATUS; 0 = DATA.

2-3

111'eI

8251A

CS (Chip Select)

Transmitter Buffer

A !'Iow" on this input selects the 8251A. No reading
or writ!!!9. will occur unless the device is selected.
When CS is ~, the Data Bus is in the float state
and RD and WR have no effect on the chip.

The Transmitter Buffer accepts parallel data from
the Data Bus Buffer, converts it to a serial bit stream,
inserts the appropriate characters or bits (based on
the communication technique) and outputs a composite serial stream of data on the TxD output pin on
the falling edge of TxC. The transmitter will begin
transmission upon being enabled if CTS =0 o. The
TxD line will be held in the marking state immediately upon a master Reset or when Tx Enable or CTS is
off or the transmitter is empty.

Modem Control
The 8251A has a set of control inputs and outputs
that can be used to simplify the interface to almost
any modem. The modem control signals are general
purpose in nature and can be used for functions other than ,modem control, if necessary.

, . Transmitter Control'
The Transmitter Control manages all activities associated with the transmission of serial data. It accepts
and issues signals both externally and internally to
accomplish this function.

DSR (Data Set Ready)
The' DSR input signal is a general-purpose, 1-bit inverting input port. Its condition can be tested by the
CPU using a Status Read operation. The DSR input
is normally used to test modem conditions such as,
Data Set Ready.
'

TxRDY (Transmitter Ready)
This output signals the CPU that the transmitter is
ready to accept a data character. The TxRDY output
pin can be used as an interrupt to the system, since
it is masked by TxEnable; or, for Polled operation,
the CPU can check TxRDY using a Status Read operation. TxRDY is automatically reset by the leading
edge of WR when a data character is loaded from
the CPU.

DTR (Data Terminal Ready)
The DTR output signal is ,a general-purpose, 1-bit
inverting output port. It can be set "low" by programming the appropriate bit in the Command Instruction
word. The DTR output signal is normally used for
modem control such as Data Terminal Ready.

Note that when using the. Polled operation, the
TxADY status bit is not masked by TxEnable, but will
only indicate the Empty/Full Status of the Tx Data
Input Register.

.RTS (Request to Send)
The RTS output signal is ,a general-purpose, 1-bit.
inverting output port. It can be set "low" by programming the approGriate bit in the Command Instruction
word. The RT output signal is normally used for
modem control such as Request to Send.

TxE (Transmitter Empty)
When the 8251 A has no characters to send, the
TxEMPTY output will go "high". It resets upon receiving a character from, CPU if the transmitter is
enabled. TxEMPTY remains high when the transmitter is disabled. TxEMPTY can be used to indicate
the end of a transmission mode, so that the CPU
"knows" when to "turn the line around" in the halfduplex operational mode.

CTS (Clear to Send)

A "low" on this input enables the B251A to transmit
serial data if theTx Enable bit in the Command byte
is set to a "one". If either a Tx Enable off or CTS off
condition occurs while the Tx is in operation, the Tx
will transmit all the data in the USART, written prior
to Tx Disable command before shutting down.

In the Synchronous mode, a "high" on this output
indicates that a character has not been loaded and
the SYNC character or characters are about to be or
are being transmitted automatically as "fillers". Tx
EMPTY does not go low when the SYNC characters.
are being shifted out.

2-4

8251A

TxD

TxRDY

TxEMPTY

TxC

INTERNAL
DATA BUS

205222-4

Figure 4. 8251A Block Diagram Showing Modem and Transmitter Buffer and Control Functions

TxC (Transmitter Clock)

Receiver Control

The Transmitter Clock controls the rate at which the
character is to be transmitted. In the Synchronous
transmission mode, the Baud Rate (1x) is equal to
the TxC frequency. In Asynchronous transmission
mode, the baud rate is a fraction of the actual TxC
frequency. A portion of the mode instruction selects
this factor; it can be 1, 1,1,6 or 1j64 the TxC.

This functional block manages all receiver-related
activities which consists of the following features.
The RxD initialization circuit prevents the 8251A
from mistaking an unused input line for an active low
data line in the "break condition". Before starting to
receive serial characters on the RxD line, a valid "1"
must first be detected after a chip master Reset.
Once this has been determined, a search for a valid
low (Start bit) is enabled. This feature is only active
in the asynchronous mode, and is only done once
for each master Reset.

For Example:
If Baud Rate equals 110 Baud,
TxC equals 110 Hz in the 1x mode.
TxC equals 1.72 kHz in the 16x mode.
TxC equals 7.04 kHz in the 64x mode.
The falling edge of TxC shifts the serial data out of
the 8251A.

The False Start bit detection circuit prevents false
starts due to a transient noise spike by first detecting
the falling edge and then strobing the normal center
of the Start bit (RxD = low).

Receiver Buffer

Parity error detection sets the corresponding status
bit.

The Receiver accepts serial data, converts this serial input to parallel format, checks for bits or characters that are unique to the communication technique
and sends an "assembled" character to the CPU.
Serial data is input to RxD pin, and is clocked in on
the rising edge of RxC.

The Framing Error status bit is set if the Stop bit is
absent at the end of the data byte (asynchronous
mode).

2-5

8251A

llitel

when the internal transfer is occurring, overrun error
will be set and the old character will be lost.

RxRDY (Receiver Ready)
This output indicates that the 8251A contains a
character that is ready to be input to the CPU.
RxRDY can be connected to the interrupt structure
of the CPU or, for polled operation, the CPU can
check the condition of RxRDY using a Status Read
operation.

RxC (Receiver Clock)
The Receiver Clock controls the rate at which the
character is to be received .. In Synchronous Mode,
the Baud Rate (1x) is equal to the actual frequency
of RxC. In Asynchronous Mode, the Baud Rate is a
fraction of the actual RxC frequency. A portion of the
mode instruction selects this factor: 1, Y16 or Y64 the
RxC.

RxEnable, when off, holds RxRDY in the Reset Condition. For Asynchronous mode, to set RxRDY, the
Receiver must be enabled to sense a Start Bit and a
complete character must be assembled and transferred to the Data Output Register. For Synchronous
mode, to set RxRDY, the Receiver must be enabled
and a character must finish assembly and be transferred to the Data Output Register.

For Example:
Baud Rate equals 300 Baud, if
RxC equals 300 Hz in the 1x mode;
RxC equals 4800 Hz in the 16x mode;
RxC equals 19.2 kHz in the 64x mode.

Failure to read the received character from the Rx
Data Output Register prior to the assembly of the
next Rx Data character will set overrun condition error and the previous character will be written over
.and lost. If the Rx Data is being read by the CPU

Baud Rate equals 2400 Baud, if
RxC equals 2400 Hz in the 1x mode;
RxC equals 38.4 kHz in the 16 mode;
RxC equals 153.6 kHz in the 64 mode.

DATA

TRANSMIT

BUS
BUFFER

BUFFER

ToO

IP ·S)

205222-5

Figure 5. 8251A Block Diagram Showing Receiver Buffer and Control Functions

2-6

inter

8251A

Data is sampled into the 8251 A on the rising edge of
RxC.

character in the Receive mode. If the 8251A is programmed to use double Sync characters (bi-sync),
then SYNDET will go "high" in the middle of the last
bit of the second Sync character. SYNDET is automatically reset upon a Status Read operation.

NOTE:
In most communication systems, the 8251A will be
handling both the transmission and reception operations of a single link. Consequently, the Receive
and Transmit Baud Rates will be the same. Both
TxC and RxC will require identical frequencies for
this operation and can be tied together and connected to a single frequency source (Baud Rate
.
Generator) to simplify the interface.

When used as an input (external SYNC detect
mode), a positive going signal will cause the 8251A
to start assembling data characters on the rising
edge of the next RxC. Once in SYNC, the "high"
input signal can be removed. When External SYNC
Detect is programmed, Internal SYNC Detect is disabled.

SYNDET (SYNC Detect!
BRKDET Break Detect)

BREAK (Async Mode Only)

This pin is used in Synchronous Mode for SYNDET
and may be used as either input or output, programmable through the Control Word. It is reset to output
mode low upon RESET. When used as an output
(internal Sync mode), the SYNDET pin will go "high"
to indicate that the 8251A has located the SYNC

This output will go high whenever the receiver remains low through two consecutive stop bit sequences (including the start bits,data bits, and parity
bits). Break Detect may also be read as a Status bit.
It is reset only upon a master chip Reset or Rx Data
returning to a "one" state.

ADDRESS BUS
Ao

)

CONTROL BUS
110 R

')2

110 W RESET

(TTL)

DATA BUS

').
B

V
CIO

0,-0 0

RESET

ClK

B251A

205222-6

Figure 6. 8251A Interface to 8080 'Standard System Bus

2-7

Intel

8251A

Programming the 8251A

DETAILED OPERATION DESCRIPTION

Prior to starting data transmission or reception, the
8251A must be loaded with a set of control words
generated by the CPU. These control signals define
the complete functional definition of the 8251A and
must immediately follow a" Reset operation (internal
or external).

General
The complete functional definition of the 8251 A is
programmed by the system's software. A set of control words must be sent out by the CPU to initialize
the 8251A to support the desired communications
format. These control words will program the: BAUD
RATE, CHARACTER LENGTH, NUMBER OF STOP
BITS, SYNCHRONOUS or ASYNCHRONOUS OPERATION, EVEN/ODD/OFF PARITY, etc. In the
Synchronous Mode, options are also provided to select either internal or external character synchronization.

The control words are split into two formats:
1. Mode Instruction
2. Command Instruction

Mode Instruction

Once programmed, the 8251A is ready to perform its
communication functions. The TxRDY output is
raised "high" to signal the CPU that the 8251A is
ready to receive a data character from the CPU. This
output (TxRDY) is reset automatically when the CPU
writes a character into the 8251A. On the other
hand, the 8251A receives serial data from the MODEM or I/O device. Upon receiving an entire character, the RxRDY output is raised "high" to signal the
CPU that the 8251A has a. complete character ready
for the CPU to fetch. RxRDY is reset automatically
upon the CPU data read operation.

This instruction defines the general operational.
characteristics of the 8251A. It must follow a Reset
operation (internal or external). Once the Mode Instruction has been written into the 8251A by the
CPU, SYNC characters or Command Instructions
may be written.

The 8251A cannot begin transmission until the Tx
Enable (Transmitter Enable) bit is set in the Command Instruction and it has received a Clear To
Send (CTS) input. The TxD output will be held in the
marking state upon Reset.

Both the Mode and Command Instructions must
conform to a specified sequence for proper device
operation (see Figure 7). The Mode Instruction.must
be written immediately following a Reset operation,
prior to using the 8251A for data communication.

ciD"

MODE INSTRUCTION

ciD "

SYNC CHARACTER 1

C/O" 1

SYNC CHARACTER 2

}

ciD"

CiD" 0

CIO " 1

This instruction defines a word that is used to control
the actual operation of the 8251A. .

All control words written into the 8251A after the
Mode Instruction will load the Command Instruction.
Command Instructions can be written into the 8251A
at any time in the data block during the operation of
the 8251A. To return to the Mode Instruction format,
the master Reset bit in the Command Instruction
word can be set to initiate an internal Reset operation which automatically places the 8251A back into
the Mode Instruction format. Command Instructions
must follow the Mode Instruction or Sync characters.

SYNC MODE
ONLY'

COMMAND INSTRUCTION

C/D" 0

ciD "

Command Instruction

DATA

COMMAND INSTRUCTION

Mode Instruction Definition
DATA

COMMAND

The 8251A can be used for either Asynchronous or
Synchronous data communication. To understand
how the Mode Instruction defines the functional operation of the 8251 A, the designer can best view the
device as two separate components, one Asynchronous and the other Synchronous, sharing the same
package. The format definition can be changed only
after a master chip Reset. For explanation purposes
the two formats will be isolated.

I~ISTRUCTION

205222-7
'The second sync character is skipped if mode instruction has
programmed the 8251A to single character sync mode. Both
sync characters are skipped if mode instruction has programmed
the 8251A to async mode.

Figure 7. Typical Data Block

2-8

inter

8251A

When no data characters have been loaded into the
8251A the TxD output remains "high" (marking) unless a Break (continuously low) has been programmed.

NOTE:
When parity is enabled it is not considered as one
of the data bits for the purpose of programming
word length. The actual parity bit received on the
Rx Data line cannot be read on the Data Bus. In
the case of a programmed character length of less
than 8 bits, the least significant Data Bus bits will
hold the data; unused bits are "don't care" when
writing data to the 8251A, and will be "zeros" when
reading the data from the 8251A.

Asynchronous Mode (Receive)
The RxD line is normally high. A falling edge on this
line triggers the beginning ota START bit. The validity of this START bit is checked by again strobing this
bit at its nominal center (16X or 64X mode only). If a
low is detected again, it is a valid START bit, and the
bit counter will start counting. The bit counter thus
locates the center of the data bits, the parity bit (if it
exists) and the stop bits. If parity error occurs, the
parity error flag is set. Data and parity bits are sampled on the RxD pin with the rising edge of the RxC.
If a low level is detected as the STOP bit the Framing Error flag will be set. The STOP bit signals the
end of a character. Note that the receiver requires
only one stop bit, regardless of the number of stop
bits programmed. This character is then loaded into
the parallel 110 buffer of the 8251A. The RxRDY pin
is raised to signal the CPU that a character is ready
to be fetched. If a previous character has not been
fetched by the CPU, the present character replaces
it in the 1/0 buffer, and the OVERRUN Error flag

Asynchronous Mode (Transmission)
Whenever a data character is sent by the CPU the
8251A automatically adds a Start bit (low level) followed by the data bits (least significant bit first), and
the programmed number of Stop bits to each character. Also, an even or odd Parity bit is inserted prior
to the Stop bit(s), as defined by the Mode Instruction. The character is then transmitted as a serial
data stream on the TxD output. The serial data is
shifted out on the falling edge of TxC at a rate equal
to 1, 1116, or 1164 that of the TxC, as defined by the
Mode Instruction. BREAK characters can be continuously sent to the TxD if commanded to do so.

152 \ 5, \

EP \ PEN \ L2 \ L,

B21 B,

BAUD RATE FACTOR
0

SYNC
MODE

(1X)

(l6X)

(64X)

CHARACTER LENGTH
0

5
BITS

6
BITS

BITS

PARITY ENABLE
1 ENABLE
0= DISABLE
0

EVEN PARITY GENERATION/CHE CK
1 EVEN
0 000
0

NUMBER OF STOP BITS

INVALID

1
BIT

1 v..
BITS

2
BITS

(ONLY AFFECTS Tx; Rx
NEVER REQUIRES MORE
THAN ONE STOP BIT)
205222-8

Figure 8. Mode Instruction Format, Asynchronous Mode
2-9

8251A

is raised (thus the previous character is lost). All of
the error flags can, be reset by an Error Reset Instruction. The occurrence of any of these errors wilf
not affect the operation of the 8251A.

Once transmission has started, the data stream at
the TxD output must continue at the TxC rate. If the
CPU does not provide the 8251 Awith a data character before the 8251A Transmitter Buffers become
empty, the SYNC characters (or character if in single
SYNC character mode) will be automatically inserted
in the TxD data stream. In this case, the TxEMPTY
pin is raised high to signal that the 8251A is empty
and SYNC characters are being sent out. TxEMPTY
does not go low when the SYNC is being shit:ted out
(see figure below). The TxEMPTY pin is internally
reset by a data character being written into the
8251A.

Synchronous Mode (Transmission)
The TxD output is continuously high until the' CPU
sends its' first character to the 8251 A which usually
is a SYNC character. When the CTS line goes low,
the first character is serially transmitted out. All charactersare shifted out on the .falling edge of TxC.
Data is shifted out at the same rate as the TxC.

0001----

TxD

GENERATED
BY82~IA

STJ;i ,

Brrs L

'MARKING

DOES NOT APPEAR
'DOD1----Dx ONTHEDATABUS

RECEIVER INPUT

RxD

~_ST_:_I~_T~ D~A_T~~B~IT_S ~
___

ST~

Brrs L

______

PROGRAMMED
CHARACTER
LENGTH
TRANSMISSION FORMAT
CPU BYTE 15·8 BITS/CHAR)
DATA

C~~RACTER'

ASSEMBLED SERIAL DATA OUTPUT ITxD)
DATA CHARACTER

STO[J'
BITS

~----~~--~--~
RECEIVE FORMAT
SERIAL DATA INPUT IRxDI
DATA CHARACTER

STOtJ
BITS

......- - - -........----'-----oooj

CPU BYTE 15·8 BITS/CHARI"

DATA CHARACTER
L..______--4_

SOI------.....
205222-9

°NOTE:
If character length is defined as 5, 6, or 7 bits the unused bits are set to "zero", '

Figure 9. Asynchronous Mode

2-10

8251A

AUTOMATICALLY INSERTED BY USART

TxD

TxEMPTV

DATA

I \

SYNC 1

SYNC Z

DATA

/ \\=\\\\\\I

-----'' '
.

\.~ _ _ _ _ _ _

I-- - - -

FALLS UPON CPU WRITING A
CHARACTER TO THE USART

NOMINAL CENTER OF LAST BIT

the USART ends the HUNT mode and is in character synchronization. The SYNDET pin is then set
high, and is reset automatically by a STATUS READ.
If parity is programmed, SYNDET will not be set until
the middle of the parity bit instead of the middle of
the last data bit.

Synchronous Mode (Receive)
In this mode, character synchronization can be internally or externally achieved. If the SYNC mode has
been programmed, ENTER HUNT command should
be included in the first command instruction word
written. Data on the RxD pin is then sampled on the
rising edge of RxC. The content of the Rx buffer is
compared at every bit boundary with the first SYNC
character until a match occurs. If the 8251A has
been programmed for two SYNC characters, the
subsequent received character is also compared;
when both SYNC characters have been detected,

Iscs I I I I
ESD

PEN

L21 Lll

205222-10

In the external SYNC mode, synchronization is
achieved by applying a high level on the SYNDET
pin, thus forcing the 8251A out of the HUNT mode.
The high level can be removed after one RxC cycle.
An ENTER HUNT command has no effect in the
asynchronous mode of operation.

I I
0

CHARACTER LENGTH
0

5
BITS

BITS

7
BITS

BITS

PARITY ENABLE
(1 = ENABLE)
(0 = DISABLE)

EVEN PARITY GENERATION/CHE CK
1 = EVEN
0= ODD

EXTERNAL SYNC DETECT
1 = SYNDET IS AN INPUT
o = SYNDET IS AN OUTPUT

SINGLE CHARACTER SYNC
1 =SINGLE SYNC CHARACTER
0= DOUBLE SYNC CHARACTER

NOTE:

205222-11

In external sync mode, programming double character sync will affect only the Tx.

Figure 10. Mode Instruction Format, Synchronous Mode

2-11

8251A

Parity error and overrun error are both checked in
the same way as in the Asynchronous Rx mode.
Parity is checked when not in Hunt, regardless of
whether the Receiver is enabled or not.

Sync characters are loaded (if in Sync Mode) then
the device is ready to be used for data communication. The Command Instruction controls the actual
operation of the selected format. Functions such as:
Enable Transmit/Receive, Error Reset and Modem
Controls are provided by the Command instruction.

The CPU can commanr:J the receiver to enter the
HUNT mode if synchronization is lost. This will also
set all the used character bits in the buffer to a
"one," thus preventing a possible false SYNDET
caused by data that happens to be in the Rx Buffer
at ENTER HUNT time. Note that the SYNDET F/F is
reset at each Status Read, regardless of whether
internal or external SYNC has been programmed.
This does not cause the 8251A to return to the
HUNT mode. When in SYNC mode, but not in
HUNT, Sync Detection is still functional, but only occurs at the "known" word boundaries. Thus, if one
Status Read indicates SYNDET and a second
Status Read also indicates SYNDET, then the programmed SYNDET characters have been received
since the previous Status Read. (If double character
sync has been programmed, then both sync characters have been contiguously received to gate a SYNDET indication). When external SYNDET mode is
selected, internal Sync Detect is disabled, and the
SYNDET F/F may be set at any bit boundary.

Once the Mode Instruction has been written into the
8251A and Sync characters inserted, of necessary,
then all further "control writes" (C/D = 1) will load a
Command Instruction. A Reset Operation (internal or
external) will return the 8251A to the Mode Instruction format.
NOTE:

Internal Reset on Power-up:
When power is first applied, the 8251 A may come up
in the Mode, Sync character or Command format. To
guarantee that the device is in the Command Instruction format before the Reset command is issued, it is safest to execute the worst-case initialization sequence (sync mode with two sync charaqters). LoadinfL three OOHs consecutively into the device with C/D = 1 configures sync operation and
writes two dummy OOH sync characters. An Internal
Reset command (40H) may then be issued to return
the device to the "idle" state.

COMMAND INSTRUCTION
DEFINITION
Once the functional definition of the 8251A has
been programmed by the Mode Instruction and the

CPU BYTES (5·8 BITS/CHAR)
DATA CHARACTERS
L...._ _ _........_

1-1- - - - - - '

ASSEMBLED SERIAL DATA OUTPUT (hOI
SYNC
CHAR 1

DATACH~~~~_CT_E_R_S

SYNC
CHAR 2

____

RECEIVE FORMAT
SERIAL DATA INPUT (RxD)
SYNC

SYNC

DATA CH;R:CTERS
I-I________~

~_C_H_A_R_l__L-_C_H_A_R_2__L-________~;
CPU BYTES (5-8 BITS/CHARI

r----~/f~---~

DATA CHARACTERS
L....________~,I-,__--~

205222-12

Figure 11. Data Format, Synchronous Mode

2-12

8251A

fH I

I RTS I

fR ISBRKI RxE I DTR IT'EN

TRANSMIT ENABLE
1 ~ enable
o ~ disable

DATA TERMINAL
READY
"high" will force DTR
output to zero

RECEIVE ENABLE
1 ~ enable
o ~ disable

SEND BREAK
CHARACTER
1 ~ forces TxD "low"
o ~ normal operation

ERROR RESET
1 = reset error flags
PE, OE, FE

REQUEST TO SEND
"high" will force RTS
output to lero

INTERNAL RESET
"high" returns 8251 A to
Mode Instruction Format

ENTER HUNT MODE'
1 - enable search for Sync
Characters

'(HAS NO EFFECT IN
ASYNCMODE)

NOTE:

205222-13

Error Reset must be performed whenever RxEnable and Enter Hunt are programmed.

Figure 12. Command Instruction Format

A normal "read" command is issued by the CPU
with C/O = 1 to accomplish this function.

STATUS READ DEFINITION
In data communication systems it is often necessary
to examine the "status" of the active device to ascertain if errors have occurred or other conditions
that require the processor's attention. The 8251A
has facilities that allow the programmer to "read"
the status of the device at any time during the functional operation. (Status update is inhibited during
status read.)

Some of the bits in the Status Read Format have
identical meanings to external output pins so that
the 8251A can be used in a completely polled or
interrupt-driven environment. TxRDY is an exception.

2-13

Inter

8251A

Note that status update can have a maximum delay of 28 clock periods from the actual event affecting the
status.

I I I I I I I
DSR

SYNDETI
BRKDET·

TxEMPTY

RxRDY

TxRDY

1 1

SAME DEFINITIONS AS 110 PINS

PA~ITY ERROR
The PE flag is set when a parity
error is detected. It is reset by .
the E R bit of the Command
Instruction. PE does not inhibit

operatIOn of the 8251 II

OVERRUN ERROR
The OE flag IS set when the CPU

does not read a character before
the next one becomes available .

reset by the ER bot of the

Command Instruction. OE does
not inhibit operation of the 8251 A
however. the previously ov~rrun
character is lost.

FRAMING ERROR IAsync onlyl
The FE flag is set when a valid
Stop bit is not detected at the
end of every character. It IS reset
by the E R bot of the Command
Instruction. FE does not Inhibit

the operation of the 8251 A.

DATA SET READY: Indocates
that the DSR IS at a zero level.

205222-14

NOTE:
1. TxRDY status bit has different meanings from the TxRDY output pin. The former is not conditioned by CTS and TxEN;
the latter is conditioned by both CTS and TxEN.
i.e. TxRDY status bit = DB Buffer Empty
TxRDY pin out = DB Buffer Empty • (CTS = 0) • (TxEN = 1)

. Figure 13. Status Read Format

2-14

infef

8251A

APPLICATIONS OF THE 8251A
ADDRESS BUS

CONTROL BUS

DATA BUS

r----'

I----tl
I
8251A

~--- L

EIA TO TTL
CONVERT
(OPT)
__
__

I'
I

..1

BAUD RATE
GENERATOR

205222-15

Figure 14. Asynchronous Serial Interface to CRT Terminal, DC-9600 Baud

)

ADDRESS BUS

I
I

)

CONTROL BUS

DATA BUS

J~~~
RxD
TxD
8251A

RxC
TxC

SYNCHRONOUS
TERMINAL
OR PERIPHERAL
DEVICE

:---l

SYNDET

205222-16

Figure 15. Synchronous Interface to Terminal or Peripheral Device

2-15

8251A

AP~LlCATIONS

OF THE 8251A (Continued)

PHONE
LINE
INTER·
FACE

TELEPHONE
LINE

205222-18

Flgur. 16. Asynchronous Interface to Telephone Lines

PHONE
LINE
INTER·
SYNC

FACE

MODEM

TELEPHONE

LINE

205222-17

Figure 17. Synchronous Interface to Telephone Lines
NOTES:
1. AC timings measured VOH = 2.0 VOL = 0.8, and with load circuit of Figure 18.
2. Chip Select (CS) and Command/Data (C/O) are considered as Addresses.
3. Assumes that Address is valid before RD J..
.
4. This recovery time is for Mode Initialization only. Write Data is allowed oniy when TxRDY = 1. Recovery Tlme between
Writes for Asynchronous Mode is 8 lev and for Synchronous Mode is 16 lev.
5. The TxC and RxC frequencies have the fOllowing limitations with respect to ClK: For 1x Baud Rate, t,-x or fRx ~
1/(30 tev): For 16x anil64x Baud Rate, fTx or fRx ~ 1/(4.5 leV). This applies to Baud Rates iessthan or equal to 64K Baud.
6. Reset Pulse Width = 6 lev minimum; System clock niust be running during Reset.
7. Status update can have a maximum delay of 28 clock periods from the event affecting the status.
8. In extemal. sync mode the tes spec. requires the ratio of the system clock (clock) to receive or transmit bit ratios to be
greater than 34. .
9. A float is defined as the pOint where the data bus falls below a logic 1 (2.0V @ IOH limit) or rises above a logic 0 (0.8V @
IOLlimit).

2-16

intJ

8251A

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Ambient Temperature Under Bias ...... O°C to 70°C
Storage Temperature .......... -65°C to

+ 150°C

Voltage on Any Pin
with Respect to Ground .......... - 0.5V to

+ 7V

Power Dissipation ........................... 1W

D.C. CHARACTERISTICS
Symbol

TA = O°C to 70°C, Vee = 5.0V ±10%, GND = OV'

Parameter

Min

Max

Test Conditions

Unit

Vil

Input Low Voltage

-0.5

0.8

VIH

Input High Voltage

2.0

Vee

Val

Output Low Voltage

VOH

Output High Voltage

IOFL

Output Float Leakage

±10

p.A

VOUT = Vee to 0.45V

III

Input Leakage

±10

p.A

VIN = Vee to 0.45V

lee

Power Supply Current

100

All Outputs = High

CAPACITANCE
Symbol

0.45
2.4

TA = 25°C, Vee = GND =

Parameter

IOl = 2.2mA

IOH = -400 p.A

Min

Max

Unit

Test Conditions

CIN

Input Capacitance

fe = 1 MHz

ClIO

I/O Capacitance

Unmeasured pins returned
toGND

A.C. CHARACTERISTICS

T A = O°C to 70°C, Vee = 5.0V ± 10%, GND = OV'

Bus Parameters (Note 1)
READ CYCLE
Symbol

Max

Unit

Test Conditions

Parameter

Min

tAR

Address Stable Before READ (CS, C/O)

(Note 2)

tRA

Address Hold Time for READ (CS, C/O)

(Note 2)

tRR

READ Pulse Width

tRO

Data Delay from READ

tOF

READ to Data Floating

250
10

ns
200

3,Cl = 150 pF

100

(Note 1,9)

WRITE CYCLE
Symbol

Parameter

Min

Max

Unit

tAW

Address Stable Before WRITE

tWA

Address Hold Time for WRITE

tww

WRITE Pulse Width

250

tow

Data Set~Up Time for WRITE

150

tWD

Data Hold Time for WRITE

tRY

Recovery Time Between WRITES

tey

2-17

Test Conditions

(Note 4)

inter

8251A

A.C. CHARACTERISTICS

(Continued)

OTHER TIMINGS
Parameter

Symbol

Min

Max

Unit

tCY

Clock Period

320

1350

tq,

Clock High Pulse Width

120

tCy-90

tq,

Clock Low Pulse Width

tR, tF

Clock Rise and Fall Time

tDTx

TxD Delay from Falling Edge of TxC

fTx

Transmitter Input Clock Frequency
1x Baud Rate
16x Baud Rate
64x Baud Rate

DC
DC
DC

Transmitter Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate

12
1

tCY
tCY

Transmitter Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate

15
3

tCY
tCY

Receiver Input Clock Frequency
1x Baud Rate
16x Baud Rate
64x Baud Rate

DC
DC
DC

Receiver Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate

12
1

tCY
tCY

Receiver Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate

15
3

tCY
tCY

tTPW

tTPD

fRx

tRPW

tRPD

tTxRDY

TxRDY Pin Delay from Center of Last Bit

tTxRDY CLEAR

TxRDY

tRxRDY

RxRDY Pin Delay from Center of Last Bit

tRxRDY CLEAR

RxRDY

tiS

Internal SYNDET Delay from Rising
Edge of RxC

tES

External SYNDET Set-Up Time After
Rising Edge of RxC

tTxEMPTY

TxEMPTY Delay from Center of Last Bit

twc

Control Delay from Rising Edge of
WRITE (TxEn, DTR, RTS)

teR

Control to READ Set-Up Time (DSR, CTS)

.!
.!

from Leading Edge of WR

from Leading Edge of RD

16tCY

-NOTE:

For Extended Temperature EXPRESS, use MIL 8251A electrical parameters.

2-18

Test Conditions
(Note 5, 6)

ns
20

/Ls

64
310
615

kHz
kHz
kHz

64
310
615

kHz
kHz
kHz

tCY

(Note 7)

400

(Note 7)

tCY

(Note 7)

400

(Note 7)

tCY

(Note 7)

tRPD-tCY

(Note 7)

tCY

(Note 7)

tCY
tCY

(Note 7)
(Note 7)

intJ

8251A

A.C. CHARACTERISTICS (Continued)
TYPICAL I:l OUTPUT DELAY VS. I:l CAPACITANCE (pF)
'20

'10
c

...J

....

::l

....
::l

..,

-10

-20
-100

' " SPEC.

;

-50

+50

+100

.; CAPACITANCE (pF)

205222-19

A.C. TESTING INPUT, OUTPUT WAVEFORM

u=x
. >
2.0

TEST POINTS

0.45

0.8

A.C. TESTING LOAD CIRCUIT

< )C
.
2.0

8251A

0.8

205222-20

AC Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "1" and O.BV for a Logic "0".

t,·

OUT

C l = 150 pF
205222-21

Figure 18

WAVEFORMS
SYSTEM CLOCK INPUT

CLOCK

205222-22

2-19

<
m
'TI

(

o:D
s:
CJ)

TRANSMITTER CLOCK AND DATA

T.C (Ix MODE)

::J

g
c:

CI)

~(16.MODE)

--l

!=tOTX

tOTX--l

T. D A T A ) (

1:=

--x==

Xl-,- - - - - - - - - .

205222-23

CD
p,)

I\)

ro
o

U1
....
»

RECEIVER CLOCK AND DATA
(R. BAUD COUNTER STARTS HERE)
START BIT

RxDATA

.1,

DATA BIT

I.
t RPO
.1
tRPW-----!·l~------.....

RxC (1x MODEl
_

8 RxC PERIODS
(16. MODE)

_ 1 _ 16 R.C PERIODS (16x MODE)

RxC (16 MODEl

INT SAMPLING
PULSE

205222-24

8251A

WAVEFORMS (Continued)
WRITE DATA CYCLE (CPU TxRDY

DATA IN (D.B.I

USART)

___---J/

_ ________~DO~N.~T~C~A~R~E____~~~~~~~~----~DO~N~.~T~C~A~R~E---

c/o

205222-25

READ DATA CYCLE (CPU -

USART)

...J/

R.RDY _ _ _ _ _

\Lj'-I_ _ _ _ _ _ _ ____

___________________...,1 ~~=~Y CLEA~I r-------~.
t

---lI

I-'RD

~'DF

DATA OUT (D.B.I _____~D~AT!!A~F~L:!!O~AT!.______t-{~D~A~T~A~O~UT~AC~T~IV~EP-D~A~T~Ac!F:!::LO~A~T

c/O

-------~~-------+-~--

. 205222-26

2-21

inter

8251A

WAVEFORMS (Continued)
~

WRITE CONTROL OR OUTPUT PORT CYCLE (CPU
OTR. RTS
(NOTE =1)

Vir

USART)

--------------_________===x=.j ________
.

I-

I-t -11~

------,---~-~

twc

I-'tow ~ ::jtwo
DATA IN (O.B.I

C/D

;~-------------

1--

tAW

____________~t
----------~----""'

---I

tWA

1-·

tA. W

---I

________

tWA

~~-----~y~----205222-27

READ CONTROL OR INPUT PORT (CPU +- USART)
OSR. CTS
\/,
(NOTE =2) _______~~A~.----------~------------------------

~.II-- tRR _I

______----,I__-__

tcR_ _ _

DATA OUT
(O.B.)

C/O

-+l

1- tRO

-I tAR I--

r-----

---

1--

tRA

------~----~!I

--I

tOF

r-~~___

tAR

I---

tRA

1;==

----------~~~--------------~y

205222-28

NOTES:
1. Twe includes lhe response timing of a control byte.
2. T CR includes the effect of CTS on the TxENBL circuitry.

2-22

<
m

TRANSMITTER CONTROL AND FLAG TIMING (ASYNC MODE)

"T1

CTS

thEMPTY_~

o
:II
s::
en

EMPTY

(ST:~~~~~;;

'0
o
;a

::;'
c

Tx REAOY

(PIN)

CID
Wr SBRK

w;
hOATA

Example Format

Q-_NM..,.In'O

DATA CHAR 3

DATA CHAR 2

DATA CHAR 1

I-DATA CHAR 4

7 Bit Character With Parity & 2 Stop Bits,

~
o

205222-29

0:1

I\)

...

I\)

N
c.:>

RECEIVER CONTROL AND FLAG TIMING (ASYNC MODE)
,----

BAt AK P[ He I
f 1-"'MINt; f HHUH

SIAT\JS {I:I

UVI RHUPII t RHOR
ISTA1US81l,

~
CHAR 2

riA_ROY

LOST

r---

f\o ROY

~A.l"

RX-l-HH1-HHH
• .om

....

Example Format

....

'W,OATA
CHAR 5

MAl£:JJr:JJ.~
STATE

a ••

= 5 Bit Character With Parity. 2 Sync Characters,

STATE

L-.JJ

SBRK .

11:\

SVN':\

DATA
CHAR 2

W'~OMMA'::!

'tV, DATA
CHAR 3

W. DATA

...

COMMAND
SBRK .

STATE

DATA
CHAR 5

SVr-..C
CHAR

-I·X,y,x· -..
-I-I·A'NoJ.-.-A-X'
205222-31

RECEIVER CONTROL AND FLAG TIMING (SYNC MODE)

o::zJ

3!:

SVI\IOfT
IPINI NOTE
1

I
'15_

il-

tES_

SVNOE T IS,BI

1-fL-

OVERRUN

+
Rd STATUS
I

--.iW,EH \
R.En

Rd DATA

Rd OAT A
CHAR3

-U
DON'T
CARE

/
RdSTATUS
WrEHa

Rd SYNC-

C»

Rd STATUS

1\ .

Rd DATA

1CHAR 1

SYNC
CHAR 1

SYNC
CHAR 2

DATA
CHAR 1

\n
DATA
CHAR 2

ll
DATA
CHAR3

'\l{VNC
CHAR 1

\r "\l/

SVNCCHAR 2

DATA
CHAR 1

DON'TeARE

DATALII
CHAR 2

ETC.

• °X'X'X'I'I~ol' , 'x·x~YYYY)
~
!If ~EGINSlJU1 .rut

x,x,x'H,x'xox'x'x,x·mox,x'x,x·mox·x~'I·mol·l,x,x·mox·x,x,x·mox·x,x,X·X,'X'X'X'X'X'N'

TTTTTTTTTTT~llrIs~!J!~lTTTTTT

R. CLOCK

EXIT HUNT MODE
SET SYNC DET

CHAR ASSY

E)(IT HUNT MODE

SET SVN DEl (STATUS BITI

SET SYNDET (STATUS BIT)

205222-32

NOTES:
1. Internal Sync. 2 Sync Characters, 5 Bits With Parity.
2. External Sync, 5 Bits, With Parity.

....
01

\....

R.i

RII DATA

ri\'

CHAR 1
II;~'

::::J

f--

b~f\- 1/

JtL-k/

Rx ROY (PIN)

_fDAT~;S~AH 2 ~

ERROR IS.,BI

~
U1

r~OTEU

82050
ASYNCHRONOUS COMMUNICATIONS CONTROLLER

•
•

Asynchronous Operation
- 5- to 8-Bit Character Format
- Odd-, Even-, or No-Parity Generation
and Detection
- Serial Bit Rate: DC to 56 Kb/s
Programmable, 16-Bit Baud Rate
Generator

Clock
• -System
On-Chip Crystal Oscillator
- Externally Generated Clock

•
•

28-Lead DIP and PLCC Packages
IBM PC (INS 16450/8250A) Software
Compatible

•
•
•
•
•
•

Seven I/O Pins
- Dedicated Modem 1/0
- General Purpose 1/0
No-TIL Interface to Most Intel
Processors
Internal Diagnostics with Local
Loopback
Complete Interrupt and Status
Reporting
CHMOS III Technology Provides
Increased Reliability and Reduced
Power Consumption
Line Break Generation and Detection

The Intel CHMOS 82050 Asynchronous Communications Controller is a low cost, higher performance alternative to the INS 16450-it emulates the INS 16450 and provides 100% compatibility with IBM PC software. Its
28-lead package provides all the functionality necessary for an IBM PC environment while substantially decreasing board space requirements. The 82050's simpler system interface reduces TTL glue-especially for
higher frequency PC bus designs. The 82050 provides alow cost, high-performance integrated modem solution when combined with Intel's 89024 modem chip set. The compact 28-pin 82050 is fabricated using
CHMOS III technology for decreased power consumption and increased reliability.

vee
vss
TxD
A(2-0)
D(7-0)
RxD

INT
RESET

Ri5

BUS
.INTERFACE
UNIT

16X
RxC

16X
TxC

WR
CS

OUT2

Ri
MODEM I/O
CLKX1
X2

DSR
DCD
DTR
RTS
CTS
290137-1

Figure 1. Block Diagram

2-26

August 1990
Order Number: 290137-004

inter

82050

iID

04
05
06
07
INT
TXO
VSS
OUT2/X2
ClK/Xl

OSR

OSR
OCO
RXO
CTS

00
A2
Al
AO
VCC

INT
TXO
VSS
OUT2/X2
ClK/Xl

290137-2

03
02
01
00
A2
Al
AD
VCC

iID

RESET
RTS
OTR
290137-3

Figure 2. PLCC Pinout

Figure 3. DIP Pinout

82050 PINOUT DEFINITION
Pin
No.

Type

RESET

RESET: A high on this input pin resets the 82050.

CHIP SELECT: A low on this input pin enables the 82050 and allows
read or write operations.

A2-AO

24-22

ADDRESS PINS: These inputs interface with three bits of the syst;::~.,
address bus to select one of the internal registers for read or write.

07-00

1-4
25-28

1/0

READ: A low on this input pin allows the CPU to read data or status
bytes from the 82050.

WRITE: A low on this input allows the CPU to write data or control
bytes to the 82050.

INT

INTERRUPT: A high on this output pin signals an interrupt request to
the CPU. The CPU may determine the particular source and cause of
the interrupt by reading the 82050 status registers.

ClK/X1

MULTIFUNCTION: This input pin serves as a source for the internal
system clock. The clock may be asynchronous to the serial clocks and
to the processor clock. This pin may be used in one of two modes:
ClK-in this mode an externally generated clock should be used to
drive this input pin; X1-in this mode the clock is generated by a crystal
to be connected between this pin (X1) and the X2 pin. (See system
clock generation.)

OUT2/X2

MULTIFUNCTION: This is a dual-function pin which may be configured
to one of the following functions: OUT2-a general purpose output pin
controlled by the CPU is only available when the ClK/X1 pin is driven
by an externally generated clock; X2-this pin serves as an output pin
for the crystal oscillator. Note: The configuration of pin is done during
hardware reset. For more details refer to the system clock generation.

Symbol

Name and Description

DATA BUS: Bi-directional, three state, 8-Bit Data Bus. These pins
allow transfer of bytes between the CPU and the 82050.

2-27

82050

82050 PINOUT DEFINITION (Continued)
Pin
No.

Type

Name and Description

TXD

TRANSMIT DATA: Serial data is transmitted via this output pin starting
at the least significant bit.

RXD

RECEIVE DATA: Serial data is received on this input pin starting at the
least significant bit.

RING INDICATION: RI- Ring indicator-input, active low. This is a
general purpose input accessible by the CPU.

DTR

DTR-DATA TERMINAL READY: Output, active low. This is a general
purpose output pin controlled by the CPU. During hardware reset, this
pin is an input used to determine the system clock mode. (See System
Clock Generation.)

DSR

1/0

DSR-DATA SET READY: Input, active low. This is a general purpose
input pin accessible by the CPU.

RTS

RTS-REQUEST TO SEND: Output, active low. This is a general
purpose output pin controlled by the CPU. During hardware reset, this
pin is an input used to determine the system clock mode. (See system
clock generation)

CTS

CLEAR TO SEND: Input active low. This is a general purpose input pin
accessible by the CPU.

DCD

1/0

vce

VCC: Device power supply.

VSS

VSS: Ground.

Symbol

DCD-DATA CARRIER DETECT.ED: Input, active low. This is a
general purpose input pin accessible by the CPU.

SYSTEM INTERFACE

CRYSTAL OSCILLATOR

The 82050 has a simple demultiplexed bus interface
which consists of a bidirectional, three-state, 8-bit
data bus and a 3-bit address bus. The Reset, Chip
Select, Read, and Write pins, along with the Interrupt
pin, provide the remaining signals necessary to interface to the CPU. The 82050's system clock can be
generated externally and provided through the ClK
pin; or its on-chip crystal oscillator can be used by
attaching a crystal to the X1 and X2 pins. For compatibility with IBM PC software, a system clock of
18.432 MHz (with divide by two enabled) is recommended. The 82050, along with a transceiver, address decoder, and a crystal, complete the interface
to the IBM PC Bus.

-:F7:f"I
rl~

290137-4

Parallel Resonant Crystal Freq. Max = 18.432 MHz
(Divided by 2)

Figure 4. Crystal Oscillator
X2 pins. The oscillator frequency is divided by two
before being inputted into the chip circuitry. If an
18.432 MHz crystal is used, then the actual system
clock frequency of the 82050 will be 9.216 MHz.
This mode is configured via a strapping option on
the RTS pin.

SYSTEM CLOCK OPTIONS

It is very important to distinguish between the clock
frequency being supplied into the 82050 and the
system clock frequency. The term system clock refers to the clock frequency being supplied to the
82050 circuitry (divided or undivided). The following
examples delineate the three options for clock usage and their effect on the 82050 system clock as
well as on the BRG source frequency:

The 82050 has two modes of system clock operation. It can accept an externally generated clock, or
use a crystal to internally generate its system clock
by using the on-chip oscillator.
The 82050 has an on-chip oscillator which can· be
used to generate its system clock. The oscillator will
take the input from a crystal attached to the X1 and
2-28

inter

82050

1. Crystal Oscillator: (Maximum 18.432 MHz)
- System Clock Frequency = Crystal
Frequency/2
- BRG Source Clock Frequency = Crystal
. Frequency/10
2. External Clock (Divide by Two Enabled):
(Maximum 18.432 MHz)
- System Clock Frequency = External Clock
Frequency/2
- BRG Source Clock Frequency = External
Clock Frequency/10
3. External Clock (Divide by Two Disabled):
(Maximum 9.216 MHz)
- System Clock Freq. = External Clock Frequency
- BRGSource Clock Freq. = External Clock
Frequency/5

NOTE:
The use of the Divide by Two strapping option in
the crsytal oscillator mode is forbidden.

BAUD RATE GENERATION
The 82050 has a programmable 16-bit Baud Rate
Generator (BRG). The 16X baud rate is generated
by dividing the source clock with the divisor count
from the BRG divisor registers (BAL, BAH). The
BRG source clock is the 82050 system clock divided
by five. If using an actual 82050 system clock of
9.216 MHz, then the BRG source clock will be 9.216
MHz/5 = 1.8432 MHz, which is compatible with the
BRG source clock fed into the IBM PC serial port
BRG. This allows the 82050, while using a faster
system clock, to maintain full compatibility with software divisor calculations based on the 1.8432 MHz
clock used in the IBM PC.

RESET
The 82050 can be reset by asserting the RESET pin.
The RESET pin must be held high for at least 8 system clock cycles. If using crystal oscillator, a reset
pulse at least 1 ms should be used to ensure oscillator start up. Upon reset, all 82050 registers (except
TXD and RXD) are returned to their default states.
During reset, the 82050's system clock mode of operation is also selected by strapping options on the
RTS and DTR pins (see system clock generation).

290137-5

Figure 5. Strapping
During the power up or reset the RTS pin is an input;
it is weakly pulled high internally and sampled by the
falling edge of reset. If it is driven low externally,
then the 82050 is configured for a crystal oscillator;
otherwise an externally generated clock is expected.

INTERRUPTS
The INT pin will go high, or active, whenever one of
the following conditions occurs provided it is enabled in the interrupt enable register (IER):
a. Receive Machine Error or Break Condition
b. Receive Data Available
c. Transmit Data Register Empty
d. Change in the State of the Modem Input Pins.

EXTERNALLY GENERATED SYSTEM
CLOCK

~t' I

The INT pin will be reset (low) when the interrupt
source is serviced. The Interrupt Identification Register (IIR) along with the Line Status Register (LSR)
and the Modem Status Register (MSR) can be used
to identify the source requesting service. The IIR
register identifies one of the four conditions listed
above. The particular event or status, which triggers
the interrupt mechanism, can be identified by reading either the Line Status Register or the Modem
Status register. If multiple interrupt sources become
active at anyone time, then highest priority interrupt
source is reflected in the IIR register when the interrupt pin becomes active. Once the highest priority
interrupt is serviced, then the next highest priority

OUT2

290137-6

Figure 7. External Clock
This is the default mode of system clock operation.
The system clock is divided by two; however, the
user may disable the divide by two by a hardware
strapping option on the DTR pin. The strapping option is similar to the one used on the RTS pin.

2-29

82050

(HIGHEST PRIORITY)
-

Rx CONDITION

------I.

;r-- Rx DATA AVAILABLE
r - - Tx DATA REGISTER STATUS

INTERRUPT _ _ _ _ _

- - - - MODEM

E
E

--------1

(LOWEST PRIORITY)

Rx PARITY ERROR
OVERRUN ERROR
BREAK DETECTED
FRAMING ERROR
DCD STATE CHANGE
RI STATE CHANGE
DSR STATE CHANGE
CTS STATE CHANGE
290137-7

Figure 8. Interrupt Structure

interrupt source is decoded into the IIR register; the
whole procedure is repeated until there are no more
pending interrupt sources.

TRANSMIT

The falling edge of the start bit triggers the RX Machine, which then starts sampling the RXD input (3
samples). If the samples do not indicate a start bit,
then a false start bit is determined and the RX Machine returns to the start bit search mode. Once a
start bit is detected, the RX Machine starts sampling
for data bits.

The 82050 transmission mechanism involves the TX
Machine and the TXD Register. The TX Machine
reads characters from the TXD Register, serializes
the bits, and transmits them over the TXD pin according to signals provided for transmission by the
Baud Rate Generator. It also generates parity, and
break transmissions upon CPU request.

If the RXD input is low for the entire character time,
including stop bits, then the RX Machine sets Break
Detect and Framing Error bits in the Line Status
Register (LSR). It loads a NULL character into the
RXD register. The RX Machine then enters the idle
state. When it detects a MARK it resumes normal
operation.

RECEIVE
The 82050 reception mechanism involves the RX
Machine and the RXD Register. The RX Machine
assembles the incoming characters, and loads them
onto the RXD Register. The RX Machine synchronizes the data, passes it through a digital filter to filter
out spikes, and then uses three samples to generate
the bit polarity.

SOFTWARE INTERFACE
. Like other 1/0 based peripherals, the 82050 is programmed through its registers to support a variety of
functions. The 82050 register set is identical to the
16450 register set to provide compatibility with software written for the IBM PC. The 82050 register set
occupies eight addresses and includes control,
status, and data registers. The three address lines
and the Divisor Latch Access Bit are used to select
the 82050 registers.

2-30

(

o·

TxD

TxData
Bit?

Tx Data
Bit6

TxData
Bit 5

Tx Data
Bit4

TxData
Bit3

TxData
Bit2

Tx Data
Bit 1

Tx Data
BitO

RxD

RxData
Bit?

Rx Dat~
Bit 6

Rx Data
Bit5

RxData
Bit4

Rx Data
Bit3

Rx Data
Bit 2

Rx Data
Bit 1

Rx Data
BitO

= 1)
BRGA MSB Divide Count (DLAB = 1)

BAL

BRGA LSB Divide Count (DLAB

BAH
IER

IIR

Parity
Mode
Bit2

Parity
Mode
Bit 1

Parity
Mode
Bit 0

Loopback
Control Bit

OUT2
Complement

Modem
Interrupt
Enable
0

Address

Default

02H

OOH

RxMachine
Interrupt
Enable

Tx Data
Interrupt
Enable

Rx Data
Interrupt
Enable

OOH

Active
Interrupt
Bit 1

Active
Interrupt
BitO

Interrupt
Pending

01H

Stop Bit
Length
Bit 0

Character
Length
Bit 1

Character
Length
BitO

OOH

RTS
Complement

DTR
Complement

OOH

Overrun
Error

Rx Data
Available

60H

State
Change
inDSR

State
Change
inCTS

OOH

CC)
I\)

I\)

LCR

DLAB
Divisor
Latch
Access Bit

MCR

LSR

MSR

DCD Input
Inverted

SCR

Set
Break

TxM
Status

TxD
Empty

Break
Detected

Framing
Error

Parity
Error

Rllnput
Inverted

DSR Input
Inverted

CTS Input
Inverted

State
Change
inDCD

State (H
Change
inRI

Scratch-Pad Register
Figure 9. Register Description Table

o
CJ'I
o

82050

TRANSMIT DATA REGISTER (TXD)

BRG DIVISOR LOW BYTE (BAL)

This register holds'the next data byte to be transmitted. When the transmit shift register becomes empty, the contents of the Transmit Data Register are
loaded into the shift register and the Transmit Data
Register Empty condition becomes true.

This register contains the least significant byte of the
Baud Rate Generator's 16-bit divisor. This register is
accessible only when the DLAB bit is set in the LCR
register.

290137-10
BAL-BRG Divisor Low Byte

290137-8
" TXD-Transmlt Data Register

RECEIVE DATA REGISTER (RXD)
This register holds the last character received by the
RX Machine. The character is right justified and the
leading bits are zeroed. Reading the register empties the register and resets tl)e Received Character
Available condition. '

BRG DIVISOR HIGH BYTE (BAH)
This register contains the most significant byte of
the Baud Rate Generator's 16-bit divisor; This register is accessible ony when the DLAB bit is set in the
LCR register.

290137-11
BAH-BRG Divisor High Byte

290137-9
RXD-Recelve Data Reglater

2-32

82050

INTERRUPT ENABLE REGISTER (IER) .
This register enables four types of interrupts which independently activate the INT pin. Each of the four
interrupt types can be disabled by resetting the appropriate bit of the IER register. Similarly by setting the
appropriate bits, selected interrupts can be enabled. If all interrupts are disabled, then the interrupt requests
are inhibited from the IIR register and the INT pin. All other functions, including Status Register and the Line
Status Register bits continue to operate normally.

290137-12
IER-Interrupt Enable Register

MIE-MODEM Interrupt Enable
RXIE-RX Machine Interrupt Enable
TXDE-TX Data Register Empty
RXDA-RX Data Available

INTERRUPT IDENTIFICATION REGISTER (IIR)
This register holds the highest priority enabled and active interrupt req'uest. The source of the interrupt request
can be identified by reading bits 2-1.

[~ I III

76151413121~O

RESERVED

_______.

•

-~;~::RUPT PENDING

--------el} INTERRUPT

-+ RESERVED

1.-_ _ _

290137-13
IIR-Interrupt Identification Register

B1, BO-Interrupt Bits, 2-1. These two bits reflect the highest priority, enabled and pending interrupt request.
11: RX Error Condition (Highest Priority)
10: RX Character Available
01: TXD Register Empty
00: Modem Interrupt (Lowest Priority)
lPN-Interrupt Pending-This bit is active low, and indicates that there is an interrupt pending. The interrupt
logic asserts the INT pin as soon as this bit goes active (NOTE: the IIR register is continuously updated; so
while the user is serving one interrupt source, a new interrupt with higher priority may enter IIR and replace the
older interrupt vector).

2-33

Intel

82050

LINE CONTROL REGISTER (LCR)
This is a read/write register which defines the basic configuration of the serial link.

DlAB

ClO} CHARACTER
ell lENGTH

SBK - SET BACK
PARITY

'-----+

[:~~ +-___

SBlO - STOP BIT lENGTH

...:....1

+-_ _ _ _ _..J

PMO

290137-14
lCR-Llne Configure Register

DLAB~Divisor

BAH.

Latch Access Bit-This bit, when set, allows access to the Divisor Count Registers BAL and
-

SBK-5et Break-This will force the TXD pin low. The TXD pin will remain low until this bit is reset.
PM2-PMO-Parity Mode Bits-These three bits are used to select the variol)s parity modes of the 82050.
PMO

PM2

PM1

Function

0
1
1
1
1

X
0
1
0
1

No Parity
Odd Parity
Even Parity
High Parity
Low Parity

0
0
1
1

SBL-Stop Bit Length-This bit defines the Stop Bit lengths for transmission. The RX Machine can identify
3/4 stop bit or more.
SBL
0
1
1

Character Length

Stop Bit Length

X
5-Bit
(6, 7, or 8-Bit)

1
11/2
2

CLO-CL 1-Character Length-These bits define the character length used on the serial link.
CL1

CLO

0
0
1
1

Character Length
5 Bits
6 Bits
7 Bits
8 Bits

1
0
1

2-34

inter

82050

LINE STATUS REGISTER (LSR)
This register holds the status of the serial link. When read, all bits of the register are reset to zero.

~rl'I'I'I~

'm-~ """'" ~""';
RESERVED

TXDE - TXD EMPTY

IIII ;

BKD- BREAK DETECTED

RXDA - RX DATA AVAILABLE

0'-0""'"" "'"
PE - PARITY ERROR

FE- FRAMING ERROR
290137-15
LSR-Line Status Register

RXDA-RX Data Available-This bit, indicates that the RXD register has data available for the CPU to read.
OE-Overrun Error-Indicates that a received character was lost because the RXD register was not empty.
PE Parity Error-Indicates that a received character had a parity error.
FE-Framing Error-Indicates that a received character had a framing error.
BkD-Break Detected-This bit indicates that a break condition was detected, i.e., RxD input was held low
for two character times.
TXDE-TXD Empty-This indicates that the 82050 is ready to accept a new character for transmission. In
addition, this bit causes an interrupt request to be generated if the TXD register Empty interrupt is enabled.
TXST- TX Machine Status-When set, this bit indicates that the TX Machine is Empty, i.e., both the TXD
register and the TX Shift Register are empty.

MODEM CONTROL REGISTER (MCR)
This register controls the modem output pins. All the outputs invert the data, i.e., their output will be the
complement of the data written into this register.

290137-16
MCR-Modem Control Register

2-35

82050
LC-Loopback Control-This bit puts the 82050 into a Local Loopback mode.
OUT2-oUT2 Output-This bit controls the OUT2 pin. The output signal is the complement of this bit.
NOTE:
This bit is only effective when the 82050 is being used with an externally generated clock.
RTS-RTS Output Bit-This bit controls the RTS pin. The output signal is the complement of this bit.
DTR-DTR Output Bit-This bit controls the DTR pin. The output signal is the complement of this bit.

MODEM STATUS REGISTER (MSR)
This register holds the status of the modem input pins (CTS, DCD, DSR, RI). It is the source of Modem
interrupts (bits 3-0) when enabled in the IER register. If any of the above input pins change levels, then the
appropriate bit in MSR is set. Reading MSR will clear the status bits.

~ ~I"'I'I'I~
I11I
"'~ .'"'~,

ro.,uoorr
COMPLEMENT RI ;

STATE CHANGE DSR

(H --> L) ill

COMPLEMENT DSR
COMPLEMENT CTS

STATE CHANGE DCD

290137-17

MSR-Mode Status Register

DCDC-DCD Complement-Holds the complement of the DCD pin.
DRIC-RI Complement-Holds the complement of the RI pin.
DSRC-DSR Complement-Holds the complement of the DSR pin.
CTSC-CrS Complement-Holds the complement of the CTS pin.
DDCD-Delta DCD-Indicates that the DCD pin has changed state since this register was last read.
DRI-Delta RI-Indicates that the RI pin has changed state from high to low since this register was last read.
DDSR-Delta DSR-Indicates that the DSR pin has changed state since this register was last read.
DCTS-Delta CTS-Indicates that the CTS pin has changed state since this register was last read.

SCRATCHPAD REGISTER (SCR)
The 8-bit Read/Write register does not control the ACC. It is intended as a scratch pad register for use by the
programmer.

2-36

intJ

82050

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

D.C. SPECIFICATIONS

Storage Temperature .......... - 65°C to + 150°C

Ambient Temperature under Bias ...... O°C to 70°C
Voltage on any Pin (w.r.t. Vss . -O.5Vto Vee+0.5V
Voltage on Vee Pin (w.r.t. VSS) ...... -0.5V to +7V
Power Dissipation ....................... 300 mW

D.C. CHARACTERISTICS
Symbol

(TA

0° TO 70°C, Vee

Parameter

5V ±10%)

Notes

Min

Max

Units

VIL

Input Low Voltage

(1 )

-0.5

0.8

VIH

Input High Voltage

(1), (7)

2.0

Vee
+0.5

VOL

Output Low Voltage

(2), (9)

0.45

VOH

Output High Voltage

(3), (9)

2.4

III

Input Leakage Current

(4)

±10

ILO

3-State Leakage Current

(5)

±10

/-LA

IOHR

Input High for DTR, RTS

(10)

0.4

IOLR

Input Low for DTR, RTS

(10)

LXTAL

X1, X2 Load

Icc

Power Supply Current

(6)

3.8
35

mA/MHz
mA (max)

Cin

Input Capacitance

(8)

Cio

I/O Capacitance

(8)

CXTAL

X1, X2 Load

NOTES:

1. Does not apply to CLK/X1 pin, when configured as crystal oscillator input (X1).
2. @ 101 =2 mAo
3. @ loh = -0.4 mA.
4. 0 < Vin < Vee.
5. 0.45V < Vou! < (Vee - 0.45).
6. Vee = 5.5V; Vii - 0.5V (max); Vih = Vee - 0.5V (min); 101 = loh = 0; 9.2 MHz (max).
7. VIH = 2.4V on RD and RXD pins.
S. Freq = 1 MHz.
9. Does not apply OUT2/X2 pin, when configured as crystal oscillator output (X2).
10. Input current for DTR, RTS pins during Reset for Clock Mode Configuration.

2-37

/-LA

. 82050

SYSTEM CLOCK SPECIFICATIONS

A.C. SPECIFICATIONS

Symbol

Parameter

Min

Max

Notes

250

(2)

TCH1CH2 ClK Rise Time

(1)

TCl2Cl1

ClK Fall Time

(1)

FXTAl

External Crystal
4.0 18.432
Frequency Rating
MHz

DIVIDE BY TWO OPTION-ACTIVE

• In the following tables, the units are ns, unless
otherwise specified.
System Interface Specification-System Clock.
Specification:

Tcy/2

ClK Period

TClCH

ClKlowTime

TCHCl

ClK High Time

DIVIDE BY TWO OPTION"":'-INACTIVE

The 82050 system clock is supplied via the ClK pin
or generated by on-chip crystal oscillator. The clock
is optionally divided by two. The ClK parameters are
given separately for internal divide-by-two option
ACTIVE and INACTIVE.
The system clock (after division by two, if active)
must be. at least 16X the Tx or Rx baud rate (the
faster of the two).

Tcy

ClK Period

108

TClCH

ClKlowTime

TCHCl

ClK High Time

250

TCH1CH2 ClK Rise Time

(1)

TCl2Cl1

(1)

ClK Fall Time

NOTES:
1. Rise/fall times are measured between 0.8 and 2.0V.
2. Tcy in ACTIVE divide by two'option is TWICE the input
clock period.

RESET SPECIFICATION
Symbol

Parameter

Min

TRSHl

Reset Width-ClK/X1 Configured to ClK

8Tcy

(1)

.6Tcy

(2)

TIlRSl

RTS/OTR lOW Setup to Reset Inactive

TRSlTX

RTS/OTR low Hold after Reset Inactive

RESET
Dffi/R~

-------1=

TRSHL

Max

Notes

Tcy - 20

(2)

~----.-'- - - - - -

~TTLRSL==:t.--TRSLTX.. -+_________

________________________

___________________

290137-18

NOTES:
1. In case of ClK/Xl configured as Xl, additional time is required to guarantee crystal oscillator wake-up.
2. RTS/DTR are internally driven HIGH during RESET active time. The pin should be either left OPEN or externally
driven lOW during RESET according to the required configuration of the system clock. These parameters specify the
timing requirements on these pins, in case they are externally driven lOW during RESET. The maximum spec on
TRSlTX requires that the RTS/DTR pins not be forced later than TRSlTX maximum.

2-38

inter

82050

READ CYCLE SPECIFICATIONS
Symbol

Parameter

Min

TRLRH

RD Active Width

TAVRL

Address/CS Setup Time to RD Active

TRHAX

Address/CS Hold Time after RD Inactive

TRLDV

Data Out Valid after RD Active

TCIAD

Command Inactive to Active Delay

TRHDZ

Data Out Float Delay after RD Inactive

Max

Notes

2Tcy + 65

(1 )

2Tcy+65

(2)

Tcy + 15

NOTES:
1. C1 = 20 pF to 100 pF.
2. Command refers to either Read or Write signals.

A2-0

VALID

D7-0------------(:~~~---------------------------------290137-19

WRITE CYCLE SPECIFICATION
Symbol

, Parameter

Min

TWLWH

WR Active Width

TAVWL

Address CS Setup Time to WR Active

TWHAX

Address and CS Hold Time after WR

TDVWH

Data in Setup Time to WR Inactive

TWHDX

Data in Hold Time after WR Inactive

~lWLWH

A2-0

D7-0

TAVWL r-

Notes

2Tcy + 15

__ ~TCIAD __
-- lWHAX.r-_

VALID
TDVWH

Max

VALID

lWHDX
VALID
.... TCIAD.:1

'\
290137-20

2·39

82510
ASYNCHRONOUS SERIAL CONTROLLER

•
•
•
•
•
•
•
•

Operation
• -Asynchronous
5· to 9·Bit Character Format
- Baud Rate DC to 288k
- Complete Error Detection

•
•
•
•

Multiple Sampling Windows
Two, Independent, Four·Byte Transmit
and Receive FIFOs with Programmable
Threshold
Two, 16·Bit Baud Rate Generators/
Timers
System Clock Options
- On·Chip Crystal Oscillator
- External Clocks, Low/High Speed

MCS·51 9·Bit Protocol Support
IBM PC AT' (INS 8250A/16450®)
Software Compatible
Control Character Recognition
CHMOS III with Power Down Mode
Interrupts Maskable at Two Levels ,
Auto Echo and Loopback Modes
Seven I/O Pins, Dedicated and General
Purpose
28·Lead DIP and PLCC Packages
(See Packaging Spec., Order #:.231369)

The Intel CHMOS 82510 is designed to increase system efficiency in asynchronous environments such as
modems or serial ports-including expanding performance areas: MCS-51 9-bit format and high speed async.
The functional support provided in the 82510 is unparalleled-two baud rate generators/timers provide independent data rates or protocol timeouts; a crystal oscillator and smart modem I/O simplify system logic. New
features-dual FIFOs and Control Character Recognition (CCR)-dramatically reduce CPU interrupts and
increase software efficiency. The 82510's software versatility allows emulation of the INS8250Al16450 for
IBM PC AT' compatibility or a high-performance mode, configured by 35 control registers. All interrupts are
maskable at two levels. The multipersonality I/O pins are configurable as desired. A DPLL and multiple
sampling of serial data improve data reliability for high-speed, asynchronous communication. The compact 28pin 82510 is fabricated with CHMOS III technology and includes a software powerdown option. -

VSS A(2-0) Vcc

0(7-0)
INT

RD
WR

:: r-

-- r+

cs RESET

SERIAL MODULE

INT I

TX
FIFO

--+

TX
MACHINE

TXD

RX
FIFO

RX
MACHINE

l+- f- I- RXD

BUS
INTERFACE
UNIT

+--+

T-'RT~ll!X

'fMTs

TT
Jx

INT
'2

INTE~ BUS

I
I

TIMING
BLOCK
(BRGS, SYS CLOCK)

MODEM
INTERFACE
MODULE

lX
RXC

lX
TXC

t -I:=+- -f!
- r+

I- r-r+
+-

ClK/Xl
OUT2/X2
R1/SClK

!5SR/TA/OUTO
DCD/IClK/OUT1

D'm/TB
RTS
CfS
290116-1

Figure 1. Block Diagram
'IBM and PC AT are trademarks of International Business Machines.

2-40

October 1989
Order Number: 290116-004

82510

D4
4

D2
D'
DO

INT

82510

TXD
vss
oUTz/XZ

ClK/X'
RiISClK
DS"/TA/oUTO

1 28 27 26

AZ
AO
8

ClK/X'
"
DS_/TA/oUTO

DCD/lClK/OUT'

RESET

RTS
ill

om/TS

290116-3

290116-2

Figure 2. PLCC Pinout

Figure 3. DIP Pinout

82510 PINOUT DEFINITION
Symbol

Pin
No.

Type

Name and Description

RESET

RESET: A high on this input pin resets the 82510 to the Default Wake-up mode.

CHIP SELECT: A low on this input pin enables the 82510 and allows read or
write operations.

A2-AO

2422

ADDRESS PINS: These inputs interface with three bits of the System Address
Bus to select one of the internal registers for read or write.

07-00

4"
25

I/O

READ: A low on this input pin allows the CPU to read Data or Status bytes from
the 82510.

WRITE: A low on this input allows the CPU to write Data or Control bytes to the
82510.

INT

INTERRUPT: A high on this output pin signals an interrupt request to the CPU.
The CPU may determine the particular source and cause of the interrupt by
reading the 82510 Status registers.

ClK/X1

MULTIFUNCTION: This input pin serves as a source for the internal system
clock. The clock may be asynchronous to the serial clocks and to the processor
clock. This pin may be used in one of two modes: ClK - in this mode an
externally generated TTL compatible clock should be used to drive this input pin;
X1 - in this mode the clock is internally generated by an on-chip crystal
oscillator. This mode requires a crystal to be connected between this pin (X1)
and the X2 pin. (See System Clock Generation.)

OUT2/X2

MULTIFUNCTION: This is a dual function pin which may be configured to one of
the following functions: OUT2 - a general purpose output pin controlled by the
CPU, only available when ClK/X1 pin is driven by an externally generated clock;
X2 - this pin serves as an output pin for the crystal oscillator. Note: The
configuration of the pin is done only during hardware reset. For more details
refer to the System Clock Generation.

TXD

TRANSMIT DATA: Serial data is transmitted via this output pin starting at the
least Significant bit.

DATA BUS: Bi-directional, three state, eight-bit Data Bus. These pins allow
transfer of bytes between the CPU and the 82510.

'P,ns 28-25 and PinS 4-1.

2-41

82510

82510 PINOUT DEFINITION (Continued)
Pin
No.

Type

RXD

'13

RECEIVE DATA: Serial data is received on this input pin starting at the least
Significant bit.
'

RI/SClK

MULTIFUNCTION: This is a dual function pin which can be configured to one of
the following functions. RI - Ring Indicator - Input, active low. This is a general
purpose input pin accessible by the CPU. SClK - This input pin may serve as a
source for the internal serial clock(s), RxClk and lor TxClk. See- Figure 12, SRG
sources and outputs.

DTR/TS

MULTIFUNCTION: This is a dual function pin which may be configured toone of
the following functions. PTR - Data Terminal Ready. Output, active low. This is a
general purpose output pin controlled by the CPU. TS - This pin outputs the
SRGS output signal when configured as either a clock generator or as a timer.
When SRGS is configured as a timer this pin outputs a "timer expired pulse."
When SRGS is configured as a clock generator it outputs the SRGS output

Symbol

Name and Description

clock

DSR/TAI

1/0

CTS

DCD/IClKI
OUT1

,12

1/0

Vee
Vss

Vee: Device power supply.

Vss: Ground.

OUTO

RTS

MULTIFUNCTION: This is a multifunction pin which may be configured to one of
the following functions. DSR - Data Set Ready. Input, active low. This is a
general purpose input pin accessible by the CPU. TA - This pin is similar in
function to pin TS except it outputs the signals from SRGA instead of SRGS.
OUTO - Output pin. This is a general purpose output pin controlled by the CPU.
REQUEST TO SEND: Output pin,.active low. This is a general purpose output
piri controlled by the CPU. In addition, in automatic transmission mode this pin,
along with CTS, controls the transmission of data. (See Transmit modes for
further detail.) During hardware reset this pin is an input. It is used to determine
the System Clock Mode. (See System Clock Generation for further detaiL)
.
CLEAR TO SEND: Input pin, active low. In automatic transmission mode it
directly controls the Transmit Machine. (See transmission mode for further
details.) This pin can be used as a General Purpose Input.
MULTIFUNCTION: This is a multifunction pin which may be configured to one of
the following functions. DCD - Data Carrier petected. Input pin, active low. This.
is a general purpose input pin accessible by the CPU. IClK - This pin is the
output of the internal system clock. OUT1- General purpose output pin.
Controlled by the CPU.

'Table 1. Multifunction Pins. '
Pin #

1/0

Timing

Modem

*OUT2

*ClK/X1

. 10

SClK

°RI

OUTO

*DSR

OUT1

IClK

°DCD

"Default

2-42

·CTS

"DTR

*RTS

inter

82510

Its register set can be used in 8250Al16450 compatibility or High Performance modes. The 8250Al
16450 mode is the default wake-up mode in which
only the 8250A/16450 compatible registers are accessible. The remaining registers are default configured to support 8250A/ 16450 emulation.

GENERAL DESCRIPTION
The 82510 can be functionally divided into seven
major blocks (See Fig 1): Bus Interface Unit, Timing
Unit, Modem Module, Tx FIFO, Rx FIFO, Tx Machine, and Rx Machine. Six of these blocks (all except Bus Interface Unit) can generate block interrupts. Three of these blocks can generate secondlevel interrupts which reflect errors/ status within the
block (Receive Machine, Timing Unit, and the Modem Module).

Software Interface
HIGH PERFORMANCE MODE
ALL BANKS FUNCTION

8250 MODE

The Bus interface unit allows the 82510 to interface
with the rest of the system. It controls access to
device registers as well as generation of interrupts
to the external world. The FIFOs buffer the CPU
from the Serial Machines and reduce the interrupt
overhead normally required for serial operations.
The threshold (level of occupancy in the FIFO which
will generate an interrupt) is programmable for each
FIFO. The timing unit controls generation of the system clock through either its on-chip crystal oscillator,
or an externally generated clock. It also provides two
Baud Rate Generators/Timers with various options
and modes to support serial communication.
290116-4

FUNCTIONAL DESCRIPTION

Figure 4. 82510 Register Architecture

CPU Interface

The 82510 is configured and controlled through its
35 registers which are divided into four banks. Only
one bank is accessible at anyone time. The bank
switching is done by changing the contents of the
bank pointer (GIR/BANK-BANKO, BANK1). The
banks are logically grouped into 8250Al16450 compatible (0), General Work Bank (1), General Configuration (2), and Modem Configuration (3). The
8250A/16450 compatible bank (Bank 0) is the default bank upon power up.

The 82510 has a simple demultiplexed Bus Interface, which consists of a bidirectional three-state
eight-bit, data bus and a three-bit address bus. An
Interrupt pin along with the Read, Write and Chip
Select are the remaining signals used to interface
with the CPU. The three address lines along with the
Bank Pointer register are used to select the registers. The 82510 is designed to interface to all Intel
microprocessor and microcontroller families. Like
most other I/O based peripherals it is programmed
through its registers to support a variety of functions.

The 82510 registers can be categorized under the
following:

Table 2. 82510 Register/Block Functions
FIFO
MODEM
RX
TX
TIMER
DEVICE
8250

Status
FLR
MSR

Enable

Configuration

Command

Data

FMD
PMD

MCR

RST,RXF

RIE

MIE

RCM
TCM

TXD,TXF

TMCR

BBL, BBH
BAL, BAH

ICM

MCR

TXD,RXD
BAL, BAH

LSR

TMST

TMIE

GSR, GIR
LSR, MSR, GIR

GER

CLCF,
BACF,BBCF
IMD

GER

LCR, MCR

2-43

RMD
TMD

RXD,RXF

82510

8250 Compatibility
Upon power up or reset, the 82510 comes up in the default wake up mode. The 8250Al16450 compatible
bank, bank zero, is the accessible bank and all the other registers are configured via their default values to
support this mode. An 18.432 MHz crystal frequency is necessary.
.

Table 3. 8250A/16450 Compatible Registers
82510 Registers
(BankO)

8250A Registers

Read

Write

Read

Write

RxD

TxD

RBR

THR

01 (DLAB

= 0)
= 1)
01 (DLAB = 1)

GER

IER

00 (DLAB

BAL

DLL

BAH

DLM

GIR/BANK

BANK

IIR

Address
00 (DLAB

02
03

LCR

MCR

LSR

MSR

ACRO

SCR

Table 4 Default Wake-Up Mode

ACR1

OOH

RxF

TxD

RIE

1EH

TxF

BAL

02H

RMD

OOH

TMST

BAH

RxD

30H

OOH

CLCF

OOH

TMCR

GER

OOH

BACF

04H

FLR

OOH

GIR/BANK

01H

BBCF

84H

RCM

LCR

OOH

PMD

FCH

TCM

MCR

OO.H

MIE

OFH

GSR

12H

LSR

60H

TMIE

OOH

ICM

MSR

OOH

BBL

05H

FMD

OOH

ACRO

OOH

BBH

OOH

TMD

OOH

RST

OOH

IMD

OCH

2-44

intJ

82510

(HIGHEST PRIORITY)
TIMER

£
Tc

TIMER A EXPIRED
TIMER B EXPIRED

TX CONDITION

TX MACHINE IDLE
RX PARITY ERROR
OVERRUN ERROR
BREAK DETECTED
BREAK TERMINATED
ADDRESS/CONTROL
CHAR. RECEIVED
ADDRESS/CONTROL
CHAR. MATCH

RX CONDITION
INTERRUPT

FRAMING ERROR
RX FIFO - - - - RX FIFO LEVEL ABOVE
THRESHOLD
TX FIFO - - - - TX FIFO LEVEL EQUAL
TO OR BELOW THRESHOLD

MODEM
(LOWEST PRIORITY)

-E'

DCD CHANGE STATE
RI CHANGE STATE
DSR CHANGE STATE
CTS CHANGE STATE

290116-5

Figure 5. Interrupt Structure

The CPU must issue an explicit Interrupt Acknowledge command via the Interrupt Acknowledge bit of
the Internal Command register. As a result the INT
pin is forced low for two clocks and then updated.

Interrupts
There are two levels of interrupt/status reporting
within the 82510. The first level is the block level
interrupts such as RX FIFO, Tx FIFO, Rx Machine,
Tx Machine, Timing unit, and Modem Module. The
status of these blocks is reported in the General
Status and General Interrupt Registers. The second
level is the various sources within each block; only
three of the blocks generate second level interrupts
(Rx Machine, Timing Unit; and Modem Module). Interrupt requests are maskable at both the block level
and at the individual source level within the module.
If more than one unmasked block requests interrupt
service an on-chip interrupt controller will resolve
contention on a priority basis (each block has a fixed
priority). An interrupt request from a particular block
is activated if one of the unmasked status bits within
the status register for the block is set. A CPU service
operation, e.g., reading the appropriate status register, will reset the status bits.

2. Automatic Acknowledge
As opposed to the Manual Acknowledge mode,
when the CPU must issue an explicit interrupt acknowledge command, an interrupt service operation
is considered as an automatic acknowledgment.
This ,forces .the INT pin low for two clock cycles.
After two cycles the INT pin is updated, i.e., if there
is still an active non-masked interrupt request the
INT pin is set HIGH.
INTERRUPT SERVICE

A service operation is an operation performed by the
CPU, which causes the source of the 82510 interrupt
to be reset (it will reset the particular status bit causing the interrupt). An interrupt request within the
82510 will not reset until the interrupt source has
been serviced. Each source can be serviced in two
or three different ways; one general way is to disable
the particular status bit causing the interrupt, via the
corresponding block enable register. Setting the appropriate bit of the enable register to zero will mask
off the corresponding bit in the status register, thus
causing an edge on the input line to the interrupt
logic. The same effect can be achieved by masking

ACKNOWLEDGE MODES

The interrupt logic will assert the INT pin when an
interrupt is coded into the General Interrupt register.
The INT pin is forced low upon acknowledgment.
The 82510 has two modes of interrupt acknowledgment:
1. Manual Acknowledge

2-45

intJ

82510

off the particular block interrupt request in GSR via
the General Enable Register. Another method,
which is applicable to all sources, is to issue the
Status Clear command from the Internal Command
Register. The detailed service requirements for each
source are given below:

The 82510 has an on-chip oscillator to generate its
system clock. The oscillator will take the inputs from
a crystal attached to the X1 and X2 pins. This mode
is configured via a hardware strapping option on
ATS.

Table 5. Service Procedures
Interrupt Status Bits Interrupt
Source & Registers Masking

Specific
Service

RESET

TMST (1-0) TMIE (1-0) ReadTMST
GSR (5)
GER (5)

Timers

Tx
GSA (4)
Machine LSA (6)

GEA (4)

Write Character
totX FIFO

LSA (4-1)
Ax
Machine RST (7-1)
GSA (2)

AlE (7-1)
GEA (2)

Read ASTor
LSR Write 0
to bit in
AST/LSA

Ax FIFO AST/LSA (0) GEA (0)
GSA (0)

Write 0 to
LSA/AST
Bit zero.
Aead Character

Tx FIFO LSA (5)
GSA (1)

GEA (1)

Write to FIFO
Aead GIA(1)

MIE.(3-0)
GEA (3)

Aead MSA
write 0 into the
appropriate bits
of MSA (3-0).

Modem

MSA (3-0)
GSA (3)

><>-......-IRTS
290116-7

Figure 7. Strapping Option
During hardware reset the ATS pin is an input; it is
weakly pulled high from within and then checked. If it
is driven low externally then the 82510 is configured
for the Crystal Oscillator; otherwise an external
clock is expected.
EXTERNALLY GENERATED SYSTEM CLOCK

I." I•

'1''''.
OUT2

I
290116-8

NOTE:
1. Only if pending interrupt is Tx FIFO.

Figure 8. External Clock
This is the default configuration. Under normal conditions the system clock is divided by two; however,
the user may disable divide by two via a hardware
strapping option on the DTR pin. The Hardware
strapping option is similar to the one used on the
ATS pin. It is forbidden to strap both DTA and ATS.

System Clock Generation
The 82510 has two modes of System Clock Operation. It can accept an externally generated clock, or
it can use a crystal to internally generate its system
clock.

Transmit

CRYSTAL OSCILLATOR

The two major blocks involved in transmission are
the Transt:nit FIFO and the Transmit Machine. The
Tx FIFO acts as a buffer between the CPU and the
Tx' Machine. Whenever a data character is written to
the Transmit Data register, it, along with the Transmit Flags (if applicable), is loaded into the Tx FIFO.

Parallel Resonant Crystal

Xl.

D~
r
c::I.
r F I .

290116-6

Figure 6. Crystal Oscillator

2-46

82510

TX FIFO

TRANSMIT CLOCKS
TXF REGISTER

There are two modes of transmission clocking, 1X
and 16X. In the 1X mode the transmitted data is
synchronous to the transmit clock as supplied by the
SCLK pin. In this mode stop-bit length is restricted to
one or two bits only. In the 16X mode the data is not
required to be synchronous to the clock. (Note: The
Tx clock can be generated by the BRGs or from the
SCLK pin.)

TXD REGISTER

DATA

FLAGS

POINTER

t--------ilr--------tl.-

MODEM HANDSHAKING
The transmitter has three modes of handshaking.

POINTER

[
,

Manual Mode-In this mode the CTS and RTS pins
are not used by the Tx Machine (transmission is
started regardless of the CTS state, and RTS is not
forced low). The CPU may manage the handshake
itself, by accessing the CTS and RTS signals
through the MODEM CONTROL and MODEM
STATUS registers.

r - ,- - - - - - - - ,

CHARACTER fRAME

TXD

~--------------~290116-9
Figure 9. Tx FIFO

The Tx FIFO can hold up to four, eleven-bit characters (nine-bits data, parity, and address flag). It has
separate read and write mechanisms. The read and
write pointers are incremented after every operation
to allow data transfer to occur in a First In First Out
fashion. The Tx FIFO will generate a maskable interrupt when the level in the FIFO is below, or equal to,
the Threshold. The threshold is user programmable.

Semi-Automatic Mode-In this mode the RTS pin
is activated whenever the transmitter is enabled.
The CTS pin's state controls transmission. Transmission is enabled only if CTS is active. If CTS becomes inactive during transmission, the Tx Machine
will complete transmission of the current character
and then go to the inactive state until CTS becomes
active again.

For example, if the threshold equals two, and the
number of characters in the Tx FIFO decreases from
three to two, the FIFO will generate an interrupt. The
threshold should be selected with regard to the system's interrupt service latency.

Automatic Mode-This mode is similar to the semiautomatic mode, except that RTS will be activated
as long as the transmitter is enabled and there are
more characters to transmit. The CPU need only fill
the FIFO, the handshake is done by the Tx Machine.
When both the shift register and the FIFO are empty
RTS automatically goes inactive. (Note: The RTS pin
can be forced to the active state by the CPU, regardless of the handshaking mode, via the MODEM
CONTROL register.)

NOTE:
There is a one character transmission delay between FIFO empty and Transmitter Idle, so a
threshold of zero may be selected without getting
an underrun condition. Also if more than four characters are written to the FIFO an overrun will occur
and the extra character will not be written to the Tx
FIFO. This error will not be reported to the CPU.

Receive
The 82510 reception mechanism involves two major
blocks; the Rx Machine and the Rx FIFO. The Rx
Machine will assemble the incoming character and
its associated flags and then LOAD them on to the
Rx FIFO. The top of the FIFO may be read by reading the Receive Data register and the Receive Flags
Register. The receive operation can be done in two
modes. In the normal mode the characters are received in the standard Asynchronous format and
only control characters are recognized. In the ulan
mode, the nine bit protocol of the MCS-51 family is
supported and the ulan Address characters, rather
than Control Characters are recognized.

TX MACHINE
The Tx Machine reads characters from the Tx FIFO,
serializes the bits, and transmits them over the TXD
pin according to the timing signals provided for
transmission. It will also generate parity, transmit
break (upon CPU request), and manage the modem
handshaking signals (CTS and RTS) if configured
so. The Tx machine can be enabled or disabled
through the Transmit Command register or CTS. If
the transmitter is disabled in the middle of a character transmission the transmission will continue until
the end of the character; only then will it enter the
disable state.

2-47

inter

82510

'Manual Mode-In this mode the Rx Machine does
not control the FIFO automatically; however, the
user may UNLOCK/LOCK the FIFO by using the
RECEIVE COMMAND r~gister.

RX FIFO

RXD REGISTER

RXF REGISTER

DATA

FLAGS

ro~----II ;r .
I
RXD

C_H_AR_A_CT_ER_FR_A_t.tE_ _....I

LI_ _ _

290116-10

Figure 10; Rx FIFO
The Rx FIFO is very similar in structure and basic
operation to the Tx FIFO. It will generate a maskable
interrupt when the FIFO level is above the threshold.
The Rx FIFO can also be configured to operate as a
one-byte buffer. This mode is used for 8250 compatible software drivers. An overrun will occur when the
. FIFO is full and the Rx Machine has a new character
for the FIFO. In this situation the oldest character is
discarded and the new character is loaded from the
Rx Machine. An Overrun error bit will also be set in
the RECEIVE STATUS and LINE STATUS registers.
The user has the option to disable the loading of
incoming characters on to the Rx FIFO by using the
UNLOCK/LOCK FIFO commands. (See RECEIVE
COMMAND register.) When the Rx FIFO is locked, it
will ignore load requests from the Rx Machine, and
thus the received characters will not be loaded into
the FIFO and maybe lost (if another character is
received). These two commands are useful when
the CPU is not willing to receive characters, or is
waiting for specific Controll Address characters. In
uLAN mode there are three options of address recognition, each of these options varies in the amount
of CPU offload, and degree of FIFO control through
OPEN/LOCK FIFO commands.

RX MACHINE
The RX Machine has two modes of clocking the incoming data-16X or 1X. In 16X synchronization is
done internally; in the 1X mode the data must be
synchronous to the SCLK pin input. The Rx Machine
synchronizes the data, passes it through a digital filter to filter out the spikes, and then uses the voting
counter to generate the data bit (multiple sampling
of input RXD). Bit polarity decisions are made on the
basis of majority voting; i.e., if the majority of the
samples are "1" the result is a "1" bit. If all samples
are not in agreement then the bit is also reported as
a noisy bit in the RECEIVE FLAGS register. The
sampling window is programmable for either 3/16 or
7/16 samples. The 3/16 mode is useful for high frequency transmissions, or when serious RC delays
are expected on the channel. The 7/16 is best suited for noisy media. The Rx machine also has a
DPLL to overcome frequency shift problems; however, using it in a very noisy environment may increase
the error, so the user can disable the DPLL via the
Receive Mode register. The Rx Machine will generate the parity and the address marker as well as'any
framing error indications.
Start Bit Detection-The falling edge of the Start
bit resets the DPLL counter and the Rx Machine
starts· sampling the input line (the number of samples is determined by the configuration of the sampling window mode). The Start bit verification can be
done through either a majority voting system or an
absolute voting system. The absolute voting requires
that all the samples be in agreement. If one of the
samples does not agree then a false Start bit is determined and the Rx Machine returns to the Start Bit
search Mode. Once a Start bit is detected the Rx
Machine will use the majority voting sampling window to receive the data bits.
Break Detection-If the input is low for the entire
character frame including the stop Bit, then the Rx
Machine will set Break Detected as well as Framing
Error in the RECEIVE STATUS and LINE STATUS
registers. It will push a NULL character onto the Rx
FIFO with a framing-error and Break flag (As part of
the Receive Flags). The Rx Machine then enters the
Idle state. When .it sees a mark it will set Break Terminated in RECEIVE STATUS and LINE STATUS
registers and resume normal operation.

Automatic Mode-In this mode the Rx Machine will
open the FIFO whenever an Address Match occurs;
it will LOCK the FIFO if an address mismatch occurs.
Semi-Automatic Mode-In this mode the Rx Machine will open the FIFO whenever an address character is received. It will not lock the FIFO if the Address does not match. The user is responsible for
locking the Rx FIFO.

2-48

82510

4 BIT DPLL
COUN TER

I I I

f// C0 ~

NARROW WINDOW

WIDE WINDOW

3 OF" 16

~ V~ V~ ~ 0 ~ v~

-- t>

70F"16

:::;:,

DATA INPUT LINE

I I r

290116-11

Figure 11. Sampling Windows
SOFTWARE
CONTROLLED

Control Characters-The Rx machine can gener·
ate a maskable interrupt upon reception of standard
ASCII or EBCDIC control characters, or an Address
marker is received in the uLAN mode. The Rx mao
chine can also generate a maskable interrupt upon a
match with programmed characters in the Address/
Control Character 0 or Address/Control Character 1
registers.

GATE
SYSCLK
XTAL CLK
SCLK

Table 6. Control Character Recognition

STANDARD SET
• ASCII:
OOOX XXXX

SCLK
SYSCLK
XTALCLK
BRGA
OUTPUT

+ 01111111

•

RxCLK
TxCLK
BRGB
SOURCE

OUT

RxCLK
TxCLK

-A-

GATE
SOURCE
-B,

Figure 12. BRG Sources and Outputs

(ASCII DEL)
(00 - 1FH

OUT

SOFTWARE
CONTROLLED

CONTROL CHARACTER RECOGNITION
Al

SOURCE

+ 7 FH)

BAUD RATE GENERATION

EBCDIC: OOXX XXXX
(00 -3FH)

The Baud Rate is generated by dividing the source
clock with the divisor count. The'count is loaded
from the divisor count registers into a count down
register. A 50% duty cycle is generated by counting
down in steps of two. When the count is down to 2
the entire count is reloaded and the output clock is
toggled. Optionally the two BAGs may be cascaded
to provide a larger divisor. Note that this is the default configuration and used for 8250Al16450 emulation.

User Programmed
• ACRO, ACR1 XXXX XXXX
REGISTERS

Baud-Rate Generators/Timers

fo = fi".IDivisor

The 82510 has two-on-chip, 16-bit baud-rate generators. Each BRG can also be configured as a Timer,
and is completely independent of the other. This can
be used when the Transmit and Receive baud rates
are different. The mode, the output, and the source
of each BRG is configurable, and can also be optionally output to external devices via the T A, TB
pins (see Fig. 12. BRG Sources and Outputs).

where fin is the input clock frequency and Divisor is
the count loaded into the appropriate count registers. System clock frequencies can be selected
(4 9.216 MHz) to eliminate baud rate error for
high baud rates.

2-49

82510

delay between the trigger and the terminal count is
given by the following equation:

Table 7. Standard Baud Rates
%

16x Divisor

Bit Rate

Erro~

Delay = Count. (System Clock Period)

.007%

To start counting, the Timer has to be triggered via
the Start Timer Command. To restart the Timer after
terminal count or while counting, the software has to
issue the trigger command again. While counting the
Timer can be enabled or disabled by using a software controlled Gate. It is also possible to output a
pulse generated upon terminal count through the TA
or TB pins.

110

5236 (1474h)

300

1,920 (780h)

1200

480 (1 EOh)

2400

240 (FOh)

9600

60 (3Ch)

19,200

30 (1 Eh)

38,400

15 (OFh)

56,000

10 (OAh)

2.8%

288,000

2 (02h)

Source ClK

Internal Sys. Clk
= 18.432 MHz/2 (Crystal)
= 9.216 MHz (External 1X clock)
=

NOTE:
Internal system clock is % crystal frequency or
clock frequency when using .,. 2 clock option.

% external

The BRG counts down in increments of two and
then is divided by two to generate a 50% duty cycle;
however, for odd divisors it will count down the first
time by 6ne. All subsequent countdowns will then
continue in steps of two. In those cases the duty
cycle is no longer exactly 50%. The deviation isgiven by the following equation:

In 1X clock mode the only clock source available is
the SCLK pin. The serial machines (both Tx Machine
and Rx Machine) can independently use one of two
clock modes, either 1X or 16X.Also no configuration
changes are allowed during operation as each write
in the BRG configuration registers causes a reset
signal to be sent to the BRG logic. The mode or
source clocks may be changed only after a Hardware or Software reset. The Divisor (or count, depending upon the mode) may be updated during operation unless the particular BRG machine is being
used as a clock source for one of the serial machines, and the particular serial machine is in operation at the time. Loading the count registers with "0"
is forbidden in all cases, and loading it with a "1" is
forbidden in the Timer Mode only.
SERIAL DIAGNOSTICS
The 82510 supports two modes of Loopback operation, Local Loopback and Remote Loopback as well
as an Echo mode for diagnostics and improved
throughput.

deviation = 1/(2. divisor)

The BRG can operate with any divisor between 1
and 65,535; however, for divisors.between 1 and 3
the duty cycle is as follows:

LOCAL LOOPBACK

Table 8 Duty Cycles
Divisor

Duty Cycle

33%

50%

Same as Source

FORBIDDEN

-+~~!..~PIN

~~).~PIN
290116-12

Figure 13. Local Loopback

Timer Mode

The Tx Machine output and Rx Machine input are
shorted internally, TXD pin output is held at Mark.
This feature allows simulation of Transmission/Reception of characters and checks the Tx FIFO, Tx
Machine, Rx Machine, and Rx FIFO along with the
software without any external side effects. The modem outputs OUT1, OUT2, DTR and RTS are internally shorted to RI, DCD, DSR and CTS respectively.
OUTO is held at a mark state.

Each of the 82510 BRGs can be used as Timers.
The Timer is used to generate time delays by counting the internal system clock. When enabled the
Timer uses the count from the Divisor/Count registers to count down to 1. Upon terminal count a
maskable Timer Expired interrupt is generated. The

2-50

intJ

82510

The 82510 powers down when the power down
command is issued via the Internal Command Register (ICM). There are two modes of power down,
Sleep and Idle.

REMOTE LOOPBACK

~PIN

r-'" '"

=
r::::l
1X!Zd~~~

In Sleep mode, even the system clock of the 82510
is shut down. The system clock source of the 82510
can either be the Crystal Oscillator or an external
clock source. If the Crystal Oscillator is being used
and the power down command is issued, then the
82510 will automatically enter the Sleep mode. If an
external clock is being used, then the user must disable the external. clock in addition to issuing the
Power Down command, to enter the Sleep mode.
The benefit of this mode is the increased savings in
power consumption (typical power consumption in
the Sleep mode is in the ranges of 100s of microAmps). However, upon wake up, the user must
reprogram the device. To exit this mode the user
can either issue a Hardware reset, or read the FIFO
Level Register (FLR) and then issue a software reset. In either case the contents of the 82510 registers are not preserved and the device must be reprogrammed prior to operation. If the Crystal Oscillator
is being used then the user must allow enough time
for the oscillator to wake up before issuing the software reset.

290116-13

Figure 14. Remote Loopback

The TXD pin and RXD pin are shorted internally (the
data is not sent on to the RX Machine). This feature
allows the user to check the communications chan·
nel as well as the Tx and Rx pin circuits not checked
in the Local Loopback mode.
AUTO ECHO

=
XD

tV®

8-+~PIN
r::::::1

RXD PIN

~.-.~

RXD

290116-14

The 82510 is in the idle mode when the Power Down
command is issued and the system clock is still running (i. e. the system· clock is generated externally
and not disabled by the user). In this mode the contents of all registers and memory cells are preserved, however, the power consumption in this
mode is greater than in the Sleep mode. Reading
FLR will take the 82510 out of this mode.

Figure 15. Auto Echo

In Echo Mode the received characters are automatically transmitted back. When the characters are
read from the Rx FIFO they are automatically
pushed back onto the Tx FIFO (the flags are also
included). The Rx Machine baud rate must be equal
to, or less than, the Tx Machine baud rate or some
of the characters may be lost. The user has an option of preventing echo of special characters; Control Characters and characters with Errors.

NOTE:
The data read from FLR when exiting Power Down
is invalid and should be ignored.

Power Down.Mode
The 82510 has a "power down" mode to reduce
power consumption when the device is not in use.

2-51

intJ

82510

DETAILED REGISTER DESCRIPTION
Table 9. Register Map
Bank

o (NAS)
8250Al16450

Read
Register

Address

o (OlAB

= 0)
1 (OlAB = 0)
o (OlAB = 1)
1 (OlAB = 1)
2
3

4
5

6
7
1 (WORK)

0
1
2
3

4
5

6
7
2 (GENERAL CONF)

4
5

6
7
3 (MODEM CONF)

RXO
GER
BAl
BAH
GIR/BANK
lCR
MCR
lSR
MSR
ACRO

TXO
GER
BAl
BAH
BANK
lCR
MCR
lSR
MSR
ACRO

RXO
RXF
GIR/BANK
TMST
FlR
RST
MSR
GSR

TXO
TXF
BANK
TMCR
MCRRCM
TCM
ICM

0
1
2
3

o (OLAB

= 0)
1 (OLAB = 0)
o (OLAB = 1)
1 (OLAB = 1)
2
3

4
5

6
7

Write
Register

FMO
GIR/BANK
TMO
IMO
ACR1
RIE
RMO

FMO
BANK
TMO
IMO
ACR1
RIE
RMO

ClCF
BACF
BBl
BBH
GIR/BANK
BBCF
PMO
MIE
TMIE

ClCF
BACF
BBl
BBH
BANK
BBCF
PMO
MIE
TMIE

(1) ACRO is used in INS8250 as a Scratch-Pad Register
(2) Olf,B = lCR Bit #7
The 82510 has thirty-five registers which are divided into four banks of register banks. Only one bank is
accessible at anyone time. The bank is selected through the BANK1-0 bits in the GIR/BANK register. The
individual registers within a bank are selected by the three address lines (A2-0). The 82510 registers can be
grouped into the following categories.

2-52

82510

BANK ZERO 8250Al1645O-COMPATIBLE BANK
Register

Address Defaul

xD (33)

Tx Data
bit7

Tx Data Tx Data
bitS
bit 5

Tx Data
bit 4

Tx Data
bit3

Tx Data
bit 2

Tx Data
bit 1

Tx Data
bit 0

RxD (35)

Rx Data
bit7

Rx Data Rx Data
bit S
bit 5

Rx Data
bit4

Rx Data
bit 3

Rx Data
bit2

RxData
bit 1

Rx Data
bitO

BAL (11)

BRGA LSB Divide Count (DLAB = 1)

02H

BAH (12)

BRGA MSB Divide Count (DLAB = 1)

OOH

GER (16)

GIR/BANK
(21)

LCR(2)

Tx Machine Modem
Interrupt
Interrupt
Enable
Enable

BANK BANK
Pointer Pointer
bit 1
bitO

DLAB
Set
Divisor
Break
Latch
Access bit

MCR (32)

LSR (22)

TxM
Idle

MSR (27)

Timer
Interrupt
Enable

Parity
Mode
bit2

Parity
Mode
bit 1

Rx Machine
Interrupt
Enable

TxFIFO
Interrupt
Enable

RxFIFO
Interrupt
Enable

OOH

Active
Block Int
bit 2

Active
Block Int
bit 1

Active
Block Int
bit 0

Interrupt
Pending

01H

Parity
Mode
bit 0

Stop bit
Length
bit 0

Character
Length
bit 1

Character
Length
bit 0

OOH

OUTO
Loopback OUT2
OUT 1
Complement Control bit Complement Complement

RTS
DTR
Complement Complement

OOH

TxFIFO
Interrupt

Overrun
Error

RxFIFO
Int Req

SOH

State (H -> L) State
Change
Change
in RI
inDSR

State
Change
inCTS

OOH

DCD Input Rllnput DSR Input
Inverted Inverted Inverted

ACRO(5)

Break
Detected

Framing
Error

CTS Input State
Inverted
Change
inDCD

Parity
Error

Address or Control Character Zero

BANK ONE-GENERAL WORK BANK
Register

Address Default

TxD (33)

Tx Data
bit7

Tx Data Tx Data
bits
bit 5

TxData
bit 4

TxData
bit 3

Tx Data
bit 2

Tx Data
bit 1

TxData
bit 0

RxD (35)

Rx Data
bit 7

Rx Data Rx Data
bits
bit 5

Rx Data
bit 4

Rx Data
bit 3

Rx Data
bit 2

Rx Data
bit 1

Rx Data
bit 0

RxF (24)

Rx Char RxChar
Noisy
OK

Rx Char
Parity
Error

Address or
Control
Character

Break
Flag

Rx Char
Framing
Error

Ninth
Data bit
of Rx Char

TxF (34)

Address Software Ninth bit
Marker bit Parity bit of Data Char

GIR/BANK
(21)

TMST(2S)

0
0

0
Active
Block Int
bit 2

0
Active
Block Int
bit 1

BANK
Pointer
bit 1

BANK
Pointer
bit 0

Active
Block Int
bit 0

Interrupt
Pending

01H

Gate B
State

Gate A
State

TimerB
Expired

Timer A
Expired

30H

TMCR (31)

Trigger
GateB

Trigger
Gate A

Start
TimerB

Start
Timer A

MCR (32)

OUTO
Loopback OUT2
OUT1
RTS
DTR
Complement Control bit Complement Complement Complement Complement

OOH

NOTE:
The register number is provided as a reference number for the register description.

2-53

intJ

82510

BANK ONE-GENERAL WORK BANK (Continued)
Register

FLR (25)

Rx FIFO Level

OOH

State
State
State
Change Change Change
inRI
inDSR inCTS

OOH

FlushTx
Machine

FlushTx Tx
FIFO
Enable

TxM
Interrupt

Modem
Interrupt

RxM
TxFIFO RxFIFO
Interrupt Interrupt Interrupt

Software
Reset

Manuallnt
Status
Acknowledge Clear
Command

RST(23) Addressl
Control
Character
Received

Addressl Break
Break
Framing
Control
Terminated Detected Error
Character
Match

Parity
Error

RCM(30) Rx
Enable

Rx
Disable

Open Rx
FIFO

MSR(27) DCD
Rllnput
Complement Inverted
TCM(29)

GSR (20)

ICM(28)

Flush
RxM

Flush
RxFIFO

DSR Input
Inverted

CTS Input State
Inverted Change
inDCD

Lock Rx
FIFO

Timer
Interrupt
0

Address Defal,llt

Tx FIFO Level
Overrun RxFIFO
Error
Interrupt
Requested
<

Tx
Disable

Power
Down
Mode

12H

BANK TWO-GENERAL CONFIGURATION

FMD(4)

GIR/BANK
(21)

BANK
Pointer
bit 1

TMD(3)

Error
Echo
Disable

IMD(1)

Rx FIFO Threshold
BANK
Pointer
bit 0

Control
9-bit
Character
Character
Echo Disable Length
0

Active
Block Int
bit2

Transmit Mode

ACR1 (6)

OOH

Active
Active
Interrupt
Block Int Block Int Pending
bit 1
bit 0

·01H

Software
Parity
Mode

OOH

OCH.

Stop Bit Length

Interrupt
RxFIFO ulan
Acknowledge Depth
Mode
Select
Mode

Address Defal,llt

Tx FIFO Threshold

Loopbackor
Echo Mode
of Operation

Address or Control Character 1

RIE(17)

RMD(7)

Addressl
Control
Character
Recognition
Interrupt
Enable

Addressl
Control
Character
Match
Interrupt
Enable

Break
Terminate
Interrupt
Enable

Break
Detect
Interrupt
Enable

Disable
DPLL

Sampling Start bit
Window Sampling
Mode
Mode

Address/Control
Character Mode

Framing
Error
Interrupt
Enable

OOH

Parity
Error
Interrupt
Enable

Overrun
Error
Interrupt
Enable

1EH

OOH

BANK THREE-MODEM CONFIGURATION
Register

Address

Defal,llt

CLCF(8)

RxClock
Mode

RxClock
Source

TxClock
Mode

TxClock
Source

OOH

BACF(9)

BRGA
Mode

-1

04H

BRGA
Clock
Source

BBL(13)

BRGB LSB Divide Count (DLAB = 1)

05H

BBH (14)

BRGB MSB Divide Count (DLAB = 1)

OOH

2-54

inter

82510

BANK THREE-MODEM CONFIGURATION (Continued)
Register

GIRfBANK
(21)

BANK
Pointer
bit 1

BBCF (10)
PMD (15)

BRGB Clock Source

BANK
Pointer
bit 0
0

3
Active
Block Int
bit 2
0

DCDIICLKf DCDIICLKf DSRfTAf DSRfTAf RIISCLK
aUT1
aUT1
aUTO
Function
aUTO
Direction
Function
Direction Function

MIE (19)

TMIE (18)

Active
Block Int
bit 1

1
Active
Block Int
bitO

Interrupt
Pending

Address Default
2

01H

BRGB
Mode

84H

DTRfTB
Function

FCH

OFH

OOH

DCD State RI State
DSR State CTS State
Change Int Change Int Change Int Change Int
Enable
Enable
Enable
Enable
0

TimerB
Interrupt
Enable

Timer A
Interrupt
Enable

CONFIGURATION
These read/write registers are used to configure the device. They may be read at anytime; however, they may
be written to only when the device is idle. Typically they are written to only once after system power up. They
are set to default values upon Hardware or Software Reset (Default Wake-Up Mode). The default values are
chosen. so as to allow the 82510 to be fully software compatible with the IBM PC Async Adapter (INS 8250Al
16450) when in the default wakeup mode. The 82510 can operate in the High Performance mode by programming the configuration registers as necessary.
.
The configuration options available to the user are listed below.

Table 11. Configuration Options
Interrupt Acknowledge Mode
• Automatic
• Manual
Receive
• Sampling Window Size
• Start Bit Detection Mode
• DPLL Disable/Enable
""LAN (8051)
Address Recognition
• Manual, Semi-Automatic,
Automatic
Diagnostics
• Loopback
• Remote
• Local
• Echo
• Yes/No
• Disable Error Echo
• Disable Control/Address
Char. Echo

FIFO
• RX FIFO Depth
• RX, TX Threshold
Clock Options
• RX, TX Clock Mode
• 1X
• 16X
• .RX, TX Clock Source
• BRGA
• BRGB
• BRGAIB Operation Mode
• Timer
• BRG
• BRGAIB Divide Count
• BRGAIB Source
• Sys Clock
• SCLK Pin
.. BRGA Output (BRGB
Only)

2-55

Control Character
Recognition
• None
• Standard
• ASCII
• EBCDIC
• Two User Programmed
TX Operation
• RTS/CTS Control
Manual, Semi-Automatic,
Automatic
• Parity Mode
• Stop Bit Length
• Character Size
I/O Pins
• Select Function for Each
Multifunction Pin
• Select Direction for Multifunction Pin (If Applicable)

Inter

82510

1. IMD-INTERNAL MODE REGISTER

I I

~I'I+I'I~
RESERVED

: II

=,~_,~"~_~~"~
LEM - LOOBACK/ECHO

~LM - ~LAN MODE

RF"D -, RxFIFO DEPTH

290116-15

IMD-Internal Mode Register
ULM:

This register defines the general device mode of operation. The bit functions are as follows:

7-4:

Reserved

lAM:

Interrupt Acknowledge Mode Bit

Manual acknowledgement of pending interrupts
1 - Automatic acknowledgement of
pending interrupts (upon CPU service)
.

This bjt, when set, configures the 82510 for the automatic acknowledge mode. This causes the 82510
INT line to go low.for two clock cycles upon service
of the interrupt. After two clock cycles it is then updated. It is useful in the edge triggered mode. In
manual acknowledgement mode the CPU. must explicitly issue a command to clear the INT pin. (The
INT pin then goes low for a minimum of two clock
cycles until another 'enabled status register bit is
set.)

RFD:

uLAN Mode

Normal Mode
1 -uLAN Mode

This bit, enables the 82510 to recognize and/or
match address using the 9-bit MCS-51 asynchronous protocol.

LEM:

Loopback/Echo Mode Select

This bit selects the mode of loopback operation, or
the mode_ of echo operation; depending upon which
operation mode is selected by the Modem Control
register bit LC.
In loopback mode (Modem Control register bit
LC = 1) it selects. between local and remote loopback.

o1-

Local Loopback
Remote Loopback '

In echo mode (Modem Control register bit LC = 0) it
selects between echo or non-echo operation.

Receive FIFO Depth

o1-

0 - No Echo
1 - Echo Operation

Four Bytes
One Byte

This bit configures the depth of the Rx FIFO. With a
FIFO depth .ofqne, the FIFO will act as a 1-byte
buffer to emulate the 8250A.

2-56

intJ

82510

2. LCR-LINE CONFIGURE REGISTER

DLAB

ClO} CHARACTER
CLl lENGTH

SBK - SET BACK
PARITY

[:~~ +------'
PMO

L -_ _. ,

SBlO - STOP BIT lENGTH

+-------1

290116-16

LCR-Line Configure Register
This register defines the basic configuration of the
serial link.

Table 13. Stop Bit Length

DLAB-Divisor Latch Access Bit-This bit, when
set, allows access to the Divisor Count registers
BAL,BAH;BBL,BBH registers.

SBL2

SBL1

SBLO

0
0
0
0

0
0

1
1

1
1
1
1

0
0

SBK-Set Break Bit-This bit will force the TxD pin
low. The TxD pin will remain low (regardless of all
activities) until this bit is reset.
PM2-PMo-Parity Mode Bits-These three bits
combine with the SPF bit of the Transmit Mode register to define the various parity modes. See Table
12.

*6/4

SPF

PM2

PM1

Function

X
0
0
0
0
1

X
0
0
1
1
0

X
0
1
0
1
0

No Parity
Odd Parity
Even Parity
High Parity
Low Parity
Software Parity

1
1
1
1
1

1
1
0
1

4/4
6/4 or 8/4'
3/4
4/4
5/4
6/4
7/4
8/4

1
1
1
1
1
2

character length IS 5 bits; else 814

CLQ-CL 1-Character Length Bits-These bits,
together with the Transmit Mode register bit NBCL,
define the character length. See Table 14.

Table 12. Parity Modes
PMO

1
1

Stop Bit Length
16X
1X

Table 14. Character Length

SBLe-Stop Bit Length-This bit, together with
SBL 1 and SBL2 bits of the Transmit Mode register,
defines the Stop-bit lengths for transmission. The Rx
machine can identify 3/4 stop bit or more. See Table
13.

2-57

NBCL

CL1

CLO

0
0
0
0

0
0

1
1

Character Length
5 BITS
6 BITS
7 BITS
8 BITS .
9 BITS

82510

3. TMD-Transmit Machine Mode Register

Tm1

TmO

TRANSMIT MODE
290116-17

TMD-Transmit Machine Mode Register
This register together with the Line Configure Register defines the Tx machine mode of operation.

01-Reserved

EED-Error Echo Disable-Disables Echo of characters received with errors (valid in echo mode
only).

82510 transmits only when CTS input is active. The

CED-Control Character Echo Disable-Disables
Echo of characters recognized as control characters
(or address characters in uLAN mode). Valid in echo
mode only.

11-Automatic Mode-In this mode the 82510
transmits only when CTS input is active. The RTS
output is activated only when transmission is enabled and there is more data to transmit.

NBCL-Nine-Bit Length-This bit, coupled with
LCR (CLO, CL 1), selects Transmit/Receive character length of nine bits. See Table 14. '

SPF-Software Parity Force-This bit defines the
parity modes along with the PMO, PM1, and PM2 bits
of the LCR register. When software parity is enabled
the software must determine the parity bit through '
the TxF register on transmission, or check the parity
bit in RxF upon reception. See Table 12.

10-Semi-Automatic Mode-In this mode the
82Ei10 activates the RTS output as long as transmission is enabled.

TM1-TMO-Transmit Mode-These bits select
one of three modes of control over the CTS and
RTS lines.

SBL2-SBL1-Stop Bit Length-These bits, together with the SBLO bit of the LCR register define
the stop bit length. See Table 13.

OO-Manual Mode-In this mode the CPU has full
control of the, Transmit operation. The CPU has to
explicitly enable/disable transmission, and activate/
check the RTS/CTS pins.

2-58

82510

4. FMD-FIFO MODE REGISTER

6151413121~1

RESERVED
RECEIVE FIFO { RFT1
THRESHOLD RFTO

1 1 .1

+-----'

~~~}

TxFIFO THRESHOLD

} RESERVED

290116-18

FMD-FIFO Mode Register
cated by these bits the Rx FIFO Interrupt is activat·
ed.

This register configures the Tx and Rx FIFO's
threshold levels-the occupancy levels that can
cause an interrupt.

3-2-Reserved
7-6-Reserved
TFT1-TFTO-Transmit FIFO Threshold-When
the TX FIFO occupancy is less than or equal to the
level indicated by these bits the Tx FIFO Interrupt is
activated.

RFT1-RFTo-Receive FIFO Threshold-When
the Rx FIFO occupancy is greater than the level indi-

5. ACRo-ADDRESS/CONTROL CHARACTER REGISTER 0

290116-47

ARCo-Address/Control Character Register 0
character must be right justified and the leading bits
be filled with zeros.

This register contains a byte which is compared to
each received character. The exact function depends on the configuration of the IMD register.

In uLAN mode this register contains the eight-bit station address for recognition. In this mode only incoming address characters (Le., characters with address bit set) will be compared to these register. The
PCRF bit in the RECEIVE STATUS register will be
set when an Address or Control· Character match
occurs.

In normal mode this register may be used to pro·
gram a special control character; a matched character will be reported in the RECEIVE STATUS register. The maximum length of the control characters is
eight bits. If the length is less than eight bits then the

6. ACR1-ADDRESS/CONTROL CHARACTER REGISTER 1

290116-48

ARC1-Address/Control Character Register 1
NOTE:
This register is identical in function to AeRO.

2-59

82510

7. RMD-RECEIVE MACHINE MODE REGISTER

}'LA~~~~N~~~~ [:~~~
DISABLE DPLL - DPD

~76151413121;~
-II

] RESERVED

_II

~I"----'

SAMPLING WINDOW- SWM MODE

START BIT SAMPLING MODE
290116-19

RMD-Receive Machine Mode Register
This.register defines the Rx Machine mode of opera·
tion.
uCMO, uCM1-uLAN/Control Character Recognition Mode-In normal mode it defines the Control
Character recognition mode. In ulan mode they define modes of address recognition.
In uLAN mode: selects the mode of address recognition.
OD-Manual Mode-Rx Machine reports reception
of any address character, via CRF bit of RECEIVE
STATUS register, and writes it to the Rx FIFO.

11-Reserved
In normal Mode: selects the mode of Standard Set
Control Character Recognition (programmed control
characters are always recognized).
00- No Standard Set Control Characters Recognized.
01- ASCII Control Characters
(00H-1 FH + 7FH).
10- Reserved.
11- EBCDIC Control Character Recognized
(OOH - 3FH).
DPD-Disable Digital Phase Locked Loo~When
set, disables the DPLL machine. (Note: using the
DPLL in a very noisy media, may increase the error
rate.)

01-Semi-Automatic Mode-Operates the same
as Manual Mode but, in addition, the Rx Machine
OPENS (unlocks) the Rx FIFO upon reception of any
address characters. Subsequent received characters will be written into the FIFO. (Note: it is the user's responsibility to LOCK the FIFO if the address
character does not match the station's address.)

SWM-Sampling Window Mode-This bit controls
the mode of data sampling:
O-Small Window, 3/16 sampling.
1-Large Window, 7/16 sampling.

1D-Automatic Mode-The Rx Machine will OPEN
(unlock) the Rx FIFO upon Address Match. In addition the Rx Machine LOCKs the Rx FIFO upon recognition of address mismatch; i.e., it controls the
flow of characters into the Rx FIFO depending upon
the results of the address comparison. If a match
occurs it will allow characters to be sent to the FIFO;
if a mismatch occurs it will keep the characters out
of the FIFO by LOCKING it.

SSM-Start Bit Sampling Mode-This bit controls
the mode of Start Bit sampling.
.
0- Majority Voting for start bit. In this mode a majority of the samples determines the bit.
1- In this mode if one of the bit samples is not
'0', the start bit will not be detected.

2-60

inter

82510

8. CLCF-CLOCKS CONFIGURE REGISTER

RxClOCK MODE-RxCM

~01511411311211 ~o 1

Rx CLOCK SOURCE - RxCS
TxClOCK MODE-TxCM -4-----'.
Tx ClK SOURCE - TxCS

RESERVED

. -

+------'

290116-20

CLCF-Clocks Configure Register
This register defines the Transmit and Receive Code
modes and sources.

TxCM-Transmit Clock Mode-This bit selects the
mode of the Transmit Data Clock, which is used to
clock out the Transmit Data.
0-16X Mode
1-1X Mode. In this mode the Transmit data is
synchronous to the Serial Clock; supplied via
the SCLK pin.

RxCM-Rx Clock Mode-This bit selects the mode
of the receive clock which is used to sample the
received data.
0-16X Mode.
1-1X Mode. In this mode the receive data must be
synchronous to the Rx Clock; supplied via the
SCLK pin.

TxCS-Transmit Clock . Source-Selects the
source of internal Transmit Clock in case of 16X
mode.
O-BRGB Output.
1-BRGA Output.

RxCS-Rx Clock Source-This bit selects the
source of the internal receive clock in the case of
16X mode (as programmed by the RxCM bit above).
O-BRGB Output
1-BRGA Output
9. BACF-BRGA CONFIGURATION REGISTER

gl+I*I~ "'~rn
,,~o=, ~,cr_~~;
RESERVED
RESERVED

RESERVED

I III

RESERVED

BAM - BRGA MODE

RESERVED

290116-21

BACF-BRGA Configuration Register
This register defines the BRGA clock sources and
the mode of operation.

BAM-BRGA Mode of Operation-Selects between the Timer mode or the Baud Rate Generator
Mode.

BACS-BRGA Clock Source-Selects the input
clock source for Baud Rate Generator A.

0- Timer Mode (in this mode the input clock
source is always the system clock).
1- Baud Rate Generator Mode

O-System Clock
1-SCLK Pin
This bit has no effect if BRGA is configured as a
timer.

2-61

82510
10; BBCF-BRGB CONFIGURATION REGISTER

290116-22

BBCF-BRGB Configuration Register
This register defines the SAGS clock sources and
mode of operation. (Note: SAGS can also take its
Input Clock from the output of SAGA.)
BBCS1, BBCSO-These two bits together define the
input Clock Sources for BAGB. These bits have no
effect when in the timer mode.
00- System Clock
01- SCLK Pin

10- BAGA Output
11- Aeserved
BBM-BAGB Mode of Operation.
0- Timer Mode (In this mode the input clock
source is always the system clock.)
1- BAG Mode

11. BAl-BRGA DIVIDE COUNT lEAST SIGNIFICANT BYTE

290116-49

BAl-BRGA Divide Count low Byte
This register contains the least significant byte of the BAGA divisor/count.
12. BAH-BRGA DIVIDE COUNT MOST SIGNIFICANT BYTE

290116-50

BAH-BRGA Divide Count High Byte
This register contains the most significant byte of the BAGA divisor/count.
13. BBl-BRGB DIVIDE COUNT lEAST SIGNIFICANT BYTE

290116-51

BBl-BRGB Divide Count Low Byte
This register contains the least significant byte of the BAGB divisor/count.

2-62

inter

.82510

14. BBH-BRGB DIVIDE COUNT MOST SIGNIFICANT BYTE

290116-52

BBH-BRGB Divide Count High Byte
This register contains the most Significant byte of the BRGB divisor/count.
15. PMD-I/O PIN MODE REGISTER

2. -~'""~"

~I'I'I'I'I~

~~~o"ro_~,"-~~;

DCD/ICLK/OUT1 DIRECTION - 0100

DCD/ICLK/OUT1 fUNCTION - 0I0f

IIII

DSR/TA/OUTO fUNCTION - DTAf

} RESERVED

RRf - RI/SCLK fUNCTION

290116-23

PMD-I/O Pin Mode Register
0- IClK (Output of the Internal System Clock).
1- OUT1 general purpose output, Controlled by
MODEM CONTROL Register
.
DTAD-DSR/TAlOUTO Direction.
0- Output: T A or OUTO (Dependent upon
DTAF).
1- Input: DSR.
DTAF-DSR/TAlOUTO Direction (output
mode only).
0- TA (BRGA Output or Timer A Termination
Pulse).
1- OUTO (general purpose output, controlled by
MODEM CONTROL).
RRF-RIISClK Function
0- SClK (Receive and/or Transmit Clock)
1-RI
DTF-DTR/TB Function
0- TB (BRGB Output Clock on Timer B termina. tion pulse depending upon the mode of
BRGB).
1-DTR

This register is used to configure the direction and
function of the multifunction pins. The following options are available on each pin.
1. Direction: Input or Output Pin.
0- Defines the Pin as an output pin (general purpose or special function).
1- Defines the pin as an input pin.
2. Function: General purpose or. special purpose pin
(no effect if the pin is programmed as an Input).
0- special function output pin.
1- general purpose output pin.
DIOD-DCDIIClK/OUT1 Direction.
0- Output: IClK or OUT1 (depending on bit
DIOF)
1-lnput: DCD.
DIOF-DCDIIClK/OUT1 Function (output
mode only).

2-63

intJ

82510

INTERRUPTISTATUS REGISTERS

Interrupt Masking

The 82510 uses a two layer approach to handle interrupt and status generation. Device level registers
show the status of the major 82510 functional block
(MODEM, FIFO, Tx MACHINE, Rx MACHINE, TIMERS, etc.). Each block may be examined by reading
its individual block level registers. Also each block
has interrupt enable/generation logic which may
generate a request to the built-in interrupt controller,
the interrupt requests are then resolved on a priority
basis.

The 82510 has a device enable register, GER, which
can be used to enable or mask-out any block interrupt request. Some of the blocks (Rx Machine, Modem, Timer) have an enable register associated with
their status register which can be used to mask out
the individual sources within the block. Interrupts are
enabled when programmed high.

16. GER-GENERAL ENABLE REGISTER

RESERVED [

=" -, " ' "'

~I'I'I'I'I~
.

'"' ' ""''"' ' '.' _TI<: IIII

RFIE - Rx FIFO INTERRUPT ENABLE

TFlE - FIFO INTERRUPT ENABLE

Tx INTERRUPT ENABLE - TxlE

"',Be<

MIE - MODEM INTERRUPT ENABLE
290116-24

GER-General Enable Register
This register enables or disables the bits of the GSR
register from being reflected in the GIR register. It
serves as the device enable register and is used to
mask the interrupt requests from any of the 82510
block (See Figure 1).

MIE-Modem Interrupt Enable.
RxIE-Rx Machine Interrupt Enable.
TFIE-Transmit FIFO Interrupt Enable.

TIE-Timers interrupt Enable

RFIE-Receive FIFO Interrupt Enable.

TxIE-Transmit Machine Interrupt Enable.
17. RIE-RECEIVE INTERRUPT ENABLE REGISTER

~76151413121~O

.
CONTROL/ADORE. SS RECOGNITION
CONTROL/ADDRESS MATCH

I III.

BREAK TERMINATED

BREAK DETECTED

RESERVED·
OVERRUN ERROR
PARITY ERROR
FRAMING ERROR

290116-25

RIE-Receive Interrupt Enable Register
This register enables interrupts from the Rx Machine. It is used to mask out interrupt requests generated by the status bits of the RST register.

BkDE-Break Detection Interrupt
Enable Interrupt on BkD bit of RST.

Enable-

FEE-Framing Error Enable-Enable Interrupt on
FE bit of RST.

CRE-Control/uLAN Address Character Recognition Interrupt Enable.-Enables Interrupt when
CRF bit of RST register is set.

PEE-Parity Error Enable-Enable Interrupt on PE
bit of RST.

PCRE-Programmable Controll Address Character Match Interrupt Enable.-Enables Interrupt on
PCRF bit of RST.

OEE-overrun Error Enable-Enable Interrupt on
OE bit of RST.

BkTe-Break Termination Interrupt Enable.
2-64

intJ

82510

18. TMIE-TIMER INTERRUPT ENABLE REGISTER

290116-26

TM IE-Timers/lnterrupt Enable Register
This is the enable register for the Timer Block. It is
used to mask out interrupt requests generated by
the status bits of the TMST register.

TBIE-Timer B Expired Interrupt
Enables Interrupt on TBEx bit of TMST.

Enable-

TAlE-Timer A Expired Interrupt
Enables Interrupt on TAEx bit of TMST.

Enable-

19. MIE-MODEM INTERRUPT ENABLE REGISTER

290116-27

MIE-Modem Interrupt Enable Register
This register enables interrupts from the Modem
Block. It is used to mask out interrupt requests generated by the status bits of the MODEM STATUS
register.

CTSE-Delta CTS Interrupt Enable-Enables Interrupt on DCTS bits of MODEM STATUS.

STATUS/INTERRUPT
DCDE-Delta DCD Interrupt Enable-Enables Interrupt on DDeD bit of MODEM STATUS.

The 82510 has two device status registers, which
reflect the overall status of the device, and five block
status registers. The two device status registers,
GSR and GIR, and supplementary in function. GSR
reflects the interrupt status of all blocks, whereas
GIR depicts the highest priority interrupt only. GIR is
updated after the GSR register; the delay is of approximately two clock cycles.

RIE-Delta RI Interrupt Enable-Enables Interrupt
on DRI bit of MODEM STATUS.
DSRE-Delta DSR Interrupt Enable-Enables Interrupt on DSR bit of MODEM STATUS.

2-65

Intel

82510

20. GSR-GENERAL STATUS REGISTER

RESERVED

2','~,""'m"""

~I'I'I'I'I~

RESERVED

Rx FIFO INTERRUPT

Tx FIFO INTERRUPT

"""m""""

I11I

Tx MACHINE INTERRUPT

MODEM INTERRUPT

290116-28

GSR-General Status Register
This register reflects all the pending block-level Interrupt requests. Each bit in GSR reflects the status
of a block and may be individually enabled by GEA.
GER masks-out interrupts from GIR; it does not
have any effect on the bits in GSA. The only way
that the bits can be masked out in GSR (i.e., not
appear in GSR) is if they are masked out at the lower
level.

MIR-Modem Interrupt Request-This bit, if set,
indicates an interrupt from the Modem Module. (As
reflected in MODEM STATUS.)
RxlR-Receive Machine Interrupt Request-(As
reflected in RST.)
TFIR-Transmit FIFO Interrupt Request-Tx
FIFO occupancy is below or equal to threshold.

TIR-Timers Interrupt Request-This bit indicates
that one of the timers has expired. (See TMST)

RFIR-Receive FIFO Interrupt Request-Rx FIFO
Occupancy is above threshold.

TxIR-Transmit Machine Interrupt RequestIndicates that the Transmit Machine is either empty
or disabled (Idle).
21. GIR/BANK-GENERAL INTERRUPT REGISTER/BANK REGISTER

":~,~::

2::-::~"" " '"

~I'I+I'I~

BANK 0
RESERVED

I11I
'

B11] BLOCK
BI2 INTERRUPT

290116-29

General Interrupt Register/Bank Register
This register holds the highest priority enabled pending interrupt from GSA. In addition it holds a pointer
to the current register segment. Writing into this register will update only the BANK bits.

101:
100:
011:
010:
001:
000:

BANK1, BANKO-Bank Pointer Bits-These two
bits point to the currently accessible register bank.
The user can read and write to these bits. The address of this register is always two within all four
register banks.

Timer Interrupt (highest priority)
Tx Machine Interrupt
Rx Machine Interrupt
Rx FIFO Interrupt
Tx FIFO Interrupt
Modem Interrupt (lowest priority)

lPN-Interrupt Pending-This bit is active low. It
indicates that there is an interrupt pending. The interrupt logic asserts the INT pin as soon as this bit
goes active. (Note: the GIR register is continuously
updated; so that, while the user is serving one interrupt source, a new interrupt with higher priority may
enter GIR and replace the older interrupt.)

B12, B11, BIO,-Interrupt Bits 0-2-These three
bits reflect the highest priority enabled pending interrupt from GSA.

2-66

intJ

82510

22. LSR-LiNE STATUS REGISTER

RESERVED
TxST
TFST

I I
~rl'I'I"~

"" L) ill

COMPLEMENT DSR
COMPLEMENT CTS

STATE CHANGE DCD

290116-35

MSR-ModemIl/O Pins Status Register
This register holds the status of the Modem input
pins (CTS, DCD, DSR, RI). It is the source of interrupts (MSR 0-3) for the MIR bit of GSR. If any of the·
above inputs change levels the appropriate bit in
MODEM STATUS is set. Reading MODEM STATUS
will clear the status bits.
DCDC-DCD Complement-Holds the complement of the DCD input pin if programmed as an input
in PMD.

DR I-Delta RI-Indicates that there was a high;tolow transition on the RI input pin since the register
was last read.
DDSR-Delta DSR-Indicates that the DSR input
pin has changed state since this register was last
read.
DCTS-Delta CTS-Indicates that the CTS input
pin has changed state since this register was last
read.

DRIC-Holds the complement of the RI input pin if
programmed as an input in PMD.

COMMAND REGISTERS
DSRC-DSR Complement-Holds the complement
of the DSR input pin if configured as an input in
PMD.

The command registers are write only; they are used
to trigger an operation by the device. Once the oPE3ration is started the register is automatically reset.
There is a device level register as well as four block
command registers. It is recommended that only one
command be issued during a write cycle.

CTSC-CTS Complement-Holds the complement
of the CTS pin.
DDCD-Delta DCD-Indicates that the DCD input
pin has changed state since this register was last
read.
2-70

82510

28. ICM-INTERNAL COMMAND REGISTER

~ I III

76151413121~O

RESERVED [

•

S/W RESET - SRST

:~:E~~:WER

DOWN
STC-STATUS CLEAR
INTA - INTERRUPT ACKNOWLEDGE

290116-36

ICM-Internal Command Register
This register activates the device's general func·
tions.

clocks; afterwards, the INT pin may again go active if
other enabled interrupts are pending. This command
is provided for the Manual Acknowledge mode of
the 82510.

SRST-Device Software RESET-Causes a total
device reset; the effect is identical to the hardware
reset (except for strapping options). The reset lasts
four clocks and puts the device into the Default
Wake-up Mode.

Ste-Status Clear-Clears the following status registers: RST, MSR, and TMST.
PDM-Power Down-This command forces the device into the power-down mode. Refer to the functional description for details.

INTA-Interrupt Acknowledge-This command is
an explicit acknowledgement of the 82510's interrupt request. It forces the INT pin inactive for two

29. TCM-TRANSMIT COMMAND REGISTER

290116-37

TCM-Transmit Command Register
This register controls the operation of the Transmit
Machine.

TxEN-Transmit Enable-Enables Transmission
by the Transmit Machine.

FTM-Flush Transmit Machine-Resets the
Transmit Machine logic (but not the registers or
FIFO) and enables transmission.

TxDi-Transmit Disable-Disables transmission. If
transmission is occurring when this command is issued the Tx Machine will complete transmission of
the current character before disabling transmission.

FTF-Flush Transmit FIFO-Clears the Tx FIFO.

2-71

inter

82510

30. RCM-RECEIVE COMMAND REGISTER

~H'I'I'I§

""'"':.=:.~::~:; I III :\ O:~~:: . ",.
RECEIVE ENABLE - R x E '

FLUSH Rx FIFO - FRF

}

LRF - LOCK Rx FIFO

290116-38

RCM-Receive Command Register
This register controls the operation of the Rx machine.
RxE-Receive Enable-Enables the reception of
characters.
RxDi-Recelve Disable-Disables reception of
data on RXD pin.
FRM-Flush Receive Machine-Resets the Rx
Machine logic (but not registers and FIFOs), enables
reception, and unlocks the receive FIFO.

FRF-Flush Receive FIFo-Glears the Rx FIFO.
LRF-Locks Rx FIFO-Disables the write mechanism of the Rx FIFO so that characters subsequently
received are not written to the Rx FIFO but are lost.
However, reception is not disabled and complete
status/ event reporting continues. (This command
may be used in the uLAN mode to disable loading of
characters into the Rx FIFO until an address match
is detected.)
ORF-open (Unlock) Rx FIFO-This command enables or unlocks the write mechanism of the Rx
FIFO.

31. TMCR-TIMER CONTROL REGISTER

7615'1413121

RESERVED {

~ I III

TIMER GAT,E B-TGB TIMER GATE A-TGA

§o

:~:: :~::~ ~:~~:

.-}

+------'

;

RESERVED
290116-39

TMCR-Timer Control Register
This register controls the operation of the two 82510
timers. It has no effect when the timers are configured as baud-rate generators. TGA and TGB are
not reset after command execution.

1-enables counting
O-disables counting
STB-Start Timer B-This command triggers timer
B. .At terminal count a status bit is set in TMST
(TBEx).

TGB-Tlmer-B Gate-This bit serves as a gate for
Timer B operation:

STA-5tart Timer A-This command triggers timer
A. At terminal count a status bit is set in TMST
(TAEx).

1-enables counting
O-disables counting
TGA-Timer-A Gat~This bit serves as a gate for
Timer-A operation:

2-72

inter

82510

32. MCR-MODEM CONTROL REGISTER

290116-40

MCR-Modem Control Register
oun-OUT1 Output Bit-This bit controls the
OUT1 pin. The output signal is the complement of
this bit.

This register controls the modem output pins. With
multi-function pins it affects only the pins configured as general purpose output pins. All the output
pins invert the data, i.e. their output will be the complement of the data written into this register.

RT5-RTS Output Bit-This bit controls the RTS
pin. The output signal is the complement of this bit.

OUTo-OUTO Output Bit-This bit controls the
OUTO pin. The output Signal is the complement of
this bit.

DTR-DTR Output Bit-This bit controls the OTR
pin. The output signal is the complement of this bit.

LCB Loopback Control Bit-This bit puts the
82510 into loopback mode. The particular type of
loop back is selected via the IMO register.

DATA REGISTERS
The data registers hold data or other information
and may be accessed at any time.

OUT2-oUT2 Output Bit-This bit controls the
OUT2 pin. The output signal is the complement of
this bit.

33. TXD-TRANSMIT DATA REGISTER

290116-53

TXD-Transmit Data Register
ter. When a byte is written to this register its contents, along with the contents of the TxF register,
are pushed to the top of the Transmit FIFO. This
register is write only.

This register holds the next data byte to be pushed
into the Transmit FIFO. For character formats with
more than eight bits of data, or with additional components (S/W Parity, Address Marker Bit) the additional data bits should be written into the TxF regis-

2-73

Intel

82510

34. TXF-TRANSMIT FLAGS REGISTER

290116-41

TxF-Transmit Flags Register
This register holds some additional components of
the next character to be pushed into the Tx FIFO.
The contents of this register are pushed into the Tx
FIFO with the Transmit Data register whenever the
"
TxD register is" written to by the CPU.

SP-Software Parity Bit-This bit is transmitted in
S/W parity mode as the character's parity bit.
DB-Ninth"Bit.of Data-In nine-bit character length
mode this bit is transmitted as the MSB (08) bit.

uLAN-uLAN Address Marker Bit-This bit is
transmitted in uLAN mode as the address marker
bit.
35. RXD-RECEIVE DATA REGISTER

290116-54

RXD-Receive Data Register
This register holds the earliest received character in
the Rx FIFO. The character is right justified and
leading bits are zeroed. This register is loaded by the

Rx Machine with the first received character. Reading the register causes the next register from the Rx
FIFO to be loaded into RxD and RxF registers.

2-74

inter

82510

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias ...... O·C to 70·C
Storage Temperature ............ - 65· to

+ 150·C
+ 0.5V

Voltage on any Pin (w.r.t. VSS) -0.5V to Vee

Voltage on Vee Pin (w.r.t. VSS) ...... -0.5V to

+ 7V

Power Dissipation ....................... 300 mW

D.C. SPECIFICATIONS
D.C. CHARACTERISTICS
Symbol
VIL

(TA = O·to 70·C, Vee = 5V ±10%)

Parameter
Input Low Voltage

Notes

Min

Max

Units

(1 )

-0.5

0.8

2.0

Vee- 0.5

0.45

VIH

Input High Voltage

(1 )

VOL

Output Low Voltage

(2), (9)

VOH

Output High Voltage

(3), (9)

III

Input Leakage Current

(4)

±10

ILO

3-State Leakage Current

(5)

±10

/LA

Icc

Power Supply Current

(6)

3.8

mA/MHz

2.4

V
/LA

Ipd

Power Down Supply

(7)

ISTBY

Standby Supply Current

(10)

500

/LA

IOHR

RTS, DTR Strapping Current

(11 )

0.4

IOLR

RTS, DTR Strapping Current

(12)

Cin

Input Capacitance

(8)

Cio

1/0 Capacitance

(8)

CXTAL

X1, X2 Load

NOTES:

1. Does not apply to eLK/X1 pin, when configured as crystal oscillator input (X1).
2.@loL=2mA.
3. @ IOH = -0.4 rnA.
4. 0 < VIN < Vee.
5. 0.45V < VOUT < (Vee - 0.45).
6. Vee = 5.5V; VIL = 0.5V (max); VIH = Vee - 0.5V (min); 35 mA (max); Typical value = 2.5 mA/MHz (Not Tested); Ext
1X elK (9 MHz max); IOL = IOH = O.
7. Vee = 5.5V; VIL = GND; VIH = Vee; IOL = IOH = 0; device at power down mode, clock running.
8. Freq = 1 MHz.
9. Does not apply to OUT2/X2 pin, when configured as crystal oscillator output (X2).
10. Same as 7, but input clock not running.
11. Applies only during hardware reset for clock configuration options. Strapping current for logic HIGH.
12. Applies only during hardware reset for clock configuration. Strapping current for logic LOW.

2-75

Intel

82510

A.C. SPECIFICATIONS

SYSTEM CLOCK SPECIFICATIONS
Symbol

Testing Conditions:
• All AC output parameters are under output load
of 20 to 100 pF, unless otherwise specified.
• AC testing inputs are driven at 2.4 for logic '1',
and 0.45V for logic '0'. Output timing measurements are made at 1.5V for both a logical '0'
and '1'.
• In the following tables, the units are ns, unless
otherwise specified.
System Interface Specification-System Clock
Specification:

Min

Max

Notes

Tcy/2

CLKPeriod

TCLCH

CLKLowTime

250

(2)

TCHCL

CLK High Time

TCH1CH2

CLK Rise Time

(1)

TCL2CL1

CLKFaliTime

(1)

FXTAL

External Crystal
Frequency Rating

4.0

18.432
MHz

DIVIDE BY TWO OPTION-INACTIVE

The 82510 system 'clock is supplied via the ClK pin
or generated by an on-chip crystal oscillator. The
.clock is optionally divided by two. The ClK parameters are given separately for internal divide-by-two
option ACTIVE and INACTIVE.
The system clock (after division by two, if active)
must be at least 16X the Tx or Rx baud rate (the
faster of the two).

Parameter.

DIVIDE BY TWO OPTION-ACTIVE

ICY

CLKPeriod

108

TCLCH

CLKLowTme

TCHCL

CLK High Time

TCH1CH2

CLK Rise Time

(1)

TCL2CL1

CLK FailTime

(1)

250

NOTES:
1. Rise/fall times are measured between 0.8 and 2.0V.
2. Tcy in ACTIVE divide by two option is TWICE the input
clock period.

RESET SPECIFICATION
. Symbol

Parameter

Min

TRSHl

Reset Width-ClK/X1 Configured to ClK

8Tcy

(1)

TTlRSl

RTS/DTR lOW Setup to.Reset Inactive

6Tcy

(2)

TRSlTX

FirS/DTR low Hold after Reset Inactive

RESET

---------/

Tcy - 20

Notes

(2)

------------

):.

....._ _ _ _ _ _ _ _ _ _ _.....i=TTLRSL.

DTR/RTS

Max

TRSLTX=r,....._~_ _

----~--------------+-------------~------290116-43

NOTES:
1. In case of CLK/X1 configured as X1, 1 Ms is required to guarantee crystal oscillator wake-up.
.
2. RTS/DTR are internally driven HIGH during RESET active .time. The pili should be either left OPEN or externally driven
LOW during RESET according. to the required configuration of the system clock. These parameters specify the timing requirements on these pins, in case they are externally driven LOW during .RESET..
The maximum spec on TRSLTX requires tha~ the RTS/DTR pins not be forced later than TRSLTX maximum.

2-76

82510

READ CYCLE SPECIFICATIONS
Symbol

Parameter

Min

RD Active Width

TAVRL

Address/CS Setup Time to RD Active

TRHAX

Address/CS Hold Time after RD Inactive

2Tcy

TRLDV

Data Out Valid Delay after RD Active

TCIAD

Command Inactive to Active Delay

TRHDZ

Data Out Float Delay after RD Inactive

Max

TRLRH

2Tcy
Tcy

Notes

65
(1 )

NOTE:
1. Command refers to either Read or Write signals.

A2-0

VALID

D7-0-------------(~~:)~------------------------~--------290116-44

WRITE CYCLE SPECIFICATION
Symbol

Parameter

Min

TWLWH WR Active Width
TAVWL

Address CS Setup Time to WR Active

D7-0

TDVWH Data in Setup Time to WR Inactive

TWHDX Data in Hold Time after WR Inactive

__ TWLWH_ -- TCIAD __
TWHAX.r-_
VALID

TDVWH

.....

Max Notes

+ 15

TWHAX Address and CS Hold Time after WR

TAVWL
A2-0

2Tcy

VALID

TWHDX

VALID
I-TCIAD.:1

\.
290116-45

NOTE:
Many of the serial interface pins have more than one function; sometimes the different functions have different timings. In
such a case, the timing of each function of a pin is given separately.

2-77

82510

SCLK PIN SPECIFICATION-16x CLOCKING
MODE
,
Symbol

Parameter

Min

Max

Notes

SCLK Rise Time

(1 )

SCLK Fall Time

(1 )

Max

Notes

Txcy

SCLK Period

216

TXLXH

SCLK Low Time

TXHXL

SCLK High Time

TXH1XH2
TXL2XL1

NOTE:
1. Rise/fall times are measured between O.8V and 2.0V.

SCLK PIN SPECIFICATION-1x CLOCK MODE
Symbol

Parameter

Min

Txcy

SCLK Period

3500

TXLXH

SCLK Low Time

1650

TXHXL

SCLK High Time

1650

TXH1XH2

SCLK Rise Time

(1 )

TXL2XL1

SCLK Fall Time

(1)

NOTE:
1. Rise/fall times are measured between O.8V and 2.0V.

RXD SPECIFICATION (1x MODE)
Parameter

Symbol

Min

TRPW

RXD Setup Time to SCLK High

250

TRPD

RXD Hold Time After SCLK High

250

Max

Notes

:: :::::::::::\::::rj~~---TRPD_\~:::~*-:~:::_/::::::::::
290116-46

TXD SPECIFICATION (1x MODE)
Parameter
TXD Valid Delay after SCLK Low

REMOTE LOOPBACK SPECIFICATION
Symbol

Parameter

TRXDTXD

TXD Delay after RXD

2-78

intJ

82510

CHAR 4

CHAR 3

CHAR 5

RXD pin

iID pin
RST (7-0)---...;:.;;;.'---+A----==---+......-.....;.;"---I'"""'"'T"-';.;.;;........---';;;;..--t~~'++T_-~=

FLR (6-4) _ _ _....::..._ _ _A-_ _..:...._ _......_--='---\"""'"'-\r-_ _...:;..._ _ _~.....~L,;.."'""'''-'-a.....;:....A...;..

INT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J

BREAK

RX FIFO
THRESHOLD
INTERRUPT

DETECTED
INTERRUPT

290116-55

Receive Logic Diagram

INT=GSR (1)

GSR (4)
TXD _ _ _-.:oSTROO

CHAR 1

05 STP

STROO

05 STP

CHAR 2

05 STP

CHAR 3

STROO

CHAR 4

05 STP

SlROO

0.4

05 STP

CHAR 5

290116-56

Transmit Logic Diagram

2-79

8273
PROGRAMMABLE HOLC/SOLC

PROTOCOL CONTROLLER

•
•
•
•
•
•

CCITT X.25 Compatible
HDLCISDLC Compatible
Fu" Duplex, Half Duplex, or Loop SDLC
Operation
Up to 64K Baud Synchronous Transfers
Automatic FCS (CRC) Generation and
Checking
Up to 9.6K Baud with On-Board Phase
Locked Loop

•
•
•
•
•
•

Programmable NRZI EncodelDecode
Two Programmable Modem Control
Ports
Digital Phase Locked Loop Clock
Recovery
Minimum CPU Overhead
Fu"y Compatible with 8048/80801
8085/8088/8086/80188/80186 CPUs
Single

+ 5V Supply

The Intel 8273 Programmable HOLC/SOLC Protocol Controller is a dedicated device designed to support the
ISO/CCITT's HOLC and IBM's SOLC communication line protocols. It is fully compatible with Intel's new high
performance microcomputer systems such as the MCS 188/186™. A frame level command set is achieved by
a unique microprogrammed dual processor chip architecture. The processing capability supported by the 8273
relieves the system CPU of the low level real-time tasks normally associated with controllers.
REGISTERS
TxlNT RESULT

COMMAND

RxlNT RESULT

PARAMETER

TEST MOOE

STATUS
RESULT.
FLAG DET

TxO

hORO

fiB;

ClK

Pii3
PB2

RESET

DATA
BUS
BUFFER

_ _ _ _-,

TxOAeK - - - - - ,
R,ORO _ - - - ,
R;OACK

Vee"

Tx INT

TxDACK

TxDRO

iITS

R,DACK

PA.

R,DRO

PA,

Plio

Rx INT

DBO

T,O

OBI

TxC

TIIINT

DB2

RxC

AxiNT

DB3

RxD

DB4

32xelK

DBS

OB6

OPll

,...--"""-.....,1.-_ R,O
R;c

RESET

OB7

GND

Ao
210479-2

Figure 2. Configuration

eLK - - - - - - '

' - - - - FLAGOET

CPU INTERFACE

210479-1

Figure 1. Block Diagram

2-80

December 1986
Order Number: 210479-003

inter

8273

beginning eight bit FLAG (F) consisting of one zero,
six ones, and a zero, an eight bit ADDRESS FIELD
(A), an eight bit CONTROL FIELD (C), a variable
(N-bit) INFORMATION FIELD (I), a sixteen bit
FRAME CHECK SEQUENCE (FCS), and an eight bit
end FLAG (F), having the same bit pattern as the
beginning flag. In HOLC the Address (A) and Control
(C) bytes are extendable. The HOLC and the SOLC
use three types of frames; an Information Frame is
used to transfer data, a Supervisory Frame is used
for control purposes, and a Non-sequenced Frame
is used for initialization and control of the secondary
stations.

A BRIEF DESCRIPTION OF
HDLC/SDLC PROTOCOLS
General
The High Level Data Link Control (HOLG) is a standard communication link protocol established by International Standards Organization (ISO). HOLC is
the discipline used to implement ISO X.25 packet
switching systems.
The Synchronous Data Link Control (SOLC) is an
IBM communicatiori link protocol used to implement
the System Network Architecture (SNA). Both the
protocols are bit oriented, code independent, and
ideal for full duplex communication. Some common
applications include terminal to terminal, terminal to
CPU, CPU to CPU, satellite communication, packet
switching and other high speed data links. In systems which require expensive cabling and interconnect hardware, any ,of the two protocols could be
used to simplify interfacing (by going serial), thereby
reducing interconnect hardware costs. Since both
the protocols are speed independent, reducing interconnect hardware could become an important application.

Frame Characteristics
An important characteristic of a frame is that is contents are made code transparent by use of a zero bit
insertion and deletion technique. Thus, the user can
adopt any format or code suitable for his system-it
may even be a computer word length or a "memory
dump". The frame is bit oriented that is, bits, not
characters in each field, have specific meanings.
The Frame Check Sequence (FCS) is an error detection scheme similar to the Cyclic Redundancy
Checkword (CRG) widely used in magnetic disk storage devices. The Command and Response information frames contain sequence numbers in the control
fields identifying the sent and received frames. The
sequence numbers are used in Error Recovery Procedures (ERP) and as implicit acknowledgement of
frame communication, enhancing the true full-duplex
nature of the HOLC/SOLC protocols.

Network
In both the HOLC and SOLC line protocols, according to a pre-assigned hierarchy, a PRIMARY (Control) STATION controls the overall network (data
link) and issues commands to the SECONDARY
(Slave) STATIONS. The latter comply with instructions and respond by sending appropriate RESPONSES. Whenever a transmitting station must
end transmission prematurely it sends an ABORT
character. Upon detecting an abort character, a receiving station ignores the transmission block called
a FRAME. Time fill between frames can be accomplished by transmitting either continuous frame preambles called FLAGS or an abort character. A time
fill within a frame is not permitted. Whenever a station receives a string of more than fifteen consecutive ones, the station goes into an IDLE state.

In contrast, BISYNC is basically half-duplex (two way
alternate) because of necessity to transmit immediate acknowledgement frames. HOLC/SOLC therefore saves propagation delay times and have a potential of twice the throughput rate of BISYNC.
IUs possible to use HOLC or SOLC over half duplex
lines but there is a corresponding loss in throughput
. because both are primarily designed for full-duplex
communication. As in any synchronous system, the
bit rate is determined by the clock bits supplied by
the modem, protocols themselves are speed independent.
A byproduct of the use of zero-bit insertion-deletion
technique is the non-return-to-zero invert (NRZI)
data transmission/reception compatibility. The latter
allows HOLC/SOLC protocols to be used with asynchronous data communication hardware in which
the clocks are derived from the NRZI encoded data.

Frames
A single communication element is called a FRAME
which can be used for both Link Control and data
transfer purposes. The elements of a frame are the

2-81

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8273

References

Guidebook to Data Communciations, Training Manual, Hewlett-Packard 5955-1715

IBM Synchronous Data Link Control General Information, IBM, GA27-3093-1.

IBM Introduction to Teleprocessing, IBM, GC 208095-02

Standard Network Access Protocol Specification,
DATA PAC, Trans-Canada Telephone System
CCG111

System Network Architecture, Technical Overview,
IBM, GA 27-3102
System Network Architecture Format andProtoco/'
IBM GA 27-3112

Recommendation X.25 ISO/CCITT March 2, 1976.
IBM 3650 Retail Store System Loop Interface OEM
Information, IBM, GA 27-3098-0

OPENING
FLAG (F)

AOORESS
FIELD (A)

01111110

CONTROL
FIELD (C)

BBITS

I~IFORMATION

FIELD (I)
VARIABLE LENGTH
(ONLY IN I FRAMES)

FRAME CHECK
SEQUENCE (FCS)

CLOSING
FLAG (F)

16 BITS

01111110

210479-37

Figure 3. Frame Format
Table 1. Pin Description
Symbol

Pin
No.

Vee

GND

Name and Function

Type
POWER SUPPLV:

+ 5V Supply.

GROUND: Ground.

RESET

RESET: A high signal on this pin will force the 8273 to an idle state.
The 8273 will remain idle until a'command is issued by the CPU. The
. modem interface output signals are forced high. Reset must be true for
a minimum of 10 TCV.

CHIP SELECT: The RD and WR inputs. are enabled by the chip select
input.

12-19

1/0

WRITE INPUT: The Write signal is used to control the transfer of either
a command or data from CPU to the 8273.

READ INPUT: The Read signal is used to control the transfer of either
a data byte or a status word from the 8273 to the CPU.

TxlNT

TRANSMITTER INTERRUPT: The Transmitter interrupt signal
indicates that the transmitter logic requires service.

RxlNT

TxDRQ

TRANSMITTER DATA REQUEST: Requests a transfer of data
between memory and the 8273 for a transmit operation.

RxRDQ

RECEIVER DMA REQUEST: Requests a transfer of data between the
8273 and memory for a receive operation.

DBo-DB7

DATA BUS: The Data Bus lines are bidirectional three-state lines
which interface with the system Data Bus.

RECEIVER INTERRUPT: The Receiver interrupt signal indicates that
. the Receiver logic requires service.

2-82

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8273

Table 1. Pin Description (Continued)
Pin
No.

Type

TXDACK

TRANSMITTER DMA ACKNOWLEDGE: The Transmitter DMA
acknowledge signal notifies the 8273 that the TxDMA cycle has been
granted.

RxDACK

RECEIVER DMA ACKNOWLEDGE: The Receiver DMA acknowledge
signal notifies the 8273 that the RxDMA cycle has been granted.

21-22

ADDRESS: These two lines are CPU Interface Register Select lines.

TxD

TRANSMITTER DATA: This line transmits the serial data to the
communication channel.

TxC

TRANSMITTER CLOCK: The transmitter clock is used to synchronize
the transmit data.

RxD

RECEIVER DATA: This line receives serial data from the
communication channel.

RxC

RECEIVER CLOCK: The Receiver Clock is used to synchronize the
receive data.

32XClK

32X CLOCK: The 32X clock is used to provide ciock recovery when an
asynchronous modem is used. In loop configuration the loop station
can run without an accurate 1X clock by using the 32X ClK in
conjunction with the DPll output. (This pin must be grounded when
not used.)

DPll

DIGITAL PHASE LOCKED LOOP: Digital Phase locked loop output
can be tied to RxC and/or TxC when 1X clock is not available. DPll is
used with 32X ClK.

FLAG DETECT: Flag Detect signals that a flag (01111110) has been
received by an active receiver.

RTS

REQUEST TO SEND: Request to Send signals that the 8273 is ready
to transmit data.

CTS

CLEAR TO SEND: Clear to Send signals that the modem is ready to
accept data from the 8273.

CARRIER DETECT: Carrier Detect signals that the line transmission
has started and the 8273 may begin to sample data on RxD line.

PA2-4

32-34

GENERAL PURPOSE INPUT PORTS: The logic levels on these lines
can be Read by the CPU through the Data Bus Buffer.

PB1-4

36-39

GENERAL PURPOSE OUTPUT PORTS: The CPU can write these
output lines through Data Bus Buffer.

CLOCK: A square wave TIL clock.

Symbol

Ao-A1

FLAG DET

ClK

Name and Function

2-83

8273

FUNCTIONAL DESCRIPTION

CPU Interface
The CPU interface is optimized for the MCS-80/
85™ bus with an 8257 DMA controller. However,
the interface is flexible, and allows either DMA or
non-DMA data transfers, interrupt or non-interrupt
driven. It further allows maximum line utilization by
providing early interrupt mechanism for buffered
(only the information field can be transferred to
memory) Tx command overlapping. It also provides
separate Rx and Tx interrupt output channels for efficient operation. The 8273 keeps the interrupt request active until all the associated interrupt results
have been read.

General
The Intel 8273 HDLe/SDLC controller is a microcomputer peripheral device which supports the In-ternational Standards Organization (ISO) High Level
Data Link Control (HDLC), and IBM Synchronous
Data. Link Control (SDLC) communications protocols. This controller minimizes CPU software by supporting a comprehensive frame-level instruction set
and by hardware implementation of the low level
tasks associated with frame assembly/disassembly
and data integrity. The 8273 can be used in either
synchronous or asynchronous applications.
In asynchronous applications the data can be programmed to be encoded/decoded in NRZI code.
The clock is derived from the NRZI data using a digital phase locked· loop. The data transparency is
achieved by using a zero-bit insertion/deletion technique. The frames are automatically checked for errors during reception by verifying the Frame Check
·Sequence (FCS); the FCS is automatically generated and appended before the final flag in transmit. _
The 8273 recognizes and can generate flags
(01111110) Abort, Idle, and GA (EOP) characters.

The CPU utilizes the CPU interface to specify commands and transfer data. It consists of seven registers addressed via CIA, A1, AD, RD and WR signals
and two independent data registers for receive data
and transmit data. A1, AD are generally derived from
two low order bits of the address bus. If an 8080
based CPU is utilized, the RD and WR signals may
be driven by the 8228 I/OR and I/OW. The table
shows the seven register select decoding:
A1 AD TxDACK RxDACK CS RD WR

o
o
0
0
1
1
1
1

The 8273 can assume either a primary (control) or a
secondary (slave) role. It can therefore be readily
implemented in an SDLC loop configuration astypified by the IBM 3650 Retail Store System by programming the 8273 into a one-bit delay mode. In
such a configuration, a two wire pair can be effectively used for data transfer between controllers and
loop stations. The digital phase locked ·Ioop output
pin can be used by the loop station without the presence of an accurate Tx clock.

0
0
1
1
0
0
1
1

X X
X X

2-84

1
1
1
1
1
1
1
1
0
1

1
1
1
1
1
1
1
1
1
0

0 1
0 0
0 1
0 0
0 1
0 0
0 1
0 0
1 1
1 0

0
1
0
1
0
1
0
1
0
1

RxlNT Result
Transmit Data
Receive Data

intJ

8273

REGISTERS
hiNT- RESULT

COMMAND

R.INT RESULT PARAMETER
TEST MODE

STATUS
RESULT

T.DRO
DPll
32X ClK

T.DACK
R.DRO

RTS

R.DACK

PB'_4
hiNT

CTS

R.INT

AD
WR
AO

READ!
WRITE
DMA!
CONTROL
lOGIC

A,
RESET

CS
ClK

FLAG DET

CPU INTERFACE

MODEM INTERFACE

210479-3

Figure 4. 8273 Block Diagram Showing CPU Interface Functions

2-85

inter

8273

RxDRQ: RECEIVE DMA REQUEST

COMMAND

Requests a transfer of data between the 8273 and
memory for a receive operation.

Operations are initiated by writing an appropriate
command in the Command Register.

RxDACK: RECEIVE DMA ACKNOWLEDGE

PARAMETER

Parameters of commands that' require additioal information are written to this register.
RESULT

Contains an immediate result describing an outcome
of an executed command.
TRANSMIT INTERRUPT RESULT

Contains the outcome of 8273 transmit operation
(good/bad completion).
RECEIVE INTERRUPT RESULT.

Contains the outcome. of 8273 receive operation
(good/bad completion), followed by additional results which detail the reason for interrupt.

The RxDACK signal notifies the 8273 that a receive
DMA cycle has been granted. It is also used with RD
to read data from the 8273 in non-DMA mode. Note:
WR must not be asserted while RxDACK.is active.
RD, WR: READ, WRITE

The RD and WR signals are used to specify the direction of the data transfer.
DMA transfers require the. use ofa DMA controller
such as the Intel 8257. The function of the DMA
controller is to provide sequential addresses and
timing for the transfer, at a starting address determined by the CPU. Counting of data blocks lengths
is performed by the 8273.
To request a DMA transfer the 8273 raises the appropriate DMA REQUEST. DMA ACKNOWLEDGE
and READ enables DMA data onto the bus (inde c
pendently of CHIP SELECT). DMA ACKNOWLEDGE
and WRITE transfers DMA data to the 8273 (independent of CHIP SELECT).

STATUS

It is also possible to configure the 8273 in the nonDMA data transfer mode. In this mode the CPU
module must pass data to the 8273 in response to
non-DMA data requests indicated by status word.

The status register reflects the state of the 8273
CPU Interface.

DMA Data Transfers
Modem Interface

The 8273 CPU interface supports two independent
data interfaces: receive data and transmit data. At
high data transmission speeds the data transfer rate
of the 8273 is great enough to justify the use of direct memory access (DMA) for the data transfers.
When the 8273 is configured in DMA mode, the elements of the DMA interfaces are:

The 8273 Modem interface provides both dedicated
and user defined modem control functions. All the
control signals are active low so that EIA RS-232C
inverting drivers (MC 1488) and inverting receivers
(MC 1489) may be used to interface to standard modems. For asynchronous operation, this interface
supports programmable NRZI data encode/decode,
a digital phase locked loop for efficient clock extraction from NRZI data, and modem control ports with
automatic CTS, CD monitoring and RTS generation.
This interface also allows the 8273 to operate in
PRE-FRAME SYNC mode in which the 8273 prefixes 16 transitions to a frame to synchronize idle lines
before transmission of the first flag.

TxDRQ: TRANSMIT DMA REQUEST

Requests a transfer of data between memory and
the 8273 for a transmit operation.
TxDACK: TRANSMIT DMA ACKNOWLEDGE

The TxDACK signal notifies the 8273 that a transmit
DMA cycle has been granted. It is also used with
WR to transfer data to the 8273 in non-DMA mode.
Note: RD must not be asserted while TxDACK is
active.

It should be noted that all the 8273 port operations
deal with logical values, for instance, bit DO of Port A
will be a one when CTS (Pin 30) is a physical zero
(logical one).

2-86

intJ

8273

PORT A -

Serial Data Logic

INPUT PORT

During operation, the 8273 interrogates input pins
CTS (Clear to Send) and CD (Carrier Detect). CTS is
used to condition the start of a transmission. If during transmission CTS is lost the 8273 generates an
interrupt. During reception, if CD is lost, the 8273
generates an interrupt.
~

The Serial data is synchronized by the user transmit
(TxC) and receive (RxC) clocks. The leading edge of
TxC generates new transmit data and the trailing
edge of RxC is used to capture receive data. The
NRZI encoding/decoding of the receive and transmit data is programmable.

The diagnostic features included in the Serial Data
logic are programmable loop back of data and selectable clock for the receiver. In the loop-back
mode, the data presented to the TxD pin is internally
routed to the receive data input circuitry in place of
the RxD pin, thus allowing a CPU to send a message
to itself to verify operation of the 8273.

I
ICTS -

CLEAR TO SEND

CD - CARRIER DETECT

210479-38

In the selectable clock diagnostic feature, when the
data is looped back, the receiver may be presented
incorrect sample timing by the external circuitry. The
user may select to substitute the TxC pin for the RxC
input on-chip so that the clock used to generate the
loop back data is used to sample it. Since TxD is
generated off the leading edge of TxC and RxD is
sampled on the trailing edge, the selected clock allows bit synchronism.

The user defined input bits correspond to the 8273
PA4, PA3 and PA2 pins. The 8273 does not interrogate or manipulate these bits.
PORT B • OUTPUT PORT

During normal operation, if the CPU sets RTS active,
the 8273 will not change this pin; however, if the
CPU sets RTS inactive, the 8273 will activate it before each transmission and deactivate it one byte
time after transmission. While the receiver is active
the flag detect pin is pulsed each time a flag sequence is detected in the receive data stream. Following an 8273 reset, all pins of Port B are set to a
high, inactive level.

ASYNCHRONOUS MODE INTERFACE

Although the 8273 is fully compatible with the
HDLC/SDLC communication line protocols, which
are primarily designed for sychronous communication, the 8273 can also be used in asynchronous
applications by using this interface. The interface
employs a digital phase locked loop (DPLL) for clock
recovery from a receive data stream and programmable NRZI encoding and decoding of data. The
use of NRZI coding with SDLC transmission guarantees that within a frame, data transitions will occur at
least every five bit times-the longest sequence of
ones which may be transmitted without zero-bit insertion. The DPLL should be used only when NRZI
coding is used since the NRZI coding will transmit
zero sequence as line transitions. The digital phase
locked loop also facilitates full-duplex and half-duplex asynchronous implementation with, or without
modems.

RTS - REQUEST TO SEND

USER DEFINED OUTPUT PB4. pel, pez, PBl

FLAG DETECT

210479-39

The user defined output bits correspond to the state
of PB4-PB1 pins. The 8273 does not interrogate or
manipulate these bits.

2-87

8273

REGISTERS

i5PIT.
ffiClK

FiTs

PB'_4

PA2 _ 4

..........' - - , - - R,O

R;C

INTERNAL DATA BUS -

MODEM INTERFACE

CPU INTERFACE

210479-4

Figure 5. 8273 Block Diagram Showing Control Logic Functions

TxD

RxD

210479-5

Figure 6. Transmit/Receive Timing

2-88

8273

quadrant A 1, it is apparent that the DPll sample
"A" was placed too close to the trailing edge of the
data cell; sample "B" will then be placed at T =
(T nominal - 2 counts) = 30 counts of the 32X ClK to
move the sample pulse "B" toward the nominal center of the next bit cell. A data edge occuring in quadrant B1 would cause a smaller adjustment of phase
with T = 31 counts of the 32X ClK. Using this technique the DPll pulse will converge to nominal bit
center within 12 data bit times, worst case, with constant incoming RxD edges.

DIGITAL PHASE LOCKED LOOP

In asynchronous applications, the clock is derived
from the receiver data stream by the use of the digital phase locked loop (DPll). The DPll requires a
clock input at 32 times the required baud rate. The
receive data (RxD) is sampled with this 32X ClK and
the 8273 DPll supplies a sample pulse nomminally
centered on the RxD bit cells. The DPll has a builtin "stiffness" which reduces sensitivity to line noise
and bit distortion. This is accomplished by making
phase error adjustments in discrete increments.
Since the nominal pulse is made to occur at 32
counts of the 32X ClK, these counts are subtracted
or added to the nominal, depending upon which
quadrant of the four error quadrants the data edge
occurs in. For example if an RxD edge is detected in

RXD ______

-J)(~

A method of attaining bit synchronism following a
line idle is to use PRE-FRAME SYNC mode of transmission.

__________________J)(~__________________J)(~___________

DPLL
SAMPLES
A

Figure 7. DPLL Sample Timing

2-89

inter

8273

SYNCHRONOUS MODEM-DUPLEX OR HALF DUPLEX OPERATION

8273

RxC
RxO
TxC
TxO

32xCLK

DJiIT

GNO

N.C.

MODEM

~
RxO

8273

TxC
TxO

MODEM

32xCLK

OPLL

N.C.

GNO

210479-7

ASYNCHRONOUS MODES-DUPLEX OR HALF DUPLEX OPERATION

8273

32xCLK

TxC
TxO

I--

RxC
RxO

I--

MODEM

"-r

MODEM

OPLL

TxC
TxO

8273

RxC
RxO
3ZxCLK

32x
CLOCK

OPLL

32x
CLOCK

210479-8

ASYNCHRONOUS-NO MODEMS-DUPLEX OR HALF DUPLEX

8273

32xCLK

TxC
TxO
RxC
RxO

----.

>----

RxC
RxO

8273

TxC
TxO
32xCLK

OPLL

32x
CLOCK

Opt[

32!c
CLOCK

210479-33

2-90

inter

8273

ondary station finding its address in the A field captures the frame for action at that station. All received
frames are relayed to the next station on the loop.

SOLC LOOP
The DPLL simplifies the SDLe loop station implementation. In this application, each secondary station on a loop data link is a repeater set in one-bit
delay mode. The signals sent out on the loop by the
loop controller (primary station) are relayed from station to station then, back to the controller. Any sec-

Loop stations are required to derive bit timing from
the incoming NRZI data stream. The DPLL generates sample Rx clock timing for reception and uses
the same clock to implement Tx clock timing.

32x
CLOCK

1
32xCLK
lX LOOP
OSCILLATOR

r-- TxC

DPLL
RxC

8273
LOOP
CONTROLLER

TxD

RxD

l
RxD RxC

TxC TxD

8273
LOOP
TERMINAL

32xCLK

TxD

8273
LOOP
TERMINAL
RxD

TXC

RxC

DPLL

32x
CLOCK

32xCLK

32x
CLOCK
210479-9

Figure 8. SOLC Loop Application

2-91

8273

PRINCIPLES OF OPERATION

Bit 7 CBSY (Command Busy)

The 8273 is an intelligent peripheral controller which
relieves the CPU of many of the rote tasks associated with constructing and receiving frames. It is fully
compatible with the MCS-80/85™ system bus. As a
peripheral device, it accepts commands from a CPU,
executes these commands and provides an Interrupt
and Result back to the CPU at the end of the execution. The communication with the CPU is done by
. activation of CS, RD, WR, pins while the A1, Ao select the appropriate registers on the chip as described in the Hardware. Description Section.

Indicates in-progress command, set. for CPU poll
when Command Register is full, reset upon command phase completion. It is improper to write a
command when CBSY is set; it results in incorrect
operation.

The 8273 operation is composed of the following
sequence of events:

COMMAND PHASE

YES

II EXECUTION PHASE I
J

~~3~U~~g~~~N~~:~~~:=:~~;~~N;O THE
THE 8273 IS ON ITS OWN TO CARRY OUT THE COMMAND.

THE 8273 SIGNALS THE CPU THAT THE EXECUTION

RESULT PHASE

I ~"::l~::EgF~~~~~:~~~~'VHC::R:E:I::~S.
210479-40

The Command Place
END OF COMMAND PHASE

During the command phase, the software writes a
command to the command register. The command
bytes provide a general description of the type of
operation requested. Many commands require more
detailed information about the command. In such a
case up to four parameters are written into the parameter register. The flowchart of the command
phase indicates that a command may not be issued
if the Status Register indicates that the device is
busy. Similarly if a parameter is issued when the Parameter Buffer shows full, incorrectoperation will occur.

YES

210479-10

The 8273 is a duplex device and both transmitter
and receiver may each be executing a command or
passing results at any given time. For this reason
separate interrupt pins are provided. However, the
command register must be used for one command
sequence at a time.

Figure 9. Command Phase Flowchart
Bit 6 CBF (Command Buffer Full)
Indicates that the command register is full, it is reset
when the 8273 accepts the command byte but does
not imply that execution has begun.

STATUS REGISTER

The status register contains the status of the 8273
activity. The description is as follows.
.
07

Bit 5 CPBF (Command Paramet.er Buffer Full)
CPBF is set when the parameter buffer is full, .and is
reset by the 8273 when it accepts the parameter.
The CPU may 1>011 CPBF to determine when additioDal parameters may be written.

I~YI~I~I~~I~ml~MI~AAI~ml

2-92

inter

8273

Bit 4 CRBF (Command Result Buffer Full)

Bit 0 TxlRA (Transmitter Interrupt Result
Available)

Indicates that an executed command immediate resuit 'is present in the Result Register. It is set by
8273 and reset when CPU reads the result.

The TxlRA is set by the 8273 when an interrupt result byte is placed in the TxlNT register. It is reset
when the CPU has read the TxlNT register.

Bit 3 RxlNT (Receiver Interrupt)
THE EXECUTION PHASE

RxlNT indicates that the receiver requires CPU attention. It is identical to RxlNT (pin 11) and is set by
the 8273 either upon good/bad completion of a
specified command or by Non-DMA data transfer. It
is reset only after the CPU has read the result byte
or has received a data byte from the 8273 in a NonDMA data transfer.

Upon accepting the last parameter, the 8273 enters
into the Execution Phase. The execution phase may
consist of ~ DMA or other activity, and mayor may
not require CPU intervention. The CPU intervention
is eliminated in this phase if the system utilizes DMA
for the data transfers, otherwise,. for non-DMA data
transfers, the CPU is interrupted by the 8273 via
TxlNT and RxlNT pins, for each data byte request.

Bit 2 TxlNT (Transmitter Interrupt)
The TxlNT indicates that the transmitter requires
CPU attention. It is identical to TxlNT (pin 2). It is set
by 8273 either upon good/bad completion of a specified command or by Non-DMA data transfer. It is
reset only after the CPU has read the result byte or
has transferred transmit data byte to the 8273 in a
Non-DMA transfer.

THE RESULT PHASE

Bit 1 RxlRA (Receiver Interrupt Result
Available)

To facilitate quick network software decisions, two
types of execution results are provided:
1. An Immediate Result
2. A Non-Immediate Result

During the result phase, the 8273 notifies the CPU of
the execution outcome of a command. This phase is
initiated by:
1. The successful completion of an operation
2. An error detected during an operation.

The RxlRA is set by the 8273 when an interrupt result byte is placed in the RxlNT register. It is reset
after the CPU has read the RxlNT register.

2-93

inter

8273

Early transmit interrupt
Frame transmit complete
DMA underrun
Clear to Send (CTS) error
Abort complete

0
0
0
0

0
0

1
0

210479-12

Figure 11. Tx Interrupt Result Byte Format

Immediate result is provided by the 8273 for commands such as Read Port A and Read Port B which
have information (CTS, CO, RTS, etc.) that the network software needs to make quick operational decisions.
A command which cannot provide an immediate result will generate an interrupt to signal the beginning
of the Result phase. The immediate results are provided in the Result Register; all non-immediate results are available upon device interrupt, through Tx
Interrupt Result Register Txl/R or Rx Interrupt Result Register Rxl/R. The result may consist of a onebyte interrupt code indicating the condition for the

interrupt and, if required, one or more bytes which
detail the condition.
Tx and Rx Interrupt Result Registers

The Result Registers have a result code, the three
high order bits 07-05 of which are set to zero for all
but the receive command. This command result contains a count that indicates the number of bits received in the last byte. If a partial byte is received,
the high order bits of the last data byte are indeterminate.
All results indicated. in the command summary must
be read during the result phase.

2-94

8273

INTERRUPT

r-:---

N~~g~AI
+

-----,

I
I DMA
I MODE

READ STATUS
REGISTER

I
I
I

I
I
r-______~Y~E=S_<

>-N_O____________~+

READ STATUS
REGISTER

DATA REQUEST
NON·DMA MODE
USE DACK + Ri'i OR
WRTO READ OR
WRITE DATA

YES

READ IIR
REGISTER

210479-13

Figure 12. Result Phase Flowchart-Interrupt Results

2·95

infe£

8273

AFTER COMMAND' PHASE COMPLETION (READ PORT A. PORT B)

READ RESULT
REGISTER

READ STATUS
REGISTER

210479-14

Figure 13. (Rx InterruplService)

DETAILED COMMAND DESCRIPTION
General
The 8273 HOLC/SOLC controller supports a comprehensive set of high level commands which allows
the 8273 to be readily used in full-duplex, half-duplex, synchronous, asynchronous and SOLC loop
configuration, with or without modems. These framelevel commands minimize CPU and software overhead. The 8273 has address and control byte buffers which allow the receive and transmit commands
to be used in buffered or non-buffered modes.
In buffered transmit mode, the 8273 transmits a flag
automatically, reads the Address and Control buffer
registers and· transmits the fields, then via OMA, it
fetches the information field. The 8273, having
transmitted the information field, automatically appends the Frame Check Sequence (FCS) and the
end flag. Correspondingly, in buffered read mode,
the Address and Control fields are stored in their
respective buffer registers and only Information
Field is transferred to memory.

Since Address/Control field extension is normally
done with software to maximize extension flexibility,
the 8273 does not create or operate upon contents
of the extended HOLC Address/Control fields. Extended fields are transparently passed by the 8273
to user as either interrupt results or data transfer
requests. Software must assemble the fields for
transmission and interrogate them upon reception.
However, the user can take advantage of the powerful 8273 commands to minimize CPU/Software
overhead and simplify buffer management in handling extended fields. For instance buffered mode
can be used to separate the first, two bytes, then
interrogate the others from buffer. Buffered mode is
perfect for a two byte address field.
The 8273 when programmed, recognizes protocol
characters unique to HOLC such as Abort, which is a
string of seven or more ones (01111111). Since
Abort character is the same as the GA (EOP) character used in SOLC Loop applications., Loop Transmit and Receive commands are not recommended
to be used in HOLC. HOLC does not support Loop
mode.

In non-buffered transmit mode, the 8273, transmits
the beginning flag automatically, then fetches and
transmits the Address, Control and Information
fields from the memory, appends the FCS character
and an end flag. In the non-buffered receive mode
the entire contents of a frame are sent to memory
with the exception of the flags and FCS.

Initialization Set/Reset Commands
These commands are used to manipulate data within the 8273 registers. The Set commands have a
single parameter which is a mask that corresponds
to the bits to be set. (They perform a logical-OR of
the specified register with the mask provided as a
parameter). The Register commands have a single
parameter which is a mask that has a zero in the bit
positions that are to be reset. (They perform a logical-ANO of the specified register with the mask).

HDLC Implementation
HOLC Address and Control field are extendable. The
extension is selected by setting the low order bit of
the field to be extended to a one, a zero in the low
order bit indicates the last byte of the respective
field.

2-96

intJ

8273

When one bit delay is set, 8273 retransmits the received data stream one bit delayed. This mode is
entered at a receiver character boundary, and
should only be used by Loop Stations.

RESET OPERATING MODE (CMD CODE 51)
A1 Ao 07· 06 05 04 03 02 01 00

~~~: ~
I

RESET ONE-BIT DELAY (CMD CODE 64)
Any mode switches set in CMO code 91 can be reset using this command by placing zeros in the appropriate positions.

A1 Ao 07 06 05 04 03 02 01 00

~~~: ~
I

(D5) HDLC MODE

The 8273 stops the one bit delayed retransmission
mode.

In HOLC mode, a bit sequence of seven ones
(01111111) is interpreted as as an abort character.
Otherwise, eight ones (011111111) signal an abort.

SET DATA TRANSFER MODE (CMD CODE 97)

A1 Ao 07 06 05 04 03 02 01

~~~: ~
I

~ ~ ~ ~ ~ ~ ~
I

(D4) EOP INTERRUPT MODE

When the data transfer mode is set, the 8273 will
interrupt when data bytes are required for transmission . or are available from a receive. If a transmit
interrupt occurs and the status indicates that there is
no Transmit Result (TxIRA = 0), the interrupt is a
transmit data request. If a receive interrupt occurs
and the status indicates that there is no receive result (RxIRA = 0), the interrupt is a receive data request.

RESET DATA TRANSFER MODE (CMD CODE
57)

A1 Ao 07 06 05 04 03 02 01 00

~~~: ~ ~
I

In EOP interrupt mode, an interrupt is generated
whenever an EOP character (01111111) is detected
by an active receiver. This mode is useful for the
implementation of an SOLC loop controller in detecting the end of a message stream after a loop poll.

(D3) TRANSMITTER EARLY INTERRUPT MODE
(Tx)
.The early interrupt mode. is specified to indicate
when the 8273 should generate an end of frame interrupt. When set, an early interrupt is generated
when the last data character has been passed to the
8273. If the user software responds with another
transmit command before the final flag is sent, the
final flag interrupt will not be generated and a new
frame will immediately begin when the current frame
is complete., This permits frames to be separated by
a single flag. If no additional Tx commands are provided, a final interrupt will follow.

If the Oata Transfer Mode is reset, the 8273 data
transfers are performed through the OMA requests
without interrupting the CPU.

NOTE:
In buffered mode, if a supervisory frame (no Information) Transmit command is sent in response to
an early Transmit Interrupt, the 8273 will repeatedly
transmit the same supervisory frame with one flag
in between, until a non-supervisory transmit is issued.

SET OPERATING MODE (CMD CODE 91)

: : I: 1~o I: 10: 1;1 ~41; I; 10: I~ I
I I· .

I 'L

Early transmitter interrupt can be used in buffered
mode by waiting for a transmit complete interrupt
instead of early Transmit Interrupt before issuing a
transmit frame command for a supervisory frame. '
See Figure 14.

FLAG STREAM MODE

1 .. PREF"RAME SYNC MODE

1 • BUFFERED MODE

1" EARLY INTERRUPT MODE

1 - EOP INTERRUPT MODE
, -HDLCMODE

210479-34

2-97

Intel

8273

(DO) FLAG STREAM MODE

Tx INTERRUPT PROCEDURE

TRANSMIT COMPLETION
(ODH)
INTERRUPT

OTHER

If this bit is set to a one, the following table outlines
the operation of the transmitter.
Transmitter State

Action

Idle

Send Flags Immediately.

Transmit or Transmit}
Transparent Active

Send Flags After the
Transmission Complete

Loop Transmit Active
1 Bit Delay Active

Ignore Command.
Ignore Command.

. If this bit is reset to zero the following table outlines
the operation of the transmitter
Action

Transmitter State

Sends Idles on Next
Character boundary.

IDLE
ND

Send Idles after the
Transmission
is Complete.

Transmit or Transmit- }
Transparent Active
Loop Transmit Active

Ignore Command.
Ignore Command.

1 Bit Delay Active

SET SERIAL 1/0 MODE (CMD CODE AD)

OTHER PROCESSING

210479-15

~.~

:::: I:I:I:I:I: I:I:I I I I

Figure 14

I, - NRZI MODE

If this bit is zero, the interrupt will be generated only
after the final flag has been transmitted.

1" TxC-Rxe
1

(02) BUFFERED MODE

=LOOP BACK TxD _RxO
210479-16

If the buffered mode bit is set to a one, the first two
bytes (normally the address (A) and control (C)
fields) of a frame are buffered by the 8273. If this bit
is a zero the address and control fields are passed
to and from memory.

RESET SERIAL 1/0 MODE (CMD CODE 60)
This command allows bits set in CMD code AO to be
reset by placing zeros in the appropriate positions.

~: I~' I~ I~ I~61 ~' I:' I~' I~21 ~' I~o I

(01) PREFRAME SYNC MODE
If this bit is set to a one the 8273 will transmit two
characters before the first flag of a frame.

(02) LOOP BACK

To guarantee sixteen line transitions, the 8273
sends two bytes of data (OO)H if NRZI is set or data
. (55)H if NRZI is not set.

If this bit is set to a one, the transmit data is internally routed to the receive data circuitry.

2-98

intJ

8273

(D1) TxC -

Receive Commands

RxC

nay

If this bit is set to a one, the transmit clock is interrouted to the receive clock circuitry. It is normally used with the loop back bit (02).

The 8273 supports three receive commands: General Receive, Selective Receive, and Selective Loop
Receive.

(DO) NRZI MODE

GENERAL RECEIVE (CMD CODE CO)

If this bit is set to a one, NRZI encoding and decoding of transmit and receive data is provided. If tJ:lis bit
is a zero, the transmit and receive data is treated as
a normal positive logic bit stream.

General receive isa receive mode in which frames
are received regardless of the contents of the address field.
A1 Ao 07 06 05 04 03 02 01 Do

NRZI encoding specifies that a zero causes a
change in the polarity of the transmitted signal and a
one causes no polarity change. NRZI is used in all
asynchronous operations. Refer to IBM document
GA27 -3093 for details.

Reset Device Command
A1

PAR:

LEAST SIGNIFICANT BYTE
OF THE RECEIVE BUFFER
LENGTH (BO)

PAR:

MOST SIGNIFICANT BYTE
OF RECEIVE
BUFFER LENGTH (B1)

1 1 1 1 0 1 01 0.1 0 1 0 1 0

Ao 07 06 05 04 03 02 01 Do

~~:: ~ ~ ~ ~ ~ ~'I ~ ~ ~
1

CMO:

I·

1: 1

, An 8273 reset command is executed by outputting a
(01)H followed by (OO)H to the reset register (TMR).
See 8273 AC timing characteristics for Reset pulse
specifications.
The reset command emulates the action of the reset
pin.
1) The modem control signals are forced high (inactive level).
2) The 8273 status register flags are cleared.
3) Any commands in progress are terminated immediately.
4) The 8273 enters an idle state until the next com-

mand is issued.
5) The Serial I/O and Operating Mode registers are
set to zero and OMA data register transfer mode
.
is selected.
6) The device assumes a non-loop SOLC terminal
role.

2-99

NOTES:
1. If buffered mode is specified, the RO, R1 receive
frame length (result) is the number of data bytes received.
2. If non-buffered mode is specified, the RO, R1 receive frame length (result) is the number of data
bytes received plus two (the count includes the address and control bytes):
3. The frame check sequence (FCS) is not transferred to memory.
4. Frames with less than 32 bits between flags are
ignored (no interrupt generated) if the buffered
mode is specified.
5. In the non-buffered mode an interrupt is generated when a less than 32 bit frame is received, since
data transfer requests have occurred.
6. The 8273 receive is always disabled when an
Idle is received after a valid frame. The CPU module must issue a receive command to re-enable the
receiver.
7. The intervening ABORT character between a final flag and an IDLE does not generate an interrupt.
8. If an ABORT Character is not preceded by a flag
and is followed by an IDLE, an interrupt will be generated for the ABORT followed by an IDLE interrupt
one character time later. The reception of an
ABORT will disable the receiver.

Intel

8273

SELECTIVE RECEIVE (CMD CODE C1)

RECEIVE DISABLE (CMD CODE 5)

CMD:

A1 AO 07 06 05 04 03 02 01 Do
0 0 111101010101011

PAR:

Terminates an active receive command immediately.
A1 Ao D7 06 D5 04 03 02 D1 Do

LEAST SIGNIFICANT BYTE
OF THE RECEIVE
BUFFER LENGTH (BO)

CMD:
PAR:

I0 I0 I1 I1 I0 I0 I0 I1 I0 I1
NONE

PAR:

MOST SIGNIFICANT BYTE
OF RECEIVE
BUFFER LENGTH (B1)

PAR:

RECEIVE FRAME ADDRESS
MATCH FIELD ONE (A1)

The 8273 supports three transmit commands:
Transmit Frame, Loop Transmit, Transmit Transparent.

PAR:

RECEIVE FRAME ADDRESS
MATCH FIELD TWO (A2)

TRANSMIT FRAME (CMD CODE C8)

Transmit Commands

A1 Ao 07 06 05 04 D3 02 01
Selective receive is a receive mode in which frames
are ignored unless the address field matches any
one of two address fields given to the 8273 as parameters.
'

CMD:

PAR:

LEAST SIGNIFICANT BYTE OF
FRAME LENGTH (LO)

111101011101010

When selective receive is used in HDLC the 8273
looks at the first character, if extended, software
must then decide if the message is for this unit.

PAR:

MOST SIGNIFICANT BYTE OF
FRAME LENGTH (L 1)

PAR:

O·

ADDRESS FIELD OF TRANSMIT
FRAME (A)

SELECTIVE LOOP RECEIVE (CMD CODE C2).

PAR:

CONTROL FIELD OF TRANSMIT
FRAME (C)

A1 Ao 07 06 05 04 03 02 01
CMD:

PAR:

111101010101110

Transmits one frame including: initial flag, frame
check sequence, and the final flag.

LEAST SIGNIFICANT BYTE
OF THE RECEIVE
BUFFER LENGTH (BO)

PAR:

MOST SIGNIFICANT BYTE
OF RECEIVE
BUFFER LENGTH (B1)

PAR:

RECEIVE FRAME ADDRESS
MATCH FIELD ONE (A1)

PAR:

RECEIVE FRAME ADDRESS
MATCH FIELD TWO (A2)

If the buffered mode is specified, the LO, L1, frame
length provides as a parameter is the length of the
information field and the address and control fields
must be input.
In unbuffered mode the frame length provided must
be the length of the information field plus two and
the add~ess and control fields must be the. first two
bytes of data. Thus only the frame length bytes are
required as parameters.

Selective loop receive operates like selective receive except that the transmitter is placed in flag
stream mode automatically after detecting an EOP
(01111111) following a valid received frame. The
one bit delay mode is also reset at the end of a
selective loop receive.

2-100

intJ

8273

After an abort character (eight contiguous ones) is
transmitted, the transmitter reverts to sending flags
or idles as a function of the flag stream mode specified.

LOOP TRANSMIT (CMD CODE CAl

Ao D7 D6 D5 D4 D3 D2 D1

CMD:

PAR:

111101011101110
LEAST SIGNIFICANT BYTE OF
FRAME LENGTH (LO)

ABORT LOOP TRANSMIT (CMD CODE CE)

A1 Ao D7 D6 D5 D4 D3 D2 D1 Do

MOST SIGNIFICANT BYTE OF
FRAME LENGTH (L1)

CMD:

PAR:

ADDRESS FIELD OF TRANSMIT
FRAME (A)

PAR:

CONTROL FIELD OF TRANSMIT
FRAME (C)

PAR:

LEAST SIGNIFICANT BYTE OF
FRAME LENGTH (LO)

PAR:

MOST SIGNIFICANT BYTE OF
FRAME LENGTH (L 1)

A1 Ao D7 D6 D5 D4 D3 D2 01

CMD:
PAR:

I0 I0 I 1 I 1 I0 I0 I 1 I 1 I 0 I 1 I
NONE

The transmitter reverts to sending flags or idles as a
function of the flag stream mode specified.

Modem Control Commands

When read Port A or Port B commands are executed
the result of the command is returned in the result
register. The Bit Set Port B command requires a parameter that is a mask that corresponds to the bits
to be set. The Bit Reset Port B command requires a
mask that has a zero in the bit positions that are to
be reset.
' '

ABORT TRANSMIT TRANSPARENT (CMD CODE
CD)

The modem control commands are used to manipulate the modem control ports.

TRANSMIT TRANSPARENT (CMD CODED C9)

A1 Ao D7 D6 D5 D4 D3 D2 D1

NONE

After a flag is transmitted the transmitter reverts to
one bit delay mode.

Transmits one frame in the same manner as the
transmit frame command except:
1) If the flag stream mode is not activE! transmission
will begin after a received EOP has been converted to a flag.
2) If the flag stream mode is active transmission will
begin at the next flag boundary for buffered mode
or at the third flag boundary for non-buffered
mode.
3) At the end of a loop transmit the one-bit delay
mode is entered and the flag stream mode is reset.

CMD:

I0 I0 I1 I1 I0 I0 I1 I1 I1 I0 I

1 1 1 1 0 1 0 11 1 0 1 0 1 1

The 8273 will transmit a block of raw data without
protocol, i.e., no zero bit insertion,flags, or frame
check sequences.

READ PORT A (CMD CODE 22)

A1 Ao D7 D6 05 0 4 03 02 0 1 Do

CMO:
PAR:

I0 I0 I0 I0 I I0 I0 I0 I I0 I
NONE

Abort Transmit Commands
An abort command is supported for each type of
transmit command. The abort commands are ignored if a transmit command is not in progress.

PAR:

A1 Ao 07 06 05 04 03 D2 D1

CMO:
PAR:

ABORT TRANSMIT FRAME (CMD CODE CC)
A1 Ao D7 D6 D5 D4 D3 D2 D1 Do

CMD:

READ PORT B (CMD CODE 23)

I0 I0 I1 I1 I0 I0 I1 I1 I0 I0 I
NONE

2-101

I0 I0 I0 I0 I 1 I0 I0 I0 I 1 I 1 I
NONE

8273

SET PORT B BITS (CMD CODE A3)

(Do) REQUEST TO SEND

This command allows user defined Port B pins to be
set.

This is a dedicted 8273 modem control signal, and
reflects the same logical state of RTS pin.

: I' 101010I' I'I 1

RESET PORT B BITS (CMD CODE 63)

::: 1: 1~I 1:

This command allows Port B user defined bits to be
reset.

RTS - REQUEST TO SEND

USER DEFINED
FLAG DETECT

:::'1: 1~ 1~ 1:

210479-35

(05) FLAG DETECT
This bit can be used to set the flag detect pin. However, it will be reset when the next flag is detected.

I' 101 01 01'1'1I

RTS - REQUEST TO SEND

USER DEFINED

FLAG DETECT

210479-36

This command allows Port B (04-01) user defined
bits to be reset. These bits correspond to Output
Port pins (PB4-PB1).

(04-01) USER DEFINED OUTPUTS
These bits correspond to the state of the PB4-PB1
output pins.

8273 Command Summary
Command Description
Set One Bit Delay

Command

HEX
A4

Results

Parameter
Set Mask

None

Reset One Bit Delay

Reset Mask

None

Set Data Transfer Mode

Set Mask

None

Reset Data Transfer Mode

Reset Mask

None

Set Operating Mode

Set Mask

None

Reset Operating Mode

Reset Mask

None

Set Serial 110 Mode

Set Mask

None

Result
Port

Completion
Interrupt

No
No
No
No
No
No
No

Reset Serial 1/0 Mode

Reset Mask

None

General Receive

BO,B1

RIC,RO,R1,(A,C)(2)

RXI/R

Yes

Selective Receive

BO,B1,A1,A2

RIC,RO,R1,(A,C)(2)

RXIIR

Yes

Selective Loop Receive

BO,B1,A1,A2

RIC,RO,R1,(A,C)(2)

RXI/R

Yes

Receive Disable

None

Transmit Frame

LO,L 1,(A,C)(1)

TIC

TXI/R

Yes

Loop Transmit

LO,L 1,(A,C)(1)

TIC

TXI/R

Yes

Transmit Transparent

LO,L1

TIC

TXI/R

Yes

Abort Transmit Frame

None

TIC

TXI/R

Yes

2-102

8273

8273 Command Summary (Continued)
Command
HEX

Command Description

Parameter

Results

Result
Port

Completion
Interrupt

Abort Loop Transmit

None

TIC

TXI/R

Yes

Abort Transmit Transparent

None

TIC

TXI/R

Yes

Read PortA

None

Port Value

Result

Read Port B

None

Port Value

Set Port B Bit

Set Mask

None

Reset Port B Bit

Reset Mask

None

NOTES:
1. Issued only when in buffered mode.
2. Read as results only in buffered mode.

C- Control field of received frame. If nonbuffered mode is specified this result is
not provided.

8273 Command Summary Key
80- Least significant byte of the receiver buffer length.
81- Most significant byte of the receive buffer
length.

RXI/R- Receive interrupt result register.
TXI/R- Transmit interrupt result register.

LO- Least significant byte of the Tx frame
length.

RO- Least significant byte of the length of the
frame received.

L 1-:- Most significant byte of the Tx frame
length.
A 1- Receive frame address match field one.
A2- Receive frame address match field two.
A- Address field of received frame. If nonbuffered mode is specified, this result is
not provided.

R1- Most significant byte of the length of the
frame received.

COMMAND

RIC- Receiver interrupt result code.
TIC- Transmitter interrupt result code.

GENERAL
RECEIVE

IRQ. R,I

DATA IN

DMA REQUESTS
DATA

~~ERRUPTS

_________________

t t t

~:A:::;,=:JC--.I.-I-,-----------

NON·BUFFERED MODE
FRAME
CPUINTERRUPTS _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _C_O_M_P_L_ET_E_~_ _ _ _ _ _~_

210479-17

Figure 15. Typical Frame Reception
NOTE:
In order to ensure proper operation to the maximum baud rate, Receive commands or Read/Write Port commands should
be written only when either the transmitter or the receiver is inactive. In full duplex systems, it is recommended that these
commands be issued after servicing a transmitter interrupt but before a new transmit command is issued. When operating in
full Duplex (active transmitter or receiver) with commands, the maximum data rate decreases to 49K Baud.

2-103

inter

8273

LAST PARAMETER
OF Tx COMMAND

i-2BYTES-j

.1.!.....,Jl

RTS _ _

CTS

-----_........

DRQ ______________________________~t~ll__~t~12~~tl~a______________________________________
BUFFER MODE

INT

EARLY
TxlNT

FINAL
TxlNT

210479-18

Figure 16a. Typical Frame Transmission, Buffered Mode

LAST PARAMETER

~3 BYTES----i

.J.'_...J!

RlS _ _

CTS ________________~

DRQ ________________

~tA__~tC__~tl~1~tl~2~tl~3__________________________

NON·BUFFER MODE
INT
EARLY
TxlNT

FINAL
TxlNT

210479-19

Figure 16b. Typical Frame Transmission, Non-Buffered Mode

2-104

infef

8273

I
)

MEMORIES

I
\

SYSTEM BUS
~

"'DBO_7
MEMR
lOW
MEMW
lOR
CS
HRO
HACK

A o,A 1
OB O_7
RD
WR
CS
TXINT
RXINT

RXC
RXD
TXC
TXD

TKORQ
8257

DMA
CONTROLLER

TxDACK

MODEM

8273

RxORO

RxDACK

MODEM CONTROLS
~

210479-20

Figure 17. 8273 System Diagram

WAVEFORMS
COMMAND PHASE
WR

~--__ PARA~ETER

i
CBSY

---'

r------.

I\.-_-JI

n ---:

I--T2~

:i---T5--i
~'-~---

I------ T3-+1

CPBF

~T4-i

I
I

210479-21

Table 2. Command Phase Timing (Full Duplex)
Symbol

Buffered

Timing Parameter

Non-Buffered

Min

Max

Min

Max

Unit

Between Command & First Parameter

756

857

tcy

Between Consecutive Parameters

604

705

tcy

Command Parameter Buffer Full Bit
Reset after Parmeter Loaded

604

705

tcy

Command Busy Bit Reset after Last
Parameter

128

702

128

803

tcy

CPBF Bit Reset after Last Parameter

604

705

tcy

2-105

8273

WAVEFORMS (Continued)
RECEIVER INTERRUPT
__ \

LAST
INTERRRUPT RESUL'l

\'----

RxlRA

---+j T2
RxlNT

r--

\'--210479-'22

Table 3. Receiver Interrupt Result Timing
Symbol

Timing Parameter (Clock Cycles)

T1
T2

RxlRA Bit Set after RIC Read
RxlNT Goes Away after Last Int. Result
Read

Buffered

Non-Buffered

Min

Max

Min

Max

18
16

29
27

18
16

29
27

Unit
tcy
tcy

TRANSMIT INTERRUPT
AD

TxlRA

TxlNT

---'
210479-23

Table 4. Transmit Interrupt Result
Symbol

Buffered

Timing (Clock Cycle)

Min
T1

TxlNT Inactive after Int. Results Read

2-106

I
I

Non-Buffered

Max

Min

Max

353

454

Unit
tcy

intJ

8273

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Ambient Temperature Under Bias ....•. O·C to 70·C
Storage Temperature .......... -6S·C to

+ 1S0·C

Voltage on Any Pin With
Respectto Ground .............. - O.SV to

+ 7V

Power Dissipation ........................ 1 Watt

D.C. CHARACTERISTICS 8273
Symbol
Vil

Parameter
. Input Low Voltage

(TA

= O·C to 70·C. Vee = + S.OV ± S%)

Min

Max

Unit

-O.S

0.8

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

IlL

Input Load Current

±10

IOFL

Output Leakage Current

±10

/LA

lee

Vee Supply Current

180

rnA

CAPACITANCE 8273
Symbol

(TA

2.0

+ O.S

VIH

Vee

O.4S

2S·C. Vee

Parameter·

V
V

2.4

/LA

= 2.0 rnA for Data Bus Pins
= 1.0 rnA for. Output Port Pins
= 1.6 rnA for All Other Pins
IOH = - 200 /LA for Data Bus Pins
IOH = -100 /LA for All Other Pins
VIN = Vee to OV
VOUT = VeetoO.4SV
IOL
IOl
IOl

0V)
Unit

CIN

CliO

I/O Capacitance

Unmeasured Pins
Returned to GND

Max

Unit

Test Conditions

1000

(TA

Typ

Test Conditions

Max

Input Capacitance

A.C. CHARACTERISTICS

Min

GND

Test Condition.s

= 1 MHz

= O·C to 70·C. Vee = + S.OV ± S%)

CLOCK TIMING (8273)
Symbol

Parameter

Min

tey

Clock

2S0

Typ

tel

Clock Low

120

tcH

Clock High

120

2-107

64K Baud Max
Operating Rate

Intel

8273

A.C. CHARACTERISTICS 8273

(TA

O°Cto 70°C, VCC

+5.0V

± 5%)

READ CYCLE
Symbol

Parameter

Min

Max

Unit

Test Conditions

tAC

Select Setup to RD

(Note 2)

tCA

Select Hold from RD

(Note 2)

tRR

RD Pulse Width

250

tAD

Data Delay from Address

300

(Note 2)

200

CL = 150 pF, (Note 2)

100

CL = 20 pF For Minimum;
.150 pF for Maximum

tRO

Data Delay from RD

tOF

Output Float Delay

toc

DACK Setup to RD

tco

DACK Hold from RD

tKO

Data Delay from DACK

300

WRITE CYCLE
Symbol

Parameter

Min

Max

Unit

tAC

Select Setup to WR

tCA

Select Hold from WR

tww

WR Pulse Width

250

tow

Data Setup to WR

150

two

Data Hold from WR

toc

DACK Setup to WR

. 25

tco

DACK Hold from WR

Test Conditions

DMA
Symbol
tca

Parameter

Min

Request Hold from WR or RD
(for Non-Burst Mode)

Max

Unit

200

Max

Unit

Test Conditions

OTHER TIMING

Symbol

Parameter

tRSTW

Reset Pulse Width

Input Signal Rise Time

Input Signal Fall Time

tRSTS

Reset to First IOWR

tCY32

32X Clock Cycle Time

tCL32

32X Clock Low Time

ICH32

32X Clock High Time

tOPLL

DPLL Output Low

Min
10

tcy
20

tCY

13.02xtcy

4xtCY

1 xtcy-50

2-108

Test Conditions

8273

A.C. CHARACTERISTICS 8273 (TA

O°C to io°c, vcc

+ 5.0V

± 5%) (Continued)

OTHER TIMING (Continued)
Parameter

Symbol

Min

Max

Unit

tOCL

Data Clock Low

1 xtCy-50

tOCH

Data Clock High

2xtCY

tOCY

Data Clock

tro

Transmit Data Delay

tos

Data Setup Time

200

tOH

Data Hold Time

100

tFLO

FLAG DET Output Low

8xtCY ± 50

Test Conditions

62.5xtCY
200

(Note 3)

NOTES:
1. All timing measurements are made at the reference voltages unless otherwise specified: Input "1" at 2.0V, "0" at 0.8V;
Output "1" at 2.0V, "0" at 0.8V.
2. tAD, tRD, tAC, and tCA are not concurrent specs.
3. If receive commands or Read/Write Port commands are issued while both the transmitter and receiver are active, this
specification will be 81.5 TCY min.

A.C. TESTING INPUT, OUTPUT WAVEFORM

"=X

2.0

0.8

2.0

TEST POINTS

0.8

0.45

A.C. TESTING LOAD CIRCUIT

ic'

DEVICE
UNDER
TEST

210479-24

A.C. Testing: Inputs are driven at 2.4V for a logic "1" and 0.45V
for a logic "0". Timing measurements are made at 2.0V for a logic
"1" and O.SV for a logic "a".

150pF

210479-25
CL ~ 150pF
CL Includes Jig Capacita.nce

WAVEFORMS
READ

OACK

=:)

1<.
IDC

ICD

f---tA~-

DATA BUS

IRR

Ii--ICA-l

IRa

-- - 1------ - -lAD
IKD

2-109

~
I ~_IDF-~

_______

210479-26

8273

WAVEFORMS (Continued)
WRITE

DACK

ID~

J<.

-.-Jl

I--tAC-~

I--tCA

'WW

--l

DATA BUS

,______ two---..J

'ow

210479-27

DMA
ORO

r'co==:}

DACK

RDORWR

CHIPCLQCK

k~3
'ICLLICH

32XCLQCK

L_£J

/
210479-28

TRANSMIT

- . - - tOCL

-----1
0-

TxD

....

I+-

tocv - _. __ ..

tOCH

.. .

--_

~
.... tTO--

210479-29

2-110

inter

8273

WAVEFORMS (Continued)
RECEIVE

......

~210479-30

DPLL OUTPUT

210479-31

FLAG DETECT OUTPUT

210479-1

2-111

8274
MULTI-PROTOCOL SERIAL CONTROLLER (MPSC)
• Asynchronous, Byte Synchronous and
Bit Synchronous Operation -

• Byte Synchronous:
-- Character Synchronization, Int. or
Ext.
_
- One or Two Sync Characters
- Automatic CRC Generation and
Checking (CRC-16)
-IBM Bisync Compatible

• Two Independent Full Duplex
Transmitters and Receivers
• Fully Compatible with 8048, 8051, 8085,
8088, 8086, 80188 and 80186 CPU's;
8257 and -8237 DMA Controllers; and
8089 I/O Proc.

• Bit Synchronous:
- SDLC/HDLC Flag Generation and
Recognition
.....; 8 Bit Address Recognition
- Automatic Zero Bit Insertion and
Deletion
- Automatic CRC Generation and
Checking (CCITT-16)
- CCITT X.25 Compatible

• 4 Independent DMA Channels
• Baud Rate: DC to 880K Baud
• Asynchronous:
_
- 5-8 Bit Character; Odd, Even, or No
Parity; 1, 1.5 or 2 Stop Bits
-Error Detection: Framing, Overrun,
and-Parity

• Available in EXPRESS and Military
The Intel 8274 Multi-Protocol Series Controller (MPSC) is designed to interface High Speed Communications
Lines using Asynchronous, IBM Bisync, and SOLC/HOLC protocol to Intel microcomputer systems. It can be
interfaced with Intel's MCS-48, -85, -51; iAPX-86, -88, -186 and -188 families, the 8237 OMA Controller, or the
8089 1/0 Processor in polled, interrupt driven, or_ OMA driven modes of operation.
The MPSC is a 40 pin device fabricated using Intel's High Performance HMOS Technology.

DBO_1

CLK'----_,

1IERf'-----,

r'<:~===:~

CONTROL

CHANNELl.
LOQIC

CHANNELl.
READ
REGISTERS
RXOA
I1<:T=====tC~H~AN~NE~L:AJ;:~ .,C.

IJII/RlIDRQ.

INt_--2

I
D.
0

COMMAND/STATUS
POINTER

w:
:I
----JI I
'--lw
o-Iw'---____--'1 I

~--I

R: 0:

R
L - -_
___

Msa

1-----.1

o--Jw

1-----lw

o--Jw
.--Jw

Lsa

Msa

LSB

Wrfte

A~I.I."

170102-3

Figure 3. Command/Status Register Architecture (each serial channel)

2-118

inter

8274

Asynchronous Mode Register Setup

00 Rx 5 b/char
01 Rx 7 b/char
10 Tx 6 b/char
11 Rx 8 b/char

WR3

00
01
10
11

WR4

OTR

WR5

AUTO
ENABLE

Rx
ENABLE

EVENI
000
PARITY

PARITY
ENABLE

RTS

X1 Clcck
X16 Clock
X32 Clock
X64 Clock
00
01
10
11

Tx s: 5 b/char
Tx 7 b/char
Tx 6 b/char
Tx 8 b/char

01
10
11

SEND
BREAK

SYNCHRONOUS OPERATIONMONOSYNC, BISYNC

1 STOP BIT
1% STOP BITS
2 STOP BITS

Tx
ENABLE

Transmit Set-Up-Monosync, Bisync

General
The MPSC must be initialized with the following parameters: odd or even parity (WR4; 01, ~O), X1
clock mode (WR4; 07, 06), 8- or 16-bit sync character (WR4; 05, 04), CRC polynomial (WR5; 02),
Transmitter Enable (WR5; 03), interrupt modes
(WR1, WR2), transmit character length (WR5; 06,
05) and receive character length (WR3; 07, 06).
WR4 parameters must be written before WR1, WR3,
WR5, WR6 and WR7.
The data is transmitted on the falling edge of the
Transmit Clc:::k, (TxC) and is received on the rising
edge of Receive Clock (RxC). The X1 clock is used
for both transmit and receive operations for all three
sync modes: Mono, Bi and External.

Transmit data is held high after channel reset, or if
the transmitter is not enabled. A break may be programmed to generate a spacing line that begins as
soon as the Send Break (WR5; 04) bit is set. With
the transmitter fully initialized and enabled, the default condition is continuous transmission of the 8- or
16-bit sync character.
Using interrupts for data transfer requires that the
Transmit InterruptiOMA Enable bit (WR1; 01) be
set. An interrupt is generated each time the transmit
buffer becomes empty. The interrupt can be satisfied either by writing another character into the
transmitter or by resetting the Transmitter Interrupti
OMA Pending latch with a Reset Transmitter Inter-

Synchronous Mode Register Setup-Monosync, Bisync

WR3

00 Rx 5 b/char
01 Rx7 b/char
10 Tx 6 b/char
11 Rx 8 b/char

WR4

WR5

OTR

0
00
01
10
11

05
AUTO
ENABLE
00
01
11

04
ENTER
HUNT
MODE

8 bit Sync
16 bit Sync
Ext Sync

Tx s: 5 bl char
Tx 7 b/char
Tx 6 b/char
Tx 8 b/char

SEND
BREAK

2-119

RxCRC
ENABLE

SYNC
CHAR
LOAD
INHIBIT

Rx
ENABLE

EVENI
ODD
PARITY

PARITY
ENABLE

Tx
ENABLE

1
(SELECTS
CRC-16)

RTS

TxCRC
ENABLE

intJ

8274

rupt/OMA Pending Command (WRO; OS, 04, 03). If
nothing more is written into the transmitter, there
can be no further Transmit Buffer Empty interrupt,
but this situation does cause a Transmit Underrun
condition (RRO; 06).

The Transmit' CRC Enable bit can be changed on
the fly any time in the message to include or exclude
a particular data character from CRC accumulation.
The Transmit CRC Enable bit should be in the de- '
sired state when the data character is loaded into
the transmit shift register. To ensure this bit in the
proper state, the Transmit CRC Enable bit must be
issued before sending the data character to the
MPSC.

Data Transfers using the ROY signal are for soft)/'Iare controlled data transfers such as block moves.
ROY tells the CPU that the MPSC is not ready to
accept/provide data and that the CPU must extend
the output/input cyCle. OMA data transfers use the
TxORQ AlB signals-which indicate that the transmit
buffer is empty, and that the MPSC is ready to accept the next data character. If the data character is
not loaded into the MPSC by the time the transmit
shift register is empty, the MPSC enters the Transmit Underrun condition.

Transmit Transparent Mode. Transparent mode
(Bisync protocol) operation is made possible by the
ability to change Transmit CRC Enable on the fly
and by the additional capability of inserting 16 bit
sync characters. Exclusion of OLE characters from
CRC calculation can be achieved by disabling CRC
calculation immediately preceding the OLE character transfer to the MPSC.

The MPSC has ty.Io programmable options for solving the transmit underrun condition: it can insert
sync characters, or it can .send the CRC characters
generated so far, followed by sync characters. FolloWing a chip or channel reset, the Transmit Underrun/EOM status bit (RRO; 06) is in a set condition
allowing the insertion of sync characters when there
is .no data to send .. The CRC is not calculated on
these automatically. inserted sync characters. When
the CPU detects the end mesSage, a Reset Transmit
Underrun/EOM command can be issued. This allows CRC to be sent when .the transmitter has no
data to send.

In the transmit mode, the transmitter always sends
the programmed number of sync bit,S (8 or 16) (WR4;
OS, 04). When in the Monosyncmode, the transmitter sends from WR6 and the receiver compares
against WR7. One or two CRC polynomials, CRC 16
or SOLC, may be used with synchronous modes. In
the transmit initialization process, the CRC generator is initialized by setting the Reset Transmit CRC
Generator command (WRO; 07; 06).

In the case of sync insertion, an interrupt is generated only after the fil'st automatically inserted sync
character has been loaded in the Transmit Shift
Register. The status register indicates the Transmit
Underrun/EOM bit and the Transmit Buffer Empty
bit are set.
In the case of CRC insertion, the Transmit Underrun/EOM bit is set and the Transmit Buffer Empty bit
is reset while CRC is being sent. When CRC has
been completely sent, the Transmit Buffer Empty
status bit is set and an interrupt is generated to indicate to the CPU that another message can begin
(this interrupt occurs because CRC has been sent
and sync has been loaded into the. Tx Shift Register). If no more messages are to be sent, the program can terminate transmission by resetting RTS,
and disabling the transmitter (WRS; 03).
Bisync CRC Generation. Setting the Transmit CRC
enable bit (WRS; DO) indicates CRC accumulation
when the program' sends the first data character to
the MPSC. Although the MPSC automatically transmits up to two sync characters (16 bit sync), it is
.wise to send a few more sync characters ahead of
the message (before enabling Transmit CRC) to ensure synchronization at the receiving end.

The External/Status interrupt (WR1; ~O) mode can
be used to monitor the status of the CTS input as
well as the Transmit Underrun/EOM latch. Optionally, the Auto Enable (WR3; 05) feature can be used
to enable the transmitter when CTS is active. The
first data transfer to the MPSC can begin when the
External/Status interrupt (CTS (RRO; 05) status bit
set) occurs tollowing the Transmit Enablecornmand
(WRS; 03).

Receive
After a channel reset, the receiver is in the Hunt
phase, during which the MPSC looks for character
synchronization. The Hunt begins only when the receiver isanabled and data transfer begins only when
character synchronization has been achieved. If
character synchronization is lost, the hunt phase can
be re-entered by writing the Enter Hunt Phase (WR3;
04) bit. The assembly of received data continues
until the MPSC is reset or until the receiver is disabled (by command or by CD while in the Auto Enables mode) or until the CPU sets the Enter Hunt
Phase bit. Under program control, all the leading
sync characters of the message can be inhibited
from loading the receive buffers by setting the Sync
Character Load Inhibit(WR3; 01) bit. After character
synchronization is achieved the assembled characters are transferred to the receive data FiFO. After

2-120

inter

8274

receiving the first data character, the Sync Character Load Inhibit bit should be reset to zero so that all
characters are received, including the sync characters. This is important because the received CRC
may look like a sync character and not get received.
Oata may be transferred with or without interrupts.
Transferring data without interrupts is used for a
purely polled operation or for off-line conditions.
There are two interrupt modes available for data
transfer: Interrupt on First Character Only and Interrupt on Every Character.
Interrupt on First Character Only mode is normally
used to start a polling loop, a block transfer sequence using ROY to synchronize the CPU to the
incoming data rate, or a OMA transfer using the
RxORQ signal. The MPSC interrupts on the first
character and thereafter only interrupts after a Special Receive Condition is detected. This mode can
be reinitialized using the Enable Interrupt On Next
Receive Character (WRO; 05, 04, 03) command
which allows the next character received to generate an interrupt. Parity Errors do not cause interrupts, but End of Frame (SOLC operation) and Receive Overrun do cause interrupts in this mode. If
the external status interrupts (WR1; 00) are enabled
an interrupt may be generated any time the CO
changes state.

modes. The Special Receive Condition interrupt is
caused by the Receive Overrun (RR1; 05) error condition. The error status reflects an error in the current word in the receive buffer, in addition to any
Parity or Overrun errors since the last Error Reset
(WRO; 05, 04, 03). The Receive Overrun and Parity
error status bits are latched and can only be reset by
the Error Reset (WRO; 05, 04, 03) command.
The CRC check result may be obtained by checking
for CRC bit (RR1; 06). This bit gives the valid CRC
result 16 bit times after the second CRC byte has
been read from the MPSC. After reading the second
CRC byte, the user software must read two more
characters (may be sync characters) before checking for CRC result in RR 1. Also for proper CRC computation by the receiver, the user software must reset the Receive CRC Checker (WRO; 07, 06) after
receiving the first valid data character. The receive
CRC Enable bit (WR3; 03) may also be enabled at
this time.

SYNCHRONOUS OPERATION-SDLC
General

Interrupt On Every Character mode generates an interrupt whenever a character enters the receive
buffer. Errors and Special Receive Conditions generate a special vector if the Status Affects Vector
(WR1 B; 02) is selected. Also the Parity Error may be
programmed (WR1; 04, 03) not to generate the special vector while in the Interrupt On Every Character
mode.

Like the other synchronous operations the SOLC
mode must be initialized with the following parameters: SOLC mode (WR4; 05, 04), SOLC polynomial
(WR5; 02), Request to Send, Oata Terminal Ready,
transmit character length (WR5; 06, 05), interrupt
modes (WR1; WR2), Transmit Enable (WR5; 03),
Receive Enable (WR3; 00), Auto Enable (WR3; 05)
and External/Status Interrupt (WR1; 00). WR4 parameters must be written before WR1, WR3, WR5,
WR6 and WR7.

The Special Receive Condition interrupt can only occur while in the Receive Interrupt On First Character
Only or the Interrupt On Every Receive Character

The Interrupt modes for SOLC operation are similar
to those discussed previously in the synchronous
operations section.

Synchronous Mode Register Setup-SOLC/HOLC

WR3

WR4

WR5

00 Rx 5 b/char
01 Rx 7 b/char
10 Rx 6 b/char
11 Rx 8 b/char
0

OTR

AUTO
ENABLES

ENTER
HUNT
MOOE

Rx
CRC
ENABLE

AOORESS
SEARCH
MOOE

Tx
ENABLE

0
(SELECTS
SOLC/HOLC
CRG)

RTS

Tx
CRC
ENABLE

1
0
(SELECTS SOLC/
HOLCMOOE)

00 Tx ,,; 5 b/char
01 Tx 7 b/char
10 Tx 6 b/char
11 Tx 8 b/char

SENO
BREAK

2-121

Intel

8274

The MPSC can be programmed to receive all frames
or it can be programmed to the Address Search
Mode. In the Address Search Mode, only frames
with addresses that match the value in WR6 or the
global address (OFFH) are received by the MPSC.
Extended address recognition must be done by the
microprocessor software.

Transmit
After a channel reset, the MPSC begins sending
SOLC flags.
Following the flags in an SOLC operation the 8-bit
address field, control field and information field may
be sent to the MPSC by the microprocessor. The
MPSC transmits the Frame Check Sequence using
the Transmit Underrun feature. The MPSC automatically inserts a zero after every sequence of 5 consecutive 1's except when transmitting Flags or
Aborts.

The control and information fields are received as
data.
SOLC/HOLC CRC calculation does not have an 8bit delay, since all characters are included in the calculation, unlike Byte Synchronous Protocols.

SOLC-like protocols do not have provision for fill
characters within a message. The MPSC therefore
automatically terminates an SOLC frame when the
transmit data buffer and output shift register have no
more bits to send. It does this by sending the two
bytes of CRC and then one or more flags. This allows very high-speed transmissions under OMA or
CPU control without requiring the CPU to respond
quickly to the end-of-message situation.

Reception of an abort sequence (7 or more 1's) will .
cause the Break/Abort bit (RRO; 07) to be set and
will cause an External/Status interrupt, if enabled.
After the Reset External/Status Interrupts Command has been issued, a second interrupt will occur
at the end of the abort sequence.

MPSC
After a reset, the Transmit Underrun/EOM status bit
is in the set state and prevents the insertion of CRC
characters during the time there is no data to send.
Flag characters are sent. The MPSC begins to send
the frame when data is written into the transmit buffer. Between the time the first data byte .is written,
and the end of the message, the Reset Transmit
Underrun/EOM (WRO; 07, 06) command must be
issued. The Transmit Underrun/EOM status bit
(RRO; 06) is in the reset state at the end of the
message which automatically sends the CRC characters.

Detailed Command/Status Description
GENERAL

The MPSC supports an extremely flexible set of serial and system interface modes.
The system interface to the CPU consists of 8 ports
or buffers:

CS A1 Ao

Th'e MPSC may tie programmed to issue a Send
Abort command {WRO; 05, 04, 03). This command
causes at least eight 1's out less than fourteen 1's to
,be sent before the line reverts to continuous flags.

0
0
0
0

Read Operation

0 Ch. A Data Read

Write Operation
Ch. A Data Write

1 0 Ch. A Status Read Ch. A Command/Parameter
0 1 Ch. B Data Read Ch. B Data Write
1 1 Ch. B Status Read Ch. B Command/Parameter

1 X X High .Impedance

High Impedance

Receive
After initialization, the MPSC enters the Hunt phase,
and remains in the Hunt phase until the first Flag is
received. The MPSC never again enters the Hunt
phase unless the microprocessor writes the Enter
Hunt command. The MPSC will also detect flags
separated by a single zero. For example, the bit pattern 011111101111110 will be detected as two
flags.

Oata buffers are addressed by Al = 0, and Command ports are addressed by A1 = 1.
COMMAND/STATUS DESCRIPTION

The following command and status bytes are used
during initialization and execution phases of operation. All Command/Status operations on the two
channels are identical, and independent, except
where noted.

2-122

intJ

8274

Command 2

Detailed Register Description
Write Register 0 (WRO):

Command 3

COMMAND/STATUS POINTER

Command 4

NUll CODE
SEND ABORT (SDlC)

Command 5

RESET EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE INTERRUPT ON NEXT Rx
CHARACTER
RESET TxINT/DMA PENDING
ERROR RESET

END OF INTERRUPT'

'Channel A only

Command 6
rool

NUll CODE
RESET Rx CRC CHECKER

Command 7

RESET Tx CRC GENERATOR
RESET Tx UNDERRUNJEOM lATCH

170102-4

07,06
00
01

WRO
02, 01, OO-Command/Status Register Pointer bits
determine which write-register the next byte is to be
written into, or which read-register the next byte is to
be read from. After reset, the first byte written into
either channel goes into WRO. Following a read or
write to any register (except WRO) the pointer will
point to WRO.

11
05, 04, 03-Command bits determine which of the
basic seven commands are to be performed.
Command 0 NUll-has no effect.
Command 1 Send Abort-causes the generation
of eight to thirteen 1's when in the
SOLC mode.

2-123

Reset External/Status Interruptsresets the latched status bits of RRO
and re-enables them, allowing interrupts to occur again.
Channel Reset-resets the Latched
Status bits of RRO, the interrupt prioritization logic and all control registers
for the channel. Four extra system
clock cycles should be allowed for
MPSC reset time before any additional commands or controls are written
into the channel.
Enable Interrupt on Next Receive
Character-if the Interrupt on First
Receive Character mode is selected,
this command reactivates that mode
after each complete message is received to prepare the MPSC for the
next message.
Reset Transmitter InterruptlOMA
Pending-if The Transmit Interrupti
OMA Enable mode is selected, the
MPSC automatically interrupts or requests OMA data transfer when the
transmit buffer becomes empty.
When there are no more characters
to be sent, issuing this command prevents further transmitter interrupts or
OMA requests until the next character has been completely sent.
Error Reset-error latches, Parity
and Overrun errors in RR1 are reset.
End of Interrupt-resElts the interrupt-in-service latch of the highestpriority internal device under service.
CRC Reset Code.
Null-has no effect.
Reset Receive CRC Checker-resets the CRC checker to O's. If in
SOLC mode the CRC checker is initialized to all 1's.
Reset Transmit CRC Generator-resets the CRC generator to O's. If in
SOLC mode the CRC generator's initialized to all 1's.
Reset Tx Underrun/End of Message
Latch.

8274

Write Register 1 (WR1):
LSB

MSB

I 106 I
07

04 : 03

04,03

Receive Interrupt Mode.

o
o

Receive Interrupts/OMA Oisabled.

1 1 0' I DO I
02

o
EXT INTERRUPT

ENABLE

TxlNTERRUPTI
DMA ENABLE

,
STATUS AFFECTS
VECTOR(CHBONLY)
(NULL CODE CH A)

05
VARIABLE
VECTOR
FIXED
VECTOR

r-------..
0

,
, ,
0

RxlNT/DMA DISABLE

RxlNT ON FIRST CHAR OR SPECIAL
CONDITION
INT ON ALL RI CHAR (PARITY AFFECTS
VECTOR)OR SPECIAL CONDITION
INT ON ALL RI CHAR (PARITY DOES
NOT AFFECT VECTOR) OR SPECIAL
CONDITION

1 " WAIT ON Ax. 0

WAITONTx

MUSTBEZERO

WAIT ENABLE 1

ENABLE. 0

Must be Zero.

Wait Enable-enables the wait function.
Channel A Only

DISABLE

WR2

170102-5

01,00
WR1
00

External/Status Interrupt Enable-allows interrupt to. occur as the result
of transitions 'on the CO, CTS or
SYNOET inputs. Also allows interrupts as the result of a Break/Abort
detection and termination, or at the
beginning of CRC, or sync character
transmission when the Transmit Underrun/EOM latch becomes set.
Transmitter InterruptiOMA Enableallows the MPSC to interrupt or request a OMA transfer when the
transmitter buffer becomes empty.
Status Affects vector-(WR1, 02 active in channel B only.) If this bit is
not set, then the fixed vector, programmed in WR2, is returned from
an interrupt acknowledge sequence.
If the bit if set then the vector returned from an interrupt acknowledge is variable as shown in the Interrupt Vector Table.

Receive Interrupt on First Character
Only or Special Condition.
Interrupt on All Receive Characters
or Special Condition (Parity Error is a
Special Receive Condition).
Interrupt on All Receive Characters
or Special Condition (Parity Error is
not a Special Receive Condition).
Wait on Receive/Transmit-when
the following conditions are met the
ROY pin is activated, otherwise it is
held in the High-Z state. (Conditions:
Interru~ Enabled Mode, Wait Enabled,CS = O,AO = 0/1,andA1 =
0). The ROY pin is pulled low when
the transmitter buffer is full or the receiver buffer is empty and it is driven
High when the transmitter buffer is
empty or the receiver buffer is full.
The ROYA and ROYs may be wired
OR connected since only one signal
is active at anyone time while the
other is in the High Z state.

System Configuration-These specify the data transfer from MPSC channels to the CPU, either interrupt or
OMA based.
Channel A and Channel B both use
interrupts.
Channel A uses OMA, Channel B
uses interrupts.

o
02

Channel A and Channel B both use
OMA.
Illegal Code.
Priority-this bit specifies the relative
priorities of the internal MPSC interruptiOMA sources.
(Highest) RxA, TxA, RxB, TxB, ExTA,
ExTB (Lowest).
(Highest) RxA, RxB, TxA, TxB, ExTA,
ExTB (Lowest).

05,04,03

2-124

Interrupt Code-specifies the behavior of the MPSC when it receives an
interrupt acknowledge sequence
from the CPU. (See Interrupt Vector
Mode Table.)

8274

a x x

100

Non-vectored interrupts-intended
for use with external OMA CONTROLLER. The Oata Bus remains in
a high impedance state during INTA
sequences.
8085 Vector Mode 1-intended for
use as the primary MPSC in a daisy
chained priority structure. (See System Interface section).

101

8085 Vector Mode 2-intended for
use as any secondary MPSC in a daisy chained priority structure. (See
System Interface section).
8086/88 Vector Mode-intended for
use as either a primary or secondary
in a daisy chained priority structure.
(See System Interface section).
Must be zero.
zero Pin 10 = RTSB
one Pin 10 = SYNOETB

07
Write Register 2 (WR2): Channel A Only
MSB

I 07

LSB

: 06

1 os I 04

I I

: 03

01 : DO

'----.",--J
0

BOTH INTERRUPT

A DMA. B INT

BOTHDMA

ILLEGAL

PRIORITY RxA

RxB

TxA

TxB

EXTA"

PRIORITY RxA

TxA

RxB

TxB

EXTA" ·EXTB"

8085 MODE 1

8085 MODE 2

8086188 MODE

ILLEGAL

EXTB"

VECTORED INTERRUPT
NON VECTORED INTERRUPT
MUST BE ZERO

1 PIN 10

PIN 10

SYNDET B
RTS B
170102-6

NOTE:
·External Status Interrupt only if EXT Interrupt Enable (WR1; DO) is set.

2-125

inter

8274

The following table describes the MPSC's response to an interrupt acknowledge sequence:

IPI

MODE

INTA

Data Bus
D7
High Impedance

Non-vectored

Any INTA

85 Mode 1

1
V7

1
V6

1st INTA
2nd INTA
3rd INTA

V4'

1
V3'

1
V2'

1
VO

V1'

VO'

85 Mode 1

1st INTA
2nd INTA
3rd INTA

1
1
0
High Impedance
High Impedance

86 Mode

1st INTA
2nd INTA

High Impedance
V7
V6
V5

V2'

85 Mode 2

1st INTA
2nd INTA
3rd INTA

High Impedance
V7
V6
V5

V4'

V3'

V2'

High Impedance
High Impedance
High Impedance
High Impedance
High Impedance

85 Mode 2

1st INTA
2nd INTA
3rd INTA

86 Mode

1st INTA
2nd INTA

-- 0

NOTE:
"These bits are variable if the "status affects vector" mode has been programmed, (WR1 S, D2).

Interrupt/DMA Mode, Pin Functions, and Priority

Ch.AWR2

Pin Functions

Int/DMA
Mode

IPOI
PIPI
RDYAI
RDYel
RxDRQA TxDRQA RxDRQe TxDRQe
Pin 11
Pin 29
Pin 30 Highest
D2 D1 Do CJ:I.A CH.B Pin 32

Priority
Lowest

INT

RxA, RxB, TxA, TxB, EXTA, EXTs

INT

RxA(1), RxB, TxB, EXTA, EXT8 (INT)

0
0

RDYA

RDYs

IPI

IPO

RxA, TxA, RxB,TxB, EXTA, EXTs

RxA, TxA (DMA)

DMA
RxDRQA TxDRQA

IPO

RxA, TxA (DMA)

DMA

RxA(1), RxB, TxB, EXTA, EXTs (INT)

INT

DMA

RxDRQA TxDRQA RxDRQs TxDRQ8

RxA, TxA, RxB, TxB (DMA)
RxA(1), RxB(1), EXTA, EXT s, (INT)
RxA, RxB, TxA, TxB, (DMA)
RxA(1), RxB(1), EXTA, EXTs (INT)

NOTE:
1. Special Receive Condition

2-126

infef

8274

Interrupt Vector Mode Table
8085 Modes
8086/88 Mode

NOTE:
1. Special Receive Condition

V4
V2

V3
V1

V2
Vo

0
0
0
0

0
0
1
1

1
1
1
1

0
0
1
1

Channel

Condition

0
1
0
1

Tx Buffer Empty
Ext/Status Change
Rx Char. Available
Special Rx Condition
(Note 1)

0
1
0
1

Tx Buffer Empty
Ext/Status Change
Rx Char. Available
Special Rx Condition
(Note 1)

= Parity Error, Rx Overrun Error, Framing Error, End of Frame (SDLC).

Write Register 2 (WR2): Channel B
MSB

WR2 CHANNEL B
D7 -DO
Interrupt vector-This register contains the value of the interrupt vector
placed on the data bus during interrupt acknowledge sequences.

LSB

Iw:~:~:":n:~: ~:wl
~------~~----------~

1,"",,""
Vector

170102-7

Write Register 3 (WR3):
MSB

LSB

Rx ENABLE
SYNC CHAR LOAD INHIBIT
L -_______ ADDR SRCH MODE (SDLCI

' - - - - - - - - - - R x CRC ENABLE
'--------------ENTER HUNT MODE
'------------------AUTO ENABLES

Rx 5 BITS/CHAR
Rx 7 BITS/CHAR
Rx 6 BITS/CHAR
Rx 8 BITS/CHAR

170102-8

2-127

inter
WR3
DO

8274

Write Register 4 (WR4):

Receiver Enable-A one enables the
receiver to begin. This bit should be
set only after the receiver has been
initialized.
Sync Character Load Inhibit-A one
prevents the receiver from loading
sync characters into the receive buffers. In SOLC, this bit must be zero.

Enter Hunt Phase-After initialization, the MPSC automatically enters
the Hunt mode. If synchronization is
lost, the Hunt phase can be re-entered by writing a one to this bit.

Auto Enable-A one written to this
bit causes CO to be automatic enable
signal for the receiver and CTS to be
an automatic enable signal for the
transmitter. A zero written to this bit
limits the effect of CD and CTS signals to setting/resetting their corresponding bits in the status register
(RRO).

07,06

Receive Character length

Receive 5 Data bits/character
Receive 7 Oata bits/character
Receive 6 Oata bits/character

1 " EVEN PARITY

o - ODD PARITY

Address Search Mode-If the SOLC
mode has been selected, 'the MPSC
will receive all frames unless this bit
is a 1. If this bit is a 1, the MPSC will
receive only frames with address
(OFFH) or the value loaded into WR6.
This bit must be zero in non-SOLC
modes.
Receive CRC Enable-A one in this
bit enables (or re-enables) CRC calculation. CRC calculation starts with
the last character placed in the Receiver FIFO. A zero in this bit disables, but does not reset, the Receiver CRC generator.

0
1

o
WR4
DO

ENABLE SYNC MODES

1 STOP BIT

1,5 STOP BITS

2 STOP BITS

8BITSYNCCHAR

16BITSYNCCHAR

SDLCIHDLCMODE(01111110)FLAG

EXTERNAL SYNC MODE

X1 CLOCK

X16 CLOCK

X32 CLOCK

X64CLOCK

170102-9

03,02

Even/Odd Parity-If parity is enabled, a one in this bit causes the
MPSC to transmit and expect even.
parity, and a zero causes it to send
and expect odd parity.
Stop bits/sync mode

o 0
o 1

Selects synchronous modes
Async mode, 1 stop bit/character

o
05,04
o 0

Parity-A one in this bit causes a parity bit to be added to the programmed number of data bits per
character for both the transmitted
and received character. If the MPSC
is programmed to receive 8 bits per
character, the parity bit is not transferred to the microprocessor. With
other receiver character lengths, the
parity bit is transferred to the microprocessor.

Receive 8 Data bits/character

o
o
.1

07,06

2-128

Async mode, 1% stop bits/character
Async mode, 2 stop bits/ character
Sync mode select
8-bit sync character
16-bit sync character
SOLC mode (Flag sync)
External sync mode
Clock Mode-Selects the clock/data
rate multiplier for both the receiver
and the transmitter. 1x mode must be
selected for synchronous modes. If
the 1x mode is selected, bit synchronization must be done externally.

8274

o
o

Clock
Clock
Clock
Clock

rate = Data
rate = Data
rate = Data
rate = Data

rate
rate
rate
rate

x 1
X 16
x 32
x 64

Write Register 5 (WR5):
MSB

LSB

I 07 1 06

051041031021011001

CRCENABLE

_ R TS
SO LC/CRC-16 (CRC MOOE)

T. ENABLE
SE NO BREAK

04
0

T.5 BITS OR LESS/CHAR

Tx 7 BITS/CHAR

Tx 6 BITS/CHAR

Tx 8 BITS/CHAR

06,05

o
o

OT R

170102-10

Bits to be sent must be right justified least significant
bit first, e.g.:

WR5

Request to Send-A one in this bit
forces the RTS pin active (low) and
zero in this bit forces the RTS pin inactive (high).
CRC Select-A one in this bit selects
the CRC-16 polynomial (X 16 + X15
+ X2 + 1) and a zero in this bit selects the CCITT-CRC polynomial (X16
+ X12 + X5 + 1). In SOLC mode,
CCITT-CRC must be selected.
Transmitter Enable-A zero in this bit
forces a marking state on the transmitter output. If this bit is set to zero
during data or sync character transmission, the marking state is entered
after the character has been sent. If
this bit is set to zero during transmission of a CRC character, sync or flag
bits are substituted for the remainder
of the CRC bits.
Send Break-A one in this bit forces
the transmit data low. A zero in this
bit allows normal transmitter operation.
Transmit Character length
Transmit 1-5 bits/character
Transmit 7 bits/character
Transmit 6 bits/character
Transmit 8 bits/character

Transmit CRC Enable-A one in this
bit enables the transmitter CRC generator. The CRC calculation is done
when a character is moved from the
transmit buffer into the shift register.
A zero in this bit disables CRC calculations. If this bit is not set when a
transmitter underrun occurs, the CRC
will not be sent.

07 06 05 04 03 02 01 DO
o 0 B5 B4 B3 B2 B1 BO
07 Data Terminal Ready-When set, this bit forces
the OTR pin active (low). When reset, this bit
forces the OTR pin inactive (high).

Five or less mode allows transmission of one to five bits per character. The
microprocessor must format the data in the following way:
07
06
05
04
03
02
01
DO
1
1
1
1
0
0
0
BO
Sends one data bit
1
1
1
0
0
0
B1
BO
Sends two data bits
0
0
0
B2
B1
BO
Sends three data bits
1
o
0
0
B3
B2
B1
BO
Sends four data bits
o
0
0
B4
B3
B2
B1
BO
Sends five data bits

2-129

inter

8274

Write Register 6 (WR6):

Write Register 7 (WR7):

MSB

LSB

IW:~:~:~:OO:OO:~:OOI

Iw:~ ~:~:oo:oo:~:ool
\

L~";k'.

Least significant
Sync byte (Address
in SOLC/HOLC Mode)

Sync byte (must
be 01111110 in
SOLC/HOLC Mode)

170102-11

170102-12

WR6
07-00

Sync/ Address-This register contains the transmit sync character in
Monosync mode, the low order B
sync bits in Bisync mode, or the Address byte in SOLC mode.

WR7
07-00

RRO
00

Sync/Flag-This register contains
the receive sync character in Monosync mode, the high order B sync bits
in Bisync mode, or the Flag character
(01111110) in SOLC mode. WR7 is
not used in External Sync mode.
02

Receive Character Available-This
bit is set when the receive FIFO contains data and is reset when the
FIFO is empty.
Interrupt In-Service*-If an Internal
Interrupt is pending, this bit is set at
the falling edge of the second INTA
pulse of an INTA cycle. In non-vectored mode, this bit is set at the failing edge of RO' after pointer 2 is
specified. This bit is reset when an
EOI command is issued and there
are no other interrupts in-service at
that time.
Transmit Buffer Empty-This bit is
set whenever the transmit buffer is

'This bit is only valid when IPI is active low and is
always zero in Channel B.
Read Register 0 (RRO):
MSB

LSB

R. CHAR AVAILABLE
INT IN-SERVICE (CHA only)
T. BUFFER EMPTY
CARRIER DETECT
SYNC/HUNT
CTS

EXTERNAL STATUS
INTERRUPT MODE

T. UNOERRUN/EOM
BREAKlABORT

170102-13

2-130

8274

empty except when CRC characters
are being sent in a synchronous
mode. This bit is reset when the
transmit buffer is loaded. This bit is
set after an MPSC reset.
Carrier Detect-This bit contains the
state of the CD pin at the time of the
last change of any of the External/
Status bits (CD, CTS, Sync/Hunt,
Break/ Abort, or Tx Underrun/EOM).
Any change of state of the CD pin
causes the CD bit to be latched and
causes an External/Status interrupt.
This bit indicates current state of the
CD pin immediately following a Reset
External/Status Interrupt command.
Sync/Hunt-In asynchronous modes,
the operation of this bit is similar to
the CD status bit, except that Sync/
Hunt shows the state of the SYNDET
input. Any High-to-Low transition on
the SYNDET pin sets this bit, and
causes an External/Status interrupt
(if enabled). The Reset External/
Status Interrupt command is issued
to clear the interrupt. A Low-to-High
transition clears this bit and sets the
External/Status interrupt. When the
. External/Status interrupt is set by the
change in state of any other input or
condition, this bit shows the inverted
state of the SYNDET pin at time of
the change. This bit must be read immediately following a Reset External/Status Interrupt command to
read the current state of the
SYNDET input.
In the. External Sync mode, the
Sync/Hunt bit operates in a fashion
similar to the Asynchronous mode,
except the Enter Hunt Mode control
bit enables the external sync detection logic. When the External Sync
Mode and Enter Hunt Mode bits are
set (for example, when the receiver is
enabled following a reset), the
SYNDET input must be held High by
the external logic until external character. synchronization is achieved. A
High at the SYNDET input holds the
Sync/Hunt status in the reset condition.
When external synchronization is
achieved, SYNDET must be driven
Low on the second rising edge' of
RxC after the rising edge of RxC on
which the last bit of the sync character was received. In other words, af-

2-131

ter the sync pattern is detected, the
external logic must wait for two full
Receive Clock cycles to activitate the
SYNDET input. Once SYNDET is
forced Low, it is good practice to
keep it Low until the CPU informs the
external sync logic that synchronization has been lost or a new message
is about to start. The High-to-Low
transition of the SYNDET output sets
the Sync/Hunt bit, which sets the External/Status interrupt. The CPU
must clear the interrupt by issuing the
Reset
External/Status
Interrupt
Command.
When the """'''"'''=
SYNDET input goes High
again,. another External/Status interrupt is generated that must also be
cleared. The Enter Hunt Mode control bit is set whenever character synchronization is lost or the end of
message is detected. In this case,
the MPSC again looks for a High-toLow transition on the SYNDET input
and the operation repeats as explained previously. This implies the
CPU should also inform the external
logic that character synchronization
has been lost and that the MPSC is
waiting for SYNDET to become ac-.
tive.
.
In the Monosync and Bisync Receive
modes, the Sync/Hunt status bit is
initially set to 1 by the Enter Hunt
Mode bit. The Sync/Hunt bit is reset
when the MPSC establishes character synchronization. The High-to-Low
transition of the Sync/Hunt bit causes an External/Status interrupt. that
must be cleared by the CPU issuing
the Reset External/Status Interrupt
command. This enables the MPSC to
detect the next transition of other External/Status bits.
.When the CPU detects the end of
message or that character synchronization is lost, it sets the Enter Hunt
Mode control bit, which sets the
Sync/Hunt bit to 1. The Low-to-High
transition of. the Sync/Hunt bit sets
the External/Status Interrupt, which
must. also be cleared by the Reset
External/Status Interrupt Command.
Note that the SYNDET pin acts as an
output in this mode, and goes low every time a sync pattern is detected in
the data stream.

8274

In the SOLC mode, the Sync/Hunt bit
is initially set by the Enter Hunt mode
bit, or when the receiver is disabled.
In any case, it is reset to when the
opening flag of the first frame is detected by the MPSC. The External/
Status interrupt is also generated,
and should be handled as discussed
previously.
Unlike the Monosyncand Bisync
modes, once the Sync/Hunt bit is reset in the SOLC mode, it does not
need to be set when the end of message is detected. The MPSC automatically maintains synchronization.
The only way the Sync/Hunt bit can
be set again is by the Enter Hunt
Mode bit, or by disabling the receiver.
Clear to Send-This bit contains the
inverted state of the CTS pin at the
time of the last change of any of the
External/Status bits (CO, CTS, Sync/
Hunt, Break/Abort, or Tx Underrun/
EOM). Any change of state of the
CTS pin causes the CTS bit to be
latched and causes an External!·
Status interrupt. This bit indicates the
inverse of the current state of the
CTS pin immediately following a Reset External/Status Interrupt command.
Transmitter Underrun/End of Message-This bit is in a set condition
following a reset (internal or external). The only command that can reset this bit is the Reset Transmit Underrun/EOM Latch command (WRO,
06 and 07). When the Transmit Underrun condition occurs, this bit is
set, which causes the External/
Status Interrupt which must be reset
by issuing a Reset External/Status
command (WRO; command 2).
Break/Abort-In the Asynchronous
Receive mode, this bit is set when a
Break sequence (null character plus
framing error) is detected in the data
stream. The External/Status interrupt, if enabled, is set when break is
detected. The interrupt service routine must issue the Reset External/
Status Interrupt command (WRO,
Command 2) to the break detection
logic so the Break sequence termination can be recognized.
The Break/Abort bit is reset when
the termination of the Break sequence is detected in the incoming
data stream. The termination of the

RR1:
03,02,01

2-132

Break sequence also causes the External/Status interrupt to be set. The
Reset External/Status Interrupt command must be issued to enable the
break detection logic to look for the
next Break sequence. A single extraneous null character is present in the
receiver after the termination of a
break; it should be read and discarded.
In the SOLC Receive mode, this
status bit is set by the detection of an
Abort sequence (seven or more 1's).
The External/Status interrupt is handled the same way as in the case of
a Break. The Break/Abort bit is not
used in the Synchronous Receive
mode.
All Sent-This bit is set when all
characters have been sent, in asynchronous modes. It is reset when
characters are in the transmitter, in
asynchronous modes. In synchronous modes, this bit is always set.
Residue Codes-Bit synchronous
protocols allow I-fields that are not
an integral number of characters.
Since transfers from the MPSC to the
CPU are character oriented, the residue codes provide the capability of
receiving leftover bits. Residue bits
are right justified in the last data by1e
received or first CRC by1e.
Parity Error-If parity is enabled, this
bit is set for received characters
whose parity does not match the programmed sense (Even/Odd). This bit
is latched. Once an error occurs, it
remains set until the Error Reset
command is written.
Receive Overrun Error-This bit indicates that the receive FIFO has been
overloaded by the receiver. The last
character in the FIFO is overwritten
and flagged with this error. Once the
overwritten character is read, this error condition is latched until reset by
the Error Reset command. If the
MPSC is in the status affects vector
mode, the overrun causes a special
Receive Condition Vector.
CRC/Framing
Error-In
async
modes, a one in this bit indicates a
receive framing error. In synchronous
modes, a one in this bit indicates that
the calculated CRC value does not
match the last two by1es received. It
can be reset by issuing an Error Reset command.

infef

8274

SDLC Residue Code Table (I Field Bits in 2 Previous Bytes)
7 bits/char

8 bits/char
RR1

03 02 01

6 bits/char

5 bits/char

FirstCRC Last Data First CRC Last Data FirstCRC Last Data First CRC Last Data
Byte
Byte
Byte
Byte
Byte
Byte
Byte
Byte

Read Register 1 (RR1): (Special Receive Condition Mode)
MSB

LSB

1~1~1~1~loo:oo:~lool
~

~
o 0 0

LALLSE NT

FIRST cRe
BYT E

LAST DATA BYTE

1 0

RESIDUE DATA
8 BITS/CHAR. MODE

PARITY ERROR
Rx OVERRUN ERROR
eRe/FRAMING ERROR
END OF FRAME (SOLe/HOLe MODE)

170102-14

2-133

Intel
D7

8274

End of Frame-This bit is valid only
in SDLC mode. A one indicates that a
valid ending flag has been received.
This bit is reset either by an Error Reset command or upon reception of
the first character of the next frame.

Read Register 2 (RR2):
MSB

LSB

IY7 : Y< Y5 : YO' >3' >2': Yl' ;V0"

..,'n,..,e..,.."-'-uP_'_ _ _
Vector

D7-DO

DMA operation is accomplished via an external DMA
controller. When the MPSC needs a data transfer, it
requests a DMA cycle from the DMA controller. The
DMA controller then takes control of the bus and
simultaneously does a read from the MPSC and a
write to memory or vice-versa.
The following section describes the many configurations of these basic types of system interface techniques for both serial channels.

"Variable In
Status Affects
Vector Mode (WR1; 02)

POLLED OPERATION

170102-15

RR2

an interrupt acknowledge signal. When the internal
or external interrupt controller receives the acknowledge,· it vectors the microprocessor to a service roU"
tine, in which the transaction occurs.

ChannelS
Interrupt Vector-Contains the interrupt vector programmed into WR2. If
the status affects vector mode is selected (WR 1; D2), it contains the
modified vector (See WR2). RR2
contains the modified vector for the
highest priority interrupt pending. If
no interrupts are pending, the variable bits in the vector are set to one.

SYSTEM INTERFACE
General
The MPSC to Microprocessor System interface can
be configured in many flexible ways. The basic interface types are polled, wait, interrupt driven, or direct
memory access driven.
Polled operation is accomplished by repetitively
reading the status of the MPSC, and making decisions based on that status. The MPSC can be polled
at any time.
Wait operation allows slightly faster data throughput
for the MPSC by manipulating the Ready input to the
microprocessor. Block Read or Write Operations to
the MPSC are started at will by the microprocessor
and the MPSC deactivates its RDY signal if it is not
yet ready to transmit the new byte, or if reception of
new byte is not completed.
Interrupt driven operation is accomplished via an in.ternal or external interrupt controller. When the
MPSC requires service, it sends an interrupt request
signal to the microprocessor, which responds with

In the polled mode, the CPU must monitor the desired conditions within the MPSC by reading the appropriate bits in the read registers. All data available,
status, and error conditions are represented by the
appropriate bits in read registers 0 and 1 for channels A and B.
There are two ways in which the software task of
monitoring the status of the MPSC has been reduced. One is the "~Ring" of all conditions into the
Interrupt Pending bit. {RRO; D1 channel A only). This
bit is set when the MPSC requires service, allowing
the CPU to monitor one bit instead of four status
registers. The other is available when the "status-affects-vector" mode is selected. By reading RR2
Channel B, the CPU can read a vector who's value
will indicate that one or more of group of conditions
has occurred, narrowing the field of possible conditions. See WR2 and RR2 in the Detailed Command
Description section.
WAIT OPERATION

Wait Operation is intended to facilitate data transmission or reception using block move operations. If
a block of data is to be transmitted, for example, the
CPU can execute a String I/O instruction to the
MPSC. After writing the first byte, the CPU will attempt to write a second byte immediately as is the
case of block move. The MPSC forces the RDY signal low which inserts wait states in the CPU's write
cycle until the transmit buffer is ready to accept a
new byte. At that time, the RDY signal is high allowing the CPU to finish the write cycle. The CPU then
attempts the third write and the process is repeated.
Similar operation can programmed for the receiver.
During initialization, wait on transmit (WR1; 05 = 0)

2-134

intJ

8274

INTERRUPT DRIVEN OPERATION

Software Flow, Polled Operation

The MPSC can be programmed into several interrupt modes: Non-Vectored, 8085 vectored, and
8088/86 vectored. In both vectored modes, multiple
MPSC's can be daisy-chained.

?
t
'''~"y-- '"'"".""~
AVAIL.)

READ RRO

In the vectored mode, the MPSC responds to an
interrupt acknowledge sequence by placing a call instruction (8085 mode) and interrupt vector (8085
and 8088/86 mode) on the data bus.

The MPSC can be programmed to cause an interrupt due to up to 14 conditions in each channel. The
status of these interrupt conditions is contained in
Read Registers 0 and 1. These 14 conditions are all
directed to cause 3 different types of internal interrupt request for each channel: receive/interrupts,
transmit interrupts and external/status interrupts (if
enabled).

READ Rx DATA

IWRITE Tx DATAl

RECEIVE

TRANSMIT

170102-16

NOTES:
1. RRO; DO is reset automatically when the data is
read.
2. RRO; 02 is reset automatically when the data is written.

This results in up to 6 internal interrupt request signals. The priority of those signals can be programmed to one of two fixed modes:
Highest Priority

or wait on receive (WR 1; 05 = 1) can be selected.
The wait operation can be enabled/disabled by setting/resetting the Wait Enable Bit (WR1; 07).

Lowest Priority

RxA RxB TxA TxB ExTA ExTB
RxA TxA RxB TxB ExT A ExTB

NOTE:
CAUTION: ANY CONDITION THAT CAN CAUSE
THE TRANSMITTER TO STOP (E.G., CTS GOES
INACTIVE) OR THE RECEIVER TO STOP (E.G.,
RX DATA STOPS) WILL CAUSE THE MPSC TO
HANG THE CPU UP IN WAIT STATES UNTIL RESET. EXTREME CARE SHOULD BE TAKEN
WHEN USING THIS FEATURE.

The interrupt priority resolution works differently for
vectored and non-vectored modes.

Hardware Configuration, Polled Operation

bADDRESS BUS

....

I I

l'lDATA BUS
RD
WR

L-

8205

P
P
~

L.-

JV CC

DBO-7

iNTA

Ao
A,

MPSC

RD
WR

170102-17

2-135

Intel

8274

Interrupt Condition Grouping
CONDITION

MODE

INTERNAL INTERRUPT
REQUEST

CHARAC-:::T:-:E::R::~====:~r~;~~~~:;-"""!:1 R~~1~::~~l~:c~~~S

RECEIVE
PARITY ERROR ==

~~~~I~~°EV::J'r\'N ERROR - - - - :

END OF FRAME (SDLC ONLY)_~-U"""""'=U
INTERRUPT
ON FIRST
CHARACTER'~~M¥.~~~~===~J~'
~~~~:':J
R, CHARACTER

FIRST NON·SYNC
CHARACTER (SYNC MODES)
DATA
FIRST
VALID ADDRESS BYTE (SDLC ONLY)

TRANSITIDN~~~~~~~~~~~~~~~~~~~~~~~~~~~~

CTS TRANSITION
SYNC TRANSITION
T. UNDERRUNIEOM
BREAK/ABORT
DETECT
CD

TRANSMIT BUFFER EMPTY

170102-18

INTERNAL'
INTERRUPT
ACCEPTED

LOWER PRIORITY INTERRUPTS NOT ACCEPTED

INTERRUPT
(EXTERNAL)

iNTA

(EXTERNAL)

HIGHER

INTA
(INTERNAL)

.....-r-I--_,.-__ NO~~~~~~.rS_----.....""'I----,,:ll1~:tJ,,~sACCEPTED

170102-19

PRIORITY RESOLUTION: VECTORED MODE
Any interrupt condition can be accepted internally to
the MPSC at any time, unless the MPSC's internal
INTA signal is active, unless a .!!!J;Iher priority interrupt is currently accepted, or if IPI is inactive (high).
The MPSC's internallNTA is set on the leading (fall-

iOg) edge of the first ExternallNTA pulse and reset
on the trailing (rising) edge of the second External
INTA pulse. After an interrupt is accepted internally,
and ExternallNT request is generated and the IPO
goes inactive. IPO and IPI are used for daisy-chaining MPSC's together.
.
.

2-136

inter

8274

In-Service Timing

,,,,",.c ",,"""" ~
ACCEPTED

INTERRUPT \

(EXTERNAL) _

\\... _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-.J

INTA
(EXTERNAL)

INTA
(INTERNAL)

IN-SERVICE
(INTERNAL)

170102-20

The MPSC's internallNTA is set on the leading (faIling) edge of·the first externallNTA pulse, and reset
on the trailing (rising) edge of the second external
INTA pulse.. After an interrupt is. accepted internally,
and externallNT request is generated and IPO goes
inactive (high). IPO and IPI are used for daisy-chaining MPSC's together.

Each of the six interrupt sources has an associated
In-Service latch. After priority has been resolved, the
highest priority In-Service latch is set. After the InService latch is set, the INT pin goes inactive (high).
NOTE:
If the External INT pin is active and the IPI signal is pulled
inactive high, the INT signal will also go inactive. IPI qualifies the External INT Signal.

2-137

inter

8274

EOI Command Timing

,INTERNAL INTERRUPT
ACCEPTED

SERVICE
ROUTINE

r--------------------------~~ ~----~
/

INTERRUPT \ .
(EXTER.OL) _
\

.
/
...._._ _ _ _ _ _ _ _ _ _- '

III'IX

(EXTERNAL)

INTO
(INTERNAL)

-----J

~~.
LOWIR

•ft.SEIilYlCE
(INTERNAL)

4--r:::WPrl

ACCEPTED

_ _- - . o J .

101 COMMAND
"(INTEJlNAL)

170102-21

Lower priority interrupts are not accepted internally
while the In-Service latch is set. However, higher priority interrupts are accepted internally and a new externallNT request is generated. ·If the CPU responds
. with new INTA sequence, the MPSC will respond
as before, suspending the lower priority interrupt.

After the interrupt is serviced,. the End-of-Interrupt
(EOI) command should be written to. the MPSC. This
command will cause an internal pulse that is used to
reset the In-Service Latch which allows service for
lower prioritY interrupts in the. daisy-chain to resume,
provid~d anew INTA sequence does not start for a
. higher priority interrupt (higher than the highest under service). If there is no interrupt pending internal- .
Iy, the IPO follows IPI.

2-138

8274

Non-Vectored Interrupt Timing
SEAVICE

ROUTINE
INTERNAL INTERRUPT

~======~LO;WE~'~P';'O;';ITY~';'NTVE';'U~P~T.~N;'OT~'~CC~EP~TEEcO~~~~~=-~

~======~~

ACCEPTED

INTEARUPT

(EXTERNAl)

iiD

(EXTERNAL)

INTERNAL POINTER

SETTOREQ2

IN·SERVICE

(INTERNAL)

EOICQ.. MAND
(INTERNAL)

170102-22

PRIORITY RESOLUTION:
NON-VECTORED MODE

In non-vectored mode, the MPSC does not respond
to interrupt acknowledge sequences. The INTA input
(pin 27) must be pulled high for proper operation.
The MPSC should be programmed to the Status-Affects-Vector mode, and the CPU should read RR2
(Ch. B) in its service routine to determine which interrupt requires service.
In this case, the internal pointer being set to RR2
provides the same function as the internal INTA sig-

nal in the vectored mode. It inhibits acceptance of
any additional internal interrupts and its leading
edge starts the interrupt priority resolution circuit.
The interrupt priority resolution is ended by the leading edge of the read signal used by the CPU to retrieve the modified vector. The leading edge of read
sets the In-Service latch and forces the external INT
output inactive (high). The internal pointer is reset to
zero after the trailing edge of the read pulse.
NOTE:
That if RR2 is specified but not read, no internal interrupts, regardless of priority, are accepted.

2-139

inter

8274

Yee

~~{
INTA
CPU

llIi

iiiTA

iPlI

MPSC
HIGHEST PRIORITY

im'

iiiTA
iPlI
MPSC

11m

iPO

MPSC
LOWEST PRIORITY

170102-23

If TPi is active (low), the MPSC knows that all higher
priority MPSC's have no interrupts pending. The TPi
pin of the highest priority MPSC is strapped active
(low) to ensure that it always has priority over the
rest.

DAISY CHAINING MPSC
In the vectored interrupt mode, multiple MPSC's can
be daisy-chained on the same INT, INTA Signals.
These signals, in conjunction with the IPI and IPO
allow a daisy-chain-like interrupt resolution scheme.
This scheme can be configured for either 8085 or
8086/88 based system.

MPSC's Daisy-chained on an 8088/86 CPU should
be" programmed to the 8088/86 Interrupt mode
(WR2; D4, D3 Ch. A). MPSC's Daisy-chained on an
8085 CPU should be programmed to 8085 interrupt
mode 1 if it is the highest priority MPSC. In this
mode, the highest priority MPSC issues the CALL
instruction during the first INTA cycle, and the interrupting MPSC provides the interrupt vector during
the following INTA cycles. Lower priority MPSC's
should be programmed to 8085 interrupt mode 2.

In either mode, the same hardware configuration is
called for. The INT request lines are wire-OR'ed together at the input of a TTL inverter which drives the
INT pin of the CPU. The INTA signal from the CPU
drives all of the daisy-chained MPSC's.
The MPSC drives IPO (Interrupt Priority Output) inactive (high) if TPi (Interrupt Priority Input) is inactive
(high), or if the MPSC has an interrupt pending.

MPSC's used alone in 8085 systems should be programmed to 8085 mode 1 interrupt operation.

ThelPO of the highest priority MPSC is connected
to the IPI of the next highest priority MPSC, and so
on.
'

2-140

intJ

8274

OMA Acknowledge Circuit
DACK o - - - - - - ,
DACK, - - - - - ,
DACK2~----r-r--~

MULTIPLEXER

DACKJ---~+-~~-~

Ao
A,

Ao
A1

170102-24

OMATiming

\"--------

Ao' Al'CS----""'"'X~______________
...J/

RD, WR - - - - - - - " " ' " ' \ \ . _ _ _ _ _ _ _ _

170102-25

OMA OPERATION

Each MPSC can be programmed to utilize up to four
DMA channels: Transmit Channel A. Receive Channel A. Transmit Channel B. Receive Channel B.
Each DMA Channel has an associated DMA Request line. Acknowledgement of a DMA cycle is
done via normal data read or write cycles. This is
accomplished by encoding the DACK signals to generate Ao. A1, and CS, and multiplexing them with the
normal Ao, A1, and CS signals.

mutations of interrupt, wait, and DMA modes for
channels A and B. Bits D1, Do of WR2 Ch. A determine these permutations.

PERMUTATIONS

Channels A and B can be used with different system
interface modes. In all cases it is possible to poll the
MPSC. The following table shows the possible per-

Permutation
WR2Ch.A
01
00

ChannelB

Wait
Interrupt
Polled

DMA
Polled

Interrupt
Polled

DMA
Polled

NOTE:
D1, DO = 1,1 is illegal.

2-141

Channel A

DE
8282
A,6-A19

ALE

~
8284A

~
~

AS-A15

8088

I-I--------------t

..lI

A16-.'9

DIDO

""1'

----------1~-__l ST"

1-1

L-..,.-

1-----

8274

M READY

8282

Hi=~~~,
I I

IIII U

ADSTB

0,,-0

~--~1Mnm
~---.,

MEJifWA

l~=======++====~~ ::~

Hl.OA

+-------, mrn

HI------,iiOW

l_~======t>~====t=t=====1AEADY

8237 A..-A

II-------,----..J

11-________-'

DRao~-----~----r1r_--------_,

RKDRO ...

CI)
I\)

TIORO ...

.j:oo

...,

~(1

o:~ ~---I+---------t_J_--------__, RIlDRQ 8
DRO,

i5ACK 1

MULTIPLEXER

oRal

________ ,

I
~~~;:=f~~~~~~I~~~==~

RESET

elK

I~:;

II I

00-0 1

EOP

T ~DRQB

Ao
A,

Co
I

______ JI

os
(FROM 8205)

t-....."

L-----------------------------------------------~4Ro
~-----------------------------------------------~
170102-26

NOTE:
The circuit was not designed based on a worst-case timing analysis. Specific implementations should include this timing analysis.

inter

8274

PROGRAMMING HINTS

Transmit Under-run/EOM Latch

This section will describe some useful programming
hints which may be useful in program development.

In SOLC/HOLC, bisync and monosync mode, the
transmit under-run/EOM must be reset to enable the
CRC check bytes to be appended to the transmit
frame or transmit message. The transmit under-runt
EOM latch can be reset only after the first character
is loaded into the transmit buffer. When the transmitter under-runs at the end of the frame, CRC check
bytes are appended to the frame/message. The
transmit under-run/EOM latch can be reset at any
time during the transmission after the first character.
However, it should be reset before the transmitter
under-runs otherwise, both bytes of the CRC may
not be appended to the frame/message. In the receive mode in bisync operation, the CPU must read
the CRC bytes and two more SYNC characters before checking for valid CRC result in RR1.

Asynchronous Operation
At the end of transmission, the CPU must issue "Reset Transmit InterruptlOMA Pending" command in
WRO to reset the last transmit empty request which
was not satisfied. Failing to do so will result in the
MPSC locking up in a transmit ,empty state forever.

Non-Vectored Mode
In non-vectored mode, the Interrupt Acknowledge
pin (INTA) on the MPSC must be tied high through a
pull-up resistor. Failing to do so will result in unpredictable response from the 8274.

HOLC/SOLC Mode
When receiving data in SOLC mode, the CRC bytes
must be read by the CPU (or OMA controller) just
like any other data field. Failing to do so will result in
receiver buffer overflow. The CRC bytes are not to
be used for CRC verification. Residue bits may be
contained in the first CRC byte. Also, the End of
Frame Interrupt indicates that the entire frame has
been received. At this point, the CRC result (RR1:
D6) and residue code (RR1; 03, 02, 01) may be
checked.

Sync Character Load Inhibit
In bisync/monosync mode only, it is possible to prevent loading sync characters into the receive buffers
by setting the sync character load inhibit bit (WR3;
01 = 1). Caution must be exercised in using this
option. It may be possible to get a CRC character in
the received message which may match the sync
character and not get transferred to the receive buffer. However, sync character load inhibit should be
enabled during all pre-frame sync characters so the
software routine does not have to read them from
the MPSC.
In SOLC/HOLC mode, sync character load inhibit bit
must be reset to zero for proper operation.

Status Register RR2
RR2 contains the vector which gets modified to indicate the source of interrupt (See the section titled
MPSC Modes of Operation). However, the state of
the vector does not change if no new interrupts are
generated. The contents of RR2 are only changed
when a new interrupt is generated. In order to get
the correct information, RR2 must be read only after
an interrrupt is generated, otherwise it will indicate
the previous state.

Initialization Sequence
The MPSC initialization routine must issue a channel
Reset Command at the beginning. WR4 should be
defined before other registers. At the end of the initialization sequence, Reset External/Status and Error Reset commands should be issued to clear any
spurious interrupts which may have been caused at
power up.

EOICommand
EOI command can only be issued through channel A
irrespective of which channel had generated the interrupt.

Priority in OMA Mode
There is no priority in OMA mode between the following four signals: TxORQ(CHA), RxORQ(CHA),
TxORQ(CHB), RxORQ(CHB). The priority between
these four signals must be resolved by the OMA
controller. At any given time, all four OMA channels
from the 8274 are capable of going active.

2-143

intJ

8274

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Ambient Temperature
Under Bias ...................... O°C to + 70°C

Storage Temperature
(Ceramic Package) .......... - 65°C to + 150°C
(Plastic Package) ............ -40°C to + 125°C
Voltage on Any Pin with
Respect to Ground ............ - 0.5V to + 7.0V

D.C. CHARACTERISTICS
Symbol

T A = O·C to + 70°C; Vee = + 5V ± 10%

Parameter

Min

Max

Units

VIL

Input Low Voltage

-0.5

+0.8

VIH

Input High Voltage

+2.0

Vee +0.5

VOL

Output Low Voltage

+0.45

VOH

Output High Voltage

+2.4

Test Conditions ...

= 2.0mA
= 200 p.A
VIN = Vee to OV
VOUT = Vee to 0.45V
IOL

IOH

IlL

Input Leakage Current

±10

p.A

IOFL

Output Leakage Current

±10

p.A

Ice

Vee Supply Current

200

NOTE:

1. For ExtendedTemperature EXPRESS, use MIL8274 electrical Parameters.

CAPACITANCETA =
Symbol

25°C', Vee

GND

Parameter

Min

Max

Units

Test Conditions

CIN

Input Capacitance

tc = 1 MHz

COUT

Output Capacitance

ClIO

Input/Output Capacitance

Unmeasured pins
returned to GND

2-144

inter

8274

A.C. CHARACTERISTICS

TA = O°Cto +70°C;Vcc = +5V ±10%

Min

Max

Units

tCY

ClK Period

250

4000

tCl

ClK low Time

105

2000

tCH

ClK High Time

105

2000

ClK Rise Time

ClK Fall Time

tAR

AO, A 1 Setup to RD .J,

tAO

AO, A 1 to Data Output Delay

tRA

AO, A 1 Hold after RD

tRO

RD.J, to Data Output Delay

tRR

RD Pulse Width

tOF

Output Float Delay

tAW

CS, AO, A 1 Setup to WR .J,

tWA

CS, AO, A 1 Hold after WR

tww

WR Pulse Width

tow

Data Setup to WR

two

Data Hold after WR

tpi
tiP
til

INT A Pulse Width

tplPO

IPI.J, to IPO Delay

100

tlO

INTA.J, to Data Output Delay

200

tco

RD or WR to ORO .J,

150

tRY

Recovery Time Between Controls

tcw

CS, AO, A 1 to ROYA or ROY B Delay

Parameter

Symbol

ns
200

200
250

ns
ns

120

250

150

IPI Setup to INTA .J,

IPI Hold after INTA t

t
t

250

300

ns
140

toCY

Data Clock Cycle

4.5

tcy

tOCl

Data Clock low Time

180

tOCH

Data Clock High Time

180

tTD

TxC to TxD Delay (x1 Mode)

tos

RxD Setup to RxC t

tOH

RxD Hold after RxC t

tlTO

TxC to INT Delay

tcy

tiRO

RxC to INT Delay

tcy

tpl

CTS, CD, SYNDET low Time

200

tpH

CTS, CD, SYNDET High Time

200

tlPO

External INT from CTS, CD, SYNDET

300

2-145

150 pF

Test Conditions

140

ns
ns
500

8274

, A.C. TESTING INPUT/OUTPUT WAVEFORM

u=x
INPUT/OUTPUT

" '>
'2,0

0,8

A.C. TESTING LOAD CIRCUIT

<, .'
2.0

TEST POINTS

DEVICE
UNDER
TEST

0.'

170102-27
A.C. Testing; Inputs are driven a12.4V for a Logic,"r' and 0.45V
for a Logic ,"0". TIming measurements are made al 2.0V for a
Logic "1" andO.8V for a Logic "0".

170102-28
CL = 100 pF
CL Includes Jig Capaclt8nce

WAVEFORMS
CLOCK CYCLE
1+-----,.--ICy--------~

ClK

170102-29

READ CYCLE

a. AD. Al
14---:--' I RR ----~

DB"DB,

1+-----1'0-----...
170102-30

2-146

inter

8274

WAVEFORMS

(Continued)

WRITE CYCLE

170102-31

DMA CYCLE

DRQ

CI.AO,Al

-,.J--

iiDORWA

170102-33

READ/WRITE CYCLE (SOFTWARE POLLED MODE)

Ci,AO,A1

RDORWR

1--------,,,-------1

"------170102-34

2-147

8274

INTA CYCLE

'"'"
I

:z:
%

NOTES:
1. INTA signal as RD signal.
2. IPI signal acts as CS signal.

2-148

;;

....

inter
WAVEFORMS

8274

(Continued)

TRANSMIT DATA CYCLE

~----'ITD------3oo,.-.t

170102-35

RECEIVE DATA CYCLE
t-------1ocv-------l

••0

~------I::==~~I"O,----\1~

\~.
170102-36

OTHER TIMING

=~,,_,~t------"'---I"-0>----IPH-~_

'OPo--Q-t.,'--___
170102-37

2-149

inter

82530/82530-6

SERIAL COMMUNICATIONS CONTROLLER (sec)

•
•

Two Independent Full Duplex Serial
Channels
On Chip Crystal Oscillator, Baud-Rate
Generator and Digital Phase Locked
Loop for Each Channel

in Express Version
• Available
Asynchronous Modes

•-

5-8 bit Character; Odd, Even or No
Parity; 1, 1.5 or 2 Stop Bits
- Independent Transmit and Receive
Clocks. 1X, 16X, 32X or 64X
Programmable Sampling Rate
- Error Detection: Framing, Overrun
and Parity
- Break Detection and Generation

for NRZ, NRZI or FM
• Programmable
Data Encoding/Decoding

•
•
•

Diagnostic Local Loopback and
Automatic Echo for Fault Detection and
Isolation
System Clock Rates:
- 4 MHz for 82530
- 6 MHz for 82530-6
Max Bit Rate (6 MHz)
- Externally Clocked: 1.5 Mbps
Self-Clocked:
375 Kbps FM CODING
187 Kbps NRZI CODING
93 Kbps Asynchronous

Interfaces with Any INTEL CPU, DMA or
• I/O
Processor
AvailaJ:>le in 40 Pin DIP and 44 Lead
• PLCC

Synchronous Modes
• -BitSDLC
Loop/Non-Loop Operation
- CRC-16 or CCITT Generation
Detection
- Abort Generation and Detection
-I-field Residue Handling
- CCITT X.25 Compatible
• Byte Synchronous Modes
-Internal or External Character
Synchronization (1 or 2 Characters)
- Automatic CRC Generation and
Checking (CRC 16 or CCITT)
-IBM Bisync Compatible

The INTEL 82530 Serial Communications Controller (SCC) is a dual-channel, multi-protocol data communications peripheral. It is designed to interface high speed communications lines using Asynchronous, Byte synchronous and Bit synchronous protocols to INTEL's microprocessors based systems. It can be interfaced with
Intel's MCS51 196, iAPX86/88/186 and 188 in polled, interrupt driven or DMA driven modes of operation.
The SCC is a 40-pin device manufactured using INTEL's high-performance HMOS' II technology .

• HMOS is a patented process of Intel Corporation.

2-150

October 1987
Order Number: 230834-003

inter

82530/82530-6

r-DATA
BUS
BUFFERS

DBO·7

CHANNEL A

t-- ~

BAUD
RATE
GENERATOR
TRANSMITTER!
RECEIVER

t-- rp. r-

p. t--

READ
REGISTERS

INT_
iJiITA
_

CONTROL
LOGIC
WRITE
REGISTERS

P. ~
p- ~

~ r~ r-

IEO-

OPERATION
CONTROL

IEI-

::J

III
..J

c
Z

II:

...~

.&iREO.. ___
a/REOa-

CHANNELB

L LllL
DIC

TKDa
RaDB
RTxCB

I >- TRaCB

.&iREO.. a/REOa-c

AlB

CSWRRD

~
~

SYSTEM INTERFACE

v-.

~
SERIAL COMMUNICATION
INTERFACE

230834-1

Figure 1. 82530 Internal Block Diagram

2-151

infef

82530/82530-6

DEll

DBD

DB3

DB2

DB5

DB4

DB7

DB6

iNf

lEO

lEI

Alii

INTA

Vee

ole

RDY.IREO.

lEO
lEI

Vee
RDY!REOa

GND

SYNC.

82530

SYNCa

RDYeIREQe

ATIC.

SYNCe

RID.

RTICe

TRIC.

RDY!REOb

SCC

RTxCa
RxDa

SYNCb
RTxCb

TRxCa

TxDa

RIDe

TxDb

'fRiee

TxDA

DTRA/REQ.

TIDe
OOCCO::::'!..Q..Q..Q..QO

RTSA

DTRelREQe

CTS.

RTSe

CD.

rna

ClK

CDe

I~ 1~1~18 d 18 I~I~ I~ z

230834-43

230834-2

Figure 2. Pin Configurations
The following section describes the pin functions of the

sec. Figure 2 details the pin assignments.

Table 1. Pin Description
PinNa.

Symbol

DIP

Type

Name and Function
DATA BUS: The Data Bus lines are bi-directional three-state lines
which interface with the system's Data Bus. These lines carry data
and commands to and from the sec.

PLCC

39
2
38
3
37
4

2
44
3
43
4
42
5

1/0
1/0
1/0
1/0
I/O
I/O
1/0
1/0

INT

lEO

INTERRUPT ENABLE OUT: lEO is High only if lEI is High and the
CPU is not servicing an sec interrupt or the sec is not requesting
an interrupt (Interrupt Acknowledge cycle only). lEO is connected
to the next lower priority device's lEI input and thus inhibits
interrupts from lower priority devices.

lEI

INTERRUPT ENABLE IN: lEI is used with lEO to form an interrupt
daisy chain when there is more than one interrupt-driven device. A
High lEI indicates that no other higher priority device has an
interrupt under service or is requesting an interrupt.

DBo
DB1
DB2
DB3
DB4
DB5
DBa
DB?

INTERRUPT REQUEST: The interrupt signal is activated when the

sec requests an interrupt. It is an open drain output.

2-152

82530/82530-6

Table '1. Pin
Symbol
INTA

Pin No.
DIP

PLCC

(Continued)

Type

Name and Funcl:ion

INTERRUPT ACKNOWLEDGE: This signal indicates an active Interrupt
Acknowledge cycle. During this cycle, the SCC interrupt daisy chain
settles. When RD becomes active, the SCC places an interrupt vector
on the data bus (if lEI is High). INTA is latched by the rising edge of
ClK.

RDYA/REQA
RDYs/REQs

10
30

11
34

0
0

SYNCA
SYNCs

11
29

12
33

I/O
1/0

Vee

Descrip~ion

POWER:

+ 5V Power supply.

READY IREQUEST: (output, open-drain when programmed for a Ready
function, driven High or low when programmed for a Request function).
These dual-purpose outputs may be programmed as Request lines for a
DMA controller or as Ready lines to synchronize the CPU to the SCC
data rate. The reset state is Ready.
SYNCHRONIZATION: These pins can act either as inputs, outputs or
part of the crystal oscillator circuit. In the Asynchronous receive mode
(crystal oscillator option not selected), these pins are inputs similar to
CTS and CD. In this mode, transitions on these lines affect the state of
the Synchronous/Hunt status bits in Read Register 0 (Figure 9) but
have no other function.
In External Synchronization mode with the crystal oscillator not
selected, these lines also act as inputs. In this mode, SYNC must be
driven lOW t1.vo receive clock cycles after the last bit in the
synchronous character is received. Character assembly begins on the
rising edge of the receive clock immediately preceding the activation of
SYNC.
In the Internal Synchronization mode (Monosync and Bisync) with the
crystal oscillator not selected, these pins act as outputs and are active
only during the part of the receive clock cycle in which synchronous
characters are recognized. The synchronous condition is not latched,
so these outputs are active each time a synchronization pattern is
recognized (regardless of characters boundaries). In SDlC mode, these
pins act as outputs and are valid on receipt of a flag.

RTxCA
RTxCs

12
28

13
32

I
I

RECEIVEITRANSMIT ClOCt(S: These pins can be programmed in
several different modes of operation. In each channel, RTxC may
supply the receive clock, the transmit cloci<, the clock for the baud rate
generator, or the clock for the Digital Phase locked loop. These pins
can be programmed for use with the respective SYNC pins as a crystal
oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate
in Asynchronous modes.

RxDA
RxDs

13
27

14
31

RECEIVE DATA: These lines receive serial data at standard TTL levels.

TRxCA
TRxCs

14
26

15
30

1/0
1/0

TxDA
TxDs

15
25

16
29

0
0

TRANSMIT DATA: These output signals transmit serial data at
standard TTL levels

DTRA/REQA
DTRs/REQs

16
24

19
27

0
0

DATA TERMINAL READY/REQUEST: These outputs follow the state
programmed into the DTR bit. They can also be used as general
purpose outputs or as Request lines for a DMA controller.

I
TRANSMIT/RECEIVE CLOCKS: These pins can be programmed in
several different modes of operation. TRxC may supply the receive
clocl< or the transmit cloC\< in the input mode or supply the output of the
Digital Phase locked loop, the crystal oscillator, the baud rate
generator, or the transmit clock in the output mode.

2-153

82530/82530-6

Table 1. Pin Description (Continued)

Pin No.

Symbol

Type

Name and Function

20
26

0
0

REQUEST TO SEND: When the Request to Send (RTS) bit in
Write Register 5 is set (Figure 10), the RTS signal goes low. When
the RTS bit is reset in the Asynchronous mode and Auto Enable is
on, the signal goes High after the transmitter is empty. In
Synchronous mode or in Asynchronous mode with Auto Enable
off, the RTS pin strictly follows the state of the RTS bit. Both pins
can be used as general-purpose outputs.

18
22

21
25

I
I

CLEAR TO SEND: If these pins are programmed as Auto Enables,
a low on the inputs enables the respective transmitters. If not
programmed as Auto Enables, they may be used as generalpurpose inputs. Both inputs are Schmitt·trigger buffered to
accommodate slow rise·time inputs. The SCC detects pulses on
these inputs and can interrupt the CPU on both logic level
transitions.

CDA
CDs

19
21

22
24

I
I

CARRIER DETECT: These pins function as receiver enables if
they are programmed for Auto Enables; otherwise theymay be
used as general-purpose input pins. Both pins are Schmitt-trigger
buffered to accommodate slow rise time signals. The SCC detects
pulses on these pins and can interrupt the CPU on both logic level
transitions.

ClK

CLOCK: This is the system SCC clock used to synchronize internal
signals.

GND

D/C

DATA/COMMAND SELECT: This signal defines the type of
information transferred to or from the SCC. A High means data is
transferred; a low indicates a command.

. 33

CHIP SELECT: This signal selects the SCC for a read or write
operation.

AlB

CHANNEL A/CHANNEL B SELECT: This signal selects the
channel, in which the read or write operation occurs.

WRITE: When the SCC is selected this Signal indicates a write
operation. The coincidence of RD and WR is interpreted as a
reset.

READ: This signal indicates a read operation and when the SCC is
selected, enables the SCC's bus drivers. During the Interrupt
Acknowledge cycle, this signal gates the interrupt vector onto the
bus if the SCC is the highest priority device requesting an interrupt.

DIP

PLCC

RTSA
RTSs

17
23

CTSA
CTSs

GROUND

2-154

82530/82530-6

GENERAL DESCRIPTION
The Intel 82350 Serial Communications Controller
(SCC) is a dual-channel, multi-protocol data communications peripheral. The SCC functions as a serialto-parallel, parallel-to-serial convertor/controller.
The SCC can be software-configured to satisfy a
wide range of serial communications applications.
The device contains sophisticated internal functions
including on-chip baud rate generators, digital phase
locked loops, various data encoding and decoding
schemes, and crystal oscillators that reduce the
need for external logic.
In addition, diagnostic capabilities-automatic echo
and local loopback-allow the user to detect and
isolate a failure in the network. They greatly improve
the reliability and fault isolation of the system.
The SCC handles Asynchronous formats, Synchronous byte-oriented protocols such as IBM Bisync,
and Synchronous bit-oriented protocols such as
HDLC and IBM SDLC. This versatile device supports
virtually any serial data transfer application (Terminal, Personal Computer, Peripherals, Industrial Controller, Telecommunication sytem, etc.).
The 82530 can generate and check CRC codes in
any Synchronous mode and can be programmed to
check data integrity in various modes. The SCC also
has facilities for modem control in both .channels. In
applications where these controls are not needed,
the modem control can be used for general purpose
I/O..
The Intel 82530 is designed to support Intel's
MCS51/96, iAPX 86/88 and iAPX 186/188 families.

ARCHITECTURE
The 82530 internal structure includes two full-duplex
channels, two baud rate generators, internal control
and interrupt logic, and a bus interface to a non-multiplexed CPU bus. Associated with each channel are
a number of read and write registers for mode control and status information, as well as logic necessary to interface modems or other external devices.
The logic for both channels provides formats, synchronization, and validation for data transferred to
and from the channel interface. The modem control

inputs are monitored by the control logic under program control. All of the modem control signals are
general-purpose in nature and can optionally be
used for functions other than modem control.
The register set for each channel includes ten control (write) registers, two synchronous character
(write) registers, and four status (read) registers. In
addition, each baud rate generator has two (read/
write) registers for holding the time constant that determines the baud rate. Finally, associated with the
interrupt logic is a write register for the interrupt vector accessible through either channel, a write-only
Master Interrupt Control register and three read registers; one containing the vector with status information (Channel B only), one containing the vector
without status (A only), and one containing the Interrupt Pending bits (A only).
The registers for each channel are designated as
follows;
WRO-WR15-Write Registers 0 through 15.
RRO-RR3, RR10, RR12, RR13, RR15-Read Registers 0 through 3, 10, 12, 13, 15.
Table 2 lists the functions assigned to each read or
write register. The SCC contains only one WR2 and
WR9, but they can be accessed by either channel.
All other registers are paired (one for each channel).

DATA PATH
The transmit and receive data path illustrated in Figure 3 is identical for both channels. The receiver has
three 8-bit buffer registers in a FIFO arrangement, in
addition to the 8-bit receive shift register. This
scheme creates additional time for the CPU to service an interrupt at the beginning of a block of highspeed data. Incoming data is routed through one of
several paths (data or CRC) depending on the selected mode (the character length in asynchronous
modes also determines the data path).
The transmitter has an 8-bit transmit data buffer register loaded from the internal data bus and a 20-bit
transmit shift register that can be loaded either from
the sync-character registers or from the transmit
data register. Depending on the operational mode,
outgoing data is routed through one of four main
paths before it is transmitted from the Transmit Data
output (TxD).

2-155

82530/82530-6

Table 2. Read and Write Register Functions
READ REGISTER FUNCTIONS

WRITE REGISTER FUNCTIONS

RRO

WRO

RR1
RR2

RR3
RR8
RR10
RR12
RR13
RR15

Transmit/Receive buffer status and External status
Special Receive Condition status
Modified interrupt vector
(Channel B only)
Unmodified interrupt
(Channel A only)
Interrupt Pending bits
(Channel A only)
Receive buffer
Miscellaneous status
Lower byte of baud rate generator time
constant
Upper byte of baud rate generator time
constant
External/Status interrupt information

WR1

WR2
WR3
WR4
WR5

WR6
WR7
.W~8

WR9
WR10
WR11
WR12
WR13
WR14
WR15

2-156

CRC initialize, initialization commands for
the various modes, shift right/ shift left
command
Transmit/Receive interrupt and data
transfer mode definition
Interrupt· vector (accessed through either
channel)
Receive parameters and control
Transmit/Receive miscellaneous parameters and modes
Transmit parameters and controls
Sync characters or SDLC address field
Sync character or SDLC flag
Transmit buffer
Master interrupt control and reset (accessed through either channel)
Miscellaneous transmitter/receiver control
bits
Clock Mode control
Lower Byte of baud rate generator time
constant
Upper Byte of baud rate generator time
constant
Miscellaneous control bits
External/Status interrupt control

(
CPU 1/0

:!!

DR GENERATOR
INPUT

CO
C
III
~

I\)

c.n
Co)

.....
CO
(;)

C
en DI
.....

I\)

c.n

lIT

Co)
(;)

'tI

DPLL
SR GENERATOR OUTPUT
DPLL OUTPUT

TA.C

RECEIVE CLOCK
CLOCK
MU'

TRANSMIT CLOCK
DPLL CLOCK

ATIC
DR GENERATOR CLOCK

SiNE
(OSCILLATOR)

230834-3

82530/82530-6

interrupts the CPU both at the start and at the end of
a received break. Reception is protected from
spikes by a transient spike-rejection mechanism that
checks the signal one-half a bit time after a Low
level is detected on the receive data input (RxDA or
RxDs). If the Low does not persist (as in the case of
a transient), the character assembly process does
not start.

FUNCTIONAL DESCRIPTION
The functional capabilities of the SCC can be described from two different points of view: as a data
communications device, it transmits and receives
data in a wide variety of data communications protocols; as a microprocessor peripheral, it interacts with
the CPU and provides vectored interrupts and handshaking signals.

Framing errors and overrun errors are detected and
buffered together with the partial character on which
they occur. Vectored interrupts allow fast servicing
of error conditions using dedicated routines. Furthermore, a built-in checking process avoids the interpretation of a framing error as a new start bit: aframing error results in the addition of one-half a bit time
to the pOint at which the search for the next start bit
begins.

DATA COMMUNICATIONS
CAPABILITIES
The SCC provides two independent full-duplex
channels programmable for use in any common
asynchronous or synchronous data-communications
protocol. Figure 4 and the following description briefly detail these protocols.
.

The SCC does not require symmetric transmit and
receive clock signals-a feature allowing use of the
wide variety of clock sources. The transmitter and
receiver can handle data at a rate of 1, 1;16, %2 or
%4 of the clock rate supplied to the receive and
transmit clock inputs. In the asynchronous modes, a
data rate equal to the clock rate, 1x mode, requires
external synchronization. In asynchronous modes,
the SYNC pin may be programmed as an input used
for functions such as monitoring a ring indicator.

Asynchronous Modes
Transmission and reception can be accomplished
independently on each channel with five to eight bits
per character, plus optional even or odd parity. The
transmitter can supply one, one-and-a-half or two
stop bits per character and can provide a break output at any time. The receiver break-detection logic

MARKING LINE

SYNC

DATA

CRC,

DATA

CRC,

eRe,

DATA

eRC,

CRC,

MONOSYNC

SYNC

DATA
SIGNAL

FLAG

ADDRESS

I
I

DATA

BISYNC

EXTERNAL SYNC

INFO;~ATION

FLAG

SDLC/HDLC/X.25

230834-4

Figure 4. see Protocols

2-158

inter

82530/82530-6

sisting of continuous flag characters or a steady
marking condition.

Synchronous Modes
The SCC supports both byte-oriented and bit-oriented synchronous communication. Synchronous-byteoriented protocols can be handled in several modes
allowing character synchronization with a 6-bit or
8-bit synchronous character (Monosync), any 12-bit
or 16-bit synchronous pattern (Bisync), or with an
external synchronous signal. Leading synchronous
characters can be removed without interrupting the
CPU.

If a transmit underrun occurs in the middle of a message, an external status interrupt warns the CPU of
this status change so that an abort may be issued.
The SCC may also be programmed to send an abort
itself in case of an underrun, relieving the CPU of
this task. One to eight bits per character can be sent
allowing reception of a message with no prior information about the character structure in the information field of a frame.

5- or 7-bit synchronous characters are detected with
8- or 16-bit patterns in the sce by overlapping the
larger pattern across multiple incoming synchronous
characters as shown in Figure 5.

The receiver automatically acquires synchronization
on the leading flag of a frame in SOLC or HOLC
mode and provides a synchronization signal on the
SYNC pin (an interrupt can also be programmed).
The receiver can be programmed to search for
frames addressed by a single byte (or four bits within
a byte) of a user-selected address or to a global
broadcast address. In this mode, frames not matching either the user-selected or broadcast address
are ignored. The number of address bytes can be
extended under software control. For receiving data,
an interrupt on the first received character, or an
interrupt on every character, or on special condition
only (end-of-frame) can be selected. The receiver
automatically deletes all Os inserted by the transmitter during character assembly. CRC is also calculated and is automatically checked to validate frame
transmission. At the end of transmission, the status
of a received frame is available in the status registers. In SOLC mode, the SCC must be programmed
to use the SOLC CRC polynomial, but the generator
and checker may be preset to all 1s or all Os. The CRC
is inverted before transmission and the receiver
checks against the bit pattern 0001110100001111.

CRC checking for Synchronous byte-oriented mode
is delayed by one character time so that the CPU
may disable CRC checking on specific characters.
This permits the implementation of protocols such
as IBM Bisync.
Both CRC-16 (X 16
(X16

X12

+ X15 + X2 + 1) and CCITT
+ 1) error checking polynomials

are supported. Either polynomial may be selected in
all synchronous modes. Users may preset the CRC
generator and checker to all 1s or all Os. The SCC
also provides a feature that automatically transmits
eRC data when no other data is available for transmission. This allows for high-speed transmissions
under OMA control, with no need for CPU intervention at the end of a message. When there is no data
or CRC to send in synchronous modes, the transmitter inserts 6-, 8-, or 16-bit synchronous characters,
regardless of the programmed character length.
The sce supports synchronous bit-oriented protocols, such as SOLC and HOLe, by performing automatic flag sending, zero insertion, and CRC generation. A special command can be used to abort a
frame in transmission. At the end of a message, the
SCC automatically transmits the CRC and trailing
flag when the transmitter underruns. The transmitter
may also be programmed to send an idle line con-

NRZ, NRZI or FM coding may be used in any 1X
mode. The parity options available in asynchronous
modes are available in synchronous modes.
The SCC can be conveniently used under OMA control to provide high-speed reception or transmission.

5 BITS

SYN~

SYNC

DATA

-------

DATA

230834-5

Figure 5. Detecting 5- or 7-Bit Synchronous Characters

2-159

inter·

82530/82530-6

insertion during messages, this bit pattern is unique
and easily recognized.

In reception, for example, the SCC can interrupt the
CPU when the first character of a message is received .. The CPU then enables the OMA to transfer
the message to memory. The SCC then issues an
end-of-frame interrupt and the CPU can check the
status of the received message. Thus, the CPU is
freed for other service while the message is being
received. The CPU may also enable the OMA first
and have the SCC interrupt only on end-of-frame.
This procedure allows all data to be transferred via
OMA.

When a secondary station has·a message to transmit and recognizes an EOP on the line, it changes
the last binary one of the EOPto a zero before
transmission. This has the effect of turning the EOP
into a flag sequence. The secondary station now
places its message on the loop and terminates the
message with an EOP. Any secondary stations·further down the loop with messages to transmit can
then append their messages to the message of the
fir:st secondary station by the same process. Any
secondary ,stations without messages to send merely echo the incoming messages and are prohibited
from placing messages on the loop (except upon
recognizing an EOP).

SOLe LOOP MODE
The SCC supports SOLC Loop mode in addition to
normal SOLC. In a loop topology, there is a primary
controller station that manages the message traffic
flow and any number of secondary stations. In Loop
mode, the SCC performs the functions of a secondary station while an SCC operating in regular SOLC
mode can act as a controller (Figure 6).

SOLC Loop mode is a programmable option in the
SCC. NRZ, NRZI,.and FM coding may all be used in
SOLC Loop mode.

BAUD RATE GENERATORS
Each channel in the SCC contains a programmable
Baud rate generator. Each generator consists of two
8-bit time constant registers that form a 16-bit time
, constant, a 16-bit down counter,. and a flip-flop on
the output producing a square wave. On startup, the
flip-flop on the output is set in a High state, the value
in the time constant register is loaded into the counter, and the counter starts counting down. The output of the baud rate. generator toggles upon reaching zero, the value in the time constant register is
loaded into the counter, and the process is repeated. The time constant may be changed at any time,
but the new value does not take effect until the next
load of the counter.
The output of the baud rate generator may be used' .
as either the transmit clock, the receive clock, or
both. It can also drive the digital phase-locked loop
(see next section).

230834-6

Figure 6. An SOLe Loop
A secondary station in an SOLC Loop is always listening to the messages being sent around the loop,
and in fact must pass these messages to the rest of
the loop by retransmitting them with a one-bit-time
delay. The secondary station can place its own message on the loop only at specific times. The control- .
ler Signals that secondary stations may transmit
messages by sending a special character, called an
EOP (End of Poll), around the loop. The EOP character is the bit pattern 11111110. Because of zero

If the receive clock or transmit clock is not programmed to come from the TRxC pin, the output of
the baud rate generator may be echoed out via the
TRxC pin.
.
The following formula relates the time constant to
the baud rate. (The baud rate is in bits/second, the
BR clock frequency is in Hz, and clock mode is 1,
16,32, or 64.)
time
BR clock frequency
constant = 2 x baud rate x clock mode - 2

2-160

intJ

82530/82530-6

In NRZ encoding, a 1 is represented by a High level
and a 0 is represented by a Low level. In NRZI encoding, as 1 is represented by no change in level
and a 0 is represented by a cha:nge in level. In FM1
(more properly, bi-phase mark) a transition occurs at
the beginning of every bit cell. A 1 is represented by
an additional transition at the center of the bit cell
and a 0 is represented by no additional transition at
the center of the bit cell. In FMo (bi-phase space), a
transition occurs at the beginning of every bit cell. A
o is represented by an additional transition at the
center of the bit cell, and a 1 is represented by no
additional transition at the center of the bit cell. In
addition to these four methods, the SCC can be
used to decode Manchester (bi-phase level) data by
using the DPLL in the FM mode and programming
the receiver for NRZ data. Manchester encoding always produces a transition at the center of the bit
cell. If the transition is 011 the bit is a O. If the transition is 110 the bit is a 1.

Table 3. Time Constant Values for Standard
Baud Rates at BR Clock = 3 9936 MHz
Time Constant
Rate
Error
(BAUD)
(decimal notation)

19200
9600
7200
4800
3600
2400
2000
1800
1200
600
300
150
134.5
110
75
50

102
206
275
414
553
830
996
1107
1662
3326
6654
13310
14844
18151
26622
39934

0.12%

0.06%
0.04%
0.03%

0.0007%
0.0015%

DIGITAL PHASE LOCKED LOOP

AUTO ECHO AND LOCAL LOOPBACK

The SCC contains a digital phase locked-loop
(DPLL) to recover clock information from a datastream with NRZI or FM encoding. The DPLL is driven by a clock that is nominally 32 (NRZI) or 16 (FM)
times the data rate. The DPLL uses this clock, along
with the datastream, to construct a clock for the
data. This clock may then be used as the SCC receive clock, the transmit clock, or both.
For NRZI coding, the DPLL counts the 32X clock to
create nominal bit times. As the 32X clock is counted, the DPLL is searching the incoming datastream
for edges (either 1/0 or 0/1). Whenever an edge is
detected, the DPLL makes a count adjustment (during the next counting cycle), producing a terminal
count closer to the center of the bit cell.
For FM encoding, the DPLL still counts from 1 to 31,
but with a cycle corresponding to two bit times.
When the DPLL is locked, the clock edges in the
datastream should occur between counts 15 and 16
and between counts 31 and O. The DPLL looks for
edges only during a time centered on the 15/1 6
counting transition.

The SCC is capable of automatically echoing everything it receives. This feature is useful mainly in
asynchronous modes, but works in synchronous and
SDLC modes as well. In Auto Echo mode TxD is
RxD. Auto Echo mode can be used with NRZI or FM
encoding with no additional delay, because the datastream is not decoded before retransmission. In
Auto Echo mode, the CTS input is ignored as a
transmitter enable (although transitions on this input
can still cause interrupts if programmed to do so). In
this mode, the transmitter is actually bypassed and
the programmer is responsible for disabling transmit- .
ter interrupts and READYIREQUEST on transmit.
The SCC is also capable of local loopback. In this
mode, TxD is RxD just as in Auto Echo mode. However, in Local Loopback mode, the internal transmit
data is tied to the internal receive data and RxD is
ignored (except to be echoed out via TxD). CTS and
CD inputs are also ignored as transmit and receive
enables. However, transitions on these inputs can
still cause interrupts. Local Loopback works in asynchronous, synchronous and SDLC modes with NRZ,
NRZI or FM coding of the data stream.

The 32X clock for the DPLL can be programmed to
come from either the RTxC input or the output of the
baud rate generator. The DPLL output may be programmed to be echoed out of the SCC via the TRxC
pin (if this pin is not being used as an input).

DATA ENCODING
The'SCC may' be programmed to encode and decode the serial data in four different ways (Figure 7).

2-161

SERIAL BIT RATE
To run the 82530 (4 MHz/6 MHz) at 1/1.5 Mbps the
receive and transmit clocks must be externally generated and synchronized to the system clock. If the
serial cJocks (RTxC and TRxC) and the system clock
(CLK) are asynchronous, the maximum bit rate is
880 Kbps/1.3 Mbps. For self-clocked operation, i.e
using the on chip DPLL, the maximum bit rate is
125/187 Kbps if NRZI coding is used and 250/375
Kbps if FM coding is used.

82530/82530-6

I
I

DATAl

BIT CELL LEVEL:

;---~----,

1----...:

HIGH ~ 1
LOW~O

1--_ _....;

FMo

BIT CENTER TRANSITION:

FM,
(BIPHASE MARK)

(BIPHASE SPACE)

NO CHANGE
CHANGE" 0

TRANSITION" 1

I----~I NO TRANSITION ~ 0
NO TRANSITION

I-----!

TRANSITION" 0

IHIGH_LOW~l

LOW_HIGH~O

230834-7

Figure 7. Data Encoding Methods
Table 4. Maximum Bit Rates
Mode

Serial clocks
generated
externally

Self·clocked
operation
NRZI
FM
ASYNC

System
Clock

System Clock!
Serial Clock

Serial Bit Rate

4MHz

1 Mbps

6MHz

1.5 Mbps

4MHz

4.5

880 Kbps

6MHz

4.5

1.3 Mbps

4MHz
6MHz
4MHz
6MHz
4MHz
6MHz

32
32
16
16
16
16

125 Kbps
187 Kbps
250 Kbps
375 Kbps
62.5 Kbps
93.75 Kbps

1/0 INTERFACE CAPABILITIES
The SCC offers the choice of Polling, Interrupt (vectored or nonvectored) and Block Transfer modes to
transfer data, status, and control information to and
from the CPU. The Block Transfer mode can be implemented under CPU or OMA control.

POLLING
All interrupts are disabled. Three status registers in
the SCC are automatically updated whenever any

Conditions

Serial clocks synchronized with system
clock. Refer to parameter # 3 and 10 in
general timings.
Serial clocks synchronized with system
clock. Refer to parameter # 3 and # 10
. in general timings.
Serial clocks and system clock
asynchronous.
Serial clocks and system clock
asynchronous

function is performed. For example, end-of-frame in
SOLC mode sets a bit in one of these status registers. The idea behind polling is for the CPU to periodically read a status register until the register contents indicate the need for data to be transferred.
Only one register needs to be read; depending on its
contents, the CPU either writes data, reads data, or
continues. Two bits in the register indicate the need
for data transfer. An alternative is a poll of the Interrupt Pending register to determine the source of an
interrupt. The status for both channels resides in
one register.

2-162

inter

82530/82530-6

INTERRUPTS
When a SCC responds to an Interrupt Acknowledge
signal (INTA) from the CPU, an interrupt vector may
be placed on the data bus. This vector is written in
WR2 and may be read in RR2A or RR2B (Figures 9
and 10).
To speed interrupt response time, the SCC can
modify three bits in this vector to indicate status; If
the vector is read in Channel A, status is never included; if it is read in Channel B, status is always
included.
Each of the six sources of interrupts in the SCC
(Transmit, Receive and External/Status interrupts in
both channels) has three bits associated with the
interrupt source: Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). Operation of the IE bits is straightforward. If the IE bit is set
for a given interrupt source, then that source dan
request interrupts. The exception is when the MIE
(Master Interrupt Enable) bit in WR9 is reset and no
interrupts may be requested. The IE bits are writeonly.
The other two bits are related to the interrupt priority
chain (Figure 8). As a peripheral, the SCC may request an interrupt only when no higher-priority device is requesting one, e.g., when lEI is High. If the
device in question requests an interrupt, it pulls
down INT. The CPU then responds with INTA, and
the interrupting device places the vector on the data
bus.
In the SCC, the IP bit signals a need for interrupt
servicing. When an IP bit is 1 and the lEI input is
High, the INT output is pulled Low, requesting an
interrupt. In the SCC, if the IE bit is not set by enabling interrupts, then the IP for that source can never be set. The IP bits are readable in RR3A.

The IUS bits Signal that an interrupt request is being
serviced. If an IUS is set, all interrupt sources of lower priority in the SCC and external to the SCC are
prevented from requesting interrupts. The internal
interrupt sources are inhibited by the state of the
internal daisy chain, while lower priority devices are
inhibited by the lEO output of the SCC being pulled
Low and propagated to subsequent peripherals. An
IUS bit is set during an Interrupt Acknowledge cycle
if there are no higher priority devices requesting interrupts.
There are three types of interrupts: Transmit, Receive and External/Status interrupts. Each interrupt
type is enabled under program control with Channel
A having higher priority than Channel B, and with
Receiver, Transmit and External/Status interrupts
prioritized in that order within each channel. When
the Transmit interrupt is enabled, the CPU is interrupted when the transmit buffer becomes empty.
(This implies that the transmitter must have had a
data character written into it so that it can become
empty.) When enabled, the receiver can interrupt the
CPU in one of three ways:
• Interrupt on First Receive Character or Special
Receive condition.
• Interrupt on all Receive Characters or Special
Receive condition.
• Interrupt on Special Receive condition only.
Interrupt-on-First-Character or Special-Condition
and Interrupt-on-Special-Condition-Only are typically
used with the Block Transfer mode. A Special-Receive-Condition is one of the following: receiver
overrun, framing error in Asynchronous mode, Endof-Frame in SOLC mode and, optionally, a parity
error. The Special-Receive-Condition interrupt is different from an ordinary receive character available
interrupt only in the status placed in the vector

see

HIGHEST PRIORITY

see

LOWEST PRIORITY

+5V

DBO-DB7
INT

INTA

»---~~----------~------------------~------------------~
+5V

230834-8

Figure 8. Daisy Chaining SCC's

2-163

inter

82530/82530-6

06 = 0) or as a request line in the DMA Block
Transfer mode (WR1; 06 = 1). To a DMA controller,
the SCC REQUEST output indicates that the SCC is
ready to transfer data to or from memory. To the
CPU, The READY line indicates that the SCC is not
ready to transfer data, thereby requesting that the
CPU extend the I/O cycle. The DTR/REQUEST line
allows full-duplex operation under DMA control.

during the Interrupt-Acknowledge cycle. In Interrupt
on First Receive Character, an interrupt can occur
from Special Receive conditions any time after the
first receive character interrupt.
The main function of the External/Status interrupt is
to monitor the signal transitions of the CTS, CD, and
SYNC pins; however, an External/Status interrupt is
also caused by a Transmit Underrun condition, or a
zero count in the baud rate generator, or by the detection of a Break (asynchronous mode), Abort
(SDLC mode) or EOP (SDLC Loop mode) sequence
in the data stream. The interrupt caused by the
Abort or EOP has a special feature allowing the SCC
to interrupt when the Abort or EOP sequence is detected or terminated. This feature facilitates the
proper termination of the current message, correct
initialization of the next message, and the accurate
timing of the Abort condition in external logiC in
SDLC mode. In SDLC Loop mode this feature allows
secondary stations to recognize the wishes of the
primary station to regain control of the loop during a
poll sequence.

PROGRAMMING
Each channel has fifteen Write registers that are individually programmed from the system bus to configure the functional personality of each channel.
Each channel. also has eight Read registers from
which the system can read Status, Baud rate, or Interrupt information.
Only the four data registers (Read, Write for channels A and B) are directly selected by a High on the
D/G input and the appropriate levels on theRD, WR
and AlB pins. All other registers are addressed indirectly by the content of Write Register Oin conjunction with a Low on th.e D/G input and the appropriate
levels on the RD, WR and AlB pins. If bit 3 in WWO
is 1 and bits 4 and 5 are 0 then bits 0, 1, 2 address
the. higher registers 8 through 15. If bits 3, 4, 5 contain a different code, bits 0, 1, 2 address the lower
registers 0 through 7 as shown on Table 5.

CPU/DMA BLOCK TRANSFER
The SCC provides a Block Transfer mode to accommodate CPU block transfer functions and DMA controllers. The Block Transfer mode uses the READY/
REQUEST output in conjunction with the READY /
REQUEST bits in WR1. The READY/REQUEST output can be defined under software control as a
READY line in the CPU Block Transfer mode (WR1;

Writing to or reading from any register except RRO,
WRO and the Data Registers thus involves two operations.

Table 5. Register Addressing
.'

O/C "Point High"
Code in WRO

High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low

Either Way
Not True
Not True
Not True
Not True
Not True
Not True
Not True
Not True
True
True
True
True
True
True
True
True

Write
Register

Read
Register

0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Data
0
1
2
3

Data

Data
0
1
2
3
(0)
(1 )
(2)
(3)
Data

10
11
12
13
14
15

10
(15)
12
13
(10)
15

D2
inWRO

0
0
0
1
1
1
1

0
1
1
0
0
1
1
0
0

1
1

0
0
0
0
1

2-164

4
5
6

inter

82530/82530-6

First write the appropriate code into WRO, then follow this by a write or read operation on the register
thus specified. Bits 0 through 4 in WWO are automatically cleared after this operation, so that WWO then
points to WRO or RRO again.

(RR12 and RR13) may be read to determine the
baud rate generator time constant. RR2 contains either the unmodified interrupt vector (Channel A) or
the vector modified by status information (Channel
B). RR3 contains the Interrupt Pending (IP) bits
(Channel A). Figure 9 shows the formats for each
read register.

Channel AlChannel B selection is made by the AlB
input (High = A, Low = B)

The status bits of RRO and RR1 are carefully
grouped to simplify status monitoring: e.g. when the
interrupt vector indicates a Special Receive Condition interrupt, all the appropriate error bits can be
read from a single register (RR1).

The system program first issues a series of commands to initialize the basic mode of operation. This
is followed by other commands to qualify conditions
within the selected mode. For example, the Asynchronous mode, character length, clock rate, number of stop bits, even or odd parity might be set first.
Then the interrupt mode would be set, and finally,
receiver or transmitter enable.

WRITE REGISTERS
The SCC contains 15 write registers (16 counting
WRB, the transmit buffer) in each channel. These
write registers are programmed separately to configure the functional "personality" of the channels. In
addition, there are two registers (WR2 and WR9)
shared by the two channels that may be accessed
through either of them. WR2 contains the interrupt
vector for both channels, while WR9 contains the
interrupt control bits. Figure 10 shows the format of
each write register.

READ REGISTERS
The SCC contains eight read registers (actually nine,
counting the receive buffer (RRB) in each channel).
Four of these may be read to obtain status information (RRO, RR1, RR10, and RR15). Two registers

R. CIfARACTEII AVAILABLE

ZERO COUNT
_ _ _ T. BUFFER EMPTY
_ _ _ _ _ CD
~

1..-_ _ _ _ _ _ SYNClHUNT

' __ _ _ _ _ _ _ _ CTS

' - - - - - - - - - - - Tx UNDERRUNlEOM
1..------------8R~OO~

230834-9

ALL SENT
RESIDUE CODE 2
' - - - - - RESIDUE CODE 1

~-'----- RESIDUE CODE 0

~------- MRITYERROR
' - - - - - - - - - - AI OVERRUN ERROR
~-----------CR~RUM~GERROR

~------------ END OF FRAMEISOLC)

Figure 9. Read Register Bit Functions

2-165

230834-10

82530/82530-6

v,
I-..---~

INTERRUPT VECTOR'

' - - - - - - - - V,

'----------~

I-..--,;.,..-----VS
~------------------~

~----------------------------~
'MODIFIED IN B CHANNEL

230834-11

CHANNEL B EXT/STAT IP'
CHANNEL B TxIP'
'------CHANNEL B RxIP'
'--------'CHANNEL A EXT/STAT II'"
' - - - - - - - - - - C H A N N E L A TxIP'
' - - - - - - - - - - - - C H A N N E L A RxIP'

~------------------O

'---------------0
'ALWAYS 0 IN B CHANNEL

230834-12

o
ON LOOP
......- - - - - - - 0

1-..------0
' - - - - - - - - - LOOP SENDING

1...------------------

0 .

' - - - -.......- - - - - - - - TWO CLOCKS MISSING
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ ONE CLOCK MISSING

230834-13

Figure 9, Read Register Bit Functions (Continued)

2-166

inter

82530/82530-6

TCo
TC,
TC.
TC.
TC.

LOWER BYTE OF
TIME CONSTANT

TCS

TeTC,

230834-14

TC.
TC.
1..-_ _ _ _ TC,.

-_
-_
-_
-_
-_
-_
-_
- TC"
L-_ '
_
TC,.

UPPER BYTE OF
TIME CONSTANT

' - - - - - - - - - - - - TC,.

' - - - - - - - - - - - - - - TC,.
' - - - - - - - - - - - - - - - TC,S

230834-15

o
ZERO COUNT IE
'------ 0
' - - - - - - - CD IE
' - - - - - - - - - SYNC/HUNT IE
' - - - - - . . ; . . . . - - - - - - CTS IE
' - - - - - - - - - - - - - TI UNDERRUNlEOM IE
' - - - - - - - - - - - - - - - BREAK/ABORT IE

Figure 9. Read Register Bit Functions (Continued)

2-167

230834-16

, Inter

82530/82530-6

WRITE REGISTER 0
IOrio.

Os ID4

D3ID2IDl

I
-

Do I
REGISTER

001'

10r

20r

0
1

1
0

30r

401'

501'

SOl'

70r

NULL CODE

0
0

POINT HIGH REGIST
RESET EXT/STATU S INTERRUPTS

1
0

SEND ABORT
ENABLE INT ON NEXT RII CHARACTER

RESET Tx INT PENDING

ERROR RESET

RESET HIGHEST IUS·

·CHANNEL·A ONLY

NULL CODE

RESET Rx CAe CHECKER

RESET Tx CRC GENERATOR

RESET TIl UNDERRUNlEOM LATCH
230834-17

WRITE REGISTER 1

EXT. INT ENABLE
TaiNT ENABLE

"-----PIIUIITY IS SPECIAL CONDITION

RxlNT ON FIRST CHARACTER OR SPECIAL CONDITION

INT ON ALL Ra CHARACTERS OR SPECIAL CONDITION

RalNT DISABLE

1 AI INT ON SPECIAL CONDITION ONLY
.L..;....L...-I

"------""AIEADYlDMA REQUEST ON RECEIVEITIIANSMIT
"---,......-----READYIDMA REQUEST FUNCTION
L----------READYIDMAREQUESTE~

230834-19

Figure 10. Write Register Bit Functions

intJ

82530/82530-6

. . .-------V3

INTERRUPT VECTOR

~---------- ~

.....- - - - - - - - - - - Vs
' - - - - - - - - - - - - - - V,
.....- - - - - - - - - - - - - - V7

230834-21

R. ENABLE
SYNC CHARACTER LOAD INHIBIT
.....- - - - ADDAESS SEARCH MODE (SDLC)
' - - - - - - - R. CRC ENABLE

~-------- ENTER HUNT MODE
' - - - - - - - - - - - - AUTO ENABLES

o
o

A. 5 BIT8ICHAAACTER
R.7BnwCHAAACTER

~~-!--IR•• BnwCHARACTER
,--,_""A. 8 BnwCHARACTEA

230834-18

WRITE REGISTEA 4

10,

1 ,1 °1
0

MAlTY ENABLE

MAlTY EVEN/ODD

SYNC MODE SENABLE

1 STOPBIT/C HAAACTER

l'h STOP BITSlCHARACTER

2 STOPBITSICHARACTER

• BIT SYNC CHARACTEA

11 BIT SYNC CHARACTER

SOLC MODE (01111110 FLAG)

EXTERNAL SYNC MODE

XI CLOCK MODE

XII CLOCK MODE

X32 CLOCK MODE

XI4 CLOCK MODE

230834-20

Figure 10. Write Register Bit Functions (Continued)

2-169

82530/82530-6

TICRCENAB~

RTS
Il5'U:ICRC-l.
TIENABLE
' -_ _ _ _ _ _ _ _ SEND BREAK

TI 5 BITS (OR LESS)ICHARACTER

TI 7 BITS/CHARACTER

~~-:""-t

TI 6 BITS/CHARACTER
TI8 BITS/CHARACTER
DTR

SYNC7
SYNC,
SYNC7
SYNCa
AOR7
AOR7

SYNCs
SYNCo
SYNCs
SYNCz
ADR,
ADRo

SYNCs
SYNCS
SYNCs
SYNC,
ADRs
ADRs

SYNC.
SYNC.
SYNC.
SYNCo
ADA4
ADA4

SYNC3
SYNC3
SYNC3
1
ADR3
X

SYNCz
SYNCz
SYNCz
1
AORz

SYNC,
SYNC,
SYNC,
1
ADR,
X

230834-22

SYNCo
SYNCo
SYNCo
1
ADRo
X

230834-23

SYNCr
SYNCs
SYNC"
SYNC"

SYNC.
SYNC.
SYNC,.
SYNC,o
1

MONOSYNC 8 BITS
MONOSYNC 6 BITS
BISYNC 16 BITS
BISYNC 12 BITS
SDLC
SDLC (ADDRESS RANGE)

SYNCs
SYNC,
SYNC'3
SYNCs
1

SYNC.
SYNCZ
SYNC,z
SYNC,
1

SYNC3
SYNC,
SYNC"
SYNCr
1

SYNCz
SYNCO
SYNC,o
SYNCt
1

SYNC,

SYNCo

SYNCt
SYNC,
1

SYNC,
SYNC.

MONOSYNC 8 BITS
MONOSYNC 8 BITS
BISYNC 18 BITS
BISYNC 12 BITS
SDLC

230834-24

Figure 10. Write Register Bit Functions (Continued)

2-170

inter

82530/82530-6

VECTOR INCLUDE STATUS
NO VECTOR
....._ _ _ _ DISABLE LOWER CHAIN

L.._ _ _ _ _ _ MASTER INTERRUPT ENABLE
.....--------STATUSHIGH/STATUS LOW
L.._ _ _ _ _ _ _ _ _ _ NON.VECTORED MODE'
NO RESET
CHANNEL RESET 8
CHANNEL RESET A
FORCE HARDWARE RESET

230834-25
'See 82530 Technical User's Manual for details of this mode.
(Document # 230925·002 or ·003)

6 BIT liiBiT SYNC
LOOP MODE
' -_ _ _ _ _ ABORT/i'iAll ON UNDERRUN
.....-------"MARK/I'lJ\G IDLE
.....- - - - -_ _ _ _ GO ACTIVE ON POLL

~-+--4

......~~-I

NRZ
NRZI
FMI (TRANSMISSION

L..;,.."IL........ FMO (TRANSMISSION

......~f-:~

' - - - - - - - - - - - - - - - CRCPRESET 110

fiiiC OUT;

230834-27

.TAL OUTPUT

TRIC OUT' TRANSMIT CLOCK
TliiC OUT' 8R GENERATOR OUTPUT

TIid: OUT'

DPLL OUTPUT

....-~-- 'TIIie 011
TRANSMIT CLOCK·

IIr.e PIN

TRANSMIT CLOCK • ~ PIN
TRANSMIT CLOCK' 8R GENERATOR OUTPUT
TRANSMIT CLOCK' DPLL OUTPUT
RECEIVE CLOCK'
RECEIVE CLOCK'

IIr.e PIN
'rJIie PIN

RECEIVE CLOCK' 8R GENERATOR OUTPUT
RECEIVE CLOCK' DPLL OUTPUT

'--------------lifiC

)(TAL/No Xtil

Figure 10, Write Register Bit Functions (Continued)
2-171

230834-29

infef

82530/82530-6

'----:: I
TC2

' - - - - - - - TC,
L.._______

LOWER BYTE OF

TC.
TCS \ TIME CONSTANT

~__________

' - -__- - - - - - _ _ _ _

L.._____________________ TC,

230634-26

:~: 1

......- - - - - TC,o
.....- - - - - - - - - - - - - TCII

UPPER BYTE OF

T.C'2 \ TIME CONSTANT
TCu

' - - - - - - - - - - - - - - - - - - - - - - - - - TC, •
.....- - - - - - - - - - - - - - - - - - - - - - - - TC,s

230634-26

WlllTlIIIOIITER 14

10.10.

I I I
D.

D2( 0,

Do ]

BR GENERATOR ENABLE
BR GENERATOR SOURCE
REQUEST FUNCTION
AUroECHO

LOCAL LOOPBACK

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
D
1

0
1

NULL COMMAND
ENTER SEARCH MODE
RElET MilliNG CLOCK
DISABLE DPLL
SET SOURCE' BR GENE RAT OR
SET SOURCE'
SETFMMODE

IWi1!

SET NRZI MODE

230834-30

Figure 10. Write Register Bit Functions (Continued)

2-172

infef

82530/82530-6

o
ZERO COUNT IE

. . . ----0

......- - - - - - CD IE

L...._ _ _ _ _ _ _ SYNC/HUNT IE

.....- - - - - - - - - CTSIE
......- - - - - - - - - - - Ta UNDERRUNlEOM IE
......- - - - - - - - - - - - BREAK/ABORT IE

230634-:31

Figure 10. Write Register Bit Functions (Continued)

82530 TIMING
The SCC generates internal control signals from WR
and RD that are related to ClK. Since ClK has no
phase relationship with WR and RD, the circuitry
generating these internal control signals must pro·
vide time for metastable conditions to disappear.
This gives rise to a recovery time related to ClK.
The recovery time applies only between bus transactions involving the SCC. The recovery time required for proper operation is specified from the rising edge of WR or RD in the first transaction in·

NB.WC ________J)(~

volving the SCC to the falling edge of WR or RD in
the second transaction involving the SCC. This time,
T REC must be at least 6 ClK cycles plus 130 ns, for
the 82530·6.

Read Cycle Timing
Figure 11 illustrates Read cycle timing. Addresses
on AlB and DIG and the status on INTA must remain stable throughout the cycle. If CS falls after RD
falls or if it rises before RD rises, the effective RD is
shortened.

___________________

A_O_D_R_E_S_S_VA_L_ID____________

--J)(~____

\'---/

\'---_ _ _ _..-J/
DBO-DB7

------------------"--~(\.____________'X

DATA VALID

)>---230634-32

Figure 11. Read Cycle Timing

2-173

82530/82530-6

Write Cycle Timing

Interrupt Acknowledge Cycle Timing

Figure_12 illustr~tes Write cycle timi~ddresses
on AlB and D/C and the status on INTA must remain stable throughout the cycle. If CS falls after
WR falls or if it rises before WR rises, the effective
WR is shortened.

Figure 13 illustrates Interrupt Acknowledge cycle
timing. Between the time INTA goes Low and the
falling edge of RD, the internal and external IEIIIEO
daisy chains settle. If there is an interrupt pending in
the SCC and lEI is High when RD falls, the Acknowledge cycle is intended for the SCC. In this case, the
SCC may be programmed to respond to RD Low by
placing its interrupt vector on 00-07 and it then sets
the appropriate Interrupt-Under-Service internally.

Alii, Dlf

INTA

ADDRESS VALID

DBO-DB7

\
/

(

DATA VALID

230834-33

Figure 12. Write Cycle Timing

INTA·\

II
AD

DBO-DB7

,Figure 13. Interrupt Acknowledge Cycle Timing

2-174

VECTOR

)
230834-34

inter

82530/82530-6

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Case Temperature
Under Bias ...................... O°C to + 70°C

Storage Temperature
Ceramic Package ............ - 65°C to + 150°C
Plastic Package ............. - 40°C to + 125°C
Voltage on Any Pin with
Respect to Ground ............ - 0.5V to + 7.0V

D.C. CHARACTERISTICS

T e = O°C to 70°C; Vee = + 5V ± 5%

Min

Max

Units

Input Low Voltage

-0.3

+0.8

VIH

Input High Voltage

+2.4

Vee +0.3

VOL

Output Low Voltage

+0.45

VOH

Output High Voltage

IlL

Input Leakage Current

±10

/LA

O.4V to 2.4V

IOL

Output Leakage Current

±10

/LA

O.4V to 2.4V

lee

Vee Supply Current

250

Symbol
VIL

Parameter

CAPACITANCE
Symbol

25°C; Vee

+2.4

GND

Parameter

Test Conditions

= 2.0 mA
IOH = -250/LA

IOL

Min

Max

Units

Test Conditions

CIN

Input Capacitance

te = 1 MHz

COUT

Output Capacitance

ClIO

Input/Output Capacitance

Unmeasured pins
returned to GND

2-175

intJ

82530/82530-6

A.C CHARACTERISTICS Tc = O°Cto +70°C;Vcc = +5V ±5%
READ AND WRITE TIMING
Number

82530 (4 MHz)

Symbol

Parameter

82530-6 (6 MHz)

Min

Max

Min

Max

Units

tCl

ClKlowTime

105

2000

1000

tCH

ClK High Time

105

2000

1000

ClK Fall Time

ClK Rise Time

tCY

ClK Cycle Time

tAW

Address to WR

250
Setup Time

tWA

Address to WR i Hold Time

tAR

Address to RD

tRA

tiC

4000

165

2000

Address to RD i Hold Time

INTA to ClK i Setup Time

Setup Time

tlW

.1 NTA

200

tWI

INTA to WR i Hold Time

tlR

INTA to RD

200

tRI

INTA to RD i Hold Time

tCI

INTA to ClK t Hold Time

100

tClW

CS low to WR

tWCS

CS to WR i Hold Time

tCHW

CS High to WR

tClR

t Setup Time
CS low to RD t Setup Time (Note 1)

tRCS

CS to RD i Hold Time (Note 1)

tCHR

CS High to RD

tRR

RD low Time (Note 1) ,

Null

Parameter Deleted

tRDI

RD i to Data Not Valid Delay

tRDV

tDF

RD i to Output Float Delay (Note 2)

to WR

Setup Time (Note 1)

Setup Time

Setup Time (Note 1)

100

390

150

to Data Valid Delay

ns -

0
250

105

NOTES:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Float delay is defined as the time required for a + O.5V change in the output with a maximum D.C. load and minimum A.C.
load.

2-176

82530/82530-6

A.C. TESTING INPUT, OUTPUT WAVEFORM

OPEN DRAIN TEST LOAD
+5V

2.2K

230834-35
A.C. Testing: Inputs are driven at 2.4V for a Logic "t" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "I" and 0.8V for a Logic "0".

A.C. TESTING LOAD CIRCUIT

230834-42

OEVICE
UNDER
TEST

~CL"150PF
-=
230834-41

CL = 150pF
CL Includes Jig Capacitance

~B.~C===>~__~__~____-t______+-________~______~~~~~~~_________

1--(.,.--

_(0).

V
_
_
+-~~=\"lOT:::-t®,.....es
f-l1 @_

:I® -

i-@-L ](

INTA

-@r---'
- ~
i-----'-r-'----

--~~_+--~--~-----+--_4~~

--+--+---:L@!if)
I-®_ .,.......-+----I---.....:f

I--@-

t----+-----{-@I---------lC-@-r-

f-@-l\...-

READ
FDOO-DB7---1-----~_tr1~~=t=====1==)(~==~=lt=~~_t----t_----------_t~
@- -I
@
'-l
I---t-@)--t--I
t------i--@-t----r--l

I-+®

r-@-

D80.D=-------t."'vr,J:-~==E=;®~21~~~~t:-:-=-:-~~U__.l.._------~'-=
:K
WRITE

RE~~~~EQ

------~~~J1.L~--~~-----+---4~~'(~-3D--------___________-I_IeI,;;;;~_-.:.....'*__........;(\!!J+1__.....
I' I \eI

\--

t--~+_I@I~~-j~-+_-___~-------

R~:g~~~~Q ------------I------..I-;::::-Q---::u+I---.J1
i5'iiiiiiEQ

I-@...r-------

REQUEST ________________________~~--------+-----------'J

@----------------------I---------~I--~(
\

~------------------230834-36

Figure 14. Read and Write Timing
2-177

inter

82530/82530-6

INTERRUPT ACKNOWLEDGE TIMING, RESET TIMING, CYCLE TIMING
Number Symbol

82530 (4 MHz)

Parameter

Min
27

tAD

Address Required Valid to Read Data
Valid Delay

TWW

WRlowTime

tDW

tWD

Data to WR

Max

82530-6 (6 MHz)
Min

590

Units

Max
325

390

Data to WR J. Setup Time

Hold Time

tWRV

WR J. to Ready Valid Delay (Note 4)

240

200

tRRV

AD J.

240

200

tWRI

WR J. to READY/REO Not Valid Delay

240

200

tRRI

RD J. to READY/REO Not Valid Delay

240

200

tDWR

to DTR/REO Not Valid Delay

5tCY
+300

5tCY
+250

tDRD

AD t

to DTR/REO Not Valid Delay

5tCY
+300

5tCY
+250

tliD

INTA to RDJ, (Acknowledge) Delay
(Note 5)

250
285

to Ready Valid Delay (Note 4)

250

til

RD (Acknowledge) low Time

tlDV

RD J. (Acknowledge) to Read Data
Valid Delay

tEl.

lEI to RD J. (Acknowledge) Setup Time

tiE

lEI to RD

tEIEO

lEI to lEO Delay Time

tCEO

ClK

tRIl

Fii5T to INT Inactive Delay (Note 4)

tRW

tWR

t to WR J. Delay for No Reset
WR t to RD J. Delay for No Reset

tRES

WR and RD Coincident low for Reset

250

tREC

Valid Access Recovery Time
(Note 3)

6tCY
+200

6tCY
+130

(Acknowledge) Hold Time

125
190

120

100

NOTES:

ns
ns

0
120

to lEO Delay

ns
100

250

500

3. Parameter applies only between transactions involving the sec.
4. Open-drain output, measured with open-drain test load.
5. Parameter is system dependent. For any sec in the daisy chain, tllO must be greater than the sum of tCEQ for the
highest priority device in the daisy chain; tEl for the see and tEIEO for each device separating them in the daisy chain.

2-178

inter

82530/82530-6

IN~----

________

RD--------------------------~~r_------~--------:L

DBO-DB7 _________________________________+-____________________

~......,:£"

lEI

lEO

®=!~-230834-37

Figure 15. Interrupt Acknowledge Timing

~--~/
230834-38

Figure 16. Reset Timing

1I~------~\.'-_______

CS _ _ _---J

_~}~---------@.~,~----~1
.J/
1\. . ._________

RD OR W R .

\'-__________________

230834-39

Figure 17. Cycle Timing

2-179

inter

82530/82530-6

GENERAL TIMING
Number Symbol

82530 (4 MHz)

Parameter

Min

Max

82530-6 (6 MHz)
Min

Units

Max

tRCC

RxC t to ClK t Setup Time (Notes 1, 4)

100

tRRC

RxD to RxC t Hold Time (X1 Mode)
(Note 1)

tRCR

FjxD to RxC t Hold Time (X1 Mode)
(Note 1)

150

tORC

RxD to RxC!. Setup Time (X1 Mode)
(Notes 1, 5)

tRCD

RxD to RxC!. Hold Time (X1 Mode)
(Notes 1, 5)

150

tSRC

SYNC to RxC t Setup Time (Note 1)

-200

'-200

tRCS

SYNC toRxC t Hold Time (Note 1)

3tCY
+200

tTCC

TxC!. to ClK t Setup Time (Notes 2, 4)

tTCT

TxC!. to TxD Delay (X1Mode) (Note 2)

300

30Q

tTCD

TxC t to TxD Delay (X1 Mode)
(Notes 2, 5)

300

tTDT

TxD to TRxC Delay (Send Clock Echo)

200

tOCH

RTxC High Time

180

150

tOCl

RTxC low Time

180

150

100

4tCY

tOCY

RTxC Cycle Time

tClCl

Crystal Oscillator Period (Note 3)

250

tRCH

TRxC High Time

180

150

tRCl

TRxC low Time

180

150

tRCY

TRxC Cycle Time (Note 6)

4tCY

tCC

CD or CTS Pulse Width

200

tSS

SYNC Pulse Width

200

tWRT

WR to RTS Valid Delay

6tCY

tWDT

WR to DTR Valid Delay

5tCY

·5tCY

.4tCY
1000

165

1000

200

NOTES:
1. RxC is RTxC or TRxC, whichever is supplying the receive clock.
2. TxC is TRxC or RTxC, whichever is supplying the transmit clock.
3. Both RTxC and SYNC have 30 pF capacitors to ground connected to them.
4. Parameter' applies only if the data rate is one-fourth the system clock (ClK) rate. In all other cases, no phase relationship
between AXe and ClK or TxC and ClK is required.
5. Parameter applies only to FM encoding/decoding.
6. Only applies to transmitter and receiver. For DPll and Baud Rate Generator Timings, the requirements ani identical to
system clock, ClK, specifications.

2-180

82530/82530-6

~~--~---t==®~

.~____~~~___________~J(~--------

230834-40

Figure 18. General Timing

2-181

APPLICATION

AP-401

.NOTE

December 1986

Designing With the 82510
Asynchronous Serial Controller

FAISAL IMDAD-HAQUE

APPLICATIONS ENGINEER

Order Number: 231928-001
2-182

DESIGNING WITH THE
82510 ASYNCHRONOUS
SERIAL CONTROLLER

CONTENTS

PAGE

1.0 INTRODUCTION ................... 2-184
1.1 Goal ............................... 2-184
1.2 Scope .............................. 2-184

2.082510 DESCRiPTION .... .......... 2-184
2.1 Overview ........................... 2-184
2.2 Bus Interface Unit (BIU) ............. 2-184

2.3 Receive Machine (RXM) ............ 2-184
2.4 Transmit Machine (TXM) ............ 2-185
2.5 Modem Interface Module ........... 2·185
2.6 Timing Unit ......................... 2-185
2.7 FIFOs, Rx and Tx ................... 2-186

3.0 HARDWARE DESiGN .............. 2-186

3.1 System Interface ................... 2-186
3.2 Reset .............................. 2-194
3.3 System Clock Options .............. 2-195
4.0 INTERRUPT BEHAVIOR ........... 2-197
4.1 FIFO Usage ........................ 2-197
4.2 Interrupt Handling .................. 2-198
4.3 Polling ............................. 2-205

5.0 SOFTWARE CONSIDERATIONS ..
5.1 Configuration .......................
5.2 Transmit Operation .................
5.3 Data Reception .....................
5.4 Timer Usage .......................
6.082510 IMPLEMENTATION OF
XMODEM ............................
6.1 XMODEM Protocol .................
6.2 Software ...........................
6.3 Software Listings ...................

2-183

2-205
2-205
2-208
2-213
2-218
2·221
2-221
2-221
2·229

InTel

AP-401

This is followed by a discussion of the hardware design
and system interface, considerations in sections three
and four. The fifth section provides some software techniques for transmitting and receiving data as well as the
use of timers. Section seven briefly discusses the file
transfer application based on the XMOOEM protocol
and includes the software listings.

1.0 INTRODUCTION
The emergence of asynchronous communications as the
most widely used protocol (it commands the largest i~
stalled base of nodes, exceeding HOLC/SOLC, the second most popular protocol, by a factor pflO to 1) for
point to point serial links has led to the need for an
asynchronous communications' component with high
integration to reduce component count and decrease
the cost of a serial port. The trend towards 'higher data
rates and multiple job, multiple user systems has underscored the need for an intelligent serial controller to
improve system throughput and decrease the CPU load
normally associated with asynchronous serial communications.
'

2.0 82510 DESCRIPTION
2.1 Overview
The 82510 can be divided into seven functional blocks
(See Figure 1): Bus Interface Unit (BIU), Timing Unit,
Modem Interface Module, Tx FIFO, Rx FIFO, Tx Machine and Rx Machine: All blocks, except BIU can generate a block interrupt request to the 82510 interrupt
logic. In the case of the Rx Machine, Timing Unit and
Modem Interface Module, multiple sources (errors and
status events) within the block cause the block interrupt
request to become active. All of the blocks have registers associated with them. The registers, allow configuration, provide status information about events/errors,
and may also be used to send commands to each block.

The 82510 CMOS Asynchronous Serial Controller is
designed to improve asynchronous communications
throughput and reduce system cost by integrating functions and simplifying the system interface. Two independent FIFOs, and Control Character Recognition
(CCR), provide data buffering and increase software
efficiency. Two Baud Rate Generators/Timers, an OnChip Crystal Oscillator and seven Programmable I/O
pins provide a high degree of integration and reduce
system component count. This, application note ,will
'demonstrate the use of these features in an Asynchronous Communications Environment.

2.2 Bus Interface Unit (BIU)

1_1 Goal
The goal of this application note is to demonstrate the
use of the major 82510 features in an asynchronous
communications environment and to depict basic hardware and software design techniques for the 82510. It
will discuss int,erfaces using both polling and interrupt
techniques, as well as the impact of FIFOs using either
scheme. An application example covering the application of Error Free File Transfer is also provided.

The Bus Interface Unit (BIU) interfaces the 82510
functional blocks to the system or CPU bus. It provid~s
read and write access to the 82510 registers and controls the generation of interrupts to the external world.
The interrupt logic resolves contention between block
interrupt requests, on a priority basis. The BIU also has
the Hardware Reset circuitry, which is driven by'the
RESET pin. The reset signal clears all internal Flip
Flops, and Registers and puts them in a predefined
state. All activities on the Bus interface, including register accesses by the CPU, are synchronized to an internal (82510) system clock, supplied via the CLK pin.

1.2 Scope
The application note describes the operation of the
82510 ASC in a normal (non 8051 9"bit) asynchronous
communications mode. The majority of the discussion
is focused towards the systems aspects of the Controller. The use of the 82510 in a multidrop or 8051 9-bit
asynchronous environment is not covered. This application note assumes that the reader is familiar with the
82510 in terms of pin description, register architecture
and interrupt structure. It is also assumed that the
reader is familiar with the information provided in the
82510 Oata Sheet.
The initial sections of the application note provide an
overview of the 82510 and its major functional blocks.

2.3 Receive Machine (RxM)
The Rx'Machine (RxM) converts the serial data to parallel imd writes it to the Rx FIFO, along with the appropriate flags (available in. the Receive Flags Register).
The Rx Machine can be configured for control character recognition, data sampling II-lld OPLL operation.
The software can check for noise, control character,
break, address or parity and framing errors by reading
the status or character flags. Optionally, the Receive
Status bits (in RST), when enabled, can generate interrupt requests. The Rx Machine block Interrupt request
is reflected in the General Status Register arid is set
when an enabled interrupt request within the Rx Ma-

2-184

inter

AP-401

chine (i.e. RST bits) becomes active. The Rx Machine
has eight registers associated with it:
Receive Data (RXD}--Receive Data Character
Receive Flags (RXF}--Receive Character Flags
Receive Status (RST}--Receive Events and Receive Errors
Receive Interrupt Enable (RIE}--Enables Interrupts
on corresponding bits in RST
Receive Mode (RMD}--Receive Machine Configuration
Receive Command (RCM}--Receiver Command Register
Line Control (LCR}--16450 Register, Character Attribute Configuration
Line Status (LSR}--I6450 Status Register, Tx and Rx
status

erate Interrupts (if enabled) upon transitions in the modem input pins (DCD, CTS, RI, and DSR). The modem output pins can be controlled by the CPU, also the
RTS pin can be used to provide flow control, in the
automatic transmission mode. It is the source of the
Modem Interrupt bit in GSR. This bit is set whenever
there is a state change in the DCD, RI, DSR or CTS
inputs (reflected in Modem Status Register) and the
corresponding enable bits are set. The function and direction of the multifunction pins can be reprogrammed
and is available as a configuration option. Multifunction pins, when configured as outputs, can be controlled by the CPU through the Modem Control Register. The Modem module has four registers associated
with it:
Modem Status
Register (MSR}--State transitions on modem input
pins, and State of the modem input pins
Modem Control (MCR}--Control state of Modem
Output pins
Modem Interrupt
Enable (MIE)-Enable Interrupt on State transitions in
modem input pins

2.4 Transmit Machine (TxM)
The Tx Machine reads characters from the Tx FIFO
and transmits them serially over the TXD line. The Tx
Machine can also transmit additional character attributes (9th bit of Data, Address Marker, Software Parity) available from the Transmit Flags, if configured in
the appropriate mode. The Tx Machine Idle interrupt
request is reflected in the GSR and LSR registers to
indicate that the Transmitter is either Empty or Disabled. The Tx Machine has six .registers associated with
it:
Line Control (LCR}--I6450 Register, Character Attribute Configuration
Line Status (LSR}--16450 Status Register, Tx and Rx
status

I/O Pin Mode (pMD}--Functions and Directions of
Multifunction pins

2.6 Timing Unit
The Timing Unit is responsible for the generation of the
.System Clock, using either its Crystal Oscillator or an
externally generated clock, and generation of the Tx
and Rx clocks from either the On-Chip Baud Rate
Generators or the SCLK pin. It is also responsible for
generating Timer Expired interrupts when the
BRGs/Timers are configured for use as Timers. There
are ten registers associated with the Timing Unit, four
of these are used in the Timer mode only.
Timer Status (TMST}--Timer A and/or Timer B expired

Transmit Mode (TMD)--Tx Machine Configuration
Transmit Command-(TCM)-Transmit Command
Register

Timer Interrupt
Enable (TMIE}--Enables Interrupts upon Expiration
of Timers A or B in TMST

Transmit Flags (TXF}--Transmit Character Flags

Timer Control (TMCR)-Start and Disable Timers

Transmit Data (TXD}--Transmit Data Character

Clock Configure (CLCF}--Select source and mode for
Tx and Rx clocks

2.5 Modem Interface Module

BRG B Configuration (BBCF}--Mode and Clock
source of BRG B

The Modem Interface module is responsible for the modem interface and general purpose I/O pins. It will gen-

2-185

AP-401

BRG B LSB of Divisor (BBL)-Least Significant Byte
of BRG B Divisor/Count

are totally independent of each other and each FIFO
can generate an interrupt request which indicates .that
the configured threshold has been met.

BRG A MSB of Divisor (BBH)-MostSignificant Byte
ofBRG B Divisor/Count

3.0 HARDWARE DESIGN
BRG A Configuration (BACF)-Mode and Clock
source of BRG A

3.1 System Interface
BRG A LSB of Divisor (BAL)-Least Significant .Byte
of BRG A Divisor/Count

The 82510 has a standard I/O peripheral interface, it
has a demultiplexed Bus, which consists of a bidirectional eight bit Data Bus, and three Address lines. Interrupt, Read, Write, Chip Select and Resetpins complete the system interface. The three address lines along
. with the Bank register are used to select a particular
register.

BRG A MSB of Divisor (BAH)-Most Significant
Byte of BRG A Divisor/Count

2.7 FIFOs, Rx and Tx
The Dual FIFOs(transmit and receive), serve as buffers for the 82510. They buffer the transmitter and Receiver from the CPU. Each of the FIFOs has a programmable threshold. The threshold is the FIFO level
which will generate an interrupt. The threshold is used
to optimize the CPU throughput and provide increased
interrupt to service latency for higher baud rates. It can
be configured through the FIFO Mode Register. Each
FIFO. character has flags associated with it (TxF and
RxF). As each character is read from the Rx FIFO its
flags are put into the RxF register. Before a write to
TXD (if character configuration requires) the character
flags are written to the TXF register. The two FIFOs

Vee

3.1.1 REGISTER ACCESS

The 82510 registers are logically divided into four
banks. Only one bank can be accessed at anyone time.
Each register bank occupies eight I/O addresses. To
select a register, the correct Bank must first be selected .
by writing to the GIRIBank register (the GIR/Bank
register I/O address is two (Ao = 0, Al = 1, A2 = 0).
Then one of the eight I/O space addresses is selected by
outputting a value (between zero and seven) to the
82510 address pins Ao-A2'

- I-

SERIAL MODULE

,- f-+

VSS

A(2-0)I D(7~0

)++-

INT

=:-

.- ~

WRI csi RESETr-

TX
FIFO

INT
BUS

•

Flro

t--+

TX
MACHINE

t- t- t-+ TXD

RX
MACHINE

t- RXD

INTERFACE

UNIT

I-!

T_IRT~J.

Ix Jx

JMJSr
INT
2

INTEiiNAL BUS

II
I

TIMING
BLOCK
(BRGS, SYS CLOCK)

lX
RXC

lX
TXC

t r--

t- ClK/Xl

I~ :::
rIr-I+- r-1-+1-+
[+-

MODEM

INTERFACE
MODULE

OUT2/X2
Iii/SClK
iiSR/TA/iiU'fO
DCii/IClK/OUT1

Mll/TB

ifi'S
CfS

231928-1

Figure 1.82510 Block Diagram

2-186

AP-401

BANK ZERO 825Q-COMPATIBLE BANK
Register

Address Oefaui

~xD

Tx Data
bit 7

Tx Data TxData
bit6
bit 5

Tx Data
bit4

Tx Data
bit 3

TxData
bit 2

Tx Data
bit 1

Tx Data
bitO

RxD

Rx Data
bit7

Rx Data Rx Data
bit6
bit 5

Rx Data
bit4

RxData
bit 3

Rx Data
bit 2

Rx Data
bit 1

Rx Data
bit 0

BAL

BRGA LSB Divide Count (DLAB = 1)

02H

BAH

BRGA MSB Divide Count (DLAB = 1)

OOH

iG ER

GIR/BANK

LCR

TxMachine Modem
Interrupt
Interrupt
Enable
Enable

BANK BANK
Pointer Pointer
bit 0
bit 1

Set
DLAB
Divisor
Break
Latch
Access bit

MCR

LSR

TxM
Idle

MSR

Timer
Interrupt
Enable

Parity
Mode
bit 2

Parity
Mode
bit 1

Rx Machine
Interrupt
Enable

TxFIFO
Interrupt
Enable

RxFIFO
Interrupt
Enable

OOH

Active
Block Int
bit2

Active
Block Int
bit 1

Active
Block Int
bitO

Interrupt
Pending

01H

Parity
Mode
bitO

Stop bit
Length
bitO

Character
Length
bit 1

Character
Length
bit 0

OOH

RTS
DTR
Complement Complement

OOH

Overrun
Error

RxFIFO
Int Reg

60H

State(H-+ L) State
Change
Change
inRI
inDSR

State
Change
inCTS

OOH

OUTO
Loopback OUT2
OUT1
Complement Control bit Complement Complement
TxFIFO
Interrupt

DCD input Rllnput DSR Input
Inverted Inverted Inverted

ACRO

Break
Detected

Framing
Error

CTS Input State
Inverted
Change
inDCD

Parity
Error

Address or Control Character Zero
BANK ONE-GENERAL WORK BANK

Address Iiefault

TxD

Tx Data
bit?

Tx Data Tx Data
bit 6
bit 5

Tx Data
bit 4

Tx Data
bit 3

Tx Data
bit 2

TxData
bit 1

Tx Data
bit 0

RxD

RxData
bit 7

Rx Data Rx Data
bit 6
bitS

Rx Data
bit 4

Rx Data
bit 3

Rx Data
bit 2

Rx Data
bit 1

Rx Data
bitO

RxF

RxChar RxChar
Noisy
OK

RxChar
Parity
Error

Address or
Control
Character

Break
Flag

RxChar
Framing
Error

Ninth
Data bit
of Rx Char

TxF

Address Software Ninth bit
Marker bit Parity bit of Data Char

GIRl BANK

TMST

0
0

0
Active
Block Int
bit 2

Active
Block Int
bit 0

Interrupt
Pending

01H

TimerB
Expired

Timer A
Expired

30H

Start
TimerB

Start
Timer A

OOH

BANK
Pointer
bit 1

BANK
Pointer
bit 0

Active
Block Int
bit 1

Gate B
State

G;ateA
State

'TMCR

Trigger
GateB

Trigger
Gate A

MCR

OUT1
RTS
DTR
OUTO
Loopback OUT 2
Complement Control bit Complement Complement Complement Complement

Figure 2. 82510 Register Map

2-187

intJ

AP-401

BANK ONE--GENERAL WORK BANK (Continued)
Register

FlR

Address/
Control
Character
Received

Address/ Break
Break
Framing
Control
Terminated Detected Error
Character
Match

RCM

Rx
Enable

Rx
Disable

MSR

DCD
Rllnput
Complement Inverted
' 0

GSR

ICM

Flush
RxM

Flush
RxFIFO

DSR Input
Inverted

CTS Input State
Inverted Change
inDCD

Ii
Timer
Interrupt

Address Default

Tx FIFO level
Parity
Error

Overrun RxFIFO
Error
Interrupt
Requested

OpenRx
FIFO

lock Rx
FIFO

RST

TCM

RxFIFO level

State
Change
inRI

OOH

State
State
Change Change
inDSR inCTS

FlushTx
Machine

FlushTx Tx
FIFO
Enable

Tx
Disable

TxM
Interrupt

Modem
Interrupt

RxM
TxFIFO RxFIFO
Interrupt Interrupt Interrupt

Software
Reset

Manuallnt
Status
Acknowledge Clear
Command

Power
Down
Mode

OOH

12H

BANK TW()-.,GENERAL CONFIGURATION

FMD

GIR/BANK

BANK
Pointer
bit 1

TMD

IMD

Error
Echo
Disable

5
BANK
Pointer
bit 0

RMD

Control
9-bit
Character
Character
Echo Disable length

Active
Block Int
bit 2

Transmit Mode

ACR1
RIE.

Rx FIFO Threshold

Address Default

TxFIFO Threshold

OOH

Active
Active
Interrupt
Block Int Block Int Pending
bit 1
bit 0

01H

Software
Parity
Mode

OOH

loopbackor
Echo Mode
of Operation

OCH

OOH

1EH

0 ..

DOH

Stop Bit length

Interrupt
RxFIFO ulan
Acknowledge Depth
Mode
Mode'
Select

Address or Control Character 1
Address/.
Control
Character
Recognition
IntE;lrrupt
Enable

Address/
Control
Character
Match
Interrupt
Enable

Break
Terminate
Interrupt
Enable

Break
Detect
Interrupt
Enable

Disabie
DPll

Sampling Start bit
Window Sampling
Mode
Mode

Address/Control
Character Mode

Framing
Error
Interrupt
Enable

Parity
Error
Interrupt
Enable

Overrun
Error
Interrupt
Enable

BANK THREE-MODEM CONFIGURATION

CLCF

RxClock
Mode

RxClock
Source

TxClock
Mode

TxClock
Source

BACF

BRGA
Clock
Source

Address

Default

OOH

BRGA
Mode

04H

BBl

BRGB lSB Divide Count (DLAB = 1)

05H

BBH

BRGB MSB Divide Count (DLAB = 1)

OOH

Figure 2_ 82510 Register Map (Continued)
2-188

inter

Ap·401

BANK THREE-MODEM CONFIGURATION (Continued)
Register

GIR/BANK

BANK
Pointer
bit 1

BBCF
PMD

5
BANK
Pointer
bit 0

BRGB Clock Source

3
Active
Block Int
bit2

DCDIICLKI DCDIICLKI DSR/TAI DSR/TAI RIISCLK
aUT 1
aUT 1
aUTO
aUTO
Function
Direction
Function
Direction Function

MIE

TMIE

2
Active
Block Int
bit 1

1
Active
Block Int
bit 0

Address Default

Interrupt
Pending

01H

BRGB
Mode

DTR/TB
Function

FCH

OFH

OOH

DCDState RIState
DSRState CTSState
Change Int Change Int Change Int Change Int
Enable
Enable
Enable
Enable
0

TimerB
Interrupt
Enable

Timer A
Interrupt
Enable

Figure 2. 82510 Register Map (Continued)
3.1.2 READ AND WRITE CYCLES

3.1.3 80186 INTERFACE

Like most other I/O based peripherals the Read and
Write pins are used to access data in the 82510. Each
read or write cycle has specified setup and hold times in
order for the data to be transferred correctly to/from
the 82510. The critical timings for the read cycle are:
I. Address Valid to· Read Active (Tavrl)
2. Command Access Time to Data Valid (Trldv)
3. Command Active Width (Trlrh)

The exact interface is shown in Figure 3. The schematic
shows the 80186 interface to the 82510 on a local bus.
Although the Data Bus is buffered, it is possible to
directly connect the 82510 to the 80186 data bus; because the Data Float Delay after read inactive is 40 ns
for the 82510, which is well under the 85 ns requirement of the 80186. The timing equations for the interface are given below.
Read Cycle:

The less critical parameters are:
4. Address Hold to Read Inactive (Trhax)
5. Data Out Float Delay after Read Inactive (Trhdz)

Address to Read Low
- Latch DeiaYmax

Tclcl - Tclavmax

+ Tclrlmin

Read Access Time = 2Tclcl - Tclrlmax - Tdvcl Transceiver DelaYmax

The critical timings for the write cycle are:
1. Address Valid to Write Low (Tavwl)
2. Write Active Time (Twlwh)
3. Data Valid to Write Inactive (Tdvwh)

Read Active Time

Trlrh

= 2Tclcl- 46
Write Cycle:

The less critical parameters are:
4. Address and Chip Select Hold Time After Write
Inactive (Twhax)
5. Data Hold Time After Write Inactive (Twhdx)
These timings determine the number of wait states reo
quired for the 82510 and the CPU interface. The inter. faces for some popular microprocessors are discussed in
the following sections.

Address Valid to Write Active = Tclcl
- Tclavmax - Latch Prop. DeiaYmax

Tcvctvmin

Write Active Time = Twlwh
= 2Tclcl - 40
Data Valid to Write Inactive = 2 Tclcl - Tcldvmax Transceiver DeiaYmax + Tcvctxmin

2-189

AP-401

16.0 MHz

rO~
Xl

.01~

RESET ~

UCS
A

•

RESET ROM
4" r--DATA
l'

...

A16-19
RES

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ALE

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AO-16

~ Rii

I...-

STB

PROGRAM RAM
~ WR

ADO-ADI6
.

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ADO-AD 15

80186

~
r-

DT/R

DEN

rro

LCS
00-15
AO-IS

STB

Rii

r-v

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XCVR

-roAT..\

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00-7

----;:

A
1'[

DB-IS

ADDR

~
RD
AO-IS

I' " " " - -

lB.432 MHz

A3-1

I
~

Rii

r°"--'

A(2-0)
00-7

Rii

RXD

82510

WR
INTO
PCSO

RESET

TXD ~

RESET

RTS

.-+

INT
74LSOS

231928-2

Figure 3.82510 Interface to 80186

2-190

AP-401

The user can transfer data to the 82510, using the
DMA capabilities of the 80186, by using the RTS pin,
in automatic modem control mode, as a DMA request
line. The RTS pin, in automatic mode, will go inactive
as soon as the Tx FIFO and the Tx shift register are
empty. It will become active once a data character is
written to the TXD register. In most 80186 DMA transfers the user has to make sure that the DMA request
line goes inactive at least two clock cycles from the end
of the DMA deposit cycle. In this case, the extra DMA
cycle is not a problem, because the Tx FIFO will buffer
the data to prevent an overrun (Since the Tx FIFO can
buffer up to four characters, the RTS pin only needs to
go inactive two. clocks before the end of the deposit
phase of the fourth DMA). Typically RTS will go inactive five (82510) system clocks after the rising edge of
write.
3.1.4 80286 INTERFACE

The 80286 interface is shown in Figure 4. The 82510 is
on the local bus, and is using the control signals from
the 82288 Bus Controller. The Data Enable (OE) is
qualified by the 82510 Chip Select, to avoid Data Bus
contention between the 82510 and the CPU. The timing
equations for the Read and Write Cycles are given be·
low.
Read Cycle:
Address Valid to Read Active = Tl (CLK period) +
T29 min (CLK to cmd active) - Tl6max (ALE active
delay) - Latch Prop. DelaYmax
Read Access to Data Valid = 2Tl (CLK period)
T29max (CLK to cmd active) - T8 (Read Data Setup
Time) - Transceiver DelaYmax

wait states means that the access times for the relevant
parameters will be increased by 250 ns.
NOTE:
The address decoding scheme of the 80286 interface is
different from the IBM PC/PC AT I/O addresses for
the serial ports, therefore the interface shown in Figure 4 cannot be used in PC/PC AT oriented designs.
3.1.5 80386 INTERFACE

The 80386 interface to the 82510 is given in Figure 5.
The example uses the Basic I/O interface given in the
80386 Hardware Reference Manual section 8.3. The
only differences are in the specific address lines used for
chip select generation, and the additional wait states in
the wait state generation logic. The address lines A3,
A4 and A5 are used to select one of the eight register
address spaces in the 82510, therefore, A6 and A7,
rather than A4 and A5, are used in the I/O decoder.
This causes a granularity of four in the 8251O's I/O
address space, i.e., the addresses oftwo consecutive registers in the 82510 differ by four.
The 82510 requires one additional wait state (as cur·
rently specified), the design assumes that the PAL
equations are modified for that purpose. The user may
also externally generate the wait states and connect to
the "other ready logic" input ORed with the RDY pin
of PAL 2. The two read timings Read Active width and
Read Access time to Data Valid each require one additional wait state in order to meet the 82510 timing requirements. The timings are given below. (82510 times
are at 9.216 MHz)
Read Cycle:
Read Access to Data Valid

Read Active Time = 2Tl (CLK period) - T29 max
(CLK to cmd active) + T30min (CLK to cmd inactive)

82510 Trldv

= 308

Write Cycle:

additional time reqd.

= 308-253.25

Address to Write Low = Tl (CLK period) + T29 min
(CLK to cmd active) - Tl6 max (ALE active delay) Latch DelaYmax
Write Active Time = 2 Tl (CLK period) - T29 max
(CLK to cmd active) + T30 min (CLK to cmd inactive)

253.25 ns

54.75 ns

Read Active Width

269.25

82510 Trlrh

= 308

additional time reqd.

308-269.25

38.75 ns

Data to Write High = 3 Tl - Tl4min (Write Data
Valid Delay) + T30min (CLK to cmd inactive) Xcvr. DelaYmax

Address Valid to Read Active = 132.75 ns
Using an 8 MHz 80286 with the 82510 at 18.432 MHz
(divide by two-9.216 MHz) requires two wait states.
The critical timings are the read cycle timings-Read
Access Time and Read Active Width. Inserting two

2-191

82510TAVRL

7ns

Since each additional wait state adds 62.5 ns at
16 MHz, the 82510 requires one additional wait state.

l
r

WAIT STATE
lOGIC

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M/ili

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STB

SO
51

INTA

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MWTC
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(
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A~AI3-007_0
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A13-0
07-0
07-0

TXD
RXD

'--

'-'-INTR

231928-4

AP-401

The required recovery time between successive commands is 123 ns for the 82510, this is well within the
331.75 ns provided by the Basic I/O interface.

with the PC software). Also since in the PC family the
interrupt request pin of the UART is gated by the
OUT2 pin, The OUT2 pin must be available in the
16450 compatibility mode, consequently the user is restricted to an external clock source when using the
82510 in the IBM PC compatible mode. The default pin
out is given in Figure 6 and the configuration is given in
Table 1. The default register values are given in the
82510 register map shown in Figure 2 in section 3.1.1.

Write Cycle:
132.75 ns

Addven to Write Low

82510TAVWL

= 7ns

Write Active Time

= 300.5 ns

82510 TWLWH

= 231 ns

Data to Write High

= 289.5 ns

82510TDVWH

= 90ns

Table 1.82510 Default Configuration

INTERRUPTS
Auto Acknowledge
All Interrupts Disabled

NOTE:
The interface shown in Figure 5 uses a different address decoding scheme than that used for the IBM
PC/PC AT families, for the serial ports. Therefore,
the interface in Figure 5 can not be used in PC/PC
AT compatible designs.

3.2 Reset
The 82510 can be reset either through hardware (Reset
pin) or Software (reset command via Internal Com- "
mand Register-ICM). Either reset would cause the
82510 to return to its default wake up mode. In this
mode the register contents are reset to their default values and the device is in the 16450 compatible configuration. The Reset pulse must be held active for at least
eight system clocks, the system clock should be running
during reset active time.
3.2.1 DEFAULT MODES FOR 16450
COMPATIBILITY

Upon reset the 82510 will return to its Default Wake
Up mode. The default register bank is bank zero. The
registers in bank zero are identical to the 16450 register
set, and provide complete software compatibility with
the 16450' in the IBM PC environment. The registers
in the other banks have default values, which configure
the 82510 for 16450 emulation. The recommended sys. tern clock (for PC compatibility) is 18.432 MHz, this
allows the baud rates generation to be done in a manner
compatible with the PC software. The PC software calculates baud rates based on a source frequency of
1.8432 MHz. The 82510 system clock (18.432 MHz) is
divided by two before being fed to BRG A and then is
again divided by five (BRG B default). This causes the
frequency to be divided by ten before being fed into
BRG A. 18.432 divided by ten yields 1.8432 MHz, so in
effect the BRG A is generating baud rates from a
source frequency of 1.8432 MHz (which is compatible
*16450 is the PC AT version of the INS 8250A.

2-194

RECEIVE
Stand Ctl. Char. Recogn. disabled
Digital Phase Locked Loop (DPLL) disabled
3/16 Sampling
Majority Vote Start bit
Non IJ-Ian (Normal) mode
BkD, FE, OE, PE Int. enabled
FIFO
Rx FIFO Depth = I
Tx FIFO Threshold = 0

AUTO ECHO Disabled
LOOP BACK Configured
.
for Local Loopback
CLOCK OPTIONS
Baud Rate = 5J.6K
Rx Clock = 16 x
Rx Clock Source = BRG B
Tx Clock = 16 x
Tx Clock Source = BRG B
BRG A Mode = BRG
BRG A Source = Sys. Clock
BRG B Mode = BRG
BRG B Source = BRG A Output
TRANSMIT
Manual Control of RTS
1 Stop Bit
No Parity
5 Bit Character

intJ

AP-401

EXTERNAL CLOCK
04

lNT

TXD

VSS
OUT2

AO
Vee

ClK

Rii

iii
DSR

WR
Cs

OCO

RESET

RXO

RTS

CTS

OTR

231928-7

NOTE:
Crystal Oscillator is always divided by two.

Figure 8. Disable Divide by Two

231928-5

Figure 6. Default Pin Out Configuration
of the 82510

3.3 System Clock Options
The term "System Clock" refers to the clock which
provides timings for most of the 82510 circuitry. The
82510 has two modes of sys,tem clock usage. It can
generate its system clock from its On-Chip Crystal Oscillator and an ext~rnal crystal, or it can use an externally generated clock, input to the device through the
CLK pin. The selection of the system clock option is
done during reset. The default system clock source is an
externally generated clock, which can be reconfigured
by a strapping option on the RTS pin. During Reset,
the RTS pin is an input; it is internally pulled high, if it
is externally driven low, then the 82510 expects to use
the Crystal Oscillator for system clock generation, otherwise it is set up for using an external clock source.
This can be done by using an open collector inverter to
RTS, the input of the inverter is the Reset signal. The
82510 has a pull up resistor in the RTS circuitry so no
. external pull up is needed. In the crystal oscillator
mode the CLKiXl pin is automatically configured to
Xl, and the OUT2/X2 pin is configured to X2. In the
External Clock mode, the CLK/X 1 is configured to
CLK and the OUT2/X2 is configured to OUT2.

If the Crystal Oscillator is being used to supply the
system clock, then the clock frequency is always divided by two before being fed into the rest of the 82510
circuitry. If, however an external clock source is being
used to supply the system clock, then the user has two
options:
1. Use the System Clock after division by two, e.g. if a
8 MHz clock is being fed into the CLK pin, then the
actual frequency of the 82510 system clock will be 4
MHz (default).
2. Disable Division by two and use the direct undivided clock, e.g. if an 8 MHz clock is being fed into the
CLK pin, then the actual frequency of the 82510
system clock is also 8 MHz.
The divide by two option is the default mode of operation in the External Clock mode of the 82510. A strapping option can be used to disable the Divide By Two
operation (For Crystal Oscillator Mode Divide By Two
must always be active). During Reset, the DTR pin is
an input; it is internally pulled high, if it is externally
driven low then the Divide By Two operation is disabled. The strapping option is identical to the one used
on RTS for selection of the System Clock source.
The 82510 system clock must be chosen with care since
it influences the wait state performance, Baud Rate
Generation (if being used as source frequency for the
BRGs), the power consumption, and the Timer counting period. The power consumption of the 82510 is dependent upon the system clock frequency. If using the
system clock as a source for the Baud Rate Generator(s), then the system clock frequency must be a baud
rate multiple in order to minimize frequency deviation.
For standard baud rates a mUltiple of 1.8432 MHz can
be used, in fact the 18.432 MHz maximum frequency
was chosen with this particular criteria in mind.

231928-6

1 ms is needed for Oscillator startup

Figure 7. Crystal Oscillator Strapping Option

2-195

AP-401

BACF(6)

SCLK
CLK/Xl

(DEF)

BRGA
CLOCK
MUX

BRGA
FSM + COUNTER
+ LOGIC

RXM
16X
CLOCK

BBCF(7-6)

SCLK
CLK/Xl

(DEF)

BRGB
CLOCK
MUX

CLCF(6)

BRGB
FSM + COUNTER
+ LOGIC

TXM

(DEF)

16X
CLOCK

CLCF(4)

TXM

TxCM BIT
OF CLCF

~------------------------------------~lX

RxCM BIT
IN CLCF

~------------------------------------~lX

CLOCK
RXM
CLOCK
231928-8

Figure 9. Timing Flow of the 82510

2-196

inter

AP-401

3.3.1 POWER DOWN MODE

3.3.1.2 Idle Mode

The 82510 has a "power down" mode to reduce power
consumption when the device is not in use. The 82510
powers down when the power down command is issued
via the Internal Command Register (ICM). There are
two modes of power down, Power Down Sleep and
Power Down Idle.

The 82510 is said to be in the Idle mode when the
Power Down command is issued and the system clock
is still running (i.e. the system clock is generated externally and not disabled by the user). In this mode the
contents of all registers and memory cells are preserved,
however, the power consumption in this mode is greater than in the Sleep mode. Reading FLR will take the
82510 out of this mode.

3.3.1.1 Sleep Mode

This is the mode when even the system clock of the
82510 is shut down. The system clock source of the
82510 can either be the Crystal Oscillator or an external clock source. If the Crystal Oscillator is being used
and the power down command is issued, then the
82510 will automatically enter the Sleep mode. If an
external clock is being used, then the user must disable
the external clock in addition to issuing the Power
Down command, to enter the Sleep mode. The benefit
of this mode is the increased savings in power consumption (typical power consumption in the Sleep
mode is in the range of hundreds of microAmps. However, upon wake up, if using a crystal oscillator, the
user must reprogram the device. The data is preserved
if the external clock is disabled after the power down
command, and enabled prior to exiting the power down
mode. To exit this mode the user can either issue a
Hardware reset, or read the FIFO Level Register (FLR)
and then issue a software reset (if using a Crystal Oscillator). In either case the contents of the 82510 registers
are not preserved and the device must be reprogrammed prior to operation.

NOTE:
The data read from FLR when exiting Power Down is
incorrect and must be ignored.

4.0 INTERRUPT BEHAVIOR

4.1 FIFO Usage
The 82510 has two independent four bytes transmit and
receive FIFOs. Each FIFO can generate an interrupt
request, when the FIFO level meets the Threshold requirements. The FIFOs can have a considerable impact
on the performance of an asynchronous communications system. For systems using high baud rates they
can provide increased interrupt-to-service latency reducing the chances of an overrun occurring. In systems
constrained for CPU time, the FIFOs can increase the
CPU Bandwidth by reducing the number of interrupt
requests generated during asynchronous communications. It can reduce the interrupt load on the CPU by
up to 75%. By choosing the FIFO thresholds which
reflect the system bandwidth or service latency requirements, the user can achieve data rates and system
throughput, unattainable with traditional UARTs.

NOTE:
If the Crystal Oscillator is being used then the user
must allow about I ms for the oscillator to wake up
before issuing the software reset.
Table 2. The Power Down Modes
Mode
Sleep

Idle

Power Consumption

Data Preservation

Crystal Oscil!.
Automatically
Disabled

Clock Source

H/W Resetar
Read FLR and
Issue S/W Reset

Exit Procedure

100-900/LA

Not Preserved
Must be Reprogrammed

External Clock
Must be Disabled
by User

Enable External
Clock, Read FLR
and Issue S/W Reset
H/W Reset

100-900/LA

Not Preserved
Must be Reprogrammed

External Clock
Running

H/W Reset
Read FLR

1-3 mA

All Data Preserved
Does Not Need to be
Reprogrammed

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Ap·401

4.1.1 INTERRUPT·TO-SERVICE LATENCY

Going back to equation (2):

The interrupt-to-service latency is the time delay from
the generation of an interrupt request, to when the interrupt source in the 82510 is actually serviced. Its
primary application is in the reception of data. In traditional UARTs the CPU must read the current character in the Receive Buffer before it is overrun by the next
incoming character. The Rx FIFO in the 82510 can
buffer up to four characters, aJlowing an interrupt-toservice latency of up to four character transmission
times. The character transmission time is the time period required to transmit one fuJI character at the given
Baud Rate. It is dependent upon the baud rate and is
given by equation (I):

Int._to_service latency < Buffer size x lO/baud rate
Int_to_service latency = # of Channels X (# of
into sources per channel)
X Time required to service interrupt
Int_to~service latency = 4 X 2 X Time required to
service interrupt

(I) Character Transmission Time

The Time required to service interrupt has been calculated to be 100 JLs for a slightly optimiZed service routine. RMX86 interrupt service time is given as 250 JLs
and for other operating systems it should be slightly
higher.
Int_to_service
latency
= 4x2xlOO s

Num. of Bits per Character Frame
Baud Rate
The Transmit and Receive FIFO thresholds should be
selected with consideration to two factors the Baud
rate, and the (CPU Bandwidth allocated for AsynchronousChannels is dependent upon the number of.channels supported since it does not include the overhead of
supporting other peripherals) number of Asynchronous
Serial ports being supported by the CPU. In order to
avoid overrun, the interrupt-to-service delay must be
less than the time it takes to fiJI the 82510 Rx FIFO.
The relationship is given by equation (2):
(2) Int_to_service-latency < FIFO Size X
Character Transmission Time
Example

Calculate the maximum baud rate that can be supported by a 6 MHz PC AT to support four Full Duplex
.
Asynchronous channels using
a) The 82510 with four byte FIFO.
b) The 82510 with one byte FIFO.
Assumptions:

• CPU dedicated to Asynchronous communications.
• UART Interrupts limited to Transmission and Reception only.
• Interrupt Routines are optimized for fast throughput.
• 10. bits per character frame.

= 800 JLs
82510 max Baud Rate = 4 X 10/800 JLs
(four byte FIFO)
= 50K bits/sec
82510 max Baud Rate = 1 X 10/800 JLs
(one byte FIFO)
= 12.5K bits/sec

4.2 Interrupt Handling
The 82510 has 16 different sources of interrupt, each of
these sources, when set and enabled, wiJI cause their
respective block interrupt requests to go active. The
block interrupt request, if enabled, wiJI set the 8251O's
INT pin high, and wiJI be reflected as a pending interrupt in the General Interrupt Register (GIR) ifno other
higher priority block is requesting service. If a higher
priority block interrupt is also active at the same time,
then the General Interrupt Register wiJI reflect the higher priority request as the source of the 82510 interrupt.
The lower priority interrupt wiJI issue a new edge on
the interrupt pin only after the higher priority interrupt
is acknowledged and if no other priority block requests
are present. Both the block interrupts and the individual sources within the blocks are maskable. The block
interrupts are enabled through the General Enable Register (GER) which prevents masked bits in the General
Status Register (GSR) from being decoded into the
General Interrupt Register. This does not prevent the
block request from being set in the General Status Register, it only prevents the masked GSR bits from being
decoded into the General Interrupt Register, and thus
generating any interrupts. The individual sources within the block are masked out via the corresponding interrupt enable register associated with the specific block
(Rx Machine, Timing Unit and the Modem I/O module each have an Interrupt Enable register).

2-198

inter

AP-401

FIFO BELOW
OR EQUAL
THRESHOLD

GER

FALLING EDGE DETECrORS

SERVICE DETECTED

ACKNOWLEDGE
COMMAND
ICM(3)

AUTOMATIC MODE
IMD(3)

231928-9

Figure 9. 82510'5 Interrupt Scheme
2-199

AP·401

4.2.1.4 Priority Resolver and General Interrupt
Register

4.2.1 THE INTERRUPT SCHEME

The 82510 interrupt logic consists of the following elements:

If more than one enabled Interrupt request from. GSR
is active, then the priority resolver is used to resolve
contention. The priority resolver finds the highest priority pending and enabled interrupt in GSR and decodes it into the General Interrupt Register (bits 3 to 1).
The General Interrupt Register can be read at any time.

4.2.1.1-lnterrupt Sources Within Blocks

Three of the 82510 functional blocks (Rx Machine,
Timer, Modem 1/0) have more than one possible
source of interrupts, for instance the Rx Machine has
seven different sources of interrupts-standard control
character recognition (Std. CCR), control character
Match (special CCR), Break Detect, Break Terminated, Overrun Error, Parity Error, and Framing Error.
The multiple sources are represented as Status bits in
the Status registers of each of these blocks. When· enabled the Status bits cause the block request to set in
the General Status Register. There is no difference in
the behavior of the INT pin or the block status bits in
GSR, for multiple sources within a block becoming active simultaneously. The corresponding block status bit
in GSR is set when one or more interrupt sources within the block become active. When the status register for
the block is read all the active interrupt sources within
the block are reset. Each source within the three blocks
can be masked through its respective enable register.

NOTE:
GIR is updated continuously, so while the user may
be serving one interrupt source, a new interrupt with
higher priority may update GIR and replace the older
one.
4.2.2 INTERRUPT ACKNOWLEDGE MODES

The 82510 has two modes of interrupt acknowledgement-Manual acknowledge and Automatic acknowledge. In Manual Acknowledge mode, the user has to
issue an explicit AcIaiowledge Command via the
Internal Command Register (ICM) in order to cause
the INT pin to go low. In Automatic Acknowledge
mode the INT pin will go low as soon as an active or
pending interrupt request is serviced by the CPU. An
operation is considered to be a service operation if it
causes the source of the interrupt (within the 82510) to·
become inactive (the specific status bit is reset). The
service procedures for each source vary, see section
4.2.3.2 for details.

4.2.1.2 General Status Register (GSR)

This register holds the status of the six 82510 blocks
(all except Bus Interface Unit). Each bit when set indicates that the particular block is requesting interrupt
service, and if enabled via the General Enable Register,
will cause an interrupt.

4.2.2.1 Automatic Acknowledgement

4.2.1.3 General Enable Register (GER)

This register is used to enableldisable the corresponding bits in the General Status Register. It can be programmed by the CPU at any time.
Table 3. Block Interrupt Priority
Block

Priority

Timers
Tx Machine
Rx Machine
Rx FIFO
TxFIFO
Modem I/O

5 (highest)
4

3
2
1

o (lowest)

GIRCODE
3 2 1 (Bits)

1 0 1
100
o1 1
010
001
000

In the automatic acknowledge mode, a service operation by the CPU will be considered as an automatic
acknowledgement of the interrupt. This will force the
INT pin low for two clock cycles, after that the INT
pin is updated i.e. if there is an active enabled source
pending then the INT pin is set high again (reflected in
GIR). This mode is useful in an edge triggered Interrupt system. Servicing any enabled and active GSR bit
will cause Auto Acknowledge to occur (independently
of the source currently decoded in the GIR register).
This can be used to rearrange priorities of the 82510
block requests.

2-200

AP-401

GSR 5
TIMER
GSR 3 (MODEM)

GIR
GIR

= 1-

INT

8259A

USER
OPERATIONS

READ GIR SERVE
(=10) TIMER

ISSUE
EOI
TO

8259A

READ GIR SERVE ISSUE
(= 2) TX FIFO
EOI
(WRITE
CHARACTERS)

READ GIR SERVE
(=0) MODEM

ISSUE
EOI

231928-10

8259A -

Edge Triggered
Non Auto EOI
82510 Automatic Acknowledge

Figure 10. Automatic Acknowledge Mode Operation

GSR
bit 3

--.J
(MODEM)

b?tS~

(TXM)

b?tS~

(TIMER)

GIR

(82590)
INT

8259A

USER

READ GIR SERVE MODEM READ GIR
(=0)
INTERRUPT
(= 10)

SERVE
TIMER

READ GIR

(=8)

SERVE
TXN

READ GIR ISSUE
(=1) MANUAL
ACK TO

82510

231928-11

NOTE:
Vector refers to GIR bit (3·0)
82510: Manual Ack. Mode
8259A: Edge Triggered Non AEOI

Figure 11. Manual Acknowledge Mode Operation

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AP-401

.4.2.2.2 Manual Mode of Acknowledgement
The Manual Acknowledgement Mode requires that,
unlike the automatic mode where a service operation is
considered as an automatic acknowledge, an explicit
acknowledge command be issued to the 82510 to cause
INT to go inactive. In this mode the CPU has complete
control over the timing of the Interrupts. Before exiting
the service routine, the CPU can check the GIR register
to see if other interrupts are pending and can service
those interrupts in the same invocation, avoiding the
overhead of another interrupt as in the Automatic

mode. Of course the user has tbe option of issuing the
acknowledge command immediately after the service,
which would be similiar in behavior to the automatic
mode. If the manual acknowledge command is given
before the active source has been serviced and no higher
priority request is pending, then the same source will
immediately generate a new interrupt. Therefore, the
software must make sure that the Manual Acknowl·
edge command is issued after the interrupt source has
been serviced by the CPU (see section 4.2.3.2. for more
details on interrupt service procedures for each source).

READ CORRESPONDING
STATUS REGISTER &
SERVICE ALL APPROPRIATE
ACTIVE BITS

RESTORE ORIGINAL
VALUE OF GIR/BANK
TO RETURN TO
ORIGINAL BANK

231928-12

Figure 12. Typical Interrupt Handler

2·202

Ap·401

4.2.3 GENERAL INTERRUPT HANDLER

In general an interrupt handler for the 82510 must first
identify the interrupt source within the 82510, transfer
control to the appropriate service routine and then
service the active source. The active source can be identified from two registers-General Interrupt Register,
or General Status Register. The GIR register identifies
the highest priority active block interrupt request. The
GSR register identifies all active (pending or in service)
Block Interrupt Requests. The typical operation of the
82510 interrupt handler is given in Figure 12. The two
major issues of concern are the source identification
and Control Transfer to the appropriate service routine.

Since the 82510 registers are divided into banks, and
the interrupt handler may change register banks during
service, it is best to save the bank being used by the
main program and then do the interrupt processing.
Upon completion of service, the original bank value is
restored to the GIR/Bank register.
4.2.3.1 Source Identification

The 82510 has 16 interrupt sources, and the CPU must
identify the source before performing any service. Although the procedure varies, the typical method would
be to identify the block requesting service by reading

USER PRIORITY

RX FIFO (HI)
RX I14ACHINE
TlIllER

( TX FIFO
TX I14ACHINE
1140DEII4 (LOW)

231928-13

Figure 13. Bypassing the 82510 Fixed Interrupt Priority

2-203

AP·401

GIR bits 3-1. If the source is either Tx Machine, Tx
FIFO, or Rx FIFO, no further indentification is needed; the user can transfer control to the service routine
(in most cases, only one Timer will be used, therefore
the Timer Routine can also be directly invoked). All
modem 1/0 interrupts can be handled via one routine
as all the modem interrupt sources are supplementary
to the modem handshaking function. The Rx Machine,
however, has two different types of interrupt sources,
event indications (CCRIAddress recognition CCR/Address Match, Break Detect, Break Terminate, and
Overrun. Error), and error indications (parity Error,
Framing Error, these error indications do not refer to
any particular character, they just indicate that the specific error was detected during reception). For most applications, the error indicators can be masked off, and
only the event driven interrupts enabled. The error indicators can be read from the Receive Flags prior to
reading a character from the FIFO. This interrupt
scheme can be used, because the Receive character error indicators are available in the Receive Flags, and
can be checked by the Receive routine before reading
the character from the Rx FIFO.

user can bypass the 8251O's priority resolution by using
the General Status Register (rather than GIN.) to determine the block interrupt sources requesting service.
Each source is checked in order of user priority and
serviced when identified (There will be no problem with
using this algorithm in auto acknowledge mode because
the INT pin will go low as soon as a pending and enabled interrupt request goes low). The user will be trading some service latency time for additional source
identification time, this algorithm's efficiency will improve as the number of block sources to verify is reduced. See Figure 13 for the algorithm.
4.2.3.2 Interrupt Service

Since all active status bits (except Rx FIFO interrupt in
LSR and RST) are reset when the corresponding block
status register is read, the interrupt routine must check
for all possible active sources within the block, and
service each active source before exiting the interrupt
handler.
The 82510 interrupt contention is resolved on a fixed
priority basis. In some applications the fixed priority
may not be suitable for the user. For these cases the

A service operation is an operation performed by the
CPU, which causes the source of the 82510 interrupt to
go inactive (it will reset the particular status bit causing
the interrupt). An interrupt request within the 82510
will not reset until the interrupt source has been serviced. Each source can be serviced in two or three different ways; one general way is to disable the particular
status bit causing the interrupt, via the corresponding
block enable register. Setting the appropriate bit of the
enable register to zero will mask off the corresponding
bit in the status register, thus causing the INT pin to go
inactive: The same effect can be achieved by masking
off the particular block interrupt request in GSR via
the General Enable Register. Another method, which is
applicable to all sources, is to issue the Status' Clear
command from the Internal Command Register; The
detailed service requirements for each source are given
below:

Table 4. Service Procedures For Each Interrupt Source
Interrupt
Source

Status Bits
& Registers

Interrupt
Masking

Specific
Service

Timers

TMST(1-0)
GSR(5)

TMIE (1-0)
GER(5)

ReadTMST

Issue
Status Clear
(StC)

Tx
Machine

GSR(4)
LSR(6)

GER(4)

Write Character
toTx FIFO

Issue StC

Rx
Machine

LSR(4-1)
RST(7-1)
GSR (2)

RIE (7-1)
GER(2)

Read RST or LSR
Write 0 to bit
in RST/LSR

Issue StC

RxFIFO

RST/LSR (0)
GSR(O)

GER(O)

, Write 0 to LSR/RST
Bit zero.
Read Character(s).

IssueStC

TxFIFO

LSR(5)
GSR(1)

GER(1)

Write to FIFO
ReadGIR

IssueStC

Modem

MSR (3-0)
GSR(3)

MIE(3-0)
GER(3)

Read MSR
write 0 into the
appropriate bits 01
olMSR (3-0)

IssueStC

General
Service

NOTE:
The procedures listed in Table 4 will cause the INT pin to go low only il the 82510 is in the automatic acknowledge mode.
Otherwise, only the internal source(s) are decoded, the INT pin will go low only when the Manual Acknowlege command is
.
issued.

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AP-401

4.3 Polling
The 82510 can be used in a polling mode by using the
General Status Register to determine the status of the
various 82510 blocks, this is useful when the software
must manage all the blocks at once. If the software is
dedicated to performing one function at a time, then
the specific status registers for the block can be used,
e.g. if the software is only going to be Transmitting, it
can monitor the Tx FIFO level by polling the FIFO
Level Register, and write data whenever the Tx FIFO
level decreases. Reception of data can be done in the
same manner.

5.0 SOFTWARE CONSIDERATIONS
5.1 Configuration
The 82510 must be configured for the appropriate
modes before it can be used to transmit or receive data.
Configuration is done via read and write registers, each
functional block (except for BIU) has a configuration
register. Typically the configuration is done once after
start up, however, the FIFO thresholds and the interrupt masks can be reconfigured dynamically. If the
82510 configuration is not \mown at start up it is best to
bring the device to a known state by issuing a software
reset command (ICM register, bank one). At this point
all block interrupts are masked out in GER and all
configuration and status registers have default values.
The bank register is pointing to bank zero. The 82510
can now be configured as follows:
1. If BRG A is being issued as a baud rate generator
then load the baud rate count into BAL and BAH
registers.
2. Configure the character attributes in LCR register
(Parity, Stop Bit Length, and Character Length).
(Note if interrupts are being used, steps 1 and 2 can
also be done at the end, since the user will have to
retu~ to bank zero to set the interrupt masks in GER)
3. Load ACRO register with the appropriate Control
or Address character (if using the Control Character Match or Address Match capability of the
82510).
4. Switch to Bank two.
(In this Bank the configuration can be done in any
order)
5. Configure the Receive and Transmit FIFO thresholds if using different thresholds than the default).

6. Configure the Transmit Mode Register for the
Stop Bit length, modem control, and if using echo
or 9 bit length or software parity, configure the
appropriate bits of the register. The default mode
of the modem control is Manual, if using the FIFO
then the automatic mode would be most useful).
7. Configure the Rx FIFO depth, interrupt acknowledge mode, ""Ian or normal mode and echo modes
in IMD register.
8. Load ACRI if necessary
9. Enable Rx Machine Interrupts as necessary via
RIE.
10. Configure RMD for CCR, DPLL operation, Sampling Window, and start bit.
11. Switch to Bank 3.
12. Configure CLCF register for Tx and Rx clocks and
or Sources
13. Configure BACF register for BRG A mode and
source.
14. Load BBL and BBH if BRGB is being used (as
either a BRG or a Timer).
15. Configure BBCF register if necessary.
16. If reconfiguration of the modem pin is necessary
then program the PMD register.
17. Enable any modem interrupt sources, if required,
via MIE register.
18. Enable Timer interrupts, if necessary, via TMIE.
19. If iIsing interrupts
then
i) Switch to Bank zero.
Disable Interrupts at CPU (either by masking
the request at the interrupt controller or executing the CLI instruction).
ii) Enable the appropriate 82510 Block interrupts
by setting bits in the GER register. (CPU interrupts can now be reenabled, but it is recommended to switch banks before enabling the
CPU interrupts).
NOTE:
At this stage it is best to leave the TxM and Tx FIFO
interrupt disabled. See section 6.3 Transmit Operation
-for details)
20. Switch to Bank One. Load Transmit Flags if using
9-bit characters, or 8051 9-bit mode or software
parity. If using interrupts CPU interrupts can now
be enabled.
Bank One is used for general operation, the 82510 can
now be used to transmit or receive characters.

2-205

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AP-401

GENERAL
CONFIGURATION

1.
2.
3.
4.
5.

CONFIGURE:
STOP BIT LENGTH
MODE OF RTS CONTROL
9-BIT CHAR. LENGTH}
S/W PARITY
OPTIONAL
AUTO ECHE MODE IN
TRANSMIT MODE REGISTER

SET RX FIFO DEPTH.
INTERRUPT
ACKNOWLEDGE MODE,
J.'LAN OR NORMAL AND
AUTO ECHO IN INTERNAL
MODE REGISTER

ENABLE INTERRUPTS FOR
RX STATUS BITS VIA
RX INTERRUPT
ENABLE REGISTER

231928-14

SET MODES OF CONTROL
CHARACTER RECOGNITION,
DATA SAMPLING, AND
DPLL USE,
IN RX MODE REGISTER

TOC
231928-15

Figure 14. Configuration Flow Chart

2-206

AP-401

t.40DEt.4 AND
TIMING UNIT
CONFIGURATION
IN CLOCKS CONFIGURE
REGISTER: SELECT SOURCES
OF TX I!c RX CLOCKS
SELECT t.40DES OF
TX I!c RX CLOCKS

CONFIGURE BRG A CLOCK
SOURCE AND t.40DE OF
OPERATION VIA BRG A
CONFIGURATION REGISTER

ENABLE THE 82510
BLOCK INTERRUPT
SOURCES VIA GENERAL
ENABLE REGISTER

CONFIGURE BRG B FOR
SOURCE AND 1oI0DE VIA BRG B
CONFIGURATION REGISTER
(IF BEING USED AS A BRG)

ENABLE INTERRUPTS
(IF NECESSARY) ON
t.40DEt.4 INPUT PINS VIA
MODEt.4 INTERRUPT
ENABLE REGISTER

231928-17

ENABLE TIMER INTERRUPTS
AS NECESSARY. VIA
TIMER INTERRUPT
ENABLE REGISTER

TO D

231928-16

Figure 14. Configuration Flow Chart (Continued)

2-207

AP-401

The transmitter has two status flags. Tx Machine Idle
and Tx FIFO interrupt request, each of these conditions may cause an interrupt, if enabled. The Transmit
Idle condition indicates that the Tx Machine is either
empty or disabled. The Tx FIFO interrupt bit is set
only when the level of the Tx FIFO is less than or equal
to the threshold. These interrupts should remain disabled until data is available for transmission. Because
outside of disabling the corresponding GSR status bits,
the only way to service Tx Idle is by writing data to the
Transmitter. Otherwise, the Tx Machine interrupt may
occur when no data is available for transmission, and as
a result will keep the INT pin active, preventing the
82510 from generating any further interrupts (unless
the Transmit Interrupt routine automatically disables
the Tx Machine Idle and Tx FIFO interrupt requests in
GSR). The threshold of the Tx FIFO is programmable
from three to zero, at a threshold of three the Tx FIFO
will generate an interrupt after a character has been
transmitted. While at a threshold of zero the interrupt
will be generated only when the Tx FIFO is empty. For
most applications a threshold of zero can be used. If the
threshold is dynamically configured, i.e. it is being
modified during operation, then the Tx FIFO level
must be checked before writing data to the transmitter.

T
X
F
I
F

o
L
E
V

E
L

-2
THRESHOLD

INACTIVE

INTER RU PTS

ACTIVE

231928-18

- - Tx Machine and 82510
- - - - User write operation

Figure 15. Tx FIFO Interrupt Hysteresis

5.2 Transmit Operation
5.2.1.1 Transmit Interrupt Handler
5.2.1 GENERAL OPERATION

To transmit a character the CPU must write it to the
TXD register, this character along with the flags from
the Tx Flags register is loaded to the top of the TX
FIFO. If the Tx Machine is empty, then the character
is loaded into the shift register, where it is serially
transmitted out via the TXD pin (the flags are not
transmitted unless the 8251O's configuration requires
their transmission e.g. ifsoftware parity is selected then
the S/W parity bit is transmitted as the parity bit of the
character). The CPU may write more than one character into the FIFO, it can write four characters in a burst
(five if the Tx Machine is empty) or it can check the
FIFO level before each write, to avoid an overrun condition to the transmitter. In the case of the latter, the
software overhead of checking the FIFO level must be
less than the time required to transmit a character, otherwise the transmit routine may not exit until another
exit condition has been met.
e.g. at 288,000 bps for an 8-bit char no parity
It takes 34.7 I-I-s to transmit one character.
If the time, from the write to TXD to the reading of the
. Transmit FIFO level, is greater than 34.7 I-I-s then the
Tx FIFO level will never reach higher than zero, and
the FIFO will always appear to be empty. Therefore, if
the transmit routine is checking for a higher level in the
FIFO it may not be able to return until some other exit
condition-such as no more data available-is met.
This can be a problem in the interrupt handler, where
the service routine is required to be efficient and fast.

The Transmit Interrupt Handler will be invoked when
either the Tx FIFO threshold has been met or if the
Transmitter is empty. Since the Tx Machine interrupt
is high priority (second highest priority, with Timer
being the highest), the interrupt line will not be released
to other lower priority, pending 82510 sources until the
Tx Machine interrupt has been serviced. If no data is
available for transmission, then the only way to acknowledge the interrupt is by disabling it in the General
Enable Register. Thus the Tx Machine interrupt should
not be enabled until there is data available for transmission. The Tx Machine interrupt should be disabled after transmission is completed.
5.2.1.2 Transmission By Polling

Transmission on a polling basis can be done by using
the General Status Register and/or the FIFO Level Register. The software can wait until the Tx FIFO and/or
the Tx Machine Idle bits are set in the General Status
Register, and then do a set number of writes to the TXD
register. This method is useful when the software is trying to manage other functions such as modem control,
timer management and data reception, simultaneously
with transmission.
If management of other functions is not needed while
transmitting, then continuous transmission can be done
by monitoring the Tx FIFO level. A new character is
written to TXD as soon as the FIFO level drops by one
level.

2-208

AP-401

DISABLE TX MACHINE
IDLE, AND TX FIFO
INT. REO. IN GER

Tx FIFO Threshold =

231928-19

NOTE:
TxM Idle and Tx FIFO Empty interrupts are enabled by the Main Program, when data transmission is required.

Figure 16. 16 Tx Interrupt Handler Flow Chart

2-209

intJ

AP-401

231928-20

Figure 17. Using GSR for Polling

2-210

inter

AP-401

231926-21

Figure 18. Data Transmission by Monitoring FIFO Level

2-211

inter

Ap·401

231928-22

Figure 19. Break Transmission Using Tx FIFO to Measure Break Length

2·212

inter

AP-401

5.2.1.3 Break Transmission

The 82510 will transmit a break when bit six of the
Line Control Register is set high. This will cause the
TXD pin to be held at Mark for one or more character
time. The Tx FIFO can be used to program a variable
length break, see Figure 19 for details. If the break
command is issued in the midst of character transmis·
sion the TXD pin will go low, but the transmitter will
not be disabled. The characters from the Tx FIFO will
be shifted out on to the Tx Machine and lost. To pre·
vent the erroneous transmission of data, The CPU must
make sure the Transmitter is empty or disabled before
issuing the Send Break command.

X
f
I

OVERRUN

~~~

.... --------

5.3.1 RECEIVE INTERRUPT HANDLER

The Receiver will generate two types of interrupts, Rx
FIFO interrupt and Rx Machine Interrupt. The Rx
FIFO interrupt requires that the CPU read data characters from the Rx FIFO. If the Rx Machine interrupts
are disabled then the CPU should also check for errors
in the character before moving it to a valid buffer. The
interrupts generated by the Rx Machine can be divided
into two categories-occurrence of errors during reception of data (parity error, framing error, overrun error),
or the occurrence of certain events (Control! Address
character received, Break detected, Break Terminated).
For typical applications, the error status of each reo
ceived character can be checked via the Receive Flags,
and the events can be handled via interrupts.

L
E

-2
THRESHOLD

,,
O~--~--------------------_m----

INACTIVE

INTERRUPTS

read characters from the 82510. Each character on the
Rx FIFO has flags associated with it, all of these flags
are generated by the Rx Machine during reception of
the character. These flags provide information on the
integrity of the character, e.g. whether the character
was received OK, or if there were any errors. The receiver status is provided via the Receive Status Register
(RST). which provides information on events occurring
within the Rx Machine, since the last time RST was
read. The information mayor may not apply to the
current character being read from the RXD register.
The CPU may read one or more characters from the
Rx FIFO. After each read, if the FIFO contains more
than a single character, a new character is loaded into
the RXD register and the flags for that character are
placed into the RXF register. The software can check
for the Rx character OK bit in the flags to make sure
that the character was received without any problems.

ACTIVE
231928-23

'" - User Read Operations
82510 Character Reception
-

5.3.2 RECEIVING DATA BY POLLING

Rx FIFO Hysteresis

5.3 Data Reception
The receiver provides the 82510 with three types of
information:
a) Data characters received
b) Rx Flags for each data character
c) Status information on events within the Rx Machine.
The Rx FIFO interrupt request goes active when the
Rx FIFO level is greater than the threshold, if the interrupt for this bit is enabled then it will generate an
interrupt to the CPU. This is a request for the CPU to

To receive data through polling, the 82510 can use the
General Status or the Receive Status Registers to check
for the Rx FIFO request. If the Receive routine does
not generate time outs or modem pin transitions, then
the data can also be received by monitoring the Rx
FIFO level in the FIFO Level Register. The implementation using GSR would be useful in applications where
the software routine must monitor the timer for time
outs or the modem pins for change in status. The example polling routine illustrates the use of the FIFO Level
Register in receiving data. It waits for the Rx FIFO
request before beginning data reception. The procedure
Rx_Data_Poll will receive the number of characters
requested in Chac-'.count and place them in the Receive buffer.

2·213

AP-401

231928-24

Figure 20. Rx FIFO Interrupt Handler

2-214

inter

AP-401

#define base Ox3F8;
/* base address of 82510 */
#define buff __ size 128;
Rx __ Data __ Poll (Char __ count, Rxbuffer)
int Char __ count;
/* Total # of bytes to be received */
char *Rxbuffer [buff size];
{

int count
0;
int status, lvI, Rok.;
While «(status
{

= (Inp(base+7)

& Ox05))

OxOl) /* I f Rx FIFO Req in GSR set
/* Assume in bank one */

/* If Rx FIFO is not empty */
While «IvI
«Inp (base+4) & Ox70)/OxlO)0&&(count < (Char __ count))

{

/* If Character Received OK */
if «(Rok
(Inp (base+l) & Ox60))
(

Rxbuffer [count]
++count;

= Inp

Ox40)

(base);

Figure 21. Example Polling Routine
CONTROL CHARACTER HANDLING

The 82510 has two modes of control character recogni·
tion. It can recognize either standard ASCII or stan·
dard EBCDIC control characters, or it can recognize a
match with two user programmed control (or Address
Characters in MCS·51 9·bit mode, for Automatic Wake
up) characters. Each mode generates an interrupt
through the Receive Status Register. The Receive Flags
also indicate whether the character being read is a con·
trol character. The usage of CCR depends on the maximum number of possible control characters that can be
received at anyone time. Applications such as Terminal Drivers, which have ·no more than two control
characters outstanding, such as XON and Ctl-C, or
XOFF and Ctl-C, can use just the Control Character
Match mode by programming the registers ACRO and
ACRI. If the CPU needs to process text on a line by
line basis the standard Control Character recognition
capabilit; can be used to determine when an end of line
has occurred e.g. a whole line has been received when a
Carriage Return (CR) or Line Feed (LF) is received by
theUART.
Implementation of a character oriented asynchronous
file transfer protocol can be done using.both standard
and specific Control Character Recognition. In such
protocols most control characters such as Start of
Header (SOH), can only be received during certain
states, these characters can be received via Standard
Control Character Recognition. A few Control Charac-

ters (e.g. abort) can be received at any stage of communication, these can be received by using the Control
Character Matching capabilities of the 82510.

5.3.3 BREAK RECEPTION
The 82510 has two status indications of break reception Break Detect indicates that a break has been detect;d on the RXD pin. Break Terminated indicates
that the Break previously detected on the RXD line has
terminated and normal Data reception can resume.
Each of these status bits can generate an interrupt request through the Rx Machine Interrupt request. N?rmal consequence of break is to abort the data reception
or to introduce a line idle delay in the middle of data
reception. In the case of the former, the Break Detect
interrupt can be used to reset the 82510 Receive Machine and the Rx routine flags; in the case of the latter,
the break terminated interrupt can be used to filter out
the break characters and resume normal reception.
Each break character is identified by a break flag in the
Rx Flags Register (the CCR flag, Framing error, and
CCR Match flag also may become active when a break
character is received) and is loaded onto the Rx FIFO
as a NULL character. If break continues even after the
Rx FIFO is full, then an overrun error will occur but
no further break characters will be loaded on to the Rx
FIFO. The user can also measure the length of the
break character stream by using the Timer.

2-215

inter

AP-401

RXt.4 INTERRUPT--+

READ DATA CHAR

READ CONTROL CHAR

READ DATA CHAR
READ CONTROL
CHARACTER

231928-25

Figure 22. Handling Control Character Interrupts

2-216

inter

Ap·401

SPECIAL ClL-CHARACTER

= XOFF
XON
CTL-C

231928-26

Figure 23. Using Control Character Match In Terminal Ports

2·217

inter

AP-401

5.3.4 DATA INTEGRITY

To improve the reliability of the incoming data the
82510 provides a digital filter, a Digital Phase Locked
Loop, and multiple sampling windows (whichprovifle a
noise indication bit).
5.3.4.1 Digital Filter

The Digital Filter is used. to filter spikes in the input
data. The Rx Machine uses a 2 of 3 filter. The output is
determined by the majority of samples. If at least two of
the three samples are "1" then the output will be a "1".
Spikes of one sample duration will be filtered but spikes
of two or more samples duration will not be filtered.

The sampling windows also provide a Noisy character
bit in the RXF register. This bit indicates that the current character being read had some noise in one or
more of its bits (all .the samples were not in agreement).
This bit .can be used along with the Parity and Framing
error bits to provide an indication of noise on the channel. For example, ifthe Noisy Character bit arid the
Parity or the Framing errors occur simultaneously,
then the noise is probably sufficient to merit a complete
check of the communications channel. The noisy bit
can also be used to determine when the cable is too long
or the baud rate is too high. The user would keep a tally
of the noisy characters, and if more than a certain number of characters were received with noise indications,
then either the baud rate should be lowered or the distance' between the two nodes should be reduced.

5.3.4.2 Digital Phase Locked Loop .

5.4 ' Timer Usage

The Digital Phase Locked Loop (DPLL) is used by the
Rx Machine to synchronize to the incoming data, and
adjust for any jitter in the incoming data.
The 82510 DPLL operates on the assumption that a
transition in the incoming data indicates the beginning
of a new bit cell. A valid asynchronous character frame
will contain one or more transitions depending upon
the data. If upon occurrence of the transition, the
DPLL phase expectation is different from the sampled
phase, then there is jitter in the incoming data. The
DPLL will compensate for the phase shift by adjusting
its phase expectations, until the expected phase and the
sampled phase. are locked in. The user can enable or
disable the DPLL through the Receive Mode Register
.
(RMD).
5.3.4.3 Sampling Windows

The sampling windows are used to generate the data
bit, by repeated sampling ofthe RXD line. The bit polarity decision is based upon a majority vote of the samples. If a majority of the samples are "1" then the bit is
a "I". If all samples are not in agreement then the
Noisy Character bit in the RXF register is set. The sampling windows are programmable for either 3 of 16 or 7
of 16. The 3/16 mode improves the jitter tolerance of
the medium. While the 7/16 window improves the impulse noise tolerance of the channel.

The 82510 has two baud rate generators, each of these
can be configured to operate as Timers. Typical applications use BRG A as a BRG and BRG B as a Timer.
Since both the Transmitter and the Receiver may need
to generate time outs, it is best to use the Timer as a
Time Base to decrement ticks (upon a Timer Expired
Interrupt) from (software implemented) Tx and/or Rx
counters. The Timer can also be used to time out the
Rx FIFO and read characters that otherwise may not
have been able to exceed the Rx FIFO threshold.
5.4.1 USE AS A TIME BASE

The transmitter and the receiver routines use a software
variable which acts as a counter. The variable is loaded
with the required number of ticks that are needed for
the Time Out period. Once started the Timer generates
an interrupt each time it expires, the interrupt handler
then decrements the counters. Once loaded the software monitors the counters until their value reaches
zero, this would indicate to the software that the required time period has elapsed. The Time Base value
should be selected with regards to the CPU interrupt
load. The CPU load will increase substantially when
the Timer is used as a Time Base, therefore using the
Timer in this mode at very high baud rates may cause
character overruns. A time base of 5 or 1 ms is probably the most useful. An additional benefit of the Time
Base is that it can support more than two counters if
required.

2-218

inter

AP-401

5.4.2 USE FOR RX FIFO TIME OUT

BRG-B is used as Timer.
BRG-A is used as BRG.
TB Ex bit In TMST Enabled.
Tx-Timer_Count contains count for Transmitter.
Rx-Timer_Count contains count for Receiver.

In the 82510, Rx FIFO interrupts will occur only after
the FIFO level has exceeded the threshold. Due to this
mechanism and the nonuniform arrival rate of characters in asynchronous communications, there is a chance
that characters will be "trapped" in the Rx FIFO for
an extended period of time.

For example, assume the 82510 is a serial port on
system and is connected to a terminal. The user is entering a command line. The Rx FIFO Threshold = 3,
and at the end only two bytes are received. Since the
FIFO threshold has not been exceeded, the Rx FIFO
interrupt is not generated. No other characters are received .for 30 minutes, if the characters (in the Rx
FIFO) are a line feed and carriage return, respectively,
the CPU may be waiting for the CR to process the
characters it has received. Consequently the characters
will not be processed for 30 minutes.

In order to avoid such situations, a Rx FIFO Time Out
mechanism can be implemented by using the 82510
Timer. The time out indicates that a certain amount of
time has elapsed since the last read operation was performed. It causes the CPU to check the Rx FIFO and
read any characters that are present,

231928-27

Figure 24. Timer use as Time Base for Transmit
and Receive

Inapplications where the character reception occurs in
a spurious manner (the exact number of characters cannot be guaranteed), the Rx FIFO Time Out is the only
way to prevent characters from being trapped. The time
out period is measured from the last read operation,
every read operation resets the Rx FIFO Tin,.::r. To
synchronize with the beginning of the data reception,
initially the Rx FIFO threshold is set to zero. After the
first character has been received, the threshold is adjusted to the desired value. When a Rx FIFO time out
occurs and no data is available, the threshold is reset to
zero. In error free data transmission, the beginning of
data transmission is signaled by the reception of a control character, such as SOH or STX, the Rx FIFO time
out mechanism should be triggered to the reception of
these control characters.

2-219

AP-401

(

MAIN RX ROUTINE)

RX fifO INTERRUPT ROUTINE

231926-26
231928-29

Figure 25. Rx FIFO Time Out Flow Chart

2-220

inter

AP-401

ONE'S
COMPLEMENT
or PACKET
NUMBER

128 BYTES
or DATA

8 BIT

128 BYTES

CONTROL
CHARACTER

231928-30

Figure 26. Packet Structure of XMODEM

6.0 82510 IMPLEMENTATION OF
XMODEM

6.2 Software

The 82510 XMODEM implementation is a file transfer
program for the 82510 based on the XMODEM protocol. The software runs on the PC AT on a especially
designed adapter board (the adapter board design is
shown in Figure 33). The software uses most of the
82510 features including the baud rate generator, Timer, Control Character Recognition and FIFOs. The
software uses an interrupt driven implementation, written in both assembly and C languages.

6.1 XMODEM Protocol
XMODEM is a popular error free data transfer protocol for asynchronous communications. Data is transferred in fixed length 128 byte packets, each packet has
a checksum for error checking. The packets are delineated by .control characters, which act as flags between
the Receiver and the Transmitter. There are four control characters, SOH, EOT, ACK, and NAK. SOH indicates the Start of a Packet, EOT indicates the End Of
Transmission; ACK and NAK are positive or negative
acknowledgements of the packet respectively. The
packet structure and protocol flow of XMODEM is
provided in the figures given below.

Interrupts are used to transmit and receive data. The
software is implemented as two independent finite state
machines-Transmit State Machine and Receive State
Machine. Each state machine is triggered by external
events such as user commands and data or Control
Character reception. The state machines communicate
with the 82510 interrupt service routines through software flags. The ove~all structure of the main routine is
given in Figure 31. The major modules of the software
are given in the hierarchy Chart, Figure 34, which lists
the different modules in order.
The interface between the main program and the interIVpt service routine is done through global flags. The
interrupt handler services four sources-Transmit,
Timer, Receive, and Control Characters. Each of the
interrupt sources communicates with each of the state
machines through the global flags. The state machines
keep track of their individual states through state variables. The interface between the individual states within
a state machine is done through state flags. The state
machine diagrams are given in Figure 29 and Figure
30.

2-221

inter

AP-401

(

TRANSMIT)

SEND 'EOT'
h I
"------,--"

ASSEMBLE
NEXT PACKET

231928-31

Figure 27. Protocol Flow for Transmit Side of XMODEM

2-222

intJ

AP-401

SEND NAK

SEND ACK

RX PACKET #
AND PACKET COMP

231928-32

Figure 28. Protocol Flow for Receive Side of XMODEM

2-223

inter

AP-401

231928-33

Figure 29. Transmit State Machine

2-224

inter

AP-401

4 SEC TIME OUT
AND <10 TIME OUTS

231928-34

Figure 30. Rx State Machine

2-225

Intel

AP-401

mit interrupt service routine reads characters from the
packet buffer and writes it to the Tx FIFO. Since it
does not require the use of the Transmit Flags, no information is written to the TXF register.

START
Initialization
WHILE (NOT QUIT)
{

UPDATE STATUS ON SCREEN
IF (KEYBOARD HIT)
THEN PROCESS COMMAND
PROCESS TRANSMIT STATE MACHINE
PROCESS RECEIVE STATE MACHINE

6.2.2 RECEPTION OF DATA

END
Figure 31. Software Structure
6.2.1 TRANSMISSION OF DATA

The Transmit interrupts are disabled until data trans.mission is required, this prevents unnecessary Transmit
interrupts. The Transmit interrupt is enabled when a
packet has been assembled or if a Control Character is
required to be transmitted. Upon invocation the Trans-

Data reception begins only after a Start of Header
(SOH) control character is received. This control character puts the receiver in a data reception mode. After
receiving the SOH, the CCR interrupt is disabled (since
all data being received now is transparent and can not
be interpreted as a control character). After 132 charactersare received, the CCR interrupt is reenabled and
the corresponding ACK or NAK sent to the Transmitting system. The receiver has a time out feature, which
causes it to check the Rx FIFO for any remaining characters. End of Transmission is indicated by an EOT
control character, which causes the file to be closed and
the Receiver to go into the Idle state.

.....- - - - - - - - SEND_CCR_RO(F'ROt.A RECEIVE STATE t.AACHINE)

TX
STATE
t.AACHINE
CCR_TO_GET
GET_CCR_RO

(,~,)

RX
STATE
t.AACHINE

BYTES RXD

RECEIVE

Figure 32. Using Flags for Communications with Interrupt Routine

2-226

231928-35

(

74LS04

A8~W
1
U9
74LS04

IBM-BUSS

PIN #
N;BN
N ;AN

A7 24

!!..

A6 25
A5 26
A4 27

~
~

DO
01

-..J

AEN

R2
2K

4r?

1 -1 f 1 I
t=============~51~ ~8~~r-~==--~
Cl

~O 2 Y112

~
~

.£
~

Q!!

!1!

1 26

2 27

Q2.

3 28

Q§.
.!2§.
QL

2
3

~
'lJ

07
jQR14

-I

lOW 13

lOW

IRQ4 24
IRQ3 25

IRQ4
'RQ3

:too

:too
a.
DI

"2ID

...

RE~~ ~O

r---'3
4

18,43~

+12V
lY

2A
GNo

2Y
-12V
U5

oTR

RTS

15
16

oTR

RTS
Xl

-12V

TXo

TXol

'tI

jQR

RESET

OSC 30
-12V 7

t!..!..;",,2
f \2K
l
2

82510

03
04
05 4

+12V

75150-P

Co)

I\)

iil
i\:,

Ull

ii'

I\)

+5V

3"- _4

A8 23
11
AEN
A9 22

28
A3
Al 30
29
A2
AO 31

16 8

oPSW

14
4

III!I' 1

Ir.::=¥
r--zo
[f;:
I

0j31 _ U110=-+

RESET

INT

-12V

+12V ..9---"-,,,,
GNo 1
GNo 31

o
.....

RXol

l.r ~ WR
'7

+5V

75154

5V 3
OSC 30

4
5

MOTHER-Bo
+5V

2T
4A

lY
2Y

14
13
12
11

Ul0

10
9

1T
U3

oSR
74LS05

131>0 12
U4

231928-36

cl
"II

6
c

Cil

f>'
I\)

::z:

ii"

~ ~

CONVIG_510

....DO

n
~
(')
:::T

231928-37

inter

AP-401

6.3 Software Listings
"AIN FROCRJ.M

PACE

ftp.c

82510 XHODEH

1. tinclude "C : \ f tp\f tp. del"
2. 'include "C, \lc\fcntl.h"
3. linclude "C, \lc\stdlib.h"
4. Unclude "C, \lc\stdio.h"
5. / •••••••••••••••• It • • • • Iit • • • • • • • • • • • • • • • • • • • t
6.

/...

7.
8.

I fI .. "
J ....

• •••• ,

.. ...

SEPTE"BER 19 B6

.. 111 • • • /

''1. II */

t. , ...
10.
11.
lZ.
13.
14.
15.
16.
17.
18.

•••••• ,

/
82110 I"ODE" I"PLE"ENTATION
/ . . . . . . . . . . . . . . . . . . . . . . . . . . " •••••••••••••••••••••• ,
ant
eof .hlse;
f. end of fila nlQ . /
tnt
rlpk =0;
int
luf1g;

tnt
int

rullg.
up_pkt_nu..

int
tnt
int

pklt;

r.toc:ntj
quit .hln;

19.

tnt

hY' :

10.
21.
Z2.
23.
14.
25.
16.
27.
28.
29.
30.
31.
32.
33.
34.
31.
36
37.
38.
39.
40.
41.
42.
43.

int
tnt
int
int
int
int
int

sohcnt =0;
rJh:nl .0 i

/. nut pacht nu.bet .. peeled by rec,iut

'* Tille

'I,

Out counter (or rlcei'er *1

/.
Gf SOli chuacters rec:ei .... d
I·
of R. FIFO Interrupts .,
c.crc.nt .0 j
I • • of Ct I-Char. Interrupts * I
I. Tuns.itter Shte Variable .,
ll_stlte .ll_1dll.
II_StJ.t. = r'I_idll; I. Receher State Variable *1
I. Indicates _ V&1id TI. Command was ;i . . n *1
t._clld • inactiv.;

/. Fi J e to be Tr_nnu t ted ./
char
t I flle nuu[401

/. Fi Ie to b. Received ./
fl1e_nlme[40J
char

tnt

lnt
int
char
chat
char
char

send _ccr_req
int ... ec .0 ;

inlet iVI;

1* Fla; - Request to T. Ctl-Char *1

1* containli the

CIR vector .1

I. T. Buffer .1
III Rio Buffer .,

hdah 1 IllJ;
tlbuf [ I 18J;
tlda ta [131 J;
r I_f_bu f 132000J;

I. HI Fill Stored in this buffer .,

*•••••••••••• *••••••••

, ••••••
1
1* •• h: state variables ••••• ,

44. I •••••••••••••••••••••••• • •• ·,
45. int
46.

It Pointer to the nut character in the
bufhr .,

tI_indJ.i

47.

48. struct
49.

50.

51.
12.
13.
54.
II.

packet
char
char
char
char
char

head;
pa.ct_num;
pact_cmpl;
but fer [118]
chksmj

57.

231928-38

82510 XMODEM Implementation

2-229

inter
PAGE

AP-401

58.

*_ .......... ** •••••••••••••••••••••••••••••• I

59. ,** •••••••
60. ,....
tJ: State aachine and interrupt
U.
handler fhgs
6Z. , ••••••••••••••••••••••••••••••••••••••

'*...

'3.
U.

'*'

h. and t .• f ito

'5. lnt

t. _uq

int

=0,

ccr_t o_t a = 0,
h_bytt_cnt =0,
pUs_sent .. 0,

u. int
70.

t.,

71. / •• Timer
72. int
h_ti ... _cnt =0;
73.

•••••• /
•• u**'

** ••••••••••••• I

indicates I request for transmission to
82510 Interrupt Hl.ndlu *1
/* Actual Ctl-chu to Trans.it *1
1'* Total. of Bytes Tnns_ithd *1
,'II. • of Packets sent ./

1* Flag -

Tunsllitter Timer Counter

**'

74. Itt CCR
75. int
olt_cc.r_tq cO;
,. Fla.g - Request to Rectin Ctl-character .,
76
int
cu_to_oet =0; ,. Received Cti-char 'Ia1uI .,
77.

,.** •• ** ••• ** ..........................................·····f

78 .
77.
80. /....
81.

.....

.. . . . ,

,.u.
,u __

.....

/
••••• I
/

HX STATE VARIABLES

83. , ....
84.

I • •••••••• "/1 • • • • • t

• • • • • • t ••••••• t •• "/I t t • • • • • • • t •••••••••••••• ,

IS.

char
87. int
'8. int

pk_chks.i
eot_cnt =0;
bld_pU_cnt;

8&.

1* Calculated Chl:sull
I of £OTI Received ·f
of Bad Packets Received */

'* •

91.
92.

I'...

I ' •• • t ••••••••••••••••• t •••••••••••••• t t t • • • • • • ~ • • • • J

"90.

/ ••••••••• t

It.tt

• • • • • • • • • • • t • • • • • • t •••• t • • • • • • • • • • • • • • • t .

ra state machine and Interrupt

••••• ,

ha.ndler flags

t •• **/

94.

'5.

.
96.

'"
int

'7
,. '"
98 .

100
101.
102.
103.

fi fo

u_byle_cnt
ttR

.0,

1* • of Bytes Rec.ived .,

=0,

/* Fh9-Indic.at inlJ that a Ct I-Chu. hu hen
receivd·'
,. Aclual Ctl-char received

int

ell _ud_' 10

int

ra_ct l_chr ... O;

104. 1** Timtt
ttl
IDS
int
u_tiae_cnt =OJ

,. Rtceive Timer Count .,

231928-39

82510 XMODEM Implementation (Continued)

2-230

infef
PACE

AP·401

IIAIN PROCRAII

ftp.c

81510 XIIODEII

106 .
107.

/ •••••••••••• "' ••••••••••••••••••••••••••• ,

lOB. /..
MAIN ROUTINE
..... ,
109. / ••••••••••••••••••• " •••• l1li • • • • • • • • • • • • • • • ,
110.
111.

()

112 .
113.
114.
115.
116
t 17.
lIB.
II'.
110.
121.

int
int
int

[11'&1,11'

int

WD_stat\Ui

tnt

.cod.
• fp;
-[alp i
["'tit j

q,tJ:fl.tlfli
,,OJ
cad", 0 j

FILE
FILE

int

int
Ul. int
int
U4, int

.0;

= 0;

west;

1Z3.

t oent

125.

tl_secs, fl_secs;
i,s, Ipcnt = 0;

int

-0

"
"

116.
127.

eLR

128.
129.
130.

"V_CURS (SO_foSC_c.);
print! (s1);
init ( ) j

131.
132.

IIENU () i
enbint4 ();

R.trlnslIit c.ount
Ti.e Out Count *1

*/
Sign On HesuQe

"
"
"
"
"

IniHalin 815 I 0 and Varhbles
Pr int Menu
Enable Interrupts in 81S9A
Issue EOI

133.
Qutp (ipOO.loil;
134.
Qutp «bpu3),OI12);
stut timer B
of Loops
135.
Ipc.nt =0;
JtUPIi Tr&ct of
136 .
137. I flt • • • _. fl • • • • • • • • t . t t ••• t • • • • • • • "* •• ' . t . t ••••••• t ••• J
138.
.~in while loop
•••• ,
139. It. t t . t t •• t t ••••• t •• t •• t**. t • • • • • • • • • • • • • • • • • • • • • " "I

I...

140.
141.

•

,", elu,r Screen

()j

"
"

•

while (quih .. fals.)
(

141.

143.
144.
145.
146 .
147.
148.
149.
150.

,,,,, ••••• ,, ••••••••••••••••••••••••••••• ,

,**

display protocol p&ramlhtl

, •••••••••

I. . . . . . . . . . .

++ Ipcnt;
mv_cuts (4,30);
printf ("loop' .. "u",lpcnt)j
lilY_CUrs

(4,50);

151.

print! ("n tnt. cnt

151.
153.
154..

1II._CUts

15S.
156.
157.
158.
IH.
160.
U1.

IU.
163.
164.
165.

'/I •• '/I'. *•••••••• /

"u",rs!cnt);

(5,'S0);

printf ("ccr int cnt
"u",ccrc.nt);
.._curs (4.1>;
print! ("interrupt yector .. "u \n", intvec);
q = inp (bp.l+4J;
tlO .. q & 0107;

my_curs (5,l);
print! ("TI FIFO
g = inp {bpl.+4)j

Iftu ",tl:fll,

01:10;
m._curs (6,1),
u f l .. q ,

printf ("RX FIFO .. "u \n",tlfl/16);
..,_curs t6, 50) ;
printf ("SDK count:. 1Ir3u",lohcntJi

231928-40

82510 XMODEM Implementation (Continued)

2-231

,inter
PACE

166,
167,
UB,
In,

170,
171,

PI,
173,
174,
In,

AP-401

HAiN PROGRAH

.,_curs (7.1'

f t P,c

8Z 51 0 SHODEH,

printt' cab,t .. flCthld "SuN,n_byte_ent);

.,,_cun (1,30);
printf c"a,t .. S.nt • 'lt3u",la_byte_cDt,;
.,_carl (7,SO);
ptinti ("EDT count ~311", •• t_C1IU,
.,_cuu (5.30);
printf ("pttl rId • "3a·.(.lp_ptt_na~-1»;
(6,30);

."_CUri

176,

prll\tf·(Hpth •• n t . 'lt3u". pttl_IlnU;
h_IICI • tl_t i.,_cnt I ZOO';

171 '

fl_l.es • rI_U.,_ent/%OO;
open_wind (3.1."TI Ti.,t");

177,

17' ,
110,
III,
lIZ '
183,
114,
115,
'116,

pHnlf (" • "20 .le.",lI_IICI);
open_wind (3,SO, .... Ti.er'"J.
prtntl ( .. a 'Iu ItCI H ;r'_ltC~);
in_CUrl

(',1) j

printt ('" ... d 'actttl Rad • li3u" ,b .. d_ptt_cnt);

",..._cun C.,, 3D);
printf

(HI

of atTa p .. cktts • "3u",reh_c.nt);

117. 1* If Co_and I.sUld then proCI" the Co•• and */

III,

I.!.

If 0 '
191.
IU,

.t..
193,

«to,

.tbhit()) ) D)

quit • proce.,_cad ()

tl.1
I

/.....

,,*....
.....

US.
196.
197,

,.....

IU,

~.*

*** .................................................. /

it.tt,

.....,

'rocI.I TI STATE KACKINE
uyilion 0

..... ,

•••••• •••••••••••••••••••••••••••••••••••• *•••••••••• ,
~

iU,
200,
1~1.

switch Ch_ltatl) (

c .... h_idle:

21Z ,
203,
104,
205.
206 '
207.
201,
209,
210,
211,

, ••••••••••••••••••••••••••••••••••••••• t •••••••••••••••• ,

"f!**

/....
.....
,,...
,....

,....
,....

.....,
........ ,
..... ,

TRANSMITTER IDLE STATE

..... ,

Chicks for .. Stnd Ctl ... Chu.
Chtch for- thl Tr ..... it Co .... nd

~ .... ,
... **/
~.,

/ ••••••••••• t ••••••••••••••••••••••••••••••••••••••••• •

~.,

212,
213,
214,
215,
216,

,. If Control Char .. cter to be Tun •• ltttd Tben Tranl.U tht
Control Char .. ct.r b, •• ttiDg tht T._,tq Flag and tnabling
tht TI" .. nd TI FIFO Interrupts .,

li7,
211,
21' ,

no,

h_rtq _ct I_ctu;

221,

t l_i_Inb ()

212.

whil. ( tl_req)OI;
h_i_dts C);
•• nd_ccr_reqalnact i ... ;

223,
314,

225,

231928-41

82510 XMODEM Implementation (Continued)

2-232

inter
PAGt

Ap·401

110\ IN PROGRAM

az 51 0

t p. c

IMODEK

If the Tran,1IIoit Co •• and is issued then 'Jait for a HAl.'
if (tI_cad
leti . . )

22& .

227.
2%8.

219.
230.
231.
232.
233.
234.
235
236.
237.
238.
239.
HO.
241.
242.
243.
244.
145.
246.
%47.

(

\a_cad = inactiv.;
g.t_c.c.r_rq aact iu;
tl:_ti •• _cnt "lOO.'Oj 1* 60 sec. Tilu Out */
h_shh '" wait_HAli
break;

cas. wait_HAK

1* 'Jaiting for I NAK chuactu to blgin TI

/ •••• t. It • • • It • • • • • • • • • • •

III • • • • • • It • • • •

*.t •• t

,tt ..

TRANSMITTER \lAITING FOR A HAK TO BECIN

IU"

TRANSMISSION.

I·t ••
I
,ttU

ttl..

......t. ,
.....
..... 1

Ch.cks For Till. Out
KA~

"Ot

RIC.i"d

wn_statul " chick_wait ();
,witch (wn_l,htus)

(

• • • • • • • • • • I!iJI • • • • /

• • • tlt

I
/
I

It,

Tiln Out or N"K Rcvd?

248 .

249.
2 SO.
251.
252.
253.
254 .
255.
2S6.
257.
258.
159.

260.

/* If Timl Out th.n Abort
t

&_, t

&t •• t

I_I d 1. i

bup ();
pr.59 ("Tia. OUT tl!! receiver not ready");
ell (\I_I". t a_c) j
open_wi nd (t 1_' • t I_C. "NONE") ;
bud:;

case waiting
break

if no Time Out and no NI.K
rc.d then do nothing

261.
162.
263.

2&4.

16S.

If NI.K received then open
file &nd adunee to
Transmit Pac.lett State */

266 .
167.
268.

fp =fop.n (ta_file_na ••• "rb" );
if (fp=" NULL>

269 .
270.
271.
27Z .
273.
274.

(

beep ()

pr ... g ("ERROR !!! file don not .ailt");
ell (tJ_r. h_c.> j
open_wind (t.~r,.t._c. "none");
tI_llat . . . la_idle;

275.
276 .
277.

)

else

278.
279.

h_state = tl_rdy;
tufl; .. akpldj

280.
281.

W1L_.tatus • 0;

282.
283.

184.
215.

/* First tast for T.
is to Preparl Packet
/* Reut Vait_N1K Fhg

)

*,
*'

buak;
)

brlat;,1 end

v,it n.t I,

231928-42

82510 XMODEM Implementation (Continued)

2-233

AP-401

PAGE

216.
217 .

ZII.
219.
190.
191.

ZU.
193.
Zt4 .
U5.
196.
297.
298 .
U9.

300
311.
302 .
303.
304.
305.
306.

Itp.c

IIlIN PROCRAH

I It ••

81510 IHODEH

t. ttt •••• t • • t t.t ••••••• t • • t . t . t •••• t •• t •••• t II •• I t . t *I

.....
,,,...
.....
,....

TANSMITTER READY TO TRANSMIT
thr •• Itagl' of tran •• h,ion

/.,**

..... ,
..... ,

pr.par. Plct,t
.tt .. I
Int. HandliH Trln.al tt ino U"*'
or retran •• tt rlqaut
..... ,

/ •• *t.t.t ttt It •••• t

••• t

••••••••• *t •••• t

t.t._ ..

t •••.••

"".t.

1* An, Control Character To Transait? */
if « .. nd_eu_flq •• lethe) II UK_rl,."))
h_rlq .ct l_chr;

Which Stagl of trln,at.,ion '*/
Iwltch (luflg)
[

eal. atptt:
if

1* 'rlpul Plctet

(h_rlq •• U

[

307.

&.abptt (pUS_llnt,rp);
cp,U.f ();
tS_fl' .pit;

301.
30P .
310.
311.

tlrf.9 .t.at,i
h_lndl .0;
tl.:,i_Inll () i

/* Rlqul.l tnt. Hilldler
to T. ditl in lIuUer
1* Stut Tnn,.inlan *1
I. Enlllll TIK Ind T.

31Z.

·rlFo

Inhrrupt. .,

313 .
314.

315.
316.
317.

h.at.
ca •• t.at,
if UI:_uq ••

311.
3U.
UO.
311.
UZ.

.0.

lntlna,t Hlndler R••• t.
this flal to 0, wilin 182
lI,t'5 IU trln.a! t hd

h_indl
pra'I (."Plct.t tran.aUhd") i
•• t_cu ..)·.· .lcli1'''
J. Vait lor ACIt or HAlt *f
tI_H.,_cnt • ~OO.lO;
./. 10 IIC Tla. Out ./
h_Itlh .·waU..:..CCi
Vait .for ctJ Charachr .,
hrflg .atptti
\a_i_dis (li
J. Disdlle Ta" aad TI rno
Interrupts

3Z3~

314.
U5.
316.
317.

UI.
319 .
330.

Ill'

331.

1* TI_rlq Rot UI.t thin,
pra., (lltranlattti_vtl);
Itlll tran.alttln,

331 .

333.

1* Th, Rltrallsait uqu •• t 11

cal. uti :

isla.d by the \llit _CC

134.
335.
~36 .
337.

state .,
outp( CbPI+U. hln);
h_rtq

340.
341.
3U.
343 .
344 .

hrflll _t •• t,i
la_I_Inb ().j

3n.

,. Inablt tl., f luh h
,

pttj

331.
339 .

:II

f Uo

h .... ,

,. tu,n •• it 'act,t,ptt. in
baffer .• ,
1* nllt hlk .. R,Tran •• it *1

1* EnaU. TI" and T.
Interrupts *1

rlFo

IIr.ati
I

br.ati 1* End h

rd, ca •• *1

231928-43

82510 XMODEM Implementation (Continued)

2-234

inter
PACE

AP-401

IIA IN PROGRAII

It p. t

US I 0 XIIODEH

......
... ,'
.....,
...... ,
•••• t,
..... ,
...........,............................................

347, / ••••••••••••••••••••••••••••••••••• 11: • • • • • • • • • • • • • • • • • • • • /
348. / ••••
349, , .... Tran •• ttt.tr State - VaitiftlJ For ttl Char.
/
350. , . . . .
351. , . . . .
MAX - reqults rlhan,.h.ion
3'%. , . . ..
AeX - Tun •• lt N.. t Pact,t
353. , . . . .

"'-'/

1$4 .

ISS. /
IH.
157.

west •

c:h.c~_wljt

();

lSI.
159 .
360.
361.

HAX Rluiud
leK RIel i wed

or Sit 11 V&it ing ' /

36Z.

363.
364.
3'5.

Iwitch (WClt)
[

'" .

/* If Til... Out, than ustart
TI Tiau. "bot t 11 Ti ••
Out count is IIre.hr than
ten *1

347.
341.

3&9 .

370
371

/. ChIck for on. of lb.
FollowinG .... nt. :
Tl •• Out

if (toent

)10)

3H.

[

373.
3?4.
375.

WClt .0

abort_tt ();
pra'9 ("rlc,ivlt not r •• pondina");
I

37& .

377 .
371.

379 .
310.
311.
312 .
313.
314.
315.
3U.

uloenl;
h_ti.'_tnt _100*10;

/* Int. Ti •• Out Count *1

I
bruk;

call wai tina

1* if waitinG. do nothinG '1

brlat;

317.

311.

1* If HAK or Corrupted
ttl-ehar. rleli",d '1

319.
390.
391.

392 .
393.
394 .
395.

rl_Gln
pra'9 ("N1K r,eth,d");
if (utl_ent )10)

CII.

ou than 10 attl.pll,

then AbortiJ
rlll_ent .0;
toent .0 j
abort_tr ();
praia ("Bid lint tranl.inion aIIorhd");

397 .
391.
399.

J• •

231928-44

82510 XMODEM Implementation (Continued)

2-235

intJ
PAGE

400.
401.
40 I403.
404.
405.
406.
401.
40B.
409.
410.
411.

AP-401

HAIN PROGRAK

ftp.o

8ZSI0 XKODEK

.1 ••

If R.tfan •• tt Count Not
ucl,ded then go bact to
Tranl.it Ihg. - hit is

r e tr an •• it _' */
hrtlg _uti;

++ rltl_cnt ;
ll_,tat. atl_tdy;
)

breat

ca •• rs_lex.:

411.

prll.V ("",eK teethed");

413.
414.
415.
416 .
411.
4\8 .
419.
420.
411.
421.
413.

r.t.~c.nhO;

lex. R,c.i".d.'

toent .. 0;
++pktl_,.nt;
PI int f ("pUs_,.nt • "311", ptt __ IInt);
if (,of ... fallt)
1* If aort data to tran,.it
thIn r.trun to akptt
shge Ind h new ptt. *1
htfl; "lItptt;
ll_,t&h .. t:r_tdy;
)

el.1

424 .

415.
426 .
421.
421.

(

pr.'g ("'Inding EOT")

cc:r_h_h II EOT;
tl_r,q .. c t I_chr ;
t._i_Inb ();
wbtl. (tl_uq 1.. O'i

429 .
430.
431.
432 .

433.

tl_i_dil ();

434 .

g.t_cer_rq :ac.ti'fl,
whi I, (g.l_cer_rq •• uti".);

435.
436.
437.
438.
439.
440.
441.
442 .
443.
444.
445.
446 .
441.

br,ak;

448 .

) /. 'end IwUe.b ta state *1

if end of f i l l , th.n
lend EOT

wlit for

Wlit

Int. Handler

to ruet fh; *1
for Aet

prasg ("EDT aetnowl.dg ••• nt rlc.iw,d");
if

(c:u_to_get ._ ACID

,. ACK nd

Clou UI • • /

[

1= fc1U' (fp);

lbort_tl();
prm.g ("(i1, tran •• ission t:oapl.h");
tI_ltate atl_ldl.;

/. R.turn to Idlt */

)

brut;
)

lend wait_e.c c:as, ./

231928-45

82510 XMODEM Implementation (Continued)

2-236

-inter
PlCE

449.

Ap·401

"l IN PROCRl"

It P c

,*** •••• ** ••••••••••••••••

U510 I"ODE"

'111 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ,

450. ,.....
ProceSJii R. STATE MACHINE
..... ,
451. /......
re"ision 0
•••
452. ,.....
453. / ••••••••••••••••••••••••••••••••••••••••••••••••••••••• "
454.
switch (n_stl,h)

**,
.*.u,

455.
456.
457.
458.
459.
460.
461.
4U.
463.
464.
465.
466 .

(

case u_idle:

/ ............. *** ••••••••••••••••••••••••••••••••••••••••• /
, .. ,.t
••••• /
, . . . . RECEIVER IDLE:

....
,".,.
........

.......... ,,
..... ,

It •••

t.t.*/

wai tI for \lSlr co_and
bel ore undinCJ NAK.

.....t.*,
.~ i t

*/
/

/ •••••• t ••••••••••• ttt •• t •••••••••••••••••••••••••••••

4£7.

/* If tlCI h. Co_and 11 is.uld

468 .
419.
470.
471.
47% .
473.
474.
475.

thin start ax t ian and chaD"

"6.
477.
471.
479.
410.
411.
41Z.
413.
484.
·415.
486 .
487.
418.
419.

R.c.hu

498.
499.
500.
501.
501.
503.
504.
5D5.
5U.

to ready

:I;

breat;

,........................................................
.ends NAK upon
Out
,
,
or checks

....
......
....
.....
........
.
................... ,
........
....
,........................................................
,

,case

ra_rd,:

, .... RECEIVER READY:
/

Tia'

/
/
/
/

for SOH

or EOT ctl .. chu.

/
/
/

,- Checks Rt: Tiaer and returns Tia, Out if e.pired
waiting if not .. pired

490.
491.
491.
493.
494.
495.
496 .
497.

st~h

,x_stat. .. ,a_,d,;
,._ti.,_cnt -10D.1D;
u_cad
inlctite;

SOH if SOH ccr ,ecei,ed
EOT if EOT ccr rec.lud -/

switch (,arUa)
(

case waitina
breat.;
C&II

SOH

/. If waiting then do nothina ./

,. If SOH nc.ited, then go into
data tlc.pt ion aodl and chaDal Rz
Ttau count to 4 .ICS . ,

,++ 50hcnt;

ra_It&t. ar .. _ptt;
ra_Hae_cnt _ZOO'4; 1* lour !lcond iiae out *1
utocnt =0;
breat;

231928-46

82510 XMODEM Implementation (Continued)

2-237

intJ
PAGE

AP-401

MAIN PROCRAM

ftp.c:

12510 IHODEI1

1* if tI •• out & not in th aidat of

508 .
SOt.
510.

pac:ht rtception then •• nd HAlt

Ie up_ptt_"ua .. 1) "

lu_byte_cnt .. 0»

(

pra.o ("u U •• oat I!!!! undint HAlt .. );
i.f Cund_ccr_rlq •• inlett •• )

512 .
513.
514.

I
ecr_to_tw -NAlti

'Ind_cel_req 81Ct ht;

S16.
517.

[a_tiat_cnt _200*10,

511.
519 .

brut;

ClSt EOT

'"'"

It If End Of Tnt rc"d,

and ht. [c"d thtn
stlnd lCI And
all
pactets uctiud in
fih .,

.& ..

513.

514.
525 .
5U.

++ tot_cnt;
.
open_wind (2Z.Sq."End of Tnt");
if Cup_p!tt_nva }t)

521 .
521.

(

if, I.tnd_ccf_rllq .. inac:ti •• )
( •• nd_eel_req .acti •• ;
cct_to_h _lCIL

530.

532.
533.
534.
535.

Send ACIt *1

R.c.i.er R.turns to
Idlt '1

1* cr."h !ilt ./

SU.

txfp .. fop.n Irll_fiI._naat,"ab+");
rwst .. {write (lu_'_bufCOJ,UI,up_pkt_nva-l',ufp);
if (rw,t (1)

537.

538.
53f .
54'

(

pras9 ("lJtih filt urn '0);
printf (".rror .. ft4u", (rwst=f.rror(rxfpl»;

54.1.
54Z.
543.

5.4.
545.

i f (r9,,1 .. Q)

r.,,1 =fclu. (rafp);

.Is.

SU.
547,'

pra.9 ("file r.c.h,.d");

pr •• v ("Error in clo.ing fil. ");

541.
549.

550.
SSt.

brUk;
I

bruk,

553.
554.

55'.
556 .
557.
551.
559,
HO.

/'. nt,

........................................................
/....
.....,
,....
..... ,
,....
..... ,

cu. u_pkt:

/. P.ck.t r.c.ption ./

,....

RECEIVE PACKET STATE

..... I

563.

,....
,....
,....

564.
565 .

/ ••••••••••••••••••••••••••••••••••••••••••••••• *•••••••• /

56l.
562.

5" .

ch.cks for Ti •• Out
or 131 byt.s r.c.h'.d
which signal. the .nd of pack't

..... ,

"'.'1
..... ,

231928-47

82510 XMODEM Implementation (Continued)

2-238

inter
PAGE 11

117
568.

569 .
570.
171.

AP-401

MAIN PROCRAM

Itp'

82510 XMODEM

/. If valid HI Time Out. i .• no data teethed for 4 secs then
c.heck R. rIFO for e.huactul &.nd Itad 11 any . . . iIable ./
if «[I:_ti ... _cnt ... 0) "
CII_byh_cnt (131»
I
utI ... (linp (bpI. +4> , 0170)1 0110);
/. check R. FIFO

171
173.
174.
575.
576.
577.
578.

«utoent l. 10) "

rI._stat. :l:rI._idlei
pc •• g: (" Rec.,i"e{ Ti •• Out, no DATA");
r.toent .0 j

511.
58l.

515.
586 .

els.
,. otherwise restart R. Tiaer, and read data fro. 510 ./
I

587 .
118 .

if
I

(nfl

'II

ufl .. «(lnp ( bpi!. +4) & 0.70)101:10);
whU. ( nfl != 0)
Read from FIFO ./

ndata [u_byt._cntl .. jnp (bpal;

594.

,._byte_cnt;

595.
196.
197.
198.
599 .
600.
601
602
603.
604.
601.
606
607.
608.
609
610.
61l.
612.
613.
614.
615.
616.
617.
618.
619.
620.
621.

ufent;
nfl;

623.
624.
625.
626 .

RJ: FIFO 1..,.1 ) a */

rI_time_cnt .. ZOOIS;

589.
590.
591.
591.
593.

&22.

1* if aore than
10 attemph
and no da ta
thin abort
tran •• l l .,

177.
180.

113.
114.

(ufl ( .. 0))

'Itoent .. 0 j
else
I

utoent

I. inc.

,._tl.,_cnt .100*4;

recdYe TiiDlOut

Count

e lie
I

U_byh_cnt .. 0;
n:tocnt cO;
pkst II:chkpkt (e.p_pkt_num)

«ptst •• tok)

'*'*

Ch.ck PI,cktt
retarnl EOK if Packtt
without trrors

(ptst .... old»

(

prmlg ("llnding ACK");
for (i..O; 1<121; i u )
ubuf [1] II: udJ.h [i+2];
writ. packet to bufftr
if (ptlt ••• ot)

'**

*.,
'*

copy to .ain fill
bufftr

82510 XMODEM Implementation (Continued)

2-239

231928-48

inter

AP-401

MAIN PROGRAM

PAGt 12

627.
628.
6U.
630.
631.
63% .
633.
634.
635.
636.
637.

Itp .•

82510 XMODEII

but_epy (lIp_pl:t_ou.);
++ up_pkt_Duai

.lse
PI •• V ("old -putet retran'.itttd");

els.
.h_pkt_pu •• ();

/. If error th,n show

pack.t If chhua and

paet.t co.ph.ent .,

638.

[I_.t.t . . . t'1:_rdJ;

639.
HO.
641.
642 .

a.kintt ();

643 .

.nbint 4 ();

set_hant (00);

Enable etl-ChI

int:ll:'

outp «bp&.l),(lnp(bp&+l)Ic.c.i.n»;
lut_bant (01);

644.
s.nd_ccr_req ... eti".;
ccr_to_h ,.,,,CK';
645.
646.
647.
648 .
649 .
650.
breat;
651.
652.
} /u .nd switch r I sht. U/
653.
654.
655.
)
end ehe
656.
657. } 1* Ind whi 1. quit
658.

,9.

/* Send leI( */

6$9.
660.
661.
662.
&63.
644.

IttSIO 0;

outp «bpa + 1),00);

cad

= 01:10;

'''lnp (OIZI);

66S. cad
66'. oatp

/* IUtt 82510
1* diubl, 82510 interrupts .,

disable Il57A interrapt *1
00010000
*1

(y: cad);
(01:21 ,clIld) i

667. ell ( ) i
668 . • cod.

= o.

"9. _u:it (tcode);
670.
&11.

)/. end a.in ./

672.

231928-49

82510 XMODEM Implementation (Continued)

2-240

AP-401

HA IN PROCRAH

PAct 13

It p. c

12510 XHOOtH

673.

674. rst510 ()
675.
616.
677.

, •••••••••••••••••••••••••••••••••••••••••••••••••••••••• /
/....
UUJI/
, .. ..
RESET 81510 to d.fault "'loki up aod.

.•.....*. II',
1:. I t . I

618. / ... .
679. , .. ..

•• t I t I
680. , . . . .
681. , •••••••••••••••••••••••••••••••••••••••••••••••••••••••• ,

Ul.

683.
684. ut_b&nk (01);
U:S. OUlp «bpu7),O.1O);
68 •. )
681.

681.
689 . • • nu ()

"0. , ••••••••••••••••••••••••••••••••••••••••••••••••• (

&91.

t.tl. ,..
&93.

displ"y. lhe .Inq on lh,
sc.rlun.

''''. ,..
'**

.. ,
..,
.. ,

..,
tI,

&95.

"6. , •••••••••••••••••••••••••••••••••••••••••••••••• 11/

697.
698.
699.
700.

open_wind (l,l,"b&ud ratl");

701.
702.

printf (" • 1100 "Ii
open_wind (1,22,"chu. silt");

703.
704.
10:1.
106.
101.
108.
109.
110.
111.
111.
113.
114.
11:1.
116 .
111.

prtntf

(" • 8 bits");

open_wind
printf ("
op.n_wind
printf ("

(1,45 , "Puit,");
dilabled");
(1,68, "Slop Bils");
• 1");

av_curs (Z,l);

pr int f ("us.r .'llag •• :") i
(10,1:1);
printf ("(1) TRANSMIT FILE
II);
OPEN_\llND (tl_r,tJ._c,"non.");

."_CUti

• .. _cuts (11,15);
printf ("(I) RECEIVE FILE
II);
OPEN_WIND (fI_r.rx_c,"non.");

231928-50

82510 XMODEM Implementation (Continued)

2-241

AP-401

PACE 14

"AIN PROCRA"

710. /
/ ••

7n.

713. I t .

714.

125101"ODE"

.................................................,
,t.
,.t,
.... ,,
,a.
,..
..,

718 .
719 . inl t

721.

ltp .•

()

Inti.lil .. Softwat. and ConfiGure.

../

the 82'510. Also
Handler.

.. ,

up the interrupt

715.
716. , • • '11 • • • • • • • _ • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ,
717.
718 .
129. h_ti.'_t.nt .ZOO;
130. ra_t i ••_cnt clOGO;

731. initpac;k (.;
731. cI •• ();
733. lnit_ih 0;
134. confio_510 ( ) i
135 . • • t_bant (01);

/' Set up lnterrupt handhr '/
Configure 12510 *1

Switch to lant on. for operation ./

736 .

737.
731. initplck
739.
740.

741.

, ••••••••••••••••••••••••••••••••••••••••••••••••• ,.

'**
,tt

Int hI iUI Ta Bufftr to NUL.

int

H,
**'
It,
, ••••••••••••••••••••••••••••••••••••••••••••••••• ,

7U. ,..
143.
744.
745.
744.

747.
741.

hpack h •• d • SOH;

741.
7!'iO.
751.
752.
753.
754.
755.
756.

,spact.head .. SOH;
hpact. pact_nu• • 0:
npact pack_nu • • 0;
hpaet.pact_e.pl • 0;
npaet.p.et_capI .. O.
for (hOi i (U9i h . '
(
r 'plet. buf fir [il .NUL;
757.
tJpaet.bafflr[iJ .NULi
751.
759. hpaet ehts • • 0;
760. r.paet. ehts • • 0;
761. )
761.

I..

763. enllint4 ()
·764.

, ••••••••••••••••••••••••••••••••••••••••••••••••• ,

76$.
ttl
766. /..
Enabh. INTt in the '259'
767. , ..
761. , ••••••••••••••••••••••••••••••••••••••••••••••••• ,

'*'
..,

7" .
770.
711. int

771. I_t

tnt_Inl) • hEF i

773.
714 . .,-tnp (lpOl);
715. tnt_Inl) • (y , int_Inb)
716. oatp UpOl,tnt_Inb);
777. )

I. 11101111 ./
j

231928-51

82510 XMODEM Implementation (Continued)

2-242

inter
PACE 15

Ap·401

MAIN PROCRAM

82510 XMODEH

ftp.c

778. llsk:int4 ()
779. / •••••••••••••• ** •••••••••••••• ,. •••••••••••••••••• ,
,,/
180. / "
,,/
Mask! INT4 in the 8259A
781. ' "
,,/
182. /fU
784.
785.

int

786.

i nt

181.

.
;

788. T",inp (ipOll;
00010000 .,
789. int_dis .. (y : 0'1101;
790.outp
(ipOl,int_dil);
191. I
192.
793. eontilil_'S10 ()
794. , ••••••••••••••••••••••••••••••••• 111:11: • • • • • • • • • • • •111/
795. ,...
,,/
Configuu thR 82510
796. 1**
,,/
797. IU
798. / •••••• iII • • • • • • • • • • • • • • • • • • • •
** •••• ,

** ••••••••••••••

199.
800.

int .al;

80 I.
802.
803.
80<1.
80'S.
806.
807.
808.
B09.
810.
8tl.
812.
813.

set_bank (02);
val .. 0'100;
outp «bpi. + <1), va!);
ul ,,0178
Gutp «bpi. +1) ,vill) j

val =0100
outp «bpa +3),ul);
val =0.30;
outp «bp&+1),ul>;
val =01.80;
outp ((bpa.+6) , u l ) ;
set_bank (031 i

814. nl .. 0150;
outp (bpal.u,t);
'fit .. OldB;
set_dlab (031;
outp «bpa), n l ) ;
"fal sO.b4;
outp «bputJ,val);
reut_dhb (03);
val = O.OOi
outp «bpu3),vall;
val =0.02;
outp «(bpu6), va 1) ;
set_bank (00);
val =blkenbi
828. outp «bpa.l),n.ll;
829. val = 0107;
830. outp «bpu3),Ya.I);
831. set_dlab (DOli
832. H,I .. OlEO i
833. outp' (bpa,YIll;
834 . • al = 0101 i
835. outp «bput),v&l);
8U. reset_did (00);
831. I

81'S.
816.
817.
B18.
819.
820.
B11.
8U.
823.
824.
825.
826.
827.

** *** ** ** *** *** *... *. **•• *.* *•••• ***. *••• *•• /
*1

1*
,. 1110 - RI FIFO depth =4. auto ac.k.nonul
1* local loopback
I. RI10 - ASCII CCR,disable dpll.71U ••apl
,. window, absolute start bit 5&m.pl1ng
1* THO - manual 1lodt. 1 stop bits
1* no 9-bit char, no s/w parity
1* FHO - RI fifo Threshold. 3
1* T. fifo threshold .0
RIE - Enable n
interrupts
1*

*1
*1
*1
.,
*1
*1
*1

,. HOOEM CONFIGURATION
CLeF - 161. DRGA
I
/'
1* DDL - for 5as h.se

/'
/'
/'

1* D8H - for 5 illS bue
/'
,. BSCF - . , ' clk source, tiau .ode
/,
f. Tt11E - Tiau B interrupt enable
/'

BAN~

0 FOR CeNERAL CONF I C
1* GER enable \i.fIr. n, eCR

./
*1

*I
*f
'/
'/
'/
'/
'/

,/
'/
'/

'/
'/
'/
'/

1* block inltrruph
I. Left - disable parity, 8 bit char
/'

'/
,/

I. BRCA di.,isor .. OlEGH for 1100
I •••

'/
'/

*••• *.* •••••• 1* 1** •••••• ** ••••••••••••••• 1

231928-52

82510 XMODEM Implementation (Continued)

2-243

intJ

AP-401

MA IN PROGRAM

PAGE 16

It p. <

n510 XHODEH

838 . • • t_dllb (bl.nt)
839.

I t*t.ttltttt ••

840. 1**
841. 1**

841.'**
843
844.

*.*t •••••••••••••••••••• t • • • • • • • • • • • • ,
ttl

Set DLAB bit to ~l1ow aceess to
Diwilor Registers

**'
'*,

**1
Itt
/ ••••••••••••••••••••••••••••••••••••••••••••••••• ,

845.
84&. int blnt;

841. (
848.

int

849.
850.
851.
852.
853.

set_bank (00);
inYll • inp(bpa +3),
iny.l .iny,1 : 0.80;

innl;

,'I

Itt dlab in teRtI

Gutp ((bp&+3),inu1);
IIt_hnt (bank);

854. )
855.
856. use.t_dlab (bant)
851.
858 .

, ............................... "•• ,U •••••••••••••• ,
,,,
'*,
",
,**
'*,

Re.et DLAD bi t of LCR
1S9. 1**
1160.
861 , ................................................. *1

861.
863. int bank;
H4. (
U5. int
invil

IIU.
867.
868.
'U,
870.
87 I.

lit_bank (00);
iny.1 • inp(bpa +3);
in".1 • (inYll & h1f);
outp «bpu3),inYal);
let_bank (bank) i
)

dhb • 0 in LeRt:/

231928-53

82510 XMODEM Implementation (Continued)

2-244

intJ

AP-401

MAIN PROGRAM

PAGE 17

....

ftp.e

82510lMODEM

a71.

1 •• t • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • I111 • • • • • UI ••• ,

813.
874 .

··....t._.,
··.........

,....

875. , ..
876. J . . . .
877. / . . . .

au. / .. ..

• ••• */

82510 interrupt . I t .. i

rout in.

tI • • • • /

81510 Inhr rupt lourees:
Ta"

eea

aU. , .. ..

t •••• /

TI FIFO
Rl FIFO
TIMER B

/
/

110. / . . . .

811. ,....
aa%. /....
813. , • .,.,.
Ut.

sas.
81'.
117
888.

• _'tt */

Identifi .. and IU'fieu the 12510 inturupt
sourc. r.qu •• tlnq •• r'fiee.

c..

sour
cad_hi
It_b;
i:

ct lc;
f 1131 j
CJirnl;
rift ... ! i

,. Stores Te.p. VAlue of elK ./

la_char;
,. S..... Bant reqister in hap.
loeltion */

900.
901. Quip «bpl.+l),hZO)
902. Jource ~ aetlre. () j
,o3. int".e. _Iourc.;
904. switch (sourcI>
905.
'0' _
case t i.u

919.
91O .
UI.

91l.
U3.

,. Cet Vector Froa GIK 123 .,
,. SU'fice the Sourc • • ,

/ ••••••••••••••••••••••••••••••••••••• *•••••••••••••••••• ,
,....
• •••• /

909. ,....
910. /U..
911. ,....

914.
9\5.
916.
917.
9IB .

/
/

1 II_51 0 ()
(

898 .
an, airYl.1 =inp (bp&+l)j

912.
913.

.....

,..........................................................

819'. int
890. int
891./int
892. int
893. int
a94. int
895. int
au. tnt
a77. int

901.
908.

.,., ... /
.,., ... /
• .... (

TIMER SERVICE ROUTINE
dee.r ••• nt, h counter
dlet ••• nts tI: counter

.....
..... ,
.....
..... ,
/

/ ....
/ •••••••••••••••••••••••••••••••••••••••••••••••••••••••• /

/. Decre.ent Tran •• t t Counhr ./

It_b. inp (lIp •• 3);
if (h_ti.,_e.nt >c)

h_t

'.,_cnt

ah_U.,_cnt - 1 j

rI_Ua,_cnt aU_Ua._cnt - 1 j
cad_II '" Oa 21 ;
Qutp ( (bpl.+3),c:.d_b
Q1Ilp «bp&+7),hOll)j
bUlt;

/. rutart tiaer .,
/. aanual lct .,

231928-54

82510 XMODEM Implementation (Continued)

2-245

AP-401

HAIN PROCRAH

PACE 18

924,
925,
91'.
927.
928.
929 .
930.
931.
932.
933.
934.

82510 XHOOEH

ftp.e

use ll.
td
/ ••••••••••••••• ,I:1II • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ,U • • • , '
"...
.. ••.• ,
/
/'U** TRANSMITTER SERVICE ROUTINE

CIS.

....
....
....

/* •••

tranl.its Four c.haracters
and rn.ts tI_uq flalJ whln
who I, packet tr an,ait tid

/
/* •••
/

.....*'
*t,.

.....
t ••••

•••• *'
•••• t,,

, ••••••••••••••••••••••••••••••••••••••••••••••••••••••• , '

93:5 .
936.
937.
938.
939.
t40.
941.
942 .
943.
944.

(h_uq )0 )

/' II data to lend ' /

[

ptt)

if (tI_uq

/, rtqulI t

to sind Pac.ket '/

[

for

i<4 ; i++)

(i .0

[

h_c.hu • hdah £i + h_indll;
oulp (bp.,tl_c:hu)j

945.
tI_indi ._4;
la_byh_c.nt +_4;.

946.
947.
948.
949 .
950.

if (h_indl )e132)
h_req • OJ

/* if 132 c.har. sint thin */
1* reset TI [equllt */

951 .
952.
953.
954.

tIst
[

/* if ttl c.har. 'transBi,.ion
rtquI.ltd , thin transmit the

955.
956.
957.
95a.
959.
960.
961.
962.
963.
964.
965.
966.
967.
968.
969.
970.
971.

char. in c.U_to_tl *1
oulp (bpI. eer_lo_h);.

tI_req ",0

else
[

/. if no data to tranllllt *1
1* then disable h interrupts .,
.It_bank (00);
outp «bpul). (inp(bpa) 'hldb»;
set_bank (01);

outp «(bp&+1),Oa08);

break

,. issue •• nual acknowledoe

231928-55

82510 XMODEM Implementation (Continued)

2-246

infef
PACE 19

AP-401

MAIN PROCRAM

rtp.c

81510 IMODEM

911.

913.
914.
915.

++ccrc:nt;
fIgl clnp (bp. +51;

9" .

flQ' _tap (lIpu!);
cUe _tnp (bp');
if «fllJl , DaFF) •• 0.411

987.
9IB.

919.
990.

991.

twitch Celie)

/* nail RST r.gistar' to I.nic.
RIM interrupt ./

I· if no trrorl and cll. char .,
1* thin prot ... control char. *1
Ind und to h or n state ./

992.

cu. NAK:

993.
994.

ca .. ACI:
If (g.t_c.c:r_rq

995.
99' .

997.
971.

leth.1

infot. tran •• ttter that
cll. char. r.c..h.d ./

g.t_cc.r_rq .jnleth.;

999 .
1000.
1001.
1002.
1003.
1004.
1005.
1006 .
1007.

eer_lo_q.t selic;

break;

c ... SOH:

cu. EOT:
if (c.tle . . SOH)
I

1001.

II· if SOH diubh eeR int. '/

nt_bant (00);
Qulp «bp&+ll,(inp(bp&+ll& c.c.idb»j
IIt_bant (01);

1009.
IDlO.
1011.
1012 .
1013 .
1014.
1015 .
1016 .

if ([I_ltat ••• [:a_rdy)

,. if r,elher waiting for
SOH Ind flady to fCY

thIn infora r.e.her of
.- 'fI.1id etl. c.har. */

10 I?

e.tl_ud_fllJ _ac.t h.;

1011.
10 19.
1020.
1021.
1022 .
1023 .
1024.
1025.
IOU.
1027 .

rI_c.tl_chr -cUe;

brut.
I

I
oulp (;

231928-62

82510 XMODEM Implementation (Continued)

2-253

AP-401

PAGE 26

HAIN PROGRAH

13511. chtpkt

82510 rHODEH

IIp.e

(ptnaa)

1359. , ••••••••••••••••••••••••••• *••••••••••••••••• ,
1360. In
.. ariH .. the chathu. and packet
u,
1361. Itt
nu.ber of the rlc.thed pactet
.. ,
r,tarns
13n. / "
shtul Cood.
"/
1363.
1364.
1365.
1366 .
1367.
1368.
1369.
1370.
1371.
1372.
1373.

•

.'./

,,/

EOK
ract,t Ok
/"
EPKNUH
Error in pacht nu.ber
/"
"/
ECKKSUH - Error in Cheek s..
/"
"/
EPKCHPL
Erro in plctet e.o.pl,.,nt
/"
/"
"/
/ •••••••••••••••••••••••••••••••••••••••••• **.1
int ptnus;
(

at',

int i.
lnt ct .. ;
1374. int lua .. 0;
1315. char
capl,lIcapl.cpl:,c:hrc:t .. ;
1376.
1377.
137e.

cpt .ptna.;

1379.
1380.

if (cpt •• udataCO])
I
c.pl ., udah [0];
neapl .:udatl [11;
if (nc.pl .... "capl )
I
for (1=1: 1<130; i++)

1381.
1312 .
1383.
1384.
1385.
1316 .
1387.
1388
1389.
1390.
1391.
1392 .
1393.

/* packet nualler correct

11:,

1* picket ntlaber eo.plat *1

IU. . . lua +rldata [11;
ct... sua" 255;
chI ct... ct.;

pt_chtsa cehreka;
if (ehrek• • • radata [130])

ehlct.ua correet Itl

rlturn (tok);
Il.e
r_eturn (ee:ht •• );

1394 .

1395.
1396 .
1397.
1398.
1399 .
1400.
1401.
1401.
1403.
1404.
1405.
1406.
1407.

el.e
retarn (epte:ap);
_lie
I

if «ndah COl

cpt -1> "

(cpt

)1»

/* old paeket nu.blt
reeei'f.d *1

return ,tinp(bpl+1)
1* en&ble TIM AND Tl FIFO .,
t.hn» j
1437. set_bank (OI)i
,. return to bank on • • /
,,, nabh interrupts *1
1438. enbint4 OJ
1439 .
1440.
1441 .

1443.
1444.

144$.

/ * ••• t ••• t t ••••••• t t t •••••••• ot *ot*.t t tt.ot totot t tot ot tot I
,otot Display. the pan •• hs of the Recli",11
u/
, •• packet pusber, ilnll the npechd pUil.eters *'*/

1446. J t ot.ottot . t •• ot ••••• t ott ••• ot •• otott ot. t t t t •• ot tot.t.ot t . otot t J
1447.
1441. ++ bad_pH_cnt;
1447. pr.sCJ ("sending NAIt. fI);
1450. print( (fl .rror • '5u",pkst>;
14$1. 1I'_cUrs (13,11;
1451. printf ("e.ptd plc:t . . . . 3u",up_pkl_nu.lj
1453 . •,_curs: (14,.);
1454. printf (OOnd ptt I", "3u", udatatO]);
145$ . •,_curs ;
14&0. printf ("r.d chksua .. 11111", udataCl30]) j
14&1 . . . v_curl (1$,40);
14&Z. printf ("I.pd chtsus = 'UX",pk_chhml;
1463 . • • nd_ccr_req .act he j
1464. ccr_to_h = NAKi
1465. )

82510 XMODEM Implementation (Continued)

2-255

231928-64

inter
PACE 21

AP-401

"AIN PROCIA"

Itp.e

USIOI"OD£"

146'. / •••• *................................ I
1167. , .. PROCEDURE BUF_CPr
.. ,
14&1. ,..
eop' •• pactet to raa barhr
146'. , ••••••••••••••••••••••••••••••••••••• /
1470. bal_tip, (plett_idS
1471. int plckt_idi
I47Z. (
1473. Int
I;
1474. Int
In~1 .0;

tI,

I4n.
1476. j1ld& a (pad:t_id-U *Uli
1477. if

140.

/ •••••••••••••••••••••••••••••••••••••••••••••••••
141. /* . .
142. , ....
PRINTS MESSACE AT "ESSAGE LINE

,t ..

*•••• t. I
... u,
.... **/

143.
t
144. I....
145. ,....

..... ,

146. , . . . .

.*.*.,

.. ... ,

.. ... /
.. ... ,

147. / ....
141. / •••••••••••••••••••••••••••••••••••••••••••••••••••••••• ,
149.
150.
1St.
cia. () i '
151.
print( COl'll,", .'G);
153.
154.
ISS. CLLC ()

156. (
157. int •• cchr ••• ct;
158.
putch '.,cchr)j
15',
prinU '''C)tIO,;
\10. I
\6\.

161.
1'3.
164.
'''.

"V_CURS (.,J)
, ••••••••••••••••••••••••••••••••••••••••••
,....
, .... PROCEDUREHV_CURS

111: • • • • • • • • • • • • • ,

1". , ... .
167.
161.
169.
17 Q.
17\.
171 ..
173.
174.

, .. ..

,.Ut

location.

, ....

I""

int
Inl
(

t .... t . t •••• t

...... t . t ............... t

.. t ... t ........... t . t

•••• *,
.....
,
.*.*.,
.*.*./

...... *t ....... /

175. Int lIecht
\76.
\77.
171.
179 .

.0·... earlor to Ipteifild

• .... ,
..... ,

.,ei i

putch ( •• cchr);

cprintf (-t'Ui"uK" oK .,)

231928-70

82510 ~MODEM Implementation (Continued)

2-261

Inter

AP-401

PACE

ASH U

1. NAME

INTERRUPT INIT.

i h l . " . 82510 rHODEH

Hpih

3. DC ROUP CROUP
DATA
4. DATA
SECHENT IIORD PUlL IC 'DATA'
5.
ASSUHE OS, DCROUP
,. DATA
ENDS
7.
9.
10.
11 .
12.

PROC
SECHENT IYTE PUlL Ie 'PROC'
ASSUHE CS '_PROC

13. PUILIC
14. PUlL IC
15.
16.
17.

inlt_ih
i h51 0

PRoe
IP
Dr
AI
OS

init_ih
push
pUlh
. push
pUlh

18.
19.

...

20.

21.
U.

nx,

...

28.
29.
30.

OFFSET ih510

CS
OS

push

p.p

23.
24.
25.
U.
27.

lar

AL ,0eH

INT

21K

pop
pop
pop
pop

OS
AI
Dr
IP

31.

ret

hit_ill

DOS uctor setup call
Yet t or
DOS Sf' tt. cll1

AH,25H

.0'

COl'll

ENDP

33.

34. ih510
IS.

push

36.
37.

push
push
push
push
push
push

38.
39.
40

4t.
H.
43.

PRoe
IP
AX

ex
ox
SI
01
DS
ES
AI, DCROUP
DS, AI
hI_SiO
ES
OS
01

pash

pu.h

44.

.0'

45.

C& 11
pop
pop
pop
pop
pop
pop
pop
pop
pop
i r et

47 .

u.
49.
SO.
51 .

H.
53.
54.
55.
56.

fir

ox
ex
Ir
AI
IP

57. lh510

ENDP

. 58.

59. _PROC

ENDS

end

231928-71

82510 XMODEM Implementation (Continued)

2-262

APPLICATION
NOTE

AP-310

June 1987

High Performance
Driver for 82510

DAN GAVISH and TSVIKA KURTS
SYSTEM VALIDATION

Order Number: 292038-001
2-263

HIGH PERFORMANCE
DRIVER FOR 82510

CONTENTS

PAGE

1.0 OVERViEW ........................ 2·265
2.0 INTRODUCTION ............... ~ ... 2·265
2.1 CPU Load Consideration ............ 2·265
2.282510 Features Used In This
Implementation .................. 2·265
3.0 THE BURST ALGORITHM ......... 2·266
3.1 Background ........................ 2·266
3.2 Burst Algorithm Description ......... 2·266
4.0 SOFTWARE MODULE MAP ....... 2·267

5.0 HARDWARE VEHICLE
DESCRIPTION .................. 2·268

6.0 SOFTWARE MODULE
DESCRIPTIONS ................ 2·268

6.1 MAIN ............................... 2·268
6.2 The Burst Algorithm Modules ....... 2·269
6.3 Initializations ....................... 2·271
6.4 Interrupt Handler ................... 2·275
APPENDIX A-PL/M SOURCE FILE .. 2·280
APPENDIX 8-'-82510 BASED SBX
SERIAL CHANNEL .................. 2·293

2·264

inter

AP-310

1.0 OVERVIEW
The 82510 Asynchronous Serial Controller is a
CHMOS UART which provides high integration features to offioad the host CPU and to reduce the system
cost.
This Ap-Note presents a mechanism for reduction and
optimization of interrupt handling during asynchronous communication using the 82510. The mechanism
is valuable in applications where handling of interrupts
degrades system performance i.e., when high baud rate
is used, when multiple channels are handled or whenever real-time constraints exist. This implementation of
the mechanism is a software driver that transmits or
receives characters at 288000 bits per second.
The driver is based on the burst algorithm which uses
the 82510 features (FIFOs, Timers, Control Character
Recognition etc.) to reduce CPU overhead. CPU is significantly off-loaded for other tasks - about 75% of
the usual load is saved.
The driver can be easily modified to run in conjunction
with other 82510 features such as the MCS-51 9-bit
Protocol.
This document provides a full description of the driver.
The burst algorithm is presented in Section 3, the software module flow-charts and their descriptions are presented in Section 6, and the PL/M software listing is
given in Appendix A.

2.0 INTRODUCTION
2.1 CPU Load Consideration
The trend towards multi-tasking systems, combined
with higher baud rates and increasing the number of
channels per CPU, has led to the need for decreasing
the CPU bandwidth consumed by the async communications for each byte transfer. Whenever the CPU is
interrupted, a certain amount of CPU time is lost in
implementing the context switch. This overhead can be
as high as hundreds of microseconds per interrupt, depending on the specific operating system parameters.
Thus, in high baud-rate or multi-channel environments,
where the interrupt frequency is very high, a substantial
portion of the CPU time is taken up by this interrupt
overhead. Therefore, systems usually require minimization of the number of interrupt events. In the case of an
asynchronous communication channel, reduction of the

number of interrupts can be achieved by servicing (Le.,
transferring to/from the buffer) as many characters as
possible whenever the interrupt routine is activated.
This can be done by utilizing FIFOs to hold received or
transmitted characters, so that the CPU is interrupted
only after a certain number of characters· have been
received or transmitted. Using a receive FIFO may
cause a potential problem: Due to the random rate of
character arrival in asynchronous communications,
there is a chance that characters will be "trapped" in
the Rx FIFO for extended periods of time. In order to
avoid such situations, a Rx FIFO time-out mechanism
can be implemented using the 82510 timer. The timeout indicates that a certain amount of time has elapsed
since the last read operation was performed. It causes
the CPU to check the Rx FIFO and read any characters that are present. This process, however, introduces
the additional overhead ofthe timer interrupt. This ApNote describes the use of the burst algorithm to avoid
the timer interrupt overhead while maintaining the use
of the Rx FIFO.

2.2 82510 Features Used In This
Implementation
The following new 82510 features were used in this implementation:
2.2.1 FIFOs

The 82510 is equipped with 2 four-byte FIFOs, one for
reception and one for transmission. While characters
are being received, a Rx FIFO interrupt is generated,
when the Rx FIFO occupancy increases above a programmable threshold. While characters are being transmitted, a Tx FIFO interrupt is generated, when the Tx
FIFO occupancy drops below a program'mable threshold. The two thresholds are software programmable,
for maximum optimization to the system requirements.
2.2.2 TIMER

The 82510 is equipped with two on chip timers. Each
timer can be used as a baud rate generator or as a general purpose timer. When two independent baud rates
are required for transmit and receive, the two timers
can be used to generate both baud rates internally. Otherwise, one timer can be used for external purposes.
The timer is loaded with its initial value by a software
command and it counts down using system clock p~ls
es. When it expires, a maskable interrupt is generated.

2-265

IrJreI

AP·310

3.0 THE BURST ALGORITHM

2.2.3 CONTROL CHARACTER RECOGNITION
Depending on the application, the software usually
checks the received characters to determine whether
certain control characters have been received, in which
case special processing is performed. This loads the
CPU, as every received character should be compared
to a list of control characters. With the 82510, the CPU
is offioaded from this overhead. Every received character is checked by the 82510, and compared to either a
standard set of control characters (ASCII or EBCDIC)
or to special user defined control characters. The software does not need to check the received characters,
and a special interrupt is provided when a received control character is detected by the 82510. The specific
operation mode (standard set, user defined, etc.) is programmable.

3.1 Background
The 82510 FIFOs are used to reduce the CPU interrupt
load. When a burst of characters is transmitted or
received, the CPU is interrupted only once per transmission or reception of up to four characters. FIFO
thresholds are programmable; thus, when high system
interrupt latency is expected, an optimal threshold may
be selected for the desired trade-off between the CPU
load, and the acceptable system interrupt latency. The
required Rx FIFO threshold is also a function of the
receive characier rate. When the rate is 'high, a deep
FIFO is required. When the rate is very low (e.g., hundreds of milliseconds between characters), a low threshold is needed, to reduce the maximum character service
latency (a character is available to the application program only after it is stored in the receive buffer).

2.2.4 INTERRUPT CONTROLLING MECHANISM
The twenty possible interrupt sources of the 82510 are
grouped into six blocks: Timer, Tx machine, Rx machine, Rx, FIFO, Tx FIFO, or Modem. Interrupt
source blocks are prioritized. The interrupt management is performed by the 82510 hardware. The CPU is
interrupted by a single 82510 interrupt signal. The interrupt handler is reported on the highest priority pending interrupt block (GIR) and on all the pending interrupt blocks (GSR), as well as on the specific interrupt
source. Interrupts are maskable at the block level and
source level. Interrupts can be automatically acknowledged (become not pending) when serviced by the soft~
ware, or manually' acknowledged by an explicit command.

The software. mechanism described here tunes the Ri
FIFO threshold dynamically when the incoming character rate is variable. The algorithm uses one of the
82510 on-chip timers for time measurement, in.order to
automatically adapt the threshold to the character reception rate. This is done' without loading the CPU
with the overhead of serving excessive interruptsgenerated by the timer mechanism itself.

3.2 Burst Algorithm Description
The 82510 timer is initialized to the time-out value with
every Rx FIFO interrupt. The time-out value is the
maximum acceptable time between a character's reception and its storage in the receive buffer, but not less
than five character-times. Upon reception of the next
character, the timer status is examined to determine,
whether the character rate is high (the timer has not yet
expired) or low (the timer has expired).

2-266

AP-310

2nd character received, at LOW rate

2nd character received, at HIGH rate

receive characters at HIGH rate

292038-1

Figure 1. Burst Algorithm State Diagram

The algorithm is best described as a finite state machine
that can be in one of three modes: HUNTING mode,
SINGLE mode, or BURST mode. In HUNTING
mode, after the first character received interrupts the
CPU, the mode switches to SINGLE. On receiving a
character in SINGLE mode (that is the second character) the timer is examined; if the character rate is very
low, the mode is switched back to HUNTING. Otherwise, the rate is high enough to switch to BURST
mode. In BURST mode, the Rx FIFO threshold is
maximal. The machine remains in BURST mode as
long as a burst of characters is being received. When
the rate of character reception becomes low, the timer
eventually expires generating a timer interrupt which
switches the mode back to HUNTING.

4.0 SOFTWARE MODULE MAP
The driver contains the following software modules:
• MAIN
• BURST ALGORITHM
- Burst Algorithm Initialization (*)
- Rx FIFO Step (*)
-

HUNTING mode
SINGLE mode
BURST mode
Timer Step (*)

• INITIALIZATIONS
- Wait for Modem Status

Note that while a burst of characters is being received,
the CPU is interrupted only once per four received
characters. If the characters are received at a very low
rate, an interrupt occurs for each received character.
The CPU is interrupted by the timer only once, when
the burst terminates. See Figure 1 for a state diagram.

• INTERRUPT HANDLER
- Rx FIFO Interrupt Service Routine
- Tx FIFO Interrupt Service Routine
- Status Interrupt Service Routine
Timer Interrupt Service Routine
- Modem Interrupt Service Routine

For more details about the burst algorithm see paragraph 6.2.

(*) The burst algorithm modules are called by the ini-

tialization module and by the interrupt handler modules.

2-267

AP·310

INITIALIZATIONS

292038-2

Figure 2. Modules Block Diagram

5.0 HARDWARE VEHICLE
DESCRIPTION

6.0 SOFTWARE MODULE
DESCRIPTIONS

The driver was tested at 288000 baud, on an 80186
based system, with an 8 MHz local bus running with 2
wait-states, and an 18.432 MHz 82510 clock. Two stations were involved: one transmitter station and one
receiver station. Each station consisted of an
iSBC186/51 with a 82510 based SBX board connected
to it. See Appendix B for description of the SBX board.
This driver is, nonetheless, suitable for running in a
large number of system environments.

6.1 MAIN
The MAIN module is a simple example of an application program that uses the driver.
The communication is done between two stations: One
station is the transmitter and the other one is the receiver. After interrupts are enabled, the program waits
for the Finish_Tx flag or the Finish_Rx flag (for the
transmitter or receiver station, respectively) to be set.
In the transmitter station, the driver is preloaded with
the transmit data. In the receiver station, the received
data is displayed after data reception is complete.

2-268

AP-310

292038-3

Figure 3. MAIN

6.2 The Burst Algorithm Modules
6.2.1 INITIALIZE THE BURST ALGORITHM

This module is called by the initialization module.
The global variable Burst_algo is used to indicate the
current burst algorithm mode.
The burst algorithm is most useful at a baud rate of
9600 or higher. At lower baud rates, where the Rx in·
terrupt rate is very low, the burst algorithm is degener·
ated (Low_baud is assigned to Burst_algo). At a
baud rate of 9600 or more, the burst algorithm mecha·
nism is initialized and starts by disabling the timer interrupt.
The initial state of the burst algorithm is HUNTING
mode. In this mode, it is looking for (hunting) the first
character. The Rx FIFO threshold is zero, thus the first
character received interrupts CPU. This interrupt starts
the burst algorithm mechanism.

2-269

BURST_algo = Low Baud

292038-4

Figure 4. Initialize The Burst Algorithm

inter

AP-310

6.2.2 BURST ALGORITHM MECHANISM

6.2.2.2 SINGLE Mode

Modules HUNTING, SINGLE, BURST are called by
Rx FIFO interrupt service routine. Module
BURST&TIMER is called by timer interrupt service
routine.

When the second character is received, the burst algorithm is in SINGLE mode. Timer status is read
(TMST). If the status indicates that the timer has expired, the receive character rate is low and there is no
need to increase the Rx FIFO threshold. The burst algorithm returns to its first state, i.e., HUNTING mode .
However, if the timer has not expired, the receive character rate is high, and the Rx FIFO threshold is set to
the maximal allowable value. The timer is restarted and
the timer interrupt is enabled so that, if it expires before
the Rx FIFO exceeds the threshold, a timer interrupt
will occur.

. 6.2.2.1 HUNTING Mode
Hunting for the first character received is the first step
in the burst algorithm. After the first character is detected, received and handled, it must be determined if
reception will be at high or low rate. This is done by
starting the timer. HUNTING mode ends by assigning
the second step, i.e., SINGLE mode, to Burst_algo.

SINGLE mode is ended by assigning the third step,
BURST mode, to BURST_algo.

SINGLE mode

BURSLalgo

BURST mode

=HUNTING

292036-5

Figure 5. The Burst Algorithm

2c270

inter

AP-310

6.2.2.3 BURST Mode
The algorithm enters BURST mode as soon as the receive character rate is evaluated as high, i.e., when two
successive characters are received without a timer expiration. The FIFO is now working at full threshold and
the timer is used as a timeout watch dog. BURST mode
is the most time-critical path of the algorithm. Therefore, it consumes a minimum amount of real time.
The timer is restarted, in order to restart a new timeout
measurement. The timer status is read to trigger automatic reset of the previous status; this is done to avoid
the timer interrupt if the timer has expired during the
Rx FIFO interrupt service routine execution.

avoid an overrun error). The module was designed to
minimize the CPU overhead inherent in the burst algorithm itself.
BURST mode is assigned the fastest path because it is
the most real time sensitive mode.
SINGLE mode has a slightly longer path. However,
under a high reception rate, the algorithm passes SINGLE mode once only and then stays in BURST mode
until the end of the burst. Under a low reception rate
the algorithm passes SINGLE mode many times, but,
since the period between two successive Rx interrupts is
long, this hardly affects system performance.

6_3 Initializations

6.2.2.4 Timer Interrupt and Bust Algorithm
If the character reception rate becomes low, then the
time between two successive Rx FIFO interrupts increases. Hence, a reduction in the reception rate causes
the timeout to expire, and a timer interrupt occurs.
This drives the algorithm back to HUNTING mode.
The timer interrupt is disabled and the Rx FIFO
threshold is configured to zero, to issue an Rx interrupt
on the first hunted character.

This module initializes the driver. It is called at program start-up.
The 82510 is configured for the specific operation mode
by the CONFIG_82510 submodule: A Software Reset
command is issued, and then the character configuration is selected. In the receiver station ACRO and
ACRI Registers are loaded with the End-Of-File
ASCII character, so that the Control Character Recognition feature of the 82510 can be used to detect the
specific file terminator. In the transmitter station, the
ASCII characters XOFF and XON are loaded to
ACRO and ACR1, respectively, to detect transmit-off/
on requests automatically. The use of the control character recognition feature of the 82510 reduces system
overhead, as the software does not need to check every
received character. A special interrupt is received when
the 82510 hardware detects a received control character.
Interrupt sources are enabled (note that a Tx interrupt
will occur immediately). BRGA is loaded to generate
the required baud rate (288000 baud in this specific
implementation). Rx FIFO .depth is set to 4. The Tx
and Rx FIFO thresholds are initialized to O. BRGB is
selected to function as a timer, and is loaded with the
timeout value (7 ms at 18.432 MHz, in this implementation). The RxC and TxC sources are selected to be
BRGA.

292038-6

Figure 6. Timer Interrupt and BURST Algorithm
Table 1. BURST Algorithm Modes
Mode

FIFO
Threshold

Timer

Timer-Interrupt

Hunting

Idle

Disabled

Single

Started

Disabled

Burst

Max.

Restarted

Enabled

The burst algorithm parameters are initialized by
INIT_BURST. WAIT_FOR_MODEM_STATUS
is called and implements a wait until the modem handshake DSR signal is set. If WAIT_FOR_MODEM_
STATUS returns with a timeout error, the modem error is processed. If no error has occurred, the following
parameters are initialized: Finish_Rx and Finish_Tx
flags, receive and transmit buffer pointers, and the receiver flag. All status registers are cleared by issuing a
STATUS CLEAR command to the ICM register.

6.2.3 FLOWCHART DESCRIPTION
The Rx FIFO interrupt handler executes the burst algorithm immediately after the Rx FIFO is emptied (to
2-271

intJ

Ap·310

292038-7

Figure 7. Initializations

2-272

AP-310

=EOF char
=EOF char
GER =Enbl Intr

ACRO
ACR1

Rx, Stat, Modem

=X_Off char
=X_On char
GER =Enbl Intr

ACRO
ACR 1

Rx, Stot, Modem

292038-8

Figure 8. 82510 Configurations

2-273

inter

AP·310

This module waits, with a timeout, for the DSR modem
handshake signal to be set. DSR should be active before

any communication starts (it indicates that the modem
is active). The returned ModeIIL-Handshake flag indicates normal return (true) or timeout error return
(false).

292038-9

Figure 9. WaiLFor_Modem_Status

2-274

AP-310

6.4 Interrupt Handler

6.4.1 INTERRUPT HANDLER STRUCTURE

The interrupt handler services the 82510 interrupt
sources. Since this is a time-critical path, the code is
optimized to minimize real time consumption.

The interrupt handler identifies the highest priority
pending 82510 interrupt, by reading GIR. The interrupt handler was designed so that shorter paths are
assigned to more real time sensitive interrupt sources.
Rx FIFO interrupt is the most sensitive, Tx FIFO is
the second most sensitive, and so on.

The interrupt handler services only one interrupt
source at a time. This prevents CPU resource starvation from other interrupt driven devices. Interrupts are
enabled at the beginning of the interrupt handler, so
that higher priority interrupt sources are not disabled
by the 82510 interrupt handler.

The programmable interrupt controller (8259A) is assumed to be configured to "edge triggering mode" and
"non-automatic end of the interrupt" mode.

292038-10

Figure 10. Interrupt Handler

2-275

AP-310

6.4.2 Rx FIFO INTERRUPT SERVICE ROUTINE

The Rx FIFO interrupt service routine first empties the
Rx FIFO. The receive data register (RXD) is read, as
many times as indicated by the FIFO occupancy register (FLR), and the characters are stored in Rx_Buf.

graph 6.2.2). Before leaving the Rx FIFO interrupt
service routine, the FIFO occupancy register is rechecked, to empty the Rx FIFO of characters that may
have been received during the Rx FIFO interrupt service routine itself. This can happen if the Rx FIFO interrupt service routine has been interrupted by a higher
priority interrupt.

After emptying the Rx FIFO, the RxFIFO interrupt
service routine executes the burst algorithm (see para-

292038-11

Figure 11. Rx FIFO Interrupt Service Routine

2-276

inter

AP-310

6.4.3 Tx FIFO INTERRUPT SERVICE ROUTINE

6.4.4 STATUS INTERRUPT SERVICE ROUTINE

The Tx FIFO interrupt service routine fills the Tx
FIFO with transmit characters while checking for the
End-Of-File terminator. According to the FIFO occupancy register (FLR), the Tx FIFO is loaded (by writing to TXD) until it is full or until the End-Of-File
character is detected. The transmitted characters are
taken from TlL-Buf. If an End-Of-File character is
identified, then the transmission is immediately ended
by disabling all 82510 interrupts and setting the Finish_Tx flag.

The status interrupt service routine has four objectives:
- To empty the Rx FIFO.
- To stop reception if an End-Of-File character is
identified by the control character recognition
mechanism (in the receiver station).
- To disable or enable the Tx interrupt ifaXOFF or
XON character, respectively, is identified by the
control character recognition mechanism (in the
transmitter station).
To handle parity, framing, or overrun errors (in the
receiver station).

t=t+ 1

292038-12

Figure 12. Tx FIFO Intr Service Routine

2-277

inter

AP-310

First the Rx FIFO is emptied. In the receiver station,
the RST register is checked to determine whether an
End-Of-File terminator has been identified by the
82510, in which case reception is stopped immediately
by. disabling all· interrupt sources and setting the
FinisLRx flag. In the transmitter station, the received
characters are checked to identify the received control
character. If XOFF is identified, Tx interrupt is disabled. If XON is identified, Tx interrupt is enabled.
Note that the software does not need to check for any

control character during normal reception; the control
characters are identified by the 82510 device.
RST is checked for parity, framing or overrun errors. If
one of these errors has occurred, then the error handling routine is executed.
If status interrupt occurs while Burst_algo is assigned
to BURST mode, the timer is restarted.
Note that status interrupt is enabled at both stations.

Receive

station

Transmit
station

292038-13

Figure 13. Status Intr. Service Routine

2-278

inter

AP-310

6.4.5 TIMER INTERRUPT SERVICE ROUTINE

6.4.6 MODEM INTERRUPT SERVICE ROUTINE

A timer interrupt occurs when the receive character
rate becomes low. The timer interrupt service routine
first empties the Rx FIFO and then switches the burst
algorithm to HUNTING mode.

Modem interrupt occurs if one of the modem lines has
dropped during transmission or reception. The modem
interrupt service routine reads the MSR register to acknowledge the modem interrupt. The modem error
routine is then executed.

292038-14

Figure 14. TIMER Intr Service Routine

292038-15

Figure 15. MODEM Intr Service Routine

2-279

AP-310

APPENDIX A
PL/M SOURCE FILE

/*************************************************************************

**
**
*

8 2 S 1 0 - HIGH

PER FOR MAN C E

Dr i v e r

This driver is optimized for Real Time Systems. It supports
high system performance. It is based on the "BURST algorithm"

**
*

*************************************************************************/

HIGHPERFORMANCE: DO

/*************************************************************************

LITERALS

*************************************************************************/
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE

LIT
TRUE
FALSE
BAUD 9600
BAUD-19200
BAUD-288000
DLAB-0
DLAB::)
CR
LF
X Off
X-on
End Of File
BASE_sIo
NASO
WORK1
GEN2
MODM3
TXD
RXD
BAL
BAH
GER
GIR
BANK
LCR
MCR
LSR
MSR
ACRO
RXF
TXF
TMST
THCR
FLR
RST
RCM
TCM
GSR
ICM
FMD
THD

LITERALLY 'LITERALLY' ,1
LIT 'OFFH'
LIT 'OOH'
LIT '003CH'
1/*
LIT 'OOlEH'
LIT '0002H'
LIT '01111111B'
1/*
LIT '10000000B'
1/*
LIT 'ODH'
1/*
LIT 'OAH'
LIT '13H'
LIT '11H'
LIT 'lAH'
1
LIT '080H'
1/*
LIT 'OOOOOOOOB'
LIT '00100000B'
LIT '01000000B'
LIT '01100000B'
LIT 'BASE S10 + 0' 1/*
LIT 'BASE-S10 + 0'
LIT 'BASE-S10 + 0'
LIT 'BASE-S10 + 2'
LIT 'BASE-S10 + 2'
LIT 'BASE-S10 + 4 '
LIT 'BASE-S10 + 4 '
LIT 'BASE-S10 + 6'
LIT 'BASE-S10 + 8'
LIT 'BASE-S10 +10'
LIT 'BASE-S10 +12'
LIT 'BASE-S10 +14' ,
LIT 'BASE-S10 + 2 ' 1/*
LIT 'BASE-S1O + 2'
LIT 'BASE-S10 + 6'
LIT 'BASE-S10 + 6'
LIT 'BASE-S10 + 8'
LIT 'BASE-S10 +10'
LIT 'BASE-S10 +10'
LIT 'BASE-S10 +12'
LIT 'BASE-S10 +14'
LIT 'BASE-S10 +14'
LIT 'BASE-S10 + 2 ' 1/*
LIT 'BASE:::S10 + 6' l'

2-280

Character'configurations

Reset DLAB
Set
DLAB
Control characters

*/
*/

8 2 S 1 0

registers

BANK 0 - NAS

BANK 1 - WORK

BANK 2 - GENERAL CONFIGURE */
292038-16

AP-310

DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
'DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE

IMD
LIT 'BASE 510 + 8'
ACR1
LIT 'BASE-510 +10'
RIE
LIT 'BASE-510 +12'
RMD
LIT 'BASE-510 +14'
CLCF
LIT 'BASE-510 + 0'
BBL
LIT 'BASE-510 + 0'
BACF
LIT 'BASE-510 + 2'
BBH
LIT 'BASE-510 + 2'
BBCF
LIT 'BASE-510 + 6'
PI1D
LIT 'BASE-510 + 8'
I1IE
LIT 'BASE-510 +10'
TI1IE
LIT 'BASE-510 +12'
OUT2 I1CR
LIT 'OOOO1000B'
DTR MCR
LIT 'OOOOOOOlB'
DSR-I1SR
LIT 'OO100000B'
CLRSTAT ICM
LIT 'OOOOO100B'
INTR 510
LIT '21H'
PORT-80130M
LIT 'OE2H'
EN 80130
LIT 'OFDH'
PORT EOI
LIT 'OEOH'
COMM-EOI
LIT '61H'
ENRTX GER
LIT 'OOOOllllB'
ENTX GER
LIT 'OOOOOO10B'
ENTXSTAT GER LIT 'OOOOll10B'
ENRX GERLIT 'OOOOl101B'
ENTIMRX GER
LIT 'OO101101B'
DISTX GER
LIT 'OOOO1101B'
DISRX-GER
LIT 'OOOOOO10B'
DISRTX GER
LIT 'OOOOOOOOB'
TXTHRESHO FI1D LIT 'OOOOOOOOB'
RXTHRESHO-FMD LIT 'OOOOOOOOB'
RXTHRESH3-FMD LIT 'OOl10000B'
MASK RXOCC
LIT 'Ol110000B'
MASK-TXOCC
LIT 'OOOOOlllB'
MASK-ACRSTAT LIT '01000000B'
CHRLEN 8
LIT 'OOOOOO11B'
STPBIT-1
LIT 'OOOOOOOOB'
PARITY-NON
LIT 'OOOOOOOOB'
SWRES CMND
LIT 'OOO10000B'
ERRCHR RST
LIT 'OOOOl110B'
ACRSTAT RIE
LIT " 01000000B'
ACRSTAT-RST
LIT '01000000B'
NONI GIR
LIT 'OO100001B'
MODMI GIR
LIT 'OO100000B'
TXI-GIR
LIT 'OO100010B'
RXI-GIR
LIT 'OO100100B'
STATI-GIR
LIT 'OO100110B'
TIMI-GIR
LIT 'OO101010B'
AUTOACK IMD
LIT 'OOOO1000B'
TIMOD BBCF
LIT 'OOOOOOOOB'
TIMBI-TMIE
LIT 'OOOOOO10B'
FIFO IMD
LIT 'OOOOOOOOB'
STARTIMB TMCR LIT 'OO100010B'
STARTIMB-TMST LIT 'OOOOOO10B'
RTXCLK BRGA CLCF LIT '01010000B'
LOW BAUD
LIT 'OOH'
HUNTING MODE LIT 'OlR'
SINGLE-MODE LIT '02R'
BURST-MODE LIT '03H'
TIME EXP
LIT 'OFFFFH'
LIT 'OOFFFH'
WAIT=TlME

;
;
;
;

;/* BANK 3 - MODEM
;/* DLAB=l
;

;/* DLAB=l
;
;
;
;

;/* Specific register bits
;
;
;

*/
*/
*/

;
;
;
;

;/* End Of Interrupt command
;/* Enable Interrupt bits
;
;
;
;
;

;/* Disable Interrupt bits
;

;/* FIFO threshold
;

*/
*/

;

;/" Mask on occupancy bits
,
;/* Mask on ACR status bits
;/* Async parameters
;
;
;
;
;
;

;/* Interrupt vector
;
;
;
;
;
;

;/* Timer
;

*/
"~I

;
;

;

,
;/* BURST algorithm
;

;
;

;/* timeout=7mS (at 18.4 Mhz)
;/* WAIT_FOR_MODEM_STATUS

*/
*/
292038-17

2-281

inter

AP-310

1***************************************************** ********************

VARIABLES

****************************************************** *******************1

DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE

TX PTR POINTER PUBLIC
TX-BUF BASED TX PTR (3000) BYTE ;
IX-TX .
WORD PUBLIC ;
RX-BUF(3000) BYTE PUBLIC;
IX-RX
WORD PUBLIC
INTR VEC
BYTE PUBLIC
FIN TX
BYTE PUBLIC
FIN-RX
BYTE PUBLIC
RX CHR
BYTE PUBLIC
TX-CHR
BYTE PUBLIC
TX-OCC
BYTE PUBLIC
RX-OCC
BYTE PUBLIC
STAT
BYTE PUBLIC
BAUD
WORD PUBLIC
TEMP
BYTE PUBLIC
FIN
BYTE PUBLIC
SELECTION
BYTE PUBLIC
RECEIVER
BYTE PUBLIC
BURST ALGO BYTE PUBLIC
MODEM-HANDSHAKE BYTE PUBLIC
COUNTER
WORD PUBLIC
RX_ERROR
BYTE PUBLIC ;

/* Transmit buffer

/* Receive

buffer

1* Finish Reception

/* Finish Transmission flag
flag

*/
*/

/* Receive station
/* BURST algorithm

*/
*/

/* Error occurred during
/* reception

/*----------------~------------------------------------------------------*/
/* I/O console utilities
$INCLUDE (:F1:TIOHP.PEX)

/* Setup and H/W configurations
$INCLUDE (:F1:HPUTIL.PEX)

DECLARE MAIN LABEL PUBLIC ;
/*************************************************************************

Procedure

INITIALIZATIONS

*************************************************************************

input:
output:
function:

called by:
calling:

*
**

**
*

*
**

none
none
driver initialization: parameters, 82510
configuration, modem status check.
Main
CONFIG_82510, INITIALIZE_BURST; WAIT_FOR_MODEM

Init .the Interrupt mechanism by enable Interrupt in GER register
At the Receive station: Enable Rx FIFO, Status and Modem Interrupts
Disable Timer Interrupt
At the Transmit station: Enable Tx FIFO, Status and Modem Interrupts
flowchart:

figure 7

description:

paragraph 6.3

*
*
*
*
*
*
**
*
*
*
**

*************************************************************************/

INITIALIZATIONS: PROCEDURE PUBLIC;
DISABLE ;
CALL SET$INTERRUPT(INTR 510,INTR HANDLER)
/* Install THE INTR HANDLER
TX CHR=OO
RX=-CHR=OO

/* Clear TX CHR and RX CHR

*/
*/
292038-18

2-282

AP-310

CALL TEXT ;

/* TX PTR is a pointer to the transmitted*/
/* data
*/
/* The index buffer are assigned to -1
*/

IX TX= OFFFFH
IX-RX= OFFFFH
FIN TX=FALSE
FIN-RX=FALSE ;
RX BUF(O)=O
RX:::ERROR=FALSE

/* Init Finish Transmit and receive flags*/

/* Reset the flag

BAUD=BAUD_288 000

/* The Async communication Baud rate is
/* the 82510-full scale 288000

*/
*/

CALL CONFIG_82510

/* Configured the 82510:
*/
/* S/W reset, character length, parity, */
/* stop bit, baud rate and fifo threshol */

1***************************************************** ********************
*
INITIALIZE BURST
*
***********w*************************************************************

*
*
*

input:
output:
function:
* called by:
.. calling:

flowchart:

none
Burst Algo
start-Burst algorithm in Hunting mode
INITIALIZATIONS
none
figure

description:

paragraph 6.2.1

*
*

*
*
*
**

*************************************************************************/

IF BAUD<=BAUD_9600

ELSE

THEN BURST ALGO=HUNTING MODE ;
/* HUNTING mode:
/* Rx FIFO threshold is a
/* Timer interrupt is disable
BURST_ALGO=LOW_BAUD

*/
*/
*/

CALL WAIT FOR MODEM STATUS ;

TEMP
TEMP
TEMP
TEMP

/* Wait for Modem handshake line "DSR"
/* if ACTIVE set
MODEM_HANDSHAKE

*/
*/

INPUT (RXD)
INPUT (RXD)
INPUT (RXD)
INPUT (RST)

END INITIALIZATIONS ;

1***************************************************** ********************
* Procedure CONFIG 82510
*

•• *.* ••••••••• ** ••• *** ••••••••• ** •• * ••• * ••• ** •••• * ••• ********************
* input:
none
*
* output:
none
*

*
*

*
*
**

function:

called by:
calling:

configure the 82510 to a specific operation
mode
INITIALIZATIONS
none

flowchart:

figure 8

description:

paragraph 6.3

*
**

****************************************************** *******************1

CONFIG_82510: PROCEDURE PUBLIC

/* Perform Software reset
OUTPUT (BANK) = WORK1;
OUTPUT (ICM) = SWRES_CMND;

/* Move to work bank
/* S/W reset command

*/
*/
*/
292038-19

2·283

AP-310

1* BANK ZERO -

NAS

(The default BANK)

1* Configured the character by writing to LCR:
1* 1 stop bit, 8 bit lengh, non parity

*1
*1

IF RECEIVER THEN OUTPUT(ACRO)=End Of File ;
1* At the Receive station EOF is
1* recognized to terminate reception
ELSE OUTPUT(ACRO)= X_OFF
1* At the Transmit station "X Off" is
1* recognized to stop transmission
1* temporary

*1
*1
*1
*1
*1

1* Enable 82510 Interrupt by set GER,
1* done at the end of INITIALIZATIONS

*1
*1

1* Init the 82510 Interrupt mechanism
DISABLE ;
IF RECEIVER THEN OUTPUT(GER)=ENRX GER ;
1* a~ the Receive station
ELSE OUTPUT(GER)=ENTXSTAT_GER
1* and the Transmit station

OUTPUT(LCR)=(STPBIT 1 + CHRLEN 8 + PARITY NON)
OUTPUT(MCR)=(DTR_MCR OR OUT2_~CR) ;
1* Required only in IBM PC environment: *1
1* set OUT2 signal to control an external*1
1* 3-state buffer that drives the 82510 *1
1* interrupt signal
*1

/* Configured baud rate to 288000
1* by writing to BRG A (BAL and BAH)
OUTPUT (LCR) =INPUT (LCR) OR DLAB 1; I*set DLAB to allow access to BRG
OUTPUT(BAL)=LOW (BAUD 288000) ;
OUTPUT (BAH) =HIGH (BAUD-288000) ;
OUTPUT(LCR)=INPUT(LCR) AND DLAB_O; 1* reset DLAB

*1
*/

1* BANK TWO - General configuration

*1
*1

OUTPUT(IMD)=(AUTOACKIMD OR FIFO IMD) ;
7* Automatic interrupt acknowledge,
1* Rxfifo depth is four bytes

*1
*1

OUTPUT (FMD)= (TXTHRESHO_FMD OR RXTHRESHO FMD) ;
1* Rxfifo threshold is temporally zero
1* for HUNTING mode (BURST algorithm)
1* Txfifo threshold is zero for max
1* interrupt latency

OUTPUT(BANK)=GEN2 ;

IF RECEIVER THEN OUTPUT(ACRl)=End Of File;
1* At the Receive station EOF is
1* recognized, the same as ACRO
ELSE OUTPUT(ACR1)=X_ON
1* At the Transmit station "X On" is
1* recognized to continue transmission
OUTPUT (RIE)

*1
*1
*1
*1

(ACRSTAT_RIE OR INPUT(RIE» ;
1* Enable interrupt on programmed control*1
1* character received (ACRO/ACR1)
*1

1* BANK THREE - MODEM configuration

OUTPUT(BANK)=MODM3 ;

OUTPUT(BBCF)=(TIMOD BBCF)
1*
OUTPUT (BANK) = NASO;
1*
OUTPUT (LCR) =INPUT (LCR) OR DLAB_1 ;
OUTPUT (BANK) = MODM3;
1*
OUTPUT (BBL) = LOW (TIME_EXP);
1*

BRG B configured to TIMER mode
*/
Move to nas bank to set DLAB
*1
1* Set DLAB to allow access to BRG
*/
MODEM bank
*1
Set max timeout (7rns if l8Mhz crystal) *1
292038-20

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AP-310

OUTPUT (BBH) = HIGH(TlME_EXP);
1*
OUTPUT (BANK) = NASO;
1*
OUTPUT (LCR) =INPUT(LCR) AND DLAB 0
OUTPUT (BANK) = MODM3;
7*
OUTPUT(CLCF)=RTXCLK BRGA CLCF
1*

to issue interrupt when time has
expired. Move to NAS bank again
; 1* Reset DLAB
switch to BANK THREE - MODEM
The receive and transmit clock source
is BRG A

*1
*1
*1
*1
*1
*1

OUTPUT (TMIE) =TIMBI_TMIE

1*
1*

Enable Timer block interrupt
(stil disabled in Timer bit in GER)

*1
*1

BANK ONE - general WORK
OUTPUT(BANK)=WORKl ;
OUTPUT(ICM)=CLRSTAT_ICM

Remain in

- The RUNTIME

1*
1*

b~nk

Issues a command to clear all
status registers

W 0 R K - THE runtime

bank

*1
*1
*1
*1

END CONFIG_82510 ;
1***************************************************** ********************
* Procedure WAIT FOR MODEM STATUS
*
*************************************************************************
* input:
none
*
Mocem Handshake
*
* output:
* function:
waits-with a timeout for DSR active,
*
*
returns status flag
*
*
* called by: INITIALIZATIONS
* calling:
none
*

* flowchart:

figure 9

description:

paragraph 6.3.1

****************************************************** *******************1

WAIT_FOR_MODEM_STATUS: PROCEDURE PUBLIC ;
MODEM HANDSHAKE = FALSE
COUNTER = WAIT_TIME ;
DO WHILE (NOT MODEN HANDSHAKE) AND «COUNTER:=COUNTER-l) > 0 )
IF (INPUT (MSR) AND DSR MSR) <> 0
THEN MODEM_HANDSHAKE
TRUE
-

END

/*************************************************************************

Procedure

INTERRUPT HANDLER

*************************************************************************

* input:
* output:

*
*
*

function:
called by:
calling:

*
** flowchart:

Tx Buffer
Rx Buffer, Finish_TX, Finish_Rx
service all 82510 interrupt sources:
Rx Fifo, Tx Fifo, Status, Timer, Modem
82510 hardware interrupt
Rx Fifo Intr, Tx Fifo Intr, status_Intr,
Timer_Intr, Modem_Inti
figure 10

description:

paragraph 6.4, 6.4.1

*
*
*
*
*

*
**

*************************************************************************/

INTR HANDLER: PROCEDURE INTERRUPT INTR_510 REENTRANT PUBLIC
ENABLE

1*
1*

Enable Interrupts of
HIGHIER priority devices

*1
*1

INTR_VEC=INPUT(GIR) ;

1*
1*

Get the 82510-highest priority
pending interrupt

*/
*/
292038-21

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AP-310

/*******~********************************************* ********************

*
Rx FIFO INTR
*
*************************************************************************
* input:
none
*
* output:
Rx Buffer, Burst Algo
*
service Rx Fifo Interrupt
*
* function:
*
receive characters; store in receive buffer
*
* called by: INTERRUPT HANDLER
*
* calling:
BURST_ALGO
*

** flowchart: figure 11
description: paragraph 6 . 4 . 2 **
****************************.************** •• ****************************/
IF INTR_VEC=RXI_GIR THEN DO ;,
RX_OCC=INPUT(FLR) ;

1*
1*
1*
1*
1*
1*

Rx fifo level occupancy
Shift the Rx occupancy bit
RX_OCC=SHR(RX_OCC,4)
to get it's real value
- OPTIMIZE code Empty the Rx FIFO and store the
received character in RX_BUF
RX_BUF(IX_RX:=IX_RX+1)=INPUT(RXD) ;
/* Read the first character immediatly
/* to save Real Time
DO WHILE (RX OCC:=RX OCC-l) > 0 ;
RX_BUF(IX=RX:=IX_Rx+l)=INPUT(RXD) ;
END;
,

*/
*/
*/
*/
*/
*/

*/
*/

/*************************************************************************
*
BURST ALGORITHM
*
*************************************************************************

* input:
* output:
* function:
*

* called by:
* calling:

** flowchart:

Burst Algo
Burst-Algo
execute a step in the burst algorithm
after characters are received
Rx_FIFO_INTR
none

' *
*
*
*
*
*

figure 5
description: par. 6.2.2.1 to 6.2.2.3
*
*************************************************************************/

1*-----------------------------------------------------------------*

* BUR S T
MOD E - step 3 (full fifo threshold)
*
*
* Reset the Timer status
*
* Restart the Timer
*-----------------------------------------------------------------*/
IF BURST ALGO = BURST MODE THEN DO ;
TEMP ~ INPUT(TMST);
OUTPUT (TMCR) =STARTIMB TMCR;
END;
-

I*--------------------~--------------------------------------------*
*
HUN TIN G MOD E, - step 1
*
* Operate the TIMER
* Change to step 2 SINGLE

mode

*
*

*-----------------------------------------------------------------*/

ELSE IF BURST ALGO = HUNTING MODE THEN DO ;
OUTPUT(TMCR)=STARTIMB TMCR
BURST_ALGO=SINGLE_MODE
END ;

292038-22

2-286

infef

AP-310

/*-----------------------------------------------------------------*
*

SIN G L E

MOD E - step 2

* If TIME has expired, means the receive
*
* rate is LOW, return to HUNTING mode
*
* If TIME did NOT expire, means the
*
* Receive rate is HIGH, set Rx FIFO threshold, Restart the
*
* Timer and switch to BURST mode
*
*----------------------------------------------------- ------------*/

ELSE IF BURST_ALGO = SINGLE_MODE THEN DO ;

IF ((INPUT(TMST) AND STARTIMB TMST) <>0) THEN
BURST_ALGO= HUNTING_MODE ;
ELSE DO;
OUTPUT (BANK) = GEN2;/* Switch to BANK TWO - General Config
OUTPUT(FMD)=TXTHRESHO FMD OR RXTHRESH3 FMD;
OUTPUT (BANK) =NASO; /* Switch to BANK ZERO - NAS
OUTPUT (GER) = ENTIMRX GER;
/* Enable TlMER,RX and MODEM interrupts
OUTPUT (BANK) =WORK1; /* Switch to BANK ONE - WORK
BURST ALGO = BURST MODE;
TEMP ~ INPUT(TMST); /* Reset timer status
OUTPUT (TMCR)
STARTIMB TMCR;
END;
END;
/* End of SINGLE mode

*/
*/
*/
*/

*/
*/

/* ..•. End of BURST algorithm ........•...••...••..........••••........ */
/*
/*

Another try to empty the Rx fifo
before leaving the interrupt handler

*/
*/

DO WHILE (INPUT (FLR) <>0)
/* Empty the Rx FIFO and store the
/* received character in RX_BUF
RX BUF(IX RX:=IX RX+1)=INPUT(RXD) ;
END ;END ;

/* End of Rx fifo interrupt

*/
*/

/*************************************************************************

TxFIFO INTR

*************************************************************************

*
*
*
*
*

input:
output:
function:
called by:
calling:

* flowchart:

Tx Buffer
Finish tx
service Tx Fifo interrupt
transmit characters from transmit buffer (OPTIMIZE code)
INTERRUPT HANDLER
none
figure 12

description:

paragraph 6.4.3

*
*

*
*
*
**

*************************************************************************/

ELSE IF INTR VEC=TXI GIR THEN DO ;
TX OCC=INPUT(FLR)-AND MASK TXOCC ;
*/
- /* Tx fifo level occupancy
/* Fill Tx FIFO, the transmitted characters are taken from TX buf
*/
DO WHILE (TX OCC:=TX OCC+l)<5 ;
OUTPUT(TXD)=TX BUF(IX TX:=IX TX+l) ;
IF TX BUF(IX TX)=End Of File-THEN DO
OUTPUT(BANK)=NASO-; ~~ /* Disable Tx interrupt, as the transmit */
OUTPUT(GER)=DISTX GER; /* delimiter character was identified
*/
OUTPUT(BANK)=WORKl
/* Switch to BANK ONE - WORK
*/
TX_OCC
5;
/* load TX_OCC to terminate external loop*/
FIN_TX = TRUE ;
/* Set Finish transmit flag
*/
END
END
END ;
/* End of TXFIFO INTR
*/
292038-23

2·287

inter

AP-310

1*************************************************************************

*.
STATUS INTR
.
*
*************************************************************************
* input:
none
*
* output:
FinishRx
*
service Status interrupt
*
* function:
*
Receive station: EOF terminate the reception
*
*
Transmit station: X Off Disable the transmission
*
*
x=on Enable the transmission
*
*
* called by: INTERRUPT HANDLER
* calling:
none
*

* flowchart: figure 13
description: paragraph 6.4.4
*
****************************************************** *******************1

STAT=INPUT(RST) ;

1* Get the current RST status

RX OCC=INPUT(FLR)
RX=OCC=SHR(RX_OCC,4)

/* Rx fifo level occupancy

DO WHILE (RX OCC>O AND (NOT FIN RX));
RX OCC=RX-OCC-1 ;
1* First, empty Rx FIFO
RX=CHR=tNPUT(RXD)

IF RECEIVER THEN
ELSE DO ;
IF RX CHR = X OFF THEN DO ;
OUTPUT(BANK)=NASO;/* Switch to BANK ZERO - NAS
OUTPUT (GER) = INPUT(GER) AND DISTX_GER ;
/* Disable Transmit interrupt
OUTPUT(BANK)=WORKl;/* switch to BANK ONE - WORK
END ;
ELSE IF RX CHR = X_ON THEN DO ;
OUTPUT(BANK)= NASO ;
OUTPUT (GER) = INPUT (GER) OR ENTX GER ;
/* Enable Transmit interrupt again
OUTPUT (BANK) = WORKl ;
END
END
END ;
IF RECEIVER THEN DO ;
IF «STAT AND ACRSTAT RST) <> 0) THEN DO ;
OUTPUT(BANK)= NASO-;
1* If End Of Line was recognized,
OUTPUT (GER) = DISRTX GER ;
-OUTPUT(BANK)= WORKl; /* Disable 825l0-interrupts and the
FIN_RX
= TRUE;
/* Reception
END ;
ELSE IF «STAT AND ERRCHR RST) <> 0) THEN DO ;
CALL WRITE(@('** ERROR-in character Status ',0))
CALL ERROR_CHAR_HANDLER ;
IF BURST ALGO=BURST MODE THEN DO ;
/* In BURST mode do:
TEMP = INPUT(TMST); /* Reset timer status
OUTPUT (TMCR)
STARTIMB TMCR;
END;
/* Restart TIMER
END

*/
*/

*1
*1
*/

*1
*1
*1

END
END ;

1* End of STATUS interrupt

*1
292038-24

2·288

intJ

AP-310

1***************************************************** *********~**********

*
TIMER INTR
*
*************************************************************************
* input:
none
*
* output:
Burst Algo
*
* function:
service Timer interrupt; receive characters
*
*
and switch Burst Algo to HUNTING mode
*
* called by: INTERRUPT HANDLER
*
* calling:
BURST &TIMER
*
** flowchart: figure 14
description: paragraph 6.4.5
**
*************************************************************************/
ELSE IF INTR_VEC=TIMI_GIR THEN DO ;
IF «RX_OCC:=INPUT(FLR»<>O) THEN DO
RX_OCC=SHR(RX_OCC,4) ; /* Rx fifo level occupancy, shift right */
/* - OPTIMIZE code */
/* Empty the Rx FIFO and store the
*/
/* received character in RX_BUF
*/
RX BUF(IX RX:=IX RX+l)=INPUT(RXD) ;
DO-WHILE (RX OCC:=RX OCC-l) > 0 ;
RX BUF(IX-RX:=IX Rx+l)=INPUT(RXD)
END /* Store the received character in RX_buf*/
END ;

/*************************************************************************
*
BURST & TIMER
*
*************************************************************************
input:
Burst_Algo
*
*
Burst Algo
* output:
*
execute a step in the burst algorithm
* function:
*
after timer interrupt; switch to HUNTING
*
*
* called by: TIMER_INTR
*
none
* calling:
*
*
*
* flowchart: figure 6
description: paragraph 6.2.2.4
*
*************************************************************************/
OUTPUT (BANK) = GEN2;
/* Switch to BANK TWO - General Config
*/
OUTPUT(FMO) = TXTHRESHO_FMD OR RXTHRESHO FMD;
,
/* Rxfifo threshold=O, Txfifo threshold=O*/
OUTPUT (BANK) = NASO;
OUTPUT (GER) = ENRX GER;
OUTPUT (BANK) = WORih; .
TEMP = INPUT (TMST) ;
BURST_ALGO
HUNTING_MODE
END ;

/*
/*
/*
/*
/*

Switch to BANK ZERO - NAS
Disable Timer interrupt and
Enable RX,STAT,MODEM interrupts
Acknowledge TIMER interrupt
Back to HUNTING mode
/* End of TIMER interrupt

*/
*/
*/
*/
*/
*/
292038-25

2-289

AP-310

/*************************************************************************

*
MODEM INTR
*
*************************************************************************
* input:
none
*
* output:
none
*
* function:
service Modem interrupt and handle modem errors.
*
*
Modem interrupt is occurred if No Modem was setup, or
*
if DSR was dropped in the middle of the communication
*
*
*
* called by: INTERRUPT HANDLER
none
*
* calling:
*

* flowchart: figure 15
description: paragraph 6.4.6
**
*************************************************************************/
ELSE IF INTR_VEC=MODMI_GIR THEN DO
STAT=INPUT(MSR)

;

Get MODEM status

Handel Modem Errors handshake

END ;

End of MODEM interrupt

OUTPUT(PORT_EOI)=COMM_EOI

1*
1*

Write End Of Interrupt command to the
PIC (8259A) -

*1
*1

END INTR_HANDLER

1***************************************************** ********************
* Procedure ERROR MODEM HANDLER
*
****************************************************** *******************1

ERROR_MODEM_HANDLER: PROCEDURE PUBLIC ;
MODEM_HANDSHAKE = FALSE ;

1*
1*

Flag indicates that an Error occurred
in Modem

*1
*1

1***************************************************** ********************

* Procedure ERROR CHAR HANDLER
*
*************************************************************************/

ERROR_CHAR_HANDLER: PROCEDURE PUBLIC ;
RX ERROR
OUTPUT (BANK)
OUTPUT (GER)
OUTPUT (BANK)

= TRUE
NASO ;
DISRTX GER
WORKl ;-

1*
1*

Flag indicates that an Error occurred
during Reception

*1
*1

1*
1*
1*

switch to BANK ZERO - NAS
Disable all the 82510 Interrupts
switch to BANK ONE - WORK

*1
*1
*1

END ERROR CHAR_HANDLER
292038-26

2·290

AP-310

1***************************************************** ********************

*
*
'*

Procedure

LOOP

LOOP procedure is executed until Transmission/Reception Finishes
or until the loop ends.

*
*

*************************************************************************/

LOOP: PROCEDURE PUBLIC
DECLARE N WORD ;
DECLARE NOM WORD ;.
DECLARE MAXLOOP BYTE
MAXLOOP= 20 ;
NOM=O ;
DO WHILE ( (NOT FIN TX) AND (NOT FIN RX) AND (NOM ' ,
CR-;-LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyz0123456789',
CR,LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyZ0123456789',
CR,LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyZ0123456789',
CR,LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyz0123456789',
CR,LF,
'ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789abcdefghijklmnopqrstuvwxyzo123456789',
CR,LF,End_Of_File,O)
/* End_Of_File-terminate the Tran~mission*/
END TEXT ;
292038-27

2-291

inter

AP-310

1***************************************************** ********************
.* External
procedures
*
*************************************************************************
* WRITELN: I/O console utility - dispaly a string, end with CR
*
I/O console utility - display a menu, enter the user
*
* MENU:

~~cti~

* DISPTEXT: I/O console utility - display the contents of the
*
Receive buffer (Rx_buf)
*
*
* INIT HARDWARE SETUP: setup and Hardware configurations of the
*
*
specific station
*
*************************************************************************/

1***************************************************** ****************~***

* Procedure
MAIN
*
*************************************************************************
* input:
Finish Rx, Finish Tx
*
* output:
Receiver flag
*
get station type (Rx or Tx) from the operator:
*
* function:
wait till communication is completed; display;
*
*
*
RECEIVER STATION SHOULD BE ACTIVATED FIRST
*
~ called by:
Application
*
INITIALIZATIONS, LOOP
*
* calling:

* flowchart:

figure

description:

paragraph 6.1

****************************************************** *~*****************/

MAIN:
CALL INIT_HARDWARE SETUP
/* External, Setup and H/W configurations*/
FIN=FALSE ;
DO WHILE NOT (FIN)
SELECTION=O ;
CALL WRITELN(@('------------------------------------------------ ',0));
SELECTION=MENU(SELECTION,@('Station: (Quit/Transmitter/Receiver) ',0)) ;
/* Get operator selection.
*/
/* Receiver station should be activated */
/* prior to the transmitter station
*/
DO CASE SELECTION ;
FIN=TRUE
/*
Quit of HIGH PERFORMANCE Driver
*/
DO ;
/* 1 - Transmit station
*/
RECElVER=FALSE ;
CALL INITIALIZATIONS
CALL LOOP;
END ;
DO :
/* 2 - Receive station
*/
RECElVER=TRUE
CALL INITIALIZATIONS
CALL LOOP ;
END
END
END

°-

CALL EXIT
END HIGHPERFORMANCE ;
/*************************************************************************/
292038-28

2-292

AP-310

APPENDIX B
82510 BASED SBX SERIAL CHANNEL
This document describes the implementation of an
82510 based SBX board that provides a RS-232 interface to any iSBC board which has an SBX connector.
The SBX can be useful for customers that need a fast
software development vehicle while the 82510 system
hardware is still in the design stage. The customer can
also use the SBX for evaluation of the 82510 in a system environment.
In order to minimize the customer's software development costs, the RMX86/286 Terminal Device Driver
for the 82510 has also been developed and can be run
by the RMX user on his iSBC with the SBX-82510
board described herewith. The RMX86/286 drivers are
available from INSITE, along with the source code and
the documentation.

BOARD DESCRIPTION

(See Figure B-1)

The following 82510 signals are connected directly to
the SBX connector (installed on the pin side): DATA,
ADDRESS, INTERRUPT, RESET, READ#,
WRITE# and CS#. Wait states are generated by a
shift register logic (U5, U7), clocked by the MCLK
signal of the SBX interface. The number of wait states
is selected by installing one of the eight jumpers to select one parallel output of the shift register. The 82510
is clocked by an 18.432 MHz Crystal (using its on-chip
oscillator). A discrete transistor is used to pull down
the RTS# signal during RESET to set the crystal mode
(note that in a larger board, an unused open collector
inverter or three-state gate can be used for this purpose). The 82510 is connected to the communication
channel through RS-232 line drivers and receivers. Either a 25 pin D-Type connector (P) or a 26 pin Fiat-Cable connector (F) is used to connect the board to the
RS-232 channel.

2-293

l
4 ' ,.

5 1'NT

, ;;
.
: o,~

221AO
U At

24 A2

~8,·
OTR#.--.-.-.
U2

n.::-

25 DO
I

26 D1

.::t..:::.=--____________________-::27:102

~~~--------------------~28~03

82510

TXolD

.::~~------------------------------------j'
04
,;:~
2 05
CTS#I'4
11

~~----------------------------------------7I3 06

"'1\

iEi

I';

~~~------------------1I-:20jRO#

iiJ

:;;

-0.

05R~ 1
...'' '°____-.,

4 07

19 WR#
18 C5#
Xl

A"J..

•

»
"U

...

Co)

I\)
I\)

III

...o
I

a.
~

::r
CD

..cr

UIW

J/3,17.35
"1O.u r

Vee 4 J / 4,18,36

1/1

J/Z

:1:::1£ Jf Jf::l!.

TTTTT
·=o.l~r

-12~

+ 12

WAIT State Generator
# of WAIT Jumper # of WAIT Jumper
to CLOSE States to CLOSE
States

1
2
3
4

81
82
83
84

5
6
7
8

85
86
87
88

Only One Jumper 8hould Be Closed at a Time

Type

Vee

GND -12

U1 82510

U2 1488

5,9

+12

Type

Vee

GND

-12

U6 Jumper
1

U7 74L800

U3 1489

8BX Male Connector for 8 Bit Bus

U4 1489

25 Pin D-Type Connector (Male)

26 Pin Flat-cable Connector (Male)

U5 74L8164 1,2,14

Either P or F should be installed.

+12

APPLICATION
NOTE

AP-36

November 1986

Using the 8273 SOLC/HOLC
Protocol Control lei

JOHN BEASTON
MICROCOMPUTER APPLICATIONS

Order Number: 611001-001
2-295

USING THE 8273 SOLCI
HOLC PROTOCOL
CONTROLLER

CONTENTS

PAGE

INTRODUCTION ....................... 2-297
SDLC/HDLC OVERVIEW . ............. 2-297
BASIC 8273 OPERATION ............. 2-300
HARDWARE ASPECTS OF THE
8273 ................................. 2-301
CPU Interface .......................... 2-301
Modem Interface ....................... 2-305

SOFTWARE ASPECTS OF THE
8273 ................................. 2-308
Command Phase Software ............. 2-309
Execution Phase Software .............. 2-310
Result Phase Software ................. 2-311

8273 COMMAND DESCRiPTION ...... 2-312
Initialization/Configuration Commands .. 2-313
Operating Mode Register ............... 2-313
Serial 110 Mode Register ............... 2-313
Data Transfer Mode Register ........... 2-313
One Bit Delay Register ................. 2-314
Receive Commands .................... 2-314
General Receive ....................... 2-314
Selective Receive ...................... 2-314
Selective Loop Receive ................ 2-314
Receive Disable ........................ 2-315
Transmit Commands .................... 2-317
Transmit Frame ........................ 2-317
Loop Transmit ......................... 2-317
Transmit Transparent .................. 2-317
Abort Commands ...................... 2-317
Reset Commands ...................... 2-318
Modem Control Commands ............ 2-319

HDLC CONSiDERATIONS ............. 2-319
LOOP CONFIGURATIONS ............ 2-320
APPLICATION EXAMPLE ............. 2-324
CONCLUSION ......................... 2-331
APPENDIX A .......................... 2-332

2-296

AP-36

INTRODUCTION

SDLC/HDLC OVERVIEW

The Intel 8273 is a Data Communications Protocol
Controller designed for use in systems utilizing either
SDLC or HDLC (Synchronous or High-Level Data
Link Control) protocols. In addition to the usual features such as full duplex operation, automatic Frame
Check Sequence generation and checking, automatic
zero bit insertion and deletion, and TTL compatibility
found on other single component SDLC controllers, the
8273 features a frame level command structure, a digital phase locked loop, SDLC loop operation, and diagnostics.

SDLC is a protocol for managing the flow of information on a data communications link. In other words,
SDLC can be thought of as an envelope-addressed,
stamped, and containing an s.a.s.e.-in which information is transferred from location to location on a data
communications link. (Please note that while SDLC is
discussed specifically, all comments also apply to
HDLC except where noted.) The link may be either
point-to-point or multi-point; with the point-to-point
configuration being either switched or nonswitched.
The information flow may use either full or half duplex
exchanges. With this many configurations supported, it
is difficult to find a synchronous data communications
application where SDLC would not be appropriate.

The frame level command structure is made possible by
the 8273's unique internal dual processor architecture.
A high-speed bit processor handles the serial data manipulations and character recognition. A byte processor
implements the frame level commands. These dual
processors allow the 8273 to control the necessary byteby-byte operation of the data channel with a minimum
of CPU (Central Processing Unit) intervention. For the
user this means the CPU has time to take on additional
tasks. The. digital phase locked loop (DPLL) provides a
means of clock recovery from the received data stream
on-chip. This feature, along with the frame level commands, makes SDLC loop operation extremely simple
and flexible. Diagnostics in the form of both data and
clock loop back are available to simplify board debug
and link testing. The 8273 is a dedicated function peripheral in the MCS-80/85 Microcomputer family and
as such, it interfaces to the 8080/8085 system with a
minimum of external hardware.
This application note explains the 8273 as a component
and shows its use in a generalized loop configuration
and a typical 8085 system. The 8085 system was used to
verify the SDLC operation of the 8273 on an actual
IBM SDLC data communications link.
The first section of this application note presents an
overview of the SDLC/HDLC protocols. It is fairly
tutorial in nature and may be skipped by the more
knowledgeable reader. The second section describes the
8273 from a functional standpoint with explanation of
the block diagram. The software aspects of the 8273,
including command examples, are discussed in the
third section. The fourth. and fifth sections discuss a
loop SDLC configuration and the 8085 system respectively.

Aside from supporting a large number of configurations, SDLC offers the potential of a 2 X increase in
throughput over the presently most prevalent protocol:
Bi-Sync. This performance increase is primarily due to
two characteristics of SDLC: full duplex operation and
the implied acknowledgement of transferred information. The performance increase due to full duplex operation is fairly obvious since, in SDLC, both stations can
communicate simultaneously. Bi-Sync supports only
half-duplex (two-way alternate) communication. The
increase from implied acknowledgement arises from the
fact that a station using SDLC may acknowledge previously received information while transmitting different
information. Up to 7 messages may be outstanding before an acknowledgement is required. These messages
may be acknowledged as a block rather than singly. In
Bi-Sync, acknowledgements are unique messages that
may not be included with messages containing information and each information message requires a separate
acknowledgement. Thus the line efficiency of SDLC is
superior to Bi-Sync. On a higher level, the potential of a
2 X increase in performance means lower cost per unit
of information transferred. Notice that the increase is
not due to higher data link speeds (SDLC is actually
speed independent), but simply through better line utilization.
Getting down to the more salient characteristics of
SDLC; the basic unit of information on an SDLC link
is that of the frame. The frame format is shown in Figure 1. Five fields comprise each frame: flag, address,
control, information, and frame check sequence. The
flag fields (F) form the boundary of the frame and all

Opening
Flag

Address
Field (A)

Control
Field (C)

Information
Field (I)

01111110

8 Bits

Any Length
. 0 to N Bits

Figure 1. SDlC Frame Format

2-297

Frame
Check
Sequence
(FCS)

Closing
Flag

16 Bits

01111110

inter

AP-36

other fields are positionally related to one of the two
flags. All frames start with an opening flag and end
with a closing flag. Flags are used for frame synchronization. They also may serve as time-fill characters between frames. (There are no intraframe time-fill characters in SDLC as there are in Bi-Sync.) The opening flag
serves as a reference point for the address (A) and control (C) fields. The frame check sequence (FCS) is referenced from the closing flag. All flags have the binary
configuration 01111110 (7EH).

The 8 bits following the address field form the control
field. The control field embodies the link-level control
of SDLC. A detailed explanation of the commands and
responses contained in this field is beyond the scope of
this application note. Suffice it to say that it is in the
control field that the implied acknowledgement is carried out through the use of frame sequence numbers.
None of the currently available SDLC single chip controllers utilize the control field. They simply pass it to
the processor for analysis. Readers wishing a more detailed explanation of the control field, or of SDLC in
general, should consult the IBM documents referenced
on the front page overleaf.

SDLC is a bit-oriented protocol, that is, the receiving
station must be able to recognize a flag (or any other
special character) at any time, not just on an 8-bit
boundary. This, of course, implies that a frame may be
N-bits in length. (The vast majority of applications tend
to use frames which are multiples of 8 bits long, however.)
The fact that the flag has a unique binary pattern would
seem to limit the contents of the frame since a flag
pattern might inadvertently occur within the frame.
This would cause the receiver to think the closing flag
was received, invalidating the frame. SDLC handles
this situation through a technique called zero bit insertion. This techniques specifies that within a frame a
binary 0 be inserted by the transmitter after any succession of five contiguous binary Is. Thus, nC) pattern of
01111110 is ever transmitted by chance. On the receiving end, after the opening flag is detected, the receiver
removes any 0 following 5 consecutive Is. The inserted
and deleted Os are not counted for error determination.
Before discussing the address field, an explanation of
the roles of an SDLC station is in. order. SDLC specifies two types of stations: primary and secondary. The
primary is the control station for the data link and thus
has responsibility of the overall network. There is only
one predetermined primary station, all other stations
on the link assume the secondary station role. In general, a secondary station speaks only when spoken to. In
other words, the primary polls the secondaries for responses. In order to specify a specific secondary, each
secondary is assigned a unique 8-bit address. It is this
address that is used in the frame's address field.
When the primary transmits a frame to a specific secondary, the address field contains the secondary's address. When responding, the secondary uses its own
address in the address field. The primary is never identified. This ensures that the primary knows which of
many secondaries is responding since the primary may
have many messages outstanding at various secondary
stations. In addition to the specific secondary address,
an address common to all secondaries may be used for
various purposes. (An all Is address field is usually
used for this "All Parties" address.) Even though the
primary may use this common address, the secondaries
are expected to respond with their unique address. The
address field is always the first 8 bits following the
opening flag.

In some types of frames, an information field follows
the control field. Frames used strictly for link management mayor may not contain one. When an information field· is used, it is unrestricted in both content and
length. This code transparency is made possible because
of the zero bit insertion mentioned earlier and the bitoriented nature of SDLC. Even main memory core
dumps may be transmitted because of this capability.
This feature is unique to bit-oriented protocols. Like
the control field, the information field is not interpreted
by the SDLC device; it is merely transferred to and
from memory to be operated on and interpreted by the
processor.
The final field is the frame check sequence (FGS). The
FCS is the 16 bits immediately preceding the closing
flag. This 16-bit field is used for error detection through
a Cyclic Redundancy Checkword (CRC). The 16-bit
transmitted CRC is the complement of the remainder
obtained when the A, C, and I fields are "divided" by a
generating polynomial. The receiver accumulates the
A, C, and I fields and also the FCS into its internal
CRC register. At the closing flag, this register contains
one particular number for an error-free reception; If
this number is not obtained, the frame was received in
error and should be discarded. Discarding the frame
causes the station to not update its frame sequence
numbering. This results in a retransmission after the
station sends an acknowledgement from previous
frames. [Unlike all other fields, the FCS is transmitted
MSB (Most Significant Bit) first. The A, C, and I fields
are transmitted LSD (Least Significant Bit) first.] The
details of how the FCS is generated and checked is
beyond the scope of this application note and since all
single component SDLC controllers handle this function automatically, it is usually sufficient to know only
that an error has or has not occurred. The IBM documents contain more detailed information for those
readers desiring it.
The closing flag terminates the frame. When the closing
flag is received, the receiver knows that the preceding
16 bits constitute the FCS and that any bits between the
control field and the FCS constitute the .information
field.

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inter

AP-36

SDLC does not support an interframe time-fill character such as the SYN character in Bi-Sync. If an unusual
condition occurs while transmitting, such as data is not
available in time from memory or CTS (Clear-to-Send)
is lost from the modem, the transmitter aborts the
frame by sending an Abort character to notify the receiver to invalidate the frame. The Abort character
consists of eight contiguous Is sent without zero bit
insertion. Intraframe time-fill consists of either flags,
Abort characters, or any combination of the two.
While the Abort character protects the receiver from
transmitted errors, errors introduced by the transmission medium are discovered at the receiver through the
FCS check and a check for invalid frames. Invalid
frames are those which are not bounded by flags or are
too short, that is, less than 32 bits between flags. All
invalid frames are ignored by the receiver.
Although SDLC is a synchronous protocol, it provides
an optional feature that allows its use on basically asynchronous data links-NRZI (Non-Return-to-Zero-Inverted) coding. NRZI coding specifies that the signal
condition does not change for transmitting a binary 1,
while a binary 0 causes a change of state. Figure 2 illustrates NRZI coding compared to the normal NRZ.
NRZI coding guarantees that an active line will have a
transition at least every 5-bit times; long strings of zeroes cause a transition every bit time, while long strings
of Is are broken up by zero bit insertion. Since asynchronous operation requires that the receiver sampling
clock be derived from the received data, NRZI encoding plus zero bit insertion make the design of clock
recovery circuitry easier.

DATA

BIT SAMPLE

I j j j j j j III

NRZ

NRZI

611001-1

Figure 2. NRZI vs NRZ Encoding

All of the previous discussion has applied to SDLC on
either point-to-point or multi-point data networks.
SDLC (but not HDLC) also includes specification for a
loop configuration. Figure 3 compares these three configurations. IBM uses this loop configuration in its
3650 Retail Store System. It consists of a single loop
controller station with one or more down-loop secondary stations. Communications on a loop rely on the
secondary stations repeating a received message down
loop with a delay of onc bit time. The reason for the
one bit delay will be evident shortly.
Loop operation defines a new special character: the
EOP (End-of-Poll) character which consists of a 0 followed by 7 contiguous, non-zero bit inserted, ones. After the loop controller transmits a message, .it idles the
line (sends all Is). The final zero of the closing flag plus
the first 7 Is of the idle form an EOP character. While

POINT·TO·POINT

LOOP

611001-3
MULTI·POINT

611001-2

Figure 3 .. Network Configurations

2-299

Ap·36

lowed by 7 Is) and the HDLC Abort (7 Is). This possible incompatibility is neatly handled by the HDLC protocol not specifying a loop configuration.

repeating, the secondaries monitor their incoming line
for an EOP character. When an EOP is detected, the
secondary checks to see if it has a message to transmit.
If it does, it changes the seventh 1 to a 0 (the one bit
delay allows time for this) and repeats the modified
EOP (now alias flag). After this flag is transmitted, the
secondary terminates its repeater function and inserts
its message (with multiple preceding flags if necessary).
After the closing flag, the secondary resumes its one bit
delay repeater function. Notice that the final zero of the
secondary's closing flag plus the repeated 1s from the
controller form an EOP for the next down-loop secondary, allowing it to insert a message if it desires.

This completes our brief discussion of the SDLC/
HDLC protocols. Now let us turn to the 8273 in particular and discuss its hardware aspects through an expla'nation of the block diagram and generalized system
schematics.

One, might wonder if the secondary missed any messages from the controller while it was inserting its own
message. It does not. Loop operation is basically halfduplex. The controller 'waits until it receives an EOP
before it transmits its next message. The controller's
reception 'of the EOP signifies that the original message
has propagated around the loop followed by any messages inserted by the secondaries. Notice that secondaries cannot communicate with one another directly, all
'secondary~to-secondary communication takes place by
way of the controller. '

'611001'-4
A. HDLC ADDRESS FIELD EXTENSION

FLAG I A

EXTENSION BIT (1 MAX)

C·I C. I .• I .•

IFCo.1 FCo.1

FLAG

611001-5
B. HDLC CONTROL FIELD EXTENSION

Figure 4

Loop protocol does not utilize the normal Abort character. Instead, an abort is accomplished by simply
transmitting a flag character. Down loop, the receiver
sees the abort as a frame which is either too short (if the
, abort occurred early in the frame) or one with an FCS
error. Either results in a discarded frame. For more
details on loop operation, please refer to the IBM documents referenced earlier.

BASIC 8273 OPERATION

Another protocol very similar to SDLC which the 8273
, supports is HDLC (High-Level Data, Link Control).
There are only three basic differences between the two:
HDLC offers extended address and control fields, and
the HDLC Abort character is 7 contiguous Is as opposed to SDLC's 8 contiguous Is.
Extended addressing, beyond the 256 unique addresses
possible with SDLC, is provided by using the address
field's least significant bit as the extended address modifier. The receiver examines this bit to determine if the
octet should be interpreted as the final address octet.
As long as the bit is '0, the octet that contains it is
considered an extended address. The first time the bit is
ai, the receiver interprets that octet as the final address
octet. Thus the address field,may be extended to any
number of octets. Extended addressing is illustrated in
Figure 4a.
A similar technique is used to extend the control field
although the extension is limited to only one extra control octet. Figure 4b illustrates control field extension.
Those readers not yet asleep may have noticed the similarity between the SDLC loop EOP character (a 0 fol-

It will be helpful for the following discussions to have
some idea of the basic operation of the 8273. Each operation, whether it is a frame transmission, reception or
port read, etc., is comprised of three phases: the Command, Execution, and Result phases. Figure 5 shows
the sequence of these phases. As an illustration of this
sequence, let us look at the transmit operation.

611001-6

Figure 5. 8273 Operational Phases

When the CPU decides it is time to transmit a frame,
the Command phase is entered by the CPU issuing a
Transmlt Frame command to the 8273. It is not sufficient to just instruct tp.e 8273 to transmit. The frame
level command structure sometimes requires more information such as frame length and address and control
field content. Once this additional information is sup-

2-300

inter

AP-36

plied, the Command phase is complete and the Execution phase is entered. It is during the Execution phase
that the actual operation, in this case a frame transmission, takes place. The 8273 transmits the opening flag,
A and C fields, the specified number of I field bytes,
inserts the FCS, and closes with the closing flag. Once
the closing flag is transmitted, the 8273 leaves the Execution phase and begins the Result phase. During the
Result phase the 8273 notifies the CPU of the outcome
of the command by supplying interrupt results. In this
case, the results would be either that the frame is complete or that some error condition causes the transmission to be aborted. Once the CPU reads all of the results (there is only one for the Transmit Frame
command), the Result phase and cons,equentIy the
operation, is complete. Now that we have a general
feeling for the operation of the 8273, let us discuss the
8273 in detail.

HARDWARE ASPECTS OF THE 8273
The 8273 block diagram is shown in Figure 6. It consists of two major interfaces: the CPU module interface
and the modem interface. Let's discuss each interface
separately.

CPU Interface
The CPU interface consists of four major blocks: Control/Read/Write logic (C/R/W), internal registers,
data transfer logic, and data bus buffers.
The CPU module utilizes the C/R/W logic to issue
commands to the 8273. Once the 8273 receives a command and executes it, it returns the results (goodlbad
completion) of the command by way of the C/R/W
logic. The C/R/W logic is supported by seven registers
which are addressed via the AO, A I> RD, and WR signals, in addition to CS. The AO and Al signals are generally derived from the two low order bits of the CPU
module address bus while RD and WR are the normal
I/O Read and Write signals found on the system control bus. Figure 7 shows the address of each register
using the C/R/W logic. The function of each register is
defined as follows:
Control Inputs

Address Inputs
A1

CSoRD

CSoWR

0
0
1
1

0
1
0
1

Status
Result
TxllR
Rxl/R

Command
Parameter
Test Mode

Figure 7. 8273 Register Selection

. - - - - - - - - FLAG DETECT

, . . - - - - - - - Co
REGISTERS

TxllR

.------CTS
,..----_RTS

COMMAND

RxllR
TEST MODE

080_7

P-----T'C

TxDRa----j
DATA
TIMING
LOGIC

I-----T'O
P-----R,C
1-----RxD

~----__ DPLL

' - - - - - - - - 32XCLK

Ao----I
A'---_I
RESET

- ----'1'1

OCLK-----~

T,INT _ - ' -_ _ _ _--'
RxlNT _ _ _ _ _ _- - '
CPU MODULE INTERFACE

MODEM INTERFACE

611001-7

Figure 6. 8273 Block Diagram
2-301

inter

AP-36

munications channel. Figure 8 illustrates the transfer
rate of data bytes that are acquired by the 8273 based
on link data rate. Full"duplex data rates above 9600
baud usually require DMA. Slower speeds mayor may
not require DMA depending on the task load and interrupt response time of the processor.

Command-8273 operations are initiated by writing
the appropriate command byte into this register.
Parameter-Many commands require more information than found in the command itself. This additional
information is provided by way of the parameter register.

Figure 9 shows the 8273 in a typical DMA. environment. Notice that a separate DMA controller, in this
case the Intel 8257, is required. The DMA controller
supplies the timing and addresses for the data transfers
while the 8273 manages the requesting of transfers and
the actual counting of the data block lengths. In this
case, elements of the data transfer interface are:

Immediate Result. {Result}-The completion information (results) for commands which execute immediately
are provided in this register.
Transmit Interrupt Result {TxI/R}-Results of transmit operations are passed to the CPU in this register.

TxDRQ: Transmit DMA Request-Asserted by the

Receiver Interrupt Result {RxI/R}-Receive operation
results are passed to the CPU via this register.

8273, this line requests a DMA transfer from memory
. to the 8273 for transmit.

Status-The general status of the 8273 is provided in
this register. The Status register supplies the handshaking necessary during various phases of the 8273 operation.

TxDACK: Transmit DMA Acknowledge-Returued by
the 8257 in response to TxDRQ, this line notifies the
8273 that a request has been granted, and provides access to the transmitter data register.

Test Mode-This register provides a software reset
function for the 8273.
The commands, Pllrameters, and bit definition of these
registers are discussed in the following software section.
Notice that there are not specific transmit or receive
data registers. This feature is explained in the data
transfer logic discussion.
The final elements of the C/RIW logic are the interrupt lines (RxINT and TxINT). These lines notify the
CPU module that either the transmitter or the receiver
requires service; i.e., results should be read from the
appropriate interrupt result register or a data transfer is
required. The interrupt request remains active until all
the associated interrupt results have been read or the
data transfer is performed. Though using the interrupt
lines relieves the CPU module of the task of polling the
8273 to check if service is needed, the state of each
interrupt line is reflected by a bit in the Status register
and non-interrupt driven operation is possible by examining the contents of these bits periodically.
The 8273 supports two independent data interfaces
through the data transfer logic; receive data and transmit data. These interfaces are programmable for either
DMA or non-DMA data transfers. While the choice of
the configuration is up to the system designer, it is
based on the intended maximum data rate of the com-

RxDRQ: Receive DMA Request-Asserted by the 8273.
.it requests a DMA transfer from the 8273 to memory
for a receive operation.
,
RxDACK: Receive DMA Acknowledge-Returned by
the 8257, it notifies the 8273 that a receive DMAcycie
has been granted, and provides access to the receiver
data register.
RD: Read-Supplied by the 8257 to indicate data is to
be read from the 8273 and placed in memory.
WR: Write--Supplied by the 8257 to indicate data is to
be written to the 8273 from memory.
To request a DMA transfer the 8273 raises the appropriate DMA request line; let us assume it is a transmitter request (TxDRQ). Once the 8257 obtains control of
the system bus by way of its HOLD and HLDA (hold
acknowledge) lines, it .notifies the 8273 that TxDRQ
has been granted by returning TxDACK and WR. The
TxDACK and WR signals transfer data to the 8273 for
a transmit, independent of the 8273 chip select pin
(CS). A similar sequence of events occurs for receiver
requests. This "hard select" of data into the transmitter
or out of the receiver alleviates the need for the normal
transmit and receive data registers addressed by a combination of address lines. CS, and WR or RD. Competi-

2-302

inter

AP-36

tive devices that do not have this "hard select" feature
require the use of an external multiplexer to supply the
correct inputs for register selection during DMA. (Do
not forget that the SDLC controller sees both the addresses and control signals supplied by the DMA controller during DMA cycles.) Let us look at typical
frame transmit and frame receive sequences to better
see how the 8273 truly manages the DMA data transfer.

At this point the requests stop, the FCS and closing flag
are transmitted, and the TxINT line is raised, signaling
the CPU that the frame transmission is complete. Notice that after the initial command and parameter loading, absolutely no CPU intervention was required (since
DMA is used for data transfers) until the entire frame
was transmitted. Now let's look at a frame reception.
80 ms

Before a frame can be transmitted, the DMA controller
is supplied, by the CPU, the starting address for the
desired information field. The 8273 is then commanded
to transmit a frame. (Just how this is done is covered
later during our software discussion.) After the command, but before transmission begins, the 8273 needs a
little more information (parameters). Four parameters
are required for the transmit frame command: the address field byte, the control field byte, and two bytes
which are the least significant and most significant
bytes of the information field byte length. Once all four
parameters are loaded, the 8273 makes RTS (Requestto-Send) active and waits for CTS (Clear-to-Send) to go
active. Once CTS is active, the 8273 starts the frame
transmission. While the 8273 is transmitting the opening flag, address field, and control field; it starts making
transmitter DMA requests. These requests continue at
character (byte) boundaries until the pre-loaded number of bytes of information field have been transmitted.

8 ms
sec/byte

800

80 "s

100

100K

611001-8

Figure 8. Byte Transfer Rate vs Baud Rate

TxDACK
RxDRO

10K

BAUD RATE (bps)

DR01
8257
DACK1
DMA
CONTROLLER

8273

RxDACK
CS AO

lOR

roo,,"m
BUS

lOW
WR

07-00

~ ~o.,.,",

ADDRESS
BUS

611001-9

Figure 9. DMA, Interrupt-Driven System

2-303

inter

AP-36

The receiver operation is very similar. Like the initial
transmit sequence, the DMA controller is loaded with a
starting address for a receiver data buffer and the 8273
is commanded to receive. Unlike the transmitter, there
are two different receive commands: General Receive,
where all received frames are transferred to memory,
and Selective Receive, where only frames having an address field matching one of two preprogrammed 8273
address fields are transferred to memory. Let's assume
for now that we want to general receive. After the receive command, two parameters are required before the
receiver becomes active: the least significant and most
significant bytes of the receiver buffer length. Once
these bytes are loaded, the receiver is active and the
CPU may return to other tasks. The next frame appearing at the receiver input is transferred to memory using
receiver DMA requests. When the closing flag is received, the 8273 checks the FCS and raises its RxINT
line. The CPU can then read the results which indicate
if the frame was error-free or not. (If the received frame
had been longer than the pre-loaded buffer length, the
CPU would have been notified of that occurrence earlier with a receiver error interrupt. The command description section contains a complete list of error conditions.) Like the transmit example, after the initial come
mand, the CPU is free for other tasks until a frame is
completely received. These examples have illustrated
the 8273's management of both the receiver and transmitter DMA channels.
It is possible to use the DMA data transfer interface in
a non-DMA interrupt-driven environment. In this case,
4 interrupt levels are used: one each for TxINT and
RxINT, and one each for TxDRQ and RxDRQ. This
configuration is shown in Figure 10. This configuration
offers the advantages that no DMA controller is re-

quired and data requests are still separated from result
(completion) requests. The disadvantages of the configuration are that 4 interrupt levels are required and that
the CPU must actually supply the data transfers. This,
of course, reduces the maximum data rate compared to
the configuration based strictly on DMA. This system
could use an Intel 8259 8-level Priority Interrupt Controller to supply a vectored CALL (subroutine) address
based on requests on its inputs. The 8273 transmitter
and receiver make data requests by raising the respective DRQ line. The CPU is interrupted by the 8259 and
vectored to a data transfer routine. This routine either
writes (for transmit) or reads (for receive) the 8273 using the respective TxDACK or RxDACK line. The
DACK lines serve as "hard" chip selects into and out
of the 8273. TxDACK + WR writes data into the 8273
for transmit. RxDACK + RD reads data from the
8273 for receive.) The CPU is notified of operation
completion and results by way of TxINT and RxINT
lines. Using the 8273, and the 8259, in this way, provides a very effective, yet simple, interrupt-driven interface.
Figure 11 illustrates a system very similar to that described above. This system utilizes the 8273 in a nonDMA data transfer mode as opposed to the two DMA
approaches shown in Figures 9 and 10. In the .nonDMA case, data transfer requests are made on the
TxINT and RxINT lines. The DRQ lines are not used.
Data -transfer requests are separated from result requests by a bit in the Status register. Thus, in response
to an interrupt, the CPU reads the Status register and
branches to either a result or a data transfer routine
based on the status of one bit. As before, data transfers
are made via using the DACK lines as chip selects to
the transmitter and receiver data registers.

07-00

~ ~""'"
Figure 10. Interrupt-Based DMA System

2-304

611001-10

AP-36

CONTROL
BUS

611001-11

Figure 11. Non-DMA Interrupt-Driven System

-CONTROL
lOR

BUS

8273

07-00

611001-12

Figure 12. Polled System

Figure 12 illustrates the simplest system of all. This
system utilizes polling for all data transfers and results.
Since the interrupt pins are reflected in bits in the
Status register, the software can read the Status register
periodically looking for one of these to be set. If it finds
an INT bit set, the appropriate Result Available bit is
examined to determine if the "interrupt" is a data
transfer or completion result. If a data transfer is called
for, the DACK line is used to enter or read the data
from the 8273. If the interrupt is a completion result,
the appropriate result register is read to determine the
good/bad completion of the operation.

The final block of the CPU module interface is the
Data Bus Buffer. This block supplies the tri-state, bidirectional data bus interface to allow communication to
and from the 8273.

The actual selection of either DMA or non-DMA
modes is controlled by a command issued during initialization. This command is covered in detail during
the software discussion.

The modem control block provides both dedicated and
user-defined modem control functions. All signals supported by this interface are active low so that EIA in-

Modem Interface
As the name implies, the modem interface is the modem side of the 8273. It consists of two major blocks:
the modem control block and the serial data timing
block.

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AP-36

verting drivers (MC1488) and inverting receivers
(MC1489) may be used to interface to standard modems.

This function is handled automatically by the 8273. If
RTS is inactive (pin is high) when the 8273 is commanded to transmit, the 8273 makes it active and then
waits for CTS before transniitting the frame. One byte
time after the end of the frame, the 8273 returns RTS to
its inactive state. However, if RTS was active when a
transmit command is issued, the 8273 leaves it active
when the frame is complete.

Port A is a modem control input port. Its representation on the data bus is shown in Figure 13. Bits Do and
D) have dedicated functions. Do reflects the logical
state of the CTS (Clear-to-Send) pin. [If CTS is active
(low), DO is a 1.1 This signal is used to condition the
start of a transmission. The 8273 waits until CTS is
active before it starts transmitting a frame. While transmitting, if CTS goes inactive, the frame is aborted and
the CPU is interrupted. When the CPU reads the interrupt result, a CTS failure is indicated.

Bit Ds reflects the state of the Flag Detect pin. This pin
is activated whenever an active receiver sees a flag character. This function is useful to activate a timer for line
activity timeout purposes.
'

D) reflects the logical state of the CD (Carrier Detect)
pin. CD is used to condition the start of a frame reception. CD must be active in time for a frame's address
field. If CD is lost (goes inactive) while receiving a
frame, an interrupt is generated with a CD failure result. CD may go inactive between frames.

Bits D) thru D4 provide four user-defined outputs. Pins
PB) thru PB4 reflect the logical state of these bits. The
8273 does not interrogate or, manipUlate these bits. D6
and D7 are not used. In addition to being able to output
to Port B, Port B may be read using a Read Port B
command. All Modem control output pins are forced
high on reset. (All commands mentioned in this section
are covered in detail later.)

Bits D2 thru D4 reflect the logical state of the PA2 thru
PA4 pins respectively.' These inputs are user defined.
The 8273 does not interrog~te or manipulate these bits.
Bits Ds, D6, and D7 are not used and each is read as a 1
for a Read Port A command.

The final block to be covered is the serial data timing
block. This block contains two sections: the serial data
.
logic and the digital phase locked loop (DPLL).

Port B is a modem control output port. Its data bus
representation is shown in' Figure 14. As in Port A, the
bit values represent the logical condition of the pins. DO
and ~are dedicated function outputs. Do represents
the RTS (Request-to-Send) pin. RTS is normally used
to notify the modem that the 8273 wishes to transmit.
D7

I, I ' I ' I I

I
I
I

Elements of the serial data logic section are the data
pins, TxD (transmit data output) and RxD (receive
data input), and the _respective data clocks, TxC and
RxC. The transmit and receive data is synchronized by
the TxC and RxC clocks. Figure 15 shows the timing
for these signals. The leading edge (negative transition)

CTS - CLEAR TO SEND
CD - CARRIER DETECT
PA2 }
PAa
USER,DEFINED INPUTS
PA4

611001-13

Figure 13. Port A (Input) Bit Definition

RTS -

::~

' - - - - - - - - PBa
~--------------PB4

REQUEST TO-SEND

USER·DEFINED OUTPUTS

' - - - - - - - - - - - - FLAG DETECT

611001-14

Figure 14. Port B (Output) Bit Definition

2-306

AP-36

nal circuitry. Clock loopback overcomes this problem
by allowing the internal routing of TxC and RxC. Thus
the same clock used to transmit the data is used to
receive it. Examination of Figure 15 shows that this
method ensures bit synchronism. The final element of
the serial data logic is the Digital Phase Locked Loop.

of TxC generates new transmit data and the trailing
edge (positive transition) of RxC is used to capture the
receive data.

=><

The DPLL provides a means of clock recovery from
the received data stream. This feature allows the 8273
to interface without external synchronizing logic to low
cost asynchronous modems (modems which do not
supply clocks). It also makes the problem of clock timing in loop configurations trivial.

X'----_

~:riiJ

To use the DPLL, a clock at 32 times the required baud
rate must be supplied to the 32 X CLK pin. This clock
provides the interval that the DPLL samples the received data. The DPLL uses the 32 X clock and the
received data to generate a pulse at the DPLL output
pin. This DPLL pulse is positioned at the nominal center of the received data bit cell. Thus the DPLL output
may be wired to RxC and/or TxC to supply the data
timing. The exact position of the pulse is varied depending on the line noise and bit distortion of the received
data. The adjustment of the DPLL position is determined according to the rules outlined in Figure 16.

611001-15

Figure 15. Transmit/Receive Timing
It is possible to reconfigure this section under program
control to perform diagnostic functions; both data and
clock loopbackare available. In data loopback mode,
the TxD pin is internally routed to the RxD pin. This
allows simple board checkout since the CPU can send
an SDLC message to itself. (Note that transmitted data
will still appear on the TxD pin.)

BI> B2,
or A2) the data edge falls in. (Each quadrant represents
832 X CLK times.) For example, if the edge is detected
in quadrant AI, it is apparent that pulse B was too close
to the data edge and the time to the next pulse must be
shortened. The adjustment for quadrant Al is specified
as - 2. Thus, the next 'i5PEE pulse, pulse C, is positioned 32 - 2 or 30 32X CLK pulses following DPLL
pulse B. This adjustment moves pulse C closer to the
nominal bit center of the next received data cell. A data
edge occurring in quadrant B2 would have caused the
adjustment to be small, namely 32 + 1 or 33 32 X
CLK pulses. Using this technique, the DPLL pulse
converges to the nominal bit center within 12 data transitions; worse case-4-bit times adjusting through
quadrant Al or A2 and 8-bit times adjusting through
BI or B2·

SYNC
MODEM

611001-17
Synchronous Modem Interface

611001-18
Asynchronous Madem Interface

When the receive ·data stream goes idle after 15 ones,
DPLL pulses are generated at 32 pulse intervals of the
32 X CLK. This feature allows the DPLL pulses to be
used as both transmitter and receiver clocks.

Figure 17. Serial Data Timing Configuration

SOFTWARE ASPECTS OF THE 8273
In order to guarantee 'sufficient transitions . of the received data to enable the DPLL to lock, NRZI encoding of the data is recommended. This ensures that,
. within a frame, data transitions occur at least every five
bit times-the longest sequence of Is which may be
transmitted with zero bit insertion. It is also recomc
mended that frames following a line idle be transmitted
with preframe sync characters which ·provide a minimum of 12 transitions. This ensures that the DPLL is
generating DPLL pulses at the nominal bit centers in
time for the opening flag. (Two DOH characters meet
this requirement by supplying 16 transitions with
NRZI encoding. The 8273 contains a mode which supplies such a preframe syric.)

The software aspects of the 8273 involve the ·communication of both commands from the CPU to the 8273
and the return of results of those commands from the
8273 to the CPU. Due to the internal processor architecture of the 8273, this CPU-8273 communication is
basically a form ofinterprocessor communication. Such
communication usually requires a form of protocol of
its own. This protocol is implemented through use of
handshaking supplied in the 8273 Status register. The
bit definition of this register is shown in Figure 18.

Figure 17 illustrates 8273 clock configurations using
either synchronous or asynchronous modems, Notice
how the DPLL output is used for both TxC and RxC in
the asynchronous case. This feature eliminates the need
for external clock generation logic where low cost asynchronous modems are used and also allows direct connection of 8273s for the ultimate in low cost data links.
The configuration for loop applications is discussed in a
following section.

2-308

TxlRA - TaiNT RESULT AVAILABLE
RdRA - RIINT RESULT AVAILABLE
AxlNT l~=~===TIINT

TxlNTERRUPT
Rx INTERRUPT

CABF - COMMAND HESULT
- BUFFER FULL
L-_ _ _ _ _ _ _ CPBF _ COMMAND PARAMETER
BUFFER FULL

L--_ _ _ _ _ _ _ _ CBF _ COMMAND BUFFER FUll
L--_ _ _ _ _ _ _ _ _ _ eaSY -:- COMMAND BUSY

611001-19.

Figure 18. Status Register Format

inter

AP-36

CBSY: Command Busy---CBSY indicates when the
8273 is in the command phase. CBSY is set when the
CPU: writes a command into the Command register,
startmg the Command phase. It is reset when the last
parameter is deposited in the Parameter register and
accepted by the 8273, completing the Command phase.
CBF: Command Buffer Full-When set, this bit indicates that a byte is present in the Command register.
This bit is normally not used.
CPBF: Command Parameter Buffer Full-This bit indicates that the Parameter register contains a parameter. It is set when the CPU deposits a parameter in the
Parameter register. It is reset when the 8273 accepts the
parameter.
CRBF: Command Result Buffer Full-This bit is set
when the 8273 places a result from an immediate type
command in the Result register. It is reset when the
CPU reads the result from the Result register.
RxINT: Receiver Interrupt-The state of the RxlNT
pin is reflected by this bit. RxINT is set by the 8273
whenever the receiver needs servicing. RxINT is reset
when the CPU reads the results or performs the. data
transfer.
TxINT: Transmitter Interrupt-This bit is identical to
RxlNT except action is initiated based on transmitter
interrupt sources.
RxIRA: Receiver Interrupt Result Available-RxlRA is
set when the 8273 places an interrupt result byte into
the RxI/R register. RxIRA is reset when the CPU
reads the Rxl/R register.
TxIRA: Transmitter Interrupt Result AvailableTxlRA is the corresponding Result Available bit for
the transmitter. It is set when the 8273 places an interrupt result byte in the Txl/R register and reset when
the CPU reads the register.
The significance of each of these bits will be evident
shortly. Since the software requirements of each 8273
phase are essentially independent, each phase is covered
separately.

Command Phase Software
Recalling the Command phase description in an earlier
section, the CPU starts the Command phase by writing
a command byte into the 8273 Command register. If
further information about the command is required by
the 8273, the CPU writes this information into the Parameter register. Figure 19 is a flowchart of the Command phase. Notice that the CBSY and CPBF bits of
the Status register are used to handshake the command
and parameter bytes. Also note that the chart shows

611001-20

Figure 19. Command Phase Flowchart

that a command may not be issued if the Status register
indicates the 8273 is busy (CBSY = 1). If a command
is issued while CBSY = 1, the original command is
overwritten and lost. (Remember that CBSY signifies
the command phase is in progress and not the actual
execution of the command.) The flowchart also includes a Parameter buffer full check. The CPU must
wait until CPBF = 0 before writing a parameter to the
Parameter register. If a parameter is issued while CPBF
= 1, the previous parameter is overwritten and lost.
An example of command output assembly language
software is provided in Figure 20a. This software assumes that a command buffer exists in memory. The
buffer is pointed at by the HL register. Figure 20b
shows the command buffer structure.
The 8273 is a full duplex device, i.e., both the transmit~er and receiver may be executing commands or passing
mterrupt results at any given time. (Separate Rx and Tx
interrupt pins and result registers are provided for this
reason.) However, there is only one Command register.
Thus, the Command register must be used for only one
command sequence at a time and the transmitter and
receiver may never be simultaneously in a command
phase. A detailed description of the commands and
their parameters is presented in a following section.

2-309

AP-36

;FUNCTION: COMMAND DISPATCHER
;INPUTS: HL - COMMAND BUFFER ADDRESS
;OUTPUTS: NONE
; CALLS : NONE
;DESTROYS: A,B,H,L,F/F'S
;DESCRIPTION: CMDOUT ISSUES THE COMMAND + PARAMETERS
;IN THE COMMAND BUFFER POINTED AT BY HL
CMDOUT: LXI
MOV
INX
CMD1:
IN
RLC
JC
MOV
OUT
CMD2:
MOV
ANA
RZ
INX
DCR
CMD3:
IN
ANI
JNZ
MOV
OUT
JMP

H,CMDBUF ;POINT HL AT BUFFER
B,M
;lST ENTRY IS PAR. COUNT
H
;POINT AT COMMAND BYTE
STAT73 I ;READ 8273 STATUS
;ROTATE CBSY INTO CARRY
CMDl
;WAIT UNTIL CBSY=O
A,M
;MOVE COMMAND BYTE TO A
COMM73
;PUT COMMAND IN COMMAND REG
A,B
;GET PARAMETER COUNT
A
;TEST IF ZERO
; IF 0 THEN DONE
H
;NOT DONE, SO POINT AT NEXT PAR
;DEC PARAMETER COUNT
B
STAT73
;READ 8273 STATUS
CPBF
;TEST CPBF BIT
CMD3
;WAIT UNTIL CPBF IS 0
A,M
;GET PARAMETER FROM BUFFER
PARM73
;OUTPUT PAR TO PARAMETER REG
CMD2
;CHECK IF MORE PARAMETERS
Figure 20A. Command Phase Software

+4
.+3
+2

PARAMETER 3

COMMAND

CMDBUF:

Execution Phase Software

PARAMETER 2
PARAMETER 1
PARAMETER COUNT

-HL

Figure 208. Command Buffer Format

During the Execution phase, the operation specified by
the Command phase is performed. If the system utilizes
DMA for data transfers, there is no CPU involvement
during this phase, so no software is required. If nonDMA data transfers are used, either interrupts or polling is used to signal a data transfer request.
For interrupt-driven transfers the 8273 raises the appropriate INT pin. When responding to the interrupt,

2-310

AP-36

the CPU must deterinine whether it is a data transfer
request or an interrupt signaling that an operation is
complete and results are available. The CPU determines the cause by reading the Status register and interrogating the associated IRA (Interrupt Result
Available) bit (TxIRA for TxINT and RxIRA for
RxINT). If the IRA = 0, the interrupt is a data
transfer request. If the IRA = I, an operation is
complete and the associated Interrupt Result register
must be read to determine the completion status (good/
bad/etc.). A software interrupt handler implementing
the above sequence is presented as part of the Result
phase software.
When polling is used to determine when data transfers
are required, the polling routine reads the Status register looking for one of the INT bits to be set. When a set
INT bit is found, the corresponding IRA bit is examined. Like in the interrupt-driven case, if the IRA = 0,
a data transfer is required. IflRA = 1, an operation is
complete and the Interrupt Result register needs to be
read. Again, example polling software is presented in
the next section.

Result Phase Software
During the Result phase the 8273 notifies the CPU of
the outcome of a command. The Result phase is initiated by either a successful completion of an operation or
an error detected during execution. Some commands
such as reading or writing the I/O ports provide immediate results, that is, there is essentially no 'delay from
the issuing of the command and when the result is
available. Other commands such as frame transmit,
take time to complete so their result is not available
immediately. Separate result registers are provided to
distinguish these two types of commands and to avoid
interrupt handling for simple results.

Immediate results are provided in the Result register.
Validity of information in this register is indicated to
the CPU by way of the CRBF bit in the Status register.
When the CPU completes the Command phase of an
immediate command, it polls the Status register waiting
until CRBF = 1. When this occurs, the CPU may read
the Result register to obtain the immediate result. The
Result register provides only the results from immediate commands.
Example software for handling immediate results is
shown in Figure 21. The routine returns with the result
in the accumulator.' The CPU then uses the result as is
. appropriate.
All non-immediate commands deal with either the
transmitter or receiver. Results from these commands
are provided in the Txl/R (Transmit Interrupt Result)
and Rxl/R (Receive Interrupt Result) registers respectively. Results in these registers are conveyed to the
CPU by the TxlRA and RxlRA bits of the status register. Results of non-immediate commands consist of one
byte result interrupt code indicating the condition for
the interrupt and, if required, one or more bytes supplying additional information. The interrupt codes and the
meaning of the additional results are covered following
the detailed command description.
Non-immediate results are passed to the CPU in response to either interrupts or polling of the Status register. Figure 22 illustrates an interrupt-driven result handler. (Please note that all of the software presented in
this application note is not optimized for either speed or
code efficiency. They are provided as a guide and to
illustrate concepts.) This handler provides for interrupt-driven data transfers as was promised in the last
section. Users employing DMA-based transfers do not

;FUNCTION: IMDRLT
;INPUTS: NONE
;OUTPUTS: RESULT REGISTER IN A
;CALLS: NONE
;DESTROYS: A, F/F'S
;DESCRIPTION: IMDRLT IS CALLED AFTER A CMDOUT FOR AN
;IMMEDIATE COMMAND TO READ THE RESULT REGISTER
IMDRLT: IN
ANI
JZ
IN
RET

STAT 73
CRBF
IMDRLT
RESL73
;RETURN

;READ
;TEST
;WAIT
;READ

8273 STATUS
IF RESULT REG READY
IF CRBF=O
RESULT REGISTER

Figure 21. Immediate Result Handler

AP-36

place the results in a result buffer pointed at by
RCRBUF and TxRBUF.

.FUNCTION; RX! - INTERRUPT DRIVEN RESULT/DATA HANDLEk
; INPUTS; ReRBur, RCVPNT

: CALLS: HONE
;OUTPUTS: ReRsur, RCVPNT
; DESTROYS: NOTHING
;DESCRIPTION: RXI IS ENTERED AT A RECEIVER INTt:;RRUPT.
;THE INTERRUPT IS TESTED FOR DATA .TRANSFER (IRA=S)
:DR RESULT (lRA"'l).
FOR DATA TRANSFER, THE DATA .IS
;PLACED IN A BUFFER AT RCVPNT. RESULTS ARE PLACED IN
; A BUFFER AT ReRsur.
;A FLAG(RXFLAG) IS SET IF THE INTERRUPT WAS A RESULT.
; (DATA TRANSFER INSTRUCTIONS ARE DENOTED BY 1-) AND

A- typical result handler for systems utilizing polling is
shown in Figure 23. Data transfers are also handled by
this routine. This routine utilizes the routines of Figure
22 to handle the results.

;HAYSE ELIMINATEO BY USt.RS USING DMA.

;
aXI:

PUSH
PUSH
PUSH

RXI1:

RXl4;
lOIN'fER
RCIlBUf
;RESTORE BUFFER POIN'!ER
RxIl
:GO BACK TO SEE IF M01 32 bits). The 8273 handles this N-bit
reception through the high order bits (D7-DS) of the
result code. These bits code the number of valid received bits in the last received information field byte.
This coding is shown in Figure 30. The high order bits
of the received partial byte are indeterminate. [The address, control, and information fields are transmitted
least significant bit (Ao) first. The FCS is .complemented and transmitted most significant bit first.]

Transmit Commands
The 8273 transmitter is supported by three Transmit
commands and three corresponding Abort commands.

returns to either Idle or Flag Stream, depending on the
Flag Stream bit of the Operating Mode register. If RTS
was active before the transmit command, the 8273 does
not change it. If it 'was inactive, the 8273 will deactivate
it within one character time.

Loop Transmit
Loop Transmit is similar to Frame Transmit (the parameter definition is the same). But since it deals with
loop configurations, One Bit Delay mode must be selected.
If the transmitter is not in Flag Stream mode when this
command is issued, the transmitter waits until after a
received EOP character has been converted to a flag
(this is done automatically) before transmitting. (The
one bit delay is, of course, suspended during transmit.)
If the transmitter is already in Flag Stream mode as a
result of a selectively received frame during a Selective
Loop Receive command, transmission will begin at the
next flag boundary for Buffered mode or at the third
flag boundary for non-Buffered mode. This discrepancy
is to allow time for enough data transfers to occur to fill
up the internal transmit buffer. At the end of a Loop
Transmit, the One Bit Delay mode is re-entered and the
flag stream mode is reset. More detailed loop operation
is covered later.

Transmit Frame
The Transmit Frame command simply transmits a
frame. Four parameters are required when Buffered
mode is selected and two when it is not. In either case,
the first two parameters are the least and the most significant bytes of the desired frame length (Lo, Ll)' In
Buffered mode, Lo and Ll equal the length in bytes of
the desired information field, while in the non-Buffered
mode, Lo and L[ must be specified at the information
field length plus tWo. (Lo and Ll specify the number of
data transfers to be performed.) In Buffered mode, the
address and control fields are presented to the transmitter as the third and fourth parameters respectively. In
non-Buffered mode, the A and C fields must be passed
as the first two data transfers.

Transmit Transparent
The Transmit Transparent command enables the 8273
to transmit a block of raw data. This data is without
SDLC protocol, i.e., no zero bit insertion, flags, or'
FCS. Thus it is possible to construct and transmit a BiSync message for front-end processor switching or to
construct and transmit an SDLC message with incorrect FCS for diagnostic purposes, Only the Lo and Ll
parameters are used since there are not fields in this
mode. (The 8273 does not support a Receive Transparent command.)

Abort Commands
When the Transmit Frame command is issued, the
8273 makes RTS (Request-to-Send) active (pin low) if
it was not already. It then waits until CTS (Clear-toSend) goes active (pin low) before starting the frame. If
the Preframe Sync bit in the Operating Mode register is
set, the transmitter prefaces two characters (16 transitions) before the opening flag. If the Flag Stream bit is
set in the Operating Mode register, the frame (including
Preframe Sync if selected) is started on a flag boundary.
Otherwise the frame starts on a character boundary.
At the end of the frame, the transmitter interrupts the
CPU (the interrupt results are discussed shortly) and

Each of the above transmit commands has an associated Abort command. The Abort Frame Transmit command causes the transmitter to send eight contiguous
ones (no zero bit insertion) immediately and then revert
to either idle or flag streaming based on the Flag
Stream bit. (The'8 Is as an Abort character is compatible with both SDLC and HDLC.)
For Loop Transmit, the Abort Loop Transmit command causes the transmitter to send one flag and then
revert toone bit delay. Loop protocol depends upon
FCS errors to detect aborted frames.

2-317

inter

AP-36

The Abort Transmit Transparent simply causes the
transmitter to revert to either idles or flags as a function of the Flag Stream mode specified.

support intraframe time fill, if the DMA controller or
CPU does not supply the data in time, the frame must
be aborted. The action taken by the transmitter on this
error is automatic. It aborts the frame just as if an
Abort command had been issued.

The Abort commands require no parameters, however,
they do generate an interrupt and return a result when
complete.
.

Clear-to-Send Error result is generated if CTS goes inactive during a frame transmission. The frame is aborted as above.

A summary of the Transmit commands is shown in
Figure 31. Figure 32 shows the various transmit interrupt result codes. As in the receiver operation, the
transmitter generates interrupts based on either good
completion of an operation or an error condition to
start the Result phase.

The Abort Complete result is self-explanatory. Please
note however that no Abort Complete interrupt is generated when an automatic abort occurs. The.next command type consists of only one command.

The Early Transmit Interrupt result occurs after the
last data transfer to the 8273 if the Early Transmit Interrupt bit is set in the Operating Mode register. If the
8273 is commanded to transmit again within two character times, a single flag will separate the frames. (Buffered mode must be used for a single flag to separate the
frames. If non-Buffered mode is selected, three flags
will separate the frames.) If this time constraint is not
met, another interrupt is generated and multiple flags
or idl,es will separate the frames. The second interrupt
is the normal Frame Transmit Complete interrupt. The
Frame Transmit Complete result occurs at the closing
flag to signify a good completion.

Reset Command
The Reset command provides a software reset function
for the 8273, It is a special case and does not utilize the
normal command interface. The. reset facility is provided in the Test Mode register. The 8273 is reset by simply outputting aOIH followed by a OOH to the Test
Mode register. Writing the OJ followed by the 00 mimicks the action required by the hardware reset. Since
the 8273 requires time to process the reset internally, at
least 10 cycles of the CLK clock must occur between
the writing of the 01 and the 00. The action taken is the
same as if a hardware reset is performed, namely:
I) The modem control outputs are forced high inactive.

The DMA Underrun result is analogous to the DMA
Overrun result in the receiver. Since SDLC does not

Results
TxllR

Hex
Code

Parameters'

Transmit Frame
Abort

C8
CC

La, L1, A, C
None

TIC ,
TIC

Loop Transmit
Abort

CA
CE

La, L1, A, C
None

TIC
TIC

Transmit Transparent
Abort

CO
CD

La, L1
None

TIC
TIC

Command

'NOTE:
A and C are passed as parameters in buffered mode only.

Figure 31. Transmitter Command Summary
Transmitter Interrupt
Result Code

RIC
D7- Da

00001100
00001101
00001110
00001111
00010000

Early Tx Interrupt
Frame Tx Complete
DMAUnderrun
Clear to Send Error
Abort Complete

Tx Status
after INT
Active
Idle or Flags
Abort
Abort
Idle or Flags

Figure 32. Transmitter Interrupt Result Codes

2-318

inter

AP-36

2) The 8273 Status register is cleared.
3) Any commands in progress cease.
4) The 8273 enters an idle state until the next command
is issued.

If non-Buffered mode is used, the A, C, and I fields are
in memory. The software must examine the initial characters to find the extent of the address field. If Buffered
mode is used, the characters corresponding to the
SOLC A and C fields are transferred to the CPU as
interrupt results. Buffered mode assumes the two characters following the opening flag are to be transferred
as interrupt results regardless of content or meaning.
(The 8273 does not know whether it is being used in an
SOLC or an HOLC environment.) In SOLC, these
characters are necessarily the A and C field bytes, however in HOLC, their meaning may change depending
on the amount of extension used. The software must
recognize this and examine the transferred results as
possible address field extensions.

Modem Control Commands
The modem control ports were discussed earlier in the
Hardware section. The commands used to manipulate
these ports are shown in Figure 33. The Read Port A
and Read Port B commands are immediate. The bit
definition for the returned byte is shown in Figures 13
and 14.00 not forget that the returned value represents
the logical condition of the pin, i.e., pin active (low) =
bit set.

Frames may still be selectively received as is needed for
secondary stations. The Selective Receive command is
still used. This command qualifies a frame reception on
the first byte following the opening flag matching either
of the A 1 or A2 match byte parameters. While this does
not allow qualification over the complete range of
HOLC addresses, it does perform a qualification on the
first address byte. The remaining address field bytes, if
any, are then examined via software to completely qualify the frame.

The Set and Reset Port B commands are similar to the
Initialization commands in that they use a mask parameter which defines the bits to be changed. Set Port
B utilizes a logical OR mask and Reset Port B uses a
logical ANO mask. Setting a bit makes the pin active
(low). Resetting the bit deactivates the pin (high).
To help clarify the numerous timing relationships that
occur and their consequences, Figures 34 and 35 are
provided as an illustration of several typical se~uences.
IUs suggested that the reader go over these diagrams
and re-read the appropriate part of the previous sections if necessary.

Once the extent of the address field is found, the following bytes form the control field. The same LSB test
used for the address field is applied to these bytes to
determine the control field extension, up to two bytes
maximum. The remaining frame bytes in memory represent the information field.

HDLC CONSIDERATIONS
The 8273 supports HOLC as well as SOLC. Let's discuss how the 8273 handles the three basic HOLC/
SOLC differences: extended addressing, extended control, and the 7 Is Abort character.
Recalling Figure 4a, HOLC supports an address fi~ld
of indefinite length. The actual amount of extensIOn
used is determined by the least significant bit of the
characters immediately following the opening flag. If
the LSB is 0, more address field bytes follow. If the
LSB is 1, this byte is the final address field byte. Software must be used to determine this extension.

Port
A Input

B Output

The Abort character difference is handled in the Operating Mode register. If the HOLe Abort Enable bi~ is
set, the reception of seven contiguous ones by an actIve
receiver will generate an Abort Oetect interrupt rather
than eight ones. (Note that both the HOLC Abort Enable bit and the EOP Interrupt bit must not be set
simultaneously. )
Now let's move on to the SOLe loop configuration
discussion.

Command

Hex
Code

Read

None

Port Value

Read

None

Port Value

Set

Set Mask

None

Reset

Reset Mask

None

Parameter

Figure 33. Modem Control Command Summary

2-319

Reg
Result

Ap·36

CARRIER DETECT

\'---

RxD

Rx COMMAND

OR~~~:~~~~~~~~~ __________________________________~~_A
____~t_c____~t~11______________________
NON·BUFFERED

FRAME

POSSIBLE

IN~~~~~~i~ __________~_________________________M
__
O_DE
____________~~C~O~M~P=LE~T~E~__~ID~L~E~I~NT

6tl001-25
A. Error-Free Frame Reception

CARRIER DETECT

\\\\\\\\\\\\

RxD

Rx COMMAND

.IN~~~~~~~~ ________...,.________~F..A..I.;..LU..R..E~I~....__~....__~........~....____.......F..A;;.;IL;,;U..R;,;;E....___
611001-26
B. Carrier Detect Failure During Frame Reception

Figure 34_ Sample Receiver Timing Diagrams

LOOP CONFIGURATION
Aside from use in the normal data link applications, the
8273 is extremely attractive in loop configuration due
to the special frame-level loop commands and the Digital Phase Locked Loop. Toward this end, this section
details the hardware and software considerations when
using the 8273 in a loop application.
The loop configuration offers a simple, low-cost solution for systems with multiple stations within a small
physical location, i.e., retail stores and banks. There are
two primary reasons to consider a loop configuration.
The interconnect cost is lower for a loop over a multipoint configuration since only one twisted pair or fiber
optic cable is used. (The loop configuration does not
support the passing of distinct clock signals from station to station.) In addition, loop stations do not need
the intelligence of a multi-point station since the loop

protocol is simpler. The most difficult aspects of loop
station design are clock recovery and implementation
of one bit delay (both are handled.neatly by the 8273).
Figure 36 illustrates a typical loop configuration with
one controller and two down-loop secondaries. Each
station must derive its own data timing from the received data stream. Recalling our earlier discussion of
the DPLL, notice that TxC and RxC clocks are provided by the DPLL output. The only clock required in the
secondaries is a simple, non-synchronized clock at 32
times the desired baud rate. The controller requires
both 32 X and I X clocks. (The I X is usually iniplemented by dividing the 32 X clock with a S-bit divider.
However, there is no synchronism requirement between
these clocks so any convenient implementation may be
used.)

2-320

intJ

AP-36

Tx COMMAND

T,D

RTS~

CTS-----...J

1
A

1
C

1'1

1'2

oR1~~~~~~~~~~~~------I--I--,--------------------------

NON-BUFFERED

MODE

IN~~~~~~i~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,-F_R_A_M_E_C_O_M_P_L_E_TE

611001-27
A. Error-Free Frame Transmission
2ND FRAME

1ST FRAME
Tx COMMAND

I I

I II I I

RTS~
CTS~
fEARLYTX

'N~~~~~~i~--------------~--------------------611001-28

8. Diagram Showing Tx Command Queing and Early Tx Interrupt
(Single flag between frames) Buffered Mode is Assumed

Tx COMMAND

L
CTS-----...J

1 CTS

IN~~~~~~i~--------------------~O~R~A~~~:~R~O~R-------ERROR
INTERRUPT

611001-29
C. CTS Failure (or other error) During Transmission

Figure 35. Sample Transmitter Timing Diagrams
2-321

inter

AP-36

1 x LOOP
OSCILLATOR
OR
DIVIDER

If the controller wants to poll the secondaries it transmits a polling frame followed by all Is (no' zero bit
insertion). The final zero of the closing frame plus the
first seven Is form an EOP. While repeating, the secondaries monitor their incoming line for an EOP. When
an EOP is received, the secondary checks if it has any
response for the controller. If not, it simply continues
repeating. If the secondary has a response, it changes
the seventh EOP one into a zero (the one bit time ,of
delay allows time for this) and repeats it, forming a flag
for the down-loop stations. After this flag is transmitted, the secondary terminates its repeater function and
inserts its response frame (with multiple preceding flags
if necessary). Mter the closing flag of the response, the
secondary re-enters its repeater function, repeating the
up-loop controller Is. Notice that the final zero of the
response's closing flag plus the repeated Is from the
controller form a new EOP for the next down-loop sec?ndary. This new EOP allows the next secondary to
Insert a response if it desires. This gives each secondary
a chance to respond.

8273
LOOP
CONTROLLER
TxD

RxD

RxC

8273

TxC

LOOP
TxD
TERMINAL

1---+-+-'" RxD

TxC

RxC

TxD

8273
LOOP
TERMINAL

611001-30

Figure 36. SDLe Loop Application

A quick review of loop protocol is appropriate. All
communication on the loop is controlled by the loop
controller. When the controller wishes to 'allow the secondaries to transmit, it sends a polling frame (the control field contains a poll code) followed by an EOP
(End-of-Poll) character. The secondaries use the EOP
character to capture the loop and insert a response
£i·ame as will be discussed shortly.
The secondaries normally operate in the repeater mode,
retransmitting received data with one bit time of delay.
All received frames are repeated. The secondary uses
the one bit time of delay to capture the loop.
When the loop is idle (no frames), the controller transmits continuous flag characters. This keeps transitions
on the loop for the sake of down-loop phase locked
loops. When the controller has a non-polling frame to
transmit, it simply transmits the frame and continues to
send flags. The non-polling frame is then repeated
around the loop and the controller receives it to signify
a complete traversal of the lopp. At the particular secondary addressed by the frame, the data is transferred
to memory while being repeated. Other secondaries
simply repeat it.
'

Back at the controller, after the polling frame has been
transmitted and the continuous Is started, the controll~r ~aits until it receives an EOP. Receiving an EOP
sIgnifies to the controller that, the original frame has
propagated around the loop followed by any responses
mserted by the secondaries. At this point, the controller
may either send flags to idle the loop or transmit the
next frame. Let's assume that the loop is implemented
completely with the 8273s and describe the command
flows for a typical controller and secondary.
The loop controller is initialized with Commands which
specify that the NRZI, Preframe Sync, Flag Stream,
and EOP Interrupt modes are set. Thus, the controller
encodes and decodes all data using NRZI format. Preframe Sync mode specifies that all transmitted frames
be prefaced with 16 line transitions. This ensures that
the minimum of 12 transitions needed by the DPLL to
lock after an all Is line has occurred by the time the
secondary sees a frame's opening flag. Setting the Flag
~tream mode starts the transmitter sending flags which
Idles the loop. And the EOP Interrupt mode specifies
that the controller processor will be interrupted when'ever the active receiver sees an EOP, indicating the
completion of a poll cycle.
When ~he. controller wishes to transmit a non-polling
frame, It stmply executes a Frame Transmit command.
Since the Flag Stream mode is set, no EOP is formed
after the closing flag. When a polling frame is to be
transmitted, a General Receive command is executed
firs~. Thi~ enables the receiver and allows reception of
all incoming frames; namely, the original polling frame
plus any response frames inserted by the secondaries.
Mter the General Receive command, the frame is
transmitted with a Frame Transmit command. When
the frame is complete, a transmitter interrupt is gener-

2-322

inter

AP-36

ated. The loop controller processor uses this interrupt
to reset Flag Stream mode. This causes the transmitter
to start sending all Is. An EOP is formed by the last
flag and the first 7 Is. This completes the loop controller transmit sequence.
At any time following the start of the polling frame
transmission the loop controller receiver will start receiving frames. (The exact time difference depends, of
course, on the number of down-loop secondaries due to
each inserting one bit time of delay.) The first received
frame is simply the original polling frame. However,
any additional frames are those inserted by the secondaries. The loop controller processor knows all frames
have been received whIm it sees an EOP Interrupt. This
interrupt is generated by the 8273 since the EOP Internipt mode was set during initialization. At this point,
the transmitter may be commanded either to enter Flag
Stream mode, idling the loop, or to transmit the next
frame. A flowchart of this sequence is shown in Figure
37.

The secondaries are initialized with the NRZI and One
Bit Delay modes set. This puts the 8273 into the repeater mode with the transmitter repeating the received
data with one bit time of delay. Since a loop station
cannot transmit until it sees an EOP character, any
transmit command is queued until an EOP is received.
Thus whenever the secondary wishes to transmit a response, a Loop Transmit command is issued. The 8273
then waits until it receives an EOP. At this point, the
receiver changes the EOP into a flag, repeats it, resets
One Bit Delay mode stopping the repeater function,
and sets the transmitter into Flag Stream mode. This
captures the loop. The transmitter now inserts its message. At the closing flag, Flag Stream mode is reset, and
One Bit Delay mode is set, returning the 8273 to repeater function and forming an EOP for the next downloop station. These actions happen automatically after a
Loop Transmit command is issued.
When the secondary wants its receiver enabled, a Selective Loop Receive command is issued~ The receiver
then looks for a frame having a match in the Address
field. Once such a frame is received, repeated, and
transferred to memory, the secondary's processor is interrupted with the appropriate Match interrupt result
and the 8273 continues with the repeater function until
an EOP is received, at which point the loop is captured
as above. The processor should use the interrupt to determine ir'it has a message for the controller. If it does,
it simply issues a Loop Transmit command and things
progress as above. If the processor has no message, the
software must reset the Flag Strel!m mode bit in the
Operating Mode register. This will inhibit the 8273
from capturing the loop at the EOP. (The match frame
and the EOP may be separated· in time by several
frames depending on how· many up-loop stations insert. ed messages of their own.) If the timing is such that the
receiver has already captured the loop when the Flag
Stream mode bit is reset, the mode is exited on a flag
boundary and the frame just appears to have extra closing flags before the EOP. Notice that the 8273 handles
the queuing of the transmit commands and the setting
and resetting of the mode bits automatically. Figure 38
illustrates the major points of the secondary command
sequence.

DENOTES COMMANO

c:::) DENOTES INTERRUPT CODE
611001-31

Figure 37_ Loop Controller Flowchart

2-323

AP-36

It is hopefully evident from the above discussion that
the 8273 offers a very simple and easy to implement
solution for designing loop stations whether they are
controllers or down-loop secondaries.

INITIALIZE SET NRZI, ONE
BIT DElAY MODES

A'Df------~~-----UP.lOOP DATA
8273

DOWN·lOOP DATA
hD

1---'---1-----1,

POAT I----~_I

611001-33

Figure 39. Loop Interface

APPLICATION EXAMPLE

DENOTES COMMANDS

<==) CENOTES INTERRUPT CODES
611001-32

Figure 3S. Loop Secondary Flowchart

When an off-line secondary wishes to come on-line, it
must do so in a manner which does not disturb data on
the loop. Figure 39 shows a typical hardware interface.
The line labeled Port could be one of the 8273 Port B
outputs and is assumed to be high (1) initially. Thus uploop data is simply passed down-loop with no delay;
however, the receiver may still monitor data on the
loop. To come on-line, the secondary is initialized with
only the EOP Interrupt ,mode set. The up-loop data is
then monitored until an EOP occurs, At this point, the
secondary's CPU is interrupted with an EOP interrupt.
This signals the CPU to set One Bit Delay mode in the
8273 and then to set Port iow (active). These actions
switch the secondary's one bit delay into the loop. Since
after the EOP only Is are traversing the loop, no loop
disturbance occurs. The secondary now waits for the
next EOP, captures the loop, and inserts a "new online" message. This signals the controller that a new
secondary exists and must be acknowledged. After the
secondary receives its ackno'Xledgement, the normal
command flow is used.

This section describes tlie hardware and software of the
8273/8085 system used to verify the 8273 implementation of SDLC on an actual IBM SDLC Link. This IBM
link was gratefully volunteered by Raytheon Data Systems in Norwood, Mass. and I wish to thank them for
their generous cooperation. The IBM system consisted
of a 370 Mainframe, a 3705 Communications Processor, and a 3271 Terminal Controller. A Comlink II
Modem supplied the modem interface and all communications took place at 4800 baud. In addition to observing correct responses, a Spectron D60 1B Datascope
was used to verify the data exchanges. A block diagram
of the system is shown in Figure 40. The actual verification was accomplished by the 8273 system receiving
and responding to polls from the 3705. This method
was used on both point-to-point and multi-point configurations. No attempt was made to implement any higher protocol software over that of the' poll and poll
responses since such software would not affect the verification of the 8273 implementation. As testimony to
the ease of use of the 8273, the system worked on the
first try.

37.

3705

MAINFRAME

COMM.
PROCESSOR

611001-34

Figure 40. Raytheon Block Diagram

An SDK-85 (System Design Kit) was used as the core
8085 system. This system provides up to 4K bytes of
ROM/EPROM, 512 bytes of RAM, 76 I/O pins, plus

2-324

intJ

AP-36

plus miscellaneous variables are stored in the 8155s.)
The RS-232 interface utilized MC1488 and MC1489
RS-232 drivers and receivers. The schematic of the system is shown in Figure 42.

two timers as provided in two 8755 Combination
EPROM/I/O devices and two 8155 Combination
RAM/I/O/Timer devices. In addition, 5 interrupt inputs are supplied on the 8085. The address, data, and
control buses are buffered by the 8212 and 8216 latches
and bidirectional bus drivers. Although it was not used
in this application, an 8279 Display Driver/Keyboard
Encoder is included to interface the on-board display
and keyboard. A block diagram of the SDK-85 is
shown in Figure 41. The 8273 and associated circuitry
was constructed on the ample wire-wrap area provided
for the user.
The example 8237/8085 system is interrupt-driven and
uses DMA for all data transfers supervised by an 8257
DMA Controller. A 2400 baud asynchronous line, implemented with an 8251A USART, provides communication between the software and the user. 8253 Programmable Interval Timer is used to supply the baud
rate clocks for the 8251A and 8273. (The 8273 baud
rate clocks were used only during initial system debug.
In actual operation, the modem supplied these clocks
via the RS-232 interface.) Two 2142 lK x 4 RAMs
provided 512 bytes of transmitter and 512 bytes of receiver buffer memory. (Command and result buffers,

One detail to note is the DMA and interrupt structure
of the transmit and receive channels. In both cases, the
receiver is always given the higher priority (8257 DMA
channel 0 has priority over the remaining channels and
the 8085 RST 7.5 interrupt input has priority over the
RST 6.5 input.) Although the choice is arbitrary, this
technique minimizes the chance that received data
could be lost due to other processor or DMA commitments.
Also note that only one 8205 Decoder is used for both
peripheral and memory Chip Select. This was done to
eliminate separate memory and I/O decoders since it
was known beforehand that neither address space
would be completely filled.
The 4 MHz crystal and 8224 Clock Generator were
used only to verify that the 8273 operates correctly at
that maximum spec speed. In a normal system, the
3.072 MHz clock from the 8085 would be sufficient.
(This fact was verified during initial checkout.)

2-325

ADDRESS

CPU

DECODER

"OMIIO (13551
EPAOMIIO (4755)

RAMIIO/COUNTER

(

FOR BUS EXPANSION

KEYBOARD DISPLAY
ADDRESS

DATA

FIELD

FiElD

"'11

iQ'
e::

....
""'
Ul

DATA

BUS

en
I\)

I\)
(1)

"'11

e::

:::s

"0
I

0'
!!!.

!l
:::s

()

""o

iii'

iil
3

(0)

1
1 lJkU~~4ffF=r ~::J)
.
:
~
R
E
S
~
r r

[: = ~l:JlJlJ: : l1: :~: : ~1:=1=l: =i: : : : : =r=r: =f: : : : : : J:_~=r=r: : : : r=: : ,
!

CONTROL

BUS

r----,

L __ ...J

,----,

L __ ..JI
8212

'--l~.
~BUS

CONTROL

"821.

L __ .J

OPTIONAL. A PLACE HAS BEEN PROVIDED ON THE PC BOARD FOA THE DEVICE BUT THE
DEVICE IS NOT INCLUDED.

611001 ~35

(

m
1K

iffiJ---

@
10

745257

B3
'A3
A4

INR

"T1

...

101M

07-00

0211

9
04 12

M£MR

------

10_"_-+__

M
E M w r - _ l
lOW

SEl

iD"
e:

01~

OATA BUS

_______ _

..,.
(1)

~
0)

N
I\)

......

I\)

5DK·85

BUS

07-00

c.:, .....

-..J

Cj'

C
~
0)
en

HRO

611llDRO

hDACK
~~4
5~

DAGKl

,: HLDA 8257

VJ
'<

RESET

AEN

8213

8253

L11

I f4E2
"BUS

07-00 WR RD

D 1" }" r:

J:..

TxCP!-

~RESET

.205

U"l L

...2.!.

~OClK

8251A

~Cs

1
AlS

R.C~

TO~1 TO CAT

A"O~

Ao1'2
CID

"tI
I
Q)

ADSTS

_'4

r: f

GATE2

1--~~IJlg
+5,. I.
13

::1:: 1

GATEO

cs~

2 1eLK
f------"O-t

QUl2

RIlDACK

I·~

;r:.

07-00 WARD

,1B IRxORQ
__

'---------

611001-36

AP-3S'

The software consists of the normal monitor program
supplied with the SDK-85 and a program to input commands to the 8273 and to display results. The SDK-85
monitor allows the user to read and write on-board
RAM, start execution at any memory location, to single-step through a program, and to examine any of the
8085's internal registers. The monitor drives either the
on-board keyboard/LED display or a serial TTY interface. This monitor was modified slightly in order to use
the 8251A with a 2400 baud CRT as opposed to the
110 baud normally used. The 8273 program implements monitor-like user interface. 8273 commands are
. entered by a two-character code followed by any parameters required by that command. When 8273 interrupts occur, the source of the interrupt is displayed
along with any results associated with it. To gain a
flavor of how the user/program interface operates, a
sample output is shown in Figure 43. The 8273 program prompt character is a "-" and user inputs are
underlined.

8273 MONITOR V1.2
SO 05
~
OR 00 01
TF C2 11 00 11 22
TxlNT

RxlNT FF EE DO

00 00 00 00 00
EO 03 00 C2 34
611001-63

Figure 43. Sample 8273 Monitor 1/0

The "SO 05" implements the Set Operating Mode command with a parameter of 05H. This sets the Buffer and
Flag Stream modes. "SS 01" sets the 8273 in NRZI
mode using the Set Serial I/O Mode command. The
next command specifies General Receiver with a receiver'buffer size of 0100H bytes (Bo = 00, BI = 01).
The "TF" command causes the 8273 to transmit a
frame containing an address field of C2H and control
field of 11H. The information field is 001122. The
"TF" command has a special format. The Lo and LI
parameters are computed from the number of information field bytes entered.
After the TF command is entered, the 8273 transmits
the frame (assuming that the Ipodem protocol is observed). After the closing flag, the 8273 interrupts the
8085. The 8085 reads the interrupt results and places
them in a buffer. The software examines this buffer for
new results and if new results exist, the source of the
interrupt is displayed along with the results.
In this example, the ODH result indicates a Frame
Complete interrupt. There is onJyone result for a transmitter interrupt, the interrupt's trailing Zero results
were included to simplify programming.
The next event is a frame reception. The interrupt results are displayed in the order read from the 8273. The
EOH indicates a General Receive interrupt with the last
byte of the information field received on an 8-bit
boundary. The 03 00 (Ro, RI) results show that there
are 3H bytes of information field received. The remaining two results indicate that the received frame had a
C2Haddress field and a 34H control field. The 3 bytes
of information field are displayed on the next line.

Figures 44 through 51 show the flowcharts used for the
8273 program development. The actual program listing
is included as Appendix A. Figure 44 is the main status
poll loop. After all devices are initialized and a prompt
character displayed, a loop is entered at LOOPIT. This
loop checks for a change of status in the result buffer or
if a keyboard character has been received by the 8251
or if a poll frame has been received. If any of these
conditions are met, the program branches to the appropriate routine. Otherwise, the loop is traversed again.
The result buffer is implemented as a 255-byte circular
buffer with two pointers: CNADR and LDADR.
CNADR is the console pointer. It points to the next
result to be displayed. LDADR is the load pointer. It
points to the next empty position in the buffer into
which the interrupt handler places the next result. The
same buffer is used for both transmitter and receiver
results. LOOPIT examines these pointers to detect
when CNADR is not equal to LDADR indicating that
the buffer contains results which have not been displayed. When this occurs, the program branches to the
DISPLY routine.
DISPLY determines the source of the undisplayed re. suIts by testing the first result. This first result is 'not
necessarily the interrupt result code. If this result is
OCH or greater, the result is from a transmitter interrupt. Otherwise it is from a receiver source. The source
of the result code is then displayed on the console along
with the next four results from the buffer. If the source
was a transmitter interrupt, the routine merely repoints
the pointer CNADR and returns to LOOPIT. For a
receiver source, the receiver data buffer is displayed in
addition to the receiver interrupt results before returning to LOOPIT.

2-328

AP-36

START

CMDREC

lOOPIT

611001-37

611001-39

Figure 44. Main Status Poll Loop

Figure 46. GETCMD Subroutine

611001-40

Figure 47. TF Subroutine

611001-38

Figure 45. DISPLY Subroutine
2-329

intJ

AP-36

If the result buffer pointers indicate an empty buffer,
the 825lA is polled for a keyboard character. If the
8251 has a character, GETCMD is called. There the
character is read and checked if legal. Illegal characters
simply cause a reprompt. Legal characters indicate the
start of a command input. Most commands are organized as two characters signifying the command action;
i.e., GR-General Receive. The software recognizes the
two character command code and takes the appropriate
action. For non-Transmit type commands, the hex
equivalent of the command is placed in the C register
and the number of parameters associated with that
command is placed in the B register. The program then
branches to the COMM routine.

611001-41

Figure 48. TxPOL Subroutine

The COMM routine builds the command buffer by
reading the required number of parameters from the
keyboard and placing them at the buffer pointed at by
CMDBUF. The routine at COMM2 then issues this
command buffer to the 827~.

PARAMETER #2
PARAMETER #1
COMMAND

-_I '

OF PARAMETERS

611001-42

Figure 49. COMM Subroutine with
Command Buffer Format

EXIT TO
MONITOA

If a Transmit type command is specified, the command
. buffer is set up similarly to the COMM routine; however, since the information field data is entered from the
keyboard, an intermediate routine, TF, is called. TF
loads the transmit data buffer pointed at by TxBUF. It
counts the number of data bytes entered and loads this
number into the command buffer as Lo, L\. The command is then issued to the 8273 by jumping to
CMDOUT.

One command does not directly result in a command
being issued to the 8273. This command, Z, operates a
software flip-flop which selects whether the software
will respond automatically to received polling frames.
If the Poll-Response mode is selected, the prompt character is changed to a '+'. If a frame is received which
contains a prearranged poll control field, the memory
location POLIN is made nonzero by the receiver interrupt handler. LOOPIT examines this location and if it
is nonzero, causes a branch to the TxPOL routine. The
TxPOL routine clears POLIN, sets a pointer to a special command buffer at CMDBUFl, and issues the
command by way of the COMM2 entry in the COMM
routine. The special command buffer contains the appropriate response frame for the poll frame received.
These actions only occur when the Z command has
changed the prompt to a '+ '. If the prompt is normal
'-', polling frames are displayed as normal frames and
no response is transmitted. The Poll-Response mode
was used during the IBM tests.

611001-43

Figure 50. Txl (Transmitter Interrupt) Routine

2-330

intJ

Ap·36

The final two software routines are the transmitter and
receiver interrupt handlers. The transmit interrupt handler, TxI, simply saves the registers on the stack and
checks if loading the result buffer will fill it. If the result buffer will overfill, the program is exited and control is passed to the SDK-85 monitor. If not, the results
are read from the TxllR register and placed in the
result buffer at LDADR. The DMA pointers are then
reset, the registers restored, and interrupts enabled. Execution then returns to the pre-interrupt location.

CHECK IF RESULTS
WILL FILL RESULT
BUFFER

~EXITTO
. MONITOR

READ RESULTS AND
PLACE IN RESULT
BUFFER

The receiver interrupt handler, RxI, is only slightly
more complex. As in TxI, the registers are saved and
the possibility of overfilling the result buffer is examined. If the result buffer is not full, the results are read
from RxllR and placed in the buffer. At this point the
prompt character is examined to see if the Poll-Response mode is selected. If so, the control field is compared with two possible polling control fields. If there is
a match, the special command buffer is loaded and the
poll indicator, POLIN, is made nonzero. If no match
occurred, no action is taken. Finally, the receiver DMA
buffer pointers are reset, the processor status restored,
and interrupts are enabled. The RET instruction returns execution to the pre-interrupt location.
This completes the discussion of the 8273/8085 system
design.

CONCLUSION
This application note has covered the 8273 in some detail. The simple and low cost loop configuration was
explored and an 8273/8085 system was presented as a
sample design illustrating the DMA/interrupt-driven
interface. It is hoped that the major features of the
8273, namely the frame-level command structure and
the Digital Phase Locked Loop, have been shown to be
a valuable asset in an SDLC system design.

611001-44

Figure 51. Rxl (Receiver Interrupt) Routine

2-331

AP-36

APPENDIX A

R5MS8 : F1 : RRl'T73. SRC
ISIS- Il 8889iS9S5 MACRO ASSEIIBlER, X19S
LOC OSJ

SEQ

MODULE

PAGE

SO\EE STATB'ENT

1 mJPAGll«l PIOO85 NOCOND
2 TRUE

EQIJ

88 FOR RRl'TI£ON
FF FOR SELF-TEST
ee FOR NORR RESPONSE
FF FOR LOOP RESPONSE
ee FOR NIl DOO
FF FOR DEft)

eeH

3;
4 TRUE1

EIlU

S;
EQIJ
6DEH
7;
S;
9;
19 I GENERAL 8273 MONITOR WITH RAI'THEDN POLl I'IOOE ADDED
111
17 ;

18
. 19
28
21
22

COIIIRID SUPPORTED ARE: RS
SS
RO
I
50
23 I
RD
24 ;
GR
2S
26
27
28
29
39
31
32
33

;
;

;
I

;
I
I

;
;
;
;

5R TF AF -

SP RP RB 58 -

RESET SERIRL It'O PIODE
SET SERIAL It'O I'IOOE
RE..G:T OPERATlI«l HODE
SET OPERATING I100E
RECEIVER DISA8LE
GENERAL RECEIVE
SELECTIVE RECEIVE
TRANSMIT FRAI1E
ABORT FRAIIE
SET PORT B
RESET PORT B
RESET 8NE BIT DELAY (P~ = 7F)
SET ONE BIT DELA\' (PAR = Be)
SELECTIVE LOOP RECEIVE
TRAN5I11T LOOP
CHANGE PIOOES FLIPIFLOP

SL TL 34 I
Z 3B I
39 i *****************************************.****...**********.....***..........
49;
41 I NOTE: 'SET' COIII1ANDS IHPLEllENT LOGICAL 'OR' Fl.N:TlONS
42 ;
'RESET' COI1ItfINI)S INFlEItENT LOGICAL 'AND' FlKTlONS
43 ;
44 i **•••************.***.**•••*********.*******...........................**********
4S ;
46 ; BUFFERED "ODE "JST BE SELECTED WI£N SELECTIVE RECEIVE 15 USED.
47 ;
48 I COMMAND FORmT IS:'CIlltlflN[) (2 LTRS)' 'PAR. H' '1'flR. '2' ETC.
49 ;
59 ; TI£ TRANSMIT FRAIIE ComN) FORMAT 15: 'TF' 'A' 'C' 'BlfFER CDNTEHTS'.
S1 ;
NO LENGTH CCUIT IS NEEDED. BlfFER CONTENTS 15 EII>ED WITH R CR

52;
53 ; ........*************.*********************.*****************

54;

55 lPOLLED 11OOE:

IIIiEN POlLED

-"00£

.........

IS SELECTED (DENOTED BY A '+' PROIf'T), IF
611001-45

2-332

inter

AP-36

56
57
62

ea9Il
Bege
ee91
ee91
B092
Be93
0092
0020
BBB4
BBB8
eBBl
BBB2

BB9B

OO9C
0090

OO9E
eBBC
0036
eBB6
2017
2918

BBA8
BBAe
0eAl
B9A2
BBA3
B9A8

B2BB
BBB0
ee62
41FF
ee63
8B61
81FF

A SNRM-P OR RR(8)-P IS RECEI'IED, A RESPONSE FRAIE If" NSA-f
OR RR(B)-f IS TRAHSI1ITTED. OTHER COI'MIOS CfERATE HOORLV.

63 .; *************************.******************.*~*****..********************
64;
65 ; 8273 EQUlHES
66 ;
; STATUS REGISTER
67 STAT73 EIlU
91lH
; COIWH) REGISTER
68 COt1II73 EaU
9IlH
; PARfI£TER REGISTER
69 PARM73 Eau
91H
; RESULT REGISTER
91H
78 RESL73 EQU
; TX INTERRUPT RESULT REGISTER
71 TXIP73 EQU
92H
; RX INTERRUPT RESlLT REGISTER
72 RXIR73 EQU
91H
; TEST ItODE REGISTER
9211
73 TESm EQU
; PARAIIETER BUFFER FIll BIT
74 CP8F
EIlU
20H
; IX INTERRUPT BIT IN STATUS REGISTER
75 TXINT EIlU
B4H
; RX INTERRUPT BIT IN STATUS REGISTER
76 RXINT Eau
asH
; IX INT RESUlT AVA!lflllE BIT
77 IXIRA EaU
8lH
; RX INT RESULT AVAILABLE BIT
78 RXIRA EQU
B211
79 ;
88 ; 8253 EIlUATES
81 ;
.: 8253 ItODE I«JRI) REGISTER
82 11OOE53 Eau
9BH
; CrulTER 8 REGISTER
83 CNT853 EIlU
9CH
; COUNTER 1 REGISTER
B4 CNTi53 EaU
90Ii
; COUNTER 2 REGISTER
85 CNT253 EQU
9£H
; CONSOLE BAUD RATE (2400)
EQU
86 COBR
BBBCH
; MOOE FOR COOHTER 9
87 IIDCNTB EQU
36H
; MODE FOR COUNTER 2
88 MDCNT2 EQU
1lB6H
; 8273 BAUD RATE lSB AOR
89 lKBRl EQU
2017H
; 8273 BAUI) RATE ItS8 AOR
98 lKBR2 EIlU
2818H
91 ;
92 ; BAUD RATE TAIllE:
BAUD RATE
lKBRl lKBR2
93 ;
*********
94;
2E
00
9600
95;
5C
00
48BB
00
96 .:
2400
89
97 ;
1200
72
91
98;
B2
600
E5
99;
300
C9
95
100 .:
181;
182 .: 8257 EQUATES
183 ;
104 MOCoE57 EQU
; 8257 I100E PORT
BASH
; CHB (RX) ffiR REGISTER
185 CHBADR EQU
IlAIlH
; CHe TERMINAL COlIIIT REGISTER
BA1H
186 CHBTC EQU
.: CHi (TX) ffiR REGISTER
187 CH1AOR EaU
eA2H
; CH1 TERllIIR COUNT REGISTER
eA3H
188 CHHC Eau
; STATUS REGISTER
109 STATS7 EQU
BASH
.: RX BUFFER START fIJORE5S
U8 R'..:BUF EQU
82eeH
; f:i BUFFER START fIlDR£SS
Ul TXBUF Eau
88BBH
; DISAilLE RX DIIA ctfHa, TX STILL ON
U2 DRDMA EQU
6211
EQU
; TERMINAL COUNT fVlI) HOllE FOR RX CIIIH£l.
113 RXTC
41FFH
; EIflBLE BOrH IX IN) RX Ctm£LS-EXT. WR. IX STCf
114 ENCIIA Eau
63H
; DISABLE IX I)I'/l CIilNHEL RX STill ON
US DTDMA EOO
6lH
.: TERMINAL COUNT Ali) PIOO£ FOR TX CIIIH£l.
81FFH
116 mc
EIlU
117 ;

..- _.

611001-46

2-333

intJ

Ap·36

118 ,8251A EIlUATES

119 ,
9889
9889

8088
8988

eecE
8827
8882

861F
85F8
875£
85BB
85E8
86C7

28C8
8883
9IlIl8

2989
2828
8000
888A
20D4
28CE
2810
2913

2088
8093
0811

0873
0811
2015
2916
2027

128 eNTL51 EIlU
Il9H
121 STRT51 EIlU
89H
88H
122 0051 EIlU
123 RXD51 EIlU
s8H
124 MOE51 EIlU
8CEH
27H
125 0051 EIlU
126 ROY
E!lJ
82H
127 ,
128 ; PIONITOR SU8ROUTlI£ E!lJATES
129 ;
138 GETCH E!lJ
861FH
131 ECHO
E!lJ
85FSH
132 I/fl.DG EIlU
87SEH
13JCN'I8N EIlU
95B8H
134CRlF
85EBH
EIlU
135 If!OUT EQU
86C7H
136 ;
137 ,"ISC EQUATES
138;
139 STJ.i C!f/
,ECHO IT
SETUP FOR COIf'ARE
O?
ROC!lIIfH)
5?
RSCOIIIRI)
D?
RO CC41IIHl
P?

mMI)

R?
START OYER
B?
RB CC41IIHl

2-336

611001-49

inter

AP·36

001)4 C3A7OO

88!>7
0BDA
BBDD
BSOE
WE8
BS8
B8E5
B8E8
BSEA
B8ED
B8EF
saF2
saF4
B8F7
saF9
saFC

FE52
CflBA89
FE5B
CAE289
FE42
CAB599
FE4C
CASfB9
C3A788

B8FF
8982
B9B5
99B6
8908
B9BB

CD1F96
CDFOO5
7B
FE52
CAC499
GA78B

B98£
8911
9914
8915
8917
B91A
B91C
891F

CD1F86
CDF885
7B
FE46
CAEC99
FE4C
CA99B9
C3A788

8922
8925
B928
8929
892B
B92E

CD1FB6
CDFOO5
7B
FE46
CACEB9
C3A788

9931
8932
8935
B937
893A
B93C
893F
8948
9943
8945
9948
8949

CD1F96
CDf895
78
FE4F
CAA6Il9
FE53

Cff38e9

F3
3A1528
FE2D
C24389
3E2B
321528
FB
C35788
3E2D
321528
FB
Cmoo

311
312
313 SOlIN:
314
315
316
317
31B
319
32B
321
322
323
324
325

326
327
328
329
33B GOWN:

332

334
335
336
337
338
339
349
341
342
343
344
345
346
347
348
349
359
351
352
353

TOWN:

ADWN.

JI'I'

ILLEG

; ILLEGfL TRY AGAIN

CALL
CIU
lID'!
CPI
JZ
CPI
1Z
CPI
JZ
CPI
1Z
CPI
JZ
CPI
JZ
JI'I'

GETCH
ECHO

; GET NEXT CHR
;EOO IT
;5£TUP FOR ~
;0'
; SO COIIflN)
;S'
; 5S COIMI)
;R?

A, B
'0'
SOCI'D
'S'
5SOO
'R'

SRCI'D

;5R

'P'
SPCI'I)
'B'
SBC!ll
'L'
5LCII>
ILLEG

;P'
; SP CImlN!)
;B'
;58 ·COIII1AfI)
;L?
; 5L COItIIH)
,ILLEGfL TRY AGAIN

COIftH)

; GET NEXT CHR

CALL
CALL
MOY
CPI
12
1i'1P

GETCH
ECHO
A,B
'R'
GROt)
ILLEG

CALL
CALL
HOY
CPI
JZ
CPI
JZ
JIt'

(lETCH
ECHO

T
TFCI'Il
'L'
TLCtI)
ILLEG

; GET NEXT CHR
;ECHO IT
; SETUP FOR COI'I'ARE
;F'
;TFCIJIt!ANO
; L'
; TL CQ1l1ff;I)
,ILLE(R, TRY AGAIN

CAlL
CAlL

(lETCH
ECHO
A· B
'F'
AFCI!I)
ILlEG

; GET NEXT CHR
; ECHO IT
; SETUP FOR COI'I'ARE
; F?
; AF COIt1fN)
; IllEGAl., TRY AGAIN

~OY

CPI
JZ
JIt'

A,B

; ECHO IT
; SETUP FOR CilI'I'iRE

iR?
;GP.C~

; ILLEGfL TRY AGAIN

;
; RE5£T POLl MODE RESPONSE - CHRHGE PROIf'T CHR AS IIIHCATOR

354 ;
355 C/tOOE: DI
356
357
359
359
368
365
366
367SW:
368
369
378
371 ;
372 ;

LDA
CPI
JHZ
MYI
STA
EI
JIt'
rtIII

PRI'I'T
SW
A, '.'
PRI'I'T

5TH

CIlOREC
A '-'
PRI1PT

EI
JI1P

CltDREC

; DISABlE INTERRUPTS
; GET ~T PROIf'T
; NORI'itl. 1tJOE?
; NO, CHIflGE IT
; NEW PROI'I'T
; STORE IEII I'R!WIPT
; ENABLE INTERru'TS
; RETURN TO LCKP
;!£II PROI'I'T CHR
; STORE IT
; ElfIIIlE INTERRUPTS
; RETURN TO LCKP

611001-50 .

2-337

inter

AP-36

lEOO

994C
894E
0951
9954
0955
8957
095A

212929
CHeA

995D
895F
9961
8964

9681
81:51
CDE59A
C35798

9967
9969
996B
996E

9681
eE69
CGE59fI
C35798

8971
8973
9975
8978

9688
eEC5
CGE59A
C3S798

8978
897D
.897F
8982

9691
eE64
COE59A
C35798

321628
216108
E5

06e4

i TRAHSltIT AHSWEF TO POll SETUP
374 i
382 TXPOL: "VI
A. 1I8I!
i CLEAR POLL I1')ICAT~
384
STA
POliN
i lNOICAT~ fllR
385
lXI
H, lOOPIT
.' SETlJ' STACK FIlR wtIfN) OOTPUT
386
PUSH H
i PIJT REMN TO Clt)l!EC ON STfI)(
387
B,04H
i GET • OF PARItETERS REAJY
"VI
388
LXI
H,OOBF1
i POINT TO SPECIAL BUFFER
C(I!IQ
389
JItP
i JUI!P TO CMIN) OUTPUTER
390 i
391;
392 i
J93 i ClltII1ANI) IIWillIENTING ROIJTINES
394 i
395 i
396 i RO - RESET OPERATING 1100£
397 i
390 ROCI1D: PIIII
B,01H
i' OF PARAI£1ER5
,COI9R()
C,51H
399
PIIII
,(E PARMTERS All) ISSUE ())fR()
499
CALL
COII1
i (E hEiiT COItfN)
401
m ~C
402 i
493 i RS - RESET SERIAL 110 I«lVE COtIIfINI)
494 i

9985 9691

99870ER4
9989 CGE59fI
II98C C3S798

898F
8m
8993
8996

9694
eEC2
CGE59A
C35708

495 RSC/tI):

PIIII
8,91H
i' OF PAI1fI'ETERS
,ctIIIIfIIi)
C,69H
PIIII
496
497
i GET PARfIIETERS All) ISSUE ())fR()
CfU
COItI
Cll)R£C
i (E NEXT COIIRIl
JIf'
498
489 ;
419 i RD - RECEIVER DISABLE C~~
411 ,
412 ROOO: l1li1
B,eeH
i' OF PARIltETERS
413
C,9C5H
i COIttfN)
l1li1
,ISSUE COItffN)
414
CfU
COllI
CII)R£C
415
JItP
i GET NEXT COIIRIl
416 i
417 i RB - RESET ONE BIT DELAY COItfN)
418 i
;. OF PARfl£TERS
419 RBCI1D: PIIII
B,01H
C,64H
429
MVI
iCOllRll
i (E PARfl£T£R All) ISSUE CQM()
421
CALL
COllI
i GET NEXT wtIfN)
422
JItP
·~EC
423;
424 ; 58 - SET ONE BIT DELAY COItffN)
425 i
426 SBCII): PIIII
8,91H
i' OF PARfl£TERS
C,eA4H
,COIIRIl
427
PIlI!
i(E PflRAI£T£R All) ISSUE COIIIKI
428
CALL
COllI
; (E NEXT wtIfN)
429
JItP
CIIlREC
439 i
431 i SL - SELECTIVE lOOP RECElYE COItfANl)
432 i
433 SLCI1D: PIlI!
8,94H
• OF PARfI£TERES
C, IlC2H
434
PIIII
COIIRIl
GET PARfI£TERS All) !SSUE COlIN)
435
CALL
COItI
(E NEXT COIMI)
JIf'
436
OOREC
437 i
438 i TL - TRANSMIT lOOP COIIIIfIII)

2-338

611001-51

AP-36

e999
899C
999E
99AB
99A3

210028
8602
36CA
218228
C3F689

e9A6
89A8
B9AA
891lD

0681
!lE91
CDE59il
(35700

89Be
99B2
99B4
9987

0691
!lEAS
CDE58R
C:;5700

898A
O",sc
B9!1E
89C1

0604
8EC1
COE5OA
C35788

B9C4
e9C6
89G8
89GB

B6e2
!lEGe
CDE5BA
C35788

89CE
89DB
89D2
8905

0688
aECC
CDE5!lfl
C35700

9908
89DA
990C
89DF

06B1
BE63
CDE58f1
C35788

e9E2
89E4
B9E6
B9E9

0681
!lEA]
CDE50A
C357B8

439 .'
H, CI1I)8\JF
440 TWID: LXI
; SET COI1IIfH) BlfFER POINTER
B,82H
441
MVI
; ure P~AttETER COUNTER
M, OCAH
442
MVI
; LOOO CllI1IIIflD INTO BlfFER
H, Cttl)BUF>2
443
LXI
; POINT AT AOR AI(> CNTL POSITIONS
444
JMP
TFCH01
; FINISH OFF ru\I1iH) IN TF ROOTlhE
445,
446 'SO - SET OPERATING MODE COIIIIfH)
447 ,
448 SOCttl)· MYI
B,81H
; I OF PARAI1ETERS
; C(J1IIfN)
449
C,91H
HI'I
; GET Pfm1ETER AI(> ISSUE COftH)
459
CAlL
COI'I1
; GET NEXT COIIfli)
451
JI1P
CMDREC
452 ;
453 ,SS - SET SERiAl 110 COIfI¥lM)
454 ;
455 SSC11D: I1VI
B,81H
; I OF Pf'lWlETERS
; COItIfN)
456
C, IlAeH
MYI
457
CALL
; GET PAI91ETER AI(> ISSUE rotfH)
C~
458
; GET NEXT COfMI)
JHP
CItJREC
459 ;
460 ; SR - SELECTIVE RECEIVE tOItflNl
461 ;
B,84H
462 SRCMD: MVI
,I OF ~AlETERS
M'II
C, BC1H
; CCIWINO
463
464
CALL
COHM
; GET PARftIETERS AND ISSlI CIMH)
; GET NEXT CIJlt1ANl)
465
JMP
CI1!>REC
466 ;
467 ,~ - GENERAL RECEIVE CIlI1II'W
46B ;
469 GRCI,O: MYI
B,82H
; III Pf1RIII£TERS
; C!WIfIII)
C, eceIl
479
MVI
; ISSUE COPtIflN)
471
CALL
COHM
472
JHP
; GET NEXT COtmND
CMOREC
473 i
474 ,AF - ABORT FRAI1E COMMAND
475 ;
476 AFCIIO: MVI
B,B9H
; III PARMTERS
; COtfAN)
C,BCCH
477
HVI
; ISSUE CIJtfH)
478
CALL
COHH
; GET NEXT ClJttAN)
479
CHDREC
Jt1'
400 ;
481 ; RP - RESET PORT DJI1I1AN)
482 ,
;. OF PfIRflIIETERS
B,81H
483 RPCMD: MYI
C,63H
,COI'IIAND
484
HVI
;GET PARMTER IN) ISSlI CIJtfH)
485
CALL
C019I
; GET NEXT ctlIIfN)
486
JIf'
C~C
487 ;
400 ; SP - SET PORT cotMID
489 ;
B,81H
,I OF fWAIETERS
498 SPCHD: MVI
, COPIIAN)
(,8fl3H
491
MVI
492
,GET PARAI1ETER AI{) ISSUE COItflN)
CALL
COM
; GET HEX CIJtIItfH)
493
JIf'
CII>REC
494 ;
495 ; TF - TRf!NSIIIT FR/lI£ iXIItN)
496 ;

611001-52

2-339

inter

Ap·36

89EC
89EF
99F1
99F3
99F6
99F7
'99F8
B9F8
99FE
9A91
8A82
9A93
9A84

218829
9692
36C8
219229
78
A7
CA978A
COfI)IIA

0AA788
23
OS
77
C3f689

9A97 2111088
9A9A 910eee
9AOO C5
9A9E COADeA
9A11 0A188A
9A14 77
9A1S 23
9A16 C1
9A17 93
9A1S C3808A
9A1B FEeD
9A1D CA248A
9A29 C1
9A21 C3A788
9A24 C1
8A25 219129
eA28 71
9A2923
9A2A 78
9A2B 9694
9A2D 21369A
9A39 C5
eA]l E3
9A32 C5
9A33 C3fB9A
eA36 C3S7118

9A391685
9A3B 2A1329
9A3E E5
9A3F 7E
9A4e E61F
9A42 FEBC
9A44 0A629A
9A47 21C3OC
9A4A CD92eC
9A4D E1
9A4E 7E
9A4F CDC796

H, CII)IItF
497 TFCI1D: LX[
; SET COItflII) BUFFER PO[NTER
MY[
498
8,02H
; LOfI) P~TER CIUlTER
/W[
499
M,8C8H
; LOfI) COIIffN) [NTO BUFFER
LX[
599
H, CI'I>8UF+2
; PO[NT AT ADR All) CNTL POSITlONS
581 TFCII)1: MOY
A,B
; TEST P~ER COIJjT
582
A
ANA
.' IS IT 97
583
JZ
TBUFL
.' YES. LIR) IX OATA BUFFER
PAR[N
584
,C£TPARMTER
CALL
585
; [LLEGAL GIl! RETURNED
JC
ILLEG
[NX
; [1£ COIIfIII) BUFFER POINTER
586
H
587
OCR
8
; DEC PARA£TER COlmER
M,A
588
MOY
; um PARAI'ETER INTO COItflII) BlfFER
589
JIf'
TFCIIl1
; GET NEXT ~ER
519
H, TXBUF
511 TBUFL: LX[
; LIR) TX OATA BUFFER POINTER
LX[
B,OOOOH
512
; ruAR BC - 8YTE C!UlTER
; 5AYE BI'TE COIJjTER
513 TBUFL1: PUSH
B
PAR[N
514
; GET OATIL FURS PARfI£TER
CALL
EIIlCH(
; IfIYB£ Ell) [F ILLEGAL
515
JC
11()\/
M,A
; LOfI) OATA BI'TE INTO BlfFER
516
; INC BUFFER POINTER
517
INX
H
; RESTORE BYTE COlmER
518
POP
B
[NX
519
; INC BYTE C!UlTER
B
529
; GET NEXT OATA
JIf'
TBUFLi
521 £ll)C11(: CPI
; RETURNEO [LLEGAL CHR CR?
CR
; YES. THEN IX BtfFER Flll
522
JZ
TMFL
523
POP
B
; RESTORE B TO SAVE STACK
, ILLEGAL CHR
524
JMP
ILLEG
; RESTORE BYTE COlmER
525 TBUFFL: POP
B
H, CIIlBUF+1
; PO INT INTO C(ftI1AN) BUFFER
526
LXI
M,C
; STORE BYTE CIUll LSB
527
I1DY
;
INC PO[NTER
528
INX
H
11()\/
/l,B
; STORE BYTE COlRIT MSB
529
B,94H
; LOfI) PARAPIETER CIUlT [NTO B
539
/WI
H, TFRET
; C£T RETlJ!N ADR FOR THIS ROOTlNE
531
LXI
; PUSH Dr«:E
532
PUSH
B
; PUT RETlRN ON STACK
533
XTHL
; PUSH IT SO CIWUT CAN USE IT
534
B
PUSH
; ISSUE ro9tAf()
535
CI1DOUT
JMP,
,GET NEXT C!mAII)
536 TFRET: JMP
CMDREC
537 ;
538 ;
539 ;ROOTlNE TO DISPLAY RESULT IN RESUlT BUFFER NI£N LIR) All) COOS«.E
549 ; POINTERS ARE D[FFERENT.
541;
542;
D,8SH
543 DISPY: MY[
; D IS RESULT'COlIlTER
544
LHLD
; GET CONSOLE POINTER
CNADR
; SAVE IT
545
PUSH
H
546
I1DY
A.M
; GET RESULT Ie
547
; LIMIT TO RESULT COO£
ANI
lFH
; TEST IF RX OR IX SOI.m
549
CPI
OCH
; CFIIlRI'. THEN RX SOI.m
549
JC
RXSORC
LX[
H, TXIItSG
559 TXSORC:
IX INT MESSAC£
DISPLAY IT
551
CALL
TYItS6
552 DISPY2: POP
H
RESTORE Calsa.E POINTER
553 DISPY1: 11()\/
GET RESULT
A."
CONYERT All) 0[SPLAY
554
CALL
IfIOOT
611001-53

2-340

AP-36

0Il52
0A54
0Il57
9AS8
Bfl59
9A5C
0Il5F

BE29
CDF895
2C
15
C24EOO
221329
C35708

556
557
558
559
560
561
562
563
564
565

JNZ

C, '
ECHO
L
D
DI5PV1

Stu)
JIIP

CII)REC

MVI
CAlL
INR
OCR

555

CIR)R

;SP C~
; DISPLAY IT
; It.( BlfFER POINTER
; DEC RESllT COOITER
; OOT IX»£
; UPOATE COOSDLE POINTER
; RETlIlN TO LIXP

;
;
;RECEIVER SOURCE - DISPLAY RESULTS
;

All)

RECEYIE BlfFER COOTENTS

566 ;
BA62
9A65
0A68
9A69
9A6A
9A6D
9A6F
0072
0073
0074
0075
BAn
oo7A
OO7C
oo7F
8Il88
8003
Ilfl86
8009
9A8C
8f!8I)

800E
009F
0092
1lA93
0094
0097
1lA99
eA9C
009D

21B80C
CD920C
E1
7E
CDC796
I!E2ll
CDF895
2C
15
7A
FE94
CAA29A
FE93
CAA700
A7
C2698A
221329
CDE895
218982
C1
78
B1
CA5798
7E
C5
CDC796
9£29
CDF895
C1
8B

009E 23

8fl9F C38D8A
8Afl2 4E
8Afl3 C5
9AA4 C37FBA
9AA7
8AflB
8Afl9
8AAA

C1
46
C5
C37F00

567 RXSORC: LXI
560
CALL
569
POP
57Il RXS1: MaY
571
CALL
572
MYI
573
CALL
574
INR
575
OCR
I\()\I
576
577
CPI
578
JZ
579
CPI
58Il
JZ
581 RXS2: ANA
582 '
JNZ
Stu)
583
584
CALl
585
LXI
586
PIP
587 RXS3: I\()\I
58Il
0RfI
589
JZ
598
MaY
591
PUSH
592
CALL
593
MYI
594
CALL
595
POP

H,RXIMSG
TY!!SG
H

A,M
IfWT
C,' ,
ECHO
L
D
A,D
94H
RIlPT
83H
RiPT
A
RXS1
CNfI)R
CRLF

H, RXBUF
B
A,B
C
CMOREC
A,"
B
IfWT

596

OCX

C,' ,
ECHO
B
B

597
59B
599

INX
JIf'

RXS3

; RX INT MESSfliO fI)R
; DISPLAY MESSfliO
; RESTORE C(J6(ll POINTER
; RETRIEYE RESllT FROM BlfFER
; CIIMRT All) DISPLAY IT
; ASCII SP
; DISPLAY IT
; It.( COOSDLE POINTER
; DEC RESllT CCU/TER
; GET SET TO TEST COOITER
; IS THE RESll T R8?
; YES, GO 5AI'E IT
;IS THE RESllT R1?
; YES, GO SAI'E IT
; TEST RESllT CfA.MER
; OOT IX»£ YET, GET NEXT RESll T
; DOOE, 50 UPOATE CONSOLE POINTER
; DISPLAY CR
; POINT AT RX BlfFER
; RETRIEYE RECEIVED COOIT
; IS CruNT 9?
; YES, GO BIU TO LOO'
; NO, GET OR
; SAI'E BC

; calVERT All) DISPLAY OR
; ASCII SP
; DISPLAY IT TO 5EI'fIlATE DATA
; RESTtI!E Be
; DEC COOIT
; It.( POINTER
; GET tEXT OR

C,M
MaV
;GET R8 FOR RESllT BlfFER
681
PUSH
B
; SAI'E IT
; R£TlIRN
682
JIIP
RXS2
693
694 RiPT: POP
B
; GET R9
695
MOY
; GET R1 FOR RESllT BlfFER
B,"
696
PUSH
B
; SAI'E IT
697
RX52
JIf'
698 ;
699
619
6U ~AIfETER INPUT - PARAl£TER REMNED IN E REGISTER
612

6ee RIlPT:

611001-54

2-341

AP·36

BAAD
BAAE
9fl89
9fl8:l

CS
1681
CD1F96
CDF895
9AB6 79
i!AB7 FE29
9A89 C2E99A
eABC CD1F96
9ABF CDF99S
9AC2 CD5E97
SACS D2E99A
9AC8 C0989S
9AC84F
9ACC 7A
eflCD A7
8ACE CAOC8A
0ADl1S
eflD2 AF
0AD3 79
8AD4 17
9t1[,5 17
0AD6 17
8AD7 17
8A08 SF

eflD9 ClBC8A
8ADC 79
I!II){) 83
8ADE Cl
8ADF C9.
eRE8 79
0AEl 37
8AE2 Cl
eRE3 C9

8AE4 CF

tIAE5 21ee28
8lE8 C5
8lE9 71
IIAEA 78
IIAEB R7

eREC CAF99A
8AEF CDRD8A
8RF2 DRA788

8AF5
8ff'6
8ff'7
8ff'8
8ff'B
8AFE

23
85
77
C:lEA8A
218828
(1

613 ;
614 P~IN:
61S
616
617
618
619
628
621 PARIN:l:
622
62:1
624
625
626
627
628
629
6:l8
631
632

PUSH
ltVi
CALL
CALL
!tOV
CPI

8
D. 91H
GETCH
ECHO
A,C

JH2

PARIN1
GETCH
ECHO

CALL
CALL
CALL

VALOO

JNC

~IN1

CALL

CNI/8N

MOY

C,A
A,D
A
PARIN2
D
A
A,C

!tOy
ANA
J2
OCR
XRA
~

RAL
RAL

634
635
RAL
636
RAL
637
MOY
E.A
PARIN3
6:l8
JIll>
A,C
639 PARIN2: I10Y
648
ORA
E
641
POP
8
642
RET
A,C
643 PARIN1: I10Y
644
STC
64S
POP
8
646
RET
647;
648 ;
649 ; JlJf' HERE IF BUFFER RJLL
658 ;
651 BUFRJL: DB
BCFH
652 ;
653 ;
654 ; COIIPIfIII) DISPATCHER
655 ;
656 ;
H, CIIOOUF
657 CG'IPI: LXI
658
PUSH
B
659
I10Y
",C
A,B
668 ctJttl: I10Y
R
661
ANA
662
JZ
CIOO.JT
663
PARIN
CIU
664
JC
ILLEG
H
665
INX
OCR
B
666
667
I!O'I
",R
668
JMP
COMM
669 CIOO.JT: LXI
It 00IItF
678
POP
B

;5II\IE BC
; SET CfR CIllflTER
; GET CfR
; ECHO IT
; PUT CfR IN A
;SP?
; 1«), ILLEGAL TRY AGAIN
; GET CfIR OF PARffIETER
; ECHO IT
,IS IT A VALID CHR?
; NO, TRY AGAIN
; CIJiVERT IT TO HEX
; SllYE IT IN C
; GET CfR CIllflTER
; IS IT 8?
; YES, OM WITH THIS PARMTER
,DEC CHR COltflER
; CLEAR CARRY
; RECOYER 1ST CHR
; ROTATE LEFT 4 PLACES

;SAVE IT IN E
; GET NEXT CfR
;21«) CHR IN A'
; CO/tBlHE BOTH CHRS
; RESTORE BC
.' RETURN TO CfUIfIl PROORAI!
; PUT ILLEGAL CHR IN A
; SET CARRY RS ILLEGAL STRTUS
.' RESTORE 8C
.' RETURN TO Cfl.LlfIl ~

; EXIT TO IKlIITOR

; SET POINTER
; SA'IE BC

; LOll) COftN) INTO IllfFER
; CHECK PARIIIETER ro.MER
;IS IT B?
; YES, GO ISSlE CQIRI)
; GET PfIRfIIETER
; ILLEGAL CHR REl1MD
; INC BlFFER POINTER
,DEC ~ER CIllflTER
PARIIIETER TO BlfFER
GETNEXT~

REPOINT POINTER
RESTORE ~ CIlJIT

2-342

611001-55

inter

AP-36

BAFF DB99
IlB81 97
9B82 0flFF9A
9B95 7E
IlI!86 03ge
IlB88 78
9B99 A7
900A CO
ilBeB 23
eaec 95
eaeo D890
BB9F E629
9811 C280eB
9814 7E
9815 0391
9817 C39898

9Il1A
981C
BB1E
8821
8822
8824
9825
9827
882A
9B28
8820
9B2E
9838
9832
8834

3E62
03AB
81ee82
79
OJAB
78
03A8
81FF41
79
03A1
78
OW
3£63
D3A8
C9

671 COIIII2:
672
673
674
675
676 PARi:

677
678
679
689
681
682
683
684
685
686
687
689
689
6ge
691
692
693
694
695
696
697
698
699
700
781
792
783
784
785
786
787

PAR2:

IN
RLC
JC
ItOV
OUT
ItOV
ANfl
RZ
INX
OCR
IN
ANI
JN2
ItOV
(XlT

STAm

PAR1

; READ 8273 STATUS
; ROTATE CBS'! INTO CPRR\'
;WAIT F~ OK
; OK. PIM: C!JtIlN) INTO A
; OOTPIJT mtfH)
; GET PARfI£TER ccurr
;ISITS?
; 'IES. ()(J£, RE"Jmj
; INC mtfH) BUFFER POINTER
; DEC PARfI£TER ccurr
; REIlD STATUS
; IS CP8F BIT SET?
; ~IT TIL ITS 9
; OK. GET PARfI£TER ~ BlfFER
; OOTPIJT PARfI£TER
; GET I£XT PfI1II£TER

CMI2
A,~

COII17.l
A.a
A
H
a
STAm
CP8F
PAR2
A.~
PAR~3

;
;
; INITIAlIZE AND ENABlE RX
;
;
A, VRDIIA
RXDI1A: ~I
OUT
ItODE57
LXI
B. RXBUF
ItOV
A.C
OUT
CH8roR
A,a
ItOV
OUT
CHBADR
B. RXTC
LXI
A.C
ItOV
OUT
ClieTC
A,B
ItOV
OUT
ClieTC
~I

A,E~

OUT
RET

ItODE57

CIflIf£L

; DISRBLE RX Dffl CIRf£L
; 8257 ItODE ~T
; RX BUFFER START ADDRESS
; RX BUFFER LSB
;CH8 ADR P~T
; RX BUFFER ..sa
;CH0 ADR P~T
; RX CH ~IIfII. COUNT
; RX TERltIIR. COUNT LSB
;CH8 TC ~T
; RX TERltIIR. COlIIT ..sa
;CH8 TC ~T
; E!RIlE ~ IOID
; 8257 ItODE ~T
;RET\MI

;

788 ;

9835 3£61
983703A8
9839 81BeOO
883C 79
9830 D3A2
883F 78
9B48 D3A2
9842 81FF81
9845 79
8IM6 D3A3
9B48 78
9849 D3A3
984B 3£63
9B4D D3A8
9B4F C9

; INITIAliZE AND EIfIIIlE T1< Dffl CIRf£L
;
;
A,D~
; DISAIllE T1< Dffl CIRf£L
TXDffl: ~I
; 8257 ItODE P~T
713
OUT
ItODE57
; T1< BUFFER START ADDRESS
714
LXI
B. T1 POINTER LSB
B
fl,B
,GET SET TO TEST
1m
751
, LI8>=CONSQ.E?
752
CIf'
L
,YES, 8lFFER FIll
753
JZ
IlUFFll
,DECCWITER
754
OCR
D
,NOT DONE, TRY fOIlN
75S
JNZ
RXI1
D, !ISH
,RESET CrumR
756
IIYI
.,RESTORE Ll8> POINTER
701
POP
H
758 RX12: IN
,READ STATUS
STAID
75~
flNl
RXINT
,TEST RX INT BIT
,DONE, 00 FINISH lI'
760
JZ
RXB
761
,READ STATUS fOIlN
IN
STAID
762
RXIRA
,IS RESl1.T REffIY?
ANI
763
,NO, TEST fOIlN
JZ
RXI2
764
,YES, READ RESULT
IN
RXIRn
765
1m
PLA
,STORE IN 8lFFER
766
,INC 8lFFER POINTER
1111
L
767
OCR
,DEC CWITER
D
768
RXI2
,GET ~ RESl1.TS
~
fl,D
769 RXI3: 1m
,GET SET TO TEST
,ALL RESl1.TS?
778
ANA
A
,YES, so FINISH lI'
771
RXI4
JZ
,NO, Ll8> 8 TIL DONE
772
IIYI
PL8!!H
m
;!lUI'
POINTER
1111
L
;DECCWITER
774
OCR
0
,00 AGAIN
77S
~
RXI3
lDfI)R
776 RX14: SHLD
,lI'OOTE Ll8> POINTER
; GET PlOOf III)ICATIlR
PRlf'T
LDA
,fOMI. ~
778
Cl'1
'-'
,YES, CLEftI lI' BEFORE ~
m
RXI6
JZ
788 ;
781 ,
POLL PlOOf so CI£()( CONTROL BYTE
782 ,
IF CONTROL IS A POLL, SET lI' SPECIAL TX CMRI) 8lFFER
783 ,
AND RETURN Nillt POLL III)ICATIlR NOT 8
784 ,
,GET PREYIOOS Ll8> ADR POINTER
78S
POP
H
,GET IC BYTE FRIll! 8lFFER
786
1m
A,"

2-344

611001-57

infef

AP-36

8C52 E61£
8C54 C2899C
I!CS7 2C
9C58 2C
8C592C
8C5A 56
8C5B 2C
9CSC 7E
i:SO FE93
9C5F CA6CIlC
9C62 FEll
8C64 C2899C
8C67 1£11
~9 C36E8C
I!C6C 1E7l
~ 212829
8m 36C8
i:73 23
8C743688
9C7623
~3688

~23

8C7A
9C78
8C7C
8C7O
8C7F
D2

23
73
lE81

321628
C3899C

ANI
JNZ
INR
INR
INR
lIlY
IIf!
lIlY
CPI

787
788

789
798
791
792
793

794
795
797
79B

i LOOC AT GOO) FRfI£ BITS
i IF NOT 8, INI£RRUPT IIlSH'T FRO! A GOO) FRII£
iB'r'PASS R8 All) R1 IN BtFFER

0,"

i GET ADR BYTE

L
A,"
SNRItP
U
RR8P
RXIS
E. RR8F
TXRET
E.NSAF
H.Cll>llFl
1L8C8H
H
1L88H

12
CPI

796

1EH
RXIS
L
L
L

JNZ
IIYI
B88
JII'
881 U:
IIYI
B82 TXRET: LXI
8B6
IIYI
8Il8
INX
IIYI
889
818
INX
811
IIYI
812
INX
lIlY
813
814
INX
815
ItOV
816
ItVI
817
STA.
818
JlI'

H
1L88H
H
11.0
H
ILE

A.81H
PIUN
RXIS

All)

5A'IE IT IN 0

i GET CHTL BYTE FRIll BtFFER
i WRS IT SNRII-P?
i I'ES; 00 SET RESPIJj!jE
iWRS IT RR(8)-P?
i YEs, 00 SET RESPOI5E. OTJ£RWISE RETII!H
i RR(8)-P SO SET RESPIJj!jE TO RR(8)-F
i 00 FINISH LOADIlIl Sl'ECIAL BtFFER
i ~-P SO SET RESPIJj!jE TO NSf+-f
i SPECIAL BtFFER ADR
i LOAD TX FRAI£ mtRI)
i INC POINTER
iL8=8
i INC POINTER
iLl=8
i INC POINTER
i LOAD RCYO ADR BYTE
i INC POINTER
i LOAD RE5P(JI5E CNTL BYTE
i SET pw. III>ICATOR NOT e
i LOAD POLL INOICATOR
iRE'IU!N

819
BC85 E1
9C86 C3899C

a9 CD1A8B
ecsc 01
8C8O Cl

829 RX16:

P(J'

821
822
823 RXIS:

)It'

RXI5

i CLEAN IJ' STACK IF r«RR. IO>E
i RETII!H

CALL

RXMA
0

i RESET ~ CIIN£l
i RESTORE REGISTERS

824

825

8CIIE F1

B26

8C9' E1

B27
828
829
B38
B31
B32
an
B34

9C98 FB

i:81 C9

~cs

8C93 7E
8C94 23

8C95 FEFF
8C97 CAA1i:
IlC9A 4F
8C9B COFlI8S
IlC9E C39~
~C1

8CA2 C9

B3S
B36

B37
838
839

POP
POP

PSN

POP
POP
EI
RET
i
i
i IIESSIIE TYPER
i
i
TYIISG: PUSH
TYIISG2: IIOY
INX
CPI
12
ItOV
CALL

i EIftIlE INTERRlPTS
i RETII!H

- ASSlI£S IIESSIIE STARTS AT II.

848
841
)It'
842
843 TYIISG1: POP
844
RET
B45

A."
H
8FFH

TYIISG1
C,A
ECHO
TYIISG2
B

5A'IE BC
GET ASCII CIt!
INC POINTER
5T(J'?
'IE5. GET SET FOR EXIT
SET IJ' FOR OISPUIY
OISPUIY CIt!
GET /£XT CIt!
RESTORE BC

RETII!H

B46

847 SIGIIlN ESAIE
848

611001-58

2-345

inter

AP-36

9CfI3

I!CI!4

38323733

9CfI8
9CIIC
8CB9
8C84
0CB6

284D4F4E .
49S44F52
28285631
2£31

849 5[GIOI: DB

CR. '8273 POI[TOR Vi. 1', CR. 8FFH

9C87 FF
858 ;
8S1 ;

852 ;
853 ; RECE[VER [NTERRlI'T I£55IIGE5
8:!4 ;

8CB9 eo
9C89 52582849

855 ;
856 RX[IISG: DB

CR. 'RX [NT -, '. 8FFH

9C8D 4£542820

1lCC1 28
IlCC2 FF

857 ;

1lCC3 eo
1lCC4 54582849

858 ; TRIINSII[nER [NTERRlf'T I£55IIGE5
859 ;
868 TXII1SG: DB
. CR. 'TX [NT - '. 8FFH

IlCC8 4£54282D

ecce 28

IlCCD FF
861 ;

862 ;
863 ; TRANSIIInER INTERRlf'T ROOTIt£
864 ;

IlCCE E5
IlCCF F5
QII C5

8CD1 OS
8CD2 .lE61

865 TXI:
866
867
868
869

8CD4 03A8

878

1684

B71

I!CI)6

8CD8 2ft1828

872

QII E5

873
874

8CDC 4S
8CDD 2111328
SCEB 84
SCEl78
8CE2 BD
8CE3 ClE4eA
SCE615
8CE7 C2ElJBC
8CER E1
8CEB DB92
8CED 77
8CEE 2C
8CEF 36BB
1K:F1 2C
8CF2 36BB
1K:F4 2C

8CF5 3688
8CF7 2C

875
876 TXI1:
1177
878
879
8BB
8B1
882
883
884

88S
886
887

8BB
889

898
891

PUSH
PUSH
PUSH
PUSH
IIYI
OOT
IIYI
LILD
PUSH
lIlY
LILD

IIf!
IIJY
CIf>
1Z
OCR
JN2
POP
IN
IIJY
IIf!
IIYI
IIf!
IIYI
IIf!
IIYI
INII

PSN
B
0

fLOTDIII
IDlE57

O.84H
LDfI)R
H

B.L
CIRlR
B
R.B

L
BIfFIL
0
TXI1
H
TXIR73

If, A
L
If,BBH
L

;SAYE II.
;5A'/E PSN
;5A'/E 8C
;5A'/E DE
; DI5IIIl.E TX DIll
; 8257 IQ)E PIWIT
;SETC~

; GET LOll) POINTER
;5A'/E IT
;5A'/E lSI! IN B
;1Ef COI!ilU POINTER
; It«: POINTER
ilEf SET TD TEST
; LOfI)=COOSO.E?
; YES. IlfFER fIl.l
; I(), TEST I£XT LOCATION.
;TRY fDUN
;RE5TDRE LOll) POINTER
; RElI) RESILT
; STORE IN IlfFER
; INII POINTER
; EXl1III ~T SPOTS •

1f,8IlH

L
1f,8IlH
l

611001-59

2-346

infef

Ap·36

eCFS
0CFR
acrB
eCFE
900:1
eD02
0003
ooB4
0005
0006

:6~e

MI'I
INR
5HLD
CALL
POP
POP
POP
POI!
EI
RET

892
891:

2C
221920
C03501l
Dl
(1
Fl
Ei
F8
C9

894

899
gee
ge1

902
903
904
905
906
%7
952
953
954

M. SOH
L
LDAt'R
TXOHfl
D
B
PSI!
H

• UPDATE LIJt1I) POINTER
,RESET DNA CHANNEL
,RESTORE DE
. ~ESTORE BC
,P£5TORE PSI!
; RESTORE Hl
,EHftBLE INTERIWPTS
; ~ETIJRN

,
;
;
.
END

PUBLIC S'lM8OLS

EXTERNIlI. S'lHBOLS

IJSER S'lMBOLS
AOWN A e922
C!1DSl A 9e27
CNTB53 A 1li!9C
CilI1II A eRE5
DEM
A BBOO
ECHO A B5F8
ILLEG A OSA,
ItlC1H2 A 9986
PAR1 A eees
POLIN A 2016
RIW
A 00B2
RSCMD A 9967
RXIl A 8C16
RXINT RBOO8
RXTC A 41FF
SPCI'ID A 99£2
STKSRT A 2OC0
TEST73 A e092
TXBUF A slli!e
n;[NT A 9994
TYMSG A ecn

AFCtIfI
CHDBFl
GNT1S>
COltlll
r,EHQDE
EtIfICHK
LDADR
HDESl
PAR2
PRMPT
RE58UF
RST65
RXI2
RXIR73
SBCItl
SRCtifl
SW
TFCM[)
TXDS1
TXIR73
TYMSGl

ASSEHBL Y Co/1PLETE..

A 99CE
A 2920
A Ili!9D
A iIA£A
A 2927
A eA1S
A 2919
A B9CE
A 0000
A 2015
A 281li!
A 20CE
A OCl:!
A 0093
A 89SS
A 99BA
A 8943
A B9£C
A 0088
A 9992
A OCA1

BliFFUL
CItDBUF
CNT25:;
CotII!2
r,ISPY

ENOItH
LF
MODES,
PARIN
RaPT
RESL 73
RST75
Rm
RXIRR
SOWN
SSCMr,

T1
TFeMOl
TXD"A
rilIRA
TYMSG2

A 9AE4
A 2eee
A 999£
A 0ftFF
A eA39
A 0061
A 0eOA
A Ili!9B
A 9AAD
A BAA2
A B991
A 2004
A 8C9
A 0092
A BSD7
A 8989
A OC6C
A 09F6
A 0035
ABBB1
A OC93

CHeAI)R
CMDOLIT
eNTLSl
COI9I73
DISPYl

GDWH
LKBRl
MOr>ES7
PARIN1
R1FT
ROCI1O
RXBlf
RXI4
RX51
SIGNON
START
TBUFFL
TFRET
TXllI1Al

l:\!'OL
YIU,G

A OOAe
A eAFB
A 1li!89
A 1li!99
A BA4E
A 08FF
A 2el?
A 1li!A8
A aRE9
A BAA?
A 995[,'
A 8200
A 9C45
A 81169
A IJl:Rl
A Bsee
A eA24
A SA]6
R 0042
A B94C
A B?SE

CHaTC
CIIDREC
CNTLC
CPBF
DISFY2
GETCH
U:SR2
HOHTOR
PARIN2
RBCMD
RPCMD
R;\D51
R:i15
RXS2
SLCI'I()
STATSl
T8UFL
TLCHO
ri.I
rliRET

A Befll
A BBS7
A B003
A 1li!29
A BA4D
A 061F
A 2918
A eees
A aAOC
A 99?B
A 99D8
A B988
R 9C89
A BA7F
A 99SF
A 9989
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TRUE
TXI1
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A 0911
A 9SB8
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A ilil62
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A 9ABC
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CNAOR A 2013
COBR A 888C
CRLF A 85EB
DTOIIA A 8861
GRC/fj A 09C4
IflCNTB A 9936
N5IlF A 1li!73
PAR1I73 A Ili!91
RDiIl A OBflF
RRIIP A 9911
RXI
A 9C99
RXIHSG A 9C88
RXS(E A 9A62
50CIIi A89A6
STAm A 9B96
TDiIl A 990E
TRUE1 A BB9B
TXIMSG A 9CCJ
TXTC R S1FF

NO ERRORS
611001-60

2-347

APPLICATION
NOTE

AP-134

October 1990

Asynchronous Communication
with the 8274 Multiple-Protocol
Serial Controller

Order Number: 210311-002
2-348

ASYNCHRONOUS
COMMUNICATION WITH
THE 8274 MULTIPLE·
PROTOCOL SERIAL
CONTROLLER

CONTENTS

PAGE

INTRODUCTION ....................... 2-350
SERIAL-ASYNCHRONOUS DATA
LINKS ............................... 2-350
MPSC SYSTEM INTERFACE .......... 2-353
PROGRAMMING ...................... 2-356
DATA LINK INTERFACE .............. 2-360
APPENDIX A:
Command/Status Details for
Asynchronous Communications ... 2-361
APPENDIX B:
MPSC Polled Transmit/Receive
Character Routines ................. 2-367
APPENDIXC:
Interrupt-Driven Transmit/Receive
Software ............................ 2-370
APPENDIX D:
Application Example Using SDK-86 .. 2-373
REFERENCES ......................... 2-386

2-349

intJ

AP-134

3. DMA Mode. The MPSC automatically requests data
transfers from system memory for both transmit and
receive functions by means of two DMA request signals per serial channel. These DMA request signals
may be directly interfaced to an 8237 or 8257 DMA
controller or to an 8089 I/O processor.
4. WAIT Mode. The MPSC ready signal is used to synchronize processor data transfers by forcing the
processor to enter wait states until the 8274 is ready
for another data byte. This feature enables the 8274
to interface directly to an 8086 or 8088 processor by
means of string I/O instructions for very high-speed
data links.

INTRODUCTION
The 8274 Multiprotocol serial controller (MPSC) is a
sophisticated dual-channel communications controller
that interfaces· microprocessor systems to high-speed
serial data links (at speeds to 880K bits per second)
using synchronous or asynchronous protocols. The
8274 interfaces easily to most common microprocessors
(e.g., 8048, 8051, 8085, 8086, and 8088), to DMA controllers such as the 8237 and 8257, and to the 8089 I/O
processor. Both MPSC communication channels are
completely independent and can operate in a full-duplex communication mode (simultaneous data transmission and reception).

Scope

Communication Functions
The 8274 performs many communications-oriented
functions, including:
Converting data bytes from a microprocessor system into a serial bit stream for transmission over
the data link to a receiving system.
- Receiving serial bit streams and reconverting the
data into parallel data bytes that can easily be pro.
cessed by the microprocessor system.
Performing error checking during data transfers.
Error checking functions include computing/transmitting error codes (such as parity bits or CRC
bytes) and using these codes to check the validity of
received data.
Operating independently of the system processor in
a manner designed to reduce the system overhead
involved in data transfers.

This application note describes the use of the 8274 in
asynchronous communication modes. Asynchronous
communication is typically used to transfer data to/
from video display terminals, modems, printers, and
other low-to-medium-speed peripheral devices. Use of
the 8274 in both interrupt-driven and polled system environments is described. Use of the DMA and WAIT
modes are not described since these modes are employed mainly in synchronous communication systems
where extremely high data rates are common. Programming examples are written in PL/M-86 (Appendix
B and Appendix C). PL/M-86 is executed by the
iAPX-86 and iAPX-88 processor families. In addition,
PL/M-86 is very similar to PL/M-80 (executed by the
MCS-80 and MCS-85 processor families). In addition,
Appendix D describes a simple application example using an SDK-86 in an iAPX-86/88 environment.

SERIAL-ASYNCHRONOUS DATA
. LINKS

System Interface
The MPSC system interface is extremely flexible, supporting the following data transfer modes:
1. Polled Mode. The system processor periodically
reads (polls) an 8274 status register to determine
when a character has been received, when a character is needed for transmission, and when transmission errors are detected.
2. Interrupt Mode. The MPSC interrupts the system
processor when a character has been received, when
a character is needed for transmission, and when
transmission errors are detected.

A serial asynchronous interface is a method of data
transmission in which the receiving and transmitting
systems need not be synchronized. Instead of transmitting clocking information with the data, locally generated clocks (16, 32 or 64 times as fast as the data transmission rate) are used by the transmitting and receiving
systems. When a character of information is sent by the
transmitting system, the character data is framed (preceded and followed) by special START and STOP bits.
This framing information permits the receiving system
to temporarily synchronize with the data transmission.
(Refer to Figure I during the following discussion of
asynchronous data transmission.)

2-350

AP-134

TlME-

_1_0

1-1-

DATA LINK IDLE START '"
(MARKING)
BIT
~

PARITY

CHARACTER (UPPER CASE S·53H)

210311-2

Figure 1. Transmission of a 7-Bit ASCII Character with Even Parity
Normally the data link is in an idle or marking state,
continuously transmitting a "mark" (binary 1). When a
character is to be sent, the character data bits are immediately preceded by a "space" (binary 0 START bit).
The mark-to-space transition informs the receiving system that a character of information will immediately
follow the start bit. Figure 1 illustrates the transmission
of a 7-bit ASCII character (upper case S) with even
parity. Note that the character is transmitted immediately following the start bit. Data bits within the character are transmitted from least-significant to most-significant. The parity bit is transmitted immediately following the character data bits and the STOP framing
bit (binary 1) signifies the end of the character.

Characters
In asynchronous mode, characters may vary in length
from five to eight bits. The character length depends on
the coding method used. For example, five-bit characters are used when transmitting Baudot Code, seven-bit
characters are required for ASCII data, and eight-bit
characters are needed for EBCDIC and binary data. To
transmit messages composed of multiple characters,
each character is framed and transmitted separately
(Figure 2).
This framing method ensures that the receiving system
can easily synchronize with the start and stop bits of
each character, preventing receiver synchronization errors. In addition, this synchronization method makes
both transmitting and receiving systems insensitive to
possible time delays between character transmissions.

Asynchronous interfaces are often used with human interface devices such as CRT/keyboard units where the
time between data transmissions is extremely variable.

VARIABLE DELAY BETWEEN
CHARACTERS

/o1

NODELAY
BETWEEN
CHARACTERS

I)lnm~
....

...in0:

...'"
'"

...
iii iii
...
0
... ...'0:"
'"I I'"
....

I
CHARACTER
*1

nnmm-'-1~LIo&I

... t:;

iii'"
0. ...

00:

..."'Iii'"

....

iii
ll.

....

in
l-

... ...
'"'1 I''""
0

I
CHARACTER CHARACTER
*2
*3

....

...in

ll.

iii
~.

'"I

CHARACTER
*4

ll.

...0

...""

'"CHARACTER I

Figure 2. Multiple Character Transmission

2-351

....

iii

210311-1

AP-134

bits per second to 38,400 bits per second. Table 1 illus·
trates typical asynchronous data rates and the associat·
ed clock frequencies required for the transmitter and
receiver circuits.

Framing
Character framing is aci::omplished by the START and
STOP bits described previously. When the START bit
transition (mark·to·space) is detected, the receiving sys·
tem assumes that a character of data will follow. In
order to test this assumption (and isolate noise pulses
on the data link), the receiving system waits one·halfbit
time and samples the data link again. If the link has
returned to the marking state, noise is assumed, and the
receiver 'waits for another START bit transition,

Table 1. Communication Data Ra~es and
Associated Transmitter/Receiver Clock Rates
Data Rate
(Bits/Second)

75
150
300
600
1200
2400
4800
9600
19200
38400

When a valid START bit is detected, the receiver sam·
pies the data link for each bit of the following charac·
ter. Character data bits and the parity bit (if required)
are sampled at their nominal centers until all required
characters are received. Immediately following the data
bits, the receiver samples the data link for the STOP
bit, indicating the end of the character. Most systems
permit specification of I, 1'/2, or 2 stop bits.

Clock Rate (kHz)

X16
1.2
2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.4 .

X32

X64

2.4
4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.4

4.8
9.6
19.2
38.4
76.8
153.6
307.2
614.2

Timing
Parity

The transmitter and receiver in an asynchronous data
link arrangement are clocked independently. Normally,
each clock is generated locally and the clocks are not
synchronized. In fact, each clock may be a slightly dif·
ferent frequency. (In practice, the frequency difference
, should not exceed a few percent. If the transmitter and
receiver clock rates vary substantially, errors will occur
because data bits may be incorrectly identified as
START or STOP framing bits.) These clocks are de·
signed to operate at 16,32, or 64 times the commimica·
tions data rate. These clock speeds allow the receiving
device to correctly sample the incoming bit stream.
Serial·interface data rates are measured in bits/second.
The term "baud" is used to specify the number of times
per second that the transmitted signal level can change
states. In general, the baud is not equal to the bit rate.
Only when the transmitted signal has two states (elec·
trica1levels) is the baud rate equal to the bit rate. Most
point·to·point serial data links use RS·232·C, RS-422,
or RS·423 electrical interfaces. These specifications call
for two electrical signal levels (the baud is equal to the
bit rate). Modem interfaces, however, may often have
differing bit and baud rates.
While there are generally no limitations on the. data
transmission rates used in an aysnchronous data link, a
limited set of rates has been standardized to promote
equipment interconnection. These rates vary from 75

In order to detect transmission errors, a parity bit may
be added to the character data as it is transferred over
the data link. The parity bit is set or cleared to make
the total number of "one" bits in the character even
(even parity) or odd (odd parity). For example, the let·
ter "A" is represented by the seven·bit ASCII code
1000001 (4IH). The transmitted data code (with parity)
for this character contains eight bits; 01000001 (4IH)
for even parity and 11000001 (OCIH) for odd parity.
Note that a single bit error changes the parity of the
received character and is therefore easily detected. The
8274 supports both odd and even parity checking as
well as a parity disable mode to support binary data
transfers.

Communication Modes
Serial data transmission between two devices can occur
in one of three modes. In the simplex transmission
mode, a data link can transmit data in one direction
only. In the half·duplex mode, the data link can trans·
mit data in both directions, but not simultaneously. In
the full·duplex mode (the most common), the data link
can transmit data in both directions simultaneously.
The 8274 directly supports the full·duplex mode and
will interface to simplex and half·duplex communica·
tion data links with appropriate software controls.

2·352

AP-134

The 8274-processor hardware interface can be configured in a flexible manner, depending on the operating
mode selected-polled, interrupt-driven, DMA, or
WAIT. Figure 3 illustrates typical MPSC configurations for use with an 8088 microprocessor in the polled
and interrupt-driven modes.
.

BREAK Condition
Asynchronous data links often include a special sequence known as a break condition. A break condition
is initiated when the transmitting device forces the data
link to a spacing state (binary 0) for an extended length
of time (typically 150 milliseconds). Many terminals
contain keys to initiate a break sequence. Under software control, the 8274 can initiate a break sequence
when transmitting data and detect a break sequence
when receiving data.

All serial-to-parallel conversion, parallel-to-serial conversion, and parity checking required during asynchronous serial I/O operation is automatically performed
by the MPSC.

Operational Interface

MPSC SYSTEM INTERFACE
Hardware Environment
The 8274 MPSC interfaces to the system processor over
an 8-bit data bus. Each serial I/O channel responds to
two I/O or memory addresses as shown in Table 2. In
addition, the MPSC supports non-vectored and vectored interrupts.
The 8274 may be configured for memory-mapped or
I/O-mapped operation.

Command, parameter, and status information is stored
in 21 registers within the MPSC (8 writable registers
and 2 readable registers for each channel, plus the interrupt vector register). These registers are all accessed
by means of the command/status ports for each channel. An internal pointer register selects which of the
command or status registers will be written or read during a command/status access of an MPSC channel.
Figure 4 diagrams the command/status register architecture for each serial channel. In the following discussion, the writable registers will be referred to as WRO
through WR7 and the readable registers will be referred to as RRO through RR2.

Table 2. 8274 Addressing

Read Operation

Write Operation

0
0
0
0
1

0
1
0
1

0
0
1
1

Ch. A Data Read
Ch. A Status Read
Ch. B Data Read
Ch. B Status Read
High Impedance

Ch. A Data Write
Ch. A Command/Parameter
Ch. B Data Write
Ch. B Command/Parameter
High Impedance

2-353

Intel

AP-134

ADDRESS BUS

.,. ...

aDATA BUS

AD
Wii
'8205

~
P

JV CC

DB0-7

INTA

Ao
A,

MPSC

CS
RD
WR

;110311-3

a) Polled Configuration

,~~f

INTA
CPU
INT

IPI

INTA

INT

I~TA

IPD

IPI

IPD
MPSC

MPSC
HIGHEST PRIORITY

INT
IPI

INTA

IPD

MPSC
LOWEST PRIORITY

210311-4

b) Daisy-Chained Interrupt Configuration
Figure 3. 8274 Hardware Interface for Polled and Interrupt-Driven Environments

The least-significant three bits ofWRO are automatically loaded into the pointer register every time WRO is
written. After reset, WRO is set to zero so that the first
write to a command register causes the'data to be loaded into WRO (thereby setting the pointer register). After WRO is written, the following read or write accesses
the register selected by the pointer. The pointer is reset
after the read or write operation is completed. In this
manner, reading or writing an arbitrary MPSC channel
register requires two I/O accesses. The first access is
always a write command. This write command is used
to set the pointer register. The second access is either a
read or a write command; the pointer register (previously set) will ensure that the correct internal register is
read or written. After this second access, the pointer
register is automatically reset. Note that writing WRO

and reading RRO does not require presetting of the
pointer register.
During initialization and normal MPSC operation, various registers are read and/or written by the system
processor. These actions are discussed in detail in the
following paragraphs. Note that WR6 and WR7 are
not used in the asynchronous communication modes.

RESET
When the 8274 RESET line is activated, both MPSC
channels enter the idle state. The serial output lines are
forced to the marking state (high) and the modem interface signals (RTS, DTR) are forced high. In addition, the pointer register is set to zero.

2-354

inter

AP-134

COMMAND/STATUS
POINTER

Dl
0

-I w

:o :

-I~______~I
-I
-I
-I
-I
-I
w

MSB

I~R

__
R

_2·_ _ _ _

MSB

~1
LSB

Read Registers

·Ch.B only

LSB

Write Registers

210311-5

Figure 4. Command/Status Register Architecture (Each Serial Channel)

External/Status Latches
The MPSC continuously monitors the state of four external/status conditions:
1. CTS-clear-to-send input pin.
2. CD-<:arrier-detect input pin.
3. SYNDET-sync-detect input pin. This pin may be
used as a general-purpose input in the asynchronous
communication mode.
4. BREAK-a break condition. (series of space bits on
the receiver input pin).

A change of state in any of these monitored conditions
will cause the associated status bit in RRO (Appendix
A) to be latched (and optionally cause an interrupt).

Error Reporting
Three error conditions may be encountered during data
reception in the asynchronous mode:
1. Parity. If parity bits are computed and transmitted
with each character and the MPSC is set to check
parity (bit 0 in WR4 is set), a parity error will occur
whenever the number of "I" bits within the character (including the parity bit) does not match the odd!
even setting of the parity check flag (bit 1 in WR4).

2-355

AP-134

2. Framing. A framing error will occur if a stop bit is
not detected immediately following the parity bit (if
parity checking is enabled) or immediately following
the most-significant data bit (ifparity checking is not
enabled).
3. Overrun. If an input character has been assembled
but the receiver buffers are fuIl (because the previously received characters have not been read by the
system processor), an overrun. error will occur.
When an "overrun error occurs, the input character
that has just been received wiIl overwrite. the immediately preceding character.

. Transmitter/Receiver Initialization
In order to operate in the asynchronous mode, each
MPSC channel must be initialized with the foIlowing
information:
1. Clock Rate. This parameter is specified by bits 6 and
7 ofWR4. The clock rate may be set to 16,32, or 64
times the data-link bit rate.. (See Appendix A for
WR4 details.)
2. Number of Stop Bits. This parameter is specified by
bits 2 and 3 of WR4. The number of stop bits may be
set to I, 1'1., or 2. (See Appendix A for \VR,4
details.)
3. Parity Selection. Parity may be set for odd, even, or
no parity by bits 0 and I of WR4. (See Appendix A
for WR4 details.)
4. Receiver Character Length. This parameter sets the
length of received characters to 5,6,7, or 8 bits. This
parameter is specified by bits 6 and 7 of WR3. (See
Appendix A for WR3 details.)
5. Receiver Enable. The serial-channel receiver operation may be enabled or disabled by setting or clearing
bit 0 of WR3. (See Appendix A for WR3 details.)
6. Transmitter Character Length. This parameter sets
the length of transmitted characters to 5, 6, 7, or 8
bits. This parameter is specified by bits 5 and 6 of
WR5. (See Appendix A for WR5 details.)·Characters
of less than 5 bits in length may be transmitted by _
setting the transmitted length to five bits (set ,bits 5
and 6 ofWR5.to 1).
The .MPSC then determines the actual number of
bits. to be transmitted from the character data byte.
The bits to be transmitted must be right justified in
the data byte, the next three bits must be set to 0 and
all remaining bits must be set to 1. The foIlowing
table illustrates the data formats for transmission of
1 to 5 bits of data:

Number of
Bits Transmitted
07 06 05 04 03 02 01 DO (Character Length)
1111000c
1
1 1 0 0 0 c c
.2
1000ccc
3
1000cccc
4
OOOccccc
5
7. Transmitter .Enable. The serial channel transmitter
operation may be enabled or disabled by setting or
clearing bit 3 of WR5. (See Appendix A for WR5
details.)

For data transmissions via a modem or RS-232-C interface; the foIlowing information must also be specified:
1. Request-to-SendlData-Terminal-Ready. Must be set
to indicate status of data terminal equipment. Request-to-send i~ controIled by bit 1 of WR5 and data
terminal ready is controlled by bit 7. (See Appendix
A for WR5 details.)
2. Auto Enable. May be set to allow the MPSC to automaticaIlyenable the channel transmitter when the
clear-tocsend signal is active and to automatically enable the receiver when the carrier-detect signal isactive. Auto Enable is controleld by bit 5 of WR3. (See
Appendix A for WR3 details.)
During initialization, it is desirable to guarantee that
the externaVstatus latches reflect the latest interface
information:Since up to two state changes are internally stored by the MPSC, at least two Reset Extema1/
Status Interrupt commands must be issued. This procedure is most easily accomplished by simply issuing this
reset command whenever the pointer register is set during initialization.
An MPSC initialization procedure (MPSC$RX$INIT)
for asynchronous communication is listed in Appendix
B. Figure 5 illustrates typical MPSC initialization parameters for use with this procedure.
call MPSC$RX$INIT(41, 1,1,0,1, 3,1,1, 3,1,1,0,1);
initializes the 8274 at address 41 as follows:
X16 clock rate
1 stop bit
Odd parity
8-bit characters
(Txand Rx)

Enable transmitter
and receiver
Auto enable set
OrR and RTS set
Break transmission disabled

Figure 5. Sample 8274 Initialization Procedure
for Polled Operation

2-356

inter

AP-134

Polled Operation
In the polled mode, the processor must monitor the
MPSC status by testing the appropriate bits in the read
register. Data available, status, and error conditions are
represented in RRO and RRI for channels A and B. An
example of MPSC-polled transmitter/receiver routines
are given in Appendix B. The following routines are
detailed:
1. MPSC$POLL$RCV$CHARACTER-This procedure receives a character from the serial data link.
The routine waits until the character-available flag in
RRO has been set. When this flag indicates that a
character is available, RRI is checked for errors
(overrun, parity, or framing). If an .error is detected, the character in the MPSC receive buffer
must be read and discarded and the error routine
(RECEIVE$ERROR) is called. If no receive errors
have been detected, the character is input from the
8274 data port and returned to the calling program.
MPSC$POLL$RCV$CHARACTER requires three
parameters-the address of the 8274 channel data
port (data$port), the address of the 8274 channel
command port (cmd$port), and the address ofa byte
variable in which to store the received character
(character$ptr).
2. MPSC$POLL$TRAN$CHARACTER-This procedure transmits a character to the serial data link.
The routine waits until the transmitter-buffer-empty
flag has been set in RRO before writing the character
to the 8274.
.
MPSC$POLL$TRAN$CHARACTER
requires
three parameters-the address of the 8274 channel
data port (data$port), the address of the 8274 channel command port (cmd$port), and the character of
data tha~ is to be transmitted (character).
3. RECElVE$ERROR-This procedure ·processes receiver errors. First, an Error Reset command is written to the affected channel. All additional error processing is dependent on the specific application. For
example, the receiving device may immediately request retransmission of the character or wait until a
message has been completed.
RECEIVE$ERROR requires two parameters-the
address of the affected 8274 command port
(cmd$port) and the error status (status) from 8274
register RRI.

Interrupt-Driven Operation
In an interrupt-driven environment, all receiver operations are reported to the system processor by means of
interrupts. Once a character has been received and assembled, the MPSC interrupts the system processor.
The system processor must then read the character
from the MPSC data buffer and clear the current interrupt. During transmission, the system processor starts

serial I/O by writing the first character of a message to
the MPSC. The MPSC interrupts the system processor
whenever the next character is required (i.e., when the
transmitter buffer is empty) and the processor responds
by writing the next character of the message to the
MPSC data port for the appropriate channel.
By using interrupt-driven I/O, the MPSC proceeds independently of the system processor, signalling the
processor only when characters are required for transmission, when characters are received from the data
link, or when errors occur. In this manner, the system
processor may continue execution of other tasks while
serial I/O is performed concurrently.

Interrupt Configurations
The 8274 is designed to interface to 8085- and 8086c
type processors in much the same manner as the 8259A
is designed. When operating in the 8085 mode, the 8274
causes a "call" to a prespecified, interrupt-service routine location. In the 8086 mode, the 8274 presents the
processor with a one-byte interrupt-type number. This
interrupt-type number is used to ''vector'' through the
8086 interrupt service table. In either case, the interrupt service address or interrupt-type number is specified during MPSC initialization.
To shorten interrupt latency, the 8274 can be programmed to modify the prespecified interrupt vector so
that no software overhead is required to determine the
cause of an interrupt. When this "status affects vector"
mode is enabled, the following eight interrupts are differentiated automatically by the 8274 hardware:
1. Channel B Transmitter Buffer Empty.
2. Channel B ExternaVStatus Transition.
3. Channel B Character Available.
4. Channel B Receive Error.
5. Channel A Transmitter Buffer Empty.
6. Channel A External/Status Transition.
7. Channel A Character Available.
8. Channel A Receive Error.

Interrupt Sources/Priorities
The 8274 has three interrupt sources for each channel:
1. Receiver (RxA, RxB). An interrupt is initiated when
a character is ·available in the receiver buffer or when
a receiver error (parity, framing, or overrun) is detected.
2. Transmitter (TxA, TxB). An interrupt is initiated
when the transmitter buffer is empty and the 8274 is
ready to accept another character for transmission.

2-357

AP-134

3. External/Status (ExTA, ExTB). An interrupt is initiated when one of the external/status conditions
(CDE, CTS, SYNDET, BREAK) changes state.
The 8274 supports two interrupt priority orderings (selectable during MPSC initialization) as detailed in Appendix A, WR2" CH-A.

Interrupt Initialization
In addition to the initialization parameters required for
polled operation, the following parameters must be supplied to the 8274 to specify,interrupt operation:
I. Transmit, Interrupt Enable. Transmitter-buffer-empty interrupts are separately enabled by bit 1 of WR I.
(See Appendix A for WRI details.)
2. Receive Interrupt Enable. Receiver interrupts are
separately enabled in one of three modes: a) interrupt
on first received character only and on receive errors
(used for message-oriented transmission systems), b)
interrupt on all received characters and on receive
errors, but do not interrupt on parity errors, and c)
interrupt on all received characters and on receive
errors (including parity errors). The ability to separately disable parity interrupts can be extremely useful when transmitting messages. Since the parity error bit in RRI is latched, it will not be reset until an
error reset operation is performed. Therefore, the
parity error bit will be set if any parity errors were
detected in a multi-character message. If this mode is
used, the serial I/O software must poll the parity
error bit at the completion of a message, and issue an
error reset if appropriate. The receiver interrupt
mode is controlled by bits 3 and 4 of WRI. (See
Appendix A for WRI details.)

3. External/Status Interrupts. External/Status interrupts can be separately enabled by bit 0 ofWRl. (See
Appendix A for WRI details.)
4. Interrupt Vector. An eight-bit interrupt-service routine location (8085) or interrupt type (8086) is specified through WR2 of channel B. (See Appendix A
for WR2 details.) Table 3 lists interrupt vector addresses generated by the 8274 in the "status affects
vector" mode.
5. "Status Affects Vector" Mode. The 8274 will automatically modify the interrupt vector if bit 3 ofWRI
is set. (See Appendix A for WRI details.)
6. System Configuration. Specifies the 8274 data transfer mode. Three configuration modes are available:
a) interrupt-driven operation for both channels, b)
DMA operation for both channels, and c) DMAoperation for channel A, interrupt-driven operation for
channel B. The' system configuration is specified by
means of bits 0 and 1 of WR2 (channel A). (See
Appendix A for WR2 details.)
7. Interrupt Priorities. The 8274 permits software specification of receive/transmit priorities by means of
bit 2 of WR2 (channel A). (See Appendix A for
WR2 details.)
8. Interrupt Mode. Specifies whether the MPSC is to
operate in a non-vectored mode (for use with an external interrupt controller), in an 8086-vectored
mode, or in an 808S-vectored mode. This parameter
is specified through bits 3 and 4 of WR2 (channel
A). (See Appendix A for WR2 details.)
An MPSC interrupt initialization procedure
(MPSC$INT$INIT) is listed in Appendix C.

2-358

inter

AP-134

Table 3. MPSC-Generated Interrupt Vectors in "Status Affects Vector" Mode

'/2

8086
Interrupt Type

Original Vector
(Specified during
Initialization)
Interrupt
Condition

8085
Interrupt Location

Channel B Transmitter
Buffer Empty

Channel B External/Status
Change

Channel B Receiver
Character Available

Channel B Receive Error

Channel A Transmitter
Buffer Empty

Channel A External/Status
Change

Channel A Receiver
Character Available

Channel A Receive Error

Interrupt Service Routines
Appendix C lists four interrupt service procedures, a
buffer transmission procedure, and a buffer reception
procedure that illustrate the use of the 8274 in interrupt-driven environments. Use of these procedures assumes that the 8086/8088 interrupt. vector is set to 20H
and that channel B is used with the "status affects vector" mode enabled.
1. TRANSMIT$BUFFER-This procedure begins serial transmission of a data buffer. Two parameters
are required-a pointer to the buffer (buf$ptr) and
the length of the buffer (buf$length). The procedure
first sets the global buffer pointer, buffer length, and
initial index for the transmitter-interrupt service routine and initiates transmission by writing the first
character of the buffer to the 8274. The procedure
then enters a wait loop until the I/O completion
status is set by the transmit-interrupt service routine
(MPSC$TRANSMIT$CHARACTER$INT).
2. RECElVE$BUFFER-This procedure inputs a line
(terminated by a line feed) from a serial I/O port.
Two parameters are required-a pointer to the input
buffer (buf$ptr) and a pointer to the buffer length
variable (buf$length$ptr). The buffer length will be
set by this procedure when the complete line has
been input. The procedure first sets the global buffer
pointer and initial index for the receiver interrupt
service routine. RECEIVE$BUFFER then enters a
wait loop until the I/O completion status is set by
the receive interrupt routine (MPSC$RECEIVE$CHARACTER$INT).

3. MPSC$TRANSMIT$CHARACTER$INT-This
procedure is executed when the MPSC Tx-bufferempty interrupt is acknowledged. If the current
transmit buffer index is less than the buffer length,
the next character in the buffer is written to the
MPSC data port and the buffer pointer is updated.
Otherwise, the transmission complete status is posted.
4. MPSC$RECEIVE$CHARACTER$INT-This procedure is executed when a character has been assembled by the MPSC and the MPSC has issued a character-available interrupt. If no input buffer has been
set up by RECEIVE$BUFFER, the character is ignored. If a buffer has been set up, but it is full, a
receive overrun error is posted. Otherwise, the received character is read from the MPSC data port
and the'buffer index is updated. Finally, if the received character is a line feed, the reception complete
status is posted.
5. RECEIVE$ERROR$INT-This procedure is executed when a receive error is detected. First, the error conditions are read from RRI and the character
currently in the MPSC receive buffer is read and discarded. Next, an Error Reset command is written to
the affected channel. All additional error processing
is application dependent.
6. EXTERNAL$STATUS$CHANGE$INT-This
procedure is executed when an external status condition change is detected. The status conditions are
read from RRO and a Reset External/Status Interrupt command is issued. Further error processing is
application dependent.

2-359

AP-134

DATA LINK INTERFACE
Serial Data Interface
Each serial I/O channel within the 8274 MPSC interfaces to two data link lines-one line for transmitting
data and one for receiving data. During transmission,
characters are converted from parallel data format (as
supplied by the system processor or DMA device) into
a serial bit stream (with START and STOP bits) and
clocked out on the TxD pin. During reception, a serial
bit stream is input on the RxD pin, framing bits are
stripped out of the data stream, and the resulting character is converted to parallel data format and passed to
the system processor or DMA device.

Data Clocking
As discussed previously, the frequency of data transmission/reception on the data link is controlled by the
MPSC clock in conjunction with the programmed
clock divider (in register WR4). The 8274 is designed to
permit all four serial interface lines (TxD and RxD for
each channel) to operate at different data rates. Four
clock input pins (TxC and RxC for each channel) are
available for this function. Note that the clock rate divider spcified in WR4 is used for both RxC and TxC on
the appropriate channel; clock rate dividers for each
channel are independent.

Modem Control
The following four modem interface signals may be
connected to the 8274:
1. Data Terminal Ready (DTR). This interface signal
(output by the 8274) is software controlled through
bit 7 of WRS. When active, DTR indicates that the
data terminal/computer equipment is active and

ready to interact with the data communications
channel. In addition, this signal prepares the modem
for connection to the communication channel and
maintains connections previously established (e.g.,
manual call origination).
2. Request To Send (RTS). This interface signal (output by the 8274) is software controlled through bit I
of WRS. When active, RTS indicates that the data
terminal/computer equipment is ready to transmit
data. When the RTS bit is reset in asynchronous
mode, the signal does not go high until the transmitter is empty.
3. Clear To Send (CTS). This interface signal (input to
the 8274) is supplied by the modem in response to an
active RTS signaLCTS indicates that the data terminal/computer equipment is permitted to transmit
data. The state of CTS is available to the programmer as bit S of RRO. In addition, if the auto enable
control is set (bit S of WR3), the 8274 will not transmit data bytes until CTS has been activated. If CTS
becomes inactive during transmission of a character,
the current character transmission is completed before the transmitter is disabled.
4. Carrier Detect (CD). This interface signal (input to
the 8274) is supplied by the modem to indicate that a
data carrier signal has been detected and that a valid
data signal is present on the RxD line. The state of
CD is available to the programmer as bit 3 of RRO.
In addition, if the auto enable control is set (bit S of
WR3), the 8274 will not enable the serial receiver
until CD has been activated. If the CD signal becomes inactive during reception of a character, the
receiver is disabled, and the partially received character is lost.
In addition to the above modem interface signals, the
8274 SYNDET input pin for channel A may be used as
a general-purpose input in the asynchronous communication mode. The status of this signal is available to the
programmer as bit 4 of status register RRO.

2-360

inter

AP-134

APPENDIX A
COMMAND/STATUS DETAilS FOR ASYNCHRONOUS
COMMUNICATION
logic and all control registers for the channel. Four extra system clock cycles should
be allowed for MPSC reset time before
any additional commands or controls are
written into the channel.
Command 4 Enable Interrupt on Next Receive Character-if the Interrupt-on-First-Receive
Character mode is selected, this command
reactivates that mode after each complete
message is received to prepare the MPSC
for the next message.
Command 5 Reset Transmitter Interrupt Pending-if
the Transmit Interrupt mode is selected,
the MPSC automatically interrupts data
when the transmit buffer becomes empty.
When there are no more characters to be
sent, issuing this command prevents further transmitter interrupts until the next
character has been completely sent.
Command 6 Error Reset-error latches, Parity and
Overrun errors in RRI are reset.
Command 7 End of Interrupt-resets the interrupt-inservice latch of the highest-priority internal device under service.

Write Register 0 (WRO):

COMMAND/STATUS POINTER
REGISTER POINTER

NULL CoDe
NOT USED IN ASYNCHRONOUS MODES
RESET EXT/STATUS INTERRUPTS
CHANNEL RESET
ENABLE INTERRUPT ON NEXT Rx

CHARACTER
RESET TxlNT PENDING
ERROR RESET

END OF INTDlRUPT ICIo. A .nIy)

NOT useD IN ASYNCHRONOUS MODes

210311-6'

Write Register 1 (WR 1):
02,01,00

Command/Status Register Pointer bits
determine which write-register the next
byte is to be written into, or which readregister the next byte is to be read from.
After reset, the first byte written into either channel goes into WRO. Following a
read or write to any register (except WRO)
the pointer will point to WRO.
05,04,03 Command bits determine which of the basic seven commands are to be performed.
Command 0 Null-has no effect.
Command I Note used in asynchronous modes.
Command 2 Reset External/Status Interrupts-resets
the latched status bits of RRO and reenables them, allowing interrupts to occur
again.
Command 3 Channel Reset-resets the Latched Status
bits of RRO, the interrupt prioritization

2-361

External/Status Interrupt Enable-allows
interrupt to' occur as the result of transitions on the CO, CTS or SYNOET inputs. Also allows interrupts as the result
of a Break/Abort detection and termination, or at the beginning of CRC, or sync
character transmission when the Transmit
Underrun/EOM latch becomes set.
Transmitter Interrupt/OMA Enable-allows the MPSC to interrupt or request a
OMA transfer when the transmitter buffer
becomes empty.
Status Affects Vector--(WRI, 02 active
in channel B only.) If this bit is not set,
then the fixed vector, programmed in
WR2, is returned from an interrupt acknowledge sequence. If the bit is set, then
the vector returned from an interrupt acknowledge is variable as shown in the Interrupt'Vector Table.

inter

AP-134

Write Register 1 (WR1):

Write Register 2 (WR2): Channel A
MSB
LSB

MSB

Loo: °1~1~:ool~lm:ool

107 1 0 10510,:0,10'1011001
'--..,---I

'--..,---I

0
0
,
,

EXT INTERRUPT
ENABLE

r.INTERRUPTI
DMA ENABLE

1 VARIABLE
0 FIXED
0
0
1
1

0
1
0
1

RxiNTIDMA DISABLE
RxlNT ON FIRST CHAR OR SPECIAL
CONDITION
INT ON ALL Ax CHAR (PARITY AFFECTS
VECTOR)OR SPECIAL CONDITION

0
1
0
1

INT ON ALL Rx CHAR (PARITY DOES
NOT AFFECT VECTOR) OR SPECIAL

CONDITION

8085 MODE 1

8086188 MODE
ILLEGAL

1
DISABLE

PIN 10

D4,D3

o1
I 0

1 1

D6
D7

= SVNDET B

J?IN 10

= RTS B

NOTE:
210311-8
'External Status Interrupt-'-only if EXT Interrupt Enable
(WR1; DO) is set.

210311-7

VECTORED INTERRUPT

NON VECTORED INTERRUPT

o
ENABLE. 0

0- PRIORITY RxA >TxA >RxB
TxB>EXTA'>EXTS'

MUST BE ZERO

MUST SEZERO

ILLEGAL

80B5 MODE 2

1 WAIT ON Rx, 0 '" WAIT ON 1x
WAIT ENABLE

A OMA. B INT
BOTH DMA

VECTOR

0
0
1
1

BOTH INTERRUPT

1 = PRIORITY RxA>RxB>TxA>
rxa>EXTA'>EXTS'

VECTOR

STATUS AFFECTS

VECTOR(CH B CNt.YI
(NULlCODECH AI

0
1
0
1

Receive Interrupt Mode.
Receive Interrupts/DMA Disabled. '
Receive Interrupt on First Character Only
or Special Condition.
Interrupt on All Receive Characters of
Special Condition (parity Error is a Special Receive Condition).
Interrupt on All Receive Characters or
Special Condition (Parity Error is not a
Special Receive Condition).
Wait on Receive/Transmit-when the following conditions are met, the RDY pin is
activated, otherwise it is held in the HighZ state. (Conditions: Interrupt Enabled
Mode, Wait Enabled, CS = 0, AO = 0/1,
and Al = 0). The RDY pin is pulled low
when the transmitter buffer is full or the
receiver buffer is empty and it is driven
High when the transmitter buffer is empty
or the receiver buffer is full. The RDY A
and RDYB may be wired or connected
since only one signal is active at anyone
time while the other is in the High Z state.
Must be Zero.
Wait Enable-enables the wait function.

m,DO

o1
10
1 1

2-362

System Configuration-These specify the
data transfer from MPSC channels to the
CPU, either interrupt or DMA based.
Channel A and Channel B both use interrupts.
Channel A uses DMA, Channel B uses interrupt.
Channel A and Channel B both use
DMA.
Illegal Code.
Priority-this bit specifies the relative priorities of. the internal MPSC interrupti
DMA sources.
(Highest) RxA, TxA, RxA, RxB,
TxBExTA, ExTB (Lowest).
(Highest) RxA, RxB, TxA, TxB, ExTA,
ExTB (Lowest).

inter
05,04,03

100

101

1 I 0

D6
07

AP-134

Interrupt Code-specifies the behavior of
the MPSC when it receives an interrupt
acknowledge sequence from the CPU. (See
Interrupt Vector Mode Table.)
Non-vectored interrupts-intended for
use with an external interrupt controller
such as the 8259A.
.8085 Vector Mode I-intended for use as
the primary MPSC in a daisy-chained priority structure.
8085 Vector Mode 2-intended for use as
any secondary MPSC in a daisy-chained
priority structure.
8086/88 Vector Mode-intended for use
as either a primary or secondary in a daisy-chained priority structure.
Must be Zero.

Write Register 3 (WR3):
MSB

LSB

R.ENABLE

L.-._ _ _ _ NOT USED IN

ASYNCHRONOUS
MODES

' - - - - - - - - - - A U T O ENABLES

R. 5 BITS/CHAR

Pin 10 = RTSB'
Pin 10 = SYNDETB.

R.7 BITSJCHAR
R. 6 BITS/CHAR
R.8 BITSJCHAR

Write Register 2 (WR2): Channel B
MSB

LSB

V7 : V6 : V5 : V4 : V3 : V2:

210311-10

L. .

V1:

Vector

07-00

210311-9

Interrupt vector-this register contains
the value of the interrupt vector placed on
the data bus during acknowledge sequences.

07,06
00

oI
I 0
I I

2-363

Receiver Enable-a one enables the receiver to begin. This bit should be set only
after the receiver has been initialized.
Auto Enables-a one written to this bit
causes CD to be an automatic enable signal for the receiver and CTS to be an automatic enable signal for the transmitter. A
zero written to this bit limits the effect of
CD and CTS signals to setting/resetting
their corresponding bits in the status register (RRO).
Receiver Character length.
Receive 5 Data bits/character.
Receive 7 Data bits/character.
Receive 6 Data bits/character.
Receive 8 Data bits/character.

Intel

AP·134

Write Register 4 (WR4):

Write Register S (WRS):

0
0

ENABLE PARITY
DISABLE PARITY

OT USED IN
ASYNCHRONOUS MODES
RTS

EVEN PARITY
ODD PARITY

' - - - - N O T USED IN
ASYNCHRONOUS MODES

' - - - - - - T x ENABLE

ENABLE SYNC MODES

1 STDPBIT

1.5 STOP BITS

2 STOP BITS

'--_ _ _ _:--_SEND BREAK

T.5 BITS OR LESS/CHAR
T. 7 BITS/CHAR
T. 6 BITS/CHAR

NOT USED IN ASYNCHRONOUS MODES

Tx 8 BITS/CHAR

' - - - - -_ _ _ _ _ _ _ _ DTR

XI CLOCK

210311-12
X16 CLOCK

X32CLOCK
X64CLOCK

210311-11

D3,D2

o0
o1
1 0
1 1
07,D6

00
o1
10
1 1

Parity-a one in this bit causes a parity bit
to be added to the programmed number of
data bits per character for both the transmitted and received character. If the
MPSC is programmed to receive 8 bits per
character, the parity bit is not transferred
to the microprocessor. With other receiver
character lengths, the parity bit is transferred to the microprocessor.
Even/Odd Parity-if parity is enabled, a
one in this bit causes the MPSC to transmit and expect even parity, and zero causes it to send and expect odd parity.
Stop Bits.
Selects synchronous modes.
Async mode, 1 stop bit/character.
Async mode, 1'12 stop bits/character.
Async mode, 2 stop bits!character.
Clock mode-selects the clock/data rate
multiplier for both the receiver and the
transmitter. If the Ix mode is selected, bit
synchronization must be done externally.
Clock rate = Data rate X 1.
Clock rate = Data rate X 16.
Clock rate = Data rate X 32.
Clock rate = Data rate X 64.

D6,D5
00
o1
10
1 1

Request to Send-a one in this bit forces
the RTS pin active (low) and zero in this
bit forces the RTS pin inactive (high).
When the RTS bit is reset in asynchronous
mode, the signal does not go inactive until
the transmitter is empty.
Transmitter Enable-a zero in this bit
forces a marking state on the transmitter
output. If this bit is set to zero during data
or sync character transmission, the marking state is entered after the character has
been sent. If this bit is set to zero during
transmission of a CRC character, sync or
flag bits are substitute4 for the remainder
of the CRC bits.
Send Break-a one in this bit forces the
transmit data low. A zero in this bit allows
normal transmitter operation.
Transmit Character length.
Transmit 5 or less bits/character.
Transmit 7 bits/character.
Transmit 6 bits/character.
Transmit 8 bits/character.

Bits to be sent must be right justified, least-significant
bit first, e.g.:
D7 D6 D5 D4 D3 D2 Dl DO

2-364

B5 B4 B3 B2 Bl BO

infef

AP-134

Read Register 0 (RRO):
MSB

Inl PENDING (CHA ONLY)
' - - - - - Tx BUFFER EMPTY
L -_ _ _ _ _

L-_____________

CARRIER DETECT
SYNDET

'--_ _ _ _ _ _ _ _ _ CTS

EXTERNAL STATUS
INTERRUPT MODE

'--_ _ _ _ _ _ _ _ _ _ _ NOT USED IN
ASYNCHRONOUS MODES
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ BREAK

210311-13

Receive Character Available-this bit is
set when the receive FIFO contains data
and is reset when the FIFO is empty.
Interrupt Pending-This Interrupt-Pending bit is reset when an EO! command is
issued and there is no other interrupt request pending at that time. In vector
mode, this bit is set at the falling edge of
the second INTA in an INT A cycle for an
internal interrupt request. In non-vector
mode, this bit is set at the falling edge of
RD input after pointer 2 is specified. This
bit is always zero in Channel B.
Transmit Buffer Empty-This bit is set
whenever the transmit buffer is empty except when CRC characters are being sent
in a synchronous mode. This bit is reset
when the transmit buffer is loaded. This
bit is set after an MPSC reset.
Carrier Detect-This bit contains the state
of the CD pin at the time of the last
change of any of the External/Status bits
(CD, CTS, Sync/Hunt, Break/Abort, or
Tx Underrun/EOM). Any change of state
of the CD pin causes the CD bit to be
latched and causes an External!Status interr~ This bit indicates current state of
the CD pin immediately following a Reset
External!Status Interrupt command.
SYNDET-In asynchronous modes, the
operation of this bit is similar to the CD
status bit, except that it shows the state of
the SYNDET input. Any High-to-Low
transition on the SYNDET pin sets this
bit, and causes an External!Status interrupt (if enabled). The Reset External!

2-365

Status Interrupt command is issued to
clear the interrupt. A Low-to-High transition clears this bit and sets the External!
Status interrupt. When the External!
Status interrupt is set by the change in
state of any other input or condition, this
bit shows the inverted state of the
SYNDET pin at time of the change. This
bit must be read immediately following a
Reset External/Status Interrupt command
to read the current state of the SYNDET
input.
Clear to Send-this bit contains the inverted state of the CTS pin at the time of
the last change of any of the External!
Status bits (CD, CTS, Sync/Hunt, Break/
Abort, or Tx Underrun/EOM). Any
change of state of the CTS pin causes the
CTS bit to be latched and causes an External!Status interrupt. This bit indicates the
inverse of the current state of the CTS pin
immediately following a Reset External!
Status Interrupt command.
Break-in the Asynchronous Receive
mode, this bit is set when a Break sequence (null charact.er plus framing error)
is detected in the data stream. The External!Status interrupt, if enabled, is set
when break is detected. The interrupt
service routine must issue the Reset External!Status Interrupt command (WRO,
Command 2) to the break detection logic
so the Break sequence termination can be
recognized.

inter

Ap·134

Read Register 1 (RR1):

~----NOT

USED IN ASYNCHRONOUS MODES

L-------____ PARITy ERROR
'-------------RxOVERRUNERROR
~

_ _ _ _ _ _ _ _ _ _ _ _ _ _ CRCIFRAMING ERROR,

' - - - - - - - " - -_ _ _ _ _ _ _ _ _ _ NOT USED IN ASYNCHRONOUS MODES
210311-14

The Break bit is reset when the termination of the
Break sequence is detected in the incoming data stream_
The termination of the Break sequence also causes the
External/Status interrupt to be set. The Reset External/Status Interrupt command must.be issued to enable
the break detection logic to look for, the next Break
sequence. A single, extraneous null character is present
in the receiver after the termination of a break; it
should be read and discarded.
DO
All sent-this bit is set when all characters
have been sent. It is reset when characters
are in the transmitter. In, synchronous
modes, this bit is always set.

Parity Error-if parity is enabled, this bit
is set for, received characters whose parity
does not' match the programmed sense
(Even/Odd). This bit is latched. Once an
error occurs, it remains set until the Error
Reset command is written.
Receive Overrun Error_this bit indicates
that the receive FIFO has been overloaded
by the receiver. The last character in the
FIFO is overwrittenand flagged with this
error. Once the overwritten character is
read, this error condition is latched until

Read Register 2 (RR2):
MSB

LSB

V7: V6: V5 : V4' : V3' : V2' : V1':

vo'l

'Variable In
LI..;.nt..;.e...
rr..;.up~t"______ Status Affects
Vector
Vector Mode (WR1; D2)
210311-15

RR2

reset by the Error Reset command~ If the
MPSC is in the "status affects vector"
mode, the overrun causes a Special Receive ErrorVector.
Framing Error-in async modes, a one in
this bit indicates a receive framing error.
It can be reset by issuing an Error Reset
command.
Channel B

D7-DO

2-366

Interrupt vector-contains the interrupt '
vector programmed into WR2. If the
"status affects vector" mode is selected, it
contains the modified vector. (See WR2.)
RR2 contains the modified vector for the
highest priority interrupt pending. If no
interrupts are pending, the variable bits in
, the vector are set to one. May be read
from Channel B only.

intJ

AP-134

APPENDIX B
MPSC-POLLED TRANSMIT/RECEIVE CHARACTER
ROUTINES

MPSC$RX$INIT: procedure (cmd$port,
clock$rate,stop$bits,parity$type,parity$enable,
rX$char$length,rxSenable,auto$enable,
tx$char$length,tx$enable,dtr,brk,rts) :
declare cmd$port
clock$rate
stop$bits
parity$type
parity$enable
rx$char$length
rx$enable
auto$enable
tx$char$length
tx$enable
dtr
brk
rts

output(cmd$port)=30H:

byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte:

/" channel reset "/

/" point to WR4 */
/* set clock rate,. stop bits, and parity information */

output(cmd$port)=14H:

output(cmd$port)=shl(clock$rate,6) or shl(stop$bits,2) or shl(parity$type,l)
or parity$enable:
output(cmd$port)=13H:
/* point to WR3 */
/* set up receiver parameters *1
output(cmd$port)=shl(rx$char$length,6) or rx$enable or shl(auto$enable,5):
output(cmd$port) =15H:
/* point to WR5 */
/* set up transmitter parameters "/
output(cmd$port)=shl(tx$char$length,S) or shl(tx$enable,3) or shl(dtr,7)
or shl(brk,4) or shl(rts,l):
end MPSC$RX$I~IT:
210311-16

2-367

intJ

AP-134

'lPSC $ PO LL$RCVSClIl\HACTER:

declare

d~taSport

cmd$port
character$ptr
character
5 ta tu s
declare char$avail
rcv$error

p rocedur e (du ta$ por t , cmdS por t , c tIL) r ae te r Spt r)

b·:,t'"!;

byte,
byte,
pointer,
based character$ptr byte,
byte;
literally '1',
literally '70H';

/* wait for input character ready */
while (input(cmd$port) and char$avail)

<> 0 do; end;

1* check for errors in received character
output(cmd$port)=l;
i f (status:=input(cmd$port) and rcv$error)
then do;
character=input (data$port) :
call RECElVE$ERROR(cmd$port,status);
return 0:
end;
else do;
character=input (data$port) ;
return OFFH;
end;

/* point to RRI */
/0 react character to clear MPSC 0/
/* clear receiver errors */
/* error return - no character avail */

/* good return - character avail */

end MPSC$POLL$RCV$CHARACTER;

MPSC$POLL$TRAN$CHARACTER: procedure(data$port,cmd$port,character);
declare data$port
cmd$por t
character

byte,
byte,
byte;

declare tx$buffer$empty literally '4';

/* wait for transmitter buffer empty 0/
while not (input(cmd$port) and tx$buffer$empty) do; end:

1* output character */
output(data$port)=character;
end MPSC$POLL$TRAN$CHARACTER;

RECElVE$ERROR: procedure(cmd$part,status);
declare cmd$part
status

byte,
byte;

autput(cmd$port)=30H;

1* error reset 0/

/* *** other application dependent
error processing should be placed here

end RECElVE$ERROR;
210311-17

2-368

intJ

AP-134

TRANSMIT$BUFFER: procedure(buf$ptr,buf$length)
declare
buf$ptr
buf$length

pointer,

byte;

/* set up transmit buffer pointer and buffer length in global variables for
interrupt service */
tX$buffer$ptr;buf$ptr;
transmit$length=buf$length;
transmit$status=not$complete;
output(data$port);transmit$buffer(O);
transmit$index=l;

/* setup status for not complete */
/* transmit first character */

/* first character transmitted */

/* wait until transmission complete or error detected */

while transmit$status = not$complete do; end;
if transmit$status <> complete
then return false;
else return true~

end TRANSMIT$BUFFER;

RECEIVE$BUFFER: procedure tbuf$ptr, buf$length'$ptr) ;
declare
buf$ptr
pointer,
buf$length$ptr pointer,
buf$length'
based buf$length$ptr byte;
/* set up receive buffer pointer in global variable for interrupt service */
rx$buffer$ptr=buf$ptr;
receive$index=O;

receive$status=not$complete;

j* wait until buffer received */

/* set status to not complete */

while receive$status = not$complete do; end;
buf$length=receive$length;
if receive$status = complete
then return true:
else return false;
end RECEIVE$BUFFER;
210311-18

2-369

inter

AP-134

APPENDIX C
INTERRUPT-DRIVEN TRANSMITIRECEIVE SOFTWARE

declare
/* global variables for buffer manipulation */

rx$buffer$ptr
pointer,
/* pointer to receive buffer */
receive$buffer based rx$buffer$ptr(128) byte,
byte initial (0),
/* indicates receive buffer status *1
receive$index
byte,
/* current index into receive buffer */
byte,
receive$length
/* length of final receive buffer */

receive$status

tx$buffer$ptr
pointer,
/* pointer to transmit buffer */
transmit$buffer based tx$buffer$ptr(128) byte,
transmit$status
byte initial(O),
/* indicates transmit buffer status */
transmit$index
byte,
1* current index into transmit buffer */
byte,
transmit$length
/* length of buffer,to be transmitted */
cmd$port
data$port
a$cmd$port
b$cmd$port
line$feed
not$complete
complete
overrun

channel$reset
error$reset
reset$ext$status

literally
literally
literally
li'terally
literally
literally
literal:!_y
li terally

'4 3R' ,
'41R' ,
'42R',
'4 3R' ,
'OAR',
"0"',

'OFFR',
"'1',

1 terally '18R' ,
\ 1 terally '30R' ,
1 terally 'lOR':
210311-20

2-370

inter

Ap· 134

MPSC$INT$INIT: procedure (clock$rate,stop$bits,parity$type,parity$enable,
rx$char$length,rx$enable,auto$enable,
tx$char$length,tx$enable,dtr,brk,rts,
ext$en,tx$en,[x$en,stat$affects$vector,
config,priority,vector$int$mode,int$vector) i
declare
clock$rate
stop$bits
parity$type
parity$enable
rx$char$length
rx$enable
auto$enable
tx$char$length
tx$enable
dtr
brk
rts
ext$en
tx$en
rx$en
stat$aff$vector
config
priority
vector$int$mode
int$vector

byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte,
byte;

output(b$cmd$port)=channel$reset;

/* 2-bit
/* 2-bit
/* I-bit
/* I-bit
/* 2-bit
/* l-bit
/* l-bit
/* 2-bit
/* I-bit
/* I-bit
/* I-bit
/* l-bit
/* I-bit
/* I-bit
/* 2-bit
/* l-bit
/* 2-bit
/* l-bit
/* 3-bit
/* .S-bit

code for clock rate divisor */
code for number of stop bits */
parity type */
parity enable */
receive character length */
receiver enable */
auto enable flag */
transmit character length */
transmitter enable */
status of DTR pin */
data link break enable */.
status of RTS pin */
external/status enable */
Tx interrupt enable */
Rx interrupt enablejmode OJ
status affects vector flag */
system config - intjDMA *j
priority flag *j
interrupt mode code */
interrupt type code */

/* channel reset */

output(b$cmd$port)=l4H;
/* point to WR4 */
/* set clock rate, stop bits, and parity information */
output(b$cmd$port)=shl(clock$rate,6) or shl(stop$bits,2) or shl(parity$type,l)
or parity$enablej
output(b$cmd$port)=13H;
/* point to NR3 */
1* set up receiver parameters */
output(b$cmd$port)=shl(rx$char$length,6) or rx$enable or shl(auto$enable,S);
output(b$cmd$port)=lSH;
/* point to WRS */
/* set up transmitter parameters *1
output(b$cmd$port)=shl(tx$char$lenqth,S) or shl(tx$enable,3) or shl(dtr,7)
or shl(brk,4) or shl(rts,l);
output(b$cmd$port)=12H;
j* set up interrupt vector */
output(b$cmd$port)=int$vector;

j* point to WR2

output(a$cmd$port)=12H;
/* point to WR2, channel A */
/* set up interrupt modes */
output(a$cmd$port)=shl(vector$int$mode,3) or shl(priority,2) or config;
output(b$cmd$port)=llH;
j* point to WRl *j
/* set up interrupt enables */
output(b$cmd$port)=shl(rx$en,3) or shl(stat$aff$vector,2) or shl(tx$en,l)
or ext$en:
end MPSC$INT$INIT;
210311-21

2-371

AP-134

MPSC$RECEIVESCIlARACTERSINT: procedure interrupt 2211,

/* ignore input if no open buffer */
if receive$status <> not$complete then

return~

1* check for receive buffer overrun */
if receive$index = 128
then receive$status=overrun:

else do;
/* read character from MPSC and place in buffer - note that the
parity of the character must be masked off during this step if
the character is less than 8 bits (e.g., ASCII)
*/
receive$buffer (receive$index) ,character=input(data$port) and 7FH,
receive$index=receive$index+l:
1* update receive buffer index */

/* check for line feed to end line */
if character = line$feed
then do; receive$length=receive$indexi receive$status=complete: end:
end,
end MPSC$RECElVE$CHARACTER$INT,

MPSC$TRANSMIT$CHARACTER$INT: procedure interrupt 20H,

check for more characters to tr,ansfer

if transmit$index < transmit$length
then do,
/* write next character from buffer to MPSC */
Qutput(data$port)=transmit$buffer(transmit$index) ,
transmit$index=transmit$index+l;
/* update transmit buffer index */
end;
else transmit$status=complete;

end MPSC$TRANSMIT$CHARACTER$INT,

RECElVE$ERROR$INT: procedure interrupt 23H,
declare
temp

byte,

output(cmd$port)=l,
receive$status=input(cmdSport) ,
temp=input(data$port) ,
Qutput{cmd$port)=error$reset;
/*

***

/* temporary character storage */
/* point to RRl */

/* discard character */
/* send error reset */

other application dependent
error processing should be placed here

* ** * /

end RECElVE$ERROR$INT,

EXTERNAL$STATUS$CHANGE$INT: procedure interrupt 21H,
transmit$status=input(cmdsport)
output(cmd$port)=reset$ext$status,

/* input status change information */

/* *** other application dependent
error processing should be placed here

*** * /

end EXTERNAL$STATUS$CHANGE$INT,
210311-19

2-372

intJ

AP-134

APPENDIX D
APPLICATION EXAMPLE USING SDK-S6
This application example shows the 8274 in a simple
iAPX-86/88 system. The 8274 controls two separate
asynchronous channels using its internal interrupt controller to request all data transfers. The 8274 driver
software is described which transmits and receives data
buffers provided by the CPU. Also, status registers are
maintained in system memory to allow the CPU to
monitor progress of the buffers and error conditions.

THE HARDWARE INTERFACE
Nothing could be easier than the hardware design of an
interrupt-driven 8274 system. Simply connect the data
bus lines, a few bus control lines, supply a timing clock
for baud rate and, voila, it's done! For this example, the
ubiquitous SDK-86- is used as the host CPU system.
The 8274 interface is constructed on the wire-wrap area
provided. While discussing the hardware interface,
please refer to Diagram 1.
Placing the 8274 on the lower 8 bits of the 8086 data
bus allows byte-wide data transfers at even I/O ad~
dresses. For simplicity, the 8274's CS input is generated
by combining the M/IO select line with address line A 7
via a 7432. This places the 8274 address range in multiple spots within the 8086 I/O address space. (While
fine for this example, a more complete address decoding is recommended for actual prototype systems.) The
8086's Al and A2 address lines are connected to the AO
and Al 8274 register select inputs respectively. Although other port assignments are possible because of
the overlapping address spaces, the following I/O port
assignments are used in this example:
Port Func~lon
Data channel A
Command/status A
Data channel 8
Command/status B

I/O Address
OOOOH
0002H
0004H
0006H

To connect the 8274's interrupt controller into the system an inverter and pull-up resistor are needed to convert the 8274's active-low, interrupt-request output,
INT, into the correct polarity for the 8086's INTR interrupt input. The 8274 recognizes interrupt-acknowledge bus cycles by connecting the INTA (INTerrupt
Acknowledge) lines of the 8274 and 8086 together.

The 8274 ReaD and WRite lines directly connect to the
respective 8086 lines. The RESET line requires an inverter. The system clock for the 8274 is provided by the
PCLK (peripheral clock) output of the 8284A clock
generator.
On the 8274's serial side, traditional 1488 and 1489 RS232 drivers and receivers are used for the serial interface. The onboard baud rate generator supplies the
channel baud rate timing. In this example, both sides of
both channels operate at the same baud rate although
this certainly is not a requirement. (On the SDK-86,
the baud rate selection is hard-wired thru jumpers. A
more flexible approach would be to incorporate an
8253 Programmable Interval Timer to allow softwareconfigurable baud rate selection.)
That's all there is to it. This hardware interface is completely general-purpose and supports all of the 8274
features except the DMA data transfer mode which requires an external DMA controller. Now let's look at
the software interface.

SOFTWARE INTERFACE
In this example, it is assumed that the 8086 has better
things to do rather than continuously run a serial channel. Presenting the software as a group of callable procedures lets the designer include them in the main body
of another program. The interrupt-driven data transfers
give the effect that the serial channels are handled in
the background while the main program is executing in
the foreground. There are five basic procedures: a serial
channel initialization routine and buffer handling routines for the transmit and receive data buffers of each
channel. Appendix D-l shows the entire software listing. Listing line numbers are referenced as each major
routing is discussed.
The channel initialization routine (INITIAL 8274),
starting with line #203, simply sets each channel into a
particular operating mode by loading the command
registers of the 8274. In normal operation, once these
registers are loaded, they are rarely changed. (Although
this example assumes a simple asynchronous operating
mode, the concept is easily extended for the byte- and
bit-synchronous modes.)

2-373

(
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CONNECTOR

ADDRESS
BUS EXPANSION
CONNECTOR

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LED DISPLAY

210311-22
(For detailed description on SDK-86, refer to SDK-86 MCS-86 System Design Kit Assembly ManuaL)

inter

AP-134

SDK·86
EXPANSION
BUS

5V
751488

40
VCC
28

INTR

Rij
WR
INTA
PCLK

RTSA

RxDA

INTA

CHANNEL
A

CLK
CDA

RESET
12

CTSA

RST

TxDA
INT

15
16

MilO

DB7

DTRA

DB6
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DB4
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DB2

RxDB

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CHANNEL
B

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COB

Cs
DTRB

A7
25

TxCA

RxCA
TxCB

PI~:

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J
210311-23

Figure 0-1. 8274/S0K-86 Hardware Interface

The channel operating modes are contained in two tables starting with line # 163. As the 8274 has only one
command register per channel, the remaining seven
registers are loaded indirectly through the WRO (Write
Register 0) register. The first byte of each table entry is
the register pointer value which is loaded into WRO
and the second byte is the value for that particular register.
The indicated modes set the 8274 for asynchronous operation with data characters 8 bits long, no parity, and
2 stop bits. An X16 baud rate clock is assumed. Also
selected is the "interrupt on all RX character" mode
with a variable interrupt vector compatible with the
8086/8088. The transmitters are enabled and all model
control lines are put in their active state.

In addition to initializing the 8274, this routine also sets
up the appropriate interrupt vectors. The 8086 assumes
the first lK bytes of memory contain up to 256 separate
interrupt vectors. On the SDK-86 the initial 2K bytes
of memory is RAM and therefore must be initialized
with the appropriate vectors. (In a prototype system,
this initial memory is probably ROM, thus the vector
set-up is not needed.) The 8274 supplies up to eight
different interrupt vectors. These vectors are developed
from internal conditions such as data requests, status
changes, or error conditions for each channel. The initialization routine arbitrarily assumes that the initial
8274 vector corresponds to 8086 vector location 80H
(memory location 200H). This choice is arbitrary since
the 8274 initial vector location is programmable.

2-375

inter

AP-134

Finally, the initialization routine sets up the status and
flag in RAM. The meaning and use of these locations
are discussed later.

The received data service routines, starting at lines
#402 and #485, simply place the received character in
the buffer after first issuing the EOI command. The
character is then compared to an ASCII CR. An ASCII CR causes the routine to set the receiver ready flag,
RX_READY _CHx, and to disable the receiver. The
CPU can interrogate this flag to determine when the
buffer contains a new line of data. The receive buffer
pointer, ~POINTER-CHx, points to the last received character and the receive counter, ~COUN
TER-CHx, contains the length.

Following the initialization routine are those for the
transmit commands (starting with line #268). These
commands assume that the host CPU has initialized the
publicly declared variables for the transmit buffer
pointer, TX_POINTER-CHx, and the buffer length,
T~LENGTH_CHx. The transmit command routines simply clear the transmitter empty flag, TX EMPTY CHx, and load the first character of the buffer into
the transmitter. It is necessary to load the first character in this manner since transmitter interrupts are generated only when the 8274's transmit data buffer becomes empty. It is the act of becoming empty which
generates the interrupt not simply the buffer being empty, thus the transmitter needs one character to start.

That completes our discussion of the command routines and their associated interrupt service routines. Although not used by the commands, two additional service routines are included for completeness. These routines handle the error and status-change interrupt vectors.
The error service routines, starting at lines #427 and
#510, are vectored to if a special receive condition is
detected by the 8274. These special receive conditions
include parity, receiver overrun, and framing errors.
When this vector is generated, the error condition is
indicated in RRl (Read Register I). The error service
routine issues an EOI command, reads RRI and places
it in the ERRO~SG_CHx variable, and then issues a reset error command to the 8274. The CPU can
monitor the error message location to detect error conditions. The designer, of course, can supply his own
error service routine.

The host CPU can monitor the transmitter empty flag,
T~EMPTY_CHx, in order to determine when
transmission of the buffer is complete. Obviously; the
CPU should only call the command routine after first
checking that the empty flag is set.
After returuing to the main program, all transmitter
data transfers are handled via the transmitter-interrupt
service routines starting at lines #360 and #443. These
routines start by issuing an End-Of-Interrupt command
to the 8274. (This command resets the interual-interrupt controller logic of the 8274 for this particular vector and opens the logic for other internal interrupt requests. The routines next check the length count. If the
buffer is completely transmitted, the transmitter empty
flag, TX_EMPTY_CHx, is set and a command is
issued to the 8274 to reset its interrupt line. Assuming
that the buffer is not completely transmitted, the next
character is output to the transmitter. In either case, an
interrupt return is executed to return to the main CPU
program.
The receiver commands start at line #314. Like the
transmit. commands, it is assumed that the CPU has
initialized the receive-buffer-pointer public variable,
~POINTER-CHx. This variable points to the
first location in an. empty receive buffer. The command
routines clear the receiver ready flag, ~READY_
CHx, and then set the receiver enable bit in the 8274
WR3 register. With the receiver now enabled, any received characters are placed in the receive buffer using
interrupt-driven data transfers.

Similarly, the status-change routines (starting lines
#386 and #469) are initiated by a change in the modem-control status lines CTS/, CD/, or SYNDET/.
(Note that WRZ bit 0 controls whether the 8274 generates interrupts based upon changes in these lines. Our
WRZ parameter is. such that the 8274 is programmed to
ignore changes for these inputs.) The service routines
simply read RRO, place its contents in the STATUS_
MSG_CHx variable and then issue a reset external
status command. Read Register 0 contains the state of
the modem inputs at the point of the last change.
Well, that's. it. This application example has presented
useful, albeit very simple, routines showing how the
8274 might be used to transmit and receive buffers using an asynchronous serial format. Extensions for byteor bit-synchronous formats would require no hardware
changes due to the highly programmable nature of the
8274's serial formats. '

2-376

AP-134

8274 APPLICATION BRIEF PROGRAM
ISIS-II IICS-1l6 I1fICRO A55E1flLER V2.1 A55E1flLV
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210311-25

2-378

inter
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AP-134

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210311-26

2-379

inter

AP-134

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210311-27

2-380

intJ

AP-134

HCS-13O IlACIIO A5SEP'IILER

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,>

IHITJAlIZATJOO COI1I'ff{, f[ll lIE 8:;4 - lIE 3274
15 SEll.!' fI(((I>(>IHG 10 lHE PHI't1tIEIERS STOPEl' IN
00011' 5TI'IITIIIl AI CHSTPS fOl( (Hff,lU " Mllf·
(HlTF'A fl1'1CIHf£L H

f1«(f\

.***.....*.. *u••• *.......u ..+** .... *.............tA< ....u.t •• *......... ~u .... t

292

8518

29)

0518(7_
e51E sceE02\l2
13522 C706e4823596
e528 eceEe6e2
Il52CC7EI608B249il6
0532 8C~tIfl02
eJ;6 C7il6OCe27706
9S3C eceEeAe2
11549 C70610028CE16
9546~

e54R C70614B2B9il6
e55e

~6e2

e5S4C7061002CDe6
IlS5A BCeE1Ae2
e5SE C7061C82FBE16
0564 ~EB2

056811F1lOO5

2\l4
2e5
206
297
298
2\l9
219
211
212
213
214
215
216
217
218

219
22\l
221
222
223
224

IHITJIL8274.
,CIFI INTERI51R8
01(, CO'tlfHU'ORUHB
SETlJP
Dr. OFFSET Cl(>5TRA
01(, CfIII!H>_Pl*LCHA
SEll!'

,IIHTlAlIZE Clii
,COPV (Iii PI1RAllETERS
, INITIAlIZE CfIIl
; COf"/ CHA

_IE~S

239

231
232
957ftBSeeee
05/D A22\lB2
1!589 A237B2
11583 A22OO2
Il586 A236e2
Il589 A326e2

Il58C A33292
Il58FII88i
0591 A22ge2
0594 A235B2
0597A22882
959A A234B2
0591> FB
959£ CJ
859F 8fI95

85A1 JC98
85A3 7484

233
234
235
236
237
238

249
241
242
243
244
245
246
247
248
249
2SB

,(NITlILI2£ STATUS BYTES

Al(;

FLAGS

IlJ\I

AX. 9

HOY

m~CjUIS6..CIfi,

IlJ\I

HOY
HOY
IlJ\I
IlJ\I
IlJ\I
IlJ\I
I'IOV

IlJ\I
IlJ\I

IL
ERRl*JI5I.LCfIIl, Al
5TATUS_II5G_C\iB, IL
5TA1IJS_1I5G_C1R IL
RlLCMLC\iB, AX
IVCmtfLCNA, 11:':
IL, 1
R'.uE~'_(1fI, IL
RlLREfllUIfl, Al
TlUIIPT'UHB, Al
TX_EIf'TUifl, Al

511
RET
5E1lJ> : HOY
CIf'
JE

IL, [D!]
IL, 9

,ClEft? ERRl* fLffi CHB
· ClEft? ERROR FUll CHA
,ClEifl STATUS FUll [HB
,C~ STATUS Flfl] CHA
,CLEft? R:~ COJNTEI' CHB
,ClEifl RX C(wIER el'l<
,SEI ~x
,SET 11:~
; SET
· SEI I:;
· EHlKE
,RE11.fII

eM Flfl] OiB

r, 001£ fLAG
FLAG Clii
ROO CIIA
[.oNE

Clf!

DOI£

INTERRUPTS
- DOI£ WITH SEll"

,PARfff:TE~ (OP'I!I~ j1f.jJj lIE

eM
210311-28

2-381

inter

AP-134

LOC OBi

UIE

85A5
95A6
8SA7
8SA9

251

EE
47
EBf6
G

2S2
25)
254
OM
255
256 +1 $EJECT
2S7
2S8

e5AA

Il5AA sa
05f11 57
85AC 52
~ C6%.o"802lJe

00Il2_

05B5 B83E2ee2
esB9 ffiIlS
0SIl8 EE

esse

SA
lI".!IO SF
esBE 58
0SIIf C3

SOURCE
OOT
IN:
JIf'
RET

[JX, IlL
DI

. OUTPUT P~RAI1ETEF'
. POINT AT IEXT PflRfIf1HH

SEll!'

.00 LOA[' IT
.OM - 50 RET'-f.N

; *•••*******.*****••***.:t**** •• ****:U.**.*.H***** ••*****.t< •••• *f:.

259
268

;.
;'

262
26,
264

.•
,•
;'
;'

265

IX CIfIIf£L B C!JtIfK. RlJJTlt£ - RlJJTlNE 15 CIlLlE(J TO
lliINSItlT A BlfFER TI£ BlfFER STflRTlNG f«JRE5S,
T'_POINTEILClIl.. AN: H£ BIJFFER LEtfJTH.. TUEtfJTH_CHB.
HIiST BE INITIII.IZED BY Tt£ CII.LlNG PROGPAM
BOm ITEMS PPE WORt. VflRlIlUS

*******... ** .... *••••**"'•••• ****"'****u*.u."'*************. ***••• *

266

TXJXt"f{l_C;e :
PIJSH
A,:
PlISH
DI

267
268

27e
271

PlISH
i'IJ\I
Ifly

272
273
274

OOy

OOY

275
276

OOT

27ll
279

POP
FOP
POP

2Be

RET

; S~ REGISTERS

Tx..EHPTY-CHB. e . CLEfIR EMPW FLfI')
,SEn.!' Pll'T POINTER
01. TUOINTEHHB
• GET ];, BIiFFEf' POINTER CIiB
fl.., lOll
; GET FIRST CHARACTER TO T:,:
OX. II.
; OOTM IT TO e274 TO GET IT STARTE[;
DX
DI
At.
; RETlfN

DX. t>flTA_PQRLCHE<

281
2B2

2B3
2B4
2e5
298

;•
.•
;'

289

2B6

2B7
2ge

9SOl
9SOl sa
escl 57
e-.JC252
esc) C686)40280

escaBA8080
9SOl B83E2C02
IISCF ffiIlS

951>1 EE
951>2 SA
951» SF
e5I)4 58
BSI)S C3

;'
;'

291
292

IX CIflIfEl A ClH1fW ROI!TIt£ - ROI!TINE IS CALlE[· TO
Tm6ItIT A BlIFFER TIE BIJFFER STARTING AC>I)RESS.
TllPOINTER_CI'II. IIID THE BlfFER LENGTH.. TX_LENGTHJtf\,
tiiST BE IHITIII.IZED B'I THE CII.LlNG PRfFj;ffi

BOm ITEMS PPE WIlID 'lARIABlES

;*"•••*U****************"'*************••:t *.**..*••• *** •••••••.+:.
TIi..CIlItfN>_CtfI:
PlISH
PlISH
PlISH
HOY
i'IJ\I

294
295
296

297

110\1

299
300
301
)02

i'IJ\I

300
304
lllS
3e6
307

300
369

31e

OIJT
PlY
POP
PlY
RET

It,

; SAllE REGISTERS

.01
&;<:

f"-.EIf'TY-Ctf\. e. QEAR EMPT'I FLAG
DX, DATILPORUHA
. SETIJP PCPT POINTER
DJ.. TXYOINTEUHA
;!lET TX BlfFER POINTER CHA
11., IDIl
,GET FIRST c_rEP TO TX
DIi.. II.
; OIJTPIJT IT TO 82,4 TO GET 'IT STAPTED
OX

DI
fIX
;RETI~

; •••***"' ..........***....**........**** •• *.......:u ••*•••• **...*•••*.*
;

;'
;'
;'

RX CIH1fN> Fll' ClfH£L B - mE Cll.LlN13 f'IlIJTlNE tlJST
INITlfl.IZE RX_POINTER_ClIi TO POINT AT THE RECmt
BlFFER BEFll'E Cfl.LlN13 THIS ROliTlIE

2-382

210311-29

infef
MCS-86 I'KRD f6SEI'IILER
L~:

00.1

AP-134

H5I'HCB

LINE
)11
U.*U*UU"''''H.u.+~ •• UH.'''U..+''U' ""' •• U+ U~""'tUt , ••• +t +...

}12

.:-,,;
B5[)I5 58
05D7 52
0508 C6%""902OO
B.."i(\ C7l'626e2_
Il"--<:: 600600

1l'5E6 B003
Il'5EB EE

esE9 SOC!
Il'5EB EE
esEC SA
e5ED 58
e5EE CJ

B5EF
esEF 58
S5FS 52
85F1 C6e635B200
85F6 C786:l2B28000
85FC 13flI!200
85FF B003
8681 EE
B682 SOCI
B604 EE
B6e5 51!
B6B6 58

8687 C3

]13

314
;15
316

317
;18
319

l2B
321
322
323

RK_Ci1t!'Ilf{'_CHB
FUSH
Ai:
.5HY£ IOHiSTEP5
0\'
PUSH
IflY
PX_REfH _[Ii!. " . CLEAR p:.; RER['Y FLAG
110'1
F'1._CCUlLCHB. ~ : (.lEMP r'X COUNTEP
HOY
0:\.' COftlff{U'ORT ~CH8
,POlin fiT ('JI'lfiAN(' F.)F'l
I10Y
IlL,
. SET UP FOR hE
[lX. fL
OUT
HOV
f'L OC1H
,WR) - 8 Bn~'[HR. EIlABLE P:-:

124
325
326
327

OOT

DX. AL

POP
POP

RET

'"'*••*U.........-"'U •• **.** •••••• ***U* •••••;f..*•••*...... ~UU:.. H.U •• ~

3213

1..'9
33\1
nl
332
333
:;34
135
336
337
J38
3J9

"
"
RX COIt/ft{> FOR C1m£L A - THE CALLII¥.l PCOJTIHE IFJ5T
;'
INITIALIZE RX_POIHTER_CHH TO POIHT AT TtIE PEEI'!E
"
BUfFER BEFCl1£ CfLLlI'" THIS H"JTlllE
; ..
; .................
**uu .. ·u't .. "' • .t:**uu ...... t;t ...... "'. . +

...,.*...............

R'i\..COlltAlfUl'II
PUSH

PUSH
IfJY
IflY

340
341
342
34l
344
345

IfJY
IiO'I

OUT
HOV

ooT

346
POP
347
POP
348
RET
349
359 +1 IEJECT

~,:
.SHII: REGISTEPS
DX
R:\_READUHA. e. CLEAR R, REAC'Y FLAG
RX_CIWLClfI, e ,CLEAR RX C~.mER
ox. C(l1I'ifW_POIH _CHA . POIiIT AT ':CIttIRN1, PC.PT
fL, 3
. SET ~ FOR WR:
DX, FL
fL, OC1H
,WR) - B BITS,lh!!, EHABLE Ri'

ox,

OX
, RETl~N

351
352

354

B6B8 52
8689 57

_59

B6BBE6Il2S1
00lE FFl'62002
8612 FFBE22B2
8616 741!E
8618_
861B BB3E2002
961F IlAB5
9621 EE

355

356

357
359
359
368
361
362

363
36-1

START OF IHTERRll'T SERVICE ROUTINES

*******....***.**...........** .............***•••.t *""",.*•• .t. ,.***

,CIfH£L B TRAH5IIIT DATA SERVICE R('JTINE

!IJ1TIHB: PUSH
PUSH
PUSH
CALL
II«:

365
366
367

IiO'I

368
369
l7a

IiO'I
OUT

DEC

JE
IflY

;SAVE REGISTERS
DI
AX
EOI
.SEh{, E01 COItlfI'ID TO 82,4
TX_PQINTEILClI! .' POINT TO HEXT ffil.~
;REII' CHRJ!IICTEP
lOlL fl
; 5TIft: IN 8UFFEP
RX..POINTER_CItl • BI.JIP THE Bl.fF£P POl/ITEP
RlLCOMLCIfl
•BI.JIP TI£ ctUITEi'
· TEST IF LftST CHAPftCTe;> TO ~ PfctlWo
IL CR"tllR
RIB
RUErov_CIIl. 1 •·IES. SET I1EAOV FLAG
ox. COtIfH)_ro!LCIIl •POINT AT (tm/{l POI"l
El, ]
,POINT AT 1*'3
OX. fl
AL.(lCBN
.DISABLE RX
ox. fl
III(
·EITHEF ~. RESTIft: I1EGI,TEPS

0:<
.I1ETl0l TO fl.fE<:i1t1I.IID

•(IfIIf£L & ERROR SERYlCE RruTINE
ERRIII! PUSH
PUSH
CALl.
lIlY

.51't.{ i'£uISTERS

· SEtij· EO! C(lloflfflt· TO 82:4

OX. Cot9ffil_POPUI£

2-384

210311-31

infef
~S-86 IKl«)

Ap·134

RSSOIlLER

lOC OSJ
867F
11681
9682
9683
11686
11688
Il689

BOO1
EE
EC
R22Se2
11838
EE
58

ASOCB
lll£

5ru TO 8274
OX, fl
AX
; RESTORE REGISTERS
OX
; REMN TO FOREGRruID

; ClRfll A TRfIlSIIIT DATA SERVICE Rc.JllHE
X1fTIHR: PUSH
PUSH
PUSIi
CAlL

INC
[lEC
.IE
IfJV
110\'
HOY

XIA.

OUT
POP
POP
POP
IRET
110'1
110\'
ooT
HO'I
POP
POP
POP
IRE!

OX
01

; SAVE REGISTERS

EOI
; SEND EOI COIftIfI) TO 8274
TXJ'OIHTER..CHR ,POINT TO NEXT clm1Cm
TIUOOTILCHR ; [lEC lEN:;TH cOI.IIm
XIA
• TEST IF 001£
DX, DATAJ'ORLC~A
'HOT 001£ - GET NEXT CHRRACm
OJ, TXJ'OINTER_CHR
AL [OIJ
; PUT CHffiIICTER IN fL
OX. fl
; OIJTPUT IT TO 8274
AX
•RESTORE PEGISTERS
OJ
OX
.' RET~N TO FOREGROOl{>
OX, CIlI1M/{d,JRLCHA
; fll CHf'MlCTERS HAVE BEEN SEll)
fl . 28H
;RESET TRPIISHITTER IHTEfiRl.~T F'EHDlIjI)
DX. fl
TU~TUHR. 1 ; DONE - 50 SET T:~ EtIP!'1 Flf(; CW
AX
; RESTORE REGISTERS
[>1
DX
i REiUF!l TO FOREGRll.ll{·

467

,CHRN£l A STAll.lS CHAt¥3E SERVICE RlJ.lTIIlE

468
469
47(1
471
472

STRIHR PUSH
PUSH
PUSH
Cfll

4/3

IfN

474

475
4i'6

IIJY
HOY

477

OUT
POP
POl'
POP
IRET

4i8
479
400
4B1
482
4B?
484
4B5
486
4S7
4['9:

[IX

,SIM REGISTERS

('i

AX
EOI
,500 EOt (t)tttfU-K) TO 8274
DX. ClWlAli>-!'OI1Uffi
fl . D,
· READ RRO
STATPS_M9HHR, fIL
. P\JT RR8 III STAll.'S M£55f1JE
fL, 100
' SEtll REET STAWS INT COftlftNV TO 8274
OX. fl
Ft:~
· RESTORE REGISTERS
DI
DX

CHANNEL A RECElVE[j DATA

RCVIHfI. PUSH
PUSH
PUSH
CAll

SE~'II(E

ROUTH«
· SAVE R£(iISTERS

[i[
A:~

EOI

SEHI:' EOI COlflAtlC' Tn ~2~4
. GET p,: CHA WH£>' POINTER

489

MOl

P:;_P>JI'H,UH~

490

NOV

0>:,

DATA_PQ~T JHA

210311-32

2-385

IflteI-

AP-134

1[5-86 HA<:RO ASSEI1IIlER

ASI'NCB

LOC (W

LINE

060A EC
Il600 8ge5
l!6OO FFIl63892
Il6El FFIl63282
1l6E5 lCBO
Il6E7 7SSE
1l6E9 C6El63SB201

1l6EEllf\B2T
fl., 3
,POINT AT WP)
DXdl
fl., OCBH
. DISABLE ~~

OUT

ox, fI.

4~1

492
493
494
495
496
497
498
499

HOI'

11£
INC
C11P

JIE
HOI'
I10Y
HOI'

SB4

RIA

POP
POP

AX
DI

SIl5

POP

[OX

SIl6

IPET

. EITHER IfiY. REST(l>E REGISTERS
. RETl.I':N TO FOO:GROlI(>

597

sea
Il6FS 52

86f( 59
96FD E8!00B

B79B llf\B2-OF-INTERRlJPT ROUTINE - SEI-I>S EOI Cat1llf(; TO 8274.
THIS COiWN) IIlST flWI/S TO ISSUED ON CIiIIf£L A
EO!:

PUSH

S28

PUSH

529

HOY

DX
DX, COIMI>_PORLCHA

539

HOI'

531
532
533
534

M
POP
POP

• SfIIiE REGISTERS
,lillAYS FOR CHANNEL A '"

Ii, :leH
DX. fI.
OX

RET

535
536
5J7

;00 OF CODE ROUTINE

539

ENll

OOS

210311-33

ASSErtllY C(lf'LETE, NO ERRORS FOCI{)

REFERENCES
1. 8274 Multiprotocol Serial Controller (MPSC) Data
Sheet, Intel Corporation, California, 1980.

2. Basics of Data Communication, Electronics Book
Series, McGraw-Hill, New York, 1976.

3. Telecommunications and the Computer, J. Martin,
Prentice-Hall, New Jersey, 1976.
4. Technical Aspects of Data Communications, J. McNamara, DEC Press, Massachusetts, 1977.
5. Miscellaneous Data Communications StandardsEIA RS-232-C, ElA RS-422, EIA RS-423, EIA
Standard Sales, Washington, D.C.

2-386

APPLICATION
NOTE

AP-145

November 1986

Synchronous Communication with
the 8274 Multiple Protocol
Serial Controller

SIKANDAR NAQVI
APPLICATION ENGINEER

Order Number: 210403-001
2-387

SYNCHRONOUS
COMMUNICATION WITH
THE 8274 MULTIPLE
PROTOCOL SERIAL
CONTROLLER

CONTENTS

PAGE

INTRODUCTION ....................... 2-389

SYNCHRONOUS PROTOCOL
OVERVIEW ......................... 2-389
BLOCK DIAGRAM ..................... 2-391
MPSC INTERRUPT STRUCTURE . ..... 2-394
MPSC MODES OF OPERATION ....... 2-398
APPLICATION EXAMPLE ............. 2-403
SPECIAL APPLICATIONS ............. 2-408
PROGRAMMING HINTS ............... 2-410
APPENDIX A: APPLICATION EXAMPLE
SOFTWARE LISTINGS .............. 2-411
APPENDIX B: MPSC READ/WRITE
REGISTER DESCRIPTIONS . ........ 2-422
REFERENCES ......................... 2-425

2-388

inter

AP-145

INTRODUCTION
The INTEL 8274 is a Multi-Protocol Serial Controller,
capable of handling both asynchronous and synchronous communication protocols. Its programmable features allow it to be configured in various operating
modes, providing opimization to given data communication application.
This application note describes the features of the
MPSC in Synchronous Communication applications
only. It is strongly recommended that the reader read
the 8274 Data Sheet and Application Note AP134
"Asynchronous Communication with the 8274 MultiProtocol Serial Controller" before reading this Application Note. This Application note assumes that the reader is familiar with the basic structure of the MPSC, in
terms of pin description, Read/Write registers and
asynchronous communication with the 8274. Appendix
A contains the software listings of the Application Example and Appendix B shows the MPSC Read/Write
Register~ for quick reference.
The first section of this application note presents an
overview of the various synchronous protocols. The
second section discusses the block diagram description
of the MPSC. This is followed by the description of
MPSC interrupt structure and mode of operation in the
third and fourth sections. The fifth section describes a
hardware/software example, using the INTEL single
board computer iSBC88/45 as the hardware vehicle.
The sixth section consists of some specialized applications of the MPSC. Finally, in section seven, some useful programming hints are summarized.
'

SYNCHRONOUS PROTOCOL
OVERVIEW
This section presents an overview of various synchronous protocols. The contents of this section are fairly
tutorial and may be skipped by the more knowledgeable
reader.

Bit Oriented Protocols Overview
Bit oriented protocols have been defined to manage the
flow of information on data communication links. One
of the most widely known protocols is the one defined
by the International Standards Organization: HDLC
Opening
Flag
Byte

Address'
Field (A)

(High Level Data Link Control). The American Standards Association's protocol, ADCCP is similar to
HDLC. CCITT Recommendation X.25 layer 2 is also
an acceptable version of HDLC. Finally, IBM's SDLC
(Synchronous Data Link Control) is also a subset of the
HDLC.
In this section, we will concentrate most of our discussion on HDLC. Figure I shows a basic HDLC frame
format.
A frame consists of five basic fields: Flag, Address,
Control, Data and Error Detection. A frame is bounded by flags-opening and closing flags. An address field
is 8 bits wide, extendable to 2 or more bytes. The control field is also 8 bits wide, extendable to two bytes.
The data field or information field may be any number
of bits. The data field mayor may not be on an 8-bit
boundary. A powerful error detection code called
Frame Check Sequence contains the calculated CRC
(Cycle Redundancy Code) for all the bits between the
flags.
ZERO BIT INSERTION

The flag has a unique binary bit pattern: 7E HEX. To
eliminate the possibility of the data field containing a
7E HEX pattern, a bit stuffing technique called Zero
Bit Insertion is used. This technique specifies that during transmission, a binary 0 be inserted by the transmitter after any succession of five contiguous binary 1'so
This will ensure that no pattern of 0 1 1 1 1 1 lOis ever
transmitted between flags. On the receiving side, after
receiving the flag, the receiver hardware automatically
deletes any 0 following five consecutive l's. The 8274
performs zero bit insertion and deletion automatically
in the SDLC/HDLC mode. The zero-bit stuffing ensures periodic transitions in the data stream. These
transitions are necessary for a phase lock circnit, which
may be used at the receiver end to generate a receive
clock which is in phase to the received data. The inserted and deleted O's are not included in the CRe checking. The address field is used to address a given secondary station. The control field contains the link-level control information which includes implied acknowledgement, supervisory commands and responses, etc. A
more detailed discussion of higher level protocol functions is beyond the scope of this application note. Interested readers may refer to the references at the end of
this application note.

Control"
Field (C)

Data
Field

Figure 1. HDLC/SDLC Frame Format
'Extendable to 2 or More Bytes.
•• Extendable to 2 Bytes.

2-389

Frame
Check
Sequence

Closing
Flag
Byte

AP-145

The data field may be of any length and content in
HOLC. Note that SOLC specifies that data field be Ii
multiple of bytes only. In data communications, it is
generally desirable to transmit data which may be of
any content. This requires that data field should not
contain characters which are defined to assist the transmission protocol (like opening flag 7EH in HOLC/
SOLC communications). This property is referred to as
"data transparency". In HOLC/SOLC, this code
transparency is madeepossible by Zero Bit Insertion discussed earlier and the bit oriented nature of the protocol.
The last field is the FCS (Frame Check Sequence). The
FCS uses the error detecting techniques called Cyclic
Redundancy Check. In SOLC/HOLC, the CCITTCRC must be used.
NON-RETURN TO ZERO INVERTED (NRZI)

NRZI is a method of clock and data encoding that is
well suited to the HOLC protocol. It allows HOLC
protocols to be used with low cost asynchronous modems. NRZI coding is done at the transmitter to enable
clock recovery from the data at the receiver terminal by
using standard digital phase locked loop techniques.
NRZI coding specifies that the signal condition edoes
not change for transmitting a 1, while a 0 causes a
change of state. NRZI coding ensures that an active
data line will have transition at least every 5-bit times
(recall Zero Bit Insertion), while contiguous O's will
cause a change of state. Thus, ZBI and NRZI encoding
makes it possible for a phase lock circuit at the receiver
end to derive a receive clock (from received data) which
is synchronized to the received data and at the same
time ensure data transparency.

Byte Synchronous Communication
As the name implies, Byte Synchronous Communication iSe a synchronous communication protocol which
means that the transmitting station is synchronized to
the receiving station through the recognition of a special sync character or characters. Two examples of Byte
Synchronous protocol are the IBM Bisync and MonoSYNC

SYNC

SOH

HEADER

sync. Bisync has two starting sync characters per message while monosync has only one sync character. For
the sake of brevity, we will only discuss Bisync here.
All the discussion is valid for Monosync also. Any eX-e
ceptions will be noted. Figure 2 shows a typical Bisync
message format.
The Bisync protocol is defined for half duplex communication between two or more stations over point to
point or multipoint communication lines. Special characters control link access, transmission of data and termination of transmission operations for the system. A
detailed discussion of these special control characters
(SYN, ENQ, STX, ITB, ETB, ETX, OLE, SOH,
ACKO, ACKI, WACK, NAK and EOT, etc) is beyond
the scope of this Application Note. Readers interested
in more detailed discussion are directed to the references listed at the end of this Application Note.
As shown in Figure 2, each message is preceded by two
sync characters. Since the sync characters are defmed
at the beginning of the message only, the transmitter
must insert fill characters (sync) in order to maintain
synchronization with the receiver when no data is being
transmitted.
TRANSPARENT TRANSMISSION

Bisync protocol requires special control characters to
maintain the communication link over the line. If the
data is EBCOIC encoded, then transparency is ensured
by the fact that the field will not contain any of the
bisync control characters. However, if data does not
conform to standard character encoding techniques,
transparency in bisync is achieved by inserting a special
character OLE (Oata Link Escape) before and after a
string of characters which are to be transmitted transparently. This ensures that any data characters which
match any of the special characters are not confused for e
special characters. An example of a transparent block is
shown in Figure 3.
In a transparent mode, it is required that the CRC
(BCC) is not performed on special characters. Later on,
we will show how the 8274 can be used to achieve
transparent transmission in Bisync mode.
STXTEXT

ETXOR ETB

CRC1

CRC2

ETX

BCC

Fig!lre 2. Bisync Message Format

DLE

STX

Enter transparent mode

TRANSPARENT TRANSMISSION

DLE

return to normal mode

Figure 3. Bisync Transparent Format

2-390

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AP-145

BLOCK DIAGRAM
This section discusses the block diagram view of the
8274. The CPU interface and serial interface is discussed separately. This will be followed by a hardware
example in the fifth section, which will show how to
interface the 8274 with the Intel CPU 8088. The 8274
block diagram is shown in Figure 4.

CPU Interface
The CPU interface to the system interface logic block
utilizes the AD, AI, CS, RD and WR inputs to communicate with the internal registers of the 8274. Figure 5
shows the address of the internal registers. The DMA
interface is achieved by utilizing DMA request lines for

each channel: TxDRQA, TxDRQB, RxDRQA,
. RxDRQB~ote that TxDRQB and RxDRQ~ecome
IPO and IPI respectively in non-DMA mode. IPI is the
Interrupt Priority Input and IPO is the Interrupt Priority Output. These two pins can be used for connecting
multiple MPSCs in a daisy chain. If the Wait Mode is
programmed, then TxRDQA and RxDRQA pins become RDYB and RDYA pins. These pins can be wireOR'ed and are usually hooked up to the CPU RDY
line to synchronize the CPU for block transfers. The
INT pin is activated whenever the MPSC requires CPU
attention. The INTA may be used to utilize the powerful vectored mode feature of the 8274. Detailed discussion on these subjects will be done later in this Application Note. The RESET pin may be used for hardware
reset while the clock is required to click the internal
logic on the MPSC.

TxDA

CHANNEL A
TRANSMITIER

DeO-7

TxCA

CHANNEL A
WRITE
REGISTERS
DCDA

CLK
RESET
RDYelTxDRaA

CTSA

CHANNEL A
CONTROL
LOGIC

RTSA
SYNDETA

ROY AIRxDRaA
Ul

IPOITxDRae
IP11RxDRae
INT

DTRA

iilJ/l--L---I CHANNEL A
READ
REGISTERS

SYSTEM
INTERFACE
CONTROL
LOGIC

S
c
a:
~1C~=======1

RxDA

CHANNEL A
RECEIVER

RxCA

INTA
AO
A1

AD
WR

TxDB
TxCB

•f

DCDe
CHANNEL B

CTSB
{

SYSTEM INTERFACE

5YNDETB
RT5B

DTlfe
RxCB
RxDB
NETWORK INTERFACE
210403-1

Figure 4. 8274 Block Diagram

2-391

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AP-145

0
0

0
1

0
0

CHA
CHA

Read Operation
DATA READ
STATUS REGISTER
(RRO,RR1)

CHA DATA WRITE
CHA COMMAND/PARAMETER
.(WRO-WR7)

Write Operation

0
0

0
1

1
1

CHB
CHB

DATA READ
STATUS REGISTER
(RRO,RR1,RR2)

CHB DATA WRITE
CHB COMMAND/PARAMETER
(WRO-WR7)

HIGHZ

Figure 5. Bus Interface

Serial Interface

Transmit and Receive Data Path

On the serial side, there are two completely independent channels: Channel A and Channel B. Each chan·
nel consists of a transmitter block, receiver block and a
set of read/write registers which are used to initialize
the device. In addition, a control logic block provides
the modem interface pins. Channel B serial interface
logic is a mirror image of Channel A serial interface
logic, except for one exception: there is only one pin for
RTSB and SYNDETB.

Figure 6 shows a block diagram for transmit and receive data path. Without describing each block on the
diagram, 'a brief discussion of the block diagram will be
presented here.

A a given time, this pin is either RTSBor SYNDETB.
This mode is programmable through one of the internal
registers on the MPSC.

TRANSMIT DATA PATH

The transmit data is transferred to the twenty-bit serial
shift register. The twenty bits are needed to store two
bytes of sync characters in bisync mode. The last three
bits of the shift register are used to indicate to the internal control logic that the current data byte has been
shifted out of the shift register. The transmit data in the

CPU 10

TxDA

TxCA

210403-2

Figure 6. Transmit and Receive Data Path

2-392

inter

AP-145

transmit shift register is shifted out through a two bit
delay onto the TxData line. This two bit delay is used
to synchronize the internal shift clock with the external
transmit clock. The data in the shift register is also
presented to zero bit insertion logic which inserts a zero
after sensing five contiguous ones in the data stream. In
parallel to all this activity, the CRC-generator is computing CRC on the transmitted data and appends the
frame with CRC bytes at the end of the data transmission.

RECEIVE DATA j)ATH

The received data is passed through a one bit delay
before it is presented for flag/sync comparison. In bisync mode, after the synchronization is achieved, the
incoming data bypasses the sync register and enters directly into the three bit buffer on its way to receive shift
register. In SDLC mode, the incoming data always
passes through the sync register where the data pattern
is continuously monitored for contiguous ones for the

FIRST DATA CHARACTER

FIRST NON· SYNC
CHARACTER (SYNC MODES)

INTERRUPT
ON FIRST RECEIVE
CHARACTER

VALID ADDRESS
BYTE (SDLC)
INTERRUPT ON
ALL RECEIVE
CHARACTERS
PARITY ERROR

RX OVER-RUN ERROR

FRAMING ERROR

SPECIAL
RECEIVE
CONDITION
INTERRUPT

END OF FRAME
(SDLCONLY)

DCD TRANSITION

MPSC
INTERRUPTS

CTS TRANSITION
EXTERNAL
STATUS
INTERRUPT
SYNC TRANSITION

TX UNDER-RUN/EOM

BREAK/ABORT DETECT

TRANSMIT
INTERRUPT

TX BUFFER EMPTY

210403-3

Figure 7_ MPSC Interrupt Structure

2-393

Intel

AP-145

zero deletion logic. The data then enters the three bit
buffer and the receive shift register, From the receive
shift register, the data is transferred to the three· byte
deep FIFO. The data is transferred to the top of the
FIFO at the chip clock rate (not the receiver clock). It
takes three chip clock/periods to transfer data from the
serial shift register to the top of the FIFO. The three bit
deep Receive Error FIFO shifts any error condition
which may have .occurred during a frame reception.
While all this is happening, the CRC checker is checking the CRC on the incoming data. The computed
CRC is checked with the CRC bytes attached to the
incoming frame and an error generated under a nocheck condition. Note that the bisync data is presented
to the CRC checker with an 8-bit delay. This is necessary to achieve transparency in bisync mode as will be
. shown later in this Application Note.

RECEIVE INTERRUPT ON RECEIVE
CHARACTER

A receive interrupt is generated when a character is
received by the MPSC. However, as will be discussed
later, this is a programmable feature on the MPSC. A
Rx character available interrupt is generated by the
MPSC after the receive character has been assembled
by the MPSC. It may be noted that in DMA transfer
mode too, a receive interrupt on the first receive character should be programmed. In SDLC mode, if address search mode has been programmed, this interrupt
will be generated only after a valid address match has
occurred. In bisync mode, this interrupt is generated on
receipt of a character after at least two valid sync characters. In monosync mode, a character followed after at
least a single valid sync character will generate this interrupt. An interrupt on first receive character signifies
the beginning of a valid frame. An· end of the frame is
characterized by an "End of Frame" Interrupt (RR1:
D7).* This bit (RR1:D7) is set in SDLC/HDLC mode
only and signifies that a valid ending flag (7EH) has
been received. This bit gets reset either by an "Error
Reset" command (WRO: D5D4D3 = 110) or upon reception of the first character of the next frame. In multiframe reception, on receiving the interrupt at the
"End of Frame" the CPU may issue an Error Reset
command which will reset the interrupt. In DMA
mode, the interrupt on first receive character is accompanied by a RxDRQ (Receiver DMA request) on the
appropriate channel. At the end of the frame, an End of
Frame interrupt is generated. The CPU may use this
interrupt to jump into a routine which may redefine the
receive buffer for the next incoming frame.

MULTI-PROTOCOL SERIAL

CONTROLLER (MPSC) INTERRUPT
STRUCTURE
The MPSC offers a very powerful interrupt structure,
which helps in responding to an interrupt condition
very quickly. There are multiple sources of interrupts
within the. MPSC. However, the MPSC resolves the
priority between various interrupting sources and interrupts the CPU for service through the interrupt line.
This section presents a comprehensive discussion of all
the 8247 interrupts and the priority resolution between
these interrupts.
All .the sources of interrupts on the 8274 can be
grouped il).to three distinct categories. (See Figure 7.)

'NOTE:
RR1:D7 is bit D7 in Read Register 1.

1. Receive Interrupts
2. Transmit Interrupts
3. External/Status Interrupts.

SPECIAL RECEIVE CONDITION INTERRUPTS

An internal interrupt priority structure sets the priority
between the interrupts. There are two programmable
options available on the MPSC. The priority is set by
WR2A, D2 (Figure 8).

So far, we have assumed that the reception is error free.
But this is not 'typical' in most real life applications.
Any error condition during a frame reception generates
yet another interrupt-special receive condition interrupt. There are four different error conditions. which
can generate this interrupt.
(i) Parity error
(ii) Receive Overrun error
(iii) Framing error
(iv) End of Frame

PRIORITY

WR2A:D2

Highest

RxA
RxA

Lowest

TxA RxB TxB EXTA EXTB
RxB TxA TxB EXTA EXTB

Figure 8. Interrupt Priority

Receive Interrupt
All receive interrupts may be categorized into two distinct groups: Receive Interrupt on Receive Character
and Special Receive Condition Interrupts.

(i) Parity error: Parity error is encountered in asynchronous (start-stop bits) and in bisync/monosync protocols. Both odd or even parity can be programmed. A
parity error in a received byte will generate a special
receive condition interrupt and sets bit 4 in RR1.

2-394

AP-145

(ii) Receive Overrun error: If the CPU or the DMA
controller (in DMA mode) fails to read a received character within three byte times after the received character interrupt (or DMA request) was generated, the receiver buffer will overflow and this will generate. a special receive condition interrupt and sets bit 5 in RR1.

The External Status Interrupt can be caused by five
different conditions:
(i) CD Transition
(ii) CTS Transition
.(iii) Sync/Hunt Transition
(iv) Tx under-run/EOM condition
(v) Break/Abort Detection.

(iii) Framing error: In asynchronous mode, a framing
error will generate a special receive interrupt and set bit
D6 in RRI. This bit is not latched and is updated on
the next received character.

CO, CTS TRANSITION

(iv) End of frame: This interrupt is encountered in
SDLC/HDLC mode only. When the MPSC receives
the closing flag, it generates the special receive condition interrupt and sets bit D7 in RRI.
All the special receive condition interrupts may be reset
by issuing an Error Reset Command.
CRC Error: In SDLC/HDLC and synchronous modes,
a CRC error is indicated by bit D6 in RR1. When used
to check CRC error, this bit is normally set until a
correct CRC match is obtained which resets this bit.
After receiving a frame, the CPU must read this bit
(RRl:D6) to determine if a valid CRC check had occurred. It may be noted that a CRC error does not
generate an interrupt.
It may also be pointed out that in SDLC/HDLC mode,

receive DMA requests are disabled by a special receive
condition and can only be re-enabled by issuing an Error Reset Command.

Transmit Interrupt
A transmit buffer empty generates a transmit interrupt.
This has been discussed earlier. under "Transmit in Interrupt Mode" and it would be sufficient to note here
that a transmit buffer empty interrupt is generated only
when the transmit buffer gets empty-assuming it had
a data character loaded into it earlier. This is why on
starting a frame transmission, the first data character is
loaded by the CPU without a transmit empty interrupt
(or DMA request in DMA mode). After this character
is loaded into the serial shift register, the buffer becomes empty, and an interrupt (or DMA request) is
generated. This interrupt is reset by a "Reset Tx Interrupt/DMA Pending" command (WRO: D5 D4 D3
101).

External/Status Interrupt
Continuing our discussion on transmit interrupt, if the
transmit buffer is empty and the transmit serial shift
register also becomes empty (due to the data character
shifted out of the MPSC), a transmit under-run interrupt will be generated. This interrupt may be reset by
"Reset External!Status Interrupt" command (WRO:
D5 D4 D3 = 101).

Any transition on these inputs on the serial interface
will generate an External!Status interrupt and set the
corresponding bits in status register RRO. This interrupt will also be generated in DMA as well as in Wait
Mode. In order to find out the state of the CTS or CD
pins before the transition had occurred, RRO must be
read before issuing a Reset External!Status Command
through WRO. A read of RRO after the Reset External!
Status Command will give the condition of CTS or CD
pins after the transition had occurred. Note that bit D5
in RRO gives the complement of the state of CTS pin
while D3 in RRO reflects the actual state of the CD pin.
SYNC HUNT TRANSITION

Any transition of the SYNDET input generates an interrupt. However, sync input has different functions in
different modes and we shall discuss them individually.
SOLC Mode

In SDLC mode, the SYNDET pin is an output. Status
register RRl, D4 contains the state of the SYNDET
pin. The Enter Hunt Mode initially sets this bit in RO.
An opening flag in a received SDLC frame resets this
bit and generates an external status interrupt. Every
time the receiver is enabled or the Enter Hunt Code
Command is issued, an external status interrupt will be
generated on receiving a valid flag followed by a valid
address/data character. This interrupt may be reset by
the "Reset External/Status Interrupt" command.
External SYNC Mode

The MPSC can be programmed into External Sync
Mode by setting WR4, D5 D4 = 11. The SYNDET
pin is an input in this case and must be held high until
an external character synchronization is established.
However, the External Sync mode is enabled by the
Enter Hunt Mode control bit (WR3: D4). A high at the
SYNDET pin holds the Sync/Hunt bit (RRO,D4) in
the reset state. When external synchronization is established, SYNDET must be driven low on second rising

2-395

inter

AP-145

edge of RxC after the rising edge of RxC on which the
last bit of sync character was received. This high to low
transition sets the Sync/Hunt bit and genera~s an external/status interrupt, which. must be reset by the Reset External/Status command. If the SYNOET input
goes high again, another External Status Interrupt is
generated, which may be cleared by Reset External/
Status command.

In SOLC Receive Mode, an Abort sequence (seven or
more l's) detection on the receive data line will generate an External/Status interrupt and set RRO,07. A
Reset External/Status command will clear this interrupt. However, a termination of the Abort sequence
will generate another interrupt and set RRO,07.again.
Once again, it may be cleared by issuing Reset External/Status Command.

Mono-Sync/Bisync Mode

This concludes our discussion on External Status Interrupts.

SYNOET pin acts as an output in this case. The Enter
Hunt Mode sets the Sync/Hunt bit in RO. Sync/Hunt
bit is reset when the MPSC achieves character synchronization. This high to low transition will generate an
external status interrupt. The SYNOET pin goes active
every time a sync pattern is detected in the data stream.
Once again, the external status interrupt may be reset
by the Reset External/Status command.

Interrupt Priority Resolution .
The internal interrupt priority between various interrupt sources is resolved by an internal priority logic
circuit, according to the priority set in WR2A. We will
now discuss the interrupt timings during the priority
resolution. Figures 9 and 10 show the timing diagrams
for vectored and non~vectoredmodes.

Tx UNDER-RUN/END OF MESSAGE (EOM)

The transmitter logic includes a trausmit buffer and a
transmit serial shift register. The CPU loads the character into the transmit buffer which is trlinsferred into
the transmit shift register to be shifted' out of the
MPSC. If the transmit buffer gets empty, a transmit
buffer empty interrupt is generated (as discussed earlier). However, if the transmit buffer gets empty and the
serial shift register gets empty" a transmit under-run
condition will be created. This generates an External
Status Interrupt and the interrupt can be cleared by the
Reset External Status command. The status register
RRO, 06 bit is set when the. transmitter under-runs.
This bit plays an important role in controlling a trans-'
mit operation, as will be discussed later in this application note.
BREAK/ ABORT DETECTION

In asynchronous mode, bit 07 in RRO is set when a
break condition is detected on the receive data line.
This also generates an External/Status interrupt which
may be reset by issuing a Reset External/Status Inter. rupt comma,lld to the MPSC. Bit 07 in RRO is reset
when the break condition is terminated on.the receive
data line and this causes another External/Status interrupt to ge generated. Again, a Reset External/Status
Interrupt command will reset this interrupt and will
enable the break detection logic to look for the next
break sequence.

VECTORED MODE

We' shall assume that the MPSC accepted an internal
request for an interrupt by activating the internal INT
signal. This leads to generating an external interrupt
signal on the INT pin. The CPU responds with an interrupt acknowledge (INTA) sequence. The leading
edge of the fIrSt INTA pulse sets an internal interrupt
acknowledge signal (we will call it Internal INTA). Internal INTA is reset by the high going edge of the third
INTA pulse. The MPSC will not accept liny internal
requests for an interrupt during the period when internal INTA is active (high). The MPSC resolves the priority during various existing internal interrupt requests
during the Interrupt Request Priority Resolve Time,
which is defined as the time between the leading edge of
the first INTA and the leading edge of the second
INTA from the CPU. Once the internal priorities have
been resolved, an internal Interrupt-in-service Latch is
set. The external INT is also deactivated when the Interrupt-in-Service Latch is set.
The lower priority interrupt requests are not accepted
internally until an EO! (WRO: 05 04 03 = 111 Ch. A
only) command is issued by the CPU. The EO! command enables the lower priority interrupts. However, a
higher priority interrupt request will still be accepted
(except during the period when internal INTA is active) even though the Internal-in-Service Latch is set.

2-396

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AP-145

INTERNAL ' N 0
ACCEPTED
EXTERNAL

INT

\ ' - -_ _ _ _

---I~
\

IPI

l~______________~\__------------~~------_r

IPO
INTA

INTERNAL
INTA

I
.-:.;::",..,.._ _ _ _ _ _ _ _ _ _
ND_IN_TE_\...JN:r.L/NTERRUPTS ACCEPTED

..y

INT.IN.SERV!:E
(INTERNAL LATCH)

EOICOMMA;,:ND~

_____________________________

210403-4

Figure 9. 8274 in 8085 Vectored Mode Priority Resolution Time

INTERNAL INT
ACCEPTED
EXTERNAL INT - - - - . .

\
IPI

\
\
\

POINTER 2
SPECIFIED

~NOINTERNALINTERRUPTS-==\

--------.,-f

ACCEPTED

....- - . . . . ,

ir---+---+-----

r-m~L~
TIME

INT-IN-SERVICE_ _ _ _ _ _ _ _ _ _ _ _ _..J
(INTERNAL LATCH)

EOICOMMAND-----------------------------------------~.~----..J

210403-5

Figure 10.8274 Non Vectored Mode Priority Resolve Time

2-397

inter

AP-145

Thi~her priority request will generate another exter~
nal INT and will have to be handled by the CPUaccording to how the CPU is set up. If the CPU is set up
to respond to this interrupt, a new INTA cycle will be
repeated as discussed earlier. It may also be noted that
a transmitter buffer empty and receive character available interrupts are cleared by loading a character into
the MPSC and by reading the character received by the
MPSC respectively.

EOI Command

The EOI command as explained earlier, enables the
lower priority interrupts by resetting the internal InService-Latch, which consequently resets the IPO output to a low state. See Figures 9 and 10 for details. Note
that before issuing any EOI command, the internal interrupting source must be satisfied otherwise, same
source will interrupt again. The Internal Interrupt is
the signal which gets reset when the internal interrupting source is satisfied (see Figure 9).

NON-VECTORED MODE

This concludes our discussion on the MPSC Interrupt
Structure.
'

Figure 10 shows the timing of interrupt sequence in
non-vectored mode. The explanation of non-vectored is
similar to the vector mode, except for the following
exceptions.
- No internal priority requests are accepted during
the time when pointer 2 for Channel B is specified.
- The interrupt request priority resolution time is the
time between the leading edge of pointer 2 and leading edge of RD active. !tmay be pointed out that in
non-vectored mode, it is assumed that the status
affects vector mode is used to expedite interrupt response.

MULTI-PROTOCOL SERIAL·
CONTROLLER (MPSC) MODES OF
OPERATION

On getting an interrupt in non-vectored mode, the CPU
must read status register RR2 to find out the cause of
the interrupt. In order to do so, first a pointer to status
register RR2 is specified and then the status read from
RR2. It may be noted here that after specifying the
pointer, the CPU must read status register RR2 otherwise, no new interrupt requests will be accepted internally.
Just like the vectored mode, no lower internal priority
requests are Ilccepted until an EOI command is issued
by the CPU. A higher priority request can still interrupt the CPU (except during the priority request inhibit
time). Itis important to note here that if the CPU does
not perform a read operation after specifying the pointer 2 for Channel B, the interrupt request accepted before the pointer 2 was activated will remain valid and
no other request (high or low priority) will be accepted
internally. In order to complete a correct priority resolution, it is advised that a read operation be done after
specifying the pointer 2B.

The MPSC provides two fully indepc:ndent channels
that may be configured in various modes of operations.
Each channel can be configured into full duplex mode
and may operate in a mode or protocol different from
the other channel. This feature will be very efficient in
an application which requires two data link channels
operating in different protocols and possibly at different
data rates. This section presents a detailed discussion
on all the 8274 modes and shows how to configure it
into these modes.

Interrupt Driven Mode
In the interrupt mode, all the transmitter and receiver
operations are reported to the processor through interrupts. Interrupts are generated by the MPSC whenever
it requires service. In the following discussion, we will
discuss how.to transmit and receive in interrupt driven
mode.
TRANSMIT IN INTERRUPT MODE

The MPSC can be configured into interrupt mode by
appropriately setting the bits in WR2 A (Write Register
2, Channel A). Figure 11 shows the modes of operation.
WR2A

IPI and IPO

So far; we have ignored the IPI and IPO signals shown
in Figures 9 and 10. We may recall that IPI is the
Interrupt-Priority-Input to the MPSC. In conjunction
with the IPO (Interrupt Priority Output), it is used to
daisy chain multiple MPSCs. MPSC daisy chaining will
be discussed in detail later in this application note.

2-398

0
0

1
1

Mode
CH A and CH B in Interrupt Mode
CH A in DMA and CH B in Interrupt
Mode
CH A and CH B in DMA Mode
Illegal

Figure 11. MPSCMode Selection for
Channel A and Channel B

AP-145

We will limit our discussion to SOLC transmit and receive only. However, exceptions for other synchronous
protocols will be pointed out. To initiate a frame transmission, the first data character must be loaded from
the CPU, in all cases. (OMA Mode too, as you will
notice later in this application note). Note that in
SOLC mode, this first data character may be the address of the station addressed by the MPSC. The transmit buffer consists of a transmit buffer and a serial shift
register. When the character is transferred from the
buffer into the serial shift regiser, an interrupt due to
transmit buffer empty is generated. The CPU has one
byte time to service this interrupt and load another
character into the transmitter buffer. The MPSC will
generate an interrupt due to transmit buffer underrun
condition if the CPU does not service the Transmit
Buffer Empty Interrupt within one byte time.
This process will continue until the CPU is out of any
more data characters to be sent. At this point, the CPU
does not respond to the interrupt with a character but
simply issues a Reset Tx INT/OMApending command (WRO: 05 0403 = 101). The MPSC will ultimately underrun, which simply means that both the
transmit buffer and transmit shift registers are empty.
At this point, flag character (7EH) or CRC byte is
loaded into the transmit shift register. This sets the
transmit underrun bit in RRO and generates "Transmit
Underrun/EOM" interrupt (RRO: 06 = I).
You will recall that an SOLC frame has two CRC bytes
after the data field. 8274 generates the CRC on all the
data that is loaded from the CPU. Ouring initialization,
there is a choice of selecting a CRC-16 or CCITT-CRC
(WR5: 02). In SOLC/HOLC operation, CCITT-CRC
must be selected. We will now see how the CRC gets
inserted at the end of the data field. Here we have a
choice of having the CRC attached to the data field or
sending the frame without the CRC bytes. Ouring
transmission, a "Reset Tx Underrun/EOM Latch"
command (WRO: 07 06 = 11) will ensure that at the
end of the frame when the transmitter underruns, CRC
bytes will be automatically inserted at the end of the
data field. If the "Reset Tx Underrun/EOM Latch"
command was not issued during the transmission of
data characters, no CRC would be inserted and the
MPSC will transmit flags (7EH) instead.
However, in case of CRC transmission, the CRC transrnission sets the Tx Underrun/EOM bit and generates a
Transmitter Underrun/EOM Interrupt as discussed
earlier. This will have to be reset in the next frame to
ensure CRC insertion in the next frame. It is recommended that Tx Underrun/EOM latch be reset very
early in the transmission mode, preferably after loading
the first character. It may be noted here that Tx Underrun EOM latch cannot be reset if there is no data in the
transmit buffer. This means that at least one character
has to be loaded into the MPSC before a "Reset Transmit Underrun/EOM Latch" command will be accepted
by the MPSC.

When the transmitter is underrun, an interrupt is generated. This interrupt is generated at the beginning of
the CRC transmission, thus giving the user enough
time (minimum 22 transmit clock cycles) to issue an
Abort command (WRO: 05 0403 = 00 1) in case if
the transmitted data had an error. The Abort Command will ensure that the MPSC transmits at least
eight I's but less than fourteen I's before the line reverts to continuous flags. The receiver will scratch this
frame because of bad CRC.
However, assuming the transmission was good (no
Abort Command issued), after the CRC bytes have
been transmitted, closing flag (7EH) is loaded into the
transmit buffer. When the flag (7EH) byte is transferred to the serial shift register, a transmit buffer empty interrupt is generated. If another frame has to be
transmitted, a new data character has to be loaded into
the transmit buffer and the complete transmit sequence
repeated. If no more frames are to be transmitted, a
"Reset Transmit INT/OMA Pending" command
(WRO: 05 04 03 = 101) will reset the transmit buffer
empty interrupt.
For character oriented protocols (Bisync, Monosync),
the same discussion is· valid, except that during transmit underrun condition and transmit underrun/EOM
bit in set state, instead of flags, filler sync characters are
transmitted.
CRC Generation

The transmit CRC enable bit (WR5: 00) must be set
before loading any data into the MPSC. The CRC generator must be reset to all 1's at the beginning of each
frame before CRC computation has begun. The CRC
computation starts on the first data character loaded
from the CPU and continues until the last data character. The CRC generated is inverted before it is sent on
the Tx Oata line.
Transmit Termination

A successful 'transmission can be terminated by issuing
a "Reset Transmit Interrupt/OMA Pending" command, as discussed earlier. However, the transmitter
may be disabled any time during the transmission and
the results will be as shown in Figure 12.
RECEIVE IN INTERRUPT MODE

The receiver has to be initialized into the appropriate
receive mode (see sample program later in this application note). The receiver must be programmed into Hunt
Mode (WR3: 04) before it is enabled (WR3: 00). The
receiver will remain in the Hunt Mode until a flag (or
sync character) is received. While in the SOLC/Bisync/Monosync mode, the receiver does not enter the
Hunt Mode unless the Hunt bit (WR3, 04) is set again
or the receiver is enabled again.

2-399

AP-145

SDLC Address byte is stored in WR6. A global address
(FFH) has been hardwired on the MPSC. In address
search mode (WR3: D2 = 1), any frame with address
matching with the address in WR6 will be received by
the MPSC. Frames with global address (FFH) will also
be received, irrespective of the condition of address
search mode bit (WR3: D2). In general receive mode
(WR3: D2 = 0), all frames will be received.

used to start a DMA transfer or a block transfer sequence using WAIT to synchronize the data transfer to
received or transmitted data.
External Status Interrupts

Any change in CD input or Abort detection in the received data, will generate an interrupt if External Status
Interrupt was enabled (WRI: DO).

Transmitter
Result
Disabled during
1. Data Transmission Tx Data will send idle
characters' which will be
zero inserted.

Special Receive Conditions

The receiver buffer is quadruply buffered. If the CPU
fails to respond to "receive character" available interrupt within a period of three byte times (received
bytes), the receiver buffer will overflow and generate an
interrupt. Finally, at the end of the received frame, an
interrupt will be generated when a valid ending flag has
been detected.

2. CRC Transmission 16 bit transmission,
corresponding to 16 bits of
CRC will be completed.
However, flag bits will be
substituted in the CRC field.
3. Immediately after
issuing ABORT
command.

Abort will still be
transmitted-output will be
in the mark state.

Receive Character Length

The receive character length (6, 7 or 8 bits/character)
may be changed during reception. However, to ensure
that the change is effective on the next received character, this must be done fast enough such that the bits
specified for the next character have not been assembled.
.

Figure 12. Transmitter Disabled
During Transmission

'NOTE:
Idle characters are defined as a string of 15 or more
contiguous ones.
Since the MPSC only recognizes single byte address
field, extended address recognition will have to be done
by the CPU on the data passed on by the MPSC. If the
first address byte is checked by the MPSC, and the
CPU determines that the second address byte does not
have the correct address field, it must set the Hunt
Mode (WR3: D2 = I) and the MPSC will start searching for a new address byte preceded by a flag.

CRC Checking

The opening flag in the frame resets the receive CRC
generator and any field between the opening and closing flag is checked for the CRC. In case of a CRC
error, the CRC/Framing Error bit in status register I is
set (RRI: D6 = I). Receiver CRC may be disabled/enabled by WR3,D3. The CRC bytes on the received
frame are passed on to the CPU just like data, and may
be discarded by the CPU.

Programmable Interrupts

The receiver may be programmed into anyone of the
four modes. See Figure 13 for details.
WR1,CHA

04
0
0

03
0

Receive Terminator

An end of frame is indicated by End of Frame interrupt. The CPU may issue an "Error Reset" command
to reset this interrupt.

Rx Interrupt Mode
Rx INT IDMA disable

DMA (Direct Memory Access) Mode

Rx INT on first character
INT on all Rx characters
(Parity affects vector)

The 8274 can be interfaced directly to the Intel DMA
Controllers 8237A, 8257A and Intel I/O Processor
8089. The 8274 can be programmed into DMA mode
by setting appropriate bits in WR2A. See Figure II for
details.

INT on all Rx characters
(Parity does not affect vector)

Figure 13. Receiver Interrupt Modes

All receiver interrupts can be disabled by WRI: D4 D3
= 00. Receiver interrupt on first character is normally
2-400

infef

AP-145

TRANSMIT IN DMA MODE

After initializing the 8274 into the DMA mode, the
first character must be loaded from the CPU to start
the DMA cycle. When the first data character (may be
the address byte in SDLC) is transferred from the
transmit buffer to the transmit serial shift register, the
transmit buffer gets empty and a transmit DMA request (TxDRQ) is generated for the channel. Just like
the interrupt mode, to ensure that the CRC bytes are
included in the frame, the transmit under-run/EOM
latch must be reset. This should preferably be done after loading the first character from the CPU. The
DMA will progress without any CPU intervention.
When the DMA controller reaches the terminal count,
it will not respond to the DMA r~quest, thus letting the
MPSC under-run. This will ensure CRC transmission.
However, the U1ider-run condition will generate an interrupt due to the Tx under-run/EOM bit getting set
(RRO: D6). The CPU should issue a "Reset TxInti
DRQ pending" command to reset TxDRQ and issue a
"Reset External Status" command to reset Tx Underrun/EOM interrupt. Following the CRC transmission,
flag (7EH) will be loaded into the transmit buffer. This
will also generate the TxDRQ since the transmit buffer
is empty following the transmission of the CRC bytes.
The CPU may issue a "Reset TxINT/DRQ pending"
command to reset the TxDRQ. "Reset TxINT/DRQ
pending" command must be issued before setting up
the transmit DMA channel on the DMA Controller,
otherwise the MPSC will start the DMA transfer immediately after the DMA channel is set up.
RECEIVE IN DMA MODE

The receiver must be programmed in RxINT on first
receive character mode (WRI: D4 D3 = 0 1). Upon
receiving the first character, which may be the address
byte in SDLC, the MPSC generates an interrupt and
also generates a Rx DMA Request (Rx DRQ) for the
appropriate channel. The CPU has three byte times to
service this interrupt (enable theDMA controller, etc.)
before the receiver buffer will overflow. It is advisable
to initialize the DMA controller before receiving the
first character. In case of high bit rates, the CPU will
have to service the interrupt very fast in order to avoid
receiver over-run.
Once the DMA is enabled, the received data is transferred to the memory under DMA control. Any received error conditions or external status change condition will generate an interrupt as in the interrupt driven
mode. The End of Frame is indicated by the End of
Frame interrupt which is generated on reception of the
closing flag of the SDLC frame. This End of Frame
condition also disables the Receive DMA request. The

End of Frame interrupt may be reset by issuing an "Error Reset" command to the MPSC. The "Error Reset"
command also re-enables the Receive DMA request. It
may be noted that the End of Frame condition sets bit
D7 in RRI. This bit gets reset by "Error Reset" command. However, End of Frame bit (RRI: D7) can also
be reset by the flag of the next incoming frame. For
proper operation, Error Reset Command should be issued "after" the End of Frame Bit (RRI: D7) is set. In
a more general case, "Error Reset" command should be
issued after End of Frame, Receive over-run or Receive
parity bit are set in RRI.

Wait Mode
The wait mode is normally used for block transfer by
synchronizing the data transfer through the Ready output from the MPSC, which may be connected to the
Ready input of the CPU. The mode can be programmed by WR I, D7 D5 and may be programmed
separately and independently on CH A and CH B. The
Wait Mode will be operative if the following conditions
are satisfied.
(i)
(ii)

Interrupts are enabled.
Wait Mode is enabled (WRI: D7) ,

(iii) CS = 0, Al = 0

The ROY output becomes active when the transmitter
buffer is full or receiver buffer is empty. This way the
ROY output from the MPSC can be used to extend the
CPU read and write cycle by inserting WAIT states.
RDY A or RDYB are in high impedance state when the
corresponding channel is not selected. This makes it
possible to connect ROY A and RDYB outputs in wired
OR configuration. Caution must be exercised here in
using the RDY outputs of the MPSC or else the CPU
may hang up for indefinite period. For example, let us
assume that transmitter buffer is full and RO!Ajs active, forcing the CPU into a wait state. If the CTS goes
inactive 'during this period, the ROY A will remain active for indefinite period and CPU will continue to insert wait states.

Vectored/Non-Vectored Mode
The MPSC is capable of providing an interrupt vector
in response to the interrupt acknowledge sequence from
the CPU. WR2, CH B contains this vector and the
vector can be read in status register RR2. WR2, CH A
(bit D5) can program' the MPSC in vectored or nonvectored mode. See Figure 14 for details.

2-401

inter

AP-145

In both cases, WR2 may still have the vector stored in
it. However, in vectored mode, the MPSC will put the
vector on the datil bus in response to the INTA (Interrupt Acknowledge) sequence as shown in Figure 15. In
non-vectored mode, the MPSC will not respond to the
INTA sequence. However, the CPU can read the vector by polling Status Register RR2. WR2A, D4 and D3
can be programmed to respond to 8085 or 8086 INTA
sequence. It may be noted here that IPI (Interrupt Priority In) pin on the MPSC must be active for the vector
to appear on the data bus.
WR2A,05
0
1

STATUS AFFECT VECTOR
The Vector stored in WR2B can be modified by the .
source of the interrupt. This can be done by setting the
status Affect Vector bit (WRI: D2). This powerful feature of the MPSC provides fast interrupt response time,
by eliminating the need of writing a routine to read the
status of the MPSC. Three bits of the vector are modified in eight different ways as shown on Figure 16. Bits
V4, V3, V2 are modified in 8085 based system and bits
V2, VI, VO are modified in 8086/88 based system.
In non-vectored mode, the status affect vector mode
can still be used and the vector read by the CPU. Status
register RR2B (Read Register 2 in Channel B) will contain this modified vector.

Interrupt Mode
Non-vectored Interrupt
Vectored Interrupt

Figure 14. Vectored Interrupt

05
0
1
1
1
1
1
1

WR2A
04
X
0
0
0
0
1
1

03
X
0
0
1
1
0
0

IPI

Mode

1st INTA

2nd INTA

3rd INTA

X
0
1
0
1
0
1

Non-Vectored
8085-1
8085-1
8085-2
8085-2
8086
8086

HI-Z
11001101
11001101
HI-Z
HI-Z
HI-Z
HI-Z

HI-Z
V7 V6 V5 V4 V3 V2V1 VO
HI-Z
V7V6V5V4V3V2V1 VO
HI-Z
V7V6 V5 V4 V3 V2 V1 VO
HI-Z

HI-Z
00000000
HI-Z
00000000
HI-Z

Figure 15. MPSC Vectored Interrupts
(8085
(8086)

V4
V2
0
0
0
0
.1
1
1
1

V3
V1
0
0
1
1
0
0
1
1

V2
VO
0
1
0
1
0
1
0
1

Channel

Interrupt Source

Tx Buffer Empty
EXT 1STAT Change
RX CHAR Available
Special Rx Condition
Tx Buffer Empty
EXT/STATChange
RX CHAR Available
Special Rx Condition

Rx SpeCial ConditIOn: Panty Error, Frammg Error, Rx Over-run Error, EOF (SDLC) .
EXT/STAT Change: Change in Modem Control Pin Status: CTS, DCD, SYNC, EOM, Break/Abort Detection.

Figure 16. Status Affect Vector Mode

2-402

inter

AP-145

DUAL PORT ACCESS
CONTROL

6273,6274

6255A

6254·2

6259A

SERIAL

PARALLEL
I/O

PIT
COUNTERS

INTERRUPT
CONTROL

I/O

LED'S

MULTIBUS
ADDRESS BITS
ADR14/·17/

CHANNEL C

210403-6

Figure 17. Functional Block Diagram-iSBC® 88/45

APPLICATION EXAMPLE
This section describes the hardware and software of an
8274/8088 system. The hardware vehicle used is the
INTEL Single Board Computer iSBC 88/45-Advanced Communication Controller. The software
which exercises the 8274 is written in PLM 86, This
example will demonstrate how 8274 can be configured
into the SDLC mode and transfer data through DMA
control. The hardware example will help the reader
configure his hardware and the software examples will
help in developing an application software. Most software examples closely approximate real data link controller software in the SDLC communication and may
be used with very little modification.

board and the schematics, refer to Hardware Manual
for the iSBC 88/45, Advanced Communication Controller. iSBC 88/45 is an intelligent slave/multimaster
communication board based on the 8088 processor, the
8274 and the 8273 SDLC/HDLC controller. Figure 17
shows the functional block diagram of the board. The
iSBC 88/45 has the following features,

iSBC® 88/45
A brief description of the iSBC 88/45 board will be
presented here. For more detailed information on the

2-403

• 8 MHz processor
• 16K bytes of static RAM (12K dual port)
• Multimaster/Intelligent Slave Multibus Interface
• Nine Interrupt Levels 8259A
• Two serial channels through 8274
• One Serial channel through 8273
• S/W programmable baud rate generator
• Interfaces: RS232, RS422/449, CCITT V.24
• 8237A DMA controller
• Baud Rate to 800K Baud

Ap·145

INITIALIZE_B274:PROCEDURE PUBLIC;
1************************************************************************1
1*

INITIALIZE THE B274 FOR SDLC MODE
1*
*1
1*
*1
1. RESET CHANNEL
1*
*1
2. EXTERNAL INTERRUPTS ENABLED
1*
*1
1*
3. NO WAIT
*1
RTS
4. PIN 10
1*
*1
5. NON-VECTORED INTERRUPT-BOBb MODE
1*
*1
b. CHANNEL A DMA. CH B INT
1*
*1
B BITS/CHAR
7. TX AND RX
1*
*1
9. ADDRESS SEARCH MODE
*I
1*
10. CD AND CTS AUTO ENABLE
1*
*1
II. XI CLOCK
1*
*1
12. NO PARITY
1*
*1
13. SDLC/HDLC MODE
1*
*1
14. RTS AND DTR
1*
*1
15. CCITT - CRC
1*
*1
lb. TRANSMITTER AND RECEIVER ENABLED
1*
*1
17. 7EH
FLAG
1*
*1
1*·
*1
1************************************************************************1

DECLARE C BYTE;
TABLE TO INITIALIZE THE 8274 CHANNEL A AND B
/* FORMAT IS: WRITE REGISTER. REGISTER DATA
1* INITIALIZE CHANNEL A ONLY
/*

*1
*1
*1

DECLARE TABLE]4_A(*) BYTE DATA
(OOH.IBH.
1* CHANNEL RESET *1
00H.80H.
1* RESET TX CRe *1
02H. IIH.
1* PIN 10=RTSB. A DMA. B INT *1
04H.20H.
1* SDLC/HDLC MODE. NO PARITY *1
07H.07EH.
1* SOLe FLAG *1
OIH.OBH.
1* RX DMA ENABLE *1
OSH.OEBH.
1* DTR. RTS. 8 TX BITS. TX ENABLE .• I
1* SDLC CRC. TX CRC ENABLE *1
ObH.55H.
1* DEFAULT ADDRESS *1
03H.OD9H.
1* 8 RX BITS. AUTO ENABLES. HUNT MODE. *1
1* RX CRC ENABLE *1
OFFH);
1* END OF INITIALIZATION TABLE *1
DECLARE TABLE_74_B(.) BYTE DATA
(02H.00H.
1* INTERRUPT VECTOR */
OIH.ICH.
1* STATUS AFFECTS VECTOR *1
OFFH);
1* END *1
1* INITIALIZE THE 8274 *1

C=O;
DO I~HILE TABLE_74_B(C) <> OFFH;
OUTPUT(COMMAND_B_74)
TABLE_74_B(C);
C=C+1;

OUTPUT OFFH;
OUTPUT(COMMAND_A]4)
TABLE]4_A( C I;
C=C+1 ;

OUTPUT (COMMAND_A]4)

TABLE]4_A(C),

C=C+1 ;

END;
RETURN;
END INITIALIZE_B274'
210403-7

Figure 18. Typical MPSC SDLC Initialization Sequence

2-404

inter

Ap·145

For this application, the CPU is run at 8 MHz. The
board is configured to operate the 8274 in SDLC operation with the data transfer in DMA mode using the
8237 A. 8274 is configured first in non-vectored mode in
which case the INTEL Priority Interrupt Controller
8259A is used to resolve priority between various interrupting sources on the board and subsequently interrupt the CPU. However, the vectored mode of the 8274
is also verified by disabling the 8259A and reading the
vectors from the 8274. Software examples for each case
will be shown later.
The application example is interrupt driven and uses
DMA for all data transfers under 8237 A control. The
8254 provides the transmit and receive clocks for the
8274. The 8274 was run at 400K baud with a local
loopback Gumper wire) on Channel A data. The board
was also run at 800K baud by modifying the software
as will be discussed later in the Special Applications
section. One detail to note is that the Rx Channel
DMA request line from the 8274 has higher priority
than the Tx Channel DMA request line. The 8274 master clock was 4.0 MHz. The on-board RAM is used to
define transmit and receive data buffers. In this application, the data is read from memory location 800H
through 810H and transferred to memory location
900H to 910H through the 8274 Serial Link. The operation is full duplex. 8274 modem control pins, CTS and
CD have been tied low (active).

on first reCeive character has been programmed although Channel A is in the DMA mode.

Interrupt Routines
The 8274 interrupt routines will be discussed here. On
an 8274 interrupt, program branches off to the "Main
Interrupt Routine". In main interrupt routine, status
register RR2 is read. RR2 contains the modified vector.
The cause of the interrupt is determined by reading the
modified bits of the vector. Note that the 8274 has been
programmed in the non-vectored mode and status affects vector bit has been set. Depending on the value of
the modified bits, the appropriate interrupt routine is
called. See Figure 19 for the flow diagram and Figure
20 for the source code. Note that an End of Interrupt
Command is issued after servicing the interrupt. This is
necessary to euable the lower priority interrupts.
Figure 21 shows all the interrupt routines called by the
Main Interrupt Routine. "Ignore-Interrupt" as the
name implies, ignores any interrupts and sets the FAIL
flag. This is done because this program is for Channel
A only and we are ignoring any Channel B interrupts.
The important thing to note is the Channel A Receiver
Character available routine. This routine is called after
receiving the first character in the SDLC frame. Since
the transfer mode is DMA, we have a maximum of
three character times to service this interrupt by enabling the DMA controller.

Software
The software consists of a monitor program and a program to exercise the 8274 in the SDLC mode. Appendix A contains the entire program listing. For the sake
of clarity, each source module has been rewritten in a
simple language and will be discussed here individually.
Note that some labels in the actual listings in the Appendix will not match with the labels here. Also the
listing in the Appendix sets up some flags to communicate with the monitor. Some of these flags are not explained in detail for the reason that they are not pertinent to this discussion. The monitor takes the command from a keyboard and executes this program, logging any error condition which might occur.

8274 Initialization
The MPSC is initialized in the SDLC mode for Channel A. Channel B is disabled. See Figure 18 for the
initialization routine. Note that WR4 is initialized before setting up the transmitter and receive parameters.
However, it may also be pointed out that other than
WR4, all the other registers may be programmed in any
order. Also SDLC-CRC has been programmed for correct operation. An incorrect CRC selection will result
in incorrect operation. Also note that receive interrupt

2-405

IF V2V1VO IF V2V1VO IF V2V1VO IF V2V1VO IF V2V1VO IF V2V1VO -

0, CALL IGNORE - INTERRUPT
1, CALL IGNORE -INTERRUPT
2, CALL CHB Rx CHAR
3, CALL IGNORE -INTERRUPT
4, CALL IGNORE -INTERRUPT
5, CALL CHA - EXTERNAL CHANGE
INTERRUPT
IF V2V1VO - 6, CALL CHA Rx CHAR
IF V2V1VO - 7, CALL CHA Rx SPECIAL

210403-8

Figure 19. Interrupt Response Flow Diagram

AP·145

1**************************1
1* MAIN INTERRUPT ROUTINE *1

1**************************1

OUTPUT (COMMAND_B_74)
2;
TEMP
INPUT (STATUS_B_74) AND 07Hl

1* SET POINTER 'TO 2*1
1* READ INTERRUPT VECTOR *1
1* CHECK FOR CHA tNT ONLY_I

1* FOR THIS APPLICATION CH B INTERRUPTS ARE IGNORED.I
DO CASE TEMP;
IGNORE_I NT;
CALL
1* V2VIVO
000*1
IGNORE_INT;
CALL
1* V2VIVO
001*1
CHB_RX_CHAR;
CALL
1* V2VIVO
010*1
CALL
IGNORE_I NT;
1* V2VIVO = 011_1
IGNORE_I NT;
CALL
1* V2VIVO
100*1
CHA_EXTERNAL_CHANGE;
CALL
1* V2VIVO = 101*1
CALL
CHA_RX_CHAR;
1* V2VIVQ = 110*1
CALL
CHA_RX_SPEC I ALi
1* V2VIVO
111*1
END;
OUTPUTlCOMMAND_A_74l ~38H;
1* END OF INTERRUPT FOR 8274 *1
RETURN;
END INTERRUPT_8274;

=
=
=
=

210403-9

Figure 20. Typical Main Interrupt Routine

1******************************************************1

1* CHANNEL A EXTERNALISTATUS CHANGE ·INTERRUPT HANDLER *1

1******************************************************1
CHA_EXTERNAL_CHANGE:

PROCEDURE;

TEMP a INPUHSTATUS_AJ4);
1* STATUS REG 1*1
IF CTEMP AND END_OF _TX~MESSAGE) = END_OF _TX_MESSAGE THEN
TXDONE S=DONE;
ELSE DO;
-

TXDONE SI::CONEs
RESULTS_S=FAILI
END;
OUTPUTCCOMMAND_A_74) = lOH;
RETURN;
END CHA_EXTERNAL_CHANGE;

1* RESET EXT/STATUS INTERRUPTS *1

1**********************************************************1

1* CHANNEL A SPECIAL RECEIVE CONDITIONS INTERRUPT HANDLER *1
I ********************************************************** I
CHA_RX_SPEC IAL: PROCEDURE.

OUTPUTCCOMMAND_AJ4) - 1;
TEMP = INPUTISTATUS_AJ4);
IF (TEMP AND END_OF ]RAME) = END_OF _FRAME THEN
DO;
IFCTEMP AND 040H) = 040H THEN
RESULTS 5 = FAIL;
1* eRe ERROR *1
RXDONE_S ;- DONE;
OUTPUTICOMMAND_A]4) = 30H; I*ERROR RESET*I
END;
ELSE DO;
, IF CTEMP AND 20H) = 20H THEN DO;·
RESULTS_S = FAIL
/* RX OVERRUN ERROR*I
RXDONE_S
DONE;
OUTPUTICOMMAND_A_74)
30H; I*ERROR RESET*I
END;
END;

RETURN.
END CHA_RX_SPECIALi

1*****************************************1

1* CHANNEL A RECEIVE CHARACTER AVAILABLE */

1*****************************************,
CHA_RX_CHAR: PROCEDURE;
OUTPUT (SINGLE_MASK) = CHO_SELI
RETURN;
END CHA_RX_CHAR;

I-ENABLE RX DMA CHANNEL_I

210403-10

Figure 21. 8274 Typical Interrupt Handling Routines

2-406

intJ

AP·145

It may be recalled that the receiver buffer is three bytes
deep in addition to the receiver shift register. At very
high data rates, it may not be possible to have enough
time to read RR2, enable the DMA controller without
overrunning the receiver. In a case like this, the DMA
controller may be left enabled before receiving the Receive Character Interrupt. Remember, the Rx DMA
request and interrupt for the receive character appears
at the same time. If the DMA controller is enabled, it
would service the DMA request by reading the received
character. This will make the 8274 interrupt line go
inactive. However, the 8259A has latched the interrupt
and a regular interrupt acknowledge sequence still occurs after the DMA controller has completed the transfer and given up the bus. The 8259A will return Level 7
interrupt since the 8274 interrupt has gone away. The
user software must take this into account, otherwise the
CPU will hang up.

The procedure shown for the Special Receive Condition
Interrupt checks if the interrupt is due to the End of
Frame. If this is not TRUE, the FAIL flag is set and
the program aborted. For a real life system, this must

be followed up by error recovery procedures which obviously are beyond the scope of this Application Note.
The transmission is terminated when. the End of Message (RRO, D6) interrupt is generated. This interrupt is
serviced in the Channel A External/Status Change interrupt procedure. For any other change in external
status conditions, the program is aborted and a FAIL
flag set.

Main Program
Finally, we will briefly discuss the main program. Figure 22 shows the source program. It may be noted that
the Transmit Under-run latch is reset after loading the
first character into the 8274. This is done to ensure
CRC transmission at the end of the frame. Also, the
first character .is loaded from the CPU to start DMA
transfer of subsequent data. This concludes our discussion on hardware and software example. Appendix A
also includes the software written to exercise the 8274
in the vectored mode by disabling the 8259A.

CHA_SDLC_TEST: PROCEDURE BYTE PUBLICi
CALL
ENABLE INTERRUPTS Si
CALL
INIT_8274_SDLC5iENABLE;
OUTPUTICOMMAND A 741 = 2BHi /* RESET TX INT IDMA
*1
OUTPUTICOMMAND -B -741 = 28Hi '* BEFORE INITIALIZING 8237*'
CALL
INIT_8237_Si
OUTPUTIDATA_A_741 = 55Hi
'*LOAD FIRST CHARACTER FROM
,*CPU *'
'* TO ENSURE CRC TRANSMISSION, RESET TX UNDERRUN LATCH */
OUTPUTICOMMAND A 741 = OCOHi
RXDONE_S, TXDONEj=NOT _DONE; /* CLEAR ALL FLAGS
*/
RESULTS_S=PASSi
/* FLAG SET FOR MONITOR
DO WHILE TXDONE5c NOT _DONEi
DO UNTIL TERMINAL COUNT
ENDi

*'*'

DO WHILEIINPUTISTATUS A 741 AND 04HI <> 04H;
/* WAIT FOR CRC TO GET TRANSMITTED 1/
/* TEST FOR TX BUFFFER EMPTY TO VERIFY THIS*/
ENDi
DO WHILE RXDONE_S=NOT _DONEi '* DO UNTIL TERMINAL COUNT */
END;
CALL
STOP 8237 Si
END CHA_SDLC_TEST; -

210403-11

Figure 22. Typical 8274 Transmit/Receive Set-Up in SOLe Mode

2-407

inter

AP-145

Vee

CPU

INT~~}-~--~---1----------------~------__- - - - - -

INTAb-----------~--4_------------~--t_---------------

8085 CPU

8085 INTERRUPT
MODE 1

IAPX·88/86
CPU

8088/86
INTERRUPT MODE

8085 INTERRUPT
MODE 3
8088/86
INTERRUPT MODE

8088/86
INTERRUPT MODE

210403-12

Figure 23. 8274 Daisy Chain Vectored Mode
It may be pointed out that lOP to IPI delay time specification is lOOns.

SPECIAL APPLICATIONS
In this section, some special application issues will be
discussed. This will be useful to a user who may be
using a mode which is possible with the 8274 but not
explicitly explained in the data sheet.

Priority
Number of 8274s
System
Resolution Time Daisy Chained
Configuration
(Max)
Min (ns)
8086-1
8086-2
8086
8088
8085-2
8085A

MPSC Daisy Chain Operation
Multiple MPSCs can be connected in a daisy-chain
configuration (see Figure'23). This feature may be useful in an application where multiple communication
channels may be required and because of high data
rates, conventional interrupt controller is not used to
avoid long interrupt response times. To configure the
MPSCs for the daisy chain operation, the interrupt priority input pins (IPI) and interrupt priority output pins
(IPO) of the MPSC should be connected as shown. The
highest priority device has its IPI pin connected to
ground. Each MPSC is progr~mmed in a vector~d
mode with status affects vector bIt set. In the 8085 basIc
systems, only one MPSC should be programmed in the
8085 Mode 1. This is the MPSC which will put the call
vector (CO Hex) on the data bus in response to the first
INTA pulse (see Figure IS). It may be pointed out that
the MPSC in 8085 Mode I will provide the call vector
irrespective of the state ofIPI pin. Once a higher priority MPSC generates an interrupt, its IPO pin goes inactive thus preventing lower priority MPSCs from interrupting the CPU. Preferably the highest priority MPSC
should be programmed in 8085 Mode 1. It may be recalled that the Priority Resolve Time on a given MPSC
extends from the falling edge of the first INTA pulse to
the falling edge of the second INTA pulse. Ouring this
period, no new internal interrupt requests are accepted.
The maximum number of the MPSCs that can be connected in a daisy chain is limited by the Priority Resolution Time. Figure 24 shows a maximum number of
MPSCs that can be connected in various CPU systems.

400
500
800
800
1200
1920

4
5
8
8
12
19

NOTE:
, Zero wait states have been assumed.

Figure 24. 8274 Daisy Chain Operation

Bisync Transparent Communication
Bisync applications generally require that data transparency be established during communication. This requires that the special control characters may not be
included in the CRC accumulation. Refer to the Synchronous Protocol Overview section fora more detailed
discussion on data transparency. The 8274 can be used
for transparent communication in Bisync communications. This is made possible by the capability of the
MPSC to selectively turnon/turnoff the CRC accumulation while transmitting or receiving. In bisync transparent transmit mode, the special characters (OLE,
OLE SYN, etc) are excluded from CRC calculation.
This can be easily accomplished by turning off the
transmit CRC calculation (WR5: 05 = 0) before loading the special character into the transmit buffer. If the
next character is to be included in the CRC accumulation, then the CRC can be enabled (WR5: 05 = I). See
Figure 25 for a typical flow diagram.

2-408

inter

, AP-145

210403-14

Figure 25. Transmit in Bisync Transparent Mode

Figure 26. Receive in Bisync Transparent Mode

During reception, it is possible to exclude received
character from CRC calculation by turning off the Receive CRC after reading the special character. This is
made possible by the fact that the received data is presented to receive CRC checker 8 bit times after the
character has been received. During this 8 bit times, the
CPU must read the character and decide if it wants to
be included in the CRC calculation. Figure 26 shows
the typical flow diagram to achieve this.
It should be noted that. the CRC generator must be

enabled during CRC reception. Also, after reading the
CRC bytes, two more characters (SYNC) must be read
before checking for CRC check result in RRI.

Auto Enable Mode
In some data communication applications, it may be
required to enable the transmitter or the receiver when
the ·CTS or the CD lines respectively, are activated by
the modems. This may be done very easily by programming the 8274 into the Auto Enable Mode. The auto
enable mode is set by writing a 'I' to WR3,D5, The
function of this mode is to enable the transmitter automatically when CTS goes active. The receiver is enabled when CD goes active. An in-active state of CTS
or CD pin will disable the transmitter or the receiver
respectively. However,the Transmit Enable bit
(WR5:D3) and Receive Enable bit (WR3:Dl) must be
set in order to use the auto enable mode. In non-auto
mode, the transmitter or receiver is enabled if the corresponding bits are set in WR5 and WR3, irrespective of
the state CTS or CD pins. It may be recalled that any
transition on CTS or CD pin will generate External/
Status Interrupt with the corresponding bits set in
RRI. This interrupt can be cleared by issuing a Reset
External/Status interrupt command as discussed earlier.
Note that in auto enable mode, the character to be
transmitted must be loaded into the transmit buffer af-

ter the CTS becomes active, not before. Any character
loaded into the transmit buffer before the CTS became
active will not be transmitted.

High Speed DMA Operation
In the section titled Application Example, the MPSC
has been programmed to operate in DMA mode and
receiver is programmed to generate an interrupt on ~he
first receive character. You may recall that the receive
FIFO is three bytes deep. On receiving the interrupt on
the first receive character, the CPU must enable the
DMA controller within three received byte times to
avoid receiver over-run condition. In the application
example at 400K baud, the CPU had approximately
60 /ks t~ enable the DMA controller to avoid receiver
buffer overflow. However, at higher baud rates, the
CPU may not have enough time to enable the DMA
controller in time. For example, at 1M baud, the CPU
should enable the DMA controller within approximately 24 /ks to avoid receiver buffer overrun. In most applications, this is not sufficient time. To solve this problem the DMA controller should be left enabled before
getting the interrupt on the first receive character
(which is accompanied by the Rx DMA request for the
appropriate channel). This will allow he DMA controller to start DMA transfer as soon as the Rx DMA
request becomes active without giving the CPU enou.gh
time to respond to the interrupt on the first receive
character. The CPU will respond to the interrupt after
the DMA transfer has been completed and will find the
8259A (see Application Example) responding with interrupt level 7, the lowest priority level. Note that the
8274 interrupt request was satisfied by the DMA controller, hence the interrupt on the first receive character
was cleared and the 8259A had no pending interrupt.
Because of no pending interrupt, the 8259A returned
interrupt level 7 in response to the INTA sequence
from the CPU. The user software should take care of
this interrupt.

2-409

inter

AP-145

PROGRAMMING HINTS

Transmit Under-Run/EOM Latch

This section will describe some useful programming
hints which may be useful in program development.

In SDLC/HDLC, bisync and monosync mode, the
transmit underrun/EOM must be reset to enable the
CRC check bytes to be appended to the transmit frame
or transmit message. The transmit under-run/EOM
latch can be reset only after the first character is loaded
into the transmit buffer. When the transmitter underruns at the end of the frame, CRC check bytes are
appended to the frame/message. The transmit under·
runlEOM latch can be reset at any time during the
transmission after the first character. However, it
should be reset before the transmitter under-runs otherwise, both bytes of the CRC may not be appended to
the frame/message. In the receive mode in bisync operation, the CPU must read the CRC bytes and two more
SYNC characters before checking for valid CRC result
in RRI.

Asynchronous Operation
At the end of transmission, the CPU must issue "Reset
Transmit Interrupt/DMA Pending" command in WRO
to reset the last transmit empty request which was not
satisfied. Failing to do so will result in the MPSC locking up in a transmit empty state forever.

Non-Vectored Mode
In non-vectored mode, the Interrupt Acknowledge pin
(INTA) on the MPSC must be tied high through a pullup resistor. Failing to do so will result in unprediCtable
response from the 8274.

Sync Character Load Inhibit

When receiving data in SDLC mode, the CRC bytes
must be read by the CPU (or DMA controller) just like
any other data field.· Failing to do so will result in receiver buffer overflow. Also, the End of Frame Interrupt indicates that the entire frame has been received.
At this point, the CRC result (RRI:D6) and residue
code (RRI:D3, D2, DI) may be checked.

In bisync/monosync mode only, it is possible to prevent
loading sync characters into the receive buffers by setting the sync character load inhibit bit (WR3:Dl = 1).
Caution must be exercised in using this option. It may
be possible to get a CRC character in the received message which may match the sync character and not get
transferred to the receive buffer. However, sync character load inhibit should be enabled during all pre-frame
sync characters so the software routine does not have to
read them from the MPSC.

Status Register RR2

In SDLC/HDLC mode, sync character load inhibit bit
must be reset to zero for proper operation.

ChB RR2 contains the vector which gets modified to
indicate the source of interrupt (see the section titled
MPSC Modes of Operation). However, the state of the
vector does not change if no new interrupts are generated. The contents of ChB RR2 are only changed when a
new interrupt is generated. In order to get the correct
information, RR2 must be read 'only after an interrupt
is generated, otherwise it will indiCate the previous
state.

EOI command can only be issued through channel A
irrespective of which channel had generated the interrupt.

HOLC/SOLC Mode

EOI Command

Priority in OMA Mode

Initialization Sequence
The MPSC initialization routine must issue a channel
Reset Command at the beginning. WR4 should be defined before other registers. At the end of the initialization sequence, Reset External/Status and Error Reset
cOIllmands should be issued to clear any spurious interrupts which may have been caused at power up.

There is no priority in DMA mode between the following four singals: TxDRQ(CHA), RxDRQ(CHA),
TxDRQ(CHB), RxDRQ(CHB). The priority between
these four signals must be resolved by the DMA controller. At any given time, all four DMA channels from
the 8274 are capable of going active.

2-410

AP-145

APPENDIX A
APPLICATION EXAMPLE: SOFTWARE LISTINGS

PL./M-B6 CQMP ILER

1SBC

8B/4~

8274 CHANNEL A SOLe TEST

SERIES-III PL/M-B6 V2.0 COMPILATION OF MODULE INIT_8274_S
OBJECT MODULE PLACED IN : Fl: SINI74. OBJ
COMPILER INVOKED BY:
PLM8b.8b :FI:SINI74.PLM TITLE(iSBC 88/458274 CHANNEL
A SOLe TEST) COMPACT NOINTVECTOR ROM

1* •••••••••••••••••••••••••••••• * •••••• **** •••• **./

1*
1*
1*
1*
f*
1*
f*
f*
f*
f*
1*
f*
f*
f*
f*
f*
f*
f*
f*
f*

*1
INITIALIZE THE 8274 FOR SOLe MODE

*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1

RESET CHANNEL
2. EXTERNAL INTERRUPTS ENABLED
3. Nil WAIT
4. PIN 10 = RTS
5. NON-VECTORED INTERRUPT-808b MODE
b. CHANNEL A DMA, CH B INT
7. TX AND R X = B B ITSfCHAR
9. ADDRESS SEARCH MODE
10. CD AND CTS AUTO ENABLE
11. Xl CLOCK

12. NO PARITY
13. SDLCfHDLC MODE
14. RTS AND DTR
1'. CCITT - CRC
lb. TRANSMITTER AND RECEIVER ENABLED
t7.7EH .. FLAQ

/ •• ***••• ***** •••••• ***** ••••• ** •••••••••••••••••• /
INIT _8274_S:

DO;

.INCLUDE (: Fl: PORTS. PLMI

1********** •••***.* •••• **********.**·*********'
/*

ISDC 88f45 PORT ASSIGNMENTS

1**.***..*** •••••••***.***•• • ••··.···········**1
2

DECLARE LIT LITERALLY 'LITERALLY';

DECLARE CHO_ADDR
CHO COUNT
CHI=ADDR
CHI_COUNT
CH2_ADDR
CH2_COUNT
CH3_ADDR
CH3_COUNT
STATUS_37
COMMAND_37
REQUEST ..REG_37
SINGLE_MASK
MODE_REG_37

1* S237A-:5

PL/M-Bb COMPILER

PORTS *1
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OBOH' ,
'OB1H',
'082H',
'OB3H',
'OB4H' ,

'CSSH',
'OBbH' ,
'OB7H',
'08BH' ,
'08BH' ,
'OB9H' ,
'OBA~'.

'OBBH' ,

iSBC BBf4' 6274 CHANNEL A SOLC TEST

CLR_BYTE_PTR_37
TEMP _REQ_37
MASTER_CLEAR_37
ALL_MASK_37

LIT
LIT
LIT
LIT

'oaCH',

LIT
LIT
LIT

'090H' ,
'091H',
'092H' ,

'08DH',
'08DH' ,
'OBFH';

f* 8254-:2 PORTS *f
DECLARE CTR_OO
CTR_OI
CTR_02

210403-15

2-411

AP-145

CONTROLO_54
STATUSO_54
CTR_IO
CTR_II
CTRI2
CONTROL I_54
STATUSI_54

LIT
LIT
LIT
LIT
LIT
LI,T
LIT

'093H',
'093H' ,
'098H',
'099H' ,
'09AH',
'09BH' ,
'09BH' ;

LIT
LIT
LIT
LIT

'QAOH',

LIT
LIT
LIT
LIT
LIT
LIT

'ODOH' ,
'ODIH',
'OD2H',
'OD2H',
'OD3H',
'OD3H';

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OEOH',
'OEOH',
'OEOH',
'OEOH',
'OE1H',
'OElH',
'OEIH',

1* 8255 PORTS *1

DECLARE PORTA_55
PORTB_59
PORTC_55
CONTROL_55

'OAIH' ,
'OA2H',

'OA3H' ;

1* 8274 PORTS *1
6

DECLARE DATA_AJ4
DATA_BJ4
BTATUB_AJ4
CDMMAND_AJ4
BTATUS_BJ4
COMMAND_BJ4

DECLARE STATUS_POLL _59
ICWI_59
OCW2_59
OCW3_59
DCWI_59
ICW2_59
ICW3_59

1* 8259A PORTS *1

ICW4_S9

1* 8274 REGISTER BIT ASS I QNMENTS
1* READ REGISTER o *1

DECLARE RX_AVAIL
INT -"ENDING
TX_EMPTY
CARR IER_DETECT
SYNC_HUNT
CLEAR_TO_SEND

PL/M-86 COMPILER

LIT
LIT
LIT
LIT
LIT
LIT

'OE1H')

*I
'OIH',
'02H' ,
'04H',
'08H' ,
'IOH',
'20H' ,

iSDe 88/45 8274 CHANNEL A SOLe TEST

END_OF _TXJ1ESSAOE LIT
LIT
BREAK_ABORT

'40H',

'80H';

1* READ REGISTER I *1

LIT
LIT
LIT
LIT
LIT

'OIH',
'IOH',
'20H'.
'40H',

DECLARE TX_B_EMPTY
EXT_B3HANGE
RX_B_AVAIL
RX_B_SPECIAL
TX_A_EI'tPTY
EXT _A_CHANGE
RX_A_AVAIL

LIT
LIT
LIT
LIT
LIT
LIT
LIT

'OOH',
'OIH',
'02H' ,
'03H' ,
'04H',
'05H' ,
'ObH' ,

RX_A_SPECIAL

LIT

'07H'J

DECLARE ALL_SENT
PARITY_ERROR
RX_OVERRUN
CRC_ERROR
END_OF _FRAI1E

'BOH'J

1* READ REGISTER 2 *1

210403-16

2-412

inter

AP-145

1* 8237 BIT ASSIQNMENTS *1
11

DECLARE CHO_SEL
CHI_SEL
CH2_SEL
CH3_SEL

WRITE_XFER
READ_X FER
DEMAND _MODE
S I NOLE_MODE
BLOCK_MODE
SET_MASK
12
13
14
15
Ii.
17
IB

I
2
2
2
3
3
2

END.
END DELAY _S.

DECLARE C

19
20

LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT
LIT

·OOH'.
·OIH'.
·02H·.
·03H·.
'04H',
·OSH·.
·OOH'.
'4OH',

·BOH'.
'04H'j

DELAY_S: PROCEDURE PUBLIC.
DECLARE D WORD.
0-01
DO WHILE D OFFH.
OUTPUT t COI'tl'tAND _B _741
TABLE] 4 Jl t C I •

c-e+1;
OUTPUTtCOMMAND_B]4I = TADLE_74_BtCI.
C=C+I,
ENOl

210403-17

2-413

AP-145

33
34
3'
36
37
38
39
40
41
42
43

c=o,

2
3
3
3
3
3

DO WHILE TABLEJ4_A(C) C· OFFH;
OUTPUT 0
then outp ut (c h_a_c ommand)
rRg_no and Ofh;
return input(ch_a_command);
'>nd rra;
rrb: procedure (reg_no) byte;
declare reg_no byte;

if (reg_no and Of h) <> 0
then output (ch_b_command)
return input(ch_b_command);
end rrb;

write selected scc register

reg_no and Ofh;

wra: procedure (reg_no, value);
declare reg_no byte;
declare value byte;
if (reg_no and Of h) <> 0
then output (ch_a_command) = reg_no and Of hi
output (ch_a_command)
value;
end wra;

·wrb: proced ure (reg_no, va 1 ue);
declare reg_no by tel
declare value byte;
if (reg_no and Of h) <> 0
then output (ch_b_command) = reg_no and Ofh;
output (ch_b_command) ~ value;
end wrbl
1*---------------------------------------------------------------~----------*I
231262-2

Figure 2. Accessing the see Registers

2-429

intJ

AP-222

3. Initialization for ASYNC Operation

4. ASYNC Communication in Polling
Mode

In the following example, channel B of the SCC is used
to perform ASYNC communication. Figure 3 shows
how the channel B is initialized and configured for
ASYNC operation. This is done by writing the various
channel B registers with the proper parameters as
shown. The comments in the program show what is
achieved by each statement. After a software reset of
the channel, register #4 should be written before writing to the other registers. The on-chip Baud Rate Generator is used to generate a 1200 bits/sec clock for both
the transmitter and the receiver. The interrupts for
transmitter and/or receiver are .enabled only for the
interrupt mode of operation; for polling, interrupts
must be kept disabled.

Figure 4 shows the procedures for reading in a received
character from the 82530 (scc_in) and for writing out
a character to the 82530 (scc_out) in the p011ing mode.
The scc~n procedure returns a byte value which is the
character read in. The receiver is polled to find if a
character has been received by the SCC. Only when a
character has been received, the character is read in
from the data port of the SCC channel B.
The sec_out. procedure requires a byte parameter
which is the character being written out. The transmit-

1*-------------------------------------------------------------------------~*'

sec ch B register initialization for ASYNC mode
call
call
call
call
call
call
call
ca 11
ca 11
call
call
ca 11
call
call

IIIrb(09.
IIIrb (04.
IIIrb(02.
IIIrb (03.
IIIrb(05.
IIIrb (06.
IIIrb (07.
IIIT·bI09.
IIIrb (10.
IIIrb (11.
IIIrb (12.
IIIrb (13.
IIIrb (14.
IIIrb (15.

enables

1*
1*
1*
1*
1*

channel B reset *1
2 stop. no paritlj. brf
64x *1
vector
20h *1
rx 8 bits/char. no auto-enable *1
tx 8 bits/char *1

vector includes status

txc = BRG • trxc = BRG out *1
to generate 1200 baud. x64 (! 4 mhz *1

/* rxc

1* BRG
1* all

source = SYS eLK. enable BRG
ext status interrupts o~F */

call IIIrb(03.
call IIIrb (05.
I~

01000000b ) i
11001110b );
00100000b );
11000000b ) i
0110000011) i
OOOOOOOOb ) ;
OOOOOOOOb ) ;
00000001b );
OOOOOOOOb ) ;
01010110b );
000 1.1 OOOb ) i
OOOOOOOOb ) i
00000011 b) i
OOOOOOOOb ) i

U000001b );
11101010b) ;

enable interrupts -

call IIIrb109.
call IIIrb(01.

1*
1*

scc-b receive enable *1
scc-b transmit enab Ie. dtr on. rts on

only for interrupt driven ASYNC 1/0

00001001b);
00010011b);

1*
1*

master IE. vector includes status */
tx • rx. ext interrupts enable *1

1*-----------------------------_·_-------------------------------------------*1
231262-3

Figure 3. Initialization for ASYNC Communication

2-430

inter

AP-222

1*--------------------------------------------------------------------------*1
1* scc data character input from channel B *1
scc_in:

procedure byte;

declare char byte;
do while (input(ch_b_command) and lh) = 0; end;
char = input(ch_b_data);
1* if rx data character is available
return char;
1* then input it to buffer *1

scc data character output to channel B

scc_out: procedure (char);
declare char byte;
do while (input(ch_b_command) and 4h) = 0; end;
output(ch_b_data) = char;
1* if tx buff empty then transfer the *1
1* data character to tx buff *1

1*----------------------------------------------------------------·---------------*1
231262-4

Figure 4. ASYNC Communication in Polling Mode

ter is polled for being ready to transmit the next character before writing the character out to the data port of
see channel B.

Includes Status' (VIS) mode is set - WR9
XXXOXXOl. Vectors and the associated events are:
Vector

Typical calls to these procedures are:

20h

abc_variable = scc_in;
call scc_out (xyz_variable);

5. ASYNC Communication in Interrupt
Mode
In contrast to polling for the receiver and/or the transmitter to be ready with/for the next character, the
82530 can be made to interrupt when it is ready to do
receive or transmit.

Event Causing Interrupt

Procedure

txintr_b

ch;....b - transmit buffer empty

22h

esi

b - external/ status change

24h

rxintr

b - receive character available

26h

src_b

28h

txintr

2ah

esi_a

2ch

rxintr

2eh

src

b
b

ch_b - special receive condition
a

a
a

a - transmit buffer empty

ch_a - external/status change
ch

a - receive character available

a - special receive condition

NOTE:
Odd vector numbers do not exist.

The on-chip interrupt controller of the see can be
made to operate in the vectored mode. In this mode, it
generates interrupt vectors that are characteristic of the
event causing the interrupt. For the example here, the
vector base is programmed at 20h and 'Vector

2-431

Figure 5 shows the interrupt procedures for the channel
B operating in ASYNe mode. The transmitter buffer
empty interrupt occurs when the transmitter can accept
one more character to output. In the interrupt procedure for transmit, the byte char_out_530 is output.
Following this, is an epiloge that is common to all the

intJ

AP-222

interrupt procedures; the first statement is an end of
interrupt command to the 82530 - note that it is issued
to channel A - and the second is an End of Interrupt
(EOI) command to the 80186 interrupt controller
which is, in fact, receiving the interrupt from the 82530.

The receive buffer full interrupt occurs when the receiver has at least one character in its buffer, waiting to be
read in by the CPU.
The esLb is not enabled to occur and src_b cannot
occur in the ASYNC mode unless the receiver is overrun or a parity error occurs.

*-------------------------------------------------------~------------------*I

1* channel B interrupt procedure5 *1

procedure

call wra(OO,38h);
output (eoir_186)
return)
end txintr_b)
procedure

interrupt 20h)

BOOOh)

l' X

intr _b:

proceduT'e

call w1'a(OO,3Bh»)
output (eoi1'_186)
1'l!tu1'n)
end T'xint1'_bJ
p1'Dcedu1'.

1* T'eset ESI

= BOOOh)

*1
*1

T'e5et highest IUS
1* non specific EOl *1

inte1'1'upt 24h)

8000h)

1*
1*

reset highest JUS
non specific EOI

,1
*1

inteT'1'upt 26h)

call WT'b(OO.30h»)
call wT'a(OO,38h)J
output (eoi1'_186)
return)
end ST'c_bJ

reset highest IUS
1* non specific EOI

interrupt 22h)

call WT'b(OO.10h»)
call wT'a(OO.3Bh»)
output (eoiT'_186)
T'e turn)
end l!1Ii_bJ

= BOOOh)

1*
1*

e1'1'or reset

reset highest IUS
1* non specific EOI

*1
*1

1*--------------_·_-----------------------------------------------~----------*I
231262-5

Figure 5. ASYNC Communication In Interrupt Mode

2-432

inter

AP-222

ed on the RxDA pin, it goes from the Hunt to the Sync
mode. It receives the frame and the end of frame interrupt (src_b, vector = 2eh) occurs.

6. Initialization for SOLC
Communication
Channel A of the SCC is programmed for being used
for SDLC operation. It uses the DMA channels on the
80186. Figure 6 shows the initialization procedure for
channel A. The comments in the software show the
effect of each statement. The on-chip Baud Rate Generator is used to generate a clock of 125 kHz both for
reception and transmission. This procedure is just to
prepare the channel A for SDLC operation. The actual
transmission and reception of frames is done using the
procedures described further.

8. SOLC Frame Transmission

7. SOLC Frame Reception
Figure 7 shows the entire set-up necessary to receive a
SDLC frame. First the DMA controller is programmed
with the receive buffer address (@rlL-bufi), byte count,
mode etc and is also enabled. Then a flag indicating
reception of the frame is reset. An Error Reset command is issued to clear up any pending error conditions. The receive interrupt is enabled to occur at the
end of frame reception (Special Receive Condition);
lastly, the receiver is enabled and put in the Hunt mode
(to detect the SDLC flag). When the first flag is detect-

Figure 8 shows the procedure for transmitting a SDLC
frame once channel A is initialized. The DMA controller is initialized with the transmit buffer address
(@tx_buff(l» - note, it is the second byte of the transmit buffer - and the byte count - again one less than the
total buffer length. This is done because the first byte in
the buffer is output directly using an I/O instruction
and not by DMA. Then the flag indicating frame transmitted is reset. The events following are very critical in
sequence:
a. Reset external status interrupts
b. Enable the transmitter
c. Reset transmit CRC
d. Enable transmitter underrun interrupt
e. Enable the DMA controller
f. Output first byte of the transmit block to data port
g. Reset Transmit Underrun Latch

1*--------------------------------------------------------------------------*1
scc_init_a:

procedurel

.cc ch A register initialization for SOLC mode
call
call
call
call
call
call
call
call
call
call
call
call
call

IIIra(09,
IIIra(04,
IIIra(Ol.
IIIra(03.
1111'01(05.
IIIra(06.
IIIra(07.
IIIra( 10.
1111'01 (11.
1111'01(12.
111""1(13.
IIIra(14.
IIIra( 15.

enables

10000000b I I
00 1 OOOOOb II
01100000b I I
11000000b I I
Ol1OOOOOb I I
01010101bll
01111110bll
10000000b) I
01010110bll
000011 lOb ) I
OOOOOOOOb ) I
00000 11 Ob ) I
OOOOOOOOb ) I

1*
1*
1*
1*
1*
1*

channel A reset *1
SOLC mode *1
OMA for Rx *1
8 bit Rx char. Rx disable *1
8 bit Tx char. Tx disable *1
node address *1
(* SOLe flag *1
1* preset eRe. NRZ encoding *1
trxc
BRG
BRG out *1
1* rxc .. txc
1* to generate 125 Kbaud. xl @ 4 mhz *1

1*
1*

BRG source
SYS eLK. OMA for Tx
all ext status interrupts off *1

call IIIra(14.
call IIIra(Ol.
call IIIra(09.

00000111 b I I
111 OOOOOb ) I
00001001 b) I

1*
1*
1*

enable : BRG *1
enable : drell *1
master IE. vector includes status

end lice init_a/

1*--------------------------------------------------------------------------*1
231262-6

Figure 6. Initialization for SOLC Communication

2-433

inter
1

AP-222

*---------------------------------------------- ---------------------------,--* 1

rx_init: procedure,
declare dma_O_mode literally '1010001001000000b';
1* src=IO, dest=M(inc), sync=src. Te, noint, priority,
outwordCdmi!l_O_dpl)
1 owl6 «tr x_b ui'f);
outword(dma_O_dph)
highI6C(trx_buff),
outword(dma_O_spl) = ch_a_data;
outwoTd(dma_O_sph) -= 0;
outword(dma_O_tc)
block_length + 2,
outword (dma,:"O_cw) - droa_O_mode 01' 0006hl

b\lte *1

1* +2 for eRe *1
1* start DMAchannel 0 *1

1* reset frame received flag *1
call wraCOO,30h),
call wraC01. 11111001b);
call wra(03, 11010001b);

1* error reset *1
1* sp. cond intT only, IIxt int IInable *1
1* enable receiver. enter hunt mode *1

1*--------------------------------------------------------------------------*1
231262-7

Figure 7. SDLC-DMA Frame Reception

1*------------------------------------------------------------------------.:.---*1
declare droa_l_mode literally 'OOOI011010000000b',
1* src=M( inc). dest=IO, sllnc=dest, Te, noint. noprior. bllte *1
low16(@tx_buff(I».
highlb(@tx_buff(I»,
ch_a_data.

outword(dma_l_~pl)

outword(dma_l_sphl
outword(dma_l_dpl)
outword(dma_l_dph)
outword(dma_l_tc)

block_length - I.

1* -1 for first bllte *1

1* Teset frame transmittlld flag *1
call
call
call
call

wra(OO, 000I0000b),
wra(05, Ol101011b).
wra(OO, 10101000b),
wTaC15, 01000000b).

1*
1*
1*
1*

reset ESI *1
enable transmitter *1
reset tx eRe, TxINT pending *1
enable
TxU int *1

outword(dma_l_cw) = droa_l_mode Dr OOObh,
1* start DMA channell *1
output(ch_a_data)
tx_buff(O);
1* first bllte - address field *1
call wraCOO, 11000000b).
1* Reset Tx Underrun latch *1

/ *--------------- -----.-----.--- ------------------------------ ------------------* I
231262-8

Figure 8. SDLC-DMA Frame Transmission

2-434

inter

Ap·222

1*--------------------------------------------------------------------------*1
1*

channel A interrupt procedures

txintr _a:

interrupt 28hl

procedure

call wra(OO.38h)l
output (eoir_18o)
returnl
end txintr_al

= 8000hi

call wra(OO.10h)l
tx_stat = rra(O)l
frame_tx = Offhl

= 8000hi

1*
1*
1*

reset ESI *1
read in status *1
set frame· transmitted flag

1*
1*

reset highest IUS *1
non specific EOI *1

1*
1*

reset highest IUS *1
non specific EOI *1

interrupt 2eh;

procedure

rx_stat = rraCt);
call wra(OO.30h)i
call wra(03.1tOOOOOOb);
frame_recd
Offhl

call wra(OO.38h)1
output (eoir_186)
returnl
end src_al

reset highest IUS *1
non specif~c EOI *1'

interrupt 2chl

procedure
call wra(OO.38h)i
output (eoir_186)
returnl
end rxintr_ai

1*
1*

interrupt 2ahi

procedure

call wraCOO.38h);
output (eoir_186)
returni
end esi_al

8000hl

1*
1*
1*

error reset *1
disable rx *1
set frame received flag

1*
1*

reset highest IUS *1
non specific EOI *1

I*-------------------------~------------------------------------------------*1
231262-9

Figure 9. SDLC·DMA Interrupt Routines

2-435

AP-222

The frame gets transmitted out with all bytes, except
the first one, being fetched by the SCC using the DMA
controller. At the end of the block the DMA controller
stops supplying bytes to the SCC. This makes the transmitter underrun. Since the Transmitter Underrun
Latch is in the reset state at this moment, the CRC
bytes are appended by the SCC at the end of the transmit block going out. An Exte11,lal Status Change interrupt (esLa, vector = 2ah) is generated with.the bit for
transmitter underrun set in RRO register. This interrupt occurs when the CRC is being transmitted out and
not when the frame is completely transmitted out.

9. SOLC Interrupt Routines
Figure 9 shows all the interrupt procedures for channel
A when operating in the SDLC mode. The procedures
of significance here are esLa and src_a.
The end of frame reception results in the src_a procedure getting executed. Here the status in register RR 1
is stored in a. variable rx~tat for future examination.
Any error bits set in status are reset, receiver is disabled
and the flag indicating reception of a new frame is set.

examination and the flag indicating transmission of the
frame is set.
End of frame processing is required after both of these
interrupt procedures. It involves looking at
rX--,-stat and tx_stat and checking if the desired operation was successful. The buffers used, may have to be
recovered or new ones obtained to start another frame
transmission or reception.

CONCLUSIONS
This article should ease the process of writing a complete data link driver for ASYNC and SDLC modes
since most of the hardware dependent procedures are
illustrated here. It was a conscious decision to make the
procedures as small and easy to understand as possible.
This had to be done at the expense of making the procedures general and not dealing with various exception
conditions that can occur.

REFERENCES

The esi_a procedure is executed when CRC of the
transmitted frame is just going out of the SCC. Reset
External Status Interrupt command is executed, the external status is stored in a variable tx_stat for future

, 2-436

1. 82530 Data Sheet, Order #230834-001
2. 82530
SCC
Technical, Manual,
#230925-001

Order

inter

AP-222

APPENDIX A
82530-BAUD RATE GENERATORS
The 82530 has two Baud Rate Generators (BRG) on
chip--one for each channel. They are used to provide
the baud rate or serial clock for receive and transmit
operations. This article describes how the BRG can be
programmed and used.

Step 1: Baud Rate Time Constant (BRTC)

The BRTC is determined by a simple formula:
BRTC

The BRG for each channel is totally independent of
each other and have to be programmed separately for
each channel. This article describes how anyone of the
two BRGs can be programmed for operation. To use
the BRG, four steps have to be performed:
1. Determine the Baud Rate Time Constant (BRTC)
to be programmed into registers WR12 (LSB) and
WR13 (MSB).
2. Program in register WRll, to specify where the
output of the BRG must go to.
3. Program the clock source to the BRG in register
WRI4.
4. Enable the BRG.

Serial Clock Frequency
2 X (Baud Rate X Baud Rate Factor)

Example:
For Serial Clock Frequency
Baud Rate
Baud Rate Factor
BRTC

4 MHz

9600
16

4000000
2 X (9600 X 16) - 2

13.021 - 2

11.021

I~I~I~I~I~I~I~I~I

II ~ I!I"" 0"' • ~AC 0'''"'

= TRANSMIT CLOCK

TRxC OUT

TRxC OUT = BR GENERATOR OUTPUT

TRxC OUT

= DPLL OUTPUT

TRxC 0/1

= RTxC PIN
= TRxC PIN
TRANSMIT CLOCK = BR GENERATOR OUTPUT

~....!!.... TRANSMIT CLOCK
~....!... TRANSMIT CLOCK

r.!.....!!....
1

'---

J!.. ~
J!.....!.
....!.- ~
....!.-...!.

TRANSMIT CLOCK

DPLL OUTPUT

RECEIVE CLOCK = RTxCPIN
RECEIVE CLOCK = TRxC PIN
RECEIVE CLOCK = BR GENERATOR OUTPUT
RECEIVE CLOCK

DPLL OUTPUT

RTxC XTAUNO XTAL

Figure 1. Write Register 11

2-437

231262-10

inter

AP-222

Table 1. BRTC - Baud Rate Time Constant
Baud Rate Factor
1

9600
4800
2400
1200
600
300

Baud
Rate

16
11.021
24.042
50.083
102.167
206.333
414.667

206.333
414.667
831.333
1664.667
3331.333
6664.667

32
4.510
11.021
24.042
50.083
102.167
206.333

64
1.255
4.510
11.021
24.042
50.083
102.167

Since only integers can be written into the registers
WRI2/WR13 this will have to be rounded off to II
and it will result in an error of:
fraction
BRTC

-- X

100

0.021
11.021

= -- X

L
Uk§~

100

0.19%

This error indicates that the baud rate signal generated
by the BRG does not provide the exact frequency required by the system. This error is more serious for
smaller baud rate factors. For asynchronous systems,
errors up to 5% are considered acceptable.
Note that for BRTC = 0, BRG output frequency
Serial Clock Freq.

0
0
0

0
1
1
1
1

1/4 x

Table I shows the BRTC for a 4 MHz serial clock with
various baud rates on the Y-axis and baud rate factors
on the X - axis. The constant that is really programmed
into registers WRI2/WR13 is the integer closest to the
BRTC value shown in the table.

NULL COMMAND
ENTER SEARCH MODE
1 0 RESET MISSING CLOCK
1 1 DISABLE DPLL
BR GENERATOR
0 0 SET SOURCE
0 1 SET SOU RCE = RTxC
1 0 SET FM MODE
1 1 SET NRZI MODE
0

231262-11

. Figure. 2. Write Register 14

WR 14/ bit D I

Step 2: BRG Output

The output of the BRG can be directed to the Receiver,
Transmitter and the TRxC output. This is programmed
by setting bits 06 OS, bits 04 03, and bits 01 00 in
register WRII to 10. See Figure 1. The output of the
BRG can also be directed to the Oigital Phase Locked
Loop (OPLL) for the on-chip decoding of the NRZI
encoded received data signal. This is done by writing
100 into bits 07 06 05 of register WRI4 as shown in
Figure 2.

BR GENERATOR ENABLE
BR GENERATOR SOURCE
DTR/REQUEST FUNCTION
AUTO ECHO
LOCAL LOOPBACK

0 ---. Clock comes from pin
RTxC

WRI4/ bit 01 = I ---. Clock comes from System
Clock (PCLK)
On RESET WRI4 / bit 01 = O.

Step 3: BRG Source Clock

It should be noted that for the case of Bit 0 I = 0, the
clock comes either from:
a. Clock on pin RTxC - if WRll / 07 = 0
or b. Crystal on pins RTxC & SYNC
-ifWRll/07 = I

Step 4: BRG Enable

This is the last step where bit 00 ofWRI4 is set to start
the BRG. The BRG can also be disabled by resetting
this bit.

2-438

intJ

AP-222

APPENDIX B
MODEM CONTROL PINS ON THE 82530
bits for CD and/or CTS must also be set in WR15 for
the interrupt to be enabled.

Introduction
This article describes how the CTS and CD pins on the
82530 behave and how to write software to service
these pins. The article explains when the External
Status Interrupt occurs and how and when to issue the
Reset External/Status Interrupt command to reliably
determine the state of these pins.
Bits D3 and D5 of~ister RRO show the inverted state
of logic levels on CD and CTS pins respectively. It is
important to note that the register RRO does not always
reflect the current state of the CD and CTS pins. Whenever a Reset External/Status Interrupt (RESI) command is issued, the (inverted) states of the CD and the
CTS pins get updated and latched into the RRO register
and the register RRO then reflect the inverted state of
the CD and CTS pins at the time of the write operation
to the chip. On channel or chip reset, the inverted state
of CD and CTS pins get latched into RRO register.
Normally, a transition on any of the pins does not necessarily change the corresponding bites) in RRO. In certain situations it does and in some cases it does not. A
sure way of knowing the current state of the pins is to
read the register RRO after a RESI command.
There are two cases:
1. External/Status Interrupt (ESI) enabled.
II. Polling (ESI disabled).
Case I: External Status Interrupt (ESI) Enabled

Whenever ESI is enabled, an interrupt can occur whenever there is a transition on CD or CTS pins - the IE

In this case, the first transition on any of these pins will
cause an interrupt to occur and the corresponding bit in
RRO to change (even without the RESI command). A
RESI command resets the interru.£!.!ine and also latches in the current state of both the CD and the CTS pins.
If there was just one transition the RESI does not really
change the contents of RRO.
If there are more than one transitions, either on the
same pin or one each on both pins or multiple on both
pins, the interrupt would get activated on the first transition and stay active. The bit in RRO corresponding
only to the very first transition is changed. All subsequent transitions have no effect on RRO. The first transition, in effect, freezes all changes in RRO. The first
RESI command, as could be ex~ed, latches the final
(inverted) state of the CD and CTS pins into the RRO
register. Note that all the intermediate transitions on
the pins are lost (because the response to the interrupt
was not fast enough). The interrupt line gets reset for
only a brief moment following the first RESI command. This brief moment is approximately 500 ns for
the 82530. After that the interrupt becomes active
again. A second RESI command is necessary to reset
the interrupt. Two RESI commands resets the interrupt
line independent of the number of transitions occurred.

Whenever operating. with ESI enabled, it is ·recommendable to issue two back-to-back RESI commands
and then read the RRO register to reliably determine
the state of the CD and CTS pins and also to reset the
interrupt line in case multiple transitions may have occurred.

SUBSEQUENT
TRANSITIONS

RESET

231262-12

State Diagram

2-439

inter

AP-222

State 2

.Case II: Polling RRO for CD and CTS Pins

If RRO is polled for determining the state of the CD
and CTS pins, then the ExternaVStatus Interrupt (ESI)
is kept disabled. In this case the bits in RRO may not
change even for the first transition. The best way to
handle this case to always issue a RESI command before reading in the RRO register to determine the state
of CD and CTS pins. Note, however, if two back-toback RESI commands were to be issued every time before reading in the RRO register, the first subsequent
transition will change the corresponding bit in RRO.

Interrupt is active (if enabled). Any further transitions have no effect. A RESI command leads to
state I, temporarily making the interrupt inactive.

CONCLUSIONS
Register RRO does not always reflect the· current (inverted) state of the CD and CTS pins. The most reliable
way to determine the state of the pins in interrupt or
polling mode is to issue two back-to-back RESI commands and then read .RRO .. While polling, the second
RES! is redundant but harmless. When issuing the
back-to-back RESI commands to 82530 note that the
separation between the two write cycles should be at
least 6 CLK + 200 ns; otherwise the second RESI will
be ignored.

The state di~m above illustrates how each transition
on CD and CTS pins affect the 82530 and what effect
the RESI command has.

State 0
It is entered on reset. No ESI due to CTS or CD are
pending in this state. Any transition on CTS or CD
pins lead to the state I accompanied by an immediate change in the RRO register.

State 1
Interrupt is active (if enabled). If a RESI command
is issued, state 0 is reached where interrupt ~ain
inactive. However, a further transition on CTS or
CD pin leads to state 2 without an immediate change
in RRO register.

2-440

inter

AP-222

APPENDIX C
THE 82530 SCC - 80186 INTERFACE AP BRIEF
INTRODUCTION

INTERFACE OVERVIEW

The object of this document is to give the 82530 system
designer an in-depth worst case design analysis of the
typical interface to a 80186 based system. This document has been revised to include the new specifications
for the 6 MHz 82530. The new specifications yield better margins and a 1 wait state interface to the CPU (2
wait states are required for DMA cycles). These new
specifications will appear in the 1987 data sheet and
advanced specification information can be obtained
from your local Intel sales office. The following analysis includes a discussion of how the interface TTL is
utilized to meet the timing requirements of the 80186
and the 82530. In addition, several optional interface
configurations are also considered.

The 82530 - 80186 interface requires the TTL circuitry
illustrated in Figure 1. Using five 14 pin TTL packages,
74LS74, 74AS74, 74AS08, 74AS04, and 74LS32, the
following operational modes are supported:
•
•
•
•
•

Polled
Interrupt in vectored mode
Interrupt in non-vectored mode
Half-duplex DMA on both channels
Full-duplex DMA on channel A

A brief description of the interface functional requirements during the five possible BUS operations follows
below.

DATA (D7-Il8)

II2S3II
D1
D.
00
04
OS
D2

4
11
31
3
38 DB"
2
••
39 12

T)cDA

••I.

R)cDA

. ..
.."
s.
SO
34

!VIm[

I!fIA
l!nli

0
0
.0

.... REO'A
,IRES.

so
H

lEI

lEO

OND

NOTES:

H -

Ul -

DRa1

INTa

IXDB
R)CDB

="fH

'!1Il!n
l!!l!fY
19m'J
it'l'n

.,
20
21
2.
28
2.
2S
22
2.
24

HIrnIG'I
vee

l!llli

lI'l'II7IINA

:~ D"'~

.4
.2
II

••

•

~EL

•• v

PULLED HIGH THROUGH &iK OHI1

704LS?4

U2 - 14A588

.274Ase4

~'.L-

______________________-'

U3 U4 -

us -

7<4ASe ..
704A574
74LS32

vs
'74ASe4
DRQa

r'~'------------------------~

231262-18

Figure 1. 82530-80186 Interface

2-441

IJHeI

AP-222

UNITS:

125NS/18

CLKOUT
AD ......
DUR
ALE

88186

i!E'R'
~

1m
82588

_'I"

DATA

I);IItA Oi§LUi ~::::::::::::::::

231262-19

Figure 2. 80186-82530 Interface Read Cycle

UNITS:

125 HS/18

CLKOUT
AD .....
DTIR
88186

ALE

iM
-m:i
JSeS

ADDRESS
82588
DATA

cl,ll:=II~'

==~::::::><

.::

.. .

><===

.:
: :~
..:
::::::::::::::::.:I:::<:::::::::::::::!:::::::?::::::::::t::::::::::::::::::::::::::::::::rtr::~:.-.:-::-::-:~-::-::-:-::-::-::-::-:'-.:-::
231262-20

Figure 3; 80186-82530 Interface Write Cycle

READ CYCLE: The 80186 read cycle requirements are
met without any additional logic, Figure 2. At least one
wait state is required to meet the 82530 tAD access
time.

is inverted to assure that WR is active low before the D
Flip·Flop is clocked. No wait states are necessary to
meet the 8253(),s WR cycle requirements, but one is
assumed from the RD cycle.

WRITE CYCLE:.The 82530 requires that data must be
valid while the WR pulse is 10w,B&ure 3. A D Flip·
Flop delays the leading edge of WR until the falling
edge of CLOCKOUT· when data is (guaranteed valid
and WR.is guaranteed active. The CLOCKOUT signal

INTA CYCLE: During an interrupt acknowledge cy·
cle, the 80186 provides two INTA pulses, on:e per bus
cycle, separated by two idle states. The 82530 expects
.only one long INTA ~e with a RD pulse occurring ,
only after the 82530 lEI/lEO daisy chain settles. As

2·442

intJ

AP-222

UNITS:

125 HSt'12

CLKOUT
AD .-:1.5

80186

DTI~

TRYFi
DEii

~i;,<~!C~;.:~<'~~~n~l~

·············1···································1···· ...................................................... ·1···················
·············1···································1···· ...................................................... ·1···················

CLK

TRYFi
82590

e
VECTOR

~ ....... I··~··········~I··;········ ..+·····················~·······I··+ ..........'£.:.:
1
•
I······r~
1

:-.··-::-::-·:-::-:.+i-::-.it··~:'i;r'£ ..:~~2l~
.

1
.

231262-21

Figure 4. 82530-801861NTA Cycle

illustrated in Figure 4, the INTA signal is sampled on
the rising edge of CLK (82530). Two D Flip·Flops and
two TTL gates, U2 and U5, are implemented to gener·
ate the proper INTA and RD pulses. Also, the INT
signal is passively pulled high, through a I k resistor,
and inverted through U3 to meet the 80186's active
high requirement.
DMA CYCLE: Conveniently, the 80186 DMA cycle
timings are the same as generic read and write operations. Therefore, with two wait states, only two modifications to the DMA request signals are necessary.
First, the RDYREQA signal is inverted through U3
similar to the INT signal, and second the DTR/REQA
signal is conditioned through a D Flip-Flop to prevent
inadvertent back to back DMA cycles. Because the
82530 DTRlREQA signal remains active low for over
five CLK (82530)'s, an additional DMA cycle could
occur. This uncertain condition is corrected when U4
resets the DTR/REQ signal inactive high. Full Duplex
on both DMA channels can easily be supported with
one extra D Flip-Flop and an inverter.
RESET: The 82530 does not have a dedicated RESET
input. Instead, the simultaneous assertion of both RD
and WR causes a hardware reset. This hardware reset
is implemented through U2, U3, and U4.

need not be as extensive as the typical interface used in
this analysis. Two alternative configurations are discussed below.
8288 BUS CONTROLLER: An 80186 based system
implementing an 8288 bus controller will not require
the preconditioning of the WR signal through theD
Flip-Flop U4. When utilizing an 8288, the control signal IOWC does not go active until data is valid, therefore, meeting the timing requirements of the 8Z5~G. In
such a configuration, it will be necessary to logically
OR the IOWC with reset to accommodate a hardware
reset operation.
NON-VECfORED INTERRUPTS: If the 82530 is to
be operated in the non-vectored interrupt mode (B step
only), the interface will not require UI or U5. Instead,
INTA on the 82530 should be pulled high, arid pin 3 of
U2 (RD AND RESET) should be fed directly into the
RD input of the SCC.
Obviously, the amount of required interface logic is application dependent and in many cases can be considerably less than required by the typical configuration,
supporting all modes of SCC operation.

DESIGN ANALYSIS
ALTERNATIVE INTERFACE
CONFIGURATIONS
Due to its wide range of applications, the 82530 interface can have many varying configurations. In most of
these applications the supported modes of operation

This design analysis is for ·a typical microprocessor system, pictured in Figure 5. The Timing analysis assumes
an 8 MHz 80186 and a 6 MHz 82530 being clocked at
4 MHz. The 4 MHz clock is' the 80186 CLKOUT divided by two by a flip-flop (U6). Also, included in the
analysis are bus loading, and TTL-MOS compatibility
considerations.

2-443

Intel

AP-222

ADDRESS
LATCH

r--

MICROPROCESSOR

;

ADDRESS BUS

"-:t""
ALE

r--

CONTRO~

"<.,7

r---- -

)

'<:

'--

ROM

RAM

I/O

r-'---

[;t

DATA BUS

f\J
.......

DATA
TRANSCEIVER

231262-22

Figure 5. Typical Mlcroprocesso,r System

TIMING ANALYSIS

Bus Loading and Voltage Level
Compatabilities
The data and address lines do not exceed the drive capability of either 80186 or the 82530. There are several
control lines that drive more than one TTL equivalent
input. The drive capability of these lines are. detailed
below.
WR: The WR signal drives U3 and U4.
• 101 (2.0 mAl > iii (-0.4 mA + -0.5 mAl
loh ( - 400 /LA) > lih (20 /LA + 20 /LA)

PCS5: The PCS5 signal drives U2 and U4.
• 101 (2.0 mAl > Iii (-0.5 mA + -0.5 mAl
loh (-400 /LA) > lih (20 /LA + 20/LA)

Certain symbolic conventions are adhered to throughout the analysis below and are introduced for clarity.
L All timing variables with a lower case first letter are
82530 timing requirements or responses (i.e., tRR):
2. All timing variables with Upper case first letters are
80186 timing responses or requirements unless preceded by another device's alpha-numeric code (i.e.,
Tclcl or '373 Tpd).
3. In the write cycle analysis, the timing variable
TpdWR186-WR530 represents the propagation delay between the leading or traili~dge of the WR
signal leaving the 80186 and the WR edge arrival at
the 82530 WR input.

Read Cycle

INTA: The INTA signal drives 2(Ul) and U5.
• 101 (2.0 mAl > Iii (-0.4 mA + -0.8 mA + -0.4 mAl
loh ( - 400 /LA) > lih (20 /LA + 40 /LA + 20 /LA)

All the 82530 I/O pins are TTL voltage level compatible.

L tAR: Address valid to RD active set up time for the
82530. Since the propagation delay is the worst case
path in the assumed typical system, the margin is calculated only for a propagation delay constrained and not
an ALE limited path. The spec value is 0 ns minimum.
• 1 Tclcl - Tclav(max) - '245 Tpd(max)
2(U2) Tpd(min) - tAR (min)

=
2-444

125 - 55 - 20.8

2(2) - 0

Tclrl(min)

63.2 ns margin

inter

AP-222

2. tRA: Address to RD inactive hold time. The ALE
delay is the worst case path and the 82530 requires 0 ns
minimum.
• 1 Tclcl - Tclrh (max) + Tchlh(min)
Tpd(min) - 2(U2) Tpd(max)
= 55 - 55

'373 LE

3. tCLR: CS active low to RD active low set up time.
The 82530 spec value is 0 ns minimum.

2 = 50 ns margin

= 35 - 1 - 5.5 = 28.5 ns margin
5. tCHR: CS inactive to RD active set up time. The
82530 requires 5 ns minimum.
• 1 Tclcl + 1 Tchcl - Tchcsx(max) + Tclrl(min) - U2
skew (RD - CS) + U2 Tpd(min) - tCHR

55 - 35 - 10 - 1

6. tRR: RD pulse active low time. One 80186 wait state
is included tO,meet the 150 ns minimum timing requirements of the 82530.
Trlrh(min)

1(Tclclwait state) - 2(U2 skew).- tRR

(250~50)

1(125) - 2(1) - 150 = 173 ns margin

= 125 - 55 - 5 - 20.8
= 170.6 ns margin

[125 - 5
'

4.41 - 0

2. tWA: WR inactive to address invalid hold time. The
82530 spec is 0 ns.
• Tclch(min) - Tcvctx(max) + Tchlh(min) + '373 LE
Tpd(min) - TpdWR186=WR530(HIGH) [U2 Tpd(max) +
U3 Tpd(max) + U4 Tpd(max)l
= 55 - 55
margin

8 - [5.5

+ 7.11

= -2.6 ns

3. tCLW: Chip select active low to WR active low hold
time. The 82530 spec is 0 ns.

2 - 5 = 131 ns margin

•

1. tAW: Address required valid to WR active low set
up time. The 82530 spec is 0 ns minimum.
Tclcl - Tclav(max) - Tcvctv(min) - '373 Tpd(max)
TpdWR186 - WR530(LOW) [Tclcl - Tcvctv(min) +
U3 Tpd(min) + U4 Tpd(min)l - tAW

Tcscsx(min) - U2 skew(RD - CS) - U2 Tpd(max)

= 125

125 - 55 - 20.8 -14.2 -'20 -325 = 65 ns

4. tRCS: RD inactive to CS inactive hold time. The
82530 spec calls for 0 ns minimum.
•

•

• 1 Tclcl - Tclcsv(max) - Tclrl(min) - U2
skew(RD - CS) + U2 Tpd(min)

= 375
margin

Write Cycle

8 - 2(5.5) = 2 ns margin

= 125 - 66 - 10 - 1

• 3 Tclcl + 1 (Tclclwait state) - Tclav(max) - '373
Tpd(max) - '245 Tpd - Tdvcl(min) - tAD

1 Tclcl - Tclcsv(max) + Tcvctv(min) - U2 Tpd(max)
TpdWR186=WR530(LOW) [Tclcl - Tcvctv(min) + U3
Tpd(min) + U4 Tpd(min)1
•

= 125 - 66 + 5 - 5.5
183.9 ns margin

7. tRDV: RD active low to data valid maximum delay
for 80186 read data set up time (Tdvcl =.20 ns). The
margin is calculated on the Propagation delay path
(worst case).
• 2 Tclcl + 1 (Tclclwait state) - Tclrl(max) - Tdvcl(min)
- '245 Tpd(max) - 82530 tRDV(max) - 2(U2) Tpd(max)

[125 - 5

4.41 =

4. tWCS: WR invalid to Chip Seloct invalid hold time.
'
82530 spec is 0 ns.
• Tcxcsx(min) - U2 Tpd(max) TpdWR186=WR530(HIGH) [U2 Tpd(max)
Tpd(max) + U4 Tpd(max)l
'
= 35

1.5 - [5.5

7.11 = 20.9 nsmargin

5. tCHW: Chip Select inactive high to WR active low
set up time. The 82530 spec is 5 ns.

= 2(125) + 1(125) - 70 -20 - 14.2 - 105 - 2(5.5)
= 154 ns margin

margin is calculated to DEN active low of next cycle.

• 1 Tclcl + Tchcl(min) + Tcvctv(min) - Tchcsx(max) U2 Tpd(max) + TpdWR186=WR530(LOW) [Tclcl Tcvctv(min) + U3 Tpd(min) + U4 Tpd(min)l - tCHW

• 2 Tclcl + Tclch(min) - Tclrh(max)
2(U2) Tpd(max) - 82530 tDF(max)

= 125 + 55 + 5 - 35 - 5.5
5 = 264 ns margin

8. tDF: RD inactive to data output float delay. The

= 250

55 -55

Tchctv(min) -

10 - 11 - 70 = 179 ns margin

9. tAD: Address required valid to read data valid maximum delay. The 82530 spec value is 325 ns maximum.

[125 -5

4.41 -

6. tww: WR active low pulse. 82530 requires a minimum of 60 ns from the falling to the rising edge of WR.
This includes one wait state.

2-445

inter

AP-222

* Twlwh [2Tclcl - 40] + 1 (Tclclwait state) - TpdWRI
186-WR530(lDW) [Tclcl - Tcvctv(min) + U3 Tpd(max)
+ U4 Tpd(max)] + TpdWR/186=WR/530(HIGH) [U2
Tpd(min) U3 Tpd(mih) + U4 Tpd(min)] - tWW

should never exist. 82530 drivers should insure that at
least one CPV cycle separates INTA and WR or RD
cycles.

= 210 + 1(125) - [125 - 5 + 4.5 + 9.2] - [1.5 + 1
+ 3.2] - 60 = 135.6 ns margin

4. tWI: WR inactive high to INTA active low minimum hold time. The spec is 0 ns and the margin a:ssumes CLK coincident with INTA.

7. tDW: Data valid to WR active low setup time. The
82530 spec requires 0 ns.

• Tclcl - Tcvctx(max) - TpdWR186 - WR530(HIGI-I)
[U3Tpd(max) + U4 Tpd(max)] + Tcvctv(min) + Ul
Tpd(min)

* Tcvctv(min) - Tcldv(max) - '245 Tpd(max) +
TpdWR186-WR530(lDW) [Tclcl - Tcvctv(min) + U3
Tpd(min) + U4 Tpd(min)]

= 125 - 55 - [5.5 + 3 + 7.1] + 5 + 10 = 69.4 ns
margin

= 5 - 44 - 14.2 + 125 - 5 + 1.0 + 4.4 = 72.2 ns
margin
8. tWD: Data valid to WR inactive high hold time. The
82530 requires a hold time of 0 ns.

5. tlR: INTA inactive high to RD active low minimum
setup time. This spec pertains only to 82530 RD cycles
and has a value of 55 ns. The margin is calculated in
the same manner as tIW.

* Tclch - skew (Tcvctx(max) + Tcvctx(min)l + '245
DE Tpd(min) - TpdWR186-WR530(HIGH) [U2 Tpd(max)
+ U3 Tpd(max) + U4 Tpd(max)]

6. tRI: RD inactive high to INTA active low minimum
hold time. The spec is 0 ns and the margin assumes
CLK coincident with INTA.

= 55 - 5 + 11.25 - [5.5 + 3.0 + 7.11 = -50.6 ns
margin

•

Tclcl - Tclrh(max) - 2 U2 Tpd(max) + Tcvctv(min)

+ Ul Tpd(min)

= 125 - 55- 2(5.5) + 5 + 10 = 74 ns margin

INTACycle:

7. tlID: INTA active low to RD active low minimum
setup time. This parameter is system dependent. For
any SCC [n the daisy chain, tlID must be greater than
the sum of tCEQ for the highest priority device in the
daisy chain, tEl for this particular SCC, and tEIBO for
each device separating them in the daisy chain. The
typical system with only 'I SCC requires t1ID to be
greater than. tCEQ. Since tEl occurs coincidently with
tCEQ and it is smaller it can be neglected. Additionally, tEIEO does not have any relevance to a system with
only one SCC. Therefore tllD > tCEQ = 250 ns.

. 1. tiC: This 82530 spec implies that the INTA signal is
latched. internally on the rising edge of CLK (82530).
Therefore the maximum delay between the 80186 asserting INTA active low or inactive high and the 82530
internally recognizing the new state of INTA is the
propagation delay through VI plus the 82530 CLK pe.
riod.

* Ul Tpd(max) + 82530 ClK period
= 45 + 250 = 295 ns
2. tCI: rising edge of CLK to INTA hold time. This
spec requires that the state of INTA remains constant
for lOOns after the rising edge of CLK. If this spec is
violated any change in the state of INTA may not be
internally latched in the 82530. tCI becomes critical at
the end of an INTA cycle when INTA goes inactive.
When calculating margins with tCI, an extra 82530
CLK period must be added to the INTA inactive delay.
3. tlW: INTA inactive high to WR active low minimum setup time. The spec pertains only to 82530 WR
cycle and has a value of 55 ns. The margin is calculated
assuming an 82530 WRcycle occurs immediately after
an INTA cycle. Since the CPV cycles following an
82530 INTA cycle are devoted to locating and executing the proper interrupt service routine, this condition

• 4 Tclcl + 2 Tidle states - Tcvctv(max) - tiC [Ul
Tpd(max) + 82530 ClK period] + Tcvctv(min) + U5
Tpd(min) + U2 Tpd(min) - tliD
= 500 + 250 - 70 - [45 + 250] + 5 + 6 + 2 - 250
= 148 ns margin
8. tlDV: RD active low to interrupt vector valid delay.
The 80186 expects the interrupt vector to be valid on
the data bus a minimum of 20 ns before T4 of the second acknowledge cycle (Tdvcl). tIDV spec is 100 ns
maximum.
• 3 Tclcl ~ Tcvctv(max) - U5 Tpd(max) - U2
Tpd(max) - tIDV(max) - '245 Tpd(max) - Tdvcl(min)
= 375 - 70 - 25 - 5.5 - 100 - 14.2 - 20 = 140.3
ns margin

2-446

AP-222

9. tIl: RD pulse low time. The 82530 requires a minimum of 125 ns.

* Tclcl + 2(Tclclwait state) - Tcvctv(min) TpdWR186-WR530(LOW) [Tcici - Tcvctv(min) + U3
Tpd(max) + U4 Tpd(max)] - Tdrqcl - tWRI

* 3 Tclcl - Tcvctv(max) - U5 Tpd(max) - U2
Tpd(max) + Tcvctx(min) + U5 Tpd(min) + U2 Tpd(min)
- tll(min)

=375 - 5 - [125 - 5 + 4.5 + 9.21 - 25 - 200 =
11.3 ns margin
NOTE:
If one wait state DMA interface is required, external
logic, like that used on the DTRREQ signal, can be
used to force the 82530 REQ signal inactive.
.

= 375 - 70 - 25 - 5.5 + 5 + 6 + 1.5 - 125 =
162 ns margin

DMACycle
Fortunately, the 80186 DMA controller emulates CPU
read and write cycle operation during DMA transfers.
The DMA transfer timings are satisfied using the above
analysis. Because of the 80186 DMA request input requirements, two wait states are necessary to prevent
inadvertent DMA cycles. There are also CPUDMA intracycle timing considerations that neeo to be addressed.

1. tDRD: RD inactive high to DTRREQ (REQUEST)
inactive high delay. Unlike the READYREQ signal,
DTRREQ does not immediately go inactive after the
requested DMA transfer begins. Instead, the DTRREQ
remains active for a maximum of 5 tCY + 300 ns. This
delayed request pulse could· trigger a second DMA
transfer. To avoid this undesirable condition, a D Flip
Flop is implemented to reset the DTRREQ signal inactive low following the initiation of the requested DMA
transfer. To determine if back to back DMA transfers
are required in a source synchronized configuration,
the 80186 DMA controller samples the service request
line 25 ns before Tl of the deposit cycle, the second
cycle of the transfer.
*

4. tREC: CLK recovery time. Due to the internal data
path, a recovery period is required between SCC bus
transactions to resolve metastable conditions internal to
the SCC. The DMA request lines are masked from requesting service until after the tREC has elapsed. In
addition, the CPU should not be allowed to violate this
recovery period when interleaving DMA transfers and
CPU bus cycles. Software drivers or external logic
should orchestrate the CPU and DMA controller operation to prevent tREC violation. In this example circuit, tREC could be improved by clocking the '530 with
a 6 MHz clock.

Reset Operation
During hardware reset, the system RESET signal is asserted high for a minimum of four 80186 clock cycles
(1000 ns). The 82530 requires WR and RD to be simultaneously asserted low for a minimum of 250 ns.
• 4 Tclcl - U3 Tpd(max) - 2(U2) Tpd(max) + U4
Tpd(min) - tREe
= 1000 - 17.5 - 2(5.5) + 3.5 - 250 ns = 725 ns
margin

4 Tclcl - Tclcsv(max) - U4Tpd(max) - Tdrqcl(min)

= 500 - 66 - 10.5 - 25 = 398.5 ns margin

82530 VALID ACCESS LOGIC

2. tRRI: 82530 RD active low to REQ inactive high
delay. Assuming source synchronized DMA transfer,
the 80186 requires only one wait state to meet the tRRI
spec of 200 ns. Two are included for consistency with
tWRI.

Due to the unique internal data path of the 82530, an
intra-access recovery time must be provided to settle
any internal metastable conditions. This internal metastble condition gives rise to the Clock Recovery
{tREC] specification required by the 82530. This tREC
is measured from the rising edge of a RD or WR to the
falling edge of the next RD or WR intended for the
82530, and equates to 6 CLK's + 130 ns. Effectively,
this specification implies that the system must provide
1130 ns (6 MHz 82530) between every CPU or other
DMA access to the 82530. (Figure 1.)

* 2 Tclcl + 2(Tclclwait state) - Tclrl(max) - 2(U2)
Tpd(max) - Tdrqcl - tRRI

=2(125)+ 2(125) - 70 - 2(5.5) - 200 = 219 ns
margin
3. tWRI: 82530 WR active low to REQ inactive high
delay. Assuming destination synchronized DMA transfers, the 80186 needs two wait states to meet the tWRI
spec. This is because the 80186 DMA controller samples requests two clocks before the end of the deposit
cycle. This leaves only 1 Tclcl + n(wait states) minus
WR active delay for the 82530 to inactivate its REQ
signal.
.

Systems that only allow CPU access to the 82530 are
not significantly impacted by this clock recovery time.
In CPU access only designs, the software designer can
insert NOP's to guarantee the tREC idle time in between successive CPU RD or WR cycles to the 82530.
Unfortunately, systems that contain more than one direct memory access device, interfacing with the 82530,
will require external hardware to arbitrate 82530 accesses and thereby guaranteeing the tREC restriction.

2-447

inter

AP-222

82530

!or--1

\ _

Non 82530 Bus Cycle

'-L

~f-o.e---- 82530 Clock Recovery nm.----I~

231262-23

Figure 6

The TTL logic pictured in Figure 7 implements the
state machine with some assorted gates, a flip-flop, and
. a shift register. PCS from the 80186 should be qualified
with RD + WR to eliminate switching glitches during
Tl. The 'LS74 and 'LSOO perform rising edge detection
to reset the shift register. The shift register clocks out
the tREC period to enable CS and the additional 2
CLK's 182530} to satisfy the 82530 3 wait state requirement. The 80186 should be programmed to use
theintemal wait state generator (3 wait states for the
82530 and an 8 MHz 80186) and the external READY
signal.

EXTERNAL VALID ACCESS
HARDWARE
To aCcommodate this clock recovery specification, external hardware has been designed for the 82530 systems containing. several DMA devices accessing the
82530 (ie., a CPU and a DMA controller). This logic
has been tailored for an 80186 ·enviroriment but can
easily be modified to fit 8086 or 80286 systems.

LOGIC STATE MACHINE
There are two basic f!lnctions that need to be performed by the external logic. The 'first is to mask the CS
signal from reaching the 82530 until the tREC intra-access idle time has elapsed. The second task is to generate a not ready condition to the CPU or DMA device
until the tREC period has expired and the minimum
wait state requirement for the particular access has
been satisfied. The simple state machine, Figure 7, illustrates the required operation.

Note of caution: This hardware logic has not been verified on a bread board in an actual system. The hardware designer should verify that this logic fulfills his
particular system timing requirements.

+5V

74LS74

ucs
U3

eLK

7404

AROY

231262-24

Figure 7
2-448

Other Components

8291A
GPIB TALKER/LISTENER
Designed to Interface Microprocessors
MHz Clock Range
• (e.g.,
• 1-8
8048/49, 8051,
16 Registers (8 Read, 8 Write), 2 for
• Data Transfer, the Rest for Interface
to an IEEE Standard 488 Digital
Interface Bus
Function Control, Status, etc.
Programmable Data Transfer Rate
Directly Interfaces to External Non• Complete Source and Acceptor
•
Inverting Tranceivers for Connection to
• Handshake
the GPIB
Talker and Listener
Provides Three Addressing Modes,
• Complete
• Allowing
Functions with Extended Addressing
the Chip to be Addressed
Either
as
a Major or a Minor Talker/
Service Request, Parallel Poll, Device
• Clear,
Listener with Primary or Secondary
Device Trigger, Remote/Local
Addressing
Functions
Handshake Provision Allows for
Selectable Interrupts
• DMA
• On-Chip
Bus Transfers without CPU Intervention
Primary and Secondary
Output Pin
Address Recognition
• Trigger
EOS (End of Sequence)
Handling of Addressing and
• On-Chip
• Automatic
Message Recognition Facilitates
Handshake Protocol
Handling of Multi-Byte Transfers
8080/85, 8086/88)

iiiII

IiiII Provision for Software Implementation

of Additional Features
The 8291A is an enhanced version of the 8291 GPIB Talker/Listener designed to interface microprocessors to
an IEEE Standard 488 Instrumentation Interface Bus. It implements all of the Standard's interface functions
except for the controller. The controller function can be added with the 8292 GPIB Controller, and the 8293
GPIB Transceiver performs the electrical interface for Talker/Listener and Talker/Listener/Controller configurations.

18291A

I
I
I

8291A

GPIBDATA

INTERFACE
FUNCTIONS

I/.!::==:::,,-

GP.s CONTROL

TO NON·INVERTING
BUS TRANSCEIVERS

TE
LE
SR

RL
pp

T/RCONTAOL

205246-1

Figure 1. Block Diagram
205246-2

Figure 2. Pin Configuration

3-1

November 1986
Order Number: 205248-002

intJ

8291A

to a listener role or vice-versa during a holdoff,
the "Holdoff on Source Handshake" has been
eliminated. Only "Holdoff on Acceptor Hand-·
shake" is available.
8. The rsv local message is cleared automatically
upon exit from SPAS if (APRS:STRS:SPAS) occurred. The automatic resetting of the bit after the
serial poll is complete simplifies the service request software.
9. The SPASC interrupt on the 8291 has been replaced by the SPC (Serial Poll Complete) interrupt
on the 8291A. SPC interrupt is set on exit from
SPAS if APRS:STRS:SPAS occurred, indicating
that the controller has read the bus status byte
after the 8291A requested service. The SPASC
interrupt was ambiguous because a controller
could enter SPAS and exit SPAS generating two
SPASC interrupts without reading the serial poll
status byte. The SPC interrupt also simplifies the
CPU's software by eliminating the interrupt when
the serial poll is half way done.
10. The rtl Auxiliary Command in the 8291 has been
replaced by Set and Clear rtl Commands in the
8291 A. Using the new commands, the CPU has
the flexibility to extend the length of local mode
or leave it as a short pulse as in the 8291.
11. A holdoff RFD on GET, SDC, and DCl feature
has been added to prevent additional bus activity while the CPU is responding to any of these
commands. The feature is enabled by a new bit
(B4) in the Auxiliary Register B.
12. On the 8291, BO could cease to occur upon IFC
going false if IFC occurred asynchronously. On
the 8291A, BO continues to occur after IFC has
gone false even if it arrived asynchronously.
13. User's software can distinguish between the
8291 and the 8291 A as follows:
a) pon (OOH to register 5)
b) RESET (02H to register 5)
c) Read Interrupt Status 1 Register. If BO interrupt is set, the device is the 8291. If BO is
clear, it is the 8291A.
This can be used to set a flag in the user's software which will permit special routines to be executed for each device. It could be included as
part of a normal initialization procedure as the
first step after a chip reset.

8291A FEATURES AND
IMPROVEMENTS
The 8291A is an improved design of the 8291 GPIB
Talker/Listener. Most of the functions are identical
to the 8291, and the pin configuration is unchanged.
The 8291A offers the following improvements to the
8291:
.
1. EOI is active with the data as a ninth data bit rather than as a control bit. This is to comply with
some additions to the 1975 IEEE-488 Standard
incorporated in the 1978 Standard.
2. The BO interrupt is not asserted until RFD is true.
If the Controller asserts ATN synchronously, the
data is guaranteed to be transmitted. If the Controller asserts ATN asynchronously, the SH
(Source Handshake) will return to SIDS (Source
Idle State), and the output data will be cleared.
Then, if ATN is released while the 8291A is addressed to talk, a new BO interrupt will be generated. This change fixes 8291 problems which
caused data to be lost or repeated and a problem
with the RQS bit (sometimes cannot be asserted
while talking).
3. llOC and REMC interrupts are setting flipflops
rather than toggling flipflops in the interrupt backup register. This ensures that the CPU knows that
these state changes have occurred. The actual
state can be determined by checking the llO and
REM status bits in the upper nibble of the Interrupt Status 2 Register.
4. DREQ is cleared by DACK (RD + WR). DREQ on
the 8291 was cleared only by DACK which is not
compatible with the 8089 I/O Processor.
5. The INT bit in Interrupt Status 2 Register is duplicated in bit 7 of the Address 0 Register. If software polling is used to check for an interrupt, INT
in the Address 0 Register should be polled rather
than the Interrupt Status 2 Register. This ensures
that no interrupts are lost due to asynchronous
status reads and interrupts.
6. The 8291 A's Send EOI Auxiliary Command works
on any byte including the first byte of a message.
The 8291 did not assert EOI after this command
for a one byte message nor on two consecutive
bytes.
7. To avoid confusion between holdoff on DAV versus RFD if a device is readdressed from a talker

3-2

intJ

8291A

Table 1. Pin Description
Pin
No.

Type

00-0 7

12-19

110

DATA BUS PORT: To be connected to microprocessor data
bus.

RSO-RS2

21-23

REGISTER SELECT: Inputs, to be connected to three
non multiplexed microprocessor address bus lines. Select
which of the 8 internal read (write) ~isters will be read from
(written into) with the execution of RO (WR).

CHIP SELECT: When low, enables reading from or writing into
the register selected by RSO-RS2.

READ STROBE: When low with CS or OACK low, selected
register contents are read.

WRITE STROBE: When low with CS or OACK low, data is
written into the selected register.

INT (I NT)

INTERRUPT REQUEST: To the microprocessor, set high for
request and cleared when the appropriate register is
accessed by the CPU. May be software configured to be
active low.

OREQ

DMA REQUEST: Normally low, set high to indicate byte
output or byte input in OMA mode; reset by OACK.

OACK

DMA ACKNOWLEDGE: When low, resets OREQ and selects
data inl data out register for OMA data transfer (actual transfer
done by RO/WR pulse).
Must be high if OMA is not used.

TRIG

TRIGGER OUTPUT: Normally low; generates a triggering
pulse with 1 /Lsec min. width in response to the GET bus
command or Trigger auxiliary command.

CLOCK

EXTERNAL CLOCK: Input, used only for T, delay generator.
May be any speed in 1-8 MHz range.

RESET

RESET INPUT: When high, forces the device into an "idle"
(initialization) mode. The device will remain at "idle" until
released by the microprocessor, with the "Immediate Execute
pon" local message.

28-35

1/0

8-BIT GPIB DATA PORT: Used for bidirectional data byte
transfer between 8291A and GPIB via non-inverting external
line transceivers.

OAV

1/0

DATA VALID: GPIB handshake control line. Indicates the
availability and validity of information on the 0101- 0108 and
EOllines.

NRFO

1/0

NOT READY FOR DATA: GPIB handshake control line.
Indicates the condition of readiness of device(s) connected to
the bus to accept data.

NOAC

1/0

NOT DATA ACCEPTED: GPIB handshake control line.
Indicates the condition of acceptance of data by the device(s)
connected to the bus.

ATN

ATTENTION: GPIB command line. Specifies how data on 010
lines are to be interpreted.

Symbol

0101-0108

Name and Function

3·3

•

Intel

8291A

Table 1. Pin Description (Continued)
Symbol

Pin
No.

Type

IFC

INTERFACE CLEAR: GPIB command line. Places the
interface functions in a known quiescent state.

SRQ

SERVICE REQUEST: GPIB command line. Indicates the need
for attention and requests an int~rruption of the current
sequence of events on the GPIB.

REN

REMOTE ENABLE: GPIB command line. Selects (in
conjunction with other messages) remote orlocal control of
the device.

EOI

I/O

END OR IDENTITY: GPIB command line. Indicates the end of
a multiple byte transfer sequence or, in conjunction with ATN,
addresses.the device during a polling sequence.

T/R1

EXTERNAL TRANSCEIVERS CONTROL LINE: Set high to
indicate output data/signals on the D101-D108 and DAV lines
and input signals on the NRFD and NDAC lines (active source
handshake). Set low to indicate input data/signals on the
D101-D108 and DAV lines and output signals on the NRFD
and NDAC.lines (active acceptor handshake).

T/R2

EXTERNAL TRANSCEIVERS CONTROL LINE: Set to
indicate output signals on the EOlline. Set low to indicate
expected input signal on the EOI line during par~lIel poll.

Name and Function

Vee

P.S.

POSITIVE POWER SUPPLY: (5V

GND

P.S.

CIRCUIT GROUND POTENTIAL.

± 10%).

NOTE:

All signals on the 8291A pins are specified with positive logic. However, IEEE 488 specifies negative logic on its 16 Signal
lines. Thus, the data is inverted once from Do-D7 to DIOo-DI08 and non· inverting bus transceivers should be used.

r - I
I

- - ..

_ _......:l"'-_....... T/R2

DREO

.-------1

DMA
CONTROLLER. I
(OPTIONAL)
J--_ _D_A_C_K_--...

L _____ .J

8291A
GPIB
INTERFACE

J---------,
T/R1

L..-_~-....

NON· INVERTING
BUS
TRANSCEIVERS

205248-3

Figure 3. 8291A System Diagram
3-4

intJ

8291A

send status. An 8291A implementation of the GPIB
offers the user three alternative addressing modes
for which the device can be initialized for each application. The first of these modes allows for the device to have two separate primary addresses. The
second mode allows the user to implement a single
talker/listener with a two byte address (primary address + secondary address). The third mode again
allows for two distinct addresses but in this instance,
they can each have a ten-bit address (5 low-order
bits of each of two bytes). However, this mode requires that the secondary addresses be passed to
the microprocessor for verification. These three addressing schemes are described in more detail in
the discussion of the Address Registers.

THE GENERAL PURPOSE INTERFACE
BUS (GPIB)
The General Purpose Interface Bus (GPIB) is defined in the IEEE Standard 488-1978 "Digital Interface for Programmable Instrumentation." Although a
knowledge of this standard is assumed, Figure 4
provides the bus structure for quick reference. Also,
Tables 2 and 3 reference the interface state mnemonics and the interface messages respectively.
Modified state diagrams for the 8291A are presented in Appendix A.

General Description
The 8291 A is a microprocessor-controlled device
designed to interface microprocessors, e.g.,
8048/49, 8051, 8080/85, 8086/88 to the GPIB. It
implements all of the interface functions defined in
the IEEE-488 Standard except for the controller
function. If an implementation of the Standard's
Controller is desired, it can be connected with an
Intel® 8292 to form a complete interface.

DEVICE A
ABLE TO
TALK, lISTEf\I

AND

III (

11111
I===t--

DATA BUS

CONTROL
IP' \l cak"lalO')

The 8291 A handles communication between a microprocessor-controlled device and the GPIB. Its capabilities include data transfer, handshake protocol,
talker/listener addressing procedures, device clearing and triggering, service request, and both serial
and parallel polling. In most procedures, it does not
disturb the microprocessor unless a byte has arrived
(input buffer full) or has to be sent out (output buffer
empty).

DEVICE B
ABLE TO
TALK AND
LISTEN

I===t-

(e,g. Iloppy
disk)

DATA BYTE
(

TRANSFER
CONTROL

DEVICE C

ONl Y ABLE

TO LISTEN
Le 9

~t-

~Ignal

GENERAL
INTERFACE

generalo.1

The 8291 A architecture includes 16 registers. Eight
of these registers may be written into by the microprocessor. The other eight registers may be read by
the microprocessor. One each of these read and
write registers is for direct data transfers. The rest of
the write registers control the various features of the
chip, while the rest of the read registers provide the
microprocessor with a monitor of GPIB states, various bus conditions, and device conditions.

(

MANAGEMENT

DEVICE 0
ONl Y ABLE
TO TALK

~t-

Ie 9 counter I

~}DIDl
DAV

NRFD
NOAC

lFe

GPIB Addressing

ATN
SRO
REN
EDI

Each device connected to the GPIB must have at
least one address whereby the controller device in
charge of the bus can configure it to talk, listen, or

205248-4

Figure 4. Interface Capabilities and
Bus Structure

3-5

8291A

Table 2. IEEE 488 Interface State Mnemonics
Mnemonic State Represented

Mnemonic State Represented.

ACDS
ACRS
AIDS
ANRS
APRS
AWNS

PPSS
PUCS

cACs

Parallel Poll Standby State
Parallel Poll Unaddressed to Configure
State
Remote State
Remote With Lockout State
System Control Active State
Source Delay State
Source Generate State
System Control Interface Clear Active
State
Source Idle State
System Control Interface Clear Idle
State
System Control Interface Clear Not
Active State
Source Idle Wait State
System Control Not Active State
Serial Poll Active State
Serial Poll Idle State
Serial Poll Mode State
System Control Remote Enable Active
State
System Control Remote Enable Idle
State
System Control Remote Enable Not
Active State
Service Request State
Source Transfer State
Source Wait for New Cycle State
Talker Active State
Talker Addressed State
Talker Idle State
Talker Primary Idle State

REMS
RWLS
SACS
SDYS
SGNS
SIAS

u
."

g~~~::.:.

:~IPS
SIDS
SIIS

GPPS· .

:GpWS. :.;

SINS

CSRS

CSWS·

SIWS
SNAS
SPAS
SPIS
SPMS
SRAS

~tf1~ .
DCAS
DCIS
DTAS
DTIS
LACS
LADS
LIDS
LOCS
LPAS
LPIS
LWLS
NPRS
PACS
PPAS
PPIS

Device Clear Idle State
Device Trigger Active State
Device Trigger Idle State
Listener Active State
Listener Addressed State
Listener Idle State
Local State
Listener Primary Addressed State
Listener Primary Idle State
Local With Lockout State
Negative Poll Response State
Parallel Poll Addressed to Configure
State
Parallel Poll Active State
Parallel Poll Idle State

SRIS
SRNS
SROS
STRS
SWNS
TACS
TADS
TIDS
TPIS

f d> The Controller function is implemented on the IntelO> 8292.

Table 3. IEEE 488 Interface Message Reference List
Mnemonic

Interface Function(s)

Message

LOCAL MESSAGES RECEIVED (By Interface Functions)
gts(l)
go to standby
ist
individual status
Ion
listen only
Ipe
local poll enable
nba
new byte available
pon
power on
rdy
ready
rpp(l)
request parallel poll
rsc(l)
request system control
rsv
request service
rtl
return to local
sic!l)
send interface clear
sre(l)
send remote enable
tca(l)
take control asynchronously

3-6

C
PP
L, LE
PP
SH
SH,AH,T,TE,L,LE,SR,RL,PP,C
AH

C
C
SR
RL

C
C
C

inter

8291A

Table 3. IEEE 488 Interface Message Reference List (Continued)
Mnemonic

Message

Interface Function(s)

tcs(1)
take control synchronously
ton
talk only
REMOTE MESSAGES RECEIVED
ATN
Attention
DAB
Data Byte
DAC
Data Accepted
DAV
Data Valid
DCL
Device Clear
END
End
GET
Group Execute Trigger
GTL
Goto Local
IDY
Identify
Interface Clear
IFC
LLO
Local Lockout
MLA
My Listen Address
MSA
My Secondary Address
MTA
My Talk Address
OSA
Other Secondary Address
OTA
Other Talk Address
PCG
Primary Command Group
PPC(2)
Parallel Poll Configure
[PPD](2)
Parallel Poll Disable
[PPE](2)
Parallel Poll Enable
PPRN(1)
Parallel Poll Response N
PPU(2)
Parallel Poll Unconfigure
REN
Remote Enable
RFD
Ready for Data
RQS
Request Service
[SDC]
Select Device Clear
SPD
Serial Poll Disable
SPE
Serial Poll Enable
SQR(1)
Service Request
Status Byte
STB
TCT or [TCT](1)
Take Control
UNL
Unlisten
REMOTE MESSAGES SENT
ATN
Attentions
DAB
Data Byte
DAC
Data Accepted
DAV
Data Valid
DCL
Device Clear
END
End
GET
Group Execute Trigger
GTL
Go to Local
IDY
Identify
IFC
Interface Clear
LLO
Local Lockout
MLAor [MLA]
My Listen Address
MSAor [MSA]
My Secondary Address
MTAor[MTA]
My Talk Address
OSA
Other Secondary Address

3·7

AH,C
T, TE
SH,AH,T,TE,L,LE,PP,C
(Via L, LE)
SH
AH
DC
(via L, LE)
DT
RL
L, LE, PP
T, TE, L, LE, C
RL
L, LE, RL, T, TE
TE, LE, RL
T, TE, L, LE
TE
T, TE
TE, LE, PP
PP
PP
PP
(via C)
PP
RL
SH
(via L, LE) .
DC
T, TE
T, TE
(via C)
(via L, LE)
C
L,LE
C
(Via T,TE)
AH
SH
(via C)
(via T)
(via C)
(via C)
C
C
(via C)
(via C)
(via C)
(via C)
(via C)

inter

8291A

Table 3. IEEE 488 Interface Message Reference List (Continued)
. Mnemonic

Interface Functlon(s)(3)

Message

OTA
PCG
PPC
[PPO]
[PPE]
PPRN
PPU
REN
RFO
ROS
[SOC]
SPO
SPE
SRO
STB
TCT
UNL

Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Disable
Parallel Poll Enable
Parallel Poll Response N
Parallel Poll Unconfigure
Remote Enable
Ready for Data
Request Service
Selected Device Clear
Serial Poll Disable
Serial Poll Enable
Service Request
Status Byte
Take Control
Unlisten

.(viaC)
(viaC)
(viaC)
(viaC)
(via C)
PP
(via C)
C
AH
T, TE
(viaC)
(viaC)
(via C)
SR
(via T,TE)
(viaC)
(via C)

NOTES:
1. These messages are handled only by Intel's 8292.
2. Undefined commands which may be passed to the microprocessor.
3. All Controller messages must be sent via Intel's 8292.

telling the 8291 A to release the holdoff. In this way,
the same byte may be read several times; or an over
anxious talker may be held off until all available data .
has been processed.

8291A Registers
A bit-by-bit map of the 16 registers on the 8291A is
presented in Figure 5. A more detaiied explanation
of, each of these registers and their functions folrows. The access of these registers by the microE!Q.cessor is accomplished by using the CS, RO,
WR, and RSO-RS2 pins.
Register

RSO-:-RS2

0
0
1

0
1
d

1
0
d

CCC
CCC
ddd

All Read Registers
All Write Registers
High Impedance

When the 8291A is addressed to talk, it uses the
data-out register to move data onto the GPIB. After
the BO interrupt is received and a byte is written to
this register, the 8291A initiates and completes the
handshake while sending the byte out over the bus.
In the BO interrupt disable mode, the user should
wait until BO is active before writing to the register.
(In the OMA mode, this will happen automatically.) A
read of the Data-In Register does not destroy the'
information in the Data-Out Register.

Data Registers ,
Interrupt Registers

1 017 1 016 1 015 1 014 \ 013 \ 012 \ 011 \ 010 \

ICPT\ APT \GET\ENO\OEC\ ERR \ BO

DATA-IN REGiSTER (OR)

INTERRUPTSlATUS 1 (1R)

ID07\ 006\005\004\003\002\ 001 \000\

\INT \ SPAS \ LLO \ REM \ SPC \ LLOC \ REMC \ AOSC

DATA-OUT REGISTER (OW)

INTERRUPT STATUS 2 (2R)

The Data-In Register is used to move data from the
GPIB to the microprocessor or to memory when the
8291A is addressed to listen. Incoming information
is separately latched by this register, and its contents are not destroyed by a write to the data-out
register. The RFO (Ready for Data) message is held
false until the byte is removed from the data in register, either by the microprocessor or by OMA. The
8291A then completes the handshake automatically.
In RFO holdaff mode (see Auxiliary Register A), the
handshake is not finished until a command is sent

ICPTI APT IGET\ENO\OEC\ ERR \ BO \ BI
INTERRUPT ENABLE 1 (1W)
1

0 \ 0 \OMAO\ OMAI\ SPC \ LLOC\REMC\AOSC\
INTERRUPT ENABLE 2 (2W)

\INT\OTO\ OLO \A05-0\A04-0\A03-0\A02-0\A01-0\
ADDRESS 0 REGISTER
3-8

inter

8291A

Figure 5. 8291A-Registers
REGISTER SELECT
COOE
RS2 RS1 RSO

REAO REGISTERS

'I0-1-7'-10-1-6'-1-01-5"""-1-01-4"'1-013-r1-0-12-1r-0- 1-1 '-10-1--'0I

WRITE REGISTERS

01'0-0-7'-10-0-6""-1-00-5'-1-00-4-'1-0-03-r10-0-2'"I0-0-1'-10-0""""0I

OATAIN

OATAOUT

I CPT I APT I GET I ENO I OEC I ERR I BO I BI

I CPT I APT I GET I ENO I OEC I ERR I BO I BI I
INTERRUPT ENABLE 1

INTERRUPT STATUS 1
liNT ISPASI LLO I REM I SPC ILLOCIREMCIAOScl

INTERRUPT STATUS 2
S8 ISEQSI S6 I S5 I S4 I S3 I S2

INTERRUPT ENABLE 2
S1

S8 I rsv I S6 I S5 I S4 I S3 I S2

SERIAL POLL STATUS
I ton lion I EOI I LPASITPASI LA I TA IMJMNI

AOORESS STATUS
ICPT7ICPT6ICPT5ICPT4ICPT3ICPT2ICPT1ICPTOI

TO I LO I

IAOM11AOMOI

AOORESS MOOE

ICNT21CNT11CNTOICOM41COM3ICOM21COM11COMoI

COMMANOPASSTHROUGH

AUX MOOE

liNT IOTa lOLa IA05-0IA04-0IA03-0IA02-0IA01-01

I ARS I OT I OL I A051 A041 A031 A021 A01 I
AOORESS 0/1

AOORESSO
x

SERIAL POLL MOOE

I OT1 I OL1 IA05-1IA04-1IA03-1JA02-1JA01-11

AOORESS 1

I EC7 I EC61 EC51 EC41 EC31 EC21 EC1 I ECO I
EOS

The 8291A can be configured to generate an interrupt to the microprocessor upon the occurrence of
any of 12 conditions or events on the GPIB. Upon
receipt of an interrupt, the microprocessor must read
the Interrupt Status Registers to determine which
event has occurred, and then execute the appropriate service routine (if necessary). Each of the 12
interrupt status bits has a matching enable bit in the
interrupt enable registers. These enable bits are
used to select the events that will cause the INT pin
to be asserted. Writing a logic" 1" into any of these
bits enables the corresponding interrupt status bits
to generate an interrupt. Bits in the Interrupt Status
Registers are set regardless of the states of the enable bits. The Interrupt Status Registers are then
cleared upon being read or when a local pon (poweron) message is executed. If an event occurs while
one of the Interrupt Status Registers is being read,
the event is held until after its register is cleared and
then placed in the register.

The mnemonics for each of the bits in these registers and a brief description of their respective functions appears in Table 4. This table also indicates
how each of the interrupt bits is set.

NOTE:
The INT bit in the Address 0 Register is a duplicate
of the INT bit in the Interrupt Status 2 Register. It is
only a status bit. It does not generate interrupts and
thus does not have a corresponding enable bit.
The BO and BI interrupts enable the user to perform
data transfer cycles. BO indicates that a data byte
should be written to the Data Out Register. It is set
by T ACS • (SWNS + SGNS) • RFD. It is reset when
the data byte is written, ATN is asserted, or the
8291A exits TACS. Data should never be written to
the Data Out Register before BO is set. Similarly, BI
is set when an input byte is accepted into the 8291 A
and reset when the microprocessor reads the Data
In Register. 80 and 81 are also reset by pon (poweron local message) and by a read of the Interrupt
Status 1 Register. However, if it is so desired, data
transfer cycles may be performed without reading
the Interrupt Status 1 Register if all interrupts except
for 80 or 81 are disabled; 80 and 81 will automatically reset after each byte is transferred.

NOTE:
Reading the interrupt status registers clears the bits
which were set. The software must examine aI/
relevant bits in the interrupt status registers before
disregarding the value or an important interrupt may
be missed.

3-9

8291A

Table 4. Interrupt Bits

Indicates Undefined Commands

CPT

An undefined command has been received.

Set by (TPAS + LPAS)oSCGoACDSoMODE 3

APT

A secondary address must be passed through
to the microprocessor for recognition.

Set by DTAS

GET

A group execute trigger has occurred.

Set by (EOS + EOI)oLACS

END

An EOS or EOI message has been received.

Set by DCAS

DEC

Device Clear Active State has occurred.

Set by TACSonba.DAC.RFD

ERR

Interface error has occurred; no listeners
are active.

TACSo(SWNS + SGNS)

A byte should be output.

A byte has been input.

Set by LACSoACDS

Shows status of the INT pin
The device has been enabled for a serial poll

INT
SPAS

The device is in local lock out state.
I LWLS+RWLS I

LLO

The device is in a remote state.
I REMS+RWLS I

REM

SPAS -SPAS if APRS:STRS:SPAS was true

SPC

These are status only. They will not generate
interrupts, nor do they have corr,esponding
mask bits.

Serial Poll Complete interrupt.

LLCNO LLO

LLOC

Local lock out change interrupt.

Remot[Jocal

REMC

Remote/Local change interrupt.

Addresse[::.unaddressed

ADSC

Address status change interrupt.'
205248-24

NOTE:
1. In ton (talk-only) and Ion (listen-only) modes, no ADSC interrupt is generated.

If the 8291A is used in the interrupt mode, the INT
and DREQ pins can be dedicated to data input and
output interrupts respectively by enabling BI and
DMAO, provided that no other interrupts are enabled. This eliminates the need to read the interrupt
status registers if a byte is received or transmitted.

completed. The bit will be set when the 8291A is an
active listener (LACS) and either EOS (provided the
End on EOS Received feature is enabled in the Auxiliary Register A) or EOI is received. EOS will generate an interrupt when the byte in the Data In Register matches the byte in the EOS register. Otherwise
the interrupt will be generated when a true input is
detected on EOL

The ERR bit is set to indicate the bus error condition
when the 8291 A is an active talker and tries to send
a byte to the GPIB, but there are no active listeners
(e.g., all devices on the GPIB are in AIDS). The logical equivalent of (nba. TACS. DAC. RFD) will set
this bit.

The GET interrupt bit is used by the microprocessor
to detect that DTAS has occurred. It is set by the
8291A when the GET message is received while it is
addressed to listen. The TRIG output pin of the
8291A fires when the GET message is received.
Thus, the basic operation of device trigger may be
started without microprocessor software intervention.

The DEC bit is set whenever DCAS has occurred.
The user must define a known state to which all device functions will return in DCAS. Typically this
state will be a power-on state. However, the state of
the device functions at DCAS is at the designer's
discretion. It should be noted that DCAS has no effect on the interface functions which are returned to
a known state by the IFC (interface clear) message
or the pon local message.

The APT interrupt bit indicates to the processor that
a secondary address is available in the CPT register
for validation. This interrupt will only occur if Mode 3
addressing is in effect. (Refer to the section on addressing.) In Mode 2, secondary addresses will be
recognized automatically on the 8291A. They will be
ignored in Mode 1.

The END interrupt bit may be used by the microprocessor to detect that a multi-byte transfer has been

3-10

8291A

The CPT interrupt bit flags the occurrence of an undefined command and of all secondary commands
following an undefined command. The Command
Pass Through feature is enabled by the BO bit of
Auxiliary Register B. Any message not decoded by
the 8291A (not included in the state diagrams in Appendix B) becomes an undefined command. Note
that any addressed command is automatically ignored when the 8291 A is not addressed.

between memory and the GPIB; DMAI (DMA in) enables the DREO (DMA request) pin of the 8291A to
be asserted upon the occurrence of BI. Similarly,
DMAO (DMA out) enables the DREO pin to be asserted upon the occurrence of BO. One might note
that the DREO pin may be used as a second interrupt output pin, monitoring BI and/or BO and enabled by DMAI and DMAO. One should note that the
DREO pin is not affected by a read of the Interrupt
Status 1 Register. It is reset whenever a byte is written to the Data Out Register or read from the Data In
Register.

Undefined commands are read by the CPU from the
Command Pass Through register of the 8291 A. This
register reflects the logic levels present on the data
lines at the time it is read. If the CPT feature is enabled, the 8291 A will hold off the handshake until
this register is read.

To ensure that an interrupt status bit will not be
cleared without being read, and will not remain uncleared after being read, the 8291A implements a
special interrupt handling procedure. When an enabled interrupt bit is set in either of the Interrupt
Status Registers, the input of the registers are
blocked until the set bit is read. and reset by the
microprocessor. Thus, potential problems arise
when interrupt status changes while the register is
being blocked. However, the 8291 A stores all new
interrupts in a temporary register and transfers them
to the appropriate Interrupt Status Register after the
interrupt has been reset. This transfer takes place
only if the corresponding bits were read as zeroes.

An especially useful feature of the 8291 A is its ability
to generate interrupts from state transitions in the
interface functions. In particular, the lower 3 bits of
the Interrupt Status 2 Register, if enabled by the corresponding enable bits, will cause an interrupt upon
changes in the following states as defined in the
IEEE 488 Standard.
Bit 0
Bit 1
Bit 2

ADSC
REMC
LLOC

change in LIDS or TIDS or MJMN
change in LOCS or REMS
change in LWLS or RWLS

Serial Poll Registers

The upper 4 bits of the Interrupt Status 2 Register
are available to the processor as status bits. Thus, if
one of the bits 0-2 generates an interrupt indicating
a state change has taken place, the corresponding
status bit (bits 3-5) may be read to determine what
the new state is. To determine the nature of a
change in addressed status (bit 0) the Address
Status Register is available to be read. The SPC interrupt (bit 3 in Interrupt Status 2) is set upon exit
from SPAS if APRS:STRS:SPAS occurred which indicates that the GPIB controller has read the bus
serial poll statos byte after the 8291A requested
service (asserted SRO). The SPC interrupt occurs
once after the controller reads the status byte if
service was requested. The controller may read the
status byte later, and the byte will contain the last
status the 8291A's CPU wrote to the Serial Poll
Mode Register, but the SROS bit will not be set and
no interrupt will be generated. Finally, bit 7 monitors
the state of the 8291A INT pin. Logically, it is an OR
of all enabled interrupt status bits. One should note
that bits 3-6 of the Interrupt Status 2 Register do
not generate interrupts, but are available only to be
read as status bits by the processor. Bit 7 in Interrupt
Status 2 is duplicated in Address 0 Register, and the
latter should be used when polling for interrupts to
avoid losing one of the interrupts in Interrupt Status
2 Register.

I SROS I S6 I S5 I S4

I S6 I S5 I S4 I S3 I S2

SERIAL POLL STATUS (3R)
S8

rsv

SERIAL POLL MODE (3W)
The Serial Poll Mode Register determines the status
byte that the 8291 A sends out on the GPIB data
lines when it receives the SPE (Serial Poll Enable)
message. Bit 6 of this register is reserved for the rsv
(request service) local message. Setting this bit to 1
causes the 8291A to assert its SRO line, indicating
its need for attention from the controller-in-charge of
the GPIB. The other bits of this register are available
for sending status information over the GPIB. Sometime after the microprocessor initiates a request for
service by setting bit 6, the controller of the GPIB
sends the SPE message and then addresses the
8291A to talk. At this point, one byte of status is
returned by the 8291A via the Serial Poll Mode Register. After the status byte is read by the controller,
rsv is automatically cleared by the 8291A and an
SPC interrupt is generated. The CPU may request
service again by writing another byte to the Serial
Poll Mode Register with the rsv bit set. If the control-

Bits 4 and 5 (DMAI, DMAO) of the Interrupt Mask 2
Register are available to enable direct data transfers
3-11

inter

8291A

ler performs a serial poll when the rsv bit is clear, the
last status byte written will be read, but the SRQ line
will not be driven by the 8291A and the SRQSbit will
be clear in the status byte.
The Serial Poll Status Register is available for reading the status byte in the Serial Poll Mode Register.
The processor may check the status of a request for
service by polling bit 6 of this register, which corresponds to SRQS (Service Request State). When a
Serial.Poll is conducted and thecontroller-in-charge
reads the status byte, the SRQS bit is cleared. The
SRQ line and the rsv bit are tied together.

Address Registers
Iton lion I EOII LPAS I TPAS I LA I TA I MJMN!
ADDRESS STATUS (4R)
II NT I DTOI DLO I ADS-O I AD4-0 I AD3-0 I AD2-0 I AD1-0 !
ADDRESS 0 (6R)

To use Mode 2 addressing the primary address must
be loaded into the Address 0 Register, and the Secondary Address is placed in the Address 1 Register.
With both primary and secondary addresses residing
on chip, the 8291A can handle all addressing sequences without processor intervention.
-In Mode 3, the 8291A handles addressing just asit does in Mode 1, except that each Major or Minor
primary address must be followed by a secondary
address. All secondary addresses must be verified
by the microprocessor when Mode 3 is used. When
the 8291A is in TPAS or LPAS (talker/listener primary addressed state), and it does not recognize the
byte on the DIO lines, an APT interrupt is generated
(see section on Interrupt Registers) and the byte is
available in the CPT (Command Pass·Through) Register. As part of its interrupt service routine, the microprocessor must read the CPT Register and write
one of the following responses to the Auxiliary Mode
Register:
1. 07H implies a non-valid secondary address
2. OFH implies a valid secondary address

I DT11 DL 1IADS-1IAD4-1IAD3-1IAD2-1IAD1-1!
Setting the TO bit generates the local ton (talk-only)
message and sets the 8291A to a talk-only mode.
This mode allows the device to operate as a talker in
an interface system without a controller.

ADDRESS 1 (7R)
I TO I LO I 0

IADM1IADMO!

ADDRESS MODE (4W)

Setting the LO bit generates the local Ion (Iistenonly) message and sets the 8291 A to a listen-only
mode. This mode allows the device to operate as a
listener in an interface system without a controller.
The above bits may also be used bya controller-incharge to set itself up for remote command or data
communication.

IARSI DT I DL I ADS I AD4 I AD3 I AD2 I AD1
ADDRESS 0/1 (6W)
The Address Mode Register is used to select one of
the five modes of addressing available on the
8291A. It determines the way in which the 8291A
uses theinformation in the Address 0 and Address 1
Registers.

The mode of addressing implemented by the 8291 A
may be selected by writing one of the following
bytes to the Address Mode Register.

-In Mode 1, the contents of the Address 0 Register
constitute the "Major" talkerllistener address while
the Address 1 Register represents the "Minor" talker/listener address. In applications where only one
address is needed, the major talker/listener is used,
and the minor talker/listener should be disabled.
Loading an address via the Address 0/1 Register
into Address Registers 0 and 1 enables the major
and minor talker/listener functions respectively.

-In Mode 2 the 8291A recognizes two sequential
address bytes: a primary followed by a secondary.
Both address bytes must be received in order to enable the device to talk or listen. In this manner,
Mode 2 addressing implements the extended talker
and listener functions as defined in IEEE-488.

Mode
Enable talk only mode (ton)
Enable listen only mode (Ion)
The 8291 may talk to itself
Mode 1, (Primary-Primary)
Mode 2 (Primary-Secondary)
Mode 3 (Primary/ APT-Primary/ APT)

The Address Status Register contains information
used by the microprocessor to handle its oWn addressing. This information includes status bits that
monitor the address state of each talker/listener,
"ton" and "Ion" flags which indicate the talk and
listen only states, and an EOI bit which, when set,
signifies that the END message came with the last
data byte. LPAS and TPAS indicate that the listener

3-12

8291A

or talker primary address has been received. The
microprocessor can use these bits when the secondary address is passed through to determine
whether the 8291A is addressed to talk or listen.
The LA (listener addressed) bit will be set when the
8219A is in LACS (Listener Active State) or in LADS
(Listener Addressed State). Similarly; the TA (Talker
Addressed bit) will be set to indicate TACS or TAOS,
but also to indicate SPAS (Serial Poll Active State).
The MJMN bit is used to determine whether the information in the other bits applies to the Major or
Minor talker/listener. It is set to "1" when the Minor
talker /Iistener is addressed. It should be noted that
only one talker/listener may be active at anyone
time. Thus, the MJMN bit will indicate which, if either, of the talker/listeners is addressed or active.

Mode 3, where secondary addresses are passed
through, must the processor intervene in the addressing sequence.
The Address 0 Register contains a copy of bit 7 of
the Interrupt Status 2 Register (lNT). This is to be
used when polling for interrupts. Software should
poll register 6 checking for INT (bit 7) to be set.
When INT is set, the Interrupt Status Register should
be read to determine which interrupt was received.

Command Pass Through Register
ICPT7ICPT6ICPT5IcPT4lcPT3IcPT2IcPT1IcPTOI
COMMAND PASS THROUGH (5R)

The Address 0/1 Register is used for specifying the
device's addresses according to the format selected
in the Address Mode Register. Five bit addresses
may be loaded into the Address 0 and Address 1
Registers by writing into the Address 0/1 Register.
The ARS bit is used to select which of these registers the other seven bits will be loaded into. The DT
and DL bits may be used to disable the talker or
listener function at the address signified by the other
five bits. When Mode 1 addressing is used and only
one primary address is desired, both the talker and
the listener should be disabled at the Minor address.

The Command Pass Through Register is used to
transfer undefined 8-bit remote message codes from
the GPIB to the microprocessor. When the CPT feature is enabled (bit BO in Auxiliary Register B), any
message not decoded by the 8291A becomes an
undefined command. When Mode 3 addressing is
used secondary addresses are also passed through
the CPT Register. In either case, the 8291A will
hold-off the handshake until the microprocessor
reads this register and issues the VSCMD auxiliary
command.

As an example of how the Address 0/1 Register
might be used, consider an example where two primary addresses are needed in the device. The Major
primary address will be selectable only as a talker
and the Minor primary address will be selectable
only as a listener. This configuration of the 8291 A is
formed by the following sequence of writes by the
microprocessor.
Data

RS2-RSO

1. Select addressing
Mode 1

Operation

CS RD WR
0

00000001

100

2. Load major address
into Address 0 Register
with listener function
disabled.

001AAAAA

110

3. Load minor address
into Address 1 Register
with talker function
disabled.

110BBBBB

110

The CPT and APT interrupts flag the availability of
undefined commands and secondary addresses in
the CPT Register. The details of these interrupts are
explained in the section on Interrupt Registers.
An added feature of the 8291A is its ability to handle
undefined secondary commands following undefined primaries. Thus, the number of available commands for future IEEE"488 definition is increased;
one undefined primary command followed by a sequence of as many as 32 secondary commands can
be processed. The IEEE-488 Standard does not permit users to define their own commands, but upgrades of the standard are thus provided for.
The recommended use of the 8291 A's undefined
command capabilities is for a controller-configured
Parallel Poll. The PPC message is an undefined primary command typically followed by PPE, and undefined secondary command. For details on this procedure, refer to the section on Parallel Poll Protocol.

At this point, the addr_esses AAAAA and BBBBB are
stored in the Address 0 and Address 1 Registers
respectively, and are available to be read by the microprocessor. Thus, it is not necessary to store any
address information elsewhere. Also, with the information stored in the Address 0 and Address 1 Registers, processor intervention is not required to
recognize addressing by the controller. Only in

Auxiliary Mode Register
ICNT21cNT11cNTOlcOM41cOM31cOM21cOM11cOMOI
AUX MODE (5W)
CNTO-2:CONTROL BITS
COMO-4:COMMAND BITS
3-13

8291A

The Auxiliary Mode Register contains a three-bit
control field and a five-bit command field. It is used
for several purposes on the 8291A:

The 8291A is designed to power up in certain states
as specified in the IEEE-488 state diagrams. Thus,
the following states are in effect in the power up
state: SIDS, AIDS, TIDS, LIDS, NPRS, LOCS, and
PPIS.

1. To load "hidden" auxililiry registers on the 8291A
2. To issue commands from the microprocessor to
the 8291A
3. To preset an internal counter used to generate
T1, delay in the Source Handshake function, as
defined in IEEE-488.

The "0000" pon is an immediate execute command
(a pon pulse). It is also used to release the "initialize" state generated by either an external reset
pulse or the "0010" Chip Reset command.

Table 5 summarizes how these tasks are performed
with the Auxiliary Mode Register. Note that the three
control bits determine how the five command bits
are interpreted.
Table 5

0010-Chip Reset (Initialize): This command has the
same effect as a pulse applied to the Reset pin. (Refer to the section on Resl9t Procedure.)
0011-Finish Handshake: This command finishes a
handshake that was stopped because of a hold off
on RFD. (Refer to Auxiliary Register A)

Code

~ontrol Command
Bits
Bits
000
001

Command

ccce

OCCCC Execute auxiliary command
ODDDD Preset internal counter to
match external clock
frequency of DDDD MHz
(DDDD binary representation
of 1 to 8 MHz)

100

DDDDD Write DDDDD into
auxiliary register A

101

DDDDD Write DDDDD into
auxiliary register B

011

0100-Trigger: A "Group Execute Trigger" is forced
by this command. It has the same effect as a GET
command issued by the controller-in-charge of the
GPIB, but does not cause a GET interrupt.
0101, 1101-Clear/Set rtl: These commands correspond to the local rtl message as defined by the
IEEE-488. The 8291 A will go into local mode when a
Set rtl Auxiliary Command is received if local lockout
is not in effect. The 8291 A will exit local mode after
receiving a Clear rtl Auxiliary Command if the 8291A
is addressed to listen.
0110-Send. EOI: The EOI line of the 8291 A may be
asserted with this command. The command causes
EOI to go true with the next byte transmitted. The
EOI line is then cleared upon completion of the
handshake for that byte.

USP3P2 P1 Enable/disable parallel
poll either in response to remote
messages (PPC followed by
PPE or PPD) or as a local
Ipe message. (Enable if U = 0,
disable if 1..I = 1.)

0111, 1111-Non ValidlValid Secondary Address or
Command (VSCMD): This command informs the
8291 A that the secondary address received by the
microprocessor was valid or invalid (0111 = invalid,
1111 = valid). If Mode 3 addressing is used, the
processor must field each extended address and respond to it, or the GPIB will hang up. Note that the
COM3 bit is the invalid/valid flag.

AUXILlAI;IY COMMANDS

Auxiliary commands are executed by the 8291 A
whenever OOOOCCCC is written into the Auxiliary
Mode Register, where CCCC is the 4-bit command
code.

The valid (1111) command is also used to tell the
8291 A to continue from the command-pass-throughstate, or from RFD holdoff on GET, SDC or DCL.

OOOO-Immediate Execute pon: This command resets the 8291A to a power up state (local pon message as defined in IEEE-488).

1000-pon: This command puts the 8291A into the
pon (power on) state and holds it there. It is similar
to a Chip Reset except none of the Auxiliary Mode
Registers are cleared. In this state, the 8291 A does
not participate in any bus activity. An Immediate Execute pon releases the 8291 A from the pon state
and permits the device to participate in the bus activityagain.

The following conditions constitute the power up
state:
1. All talkers and listeners are disabled.
2. No interrupt status bits are set.

3-14

8291A

Thus, the shortest T1 is achieved by setting NF = 1
using an 8 MHz clock with a 50% duty cycle clock
(tSYNC<63 ns):

0001, 1001-Parallel Poll Flag (local "ist" message):
This command sets (1001) or clears (0001) the parallel poll flag. A "1" is sent over the assigned data
line (PRR = Parallel Poll Response true) only if the
parallel poll flag matches the sense bit from the Ipe
local message (or indirectly from the PPE message).
For a more complete description of the Parallel Poll
features and procedures refer to the section on Parallel Poll Protocol.

T 1 (HS)

AUXILIARY REGISTER A

Auxiliary Register A is a "hidden" 5-bit register
which is used to enable some of the 8291A features.
Whenever a 100 A4A3A2A1AO byte is written into the
Auxiliary Register, it is loaded with the data
A4A3A2A1AO' Setting the respective bits to "1" enables the following features.

INTERNAL COUNTER

The internal counter determines the delay time allowed for the setting of data on the DIO lines. This
delay time is defined as T 1 in IEEE-488 and appears
in the Source Handshake state diagram between the
SDYS and STRS. As such, DAV is asserted T 1 after
the DIO lines are driven. Consequently, T1 is a major factor in determining the data transfer rate of the
8291A over the GPIB (T1 = TWRDV2-TWRD15).

AO-RFD Holdoff on all Data: If the 8291A is listening, RFD will not be sent true until the "finish handshake" auxiliary command is issued by the microprocessor. The holdoff will be in effect for each data
byte.

When open-collector transceivers are used for connection to the GPIB, T1 is defined by IEEE-488 to be
2 fJ-s. By writing 0010DDDD into the Auxiliary Mode
Register, the counter is preset to match a fc MHz
clock input, where DDDD is the binary representation of NF [1 ~NF~8, NF = (DDDD)21. When NF =
fc, a 2 fJ-s T1 delay will be generated before each
DAV asserted.

A1-RFD Holdoff on End: This feature enables the
holdoff on EOI or EOS (if enabled). However, no
hold-off will be in effect on any other data bytes.
A;r-End on EOS Received: Whenever the byte in
the Data In Register matches the byte in the EOS
Register, the END interrupt bit will be set in the Interrupt Status 1 Register.
A3-0utput EOI on EOS Sent: Any occurrence of
data in the Data Out Register matching the EOS
Register causes the EOI line to be sent true along
with the data.

tSYNC is a synchronization error, greater than zero
and smaller than the larger of T clock high and T
clock low. (For a 50% duty cycle clock, tSYNC is less
than half the clock cycle).

A4-EOS Binary Compare: Setting this bit causes
the EOS Register to function as a full 8-bit word.
When it is not set, the EOS Register is a 7-bit word
(for ASCII characters).

If it is necessary that T 1 be different from 2 fJ-s, NF
may be set to a value other than fc. In this manner,
data transfer rates may be programmed for a given
system. In small systems, for example, where transfer rates exceeding GPIB specifications are required, one may set NF

\'-0 __

--tRR-

--'RA-

...- - · - - - - ' A O - - - - -

~
. . . tAR

.-.

4-----

. DATA BUS
(DATA OUT)

---

tRO------=--'

I---- 'ROF

VALID DATA

It'
205248-7

WRITE

CS/RSj

WRITE

DATA MAY CHANGE

-'WA- '

I--tow-

-'AW---

DATA BUS
(DATA IN)

'ww

)(

'WO~·

VALID DATA

DATA MAY CHANGE

205248-8

DMA

DREQ

__ ---Jl
•

DACK--------------------~

RDorWR------------------------------------~

205248-9

3-24

intJ

8291A

A.C. TIMING MEASUREMENT POINTS AND LOAD CONDITIONS
INPUT/OUTPUT

DEVICE
UNDER

TEST

= 150 pF

205248-10
A.C. Testing: Inputs are driven at 2.4V for a Logic "I" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "I" and 0.8V for a Logic "0".

205248-11

GPIB TIMINGS(1)
Max

Units

TEOT13(2)

Symbol

EOI J., toTR1 t

135

PPSS, ATN = OA5V

TEOD16

EOI J., to 010 Valid

155

PPSS, ATN = OA5V

TEOT12

EOI t toTR1 J.,

155

PPSS, ATN = OA5V

TATND4

ATN J., to NDAC J.,

155

TATT14

ATN J., toTR1 J.,

155

TACS, AIDS

TATT24

ATN J., toTR2J.,

155

TACS, AIDS

TDVND3-C

DAV J., to NDAC t

650

AH,CACS

TNDDV1

NDAC t to DAV t

350

SH, STRS

TNRDR1

NRFD t to DREQ t

400

TDVDR3

DAV J., to DREQ t

600

AH, LACS, ATN = 2AV

TDVND2-C

DAV t to NDAC J.,

350

AH, LACS

Parameter

Test Conditions

TACS, AIDS

TDVNR1-C

DAV t to NRFD t

350

AH, LACS, rdy = True

TRDNR3

RDJ., to NRFDt

500

AH, LACS

TWRD15

WR t to 010 Valid

280

SH, TACS, RS = OAV

TWRE05

WR t to EOI Valid

350

SH,TACS

TWRDV2

WRt toDAVJ.,

+ tSYNC

High Speed Transfers Enabled,
NF = fc, tSYNC = %-fc

830

NOTES:

1. All GPIB timings are at the pins of the 8291 A.
2. The last number in the symbol for any GPIB timing parameter is chosen according to the transition directions of the
reference signals. The following table describes the numbering scheme.

t
t

.J,

.J, to
.J, to

.J,

to VALID

.J, to VALID

3-25

inter

8291A

APPENDIX A
MODIFIED STATE DIAGRAMS
Figure A-1 presents the interface -function state diagrams. It is derived from IEEE Std. state diagrams,
with the following changes: -

A The 8291A supports the complete set of IEEE488 interface functions except for the controller. These-include: SH1, AH1, T5, TE5, L3, LE3, SR1,
RL1, PP1, DC1, DT1, and CO.
B. Addressing modes Included in T, L stat~ diagrams.

Consider the condition when the -Not-Ready-ForData signal (pin 37) is active. Intel indicates this active low signal with the symbol NRFD (VOUT ~ VOL
for AH; VIN ~ VIL for SH). The IEEE-488-1978 Standard, in its state diagrams, indicates the active state
of this Signal (True condition) with NRFD.
D. All remote multiline messages decoded are con"
ditioned by ACDS. The multiplication by ACDS is
not drawn to simplify the diagrams.

E. The symbol

Note that in Mode 3, MSA, OSA are generated only
after secondary address validity check by the microprocessor (APT interrupt).
C. In these modified state diagrams, the IEEE-488-'
1978 convention of negative (low true) logic is
followed. This should not be confused with the
Intel pin- and signal-naming convention based on
positive logic. Thus, while the state diagrams below carry low true logic, the signals described
elsewhere-in this data sheet are consistent with
--Intel notatioA and are based on positive logic.
Convention
Level

Logic

IEEE-488

Intel

T
F
T
F
T
F

DAV
DAV
NDAC
NDAC
NRFD
NRFD

0
1

x-8 _
205248-12

indicates:
1. When event X occurs, the function returns to
state s.
2. X overrides any other transition condition in the
function.
Statement 2 simplifies the diagram, avoiding the explicit use of X to condition all transitions from S ~o
other states.

r----'
I

I
IL

_ _ _ _ JI

pon
ATN + fj
(WITHIN 12)

DAV

=TACS + SPAS

205248-13

Figure A-1. 8291A State Diagrams
. 3-26

inter

8291A

NDAC

r-----,
I
I
I
AH
I
I
I

NRFD

L ____

pon--_~

·THIS TRANSITION WILL NEVER
OCCUR UNDER NORMAL OPERATION.
tTOElAV IS ABOUT 300 NS

F2 ,WITHIN '2)

FOR DEBOUNCING DAV.

NDAC.._---\

END IF (EOI + EOS) RECEIVED

F2 = ATN + LACS + LADS
F3 = ATN + rdy
T3' = T3 • CPT' APT

205248-14

r----...,
I

I
I

L ____ J

pon---~

IFC
,WITHIN

STB AND RaS AVAILABLE
TO SH

,.1

)-----;.. DAB AVAILABLE TO SH

EOIIF DAB = EOS

F4 = OTA + (OSA. TPAS
MODE 1 + MLA • MODE 1

MSA. LPAS) •

205248-15

Figure A-1. 8291A State Diagrams (Continued)

3-27

inter

8291A·

MTA
p o n - - -. .

PCG·MTA

SPE

pon---~

SPO

IFC
(WITHIN 14)

205248-16

r-'----,
RQS IN STB

.$V. SPAS

SRQ

I
I
I

SRQ

L ____

I
)
I

pon---_'i

SPAS

205248-17

Figure A-1. 8291A State Diagrams (Continued)

3-28

intJ

8291A

r - - - - -1
I

pon

I
I

----of

IFC (WITHIN 14)

MLA

p o n - - -.......~

PCG· MLA
205248-18

r-----l

I
F5·

rti

____

pon---_-t

REN
(WITHIN 14)

GTL·LADS
205248-19
F5 ~ (MLA' MODE 1

LPAS' MSA' MODE 1)

Figure A-1. 8291A State Diagrams (Continued)

3-29

8291A

r----'
I
I

I
I

PP 2

L ____

pon---~

lOY'

lOY
(WITHIN tS)

(WITHIN tS)

PPRN = RESPONSE - - - - I

205248-20
'lOY = ATN • EOI

r----'
I

I
I

I
DC

L_~

I
I

__ J

205248-21

= DCl + SOC. LADS

r--:--'

I
I
lOT
I
Il ____ J I

GET· LADS

205248-22

Figure A-1. 8291A State Diagrams (Continued)

3-30

8291A

APPENDIX B
Table B-1. IEEE 488 Time Values
Time Value
Identifier(1)

Function (Applies to)

Description

t5
T6
T7

SH
LC, IC, SH, AH, T, L
AH
T, TE, L, LE, C, CE
PP
C
C

T8
Tg

C
C

Settling Time for Multiline Messages
Response to ATN
Interface Message Accept Time(S)
Response to IFC or REN False
Response to ATN + EOI
Parallel Poll Execution Time
Controller Delay to Allow Current Talker
to see ATN Message
Length of IFC or REN False
Delay for EOI(5)

T1
t2
Ts

Value
~

2/Ls(2)

::; 200 ns
> 0(4)
< 100 /Ls
::; 200 ns
~
~

2/Ls
500 ns

> 100 /Ls
~

1.5 /Ls(6)

NOTES:
1. Time values specified by a lower case t indicate the maximum time allowed to make a state transition. Time values
specified by an upper case T indicate the minimum time that a function must remain in 11 state before exiting.
2. If three-state drivers are used on the 010, DAV, and EOllines, T1 may be:
1. ;;, 1100 ns.
2. Or ;;, 700 ns if it is known that within the controller ATN is driven by a three-state driver.
3. Or ;;, 500 ns for all subsequent bytes following the first sent after each false transition of ATN (the first byte must be sent
in accordance with (1) or (2).
4. Or ;;, 350 ns for all subsequent bytes following the first sent after each false transition of ATN under conditions specified
in Section 5.2.S and warning note. See IEEE Standard 488.
3. Time required for interface functions to accept, not necessarily respond to interface messages.
4. Implementation dependent.
5. Delay required for EOI, NDAC, and NRFD signal lines to indicate valid states.
6. ;;, 600 ns for three-state drivers.

3-31

intJ

8291A

APPENDIX C
THE THREE-WIRE HANDSHAKE.
TWRDI5

0101-0108

VALID

f4T11

4
' NOT VALID

VALID

f4-~

_TWRDV2

!-TNDDV1_1-TDVNR,_

--,1£.
I

I+-TRDNR3-

__J

NRFD

f-TDVND3_

r--

OREQ(SH)

_TDVDR3
DREQ(AH)

-ell

~
205248--23

Figure C-1. 3-Wlre Handshake Timing at 8291A

3·32

8292
GPIB CONTROLLER
•

Complete IEEE Standard 488 Controller
Function

•

Complete Implementation of Transfer
Control Protocol

•

Interface Clear (IFC) Sending Capability
Allows Seizure of Bus Control and/or
Initialization of the Bus

•

Synchronous Control Seizure Prevents
the Destruction of Any Data
Transmission in Progress

•

Responds to Service Requests (SRQ)

•

Sends Remote Enable (REN), Allowing
Instruments to Switch to Remote
Control

Connects with the 8291 to Form a
Complete IEEE Standard 488 Interface
Talker / Listener/Controller

The 8292 GPIB Controller is a microprocessor-controlled chip designed to function with the 8291 GPIB Talker/Listener to implement the full IEEE Standard 488 controller function, including transfer control protocol.
The 8292 is a preprogrammed Intel® 8041 A.

MICROPROCESSOR SYSTEM BUS

IFCL

r--- --...
II

I
I

OMA
CONTROLLER
(OPTIONAL)

OACK

I--::-==-i

I
I

8291

OREO

GPIB
TALKERI
LISTENER

L ______ I

8292
GPIB
CONTROLLER

REN

RESET

OAV

Vee

IBFI

TIR 2

TiRi

VCC
COUNT

OBFI

GNO

EOI

AD
AD

SPI

CIC

SYNe

TCI

ATNO

CLTH

Vee

8293

BUS
TRANSCEIVERS

SYC

IFC

IITNI

VSS

SRO

205250-2
GENERAL PURPOSE INTERFACE BUS

Figure 2. Pin Configuration
205250-1

Figure 1.8291,8292 Block Diagram

3-33

November 1986
Order Number: 205250·002

8292

Table 1 Pin Description
Pin
Number

Type

IFCL

IFC RECEIVED (LATCHED): The 8292 monitors the IFC Line (when not
system controller) through this pin.

X1> X2

2,3

CRYSTAL INPUTS: Inputs for a crystal, LC or an external timing signal to

Symbol

Name and Function

determine the internal oscillator frequency.

RESET

RESET: Used to initialize the chip to a known state during power on.

CHIP SELECT INPUT: Used to select the 8292 from other devices on the

common data bus.
RD

READ ENABLE: Allows the master CPU to read from the 8292.

ADDRESS LINE: Used to select between the data bus and the status

register during read operations and to distinguish between data and
commands written into the 8292 during write operations.
WR

SYNC

SYNC: 8041 A instruction cycle synchronization signal; it is an output

clock with a frequency of XTAL .;- 15.

I/O

DATA: 8 bidirectional lines used for communication between the central
processor and the 8292's data bus buffers and status register.

7,20

P.S.

GROUND: Circuit ground potential.

SRQ

SERVICE REQUEST: One of the IEEE control lines. Sampled by the
8292 when it is controller in charge. If true, SPI interrupt to the master will
be generated.

ATNI

ATTENTION IN: Used by the 8292 to monitor the GPIBATN control line.

IFC

I/O

SY9

SYSTEM CONTROLLER: Monitors the systefTI controller switch.

CLTH

CLEAR LATCH: Used to clear the IFCR latch after being recognized by

ATTENTION OUT: Controls the ATN control line of the bus through
external logic for tcs and tca procedures. (ATN is a GPIB control line, as
defined by IEEE Std. 488-1978.)

5,26,40

P.5.

00-0 7
Vss

12-19 ,

WRITE ENABLE: Allows the master CPU to write to the 8292.

If is used during the transfer control procedure.

ArNo
Vee
COUNT

INTERFACE CLEAR: One of the GPIB management lines, as defined by
,IEEE Std. 488-1978, places all devices in a known quiescent state.

the 8292. Usually low (except after hardware Reset), it will be pulsed high
when IFCR is recognized by the 8292.

VOLTAGE: +5V supply input ±10%.
EVENT COUNT: When enabled by the proper command the internal

counter will count external events through this pin. High to low transition
will increment the internal counter by one. The pin is sampled once per
three internal instruction cycles (7.5 /-Lsec sample period when using 5
MHz XTAL).lt can be used for byte counting when connected to NOAC,
or for block counting when conntjlcted to the EOL
REN

REMOTE ENABLE: The Aemote,Enable bus signal selects remote or

local control of the device on the bus. A GPIB bus Signal selects remote
or locaJ control of the device on the bus. A GPIB bus management line,
as defined by IEEE Std. 488-1978.

3-34

8292

Table 1. Pin Description (Continued)
Symbol

Pin
No.

Type

DAV

I/O

DATA VALID: Used during parallel poll to force the 8291 to accept the
parallel poll status bit. It is also used during the tcs procedure.

IBFI

INPUT BUFFER NOT FULL: Used to interrupt the central processor
while the input buffer of the 8292 is empty. This feature is enabled and
disabled by the interrupt mask register.

OBFI

OUTPUT BUFFER FULL: Used as an interrupt to the central processor
while the output buffer of the 8292 is full. The feature can be enabled and
disabled by the interrupt mask register.

E012

I/O

END OR IDENTIFY: One of the GPIB management lines, as defined by
IEEE Std. 488-1978. Used with ATN as Identify Message during parallel
poll.

SPI

SPECIAL INTERRUPT: Used as an interrupt on events not initiated by
the central processor.

TCI

TASK COMPLETE INTERRUPT: Interrupt to the control processor used
to indicate that the task requested was completed by the 8292 and the
information requested is ready in the data bus buffer.

CIC

CONTROLLER IN CHARGE: Controls the SIR input of the SRQ bus
transceiver. It can also be used to indicate that the 8292 is in charge of
the GPIB bus.

Name and Function

FUNCTIONAL DESCRIPTION

OPIB

The 8292 is an Intel 8041A which has been programmed as a GPIB Controller Interface element. It
is used with the 8291 GPIB Talker/Listener and two
8293 GPIB Transceivers to form a complete IEEE488 Bus Interface for a microprocessor. The electrical interface is performed by the transceivers, data
transfer is done by the talker /listener, and control of
the bus is done by the 8292. Figure 3 is a typical
controller interface using Intel's GPIB peripherals.

PROCESSOR
BUS

OPIB

205250-3

Figure 3. Talker/Listener/Controller
Configuration

3-35

8292

The internal RAM in the 8041 A is used as a special
purpose register bank for the 8292. Most of these
registers (except for the interrupt flag) can be accessed through commands to the 8292. Table 2
identifies the registers used by the 8292. and how
they are accessed.
'

Event Counter Interrupt. The requested .number of blocks of data byte has been transferred. The EV interrupt flag is cleared by the
lACK command.
SRQ Service Request. Notified the 8292 that a
se.rvice request (SRO) message has been received. It is cleared by the lACK command.
ERR Error occurred. The type of error can be determined by reading the error status register.
This interrupt flag is cleared by the lACK command.
SYC System Controller Switch Change. Notifies
the processor that the state of the system
controller switch has changed. The actual
state is contained in the GPIB Status Register. This flag is cleared by the lACK command.

Interrupt Status Register
I SYC I ERR I SRO I EV I X IIFCR IIBF I OBF 1

The 8292 can be configured to interrupt the micro- '
processor on one .of several conditions. Upon receipt of the interrupt the microprocessor must read
the 8292 interrupt status register to determine which
event caused the interrupt, and then the appropriate
subroutine cali be performed. The interrupt status
register is read with Ao high. With the exception of
Interrupt Mask Register
OBF and IBF, these interrupts are enabled or disabled by the SPI interrupt mask. OBF and IBF have
11 1 SPI I TCI SYC I OBFI 1 IBFI I 0 I SRO 1
their own bits in the interrupt mask (OBFI and IBFI).
Do
OBF Output Buffer Full. A byte is waiting to be read
by the microprocessor. This flag is cleared .
The Interrupt Mask Register is used to enable feawhen the output data bus buffer is read.
tures and to mask the SPI and TCI interrupts. The
IBF Input Buffer Full. The byte previously written
flags in the Interrupt Status Register will be active
by the microprocessor has not been· read yet
even when masked out. The Interrupt Mask Register
by ~he 8292. If another byte is written to the
is written when Ao is low and reset by the RINM
8292 before this flag clears, data will be lost.
command. When the register is read, D1 and D7 are
IBF is cleared when the 8292 reads the data
undefined. An interrupt is enabled by setting the corbyte.
responding register bit.
IFCR Interface Clear Received. The GPIB system
.SRQ Enable interrupts on SRO received.
controller has set IFC. The 8292 has become
IBFI Enable interrupts on input buffer empty.
idle and is no loliger is charge of the bus. The
flag is cleared when the lACK command is
OBFI Enable interrupts on output buffer full.
issued.
Table 2. 8292 Registers

WRITE TO 8292

READ FROM 8292

INTERRUPT STATUS

1 SYC 1 ERR 1 SRO 1 EiI 1
07 '

1 x

I
I

CSBS

REN

1 IFCR 1

IBF

ERROR FLAG
I

I
I

I USER

1 x 1 x

INTERRUPT MASK

1 OBF 11 1 1 1

0
0

I
I

TCI

OAV

I SYCS

IFC

GPIB (BUS) STATUS
EOI

SYC

IFC

0
0

I
I

TIME OUT STATUS

1 SRO

ERROR MASK
I

1USER I

CONTROLLER STATUS
CA

1 SYC 1 OBFI 1 IBFi 1

DO
ITOUT3ITOUT2ITOUT1Io.

I 0

1TOUT3I TOUT21TOUT1I

COMMAND FIELD

1 REN

ANTI

1 1 1 1 1 1

I SRO 10' I

SRO 10'

EVENT COUNTER STATUS.

I
I

SPI

I
I

0
0

I
I

10 '

10'

I
I

0
0

I
I

EVENT COUNTER

NOTE: These registers are accessed by a special utility
command. see page 7;

3-36

10'

TIMEOUT

intJ

8292
on pin 39 of the 8292 (COUNT). It can be connected
to EOI or NDAC to count blocks or bytes respectively during standby state. A count of zero equals 256.
This register cannot be read, and is written using the
WEVC command.

SYC Enable interrupts on a change in the system
controller switch.
TCI Enable interrupts on the task completed.
SPI Enable interrupts on special events.
NOTE:
The event counter is enabled by the GSEC command, the error interrupt is enabled by the error
mask register, and IFC cannot be masked (it will always cause an interrupt).

Event Counter Status Register

Controller Status Register
ICSBSI CA I X I X Isycsi IFC I REN I SRO I
DO
The Controller Status Register is used to determine
the status of the controller function. This register is
accessed by the RCST command.
SRQ
REN
IFC
SYCS
CA

Service Request line active (CSRS).
Sending Remote Enable.
Sending or receiving interface clear.
System Controller Switch Status (SACS).
Controller Active (CACS + CAWS
CSWS).

This register contains the current value in the event
counter. The event counter counts back from the
initial value stored in the Event Counter Register to
zero and then generates an Event Counter Interrupt.
This register cannot be written and can be read using a REVC command.
Time Out Register
Do
The Time Out Register is used to store the time
used for the time out error function. See the individual timeouts (TOUT1, 2, 3) to determine the units of
this counter. This Time Out Register cannot be read,
and it is written with the WTOUT command.

CSBS Controller Stand-by State (CSBS, CAl
(O,O)-Controller Idle.

Time Ol,lt Status Register

GPIB Bus Status Register

This register contains the current value in the time
out counter. The time out counter decrements from
the original value stored in the Time Out Register.
When zero is reached, the appropriate error interrupt
is generated. If the register is read while none of the
time out functions are active, the register will contain
the last value reached the last time a function was
active. The Time Out Status Register cannot be written, and it is. read with RTOUT command.

I REN I DAV I EOI I X I SYC IIFC I ATNI I SRO I
DO
This register contains GPIB bus status information. It
can be used by the microprocessor to monitor. and
manage the bus. The GPIB Bus Register can be
read using the RBST command.
Each of these status bits reflect the current status of
the corresponding pin on the 8292.
SRQ Service Request
ATNI Attention In
IFC Interface Clear
SYC System Controller Switch
EOI End or Identify
DAV Data Valid
REN Remote Enable

Error Flag Register

Four errors are flagged by the 8292 with a bit in the
Error Flag Register. Each of these errors can be
masked by the Error Mask Register. The Error Flag
Register cannot be written, and it is read by the
lACK command when the error flag in the Interrupt
Status Register is set.
TOUT1 Time Out Error 1 occurs when the current
controller has not stopped sending ATN after receiving the TCT message for the time
period specified by the Time Out Register.
Each count in the Time Out Register is at
least 1800 tey. After flagging the error, the
8292 will remain in a loop trying to take control until the current controller !;\tops send-

Event Counter Register

The Event Counter Register contains the initial value
for the event counter. The counter can count pulses
3-37

inter

8292

ing ATN or a new command is written by
the microprocessor. If a new command is
written, the 8292 will return to the loop after
executing it.
TOUT2 Time Out Error 2 occurs when the transmission between the addressed talker and listener has not started for the time period
specified by the Time Out Register. Each
count in the Time Out Register is at least 45
tCY.' This feature is only enabled when the
controller is in the CSBS state.
TOUT3 Time Out Error 3 occurs when the hand, shake signals are stuck and the 8292 is not
succeeding in taking control synchronously
for the time period specified by the Time
Out Register. Each count in the Time Out
Register is at least 1800 tCY. The 8292 will
continue checking ATNI until it becomes
true or a new commnand is received. After
performing the new command, the 8292 will
return to the ATNI checking loop.
USER User error occurs when request to assert
IFC or REN was received and the 8292 was
not the system controller.

FD-SPCNI-Stop Counter Interrupts
This command disables the internal counter interrupt so that the 8292 will stop interrupting the master
on event counter underflows. However, the counter
will continue counting and its contents can still be
used.

F1-GIDL-Go To Idle
This command is used during the transfer of control
procedure while transferring control to another controller. The 8292 will respond to this command only
if it is in the active state. ATNO will go high, and CIC
will be high so that this 8292 will no longer be driving
the ATN line on the GPIB interface bus. TCI will be
set upon completion.

F2-RST-Reset
This command has the same effect as asserting the
external reset on the 8292. For details, refer to the
reset procedure described later.

F3-RSTI-Reset Interrupts

Error Mask Register

I 0 I0 IUSER I0 I0 ITOUT ITOUT ITOUT I
3

Do
The Error Mask Register is used to mask the interrupt from a particular type of error. Each type of error
interrupt is enabled by setting the corresponding bit
in the Error Mask Register. This register can be read
with the RERM command and written with Ao low.

Command Register

I I I OP

Do
Commands are performed by the 8292 whenever a
byte is written with Ao high. There are two categories
of commands distinguished by the OP bit (bit 4). The
first category is the operation command (OP = 1).
These commands initiate some action on the interface bus. The second category is the utility command (OP = 0). These commands are used to aid
the communication between the processor and the
8292.

This command resets any pending interrupts and
clears the error flags. The 8292 will not return to any
loop it was in (such as from the time out interrupts).

F4-GSEC-Go To Standby, Enable Counting
The function causes ATNO to go high and the Counter will be enabled. If the 8292 was not the active
controller, this command will exit immediately. If the
8292 is the active controller, the counter will be
loaded with the value stored in the Event Counter
Register, and the internal interrupt will be enabled so
that when the counter reaches zero, the SPI interrupt will be generated. SPI will be generated every
256 counts thereafter until the controller exits the
standby state or the SPCNI command is written. An
initial count of 256 (zero in the Event Counter Register) will be used if the WEVC command is not executed. If the data transmission does not start, a
TOUT2 error will be generated.

F5-EXPP-Execute Parallel Poll
This command initiates a parallel poll by asserting
EOI when ATN is already active. TCI will be set at
the end of the command. The 8291 should be previously configured as a listener. Upon detection of
DAV true, the 8291 enters ACDS and latches the
parallel poll response (PPR) byte into its data in register. The master will be interrupted by the 8291 BI
interrupt when the PPR byte is available. No interrupts except the IBFI will be generated by the 8292.
The 8292 will respond to this command only when it
is the active controller.

OPERATION COMMANDS
Operation commands initiate some action on the
GPIB interface bus. It is using these commands that
the control functions such as polling, taking and
passing control, and system controller functions are
performed.
3-38

intJ

8292

ing the controller function for being in the GSBS
(else it will exit immediately), ATNO will go low, and
a TGI interrupt will be generated.

F6-GTSB-Go To Standby
If the 8292 is the active controller, ATNO will go high
then TGI will be generated. If the data transmission
does not start, a TOUT2 error will be generated.

FD-TCSY-Take Control Synchronously

If the 8292 is the system controller, then REN will be
asserted false and TGI will be set true. If it is not the
system controller, the User Error bit will be set in the
Error Flag Register.

There are two different procedures used to transfer
the 8292 from GSBS to GAGS depending on the
state of the 8291 in the system. If the 8291 is in
"continuous AH cycling" mode (Aux. Reg. AD = A1
= 1), then the following procedures should be followed:

FS-SREM-Set Interface To Remote Control

1) The master microprocessor stops the continuous
AH cycling mode in the 8291;

F7-SLOC-Set Local Mode

This command will set REN true and TGI true if this
8292 is the system controller. If not, the User Error
bit will be set in the Error Flag Register.

2) The master reads the 8291 Interrupt Status 1
Register;
3) If the END bit is set, the master sends the TGSY
command to the 8292;

F9-ABORT-Abort All Operation, Clear
Interface

4) If the END bit was not set, the master reads the
8291 Data In Register and then waits for another
BI interrupt from the 8291. When it occurs, the
master sends the 8292 the TGSY command.

This command will cause IFG to be asserted true for
at least 100 J-Lsec if this 8292 is the system controller. If it is in GIDS, it will tai
2.0

POIN~S

D..

0.45

2.0

TEST

0.8

A.C. TESTING LOAD CIRCUIT

DEVICE
UNDER

TEST

'lC

205250-6
A.C. Testing: Inputs are driven at 2.4V for a Logic "I" and 0.45V
for a Logic "0". Timing measurements are made at 2.0V for a
Logic "I" and O.SV for a Logic "0".

-=
205250-7
CL Include Jig Capacitance.

CLOCK DRIVER CIRCUITS
CRYSTAL OSCILLATOR MODE

DRIVING FROM EXTERNAL SOURCE
+5V

: Lr-----

< 15 pF
(INCLUDES XTAL.
SOCKET. STRAY)

~
I
I

15-25pF

XTALI
4701/

6 mHZ

Jo-+-----=-t HAL 1
+5V

~_____
(INCLUDES SOCKET.
STRAY)

XTAl2
4701/

"---.4---''-1 XTAL2
205250-S

NOTE:
205250-9
Both XTAL 1 and XTAL2 should be driven. Resistors to
Vcc are needed to ensure VIH = 2.8V if TTL circuitry
is used.

NOTE:
Crystal series resistance should be <750. at 6 MHz;
<1800. at 3.6 MHz.

LC OSCILLATOR MODE

L
45,..H
120 ,..H

C
20pF
20pF

NOMINAL!
5.2 MHz
3.2 MHz

rIo ~,
T
-=-

XTAU'
1
f = 27f,f[C'

C·=C+3Cpp
2
XTAU

NOTES:
205250-10
1. Cpp ::::: 5-10 pF pin-to-pin capacitance
2. Each C should be approximately 20 pF, including stray capacitance.

3-46

intJ

8292

WAVEFORMS
READ OPERATION-DATA BUS BUFFER REGISTER

Cs OR Ao
(SYSTEM'S
ADDRESS BUS)

K
-tAR""""':"-

- - tRA--

IRR

IRV

AD
(READ CONTROL)

/
-tOF--

-tRO_lAD

DATA BUS _ _ _ _ _ _ _......,.._:,..I---D-AT-A-VA-L-to---;! _ _ _ _ _ _ _ __
(OUTPUn

205250-11

WRITE OPERATION-DATA BUS BUFFER REGISTER
CSORAo
(SYSTEM'S
ADDRESS BUS)

________________

-lAW-I 1 - '
(WRITE

CONTR~~

Iww

~F---------"";
-tow-

DATA BUS
(INPUT)

DATA
MAY CHANGE

----_____

DATA VALID

IWD

DATA
MAY CHANGE

-J~-----~~---------205250-12

3-47

intJ

8292

APPENDIX A
The following tables and state diagrams were taken from the IEEE Standard Digital Interface for Programmable Instrumentation, IEEE Std. 488-1978. This document is the official standard for the GPIB bus and can be
purchased from IEEE, 345 East 47th St., New York, NY 10017.

C MNEMONICS
Messages

=power on
=request system control
=request parallel poll
=go to standby
=take control asynchronously
=take control synchronously
=send interface clear
=send remote enable
IFC = interface clear
ATN =attention
TCT =take control

pan
rsc
rpp
gts
tca
tcs
sic
sre

Interface States
CIDS
CADS
CTRS
CACS
CPWS
CPPS
CSBS
CSHS
CAWS
CSWS
CSRS
CSNS
SNAS
SACS
SRIS
SRNS
SRAS
SIIS
SINS
SIAS

~
~

=controller idle state
=controller addressed state
=controller transfer state
=controller active state
=controller parallel poll wait state
=controller parallel poll state
=controller standby state
=controller standby hold state
=controller active walt state
=controller synchronous wait state
=controller service requested state
=controller service not requested state
=system control not active state
=system control active state
=system control remote enable idle state
=system control remote enable not active state
=system control remote enable active state
=system control interface clear idle state
=system control interface clear not active state
=system control interface clear active state
=accept data state (AH function)
=acceptor not ready state (AH function)

~ = source delay state (SH function)
cm@ = source transfer state (SH function)
~

=talker addressed state (T function)
205250-14

iFC

pon_lCIDSJ"
(SACS)/'-/"

~Q
O~

CTRS

(WITHIN 14)
IIFC

(ACDS) I\ITCT

(TADS)!

TCT

SRC

(ACDS)

lea

(ANRS)

"II

iEi
c

ii1

:""
c.J

J,.
CD

(')

en
SeD
c

,se

;

3
(SACS)

NOTES:
• T10 > 1.5 /Lsec
t The microprocessor must wait for the 80 interrupt before writing the GTSB or GSEC
commands to ensure that (STRS 1\ SDYS) is true.

sic

205250-13

inter

8292

REMOTE MESSAGE CODING
Bus Signal Line(s) and Coding That
Asserts the. True Value of the Message
Mnemonic

C
L D
Y A I
p S 0

Message Name

E S 8 7 6 5 4 3 2 1
ACG
ATN
DAB

GET
GTL
IDY
IFC
LAG
LLO
MLA

Addressed Command Group
M AC Y
Attention
U UC X
Data Byte
(Notes 1, 9) M DD D
8
Data Accepted
U HS X
Data Valid
U HS X
Device Clear
M UC Y
End
U ST X
(Notes 2, 9) M DD E
End of String
8
Group Execute Trigger
M AC Y
Goto Local
M AC Y
Identify
U UC X
Interface Clear
U UC X
Listen Address Group
M AD Y
Local Lock Out
M UC Y
My Listen Address
(Note 3) M AD Y

MTA

My Talk Address

(Note 4)

MSA

My Secondary Address

(Note 5)

NUL
OSA
OTA
PCG
PPC
PPE

Null Byte
Other Secondary Address
Other Talk Address
Primary Command Group
Parallel Poll Configure
Parallel Poll Enable

(Note 6)

PPD

Parallel Poll Disable

(Note 7)

PPR1
PPR2
PPR3
PPR4
PPR5
PPR6
PPR7
PPR8
PPU
REN
RFD
RQS
SCG
SDC
SPD

Parallel Poll Response 1
Parallel Poll Response 2
Parallel Poll Response 3
Parallel Poll Response 4
Parallel Poll Response 5
Parallel Poll Response 6
Parallel Poll Response 7
Parallel Poll Response 8
Parallel Poll Unconfigure
Remote Enable
Ready for Data
Request Service
Secondary Command Group
Selected Device Clear
Serial Poll Disable

DAC
DAV
DCL
END
EOS

(Note 10)

(Note 9)

NN
DRD
AFA
VDC

AESIR
TORFE
NIQCN

0 0 0 X X X X
XXX
X X X X
X X X X X X X
XXX
1 X X X X
D D D D D D D
X X X
oX XXX
7 6 543 2 1
X XX X XX X
X X 0
XXXXX
X X X X X X X
X X X X X
1 X X
0 0 1 0 1 0 0
X X X
1X X X X
XX X X X X X
o1 XXX
X X X
E E E E E E E
oX XXX
X X X
7 6 5 4 3 2 1
0 0 0 1 0 0 0
XXX
1 X X X X
0 0 0 0 0 0 1
X X X
1 X X X X
X X X X X X X
X X X
X 1 X X X
XXX
X X X 1 X
X X X X X X X
0 1 X X X X X
X X X
1 X X X X
0 0 1 0 0 0 1
XXX
1 X X.X X
0 1 L L L L L
XXX
X X X X
54321
M AD Y
OTTTTT
XXX
XXXX
432 1
5
M SE Y
1SSSSS
XXX
XXXX
54321
X X X
XXXXX
M DD 0 o 0 0 0 000
M SE
(OSA = SCG /\ MSA)
(OTA = TAG /\ MTA)
MAD
M(PCG =ACG V UCG V LAG V TAG)
M AC Y 00 0 0 1 0 1
XXx.
1XXXX
M SE Y
10SPPP
XXX
X X X X
321
M SE Y 1
1DDDD
X X X
XXXX
432 1
'1
U ST X X X X XX X 1
X.X X
X X X
USTXXXXXX1X
X X X
1
XXX
U ST X .X X X X 1 X X
X X X
XXX
U ST X X X X 1 X X X
X X X
X X X
U ST X X X 1 X X X X
XXX
XXX
XXX
XXX
U ST X X 1 X X X X X
U ST X 1 X X X X X X
XXX
X X X
X X X
1 X X X
U ST 1 X X X X X X X
X X X
1 X X X X
M UC Y 0 0 1 0 1 0 1
XXX
X X X X 1
U UC X X X X X X X X
X 0 X
XXXXX
U HS X X X X X X X X
X X X
oXXXX
U ST X 1 X X X X X X
M SE Y 1 1 X X X X X
X X X
XXXX
MAC YO 0 001 0 0
X X X
X X X X
M UCY 0 0 1 1 0 0 1
XXX
XXXX

3-50

inter

8292

REMOTE MESSAGE CODING (Continued)
Bus Signal Line(s) and Coding That
Asserts the True Value of the Message
Mnemonic

Message Name

C
L D
Y A I
P S 0
E S 876 5 432

D
I

0
1

M UC Y 0 0 1 1 0 0 0
USTXXXXXXXX
(Notes 8, 9) M ST S X S S S S S S
65432 1
8
Take Control
M AC Y 0 0 0 1 0 0 1
Talk Address Group
M AD Y 1 0 X X X X X
Universal Command Group
M UC Y 0 0
XXXX
Unlisten
M 10 Y 0 1 1 1 1 1 1
(Note 11) M 1 0 Y 1 0 1 1 1 1 1
Untalk

SPE
SRQ
STB

Serial Poll Enable
Service Request
Status Byte

TCT
TAG
UCG
UNL
UNT

NN
DRD
A FA
VDC

A E SIR
TOR F E
N I Q C N

X X X
X X X
X X X

1 X X X X
X X 1 X X
0 X X X X

X X X
X X X
X X X
X X X
XXX

X
X
X
X
X

The 1/0 coding on ATN when sent concurrent with multiline messages has been added to this revision for interpretive
convenience.
NOTES:

1.
2.
3.
4.
5.
6.

01 - 08 specify the device dependent data bits.
E1-E8 specify the device dependent code used to indicate the EGS message.
L1-L5 specify the device dependent bits of the device's listen address.
T1-T5 specify the device dependent bits of the device's talk address.
51-55 specify the device dependent bits of the device's secondary address.
5 specifies the sense of the PPR.
Response = 5mist
P1- P3 specify the PPR message to be sent when a parallel poll is executed.
P3
P2
P1
PPR Message

PPR1

1
1
1
PPR8
7. 01-04 specify don't-care bits that shall not be decoded by the receiving device. It is recommended that all zeroes be
sent.
8. 51-S6, S8 specify the device dependent status (010.7 is used for the RQS message.)
9. The source of the message on the ATN line is always the C function, whereas the messages on the DIG and EGI lines
are enabled by the T function.
10. The source of the messages on the ATN and EGI lines is always the C function, whereas the source of the messages on
the 010 lines is always the PP function.
11. This code is provided for system use.

3-51

8294A
DAT'A ENCRYPTION/DECRYPTION UNIT
Certified by National Bureau of
• Standards
400 Byte/Sec Data Conversion Rate
• 64-Bit
Data Encryption Using 56-Bit Key
• DMA Interface
• 3 Interrupt Outputs to Aid in Loading
• and Unloading Data
• 7-Bit User Output Port

5V ± 10% Power Supply
• Single
Compatible with iAPX-86, 88,
• Fully
MCS-85™, MCS-80™, MCS-51TM, and
MCS-48TM Processors

•
• Encrypt and Decrypt Modes Available
Implements Federal Information
Processing Data Encryption Standard

The Intel® 8294A Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and
decrypt 64-bit blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard. The DEU operates on 64-bit text words using a 56-bit user-specified key to produce 64-bit
cipher words. The operation is reversible: if the cipher word is operated upon, the original text word is produced. The algorithm itself is permanently contained in the 8294A; however, the 56-bit key is user-defined and
may be changed at any time.
The 56-bit key and 64-bit message data are transferred to and from the 8294A in 8-bit bytes by way of the
system data bus. A DMA interface and three interrupt outputs are available to minimize software overhead
associated with data transfer. Also, by using the DMA interface two or more DEUs may be operated in parallel
to achieve effective system conversion rates which are virtually any multiple of 400 bytes/second. The 8294A
also has a 7-bit TTL compatible output port for user-specified functions.
Because the 8294A implements the NBS encryption algorithm it can be used in a variety of Electronic Funds
Transfer applications as well as other electronic banking and data handling applications where data must be
encrypted.

DATA
BUS

NC
Xl
X2
RESET

1-8
\-'_

Vee

cs
GNO
RO

OAV----j
CCMP----j
RESET - - - - - '

SYNX~_.

-~.

ORO
DACK

x,---=L::J

+5V -

POWER -GND------

INTERNAL
BUS

210465-1

Figure 1. Block Diagram

WR
SYNC
00
01
02

P5
P4
P3
P2

PD
VOO
VCC
CCMP
NC
NC
NC
210465-2

Figure 2. Pin Configuration

3-52

November 1986
Order Number: 210465·004

inter

8294A

Table 1. Pin Description
Symbol

Pin
No.

Type

Name and Function

NO CONNECTION.

X1
X2

2
3

CRYSTAL: Inputs for crystal, L-C or external timing signal to determine
internal oscillator frequency.

RESET

Vee

GNO

READ: An active low read strobe at this pin enables the CPU to read
data and status from the internal OEU registers.

ADDRESS: Address input used by the CPU to select OEU registers
during read and write operations.

WRITE: An active low write strobe at this pin enables the CPU to send
data and commands to the OEU.

SYNC

SYNC: High frequency (Clock
for external circuitry.

12
13
14
15
16
17
18
19

I/O

01
02
03
04
05
06
07

RESET: A low signal to this pin resets the 8294A.
POWER: Tied high.

CHIP SELECT: A low signal to this pin enables reading and writing to
the 8294A.
GROUND: This pin must be tied to ground.

15) output. Can be used as a strobe

DATA BUS: Three-state, bi-directional data bus lines used to transfer
data between the CPU and the 8294A.

GNO

GROUND: This pin must be tied to ground.

Vee

POWER:

+ 5V power input: + 5V ± 10%.

NO CONNECTION.

OACK

DMA ACKNOWLEDGE: Input signal from the 8257 OMA Controller
acknowledging that the requested OMA cycle has been granted.

ORO

DMA REQUEST: Output signal to the 8257 OMA Controller requesting
aOMAcycle.

SRO

SERVICE REQUEST: Interrupt to the CPU indicating that the 8294A is
awaiting data or commands at the input buffer. SRO = 1 implies IBF

OAV

OUTPUT AVAILABLE: Interrupt to the CPU indicating that the 8294A
has data or status available in its output buffer, OAV = 1 implies OBF

=1.
NO CONNECTION.

3-53

inter

8294A

Table 1. Pin Description (Continued)
Symbol

Pin
No.

P6
PS
P4
P3
P2
P1
PO

33
32
31
30
29
28
27

VDD

Type

Name and Function
OUTPUT PORT: User output port lines. Output lines available to the
user via a CPU command which can asset selected port lines. These
lines have nothing to do with the encryption function. At power-on,
each line is in a1 state.

POWER:

+ SV power input. (+ SV ± 10%) Low power standby pin.

Vee

CCMP

NO CONNECTION.

POWER: Tied high.

CONVERSION COMPLETE: Interrupt to the CPU indicating that the
encryption/decryption of an 8-byte block is complete.

FUNCTIONAL DESCRIPTION

RD
1
0
1
0
X

OPERATION
The data conversion sequence is as follows:
1) A Set Mode command is given, enabling the desired interrupt outputs.
2) An Enter New Key command is issued, followed
by 8 data inputs which are retained by the DEU
for encryption/decryption. Each byte must have
odd parity.
3) An Encrypt Data or Decrypt Data command sets
the DEU in the desired mode.

WR . CS
0
1
0
1
X

0
0
0
0
1

0
0
1
1
X

Data Input Buffer
Data Output Buffer
Command Input Buffer
Status Output Buffer
Don't Care

The functions of each of these registers are described below.
Data Input Buffer-Data written to this register is
interpreted in one of three ways, depending on the
preceding command sequence.
1) Part of a key.

After this, data conversions are made by writing 8
data bytes and then reading back 8 converted data
bytes. Any of the above commands may be issued
between data conversions to change the basic operation of the DEU; e.g., a Decrypt Data command
could be issued to change the DEU from encrypt
mode to decrypt mode without changing either the
key or the interrupt outputs enabled.

2) Data to be encrypted or decrypted.
3) A DMA block count.
Data Output Buffer-Data read from this register is
the output of the encryption/decryption operation.

INTERNAL DEU REGISTERS

Command Input Buffer-Commands to the DEU
are written into this register. (See command summary below.)

Four internal registers are addressable by the. master processor: 2 for input, and 2 for output. The following table describes how these registers are accessed.

Status Output Buffer-DEU status is available in
this register at all times. It is used by the processor
for poll-driven command and data transfer operations.

3-S4

STATUS BIT:

7 6 S

FUNCTION:

X X X KPE CF DEC IBF OBF

intJ

8294A

OBF Output Buffer Full; OBF = 1 indicates that
output from the encryption/decryption function is available in the Data Output Buffer. It is
reset when the data is read.

This command puts the 8294A into the decrypt
mode.
4-Set Mode

Input Buffer Full; A write to the Data Input
Buffer or to the Command Input Buffer sets
IBF = 1. The DEU resets this flag when it has
accepted the input byte. Nothing should be
written when IBF = 1.
DEC Decrypt; indicates whether the DEU is in an
encrypt or a decrypt mode. DEC = 1 implies
the decrypt mode. DEC = 0 implies the encrypt mode.
After 8294A has accepted a 'Decrypt Data' or
'Encrypt Data' command, 11 cycles are required to update the DEC bit.
.
CF
Completion Flag; This flag may be used to indicate any or all of three events in the data
transfer protocol.
1) It may be used in lieu of a counter in the
processor routine to flag the end of an
8-byte transfer.
2) It must be used to indicate the validity of
the KPE flag.
3) It may be used in lieu of the CCMP interrupt
to indicate the completion of a DMA operation.
KPE Key Parity Error; After a new key has been
entered, the DEU uses this flag in conjunction
with the CF flag to indicate correct or incorrect parity.
IBF

OPCODE:
MSB
where:
A is the OAV (Output Available) interrupt enable
B is the SRO (Service Request) interrupt enable
C is the DMA (Direct Memory Access) transfer enable
D is the CCMP (Conversion Complete) interrupt
enable
This command determines which interrupt outputs
will be enabled. A "1" in bits A, B, or D will enable
the OAV, SRO, or CCMP interrupts respectively. A
"1" in bit C will allow DMA transfers. When bit C is
set the OAV and SRO interrupts should also be
enabled (bits A, B = 1). Following the command
in which bit C, the DMA bit, is set, the 8294 will
expect one data byte to specify the number of
8-byte blocks to be converted using DMA.

5 - Write to Output Port
OP CODE:

101
MSB

1010101010101
LSB

This command is followed by 8 data byte inputs
which are retained in the key buffer (RAM) to be
used in encrypting and decrypting data. These data
bytes must have odd parity represented by the LSB.

The timing sequence for entering a new key is
shown in Figure 3. A flowchart showing the CPU
software to accommodate this sequence is given
in Figure 4.

;-1o""l-o-'I--r---'-I-o"'-1-0-'-1-0r-I0-'1
MSB

After the Enter New Key command is issued, 8
data bytes representing1he new key are written to
the data input buffer (most significant byte first).
After the eighth byte is entered into the DEU, CF
goes true (CF = 1). The CF bit goes false again
when KPE is valid. The CPU can then check the
KPE flag. If KPE = 1, a parity error has been detected and the DEU has not accepted the key.
Each byte is checked for odd parity, where the
parity bit is the LSB of each byte.

LSB

This command puts the 8294A into the encrypt
mode.

3 - Decrypt Data
OPCODE:
MSB

PROCESSOR/DEU INTERFACE
PROTOCOL
ENTERING A NEW KEY

2 - Encrypt Data
OP CODE:

LSB

This command causes the 7 least significant bits
of the command byte to be latched as output data
on the 8294 output port. The initial output is
1111111. Use of this port is independent of the
encryption/ decryption function.

Enter New Key

OPCODE:

. '11-rI-P6-rI-Ps-rl-p4-rIPs- rIP2-'I-p-'1I"p""o1
MSB

COMMAND SUMMARY

LSB

3-55

inter

8294A

ENCRYPTING OR DECRYPTING DATA
IBF

~ ___

Jl,---_

=oJ

KPE _ _ _ _ _ _'N_V_AL_'D_ _ _ _ _

.,.IL-l..f"-L.J----U------- IL
CHECKLr
KPE

NEW

r;;;I r;E;- -

U DATA U DATA

-lJ KEY

DATA

KEY
COMMAND

210465-3

Figure 3. Entering a New Key

Since CF
1 only for a short period of time after
the last byte is accepted, the CPU which polls the
CF flag might miss detecting CF = 1 momentarily.
Thus, a counter should be used, as in Figure 4, to
flag the end of the new key entry. Then CF is used to
indicate a valid KPE flag.

Figure 5 shows the timing sequence for encrypting
or decrypting data. The CPU writes a data bytes to
the DEU's data input buffer forencryption/decryption. CF then goes true (CF =1) to indicate that the
DEU has accepted the a-byte block. Thus, the CPU
may test for IBF = 0 and CF = 1 to terminate the
input mode, or it may use a software counter. When
the encryption/decryption is complete, the CCMP
and OAV interrupts are asserted and the OBF flag is
set true (OBF = 1). OAV and OBF are set false
again after each of the converted data bytes is read
back by the CPU. The CCMP interrupt is set false,
and remains false, after the first read. After a bytes
have been read back by the CPU, CF goes false (CF
= 0). Thus, the CPU may test for CF = 0 to termi·
nate the read mode. Also, the CCMP interrupt may
be used to initiate a service routine which performs
the next series of a data reads and a data writes.
Figure 6 offers two flowcharts outlining the alternative means of implementing the data conversion pro·
tocol. Either the CF flag or a software counter may
be used to end the. read and write modes.
SRQ = 1 implies IBF =0, OAV = 1 implies OBF =
1. This allows interrupt routines to do data transfers
without checking status first. However, the OAV
service routine must detect and flag the end of a
data conversion.
r---I
IL_ _ _ _ _ _ _...JI
IL_ _ __

CCMPI
{lFENABlEDI

Jl'--_ _ _ _ _ _ __
.JLfL_Jl'----_ __
nIl -----

sRalU

(lFENABlEDI

IB'

OATA REGISTER

1 BYTe OF KEY
aAV
(IF ENABLEDI

1-1+1

I IL_

~rr

aa'

8 DATA WRITES

m. _ MAXIMUM

8 DATA READS

210465-5

Figure 5. Encrypting/Decrypting Data
210465-4

Figure 4. Flowchart for Entering a New Key

3-56

8294A

USING DMA

USING SOFTWARE COUNTER

The timing sequence for data conversions using
DMA is shown in Figure 7. This sequence can be
better understood when considered in conjunction
with the hardware DMA interface in Figure 8. Note

IIFEN;;l~~ 1_......J~________________.....Ir
CF

1-1+1
SRO

IIFENAOLEDI

=rlL..._ _ _ _-----.J1
LnILJ --l
' - - _ - ' - -_ _ _ _ _ __

IL_JL
DAQ~-Lr1 __ JL
OAV

CACK

-U-ULr--U-

LJ--U-

w.1nJlJh1J
SET
DMA

MODE

DMA

8 DMA READS
B DMA WRITES
BLOCI'.:
COUNT
In) _ _ _ _ _ _ _ _ _ _ _ __

210465-6
210465-8
USING CF FLAG

IBF

= O?

DATA REGISTER - 1 DATA BYTE

lVES
NO

Figure 7. DMA Sequence

8257

CF = 11 )
YES

~8
'---r;;o"

~
~
I

READ 1 CODED DATA BYTE

I
210465-7

Figure 6. Data Conversion Flowcharts
00----_(1:

AD====~~

210465-9

Figure 8. DMA Interface

3-57

8294A

that the use of the DMA feature requires 3 external
AND gates and 2 DMA channels (one for input, one·
for output). Since the DEU has only one DMA request pin, the SRO and OAV outputs are used in
conjunction with two of the AND gates to create separate DMA request outputs for·the 2 DMA channels.
The third AND gate combines the two active-low
DACK inputs.
To initiate a DMA transfer, the CPU must first initialize the two DMA channels as shown in the flowchart
in Figure 9. It must then issue a Set Mode command
to the DEU enabling the OAV, SRO, and DMA outputs. The CCMP interrupt may be enabled or disabled, depending on whether that output is desired.
Following the Set Mode command, there must be a
data byte giving the number of 8-byte blocks of data
(n < 256) to be converted. The DEU then generates
the required number of DMA requests to the 2 DMA
channels with no further CPU intervention. When the
requested number of blocks has been converted,
the DEU will set CF and assert the CCMP interrupt (if
enabled). CCMP then goes false again with the next
write to the DEU (command or data). Upon completion of the conversion, the DMA mode is disabled
and the DEU returns to the encrypt/decrypt mode.
The enabled interrupt outputs, however, will remain
enabled until another Set Mode command is issued.

SINGLE BYTE COMMANDS
Figure 10 shows the timing and protocol for single
byte commands. Note that any of the commands is
effective as a pacify command in that they may be
entered at any time, expect during a DMA conversion. The DEU is thus set to a known state. However, if a command is issued out of sequence, an additional protocol is required (Figure 11). The CPU must
wait until the command is accepted (IBF = 0). A
data read must then be issued to clear anything the
preceding command sequence may have left in the
Data Output Buffer.

SRQ

UF ENABLED)

__________~n~______~

u
u

AO __________

~rl~

___________

.----S(

USING DMA

COMMAND REGISTER -COMMAND

INITIALIZE OMA READ CHANNEL POINTER

INITIALIZE OMA WRITE CHANNEL POINTER

8
COMMAND REGISTER - - OEH OR OFH

210465-11

Figure 10. Single Byte Commands
DATA REGISTER -

CPU/DEUINTERFACES

NUMBER OF BLOCKS TO BE COOED

~
~

Figures 12 through 15 illustrate four interface configurations used in the CPU/DEU data transfers. In all
cases SRO will be true (if enabled) and IBF will be
false when the DEU is ready to accept data or commands.
.

210465-10

Figure 9_ DMA Flowchart

3-58

inter

8294A

PACIFY

INT1:====================4-

INT2

MASTER
PROCESSOR

INTERFACE

D'¢¢
D, •

SRa

I\li--82941.
DEU

WR--

cs--_

..---

COMMAND REGISTER _

CAV

210465-15

DOH

Figure 14. Dual Interrupt Interface

READ DATA REGISTER

8257

210465-12 .

Figure 11. Pacify Protocol

INTERFACE TO 8086,

(g:'<=C>G

B088'1 AD -.--

~~~OE:O:~O~::sg:

Wii. - - -

B294A
DEU

cs--AD

iNT-------oc:!l

RD _________

210465-13

Wii-------------.q

Figure 12. Polling Interface

210465-16
DMARO is for memory to DEU Data Transfer
DMAR1 is for DEU to memory Data Transfer
Use of CCMP is optional

mr------------------------,

Figure 15. DMA Interface
MASTER
PROCESSOR

OSCILLATING AND TIMING CIRCUITS

INTERFACE
8294A
DEU

AD - - -

The 8294A's internal timing generation is controlled
by a self-contained oscillator and timing circuit.. A
choice of crystal, L-C or external clock can be used
to derive the baSic oscillator frequency.

CCMPf---IO<:)O---'

210465-14

The resident timing circuit consists of an oscillator; a
state counter and a cycle counter as illustrated in
Figure 16.

Figure 13. Single Interrupt Interface

3-59

inter

8294A

SYNC

1-.....4--0UTPUT
(1.25-15 "sec)

'---v------'
INTERNAL TIMING

210465-17

Figure 16. Oscillator Configuration

OSCILLATOR MODE

LC OSCILLATOR MODE

1
1 = 21TJ[C'

C1
XTAL'
r _.•ft---r---.-----I
I
~.83-'2
!

_.L_
C2

rl
"::'
C3

C +3 Cpp
2
Cpp = 5-10 pF
Pin-to-Pin
Capacitance

MHz

I'rc::::J

l(I-~I~~~~
3 XTAl2

I\"

210465-19

__
C_

210465-18
Cl = 5 pF
C2 = Crystal + Stray < 15 pF
C3 = 20-30 pF
Crystal series resistance should be less than 75n at 6 MHz; less
than 180n at 3.6 MHz; less than 300 at 12 MHz.

Nominal

20pF
1'.5MHz
20pF
5.2 MHz
20pF
3.2 MHz
Each C should be approximately 20 pF
including stray capacitance.

Figure 17. Recommended Crystal·

DRIVING FROM EXTERNAL SOURCE-TWO OPTIONS
+5.

,----.....:.j

XlAL ,

+5.

»--.......1---"-1 XTAl2
210465-20
For the 8294A XTAL2 must be high 35-65% of the period.
Rise and fall times must not exceed IOns.
Resistor to Vee is needed to ensure VIH = 3.0V if TTL circuitry is used.

Figure 18. Recommended Connection for External Clock Signal

3-60

intJ

8294A

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

AmbientTemperature Under Bias .... O'C to + 70'C

Storage Temperature .......... -65'C to + 150'C
Voltage on Any Pin With
Respect to Ground .............. - 0.5V to + 7V
Power Dissipation ....................... 1.5 Watt

D.C. AND OPERATING CHARACTERISTICS
= O'Cto +70'C, Vee = +5V ±10%, vss = OV

Symbol

Limits

Parameter
Min

Typ

Unit

Test Conditions

Max

VIL

Input Low Voltage (All
Except X1, X2, RESET)

-0.5

0.8

VIL1

Input Low Voltage (X1' X2,
RESET

-0.5

0.6

VIH

Input High Voltage (All
Except X1, RESET)

2.0

Vee

VIH1

Input High Voltage (X1'
RESET

3.5

Vee

VIH2

Input High Voltage (X2)

2.2

Vee

VOL

Output Low Voltage (00-07)

0.45

IOL

Vou

Output Low Voltage (All
Other Outputs)

0.45

IOL

VOH

Output High Voltage (00-07)

2.4

IOH

VOH1

Output High Voltage (All
Other Outputs)

2.4

IOH

IlL

Input Leakage Current
(RO, WR, CS, Ao)

±10

p.A

Vss :::;; VIN :::;; Vee

IOFL

Output Leakage Current
(00-07, High Z State)

±10

p.A

Vss + 0.45 :::;; VOUT :::;; Vee

100

Voo Supply Current

100 + lee

Total Supply Current

135

Low Input Load Current
(Pins 24, 27 -38)

0.3

VIL

= 0.8V

IU1

Low Input Load Current
(RESET)

0.2

VIL

= 0.8V

IIH

Input High Leakage Current
(Pins 24, 27 -38)

100

p.A

VIN

= Vee

CIN

Input Capacitance

CliO

1/0 Capacitance

3-61

= 2.0 mA
= 1.6 mA
= -400 p.A
= -50 p.A

inter

8294A

A.C. CHARACTERISTICS

TA = O·Cto +70·C, vcc = voo = +5V ±10%, vss = ov

DBB READ
Symbol

Parameter

Min

tAR

CS, Ao Setup to RD !

tRA

CS, Ao Hold After RD

tRR

RD Pulse Width

tAD

CS, Ao to Data Out Delay

tRO

tOF

tCY

Cycle Time

!
t

Max

Unit

160

Test Conditions

=
=

130

to Data Out Delay

130

to Data Float Delay

,""S

1-12 MHz Crystal

Max

Unit

Test Conditions

1.25

100 pF
100 pF

DBB WRITE
Symbol

Parameter

Min

tAW

CS, Ao Setup to WR

tWA

CS, Ao Hold After WR

tww

WR Pulse Width

tow

Data Setup to WR

two

Data Hold to WR

t
t

160

130

DMA AND INTERRUPT TIMING
Symbol

Parameter

Min

tACC

DACK Setup to Control

tCAC

DACK Hold After Control

tACO

DACK to Data Valid

Max

Unit

Test Conditions

ns
ns
130

tCRQ

Control L.E. to DRQ T.E.

110

tCI

Control T.E. to Interrupt T.E.

400

100 pF

CLOCK
Symbol

Min

Max

Units

tCY

Cycle Time

1.25

9.20

,""s(1)

tCYC

Clock Period

83.3

613

tPWH

Clock High Time

Clock Low Time

tPWL

Parameter

ns
ns

Clock Rise Time

Clock Fall Time

NOTE:
1. ICY = 15/f(XTAL)

3-62

inter

8294A

A.C. TESTING INPUT, OUTPUT WAVEFORM
2.4

2.0

TEST POINTS

0.8

0.45

2.0

0.8

210465-21

WAVEFORMS
READ OPERATION-OUTPUT BUFFER REGISTER
Cs OR Ao

]

X
,

~IAR-i
IRR

~~
(OUTPUn

-tRA--l

(SYSTEM'S
ADDRESS BUS)

-IAO-----

(A EAD CONTROL)

-IOF-

~~~-IAD---

------------< ~--DATAVALtD---~------------210465-22

WRITE OPERATION-INPUT BUFFER REGISTER
CS OR Ao

------','xrf

1''---------------

(SYSTEM'S

ADDAESS BUS,

_~IAW-~~. IWW--U_IWAWA

DATA BUS
DATA
(IN Pun _ _ _ _....:M:::A:..:y..:C::.,:H;::AN:.:G:.:E_ _ _--J

~-,ow_--n~-ltwD
_~_ DATA YALlD--

(WRITE CONTROL)

DATA

1 ' - - - - - - - - r - '-_ _ _ _ _...;M:::;A.:..;y...:C::.;H"'AN:.:;G::.:E'--_ _ _ __
210465-23

3-63

intJ

8294A

DMA AND INTERRUPT TIMING
O / ( O K - - - -.....

I
-

tCAe

RDorWR -----t-----.....

.....

ORa-----t---~-----ICRQ

DATA

B U S - - - - - f - - - - - - -___......
VALID

OAVorSRQ-----t----------,.----____f-___,
210465-24

CLOCK TIMING

2.4Y -

XTAL2

1.8Y _ _ _ _ _ _ _

.....l..I.::===-==Ll

.4SY-

210465-25

3-64

APPLICATION
NOTE

AP-166

October 1990

Using the 8291A GPIB
Talker /Listener

Order Number: 230832-001
3-65

USING THE 8291A GPIB
TALKER/LISTENER

CONTENTS

PAGE

INTRODUCTION ........................ 3-67
OVERVIEW OF IEEE 488/GPIB ........ 3-68
Interface Functions ...................... 3-68
Electrical Signal Lines ................... 3-68
Transfer Control Lines ................... 3-70
Bus Commands ......................... 3-70
Addressing Techniques .................. 3-70
INTEL'S

GPIB COMPONENTS ....... 3-70

Overview of the 8291A GPIB Talkerl
Listener ............................... 3-71
Address Mode .......................... 3-72
APPLICATION OF THE 8291A ......... 3-73
Talker Functions ........................ 3-73
Addressed Talker (via MTA Message) ... 3-73
LISTENER FUNCTIONS ................ 3-73
Addressed Listening (via the MLA
Message) ............................. 3-73
Remote/Local and Lockout .............. 3-73
Polling .................................. 3-74
Serial Poll ............................... 3-74
Parallel Poll ............................. 3-76
APPLICATION EXAMPLES ............. 3-77
Two Software Drivers .................... 3-77
8291A with HP 9835A ................... 3-77
CONCLUSION .......................... 3-78
REFERENCES .......................... 3-78
APPENDIX A: SYSTEM BLOCK
DIAGRAM WITH 8088 ................ 3-79
APPENDIX B: SOFTWARE DRIVERS
FOR BLOCK DATA TRANSFER ...... 3-80
APPENDIX C: SOFTWARE FOR HP
9835A ................................ 3-88
APPENDIX D: SOFTWARE FOR HP
8088/HP 9835A VIA GPIB ............ 3-89

3-66

AP-166

INTRODUCTION
This application note explains the Intel 8291A GPIB
(General Purpose Interface Bus) Talker/Listener as a
component, and shows its use in GPIB interface design
tasks.

DEVICE A
ABLE TO
TALK, LISTEN,
AND
CONTROL

The first section of this note presents an overview of
IEEE 488 (GPIB). The second section introduces the
Intel GPIB component family. A detailed explanation
of the 8291A follows. Finally, some application examples using the component family are presented.

II D

r--'----<

DATA BUS

(e.g. calculalor)

DEVICE B
ABLE TO
TALK AND
LISTEN

I---'

(e.g. digital
multimeter)

DATA BYTE
TRANSFER
CONTROL

(....- rDEVICEC
ONLY ABLE
TO LISTEN

r-----<

(e.g. signal
generalor)
GENERAL
INTERFACE
MANAGEMENT

-I-

(
DEVICE D
ONLY ABLE
TO TALK

I---

(e.g. counler)

} 010 1 ... 8

Data InpuVOulpul

DAV

Data Available

NRFD
NDAC

Nol Ready lor Data
Nol Data Accepled

IFC

Inlerlace Clear

ATN

AHenlion

SRQ

Service Requesl

REN

Rem ote Enable

EOI

End or Idenlily

230832-1

Figure 1. Interface Capabilities and Bus Structure

3-67

intJ

AP-166

OVERVIEW OF IEEE 488/GPIB

Electrical Signal Lines

The GPIB is a parallel interface bus with an asynchrQnQUS interlocking data exchange handshake mechanism. It is designed to, provide a CQmmQn cQmmunicatiQn interface amQng devices .over a maximum distance
.of 20 meters at a maximum speed .of 1 Mbps. Up to 15
devices may be cQnnected tQgether. The asynchrQnQus
interlQcking handshake dispenses with a CQmmQn synchronizatiQn clQck, and allQws intercQmmunicatiQn
amQng devices capable .of running at different speeds.
During any transactiQn, the data transfer .occurs at the
speed .of the slQwest device invQlved.

As shQwn in Figure I, the,GPIB is cQmpQsed .of eight
data lines (008-001), five interface management lines
(IFC, ATN, SRQ, REN, EOI), and three transfer CQntrol lines (DAY, NRFD, NDAC) .
The eight data lines are used tQ transfer data and CQmmands frQm .one device tQ another with the help .of the
management and contrQl lines. Each .of the five interface management lines has a specific functiQn.
ATN (attentiQn) is used by the CQntroller tQ indicate
that it (the cQntroller) has access tQ the GPIB and that
its .output .on the data lines is tQ be interpreted as a
command. ATN is alsQ used by the cQntrQller alQng
with EOI to indicate a parallel PQll.

The GPIB finds use in a diversity .of applications requiring cQmmunicatiQn amQng digital devices .over
short distances. CQmmQn examples are: programmable
instrumentatiQn systems, cQmputer tQ peripherals, etc.

SRQ (service request) is used by a device to request
service frQm the contrQller.

The interface is cQmpletely defined in the IEEE
STD.-488-1978.

REN (remQte enable) is used by the cQntrQller tQ specify the cQmmand SQurce .of a device. A device can be
issued cQmmands either lQcally thrQugh its front panel
.or by the controller.

A typical implementatiQn cQnsists of lQgical devices
which talk (talker), listen (listeners), and cQntrQl GPIB
activity (cQntrollers).

Interface Functions
The interface between any device and the bus may have
a cQmbination .of several different capabilities (called
'functiQns'). AmQng a total .of ten functiQns defined, the.
Talker, Listener, SQurce Handshake, Acceptor Handshake and CQntroller are the mQre CQmmQn examples.
The Talker functiQn allQws a device tQ transmit data.
The Listener fUlictiQn allQws reception. The Source and
AcceptQr Handshakes, synchronized with the Talker
and Listener functiQns respectively, exchange the handshake signals that cQQrdinate data transfer. The CQntroller functiQn allQws a device tQ activate the interface
functiQns' .of the various devices thrQugh cQmmands.
Other interface functiQns are: Service request, RemQte
lQcal, Parallel PQll, Device clear and Device trigger.
Each interface may nQt cQntain all these functiQns: Further, most .of these functiQns may be implemented tQ
variQus levels (called 'subsets') .of capability. Thus, the
.overall capability .of an interface may be tailQred tQ the
needs .of the cQmmunicating device.

EOI (end .or identify) may be used by the cQntrQller as
well as talker. A cQntroller uses EOI alQng with ATN
tQ demand a parallel PQll. Used by a talker, EOI indicates the last byte .of a data blQck.
IFC (interface clear) fQrces a cQmplete GPIB interface
tQ the idle state. This CQuld be cQnsidered the GPIB's
"interface reset." GPIB architecture allQws fQr more
than .one cQntroller to be connected tQ the bus simultaneQusly. Only .one .of these cQntrQllers may be in CQmmand at any given time. This device is knQwn as the
cQntroller-in-charge. CQntrol can be passed frQm .one
cQntrQller tQ anQther. Only .one amQng all the controllers present .on a bus can be the system cQntroller. The
system cQntrQller is the .only device allQwed tQ drive
IFC.

3-68

infef

AP-166

NRFD SIGNAL LINES GOES HIGH

YES

r-_ _,,-_ _.,ONLY WHEN ALL ACCEPTORS ARE READY
DATA IS VALID AND MAY
NOW BE ACCEPTED

DATA IS NOT TO BE CONSIDERED
VALID AFTER THIS TIME

SETNDACLOW

230832-2

NOTE:
Flow diagram outlines sequence of events during transfer of data byte. More than one listener at a time can accept data
because of logical connection of NRFD and NDAC lines.

Figure 2. Handshake Flowchart

3·69

inter

AP-166

Transfer Control Lines
The transfer control lines conduct the asynchronous interlocking three-wire handshake.
.
DAV (data valid) is d.riven by a talker and indicates
that valid data is on the bus.
NRFD (note ready for data) is driven by the listeners
and indicates that not all listeners are ready for more
data.
NDAC (not data accepted) is used by the listeners to
indicate that not all listeners have read the GPIB data
lines yet.
The asynchronous 3-wire handshake flowchart is.
shown in Figure 2. This is a concept fundamental to the
asynchronous nature of the GPIB and is reviewed in
the following paragraphs. .
Assume that a talker is ready to start a data transfer.
At the beginning of the handshake,lIlRFD is false indicating that the Iistener(s).is ready for data. NDAC is
true indicating that the Iistener(s) has not accepted the
data, since no data has been sent yet. The talker places
data on the data lines, waits for the required settling
time, and then indicates valid data by driving DAV
true. All active listeners drive NRFD true htdicating
that they are not ready for more data. They then read
the data and drive NDAC false to indicate acceptance.
The talker responds by deasserting DAV and readies
itself to transfer the next byte. The listeners respond to
DAV false by driving NDAC true. The tlilker can now
drive the data lines with a new data byte and wait for
NRFD to be false to start the next handshake cycle.

Bus Commands
When ATN and DAV are true data patterns which
have been placed by the controller on the GPIB, they
are interpreted as comnuinds by' the other devices on
the interface. The GPIB standard contains a repertory
of commands such as MTA (My Talk Address), MSA
(My Secondary Address), SPE (Serial ~oll Enable), etc.
All other patterns in conjunction with ATN and DAV
are classified as undefined commands and'their meaning is user-dependent.

Addressing Techniques
To allow the controller to issue commands selectively
to specific devices, three types. of addressing exist on the
GPIB: talk only/listen only (ton/lon), primary, and
secondary.
.

Ton/Ion is a method where the ability of the GPIB
interface to talk or listen is determined by the device
and not by the GPIB controller. With this method,
'fixed poles can be easily designated in simple systems
where reassignment is not necessary. This is appropriate and convenient for certain applications. For example, a logic analyzer might by interfaced via the GPIB
to a line printer in order to document some type of
failure. In this case, the line printer simply listens to the
logic analyzer, which is a talker.
The controller addresses devices through three commands, MTA (my talk address), MLA (my listen address), and MSA (my secondary address). The device
address is imbedded iii the command bit pattern. The
device whose address matches the imbedded pattern is
enabled. Some devices may have the same logical talk
and listen addresses. This is allowable since the talker
and listener are separate functions. However, two of the
same functions cannot have the same address.
In primary addressing, a device is enabled to talk' (listen) by receiving the MTA (MLA) message.
. .
Secondary addressing extends the address field from 5
to 10 bits by allowing an additional byte. This ac;lditionaI byte is passed via the MSA message. SecOndary addressing can also be used to logically divide devices into
various subgroups. The MSA message applies only to
the device(s) whose primary address immediately precede it.
.

INTEL'S® GPIB COMPONENTS
The logic designer implementing a GPIB interface has,
in the past, been faced with a difficult and complex
discrete logic design. Advances in LSI technology have
produced sophisticated microprocessor and peripheral
devices which combine to reduce this once complex interface task to a system consisting of a small ~et of
integrated circuits and some software drivers. A microprocessor hardware/software solution and a high-level
language source code provide an additional benefit in
end-product maintenance. Product changes are a simple matter of revising the product software. Field
changes are as easy as exchanging EPROMS.
Intel has provided an LSI solution to GPIB interfacing
with a talkerllistener device (829IA), a controller device (8292), and a transceiver (829,3). An interface with
all capabilities except for the controller function can be
. built with an 829lA and a pair 0(8293's. The addition
of the 8292 produces a complex· interface. Since most
devices in a GPIB system will not have the controller
function capability, this modular approach provides the
least cost to the majority of interface designs.

3-70

AP-166

Current states of the 8291A can be determined by examining the device's status read registers. In addition,
the 8291A contains 8 write registers. These registers are
shown in Figure 3. The three register select pins RS3RSO are used to select the desired register.

Overview of the 8291 A
GPIB Talker/Listener
The'Intel 829lA GPIB Talker/Listener operates over a
clock range of 1 to 8 MHz and is compatible with the
MCS-85, iAPX-86, and 8051 families of microprocessors.

The data-in register moves data from the GPIB to the
microprocessor or to memory when the 8291 A is addressed to listen. When the 8291A is addressed to talk,
it uses the data-out register to move data onto the
GPIB. The serial poll mode and status registers are
used to request service and program the serial poll
status byte.

A detailed description of the 8291A is given in the data
sheet.
The 8291A implements the following functions: Source
Handshake (SH), Acceptor Handshake (AH), Talker
Extended (TE), Service Request (SRQ), Listener Extended (LE), Remote/Local (RL), Parallel Poll (PP2),
Device Clear (DC), and Device Trigger (DT).

Read Registers

I I
DI7

DI6

A detailed description of each of the registers, along
with state diagrams can be found in the 8291A data
sheet.

DIS I DI4

DI3

DI2

DI1

DIO I 0

Write Registers

D071 8061 DOS I D04 I D03 I D02 I D01 I DOO I

DATA IN

DATA OUT

CPT I APT I GET I END I DEC I ERR I BO

I 0

CPT I APT I GET I END I DEC I ERR I BO

INTERRUPT STATUS 1

liNT I SPAS I LLO I REM I SPC I LLOC I REMC I ADSC I 0

I DMAO I DMAI I SPC I LLOC I REMC I ADSC

INTERRUPT STATUS 2
S8 I SRQS I S6 I SS I S4 I S3 I

I Lon I EOI I LPAS I TPAS I

I TO

S8 I RSV I

LA I TA I MJMNI 1

ADDRESS STATUS

CPT71 CPT61 CPTsl CPT41 CPT31 CPT2 1 CPT1 I CPTO

SS I S4
S3
I
I
SERIAL POLL MODE

0
0
0
I
I
I
ADDRESS MODE

I ADM1 I ADMO I

CNT21 CNT1 I CNTO I COM41 COM31 COM21 COM1 I COMO I
AUXMODE

liNT I DTO I DLO IADS.oIAD4-0IAD3-0IAD2.0IAD1.ol 1

ARS I DT

ADDRESS 0
X

COMMAND PASS THROUGH

INTERRUPT ENABLE 2

SERIAL POLL STATUS 2

I ton

INTERRUPT ENABLE 1

DL I ADS I AD4 I AD3 I AD2 I AD1

ADDRESS 0/1

I DT1 I DL 1 I ADS-11 AD4.11 AD3-11 AD2-11 AD1-11

I EC7 I EC61

ADDRESS 1

ECS I EC4 I EC3 I EC2 I EC1 I ECO
EOS

Figure 3. 8291A Registers

3-71

AP-166

address 1 registers allow reading of these programmed
addresses plus trading of the interrupt bit. The EOS
register is used to program the end of sequence character.

Address Mode
The address mode and status registers are used to program the addressing modes and track addressing st!ltes.
The auxiliary mode register is used to select a variety of
functions.- The command pass through register is used
for undefined commands and extended addresses. The
address 0/1 register is used to program the addresses to
which the 8291A will respond. The address 0 and

Detailed descriptions of the addressing modes available
with the 8291A are described in the 8291A data sheet.
Examples of how to program these modes are shown
below.

1. MODE: Talker has single address of 01 H
Listener has single address of 02H
CPU Writes to:

Pattern

. Comment

Address Mode Register
Address 0/1 Register
Address 0/1 Register

0000 0001
0010 0001
1100 0010

Select Mode 1 Addressing Major is Talking. Address = 01H
Minor is Listener. Address = 02H

2. MODE: Talker has single address of 01 H
Listener has single address of 02H

CPU Writes to:

Pattern

Comment

Address Mode Register
Address 0/1 Register
Address 0/1 Register

0000 0001
0100 0010
1010 0001

Select Mode 1 AddreSSing
Major is Lil;tener. Address = 02H
Minor is Talking. Address = .01 H

Note that in both of the above examples, the listener will respond to a MLA message with five least significant bits
equal to 02H and the talker to a OIH.
. 3. MODE: Talker and listener both share a single address of 03H

CPU Writes to:

Pattern

Comment

Address Mode.Register
Address 0/1 Register
Address 0/1 Register

00000001
0000 0011
11100000

Select Mode 1 AddreSSing
Talker and Listener Address = 03
Minor Address is disabled

4. MODE: Talker and listener have a primary address of 04H and a secondary address of OSH
CPU Writes to: .

Pattern

Comment

Address Mode Register
Address 0/1 Register
Address 0/1 Register

0000 0010
0000 0100
1000 0101

Select Mode 2 AddreSSing
Primary Address =; 04H
Minor Address is disabled

5. MODE: Talker has a primary address of 06H. Listener has a primary address of 07H

CPU Writes to:

P$ttern

Comment

Address Mode Register
Address 0/1 Register
Address 0/1 Register

0000 0011
0010 0110
11000111

Select Mode 3
Talker Address = 06
Listener Primary = 07

The CPU will verify the secondary addresses which could be the same or different.

3-72

inter

AP-166

APPLICATION OF THE 8291A

LISTENER FUNCTIONS

This phase of the application note will examine programming of the 8291A, corresponding bus commands
and responses, CPU interruption, etc. for a variety of
GPIB activities. This should provide the reader with a
clear understanding of the role of the 8291A performs
in a GPIB system. The talker function, listener function, remote message handling, and remote/local operations including local lockout, are discussed.

LISTEN-ONLY (Ion). In listen-only mode the 8291
will not respond to the My Listen Address (MLA) message from the controller. The sequence of events is as
follows:
I) The Interrupt Enable registers are programmed.
2) Lon is selected.
3) EOS character is programmed.
4) "Pon" local message is sent.
5) CPU waits for BI and reads the byte from the datain register;

Talker Functions

Note that enabling both ton and Ion can create an internal loopback as long as another listener exists.

TALK-ONLY (ton). In talk only mode the 8291A will
not respond to the MTA message from a controller.
Generally, ton is used in an environment which does
not have a controller. Ton is also employed in an interface that includes the controller function.

Addressed Listening
(via the MLA Message)

When the 8291A is used with the 8292, the sequence of
events for initialization are as follows:
I) The Interrupt/Enable registers are programmed.
2) Ton is selected.
3) Settling time is selected.
4) EOS character is loaded.
5) "Pon" local message is sent.
6) CPU waits for Byte Out (BO) and sends a byte to
the data out register.

The GPIB controller will direct the 8291A to listen by
sending a MLA message containing the 8291A's listen
address. The sequence of events is as follows:
I) The Interrupt Enable registers are programmed.
2) The serial poll mode register is loaded as desired.
3) Talker and listener addresses are loaded;
4) "Pon" local message is sent.
5) The CPU waits for an interrupt. When the controller has sent the MLA message for the 8291A, the
ADSC bit will be set.
6) The CPU reads the Address Status Register to determine if the 8291A has been addressed to listen
(LA = I).
7) CPU waits for an interrupt for BI or ADSC.
8) When BI is set, the CPU reads the data byte from
the data-in register.
9) The CPU continues to poll the status registers.
10) When unaddressed, ADSC will be set and LA reset.

Addressed Talker (via MTA Message)
The GPIB controller will direct the 8291A to talk by
sending a My Talk Address (MTA) message containing
the 8291A's talk address. The sequence of events is as
follows:
I) The interrupt enable and serial poll mode registers
are programmed.
2) Mode I is selected.
3) Settling time is selected.
4) Talker and listener addresses are programmed.
5) Power on (pon) local message is sent.
6) CPU ~aits for an interrupt. When the controller
has sent the MTA message for the 8291A an interrupt will be generated if enabled and the ADSC bit
will be set.
7) CPU reads the Address Status register to determine
if the 8291A has been addressed to talk (TA = 1).
8) CPU waits for an interrupt from either BO or
ADSC
9) When BO is set, the CPU writes the data byte to
the data out register.
10) CPU continues to poll the status registers.
11) When u~addressed ADSC, will be set andTA reset.

Remote/Local and Lockout
Remote and local refer to the source of control of a
device connected to the GPIB. Remote refers to control
from the GPIB controller-in-charge. Local refers to
control from the device's own system. Reference should
be made to the RL state diagram in the 2891A data
sheet.
.
Upon "pon" the 8291A is in the local state. In this state
the REM bit in Interrupt Status I Register is reset.
When the GPIB controller takes control of the bus it
will drive the REN (remote enable) line true. This will
cause the REM bit and REMC (remote/local change)
bit to be set. The distinction between remote and local
modes is necessary in that some types of devices will
have local controls which have functions which are also
controlled by remote messages.

3-73

inter

AP-166

These two methods are called Serial and Parallel Poll.
The controller performs one of these two polling methods after a slave device requests service. As implied in
the name, a Serial Poll is when the controller sequentially asks each device if it requested service. In a Paral~
lei Poll the controller asks all of the devices on the
GPIB if they requested service, and they reply in parallel.

In the local state the device is allowed to store, but not
respond to, remote messages which control functions
which are also controJled by local messages. A ,device
which has been addressed to listen will exit the local
state and go to the remote state if the REN message is
,true and the local rtl (return to local) message is false.
The state of the "rtl" local message is ignored and the
device is "locked" into the local state if the LLO remote message is true. In the Remote state ,the device is
not allowed to respond to local messages which control
function that are also controlled by remote messages. A
device will exit the remote state and enter the local
state when REN goes false. It will also enter the local
state if the GTL (go to local) remote message is true
and the device has been addressed to listen. It will also
enter the local state if the rtl message is true and the
LLO message is false or ACDS is inactive.

Serial Poll
When the controller performs a Serial Poll, each slave
device sends back to the controller a Serial Poll Status
Byte. One of the bits in the Serial Poll Status Byte indicates whether this device requested service or not. The
remaining 7 bits are used defined, and they are used to
indicate what type of service is required. The IEEE-488
spec only defines the service request bit, however HP
has defined a few more bits in the Serial Poll Status
Byte. This can be seen in Figure 4.

A device will exit the remote state and enter RWLS
(remote with lockout state) if the LLO (local lockout)
message is true and ACDS is active. In this mode, those
local messages which control functions which are also
controlled by remote messages are ignored. In other
words, the "rtl" message is ignored. A device will exit
RWLS and go to the local state if REN goes false. The
device will exit RWLS and go to LWLS if the GTL
message is true and the device is addressed to listen.

When a slave device needs service it drives the SRQ line
on the GPIB bus true (low). For the 8291A this is done
by setting bit 7 in the Serial Poll Status Byte. The CPU
in the controller may be interrupted by SRQ or it may
poll a register to determine the state of SRQ. Using the
8292 one could either poll the interrupt status register
for the SRQ interrupt status bit, or enables SRQ to
interrupt the CPU. After the controller recognizes a
service request, it goes into the serial poll routine.

Polling
The IEEEA88 standard specifies two methods for a
slave device to let the controller know that it needs
service.

The first thing the controller does in the serial poll routine is assert ATN. When ATN is asserted true the
controller takes control of the GPIB, and all slave de-

SERVICE REQUESTED

0: SERVICE NOT REQUESTED

•

~ DEVICE DEPENDENT STATUS BITS ~
TXPICAL HP U~ 1:

NOT USED

I0:

SERVICE REQUESTED
SERVICE NOT REQUESTED

•

DEVICE DEFINED
1: OPERATION COMPLETE

BUSY

11:

ERROR

10:

NORMAL

L-.._ _ _ _~

Figure 4. The Serial Poll Status Byte

3-74

•

230832-3

inter

AP-166

vices on the bus must listen. All bytes sent over the bus
while ATN is true are commands. After the controller
takes control, it sends out a Universal Unlisten (UNL),
which tells all previously addressed listeners to stop listening. The controller then sends out a byte called SPE
(Serial Poll Enable). This command notifies all of the
slaves on the bus that the controller has put the GPIB
in the Serial Poll Mode State (SPMS). Now the controller addresses the first slave device to TALK and puts
itself in the listen mode. When the controller resets
ATN the device addressed to talk transmits to the controller its Serial Poll Status Byte. If the device just
polled was the one requesting service, the SRQ line on
the GPIB goes false, and bit 7 in the serial poll status
byte of the 8291A is reset. If more than one device is
requesting service, SRQ remains low until all of the
devices requesting service have been polled, since SRQ
is wire-ored. To continue the Serial Poll, the controller
asserts ATN, addresses the next device to talk then
reads the Serial Poll Status Byte. When the controller is
finished polling it asserts ATN, sends the univeral untalk command (UNT), then sends the Serial Poll Disable command (SPD). The flow of the serial poll can be
seen from the example in Figure S.

B. CONTROLLER RECOGNIZES SRQ AND
ASSERTS ATN

The 8292's SPI pin 33 interrupts the CPU. The CPU
reads the 8292's Interrupt status register and finds the
SRQ bit set. The CPU tells the 8292 to 'Take Control
Synchronously' by writing a OFDH to the 8292's command register.
C. THE CONTROLLER SENDS OUT THE
FOLLOWING COMMANDS: UNIVERSAL
UNLISTEN (UNL), SERIAL POLL ENABLE (SPE),
MY TALK ADDRESS (MTA)

(MTA is a command which tells one of the devices on
the bus to talk.)
The CPU in the controller waits for a BO (byte out)
interrupts in the 8291A's interrupt status 1 register before it writes to the Data Out register a 3FH (UNL),
18H (SPE), OlOXXXXX (MTA). The X represents the
programmable address of a device on the GPIB. When
the 8291A in the slave device receives its talk address,
the ADSC bit in the Interrupt Status register 2 is set,
and in the Address Status Register T A and TPAS bits
are set.

0) DEVICE A REQUESTS SERVICE (SRQ)
1) ASSERT ATN
2) UNIVERSAL UNLISTEN (UNL)
3) SERIAL POLL ENABLE (SPE)
4) DEVICE A TALK ADDRESS (MTA)
5) RELEASE ATN
6) DEVICE A STATUS BYTE (STD) (RQS SET)
7) ASSERT ATN
.
8) DEVICE B TALK ADDRESS (MTA)
9) RELEASE ATN
10) DEVICE B STATUS BYTE (STB) (RQS
CLEAR)
11) ASSERT ATN
12) DEVICE C TALK ADDRESS (MTA)
13) RELEASE ATN
14) DEVICE C STATUS BYTE (STB) (RQS
CLEAR)
IS) ASSERT ATN
16) UNIVERSAL UNTALK (UNT)
17) SERIAL POLL DISABLE (SPD)
18) GO PROCESS SERVICE REQUEST

D. CONTROLLER RECONFIGURES ITSELF TO
LISTEN AND RESETS ATN

The CPU in the controller puts the 8291 A in the listen
only mode by writing a 40H to the Address Mode register of the 8291A, and then a OOH to the Aux Mode
register. The second write is an 'Immediate Execute
pon' which must be used when switching addressing
modes such as talk only to listen only. To reset ATN
the CPU tells the 8292 to 'Go To Standby' by writing a
OF6H to the command register. The moment ATN is
reset, the 8219A in the slave device sets SPAS in Interrupt Status 2 register, and transmits the serial poll
status byte. SRQS in the Serial Poll Status byte of the
8291A slave device is reset, and the SRQ line on the
GPIB bus becomes false.
E. THE CONTROLLER READS THE SERIAL
POLL STATUS BYTE, SETS ATN, THEN
RECONFIGURES ITSELF TO TALK

Figure 5. Serial Polling

The CPU in the controller waits for the Byte In bit (BI)
in the 8291A's Interrupt Status 1 register. When this bit
is set the CPU reads the Data In register to receive the
Serial Poll Status Byte. Since bit 7 is set, this was the
device which requested service. The CPU in the controller tells the 8292 to 'Take Control Synchronously'
which asserts ATN. The moment ATN is asserted true
the 8291A in the slave device resets SPAS, and sets the

The following section describes the events which happen in a serial poll when 8291A and 8292 are the controller, and another 8291A is the slave device. While
going through this section the reader should refer to the
register diagrams for the 8291A and 8292.
A. DEVICE A REQUESTS SERVICE
(SRQ BECOMES TRUE)

The slave devices rsv bit in the 2819A's serial poll mode
register is set.

3-75

inter

AP-166

Serial Poll Complete (SPC) bit' in the Interrupt Status 2
register. The controller reconfigures itself to talk by setting the TO bit in the Address Mode register and then
writing a OOH to the Aux Mode register.
F. THE CONTROLLER SENDS THE COMMANDS
UNIVERSAL UNTALK (UNT), AND SERIAL POLL
DISABLE (SPD) THEN RESETS THE SRQ BIT IN
THE 8292 INTERRUPT STATUS REGISTER

The CPU in the controller waits for theBO Interrupt
status bit to be set in the Interrupt Status 1 register of
the 8291A before it writes 5FH (UNT) and 19H (SPD)
to the Data Out register. The CPU then writes a 2BH
t~ t~e 8292's command register to reset the SRQ status
bit In the Interrupt Status register. When the 8291A in
the slave device receives the UNT command the ADSC
bit in the Interrupt Status 2 register is set, and the T A
and TPAS bits in the Address Status register will be
reset. At this point the controller can service the slave
device's request.
Note that in the software listing of AP-66 (USING
THE 8292 GPIB CONTROLLER) there is a bug in
the serial poll routines. In the 'SRQ ROUTINE' when
the CPU finds that the SRQ bit in the interrupt status
register is set, it immediately writes the interrupt Acknowledge command to the 8292 to reset this bit. However the SRQ GPIB line will still be driven true until
the slave device driving SRQ has been polled. Therefore, the SRQ status bit in the 8292 will become set and
latched again, and as a result the SRQ status bit in the
8.292 will still be set after the serial poll. The proper
time to reset the SRQ bit in the 8292 is after SRQ on
the GPIB becomes false.

The S bit is the sense bit. If the "ist" (individual status)
local message value matches the sense bit, then the
829lA will give a true response to a parallel poll. Bits
P3-PI identify which data line is used for a response.
For example, assume the programmer decides that the
system containing the 829lA shall participate in parallel poll. The programmer, upon system initialization
would write to the Aux Mode Register and reset the U
bit and set the S bit plus identify a data line (P3-PI
bits). At "pon," the 829lA would not respond true to a
parallel poll unless the parallel poll flagis set (via Aux
Mode Register command).
When a status condition in the user system occurs and
the programmer decides that this condition warrants a
true response, then programmers software should set
the parallel poll flag. Since the S bit value matches the
"ist" (set) condition a true response will be given to all
parallel polls.
.
An additional method of parallel polling reading exists
known as a PPI implementation. In this case the controller sends a PPE (parallel poll enable) message. PPE
contains a bit pattern similar to the bit pattern used to
program the "Ipe" local message. The 8291A will receive this as an undefined command and use it to generate an "Ipe" message. Thus the controller is specifying
the sense bits and data lies for a response. A PPD (parallel poll disable) message exists which clears the bits
SP3P2PI and sets the U bit. This also will be received
by the 8291A and used to generate an "Ipe" false local
message.
The actual sequence of events is as follows. The contro!le: sends a PPC (parallel poll configure) message.
ThiS IS an undefined command which is received in the
CPT register and the handshake is held off. The local
CPU reads this bit pattern, decodes it, and sends a
VSCMD message to the Aux Mode Register. The controller then sends a ppe message which is also received
as an undefined command in the CPT register. The
local .CPU reads this,· decodes it clears the MSB, and
writes this to the Aux Mode Register generating the
"Ipe" message.

Parallel Poll
The 8291A supports an additional method for obtaining status from devices known as parallel poll (PPOL).
This method limits the controller to a maximum of 8
d~vices at a time since each device will produce a single
bit response on the GPIB data lines. As shown in the
state diagrams, there are three basic parallel poll states:
PPIS (parallel poll idle state), PPSS (parallel poll standby state), and PPAS (parallel poll active state).

The controller then sends ATN and EOI true and the
8291A drives the appropriate data line if the "ist" (parallel poll flag) is true. The controller will then send a
PPD (parallel poll disable) message (again, an undefined command). The CPU reads this from the CPT
register and uses it to write new "Ipe" message (this
"Ipe" message will be false). The controller then sends a
PPU (parallel poll unconfigure) message. Since this is
also an undefined command, it goes into the CPT register. When the local CPU decodes this, the CPU should
clear the "ist" (parallel poll flag).

In PPIS, the device's parallel poll function is in the idle
state and will not respond to a parallel poll. PPSS is the
standby state, a state in which the device will respond
~o. ~ parallel poll from the controller. The response is
Initiated by the controller driving both ATN and EOI
true simultaneously.
The 829lA state diagram shows a transition from PPIS
to PPS~ with the "Ipe'; message. This is a PP2 implementatIOn for a parallel poll. This "Ipe" (local poll enable) local message is achieved by writing
OllUSP3P2PI to the Aux Mode Register with U=O.
3-76

inter

AP-166

In this example, the 8292 was removed from its socket
and the OPT A and OPTB pins of the two 8293 transceiver reconfigured to modes a and I. Optionally, the
mode pins could have been left wired for modes 2 and 3
and the 8292 left in its socket with its SYC pin wired to
ground. This would have produced the same effect.

APPLICATION EXAMPLES
In the course of developing this application note, two
complete and identical; GPIB systems were built. The
schematics and block diagrams are contained in Appendix 1. These systems feature an 8088 CPU, 8237 DMA
controller, serial I/O (8215a and 8253), RAM,
EPROM, and a complete GPlB talker/listener controller. Jumper switches were provided to select between a
controller function and a talker/listener function. This
system design is based on the design of Intel's SDK-86
prototyping kit and thus shares the same I/O and
memory addresses. This system uses the same download software to transfer object files from Intel development systems.

The first action performed is sending IFC. Generally,
this is done when a controller first comes on line. This
pulse is at least 100 J.l.s in duration as specified by the
IEEE-488 standard.
The software checks to see if active listeners are on line.
For demonstration purposes, the HP 9835A will flag
the operator to indicate that listeners are on line.

Two Software Drivers
Two software drivers were developed to demonstrate a
ton/Ion environment. These two programs (BOARD 1
and BOARD 2) are contained in Appendix 2.
In this example, one of the systems (BOARD 1) initially is programmed in talk-only mode and synchroniza- '
tion is achieved by waiting for the listening board to
become active. This is sensed by the lack of a GPIB
error since a condition of no active listener produces an
ERR status condition. Board I upon detecting the presence of an active listener transmits a block of 100 bytes
from a PROM memory across the bus. The second system (BOARD 2) receives this data and stores it in a
buffer, EOI is sent true by the talker (BOARD I) with
the last byte of data. Upon detection of EOI, BOARD
2 switches to the talk only mode while BOARD 1 upon
terminal count switches to the listen only mode.
BOARD 2 then detects the presence of an active listener and transmits the contents of its buffer back to
BOARD 1 which stores this data in the buffer. EOI
again is sent with the last byte and BOARD 2 switches
back to listen-only. BOARD 1 upon detecting EOI
then compares the contents of its buffer with the contents of its PROM to ensure that no data transmission
errors occurred. The process then repeats itself.

8291A with HP 9835A
An example of the 8291A used in conjunction with a
bus controller is also included in this application note.
In this example, the 8291A system used in previous
experiments was connected via the GPIB to a HewlettPackard 9835A desktop computer. This computer contains, in addition to a GPlB interface, a black and
white CRT, keyboard, tape drive for high quality data
cassettes, and a calculator type printer. The software
for the HP9835S is shown in Appendix 3. The user
should refer to the operation manuals for the
HP 9835A for information on the features and programming methods for the HP 9835A.

The HP 9835A then configures and performs a parallel
poll (PPOL). The parallel poll indicates 1 bit of status
of each device in a group of up to 8 devices. Such information could be used by an application program to determine whether optional devices are part of a system
configuration. Such optional devices might include
mass storage devices, printers, etc., where the application software for the controller might need to format
data to match each type of device. Once the PPOL
sequence is finished, the HP 9835A offers the user the
opportunity to execute user commands from the keyboard. At this time the HP 9835A sits in a loop waiting
for an SRQ condition. When the operator hits a key on
the keyboard, the HP 9835A processor is interrupted
and vectors to a service routine where the key is read
and the appropriate routine is executed. The HP 9835A
will then return to the loop checking for the SRQ true.
For this application, the valid keys are G, D, R, H, and
X. Pressing the "G" key causes the GET command to
be sent across the bus. A message to this effect is printed in the CRT and the HP 9835A returns. The "D" key
causes the SDC message to be sent with the 8291A
being the addressed device. Again, an appropriate mesage is output on the HP 9835A CRT. The "R" key
causes the GTL message to be sent. The CRT displays
"REMOTE MESSAGE SENT." The "H" key causes a
menu to be displayed on the HP 9835A CRT screen.
This menu lists the allowed commands and their functions. NO GPlB commands are sent. The "X" key allows the operator to send one line of data across the
bus. The line of data is terminated by a carriage return
and line feed produced by pressing the "CONTINUE"
key on the HP 9835A.
The characters are ,stored in the sequence entered into a
buffer whose maximum size is 80 characters. Pressing
the "CONTINUE" key terminates storing characters
in the array and all characters including the carriage
return and line feed are sent. EOI is then sent true with
a false byte of OOH. This false byte is due to the 1975
standard which allows asynchronous sending and reception of EO!. (The 8291A supports the later 1978
standard which eliminates this false byte.)

3-77

inter

AP-166

After any key command is serviced control returns to
the loop which checks for SRQ active. Should SRQ be
active, then the keyboard interrupt is disabled and a
message printed to indicate that SRQ has been received
true.

Next, the GET bit is examined and if true, the CRT
screen connected to the serial channel on the 8291A
system prints a message to indicate that the trigger
command has been received. A similar process occurs
with the DEC and REMC status bits.

The controller then performs a parallel poll.

Address Status Chagne (ADSC) is checked to see if the
8291A has been addressed or unaddressed by the controller. If ADSC is false, then the software checks the
keyboard at the CRT terminal. If ADSC is set, then the
T A and LA bits are read and evaluated to determine
whether the 8291A has been addressed to talk or listen.
The DMA controller is set to start transfers at the start
of the character buffer and the type of transfer is determined by whether the 8291A in in TADS or LADS.
We only need to set up the DMA controller since the
transfers will be transparent to the system processor.
The keyboard from the CRT terminal is then checked.
If a key has been hit, then this character is stored in the
character buffer and the buffer printer set to the next
character location. This process repeats until the received character is a line feed. The line feed is echoed to
the CRT, the serial poll status byte updated and the
SRQline driven true. This allows the 8291A system to
store up to one line of characters before requesting a
transfer to the controller. Recall that upon receiving an
SRQ, the controller will perform a serial poll and subsequently address the 8291A to talk. The 8291A system
then goes back to reading the status register thus repeating the process.

This is an example of how parallel poll may be used to
quickly check which group of devices contains a device.
sending SRQ. The eight devices in a group would, of
course, have software drivers which allow a true response to a PPOL if that device is currently driving
SRQ true. This would be a valuable method of isolation
of the SRQ source in a system with a large number of
devices. In this application program, only the response
from the 8291A is of concern and only the 8291A's
response is considered. It does, however, demonstrate
the technique employed. If a true response from the
8291 A is detected, then a message to this effect is printed on the HP 9835A CRT screen. From this process,
the controller has identified the device requesting service and will use a serial poll (SPOL) to determine the
reason for the service request. This method of using
PPOL is not specifically defined by the IEEE-488 standard but is a use of the resources provided.
The controller software then prints a message to indicate that it is about. to perform a serial poll. This serial
poll will return to the controller the current status of
the 2819A and clear the service request. The status byte
received is then printed on the CRT screen of the
HP 9835A. One of the 8291A status bits indicates that
the 8291A system has a field (on line or less) of data to
transfer to the HP 9835A. If this bit is set, then the
HP 9835A addresses the 8291A system to talk. The
data is sent by the 8291A system is then printed on the
CRT screen of the HP 9835A. The HP 9835 then enables the keyboard interrupts and goes into its SRQ
checking loop.

CONCLUSION
This application note has shown a basic method to view
the IEEE 488 bus, whe.n used in conjunction with Intel's 8291A.
The main reference for GPIB questions is the IEEE
Standard 488-1978. Reference 8291A's data sheet for
detailed information on it.

Appendix 4 contains the software for the 8291A system
which is connected to the HP 9835A via the GPIB.
This software throws away the first byte of data it receives since this transfer was used by the HP 9835A to
test when the 8291A system came on line.

Additional Intel GPIB products include iSBX-488,
which is a multimode board consisting of the 8291A,
8292, and 8293.

REFERENCES

Next, both status registers are read and .stored in the
two variable STAT I and STAT 2. It is necessary to
store the status since reading the status registers clears
the status bits.

8291A Data Sheet
8292 Data Sheet
8293 Data Sheet
Application Note #66 "Using the 8292 GPIB Controller"
·PLM-86 User Manual
HP 9835A User's Manual
IEEE--488-1978 Standard

Initially, six status bits are evaluated (END, GET,
CPT, DEC, REMC, ADSC). Some of these conditions
require that additional status bits be evaluated.
If END is true, then the 8291A system has received a
block from the HP 9835A and the contents of a buffer
is printed on the CRT screen. Next, the CPT bit is
checked. PPC and PPE are only valid undefined commands in this example.

3-78

AP-166

APPENDIX A
SYSTEM BLOCK DIAGRAM WITH 8088

3-79

inter

AP-166

APPENDIX B
SOFTWARE DRIVERS FOR BLOCK DATA TRANSFER

PLlM'-86 cor'oP ILER

BOARD 1

1515'-11 PLtr1-86
VI
(OMPILATJUt, OF MODUl.E RO"'RD !
OEJECT MODULE PLACED IN'
r!
ORO 1
OB~
COMPILER INVOKED :lV:
PLl186.
FI:
BRDl,
SRC SYMBOLS MEDIUM

1*
i*
1*
/*

1*
1*
1*
1*
/..
f*

1*
1*
1*
1*

BOARD 1 TPT PROGRAM
*1
THIS JJONin TAL~,S Ttl THE OTHER BOARD e',
'J
TRANSFERRING A BLOCK OF DATA VIA THE 8237
"I
COVPLED tHTH THE: 8291A
THE 8291A IS PROGRAM- *1
MED TO SEND EO! I,HEN RECOGNIZING THE LAST
*1
DATA ByTE'S BIT PATTERN.
WHILE DATA IS BEING *1
TRANSFERRED. THE PROCESSOR PERFORMS
lID READS *1
OF THE [>237 CQ'_'IH REG {STERS TO SIMULATE. BUS
*1
ACTIVIT(. AND TO DE1ERMINE WHEN TO TURN THE
*1
LINE AROUND. A!"TER THF. 8237 HAS REACHED ·.f
TERMINAL COUNT. THE 8291A IS PROGRAMMED TO
*1
THE LISTENER ST"'TE AI~D WAITS FOR THE BLOCK
*1
TO DE TR"INSMITTED }lACK FROM THE SECOND BOARD, *1
THIS O"TA IS PLACED IN A SECOND BUFFER AND
*1
ITS CONTEtHS cor1PARED WITH THE ORIGINAL D,ATA *1
TO CHECK FOR INTERFACE INTEGR ITY.
*1

BOARDI :
DO,

l* PROCEDURES *1
2
3

4
5
6
7

3
2
2

8
9

CO:

PROCEDURE (XXX)
DECLARE XXX BYTE.
SER$STAT LITERALLY
'OFFF2H'.
SER$DATA
LITERAL.LY
'OFFFOH'.
TXRDY
LITERALLY
·OIH·.
lJO t,HILE (INPUT
(SER$STAT> AND TXRDY) C>
END,
XXX,
.OUTPUT (SER$DATA)
END CO,

TXRDY,

SETUP BUFFERS *1
DECLARE BUFF2 (100)
BYTE,
1* RAM STORAGE AREA
DECLARE BUFFI (100) BYTE DATA
(1,2,3.4.5.6.7.8.9.10H.
l1H, 12H. 13H. 14H. ISH.
21HI 22H, 23H. 24H, 25H.
31H. 32H, 33H. 34H. 35H.
41H. 42H. 43H. 44H. 45H.
5tH. 52H, 53H. 54H. 55H.
6tH. 62H, 63H. 64H. 65H.
7tH. 72H. 73H. 74H. 75H.
B1H· 82H. 83H. 84H. 85H.

16H.
26H.
36H.
46H.
56H.
66H.
76H.
86H.

17H.
27H.
37H.
47H.
57H.
67H.
77H.
87H.

IBH.
2BH.
3BH,
4BH,
58H.
6BH.
78H.
B8H.

19H.
29H.
39H.
49H.
39H.
69H.
79H.
89H.

20H.
30H.
40H.
50H.
60H.
70H.
BOH.
90H.

230832-5

3-80

inter
PL/M-86

AP-166

COMPILER

BOARD I
'11H, 92H, 93H, '14H, 95H, 96H, 97H, 9SH,
DECLARE BUFF3 ( (7)
BYTE DATA
(DDH, OAH. 'COt1PARE ERROR', ODH
C.~fO;

'*
11

8237 rOPT ADDRESSES

ODH);

1* ROM STORAGE AREA *1

DECLARE
CLEAR$FF
START$O$LO
START$O$HI
O$COUNT$LO
O$COUNT$HI
SET$110DE
CMD$37
SEal1ASK

LITERALLY
LI TER ALL y
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY

'OFFDDH', /* M"STER CLEAR *1
OFF DOH' ,
'OFFDOH',
'OFFD1H',
'OFFD1H',
'OFFDBH',
'OFFDSH'
'OFFDFH'

12
13

;* 8237 CCMI1AND
- DATA BYTES <01
DECLARE
Dl1A$ADR$TALK
POINTER;
DECLARE
DMA$ADR~LSTN
POItHER;

DECLARE
RD$TRANSFER
WR$TRANSFER
NORM$TIME
TC$L.Ol
T.:$HI t
TC$L.O:;'~

TC
I

99H,·

LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERAl.LY 'OlH'
BYTE;

'4SH' ,
'44H' ,
'20H',
'OFFH',
'OOH',

'990',

100 XFERS

DECl.ARE
DI1A$~'RD$TI,I_~.

Dl1A$~'RD$LSTN

(2)
(2)

i~ORD

~'ORD

(@DMA$ADR$TALK) ,
(@DMA$ADR$LSTN) ;

1* 8291A PORT ADDRESSES *1
16

DECLARE
PORT$OUT
PORT$IN
STATUS$1
STATUS$2
ADDR$STATUS
C0I1MAND$r10D
AOOR$O
EOS$REG

LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALl.Y

'OFFCOH' ,
'OFFCOH'
'OFFC1H' ,
'OFFC2H' ,
'OFFC4H' ,
'OFFC5H',
'OFFC6H' ,
'OFFC7H' ,

I·' DATA OUT*I
I*INTR STAT 2*1
1* INTR STAT 2 *1
I*CMO PASS THRU

EOS REGISTER *1

230832-6

3-81

inter

AP-166

1* B291A COliMM.O
PL/M-B6 COMPILER

DATA BYTES <;

BOARDI

DECU,RE
Et~D$EOI

L ITER ALL Y
ONE LI TERALL Y
paN
LI TERALL Y
RESET
LITERALLY
CLEAR
LI TERALL Y
DMA$REG$L LITERALLY
L't1A$REG$T LITERALLY
MODI$TO
LITERALLY
MOD ULO
l.I TERALL Y
EOS LITERALLY
PRESCALER LITERALLY
HIGHSSPEED LITERALLY
OKAY
LITERALLY
XYZ
BYTE,
MATCH
~~ORD,
aD
LI TERALL Y
BI
l [ fERALL Y
ERR
L ITER ALL Y

'BBH',
'lOH',
~OOH/,

'02H',
'OOH',
, lOH',
'20H',
'BOH',
'40H',
'ODH',
'23H',
'OA4H',
'OFFFFH' ,

'02H',
'OIH' "
'04H';

1* CODE BEGINS *1
18

START91':
OUTPUT

(STATUSS2)

=CLEAR;

1* SHUT-OFF DMA REG BITS TO *1
1* PREVENT EXTRA DMA REGS *1
I*FROM 8291A
*1

Ii< MNHPUU,TE DMA ADDRESS VARIABLES

DMA$ADRSrAL.K
=(@IlUFFI);
DMA$ADR$LSTN
= (@BUFF2) ;
DMASWRD$TALK(I)=SHL (DMA$WRD$TALK(!), 4);
DtiA$WRDSTALK (0) =DliASI~RD$TALK (0) + DMASWRDSTALK (1);
DMASI~RDSLSTN ( 1 ) =SHL (DliASWRDSLSTN (1), 4);
DI1ASWRDSLSIN (0) =OMASI~RDSLSTN (0) +DMASWRDSLSTN (1),

:;:0
21

22
23
24

INIT371 .

1* ItHT 8237 FOR TALKER FUNCTIONS *1
26

27
28
29
30
31
32
33

PLlM-86 COMPILER

OUTPUT
OUTPUT
OUTP\,lT
OUTPUT
OUTPUT

(CLEARSFF)
(CMDS37)
(SETSli0DE)
(SETSMASK)
(STARTSOSLO)

=CLEAR;I* TOGGLE MASTER CLEAR
=NORMSTIME,
=RDSTRANSFER;
=CLEAR,
=DMASWRDSTALK (0);
DMA$\~RDSTALK (0)
=SHR COliASWRDSTALK (0), 8),
OUTPUT
(STARTSOSHI)
=DMASWRDSTALK (0),
OUTPUT
(OSCOUNTSLO)
=TCSL02;
OUTPUT
(OSCOUNT$HI)
=TCSHI2;
1* INIT 8291A FOR TALKER FUNCTIONS *1

Il OAR OJ,

230832-7

3-82

inter

AP-166

34
35
36
37
38
39

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

(EOS$REG)
=EOS,
(Cot1MAND$MOD)
=END$EO Ii I *
EO I ON EOS SENT
(ADDR$STATUS)
=MOD!$TO, 1*' TALK ONLY *1
(C Ot1MAt,D$MOD)
=PRESCALER.
(COt1t1AND$t10D)
o'HIGH$SPEED,

1* WAlT FOR EO! RECEIVED *i

(STATUS$2)

=DMA$REQ$L,

ENABLE DMA REGS

DNE;

230832-8

3-83

AP-166

PL/M-B6 COMPILER
70

BclARP

CMPBlY.2·
i ..

CC!1PARE THE HID BUFFERS CONTENTS *1

11ATCH=CMPB
71

IF r1ATCH

!,.
73
74
75

(@BUFFL

@BUFF2.

OKAY THEN GOTO START9l;

GE'JD ERROR MESSAGE IN BUFFER 3

DO 1;0 TO 16;
CALL CO
(!lUFF 3
END;

100);

(I )

);

COTO START91;

MODULE mFORMATION:
CCiDE AREA SIZE
CONSTANT AREA SIZE
VARIA!lLE AREA SIZE
MAXIMUM STACK SIZE
243 LINES READ
o PROGRAM ERRCR (5)

END OF PLIt1-86

=010!lH
=0075H
=0070H
=0006H

4750
1170
1120
60

COMP ILATION

230832-9

3-84

inter

AP-166

PL/M-86 Cor1PILER

BOARD2

ISIS-II PL/M-86 VI. 1 Cor1PILATION OF MODULE BOARD2
OBJECT ri0DULE PLACED IN
Fl: BRD2. OBJ
COMPILER INVOKED !lY:
PLM86
Fl:
BRD2. SRC

2 TPT PROGRAM
*i
*1
THIS BOARD LISTENS TO THE OTHER BOARD (1)
*1
Ar~D DtiA'S DATA INTO A BUFFER, ~,HILE WAITING *1
FOR THE END lNTERRUPT BIT TO llECor1E ACTIVE *1
UPON Er.D ACTIVE. THE DATA IN THE BUFFER IS *1
SENT BAC~ TO THE FIRST BOARD VIA THE GPID
*1
WHEN THE BLOCK IS FINISHED THE 8291A IS *1
PROGRAr1MED BACK INTO THE LISTENER MODE
*1

I ' BOARD
/*

1*
/*

'*1*
1*

1l0ARD2
DO,
1* 8237 PORT ADDRESSES *1

DECLARE
Cl.EAR$FF
START$O$Lo
START$OSHI
O$COUNT$LO
O$COUtH$HI
SET$MODE
CI1D$37
SET$MASK
1* 8237 CUMMAND

- DATA BYTES

I*MASTER CLEAR *1

DECLARE
RD$TRANSFER
LITERALLY
WR$TRANSFER
LITERALLY
ADDR$IA
LITERALLY
ADDR$11l
LITERALLY
I,ORI1$TIME
LITERALLY
TC$LOI
LITERALLY
TC$HII
LITERALLY
TC$L02
LITERALLY
TC$HI2
LITERALLY
LITERALLY
TC

1* 8291A
4

'OFFDDH'.
'OFFDOH'.
'OFFDOH'.
'OFFDIH' •
'OFFDIH' •
'OFFDBH' •
'OFFD8H' •
'OFFDFH' ,

LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY

'48H".
'44H'.
'~OH'.

'OIH' ,
'20H'.
'OFFH'.
'~OH' •
'99D',
'~OH'.

'OlH' •

PORT ADDRESSES *1

DECLARE
PORT$OUT
PORT$W
STATUS$l
STATUS$2
ADDR$STATUS
COr1IiAND$110D

LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY

'OFFCOH' •
'OFFCOH'.I* DATA IN *1
'OFFCIH'. 1* INTR STAT 1 *1
'OFFC2H' , 1* INTR STAT :2 *1
'OFFC4H', 1* ADDR STAT
*1
'OFFC5H' • 1* CriD PASS THRU *1
230832-10

3-85

inter

AP-166

PL/M-B6 COMP Il.ER

1l0f",D2
ADDR$O
EOS$REG

LITERALLY
LITERALLY

/ .. 8291A

COI1MAND- DATI, BYTES *1

'BSH',
'10H

'OOH',
"02H',

'OOH',
'IOH' ,
'20H'1

'BOH',
'40' ,
'ODH',
.'23H'.

'A4H',
'02H',
'OIH' ,
'04H',

START91.
OUTPUT

(STATUS$2)

=CLEAR:

END INITILIZATION STATE *1

i* HUT B237 FOR LISTENER FUNCTION

8
9
10
II
12
13
14

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPLUT

(CLEAR$FF)
=CLEAR; /* TOGGLE MASTER RESET *1
(CI1D$37)
=NORM$TII1E.
(SET$110DE)
=WR$TRAI~SFER,
1* BLOCK XFER MODE *1
(SET$MASK)
=CLEAR,
(START$O$LO)
=ADDR$IA;
(START$O$HI)
=ADDR$IB.
«(j$COUtH$LOl
=TC$LOL
(Q$COUNT$HI)
=TC$HI1;

INIT 8291A

l~AIT

FOR LISTENER FUNCTIONS

OUTPUT
(COMt1AND$MOD)
=RESET;
OUTPUT
(ADDR$STATUS)
=MOD1$LO,
(COMMAND$MOD)
=PON,
OUTPUT
DO \~HILE (INPUT
(STATUS$I)
AND llI)
END.
1* WAIT FOR BI INTR *1
XYZ= INPUT - (PORT$IN),
OUTPUT
(STATUS$2)
=Dt1A$REG$L,
1*

->/

INIT37L.

/.
15
1617
18
19 2
20
21

EOS REGISTER *1

DECLARE
END$EOI
LI TERALL Y
DNE LITERALLY
F or~
LI TER Al.L Y
RESET
LI TERALl. Y
CLEAR
LITERALLY
Dt1A$REO$L L ITER ALL Y
DMA$REO$T LITERALLY
MODI$TO
LITERALLY
MODI !fLO
LITERALLY
EOS LITERALLY
PRESCALER LITERALLY
HIGH$SPEED LITERALLY
XYZ
BYTE,
BO
l.ITERALLY
BI
LITERALLY
ERR
I. I TERAI.L Y

'OFFC6H',
'OFFC7H',

=0;

UtHIL EOI RCVD AND END INTR-llIT SET

l~HILE

(INPUT

(STATUS$I)

AND DNE )

_*1

<:>

DNE,
230832-11

3-86

intJ
PLiM-·86

AP-166

COMPILER

BOARD2
END,

INIT37T!
1* INIT 8237 FOR TALI',ER

25
26
27
28
29
30
31
32

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

33
34
35
36
37
38

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

FUI~CTION

(STATUS$2)
=CLEAR,
1* CLEAR 8291A DRQ *1

TC,

GOTO START91,
END,

MODULE I NI'"OR MATI ON
CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
152 LINES READ
.
o PROGRAM ERROR (5)

=0122H
=OOOOH
=OOOIH
=OOOOH

2900
OD
ID
00

230832-12

3-87

intJ

AP-166

APPENDIX C
SOFTWARE FOR HP 9835A

1£1
REM SEtHI IN
TERFACE CLEAR
20
ABORTIO 7
30
REM FORCE E
RRORS UNTIL LIST

ORM 1 HG SER I AL PO
L~ TO CET STRTUS

180

320

IF SrCl=O TH

EN GOIO L... · ... n
19(, OF;: n:'
PF: J IH (HR$ I
121, "SR(l RECEIVE
D" '

EHERS ACT I YE
40 Freer,..:
OUT
,K"; "B"
50 Chkstst:
ST
ATUS 7.Sto.thSto.
t2,StOot3,Sto.t4

330

IF Err=! TH

EN GOTO Freer,..

230

80
PRINT CHRt(
12), "LISTENERS A
RE ON LINE
90
'REI1 CONFIGU
RE PPOLL
100 PPOLL CON':
GURE 704 j .. 000~.H :
(H)"

PRIfIT

520

bi t

120
PRINT CHE.,
12), "PARALLEL PO

291
280
PRINT "'SR'
NOT FROM 8291"
281
PRHH ",CCIt·Hi
AND = ?
(HIT
'H' FOR LI STI •
29£1 cOTO Keyen
308 PB291:
PRIN
T "SRQ IS FROM H
CC 82'91
THE
EtiTERPR I BE"'
310
PRlliT "'PERF

130 REM ENABLE
KEYBOARD ItITERRU
PT
140 PR I NT "COHM
AIID = ?
(HIT
'H' FOE: L1STI"
150 KE'yen=
ON K
BD COSUB 610
160 STATUS 7;S,

at 1, Stat2, S1.O,t3,

"~,T";GS

560

PRINT CHRt (

610 J.ihatkey:

PRINT' "COMI1
(HIT
AND ::: ?

'H' FOP LI STl"
770 RETURti
780 R"'M:
LOCAL
704
798
PRINT CHR' (
121. "RE"OTE MESS
ACE SENT"
8BO PRIHT ,"
810
PRIHT "COMM

AND = ?
(HIT
'w FOR LIST) ~
820

RETURN

830 Heh·: . PRINT

M Kt [BB]
€·20
K$=KBU
630
IF Kt="'C" T

CHR$(12)
848
PRIHT
@@@
@ OPERATOR ALLO~
ABLE COMMANDS @@

HEN
640
HEN
650
HEN
660
HEN
670

230832-13

PRINr"~

768

570
PRINT "COMM
AND = ?
(HIT
'H' FOR L1STI"
589
GO TO Keyen
59B
REM INTERRU
PT SERYICE ROUT!
NES
600
REM CET KEY
BORRD DATA

2713
IF Ppol1byt.
0=8 THEN COTO "

LL CONFIGURED"

SING

12),"SElECTlVE D
EVICE CLEAR SENT
750

12) ,es

___ _

J NAND (Ppo 11 byt Eo,
BI

resJ)onse or.
4

IF Dxt'er';O

THEM GOTO Re')r
539
COrD Keyen
531 'Rev,..:
REI1 R
EADY TO RCY CHAR
S FROM GPIB
540
DIM CH80]
550
EHTER 784 U

26S--Ppoll byt II?=B

118

t-t'=BINAN

D(S~oto1)

Ppol1byte=P

"; Pp(fl I byt e

.
:,.:~

340

POLl( 71
248
PRINT "PARA
LLEL POLL BYTE =
250

PRINT CHR. (

12), "Status = .. ;

510t

210
PRlHT "SEND
IHC PARALLEL POL
L RESPONSE MESSA
CE"
220
REM EXECUT!
HC PARALLEL POLL

Err=S,tCltZ A

R 704
698 PRINT CHR.(
12), MGROUP EXECU
TE TRIGGER S[»T"
700
PRINT
718
PRINT "COltH
AND =?
(HIT
'H' FOR LIST)"
720
RETURN
730 Dec:
RESET
7B4
740
PRIHT CHR$ (

STATUS 704;

Sto.t

2ee

PUT 704 USINC ".

6£1
tlD
70

Sto.t4
1 T"O SrCl=BI HAtHI (
Statl,U8)

GOTO Get
IF K$="D"
GOTO Dec
IF K$="R" T
GOTO ReM
IF K$="W
COTO He1 p
IF Kt="'X" T

850
PRINT
hi t
key
resul t"
860
PRINT
Send GET ...
esso.'5IIe.~

870

HEN COTO X",i t
680 Get:

Send DtC

I'l

@ossO-ge"

TRICjSE

230832-14

8~e

PRINT
P
Send REM, L

940 XMi t:
DIM A
H801
950
PRINT CHRS: (

OC l"Iesso.'ge"
890

Xl"'li ts

91 "
990

12), "Enter data

ke~d:

oord input to
PRINT

to send and hi t

::,~

CONTINUE"

960

919
920
90

930

PRIHT
PRINT

ahead, TRY"

INPUT At

97B
OUTPUT 704 j
At
971
EOl 719
980
PRINT "COMM
AHD = ?
(HIT
'H' FOR L1STI"
990
RETURH
1 BOe END

Pri nts thi

s to.b1e"

RETURt~

3-88

230832-15

inter

Ap·166

APPENDIX D
SOFTWARE FOR HP 8088/HP 9835A VIA GPIB

PL/M-B6 COMPILER

HPIB

ISIS-II PL/M-B6 VI. 1 COMPILATION OF MODULE HPIB
OBJECT MODULE PLACED IN :Fl:HPIB.oBJ
COMPILER INVOKED BY: PLMB6 :Fl:HPIB.SRC LARGE

HPIB:
1*

PARAMETER DECLARATIONS
*1

DO,
2

DECLARE
AoDRSHI
LITERALLY
'OlH'.
ADDRSLo
LITERALLY
'~OH'.
ADSC
LITERALLY
'OlH'.
BI
LITERALLY
'OlH'.
Bo
LITERALLY
'02H'.
CHARSCOUNT BYTE.
CHAR
BYTE.
CHARS(BOI
BYTE.
CLEAR
LITERALLY
'OOH'.
CPT
LITERALLY
'BOH'.
CRLF
LITERALLY
'OAH'.
DEC
LITERALLY
'OBH'.
DMASADRSLSTN
POINTER.
DMASADRSTALK
POINTER.
DMASWRDSLSTNC21 WORD AT
(eDMASADRSLSTNI.
DMASWRDSTALKC21 WORD AT
(eDMASADRSTALKI.
DMASREOSL
LITERALLY
'lOH'.
DMASREOST
LITERALLY
'20H'.
DNE
LITERALLY
'10H'.
ENDSEOI
LITERALLY
'BBH',
EOS
LITERALLY
'ODH'.
ERR
LIT~ALLY
'04H'.
gET
LITERALLY
'20H'.
I
BYTE.
LISTEN
LITERALLY
'04H·.
MLA
LITERALLY
'04H'.
MODES 1
LITERALLY
'OlH'.
NOSDMA
LITERALLY
'~OH'.
NOSRSV
LITERALLY
'OOH'.
NORMSTIME
LITERALLY
'20H'.
PoN
LITERALLY
'OOH'.
PPC
LITERALLY
'OllH'.
PPESMASK
LITERALLY
'60H'.
PPOLLSCNFgSFLAG LITERALLY
'OlH'.
PPOLLSENSBYTE
BYTE.
PRISBUFCBOI BYTE AT
(eCHARSI.
RDSXFER
LITERALLY
'4BH'.
RESET
LITERALLY
'02H'.
REMC
LITERALLY
'02H'.
RSV
LITERALLY
'40H'.
RXRDY
LITERALLY
'02H'.

3-89

230832-16

AP-166

PL/M-S6 COMPILER

HPIB

SROS
LITERALLY
'40H',
, STATl
BYTE.
STAT2
BYTE.
TALK
LITERALLY
'02H',
TASORSLA
BYTE,
TRO
LITERALLY
'41H',
TC
LITERALLY
'01H',
TCSHI
LITERALLY
'OOH',
TCSLO
LITERALLY
'OFFH',
TXRDY
LITERALLY
'01H',
UDC
BYTE.
WRSXFER
LITERALLY
'44H',
XYZ
BYTE;
1*

PORT DECLARATIONS
*1

DECLARE
ADDRSO
ADDRSSTATUS
CLEARSFF
CMDS37
COMMANDSMOD
COUNTSHI
COUNTSLO
CPTSREG
EOSSREG
PORTSIN
PORTSOUT
SERSDATA
SERSSTAT
SETSMASK
SETSMODE
SPOLLSSTAT
STARTSHI
STARTSLO
STATUSS1
STATUSS2

4
:I
6
7
S

LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY,
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY
LITERALLY

'OFFC6H'.
'OFFC4H',
'OFFDDH'.
'OFFDSH',
'OFFC:lH'.
'OFFD1H'.
'OFFD1H' •
'OFFC5H',
'OFFC7H',
'OFFCOH',
'OFFCOH'.
'OFFFOH'.
'OFFF2H'.
'OFFDFH',
'OFFDBH'.
'OFFC3H'.
'OFFDOH'.
'OFFDOH'.
'OFFC1H'.
'OFFC2H';

1* CT't

m@ssages list *1

DECLARE
DECLARE
DECLARE
DECLARE
DECLARE

GETSMSG(ll) BYTE DATA (ODH.OAH. 'TRIGGER', OAH. ODH);
DECSMSG(16) BYTE DATA (ODH.OAH. 'DEVICE CLEAR'. OAH. ODH),
REMCSMSQ(10) BYTE DATA (ODH.OAH. 'REMOTE'. ODH. OAH),
CPTSMSG(22) BYTE DATA (ODH.OAH. 'UNDEF CMD RECElVED'.OAH.ODHI,
HUHSMSQ<1l1 BYTE DATA (ODH.OAH. 'HUH ???·.ODH.OAH),

1* called PT'DCRduT'RS *1
9

REOSER:

PROCEDURE;
230832-17

3-90

AP-166

PL/M-86 COMPILER
10
11

OUTPUT (SPOLL.STATI =TRG,

DO WHILE (INPUT (SPOLL.STATI AND SRGSI-SRGS,
END,
OUTPUT (SPOLL.STATI-NO.RSV,

17
18
19
20
21
22
23
24
2S

3
2
2
1
2
3
3
2

DO WHILE (INPUT (SER.STATI AND TXRDYI<>TXRDY,

END,

OUTPUT (SERSDATAI=XXX,
END CO,
HUH:
PROCEDURE,
DO 1=0 TO 10,
CALL CO (HUHSMSG( I I I;
END,
END HUH,
CI:

2
2

3
3
3
3
3
3
3
3
3
4

39
40
41
42
43
44

4
4
3
3
2

PROCEDURE,
IF (INPUT (SER.STATI AND RXRDYI=RXRDY THEN
DO,
1=0;

STORE.CHAR:

45
46

END REQSER,
CO: PROCEDURE(XXXI,
DECLARE
XXX
BYTE,

26
27
28
29
30
31
32
33
34
3S
36
37

HPIB

END,
END CI,
,TALK$EXEC:

CHAR.COUNT=O,
CHAR-(INPUT (SER.DATAI AND 7FHI,
CHAR.COUNT=CHARSCOUNT+l,
CALL CO (CHARli
CHARS( I I=CHAR,
1=1+1,
IF CHAR <> CRLF THEN
DO,
DO WHILE (INPUT (SER$STATI AND RXRDYI <>RXRDY,
END,
GOTO STORE.CHAR,
END.
CALL REGSER,

PROCEDURE.

OUTPUT (STATUS$21-CLEAR,
1*

manipulate

addre~s

bits fDr DMA cDntrDller

47
48
49

2
2.

DMA$ADR.TALK=(@CHARSI,
DMA$WRD$TALK(II-SHL(DMASWRD$TALK(II.41,
DMASWRD.TALK(OI-DMA.WRD.TALK(OI+DMASWRD.TALK(II.

OUTPUT (CLEAR.FFI =CLEAR.

230832-18

3-91

infef

AP-166

PL/M-S6 COMPILER

HPIB

:51
:52
:53
:54
:55
:56
:57
58

2
2
2
2
2
2
2
2

OUTPUT (CM037)-NORM$TIME,
OUTPUT (SET$MODE)-RD$XFER,
OUTPUT (SET$MASK)=CLEAR,
OUTPUT (START$LO)=DMA$WRD$TALK(O) ,
DMA$WRD$TALK(0)=SHR(DMA$WRD$TALK(0).8),
OUTPUT (START$HI)-DMA$WRD$TALK(O),
OUTPUT (COUNT$LO)-CHAR$COUNT,
OUTPUT (COUNT$HI)=O,

:59
60

2
2

OUTPUT (EOS$REQ)=EOS,
OUTPUT (COMMAND$MOO)=END$EOI,

61
62
63

2
3
2

DO WHILE (INPUT (STATUS$I) AND BO)=O,
END,.
OUTPUT (PORT$OUT)-OAAH,

64
65
66
67
68
69

2
3
4
3
3
2

00 WHILE (INPUT (STATUS$I) AND ERR)-ERR,
DO WHILE (INPUT (STATUS$I) AND BO)-O,
END,
OUTPUT (PORT$OUT)=OAAH,
END,
OUTPUT. (STATUS$2)=DMA$REO$T,

END TALK$EXEC,

72
73
74
75
76
77
7S
79
80
81
82
83
84
85

2
2
2
2
2
2
2
2
2
2
2
2
2
2

OUTPUT (STATUS$2)=CLEARl
OUTPUT (CLEAR$FF)=CLEAR,
OUTPUT (CMO$37)=NORM$TIME,
OUTPUT (SET$MODE)-WR$XFERl
OUTPUT (SET$MASK)=CLEAR;
DMA$ADR$LSTN" (.CHARS) ;
DMA$WRO$LSTN(I)=SHL(DMA$WRO$LSTN(1).4);
DMA$WRD$LSTN(0)-DMA$WRD$LSTN(0)+DMA$WRD$LSTNC1)l
OUTPUT CSTARi$LO)-DMA$WRO$LSTNCO),
DMA$WRD$LSTNCO)zSHRCDMA$WRD$LSTNCO).8);
OUTPUT (START$HI)-DMA$WRO$LSTNCO);
OUTPUT CCOUNT$LO)=TC$LO;
OUTPUT CCOUNT$HI)=TC$HI;
OUTPUT CSTATUS$2)=DMA$REO$L,

END LISTEN$EXEC;

PROCEDURE,

PRINTER:

PROCEDURE,

IzQ,

89
90
91
92
93

2
3
3
3
2

00 WHILE PRI$BUF(I) <>CRLFl
CALL CO (PRI$BUF(I»;

END PRINTER;

END;
CALL CO (PRI$BUF(I»,

230832-19

3·92

intJ

AP-166

PL/M-B6 COMPILER

HPIB

ADSC.EXEC:

PROCEDURE,

TA.OR.LA=INPUT IADDR.STATUSl,

97
9B

2
2

100

IF ITA.OR.LA AND TALKl=TALK THEN
CALL TALK.EXEC,
IF ITA.OR.LA AND LISTENlzLISTEN THEN
CALL LISTEN.EXEC,

101

END ADSC.EXEC,

102
103
104
105
106
107
lOB
109
110
111

1
2
3
3

2
1
2
3
3
2

112

113
114
115
116

2
3
3
2

PROCEDURE,
DO 1=0 TO 10,
CALL CO I GET.MSG I II I,
END,
END GET.EXEC,

DEC.EXEC:

PROCEDURE,
DO 1=0 TO 15,
CALL CO IDEC.MSGIIII,
END,
END DEC.EXEC,

REMC.EXEC:

PROCEDURE,
DO 1=0 TO 9,
CALL CO IREMC.MSG( I 1.1'
END,
END REMC.EXEC,

PPOLL.CON:

117
11B

119

120
121

GET.EXEC:

END PPOLL.CON,
PPOLL.EN:

122

2
2

123

124

125
126

127

PROCEDURE,

OUTPUT (COMMAND.MODI=PPOLL.CNFG.FLAG,

PROCEDURE,

PPOLL.EN.BYTE=(UDC AND 6FHI,
OUTPUT I COMMAND.MODI-PPOLL.EN.BYTE,
END PPOLL.EN,
CPT.EXEC:

PROCEDURE,
DO 1=0 TO 21,
CALL CO (CPT'MSG(Ill,
END,

12B

129

130

131

UDC-INPUT (CPT'REGI,
UDC-(UDC AND 7FHI,
IF IUDC AND PPCl=PPC THEN
CALL PPOLL.CON,

132
133

2
2

IF (UDC AND PPE.MASKI-PPE.MASK THEN
CALL PPOLL.EN,

3-93

230832-20

AP-166

HPIB

PL/M-86 COMPILER

134

END CPTtEXEC;

BEGIN CODE
*1

INIT:

135
136
137
138
139
140

OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT

141

LISTENERS:

(CLEARtFF) =CLEAR;
(COMMANDtMOD)
-RESET;
(ADDRtSTATUS)
-MODEtl;
(ADDRtO)
=MLA;
(STATUSt2) =NOtDMA;
(COMMANDtMOD)
-PON;

1* response to listeners check *1

142

DO WHILE (INPUT (STATUSti) AND BI)=O;
END;

XVZ=INPUT (PORTtIN);
XVZ-INPUT (STATUSt21;

143
144
CMD:

145

RDSTAT:
1* read status registers and interpret command *1
STAT1=INPUT (STATUSti);
STAT2-INPUT (STATUSt2);

146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
16B
169

1
1
1
1
2
2
2
1
1

2
2
2
1
1
2
2
2
1
1
2
2
2
1

IF (STATl AND DNEI-DNE THEN
CALL PRINTER.
IF (STAT1 AND CPT)-CPT THEN
DO;
CALL CPTtEXEC,
STAT2-(STAT2 AND OFEH),
END,
IF (STATl AND GET I-GET THEN
00;
CALL GETtEXEC;
STAT2-(STAT2 AND OFEHI;
END,
IF (STATl AND DEC I-DEC THEN
DO,
CALL DECtEXEC;
STAT2-(STAT2 AND OFEH) ,
END,
IF (STAT2 AND REMCI=REMC THEN
DO;
CALL REMCtEXEC;
STAT2=(STAT2 AND OFEHI,
END;
IF (STAT2 AND ADSCI=ADSC THEN

3-94

230832-21

inter

Ap·166

P~/M-B6

HPIB

COMPI~ER

170
171

1
2

DO.

172

2
2

STAT2~(STAT2

173

CA~~

ADSC'EXEC.
AND OFEH),

,END.
CI.

174

CA~~

17~

GOTO CMD,

END.

176

MODU~E

INFORMATION:

CODE AREA SIZE
= 0475H
CONSTANT AREA SIZE
OOOOH
VARIAB~E AREA SIZE a 0061H
MAXIMUM STACK SIZE = OOOAH
349 ~INES READ
o PROGRAM ERROR(S)
--liND OF""

1141D

OD
97D
100

p~/M-e6 COMPI~ATIDN

230832-22

3-95

APPLICATION
. NOTE

AP-66

June 1989

Using the 8292 GPIB Controller

Order Number: 231324-002

3-96

USING THE 8292 GPIB
CONTROLLER

CONTENTS

PAGE

INTRODUCTION . ....................... 3-98
GPIB/IEEE 488 OVERVIEW ............ 3-98
HARDWARE ASPECTS OF THE
SYSTEM ............................
8291 Talker/Listener ...................
8292 Controller ........................
8293 Bus Transceivers .................
ZT7488/18 GPIB Controller ............

3-104
3-104
3-105
3-105
3-108

8292 COMMAND DESCRIPTION ...... 3-110
SOFTWARE DRIVER OUTLINE ....... 3-114
Initialization ............................ 3-115
Talker/Listener ........................ 3-115
Send Data ............................. 3-115
Receive Data .......................... 3-117
Transfer Data .......................... 3-119
Controller .............................. 3-119
Trigger ................................. 3-119
Device Clear ........................... 3-120
Serial Poll .............................. 3-120
Parallel Poll ............................ 3-121
Pass Control ........................... 3-123
Receive Control ........................ 3-124
Service Request ....................... 3-126
System Controller ...................... 3-126
Remote ................................ 3-126
Local .................................. 3-126
Interface Clear/Abort ................... 3-127
INTERRUPT AND DMA
CONSIDERATIONS ................. 3-127
APPLICATION EXAMPLE ............. 3-128
CONCLUSION ......................... 3-129
APPENDIX A .......................... 3-130
Source Listings .................. 3-130-3-147
APPENDIX B .......................... 3-148
test Cases for the Software Drivers .... 3-148
APPENDIX C .......................... 3-154
Remote Message Coding ............... 3-154
3-97

inter

AP-66

INTRODUCTION
The Intel® 8292 is a preprogra~med UPITM-41A that
implements the Controller function of the IEEE Std
488-1978 (GPIB, HP-IB, IEC Bus, etc.). In order to
function the 8292 must be used with the 8291 Talker/
Listener and suitable interface and transceiver logic
such as a pair of Intel 8293s. In this configuration the
system has the potential to be a complete GPIB Controller when driven by the appropriate software. It has
the following capabilities: System Controller, send IFC
and Take Charge, send REN, Respond to SRQ, send
Interface messages, Receive Control, Pass Control, Parallel Poll and Take Control Synchronously.
This application note will explain the 8292 only in the
system context of an 8292, 8291, two 8293s and the
driver software. If the reader wishes to learn more
about the UPI-4IA aspects of the 8292, Intel's Application Note AP-41 describes the hardware features and
programming characteristics of the device. Additional
information on the 8291 may be obtained in the data
sheet. The 2893 is detailed in its data sheet. Both chips
will be covered here in the details that relate to the
GPIB controller.
The next section of this application note presents an
overview of the GPIB in a tutorial, but comprehensive
nature. The knowledgeable reader may wish to skip this
section; however, certain basic semantic' concepts introduced there will be used throughout this note.
Additional sections cover the view of the 8292 from the
CPU's data bus, the interaction of the 3 chip types
(8291, 8292, 8293), the 8292's software protocol and
the system level hardware/software protocol. A brief
description of interrupts and DMA will be followed by
an application example. Appendix A contains. the
source code for the system driver software.

GPIBIIEEE 488 OVERVIEW
Design Objectives
WHAT IS THi; IEEE 488 (GPIB)?'

The experience of designing systems for a variety of
applications in the early 1970's caused Hewlett-Packard to define a standard intercommunication mechanism which would allow them to easily assemble instrumentation systems of varying degrees of complexity. In
a typical situation each instrument designer designed
hislher own interface from scratch. Each one was inconsistent in terms of electrical levels, pin-outs on a
connector, and types of connectors. Every time they

built a system they had to invent new cables and new
documentation just to spedfy the cabling and interconnection procedures.
Based on this experience, Hewlett-Packard began to define a new interconnection scheme. They went further
than that, however, for they wanted to specify the typical communication protocol for systems of instruments.
So in 1972, Hewlett-Packard came out with the first
version of the bus which since has been modified and
standardized by a committee of several manufacturers,
coordinated through the IEEE, to perfect what is now
. known as the IEEE 488 Interface Bus (also known as
the HPIB, the GPIB and the IEC bus). While this bus
specification may not be perfect, it is a good compromise of the various desires and goals of instrumentation
and computer peripheral manufacturers to produce a
common interconnection mechanism. It fits most instrumentation systems in use today and also fits very
well the microcomputer I/O bus requirements. The basic design objectives for the GPIB were to:
I) Specify a system that is easy to use, but has all of the
terminology and the definitions related to that system precisely spelled out so that everyone uses the
saine language when discussing the GPIB.
2) Define all ofthe mechanical, electrical, and functional interface requirements of a system, yet not define
any of the device aspects (they are left up to the
instrument designer).
3) Permit a wide range of capabilities of instruments
and computer peripherals to use a system simultaneously and not degrade each other's performance.
4) Allow different manufacturers' equipment to be connected together and work together on the same bus.
5) Define a system that is good for limited distance interconnections.
6) Define a system with minimum restrictions on performance of the devices.
7) Define a bus that allows asynchronous communication with a wide range of data rates.
8) Define a low cost system that does not require extensive and elaborate interface logic for the low cost
instruments, yet provides higher capability for the
higher cost instruments if desired.
9) Allow systems to exist that do not need a central
controller; that is, communication directly from one
instrument to another is possible.
Although the GPIB was originally designed for instrumentation systems, it became obvious that most of
these systems would be controlled by a calculator or
computer. With this in mind several modifications were
made to the original proposal before its final adoption
as an international standard. Figure I lists the salient
characteristics of the GPIB as both an instrumentation
bus and as a computer I/O bus.

3-98

AP-66

requires special attention to considerations beyond the
scope of this note. Although not required, data buffering in each device will improve the overall bus performance and allow utilization of more of the bus bandwidth.

Data Rate
1M bytes/s, max
250k bytes/s, typ
Multiple Devices
15 devices, max (electrical limit)
8 devices, typ (interrupt flexibility)
Bus Length
20 m, max
2 m/device, typ
Byte Oriented
8-bit commands
8-bit data
Block Multiplexed
Optimum strategy on GPIB due to
setup overhead for commands
Interrupt Driven
Serial poll (slower devices)
Parallel poll (faster devices)
Direct Memory Access
One DMA facility at controller
serves all devices on bus
Asynchronous
One talker
3-wire handshake
Multiple listeners
I/O to I/O Transfers
Talker and listeners need not
include microcomputer/controller

Multiple Devices-Many microcomputer systems used
as computers (not as components) service from three to
seven peripherals. With the GPIB, up to 8 devices can
be handled easily by I controller; with some slowdown
in interrupt handling, up to IS devices can work together. The limit of 8 is imposed by the number of unique
parallel poll responses available; the limit of IS is set by
the electrical drive characteristics of the bus. Logically,
the IEEE 488 Standard is capable of accommodating
more device addresses (31 primary, each potentially
with 31 secondaries).
Bus Length-Physically, the majority of microcomputer systems fit easily on a desk top or in a standard 19/1
(48-cm) rack, eliminating the need for extra long cables. The GPIB is designed typically to have 2m of
length per device, which accommodates most systems.
A line printer might require greater cable lengths, but
this can be handled at the lower speeds involved by
using extra dummy terminations.
Byte Oriented-The 8-bit byte is almost universal in
I/O applications; even 16-bit and 32-bit computers use
byte transfers for most peripherals. The 8-bit byte
matches the ASCII code for characters and is an integral sUbmultiple of most computer word sizes. The
GPIB has an 8-bit wide data path that may be used to
transfer ASCII or binary data, as well as the necessary
status and control bytes.

}

Figure 1. Major Characteristics of GPIB as
Microcomputer 1/0 Bus

The bus can be best understood by examining each of
these characteristics from the viewpoint of a general
microcomputer I/O bus.

Data Rate-Most microcomputer systems utilize peripherals of differing operational rates, such as floppy
discs at 31k or 62k bytes/s (single or double density),
tape cassettes at 5k to 10k bytes/s, and cartridge tapes
at 40k to 80k bytes/so In general, the only devices that
need high speed I/O are 0.5/1 (1.3-cm) magnetic tapes
and hard discs, operational at 30k to 781k bytes/s, respectively. Certainly, the 2S0k-bytes/s data .rate that
can be easily achieved by the IEEE 488 bus is sufficient
for microcomputers and their peripherals, and is more
than needed for typical analog instruments that take .
only a few readings per second. The IM-byte/s maximum data rate is not easily achieved on the GPIB and

3-99

Block Multiplexed-Many peripherals are block oriented or are used in a block mode. Bytes are transferred in
a fixed or variable length group; then there is a wait
before another group is sent to that device, e.g., one
sector of a floppy disc, one line on a printer or type
punch, etc. The GPIB is, by nature, a block multiplexed bus due to the overhead involved in addressing
various devices to talk and listen. This overhead is less
bothersome if it only occurs once for a large number of
data bytes (once per block). This mode of operation
matches the needs of microcomputers and most of their
peripherals. Because of block multiplexing, the bus
works best with buffered memory devices.
Interrupt Driven-Many types of interrupt systems exist, ranging from complex, fast, vectored/priority networks to simple polling schemes. The main tradeoff is
usually cost versus speed of response. The GPIB has
two interrupt protocols to help span the range of applications. The first is a single service request (SRQ) line
that may be asserted by all interrupting devices. The
controller then polls all devices to find out which wants
service. The polling mechanism is well defined and can

AP-66

be easily automated. For higher performance, the parallel poll capability in the IEEE 488 allows up to eight
devices to be polled at once--each device is assigned to
one bit of the data bus. This mechanism provides fastrecognition of an interrupting device. A drawback is
the frequent need for the controller to explicitly conduct a parallel poll, since there is no equivalent of the
SRQ line for this mode.

Asynchronous Transfers-An asynchronous bus is desirable so that each device can transfer at its own rate.
However, there is still a strong motivation to buffer the
data at each device when used in large systems in order
to speed up the aggregate data rate on the bus by allowing each device to transfer at top speed. The GPIB is
asynchronous and uses a special 3-wire handshake that
allows data transfers from one talker to many listeners.

Direct Memory Access (DMAJ-In many applications,
no immediate processing of I/O data on a byte-by-byte
basis is needed or wanted. In fact, programmed transfers slow down the data transfer rate unnecess~rily in
these cases, and higher speed can be obtained using
DMA. With the GPIB, one DMA facility at the controller serves all devices. There is no need to incorporate complex logic in each device.

I/O to I/O Transfers-In practice, I/O to I/O transfers
are seldom' done due to the need for processing data
and changing formats or due to mismatched data rates.
However, the GPIB can support this mode of operation
where the microcomputer is neither the talker nor one
of the listeners.

rrrrr

DEVICE A
ABLE TO
TALK. LISTEN.
AND
CONTROL

ruf

DATA BUS

(e.g. computer)

DEVICE B
ABLE TO
TALK AND
LISTEN

(e.g. digital
multime.er)

(f--- "DEVICE C
ONLY ABLE
TO LISTEN

(e.g. signal

DATA BYTE
TRANSFER
CONTROL

==1-

generalor)

GENERAL
INTERFACE
MANAGEMENT

(
OEVICE 0
ONLY ABLE
TO TALK

(e.g. counter)

0101."(1DATA
NPUT10UTPUT)

DAV (DATA VAllO)
NRFD (NOT READY FOR DATA)
NDAC(NO T DATA ACCEPTED)
IFC (INTER FACE CLEAR)
ATN (ATTE NTION)
SRQ (SERV ICE REQUEST)
REN (REM OTE ENABLE)
EOI (ENO. OR·IDENTIFY)

231324-1

Figure 2. Interface Capabilities and Bus Structure

3-100

inter

AP-66

GPIB Signal Lines
DATA BUS

The lines DIOI through DI08 are used to transfer addresses, control information and data. The formats for
addresses and control bytes are defined by the IEEE
488 standard (see Appendix C). Data formats are undefined and may be ASCII (with or without parity) or
binary. Dial is the Least Significant bit (note that this
will correspond to bit a on most computers).

NDAC-Not Data Accepted. This handshake line is asserted by a Listener to indicate it has not yet accepted
the data or control byte on the DIO lines. Note that the
Controller will not see NDAC deasserted (i.e., data accepted) until all devices have deasserted NDAC.
DAV-Data Valid. This handshake line is asserted by
the Talker to indicate that a data or control byte has
been placed on the DIO lines and has had the minimum
specified settling time.

010

--fL.._ _ _--I~-n(.._____~-

MANAGEMENT BUS
H-

A TN-Attention. This signal is asserted by the Controller to indicate that it is placing an address or control byte on the Data Bus. ATN is de-asserted to allow
the assigned Talker to place status or data on the Data
Bus. The Controller regains control by reasserting
ATN; this is normally done synchronously with the
handshake to avoid confusion between control and data
bytes.
EOI-End or Identify. This signal has two uses as its
name implies. A talker may assert EOI simultaneously
with the last byte of data to indicate end of data. The
Controller may assert EOI along with ATN to initiate a
Parallel Poll. Although many devices do not use Parallel Poll, all devices should use EOI to end transfers
(many currently available ones do not).
SRQ-Service Request. This line is like an interrupt: it
may be asserted by any device to request the Controller
to take some action. The Controller must determine
which device is asserting. SRQ by conducting a Serial
Poll at its earliest convenience. The device deasserts
SRQ when polled.
IFC-Interface Clear. This signal is asserted only by
the System Controller in order to initialize all device
interfaces to a known state. After deasserting IFC, the
System Controller is the active controller of the system.

REN-Remote Enable. This. signal is asserted only by
the System Controller. Its assertion does not place devices into Remote Control mode; REN only enables a
device to go remote when addressed to listen. When in
Remote, a device should ignore its front panel controls.

DAY

L-

H-,...,1'--______n ..____
rlL______1l.

NRFO L _ - - - '

NOAC: - _ _ _ _ _

231324-2

Figure 3. GPIB Handshake Sequence

GPIB Interface Functions
There are ten (10) interface functions specified by the
IEEE 488 standard. Not all devices will have all functions and some may only have partial subsets. The ten
functions are summarized below with the relevant section number from the IEEE document given at the beginning of each paragraph. For further information
please see the IEEE standard.
1) Sll-Source Handshake (section 2.3). This function provides a device with the ability to properly
transfer data from a Talker to one or more Listeners using the three handshake lines.
2) All-Acceptor Handshake (section 2.4). This function provides a device with the ability to properly
receive data from the Talker using the three handshake lines. The AH function may also delay the
beginning (NRFD) or end (NDAC) of any transfer.
3) T-Talker (section 2.5). This function allows a device to send status and data bytes when addressed
to talk. An address consists of one (Primary) or two
(primary and Secondary) bytes. The latter is called
an extended Talker.

TRANSFER BUS

NRFD-Not Ready For Data. This handshake line is
asserted by a listener to indicate it is not yet ready for
the next data or control byte. Note that the Controller
will not see NRFD deasserted (i.e., ready for data) until
all devices have deasserted NRFD.

3-101

Intel

AP-66

4) L-Listener (section 2.6). This function allows a
device to receive data when addressed to listen.
There can be extended Listeners (analogous to extended Talkers above).
5) SR-Service Request (section 2.7). This function
allows a device to request service (interrupt) the
Controller. The SRQ line may be asserted asynchronously.
6) RL-Remote Local (section 2.8). This function allows a device to be operated in two modes: Remote
via the GPIB or Local via the manual front panel
controls.
i) PP-Parallel Poll (section 2.9). This function allows a device to present one bit of status to the
Controller-in-charge. The device need not be addressed to talk and no handshake is required.
8) .DC-Device Clear (section 2.10). This function allows a device to be cleared (initialized) by the Controller. Note that there is a difference between DC
(device clear) and the IFC line (interface clear).
9) DT-Device Trigger (section 2.11). This function
allows a device to have its basic operation started
either individually or as part of a group. This capability is often used to synchronize several instruments.
10) C-Controller (section 2.12). This function a.llows
a device to send addresses, as well as universal and
addressed commands to other devices. There may
be more than one controller on a system, but only
one may be the controller-in-charge at anyone
time.

GNO

REN

0108
0107
0106

SHIELD
ATN
SRQ
IFC
NOAC
NRFO
OAV
EOI

0104
0103
0102
0101

231324-3

Figure 4. GPIB Connector

GPIB Signal Levels

At power-on time the controller that is hardwired to be
the System Controller becomes the active controller-incharge. The System Controller has severalunique capabilities including the ability to send Interface Clear
(IFC-c1ears all device· interfaces and returns control
to the System Controller) and to send Remote Enable
(REN-allows devices to respond to bus data once they
are addressed to listen). The System Controller may
optionally Pass Control to another controller, if the system software has the capability to do so.

The GPIB signals are all TIL compatible, low true
signals. A signal is asserted (true) when its electrical
voltage is less than 0.5 volts and is deasserted (false)
when it is greater than 2.4 volts. Be careful not to become confused with the two handshake signals, NRFD
. and NDAC which are also low true (i.e. > 0.5 volts
implies the device is Not Ready For Data).
The Intel 8293 GPIB transceiver chips ensure that all
relevant bus driver/receiver specifications are met. Detailed bus electrical specifications may be found in Section 3 of the IEEE Std 488-1978. The Standard is the
ultimate reference for all GPIB questions.

GPIB Message Protocols
GPIB Connector
The GPIB connector is a standard 24-pin industrial
connector such as Cinch or Amphenol series 57 MicroRibbon. The IEEE standard specifies this connector, as
well as the signal connections and the mounting hardware.
The cable has 16 signal lines and 8 ground lines. The
maximum length is 20 meters with no more than two
meters per device.

The GPIB is a very flexible communications medium
and as such has many possible variations of protocols.
To bring some order to the situation, this section will
discuss a protocol similar to the one used by Ziatech's
ZT80 GPIB controller for Intel's MULTIBUSTM computers. The ZT80 is a complete high-level interface
processor that executes a set of high level instructions
that map directly into GPIB actions. The sequerices of
commands, addresses and data for these instructions
provide a good example of how to use the GPIB (additional information is available in the ZT80 Instruction
Manual). The 'null' at the end of each instruction is for
cosmetic use to remove previous information from the
DIO lines.

3-102

inter

AP-66

DATA-Transfer a block of data from device A to devices B, C ...
1) Device A Primary (Talk) Address
Device A Secondary Address (if any)
2) Universal Un1isten
3) Device B Primary (Listen) Address
Device B Secondary Address (if any)
Device C Primary (Listen) Address
etc.
4) First Data Byte
Second Data Byte

Last Data Byte (EO!)
5) Null

TRIGR-Trigger devices A, B ... to take action
1) Universal Unlisten
2) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3) Group Execute Trigger
4) Null
PSCTL-Pass control to device A
1) Device A Primary (Talk) Address
Device A Secondary Address (if any)
2) Talk Control
3) Null
CLEAR-Clear all devices
1) Device Clear
2) Null
REMAL-Remote Enable
1) Assert REN continuously
GOREM-Put devices A, B, ... into Remote
1) Assert REN continuously
2) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3) Null

2) Go To Local
3) Null

LOCAL-Reset all devices to Local
1) Stop asserting REN
LLKAL-Prevent all devices from returning to Local
1) Local Lock Out
2) Null
SPOLL-Conducts a serial poll of devices A, B, ...
1) Serial Poll Enable
2) Universal Unlisten
3) ZT 80 Primary (Listen) Address
ZT 80 Secondary Address
4) Device Primary (Talk) Address
Device Secondary Address (if any)
5) Status byte from device
6) Go to Step 4 until all devices on list have been polled
7) Serial Poll Disable
8) Null
PPUAL-Unconfigure and disable Parallel Poll response from all devices
1) Parallel Poll Unconfigure
2) Null
ENAPP-Enable Parallel Poll response in devices A, B,
1) Universal Unlisten
2) Device Primary (Listen) Address
Device Secondary Address (if any)
3) Parallel Poll Configure .
4) Parallel Poll Enable
5) Go to Step 2 until all devices on list have been configured.
6) Null

DISPP-Disable Parallel Poll response from devices A;
B, ...
1) Universal Unlisten
2) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.
3) Disable Parallel Poll
4) Null
This Ap Note will detail how to implement a useful
subset of these controller instructions.

GOLOC-Put devices A, B, ... into Local
1) Device A Primary (Listen) Address
Device A Secondary Address (if any)
Device B Primary (Listen) Address
Device B Secondary Address (if any)
etc.

3-103

intJ

AP·66

from the CPU; the other seven control various features
of the 8291.

HARDWARE ASPECTS OF THE
SYSTEM

The 8291 interface functions will be software configured in this application example to the following subsets for use with the 8292 as a controller that does not
pass control. The 8291 is used only to provide the
handshake logic and to send and receive data bytes. It
is not acting as a normal device in this mode, as it never
sees ATN asserted.
SH1 Source Handshake
AH 1 Acceptor Handshake
T3 Basic Talk-Only
L1
Basic Listen-Only
SRO No Service Requests
RLO' No RemotelLocal
PPO No Parallel Poll Response
DCO No Device Clear
DTO No Device Trigger

8291 GPIB Talker/Listener
The 8291 is a custom designed chip that implements
many of the non-controller GPIB functions. It provides
hooks so the user's software can implement additional
features to complete the set. This chip is discussed in
detail in its data sheet. The major features are summarized here:
- Designed to interface microprocessors to the GPIB
- Complete Source and Acceptor Handshake
- Complete Talker and Listener Functions with extended addressing
.
- Service Request, Parallel Poll, Device Clear, Device
Trigger, Remote/Local functions
- Programmable data transfer rate
- Maskable interrupts
- On-chip primary and secondary address recognition
- 1-8 MHz clock range
- 16 registers (8 read, 8 write) for CPU interface
- DMA handshake provision
- Trigger output pin
- On-chip EOS (End of Sequence)

If control is passed to another controller, the 8291 must

The pinouts and block diagram are shown in Figure 5.
One of eight read registers is for data transfer to the
CPU; the other seven allow the microprocessor to monitor the GPIB states and various bus and device conditions. One of the eight write registers IS for data transfer

be reconfigured to act as a talkerllistener with the following subsets:
SH1 Source Handshake
AH 1 Acceptor Handshake
T5
Basic Talker and Serial Poll
L3
Basic Listener
SRI Service Requests
Ri, 1 Remote/Localwith Lockout
PP2 Reconfigured Parallel Poll
DC 1 Device Clear
DTt Device Trigger
CO Not a Controller

Block Diagram

Pin Configuration

GPIB CONTROL

T.O NON·INVERTING
BUS TRANSCEIVERS

I
I

T/RCONTROL

231324-5

231324-4

Figure 5. 8291 Pin Configuration and Block Diagram

3-104

AP-66

The status register is used to pass Interrupt Status information to the master CPU (AO = 1 on a read).

Most applications do not pass control and the controller is always the system controller (see 8292 commands
below).

The DBBOUT register is used to pass one of five other
status words to the master based on the last command
written into DB BIN. DBBOUT is accessed when AO
= 0 on a Read. The five status words are Error Flag,
Controller Status, GPIB Status, Event Counter Status
or Time Out Status.

8292 GPIB Controller
The 8292 is a preprogrammed Intel 8051A that provides the additional functions necessary to implement a
GPIB controller when used with an 8291 Talker/Listener. The 8041A is documented in both a user's manual and in AP-41. The following description will serve
only as an outline to guide the later discussion.

DBBIN receives either commands (AO = 1 on a Write)
or command related data (AO = 0 on a write) from the
master. These command related data are Interrupt
Mask, Error Mask, Event Counter or Time Out.

The 8292 acts as an intelligent slave processor to the
main system CPU. It contains a processor, memory,
I/O and is programmed to perform a variety of tasks
associated with GPIB controller operation. The on-chip
RAM is used to store information about the state of the
Controller function, as well as a variety of local variables, the stack and certain user status information.
The timer/counter may be optionally used for several
time-out functions or for counting data bytes transferred. The I/O ports provide the GPIB control signals,
as well as the ancillary lines necessary to make the
8291, 2, 3 work together.

8293 GPIB Transceivers
The 8293 is a multi-use HMOS chip that implements
the IEEE 488 bus transceivers and contains the additianallogic required to make the 8291 and 8292 work
together. The two option strapping pins are used to
internally configure the chip to perform the specialized
gating required for use with 8291 as a device or with
8291/92 as a controller.
In this application example the two configurations used
are shown in Figure 7a and 7b. The drivers are set to
open collector or three state mode as required and the
special logic is enabled as required in the two modes.

The 8292 is closely coupled to the main CPU through
three on-chip registers that may be independently accessed by both the master and the 8292 (UPI-41A).
Figure 6 shows this Register Interface. Also refer to
Figure 12.

I\.~VL ~

I\.

- r-~ - 0...
~
~

IZ:

CPU

~~ ~t::1'\
r--

'-V

- - -

RO
WR

STATUS

OBBIN

OBBOUT

I
231324-48

0
0
0
0
1

0
1
0
1

0
0
1
1

1
1
0
0

READ DB BOUT
READ STATUS
WRITE DBBIN (DATA)
WRITE DBBIN (COMMAND)
NO ACTION

FigureS. UPI-41A Registers

3-105

I
I UPI-41A

Ap·66

b. 8293 Mode 3

8. 8293 Mode 2

MODE 2

:mRI
~

NDAC

tilW

iiiifij

T/1I1

Dio,

IFC
SYC

iiEii

SRa*

lT1iII
lTR

ATN*

EOI*

EIII

231324-7

231324-6

Figure 7

829112/3 Chip Set
Figure 8 shows the four chips interconnected with the
special logic explicitly shown.
The 8291 acts only as the mechanism to put commands
and addresses on the bus while the 8292 is asserting
ATN. The 8291 is tricked into believing that the ATN
line is not asserted by the ATN2 output of the ATN
transceiver and is placed in Talk-only mode by the
CPU. The 8291 then acts as though it is sending data,
when in reality it is sending addresses and/or commands. When the 8292 deasserts ATN, the CPU software must place the 8291 in Talk-only, Listen-only or
Idle based on the implicit knowledge of how the controller is going to participate in the data transfer. In
other words, the 8291 does not respond directly to addresses or commands that it sends on the bus on behalf
ofthe Controller. The user software, through the use of
Listen-only or Talk-only, makes the 8291 behave as
though it were addressed.

Although it is not a common occurrence, the GPIB
specification allows the Controller to set up a data
transfer between two devices and not directly participate in the exchange. The controller must know when
to go active again and regain Control. The chip set accomplishes this through use of the "Continuous Acceptor Handshake cycling mode" and the ability to detect
EOI or EOS at the end of the transfer. See XFER in the
Software Driver Outline below.
If the 8292 is not the System Controller as determined
by the signal 011 its SYC pin, then it must be able to

respond to an IFC within 100 p.sec. This is accomplished by the cross-coupled NORs in ~e 7a which
deassert the 8293's internal version of CIC (Not Controller-in-Charge). This condition is latched until the
8292's firmware has received the IFCL (interface clear
received latch) signal by testing the IFCL input. The
firmware then sets its signals to reflect the inactive condition and clears the 8293's latch.

3-106

inter

AP-66

MODE 3

~tf

ATNO
IFCL

rJAfI

DAY

~
~~

OPTB

OAY*

T/R1

Di"O"1-8

j)jQj

REN

DlO2

EOi

Di03

T/R2

lllO4

jjj"()5

NRFO

0106

NOAC

0107

Rr--

Ol 07*

0108

~r--

01 08*

Rr-Rr-[M=r--

8291

010

~r-~r--

EOi
ATN

01 05*

01 06*

ATN

SRO
t---

MODE 2

NOAC

DAY
NRFO

SIR

T/R1
IFC

IFC

SYC

SYC
REN

REN

8292

OPTA

SRO

SAO

ATNl

ATNI
ATN

EOi2

EOl2
ATNO

Ji'fN"lj

e
Ii

~
SIR

T~r--

iFCL

CLTH

CLTH
CIC

CIC

NOAC*
NRFO'"
IFC*
REN*

SRO*
ATN*

_~JT

v=R=
S R

T/R2

iFCL

TiC

~
SR

EOI

COUNT

T'C

OPTA

~ OPTB

EOI*

T C

~
231324-8

Figure 8. Talker/Listener/Controller

3-107

inter

Ap·66

In order for the 8292 to conduct a Parallel Poll the
8291 must be able to capture the PP response on the
DIO lines. The only way to do this is to fool the 8291
by putting it into Listen-only mode and generating a
DA V condition. However, the bus spec does not allow
a DAV during Parallel Poll, so the back-to-back 3-state
buffers (see Figure 7b) in the 8293 isolate the bus and
allow the 8292 to generate a local DAV for this purpose. Note that the 8291 cannot assert a Parallel Poll
response. When the 8292 is not the controller-in-charge
the 8291 may respond to PPs and the 8293 guarantees
that the DIO drivers are in "open collector" mode
through the OR gate (Figure 7b).

Figure 9 shows the card's block diagram. The
ZT7488/18 plugs into the STD bus, a 56 pin 8 bit microprocessor oriented bus. An 8085 CPU card is also
available on the STD bus and will be used to execute
the driver software.
The 8291 uses I/O Ports 60H to 67H and the 8292 uses
I/O Ports 68H and 69H. The five interrupt lines are
connected to a three-state buffer at I/O Port 6FH to
facilitate polling operation. This is required for. the
TCI, as it cannot be read internally in the 8292. The
other three 8229 lines (SPI, IBF, OBF) and the 8291's
INT line are also connected to minimize the number of
I/O reads necessary to poll the devices.

ZT7488/18 GPIB Controller

NDAC is connected to COUNT on the 8292 to allow
byte counting on data transfers. The example driver
software will not use this feature, as the software is
simpler and faster if an internal 8085 register is used for
counting in software.

Ziatech's GPIB Controller, the ZT7488/18 will be used
as the controller hardware in this Application Note.
The controller consists of an 8291, 8292, an 8 bit input
port and TTL logic equivalent to that shown in Figure 8.

DATA BUS
00-07

8291

BUFFERS

;---Y

r---I----'3-STATE
BUFFERS

10 EXP'

ADDRESS

AS-A7

ADDRESS

CARD
SELECT
DECODER

A3.A4

INTERFACE
LOGIC

r--- -

r--.

'--

829.

WT'
SYS RESET"

r;>MA
CONNECTOR

CLOCK'

RD·

I-----

t---'-

'-ADDRESS
Ag.A>

'---

~t>----O

PORT
SELECT
DECODER

'-ff--

GP'8

co NNECTOR

TRANS-

INTERRUPT

PORT

CEIVERS

f::L....-

231324-9
'INDICATES ACTIVE LOW LOGIC

Figure 9. ZT7488/18 GPIB Controller

3-108

inter

AP-66

READ REGISTERS

PORT #

WRITE REGISTERS

'"I0-17-'--1-01-6"'1-0-15"'1-0-14--'1-01-3--'1-0-12--;-1-0-11-'--0-10-' 6H 100710061 0051 0041 003 I 0021 001 I 000
DATA IN

DATA OUT

I CPT I APT I GET I ENO I OEC I ERR I 80

61 H I CPT I APT I GET I ENO I OEC I ERR I BO I

rsv 1 56 1 55 1 54 1 53 1 52 1 51
SERIAL POLL MODE

INTERRUPT STATUS 1

INTERRUPT MASK 1

liNT 15PA51 LLO I REM 15PA5CILLOCIREMCIA05CI
INTERRUPT MASK 2

INTERRUPT STATUS 2
I 58 15R051 56 1 55 1 54 1 53 1 52 1 51
SERIAL POLL STATUS

I 63H

I ton 1 Ion 1 EOI 1LPA5 1 TPA5 1 LAI TA IMJMNI 64H I TO 1 LO 1 0 1 0 1 0 1 0
ADDRESS STATUS
ADDRESS MODE

1AOM 11 AOMOI

ICPT71 CPT61CPT51 CPT41 CPT31 CPT21 CPT1 1CPTO I 65H ICNT21cNT11 CNTO ICOM41 COM31COM21COM11COMOI
COMMAND PASS THROUGH

AUX MODE

X I OTO I OLO IA05-01 A04-0 IA03-0IA02-0IA01-0 1 66H I AR5 I OT I OL I A051 A04 I A03 I A02 I A01 I
ADDRESS 0
ADDRESS 0/1
X 1 OT1 I OL1 IA05-11A04-1IA03-1IA02-1IA01-11 67H I EC71 EC61 EC5 I EC41 EC3 I EC21 EC1 I ECO I
ADDRESS 1

EOS

Figure 10. 8291 Registers

1 "1

iiEiiii

., O " I t - - - = " - - - - - - - - - - - - - - - - - - - - - - - - - ,

A, ~

10if

B2~O'~~-~~-_r-----~---------_,

IT :: ~

wnJ....::::

°3

MEMW

04tt+h--..!:mw'-"w~-_t__,_----_+_r__--------_+_.....,

.~
1_

IO/M.------"
RE.ET---'---t-H--t+-t---~__t__t-__lV

IN~-1
'NTA~1===f:an===f*=E=~===t:~~------j-t_t----,--,
07.00_

1::..

11~1~~

RST RD W R G

- , / 07-DO

INTI-----II

•

Ii
HOLDHLDACLK-

'-'I
f-

OACKO

p-------c

r----<1CS

DACK

ORaD I - - DREa
8251-5
8291
HRa

I----

~~
It~
elK

~-~
_~

ft!
~

RSO

CLKCS

~~~
SRa
=~=~
.TN

~
~
TIRl

Tel

---<

2142

~~N
SRa
D7-DO
COUNT 8292
CIC

~~~~

T/R2

-..,.~

:~:~
IFCL

;~6H

r W _14_

~
~

1-1---

=--_______--"":.:.::..-c...:....::_ _ _

A15 . . .

~:tl

I~[~~~~~~~~~~

~R';";R

RST RD WR
IBFI

~~~~
~

8259-5

-vt

AOt--

_ _ _ _ _ _ _ _ _ _ _ _-..:..::_ _~=___---1
231324-10

Figure 11. DMA/lnterrupt GPIB Controller Block Diagram
3-109

inter

AP-66

The application example will not use DMA or interrupts; however, the Figure II block diagram includes
these features for completeness. '

ister. Note the two letter mnemonics to be used in later
discussions. The CPU must not write into the 8292
while IBF (Input Buffer Full) is a one, as information
will be lost.

The 8257-5 DMA chip can be used to transfer data
between the RAM and the S291 Talker/Listener. This
mode allows a faster data rate on the GPIB and typically will depend on the 8291's EOS or EO! detection to
terminate the transfer. The 8259-5 interrupt controller
is used to vector the five possible interrupts for rapid
software handling of the various conditions.

Direct Commands
Both the Interrupt Mask (1M) and, the. Error Mask
(EM) register may be directly written with the LSB of
the address bus (AO) a "0". The firmware uses the MSB
of the data written to differentiate between 1M and EM.

8292 COMMAND DESCRIPTION

LOAD INTERRUPT MASK

This section discusses each command in detail arid relates them to a particular GPIB activity. Recall that
although the S04IA has only two read registers and one
write register, through the magic of on-chip firmware
the 8292 appears to have six read registers .and five
write registers. These are listed in Figure 12. Please see
the S292 data sheet for detailed definitions of each regREAD FROM 8292

This command loads the Interrupi Mask with 'D7 - DO.
Note that D7 must be a "I" and that interrupts are
enabled by a corresponding "I" bit in this register. IFC
interrupt cannot .be masked off; however, when the
8292 is the System Controller; sending an ABORT
command will not cause an IFC interrupt.

PORT'"

WRITE TO 8292

INTERRUPT STATUS
I SYC IERRI SRO lEvi

COMMAND FIELD

X IIFCR I IBF I OBF I

B9H

LI1:,..J1_1"---,-1---=---1I...,:o-,--p.....
l-...:c,--,-l--=-.c--,-l_c,,,--,---c=--.J

DO
ERROR FLAG·

INTERRUPT MASK

11 ISP11 TCI ISYCIOBFII IBFI I

I SRO

Do
CONTROLLER STATUS·
ICSBsl CA I

IREN 10AVI
0

X I X Isycsi IFC I REN I SRO
GPIB (BUS) STATUS·

10 1 0 1 0 1
TIME OUT STATUS·

EVENT COUNTER·

BSH

101 0 1 0

BSH

IDI

BSH

EOI 1
SYC 1 IFC 1 ANTI 1 SRO
EVENT COUNTER STATUS·

0 1 0

ERROR MASK

I
0 1 D

1 0 1 ,0 1

• Note: These registers are accessed by a special
'
utility command.

Figure 12. 8292 Registers

3-110

1 0 1 0 1 0
TIMEOUT"

inter

AP-66

When the 8292 has completed the command, IBF will
become a "0" and will cause an interrupt if masked on.

LOAD ERROR MASK

This command loads the Error Mask with D7-DO.
Note that D7 must be a zero and that interrupts are
enabled by a corresponding "1" bit in this register.

Utility Commands
These commands are used to read or write the 8292
registers that are not directly accessible. All utility
commands are written with AO = 1, D7 = D6 = D5
= 1, D4 = O. D3-DO specify the particular command.
For wiiting into registers the general sequence is:
1) wait for IBF = 0 in Interrupt Status Register
2) write the appropriate command to the 8292,
3) write the desired register value to the 8292 with AO
= 1 with no other writes intervening,
4) wait for indication of completion from 8292 (IBF =
0).
For reading a register the general sequence is:
1) wait for IBF = 0 in Interrupt Status Register

WTOUT-Write to Time Out Register
(Command = OEIH)
The byte written following this command will be used
to determine the number of increments used for the
time out functions. Because the register is 8 bits, the
maximum time out is 256 time increments. This is
probably enough for most instruments on the GPIB but
is not enough for a manually stepped operation using a
GPIB logic analyzer like Ziatech's ZT488. Also, the
488 Standard does not set a lower limit on how long a
device may take to do each action. Therefore, any use
of a time out must be able to be overridden (this is a
good general design rule for service and debugging considerations).
The time out function is implemented in the 8292's
firmware and will not be an accurate time. The counter
counts backwards to zero from its initial value. The
function may be enabled/disabled by a bit in the Error
mask register. When the command is complete IBF will
be set to a "0" and will cause an interrupt if masked on.

2) write the appropriate command to the 8292
3) wait for a TCI (Task Complete Interrupt)
4) Read the value· of the accessed register from the 8292
with AO = o.

WEVC-Write to Event Counter
(Command = OE2H)
The byte written following this command will be loaded into the event counter register and event counter
status for byte counting. The internal counter is incremented on a high to low transition of the COUNT (Tl)
input. In this application example NDAC is connected
to count. The counter is an 8 bit register and therefore
can count up to 256 bytes (writing 0 to the EC implies a
count of 256). If longer blocks are desired, the main
CPU must handle the interrupts every 256 counts and
carefully observe the timing constraints.
Because the counter has a frequency range from 0 to
133 kHz when using a 6 MHz crystal, this feature may
not be usable with all devices on the GPIB. The 8291
can easily transfer data at rates up to 250 kHz and even
faster with some tuning of the system. There is also a
500 ns minimum high time requirement for COUNT
which can potentially be violated by the 8291 in continuous acceptor handshake mode (i.e., TNDDVI +
TDVND2 - C = 350 + 350 = 700 max). When
cable delays are taken into consideration, this problem
.
will probably never occur.

REVC-Read Event Counter Status
(Command = OE3H)
This command transfers the content of the Event
Counter to the DBBOUT register. The firmware then
sets TCI = 1 and will cause an interrupt if masked on.
The CPU may then read the value from the 8292 with
AO = o.

RINM-Read Interrupt Mask Register
(Command = OE5H)
This command transfers the content of the Interrupt
Mask register to the DBBOUT register. The firmware
sets TCI = 1 and will cause an interrupt if masked on.
The CPU may then read the value.

RERM-Read Error Mask Register
(Command = OEAH)
This command transfers the content of the Error Mask
register to the DBBOUT register. The firmware sets
TCI = 1 and will cause an interrupt if masked on. The
CPU may then read the value.

3-111

RCST-Read Controller Status Register
(Command = OE6H)

intJ

Ap·66

This command transfers the content of the Controller
Status register to the DBBOUT register. The firmware
sets TCI = 1 and will cause an interrupt if masked on.
The CPU may then read the value.

Operation Commands. It is not meant to replace the
complete controller state diagram in the IEEE Standard.
RST-Reset (Command

RTOUT-Read Time Out Status Register
(Command = OE9H)

OF2H)

This command has the same effect as an external reset
applied to the chip's pin #4. The 8292's actions are:
1) All outputs go to their electrical high state. This
means that SPI, TCI, OBFI, IBFI, CLTH will be
TRUE and all'other GPIB signals will be FALSE.
2) The 8292's firmware will cause the above mentioned
five signals to go FALSE after approximately 17.S
JLs (at 6 MHz).
3) These registers will be cleared: Interrupt Status, Interrupt Mask, Error Mask, Time Out, Event Counter, Error Flag.
4) If the 8292 is the System Controller (SYC is TRUE),
then IFC will be sent TRUE for approximately
100 JLs and the Controller function will end up in
charge of the bus. If the 8292 is not the System Controller then it will end up in an Idle state.
S) TCI will not be set.

This command transfers the content of the Time Out
Status register to the DBBOUT register. The firmware
sets TCI = 1 and will cause an interrupt if masked on.
The CPU may then read the value.
If this register is read while a time-out function is in
process, the value will be the time remaining before
time-out occurs. If it is read after a time-out, it will be
zero. If it is read when no time-out is in process, it will
be the last value reached when the previous timing occurred.
RBST-Read Bus Status Register
(Command = OE7H)
This command causes the firmware to read the GPIB
management lines, DAY and the SYC pin and place a
copy in DBBOUT. TCI is set to "1" and will cause an
interrupt if masked on. The CPU may read the value.
RERF-Read Error Flag Register
(Command = OE4H)
This command transfers the content of the Error Flag
register to the DBBOUT register. The. firmware sets
TCI = I and will cause an interrupt if masked on. The
CPU may then read the value.
This register is also placed in DBBOUT by an lACK
command if ERR remains set. TCI is set to "1" in this
case also.

,--------------,
I

lACK-Interrupt. Acknowledge
(Command = Al A2 A3 A4 1 AS 1 1)

L ___ _

This command is used to acknowledge any combinations of the five SPI interrupts (AI-AS): SYC, ERR,
SRQ, EY, and IFCR. Each bit AI-AS is an individual
acknowledgement to the corresponding bit in the Interrupt Status Register. The command clears SPI but it
will be set again if all of the pending interrupts were not
acknowledged.
If A2 (ERR) is "1", the Error Flag register is placed in
DBBOUT and TCI is set. The CPU may then read the
Error Flag without issuing an RERF command.

IAaO~~~~yC------~

-.!Y~~O~R~~ _ _ _ _ ~

231324-11

Figure 13. 8292 Command Flowchart

RSTI-Reset Interrupts (Command

OF3)

This command clears all pending interrupts and error
flags. The 8292 will stop waiting for actions to occur
(e.g., waiting for ATN to go FALSE in a TCNTR command or waiting for the proper handshake state in a
TCSY command). TCI will not be set.
ABORT-Abort all operations and Clear Interface
(Command = OF9H)

Operation Commands
The following diagram (Figure 13) is an attempt to
show the interrelationships among the various 8292

If the 8292 is not the System Controller this command
acts like a NOP and flags a USER ERROR in the Error Flag Register. No TCI will occur.

3-112

inter

AP-66

If the 8292 is the system Controller then IFC is set
TRUE for approximately 100 fts and the 8292 becomes
the Controller-in-Charge and asserts ATN. TCI will be
set, only if the 8292 was NOT the CIC.

sets ATN FALSE and TCI TRUE. This command is
used as part of the Send, Receive, Transfer and Serial
Poll System commands (see next section) to allow the
addressed talker to send data/status.

STCNI-Start Counter Interrupts
(Command = OFEH)
Enables the EV Counter Interrupt. TCI will not be set.
Note that the counter must be enabled by a GSEC command.

If the data transfer does not start within the specified
Time-Out, the 8292 sets TOUT2 TRUE in the Error
Flag Register and sets SPI (if enabled). The controller
continues waiting for a new command. The CPU must
decide to wait longer or to regain control and take corrective action.

SPCNI-Stop Counter Interrupts
(Command = OFOH)
.

GSEC-Go To Standby and Enable Counting
(Command = OF4H)

The 8292 will not generate an EV interrupt when the
counter reaches O. Note that the counter will continue
counting. TCI will not be set.

This command does the same things as GTSB but also
initializes the event counter to the value previously
stored in the Event Counter Register (default value is
256) and enables the counter. One may wire the count
input to NDAC to count bytes. When the counter
reaches zero, it sets EV (and SPI if enabled) in Interrupt Status and will set EV every 256 bytes thereafter.
Note that there is a potential loss of count information
if the CPU does not respond to the EV /SPI before another 256 bytes have been transferred. TCI will be set
at the end of the command.

SREM-Set Interface to Remote Control
(Command = OF8H)
If the 8292 is the System Controller, it will set REN
and TCI TRUE. Otherwise it only sets the User Error
Flag.

SLOC-Set Interface to Local Mode
(Command = OF7H)

TCSY-Take Control Synchronously
(Command = OFDH)

If the 8292 is the System Controller, it will set REN
FALSE and TCI TRUE. Otherwise, it only sets the
User Error Flag.

EXPP-Execute Parallel Poll
(Command = OF5H)
If not Controller-in-Charge, the 8292 will treat this as a
NOP and does not set TCI. If it is the Controller-inCharge then it sets IDY (EO! & ATN) TRUE and
generates a local DAV pulse (that never reaches the
GPIB because of gates in the 8293). If the 8291 is configured as a listener, it will capture the Parallel Poll
Response byte in its data register. TCI is not generated,
the CPU must detect the BI (Byte In) from the 8291.
The 8292 will be ready to accept another command
before the BI occurs; therefore the 8291 's BI serves as a
task complete indication.

GTSB-Go To Standby (Command = OF6H)
If the 8292 is not the Controller-in-Charge, it will treat
this command as a NOP and does not set TCI TRUE.
Otherwise, it goes to Controller Standby State (CSBS),

If the 8292 is not in Standby, it treats this command as
a NOP and does not set TCI. Otherwise, it waits for the
proper handshake state and sets ATN TRUE. The 8292
will set TOUT3 if the handshake never assumes the
correct state and will remain in this command until the
handshake is proper or a RSTI command is issued. If
the 8292 successfully takes control, it sets TCI TRUE.
This is the normal way to regain control at the end of a
Send, Receive, Transfer or Serial Poll System Command. If TCSY is not successful, then the controller
must try TCAS (see warning below).

TCAS-Take Control Asynchronously
(Command = OFCH)
If the 8292 is not in Standby, it treats this command as
a NOP and does not set TCI. Otherwise, it arbitrarily
sets ATN TRUE and ECI TRUE. Note that this action
may cause devices on the bus to lose a data byte or
cause them to interpret a data byte as a command byte.
Both Actions can result in anomalous behavior. TCAS
should be used only in emergencies. If TCAS fails, then
the System Controller will have to issue an ABORT to
clean things up.

3-113

Ap·66

GIDL-Go to Idle (Command = OFIH)

In order to use polling with the 8292 one must enable
TCI but not connect the pin to the CPU's interrupt pin.
TCI must be readable by some means. In this application example it is connected to bit I port 6FH on the
ZT7488/18. In addition, the other three 8292 interrupt
lines and the 8291 interrupt are also on that port (SPIBit 2, IBFI-Bit 4, OBFI-Bit 3, 8291 INT-Bit 0).

If the 8292 is not the Controller in Charge and Active,
then it treats this command as a NOP and does not set
TCI. Otherwise, it sets ATN FALSE, becomes Not
Controller in Charge, and sets TCI TRUE. This command is used as part of the Pass Control System Command.

These drivers assume that only primary addresses will
be used on the GPIB. To use secondary addresses, one
must modify the test for valid talk/listen addresses
(range macro) to include secondaries.

TCNTR-Take (Receive) Control
(Command = OFAH)
If the 8292 is not Idle, then it treats this command as a
NOP and does not set TCI. Otherwise, it waits for the
current Controller-in-Charge to set ATN FALSE. If
this does not occur within the specified Time Out,· the
8292 sets TOUT! in the Error Flag Register and sets
SPI (if enabled). It ~ill not proceed until ATN goes
false or it receives an RSTI command. Note that the
Controller in Charge must previously have sent this
controller (via the 8291 's command pass through register) a Pass Control'message. When ATN goes FALSE,
the 8292 sets CIC, ATN and TCI TRUE and becomes
Active.

SOFTWARE DRIVER OUTLINE
The set of system commands discussed below is shown
in Figure 14. These commands are implemented in software routines executed by the main CPU.
The following section assumes that the Controller is the
System Controller and.will not Pass Control. This is a
valid assumption for 99 + % of all controllers. It also
assumes that no DMA or Interrupts. will be used. SYC
(System Control Input) should not be changed after
Power-on in any system-it adds unnecessary complexity to the CPU's software.

3-114

INIT

INITIALIZATION

TalkerI Listener
SEND
SEND DATA
RECV
RECEIVE DATA
XFER
TRANSFER DATA
Controller
TRIG
DCLR
SPOL
PPEN
PPDS
PPUN
PPOL
PCTL
RCTL
SRQD

GROUP EXECUTE TRIGGER
DEVICE CLEAR
SERIAL POLL
PARALLEL POLL ENABLE
PARALLEL POLL DISABLE
PARALLEL POLL UNCONFIGURE
PARALLEL POLL
PASS CONTROL
RECEIVE CONTROL
SERVICE REQUESTED

System Controller
REME REMOTE ENABLE
LOCL
LOCAL
IFCL
ABORT IINTERFACE CLEAR

Figure 14. Software Drive Routines

AP-66

Set internal counter to 3 MHz to match the clock input
coming from the 8085 by writing 23H to Port 65H.
High speed mode for the handshakes will not be used
here even though the hardware uses three-state drivers.

Initialization
8292-Comes up in Controller Active State when SYC
is TRUE. The only initialization needed is to enable the
TCI interrupt mask. This is done by writing OAOH to
Port 68H. .

No interrupts will be enabled now. Each routine will
enable the ones it needs for ease of polling operation.
The INT bit may be read through Port 6FH. Clear
both interrupt mask registers.

8291-Disable both the major and minor addresses because the 8291 will never see the 8292's commands/addresses (refer to earlier hardware discussion). This is
done by writing 60H and OEOH to Port 66H.

Release the chip's initialization state by writing 0 to
Port 65H.

Set Address Mode to Talk-only by writing 80H to Port
64H.

INIT:
Enable-8292
Enable TCI
Enable-8291
Disable major address
Disable minor address
ton
Clock frequency
All interrupts off
Immediate execute pon

;Setup In. pins for Port 6FH
;Task complete must be on
;In controller usage, the 8291
;Is set to talk only and/or listen only
;Talk only is our rest state
;3 MHz in this ap note example
;Releases 8291 from init. state

Talker/Listener Routines
SEND DATA
SEND

This system command sends data from the CPU to one
or more devices. The data is usually a string of ASCII
characters, but may be binary or other forms as well.
The data is device-specific.
My Talk Address (MTA) must be output to satisfy the
GPIB requirement of only one talker at a time (any
other talker will stop when MTA goes out). The MTA
is not needed as far as the 8291 is concerned-it will be
put into talk-only mode (ton).

This routine assumes a non-null listener list in that it
always sends Univeral Unlisten. If it is desired to send
data to the listeners previously addressed, one could
add a check for a null list and not send UNL. Count
must be 255 or less due to an 8 bit register. This routine
also always. uses an EOS character to terminate the
string output; this could easily be eliminated and rely
on the count. Items in brackets ( ) are optional and will
not be included in the actual code in Appendix A.

3-115

inter

Ap·66

SEND:

Output-to-8291 MTA, UNL
Put EOS into 8291
While 20H ~ listener ~ 3EH
output-to-8291 listener
Increment listen list pointer
Output-to-8292 GTSB
Enable-8291
Output EOI on EOS sent
I f count < > 0 then
While not (end or count
0)
(could check tout 2 here)
Output-to-8291 dat;a
Increment data buffer pointer
Decrement count
Output-to-8292 TCSY
(If tout3 then take control async)
Enable 8291
No output EOI on EOS sent
Return

;We will talk, nobody listen
;End of string compare character
;GPIB listen addresses are
; n space n thru n> n ASCII
;Address all listeners
;8292 stops asserting ATN, go to standby
;Send EOI along with EOS character
;Wait for EOS or end of count
;Optionally check for stuck bus-tout 2
;Output all data, one byte at a time
;8085 CREG will count for us
;8292 asserts ATN, take control sync.
;If unable to take control sync.
;Restore 8291 to standard condition

B = 40H

231324-12

Figure 15. Flowchart for Receive Ending Conditions

3·116

AP-66

CONTROLLER
8291,8292

LSTN
"!"

CTLR

DEVICE

TALK
"0"

TALK
"R"

DEVICE

LSTN

TALK

"+"

"K"

DEVICE

TALK
"II"

231324-13

Figure 16. SEND to "1", "2", "> "; "ABCD"; EOS

"0"

RECEIVE DATA
RECV

This system command is used to input data from a
device. The data is typically a string of ASCII characters.
This routine is the dual of SEND. It assumes a new
talker will be specified, a count of less than 257, and an
EOS character to terminate· the input. EO! received
will also terminate the input. Figure 15 shows the flow
chart for the RECV ending conditions. My Listen Address (MLA) is sent to keep the GPIB transactions

totally regular to facilitate analysis by a GPIB logic
analyzer like the Ziatech ZT488. Otherwise, the bus
would appear to have no listener even though the 8291
will be listening.
Note that although the count may go to zero before the
transmission ends, the talker will probably be left in a
strange state and may have to be cleared by the controller. The count ending of RECV is therefore used as an
error condition in most situations.

3-117

inter

AP-66

RECV:

Put EOS into 8291
I f 40H s; talker s; 5EH then
Output-to-829l talker
Increment talker pointer
Output-to-829l UNL, MLA
Enable-829l
Holdoff on end
End on EOS received
lon, reset ton
Immediate execute pon
Output-to-8292 GTSB
While not (end or count
0
(or tout2))
Input-from-829l data
Increment data buffer pointer
Decrement count
(If count = 0 then error)
Output-to-8292 TCSY
(If ToutS then take control async.)
Enable-829l
No holdoff on end
No end on EOS received
ton, reset Ion
Finish handshake
Immediate execute pon
Return error-indicator

;End of string compare character
;GPIB talk addresses are
;n@n thru n /\ n ASCII
;Do this for consistency's sake
;Everyone except us stop listening
;Stop when EOS character is
;Detected by 8291
;Listen only (no talk)
;8292 stops asserting ATN, go to standby
;wait for EOS or EOI or end of count
;optionally check for stuck bus-tout2
;input data, one byte at a time
;Use 8085 C register as counter
;Count should not occur before end
;8292 asserts ATN take control
;If unable to take control sync.
;Put 8291 back as needed for
;Controller activity and
;Clear holdoff due to end
;Complete holdoff due to end, if any
;Needed to reset Ion

CONTROLLER
8211,1202

TALK
"A"

LOTH

..,..

eTLR

TALK
"A"

DEVICE
LSTH

TALK

"I"

"0"

TAlK
"Q-

TALK
-R"

LSTN
"2"

DEVICE

TALK
-K"

LSTH
"."

TALK
"K"

DEVICE

LSTN
">"

LSTH

TALK

">"

"A"

231324-15

231324-14

Figure 18. XFER from" /\ "to "1", "2", "+";
EOS = ODH

Figure 17. RECV from "R"; EOS = ODH

3-118

inter

AP-66

This is accomplished through the use of the 8291's continuous acceptor handshake mode while in listen-only.

TRANSFER DATA
XFER

This system command is used to transfer data from a
talker to one or more listeners where the controller
does not participate in the transfer of the ASCII data.

This routine assumes a device list that has the ASCII
talker address as the first byte and the string (one or
more) or ASCII listener addresses following. The EOS
character or an EO! will cause the controller to take
take control synchronously and thereby terminate the
transfer.

XFER:

Output-to-8291: Talker, UNL
While 20H S listen S 3EH
Output-to-8291: Listener
Increment listen list pointer
Enable-8291
lon, no ton
Continuous AH mode
End on EOS received
Immediate execute PON
Put EOS into 8291
Output-to-8292: GTSB
Upon end (or tout2) then
Take control synchronously
Enable-8291
Finish handshake
Not continuous AH mode
Not END on EOS received
ton
Immediate execute pon
Return

;Send talk address and unlisten
;Send listen address
;Controller is pseudo listener
;Handshake but don't capture data
;Capture EOS as well as EOI
;Initialize the 8291
;Set up EOS character
;Go to standby
;8292 waits for EOS or EOI and then
;Regains control
;Go to Ready for Data

Controller
GROUP EXECUTE TRIGGER

TRIG
This system command causes a group execute trigger
(GET) to be sent to all devices on the listener list. The
intended use is to synchronize a number of instruments.

TRIG:

Output-to-8291 UNL
While 20H S listener s 3EH
Output-to-8291 Listener
Increment listen list pointer
Output-to-8291 GET
Return

;Everybody stop listening
;Check for valid listen address
;Address each listener
;Terminate on any non-valid character
;Issue group execute trigger

3-119

AP-66

CONTROLLER

8291.8292

8291,8292
LSTH

LSTH

TALK
"A"

"'"

TALK
"A"

TALK
"0"

TALK
"A"

DEVICE
LSTH
"2"

DEVICE
LSTH

TALK
"K"

~,,,,,

DEVICE

DEVICE
TALK'
·11·

LSTH

">"

TALK
"K':

...TALK
".

LSTH

">"

231324-17

231324-16

Figure 19. TRIG "1", "+"

Figure 20. DCLR "1", "2'"

DEVICE CLEAR

DCLR < Listener list>
This system command causes a device clear, (SDC) to

bC sent to all devices on the listener list. Note that this

is not intended to clear the GPIB interface of the deviCe, but should clear the device-specific logic,

DCLR:

Output-to-829l UNL
While 20H s listener s 3EH
Output-to-829l Listener
Increment listen'list pointer
Output-to-829l SDC
Return

;Everybody stop listening
;Check for valid listen.address
;Address each listener
;Terminate on any non-valid character
;Selective device clear

SERIAL POLL

SPOL
This system command sequentially addresses the designated devices and receives one byte of status from each.

The bytes are stored in the buffer in the same order as
the devices appear on the talker list. MLA is output for
completeness,

3-120

infef

AP-66

SPOL:
Output-to-8291 UNL, MLA, SPE

While 40H ,,; talker ,,; 5 EH
Output-to-8291 talker
Increment talker list pointer
Enable-8291
lon, reset ton
Immediate execute pon
Output-to-8292 GTSB
Wait for data in (BI)
Output-to-8292 TCSY
Input-from-8291 data
Increment buffer pointer
Enable 8291
ton, reset Ion
Immediate execute pon
Output-to-8291 SPD

;Unlisten, we listen, serial poll enable
;Only one byte of serial poll
;Status wanted from each talker
:Check for valid transfer
:Address each device to talk
:One at a time
:Listen only to get status
:This resets ton
;Go to standby
;Serial poll status byte into 8291
:Take control synchronously
:Actually get data from 8291

:Reset Ion
:Send serial poll disable after all
devices polled

Return

CONTROLLER
8291,8292
TALK
"A"

LSTN

"'"

TALK
"A"

DEVICE
LSTN

"'"

lSTN

TALK

"1"

"Q"

LSTN
"2"

TALK
~R"

LSTN

TALK
"K"

","

LSTN

lSTN

">"

TALK
"1\"

231324-18

231324-19

Figure 21. SPOL "Q", "R", "K"," 1\"

Figure 22" PPEN "2"; iP3P2P1 = 01118

PARALLEL POLL ENABLE

PPEN
This system command configures one or more devices to respond to Parallel Poll, assuming they implement subset
PPI. The configuration information is stored in a buffer with one byte per device in the same order as

3-121

inter

AP-66

devices appear on the listener list. The configuration byte has the format XXXXIP3P2Pl as defined by the IEEE
Std. P3P2Pl indicates the bit # to be used for a response and I indicates the assertion value. See Sec. 2.9.3.3 of the
Std. for more details.

PPEN:

Output-to-829l UNL
While 20H ,;: Listener ,;: 3EH
Output-to-829l listener
Output-to-829l PPC, (PPE or data)
Increment listener list pointer
Increment buffer pointer
Return

;Universal unlisten
;Check for valid listener
;Stop old listener, address new
;Send parallel poll info
;Point to next listener
;One configuration byte per listener

PARALLEL POLL DISABLE

PPDS
This system command disables one or more devices from responding to a Parallel Poll by issuing a Parallel Poll
Disable (PPD). It does not deconfigure the devices.
PPDS:

Output-to-829l UNL
While 20H ,;: Listener ,;: 3EH
Output-to-829l listener
Increment listener list pointer
Output-to-829l PPC, PPD
Return

;Universal Unlisten
;Check for valid listener
;Address listener
;Disable PP on all listeners

CONTROLLER

8291,8292
LSTN

8291,8292
LSTN
"I"

TALK
"A"

I !

TALK

"A"

...
y

TALK

DEVICE
TALK
"0"

LSTN

"'"

"0"

DEVICE

I\"

TALK
"R"

LSTN

TALK

"2"

"R"

DEVICE

I\"
V

TALK

LSTN

TALK
"K"

"+"

"K"

...
v

TALK

"""

DEVICE
LSTN
'!>"

TALK

"A"

231324-21

231324-20

Figure 23. PPDS "1", "+", ">"

Figure 24. PPUN
3-122

inter

AP-66

PARALLEL POLL UNCONFIGURE

PPUN

This system command deconfigures the Parallel Poll response of all devices by issuing a Parallel Poll Unconfigure
message.
PPUN:

;Unconfigure all parallel poll

Output-to-8291 PPU
Return

CONDUCT A PARALLEL POLL

PPOL

served by the controller, the CPU should explicitly acknowledge each device by a device-dependent data
string. Otherwise, the response bit will still be set when
the next Parallel Poll occurs. This command returns
one byte of status.

This system command causes the controller to conduct
a Parallel Poll on the GPIB for approximately 12.5
fLsec (at 6 MHz). Note that a parallel poll does not use
the handshake; therefore, to ensure that the device
knows whether or not its positive response was obPPOL:

Enable-8291
lon
Immediate execute pon
Output-to-8292 EXPP
Upon BI
Input-from-8291 data
Enable-8291
ton
Immediate execute pon
Return Data (status byte)

;Listen only
;This resets ton
;Execute parallel poll
;When byte is input
;Read it
;Talk only
;This resets lon

PASS CONTROL

PCTL < talker>

This system command allows the controller to relinquish active control of the GPIB to another controller.
Normally some software protocol should already have
informed the controller to expect this, and under what
conditions to return control. The 8291 must be set up
PCTL:
I f 40H :;:: talker :;:: 5EH then
i f talker < > MTA then

output-to-8291 talker, TCT
Enable-8291
not ton, not lon
Immediate execute pon
My device address, mode 1
Undefined command pass through
(Parallel Poll Configuration)
Output-to-8292 GIDL
Return

to become a normal device and the CPU must handle
all commands passed through, otherwise control cannot be returned (see Receive Control below). The controller will go idle.

;Cannot pass control to myself
;Take control message to talker
;Set up 8291 as normal device
;Reset ton and lon
;Put device number in Register 6
;Required to receive control
;Optional use of PP
;Put controller in idle

3-123

inter

AP-66

CONTROLLER
1291,1212

CONTROLLEA
8291,8292

~
;.
'T'

LSTH
"1"

"A"

5!1~

0101

DEVICE

DEVICE·

LaTH

TALK"

"I"

"Q"

_0102

LSTH
"1"

DEVICE

TALK
"Q"

DEVICE

LITH

TALK

LSTN

"2"

TALK

"A"

"2"

"A"·

0103

DEVICE
LaTN

"."

DEVICE
TALK

LSTH

"1("

" "

DEVICE
LaTH
"Y

TALK
, "K"

DEVICE
TALK
"A"

LaTH

TALK

231324-22

Figure 25. PPOL

LaTH

TALK

">"

"1\"

"C"

CONTROLLER

231324-23

RECEIVE CONTROL
Figure 26. PCTL "C"

RCTL
This system command is used to get control back from
the current controller-in-charge if it has passed control
to this inactive controller, Most GPIB systems do not
use more than one controller and therefore would not
.need this routine.

whereby the controller-in-charge sends a data message
to the soon-to-be-active controller. This message should
give the current state of the system, why control is being passed, what to do, and when to pass control hack.
Most of these issues are beyond the scope of this Ap
Note.
.

To make passing and receiving control a manageable
event, the system designer should specify a protocol

3-124

inter

AP-66

RCTL:

Upon CPT
If (command=TCTl then
If TA then
Enable-8291
Disable major device number
ton
Mask off interrupts
Immediate execute pon
Output-to-8292 TCNTR
Enable-8291
Valid command
Return valid
Else
Enable-8291
Invalid command
Else
Enable-8291
Invalid command
Return invalid

;Wait for command pass through bit in 8291
;If command is take control and
;We are talker addressed
;Controller will use ton and Ion
;Talk only mode
;Take (receivel control
;Release handshake

;Not talker addr. so TCT·not for us
;Not TCT, so we don't care

"~~~td

SYSTEM
CONTROLLER
8291,8292

8291.8292

LSTN

"".

TALK
"A"

CTLR

DEVICE
LSTN

TALK

LSTN

TALK

"I"

"0"

"I"

"0"

TALK
"R"

LSTN
"2"

TALK
"K"

LSTN

TALK
"/I."

LSTN

DEVICE

r-..

DEVICE
LSYN

''2"

DEVICE

.....

-v' LSTN
. ...
~

TALK

"."

"C"

"R"

DEVICE
LSTN

"."

LSTN

TALK

DEVICE

~
v

15a:

DEVICE

r-..

TALK
·"K"

DEVICE

">"

TALK

..,,"

231324-25

Figure 28. REME

CONTROLLER

231324-24

Figure 27. RCTL

3·125

infef

AP-66

SERVICE REQUEST

SRQD
This system command is used to detect the occurrence of a Service Request on the GPIB. One or more devices may
assert SRQ simultaneously, and the CPU would normally conduct a Serial Poll after calling this routine to determine
which devices are SRQing.

SRQD:

SRQ then
Output-to-8292 IACK.SRQ
Return SRQ
Else return no SRQ

;Test 92 status bit
;Acknowledge it

System Controller
REMOTE ENABLE

REME
This system command asserts the Remote Enable line (REN) on the GPIB. The devices will not go remote until they
are later addressed to listen by some other system command.

REME:

Output-to-8292 SREM
Return

;8292 asserts remote enable line

LOCAL

LOCL
This system command deasserts the REN line on the GPIB. The devices will go local immediately.

LOCL:

Output-to-8292 SLOC
Return

;8292 stops asserting remote

3·126

ena~le

inter

AP-66

SYSTEM
CONTROLLER
8291.8292
LSTN

"'"

SYSTEM
CONTROLLER
LSTN

TALK
"A"

"'"

CTLR

TALK
"A"

!!:
DEVICE

DEVICE
TALK
"0"

LSTN
"I"

TALK
"R"

LSTN
"2"

LSTN

TALK

LSTN

"."

"K"

"."

TALK
"A"

LSTN

LSTN
"1"

DEVICE

DEVICE
LSTN
"2"

DEVICE

">"

TALK
"R"

DEVICE

LSTN

TALK
"0"

">"

TALK
"10."

231324-27

231324-26

Figure 30. IFCL

Figure 29. LOCL
INTERFACE CLEARI ABORT

IFCL

This system command asserts the GPIB's Interface
Clear (IFC) line for at least 100 microseconds. This
causes all interface logic in all devices to go to a known
state. Note that the device itself mayor may not be

reset, too. Most instruments do totally reset upon IFC.
Some devices may require a DCLR as well as an IFCL
to be completely reset. The (system) controller becomes
Controller-~-Charge.

IFCL:

Output-to-8292 ABORT
Return

;8292 asserts Interface Clear
;For 100 microseconds

INTERRUPTS AND DMA
CONSIDERATIONS
The previous sections have discussed in detail how to
use the 8291, 8292, 8293 chip set as a GPIB controller
with the software operating in a polling mode and using
programmed transfer of the data. This is the simplest
mode of use, but it ties up the microprocessor for the
duration of a GPIB transaction. If system design constraints do not allow this, then either Interrupts and/or
DMA may be used to free up processor cycles.

The 8291 and 8292 provide sufficient interrupts that
one may return to do other work while waiting for such
things as 8292 Task Completion, 8291 Next Byte In,
8291 Last Byte Out, 8292 Service Request In, etc. The
only difficulty lies in integrating these various interrupt
sources and their matching routines into the overall
system's interrupt structure. This is highly situation"
specific and is beyond the scope of this Ap Note.
The strategy to follow is to replace each of the WAIT
routines (see Appendix A) with a return to the main,
code and provide for the corresponding interrupt to
bring the control back to the next section of GPIB

3-127

AP-66

MAIN CODE

INTERRUPT CODE

GPIB SUBROUTINE

USER:

SEND:

ACTIVATE
SEND ..

(WAIT 0)

== ____________
~ ~~O?
INT'

(WAIT 0)
_ _ _ _ _- - - - - - ~
GPIBBO?
- -......I - - - - - - - = : = : - - - - - - - - - ( W A I T 0)

~INT:

~ IN:PIB BO?-

-(WAITT)

~ INT: GPIB BO?
----=~
GPIB TCI?~
--

ETC.

231324-28

Figure 31. GPIB Interrupt and Co-Routine Flow of Control
code. For example WAlTO (Wait for Byte Out of
8291) would be replaced by having the BO interrupt
enabled and storing the (return) address of the next
instruction in a known place. This co· routine structure
will then be activated by a BO interrupt. Figure 31
shows an example of the flow of control.
DMA is also useful in relieving the processor if the
average length of a data buffer is long enough to overcome the extra time used to set up a DMA chip. This
decision will also be a function of a data rate of the
instrument. The best strategy is to use the DMA to
handle only the data buffer transfers on SEND and
RECV and to do all the addressing and control just as
shown in the driver descriptions.

be found.on the GPIB. The Ziatech ZT488 GPIB analyzer is used to single step the bus to facilitate debugging the system. It also serves as a training/familiarization aid for newcomers to the bus.
This example will set up the function generator to output a specific waveform, frequency and amplitude. It
will then tell the counter to measure the frequency and
Request Service (SRQ) when complete. The program
will then read in the data. The assembled source code
will be found at the end of Appendix A.

ZT7488/18

CONTROLLER

Another major reason for using a DMA chip is to increase the data rate and therefore increase the overall
transaction rate. In this case the limiting factor becomes the time used to do the addressing and control of
the GPIB using software like that in Appendix A. The
data transmission"time becomes insignificant at DMA
speeds unless extremely long buffers are used.
Refer to Figure 11 for a typical DMA and interrupt
based design using the 8291, 8292, 8293. A system like
this can achieve a 250K byte transfer rate while under
DMA control.

LSTN

"'-

CTLR

TALK
"A-

HP 5328A

COUNTER
TALK
"Q-

LSTN

"'-

HP 3325A

FUNCTION
GENERATOR
LSTN
"2-

TALK
"R"

APPLICATION EXAMPLE
ZT488

This section will present the code required to operate a
typical GPIB instrument set up as shown in Figure 32.
The HP5328A universal counter and the HP3325 function generator are typical of many GPIB devices; however, there are a wide variety of software protocols to
3-128

GPIB ANALYZER

231324-29

Figure 32. GPIB Example Configuration

intJ
SEND
LSTN: "2", COUNT:
;SETS UP FUNCTION
;COUNT EQUAL TO #
;EOS CHARACTER IS

AP-66

15, EOS: ODH, DATA: "FUIFR37KHAM2VO (CR)"
GEN. TO 37 KHZ SINE, 2 VOLTS PP
CHAR IN BUFFER
(CR) = ODH = CARRIAGE

SEND
LSTN: "1", COUNT: 6, EOS: "T" DATA: "PR4G7T"
;SETS UP COUNTER FOR P:INITIALIZE, F4: FREQ CHAN A
G7:0.1 HZ RESOLUTION, T:TRIGGER AND SRQ
;COUNT IS EQUAL TO # CHAR
WAIT FORSRQ
SPOL TALK: II Q", DATA: STATUS 1
;CLEARS THE SRO_IN THIS EXAMPLE ONLY FREQ CTR ASSERTS SRQ
RECV TALK: "Q", COUNT: 17, EOS: OAH,
DATA:"+
37000.0E+0" (CR) (LF)
;GETS 17 BYTES OF DATA FROM COUNTER
;COUNT IS EXACT BUFFER LENGTH
;DATA SHOWN IS TPYICAL HP5328A READING THAT WOULD BE RECEIVED

CONCLUSION
This Application Note has shown a structured way to
view the IEEE 488 bus and has given typical code sequences to make the Intel 8291, 8292, and 8293's behave as a controller of the GPIB. There are other ways
to use the chip set, but whatever solution is chosen, it
must be integrated into the overall system software.

The ultimate reference for GPIB questions is the IEEE
Std 488 -1978 which is available from IEEE, 345 East
47th St., New York, NY, 10017. The ultimate reference
for the 8292 is the source listing for it (remember it's a
pre-programmed UPI-41A) which is available from INSITE, Intel Corp., 3065 Bowers Ave., Santa Clara, CA
95051.

3-129

inter

AP-66

APPENDIX A

ISIS-II 838A/BA85 MACHO ASSE~BLER. V3. A
GPIR CON'rH.OLLER SUBROU'fINES
LOC

OBJ

LINE

SOURCE ST.A.TEMEN'r

I S'rI'fLE ('GPIR CON'rROLLER SUBROU'rINES I)
2
3
GPIB CONTROLLER SUBROUTINES

4
5
~

for Intel 8291, 8292 on ZT 74Bq/lA
Bert Forbes, Ziatech Corporation

7
8

2410 Broad Street
San Luis Ohispo, CA, USA 934{H

13AB

ee6B

BA61
B361
3A92
BBBI
3e13
BB8B
3a62

13
II
12
13
14
15
H

Genera 1 Defi nit ions & Equates
8291 Control Values

ORG

17 PRT91

EOU

18
19
23
21
22
,23
24
25
26
27
28
29
3A
31
32

IABBH

, I'or ZT748B/18 w/RBR5

: 8291 Base Port

Reg .e Data in & Data out
DIN
DOUT

EOU
EQU

INTI
INTHI
BOM

EQU
EOU
EQU
EQU
'EQU
EOU

~IH

ENDMK
CPT

;

PRT9l+" ~ 91 Data in reg
PRT9l+" ; 91 Data out req'

Req • I Interrupt 1 Constants
PRT9l+} ; INT Req 1
PRT9l+l : INT Mask Reg. 1
02
10H

; 91 80 I"l'TRP Mask
,91 BI INTRP Mask
; 91 Er-.JD INTRP Mask

BAH

;91 command pass thru lnt hit

Req .2 Interrupt 2

INT2

EOU

34
35
36
37
38
39

,
ADRMD
TON
LON
TLON
MODEl

Reg 14 Address !I1ode Constants
fWU
PRT9l+4 ;91 ad"ress lT,ode register t
EQU
eOH
;91 talk only mode & not listen only
EQU
49H
; 91 li sten only & not ton
EQU
"eOH
;91 talk Ii. listen only
EQU
91
;mode 1 addressing for device

PRT91+2

33
3B64
BBBB
8B4B

aBCe
eaal
a364
302a
eae2

9BB!

41
42 ADRST
43 EOIST
44 TA
45 LA

46
a965
3a23

47
48 AUXMD
49 CLKRT

Reg 14
EQU
EQU
EOU
EQU

Reg .5
EQU
EQU

(Read)
AdClress Status Register
PRT9l+4 ; reg '4
23H
2

:listener active

(Write) AuxilIary Mode Reqister
PRT9l+5 ;91 auxilIary mode rcqister
23H
;91 3 Mhz clock input

231324-30

3-130

inter

AP·66

0003
BB06

59 FNHSK
51 SDEOI

EQU

~0B~

03
Ali

EQI]

91 fininsh handshake command
91 send EOl wi th next hyte

52 AXRA

8~H

0901
0002
0003
0004
0098
B90F
0997
90A0
B901

53 HOHSK

EQU

91 aux. req A pattern
91 hold off h~nr1shake on all hytes

HOEND

EQU

91 holr) off handshake on end

55 CAHCY
56 EnEOS
57 EOIS

EOU

91 continuous AH eyel inq

EQU

EQU
EQU
EOU

B
AFH
e7H

91 end on EOS received
91 output EOI on EOS sent
91 valid command pass throuqh
91 invalid command pass through

EQU

0A0H

Aux. reg. B pattern

EQU

AIH

command pass thru enable

Reg !5

(Read)

58 VSCi1D

59
69
61
62
63

NVCMD
AXRB
CPTEN
,

CPTRG

EOU

EQU

PRT9l+5

Req l!'i

Address A/I req. constants

li5 ,

B067

66
67 AORAl
68 D'rOLl
59 OTOL2
70 ,
71 ,
72 EOSR

EQU

PRT9l+6

EOU

GAH

EOU

~E0H

Reg t7
EQU

Eas
Character Reqister
PRT9l+7

8292

CONTROL VALUES

:Disable major talker & listener
;Oisahle minor talker" listener

73 ;

74,
7S ;
76 ,

77,
0068

78
79 PRT92

EQU

PRT91+8 ,8292 Base Port t

81 INTMR
82 INTM
83

EQU

PRT92+9 ; 92 INTRP rlOV

ou'r
INX
J,~P

WAITO
IN
ANI

JNZ
WAITT
IN

;Wait for previous listener sent
INTI
BOM

7?3907.

A,M

PRTF
TCIF
?103114

Aiu

PRTF
TCIF

??~B95

;Sanli EOI wi th EOS character

;Wait for TCI to qo false

;Wait for TCI on GTSe
;Get task complete int,eto.
;Mask it
;Wait for task to be .complete

331
332 I
333 ,

delete next

1064 79

334

1965
1065
1069
196A
106C

336+
337
338 SEND3:
339
340
341

MOV
SETF
ORA

335
B7
CA88U
1A
03~0

342

A,C

;Get count
;Set flaqs

SENM

LDAX
OUT

Dou'r

CMP

instructions to make count of 0=2511

If count=0, send no data
Get data byte
Output to GPIB
'fest EOS •.. this is faster
and uses less code than usinq
91' sEND 0 r EOI bits

231324-34

3-134

inter
10~0

CA71'U

1070
1972
lB74
1977
1078
1079
107C
1071'
1080

OB61
E6A2
CA7910
13
00
C26910
C38BlA
13
UO

1081 OB61
1083 E602
loB5 CA8110
1888 3Et'O
1081'. D3~9
108C 3E8o
108E D365
1090 OB6F
1092 E~02
1994 C29310
1097
1099
1098
109E

OB6F
E692
CA9718
C9

AP-66

343
H4 SEND4:
345+??0806:
346+
347+
348
349
350
)';1
352 SEN05:
353
354

WAlTa
IN
ANI
JZ
INX
OCR
J~Z

J"P
INX
OCR
WAlTa
IN
ANI
3Z

lOAD 0360
10AF 23
10B0
1082
1984
lAB7
10B9

OB61
E692
CA80U
JE3F
0360

10BB 0861
lBBO E602
10BF C!'.BBlO

ao~

710886
0
C
SEN03
SEN05
0
C

qn finish

;Decrement count

,If count < > 0. qo send
;Else qo finish
; for consi~tency

INTI
80""
??""07

;Get IntI status
;Check for byte out
; If not, try a'lain
;assumptions for the next subroutine are met
;Take control syncronously

~::~~ i~r

*._ *_

38~

7E
FE49
1'1'.3911
FE5F
1'23911

;Get IntI status
;Check for byte out
,If nnt, try aqilin
; Increment buffer pointer

A,TCSY
""VI
OUT
C/l092
A,AXRA ; Reset send EOI on EOS
"'VI
OUT
AUXMO
WAITX
;Wa,it for TCl false
3~4+??8888: IN
PRTF
365+
1'.'11
TCIF
36~+
3NZ
?103"8
367
WAIT'r
;Wait for TCI
368+??0009 : IN
PRTF
iGet task complete int,etc.
369+
!'.NI
TCIF
379+
JZ
710089
task to be complete
371
RET
372 ;.11 _II __ • • • ___ II II_ * _1111_
* *_ ••• _1111 • • _11. _____ 1111 __ * ___ 1111 __ •
373
374
RECEIVE ROU'rINE
375
376
377 ; IN pu'r:
HL talker pointer
378
De nata buffer pointer
379
C count (max buffer size) " implies 2S~

~:~

10!'.2
101'.3
101'.5
101'.8
10!'.!'.

, If char = EOf;

INTI

;This ensures that the stant:1ard entry

355+170807:
356+
357+
358
359 SEN06:
369
361
362
363

;ou'rpUT:
3B2 ,CALLS:
383 ,OESTRO~S:
384 I
385 ,RETURNS:

1091' 78
101'.0 0367

SENDS

387
388
389 ,
390 RECV:
391
392
393+
394+
395+
396+
397+
398+
399+
400+
491+
402+
403
484
405
406
407+??09U:
408+
499+
410
411
412
413+179011 :
414+
415+

~il ~~S h~~~!~c~:rnted at

_ •••

* _____ *

by DE

None
A, BC;" DE, HL! F
A=0 normal

termination--EOS detected

A=40 £rror--- count overrun
A<4A or A>SEH Error--- ban talk ad<1ress

/lOV

ou'r

RANGE

A,S
EOSR

;Get BOS charaoter
;Output it to 91

40H, 5EH, RECV6

;Checks for value in range
;branches to label if not
~ in range .. Falls throuqh if
~ lower <- ( (H) (L) ) <=- upper ..
~Get next byte.
MOV
CPI
3M
CPI
JP

ou'r
INX

!'..M
4AH
RECV6
SEH+l
RECV6
DOUT

~valid if 4BH(= talk <=SEH
~Output talker to GPIB

;Incr pointer for consistency

ou'r

INTI
BOM
710010
A,UNL
DOUT

iGet Intl status
;Check for byte out
; If not, try .again
;Stop other 1 isteners

"'!'.ITO
IN
ANI
JZ

INTI
BOM
118A11

;Get IntI status
;Check' for byte out
~If not, try aqain

'''AI'ro
IN
Mil
JZ
MVI

231324-35

3-135

intJ
1eC2
1BC4
10CG
10CB

3E21
DH0
3£B6
D355

10CA DBIiI
1eee £5A2

1eCE CACA10
1eDl 3E4.
10D3 D3~4
10D5 AF
lBD6 D355
10DB 3EF6
19DA D3~9
10DC DB6F
1eD£ £632
10£0 C2DClB
lB£3
10E5
10£A
10EC
1.£D
U£F
10F2
UF3
UF5
10F8
UFA
19FB
lAFC
19FD
119.
1192

DB6F
£592
DB51
47
£619
C20511
78
£691
CAEA10
DB6.
12
13
9D
C2M19
9640
c31711

1195
1196
1108
110B
1100
1110
1112
1113
1114
1115

78
£691
C21911
OB61
C30611
oa60
12
13
0D
0600

1117 3EFD
1119 0369
I11B OB6F
1110 £692
111F C21B11
1122 086F
1124 £692
1126 CA2211

1129
1128
1120
112F
1131
1133

3£B0
0365
3£8.
0364
3£93
D365

1135 IIF
1136 0365
1138 78
~139 C9

AP-66

41~
~VI
A,MLA
; For completeness
417
OUT
Dou'r
418
~VI
A, AXRA+HOE"'ID+EDEOS
; Enti when
419
ou'r
AUXMD
;E05 or EDt & Holtloff
429
WALTa
421+179.12:
IN
INTI
;Get IntI status
422+
ANI
BaM
;Check for byte out
423+
JZ
770012
;If not, try again
424
~vI
A,LON
;Listen only
425
ADRM.D
ou'r
426
CLRA
; Irnmed iate XEO PQN
427+
XRA
A
IA XOR A =~
428
OUT
AUXMD
429
MVI
A,GTSB
:Goto stan~by
430
CM092
ou'r
431
WAITX
;Wait for Tel ... "
PRTF
432+??AA13: IN
TCIF
ANI
433+
434+
JNZ
??A?Jl3
435
WAITT
;wait for TCI=l
43fi+1?0014: IN
PRTF
;Get task complete lnt ,etc.
437+
TCIF
ANI
;Mask it
439 R£CVl:
IN
INTI
;Get 91 lnt status (END &/or Bt)
44.
/lOV
a,A
;Save it in B for Bt check later
441
ANI
ENOMK
;Check for EOS or EOI
442
JNZ
RECV2
;Yes end--- go wait for BI
MOV
443
A,B
;NO, ret~ieve status &
444
ANI
BIM
; check for BI
445
JZ
RECV1
:NO, go wait for either END or BI
44 fi
IN
DIN
;YES, 81--- get data
'447
STAX
o
;Store it in buffer
448
INX
o
;Increment buffer pointer
449
DCR
C
:Decrement Counter
450
JNZ
RECVl
;If count < > A go back' wait
451
MVI
;Else set error indicator
B,40"
452
JMP
RECV5
;And go take control
453 ,
454 R£CV2: MOV
A,B
;Retreive status
455 R£CV3: ANI
BIM
;Check for BI
456
JNZ
;If BI then ~o input data
RECV4
457
IN
INTI
;Else wait for last BI
458
JMP
RECV3
:In loop
459 RECV4:
III
OIN
;Get data byte
460
STAX
;Store it in buffer
D
461
INX
D
;Incr .data pointer
462
DCR
C
;Decrement count, but iqnore it
4~3
MVI
B,.
;Set normal completion indicators
464 ,
465 RECV5:
MVI
A,TCSY
;Take control synchronously
466
OUT
CM092
467
WAITX
;Wait for TCI=0i (7 tcy)
46B+179015: IN
PRTF
469+
ANI
TCIF
470+
JNZ
??0''15
471
WAITT
:Wait for TCI=1
,472+??90lfi: IN
PRTF
:Get task complete int,etc.
473+
ANI
TCIF
:Mask it
474+
JZ
113016
;Wttit for task to be complete
475
476 ;1f timeout
is to be checked, the above WAITT should
477 :be o:nitted & the appropriate code to look for Tel or
478 ;TOU'f3 inserted here.
479
489
MVI
A, AXRA
:Pattern to clear 91 E~D connitions
481
AUXMD
ou'r
482
MVI
A,TON
;This bit pattern alrett"'y in "A"
483
OUT
ADR.""ID
;Output TON
484
MVI
A,FNHSK }Finish handshake
485
OUT
AUXMO
486
CLRA
487+
XRA
A
;A XOR A :::9
488
AUXMD
ou'r
; Immed iate execute PON-Reset LON
489
MOV
A,B
;Get completion character
490 RECV6:
RET

3-136

231324-36

inter

AP-66

491
492 ;*.****.****** •••••• ****** •• *****************************.****
493
XFEH "OUnNE
494
495 ,
49~ ,INPu'rs:
HL lievice list pointer
497
B EOS character
498 ;ou'rpUTS:
None
499 ,CALLS:
None
590 ;OESTROYS:
A, HL, F
591 :RETURNS:
A=" normal, A ( > " bali talker
592

5~3

504 ,NOTE:
595
596
591
598
599
519 ,
511 XFER:

XFER will not work if the talker
uses FoOl to terminate ·the transfer ..

RANGE

51H

11311.
1138
1130
1149
1142
1145
1147

7E
FE40
FABB11
FE5F
F28Bll
0350
23

1148
11411.
114C
114F
1151

OB61
E602
C1I4B11
]E3F
0369

1153
1154
1156
1159
115B

7E
FE2S
FMC11
FE3F
F26C11

115E
1169
1162
1165
1166
1168
1169

0861
E692
CA5El1
7E
0360
23
C35311

116C
116E
1170
1173
1175
1177
1179

OB61
E602
CA6C11
3E87
0365
3EU
0364

117a
117C
117E
117F
1181
1183

AF
0365
78
D367
3EF6
D369

513+
514+
515+
516+
517+
51R+
519+
520+
521+
522
523
524
525+119017:
526+
527+
528
529
539 XFERl:
531+
532+
533+
534+
535+
536+
537+
538+
539+
540+
541
542+119018:
543+
544+
545
546
547
548
549 XFER2:
550+110019:
551+
552+
553
554
555

556
557
558+
559
560

,lower

(

(H) (L)

) <= upper.

;Get next byte ..
MOV
CPI

A,M
49H
XFER4
5P'H+l
XFER4
lJOUT

CPI
.TP
OUT
INX
"AI'rO
IN
ANI

BaM

110"'17

MVI
OUT
RANGE

A,UNL
OOUT

MOV
CPI
JH
CPI

A,II

IN'rl

; Send it to GPIB
:Iner pointer

;Get IntI status
;Cheek for byte out
:If not, try again
;Universal unl isten

2AH,3EH,XFER2
;Check for valid listener
;Checks for value in ranqe
;branches to label if not
;in range. Falls through if
,lower <= (

(H) (L)

) <=upoer.

;Oet next byte.

JP
WAITO
IN
ANI
JZ

MOV
ou'r
INX

JMP
WAITO
IN
ANI
JZ

MVI
OUT
"VI
ou'r
CLRA
XRA
OUT
~OV

551

QU'f

562

MVI
OUT

563

Intel will be making hardware
modifications to the 9291 that will
correct this problem. Until that time,
only EOS may be used without possible
loss of the last data byte transfared.
4AH,5EH,XFER4
;Check for valid talker
:Checks for value in ranqe
;branehes to label if not
;in range. Falls throuqh if

·29H
XFER2
3EH+l
XFER2
INTI
BOM
710Bl8
11.,1<
lJOUT

;Get IntI status
;Cheek for byte ·out
:If not, try again
;Get 1 istener

;Iner pointer
;Loop until non-valid listener

XFER1

;Get IntI status
;Check for byte out
;If not, try again
A, AXRA.+CAHCY+EDEOS
;Invisible handshake
AUX"'I.D
;Continuous A.H mode
A,LON
;Listen only

INTI
80M
11A919

ADR~D

AUXMD
A,B
EOSR
A,GTSB
CMD92

;/\ XOR A ... 0
;Immed. XEQ PON"
;Get EQS
;Output it to 91
;Go to standby

231324-37

3-137

AP-66

56~

1185 OB6F
1187 £692
1189 C28511
118C OB6F

565+??CHf2g:
556+
557+
558
569+1?0321 :

118£ £692

570+

1190
1193
1195
1197
119A
119C

571+
572 XFER3:
573
574
575
576
577
578+179022:
579+

CA8C11
OB61
£610
CA9311
38m
0359

119£ OB5F
11A0 E632
11A2 C29£11
11A5
11A7
11A9
11AC
11AB
11B0
11B2
11B4
11B6

PBH
£602
CAA511
3E80
0365
3E03
0355
3E80
0364

11B8 AF
11B9 0355
118B C9

11BC 3E3F
11BE 0360

11C9
11C1
11C3
11C6
11C8

7E
FE20
FA0911
FE3F
F20911

11ca
11CO
11CF
1102
1103
1105
1106

OB61
E6n
CACB11
7£
0360
23
C3C011

1109
110B
1100
11E0
11E2

OB61
E,02
CAP911
3E08
03"0

11E4 OB61
11£6 E6~2

580+

5B1
582+710023:
583+
. 584+
5~5

586
587
588
589
590
591
592+
593
594 XFfl4:
595 ,

WAITX
IN
ANI

JNZ
wAIT'r
IN
ANI

PRT~'

TCIF
??A829

,JZ

PRTF
TCIF
?10321
INT1
ENDMK
XFER3

MVI

A, TCSY

OU'f

C~092

JZ
IN
ANI

WA I'r X
IN
ANI

JNZ
WAITT
IN
ANI

JZ
"VI
OUT
MVI

ou'r
~VI

ou'r
CLRA
XRA
OUT
RET

;Wa it for TCS
;Get task complete int,etc.
;Mask it
;Wait for task to be complete
;Get END status hi t
;Mask it

;'rake control syncronously-

PRTF
TCIF
1?0322

;wait for TCI
PRTF
TCn'
??9923
A, AXRA
AUX"IO

;Get task complete int,etc.
:Mask it

;wait for task to be complete
;Not cont AH or END on EOS

A,FNHSK ;Finish handshake
AUX"IO
A.TON

;Talk only

ADRMD

;Normal return A=A
A

,A XOR A =3

AUX~O

;Immediate XEQ PON

.*.

596 ; ... ** *** ***** ... ** ***
** ** * * **** * ** .'* •• * * ** ** ** * *** * *
597
598
599
TRIGGER ROUTI~E
690
601
602 ;I~PUTS:
HL listener list pointer
693 ;OUTPU'fS:
None
504 ;eALLS:
None
605 ;DESTROYS:
A, HL,
606
607 ,
608 'rRIG:
MVI
A,UNL
;
699
OUT
DOUT
;Send universal unl isten
610 TRIG1:
RANGE
20H, 3EH, TRIG2
;Check for val id 1 i sten
,11+
:Checks for value in range
012+
i branches to label if not
613+
; in range. Falls through if
614+
;lower (= ( (H) eLl) (= upper.
615+
;Get next byte.
6H+
MOV
A,M
617+
CPI
29H
618+
J~
TRIG2
619+
CPI
3EH+1
620+
JP
TRIG2
621
WAITO
;Wait for U~L to finish
622+710024 :
I~
INn
;Get IntI status
623+
ANI
BOM
; Check for byte out
624+
JZ
??0324 ;If not, try aqain
625
~OV
A,M
iGet listener
626
OOUT
ou'r
; Send Li stener to GPI'S
627
INX
H
;Iner. pointer
628
TRIG}
JMP
;Loop until non-valid char
629 TRIG2: WAITO
;Wait for last listen to finish
630+170925:
IN
INn
;Get IntI 'st~tus
631+
ROM
ANI
;Check for byte out
632+
JZ
??fl025 iIf not, try again
,WI
633
A,GET
; Send q roup execute tr i!)ger
634
OUT
OOUT
ito all addresseti listeners
635
WAITO
636+?10026:
IN
INT1
;Ge~ IntI status
637+
ANI
,Check for byte out

3-138

231324-38

inter

AP-66

11E8 CAE411
11EB C9

638+
639
648 ,
641 J •••

~!;

644
645
646
647
648
649
659

11EC 3E3F
llEE D36B

llF9
11Fl
11F3
UF6
llF8

7E
FE28
FA8912
FE3F
F28912

11F8
UFO
UFF
12B2
1283
1285
12B6

0861
E682
C1IF811
7E
0368
23
C3F811

1289
1288
1280
1218
1212

0861
E682
CA8912
3E84
0368

1214
1216
1218
1218

0861
E6B2
CA1412
C9

~~~

; If not, try again

_**._. __ ........ _._- _._-***---------.. _.-

DEVICE CLEAR ROU'rINE

,
: INPUTS:
,OUTPUT:
,CALLS:
,DESTROYS:

HL 1 i stener pointer
None
None

bCLR:

A,UNL
DOUT
28H, 3EH, DCLR2

653
654 DCLRI.
655+
656+
657+
65B+
659+
668+
661+
662+
663+
664+
665
666+778827.
667+
668+
669
678
671

778126

RET

A, HL, F

MVI
OUT
RANGE

,Checks for value In range
;branches to label if not
; in range. Falls through if
,lower (= ( (HI (LI I ( s upper.
;Get next byte.
MOV
CPI

A,M
28H
DCLR2

CPI

JEH+l

DCLR2

WAITO
IN
ANI
JZ

MOV
OUr
INX
J'MP

673 DCLR2: WAITO
674+118828:
IN
675+
ANI
676+
JZ
677
MVI
678
OUT
679
WAITO
688+??B829:
IN
681+
ANI
682+
JZ
683
RET
684 ,
685 ; •• _____ e_

INTI
BOM
7?8827
A,M
DOUT

;Get IntI status
;Check for byte out
;If not, try again
;Send listener to GPIS

DeLRl
INTI
BOM
118828

iGet IntI status
;Check for byte out
iIf not, try aqaln

A., SOC

,Send device clear

DOUT

;To all addressed listeners

INTl
BOM
779029

;Get IntI status
;Check for byte out
; If not, try aga~n

"''''**''''''''' *** ** *** _____ .tI."' ________ ._. ____ •••

686
687

SERIAL POLL ROUTINE

~88

;
689 ,INPUTS:
69" ;
. fi91 ;OUTPUTS:

121C 3E3F
121E 0368
1228
1222
1224
1227
1229

DB61
E682
CA2812
3E21
0368

122B
1220
122F
1232
1234

DB61
£682
CA2B12
3El8
D3G8

1236 DB61

692 ,CALLS:
693 ,DESTROYS:
694 ,
695 SPOL:
MVI
696
OUT
697
WAITO
698+77B838:
IN
699+
AliI
788+
JZ
781
PlVI
782
OUT
783
WAITO
794+778831 :
IN
785+
ANI
786+
JZ
7B7
MVI
788
OUT
WAITO
719
718+778B32:
IN

HL talker list pointer

DE status 'buffer pointer
Fills buffer pointed to by DE
None
A, BC, DE, HL, F
A,U"L

;Universal unlisten

DOUT
INTI
80M
??BB30
A,MLA

,Get IntI status
; Check fo r byte out
;If not, try aqain
; My 11 sten add ress

DOUT
INTI
BOM
110831
A.SPE
DOUT

;Get IntI status
,Check for byte out
;If not, try again

INTI

,Get Intl status

,Serlol poll enable

;To be formal

~bout

231324-39

3-139

AP-66

1238 £1)"2
123A C1I3~12

n1+
712+
713 SPOL1,
714+
715+
716+

ANI

BOIloll
??AIH2

RANGE

4~:i,Sp.H,SpaL2

;Checks for value in ranqe
;hranches to laryel if not
; in ranqe. Falls through if
; lower <= ( IH) (L) ) <= upper.
;Get next hyte.

717+

1230
123E
1240
1243
1245
1248
1249
1249
124C
124E

7E
FE40
FA9412
FE5F
F29412
7£
0360
23
3£40
D364

1250 0961
1252 E502
1254 CA5012
1257
1258
125A
125C

IIF
0365
3EF6
0369

125E OB6F
1250 E502
1252 C25E12
1265 086F
1267 £602
1269 CM512
126C
126E
126F
1271
1274
1276

OB61
47
E6~1

CA6C12
3EFO
03S9

1278 096F
127A E602
127C C27812
127F
1281
1283
1286
1288
1289
128A
128c

096F
E692
CA7F12
0960
12
13
3E80
03'4

128E AF
128F 0365
1291 C33012
1294 3E19
1296 0360
1298 0961
129A E602
129C CA9812
129F AF
12A0 0365
12A2 C9

71B+
719+
720+
721+
722+
723+
724
725
726
727
728
729
730+710033,
731+
732+
733
734+
735
736
737
738
739+??0234,
74a+
741+
742
743+??~035,

744+
745+
746
747+110036,
748+
749+
759+
751
752
753
754+719037,
755+
756+
757
758+110338,
759+
769+
761
762
763
764
765
766
767+
768
769
770
771 ,
772 SPOL2,
773
774
775+710939:
776+
777+
778
779+
780
781
782 I
783 I

784

;Check for byte out

:If not, try aqain
;Check for valid talker

MOV
CPI

A,M

ou'r

40H
SPOL2
5EH+!
SPOL2
A,M
oou'r

INX

MVI
ou'r
WAITO

ADRMO

CPI
JP
,~OV

IN
A~I

A,LO~

INn
80~

110033

CLRA

XRA

Ou'r

AUXMD

MVI
ou'r
WAITX
IN
ANI

A,GTSB

PRTF
TCIF
?1B934

WAITT
IN
ANI

PRTF
TCIF

WIlITI
IN
MOV
ANI

JZ
MVI
ou'r
WAITX
IN
A~I

JNZ
WAIT'r
IN
ANI

JZ
IN
STAX
INX
MVI
OUT
CLRA
XRA
ou'r

;Wait for talk a~dress to complete
;Get IntI status
;Check for byte out
;If not, try again
;Pattern for immediate XEQ PON
:A XOR A ."
;Goto standby

CM092

JNZ

;Get talker
; Seno to GPIB
;Incr talker list pointer
:Listen only

110~35

IN'r!
B,A
BIM
n3036
A,TCSY
CMD92

;Wait for Tel false

:Wait for TCI
:Get task complete int,etc.
:Mask it
;Wait for task to he complete
:Wait for status byte input
;Get INTI status
:Save- status in B
;Check for byte in
;It not, just try again
:Take contra"! sync
;Wait for Tel false

PRTF
TCIF
??""37
PRTF
TCIF
1?o"38
DIN

o
o
A,TON

;Wait for Tel
;Get task c-omplete int,etc.
:Mask it
:Wait for task to be complete
:Get ser ial PDII status byte
;Store it in buffer
: Incr pointer
:Talk only for controller

AORMO

II
AUXMD

JMP

:A XOR A =A
j Immed i ta te XI::Q PON
;CLR LA

SPOLl

,Go on to next device on list

MVI
OUT
'j/AI'rO
IN
ANI

""SPO
OOUT

;Serial poll disable
;we know BO was set (WAITO above)

INTl

118039

;Get IntI status
JCheck for byte out
;1.£ not, try a'1ain

CLRA
XRA

;A XOR A =R

OUT

AUXMO

;Immediate XEQ PON to clear LA

RET

80M

**** •• *********.*****.************* **.************ •••
231324-40

3-140

inter

Ap·66

7ft5

Pl'.RALLEL POLL ENA8LE ROUTINE

78~

121'.3 3E3F
121'.5 0350

7ft7 INPUTS:
HL listener list pointer
788
DE confiquration byte pointer
789 OUTPu'rs:
None
790 CALLS:
None
791 DESTROYS:
A, DE, HL, F
792
793
794 PEN:
MVI
A,UNL
;Universal un! isten
795
OUT
oou'r
795 PPEN1:
RANGE
2AH,3EH,PPEN2
,Check for valid listener
797+
;Checks for value in range
798+
; branches to label if not
799+
,in rant'Je. Falls throut'Jh if
800+
; lower
(H) (Ll ) <= upper.
891+
;Get next byte.
802+
MOV
A,M
883+
CPI
20H
804+
J~
PPEN2
805+
CPI
3EH+l
806+
JP
PPEN2
8B7
WAITO
;Valid wait 91 data out req
808+770049:
IN
INT1
fGet IntI status
809+
ANI
BOM
;Check for byte out
810+
JZ
??B'UA ilf not, tryaqain
811
MOV
1'.,01
;Get 1 istener
812
OUT
OOUT
813
',AlTO
814+170041:
IN
INn
;Get IntI status
815+
MI
80M
;Check for byte out
816+
JZ
710041
ilf not, try again
817
MVI
A.,PPC
;Parallel poll confiqure
818
ou'r
DOUT
819
WAITO
820+110942 :
IN
INTl
;Get IntI status
,821+
A~I
80M
;Check for byte out
822+
JZ
77A042 ;If not, try again
823
LDAX
o
;Get matchin., confiquration byte
824
ORI
PPE
;Merge with parallel poll enable
825
OUT
DOUT
826
INX
K
;Iner pointers
827
INX
o
828
JMP
PPEN1
;Loop until invalid listener char
829 PPEN2: l'iAITO
830+770043:
IN
INT1
;Get IntI status
831+
ANI
80'1
;Check for byte out
832+
JZ
??BBH ;If not, try again
833
RET
834 ,
835 ,PARALLEL POLL OISA8LE ROU'fINE
836 ;
837 ,INPUTS:
ttL listener list pointer
838 ,OUTPUTS.
~one
839 ,Cl'.LLS:
None
840 ,DESTROYS.
A, HL, F
841 ,
842 PPOS:
A,UNL
/'IVI
,Universal unl isten
843
ou'r
OOUT
844 PPOS1:
RANGE
23H, 3£H, PPDS2
;Check for val id Ii stener
845+
;Checks for value in ranqe
846+
;branches to label if not
847+
;in ran'1e. Falls'throuqh if
848+
flower <= ( eft) eLl) <"" upper ..
849+
;Get next h.yte.
85A+
MOV
A,M
851+
CPI
28H
852+
J'I
PPOS2
853+
CPI
3EH+l
854+
3P
PPOS2
855
WAITO
856+??0844 :
IN
nIT 1
;Get IntI status
857+
A~I
BOM
:Check for byte out
858+
710044 ; If not, try again
JZ'

<= (

121'.7
121'.8
121'.1'.
121'.0
12AF

7E
FE20
FA0812
FE3F
F20812

12B2
12B4
12B6
12B9
12BA

OB61
E602
CAB212
7E
0350

12BC
12BE
12Ca
12C3
12C5

0861
E602
CABC12
lE05
"H0

12C7 OB61
12C9 E~n
12C~ CAC712
12CE 11'.
12CF F660
1201 0360
1203 23
1204 13
1205 C3A712
1208
1201'.
12DC
12DF

OB61
E602
CA0812
C9

12E0 3£3F
12E2 0350

12E4
12E5
12E7
12EA
12EC

7E
FE20
FAF012
FE3F
F2F012

12EF OB61
12F1 E602
12F3 CAEF12

231324-41

3-141

intJ
12F~ 7E
12F7 03~9
12F9 23
12FA C3E412

12FO 0861
12[o"'F £'592

1391 CAF012
1304 3 E95
139~ 0359
1398
139A
13AC
139F
1311

OB61
E692
CA9813
3E70
OHA

1313
1315
1317
131A

0861
E602
CA1313
C9

AP-66

859
815A
861
862
863 PPOS2:
81i4+??Ba45:
865+
SSt;+
8<;7
868
859

~OV
OUT

A,M
DOUT

INX

;Get 1 istener

; Incr pointer
lnval id listener

J~P

PPDS1

;Loop UF'ltil

WAlTa
IN
ANI

IN'rl
80~

;Get IntI status
;Check for hyte out
,If not, try aqain
;Parallel poll confiqure

,JZ

"VI
ou'r
WAITO
IN
870+??B341'i :
ANI
8U+

?10A45
A,PPC
OOUT

I"'rl
B01"

;Get IntI status
;Check for byte out

??094fi

873

MVI

874
875

A,PPD
DOUT

,If not. try aqain
;Parallel poll disable

OUT

872+

R7fl+??A047 :

877+
878+
879
880
881

WAITO
IN
·ANI

INT1
80"1
??~H147

;Get IntI status
;Check for byte out
,If not, try aga in

RET
PARA~~EL PO~L

UNCONFIGURE ALL ROUTINE

882

131B 3E15
1310 0363
131F
1321
1323
1326

0861
E692
CAIF13
C9

883 ;
884 ; INPUTS:
885 ,OUTPUTS:
886 ;CALLS:
887 ,DESTROYS:
888 ,
889 PPUN:
.~VI
890
ou'r
891
WAlTa
IN
892+??""4 8:
893+
ANI
894+
JZ
895
RET

None
None
None
A, F

A,PPU

;Parallel poll unconfiqure

DOu'r
INTI
BaM
179948

:Get Intl status
;Check for byte out
;If not, try 81ain

~~j : ................................................. .
898 ,
899 ,CONDUCT A PARA~~E~ PO~~
900
901
992 ; INPU'rS:
None
903 ,OUTPUTS:
None
904 ;CALLS:
None
905 ; DESTRO¥S:
A, B, fo'
906 ;RETURNS:
A= parallel poll status byte
907
908 PPO~:
~VI
A,LON
;Listen only
909
ou'r
AOR"ID
910
CLRA
; Immed iate XEO PON
911+
XRA
A
;A XOR A =9
912
OUT
AUXMO
;Reset TO'"
913
'IVI
A, EXPP
1Execute parallel poll
914
OUT
CM092
915
WAITI
;Wait for completion= RI on 91
916+?19049: IN
INT1
;Get INTI status
917+
MOV
B,A
;Save status in B
918+
ANI
RIM
;Check for byte in
919+
JZ
??0049
;If not, just try aqain
920
MVI
A, TO,",
;Talk only
921
OUT
ADRMD
922
CLRA
;Immediate XEQ PON
923+
XRA
A
;A XOR A =0
924
ou'r
AUX'IO
;Reset LO~
925
IN
DIN
;Get PP byte
925
RET
927
928 **********************************************
929 PASS CONTRO~ ROU'tINE
930
931 INPU'rS:
HL pointer to tAlker
932 Ou'rpuTS:
None

1327 3E49
1329 0364
1328
132C
132£
1339

AF
0365
3EF5
0369

1332
1334
1335
1337
133A
133C

0861
47
E691
CA3213
3E8A
0354

133E
133F
1341
1343

AF
0365
0869
C9

3-142

231324-42

inter

1344
1345
1347
134A
134C
134F
1351
1354

7E
FE4e
FA8A13
FE SF
F28A13
FE41
CA8A13
0360

1356
1358
135A
1350
135F

OB61
EGe 2
CA5513
3E09
DHO

1361
1363
1365
1368
136A

DB61
E602
CA6113
3EU
0364

13~C

1360
135F
1371
1373
1375

0365
3E81
0366
3EA1
0365

1377 3EF1
1379 0369
137B DB5F
1370 E602
137F C27813
1382
1384
13B5
1389
138A

D86F
E602
CA8213
23
C9

Ap·66

. None
933 ,CALLS:
934 ,DES'rRO~S:
1\, HL, F
935 PCTL:
RANGE
40H,SEH,PCTLl
;Is it a valid talker
936+
;Checks for value in rantte
937+
;brenches to la~el if not
938+
;in ranqe. Falls through if
939+
,lower (= ( (Hl (Ll 1 (= upper.
940+
;Get next byte.
941+
MOV
A,M
942+'
CPI
4AH
J,~
943+
PCTL1
944+
CPI
5EH+l
945+
.JP
PCTL1
946
CPI
MTA
,Is it my talker address
947
JZ
PCTL1
;Yes, just return
948
OUT
OOU1'
; Senrt on CPI B
949
WAITO
950+710~59:
IN
INT1
;Get IntI status
951+
A~I
80M
;Check for byte out
952+
JZ
??AA59 ;If not, try again
953
A,TCT
;Take control messaqe
"VI
954
ou'r
OOUT
955
WAITO
956+710851:
IN
IN"rl
;Get IntI status
ANI
957+
BOM
;Check for hyte out
958+
JZ
110351 IIf not, try aqain
A,MODE1 ;Not talk only or listen only
959
MVI
960
OUT
ADRMD
;Enable 91 arlnress mone 1
951
CLRA
952+
XRA
A.
JA XOR A =0
963
OUT
A.UXMD
;Immediate XEQ paN
904
~VI
A.,MDA
;My device address
965
OUT
ADR"1
':enabled to talk and listen
965
MVI.
A,AXR8+CPTE'4
:Command pass thru enable
967
OUT
AUXMD
968 ;*******optional PP configuration goes here*****.**
959
MVt
A,GtDL ;92 go idle command
970
OUT
Cf'lD92
971
WAITX
972+??f;H~52: IN
PRTF
973+
TCIF
ANI
974+
119B52
JNZ
975
WAITT
;Wait for Tel
976+710053: IN
PRTF
;Get task cl)mplete Int,etc.
977+
ANI
;Mask It
TCIF
978+
JZ
179953 ;Wait for task· to be complete
979
INX
H
990 PCTL1:
RET
9B1
~2

138B
1380
138F
1392
1394

DB51
E680
CACF13
OB65
FE09

983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
lIn"
18B!
1082
1003
1004
1005

; ***.*****.*******************************
,
,RECEIVE CONTROL ROUTINE
,
,INPUTS:
None
,OU'rpUTS:
None
,CALLS:
None
,DESTROYS:
A, F
B= invalid (not take control to us or cpr bi t .not on)
,RETURNS:
,
< > B = valid take control-- 92 will now be in control
THIS CODE MUST BE TIG~TLY INTEGRATED I~TO AN~ USEQ
,NOTE:
SOFTWARE THA'r FUNCTIONS WITH 'rHE ~291 A~ A DEVICE.
NOR"'ALL~ SOO'lE ADVA'ICE WARNING OF IMPENDl'1G PASS
CONTROL SHOULD BE GIVE" TO US BY "rHE CONTROLLER
WITH OTHER USEFUL INFO. THIS PROTOCOL IS SITUATION
SPECIFIC AND WILL NOT BE COVERED HERE.
;
RCTL:

IN
ANI

JZ
IN
CPI

INT1

CPT

RC'rL2
CPTRG
TCT

Get INTI req (i.e. CPT etc.)
Is command pass thru on ?
No, invalid-- go return
Get command
Is it take control?

231324-43

3-143

intJ
1396
1399
1396
139D

C2CA13
D664
E6g2
CACA13
13A~ 3£60
13A? OH6

13A4 3E8"

13M 0364
13M
13.0.9
13A6
13AO
13AF
1361
1363
1365

M'
D361
0362
0365
3EFA
0369
3E9,'
0365

13B7 066F
13B9 E6g2
138B C2B713
13dE
13CftJ
13C2
13C5
13C7
13CA
13CC

OB6F
Ef}"2
CASE13
3E~9

C3CF13
3EAF
D365

13CE AF
13CF C9

AP-66

JNZ

10A6
1007
1908
1009
lAlA

IN
ANI
,1Z
MVI

RCTL1
ADRC;T
'rA
RCTr.1

iNo,

qo return invalid

:Get

ad~ress

status

:Is TA on' ?

;No -- go return invalin
A,DTDLI ;Di!:;;aole talker listener

lAll
ou'r
AORAI
MVI
lA12
;Talk only
A,TON
ADRk1J)
lA13
ou'r
1914
CLRA
1915+
XRA
A
;A XOR A =0
1 A16
OUT
INn
,Mask off I~T hits
1917
oU'r
INT?
lA18
ou'r
AUXMD
1919
MVI
h,TCN'rA. ;Take (receive). control 92 command
192A
ou'r
CMD92
1021
MVI
A, VSC;t1.0 ;valio corn.manri pl'Ittern for 91
1022
OUT
AUXMD
1923 : ******** optional TOUT} check could be put here ********
lH24
'N'AITX
UJ25+??AA54 : IN
PRTF
ANI
1926+
TCIF
1927+
JNZ
??~e54
lA28
WAITT
;Wait for Tcr
1029+110355: IN
PRTF
,;Get task complete int,etc.
193A+
ANI
TCIF
;Mask it
IIBl+
??~;:'5Cj
JZ
;wait for task to be complete
1932
MVI
A,TCT
;Valid return pattern
1033
J'IP
RCTL2
;Only one return per routine
1934 RCTL1:
MVI
A,VSCMD ;Acknowledqe cP'r
1935
OUT
AUX,"'O
1~36
CLRA
;Error return pattern
1A37+
XR!\
;A XOR A =3
1938 RCTL2:
RET
1039
1"'4 ~ J
*.*.********************.****.***
1041
1042
SRO ROUTI~E

_._-*- -_._-_ .. _.

1~43

1300
1302
1304
1307
13D9
130B
130D
13DF
13E2

0869
E629
CAE213
F638
D369
0669
'E692
CAOB13
C9

1944 ; INPUTS:
None
1945 :ou'rpUTS:
None
1046 ;CALLS:
None
1047 ;RETURNS:
A= " no SilO
1948
SRQ occuren
A < >
1049
1"59 ,
1051 SRQD:
·IN
INTST
;Get 92 '5 IIIJTRQ stAtus
1052
ANI
SRQ~T
1~ask off SRQ
,JZ
lA53
;Not set--- go return
SH002
1954
ORI
lACK
;Set--- must clear it with lACK
1955
ou'r
CMD92
1A56 'SRQ01:
IN
INTST
;Get IBF
1057
ANI
IRFRT
;Mask it
1058
JZ
SRQ01
:Wait if not set
1A59 SRQD2:
RET
IrHi3 ;
le6} ;************************************ •• ******
1062 ,
1A63 ,REMOTE ENABLE ROUTINE
1964
lAGS; INPUTS:

1A56

,ou'rpu'rs:

11'f67 ;CALLS:
leGS ;DESTROYS:

13E3 3EF8
13E5 0359
13E7 OB6F
13E9 E6A2
13EB C2E713
13EE OB6F
13FA £6A2
13F2 CAEE13

1059 ,
1070 REME:
1071
1072

MVI
OUT
W'AI'rx
1073+??ftJASIl: IN
ANI
1074+
JNZ
IB75+
WAIT'r
lH76
1977+710057: IN
ANI
1078+
1979+
JZ

None
None
NO~E

A. F
A,SRENI

CM092

;92 asserts remote enable
;Wait for TCI = 0

PRTF
TCIF
??"~5t;

PRTF
TCIF
??~!oJ57

,Wo!'Iit for TCI
:Get task complete int,ete.
;Mask it
;Wait for task to be complete

3-144

231324-44

infef
13"5 C9

AP-66

IB8~

Rf-T

1"81
1082 ; * * * ...... *".111 * ........ 111111 •• """ •• * .... " * .... * .. * * •• III_ *
In83
U84 : LOCAL ROU'fIN E:
1885
1886
1887 ;INPU'l'S:
None
None
1888 ;OUTPUTS:
None
1889 ,CALLS:
1098 ;DESTROYS:
A. F
1891
MVI
lA92 LOCL:
OUT
;92 stops asserting remote enable
1893
o'IAITX
1894
;Wait for Tel =="
lA95+??01)58: IN
PH'l'F
1096+
ANI
TCIF
1897+
JNZ
??005A
;Wa i t for Tel
1098
'''AIT'r
:Get task complete int ,etc.
1099+??(H159: IN
PRTF
;Mask it
1100+
ANI
TCIF
1101+
??9959
:Wait for task to be complete
JZ
1102
RET

13F6 3£F7
13F8 0359
13,'A DB6F
13FC £632
13FE C2FA13
1401
1403
1485
1488

OBGF
£682
CA8114
C9

ii:~

;...............................................

1105
1196 ;

1489 3£F9
0359

148~

1480 ORnF
148F £582
1411 C2B014
1414 OBnF
1416 En82
1418 CA1414

141B C9

I~TEHFAC£

CLEAR /

AROnT ROU'fINE

1187
llOB
None
1109 ; INPu'rs:
None
l11A ;ou'rpUTS:
None
1111 ;CALLS:
1112 ; OEST~OYS:
A. F
1113
1114
1115 IFeL:
MVI
A,ABORT
1116
OUT
CMD92
;Send IFC
1117
'NAITX
;Wait for Tel =t1
1118+??0:;)60: IN
PRTF
1119+
ANI
TcrF
1120+
JNZ
??"I1Fi'3
1121
WAITT
;1'lait for TCI
1122+??a0f11: IN
PRTF
;Get task complete int,etc~
1123+
ANI
TCIF
;Mask it
1124+
JZ
770-;:' j::jl
iWa it fo r ta sk to be complete
1125 ;Delete both '~AITX " WAITT if this routine
1125 lis to be called while the 9292 is
1127 ;Controller-in-Charqe~ If not C.I.C. then
1128 :TCI is set, else nothing is set (IFC is sent)
1129 land the WAIT1S will hang forever
113a
RET
'
1132

3-145

231324-45

inter

AP-66

1133 ,APPLICATION
1134
BB32
1ia31
BB51
OBBD
9BBA

1135
1136
1137
1138
1139
1149

DB~'F

OB49
141C
1429
1424
1428
142/1
BOOF1428
142F
90B6
1431
1432
1433
1434
1435
143~

46553146
5233374B
48414032
564F
DO
58463447
3754
31
FF
32
FF
51
FF

FGDNL
FCDNL
FCDNT
CR
LF
LEND
1141 SROM
1142
1143 FGOA1'A:

~DH

;Freq etr talk address
;ASCII carriaqe return

BAH
OFFH
40H

:List end for Talk/Listen lists
;Bit indicatinq device sent SRO

·FUIFR37KHA~2VO·

1148 LL2:

FODNL, LEND

;Listen list for func. gen

1149 TLl:

FCDNT,LEfIIo

;'ralk list for freq etr

1151 ,SETUP FUNCTION GENERATOR

8E06

1161
1162
1163
1164

MVI
MVI
LXI
LXI
CALL

1159

11~5

3CBB
JeBB
BU1

;E05

;Count

D,FGDATA
;Data pointer
H;LL2
;Listen nst pointer
SEND

COU~TER

,..VI
MVI

B,eR

C, LIMl

LXI
LXI
CALL

B,'T'
;EOS
C,Llflf2 ;Count
0, FCDATA .
H,LLl
SEND

,Data pointer
;Listen list pointer

1166 I WAIT FOR S~O FROM FREO cm
1167
1168
CALL
SROD
,Has SRQ occurred
.JZ
1169
LOOP
;No, wait for it
1178
1171 ;SERI/IL POLL TO CLEAR SRO
1172
1173
LXI
D,SPBYTE
,suffer pointer
1174
LXI
H,TLI
;Talk list pointer
1175
CALL
SPOL
1176
DCX
D
;Backup buffer pointer to otr byte
1177
LDAX
D
;Get status byte
1178
ANI
SROM
;Did ctr assert SRQ ?
1179
.JZ
ERROR
;etr shoulti have said yes
1180 I
1181 ,RECEIVE READING FROM COUNTER
1182
1183
MVI
B,LF
;EOS
1184
""VI
C,LINl3 ;Count
1185
LXI
H,TL1
,Talk list pointer
1186
LXI
0, FCDATI
;Data In huffer pointer
1187
CALL
RECV
1188
JNZ
ERROR
1189
119B ; ***.* ••• rest of user processinq qoes here *****
1191

,
,

1192
1477 B8

;Data to set up func. qen

;Buffer lenqth
;Listen list for freq etr

1158 ;SETUP FREQ

B68A
8E11
213514
11913C
CD9F1B
C27714

,eR

6
FCDNL, LEND

1168

1467
1469
1468
146£
1471
1474

,ASCII line feed

EQU
DB

8~54

llBB3C
213514
CD1C12
1B
1A
E648
CA7714

A~CII,lstn

1146 LIM2
1147 LL1:

1444

1457
145A
1450
1468
1461
1462·
1464

;Freq etr device num *1*

;Buffer lenqth
;. Data to set up {req etr

1152
1153
1154
1155
1156
1157

1451 CDDBl3
1454 CA5114

'I'
'Q'

'PF4G7T '

e60D
8E9F
111C14
213314
CD1C10

213114
CD1C18

8~a5'

,Fune qen device num *2* ASCII,lst"

1437
1439
143B
143E
1441

112a14

CODE FOR

'2'

'1144 LIM1
EQU
1145 FCDATA: DB

115B

1446
1448
144B
144E

EXA~PLP.

EOU
EQU
P.OU
EQU
EQU
EOU
EQU

1193 ERROR:
1194 I
1195 ORG
1195 SpaYTE:
1197 LIOIl

NOP
. ETC.
3CnOA
OS
EOU

;User dependant error handling
1
17

; Location for ser ial poll byte
;Max freq counter input

231324-46

3-146

inter

AP-66

1198 FCOA'j'I: OS
E>lD
1199

3C01

;Freq ctr input buffer

LIM3

PUBLIC SYMIIOLS

EXTEROI/AL SYMBOLS

us EH SY .... HOLS
ABORT
A AAF9
SI"
CLHs'r
DCLR
I:: DE 05
EilROR
}o'CDNL
Gst:c

IFCL
IN'fs'r
LL1
JIIIODEI
PPD
PP~N2

A Aon1
A IHI"!'
A ilEe
A 8BA4

A 1477
• 0031
A (JIlF4

A
A
A
A
A
A

1499
!"'''9
1431
IHHn
007~

12D8

HANG&

+ enes

RECVl
Ht:H.F
SOBOl
5['0106
SPIF
500"1
feN'fH.
TaST

A
A
A
A
A
A
A
A

U~L

\'iou'r

lOBA
A0&4
ifO""

1985
"""4
1308
"'''FA

ADIHH
HOF
C"ID92
DCLRI
END"1K

EVdIT
FCOf:::>

N';

"''''
Vl...J

0
N

> > u x

...J

~ >III

III

:::>

'"
,; :;i

liil

ADO
ADI

AGND

AD2

VREF

AD3

vpD

AD4

sic

AD5

RST

AD6

SDATA

AD7

SClK

AD8

TClO

AD9

TCll

AD10

s/i.

ADll

RTS

AD12

CTS

AD13

STR

AD14

DTR

AD15
SH

XTClK

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

270242-5

68 Pin PLCC
Figure 2. Device Packages

4-3

89024

when received carrier is dropped. The modem chipset can also be configured to transmit 'long-space'
just before disconnection, in each of the aforementioned cases.
.

CALL ESTABLISHMENT,
TERMINATION AND RETRAIN
The 89024 modem system incorporates all protocols and functions required for automatic or manual
call establishment. The modem system also incorporates all protocols and functions required for progress and termination of a data call.

Because the CCITT and Bell modem connection
protocols do not provide recognition of remote modem type (Le. V.22 bis to 212A), the Intel chip-set
provides the additional capability of identifying the
remote modem type. This feature is beneficial during
the migration phase of the technology from the
1200 bps to 2400 bps. In North America, where the
installed base of 1200 bps modems is mostly madeup of 212A type, this feature allows a "Data Base
Service Provider" to easily upgrade the existing
212A modems to 2400 bps V.22 bis standard, transparently, to 212A users. Similarly, a user with a
89024 based modem system can automatically call
data bases with either 212A or V.22 bis modems,
without concern over the difference. This feature's
benefits are realized in smooth upgrading of data
links, with minimum cost and reduced disruption in
services. Refer to Table 1 for a detailed description
of remote modem compatibility.

The modem chip-set has a built-in auto-dialer, both
DTMF and Pulse type. The modem can detect the
dial, busy, and ringback signals at remote end, and
will provide call progress messages to the user. The
modem is capable of re-dialing the last number di-'
aled, by one command.
The mO,dem when configured for auto-answer, will
answer an incoming call, remain silent for the two
second billing delay interval, before transmitting the
answer tones. Afterwards modem to modem identification and handshaking will proceed at a speed and
operating mode acceptable to both ends of the link.
The data call can also be setup by manual dialing
with the modems set to data mode, or by voice to
data transfer by means of mechanical switch (exclusion key), using the SH pin. Once set to data mode,
the modem handshaking will proceed before the
modems will be ready to accept and exchange data.

SOFTWARE CONFIGURATION
COMMANDS
This section lists the 89024 commands and registers
that may be used while configuring the modem.
Commands instruct the modem to perform an ac. tion, the value in the associated registers determine
how the commands are performed, and the result
codes returned by the modem tell the user about the
execution of the commands.

During data transmission, if one of the modems finds
that the received data is likely to have a high bit error
rate (indicated by a large mean square error in the
adaptive equalizer), it initiates a retrain sequence.
This automatic retrain feature is only available at
2400 bps, and is compatible with CCITT V.22 bis
recommendations.
Disconnection of the data call can be initiated by the
DTE at the local end or by the remote DTE, (if the
modem is configured to accept it). Whether DTR will
initiate a disconnect, depends on the last &D com- .
mand. Receiving a long space from a remote modem will initiate a disconnect only after a Y1 command. The optional disconnect requests originated
by the remote modem, are of two types, (1) disconnect when receiving long-space, and (2) disconnect

4-4

The commands may be entered in a string: with or
without spaces in between. Any spaces within or between commands will be ignored by the modem.
During the entry of any command, the 'backspace'
key (CNTRl H) can be used to correct any error.
Upper case or lower case characters can be used in
the commands. Commands described in the following paragraphs refer to asynchronous terminals using ASCII codes.

89024

Table 1. Remote Modem Compatibility
Originating
89024
Modem
Bell
CCITT

300
1200
300
1200
2400

Answering
89024
Modem
Bell
CCITT

300
1200
300
1200
2400

Bell
300

Bell
1200

300
1200'

300
1200

1200'
1200'

1200
1200

Answering Modem
CCITT
CCITT
300
1200

300

Bell
300

Bell
1200

300
300

1200
1200

300'
300'

1200
1200

300'
1200

300'
1200·

1200
1200

1200
2400

Originating Modem
CCITT
CCITT
300
1200

300
-

CCITT
2400

1200
1200

CCITT
2400
1200
1200

1200
2400

• These connection data rates are obtained when connecting 89024 based modems end to end. The same results may not
be obtained when a 89024 based modem is connected to other modems.

& Command Set

Command Set
AT

A
AI
Bn(1)
Os
En
Hn

In
Ln
Mn

o
Qn
Sn = x
Sn?
Vn
Xn
Yn
Z

+++

Attention code.
Go off-hook in answer mode
Repeat previous command string
BELLICCITT Protocol Compatibility at
1200 bps
The dialing commands
(O-g ABC 0 • # P R T S W ,; @)
Echo command (En)
Switch-Hook Control
If &J1 option is selected, H1 will also
switch the auxiliary relay
.Request Product Code and Checksum
Speaker Volume
Monitor On/Off
On-Line
Result Codes
Write S Register
Read S Register
Enable Short-Form Result Codes
Enable Extended Result Code
Enable Long Space Disconnect
Fetch Configuration Profile
The Default Escape Code

DCDOptions
DTROptions
Fetch Factory Configuration Profile
Guard Tone
Telephone Jack Selection
Leased/Dial-up Line Selection
Async/Sync Mode Selection
Make/Break Pulse Ratio
RTS/CTS Options
DSROptions
Test Commands
Write Configuration to Non Volatile Memory
&x(1) Sync Clock Source
&Z
Stofe Telephone Number

&0
&F
&G
&J
&L
&M(1)
&P
&R
&S
&T
&W

NOTE:
1. Available in external code only.

4-5

inter

89024

Dial Modifiers

CONFIGURATION REGISTERS
P
R
T
5
W

The modem stores all the configuration information
in a set of registers. 50me registers are dedicated to
special command and function, and others are bitmapped, with different commands sharing the register space to store the command status.
50'
51
52
53
54
55
56
57
58
59
510
511"
512
513
514 •
515
516
517
518 •
519
520
521 •
522 •
523 •
524
525 •
526 •
527 •

Ring to Answer
Ring Count. (Read Only)
Escape Code Character
Carriage Return Character
Line Feed Character
Back 5pace Character
Wait for Dial Tone
Wait for Data Carrier
Pause Time for the Comma Dial Modifier
Carrier Detect Response Time
Lost Carrier to Hang Up Delay
DTMF Tone Duration
Escape Code Guard Time
Not Used
Bit Mapped Option Register
Not Used
Modem Test Options
Not Used
Test Timer
Not Used
Not Used
Bit Mapped ,Options Register
Bit Mapped Options Register
Bit Mapped Options Register
Not Used
Delay to DTR (5ync Only)
RT5 to CT5 Delay (Half Dup.)
Bit Mapped Options Register

Pulse Dial
Originate call in Answer Mode
Tone.Dial
Dial a stored number.
Wait for dial tone
Delay a dial sequence
Return to command state
Initiate a flash
Wait for quiet

Example:
Terminal: AT &Z T 1 (602) 555-1212
Modem: OK
Result:

Modem stores T16025551212 in the external NVRAM.

The number can be dialed from asynchronous mode
by issuing the following command:
Terminal: AT D5
Modem: T16025551212
or by turning on DTR when in 5ynchronous Mode 2.
Up to 33 symbols (dial digits and dial modifiers) may
be stored. 5paces and other delimiters are ignored
and do not need to be included in the count. If more
than 33 symbols are supplied, the dial string will be
truncated to 33.

APPLICATIONS OVERVIEW
The block diagram of a stand-alone 300 to 2400 bps
Hayes compatible modem is depicted in Figure 3.
The DAA section shown in this diagram may be obtained with FCC. registration, or implemented using
the suggested diagram in Figure 4.

NOTE:
• These S registers can be stored in the NVRAM .
•• Available in internal code only.

4-6

inter

89024

POWER SUPPLY
DGND

RST

VOLTS

AGND

AUDIO

-S VOLTS

~ONITOR

TELEPHONE LINE
INTERFACE

II-'" >'" ":z:
V>

u
u

m
m

> >

""" ""

DAA
AND
4W/2W

Vee
HY"

X2
V REF

89026

ClKIN
ED
STR

89027

CLKOUT

SERIAL

DIGITAL

TSYNC

INTERFACE

TSYNC

V.24/

SDATA

RS232C

SClK

1E
TIP

AZI

ED
STR

:z:
V>
V>

:z:
in

RING

.OIS",F
AOI

TRXCAR

A02
TXO

RCVCAR

TXl
TX2

:::>

A~P

J~""
LEVEL
SELECT

":z:""
~
w

:z:
:J

TIP

:z:
RING ~

Ail

~IC

TX3

DTE

SH
iii

270242-6
'Internal code supports 9346
External code supports X2444

Figure 3. Typical Modem Configuration with External Hybrid

..------f--.TIP

AR~----------------------------------~~~
6H~----------------------------~

.--+--------+-_+ RING

AUXILIARY
BUSINESS
PHONE

~IC

10K
+SV

toN

~
'"
g

0-....---1---+-+ RING

A02~_t------._--~

TELEPHONE
LINE OR
DATA PHONE

must be connected to Vee.
4. SS pin reserved for future use.
5. With internal ROM enabled, ADO-AD1 are used as AA and JS.
6. Pins with direction "In" must not be left floating.

89026 PIN DESCRIPTION

XTCLK*

A Low indicates maintenance condition in the modem.

Transmitter timing from OTE, when external clock
option is selected.

The serial data from OTE to be transmitted on the
line. A logic 'high' is mark. In synchronous mode,
89026 samples this data on the rising edges of
TCLK.

DCD
In async operation, OeD remains Low regardless of
data carrier (default), or it can be programmed to
indicate received carrier signal is within the required
timing and amplitude limits. In sync operation Low
indicates the received carrier signal is within the required timing and amplitude limits.

TXD

TCLK*

DSR

Clock output from 89026 as timing source for data
exchange from OTE to modem. Serial data is read
on the rising edges of the TCLK. This output is High
in asynchronous mode.

Low indicates modem is off-hook, and it is in data
transmission mode, and the answer tone is being
exchanged, CTS Low indicates modem is prepared
to accept data.

RXD

RTS

The serial data to OTE. 'Mark' is a logic High. In
synchronous mode, the rising edge of RCLK occurs
in the middle of RXO.

In async mode RTS is ignored. Under command
control, in sync mode RTS can be ignored, or the
modem can respond with a Low on CTS.

RCLK*

DTR

Synchronous clock output. Rising edge of RCLK oc'curs in the middle of each RXO, bit. This pin remains
High in asynchronous mode.

&00 command will cause the modem to ignore OTR.
For &01 the modem assumes the asynchronous
command state on a Low to High transition of the
OTR circuit. The &02 command does the same as
&01 except the state of OTR will enable/disable
auto answer. A Low to High transition of OTR after
the &03 command will cause the modem to assume
the initialization state.

Vpp
This function is not used and should not be connected.
"External' code only.

4-12

intJ

89024

B/C"

REMlB"

Low configures the modem to CCITT V.21. High will
configure the modem to Bell 103, when at 300 bps
speed. This pin only affects the modem in FSK operation.

A logic Low on this pin initiates a remote loopback
condition.

51
Selects one of the two data rates or ranges of rates
in the DTE to correspond to the rate in modem. Low
selects the higher rate (2400 CCITT/1200 BELL) or
range of rates. High selects the Low rate or range of
rates.

TCl1, TClO
These pins are used as the serial clock and data for
interface to an NVRAM. Refer to Figure 3. TCLO is
used to output a clock and serial data is transferred
on TCL1.

DIS

A Low on this pin will indicate the smart mode which
will respond to all commands. A High will ignore all
commands.

This Auxiliary relay control is for switching a relay for
voice or data calls. High is voice, Low is data.

VREF
Voltage reference for the analog to digital converter
should be connected to the 89027 AVcc.

A Low signal from DAA indicates line ringing. This
input is ignored when the modem is configured for
leased line. This signal should follow the ring cadence.

VPD
The internal RAM power down supply voltage to be
connected to 5 Volts during normal operation.

OH
Low sets an off hook condition, high sets an on
hook. When dialing, this signal is used to pulse dial
the line.

S/A
The function of this pin is re-defined as external
NVRAM CEo

SH"
Used as a telephone voice to data switch or vice
versa. Any logic level transition will, toggle the modem state. This input is ignored, if a software command attempts to switch the modem between voice
and data.

CONFIG
Reserved for future use. This signal should be pulled
high.

EA
When High, memory access from address 2000H to
4000H are directed to on-chip ROM. When Low, all
memory access is directed to off-chip memory.

AA
Used as an indicator for Auto Answer status and
Ring indicator. Active low.

lCllB*
A Low will'set the modem in the iocal analog loopback test mode. Logic Low levels applied simultaneously to REMLB and LCLLB pins, sets the modem '
to the local digital loopback.

89026 ABSOLUTE MAXIMUM
RATINGS**

"WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.

+ 70°C
.......... -40°C to + 125°C

Voltage from Any Pin to
Vss or AGND ................. -0.3V to

"External code only

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Temperature Under Bias ............ O°C to
Storage Temperature

Low is used to pulse A and A 1 leads to control a 1A2
Key System jack. ,

+ 7.0V

Average Output Current from Any Pin ....... 10 mA
Power Dissipation ...................... 1.5 Watts

4-13

infef

89024

OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Units

Ambient Temperature Under Bias

+70

°C

Vee

Digital Supply Voltage

4.75

5.25

VREF

Analog Supply Voltage

4.75

5.25

FREQ

ClKIN Frequency 12.96 MHz

-0.01%

+0.01%

VPD

Power-Down Supply Voltage

4.75

5.25

NOTE:

The AGND and Vss on both the 89026 and the 89027 must be nominally at the same potential.

D.C. CHARACTERISTICS Test Conditions: Vee, VREF, VPD, Vpp, VEA
= 12.96 MHz; TA = O°C to 70°C, VSS, AGND = OV

= 5.0V ±0.25V;

Fosc

Symbol

Parameter

Ice

Vee Supply Current (O°C :s; T A :s; 70°e)

Icel

Vee Supply Current (TA

IpD

VpD Supply Current

IREF

VREF Supply Current

Min

70°C)

Max

Units

240

185

-0.3

Test Conditions
All Outputs
Disconnected
Normal Operation
and Power-Down

VIL

Input low Voltage

+0.8

VIH

Input High Voltage
(Except RESET, NMI, ClKIN)

2.0

Vee + 0.5

VIHl

Input High Voltage, RESET Rising

2.4

Vee + 0.5

VIH2

Input High Voltage, RESET Falling Hysteresis

2.1

Vee + 0.5

VIH3

Input High Voltage, NMI, ClKIN

2.2

Vee + 0.5

III

Input Leakage Current

SCLK

,...z ~
VJ

...'"x ... " "

vee

SDATA

STR

TSYNC

ClKOUT

..J

U
VJ

U
U

...'" "

..J

TX3

TX2

vss

TX2

AOl

Vss

AVee

CLKSEL

AVee

AGND

TXl

CLKSEL
AGND

TXO

RST

TXD

HYB

ClKOUT2

HYB

RST

AMP

CLKOUT2

AD2

AZ2

AZl

Vee

12131415161718

290272-4

290272-3

58-Pin PLCC

...:::> ...

..J
Q
Z 10>
:::E

...

'""

IV)

a '" ~ I~
'"

~
10>

:l ~ ILS

u
U

"';!;

Ill'"
IIl..J

> > u

'" "
X

" ...

a VJ
~
..J :::>
t> 0>

;!;

'"
:;i

llil
ADO

ADl
AGND

AD2

VREF
CDE

AD3
AD4

AD5

RST

AD6

SDATA

AD7

SClK

AD8

TClO

AD9

TCLl

AD10

sfi>.

AD11

RTS

AD12

CTS

AD13

STR

AD14
AD15

DTR

ClKIN2

XTCLK

290272-5

Figure 3. Device Packages
4-25

89C024LT

CALL ESTABLISHMENT,
TERMINATION AND RETRAIN
The 89C024lT modem system incorporates all protocols and functions required for automatic or manual call establishment. The modem system also incorporates all protocols and functions required for progress and termination of a data call. '
The modem chip set has a built-in auto-dialer, both
DTMF and Pulse type. It can detect dial, busy, and
ring back signals from the remote end, and will provide call progress messages to the user. The modem is also capable of re-dialing the last number
dialed.
The modem, when configured for auto-answer, will
answer an incoming call, remain silent for the two
second billing delay interval, and then transmit the
answer tones. Afterwards modem to modem identification and handshaking will proceed at a speed and
operating mode acceptable to both ends of the link.
The data call can also be setup by manual dialing. A
transition from voice (Le., for the purpose of manual
dialing) to data mode can be done by the use of a
mechanical switch (exclusion key) on the SH pin.
Once set to data mode, the modem handshaking will
proceed before the modems will be ready to accept
and exchange data.

by the remote modem, are of two types, (1) disconnect when receiving long-space, and (2) disconnect
when received carrier is dropped. The modem chip
set can also be configured to transmit "long-space"
just before disconnection.
Because the cCln and Bell modem connection
protocols do not provide recognition of remote modem type (Le. V.22 bis to 212A), the Intel chip set
provides the additional capability of identifying the
remote modem type. This feature is beneficial during
the migration phase of the technology from the 1200
bps to 2400 bps. In North America, where the installed base of 1200 bps modems is mostly made-up
of 212A type, this feature allows a "Data Base Service Provider" to easily upgrade the existing 212A
modems to 2400 bps V.22 bis standard, transparently, to 212A users. Similarly, a user with a 89C024lT
based modem system can automatically call data
bases with either 212A or V.22 bis modems, without
concern over the difference. This feature's benefits
are realized in smooth upgrading of data links, with
minimum cost and reduced disruption in services.
Refer to Table 1 for a detailed description of remote
modem compatibility.

SOFTWARE CONFIGURATION
COMMANDS
This section lists the 89C024lT commands and registers that may be used while configuring the modem. Commands instruct the modem to perform an
action, the value in the associated registers determine how the commands are performed, and the result codes returned by the modem tell the user
about the execution of the commands.

The commands may be entered separately or in
string fashion. Any spaces within or between commands will be ignored by the modem. During the entry of any command, the 'backspace' key (CNTRl H)
can be used to correct any error. Upper case or lower case characters can be used in the commands.
Commands described in the following paragraphs
refer to asynchronous terminals using ASCII codes.

Disconnection of the data call can be initiated by the
DTE at the local end or by the remot-e DTE (if the
modem is configured to accept it). Whether DTR will
initiate a disconnect depends on the last &D command. Receiving a long space from a remote modem will initiate a disconnect only after a Y1 command. The optional disconnect requests, originated

4-26

89C024LT

Table 1. Remote Modem Compatibility
Originating
89C024LT
Modem
Bell
CCITT

300
1200
300
1200
2400

Answering
89C024LT
Modem
Bell
CCITT

300
1200
300
1200
2400

Bell
300

Bell
1200

300
1200'

300
1200

1200'
1200'

1200
1200

300
-

Bell
300

8ell
1200

300
300

1200
1200

300'
300'

1200
1200

Answering Modem
CCITT
CCITT
300
1200
300'
1200
1200
1200

Originating Modem
CCITT
CCITT
1200
300

300

CCITT
2400
300'
1200
1200
2400

CCITT
2400

1200
1200

1200
2400

* These connection data rates are obtained when connecting 89C024LT based modems end to end. The same results may
not be obtained when a 89C024LT based modem is connected to other modems.

Command Set
AT

A
AI
Bn
Ds
En
Hn

In
Ln
Mn

Sn=x
Sn?
Vn
Xn
Yn

+++

MNP Feature Control Command Set

Attention code.
Go off-hook in answer mode
Repeat previous command string
BELL/CCITT Protocol Compatibility at
300 and 1200 bps
The dialing commands
(O·g ABC D • # P R T S W ,; @)
Echo command (En)
Switch-Hook Control
If &J1 option is selected, H1 will also
switch the auxiliary relay
Request Product Code and Checksum
Speaker Volume
Monitor On/Off
On-Line
Result Codes
Write S Register
Read S Register
Enable Short-Form Result Codes
Enable Extended Result Code
Enable Long Space Disconnect
Fetch Configuration Profile
The Default Escape Code

\An
%An
\Bn
\Cn
\Gn

\In
\Kn
\Nn

\0
\On
\Tn
\U

Wn
\Xn

\Y
\Z

Maximum MNP Block Size
Set Auto·Reliable Fallback Character
Transmit Break
Set Auto·Reliable Buffer
Set Modem Port Flow Control
Bits per Second Rate Adjust
Set Break Control
Set Operating Mode
Originate Reliable Link
Set Serial Port Flow Control
Set Inactivity Timer
Accept Reliable Link
Modify Result Code Form
Set XON/XOFF Pass·Through
Switch to Reliable Mode
Switch to Normal Mode

& Command Set
&Cn
&Dn
&Fn
&Gn

DCDOptions
DTROptions
Fetch Factory Configuration Profile
Guard Tone
&In Telephone Jack Selection
&Ln Leased/Dial·up Line Selection
&Mn Async/Sync Mode Selection
&Pn Make/Break Pulse Ratio
&Rn RTS/CTS Options
&Sn DSR Options
&Tn Test Commands
&Wn Write Configuration to Non Volatile Memory
&Xn Sync Clock Source
&Yn Default NVRAM Profile Select
&Zn Store Telephone Number

+ Command Set
Disable/Enable Power Down
Time to Power Down
4·27

inter

89C024LT

CONFIGURATION REGISTERS
The modem stores all the configuration information
in a set of registers. Some registers are dedicated to
a special command and function, and others are bitmapped, with different commands sharing the register space to store the command status.
SO·
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11'
S12
S13
S14'
S15
S16
S17
S18'
S19
S20
S21'
S22'
S23'
S24
S25'
S26'
S27'
S31'

Ring to Answer
Ring Count. (Read Only)
Escape Code Character
Carriage Return Character
Line Feed Character
Back Space Character
Wait for Dial Tone
Wait for Data Carrier
Pause Time for the Comma Dial Modifier
Carrier Detect Response Time
Lost Carrier to Hang Up Delay
DTMF Tone Duration
Escape Code Guard Time
Not Used
Bit Mapped Option Register
Not Used
Modem Test Options
Not Used
Test Timer
Not Used
Not Used
Bit Mapped Options Register
Bit Mapped Options Register
Bit Mapped Options Register
Not Used
Delay to DTR (Sync Only)
RTS to CTS Delay (Half Dup.)
Bit Mapped Options Register
Bit Mapped Options Register

Example:
Terminal: AT &20 = T 1 (602) 555-1212
Modem: OK
Result:
Modem stores the Tone Dial (T) modifier
and phone number T16025551212 in the
external NVRAM.
The number can be dialed from asynchronous mode
by issuing the following command:
Terminal: AT DSO
Modem: T16025551212
Result:
Modem dials phone number and attempts
to establish a connection.
or by turning on DTR when in Synchronous Mode 2.
Up to 33 symbols (dial digits and dial modifiers) may
be stored. Spaces and other delimiters are ignored
and do not need to be included in the count. If more
than 33 symbols are supplied, the dial string will be
truncated to 33.

POWER MANAGEMENT
The flexible power management controls allow for a
variety of command and hardware driver options.
The power down sequence is initiated by placing a
logic "low" on pin 15 (PD) of the 89C026LT. The
laptop can control the PD signal directly. If such a
signal is unavailable, PD can be controlled by communications software via DTR. Lack of data activity
or an in,coming ring signal can also be used to control PD.
Placing the crystal on the 89C026LT (Figure 10) allows it to reduce power consumption by turning off
the oscillator. When online and connected to a remote modem, the power consumption for the
89C024LT is typically 400 mW. Additionally, when
the 89027 is not needed (on-hook, not connected to
a remote modem) the 89C026LT places it in standby. In standby the chip set power consumption is
typically 255 mW. When powered down via the PD
pin on the 89C026LT, the chip set typically consumes 5 mW. Minimum memory-system power-consumption can be achieved by chip selecting memory
only when addressed.

NOTE:
• These S registers can be stored in the NVRAM.

DIALING
Dial modifiers are available for adding conditions to
dialed phone numbers.
Dial Modifiers
P
Pulse Dial
R
Originate call in Answer Mode
T
Tone Dial
S
Dial a stored number
W Wait for dial tone
Delay a dial sequence
Return to command state
!
Initiate a flash
@
Wait for quiet

APPLICATIONS OVERVIEW
The block diagram of a stand-alone 300 to 2400 bps
Hayes compatible modem is depicted in Figure 4.
The DAA section shown in this diagram may be implemented using the suggested diagram in Figure 5.
Figure 6 shows the use of the power-down feature.

4-28

intJ

89C024LT

POWER SUPPI.. Y

DGHO

RST

+5 VOLTS

AGNO

AUDIO

-5 VOLTS

tolONITOR

HYB

TIP

AZ,
AZ2

A"P

RING

.015,uF

AO'

TRXCAR

A02

RCVCAR

TXO
TX' JrRANS"IT
LEVEL
TX'

SERIAL
PORT

TX2

LAPTOP

SELECT

T'"'P
RING
"'C

290272-6

Figure 4. Typical Laptop Modem

,-----1--+ TIP
..-1-_______________+_-.
~r-------------------------,

.-+---+_ RING
"'C

AUXILIARY
BUSINESS
PHONE

10K
+5V

-+++ RING

b-....

I'g
to

A02/+-....- -....- - . .

TELEPHONE
LINE OR
DATA PHONE

AD1

~--+---------~O

b-+.....+++TlP

~~-------~

~L---------[iE~X~CL~U~SI~ON~KIT~~::::::::::::::~
r
STATE DETECTOR

290272-7

Figure 5. Typical Telephone Line Interface Using Internal Hybrid
:~~E~~p~~~

-----0

89C026LT

IDTR~
IRI

Vpp

TXD

RXO

1.0J.l.F/

DGNO

Figure 6. Power-Down Control
4-29

290272-13

89C024LT

SYSTEM COMPATIBILITY SPECIFICATIONS
Spe~ification

Parameter
Synchronous
Asynchronous

2400 bps ± 0.01 %
1200 bps ±0.01%

V.22 bis
V.22 and BELL 212A

2400, 1200 bps, character asynchronous.

o- 300 bps an isochronous.

Asynchronous Speed Range

+ 1% :- 2.5% default. Extended + 2.3% - 2.5% range of CCITT
standards optional via software customization.

Asynchronous Format

10 bits, including start, stop, parity. (8, 9, 11 bits optional via S/W
customization.)

Synchronous Timing Source

a) Internal, derived from the local oscillator.
b) External, provided by DTE through XTCLK.
c) Slave, derived from the received clock.

Telephone Line Interface

Two wire full duplex over public switched network .or 4 wire
leased lines.
On-chip hybrid and billing delay timers.

Modulation

V.22 bis, 16 point QAM at 600 baud.
V.22 and 212A, 4 point PSK at 600 baud.
V.21 and 103, binary phase coherent FSK

Output Spectral Shaping

Square root of 75% raised cosine, QAM/PSK.

Transmit Carrier Frequencies
V.22 bis, V.22, 212A
V.21

Bell 103 mode

Received Signal Frequency Tolerance
V.22 bis, V.22, 212A
V.21

Bell 103

Originate
Answer
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'

1200 Hz
2400 Hz
1180 Hz
980 Hz
1850 Hz
1650 Hz
1070 Hz
1270 Hz
2020 Hz
2225 Hz

±
±
±
±
±
±
±
±
±
±

Originate
Answer
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'

2400 Hz ±
1200 Hz ±
1850 Hz ±
1650 Hz ±
1180 Hz ±
980 Hz±
2020 Hz ±
2225 Hz ±
1070 Hz ±
1270 Hz ±

.02%
.02%
.02%
.02%
.02%
.02%
.02%
.02%
.02%
.02%
7 Hz
7 Hz
12 Hz
12 Hz
12 Hz
12 Hz
12 Hz
12 Hz
12 Hz
12 Hz

Typical Energy Detect Sensitivity

Greater than -43 dBm ED is ON. Less than -48 dBm ED is
OFF. Signal in dBm measured at A02.

Energy Detect Hysteresis

A minimum Hysteresis of 2 .dB for QAM scrambled mark.

Line Equalization

Fixed compromise equalization, transmit.
Adaptive equalizer for PSK/QAM, receive.

Diagnostics Available

Local analog loopback.
Local digital loopback.
Remote digital loopback.

Self Test Pattern Generator

Alternate 'ones' and 'zeros' and error detector, to be used along
with most loopbacks.
A number indicating the bit errors detected is sent to DTE.

4-30

inter

89C024LT

RECEIVER PERFORMANCE SPECIFICATIONS
Typical SNR for
10- 5 BER Performance

Test Cases
Data
Mode

Rx Level
(dBm)

Answer
(dB)

Originate
(dB)

16.5

V.22 bis
Synchronous

-30

-40

16.5

V.22/Bell 212A
Synchronous

-30

6.5

-40

6.5

V.21
Asynchronous

-30

7.5

-40

Bell 103
Asynchronous

-30

11.5

-40

11.5

Test Conditions:
-

Receive Signal (Rx) measured at A02 (transmit level set at - 9 dBm)

Unconditioned 3002 Line

3 KHz Flat-Band Noise

PERFORMANCE SPECIFICATIONS
Parameter

Min

DTMF Level

Typ

Max

4.0

dBm
-35

DTMF Second Harmonic
DTMF Twist (Balance)

Units

Comments

atA01
HYB enabled into 600n

100

Software Controlled

Pulse Dialing Rate

10/20

pps

Software Controlled

Pulse Dialing Make/Break

39/61
33/67

%
%

qefault DTMF Duration

Pulse Interdigit Interval

785

ms
2.1

Billing Delay Interval

sec

540
-3

Hz
dB

1800
-6

Hz
dB

Dial Tone Detect Duration

3.0

sec

Ringback Tone Detect
Duration
Cadence

0.75
1.5

sec

Guard Tone Frequency
Amplitude
Frequency.
Amplitude

Busy Tone Detect
Duration
Cadence

US
UK, Hong Kong

referenced to High
Channel transmit.
QAM/PSK Modes Only

Off/On Ratio

0.2

sec

0.67

1.5

4-31

Off/On Ratio

89C024LT

eration, DPSK and QAM is used to send 2 to 4 bits
of information respectively at 600 baud to the AFE.
Because the QAM coding technique is an inherently
synchronous transmission mechanism, in the case
of asynchronous QAM transmission, the asynchronous data is synchronized by adding or deleting stop
bits. Following the synchronization process, the
89CD26LT transmits digitized phase and amplitude
samples to 89027 over the high speed serial link.

89C026LT OVERVIEW
The 89CD26LT processor performs data manipulation, signal processing and user interface functions.
It requires a single ROM and RAM to execute standard, and/or custom code with high level protocol
functions. A block diagram of the 89CD26LT is provided in Figure 7.
89CD26LT contains a TTL compatible serial link to
DTE equipment, along with a full complement of
V.24/RS-232-C control signals. A UART or USART
may be used to transfer data to and from a microcomputer bus. The 89CD26LT supports the industry
standard AT command set facilitating compatability
with most PC software.

In the receive operation, the information is received
by the 89C026LT from the 89027 as two signals
which are 90. degrees phase shifted from each other. These analog signals are then digitized by the
AID converter resident on the 89C026LT. By using
DSP algorithms, the received signals are processed
using adaptive equalization for telephone line delay,
amplitude distortion and gain adjustments and the
signal demodulated. Following demodulation, the
data is unscrambled, and if necessary, returned to
asynchronous format.

During transmit operation, the 89C026LT synthesizes DTMF tones and the 300. BPS FSK modem
signal and transmits them to the 890.27 as digitized
amplitude samples. During 120.0 and 240.0. BPS op-

.--------------------------------------------------------.

I~-------I~ I

I
I

..... - - - - - - + - 0

I
I

I
I
I

RXD(103)
TDX(104)
. TCLK(114)
RClK(ll5)
XTClK(ll3)
RTS
CTS

AUTO BAUD-RATE/
DATA FORMAT
DETECTOR

---{--+
.......1..-..+

-+-+

DTR~

COMMAND INTERPRETER

~el

DATA
RETRAIN
lOOPBACK
PATIERN
DETECT

« ...
..J!!!

DSR
I
~t"l
REMlB(140) ---:......... ~ ~
lCllB(141) ~ 8~

1+_ _ _ _ _ _ _-.

fM
DCD

~ 0~

s/A --:---+

a5~R 1-_-+1

DATA

TClO ~ ~>=
TCll ~ ~Ci1
CONFIG --.--+ ;;#.

PO -!--+
OH
I

MNP
PROTOCOL
ENGINE
TSYNC
SCLK
SDATA

DATA

Ali

SE ---{--+
III --;--+

D/S--+
I
I
I
I
I

--1---r -r- T-T--T---r---r---------------------------!
RST

CDE

Vee VSSl

VSS2

AGND

VPP
290272-8

Figure 7. 89C026LT Block Diagram

4-32

infef

89C024LT

89C026LT PINOUT
Symbol

Function (89C024LT)

Direction(4)

Pin No.

ClKIN
ClKIN2
RST

12.96 MHz master clock from 89027
270 KHz from 89027
Chip reset (active low)

In
In
In

67
44
16

I
STR
ED

In-phase received signal
Ouadrature-phase received signal
Symbol Timing from 89027
Energy Detect input

In
In
In
In

11
10
24
9

TSYNC
SDATA
SClK

Transmitter sync pulse to 89027
Serial Data to 89027
Serial Clock to 89027

Out
Out
Out

35
17
18

OH
SH
RI
AR

Off-Hook control to DAA
Switch-Hook from dataphone
Ring Indicator from DAA
Aux Relay control to DAA

Out
In
In
Out

33
5
42
38

TCl1
TClO
PD
S/A
D/S
CONFIG

NVRAM Data I/O
NVRAM ClK
Power-down control
NVRAMCE
Dumb/Smart mode select
Reserved for future use (VeC>(2)

I/O
Out
In
Out
In
In

20
19
15
21
6
8

Test Mode Indicator

Out

TXD
RXD
RTS
CTS
DSR
DCD
DTR
RClK
TClK
XTCLK
REMlB
lCllB

Transmitted data from DTE
Received data to DTE
Request to send from DTE
Clear to Send to DTE
Data Set Ready to DTE
Data Carrier Detect to DTE
Data Terminal Ready from DTE
Received clock to DTE
Transmit clock to DTE
External timing clock from DTE
Speed Indicator to DTE
Remote loopback Command from DTE
local loopback Command from DTE

In
Out
In
Out
Out
Out
In
Out
Out
In
Out
In
In

27
29
22
23
30
31
25
34
28
26
32
7
4

Vee
CDE
VREF
VSS1
VSS2
AGND
Vpp

Positive power supply ( + 5V)
Clock detect enable (VSS)(1)
A/D converter reference
Digital ground
Digital ground
Analog ground
Timing pin for return from power-down

+5V
GND
+5V
GND
GND
AGND
In

1
14
13
36
68
12
37

EA
ADO-AD15
AA
JS
CD
MR
REl
CLASS5
ERR

External Memory enable
External memory access address/data(3)
Auto Answer(3)
Jack Select(3)
Carrier Detect Indicator(3)
Modem Ready Indicator(3)
MNP Reliable Link Active(3)
MNP Class 5 Compression Active(3)
Error detected by MNP(3)

In
I/O
Out
Out
Out
Out
Out
Out
Out

4-33

2
60-45
60
59
58
57
56
55
54

intJ

89C024LT

89C026LT PINOUT (Continued)
Symbol

NMI
X2
CLKOUT
BUSWIOTH
INST
ALE
RO
READY
BHE
WR

Function (89C026L

Directlon(4)

Non-maskable Interrupt(Vss)(1)
Crystal output
Clkoutput
Bus Width
External memory instruction fetch
Address latch enable
External memory read
External memory ready
External memory bus high enable
External memory write

In
Out
Out
In
Out
Out
Out
In
Out
Out

Pin No.
3
66
65
64
63
62
61
43
41
40

NOTES:
1. Pins marked with (Vss) must be connected to Vss:
2. Pins marked with (Vee) must be connected to Vee.
3. ADO-AD3 are used as AA, JS, CD, MR , REL, CLASS 5, and ERR respectively.
4. Pins with direction "IN" must not be left floating.

Transmitter timing from OTE, when external clock
option is selected.

down option is used. This capacitor causes an internal timing circuit to give the oscillator time tostabilize before turning on· internal clocks. This pin may
be left floating or connected through a 1.0· p.F capacitor to Vss if power-down mode is not required.

TXD

89C026LT PIN DESCRIPTION

XTCLK

A low indicates maintenance cQndition in the modem.

The serial data from OTE to be transmitted on the
line. A logic 'high' is mark. In synchronous mode,
89C026LT samples this data on the rising edges of
TCLK.

DCD

In async operation, OCO remains low regardless of
data carrier (default), or it can be programmed to
indicate received carrier signal is within the required
timing and amplitude limits. In sync operation low
indicates the received carrier signal is within the required timing and amplitude limits.

TCLK
Clock output from 89C026LT as timing source for
data exchange from DTE to modem. Serial data is
'read on the rising edges of the TCLK. This output is
High in asynchronous mode.

RXD

DSR

The serial data to OTE. A logic 'high' is mark. In
synchronous mode, the rising edge of RCLK occurs
in the middle of RXO.

A low indicates modem is off-hook, is in data transmission mode, and the answer tone is being exchanged. CTS low indicates modem is prepared to
accept data.

RCLK

RTS

Synchronous clock output. Rising edge of RCLK occurs in the middle of each RXO bit. This pin remains
High in asynchronous mode.

In async mode RTS i~nored. Under command
control, in sync mode RTS can be ignored, or the
modem can respond with a Low on CTS.

DTR

Power-down control. A low on this input pin, in conjunction with the + En and + Tn commands, will
cause the modem to. go into a power-down mode.

&00 command will cause the modem to ignore OTR.
For &01 the modem assumes the asynchronous
command state on a low-to-high transition of the
OTR circuit. The &02 command does the same as
&01 except the state of OTR will enable/disable
auto answer. A low-to-high transition of OTR after
the &03 command will cause the modem to assume
the initialization state.

Vpp

Timing pin for return from power-down. Connect· a
1.0 p.f capacitor between Vpp and Vssif the power-

4-34

89C024LT

TCl1, TClO

ERR

These pins are used as the serial clock and data for
interface to an NVRAM. Refer to Figure 3. TCLO is
used to output a clock and serial data is transferred
in on TCL1.

Goes low for 1 second whenever MNP detects an
error.

Sf
Selects one of the two data rates or ranges of rates
in the DTE to correspond to the rate in modem. Low
selects the higher rate (2400 CCITT11200 BELL) or
range of rates. High selects the Low rate or range of
rates.

AR
This Auxiliary relay control is for switching a relay for
voice or data calls. High is voice, low is data.

DIS

A low signal from DAA indicates line ringing. This
input is ignored when the modem is configured for
leased line. This signal should follow the ring cadence.

A low on this pin will indicate the smart mode which
will respond to all commands. A High will ignore all
commands.

VREF

Low sets an off hook condition, high indicates an on
hook. When dialing, this signal is used to pulse dial
the line.

Voltage reference for the analog to digital converter
should be connected to the 89027 AVcc.

CDE
SH

This pin must be connected to Vss.

Used as a telephone voice to data switch or vice
versa. Any logic level transition will toggle the modem state between voice and data.

S/A
The function of this pin is re-defined as external
NVRAM CEo

AA
Used as an indicator for Auto Answer status and
Ring indicator. Active low.

CON FIG
Reserved for future use. This signal should be pulled
high.

lCllB

A low will set the modem in the local analog loopback test mode. Logic Low levels applied simultaneously to REMLB and LCLLB pins, sets the modem
to the local digital loopback.

When high, memory access from address 2000H to
4000H are directed to on-chip ROM. When low, all
Memory access is directed to off-chip memory. This
pin must be tied high.

REMlB
A low on this pin initiates a remote loopback condition.

Low is used to pulse A and A1 leads to control a 1A2
Key System jack.

BUSWIDTH

A Low indicates the presence of carrier signal on the
line.

When high, external memory accesses are 16 bits
wide. When low, external memory accesses are 8
bits wide. This pin must be tied low.

MR
A low indicates the presence of the DSR signal.
Toggling indicates that a test mode is active.

READY
When high, no wait states are inserted in external
memory accesses. When low, one wait state is inserted in each external memory access.

REl
A low indicates that an MNP reliable link has been
established.

ClASS5
A low indicates that MNP Class 5 (data compression) is in operation.

4-35

intJ

89C024LT

89C026LT ABSOLUTE MAXIMUM
RATINGS*

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice.

Temperature Under Bias ............ O°C to + 70°C
Storage Temperature .......... -40°C to + 125°C

Voltage from Any Pin to
VssorAGND ................. -0.5Vto +7.0V
Average Output Current from Any Pin ....... 10 mA
Power Dissipation ...................... 1.5 Watts

OPERATING CONDITIONS
Symbol
TA

Parameter

Min

Max

Units

Ambient Temperature Under Bias

+70

°C

Vee

Digital Supply Voltage

4.75

5.25

"REF

Analog Supply Voltage

4.75

5.25

fose

ClKIN Frequency

12.95870

12.96130

MHz

NOTE:

The AGND and Vss on both the 8ge026LT and the 89027 must be nominally at the same potential.

D.C. CHARACTERISTICS
Symbol
VIL

Parameter
Input low Voltage

Typ(7)

Max

Units

-0.5

+0.8

Min

VIH

Input High Voltage(l)

0.2 Vee + 0.9

Vee + 0.5

VIHl

Input High Voltage on ClKIN

0.7 Vee

Vee + 0.5

VIH2

Input High Voltage on RESET

2.2

Vee + 0.5

VOL

Output Low Voltage

0.3
0.45
1.5

V
V
V

VOH

Output High Voltage(4)

Vee - 0.3
Vee - 0.7
Vee - 1.5

V
V
V

VOHl

Output High Voltage(3)

Vee - 0.3
Vee - 0.7
Vee - 1.5

V
V
V

III

Input Leakage Current(5)

ILil

±10

p,A

Input Leakage Current(6)

±3

p,A

IlL

logical 0 Input Current(3)

-50

p,A

IILl

logical 0 Input Current
in RESET(2) (ALE, RD,
WR, BHE, INST, SClK)

-850

p,A

4-36

Test Conditions

= 200 p,A
= 3.2mA
= 7mA
IOH = -200 p,A
IOH = -3.2mA
IOH = -7mA
IOH = -10 p,A
IOH = -30 p,A
IOH = -60 p,A
o < VIN < Vee 0< VIN < VREF
VIN = 0.45V
VIN = 0.45V

IOL
IOL
IOL

0.3V

89C024LT

D.C. CHARACTERISTICS (Continued)
Symbol
IREF

Parameter

Min

AID Converter

Typ(7j

Max

Units

Test Conditions

CLKIN = 12.96 MHz
Vec = Vpp = VREF = 5.25

CLKIN

Reference Current
ICCI

Active Mode Current
(Typical)

RRST

RESET Pullup Resistor

Pin Capacitance
(Any Pin to VSS)

IpD

Power-Down Mode Current

50K

fTEST

/-LA

Vcc

12.96 MHz

1.0 MHz

Vpp

VREF

5.25

NOTES:

(Notes apply to all specifications)
1. All pins except RESET and ClKIN.
2. Holding these pins below VIH in RESET may cause the part to enter test modes.
3. TClO, TCl I, S/A, RTS, CTS, DSR, DCD, ST, OH.
4. BHE, INST, ClKOUT, RESET, TClK, RXD, RClK, TSYNC, TM, SClK, SDATA. The VOH specification is not valid for
RESET.
5. CDE, EA, READY, BUSWIDTH, NMI, STR, DTR, XTCLK, TXD, B/C, CLKIN2, and RI.
6. SID, SH, REMlB, LCLLB, I, Q, CON FIG, ED.
7. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vcc = 5V.

A.C. CHARACTERISTICS (Over specified operating conditions)
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times

10 ns, fosc 12.96 MHz

This system must meet these specifications to work with 89C026LT:
Symbol

Parameter

Min

Max

Units

TAVYV

Address Valid to READY Setup

2Tosc - 85

TLlYV

ALE Low to READY Setup

Tosc - 72

TYLYH

Non READY Time

TClYX

READY Hold after CLKOUT Low

hLYX

READY Hold after ALE Low

TAVGV

Address Valid to Buswidth Setup

TLLGV

ALE Low to Buswidth Setup

TCLGX

Buswidth Hold after CLKOUT Low

No Upper Limit.

Notes

Tosc - 30

(Note 1)

Tosc - 15

2 Tosc - 40

(Note 1)

2 Tosc - 85

Tosc - 70

ns
ns

TAVDV

Address Valid to Input Data Valid

3 Tosc - 67

TRlDV

RD Active to Input Data Valid

Tosc - 23

TCLDV

CLKOUT Low to Input Data Valid

Tosc - 50

TRHDZ

End of RD to Input Data Float

Tosc - 20

TRXDX

Data Hold after RD Inactive

NOTE:

1. If max is exceeded, additional wait states will occur.

4-37

89C024LT

A.C. CHARACTERISTICS (Continued)
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall tines = 10 ns, fOSC 12.96 MHz
The 89C026LT will meet these specifications:
Symbol

Min

Max

Units

12.95870

12.96130

MHz

1/FCLKIN(MAX)

1/FCLKIN(MIN)

110

Parameter

FCLKIN

Oscillator Frequency

Tosc

Oscillator Period

TXHCH

FCLKIN High to CLKOUT High or Low

TCLCL

CLKOUT Cycle Time

TCHCL

CLKOUT High Period

TOSC - 10

Tosc + 10

TCLLH

CLKOUT Falling Edge to ALE Rising

-5

TLLCH

ALE Falling Edge to CLKOUT Rising

-15

TLHLH

ALE Cycle Time

TLHLL

ALE High Period

Tosc - 10

TAVLL

Address Setup.to ALE Falling Edge

TOSC - 20

ns
ns

Address Hold after ALE Falling Edge ,

TOSC - 40

ALE Falling Edge to RD Falling Edge

Tosc - 40

TRLCL

RD Low to CLKOUT Falling Edge

TRLRH

RD Low Period

TRHLH

RD Rising Edge to ALE Rising Edge

TRLAZ

RD Low to Address Float

TLLWL

ALE Falling Edge to WR Falling Edge

TCLWL

CLKOUT Low to WR Falling Edge

TQVWH

Data Stable to WR Rising Edge

4 TOSC

TLLAX

Tosc + 10

TosC - 5

TosC + 25

TOSC+ 25

TosC

ns
ns

Tosc - 23

TCHWH

CLKOUT High to WR Rising Edge

-10

TWLWH

WR Low Period

TOSC - 30

TOSC + 5

TWHQX

Data Hold after WR Rising Edge

TosC - 10

TWHLH

WR Rising Edge to ALE Rising Edge

TosC - 10

TOSC + 15

TWHBX

SHE, INST, Hold after WR Rising Edge

Tosc - 10

TRHBX

SHE, INST, Hold after RD Rising Edge

TOSC - 10

TWHAX

AD8-15 Hold after WR Rising Edge

TOSC - 50

TRHAX

AD8-15 Hold after RD Rising Edge

TOSC - 25

NOTES:
1. Typical specifications, not guaranteed.
2. Assuming back-to-back bus cycles.

4-38

(Note 2)

Tosc - 10
0

(Note 1)

2 Tosc

hLRL

Notes

(Note 2)

intJ

89C024LT

WAVEFORMS

CLKIN

CLKOUT

ALE

--o.J--- tLLRL --+f.o>--

BUS

tAVLL ---.,,~-

-<,:-__

..;A..;D.;.D..;RE;;.;S.;.S_O..;U_T_ _~

':-_~;';';';;~~~-:--! ,-__A_D.;.D_RE_S_S_ __

BHE,INST

VALID

ADB-1S

ADDRESS OUT
290272-9

CLKIN

CLKOUT

ALE

READY

tAVYV I
.
__~____tA_V_G_Vt=::1
BUS WIDTH

BUS

--<

j~
tLLGV

ADDRESS OUT

II-~-;""'/'''''''-'~

(

)

DATA

»}

\~_____________________-J~
290272-10

Figure 8. Bus Signal Timings

4-39

intJ

89C024LT

shaping filters, combined with the necessary guard
tone, smoothed by a low pass filter, and transmitted
to the line. Prior to trans'mitting either FSK or QAM
signals to the telephone line, the 89027 adjusts the
signal gain through an on-board programmable gain
amplifier.

89027 OVERVIEW
The 89027 is a 28 pin CHMOS analog front end device, which performs most of the complex filtering
functions required in modem transmitters and receivers. A general block diagram of this chip is provided in Figure 9. Most of the analog signal processing functions in this chip are implemented with
CHMOS switched capacitor technology. The 89027
functions are controlled by 89C026LT, through a
high speed serial data link.

During the receive operation, the received FSK and
QAM signals are passed through anti-alias filters,
band split filters, automatic gain control and carrier
detect circuits, a Hilbert transform filter, and the output sent to the 89C026LT processor as analog signals.

During FSK transmit operation, the 89027 receives
digitally synthesized mark and space sinusoid amplitude information from the 89C026LT. The 89027
converts the signal to its analog equivalent, filters it,
and transmits it to the telephone line. For QAM
transmission, the signal constellation points are
transferred to the 89027. This information is modulated into an analog signal, passed through spectral

Other functions provided by the 89027 are: an onboard two wire to four wire circuit with disable capability, an audio monitor output with software configurable gain, and a programmable gain transmit signal.
The 89027 is available in 28 pin plastic DIP and
PLCC packages.

,.-----------------------------------------------------------------.
...----4---;+ AhlP
Xl

X2
A02
HYB

AOI

r---r--1---T-- ------

• - T- -1--Vee

vaa

AGNO

vss

RST

AVee

AZ2

AZI

OUTPUT LEVEL
TX3-TXO

290272-11

Figure 9. 89027 Block Diagram

4-40

intJ

89C024LT

89027 PINOUT
Symbol

Function (89027)

Vcc
VBB
Vss
AGND
AVcc

Positive Power Supply (Digital)
Negative Power Supply
Digital Ground
Analog Ground
Positive Power Supply (Analog)

X1
X2
CLKOUT
CLKOUT2

Xtal Oscillator
Xtal Oscillator
12.96 MHz Clock Output to 89C026LT
270 KHz Clock Output to 89C026LT

RST
HYB
AZ1
AZ2

Chip reset (active low)(3)
Enable on-chip hybrid(1)
Auto-zero capacitor
Auto-zero capacitor

SDATA
SCLK
TSYNC

Serial data from 89C026LT
Serial clock from 89C026LT
Transmitter sync from 89C026LT

STR
ED
I
Q

Direction

Pin No.

+5V
-5V
DGND
AGND
+5

28
15
24
21
7

In
Out
Out
Out

23
25
26
19

In
In
In

20
10
16
17

In
In
In

2
1
3

Symbol timing to 89C026LT
Receiver energy detect to 89C026LT
In phase received signal to 89C026LT
Quadrature-phase received signal to 89C026LT

Out
Out
Out
Ouf

27
18
13
14

A01
A02
AMP

Transmitter output
Receiver input
Output to monitor speaker

Out
In
Out

6
12
11

TXO
TX1
TX2
TX3

Transmitter level
Transmitter level
Transmitter level
Transmitter level

In
In
In
In

9
8
5
4

(Note 2)

Out

control (LSB)(1)
control(1)
control(1)
control (MSB)(1)

NOTE:

1. When held high, these pins must be connected through 10K resistors to Vee.
2. Reserved Pin. Must be left No Connect.
3. Connect to reset circuitry through a 10K resistor.

A01

89027 Pinout Description

Transmitter output.

TXO-3

A02

These four pins control the transmitted signal level.
Refer to Transmit Level Table.

Receiver input.

HYB

AMP

This pin enables the on-chip hybrid. A line impedance matching network must be connected between
A01 and A02 when HYB is enabled. If HYB is disabled and an external 4W/2W hybrid is used, the
hybrid receive path must be amplified by 6 dB.

This output can be used to monitor the call progress
tones and operation of the line.

4-41

89C024LT

NOTES:
1. Applies to pins SCLK, SDATA, TSYNC, RST,
HYB, TXO-TX3 only.
2. Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS(2)
Storage Temperature ............ - 40 to

+ 70° C
+ 125° C

All Input and Output Voltages
with Respect to VBB .......... - 0.3V to

+ 13.0V

Temperature Under Bias ............. 0 to

All Input and Output Voltages
with Respect to Vee & AVec ..... -13.0V to 0.3V
Power Dissipation ........................ 1.35W
Voltage with Respect
to V SS(1) ....................... - 0.3V to 6.5V

OPERATING CONDITIONS
Symbol

Parameter

Min

Max

Units

Ambient Temperature Under Bias

+.70

°C

Vee

Digital Supply Voltage

4.75

5.25

VBB

Analog Supply Voltage

-4.75

-5.25

POWER DISSIPATION AmbientTemp = 0° to 70° C, Vee = AVee= 5 ± 5%, Vss= AGND= OV.
Symbol

Parameter

Min

Typ

Max

Units

AlcC1

AVec Operating Current

ICC1

Vee Operating Current

Ibb1

VBB Operating Current

-15

-21

Alccs

AVec Standby Current

0.2

Iccs

Vee Standby Current

-2

Ibbs

VBB Standby Current

-0.6

Alccp

AVec Power-Down Current

100

}J-A

Icc p

Vee Power-Down Current

450

}J-A

Ibbp

VBB Power-Down Current

450

Pdo

Operating Power Dissipation

175

250

Pds

Standby Power Dissipation

Pdp

Power Down Power Dissipation

4-42

}J-A

89C024LT

D.C. CHARACTERISTICS (TA=O°C to 70°C, AVee = Vee = 5V ±5%, VBB = 5V ±5%, AGND =
Vss = OV), supply voltage must be at the same potential as the 89C026LT power supply. Typical Values are
for TA = 25°C and nominal power supply values. Vee, and AVee. Vee, AVee and 89C026LT VREF must be
nominally at the same potential.
Inputs: TXO, TX1, TX2, TX3, HYB, RST
Outputs: CLKOUT
Symbol

Parameter

Min

Max

Units

Iii

Input Leakage Current

-10

+10

IJoA

Vii

Input Low Voltage

Vss

0.8

Vih

Input High Voltage

2.0

Vee

Vol

Output Low Voltage

0.4

Voh

Output High Voltage

Vcol

CLKOUT Low Voltage

Vcoh

CLKOUT High Voltage

2.4
0.4
0.7 Vee

Test Conditions

Vss

oS:

Yin

oS:

Vee

101 :? -1.6mA,1 TIL load

loh

Load Capacitance = 60 pF

oS:

50lJoa, 1 TIL load

A.C. CHARACTERISTICS (TA = 25°C, Vee = AVee = 5V, Vss = AGND = OV, VBB = -5V)
ANALOG INPUTS:A02
Parameter

Min

Typ

A02 Receive Signal Level
A02 Input Resistance
A02 Allowed DC offset

Max

Units

-9

dBm

MOhms

-30

+30

AUTO ZERO CAPACITANCE
Capacitance = 0.015 IJoF
Tolerance = ±20%
Voltage Rating = 10V
Type = Non-Electrolytic, low leakage.

4-43

Test Condition

Hybrid Enabled
-2.5V- «
<>
~ ~ In

SDATA

vee
STR

TSYNC

CLKOUT

TX3

TX2

vss
Xl

AOl

<.J

....
::>
0

o '"
;;>1;;

"<.J
..J

TX2

AOl

vss
Xl

AVec

CLKSEL

AVec

..J

TXl

AGND

TXl

CLKSEL

TXO

RST

TXO

AGND

HYB

CLKOUT2

HYB

RST

AMP

CLKOUT2

A02

A22

AZl

Vee

'"'
«
0

"'-

'"'N
>" ' N
« «

68-Pin PLCC

...<>

...

..J
m

z 1,.
Q
o ...

III)

I':::f"

ci-liJi :l ~ liS

:J:
....
....
::> <>

0 :i
'"'~
0
III
en'"
0
en..J
..J ::>
> > 0 'x"' 0 m

...
III

~ I~

ADO

ADl

AGND

AD2

VREF

AD3

CDE

AD4

ADS

RST

AD6

SDATA

AD7

SCLK

ADS

TClO

AD9

TCLl

A010

S/i.

AOll

RTS

A012

CTS

A013

STR

4014

DTR

4015
CLKIN2

XTCLK

Figure 3. Device Packages

4-48

...<>

89C024FT

CALL ESTABLISHMENT,
TERMINATION AND RETRAIN
The 89C024FT modem system incorporates all protocols and functions required for automatic or manual call establishment. The modem system also
incorporates all protocols and functions required for
progress and termination of a data call.
The modem chip-set has a built-in auto-dialer, both
DTMF and Pulse type. It can detect dial, busy, and
ringback signals from the remote end, and will provide call progress messages to the user. The modem is also capable of re-dialing the last number
dialed.
The modem, when configured for auto-answer, will
answer an incoming call, remain silent for the two
second billing delay interval, and then transmit the
answer tones. Afterwards modem to modem identification and handshaking will proceed at a speed
and operating mode acceptable to both ends of the
link.
The data call can also be setup by manual dialing.
A transition from voice (Le., for the purpose of manual dialing) to data mode can be done by the use of
a mechanical switch (exclusion key) on the SH pin.
Once set to data mode, the modem handshaking
will proceed before the modems will be ready to accept and exchange data.
During data transmission, if one of the modems
finds that the received data is likely to have a high
bit error rate (indicated by a large mean square error
in the adaptive equalizer), it initiates a retrain sequence. This automatic retrain feature is only available at 2400 bps, and is compatible with CCITT V.22
bis recommendations.
Disconnection of the data call can be initiated by the
DTE at the local end or by the remote DTE (if the
modem is configured to accept it). Whether DTR will
initiate a disconnect depends on the last &D command. Receiving a long space from a remote modem will initiate a disconnect only after a Yl
command. The optional disconnect requests,

originated by the remote modem, are of two types,
(1) disconnect when receiving long-space, and (2)
disconnect when received carrier is dropped. The
modem chip-set can also be configured to transmit
"long-space" just before disconnection.
Because the CCITT and Bell modem connection
protocols do not provide recognition of remote modem type (Le., V.22 bis to 212A), the Intel chip-set
provides the additional capability of identifying the
remote modem type. This feature is beneficial during the migration phase of the technology from the
1200 bps to 2400 bps. In North America, where the
installed base of 1200 bps modems is mostly madeup of 212A type, this feature allows a "Data Base
Service Provider" to easily upgrade the existing
212A modems to 2400 bps V.22 bis standard, transparently, to 212A users. Similarly, a user with a
89C024FT based modem system can automatically
call data bases with either 212A or V.22 bis modems, without concern over the difference. This feature's benefits are realized in smooth upgrading of
data links, with minimum cost and reduced disruption in services. Refer to Table 1 for a detailed description of remote modem compatibility.

SOFTWARE CONFIGURATION
COMMANDS
This section lists the 89C024FT commands and
registers that may be used while configuring the modem. Commands instruct the modem to perform an
action, the value in the associated registers determine how the commands are performed, and the
result codes returned by the modem tell the user
about the execution of the commands.
The commands may be entered separately or in
string fashion. Any spaces within or between commands will be ignored by the modem. During the
entry of any command, the 'backspace' key (CNTRl
H) can be used to correct any error. Upper case or
lower case characters can be used in the commands. Commands described in the following paragraphs refer to asynchronous terminals using
ASCII codes.

4-49

89C024FT

Originating
89C024FT
Modem
Bell
CCID

Table 1 Remote Modem Compatibility
Answering Modem
Bell
Bell
CCITT
CCITT
300
1200
300
1200
300
1200
300
1200
2400

Answering
89C024FT
Modem
Bell
CCID

300
1200
300
1200
2400

300
1200'

300
1200

1200'
1200'

1200
1200

Bell
300

Bell
1200

300
300

1200
1200

300'
300'

1200
1200

300
-

300'
1200

1200
1200

1200
2400

Originating Modem
CCITT
CCITT
300
1200

300

CCITT
2400

1200
1200

1200
2400

• These connection data rates are obtained when connecting 89C024FT based modems end to end. The same results may
not be obtained when a 89C024FT based modem is connected to other modems.

V.42/42bis Feature Control Commands

Command Set
AT

A
A/

Bn
Ds
En
Hn
In
Ln
Mn
Nn

Qn
Sn=x
Sn?
Vn
Xn
Yn
Z

+++

&Cn
&Dn
&Fn
&Gn
&In
&Ln
&Mn
&Pn
&Rn
&Sn
&Tn
&Wn
&Xn
&Yn
&Zn

Attention code.
Go off-hook in answer mode
Repeat previous command string
BELLICCITT Protocol Compatibility
at 300 and 1200 bps
The dialing commands
(0-9 ABC D' # P R T S W , ; @)
Echo command (En)
Switch-Hook Control
If &J1 option is selected, H1 will also
switch the auxiliary relay
Request Product Code and Checksum
Speaker Volume
Monitor On/Off
Maximum Line (DCE) rate
On-Line
Result Codes
Write S Register
Read S Register
Enable Short-Form Result Codes
Enable Extended Result Code
Enable Long Space Disconnect
Fetch Configuration Profile
The Default Escape Code
DCD Options
DTR Options
Fetch Factory Configuration Profile
Guard Tone
Telephone Jack Selection
Leased/Dial-up Line Selection
Async/Sync Mode Selection
Make/Break Pulse Ratio
RTS/CTS Options
DSR Options
Test Commands
Write Configuration to Non
Volatile Memory
Sync Clock Source
Default NVRAM Profile Select
Store Telephone Number

L-~---'-~~~---=---~~~~~~~~----'4-50

-In
"Hn
"Nn
"On

V.42 Detection Phase Control
V.42bis Compression Control
V.42bis Dictionary Size
V.42bis Dictionary String Length
MNP Feature Control Command Set

\An
%An
\Bn
\Cn
\Gn
\In
\Kn
\Nn
\0
\Qn
\Tn
\U
Wn
\Xn
\Y

Maximum MNP Block Size
Set Auto-Reliable Fallback Character
Transmit Break
Set Auto-Reliable Buffer
Set Modem Port Flow Control
Bits per Second Rate Adjust
Set Break Control
Set Operating Mode
Originate Reliable Link
Set Serial Port Flow Control
Set Inactivity Timer
Accept Reliable Link
Modify Result Code Form
Set XON/XOFF Pass-Through
Switch to Reliable Mode
Switch to Normal Mode
Power Down Commands
Disable/Enable Power Down
Time to Power Down

89C024FT
Example:

CONFIGURATION REGISTERS

Terminal: AT &ZO
Modem: OK

The modem stores all the configuration information
in a set of registers. 80me registers are dedicated
to a special command and function, and others are
bit-mapped, with different commands sharing the
register space to store the command status.
80*
81
82
83
84
85
86
87
88
89
810
811 *
812
813
814*
815
816
817
818*
819
820
821.*
822*
823*
824
825*
826*
827*
831 *
837
8100

Result:

or by turning on DTR when in 8ynchronous Mode
2. Up to 33 symbols (dial digits and dial modifiers)
may be stored. 8paces and other delimiters are ignored and do not need to be included in the count.
If more than 33 symbols are supplied, the dial string
will be truncated to 33.

POWER MANAGEMENT
The flexible power management controls allow for a
variety of command and hardware driver options.
The power down sequence is initiated by placing a
logic "low" on pin 15 ~) of the 89C026FT. The
laptop can control th~D Signal directly. If such a
signal is unavailable, PD can be controlled by communications software via DTR. Lack of data activity
or an in-coming ring signal can also be used to control PD.
Placing the crystal on the 89C026FT (Figure 10)
allows it to reduce power consumption by turning off
the oscillator. When online and connected to a remote modem, the power consumption for the
89C024FT is typically 400 mW. Additionally, when
the 89027 is not needed (on-hook, not connected
to a remote modem) the 89C026FT places it in
stand-by. In standby the chip-set power consumption is typically 255 mW. When powered down via
the PD pin on the 89C026FT, the chip-set typically
consumes 5 mW. Minimum memory-system powerconsumption. can be achieved by chip selecting
memory only when addressed.

DIALING
Dial modifiers are available for adding conditions to
dialed phone numbers.
Dial Modifiers

8
W
!
@

Modem stores the Tone Dial (T) modifier
and phone number T16025551212 in the
external NVRAM.

Terminal: AT D80
Modem: T16025551212
Result:
Modem dials phone number and attempts to establish a connection.

NOTE:

Pulse Dial
Originate call in Answer Mode
Tone Dial
Dial a stored number
Wait for dial tone
Delay a dial sequence
Return to command state
Initiate a flash
Wait for quiet

T 1 (602) 555-1212

The number can be dialed from asynchronous mode
by issuing the following command:

Ring to Answer
Ring Count. (Read Only)
Escape Code Character
Carriage Return Character
Line Feed Character
Back 8pace Character
Wait for Dial Tone
Wait for Data Carrier
Pause Time for the Comma Dial
Modifier
Carrier Detect Response Time
Lost Carrier to Hang Up Delay
DTMF Tone Duration
Escape Code Guard Time
Not Used
Bit Mapped Option Register
Not Used
Modem Test Options
Not Used
Test Timer
Not Used
Not Used
Bit Mapped Options Register
Bit Mapped Options Register
Bit Mapped Options Register
Not Used
Delay to DTR (8ync Only)
RT8 to CT8 Delay (Half Dup.)
Bit Mapped Options Register
Bit Mapped Options Register
Maximum Line (DCE) Rate
Mean Error Monitor Register

* These S registers can be stored in the NVRAM.

P
R
T

APPLICATIONS OVERVIEW
The block diagram of a stand-alone 300 to 2400 bps
Hayes compatible modem is depicted in Figure 4.
The DAA section shown in this diagram may be implemented using the suggested diagram in Figure
5. Figure 6 shows the use of the power-down
feature.

4-51

89C024FT

POWER SUPPLY
DGNO

ill

+S VOLTS

AGND

X,
X2
89C026FT

HVB

89027

CLKOUT

PORT

TSYNC

SDAlA
selK
ClKIN2

SDAlA

TIP
AZ,
AZ2

ED
STR

SERIAL

AUDIO
MONITOR

-5 VOLTS

RING

.015,uF

A"P
AO,

TRXCAR

A02
TXO

seLK

TX'
TX2

CLKOUT2

TX3

RCVCAR
}TRANS"IT
LEVEL
SElECT

OH
Ail
SH

RING

"'C

Figure 4. Typical Laptop Modem

TIP

peoR

,.",
TIP

AR~------------------------------i---,

.-+------+_

R'NG

AUXILIARY

BUSINESS
PHONE

.... "'C

Figure 5. Typical Telephone Line Interface Using Internal Hybrid
POWER DOWN ---------<0

/DTR~
/R'

TXD
RXD

1.0 P

'T
DGNO

Figure 6. Power-Down Control
4-52

89C024FT

SYSTEM COMPATIBILITY SPECIFICATIONS
Parameter
Synchronous
Asynchronous
Asynchronous Speed Range

Specification
2400 bps ± 0.Q1 %
1200 bps ±0.01 %

V.22 bis
V.22 and BELL 212A

2400, 1200 bps, character asynchronous.

o - 300 bps anisochronous.
+ 1 % - 2.5% default. Extended + 2.3%

- 2.5% range of CCITT
standards optional via software customization.

Asynchronous Format

10 bits, including start, stop, parity. (8, 9, 11 bits optional via S/W
customization.)

Synchronous Timing Source

a) Internal, derived from the local oscillator.
b) External, provided by DTE through XTCLK.
c) Slave, derived from the received clock.

Telephone Line Interface

Two wire full duplex over public switched network or 4 wire
leased lines.
On-chip hybrid and billing delay timers.

Modulation

V.22 bis, 16 point QAM at 600 baud.
V.22 and 212A, 4 point PSK at 600 baud.
V.21 and 103, binary phase coherent FSK

Output Spectral Shaping

Square root of 75% raised cosine, QAM/PSK.

Transmit Carrier Frequencies
V.22 bis, V.22, 212A
V.21

Bell 103 mode

Received Signal Frequency Tolerance
V.22 bis, V.22, 212A
V.21

Bell 103

Originate
Answer
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'

1200 Hz
2400 Hz
1180 Hz
980 Hz
1850 Hz
1650 Hz
1070 Hz
1270 Hz
2020 Hz
2225 Hz

±
±
±
±
±
±
±
±
±
±

.02%
.02%
.02%
.02%
.02%
.02%
.02%
.02%
.02%
.02%

Originate
Answer
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'
Originate 'space'
Originate 'mark'
Answer 'space'
Answer 'mark'

2400 Hz
1200 Hz
1850 Hz
1650 Hz
1180Hz
980 Hz
2020 Hz
2225 Hz
1070 Hz
1270 Hz

±
±
±
±
±
±
±
±
±
±

7 Hz
7Hz
12 Hz
12 Hz
12Hz
12 Hz
12 Hz
12 Hz
12 Hz
12 Hz

Typical Energy Detect Sensitivity

Greater than -43 dBm ED is ON. Less than -48 dBm ED is
OFF. Signal fn dBm measured at A02.

Energy Detect Hysteresis

A minimum Hysteresis of 2 dB for QAM scrambled mark.

Line Equalization

Fixed compromise equalization, transmit.
Adaptive equalizer for PSK/QAM, receive.

Diagnostics Available

Local analog loopback.
Local digital loopback.
Remote digital loopback.

Self Test Pattern Generator

Alternate 'ones' and 'zeros' and error detector, to be used along
with most loopbacks.
A number indicating the bit errors detected is sent to DTE.

4-53

89C024FT

RECEIVER PERFORMANCE SPECIFICATIONS
Typical SNR for
10- 5 BER Performance

Test Cases
Data
Mode

RxLevel
(dBm)

Answer
(dB)

Originate
(dB)
16.5'

V.22 bis
Synchronous

-30

-40

16.5

V.22/BeIl212A
Synchronous

-30

6.5

-40

6.5

V.21
Asynchronous

-30

7.5

-40

Bell 103
Asynchronous

-30

11.5

-40

11.5

Test Conditions:
-

Receive Signal (Rx) measured at A02 (transmit level set at - 9 dBm)

Unconditioned 3002 Line

3 KHz Flat-Band Noise

PERFORMANCE SPECIFICATIONS
Parameter

Min

Typ

Max

4.0

DTMF Level

dBm
-35

DTMF Second Harmonic
DTMF Twist (Balance)

Units
dB

Comments
atA01
HYB enabled into 600n

3
100

Software Controlled

Pulse Dialing Rate

10/20

pps

SoftWare Controlled

Pulse Dialing Make/Break

39/61
33/67

%
%

Default DTMF Duration

Pulse Interdigit Interval

785

ms
2.1

Billing Delay Interval

sec

540
-3

Hz
dB

1800
-6

Hz
dB

Dial Tone Detect Duration

3.0

sec

Ringback Tone Detect
Duration
Cadence

0.75
1.5

s~c

Guard Tone Frequency
Amplitude

Frequency
Amplitude

Busy Tone Detect
Duration
Cadence

US
UK, Hong KonJl

referenced to High
Channel transmit.
QAM/PSK Modes Only

Off/On Ratio

0.2

sec

0.67

1.5

4·54

Off/On Ratio

89C024FT

amplitude samples. During 1200 and 2400 BPS operation, DPSK and QAM is used to send 2 to 4 bits
of information respectively at 600 baud to the AFE.
Because the QAM coding technique is an inherently
synchronous transmission mechanism, in the case
of asynchronous QAM transmission, the asynchronous data is synchronized by adding or deleting stop
bits. Following the synchronization process, the
89C026FT transmits digitized phase and amplitude
samples to 89027 over the high speed serial link.

89C026FT OVERVIEW
The 89C026FT processor performs data manipulation, signal processing and user interface functions. It requires a single 64K x 8 ROM and 32K x
8 RAM to execute standard, and/or custom code to
perform the V.42/42bis and MNP4/5 protocol functions. The ROM and RAM addresses overlap in external memory and are decoded using the INST and
AD15 signals. A block diagram of the 89C026FT is
provided in Figure 7.

In the receive operation, the information is received
by the 89C026FT from the 89027 as two signals
which are 90 degrees phase shifted from each other.
These analog signals are then digitized by the AID
converter resident on the 89C026FT. By using DSP
algorithms, the received signals are processed us. ing adaptive equalization for telephone line delay,
amplitude distortion and gain adjustments and the
signal demodulated. Following demodulation, the
data is unscrambled, and if necessary, returned to
asynchronous format.

89C026FT contains a TTL compatible serial link to
DTE equipment, along with a full complement of
V.24/RS-232-C control signals. A UART or USART
may be used to transfer data to and from a microcomputer bus. The 89C026FT supports the industry
standard AT command set facilitating compatibility
with most PC software.
During transmit operation, the 89C026FT synthesizes DTM F tones and the 300 BPS FSK modem signal and transmits them to the 89027 as digitized

~---------------------------------------f--~------- ------1

I
Q

COMMAND INTERPRETER

I
I

RXD(103)
TDX(104)
TCLK(114)
RCLK(115)
XTCLK(113)

AUTO BAUD-RATE/
DATA FORMAT
DETECTOR

-+-+
--'--+

RTS~ oiQ

CTS
DTR ---'--+
DSR
I
REMLB(140)'-;"""'"
LCLLB( 141) ---'--+

L~fri~~~K 1 + - - - - - - - - ,
DETECT

'" 0
~ ~

DATA

---'--+
~ ~~
--.---+- "'"

S/A ---'--+

P5~

RETRAIN

~!!!
Ii: [;3
!z ~
w~

DCD
TCLO
TCLl
CON riG

DATA

Z '"

G!z
oS

TSYNC
SCLK
SDATA

SB~

~ ---T-+
D/S--+
I
I
I

DATA

I
I

~--l---r-l--l---r--l----r--·l------------------------- ---!
RST

CDE

Vee VSS1

VSS2

AGND

Vpp

Figure 7. 89C026FT Block Diagram

4-55

89C024FT

89C026FT PINOUT
Symbol

Function (89C026FT)

Direction!")

Pin No.

ClKIN
ClKIN2
RST

12.96 MHz master clock from 89027
270 KHz from 89027
Chip reset (active low)

In
In
In.

.67
44
16

I
Q
STR
ED

In-phase received signal
Quadrature-phase received signal
Symbol Timing from 89027
Energy Defect input

In
In
In
In

11
10
24
9

TSYNC
SDATA
SClK

Transmitter sync pulse to 89027
Serial Data to 89027
Serial Clock to 89027

Out
Out
Out

35
17
18

OH
SH
RI
AR

Off-Hook control to DAA
Switch-Hook from dataphone
Ring Indicator from DAA
Aux Relay control to DAA

Out
In
In
Out

33
5
42
38

TCl1
TClO
PO

1/0

DIS
CONFIG

NVRAM Data I/O
NVRAM ClK
Power-down control
NVRAM CE
DumblSmart mode select
Reserved for future use (Veel (2)

Out
In
·Out
In
In

20
19
15
21
6
8

Test Mode Indicator

Out

TXD
RXD
RTS
CTS
DSR
DCD
DTR
RClK
TClK
XTClK
SI
REMlB
lCllB

Transmitted data from DTE
Received data to DTE
Request to send from DTE
Clear to Send to DTE
Data Set Ready to DTE
Data Carrier Detect to DTE
Data Terminal Ready from DTE
Received clock to DTE
Transmit clock to DTE
External timing clock from DTE
Speed indicator to DTE
Remote loopback Command from DTE
local loopback Command from DTE

In
Out
In
Out
Out
Out
In
Out
Out
In
Out
In
In

27
29
22
23
30
31
25
34
28
26
32
7
4

Vee
CDE
V REF
VSS1
VSS2
AGND
Vpp

Positive power supply ( + 5V)
Clock detect enable (Vss)(1)
AID converter reference
Digital ground
Digital ground
Analog ground
Timing pin for return from power-down

+5V
GND
+5V
GND
GND
AGND
In

1
14
13
36
68
12
37

EA
ADO-AD15
AA
JS
CD
MR
REl
COMP
ERR
lAPM

External Memory enable
External memory access address/date(3)
Auto Answer(3)
Jack Select(3)
Carrier Detect Indicator(3)
Modem Ready Indicator(3)
MNP Reliable Link Active(3)
Compression Active V.42bis or MNP 5(3)
Error detected by lAPM or MNP(3)
lAPM Reliable Link Active(3)

s/li.

4-56

In
1/0

Out
Out
Out
Out
Out
Out
Out
Out

2
60-45
60
59
58
57
56
55
54
53

89C024FT

89C026FT PINOUT (Continued)
Symbol
NMI
X2

CLKOUT
BUSWIOTH
INST
ALE
RO
READY
BHE
WR

Oirection(4)

Function (89C026FT)
Non-maskable interrupt(V55)(1)
Crystal output
Clk output
Bus Width
External memory instruction fetch
Address latch enable
External memory read
External memory ready
External memory bus high enable
External memory write

In
Out
Out
In
Out
Out
Out
In
Out
Out

Pin No.
3
66
65
64
63
62
61
43
41
40

NOTES:
1. Pins marked with (Vssl must be corrected to Vss.
2. Pins marked with (Vecl must be connected to Vee.
3. ADO-AD3 are used as AA, JS, CD, MR, REL, COMP, ERR, and LAPM respectively.
4. Pins with direction "IN" must not be left floating.

89C026FT PIN DESCRIPTION

XTCLK
Transmitter timing from OTE, when external clock
option is selected.
TXO
The serial data from OTE to be transmitted on the
line. A logic 'high' is mark. In synchronous mode,
89C026FT samples this data on the rising edges of
TCLK.

TCLK
Clock output from 89C026FT as timing source for
data exchange from OTE to modem. Serial data is
read on the rising edges of the TCLK. This output is
High in asynchronous mode.

RXO
The serial data to OTE. A logic 'high' is mark. In
synchronous mode, the rising edge of RCLK occurs
in the middle of RXO.

RCLK
Synchronous clock output. Rising edge of RCLK occurs in the middle of each RXO bit. This pin remains
High in asynchronous mode.
PO
Power-down control. A Iowan this input pin, in conjunction with the + En and + Tn commands, will
cause the modem to go into a power-down mode.

Vpp
Timing pin for return from power-down. Connect a
1.0 f.Lf capacitor between Vpp and VS5 if the power-

down option is used. This capacitor causes an internal timing circuit to give the oscillator time to stabilize before turning on internal clocks. This pin may
be left floating or connected through a 1.0 f.LF capacitor to VS5 if power-down mode is not required.
TM
A low indicates maintenance conditiQn in the
modem.
OCO
In async operation, OeD remains low regardless of
data carrier (default), or it can be programmed to
indicate received carrier signal is within the required
timing and amplitude limits. In sync operation low
indicates the received carrier Signal is within the
required timing and amplitude limits.
OSR
A low indicates modem is off-hook, is in data transmission mode, and the answer tone is being exchanged. CTS low indicates modem is prepared to
accept data.
RTS
In async modeRTS i~ored. Under command
control, in sync mode RTS can be ignored, or the
modem can respond with a Low on CTS.

OTR
&00 command will cause the modem to ignore OTR.
For &01 the modem assumes the asynchronous
command state on a low-to-high transition of the
OTR circuit. The &02 command does the same as
&01 except the state of OTR will enable/disable
auto answer. A low-to-high transition of OTR after
the &03 command will cause the modem to assume
the initialization state.
4-57

89C024FT
TCl1, TClO

ERR

These pins are used as the serial clock and data for
interface to an NVRAM. Refer to Figure 3. TCLO is
used to output a clock and serial data is transferred
in on TCL1.

Goes low for 1 second whenever a reliable connection detects an error.

AR
This Auxiliary relay control is for switching a relay
for voice or data calls. High is voice, low is data.
RI
A low signal from DAA indicates line ringing. This
input is ignored when the modem is configured for
leased line. This signal should follow the ring
cadence.

OH
Low sets an off hook condition, high indicates an on
hook. When dialing, this signal is used to pulse dial
the line.

Sf
Selects one of the two data rates or ranges of rates
in the DTE to correspond to the rate in modem. Low
selects the higher rate (2400 CCITT/1200 BELL) or
range of rates. High selects the Low rate or range
of rates.

DIS
A low on this pin will indicate the smart mode which
will respond to all commands. A High will ignore all
commands.

VREF
Voltage reference for the analog to digital converter
should be connected to the 89027 AVcc '

CDE
SH

This pin must be connected to Vss.

Used as a telephone voice to data switch or vice
versa. Any logic level transition will toggle the modem state between voice and data.

SiA

AA
Used as an indicator for Auto Answer status and·
Ring indicator. Active low.

lCllB
A low will set the modem in the local analog loopback test mode. Logic Low levels applied simultaneously to REMLB and LCLLB pins, sets the modem
to the local digital loopback.

REMlB
A low on this pin initiates a remote loopback
condition.

CD
A low indicates the presence of carrier signal on the
line.

MR
A low indicates the presence of the DSR signal. Toggling indicates that a test mode is active.
.

REl
A low indicates that an MNP reliable link has been
established.

The function of this pin is re-defined as external
NVRAM CEo
CON FIG
Reserved for future use. This signal should be
pulled high.

EA
When high, memory access from address 2000H to
4000H are directed to on-chip ROM. When low, all
Memory access is directed to off-chip memory. This
pin must be tied high.
JS
Low is used to pulse A and A 1 leads to control a
1A2 Key System jack.
BUSWIDTH
When high, external memory accesses are 16 bits
wide. When low, external memory accesses are 8
bits wide. This pin must be tied low.

READY
When high, no wait states are inserted in external
memory accesses. When low, one wait state is inserted in each external memory access.
INST

Output high during an external memory read indicates the read is an instruction fetch. INST is actiA low indicates that data compression is in operavated only during external memory accesses and
tion (V.42bis or MNP Class 5).
output low for data fetch. INST along with AD15 are
lAPM
used to decode the overlapping external ROM and
A low indicates that a LAPM reliable link has been
RAM.
established.
4-58

89C024FT

• Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

89C026FT ABSOLUTE MAXIMUM
RATINGS·
Temperature Under Bias ......... O°C to

+ 70°C

Storage Temperature ........ - 40°C to + 125°C
Voltage from Any Pin to
Vss or AGND ................ - 0.5V to

+ 7.0V

Average Output Current from Any Pin ..... 10 mA

NOTICE Specifications contained within the
following tables are subject to change.

Power Dissipation ................... 1.5 Watts

OPERATING CONDITIONS
Symbol

Parameter

Min

Ambient Temperature Under Bias

Vee

Digital Supply Voltage

VREF

Analog Supply Voltage

fose

ClKIN Frequency

Max

Units

+70

°C

4.75

5.25

4.75

5.25

12.95870

12.96130

MHz

NOTE:

The AGND and Vss on both the 89C026FT and the 89027 must be nominally at the same potential.

D.C. CHARACTERISTICS
Symbol

Parameter

Typ(7)

Min

Max

Units

+0.8

0.2 Vee + 0.9

Vee + 0.5

0.7 Vee

Vee + 0.5

2.2

Vee + 0.5

0.3
0.45
1.5

V
V
V

IOL = 200/LA
IOL = 3.2 mA
IOL = 7 mA

V
V

IOH = - 200 /LA
IOH = -3.2mA
IOH = -7mA

V
V
V

IOH = -10 /LA
IOH = -30/LA
IOH = -60/LA

-0.5

Test Conditions

VIL

Input low Voltage

VIH

Input High Voltage(1)

VIH1

Input High Voltage on ClKIN

VIH2

Input High Voltage on RESET

VOL

Output low Voltage

VOH

Output High Voltage(4)

Vee - 0.3
Vee - 0.7
Vee- 1.5

VOH1

Output High Voltage(3)

Vee - 0.3
Vce - 0.7
Vee - 1.5

III

Input leakage Current(5)

±10

/LA

ILl1

Input leakage Current(6)

±3

/LA

0< VIN < VREF

IlL

logical 0 Input Current(3)

-50

/LA

VIN = 0.45V

IIL1

logical 0 Input Current
in RESET(2) (ALE, RD,
WR, SHE, INST,SClK)

-850

/LA

VIN = 0.45V

4-59

VIN < Vee - 0.3V

89C024FT

D.C. CHARACTERISTICS (Continued)
Symbol

Parameter

Min

Typ(7)

IREF

AID Converter
Reference Current

2·

lee1

Active Mode Current
(Typical)

RRST

RESET Pullup Resistor

Pin Capacitance
(Any Pin to VSS)

IpD

Power-Down Mode Current

Max

Units

Test Conditions

CLKIN = 12.96 MHz
Vee = Vpp = VREF = 5.25

CLKIN

50K

frEST

p.A

Vee

12.96 MHz

1.0 MHz

Vpp

VREF

5.25

NOTES:
(Notes apply to all specifications)
1. All pins except RESET and CLKIN.
. 2. Holding these p~s belo~ in RESET 1'11§' cause the part to enter test modes.
3. TCLO, TCL1, S/A, RTS, CTS, DSR, DCD, SI, OH.
4. BHE, INST, CLKOUT, RESET, TCLK, RXD, RCLK, TSYNC, TM, SCLK, SDATA. The VOH specification is not valid for
RESET.
5. CDE, EA, READY, BUSWIDTH, NMI, STR, DTR, XTCLK, TXD, B/C; CLKIN2, and RI.
6. SID, SH, REMLB, LCLLB, I, Q, CONFIG, ED.
7. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature
and VREF = Vee = SV.

A.C. CHARACTERISTICS (Over specified operating conditions)
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall times

10 ns, fosc 12.96 MHz

This system must meet these specifications to work with 89C026FT:
Symbol

Parameter

Min

Max

Units

TAVYV

Address Valid to HEADY Setup.

2Tose -65

TLLYV

ALE Low to READY Setup

Tosc - 72

TYLYH

Non READY Time

TeLYX

READY Hold after CLKOUT Low

TLLYX

READY Hold after ALE Low

TAVGV

Address Valid to Buswidth Stlltup

hLGV

ALE Low to Buswidth Setup

TCLGX

Buswidth Hold after CLKOUT Low

TAVDV

Address Valid to Input Data Valid

No Upper Limit

Notes

Tose - 30

(Note 1)

TOSC - 15

2 Tose - 40

(Note 1)

2 Tose - 65

Tose - 70

ns
3TOsc-67

TRLDV

RDActive to Input Data Valid

Tose - 23

TeLDv

CLKOUT Low to Input Data Valid

Tose - 50

TRHDZ

End of RD to Input Data Float

Tose - 20

TRXDX

Data Hold after RD Inactive

NOTE:
1. If max is exceeded, additional wait states will occur.

4-60

89C024FT

A.C. CHARACTERISTICS (Continued)
Test Conditions: Capacitive load on all pins = 100 pF, Rise and fall tines = 10 ns, fosc 12.96 MHz
The 89C026FT will meet these specifications:
Symbol

Parameter

FCLKIN

Oscillator Frequency

Tosc

Oscillator Period

TXHCH

FCLKIN High to CLKOUT High or Low

Min

Max

Units

12.95870

12.96130

MHz

1/FCLKIN{MAX)

1/FCLKIN{MIN)

110

TCLCL

CLKOUT Cycle Time

TCHCL

CLKOUT High Period

TCLLH

CLKOUT Falling Edge to ALE Rising

-5

TLLCH

ALE Falling Edge to CLKOUT Rising

-15

TLHLH

ALE Cycle Time

TLHLL

ALE High Period

Tosc - 10

ToSC

4 Tosc
Tosc

TAVLL

Address Setup to ALE Falling Edge

Tosc - 20

TLLAX

Address Hold after ALE Falling Edge

Tosc - 40

TLLRL

ALE Falling Edge to RD Falling Edge

Tosc - 40

TRLCL

RD Low to CLKOUT Falling Edge

TRLRH

RD Low Period

TRHLH

RD Rising Edge to ALE Rising Edge

TRLAZ

RD Low to Address Float

TLLWL

ALE Falling Edge to WR Falling Edge

TCLWL

CLKOUT Low to WR Falling Edge

TOVWH

Data Stable to WR RiSing Edge

TCHWH

CLKOUT High to WR Rising Edge

TWLWH

WR Low Period

ns
30

Tosc - 5

Tosc

+ 25
+ 25

-10

ns
ns

Tosc

TWHOX

Data Hold after WR Rising Edge

Tosc - 10

TWHLH

WR RiSing Edge to ALE Rising Edge

Tosc - 10

TWHBX

SHE, INST, Hold after WR Rising Edge

Tosc - 10

TRHBX

SHE, INST, Hold after RD Rising Edge

Tosc - 10

TWHAX

AD8-15 Hold after WR Rising Edge

Tosc - 50

TRHAX

AD8-15 Hold after RD Rising Edge

Tosc - 25

NOTES:
1. Typical specifications, not guaranteed.
2. Assuming back-to-back bus cycles.

4-61

(Note 2)

ns
25

Tosc - 23

Tosc - 30

Tosc - 10
0

(Note 1)

2 Tosc
Tosc - 10

Notes

ns
ns

(Note 2)

""_I®
11I'eI

89C024FT

WAVEFORMS

CLKIN

CLKOUT

ALE

--o+-- tLLRL --+--

~VLL - ' i - -

BUS

ADDRESS OUT
I ~VDV
i-=-=.tLLWL

BUS

--<

ADDRESS OUT

ADDRESS

-~----'

"""'I

BHE,INST

VALID

AD8-1S.

ADDRESS OUT

CLKIN

CLKOUT

ALE

READY

tAVYv

__P-____~_V_G_Vt:::1
BUS WIDTH

BUS

--<

'!.

tLLGV

ADDRESS OUT

t::""""'~(;'''';';''"'...,

(

)

DATA

>)}

_______________________r-

Figure 8. Bus Signal Timings

4-62

89C024FT

guard tone, smoothed by a low pass filter, and transmitted to the line. Prior to transmitting either FSK or
QAM signals to the telephone line, the 89027
adjusts the signal gain through an on-board
programmable gain amplifier.

89027 OVERVIEW
The 89027 is a 28 pin CHMOS analog front end
device, which performs most of the complex filtering
functions required in modem transmitters and receivers. A general block diagram of this chip is provided in Figure 9. Most of the analog Signal
processing functions in this chip are implemented
with CHMOS switched capacitor technology. The
89027 functions are controlled by 89C026FT,
through a high speed serial data link.

During the receive operation, the received FSK and
QAM signals are passed through anti-alias filters,
bandsplit filters, automatic gain control and carrier
detect circuits, a Hilbert transform filter, and the output sent to the 89C026FT processor as analog
signals.

During FSK transmit operation, the 89027 receives
digitally synthesized mark and space sinusoid amplitude information from the 89C026FT. The 89027
converts the signal to its analog equivalents, filters
it, and transmits it to the telephone line. For QAM
transmission, the signal constellation points are
transferred to the 89027. This information is modulated into an analog signal, passed through spectral shaping filters, combined with the necessary

Other functions provided by the 89027 are: an onboard two wire to four wire circuit with disable capability, an audio monitor output with software configurable gain, and a programmable gain transmit
signal.
The 89027 is available in 28 pin plastic DIP and
PLCC packages.

p-----------------------------------------------------------------

r-----------;------~AMP

Xl
X2
~A02

+!-HYB

t-----.+

.-r- -l---T---T--l- -- T--- --- -Vee

VBB

AGND

Vss

RST

AVee

AZ2

AZI

Figure 9. 89027 Block Diagram

4-63

OUTPUT LEVEL
TX3-TXO

AOI

89C024FT

89027 PINOUT
Direction

Pin No.

+5V
-5V
DGND
AGND
+5

28
15
24
21
7

Xtal Oscillator
Xtal Oscillator
12.96 MHz Clock Output to 89C026FT
270 KHz Clock Output to 89C026FT

In
Out
Out
Out

23
25
26
19

RST
HYB
AZl
AZ2

Chip reset (active low)(3)
Enable on-chip hybrid(1)
Auto-zero capacitor
Auto-zero capacitor

In
In
Out
In

20
10
16
17

SDATA
SCLK
TSYNC

Serial data from 89C026FT
Serial clock from 89C026FT
Transmitter sync from 89C026FT

In
In
In

2
1
3

STR
ED
I
Q

Symbol timing to 89C026FT
Receiver energy detect to 89C026FT
In phase received signal to 89C026FT
Quadrature-phase received Signal to 89C026FT

Out
Out
Out
Out

27
18
13
14

AOl
A02
AMP

Transmitter output
Receiver input
Output to monitor speaker

Out
In
Out

6
12

TXO
TXl
TX2
TX3

Transmitter level
Transmitter level
Transmitter level
Transmitter level

In
In
In
In

9
8
5
4

(Note 2)

Symbol

Function (89027)

VCC
VBB
Vss
AGND
AVcc

Positive Power Supply (Digital)
Negative Power Supply
Digital Ground
Analog Ground
Positive Power Supply (Analog)

Xl
X2
CLKOUT
CLKOUT2

control (LSB)(1)
control(1)
control(1)
control (MSB)(1)

NOTE:

1. When held high, these pins must be connected through 10K resistors to Vee.
2. Reserved Pin. Must be left No Connect.
, 3. Connect to reset circuitry through a 10K resistor.

89027 Pinout Description

AOl
Transmitter output.

TXO·3

These four pins control the transmitted signal level.
Refer to Transmit Level Table.

A02
Receiver input.

HYB
This pin enables the on-chip hybrid. A line impedance matching network must be connected between
AOl and A02 when HYB is enabled. If HYB is disabled and an external 4W 12W hybrid is used, the
hybrid receive path must be amplified by 6 dB.

AMP
This output can be used to monitor the call progress
tones and operation of the line.

4-64

89C024FT

ABSOLUTE MAXIMUM RATINGS(2)
Temperature Under Bias ............. 0 to + 700 C
Storage Temperature ............ - 40 to + 1250 C
All Input and Output Voltages
with Respect to Vss .......... -0.3V to + 13.0V
All Input and Output Voltages
with Respect to Vee & AVee ..... -13.0V to 0.3V
Power Dissipation ........................ 1.35W
Voltage with Respect
to VSS(1) ....................... -0.3V to 6.5V

OPERATING CONDITIONS
Parameter

Symbol

Ambient Temperature Under Bias

TA
Vee
Vss

Digital Supply Voltage
Analog Supply Voltage

Min

Max

Units

+70

4.75

5.25

-4.75

-5.25

POWER DISSIPATION Ambient Temp = 0 to 70 C, Vee = AVee = 5 ± 5%, Vss = AGND = OV.
Typical values shown are for T A = 25 C and nominal power supplies.
0

Symbol

Parameter

Min

Cu~rent

Typ

Max

Units

AlcC1

AVee Operating

rnA

ICC1

Vee Operating Current

rnA

Ibb1

Vss Operating Current

-15

-21

rnA

Alccs

AVee Standby Current

0.2

rnA

Iccs

Vee Standby Current

rnA

-2

rnA

Ibbs

Vss Standby Current

-0.6

Alccp

AVee Power-Down Current

100

/LA

Iccp

Vee Power-Down Current

450

/LA

Ibbp

Vss Power-Down Current

450

Pdo

Operating Power Dissipation

175

250

Pds

Standby Power Dissipation

Pdp

Power Down Power Dissipation

4-65

/LA

89C024FT

D.C.

CHARA~TERISTICS (TA = O°C to 70°C, AVee = Vee = SV ± S%, Vee = SV ± S%, AGND =

Vss = OV).
Inputs: TXO, TX1, TX2, TX3, HYB, RST
Outputs: CLKOUT

Symbol

Parameter

Min

Max

Units

Test Conditions

iii

Input Leakage Current

-10

+10

p.A

VSS ~ Vin ~ Vee

Vii

Input Low Voltage

Vss

0.8

2.0

Vee

0.4

V
V

loh

0.4

Load Capacitance

Vih

Input High Voltage

Vol

Output Low Voltage

Voh

Output High Voltage

Vcol

CLKOUT Low Voltage

Vcoh

CLKOUT High Voltage

A.C. CHARACTERISTICS

2.4

0.7 Vee

2S0C, Vee

Min

Typ

(TA

AVee

SV, vss

101

AGND

-1.SmA,1 TTLioad
SOp.a, 1 TTL load

OV, vee

=
=

SO pF
SO pF

-SV)

ANALOGINPUTS:A02
Parameter
A02 Receive Signal Level
A02 Input Resistance
A02 Allowed DC offset

Max

Units

-9

dBm

MOhms

-30

+30

AUTO ZERO CAPACITANCE
Capacitance = 0.01S p.F
Tolerance = ±20%
Voltage Rating = 10V
Type = Non-Electrolytic, low leakage.

4-SS

Test Condition
Hybrid Enabled
-2.SV

invoke IPPS
initialize file format
filename resulting from linking
logical unit is byte
input file is in words (2 bytes)
output file is in bytes
low order bytes to one file
high order bytes to another
press "enter" to exit formatting
the following assumes that an
INTEL PiUP 20lA programmer is
connected to the PC

TYPE
27128
COPY 32ATR.LO TO PROM
COPY 32ATR.HI TO PROM
EX

display available EPROM types
specify EPROM type
insert blank EPROM into programmer
copy low byte file to prom
insert blank EPROM into programmer
copy low byte file to prom
exit IPPS

Custom routines can now be tested by placing EPROMS into target hardware.

REFERENCES
1. "FSK Modems: TCM3105 Designers Information" from Telecommunications Circuits Data Book, 1986. By

Texas Instruments.
2. MEKII 89024 Enhanced Modem Evaluation Kit Users Manual, 1987. By Intel Corp.
3. 89024 Modem Reference Manual, 1987. By Intel Corp.
4. Developing MCS-96 Applications Using the SBE-96. Application Note AP-273 (Order Number 280249-001). By
Intel Corp.

4-85

PCM Codec /Filter
andCombo

2910A
PCM COOEC - /LLA W
8-BIT COMPANDED AID AND 01 A CONVERTER

•
•

78dB Dynamic Range, with Resolution
• Equivalent
to 12-Bit Linear Conversion

Per Channel, Single Chip Codec
CCITT G711 and G712 Compatible, ATT
T1 Compatible with 8th Bit Signaling

Around Zero
On-Chip Voltage Reference
• Precision
Low Power Consumption 230 mW Typ.
• Standby Power 33mW Typ.

Microcomputer Interface with On-Chip
• Timeslot
Computation

•

Simple Direct Mode Interface When
Fixed Timeslots are Used

•

±5% Power Supplies: + 12V, +5V, -5V

•

Fabricated with Reliable N-Channel
MOS Process

The Intel 2910A is a fully integrated PCM (Pulse Code Modulation) Codec (Coder-Decoder), fabricated with
N-channel silicon gate technology. The high density of integration allows the sample and hold circuits, the
digital-to-analog converter, the comparator and the successive approximation register to be integrated on the
same chip, along with the logic necessary to interface a full duplex PCM link and provide in-band signaling.
The primary applications are in telephone systems:
• Transmission

-T1 Carrier

• Switching

-Digital PBX's and Central Office Switching Systems

• Concentration

-Subscriber Carrier/Concentrators

The wide dynamic range of the 2910A (78dB) and the minimal conversion time (80JLsec minimum) make it an
ideal product for other applications, like:
• Date Acquisition

• Telemetry

• Secure Communications Systems

• Signal Processing Systems

@SIGX_-t_ _ _ _ _ _ _T_R_AN_SM_IT_SE_C_T_'o_N-,AID

o
V'x - - J - - - l
@)AUTO
SAMPLE
CD CAP 'x
0 CAP2 x - - t - - - - i

r--L-----1

H:lD I - - - - - - - i

AP~~~~~~~~~ON
REGISTER

_-+-_

TS x

%'
~:V

~Kx ~
'Sx

Vee
TS x

V'R

GAOO

006785-1

r--'-I~~-De

I---t-- ClKc ®
L-r_J--1'--- PDN ®

r . . . . I~-I--DR
®
1---t_-ClKR@
I---t-- 'SR @

~GR_-+---------------~

----f-C

PINMJM8ER

GRDA

GRDD

CAP

lx. CAP 2x

Holding Capacitor

VFx

Analog Input

VFA

Analog Output

DA,De,SIGx

Digital Input

SIGA, Ox, TSx

Digital Output

ClKc, elKx, ClKA Clock Input
FSx, FSA

006785-2

Figure 1. Block Diagram

Figure 2. Pin
Configuration

Frame Sync Input

AUTO

Auto Zero Output

VBS

Power (-5V)

Vee

Power (+5V)

VDD

Power (+ 12V)

PDN

Power Down

GRDA

Analog Ground

GRDD

Digital Ground

No Connect

Figure 3. Pin Names

5-1

November 1986
Order Number: 006785-002

inter

2910A

Pin Description
Pin No.

Symbol

Function

Description

Hold

Connections for the transmit holding capacitor. Refer to
Applications section.

CAP1x

CAP2x

VFx

Input

Analog input to be encoded·into a PCM word. The signal on this
lead is sampled at the same rate as the transmit frame
synchronization pulse FSx, and the sample value is held in the
external capacitor connected to the CAP1 x and CAP2x leads
until the encoding process is completed.

AUTO

Output

Most significant bit of the encoded PCM word ( + 5V for negative,
- 5V for positive inputs). Refer to the Codec Applications
section.

GRDA

Ground

Analog return common to the transmit and receive analog
circuits. Not connected to GRDD internally.

SIGR

Output

Signaling output. SIGR is updated with the 8th bit of the receive
PCM word on signaling frames, and is latched between two
signaling frames. TTL interface.

VDD

Power

+ 12V ± 5%; referenced to GRDA.

Input

Receive PCM highway (serial bus) interface. The Codec serially
receives a PCM word (8 bits) through this lead at the proper time
defined by FSR, CLKR, De, and CLKe.

PDN

Output

Active high when Codec is in the power down state. Open drain
output.

VFR

Output

Analog output. The voltage present on VFR is the decoded value
of the PCM word received on lead DR. This value is held
constant between two conversions.

No
Connects

Recommended practice is to strap these NC's to GRDA.

GRDD.

Ground

Ground return common to the logic power supply, Vee.

Output

Output of the transmit side onto the send PCM highway (serial
bus). The 8-bit PCM word is serially sent out on this pin at the
proper time defined by FSx, CLKx, De, and CLKe. TTL threestate output.

TSx

Output

Normally high, this signal goes low while the Codec is
transmitting an 8-bit PCM word on the Ox lead. (Timeslot
information used for diagnostic purposes and also to gate the
data on the Ox lead.) Open drain output.

Vee

Power

+ 5V ± 5%, referenced to GRDD.

CLKR

Input

Master receive clock. defining the bit rate on the receive PCM
highway. Typically 1.544 Mbps for a T1 carrier system. Maximum
rate 2.1 Mbps. 50% duty cycle. TTL interface.

FSR

Input

Frame synchronization pulse for the receive PCM highway.
Resets theon-chip timeslot counter for the receive side.
Maximum repetition rate 12 KHz. Also used to differentiate
between non-signaling frames and signaling frames on the
receive side. TTL interface.
5-2

inter

2910A

Pin Description (Continued)
Pin No.

Symbol

Function

CLKx

Input

Master transmit clock defining the bit rate on the transmit PCM
highway. Typically 1.544 Mbps for a T1 carrier system. Maximum
rate 2.1 Mbps. 50% duty cycle. TTL interface.

Description

FSx

Input

Frame synchronization pulse for the transmit PCM highway.
Resets the on-chip timeslot counter for the transmit side.
Maximum repetition rate 12 KHz. Also used to differentiate
between non-signaling frames and signaling frames on the
transmit side. TTL interface.

SIGx

Input

Signaling input. This digital input is transmitted as the 8th bit of
the PCM word on the Ox lead, on signaling frames. TTL
interface.

Vss

Power

- 5V ± 5%, referenced to GRDA.

Input

Data input to program the Codec for the chosen mode of
operation. Becomes an active low chip select when CLKe is tied
to Vee. TTL interface.

CLKe

Input

Clock input to clock in the data on the De lead when the timeslot
assignment feature is used; tied to Vee to disable this feature.
TTL interface.
previously described and SUbstitute the signal present on lead SIGx for the least significant bit of the
encoded PCM word. Similarly, on a receive signaling
frame, the Codec will decode the 7 most significant
bits according to the CCITT G733 recommendation
and will output the least significant bit value on the
SIGR lead until the next signaling frame. Signaling
frames on the send and receive sides are independent of each other, and are selected by a doublewidth frame sync pulse on the appropriate channel.

FUNCTIONAL DESCRIPTION
The 2910A PCM Codec provides the analog-to-digital and the digital-to-analog conversions necessary
to interface a full duplex (4 wires) voice telephone
circuit with the PCMhighways of a time division multiplexed (TOM) system.
In a typical telephone system the Codec is used between the PCM highways and the channel filters.
The Codec provides two major functions:
• Encoding and decoding of analog signals (voice
and call progress tones)

,---------------------I

• Encoding and decoding of the signaling and supervision information

PABX I C.O SWITCHING SYSTEM I CHANNEL BANK

I
I

On a non-signaling frame, the Codec encodes the
incoming analog signal at the frame rate (FSx) into
an 8-bit PCM word which is sent out on the Ox lead
at the proper time. Similarly, the Codec fetches an 8bit PCM word from the receive highway (DR lead)
and decodes an analog value which will remain constant on lead VFR until the next receive frame.
Transmit and receive frames are independent. They
can be asynchronous (transmission) or synchronous
(switching) with each other.

I
I ,--...J.....---.
I SUPERVISION

PROTECTION

I
BATTERY

FEED

2110"
CODEC

RINGING

L __________________

~M~I~~VS

006785-4

For channel associated signaling, the Codec transmit side will encode the incoming analog signal as

Figure 4. Typical Line Termination

5-3

inter

2910A

The 291 OA Codec is intended to be used on line and.
trunk terminations. The call progress tones (dial
tone, busy tone, ring-back tone, re-order tone), and
the prerecorde,d announcements, can be sent
through the voice-path; digital signaling (off hook
and disconnect supervision, rotary dial pulses, ring
control) is sent through the signaling path.
Circuitry is provided within the Codec to internally
define the transmit and receive timeslots. In sm~1I
systems this may eliminate the need for any external
timeslot exchange; in large systems it provides one
level of concentration. This feature can be bypassed
and discrete timeslots sent to each Codec within a
system.

Bit 1

Bit 2

Mode

0
0
1
1

0
1
0
1

X&R
X
R
Standby

Bit

In the power-down mode, most functions of the Codec are directly disabled to reduce power dissipation
to a minimum.

Tlmeslot

.0
0

0
0

0
1

1
2

•
•
•
•
1

•
•
•
•

The Codec will retain the control, word (or words)
until a new word is loaded in or until power is lost.
This feature permits dynamic allocation of timeslots
for switching applications.

COOEC OPERATION
Codec Control
The operation of the 2910A is defined by serially
loading an a-bit word through the Dc lead (data) and
. the CLKc lead (clock). The loading is asynchronous
with the other operations of the Codec, and takes
place whenever transitions occur on the CLKc lead.
The Dc input is loaded in during the trailing edge of
the CLKc input.

CLKC

BITl BIT • ~~N xB~. BIT7 BITi
lBI~'LE::T21~MESLOT:
nx~
MODE

006785-3

The control word contains two fields:
Bit 1 and Bit 2 define whether the subsequent 6 bits
apply to both the transmit and receive side (00), the
transmit side only (01), the receive side only (10), or
whether the Codec should go into the standby, powerdown mode (11). In the last case (1.1), the following 6 bits are irrelevant.

Microcomputer Control Mode
In the microcomputer mode, each Codec performs
its own timeslot. computation independently for the
transmit and receive channels by counting clock
pulses (CLKx and CLKR). All Codecs tied to the
. same data bus receive identical framing pulses (FSx
and FSR). The framing pulses reset the on-chip
timeslot counters every frame; hence the timeslot
counters of all devices are synchronized. Each Codec is programmed via CLKc and Dc for the desired
transmit and receive timeslots according to the description in the Codec Control Section. All Codecs
tied to the same DR bus will, in general, have different receive timeslots, although that is not a device
requirement. There may. be separate busses for
transmit and receive or all Codecs may transmit and
receive over the same bus, in which case the transmit and receive channels must be synchronous
(CLKx = CLKR). There are no other restrictions on
timeslot assignments; a device may have the same
transmit and receive timeslot even if a single bus is
used.
There are several requirements for using the
CLKc-Dc interface in the microcomputer mode.
1) A complete timeslot aSSignment, consisting of
eight negative transitions of CLKc, must be made
in less than one frame period. The assignment

The last 6 bits of the control word define the timeslot
assignment, from 000000 (timeslot 1) to 111111
(timeslot 64). Bit 3 is the most significant bit and bit a
the least significant bit and last into the Codec.

5-4

inter

2910A

can overlap a framing pulse so long as all 8 control bits are clocked in within a total span of
125 /-Ls (for an 8 KHz frame rate).CLKe must be
left at a TTL low level when not assigning a timeslot.

the supplies are applied, it is recommended that
either power down assignment be made first, or
the first timeslot assignment be a transmit timeslot or a transmit/receive timeslot. The consequence of making a receive timeslot assignment
first, after supply application, is that the transmit
channel will assume times lot 1, potentially producing bus contention.
5) Transmit only/receive only operation is permitted
provided that a power down assignment is made
first. Otherwise, special circuits which use only
one channel should be physically disconnected
from the unused bus; this allows a timeslot to be
made to an unused channel without consequence.
6) Both frame synchronizing pulses (FSx, FSR) must
be active at all times after power on clear (after
power supplies are turned on). This requirement
must be met during powerdown and receive only
or transmit only operation, as well as during normal transmit and receive operation.

2) A dead period of two frames must always be observed between successive timeslot assignments. The two frame delay is measured from the
rising edge of the first CLKe transition of the previous timeslot assigned.
3) When the device is in the power-down state
(Standby), the following three-step sequence
must be followed to power-up the codec to avoid
contention on the transmit PCM highway.
a) Assign a dummy transmit timeslot. The dummy
should be at least two times lots greater than
the maximum valid system timeslot (usually 24
or 32). For example, in a 24 timeslot system,
the dummy could be any timeslot between 26
and 64. This will power-up the transmit side,
but prevent any spurious Ox or TSx outputs.
b) Two frames later, assign the desired transmit
timeslot.
c) Two frames later assign the desired receive
timeslot.

Example of Microcomputer Control Mode:
The two words 01000001 and 10000010 have been
loaded into the Codec. The transmit side is now programmed for timeslot 2 and· the receive side for
timeslot 3. The Codec will output a PCM word on the
transmit PCM highway (bus) during the timeslot' 2 of
the transmit frame, and will fetch a PCM word from
the receive PCM highway during timeslot 3.

4) Initialization sequence: The device contains an
on-chip power-on clear function which guarantees that with proper sequencing of the supplies
(Vee or VDD on last), the device will initialize with
no timeslot assigned to either the transmit or receive channel. After a supply failure or whenever

rSEPARATEO BY AT LEAST TWO FRAMESl

~~
9LKc .
I
I
~ \--,

Dc
I
I
,

l.-f

01000001

I
I
I
I'

I
I
I

10000010

Figure 5. Microcomputer Mode Programming Example

5-5

L-:

..---.

L------J

I
I
I
.1

006785-5

•

Intel

2910A

XMT TIME SLOT 1

FSx

XMT TIME SLOT 3

XMT TIME SLOT 2

CLK x IN

...!2 OUT
TS x OUT
Rev TIME SLOT 3

Fs" IN

PCM WORD CLOCKED IN

.,
--l

. 006785-6

Figure 6. Microcomputer Mode PCM Highway Example
In this example the Codec interface to the PCM
highway then functions as shown above. (FSx and
FSR may be asynchronous.)

fied limits. This assumes that CLKe is tied to Vee
and that all clocks are available at the time the supplies have settled.

Direct Control Mode

General Control Requirements

The direct mode of operation will be selected when
the CLKe pin is strapped to the + 5 volt supply
(Vee). In this mode, the Dc pin is an active low chip
select. In other words, when Dc is low, the device
transmits and receives in the timeslots which follow
the appropriate framing pulses. With Dc high the device is in the power down state. Even though CLKe
characteristics are simpler for the 2910A it will operate properly when plugged into a 2910 board.

All bit and frame clocks should be applied whenever
the device is active. In particular, an unused channel
cannot be deactivated by removal of its associated
frame or bit clock while the other channel of the
same device remains active.
A single channel cannot be deactivated except by
physical disconnection of the data lead (Dx or DR)
from the system data bus. A device (both transmit
and receive channels) may be deactivated in either
control mode by powering down the device. Both
channels are always powered down together.

Deactivation of a channel by removal of the appropriate framing pulse (FSx or FSR) is not permitted.
Specifically, framing pulses must be applied for a
minimum of two frames after a change in state of Dc
in order for the Dc change to be internally sensed. In
particular, when entering standby in the direct mode,
framing pulses must be applied as usual for two
frames after Dc is brought high.

Encoding
The VF signal to be encoded is input on the VFx
lead. An internal switch samples the signal and the
hold function is performed by the external capacitor
connected to the CAP1 X and CAP2x leads. The
sampling and conversion is synchronized with the

The Codec will enter the direct mode within three
frame times (375 /los) as measured from the time the
device power supplies settle to within the speci-

1 - - - - - 193 X CLK.

FSJ(

..Jl

•

(24 CHANNEL SYSTEM)

TIME SLOT 20

0, .•.•. ---------- .----------. -- --. --. --.

I
"

---l f.--

fSa

---i I-',;.;--0.'
--..... ------. -- .------... --....----.. --.

TIME SLOT 20

--·0-- --. -- .. ---- -------- .. -- ----------. ---P.lOG TILD..!Y.iTAl CONV

~==============~~--~=$~~~============~~-c~t==================---~~~
006785-7

Figure 7. Transmit Encoding

5-6

2910A

transmit timeslot. The PCM word is then output on
the Ox lead at the proper timeslot occurrence of the
following frame. The AID converter saturates at approximately ± 2.2 volts RMS (± 3.1 volts peak).

• A frame synchronization pulse which is a full
clock period in duration (CLKx· period for FSx
CLKR period for FSR) designates a non-signaling
frame.
co A frame synchronization pulse which is two full
clock periods in duration (two CLKx periods for
FSx, two CLKR periods for FSR) designates a signaling frame.

Decoding
The PCM word is fetched by the DR lead from the
PCM highway at the proper timeslot occurrence. The
decoded value is held on an internal sample and
hold capacitor. The buffered non-return to zero output signal on the VFR lead has a dynamic range of
approximately ± 2.2 volts RMS (± 3.1 volts peak).

On the encoding side, when the FSx pulse is widened, the 8th bit of the PCM word will be replaced by
the value on the SIGx input at the time when the 8th
bit is output on the Ox lead.

Signaling

On the decoding side, when the FSR pulse is widened, the 8th bit of the PCM word is detected and
transmitted on the SIGR lead. That output is latched
until the next receiving signaling frame.

The duration of the FSx and FSR pulses defines
whether a frame is an information frame or a signaling frame:

1•

TS..

"1 I-

The remaining 7 bits are decoded according to the
value given in the CCITT G733 recommendation.
The SIGR lead is reset to a TTL low level whenever
the Codec is in the power-down state.

TSn.

192 iTS.. I "

TSn,

CLKX~J~,J1..J1..JiU'~
192

8n-7

FS X ~
~

,~,--+.- - - - - - - - -

.--------------------------'~::' •. '- . . . • . -- . . . . ' . - .

:x :::::::::::: :::::: :::::~:

XMIT SIGNAL FRAME

i:::::: : ::::

. . . .,

jGX.:

:~:: x::::::::;==t=========O=A=
006785-8

Figure 8. Transmit 8th Bit Signaling

TS.,

1•

TSn,

192

I•

TS.,

TSn n

CLKR~'~'.f1..fU1U'l.Il..I1SU1..J1
192

REC. SIGNAL FRAME

FS. .Jl

,~,

___________
SIGR

DR
SIG

~~~=:::=::~====:~====~:::::::::::~::::::~:~~~~~::=:~:~._~::::::~::::~~

===========:

B8::

006785-9

Figure 9. Receive 8th Bit Signaling

5-7

'ib

•

infef

2910A

T1 Framing

Precision Voltage Reference for the
D/A Converter

The Godec will accept the standard 03/04 framing
format of 193 clock pulses per frame (equivalent to
GLKx, GLKR of 1.544 Mb/s). However, the 193rd bit
may be blanked (equivalent to GLKx, GLKR of
1.536 Mb/s) if desired.

The voltage reference is generated on the chip and
is calibrated during the manufacturing process. The
technique uses the difference in sub-surface charge
density between two suitably implanted MOS devices to derive a temperature stable and bias stable
reference Voltage.

Standby Mode-Power Down
A gain setting op amp, programmed during manufacturing, "trims" the reference voltage source to the
final precision voltage reference value provided to
the 0/ A converter. The precision voltage reference
determines the initial gain and dynamic range characteristics described in the A.G. Transmission Specification section.

To minimize power consumption and heat dissipation a standby mode is provided where all Godec
functions are disabled except for De and GLKe
leads. These allow the Godec to be reactivated. In
the microcomputer mode the Godec is placed into
standby by loading a control word (Dc) with a "1" in
bits 1 and 2 locations. In the direct mode when De is
brought high, the all "1 's" control word is internally
transferred to the control register, invoking the
standby condition.

fL-Law Conversion
,..,-Iaw represents a particular implementation of a
piece-wise linear approximation to a logarithmic
compression curve which is:

While in the standby mode, the Ox output is actively
held in a high impedance state to guarantee that the
PGM bus will not be driven. The SIGR output is held.
low to provide a known condition and remains this
way upon activation until it is changed by signaling.

F(x)

The power consumption in the standby mode is typically 33 mW.

where x

,.., =

Whether the device is used in the direct or microcomputer mode, an internal reset (power-on clear) is
generated, forcing the device into the power down
state, when power is supplied by any of the following
methods. (1) Device power supplies are turned on in
a system power-up situation where either Vee or
Voo is applied last. (2) A large supply transient causes either of the two positive supplies to drop to less
than approximately 2 volts. (3) A board containing
Godecs is plugged into a "hot" system where Vee or
VOD is the last contact made. It may be necessary to
trim back the edge connector pins or fingers on Vee
or VDO relative to the other supply to guarantee that
the power-on clear will operate properly when a
board is plugged into a "hot" system. Furthermore,
the Godec will inhibit activity on TSx and Ox during
the application of power supplies.

Ixl

input signal

Sgn(x)

Power-On Clear

Sgn(x) In(1 + ,..,Ixl) 0
In(1 +,..,)

sign of input signal
255 (defined by AT & T)

The 2910A ,.., = 255 law Godec uses a 15 segment
approximation to the logarithmic law. Each segment
consists of 16 steps. In adjacent segments the step
sizes are in a ratio of two to one. Within each segment the step size is constant except for the first
step of the first segment of the encoder, as indicated
in the attached table. The output levels are midway
between the corresponding decision levels. The output levels Yn are related to the input levels xn by the
expression:
Yn =

x +x
n

for 1 ~ n ~ 127

Yo = Xo = 0 for n = 0
These relationships are implicit in the following table.

The device is also tolerant of transients in the negative supply (Vss) so long as Vss remains more negative than -3.5 volts. VSB transients which exceed
this level should be detected and followed by a sys.
tem reinitialization.

5-8

inter

2910A

Theoretical ,..,-Law-Positive Input Values (for Negative Input Values, Invert Bit 1)
1
Segment
Number

No. of Steps
x Step Size

Value at
Segment
End
Points

Decision
Value
Numbern

Decision
Va)uexn(l)

8159(5)

(128)

(8159)

127

7903

I
I
I
I

Msa

PCMWord(3)

Normalized
Value
at Decoder
Output Yn(4)

Decoder
Output
Value
Number

8031

127

I
I
I
I
I
I

B'itNumber

LSa

1 234 567 8

1 000 000 0
8

16 x 256

4063
7

16x 128

2015
6

16x64

991
5

16x32

479
4

16x16

113

4319

112

4063

I
I
I
I

2143

2015

I
I
I
I

1055

991

I
I
I
I

511

479

I
I
I
I

(see Note 2)

I
I
1 0 0 o 1 1 1 1 I-

(see Note 2)

I
I
1 0 0 1 1 1 1 1 I-

(see Note 2)

I
I
1 o 1 o 1 1 1 1 I-

i
(see Note 2)
I
I
1 o 1 1 1 1 1 1

239

223

16x8

I
I
I
I

I
I

103

16x4

I
I
I
I

I
I
I

I
I
I
I

15x2

I
I

(see Note 2)

I
I

4191

112

I
I
I
I
I
I

2079

I
I
I
I
I
I

1023

I
I
I
I
I
I

495

I
I
I
I
I
I

231

I
I
I
I
I
I

I-

I
I
I
I
I
I

(see Note 2)

I
I
1 1 1 1 1 1 1 0

1x 1

I-

1 1 1 o 1 1 1 1
31

I-

(see Note 2)

·1 1 0 1 1 1 1 1
95

I-

(see Note 2)

1 1 0 o 1 1 1 1
223

I-

1 1 1 1 1 1 1 1

NOTES:
1.8159 normalized value units correspond to the value of the on-chip voltage reference,
2. The PCM word corresponding to positive input values between two successive decision values numbered nand n + 1
(see column 4) is (255-n) expressed as a binary number,
3. The PCM word on the highways is the same as the one shown in column 6.
4. The voltage output on the VFR lead is equal to the normalized value given in the table, augmented by an offset. The
offset value is approximately 15 mY.
5. x128 is a virtual decision value.

5-9

•

2910A

006785-10

Figure 10. Codec Transfer Characteristic

one half-step away from the origin. For example, the
maximum decoder output level for signaling frames
has normalized value 7903, whereas it has value
8031 in normal (non-signaling) frames.

During signaling frames, a 7-bit transfer characteristic is implemented in the decoder. This characteristic
is derived from the decoder values in the attached
table by assuming a value of "1" for the LSB (8th
bit) and shifting the decoder transfer characteristics

APPLICATIONS

VFx

,------------,
~
+
CODEC

5009

CAP1x

CAPx
2000 pF

150 KO :

'f
GRDA

I
I

2 mV OFFSET

L-tRDA --- ------ J
006785-11

Figure 11. Circuit Interface-without External Auto Zero

5-10

inter

2910A

For an 8 KHz sampling system 'the transmit holding
capacitor CAPx should be 2000 pF ±20%.

The circuit interface with auto zero drawing shows a
possible connection between the VFx and AUTO
leads with the recommended values of C1 = 0.3 J.LF,
R1 = 150 Kfl., R2 = 330 Kfl., and R3 = 470 Kfl..

Auto Zero

Filters Interface

The 291 OA contains a transparent on-chip auto zero
plus a device pin for implementing a sign-bit driven
external auto zero feedback loop. The on-chip auto
zero reduces the input offset voltage of the encoder
(VFx) to less than 3 mV. For most telephony applications, this input offset is perfectly acceptable, since it
insures the encoder is biased in the lower 25% of
the first segment.

The filters may be interfaced as shown in the circuit
interface diagrams. Note that the output pulse
stream is of the non-return-to-zero type and hence
requires the (sin x)/x correction provided by the
2912A filter.

Where lower input offset is required the· external
auto zero loop may be used to bias the encoder exactly at the zero crossing point. The consequence of
the external auto zero loop, aside from extra components, is the addition of the dithering auto-zero signal to the input signal, resulting in slightly higher idle
channel noise (approximately 2dB) than when the
external loop is not used. Consequently, where the
application permits, it is recommended that the external auto zero loop not be used. When not used,
the AUTO pin should float.

For higher drive capability or increased system reliability it may be desirable that the Ox output of a
group of Codecs be buffered from the system PCM
bus with an external three-state or open collector
buffers. A buffer can be enabled with the appropriate
Codec generated TSx signal or signals. TSx signal
may also be used to activate external zero code suppression logic, since the occurrence of an active
state of any TSx implies the existence of PCM voice
bits (as opposed to transparent data bits) on the
bus.

Holding Capacitor

r------

Ox Buffering

I
I
I

r---

VFx

~--"'V>_---l AUTO

R3
470 Kn

R,
330n

-=-

GRDA
VFR

006785-12

Figure 12. Circuit Interface-with External Auto Zero

5-11

inter

2910A

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet. The specifications are subject to change without notice.

Temperature Under Bias ......... -1 O·C to + BO·C

Storage Temperature .......... - 65·C to + 150·C
All Input or Output Voltages with
Respect to Vss ................ - O.3V to + 20V
VCC, VDD, GRDD, and GRDA with.
Respect to Vss ................ - O.3V to + 20V
Power Dissipation ........................ 1.35W

D.C. CHARACTERISTICS
TA=O·C to +70·C, VDD= +12V ±5%, VCC= +5V ±5%, Vss= -5V ±5%, GRDA=OV, GRDD=OV,
unless otherwise specified

DIGITAL INTERFACE
Symbol

Limits

Parameter
Min

Typ(l)

Test Conditions

Units
Max

IlL

Low Level Input Current

",A

VIN

IIH

High Level Input Current

",A

VIN> VIH

VIL

Input Low Voltage

0.6

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

2.0

< VIL

V
0.4

2.4

Dx, 10L = 4.0 mA
SIGR, 10L = 0.5 mA
TSx, 10L = 3:2 mA, Open Drain
PDN, 10L = 1.6 mA, Open Drain

Dx,lOH = 15 mA
SIGR 10H = 0.08 mA

ANALOG INTERFACE
Symbol

Limits

Parameter
Min

Typ(l)

Max

Units

Test Conditions

ZAI

Input Impedance when
Sampling, VFx

125

300

500

in Series with CAPx to GRDA,
-3.1V < VIN < 3.1V

ZAO

Small Signal Output
Impedance, VFR

100

180

300

-3.1V

VOR

Output Offset Voltage at VFR

±50

all "ls" code sent to DR

VIX

Input Offset Voltage at VFx

±5

VFx Voltage Required to
Produce all "1 s.. Code at Dx

VOL

Output Low Voltage at AUTO

(Vss+2)

400 KO, to GRDA

VOH

Output High Voltage at AUTO

400 KO, to GRDA

Vss
(Vcc- 2)

Vcc

< VOUT < 3.1V

POWER DISSIPATION
Symbol

Limits

Parameter
Min

Typ(l)

Units _

1000

Standby Current

0.7

1.1

Icco

Standby Current

7.0

Isso

Standby Current

2.5

1001

Operating Current

Icci

Operating Current

Issl

Operating Current

6.0

NOTE:
1. Typical values are for TA

25·C and nominal power supply values.
5-12

Test Conditions

Max
Auto Output = Open Clock
Frequency = 2.048 MHz

infef

2910A

A.C. CHARACTERISTICS
TA=O·C to +70·C, VDD= +12V ±5%, vcc= +5V ±5%, VBB= -5V ±5%, GRDA=OV, GRDD=OV,
unless otherwise specified
TRANSMISSION
Symbol

Limits

Parameter

Typ(1)

Min
SID

Signal/Tone Distortion Ratio,
C-Message Weighted
Half Channel
(See Figure 1)

Unit

Test Conditions

dB
dB
dB

VFx = 1.02 KHz, Sinusoid
-30 dBmO ,;; VFx ,;; 0 dBmO
-40 dBmO ,;; VFx < -30 dBmO
-45 dBmO ,;; VFx < -40 dBmO

Max

36
30
27
±0.25
±0.60
±1.5

±0.30
±0.70
±1.B

dB
dB
dB

VFx = 1.02 KHz, Sinusoid
-37dBmO';; VFx';; +3dBmO
-50 dBmO ,;; VFx < -37 dBmO
-55 dBmO ,;; VFx < -50 dBmO

±0.0002
±0.0004

±0.0004
±O.OOOB

dB/mV
dB/mV

-37 dBmO ,;; VFx ,;; +3 dBmO
-50 dBmO ,;; VFx < -37 dBmO

llG
Gain Tracking Deviation
Half Channel(2)
Reference Level 0 dBmO
llGv

llG Variation with Supplies
Half Channel

llGT

llG Variation with Temperature
Half Channel

±0.001
±0.002

±0.002
±0.005

dBI'C
dBI'C

-37 dBmO ,;; VFx ,;; +3 dBmO
-50 dBmO ,;; VFx < -37 dBmO

NIC1

Idle Channel Noise, C-Message
Weighted

dBrncO

No Signaling(3)

NIC2

Idle Channel Noise, C-Message
Weighted

dBrncO

with 6th and 12th Frame
Signaling(3)

NIC3

Idle Channel Noise, C-Message
Weighted

dBrncO

with 1 KHz Sign BitToggle

Harmonic Distortion (2nd or 3rd)

-4B

-44

IMD

Intermodulation Distortion
2nd Order
3rd Order

-45
-55

dB
dB

VFx = 1.02 KHz, 0 dBmO;
Measured at Decoder Output VFR
4-Tone Stimulus in Accordance
with BSTR PUB 41009

NOTES:
1. Typical values are for T A = 25°C and nominal supply values.
2. Measured in one direction, either decoder or encoder and an ideal device, at 23°C, nominal supplies.
3. If the external auto-zero is used NIC1 has a typical value of B dBrncO and NIC2 has a typical value of 13 dBrncO.
4. DR of Device Under Test (D.U.T.) driven with repetitive digital word sequence specified in CCITT recommendation G.711.
Measurement made at VFR output.
5. With the D.C. method the positive ancj negative clipping levels are measured and AIR is calculated. With the A.C. method
a sinusoidal input· signal to VFx is used where AIR is measured directly.
36
~---------------~~

:.;,.............
///

AT&T 03 CHANNEL
BANK COMPATIBILITY
SPECifiCATION

~~~~~~~~~~~

(ISSUE 3·10·17)

L--..--:=j~~~~~~

ATAT
D3 CHANNEL lANK

COIiPATIIIUTY
SPECIFICATION

-55

(lSSUE31G-17)

INPUT

_37.-_ _ _ _.....:;·3 :;:~~

END-TO-END

-,
·30

-20

INPUT LEVEl {dBmOI

006785-13

006785-14

Figure 14. Gain Tracking Deviation (~G)
(Half-Channel)

Figure 13. Signal/Total Distortion Ratio
(Half-Channel)

5-13

inter

2910A

A.C. CHARACTERISTICS
TA=O'C to +70'C, VDD=+12V ±5%, vee
unless otherwise specified (Continued)

+5V ±5%, vss= -5V ±5%, GRDA=OV, GRDD=OV,

GAIN AND DYNAMIC RANGE
Symbol

Limits

Parameter
Min

DmW

Digital Milliwatt Response

Unit

Typ(1)

5.53

5.63

5.73

dBm

-0.001

-0.002

dBI"C

±0.07

2.23

VRMS

DmWT

DmWO Variation with
Temperature

DmWS

DmWo Variation with
Supplies

AIR

Input Dynamic Range

AIRT

Input Dynamic Range with
Temperature

-0.5

AIRS

Input Dynamic Range with
Supplies

±18

mVRMS

AOR

Output Dynamic Range, VFR 2.13

2.19

VRMS

AORT

AOR Variation with
Temperature

-0:5

AORS

AOR Variation with Supplies

±18

2.17

Test Conditions

Max

2.20

2.16

23'C, Nominal Supplies(4)
Relative to 23'C(4)
Supplies ± 5%(4)
Using D.C. and A. C. Tests(5)
23'C, Nominal Supplies

mVRMsl"C Relative to 23'C
Supplies ±5%
23'C, Nominal Supplies

mVRMSI"C Relative to 23'C
mVRMS

Supplies ±5%

SUPPLY REJECTION AND CROSSTALK
Symbol

Limits

Parameter
Min

Typ(1)

Unit

Test Conditions

Max

PSRR1

VDD Power Supply Rejection Ratio

Decoder Alone(2)

PSRR2

Vss Power Supply Rejection Ratio

Decoder Alone(2)

PSRR3

Vee Power Supply Rejection Ratio

Decoder Alone(2)

PSRR4

VDD Power Supply Rejection Ratio

Encoder Alone(3)

PSRR5

Vss Power Supply Rejection Ratio

Encoder Alone(3)

(Note 4)

(Note 5)

PSRR6

Vee Power Supply Rejection Ratio

CTR

Crosstalk Isolation, Receive Side

CTT

Crosstalk Isolation, Transmit Side

CAPX

Input Sample and Hold Capacitor

1600

200

2400

NOTES:
1. Typical values are for TA = 25'e and nominal power supply values.
2. D.U.T. decoder; impose 200 mVp.p, 1.02 KHz on appropriate supply; measurement made at decoder output;
idle channel conditions.
3. D.U.T. encoder; impose 200 mVp'p, 1.02 KHz on appropriate supply; measurement made at encoder output;
idle channel conditions.
4. VFx of D.U.T. encoder = 1.02 KHz, 0 dSmO. Decoder under quiet channel conditions; measurement made
output.
5. VFx = 0 Vrms. Decoder = 1.02 KHz, 0 dSmO. Encoder under quiet channel conditions; measurement made
output.

5-14

decoder in
encoder in
at decoder
at encoder

intJ

2910A

A.C. CHARACTERISTIC-TIMING SPECIFICATION(1)
TA=O·Cto +70·C, voo= + 12V ±5%, vcc= +5V ±5%, vss= -5V ±5%, GRDA=OV, GRDD=OV,
unless otherwise specified
CLOCK SECTION
Symbol

Limits

Parameter

Min
'tCY

Clock Period

tr, tf

Clock Rise and Fall Time

tCLK

Clock Pulse Width

215

tcoc

Clock Duty Cycle (tCLK .;- tCY)

Units

485
0

Comments

Max

CLKx, CLKR (2.048 MHz Systems), CLKc

CLKx, CLKR, CLKc

CLKx, CLKR

TRANSMIT SECTION
Symbol

Limits

Parameter

Min

Units

Comments

Timeslot

from Leading Edge of Transmit Timeslot (2)

Max

tVFX

Analog Input Conversion

tozx

Data Enabled on TS Entry

180

0< CLOAO < 100 pF

tOHx

Data Hold Time

230

0< CLOAO < 100 pF

tHZX

Data Float on TS Exit

245

CLOAO = 0

tsON

Timeslot X to Enable

220

Xto Disable

225

CLOAO < 100pF

tSOFF

Timeslot

CLOAO = 0

tss

Signal Setup Time

Relative to Bit 7 Falling Edge

tSH

Signal Hold Time

100

Relative to Bit 8 Falling Edge

tFSO

Frame Sync Delay

150

RECEIVE AND CONTROL SECTIONS
Symbol

Parameter

Limits
Min

Max

9Y16

9 V,6

tVFR

Analog Output Update

tOSR

,Receive Data Setup

tOHR

Receive Data Hold

tSIGR

SIGR Update

Units

Comments

Timeslot

from Leading Edge of the Channel Timeslot

ns
ns
1

,...s

from Trailing Edge of the Channel Timeslot

tFso

Frame Sync Delay

tosc

Control Data Setup

115

Microcomputer Mode Only

tOHC

Control Data Hold

115

Microcomputer Mode Only

150

NOTES:
1, All timing parameters referenced to 1.5V, except tHZX and tSOFF which reference to high impedance state.
2. The 20 timeslot minimum insures that the complete AlO conversion will take place under any combination of receive
interrupt or asynchronous operation of the Codec. If the transmit channel only is operated, the AID conversion can be
completed in a minimum of 11 timeslots. Refer to the Codec Control General Requirement section for instructions on setting
a channel in ·an idle condition.

5-15

-I

:IJ

:::!

<
rn

>
z

i:
:::j
i:

elK,

'\.

,\;,

'\.

-t
G)

::D

006785-15

I\)

<»

102x
Ox

SIG

~ON'T

CARE

'j
55
_.

I.
r--

VALID

.--It'I 5H
I

--O-O-N-'T--

__C_A_R_E;.-__

006785-16

::!
is:

cg
::0

is:

17~
:5"
c:
(1)

.&
006785-17
N

CO
....
C
»

-.J

elK R

,--

SIGR: : : : : : : : : : : : : : : : : : : : : : : : : :~ ~ : ': : : : :~ : : : : ~ ~ : : ~ : ~<:
VALID

006785-18

2910A

TIMING WAVEFORMS (Continued)
CONTROL TIMING

,.
0>

5-18

2911A-1
PCM CODEC-A LAW
a-BIT COMPANDED AID AND DI A CONVERTER

•
•
•
•
•±

Per Channel, Single Chip Codec

CCITT G711 and G732 Compatible,
Even Order Bits Inversion Included

Microcomputer Interface with On-Chip
Time-Slot Computation
Simple Direct Mode Interface When
Fixed Timeslots Are Used
5% Power Supplies:

+ 12V, + 5V,

- 5V

•
•
•
•

66 dB Dynamic Range, with Resolution
Equivalent to 11-Bit Linear Conversion
Around Zero
Precision On-Chip Voltage Reference
Low Power Consumption 230 mW Typ.
Standby Power 33 mW Typ.
Fabricated with Reliable N-Channel
MOS Process

The Intel 2911A is a fully integrated PCM (Pulse Code Modulation) Codec (Coder· Decoder), fabricated with
N-channel silicon gate technology. The high density of integration allows the sample and hold circuits, the
digital-to·analog converter, the comparator and the successive approximation register to be integrated on the
same chip, along with the logic necessary to interface a full duplex PCM link.
The primary applications are in telephone systems:
• Transmission
• Switching
• Concentration

30/32 Channel Systems at 2.048 Mbps
Digital PBX's and Central Office Switching Systems
Subscriber Carrier/Concentrators

The wide dynamic range of the 2911 A (66 dB) and the minimal conversion time (80 p.s minimum) make it an
ideal product for other applications, like:
.
• Secure Communications Systems
• Signal Processing Systems

• Data Acquisition
• Telemetry

TRANSMIT SECTION AID

o
o

VF,

r------1--4-.

--!----I

AUTO

CD CAP '0 CAP2 '_-+__-i

S,,:"LE I - - - - - i
HOLD

@
@
CLK K @)
Ts,.

SUCCESSIVE
APPROXIMATION

FS,

270158-1

Figure 1. Pin
Configuration
CAP lx. CAP 2x

Holding CapaCitor

VFX

Analog Input

VFR

Analog Output

DR. De

Digital Input

TSx

Ox.
CLKe. CLKx. CLKR

,"--1--4--0. 0

I-+_CLK.@
1-+-F5" ®

Digital Output
Clock Input

FSx. FSR

Frame Sync Input

AUTO

Auto Zero Output

Vee

Power (-SV)

Vee

Power (+SV)

Vee
PDN

Power (+ 12V)

GRDA

Analog Ground

GRDD

Digital Ground

No Connect

'--_...J

PIN""""'.

270158-2

Power Down

Figure 3. Block Diagram

Figure 2. Pin Names

5-19

November 1~86
Order Number: 270158-001

inter
PIN DESCRIPTION
Pin No
1

Symbol
CAP1x

Function

Description

Hold

Connections for the transmit holding capacitor. Refer to
-Applications section.

CAP2x

VFx

Input

Analog input to be encoded into a PCM word. The signal on
this lead is sampled at the same rate as the transmit frame
synchronization pulse FSx, and the sample value is held in the
external capacitor connected to the CAP1 X and CAP2x leads
until the encoding process is completed.

AUTO

Output

Most significant bit of the encoded PCM word ( + 5V for
negative, - 5V for positive values). Refer to the Codec
Applications section.

GRDA

Ground

Analog return common to the transmit and receive analog
circuits. Not connected to GRDD internally.

Voo

Power

+ 12V ± 5%; referenced to GRDA.

Input

Receive PCM highway (serial bus) interface. The Codec
serially receives a PCM word (8 bits) through this lead at the
proper time defined by FSR, CLKR, De, and CLKe.

PDN

Output

Active high when the Codec is in the power down state. Open
drain output.

VFR

Output

Analog Output. The voltage present on VFR is the decoded
value of the PCM word received on lead DR. This value is held
constant between two conversions.

NC
NC

No
Connects

Recommended practice is to strap these NC's to GRDA.

11
12

GRDD

Ground

Ground return common to the logic power supply; Vee.

Output

Output of the transmit side onto the send PCM highway (serial
bus). The 8-bit PCM word is serially sent out on this pin at the
proper time defined by FSx, CLKx, De, and CLKe. TTL threestate output.

TSx

Output

Normally high, this signal goes low while the Codec is
transmitting an 8-bit PCM word on the Dx lead. (Timeslot
information used for diagnostic purposes and also to gate the
data on the Dx lead.) Open drain output.

Vee
CLKR

Power

+ 5V ± 5%, referenced to GRDD.

Input

Master receive clock defining the bit rate on the receive PCM
highway. Typically 2.048 Mbps for a carrier system. Maximum
rate 2.1 Mbps. 50% duty cycle. TTL compatible.

FSR

Input

Frame synchronization pulse for the receive PCM highway.
Resets the on-chip timeslot counter for the receive side.
Maximum repetition rate 12 KHz. TTL interface.

CLKx

Input

Master transmit clock defining the bit rate on the transmit
PCM highway. Typically 2.048 Mbps for a carrier system.
Maximum rate 2.1 Mbps. 50% duty cycle. TTL interface.

FSX

Input

Frame synchronization pulse for the transmit PCM highway.
Resets the on-chip timeslot counter for the transmit side.
Maximum repetition rate 12 KHz. TTL interface.

VBB

Power

-5V

Input

Data input to program the Codec for the chosen mode of
operation. Becomes an active low chip select when CLKe is
tied to Vee. TTL interface.

CLKe

Input

Clock input to clock in the data on the De lead when the
timeslot assignment feature is used; tied to Vee to disable this
feature. TTL interface.

± 5%, referenced to GRDA.

5-20

infel"

2911A-1

CO DEC OPERATION

FUNCTIONAL DESCRIPTION
The 2911 A PCM Codec provides the analog-to-digital and the digital-to-analog conversions necessary
to interface a full duplex (4 wires) voice telephone
circuit with the PCM highways of a time division multiplexed (TOM) system. The Codec is intended to be
used on line and trunk terminations.

Codec Control
The operation of the 2911A is defined by serially
loading an a-bit word through the Dc lead (data) and
the CLKc lead (clock). The loading is synchronous
with the other operations of the Codec, and takes
place whenever transitions occur on the CLKc lead.
The Dc input is loaded in during the trailing edge of
the CLKc input.

In a typical telephone system the Codec is located
between the PCM highways and the channel filters.
The Codec encodes the incoming analog signal at
the frame rate (FSx) into an a-bit PCM word which is
sent out on the Ox lead at the proper time. Similarly,
on the receive link, the Codec fetches an a-bit PCM
word from the receive highway (DR lead) and decodes an analog value which will remain constant on
lead VFR until the next receive frame. Transmit and
receive frames are independent. They can be asynchronous (transmission) or synchronous (switching)
with each other.

Bill

BlT3

81T4

BIT5

BIT6

BIT 7

BITS

~S~~~~T-1 ___-=TI'::S;~~T\:'""

I
270158-4

The control word contains two fields:

Circuitry is provided within the Codec to internally
define the transmit and receive timeslots. In small
systems this may eliminate the need for any external
timeslot exchange; in large systems it provides one
level of concentration. This feature can be bypassed
and discrete times lots sent to each Codec within a
system.

Bit 1 C!.nd Bit 2 define whether the subsequent 6 bits
apply to both the transmit and receive side (00), the
transmit side only (01), the receive side only (10), or
whether the Codec should go into the standby, power-down mode (11). In the last case (11), the following 6 bits are irrelevant.

In the power-down mode, most functions of the Codec are directly disabled to reduce power dissipation
to a minimum.

,..c;;;;~~:)

TELEPHONE SET

r--------------------~-

PABX I C.O. SWITCHING SYSTEM I CHANNEL BANK

I
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TRANSMISSION
HIGHWAYS

CONTROL HIGHWAYS
OFF·HOOK I ROTARY DIAL PULSES
SUPERVISION
PROTECTION

BATTERY
FEED

I
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RINGING

I
I _____________________ _
L
270158-3

Figure 4. Typical Line Termination

5-21

inter

2911A-1

The last 6 bits of the control word define the timeslot
assignment, from 000000 (timeslot 1) to 111111
(timeslot 64). Bit 3 is the most significant bit and bit 8
the least significant bit and last into the Co dec.
Bit 1 Bit 2

0
1
0
1

0
0
1
1

X&R
X
R
Standby

Bit
4 5 6

7 8

0
0

0
1

•
e

•
•

2. A dead period of two frames must always be observed between successive times lot assignments. The two frame delay is measured from the
rising edge of the first CLKe transition of the previous timeslot assigned.
3. When the device is in the power-down state
(Standby), the following three-step sequence
must be followed to power-up the codec to avoid
contention on the transmit PCM highway.
a. Assign a dummy transmit timeslot. The dummy
should be at least two timeslots greater than
the maximum valid system (usually 24 or 32).
For example, in a 24 timeslot system, the dummy could be any timeslot between 26 and 64.
This will power-up the transmit side, but prevent any spurious Dx or TSx outputs.
b. Two frames later, assign the desired transmit
timeslot.
c. Two frames later assign the desired receive
timeslot.
.

Mode

0
0

can overlap a framing pulse so long as all 8 control bits are clocked in within a total span of
125 JLs (for an 8 KHz frame rate). CLKe must be
left at a TTL low level when not assigning a timeslot.

Time-Slot

1
2

•
•
•
•

The Codec will retain the control word (or words)
until a new word is loaded in or until power is lost.
This feature permits dynamic allocation of timeslots
for switching applications.

4. Initialization sequence: The device contains an
on-chip power-on clear function which guarantees
that with proper sequencing of the supplies (Vee
or Voo on last), the device will initialize with no
timeslot assigned to either the transmit or receive
channel. After a supply failure or whenever the
supplies are applied, it is recommended that either power down assignment be made first, or the
first times lot assignment be a transmit timeslot or a transmit/receive timeslot. The consequence of making a receive timeslot assignment
first, after supply application, is that the transmit
channel will assume timeslot 1, potentially producing bus contention.
5. Transmit only/receive only operation is permitted
provided that a power down assignment is made
first. Otherwise, special circuits which use only
one channel should be physically disconnected
from the unused bus; this allows a timeslot to be
made to an unused channel without consequence.
6. Both frame synchronizing pulses (FSx, FSR) must
be active at all times after power on clear (after
power supplies are turned on). This requirement
must be met during powerdown and receive only
or transmit only operation, as well as during normal transmit and receive operation.

Microcomputer Control Mode
In the microcomputer mode, each Codsc performs
its own times lot computation independently for the
transmit and receive channels by counting clock
pulses (CLKx and CLKR). All Codecs tied to the
same data bus receive identical framing pulses (FSx
and FSR). The framing pulses reset the on-chip
timeslot counters every frame; hence the timeslot
counters of all devices are synchronized. Each Codec is programmed via CLKe and Dc for the desired
transmit and receive timeslots according to the description in the Codec Control Section. All Codecs
tied to the same DR bus will, in general, have different receive timeslots, although that is not a device
requirement. There may be separate busses for
transmit and receive or all Codecs may transmit and
receive over the same bus, in which case the transmit and receive channels must be synchronous
(CLKx = CLKR). There are no other restrictions on
timeslot assignments; a device may have the same
transmit and receive timeslot even if a single bus is
used.
There are several requirements for using the
CLKe-De interface in the microcomputer mode.
1. A complete timeslotassignment, consisting of
eight negative transitions of CLKe, must be made
in less than one frame period. The assignme~t

Example of Microcomputer Control Mode:
The two words 01000001 and 10000010 have been
loaded into the Codec. The transmit side is now programmed for timeslot 2 and the receive side for
5-22

2911A-1

timeslot 3. The Godec will output a PGM word on the transmit PGM highway (bus) during the timeslot 2 of the
transmit frame, and will fetch a PGM word from the receive PGM highway during timeslot 3.

SEPARATED BV AT LEAST TWD FRAMESl

Ji1..J2lJ3l.Fl.~
~LKc

;

~~:
Dc
I

:
I

.1
I

01000001

:
I

1 I

10000010

270158-5

Figure 5. Microcomputer Mode Programming Examples
In this example the Godec interface to the PGM highway then functions as shown below. (FSx and FSR may
be asynchronous.)

XMT TIME SLOT 1

XMT TIME SLOT J

XMT TIME SLOT 2

Fs,. IN
eLK. IN

Ox OUT
TS. OUT
Aev TIME SLOT 1

Fs"

Rev TIME SLOT 3

PCM WORD CLOCKED IN

270158-6

Figure 6. Microcomputer Mode peM Highway Example
The Godec will enter direct mode within three frame
times (375 !-,-s) as measured from the time the device power supplies settle to within the specified limits. This assumes that GLKe is tied to Vee and that
all clocks are available at the time the supplies have
settled.

Direct Control Mode
The direct mode of operation will be selected when
the GLKe pin isstrapped to the +5V supply (Vecl.
In this mode, the De pin is an active low chip select.
In other words, when De is low, the device transmits
and receives in the timeslots which follow the appropriate framing pulses. With De high the device is in
the power down state. Even though GLKe characteristics are simpler for the 2911 A it will operate properly when plugged into a 2911 board.

General Control Requirements
All bit and frame clocks should be applied whenever
the device is active. In particular, an unused channel
cannot be deactivated by removal of its associated
frame or bit clock while the other channel of the
same device remains active.

Deactivation of a channel by removal of the appropriate framing pulse (FSx or FSR) is not permitted.
Specifically, framing pulses must be applied for a
minimum of two frames after a change in state of De
in order for the De change to be internally sensed. In
particular, when entering standby in the direct mode,
framing pulses must be applied as usual for two
frames after De is brought high.

A single channel cannot be deactivated except by
physical disconnection of the data lead (OX or DR)
from the system data bus. A device (both transmit
and receive channels) may be deactivated in either
control mode by powering down the device. Both
channels are always powered down together.
5-23

Intel

2911A-1

Encoding
The VF signal to be encoded is input on the. VFx
lead. An internal switch samples the signal and the
hold function is performed by the external capacitor
connected to the CAP1 X and CAP2x leads. The

sampling and conversion is synchronized with the
transmit timeslot. The PCM word is then output on
the Ox lead at the proper timeslot occurrence of the
following frame. The AID converter saturates at approximately ±2.2V RMS (±3.1V peak).

·----.5GX ClK.------!·

fool

... ~~___~..=.~CKUM~=El~S=~~MI~=_TT--J~----------~~==~",_~L-----------------TIME SLOT 20 --I I-TIME SLOT 20 -I
0. ..... - .. - .... _.. _........ _......
.., .. -0 .............. _....... -.- ... -... ..... ... ... ..
,............. _..... -_ ... _....... -........ _Tt;

, 270158-7

Figure 7. Transmit Encoding

Standby Mode-Power Down
To minimize power consumption and heat dissipation a standby mode is provided where all Codec
functions are disabled except for De and CLKe
leads. These allow the Codec to be reactivated. In
the microcomputer mode the Co dec is placed into
standby by loading a control word (Dc) with a "1" in
bits 1 and 2 locations. In the direct mode when De !s
brought high, the all "1 's" control word is internally
transferred to the control register, invoking the
standby condition.
.

generated, forcing the device into the power down
state, when power is supplied by any of the following
methods. (1) Device power supplies are turned on in
a system power-up situation where either Vee or
VDD is applied last. (2) A large supply transient causes either of the two positive supplies to drop to approximately 2V. (3) A board containing Codecs is
plugged into a "hot" system where Vee or VDD is
the last contact made. It may be necessary to trim
back the edge connector pins or fingers on Vee or
VDD relative to the other supply to guarantee that
the power-on clear will operate properly when a
board is plugged into a "hot" system. Furthermore,
the Codec will inhibit activity on TSx and Dx during
the application of power supplies.
The device is also tolerant of transients in the negative supply (Vss) so long as VSB remains more negative than -3.5V. Vss transients which exceed this
level should be detected and followed by a system
reinitialization.

Precision Voltage Reference for the
DIA Converter
'

While in the standby mode, the Ox output is actively
held in a high impedance state to guarantee that the
PCM bus will not be driven.

The power consumption in the standby mode is typically 33 mW.

Power-On Clear
Whether the device is used in the direct or microcomputer mode, an internal reset (power-on clear) is

5-24

2911A-1

A gain setting op amp, programmed during manufacturing, "trims" the reference voltage source to the
final precision voltage reference value provided to
the Df A converter. The precision voltage reference
determines the initial gain and dynamic range characteristics described in the A.G. Transmission Specification section.

CONVERSION LAW
The conversion law is commonly referred to as the A
Law.
F(x) = Sgn(x) [ 1 + 10glO (AIX I)].
1 + 10910A

1I A :0; Ixl :0; 1

where: x = the input signal
Sgn(x) = sign of the input signal
A = 87.6 (defined by GGID)

The Godec provides a piecewise linear approximation of the logarithmic law through 13 segments.
Each segment is made of 16 steps with the exception of the first segment, which has 32 steps. In adjacent segments the step sizes are in a ratio of two to
one. Within each segment, the step size is constant.
The output levels are midway between the corresponding decision levels. The output levels Yn are
related to the input levels xn by the expression:
Yn

F(x) = Sgn(x) [

Alxl
].
1+log10 A

Xn -1

+ Xn

• 0

< n :0;

128

0:0; Ixl :0; 1/A

270158-8

Figure 10. Codec Transfer Characteristic

5-25

infef

2911A·1

Theoretical A·Law-Positive Input Values (for Negative Input Values, Invert Bit 1)
1
Segment
Number

No. of Steps
x Step Size

Value at
Segment
End Points

Decision
Value
Numbern

Value xn(l)

A096(3)

(128)

(4096)

127

3968

I
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5
Decision

PCM Word(4)

Normalized
Value
at Decoder
Output Yn(S)

Decoder
Output
Value
Number

Bit Number

12345678
·11111111

16x 128

113

2176

112

2048

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1088

1024

I
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544

512

I
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272

256

I
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(Note 2)

1 1 1 1 0000
2048
6

16x64

(Note 2)

11100000
1024
5

16x32

(Note 2)

11010000
512
4

16x 16

(Note 2)

11000000
256
3

16x8

136

128

I
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I

(Note 2)

10110000
128
2

16x4

I
I
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(Note 2)

10100000
64
1

32 x 2

(Note 2)

10000000

4032

128

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2112
I
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1056
I
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528
I
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264
I
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132
I
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66
I
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1

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113

I
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97

I
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81

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65

I
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49

I
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33

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1

NOTES:
1. 4096 normalized value units correspond to the value of the on-chip voltage reference.
2. The PCM word correspon'ding to positive input values between two successive decision values numbered nand n + '1
(see column 4) is (128 + n) expressed as a binary number.
3. X128 is a virtual decision value.
4. The PCM word on the highways is the same as the one shown in column 6, with the even order bits inverted, The 2911 A
provides for the inversion of the even order bits on both the send and receive sections.
5, The voltage output on the VFR lead is equal to the normalized value given in the table, augmented by an offset The
offset value is approximately 15 mV.

5-26

inter

2911A-1

APPLICATIONS

r------....,

Holding Capacitor

I
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I

I
I

For an 8 KHz sampling system the transmit holding
capacitor CAPx should be 2000 pF ±20%.

I
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CODEC

500Q

CAP1x

CAPl(

1SOKl1

R,
470 Kn

-= GRDA

I
I

2000 pF

150 KII :

.3"F

AUTO

VFx

R,
330fl

r-------------,
VFx

r---

L __ _

L2"~~~ __ _.J

270158-10

Figure 12. Circuit Interface-With
External Auto Zero

,
I
1

2 mV OFFSET

L-:hROA -- - ------ J

Auto Zero
The 2911 A contains a transparent on-chip auto zero
plus a device pin for implementing a sign-bit driven
external auto zero feedback loop. The on-chip auto
zero reduces the input offset voltage of the encoder
(VFx) to less than 3 mV. For most telephony applications, this input offset is perfectly acceptable, since it
insures the encoder is biased in the lower 25% of
the first segment.

270158-9

Figure 11. Circuit Interface-Without
External Auto Zero

Filters Interface
The filters may be interfaced as shown in the circuit
interface diagrams. Note that the output pulse
stream is of the non-return-to-zero type and hence
requires the (sin x)/x correction provided by the
2912A filter.

Where lower input offset is required the external
auto zero loop may be used to bias the encoder exactly at the zero crossing point. The consequence of
the external auto zero loop, aside from extra components, is the addition of the dithering auto-zero signal to the input signal, resulting in slightly higher idle
channel noise (approximately 2 dB) than when the
external loop is not used. Consequently, where the
application permits, it is recommended that the external auto zero loop not be used. When not used,
the AUTO pin should float.

DX Buffering
For higher drive capability or increased system reliability it may be desirable that the Ox output of a
group of Codecs be buffered from the system PCM
bus with an external three-state or open collector
buffers. A buffer ca.!!.!>e enabled with the appropriate
Codec generated TSx signal or signals. TSx signal
may also be used to activate external zero code suppression logic, since the occurrence of an active
state of any TSx implies the existence of PCM voice
bits (as opposed to transparent data bits) on the
bus.

The circuit interface with external auto zero drawing
shows a possible connection between VFx and
AUTO leads with the recommended values of
C1 = 0.3 p,F, R1 = 150 K.o, R2 = 330.0, and
R3 =470 K.o.

5-27

intJ

2911A-1

ABSOLUTE MAXIMUM RATINGS*

NOTICE: This is a production data sheet The specifications are subject to change without notice.

Temperature Under Bias ......... -1 O·C to + 80·C

Storage Temperature .......... - 6S·C to + lS0·C
All Input or Output Voltages with
Respectto )JBB ................ - 0.3V to + 20V
Vee, Voo, GRDA, and GRDA with Respect
toVBB ....................... -0.3Vto +20V
Power Dissipation ........................ 1.3SW

D.C. CHARACTERISTICS
TA = O·Cto +70·C, Voo = +12V ±S%, Vee = +SV ±S%, VBB = -SV ±S%, GRDA = OV, GRDD = OV,
unless otherwise specified.
DIGITAL INTERFACE
Symbol

Limits

Parameter
Min

Typ(1)

Unit

Test Conditions

Max

< VIL

IlL

Low Level Input Current

,...A

VIN

IIH

High Level Input Current

,...A

VIN> VIH

VIL

Input Low Voltage

0.6

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

2.2
0.4

2.4

Ox, IOL = 4.0 mA
TSx, IOL = 3.2 mA, open drain
PDN, IOL = 1.6 mA, open drain

Ox, IOH= lS mA

ANALOG INTERFACE
Symbol

Limits

Parameter
Min

Typ(1)

Max

Unit

Test Conditions

ZAI

Input Impedance when
Sampling, VF~

12S

300

SOO

In series with CAPx to GRDA,
-3.1V < VIN < 3.1V

ZAO

Small Signal Output
Impedance, VFR

100

180 '

300

-3.1V

VOR

Output Offset Voltage at VFR

-so

Minimum code to DR

VIX

Input Offset Voltage at VFx

-S

Minimum positive code
produced at Ox

VOL:

Output Low Voltage at AUTO

VBB

(VBB +2)

400 KO to GRDA

VOH

Output High Voltage at AUTO (Vee -2)

Vee

400 KO to GRDA

S-28

< VOUT < 3.1V

2911A-1

D.C. CHARACTERISTICS
TA = O°Cto + 70°C, VOO = + 12V ±5%, VCC = +5V ±5%, VSS = -5V ±5%, GRDA = OV, GRDD = OV,
unless otherwise specified. (Continued)
POWER DISSIPATION
Symbol

Limits

Parameter

Typ(1)

Min

Unit

Test Conditions

Max

1000

Standby Current

0.7

1.1

Icco

Standby Current

4.0

7.0

Isso

Standby Current

1.0

2.5

1001

Operating Current

Icci

Operating Current

ISSI

Operating Current

4.0

6.0

Auto Output = Open
Clock Frequency = 2.048 MHZ

NOTE:

1. Typical values are for TA

25°C and nominal power supply values.

A.C. CHARACTERISTICS
TA = O°C to + 70°C, VOO = + 12V ±5%, VCC = +5V ±5%, VSS = -5V ±5%, GRDA = OV, GRDD = OV,
unless otherwise specified.
TRANSMISSION
Symbol

Limits

Parameter
Min

SID

aGv
aGT
Nlc
HD

IMD1
IMD2

Typ(1)

Unit

Test Conditions

Max

Signal to Total Distortion Ratio. 37
CCITT G. 712 Method 2

Signal level 0 dBmO to
-30 dBmO

(Half Channel)

Signal level to -40 dBmO

Signal level to -45 dBmO

dB
dB
dB

VFx = 1.02 KHz, sinusoid
-40 dBmO ~ VFx ~ +3 dBmO
-50 dBmO ~ VFx < -40 dBmO
- 55 dBmO ~ VFx < - 50 dBmO

2911A
Gain Tracking Deviation
Half Channel(3)
Reference Level -10 dBmO
aG Variation with Supplies
Half Channel
aG Variation with
Temperature Half Channel
Idle Channel Noise
Harmonic Distortion
(2nd or 3rd)

±0.25
±0.60
±1.5

±0.30
±0.70
±1.8

±0.0002 ±0.0004 dB/mY -40 dBmO
±0.0004 ±0.0008 dB/mY -50 dBmO
±0.001
±0.002

±0.002
±0.005

-85

-78

-48

-44

Intermodulation Distortion
G.712(7.1)
G.712(7.2)

-45
-50

5-29

dBrC -40 dBmO
dBrC -50 dBmO

~
~
~
~

VFx
VFx

< -40 dBmO

VFx
VFx

< -40 dBmO

+3 dBmO
+3 dBmO

dBmOp Quiet Code. (Note 2)
dB

VFx ~ 1.02 KHz, 0 dBmO;
measured at decoder output VFR

dB
CCITT G.712
dBmO Two Tone Method

infef

2911A·1

A.C. CHARACTERISTICS
TA = O°Cto + 70°C, VDD = +12V ±5%, Vee
unless otherwise specified. (Continued)

+5V ±5%, VSS

-5V ±5%, GRDA

OV, GRDD

OV,

GAIN AND DYNAMIC RANGE
Symbol

Parameter
Min

DmW

Digital Milliwatt Response

DmWT

DmWo Variation with
Temperature

DmWs

DmWo Variation
with Supplies

AIR

Input Dynamic Range

AIRT

5.58

Limits
Typ(1)

Unit

Test Conditions

Max

5.66

5.78

dBm

-0.001

-0.002

dBI"C

Relative to 23°C(4)

±0.07

Supplies ±5%(4)

2.243

VRMS

Input Dynamic Range
vs Temperature

-0.5

mVRMSI"C

AIRS

Input Dynamic Range
vs Supplies

±18

mVRMS

AOR

Output Dynamic Range,
VFR

2.20

VRMS

AORT

AOR Variation with
Temperature

-0.5

mVRMSI"C

AORS

AOR Variation with Supplies

±18

mVRMS

2.183

2.14

2.213

2.17

23°C, nominal supplies(4)

Using D.C. and A.C. tests(S)
23°C, nominal supplies
Relative to 23°C
Supplies ± 5%
23°C, Nominal Supplies
Relative to 23°C
Supplies ±5%

SUPPLY REJECTION AND CROSSTALK
Symbol

Parameter
Min

Limits
Typ(1)

Unit

Test Conditions

Max

PSRR1

VDD Power Supply Rejection Ratio

decoder alone(6)

PSRR2

Vss Power Supply Rejection Ratio

decoder alone(6)

PSRR3

Vee Power Supply Rejection Ratio

decoder alone(6)

PSRR4

VDD Power Supply Rejection Ratio

encoder alone(7)

.PSRRs

Vss Power Supply Rejection Ratio

encoder alone(7)

PSRR6

Vee Power Supply Rejection Ratio

encoder alone(7)

CTR

Crosstalk Isolation, Receive Side

(Note 8)

CTT

Crosstalk Isolation, Transmit Side

(Note 9)

CAPX

Input Sample and Hold Capacitor

1600

2000

2400

NOTES:
1. Typical values are for TA = 2Soe and nominal power supply values.
2. If the external auto zero is used NIC has a typical value of - 76 dSmO.
3. Tested and guaranteed at 23°e, nominal supplies.
.
4. DR of Device Under Test (D.U.T.) driven with repetitive digital word sequence specified in eCITT recommendation G.711.
Measurement made at VFR output.
5. With the D.C. method the positive and negative clipping levelS are measured and AIR is calculated. With the A.C. method
a sinusoidal input Signal to VFx is used where AIR is measured directly.
6. D.U.T. decoder; impose 200 mVpp, 1.02 KHz on appropriate supply; measurement made at decoder output; decoder in
idle channel conditions.
7. D.U.T. encoder, impose 200 mVpp, 1.02 KHz on appropriate supply; meaurement made at encoder output; encoder in idle
channel conditions.
8. VFx of D.U.T encoder = 1.02 KHz, 0 dSmO. Decoder under quiet channel conditions; measurements made at decoder
output.
9. VFx = 0 Vrms. Decoder = 1.02 KHz, 0 dSmO. Encoder under quiet channel conditions; measurement made at encoder
output.
5-30

inter

2911A-1

60
(dB) •

.1.1

+1
+.7

r---~~----~~----------------------~~l~~l
~.55
-SO
-40
+3
dBmO
-.7
-1

ccm 0.712

-1.8

-3

270158-11

Figure 13. Tracking Deviation (t..G) (Half Channel)

;37~_ _ _......;29;,;,I;..IA-~IS;;..P;;.EC~_ _ _ _....

-i
-r1 bii~

REFERENCE

AUTO
ZERO

t---y--"
. Dx
SAMPLE
AND HOLD
ANDDAC

f-.I COMPARATOR l-.f

1
'L..-

"'1\

rE
c

U'1

..... n

.....

RECEIVE
SECTION
GSR-.............,

a .TSxlDCLKx:

I..

SIGx/ASEL

FSx

CLKx

CD
Co)

III

::2

CONTROL
LOGIC

_ __
REFERENCE

t V..f

Vee

~LOOP

DIGITAL
TO
ANALOG
CONTROL
LOGIC

I--

f
GRDD

tt=~SEL

...................•:....... ............................................................

SAMPLE
AND HOLD
AND DAC

DCLKR

INPUT
'REGISTER

L.---r--a-SIGR

GRDA

F5R

:.:-:.:.:.:.:.:.:-:.:•..:-:.:.:.:...:.:.:.:.:.•.:•••.•:':';~:~I':~:.:~:.;.:.:.:.:~:.:.:.:.:.:.:.:.

FILTER

PWRO+~-+--t--~l

PWRO-~~~~

CONTROL
SECTION

t5::: H W"~ I'~

iii'

OUTPUT
REGISTER

I-

[:::,,:::,::::::::::::::::::::::::::::::,,:::::::.;.;.;.:.;.::::::;:::::::;:::::;:;::::::;;:;:;:::;.:.;.:.;.;.;.;.;.:;;.:.:.;.;.:.;.;.;.:.:.;.;.;.:.;;;;;.",.;.;.:.;.;.;.:.;.:.;.:.;.:.;.;.;.:.;.:.;.:.;.:.;.;.; :.;.;.;.;....... ;.;.;:;:;:.;;.;.;:;:.:.:.:.;

ANALOG
TO
DIGITAL
CONTROL
LOGIC

SUCCESSIVE
APPRDXIMATION
REGISTER

'--,r----'

iil
~

1. .---------.

CUTESTPOINTS< 2.0

V-

O.&~

_0.&

210629-17
A.C. Testing: Inputs are driven at 2.4V for a Logic "1" and 0.45V
for Logic "0". Timing measurements are made at 2.0V for a Logic
"I" and 0.8V for a Logic "0".

5-66

2916/2917
HMOS COMBINED SINGLE CHIP PCM CODEC AND FILTER

•
•
•
•

Timing Mode for Standard
• Fixed
32-Channel Systems: 2.048 MHz

2916 p.-Law, 2.048 MHz Master Clock
2917 A-Law, 2.048 MHz Master Clock

Master Clock

New 16-Pin Package for Higher
Linecard Density

Power HMOS-E Technology
• -Low5 mW
Typical Power Down

AT&T 03/04 and CCITT Compatible

•

Variable Timing Mode for Flexible
Digital Interlace: Supports Data Rates
from 64 KB to 2.048 MB

•

Fully Differential Internal Architecture
Enhances Noise Immunity

-140 mW Typical Operating
Chip Auto Zero, Sample and Hold,
• On
and Precision Voltage References
with Direct Mode Intel
• Compatible
2910A, 2911A, and 2912A Designs

The Intel 2916 and 2917 are limited feature versions of Intel's 2913 and 2914 combination co dec/filter chips.
They are fully integrated PCM codecs with transmit/receive filters fabricated in a highly reliable and proven
N-channel HMOS silicon gate technology (HMOS-E). These devices provide the functions that were formerly
provided by two complex chips (2910A or 2911A and 2912A). Besides the higher level of integration, the
performance of the 2916 and 2917 is superior to that of the separate devices.
The primary applications for the 2916 and 2917 are in telephone systems:
• Switching-Digital PBX's and Central Office Switching Systems
• Subscriber Instruments-Digital Handsets and Office Workstations
Other possible applications can be found where the wide dynamic range (78 dB) and minimum conversion time
.
(125 p.s) are required for analog to digital interface functions:
• High Speed Modems
• Voice Store and Forward

• Secure Communications
• Digital Echo Cancellation

•

vcc

VBB
PWRO+

GSx

PWRO-

VFX I -

PiiN

GRDA

DCLK R

TSXIDClKX

FS R

FSx

GRDD

ClK
270156-1

Figure 1. Pin Configuration

5-67

September 1990
Order Number: 270156-002

inter

2916/2917

XMIT .
SECTION'

GS,

AUTO

--11----..,

ZERO

YFxl-

SAMPLE

SUCCESSIVE

COMPARATOR

AND HOLD
AND OAC

APPROXIMATION
REGISTER

.
OUTPUT
REOtS'E"

.ftxlDCLKx

ANALOG

TO
DIGITAL
CONTROL
LOGIC

1 - - - - - - - - - ' - - -....- 1••,
141------------t.-'cLK

"CV
SECTION

IUFFER
PWAO+

--++-t---,

SAMPLE

AND HOLD
AND OAe

PW"O-

_-+~

__--'

Vee.

v..

GRDO

GRDA

Fs..

270156-2

Figure 2. Block Diagram

Table 1. Pin Names
Name

Description

Name

Description

Vee

Power (-5V)

GSx

Transmit Gain Control

PWRO+, PWRO-

Power Amplifier Outputs

VFxl -

Analog Input

PDN

Power Down Select

GRDA

Analog Ground

DClKR

Receive Variable Data Clock

TSx

Timeslot Strobe/Buffer Enable

Receive PCM Input

DClKx

Transmit Variable Data Clock

FSR

Receive Frame
Synchronization Clock

GRDD

Digital Ground

Vee

Power (+5V)

5-68

Transmit PCM Output

FSx

Transmit Frame
Synchronization Clock

ClK

MasterClock

inter

2916/2917

Table 2. Pin Description
Symbol

Function

Vss

Most negative supply, input voltage is - 5 volts ± 5%.

PWRO+

Non-inverting output of power amplifier. Can drive transformer hybrids or high impedance loads
directly in either a differential or single ended configuration.

PWRO-

Inverting output of power amplifier. Functionally identical and complementary to PWRO +.

PDN

Power down select. When PDN is TTL high, the device is active. When low, the device is
powered down.

DClKR

Selects the fixed or variable data rate mode. When DCLI35dB

NotSpec'd

> 35dB

Trim Using Pot Necessary

Precision Resistors
Eliminate Trim Req.

Direct

Yes

Timeslot Assign

Yes

1 KHz
> 10 KHz

Gain Setting
Operating Modes

5mW

38-40
1.536, 1.544, 2.048 Mbps

-Variable
Companding Law

33mW

On-Chip VREF
ICN -

Half Channel Improvement

15 dBrncO Transmit
11 dBrncO Receive

SID -

Half Channel Improvement

See Data Sheet

See Section 2.0

GT - Half Channel Improvement

See Data Sheet

See Section 2.0

PDN Pin

Frame Sync Removal or PDN Pin

Signalling

2910-8th Bit

2914-8th Bit

Auto Zero

External

Internal

S&HCaps

External Transmit
Internal Receive

Internal

Test Modes

None.

Design Tests
Manufacturing Test
On-Line Operational Tests

Resistive Ladder

Capacitive Charge Redistribution
Ladder

Power Down (Standby)

Encoder Implementation
Filter/Gain Trim

Fuse Blowing

5-91

± 0.2 dB

Fuse Blowing

± 0.04 dB

inter

AP-142

XMIT
SECTION
AUTO
ZERO

0,
VFxl+

SAMPLE
AND HOLD

SUCCESSIVE
APPROXIMATION
REGISTER

COMPARATOR

AND OAC

VFXI-

OUTPUT
REGISTER

TSXfOCLKIt
SIGx/ASEL

as, - - t - - - - - '
ANALOG
TO
DIGITAL
CONTROL

I----------+----+_-FS,

L_L~O;QI:e_t---_-------1--'CLKX

Rev
SECTION
ClKS£l

I'I!l'I
LOOP

PWRO+_-+-..--..,

DCLKA

PWRO-

--t-+--..J

'-----it---SlaR

Vee

Ve,

GADO

ORDA

210314-2

(a) Combo chip Block Diagram
VBB
PWRO +, PWROGSR
PDN
CLKSEL
LOOP
SIGR
DCLKR
DR
FSR
GRDD
Vee

Power (-5V)
Power Amplifier Outputs
Rec.eive Gain Control
Power Down Select
Master Clock Frequency
Select
Analog Loop Back
Receive Signaling Bit Output
Receive Variable Data Clock
Receive PCM Input
Receive Frame
Synchronization Clock
Digital Ground
Power (+5V)

GSx
VFxl-, VFxl +
GRDA
NC
SIGx

Transmit Gain Control
Analog Inputs
Analog Ground
No Connect
Transmit Signaling Input

ASEL
TSx
DCLKx
Ox
FSx

IL- or A-law Select
Timeslot Strobe/Buffer Enable
Transmit Variable Data Clock
Transmit PCM Output
Transmit Frame
Synchronization Clock
Transmit Master Clock
Receive Master Clock

CLKx
CLKR

(b) Combochip Pin Names
Figure 2. Block Diagram of 2913/14 Combochip

5-92

intJ

AP-142

shows the significant improvement in the combochip
both in performance levels and system flexibility.

Table 3. 2914 Factors which Increase Linecard
Manufacturing Yields and Efficiency

• Higher Reliability
-Fewer connections and components
-More integrated packaging
-More margin to specs
-Lower power
-NMOS proven process
-Less sensitive to parameter variations

2.0 DESIGN CONSIDERATIONS
The key point with the 2913/14 is that it will result in a
linecard that performs better and costs less than any
two-chip codec/filter solution. The lower cost results
from many factors, as seen in Table 2. Both direct replacement costs and less tangible design and manufacturing time savings combine to yield lower recurring
and nonrecurring costs. As an example, the wider margins to transmission specs and the higher power supply
rejection ratios of the 2913/14 will both shorten the
design time needed to build and test the linecard prototype and reduce the reject rate on the manufacturing
line.

• Fewer Manufacturing Steps
-No gain trimming
-On chip VREF
-Wide power supply tolerance
-On chip test modes
-Wide margins to spec

Table 2. 2913/14 Factors which Lower the Cost
of Linecard Design and Manufacturing

• Lower LSI Cost (2914 vs. 2910/11
2912)

+
Table 4. Design Factors for 2914 which Reduce
Linecard PCB Area

• Fewer External Components
•
•
•
•

Less Board Area
Shorter Design/Prototype Cycle
Better Yields/Higher Reliability
Lower Power/Higher Density

• Integrated Packaging
-2914 vs. 2910/11 + 2912
= 1/3 board area
-2913 takes even less space
• Fewer Interconnects/Components
-Codec/filter combined
-On-chip reference voltage
-On-chip auto zero
-On-chip capacitors
-No gain trim components
-No voltage regulators

Part of the recurring cost of linecard production is the
efficiency of the manufacturing line in turning out each
board. This is measured in both parts cost and time.
Average manufacturing time is strongly effected by the
line yield, i.e., the reject rate reliability. Alinecard using the 2913/14 has many labor-saving features, which
also increases the reliability of the manufacturing process. Some of these features are detailed in Table 3.
The combination of fewer parameters to trim (gain, reference voltage, etc.), tolerance to wider power supply
variations, and on-chip test modes make the linecard
very manufacturable compared to first-generation designs.

• Efficient Layout (Facilitates Auto Insertion)
-Analog/digital sections separated on
chip
-Digital traces can cross under chip
-Two power supplies only
-Low power/high density

Probably the most obvious improvement in linecard design based around the 2913/14 is the reduction in linecard PCB area needed compared to two-chip designs.
The combination of the codec and filter into a single
package alone reduced the LSI area by one-third. Table
4 shows many of the other ways in which board area is
conserved. In general, it reduces to fewer components,
more on-chip features, and layout of the chip resulting
in an efficient board layout which neatly separates the
analog and digital signals both inside the chip and on
the board.

5-93

AP-142

Table 5 2913/14 Operating Mode Options Add Flexibility to Linecard Design
Option

Results of Mode Selection

Mode Control Pins

2914 (24 Pin)

+ Signalling

2913 (20 Pin)
I
I A-Law/,...-Law, no Signalling

Companding Law

SIGX/ASEL

A-Law or ,...-Law

Power Down

PDN

Transmit & Receive Side Go To Standby Power (5 mW)

FSx & FSR Removed

Same (12 mW)

FSxRemoved

Transmit Side Goes to Standby (110 mW)

FSR Removed

Receive Side Goes to Standby (70 mW)

- Vee/GRDDlVss
DCLKR = Vss

1.536/1.544/2.048 Mbps in Fixed Data Rate Mode

- Vee/GRDDlVss
DCLKs = Clock

Variable Data Rate Mode from 64 Kbps to 2.048 Mbps,
No Signalling

Data Rate

Test Modes

LOOP - Vee
PDN

Vss

DR - Vss

Implements Analog Loopback

I No Loopback Capability

Provides Access to Transmit Codec Through ASEL and TSX
Pins
.
Provides Access to RCV Filter Input at DCLKR and Transmit
Filter Outputs at ASEL and TSX Pins

Many of the factors discussed-which result in efficient, cost-effective linecard designs-are discussed in
more detail both in the 2913/14 data sheet and in the
following sections of this note.

2.1 Operating and Test Mode
Selection
A key to designing with the 2913/14 combo is the wide
range of options available in configuring, either with
strap options or in real time, the different modes of
operation. The 2913 combochip (20 pins) is specifically
aimed at synchronous switching systems (remote concentrators, PABXs, central offices) where small package size is especially desirable. The 2914 combochip (24
pins) has additional features which are most suitable for
applications requiring 8th-bit signalling, asynchronous
operation, and remote testing of transmission paths
(e.g., channel banks). Once the specific device is selected, there is a wide range of operating modes to use in
the card design, as seen in Table 5. This table lists the
optional parameters and the pins which control the operating mode. The result of selecting a mode is listed for
both the 2913 and 2914.

without significant system timing, control, or software
modifications. To this end, two distinct user-selectable
. timing modes are possible with the combochip. For
purposes of discussion, these are designated (a) fixed
data rate timing (FDRT) and (b) variable data rate timing (VDRT);
FDRT is identical to the 2910/2911 codec timing in
which a single high-speed clock serves both as master
clock for the codec/filter internal conversion/filtering
functions and as PCM bit clock for the high-speed serial PCM data bus over. which the combochip transmits
and receives its' digitized voice code words. In this
mode, PCM bit rates are necessarily confined to one of
three distinct frequencies (1.536 MHz, 1.544 MHz, or
2.048 MHz). Many recently designed systems employ
this type of timing which is sometimes referred to as
burst-mode timing because of the low duty cycle of
each timeslot (i.e., channel) on the time division multiplexed PCM bus. It is possible for up to 32 active combochips to share the same serial PCM,bus with FDRT.
VDRT (sometimes referred to as shift register timing),
by comparison, utilizes one high-speed master clock for
the combochip internal conversion/filtering functions
and a separate, variable frequency, clock as the PCM
bit clock for the serial PCM data bus. Because the serial
PCM data rate is independent of internal conversion
timing, there is considerable flexibility in the choice of
PCM data rate. In this mode the master clock is permitted to be 1.536 MHz, 1.544 MHz, or 2.048 MHz,
while the bit clock can be any rate between 64 KHz and
2.048 MHz. In this mode it is possible to have a dedicated serial bus for each combochip or to share a single
serial PCM bus among as many as' 32 active combochips.

The purpose of offering these options is to ensure that
the 2913/14 combo will accommodate any existing
linecard design with architectural transparency. At the
same time, features were designed in to facilitate design
and manufacturing testing to reduce overall cost of development and production.

2.2 Data Rate Modes
Any rapid conversion scenario presumes that the combochip will fit existing system architectures (retrofit)
5-94

inter

AP-142

Thus, the two predominant timing configurations of
present system architectures are served by the same device, allowing, in many cases, linecard redesign without
modification of any common system hardware or software. Additional details relating to the design of systems using either mode are found in section 3.0.

have its effect on line circuit costs even though the system transmission specifications may not reflect the improved performance margin.
Half channel measurements have been made of the
transmission parameters-gain tracking (GT), signal to
distortion ratio (SID), and idle channel noise (lCN).

2.3 Margin to Performance
Specifications

Gain Tracking-Figure 3 shows the gain tracking data
for both the transmit and receive sides of the combo
using both sine wave testing (CClrr G712.11 Method
2) and white noise testing (CClrr G712.11 Method I).
The data shows a performance very nearly equal to the
theoretically best. achievable using both test techniques.
End to end measurements, although not spec'd, also
show a corresponding good performance with errors
less than or equal to the sum of the half channel values.

The combochip benefits from design, manufacturing,
and test experience with first-generation PCM products
on the part of the system manufacturer, component
suppliers, and test equipment suppliers. The sub-millivolt PCM measurement levels and tens of microvolts
accuracy requirements on the lowest signal measurements often result in tester correlation problems, yield
losses, and excess costs for system and PCM component manufacturers alike. Thus additional performance
margin built into the PCM components themselves will

Signal to Distortion Ratio-This is a measure of the
system linearity and the accuracy in implementing the
companding codes. Figure 4 shows the excellent perfor-

Gain Tracking Error Versus Signal Level
2914 Combo AID
Sinusoidal Test (CCITTG712.11 Method 2)

Gain Tracking Error Versus Signal Level
2914 Combo DIA
Sinusoidal Test (CCITT G712.11 Method 2)

a: 1
o
a:

1
L-- 1
I

..,ffi

.Ci
.

~--I---I---I---I I ~~r

-55-50

-'\O----------p+3
I--~
'dBmO
I
,
1
,
I
,
I

,
,I

I
I
---,
1
- - - - - - - - - - - 1 INPUT
I U
1
1
1 1 LEVEL
-55-SO -40----------·0+3
1--"';
dBmo

-.5

~ -1

I
I

1
1
I

-2

210314-4

210314-3

Gain Tracking Error Versus Signal Level
2914 Combo AID
White Noise Test (CCITT G712.11 Method 1)

Gain Tracking Error Versus Signal Level
2914ComboD/A
White Noise Test (CCITT G712.11 Method 1)

1
1
1

~ .5

~ 0

-55 -so

-1

. -40

r-----------I

II:

~ 0
;;;
~ -.5
~

"LEVEL
0 +3
ldBmO

I-~

,
1

-2

-1

- - - - - - - - ______ 1

~ .5
w

INPUT

~ -.5
~

'-,

--I_ _._ _ _ _ _ _ _ _ _ _ _ J1

;;;

1
I
1

INPUT
1 ILEVEL
-55 -50 -40
0 +3
r - - - - - - - - - ----idBmO
I
I

,oJ

,
1

-2

210314-6

210314-5

Figure 3. 2914 Half Channel Gain Tracking Performance Measurements
for Both Sine and Noise Testing

5-95

•

AP-142

...

0'40
~

~3O

AID SINEWAVE TEST

~-D-I-A-S-IN-E-W-AV-E-T-E-ST----,

o
1;;20
is
....
;:!

_45 _40 -35 -30 -25

-15

oL-----r--r-,--,--.-----r-----r~--~
-45 _40 -35 -30 -25

-5

INPUT LEVEL (dBmO)

-15

-5

INPUT LEVEL (dBmO)

210314-7

210314-8

iii

~ 40

/:~'~'nn

~
a:

Z30

Iii

FULL CHANNEL SPEC-

50 -45 _40 -35 -30 -25

-15

~ 0~-50~-_4r5--_4rO---3r5--'3-0--'25------TI5------r5L,Or-'5-

-5

INPUT LEVEL (dBmO)

210314-'9

210314-10

Figure 4. 2914 Half Channel Signal to Distortion Ratio (SID) Performance Measurements
for Both Sine and Noise Testing
. mance of the 2914 for both the transmit (AID) and
receive (DI A) channels using sine wave and noise testing. The margin is greater than 3 dB above. the half
channel spec which means that a larger error budget is
available to the rest of the channel.

Power Supply Rejection-Circuit innovation in the internal combochip design has resulted in significant improvements in power supply rejection in the 5 to 50
KHz range (Figure 7), and it is this frequency band
which usually contains the bulk of the switching regulator noise. These higher frequencies, outside the audio
range as they are, are not objectionable or even detectable in the transmit direction except to the extent that
they alias into the. audio range as a result of internal
sampling processes in the transmit filter and AID converter. Sampling techniques in the combochip minimize
this aliasing. In the receive direction, excess high frequency noise which propagates onto the subscriber loop
can interfere with signals in adjacent wires and is thus
objectionable even without aliasing. The symmetrical
true differential analog outputs of the combochip are an
improvement from earlier designs which failed to maintain true power supply symmetry through the output
amplifiers. Not only does the differential design improve transmission performance, but it also reduces the
need for power supply bypass capacitors, thereby saving component cost on the Iinecard.

Statistical Analysis-A statistical analysis of G.T. and
SID measurements over many devices shows a very
tight distribution, as seen in Figure 5. There are several
consequences resulting from this highly desirable distribution: (l) the device performance is controllable, resulting in high yields, (2) the device circuit design is
tolerant of normal process variations, thereby ensuring
predictable production yields and high reliability, and
(3) understanding of the circuit design and process fundamentals is clearly demonstrated-largely as a result
of previous telephony experience with the Intel NMOS
process.
Idle Channel Noise-The third transmission parameter
is idle channel noise (ICN). Figure 6 gives half channel
ICN measurements which show a substantial margin to
specification.

5-96

intJ

AP-142

iii'

:!!.
II:

ffi

5i -.5
II:

~ -1
C
CI

L _

==-

-55 -50

:!!.40

1
I
1

I~ENVELOPE

II:

MINIMAX

ii
II:

L ________ ": INPUT
LEVEL
I

~ 3D

;:::

1
1
1

-49.---------1 0 +3

1---

MINIMAX'
lENVELOPE

AT&T SPEC. TA. 64
2914 COMBOCHIP
D/A SINEWAVE TEST

0
;; 20

idBmO

...0

1
I
I

;:!
0

5 10'

-2

210314-11

iii

0
-45 -40 -35 -3D -25

-15

-5

INPUT LEVEL (dBmO)

210314-12

Figure 5. Statistical Analysis of Transmission Performance Showing
Tight Distribution Over Many Devices

I
I

Weighting

ICN

AID

C Message

15 dBrnCO

D/A

C Message

11 dBrnCO

The concern for linecard power consumption and dissipation is related both to the cost of providing power
and to the system density problem involving convection
heat removal from the linecards. Consequently, much
recent line circuit development activity centers on elimination of the inefficient resistive line current feed both
by current limiting in short loops and by more exotic
and expensive per-line dc-de converters. For both present-generation designs and cost-reduction redesigns,
the typical combochip dissipation of 140 mW
active/5 mW standby will allow system board packing
density improvements and power supply cost reductions.

Figure 6. 2914 Idle Channel Noise (ICN)
Measurements
Autozero-The autozero circuit is contained complete·
lyon-chip. It automatically centers the signal/noise distribution at the encoder input. This ensures minimal
ICN due to bit toggling and also maintains maximum
sensitivity to the AC signals of interest.

A closer look at the effect ofloading (duty cycle) on the
average power dissipation of a combochip is given in
Table 6. Typical loading percents run as low as 5% for
very large switching systems (thousands of lines) up to
100% in nonswitching applications such as channel
banks. Clearly, the average power dissipation in a typical switching system is below 35 mW which facilitates
board packing density and cost of power considerations.

2.4 Power Conservation
Figure 8 illustrates typical power consumption and office equipment dissipation for a resistive line biasing
arrangement (with no loop current limiting) and for the
per-line PCM components. It can be seen that overall
line circuit power consumption and dissipation are
strong functions of subscriber loop resistance, and are
dominated by line biasing current regardless of loop
length. It can also be seen that the combochip achieves
significant reductions in PCM component contributions relative to both the 29l0A12912A and
291012912. Present residential traffic characteristics
are such that the PCM components are active less than
10% of the time, and in its low-power standby state,
the combochip power dissipation drops to typically
5 mW as the line current (and dissipation) goes to its
background on-hook leakage level of typically a few
milliwatts(but for very leaky lines, as much as 50 m W 500mW).

Table 6. Typical Power Dissipation Per Line
Using 2914 Combochip

5-97

Duty
Cycle

Power
Dissipation

Central
Office

12mW

PABX

15%

25mW

Peak Hour
C.O.

50%

73mW

Channel
Bank

100%

140mW

inter

AP-142

POWER LINE
HARMONICS

VOICEBAND

SWITCHING REGULATOR

1000HZ

100

l0000HZ

-2ODB

-3ODB

-40DB

-50DB

210314-13

Figure 7.Wideband 2914 Power Supply Rejection Ratio (PSRR)

72 VOLT BATTERY
900 OHM FEED RESISTOR
NO CURRENT LIMITING

200

400

600

800

1000

1200

1400

1800

2000

SUBSCRIBER LOOP RESISTANCE (OHMS)

210314-14

Figure 8. Line Circuit Power Consumption and Dissipation Curves

5·98

intJ

AP-142

has previously been in the nominal insertion loss of the
PCM filter and in the uncertainty of the reference voltage of the codec. With this cumulative 0.15 dB uncertainty in the PCM components themselves, the system
manufacturer had no choice but to resort to the cost
and manufacturing complexity of the active trim. The
combochip, however, can be trimmed during its manufacture to a nominal tolerance of ± 0.04 dB which ineludes uncertainties in both the filter and codec voltage
reference functions. This leaves 0.21 dB uncertainty to
variations in the other line circuit elements and to temperature and supply variations.

2.5 Elimination of Gain Trim in the Line
Circuit
Four resistors-RI-R4 of Figure 9-on the transformer side of the PCM components are used to establish
appropriate transmission levels at the PCM components and are, at first glance, equivalent in the two cases. However, a significant reduction in linecard manufacturing costs associated with individual line trim (or
mop-up) is possible with the combochip. The need for
this trim is dictated by system gain contrast specifications which typically require that the line-to-line gain
variation shall not exceed 0.5 dB, which translates to
0.25 dB for each (transmit and receive) channel. Table
7 shows that the major portion of this gain variation

The variation in combochip gain with supply and temperature has also been improved to allow as low as

2910/11

PCMCOOEC

TRANSFORM_~E~R~t==:::;;-r=4

~;---,

l____________~~::~~~~~~~~~~~~~~~~~~~vCC

GRDD

VSS
GRDA
210314-15

(a) Line Circuit Utilizing Single-Chip PCM Codec and Filter

:=q
RING

C=::F,i::;====;=,I!

TRANSFORMER
r----,.-..,'~_-'t.

_
11

~
±

r--I---J

....

...3

i:!it§ oj~

~ I~... . . "
.£1:.
....
~u
...

g g g
u..a:

210314-16

(b) Line Circuit Using Combochip
Figure 9. Schematics of the CodeclFilter Function and the 2/4 Wire Hybrid Transformers

5-99

•

infef

AP-142

Table 7. Gain Trim Budget for Codec/Filter Functions
Device

2910
2912

2914

Manufacturing Uncertainty
(Initial)

Total

Variation' Budget
for Other Components

±0.1
±0.05
±0.15

±0.3 dB

OdB

±O.OB

±0.12 dB

±0.13dB

, ~Supplies

±0.1
±0.05
±0.15
±0.04
..

Assumes 0.5 dB end to end gain contrast specifications .

0.08 dB variation over supplies and temperature so that
more than half the system specification could be reserved for transformer, wiring, and resistor uncertainties. This possibility of using fixed precision gain trim
components and abandoning the active trim holds the
potential for simplification and· cost reduction of the
line board manufacturing process.
.

version, Switching, and Transmission using the Intel
291OA/2911A codec and 2912 PCM filter) also describes the basics of using the fixed data rate mode for
first-generation codecs and filters which is essentially
the same as for the 2913/14 second-generation combochip.

3.2 Variable Data Rate Mode

2.6 Power Up/Down Considerations
Power Supply Sequence-There are no requirements
for a particular sequence of powering up the combochip. All discussions of power up or power down timing assume that both Vee and VBB are present.
Power Up Delay-Upon application of power supplies,
or coming out of the standby power down mode, three
circuit time constants must be observed: (1) digital signal timing, (2) autozero timing, and (3) filter settling.
An internal timing circuit activates SIF" D x, and TS x
approximately two or three frames after power up. Until this time, SIGr is held low and the other two signals
are in a tri-state mode. During this time, SIGx will have
no effect on the PCM output.
Power Down Modes-These modes are described in detail in Table 3 of the 2913/14'data sheet except for a
fail-safe mode in case CLKx is interrupted. If this
should happen, both Dx and TSx go into the tri-state
mode until the clock is restored. This ensures the safety
of the PCM highway should the interrupted clock be a
local problem.

3.0 OPERATING MODES
There are three basic operating mode~ that are supported by the 2913/14: fixed data rate timing (FDRT), variable data rate timing (VDRT), and on-line testing.

The VDRT mode is described in some detail both in
section 2.2 and in the 2913/14 data sheet. This section
.focuses on two design aspects: (1) the advantage of
clocking data on the rising edges of the clock for transmit and receive data, respectively, and (2) making the
2913/14 transparent in previously designed systems (a
retrofit, cost reduction redesign).
Clock Timing-The 2913/14 is ideally set up to transmit and receive data, using the same clock, with no race
conditions or other marginal timing requirements. This
is accomplished by transmitting data on the rising edge
of the first clock pulse following the data enl!ble pulse
FSx and receiving data on the falling edge of the clock
which is directly in the middle of the Dx data pulse.
Several manufacturers use leading edge timing for both
transmit and receive requiring an inversion of the receive clock.
Figure 10 shows the transmit and receive clock and
data timing for an entire time slot of data. A closer look
at the timing functions is given in Figure 11 which
looks specifically at the first clock cycle after the trans. mit data enable FSx.
According to the 2913/14 data sheet, the frame syncl
data enable FSx must precede the clock (DCLKX) by
at least Ttsdx or nominally 15 ns for that clock pulse to
be recognized as the first clock pulse in the time slot. In
actuality, the 2914 will allow FSx to lag up to 80 ns the
DCLKx rising edge and recognize it as the first clock
pulse in a 2.048 MHz system.

3.1 Fixed Data Rate Mode
The FDRT mode is described in some detail in both
section 2.2 of this note and in the 2913/14 data sheet.
In addition, Intel Application Note AP-64 (Data Con-

Once FSx has reached VIH of about 2V, the Dx output
will remain in the tri-state high-impedance mode for

5-100

inter

AP-142

Transmit Timing

210314-17

Receive Timing

210314-18

NOTE:
All timing parameters referenced to VIH and VIL except tOON and tOFF which reference a high impedance state.

Figure 10. Variable Data Rate Timing for an Entire Time Slot

T don or about 34 ns longer. It then comes out of tristate
and will represent some data which is invalid until the
valid data is available TDDX or about 75 ns (100 ns
worst case) after the clock rising edge. This means there
is about 90 ns of invalid data after the tri-state mode.
At this point there is valid data on the Dx highway
that lasts for approximately one full clock cycle.
Since the Dx highway is tied directly to the Dr highway in digital loopback, the valid data above is now
available to the receive channel with some propagation
delay. The receiver is only interested in the data for
about a 50 ns (110 ns worst case) window centered
about the falling edge of the DCLKr clock which occurs about half a clock cycle from the FSr rising edge.
The window width is equal to the data set-up time.
Tdsf> plus the clock fall time, Tf, plus the data hold
time, Tdhr. Information at any other time on the Dr
highway falls into the DON'T CARE category.
Retrofitting the 2913/14--Several switching/transmission systems have been designed using first-generation
codecs which operate at data rates from 64 Kbps to
2.048 MBps. In addition, they may have been designed
using the rising clock edges for both transmit and receive data.

Other aspects of these older designs could be relative
skewing between the sync pulses (Data Enable) and the
clock pulses in such a way that the sync pulse occurs
after (Lags) the first clock pulse rising edge. All of these
conditions can be easily handled using the variable data
rate timing mode of the 2913/14 plus some simple externallogic. By the addition of this logic, the 2913/14
becomes transparent to the older design thereby allowing an upgrade in performance while having no impact
on backplane wiring or on system control hardware/
software. In addition, many of the features of the
2913/14 may be incorporated, such as the test modes,
which provide additional capabilities beyond those
available in the original design and at a lower cost.
The circuit diagram in Figure 12 shows the maximum
amount of additional random logic that could be necessary to make the 2913 or 2914 completely transparent
at the linecard level (no impact on backplane wiring or
timing). The inverter on DCLKR inverts all the receive
clocks for each linecard. This inverter is only needed if
(1) the transmit and receive clocks are inverted at the
systemlbackplane level (as opposed to the linecard level) and (2) the previous design used only rising (or falling) edges to clock the transmit/receive data.

5-101

AP-142

DIGITAL LOOP BACK
VARIABLE DATA RATE MODE

FlX.FlA.

"''''2v2v-----/

~_:'

Ttod.=15naec

-If-1
1

,,------

l i L A / ' " Tdd.=100 noec I

DCLK •• r

.........
~

~~~'~',II r---------.~'_+------------~
1

1
1

TRANSMIT DATA VALID

~~~:ATE

7i
1 I
1 1

Tdon"'35 nHC 1
I
DON'T
C/IRE

DON'T
CARE

I
I RECEIVE DATA

I
IDr

Tnt."""SO nteC

(SETUP TIME)

210314-19

Figure 11. Waveform Timing Diagrams for the 2913/14

3.3 On-Line Test Modes

4.1 Design/Prototype Testing

Two modes are available which permit maintenance
checking of the linecard up. to the SLIC/combochip
interface. including the PCM highways and time slot
interchanges. Tests include time slot-dependent error
checking. The two test modes are called "redundancy
testing"- and "analog loopback." These test modes are
described in detail in Section 4.3.

In the design of a linecard prototype or in the qualification of a device, it is often helpful to have direct access
to the internal nodes at key points in the LSI system.
Some manufacturers even dedicate pins specifically for
this function. The Intel 2913/14 approach was to reduce cost by using multifunction pins and smaller packages to achieve this goal. Measurements through these
multipurpose pins will typically yield full device capability against performance specifications, however these
measurements are not· included in the device specifications. This is done for two reasons: first, to save manufacturing cost by eliminating unnecessary tests and
specifications, and, second, more cost effective manufacturing test techniques are available, as discussed in
section 4.2.

4.0 MULTIMODE TEST CAPABILITIES
The 2913/14 was designed with every phase of design,
manufacturing, and operation taken into consideration.
In particular, several test modes have been implemented within the device with essentially no increase in the
package size or pin count. These test modes fall into
three categories: design/prototype tests, manufacturing
tests, and on-line operation tests; see Table 8.

5-102

inter

AP-142

2913 HOOKUP

2914 HOOKUP

Vaa
PWRO+

VCC
GSx

PWRO-

VFXI-

GSR
PDN

VFxl+
GRDA

DR C 8
r-FSR-( 9
GRDD C 10

,....!')

DCLKX

PWRO-

VFXIVFXI+

GRDA

ClKSEL

LOOP

TSXIDCLKX-

iDCLKR-L
DR
r-FSR-C
GRODe

I
I
I
I
I
I
I
I
I
I

NC
SIGXIASEL

SIG RL-

P-'

13p Ox
12P.FSX11
CLKX

P
'---

DCLKR

VCC
GSx

GSR
PDN

ASEL

ClKSEl
,--DCLKR

PWRO+

9
10
11
12

e-"Ts XIDCLKx
16 POX
ISi=rFSX " P CLKX
13 P CLKR

TSXI
I

TSRI

210314-20

NOTE:
(1) One inverter per linecard.

Figure 12. Circuit Diagram Showing Connections Needed to Retrofit the 2913/14
into Existing Variable Data Rate Systems
Transmit Coded (Encoder)-The transmit filter can be
bypassed by directly accessing the differential input of
the transmit encoder with an analog differential drive
signal. Table 9 shows the control pin voltages and the
input pins for this test. This test mode permits DC testing of the encoder which is otherwise blocked by the
AC coupling (low frequency reject filter) of the transmit filter.

Table 8. Multimode Testing for Each Level from
Design to On-Line Operation
• Design/Prototype Testing
- Direct access to transmit codec inputs
- Direct access to the receive filter input
and the transmit filter differential outputs

Transmit and Receiver Filter-Table 9 shows the control values that permit access to the differential outputs
of the transmit filter and the single-ended input to the
receive filter. The voltage difference between the transmit filter outputs represents the filtered output that will
be encoded. By driving VFxI (single ended or differentially), the transmit filter response is obtained as a differential output. The final stage is the 60 Hz reject filter
which is a switched capacitor filter sampled at an
8 KHz rate. When measured digitally (after the encoder), the filter characteristic is obtained directly: however, when measured in analog, a sin (wT/2)/wT/2 correction factor must be included.

• Manufacturing Tests
- Standard half channel tests for combined codec/filters
- Filter response half channel measurements
• Operation On-Line Tests
- Analog loopback for testing PCM and
codec analog highways
- Redundancy checks with repeatable
Dx outputs
Table 9 gives the input control pin values and the corresponding functions assigned to the key test pins on the
2914 for the design test modes.

5-103

intJ

AP-142

Table 9. 2914 Test Functions and Control Inputs for the Design Test Modes
Input

Pin Function (24-Pin)

Test
Function

Pin 9
DCLKR

Pin 17
TSx/DCLKx

Pin 18
SIGx/ASEL

O-Vee

DCLKR

TSx/DCLKx

SIGx/ASEL.

Normal Operation

VBB

O-Vee

+VFX

-VFX

Encoder

VBB

VFRI

+VFXO

-VFXO

RCV, XMIT Filter

PDN

O-Vee

NOTES:
The terms used above are defined as:
± VFX = Encoder Input
±VFXO = XMIT Filter Output
VFRI = ReV Filter Input

The input to the receive filter first passes through a
sample and hold. This is necessary to simulate the
sin (wT/2)/wT/2 characteristic that results from the
decoder 0/A output. The net result is a filter characteristic that can be compared directly to the specifications.

ENCODER/DECODER TESTING

Start-up Procedure for Test Modes-To place the
2913/14 in the test mode it is first necessary to operate
the device for a few ms in normal operation. Then VBB
can be applied to the control pins to select the desired
test access.

4.2 Production Testing
While it may ·be convenient for the designer to have
access to both the filter and the codec inputs and out·
puts during the design or evaluation phase the final
product will always use the filter and codec circuits
together with all signals passing through both on the
way to or from the PCM highways. It therefore makes
sense to perform all manufacturing measurements with
the device configured in its normal operating mode, i.e.,
all measurements should be complete filterlCodec half
channel measurements. This approach not only tests
the combo as it will actually be used, but also. saves
time and money by eliminating separate measurements
and correlation exercises to determine the full half
channel performance.
Since the transmission specifications of SID, gain
tracking, and ICN all require measurements which are
"in·band" or "filter independent," the codec functions
can be easily tested using conventional half channel
measurement equipment. The apparent difficulty arises
in trying to fully measure the filter characteristics be·
yond the half sampling frequency of 4 KHz. In fact,
this is not really a problem with today's computerbased testing plus an understanding of the sampled data
process which is discussed under "Filter Testing".

Transmission specifications are AC·coupled in-band
measurements when using either CCITT G.712.1I
methods I & 2 (white noise testing and sinusoidal testing, respectively) or AT&T Pub 43801 (Sinusoidal
Testing). The noise testing uses a narrowband of flat
noise from 300 to 500 Hz to drive the filter/codec (either in analog or the equivalent digital sequence for the
transmit/receive charlnels, respectively). The resulting
harmonic products are used to determine SID. Like·
wise, gain tracking is also determined from this signal
input. Sinusoidal testing uses a tone at 1.020 KHz for
SID measurements and gain tracking measurements.
Idle channel noise meas4rements require the combined
filter/codec since it has long been shown that separate
measurements of filters and codecs are difficult to relate
to the combined measurement (usually there is no specific relationship because of the non-linear properties of
the encoder/decoder operations). Typically the frequency response of ICN measurements is primarily determined by the weighting filter (either C message or
psophometric, which are both AC·coupled, bandpass
type filters).
The conclusion is that combined filter/codec testing in
no way limits the measurement of half channel trans·
mission parameters of SID, G.T., or ICN.
FILTER TESTING
Testing the filter response, of the transmit and receive
channels presents two separate test situations which, in
some ways, are mirror images of one another. With the
transmit side, signals may be introduced at any frequency to test the filter response. At the output of the
filter, the resulting signals are sampled at 8 KHz and
digitized resulting in a sequence of PCM words representing the samples of filtered input signal. On the reo
ceive side, a digital PCM sequence of samples representing the driving signal is converted to an analog signal by the decoder and can be measured at the filter
. output in analog form.

5-104

infef

AP-142

Sampling Process-In both cases of testing the filter,
the signal eventually is in a sampled form. Since the
sampling rate is fixed at 8 KHz, all signals must be
represented below 4 KHz (half the sampling frequency). This means that the PCM bit stream can only represent signals at frequencies below 4 KHz. If a signal
above 4 KHz is sampled, those samples appear exactly
as if the signal was at a frequency mirror imaged about
4 KHz. Two examples include signals at 5 KHz and
7 KHz which will result in samples that look like signals of 5-8 KHz = 3 KHz and 7-8 KHz = I KHz,
respectively.
Conversely, the sampling process produces replicas (aliasing) of the sampled signal around multiples of the
sampling frequency. Therefore, if two signals are introduced digitally representing I KHz and 2 KHz, there
will also be frequency components located at 8 KHz =
± I KHz and 8 KHz = ± 2 KHz, and so on for all
multiples of 8 KHz. Thus it is possible to generate frequencies at arbitrary values after sampling by controlling the frequency of each signal within the 4 KHz input band regardless of whether it is in analog or PCM.
When an analog signal is sampled, the frequency components generated are all of the same amplitude as the
corresponding input spectral components. Therefore,
on the transmit side, measurements made from the
PCM data will have a throughput gain of unity except
where components are superimposed (e.g., a 4 KHz input signal will have an alias component at 4 KHz
which may double the amplitude at 4 KHz when the
two components are combined).

are generated to determine spectral frequencies and amplitudes at the codec output, or (2) use an "ideal" D/A
converter on the PCM samples to convert the digital
data back to analog so that the spectral amplitudes and
frequencies can be determied using analog circuits such
as spectrum analyzers or filter banks. In either case, the
effects of sampling will be the same. Figure 13 shows
two spectral diagrams of amplitude versus frequency.
The top diagram represents the locations of nine test
frequencies corresponding to the seven specified frequencies in the 2913/14 data sheet plus a component at
7 KHz and one at 10 KHz. The bottom figure shows
the "equivalent" spectral component locations when
carried in the PCM bit stream. As an example, frequency # 8 is located at 7 KHz. The corresponding PCM
frequency is seen in the lower figure at 1 KHz. Note
also that the analog component at 9 KHz (see #8*)
would also generate the I KHz component in the PCM
data.
To test the filter, the desired test frequencies are introduced in analog to the filter input in such a way that
there is no confusion as to where the resulting component will be after sampling (i.e., don't simultaneously
put in 1 KHz and 7 KHz since both of these inputs
result in a 1 KHz component in the PCM data). Then,
using either technique (FFT or analog) mentioned
above, measure the amplitude of the corresponding

•

When an analog signal. is reconstructed from digital
samples, it goes through a sample and hold stage which
has the effect of imposing a weighting function on the
resulting spectral components that is represented by
234

FREQ
kHz

210314-21

Sinc [ w2T]

(a) Analog Signal Frequency Locations

wT
2

where w is the actual spectral component frequency
going into the filter, and T is the width of the hold
pulse at the decoder output. For the 2913/14, the analog output is held the full sample period of 125 JLs
(1/8000 Hz) so that a frequency component at ft will
have a weighting of
4

8000)
. [7T
ft ]
W= ( - Sm
--

7Tft

FREQ
kHz

210314-22

8000

(b) PCM Representation of the Signals in (a)

Transmit Filter Test Approach-Two approaches can
be used for half channel testing of the transmit filter
characteristic: (l) input analog test frequencies and perform an FFT on the corresponding PCM samples that

5-105

Figure 13. Spectral Properties of the Filter Test
Frequencies in Analog and PCM

Intel

AP-142

sampled component. The difference between that amplitude and the input amplitude represents the filter
attenuation at the frequency of the input signal. So, if
the signal was at 7 KHz, the FFT will determine the
amplitude of the corresponding 1 KHz signal. The amplitude change relative to the input will represent the
mter attenuation at 7 KHz.

desired test frequency. The various weighting values are
easily handled by computer-based test equipment since
the inverse weighting function can be stored in the
computer and applied to each measured amplitude as
appropriate.

4.3 Operational On-Line Testing
Receive Filter Test Approach-In this case, the PCM
test signals can be generated directly from digital circuits or by going through an "ideal" A/D (companded)
to generate the PCM samples. Since these samples represent frequencies below the half sampling rate, Figure
12(b) now represents the input signals and 12(a) the
output, but with one significant difference-a
Sinc[7T fl/8000] weighting function is imposed on all
the frequency components because of the decoder sample and hold output. At the mter output, the spectral
component amplitudes will include the effect of the m- .
ter response and the weighting function measured at
the actual test frequency. The receive filter includes a
compensation network for the weighting function in its
passband. Therefore, inside the passband (300 Hz to
3.4 KHz) the measured amplitudes should be compared
directly to the data sheet specifications. Frequencies,
outside the passband must be compensated for the
weighting function first to determine the true mter response.
Summary of Filter Testing-Table 10 lists the nine test
frequencies shown in Figure 12 for both the transmit
and receive mter testing. For each mter test, the input
frequency (analog or PCM), measurement frequency,
and test circuit gain is tabulated corresponding to the

Two test modes are available which facilitate on-line
testing to verify operation of both the combochip and
the entire switching highway network. The first is simply the capability to duplicate the same Dx transmission in multiple PCM time slots (redundancy checking), and the second is the analog loopback capability
which allows the testing of a call completion through
the entire PCM voice path including the time slot interchange network.
Redundancy Checking-A feature of the 2913/14 is
that the same 8-bit PCM word can be put on the Dx
highway in multiple time slots simply by holding the
frame sync/data enable (FSx) high and continuing to
supply clock pulses (CLKx or DCLKx). If the data
enable was held high for multiple time slots, each time
slot would have identical data in it. By routing this data
through the PCM highways, time slot interchanges,
etc., and then correlating the data between time slots, it
would be possible to detect time slot-dependent data
errors. When this test mode is used, no other data will
be generated for the transmit highway until the frame
sync returns low for at least one full clock cycle.

Table 10. Filter Response Testing Input/Output Frequencies and Amplitude Gain Schedule
Test
Freq.
1

200

Receive

Transmit
Input
Freq.
200

Measured
Freq.

Amp
Weighting

200

Input
Freq.
200

Measured
Freq.

Amp
Weighting

200

300

3000

3300

3400

4000

oto 2

4000

Ot02

4600

3400

4600

S.Inc [4600
7T]
---

7000

1000

7000

S.Inc [7000
7T]
--8000

10000

2000

10000

S.Inc [10000
7T]
--8000

8000

5-106

inter

AP-142

Analog Loopback-The 2914 (2913 does not have this
feature) has the capability to be remotely programmed
to disconnect the outside telephone lines and tie the
transmit input directly to the receive output to effect
analog loopback within the combo chip. This is accomplished by setting the LOOP input to Vee (TTL high).
The result is to disconnect VFxI + and VFxI - from
the external circuitry and to connect internally
PWRO+ to VFxI+, GS r to PWRO-, and VFxIto GSx (see Figure 14).

With this test set up, the entire PCM and analog transmission path up to the SLIC can be tested remotely by
assigning a PCM word to a time slot that is read by the
combo being tested. This data is converted to analog
and passed out of the receive channel. It is taken as
input by the transmit channel where it is filtered and
redigitized (encoded) back to PCM. The PCM word
can now be put on the transmit highway and sent back
to the remote test facility. By comparing the PCM data
(individually or as a series of codes) the health of that
particular connection can be verified.

--------------------------,

I-LOOP
I

I
I

TRANSMIT
VOICE

DX I

DIGITIZED
PCM
lOOP BACK
RESPONSE

VFXI+

PWRO+

-1--+----"7"'+1----1

PWRO--r--~-~

h
~

COMBOCHIP ANALOG LOOP BACK FUNCTION

DIGITIZED
PCM
TEST
TONE

210314-23

Figure 14. Simplified Block Diagram of 2914 Combochip in the Analog Loopback Configuration

5-107

DOMESTIC SALES OFFICES
ALABAMA
Intel Corp.
5015 Bradford Dr.. #2

Huntsville 35805
Tel: (205) 830-4010
FAX: (205) 837-2640
ARIZONA

tlntel Corp.
410 North 44th Street

Suite 500
Phoenix 85008
Tel: (602) 231-0386
FAX: (602) 244-0446

Intel Corp.
7225 N. Mona Lisa Rd.
Suite 215
Tucson 85741
Tel: (602) 544-0227
FAX: (602) 544-0232
CALIFORNIA

tlntel Corp.
21515 Vanowen Street
Suite 116
Canoga Park 91303
Tel: (818) 704-8500
FAX: (818) 340-1144
tlntel Corp.
300 N. Continental Blvd.
Suite 100
EI Segundo 90245
Tel: (213) 640-6040
FAX: (213) 640-7133
Intel Corp.
1 Sierra Gate Plaza
Suite 280C
Roseville 95678
Tel: (916) 782-8086
FAX: (916) 782-8153
tlntel Corp.
9665 Chesapeake Dr.
Suite 325
San Diego 92123
Tel: (619) 292-8086
FAX: (619) 292-0628
tlntel Corp. '"
400 N. Tustin Avenue
Suite 450
Santa Ana 92705
Tel: (714) 835-9642
1WX: 910-595-1114
FAX: (714) 541-9157
tlntel Corp.'"
San Tomas 4
2700 San Tomas Expressway
2nd Floor
Santa Clara 95051
Tel: (408) 986-8086
1WX: 910-338-0255
FAX: (408) 727-2620
COLORADO

Intel Corp.
4445 Northpark Drive
Suite 100
Colorado Springs 80907
Tel: (719) 594-6622
FAX: (303) 594-0720
tlntel Corp. '"
600 S. Cherry 51.
Suite 700
Denver 80222
Tel: (303) 321-8086
TWX: 910-931-2289
FAX: (303) 322-8670
CONNECTICUT

tlntel Corp.
301 Lee Farm Corporate Park
83 Wooster Heights Rd.
Danbury 06810
Tel: (203) 748-3130
FAX: (203) 794-0339

tSales and Service Office
"'Field Application Location

FLORIDA

tlntel Corp.

MICHIGAN

tlntel Corp.*

tlntel Corp.

Suite loa
Beachwood 44122
Tel: (216) 464-2736
TWX: 810-427-9298
FAX: (804) 282-0673

tlntel Corp.

MINNESOTA

OKLAHOMA

Suite 340
Orlando 32822
Tel: (407) 240-8000
FAX: (407) 240-8097

tInter Corp.
3500 W_ 801h 51.
Suite 360
Bloomington 55431
Tel: (612) 835-6722
1WX: 910-576-2867
FAX: (612) 831-6497

Deerfield Beach 33441
Tel: (305) 421-0506
FAX: (305) 421-2444

5850 T.G. Lee Blvd.

Intel Corp.
11300 4th Street North
Suite 170
St. Petersburg 33716
Tel: (813) 577-2413
FAX: (813) 578-1607
GEORGIA

tlntel Corp.
20 Technology Parkway
Suite 150
Norcross 30092
Tel: (404) 449-0541
FAX: (404) 605-9762
ILLINOIS

tlntel Corp.'"
Woodfield Corp. Center III
300 N. Martingale Road
Suite 400
Schaumburg 60173
Tel: (708) 605-8031
FAX: (708) 706-9762

MISSOURI

tlntel Corp.
4203 Earth City Expressway
Suite 131

i;r~3~~ g2~~~90

FAX: (314) 291-4341
NEW JERSEY

tlntel Corp.'"
Parkway 109 Office Center
328 Newman Springs Road
Red Bank 07701
Tel: (201) 747-2233
FAX: (201) 747-0983
Intel Corp.
280 Corporate Center
75 Livingston Avenue
First Floor
Roseland 07068
Tel: (201) 740-0111
FAX: (201) 740-0626

INDIANA

NEW YORK

tlntel Corp.
8910 Purdue Road
Suite 350
Indianapolis 46268
Tel: (317) 875-0623
FAX: (317) 875-8938

Intel Corp.'"
850 Crosskeys Office Park
Fairport 14450
Tel: (716) 425·2750
TWX: 510-253-7391
FAX: (716) 223-2561

IOWA

Intel Corp.
1930 St. Andrews Drive N.E.
2nd Floor
Cedar Rapids 52402
Tel: (319) 393-5510
KANSAS

tlntel Corp.
10985 Cody 51.
Suite 140
Overland Park 66210
Tel: (913) 345-2727
FAX: (913) 345-2076
MARYLAND

tlntel Corp.'"
10010 Junction Dr.
Suite 200
Annapolis Junction 20701
Tel: (301) 206-2860
FAX: (301) 206-3677
(301) 206-3678

tlntel Corp.'"
2950 Express Dr., South
Suite 130
Islandia 11722
Tel: (516) 231-3300
TWX: 510-227-6236
FAX: (516) 348-7939
tlntel Corp.
Westage Business Center
Bldg. 300, Route 9
Fishkill 12524
Tel: (914) 897-3860
FAX: (914) 897-3125
NORTH CAROLINA

tlntel Corp.
5800 Executive Center Dr.
Suite 105
Charlotte 28212
Tel: (704) 568-8966
FAX: (704) 535-2236
tlntel Corp.
5540 Centerview Dr.
Suite 215
Raleigh 27606
Tel: (919) 851-9537
FAX: (919) 851-8974

MASSACHUSETTS

tlntel Corp.'"
Westford Corp. Center
3 Carlisle Road
2nd Floor
Westford 01886
Tel: (508) 692-0960
TWX: 710-343-6333
FAX: (508) 692-7867

OHIO

tlntel Corp. '"
3401 Park Center Drive
Suite 220
Dayton 45414
Tel: (513) 890-5350
1WX: 810-450-2528
FAX: (513) 890-8658

VIRGINIA

25700 SCience Park Dr.

7071 Orchard Lake Road
Suite 100
West Bloomfield 48322
Tel: (313) 851-8096
FAX: (313) 851-8770

800 Fairway Drive
Suite 160

tlntel Corp.
1504 Santa Rosa Road
Suite 108

Richmond 23288
Tel: (804) 282-5668
FAX: (216) 464-2270
WASHINGTON

Intel Corp.

6801 N. Broadway
Suite 115
Oklahoma City 73162
Tel: (405) 848-8086
FAX: (405) 840-9819
OREGON

tlntel Corp.
15254 N.w. Greenbrier Parkway
Building B
Beaverton 97005
Tel: (503) 645-8051
TWX: 910-467-8741
FAX: (503) 645-8181

tlnlel Corp.
155 IOBth Avenue N.E.
Suite 386
Bellevue 98004
Tel: (206) 453-8086
TWX: 910-443-3002
FAX: (206) 451-9556

Intel Corp.
408 N. Mullan Road
Suite 102
Spokane 99206
Tel: (509) 928-8086
FAX: (509) 928-9467
WISCONSIN

PENNSYLVANIA

tlntel Corp. *
925 Harvest Drive
Suite 200
Blue Bell 19422
Tel: (215) 641-1000
FAX: (215) 641-0785
tlntel Corp.'"
400 Penn Center Blvd.
Suite 610
Pittsburgh 15235
Tel: (412) 823-4970
FAX: (412) 829-7578
PUERTO RICO

tlntel Corp.
South Industrial Park
P.O. Box 910
Las Piedras 00671
Tel: (809) 733-8616
TEXAS

Intel Corp.
8911 Capita! of Texas Hwy.
Austin 78759
Tel: (512) 794-8086
FAX: (512) 338-9335
tlntel Corp.'"
12000 Ford Road
Suite 400
DalJas 75248
Tel: (214) 241-8087
FAX: (214) 484-1180
tlntel Corp.'"
7322 S.W. Freeway
Suite 1490
Houston 77074
Tel: (713) 988-8086
TWX: 910-881-2490
FAX: (713) 988-3660
UTAH

tlntel Corp.
428 East 6400 South
Suite 104
Murray 84107
Tel: (801) 263-8051
FAX: (801) 268-1457

Intel Corp.
330 S. Executive Dr.
Suite 102
Brookfield 53005
Tel: (414) 784-8087
FAX: (414) 796-2115

CANADA
BRITISH COLUMBIA

Intel Semiconductor of
Canada, Ltd.
4585 Canada Way
Suite 202
Burnaby V5G 4L6
Tel: (604) 298-0387
FAX: (604) 298-8234
ONTARIO

tlntel Semiconductor of
Canada, Ltd.
2650 Queensview Drive
Suite 250
Ottawa K2B 8H6
Tel: (613) 829-9714
FAX: (613) 820-5936
tlntel Semiconductor of
Canada, Ltd.
190 Attwell Drive
Suite 500
Rexdale M9W 6H8
Tel: (416) 675-2105
FAX: (416) 675-2438
QUEBEC

tlntal Semiconductor of
Canada, Ltd.
1 Rue Holiday
Suite 115
Tour East
pt. Claire H9R 5N3
Tel: (514) 694-9130
FAX: 514-694-0064

DOMESTIC DISTRIBUTORS
ALABAMA

Arrow Electronics. Inc.
1015 Henderson Road
Huntsville 35805
Tel: (205) 637-6955
FAX: 205-751-1581

Hamilton/Avnet Computer
4930 I Corporate Drive
Huntsville 35805

tArrow Electronics, Inc.
2961 Dow Avenue
Tustin 92680

tWyle Distribution Group
17872 Cowan Avenue
Irvine 92714

tPioneerfTechnologies Group, Inc.
337 Northlake Blvd .. Suite 1000
Alta Monte Springs 32701

Tel: (714) 836-5422
TWX: 910-595-2660

Tel: (714) 663-9953
TWX: 910-371-7127

Tel: (407) 634-9090
FAX: 407-834-0865

tWyle Distribution Group
26677 W. Agoura Rd.

PioneerfTechnoloQies Group, Inc.
674 S. Military Trail
Deerfield Beach 33442

Hamilton/Avnet Computer
3170 Pullman Street
Costa Mesa 92626

Calabasas 91302
Tel: (616) 660-9000
TWX: 372-0232

Hamilton/Avnet Computer
13618 West 190th Street
Gardena 90248

COLORADO

Huntsville 35805
Tel: (205) 837-7210
FAX: 205-721-0356

Hamilton/Avnet Computer
4103 Northgate Blvd.
Sacramento 95834

Arrow Electronics, Inc.
7060 South Tucson Way
Englewood 801 t 2

~9~oSt~~~~area~~ve

Hamilton/Avnet Computer
4545 Viewridge Avenue
San Diego 92123

Tel: (205) 630-9526
FAX: (205) 830-9557

Hamilton/Avnet Computer
1175 Bordeaux Drive
Sunnyvale 94089

Pioneer/Technolagies Group, Inc.
4825 University Square
Huntsville 35805

Hamilton/Avnet Electronics
21150 Caljfa Street
Woodland Hills 91367

Hamiltan/Avnet Electronics
4940 Research Drive

Suite 120
HUntsville 35806

Tel: (205) 637-9300
FAX: 205-637-9356
ALASKA

HamiitonfAvnet Computer
1400 W. Benson Blvd., Suite 400
Anchorage 99503
ARIZONA

fArrow Electronics, Inc,
4134 E. Wood Street
Phoenix 85040
Tel: (602) 437-0750

1WX: 910-951-1550
Hamilton/Avnet Computer
30 South McKemy Avenue
Chandler 85226

tHamilton/Avnet Electronics
3170 Pullman Street
Costa Mesa 92626
Tel: (714) 641-4150

1WX: 910-595-2636
tHamiltonlAvnet Electronics
1175 Bordeaux Drive
Sunnyvale 94086
Tel: (406) ·743-3300
TWX: 910-339-9332

tHamilton/Avnet Electronics
4545 Ridgeview Avenue
San Diego 92123
Tel: (619) 571-7500
TWX: 910-595-2636

tHamiiton/Avnet Electronics
21150 Calila 51.

Hamilton/Avnet Computer

Woodland Hills 91376

90 South McKemy Road

Chandler 85226

Tel: (816) 594-0404
FAX: 816-594-6233

tHamilton/Avnet Electronics
505 S. Madison Drive
Tempe 85281

tHamilton/Avnet Electronics
10950 W. Washington Blvd.
Culver City 20230

Tel: (602) 231-5140

1WX: 910-950-0077

Tel: (213) 556-2456
TWX: 910-340-6364

Hamilton/Avnet Electronics
30 South McKemy
Chandler 85226

tHamiiton/Avnet Electronics
1361 B West 190th Street
Gardena 90248

Tel: (602) 961-6669
FAX: 602-961-4073

Tel: (213) 217-6700
TWX: 910-340-6364

Wyle Distribution Group
4141 E. Raymond
Phoenix 85040

tHamilton/Avnet Electronics
4103 Northgale Blvd.

Sacramento 95834

Tel: (602) 249-2232

Tel: (916) 920-3150

1WX: 910-371-2871
CALIFORNIA

Pioneer/Technologies Group, Inc.
134 Rio Robles
San Jose 95134

Arrow Commercial System Group
1502 Crocker Avenue

Tel: (406) 954-9100
FAX: 406-954-9113

Hayward 94544
Tel: (415) 489-5371
FAX: (415) 469-9393

Wyle Distribution Group

Arrow Commercial System Group
14242 Chambers Road
Tustin 92680
Tel: (714) 544-0200
FAX: (714) 731-6436

tArrow Electronics, Inc.
19748 Dearbom Street
Chatsworth 91311
Tel: (213) 701-7500

Tel: (303) 790-4444

Hamilton/Avnet Computer
9605 Maroon Circle, Ste. 200
Engelwood 80112
tHamHton/Avnet Electronics
9605 Maroon Circle
Suite 200
Englewood 80112
Tel: (303) 799-{1663
TWX: 910-935-0767

twyle Distribution Group
451 E. 124th Avenue
Thornton 80241

1WX: 910-493-2066

Tel: (916) 638-5282

tArrow Electronics, Inc.
9511 Ridgehaven Court
San Diego 92123

tWyle Distribution Group
9525 Chesapeake Drive

~:r Psi~o5~~~~;71

Tel: (404) 497-1300

1WX: 810-766-0439
Hamilton/Avnet Computer
5825 D. Peachtree Corners E.
Norcross 30092

Tel: (404) 447-7500
TWX: 610-766-0432

tArrow Electronics, Inc.
12 Beaumont Road
Wallingford 06492
Tel: (203) 265-7741
TWX: 710-476-0162

Hamitton/Avnet Computer
Commerce Industrial Park
Commerce Drive
Danbury 06810
tHamilton/Avnet Electronics
Commerce Industrial Park
Commerce Drive
Danbury 06610
Tel: (203) 797·2600
TWX: 710-456-9974

tPioneer/Slandard Electronics
t 12 Main Street
Norwalk 06851

Pioneer{Technologies Group. Inc.
3100 F Northwoods Place
Norcross 30071
Tel: (404) 448-1711
FAX: 404-446-6270
ILLINOIS

tArrow Electronics, Inc.
1140 W. Thorndale
Itasca 60143
Tel: (706) 250-0500
TWX: 706-250-0916

Hamilton/Avnet Computer
1130 Thorndale Avenue
Bensenville 60106

Tel: (203) 853-1515
FAX: 203-638-9901

tHamilton/Avnet Electronics
1130 Thorndale Avenue
Bensenville 60106

FLORIDA

Tel: (706) 860-7760
1WX: 708-860-6530

tArrow Electronics, Inc.
400 Fairway Drive
Suite 102
Deerfield Beach 33441

MTI Systems Sales
1100 W. Thorndale

Tel: (305) 429-8200
FAX: 305-426-3991

tArrow Electronics, Inc.
37 Skyline Drive
Suite 3101

6601 NoW. 151h Way

tWyle Distribution Group
2951 Sunrise Blvd., Suite 175
Rancho Cordova 95742

tArrow Electronics, Inc.
4250 E. Rivergreen Parkylay
Deluth 30136 .

CONNECTICUT

124 Maryland Street

Garden Grove 92641

Delulh 30139
Tel: (404) 623-6625
FAX: (404) 623-8602

tHamilton/Avnet Electronics
5825 0 Peachtree Corners
Norcross 30092

~~~(~f~)dg~~o
~~~ g:~~U::~l~;~UP

GEORGIA

Arrow Commercial System Group
3400 C. Corporate Way

Tel: (303) 457-9953
TWX: 910-936-0770

Lake Marv 32746
Tel: (407) 323-0252
FAX: 407-323-3169

Tel: (714) 891-1717
FAX: 714-691-1621

Tel: (305) 426-6677
FAX: 305-481-2950

Hamilton/Avnet Computer
Ft. Lauderdale 33309
Hamilton/Avnet Computer
3247 Spring Forest Road
St. Peters~urg 33702
tHamilton/Avnef. Electronics
6801 NW. 15th Way
Ft. Lauderdale 33309
Tel: (305) 971-2900
FAX: 305-971-5420

tHamilton/Avnet Electronics
3197 Tech Drive North
SI. Petersburg 33702

Itasca 60143
Tel: (708) 773-2300

tPioneer/Standard Electronics
2171 Executive Dr., Suite 200
Addison 60101
Tel: (708) 495-9660
FAX: 706-495-9631
INDIANA

tArrow Electronics, Inc.
7108 Lakeview Parkway West Drive
Indianapolis 46268
Tel: (317) 299-2071
FAX: 317-299-{1255

Hamilton/Avnet Computer
485 Gradle Drive
Carmel 46032
Hamilton/Avnet Electronics
485 Gradle Drive
Carmel 46032
Tel: (317) 644-9333
FAX: 317-844-5921

Tel: (619) 565-4600
FAX: 619-279-6062

1WX: 910-335-1590

Tel: (613) 573-3930
FAX: 613-572-4329

tArrow Electronics, Inc.
521 Weddell Drive
Sunnyvale 94086

tWyle Distribution Group
3000 Bowers Avenue
Santa Clara 95051

tHamiiton/Avnet Electronics
6947 University Boulevard
Winter Park 32792

tPioneer/Standard Electronics
9350 Priority Way
West Drive
Indianapolis 46250

Tel: (406) 745-6600
TWX: 910-339-9371

Tel: (406) 727-2500

1WX: 406-966-2747

Tel: (407) 626-3666
FAX: 407-676-1676

Tel: (317) 573-0680
FAX: 317-573-{1979

tCertified Technical Distributor

DOMESTIC DISTRIBUTORS (Contd.)
IOWA
Hamilton/Avnet Computer
915 33rd Avenue SW
Cedar Rapids 52404
Hamilton/Avnet Electronics
915 33rd Avenue, S.W.
Cedar Rapids 52404
Tel: (319) 362-4757
KANSAS
Arrow Electronics, Inc.
8208 Melrose Dr., Suite 210
Lenexa 66214
Tel: (913) 541-9542
FAX: 913-541-0328
Hamilton/Avnst Computer
15313 W. 95th Slreet
Lenexa 61219

Hamihon/Avnst Computer
2215 S.E. A-5
Grand Rapids 49508

HamihonJAvnet Computer
10 Industrial Road

~r:~~:J~~R~~,m&:.e:oo

tHamiltonJAvnet Electronics
1 Keystone Ave., Bldg. 36

Hamllton/Avnet Electronics
2215 29th Street S.E.
Space A5
Grand Rapids 49508
Tel: (616) 243-8805
FAX: 616-698-1831

FAX: 609-751-2552

Novi 48050

Hamiiton/Avnel Electronics
41650 Garden Brook

Novi 48050
Tel: (313) 347-4271
FAX: 313-347-4021

tHamihon/Avnet Electronics

tPioneer/Standarcl Electronics
4505 Broadmoor S.E.
Grand Rapids 49508
Tel: (616) 698-1800
FAX: 616-698-1831

KENTUCKY

tPloneer/Standard Electronics
13485 StamJord
Livonia 48150
Tel: (313) 525-1800
FAX: 313-427-3720

15313 W. 95th
Overland Park 66215
Tel: (913) 888-8900
FAX: 913-541-7851

Hamilton/Avnel Electronics
805 A. Newtown Circle

Lexington 40511
Tel: (606)'259-1475
MARYlAND
tArrow Electronics. Inc.
, 8300 Guilford Drive
Suite H, River. Center
Columbia 21046
Tel: (301) 995-6002
FAX: 301-381-3854
Hamilton/Avnet Computer
6822 Oak Hall Lane
Columbia 21045
tHamiHon/Avnet Electronics
6822 Oak Hall Lane
Columbia 21045
Tel: (301) 995-3500
FAX: 301-995-3593

~:o,,:~~~~.'~~~r8;.

Columbia 21046
Tel: (301) 290-8150
FAX:.301-290-6474

tPioneerfTechn.oIogies Group, Inc.
9100 GaIther Road
Gaithersburg 208n

Tel: (301) 921-0660
FAX: 301-921-4255
MASSACHUSETTS
Arrow ElectroniCS, Inc.
25 Upton Dr.

~:~i~8t\)'M'J-~

TWX: 710-393-6nO
Hamiiton/Avnet Computer
10 0 Centennial Drive
Pealbody 01960
tHamilton/Avnet Electronics
100 Centennial Drive

Peabody 01960
Tel: (SOB) 532-9838
FAX: 508-596-7802

tPioneerlstandard Electronics
44 Hartwell Avenue

~:f:i(m~ g~l !a~00
FAX: 617-863-1547

Wyle Distrib.utlon Group
15 Third Avenue
Burlington 01803

Tel: (617) 272-7300
FAX: 617-272-6809
MICHIGAN
tArrow Electronics, Inc.
19880 HaggertY.Road
Livonia 46152

Tel: (313) 665-4100

TWX: 810-223-6020

tcertified Technical Distributor

MtNNESOTA
tArrow Electronics, Inc.
5230 W. 73rd Street
Edina 55435
Tel: (612) 830-1800
TWX: 910-576-3125
Hamilton/Avoet Computer
12400 Whitewater Orive
Minnetonka 55343
tHamiiton/Avnet Electronics
12400 Whitewater Drive
Minnetonka 55434
Tel: (612) 932-0600
TWX: 910-576-2720
tPioneer/Standard Electronics
7625 Golden Trl80ge Dr.
SulteG
Eden Prairie 55343
Tel: (612) 944-3355
FAX: 612-944-3794
MtSSOURI
tArrow ElectroniCS, Inc.
2380 Schuetz
81. Louis 63141
Tel: (314) 567-6898
FAX: 314-567-1164
HamUton/Avnet Computer
739 Goddard Avenue
Chesterfield 63005
tHamilton/Avnet Eleclronics
741 Goddard
Chesterfield 63005
Tel: (314) 537-1600
FAX: 314-537-4248
NEW HAMPSHIRE
Hamilton/Avnet Computer
2 Executive Park Drive
Bed10rd 03102
Hamifton/Avnet Computer
444 East Industrial Park 0,.
Manchester 03103
NEW JERSEY
tArrow Electronics, Inc.
4 East Stow Road
UnH 11
Marhon 08053
Tel: (609) 596-8000
FAX: 609-596-9632
tArrow Electronics
6 Century Drive
Parsipanny 07054
Tel: (201) 538-0900
FAX: 201-538-0900

~=~g~~v~~e~~~~~6

Cherry Hill 08003

Fairfield 07006

~~~(~i"4~~og~10

tHamJlton/Avnet Electronics
10 Industrial

Fairtield 07006
Tel: (201) 575-3390
FAX: 201-575-5839

~tt:a~s~~l:ems Sales
Fairfield.07006
Tel: (201) 227-5552
FAX: 201-575-6336
tPioneer/Standard Electronics
14·A Madison Rd.
Fairfield 07006
Tel: (201) 575-3510
FAX: 201-~75-3454

tPioneerlStandard Electronics

&'~~s:.tcin~~s~~~ 11797

Tel: (516) 921-8700 .
FAX: 516-921-2143

tPioneer/Slandard Electronics
840 Fairport Park
Fairport 14450
Tel: (716) 381-7070
FAX: 716-381-5955
NORTH CAROLINA'
tArrow Electronics, Inc.
5240 GreensdaJry Road

~:I~\~~ ~7:ra.3132

TWX: 510-928-1856
Hamllton/Avnet ComFfcuter
3510 Sprln~orest oad
Raleigh 27
tHamilton/Avoet Electronics
3510 Spring Forest Drive

~~~~~9r~t0819

NEW MEXICO

TWX: 510-928-1836

Alliance Electronics Inc.
105tO Research Avenue
Albuquerque 87123
Tel: (505) 292-3360
FAX: 505-292-6537

Charlotte 28210
Tel: (919) 527-8188
FAX: 704-522-8564

Hamilton/Avnet Computer
5659 Jefferson, N.E. Suites A & B
Albuquerque 87109
tHamilton/Avnet Electronics
5659A Jefferson N.E.
Albuquerque 87109
Tel: (505) 765-1500
FAX: 505-243-1395
NEW YORK
tArrow Electronics, Inc.
3375 Brighton Henrietta Townline Rd.
Rochester 14623
Tel: (716) 427-0300
TWX: 510-253-4766

~~~e~~~e~~~~~o~:~: g~d.P. Inc.

~~~~e:Je~i~~~~~~~~:roup,

Inc.

Suite 148
Durham2n13
Tel: (919) 544-5400
FAX: 919-544-5885
OHIO
Arrow Commercial System Group
284 Cramer Creek Court
Dublin 43017
Tel: (614) 889-9347
FAX: (614) 889-9680
tArrow Electronics, Inc.
6238 Cochran Road
Solon 44139

Arrow Electronics, Inc.
20 Oser Avenue
Hauppauge 11788
Tel: (516) 231-1000
TWX: 510-227-6623

Tel: (216) 248-3990
TWX: 810-427-9409

Hamilton/Avnet Computer
933 Motor Parkway
Haupauge 11788

Hamflton/Avnet Computer
30325 Bainbridge Rd., Bldg. A

Hamilton/Avnst Computer
2060 Townline
Rochester 14623

tHamiftonJAvnet Electronics
7760 Washington Village Dr.
Dayton 45459
Tel: (513) 439-6733
FAX: 513-439-6711

tHamilton/Avnet Electronics
933 Motor Parkway
Hauppauge 11788
Tel: (516) 231-9800
TWX: 510-224-6166
tHamilton/Avnet Electronics
2060 Townline Rd.
Rochester 14623
Tel: (716) 272-2744
TWX: 510-253-5470
. HamUton/Avnet ElectroniCS
103 Twin Oaks Drive
Syracuse 13206
Tel: (315) 437-0288
'TWX: 710-541-1560

~~~:~~~e~:~~~:e

Port Washington 11050
Tel: (516) 621-6200
FAX: 510-223-0846
Pioneer/Standard Electronics
68 Corporate Drive
Binghamton 13904
Tel: (607) 722-9300
FAX: 607-722-9562
Pioneer/Standard Electronics
40 Oser Avenue
Hauppauge 11787
Tel: (516) 231-9200
FAX: 510-227-9869

Hamiiton/Avnet com~uter
7764 Washlnron Vii age Or.
Dayton 4545

Solon 44139

tHamiiton/Avnet ElectroniCS
30325 Bainbridge
Solon 44139
Tel: (216) 349-5100
TWX: 810-427-9452
Hamilton/Avnet Computer
777 Brooksedge Blvd.
Westerville 43081
Tel: (614) 892-7004
FAX: 614-882-8650
Hamihon/Avnet Electronics
777 Brooksedge Blvd.
Westerville 43081
Tel: (614) 882-7004
MTI Systems Sales
23400 Commerce Park Road
Beachwood 44122
Tel: (216) 464-6688
tPioneer/Standard Electronics
4433 Interpoint Boulevard

!?:r(5~~f~~~-99oo

FAX: 513-236-6133
tPioneer/Slandard "Electronics
4800 E. 131st Street
Cleveland 44105
Tel: (216) 587-3600
FAX: 216-663-1004

DOMESTIC DISTRIBUTORS (Contd.)
OKLAHOMA

Arrow Electronics, Inc.

4719 South Memorial Dr.
Tulsa 74145

tHamiitonJAvnet Electronics
12121 E. 51st St., Suite lO2A

Tulsa 74146

Hamilton/Avnet Computer
1807A West Braker Lane
Austin 7B758
Hamilton/Avnet Computer
Forum 2
4004 Beltline, Suite 200

tHamilton/Avnet Electronics
17761 N.E. 78th Place
Redmond 98052

Dallas 75244

Tel: (206) 881-6697
FAX: 206-867-0159

Tel: (918) 252-7297

Hamilton/Avnet Computer

OREGON

Stafford 77477

4850 Wrighl Rd_. Suite 190

tAl mac Electronics Corp.

Hamilton/Avnet Computer
17761 Northeast 78th Place
Redmond 9B052

~Ie

Distribution Group
1 385 N.E. 90th Street
Redmond 98052

tHamilton/Avnet Electronics
1807 W. Braker lane
Austin 78758

Tel: (206) 881-1150
FAX: 206-881-1567

Tel: (503) 629-8090
FAX: 503-645-0611

Tel: (512) 837-8911
TWX: 910-874-1319

WISCONSIN

HamiltonfAvnet Computer
9409 Southwest Nimbus Ave.
Beaverton 97005

tHamiiton/Avnet Electronics
4004 Beltline, Suite 200

Arrow Electronics, Inc.
200 N. Patrick Blvd., Ste. 100
Brookfield 53005

1885 N.W. 169th Place

Beaverton 97005

tHamilton/Avnet Electronics
9409 S.W. Nimbus Ave.
Beaverton 97005
Tel: (503) 627-0201
FAX: 503-641-4012
Wyle

9640 Sunshine Court
Bldg_ G. Suile 200

Beaverton 97005
Tel: (503) 643-7900
FAX: 503-646-5466
PENNSYLVANIA

Arrow Electronics. Inc.
650 Seco Road
Monroeville 15146
Tel: (412) 856-7000

Hamilton/Avnet Computer
2800 Liberty Ave_. Bldg_ E

Pittsburgh 15222

Hamilton/Avnet Electronics
2800 Liberty Ave_

Pittsburgh 15238
Tel: (412) 281-4150

Pioneer/Standard Electronics
259 Kappa Drive

Dallas 75234
Tel: (214) 308-8111

TWX: 910-860-5929
tHamilton/Avnet Electronics
4850 Wright Rd., Suite 190
Stafford 77477
Tel: (713) 240-1733
lWX: 910-881-5523

tPioneer/Standard Electronics
1826-0 Kramer
Austin 78758
Tel: (512) 835-4000
FAX: 512-835-9829

Tel: (414) 792-0150
FAX: 414-792-0156

Hamilton/Avnet Computer
20875 Crossroads Circle
Suite 400
Waukesha 53186
tHamiiton/Avnet Electronics
28875 Crossroads Circle
Suite 400
Waukesha 53186
Tel: (414) 784-4510
FAX: 414-764-9509

tZentronics
1355 Meyerside Drive
Mississauga 15T 1C9
Tel: (416) 564-9600
FAX: 416-564-8320

Calgary T2E 6Z2

tZentronics
155 Colonnade Road
Unit 17
Nepean K2E 7K1

tPioneer/Slandard Electronics
10530 Rockley Road
Houston 77099
Tel: (713) 495-4700
FAX: 713-495-5642

tWyle Distribution Group
IBID Greenville Avenue
Richardson 75081

Hamilton/Avnet Electronics
2816 21st Slrest N_E_ #3
Calgary T2E 6Z3
Tel: (403) 230-3586
FAX: 403-250-1591

Calgary T2E 7H
Tel: (403) 295-8818
FAX: 403-295-8714

Arrow Commercial System Group

Tel: (901) 367-0540
FAX: (901) 367-2081

Tel: (613) 226-1700
FAX: 613-226-1184

Hamilton/Avnet Computer
2816 21st Street Northeast

UTAH

SUite 7
Memphis 38118

tHamilton/Avnet Electronics
190 Colonnade Road South
Nepean K2E 7L5

ALBERTA

Zentronics
6815 #8 Street N.E.
Suite 100

3635 Knight Road

Tel: (416) 677-7432
FAX: 416-617-0940

Tel: (214) 386-7300
FAX: 214-490-6419

Tel: (214) 235-9953
FAX: 214-644-5064

TENNESSEE

Hamilton/Avnet Computer
6845 Rexwood Road
Units 7, 8, & 9
Mississuaga l4V 1R2
Hamilton/Avnet Computer
190 Colonade Road
Nepean K2E 7J5
tHamilton/Avnet Electronics
6845 Rexwood Road
Units 3-4-5
Mississauga l4T 1R2

CANADA

Tel: (412) 782-2300
FAX: 412-963-8255

Tel: (215) 674-4000
FAX: 215-674-3107

Hamilton/Avnet Computer
Canada System Engineering
Group
368B Nashua Drive
Units7&8
Mississuaga l4V 1M5
Hamilton/Avnet Computer
3688 Nashua Drive
Units 9 & 10
Mississuaga l4V 1M5

tPioneer/Standard Electronics
13710 Omega Road
Dallas 75244

Pittsburgh 15238

tPioneer/Technologies Group. Inc.
Delaware Valley
261 Gibralter Road
Horsham 19044

tArrow Electronics, Inc.
1093 Meyerside, Unit 2
Mississauga L5T 1M4
Tel: (416) 673-7769
FAX: 416-672-0849

Hamilton/Avnet Computer
1585 West 2100 South
Salt Lake Ci1y 84119

BRITISH COLUMBIA

tHamilton/Avnet ElectroniCS
1585 West 2100 South

tHamiltonJAvnet Electronics
8610 Commerce Ct.
Burnaby V5A 4N6

Salt Lake Ci1y 64119
Tel: (801) 972-2800
lWX: 910-925-4018

tWyle Distribution Group
1325 West 2200 South

Suite E
West Valley 84119
Tel: (801) 974-9953

Tel: (804) 420-4101
FAX: 604-437-4712

Zentronics
108-11400 Bridgeport Road
Richmond V6X 1T2

Tel: (613) 226-8840
FAX: 613-226-6352
QUEBEC

Arrow Electronics Inc.
1100 St. Regis
Dorval H9P 2T5
Tel: (514) 421-7411
FAX: 514-421-7430

Arrow Electronics, Inc.
500 Boul. St-Jean-Baptiste
Suite 280
Quebec G2E 5R9
Tel: (418) 871-7500
FAX: 418-871-6816

Hamiiton/Avnet Computer
2795 Rue Halpern
SI. Lauren1 H4S 1P8

Tel: (604) 273-5575
FAX: 604-273-2413

tHamilton/Avnet Electronics
2795 Halpern
51. Laurent H2E 7Kl

TEXAS

WASHINGTON

ONTARIO

Tel: (514) 335-1000
FAX: 514-335-2481

Arrow Electronics, Inc.
3220 Commander Drive
Carrollton 75006

tAlmac Electronics Corp.
14360 S.E. Eastgate Way
Bellevue 98007

Arrow Electronics, Inc.
36 Antares Dr., Unit 100

520 McCaffrey

Tel: (214) 380-6464
FAX: (214) 248-7208

Tel: (206) 643-9992
FAX: 206-643-9709

tCertified Technical Distributor

Nepean K2E 7W5
Tel: (613) 226-6903
FAX: 613-723-2018

tZentronics
SI. Laurent H4T 1N3
Tel: (514) 737-9700
FAX: 514-737-5212

EUROPEAN SALES OFFICES
FINLAND

ITALY

SWEDEN

UNITED KINGDOM

Intel Finland OY
Ruosilantie 2
00390 Helsinki
Tel: (358) 0 544 644
TLX: 123332

Intel Corporation Iialia S.p.A.
Milanofiori Palazzo E
20094 Assago
Milano
Tel: (39) (02) 89200950
TLX: 341286

Intel Sweden A.B.
Dalvagen 24
171 36 Solna
Tel: (46) 8 734 01 00
TLX: 12261

Intel Corporation (U.K.) Ltd.
Pipers Way
Swindon, Wiltshire SN3 lRJ
Tel: (44) (0793) 696000
TLX: 444447/8

NETHERLANDS

SWIT2ERLAND

WES, GERMANY

Intel Semiconductor B.V.
Postbus 84130
3099 CC Rotterdam
Tel: (31) 10.407.11.11
TLX: 22283

Intel Semiconductor A.G.
Zuerichstrasse
6165 Winkel-Rueti be; Zuerich
Tel: (41) 01/860 62 62
TLX: 825977

Intel GmbH
Dornacher Strasse 1
8016 Feldkirchen bei Muenchen
Tel: (49) 089/90992-0
FAX: (49) 089/904/3948

FRANCE
Intel Corporation SAR.L
1, Rue Edison-BP 303
78054 81. Quentin-en-Yvelines
Cedex
Tel: (33) (1) 30 57 7000
TLX: 699016
ISRAEL
Intel Semiconductor Ltd.
Atidim Industrial Park-Neve Share!

P.O. Box 43202
Tel-Aviv 61430
Tel: (972) 03-498080
TLX: 371215

Intel GmbH
Abraham Uncoln Strasse 16-18
6200 Wiesbaden
Tel: (49) 06121/7605-0
TLX: 4-186183
Intel GmbH
Zettachring lOA
7000 Stuttgart 80
Tel: (49) 0711/7287-280
TLX: 7-254826

SPAIN
Intel Iberia SA
Zurbaran, 28
28010 Madrid
Tel: (34) (1) 308.25.52
TLX: 46880

EUROPEAN DISTRIBUTORS/REPRESENTATIVES
AUSTRIA

IRELAND

NORWAY

TURKEY

Bacher Electronics G.m.b.H.
Rotenmuehlgasse 26
1120 Wien
Tel: (43) (0222) 83 56 46
TLX: 31532

Micro Marketing Ltd.
Glenageary Office Park
Glenageary
Co. Dublin
Tel: (21) (353) (01) 856288
FAX: (21) (353) (01) 857364
TLX: 31584

Nordisk Elektronikk (Norge) A/S
Postboks 123
Smedsvingen 4
1364 Hvalstad
Tel: (47) (02) 84 62 10
TLX: 77546

EMPA Ele'ctronic
Lindwurmstrasse 95A
8000 Muenchen 2
Tel: (49) 089/53 80 570
TLX: 528573

BELGIUM
Inefco Belgium SA
Av. des Croix de Guerre 94
1120 Bruxelfes

?10~60~~~~~!rnlaan, 94
Tel: (32) (02) 21601 60
TLX: 64475 or 22090
DENMARK
ITT-Multikomponent
Naverland 29
2600 Glostrup
Tel: (45) (0) 2 45 66 45
TLX: 33 355

FINLAND
OY Fintronic AB
Melkonkatu 24A
00210 Helsinki
Tel: (358) (0) 6926022
TLX: 124224

FRANCE
Almex
Zone industrielle d'Antony
48, rue de l'Aubepine
BP 102
92164 Antony cedex
Tel: (33) (1) 46 66 21 12
TUe 250067
Jermyn
60, rue des Gemeaux
Sllie 580
94653 Rungis Cedex
Tel: (33) (1) 49 78 49 78
TLX: 261585

~~~~o~9~~~ieres
4, avo Laurent-Cely
92606 Asnieres Cedex
Tel: (33) (1) 47 90 62 40
TLX: 611448
Tekelec-Airtronic
Cite des Bruyeres
Rue Carle Vernet - BP 2
92310Sevres
Tel: (33) (1) 45 34 75 35
TLX: 204552

ISRAEL
Eastronics Ltd.
11 Rozanis Street
P.O.B. 39300
Tel-Aviv 61392
Tel: (972) 03-475151
TLX: 33638

ITALY
Intesi
Divisione ITT Industries GmbH
Viale Milanofiori
Palazzo E/5

~~R9(g~g~~1~31

TLX: 311351

Lasi Elettronica S.pA
V. Ie Fulvio Testi, 126
20092 Cinisello Balsamo (MI)
Tel: (39) 0212440012
TLX: 352040
Telcom S.r.l.
Via M. Civilali 75
20148 Milano
Tel: (39) 0214049046
TLX: 335654
In Multicomponents
Viale Milanofiori E/5

~~R~g9')g~fs~1~31

TLX: 311351

Silverstar
Via Dei Gracchi 20
20146 Milano
Tel: (39) 02149961
TLX: 332189

NETHERLANDS
Koning en Hartman
Elektroteehniek B.V.
Energieweg 1
2627 AP Delft
Tel: (31) (1) 15/609906
TLX: 38250

fflX: 837931
UNITED KINGDOM

PORTUGAL
ATO Portugal LOA
Rua Dos Lusiados, 5 Sala B
1300 Lisboa
Tel: (35) (1) 64 80 91
TLX: 61562
Ditram
Avenida Miguel Bombarda, 133
1000 Lisboa
Tel: (35) (1) 54 53 13
TLX: 14182

SPAIN
ATD Electronica, SA
Plaza Ciudad de Viena, 6
28040 Madrid
Tel: (34) (1) 2344000
TLX: 42477

ITI-SESA
Calle Miguel Angel, 21-3
28010 Madrid
Tel: (34) (1) 419 09 57 '
TLX: 27461
Metrologia Iberica, SA
Clra. de Fuenearral, n.80
28100 Alcobendas (Madrid)
Tel: (34) (1) 653 86 11

SWEDEN
Nordisk Elektronik AB
Torshamnsgatan 39
Box 36
16493 Kista
Tel: (46) 08-03 46 30
TLX: 10547

SWIT2ERLAND
Industrade A.G.
Hertistrasse 31
8304 Wallisellen
Tel: (41) (01) 8328111
TLX: 56788

Rapid Recall, Ltd.
Rapid House
Oxford Road
High Wycombe
Buckinghamshire HP11 2EE
Tel: (44) (0494) 26271
FAX: (44) (0494) 21860

Accent Electronic Components Ltd.
Jubilee House-, Jubilee Road
Letchworth, Herts SG6 1QH
Tel: (44) (0462) 670011
FAX: (44) (0462) 682467

fflX: 826505
Bytech Components Ltd.
12A Cedarwood
Chineham Business fark
Crockford Lane
Basingstoke
Hanls RG24 OWD
Tel: (0256) 707107
FAX: 0256-707162
Conformix
Unit 5
AIM Business Centre
Dixons Hilt Road
Welham Green
South Hatfield
Herts AL9 7JE
Tel: (07072) 73282
FAX: (07072) 61678
Bytech Systems
3 The Western Centre
Western Road
Braeknell RGt2 tRW
Tel: (44) (0344) 55333
FAX: (44) (0344) 867270

fflX: 849624
Jermyn
Vestry Estate
Otford Road
Sevendaks
Kent TN 14 5EU
Tel: (44) (0732) 450144
FAX: (44) (0732) 451251

fflX: 95142
MMDUd.
3 Bennet Court
Bennet Road
Reading
Berkshire RG2 OQX
Tel: (44) (0734) 313232
FAX: (44) (0734) 313255

fflX: 846669

Rapid Recall, Ltd.
28 High Street
Nantwich
Cheshire CW5 5AS
Tel: (0270) 627505
FAX: (0270) 629883

fflX: 36329
WEST GERMANY
Electronic 2000 AG

~6~~%~~~~~~n

' :2
Tel: (49) 089/42001-0
TLX: 522561
ITT Multikomponent GmbH
Postfach 1265
Bahnhofstrasse 44
7141 Moeglingen
Tet: (49) 07141/4879
TLX: 7264472
Jermyn GmbH
1m Dachsstueck 9
6250 Limburg
Tel: (49) 06431/508-0
TLX: 415257-0
Metrologie GmbH
Meglingerstrasse 49
8000 Muenchen 71
Tel: (49) 089/78042-0
TLX: 5213189
Proelectron Vertriebs GmbH
Max Planck Strasse 1-3
6072 Dreieleh
Tel: (49) 06103/30434-3
TLX: 417903

YUGOSLAVIA
H.R. Microelectronics Corp.
2005 de la Cruz Blvd., Ste.223
Santa Clara, CA 95050
U_S.A.
Tel: (1) (408) 988-0286
TLX: 387452
Rapido Electronic Components
S.p.a.
Via C. Beccaria, 8
34133 Trieste
lIalia
Tel: (39) 040/360555
TLX: 460461

INTERNATIONAL SALES OFFICES
AUSTRALIA

INDIA

Intel Australia Ply. Ltd.
Unit 13
Allambie Grove Business Park
25 Frenchs Forest Road East
Frenchs Forest, NSW, 2086
Tel: 61-2975-3300
FAX: 61·2975-3375

Intel Asia Electronics, Inc.
4/2, Samrah Plaza
St. Mark's Road
Bangalore 560001
Tel: 011-91-612-215065
TLX: 953-845-2646 INTL IN

BRAZIL

JAPAN

Intel Semicondutores do Brazil LTDA
Av. Paulista, 1159-CJS 404/405
01311 - Sao Paulo - S.P.
Tel: 55-11-287-5899
TLX: 3911153146 lSDB
FAX: 55-11-287-5119

Inlel Japan K.K.
5-6 Takodai, Tsukuba·shi
Ibaraki, 300-26
Tel: 0298-47-8511
TLX: 3656-160
FAX: 0298-47-8450

CHINA/HONG KONG
Intel PAC Corporation
IS/F, Office 1, Cilie Bldg.
Jian Guo Men Wai Street
Beijing, PRC
Tel: (1) 500-4850
TLX: 22947 INTEL CN
FAX: (1) 500-2953
Intel Semiconductor Ltd. *
10fF East Tower
Bond Center
Queensway, Central
Hong Kong
Tel: (852) 844-4555
FAX: (852) 868-1989

fAX: 091-812-215067

Intel Japan KK.*
Daiichi Mitsugi Bldg.
1-8889 Fuchu-cho
Fuchu-shi, Tokyo 183
Tel: 0423-60-7871
FAX: 0423-60-0315
Intel Japan K.K *
Bldg. Kumagaya
2-69 Hon-cho
Kumagaya-shi, Saitama 360
Tel: 0485-24-6871
FAX: 0485-24-7516

~NTERNATIONAL
ARGENTINA
Dafsys S.R.L.
Chacabuco, 90-6 Piso
1069:Buenos Aires
Tel: 54-1-334-7726
FAX: 54-1-334-1871

AUSTRALIA
Email Electronics
15-17 Hume Street
Huntingdale, 3166
Tel; 011-61-3-544-8244
TLX: M30895
FAX: 011-61-3-543-6179
NSD-Australia
205 Middleborough Rd.
Box Hill, Victoria 3128
Tel: 03 8900970
FAX: 03 8990819

BRAZIL
Elebra Componenles
Rua Geraldo Flausina Gomes, 78
7 Andar
04575 - Sao Paulo - S.P.
Tel: 55-11-534-9641
TLX: 55-11-54593/54591
FAX: 55-11-534-9424

CHINA/HONG KONG
Novel Precision Machinery Co., Ltd.
Room 728 Trade Square
681 Cheung Sha Wan Road
Kowloon, Hong Kong
Tel: (852) 360-8999
TWX: 32032 NVTNL HX
FAX: (852) 725-3695

INDIA
Micronic Devices
Arun Complex
No. 65 D.V.G. Road
Basavanagudi
Bangalore 560 004
Tel: 011-91-812-600-631
011-91-812-611-365
TLX: 9538458332 MDBG

*Field Application Location

Intel Japan K.K.*
Kawa-asa Bldg.
2-11-5 Shin-Yokohama
Kohoku-ku, Yokohama-shi
Kanagawa, 222
Tel: 045-474-7661
FAX: 045-471-4394
Intel Japan K.K.*
Ryokuchi-Eki Bldg.
2-4-1 Terauchi
Toyonaka-shi. Osaka 560
Tel: 06-863-1091
FAX: 06-863-1084
Intel Japan KK
Shinmaru Bldg.
1-5-1 Marunouchi
Chiyoda-ku, Tokyo 100
Tei: 03-201-3621
FAX: 03-201·6850

SINGAPORE
Intel Singapore Technology, Ltd.
101 Thomson Road #21-05/06
United Square
Singapore 1130
Tel: 250-7811
TLX: 39921 INTEL
FAX: 250-9256

TAIWAN
Intel Technology Far East Ltd.
8th Floor, No. 205
Bank Tower Bldg.
Tung Hua N. Road
Taipei
Tel: 886-2-716-9660
FAX: 886-2-717-2455

Intel Japan K.K.
Green Bldg.
1-16·20 Nishiki
Naka-ku, Nagoya-shi
Aichi 450
Tel: 052-204-1261
FAX: 052-204-1285

KOREA
Intel Technology Asia, Ltd.
16th Floor, Life Bldg.
61 Yoido-dong, Youngdeungpo-Ku
Seoul 150-010
Tel: (2) 784-8186_ 8286, 8386
TLX: K29312 INTELKO
FAX, (2) 784-8096

DISTRIBUTORS/REPRESENTATIVES

Micronic Devices
No. 516 5th Floor
Swastik Chambers
Sian, Trambay Road
Chembur
Bombay 400 071
TLX: 9531 171447 MDEV
Micronic Devices
2518, 1sl Floor
Bada Bazaar Marg
Old Rajinder Nagar
New Delhi 110060
Tel: 011-91-11-5723509
011-91-11-589771
TLX: 031-63253 MDND IN
Micronic Devices
6-3·348/12A Dwarakapuri Colony
Hyderabad 500 482
Tel: 011-91-842-226748
S&S Corporation
1587 Kooser Road
San Jose, CA 95118
Tel: (408) 978-621.6
TLX: 820281
FAX: (408) 978-8635

Okaya Koki
2-4-18 Sakae
Naka-ku, Nagoya-shi 460
Tel: 052-204-2916
FAX: 052-204-2901
Ryoyo Electro Corp.
Konwa Bldg.
1-12-22 Tsukiji
Chuo-ku, Tokyo 104
Tel: 03-546-5011
FAX: 03-546-5044

KOREA
J-Tek Corporation
Dong Sung Bldg. 9/F
158-24, Samsung-Dong, Kangnam-Ku
Seoul 135-090
Tel: (822) 557-8039
FAX: (822) 557-8304
Samsu ng Electronics
Samsung Main Bldg.
150 Taepyung-Ro-2KA, Chung-Ku
Seoul 100-102
C.P.O. Box 8780
Tel: (822) 751-3680
TWX: KORSST K 27970
FAX: (822) 753-9065

JAPAN

MEXICO

Asahi Electronics Co. Ltd.
KMM Bldg. 2-14-1 Asano
Kokurakita-ku
Kitakyushu-shi 802
Tel: 093-511-6471
FAX: 093-551-7861

SSB Electronics, Inc.
675 Palomar Street, Bldg. 4, Suite A
Chula Vista, CA 92011
Tel: (619) 585-3253
TLX: 287751 CBALL UR
FAX: (619) 585-8322

CTC Components Systems Co., Ltd.
4-8- ~ Do~ashi, Miyamae-ku
Kawasakl-shi, Kanagawa 213
Tel: 044-852-5121
FAX: 044-877-4268

Dicopel SA
Tochtli 368 Fracc. Ind. San Antonio
Azcapotzalco
C.P. 02760-Mexico, D.F.
Tel: 52-5·561-3211
TLX: 177 3790 Dicome
FAX: 52-5-561-1279

Dia Semicon Systems, Inc.
Flower Hill Shinmachi Higashi-kan
1-23-9 Shin machi, Setagaya-ku
Tokyo 154
Tel: 03-439-1600
FAX: 03-439-1601

PHI SA de C_V.
Fco. Villa esq. Ajusco sin
Cuernavaca - Morelos
Tel: 52-73-13-9412
FAX: 52-73-17-5333

NEW ZEALAND
Email Electronics
36 Ollve Road
Penrose, Auckland
Tel: 011·64-9-591-155
FAX: 011-64-9-592-681

SINGAPORE
Electronic Resources Pte, Ltd.
17 Harvey Road
#03-01 Singapore 1336
Tel: (65) 283-0888
TWX: RS 56541 ERS
FAX: (65) 289-5327

SOUTH AFRICA
Electronic Building Elements
178 Erasmus St. (off Watermeyet St.)
Meyerspark, Pretoria, 0184
Tel: 011-2712-803-7680
FAX; 011-2712-803-8294

TAIWAN
Micro Electronics Corporation
12th Floor, Section 3
285 Nanking East Road
Taipei, RO.C.
Tel: (886) 2-7198419
FAX: (886) 2-7197916
Acer Sertek Inc.
15th Floor, Section 2
Chien Kuo North Rd.
Taipei 18479 RO.C.
Tel: 886-2-501-0055
TWX: 23756 SERTEK
FAX: (886) 2-5012521

DOMESTIC SERVICE OFFICES
ALASKA

CONNECTICUT

MARYLAND

NEW YORK

PUERTO RICO

Intel Corp.
c/o TransAlaska Network
1515 Lore Rd.
Anchorage 99507
Tel: (907) 522-1776

"'Intel Corp.
301 Lee Farm Corporate Park
83 Wooster Heights Rd.
Danbury 06811
Tel: (203) 748-3130

"*Intel Corp.
10010 Junction Dr., Suite 200
Annapolis Junction 20701
Tel: (301) 206-2860

"'Intel Corp.
2950 Expressway Dr. South
Suite 130
Islandia 11722
Tel: (516) 231-3300

Intel Corp.
South Industrial Park

Intel Corp.
c/o TransAlaska Data Systems

FLORIDA

MASSACHUSETIS

Intel Corp.
Westage Business Center
Bldg. 300, Route 9
Fishkill 12524
Tel: (914) 897-3860

clo Gel Operations
520 Fifth Ave., Suite 407
Fairbanks 99701
Tel: (907) 452-6264
ARIZONA
*Intel Corp.
410 North 44th Street
Suite 500
Phoenix 85008
Tel: (602) 231-0386
FAX: (602) 244-0446
*Intel Corp.
500 E. Fry Blvd., Suite M-15
Sierra Vista 85635
Tel: (602) 459-5010
ARKANSAS
Intel Corp.
c/o Federal Express
1500 West Park Drive
Little Rock 72204
CALIFORNIA
*Intel Corp.
21515 Vanowen St., Ste. 116
Canoga Park 91303
Tel: (818) 704-8500
*Intel Corp.
300 N~ Continental Blvd.
Suite 100
El Segundo 90245
Tel: (213) 640-6040
*Intel Corp.
1900 Prairie City Rd.
Folsom 95630-9597
Tel: (916) 351-6143
*Intel Corp.
9665 Chesapeake Dr., Suite 325
San Diego 92123
Tel: (619) 292-8086
**Intel Corp.
400 N. Tustin Avenue
Suite 450
Santa Ana 92705
Tel: (714) 835-9642
**Intel Corp.
2700 San Tomas Exp., 1st Floor
Santa Clara 95051
Tel: (408) 970-1747

"'*Intel Corp.
800 Fairway Dr., Suite 160
Deerfield Beach 33441
Tel: (305) 421-0506
FAX: (305) 421-2444

'**Intel Corp.
Westford Corp. Center
3 Carlisle Rd., 2nd Floor
Westford 01886
Tel: (508) 692-0960

"Intel Corp.
5850 T.G. Lee Blvd., Ste. 340
Orlando 32822
Tel: (407) 240-8000

MICHIGAN

GEORGIA
*Intel Corp.
20 Technology Park, Suite 150
Norcross 30092
Tel: (404) 449-0541
5523 Theresa Street
Columbus 31907

*Intel Corp.
7071 Orchard Lake Rd., Ste. 100
West Bloomfield 48322
Tel: (313) 851-8905
MINNESOTA
*Intel Corp.
3500 W. 80th St., Suite 360
Bloomington 55431
Tel: (612) 835-6722

HAWAII

MISSISSIPPI

**Intel Corp.
Honolulu 96820
Tel: (808) 847-6738

Intel Corp.
c/o Compu-Care
2001 Airport Road, Suite 205F
Jackson 39208
Tel: (601) 932-6275

ILLINOIS
.. *tlntel Corp.
Woodfield Corp. Center III
300 N. Martingale Rd., Ste. 400
Schaumburg 60173
Tel: (708) 605-8031

MISSOURI

INDIANA

"Intel Corp.
4203 Earth City Exp., Ste. 131
Earth City 63045
Tel: (314) 291-1990

*Intel Corp.
8910 Purdue Rd., Ste. 350
Indianapolis 46268
Tel: (317) 875-0623

Intel Corp.
Route 2, Box 221
Smithville 64089
Tel: (913) 345-2727

KANSAS

NEW JERSEY

*Intel Corp.
10985 Cody, Suite 140
Overland Park 66210
Tel: (913) 345-2727

**Intel Corp.
300 Sylvan Avenue
Englewood Cliffs 07632
Tel: (201) 567-0821

KENTUCKY

*Intel Corp.
Parkway 109 Office Center
328 Newman Springs Road
Red Bank 07701
Tel: (201) 747-2233

Intel Corp.
133 Walton Ave .. Office lA
Lexington 40508
Tel: (606) 255-2957

COLORADO

Intel Corp.
896 Hillcrest Road, Apt. A
Radcliff 40160 (Louisville)

*Intel Corp.
600 S. Cherry St., Suite 700
Denver 80222
Tel: (303) 321-8086

Hammond 70401
(serviced from Jackson, MS)

CALIFORNIA

MARYLAND

2700 San Tomas Expressway
Santa Clara 95051
Tel: 1-800-328·0386

10010 Junction Dr.
Suite 200
Annapolis Junction.20701
Tel: 1-800-328-0386

LOUISIANA

NEW MEXICO
Intel Corp.
Rio Rancho' 1
4100 Sara Road
Rio Rancho 87124-1025
(near Albuquerque)
Tel: (505) 893-7000

Intel Corp.
5858 East Molloy Road
Syracuse 13211
Tel: (315) 454-0576
NORTH CAROLINA
"'ntel Corp.
5800 Executive Center Drive
Suite 105
CharloHe 28212
Tel: (704) 568-8966
.... Intel Corp.
5540 Centerview Dr., Suite 215
Raleigh 27606
Tel: (919) 851-9537
OHIO

NEW YORK
2950 Expressway Dr., South
Islandia 11722
Tel: (506) 2.31-3300

*Carry-in locations
**Carry-in/mail-in locations

**Intel Corp.
Westech 360, Suite 4230
8911 Capitol of Texas Hwy.
Austin 78752-1239
Tel: (512) 794-8086
....tlntel Corp.
12000 Ford Rd., Suite 401
Dallas 75234
Tel: (214) 241-8087
**Intel Corp.
7322 SW Freeway, Suite 1490
Houston 77074
Tel: (713) 988-8086
UTAH
Intel Corp.
428 East 6400 South
Suite 104
Murray 84107
Tel: (801) 263-8051
FAX: (801) 268-1457
VIRGINIA
*Intel Corp.
1504 Santa Rosa Rd., Ste. ·108
Richmond 23288
Tel: (804) 282-5668

*Intel Corp.
25700 Science Park Dr., Ste. 100
Beachwood 44122
Tel: (216) 464-2736

WASHINGTON

OREGON
**Intel Corp.
15254 N.W. Greenbrier Parkway
Building B
Beaverton 97005
Tel: (503) 645-8051
PENNSYLVANIA
*tlntel Corp.
925 Harvest Drive
Suite 200
Blue Bell 19422
Tel: (215) 641-1000
1-800-468-3548
FAX: (215) 641-0785
**tlntel Corp.
400 Penn Center Blvd., Ste. 610
Pittsburgh 15235
Tel: (412) 823-4970
*Intel Corp.
1513 Cedar Cliff Dr.
Camp Hill 17011
Tel: (717) 761-0860

SYSTEMS ENGINEERING OFFICES
MINNESOTA

TEXAS

**Intel Corp.
3401 Park Center Dr., Ste. 220
Dayton 45414
Tel: (513) 890-5350

CUSTOMER TRAINING CENTERS

3500 W. 80th Street
Suite 360
Bloomington 55431
Tel: (612) 835-6722

P.O. Box 910

Las Piedras 00671
Tel: (809) 733-8616

**Intel Corp.
155 108th Avenue N.E., Ste. 386
Bellevue 98004
Tel: (206) 453-8086

CANADA
ONTARIO
**Intel Semiconductor of
Canada, Ltd.
2650 Queensview Dr., Ste. 250
OHawa K2B 8H6
Tel: (613) 829-9714
**Intel Semiconductor of
Canada, Ltd.
190 Attwell Dr., Sle. 102
Rexdale (Toronto) M9W 6H8
Tel: (416) 675-2105
QUEBEC
**Intel Semiconductor of
Canada, Ltd.
1 Rue Holiday
Suite 115
Tour East
Pt. Claire H9R 5N3
Tel: (514) 694-9130
FAX: 514-694-0064

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