1991_Motorola_ECLin PS_Data 1991 Motorola ECLin PS Data

User Manual: 1991_Motorola_ECLinPS_Data

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Numeric Index
General Information
ECIJ:PS

Family Specifications
& Device Data Sheets
Design Guide

This databook contains device specifications for
Motorola's ECLinPS advanced ECL logic family.
ECLinPS (ECL in picoseconds) was developed in
response to the need for an even higher performance ECL
family of standard logic functions, particularly in the Computer, Automated Test, Instrumentation and Communications
industries. Family general features as well as specific functions were developed in close consultation with ECL systems
design engineers.
ECUnPS offers the user a single gate delay of 500
ps max., including package delay, and a flip-flop toggle
frequency of 1100 MHz.
ECUnPS is compatible with two different ECL standards. Each function is available with either MECL 10KH
compatibility (MC10Exxx series) or 100K compatibility
(MC100Exxx series).
ECUnPS is offered in the 28-lead plastic leaded chip
carrier (PLCC), a J-Iead surface mount IC package. This
package was selected for high performance, reduced parasitics and good thermal handling in a low cost, standard
package, and reflects an industry trend towards surface
mount assembly.

Suggested References:

The user is referred to the following for general information on the MECL and 100K ECL families:
Motorola MEeL Device Data Book, Motorola Inc., 1987. Stock code DL122/D.
F100K EeL Data Book, Fairchild Camera and Instrument Corp.
Motorola MEeL System Design Handbook, second edition. Motorola Inc., 1983. Stock code HB205RlID.
Signetics EeL 10K/toOK Data Manual.

ECLinPS

MOSAIC, MECL 10K and MECL 10KH are trademarks of Motorola Inc.

©MOTOROLA INC .. 1991

Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume
any liability arising out afthe application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights
of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure afthe Motorola product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola,
Inc. is an Equal Opportunity/Affirmative Action Employer.

ECLinPS

Numeric Index

This section lists ECUnPS family functions in numericalorder.
MC10E series devices are compatible with the MECL
10KH family. MC100E series are compatible with toOK ECL.

ECLinPS
1-1

ECl:PS
Numeric Index
Numeric Index
MC101
MC100
E016
El0l
El04
El07
E111
El12
El16
E122
E131
E136
E137
E141
E142
El43
E150
E151
1:154
E155
E1!i6
E157
E158
E160
E163
E164

Function

Page

8-Bit Synch. Binary Counter
QUAD 4-lnput OR/NOR Gate
QUINT 2-lnput AND/NAND Gate
QUINT 2-lnput XOR/XNOR Gate
1:9 Differential Clock Driver
QUAD Driver, Common Enable
QUINT Diff. Line Receiver
9-Bit Buffer
4-Bit 0 Flip-Flop
6-Bit Universal Counter
8-Bit Ripple Counter
8-Bit Universal Shift Register
9~Bit Shift Register
9-Bit Hold Register
6-Bit 0 Latch
6-Bit 0 Register
5-Bit,.2: 1 Mux Latch
. 6-Bit 2: 1 Mux Latch
3-Bit 4: 1 Mux Latch
QUAD 2:1 Mux, Separate Selects
5-Bit ;1:1 Multiplexer
12-Bit Parity Gen/Checker
2-Bit 8: 1 Multiplexer
16:1 Multiplexer

3-3
3-9
3-11
3-13
3-15
3-18
3-20
3-22
3-24
3-26
3-27
3-28
3-30
3-32
3-34
3-36
3-38
3-40
3-42
3-44
3-46
3-48
3-50
3-52

MC101
MC100

Function

Page

E166
E167
E171
E175
E193
E195
E196
*E197
E212
E241
E256
E336
E337
E404
E416
E431
E445
E446
E451
E452
E457
*E1651
*E1652

9-Bit Magnitude Comparator
6-Bit2: 1 Mux Register
3-Bit 4:1 Multiplexer
9-Bit Latch w/Parity Gen/Checker
8-Bit EDAC/Parity
Programmable Delay Chip
Programmable Delay Chip
High Speed Data Separator
3-Bit Scannable ECL Driver
8-Bit Scannable Register
3-Bit 4: 1 Mux Latch
3-Bit Registered Bus Xcvr
3-Bit Scannable Bus Xcvr
QUAD High Freq. Diff. AND
QUINT High Freq. Line Receiver
3-Bit Diff. Set/Reset Flip-Flop
1:4 Serial/Paraliel Converter
4: 1 Parallel/Serial Converter
6-Bit 0 Reg. Diff. 0 and Clk
5-Bit 0 Reg. Diff. 0, Clk and Q
TRIPLE High Freq. Diff. 2: 1 Mux
Dual Analog Comparator
Dual Analog Comparator

3-54
3-56
3-58
3-60
3-62
3-64
3-68
3-73
3-87
3-89
3-91
3-93
3-95
3-98
3-100
3-102
3-104
3-105
3-106
3-108
3-110
3-112
3-114

*10E version only

Nomenclature

MC 10 E xxx FN
MC 100 E xxx FN

Motorola Standard Prefix
• XC - non reliability-qualified
• MC - fully qualified

_." ,mo,
• FN -

PLCC package

3-digit function identifier

Compatibility Identifier
·10 - MECL 10KH compatible
·100 - lOOK compatible

.....- - - - ECLinPS family identifier

ECLinPS

1-2

Selection Guide
Gates

Quad 4-lnput OR/NOR
Quint 2-lnput AND/NAND
Quint 2-lnput XOR/XNOR
Quad 2-lnput AND/NAND, Differential

Counters

8-Bit Synchronous Binary Counter
6-Bit Synchronous Universal Counter
8-Bit Triple Counter

El0l
El04
El07
E404

E016
E136
E137

Shift Registers
Buffers

9-Bit Buffer
1:9 Differential Clock Driver
Quad Driver with Enable
3-Bit Scannable Driver

8-Bit
8-Bit
9-Bit
9-Bit
3-Bit

E122
Ell1
El12
E212

Flip-Flops/Registers

4-Bit
6-Bit
6-Bit
9-Bit
3-Bit
5-Bit

D (Async Set/Reset)
D (Async Reset)
D, Diff. Data & CLK Inputs
Hold Register
D, Edge Triggered Set & Reset
Diff. DReg.

E141
E241
E142
E143
E212

Parity Generator/Comparator

12-Bit Parity Generator/Checker
9-Bit Magnitude Comparator
8-Bit Error Detection/Correction (EDAC)
9-Bit Latch w/Parity Gen/Checker

E131
E151
E451
E143
E431
E452

E160
E166
E193
E175

Line Receivers

Quint Differential Line Receiver
1:9 Differential Clock Driver
6-Bit DReg., Diff. Data & CLK Inputs
Quint High Freq. Differential Line Receiver
5-Bit Diff. DReg.

Latches

6-Bit D (Async Reset)
9-Bit Latch w/Parity Gen/Checker

Shift Register (bidirectional)
Scannable Register (unidirectional)
Shift Register (unidirectional)
Hold Register
Scannable Driver

E150
E175

E116
Elll
E451
E416
E452

Multiplexers
Bus Transceivers

5-Bit 2:1 Multiplexer
3-Bit 4: 1 Multiplexer
2-Bit 8: 1 Multiplexer
Single 16:1 Multiplexer
Quad 2:1 Mux, Indiv. Select
Triple 2: 1 Mux, Differential

E158
E171
E163
E164
E157
E457

3-Bit Registered Bus XCVR
3-Bit Scannable Reg. Bus XCVR
Miscellaneous

Dual Analog Comparator w. Latch
Dual Analog Comparator w. Latch & Hysteresis
Programmable Delay Chip, Digital
Programmable Delay Chip, Digital & Analog
Hard Disk Data Separator
1:4 Serial/Parallel Converter
4:1 Parallel/Serial Converter

Mux-Latches

5-Bit
6-Bit
3-Bit
3-Bit

2:1 Mux-Latch
2: 1 Mux-Latch
4:1 Mux-Latch
4: 1 Mux-Latch

E154
E155
E156
E256

Mux-Registers

6-Bit 2:1 Mux-Register

E336
E337

E167

ECLinPS
1-3

E1651
E1652
E195
E196
E197
E445
E446

ECLinPS

1-4

General Information

CONTENTS

This section contains a technical overview of the
ECUnPS family as well as an outline of its electrical characteristics. In addition the section outlines the procedures
and philosophies used to AC test the family.

Family Overview . ....................... 2-2
Electrical Characteristics . ................ 2-7

ECLinPS
2-1

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
GENERAL INFORMATION

Family Overview

SECTION 1
Family Overview

Introduction

system power and board space while maintaining exceptional system timing.

Recent advances in bipolar processes have led to a
proliferation of very high speed lSI and VlSI gate arrays in
high end computer applications. The advent of these high
speed arrays has created a need for a high speed logic family
to tie or "glue" them together. Because arrays have a finite
amount of circuitry and 1/0 pins, glue functions which are
sensitive to either of these parameters may be better performed off of the array. In addition glue functions which
require very tight skew control may be difficult to perform on
an array due to the inherent skew of the large packages
associated with large gate arrays. Therefore although the
trend is to push more and more of the logic onto the array,
there are design constraints which make performing some of
the logic, such as clock distribution, multiplexing, decoding,
latching, memory addressing and translating, in glue an
attractive alternative.
The high end computer segment is not the only market
segment pushing for higher performance logic parts. ATE,
instrumentation and communication designs can have data
rate requirements ranging from 300MHz to as high as
2.5GHz. Because large high speed arrays do not always
lend themselves to passing high frequency signals on and off
chip, portions of the designs must be realized with discrete
logic. The current bipolar logic families are not capable of
operating at these high frequencies.
To answer the call for a very high speed bipolar logic
family Motorola has designed and produced the ECLinPS
(ECl in Pica Seconds) logic family. The family was designed
to meet the most stringent of system requirements in speed,
skew and board density as well as maintaining compatibility
to existing ECl families.

Transmission line Drive Capability
The low output impedance, high input impedance and
high current drive cilpability of ECl makes it an ideal
technology for driving transmission lines. Regardless of the
technology, as system speeds increase, interconnect becomes more of a transmission line phenomenon. With ECl
no special line driving devices are necessary as all ECl
devices are line drivers.
Constant Power Supply Current Drain
Because of the differential amplifier design used for
ECl circuits the current is not switched on and off but rather
simply steered between two paths. Thus the current drain of
an ECl device is independent of the logic state and the
frequency of operation. This current stability greatly simplifies system power supply design.
Input Pulldown Resistors
ECl inputs have 50Kn - 75Kn internal pulldown resistors which pull the input to VEE (logic lOW) when left open.
This allows unused inputs to be left open and greatly
simplifies logic design.
Differential Drive Capability
Because of the presence of high current drive complimentary outputs, ECl circuits are ideally suited for driving
twisted pair lines or cables over long distances. With common mode noise rejection of 1V or more ECl line receivers
are less susceptible to common mode noise. In addition their
differential inputs need only a few hundred millivolt voltage
differences to correctly interpret the logic.

Eel Design Benefits
High Speed Design Philosophy
The speed benefits of an ECl design over those of
alternative logic technologies are well documented, however there are a number of other important features that
make ECl an attractive technology for system designs. The
ECLinPS logic family as with other ECl families afford the
following advantages:

Today a truly high speed logic family needs more than
simply short propagation delays. The minimization of all
types of skew as well as a level of logic density which affords
a smaller amount of board space for an equivalent function
are also necessities of a high speed family. The following
summary will outline the steps taken by Motorola to achieve
these goals in the development of the ECLinPS logic family.

Complimentary Outputs
Complimentary outputs are available on many functions with equal propagation delays between the two paths.
This alleviates the need for external inverters and saves

Fast Propagation Delays
The ECLinPS family boasts 500ps maximum packaged

ECLinPS

2-2

Family Overview
ing situations a minimum of three single ended outputs per
Veeo has been employed in the family. Optimum placement of these Vceo's also results in superior output to
output skew.

gate delays and typical flip flop toggle frequencies of 1 AGHz.
Simple gate functions show typical propagation delays of
360ps at 25mW of power for a speed power product of only
9pJ. For higher density devices internal gates run at 100ps
with 5mW of power for a speed power product of only .5pJ.

Advanced Bipolar Processing
Internal Differential Interconnect
The propagation delay window size, skew between
rising and falling inputs and susceptibility to noise are all
phenomenon which are exacerbated by Vss switching reference variation. By extensively using differential interconnects internal to the chip the ECLinPS family has been able
to achieve superior performance in these areas.

The ECLinPS logic family is fabricated using Motorola's
MOSAIC III process, a process which is two generations
ahead of the process used in the development of the 10KH
family. The small geometries and feature sizes ofthe MOSAIC
III process enables the ECLinPS logic family to boast of a
nearly 3 fold improvement in speed at less than half the
power of existing ECl logic families.
The MOSAIC III process is a double polysilicon process
which uses a unique self-alignment scheme for device
electrode and isolation definition. The process features self
aligned submicron emitters as well as polysilicon base,
collector and emitter electrodes. In addition polysilicon resistors, diodes and capacitors are available to minimize the
parasitic capacitance of an ECl gate. Figure 1.1 shows a
cross section for an NPN device using the MOSAIC III
process.

Propagation Delay Temperature Insensitivity
The variation of propagation delay through an ECLinPS
device across temperature is typically less than 50ps. This
stability allows for faster designs due to tighter delay windows across temperature.
Input impedance and Loading Capacitance
The input structures of the ECLinPS family show a
positive real impedance across the applicable input frequency range. This ensures that the system will remain
stable and operate as designed over a wide range of input
frequencies. The input loading capacitance typically measures only 1.5pF and is virtually independent of input fanout
as the device capacitance is less than 5% of the total.
Because the propagation delay of a signal down a transmission line is adversely affected by loading capacitance the
overall system speed is enhanced.
Input Buffers
To minimize propagation delays in a system environment, inputs with a large internal fanout are buffered to
minimize the loading capacitance on the transmission line.

Figure 1.1 - MOSAIC III Cross Section

High Level of Integration
28 pin designs allow for the design of 9 bit functions for
implementation in byte plus parity applications. Full byte plus
parity implementation reduces total package count and
saves expensive board space.

By incorporating the use of polysilicon contacts and
resistors through the MOSAIC III process, the parasitic
capacitances of an ECLinPS gate are minimized, thus
minimizing the time constants which comprise the switching
delays of the gate. The resultant gates show delays of 100ps
for internal gates and 200ps for output gates capable of
driving son loads. The small geometries of the process,
nearly 350% reduction in device area compared to a 10KH
device, allows these internal gate delays to be achieved at
only 800flA of current.

Space Efficient Package
Surface mount PlCC package affords a high level of
integration with a minimum amount of required board space.
Quad layout of the package equalizes pin lengths thus
minimizing the skew between similar internal paths.

Universal Compatibility

Flow Through Pin Assignment
Input and output pins have been laid out in a flow
through pattern with the inputs on one side of the package
and the outputs on the other. This flow through pattern helps
to simplify the PC board layout operation.

Each member of the ECLinPS family is available in both
of the existing ECl standards: 10E series devices are
compatible with the MECl 1OKH family; 1OOE series devices
are compatible with ECl 100K. In addition, to maintain
compatability with temperature compensated, three level
series gated gate arrays the 1OOE devices are guaranteed to

Multiple VCCO pins
To minimize the noise generated in simultaneous switch-

ECLinPS

2-3

Family Overview
operate without degradation to a VEE of -S.46V.
The section below presents comparison between thE!
two standards in the new context of. the ECLinPS family. The
user is also referred to the Electrical Characteristics section
of this book as well as appropriate family databooks and
other literature for descriptive information on the earlier ECl
families.
Because no supplier previous to Motorola has offered
both EClstandards on an identical process, comparison of
existing 1OKH and 1OOK style devices has some limitations.
Comparison of the two standards fabricated withtwd different processes has sometimes led to the errone'ous conclusion that there are inherent ACperformance differences
between them. In reality this is not the case. The only
inherent difference between the two standards is the difference in the behavior of the DC characteristics with temperature.

and board space problems, the propagation delays through
the DIP package were nearly twice as long as the delay
through the silicon.
The 28 pin PlCC package emerged as the clear favorite
both internally and with the high speed market in general.
The package offers a quad layout to minimize both lead
lengths and lead length differences. As a result the parasitics and delays of the package are very well suited for a
high speed logic family. In additionthe nearly matched lead
lengths allow for tighter skew among similar paths through
the Chip.
The board density potential of the PlCC is also attractive in that it allows for a nearly 100% reduction in board
space when compared to the DIP alternative. The package
is approximately a half inch square with SO mil spaced Jbend leads. More detailed measurements can be found in
the package section of this databook. The J bend leads
provide a smaller footprint than a gull wing package and
propose fewer temperature expansion coefficient mismatch
problems than the lead less alternative.
Thermally the standard PlCC exhibits a ElJA of 43.SoC
per watt at SOO Ifpm air flow. With this thermal resistance
most 28 pin functions can be implemented with the MOSAIC
III process without encountering any severe thermal problems. For more details on thermal issues of the ECLinPS
family refer to the thermal section of this databook.

AC Performance
From an IC design standpoint the only differences
between a 10E device and a100E device in the ECLinPS
family is a small temperature compensation network in the
100E output gate, and very minimal differences in the two
bias generator networks. Therefore one would expect that
from an AC standpoint the performance of the two standards
in the ECLinPS family should be nearly identical; measurements prove this to be the case. There is no significant
measurable difference in the riselfall times, propagation
delays or toggle frequencies when comparing a 10E and
1OOE device. The minor difference between previous 10KH
and 100K designs is due to the fact that the two are
fabricated on differentprocE!sses, and in some cases are
designed for operation at different power levels.

Abbreviation Definitions
The following is a list of abbreviations found in this
databook and a brief definition of each.

Current

Summary

Total power supply current drawn from .the pOSitive supply by an ECLinPS unit under test.

Summarizing the above information; in general the two
ECl design standards, although differing somewhat in DC
parameters, are nearly identical when one compares the AC
performance for a given device. There may be very small
differences in the AC measurements due to the slightly
smaller output swing of the 100E device. However these
difference are negligible when compared to the absolute
value of the measurements. Therefore from an AC standpoint there is no real advantage in using one standard over
the other, thus removing AC performance as a decision
variable in high speed system design,

Total power supply current drawn from an EClinPS device under test by the negative supply.
Current drawn by the input of an ECLinPS device with a specified low level (Vll min) forced on
the input.
Current drawn by the input of an ECLinPS device with a specified high level (VIH max) forced
on the input.

Packaging

The current sourced by an output under specified load.conditions.

During the definition phase of the ECLinPS family much
attention was placed on the identification of a suitable
package for the family. The package h.ad to meet the criteria
of minimum parasitics and propagation delays along with an
attractive I/O vs board space relationship. Although the DIP
package offered a level of familiarity and convenience the
performance of the package with a very high speed logic
family was inadequate. In addition to the obvious parasitics

Voltage
VBB

The switching reference voltage
Base-to-emitter voltage drop of a transistor at

ECLinPS

2-4

Family Overview
specified collector and base currents.
Vpp

Minimum peak to peak input voltage for differential input devices.

VeMR

The voltage range in which the logic HIGH voltage level of a differential input signal must fall
for a differential input device.

Power supply connection to the output emitter
follower of an ECLinPS gate. For the ECLinPS
logic family VCC and VCCO are common nodes.

VeuT

The logic LOW voltage level for ECL BUS outputs which attain cutoff of the output emitter follower.

VEE

The most negative supply voltage to an ECLinPS
device.

Vsup

The maximum voltage difference between VEE
and VCC for the E1651 comparator.

V ,H

Nominal input logic HIGH voltage level.

Timing Parameters

V ,H max

Maximum (most positive) logic HIGH voltage level for which all parametric specifications hold.

Waveform rise time of an output signal measured from the 20% to 80% levels of the signal.

V ,H min

Minimum (least positive) logic HIGH voltage level for which all parametric specifications hold.

Waveform fall time of an output signal measured
from the 20% to 80% levels of the signal.

V'l

Nominal input logic LOW voltage.

TpD±±

Propagation delay of a signal measured for a
rising/falling input to a rising/falling output.

V'l max

Maximum (most positive) logic LOW voltage level for which all parametric specifications hold.

xpt

The crossing point of adifferential input or output
signal. The reference point for which differential
delays are measured.

TplH

The propagation delay for an output transitioning from a logic LOW level to a logic HIGH level.

TpHl

The propagation delay for an output transitioning from a logic HIGH level to a logic LOW level.

f MAX

Maximum input frequency for which an ECLinPS
flip flop will function correctly.

feouNT

Maximum input frequency for which an ECLinPS
counter will function properly.

fSHIFT

Maximum input frequency for which an ECLinPS
shift register will function properly.

tSKEW

The maximum delay difference between similar
paths on a single ECLinPS device.

Setup time; the minimum amount oftime an input
must transition before a clock transition to ensure proper function of the device.

Hold time: the minimum amount of time an input
must remain asserted after a clock transition to
ensure proper operation of the device.

tRR

Release time or Reset Recovery Time; the mini

Ves

Collector-to-base voltage drop of a transistor at
specified collector and base currents.

Vee

The most positive supply voltage to an ECLinPS
device.

Veeo

V,lmin

Minimum (least positive) logic HIGH voltage level for which all parametric specifications hold.

V OH

Output logic HIGH voltage level for the specified
load condition.

VOHA

Output 10gic.HIGH voltage level with the inputs
biased at VIH min or VOL max.

VOH max

Maximum (most positive) logic HIGH output volItage level.

V OH min

Minimum (least positive) logic HIGH output voltagelevel.

Val

Output logic LOW voltage level for the specified
load condition.

VOLA

Output logic LOW voltage level with the inputs
biased at VIH min or VOL max.

Val max

Maximum (most positive) logic LOW output
voltage level.

Val min

Minimum (least positive) logic LOW output
voltage level.

VTT

Output termination voltage for ECLinPS open
emitter follower outputs.

ECLinPS
2-5

Family Overview
mum amount of time after a signal is de-asserted
that a different input must wait before assertion
to ensure proper functionality of the device.

min

kage between the case and the ambient.
Ifpm

Linear feet per minute.

Miscellaneous

Minimum pulse width of a signal necessary to ensure proper functionality of a device.

D.U.T.

Device under test.

G'N

Input capacitance of a device.

Z'N

Input impedance of a device.

GOUT

Output capacitance of a device.

Temperature
The maximum temperature at which a device
may be stored without damage or performance
degradation.
Junction (or die) temperature of an integrated
circuit device.

Output impedance of a device.

Ambient (environment) temperature existing in
the immediate vicinity of an integrated circuit
package.

The total dc power applied to a device, not including any power delivered from the device to
the load.

Thermal resistance of an integrated circuit package between the junction and the ambient.

Load resistance

RT
Thermal resistance of an integrated circuit package between the junction and the case.

Transmission line termination resistor.
An input pull-down resistor.

P.U.T.

Thermal resistance of an integrated circuit pac-

ECLinPS

2-6

Pin under test.

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
GENERAL INFORMATION

Electrical Characteristics

SECTION 2

Electrical Characteristics

DC Characteristics

The 10E devices are voltage compensated but not
temperature compensated, therefore although the output
voltage levels are insensitive to variations in VEE they do vary
with temperature. The transfer curves in Figure 2.2 pictorially illustrate the behavior of the 10E outputs. In order to
maintain noise margins overtemperature it is important that
the VBB switching reference tracks with temperature in such
a way as to remain centered between the VOH and VOL levels.
As shown in Table 2.1 the temperature tracking rates of the
V OH and VOL for a 10E device are not equal. Therefore it is

ECLinPS Transfer Curves
As mentioned in the previous section, except for the
E16S1, E16S2 and E197 all ECLinPSdevices are offered in
either 1OE or 1OOE versions to be compatible with 1OKH or
100K ECl logic respectively. The following information will
overview the DC characteristics of the two versions of
ECLinPS devices, for more detailed discussions the reader
is referred to the MECl and F100K databooks.
Both 10E and 100E devices produce =800mV output
swings into a specified SOQ to -2.0V load. However because
of the low output impedance (Figure 2.1) of both standards
neither is limited to SOQ loads. larger load resistances can
be used to reduce the system power without sacrificing the
speed of the device. Of course the overall system speed will
be reduced due to the increased delays of the interconnect
traces. In addition, to better drive high capacitive lines,
smaller resistances, down to 2SQ, can be used without
violating the SOmA max output current specification. It is
however recommended that for lines of less than 3SQ
specialized 2SQ driver circuits or "ganged" output schemes
should be used to ensure optimum long term reliability of the
device.

-0.8

I
I~

-1.0

"
l!!

'0
>
'5
S::I

1\ I

-1.2

~5~

-1.4

II \

-1.6

,1.B

T
-2.0

-1.8

JlT

I VEE = -4.94V to -5.46V I
-1.6

-1.4

-1.2

-1.0

-O.B

Input Voltage (V)
-0.8
25°C

o·c

-1.0

"
~

\[\U,

-1.2

~A
~M

>
'5
a.
'5

7S"C

-1.4

-1.6

J\\ \

-1.B

~
-2.0

-1.75

·1.5

-1.25

-1.0

-0.75

-0.5

-2.0

-0.25

Output Voltage (V)

-1.B

[$
-1.6

·1.4

-1.2

-1.0

-O.B

Input Voltage (V)

Figure 2.1 • Output Characteristics vs Load

Figure 2.2 • ECLinPS 10E Transfer Curves

ECLinPS

2-7

Electrical Characteristics
necessary to design the VBB reference such that it tracks at
a rate equal to the average rate of the difference between the
high and low output level tracking rates. Table 2.1 also
outlines the temperature tracking behavior of a 10E VBB
switching reference.

10E

min

typ

max

IWoH/I1T (mV/oC)
I1Vo/I1T (mV/oC)
I1VBB/I1T (mV/oC)
I1Vojl1VEE (mV/v)
I1Vo/I1VEE (mV/v)
I1VBB/I1VEE (mV/v)

1.1
0
0.6
0
0
0

1.2
0.4
0.8
5
10
5

1.4
0.6
1.0
20
30
20

100E

min

typ

max

I1V oH/I1T (mV/oC)
I1VoL/I1T (mV/oC)
I1VBB/I1T (mV/oC)
I1VoH/I1VEE (mV/v)
I1Vo/I1VEE (mV/v)
I1VBB/I1VEE (mV/V)

-.15
-.30
-.20
0
0
0

0
0
0
5
10
5

.15
.30
.20
20
30
20

Since the VBE'S of the current source transistor reduce
with temperature, if the current source reference remains
constant ,as is the case for 1DOE devices, the lEE of the
device will vary with temperature. Careful scrutiny of the data
sheets will reveal that the worst case lEE for a function is
higher for the 100E version than the 10E version of that
device. As a result from a power standpoint a 1DOE device
operating at 85°C with a -4.5V VEE will be nearly identical to
a 1OE device operating with a -5.2V VEE under identical temperature conditions.
Although differing somewhat in many DC parameters,
1DE and 100E devices do share a couple of the same DC
characteristics. Both designs show superior lEE vs VEE tracking rates due to the design of the voltage regulator. With a
tracking rate of <3%/V this variation can effectively be
ignored during system design. The output level and refer·
ence level variation with VEE are also outstanding as can be
seen in Table 2.1.
Noise Margin
The noise margin of a device is a measure of a device's
resistance to undesirable switching. For ECLinPS as well as
all ECl devices, noise margin is a DC specification. The
noise margin is defined as the difference between the
voltage level of an output of the sending device and the
required voltage level of the input of the receiving device.
Therefore a worst case noise margin can be calculated from
the ECLinPS data sheets by simply subtracting the V,Lmax
or V,Hmin from the VOL min or VOHmax respectively. Table 2.2
below illustrates the worst case and typical noise margins for
both 1OE and 1DOE ECLinPS devices. Notice that the typical
noise margins are approximately 100mV larger than the
worst case.

Table 2.1 - ECLinPS Voltage Level Tracking Rates
The 1DOE devices, on the other hand, are temperature
and voltage compensated, therefore the output levels remain fairly constant over variations in both VEE and temperature. Figure 2.3 shows the transfer characteristics for a 100E
device. The associated tracking rates are illustrated in Table
2.1. Notice that in this case the VBB switching reference is
designed to remain constant over temperature to maintain
an optimum position within the output swing of the device.
This flat temperature tracking of the internal reference levels
leads to a phenomena particular to the 1OOE devices.

10E

NM H1GH (mV)
NM Low (mV)

·0.8

·1.0

-1.475, 1.035

-1.2

'""

-1.4

$
I

-1.6

-1.475, 1.610

::I

1f
Y

-1.165, -1.035

-2.0

-1.8

-1.4

-1.2

-1.0

min

typ

150
150

240
280

140
145

210
230

As mentioned above the noise margins of a device are
a DC measurement and thus can lead to some false impressions of the noise immunity of a system. For instance from
the chart the worst case noise margin is 140mV for a high
level of a 100E device. This would suggest that an undershoot on this line of greater than 140mV could cause an error
in the system. This however is not necessarily the case as
the determination as to whether or not an AC noise signal is
propagated is dependent on line impedances, output impedances and propagation delays as well as noise margins. A
more thorough investigation of the noise immunity of a
system can be found in Application Note AN-592.

vEE"4.2ovlo,s.46v
-1.6

typ

Table 2.2 - DC Noise Margins

-1.165, -1.610

JOOl

-1.8

100E

min

-0.8

Input Voltage (V)

Figure 2.3- ECLinPS 100E Transfer Characteristics

ECLinPS

2-8

Electrical Characteristics
AC Characteristics

parameters such as skew, setup/hold times, release times,
and maximum frequency. The following few paragraphs will
outline the ways in which Motorola defines these parameters.

Parameter Definitions
The device data sheets in Section 3 contain specifications for the propagation delays and rise/fall times for each
of the devices in the ECLinPS family. In addition, where applicable, skew, setup/hold, maximum toggle frequencies
(fMAX ) , reset recovery and minimum pulse width specifications are included. The waveforms and terminologies used
in describing the propagation delays and rise/fall times of the
ECLinPS family are depicted in Figure 2.4 below.

Skew Times
In the design of high speed systems skew plays nearly
as important a role as propagation delay. The majority of the
devices in the ECLinPS family have the skew between
outputs specified. This skew specification represents the
typical difference between the delays of similar paths on a
single chip. No maximum value for skew is specified due to
the difficulty in the production testing of this parameter. The
user is encouraged to contact an ECLinPS application
engineer to obtain actual evaluation data if this parameter is
critical in their designs.
Set-Up and Hold Times
Motorola defines the setup time of a device as the
minimum time, prior to the transition of the clock, that an input
must be stable to ensure that the device operates properly.
The hold time, on the other hand, is defined as the minimum
time that an input must remain stable after the transition of
the clock to ensure that the device operates properly. Figure
2.5 illustrates the way in which Motorola defihes setup and
hold times.

Rise and Fall Times

Data
ts

50%

Single-Ended Propagation Delay

Clock
Tpd
V out

V out

Vout

Figure 2.5 - Set-Up and Hold Waveforms

V out
Release Times
Release times are defined as the minimum amount of
time an input must waillo be clocked after an enable, master
reset or set Signal is deactivated to ensure proper operation.
Because more times than not this specification is in reference to a master reset operation this parameter is often
called reset recovery time. Figure 2.6 illustrates the definition of release time in the Motorola data sheets.

Differential Propagation Delay

Figure 2.4 - ECLinPS TPO Measurement Waveforms
Propagation delays and rise/fall times are generally well
understood parameters, howeverthere is sometimes confusion surrounding the definitions of more specialized AC

ECLinPS

2-9

Electrical Characteristics

Master Reset
Y.Data

Clock

[> Clock

Figure 2.6 - ECLinPS Release Time Waveforms
Figure 2.7 - f MAX Measurement

Measurement
In general fMAX is measured in the manner shown in
Figure 2.7 with the fail criterion being either a swing of
600mV or less, or a miscount. However in some cases the
feedback method of testing can lead to a pessimistic value
of f MAX because the feedback path delay is such thatthe
setup times of the device are violated. If this is the Case it is
necessary to have two free running signal generators to
ensure that the setup times are observed. This parameter,
along with fSHIFT and fCOUNT.represents the maximum frequency at which a particularflip flop, shift register or counter
can be clocked with the divide, shift or count operation
guaranteed. This number is generated from worst case
operating conditions, thus under nominal operating conditions the maximum toggle frequency is higher.
'MAX

AC Testing ECLinPS Devices
The introduction of the ECLinPS family raised the
performance of silicon t,o a new domain. As the propagation
delays of logic devices become ever faster the task of
correlating between test setups becomes increasingly challenging. To obtain test'results which correlate with Motorola,
various testing techniques must be adhered to. A typical
schematic for an ECLinPS test setup is illustrated in Figure
2.8.
A solid ground plane is a must in the test setup, as the
two power supplies are bypassed to this ground plane. A
20~F capacitor from the two power supplies to ground is

Channel A

son Coax
son Coax
vccd·--------~~

Oscilloscope

(+2.0V) /
ChannelS
VCC
(+2.0V)

son Coax
son

0.01~F

-3.2V·

• VEE = -3.2V for 10Exxx; -2.5V for 1OOExxx .
•• MultipleVCCo's exist on most parts

Figure 2.8 • Typical ECLinPS Test Setup

ECLinPS

2-10

Electrical Characteristics
phenomena which can lead to inaccuracies in AC measurements. To minimize degradation of the input and output edge
rates a 50n coaxial cable with a teflon dielectric is recommended, however any other cable with a bandwidth of
>5.0GHz is adequate. In addition, the cables from the device
under test (OUT) to the inputs of the scope should be
matched in length to prevent any errors due to different path
lengths from the OUT to the scope. The interconnect fittings
should be 50n SMA straight or SMA launchers to minimize
impedance mismatches at the interface of the coax and test
PC board. Although a teflon laminate board is preferable, an
FR4 laminate board is acceptable as long as the signal
traces are kept to five inches or less. Longer traces will result
in significant edge rate degradation of the input and output
Signals.
To make the board useful for incoming inspection or
other volume testing the board needs to be fitted with a
socket. Although not suitable for AC testing due to different
pin lengths and large parasitics, there are through hole
sockets which are adequate for DC testing of ECLinPS
devices. For AC testing purposes a 28 pin PLCC surface
mount socket is recommended. At the publication of this
databook there are two sockets available which the Motorola
ECLinPS group recommends: AMP part # 822039-1 and
Method Electronics part #'s 213-028-601 or 213-028-602.
To ease the correlation issue Motorola has developed
a universal AC test board which is now available to customers. The board is fitted with a PLCC socket and comes with
instructions on how it can be configured for the different
device types in the family. For ordering information see the
description on the following page.
Finally, to ensure correlation between Motorola and the
customer, ·high performance state-of-the-art measuring
equipment should be used. The pulse generator must be
capable of producing the required input levels with rise and
fall times of 500ps. In addition, if fMAX is going to be tested,
a frequency of of up to 1.5GHz may be needed. The oscilloscope should also be of the utmost in performance with a
minimum bandwidth of 5.0 GHz.

20!!F capacitor from the two power supplies to ground is
used to dampen any supply variations. An RF quality .01!!F
capacitor from each power pin to ground is used to decouple
the fixture. These .01!!F capacitors should be located as
close to the power pins of the package as possible. In
addition, in order to minimize the inductance of the power
pins, all of the power leads should be kept as short as
possible. The power supplies are shifted by +2.0V so thatthe
load comprises only the precision 50n input impedance of
the oscilloscope. Use of this technique will assure that the
customer and Motorola are terminating devices into equivalent loads and will improve test correlation.
To further standardize testing any unused outputs should
be loaded with 50n to ground.
Because the power supplies are shifted, the input levels
must also be shifted by an equal amount. Table 2.3 gives the
typical input levels for the ECLinPS family and their corre-

10Exxx

Typical

Shifted

VIL

-1.75V

+0.25V

V,H

-0.90V

+1.10V

100Exxx

Typical

Shifted

VIL

-1.70V

+0.30V

V,H

-0.95V

+1.05V

Table 2.3 - Eel levels after Translating by +2.0V
sponding +2.0V shifted levels.
The test fixture should be in a controlled impedance
50n environment, with any non-50n interconnects, or stubs,
kept as short as possible «1/4"). This controlled impedance
environment will help to minimize overshoot and ringing, two

Figure 2.9 -

ECLinPS AC Test Board

ECLinPS

2-11

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
APPLICATIONS INFORMATION

Engineering Evaluation Board
for 28 Pin ECl Devices in the PlCC Package
Part # EClPSBD28

DESCRIPTION
This board is designed to provide a low cost characterization tool for evaluating ECl devices in the ECLinPS
Product Family. The board provides a high bandwidth 50 ohm controlled impedance environment. The board
is universal and can be configured by the user for any of the 28 pin PLCC devices in the family depending on
the input, output, and power pinout layout of the device. The table below indicates common input/output/power
devices.
Group
CONF1
CONF2
CONF3
CONF4
CONF5
CONF6
CONF7
CONF8
CONF9
CONF10
CONF11
CONF12
CONF13
CONF14
CONF15

Base Device

Pin Qompatible Devices

E196
E142
E337
E212
E156
E158
E154
E101
E112
E431
E111
E164
E451
E163
E193

E195
E016,E141,E143,E241
E336
E1 04,E1 07,E150,E151
E155,E167,E171,E256
E116,E122,E175,E416
E452
E131,E157,E404
E457
E160
E166

Table 1: Cross Reference of Board Configuations
The board is designed to test devices using the fly-by (Kelvin contact) test method, therefore one input force
trace and one input sense trace exists for each input pin. This allows termination of the input and output signals
into the highly accurate 50 ohm impedance of an oscilloscope. The layout is engineered to have equal length
traces from the device under test (OUT) socket to the sense outputs which simplifies the calibration
requirements for accurate AC measurements.
The kit provides a printed circuit board with an attached surface mount socket as well as assembly
instructions. For superior impedance control from the cable to the board, Motorola recommends the use of SMA
coaxial connectors.

ECLinPS
2-12

MOTOROLA

<:>

0~
10 uF
capacitors
Locations

A. Location of
sense ring
for SMAs

B. Vias to the
power planes

Figure 1. Front View of ECLinPS Evaluation Board

ECLinPS
2-13

Group Part(s)

'}' g

...
.j>.

::J

iJ
CJ)

eONFl
eONF2
eONF3
eONF4
CONFS
eONF6
eONF7
eONF8
eONF9
eONF10
eONFll
eONF12
eONF13
eONF14
eONF1S

E196
E142
E337
E212
E1S6
E1SB
E1S4
El01
E112
E431
El11
E164
E4S1
E163
E193

VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE

I
I
I
I
I
INB
INB
I
I
INB
I
I
I
I
I

I
I
I
I
I
I
I
I
I
I

VB
I
Ne
I
I

VB Ne
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I Ne
I
I
Ne 0
I
I
I
I
I
I
I
I

Ne
I
I

I
I
I
0
I
Vee
I
I
0
I
0
I
I
I
I

Vee
I
I
I
I
Vee
I
0
I
I
I
I

Pl0

Pll

P12

P13

I
0
I
0
I
0

0
0
Ne
0

0
0
0

Vee

0
0
I
0
Vee
Vee
0
0
0
0
0
Vee
0
0
0

Vee
Vee
0
I
0
I
I
0
INB

Vee
I
I
I
I

Vee
I
0
I
0
I

L
I
Vee

Vee
Vee
0
I
0
I
0
I
Vee
I
0

Vee
0
0
0

Vee
Vee
Vee
0
I
0
I
0

0
Ne
0
0
0
0
0
0
0
0
I
0
0
0
-

P14

Vee
Vee
0
0
0
0
0
0
0
0
0
Vee
Vee
Vee

PIS

P16

P17 P18

P19

P20

P21

P22 P23 P24

Ne
0
I
0
0
0
0
0
0
0
0
0
0
0
0

Ne
0
0
0

Vee
Vee

I
I
I

I
I
I
I
I
I
I
I
0
I
0
I
I
I
I

Vee Vee
0
Vee
0
Vee
0
Vee
0
0
0
0
0
0

Vee
0
0
Ne
0

Vee
Vee

Vee

Vee
Vee

Vee

0
Vee
Vee

Vee

I
0
Ne
0
0
0
0
0
0
0
0
0
0
0
0

Vee
Vee
0
0
O·
I
0
Vee
Vee
Vee
0

I
I
I
0 Vee 0
I
I
I
0
0 Vee
I
0 Vee
I
0 Vee
0 Vee 0
I
I
INB
0 Vee
0
I
I
I
I
I
I
I
I
I
I
I
Vee

-L---

I
I
I
I
I
I
I
I
0
I
0
I
I
I
I

P2S

P26

P27 P28

I
I
I
I
I
I
I
I
0
INB
0
I
I
I
I

I
I
I
I
I
I
I
I
Vee
I
VEE
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
VB
I
I

L-.----~L...__

Table 2. Pin Cross Reference

KEY:

"I"
"0"
"VEE"

"Vcc"
"NC':
"VB"

designates an input
designates an output
designates the lower voltage rail
designates the upper voltage rail
designates a no connect
designates VBB output which should
not be terminated into 50 ohms

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
__

of
eonnectors
35
37
37
33
40
32
38
40
26
44
25
44

37
42
38
---

ASSEMBLING THE ECLinPS EVALUATION BOARD
The evaluation board is designed for characterizing devices in a laboratory environment using high bandwidth
sampling oscilloscopes such as the Hewlett Packard 54120T, the Tektronix 11800 Series, or the Tektronix 7854.
The board is designed using Kelvin contact (fly·by) techniques to present the input signals to the DUT. Each
pin on the board has two traces, one force and one sense. Inputs pins use one force and one sense line, while
outputs need only a sense line. This means that input signals are terminated through the sense line into the
50 ohm input of asampling oscilloscope instead of atthe inputto the DUT. Please refer to the AC Testing section
of the ECLinPS Data Book for further information and a simplified figure of the test setup.
The first step in building a board is determining which input/output/power configuration is necessary for the de·
vice of interest. Table 1 on the first page of the Applications Information shows all the board configurations.
For example, if the devices of interest were the E1 04 and the E151, then CONF2 would be selected. Table 2
is a pin cross reference for each configuration.
I. Installing the SMA Connectors

Table 2 indicates the number of SMA connectors needed to populate an evaluation board for a given configura·
tion. Depending on the device and the parameters of interest, it may not be necessary to install the full comple·
ment of SMA connectors. For example, some devices have two clock inputs or common clocks and individual
clocks. Figure 1 is the front view of the ECLinPS evaluation board. Item A points to the inner ring which connects
to the sense traces of the DUT. The outer ring connects to the force traces. An input requires one SMA connec·
tor for the force and one SMA connector for the sense, while an output only requires a connection to the sense
trace. Insert all the SMA connectors into the board and solder to the board. A simple assembly technique is
to place a stiff piece of cardboard (8" x 7" or larger) on top of all the connectors and hold the board and cardboard
together. Invert the board, place on a level surface, and all the connectors will be seated properly and can be
soldered in place.
II. Connecting Power Planes to OUT Socket

There are four voltage planes on the ECLPSBD28. One is dedicated to ground and the other three: B1, B2,
B3 are uncommitted. These planes are accessible through a power connection and sets of four vias that are
adjacent to each sense trace. This is identified as Item B in Figure 1. For standard parts, B1 can be assigned
VCC, B2 can be assigned to VEE, and B3 can be assigned to ground. Table 2 indicates which pins need to
be connected to the various supply Voltages. On the front side of the board, solder ajumperwire from the closest
VEE orVcc via to the sense trace for each VCC, VCCO, and VEE pin. Nearthe DUTthere are sets of ground/
bias plane vias that accommodate power supply decoupling capacitors. These are identified as Item C. On the
front side of the board install 1a ~F capacitors and on the back side install a 0.01 ~F high frequency capacitor
in parallel to decouple the VEE and VCC planes.
III. Cutting Force Traces for Outputs

Because of the design of the board all force traces for output pins will appear as transmission line stubs con·
nected to the output pin. On the back side of the board, cut the force traces associated with the outputs using
a razor blade knife. It is important to cut the trace very close to the DUT area to minimize the stub length. Also
cut the force traces that are connected to VCC, Vcco, and VEE pins.
IV. Installing the Chip Capacitors for the VCCIVCCO Pins

In the kit are 0.01 ~F chip capacitors for use in decoupling the VCC and VCCO pins to the ground plane. This
is critical because the power pins are not directly connected to the VCC plane as in an actual board layout. On
the back side of the board beneath the DUT socket are pads for each pin which allow connection of chip capaci·
tors to the center island (GND) for each VCC and VCCO pin. Stand the chip capacitors on edge when soldering
them in place so that adjacent pins are not shorted together.

ECLinPS
2·15

V. Final Assembly
The board power plane interface is designed to accommodate a 15 pin right angle D connector. This can be
used directly, or wires can be inserted into the vias to connect to the power planes that were connected to the
DUT in part II. Attach standoffs into the four 0.25 inch holes at the corners of the board. This completes the
assembly of the evaluation board and it should be ready to test.

VI. SMA Connector Suppliers
Below are two suppliers who manufacture PC Mount SMA connectors which interface to the evaluation board.
Motorola has used these two connectors before, but there are other vendors who manufacture similar products.

EF Johnson
299 Johnson Ave. P.O. Box 1249
Waseca, Minnesota 56093
(800)-247-8343 or (507)-835-6222

0.200" PC Mount SMA
Jack Receptacle
142-0701-201

MACOM Omni Spectra
140 Fourth Avenue
Waltham, Massachusetts 02254
(617)-890-4750

0.200" PC Mount SMA
Straight Jack
2062-0000-00

ECLinPS
2-16

EC!:PS

Family Specifications
& Device Data Sheets

This section contains AC & DC specifications for each
ECUnPS device type. Specifications common to all device
types can be found in the first part of this section. While
specifications unique to a particular device can be found in
the individual data sheets following the family specifications.

Data Sheet Classification

Advance Information -

product in the sampling or pre-production stage at the time of publication.

Product Preview- product in the design stage at the time of publication.

ECLinPS
3-1

ECl::PS
Family Specifications
Absolute Maximum Ratings
Beyond which device life may be impaired. 1
Characteristic
Power Supply (Vee
Input Voltage (Vee

Symbol

Rating

Unit

VEE

-8 to 0

Vdc

= 0 V)
= 0 V)

o to

Output Current,- Continuous
-Surge

lout

Operating Temperature Range
10E Series
100E Series

Operating Range 2

-6 V

Vdc

50
100

o to
o to

mA
°e

+75
+85

-5.7 to -4.2

VEE

1. Unless specified otherwise on Individual data sheet.

2. Parametric values specified at: 100E series: - 4.2 V to - 5.46 V
10E series: -4.94 V to -5.46 V

10E Series DC Characteristics
VEE

= -5.2 V ±

5%; Vee

= Veeo = GN01
Q'C

75°C

25'C

85°C

Min

Max

Min

Max

Min

Max

Min

Max

Unit

VOH

Output HIGH Voltage

-1020

-840

-980

-810

-920

-735

-910

-720

VOL

Output LOW Voltage

-1950

-1630

-1950

-1630

-1950

-1600

-1950

-1595

VIH

Input HIGH Voltage

-1170

-840

-1130

-810

-1070

-735

-1060

-720

VIL

Input LOW Voltage

-1950

-1480

-1950

-1480

-1950

-1450

-1950

-1445

IlL

Input LOW Current

0.5

Symbol

Characteristic

0.5

0.3

J,tA

1. 10E senes CircUits are deSigned to meet the de specifications shown In the table, after thermal equIlibrium has been established. The CirCUit IS In a test
socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50 0 resistor to - 2.0 Yolts, except bus outputs which, where specified, are terminated into 25 n.

100E Series DC Characteristics
VEE

= -4.2Vto

Symbol

-5.46 V; Vee

= Veeo = GNO;TA = oOeto

Characteristic

Min

Typ

+85°e
Max

Unit

VOH

Output HIGH Voltage

-1025

-955

-880

VOL

Output LOW Voltage

-1810

-1705

-1620

VOHA

Output HIGH Voltage

-1035

VOLA

Output LOW Voltage

mV
-1610

Conditions
VIN = VIH(max)
OrVIL(min)
VIN = VIH(min)
or VIL(max)

Loading with
50 to -2.0 V

VIH

Input HIGH Voltage

-1165

-880

Guaranteed HIGH Signal for All Inputs

VIL

Input LOW Voltage

-1810

-1475

Guaranteed LOW Signal for All Inputs

IlL

Input LOW Current

0.5

p.A

VIN

VIL(min)

ThiS table replaces the three tables at different supply voltages In the prevIous edition and In Eel 100K literature. The same DC parametnc values at VEe =

-4.5 V now apply across the full VEE range of -4.2 to -5.46 V.

ECLinPS

3-2

MOTOROLA
SEMICONDUCTOR
_ _ _ _ _ _ _ _ _ _ __
TECHNICAL DATA

•
•
•
•
•
•
•
•

MC10E016
MC100E016

700 MHz Min. Count Frequency
1000 ps ClK to Q, TC
Internal TC Feedback (Gated)
8-Bit
Fully Synchronous Counting and TC Generation
Asynchronous Master Reset
Extended 100E VEE Range of - 4.2 V to - 5.46 V
75 k!l Input Pulldown Resistors

8-BIT SYNCHRONOUS
BINARY UP COUNTER

The MC10E/100E016 is a high-speed synchronous, presettable, cascadable 8-bit
binary counter. Architecture and operation are the same as the MC10H016 in the
MECl 10KH family, extended to 8-bits, as shown in the logic symbol.
The counter features internal feedback of TC, gated by the TClD (terminal count
load) pin. When TClD is lOW (or left open, in which case it is pulled lOW by the
internal pull-downs), the TC feedback is disabled, and counting proceeds continuously, with TC going lOW to indicate an all-one state. When TClD is HIGH, the TC
feedback causes the counter to automatically re-Ioad upon TC = lOW, thus functioning as a programmable counter.

PINOUT: 28-lEAD PLCC (TOP VIEW)

FUNCTION TABLE

Vcca

'fC

CE PE TClD MR ClK
L
L
H

l
H
H
H

X
X

ClK

TClD

Vcc

VEE

Z
ZZ

VCCO

=
=

L
H
X
X
X

l
L
L
l
L
H

Z
Z
Z
Z
ZZ
Z

Function
Load Parallel (P n to On)
Continuous Count
Count; Load Parallel on fC = lOW
Hold
Masters Respond, Slaves Hold
Reset (On: = LOW, TC : = HIGH)

clock pulse (low to high);
clock pulse (high to low)

PIN NAMES

Vcca

Pin
Po-P7
00- 0 7
CE
PE
MR
ClK
TC
TCLD

ECLinPS

3-3

Function
Parallel Data (Preset) Inputs
Data Outputs
Count Enable Control Input
Parallel Load Enable Control Input
Master Reset
Clock
Terminal Count Output
TC-load Control Input

8·BIT BINARY COUNTER LOGIC DIAGRAM

02"""00

i'E
TClD~

r---OOM r---1

(")

W
~

r
S·
iJ

(J)

MR ---l ") I

I
I

I
I
BIT 1

BIT 0

W
I
I
I
I
I
I
I
I
I

r
I
I

~~Go
0 102
03
§TI5

BIT 2-BIT 6

I
I
I

s::

C')

......

------l
I

0
BIT7

m
......

I
I
I
I
I

O'l

s::

C')

......

0
0

......

O'l

ClK

'"
TC

Note that this diagram is provided for understanding of logic operation only.
It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.

MC10E016, MC100E016
DC Characteristics:

VEE = V EE(min) to VEE(max); Vee = Vceo = GND
O°C

Symbol

Characteristic

I'H

Input HIGH Current

lEE

Power Supply Current

r--

min

25°C
max

min

'COUNT

tplH
tpHl

typ

max

Unit

150

Characteristic

min

typ

Max. Count Frequency

700

900

181
181

151

181

151

181

151

181

174

208

25°C

ClKtoO

600

725

MRloO
ClK to TC (O's loaded)
ClK 10 TC (O's unloaded)

600
550
550

775
775
700

MRloTC

625

775

max

85°C

min

typ

max

min

typ

700

900

1000

600

725

1000
1050

600
550
550

775
775
700

625

775

150

-30

150
600
600

max

700

900

1000

600

725

1000

1000
1050

600
550

775

1000
1050

900
1000

550
625

Unit

Condition

MHz

Propagalion Delay 10 Oulput

900
1000

775
700
775

1
1

900
1000

Setup Time

Pn
CE

150

-30

600

400

600

400

PE
TClD

600
500

400

600
500

400
300

Hold Time
Pn

250

30
-400

250

30
-400

100

-400
-300

0
100

-400
-300

0
100

-400
-300

700

900

700

900

700

300

500

-30
400
400
300
ps

0
0

IRA

Reset Recovery Time

900

tpw

Minimum Pulse Widlh
ClK, MR

400

ps
ps

400

Rise/Fall Times
20 -80%

Condition

VEE = VEE(min) to VEE(max); Vee = Veeo= GND

TClD

min

mA
151
151

CE
PE

85°C
max
150

O°C
Symbol

typ

150

10E
100E

ACCharacteristics:

typ

ps
300

510

800

300

510

800

300

510

800

1. ClK to Tc propagation delay is dependent on the loading of the Q outputs. With all of the Q outputs loaded the noise generated in going
from a 11111111 state to a 0000 0000 state causes the ClK to

Tc+ delay to increase

ECLinPS

3-5

,MC1 OE016, MC100E016
FUNCTION TABLE
FUNCTION

TCLD

CLK

P7-P4

L
H
H
H
H
L
H
H
H
H
H
H
H
H
X

X
L
L
L
L
X
H
H
L
L
L
L
L
L
X

L
L'
L
L
L
L
L
L
L
L
L
L
L
L
H

X
L
L
L
L
X
X
X
H
H
H
H
H
H
X

Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z

H
X
X
X
X
H
X
X
H
H
H
H
H
H
X

Load
Count

Load
Hold
Load On
Terminal
Count

Reset

P3 P2 P1 PO

H
X
X
X
X
H
X
X
L
L
L
L
L
L
X

L
X
X
X
X
L
X
X
L
L
L
L
L
L
X

L
X
X
X
X
L
X
X
H
H
H
H
H
H
X

X
X
X
X
H
X
X
H
H
H
H
H
H
X

Q7-Q4 Q3 Q2 Q1 QO

H
H
H
H
L
H
H
H
H
H
H
H
H
H
L

H
H
H
H
L
H
H
H
H
H
H
L
L
H
L

H
H
H
H
L
H
H
H
H
H
H
H
H
L
L

L
L
H
H
L
L
L
L
L
H
H
H
H
L
L

L
H
L
H
L
L
L
L
H
L
H
L
H
L
L

H
H
H
L
H
H
H
H
H
H
L
H
H
H
H

Applications Information
Cascading Multiple E016 Devices
For applications which call for larger than 8-bit counters
multiple E016's can be tied together to achieve very wide bit
width counters. The active low terminal count (TC) output and
count enable input (CE) greatly facilitate the cascading of
E016 devices, Two E016's can be cascaded withoutthe need
for external gating, however for counters wider than 16 bits
external OR gates are necessary for cascade implementations.
Figure 1 below pictorally illustrates the cascading of 4
E016's to build a 32-bit high frequency counter. Note the E1 01
gates used to OR the terminal count outputs olthe lower order
E016's to control the counting operation of the higher order
bits. When the terminal count of the preceeding device (or
devices) goes low (the counter reaches an all 1's state) the
more significant E016 is set in its count mode and will count
one binary digit upon the next positive clock transistion. In
addition, the preceeding devices will also count one bit thus
sending their terminal count outputs back to a high state dis-

abling the count operation of the more significant counters
and placing them back into hold modes, Therefore, for an
E016 in the chain to count all olthe lower order terminal count
outputs must be in the low state. The bit width of the counter
can be increased or decreased by simply adding or subtracting E016 devices from Figure 1 and maintaini'ng the logic
pattern illustrated in the same figure.
The maximum frequency of operation for the cascaded
counter chain is set by the propagation delay of the TC output
and the necessary setup time of the CE input and the propagation delay through the OR ga.m.controlling it (for 16-bit
counters the limitation is only the TC propagation delay and
the CE setup time). Figure 1 shows E101 gates used to
control the count enable inputs, however if the frequency of
operation is lower a slower ECL OR gate can be used. Using
the worst case guarantees for these parameters from the
ECLinPS data book the maximum count frequency for a
greater than 16-bit counter is 475MHz and that for a 16-bit

Loadcr----__________. -______--------,----------------------,--------------------,
QO->Q7

"LO"

QO·>Q7

QO-> Q7

E016

LSB

QO->Q7

E016
MSB

PO -> P7

Clocko-_t--------------.....--------------------_------------------~

Figure 1 - 32-Bit Cascaded E016 Counter

ECLinPS

3-6

MC10E016, MC100E016
Applications Information
counter is 625MHz. Note that this assumes the trace delay
between the TC outputs and the CE inputs are negligible. If
this is not the case estimates of these delays need to be added
to the calculations.

Divide
Ratio

Programmable Divider
The E016 has been designed with a control pin which
makes it ideal for use as an 8-bit programmable divider. The
TCLD pin (load on terminal count) when asserted reloads the
data present at the parallel input pin (Pn's) upon reaching
terminal count (an all 1's state on the outputs). Because this
feedback is built internal to the chip the programmable division operation will run at very nearly the same frequency as
the maximum counting frequency of the device. Figure 2
below illustrates the input conditions necessary for utilizing
the E016 as a programmable divider set up to divide by 113.

Preset Data Inputs
P7 P6 P5 P4 P3 P2 P1

2
3
4
5

H
H
H
H

H
H
H
L

H
L
L
H

L
H
L
H

112
113
114

H
H
H

L
L
L

H
L
L

L
H
H

L
H
L

254
255
256

L
L
L

L
L

L
L
L

L
L

L
H
L

··

·
·
L

·· .

· .
·
L H

HLLLHHHH

Table 1 - Preset Values for Various Divide Ratios
P7 P6 P5 P4 P3 P2 P1
H

TCLD

PO
full clock period. For even divide ratios, twice the desired
divide ratio can be loaded into the E016 and the TC output can
feed the clock input of a toggle flip flop to create a signal
divided as desired with a 50% duty cycle.
A single E016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256 are needed
multiple E016's can be cascaded in a manner similar to that
already discussed. When E016's are cascaded to build larger
dividers the TCLD pin will no longer provide a means for
loading on terminal count. Because one does not want to
reload the counters untill all of the devices in the chain have
reached terminal count, external gating of the TC pins must be
used for multiple E016 divider chains.
Figure 4 on the following page shows a typical block
diagram of a 32-bit divider chain. Once again to maiximizethe
frequency of operation E1 01 OR gates were used. For lower
frequency applications a slower OR gate could replace the
E..! 0 1. Note that for a 16-bit divider the OR function feeding the
PE (program enable) input CANNOT be replaced by a wire
OR tie as the Tc output of the least significant E016 must also
feed the CE input of the most significant E016. If the two TC
outputs were OR tied the cascaded count operation would not
operate properly. Because in the cascaded form the PE

Figure 2 - Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division the designer simply subtracts
the binary equivalent ofthe desired divide ratio from the binary
value for 256. As an example for a divide ratio of 113:
Pn's = 256 - 113 = 8F,s = 1000 1111
where:
PO = LSB and P7 = MSB
Forcing this input condition as per the setup in Eigure 2 will
result in the waveforms of Figure 3. Note that the TC output is
used as the divide output and the pulse duration is equal to a

Load

'00' 0000

, 00' 000'

1100

11111101

11111110

Clock

+--,

P~E__________

Divide by 113

Divide by 113 E016 Programmable Divider Waveforms

ECLinPS

3-7

11111111

Load

MC10.E016, MC100E016
Applications Information

"LD"

E016
LSB

PO -> P7

Clockir-_ir-------4_-----------il-------------l

32-81t Cascaded E016 Programmable Divider
feedback is external and requires external gating the maximum frequency of operation will be significantly less than the
same operation in a single device.

Maximizing E016 Count Frequency
The E016 device produces 9 fast transitioning single
ended outputs, thus Vee noise can become significant in
situations where all of the outputs switch simulataneously in
the same direction. This Vee noise can negatively impact the
maximum frequency of operation of the device. Since the

device does not need to have the Q outputs terminated to
count properly, it is recommended that if the outputs are not
going to be used in the rest of the system they should be left
unterminated. In addition if only a subset of the Q outputs are
used in the system only those outputs should be terminated.
Not terminating theunused outputs will not only cut down the
Vee noise generated but will also save in total system power
dissipation. Following these guidelines will allow designers to
either be more aggressive in their designs or provide them
with an extra margin to the published data book specifications.

ECLinPS
3-8

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

MC10E101
MC100E101

• 500 ps Max. Propagation Delay
• Extended 100E VEE Range of -4.2 V to -5.46 V
• 75 kG Input Pulldown Resistors

The MC10E/l00El0l is a quad 4-input ORINOR gate.

QUAD 4-INPUT
OR/NORGATE

PINOUT: 28-lEAD PlCC (TOP VIEW)
Caa

D3b

0Jc

D3d

Veeo ii3

lOGIC SYMBOL

DOa
DOb

Doc
Dod
Dla
Dlb
Ole
Old

D2a
D2b
D2e
D2d
D3a

PIN NAMES
DOa-D3d
00-03
00-0 3

D3b

Function

D3e

Data Inputs
True Outputs
Inverting Outputs

D3d

ECLinPS
3-9

~~
Ql

~~
02

~~
Q3

MC1 OE1 01, MC1 00E1 01
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veeo= GND
25°C

O°C
Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

ACCharacteristics:

min

typ

max

min

150

tpLH
tpHL
tSKEW
tSKEW

t,
tf

85°C
max

min

typ

150

max

Unit

150

IlA

Condition

mA
30
30

36
36

30
30

36
36

30
35

36
42

VEE = VEE(min) to VEE(max); Vee = Veeo= GND
25°C

O°C
Symbo

typ

85°C

Characteristic

min

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
DtoO

200

350

500

200

350

500

200

350

500

Condition

Within-Device Skew
Within-Gate Skew
Rise I Fall Time
20-80%

Unit

50
25

ps
300

380

575

300

380

575

300

380

575

1. Within-device skew is defined as identical transitions on similar paths through a device
2. Within-gate skew is defined as the variation in propagation delays of a gate when driven from its different inputs.

ECLinPS

3-10

1
2

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

•
•
•
•

MC10E104
MC100E104

600 ps Max. Propagation Delay
OR/NOR Function Outputs
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kn Input Pulldown Resistors

The MC10E/l00El04 is a quint 2·input AND/NAND gate. The function output F is
the OR of all five AND gate outputs, while F is the NOR. The Q outputs need not be
terminated if only the F outputs are to be used.

QUINT 2-INPUT
AND/NAND GATE

PINOUT: 28-LEAD PLCC (TOP VIEW)
D3a

D4b

D4a

Ne Veeo

LOGIC SYMBOL

D3b

D2a

D2b

Vee

VEE

D1a

D1b

Doa

DOa

DOb

D1a

D1b

DOb

Veeo

D2a

D2b

PIN NAMES
Function

DOa-D4b

Qo-C4
Qo-C4
F

Data Inputs
AND Outputs
NAND Outputs
OR Output
NOR Output

FUNCTION OUTPUTS

F = (DO a ' DOb)
(D3a • D3b)

+ (Dla' Dlb) + (D2a' D2b) +
+ (D4a' D4b)

ECLinPS
3-11

D3a

OJb

D4a

D4b

MC10E104, MC100E104
DC Characteristics:

VEE = VEE(min) to VEE(max);

Vcc = V ceo = GND

O°C

Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current

min

typ

min

200

tpLH

tSKEW

min

typ

max

Unit

200

j.tA

100E

VEE = VEE(min) to VEE(max);

Vee = Vcca= GND
25°C

85°C

min

typ

max

min

typ

max

min

typ

max

DloO

225

385

600

225

385

600

225

385

600

DtoF

500

725

1000

500

725

1000

500

725

1000

Characteristic

Condition

mA
38

Propagalion Delay 10 Oulpul

Unit

Condition

Within-Device Skew

DtoO
I,

max
200

O°C

IpHL

typ

tOE

ACCharacteristics:

Symbol

85°C

25°C

max

Rise I Fall Times

20-80%

275

425

700

275

425

700

275

425

700

300

475

700

300

475

700

300

475

700

1" Within-device skew is defined as identical transitions on similar paths through a device

ECLinPS
3-12

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

MC10E107
MC100E107

• 600 ps Max. Propagation Delay

• ORINOR Function Outputs
• Extended 100E VEE Range of -4.2 V to -5.46 V
• 75 kO Input Pulldown Resistors

The MC10EI100El07 is a quint 2-input XOR/XNOR gate. The function output F is
the OR of all five XOR outputs, while F is the NOR. The Q outputs need not be
terminated if only the F outputs are to be used.

QUINT 2-INPUT
XOR/XNOR GATE

PINOUT: 28-LEAD PLCC (TOP VIEW)

LOGIC SYMBOL

~-6Hi+---

~J-++++----ao

DOb Veea

111 Veea

.........---'iH----

/o--ttil----

111

.........-'H----Q2
PIN NAMES
Pin
Daa-D4b
00-0 4
00-0 4

~)---++----02

Function
Data Inputs
XOR Outputs
XNOR Outputs
OR Output
NOR Output

~-""'---Q3
......-'I~-+---03

FUNCTION OUTPUTS
F

(DO a EB Dab) + (Dla
(D3a EB D3b) + (D4a

...........--4----<4

EB Dlb) +
EB D4b)

(D2a

EB D2b) +

~J__---Cl4

ECLinPS
3-13

MC10E107, MC100E107
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veeo= GND
25°C

O°C
Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

r--

AC Characteristics:

min

typ

max

min

200

tpLH
tpHL

tSKEW

t,
tf

85°C
max

min

typ

200

max

Unit

200

IlA

Condition

mA
42
42

50
50

42
42

42
48

50
50

50
58

VEE = VEE(min) to VEE(max); Vee = Veeo= GND
25°C

O°C
Symbol

typ

85°C

Characteristic

min

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
DtoQ
DtoF

250
500

410

600
1000

250
500

410

600
100

250
500

410

600
1000

Condition

Within-Device Skew
DtoQ
Rise I Fall Times
20 -80%
Q
F

Unit

725

ps
75

1
ps

275
300

450
475

700
700

275
300

450
475

700
700

1. Within-device skew is defined as identical transitions on similar paths through a device

ECLinPS
3-14

275
300

450
475

700
700

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA
•
•
•
•
•
•
•

low Skew
Guaranteed Skew Spec
Differential Design
Vas Output
Enable
Extended 100E VEE Range of - 4.2 V to - 5.46 V
75 kn Input Pulldown Resistors

MC10E111
MC100E111

The MC10EI100E111 is a low skew 1-to-9 differential driver, designed with clock
distribution in mind. It accepts one signal input, which can be either differential or
else single-ended if the Vas output is used. The signal is fanned out to 9 identical
differential outputs. An enable input is also provided. A HIGH disables the device
by forcing all Q outputs lOW and all IT outputs HIGH.
The device is specifically designed, modeled and produced with low skew as the
key goal. Optimal design and layout serve to minimize gate to gate skew withindevice, and empirical modeling is used to determine process control limits that
ensure consistent tpd distributions from lot to lot. The net result is a dependable,
guaranteed low skew device.
To ensure that the tight skew specification is met it is necessary that both sides
of the differential output are terminated into 50 n, even if only one side is being
used. In most applications, all nine differential pairs will be used and therefore terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same
VCCO) as the pair(s) being used on that side, in order to maintain minimum skew.
Failure to do this will result in small degradations of propagation delay (on the
order of 10-20 psI of the output(s) being used which, while not being catastrophic
to most designs, will mean a loss of skew margin.
The Vas output is intended for use as a reference voltage for single-ended
reception of ECl signals to that device only. When using for this purpose, it is recommended that Vas is decoupled to VCC via a 0.01 ILF capacitor.

Veeo

LOGIC SYMBOL

VEE

03
Q4

PINOUT: 28-LEAD PLCC
(TOP VIEW)

Vee

Veco

Vaa

05
08

Veeo

PIN NAMES
Pin
IN, IN
EN
QO, QO-QS' QS
VSS

00
Ql

1:9 DIFFERENTIAL
CLOCK DRIVER

Function
Differential Input Pair
Enable
Differential Outputs
VSS Output

Vaa - - - -

ECLinPS
3-15

MC10E111, MC100E111
DC CHARACTERISTICS: VEE

VEE (min) to VEE (max); Vcc
TA

Symbol
Vss

Characteristic

Min

Output Reference Voltage
10E
100E

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

AC CHARACTERISTICS: VEE

Typ

VCCO
TA

Max

Min

GND

= 25'C
Typ

-1.38
-1.38

-1.27 -1.35
-1.26 -1.38

Min

= 85°C
Typ

-1.25 -1.31
-1.26 -1.38

150

Max

Unit

Conditions

V
-1.19
-1.26

150

mA
48
48

Characteristic

Min

VCCO

= DOC
Typ

TA
Max

60
60

48
48

60
60

VEE (min) to VEE (max); VCC
TA

Symbol

= D'C

Min

48
55

60
69

GND

= 25°C
Typ

Max

Min

tpLH
tpHL

Propagation Delay to Output
IN (differential)
IN (single-ended)
Enable
Disable

tskew

Within-Device Skew

Setup Time
EN to IN

200

Hold Time
IN to EN

-200

Release Time
EN to IN

300

100

300

100

Vpp

Minimum Input Swing

250

VCMR

Common Mode Range

-1.6

tr
tf

Rise/Fall Times
20-80%

275

= 85'C
Typ

Max

Unit

Note

ps
430
330
450
450

630
730
850
850
25

430
330
450
450

630
730
850
850
25

375

-1.6

600

275

375

1
2
3
3

630
730
850
850
25

-200

300

100

250

250
-0.4

430
330
450
450

-0.4

-1.6

600

275

375

-0.4

600

Notes:
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. (See Definitions and Testing of ECLinPS AC Parameters in this publication.)
2. The single-ended propagation delay is defined as the delay from the 50% pOint of the input signal to the 50% point of the output signal.
_
(See Definitions and Testing of ECLinPS AC parameters in this publication.)
3. Enable is defined as the pro.l!agation delay from the 50% point of a negative transition on EN to the 50% point of a positive transition on Q
(or a negative transition on Q).
_
Disable is defined as the pr,Q.Pagation delay from the 50% point of a positive transition on EN to the 50% point of a negative transition on Q
(or a positive transition on Q).
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. The setup tim!..ls the minimum time that EN must be asserted prior to the next transition of IN/iN to prevent an output response greater than ± 75
mV to that INIIN transition (see Figure 1),_
6. The hold time is the minimum time that EN must remain asserted after a negative going IN or a positive going IN to prevent an output response
_
greater than :!:: 75 mV to that IN/iN' trnasitio~ee Figure 2).
7. The release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the
specified IN to Q propagation delay and output transition times (see Figure 3).
8. Vpp(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The Vpp(min) is AC limited
for the E111 as a differential input as low as 50 mV will still produce full ECl levels at the output.
9. VeMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to Vpp(min).

ECLinPS

3-16

MC10E111, MC100E111

Setup Time

Hold Time

~~
IN

"1
~ ~75mV1
o----v--l
EN

Q-f"\..-Tf

50%

~75 mV

o--v--l 1

Q---A...-TT

-~ ~

EN~
"

50%

a
Q

><=

~75mV

Figure 1

Release Time

Figure 2

ECLinPS
3-17

Figure 3

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

•
•
•
•

MC10E112
MC100E112

600 ps Max. Propagation Delay
Common Enable Input
Extended 100E VEE Range of -4.2 V to -5.46 V
75 k!l Input Pulldown Resistors

The MC10E/l00El12 is a quad driver with two pairs of ORINOR outputs from
each gate. and a common. buffered enable input. Using the data inputs the device
can serve as an ECL memory address fan-out driver. Using just the enable input.
the device serves as a clock driver. although the MC10E/l00Elll is designed specifically for this purpose. and offers lower skew than the El12. For memory address
driver applications where scan capabilities are required. please refer to the E212
device.

QUAD
DRIVER

LOGIC SYMBOL
PINOUT: 28-LEAD PLCC (TOP VIEW)

Qi 03a

Q3b

Q3a
22

Veeo Q2b
21

l'i2a:
/ " - - - - Q Oa

Veea

Q2b

Q2a

Vee

VEE

Qlb

Qla

Qlb

-----4

" ' - - - - Oob
....01----- 00.

'----Oob
/"----Ql.

°1---+--4

....<:>-----Qla
'-----Qlb

Qla

Veea 00.

QOb

QOa

QOb

Veea

~----Qlb

/"----Q2a
~----Q2b

A)-----l'i2a:
'-----Q2b
/"----Q3a

PIN NAMES

~-----Q3a

Function

Pin
00-0 3
EN
ana. onb
ana. onb

..A:ll----- Q3b

Data Inputs
Enable Input
True Outputs
Inverting Outputs

~----Q3b

ECLinPS
3-18

MC10E112, MC100E112
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veeo= GND
O°C

Symbol
I'H

Characteristic

min

typ

Input HIGH Current
D
EN

lEE

tpLH
tpHL

tSKEW

tr
If

max

min

typ

200
150

max

Unit

Condition

200
150
rnA

47
47

56
56

47
54

56
56

56
65

VEE = VEE(min) to VEE(max); Vec = Vcco= GND
25°C

O°C
Symbol

typ

IJA

Power Supply Current
10E
100E

ACCharacteristics:

min

200
150

85°C

25°C
max

85°C

Characteristic

min

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
D
EN

200
275

400
450

600
675

200
275

400
450

600
675

200
275

400
450

600
675

Condition

Within-Device Skew
Dn toQn, Qn
Qnato Qnb
Rise / Fall Times
20- 80%

Unit

ps
80
40

80
40

1
2
ps

275

425

700

275

425

700

1. Within-device skew is defined as identical transitions on similar paths through a device
2. Skew defined between common OR or common NOR outputs of a single gate.

ECLinPS

3-19

275

425

700

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TeCHNICAL DATA
•
•
•
•
•

500 ps Max. Propagation Delay
VSS Supply Output
Dedicated VCCO Pin for Each Receiver
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kG Input Pulldown Resistors

MC10E116
MC100E116

The MC10E/100E116 is a quint differential line receiver with emitter-follower outputs. An internally generated reference supply (VSS) is available for single-ended
reception.
Active current sources plus a deep collector feature of the MOSAIC III process
provide the receivers with excellent common-mode noise rejection. Each receiver
has a dedicated VCCO supply lead, providing optimum symmetry and stability.
The receiver design features clamp circuitry to cause a defined state if both the
inverting and non-inverting inputs are left open; in this case the Q output goes
lOW, while the IT output goes HIGH. This feature makes the device ideal for
twisted pair applications.
If both inverting and non·inverting inputs are at an equal potential of >-2.5 V,
the receiver does not go to a defined state, but rather current-shares in normal differential amplifier fashion, producing output voltage levels midway between HIGH
and lOW, or the device may even oscillate.
The device VSS output is intended for use as a reference voltage for singleended reception of ECl signals to that device only. When using for this purpose, it
is recommended that VSS is decoupled to VCC via a 0.01 JLF capacitor. Please refer
to the interface section of the design guide for information on using the E116 in
specialized applications.
The E116 features input pull-down resistors, as does the rest of the ECLinPS
family.
For application which require bandwidths greater than that of the E116, the E416
device may be of interest.

QUINT DIFFERENTIAL
LINE RECEIVER

LOGIC SYMBOL

PINOUT: 28-LEAD PLCC (TOP VIEW)

Veeo 04

Veeo

ii3

Vee

VEE

Ves

Veeo

a;D,

0, Veeo 00

Do Veeo

PIN NAMES
Pin

DO, 00-04, 04
00, 00-04, 04
VBB

Function

Differential Input Pairs
Differential Output Pairs
Reference Voltage Output

VBB 01----11

ECLinPS

3-20

MC10E116, MC100E116
DC Characteristics:

VEE = V EE(min) to VEE(max);

V cc = Vcco = GND

DoC
Symbol
VBB

Characteristic

min

typ

85°C
max

min

typ

max

-1.27 -1.35

-1.25 -1.31

-1.19

100E

-1.38

-1.26 -1.38

-1.26

Power Supply Current

Unit

Condition

V
-1.38

lEE

VCMR

25°C
max

10E

Input HIGH Current

Vpp(DC)

typ

Output Reference Voltage

I'H

min

200

IJA
mA

10E

100E

Input Sensitivity

150

Common Mode Range

-2.0

150
-0.6

150

-2.0

-0.6

-2.0

-0.6

1. VPP is the minimum differential input voltage required to assure full ECl levels are present at the outputs.
2. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the "HIGH" input is
within the VCMR range and the input swing is greater than VPPMIN and < 1V.
AC Characteristics:

VEE = V EE(min) to V EE(max);

V cc = V cco = GND

DOC
Symbol
tpLH
tpHL

Vpp(AC)
tSKEW

Characteristic

max

min

typ

max

min

typ

max

200

300

450

200

300

450

200

300

450

D(SE)

150

300

500

150

300

500

150

300

500

Propagation Delay to Output

Minimum Input Swing

Unit

Condition

150

Within-Device Skew

ps
50

±10

Duty Cycle Skew
tplH - tpHl

85°C

typ

Dn to an, an

tSKEW

25°C

min

Rise / Fall Times
20- 80%

ps
275

375

575

275

375

575

275

1 . M'nlmum ,nput sWing for which AC parameters are guaranteed.
2. Within-device skew is defined as identical transitions on similar paths through a device
3. Duty cycle skew defined only for differential operation when the delays are measured from the
cross point of the inputs to the cross points of the outputs

ECLinPS

3-21

375

575

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

MC10E122
MC100E122

• 500 ps Max. Propagation Delay
• Extended 100E VEE Range of -4.2 V to -5.46 V
• 75 kO Input Pulldown Resistors
DESCRIPTION
The MC10E/100E122 is a 9-bit buffer. The device contains nine non-inverting
buffer gates.

9-BIT

BUFFER

PIN NAMES
Pin
DO-OS
Qo-QS

Function
Data Inputs
Data Outputs

ECLinPS
3-22

MC10E122, MC100E122
DC Characteristics:

VEE = VEE(min) to VEE(max); Vcc = Vcco= GND
O°C

Symbol

Characteristic

I'H

Input HIGH Current

lEE

Power Supply Current
10E
100E

I----

AC Characteristics:

min

typ

min

tpLH
tpHL
tSKEW

max

min

typ

200

max

Unit

200

Condition

mA
41
41

49
49

41
41

49
49

41
47

49
57

VEE = VEE(min).to VEE(max); Vcc = Vcco = GND
25°C

85°C

Characteristic

min

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
DtoO

150

350

500

150

350

500

150

350

500

Within-Device Skew

Rise / Fall Times
20 -80%

Unit

Condition

DtoO
tr
tf

typ

200

O°C
Symbol

85°C

25°C
max

1
ps

300

425

800

300

425

800

1. Within-device skew IS defined as Identical transitions on similar paths through a deVice

ECLinPS

3-23

300

425

800

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA
•
•
•
•
•
•
•

1100 MHz Min. Toggle Frequency
Differential Outputs
Individual and Common Clocks
Individual Resets (asynchronous)
Paired Sets (asynchronous)
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kll Input Pulldown Resistors

MC10E131
MC100E131

4-BIT

The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (Cc) lOW
and using the Clock Enable (CE) inputs for clocking. Common clocking is achieved
by holding the CE inputs lOW and using Cc to clock all four flip-flops. In this case,
the CE inputs perform the function of controlling the common clock, to each flipflop.
Individual asynchronous resets are provided (R). Asynchronous set controls (5)
are ganged together in pairs, with the pairing chosen to reflect physical chip
symmetry.
Data enters the master when both Cc and CE are lOW, and transfers to the slave
when either Cc or CE (or both) go HIGH.
lOGIC SYMBOL

PINOUT: 28-lEAD PlCC (TOP VIEW)
D2

CE2

VCCO

o FLlP·FlOP

CE3

eE3-

~ I>

S12

VCC

VEE

eE2

>--L-- >

S03

CEO

CEl

VCCO

00--

S03
S12
Cc

00--

PIN NAMES
Pin
Do-D3
CEo-CE3
Ro-R3
Cc
S03,S12
00-0 3
00-0 3

eEl

H->

Ofr- 01
01--- 01

Function
Data Inputs
Clock Enables (Individual)
Resets
Common Clock
Sets (paired)
True Outputs
Inverting Outputs

RO
eEODO

ECLinPS

3·24

~I>

D
S

Ofr01--- 00

MC10E131, MC100E131
DC Characteristics:

VEE = V EE(min) to VEE(max); V cc = V cco = GND
O°C

Symbol
IIH

lEE

Characteristic

min

typ

Inpul HIGH Currenl
Cc

min

300

150

300
150

Condition

10E

100E

VEE = VEE(min) to VEE(max); Vcc = Vcco = GND

IpLH

Propagalion Delay 10 Output

typ

25°C

max

min

typ

85°C

max

1100 1400

min

typ

max

1100 1400

360

325

500

675

325

350

550

725

350

550

725

350

550

150

500

700

360

500

700

360

500

175

-20

400

150

700

500

675

325

500

675

550

725

350

550

725

350

550

725

150

175

-20

150

-20

400

150

400

150

ps
2

Hold Time
D

IAA

Reset Recovery Time

tpw

Minimum Pulse Widlh
Clk, S, R

Condition

MHz

SelupTime
D

Unit

ps
2
ps
ps
400

Within-Device Skew

400

400
60

ps
ps

Rise / Fall Times
20 -80%

Unit

450

Power Supply Current

1100 1400

350

450

Max. Toggle Frequency

max

300

f MAX

I SKEW

typ

O°C

min

max

fLA
350

Characteristic

IpHL

typ

350
450

ACCharacteristics:

Symbol

85°C

25°C

max

300
..

480

675

300

480

675

1. Within-device skew IS defined as Identical transitions on similar paths through a device
2. Setup/hold times guaranteed for both Cc & CE

ECLinPS
3-25

300

480

675

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

MC10E136
MC100E136

Product Preview
700MHz Min. Count Frequency
Look-Ahead-Carry Input and Output
Fully Synchronous Up and Down Counting
Asynchronous Master Reset
Internal 75kQ Input Pulldown Resistors
Extended 1OOE VEE Range of -4.2V to -5.46V

6-81T
UNIVERSAL
COUNTER

The MC 10E136/100E136 is an 6-bit synchronous, presettable, cascadable
universal counter.
The device offers a look-ahead-carry input and generates a look-ahead-carry
output. These two features allow for the cascading of multiple E136's to wider bit
widths that operate at nearly the same frequency as a stand alone counter. The
CLOUT output will pulse low for one clock cycle one count before the counter reaches
terminal count.
The COUT pin will pulse low for one clock cycle when the counter reaches
terminal count. The differential COUT output facilitates its use in programmable divider
and self-stopping counter applications.

PINOUT: 28-LEAD PLCC (TOP VIEW)
03

veea 05
22

veea

PIN NAMES

vee

VEE

veea

elK

eaUT

elN

eaUT

eLlN

CLOUT

DO veea 00

veea

FUNCTION

DO-D5
00-05
S1, S2
MR
CLK
COUT,COUT
CLOUT
CIN
CUN

Preset Data Inputs
Differential Data Outputs
Mode Control Pins
Master Reset
Clock Input
Carry Out Output (Active LOW)
Look-Ahead-Carry Output
Carry In Input (Active LOW)
Loak-Ahead-Carry Input

FUNCTION TABLE

CIN

ClK

L
L
L
H
H
H

L
H
H
L
L
H

Z
Z
Z
Z
Z
Z

L
L
L
L
L
L
H

L
H
L
H

X
X

Function
Preset Parallel Data Inputs
Increment ( Count Up )
Hold Count
Decrement ( Count Down)
Hold Count
Hold Count
Reset (On = LOW; COUT = HIGH)

Z = low to High Transition
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product
without notice.

ECLinPS

3-26

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA
~-

.
•
MC10E137

Product Preview
1.2GHz Min_ Count Frequency
Synchronous and Asynchronous Enable Pins
Differential Clock Input and Data Output Pins
Asynchronous Master Reset
Internal 75k.Q Input Pulldown Resistors
Extended IOOE VEE Range of ~4_2V to ~5_46V

...

-.----------~

MC100E137

The MCI OE/I OOEI37 is a very high speed binary ripple counteL The two least
significant bits were designed with very fast edge rates while the more significant bits
maintain standard ECLinPS output edge rates. This allows the counter to operate at
very high frequencies while maintaining a moderate power dissipation level.
Soth synchronous and asynchronous enables are available to maximize the
devices flexibility for various applications. The device is ideally suited for multiple
frequency clock generation as well as a counter in a high performance ATE time
measurement board.
The asynchronous Master Reset resets the counter to an all zero state upon
assertion.

a-BIT
RIPPLE
COUNTER

PIN NAMES
PIN

FUNCTION
-

CLK,C~
QO~Q7, QO~Q7

EN
ESI, ES2
MR
VSS

a1 a1

Differential Clock Inputs
Differential Q Outputs
Asynchronous Enable Input
Synchronous Enable Inputs
Asynchronous Master Reset
Switching Reference Output

a6 a6

a7 a7

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product
without notice.

ECLinPS
3-27

MOTOROLA

SEMICONDUCTOR - - - - -_ _ _ _ _ __

TECHNICAL DATA

•
•
•
•
•
•
•

MC10E141
MC100E141

700 MHz Min. Shift Frequency
8-Bit
Full-Function, Bi-Directional
Asynchronous Master Reset
Pin-Compatible with E241
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kll Input Pulldown Resistors

8-BIT
SHIFT REGISTER

The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs
serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs
DO-D7 accept parallel input data, while DUDR accept serial input data for left/right
shifting.
The select pins, SELO and SEL 1, select one of four modes of operation: Load,
Hold, Shift Left, Shift Right, according to the Function Table.
Input data is accepted a set-up time before the positive clock edge. A HIGH on
the Master Reset (MR) pin asynchronously resets all the registers to zero.
PINOUT: 28-LEAD PLCC (TOP VIEW)

SELO

I>]

Veeo Q7
FUNCTION TABLE

SEll

Vee

SELl

l
l
H
H

l
H
l
H

Function
load
Shift Right (On to On + 1)
Shift left (On to On -1)
Hold

PIN NAMES

Veeo

SELO

Function

00-07

DL, DR
SElO, SEll
ClK

00-0 7
MR

LOGIC SYMBOL

Parallel Data Inputs
Serial Data Inputs
Mode Select Inputs
Clock
Data Outputs
Master Reset

SEL1----~--~~--~--------~--+-~~----------~

SELO

--------~~--~------------~~~------------~

eLK----------~_+--------------~~r---------------~
MR------------~----------------~~----------------~

ECLinPS

3-28

MC10E141, MC100E141
DC Characteristics:

VEE = VEE(min) to VEE(max); Vcc = Vcco= GNO
O°C

Symbol

Characteristic

min

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

AC Characteristics:

typ

25°C
max

min

typ

150

min

150

Condition

mA
131

157

131

157

131

157

151

181

VEE = V EE(min) to VEE{max); Vcc = Vcco = GND

fSHIFT

Max. Shift Frequency

700

900

tplH
tpHl

Propagation Oelay to Output
Clk
MR

625
600

750
725

25°C

175

max

min

typ

700

900

625
600

750
725

175

85°C
max

min

typ

700

900

625
600

750
725

-125

175

350
300

+200
+150

350
300

+25
+200
+150

-25
-200

700

max

Unit

Condition

MHz
ps

975
975

Setup Time
D
SELO
SEL1

350
300

25
200
150

Hold Time
D
SELO
SEL1

200
100
100

-25
-200
-150

200
100
100

-25
-200
-150

200
100
100

tRR

Reset Recovery Time

900

700

900

700

900

tpw

Minimum Pulse Width
Clk,MR

400

t,
tf

150

157

typ

tSKEW

Unit

131

O°C

max

157

min

typ

131

Characteristic

Symbol

85°C
max

975
975
ps

-150
ps
ps

Within-Device Skew

400

Rise / Fall Times
20 -80%

ps
300

525

800

300

525

800

300

525

800

1. Within-device skew IS defined as Identical transilions on similar paths through a device

EXPANDED FUNCTION TABLE
Function

Load
Shift Right

X
X
X

Shift Left

L
H

Hold
Reset

X
X
X

L
H

X
X
X
X
X

SElO SEll
L
L
L
H
H
H
H

L
H
H
L
L
H
H

ClK

L
L
L
L
L
L
L
H

Z
Z
Z
Z
Z
Z
Z
X

DO
L
H
L
00
00
00
L

Dl
00
L
00
01
01
01
L

02
01
00
01
02
02
02
L

03
02
01
02
03
03
03
L

04
03
02
03
04
04
04
L

05
04
03

06
05
04
05
L
L
L
L

D7
06
05
L
H
H
H
L

ECLinPS

3-29

05
05
05
L

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

•
•
•
•
•
•

MC10E142
MC100E142

700 MHz Min. Shift Frequency
9-Bit for Byte-Parity Applications
Asynchronous Master Reset
Dual Clocks
Extended 100E VEE Range of -4.2 V to-5.46 V
75 kG Input Pulldown Resistors

9-BIT
The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applicaSHIFT REGISTER
tions in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in
one direction. The nine inputs DO-DB accept parallel input data, while S-IN accepts
serial input data.
The SEl (Select) input pin is used to switch between the two modes of operation
- SHIFT and lOAD. The shift direction is from bit 0 to bit B. Input data is accepted
by the registers a set-up time before the positive going edge of ClK1 or ClK2;
shifting is also accomplished on the positive clock edge. A HIGH on the Master
Reset pin (MR) asynchronously resets all the registers to zero.
lOGIC SYMBOL
PINOUT: 28-lEAD PlCC (TOP VIEW)
SEl

Veea

ClK1

ClK2

VCC

VEE

S·IN

Vcca

Vcca 00

FUNCTION TABLE
SEL

Mode

L
H

LOAD
SHIFT

PIN NAMES
Pin
00-08
S-IN
SEL
ClK1, ClK2
MR

Qo-Os

Function
Parallel Data Inputs
Serial Data Input
Mode Select Input
Clock Inputs
Master Reset
Data Outputs

ECLinPS

3-30

MC10E142, MC100E142
DC Characteristics:

VEE = VEE(min) to VEE(max); Vcc = Vcco= GND
25°C

O°C
Symbol

Characteristic

I'H

Input HIGH Current

lEE

Power Supply Current

min

typ

max

min

tpLH
tpHL

150

IlA

Condition

mA
145

120

145

100E

120

145

120

145

138

165

VEE = VEE(min) to VEE(max); Vcc = Vcco= GND

Characteristic

min

typ

Max. Shift Frequency

700

900

600
600

800
800

Propagation Delay to Output
Clk

SelupTime
D

25°C
min

typ

700

900

600
600

800
800

max

-100

300

150

300
75

85°C
max

min

typ

max

700

900

600
600

800

1000

800

1000

-100

300

150

300

150

100
-150

300
75

100
-150

300
75

100
-150

700

900

700

900

700

Condition

MHz

1000
1000

Hold Time

Resel Recovery Time

900

Ipw

Minimum Pulse Widlh
Clk,MR

400

ps
ps

Wilhin-Device Skew
Rise / Fall Times
20 -80%

Unit

IRR

Ir
I,

Unit

120

D
SEL

I SKEW

max

145

SEL
Ih

typ

120

MR
ts

min

150

O°C

'SHIFT

85°C
max

10E

AC Characteristics:

Symbol

typ

400
75

ps
ps

300
..

525

800

300

525

800

1. Within-deVice skew IS defined as Identical transitions on similar paths through a device

ECLinPS
3-31

300

525

800

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

•
.•
•
•
•
•

MC10E143
MC100E143

700 MHz Min. Operating Frequency
9-Bit for Byte-Parity Applications
Asynchronous Master Reset
Dual Clocks
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kO Input Pulldown Resistors

The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs
00-08 accepting parallel input data.
The SEl (Select) input pin is used to switch between the two modes of operation
- HOLD and lOAD. Input data is accepted by the registers a set-up time before
the positive going edge of ClK1 or ClK2. A HIGH on the Master Reset pin (MR)
asynchronously resets all the registers to zero.

LOGIC SYMBOL

PINOUT: 2a-lEAD PLCC (TOP VIEW)
SEl

VCCO

ClK1

ClK2

VCC

VEE

05·

VCCO

9-BIT
HOLD REGISTER

FUNCTION TABLE
SEl

Mode

l
H

lOAD
HOLD

PIN NAMES
Pin
DO-OS
SEl
ClK1, ClK2
MR

Oo-OS
NC

Function
Parallel Data Inputs
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
No Connection

SEl
elK1
ClK2
MR---C>-----------~

ECLinPS
3-32

MC1QE143, MC100E143
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veeo= GND
O°C

Symbol

Characteristic

I'H

Input HIGH Current

lEE

Power Supply Current
10E

min

25°C
max

min

150

145

120

145

120

145

138

165

VEE = VEE(min) to VEE(max); Vee = Vcco= GND

700

900

tpLH

Propagation Delay to Output
Clk

600
600

800
800

50
300

-100

MR
Setup Time
D
SEL

25°C
max

85°C
min

typ

700

900

600
600

800
800

-100

150

50
300

300
75

100
-150

300
75

100
-150

900

700

900

700

min

typ

700

900

600
600

800
800

-100

150

50
300

300
75

100
-150
700

max

D
SEL

Unit

Condition

MHz
ps

1000
1000

1000
1000
ps

150

Hold Time

tRR

Reset Recovery Time

900

tpw

Minimum Pulse Width
Clk,MR

400

ps
ps

Within-Device Skew

400
75

Rise / Fall Times
20 -80%

Condition

mA
120

Max. Toggle Frequency

tr
tf

Unit

145

f MAX

tSKEW

max

120

typ

145

min

120

Characteristic

tpHL

85°C
max
150

O°C
Symbol

typ

150

100E

ACCharacteristics:

typ

ps
300

525

800

300

525

800

1. Within-device skew IS defined as Identical transitions on similar paths through a deVice

ECLinPS

3-33

300

525

800

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . .. .
TECHNICAL DATA

MC10E150
MC100E150

• 800 ps Max. Propagation Delay
• Extended 100E VEE 'Range of ~4.2 V to -5.46 V
• 75 kG Input Pulldown Resistors

The MC10E/100E150 contains six D-type latches with differential outputs. When'
both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data
transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2
(or both) latches the data. The Master Reset (MR) overrides all other controls to set
the Q outputs low.

PINOUT: 28-lEAD PLCC (TOP VIEW)
LOGIC SYMBOL
MR

LEN2 LEN1
23

Veeo

115

00 - - - I

1i4

Os
VEE

Ci2
Do

VCCO

if," Veeo'

PIN NAMES
Pin
DO-OS
LEN1, LEN2
MR

00-0 5

00--05

Function
Data Inputs
Latch Enables
Master Reset
True Outputs
Inverting Outputs

LEN1
LEN2

ECLinPS

3-34

6-BIT
D LATCH

MC10E150, MC100E150
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veeo= GND
25°C

O°C
Symbol
IIH

lEE

f------

Characteristic

min

typ

max

min

85°C
max

min

typ

max

200
150

Power Supply Current

10E
100E

52
52

62
62

52
52

62
62

62
72

VEE = VEE(min) to VEE(max); Vee = Veeo= GND
O°C

85°C

25°C

min

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
D

250

375

250

375

550

250

375

550

375
450

500
625

550
700

375
450

500
625

700
750

375
350

500
625

700
750

200

Hold Time
D

200

-50

200

-50

200

-50

tRR

Reset Recovery Time

750

650

750

650

750

650

tpw

Minimum Pulse Width

tpHL

LEN
MR
ts

MR
tSKEW
t,
tf

Condition

750

ps
ps

400

Within-Device Skew
Rise I Fall Times
20-80%

Unit
ps

Setup Time
D

Condition

200
150

Characteristic

tpLH

Unit

IJ:A

Input HIGH Current
D
LEN, MR

ACCharacteristics:

Symbol

typ

400

ps
ps

300

450

650

300

450

650

1. Within-device skew IS defined as identical transitions on similar paths through a device

ECLinPS

3-35

300

450

650

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

•
•
•
•
•
•

MC10E151
MC100E151

1100 MHz Min. Toggle Frequency
Differential Outputs
Asynchronous Master Reset
Dual Clocks
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kO Input Pulldown Resistors

The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops
with differential outputs. Data enters the master when both ClK1 and ClK2 are
lOW, and is transferred to the slave when ClK1 or ClK2 (or both) go HIGH. The
asynchronous Master Reset (MR) makes all Q outputs go lOW.

6-BIT
D REGISTER

PINOUT: 28-LEAD PLCC (TOP VIEW)
MR

ClK2 ClK1

VCCO

115

LOGIC SYMBOL

li4

VCC

VEE

lio
01
01

VCCO

TIl

03
03

VCCO

fi4
PIN NAMES
Pin

00-0 5
ClK1, ClK2
MR

00-0 5
00-0 5

Function

Data Inputs
Clock Inputs
Master Reset
True Outputs
Inverted Outputs

ECLinPS

3-36

MC1 OE151, MC100E151
DC Characteristics:

VEE = VEE(min) to VEE(max); Vec = Vcco= GND
25'G

O'G
Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

ACCharacteristics:

min

typ

max

min

Max. Toggle Frequency

1100 1400

Propagation Delay to Output
Glk
MR

475
475

650
650

Hold Time
D

tRR
tpw

tSKEW
tr
tf

typ

max

Unit

150

Condition

78
78

65
65

65
75

78
78

78
90

VEE = VEE(min) to VEE(max); Vcc = Veco= GND

min

tplH
tpHl

min

mA
65
65

Characteristic

'MAX

85'G
max
150

150

O'G
Symbol

typ

min

typ

min

typ

max

1100 1400

Unit

Condition

MHz
ps

650
650

-175

350

175

Reset Recovery Time

750

550

Minimum Pulse Width
ClK, MR

400

800
850

475
475

650
650

-175

350

175

350

175

750

550

750

550

800
850
ps

ps
ps

Within-Device Skew
Rise / Fall Times
20-80%

max

1100 1400

475
475

Setup Time
D

85'G

25'C
max

400
65

ps
ps

300

450

700

300

450

700

1. Within-device skew is defined as identical transitions on similar paths through a device

ECLinPS

3-37

300

450

700

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

•
•
•
•
•
•
•

MC10E154
MC100E154

850 ps Max. LEN to Output
825 ps Max. 0 to Output
Differential Outputs
Asynchronous Master Reset
Dual Latch-Enables
Extended 100E VEE Range of -4.2 V to -5.46 V
75 Idllnput Pulldown Resistors

The MC10E/l00E154 contains five 2:1 multiplexers followed by transparent
latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW,
the latch is transparent, and output data is controlled by the multiplexer select control, SEl. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The
Master Reset (MR) overrides all other controls to set the Q outputs LOW.

LOGIC SYMBOL

PINOUT: 28-LEAD PLCC (TOP VIEW)
D4b

D4a

OJb

D3a Veeo

li3

SEL

,if.'

5-BIT
2:1 MUX-LATCH

Dna

Dab

LENl

Dla

LEN2

Vee

Dlb

VEE

D2a

D2b

0Ja

OJb

D4a

04.

D4b

D.t

Daa

01
01

Dla

Dlb

D2a

D2b Veeo

PIN NAMES
Pin
DOa-D4a
DOb-D4b
SEL
LEN', LEN2
MR

00-14
00-14

Function

SEL

Input Data a
Input Data b
Data Select Input
Latch Enables
Master Reset
True Outputs
Inverted Outputs

LENl
LEN2

ECLinPS

3-38

MC10E154, MC100E154
DC Characteristics:

VEE = VEE(min) to VEE(max);

Vee = Veeo = GND
25°C

O°C
Symbol

Characteristic

I'H

Input HIGH Current

lEE

Power Supply Current

r--

min

typ

max

min

150

tpHL

Unit

150

IlA

100E

105

VEE = V EE(min) to V EE(max); V cc = Vcco = GND

Characteristic

25°C

85°C

min

typ

max

min

typ

max

min

typ

max

325

500

700

325

500

700

325

500

700

Propagation Delay to Output
D

475

650

925

475

650

925

475

650

925

LEN

350

500

750

350

500

750

350

500

750

450

600

800

450

600

800

450

600

800

300

100

300

100

300

100

SEL

500

250

500

250

500

250

300
200

-100

-100
-250

300
200

-100

-250

300
200

800

600

800

600

800

600

Setup Time

Condition

Hold Time

Reset Recovery Time

tpw

Minimum Pulse Width

-250
ps
ps

400

MR
Within-Device Skew

400
50

Rise / Fall Times
20 - 80%
IS

Unit
ps

SEL

1. Within-deViCe skew

Condition

mA
76

tRA

max

SEL

typ

tSKEW

min

150

O°C

tplH

85°C
max

10E

AC Characteristics:

Symbol

typ

ps
300

475

800

300

475

800

defined as Identical transitions on similar paths through a device

ECLinPS

3-39

300

475

800

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

•
•
•
•
•
•
•

MC10E155
MC100E155

850 ps Max. LEN to Output
.825 ps Max. D to Output
Single-Ended Outputs
Asynchronous Master Reset
Dual Latch-Enables
Extended 100E VEE Range of - 4.2 V to - 5.46 V
75 kn Input Pulldown Resistors

The MC10E/100E155 contains six 2:1 mUltiplexers followed by transparent
latches with single-ended outputs. When both Latch Enables (LEN1, LEN2) are
LOW, the latch is transparent, and output data is controlled by the multiplexer
select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q
outputs LOW.

6-BIT
2:1 MUX-LATCH

LOGIC SYMBOL
PINOUT: 28-LEAD PLCC (TOP VIEW)
Dsa

Doa----i
D«b

D4a

D3b

D3a

Veeo
Dob----i

19
DSb

LEN1

LEN2

Vee

VEE

SEL

Veco

Doa
10
DOb

D1 a

D1b

D2a

D2b Veco

Dsa---+-i

PIN NAMES
Pin
DOa-D4a
DOb-D4b
SEL
LEN1, LEN2
MR

Qo--C4

Dsb---H

Function
Input Data a
Input Data b
Data Select Input
Latch Enables
Master Reset
Outputs

SEL
LENl
LEN2

ECLinPS
3-40

MC10E155, MC100E155
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veeo= GND
25°C

O°C
Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

AC Characteristics:

min

typ

max

min

85°C
max

min

typ

150

max

Unit

150

!lA

102
102

85
85

102
102

85
98

102
117

VEE = VEE(min) to VEE(max); Vee = Vceo = GND
85°C

25°C

Characteristic

min

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
D
SEL
LEN
MR

325
475
350
450

500
675
500
600

700
925
750
850

325
475
350
450

500
675
500
600

700
925
750
850

325
475
350
450

500
675
500
600

700
925
750
850

SelupTime
D

300

100

300

250

500

300
500

100

500

100
250

250

Hold Time
D
SEL

300
0

-100
-250

300
0

-100
-250

300
0

-100
-250

tRR

Reset Recovery Time

800

650

800

650

800

650

tpw

Minimum Pulse Width
MR

400

tpLH
tpHL

SEL
th

tSKEW
tr
t,

Condition

mA
85
85

O°C
Symbol

typ

Condition

ps
ps

Within-Device Skew
Rise / Fall Times
20-80%

Unit

400
75

ps
ps

300

450

800

300

450

800

"
1, Wllhln-devlce skew IS defined as IdentIcal transliions
on similar paths through a deVice

ECLinPS

3-41

300

450

800

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

•
•
•
•
•
•
•

MC10E156
MC100E156

950 ps Max. D to Output
850 ps Max. LENto Output
Differential Outputs'
Asynchronous Master Reset
Dual Latch-Enables
Extended 100E VEE Range of -4.2 V to -.5.46 V
75 kO Input Pulldown Resistors

The MC10EI100E156 contains three 4:1 multiplexers followed by transparent
latches with differential outputs. When both Latch Enables (LEN1,LEN2)'are LOW,
the latch is transparent, and output data is controlled by the multiplexer select controls (SELO, SELl). A logic HIGH on either LEN 1 or lEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.

LOGIC SYMBOL

PINOUT: 28-lEAD PlCC (TOP VIEW)
O, b

O,a

02d

02e

°2 b

02a Veeo
20

1---10

SELO

SELl

Vee

VEE

LEN1

LEN2

Veeo

ao
10

O,d

OOa

Dob

Doc

Dod Veeo

4:1

MUX

SElO
SEll .

PIN NAMES
Pin
Dox-DJX
SELO, SEL'
LEN', LEN2
MR
00-0 2
00-0 2

3-BIT
4: 1 MUX-LATCH'

Function

LENI
LEN2 .

Input Data
Select Inputs
Latch Enables
Master Reset
True Outputs
Inverted Outputs

ECLinPS
3-42

MC10E156, MC100E156
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veco= GND
25°C

O°C
Symbol

Characteristic

I'H

Input HIGH Current

lEE

Power Supply Current

min

typ

max

min

150

tpLH
tpHL

min

typ

max

Unit

150

!!A

100E

75
75

25°C

90
103

85°C

Characteristic

min

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
D

400

600

900

400

600

900

400

600

900

550
450

775

1050

900

500
600

800
825

350

650
500

900

350
350

650
500

550
450

775

900

550
450

775

650

350

600

350

600

D
SELO

400

275

400

275

400

275

700
600

300
400

700
600

300
400

700

SEL1

600

300
400

300

-275

300

-275

SELO
SEL1

100

-300

300
100

-400

200

-300
-400

100

200

-300
-400

800

600

800

600

800

600

SEL1
LEN
MR

800
825

tRR

Reset Recovery Time

tpw

Minimum Pulse Width
MR

tSKEW

ps
ps

400

Within-Device Skew

400
50

Rise I Fall Times
20-80%

Condition

900
825

Hold Time

Unit
ps

Setup Time

Condition

10E

SELO

t,
tf
.

85°C
max
150

O°C
Symbol

typ

ps
275

475

700

275

475

700

1. Within-device skew IS defined as Identical transitions on similar paths through a device

ECLinPS

3-43

275

475

700

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA.

MC10E157
MC100E157

Individual Select Controls
550 ps Max. D to Output
800 ps Max. SEL to Output
Extended I OOE VEE Range of -4.2V to -5.46V
Internal 75kQ Input Pulldown Resistors
The MC I OE/I 00E157 contains four 2: 1 multiplexers with differential outputs. The
ouput data are controlled by the individual Select (SEL) inputs. The individual select
control makes the devices well suited for random logic designs.

PINOUT: 28·LEAD PLCC (TOP VIEW)
SEL3

D3a

D3b vcco
22

D2b

D2a

SEL2

VCC

VEE

SEL1

D1a

D1b

SELO DOa

DOb

Veca

FUNCTION TABLE
SEL

Data

PIN NAMES
PIN

FUNCTION

DOa- D3a
DOb- D3b
SELO-SEL3
00-03
00-03

Input Data a
Input Data b
Select Inputs
True Outputs
Inverted Outputs

ECLinPS

3-44

QUAD
2:1 MULTIPLEXER

MC10E157, MC100E157
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veeo = GND
25°C

O°C
Symbol
IIH

lEE

Characteristic

min

typ

Input HIGH Current
D
SEL

min

tplH
tpHl

tSKEW
tr
tf

85°C
max

min

typ

max

Unit

Condition

I1A
200
150

200
150
mA

32
32

38
38

32
32

32
37

38
38

38
44

VEE = VEE(min) to VEE(max); Vee = Veea = GND
25°C

O°C
Symbol

typ

200
150

Power Supply Current
10E
100E

AC Characteristics:

max

85°C

Characteristic

min

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
D
SEL

220
425

380
600

550
800

220
425

380
600

550
800

220
425

380
600

550
800

Condition

Within-Device Skew
Rise/Fall Times
20 - 80%

Unit

ps
ps

275

400

650

275

400

650

1. Within-device skew IS defined as Identical transitions on similar paths through a device

ECLinPS

3-45

275

400

650

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . .. .

TECHNICAL DATA

•
•
•
•
•
•

MC10E158
MC100E158

600 ps Max. 0 to Output
800 ps Max. SEL to Output
Differential Outputs
One VCCO Pin Per Output Pair
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kG Input Pulldown Resistors

The MC10E/l00E158 contains five 2:1 multiplexers with differential outpvts. The
output data are controlled by the Select input (SEL).

5·BIT
2:1 MULTIPLEXER

PINOUT: 28~LEAD PLCC (TOP VIEW)

LOGIC SYMBOL

FUNCTION TABLE
SEL

Data

H
L

Dab

llo

O,a

O,b

D2lI

02b

Daa

Dab

04a

04b

Ao-As
a:
0

B>A

VEE

A=B.

::;;

A.!

VCCO

A>B

Bo-B8

PIN NAMES
Pin

Ao-Aa

Bo-Ba
A>B
B>A
A=B

Function

A Data Inputs
B Data Inputs
A Greater than B Output
B Greater than A Output
A Equal to B Output
(active-LOW)

ECLinPS
3-54

B>A

MC10E166, MC100E166
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veeo = GND

Characteristic

I'H

Input HIGH Current

lEE

Power Supply Current

min

typ

max

min

tpHL

t,
tf

max

min

typ

150

max

Unit

150

136

113

136

113

136

100E

113

136

113

136

130

156

VEE = V EE(min) to VEE(max); Vee = Veeo = GND

Characteristic

25°C

85°C

min

typ

max

min

typ

max

min

typ

max

DtoA=B

500

750

1100

500

750

1100

500

750

1100

DtoAB

500

850

1400

500

850

1400

500

850

1400

300

450

800

300

450

800

300

450

800

Propagation Delay to Output

Unit
ps

Rise / Fall Time
20 - 80%

Condition

mA
113

O°C

tpLH

typ

10E

AC Characteristics:

Symbol

85°C

25°C

O°C

Symbol

ECLinPS

3-55

Condition

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

•
•
•
•
•
•
•

MC10E167
MC100E167

1000 MHz Min. Operating Frequency
800 ps Max. Clock to Output
Single-Ended Outputs
Asynchronous Master Resets
Dual Clocks
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kG Input Pulldown Resistors

The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with
single-ended outputs. Input data are selected by the Select control, SEL. The
selected data are transferred to the flip-flop outputs by a positive edge on ClK1 or
ClK2 (or both). A HIGH on the Master Reset (MR) pin asynchronously forces all Q
outputs lOW.

lOGIC SYMBOL

PINOUT: 2S-lEAD PlCC (TOP VIEW)
Dsa

D4b

D4a

D3b

D3a

6-BIT
2:1 MUX-REGISTER

Veeo

Doa---f

1 - - - 00

Dob---f
DSb

ClKl
ClK2

Vce

VEE

SEl

Vceo

D, a --+-i

1 - - - 0,

Dsa--+-i

I---Os

Dob

D, a

D,b

D2a

D2b

VCCO

FUNCTION TABLE
SEL

Data

H
L

a
DSb _ _+-I

PIN NAMES
Pin
DOa-D5a
DOb-D5b
SEL
CLK1,CLK2
MR
Qo-0 5

Function

SEl

Input Data a
Input Data b
Select Input
Clock Inputs
Master Reset
Data Outputs

ClKl
ClK2

ECLinPS
3-56

MC10E167, MC100E167
DC Characteristics:

VEE = V EE(min) to VEE(max); Vee

=Vceo =GND
25°C

O°C

Symbol

Characteristic

min

I'H

Input HIGH Current

lEE

Power Supply Current

typ

max

min

150

113

100E

113

108

130

VEE

= V EE(min) to VEE(max);

Vee

1000 1400

tpLH

Propagation Delay to Output

=Vceo = GND

typ

85°C

25°C

max

min

typ

max

1000 1400

min

typ

max

1000 1400

650

800

450

650

800

450

650

800

450

650

850

450

650

850

450

650

850

100

-50

100

-50

100

-50

SEL

275

125

275

125

275

125

300

SEL

50
-125

300
75

50
-125

300
75

50
-125

750

550

750

550

750

550

Setup Time

Hold Time

tpw

Minimum Pulse Width
Clk,MR

ps
ps

400

Within-Device Skew

400

400
75

ps
ps

Rise / Fall Times
20-80%

Condition

ps
450

Reset Recovery Time

Unit
MHz

Clk

tRR

Condition

mA
113

Max. Toggle Frequency

tr
tf

Unit

f MAX

tSKEW

max

113

min

typ

Characteristic

min

150

O°C

tpHL

85°C

max

10E

AC Characteristics:

Symbol

typ

300
..

450

800

300

450

800

1. Within-device skew IS defined as Identical transitions on similar paths through a device

ECLinPS

3-57

300

450

800

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

•
•
•
•
•

MC10E171
MC100E171

725 ps Max. D to Output
Split Select
Differential Outputs
Extended 100E VEE Range of -4.2 V to -5.46 V
75 k!l Input Pulldown Resistors

The MC10E/100E171 contains three 4:1 multiplexers with differential outputs.
Separate Select controls are provided for the leading 2: 1 mux pairs (see logic sym·
bol). The three Select inputs control which one of the four data inputs in each case
is propagated to the corresponding output.

3·BIT
4:1 MULTIPLEXER

PINOUT: 28·LEAD PLCC (TOP VIEW)
Dlb

Dla

D2d

D2e

D2b

D2a

Veeo

LOGIC SYMBOL
DOa

2:1
MUX

DOb

SEL

SEL1A

li2

SEL1B

°2

SEL2

Vee

VEE

°1

Veea

01a

01b

Old

Ooa

Dob

DOC

Dod

Veea

DOC
Dod

Ole

2:1
MUX

Old

FUNCTION TABLE
Pin

State

SEL2
SELlA
SEL1B

H
H
H

Operation

028

Output c/d data
Input d data
Input b data

°2b

PIN NAMES

D2e

Pin
DOX-D2X
SELlA, SEL1B
SEL2

00-°2
'00-'02

Function
02d

Data Inputs
First-stage Select Inputs
Second-stage Select Input
True Output
Inverted Output

SEllA
SEL1B
SEL2

ECLinPS

3·58

li2

MC1 OE171, MC100E171
DC Characteristics:

VEE = VEE(min) to VEE(max); 'V ee = Veeo= GND
O°C

Symbol

Characteristic

I'H

Input HIGH Current

lEE

Power Supply Current

min

typ

25°C

max

min

150

tpLH

I SKEW

tr
tf

min

typ

150

max

Unit

150

flA

100E

VEE = VEE(min) to VEE(max); Vee = Veeo= GND

Characteristic

25°C

85°C

min

typ

max

min

typ

max

min

typ

max

275

480

650

275

480

650

275

480

650

SEll

450

650

850

450

650

850

450

650

850

SEL2

350

550

700

350

550

700

350

550

700

Propagation Delay to Output

Unit

Condition

Within-Device Skew

Dnm, Dnm to On

Da, Db, Dc, Dd 10 0

Rise / Fall Time
20-80%

Condition

mA
56

O°C

tpHL

85°C

max

10E

ACCharacteristics:

Symbol

typ

ps
300

475

650

300

475

650

300

475

650

1. Within-device skew IS defined as Identical transitions on similar paths through a device; n=O,l ,2 m=a,b,c,d.

ECLinPS

3-59

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

MC10E175
MC100E175

9-bit Latch
Parity Detection/Generation
800 ps Max. D to Output
Reset
Extended 1OOE VEE Range of -4.2V to -5.46V
Internal 75kr.! Input Pulldown Resistors
The Me 1OEl1 00E175 is a 9-bit latch. It also features a tenth latched output,
ODDPAR, which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH
if an odd number of the inputs are HIGH).
The E175 can also be used to generate byte parity by using D8 as the parity-type
select ( L = even parity, H = odd parity), and using ODDPAR as the byte parity output.
The LEN pin latches the data when asserted with a logical high and makes the
latch transparent when placed at a logic low level.

9-81T LATCH
WITH PARITY

PINOUT: 28·LEAD PLCC (TOP VIEW)

vcca

LOGIC SYMBOL

veea

vcc

DO----~---------------4 D

ODDPAR

bils

VEE

LEN

vcca

'·7
D8~~~------------~~ D
EN

veea

0
0
0

veea

>
:D

PIN NAMES
LEN------------------~

FUNCTION

DO- D8

Data Inputs

LEN

Latch Enable
Master Reset

MR
00-08
ODDPAR

MR----------------------~

Data Outputs
Parity Output

ECLinPS

3-60

MC10E175, MC100E175
DC Characteristics:

VEE

= VEE(min) to VEE(max);

Vee

= Veea = GND

O'C
Symbol

Characteristic

min

IIH

Input HIGH Current

lEE

Power Supply Current
10E
100E

AC Characteristics:

VEE

typ

min

IplH
tpHl

tRR
tSKEW

max

Characteristic

min

110
110

132
132

Vee

Propagation Delay to Output
DtoO
DtoODDPAR
LEN to 0
LEN to ODDPAR
MR to 0 (lpHl )
MR to ODDPAR (tpHl )

132
132

110
127

max

Unit

150

flA

Condilion

25'C

85°C

min

450
850
525
525
525
525

600 800
1150 1450
700 900
700 900
700 900
700 900

450
850
525
525
525
525

Setup Time
D(O)
D (ODDPAR)

275
900

100
700

275
900

Hold Time
D(O)
D (ODDPAR)

175
-300

-100
-700

175
-300

Reset Recovery Time

850

600

850

typ

132
152

= Veea = GND

max

min

600 800
1150 1450
700 900
700 900
700 900
700 900

450
850
525
525
525
525

typ

max

Unit

Condition

ps
600 800
1150 1450
700 900
700 900
700 900
700 900
ps

Within-Device Skew
LEN, MR
DtoO
Dto ODD PAR

850

600

ps
ps

75
75
200

75
75
200
ps

300
..

500

800

300

500

800

FUNCTION TABLE
D

ODDPAR

H
L

L
L
H

L
L
L
H

H
L

H if odd no. of Dn HIGH
H if odd no. of Dn HIGH

typ

150

1. Wlthm-devlce skew IS defmed as Identical transitions on similar paths through a device

X
X

min

mA
110
110

= VEE(min) to VEE(max);

Rise/Fall Times
20 - 80%

t,
tf

Iyp

150

O'C
Symbol

85'C

25'C
max

ECLinPS

3-61

300

500

800

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

•
•
•
•
•
•

MC10E193
MC100E193

Hamming Code Generation
a-Bit Word, Expandable
Provides Parity of Whole Word
Scannable Parity Register
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kO Input Pulldown Resistors

The MC10E/100E193 is an error detection and correction (EDAC) circuit. Modified
Hamming parity codes are generated on an 8-bit word according to the pattern
shown in the logic symbol. The P5 output gives the parity of the whole word. The
word parity is also provided at the PGEN pin, after OddlEven parity control and
gating with the BPAR input. This output also feeds to a 1-bit shiftable register, for
use as part of a scan ring.
The combinatorial part of the device generates the same code pattern as the
MC10193, a member of the MECL 10K family. The user is referred to the 10193
data sheet in the MECL Device Data Book for a fuller description of pattern expansion to long words, along with check bit generation and decoding schemes.
Used in conjunction with 12-bit parity generators such as the E160, a SECDED
(single error correction; double error detection) error system can be designed for a
multiple of an 8-bit word.

ECLinPS

3-62

ERROR DETECTIONI
CORRECTION CIRCUIT

MC10E193, MC100E193
DC Characteristics:

VEE

= VEE(min) to VEE(max);

Vee

=Vceo = GND
25°C

O°C
Symbol
IIH
lEE
f--

Characteristic

min

typ

Input HIGH Current

max

min

112
112

134
134

VEE = V EE(min) to VEE(max); Vee

Unit

150

112
112

134
134

112
129

155

=Vceo = GND
25°C

85°C

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
Bto P1, P2, P3, P4
BtoP5

350
400

700

1000
1150

350
400

700
775

1000
1150

350
400

700
775

1000
1150

350

650 850
1000 1450
550 850

350

650 850
1000 1450

350

600
300

650 850
1000 1450

400

150

400

300

50
350
250

300
750

775

600
300

550

850

600
300

550

850
ps

EV/OD
BPAR

750
500
1300
1300

1700 1100

Hold Time
SHIFT
S-IN
HOLD

-EN

EV/OD
BPAR
B

850

400

150

300

350
250
850

750
500
1300

850
1700 1100

1300

350
250
850
850

500
1300
1300

850

150

1700 1100
ps

200
300
100

-150

200

-150

-50
-350

300
100

-50
-350

100 -250
-200 -850
-200 -850
-300 -1100

100
-200

-250

300

200
300
100

-50
-350

100 -250
-200 -850
-200 -850
-300 -1100

-850

-200 -850
-300 -1100

Rise / Fall Times
20 -80%

Unit
ps

Setup Time

-HOLD

Condition

134

min

SHIFT
S-IN

t,
tf

max

Characteristic

ClK to PARERR

typ

10E
100E

EV/OD, BPAR to PGEN
Bto PGEN

min

150

O°C

tpLH
tpHL

85°C
max

Power Supply Currenl

AC Characteristics:

Symbol

typ

ps
300

700

1100

ECLinPS

3-63

7000 1100

700

1100

Condition

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA
2ns Worst Case Delay Range
~20ps I Delay Step Resolution
> 1GHz Bandwidth
On Chip Cascade Circuitry
Extended 100E VEE Range of -4.2V to -5.46V

MC10E195
MC100E195

The MC 1OEl1 OOE 195 is a programmable delay chip (PDC)
designed primarily forciockde-skewing and timing adjustment.
It provides variable delay of a differential ECl input transition.
The delay section consists of a chain of gates organized as
shown in the logic symbol. The first two delay elements feature
gates that have been modified to have delays 1.25 and 1.5
times the basic gate delay of approximately 80ps. These two
elements provide the E195 with adigitally-selectable resolution
of approximately 20ps. The required device delay is selected
by the seven address inputs D[0:6], which are latched on chip
by a high signal on the latch enable (lEN) control.
Because the delay programmability of the E195 is achieved
by purely differential ECl gate delays the device will operate
at frequencies of >1GHz while maintaining over 600mV of
output swing.
The E195 thus offers very fine resolution, at very high
frequencies, that is selectable entirely from a digital input
allowing for very accurate system clock timing.

PROGRAMMABLE
DELAY
CHIP
An eighth latched input, D7, is provided for cascading
multiple PDC's for increased programmable range. The cascade
logic allows full control of multiple PDC's, at the expense of only
a single added line to the data bus for each additional PDC,
without the need for any external gating.
02

LEN

vee

PIN NAMES
PINOUT: 28-LEAD PLCC
(TOP VIEW)

VEE

Function
IN

INIIN
EN
D[0:7]
Q/O
lEN
SET MIN
SET MAX
CASCADE

Signal Input
Input Enable
Mux Select Inputs
Signal Output
latch Enable
Min Delay Set
Max Delay Set
Cascade. Signal

VBB

veeo
10
Ne

(fJ

VBB------1

01 •

LOGIC DIAGRAM - SIMPLIFIED

veeo

• delays are 25% or %50 longer than
standard (standard",aOps)

ECLinPS

3-64

:;;
fW

(fJ

«
a
Ul
«
a

MC1 OE195, MC100E195

DC Characteristics:

VEE

= VEE(min) to VEE(max);

Vee

= Veeo = GNO

Symbol

Characteristic

min

I'H

Input HIGH Current

lEE

Power Supply Current

typ

max

min

150

tpHl

tRANGE

150

jlA

156

100E

130

156

130

156

150

179

VEE

= VEE(min) to VEE(max);

Characteristic

Vee

= Veeo = GNO

min

typ

25°C
max

min

typ

85°C
max

min

typ

max

Propagation Delay

Unit

Notes

=0
= 127
EN to Q; Tap = 0

1210 1360 1510 1240 1390 1540 1440 1590 1765
3320 3570 3820 3380 3630 3880 3920 4270 4720

07 to CASCADE

300

IN to Q; Tap
IN to Q; Tap

Condition

mA
130

1250 1450 1650 1275 1475 1675 1350 1650 1950
450

700

300

450

700

300

450

700

Programmable Range
2000 2175

2375 2580

2050 2240

Step Delay

03 High

ps
17

17.5

105

136

180

55
115

42
84

120

180

65
140

168

205

70
140

105

04 High

250

272

325

250

280

325

305

336

380

05 High

505

544

620

515

560

620

672

740

06 High

1000 1088 1190 1030 1120 1220 1240 1344 1450

Linearity

34
55
115

Duty Cycle Skew
±30

tpHL - tpLH

±30

Setup Time
o to LEN

200

OtolN

800

200

-EN to IN
th

Unit

156

02 High

max

130

01 High

tSKEW

typ

156

DO High

Lin

min

130

tpD (max) - tpD (min)
"'t

max
150

O°C

tplH

typ

10E

AC Characteristics:

Symbol

85°C

25°C

O°C

200

Hold Time

LEN to 0

500

IN to EN

250

500
0

ECLinPS

3-65

250

500
0

250
4

Mel0E195,MC100E195

AC Characteristics (Cant): VEE = VEE(min) to VEE(max)' Vcc = Vcco = GND'
QOC
Symbol
tR

4.
5.
6.
7.

min

Release Time
EN to IN
SET MAX to LEN
SET MIN to LEN

300
800
800

tji!

Jitter

Rise/Fall Time
20 - 80% (Q)
20 - 80% (CASCADE)

~
1.
2.
3.

Characteristic

typ

25°C
max

min

typ

85°C
max

min

typ

max

Unit

Notes

ps
300
800
800

300
800
800

ps
125
300

225
450

325
650

125
300

225
450

325
650

125
300

225
450

325
650

Duty cycle skew guaranteed only for differential operation measured from the cross point pf the input to the cross point of the output.
This setup time defines the amount of tim~rior to the input signal the delay tap of the device IJlllst be set.
This setup time is the minimumJime that EN must be asserted prior to the next transition of IN/IN to prevent an output response
greater than ±75mV to that IN/IN trimsit!2.0.
_
.
This hold time is the minimum time that EN mU'l!.remain asserted after a negative going IN or positive going IN to prevent an
output response greater than ±75mV to that IN/IN transition.
This release time is the minimum time that EN must be deasserted prior to the next INiiN transition to ensure an output response
that meets the specified IN to Q propagation delay and transition times.
Specifcation limits representthe amount of delay added with the assertion of each individual delay control pin. The various
combinations of asserted delay control inputs will typically realize DO resolution steps across the specified programmable range.
The linearity specification guarantees to which delay control input the programmable steps will be monotonic (ie. increasing delay
steps for increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the DO input, however under
worst case conditions and process variation, delays could decrease slightly with increasing binary counts when the DO input is the
LSB. With the D1 input as the LSB the device is guaranteed to be monotonic over all ~pecified environmental conditions and process
variation.
The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.

ECLinPS

3-66

MC10E195, MC100E195

Applications Information

A7--~----+-+-+-+-4-0

E195

vee
veca

Chip #1

vee
veca

Chip #2

Input

0
z x oWIW
:; ~ C3 {jvcco

lifi

>W >-

lifi

W '"
'-' '"
'-'

Output

a
{jvcco

WIW

:; ~ t3
>- >- Ul Ul
W
W '" '"
Ul "
'-'

Figure 1 - Cascading Interconnect Architecture
Cascading Multiple E19S's
To increase the programmable range of the E195 internal
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E195's without the need for any
external gating. Furthermore this capability requires only one
more address line per added E195. Obviously cascading
multiple poe's will result in a larger programmable range
however this increase is at the expense of a longer minimum
delay
Figure 1 illustrates the interconnect scheme for cascading
two E195's. As can be seen, this scheme can easily be
expanded for larger E195 chains. The 07 input of the E195 is
the cacade control pin. With the interconnect scheme of Figure
1 when 07 is asserted it signals the need for a larger
programmable range than is acheivable with a single device.
An expansion of the latch section of the block diagram is
pictured below. Use of this diagram will simplify the explanation
of how the cascade circuitry works. When 07 of chip #1 above
is low the cascade output will also be low while the cascade bar
output will be a logical high. In this condition the SET MIN pin
of chip #2 will be asserted and thus all of the latches of chip #2
will be reset and the device will be set at its minimum delay.
Since the RESET and SET inputs of the latches are overriding
any changes on the AO-AS address bus will not affect the

operation of chip #2.
Chip #1 on the other hand will have both SET MIN and SET
MAX de-asserted so that its delay will be controlled entirely by
the address bus AO-AS. If the delay needed is greater than can
be acheived with 31.75 gate delays (1111111 on the AO-AS
address bus) 07 will be asserted to signal the need to cascade
the delay to the next E 195 device. When 07 is asserted the SET
MIN pin of chip #2 will be de-asserted and the delay will be
controlled by the AO-AS address bus. Chip #1 on the other hand
will have its SET MAX pin asserted resulting in the device delay
to be independent of the AO-AS address bus.
When the SET MAX pin of chip #1 is asserted the 00 and
01 latches will be reset while the rest of the latches will be set.
In addition, to maintain monotonicity an additional gate delay is
selected in the cascade Circuitry. As a result when 07 of chip
#1 is asserted the delay increases from 31 .75 gates to 32 gates.
A 32 gate delay is the maximum delay setting for the E195.
To expand this cascading scheme to more devices one
simply needs to connect the 07 input and CASCAOE outputs
of the current most significant E 195 to the new most significant
E195 in the same manner as pictured in figure 1. The only
addition to the logic is the increase of one line to the address
bus for cascade control of the second POCo

[r=
Bill

CASC'O'

-CASCADE

Co,

SET MIN

-+....l..------l:--.L.----+.....l______+--L____-+__L

+-..l..____-l~

____

.....J

SET MAX_--'-______---'________....L________.l.....______.....l________...L______

Figure 2 - Expansion of the Latch Section of the E19S Block Diagram

ECLinPS

3-67

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

MC10E196
MC100E196

2ns Worst Case Delay Range
~20ps Digital Step Resolution
Linear Input for Tighter Resolution
>IGHz Bandwidth
On Chip Cascade Circuitry
Extended 100E VEE range of -4.2V to -5.46V
The MC1 OE/1 00E196 is a programmable delay chip (PDC)
designed primarily for very accurate differential ECl input edge
placement applications.
The delay section consists of a chain of gates and a linear
ramp delay adjust organized as shown in the logic symbol. The
first two delay elements feature gates that have been modified
to have delays 1.25 and 1.5 times the basic gate delay of
approximately BOps. These two elements provide the E196
with a digitally-selectable resolution of approximately 20ps.
The required device delay is selected by the seven address
inputs 0[0:6], which are latched on chip by a high signal on the
latch enable (lEN) control.
The FTUNE input takes an analog voltage and applies it to'
an internal linear ramp for reducing the 20ps resolution still
further. The FTUNE input is what differentiates the E196 from
the E195.

PROGRAMMABLE
DELAY
CHIP

An eighth latched input, 07, is provided for cascading
multiple POC's forincreased programmable range. The cascade
logic allows full control of multiple POC's, at the expense of only
a single added line to the data bus for each additional PDC,
without the need for any external gating.
D2

FTUNE

PIN NAMES
VCC

LEN

Function

PINOUT: 28-LEAD PLCC
(TOP VIEW)

VEE

IN/IN
EN
O['?,:7]
Q/Q
lEN
SET MIN
SET MAX
CASCADE
FTUNE

Signal Input
Input Enable
Mux Select Inputs
Signal Output
latch Enable
Min Delay Set
Max Delay Set
Cascade Signal
Linear Voltage Input

vcca

Q
vcca

VBB
10
NC

fW
C/l

LOGIC DIAGRAM- SIMPLIFIED

Lll

::;;

<
0

C/l

FTUNE

VBB---I

iN
EN

'delays are 25% or %50 longer than

standard

(slandard~80ps)

ECLinPS

3-68

MC1 OE196, MC100E196
DC Characteristics:

VEE

= VEE(min) to VEE(max);

Vee

= Veeo = GND
25°C

O°C
Symbol

Characteristic

min

IIH

Input HIGH Current

lEE

Power Supply Current

typ

max

min

150

tpHL

tRANGE

150

j.lA

130

156

100E

130

156

130

156

150

179

VEE

= VEE(min) to VEE(max);

Characteristic

Condition

mA
156

min

Vee

= Veeo = GND

typ

25°C
max

min

typ

85°C
max

min

typ

max

Propagation Delay

Unit

Notes

IN to Q; Tap = 0
~to Q; Tap = 127
EN to Q; Tap = 0

1210 1360 1510 1240 1390 1540 1440 1590 1765
3320 3570 3820 3380 3630 3880 3920 4270 4720
1250 1450 1650 1275 1475 1675 1350 1650 1950

D7 to CASCADE

300

450

700

300

450

700

300

450

700

Programmable Range
2000 2175

2375 2580

2050 2240

Step Delay

ps
17.5

17
34

105

120

D3 High

115

136

180

115

140

180

140

168

205

D4 High

250

272

325

250

280

325

305

336

380

D5 High

505

544

620

515

560

620

672

740

D6 High

1000 1088 1190 1030 1120 1220 1240 1344 1450

Linearity

D2 High

Duty Cycle Skew
±30

tpHl - tplH
ts

Unit

130

D1 High

tSKEW

max

156

DO High

Lin

typ

130

tpo (max) - tpo (min)
L1t

min

150

O°C

tpLH

85°C
max

10E

AC Characteristics:

Symbol

typ

±30

Setup Time

Dto LEN

200

Dto IN

800

EN to IN

200

Hold Time

LEN to D

500

INto EN

250

500
0

ECLinPS
3-69

250

500
0

250
4

MC1 OE196, MC100E196
AC Characteristics (Cant): VEE

= VEE(min) 10 VEE(max);

Vcc

= Vcco = GND

O°C
Symbol
IR

Ijil

Ir
I,
1.
2.
3.
4.
5.
6.
7.

Characteristic

min

Release Time
ENlo IN
SET MAX 10 LEN
SET MIN 10 LEN

300
800
800

typ

25°C
max

min

typ

85°C
max

min

typ

max

Unit

Notes

Jitter

300
800
800

Rise/Fall Time
20-80% (Q)
20 - 80% (CASCADE)

300
800
800

ps
125
300

225
450

325

125

650

300

225
450

325
650

125
300

225
450

325
650

Duty cycle skew guaranteed only for dlfferenltal operation measured from the cross pOint of the Input to the cross pomt of the output.
This setup time defines the amount of tim~rior to the input signal the delay tap of the device IJl1lst be set.
This setup time is the minimumjime that EN must be asserted prior to the next transition of IN/IN to prevent an output response
greater than ±75mV to that IN/IN transition.
This hold time is the minimum time that EN mus.lremain asserted after a negative going IN or positive going iN to prevent an
output response greater than ±75mV to that IN/IN transition.
This release time is the minimum time that EN must be deasserted prior to the next IN/iN transition to ensure an output response
that meets the specified IN to Q propagation delay and transition times.
Specifcation limits represent the amount of delay added with the assertion of each individual delay control pin. The various
combinations of asserted delay control inputs will typically realize DO resolution steps across the specified programmable range.
The linearity specification guarantees to which delay control input the programmable steps will be monotonic (ie. increasing delay
steps for increasing binary counts on the control inputs On). Typically the device will be monotonic to the DO input, however under
worst case conditions and process variation, delays could decrease slightly with increasing binary counts when the DO input is the
LSB. With the 01 input as the LSB the device is guaranteed to be monotonic over all specified environmental conditions and process
variation.
The jitter of the, device is less than what can be measured without resorting to very tedious and specialized measurement techniques.

Analog Input Characteristics: Flune = VCC 10 VEE

Propagation Delay vs Ftune Voltage (100E196)

140
120
(ij'

S
>ca
Qj

I\..

100
80

iCI

I\..
......

...

0
D-

......

t-h

o
-4.5

-3.5

-2.5

-1.5

Ftune Voltage (V)

ECLinPS

3-70

-0.5

MC10E196, MC100E196
Analog Input Characteristics (cont): Ftune

VCC to VEE

Propagation Delay vs Ftune Voltage (10E196)

'iii'

>ca
'iii

c:
0

iOl
ca

rr.

100
90
80
70
60
50
40
30
20
10
0

r--

1'\

r...

r-5

-4

-3

-2

-1

Ftune Voltage (V)

USING THE FTUNE ANALOG INPUT
The analog FTUNE pin on the E196 device is intended to
enhance the 20ps resolution capabilities of the fully digital
E195. The level of resolution obtained is dependent on the
number of increments applied to the appropriate range on the
FTUNE pin.
To provide another level of resolution the FTUNE pin must
be capable of adjusting the delay by greater than the 20ps
digital resolution. From the provided graphs one sees that this
requirement is easily achieved as over the entire FTUNE
voltage range a lOOps delay can be achieved. This extra
analog range ensures that the FTUNE pin will be capable even
under worst case conditions of covering the digital resolution.

Typically the analog input will be driven by an external
DAC to provide a digital control with very fine analog output
steps. The final resolution of the device will be dependent on
the width of the DAC chosen.
To determine the voltage range necessary for the FTUNE
input, the graphs provided should be used. As an example if a
range of 40ps is selected to cover worst case conditions and
ensure coverage of the digital range, from the 1OOE196 graph
a voltage range of -3.25V to -4V would be necessary on the
FTUNE pin. Obviously there are numerous voltage ranges
which can be used to cover a given delay range, users are given
the flexibility to determine which one best fits their designs.

ECLinPS

3-71

MC1 OE196, MC100E196
Applications Information
ADDRESS BUS (AD - AS)

" " " "

FTUNE

E196

vee

LEN

Chip #1

veca

VEE

LEN
VEE

I:>-- IN
Input
I:>-- iN

VBB

liD

,. ''"" "wr"
z

Q
C3 (jVCCO
en en
~ ~
en en

VBB

"'" "'"

liD

Figure 1 - Cascading Interconnect Architecture
Cascading Multiple E196's
To increase the programmable range of the E196 internal
cascade circuitry has been included. This circuitry allows for
the cascading of multiple E196's without the need for any
external gating. Furthermore this capability requires only one
more address line per added E196. Obviously cascading
multiple POC's will result in a larger programmable range
however this increase is at the expense of a longer minimum
delay.
Figure 1 illustrates the interconnect scheme for cascading
two EI96's. As can be seen, this scheme can easily be
expanded for larger E196 chains. The 07 input of the E196 is
the cacade control pin. With the interconnect scheme of Figure
1 when 07 is asserted it signals the need for a larger
programmable range than is acheivable with a single device.
An expansion of the latch section of the block diagram is
pictured below. Use of this diagram will simplify the explanation
of how the cascade circuitry works. When 07 of chip #1 above
is low the cascade output will also be low while the cascade bar
output will be a logical high. In this condition the SET MIN pin
of chip #2 will be asserted and thus all of the latches of chip #2
will be reset and the device will be set at its minimum delay.
Since the RESET and SET inputs of the latches are overriding
any changes on the AO-A6 address bus will not affect the

operation of chip #2.
Chip#1 on the other hand will have both SETMIN and SET
MAX de-asserted so that its delay will be controlled entirely by
the address bus AO-A6. If the delay needed is greater than can
be acheived with 31.75 gate delays (1111111 on the AO-A6
address bus) 07 will be asserted to signal the need to cascade
thedelaytothe next E196 device. When 07 is asserted the SET
MIN pin of chip #2 will be de-asserted and the delay will be
controlled by the AO-A6 address bus. Chip #1 on the other hand
will have its SET MAX pin asserted resulting in the device delay
to be independent of the AO-A6 address bus.
When the SET MAX pin of chip #1 is asserted the DO and
01 latches will be reset while the rest of the latches will be set.
In addition, to maintain monotonicity an additional gate delay is
selected in the cascade circuitry. As a result when 07 of chip
#1 is asserted the delay increases from 31.75gatesto 32 gates.
A 32 gate delay is the maximum delay setting for the E196.
When cacsading multiple POC's it will prove more cost
effective to use a single E196 for the MSB of the chain while
using E195 for the lower order bits. This is due to the fact that
only one fine tune input is needed to further reduce the delay
step resolution.

To sel"1}""'''

£F
Bit7

CASC'D'

-CASCADE

Co"

SET MIN

-+.....l---+....l.---+-...l...---I-...L-_--l_L__-+_L__--1---.!

SETMAX-....L----...L----.L.----L----1-----.l.-----

Figure 2 - ExpanSion of the Latch Section of the E195 Block Diagram

ECLinPS

3-72

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

Advanced Information

MC10E197

2:7 and 1:7 Rll Format Compatible
Fully Integrated VCO for 50Mb/s Operation
External VCO Input for Higher Operating Frequency
Anti-equivocation Circuitry to Ensure Pll lock
The MCl OE197 is an integrated data separator designed
for use in high speed hard disk drive applications. With data
rate capabilities of up to 50Mb/s the device is ideally suited for
today's and future state-of-the-art hard disk designs.
The E197 is typically driven by a pulse detector which
reads the magnetic information from the storage disk and
changes it into ECl pulses. The device is capable of
operating on both 2:7 and 1 :7 Rll coding schemes. Note that
the E197 does not do any decoding but rather prepares the
disk data for decoding by another device.
For applications with higher data rate needs, such as tape
drive systems, the device accepts an external VCO. The
frequency capability of the integrated VCO is the factor which
limits the device to 50Mb/s.
A special anti-equivocation circuit has been employed to
ensure timely lock-up when the arriving data and VCO edges
are coincident.
Unlike the majority of the devices in the ECLinPS family,
the E197 is available in only 10KH compatible ECL. The
device is available in the standard 28-lead PlCC.
Since the E197 contains both analog and digital circuitry,
separate supply and ground pins have been provided to
minimize noise coupling inside the device. The device can
operate on either standard negative ECl supplies or as is
more common on positive voltage supplies.

Data Separator

PINOUT: 28-Lead PLCC (TOP VIEW)
0

()

(5
()

()

()
N

'" '" '">'"
22

8
()
()

TEST

RDCLK

EXTVeo

RDCLK

ENveo

vee

VEE

RDATA

ACQ

RDATA
PUMPUP

TYPE

RSETDN

RDEN

II:

LOGIC SYMBOL

I~ "'"
II:

z
[i'

::;

=>
D..

()
()

RDEN----------------------,

REFCLK------------fp;;;~;;;;:;]

PUMPUP
VCOIN

PUMPDN

EXTVCO

RSETUP

ENVCO
ASETDN
RAWD

RDATA

ACQ
TYPE

RDCLK

This document contains information on a new product. Specifications and information herein are subject to change without notice.

ECLinPS

3-73

MC10E197
Pin Description
REFCLK

Reference clock equivalent to one clock cycle per decoding window.

RDEN

Enable data synchronizer when HIGH. When LOW enable the phase/
frequency detector steered by REFCLK.

RAWD

Data Input to Synchronizer logic.

VCOIN

VCO control voltage input

CAPI/CAP2

VCO frequency controlling capacitor inputs

---

ENVCO

VCO select pin. LOW selects the internal VCO and HIGH selects the
external veo input. Pin floats LOW when left open.

EXTVCO

External VCO pin selected when ENVCO is HIGH

ACO

Aquisistion circuitry select pin. This pin must be driven HIGH at the
end of the data sync field for some sync field types.

TYPE

Selects between the two types of commonly used sync fields. When
LOW it selects a sync field interspersed with 3 zeroes ( 2:7 RLL
code). When HIGH it selects a sync field interspersed with 2 zeroes
(1:7 RLL code).

TEST

Input included to initialize the clock flip-flop for test purposes only. Pin
should be left open (LOW) in actual application.

PUMPUP

Open collector charge pump output for the signal pump

PUMPDN

Open collector charge pump output for the reference pump

RSETUP

Current setting resistor for the signal pump

RSETDN

Current setting resistor for the reference pump

RDATA

Synchronized data output

RDCLK

Synchronized clock output

Vee. Veeo.
Veevco

Most positive supply rails. Digital and analog supplies are independent
on chip

VEE'VEEVeO

Most negative supply rails. Digital and analog supplies are independent
on chip

ECLinPS

3-74

MC10E197
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = GND or Vee = 4.75V to 5.25V; VEE = GND
25°C

O°C

Symbol

Characteristic

min

max

typ

min

typ

150

85°C

max

min

typ

max

Unit

150

J.lA

j.!A

Condition

I'H

Input HIGH Current

I'L

Input LOW Current

0.5

lEE

Power Supply Current

180

ISET

Charge Pump Bias Current

0.5

lOUT

Charge Pump Output

J.lA

Vee

max

Unit

150
0.5

0.5

Leakage Current
V AeT

PUMPUP/PUMPDN

V ee -2.5

Vee Vee -2.5

Vee

Vee -2.5

Active Voltage Range

10 KH LOGIC LEVELS
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veeo =Veco,=Veeveo= GND
OOG

Symbol

Characteristic

min

25°C

typ

max

min
-980

typ

85°C

max

min

typ

-810

-910

-720

V OH

Output HIGH Voltage

-1020

-840

VOL

Output LOW Voltage

-1950

-1630 -1950

-1595

V ,H

Input HIGH Voltage

-1170

-840 -1130

-810 -1060

-720

V ,L

Input LOW Voltage

-1950

-1480 -1950

-1445

max

Unit

Condition

POSITIVE EMITTER COUPLED LOGIC LEVELS
DC Characteristics:

VEE =V EEveo=GND;

Vee = V ecoo=VCCo,=Veeveo=+5 volts'
25°C

O°C

min

85°C

max

Characteristic

min

VOH

Output HIGH Voltage

3980

4160 4020

4190 4090

4280

VOL

Output LOW Voltage

3050

3370 3050

3405

V ,H

Input HIGH Voltage

3830

4160 3870

4190 3940

4280

V ,L

Input LOW Voltage

3050

3520 3050

3050 3050

3555

Symbol

typ

max

'VOH and VOL levels will vary 1: 1 with Vee

ECLinPS
3-75

typ

min

typ

Condition

MC10E197
AC Characteristics:

VEE = VEE(min) to VEE(max); Vce = GND or Vee = 4.75V to 5.25V; VEE = GND
O°C

Symbo

Time from RDATA Valid to
Rising Edge of RDCLK

Time from Rising Edge of
RDCLK to RDATA invalid

tSKEW

fvco

1.
2.
3.
4.
5.
6.
7.

Characteristic

min

25°C
max

Tvco-500

150

Tuning Ratio

1.53

300

1.53

max

Tvco

150
1.87

min

T vco-500

Tvco

300

Frequency of the VCO

85°C
max

Tvco -500

Tvco

Skew Between RDATA and
RDATA

min

150
1.87

1.53

Unit

4,7

MHz
1.87

Condition

Applies to the Input current lor each Input except VeOIN
For a nominal set current 01 3.72 mA, the resistor values lor RSETUP and RSETDN should be 130Q(0.1%). Assuming no variation
between these two resistors the current match between the PUMPUP and PUMPDN output signals should be within ±3%. ISET is
calculated as (VEE + 1.3v -V BE)/R; where R is RSETUP or RSETDN and a nominal value lor VBE is 0.85 volts.
Output leakage current 01 the PUMPUP or PUMPDN output signals when at a LOW level.
TVCD is the period 01 the yeo.
The veo Irequency determined with VeOIN = VEE + 0.5volts and using a 1OpF tuning capacitor.
The tuning ratio is delined as the ratio 01 I VCDMAX to IVCDMIN ,where IVCOMAX is measured at VeOIN = 1.3v + VEE and
IVCDMAX is measured at VeOIN = 2.6v + VEE'
Setup and hold timing diagrams:

If.o"~--Is-If.o·~--IH-I

Applications Information
General Operation
Operation

The E197 is a phase-locked loop circuit consisting of an
internal VCO, a Data Phase detector with associated acquisition
circuitry, and a PhaselFrequency detector(Fig. 1). In addition, an
enable pin(ENVCO) is provided to disable the internal VCO and
enable the external VCO input. Hence, the user has the option of

supplying the VCO signal.
The E197 contains two phase detectors: a data phase detector for synchronizing to the non-periodic pulses in the read data
stream during the data read mode of operation, and a phasel
frequency detector for frequency (and phase) locking to an external reference clock during the "idle" mode of operation. The read
enable (RDEN) pin muxes between these two detectors.

ECUnPS

3-76

MC10E197
Data Read Mode
The data pins (RAWD) are enabled when the RDEN pin is
placed at a logic high level, thus enabling the Data Phase
detector(Fig. 1) and initiating the data read mode. In this mode the
loop is servoed by the timing information taken from the positive
edges of the input data pulses. This phase detector samples
positive edges from the RAWD signal and generates both a pump
up and pump down pulse from any edge of the input data pulse.
The leading edge of the pump up pulse is time modulated by the
leading edge of the data signal, whereas the rising edge of the
pump up pulse is generated synchronous to the veo clock. The
falling edge of the pump down pulse is synchronous to the rising
edge of the veo clock and the rising edge of the pump down signal
is synchronous to the falling edge of the veo clock. Since both
edges of the veo are used the internal clock a duty cycle of 50%.
This pulse width modulation technique is used to generate the
servoing signal which drives the yeo. The pump down signal is
a reference pulse which is included to provide an evenly balanced
differential system, thereby allowing the synthesis of a veo input
control signal after appropriate signal processing by the loop filter.
By using suitable external filter circuitry, a control signal for
input into the veo can be generated by inverting the pump down
signal, summing the inverted signal with the pump up signal and
averaging the result. The polarity of this control signal is defined
as zero when the data edges lead the clock by a half clock cycle.
If the data edges are advanced with respect to the zero polarity
data/yeO edge relationship, the control signal is defined to have
a negative polarity; whereas if the veo is advanced with respect
to the zero polarity datalVeO edge relationship, the control signal
is defined to have a positive polarity. If there is no data edge
present at the RAWD input, the corresponding pump up and pump
down outputs are not generated and the resulting control output is
zero.
Acquisition Circuitry
The acquisition circuitry is provided to assist the data phase
detector in phase locking to the sync field that precedes the data.
Forthe case in which lock-up is attempted when the data edges are
coincident with the veo edges, the pump down signal may enter
an indeterminate state for an unacceptably long period due to the
violation of internal set up and hold times. After an initial pump
down pulse, the circuit blocks successive pump down pulses, and
inserts extra pump up pulses, during portions of the sync field that
are known to contain zeros. Thus the data phase detector is forced

to have a nonzero output during the lock-up period, and the
restoring force ensures correction of the loop within an acceptable
time. Hence, this circuitry provides a quasi-deterministic pump
down output signal, under the condition of coincident data and
veo edg~lIowing lock-up to occur without excessive delays.
The AeO line is provided to disable(disable = HIGH) the
acquisition circuit during the data portion of a sector block. Typically, this circuit is enabled at the beginning of the sync field by a
one-shot timer to ensure a timely lock-up.
The TYPE line allows the choice between two sync field
preamble types: transitions interspersed with two zeros between
transitions, or three zeros between transitions. These types of
sync fields are used with the 1 :7 and 2:7 RLL coding schemes,
respectively.
Idle Mode
In the absence of data or when the drive is writing to the disk,
PLL servoing is accomplished by pulling the read enable line
(RDEN) low and providing a reference clock via the REFCLK pins.
The condition whereby RDEN is low selects the Phase/FrequenCy
detector(Fig. 1) and the 1OE197 is said to be operating in the "idle
mode." In order to function as a frequency detector the input
waveform must be periodic. The pump up and pump down pulses
from the Phase/Frequency detector will have the same frequency,
phase and pulse width only when the two clocks that are being
compared have their positive edges aligned and are of the same
frequency.
As with the data phase detector, by using suitable external
filter circuitry, a VCO input control signal can be generated by
inverting the pump down signal, summing the inverted signal with
the pump up signal and averaging the result. The polarity of this
control signal is defined as zero when all positive edges of both
clocks are coincident. For the case in which the frequencies of the
two clocks are the same but the clock edges of the reference clock
are slightly advanced with respect to the veo clock, the control
signal is defined to have a positive polarity. A control signal with
negative polarity occurs when the edges of the reference clock are
delayed with respect to those of the yeo. If the frequencies of the
two clocks are different, the clock with the most edges per unit time
will initiate the most pulses and the polarity of the detector will
reflect the frequency error. Thus, when the reference clock is
higher in frequency than the veo clock the polarity of the control
signal is positive; whereas a control signal with negative polarity
occurs when the frequency of the reference clock is lower than the
veo clock.

Phase Lock Loop Theory
Introduction
f---..-----ox"I'i

Phase lock loop (PLL) circuits are fundamentally feedback
systems used to synchronize the frequency of an oscillator to an
incoming signal. In addition to frequency synchronization, the PLL
circuitry is designed to minimize the phase difference between the
system input and output signals. A block diagram of a feedback
control system is shown in Figure 1.
where:
A(s) is the product of the feed-forward transfer functions.

Figure 1 - Feedback System

ECLinPS

3-77

MC10E197
B(s) is the product of the feedback transfer functions.

NRZ
Data Sequence

The transfer function for this closed loop system is

A(s)
1 + A(s)B(s)
Typically, phase lock loops are modeled as feedback systems connected in a unity feedback configuration(B(s)=l) with a
phase detector, a VCO(voltage controlled oscillator), and a loop
filter in the feed-forward path, A(s). Figure 2 illustrates a phase
lock loop as a feedback control system in block diagram form.

Code Sequence

00
01

1000
0100

100
101
111

001000
100100
000100

1100
1101

00001000
00100100

Table 1 - 2:7 RLL Encoding Table

NRZ
Data Sequence

Figure 2 - Phase Lock Loop Block Diagram

XOl
010

XOO

1100
1101
1110
1111

The closed loop transfer function is:

1 + Kq,

Code Sequence

00
01
10

--f F(s)

010001

XOOOOO
XOOOOl
010000

An X in the leading bit of a code sequence
is assigned the complement of the bit

where:
K,= the phase detector gain.
Ko= the VCO gain. Since the VCO introduces a pole at
the origin of the s-plane, Ko is divided by s.
F(s) = the transfer function of the loop filter.

Table 2 - 1 :7 RLL Encoding Table

Sync Pattern

The 10E197 is designed to implementthe phase detector and
VCO functions in a unity feedback loop, while allowing the user to
select the desired filter function.

Gain Constants
As mentioned, each of the three sections in the phase lock
loop block diagram has an associated open loop gain constant.
Further, the gain constant of the filter circuitry is composed of the
product of three gain constants, one for each filter subsection. The
open loop gain constant of the feed-forward path is given by
eqt. 1

Read Mode

Idle Mode

2:7

121 mV/radian

484 mV/radian

1:7

161 mV/radian

483 mV/radian

Table 3 - Phase Detector Gain Constants

VCO Gain Constant
The gain of the VCO is a function of the tuning capacitor. For a
value of 10 pF a nominal value of the gain,Ko,is 20MHz per volt.

and obtained by performing a root locus analysis.

Filter Circuitry Gain Constant(s)

Phase Detector Gain Constant

The open loop gain constant of the filter circuitry is given by:

The gain of the phase detector is a function of the operating mode
and the data pattern. The 1OE197 provides data separation for
signals encoded in 2:7 or 1:7 RLL encoding schemes; hence
Tables 1 and 2 are coding tables for these schemes. Table 3 lists
nominal phase detector gains for both 2:7 and 1:7 sync fields.

eqt. 2

The individual gain constants are defined in the appropriate
subsections of this document.

ECLinPS
3-78

MC10E197
Loop Filter
The two major functions of the loop filter are to remove any
noise or high frequency components present in the phase detector
output signal, and more importantly to control the characteristics
which determine the dynamic response of the phase lock loop i.e.
capture range, loop bandwidth, capture time, and transient response.
Although a variety of loop filter. configurations exist, this
section will only describe a filter capable of performing the signal
processing as described in the Data Read Mode and the Idle Mode
sections. The loop filter consists of a differential summing amplifier
cascaded with an augmenting integrator which drives the VeOIN
input to the 1OE197 through a resistor divider network(Fig. 3).
The transfer function and the element valL\es for the loop filter
are derived by dividing the filter into three cascaded subsections:
filter input, augmenting integrator, and the voltage divider
network(Fig.4).

~ (s)

Figure 4 - Loop Filter Block Diagram
A root locus analysis is performed on the open loop transfer
function to determine the final pole-zero locations and the open
loop gai n constant for the phase lock loop. Note that the open loop
gain constant impacts the crossover frequency and that a lower
frequency crossover point means a much more efficient filter.
Once these positions and constants are determined the component values may be calculated.
R,

Loop Filter Transfer Function
MC34182

The open loop transfer function of the phase lock loop is the
product of each individual filter subsection, as well as the phase
detector and veo. Thus, the open loop filter transfer function is:

Fo (s); K

* -s- * F1 (s) * ~ (s) * Fd(s)
R,

where:
Vccvco

F1(S)

K1
(s + P1)

~ (s)

Fd(s)

[s2+ (21;0001 ) s +

0)~11
Filter Input

(s + z)
[s2+(21;00
)s+0)21
02
02

1
(s + P2 )

Figure 5 - Filter Input Sunsection

The primary function of the filter input subsection is to convert
the output of the phase detector into a single ended signal for
subsequent processing by the integrator Circuitry. This subsection
consists of the 1OE197 charge pump current sinks, two shunt
capacitors, and a differential summing amplifier(Fig. 5).

PUMPUPo---->r-vVV-~--~~---~-~~~-~~-~

Rv
MC34182

PUMPDN o-----r~'V'v-_+

Vccvco

VEEVCO

Vccvco

Figure 3 - Loop Filter Circuitry

ECLinPS

3-79

MC10E197
RSETUP

0-___.------,
4640

~--_--o

464n

4640:

op-amp are obtained from the data sheets. Typically, op-amp
manufacturers do not provide information on the location of the
second open loop pole, however it can be approximated by
measuring the roll off olthe op-amp in the open loop configuration;
the second pole is located where the gain begins to decrease at a
rate of 40dB per decade. The inclusion of both poles in the
differential summing amplifier transfer function becomes important when closing the feedback path around the op-amp because
the poles migrate; and this migration must be accounted for to
accurately determine the phase lock loop transient performance.

RSETDN

4640

Veevco

Typically theop-amp poles can be approximated by a pole
pair occurring as a complex conjugate pair making an angle of 45°
to the real axis of the complex frequency plane. Two constraints
on the selection of the op-amp pole pair are that the poles lie
beyond the crossover frequency and they are pOSitioned for near
unity gain operation. Performing a root locus analysis on the opamp open loop configuration and adhering to the two constraints
yields the pole pOSitions contributed by the op-amp.

Electronic Switch

Figure 6 - Dual Bandwidth Current
Source Implementation
Hence, this portion of the filter circuit contributes a real pole
and two complex poles to the overall loop transfer function F(s).
Before these pole locations are selected, appropriate values for
the current setting resistors(RSETUP and RSETDN) must be ascertained. The goal in choosing these resistor values is to
maximize the gain of the filter input subsection while ensuring the
charge pump output transistors operate in the active mode. The
filter input gain is maximized for a charge pump current of 1.1 mA;
a value of 4640 for both RSETUP and RSETDN yields a nominal
charge pump current of 1.1 mAo
It should be noted that a dual bandwidth implementation of the
phase lock loop may be achieved by modifying the current setting
resistors such that an electroniC switch enables one of two resistor
configurations. Figure6 shows a circuit configuration capable of
providing this dual bandwidth function. Analysis of the filter input
circuitry yields the transfer function:

Determination of Element Values
Since the difference amplifier is configured to operate as a
differential summer the resistor values associated with the amplifier are of equal value. Further, the typical input resistance to the
summing amplifier is 1 kn; thus the op-amp resistors are set at 1
kO. Having set the input resistance to the op-amp and selected the
position of the real pole, the value of the shunt capacitors is
determined using the following relationship:

Ip 1 I= -2-1t~~-C1 IN

eql. 4

Augmenting Integrator
The augmenting integrator consists of an active filter with a
lag-lead network in the feedback path(Fig. 7).

The gain constant is defined

as:

K =A __1_
1
1 CIN

RIA

"'N
eqt. 3
MC34182

where:

+
A 1 = op-amp gain constant for the
selected pole positions.

RIA

CIN = phase detector shunt capacitor.
VCCVCO

The real pole is a function of the input resistance to the op-amp and
the shunt capacitors connected to the phase detector output. For
stability the real pole must be placed beyond the unity gain
frequency; hence, this pole is typically placed midway between the
unity crossover and phase detector sampling frequency, which
should be about ten times greater.
The second order pole set arises from the two pole model for
an op-amp. The open loop gain and the first open loop pole for the

V02

Figure 7 - Integrator Subsection
Analysis of this portion of the filter circuit yields the transfer
function:

ECLinPS
3-80

* _1_ *
s

(s + z)
[s2+(2~0))S + 0)2

MC10E197
Voltage Divider

The gain constant is defined as:

The input range to the VCOIN input is from 1.3v + VEE to 2.6v
+ VEE' hence the output from the augmenting amplifier section
must be attenuated to meet the VCOIN constraints. A simple
voltage divider network provides the necessary attenuation(Fig.

eqt. 5
where:

8).

A I ; op-amp gain constant for selected

Rv
~No-------~~~--~------~~----~

pole positions.
R A ; integrator feedback resistor.

RIA; integrator input resistor.
The integrator circuit introduces a zero, a pole at the origin, and a
second order pole set as described by the two pole model for an
op-amp. As in the case of the differential summing amplifier, we
assume the op-amp pole pair occur as a complex conjugate pair
making an angle of 45° to the real axis of the complex frequency
plane; are positioned for near unity gain operation; and are located
beyond the crossover frequency. Since both the summing and
integrating op-amps are realized by the same type of opamp(MC34182D), the open loop pole positions for both amplifiers
will be the same.
Further, the loop transfer function contains two poles located
at the origin, one introduced by the integrator and the other by the
VCO; hence a zero is necessary to compensate for the phase shift
produced by these poles and ensure loop stability. The op-amp
will be stable if the crossover pOint occurs before the transfer
function phase angle becomes 180°. The zero should be positioned much less than one decade before the unity gain frequency.
As in the case of the filter input circuitry, the poles and zero
from this analysis will be used as open loop poles and a zero when
performing the root locus analysis for the complete system.

Figure 8 - Voltage Divider Subsection
In addition, a shunt filter capacitor connected between the
VCOIN input pin and VEE provides the voltage divider subsection
with a single time constant transfer function that adds a pole to the
overall loop filter. The transfer function for the voltage divider
network is:

The gain constant, Kd, is defined as:

eqt. 9

Determination of Element Values
The location of the zero is used to determine the element values
for the augmenting integrator. The value of the capacitor, CA, is
selected to provide adequate charge storage when the loop is not
sampling data. A value of 0.1 ~F is sufficient for most applications;
this value may be increased when the RDCLK frequency is much
lower than 4 MHz. The value of RA is governed by:

I I=
z

-2-1t-R"'-A--A
C

eqt. 6

The value of Kd is easily extracted by rearranging Equation 1 :
Kol

eqt. 10

Kd ; K * K * K * K
<\l

The gain constant Kd is set such that the output from the integrator
circuit is within the range 1.3v +VEE to 2.6v +VEE.
The pole for the voltage divider network should be positioned an
octave beyond that for the filter input.

Determination of Element Values
For unity gain operation of the integrating op-amp the value of R'A
is selected such that:

eqt. 7

It should be noted that although the zero can be tuned by varying
either RA or C A' caution must be exercised when adjusting the zero
by varying CA because the integrator gain is also a function of CA.
Further, the gain of the loop filter can be adjusted by changing the
integrator input resistor R,A.

Once the pole location and the gain constant Kd are established
the resistor values for the voltage divider network are determined
using the design guidelines mentioned above and from the following relationship:

Having determined the resistor values, the filter capacitor is
calculated by rearranging Equation 9:

ECLinPS
3-81

MC10E197.
Finally, a bias diode is included in the voltage divider network to
provide temperature compensation. The finite resistance of this
diode is neglected for these calculations.

eqt. 9a

Calculations For a 2:7 Coding Scheme
Introduction

positioned midway between the unity crossover point and the
phase detector sampling frequency. Hence, the open loop filter
input pole position is selected as:

The circuit component values are calculated for a 2:7 coding
scheme employing a data rate of 23 MbiVsec. Since the number
of bits is doubled when the data is encoded, the data clock is at half
the frequency of the RDCLK signal. Thus the operating frequency
for these calculations is 46 MHz. Further, the pole and zero
positions are a function of the data rate, hence the component
values derived by these calculations must be scaled if a different
operating frequency is used. Finally, it should be noted that the
values are optimized for settling time.
The analysis is divided into three parts: static pole positioning,
dynamic pole positioning, and dynamic zero positioning. Dynamic
poles and zeros are those which the designer may position, to yield
the desired dynamic response, through the judicious choice of
element values. Static poles are not directly controlled by the
choice of component values.

The voltage divider pole is set approximately one octave
higher than the filter input pole. Thus the open loop voltage divider
pole position is picked to be:

P~ = -2.57 MHz

Dynamic Zero
Finally, the zero is positioned much less than one decade
before the crossover frequency; for this design the zero is placed

at:

Static Poles

z =-311 Hz
Each op-amp introduces a pair of "static" complex conjugate
poles which must lie beyond the crossover frequency. As obtained
from the data sheets and laboratory measurements the two open
loop poles for the MC34182D are:

Once the dynamic pole and zero positions have been determined,
the phase margin is determined using a Bode plot; if the phase
margin is not sufficient, the dynamic poles may be moved to
improve the phase margin. Finally, a root locus analysis is
performed to obtain the optimum closed loop pole positions forthe
dynamic characteristics of interest.

P;a=-0.1 Hz
P;b= -11.2 Hz

Component Values

Performing a root locus analysis and following the two guidelines
previously stated, an acceptable pole set is:

Having determined the closed loop pole and zero positions
the component values are calculated. From the root locus analysis
the dynamic pole and zero positions are:

P1a = -5.65 + j5.65 MHz
P1b = -5.65 - j5.65 MHz

P 1 = -573 kHz

Both op-amps introduce a set 01 static complex-conjugate poles at
these positions for a total of four poles. Further, the loop gain for
each op-amp associated with these pole positions is determined
from the root locus analysis to be:

P 2 = -3.06 MHz
z

=-311 Hz

Filter Input Subsection
Rearranging Equation 4:
In addition to the op-amps, the integrator and the VCO each
contribute a static pole at the origin. Thus, there are a total of six
static poles.

Dynamic Poles
The filter input and the voltage divider sections each contribute a
dynamic pole. As stated previously, the filter input pole should be

and substituting 573 kHz for the pole position and 1 k.Q for the
resistor value yields:

ECLifiPS
3-82

MC10E197
Having determined the gain constant Kd, the value of R, is selected
such that the constraints R, > Ro and:

Augmenting Integrator Subsection

f«J

Rearranging Equation 6:

21tiP2iare fulfilled. The pole position P, is determined from the root locus
analysis to be:

and substituting 311 Hz for the zero position and 0.1 fl F for the
capacitor value yields:
RA = 5.11

P 2 : -3.06 MHz
Hence, R, is selected to be:

Rv = 2.15 kO

From Equation 7 the value for the other resistors associated with
the integrator op-amp are set equal to RA :

and Ro is calculated to be:
Ro

RIA: R A :

5.11

= 700

Finally, using Equation 8a:

Voltage Divider Subsection

eqt. 8a

The element values for the voltage divider network are calculated using the relationships presented in Equations 8, 9, and 10
with the constraintthat this divider network must produce a voltage
that lies within the range 1.3v + VEE to 2.6v + VEE'
Restating Equation 9,

Note that the voltage divider section can be used to set the gain,
but the designer is cautioned to be sure the input value to VCOIN
is within the correct range.

Kd : K • K • K' K

Ro and:

and substituting 311 Hz for the zero position and 0.1 J.IF for the
capacitor value yields:

are fulfilled. The pole position P2 is determined from the root locus
analysis to be:

RA = 5.11 kQ

P 2 = -2.73 MHz
From Equation 7 the value for the other resistors associated with
the integrator op-amp are set equal to RA :

Hence, R, is selected to be:
Rv = 2.15kQ
and Ro is calculated to be:

Voltage Divider Subsection
Ro
The element values for the voltage divider network are calculated using the relationships presented in Equations 8, 9, and 10
with the constraint that this divider network must produce a voltage
that lies within the range 1.3v + VEE to 2.6v + VEE.
Restating Equation 9,

= 453 n

Finally, using Equation 8a:

eqt. 8a

the capacitor value Cd is calculated to be:

From the root locus analysis Ko' is determined to be:

EGLinPS
3-85

MC10E197
Again, note the voltage divider section can be used to setthe gain,
but the designer is cautioned to be sure the input value to VCOIN
is within the correct range.

Thus the element values for the filter are:
Filter Input Subsection:

= 588 pF

Component Scaling

C IN

As mentioned, these design equations were developed for a
data rate of 20 Mbitlsec. If the data rate is different from the
nominal design value the reactive elements must be scaled
accordingly. The following equations are provided are to facilitate
scaling and were derived with the assumptions that a 1:7 coding
scheme is used and that the RDCLK signal is twice the frequency
of the data clock:

R1 = 1 kQ

Integrator Subsection:

CA = 0.1 J.tf
R A =5.11kQ

CIN=294*~
f
Cd = 156 *

(pF)

eqt. 13

(pF)

eqt. 14

R IA = 5.11 kQ
Voltage Divider Subsection:

where f is the RDCLK frequency in MHz.

Cd = 312

Example for an 10 Mbit/sec Data Rate

Rv = 2.15 kQ

As an example of scaling, assume the given filter and a 1:7
code are used but the data rate is 10 Mbitlsec. The dynamic pole
positions, and therefore the bandwidth of the loop filter,are a
function of the data rate. Thus a slower data rate will force the
dynamic poles and the bandwidth to move to a lower frequency.
From Equation 13 the value of C'N is:

Ro = 453 Q

C IN = 588 pF
and from Equation 14 the value of Cd is:

C d =312

Note, the poles P, and P2 are now located at:

P 1 = -271 kHz

= -1.36 MHz

And, the open loop filter unity crossover point is at 300 kHz.
As in the case of the 2:7 coding scheme, the gain can be adjusted
by changing the value of R'A and the value of Cd' Varying the gain
by changing Cd is not recommended because this will also move
the poles, hence affect the dynamic performance of the filter.

ECLinPS
3-86

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

MC10E212
MC100E212

Scannable Version El12 Driver
1025ps Max. ClK to Output
Dual Differential Outputs
Master Reset
Extended 100E VEE Range of -4.2V to -5.46V
Internal 751<.0 Input Pulldown Resistors
The MC 1OE/l OOE2l2 is a scannable registered ECl driver typically used as a
fan-out memory address driver for ECl cache driving. In a VlSI array based CPU
design, use of the E2l2 allows the user to conserve array output cell functionality and
also output pins.
The input shift register is designed with control logic which greatly facilitates its use
in boundary scan applications.

3-BIT SCANNABLE
REGISTERED
ADDRESS DRIVER

PINOUT: 28-LEAD PLCC (TOP VIEW)
SHIFT MR
25

NC S·OUT VCCO Q2b

Q2a

LOGIC SYMBOL

lOAD

Q2b

ClK

Q2a

VCC

VEE

Qlb

Q1a

Qlb

,------S·OUT

Q2b
Q2a
D2

Qla

S·IN
10
NC VCCO QOa

QOb

QOa

Qlb
Qla

COb VCCO

PIN NAMES
PIN

FUNCTION

00-02
S-IN

Scan Input

lOAD
SHIFT
ClK
MR
S-OUT

QOb
QOa

Data Inputs
DO

lOAD/HOLD Control
Scan Control
Clock
Reset

O[O:2]a, O[O:2]b

Scan Output
True Outputs

O[O:2]a, O[O:2]b

Inverting Outputs

S·IN
LOAD
SHIFT
ClK
MR

ECLinPS

3-87

QOa
QOb

MC10E212 MC100E212
DC Characteristics:

VEE

= VEE(min) to VEE(max);

Vee

= Veco = GND
25°C

O°C

Symbol

Characteristic

min

typ

max

min

150

I'H

Input HIGH-Current

lEE

Power Supply Current

tpHL

min

typ

150

max

Unit

150

J.LA

100E

110

VEE

= VEE(min) to VEdmax);

Characteristic

Vcc

= Vcco = GND
25°C

85°C

min

typ

max' min

typ

max

min

typ

max

575

800

1025

575

800

1025

575

800

1025

575

800

1025

575

800

1025

575

800

1025

CLKto S-OUT

575

800

1025

575

800

1025

575

800

1025

175

SHIFT
-LOAD

150

-50

150

-50

150

-50

225

150

50
-50

225

S-IN

50
-50

150

50
-50

250

25
100

Propagation Delay to Output
CLK

SHIFT

300

100

300

100

300

LOAD

225

S-IN

300

100

300

100

300

100

600

350

600

350

600

350

Reset Recovery

tAR

Condition

Hold Time

Unit
ps

Setup Time

Condition

mA
80

O°C

tpLH

85°C

max

10E

AC Characteristics:

Symbol

typ

tSKEW

Within-Device Skew

100

tSKEW

Within-Gate Skew

Rise/Fall Times

20 - 80%

275

425

650

275

425

650

275

425

650

1. Within-device skew IS defined as Identical tranSitions on similar paths through a device.
2. Within-gate skew is defined as the difference in delays between various outputs of a gate when driven from the same input.

FUNCTION TABLE
LOAD

SHIFT

MODE

Load

Hold

X
X

Shift

Reset

ECLinPS

3-88

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

•
•
•
•
•
•

MC10E241
MC100E241

SHIFT overrides HOLD/lOAD Control
1000 ps Max. ClK to Q
Asynchronous Master Reset
Pin-Compatible with E141
Extended 100E VEE Range of - 4.2 V to - 5.46 V
75 kO Input Pulldown Resistors

The MC10E/l00E241 is an 8-bit shiftable register. Unlike a standard universal
shift register such as the E141, the E241 features internal data feedback organized
so that the SHIFT control overrides the HOLD/lOAD control. This enables the normal operations of HOLD and lOAD to be toggled with a single control line without
the need for external gating. It also enables switching to scan mode with the single
SHIFT control line.
The eight inputs 00-07 accept parallel input data, while S-IN accepts serial input
data when in shift mode. Data is accepted a set-up time before the positive-going
edge of ClK; shifting is also accomplished on the positive clock edge. A HIGH on
the Master Reset pin (MR) asynchronously resets all the registers to zero.

8-BIT
SCANNABLE REGISTER

PINOUT: 28-lEAD PLCC (TOP VIEW)
SElO

Veeo

LOGIC SYMBOL

07
S-IN

---;::::;:=1~---==~

SEll

00---1
05

Vee

VEE

S·IN

Veco

(J.t

04 VCCO

02
HOLD/LOAD - _ _-'
SHIFT _ _ _ _ _ _....J

PIN NAMES
Pin
00-0 7
S-IN
SElO
SEll
ClK
MR

00-0 7

ClK - -_ _ _ _ _ _---1

Function

MR---------~

Parallel Data Inputs
Serial Data Input
SHIFT Control
HOLD/LOAD Control
Clock
Master Reset
Data Outputs

ECLinPS

3-89

MC10E241, MC100E241
DC Characteristics:

..
,.
VEE =V EE(min) to VEE(max); Vee

=Vceo = GND

O°C

Symbol

min

Characteristic

liH .

Input HIGH Currsnt

lEE

Power Supply Current

max

min

tpLH
tpHL

Unit

150

IlA

125

150

100E

125

150

125

150

144.

173

VEE

=VEE(min) to VEE(max);

Characteristic

min

typ

Max. Shift Frequency

700

900

Vee

=Vceo = GND
25'C

Clk

625

750

600

725

175

max

min

typ

700

900

975

625

750

975

600

725

175

85'C

max

min

typ

max

700

900

975

625

750

975

600

725

975

175

SELO (SHIFT)

350

200

350

200

350

200

SEL 1 (HOLD/LOAD)

400

250

400

250

400

S-IN

125

-100

125

-100

125

250
;100

200

-25

200

-25

200

-25

Hold Time

ps
100

-200

100

-200

100

-200

SEL 1 (HOLD/LOAD)

-250

S-IN

300

100

300

100

300

100

900

600

900

600

900

600

Clk, MR

ps
ps

400

Within-Device Skew

400
60

ps
ps

Rise / Fall Times
20 - 800;:0

Condition

Setup Time

Minimum Pulse Width

Unit
MHz

Propagation Delay to Output

tpw

Condition

mA
150

Reset Recovery Time

max

125

tRR

tr
tf

typ

150

D
SELO (SHIFT)

tSKEW

min

125

max
150

150

O°C

fSHIFT

typ

10E

AC Characteristics:

Symbol

85'C

25'C

typ

300

525

800

300

525

800

1. Within-device skew IS defined as Identical transitions on similar paths through a device

ECLinPS

3-90

300

525

800

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

•
•
•
•
•
•

MC10E256
MC100E256

950 ps Max. D to Output
850 ps Max. LEN to Output
Split Select
Differential Outputs
Extended 100E VEE Range of - 4.2 V to - 5.46 V
75 kD Input Pulldown Resistors

The Me1 OE/1 00E256 contains three 4: 1 multiplexers followed by transparent
latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is
controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.

LOGIC SYMBOL

PINOUT: 28-LEAD PLCC (TOP VIEW)
Dlb

Dla

D2d

D2e

D2b

D2a

Veeo

DOa
DOb

SELlA

DOe

SELlB

DOd
SEL2

Vee

VEE

LEN

Veeo

Ole

Dla
Dlb

Dle
Old

Old

DOa

DOb

DOe

DOd

Veeo

00
D2a

FUNCTION TABLE
Pin

State

H
H
H

SEL2
SELlA
SEL1B

D2b

Operation
Output cld Data
Input d Data
Input b Data

D2e
D2d

PIN NAMES
Pin
DOx-D2x
SEL lA. SEL 1B
SEL2
LEN
MR
00, 00-0 2, 02

3-BIT
4: 1 MUX-LATCH

SEllA

Function

SELlB

Data Inputs
First-stage Select Inputs
Second-stage Select Input
Latch Enable
Master Reset
Data Outputs

SEL2
LEN

ECLinPS
3-91

MC10E256, MC100E256
DC Characteristics:

VEE = VEE(min) to VEE(max); Vee = Veeo= GND
DoC

Symbol

Characteristic

IIH

Input HIGH Current

lEE

Power Supply Cu'rrent
10E
100E

r---

ACCharacteristics:

min

typ

25°C
max

min

150

tpLH
tpHL

typ
,

max

Unit

150

IlA

Condition

mA
69
69

83
83

69
69

83
83

69
79

83
96

25°C

85°C

Characteristic

min

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
D
SEL1
SEL2
LEN
MR

400
550
450
350
350

600
775

900
1050

400
550

600
775

900
1050

400
550

600
775

900
1050

650
500
600

900
800
825

450
350
350

650
500
600

900
800
825

450
350
350

650
500
600

900
800
825

400

275

400

275

400

275

600
500

300
250

600
500

300
250

600
500

300
250

300
100
200

-275

-300
-250

300
100
200

-300
-250

300
100
200

-275
-300
-250

600

700

600

700

600

Setup Time
D
SEL1
SEL2
Hold Time
D

Condition

Reset Recovery Time

700

tpw

Minimum Pulse Width
MR

400

ps
ps

Within-Device Skew
Rise I Fall Times
20-80%

Unit
ps

tRR

t,
tf

min

VEE = VEE(min) to VEE(max); Vee = Veeo = GND

SEL1
SEL2

tSKEW

85°C
max
150

DoC
Symbol

typ

400

400
50

ps
ps

275

475

700

275

475

700

1. Within-device skew is defined as identical transitions on similar paths through a device

ECLinPS
3-92

275

475

700

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

•
•
•
•
•
•
•
•
•

MC10E336
MC100E336

25 n Cutoff Bus Outputs
50 n Receiver Outputs
Transmit and Receive Registers
1500 ps Max. Clock to Bus
1000 ps Max. Clock to 0
Bus Outputs Feature Internal Edge Slow-Down Capacitors
Additional Package Ground Pins
Extended 100E VEE Range of - 4.2 V to - 5.46 V
75 kn Input Pulldown Resistors

3-BIT REGISTERED
BUS TRANSCEIVER

The MC10E/100E336 contains three bus transceivers with both transmit and
receive registers. The bus outputs (BUSD-BUS2) are specified for driving a 25 n
bus; the receive outputs (00-02) are specified for 50 n. The bus outputs feature a
normal HIGH level (VOH) and a cutoff lOW level - when lOW, the outputs go to
- 2.0 V and the output emitter-follower is "off," presenting a high impedance to
the bus. The bus outputs also feature edge slow-down capacitors.
The Transmit Enable pins (TEN) control whether current data is held in the transmit register, or new data is loaded from the AlB inputs. A lOW on both of the Bus
Enable inputs (BUSEN), when clocked through the register, disables the bus outputs to - 2.0 V.
The receiver section clocks bus data into the receive registers, after gating with
the Receive Enable (RXEN) input.
All registers are clocked by a positive transition of ClK1 or ClK2 (or both).
Additional leadframe grounding is provided through the Ground pins (GND)
which should be connected to 0 V. The GND pins are not electrically connected to
the chip.
LOGIC SYMBOL
PINOUT: 28-LEAD PLCC (TOP VIEW)
TEN2 TEN1

VCCO

Ao
BO

23
BUSEN1

GND

BUSEN2

BUS2
VCC
01

VEE

ClK1

VCCO

ClK2

BUS1

BUS2

GND
10
BO

VCCO BUSO GND

11
00

TEN1
TEN2
RXEN

D-----!--t----'

BUSEN1 D---,...,[
BUSEN2 D---d.--1
ClK1
ClK2

ECLinPS

3-93

MC10E336, MC100E336
DC Characteristics:

VEE = V EE(min) to VEE(max); Vee = Vceo = GND
25°C

O°C
Symbol
VeuT
IIH

Characteristic

min

'Cut-off Output Voltage

-2.10

typ

max

min

typ

-2.03 -2.10

Input HIGH Current
RXEN
All Other Inputs

85°C
max

min

typ

-2.03 -2.10

max

Unit

-2.03

V
I1A

225
150

Power Supply Current
10E
100E
'measured with VTT = -2.1 OV

225
150

225
150
mA

lEE

ACCharacteristics:

125
125

150
150

125
125

tpLH
tpHL

tpw

t,
tf

150
150

125
144

150
173

VEE = VEE(min) to VEE(max); Vee = Veca= GND
O°C

Symbol

Condition

min

typ

max

min

Propagation Delay to Output
ClktoO
ClktoBUS

500
825

700 100
1250 1800

Setup Time
BUS, RXEN
BUSEN
A, B Data
TEN

150
100
300
450

Hold Time
BUS, RXEN
BUSEN
A, BData
TEN

450
500
350
200

Minimum Pulse Width
Clk

400

Rise I Fall Times
20-80%(On)
20 - 80% ( BUSn Rise)
20 - 80% ( BUSn Fall )

85°C

25°C

Characteristic

typ

max

min

typ

max

500
825

700 1000
1250 1800

500
825

700 1000
1250 1800

-150
-200
-50
150

150
100
300
450

-150
-200
-50
150

150
100
300
450

-150
-200
-50
150

150
200
50
-150

450
500
350
200

150
200
50
-150

450
500
350
200

150
200
50
-150

Unit
ps

ps
400

400
ps

300
500
300

450
800
500

700
1000
800

300
500
300

ECLinPS
3-94

450
800
500

700
1000
800

300
500
300

450
800
500

700
1000
800

Condition

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

MC10E337
MC100E337

Advance Information
•
•
•
•
•
•
•
•
•
•
•
•

Scannable Version of E336
25 0 Cutoff Bus Outputs
50 0 Receiver Outputs
Scannable Registers
Sync. and Async. Bus Enables
Non-Inverting Data Path
1500 ps Max. Clock to Bus (Data Transmit)
1000 ps Max. Clock to 0 (Data Receive)
Bus Outputs Feature Internal Edge Slow-Down Capacitors
Additional Package Ground Pins
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kO Input Pulldown Resistors

3-BIT
SCANNABLE
REGISTERED
BUS TRANSCEIVER

The MC10EI100E337 is a 3-bit registered bus transceiver with scan. The bus outputs (BUSO-BUS2) are specified for driving a 25 0 bus; the receive outputs
(00-02) are specified for 50 O. The bus outputs feature a normal HIGH level (VOH)
and a cutoff lOW level- when lOW, the outputs go to - 2.0 V and the output
emitter-follower is "off," presenting a high impedance to the bus. The bus outputs
also feature edge slow-down capacitors.
Both drive and receive sides feature the same logic, including a loopback path to
hold data. The HOLD/lOAD function is controlled by Transmit Enable (TEN) and
Receive Enable (REN) on the. transmit and receive sides respectively, with a HIGH
selecting lOAD. Note that the implementation of the E337 Receive Enable differs
from that of the E336.
A synchronous bus enable (SBUSEN) is provided for normal, non-scan operation. The asynchronous bus disable (ABUSDIS) disables the bus immediately for
scan mode.
The SYNCEi'ii input is provided for flexibility when re-enabling the bus after disabling with ABUSDIS, allowing either synchronous or asynchronous re-enabling.
An alternative use is asynchronous-only operation with ABUSDIS, in which case
SYNCEN is tied lOW, or left open. SYNCEN is implemented as an overriding SET
control (active-lOW) to the enable flip-flop.
Scan mode is selected by a HIGH at the SCAN input. Scan input data is shifted in
through S_IN, and output data appears at the 02 output.
All registers are clocked on the positive transition of ClK. Additional lead-frame
grounding is provided through the Ground pins (GND) which should be connected
to 0 V. The GND pins are not electrically connected to the chip.
PIN NAMES
Pin
Ao--A2
Bo-B2
S-IN
TEN,REN
SCAN
ABUSDIS
SBUSEN
SYNCEN
ClK
BUSO-BUS2
00-02

Function
Data Inputs A
Data Inputs B
Serial (Scan) Data Input
HOLD/lOAD Controls
Scan Control
Asynchronous Bus Disable
Synchronous Bus Enable
Synchronous Enable Control
Clock
25 n Cutoff Bus Outputs
Receive Data Outputs (02 serves as
SCAN_OUT in scan mode)

This document contains information on a new product. Specifications and information herein are subject to change without notice.

ECLinPS
3-95

MC10E337, MC100E337
PINOUt: 28-LEAD PLCC (TOP VIEW)
SBUSEN SYNCEN BO
25

AO ABUSDIS VCCO

00
19
GND

SCAN
S-IN

BUSO

TEN

VCC

VEE

01
VCCO
BUS1

GND

VCCO BUS2 GND

LOGIC SYMBOL

_--------aBUS2

A2
B2

,...4--1----0 BUS1
01

A1
B1

_-+--+----CI BUSO
00

AO
BO

S_INo---+...J
TEN
RENo----+--If---H-------l
SCANo-----J'---+---l+------.....J
ABUSDIS o - - - - - - I - - . J I
SBUSEN 0 - - - - - - /
SYNCEN 0 - - - - 4
CLKc>------l------------...J

ECLinPS
3-96

MC10E337, MC100E337
DC Characteristics:

VEE

= VEE(min) to VEE(max); Vee = Veco = GND
25°C

O°C

Symbol
VeuT
IIH

lEE

Characteristic

min

'Cut-off Output Voltage

-2.10

typ

max

min

VEE

Characteristic

rnA
145

174

145

174

145

174

145

174

145

174

167

200

min

typ

25°C

max

min

typ

85°C

max

min

typ

max

Unit
ps

ClktoQ

450

1000

450

1000

450

Clk to BUS

800

1800

800

1800

800

1800

ABUSDIS

500

1500

500

1500

500

1500

800

1800

800

1800

800

1800

1000

Setup Time

ps
350

350

SBUSEN

100

Data, S-IN

400

TEN,REN,SCAN

550

BUS

350

SBUSEN

500

Data, S-IN

350

TEN,REN,SCAN

200

400

Hold Time

Minimum Pulse Width
Clk

Propagation Delay to Output

BUS

-2.03

Condition

= VEE(min) to VEE(max); Vee = Veea = GND

-SYNCEN

tpw

Unit

150

O°C

max

= -2.10V

AC Characteristics:

typ

![A
150

100E

tpLH

min

Power Supply Current

"measured with VTT

tpHL

85°C

max

-2.03 -2.10

Input HIGH Current
All Other Inputs

10E

Symbol

typ

Rise I Fall Times

20-80%(Qn)

300

800

20 - 80% ( BUSn Rise)

500

1000

20 - 80% ( BUSn Fall )

300

800

300

800

500

800
1000

500

1000

300

800

300

800

EClinPS
3-97

Condition

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

MC10E404
MC100E404

Differential D and 0
700 ps Max. Propagation Delay
High Frequency Outputs
Extended lOOE VEE Range of -4.2V to -S.46V
Internal7SkO Input Pulldown Resistors
The MC 1OE404/1 00E404 is a 4-bit differential AND/NAND device. The differential
. operation of the device makes it ideal for pulse shaping applications where duty cycle
skew is critical. Special design techniques were incorporated to minimize the skew
between the upper and lower level gate inputs.
Because a negative 2-input NAND function is equivalent to a 2-input OR function.
the differential inputs and outputs of the device also allow for its use as a fully
differential 2 input OR/NOR function.
The output RISE/FALL times of this device are significantly faster than most other
standard ECLinPS devices resulting in an increased bandwidth.
The differential inputs have clamp structures which will force the Q output of a gate
in an open input condition to go to a LOW state. Thus inputs of unused gates can be
left open and will not affect the operation of the rest of the device.

LOGIC SYMBOL

PINOUT: 28-LEAD PLCC (TOP VIEW)
D3A

D3A

D3B

D3B veea 03

D
o a G 00
DOa

D2B

D2A

vee

VEE

D2A

D1B

DOb
DOb

D
D1a
1 a G 01
D1b
D1b

00
7

D1A

D1A DOB

DOB

DOA

veea

D2aG02
D2a
D2b
02
D2b

PIN NAMES
PIN

FUNCTION

Differential Data Inputs

D[0:4]. D[0:4]

D
3aG03
D3a

Differential Data Outputs

0[0:4]. Q[0:4]

D3b
D3b

FUNCTION TABLE
Da

L
L
H

L
H
L
H

L
L
L
H

QUAD
DIFFERENTIAL
AND/NAND

Da
L
L
H
H

Db
L
H
L
H

Q
L
H
H
H

ECLinPS

3-98

MC10E404, MC100E404

DC Characteristics:

VEE

=VEE(min) to VEE(max);

=Vcco = GND

Vcc

25°C

O°C

Symbol

Characteristic

min

I'H

Input HIGH Current

lEE

Power Supply Current

I---

Vpp(DC)
VCMR

typ

max

min

typ

150

85°C

max

min

typ

150

max

Unit

150

10E

106

127

106

127

106

127

100E

106

127

106

127

122

146

Input Sensitivity

Common Mode Range

Condition

-1.5

1. Dlfferenlial Input voltage required to obtain a full ECl sWing on the outputs.
2. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the
input signals are within the VCMR range and the input swing is greater than V PP MIN and < 1V.

AC Characteristics:

VEE

=V EE(min) to VEE(max);

V cc

=V cco = GND
25°C

O°C

Symbol
tplH
tpHl

tSKEW
Vpp(AC)
tr
tf

Characteristic

85°C

min

typ

max

min

typ

max

min

typ

max

350

475

650

350

475

650

350

475

650
700

Propagation Delay to Output
Da(Diff)

300

475

700

300

475

700

300

475

Db (Dill)

375

500

675

375

500

675

375

500

675

Db (SE)

325

500

725

325

500

725

325

500

725

Within-Device Skew

150

Rise / Fall Time
20 - 80%

Condition

Da (SE)

Minimum Input Swing

Unit

150

400

150

400

1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Minimum input swing for which AC parameters are guaranteed.

ECLinPS

3-99

150

400

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

TECHNICAL DATA

MC10E416
MC100E416

Differential D and Q; V BB available
600 ps Max. Propagation Delay
High Frequency Outputs
2 Stages of Gain
Extended 1ODE VEE Range of -4.2V to -5.46V
Internal 75kn Input Pulldown Resistors

QUINT
DIFFERENTIAL
LINE RECEIVER

The MC 1OE416/1 00E416 is a 5-bit differential line receiving device. The 2.0 GHz
of bandwidth provided by the high frequency outputs makes the device ideal for
buffering of very high speed oscillators.
A V BB pin is available to AC couple an input signal to the device. More information
on AC coupling can be found in the design handbook section of this data book.
The design incorporates two stages of gain internal to the device making it an
excellent choice for use in high bandwidth amplifier applications.

LOGIC SYMBOL
PINOUT: 28-LEAD PLCC (TOP VIEW)

veeo

veea

oo~oo
DO

"~Q'

vee

VEE

VBB

~~~

veea

01
5

veea

D3~OO

FUNCTION

D[0:4). D[0:4)

"~~

PIN NAMES
PIN

Differential Data Inputs

Q[0:4). Q[0:4)

Differential Data Outputs

VBB a

ECLinPS
3-100

MC10E416, MC100E416

DC Characteristics:

VEE

=VEE(min) to VEE(max);

=Veeo = GND

Vee

25°C

O°C
Symbol
Vee

r---

Characteristic

min

Output Reference Voltage
10E
100E

I'H

Input HIGH Current

lEE

Power Supply Current
10E

r---

VeMR

Input Sensitivity

max

typ

85°C
max

min

typ

max

Unit

Condition

V
-1.19

-1.25 -1.31
-1.26 -1.38

150

-1.26

150

~
mA

135

162

135

162

135

Common Mode Range

min

-1.27 -1.35
-1.26 -1.38

-1.38
-1.38

100E
Vpp(DC)

typ

162
162

-1.5

162
186

-1.5

135
155

-1.5

1. Differential input voltage required to obtain a full ECl swing on the outputs.
2. VCMA is referenced to the most positive side of the differential input signal. Normal operation is obtained when the
input signal are within the VCMA range and the input swing is greater than V PP MIN and < 1V

AC Characteristics:

VEE

=VEE(min) to VEE(max);

Vee

=Vceo = GND

O°C
Symbol
tplH
tpHl

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
D(Diff)

250

350
350

500
550

250

350
350

500
550

250

350

500

200

350

550

tSKEW

Within-Device Skew

tSKEW

Duty Cycle Skew

Minimum Input Swing

Unit

200

±10

150

Rise / Fall Time
20 - 80%

Condition

tplH - tpHl

85°C

min

D(SE)

Vpp(AC)

25°C

Characteristic

100

200

350

100

200

350

100

200

350

1. Within-device skew is defined as identical transitions on similar paths through a device
2. Duty cycle skew defined only for differential operation when the delays are measured from the cross point of
the inputs to the cross point of the outputs.
3. Minimum input swing for which AC parameters are guaranteed

ECLinPS
3-101

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

j;C10E431
~100E431

Edge-Triggered Asynchronous Set and Reset
Differential D. CLK and Q; VBB Reference Available
1100 MHz Min. Toggle Frequency
Extended 1OOE VEE Range of -4.2V to -5.46V
The MC 1OE/1 00E431 is a 3-bit flip-flop with differential clock. data input and data
output.
The asynchronous Set and Reset controls are edge-triggered rather than level
controlled. This allows the user to rapidly set or reset the flip-flop and then continue
clocking at the next clock edge. without the necessity of de-asserting the setlreset
signal (as would be the case with a level controlled setlreset).
The E431 is also designed with larger internal swings. an approach intended to
minimize the time spent crossing the threshold region and thus reduce the metastability
susceptibility window.

LOGIC SYMBOL

PINOUT: 28-LEAD PLCC (TOP VIEW)
VBB CLK2 C.LK2
25

3-BIT
DIFFERENTIAL
FLIP-FLOP

so
DO

DO
CLKO

CLKO

CLKO CLKO

vcca

01
CLK1

CLK1

PIN NAMES
PIN

FUNCTION

D[O:2]. D[O:2]
CLK[O:2]. CLK[O:2]
S[O:2]
R[O:2]
VBB
Q[O:2]. Q[O:2]

Differential Data Inputs

Differential Clock Inputs
Edge Triggered Set Inputs
Edge Triggered Reset Inputs
VBB Reference Output
Differential Data Outputs

02
CLK2

FUNCTION TABLE

CLK2

CLKn

L
H

Z
Z
L

L
L

L
H

Z
L

L
Z

L
H

X
X

R2
VBB ..

Z=Low to high transition

ECLinPS
3-102

MC1 OE431 , MC100E431
DC Characteristics:

VEE

=V EE(min) to VEdmax);

Vcc

= Vcco = GND

O'C

Symbol
V BB

Characteristic

min

85'C

25'C

max

min

typ

max

min

typ

max

Output Reference Voltage
-1.38

-1.27 -1.35

-1.25 -1.31

-1.19

100E

-1.38

-1.26 -1.38

-1.26

Input HIGH Current

lEE

Power Supply Current

150

Condition

!-LA
mA

10E

110

132

110

132

110

132

100E

110

132

110

132

127

152

Common Mode Range

Unit
V

10E

I'H

V CMR

typ

-1.5

1. VeMR IS referenced to the most positive side of the differential Input signal. Normal specified operation IS obtained
when the input signals are within the VeMR range and the input swing is greater than VPP MIN and < 1V.

AC Characteristics:

VEE = V EE(min) to V EE(max); V cc = V cco = GND
25'C

O'C

Symbol

Characteristic

min

f MAX

Max. Toggle Frequency

1100 1400

tpLH

Propagation Delay to Output

tpHL

ClK(Diff)

Vpp(AC)
t,
tf

typ

85'C

max

1100 1400

min

typ

max

1100 1400

Unit

Condition

MHz

600

750

450

600

750

450

600

750

400

600

800

400

600

800

400

600

800

550

725

925

550

725

925

550

725

925

550

725

925

550

725

925

550

725

925

200

1000

700

1000

700

1000

700

1000

700

1000

700

1000

700

200

Setup Time

Hold Time

Minimum Pulse Width

ps
400

ClK

tSKEW

min

ClK (SE)

D
tpw

max

ps
450

typ

Within-Device Skew
Minimum Input Swing

400

400
50

150

Rise/Fall Times

20 - 80%

275

450

650

275

450

650

275

450

650

1. These setup times define the minimum time the ClK or SET/RESET Input must wall after the assertion of the
RESET/SET input to assure the proper operation of the flip-flop.
2. Within-device skew is defined as identical transitions on similar paths through a device.
3. Minimum input swing for which AC parameters are guaranteed.

ECLinPS

3·103

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..

-·----·---- - - - :G

TECHNICAL DATA

Product Preview

MC10E445
MC100E445

On Chip Clock +4 and +8
2.5Gb/s Data Rate Capability
Differential Clock and Serial Inputs
VBB Output for Single-ended Input Applications
Asynchronous Data Synchronization
Mode Select to Expand to 8 Bits
Internal 75k!:! Input Pulldown Resistors
Extended 1OOE VEE Range of -4.2V to -5.46V

_ ... __

()

SINA SINA

(J)

a: MODE NC VCCO

-----

PIN NAMES

i;;

(J)

4-BIT
SERIAL/PARALLEL
CONVERTER

The MC1 OE/1 00E445 is an integrated 4-bit serial to parallel data converter. The
device is designed to operate for NRZ data rates of up to 2.5Gb/s. The Chip generates
a divide by four and a _divide by 8 clock for both 4-bit conversion and a two chip 8-bit
conversion function. The conversion sequence was chosen to convert the first serial
bit to QO, the second to Q1 etc.
Two selectable serial inputs provide a loopback capability for testing purposes
when the device is used in conjunction with the E446 parallel to serial converter.
The start bit for conversion can be moved using the SYNC input. A single pulse
applied asynchronously for at least two cycles of the input clock signal shifts the start
bit for conversion by one bit. For each additional shift required, an additional pulse
must be supplied.
The MODE input is used to select the conversion mode of the device. With the
MODE input LOW, or open, the device will function as a 4-bit converter. When the
MODE input is driven HIGH the data at the output will change on every eighth clock
cycle thus allowing for an 8-bit conversion scheme using two E445's.

PINOUT: 28-LEAD PLCC (TOP VIEW)

._"

FUNCTION
--

SINA, SINA
SINS, SINS
SEL
SOUT, SOUT

19
lSJ SOUT

vee

SOUT

00-03_
CLK,CLK
ClI4, ClI4
ClI8, ClI8
MODE
SYNCH

veeo

Dill. Serial Data Input A
Dill. Serial Data Input S
Serial Input Select Pin
Dill. Serial Data Output
Parallel Data Outputs
Dill. Clock Inputs
Ditt. +4 Clock Output
Ditt. +8 Clock Output
Conversion Mode 4-biV8-bit
Conversion Synchronizing Input

02
10

CUB CUB veeo

eU4

FUNCTION TABLES

eU4 veco 03

MODE

Conversion

L
H

4 Sit
8 Sit

SEL
H
L

Serial Input
A
S

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product
without notice.

ECLinPS

3-104

MOTOROLA

SEMICONDUCTOR - - - - - - - - - - - -

TECHNICAL DATA

MC10E446
MC100E446

Product Preview
On Chip Clock +4 and +8
2.5Gb/s Data Rate Capability
Differential Clock and Serial Inputs
VBB Output for Single-ended Input Applications
Mode Select to Expand to 8 Bits
Internal 75kl:2 Input Pulldown Resistors
Extended 1ODE VEE Range of -4.2V to -5.46V

4-BIT
PARALLEL/SERIAL
CONVERTER

The MC1 OE/1 00E446 is an integrated 4-bit parallel to serial data converter. The
device is designed to operate for NRZ data rates of up to 2.5Gb/s. The chip generates
a divide by four and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit
conversion function. The conversion sequence was chosen to convert the parallel data
into a serial stream from bit DO to 03. A serial input is provided to cascade two E446
devices for 8 bit conversion applications.
The SYNC input can be used to reset the internal clock conversion unit to select
the start of the conversion process.
The MODE input is used to select the conversion mode of the device. With the
MODE input LOW, or open, the device will function as a 4-bit converter. With the
MODE input driven HIGH data at the serial input are read at one half of the +8 clock
cycle thus allowing for an 8 bit conversion using two E446's.

PIN NAMES

PINOUT: 28-LEAD PLCC (TOP VIEW)
DO

D3 MODE NC

ClK

VBB

VCC

VEE

SOUT

SIN

SOUT

SIN

VCCO
NC
10
VCCO CUB

CUB

vcco CU4

FUNCTION

SIN
DO-D3 - SOUT, SOUT
ClK,ClK

Diff. Serial Data Input
Parallel Data Input
Diff. Serial Data Output
Dill. Clock Input
Dill. 4 Clock Output
Dill. S Clock Output
Conversion Mode, 4 billS bit
Conversion Synchronizing Input

CU4, CU4
CUS, CUS
MODE
SYNC

FUNCTION TABLES

MODE

Conversion

l
H

4 Bit
S Bit

CU4 VCCO

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product
without notice.

ECLinPS
3-105

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

•
•
•
•
•
•

MC10E451
MC100E451

Differential Inputs: Data and Clock
Vss Output
1100 MHz Min. Toggle Frequency
Asynchronous Master Reset
Extended 100E VEE Range of -4.2 V to -5.46 V
75 kO Input Pulldown Resistors

The MC10E/100E451 contains six D-type flip-flops with single-ended outputs and
differential data inputs. The common clock input is also differential. The registers
are triggered by a positive transition of the positive clock (ClK) input.
A HIGH on the Master Reset (MR) input resets all Q outputs to lOW. The VSS
output is intended for use as a reference voltage for single-ended reception of ECl
signals to that device only. When using for this purpose, it is recommended that
VSS is decoupled to VCC via a 0.Q1 JLf capacitor.
PINOUT: 28-lEAD PlCC (TOP VIEW)

liS

6-BIT D REGISTER,
DIFF. DATA & CLOCK

lOGIC SYMBOL

Veeo

DO
00

CLK
Vee

D,
0,

CLK

VCC

VEE

VCCO

D2
02

ii1

"
Vcca

D4
04

PIN NAMES
Pin
00-0 5
Do-D5
CLK
CLK
MR

Vee
00-0 5

Function

+Data Input
-Data Input
+ Clock Input
- Clock Input
Master Reset Input
Vee Output
Data Outputs

CLK
CLK

MR
Vee

ECLinPS
3-106

MC1 OE451 , MC100E451
DC Characteristics:

VEE = V EE(min) to V EE(max); V cc = V cco = GND
25°C

O°C
Symbol
VBB

Characteristic

max

min

typ

85°C
max

min

typ

max

-1.38

-1.27 -1.35

-1.25 -1.31

-1.19

100E

-1.38

-1.26 -1.38

-1.26

lEE

Power Supply Current

150

Condition

IlA
rnA

10E

101

100E

101

116

Common Mode Range

Unit
V

10E

Input HIGH Current

VCMR

typ

Output Reference Voltage

I'H

min

-2.0

-0.4

-2.0

-0.4

-2.0

-0.4

1. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the "HIGH" input is
within the VCMR range and the input swing is greater than VPPMIN and < 1V.

AC Characteristics:

VEE = V EE(min) to V EE(max); V cc = V cco = GND
O°C

Symbol

Characteristic

min

f MAX

Max. Toggle Frequency

1100 1400

tplH

Propagation Delay to Output

tpHl

typ

85°C
max

1100 1400

min

typ

max

1100 1400

800

475

650

ClK (SE)

425

650

850

425

600

850

425

150

-100

150

250

100

250

800

475

650

800

650

850

425

650

850

600

850

425

600

850

-100

150

-100

100

250

100

Hold Time

Minimum Input Swing

150

tRR

Reset Recovery Time

750

tpw

Minimum Pulse Width

159

150
600

750

600

750

mV
600

ps
ps

400

Within-Device Skew

400

400
100

100

Rise I Fall Times
20 - 80%

Condition

MHz

Setup Time

ClK, MR

Unit

ps
650

Vpp(AC)

t,
tf

min

475

tSKEW

25°C
max

ClK(Diff)

D
th

typ

ps
275

450

800

275

450

800

1. Minimum input voltage for which AC parameters are guaranteed
2. Within-device skew is defined as identical transitions on similar paths through a device

ECLinPS

3-107

275

450

800

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

MC10E452
MC100E452

Differential 0, ClK and 0; VBB Reference Available
1100 MHz Min. Toggle Frequency
Asynchronous Master Reset
Extended lODE VEE Range of -4.2V to -5.46V
The MC 1DEll 00E452 is a 5-bit differential register with differential data ( inputs
and outputs) and clock. The registers are triggered by a positive transition of the
positive clock (ClK) input. A high on the Master Reset (MR) asynchronously resets all
registers so that the 0 outputs go lOW.
The differential input structures are clamped so that the inputs of unused registers
can be left ope.!! without ~tting the bias network of the device. The clamping action
will assert the 0 and the ClK sides of the inputs. Because of the edge triggered flip
flop nature of the device simultaneously opening both the clock and data inputs will
result in an output which reaches an unidentified but valid state.
The fully differential design of the device makes it ideal for very high frequency
applications where a registered data path is necessary.

5-81T
DIFFERENTIAL
REGISTER

LOGIC SYMBOL

PINOUT: 28-LEAD PLCC (TOP VIEW)
0 0 - - - ' ....
03

i54

vcco

50--",-,/

ClK

vce

VEE

VBB

50 vcco

Qli

PIN NAMES
PIN

01--++-f'

Di--++ 1.0 GHz bandwidth to
meet the needs of the most demanding sYSitem clock.
Both separate selects and a common select are provided to make the device well
suited for both data path and random logic applications.

LOGIC SYMBOL

PINOUT: 28-LEAD PLCC (TOP VIEW)
SEL2 D2A
25

D2A VBB
23

D2B
21

D2B eOMSEL
20

TRIPLE
DIFFERENTIAL
2:1 MULTIPLEXER

DOa

DOb

SELl

D1A

vee

VEE

VBB

D1B

Dla

D1B

Dlb

SELO DOA

DOA VBB

9
DOB

DOb
SELO

Dla

Dlb

SEL1

DOB veeo

FUNCTION TABLE
D2a

SEL

Data

H
L

D2a

D2b
D2b
SEL2-J....:>-....

PIN NAMES
PIN

FUNCTION

Dn[0:2], Dn[0:2]
SEL
COMSEL
VBB 0[0:2], 0[0:2]

eOMSEL

Differential Data Inputs
Individual Select Input
Common Select Input
VBB Reference Output
Differential Data Outputs

ECLinPS
3-110

MC1 OE457, MC100E457

DC Characteristics:

VEE = VEE(min) to VEE(max);

Vcc = Vcco= GND

O°C
Symbol
V BB

Characteristic

25°C
max

min

typ

85°C
max

min

typ

max

-1.38

-1.27 -1.35

-1.25 -1.31

-1.19

100E

-1.38

-1.26 -1.38

-1.26

lEE

Power Supply Current

Unit

Condition

10E

Input HIGH Current

VCMR

typ

Output Reference Voltage

IIH

Vpp(DC)

min

150

f!A
mA

10E

110

100E

110

106

127

Input Sensitivity

Common Mode Range

-1.5

1. Differential input voltage required to obtain a full ECl swing on the outputs.
2. VeMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the
input signal are within the VCMR range and the input swing is greater than VPP MIN and < 1V.

AC Characteristics:

VEE = V EE(min) to VEE(max);

V cc = V cco = GND

O°C
Symbo
tpLH
tpHL

Characteristic

max

min

typ

max

min

typ

max

D(Diff)

375

475

650

375

475

650

375

475

650

Propagation Delay to Output
D

325

475

700

325

475

700

325

475

700

350

500

725

350

500

725

350

500

725

COMSEL

375

525

750

375

525

750

375

525

750

tSKEW

Duty Cycle Skew
tpLH - tpHL
Minimum Input Swing

Unit

±10

150

Rise / Fall Time
20-80%

Condition

SEL

Within-Device Skew

tr
tf

85°C

typ

tSKEW

Vpp(AC)

25°C

min

150

275

450

150

275

450

150

275

1. Within-device skew is guaranteed for identical transitions on similar paths through a device
2. Duty cycle skew guarantee holds only for differential operation when the delays are measured from the
cross point of the inputs to the cross point of the outputs.
3. Minimum Input Swing for which AC parameters are guaranteed.

ECLinPS
3-111

450

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

Advance Information
•
•
•
•
•
•

MC10E1651

Typ. 3.0 dB Bandwidth> 1 GHz
Typ. V to Q Propagation Delay ps
Typ. Output Rise/Fall 300 ps
Common Mode Range - 2.0 V to + 3.0 V
Individual Latch Enables
Differential Outputs

DUAL ANALOG
COMPARATOR W. LATCH

The MC10E1651 is functionally and pin-for-pin compatible with the MC1651 in
the MECL III family, but is fabricated on Motorola's advanced MOSAIC III process.
The part has been designed with the goal of minimizing variations in propagation
delay versus the amount of input overdrive. The output voltage levels are compatible with 10KH (and 10E) standard logic devices.

PINOUT: 16-PIN CERAMIC DIP (TOP VIEW)

GND

Qii

LENb

Vlb

V2b

Vcc

VCC

VEE

LSUFFIX
CERAMIC PACKAGE
CASE 620

GND

LENa

V2a

Vla

LENb

-----{;>

VEE = -5.2V
VCC = H.OV

FUNCTION TABLE
LEN

V1, V2

H
H
L

Vl > V2
Vl < V2
X

10E1651 20-LEAD PLCC PINOUTS

H
L
Latched

Qb LENb NC

Vlb V2b

14
VCC

Qb
GND

NC
11

LENa

V2a Vla

This document contains information on a new product. Specifications and information are subject to change without notice.

ECLinPS

3-112

MC10E1651
ABSOLUTE MAXIMUM RATINGS:
Beyond which device life may be impaired
Symbol
VSUP

VPP

Characteristic

min

typ

max

Total Supply Voltage
IVEEI + IVCCI

12.0

Differential Input Voltage
IVl -V21

3.0

DC Characteristics:

Unit
V

VEE = -5.2 V ± 5%;

Vee = +5.0V ± 5%
O'C

Symbol

Characteristic

min

typ

25'C

max

min
-980

V OH

Ouput HIGH Voltage

-1020

-840

VOL

Output Low Voltage

-1950

-1630 -1950

typ

85'C

max

min

-810

typ

max

Unit

-920

-735

-1630 -1950

-1600

mV
IJA

Input Current (V1, V~

I'H

Input HIGH Current (LEN)

150

150
50
-55

3.0

Unit

Icc

Positive Supply Current

lEE

Negative Supply Current

-55

VCMR

Common Mode Range

AC Characteristics:

-2.0

3.0

-2.0

tplH
tpHl

tr
tf

-2.0

VEE = -5.2 V ± 5%; Vee = +5.0V ± 5%
25'C

O'C

Symbol

3.0

Characteristic

85'C

min

typ

max

min

typ

max

min

typ

max

VtoO

600

850

1150

600

850

1150

600

850

1150

LEN toO

500

750

950

500

750

950

500

750

950

200

300

700

200

300

700

200

300

700

Propagation Delay to Output

Rise / Fall Times
20 - 80%

Condition

Note: Contact factory for more complete data sheet

ECLinPS
3-113

Condition

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
TECHNICAL DATA

MC10E1652

Typ. 3.0 dB Bandwidth> 1.0GHz
Typ. V to Q Propagation Delay of 850 ps
Typ. Output Rise/Fall of 300 ps
Common Mode Range -2.0 V to +3.0 V
Individual Latch Enables
Differential Outputs
User Controlled Input Hysterisis

DUAL ANALOG

COMPARATOR
wI LATCH

The MC10E1652 is functionally compatible with the MC10E1651 and thus the
MC1651 in the MECL III family. The hysterisis control pin HYS allows the user to
define the amount of input hysterisis where as the MC1 OE1651 has a built in fixed level
of input hysterisis. The device comes in a 10E version only, thus the outputs are only
compatible with 10KH logic devices. The device is available in both a 16-pin DIP and a
20-pin PLCC surface mount package.

PINOUT: 20-LEAD PLCC (TOP VIEW)
Qb LENb Ne V1b

LOGIC DIAGRAM

V2b

V1a

V2a

Q
18

vee

GNO

HYS
11

LENa

HYS

VEE
vee

V1b
Q

V2b

Qa LENa Ne V2a V1a

LENb

PINOUT: 16-PIN CERAMIC DIP (TOP VIEW)
GND Qb

VEE = -5.2 V

Qb LENb V1b V2b vce HYS

vee = +5.0 V

GND

LENa V2a V1 a vec VEE

FUNCTION TABLE

ECLinPS
3-114

LEN

V1,V2

H
H

V1 > V2
V1 < V2

H
L

Latched

MC10E1652
ABSOLUTE MAXIMUM RATINGS:
Beyond which device life may be impaired
Symbol
VSUP

VPP

Characteristic

min

typ

Total Supply Voltage
IVEEI + Iveel

12.0

Differential Input Voltage
IV1 ·V21

3.0

DC Characteristics:

Unit

max

VEE =·5.2 V ± 5%; Vee

=+5.0V ± 5%
ooe

Symbol

Characteristic

min

typ

25°e
min

max

typ

85°C
max

min

V OH

Ouput HIGH Voltage

·1020

·840 ·980

·810 ·920

VOL

Output Low Voltage

·1950

·1630 ·1950

typ

max

Unit

·735

·1600 mV

Input Current (V1. V~
Input HIGH Current (LEN)

65
150

IJA

IIH
Icc
lEE

Positive Supply Current
Negative Supply Current

50
·55

3.0

Unit

VCMR

Common Mode Range

AC Characteristics:

·2.0

3.0

·2.0

tpLH
tpHL

t,
tf

·2.0

VEE = ·5.2 V ± 5%; Vee = +5.0V ± 5%
25°C

O°C
Symbol

3.0

Condition

85°C

Characteristic

min

typ

max

min

typ

max

min

typ

max

Propagation Delay to Output
VtoQ
LENtoQ

600
500

850
750

1150
950

600
500

850
750

1150
950

600
500

850
750

1150
950

Rise / Fall Times
20·80%

200

300

700

200

300

700

200

300

700

Note: Contact factory for more complete data sheet.

ECLinPS
3-115

Condition

ECLinPS
3-116

Design Guide

This section contains a design guide written exclusively with the ECUnPS product family in mind. The design
guide deals with system design aspects of using the family.
This section is not meant to be a replacement for the MECL
System Design Handbook but rather a supplement to the
information contained in it.

CONTENTS
System Basics ........................
Transmission Line Theory ...............
System Interconnect . ...................
Interfacing with ECLinPS ................
Package and Thermal Information . ........
Quality and Reliability ..................

ECLinPS
4-1

4-2
4-8
4-18
4-29
4-32
4-38

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
DESIGN GUIDE

System Basics

SECTION 1
System Basics

Although both the 10E and 1OOE devices can tolerate
variations in the VEE supply without any detrimental effects,
it is recommended that the VEE supply also have a dedicated
power plane. If this is not a feasible constraint care should be
taken sothatthe IRdrops of the VEE busdo notcreatl') a VEE
voltage outside of the specification range. To provide the
switching currents resulting from stray capacitances and
asymmetric loading, the VEE power supply in an ECl system .
nel;!ds to be bypassed. It is recommended that the VEE
supply be bypassed at each device with an RF quality .01 fJF
capacitor to ground. In addition the supply should also be
bypassed to ground with a 1J.lF -1 OJ.lF capacitor althe power
inputs to a board. If a separate output termination plane is
used the VEE supply will be of a static nature as the output
switching current will return to ground via the VTT supply,
thus the bypassing of every device may be on the conservative side. lithe design is going to include a liberal use of serial
or Thevenin equivalent termination schemes a properly
bypassed VEE plane is essential.

Power Supply Considerations
The following text gives a brief description of the requirements and recommendation for treatment of power
supplies in an ECLinPS system design. A more thorough
narration on the general subject of power supplies can be
found in the Motorola System Design Handbook.
Vee Supply
As with all previous ECl families the ECLinPS logic
family is designed to operate with negative power supplies,
in other words with Vee connected to ground. However
ECLinPS circuits will work fine with positive power supplies
as long as special care has been taken to ensure a stable,
quiet Vee supply. The output voltage levels for a positive
supply system can be determined by simply subtracting the
absolute value of the standard negative output levels from
the desired Vee'
To provide as small an AC impedance as possible, and
minimize power bus IR drops, the Vee supply should have
a dedicated power plane. By providing a full ground plane in
the system the deSigner ensures that the current return path
for the signal traveling down a transmission line does not
encounter any major obstructions. It is imperative that'the
noise and voltage drops be as small as possible on the Vec
plane as the internal switching references and output levels
are all derived off of the Vee power rail. Thus any perturbations on this rail could adversely affect the noise margins of
a system.

VTT Supply
The output edge rates of the ECLinPS family necessitate an almost exclusive use of controlled impedance transmission lines for system interconnect (the details of this
claim will be discussed in a latter section). Thus, unless
Thevenin equivalent termination schemes are going to be
used, a V TT supply is a must in ECLinPS designs. The choice
of using only Thevenin equivalent termination schemes to
save a power supply should not be made lightly as the
Thevenin scheme consumes up to ten times more power
than the equivalent parallel termination to a -2.0V VTT supply.
As was the case for the VEE supply, a dedicated power
plane, liberally bypassed as described above, should be
used for the VTT supply. In designs which rely heavily on
parallel termination schemes the VTT supply will be responsible for returning the switching current of the outputs to
ground, therefore a low AC impedance is a must. For
bypassing, many SIP resistor packs have bypass capaCitors
integrated in their design to supply the necessary bypassing
of the supply. The useof SIP resistors will be discussed more
thoroughly in a latter chapter.

VEE Supply
To take advantage of increased logic density and temperature compensated outputs many designers are building
array options with both temperature compensated output
levels and a -5.2V VEE supply. To alleviate any problems with
interfacing these arrays to ECLinPS 1OOE devices Motorola
has specified the operation of 100E devices to include the
standard 1OKH VEE voltage range. Moreover, because of the
superior voltage compensation of the bias network, this
guarantee comes without any changes in the DC or AC
specification limits. With the availability of both 10KH and
lOOK compatible devices in the ECLinPS family there is
generally no need to run 1OE devices at lOOK voltage levels.
If however this is desired, the 10E devices will function
at1 OOE VEE levels with, at worst, a small degradation in AC
performance for a few devices due to soft saturation of the
current source device.

Handling of Unused Inputs and Outputs
Unused Inputs
All ECLinPS devices have internal 50Kn-75Kn pulldown resistors connected to VEE' As a result an input which

ECLinPS

4-2

System Basics
is left open will be pulled to VEE and thus set at a logic lOW.
These internal pulldowns provide more than enough noise
margin to keep the input from turning on if noise is coupled
to the input, therefore there is no need to tie the inputs to VEE
external to the package. In addition by shorting the inputs to
VEE external to the package one removes the current limiting
effect of the pulldown resistor and under extreme VEE conditions the input transistor could be permanently damaged. If
there are concerns about leaving sensitive inputs, such as
clocks, open they should be tied low via an unused output or
a quiet connection to VIT •
Unless otherwise noted on the data sheets, the outputs
to differential input devices will go to a defined state when the
inputs are left open. This is accomplished via an internal
clamp. Note that this clamp will only take over if the voltage
at the inputs fall below = -2.SV. Therefore if equal voltages
of greater than -2.SV are placed on the inputs the outputs will
attain an undefined midswing state.
Unlike saturating logic families the inputs to an ECLinPS,
or any ECl device, cannot be tied directly to Vee to implement a logic HIGH level. Tying inputs to Vee will saturate the
input transistor and the AC and DC performance will be
seriously impaired. A logic HIGH on an ECLinPS input
should be tied to a level no higher than 600mV below the
Vee rail and more typically no higher than the specified
V,Hmax limit. A resistor or diode tree can be used to generate
a logic HIGH level or more commonly an output of an unused
gate can be used.

generation of crosstalk and other noise phenomena during
simultaneous switching situations. Although the noise generated in EClsystems is minor compared toothertechnologies there are methods to even further minimize the problem.
Figure 1.1 below illustrates the two output scenarios of
an Eel device: differential outputs and single ended outputs. During switching the current in the output device will
change by =17mA when loaded in the normal
to -2.0V
load. With differential outputs as one output switches from a
low to a high state the other switches from a high to a low
state simultaneously thus the resultant current change
through the Vceo connection is zero. The current simply
switches between the two outputs. However for the single
ended output, the current change flows through the V ceo
connection of the output device. This current change through
the V ceo pin of the package causes a voltage spike due to the
inductance of the pin.

son

0UIPUI
Current
Flow

OUT
IN

Unused Outputs
The handling of unused outputs is guided by two criteria:
power dissipation and noise generation. For single ended
output devices it is highly recommended to leave unused
outputs unterminated as there are no benefits in the alternative scheme. This not only saves the power associated with
the output but also reduces the noise on the Vee line by
reducing the current being switched through the inductance
of the Vee pins. For the counters and shift registers of the
family the count and shift frequencies will be maximized if the
parallel outputs are left unterminated. Of course for applications where these parallel outputs are needed this is not a
viable alternative.
Forthe differential outputs, on the other hand, things are
a little less cut and dry. If either of the outputs of a complimentary output pair is being used both outputs of the pair should
be terminated. This termination scheme minimizes the current being switched through the Vee pin and thus minimizes
the noise generated on Vee' If, however, neither of the
outputs of a complimentary pair are being used it makes
most sense to leave these unterminated to save power. Note
that the E 111 device has special termination. rules; these
rules are outlined on the data sheet for the device.

Minimizing Simultaneous Switching Noise
A common occurrence among ECl families is the

Single-Ended Output

OUT
IN
OUT

Differential Outputs

Figure 1.1 - Eel Output Structures
Traditionally manufacturers of ECl products have attempted to combat this problem by providing a separate Vee
pin for the output device (Vceo' V eeA etc.) and the internal
circuitry. By doing this the noise generated on the Vceo of the
output devices would see a high impedance internal to the

ECLinPS
4-3

System Basics
For ECLinPS devices the capacitive load produced by
an input ranges from 1.2pF to 2.0pF. The majority (~95%) of
this capacitance is contributed by the package with very little
added by the internal input circuitry. For this reason the
range is generally a result ofthe difference between a corner
and a center pin for the PlCC package. A good typical
capacitance value for a center pin is 1.4pf and for a corner
pin 1. 7pf. The capacitances for the other pins can be
deduced through a linear interpolation.

chip and not couple onto the the Vee line which controls the
output and internal bias levels. Unfortunately in practice the
noise generated on the V ceo would couple into the chip Vee
through the collector base capacitance ofthe output device,
thus a large portion of the noise seen on the V ceo line would
also be seen on the Vce line.
Forthe ECLinPS family and its associated edge speeds
it was decided that multiple V ceo pins would be necessary to
minimize the inductance and the associated noise generation. A design rule was established so that there would be no
more than three single ended outputs per V ceo pin. Initially
the Vee and Vceo pins were kept isolated from one another.
However it was discovered that in certain applications the
parasitics of the package and the output device would
combine to produce an instability which resulted in the
outputs going into an OSCillatory state. To alleviate this
oscillation problem it was necessary to make the V ce and
V ceo metal common internal to the package. Subsequent
evaluation showed that because of the liberal use of Vceo
pins the noise generated is equal to or less than that of
previous ECl families.
To further reduce the noise generated there are some
things that can be done at the system level. As mentioned
above there should be adequate bypassing of the Vee line
and the guidelines forthe handling of unused outputs should
be followed. In addition for wide single ended output devices
an increase in the characteristic impedance ofthe transmission line interconnect will result in a smaller time rate of
change of current; thus reducing the voltage glitch caused by
the inductance of the package. This noise improvement
should, of course, be weighed againstthe potential slowing
of the higher impedance trace to optimize the performance
ofthe entire system. In addition the connection between the
device Vee pins and the ground plane should be as small as
possible to minimize the inductance of the Vee line. Note that
a device mounted in a socket will exhibit a larger amount of
Vee noise due to the added inductance of the socket pins.

Wired-OR Connections
The use of wired-or connections in ECl designs is a
popular way to reduce total part count and optimize the
speed performance of a system. The limitation of OR-tying
ECl outputs has always been a combination of increased
delay per OR-tie and the negative going disturbance seen at
the output when one output switches from a high to a low
while the rest of the outputs remain high. For high speed
devices the latter problem is the primary limitation due to the
increased sensitivity to this phenomena with decreasing
outpultransition times. The following paragraph will attempt
to describe the wire-OR glitch phenomena from a physical
perspective.
Figure 1.2 illustrates a typical wire-OR situation. For
simplicity the discussion will deal with only two outputs,
however the argument could easily be expanded to include
any number of outputs. If both the A and the B outputs start
in the high state they will both supply equal amounts of
currenlto the load. If the B outpulthen transitions from a high
to a low the line althe emitterof B will see a sudden decrease
in the line Voltage. This negative going transition on the line
will continue downward at the natural fall time of the output
until the A output responds to the voltage change and
supplies the needed current to the load. This lag in the time
it takes for A to correct the load current and return the line to
a quiescent high level is comprised of three elements: the
natural response time of the A output, the delay associated
with the trace length between the two outputs and the time
it takes for a signal to propagate through the package. The
trace delay can be effectively forced to zero by OR-tying
adjacent pins. The resulting situation can then be considered "best case". In this best case situation if the delay
through the package is not a significant portion of the
transition time of the output the resulting negative going
glitch will be relatively small (~1 OOmV). A disturbance of this
size will not propagate through a system. As the trace length
between OR-tied outputs increases, the magnitude of the
negative going disturbance will increase. Older ECl families
specified the maximum delay allowed between OR-tied
outputs to prevent the creation of a glitch which would
propagate through a system.
As this glitch phenomena is a physical limitation, due to
decreased edge rates, ECLinPS devices are susceptible to
the problem to an even greater degree than previous slower
ECl families. The package delay of even the 28-lead PlCC

Effects of Capacitive Loads
The issue of AC parametric shifts with load capacitance
is a common concern especially with designers coming from
the TTL and CMOS worlds. For ECLinPS type edge speeds
wire interconnect starts acting like transmission lines for
lengths greater than 1/2". Therefore in ECLinPS designs for
the majority of cases the load on an output is seen by the
transmission line and not the output of the driving device.
The effects of load capacitance on transmission lines will be
discussed in detail in the next section.
If the load is close to the driving output «1/2"), the
resulting degradation will be 15-25ps/pF for both propagation delays and edge rates. In general a capacitive load on
an emitter follower has a greater impact on the falling edge
than the rising edge. Therefore the upper end of the range
given above represents the effect on fall times and the
associated propagation delays while the lower end represents the effect on the riSing output parameters.

ECLinPS

4-4

System Basics

Package

logic technologies are intimately tied to variations in the input
thresholds. As illustrated in Figure 1.3 although the delays
when measured from the threshold of the input to the 50%
point of the output are equal; when measured from the
specified 50% point olthe inputlo the 50% point of the output
the delays will vary with any shift in the switching reference.
Obviously the magnitude of the delay difference is also
proportional to the edge rate of the input. In addition to
increasing the size olthe delay windows, this reference shift
will cause the duty cycle of the output of a device to be
different than that of the input. Unfortunately these thresholds are perhaps the most difficult aspects of a logic device
to control. As a result for the ultimate in low skew performance differential ECl devices are a must. A quick perusal of
the ECLinPS databook will reveal a relatively large number
of totally differential devices which will lend themselves
nicely to very low skew applications such as clock distribu-

Figure 1.2 - Typical Wire-OR Configuration
is a significant portion of the transition times for an ECLinPS
device. Therefore even in the best case situation described
above one can expect an ~200mV glitch on the OR-tied line.
A glitch of this magnitude will not propagate through the
system but it is significantly worse than the best case
situation of earlier ECl families. In fact as long as the
distance between OR-tied outputs is kept to less than 112"
the resulting line disturbance will not be sufficientlo propagate
through most systems.
With this in mind the following recommendations are
offered for OR-tying in ECLinPS designs. First OR-tying of
clock lines should be avoided as even in the best case
situation the disturbance on the line is significant and could
cause false clocking in some situations. In addition wireORed outputs should be from the same package and preferably should be adjacent pins. Non adjacent outputs should
be within 1/2" of each other with the load resistor connection
situated near the midpoint of the trace (Figure 1.2). By
following these guidelines the practice of wire-ORing ECl
outputs can be expanded to the ECLinPS family without
encountering problems in the system.
A detailed discussion of wire-OR connections in the
ECLinPS world of performance is beyond the scope of this
text. For this reason a separate application note has been
written which deals with this situation in a much more
thorough manner. Anyone planning to use wire-OR connections in their ECLinPS design is encouraged to contact a
Motorola representative to obtain this application note.

Data

I
I

Tponom
Tpomax

Tponom~
Tpomin

. : ~~______________~~~~
ET'50%
Output

Figure 1.3 - Delay vs Switching Reference Offset

Clock Distribution
tion.
Clock skew is a major contributor to the upper limit of
operation of a high speed system, therefore any reduction in
this parameter will enhance the overall performance of a
system. Through the ECLinPS family and new offerings in
the 10KH family Motorola is providing devices uniquely
designed to meet the demands of low skew clock distribution.
By far the largest contributor to system skew is the
variation between different process lots of a given device.
This variation is what defines the total delay window specified in the data sheets. This window can be minimized if the
devices are fully differential due to the output level defined
thresholds which ensure a "centered" input swing. The
propagation delay windows of single ended ECl and other

In addition to these generic differential devices there are
several devices which were designed exclusively for clock
distribution systems. With past ECl families designers were
forced to build clock distribution trees with devices which
were compromises at best. The ECLinPS family, however,
was built around the Elll clock distribution chip; a fully
differential 1:9 fanout device which boasts within part skews
as well as part to part skews unequaled in today's market.
Additionally, to further deskew clock lines the E195
programmable delay chip is available. Although static delay
lines can remove built in path length difference skew they
can not compensate for variations in the delays of the
devices in the clock path. The E195 allows the user to delay
a signal over a 2ns range in ~20ps steps. Through the use

ECLinPS

4-5

System Basics
The metastability behavior and measurement of a flip
flop is a complicated subject and necessitates much more
time than is available in this forum for a thorough explanation. As a result the following description is of an overview
nature. Anyone interested in a more thorough narration on
the subject is encouraged to contact a Motorola representative to acquire the application note which contains a more
detailed discussion on the subject.
In many designs occassions arise where an asynchronous signal needs to be synchronized to the system clock.
Generally this task is accomplished with the use of a single
or series ofD flip flops as pictured in Figure 1.4. Because the
data signal and the clock signal are asynchronous the
system designer cannot guarantee that the setup and hold
specifications for the device will be met. This in and of itself
would not cause a problem if it was not for the metastable
behavior of a D flip flop. The metastable behavior of a flip flop
is described by the outputs of a device attaining a nondefined logic level or perhaps going into an OScillatory state
when the data and the clock inputs to the flip flop switch
simultaneously. It has been shown that this metastable behavior occurs across technology boundaries as well as
across performance levels within a technology.
For Eel the characterisitic of a flip flop in a metastable
state is a device whose outputs are in a non-defined state
near the midpoint of a normal output swing. The output will
return randomly to one of the two defined states some time
later (Figure 1.5). The two parameters of importance when
discussing metastability are the metastablity window; the

of this device the designer can match skews between clocks
to 20ps.
Although these two devices satisfy the needs for many
Eel designers they do overlook the needs of a special
subset; the designer who mixes Eel and TTL technologies.
When translating between Eel and TTL much of the skew
performance gained through the Elll is lost when passed
through the translator and distributed in TTL. To solve this
problem a new set of translators have been introduced in the
MECl 1OKH family. The H641 and H643 receive a differential Eel input and fan out nine TTL outputs with a guaranteed
unparalleled skew between the TTL outputs. The H640 and
H642 take differential EeL inputs and generate low skew
TTL outputs which are ideal for driving clocks in 68030 and
68040 microprocessor systems. By using the EeL aspects
of the Elll to distribute clock lines across the backplane to
TTL cards and receiving and translating these signals with
the H640, H641 , H642 or H643 a TTL clock distribution tree
can be designed with a performance level unheard of with
past logic families.
Through the development of a library of differential
devices, specialized low skew distribution chips and high
resolution programmable delay chips Motorola has serviced
the need for low skew clock distribution designs. These
offerings open the door for even higher performance next
generation machines.

Metastability Behavior

System 1

System 1
Clock

System 1
Ouput

.....J'"LSL

0 1 - - - - - - 1 System 2 Input

Data

D·Flip Flop

System2~

System 2

Clock

System 1

System
Clock

System 1

Ouput

...fLJ"L

Data

D-Flip Flop
System
Clock

Clock

Data

D-Flip Flop

,..- [>CIOCk

TO Delay

Figure 1.4 - Clock Synchronization Schemes

ECLinPS

4-6

System 2 Input

,--

System 2

System Basics

The challenge then becomes, how to characterize metastability behavior given the above circumstances. The standard method in the industry is to use Stoll's' equation, combined with the standard MTBF equation, to develop the
following relationship:

where:

Figure 1.5 - Metastable Behavior of an Eel Flip Flop

fe:
fo:
T p:
t:
't:

Clock Frequency
Data Frequency
FF Propagation Delay
Time Delay Between FF Clocks
FF Resolution Time Constant

Note thatthe clock frequency, data frequency and time delay
between flip flops are user defined parameters, thus it is up
to Motorola to provide only the propagation delays and the
resolution time constants for the ECLinPS flip flops.
The propagation delays are obviously already defined
so this leaves only the resolution time constant yet to be
determined. An evaluation fixture was fabricated and several ECLinPS flip flops were t;lvaluated for resolution time
constants. The results of the evaluation showed thatthe time
constant was somewhat dependent on the part type as all
the flip flops in the ECLinPS family do not use the same
general design. The time constants range from 125 - 225 ps
depending on the part type.
As an example for a system with a 1OOMHz clock and
75MHz data rate the required delay between clock edges of
a cascaded flip flop chain for the E151 register, assuming a
't of 200ps, would be:

window in time for which a transition on both the data and the
clock will cause a metastable output, and the settling time;
the time ittakes for a metastable outputto return to a defined
state. For the single flip flop design of Figure 1.3, the data
being fed into system 2 will be in an undefined state and thus
unusable if the synchronizing flip flop enters a metastable
state. Because of this a more popular design incorporates
multiple flip flop chains with cascading data inputs and clock
inputs which are delayed with respect to each other. This redundancy of flip flops helps to reduce the probability that the
data entering system 2 will be at an undefined level which
could wreak havoc on the logic olthat system. This reduction
in probability relies on thefactthat even ilthe preceeding flip
flop goes metastable it will settle to a defined state prior to the
clocking ofthe following flip flop. Obviously once the first flip
flop goes metastable there is an even chance that it will settle
in the wrong state and thus information will be lost. However,
there are error detection and correction methods to circumvent this problem. The larger the flip flop chain the lower the
probability of metastable data being fed into system 2.
Unfortunately for ECLinPS levels of performance both
the window width and the settling time are difficult or impossible to measure directly. The metastable window for an
ECLinPS flip flop is assuredly less than 5ps and most likely
less than 1ps based on SPICE level simulation results. In
either case, with todays measuring eqUipment it would be
impossible to measure this window width directly. Although
it is feasible to measure the settling time for a given occurence, this parameter is notfixed but rather is of a variable
length which makes it impossible to provide an absolute
guarantee.

MTBF = 1/ (2*1 OOMHz*75MHz*800ps*1 0

'V200P' )

solving for an MTBF of 10 years yields:
t = 3.1 ns therefore:

So for an MTBF of 10 years for the above situation the
second flip flop should be clocked 3.9ns afierthe first. Similar
results can be found by applying the equation to different
data and clock rates as well as different acceptable MTBF
rates.
'Stoll, P. "How to Avoid Synchronization Problems,"
VlSI Design, November/December 1982. pp. 56-59.

ECLinPS

4-7

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
DESIGN GUIDE

Transmission Line Theory

SECTION 2

Transmission Line Theory
passing through a point on the line. Thus, 4, can be
expressed in terms of the distributed inductance and capacitance of the line as shown by Equation 1.

Introduction
The ECLinPS family has pushed the world of ECl into
the realm of picoseconds. Whim output transitions move into
this picosecond region it becomes necessary to analyze
system interconnects to determine if transmission line phenomena will occur. A handyrule of thumb to determine if an
interconnect trace should be considered a transmission line
is if the interconnect delay is greater than 118th of the signal
transition time it should be considered a transmission line
and afforded all of the attention required by a transmission
line. If this rule is applied to the ECLinPS product line a
typical PCB trace will attain transmission line behaviors for
any length> 1/4" . Thus, a brief overview ofiransmission line
theory is presented, including a discus.sion of distributed and
lumped capacitance effects on transmission lines. For a
more thorough discussion of transmission lines the reader is
referred to Motorola's MECl Systems Design Handbook.

(eqt. 1)
where:·
lo = Inductance per unit length (H)
Co = Capacitance per unit length (F)

Propagation Delay
Propagation delay (Tpo) is also expressed as a function
of both the inductance and capacitance per unit length of a
transmission line. The propagation delay of the line is
defined by the following equation:
(eqt. 2)
If lo is expressed as microHenry'.s per unit length and
capacitance as picoFarad's per unit length, the units for
delay are nanoseconds per unit length. The propagation
velocity is defined as the reciprocal of the propagation delay:

Background
Exact transmission line analysis can be both tedious
and time consuming, therefore assumptions for simplifying
these types of calculations must be made. A reasonable
assumption is that interconnect losses caused by factors
such as bandwidth limitations, attenuation, and distortion
are negligible for a typical PCB trace. The basis for this
assumption is that losses due to the interconnect conductor
are only a fraction of the total losses in the entire interface
scheme. In addition, the conductivity of insulating material is
very small, as a result the dielectric losses are minimal. A
second and more fundamental assumption is that transmission line behavior can be described by two parameters: line
characteristic impedance (4,), and propagation delay (Tpo)'

lo and Co can be determined using the easily measured
parameters of line delay (To)' line length (l), and the line
characteristic impedance (4,) in conjunction with Equations
1 and 2. The propagation delay is defined as the ratio of line
delay to line length:
Tpo=Toll
Combining equations 1 and 2 yields:
(eqt. 3)·
(eqt. 4)

Characteristic Impedance
An interconnect which consists of two conductors and a
dielectric, characterized by distributed series resistances
and inductances along with distributed parallel capacitances
between them, is defined as a transmission line. These
transmission lines exhibit a characteristic impedance over
any length for which the distributed parameters are constant.
Since the contribution of the distributed series resistance to
the overall impedance is minimal, this term can be neglected
when expressing the characteristic impedance of a line. The
characteristic impedance is a dynamic quantity defined as
the ratio of the transient voltage to the transient current

Termination and Reflection Theory
Figure 2.1 shows an ECLinPS gate driving a lossless
transmission line of characteristic impedance
and terminated with resistance 1\. Modifying the circuit of Figure 2.1
such that the driving gate is represented by its equivalent
circuit gives the configuration shown in Figure 2.2.
For a positive step function V,N , a voltage step Vs travels
down the transmission line. The initial current in the transmission line is determined by the ratio Vs/Zo' When the

ECLinPS
4-8

Transmission Line Theory

==::J----r-

~
~r:)

Case 1: Rs < Zo; R T ", Zo
The initial current in the transmission line is determined
by the ratio VsIlo. However, the final steady state current is
determined by the ratio VslRT; assuming ohmic losses in the
transmission line are negligible. For case 1, an impedance
discontinuity exists at the line-load interface which causes a
reflected voltage and current to be generated at the instant
the initial signal arrives at this interface. To determine the
fraction of the traveling wave that will be reflected from the
line-load interface, Kirchoff's current law is applied to node
"a" in Figure 2.2. This results in the following:

Node "a"

IRE

Figure 2.1 - Typical Transmission Line
Driving Scenario
traveling wave arrives at the termination resistor R,-, Ohm's
Law must be maintained. If the line characteristic impedance
and the termination resistance match(i.e. lo=RT), the travel·
ing wave does not encounter a discontinuity at the line-load
interface; thus the total voltage across the termination resis·
tance is the incident voltage Vs' However, if mismatches
between the line characteristic impedance and the termination resistance occur, a reflected wave must be set up to
ensure Ohm's Law is obeyed at the line-load interface. In
addition, the reflected wave may also encounter a disconti·
nuity at the interface between the transmission line and the
source resistance, thereby sending a re-reflected wave back
towards the load. When neither the source nor the load impedance match the line characteristic impedance multiple
reflections occur with the reflected signals being attenuated
with each passage over the transmission line. The output
response of this configuration appears as a damped oscillation, asymptotically approaching the steady state value, a
phenomenon often referred to as ringing.

Using substitution:
(eqt. 5)
Since only one voltage can exist at node "a" at any instant in
time:
(eqt. 6)
Combining Equations 5 and 6, and solving for VR yields:

(eqt. 7)
Therefore:

The term PL' referred to as the load reflection coefficient, represents the fraction of the voltage wave arriving at the lineload interface that is reflected back toward the source.
Similarly, a source reflection coefficient can be derived
as:

Figure 2.2 - Thevenin Equivalent Circuit of Figure 2.1

In performing transmission line analysis, designers may
encounter one of three impedance situations:

(eqt. 8)
From equations 7 and 8 it is apparent that multiple
reflections will occur when neither the source nor the load
impedances match the characteristic impedance of the line.
A general equation for the total line voltage as a function of
time and distance is expressed by Equation 9.

where:
Rs = Source Resistance
RT = Termination Resistance

V(x,t) =

ECLinPS

4-9

VA(t)*[U(t-TpD'x) + PL'U(t-TpD (2L-x) +
PL'P s'U(t-TPD(2L+x)) +
(P L**2)*(ps 'U(t-T PD(4L-x)) +

Transmission Line Theory
(P L**2)*ps "2)*U(t-Tpo(4Ltx» t ... ] t
Voc
(eqt. 9)

ZO=50Q

)

where:
VA = Voltage Entering the Transmission Line
T PO = Propagation Delay of the Line
L
= Total Line Length
x
= Distance to an Arbitrary Point on the Line
V DC = Initial Quiescent Voltage of the Line

Figure 2.4 " Transmission Line Model for ~ > Zo
VTF = (65/71)*(-0.9) = -0.82V

Finally, the output voltage, VI' can be derived from the
reflection coefficient by combining Equations 6 and 7:

The input voltage is a ramp from -1.75V to -0.9V. The initial
voltage traveling down the line is:

VT=(1 t(RT-ZO)/(RTtZO))*Vs

Vs = (50/56)*0.85 = 0.76V

VT=(2*R!(RTtZO)*Vs

From Equations 7 and 8:

The two possible configurations for the Case 1 conditions are RT>ZO and RT Zo
Forthe case in which Rr>Za, PLis.positive, and the initial
current at node "a" is greater than the final quiescent current

From Equation 9, the output voltage VT after one line delay
is:

I'N'TIAL > IFINAL
Likewise, after a time equal to three times the line delay, the
output voltage VT is

Hence:

Thus a reflected current, IR' must flow toward the source in
order to attain the final steady state current as shown in
Figure 2.3.
An example of a line mismatched at both ends, with the

Additional iterations of Equation 9 can be performed to show
that the ringing asymptotically approaches the final line
voltage of -0.82V. Ringing is a characteristic response for
transmission lines mismatched at both ends with Rr > ZOo A
SPICE representation of configuration 1 is illustrated in
Figure 2.5.

~I~

-Is

I -tIR

I-

I
I

Distance

Figure 2.3 " Reflected Voltage Wave for ~ > Zo
termination resistance greater than the load resistance is
shown in Figure 2.4. The initial steady state output voltage
is given by:

~
Time

VTI = (65/71)*(-1.75) = -1.60V

H=1000 psldiv
V=200 mVldiv

The final steady state output voltage is given by:
Figure 2.5 SPICE Results for Circuit of Figure 2.4

ECLinPS
4-10

Transmission Line Theory
VTF

Configuration 2: RT < Zo
For the case in which RT Line Delay

Zo; 50n
)

Figure 2.9 shows the line response for the same circuit
as above, but for the case in which the input pulse width is
less than the line delay. As in the previous example, the initial
steady state voltage across the transmission line is -1.49
volts, and the reflection coefficients are -0.18 and -0.79 for
the load and source respectively. However, the intermediate

Figure 2.7· Transmission Line Model for R, < Zo

ECLinPS

4·11

Transmission Line Theory
~~

....

\
\

...

'5
'5

i\\...

LJ L L/\.

"'\

Time

H= 1000 ps/div
V=200 mV/div

H= 1000 ps/div
V=100 mV/div

Figure 2.9 - SPICE Results for Circuit of Figure 2.7
with Input Pulse < Line Delay

Figure 2.11 - SPICE Results for Shorted Line
with the Input Pulse Width> Line Delay

voltage across the transmission line is a series of positivegoing pulses of decreasing amplitude for each round trip of
the reflected voltage, until the final steady state voltage of 1.49 volts is reached.

source end the voltage is partially reflected back toward the
shorted end in accordance with the source reflection coefficient. Thus, the voltage at the shorted end of the transmission line is always zero while at the source end the voltage
is reduced for each round trip of the reflected voltage. The
voltage at the source end tends toward the final steady state
condition of zero volts across the transmission line. The
values of the source and line characteristic impedances in
this example are such that the amplitude decreases by 50%
with each successive round trip across the transmission line.
Figure 2.12 shows the line response for the same circuit
as above, but for the case in which the input pulse width is
less than the line delay. As in the previous example, the
initial and final steady state voltages across the transmission
line are zero, and the reflection coefficients are -1 and -0.5
for the load and source respectively. However, the intermediate voltage across the transmission line is a series of
negative pulses with the amplitude of each pulse decreasing
for each round trip of the reflected voltage until the final
steady state voltage of zero volts is attained. Again, for this
example the amplitude of the output response decreases by

ShortedUne
The shorted line is a special case of configuration 2 in
which the load reflection coefficient is -1 , and the reflections
tend toward the steady state condition of zero line voltage
and a current defined by the source voltage and the source
resistance.

R - 16 7n

Zo = 50n

~~):=J-)---r'l0 VT

VIN

CS?

Figure 2.10 - Transmission Line Model
for Shorted Line
An example of a shorted line is shown in Figure 2.10.
The transmission line response for the case in which the
input pulse width is greater than the line delay is shown in
Figure 2.11. The initial and final steady state voltages across
the transmission line are zero. The source is a step function
with a 0.85 volt amplitude. The initial voltage traveling down
the line is:

f\
\

II \

= (50/66.7)*0.85 = 0.64V

\ !

From Equations 7 and 8,

PL = (0-50)/(0+50) = -1

Time

Ps = (16.7-50)/(16.7+50) = -0.5
Upon reaching the shorted end of the line, the initial voltage
waveform is inverted and reflected toward the source. At the

H=1000 ps/div
V=200 mV/div

Figure 2.12 - SPICE Results for Shorted Line
with the Input Pulse Width < Line Delay

ECLinPS
4-12

Transmission Line Theory
50% for each successive reflection due to the choice of
source and transmission line characteristic impedances.

Case 2: Rs $; Zo; RT

Zo
As in Case 1, the initial current in the transmission line
is determined by the ratio of VslZa' Similarly, since RT = Za
the final steady state current is also determined by the ratio
Vs/Za' Because a discontinuity does not exist at the line-load
interface all the energy in the traveling step is absorbed by
the termination resistance, in accordance with Ohm's Law.
Therefore no reflections occur and the output response is
merely a delayed version of the input waveform.

/
H=400ps/div
V=200 mV/div

Time
ZO=50Q

)

Figure 2.14· SPICE Results for Matched Termination
resistance matches the line characteristic impedance.
Ringing or stair-step output responses do not occur since the
load reflection coefficient is zero.

Figure 2.13 - Transmission Line Model
for Matched Termination

Case 3: Rs

Zo; RT", Zo
When the termination resistance does not match the
line characteristic impedance reflections arising from the
load will occur. Fortunately, in case 3, the source resistance
and the line characteristic impedance are equal, thus the
reflection coefficient is zero and the energy in these reflections is completely absorbed at the source thus no further
reflections occur.

An example of a line mismatched at the source but
matched at the load is shown in Figure 2.13. For an input
pulse of -1.75V to -0.9V is given by:
VTI = (50/56)*(-1.75) = -1.56V
The final steady state output voltage is given by

ZO=50Q

)

VTF = (50/56)*(-0.9) = -0.80V
The source is a step function with an 0.85 volt amplitude.
The initial voltage traveling down the line is:
Vs = (50/56)*0.85 = 0.76V

Figure 2.15· Transmission Line Model for Vs

=Zo

From Equations 7 and 8,
An example of a line mismatched at the load but
matched at the source is shown in Figure 2.15. For an input
pulse of -1.75V to -0.9V the initial steady state output voltage
is given by:

PL = (50-50)/(65+50) = 0
Ps = (6-50)/(6+50) = -0.79
From Equation 9, the output voltage VT after one line delay
is:

VTI = (65/115)*(-1.75) = -0.99V
The final steady state output voltage is given by

VT(L,Tpo) = VA(t)*[1 + pLl + Voc = -0.80V
VTF = (65/115)*(-0.9) = -0.51 V
Likewise, after a time equal to three times the line delay, the
output voltage VT is:

The source is a step function with a 0.85 volt amplitude. The
initial voltage traveling down the line is:
Vs = (50/100)*0.85 = 0.43V

Thus the output response attains its final steady state value
( Figure 2.14) after only one line delay when the termination

From Equations 7 and 8,

ECLinPS

4·13

Transmission Line Theory
PL

= (65-50)/(65+50) =0.13

)-0

Ps = (50-50)/(50+50) = 0
From Equation 9, the output voltage VT after one line delay
is:

Figure 2.17 - Series Terminated Transmission Line
Likewise, after a time equal to three times the line delay, the
output voltage VT is:

Thus the output response attains its final steady state value
after one line delay when the source resistance matches the
line characteristic impedance. Again, ringing or a stair-step
output does not occur since the load reflection coefficient is
zero ( Figure 2.16).

vS = (50/100)*0.85 = 0.43V

I
V
Time

wave will be reflected toward the source. Since the source
resistance matches the line characteristic impedance all the
energy in the reflected wave is absorbed, and no further
reflections occur. This "source absorption" feature reduces
the effects of ringing, making series terminations particularly
useful for transmitting signals through a backplane or other
interconnects where discontinuities exist.
As stated previously, the signal in the line is only at half
amplitude and the reflection restores the signal to the full
amplitude. It is important to ensure that all loads are located
near the end of the transmission line so that a two step input
signal is not seen by any of the loads.
For the series terminated circuit of Figure 2.17 with
+ RST = Zo and an input pulse rising from -1. 75V to -0.9V, the
initial line voltage VTI is -1.325V and the final line voltage,
VTF , is -0.9V. The source is a step function with a 0.85 volt
amplitude. The initial voltage traveling down t~e line is:

From Equations 7 and 8,

PL = (00-50)/(00+50) = 1
H=400ps/div
V=100 mV/div

Ps = (50-50)/(50+50) = 0
From Equation 9, the output voltage VT after one line delay
is:

Figure 2.16 - SPICE Results for Circuit of Figure 2.15
Series Termination
Series termination represents a special subcategory of
Case 3 in which the load reflection coefficient is + 1 and the
source resistance is made equal to the line characteristic
impedance by inserting a resistor, RST' between and in
series with, the transmission line and the source resistance
Ro' The reflections tend toward the steady state conditions
of zero current in the transmission line, and an output voltage
equal to the input voltage. This type of termination is illustrated by the circuit configuration of Figure 2.17. The initial
voltage down the line will be only half the amplitude of the
input signal due to the voltage division of the equal source
and line impedances.

Likewise, after a time equal to three times the line delay, the
output voltage VT is:

Since the load reflection coefficient is unity, the voltage
at the output attains the full ECl swing, whereas the voltage
at the beginning of the transmission line does not attain this
level until the reflected voltage arrives back at the source
termination (Figures 2.17 and 2.18). No other reflections
occur because the source impedance and line characteristic
impedance match.
.
.

(eqt.10)

Capacitive
The load reflection coefficient tends to unity, thus a
voltage wave arriving at the load will double in amplitude,
and a reflected wave with the same amplitude as the incident

Effect~

on Proppgation Delay

Lumped Capacitive Loads

ECLinPS
4-14

The effect of load capacitance on propagation delay

Transmission line Theory
r'-l

~./

/ I~

/
f

II
)
H=400 ps/div
V=200 mV/div

Time

H= 1000 ps/div
V=200 mV/div

Time

Figure 2.20 - Line Delay vs Lumped Capacitive Load

Figure 2.18 - SPICE Results for Series
Terminated Line

in delay for load capacitances of 0, 1, 5, 10 and 20 picoFarads.
The increase in propagation delay can be determined
by using Thevenin's theorem to convert the transmission line
into a single time constant network with a ramp input voltage.
The analysis applies to both series and parallel terminations,
since both configurations can be represented as a single
time constant network with a time constant, t, and a Thevenin
impedance Z'.
Figure 2.21 shows the Thevenized versions for the
series and parallel terminated configurations. The Thevenin
impedance for the series configuration is approximately
twice that for the parallel terminated case, thus the time
constant will be two times greater for the series terminated
configuration. Since t is proportional to the risetime, the
risetime will also be two times greater;thus the reason for the
larger impact of capacitive loading on the series terminated
configuration.

must be considered when using high performance inte·
grated circuits such as the ECLinPS family. Although
capacitive loading affects both series and parallel termination schemes, it is more pronounced for the series terminated case. Figure 2.19a illustrates a series terminated line
with a capacitive load CL. Under the no load condition, CL=O,
the delay between the 50% point of the input waveform to the

Figure 2.19a - Lumped Load Transmission
Line Model

Z'=Zo

50% point of the output waveform is defined as the line delay
To' A capacitive load placed at the end of the line increases
the risetime of the output signal,thereby increasing To by an
amount ~To (Figure 2.19b). Figure 2.20 shows the increase

VIN~
z'c=ZOc L

I-=- CL

Thevenin Equivalent Series Termination
~

z=~~

VIN~

Line
Input

-=- ICL
-=-

"'N/2~
-

z'C=(Zo /2)C L

Thevenin Equivalent Parallel Termination
~_ _ _ VHIGH

~Loaded
/"
Line

Output

Aol'----

t R= 0.6a

Response

a= 1.67t R
VLOIW---_ _...J

Unloaded
Response

t= a

Figure 2.21 - Thevenin Equivalent Lumped
Capacitance Circuits

Figure 2.19b - ~TD Introduced by Capacitive Load

ECLinPS

4-15

ICL

-=-

Transmission Line Theory
gation delay. A circuit configuration for observing distributed
capacitive loading effects is shown in Figure 2.23.

2.0

1.5

,..-

1.0

0.5

0.0

0.5

V
Figure 2.23 - Transmission Line Model for Distributed
Capacitive Load
1.0

1.5

2.0

2.5

Each capacitive load connected along a transmission
line causes a reflection of opposite polarity to the incident
wave. If the loads are spaced such that the risetime is
greater than the time necessary for the incident wave to
travel from one load to the next, the reflected waves from two
adjacent loads will overlap. Figure 2.24 shows the output
response for a transmission line with two distributed capacitive loads of 2pF separated by a line propagation time of
750ps. The upper trace, with a 20-80% input signal risetime
of 400ps, shows two distinct reflections. The middle and
lower traces with 20-80% risetimes of 750 ps and 950ps
respectively, show that overlap occurs as the risetime becomes longer than the line propagation delay.

Normalized Line-Load Time Constant (Z'C I t R )

Figure 2.22 - Normalized Delay Increase Due
to Lumped Capacitive Load
The relationship between the change in delay and the
line-load time constant is shown in Figure 2.22. Both the
delay change(j.T Dland the line-load time constant(Z'C) are
normalized to the 20-80% risetime of the input signal. This
chart provides a convenient graphical approach for approximating delay increases due to capacitive loads as illustrated
by the following example.
Given a 1000 series terminated line with a 5pF load at
the end of the line and a no load rise time of 400ps the
increase in delay, j.TD' can be determined using Figure 2.22.
The normalized line-load time constant is:
Z'C/IR = 1000*5pF/400ps = 1.25
Using this value and Figure 2.22:

Therefore:
j.T D = 0.9*400ps = 360ps

Time

Thus 360ps is added to the no load delay to arrive at the
approximate delay for a 5pF load. For a 1000 line employing
a matched parallel termination scheme, Z'=500, the added
delay is only 240ps. This added delay is significantly less
than the one encountered for the series terminated case.
Thus when critical delay paths are being designed it is
incumbent on the designer to give special consideration to
the termination scheme, lumped loading capacitance and
line impedance to optimize the delay performance of the
system.

H= 1000 ps/div
V=100 mV/div

Figure 2.24 - Reflections Due to
Distributed Capacitance
Increasing the number of distributed capacitive loads
effectively decreases the line characteristic impedance as
demonstrated by Figure 2.25. The upper trace shows that
reflections occur for approximately 3.5 ns, during which time
the characteristic impedance olthe line appearslower(= 760)
than actual due to capacitive loading. After the reflections
have ended, the transmission line appears as a short and the
final steady state voltage is reached. The middle trace shows
that decreasing the' termination resistance to match the
effective line characteristic imper':mce produces a response
typical of a properly terminated line. Finally, the lower trace
shows that the original steady state output can be attained
by changing the source resistance to match the load res is-

Distributed Capacitive Loads
In addition to lumped loading, capacitive loads may be
distributed along transmission lines. There are three consequences of distributed capacitive loading of transmission
lines: reflections, lower line impedance, and increased propa-

EClinPS
4-16

Transmission Line Theory
For the circuit used to obtain the traces in Figure 2.25,
the distributed load capacitance is 4pF. From Equation 3,
Co is calculated as

/ I~

Iii

//1' ~

-1/
-

""-

Co = 750 ps/930 = 8pF

RS= RT = 93Q\

RS= 93!1, R T = 76Q

Hence:

Zo'

I
RS

76Qr

93Q/,t(1 + 4pF/8pF) = 760

Thus the effective line impedance is 170 lower than the
actual impedance while reflections are occurring on the line.

I
Time

H=2000 psJdiv
V=100 mVJdiv

Line Delay Increase
The increase in line delay caused by distributed loading
is calculated by adding the distributed capacitance (CD) to
the intrinsic line capacitance in Equation 2.

Figure 2.25 • Characteristic Impedance Changes
Due to Distributed Capacitive Loads
tance and the effective characteristic capacitance.

TpD

Reduced Line Characteristic Impedance
To a first order approximation the load capacitance(C L )
is represented as an increase in the intrinsic line capacitance
along that portion of the transmission line for which the load
capacitances are distributed. If the length over which the
load capacitances are distributed is defined as "L" the
distributed value of the load capacitance(CD) is given by

TpD' = ,t(Lo '(Co+C o))

,t(Lo 'Co)

TpD' = T pD ·,t(1 + CD/CO)

(eqt.13)

Once again for the circuit used to obtain the traces in
Figure 2.25, the distributed load capacitance is 4pF. From
the previous example the intrinsic line capacitance is 8 pF
therefore,

(eqt. 11)
T po' = 750ps·,t(1 + 4pF/8pF) = 919ps
The reduced line impedance is obtained by adding CD to Co
in Equation 1.

Thus, the effect of distributed load capacitance on line delay
is to increase the delay by 169ps. From Equation 13 it is
obvious that the larger the Co of the line the smaller will be
the increase in delay due to a distributive capacitive load.
Therefore, to obtain the minimum impedance change and
lowest propagation delay as a function of gate loading, the
lowest characteristic impedance line should be used as this
results in a line with the largest intrinsic line capacitance.

Zo = ,t(Lo/C o)
Zo' = ,t(Lo/(Co + CD)) = ,t(Lo/(C o'(1+C D/C O )))
(eqt. 12)

ECLinPS
4·17

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
System Interconnect

DESIGN GUIDE

SECTION 3
System Interconnect

Introduction

3. Multilayer boards
The most common printed circuit board material used for
digital designs is a glass- epoxy laminate. These boards use
a fiberglass dielectric with copper foils bonded to both sides
of the dielectric material by an epoxy resin. Other substrate
materials include a fiberglass dielectric with a polyimide
resin and fiberglass dielectric with a teflon resin. For
multilayer boards the inner layers are separated by sheets of
prepreg which acts as both a dielectric material and a
bonding agent between layers.
The choice of substrate material depends on the function for which the board will be used, the environment in
which the board is to operate, and costs. Table 3.1 lists
several phYSical qualities which characterize several of the
the available PCB types. Each available substrate material
has its own properties which makes it ideally suited for
particular applications.

As mentioned earlier, edge rates of the ECLinPS family
are such that most interconnects must be treated as transmission lines. Thus, a controlled impedance environment is
necessary to produce predictable interconnect delays as
well as limiting the reflection phenomena of undershoot and
overshoot. The three most common techniques for circuit
and/or system interconnect at high data rates are microstrip,
stripline and coaxial cable; both microstrip and stripline are
printed circuit board methods whereas coaxial cable is most
often used for interconnecting different parts of a system
which are separated by relatively large distances. For
slower speed applications «300M Hz) a twisted pair scheme
also works well. The scope of this writing will not include the
twisted pair technique, however a detailed discussion of this
topic can be found in the MECL System Design Handbook.
Finally, wirewrap boards are not recommended for the
ECLinPS family because the fast edge speeds exceed the
capabilities of normal wirewrapped connections. Mismatches
at the connections cause reflections which distort the fast
signal, significantly reducing the noise immunity of the system and perhaps causing erroneous operation.

Glass-Epoxy
Possesses good moisture absorption, chemical, and
heat resistance properties as well as mechanical strength
over standard humidity and temperature ranges. The most
widely used versions are G10 and FR4, the fire resistant
version of G10.

Printed Circuit Boards

Glass-Polyimide
Good for elevated temperature operation because of its
tight tolerance of the coefficient of thermal expansion. Very
hard material, so it may damage drilling eqUipment when
being drilled.

Printed circuits boards (PCB's) provide a reliable and
economical means of interconnecting electrical signals
between system components. Printed circuit boards consist
of a dielectric substrate over which the conducting printed
circuit material is placed. Three major categories of printed
circuit boards exist:

Glass-Teflon
Good for use when a low dielectric material is required.
Very soft material, so it may be difficult to build features

1. Single-sided boards
2. Double-sided boards

Material

Dielectric
Constant

Dissipation
Factor

Thermal Coefficient
of Expansion

Tensile
Modulus

Glass-Epoxy

4.8 (1MHz)

0.022 (1 MHz)

13 - 16 (1O. B/OC)

2.5

PTFE

2.1 (10GHz)

0.0004 (10GHz)

224 (1 O·B/oC)

0.05

Glass-Polyimide

4.5 (1MHz)

0.10 (1MHz)

12 - 14 (10· B/0 C)

2.8

Table 3.1 - Characterisitics of Common PCB Materials

ECLinPS
4-18

System Interconnect
requiring precise geometries. Relatively expensive material.

h =mils
E= 4.8

"
.5:

Microstrip
A microstrip line is the easiest printed circuit interconnect to fabricate because it consists simply of a ground plane
and flat signal conductor separated by a dielectric ( Figure
3.1).

II.

.eo
0

h=60

...
..
:::;
'u

h = 100

30
Ground Plane

Figure 3.1 - Microstrip Line

The characteristic impedance, Zo, of a microstrip line is
given by:

In [

87
,I (E, + 1.41)

(5.98 • h) ]
( 0.8w+t)

(eq!. 1)
3

where:
= Relative Dielectric Constant of the Substrate
w = Width of the Signal Trace
= Thickness of Signal Trace
t
= Thickness of the Dielectric
h

130 -f-~-+--+--+---IE= 4.8

t= 1.4mil

.§

c
:::;

105

125

Figure 3.2 is a plot of characteristic impedance as a
function of trace width and dielectric thickness for a dielectric
constant of 4.8 and a trace thickness of 1.4mils (1 ounce
copper). Using the equation for Co developed in the previous
chapter and Equation 1 above the capacitance per unit
length can be calculated for various trace widths. Figure 3.3
plots Co vs trace width for several different dielectric thicknesses. In addition Figure 3.3 plots Co vs the characteristic
impedance for a microstrip line for the dielectric constant
and trace thickness given above.
The propagation delay for a signal on a microstrip line
is described by the following equation:

h = mils

Figure 3.3 - Line Capacitance vs Line Impedance
and Trace Width

150

110

r----. I----

Characteristic Impedance-Zo (n)

To mitigate the effects of electric field fringing, an
additional constraint is that the width of the ground plane be
such that it extends past each edge of the signal line by at
least the width of the signal line.

--........
25

0.1 < w/h < 3.0 and 1 < E, < 15

."
.....
.

Equation 1 is accurate to within ±5% when:

£0

110

E= 4.8
t = 1.4mils

Zo =

90
Trace Width (mils)

h = 100

TPD

1.016,1(0.475 • E, + 0.67) ns/foot

(eqt2)

h = 60

where:
= Dielectric Constant of the Board Material

30
10

110

Note that the propagation delay is dependent only on the
dielectric constant of the PCB substrate. Figure 3.4 plots the
propagation delay of a microstrip line versus the dielectric
constant of the PCB.

Trace Width (mils)

Figure 3.2 - Microstrip Impedance vs Trace Width

ECLinPS

4-19

System Interconnect
200
~

180

160

.'"

140

120

./'

Q
Q.

11-

9:0

~
c

./'

......
u

V
./

~
.!!!

.§

b=mils
£=4.8
t= 1.4mil

c
::i

50
b = 20

100
2

Trace Width (mils)

Dielectric Constant (e r )

Figure 3.6 - Stripline Impedance vs Trace Width

Figure 3.4 - Propagation Delay vs Dielectric Constant

As was the case with a microstrip line the capacitance
per unit length of a stripline trace can be calculated using the
Co equation from Chapter 2. The graphs of Figure 3.7 plot

Stripline
Stripline is a printed circuit board interconnect in which
a signal conductor is placed in a dielectric medium which is
"sandwiched" between two conducting layers (Figure 3.5).

4.0 ..,-_ _..,-_ _..,-_ _.,-_ _.,-_--,
~

.5
IL

3.5

===:0

VEE

(eqt. 12)

Figure 3.12 - Unterminated Transmission Line
where:
l
= Line length
tA = Rise time
T po= Propagation Delay per unit length

The function of RE is to provide the drive current for a
high to low transition at the driver output. Since the reflection
coefficient at the load is of opposite polarity to that at the
source, the signal will be reflected back and forth over the
transmission line with the polarity changing after each reflection from the source impedance. Thus, steps appear at the
input tothe receiving gate. When RE is too large steps appear
in the trailing edge of the propagating signal that slows the
edge speed of the input to the receiving gate, subsequently
causing an increase in the net propagation delay. A reasonable negative-going signal swing at the input of the receiving
gate results when the value of RE is selected to produce an
initial step of 600mV at the driving gate. Hence:
1* Zo > 0.6

(eqt. 8)

6.2Zo eo RE (1 DE), 4.9Zo eo RE (100E)

(eqt. 9)

Further, the propagation delay increases with gate loading,
thus the actual delay per unit length (Tpo') is given as:
Tpo' = TpD • ~(1 + CD I (l* Co))
Substitution of the modified delay per unit length into Equation 12 and rearranging yields Equation 13:
(eqt. 13)
Solving Equation 13 for the maximum line length produces:
lma> = 0.5 '(~( (CD I Co) •• 2
+ (tAl T pD )" 2) - Col Co

(eqt. 14)

Assuming a worst case capacitance of 2 pF and a rise time
of 200 ps for the ECLinPS family gives a value of 0.3 inches
for the maximum open line length.
Table 3.3 shows maximum open line lengths derived
from SPICE simulations for single and double gate loads, a
maximum overshoot of 40% and undershoot of 20% was
assumed. The simulation results indicate that for a son line
a stub length of ~ 0.3 inches will limit the overshoot to less
than 40%, and the undershoot to within 20% of the logic
swing. Signal traces will most assuredly be larger than .3"
for all but the simplest of interconnects, thus for most
practical applications it will be necessary to use ECLinPS
devices in a controlled impedance environment.

Load resistors of less than 180n should not be used because the heavy load may cause a reduction in noise
immunity when the output is in the high state due to an
increased output emitter-follower VBE drop.
When the driver gate delivers a full ECl swing, the
signal propagates from point A arriving at pOint B a time To
!ater. At point B the signal is reflected as a function of PL' The
Input Impedance of the receiving gate is large relative to the
line characteristic impedance, therefore:
(eqt. 10)
A large positive reflection occurs resulting in overshoot. The
reflected signal reaches point A at time 2To' and a large

ECLinPS

4-23

System Interconnect
Microstrip
Zo (0)

50
68
75
82
90
100

Fanout

Stripline
Fanout

Fanout

Lmax (in)

Lm.. (in)

0.3
0.3
0.3
0.3
0.3
0.25

0.2
0.15
0.15
0.1
0.1
0.1

0.3
0.25
0.25
0.25
0.25
0.25

0.15
0.1
0.1
0.1
0.1
0.1

Table 3.3 - SPICE Derived Maximum Open Line Lengths for ECLinPS Designs
additional supply voltage. An alternate approach to using a
single power supply is to use a resistor divider network as
shown in Figure 3.13b. The Thevenin equivalent of the two
resistors is a single resistor equal to the characteristic
impedance of the line, and terminated to VTr The values for
resistors R, and R2 may be obtained from the following
relationships:

Parallel Termination
When the fastest circuit performance or the ability to
drive distributed loads is desired, parallel termination is the
method of choice. An important feature of the parallel
termination scheme is the undistorted waveform along the
full length of the line. A parallel terminated line is one in which
the receiving end is terminated to a voltage (VTT) through a
resistor (RT ) with a value equal to the line characteristic
impedance (Figure 3.13a). An advantage of this technique
is that power consumption can be decreased by a judicious
choice of VTr For 500 systems the typical value of VTT is
negative two volts.
Although the single resistor termination to VTT con·
serves power, it offers the disadvantage of requiring an

(eqt. 15)
(eqt. 16)
For a nominal 1OE supply voltage of -5.2V and VTT of -2V:
(eqt. 17)
(eqt. 18)

R2 = 2.6' Zo
R, = R2 /1.6

For a nominal 1OOE supply voltage of -4.5V and VTT of -2V

R2 = 2.25' Zo
R, = R2/ 1.25

(eqt. 19)
(eqt. 20)

Table 3.4 provides a reference of values for the resistor
divider network of Figure 3.13b.
Figure 3.13a Parallel Termination to VTT
10E

lODE

ZO(O)

50
70
75
80
90
100
120
150

R, (0)

R2 (0)

R,(O)

R2 (0)

81
113
121
130
146
162
194
243

130
182
195
208
234
260
312
390

90
126
135
144
161
180
216
270

113
158
169
180
202
225
270
338

Figure 3.13b Thevenin Equivalent Parallel Termination
Figure 3.13 - Parallel Termination Schemes

Table 3.4 - Thevenin Termination Resistor Values

ECLinPS

4-24

System Interconnect
For both configurations, when the equivalent termination resistance matches the line impedance no reflection
occurs because all the energy in the signal is absorbed by
the termination. Hence, the primary tradeoff between the
two types of termination schemes are power versus power
supply requirements. As mentioned earlier the VTT scenario
requires an extra power supply, however the Theveninization technique will consume 10 fold more DC power. Fortunately this extra power consumption will not be seen on the
die, therefore both techniques will result in the same die
junction temperatures.
ECLinPS output drivers consists of emitter followers
designed to drive a 500 load into a negative two volt supply
(VTT)' Under these conditions the nominal 1OE output levels
are -1. 75volts at 5mA for the low state and -0.9volts at 22m A
for the high state. For the 1OOE devices the nominal output
levels are -0.955 volts at 20.9mA for the high state and 1.705volts at 5.9mA for the low state.
Figure 3.14 shows the nominal output characteristics
for ECLinPS devices driving various load impedances returned to a negative two volt supply. This plot applies to both
10E and 1OOE versions of the ECLinPS family. The output
resistances RH (high state output resistance) and RL (low
state output resistance) are obtained from the reciprocal of
the slope at the desired operating point. Many applications
require loads other than 500, the resulting VOH and VOL
levels can be estimated using the following technique.

r------~----~-,l--oVOH

-770mV .,.

VOL

-1710mV

Figure 3.15 • Equivalent Model for
Calculating 1DE Output Levels

where:
IHOUT = (-770mV - VTT)/(60 + RT)
and
VOL = -171 OmV - S*ILQUT

(eqt. 22)

where:
ILOUT = (-1710mV - VTT) I (SO + RT)
lODE Devices
The equivalent output circuit is shown in Figure 3.16.
The output levels are estimated from Figure 3.16 as follows:

VOH = -S30mV - 6*I HOUT

(eqt. 23)

where:
IHOUT = (-S30mV - VTT) I (60 + RT)

-2.0

-1.75

-1.5

-1.25

-1.0

-0.75

-0.5

-0.25

Output Voltage (V)

Figure 3.14· ECLinPS Output Charactersitics
-1660mV

IDE Devices
The equivalent output circuit is shown in Figure 3.15.
The output levels are estimated from Figure 3.15 as follows:

VOH = -770mV - 6*I HOUT

Figure 3.16· Equivalent Circuit for
Calculating 1DDE Output Levels

(eqt. 21)

ECLinPS

4·25

System Interconnect
and
VOL = -1660mV - S*I LOUT

As mentioned in the Transmission line section, series
termination techniques are useful when the interconnect
lengths are long or impedance· discontinuities exist on the
line. Additionally, the signal travels down the line at half
amplitude minimizing. problems associated. with crosstalk.
Unfortunately, a drawback with this technique is the possibility of a two step signal appearing when the driven inputs are
far from the end of the transmission line. To avoid this
problem the distance between the end of the transmission
line and input gates should adhere to the guidelines specified in Table 3.3 from the section on unterminated lines.

(eqt. 24)

where:
'LOUT = (-1660mV - VTT)/(SQ + RT)
SIP Resistors
The choice of resistor type for use as the termination
resistor has several a!ternatives. Although the use of a
discrete, preferably chip resistor, offers the best isolation
and lowest parasitic additions there are SIP resistor packs
which will work fine for ECLinPS designs. SIP resistors offer
a level of density which is impossible to obtain using their
discrete counterparts. However, there are some guidelines
which the user should follow when using SIP resistor packs.
Always terminate complimentary outputs in the same pack
to minimize inductance effects on the SIP power pin. Noise
generated on this pin will couple directly into all of the
resistors in the pack. In addition, the SIP package should
incorporate bypass capacitors in the design (Figure 3.17).
These capacitors are necessary to help maintain a solid VTT
level within the package, again mitigating any potential
crosstalk or feedthrough effects. A 10 pin SIP like the DALE
CSRC-1 OB21-500J/1 03M, is suitable for providing 50Q terminations while maintaining a relatively noise free environment to non-switching inputs.

Series Termination Theory
When the output of the series terminated driver gate
switches, a change in voltage(d V B) occurs at the input to the
transmission line:.
(eql. 25)
where:.
V,N = Internal Voltage Change
Za = Line Characteristic Impedance
Rs = Output Impedance of the Driver Gate
RST = Termination Resistance
Since Zo = RST + Rs substitution into Equation 25 yields:
(eqt. 26)
From Equation 26 an incident wave of half amplitude propagates down the transmission line. Since the transmission
line is unterminated at the receiving end, the reflection
coefficient at the load is approximately unity; therefore the
reflection causes the voltage to double at the receiving end.
When the reflected wave arrives at the source end its energy
is absorbed by the series resistance producing no further
rellections as the impedance is equal to the characteristic
impedance of the line.
A extension of the series termination technique using
parallel fanout eliminates the problem of lumped loading at
the expense of extra transmission lines (Figure 3.19).

Figure 3.17 - Standard Eel 10 pin SIP
Series Termination Technique
Series Damping is a technique in which a termination
resistance is placed between the driver and the transmission
line with no termination resistance placed at the receiving
end of the line (Figure 3.1S).
Series Termination is a special case of series damping
in which the sum of the termination resistor (RST ) and the
output impedance of the driving gate (Ra) is equal to the line
characteristic impedance.

STn

D-

R
~"")---Z-O-~

n ( total number of lines)

Figure 3.18 - Series Termination

Figure 3.19 - Parallel Fanout using Series Termination

ECLinPS

4-26

System Interconnect
Calculation of RE

For the 1DE series

RE functions to establish VOH and VOL levels and to
provide the negative going drive into RST and Zo when the
driver output switches to the low state. The value of RE must
be such that the required current is supplied to each transmission line while not allowing the output transistor to turn off
when switching from a high to a low state. An appropriate
model is to treatthe output emitter follower as a simple switch
( Figure 3.20 ).

VOH

= -0.9V, VSWING = 0.85V, VEE = -5.2V

[-0.9 - (-5.2)] / (RST + RE + Zo)

0.531 / Zo

For the lODE series:
VOH

= -0.955V, VSWING = 0.75,

VEE = -4.5V
(eql. 30)

Figure 3.19 showed a modification of the series termination scheme in which several series terminated lines are
driven by a single Eel gate. The principle concern when
applying this technique is to maintain the current in the
output emitter follower below the maximum rated value. The
value for RE can be calculated by viewing the circuit in terms
of conductances.

Figure 3.20 - Equivalent Circuit for RE Determination

The worst case scenario occurs when the driver output
emitter follower is cutoff during a negative going transition.
When this happens the switch can be considered opened,
and at the instant it opens the line characteristic impedance
behaves as a linear resistor returned to VOH' The model
becomes a simple series resistive network as shown in
Figure 3.21 .

GE > G, + G2 + ... + G,

(eql. 31)

For the 1DE series
1/ RE ~ 1/ (7.10"Z01 -Rsn ) +
1/( 7.10"Z02 - RST2 ) +
1 / ( 7.1 O"Zo, -RST' )

(eql. 32)
where n is the number of parallel circuits.
For the lODE series

Figure 3.21 - Equivalent Circuit with Output Cutoff

1 / RE ~ 1 / ( 6.56"Z01 -RST1 ) +
1 / ( 6.56"Z02 - RST2 ) +
1 / ( 6.56"Zo, -RST' )

The maximum current occurs at the instant the switch
opens and is given by Equation 27.

(eql. 27)
(eql. 33)

The initial current must be sufficient to generate a transient
voltage equal to half of the logic swing since the voltage at
the receiving end ofthe line doubles forthe series terminated
case. To insure the pull down current is large enough to
handle reflections caused by discontinuities and load capacitances the transient voltage is increased by 25%.
Therefore,
I'N'T = ( 1.25"VSWING/2 ) / Zo

where n is the number of parallel circuits.
When a series terminated line is driving more than a
single Eel load the issue of maximum number of loads must
be addressed. The factor limiting the number of loads is the
voltage drop across the termination resistor caused by the
input currents to the Eel loads when the loads are in the
quiescent high state. A good rule of thumb is to determine
if the loss in high state noise margin is acceptable. The loss
in noise margin is given by
NMLOSS = IT " (R ST + Ro)
(eql. 34)

(eql. 28)

To satisfy the initial constraints 1M AX> I'N'T

ECLinPS

4-27

System Interconnect
RO

is 150j.tA. Thus for the circuit shown in Figure 3.22 in which
three gate loads are present in a 50n environment the loss
in high state noise margin is calculated as:

RST
RE

NM LOSS = 3 • 150j.tA • 50n = 22.5mV

ECLinPS 1/0 SPICE Modeling Kit

VEE
Due to the heavier reliance on simulation tools for initial
prototyping, Motorola has put together a SPICE modeling kit
aimed at aiding the customer in modeling board interconnect
behavior. The kit includes representative drivers and receivers as well as the necessary SPICE model parameters. In
addition tips are provided for simulating a wide range of
output conditions. The kit, in conjunction with todays CAD
tools, can greatly simplify the design and characterization of
critical nets in a design. Anyone interested in obtaining a
copy is encouraged to contact an ECLinPS Application
Engineer.

Figure 3.22 - Noise Margin Loss Example

where:
IT = Sum of I'NH Currents
For the majority of devices in the ECLinPS family the
typical maximum value for quiescent high state input current

ECLinPS

4-28

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
DESIGN GUIDE

Interfacing

SECTION 4
Interfacing with ECLinPS

±200ps/ns gate-gain delay (delay vs input edge rate) can be
assumed or a more typical value of ±75ps/ns can be used.

Interfacing to Existing ECl Families
There currently exists two basic standards for high
performance ECl logic devices: 10KH and 100K. To maximize system flexibility each member of the ECLinPS family
is available in both of the existing ECl standards: 1OE series
devices are compatible with the MECl 10KH family; 100E
series devices are compatible with ECl lOOK.
The difference in the DC behavior of the outputs of the
two different standards necessitates caution when mixing
the two technologies into a single ended input design. As
illustrated in Figure 4.1 and Table 4.1, there is no problem
when a 1OKH device is used to drive a lOOK device, however
problems arise when the scenario is reversed.
For the case of a lOOK device driving a 1OKH device the
worst case noise margin is reduced to 35mV, a noise margin
which is unacceptable for most designs. Since the problems
of interfacing are an output tracking rate vs a Vee tracking
rate problem if the system uses only differential interconnect
between the two technologies there will be no loss of noise
margin and the design will operate as desired.
Fortunately the ECLinPS family, by offering devices in
both standards, allows the user to integrate higher performance technology into his design without having to battle
these interface problems.
Another area of concern when interfacing to older
slower logic families is the behavior of ECLinPS devices with
slower input edge rates. Typically, other than clock inputs,
the ECLinPS family will function properly for edge speeds of
up to 20ns. For edges significantly slower than 20nS the
Schmitt trigger circuit of Figure 4.2 can be used to sharpen
the edge rates reliably.
Obviously a very slow edge rate will amplify differences
in delay paths due to any offset of the Vee switching reference. This extra delay should be included in speed calculations of a design. For calculation purposes a worst case

lOOK Driving 10KH
-0.8

-1.0

-1.2

.l!!

-1.4

-1.6

-1.8

~C.

Temperature (OC)
10KH Driving lOOK
-0.8

-1.0

-1.2

-1.4

-1.6

Drvr> Rcvr

NM - High

NM-low

10KH> 10KH
10KH > lOOK
100K> lOOK
100K> 10KH

150mV
145mV
130mV
35m V

150mV
125mV
135mV
130mV

-1.8

Temperature (OC)
Table 4.1 - Worst-Case Noise Margins of a
Mixed 10KH and lOOK Design

Figure 4.1 -Interfacing 10KH ECl and lOOK ECl

ECLinPS
4-29

Interfacing
Clock inputs on flip flop devices in the ECLinPS family
are especially sensitive to slow edge rates. Flip flops have
been successfully clocked in a noise free bench setup
environment with edge rates of up to 20ns. However in ATE
systems where more noise is present clocking problems
arise with input edge rates of greater than 6 or 7ns. To ensure
reliable operation in a system with input clock edges slower
than 7ns it is recommended that the signals be buffered with
an ECLinPS buffer circuit (E122, E116, E101 etc) or, for
extreme conditions, the Schmitt trigger of Figure 4.2 to provide the gain necessary to sharpen the edges on the clock
pulse.

designer is using a GaAs device which produces these -.3V
signals in an ECLinPS design he contact a Motorola Applications Engineer to determine if the ECLinPS device being
driven will be susceptible to saturation.

ACCoupling
In some cases it may be necessary to interface an
ECLinPS design with a signal which lacks any DC offset. The
differential devices in the ECLinPS family are ideally suited
for this application. As pictured in Figure 4.3 the signal can
be AC coupled and biased around the VBB switching reference of the device. Note that this scheme only works for a
data stream with no DC bias, for data streams such as RZ or
unencoded NRZ DC restoration must be performed prior to
AC coupling it to an ECLinPS device.

o--J r------,:---j

OUT

.001I1F

4000

50Q

01~
50n

50n

Figure 4.2 - Schmitt Trigger w/100mV of Hysteresis
Figure 4.3 - AC Couple Circuit

Interfacing to TIL/CMOS Logic
To interface ECLinPS devices to TTL or CMOS subsystems there exists several new product offerings, as well as
several existing devices, in the MECl 1OKH family which are
ideally suited to the task. These translation devices are
specially suited for clock distribution, DRAM driving as well
as general purpose translation in both single supply and dual
supply environments.
In mixed technology environments it is recommended
that the noisy supplies of TTL and CMOS circuits be isolated
from the ECl supplies. This can be done either through
separate power planes in the board or a common plane with
isolated ECl. and TTL power sub-planes. The planes of
common voltages (ie. ECl Vee and TTL ground for split
supply systems or common Vee and ground for a single
supply system) should then be connected to a common
system ground or power supply through an appropriate edge
connector.

The 50n resistor of Figure 4.3 provides the termination
impedance while the VBB pin provides the DC offset. The
capacitor used to couple the signal must have an impedance
of «50n for all frequency components of the input signal.
Because large capacitors appear somewhat inductive at
high frequencies it may be necessary to use a small capacitor in parallel with a larger one to achieve satisfactory
operation. In addition it is important to bypass the VBB line
when used in this manner to minimize the noise coupled into
the device.
Because the AC signal is biased around VBB' the output
of the ECLinPS device when AC coupled will have a duty
cycle identical to the input. Thus this type of application is
ideal for transforming high frequency sinusoidal waveforms
from an oscillator into a square wave with a 50% duty cycle.
The E416 device is a specialized line receiver with a much
higher bandwidth than alternative ECLinPS devices, therefore for frequencies of >500MHz it is recommended that the
designer use this device.
The above mentioned scenario will work fine as long as
the input signal is present, however if the the inputs to the
AC coupled device are left open problems may occur. With
no input signal both inputs will go to VBB and an undefined
output, and perhaps an oscillating output, will result. If a
defined output is necessary for an open input scenario, the

InterfaCing to GaAs Logic
In general GaAs logic is designed to interface directly
with ECl, however in some instances the worst case VOH of
a GaAs output can go as high as -0.3V. An ECLinPS device,
depending on the input structure, may become saturated
when driven with a -0.3V signal. It is recommended that if the

ECLinPS
4-30

Interfacing
to generate a VBB reference with the necessary current sinking capability. A single gate configured in this way will source
or sink upto 1OmA without a significant shift in the generated
V BB level. If more current is needed several gates can be
connected in parallel to provide the extra drive capability .
Note that the circuit pictured in Figure 4.4 will result in
the Q outputs going high when the inputs are left open. If the
opposite is desired the resistor to Vee can be tied to the
inverting input and V BB to the non-inverting input.

2.SKU

0---1 f - - t - - - - j

OUT

.0011J.F

son

sou

Figure 4.4 - AC Couple Circuit with DC Offset
500

circuit of Figure 4.4 can be used. The resistor tree between
Vee and V BB creates an offset between the two inputs so that
if the driving signal is lost a stable defined output will occur.
Unfortunately this configuration will adversely affect the
duty cycle of the output. Depending on the frequency of the
output, the duty cycle will change due to the longer distance
to threshold on a rising edge as opposed to a falling edge.
With this in mind it becomes obvious that the smallest
feasible offset would be the best solution. For stability a
minimum of 25mV is recommended, however this will not
produce full ECl levels at the outputs of an E116 and thus
another differential gate should be used to further amplify the
Signal. The gain of the E4l6 on the other hand is sufficient
to produce acceptable levels at the outputs for DC input
voltage differences of 25mV. If a 150mV offset is used full
ECl levels will be seen at the outputs of the E 116 however
the price in duty cycle skew will be high. Of course if the
signal is divided after it is received the duty cycle will be
restored.
When using the circuit of Figure 4.4 care should be
taken to limit the current sunk by the VBB pin to a maximum
of O.5mA. To achieve an offset of greater than 25m V for the
circuit of Figure 4.4 the DC current will necessarily need to
be greater than O.5mA. To alleviate this dillema one of the
gates olthe E116 can be configured as pictured in Figure 4.5

Single Gate VBB Generator

Multiple Gate VBB Generator

Vn
Figure 4.5 - High Current V•• Generator

ECLinPS
4-31

MOTOROLA

SEMiCONDUCTOR . . . . . . . . . . . . . . . . . . . . . ..
DESIGN GUIDE

Package & Thermal

SECTIONS

Package and Thermal Information

Package Choice

and reel product. Therefore, to order the MC10Elll FN in
tape and reel the part number would become
MCl OElll FNR2.

ECLinPS is offered in the 28-lead plastic leaded chip
carrier (PLCC) package, a leaded surface mount IC package. The lead form is of the "J-Iead" type. For detailed
dimensions of the 28-lead PLCC refer to the package
description drawings at the end of this section.
The PLCC was selected as the optimum combination of
performance, physical size and thermal handling in a low
cost standard package. While more exotic packages existto
improve these qualities still further, the cost of these is
prohibitive for many applications.
The PLCC features considerably faster propagation
delay and reduced parasitics compared to a DIP package of
similar pin-count; two properties that make it eminently
suitable for very high performance logic.
The 28-lead PLCC for the ECLinPS family is available
in tape and reel form to further facilitate automatic pick and
place. The characteristics of the 28-lead PLCC reel are
described in Figure 5.1 below.

Reliability of Plastic Packages
Although today's plastic packages are as reliable as
ceramic packages under most environmental conditions, as
the junction temperature increases a failure mode unique to
plastic packages becomes a significant factor in the long
term reliability of the device.
Modern plastic package assembly utilizes gold wire
bonded to aluminum bonding pads throughout the electronics industry. As the temperature of the silicon Ounction
temperature) increases an intermetallic compound forms
between the gold and aluminum interface. This intermetallic
formation results in a significant increase in the impedance
of the wire bond and can lead to performance failure of the
affected pin. With this relationship between intermetallic
formation and junction temperature established it is incumbent on the designer to ensure that the junction temperature
for which a device will operate is consistent with the long term
reliability goals of the system.
Reliability studies were performed at elevated ambient
temperatures (125°C) from which an arrhenius equation
relating junction temperature to bond failure was established. The application of this equation yields the table of
Figure 5.2. This table relates the junction temperature of a
device in a plastic package to the continuous operating time
before 0.1% bond failure (1 failure per 1000 bonds)
ECLinPS devices are designed with chip power levels
that permit acceptable reliability levels, in most systems,
under the conventional 500lfpm (2.5m/s) airflow.

General Information
Reel Size:
13" (330mm)
Tape Width: 24mm
Units/Reel: 500

Mechanical Polarization

@EBEBEBEBEBEB

Bb3JB

View From
Tape Side

Thermal Management
As in any system, proper thermal management is essential to establish the appropriate trade-off between performance, denSity, reliability and cost. In particular, the
designer should be aware of the reliability implication of
continuously operating semiconductor devices at high junction temperatures.
The increasing popularity of surface mount devices
(SMD) is putting a greater emphasis on the need for better
thermal management of a system. This is due to the fact that
SMD packages generally require less board spacethantheir
through hole counterparts so that designs incorporating

Linear Direction of travel

Figure 5.1 - 28-Lead PLCC Tape & Reel Information

To order ECLinPS in tape and reel form a minimum
3000 piece order per device type is required. In addition
orders must be full reels or multiples of full reels as no partial
reels will be shipped. An R2 suffix has been established to
add to the end olthe part number to signify the desire for tape

ECLinPS
4-32

Package & Thermal
T = 6.376 x 10"' e

[~~;51i2:~J

towards smaller denser designs makes it incumbent on the
designer to provide for the removal of thermal energy from
the system. Users should be aware that they control many of
the variables which impact the junction temperatures and
thus to some extent the long term reliability of their designs.

Where:
T = Time to .1 % bond failure
Junction
Temp·ee)

Time (Hrs.)

Time (Yrs.)

80
90
100
110
120
130
140

1,032,200
419,300
178,700
79,600
37,000
17,800
8,900

117.8
47.9
20.4
9.1
4.2
2.0
1.0

Calculating Junction Temperature
The following equation can be used to estimate the
junction temperature of a device in a given environment:

TJ
TA
Po
e JA

Figure 5.2 - TJ vs Time to .1% Bond Failure

= Junction Temperature
= AmbientTemperature
= Power Dissipation
= Avg Pkg Thermal Resistance (Junction - Ambient)

The power dissipation factor is made up oftwo elements: the
internal gate power and the power associated with the output
terminations. Essentially the two contributors can be calculated separately, then added to give the total power dissipation for a device.
To calculate the power of the internal gates the user
simply multiplies the lEE of the device times VEE' Since lEE in
ECl is a constant parameter frequency need not be factored
into the calculations. A worst case or typical number for chip
power can be calculated by using either worst case or typical
data book values for the lEE and VEE of a device.
Next the power of the outputs needs to calculated so
that the total power dissipation for a device can be determined. The output power is dependent on the termination
resistance and the termination scheme used to pulldown the
outputs. The most typical termination scheme for ECLinPS
designs is a parallel termination into -2.0V. For this scheme
the following equation describes the power for a single
output of the device:

SMD technologies have a higher thermal density. To optimize the thermal management of a system it is imperative
that the user understand all of the variables which contribute
to the junction temperature of the device.
The variables involved in determining the junction
temperature of a device are both supplier and user defined.
The supplier through lead frame design, mold compounds,
die size and die attach can positively impact the thermal
resistance and thus the junction temperature of a device.
Motorola continually experiments with new package designs
and assembly techniques in an attempt to further enhance
the thermal performance of its products.
It can be argued that the user has the greatest control
of the variables which commonly impact the thermal per·
formance of a device. Ambient temperature, air flow and
related cooling techniques are the obvious user controlled
variables, however PCB substrate material, layout density,
size of the air-gap between the board and the package,
amount of exposed copper interconnect, use of thermallyconductive epoxies and number of boards in a box can all
have significant impacts on the thermal performance of a
system.
PCB substrates all have different thermal characteristics, these characteristics should be considered when exploring the PCB alternatives. The user should also account
for the different power dissipations of the different devices in
his system and space them on the PCB accordingly. In this
way the heat load is spread across a larger area and "hot
spots" do not appear in the layout. Copper interconnect
traces act as heat radiators therefore significant thermal
dissipation can be achieved through the addition of interconnect traces on the top layer of the board. Finally the use of
thermally conductive epoxies can accelerate the transfer of
heat from the device to the PCB where it can more easily be
passed to the ambient.
The advent of SMD packaging and the industry push

V OUT
RT

= V OH or VOL
= Termination Resistance

The power dissipated in the output of a device is dependent
on the duty cycle of that output. For an output terminated to
VTT the worst case situation would be if the output was in the
high state all of the time, for an output terminated to VEE the
low state will represent worst case. For single ended output
devices typically the power is calculated with the outputs in
the worst case and for a 50% duty cycle. For differential
outputs the power for a differential pair is constant since they
are always in complimentary states, therefore for a given
output the power will simply be the average of the high and
low state output powers. Figure 5.3 shows the various output
power levels for the different output types and conditions. In
addition the table includes power numbers for various other

ECLinPS
4-33

Package & Thermal
Output Power (mW)
Termination
Resistance

Differential Output

Single-ended Output
(50% Duty Cycle)

Single-ended Output
(Worst Case)

10E

100E

10E

lODE

10E

100E

SO to-2.0V
68 to-2.0V
100 to -2.0V

14.3
10.5
7.1

15.0
11.1
7.5

14.3
10.5
7.1

15.0
11.1
7.5

19.8
14.6
9.9

20.0
14.7
10.0

510 to-5.2V
330 to-S.2V
180 to-5.2V

9.7
15.0
27.S

9.8
15.1
27.8

9.7
15.0
27.5

9.8
15.1
27.8

11.8
18.3
33.5

11.7
18.0
33.1

510 to-4.5V
330 to-4.5V
180 to-4.SV

7.8
12.3
22.6

9.3
14.4
26.4

Figure 5.3 - Output Power for Various Termination Schemes
termination resistances and alternative termination schemes.
These numbers can be derived by determining the loUT and
V OUT for the different alternatives and applying the equation
above.
Now that the power dissipation of a device can be
calculated one needs to determine which level of the parameter ( ie. typical, max etc .. ) to use to estimate the long
term reliability of the system. Since this number is statistical
in nature simply applying the worst case numbers will be
overly pessimistic as these parameters vary statistically
themselves. It is not very likely, for instance, that every
device type will be operating at the maximum specified lEE
level. Assuming all worst case conditions can have a significant impact on the resulting junction temperature estimates
leading to erroneous conclusions about the reliability of the
design.

Another important parameter for calculating the junction temperature of a device is the junction-ambient thermal
resistance,ElJA , of the package. ElJA is expressed in °C per
watt (OCIW) and is used to determine the temperature elevation of the die Ounction) over the external package ambient
temperature. Standard lab measurements of this parameter
for the 28-lead PLCC yields the graph of figure 5.4.
An alternative calculation scheme forTJsubstitutes the
case temperature (Tc) and the junction-to-case (ElJc) thermal resistance for their ambient counterparts in the TJequation previously mentioned. The. ElJC for the 28-lead PLCC is
32°CIW. This parameter is measured by submerging the
device in a liquid bath and measuring the temperature of the
bath, therefore it represents an average case temperature.
Thedifficulty in using this method arises in the determination

80
70
60

...
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