1991_National_FDDI_Handbook 1991 National FDDI Handbook

User Manual: 1991_National_FDDI_Handbook

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FODI

DATABOOK
1991 Edition

FOOl Overview
DP83200 FOOl Chip Set
Development Support
Application Notes and System Briefs
Appendix/Physical Dimensions
iii

••
•

III

TRADEMARKS
Following is the most current list of National Semiconductor Corporation's trademarks and registered trademarks.
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ABELTM is a trademark of Data 1/0 Corporation.
GAL® is a registered trademark of Lattice Semiconductor.
IBM®, PC® and PC-AT c..>
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PLAYER
TTlSD

25

LBD+

CLKDET

24

LBD-

CRD EN

23

OSC FLTR+

DP83231

DATA+
DATA-

22

OSC FLTR-

TTL SO,

21

DIF AMP

ClK OET

TEST EN

10

20

OSC IN

AVec

11

19

OSC OUT

RXD :t

lBD :t,
ElB,

CRD EN

18
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TL/F/103B4-2

Order Number DP83231AV
See NS Package Number V28A
TL/F/10384-4

FIGURE 2-2. DP83231 Pinout

FIGURE 2-3. System Connection Diagram

2-7

....

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co

a.
C

3.0 Pin Descriptions
Symbol

Description

Pin No.

1/0

DATA + ,
DATA-

8,
9

I

DATA±: 4B/5B serial NRZI data inputs originating from a fiber optic receiver and presented for
the purpose of resynchronization and clock recovery: These differential100k ECl compatible
inputs are selected when the ElB input is at a logic low level.

lBD+,
lBD-

25,
24

I

loopback Data±: 4B/5B serial NRZI data inputs originating from a local PLAYER device and
presented for the purpose of station diagnostics. These differential 1Oak ECl compatible inputs
are selected when the ElB input is at a logic High level.

ElB

4

I

Enable loopback: TTL compatible input which selects between the DATA ± inputs or the lBD
± inputs. The lBD inputs are selected when the ElB" pin is at a logic High level and the DATA
inputs when at a logic low level.

ClKDET

6

0

Clock Detect: CMOS output used to indicate that the chip has detected the presence of a
continuous data frequency greater than 3.0 MHz. A logic High level on the output will indicate that
valid input data has been detected.

CRDEN

7

I

CRD Enable: TTL compatible input which directs the differential charge pump outputs to either
operate the crystal oscillator at the center of its operating range or to track out the VCO phase
errors in the second PlL. The CRD EN input will reset the ClK DET function and will force the
oscillator to the center of its operating range when at a logic lOW level and will allow normal Pll
tracking operation when at a logic High level. Deassertion of the CRD EN input will momentarily
stop the VCO.

OSCFlTR+,
OSCFlTR-

23,
22

0

Oscillator Filter ± : The differential charge pump up and down outputs which are part of the
second PlL. A three element filter should be connected to each of these pins which consists of
one capacitor in parallel with a resistor and another capacitor to ground. These outputs are driven
to their maximum upper operating level when the CRD EN pin is at a logic lOW level or when
valid data frequencies are not recognized at the data inputs.

DIFAMP
OUT

21

0

Differential Amplifier Output: The differential amplifier output associated with the second Pll
which is used to adjust the frequency of the external crystal.

OSC_IN,
OSC_OUT

20,
19

I

Oscillator Input and Output: The terminals for the crystal oscillator which require connection of
,
the crystal tank circuit, varactors, and capacitors.

RXC+,
RXC-

3,
2

0

Receive Clock: Differential 1OOK ECl receive clock outputs which operate at 125 MHz
synchronized to the selected inputs (NRZI DATA ± or lBD ±) when valid line state data is
present. When valid line state data is not present these outputs continue to operate at a nominal
frequency of 125 MHz ± 12 kHz. These outputs should be terminated externally with a
conventional ECl 500. equivalent load.

RXD+,
RXD-

27,
26

0

Receive Data: Differential 1OaK ECl received data outputs which provide a resynchronized
equivalent of the selected NRZI DATA or lBD inputs. The received data output transitions occur
concurrent with the falling edge of the RXC ± output. These outputs should be terminated
externally with a conventional ECl 500. equivalent load.

VCOFlTR

13

0

VCO Filter: low pass filter associated with the first PlL. A three element filter should be
connected to this pin which consists of one capaCitor in parallel with a resistor and another
capaCitor to ground.

SD+,
SD-

18,
17

I

Signal Detect: Differential inputs to a 1OaK ECl to TTL translator intended for conversion of the
fiber optiC receiver's ECl Signal detect to TTL for a player device. The inputs are used in the test
modes as inputs for single stepping and gating the VCO.

TTlSD

5

0

TTL Signal Detect: Intended to be a Signal detect output in TTL format for use by the PLAYER

chip.
TEST EN

10

DVcc

16

I

Test Enable: CMOS input which enables the test functions. This input must be at a logic low level
in normal operation.
Digital Vee: Positive power supply for most of the internal logic circuitry intended for + 5V
operation ± 5% relative to ground. Bypass capaCitors should be placed as close as possible
across the DVcc and DGND pins. DVcc, AVec and EXTVcc should be tied together through
chokes.

-"-

2-8

C

3.0 Pin Descriptions

"C

CO

(Continued)

W

I\)

Symbol

Pin No.

W
......

Description

I/O

EXTVee

28

External Vee: Positive power supply for all the input and output buffers intended for + 5V operation
± 10% relative to ground. Bypass capacitors should be placed as close as possible across the
EXTVee and EXTGND pins. DVee, AVec and EXTVee should be tied together at the device pins
through chokes.

DGND

15

Digital Ground: Power supply return for the internal circuitry. DGND. AGND and EXT GND pins
should be tied together.

EXTGND

1

External Ground: Power supply return for the input and output buffers. DGND, AGND and EXT GND
pins should be tied together.

AVec

11

Analog Vee: Positive power supply for the critical analog circuitry intended for + 5V operation ± 5 %
relative to ground. Bypass capacitors should be placed as close as possible across the AVec and
AGND pins. DVee, EXTVee and AVec should be tied together through chokes.

AGND

14

Analog Ground: Power supply return for the critical analog circuitry. DGND, EXTGND and AGND
pins should be tied together.

VCOBIAS

12

I

VCO Bias: TTL compatible input that sets the nominal frequency for the VCO by the selection of the
resistor value between this input and AVec. A 30 kD value for this resistor will provide nominally
125 M Hz on the RXC outputs.

4.0 Electrical Characteristics
ECL Signals
Output Current

4.1 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature

- 65°C to + 150°C

TTL Signals
Inputs
Outputs

-20 rnA

Supplies
EXTVee to EXTGND
DVeetoDGND
AVec to AGND

-0.5Vto +7V
-0.5Vto +7V
-0.5Vto +7V

ESD Susceptibility

5.5V
5.5V

2000V

4.2 RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

Min

Typ

Max

Units

4.75

5

5.25

V

VeetoGND

Power Supply

VIH

High Level
Input Voltage

TTL

2.0

ECl

Vee- 1.165

Vee - 0.880

low level
Input Voltage

TTL
Vee - 1.810

Vee - 1.475

IOH

High Level
Output Current

TTL Outputs
(Note 1)

-0.4

rnA

IOl

low Level
Output Current

TTL Outputs
(Note 1)

4.0

rnA

FVCO

VCO Frequency

Vil

ECL

FXTL

Crystal Frequency

TA

Operating Temperature

Note 1: TTL outputs include
Eel outputs include

V
0.8

250

MHz

10.416667
0

elK DET and TTLSD.
RXC± and RXD±.

2-9

25

V

MHz
70

°C

•

4.0 Electrical Characteristics (Continued)
4.3 DC ELECTRICAL CHARACTERISTICS
Symbol

Conditions

Parameter

VIC

Input Clamp Voltage

liN = 18mA

VOH

High Level
Output Voltage

TTL Outputs: IOH = -400/LA

VOL

Low Level
Output Voltage

ECL Outputs:
50n Load to Vee - 2V

Min

II

Max High Level
Input Current

TTL Inputs: VIN = 7V

IIH

High Level
Input Current

TTL Inputs: VIN = 2.7V

IlL

Low Level
Input Current

TTL Inputs: VIN = 0.4V

Ifilter

Charge Pump Current

Source

Units
V

VCC- 2

V
Vee - 880

mV

0.5

V

Vee - 1620

mV

100

/LA

-20

20

/LA

-20

20

/LA

-0.3

-0.7

mA

0.3

0.7

mA

-500

500

nA

Vee - 1025

TTL Outputs: IOL = 4 mA
ECL Outputs:
50n Load to Vee - 2V

Max
-1.5

Vee - 1810

Sink
TRI·STATE'"

Supply Current
180'
mA
ICC
'Includes 60 mA due to external EOl termination of two differential Signals.
For lOOk EOl output buffers, output levels are specHied as:
VOH--",ax = Vee - 0.88V
VOLmax = Vee - 1.62V
Since the outputs are differential, the average output level Is Vee - 1.25V. The test load per output is son at Vee - 2V. The external load current through this
50n resistor is thus:

Uoad = [(Vee - 1.25) - (Vee - 2)1/50A
= 0.015A
= 15 rnA
There are 2 pairs of differential EOl signals, so lhe total EOl current is 60 mA.
4.4 AC ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Conditions

Tl

Phase Difference

T2

RXC Pos. Pulse Width

(Note 1)

T3

CLKDETTime

CRD EN Neg. Pulse Width = 1 /Ls
(Valid DATA ± Present)

T4
Valid Data Time
CROEN = High
Note 1: These parameters are not tested, but are assured by correlation with characterization data.

2·10

Min

Max

Units

-2

2

ns

3

5

ns

100

/Ls

100

/Ls

,----------------------------------------------------------------------, c
~
4.0 Electrical Characteristics (Continued)
Co)

...

N

TYPICAL WAVEFORMS

Co)

RXD

RXC

/-T3
elK DET

DATA :t:

elK DET
TLlF/l0384-5

FIGURE 4-1. DP83231 Timing Waveforms
DATA

CD

CRD
EN

-----'

------------------------~

LJ
~

RXC

r

m
TEST
EN

or
DATA

RXC
DIF
AMF

fII

In lock
~\----------------________~ln~l~oc~k_
_ _ _ _ _ _ _ _r
\ Centor Tuning Vollago
TL/F/l0384-6

FIGURE 4-2. Typical Waveforms

2-11

~
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r----------------------------------------------------------------------------------------------,
4.0 Electrical Characteristics (Continued)

a.
Q

DATA

+ (Bit shift shown)

RXD +
RXC +
DATA +
1 __ 0
(Logic
Value) •

--r-

o
•

o

~

OP83231 Ganal1ltad
BR Capture Windows

Nominal
Window Cantor
/ .
(M.an Bit Position)

Window Truncation

Window Truncation
Id ••1 Window Width. tw

= Tvco = 8 ns - - - - i..
TLlF/l0384-7

FIGURE 4·3. Synchronization Window

iI ~~1

i1

7Pf

10kn

27pf

H

AGND

240 kn

GND

2.2kn

15pf

+5V

330pf

150pf

R=1.6Zo
OSC flTR
ClK

Olff.

OSC

AMP

OUT

ose veo
IN

R= 1.6Zo

_-+---+

flTR RXO+t---.....

DEl
R=2.6Zo

R=2.6Zo

TTLSD

ElB

DP83231
+5V

DATA :t

lBD i

R = 1.6 Io

R=1.6Io
SO i

EXT
DGND

GND

VCO
BIAS

AGNO

CRD
EN

---+

R X e : t - - - - t -....

R=2.6Io

R=2.6Io

Zo Is the line impedance

30kn
TLlF/l0384-8

All component values ± 5%.

FIGURE 4·4. General Wiring Diagram

2·12

r----------------------------------------------------------------------.c

;g

5.0 Detailed Information

Co)

Capacitance:

Crystals
C5400N

800A-A-10.41667-32

Frequency Calibration: ± 20 PPM
± 20 PPM

Aging:

<

Pull ability:

either a
;"0.021

• The crystal, asc FLTRs and the vca FLTA circuitries
should be connected to Ground on isolated branches off of
the DGND pin. If using a multilayered board with dedicated
Vee and Ground planes ensure that for the ground plane
that the ceramic resonator, asc FLTRs and the vca FLTR
circuitries have their own small isolated islands that are connected to the DGND and AGND pins as described above.

±10 PPM
motional

capacitance

of

or

• The DVee and AVec pins should be connected to Vee on
an isolated branches off of the EXTVee pin, preferably being connected through a ferrite bead or a small inductor.

a change of at least 100 PPM when
the CL is changed from 32 pF to 18 pF
and a change of -100 PPM when the
CL is changed from 32 pF to 50 pF.

• The DGND and AGND pins should be connected to GND
on an isolated branches off of the EXTGND pin. Connection
to the ground plane should be made only at the EXTGND
pin.

Varactors
• Manufacturer: Alpha Industries (617) 935-5150
Part#:

30 pF

• No TTL logic lines should pass through the crystal asc
FLTAs or vca FLTR circuitry areas to avoid the possibility
of noise due to crosstalk.

10.41667 MHz

Load Capacitance, CL: 32 pF
Frequency Stability
(0·C-70·C):

<

• The part should be bypassed between the EXTVee and
EXTGND as close to the chip as possible (preferably under
the chip using chip caps). The part should also be bypassed
between the DVee and DGND and the AVec and AGND as
close to the chip as possible.

Key Specifications:
Center Frequency:

Vr = 1V: C > 85 pF
Vr = 4V: 15 pF < C

5.2 LAYOUT RECOMMENDATIONS

• Manufacturer: Standard Crystal Corporation
(818) 443-2121
Part#:

Co)

@
@

• Manufacturer: Nel Frequency Controls (414) 763-3591
Part#:

N

....

Key Specifications:

5.1 SPECIAL EXTERNAL COMPONENTS

DKV651 0-71

Connection to Ground
plane or exlernal Ground

Conneclion 10 Vee
plane or exlernal Vee

Analog Area
do not route
TIL Logic
signals Ihrough
Ihls area.

4

1\

Analog :e: :o-n:1

~O~I:

- - - - - - - •

TIL Logic signals Ihrough
Ihls area.
TL/F/l03B4-10

This drawing was done with convenience in mind.

FIGURE 5-1. Recommended Layout

2-13

•

....
('I)

~

CD
~

5.0 Detailed Information

(Continued)

5.3 INPUT AND OUTPUT SCHEMATICS

SD±
-

DATA±,LBD±

,---....--ovcc

.....- - . - -.....- - - D VCC

DGND
DGND

-=

TlIF/l0S84-12

Tl/F/l0S84-11

DIFAMP

OSCFLTR

osc
FLTR
TLlF/l0S84-1S

Tl/F/l0384-14

VCOFLTR

OSCIN,OSCOUT

. . . - - - - -....- - - D VCC

p---veo
FLTR

DGND
TL/F/l0S84-15

TlIF/l0S84-16

2-14

5.0 Detailed Information

(Continued)

5.3 INPUT AND OUTPUT SCHEMATICS (Continued)

CRDEN,ElB
DVcc -

TEST EN

....- - -....- - - -

DVcc

DGND _
TL/F/103B4-17

DGND
TL/F/10384-1B

RXC±,RXD±

ClK DET, TTlSD

EXTVCC

DVcc

RXC+. RXC-.
RXD+, RXD-

CLK DET,
TTLSD

TLlF/103B4-19

DGND
TL/F/103B4-20

Typical ESD Structure

TLlF/103B4-21

2-15

_ r------------------------------------------------------------------------------

C")

~

D-

C

5.0 Detailed Information

(Continued)

5.4 DEBUG PROCEDURE

from the nominal value dependent on temperature and data
rate frequency error. If this pin is oscillating then the OSC
FLTR pins are unstable and the filters should be examined
for possible PC board shorts, opens or instability. If the OIF
AMP pin is near ground then check to see if the ELB input is
selecting the correct data input. If the OIF AMP pin continues to be near ground or Vee, then the accuracy of the 62.5
MHz source should be examined to verify it is within the ± 3
KHz (50 PPM) FOOl system data rate specification.

Evaluation of the OP83231 should begin by tying the CRO
EN and TEST EN pins low and confirming that the SO ±
pins are above 2V. This will disable the differential phase
comparator allowing the crystal resonator to run at its center
frequency and will keep the part out of a test mode. The first
PLL (see Figure 5-2) should be evaluated. The variable capacitor in the crystal resonator circuitry should be tuned so
that the crystal resonator oscillates at 10.41666 MHz. If the
oscillator circuit fails to oscillate the voltage levels of the
OSC IN and OSC OUT pins should be examined. The DC
voltage on these pins should be equal to approximately
Vee + 2 (with or without the crystal present). The capacitors which form the oscillator tank circuit should be returned
to the isolated ground branch in close proximity. After
checking the crystal frequency, examine the RXC ± output
and verify that this frequency is twelve times the crystal frequency. If this is not true then the VCO FLTR output should
be examined for possible PC board shorts, opens or filter
instability. The VCO FLTR pin should be stable at approximately a 1.5V DC level in operation.

OSC OSC
In Out

If the VCO FLTR pin is oscillating then the loop filter components for this pin were either chosen inappropriately or were
placed in the incorrect position.
Once it is known that the first PLL is working, force CRO EN
high and input a constant 62.5 MHz ± 50 ppm (1T pattern)
data stream to the OATA± inputs (see Agure 5-3). To see
how well the second loop is working examine the OIF AMP
pin. If the incoming data rate is exactly 62.5 MHz and the
crystal resonator was accurately adjusted as described
above, then the OIF AMP pin voltage should be stable at
approximately 2.25V. The voltage at this pin will vary

FLTR

Test
EN
TUF/l03B4-22

FIGURE 5-2. 1st PLL

CRD
EN
Data

VCO

RXC:t _ _...;:a,...

OSC

FLTR

+

Dill
Amp

:t
Sync

LBO :t

and

Delay Line

ELB--.....I

1-_ _ _...

RXD :t -~;.J....- - - - I
Slmpllfled
R~:t_~~+---------~--------------------i

1st PLL

(VCO)
TUF/l03B4-23

FIGURE 5·3. 2nd PLL

2-16

r----------------------------------------------------------------------.c
5.0 Detailed Information

"'U

~

(Continued)

N

....

5.5 AC TEST CIRCUITS

(0)

5V

-.1.0 kll

TLlF/l03B4-25

FIGURE 5·5. Switching Test Circuit
for All ECl Input and Output Signals
TLlF/l03B4-24

FIGURE 5·4. Switching Test Circuit
for All TTL Output Signals

fII

2·17

~National

~ Semiconductor

DP83241 CDDTM Device
(FDDI Clock Distribution Device)
General Description

Features

The COD device is a clock generation and distribution device intended for use in FOOl (Fiber Distributed Data Interface) networks. The device provides the complete set of
clocks required to convert byte wide data to serial format for
fiber medium transmission and to move byte wide data between the PLAYERTM and BMACTM devices in various station configurations. 12.5 MHz and 125 MHz differential ECl
clocks are generated for the conversion of data to serial
format and 12.5 MHz and 25 MHz TTL clocks are generated
for the byte wide data transfers.

• Provides 12.5 MHz and 25 MHz TTL clocks
• 12.5 MHz and 125 MHz ECl clocks
• 5 phase TTL local byte clocks eliminate clock
skew problems in concentrators
• Intemal VCO requires no varactors. coils or
adjustments
• Option for use of High Q external VCO
• 125 MHz clock generated from a 12.5 MHz crystal
• External Pll synchronizing reference for
concentrator configurations
• 28-pin PlCC package
• BiCMOS processing
TO HOST SYSTEM

DP83231
CRD
(CLOCK
RECOVERy)

~
TO FIBER OPTIC
TRANSCEIVER PAIR

FIGURE 1-1. FOOl Chip Set Block Diagram

2-18

TLlF/10385-1

~--------------------------------------------------~c

Table of Contents
1.0 FOOl CHIP SET OVERVIEW

5.0 DETAILED INFORMATION

~

Co)

~

....

5.1 External Components

2.0 FUNCTIONAL DESCRIPTION

5.2 Concentrator and Dual Attach Station Configurations

3.0 PIN DESCRIPTIONS

5.3 Layout Recommendations

4.0 ELECTRICAL CHARACTERISTICS

5.4 Input and Output Schematics

4.1 Absolute Maximum Ratings

5.5 System Debugging Flowchart

4.2 Recommended Operating Conditions

5.6 AC Test Circuits

4.3 DC Electrical Characteristics
4.4 AC Electrical Characteristics

•
2·19

_

"1:1'

N

CO)

co

a.
C

r---------------------------------------------------------------------~

DP83261 BMACTM Device
Media Access Controller

1.0 FDDI Chip Set Overview
National Semiconductor's FDDI chip set consists of five
components as shown in Figure 1-1. For more information
about the other devices in the chip set, consult the appropriate data sheets and application notes.

The BMAC device implements the Timed Token Media Access Control protocol defined by the ANSI FDDI X3T9.5
MAC Standard.

DP83231 CRDTM Device
Clock Recovery Device

Features
• All of the standard defined ring service options
• Full duplex operation with through parity
• Supports all FOOl Ring Scheduling Classes (Synchronous, Asynchronous, etc.)

The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream.

Features

• Supports Individual, Group, Short, Long, and External
Addressing

• PHY Layer loopback test
• Crystal controlled
• Clock locks in less than 85

• Generates Beacon, Claim, and Void frames internally

'""S

• Extensive ring and station statistics gathering

DP83241 CDDTM Device
Clock Distribution Device

• Extensions for MAC level bridging
• Separate management port that is used to configure and
control operation

From a 12.5 MHz reference, the Clock Distribution Device
synthesizes the 125 MHz, 25 MHz and 12.5 MHz clocks
required by the BSI, BMAC, and PLAYER devices.

• Multi-frame streaming interface

DP83265 BSITM Device
System Interface

DP83251/55 PLAYERTM Device
Physical Layer Controller

The BSI Device implements an interface between the National FDDI BMAC device and a host system.

The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9.5 Standard.

Features
• 32-bit wide Address/Data path with byte parity
• Programmable transfer burst sizes of 4 or 8 32-bit words
• Interfaces to low-cost DRAMs or directly to system bus

Features
• 4B/5B encoders and decoders

• Provides 2 Output and 3 Input Channels

• Framing logic
• Elasticity Buffer, Repeat Filter, and Smoother

• Supports Headerllnfo splitting
• Efficient data structures

• Line state detector/generator

• Programmable Big or Little Endian alignment
• Full Duplex data path allows transmission to self
• Comfirmation status batching services

• Link error detector
• Configuration switch
• Full duplex operation
• Separate management port that is used to configure and
control operation.

• Receive frame filtering services
• Operates from 12.5 MHz to 25 MHz synchronously with
host system

In addition, the DP83255 contains an additional
PHY_Data. request and PHY_Data.indicate port required
for concentration and dual attach stations.

2-20

2.0 Functional Description
The CDD device clocks are all generated from and phase
aligned to either a 12.5 MHz crystal oscillator or a TTL input
reference source using digital phase locked loop techniques. The architecture of the Clock Distribution Device ensures that the output clocks which are generated have frequency tolerances identical to the 50 PPM crystal reference.
When the reference input signal is a backplane signal, the
matching of the phase comparator input path delays guarantees phase alignment within 3 ns.
The phase locked loop generates the desired clocks as
shown in the device Block Diagram. One of the local By1e
Clock (lBC) phases is connected to the FEEDBK IN input of
the phase comparator where its phase and frequency are
compared against that of the selected input reference signal. Any phase error between these signals results in a correction of the voltage into the Voltage Controlled Oscillator
(VCO) which is proportional to the amount of phase error.
The correction voltage tends to drive the frequency of the
VCO in the direction which, when divided down, minimizes
the lBC to reference signal phase difference. When the
phase transition of the lBC occurs before that of the reference input the VCO frequency is sensed as being too fast
and produces a negative going correction to the VCO input.
This in turn slows down the VCO's frequency and delays the
subsequent lBC phase transitions.
The device's differential 125 MHz ECl transmit clock and
differential 12.5 MHz ECl load strobe are used by the
PLAYER device to convert data from by1e wide NRZ format
to serial NRZi format for fiber medium transmission. A
12.5 MHz TTL local by1e clock is provided for use by the
PLAYER and the BMAC devices. Five phases of the local
by1e clock are provided for use in large multi-board concentrator configurations to aid in cancelling out backplane delays. A 25 MHz local Symbol Clock (lSC) is provided which
is in phase with the local by1e clocks and has a 40% HIGH
and 60% lOW duty cycle.

mon reference signal. The VCO SEl input provides the option to use the internally provided VCO or an external lC
voltage controlled oscillator. Although the stability of the internal VCO should be adequate for most applications the
external VCO option provides the means of obtaining the
maximum possible oscillator Q. The PHASE SEl input pin
provides the option of selecting whether the five phase lBC
outputs are phase offset 36 degrees or 72 degrees (8 ns or
16 ns).
The phase locked loop (Pll) elements, with the exception
of the loop filter which consist of two capacitors and a resistor, are fully contained within the device. The internal VCO
associated with the Pll has been implemented totally within the device and requires no external lC oscillator tank
coils, capacitors, or varactors. The external VCO option
does provide a means of using these conventional lC oscillator techniques if desired.

Connection Diagram
28-Pin PlCC Package

REFIN

5

LBCI

XTLOUT

LBC2

NC

LBC3
DPB3241B

XTtIN
REFSEL

LBC4
LBC5

FILTER

10

LSC

VCORST

11

PHASESEL

TLlF/l0385-25

The device provides three user-selectable features. The
REF SEl input provides the option to lock the device's outputs to a crystal oscillator or to an external TTL signal (REF
IN). The REF IN signal is particularly useful in concentrators
where multiple boards need to be phase locked to a com-

Order Number DP83241BV
See NS Package Number V28A
FIGURE 2-1. DP83241 Pinout

Block Diagram
XTL IN

XTL OUT

REF SEL

INT
Vee

EXT
Vee

INT
GND

EXT
GND

SUB
GND

...L...L...L...L...L
- - -

- - -

REF IN

FILTER

FEEDBK IN
VCO RST
PHASE SEL

II

LSC
XVCO IN
XVCO INB
veo SEL

LBC5

LBC4

LBC5

LBC2

LOCI TBC TBC TXC TXC

+ -

+ -

FIGURE 2-2. DP83241 Block Diagram
2-21

TLlF/l0385-3

3.0 Pin Descriptions
Symbol

Pin
No.

Desc'riptlon

110

DVee

16

Digital Vee: Positive power supply for all the internal circuitry intended for operation at 5V ± 5% relative
to GND. A bypass capacitor should be placed as close as possible across the DVee and DGND pins.

EXTVcc

28

External Vee: Positive power supply for all the output buffers intended for operation at 5V ± 5% relative
to GND. A bypass capacitor should be placed as close as possible across the EXTVee and EXTGND
pins.

DGND

15

Digital Ground: Internal circuit power supply return.

EXTGND

1

External Ground: Output buffer power supply return.

AGND

14

Analog Ground: Substrate ground used to ensure proper device biasing and isolation.

AVee

18

Analog Vee: Positive power supply for the critical analog circuitry, intended for + 5V operation ± 5%
relative to Ground. A bypass cap should be placed as close as possible between AVee and AGND.

XTLIN

B

XTLOUT

6

REF IN

I

External Crystal Oscillator Input: XTL IN can also be used as a CMOS compatible reference frequency
input for the PLL. This input is selected when REF SEL is at a logical LOW level. The component
connections required for oscillator operation are shown in the application diagrams.

5

I

Reference Input: TTL compatible input for use as the PLL's phase comparator reference frequency
input when the REF SEL is at a logic HI level. This input is for use in concentrator configurations where
there are multiple CDD devices at a given site requiring synchronization.

FEEDBKIN

4

I

Feedback Input: TTL compatible input for use as the PLL's phase comparator feedback input to close
the loop. This input is intended to be driven from one of the LBCs (Local Byte Clocks). This input is
designed to provide the same frequency and within 2 ns of the same phase as REF IN when REF IN is in
active operation.

REFSEL

9

I

Reference Select: TTL compatible input which selects either the crystal oscillator inputs XTL IN and
XTL OUT or the REF IN inputs as the reference frequency inputs for the PLL. The crystal oscillator inputs
are selected when REF SEL is at a logic LOW level and the REF IN input is selected as the reference
frequency when REF SEL is at a logic HI level.

FILTER

10

a

Filter: Low pass PLL loop filter pin. A three element filter, consisting of one capacitor in parallel with a
resistor and another capacitor, should be connected between this pin and ground.

VCOSEL

17

I

VCO Select: TTL compatible input used to select either the internal VCO or an external VCO through the
XVCO IN and XVCO INB pins. The internal VCO is selected when the VCO SEL pin is at a logic HIGH
level and the external veo is selected when at a logic LOW level.

XVCOIN,
XVCOINB

13,
12

I

External VCO Inputs: Differential inputs for use with an external VCO. These inputs are D.C. biased to
approximately one half Vee, and can be connected to either a full differential VCO, or a single-ended
VCO. To use a Single-ended VCO, couple the signal into one of the inputs through a series low value
capacitor and bypass the other input to GND through a 0.01 p.F capacitor. When not in use, ground one
input, and let the other float.

External Crystal Oscillator Output: XTL OUT is not intended for use as a logic drive output pin.

2-22

3.0 Pin Descriptions (Continued)
Pin
No.

110

VCORST

11

I

VCO Reset: TTL compatible input used to reset the internal VCO on system power up. This input
stops the VCO from oscillating when at a logic HI level thereby reinitializing each of the gates in
the ring oscillator.

TXC+.
TXC-

3.
2

a

Transmit Clock: lOOK ECL compatible differential outputs for use at 125 MHz as the fiber
medium Transmit Clock (TXC) source for the PLAYER device.

TBC+,
TBC-

27,
26

a

Transmit Byte Clock: lOOK ECL compatible differential outputs for use at 12.5 MHz as a load
strobe or transmit byte clock by the PLAYER device to convert byte wide data to serial format for
fiber medium transmission. These outputs are positioned to transition on the falling edge of the
TXC + clock output to provide the maximum setup and hold margin. They are also phase
coherent with the TTL LBCl output, but the phase transition occurs approximately IOns earlier.

25,24,
23,22,21

a

Local Byte Clocks: TTL compatible local byte clock outputs which are phase locked to crystal
oscillator reference signals. These outputs have a 50% duty cycle waveform at 12.5 MHz. The
PHASE SEL input determines whether the five phase outputs are phase offset by 8 ns or 16 ns.

LSC

20

a

Local Symbol Clock: TTL compatible 25 MHz output for driving the BMAC device. This output's
negative phase transition is aligned with the LBCl output transitions and has a 40% HI and 60%
LOW duty cycle.

PHASESEL

19

I

Phase Select: TTL compatible input used to select either a 8 ns or 16 ns phase offset between
the 5 local byte clocks. The LBC's are phase offset 8 ns apart when PHASE SEL is at a logic LOW
level and 16 ns apart when at a logic HI level.

Symbol

LBCl thru 5

Description

fII

2-23

4.0 Electrical Characteristics
4.1 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
- 65·C to + 150·C
Storage Temperature
TIL Signals
Inputs
-0.5Vto +5.5V
Outputs
-0.5Vto +5.5V

ECL Signals
Output Current
Supplies
EXTVee to EXTGND
DVeetoDGND
AVeeto AGND
ESD Protection

-50mA
-0.5Vto +7V
-0.5Vto +7V
-0.5Vto +7V
1500V

4.2 RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Units

4.75

5.0

5.25

V

Parameter

VeetoGND

Power Supply

VIH

High Level Input Voltage
Low Level Input Voltage

Vil

TTL

2.0

ECL

Vee - 1.165

Vee - 0.880

Vee - 1.810

Vee -1.475

V

TTL

0.8

ECl

V

IOH

High level
Output Current

TTL Outputs
(Note 1)

-0.4

mA

IOl

low level
Output Current

TTL Outputs
(Note 1)

8.0

mA

Fveo

VCO Frequency (lNT or EXT)

250

FREF

Reference Input Frequency

12.5

Operating Temperature
TA
Note 1: TTL outputs Include lBC1, lBC2, lBC3, lBC4, lBe5 and lSC.

0

25

MHz
MHz
70

·C

Max

Units

-1.5

V

4.3 DC ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Conditions

Min

= 18mA

Vie

Input Clamp Voltage

liN

VOH

High level
Output Voltage

TTL Outputs: IOH

= -400/LA

EClOutputs:
50n load to Vee - 2V

V

Vee - 2
Vee -1025

= 8 mA

Vee - 880

mV

0.5

V

Vee - 1620

mV

100

/LA
/LA

low level
Output Voltage

TTL Outputs: IOl

II

Max High level
Input Current

TTL Inputs: VIN

= 7V

IIH

High level
Input Current

TTL Inputs: VIN

= 2.7V

-20

20

III

low level
Input Current

TTL Inputs: VIN

= 0.4V

-20

20

/LA

IFilter

Charge Pump Current

Source

-0.7

+0.7

mA

0.2

0.7

mA

-250

250

nA

VOL

EClOutputs:
50n load to Vee - 2V

Sink
TRI·STATEIID

Vee - 1810

mA
Supply Current
170'
lee
'Includes 60 mA due to external ECl termination of two differential signals.
For tOOk ECl output buffers, output levels are specified as:
VOH-Max ~ Vee - O.BBV
VOL~ax ~ Vee - 1.62V
Since the outputs are differential, the average output level is Vee - 1.25V. The test load per output is son at Vee - 2V. The extemalload current through this
500. resistor is thus:

I_load

[(Vee - 1.25) - (Vee - 2)]/50 Amps
0.015 Amps
~ 15mA
There are 2 pairs of differential ECl Signals, so the total ECl current is 60 mAo
~

~

2·24

C

"U

4.0 Electrical Characteristics (Continued)

co
Co)

N

4.4 AC ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Tl

TBCtoTXC

T2

TBCto LBCl

TPhase1

LBCl toLBC2

TPhase2

Conditions

LBCl toLBC4

TPhase4

LBCl to LBC5

Max

Units

-1.5

1.5

ns

10

20

ns

PHASE SEL = Low

3

13

ns

PHASE SEL = High

43

53

ns
ns

(Note 1)

LBCl to LBC3

TPhase3

Min

PHASE SEL = Low

11

21

PHASE SEL = High

11

21

ns

PHASE SEL = Low

19

29

ns

PHASE SEL = High

59

69

ns

PHASE SEL = Low

27

37

ns

PHASE SEL = High

27

37

ns

T3

LSCtoLBCl

-4

6

ns

T4

LSC Positive Pulse Width

12

19

ns

T5

REF IN to FEEDBK IN

In Lock (Note 1)

-3

3

ns

T6

TXC Positive Pulse Width

(Note 1)

3.5

4.5

ns

T7

LBC Positive Pulse Width

35

45

ns

.....
""'"

Note 1: These parameters are not tested, but are assured by correlation with characterization data.

r4~r;;;;.,-...

TXC

.....T6

... ~~

TBC 50"

• ••

I-T2

LBCl

--~~,

1.5V-'!\
'--~---

~

,r------

.....
1.5V..., ....

....

LBC2-5

50"2
T

... - - - - - - '

..... Tphasel-4

i-

Tphasel-4 ...

-'\"1.5V

~C ,,,~ D-~ .'\o~-~-V---··· -l--r-4-+.-·. .

1.5V7~

T3- . 1

REf IN

FEEDBK IN

,,,{~

f
TL/F/l038S-4

FIGURE 4-1. AC Timing Waveforms

2-25

fII

_ r----------------------------------------------------------------------,

'OS'

C'I)

4.0 Electrical Characteristics (Continued)

a.

4.4 AC ELECTRICAL CHARACTERISTICS (Continued)

N

co

Q

TXC

TBC

j

LBC1

J

LBC2

~

I

LBC3

-_

.......

PHASE SEL
IS LOW

LBC4 ...;._ _ _~

L

LBCS ......_ _ _ _~

LSC

LBC1

J

LBC3

-+-_.......

L

LBCS _ _ _ _ _.....

PHASE SEL
IS HIGH

I

LBC2 -;--,..._ _ _ _ _...

'--__

LBC4

~I
TLlF/10385-5

FIGURE 4-2. Typical Clock Relationships

2-26

Loop Filter Calculations
Let us now design an example system with the following
characteristics:

Several constants need to be known in order to determine
the loop filter components. They are the loop divide ratio, N,
the phase detector gain, Kp, the vce gain, Ko, the loop
bandwidth, Wo, and the phase margin, cp. The constants Kp
and Ko for the DP83241 are fixed at 80 ",Alrad and 0.8
GradlV respectively. N is equal to the vce frequency divided by the reference frequency. Wo is recommended to be
less than 1/20th of the reference frequency (times 21T
rads). Having found all these constants, the following equations are used to find the component values:
For cp = 57' phase margin:

• 12.5 MHz Crystal reference.
• 250 MHz vce.
Since the vce is twenty times the frequency of the reference frequency, we get N = 20. We will set Wo to be 1/30th
of the reference frequency or 2.62 x 106 Rad.
From these values we get:
Cl = 1400 pF, C2 = 140 pF, and Rl = 9000.
Let us now design an example system with the following
characteristics:

Rl = (1.1 N wo)/(Kp Ko)
Cl = (3 Kp Ko)/(N wo2)
C2 = (0.3 Kp Ko(l(N wo2)
For a phase margin other than 57':
Rl = (Cosec cp + 1)((N wo/2 Kp Ko))
Cl = (Tan cp) ((2 Kp Ko)/(N wo2))
C2 = (Sec cp - Tan cp) ((Kp Ko/(N wo2))

• 12.5 MHz Crystal reference.
• 250 MHz External vee with a gain of 40 MRadlV.
We will set Wo to be 1/78th of the reference frequency or
1.0 x 106 Rad.
From these values we get:
Cl = 470 pF, C2 = 47 pF, and Rl = 6.8 kn.
FILTER PIN

The component equations above are not meant to provide
optimal solutions for all implementations.

::0
TL/F/l0365-27

2-27

.....
..,.
~

CD
~

5.0 Detailed Information
5.1 EXTERNAL COMPONENTS

.-_-----+--.

DGNO

9104
+5V
1000pr

veo
RST

LSC

R=I.6Zo

R= 1.6 Zo

R=2.6Zo

R=2.6Zo

TXC~

+5V
PHASE SEL
veo SEL

-

DP83241

+5V

REr SEL

GNO

EXT

LBC2-

GNO

LaC5

LBCI

FE£OBK
IN

R= 1.6Zo

R=I.6Zo

R=2.6Z0

R=2.6Zo

TBC~

-

Zo Is the line Impedance

TLIFII0385-6

The Filter components are based on a 12.5 MHz Crystal and a 250 MHz VCO.
All component values ± I 0%.

FIGURE 5·1. General Wiring Diagram

6.8K
470pr
+5V

DGNO

24pr

+5V

47pr
5104
tOKQ

+5V

i--L----.J=~~:1.----.!.--.l---.,
XTL OUT
XTL IN
LSC

R= 1.6Zo
R= 1.6Zo

R=2.6Zo

R=2.6Zo

+5V

R= t.6Zo

R=I.6Zo

R=2.6Zo

R=2.6Zo

Zo Is the lint Impedance

The Filter components are based on a 12.5 MHz Crystal and an external 250 MHz VCO with a gain of 40 MRadlV.
All component values ±10%.

FIGURE 5·2. General Wiring Diagram with an External VCO

2·28

TLlF110385-7

r-----------------------------------------------------------~c

"'U
CD

5.0 Detailed Information (Continued)

Co)
I\)

0l:Io
.....

TABLE 5·1. Special External Components
Crystal Resonator:

Part #:
Manufacturer:
Key Specifications:

C5410N
NEL
12.5000 MHz Center Frequency,
20 PPM Accuracy, O·C to + 70·C
15 pF Load Capacitance

Varactor Diode:

Part#:
Manufacturer:
Key Specifications:

MV21 05
Motorola
Cap Tolerance ± 10%

VHF NPN Transistor:

Part#:
Manufacturer:
Key Specifications:

PN3563
National Semiconductor

Inductor.

Part#:
Manufacturer:
Key Specifications:

5.2 CONCENTRATOR AND DUAL ATTACH STATION
CONFIGURATIONS

period and the skew between the COD devices on the two
boards is minimal. In a larger concentrator configuration
where this skew becomes too large, the data setup time of
the downstream station will be directly impacted. One way
to avoid this problem is to latch data into the next station.
The strobe for the latch will be supplied by one of the LBC
outputs from the upstream station's CDO device. An LBC
output phase is chosen that occurs after the physical layer
data is stable. Assuming that the data and LBC flight times
are equal, the LBC output will latch data for the next station.
The LBC output phase should be selected to give the optimum setup and hold time for the receiving station's physical
layer function.

5.2.1 Concentrator Applications
An application where many of the features of the COD de·
vice are used is a FOOl concentrator. A concentrator is
used to connect several workstations and peripherals to a
Single node in the network. A concentrator provides the ability to easily bypass or insert multiple stations into the network. The COO device in each station is driven from a common oscillator instead of each COD device being driven by
its own crystal. In a small concentrator, the same LBC
phase can be used in each station since the data flight time
from one board to another is small compared to the LBC

--

--- -

- - -- -- - -

~7 ~~

1

PHY

1% Turns

~7 J.~

J

I

PHY

I

COO

~~

I

.-- - - -I
I
I
I

~7

1

J.),

PHY

J

jlOCI
lOCI

1

COD

J+-

1+

I OscillatorJ -

lOCI

1

coo

---.. ;;:st~;-----TLlF/l0385-8

FIGURE 5-3. Small Concentrator Application

fII

2-29

5.0 Detailed Information (Continued)

LBC1

----------------Master

----------------_.
Board 1

-----------Board N
TLlF/l03B5-9

FIGURE 5-4. Large Concentrator Application

Board 1
LBCI
(BOARD I)
DATA OUT
Board N
DATA IN

-t=\

~
* Th~
i,

LBC3
(BOARD I)

I

\

\
>®C

I

LATCH OUT
i----Td---i

LBCI
(BOARD N)
TLlF/l03B5-10

T. =
Tb =
Tc =
Td =

Time to latch data out of the Physical Layer (Board 1)
Data flight time
Latch delay
Ideal setup time for incoming data
= Tdl + Td2 + Td3
Tdl = Reference error between COD devices
Td2 = Minimum phase resolution of COD device = 8 ns
Td3 = Setup time

FIGURE 5-5. Large Concentrator Timing

2-30

c

5.0 Detailed Information

"co

(Continued)

c.,)

needed at the CDD device for this method of routing the
ECL signals. The value of this resistor can be calculated
from the following equation:

5.2.2 CDD Device Driving Multiple PLAYER Devices
In a FDDI concentrator or dual attach station, it may be
necessary for a single DP83241 Clock Distribution Device
(CDD device) to drive multiple DP83251 155 PLAYER devic·
es. Since these PLAYER devices will be running synchro·
nously to each other they must have the same clocks. The
easiest way to accomplish this is to have one CDD device
drive multiple PLAYER devices.

R (Max) = 10Zo - RS

e

n

Where:
Re (Max) -

We are only concerned with the ECL outputs being able to
drive multiple loads. The conventional way of directly wiring
the one output to many inputs will not work. If the ECL signals are split into multiple traces then reflections will result
which may ruin the signal's integrity. An appropriate method,
where individual traces with a series resistor connected to
each load, is used instead. The series resistor should match
the line impedance and be placed as close to the CDD device as possible. The resistor will act as a voltage divider
and cut the voltage level of the signal in half. When this
modified signal reaches the input of the unterminated gate,
reflections will cause the signal to double and the receiving
input will see the full voltage swing. The reflection will then
travel back towards the CDD device, but the series resistance will stop this action. An emitter pulldown resistor is

n-

Largest emitter pulldown resistor
that can be used
Number of parallel lines being driven

Zo - Trace impedance
RS -

Series damping resistor

Another method for sending the ECL signal to multiple players is to route the ECL signal as a bus line and have each
load connected to the bus. The ECL bus line must be terminated only at the very end with a matching impedance (e.g.:
a 50.0. line will be terminated with a 50.0. load to Vee - 2V).
It is preferred that the input pin be directly connected to the
bus and not have a signal tap connected to the bus. However, if a tap off the bus is necessary, the shortest possible tap
is recommended.

DP83251

DP83251
Rs

TXC+ 1-1>---'111/\,----/

DP83241
DP83251

R.

DP83251
TLlF/10385-12

FIGURE 5-7. CDD Device Driving Four PLAYER Devices in Parallel

2-31

N

....
~

,..
..,.
N

C')

co

Il.

C

,-------------------------------------------------------------------------------------,
5.0 Detailed Information (Continued)
As with any high speed Signal, the routing of the Signal must
be carefully done. Sharp corners and other changes in trace
impedance should be avoided to reduce reflections in high
speed signal traces. Traces longer then one inch should
have a series or parallel termination scheme. Further system considerations can be found in National's F100K Design Guide. If these methods are followed the DP83241 signals will be able to drive multiple DP83251/55 PLAYER devices without any problems.

The most conservative method for routing the ECl signals
to multiple loads is to use the F100115 Quad low Skew
Driver. This device takes a differential ECl signal and outputs four of the same differential signals with a skew between them of less than 75 ps. Two of these devices will
allow the CDD device to drive four PLAYER devices. This
setup allows the ECl signals to be routed in a point to point
configuration to each PLAYER device.

~

DP83241

I.SZo

TXC+

Zo

1
DP83251

1

1

DP83251

DP83251

2.6Zo

-==
TL/F/lD385-13

FIGURE 5·8. Proper Bus Line Termination and Connections

DP83251
TOC+
nec+

DP83251
TSe-

nec+

nee-

necTSC+

TOC

nec+

F100115
nee-

DP83241
TOC+

F100115
TSCnec+

I

nec-

TSC+

DP83251

TSC-

nec+

TSC+

TOC

nec-

DP83251
TL/F/l0385-14

o Parallel Terminalion

FIGURE 5·9. CDD Device Driving Four PLAYER Devices Using Two F100115 Quad Low Skew Drivers

2-32

5.0 Detailed Information

(Continued)

5.3 LAYOUT RECOMMENDATIONS

• The external crystal circuitry should be connected to
Ground on an isolated branch off of the DGND pin .

• The part should be bypassed between the EXTVee and
EXTGND as close to the chip as possible (preferably under the chip using chip caps). The part should also be
bypassed between the DVee and DGND as close to the
chip as possible.

• The DGND pin should be connected to Ground off of an
isolated branch of the EXTGND pin, connected through a
ferrite bead or small inductor.
• The AGND pin should be connected to Ground off of an
isolated branch of the DGND pin, connected through a
ferrite bead or small inductor.

• The part should be bypassed between AVec and AGND
as close to the chip as possible.
• No TTL logic lines should pass through the external crystal or filter circuitry areas to avoid the possibility of noise
due to crosstalk.

• If the part is being driven by an external reference, the
XTL IN pin should be tied to either GND or Vee.
• If using a multilayered board with dedicated Vee and
Ground planes, ensure that the external crystal circuitry
has its own small isolated ground island that is connected to the AGND, DGND and EXTGND pins as described
above.

• The filter circuitry should be connected to Ground on an
isolated branch off of the AGND pin.
• The DVcc pin should be connected to Vee on an isolated branch off of the EXTVee pin, preferably being connected through a ferrite bead or small inductor.

• See Figure 5. 1 for component values.
• For best performance tie the VCORST pin to AGND.

• The AVec pin should be connected to Vee on an isolated branch off of the DVee pin, preferably being connected through a ferrite bead or small inductor.

GND

Vee

25
24

External
Crystal
Circuitry

23
22

21

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20

~

~'\~"''''''''''''''''~~i.: )(~~
~ L" ~",~A:
I""'''''
:·:i~,

This area should not have any other :
TTL signals passing through it. --+

Filter Circuitry

This drawing was done with convenience in mind.
Note: Pin 7 need nol be hooked up.

TLIFI1038S-IS

FIGURE 5-10. Recommended Layout

•
2-33

5.0 Detailed Information (Continued)
5.4 INPUT AND OUTPUT SCHEMATICS
XTL IN, XTL OUT

XVCO IN, XVCO INB
...-_ _-DVec

DVec
+2

_
DGND

EXTGND

-=-

TL/F/1038S-17

, TLlF/1D38S-16

Filter

TTL Outputs: LBC1-LBC5, Symbol Clock

. - - - - -.....---DVee

EXTVCC -

.....- -.....- - - - - - - - ,
2611

p. ••• TTL
OUTPUTS:
(LBC1-L8CS,
Symbol Clock)

FlLTtR

EXTGNO
TL/F/1038S-18

CMOS Inputs: REF IN, FEEDBK IN, PHASE SEL,
VCO RST, VCO SEL

TLlF/1038S-19

Typical ESD
Structure

r----.....-ovcc

TXC+, TXC-, TBC+, TBCEXTVec

TXC+, TXC-,
TBC+, TBC-

TL/F/1038S-21

EXTGND
TLlF/1038S-22

TL/F/1038S-20

2-34

5.0 Detailed Information

(Continued)

5.5 SYSTEM DEBUGGING FLOWCHART

Check to make sure
that the VCO RST Is
at a logic lOW and
that the VCO SEl Is

No

set to the correct
VCO (EXT or INT).

The loop filter Is
unstabla and should
be examlnad.

Check MOD SEl and
make sure tho VCO
Is set for the
correct VCO Range.

Make sure that ana
of tho lBC outputs
Is connected to the
fEEDBK IN pin.

Ves

Maka sure that the
REf SEl Input Is
selecting the correct
raferenca Input and
check to make sure
tho referanca Input
Is at the correct
frequency.

Tho Part should be
In lock. If using an
axtemal VCO, adjust
tho circuitry to give
a nominal value of
2.0 Volts on the
filTER pin.

Ves

TL/F/l03B5-23
Note 1: If the crystal oscillator is chosen as the input reference source then the XTl OUT pin should be checked for the correct frequency of oscillation. If the
oscillator fails to oscillate then the DC voltage on these pins should be checked and be equal to approximately Vee" 2 (with or without the crystal oscillator
present).

5.6 AC TEST CIRCUITS
SV

1.3kn
Tl/F/l03B5-26

FIGURE 5·12. Switching Test Circuit
for All ECl Output Signals
TUF/l03B5-24

fII

FIGURE 5·11. Switching Test Circuit
for All TTL Output Signals

2-35

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OP83251/55 PLAVERTMOevice
(FOOl Physical Layer Controller)
General Description

Features

The DP83251/DP83255 PLAYER device implements one
Physical Layer (PHY) entity as defined by the Fiber Distributed Data Interface (FDDI) ANSI X3T9.5 Standard. The PLAYER device contains NRZ/NRZI and 4B/5B encoders and
decoders, serializer/deserializer, framing logic, elasticity
buffer, line state detector/generator, link error detector, repeat filter, smoother, and configuration switch.

•
•
•
•
•
•
•
•
•

Low power CMOS-BIPOLAR process
Single 5V supply
Full duplex operation
. Separate management interface (Control Bus)
Parity on PHY-MAC Interface and Control Bus Interface
On-Chip configuration switch
Internal and external loopback
DP83251 for single attach stations
DP83255 for dual attach stations

TO HOST SYSTEM

DP83241
CDD
(CLOCK
DISTRIBUTION)

DP83231
CRD
(CLOCK
RECOVERY)

'----y--J
TO FIBER OPTIC
TRANSCEIVER PAIR

FIGURE 1-1. FOOl Chip Set Block Diagram

2-36

TL/F/10386-1

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Table of Contents

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7.0

ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
7.2 Recommended Operating Conditions
7.3 DC Electrical Charcteristics
7.4 AC Electrical Charcteristics
7.5 Test Circuits
8.0 DETAILED DESCRIPTIONS
8.1 Framing Hold Rules
8.2 Noise Events
8.3 Link Errors
8.4 Repeat Filter
8.5 Smoother
8.6 National Byte-wide Code for PHY-MAC Interface

1.0
2.0

FOOl CHIP SET OVERVIEW
ARCHITECTURE DESCRIPTION
2.1
Overview
2.2 Interfaces
3.0 FUNCTIONAL DESCRIPTION
3.1 Receiver Block
3.2 Transmitter Block
3.3 Configuration Switch
4.0 MODES OF OPERATION
4.1 Run Mode
4.2 Stop Mode
4.3 Loopback Mode
4.4 Cascade Mode
5.0 REGISTERS
6.0 PIN DESCRIPTIONS
6.1 DP83251
6.2 DP83255

2-37

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,---------------------------------------------------------------------------------,
1.0 FDDI Chip Set Overview
National Semiconductor's FOOl chip set consists of five
components as shown in Figure '1·1. For more information
on the other devices of the chip set, consult the appropriate
datasheets and application notes.
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DP83231 CRDTM Device'
Clock Recovery Device

DP83261 BMACTM Device
Media Access Controller

The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream.

The BMAC device implements the Timed Token Media Ac·
cess Control protocol defined by the ANSI FDDI X3T9.5
MAC Standard.

Features

Features

• PHY Layer loopback test
• Crystal controlled
• Clock locks in less than 85 p.s

• All of the standard defined ring service options
• Full duplex operation with through parity
Supports all FDDI Ring Scheduling Classes (Synchro·
nous, Asynchronous, etc.)

DP83241 CDDTM Device
Clock Distribution Device

• Supports Individual, Group, Short, Long, and External
Addressing
• Generates Beacon, Claim, and Void frames internally
o Extensive ring and station statistic gathering

From a 12.5 MHz reference, the Clock Distribution Device
synthesizes the 125 MHz, 25 MHz, and 12.5 MHz clocks
required by the BSI, BMAC and PLAYER devices.

• Extensions for MAC level bridging
• Separate management port that is used to configure and
control their operation

DP83251/55 PLAYERTM Device
Physical Layer Controller

• Multi·frame streaming interface

The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FOOl PHY X3T9.5 Stan·
dard.

DP83265 BSITM Device
System Interface
The BSI device implements the interface between the
BMAC device and a host system.

Features
• 4B/5B encoders and decoders
• Framing logic
• Elasticity Buffer, Repeat Filter and Smoother

Features

• Line state detector/generator

• Programmable transfer burst sizes of 4 or 8 32·bit words
• Interfaces to low cost DRAMs or directly to system bus

• 32·bit wide Address/Data path with byte parity

•
•
•
•

Link error detector
Configuration switch
Full duplex operation
Separate management port that is used to configure and
control their operation
In addition, the DP83255 contains an additional
PHY_Data. request and PHY_Data.indicate port required
for concentrators and dual attach stations.

• Provides 2 Output and 3 Input Channels
• Supports Header/Info splitting
• Efficient data structures
• Programmable Big or Little Endian alignment
• Full duplex data path allows transmission to self
• Confirmation status batching services
• Receive frame filtering services
• Operates from 12.5 MHz to 25 MHz synchronously with
the host system

2·38

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2.0 Architecture Description

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• Generates Idle, Master, Halt, Quiet or other user defined
symbol pairs upon request.

2.1 OVERVIEW

The PLAYER device is comprised of four blocks: Receiver,
Transmitter, Configuration Switch and Control Bus Interface
as shown in Figure 2-1.
Receiver

During normal operation, the Receiver Block accepts serial
data as inputs at the rate of 125 Mbps from the Clock Recovery Device (DP83231). During the Internal Loopback
mode of operation, the Receiver Block accepts data from
the Transmitter Block as inputs.
The Receiver Block performs the following operations:
• Converts the incoming data stream from NRZI to NRZ, if
necessary

C

• Provides smoothing function when necessary.
During normal operation, the Transmitter Block presents serial data to the fiber optic transmitter. While in the External
Loopback mode, the Transmitter Block presents serial data
to the Clock Recovery Device.

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• Program the Configuration Switch.
• Enable/disable functions within the Transmitter and Receiver Blocks (Le., NRZ/NRZI Encoder, Smoother, PHY
Request Data Parity, Line State Generation, Symbol Pair
Injection, NRZ/NRZI Decoder, Cascade Mode, etc.).
The Control Bus Interface also performs the following functions:
o Monitors Line States received

• Compensates for the differences between the upstream
and local clocks
• Decodes Line States
• Detects link errors
Finally, the Receiver Block presents data symbol pairs
(bytes) to the Configuration Switch Block

• Monitors link errors detected by the Receiver Block
• Monitors other error conditions
2.2 INTERFACES
The PLAYER device connects to external components via 5
functional interfaces: Serial Interface, PHY Port Interface,
Control Bus Interface, Clock Interface, and the Miscellaneous Interface.

Configuration Switch
An FDDI station may be in one of three configurations: Isolate, Wrap or Thru. The Configuration Switch supports these
configurations by switching the transmitted and received
data paths between the PLAYER and BMAC devices.
The configuration switching is performed internally, therefore no external logic is required for this function.

Serial Interface
The Serial Interface connects the PLAYER device to a fiber
optic transmitter (FOTX) and the Clock Recovery Device
(DP83231).

Transmitter

The Transmiter Block accepts 1O-bit bytes from the Configuration Switch.
The Transmitter Block performs the following operations:
• Encodes the data from 4B to 5B coding.
• Filters out code violations from the data stream.
TO BMAC OR PLAYER DEVICE

TO BMAC OR PLAYER DEVICE

PHY PORT INTERFACE
PHY REQUEST DATA

PHY PORT INTERFACE

PHY INDICATE DATA

PHY REQUEST DATA

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SERIAL INTERFACE
PMD INDICATE DATA

SERIAL INTERFACE
PMD REQUEST DATA
TO FIBER OPTIC TRANSMITTER

FROM CRD DEVICE

TLlF/l0386-2

FIGURE 2-1. PLAYER Device Block Diagram

2-39

......

.......

• Converts the data stream from NRZ to NRZI format
ready for transmission, if necessary.

Control Bus Interface
The Control Bus Interface allows a user to:

• Decodes the data from 5B to 4B coding
• Converts the serial bit stream into 10-bit bytes

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2.0 Architecture Description

3.0 Functional Description

(Continued)

The PLAYER Device is comprised of four blocks: Receiver,
Transmitter, Configuration Switch and Control Bus Interface.

PHY Port Interface
The PHY Port Interface connects the PLAYER device to
one or more BMAC devices and/or PLAYER devices. Each
PHY Port Interface consists of two byte-wide-interfaces,
one for PHY Request data input to the PLAYER device and
one for the PHY Indicate data output of the PLAYER device.
Each byte-wide interface consists of a parity bit (odd parity),
a control bit, and two 4-bit symbols.

3.1 RECEIVER BLOCK
During normal operation, the Receiver Block accepts serial
data as inputs at the rate of 125 Mbps from the Clock Recovery Device (DP83231). During the Internal loopback
mode of operation, the Receiver Block accepts data from
the Transmitter Block as input.
The Receiver Block performs the following operations:

The DP8355 PLAYER device has two PHY Port Interfaces
and the DP83251 has only one PHY Port Interface.

• Converts the incoming data stream from NRZI to NRZ, if
necessary

Control Bus Inter1ace
The Control Bus Interface connects the PLAYER device to
a wide variety of microprocessors and microcontrollers. The
Control Bus is an asynchronous interface which provides
access to 32 8-bit registers.

• Decodes the data from 5B to 4B coding
• Converts the serial bit stream into National byte-wide
code
• Compensates for the differences between the upstream
and local clocks

Clock Inter1ace
The Clock Interface consists of 12.5 MHz and 125 MHz
clocks used by the PLAYER device.

• Decodes Line States
• Detects link errors
Finally, the Receiver Block presents data symbol pairs to
the Configuration Switch Block.

The clocks are generated by either the Clock Distribution
Device (COD device) or the Clock Recovery Device (CRD
device).

• User definable enable signals
• Synchronization for cascaded PLAYER devices (a highperformance non-FOOl mode)

The Receiver Block consists of the following functional
blocks:
NRZI to NRZ Decoder
Shift Register
Framing logiC
Symbol Decoder
line State Detector
Elasticity Buffer
link Error Detector

• CMOS power and ground, and ECl ground and power

See Rgure 3-1.

Miscellaneous Inter1ace
The Miscellaneous Interface consists of:
• A reset signal
• User definable sense signals

TO CONFIGURATION SWITCH

TO REGISTERS

FROM TRANSMITTER BLOCK
(INTERNAL LOOPBACK)
FROM SERIAL INTERFACE

TLlF/103B6-3

FIGURE 3·1. Receiver Block Diagram

2-40

C

3.0 Functional Description

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(Continued)
Idle Line State
The Line State Detector recognizes the incoming data to be
in the Idle Line State upon the reception of 2 Idle symbol
pairs nominally (plus up to 9 bits of 1 in start up cases).
Idle Line State indicates the preamble of a frame or the lack
for frame transmission during normal operation. Idle Line
State is also used in the handshake sequence of the PHY
Connection Management process.

NRZI TO NRZ DECODER
The NRZI to NRZ Decoder converts Non-Return-To-ZeroInvert-an-Ones data to Non-Return-To-Zero data.
This function can be enabled and disabled through bit 7
(RNRi) of the Mode Register (MR). When the bit is cleared,
it converts the incoming bit stream from NRZI to NRZ.
When the bit is set the incoming NRZ bit stream is passed
unchanged.
SHIFT REGISTER
The Shift Register converts the serial bit stream into symbol-wide data for the 58/48 Decoder.
The Shift Register also provides byte-wide data for the
Framing Logic.

TABLE 3-1. Symbol Decoding
Symbol

a
1
2
3
4
5
6
7
B

FRAMING LOGIC
The Framing Logic performs the Framing function by detecting the beginning of a frame or the Halt-Halt or Halt-Quiet
symbol pair.
The J-K symbol pair (11000 10001) indicates the beginning
of a frame during normal operation. The Halt-Halt (00100
00100) and Halt-Quiet (00100 00000) symbol pairs are detected during Connection Management (CMT).
Framing can be temporarily suspended (Le. framing hold), in
order to maintain data integrity. The Framing Hold rules are
explained in Section B.l.

9
A
8
C
0
E
F

SYMBOL DECODER
The Symbol Decoder is a two level system. The first level is
a 5-bit to 4-bit converter, and the second level is a 4-bit
symbol pair to the NSC byte-wide code converter.
The first level latches the received 5-bit symbols and decodes them into 4-bit symbols. Symbols are decoded into
two types: data and control. The 4-bit symbols are sent to
the Line State Detector and the second level of the Symbol
Decoder. See Table 3-1 for the 58/48 Symbol Decoding
list.
The second level translates two 4-bit symbols from the 58/
48 converter and the line state information from the Line
State Detector into the National byte-wide code. More details on the National byte-wide code can be found 'in Section
B.6.

I (Idle)
H(Halt)
JK (Starting
Delimiter)
T (Ending
Delimiter)
R (Reset)
S(Set)
Q(Quiet)
V (Violation)
V
V
V
V
V
V
V
V'

LINE STATE DETECTOR
The FOOl Physical Layer (PHY) standard specifies eight
Line States that the Physical Layer can transmit. These Line
States are used in the Connection Management process.
They are also used to indicate data within a frame during the
normal operation.
The Line State Detector detects nine Line States, one more
than the required Line States specified in the standard.
The Line States are reported through the Current Receive
State Register (CRSR), Receive Condition Register A
(RCRA), and Receive Condition Register 8 (RCR8).

I'

Incoming 5B

Decoded4B

11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

11111
00100
11000&
10001
01101

1010
0001
1101

00111
11001
00000
00001
00010
00011
00101
00110
01000
01100
10000

0101
0110
0111
0010
0010
0010
0010
0010
0010
0010
0010
0010
0011
1011

Noles:
V' denotes PHY Invalid or an Elasticity Buffer stuff byte.
I' denotes Idle symbol in ILS or an Elasticity Buffer stuff byte.

Line States Description
Active Line State
The Line State Detector recognizes the incoming data to be
in the Active Line State upon the reception of the Starting
Delimiter (JK symbol pair).
The Line State Detector continues to indicate Active Line
State while receiving data symbols, Ending Delimiter (T
symbols), and Frame Status symbols (R and S) after the JK
symbol pair.

Super Idle Line State
The Line State Detector recognizes the incoming data to be
in the Super Idle Line State upon the reception of eight consecutive Idle symbol pairs nominally (plus 1 symbol pair).
The Super Idle Line State is used to insure synchronization.

2-41

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3.0 Functional Description (Continued)
ceive Clock, while data is read from the registers with the
Local Byte Clock.
'

No Signal Detect
The Line State Detector recognizes the incoming data to be
in the No Signal Detect state upon the deassertion of the
Signal Detect signal. No Signal Detect indicates that the
incoming link is inactive.

The Elasticity Buffer will recenter (i.e. set the read and write
pOinters to a predetermined distance from each other) upon
the dete,ction of a JK or every four byte times during PHY
Invalid (i.e. MLS, HLS, QLS, NLS, NSD) and Idle Line State.
To resolve metastability problems, the Elasticity Buffer is
deSigned such that a given register cannot be written and
read simultaneously under normal operating conditions. In a
symbol-wide station, a 5-bit off boundary JK following after a
maximum size frame situation may be produced which may
result in a sma" increase in the probability of an error
caused by a metastability condition.

Master Line State
The Line State Detector recognizes the incoming data to be
in the Master Line State upon the reception of eight consecutive Halt-Quiet symbol pairs nominally (plus up to 2 symbol
pairs in start up cases).
The Master Line State is used in the handshake sequence
of the PHY Connection Management process.
Halt Line State

LINK ERROR DETECTOR

The Line State Detector recognizes the incoming data to be
in the Halt Line State upon the reception of eight consecutive Halt symbol pairs nominally (plus up to 2 symbol pairs in
start up cases).

The Link Error Detector provides continuous monitoring of
an active link (i.e. during Active and Idle Line States) to
insure that it meets the minimum Bit Error Rate requirement
as set by the standard or user to remain on the ring.
Upon detecting a link error, the internalB-bit Link Error Monitor Counter is decremented. The start value for the Link
Error Monitor Counter is programmed through the Link Error
Threshold Register (LETR). When the Link Error Monitor
Counter reaches zero, bit 4 (LEMn of the Interrupt Condition Register (lCR) is set to 1. The current value of the Link
Error Monitor Counter can be read through the Current Link
Error Count Register (CLECR). For higher error rates the
current value is an approximate count because the counter
rolls over.
There are two ways to determine Link Error Rate: polling
and interrupt.

The Halt Line State is used in the handshake sequence of
the PHY Connection Management process.
Quiet Line State
The Line State Detector recognizes the incoming data to be
in the Quiet Line State upon the reception of eight consecutive Quiet symbol pairs nominally (plus up to 9 bits of 0 in
start up cases).
The Quiet Line State is used in the handshake sequence of
the PHY Connection Management process.
Noise Line State
The Line State Detector recognizes the incoming data to be
in the Noise Line State upon the reception of 16 noise symbol pairs.

Polling
The Link Error Monitor Counter is set to the value of FF.
This start value is programmed through the Link Error
Threshold Register (LETR).

The Noise Line State indicates that data is not received
correctly. A detailed description of a noise event can be
found in Section B.2.

Upon detecting a link error, the Current Link Error Counter is
decremented.
The Host System reads the current value of the Link Error
Monitor Counter via the Current Link Error Count Register
(CLECR). The Counter is then reset to FF.

Line State Unknown
The Line State Detector recognizes the incoming data to be
in the Line State Unknown state upon the reception of one
inconsistent symbol pair (i.e. data that is not expected). This
may be the beginning of a new line state.

Interrupt
The Link Error Monitor Counter is set to the value of FF.
This start value is programmed through the Link Error
Threshold Register (LETR).
Upon detecting a link error, the Line Error Monitor Counter
is decremented. When the counter reaches zero, bit 4
(LEMn of the Interrupt Condition Register (ICR) is set to 1,
and the interrupt Signal goes low.

Line State Unknown indicates that data is not received correctly. If the condition persists the noise line state may be
entered.

ELASTICITY BUFFER
The Elasticity Buffer performs the function of a "variable
depth" FIFO to compensate for clock skews between the
Receive Clock (RXC ±) and the Local Byte Clock (LBC).
Bit 5 (EBOU) of the Receive Condition Register B (RCRB) is
set to 1 to indicate an error condition when the Elasticity
Buffer cannot compensate for the clock skews.

The Host System is interrupted when the Link Error Monitor
Counter reaches O.
A state table describing Link Errors in more detail can be
found in Section B.3.

The Elasticity Buffer wi" support maximum clock skews of
± 50 ppm with a maximum packet length of 4500 bytes.
To make up for the accumulation of frequency disparity between the two clocks, the Elasticity Buffer wi" insert or delete Idle symbol pairs in the preamble. Data is written into
the byte-wide registers of the Elasticity Buffer with the Re-

Miscellaneous Items
When bit d (RUN) of the Mode Register (MR) is set to zero,
or when the PLAYER device is reset through the Reset pin
(RSn, the Signal Detect line (TTLSD) is internally forced to
zero and the Line State Detector is set to Line State Unknown.

2-42

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."

3.0 Functional Description (Continued)

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While in the External Loopback mode, the Transmitter Block
presents serial data to the Clock Recovery Device.

3.2 TRANSMITTER BLOCK
The Transmitter Block accepts 1a-bit bytes from the Configuration Switch.

The Transmitter Block consists of the following functional
blocks:

The Transmitter Block performs the following operations:

Data Registers
Parity Checker
4B/5B Encoder
Repeat Filter
Smoother
Line State Generator
Injection Control Logic
Shift Register
NRZ to NRZI Encoder

• Encodes the data from 4B to 5B coding
• Filters out code violations from the data stream
• Is capable of generating Idle, Master, Halt, Quiet, or other user defined symbol pairs
• Converts the data stream from NRZ to NRZI ready for
transmission
• Serializes data
During normal operation, the Transmitter Block presents serial data to the fiber optic transmitter.

!

I

REPEATER FILTER

I

SMOOTHER

!

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1

1
!

I

SHIFT REGISTER

r

NRZ TO NRZI ENCODER

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PARITY CHECKER

•

I

!

\

TO RECEIVER
BLOCK

..

I

...
4B/5B ENCODER

N

REGISTERS

DATA REGISTER

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See Figure 3-2.

CONFIGURATION SWITCH

I

N

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I

LINE STATE GENERATOR --.

~

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/

I INJECTION CONTROL LOGIC

I

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SERIAL INTERFACE
TUF/10386-4

FIGURE 3-2. Transmitter Block Diagram

2-43

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3.0 Functional Description (Continued)
LINE STATE GENERATOR
The Line State Generator allows the transmission of the
PHY Request data and can also generate and transmit Idle,
Master, Halt, or Quiet symbol pairs which can be used to
implement the Connection Management procedures as
specified in the FOOl Station Management (SMT) document.
The Line State Generator is programmed through Transmit
bits 0 to 2 (TM <2:0» of the Current Transmit State Register (CTSR).
Based on the setting of these bits, the Transmitter Block
operates in the Transmit Modes where the Line State Generator overwrites the Repeat Filter and Smoother outputs.

DATA REGISTERS
Data from the Configuration Switch is stored in the Data
Registers. The 10-bit byte-wide data consists of a parity bit,
a control bit, and two 4-bit symbols as shown in Figure 3-3.

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Control Bit

bO

b7
Data Bits

FIGURE 3·3. Byte·Wide Data
PARITY CHECKER
The Parity Checker verifies that the parity bit in the Data
Register represents odd parity (I.e. odd number of 1s).
The parity checking is enabled and disabled through bit 6
(PRDPE) of the Current Transmit State Register (CTSR).
If a parity error occurs, the Parity Checker will set bit 0 (OPE)
in the Interrupt Condition Register (ICR) and report the error
to the Repeat Filter.

See Table 3-3 for the listing of the Transmit Modes.
TABLE 3·2. 4B/5B Symbol Encoding

4B/5B ENCODER
The 4B/5B Encoder converts the two 4-bit symbols from
the Configuration Switch into their respective 5-bit codes.
See Table 3-2 for the Symbol Encoding list.
REPEAT FILTER
The Repeat Filter· is used to preven.t the propagation of
code violations in data frames, to the downstream station.

Symbol

4BCode

Outgoing5B

0
1
2
3
4
5

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101

0000

111100r
11111
11000 and
10001
01101

6
7·
B

Upon receiving violations in data frames, the Repeat Filter
replaces them with two Halt symbol pairs followed by Idle
symbols. Thus the code violations are isolated and recovered at each link and will not be propagated throughout the
entire ring.

9
A
B
C

Details on Repeat Filter operation are described in Section

0

8.4.

E
F

SMOOTHER
The Smoother is used to keep the preamble length of a
frame to a minimum of 6 Idle symbol pairs.
Idle symbols in the preamble of a frame may have been
added or deleted by each station to compensate for the
difference between the Receive Clock and its Local Clock.
The preamble needs to be maintained at a minimum length
to allow stations enough time to complete processing of one
frame and prepare to receive another. Without the Smoother function, the minimum preamble length (6 Idle symbol
pairs) may not be maintained as several stations may consecutively delete Idle symbols.

N
JK
T
R
S

(Starting
Delimiter)
(Ending
Delimiter)
(Reset)
(Set)

1101
0100 or
0101
0110
0111

00111
11001

TABLE 3-3. Transmit Modes

The Smoother attempts to keep the number of Idle symbol
pairs in the preamble at 7 by:

Active Transmit Mode

Normal Transmission Mode

Off Transmit Mode

• Deleting an Idle symbol pair in preambles which have
more than 7 Idle symbol pairs
and lor

Transmit Quiet symbol pairs
and disable the Fiber OptiC
Transmitter

Idle Transmit Mode

Transmit Idle symbol pairs

Master Transmit Mode

Transmit Halt·Quiet symbol
pairs

Quiet Transmit Mode

Transmit Quiet symbol pairs

Reserved Transmit
Mode

Reserved for future use. If
selected, Quiet symbol pairs
will be transmitted.

Halt Transmit Mode

Transmit Halt symbol pairs

• Inserting an Idle symbol pair in preambles which have
less than 7 idle symbol pairs (i.e. Extend State).
The Smoother Counter starts counting upon detecting an
Idle symbol pair. It stops counting upon detecting a JK symbol pair.
More details on the operation of the Smoother can be found
in Section 8.5.

2-44

3.0 Functional Description (Continued)
In the No Injection mode, the data stream is transmitted
unchanged.
In the One Shot mode, ISRA and ISRB are injected once on
the nth byte after a JK, where n is the programmed value
specified in the Injection Threshold Register.
In the Periodic mode, ISRA and ISRB are injected every nth
symbol.
In the Continuous mode, all data symbols are replaced with
the contents of ISRA and ISRB. This is the same as periodic
mode with IJTR = O.

INJECTION CONTROL LOGIC
The Injection Control Logic replaces the data stream with a
programmable symbol pair. This function is used to transmit
data other than the normal data frame or Line States.
The Injection Symbols overwrite the Line State Generator
(Transmit Modes) and the Repeat Filter and Smoother outputs.
These programmable symbol pairs are stored in the Injection Symbol Register A (ISRA) and Injection Symbol Register B (ISRB). The Injection Threshold Register (IJTR) determines where the Injection Symbol pair will replace the data
symbols.
The Injection Control LogiC is programmed through the bits
o and 1 (IC<1:0» of the Current Transmit State Register
(CTSR) to one of the following Injection Modes (see Figure

SHIFT REGISTER
The Shift Regiser converts encoded parallel data to serial
data. The parallel data is clocked into the Shift Register by
the Transmit Byte Clock (TBC±), and clocked out by the
Transmit Bit Clock (TXC ±).

3-4):

NRZ TO NRZI ENCODER
The NRZ to NRZI Encoder converts the serial Non-ReturnTo-Zero data to Non-Return-To-Zero-Invert-On-One data.
This function can be enabled and disabled through bit 6
(TNRZ) of the Mode Register (MR). When programmed to
"0", it converts the bit stream from NRZ to NRZI. When
programmed to "1", the bit stream is transmitted NRZ.

1. No Injection (i.e. normal operation)
2. One Shot
3. Periodic
4. Continuous

One Shot (Notes 1, 3)
nth

I
I

D

I

D

I· I

D

I··· I

D

n=O

I
1

1

XX

TL/F/l0386-5

•

•

:~:~ 1 xx 1 xx I·· ·1 xx 1:~:d

1 xx 1 xx I·· ·1 xx 1
n=O

XX

n=IJTR

Periodic (Notes 2, 3)

XX

I:;::1

n=1

n=IJTR n=O

n=1

n=IJTR

TL/F/l0366-6

Continuous (Note 3)

TUF/l0386-33

Where
ISRA: Iniection Symbol Register A
ISRB: Injection Symbol Register B
IJTR: Iniection Threshold Register
Note 1: In one shot when n + 0 the JK is replaced.
Note 2: In periodic when n = 0 all symbols are replaced.
Note 3: Max value on n = 255.
FIGURE 3-4. Injection Modes

2-45

•

~~------------------------------------------------~
~

C'I
C')

co

a.

C
.....
..~

C'I
C')

co

a.
C

3.0 Functional Description

(Continued)
PHY Port Interface output data paths, A-Indicate and
B_lndicate, that can drive output data paths of the external
PHY Port Interface. The third output data path is connected
internally to the Transmit Block.
The Configuration Switch is the same on both the DP83251
device and the DP83255 device. However, the DP83255
has two PHY Port interfaces connected to the Configuration
Switch, whereas the DP83251 has one PHY Port Interface.
The DP83255 uses the A-Request and A-Indicate paths
as one PHY Port Interface and the B_Request and B_lndicate paths as the other PHY Port interface (see Figure 35a). The DP83251, having only one port interface, uses the
B_Request and A-Indicate paths as its external port. The
A-Request and B_lndicate paths of the DP83251 are null
connections and are not used by this device (see Figure 35b).

3.3 CONFIGURATION SWITCH
The Configuration Switch consists of a set of multiplexors
and latches which allow the PLAYER device to configure
the data paths without the need of external logic. The Configuration Switch is controlled through the Configuration
Register (CR).
The Configuration Switch has four internal buses, the
A-Request bus, the B_Request bus, the Receive bus, a?d
the PHY_Invalid bus. The two Request buses can be drIven by external input data connected to the external PHY
Port Interface. The Receive bus is internally connected to
the Receive Block of the PLAYER device, while the PHY_
Invalid bus has a fixed 10-bit LSU pattern, useful during the
connection process. The configuration switch also has three
internal multiplexors, each can select any of the four buses
to connect to its respective data path. The first two are

~

~

!;!

.~

~
z

>=

>'

>-

il:

il:

§

fl
0;

il:

...:z:>=

il:

"-REQUEST

"-REQ BUS

PHY INVALID

PHY INVALID

REC BUS

REC BUS

"""~
1

~IT

~
::E

g

~
0

eo

DATA

A

'"enz
g

"""~

""u

I'"

I:

~

TL/Fho386-7

B_INDICATE

J

1

"--~ITDATA

DP83251

"""~
!:

~B_REQUEST

L

B.REQ BUS

"-REQ BUS

"--

1

UNDICATE

I

DP83255

~

L

~
.,

B.REQ BUS

fl

0;

>=

L

~B_REQUEST

"-REQUEST

~

B_INDICATE

UNDICATE

L

~

io! '
~

z

~

::E

~

g

.

g
TL/F/10386-34

FIGURE 3-5a. Configuration Switch Block
Diagram for DP83255

FIGURE 3-5b. Configuration Switch Block
Diagram for DP83251

2-46

C

3.0 Functional Description

."


~

• Flushes the Elasticity Buffer.
• Forces Line State Unknown in the Receiver Block.
• Outputs LSU symbol pairs (0 1 0011 1010) through
the PHY Data Indicate pins (AlP, AIC, AID <7:0>, BIP,
BIC, BID<7:0».

12

e:

TUF/103B6-42

FIGURE 4-1a. Configuration Switch
Loopback for DP83255

• Outputs Quiet symbol pairs through the PMD Data Request pins (TXD±).
• Resets all Control Bus register contents to zero or default values.
oUNDICATE

4.3 LOOPBACK MODE
The PLAYER device provides three types of loopback tests:
Configuration Switch Loopback, Internal Loopback, and External Loopback. These Loopback modes can be used to
test different portions of the device.

A..REQUEST

B..REQUEST

4.3.1 Configuration Switch Loopback
The Configuration Switch Loopback can be used to test the
data paths of the BMAC device(s) that are connected to the
PLAYER device before transmitting and receiving data
through the network.
In the Configuration Switch Loopback mode, the PLAYER
device performs the following functions:

B-REQ BUS _ _

_ J ... ~

UEQ BUS.....

... ~ ... ~

I

_1_

RECBUS----.l----

DP83251

I
I

I
I

I
I

I

I

I

J_~

_1_

~ .....

I
I
_1_
...... -.-I ~ ............... i'"
r _1_I ...... ..

PHY INVALID ........... i ..................

• Selects Port A PHY Request Data, Port B PHY Request
Data, or PHY Invalid to connect to Port A PHY Indicate
Data via the A-IND Mux.

...

I
I

I

-~

, ... ~ ......... i'" .............. ..
--'-------

TRANSMIT DATA

• Selects Port A PHY Request Data, Port B PHY Request
Data, or PHY Invalid to connect to Port B PHY Indicate
Data via the B_IND Mux.
• Connects data from the Receiver Block to the Transmitter Block via the Transmitter_Mux. (The PLAYER device
is repeating incoming data from the media in the Configuration Switch Loopback mode.)

TLlF/10386-43

See Figure 4-18 and 4-1b for block diagrams.

FIGURE 4-1b. Configuration Switch
LoopbackforDP83251
FIGURE 4-1.

2-50

4.0 Modes of Operation

(Continued)
• Outputs Quiet symbols through the External Loopback
Data pins (LBD±).
The level of the Quiet symbols transmitted through the
TXC ± pins is programmable through the Transmit Quiet
Level bit of the Mode Register.
The level of the Quiet symbols transmitted through the
LBD ± pins is always high, regardless of the Transmit Quiet
Level bit of the Mode Register.
If both Internal Loopback and External Loopback modes are
selected, Internal Loopback mode will have priority over External Loopback mode.
See Figure 4-2 for a block diagram.

4.3.2 Internal Loopback
The Internal Loopback mode can be used to test the functionality of the PLAYER device and to test the data paths
between the PLAYER and BMAC devices before ring insertion.
When in the Internal Loopback mode, the PLAYER device
performs the following functions:
• Directs the output data of the Transmitter Block to the
input of the Receiver Block through internal paths (see
Figure 2-1 PLAYER Device Block Diagram).
• Ignores the PMD Data Indicate pins (RXD ± and RXC ±),
• Outputs Quiet symbols through the PMD Data Request
pins (TXD±), and
TO

B~AC

OR PLAYER DEVICE

TO BMAC OR PLAYER DEVICE

PHY PORT INTERFACE
PHY REQUEST DATA

PHY PORT INTERFACE

PHY INDICATE DATA

I

PHY REQUEST DATA

PHY INDICATE DATA

I

CONFIGURATION SWITCH

T

o
C

o

N

T

I

I

t

SERIAL INTERFACE
INDICATE DATA

P~D

+

-L
RECEIVER
BLOCK

CONTROL BUS INTERFACE

REGISTERS

1

'I

TRANSMlnER
BLOCK

I

R

o
L

B
U
S

INTERNAL LOOPBACK PATH

SERIAL INTERFACE
REQUEST DATA

IGNORED INPUTS

P~D

TO FIBER OPTIC

FROM CRD DEVICE

FORCED QUIET SYMBOLS
TRANS~lnER

TL/F/10386-16

FIGURE 4-2. Internal Loopback

fII

2-51

~r-------------------------------------------------------------~
~

N

CO)

CD
D..

Q
......
~

N

CO)

~

Q

4.0 Modes of Operation

(Continued)
• Outputs Quiet symbols through the PMD Data Request
pins (TXD±).

4.3.3 External Loopback
The External Loopback mode can be used to test the functionality of the PLAYER device and to test the data paths
between the PLAYER, CRD, and BMAC devices before
transmitting and receiving data through the network.

The level of the Quiet symbols transmitted through the
TXC± pins is programmable through the Transmit Quiet
Level bit of the Mode Register.

When in the External Loopback mode, the PLAYER device
performs the following functions:

If both Internal Loopbackand External Loopback modes are
selected, Internal Loopback mode will have priority over External Loopback mode.

• Directs the output data of the Transmitter Block to the
external Loopback Data pins (LBD ±), which are normally connected to the Clock Recovery Device (see Figure
2. PLAYER Device Block Diagram).·

TO

B~AC

See Figure 4-3 for a block diagram.

TO

OR PLAYER DEVICE

PHY PORT INTERFACE
PHY REQUEST DATA

B~AC

OR PLAYER DEVICE

PHY PORT INTERFACE

PHY INDICATE DATA

PHY REQUEST DATA

PHY INDICATE DATA
T

1
RECEIVER
BLOCK

I

REGISTERS

SERIAL INTERFACE
INDICATE DATA

o

I

CONFIGURATION SWITCH

C

o

CONTROL BUS INTERFACE

L.

'I TRANS~lmR
BLOCK

I

N
T
R

o
L

B
U
S

SERIAL INTERFACE
REQUEST DATA

P~D

P~D

EXTERNAL LOOPBACK

FORCED QUIET

SY~BOLS

CLOCK RECOVERY DEVICE

IGNORED INPUTS
FROM FIBER OPTIC RECEIVER

TO FIBER OPTIC TRANSMITTER
TUF/l0386-17

FIGURE 4·3. External Loopback

2-52

~----------------------------------------------------------------'C

4.0 Modes of Operation

"V

co

(Continued)

Co)

• Data frames must be a minimum of three bytes long (including the JK symbol pair). Smaller frames will cause
Elasticity Buffer errors.
• Data frames must have a maximum size of 4500 bytes,
with a JK starting delimiter and a (T or R or SIx or x(T or
R or S) ending delimiter byte.

4.4 CASCADE MODE
The PLAYER device can operate in the Cascade (parallel)
mode-Figure 4-4-which is used in high bandwidth, pointto-point data transfer applications. This is a non-FDDI mode
of operation.

CONCEPTS

3. Due to the different clock rates, the JK symbol pair may
arrive at different times at each PLAYER device. The total
skew between the fastest and slowest cascaded PLAYER devices receiving the JK starting delimiter must not
exceed 80 ns.
4. The first PLAYER device to receive a JK symbol pair will
present it to the host system and assert the Cascade
Ready signal. The PLAYER device will present one more
JK as it waits for the other PLAYER devices to recognize
their JK. The maximum number of consecutive JKs that
can be presented to the host is 2.
5. The Cascade Start Signal is set to 1 when all the cascaded PLAYER devices release their Cascade Ready signals.
6. Bit 4 (CSE) of the Receive Condition Register B (RCRB)
is set to 1 if the Cascade Start signal (CS) is not set
before the second falling edge of clock signal LBC from
when Cascade Ready (CR) was released. CS has to be
set within approximately 80 ns of CR release. This condition signifies that not all cascaded PLAYERs have received their respective JK symbol pair within the allowed
skew range.
7. If the JK symbols are corrupted in the point-to-point links,
some PLAYER devices may not report a Cascaded Synchronization Error.
8. To guarantee integrity of the interlrame information, the
user must put at least 8 Idle symbol pairs between
frames. The PLAYER device will function properly with
only 4 Idle symbol pairs, however the interlrame symbols
may be corrupted with random non-JK symbols.
The BMAC device could be used to provide required framing and optical FCS support.

In the Cascade mode, multiple PLAYER devices are connected together to provide data transfer at multiples of the
FDDI data rate. Two cascaded PLAYER devices provide a
data rate twice the FDDI data rate; three cascaded PLAYER
devices provide a data rate three times the FDDI data rate,
etc.
Multiple data streams are transmitted in parallel over each
pair of cascaded PLAYER devices. All data streams start
simultaneously and begin with the JK symbol pair on each
PLAYER device.
Data is synchronized at the receiver of each PLAYER device by the JK symbol pair. Upon receiving a JK symbol pair,
a PLAYER device asserts the Cascade Ready signal to indicate the beginning of data reception.
The Cascade Ready signals of all PLAYER devices are
open drain ANDed together to create the Cascade Start
signal. The Cascade Start signal is used as the input to
indicate that all PLAYER devices have received the JK symbol pair. Data is now being received at every PLAYER device and can be transferred from the cascaded PLAYER
devices to the host system.
See Figure 4-5 for more information.

OPERATING RULES
When the PLAYER device is operating in Cascade mode,
the following rules apply:
1. Data integrity can be guaranteed if the worst case fiber
optic transmission skew between parallel fiber cables is
less than 40 ns. This amounts to about 785 meters of
fiber, assuming a 1 % worst case variance.
2. Even though this is a non-FDDI application, the general
rules for FDDI frames must be obeyed.

N
U1

.....
.....
C

"V

co
Co)

N
U1
U1

fI

2-53

II)
II)

C'\I

C')

co

4.0 Modes of Operation

(Continued)

D..

C

.......
.....
II)
C'\I

C')

co

D..

C

HOST SYSTEM

HOST SYSTEM

TLlF/l0386-18

FIGURE 4·4. Parallel Transmission

CASCADE READY

f

.D.AT.A...·:..1Ij PLAYER
1::IDEVICE:1
RX
RX

...011

.. ...

...

14J___D•A•TAiiIIji.·.otI PLAYER
...... 1 DEVICE 2
~

:::

HOST SYSTEM

...

RX

..

...011
~

illij'

DATA ..:

I

1+.+"::":;=~':';;;':''--,

~
1.1-""":::"-'+--CA-S-C-AD-E-S-T-A-RT-+-+I ~
....

CASCADE READY

:z

~

I:::

z

Cl

~~

.. ::.

r ....... ::: •.....

I"-If~:".. . .I

,I"'....·--....+-C-A-SC-A-D-E-S-TA-R-T--H

PLAYER
DEVICE N

.. .

r.I:.•.•.

CASCADE READY
CASCADE START

TLlF/l0386-19

FIGURE 4·5. Cascade Mode of Operation
Note: N is recommended to be less than 3 for this mode. See Application Note 679 for larger values of N.

2·54

c

5.0 Registers
The PLAYER device is initialized, configured, and monitored via 32 8·bit registers. These registers are accessible through the
Control Sus Interface.

.....
......
U1

C

Table 5·1 is a Register Summary List. Table 5·2 shows the contents of each register.

"

0)
(0)
I\)

TABLE 5·1. Register Summary
Register
Address

Register
Symbol

Access Rules

OOh

MR

Mode Register

Always

Always

Register Name
Read

Write

01h

CR

Configuration Register

Always

Always

02h

ICR

Interrupt Condition Register

Always

Conditional

03h

ICMR

Interrupt Condition Mask Register

Always

Always

04h

CTSR

Current Transmit State Register

Always

Conditional

05h

IJTR

Injection Threshold Register

Always

Always

06h

ISRA

Injection Symbol Register A

Always

Always

07h

ISRB

Injection Symbol Register B

Always

Always

08h

CRSR

Current Receive State Register

Always

Write Reject

09h

RCRA

Receive Condition Register A

Always

Conditional

OAh

RCRB

Receive Condition Register B

Always

Conditional

OSh

RCMRA

Receive Condition Mask Register A

Always

Always

OCh

RCMRB

Receive Condition Mask Register B

Always

Always

ODh

NTR

Noise Threshold Register

Always

Always

OEh

NPTR

Noise Prescale Threshold Register

Always

Always

OFh

CNCR

Current Noise Count Register

Always

Write Reject

10h

CNPCR

Current Noise Prescale Count Register

Always

Write Reject

llh

STR

State Threshold Register

Always

Always

12h

SPTR

State Prescale Threshold Registger

Always

Always

13h

CSCR

Current State Count Register

Always

Write Reject

14h

CSPCR

Current State Prescale Count Register

Always

Write Reject

ISh

LETR

Link Error Threshold Register

Always

Always

16h

CLECR

Current Link Error Count Register

Always

Write Reject

17h

UDR

User Definable Register

Always

Always

18h

IDR

Device ID Register

Always

Write Reject

19h

CIJCR

Current Injection Count Register

Always

Write Reject

lAh

ICCR

Interrupt Condition Comparison Register

Always

Always

ISh

CTSCR

Current Transmit State Comparison Register

Always

Always

lCh

RCCRA

Receive Condition Comparison Register A

Always

Always

tDh

RCCRB

Receive Condition Comparison Register B

Always

Always

lEh

RRO

Reserved Register 0

Always

Write Reject

lFh

RRI

Reserved Register 1

Always

Write Reject

2·55

"

0)
(0)
I\)

U1
U1

5.0 Registers (Continued)
TABLE 5·2. Register Content Summary
Register
Address

Register
Symbol

Bit Symbols
07

06

04'

05

03
CM

02

01

00

EXLB

ILB

RUN

OOh

MR

RNRZ

TNRZ

TE

TaL

01h

CR

BIE

AlE

TRS1

TRSO

BIS1

BISO

AIS1

AlSO

02h

ICR

UDI

RCB

RCA

LEMT

CWI

CCR

CPE

DPE

03h

ICMR

UDIM

RCBM

RCAM

LEMTM

CWIM

CCRM

CPEM

DPEM

04h

CTSR

RES

PRDPE

SE

IC1

ICO

TM2

TM1

TMO

05h

IJTR

IJT7

IJT6

IIJ5

IJT4

IJT3

IJT2

IJT1

IJTO

06h

ISRA

RES

RES

RES

IJS4

IJS3

IJS2

IJS1

IJSO

07h

ISRB

RES

RES

RES

IJS9

IJSB

IJS7

IJS6

IJS5

OBh

CRSR

RES

RES

RES

RES

LSU

LS2

LS1

LSO

OLS

NSD

09h

' RCRA

LSUPI

LSC

NT

NLS

MLS

HLS

OAh

RCRB

RES

SILS

EBOU

CSE

LSUPV

ALS

ST

ILS

OBh

RCMRA

LSUPIM

LSCM

NTM

NLSM

NLSM

HLSM

OLSM

NSDM

OCh

RCMRB

RES

SILSM

EBOUM

CSEM

LSUPVM

ALSM

STM

ILSM

ODh

NTR

RES

NT6

NT5

NT4

NT3

NT2

NT1

NTO

OEh

NPTR

NPT7

NPT6

NPT5

NPT4

NPT3

NPT2

NPT1

NPTO

OFh

CNCR

NCLSCD

CNC6

CNC5

CNC4

CNC3

CNC2

CNC1

CNCO

10h

CNPCR

CNPC7

CNPCS

CNPC5

CNPC4

CNPC3

CNPC2

CNPC1

CNPCO

11h

STR

RES

ST6

ST5

ST4

ST3

ST2

ST1

STO

SPT2

SPT1

SPTO

SPT6

SPT5

SPT4

SPT3

SCLSCD

CSC6

CSC5

CSC4

CSC3

CSC2

CSC1

CSCO

CSPC7

CSPC6

CSPC5

CSPC4

CSPC3

CSPC2

CSPC1

CSPCO

LET6

LET5

LET4

LET3

LET2

LET1

LETO

LEC4

LEC3

LEC2

LEC1

LECO
SBO

12h

SPTR

'SPT7

13h

CSCR

14h

CSPCR

15h

LETR

LET7

CLECR

LEC7

LECS

LEC5

17h

UDR

RES

RES

RES

RES

EB1

EBO

SB1

1Bh

IDR

DID7

DID6

DID5

DID4

DID3

DID2

DiD1

DIDO

19h

CIJCR

IJC7 ,

IJC6

IJC5

IJC4

IJC3

IJC2

IJC1

IJCO

1Ah

ICCR

UDIC

RCBC

RCAC

LEMTC

CWIC

CCRC

CPEC

DPEC

1Bh

'. CTSCR

RESC

PRDPEC

SEC

IC1C

ICOC

TM2C

TM1C

TMOC

1Ch

RCCRA

LSUPIC

LSCC

NTC

NLSC

MLSC

HLSC

OLSC

NSDC

1Dh

RCCRB

RESC

SILSC

EBOUC

CSEC

LSUPVC

ALSC

STC

ILSC

.1Eh

RR1

RES

RES

RES

RES

RES

RES

RES

RES

1Fh

RR2

RES

RES

RES

RES

RES

RES

RES

RES

16h

2-56

c

5.0 Registers

;;g

(Continued)

w
~
.....

MODE REGISTER (MR)

......

The Mode Register is used to initialize and configure the PLAYER device.
In order to minimize interruptions on the network, it is recommended that the PLAYER device first be put in STOP mode (Le. set
the RUN bit to zero) before programming the Mode Register, the Configuration Register, or the Current Transmit State Register.

READ

ADDRESS

I

OOh
D7

I

RNRZ
Bit

Always

D6

I

"tJ

CD
W
N

c.n
c.n

ACCESS RULES

I

C

TNRZ

WRITE

I

D5

I

TE

Always
D4

I

TQL

I
D3

I

CM

Symbol

D2

I

D1

EXLB

I

ILB

DO

I

RUN

I

Description

DO

RUN

RUN/STOP
0: Enables the STOP mode. Refer to Section 4.2, STOP Mode of Operation, for more
information.
1: Normal Operation (i.e. RUN mode).
Note: The RUN bil is aulomalically sello 0 when Ihe RST pin is asserted (i.e. sello ground).

D1

ILB

INTERNAL LOOPBACK:
0: Disables Internal Loopback mode (i.e. normal operation).
1: Enables Internal Loopback mode.

D2

EXLB

EXTERNAL LOOPBACK
0: Disables External Loopback mode (i.e. normal operation).
1: Enables External Loopback mode.

D3

CM

CASCADE MODE:
0: Disables synchronization of cascaded PLAYER devices.
1: Enables the synchronization of cascaded PLAYER devices.

04

TQL

TRANSMIT QUIET LEVEL:. This bit is used to program the transmission level of the Quiet
symbols.
0: Low level Quiet symbols are transmitted through the PMD Data Request pins
(i.e. TXD+ = low, TXD- = high).
1: High level Quiet symbols are transmitted through the PMD Data Request pins
(i.e. TXD+ = high, TXD- = low).

D5

TE

TRANSMIT ENABLE: The TE bit controls the action of FOTX Enable (TXE) pin independent
of the current transmit mode. When TE is 0, the TXE output disables the optical transmitter;
when TE is 1, the optical transmitter is disabled during the Off Transmit Mode (OTM) and
enabled otherwise. The On and Off level of the TXE is dependent on the FOTX Enable Level
(TEL) pin to the PLAYER device. The following rules summarizes the output of TXE:
(1) If TE = 0, then TXE = Off
(2) If TE = 1 and OTM, then TXE = Off
(3) If TE = 1 and not OTM, then TXE = On.

D6

TNRZ

TRANSMIT NRZ DATA:
0: Transmits data in Non-Return-To-Zero-Invert-On-Ones format.
1: Transmits data in Non-Return-To-Zero format.

07

RNRZ

RECEIVE NRZ DATA:
0: Receives data in Non-Return-To-Zero-Invert-On-Ones format.
1: Receives data in Non-Return-To-Zero format.

Refer to Section 4.3, Loopback Mode of Operation, for more information.

Refer to Section 4.3, Loopback Mode of Operation, for more information.

Refer to Section 4.4, Cascade Mode of Operation, for more information.

2-57

•

5.0 Registers

(Continued)

CONFIGURATION REGISTER (CR)
The Configuration Register controls the Configuration Switch Block and enables/disables both the A and B Indicate output
ports.
Note that the B_lndicate output port is offered only on the DP83255 (for Dual Attach Stations), and not in the DP83251 (for
Single Attach Stations).
For further information, refer to Section 3.3, Configuration Switch.
ACCESS RULES
ADDRESS

I
07

I

BIE
Bit

DO,D1

AlE

I

Always

06

I

WRITE

READ

I

01h

05

I

TRS1

Always

I

I

BIS1

04

I

TRSO

BISO,BIS1

BISO

I

AIS1

DO

I

AlSO

I

Description
A.-INDICATE SELECTOR <0, 1>: The ~Indicate Selector <0, 1> bits select one of the four
Configuration Switch data buses for the ~Indicate output port (AlP, AIC, AID < 7:0».
AIS1
0
0
1
1

D2,D3

I

Symbol
AISO,AIS1

01

02

03

AlSO
0
1
0
1

PHY Invalid Bus
Receiver Bus
A-Request Bus
B_Request Bus

B_INDICATE SELECTOR <0, 1>: The B_lndicate Selector <0, 1> bits select one of the four
Configuration Switch data buses for the B_lndicate output port (BIP, BIC, BID <7:0».
BIS1
BISO
0
PHY Invalid Bus
0
0
1
Receiver Bus
1
0
A-Request Bus
B_Request Bus
1
1
Note: Even though this bit can be set andlor cleared in the DPB3251 (for Single Attach Stations), it will not affect
any lias since the DPB3251 does not offer a B_lndicate port.

04,05

TRSO, TRS1

TRANSMIT REQUEST SELECTOR <0, 1>: The Transmit Request Selector <0, 1> bits select
one of the four Configuration Switch data buses for the input to the Transmitter Block.
TRS1
TRSO
PHY Invalid Bus
0
0
0
1
Receiver Bus
1
0
A-Request Bus
B_Request Bus
1
1
Note: If the PLAYER device is in Active Transmit Mode (i.e. the Transmit Mode bits (TM < 2:0> ) of the Current
Transmit State Register (CTSR) are set to 000) and the PHY Invalid Bus is selected, then the PLAYER device will
transmit a maximum of four Halt symbol pairs and then continuous Idle symbols due to the Repeat Filter.

06

AlE

"-INDICATE ENABLE:
0: Disables the A-Indicate output port. The A-Indicate port pins will be at TRI·STATE when
the port is disabled.
1: Enables the A-Indicate output port (AlP, AIC, AID<7:0».

07

BIE

B_INDICATE ENABLE:
0: Disable the B_lndicate output port. The B_lndicate port pins will be at TRI·STATE
when the port is disabled.
1: Enables the B_lndicate output port (BIP, BIC, BID<7:0».
Note: Even though this bit can be set andlor cleared in the DPB3251 (for Single Attach Stations), it will not affect
any lias since the DPB3251 does not offer a B_lndicate port.

2·58

5.0 Registers

(Continued)

INTERRUPT CONDITION REGISTER (ICR)

The Interrupt Condition Register records the occurrence of an internal error event, the detection of Line State, an unsuccessful
write by the Control Bus Interface, the expiration of an internal counter, or the assertion of one or more of the User Definable
Sense pins.
The Interrupt Condition Register will assert the Interrupt pin (IND when one or more bits within the register are set to 1 and the
corresponding mask bits in the Interrupt Condition Mask Register (ICMR) are also set to 1.
ACCESS RULES
READ

ADDRESS

I
D7

I

UDI
Bit

DO

I

02h
D6

I

RCB

WRITE

Always

I

Conditional

I

LEMT

D5

I

D4

RCA

I
D3

I

D2

CWI

Symbol

DPE

I

D1

CCR

I

CPE

DO

I

DPE

I

Description
PHY_REQUEST_DATA PARITY ERROR: This bit will be setto 1 when:

(1) The PHY Request Data Parity Enable bit (PRDPE) of the Current Transmit State Register
(CTSR) is set to 1 and
(2) The Transmitter Block detects a parity error in the incoming PHY Request Data.
The source of the data can be from the PHY Invalid Bus, the Receiver Bus, the A-Bus, or the
B_Bus of the Configuration Switch.
D1

CPE

CONTROL BUS DATA PARITY ERROR: This bit will be set to 1 when:
(1) The Control Bus Parity Enable pin is asserted (CBPE = Vecl and
(2) The Control Bus Interface detects a parity error in the incoming Control Bus Data
(CBD<7:0» during a write cycle.

D2

CCR

CONTROL BUS WRITE COMMAND REJECT: This bit will be set to 1 when an attempt to

write into one of the following read-only registers is made:
Current Receive State Register (Register 08, CRSR)
Current Noise Count Register (Register OF, CNCR)
Current Noise Prescale Count Register (Register 10, CNPCR)
Current State Count Register (Register 13, CSCR)
Current State Prescale Count Register (Register 14, CSPCR)
Current Link Error Count Register (Register 16, CLECR)
Device ID Register (Register 18, IDR)
Current Injection Count Register (Register 19, CIJCR)
Reserved Register 0 (Register 1E, RRO)
Reserved Register 1 (Register 1F, RR1)
D3

CWI

CONDITIONAL WRITE INHIBIT: Set to 1 when bits within mentioned registers do not match
bits in compare register. This bit ensures that new (i.e. unread) data is not inadvertently
cleared while old data is being cleared through the Control Bus Interface.

This bit is set to 1 to prevent the setting or clearing of any bit within the following registers:
Interrupt Condition Register (Register 02, ICR)
Current Transmit State Register (Register 04, CTSR)
Receive Condition Register A (Register 09, RCRA)
Receive Condition Register B (Register OA, RCRB)
when they differ from the value of the corresponding bit in the following registers respectively:
Interrupt Condition Compare Register (Register 1A, ICCR)
Current Transmit State Compare Register (Register 1B, CTSCR)
Receive Condition Compare Register A (Register 1C, RCCRA)
Receive Condition Compare Register B (Register 1D, RCCRB)
This bit must be cleared by software. Note that this differs from the BMAC device bit of the
same name.

2-59

5.0 Registers (Continued)
INTERRUPT CONDITION REGISTER (ICR) (Continued)
Bit

Symbol

04

LEMT

LINK ERROR MONITOR THRESHOLD: This bit is set to 1 when the internalS-bit Link Error Monitor
Counter reaches zero. It will remain set until cleared by software.
During the reset process (i.e. RS'i" = GND), the Link Error Monitor Threshold bit is set to 1 because the
Link Error Monitor Counter is initialized to zero.

D5

RCA

RECEIVE CONDITION A: This bit is set to 1 when:
(1) One or more bits in the Receive Condition Register A (RCRA) is set to 1 and
(2) The corresponding mask bits in the Receive Condition Mask Register A (RCMRA) are also set to 1.
In order to clear (i.e. set to 0) the Receive Condition A bit, the bits within the Receive Condilion Regisler
A Ihal are sello 1 musl firsl be either cleared or masked.

D6

RCB

RECEIVE CONDITION B: This bit is sel to 1 when:
(1) One or more bits in the Receive Condition Register B (RCRB) is set to 1 and
(2) The corresponding mask bits in the Receive Condilion Mask Register B (RCMRB) are also sello 1.
In order 10 clear (i.e. set to 0) the Receive Condition B bit, the bits within the Receive Condilion Register
B that are sello 1 musl first be either cleared or masked.

D7

UDI

USER DEFINABLE INTERRUPT: This bit is set to 1 when one or both of the Sense Bits (SBO or SB1) in
the User Definable Register (UDR) is set to 1.
In order to clear (i.e. set to 0) the User Definable Interrupt Bil, both Sense Bits must be set to O.

Description

2-60

Ie

."

5.0 Registers (Continued)

CD

Co)

INTERRUPT CONDITION MASK REGISTER (ICMR)
The Interrupt Condition Mask Register allows the user to dynamically select which events will generate an interrupt.
The Interrupt pin will be asserted (i.e. INT = GND) when one or more bits within the Interrupt Condition Register (lCR) are set to
1 and the corresponding mask bits in this register are also set to 1.
This register is cleared (i.e. set to 0) and all interrupts are initially masked during the reset process.
ACCESS RULES
ADDRESS

I

I

03h
07

I

UDIM

READ

I

I

Always
05

06
RCBM

WRITE

I

RCAM

Always
04

I

LEMTM

I
03

I

02

CWIM

I

CCRM

01

I

CPEM

DO

I

DPEM

I

Bit

Symbol

Description

DO

DPEM

PHY_REQUEST_DATA PARITY ERROR MASK: The mask bit for the PHY_Request Data Parity
Error bit (DPE) of Interrupt Condition Register (ICR).

D1

CPEM

CONTROL BUS DATA PARITY ERROR MASK: The mask bit for the Control Bus Data Parity Error bit
(CPE) of the Interrupt Condition Register (ICR).

D2

CCRM

CONTROL BUS WRITE COMMAND REJECT MASK: The mask bit for the Control Bus Write
Command Reject bit (CCR) of the Interrupt Condition Register (ICR).

D3

CWIM

CONDITIONAL WRITE INHIBIT MASK: The mask bit for the Conditional Write Inhibit bit (CWI) of the
Interrupt Condition Register (lCR).

D4

LEMTM

LINK ERROR MONITOR THRESHOLD MASK: The mask bit for the Link Error Monitor Threshold bit
(LEMT) of the Interrupt Condition Register (ICR).

D5

RCAM

RECEIVE CONDITION A MASK: The mask bit for the Receive Condition A bit (RCA) of the Interrupt
Condition Register (ICR).

D6

RCBM

RECEIVE CONDITION B MASK: The mask bit for the Receive Condition B bit (RCB) of the Interrupt
Condition Register (ICR).

D7

UDIM

USER DEFINABLE INTERRUPT MASK: The mask bit for the User Definable Interrupt bit (UDI) of the
Interrupt Condition Register (lCR).

2·61

N

....
.....
(It

Ie

."
CD

Co)

N

(It
(It

5.0 Registers (Continued)
CURRENT TRANSMIT STATE REGISTER (CTSR)
The Current Transmit State Register can program the Transmitter Block to internally generate and transmit Idle, Master, Halt,
Quiet, or user programmable symbol pairs, in addition to the normal transmission of incoming PHY Request data. The Smoother
and PHY Request Data Parity may also be enabled and disabled through this register.
The Transmit Modes overwrite the Repeat Filter and Smoother outputs, while the Injection Symbols overwrite the Transmit
Modes.
During the reset process (i.e. RSi = GND) the Transmit Mode is set to Off (TM <2:0> = 010), the Smoother is enabled (i.e. SE
is set to 1), and the Reserved bit (b7) is set to 1. All other bits of this register are cleared (i.e. set to 0) during the reset process.
ACCESS RULES
ADDRESS

I
07

I

RES

READ

I

04h

06

I

PRDPE

WRITE

I

Always

Conditional

05

I

SE

04

I

IC1

I
03

I

ICO

02

I

TM2

01

I

TM1

DO

I

TMO

I

Bit

Symbol

Description

00,01,
02

TMO, TM1,
TM2

Transmit Mode < 0, 1, 2>: These bits select one of the 6 transmission modes for the PMD Request
Data output port (TXD ±).
TM2

TM1

TMO

o

o

o

o

o

Active Transmit Mode (ATM): Normal
transmission of incoming PHY Request data.
Idle Transmit Mode (ITM): Transmission of
Idle symbol pairs (11111 11111).

o

o

o

Off Transmit Mode (OTM): Transmission of
Quiet symbol pairs (00000 00000) and
. deassertion of the FOTX Enable pin (TXE).
Reserved: Reserved for future use. Users
are discouraged from using this transmit
mode. If selected, however, the transmitter
will generate Quiet symbol pairs (00000
00000).

o

o

o

Master Transmit Mode (MTM):
Transmission of Halt and Quiet symbol pairs
(0010000000).
Halt Transmit Mode (HTM): Transmission of
Halt symbol pairs (00100 00100).

o

Quiet Transmit Mode (QTM): Transmission
of Quiet symbol pairs (00000 00000).
Reserved: Reserved for future use. Users
are discouraged from using this transmit
mode. If selected, however, the transmitter
will generate Quiet symbol pairs (00000
00000).

2·62

o
5.0 Registers

"

CO
W

(Continued)

I'\)

CURRENT TRANSMIT STATE REGISTER (CTSR) (Continued)
Bit

Symbol

D3,D4

ICO,lCl

Description
Injection Control < 0, 1 >: These bits select one of the 4 injection modes. The injection modes
overwrite data from the Smoother, Repeat Filter, Encoder, and Transmit Modes.

en
....
......

o

"

CO
W

I'\)

en
en

ICO is the only bit of the register that is automatically cleared by the PLAYER device after the One Shot
Injection is executed. The automatic clear of ICO during the One Shot mode can be int!lrpreted as an
acknowledgment that the One Shot has been completed.

D5

SE

IC1
0

ICO
0

0

1

One Shot: In one shot mode, Injection
Symbol Register A (ISRA) and Injection
Symbol Register B (ISRB) are injected n
symbol pairs after a JK, where n is the
programmed value of the Injection Count
Register (IJCR). If IJCR is set to 0, the JK
symbol pair is replaced by ISRA and ISRB.
Once the One Shot is executed, the PLAYER
device automatically sets ICO to 0, thereby
returning to normal transmission of data.

1

0

Periodic: In Periodic mode, Injection Symbol
Register A (ISRA) and Injection Symbol .
Register B (ISRB) are injected every (n + 1)th
symbol pair, where n is the programmed
value of the Injection Count Register (IJCR).
If IJCR is set to 0, all data symbols are
replaced with ISRA and ISRB.

1

1

Continuous: In Continuous mode, all data
symbols are replaced with Injection Symbol
Register A (ISRA) and Injection Symbol
Register B (ISRB).

No Injection: The normal transmission of
incoming PHY Request data (i.e. symbols are
not injected).

SMOOTHER ENABLE:
0: Disables the Smoother.
1: Enables the Smoother.
When enabled, the Smoother can redistribute Idle symbol pairs which were added or deleted by
the local or upstream receivers.
Note: Once the counter has started, it will continue to count irrespective of the incoming symbols with the exception of a
JK symbol pair. This bit should be enabled for interoperable operation.

D6

PRDPE

PHY_REQUEST DATA PARITY ENABLE:
0: Disables PHY_Request Data parity.
1: Enables PHY_Request Data parity.

D7

RES

RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset process. It may be set or
cleared without any effects to the functionality of the PLAYER device.

2-63

•

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
,U)

C'I

C")

CIO

~
.....

....

U)

C'I

C")

~

C

5.0 Registers

(Continued)

INJECTION THRESHOLD REGISTER (lJTR)
The Injection Threshold Register, in conjunction with the Injection Control bits (IC< 1:0» in the Current Transmit State Register
(CTSR), set the frequency at which the Injection Symbol Register A (ISRA) and Injection Symbol Register B (ISRB) are inserted
into the data stream. It contains the start value for the Injection Counter.
The Injection Threshold Register value is loaded into the Injection Counter when the counter reaches zero or during every
Control Bus Interface write-cycle of this register.
The'lnjection Counter is an 8-bit down-counter which decrements every 80 ns. Its current value is read for CIJCR.
The counter is active only during One Shot or Periodic Injection Modes (i.e. Injection Control<1:0> bits (lC<1:0» of the
Current Transmit State Register (CTSR) are set to either 01 or 10). The Transmitter Block will replace a data symbol pair with
ISRA and ISRB when the counter reaches 0 and the Injection Mode is either One Shot or Periodic.
If the Injection Threshold Register is set to 0 during the One Shot mode, the JK will be replaced with ISRA and ISRB. If the
Injection Threshold Register is set to 0 during the Periodic mode, all data symbols are replaced with ISRA and ISRB.
The counter is initialized to 0 during the reset process (i.e. RST = GND).
For further information, see the' Injection Control Logic subsection within Section 3.2.
ACCESS RULES
ADDRESS

I
07

I

IJT7

Bit

Always

06

I

WRITE

READ

I

05h

IJT6

I

05

I

IJT5

Always

04

I

IJT4

I
02

03

I

IJT3

Symbol

I

IJT2

01

I

IJT1

DO

I

IJTO

I

Description

00

IJTO

INJECTION THRESHOLD BIT <0>: Least significant bit (LSB) of the start
value for the Injection Counter.

01-6

IJTl-6

INJECTION THRESHOLD BIT < 1-6>: Intermediate bits of start value for the
Injection Counter.

07

IJT7

INJECTION THRESHOLD BIT <7>: Most significant bit (MSB) of the start
value for the Injection Counter.

2-64

c
5.0 Registers

~

(Continued)

Co)

N
U1

INJECTION SYMBOL REGISTER A (ISRA)
The Injection Symbol Register A, along with Injection Symbol Register B, contains the programmable value (already in 5B code)
that will replace the data symbol pairs.
The One Shot mode, ISRA and ISRB are injected n bytes after the next JK, where n is the programmed value of the Injection
Threshold Register. In the Periodic mode, ISRA and ISRB are injected every nth symbol pair. In the Continuous mode, all data
symbols are replaced with ISRA and ISRB.
ACCESS RULES
ADDRESS

I
D7

I

READ

I

06h

RES
Bit

Always

D6

I

RES

I

"'CJ

c»
Co)
N
U1
U1

WRITE

I

D5
RES

.....

"C

Always

D4

I

IJS4

I
D2

D3

I

IJS3

Symbol

I

IJS2

D1

I

IJS1

DO

I

IJSO

I

Description

00

IJSO

INJECTION THRESHOLD BIT <0>: Least significant bit (LSB) of Injection
Symbol Register A.

01-3

iJSl-3

INJECTION THRESHOLD BIT < 1-3>: intermediate bits of Injection Symbol
RegisterA.

04

IJS4

INJECTION THRESHOLD BIT <4>: Most significant bit (MSB) of injection
Symbol Register A.

05

RES

RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.

D6

RES

RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.

07

RES

RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.

•
2-65

it)
it)

C'I
C")

5.0 Registers (Continued)

CCI

a.
Q
......
.,..
it)

C'I

C")

CCI

a.
Q

INJECTION SYMBOL REGISTER B (ISRB)
The Injection Symbol Register B, along with Injection Symbol Register A, contains the programmable value (already in 5B code)
that will replace the data symbol pairs.
The One Shot mode, ISRA and ISRB are injected n bytes after the next JK, where n is the programmed value of the Injection
Threshold Register. In the Periodic mode, ISRA and ISRB are injected every nth symbol pair. In the Continuous mode, all data
symbols are replaced with ISRA and ISRB.
ACCESS RULES
ADDRESS

I
07

I

READ

I

07h

RES

Bit

Always

06

I

RES

WRITE

I

05

I

RES

Always

04

I

IJS9

I
03

I

02

IJS8

I

Symbol

IJS7

01

I

IJS6

DO

I

IJS5

I

Description

00

IJS5

INJECTION THRESHOLD BIT<5>: Least significant bit (LSB) of Injection
Symbol Register B.

01-3

IJS6-8

INJECTION THRESHOLD BIT <6-8>: Intermediate bits of Injection Symbol
Register B.

04

IJS9

INJECTION THRESHOLD BIT <9>: Most significant bit (MSB) of Injection
Symbol Register B.

05

RES

RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.

06

RES

RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.

07

RES

RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. The reserved bit is set to 1 during the reset
process. It may be set or cleared without any effects to the functionality of the PLAYER
device.

2-66

C

5.0 Registers

"'tI
CCI

(Continued)

IN
N
U1

CURRENT RECEIVE STATE REGISTER (CRSR)
The Current Receive State Register represents the current line state being detected by the Receiver Block. Once the Receiver
Block recognizes a new Line State, the bits corresponding to the previous line state are cleared, and the bits corresponding to
the new line state are set.
During the reset process (RST = GND), the Receiver Block is forced to Line State Unknown (Le. the Line State Unknown bit
(LSU) is set to 1).
ACCESS RULES
ADDRESS
08h

READ

WRITE

Always

Write Reject

D7

D6

D5

D4

D3

D2

D1

DO

RES

RES

RES

RES

LSU

LS2

LS1

LSO

Bit

Symbol

00,01
02

LSO, LS1,
LS2

..........
C

"'tI
CCI

IN
N
U1
U1

Description
LINE STATE <0, 1,2>: These bits represent the current Line State being detected by the Receiver
Block. Once the Receiver Block recognizes a new line state, the bits corresponding to the previous
line state are cleared, and the bits corresponding to the new line state are set.
LS2
0

LS1
0

LSO
0

0

0

1

Idle Line State (ILS): Received a minimum
of two consecutive Idle symbol pairs (11111
11111).

0

1

0

No Signal Detect (NSD): The Signal Detect
pin (TTLSD) has been deasserted, indicating
that the Clock Recovery Device is not
receiving data from the Fiber Optic Receiver.

0

1

1

Reserved: Reserved for future use.

1

0

0

Master Line State (MLS): Received a
minimum of 8 consecutive Halt-Quiet symbol
pairs (0010000000).

1

0

1

Halt Line State (HLS): Received a minimum
of 8 consecutive Halt symbol pairs (00100
00100).

1

1

0

Quiet Line State (QLS): Received a
minimum of 8 consecutive Quiet symbol pairs
(0000000000).

1

1

1

Noise Line State (NLS): Detected a
minimum of 16 noise events. Refer to the
Receiver Block for further information on
noise events.

Active Line State (ALS): Received a JK
symbol pair (11 000 10001), and possibly
followed by data symbols.

03

LSU

LINE STATE UNKNOWN: The Receiver Block has not detected the minimum conditions to enter a
known line state. When the Line State Unknown bit is set, LS < 2:0 > represent the most recently
known line state.

04

RES

RESERVED: Reserved for future use. The reserved bit is set to O.
Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore
the Control Bus write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition
Register (ICR) to 1.

2-67

•

5.0 Registers (Continued)
CURRENT RECEIVE STATE REGISTER (CRSR) (Continued)
Bit

Symbol

05

RES

Description
RESERVED: Reserved for future use. The reserved bit is set to O.
Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore the
CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1.

06

RES

RESERVED: Reserved for future use. The reserved bit is set to O.
Note: Users are discouraged from using this bit. An attempt to write into this bH will cause the PLAYER device to ignore the
CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (lCR) to 1.

07

RES

RESERVED: Reserved for future use. The reserved bit is set to O.
Note: Users are discouraged from using this bit. An attempt to write into this bit will cause the PLAYER device to ignore the
CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (lCR) to 1.

2-68

5.0 Registers

(Continued)

RECEIVE CONDITION REGISTER A (RCRA)
The Receive Condition Register A maintains a historical record of the Line States recognized by the Receiver Block.
When a new Line State is entered, the bit corresponding to that line state is set to 1. The bits corresponding to the previous Line
States are not cleared by the PLAYER device, thereby maintaining a record of the Line States detected.
The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register A is set to 1 and the corresponding mask bit(s) in Receive Condition Mask Register A (RCMRA) is
also set to 1.
ACCESS RULES
ADDRESS

I
07

I

LSUPI
Bit

READ

I

09h

06

I

WRITE

Always

I

Conditional

05

I

LSC

NT

04

I

I
D3

NLS

I

D2

MLS

Symbol

I

HLS

D1

I

QLS

DO

I

NSD

I

Description

DO

NSD

NO SIGNAL DETECT: Indicates that the Signal Detect pin (TTLSD) has been
deasserted and that the Clock Recovery Device is not receiving data from the
Fiber Optic Receiver.

D1

QLS

QUIET LINE STATE: Received a minimum of eight consecutive Quiet symbol
pairs (00000 00000).

D2

HLS

HALT LINE STATE: Received a minimum of eight consecutive Halt symbol
pairs (00100 00100).

D3

MLS

MASTER LINE STATE: Received a minimum of eight consecutive Halt-Quiet
symbol pairs (00100 00000).

D4

NLS

NOISE LINE STATE: Detected a minimum of sixteen noise events.

D5

NT

NOISE THRESHOLD: This bit is set to 1 when the internal Noise Counter
reaches O. It will remain set until a value equal to or greater than one is
loaded into the Noise Threshold Register or Noise Prescale Threshold
Register.
During the reset process (i.e. RST = GND), since the Noise Counter is
initialized to 0, the Noise Threshold bit will be set to 1.

D6

LSC

LINE STATE CHANGE: A line state change has been detected.

D7

LSUPI

LINE STATE UNKNOWN & PHY INVALID: The Receiver Block has not
detected the minimum conditions to enter a known line state.
In addition, the most recently known line state was one of the following line
states: No Signal Detect, Quiet Line State, Halt Line State, Master Line State,
or Noise Line State.

2-69

Lt)
Lt)

C'I
C")

co
a..
Q

"....
Lt)

C'I
C")

co
a..
Q

5.0 Registers (Continued)
RECEIVE CONDITION REGISTER B (RCRB)
The Receive Condition Register B maintains a historical record of the Line States recognized by the Receiver Block.
When a new Line State is entered, the bit corresponding to that line state is set to 1. The bits corresponding to the previous Line
States are not clear by the PLAYER device, thereby maintaining a record of the Line States detected.
The-Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition Register B is set to 1 and the corresponding mask bits in Receive Condition Mask Register B (RCMRB) is
also set to 1.
ACCESS RULES
ADDRESS

I
07

I

READ

I

OAh

RES

Bit

Always

06

I

SILS

WRITE

I

Conditional

05

I

EBOU

04

I

CSE

I
03

I

02

LSUPV

Symbol

I

ALS

01

I

ST

DO

I

ILS

I

Description

DO

ILS

IDLE LINE STATE: Received a minimum of two consecutive Idle symbol
pairs (11111 11111).

D1

ST

STATE THRESHOLD: This bit will be set to 1 by the PLAYER device when
the internal State Counter reaches zero. It will remain set until a value equal
to or greater than one is loaded into the State Threshold Register or State
Prescale Threshold Register, and this register is cleared.
During the reset process (I.e. RST = GND), since the State Counter is
initialized to 0, the State Threshold bit is set to 1.

D2

ALS

ACTIVE LINE STATE: Received a JK symbol pair (1100010001), and
possibly data symbols following.

D3

LSUPV

LINE STATE UNKNOWN & PHY VALID: Receiver Block has not detected
the minimum conditions to enter a know line state when the most recently
known line state was one of the following line states: Active Line State or Idle
Line State

D4

CSE

CASCADE SYNCHRONIZATION ERROR: When a synchronization error
occurs, the Cascade Synchronization Error bit is set to 1.
A synchronization error occurs if the Cascade Start signal (CS) is not asserted
within approximately 80 ns of Cascade Ready (CR) release.

D5

EBOU

ELASTICITY BUFFER UNDERFLOWIOVERFLOW: The Elasticity Buffer
has either overflowed or underflowed. The Elasticity Buffer will automatically
recover if the condition which caused the error is only transient.

D6

SILS

SUPER IDLE LINE STATE: Received a minimum of eight Idle symbol pairs
(11111 11111).

D7

RES

RESERVED: Reserved for future use. The reserved bit is set to 0 during the
reset process.
Note: Users are discouraged from uSin~ this bit. It may be set or cleared without any
effects to the functionality of the PLAY R device.

2-70

5.0 Registers (Continued)
RECEIVE CONDITION MASK REGISTER A (RCMRA)
The Receive Condition Mask Register A allows the user to dynamically select which events will generate an interrupt.
The Receive Condition A bit (RCA) of the Interrupt Condition Register (lCR) will be set to 1 when one or more bits within the
Receive Condition Register A (RCRA) is set to 1 and the corresponding mask bites) in this register is also set to 1.
Since this register is cleared (i.e. set to 0) during the reset process, all interrupts are initially masked.
ACCESS RULES
ADDRESS

I

I

OSh

07

I

READ

LSUPIM

Bit

Always

06

I

WRITE

I

05

LSCM

I

NTM

04

I

I

Always

03

NLSM

I

02

MLSM

Symbol

I

HLSM

01

I

QLSM

DO

I

NSOM

I

Description

00

NSOM

NO SIGNAL DETECT MASK: The mask bit for the No Signal Oetect bit (NSO)
of the Receive Condition Register A (RCRA).

01

QLSM

QUIET LINE STATE MASK: The mask bit for the Quiet Line State bit (QLS) of
the Receive Condition Register A (RCRA).

02

HLSM

HALT LINE STATE MASK: The mask bit for the Halt Line State bit (HLS) of
the Receive Condition Register A (RCRA).

03

MLSM

MASTER LINE STATE MASK: The mask bit for the Master Line State bit
(MLS) of the Receive Condition Register A (RCRA).

04

NLSM

NOISE LINE STATE MASK: The mask bit for the Noise Line State bit (NLS)
of the Receive Condition Register A (RCRA)

05

NTM

NOISE THRESHOLD MASK: The mask bit for the Noise Threshold bit (Nn of
the Receive Condition Register A (RCRA).

06

LSCM

LINE STATE CHANGE MASK: The mask bit for the Line State Change bit
(LSC) of the Receive Condition Register A (RCRA).

07

LSUPIM

LINE STATE UNKNOWN & PHY INVALID MASK: The mask bit for the line
State Unknown & PHY Invalid bit (LSUPI) of the Receive Condition Register A
(RCRA).

2-71

It)
It)

~
co

a.
Q

.....
....

It)

N

('I)

co

a.
Q

5.0 Registers (Continued)
RECEIVE CONDITION MASK REGISTER B (RCMRB)
The Receive Condition Mask Register B allows the user to dynamically select which events will generate an interrupt.
The Receiver"ConditionB bit (RCB) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the
Receive Condition B (RCRA) is set to 1 and the corresponding mask bits in this register is also set to 1.
Since this register is cleared (i.e. set to 0) during the reset process, all interrupts are initially masked.
ACCESS RULES
ADDRESS

I
07

I

RES

Bit

READ

I

OCh

Always

06

I

SILSM

WRITE

I

05

I

EBOUM

Always

04

I

I
03

CSEM

I

02

LSUPVM

Symbol

I

ALSM

DO

01

I

STM

I

ILSM

I

Description

DO

ILSM

IDLE LINE STATE MASK: The mask bitforthe Idle Line State bit (ILS) of the
Receive Condition Register B (RCRB).

01

STM

STATE THRESHOLD MASK: The mask bit of the StateThreshold bit (Sn of
the Receive Condition Register B (RCRB).

02

ALSM

ACTIVE LINE STATE MASK: The mask bit for the Active Line State bit (ALS)
"of the Receive Condition Register B (RCRB).

03

LSUPVM

LINE STATE UNKNOWN & PHY VALID MASK: The mask bitfor the Line
State Unknown & PHY Valid bit (LSUPV) of the Receive Condition Register B
(RCRB).

04

CSEM

CASCADE SYNCHRONIZATION ERROR MASK: The mask bit for the
Cascade Synchronization Error bit (CSE) of the Receive Condition Register B
(RCRB)."

05

EBOUM

ELASTICITY BUFFER OVERFLOWIUNDERFLOW MASK: The mask bit for
the ElasticitY Buffer Overflow/Underflow bit (EBOU) of the Receive Condition
Register B (RCRB).

06

SILSM

SUPER IDLE LINE STATE MASK: The mask bitfor the Super Idle Line State
bit (SILS) of the Receive Condition Register B (RCRB).

07

RESM

RESERVED MASK: The mask bit for the Reserved bit (RES) of the Receive
Condition Register B (RCRB).

2·72

c

~

5.0 Registers (Continued)

~

NOISE THRESHOLD REGISTER (NTR)
The Noise Threshold Register contains the start value for the Noise Counter. This counter may be used in conjunction with the
Noise Prescale Counter for counting the Noise events. Definiton of Noise event is explained in detail in Section B.2. The Noise
Counter decrements once every BO ns if the noise Prescale counter is zero and there is a noise event. As a result, the internal
noise counter takes
((NPTR+ 1) x (NTR+1)) x BO ns

.........C

."
CO

Co)
II.)

en
en

to reach zero in the event of continuous Noise event.
The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true:
(1) Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State, Active
Line State, or Line State Unknown.
or
(2) The current Line State is either Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect
or
(3) The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle.
In addition, the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale
Counter reaches zero.
The Noise Counter and Noise Prescale Counter will continue to count, without resetting or reloading the threshold values, if a
Line State change occurs and the new line state is either Noise Line State, Active Line State or Line State Unknown.
When both the Noise Threshold Counter and Noise Counter both reach zero, the Noise Threshold bit of the Receive Condition
Register A will be set.
ACCESS RULES
ADDRESS

I
D7

I

READ

I

ODh

NT?

Bit

Always

D6

I

NT6

WRITE

I

D5

I

NT5

Always

D4

I

I
D3

NT4

I

D1

D2

NT3

Symbol

I

NT2

I

NT1

DO

I

NTO

I

Description

DO

NTO

NOISE THRESHOLD BIT: Least significant bit (LSB) of the start value
for the Noise Counter.

D1-5

NT1-5

NOISE THRESHOLD BIT < 1-5>: Intermediate bits of start value for the
Noise Counter.

D6

NT6

NOISE THRESHOLD BIT <6>: Most significant bit (MSB) of the start value
for the Noise Counter.

D7

RES

RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. Write data is ignored since the reserved
bit is permanently set to O.

fII

2·73

U)
U)

N

('f)

CD

a.
C
......
....
U)

N

('f)

~

C

r---------------------------------------------------------------------------------.
5.0 Registers (Continued)
NOISE PRESCALE THRESHOLD REGISTER (NPTR)
The Noise Prescale Threshold Register contains the start value for the· Noise Prescale Counter. The Noise Prescale Counter is a
count-down counter and it is used in conjunction with the Noise Counter for counting the Noise events. The Noise Pre scale
Counter decrements once every 80 ns while there is a noise event. When the Noise Prescale Counter reaches zero, it reloads
the count with the content of the Noise Prescale Threshold Register and also causes the Noise Counter to decrement.
The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true:
(1) Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State, Active
Line State, or Line State Unknown.
or
(2) The current Line State is either, Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect
or
(3) The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle.
In addition, the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale
Counter reaches zero.
The Noise Counter and Noise Prescale Counter will continue to count, without resetting or reloading the threshold values, if a
Line State change occurs and the new line state is either Noise Line State, Active Line State, or Line State Unknown.
When both the Noise Threshold Counter and Noise Counter both reach zero, the Noise Threshold bit of the Receive Condition
Register A will be set.
ACCESS RULES
ADDRESS

I
D7

I

NPT7

Bit
DO

01-6
07

READ

I

OEh

Always

D6

I

NPT6

WRITE

I

D5

I

NPT5

Always
D4

I

I
D3

NPT4

I

D2

NPT3

I

Symbol
NPTO
NPTI-6
NPT7

NPT2

D1

I

NPT1

DO

I

NPTO

I

Description
NOISE PRESCALE THRESHOLD BIT < 0>: Least significant bit (LSB) of the
start value of the Noise Prescale Counter.
NOISE PRESCALE THRESHOLD BIT: Intermediate bits of start
value for the Noise Prescale Counter.
NOISE PRESCALE THRESHOLD BIT < 7>: Most significant bit (MSB) of the
start value for the Noise Prescale Counter.

2-74

o

;g

5.0 Registers (Continued)

Co)

N
U1

CURRENT NOISE COUNT REGISTER (CNCR)
The Current Noise Count Register takes a snap-shot of the Noise Counter during every Control Bus Interface read-cycle of this
register.
During a Control Bus Interface write-cycle to the Current Noise Count Register, the PLAYER device will set the Control Bus
Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.

ACCESS RULES
ADDRESS

I
07

I

NCLSCD

Bit

READ

I

OFh

I

I

Write Reject

05

CNC6

I

co
Co)

N
U1
U1

WRITE

Always

06

....
o
"."

CNC5

03

04

I

CNC4

I

I

02

CNC3

Symbol

I

CNC2

01

I

CNC1

DO

I

CNCO

I

Description

DO-6

CNCO-6

CURRENT NOISE COUNT BIT <0-6>

D7

NCLSCD

NOISE COUNTER LINE STATE CHANGE DETECTION

•
2-75

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
U)

C'I

Cf)

~

Q
.....
....

~
Cf)
co

a.
Q

5.0 Registers (Continued)
CURRENT NOISE PRESCALE COUNT REGISTER (CNPCR)
The Current Noise Prescale Count Register takes a snap-shot of the Noise Prescale Counter during every Control Bus Interface
read-cycle of this register.
During a Control Bus Interface write-cycle to the Current Noise Prescale Count Register, the PLAYER device will set the Control
Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.

ACCESS RULES
ADDRESS
10h

D7

I

READ

WRITE

Always

Write Reject

D6

CNPC7

Bit
00-7

I

D5

CNPC6

I
I

I

CNPC5

Symbol
CNPCO-7

D4

I

D3

CNPC4

I
I

I

D1

D2

CNPC3

I

CNPC2

I

CNPC1

DO

I

CNPCO

Description
CURRENT NOISE PRESCALE COUNT BY <0-7>

2-76

I

C

5.0 Registers

"U

m
Co)

(Continued)

N
CI1

STATE THRESHOLD REGISTER (STR)
The State Threshold Register contains the start value of the State Counter. This counter is used in conjunction with the State
Prescale Counter to count the Line State duration. The State Counter will decrement every 80 ns if the State Prescale Counter is
zero and the current Line State is Halt Line, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect. State The
State Counter takes
«SPTR+ 1) x (STR+ 1» x 80 ns
to reach zero during a continuous line state condition.
The threshold values for the State Counter and State Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true:
(1) Both the State Counter and State Prescale Counter reach zero and the current Line State is Halt Line State, Idle Line State,
Master Line State, Quiet Line State, or No Signal Detect
or
(2) A line state change occurs and the new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or
No Signal Detect
or
(3) The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle.
In addition, the value of the State Prescale Threshold register is loaded into the State Prescale Counter if the State Prescale
Counter reaches zero.
The State Counter and State Prescale Counter will reset by reloading the threshold values, if a Line State change occurs and the
new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detect.

ACCESS RULES
ADDRESS

I
D7

I

READ

I

11h

ST7

Bit
DO

Always

D6

I

ST6

WRITE

I

D5

I

ST5

Always

D4

I

I
D3

ST4

I

D2

ST3

I

D1

I

ST1

DO

I

STO

I

Description

Symbol
STO

ST2

STATE THRESHOLD BIT <0>: Least significant bit (LSB) of the start value
for the State Counter.

01-5

ST1-5

STATE THRESHOLD BIT < 1-5>: Intermediate bits of start value for the
State Counter.

06

ST6

STATE THRESHOLD BIT < 6 >: Most significant bit (MSB) of the start value
for the State Counter.

07

RES

RESERVED: Reserved for future use.
Note: Users are discouraged from using this bit. Write data is ignored since the reserved

bit is permanently set to O.

2·77

....
.....
C

"U

m
Co)

N
CI1
CI1

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
U)

~
co

5.0 Registers

(Continued)

a.

STATE PRESCALE THRESHOLD REGISTER (SPTR)

U)

The State Prescale Threshold Register contains the start value for the State Prescale Counter. The State Prescale Counter is a
down counter. The Register is used in conjunction with the State Counter to count the Line State duration.

c
.....
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C")

co

a.
C

The State Prescale Counter will decrement every 80 ns if the current Line State is Halt Line, Idle Line State, Master Line State,
Quiet Line State, or No Signal Detect. As a result, the State Prescale Counter takes SPTR x 80 ns to reach zero during a
continuous line state condition. When the State Prescale Counter reaches zero, the State Prescale Threshold Register will be
reloaded into the State Prescale Counter.
The threshold values for the State Counter and State Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true:
(1) Both the State Counter and State Prescale Counter reach zero and the current Line State is Halt Line State, Idle Line State,
Master Line State, Quiet Line State, or No Signal Detect.
or
(2) A Line State change occurs and the new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or
No Signal Detect
or
(3) The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle.
The State Counter and State Prescale Counter will reset by reloading the threshold values, if a Line State change occurs and the
new Line State is Halt Line State, Idle Line State, Master Line State, Quiet Line State, or No Signal Detec.t.
ACCESS RULES
ADDRESS

I
D7

I

SPT7

Bit

Always

D6

I

WRITE

READ

I

12h

SPT6

I
D4

D5

I

SPT5

Always

I

I
D2

D3

SPT4

I

SPT3

I

Symbol

SPT2

D1

I

SPT1

DO

I

SPTO

I

Description

DO

SPTO

STATE PRESCALE THRESHOLD BIT <0>: Least significant bit (LSB) of
the start value for the State Prescale Counter.

01-6

SPT1-6

STATE PRESCALE THRESHOLD BIT < 1"'6>: Intermediate bits of start
value for the State Prescale Counter.

07

SPT7

STATE PRESCALE THRESHOLD BIT < 7 >: Most significant bit (MSB) of
the start value for the State Prescale Counter.

2-78

.----------------------------------------------------------------------.0
5.0 Registers

"'U

co
Co)

(Continued)

N
U'I

CURRENT STATE COUNT REGISTER (CSCR)
The Current State Count Register takes a snap-shot of the State Counter during every Control Bus Interface read-cycle of this
register.
During a Control Bus Interface write-cycle to the Current State Count Register, the PLAYER device will set the Control Bus Write
Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 and will ignore a write-cycle.
ACCESS RULES
ADDRESS

I
07

I

Bit

I

CSC6

I

Always

06

SCLSCD

Write Reject

04

05

I

,

WRITE

READ

I

13h

CSC5

I

CSC4

I
03

I

02

CSC3

Symbol

I

CSC2

01

I

CSCI

DO

I

CSCO

I

Description

< 0-6 >

DO-6

CSCO-6

CURRENT STATE COUNT BIT

D7

SCLSCD

STATE COUNTER LINE STATE CHANGE DETECTION

2-79

....
.....
o"'U
co
Co)

N
U'I
U'I

5.0 Registers (Continued)
CURRENT STATE PRESCALE COUNT REGISTER (CSPCR)
The Current State Prescale Count Register takes a snap-shot of the State Prescale Counter during every Control Bus interface
read-cycle of this register.
During a Control Bus Interface write-cycle to the Current State Prescale Count Register, the PLAYER device will set the Control
Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (lCR) to 1 and will ignore a write-cycle.
ACCESS RULES
ADDRESS

I
D7

READ

I

14h

Always

D6

I CSPC7 I
Bit
00-7

CSPC6

WRITE

I

D5

I
I
I

CSPC5

I

Write Reject
D3

D4

I

CSPC4

Symbol
CSPCO-7

I

D2

CSPC3

I
I

I

CSPC2

D1

I

DO

CSPC1

I

CSPCO

I

Description
CURRENT STATE PRESCALE COUNT <0-7>

2-80

C

""0

5.0 Registers

(XI
Co)

(Continued)

...
N

LINK ERROR THRESHOLD REGISTER (LETR)

U1

The Link Error Threshold Register contains the start value for the Link Error Monitor Counter, which is an 8-bit down-counter that
decrements if link errors are detected.
When the Counter reaches 0, the Link Error Monitor Threshold Register value is loaded into the Link Error Monitor Counter and
the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition Register (ICR) is set to 1.
The Link Error Monitor Threshold Register value is also loaded into the Link Error Monitor Counter during every Control Bus
Interface write-cycle of LETR.

C

""0
(XI
Co)

N

U1

U1

The Counter is initialized to 0 during the reset process (i.e. RST = GND).
ACCESS RULES
ADDRESS

I
07

I

READ

I

15h

LET7

Bit

06

I

LET6

WRITE

I

Always

D5

I

LET5

Always

D4

I

I
D3

LET4

I

D1

D2

LET3

Symbol

I

LET2

I

LET1

DO

I

LETO

I

Description

DO

LETO

LINK ERROR THRESHOLD BIT <0>: Least significant bit of the start value
for the Link Error Monitor Counter.

D1-6

LET1-6

LINK ERROR THRESHOLD BIT < 1-6>: Intermediate bits of start value for
the Link Error Monitor Counter.

D7

LET7

LINK ERROR THRESHOLD BIT <7>: Most significant bit of the start value
for the Link Error Monitor Counter.

FJI

2-81

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
U)

N

('I)

~
Q

.....
....
U)

~

~

Q

5.0 Registers (Continued)
CURRENT LINK ERROR COUNT REGISTER (CLECR)
The Current Link Error Count Register takes a snap-shot of the Link Error Monitor Counter during every Control Bus Interface
read-cycle of this register.
During a Control Bus Interface write-cycle, the PLAYER device will set the Control Bus Write Command Reject bit (CCR) of the
Interrupt Condition Register (lCR) to 1 and will ignore a write-cycle.
ACCESS RULES
ADDRESS

I
D7

I

LEC7

READ

I

16h

Always

D6

I
Bit
00-7

LEC6

WRITE

I

Write Reject

D5

I

LEC5

I
I

D4

I

LEC4

I
D2

D3

I

LEC3

I
I
I

Symbol
LECO-7

2-82

LEC2

D1

I

LEC1

DO

I

LECO

I

Description
LINK ERROR COUNT BIT <0-7>

C

5.0 Registers

'a
00

(Continued)

Co)

USER DEFINABLE REGISTER (UDR)
The User Definable Register is used to monitor and control events which are external to the PLAYER device.
The value of the Sense Bits reflects the asserted/deasserted state of their corresponding Sense pins. On the other hand, the
Enable bits assert/ deassert the Enable pins.

I

READ

I

17h
D7
RES

Bit

Always

D6

I

....
.....
C

'a
00
Co)

N

ACCESS RULES
ADDRESS

I

N

c.n

RES

I

D5

I

RES

c.n
c.n

WRITE
Always
D4

I

RES

I
D3

I

D2

EB1

Symbol

I

EBO

DO

D1

I

SB1

I

SBO

I

Description

DO

SBO

SENSE BIT 0: This bit is set to 1 if the Sense Pin 0 (SPO) is asserted (i.e. SPO = Vee! for a minimum of
160 ns. Once the asserted signal is latched, Sense Bit 0 can only be cleared through the Control Bus
Interface, even if the signal is deasserted. This ensures that the Control Bus Interface will record the
source of events which can cause interrupts in a traceable manner.

D1

SB1

SENSE BIT 1: This bit is set to 1 if the Sense Pin 1 (SP1) is asserted (i.e. SP1 = Vee! for a minimum of
160 ns. Once the asserted signal is latched, Sense Bit 1 can only be cleared through the Control Bus
Interface, even if the signal is deasserted. This ensures that the Control Bus Interface will record the
source of events which can cause interrupts in a traceable manner.

D2

EBO

ENABLE BIT 0: The Enable Bit 0 allows control of external logic through the Control Bus Interface. The
User Definable Enable Pin 0 (EPO) is asserted/deasserted by this bit.
0: EPO is deasserted (i.e. EPO = GND).
1: EPO is asserted (i.e. EPO = Vee).

D3

EB1

ENABLE BIT 1: This bit allows control of external logic through the Control Bus Interface. The User
Definable Enable Pin 0 (EPO) is asserted/deasserted by this bit.
0: EP1 is deasserted (i.e. EP1 = GND).
1: EP1 is asserted (i.e. EP1 = Vee!.

D4-7

RES

RESERVED: Reserved for future use. The reserved bit is set to 0 during the initialization process
(i.e. RST = GND).
Nole: Users are discouraged from using this bit. It may be set or cleared without any effects to the functionality of the
PLAYER device.

II

2-83

~
~

~

CIO
~

......
~

~

~

C

,---------------------------------------------------------------------------------,
5.0 Registers (Continued)
DEVICE ID REGISTER (IDR)

The Device 10 Register contains the binary equivalent of the revision number for this device. It can be used to ensure proper
software and hardware versions are matched.
During the Control Bus Interface write-cycle, the PLAYER device will set the Control Bus Write Command Register bit (CCR) of
the Interrupt Condition Register (ICR) to 1, and will ignore write-cycle.
ACCESS RULES
ADDRESS

I

I

18h
D7

I

READ

0107

Bit

Always

D6

I

0106

WRITE

I

Write Reject

D5

I

0105

D4

I

I
D3

0104

I

D2

0103

I

Symbol

0102

DO

D1

I

0101

I

DIDO

I

Description

DO

DIDO

DEVICE ID BIT <0>: Least significant bit (LSB) of the revision number.

01-6

0101-6

DEVICE ID BIT

07

0107

DEVICE ID BIT

< 1-0-6>: Intermediate bits of the revision number.
<7>: Most significant bit (MSB) of the revision number.

2-84

,----------------------------------------------------------------------, C
"'til
co
5.0 Registers (Continued)
(0)
N

CURRENT INJECTION COUNT REGISTER (CIJCR)

....
.....
C
;g
(II

The Current Injection Count Register takes a snap-shot of the Injection Counter during every Control Bus Interface read-cycle of
this register.
During a Control Bus Interface write-cycle, the PLAYER device will set the Control Bus Write Command Reject bit (CCR) of the
Interrupt Condition Register (lCR) to 1 and will ignore a write-cycle.
The Injection Counter is an 8-bit down-counter which decrements every 80 ns.

(0)

N

(II
(II

The counter is active only during One Shot or Periodic Injection Modes (i.e. Injection Control <1:0> bits (IC<1:0» of the
Current Transmit State Register (CTSR) are set to either 01 or 10).
The Injection Threshold Register (IJTR) value is loaded into the Injection Counter when the counter reaches zero and during
every Control Bus Interface write-cycle of IJTR.
The counter is initialized to
ACCESS RULES
ADDRESS

I
07

I

IJC7

Bit

Always

06

I

IJC6

I

Write Reject

05

I

IJC5

GND).

WRITE

READ

I

19h

a during the reset process (i.e. RST =

04

I

I
03

IJC4

I

02

IJC3

Symbol

I

IJC2

01

I

IJC1

DO

I

IJCO

I

Description

DO

IJCO

INJECTION COUNT BIT <0>: least significant bit (lSB) of the current value
of the Injection Counter.

D1-6

IJC1-6

INJECTION COUNT BIT < 1-6>: Intermediate bits representing the current
value of the Injection Counter.

D7

IJC7

INJECTION COUNT BIT <7>: Most significant bit (MSB) of the current
value of the Injection Counter.

II

2-85

5.0 Registers (Continued)
INTERRUPT CONDITION COMPARISON REGISTER (ICCR)
The Interrupt Condition Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER device
before it can be written to by the Control Bus Interlace.
The current state of the Interrupt Condition Register (ICR) is automatically written into the Interrupt Condition Comparison
Register (i.e. ICCR = ICR) during a Control Bus Interface read-cycle of ICA.
During a Control Bus Interlace write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within ICR when the value of a bit in ICR differs from the
value of the corresponding bit in the Interrupt Condition Comparison Register.
ACCESS RULES
ADDRESS

I

07

I

UDIC

Bit

READ

I

1Ah

06

I

RCBC

WRITE

I

Always

05

I

RCAC

Always

04

I

I
03

LEMTC

I

02

CWIC

Symbol

I

CCRC

01

I

CPEC

DO

I

DPEC

I

Description

DO

DPEC

PHY-REQUEST DATA PARITY ERROR COMPARISON: The comparison
bit for the PHY_Request Data Parity Error bit (OPE) of the Interrupt Condition
Register (lCR).

D1

CPEC

CONTROL BUS DATA PARITY ERROR COMPARISON: The comparison bit
for the Control Bus Data Parity Error bit (CPE) of the Interrupt Condition
Register (ICR).

02

CCRC

CONTROL BUS WRITE COMMAND REJECT COMPARISON: The
comparison bit for the Control Bus Write Command Reject bit (CCR) of the
Interrupt Condition Register (ICR).

D3

CWIC

CONDITIONAL WRITE INHIBIT COMPARISON: The comparison bit for the
Conditional Write Inhibit bit (CWI) of the Interrupt Condition Register (lCR).

04

LEMTC

LINK ERROR MONITOR THRESHOLD COMPARISON: The comparison bit
for the Link Error Monitor Threshold bit (LEMn of the Interrupt Condition
Register (lCR).

05

RCAC

RECEIVE CONDITION A COMPARISON: The comparison bit for the
Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR).

06

RCBC

RECEIVE CONDITION B COMPARISON.: The comparison bit for the
Receive Condition B bit (RCB) of the Interrupt Condition Register (lCR).

07

UDIC

USER DEFINABLE INTERRUPT COMPARISON: The comparison bit for the
User Definable Interrupt bit (UDIC) of the Interrupt Condition Register (lCR).

2-86

5.0 Registers (Continued)
CURRENT TRANSMIT STATE COMPARISON REGISTER (CTSCR)
The Current Transmit State Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER
device before it can be written to by the Control Bus Interface.
The current state of the Current Transmit State Register (CTSR) is automatically written into the Current Transmit State
Comparison Register A (i.e. CTSCR = CTSR) during a Control Bus Interface read-cycle of CTSR.
During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (lCR) to 1 and disallow the setting or clearing of a bit within the CTSR when the value of a bit in the CTSR
differs from the value of the corresponding bit in the Current Transmit State Comparison Register.
ACCESS RULES
ADDRESS

I

I

Bit

Always

06

07
RESC

READ

I

1Bh

I

WRITE

I

05

PROPEC

I

SEC

Always

04

I

IC1C

I
02

03

I

ICOC

I

TM2C

01

I

TM1C

DO

I

TMOC

I

Description

Symbol

DO

TMOC

TRANSMIT MODE <0> COMPARISON: The comparison bitfor the
Transmit Mode < 0 > (TMO) of the Current Transmit State Register (CTSR).

D1

TM1C

TRANSMIT MODE < 1 > COMPARISON: The comparison bit for the
Transmit Mode < 1 > bit (TM1) of the Current Transmit State Register
(CTSR).

D2

TM2C

TRANSMIT MODE < 2> COMPARISON: The comparison bit for the
Transmit Mode < 2 > bit (TM2) of the Current Transmit State Register
(CTSR).

D3

ICOC

INJECTION CONTROL <0> COMPARISON: The comparison bit for the
Injection Control <0> bit (I CO) of the Current Transmit State Register
(CTSR).

04

IC1C

INJECTION CONTROL < 1 > COMPARISON: The comparison bit for the
Injection Control < 1 > bit (IC1) of the Current Transmit Register (CTSR).

05

SEC

SMOOTHER ENABLE COMPARISON: The comparison bit for the Smoother
Enable bit (SE) to the Current Transmit State Register (CTSR).

06

PROPEC

PHY_REQUEST DATA PARITY ENABLE COMPARISON: The comparison
bit for the PHY_Request Data Parity Enable bit (PROPE) of the Current
Transmit State Register (CTSR).

07

RESC

RESERVED COMPARISON: The comparison bit for the Reserved bit (RES)
of the Current Transmit State Register (CTSR).

•
I

2-87

5.0 Registers (Continued)
RECEIVE CONDITION COMPARISON REGISTER A (RCCRA)
The Receive Condition Comparison Register A ensures that the Control Bus must first read a bit modified by the PLAYER device
before it can be written to by the Control Bus Interface.
The current state of RCRA is automatically written into the Receive Condition Comparison Register A (i.e. RCCRA = RCRA)
during a Control Bus Interface read-cycle of RCRA.
During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWll of the Interrupt
Condition Register (lCR) to 1 and prevent the setting or clearing of a bit within RCRA when the value of.a bit in RCRA differs
from the value of the corresponding bit in the Receive Condition Comparison Register A.
ACCESS RULES
ADDRESS

I

I

D7

I

READ

1Ch

LSUPIC

D6

I

LSCC

WRITE

I

Always
D5

I

D4

NTC

I

I

Always

NLSC

I

D1

D2

D3
MLSC

I

HLSC

I

QLSC

DO

I

NSDC

I

Bit

Symbol

DO

NSDC

NO SIGNAL DETECT COMPARISON: The comparison bit for the No Signal Detect bit
(NSDl of the Receive Condition Register A (RCRA).

Description

D1

QLSC

QUIET LINE STATE COMPARISON: The comparison bit for the Quiet Line State bit
(QLS) of the Receive Condition Register A (RCRAl.

D2

HLSC

HALT LINE STATE COMPARISON: The comparison bit for the Halt Line State bit (HLSl
of the Receive Condition Register A (RCRA).

D3

MLSC

MASTER LINE STATE COMPARISON: The comparison bit for the Master Line State bit
(MLSl of the Receive Condition Register A (RCRA).

04

NLSC

NOISE LINE STATE COMPARISON: The comparison bit for the Noise Line State bit
(NLS) of the Receive Condition Register A (RCRA).

D5

NTC

NOISE THRESHOLD COMPARISON: The comparison bit for the Noise Threshold bit
(NT) of the Receive Condition Register A (RCRAl.

06

LSCC

LINE STATE CHANGE COMPARISON: The comparison bit for the Line State Change
bit (LSC) of the Receive Condition Register A (RCRA).

07

LSUPIC

LINE STATE UNKNOWN" PHY INVALID COMPARISON: The comparison bit for the
Line State Unknown & PHY Invalid bit (LSUPI) of the Receive Condition Register A
(RCRA).

2-88

5.0 Registers

(Continued)

RECEIVE CONDITION COMPARISON REGISTER B (RCCRB)
The Receive Condition Comparison Register B ensures that the Control Bus must first read a bit modified by the PLAYER device
before it can be written to by the Control Bus Interface.
The current state of RCRB is automatically written into the Receive Condition Comparison Register B (i.e. RCCRB = RCRB)
during a Control Bus Interface read-cycle RCRB.
During a Control Bus Interface write-cycle, the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRB when the value of a bit in RCRB differs
from the value of the corresponding bit in the Receive Condition Comparison Register B.
ACCESS RULES
ADDRESS

I

06

07

I

I

1Dh

RESC

READ

I

SILSC

WRITE

I

Always

05

I

I

Always

04

EBOUC

I

CSEC

02

03

I

LSUPVC

I

ALSC

DO

01

I

STC

I

ILSC

I

Bit

Symbol

DO

ILSC

IDLE LINE STATE COMPARISON: The comparison bit for the Idle State bit (ILS) of the
Receive Condition Register B (RCRB).

Description

D1

STC

STATE THRESHOLD COMPARISON: The comparison bit for the State Threshold bit
(ST) of the Receive Condition Register B (RCRB).

D2

ALSC

ACTIVE LINE STATE COMPARISON: The comparison bit for the Active Line State bit
(ALS) of the Receive Condition Register B (RCRB).

D3

LSUPVC

LINE STATE UNKNOWN 8. PHY VALID COMPARISON: The comparison bit for the Line
State Unknown & PHY Valid bit (LSUPV) of the Receive Condition Register B (RCRB).

D4

CSEC

CASCADE SYNCHRONIZATION ERROR COMPARISON: The comparison bit for the
Cascade Synchronization Error bit (CSE) of the Receive Condition Register B (RCRB).

D5

EBOUC

ELASTICITY BUFFER OVERFLOWIUNDERFLOW COMPARISON: The comparison bit
for the Elasticity Buffer Overflow/Underflow bit (EBOU) of the Receive Condition
Register B (RCRB).

D6

SILSC

SUPER IDLE LINE STATE COMPARISON: The comparison bit for the Super Idle Line
State bit (SILS) of the Receive Condition Register B (RCRB).

D7

RESC

RESERVED COMPARISON: The comparison bit for the Reserved bit (RES) of the
Receive Condition Register B (RCRB).

RESERVED REGISTER 0 (RRO) ADDRESS 1Eh-DO NOT USE
RESERVED REGISTER 1 (RR1) ADDRESS 1Fh-DO NOT USE

2-89

It)
It)

N

CW)

co

11.

Q

....
'"

It)

N

CW)

co

11.

Q

6.0 Pin Descriptions
6.1 DP83251
The pin descriptions for the DP83251 are divided into 5 functional interfaces: Serial Interface, PHY Port Interface, Control Bus
Interface, Clock Interface, and Miscellaneous Interface.
For a Pinout Summary List, refer to Table 6-1.
..,
..,
....
:;: c
0
0
c
'"0 0 0 0 0 0 i5 c0 "
"

e;

f!;

...en
u

...

en
u

en
u

...

>" uen

en
u

z

'"

...

en

u

en
u

z

'"

en
u

en
u

...... ...uen ......uen

>" uen

en

u

...
en
u

I~

iNT
CE

GND

12

PE

13

SPO

14

SP1

15

RST

74

0

73
72

R/W

AlP

16

BRP

Ale

17

BRC

AID7

18

BRD7

AID6

19

BROS

GND

20

AID5

21

Vee

22

AID4

23

DP83251
PLAYER
84-PIN PLCC

GND
BRD5

Vee
BRD4

GND

24

AID3

25

BRD3

AID2

26

BRD2

AID1

27

BRD1

AIDO

28

CS

29

GND

BRDO
57

LBC

CR

30

N/C

31

55

N/C

N/c

32

54

N/C

TXE

0

u

0

CIl

t=

en

;;:l

+

I

U

u

'"

'"

><

><

" ~
+
>u

I

0

><

0

z

'" '" '"

+

0

en

..J

...
I

0

..J

!:l +

>

~

l-

I

0

~

0

z

'"

+

u

><

I-

I

u

><

l-

Order Number DP83251V
See NS Package Number V84A
FIGURE 6-1. DP83251 84-Pln PLCC Pinout

2-90

<> +
u
>" ...

I-

I

...u

I-

~
TL/F/10388-20

6.0 Pin Descriptions (Continued)
TABLE 6-1. DP83251 Pinout Summary
Pin No.

Signal Name

Symbol

I/O

Eel/TTL/Open
Drain/Power

1

Control Bus Data < 2 >

CBD2

1/0

TTL

2

Control Bus Data < 3 >

CBD3

1/0

TTL

3

CMOS 1/0 Ground

GND

4

Control Bus Data < 4 >

CBD4

1/0

5

Control Bus Data < 5 >

CBD5

1/0

6

CMOS 1/0 Power

Vee

7

Control Bus Data <6>

CBD6

1/0

TTL

8

Control Bus Data < 7 >

CBD7

1/0

TTL

9

Control Bus Data Parity

CBP

1/0

TTL

10

Enable Pin 0

EPO

0

TTL

11

Enable Pin 1

EP1

0

TTL

+OV
TTL
TTL
+5V

12

CMOS Logic Ground

GND

13

Control Bus Data Parity Enable

CBPE

I

TTL

14

Sense Pin 0

SPO

I

TTL

15

Sense Pin 1

SP1

I

TTL

16

PHY Port A Indicate Parity

AlP

0

TTL

17

PHY Port A Indicate Control

AIC

0

TTL

18

PHY PortA Indicate Data<7>

AID7

0

TTL

19

PHY Port A Indicate Data < 6 >

AID6

0

20

CMOS 1/0 Ground

GND

+OV

TTL
+OV

0

21

PHY Port A Indicate Data < 5 >

AID5

22

CMOS 110 Power

Vee

TTL

23

PHY PortA Indicate Data<4>

AID4

24

CMOS Logic Ground

GND

25

PHY PortA Indicate Data<3>

AID3

0

26

PHY Port A Indicate Data < 2 >

AID2

0

TTL

27

PHY Port A Indicate Data < 1 >

AID1

0

TTL

+5V

0

TTL
+OV
TTL

28

PHY PortA Indicate Data

AIDO

0

TTL

29

Cascade Start

CS

0

TTL

30

Cascade Ready

CR

I

Open Drain

31

No Connect

N/C

I

TTL

32

No Connect

N/C

33

Clock Detect

CD

34

Signal Detect

TTLSD

I

TTL

35

External Loopback Enable

ELB

0

TTL

2-91

fI

6.0 Pin Descriptions (Continued)
TABLE 6·1. DP83251 Pinout Summary (Continued)
Pin No.

Signal Name

Symbol

I/O

Eel/TTL/Open
Drain/Power
ECl

36

Receive Bit Clock +

RXC+

I

37

Receive Bit Clock -

RXC-

I

38

ECl logic Power

Vee

39

Receive Data +

RXD+

I
I

ECl
+5V
ECl

40

Receive Data -

RXD-

41

ECl logic Ground

GND

42

Extemal loopback Data +

lBD+

0

ECl

43

Extemal loopback Data -

lBD-

0

ECl

44

ECl 1/0 Power

Vee

45

Transmit Data+

TXD+

0

46

Transmit Data+

TXD-

0

47

ECl logic Ground

GND

48

Transmit Bit Clock +

TXC+

I

49

Transmit Bit Clock -

TXC-

I

50

ECl logic Power

Vee

ECl
+OV

+5V
ECl
ECl
+OV
ECl
ECl
+5V

51

Transmit Byte Clock +

TBC+

I

ECl

52

Transmit Byte Clock -

TBC-

I

ECl

53

FOTX Enable level

TEL

I

TTL

54

No Connect

N/C

55

No Connect

N/C

56

FOTXEnable

TXE

0

TTL

57

local Byte Clock

lBC

I

TTL

58

PHY Port B Request Data < 0>

BRDO

I

TTL

59

PHY Port B Request Data < 1 >

BRD1

I

TTL

60

PHY Port B Request Data <2>

BRD2

I

TTL

61

PHY Port B Request Data < 3 >

BRD3

I

TTL

62

CMOS logic Ground

GND

63

PHY Port B Request Data <4>

BRD4

64

CMOS 110 Power

Vee

65

PHY Port B Request Data < 5>

BRD5

66

CMOS 110 Ground

GND

67

PHY Port B Request Data <6>

BRD6

I

TTL

68

PHY Port B Request Data < 7>

BRD7

I

TTL

69

PHY Port B Request Control

BRC

I

TTL

70

PHY Port B Request Parity

BRP

0

TTL

2·92

+OV

I

TTL
+5V

I

TTL
+OV

c

;g

6.0 Pin Descriptions (Continued)

Co)

N
CII

TABLE 6-1. DP83251 Pinout Summary (Continued)

Pin No.

Signal Name

Symbol

I/O

Eel/TTL/Open
Drain/Power

71

- PLAYER Device Reset

RSf

I

TTL

72

Read/- Write

R/W

I

TTL

73

Chip Enable

CE

I

TTL

74

-Interrupt

INT

0

Open Drain

75

- Acknowledge

ACK

0

Open Drain

76

Control Bus Address

CBAO

I

TTL

77

Control Bus Address < 1 >

CBA1

I

TTL

78

Control Bus Address < 2>

CBA2

I

TTL

79

Control Bus Address < 3 >

CBA3

I

TTL

I

80

Control Bus Address<4>

CBA4

81

CMOS Logic Power

Vee

82

Control Bus Data <0>

CBDO

I/O

83

Control Bus Data < 1 >

CBD1

I/O

84

CMOS Logic Ground

GND

.....
.....
C

"'U

co
~
CII
CII

TTL
+5V
TTL
TTL
+OV

fII

2·93

6.0 Pin Descriptions (Continued)
SERIAL INTERFACE
The Serial Interface consists of I/O signals used to connect the PLAYER device to the Physical Medium Dependent (PMD)
sublayer.
The PLAYER device uses these signals to interface to a Fiber Optic Transmitter (FOTX), Fiber Optic Receiver (FOXR), Clock
Recovery Device (CRD device), and Clock Distribution Device (CDD device).
Symbol

Pin No.

I/O

Description

CD

33

I

Clock Detect: A TIL input signal from the Clock Recovery Device indicating that the
Receive Clock (RXC ±) is properly synchronized with the Receive Data RXD ±).

TIlSD

34

I

Signal Detect: A TIL signal from the clock Recovery Device indicating that a signal is
being received by the Fiber Optic Receiver.

RXD+
RXD-

39
40

I

Receive Data: Differentiai lOOK ECl, 125 Mbps serial data input signals from the Clock
Recovery Device.

TXD+
TXD-

45
46

0

Transmit Data: Differential, lOOK ECl, 125 Mbps serial data output Signals to the Fiber
Optic Transmitter.

ElB

35

0

External Loopback Enable: A TIL output signal to the Clock Recovery Device which
enables/disables loopback data through the Clock Recovery Device. This signal is
controlled by the Mode Register.

lBD+
lBD-

42
43

0

Loopback Data: Differential, lOOK ECl, 125 Mbps, external serialloopback data output
. signals to the Clock Recovery Device.
When the PLAYER device is not in externalloopback mode, the lBD+ signal is kept
high and the lBD- signal is kept low.

TEL

53

I

FOTX Enable Level: A TIL input signal to select the Fiber Optic Transmitter Enable
(TXE) signal level.

TXE

56

0

FOTX Enable: A TIL output signal to enable/disable the Fiber Optic Transmitter. The
output level of the TXE pin is determined by three parameters, the Transmit Enable (TE)
bit in the Mode Register, the TM2-TMO bits in the Current Transmit State Register, and
also the input to the TEL pin.
The following rules summarizes the output of the TXE pin:
(1) liTE = and TEL = GND,thenTXE = Vee
(2) liTE = 0 and TEL = Vee, then TXE = GND
(3) liTE = 1 and OTM and TEL = GND, then TXE = Vee
(4) liTE = 1 and OTM and TEL = Vee, then TXE = GND
(5) liTE = 1 and not OTM and TEL = GND, then TXE = GND
(6) liTE = 1 and not OTM and TEL = Vee, then TXE = Vee

o

2-94

C

"tI

co

6.0 Pin Descriptions (Continued)

(0)

N
U1

PHY PORT INTERFACE

.....

The PHY Port Interface consists of I/O signals used to connect the PLAYER Device to the Media Access Control (MAC)
sublayer or other PLAYER Devices. The DP63251 Device has one PHY Port Interface which consists of the B_Request and the
A-Indicate paths.

......

Each path consists of an odd parity bit, a control bit, and two 4-bit symbols.

N
U1
U1

Refer to Section 3.3, the Configuration Switch, for further information.
Description

Pin No.

1/0

AlP

16

a

PHY Port A Indicate Parity: A TTL output signal representing odd parity for the 10-bit
wide Port A Indicate signals (AlP, AIC, and AID<7:0».

AIC

17

a

PHY Port A Indicate Control: A TTL output signal indicating that the two 4-bit symbols
(AID<7:4> and AID<3:0» are either control symbols (AIC = 1) or data symbols (Ale
= 0).

AID7
AID6
AIDS
AID4

16
19
21
23

a

PHY Port A Indicate Data: TTL output signals representing the first 4-bit data/control
symbol.

AID3
AID2
AIDI
AIDO

25
26
27
26

a

BRP

70

I

PHY Port B Request Parity: A TTL input signal representing odd parity for the 10-bit
wide Port A Request signals (BRP, BRC, and BRD<7:0».

BRC

69

I

PHY Port B Request Control: A TTL input signal indicating that the two 4-bit symbols
(BRD<7:4» and BRD<3:0» are either control symbols (BRC = 1) or data symbols
(BRC = 0).

BRD7
BRD6
BRD5
BRD4

66
67
65
63

I

PHY Port B Request Data: TTL input signals representing the first 4 bit data/control
symbol.

BRD3
BRD2
BRD1
BRDO

61
60
59
56

I

Symbol

AID7 is the most significant bit and AID4 is the least significant bit of the first symbol.
PHY Port A Indicate Data: TTL output signals representing the second 4-bit datal
control symbol.
AID3 is the most significant bit and AIDO is the least significant bit of the second symbol.

BRD7 is the most significant bit and BRD4 is the least significant bit of the first symbol.
PHY Port B Request Data: TTL input signals representing the second 4-bit datal control
symbol.
BRD3 is the most significant bit and BRDO is the least significant bit of the second
symbol.

2-95

C

"tI

co

(0)

6.0 Pin Descriptions (Continued)
CONTROL BUS INTERFACE
The Control Bus Interface consists of I/O signals used to connect the PLAYER device to Station Management (SMn.
The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor. It provides
access to 32 8-bit internal registers.
Refer to Figure 22, Control Bus Timing Diagram, for more information.
Symbol

Pin No.

I/O

Description

CE

73

I

Chip Enable: An active-low, TTL, input signal which enables the Control Bus port for a read
or write cycle. R/W, CBA<4:0>, CBP, and CBD<7:0> must be valid at the time -eE is low.

R/W

72

I

Read/-Write: A TTL input signal which indicates a read Control Bus cycle (R/W = 1), or
a write Control Bus cycle (R/W = 0). This signal must be valid when -eE is low and held
valid until ACK becomes low.

ACK

75

0

- Acknowledge: An active low, TTL, open drain output signal which indicates the
completion of a read or write cycle.
During a read cycle, CBD<7:0> are valid as long as ACK is low (ACK = 0).
During a write cycle, a microprocessor must hold CBD<7:0> valid until ACK becomes low.
Once ACK is low, it will remain low as long as CE remains low (CE = 0).

INT

74

0

-Interrupt: An active low, open drain, TTL, output signal indicating that an interrupt
condition has occurred. The Interrupt Condition Register (ICR) should be read in order to
find out the source of the interrupt. Interrupts can be masked through the use of the
Interrupt Condition Mask Register (ICMR).

CBA4
CBA3
CBA2
CBA1
CBAO

80
79
78
77
76

I

Control Bus Address: TTL input signals used to select the address of the register to be
read or written.
CBA4 is the most significant bit (MSB), CBAO is the least significant bit (LSB) of the address
signals.
These signals must be valid when
is low and held valid until ACK becomes low.

CBPE

13

I

CBP

9

I/O

Control Bus Parity: A bidirectional, TTL signal representing odd parity for the Control Bus
data (CBD < 7:0 > ).
During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.
During a write cycle, the signal must be valid when CE is low, and must be held valid until '
ACK becomes low. If incorrect parity is used during a write cycle, the PLAYER device will
inhibit the write cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt
Condition Register (lCR).

CBD7
CBD6
CBD5

8
7
5

I/O

CBD4
CBD3
CBD2
CBD1
CBDO

4
2
1
83
82

Control Bus Data: Bidirectional, TTL signals containing the data to be read from or written
to a register.
During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.
During a write cycle, the signal must be valid when CE is low, and must be held valid until
ACK becomes low.

a:

Control Bus Parity Enable: A TTL input signal which, during write cycles, will enable or
disable the Control Bus parity checker. Note that the Control Bus will always generate
parity during read cycles, regardless of the state of this signal.

2-96

6.0 Pin Descriptions (Continued)
CLOCK INTERFACE
The Clock Interface consists of 12.5 MHz and 125 MHz clocks used by the PLAYER device. The clocks are generated by either
the Clock Distribution Device or Clock Recovery Device.
Symbol

PlnNo.

1/0

LBC

57

I

Local Byte Clock: A TTL, 12.5 MHz, 50% duty cycle, input clock from the Clock
Distribution Device. The Local Byte Clock is used by the PLAYER device's internal
CMOS logic and to latch incoming/outgoing data of the Control Bus Interface, Port A
Interface, Port B Interface, and other miscellaneous lias.

Description

RXC+
RXC-

36
37

I

Receive Bit Clock: Differential 1OOk ECL, 125 MHz clock input signals from the Clock
Recovery Device. The Receive Bit Clock is used by the Serial Interface to latch the
Receive Data (RXD ±).

TXC+
TXC-

48
49

I

Transmit Bit Clock: Differential 1OOk ECL, 125 MHz clock input signals from the Clock
Distribution Device. The Transmit Bit Clock is used by the Serial Interface to latch the
Transmit Data (TXD ±).

TBC+
TBC-

51
52

I

Transmit Byte Clock: Differental1 OOk ECL, 12.5 MHz clock input signals from the Clock
Distribution Device. The Transmit Byte Clock is used by the PLAYER device's internal
Shift Register Block.

2·97

II)
II)

IN

Cf)

co

a.
Q

.....
....

II)

6.0 Pin Descriptions (Continued)
MISCELLANOUS INTERFACE
The Miscellaneous Interface' consists of a reset signal, user definable sense signals, user definable enable signals, Cascaded
PLAYER devices synchronization signals, ground signals, and power signals.

IN

Cf)

Pin No.

I/O

Description

RST

71

I

Reset: An active low, TTL, input signal which clears all registers. The signal
must be kept asserted for a minimum of 160 ns.
Once the RSi' signal is asserted, the PLAYER device should be allowed 960
ns to reset internal logic. Note that bit zero of the Mode Register will be set to
zero (i.e. Stop Mode). See Section 4.2, Stop Mode of Operation for more
information.

SPO

14

I

User Definable Sense Pin 0: A TTL input signal from a user defined source.
Bit zero (Sense Bit 0) of the User Definable Register (UDR) will be set to one
if the signal is asserted for a minimum of 160 ns.
Once the asserted signal is latched, Sense Bit 0 can only be cleared through
the Control Bus Interface, even if the signal is deasserted. This ensures that
, the Control Bus Interface will record the source of events which can cause
interrupts.

Symbol

co

a.
Q

,

SPI

15

I

User Definable Sense Pin 1: A TTL input signal from a user defined source.
Bit one (Sense Bit 1) of the User Definable Register (UDR) will be set to one if
the signal is asserted for a minimum of 160 ns.
Once the asserted signal is latched, Sense Bit 1 can only be cleared through
the Control Bus Interface, even if the signal is deasserted. This ensures that
the Control Bus Interface will record the source of events which can cause
interrupts.

EPO

10

0

User Definable Enable Pin 0: A TTL output signal allowing control of
external logic through the CBUS Interface. EPO is asserted/deasserted
through bit two (Enable Bit 0) of the User Definable Register (UDR). When
Enable Bit 0 is set to zero, EPO is deasserted. When Enable Bit 0 is set to
one, EPO is asserted.

EPI

11

0

User Definable Enable Pin 1: A TTL output signal allowing control of
external logic through the CBUS Interface. EPI is asserted/deasserted
through bit two (Enable Bit 1) of the User Definable Register (UDR). When
Enable Bit 1 is set to zero, EPI is deasserted. When Enable Bit 1 is set to
one, EPI is asserted.

CS

29

I

Cascade Start: A TTL input signal used to synchronize cascaded PLAYER
devices in pOint-to-point applications.
The signal is asserted when all of the cascaded PLAYER devices have the
Cascade Mode (CM) bit of Mode Register (MR) set to one, and all of the
Cascade Ready pins of the cascaded PLAYER devices have been released.
For further information, refer to Section 4.4, Cascade Mode of Operation.

CR

30

0

Cascade Ready: An Open Drain output signal used to synchronize cascaded
PLAYER devices in point-to-point applications.
The signal is released (i.e. an Open Drain line is released) when all the
cascaded PLAYER devices have the Cascade Mode (CM) bit of the Mode
Register (MR) set to one and a JK symbol pair has been received.
For further information, refer to Section 4.4, Cascade Mode of Operation.

2-98

C

"tI

6.0 Pin Descriptions (Continued)

CD

Co)

N

POWER AND GROUND
All power pins should be connected to a single 5V power supply. All ground pins should be connected to a common OV supply.

U1
.....
.....

Symbol

"tI

PinNo.

I/O

Description

C

CD

Co)

GND

3

Ground: Power supply return for Control Bus Interface CMOS I/Os.

Vee

6

Power: Positive 5V power supply (±5% relative to ground) for Control Bus Interface
CMOSI/Os.

GND

12

Ground: Power supply return for internal CMOS logic.

GND

20

Ground: Power supply return for Port A Interface CMOS I/0s.

Vee

22

Power: Positive 5V power supply (± 5% relative to ground) for the Port A Interface
CMOS I/Os.

GND

24

Ground: Power supply return to internal CMOS logic.

Vee

38

Power: Positive 5V power supply (± 5% relative to ground) for internal ECl logic.

GND

41

Ground: Power supply return for internal ECl logic.

Vee

44

Power: Positive 5V power supply (± 5% relative to ground) for the Serial Interface ECl II
Os.

GND

47

Ground: Power supply return for internal ECl logic.

Vee

50

Power: Positive 5V power supply (± 5% relative to ground) for the Serial Interface ECl II
Os.

GND

62

Ground: Power supply return for internal CMOS logic.

Vee

64

Power: Positive 5V power supply (± 5% relative to ground) for the Port A Interface
CMOS I/Os.
Ground: Power supply return for Port A Interface CMOS I/0s.

GND

66

Vee

81

Power: Positive 5V power supply (± 5% relative to ground) for internal CMOS logic.

GND

84

Ground: Power supply return for internal CMOS logic.

NO CONNECT PINS
Symbol

N/C
N/C
N/C
N/C

Pin No.

Description

I/O

31

No Connect: Not used by the PLAYER device

32

No Connect: Not used by the PLAYER device

54

No Connect: Not used by the PLAYER device

55

No Connect: Not used by the PLAYER device

2-99

N

U1
U1

U)
U)

C'I

CO)

r---------------------------------------------------------------------------------,
6.0 Pin Descriptions (Continued)

~

6.2 DP83255

.-

The pin descriptions for the DP83255 are divided into six functional interfaces; Serial Interface, PHY Port Interface, Control Bus
Interface, Clock Interface, and Miscellaneous Interface.

c......
~
CO)

~

For a Pinout Summary List; refer to Table 6-2.

c

o

DP83255

PLAYER
132-PIN PQFP

TLlF/l0386-21

Order Number DP83255AVF
See NS Package Number VF132A
FIGURE 6-2. DP83255 132-Pln PQFP Pinout

2-100

c

;g

6.0 Pin Descriptions (Continued)

Co)

N
UI

TABLE 6-2. DP83255 Pinout Summary

Pin No.

Signal Name

Symbol

1

CMOS Logic Ground

GND

1/0

Eel/TTl/Open
DralnlPower
+OV

2

Control Bus Data<2>

CBD2

1/0

3

Control Bus Data<3>

CBD3

1/0

4

CMOS 1/0 Ground

GND

5

Control Bus Data<4>

CBD4

1/0

TTL

6

Control Bus Data < 5 >

CBD5

1/0

TTL

7

CMOS 1/0 Power

Vee

8

Control Bus Data<6>

CBD6

1/0

TTL

9

Control Bus Data<7>

CBD7

1/0

TTL

10

Control Bus Data Parity

CBP

1/0

TTL

TTL

+5V

Enable Pin 0

EPO

0

TTL

Enable Pin 1

EP1

0

TTL

13

No Connect

14

No Connect

15

No Connect

16

No Connect

N/C
N/C
N/C
N/C
N/C
N/C
N/C

No Connect
No Connect

19

No Connect

20

CMOS Logic Ground

GND

21

Control Bus Data Parity Enable

CBPE

I

TTL

22

Sense Pin 0

SPO

I

TTL

23

Sense Pin 1

SP1

I

TTL

24

PHY Port A Indicate Parity

AlP

0

TTL

25

PHY Port A Request Parity

ARP

I

TTL

26

PHY Port A Indicate Control

AIC

0

TTL

27

PHY Port A Request Control

ARC

I

TTL

28

PHY Port A Indicate Data <7>

AID7

0

TTL

+OV

29

PHY PortA Request Data<7>

ARD7

I

TTL

30

PHY PortA Indicate Data<6>

AID6

0

TTL

31

PHY Port A Request Data <6>

ARD6

I

32

CMOS 1/0 Ground

GND

33

PHY A Indicate Data<5>

AID5

0

34

PHY A Request Data<5>

ARD5

I

35

CMOS 1/0 Power

Vee

2-101

~

UI
UI

TTL

11

18

C

;g

+OV

12

17

....
.....

TTL
+OV
TTL
TTL
+5V

fII

6.0 Pin Descriptions (Continued)
TABLE 6-2. DP83255 Pinout Summary (Continued)
Pin No.

Signal Name

Symbol

I/O

Eel/TTL/Open
Drain/Power
TTL

PHY A Indicate Data<4>

AID4

0

37

PHY A Request Data<4>

ARD4

I

38

CMOS logic Ground

GND

39

PHY Port A Indicate Data < 3 >

AID3

0

TTL

40

PHY Port A Request Data < 3 >

ARD3

I

TTL

41

PHY Port A Indicate Data <2>

AID2

0

TTL

42

PHY Port A Request Data <2>

ARD2

I

TTL

43

PHY Port A Indicate Data < 1 >

AID1

0

TTL

44

PHY Port A Request Data < 1 >

ARD1

I

TTL

45

PHY Port A Indicate Data < 0 >

AIDO

0

TTL

46

Port A Request Data < 0 >

ARDO

I

TTL

47

Cascade Start

CS

I

TTL

48

Cascade Ready

CR

0

Open Drain

36

TTL
+OV

56

No Connect

N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C

57

Clock Detect

CD

I

TTL

58

Signal Detect

TTlSD

I

TTL

59

External loopback Enable

ElB

0

TTL

60

Receive Bit Clock +

RXC+

I

ECl

61

Receive Bit Clock -

RXC-

I

62

ECl logic Power

Vee

63

Receive Data +

RXD+

I

64

Receive Data -

RXD-

I

65

ECl logic Ground

GND

49

No Connect

50

No Connect

51

No Connect

52

No Connect

53

No Connect

54

No Connect

55

No Connect

ECl
+5V
ECl
ECl
+OV

66

External loopback Data +

lBD+

0

67

External loopback Data -

lBD-

0

68

ECl I/O Power

Vee

69

Transmit Data +

TXD+

0

ECl

70

Transmit Data -

TXD-

0

ECl

2-102

ECl
ECl
+5V

Ie
"'U

6.0 Pin Descriptions (Continued)

Q)
Co)

N

TABLE 6-2. DP83255 Pinout Summary (Continued)

Pin No.

Signal Name

Symbol

110

71

ECl logic Ground

GND

72

Transmit Bit Clock +

TXC+

I

ECl

73

Transmit Bit Clock -

TXC-

I

ECl

+OV

74

ECl logic Power

Vee

75

Transmit Byte Clock +

TBC+

I

ECl

76

Transmit Byte Clock -

TBC-

I

ECl

77

FOTX Enable level

TEL

I

TTL

78

No Connect

N/C

79

No Connect

80

No Connect

85

No Connect

86

FOTXEnable

TXE

0

TTL

87

local Byte Clock

LBC

I

TTL

88

PHY Port B Indicate Data <0>

BIDO

0

TTL

89

PHY Port B Request Data <0>

BRDO

I

TTL

90

PHY Port B Indicate Data < 1 >

BID1

0

TTL

81

No Connect
No Connect

83

No Connect

84

No Connect

91

PHY Port B Request Data < 1 >

BRD1

I

TTL

92

PHY Port B Indicate Data<2>

BID2

0

TTL

93

PHY Port B Request Data < 2 >

BRD2

I

TTL

94

PHY Port B Indicate Data<3>

BID3

0

TTL

95

PHY Port B Request Data <3>

BRD3

I

TTL

96

CMOS Logic Ground

GND

97

PHY Port B Indicate Data <4>

BID4

0

98

PHY Port B Request Data <4>

BRD4

I

99

CMOS I/O Power

Vee

100

PHY Port B Indicate Data

BIDS

0

"'U
Q)
Co)

N

en
en

I

+OV
TTL
TTL
+SV
TTL

101

PHY Port B Request Data 

BROS

102

CMOS I/O Ground

GND

103

PHY Port B Indicate Data < 6 >

BID6

0

TTL

104

PHY Port B Request Data <6>

BRD6

I

TTL

10S

PHY Port B Indicate Data<7>

BID7

0

TTL

2-103

Ie

+5V

N/C
N/C
N/C
N/C
N/C
N/C
N/C

82

....
.....
en

Eel/TTL/Open
Drain/Power

TTL
+OV

•

6.0 Pin Descriptions (Continued)
TABLE 6·2. DP83255 Pinout Summary (Continued)
Eel/TTL/Open
Drain/Power

Pin No.

Signal Name

106

PHY Port B Request Data<7>

BRD7

I

TTL

107

PHY Port B Indicate Control

BIC

a

TTL

108

PHY Port B Request Control

BRC

I

TTL

109

PHY Port B Indicate Parity

BIP

a

TTL

110

PHY Port B Request Parity

BRP

I

TTL

111

- PLAYER Device Reset

RSf

I

TTL

112

Read/-Write

R/W

I

TTL

113

Chip Enable

~

I

TTL

114

-Interrupt

a

Open Drain

115

No Connect

116

No Connect

117

No Connect

118

No Connect

119

No Connect

120

No Connect

Symbol

I/O

121

No Connect

122

No Connect

iN'f
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C

123

- Acknowledge

~

a

Open Drain

124

Control Bus Address <0>

CBAO

I

TTL

125

Control Bus Address < 1>

CBA1

I

TTL

126

Control Bus Address <2>

CBA2

I

TTL

127

Control Bus Address <3 >

CBA3

I

TTL

128

Control Bus Address < 4>

CBA4

I

129

CMOS Logic Power

Vee

130

Control Bus Data <0 >

CBDO

110

TTL

131

Control Bus Data < 1 >

CBD1

110

TTL

132

CMOS Logic Ground

GND

2-104

TTL
+5V

+OV

C

-a

6.0 Pin Descriptions (Continued)

C»

w

SERIAL INTERFACE

N
U1

The Serial Interface consists of I/O signals used to connect the PLAYER device to the Physical Medium Dependent (PM D)
sublayer.

C

The PLAYER device uses these signals to interface to a Fiber Optic Transmitter (FOTX), Fiber Optic Receiver (FORX), Clock
Recovery Device (CRD device), and Clock Distribution Device (CDD device).
PlnNo.

1/0

CD

57

I

Clock Detect: A TTL input signal from the Clock Recovery Device indicating that the
Receive Clock (RXC ±) is properly synchronized with the Receive Data (RXD ±).

TTlSD

58

I

Signal Detect: A TTL input signal from the Clock Recovery Device indicating that a
signal is being received by the Fiber Optic Receiver.

RXD+
RXD-

63
64

I

Receive Data: Differential lOOK ECl, 125 Mbps serial data input signals from the Clock
Recovery Device.

TXD+
TXD-

69
70

0

Transmit Data: Differential, lOOK ECl, 125 Mbps serial data output signals to the Fiber
Optic Transmitter.

ElB

59

0

External Loopback Enable: A TTL output signal to the Clock Recovery Device which
enables/disables loopback data through the Clock Recovery Device. This signal is
controlled by the Mode Register.

lBD+
lBD-

66
67

0

Loopback Data: Differential, lOOK ECl, 125 Mbps, serial externalloopback data output
signals to the Clock Recovery Device.

Symbol

......
.......
-a
C»

w

N
U1
U1

Description

When the PLAYER device is not in externalloopback mode, the lBD+ signal is kept
high and the lBD- signal is kept low.
TEL

77

I

TXE

86

0

FOTX Enable Level: A TTL input signal to select the Fiber Optic Transmitter Enable
(TXE) signal level.
FOTX Enable: A TTL output signal to enable/disable the Fiber Optic Transmitter. The
output level of the TXE pin is determined by three parameters, the Transmit Enable (TE)
bit in the Mode Register, the TM2-TMO bits in the Current Transmit State Register, and
also the input to the TEL pin.
The following rules summarizes the output of the TXE pin:
(1) If TE = 0 and TEL = GND, then TXE = Vee
(2) If TE = 0 and TEL = Vee, then TXE = GND
(3) If TE = 1 and OTM and TEL = GND, then TXE = Vee
(4) If TE = 1 and OTM and TEL = Vee, then TXE = GND
(5) If TE = 1 and not OTM and TEL = GND, then TXE = GND
(6) If TE = 1 and not OTM and TEL = Vee, then TXE = Vee

•
2-105

6.0 Pin Descriptions (Continued)
PHY PORT INTERFACE
The PHY Port Interface consists of I/O signals used to connect the PLAYER Device to the Media Access'Control (MAC)
sublayer or other PLAYER Devices. The DP83255 Device has two PHY Port Interfaces. The LRequest and Llndicate paths
form one PHY Port Interface and the B_Request and B_lndicate paths form the second PHY Port Interface. Each path
consists of an odd parity bit, a control bit, and two 4-bit symbols.
Refer to Section 3.3, the Configuration Switch, for more information.
Symbol

Description

IIlnNo.

1/0

AlP

24

0

PHY Port A Indicate Parity: A TTL output signal representing odd parity for the 10-bit
wide Port A Indicate signals (AlP, AIC, and AID <7:0».

AIC

26

0

PHY Port A Indicate Control: A TTL output signal indicating that the two 4-bit symbols
(AID<7:4> and AID<3:0» are either control symbols (AIC = 1) or data symbols (AIC
= 0).

AID7
AID6
AID5
AID4

28
30
33
36

0

PHY Port A Indicate Data: TTL output signals representing the first 4-bit data/control
symbol.
AID7 is the most significant bit and AID4 is the least significant bit of the first symbol.

AID3
AID2
AIDI
AIDO

39
41
43
45

0

PHY Port A Indicate Data: TTL output signals representing the second 4-bit datal
control symbol.
AID3 is the most significant bit and AIDO is the least significant bit of the second symbol.

ARP

25

I

PHY Port A Request Parity: A TTL input signal representing odd parity for the 10-bit
wide PortA Request signals (ARP, ARC, and ARD<7:0».

ARC

27

I

PHY Port A Request Control: A TTL input signal indicating that the two 4-bit symbols
(ARD<7:4> and ARD<3:0» are either control symbols (ARC = 1) or data symbols
(ARC = 0).

ARD7
ARD6
ARD5
ARD4

29
31
34
37

I

PHY Port A Request Data: TTL input signals representing the first 4 bit datal control
symbol.
ARD7 isthe most significant bit and ARD4 is the least significant bit of the first symbol.

ARD3
ARD2
ARDI
ARDO

40
42
44
46

I

PHY Port A Request Data: TTL input signals representing the second 4-bit datal control
symbol.
ARD3 is the most significant bit and ARDO is the least significant bit of the second
symbol.

2-106

C

6.0 Pin Descriptions

"tI

co

(Continued)

Co)
I\)

U'I
.....
.....

PHY PORT INTERFACE (Continued)
Symbol
BIP

PlnNo.

1/0

109

0

Description
PHY Port B Indicate Parity: A TTL output signal representing odd parity for the 10-bit
wide Port B Indicate signals (BIP, BIC, and BID<7:0».

BIC

107

0

PHY Port B Indicate Control: A TTL output signal indicating that the two 4-bit symbols
(BID<7:4> and BID<3:0» are either control symbols (BIC = 1) or data symbols (BIC
= 0).

BID7
BID6
BIDS
BID4

105
103
100
97

0

PHY Port B Indicate Data: TTL output signals representing the first 4-bit datal control
symbol.

BID3
BID2
BIDl
BIDO

94
92
90
88

0

BRP

110

I

PHY Port B Request Parity: A TTL input signal representing odd parity for the 10-bit
wide Port B Request signals (BRP, BRC, and BRD<7:0».

BRC

108

I

PHY Port B Request Control: A TTL input signal indicating that the two 4-bit symbols
(BRD<7:4» and BRD<3:0» are either control symbols (BRC = 1) or data symbols
(BRC = 0).

BRD7
BRD6
BROS
BRD4

106
104
101
98

I

PHY Port B Request Data: TTL input signals representing the first 4-bit datal control
symbol.

BRD3
BRD2
BRDl
BRDO

95
93
91
89

I

C

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co
Co)

I\)

U'I
U'I

BID7 is the most significant bit and BID4 is the least significant bit of the first symbol.
PHY Port B Indicate Data: TTL output signals representing the second 4-bit datal
control symbol.
BID3 is the most significant bit and BIDO is the least significant bit of the second symbol.

BRD7 is the most significant bit and BRD4 is the least significant bit of the first symbol.
PHY Port B Request Data: TTL input signals representing the second 4-bit datal control
symbol.
BRD3 is the most significant bit and BRDO is the least significant bit of the second
symbol.

•
2-107

II)
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co

a.

6.0 Pin Descriptions (Continued)
CONTROL BUS INTERFACE
The Control Bus Interface consists of 1/0 signals used to connect the PLAYER device to Station Management (SMn.
The Control Bus is an asynchronous interface between the PLAYER device and a general purpose microprocessor. It provides
access to 32 8-bit internal registers.
Refer to Figure 22, Control Bus Timing Diagram, for further information.

C

PlnNo.

1/0

Description

CE

113

I

Chip Enable: An active-low, TTL, input signal which enables the Control Bus port for a
read or write cycle. R/W, CBA <4:0>, CBP, and CBD<7:0> must be valid atthe time CE
is low.

R/W

112

I

Readl - Write: A TTL input signal which indicates a read Control Bus cycle (R/W = 1),
or a write Control Bus cycle (R/W = 0). This signal must be valid when CE: is iow and
held valid until ACK becomes low.

ACK

123

0

- Acknowledge: An active low, TTL, open drain output signal which indicates the
completion of a read or write cycle.
During a read cycle, CBD<7:0> are valid as long asACKis low (ACK = 0).
During a write cycle, a microprocessor must hold CBD<7:0> valid until ACK becomes
low.
Once ACK is low, it will remain low as long as CE remains low (CE = 0).

INT

114

0

-Interrupt: An active low, open drain, TTL, output signal indicating that an interrupt
condition has occurred. The Interrupt Condition Register (lCR) should be read in order to
determine the source of the interrupt. Interrupts can be masked through the use of the
Interrupt Condition Mask Register (ICMR)

CBA4
CBA3
CBA2
CBA1
CBAO

128
127
126
125
124

I

Control Bus Address: TTL input signals used to select the address of the register to be
read or written.
CBA4 is the most significant bit and CBAO is the least significant bit of the address
signals.
These signals must be valid when CE is low and held valid until ACK becomes low.

CBPE

21

I

Control B,us Parity Enable: A TTL input signal which, during write cycles, will enable or
disable the Control Bus parity checker. Note that the Control Bus will always generate
parity during read cycles, regardless of the state of this signal:

CBP

10

1/0

Control Bus Parity: A bidirectional, TTL signal representing odd parity for the Control
Bus data (CBD<7:0».
During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.
During a write cycle, the signal must be valid when CE is low, and must be held valid until
ACK becomes low. If incorrect parity is used during a write cycle, the PLAYER device will
inhibit the write cycle and set the Control Bus Data Parity Error (CPE) bit in the Interrupt
Condition Register (ICR).

CBD7
CBD6
CBD5
CBD4
CBD3
CBD2
CBD1
CBDO

9
8
6
5
3
2
131
130

1/0

Control Bus Data: Bidirectional, TTL signals containing the data to be read from or
written to a register.
During a read cycle, the signal is held valid by the PLAYER device as long as ACK is low.
During a write cycle, the signal must be valid when CE is low, and must be held valid until
ACK becomes low.

Symbol

2-108

6.0 Pin Descriptions (Continued)
CLOCK INTERFACE
The Clock Interface consists of 12.5 MHz and 125 MHz clocks used by the PLAYER device. The clocks are generated by either
the Clock Distribution Device or Clock Recovery Device.

PlnNo.

1/0

lBC

Symbol

87

I

Local Byte Clock: A TTL, 12.5 MHz, 50% duty cycle, input clock from the Clock
Distribution Device. The local Byte Clock is used by the PLAYER device's internal
CMOS logic and to latch incoming/outgoing data of the Control Bus Interface, Port A
Interface, Port B Interface, and other miscellaneous I/Os.

Description

RXC+
RXC-

60
61

I

Receive Bit Clock: Differential, lOOk ECl, 125 MHz clock input signals from the Clock
Recovery Device. The Receive Bit Clock is used by the Serial Interface to latch the
Receive Data (RXD ±).

TXC+
TXC-

72
73

I

Transmit Bit Clock: Differential, lOOk ECl, 125 MHz clock input signals from the Clock
. Distribution Device. The Transmit Bit Clock is used by the Serial Interface to latch the
Transmit Data (TXD ±).

TBC+
TBC-

75
76

I

Transmit Byte Clock: Differental, lOOk ECl, 12.5 MHz clock input signals from the
Clock Distribution Device. The Transmit Byte Clock is used by the PLAYER device's
internal Shift Register Block.

2·109

6.0 Pin Descriptions (Continued)
MISCELLANEOUS INTERFACE
The Miscellaneous Interface consists of a reset signal, user definable sense signals, user definable enable signals, Cascaded
PLAYER device's synchronization signals, ground signals, and power signals.
Pin No.

I/O

Description

RSi

111

I

' Reset: An active low, TIL, input signal which clears all registers. The signal must be kept
asserted for a minimum of 160 ns.
Orice the RST signal is asserted, the PLAYER device should be allowed 960 ns to reset
internal logic. Note that bit zero of the Mode Register will be set to zero (i.e. Stop Mode).
See Seqtion 4.2, Stop Mode of Operatjon for more information.

SPO

22-

I

User Definable Sense Pin 0: A TIL input signal from a user defined source. Bit zero
(Sense Bit 0) of the User Definable Registe(UDR) will be set to one if the signal is
asserted for a minimum of 160 ns.
Once the asserted signal is latched, Sense Bit 0 can only be cleared through the Control,
Bus Interface, even if the signal is deasserted. This ensures that the Control Bus
Interface will record the source of events which can cause interrupts.

SP1

23

I

User Definable Sense Pin 1: A TIL input signal from a user defined source. Bit one
(Sense Bit 1) of the User Definable Register (UDR) will be set to one if the signal is
asserted for a minimum of 160 ns.
Once the asserted signal is latched, Sense Bit 0 can only be cleared through the Control
Bus Interface, even if the signal is deasserted. This ensures that the Control Bus
Interface will record the source of events which can cause interrupts.

EPO

11

0

User Definable Enable Pin 0: A TIL output signal allowing control of external logic
through the Control Bus Interface. EPO is asserted/deasserted through bit two (Enable
Bit 0) of the User Definable Register (UDR). When Enable Bit 0 is set to zero, EPO is
deasserted. When Enable Bit 0 is set to one, EPO is asserted.

EP1

12

0

User Definable Enable Pin 1: A TIL output signal allowing control of external logic
through the Control Bus Interface. EP1 is asserted/deasserted through bit two (Enable
Bit 1) of the User Definable Register (UDR). When Enable Bit 1 is set to zero, EP1 is
deasserted. When Enable Bit 1 is set to one, EP1 is asserted.

CS

47

I

Cascade Start: A TIL input signal used to synchronize cascaded PLAYER devices in
pOint-to-point applications.
The signal is asserted when all of the cascaded PLAYER devices have the Cascade
Mode (CM) bit of the Mode Register (MR) set to one, and all of the Cascade Ready (CR)
pins ofthe cascaded PLAYER devices have been released.
For further information, refer to Section 4.4, Cascade Mode of Operation.

CR

48

0

Cascade Ready: An Open Drain output signal used to synchronize cascaded PLAYER
devices in point-to-point applications.
The signal is released when all the cascaded PLAYER devices have the Cascade Mode
(CM) bit of the Mode Register (MR) set to one and a JK symbol pair has been received.
For further Information, refer to section 4.4, Cascade Mode of Operation.

, Symbol

2-110

6.0 Pin Descriptions (Continued)
POWER AND GROUND
All power pins should be connected to a single 5V power supply. All ground pins should be connected to a common OV ground
supply.
Symbol

Pin No.

Description

I/O

GND

1

Ground: Power supply return for internal CMOS logic.

GND

4

Ground: Power supply return for Control Bus Interface CMOS I/0s.

Vee

7

Power: Positive 5V power supply (± 5% relative to ground) for Control Bus Interface
CMOSI/Os.

GND
GND

20

Ground: Power supply return for internal CMOS logic.

32

Ground: Power supply return for Port A Interface CMOS I/0s.

Vee

35

Power: Positive 5V power supply (± 5% relative to ground) for the Port A Interface
CMOSI/Os.

GND

38

Ground: Power supply return for internal CMOS logic.

Vee

62

Power: Positive 5V ppwer supply (± 5% relative to ground) for internal ECL logic.

GND

65

Ground: Power supply return for internal ECL logic.

Vee

68

Power: Positive 5V power supply (±5% relative to ground) for the Serial Interface ECL II
Os.
Ground: Power supply return for internal ECL logic.

GND

71

Vee

74

Power: Positive 5V power supply (± 5% relative to ground) for internal ECL logic.

GND

96

Ground: Power supply return for internal CMOS logic.

Vee

99

Power: Positive 5V power supply (± 5% relative to ground) for Port B Interface CMOS II
Os.

GND

102

Ground: Power supply return for Port B Interface CMOS 1/05.

Vee

129

Power: 5V power supply (± 5% relative to ground) for internal CMOS logic.

GND

132

Ground: Power supply return for internal CMOS logic.

2-111

Lt)

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f
c

6.0 Pin Descriptions (Continued)
NO CONNECT PINS
Description

Symbol

Pin No•

N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C

I/O

13

No Connect: Not used by the PLAYEA device

14

No Connect: Not used by the PLAYEA device

15

No Connect: Not used by the PLAYEA device

16

No Connect: Not used by the PLAYEA device

17

No Connect: Not used by the PLAYEA device

18

No Connect: Not used by the PLAYEA device

19

No Connect: Not used by the PLAYEA device

49

No Connect: Not used by the PLAYEA device

50

No Connect: Not used by the PLAYEA device

51

No Connect: Not used by the PLAYEA device

52

No Connect: Not used by the PLAYEA device

53

No Connect: Not used by the PLAYEA device

54

No Connect: Not used by the PLAYEA device

55

No Connect: Not used by the PLAYEA device

56

No Connect: Not used by the PLAYEA device

78

No Connect: Not used by the PLAYEA device

79

No Connect: Not used by the PLAYEA device

80

No Connect: Not used by the PLAYEA device

81

No Connect: Not used by the PLAYEA device

82

No Connect: Not used by the PLAYEA device

83

No Connect: Not used by the PLAYEA device

84

No Connect: Not used by the PLAYEA device

85

No Connect: Not used by the PLAYEA device

115

No Connect: Not used by the PLAYEA device

116

No Connect: Not used by the PLAYEA device

117

No Connect: Not used by the PLAYEA device

118

No Connect: Not used by the PLAYEA device

119

No Connect: Not used by the PLAYEA device

120

No Connect: Not used by the PLAYEA device

121

No Connect: Not used by the PLAYEA device

122

No Connect: Not used by the PLAYER device

2-112

C

"'D

7.0 Electrical Characteristics

CD

Co)

N
UI

7.1 ABSOLUTE MAXIMUM RATINGS
Symbol
Vee

Parameter

Conditions

Supply Voltage

Min

Typ

-0.5

Max

Units

7.0

V

DCIN

Input Voltage

-0.5

Vee + 0.5

DCOUT

Output Voltage

-0.5

Vee + 0.5

V

Storage Temperature

-65

150

·C

V

....
.....
C

"'D
CD

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N
UI
UI

7.2 RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Vee

Supply Voltage

TA

Operating Temperature

Conditions

Min

Typ

Max

Units

4.75

5.25

V

0

70

·C

7.3 DC ELECTRICAL CHARACTERISTICS
The DC characteristics are over the operating range. unless otherwise specified.
DC electrical characteristics for the TIL. TRI-STATE output signals of PHY. Port Interfaces. and CBUS Interface.
Symbol

Parameter

Conditions

IOZ1

TRI-STATE Leakage
(CBP & CBD7 -0)

VOUT = Vee

IOZ2

TRI-STATE Leakage
(CBP & CBD7 -0)

VOUT = VGND

IOZ3

TRI-STATE Leakage
(AID & BID)

VOUT = Vee
(Note 1)

IOZ4

TRI-STATE Leakage
(AID&BID)

VOUT = GND

Min

Typ

Max

Units

10

/LA

-10

/LA

60

/LA

-500

/LA

Note 1: Output buffer has a p-channel pullup device.

DC electrical characteristics for all TIL input signals and the following TIL output signals: External Loopback (ELB). Fiber Optic
Transmitter Enable (TXE). Enable Pin 0 (EPO). and Enable Pin 1 (EP1).
Symbol

Parameter

Conditions

VOH

Output High Voltage

10H = -2mA

VOL

Output Low Voltage

10L = 4mA

VIH

Input High Voltage

VIL

Input Low Voltage

Vie

Input Clamp Voltage

liN = -18 mA

IlL

Input Low Current

IIH

Input High Current

Min

Typ

Max

Units

0.5

V

V

Vee - 0.5

2.0

V
0.8

V

-1.5

V

VIN = GND

-10

/LA

VIN = Vee

+10

/LA

fII

2-113

II)
II)

N

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......
....

II)

N

C")

CD

a.
C

7.0 Electrical Characteristics (Continued)
DC electrical characteristics for all Open Drain output signals (INT, ACK and CR).
Symbol

Parameter

Conditions

Min

Typ

Max

Units

VOL

Output Low Voltage

IOL = SmA

0.5

V

loz

TRI-STATE Leakage

VOUT = Vee

10

,.A

DC electrical characteristics for all 100k ECL input and output signals.
Symbol

Parameter

Conditions

Min

VOH

Output High Voltage

VIN = VIH (max)

VOL

Output Low Voltage

VIN = VIL(min)

VIH
VIL

Typ

Max

Units

Vee - 1.025

Vee - 0.S80

V

Vee - 1.810

Vee - 1.620

V

Input High Voltage

Vee -1.165

Vee - 0.S80

V

Input Low Voltage

Vee - 1.S10

Vee - 1.475

V
,.A
,.A

IL

Input Low Current

VIN = GND

-10

IH

Input High Current

VIN = Vee

100

Supply Current electrical characteristics
Symbol

Parameter

Conditions

Min

Typ

Max

Units

Total Supply
LBC = 12.5 MHz
Icc
mA
440'
TXC = 125 MHz
Current
'Note: The PLAYER device has two pairs of differential ECL outputs, therefore 60 mA of the total supply current is actually consumed by external termination
resistors and the maximum current consumed by the PLAYER device alone is only 3BO mAo The EeL termination current is calculated as follows:
VOILmax = Vee - 0.88V
VOLmax = Vee - 1.S2V
Since the outputs are differential, the average output level is Vee - 1.25V. The test load per output is son at Vee - 2V, therefore the extemalload current
through the son resistor is:
'LOAD = [(Vee - 1.25) - (Vee - 2)]/50
= 0.015A
=15mA.
As result, two pairs of EeL outputs consume so mAo

2-114

7.0 Electrical Characteristics (Continued)
7.4 AC ELECTRICAL CHARACTERISTICS
The AC Electrical characteristics are over the operating range, unless otherwise specified.
AC Characteristics for the Control Bus Interface
Symbol

Parameter

Min

Max

Units

T1

CE Setup to LBC

5

ns

T2

LBCPeriod

80

ns

T3

LBC to ACK Low

T4

CE Low to ACK Low

T5

LBC Low to CBO(7-0) and CBP Valid

290

45

ns

540

ns

60

ns

60

ns

T6

LBC to CBO(7-0) and CBP Active

T7

CE Low to CBO(7 -0) and CBP Active

225

475

ns

T8

CE Low to CBO(7 -0) and CBP Valid

265

515

ns

T9

LBC Pulse Width High

35

45

ns

T10

LBC Pulse Width Low

35

45

ns

T11

CE High to ACK High

45

ns

T12

R/W, CBA(7-0), CBO(7-0) and
CBP Set up to CE Low

T13

CE High to R/W, CBA(7-0),
CBO(7-0) and CBP Hold Time

5

ns

0

ns

T14a

R/W to LBC Setup Time

0

ns

T14b

CBA to LBC Setup Time

10

ns

T14c

CBO and CBP to LBC Setup Time

0

ns

T15

ACK Low to CE High Lead Time

0

ns

T16

CE Minimum Pulse Width High

20

T17

CE High to CBO(7-0) and CBP TRI-STATE

T18

ACK High to CE Low

T19

CBO(7-0) Valid to ACK Low Setup

20

ns

T20a

LBC to R/W Hold Time

10

ns

T20b

LBC to CBA Hold Time

10

ns

T20c

LBC to CBO and CBP Hold Time

20

ns

ns
55

0

ns
ns

T21

LBC to INT Low

55

ns

T22

LBC to TNT High

60

ns

Asynchronous Definitions
T4(min)

T1 +(3*T2)+T3

T4 (max)

T1 + (4 * T2) + T3

T7(min)

T1 + (2 • T2) + T6

T7(max)

T1 + (3 • T2) + T6

T8(min)

T1 + (2' T2) + T9 + T5

T8 (max)

T1 + (3 • T2) + T9 + T5

Note: MinIMax numbers are based on T2

~

80 ns and T9

~

fJI
T10

~

40ns.

2-115

~

~
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co

.--------------------------------------------------------------------,
7.0 Electrical Characteristics (Continued)

Q.

Q
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~

~

116

R/W

Q

~
CBA

XXX

ADDRESS VAUD IN

caD &

2QQ{

DATA YALID IN

CBP

[XXX

~X

:X :X

.~7 ~ ~
T~

\

~
TL/F/1038B-23

TL/F/1D3BB-22

FIGURE 7·1. Control Bus Write Cycle Timing

FIGURE 7-2. Control Bus Read Cycle Timing

TLlF/103BB-35

FIGURE 7-3. Control Bus Synchronous Write Cycle Timing

LBC

R/fl

COBCBP
It

---------..::::..~~~~~~iP

m ------------+--""'\
TLlF/103B6-24

FIGURE 7-4. Control Bus Synchronous Read Cycle Timing

'TL/F/103BB-44

FIGURE 7-5. Control Bus Interrupt Timing

2·116

C

"tI

7.0 Electrical Characteristics (Continued)

ext

Co)

N

AC Characteristics for the Clock Signals
Symbol

Parameter

T23

TBC to TXC Hold Time

T24

TBC to TXC Setup Time

T25

TBC to LBC Skew

Conditions

Min

(Note 1)
(Note 1)

Typ

Max

2

ns

2.5
10

Units

ns
22

ns

T26

RXC Duty Cycle

(Note 1)

3.0

5.0

ns

T27

TXC Duty Cycle

(Note 1)

3.5

4.5

ns

T2B

TBC Duty Cycle

37

43

ns

T29

LBC Duty Cycle

35

45

ns

C1I
....
....
C

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ext

Co)

N

C1I
C1I

Note 1: RXC duty cycle, TXC duty cycle, and TBC to TXC setup time are not tested, but are assured by correlation with characterization data.
Note 2: When PLAYER is used in FOOl applications, TBC and LBC periods will be 80 ns and RXC and TXC periods will be 8 ns.

RXC

TXC

TSC

LOC

i---T29---i
TL/F/l0386-36

FIGURE 7-6. Clock Signals

fII

2-117

II)
II)

N

C')

co
a..

C
.....
.,...

II)

N

C')

7.0 Electrical Characteristics (Continued)
AC Characteristics for PHY Port Interfaces
Symbol

Conditions

Min

Typ

Max

Units

T30

LBC to Indicate Data Changes
from TRI-STATE to Data Valid

70

ns

T31

LBC to Indicate Data Changes
from Active to TRI-STATE

70

ns

T32

LBC to Indicate Data Sustain

T33

LBC to Valid Indicate Data

T34

Request Data to LBC Setup Time

15

ns

T35

Request Data to LBC Hold Time

5

ns

~

C

Parameter

LBC

7

ns
45

ns

'r-

-'
.....

AIP,BIP,
AIC,BIC, AID,BID

T30

Jm

--

J

..... T31 I-

~.

VALID DATA

XX)

VALID DATA

'IJ

-T34----- !--T35 .....
ARP, BRP,
ARC,BRC,
ARD,BRD

J

VALID DATA
TLlF/10386-37

FIGURE 7·7. PHY Port Interface Timing

,

2-118

c

."

7.0 Electrical Characteristics (Continued)

CD

Co)

N
U'I

AC Characteristics for the Serial Interface
Symbol

Parameter

Conditions

Min

Typ

Max

Units

T36

RXD to RXC Setup Time

2

ns

T37

RXD to RXC Hold Time

2

ns

T38

TXC to TXD Change Time

8

ns

T39

TXC to LBD Change Time

8

ns

T40

CD Min Pulse Width

120

ns

T41

SD Min Pulse Width

120

ns

RXC+/-

RXD+/-

TXC+/-

TXD+/-

LBD+/-

;

CD

SD

'~=1
141

f

~

FIGURE 7-8. Serial Interface Timing

2·119

TL/F/l038B-38

.....
.....
C

."
CD

Co)

N
U'I
U'I

~r-------------------------------------------------------------------~

N

CO)

~

C
......
.\I)

7.0 Electrical Characteristics (Continued)
7.5 AC TEST CIRCUITS

N

CO)

~

C

Tl/F/l0386-28

FIGURE 7·10. Switching Test Circuit
for All TTL Output Signals

2k.Q

-

521.
TLlF/l0386-26

Note: 51 is closed for TPZL and TPLZ
52 is closed for TPZH and TPHZ
51 and 52 are open otherwise

FIGURE 7·9. Switching Test Circuit
for All TRI-STATE Output Signals

TL/F/l0386-30

Note: CL = 30 pF Includes seepe and all stray capacitance without device In
test fixture

TL/F/l0386-29

FIGURE 7-11. Switching Test Circuit
for All Open Drain Output Signals
(INT, ACK and eli)

FIGURE 7·12. Switching Test Circuit
for All ECL Input and Output Signals

2·120

IC
"tI

Test Waveforms

00
Co)

N

....
.....
U1

IC
"tI
00

VCC -l.165V

VCC -1.475V

Co)

...F\...

N

U1
U1

,

i~-1.4V
, J ,~V
'CC- ,.~'

,~'

TLlF/l0386-39

FIGURE 7-13. EeL Output Test Waveform

3.0V

''='"
,

OVJ. 1.5V

\....

'~

:~

,~.'

TL/F/l0386-40
Note: All CMOS inputs and outputs are TTL compatible

FIGURE 7-14. TTL Output Test Waveform

--7:'" 1.5V
___-+,___...J11.5V
,T
,
pHZ
0/,

LBC

CBD<7:0>I I< CBP

f

~
:

;TpLZ,
~,

,

1.5V'

,

VOL +O.5V
TL/F/l0386-41

FIGURE 7-15. TRI-STATE Output Test Waveform

2-121

II)
II)

C"I
CO)

co

a.

C
.....
....

~
CO)
co

a.
C

8.0 Detailed Descriptions
8.2 NOISE EVENTS

This section describes in detail several functions that had
been discussed previously in Section 3.0, Functional Descriptions .

A Noise Event is defined as follows:
A noise event is a noise byte, a byte of data which is not in
line with the current line state, indicating error or corruption.

8.1 FRAMING HOLD RULES
DETECTING JK

Noise Event = [SO. - CD) +

The JK symbol pair can be used to detect the beginning of a
frame during Active Line State (ALS) and Idle Line State
(ILS).

[SO • CD • PI • - (II + JK + AB)) +
[SO • CD • - PI • (PB = II) • AB)

While the Line State Detector is in the Idle Line State the
PLAYER device "reframes" upon detecting a JK symbol
pair and enters the Active Line State.
During Active Line State, acceptance of a JK symbol (reframing) is allowed on anyon-boundary JK which is detected at least 1.5 byte times after the previous JK.

Where:

•
+

Logical AND
Logical OR
Logical NOT

SO = Signal Detect
CD = Clock Detect
Previous Byte
PB
PLS = Previous Line State

During Active Line State, once reframed on a JK, the subsequent off-boundary JK is ignored, even if it is detected beyond 1.5 byte times after the previous JK.
During Active Line State, an Idle or Ending Delimiter
symbol will allow reframing on any subsequent JK, if a JK is
detected at least 1.5 bytes times after the previous JK.

m

PI

DETECTING HALT·HALT 8. HALT·QUIET
During Idle Line State, the detection of a Halt-Halt, or HaltQuiet symbol pair will still allow the reframing of any subsequent on-boundary JK.

PHY Invalid = HLS + QLS +
NLS + ( ULS •
(ALS + ILS))l

ILS = Idle Line State
ALS = Active Line State
ULS = Unknown Line State

Once a JK is detected during Active Line State, off-boundary Halt-Halt, or Halt-Quiet symbol pairs are ignored until the
Elasticity Buffer (EB) has an opportunity to recenter. They
are treated as violations.

HLS = Halt Line State
QLS = Quiet Line State
MLS = Master Line State
NLS = Noise Line State
ULS = Unknown Line State

After recentering on a Halt-Halt, or Halt-Quiet symbol pair,
all off-boundary Halt-Halt or Halt-Quiet symbol pairs are ignored until the EB has a chance to recenter during a line
state other than Active Line State (which may be as long as
2.8 byte times).

J
K
R

S

2-122

Idle symbol
First symbol of start delimiter
Second symbol of start delimiter
Reset symbol
Set symbol

T

End delimiter

A
B

n+R+S+T

n

= Any data symbol

n+R+S+T+1

MLS
[PLS

+

.----------------------------------------------------------------------.0
;g

8.0 Detailed Descriptions (Continued)

Co)

N
U1

8.3 LINK ERRORS

.....
......
o

A Link Error is defined as follows:

;g

Link Error Event = [ALS • (1-1 + xV + Vx +
H-H)) + [ALS. -SOl + [ILS.
-(II + JK)) + ilLS. -SD)1 +
[ULS • (PLS = ALS) • LinLError_Flag • - SB • - (HH + HI +
II + JK)1
Set LinLError_Flag = [ALS • (HH
SH + TH)1

+

NH

+

RH

Co)

N
U1
U1

+

Clear LinLError_Flag = [ALS. JKI + ilLS. JKI +
[ULS • (PLS = ALS •
LinLError_Flag • - SB •
- (HH + HI + II + JK)1
Where:

+

Logical NOT
Logical OR

•

Logical AND

ILS
Idle Line State
ALS = Active Line State
ULS = Unknown Line State
x

= Any symbol

H
J
K
V

= Halt symbol

R
S

= Reset symbol

T
N

= End delimiter symbol

Idle symbol
= First Symbol of start delimiter
= Second symbol of start delimiter
= Violation symbol
= Set symbol
= Data symbol converted to 0000 by the PLAY-

ER device Receiver Block in symbol pairs that
contain a data and a control symbol
PLS = Previous Line State
SO = Signal Detect
SB = Stuff Byte: Byte inserted by EB before a JK
symbol pair for recentering or due to off-axis
JK

2-123

Ln r-------~----------------------------------------------------------------------__,
Ln
N

CO)

8.0 Detailed Description (Continued)

C
.....
.,...

The repeat filter prevents the propagation of code violations to the downstream station .

co
D.;

8.4 REPEAT FILTER

Ln
N

CO)

~

C

REPEAT
nn

~
JK

~

END

IDLE
WW

TW
TW

JK+TPARITY

~

JK
JK

WW

:Ll

WI
F_IDLE

OK·W) + TPARITY
NT
NT

"

"

JK
JK

TW
TI
NI+IX
(PHY VALID)
(V'+I') ALSZILSZ

"

"HALT
(H+S+R+V)X+N(f·~ + TPARITY

a·JK)x + TPARITY

HH
JK
JK

HH
IX

"

(PHY VALID)
(V'+I') ALSZILSZ
HH
TL/F/l0386-31
Note: Inputs to the Repeat Filter state machine are shown above tha transition lines, while outputs from the state machine are shown below the transition lines.
Nota: Abbreviations used in the Repeat Filter State Diagram are shown in Table VIII.

FIGURE 8·1. Repeat Filter State Diagram

2·124

8.0 Detailed Descriptions (Continued)
The Repeat Filter complies with the FOOl standard by ob·
serving the following:
1. In Repeat State, violations cause transitions to the Halt
State and two Halt symbol pairs are transmitted (unless
JK or Ix occurs) followed by transition to the Idle State.
2. When Ix is encountered, the Repeat Filter goes to the Idle
State, during which Idle symbol pairs are transmitted until
a JK is encountered.
3. The Repeat Filter goes to the Repeat State following a JK
from any state.
The END State, which is not part of the FOOl standard,
allows an R or S prior to a T within a frame to be recognized
as a violation. It also allows NT to end a frame as opposed
to being treated as a violation.

TABLE 8·1. Abrevlatlons used In

the Repeat Filter State Diagram
Force Idle-True when not in Active
Transmit Mode
W:
Represents the symbols R, or S, or T
-TPARITY: Parity error
nn:
Data symbols (for C = 0 in the PHY·MAC
Interface)
N:
Data portion of a control and data symbol
mixture
X:
Any symbol (i.e. don't care)
V':
Violation symbols or symbols inserted by
the Receiver Block
I':
Idle symbols or symbols inserted by the
Receiver Block
Active Line State or Idle Line State (i.e.
ALSZILSZ:
PHY Invalid)
- ALSZILSZ: Not in Active Line State nor in Idle Line
State (i.e. PHY Valid)
H:
Halt symbol
R:
Reset symbol
S:
Set symbol
T:
Frame ending delimiter
Frame start delimiter
JK:
I:
Idle symbol (Preamble)
V:
Code violations

•
2·125

~r--------------------------------------------------------------------,
~

N

C')

~

C
.....
....

8.0 Detailed Descriptions (Continued)
8,5 SMOOTHER

CONTRACT

EXTEND

~

N

C')

SE + F_IDLE

co

a.

~

C

SE+F_IDLE

II

II'X n_1= w.

Xn
C=C+ 1

Xn+1
C= C +1

_

.

R'c>o

. 1I'(Xn- 1 = II +X n- 1 = nn)

...
jj'JK

Xn
C= C+ 1

Xn
C=C+ 1

.

......
JK'C> 7'X n_1 = II

JK'C< 7'X n_1= II

Xn- I

...

Xn
C=O

Xn
C=O

JK'X n_1 = II

......

Xn- 1
C=O

-II'JK'C = 0
Xn

..L

""

.
Notes:
SE: Smoother Enable
C: Preamble Counter
F_IDLE: Force_Idle (Stop or A'fM)
Xn: Current Byte
Xn-l: Previous Byte

TL/F/l0388-32

WoRST

FIGURE 8-2, Smoother State Diagram

2·126

C

."

co
Co)

8.0 Detailed Descriptions (Continued)
Line State are Idle symbols, then the Symbol Decoder generates l'kiLS as its output. Note that in this case the coded
byte is represented in the form Receive State (b7-4),
Known/Unknown Bit (b3) and the Last Known Line State
(b2-0). The Receive State is 4 bits long and it represents
either the PHY Invalid (0011) or the Idle Line State (1011)
condition. The Known/Unknown Bit shows if the symbols
received match the line state information in the last 3 bits.

8.6 NATIONAL BYTE·WIDE CODE FOR PHY·MAC IN·
TERFACE

The PLAYER device outputs the National byte-wide code
from its PHY Port Indicate Output to the MAC device. Each
National byte-wide code may contain data or control codes
or the line state information of the connection. Table 8-2
lists all the possible outputs.
During Active Line State all data and control symbols are
being repeated to the PHY Port Indicate Output with the
exception of data in data-control mixture bytes. That data
sybmol is replaced by zero. If only one symbol in a byte is a
control symbol, the data symbol will be replaced by 0000
and the whole byte will be presented as control code. Note
that the Line State Detector recognizes the incoming data
to be in the Active Line State upon reception of the Starting
Delimiter (JK symbol pair).

During any line state other than Idle Line State or Active
Line State, the Symbol Decoder generates the code V'kLS
if the incoming symbols match the current line state. The
symbol decoder generates V'uLS if the incoming symbols
do not match the current line state.

During Idle Line State any non Idle symbols will be reflected
as the code l'uILS. If both symbols received during Idle

2-127

~

U1

.....
.......
C

."

co
Co)

~

U1

II)
II)

N

Cf)

~

8.0 Detailed Descriptions (Continued)
Table 8-2.

C
......
....

Current Line State

II)

N

Cf)

Symbol 1
Data
Control Bit

Symbol 2
Control Bit
Data

National Code
Control Bit
Data

co

ALS

0,

n

0,

n

0,

non

C

ALS

0,

n

1,

C

1,

N-C

a.

ALS

1,

C

0,

n

1,

CoN

ALS

1,

C

1,

C

1,

C-C

ILS

1,

I

1,

I

1,

I'-k-LS

ILS

1,

I

x,

Not!

1,

I'-u-LS

ILS

Not!

1,

I

1,

I'-u-LS

Not I

1,

I'-u-LS

x

x,
x,

Not!

Stuff Byte during ILS

x,
x,
x,

x

1,

I'-k-ILS

Not ALS and Not ILS

1,

M

1,

M

1,

V'-k-LS

Not ALS and Not ILS

1,

M

x,

NotM

1,

V'-u-LS

Not ALS and Not ILS

x,
x,
x,

NotM

1,

M

1,

V'-u-LS

NotM

x,
x,

NotM

1,

V'-u-LS

x

1,

V'-k-LS, V'-u-LS
or I'-u-ILS

ILS

Not ALS and Not ILS
Stuff Byte during
NotlLS

x

EB Overflow/Underflow

1,

00111011

SMT PI Connnection (LSU)

1,

00111010

Where:
n = Any data symbol in [0,1,2, ... Fl
C = Any control symbol in [V, R, S, T, I, HI
N = 0000 = Code for data symbol in a data control mixture byte
I = Idle Symbol
M = Any symbol that matches the current line state
I' = 1011 = First symbols of the byte in Idle Line State
V' = 0011 = PHY Invalid
LS = Line State
ALS = 000
ILS = 001
NSD = 010
MLS = 100
HLS = 101
QLS = 110
NLS = 111
u = 1 = Indicates symbol received does not match current line state
k = 0 = Indicates symbol received matches current line state
x = Don't care

2-128

C
'"D

8.0 Detailed Descriptions (Continued)

Q)

Example:

(II

W
N

Incoming 5B Code

Decoded 4B Code

National Byte-Wide Code (wlo parity)

.....
.....

9876543210

C321 0 C 3210

C 7653 3210

Q)

1111111111 (II)

1 10101 1010 (II)

110110001 (I'-k-ILS)*

W
N

11111 11111 (II)

1 10101 1010 (II)

110110001 (I'-k-ILS)

1111111111 (II)

1 10101 1010 (II)

110110001 (I'-k-ILS)

11000 10001 (JK)

1110111101 (JK)

1 1101 1101 (JK Symbols)

...... --

--- -- (xx)

O----O----(xx)

0----

- - - - (Data Symbols)

..........
..........

-----(xx)

0----0---- (xx)

0----

- - - - (Data Symbols)

--- -- (xx)

O----O----(xx)

0----

- - - - (Data Symbols)

(More data ...)

..........
..........

---- - (xx)

O----O----(xx)

0- - --

- - - - (Data Symbols)

--- -- (xx)

0----0---- (xx)

0----

- - - - (Data Symbols)

-----

--- -- (xx)

O----O----(xx)

0- - --

- - - - (Data Symbols)

01101 00111 (TR)

1010110110 (TR)

1 0101 0110 (T and R Symbols)

0011100111 (RR)

1011010110 (RR)

1 01100110 (Two R Symbols)

11111 11111 (II)

1 10101 1010 (II)

1 1010 1010 (Idle Symbols)

11111 11111 (II)

1101011010 (II)

110101010 (Idle Symbols)

11111 11111 (II)

1101011010(11)

110110001 (I'-k-ILS)
110110001 (I'-k-ILS)

1111111111 (II)

1101011010 (II)

11111 11111 (II)

1 10101 1010 (II)

1 10110001 (I'-k-ILS)

0010000100 (HH)

1 0001 1 0001 (HH)

110111001 (I'-u-ILS)

0010000100 (HH)

1 0001 1 0001 (HH)

110111001 (I'-u-ILS)

0010000100 (HH)

1 0001 1 0001 (HH)

110111001 (I'-u-ILS)

0010000100 (HH)

1 0001 1 0001 (HH)

110111001 (I'-u-ILS)

0010000100 (HH)

1 0001 1 0001 (HH)

110111001 (I'-u-ILS)

0010000100 (HH)

1 0001 1 0001 (HH)

110111001 (I'-u-ILS)

0010000100 (HH)

1 0001 1 0001 (HH)

110111001 (I'-u-ILS)

0010000100 (HH)

1 0001 1 0001 (HH)

100110101 (V'-k-HLS)

0010000100 (HH)

1 0001 1 0001 (HH)

1 0011 0101 (V'-k-HLS)

0010000100 (HH)

1 0001 1 0001 (HH)

100110101 (V'-k-HLS)

11111 11111 (II)

1101011010(11)

1 0011 1101 (V'-u-HLS)

11111 11111 (II)

1 101011010 (II)

110110001 (I'-k-ILS)

1111111111 (II)

1 10101 1010 (II)

110110001 (I'-k-ILS)

·Assume the receiver is in the Idle Line State.

2-129

C

'"D

(II
(II

~

r------------------------------------------------------------------------------------,

I ~National
c

~ Semiconductor

OP83261 BMACTM Oevice
(FOOl Media Access Controller)
General Description

Features

The OP83261 BMAC device implements the Media Access
Control (MAC) protocol for operation in an FOOl token ring.
The BMAC device provides a flexible Interface to the BSITM
device. The BMAC device offers the capabilities described
in the ANSI X3T9.5 MAC Standard and several functional
enhancements allowed by the Standard.

• Full duplex operation with through parity
• Supports all FOOl ring scheduling classes (asynchronous, synchronous, restricted asynchronous, and
immediate)
• Supports individual, group, short, long and external
addressing
• Generates Beacon, Claim and Void frames without
intervention
• Provides extensive ring and station statistics
• Provides extensions for MAC level bridging
• Provides separate management interface
• Uses low power microCMOS

The BMAC device transmits, receives, repeats, and strips
tokens and frames. It uses a full duplex architecture that
allows diagnostic transmission and self testing for error isolation. The duplex architecture also allows full duplex data
service on point-to-point connections. Management software is also aided by an array of on chip statistical counters,
and the ability to internally generate Claim and Beacon
frames without program intervention. A multi-frame streaming interface is provided to the system interface device.

TO HOST SYSTEM

DP83241
COD
(CLOCK
DISTRIBUTION)

DP83231
CRD
(CLOCK
RECOVERY)

'----...r--'
TO FIBER OPTIC
TRANSCEi.ER PAIR

FIGURE 1-1. FOOl Chip Set Block Diagram

2-130

TL/F/10387-1

Table of Contents
1.0 FOOl CHIP SET OVERVIEW

6.0 CONTROL INFORMATION
6.1 Conventions
6.2 Access Rules
6.3 Operation Registers
6.4 Event Registers
6.5 MAC Parameters
6.6 Timer Thresholds
6.7 Event Counters

2.0 ARCHITECTURAL DESCRIPTION
2.1 Ring Engine
2.2 Interfaces
3.0 FEATURE OVERVIEW
4.0 FOOl MAC FACILITIES
4.1 Symbol Set
4.2 Protocol Data Units
4.3 Frame Counts
4.4 Timers
4.5 Ring Scheduling

7.0 SIGNAL DESCRIPTIONS
7.1 Control Interface
7.2 PHY Interface
7.3 MAC Indication Interface
7.4 MAC Request Interface
7.5 Electrical Interface
7.6 Pinout Summary
7.7 Pinout Diagram

5.0 FUNCTIONAL DESCRIPTION
5.1 Token Handling
5.2 Servicing Transmission Requests
5.3 Request Service Parameters
5.4 Frame Validity Processing
5.5 Frame Status Processing
5.6 SMT Frame Processing
5.7 MAC Frame Processing
5.8 Receive Batching Support
5.9 Immediate Frame Transmission
5.10 Full Duplex Operation
5.11 Parity Processing

8.0 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
8.2 Recommended Operating Conditions
8.3 DC Electrical Characteristics
8.4 AC Electrical Characteristics
APPENDIX A. RING ENGINE STATE MACHINES

A.l Receiver
A.2 Transmitter

2-131

,..

CD

N

C')

CO

a..

C

r---------------------------------------~--------------------------------------------,

1.0 FDDI Chip Set Overview
National Semiconductor's DP83200 FDDI chip set consists
of five components as shown in Figure't-t. For more information on the other devices of the chip set, consult the
appropriate datasheets and application notes.

DP83261 BMACTM Device
Media Access Controller
The BMAC device implements the Timed Token Media Access Control protocol defined by the ANSI X3T9.5 FDDI
MAC Standard.

DP83231 CRDTM Device
Clock Recovery Device

Features

The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream.

• All of the standard defined ring service options. '
• Full duplex operation with through parity

Features
• PHY Layer loopback test
• Crystal controlled
• Clock locks in less than 85

• Supports all FDDI Ring Scheduling Classes (Synchronous, Asynchronous, etc.)
• Supports Individual, Group, Short, Long, and External
Addressing

"'S

• Generates Beacon, Claim, and Void frames internally

DP83241 CDDTM Device
Clock Distribution Device

• Extensive ring and station statistic gathering
• Extensions for MAC level bridging
• Separate management port that is used to configure and
control operation
''

The Clock Distribution Device generates the clocks required
by the FDDI Devices on a board.

• Multi-frame streaming interface

Features

"
..
• Utilizes a 12.5 MHz crystal or reference

DP83265 BSITM Device
System Interface

• Generates the 125 MHz, 25 MHz, and 1,2.5 MHz clock
required by the BMAC, PLAYER, and BSI devices

The BSI device implements the interface between the
BMAC device and a host system.

• Generates 5 phases of the 12.5 MHz clock for use by
external system logic

Features

DP83251155 PLAYERTM Device
Physical Layer Controller

• 32-bit wide Address/Data path with byte parity
• Programmable transfer burst sizes of 4 or 8 32-bit words
• Interfaces to low cost DRAMs or directly to system bus

The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FDDI PHY X3T9.5 Standard.

• Provides 2 Output and 3 Input Channels
• Supports Headerllnfo splitting
• Operates from 12.5 MHz to 25 MHz synchronously with
the host system

Features
• 4B/5B encoders and decoders

• Efficient data structures

• Framing logic
• Elasticity Buffer, Repeat Filter and Smoother

• Programmable Big or Little Endian alignment
• Full duplex data path allows transmission to self

• Line state detector/generator

• Confirmation status batching services

• Link error detector

• Receive frame filtering services

• Configuration switch
• Full duplex operation
• Separate management port that is used to configure and
control operation
In addition, the DP83255 contains an additional PHY_
Data.request and PHY_Data.indicate port required for concentrators and dual attach stations.

2-132

r----------------------------------------------------------------------.c

"tI

co
Co)

2.0 Architectural Description
Source Address. Frames with a Source Address matching
one of the station individual addresses are stripped by the
Ring Engine. Status is available at the MAC interface for
every transmitted frame.

The BMAC device receivers, transmits, and strips or repeats
Protocol Data Units (PDUs, i.e., Tokens and Frames) and
handles the token management functions required by the
timed token protocol in accordance with the FOOl MAC
Standard.

For reception, the Ring Engine sequences through the incoming byte stream, comparing received destination addresses against the station's short or long address. The results of these comparisons are made available at the MAC
interface. The System Interface then decides how to handle
the frame. In the normal case, a frame with a Destination
Address matching one of the station addresses is copied
and passed to the system.

The BMAC device is comprised of the Ring Engine (RE) and
interfaces to the Control Bus (Control Interface), the
PLAYER device (PHY Interface) and a System Interface
such as the BSI device (MAC Interface) as shown in
Figure 2-1.
On transmission, the system interface prepares one or more
frames for transmission and requests a service opportunity.
Based on the requested service class and requested token
type, the Ring Engine waits for a token meeting the requested criteria. When a token is captured, the Ring Engine signals the interface and soon thereafter transmission begins.
After traversing the ring, frames are stripped based on the

...

The BMAC device utilizes a full duplex, byte-wide (symbol
pair) architecture. There are two bytes of delay in the Transmit path, three bytes of delay in Receive and Repeat paths,
and two bytes of delay in the Loopback path.

To HOST SYSTEM
H
Flags II:
Control
Signals

MA..INDICATE (7:0)
MA..INDICATE PARITY

I

Transmit"
Parameters II:
Handshake
Signals ~

~

MA..REQUEST (7:0)
MA.:..REQUEST PARITY

~"

I

MAC INTERFACE

r---

8
z

iI
0
r-

ID

RING ENGINE

I

I

I

PHY INTERFACE
.oil

"PH_INDICATE (7:0)
PH_INDICATE CONTROL
PH_INDICATE PARITY

PH_REQUEST (7:0)
PH_REQUEST CONTROL
PH_REQUEST PARITY

c

'"z
;;:I

'"n>!

...

I-

.
...

0'

...

I
r-

ID

c

'"

'II"
To PLAYER DEVICE
TUF/10387-2

FIGURE 2-1. BMAC Device Interfaces

2-133

...
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r-----------------------------------------------------------------------------------------~

~

2.0 Architectural Description

c

2.1 RING Er,lGINE
The BMAC device is operated by the'Ring Engine which is
comprised of four blocks: Receiver, Transmitter, MAC Pa,
rameter RAM, and Counters/Timers as shown in Figure 2-2.

~

(Continued)
lected. During Frame Repeating, data from the Receiver
Block is selected.
During Frame Transmission, thEi Transmitter Block performs
the following functions:
'
• Captures a token to gain the right to transmit

2.1.1 Receiver
The Receiver Block accepts data from the PLAYER device
in the, byte stream format (PH_Indicate).
Upon receiving the data, the Receiver Slack performs the
following functions: .
.
,

• Transmits one or more frames
• Generates the Frame Check Sequence during transmission and appends it at the end of the frame
• Generates the Frame Status field that is transmitted at
the end of the frame

• Determines the beginning and ending of a Protocol Data
Uflit(PDU)
• Decodes the Frame Control field to determine the PDU
type (frame or token)

• Issues the token al'the erid of frame transmission'
During Frame Repeating, the Transmitter Block performs
the following functions:
• Repeats the received frame and modifies the Frame
Status field at the end of the frame as specified by the
standard

• Compares the received Destination and Source Addresses with the internal addresses
• Processes data within the frame
• Calculates and checks the Frame Check Sequence at
the end of the frame

Whether transmitting or repeating frames, the Transmitter
Block also performs the following functions:
• Strips the frame(s) that are transmitted by this station

• Checks the Frame Status field
And finally, the Receiver Biock presents the data to the
MAC Interface along with the appropriate control signals
(MLlndicate).

• Generates Idle symbols between frames
Data is presented from the Transmitter Block to the
PLAYER device in the byte stream format (PH_Request).

2.1.2 Transmitter

2.1.3 MAC Parameter RAM

The Transmitter Block inserts frames from this station into
the ring in accordance with the FDDI Timed Token MAC
protocol. It also repeats frames from other stations in the
ring. The Transmitter block multiplexes data from the ML
Request Interface and data from the Receiver Block. During
Frame Transmission, data from the Request Interface is se-

The MAC Parameter RAM block is a dual port RAM that
contains MAC parameters such as the station's short and
long addresses. These parameters are initialized via the
Control Interface. Both the Receiver and Transmitter Blocks
may access the RAM.

To MAC INTERFACE
A

~A..lndlcate

Flags Be
Control
Signals

" " , i,':> '
.,'

.1 Parameter 1

AMC

,0,

I

<::::FCSf'l

........
,"

,',

.....

,'

,'

.'

,','
"

..........

':':~":'.::

.::::
,"

I

TSM

RSM

',"

...... .

',"

",'.'

",

., .. '

....

.

...... . ., ,' ,, ''

",

",

ROM:

I Countersl
TImers I

,','

....

RAM

.:

f

".,'

Repeat Path

.....

, ' , ' ",'

['~~s';;i\t~r :;';:;::
QU D'."'-\..1.

To PHY INTERFACE
TLlF1103B7-4

FIGURE 2-2. Ring Engine OV6i"ylew Block Clagiam

2-134

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2.0 Architectural Description

(Continued)
The Receiver uses these parameters to compare addresses
in incoming frames with its addresses stored in the Parameter RAM.
The Transmitter uses the Parameter RAM for generating the
Source Address for all frames (except when Source Address Transparency is enabled) and for the Destination Address and Information fields in Claim and Beacon frames.
The MAC Parameter RAM block is described in greater details in Section 6.5.
2.1.4 Counter/Timer
The Counter/Timer block maintains all of the Counters and
Timers required by the Standard.

Co)

The MAC Interface is synchronous and is divided into separate MAC Request and MAC Indication interfaces.
Data is transferred from the system interface to the Ring
Engine via the MAC Request Interface. The M~Request
Interface consists of a parity bit (Odd parity) and byte-wide
data along with the transmit parameters and handshake signals. The MAC Request Interface utilizes a handshake that
separates token capture from data transmisson. A captured
token may be held until it is no longer usable. Void frames
are automatically generated to allow data interface logic as
much time as it needs to prepare a transmission.

N

G)

.....

Data is transferred from the Ring Engine to the system interface via the MAC Indication Interface. The M~lndicate
Interface consists of a parity bit (Odd parity) and byte-wide
data along with Addressing Flags and Frame Sequencing
signals. The Addressing Flags give the result of the address
comparisons performed by the Ring Engine. These are used
to decide whether to continue to copy or to reject frames.
The MAC Indication Interface also accepts inputs to determine how to set the control indicators and increment the
statistical counters based on external address comparison
logic and frame copying logic. Frames may also be stripped
based on external comparisons.

Events which occur too rapidly for software to count. such
as the various Frame Counts. are included in the Event
Counters. The size of the wrap around counters has been
chosen to require minimal software intervention even under
marginal operating conditions. Most of the Counters increment in response to events detected by the Receiver. The
Counters are readable via the Control Interface.
The Token Rotation and Token Holding Timers which are
used to implement the Timed Token Protocol are contained
within the Timer Block.
The Counters and Timers are described in detail in Sections
6.6 and 6.7.

2.2.3 Control Bus Interface
The Control Interface implements the interface to the Control Bus by which to initialize. monitor and diagnose the operation of the BMAC device. The Control Interface is an
8-bit asynchronous interface in order to minimize pinout and
layout. All information that must be synchronized with the
data stream crosses the MAC Interface.

2.2 INTERFACES
2.2.1 PHY Interface
The PHY Intreface is a synchronous interface that provides
an encoded byte stream to the PLAYER device (the PHY
Request byte stream). and receives an encoded byte
stream from the PLAYER device (the PHY Indication byte
stream).
.

The Control bus is separated completely from the MAC and
PHY Interfaces in order to allow independent operation of
the processor on the Control Bus. The Control Interface
provides the synchronization between the Control Bus and
the Ring Engine.

The BMAC device connects to one or two PLAYER devices
via the PH_Indicate and P~Request Interfaces.
Data is transferred from the PLAYER device to the Ring
Engine via the PH_Indicate Interface. Data is transferred
from the Ring Engine to the PLAYER device via the PH_
Request Interface.
The 10-bit byte transferred in both directions across the
PH_Indicate and PH_Request interfaces consists of one
parity bit (Odd parity). one Control bit. and 8 bits of data.
The Control Bit determines if the 8 data bits are a data
symbol pair or a control symbol pair.

3.0 Feature Overview
The BMAC device implements the standard FDDI MAC protocol. It also provides additional addressing. bridging. and
service class functions to allow maximal flexibility in designing an FDDI station.
The BMAC device offers extensive diagnostic features including a number of diagnostic counters. a dedicated interface for control and configuration. and a capability to perform Self Testing. Furthermore. the BMAC device allows the
tuning of certain parameters to increase the performance of
the network.

2.2.2 MAC Interface
The MAC Interface provides the required information and
handshakes to allow a system interface (such as the
DP83265 BSI) to exploit the capabilities of the Ring Engine.

•
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3.0 Feature Overview

(Continued)
3.1 FDDI MAC SUPPORT
The BMAC device implements the Standard ANSI X3T9.5
FOOl MAC protocol for transmitting, receiving, repeating
and stripping frames. Many of the. capabilities defined in
MAC-2 are included in the BMAC device such as bridging
end station support for setting the control indicators, and
the statistic counters. The BMAC device provides all of the
information necessary to implement the service primitives
defined in the standard.
The BMAC device also implements many of the permitted
extensions to the FOOl-MAC standard as captured In the
FOOl MAC-2 document. These include the extensions for
MAC level bridging, Group Addressing support that can be
used for SMT, reporting of additional events to aid the ring
management processes and enhanced versions of the state
machines.

These counters allow measurement of the following:
• Number of frames transmitted and received by the station
• Number of frames copied as well as frames not copied
because of insufficient buffering
• Frame error rate of an incoming phYSical connection to
the MAC
• Load on the ring based on the number of tokens received and the ring latency
• Ring latency
• Lost frames
The size of these counters has been selected to keep the
frequency of overflow small, even under. worst case operating conditions.
3.6 MANAGEMENT SERVICES
The BMAC device provides management services to the
Host System via the Control Bus Interface. This interface
allows access to internal registers to control and configure
the BMAC device.

3.2 MAC ADDRESSING SUPPORT
Both long (4B-bit) and short (16-bit) addressing are supported simultaneously, for both Individual and Group addresses.
Up to 12B contiguous programmable group addresses and
up to 15 Fixed Group Addresses plus the universal/broadcast address are recognized. Limited operation with null addresses is supported. An interface to external address
matching logic is provided to augment the Ring Engine's
addressing capabilities.
.

3.7 RING PARAMETER TUNING
The BMAC device includes settable parameters to allow
tuning of the network to increase performance over a large
range of network sizes.
The BMAC device supports systems of two stations with
little cable between them to ring configurations much larger
than the 1000 physical attachments and/or 200 km distance that are specified as the default values in the standard.
The BMAC device also handles frames larger than the 4500
byte default maximum frame size as specified in the Standard.

3.3 MAC BRIDGING SUPPORT
Several features are provided to aid in Bridging applications.
On the receive side, external address matching logic can be
used to examine the PH_Indicate byte stream to decide
whether to copy a frame, how to set the control indicators
and how to increment the counters.
On the transmit side, transparency options are provided on
the Source Address, the most significant bit of the Source
Address, and the FCS.

3.8 MULTI-FRAME STREAMING INTERFACE
The BMAC device provides an interface to support a multiframe streaming interface. Multiple frames can be transmitted after a token is captured within the limits of the token
timer thresholds.

In addition, support for an alternate Void stripping mechanism provides maximal flexibility in the generation of frames.
3.4 MAC SERVICE CLASS SUPPORT
All of the FOOl MAC service classes are supported by the
BMAC device. These include the Synchronous, Asynchronous, Restricted Asynchronous, and Immediate service
classes.
For Synchronous transmission, one or more frames are
transmitted in accordance with the station's synchronous
bandwidth allocation.
For Asynchronous transmission, one programmable asynchronous priority threshold is supported in addition to the
threshold at the Negotiated Target Token Rotation time.
For Restricted Asynchronous transmission, support is provided to begin, continue and end restricted dialogues.
For Immediate transmissions, support is provided to send
frames from either the Oata, Beacon or Claim states and
either ignore or respond to the received byte stream. After
an immediate transmission a token may optionally be issued.

3.9 GENERATES BEACON, CLAIM,
AND VOID FRAMES INTERNALLY
For purposes of transient token and ring recovery, no processor intervention is required. The BMAC device automatically generates the appropriate MAC frames.
3.10 SELF TESTING
Because the BMAC device is full duplex, loopback testing is
possible before entering the ring and during normal ring operation.
There are several posible loopback paths:
• internal to the BMAC device
• through the PLAYER device(s) using the PLAYER device
configuration switch
• through the CRO device.
These paths allow error isolation down to the device level.
The BMAC device also supports through parity.

3.5 DIAGNOSTIC COUNTERS
The BMAC device includes a number of diagnostic counters
that monitor ring and station performance.

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4.0 FOOl MAC Facilities
4.1 SYMBOL SET

4.2 PROTOCOL DATA UNITS

The Ring Engine recognizes and generates a set of sym·
bois. These symbols are used to convey Une States (such
as the Idle Une State), Control Sequences (such as the
Starting and Ending Delimiters) and Data.
Additional information regarding the symbol set can be
found in the FDDI PHY Standard.

The Ring Engine recognizes and generates two types of
Protocol Data Units (PDUs): Tokens and Frames.
The Token is used to control access to the ring. Only the
station that has captured the token has the right to transmit
new information. The format of a token is shown in Figure
4·1.

The Ring Engine expects that the Starting Delimiter will al·
ways be conveyed on an even symbol pair boundary. Fol·
lowing the starting delimiter, data symbols should always
come in matched pairs. Similarly the Ending Delimiter
should always come in one or more matched symbol pairs.

FIGURE 4-1. Token Format
Frames are used to pass information between stations. The
format of a frame is shown in Figure 4·2 with the field defini·
tions in Table 4·2.

The symbol pairs conveyed at the PHY Interface are shown
in Table 4·1.

FIGURE 4-2. Frame Format
TABLE 4-1. Symbol Pair Set
Type

Symbols

Starting Delimiter

JK

Ending Delimiter

TT orTR orTS or nT

Frame Status

RR orRS orSR orSS

Idle

II or nl

Data Pair

nn

Note: n represents any data symbol (O-F).
Symbol pairs others than the defined symbols are treated as code violations.
Section 7.2 has additional information on the symbol pairs generated and interpreted by the Ring Engine.

TABLE 4-2. PDU Fields
Name

Description

SFS

Start of Frame Sequence

Size

PA

Preamble

8 or More Idle Symbol Pairs

SD

Starting Delimiter

JK Symbol Pair

FC

Frame Control Field

1 Data Symbol Pair

DA

Destination Address

2 or 6 Symbol Pairs
2 or 6 Symbol Pairs

SA

Source Address

INFO

Information Field

FCS

Frame Check Sequence

EFS

End of Frame Sequence

ED

Ending Delimiter

At Least 1T Symbol for Frames;
At Least 2T Symbols for Tokens

FS

Frame Status

3 or More R or S Symbols

2·137

4 Symbol Pairs

N

....

Q)

....
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a.
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4.0 FDDI MAC Facilities (Continued)
TABLE 4-4. MAC/SMT Frames Types

4.2.1 PDU Fields
Start of Frame. Sequence

CLFF

rZZZ

PDUType

The Start of Frame Sequence (SFS) consists of the Preamble (PA) followed by the Starting Delimiter (SD).

1000

0000

Non-Restricted Token

1100

0000

Restricted Token

OLOO

0000

Void Frame

OLOO

0001 to
1110

SMTFrame

OLOO

1111

SMT Next Station
Addressing Frame

1LOO

·0001

Other MAC Frame

1LOO

0010

MAC Beacon Frame

1LOO

0011

MAC Claim Frame

1LOO

0100 to
1111

Other MAC Frame

The Preamble is.a sequence of zero or more Idle symbols
that is used to separate the PDUs. The Ring Engine Receiver can process and repeat a frame or token with no preamble. The Ring Engine Transmitter generates frames with at
least 8 bytes of preamble. The Ring Engine Transmitter also
guarantees that valid FDDI frames will never be transmitted
with more than 40 bytes of preamble.
The Starting Delimiter is used to indicate the start of a new
PDU. The Starting Delimiter is the JK symbol pair.
The Ring Engine expects the Starting Delimiter to be conveyed across the PH_Indication Interface as a single byte.
Similarly, the Ring Engine only generates Starting Delimiters
aligned to the byte boundary.
Frame Control
The Frame Control (FC) field is used to discriminate PDUs.
For tokens, the FC field identifies Restricted and Non-restricted tokens. For frames, the FC field identifies the frame
types and format and how the frame is to be processed.

Destination Address
The Destination Address (DA) field is used to specify the
station(s) that should receive and process the frame.
The DA can be an Individual or Group address. This is determined by the Most Significant Bit of the DA (DAIG).
When DAIG is 0 the DA is an Individual Address, when
DA.lG is 1 the DA is a Group Address. The Broadcast/Universal address is a Group Address.

The one byte FC field is form~tted as shown in Figure 4-3.
IclLIFFlrltzzl
FIGURE 4-3. Frame Control Field
The C (Class) bit specifies the MAC Service Class as Asynchronous (C = 0) or Synchronous (C == 1).

The DA field can be a Long or Short Address. This is determined by the L bit in the FC field (FC.L). If FC.L is 1, the DA
is a 48-bit Long Address. If FC.L is 0, the DA is a 16-bit
Short Address.

The L (Length) bit specifies the length of the MAC Address
as Short (L = 0) or Long (L = 1). A Short Address is a 16bit address. A Long Addres.s is a 48-bit address.

The Ring Engine maintains both a 16-bit Individual Address,
My Short Address (MSA) and a 48·bit Individual Address,
My Long Address (MLA).

The FF (Format) bits specify the PDU types as shown in
Table 4-3.
The r (Reserved) bit is currently not specified and sh'ould
always be transmitted as Zero (Exception: SMT NSA
Frames).
.

On the receive side, if DAIG is 0 the incoming DA is com·
pared with MLA (if FC.L = 1) or MSA (if FC.L = 0). If the
received DA matches MLA or MSA the frame is intended for
this station and the address recognized flag (A....Flag) is set.
If DAIG is 1, the DA is a Group Address and is compared
with the set of Group Addresses recognized by the Ring
Engine. If a match occurs the address recognized flag
(A....Flag) is set. The A....Flag is used by system interface logic as part of the criteria (with FC.L, DAIG and
M_Flag) to determine whether or not to copy the frame. If
the A....flag is set, the system interface will normally attempt
to copy the frame.

The ZZZ (Control) b.its are used in conjunction with the C
and FF bits to specify the type of PDUs. These bits may be
used to affect protocol processing criteria such as the Priority, Protocol Class, Status Handling, etc.
TABLE 4-3. Frame Control Format Bits
FC.FF

PDUTypes

0

0

SMT/MAC

0

1

LLC

1

0

Reserved for Implementer

1

1

Reserved for Future Standardization

On the transmit side, the DA is provided by the system interface logic as part of the data stream. The length of the
address to be transmitted is determined by the L bit of the
.FC field. (The FC field is also passed in the data stream.)
The Destination Address can be an Individual, Group, or
Broadcast Address.

When the Frame Control Format bits (FG.FFJ indicate a
SMT or MAC PDU, the frame type is identified as shown in
Table 4-4.
.

Source Address
The Source Address (SA) field is used to specify the ad·
dress of the station that originally transmitted the frame.

2-138

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4.0 FOOl MAC Facilities

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co

(Continued)

(0)

N

End of Frame Sequence

The Source Address has the same length as the Destination
Address (i.e., if the DA is a 16-bit Address, the SA is a 16-bit
Address; if the DA is a 4B-bit Address, the SA is a 48-bit
Address).
On the receive side, the incoming SA is compared with either MSA or MLA. If a match occurs between the incoming
SA and this station's MLA or MSA, the M_Flag is set. This
flag is used to indicate that the frame is recognized as having been transmitted by this station and is stripped. The
most significant bit of the SA (SA.IG) is not evaluated in the
comparison.

The End of Frame Sequence (EFS) always begins with a T
symbol and should always contain an even number of symbols. For Tokens an additional T symbol is added. For
frames the Ending Delimiter (ED) is followed by one or more
Frame Status Indicators (FS).
The Frame Status (FS) field is used to indicate the status of
the frame. The FS field consists of three Indicators: Error
Detected (E), Address Recognized (A), and Frame Copied
(C). These Indicators are created and modified as specified
in the Standard.
For frames transmitted by the Ring Engine, the E, A and C
Indicators are appended to all frames and are transmitted
as R symbols. No provisions are made to generate additional trailing control indicators.

On the transmit side, the station's individual address is
transmitted as the SA. Since the SA field is normally used
for stripping frames from the ring, the SA stored by the Ring
Engine normally replaces the SA from the data stream. The
length of the address to be transmitted is determined by the
L bit of the FC field. (The FC field is passed in the data
stream.) The most significant bit of the SA (SA.IG) is normally transmitted as 0, independent of the value passed
through the data stream.

For frames repeated by the Ring Engine, the E, A and C
Indicators are handled as specified in the Standard. Additional trailing control indicators are repeated unmodified
provided they are properly aligned. See Section 5.5 for details on Frame Status Processing.

As a transmission option, the SA may also be transmitted
transparently from the data stream. When the SA Transparency option is used, an alternate stripping mechanism is
necessary to remove these frames from the ring. (The Ring
Engine provides a Void Stripping Option. See Section
7.4.2.4 for futher information.)
As a separate and independent transmission option, the
MSB of the SA may also be transmitted transparently from
the data stream. This is useful for end stations participating
in the Source Routing protocol.

4.2.2 Token Formats
The Ring Engine supports non-restricted and restricted Tokens. See Figures 4-4 and 4-5.

FIGURE 4-4. Non-Restricted Token Format

Information
The Information field (Info) contains the Service Data Unit
(SDU). A SDU is the unit of data transfer between peer users of the MAC data service (SMT, LLC, etc). There is no
INFO field in a Token.

SFS

FC

SD

CO

FIGURE 4-5. Restricted Token Format
Non-Restricted
A non-restricted token is used for synchronous and non-restricted asynchronous transmissions.
Each time the non-restricted token arrives, a station is permitted to transmit one or more frames in accordance with its
synchronous bandwidth allocation regardless of the status
of the token (late or early).

The INFO field contains zero or more bytes.
On the receive side, the INFO field is checked to ensure
that it has at least the minimum length for the frame type
and contains an even number of symbols, as required by the
Standard.
The first 4 bytes of the INFO field of MAC frames (e.g., MAC
Beacon or MAC Claim) are stored in an internal register and
compared against the INFO field of the next MAC frame. If
the data of the two frames match, the Samelnfo signal is
generated. This signal may be used to copy MAC frames
only when new information is present.

Asynchronous transmissions occur only if the token is early
(usable token) and the Token Holding Timer has not
reached the selected threshold.
Restricted
A restricted token is used for synchronous and restricted
asynchronous transmissions only.
A station which initiates the restricted dialogue captures a
non-restricted token and releases a restricted token. Stations that participate in the restricted dialogue are allowed
to capture the restricted token. A station ends the restricted
dialogue by capturing the restricted token and releasing a
non-restricted token.

On the transmit side, the Ring Engine does not limit the
maximum size of the INFO field, but it does insure that
frames are transmitted with a valid DA and SA.
Frame Check Sequence
The Frame Check Sequence (FCS) is a 32-bit Cyclic Redundancy Check that is used to check for data corruption in
frames. There is no FCS field in a Token.
On the receive side, the Ring Engine checks the FCS to
determine whether the frame is valid or corrupted.
On the transmit side, the FCS field is appended to the end
of the INFO field. As a transmission option, appending the
FCS to the frame can be inhibited (FCS Transparency).

4.2.3 Frame Formats
The Ring Engine supports all of the frame formats permitted
by the FDDI standard. All frame types may be created external to the BMAC device and be passed through the MAC
Request Interface to the Ring. The BMAC device also has
the ability to generate Void, Beacon and Claim frames internally.

2-139

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4.0 FOOl MAC Facilities (Continued)
Frames Generated by the Ring Engine
The Ring Engine generates and. detects several frames in
order to attain and maintain an operational ring.

Frames Generated Externally
The Ring Engine transmits frames passed to it from the System Interface. The data portion of the frame is created by
the System Interface. This begins with the FC field and ends
with the last byte of the INFO field. The FC field is passed
transparently to the ring. The length bit in the FC field is
used to determine the length of the transmitted addresses.
The data is passed as a byte stream across the MAC Request Interface as shown in Table 4-5.
Before the frame is transmitted, the Ring Engine inserts the
Start of Frame Sequence with at least 8 bytes of Preamble
but no more than 40 bytes of Preamble. The starting delimiter is transmitted as a JK symbol pair. The Source Address
is normally transmitted by the Ring Engine since it uses the
Source Address to strip the frame from the ring. This can be
overridden by using the Source Address transparency capability. Similarly, the Frame Check Sequence (4 bytes) is normally transmitted by the Ring Engine. This can be overridden with the FCS transparency capability. With FCS transparency, the FCS is transmitted from the data stream. The
End of Frame Sequence is always transmitted by the Ring
Engine as TR RR.
Frames transmitted by the Ring Engine must have a valid
DA and SA field. If the end of a frame is reached before a
valid length is transmitted, the frame will be aborted and a
Void frame will be transmitted.

Void Frames
Void frames are used during normal operation. The Ring
Engine generates two types of void frames: regular Void
frames and My_Void frames. See Table 4-S.
If short addressing is enabled, Void frames with the short
address are transmitted, otherwise Void frames with the
long address are transmitted.
Void frames are transmitted in order to reset the Valid
Transmission timers (TVX) in other stations in order to eliminate an unnecessary entry to the Claim state. Stations are
not required to copy Void frames. Void frames are transmitted by the Ring Engine in two situations:
1. While holding a token when no data is ready to be transmitted.
2. After a frame transmission is aborted.
My_Void frames are transmitted by the Ring Engine in
three situations:
1. After a request to measure the Ring Latency has been·
made when the next early token is captured.
2. After this station wins the Claim Process before the token
is issued.
3. After a frame has been transmitted with the STRIP option
before the token for that service opportunity is issued.
Void frames are also detected by the Ring Engine. A Void
frame with a Source Address other than MSA or MLA is
considered an Other_Void frame.

TABLE 4-5. Frame Formats
Field

Size

PA

:0:8; S:40

SD

1

FC

1

FC

FC

DA

20rS

DA

DA

SA

2 orS

SA

MSA,MLA,
or SA

INFO

:0:0

INFO

INFO

FCS

4 if Present

FCS

FCS

ED

1

TR

FS

1

RR

MLRequest

PH_Request
Idle Pairs
JK

Claim Frames
Claim frames are generated continuously with minimum preamble while the Ring Engine is in the Transmit Claim state.
The format of Claim frames generated by the Ring Engine is
shown in Table 4-7. When long addressing is enabled,
frames with the long address are transmitted, otherwise
frames with the short address are transmitted.
The Ring Engine detects reception of valid Claim frames. A
comparison is performed between the (first) four bytes of
the received INFO field and TREQ in order to distinguish
Higher_Claim, Lower_Claim, and My_Claim. Details are
given in Appendix A.

TABLE 4-6. Void Frames
Type

Enable

Size

SFS

FC

DA

FCS

EFS

MSA

FCS

TRRR

MLA

FCS

TRRR

MSA

MSA

FCS

TRRR

MLA

MLA

FCS

TRRR

Void

ESA

Short

PA

SD

40

Null

Void'

NotESA

Long

PA

SD

00

Null

My_Void

ESA

Short

PA

SD

40

My_Void

NotESA

Long

PA

SD

00

SA

TABLE 4-7. Claim Frames
Type

Enable

Size

My_Claim

NotELA

Short

PA

My_Claim

ELA

Long

PA

FC

DA

SA

INFO

FCS

EFS

SD

83

MSA

MSA

TREQ

FCS

TRRR

SD

C3

MLA

MLA

TREQ

FCS

TRRR

SFS

I
I

2-140

C

"'CJ

4.0 FOOl MAC Facilities (Continued)
4.3.3 Lost Frame Count
The Lost Frame Count (LFCn is specified in the FDDI MAC
Standard, and is the count of all instances where a format
error is detected in a frame or token such that the credibility
of PDU reception is placed in doubt. The Lost Frame Count
is incremented when any symbol other than data or Idle
symbols are received between the Starting and Ending Del·
imiters of a PDU (this includes parity errors).

Beacon Frames
Beacon frames are transmitted continuously with minimum
preamble when the Ring Engine is in the Transmit Beacon
state. The format of Beacon frames generated by the Ring
Engine is shown in Table 4·8. When long addressing is en·
abled, frames with the long address are transmitted, other·
wise frames with the short address are transmitted.
When the Transmit Beacon State is entered from the Trans·
mit Claim State the first byte of the 4 byte TBT Field is
transmitted as Zero.
Beacon frames that require alternative formats such as Di·
rected Beacons must be generated externally.
The Ring Engine detects reception of valid Beacon frames
and distinguishes between Beacon frames transmitted by
this MAC (My_Beacon) and Beacon frames transmitted by
other stations (Other_Beacon). Details are given in Appen·
dix A.

4.3.5 Frames Not Copied Count
The Frames Not Copied Count (FNCT) is specified in the
FDDI MAC·2 Standard, and is the count of frames intended
for this station that were not successfully copied by this
station. The count is incremented when an internal or exter·
nal (when Option.EMIND is enabled) Destination Address
match occurs, no errors were detected in the frame, and the
frame was not successfully copied (VCOPY = 0). This
count is an indication of insufficient buffering or frame pro·
cessing capability for frames addressed to the station. MAC
frames, Void frames and NSA frames received with the A
indicator set are not included in this count.

The size of the counters has been chosen such that minimal
software intervention is required, even under marginal oper·
ating conditions.
The following counts are maintained by the Ring Engine:
Frame Received
Error Isolated
Lost Frame
Frames Copied
Frames Not Copied
Frames Transmitted

4.3.6 Frames TransmItted Count
The Frames Transmitted Count (FTCn is specified in the
FDDI MAC·2 Standard, and is incremented every time a
complete frame is transmitted from the MAC Request Interface. The count is provided as an aid to accumulate station
performance statistics. Void and MAC frames generated by
the Ring Engine are not included in the count.

4.3.1 Frame Received Count
The Frame Received Count (FRCT) is specified in the FDDI
MAC Standard, and is the count of all complete frames reo
ceived. This count includes frames stripped by this station.

4.4 TIMERS

4.4.1 Token Rotation Timer

4.3.2 Error Isolated Count
The Error Isolated Count (EICT) is specified in the FDDI
MAC Standard, and is the count of error frames detected by
this station and no previous station. It increments when:

The Token Rotation Timer (TRn times token rotations from
arrival to arrival. TRT is used to control ring scheduling duro
ing normal operation and to detect and recover from serious
ring error situations.

1. An FCS error is detected and the received Error Indicator
(Er) is not equal to S.
2. A frame of invalid length (I.e., off boundary T) is received
and Er is not equal to S.
3. Er is not R or S.

TRT is loaded with the maximum token rotation time, TMAX,
when the ring is not operational. TRT is loaded with the
negotiated Target Token Rotation Time, TNEG, when the
ring is operational.

TABLE 4-8. Beacon Frames
Type

Enable

Size

My_Beacon

NotELA

Short

PA

My_Beacon

ELA

Long

PA

m
.....

4.3.4 Frame Copied Count
The Frames Copied Count (FCCn is specified in the FDDI
MAC·2 Standard, and is the count of the number of frames
copied by this station. The count is incremented when an
internal or external match occurs (when Option.EMIND is
enabled) on the Destination Address, no errors were detect·
ed in the frame and the frame was successfully copied
(VCOPY = 1). This can be used to accumulate station per·
formance statistics. Frames copied promiscuously, MAC
frames, Void frames and NSA frames received with the A
indicator set are not included in this count.

4.3 FRAME COUNTS
To aid in fault isolation and to enhance the management
capabilities of a ring, the Ring Engine maintains several
frame counts. The Error and Isolated frame counts incre·
ment when a frame is received with one or more errors that
were previously undetected. The Ring Engine then corrects
the error such that a downstream station will not increment
its count.

FRCT
EICT
LFCT
FCCT
FNCT
FTCT

co
~

SFS

I
I

FC

DA

SA

SD

82

Null

MSA

SD

C2

Null

MLA

2·141

INFO

FCS

EFS

TBT

FCS

TRRR

TBT

FCS

TRRR

fII

~

CD
C\I

CO)

CO

a.
Q

r----------------------------------------------------------------------------------------------,
4.0 FOOl MAC Facilities (Continued)
The Latency Counter increments every 16 byte times
(1.28 its) and is used to measure ring latencies up to
1.3421772 seconds directly with an accuracy of 1.2 its. No
overflow or increment event is provided with this counter.

4.4.2 Token Holding Timer
The Token Holding timer (THT) is used to limit the amount
of ring bandwidth used by a station for asynchronous traffic
once the token is captured. THT is used to determine if the
captured token is (still) usable for asynchronous transmis·
sion. A token is usable for asynchronous traffic if THT has
not reached the selected threshold. Two asynchronous
thresholds are supported; one that is fixed at the Negotiated
Target Token Rotation Time (TNEG), and one that is pro·
grammable at one of 16 Asynchronous Priority Thresholds.
Requests to transmit frames at one of the priority thresholds
are serviced when the Token Holding Timer (THT) has not
reached the selected threshold.

4.5 RING SCHEDULING
FDDI uses a timed token protocol to schedule the use of the
ring. The protocol measures load on the network by timing
the rotation of the token. The longer the token rotation time
the greater the instantaneous load on the network. By limit·
ing the transmission of data when the token rotation time
exceeds a target rotation time, a maximum average token
rotation time is realized. The protocol is used to provide
different classes of service.
Multiple classes of service can be accommodated by setting
different target token rotation times for each class of service.
The Ring Engine supports Synchronous, Non-Restricted
Asynchronous, Restricted Asynchronous, and Immediate
service classes. The Immediate service class is supported
when the ring is non-operational; the other classes are supported when the ring is operational.

4.4.3 Late Count
The Late Count (LTCT) is implemented differently than sug·
gested by the Standard, but provides similar information.
The function of the Late Count is divided beween the Late_
Flag that is equivalent to the standard Late Count with a
non·zero value and a separate counter. Late Flag is main·
tained by the Ring Engine to indicate if it is possible to send
asynchronous traffic. When the ring is operational, Late
Count indicates the time it took the ring to recover the last
time the ring went non·operational. When the ring is non·op·
erational, Late Count indicates the time it has taken (so far)
to recover the ring.
'

4.5.1 Synchronous Service Class
The Synchronous service class may be used to guarantee a
maximum response time (2 times TIRT), minimum bandwidth, or both.
Each time the token arrives, a station is permitted to transmit one or more frames in accordance with its synchronous
bandwidth allocation regardless of the status of the token
(late or early; Restricted or Non-Restricted).
Since the Ring Engine does not provide a mechanism for
monitoring a station's synchronous bandwidth ,utilization,
the user must insure that no synchronous request requires
more than the allocated bandwidth.

The Late Count is incremented every time TRT expires
while the ring is non·operational and Late_Flag is set (once
every TMAX).
The Late Count is provided to assist Station Management,
SMT, in the isolation of serious ring errors. In many situa·
tions the ring will recover very quickly and late count will bel
of marginal utility. However in the case of serious ring er·
rors, it is helpful for SMT to know how long it has been since
the ring went non·operational (with TMAX resolution) in or·
der to determine if it is necessary to invoke recovery proce·
dures. When the ring goes no operational there is no way to
know how long it will stay non·operational, therefore a timer
is necessary. If the Late Count were not provided, SMT
would be forced to start a timer every time the ring goes
non·operational even though it may seldom be used. By us·
ing the provided Late Count, an SMT implementation may
be able to alleviate this additional overhead.

To help ensure that synchronous bandwidth is properly allocated after ring configuration, synchronous requests are not
serviced after a Beacon frame is received. After a major
reconfiguration has occurred, management software must
intervene to verify or modify the current synchronous bandwidth allocation.
4.5.2 Non-Restricted Asynchronous Service Class
The Non-Restricted Asynchronous service class is typically
used with interactive and background trafiic. Non-restricted
Asynchronous requests are serviced only if the token is early and the Token Holding Timer has not reached the selected threshold.

4.4.4 Valid Transmission Timer
The Valid Transmission Timer (TVX) is reset every time a
valid PDU is received. TVX is used to increase the respon·
siveness of the ring to errors. Expiration of the TVX indio
cates that no PDU has been received within the timeout
period and causes the Transmitter to invoke the recovery
Claim Process.

Asynchronous service is available at two priority thresholds,
the Negotiated Target Token Rotation Time plus one programmable threshold. Managemef!t software may use the
priority thresholds to discriminate additional classes of traffic based on current loading characteristics of the ring. The
priority thresholds may be determined using the current
TIRT and the Ring Latency. In this case, application software is only concerned with the priority level of a request.

4.4.5 Token Received Count
The Token Received Count (TKCT) is incremented every
time a valid token arrives. The Token Count can be used
with the Ring Latency Count to calculate the average net·
work load over a period of time. The frequency of token
arrival is inversely related to the network load.

As an option, Asynchronous Requests may be serviced with
THT disabled. This is useful when it is necessary to guarantee that a multi-frame request will be serviced on a single
ioken opportuniiy. Because of ihe possibiiiiy of causing laie
tokens, this capability should be used with caution, and
should only be allowed when absolutely necessary.

4.4.6 Ring Latency Count
The Ring Latency Count (RLCT) is a measurement of time
for PDUs to propagate around the ring. This counter con·
tains the last measured ring latency whenever the Ring La·
tency Valid bit of the Token Event Register (TELR.RLVLD)
is one.
2-142

C

"tJ

4.0 fOOl MAC Facilities (Continued)

co

Co)

4.5.3 Restricted Asynchronous Service Class

Immediate requests are only serviced when the ring is nonoperational. Immediate requests may be serviced from the
Transmitter Data, Claim, and Beacon states Options are
available to force the Ring Engine to enter the Claim or
Beacon state, to prohibit it from entering the Claim state, or
to remain in the Claim state when receiving My_Claim.
On the completion of an Immediate request, a Token (Nonrestricted or Restricted) may optionally be issued. Immediate requests may also be used in non-standard applications
such as a full duplex point to point link.

The Restricted Asynchronous service class is useful for
large transfers requiring all of the available Asynchronous
bandwidth. The Restricted Token service is useful for large
transfers requiring all of the available (remaining) asynchronous bandwidth.
The Restricted Token service may also be used for operations requiring instantaneous allocation of the remaining
synchronous bandwidth when Restricted Requests are
serviced with THT disabled. This is useful when it is necessary to guarantee atomicity, i.e., that a multi-frame request
will be serviced on a single token opportunity.
A Restricted dialogue consists of three phases:
1. Initiation of a Restricted dialogue:
o Capture a Non-Restricted Token

5.0 Functional Description
5.1 TOKEN HANDLING
5.1.1 Token Timing Logic
The FDDI Ring operates based on the Timed Token Rotation protocol where all stations on the ring negotiate on the
maximum time that the stations have to wait before being
able to transmit frames. This value is termed the Negotiated
Target Token Rotation Time (nRn. The nRT value is
stored in the TNEG Register.

o Transmit zero or more frames to establish a Restricted

dialogue with other stations
o Issue a Restricted Token to allow other stations in the

dialogue to transmit frames
2. Continuation of a Restricted dialogue:
o Capture a Restricted Token

Stations negotiate for nRT based on their TREQ that is
aSSigned to them upon initialization.

o Transmit zero or more frames to continue the Restricto

Each station keeps track of the token arrival by setting the
Token Rotation Timer (TRT) to the nRT value. If the token
is not received within nRT (the token is late), the event is
recorded by setting the Late_Flag. If the token is not received within twice nRT (TRT expires and Late_Fiag is
set), there is a potential problem in the ring and the recovery
process is invoked.

ed dialogue
Issue a Restricted Token to allow other stations in the
dialogue to transmit frames

3. Termination of a Restricted dialogue:
o Capture a Restricted Token
o Transmit zero or more frames to continue the Restrict-

ed dialogue

Furthermore, the Token Holding Timer (THT) is used to limit
the amount of ring bandwidth used by a station for Asynchronous traffic once the token is captured. Asynchronous
traffic is prioritized based on the Late_Flag which denotes
a threshold at nRT and an additional Asynchronous Priority Threshold (THSH). The Asynchronous Threshold comparison (Apri 1) is pipe lined, so a threshold crossing may not
be detected immediately; however, the possible error is a
fraction of the precision of the threshold values.

o Issue a Non-restricted Token to return to the Non-re-

stricted service class
Initiation of a Restricted dialogue will prevent all Non-restricted Asynchronous traffic throughout the ring for the duration of the dialogue, but will not affect Synchronous traffic.
To ensure that the Restricted traffic is operating properly, it
is possible to monitor the use of Restricted Tokens on the
ring. When a Restricted Token is received, the event is
latched and under program control may generate an interrupt. In addition, a request to begin a Restricted dialogue
will only be honored if both the previous transmitted Token
and the current received Token were Non-restricted tokens.
This is to ensure that the upper bound on the presence of a
Restricted dialogue in the ring is limited to a single dialogue.

The Token Timing Logic consists of two Timers, TRT and
THT, in addition to the TMAX and TNEG values loaded into
these counters (See Figure 5-1).
The Timers are implemented as count-up counters that increment every 80 ns. The Timers are reset by loading TNEG
or TMAX into the counters where TNEG and TMAX are unsigned twos complement numbers. This allows a Carry flag
to denote timer expiration.
On an early token arrival (Late_Flag is not set), TRT is
loaded with TNEG and counts up. On a late token arrival
(Late_Flag is set), Late_Flag is cleared and TRT continues to count. When TRT expires and Late_Flag is not set,
Late_Flag is set and TRT is loaded with TNEG.
THT follows the value of TRT until a token is captured.
When a token is captured, TRT may be reloaded with TNEG
while THT continues to count from its previous value (THT
does not wrap around). THT increments when enabled. THT
is disabled during synchronous transmission and a special
class of asynchronous transmission. THT is used to determine if the token is usable for asynchronous requests.

As suggested by the MAC-2 Draft standard, to help ensure
that only one Restricted dialogue will be in progress at any
given time, Restricted Requests are not serviced after a
MAC frame is received until Restricted Requests are explicitly enabled by management software. Since the Claim Process results in the generation of a Non-restricted Token,
this prevents stations from initiating another restricted dialogue without the intervention of management software.
4.5.4 Immediate Service Class
The Immediate service class facilitates several non-standard applications and is useful in ring failure recovery (e.g.,
Transmission of Directed Beacons). Certain ring failures
may cause the ring to be unusable for normal traffic, until
the failure is remedied.

2-143

N
CD

....

,..

re

C')

~

C

5.0 Functional Description (Continued)
~----~
THEG

I

-"
I I
~TE
FLAG

ASYNCHRONOUS
THRESHOLD

~

"

~

I

I

TMAX

~

~ RING OPERATIONAL

TRT

+

I

THT

+

COIAPARISON LOGIC

I

I

TRT LOAD

c:

THT LOAD
THT ENABLE

/
USEABLE TOKEN

TL/F/103B7-3

FIGURE 5-1. Token Timing Logic

It TRT expires while Late_Flag is set, TRT is loaded with
TMAX and the recovery process (Claim) is invoked. When
TRT expires and the ring is not operational, TRT is loaded
with TMAX. TRT is also loaded with TMAX on a MAC Reset.

own Beacon frame. That station then enters the Claim Process, to re·initialize the ring.
5.2 SERVICING TRANSMISSION REQUESTS
A Request to transmit one or more frames is serviced by the
Ring Engine. After a Request is submitted to the Ring Engine, the Ring Engine awaits an appropriate Service Opportunity in which to service the Request. Frames associated
with the Request are transmitted during the Service Opportunity. The definition of a Service Opportunity is different
depending on the operational state of the ring.

5.1.2 Token Recovery
While the ring is operational, every station in the ring uses
the Negotiated Target Token Rotation Time, TNEG. The
MAC implements the protocol for negotiation of this target
token rotation time (TTRT) through the Claim Process. The
shortest requested Token Rotation Time is used by all of
the stations in the ring as the TNEG.

A Service Opportunity begins when the criteria presented to
the Ring Engine are met. This criteria contains the requested service class (synch, asynch, asynch priority, immediate)
and the type of token to capture (restricted, non-restricted,
any, none).

If TRT expires with Late_Flag set, a token has not been
received within twice TTRT (Target Token Rotation Time). If
TVX (Valid Transmission Timer) expires, the station has not
received a valid token within TVX Max. Both these events
require token recovery and cause the Ring Engine to enter
the Claim Process.

During a service opportunity, the Ring Engine guarantees
that a valid frame is sent with at most 40 bytes of preamble.
When data is not ready to be transmitted, Void frames are
transmitted to reset the TVX timers in all stations. During an
immediate request while in the Claim or Beacon States,
when no Claim or Beacon frames are ready to be transmitted, the internally generated Claim or Beacon frames are
transmitted.

In the Claim Process a MAC continuously transmits Claim
frames containing TREQ. Should the MAC receive a Claim
frame with a shorter TREQ (larger value-Higher_Claim) it
leaves the Claim State. A station that receives its own Claim
frame gains the right to send the first token and make the
ring operational again. If the Claim Process does not complete successfully, TRT will expire and the Beacon Process
is invoked.

5.2.1 Service Opportunity While Ring Operational
Beginning of Service Opportunity

The Beacon Process is used for fault isolation. A station
may invoke the Beacon Process through an SM_
Control.request(Beacon). When a station enters the Beacon
Process, it continuously sends out Beacon frames. The
Beacon Process is complete when a station receives its

Table 5-1 shows the conditions that must be true when a
valid token is received in order to begin a Service Opportunity when the ring is operational.

TABLE 5-1. Beginning of Service Opportunity
Requested
Service Class

Requested Token
Capture Class

Asynchronous Priority

non-restricted

THT> THSH
Late_Flag = 0
RinQ-Op = 1

non-restricted

Asynchronous

non-restricted

Late_Flag = 0
RinQ-Op = 1

non-restricted

Asynchronous

restricted

Late_Flag = 0
RinQ-Op = 1

restricted

Synchronous

any

Criteria

RinQ-Op
2·144

=1

Received
Token Class

any

.----------------------------------------------------------------------,0
"g

5.0 Functional Description

co

(Continued)
In addition to the criteria mentioned above, additional criteria apply to the servicing of Synchronous and Restricted
Requests.
• Synchronous Requests are not serviced if RELR.BCNR
is set (See Section 4.5.1).
• Restricted requests are not serviced when RELR.BCNR,
RELR.CLMR, or RELR.OTRMAC are set. (See Section
4.5.3).

Co)

transmitter Data, Claim or Beacon State, and the transmitter
is in the appropriate state.
The service opportunity continues until anyone of the following conditions exist:
1. No (additional) frames are to be sent
2. TMAX of time elapses on this request

N

en

-"

3. The transmitter exits the requested state
4. The ring becomes operational while servicing an immediate request

• Restricted Dialogues may only begin when a non-restricted token has been received and transmitted (See Section 4.5.3).

5.2.3 Frame Transmission
Frames associated with the current request may be transmitted at any time during a Service Opportunity. In many
applications, data is ready to be transmitted when the request is presented to the interface. Soon after the Service
Opportunity begins, frame transmission begins. In other applications in order to minimize the effects of ring latency it is
desirable to capture the token when no data is ready to be
transmitted. This capability results in wasted ring bandwidth
and should be used judiciously.
During transmission, a byte stream is passed from the System Interface to the MAC Request Interface. The data is
passed through the Ring Engine and appears at the PHY
Request Interface two byte times later.
While a frame is being transmitted, the request parameters
for the next request (if different) may be presented to the
interface. At the end of the current frame transmission, a
decision is made to continue or cancel the current service
opportunity based on the new request parameters.

End of Service Opportunity
The Service Opportunity continues until either a token is
issued or the ring becomes non-operational.
A token is issued after the current frame, if any, is transmitted when:
1. It is no longer necessary to hold the token
• All frames of all active requests have been transmitted
2. The token became unusable while servicing a request
• Asynchronous Priority threshold reached (If an Asynch
Priority Request is being serviced)
• THT expired (if enabled)
When the ring becomes non-operational the current frame
transmission is aborted. The ring may go non-operational
while holding a token as a result of anyone of the following
conditions:
• A MAC Reset
• Reception of a valid MAC frame
• TRT expiration, (TRT was reset when the token was captured)

During a transmission several errors can occur. A transmission may be terminated unsuccessfully because of external
buffering or interface parity errors, internal Ring Engine errors, a MAC reset, or reception of a MAC frame. When a
transmission is aborted due to an external error (and
Option.IRPT is not set), a Void frame is transmitted to reset
the TVX timers in all stations in the ring. When a frame is
aborted due to a transmission error, the Service Opportunity
is not automatically ended.

Issue Token Type
The criteria presented to the Ring Engine to begin a Service
Opportunity, also contains the Issue Token Class. The Issue
Token Class is used if servicing of that request was completed (the last frame of that request was transmitted), otherwise a token of the Capture Token Class is issued.

5.3 REQUEST SERVICE PARAMETERS

When servicing multiple requests on a single service opportunity, the Issue Token Class of the previous class becomes
the capture class for the next request for purposes of determining usability.
The type of token issued depends on the service class and
the type of token captured as shown in Table 5-2.

5.3.1 Request Service Class
The Request Service corresponds to the Request
Service Class and the token class parameters of the
(SM-lMA-DATA.request and (SM_)MA-Token.request
primitives as specified in the Standard.
14 useful combinations of the Requested Service Class
(Non-Restricted Asynchronous, Restricted Asynchronous,
Synchronous, Immediate), the Token Capture and Issue
Class, and THT Enable are supported by the Ring Engine as
shown in Table 5-3.

5.2.2 Service Opportunity while
Ring Not Operational
While the ring is not operational, a service opportunity occurs if an immediate transmission is requested from the

TABLE 5-2. Token Transmission Type
Service Class

Token Captured

Token Issued

Non-Restricted

Non-Restricted

Non-Restricted

Begin Restricted

Non-Restricted

Restricted

Continue Restricted

Restricted

Restricted

End Restricted

Restricted

Non-Restricted

Immediate

None

None

Immediate Non-Restricted

None

Non-Restricted

Immediate Restricted

None

Restricted

2-145

Ell

5.0 Functional Description (Continued)
TABLE 5-3. Request Service Classes
RQRCLS

Name

0000

None

None

0001

Apri_1

Async
THSH1

0010

Reserved

Reserved

0011

Reserved

Reserved

0100

Syn

Synch

0101

Imm

Immediate

THT

Token
Capture

Token
Issue

Enabled

Non-rstr

Non-rstr

Disabled

Any

Captured

1

Disabled

None

None

4

Class

Notes

0110

ImmN

Immediate

Disabled

None

Non-rstr

4

0111

ImmR

Immediate

Disabled

None

Rstr

4

Non-rstr

1000

Asyn

Asynch

Enabled

Non-rstr

1001

Rbeg

Restricted

Enabled

Non-rstr

Rstr

2,3

1010

Rend

Restricted

Enabled

Rstr

Non-rstr

2

1011

Rcnt

Restricted

Enabled

Rstr

Rstr

2

Non-rstr

1100

AsynD

Asynch

Disabled

Non-rstr

1101

RbeginD

Restricted

Disabled

Non-rstr

Rstr

2,3

1110

RenD

Restricted

Disabled

Rstr

Non-rstr

2

1111

RcntD

Restricted

Disabled

Rstr

Rstr

2

Note 1: Synchronous Requests are not serviced when bit BCNR of the Ring Event Latch Register is set.
Note 2: Restricted Requests are not serviced when bit BCNR, CLMR, or OTRMAC of the Ring Event Latch Register is set.
Note 3: Restricted Dialogues only begin when a Non-Restricted token has been received and transmitted.
Note 4: Immediate Requests are serviced when the ring is Non-Operational. These requests are serviced Irom the Data state H ne~her signal ROCLM nor ROBCN
is asserted. If signal ROCLM is asserted, Immediate Requests are serviced lrom the Claim State. II signal ROBCN is asserted, Immediate Requests are serviced
from the Beacon State. ROCLM and ROBCN do not cause transitions to the Claim and Beacon States.

Requests are serviced on a Service Opportunity meeting
the requested criteria.
External support is required to limit the requests presented
to the MAC Interface by different MAC Users (SMT, LLC,
etc.).
A Token Capture Class of non-rstr indicates that the Transmitter Token Class must be Non-Restricted to begin servicing the request. A Token Capture Class of rstr indicates
that the Transmitter Token Class must be Restricted to begin servicing the Request. A Token Issue Class of non-rstr
means that the Transmitter Token Class will be Non-Restricted upon completion of the request. A Token Issue
Class of rstr means that the Transmitter Token Class will be
Restricted upon completion of the request.

Source Address Transparency
Normally the SA field in a frame is generated by the BMAC
device, using either the MSA or MLA. When the SA Transparency option is selected, the SA from the data stream is
transmitted in place of the MSA or MLA. The SAT option
can be invoked on 'a per frame basis upon the assertion of
the SAT signal (Pin 12).

,

When the SA Transparency option is selected, it is necessary to rely on an alternate stripping mechanism because
stripping based on the returning SA only guarantees that
frames with MSA or MLA will be stripped. Either the Void
Stripping option (described below) may be invoked, or external hardware that forces stripping using the EM (External
M_Flag) Signal is required.
The MSB of the SA is not controlled by this option. It is
normally forced to Zero. It can be controlled using the
Source Address MSB Transparency option described below.
SA Transparency is possible for all frames (including MAC
frames). External support is required to limit the use of SA
Transparency to certain MAC Users. SA Transparency
should not be used with externally generated MAC Frames
in order to maintain accountability, but this is not enforced
by the Ring Engine.

5.3.2 Request Options
The Request Options provide the ability for Source Address
Transparency (SAT) and FCS Transparency (FCSn. In both
cases, data from the request stream is transmitted in place
of data from either the Ring Engine. The use of Source Ad·
dress transparency has no effect on the sequencing of the
interface. When Source Address transparency is not used,
the SA from the internal parameter RAM is substituted for
the SA bytes in the request stream, which must still be present. Since the FCS is appended to the frame, when FCS
transparency is not used, no FCS bytes are present in the
request stream.

2-146

5.0 Functional Description (Continued)
SA Transparency also overrides the Long and Short Addressing enables. For example, if Long Addressing is not
enabled, it is still possible to transmit frames with Long Addresses. Similarly, if Short Addressing is not enabled, it is
still possible to transmit Frames with Short Addresses. This
may be useful in full duplex point to point applications and
for diagnostic purposes.

Void Stripping is also automatically invoked by this station if
it wins the Claim Process before the initial token is issued.
This removes all fragments and ownerless frames from the
ring when the ring becomes operational.
FCS Transparency
Normally, the BMAC device generates and transmits the
FCS. When the Frame Check Sequence Transparency option is selected, the Ring Engine device does not append
the FCS to the end of the Information field. This option is
selected by asserting signal FCST (Pin 14).
The receiving stations treat the last four bytes of the data
stream as the FCS.
This option may be useful for end to end FCS coverage
when crossing FOOl bridges, for diagnostic purposes, or in
Implementer frames.

Source Address Most Significant Bit Transparency
With the Source Address MSB Transparency option, the
MSB of the SA is sourced from the data stream, as opposed
to being transmitted as Zero. The SA MSB Transparency
option is selected by asserting signal SAIGT (Pin 11).
Unless the Source Address Transparency option is also selected, the rest of the SA is generated by the Ring Engine.
The MSB of the SA is used to denote the presence of the
Routing Information Field used in Source Routing algorithms (as in the IEEE 802.5 protocol). This option is useful
for stations that utilize Source Routing. In these applications, the SA can still be generated by the Ring Engine,
even when routing information is inserted into the data
stream.

5.4 FRAME VALIDITY PROCESSING
A valid frame is a frame that meets the minimum length
criteria and contains an integral number of data symbol
pairs between the Starting and Ending Delimiters as shown
in Table 5-4.
On the Transmit side, frames are checked to see that they
are of a minimum length. If the end of a frame is reached
before a valid length is transmitted, the frame will be aborted and a Void frame will be transmitted (as with all aborted
frames). A MAC frame with a zero length INFO field will not
be aborted even though the Receiver will not recognize it as
a valid frame. Frame lengths are not checked for the maximum allowable length (4500 bytes).

Void Stripping
This option is useful for removing bridged and ownerless
frames and remnants (fragments) from the ring.
In the Void Stripping protocol, two My_Void frames are
transmitted at the end of a service opportunity. Stripping
continues until one of the following conditions occur:
• One My_Void frames returns (The Second My_Void
will be stripped on the basis of the SA)

Also on the Transmit side, the L bit in the FC field is
checked against the ESA and ELA bits in the Option Register (if the SA Transparency option is not selected) to insure
that a frame of that address length can be transmitted. If the
selected address length is not enabled, the frame is aborted
at the beginning of the SA field. If SA Transparency is selected, the frame is not aborted.

• A Token is received
• An Other_Void is received
• A MAC frame other than My_Claim is received
• A MAC Reset occurs
If any frame of a Service Opportunity requests this option,
then all frames on that service opportunity will be stripped
using this method. Void Stripping is invoked upon the assertion of the STRIP signal (Pin 13) at the beginning of a frame
transmission.

TABLE 5-4. Valid Frame Length
Frame Types

Short Address

Long Address

Notes

(Minimum Number of Bytes)

Void

9

17

MAC

13

21

Ineluding a 4 Byte
INFO Field

Non-MAC

9

17

Including a 0 Byte
INFO Field

2-147

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5.0 Functional Description

(Continued)
The received value of the Control Indicators for every frame
received is reported at the MAC Indicate Interface on signals MID(7-0). On a frame transmitted by this station, the
returning Control Indicators give the transmission status.

5.5 FRAME STATUS PROCESSING

Each frame contains three or more Control Indicators. The
FDDI Standard specifies three: the E, A, and C Indicators.
When a frame is transmitted, the Control Indicators are
transmitted as R (Reset) symbols. If an error is detected by
a station that receives the frame, the E Indicator is changed
to an S (Set) symbol. If a station recognizes the DA of a
frame as its own address (Individual, Group or Broadcast),
the A Indicator is changed to an S symbol. If that station
then copies the frame, the C Indicator is changed to an S
symbol.

The Ending Delimiter followed by the Frame Status Indicators should begin and end on byte boundaries. Control Indicators are repeated until the first non R, S, or T is received.
The processing of properly aligned E, A, and C indicators by
the Ring Engine is detailed in Table 5-5. Given the shown
received Control Indicator values and the settings of the
internal flags, the noted control indicator values will be
transmitted.

TABLE 5-5. Control Indicators Processing
Flags

Received Indicators

Transmitted Indicators

E

A

C

E

A

Copy

N

E

A

R

R

R

0

0

X

X

R

R

S

R

R

R

0

1

0

X

R

S

R

R

R

R

0

1

1

X

R

S

S

X

R

R

1

X

X

X

S

R

R
S

C

R

R

S

0

0

X

X

R

R

R

R

S

0

1

a

X

R

S

R

R

R

S

0

1

1

X

R

S

S

X

R

S

1

X

X

X

S

R

S

R

S

R

0

X

X

1

R

S

R

R

S

R

0

X

0

0

R

S

R

R

S

R

0

1

1

0

R

S

S

R

S

R

0

0

X

X

R

S

R

R

S

S

0

X

X

X

R

S

S

X

S

S

1

X

X

X

S

S

S

R

R

T

0

0

X

X

R

R

T

R

R

T

0

1

a

X

R

S

R
S

R

R

T

0

1

1

X

R

S

X

R

T

1

X

X

X

S

R

T

R

S

T

0

1

1

0

R

S

S

R

S

T

0

0

X

X

R

S

T

R

S

T

0

1

0

X

R

S

R

R

S

T

0

1

1

1

R

S

R

S

T

1

X

X

X

S

S

T

X

E_Flag is set when the local FCS check fails or when the E Indicator is received as anything other than R.
A-Flag is the internal _Flag or the external A Flag (pin EA) when Option.Emind is set.
The Copy Flag is a one cycle delayed version of the VCOPY input.

N_Flag indicates that an NSA frame is being received. This signal is sampled at the same time that the received A indicator is being investigated.

X Represents a Don't Care Condition,

2-148

5.0 Functional Description

(Continued)

5.5.1 Odd Symbols Handling

A Higher_Claim frame is a Claim frame with a Source Ad·
dress that does not match this station address and the
T_Bid_Rc in the INFO field is greater than this station's
TREQ.

When the first T symbol of a frame is received as the second symbol of a symbol pair (the T symbol is received offboundary), the Ring Engine corrects this condition by send·
ing out the symbol sequence TSII. This symbol sequence
indicates the end of the frame and that an error has been
detected in the frame. Note that this is a low probability
error event.

A lower_Claim frame is a Claim frame with a Source Address that does not match this station address and the
T_Bid_Rc in the INFO field is less than this station's
TREQ.

Reception of symbols other than R, S, and T during the
Frame Status processing is also a low probability event.
This event is handled slightly differently on the first byte of
the Ending Frame Status.

Transmit
Claim frames are transmitted continuously while in the
Claim State.
Claim frames are generated by the Ring Engine, unless an
Immediate Claim Request is present at the MAC Request
Interface. Even if an Immediate Claim Request is present at
the MAC Request Interface, at least one Claim frame must
be generated by the Ring Engine before Claim frames from
the Interface are transmitted.

On the first byte of the Ending Frame Status, if the symbol
following the T symbol is not [R or Sl, the symbol sequence
TSII is transmitted and the error and frame counts are incre·
mented.
After the first byte of the Ending Frame Status, if either the
first symbol is not [R or S1 or the second symbol is not [R or
S or Tl, an Idle symbol pair (II) is transmitted.

For internally generated Claim frames, the Information field
is transmitted as the 4·byte Requested Target Token Rota·
tion Time.

5.6 SMT FRAME PROCESSING
All SMT frames are handled as all other frames with the
exception of the SMT Next Station Addressing (SMT NSA)
frame. NSA frames are used to announce this station's ad·
dress to the next addressed station. The current SMT protocol requires stations to periodically (at least once every 30
seconds) transmit an NSA frame. Since the Broadcast ad·
dress is used, and every station is required to recognize the
broadcast address, the downstream neighbor will set the A
Indicator. A station can determine its upstream neighbor by
finding NSA frames received with the A Indicator received
as R. By collecting this information from all stations, a map
of the logical ring can be built.

The Information field of a Claim frame consists of the station's Requested Target Token Rotation Time. In the Ring
Engine implementation, TREQ is programmable with
20.48
resolution and a maximum value of 1.34 seconds.

"'S

Claim Protocol
Entry to the Claim state occurs whenever token recovery is
required. The Recovery Required condition occurs when:
• TRT expires and late_Flag is set
o TVX expires

• A lower Claim frame or My_Beacon frame is received
Entry to the Claim state may be blocked by enabling the
Inhibit Recovery Required option (bit Option.ITR).

Additionally, only the station that sets the A Indicator is permitted to set the C Indicator on such frames. In this way, the
station that sends out the NSA frame can determine if the
next addressed station copied the frame by examining the
returning C Indicator.

The Claim state is entered (even if Option.IRR = 1) with a
SM_MLControl.request (Claim) (Set Function.ClM to 1).
While in the Claim state:
• Claim frames are transmitted continuously

5.7 MAC FRAME PROCESSING

• If a Higher Claim frame is received, the station exits the
Claim state and enters the IDLE state. In this state it then
repeats additional Higher Claim frames.

Upon the reception of a valid MAC frame (Claim, Beacon, or
Other), the Ring_Operational flag is reset and the Ring Engine enters the Idle, Claim or Beacon State. Received Claim
and Beacon frames are processed as defined in the Standard (See Appendix A), unless inhibited by the bits in the
Option Register.

• If a lower Claim frame is received, this station continues
to send its own Claim frames and remains in the Claim
state.
Eventually, if a logical ring exists, the station with the shortest TREQ on the ring should receive its own Claim frames,
the My Claim frame. This completes the Claim Token Pro·
cess. This one station then earns the right to issue a token
to establish an Operational ring.

5.7.1 Claim Token Process
Receive
When a Claim frame is received, its Frame Type is reported
(Claim frame) along with the type of Claim frame.
There are three types of Claim frames:
Higher_Claim, and lower_Claim.

An option is provided to remain in the Claim state if this
station won the Claim Token Process by enabling the Inhibit
Token Release Option (bit Option.ITR).

My_Claim,

A My_Claim frame is a Claim frame with a Source Address
that matches this station address and the T_Bid_Rc in the
INFO field is equal to this station's TREQ.

2-149

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r----------------------------------------------------------------------------------------------,
5.0 Functional Description (Continued)
5.7.2 Beacon Process

5.8 RECEIVE BATCHING SUPPORT
The Ring Engine stores each received SA and compares
the incoming SA with the previous SA. This may be used to
batch status on frames received from the same station.
The SameSA signal is asserted when:
1. The curent and previous non-Void frames were not MAC
frames

Receive
When a Beacon frame is received, its Frame Type is reported (Beacon frame) along with the type of Beacon frame.
There are two types of Beacon frames: My_Beacon and
Other_Beacon.
A Beacon frame is considered a My_Beacon if its Source
Address matches this station's address (long or short).
A Beacon frame is marked as Other_Beacon if its Source
Address does not match this station's address.

2. The size of the address of the current frame is the same
as the size of the address of the previous non-Void frame
3. The SA of the current frame is the same as the SA of the
previous non-Void frame.
On MAC frames, the Information fields are compared. This
information may be useful to inhibit copying MAC frames
with identical information. This is particularly useful for copying Claim and Beacon frames when new information is pres·
ent.
The Same INFO signal is asserted when:
1. The current and previous non-Void frames were both
MAC frames (not necessarily the same FC value).
2. The first four bytes of the INFO field of the current frame
is the same as the first four bytes of the INFO field of the
previous non·Void frame.
The size of the addre,ss of MAC frames is not checked.

Transmit
Beacon frames are transmitted continuously while in the
Beacon state.
Beacon frames are generated by the Ring Engine, unless an
Immediate Beacon Request is present at the MAC Request
Interface. Even if an Immediate Beacon Request is present
at the MAC Request Interface, at least one Beacon frame
must be generated by the Ring Engine before Beacon
frames from the Interface are transmitted.
For internally generated Beacon frames, the Ring Engine
uses the TBT in the Information field.
Beacon Protocol
Entry to the Beacon state occurs under two conditions:

5.9 IMMEDIATE FRAME TRANSMISSION
Immediate requests are used when it is desirable to send
frames without first capturing a token. Immediate requests
are typically used as part of management processes for error isolation and recovery. Immediate requests are also use·
ful in full duplex applications. Immediate requests are serviced only when the station's Ring_Operational flag is not
set (CTSR.ROP = 0).

• A failed Claim Process (TRT expires during the Claim
process)
• An SM_M~Control.request (Beacon)
(Set Function.BCN to 1).
Beacon frames are then transmitted until the Beacon process is completed.
If an Other_Beacon frame is received, this station exits the
Beacon state, stops sending its own Beacon frames, and
repeats the incoming Beacon frames.,

To transmit an Immediate request, the request must first be
queued at the M~Request Interface. If the Ring is not
operational (RinQ-Operational flag is not set), the request
will be serviced immediately. If the Ring is operational
(Ring_Operational flag is set), the request will be serviced
when the Ring becomes non·operational. The Ring becomes non-operational as a result of a MAC Reset
(Function.MCRST is set to One) or any of the conditions
causing the Reset or Recovery Actions are performed.

If a My_Beacon frame is received, the station has received
back its own Beacon frame; thus successfully completing
the Beacon process. The station then enters the Claim Process.
5.7.3 Handling Reserved MAC Frames
A Reserved MAC frame is any MAC frame aside from the
Claim and Beacon frame. Tokens are not considered MAC
frames even though Format bit (FC.FF) are the same as for
MAC frames.
When a Reserved MAC frame (Other_MAC) is received, it
is treated as a Higher Claim. If the Transmitter is in the
Claim state when a Reserved MAC frame is received, the
Transmitter returns to the Idle state and then repeats the
next Reserved MAC frame received. If the Transmitter is in
the Beacon state and a Reserved MAC frame is received,
the Transmitter continues to transmit Beacon frames. If the
Transmitter is in the Idle state, the Reserved MAC frame is
repeated.

In addition to servicing an Immediate request from the
Tx-Data State, it is also possible to service Immediate requests from the Claim or Beacon State. When transmitting
from the Claim or Beacon state, in addition to requesting an
Immediate Transmission Service Class, the RQCLM or
RQBCN signals (pins 15 and 16) must be asserted to indio
cate an Immediate Claim or Immediate Beacon request.
These requests will only be serviced when in the Claim or
Beacon state. Entry to the Beacon State can be forced

2-150

5.0 Functional Description

(Continued)
When parity is not used on an Interface, the parity provided
by the BMAC device for its outputs may be ignored. For the
BMAC device's inputs, the result of the parity check is used
only if parity on that Interface is enabled.

by setting bit Function.BCN to One. Entry to the Claim State
can be forced by setting bit Function.ClM to One.
While in the Claim or Beacon state, the Ring Engine will
transmit internally generated Claim or Beacon frames except when an Immediate Claim or Beacon request is present at the MA-Request Interface, signal RQClM or
ROBCN is asserted, and a frame is ready to be transmitted.
At least one internally generated Claim or Beacon frame
must be transmitted before an Immediate Claim or Beacon
request is serviced. It is possible for the internally generated
frame to return before the end of the requested frame has
been transmitted. To allow time for the requested frame(s)
to be transmitted before leaving the Claim or Beacon state,
bit ITR (for Claim) or bit IRR (for Beacon) of the Option
Register should be set to One.

Interface parity is enabled by setting the appropriate bit in
the Mode register: Mode.CBP for Control Bus Parity,
Mode.PIP for PHY Indication parity and Mode.MRP for MAC
Request Parity. A Master Reset (Function. MARST) disables
parity on all interfaces.
On the PHY Request interface, parity is generated for internally sourced fields (such as the SA or FCS on frames when
not using SA or FCS transparency, and internally generated
Beacon, Claim and Void frames). In REV 1 of the BMAC
device, MRP is passed transparently to PRP for externally
sourced fields independent of the value of the Mode.MRP.
In all later revisions, correct Odd parity is always generated
for PRP. This allows through parity support at the PHY interface even if parity is not used at the MAC interface. This is
very desirable since every byte of data that traverses the
ring travels across the PHY Interface which is actually part
of the ring.

While an Immediate request is being serviced (from any
state), if bit IRPT of the Option Register is set to One (Inhibit
Repeat option), all received frames (except lower_Claim
and My_Beacon frames) are ignored and the Immediate
request continues. lower_Claim and My_Beacon frames
can also be ignored by setting bit IRR of the Option Register.

Through parity is not supported in the Control Interface Registers and the Parameter RAM. Parity is generated and
stripped at the Control Interface.

5.10 FUll DUPLEX OPERATION
The BMAC device supports full duplex operation by
1. Suspending the Token Management and Token Recovery protocols (set Option.IRR)

Handling Parity Errors
Parity errors are reported in the Exception Status Register
when parity on that interface is enabled.
A parity error at the PHY interface (when Mode.PIP is set) is
treated as a code violation and ESR.PPE is set. If the parity
error occurs in the middle of a POU (token or frame) reception, the POU is stripped, a Format Error is Signaled
(Fa ERROR) and the lost Count is incremented.

2. Inhibiting the repetition of all PO Us (set Option.IRpn
3. Using the Immediate Service Class
Frames of any size may be transmitted or received, subject
to the minimum length specified in Section 5.4.
5.11 PARITY PROCESSING
The BMAC device contains five data interfaces as shown in
Table 5-6.

A parity error at the MAC Interface (when Mode.MRP is set)
during a frame transmission from the MAC interface (while
TXACK is asserted) causes the frame transmission to be
aborted. When a frame is aborted, a Void frame is transmitted to reset every station's TVX timer. A parity error (when
enabled) causes ESR.MPE to be set.

Through Parity is supported on the internal data paths between any Request interface and any Indicate interface.
Odd Parity is provided every clock on all data outputs and is
checked every clock on all data inputs. Parity errors are not
propagated through the BMAC device (from the MAC Request and PHY Indication interface to the PHY Request interface or from the PHY Indication interface to the MAC
Indication interface). Parity errors are isolated and resolved.

A parity error at the Control Interface (when Mode.CBP is
set) will cancel the current write access. ESR.CPE is set to
indicate that a parity error occurred and ESR.CCE is set to
indicate that the write was not performed.

TABLE 5-6. BMAC Device Parity
Parity
On

Parity

MAC Request Interface

MRD(7:0)

MRP

I

MAC Indication Interface

MID(7:0)

MIP

a

PHY Request Interface

PRD(7:0),
PRC

PRP

a

PHY Indication Interface

PID(7:0),
PIC

PIP

I

Control Interface

CBD(7:0)

CBP

1/0

Interface

2-151

Direction

til

.,...
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6.0 Control Information
6.2 ACCESS RULES

The Control Information includes Operation, Event, Status
and Parameter Registers that are used to manage and operate the Ring Engine. A processor on the external Control
Bus gains access to read and write these parameters via
the Control Interface.
The Control Information Address Space is divided into 4
groups as shown in Table 6-1. An information summary is
given for each group (see Tables 6-2 through 6-5) followed
by a detailed description of all registers.

All parameters are accessible in Diagnose Mode. Reserved
address space is not accessible in any mode. Certain Status
and Parameter Registers are not accessible while in Run
mode.
All Control Interface accesses are checked against the current operational mode to determine if the register is currentIy accessible. If not currently accessible, the Control Bus
Interface access is rejected (and reported in an Event Register). This means that all Control Bus Interface accesses
complete in a deterministic amount of time.

6.1 CONVENTIONS
When referring to multi-byte fields, by1e 0 is always the most
significant by1e. When referring to bits within a byte, bit (7) is
the most significant bit and bit (0) is the least significant bit.

The Exceptional Status Register can be checked to verify
that the operation terminated normally.

When referring to the contents of a byte, the most signficant
bit is always referred to first.
When referring to a bit within a byte the notation
register_name.biLname is used. For example, Mode.RUN
references the RUN bit in the Mode Register.
TABLE 6-1. Control Information Address Space
Write Conditions

Address Range

Description

Read Conditions

00-07

Operation Registers

Always (Note 2)

Always (Note 2)

08-2F

Event Registers

Always (Note 2)

Always (Cond) (Note 2)

30-3F

Reserved

N/A

N/A

40-7F

MAC Parameters

Stop Mode
(Notes 1,3)

Stop Mode
(Notes 1, 3)

80-BF

Counters/Timers

Always

Stop Mode
(Note 1)

CO-FF

Reserved

N/A

N/A

Note 1: An attempt to access a currently inaccessible location because of the current mode or because it is in a reserved address space will cause a command
error (bit CCE of the Exception Status Register is set to One).
Note 2: Read and write accesses to reserved location within the Operation and Event Address ranges cause a command error (bit CeE of the Exception Status
Register is set to One).
Note 3: The MAC Parameter RAM is also accessible when conditions a, b, and c are true. Otherwise accesses will cause a command error (ESR.GEE set to One)
and the access will not be performed.
a. The MAC Transmitter is in states TO, T1 or T3;
b. Bits ITC and IRR of the Option Register are set to One.
c. Bits ClM and BCN of the Function Register are not set to One.
Note 4: Reserved bits in registers are always read as 0 and are not writable.

TABLE 6-2. Operation Registers
Addr

Name

07

06

05

04

03

02

01

DO

Read

Write

0

Mode

DIAG

IlB

RES

RES

PIP

MRP

CBP

RUN

Always

Always

1

Option

ITC

EMIND

IFCS

IRPT

IRR

ITR

ELA

ESA

Always

Always
Always

2

Function

RES

RES

RES

ClM

BCN

MCRST

RES

MARST

Always

3-6

Reserved

RES

RES

RES

RES

RES

RES

RES

RES

N/A

N/A

7

Revision

Always

Always

REV(7-0)

Note: Attempts to access reserved locations will result in Command Rejects (ESR.CCE set to ONE).

2-152

C

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6.0 Control Information (Continued)

CO
Co)

N

Addr
9-8
C
D
E
F
10

Name
CMP
Reserved
CRSO
Reserved
CTSO
Reserved
RELRO

11

REMRO

12
13
14
15
16-17
18

RElR1
REMR1
TElRO
TEMRO
Reserved
CllR

19

CIMR

8

1A-1B Reserved
1C
COLR
1D

COMR

1E-27

Reserved

28

IElR

29-2B
2C
2D
2E
2F

Reserved
ESR
EMR
ICR
IMR

TABLE 6-3. Event Registers
04
03
02
01
DO
Read
Write
Always Always
CMP(7-0)
N/A
N/A
RES
RES
RES
RES
RES
RES
RES
RES
RFLG
RS1
RSO
RTS2
RTS1
RTSO
Always Ignore
RS2
RES
N/A
N/A
RES
RES
RES
RES
RES
RES
RES
RES
ROP
TS2
TS1
TSO
TTS3
TTS2
TTS1
TTSO
Always Ignore
N/A
N/A
RES
RES
RES
RES
RES
RES
RES
RES
DUP
Always Condition
RES
PINV
OTR
CLMR
8CNR
RNOP
ROP
ADD
MAC
DUP
OTR
RES
PINV
8CNR
ROP
Always Always
CLMR
RNOP
ADD
MAC
LOClM HIClM MYClM
RES
RES
RES
MYBCN OTRBCN Always Condition
LOCLM HICLM MYCLM
RES
RES
RES
MYBCN OTRBCN Always Always
RlVD TKPASS TKCAPT CBERR DUPTKR TRTEXP TVXEXP ENTRMD Always Condition
RlVD TKPASS TKCAPT CBERR DUPTKR TRTEXP TVXEXP ENTRMD Always Always
N/A
N/A
RES
RES
RES
RES
RES
RES
RES
RES
RES
TK
FR
FR
FR
FR
FREI
FR
Always Condition
RCVD
TRX
NCOP
COP
lST
RCV
Always Always
RES
TK
FR
FR
FR
FR
FREI
FR
RCVD
TRX
NCOP
COP
LST
RCV
N/A
N/A
RES
RES
RES
RES
RES
RES
RES
RES
Always Condition
RES
TK
FR
FR
FR
FR
FREI
FR
RCVD
TRX
NCOP
COP
lST
RCV
RES
TK
FR
FR
FR
FR
FREI
FR
Always Always
RCVD
RCV
TRX
NCOP
COP
LST
RES
RES
RES
RES
N/A
N/A
RES
RES
RES
RES
TSM
RSM
RES
RES
RES
RES
MPE
Always Condition
RES
ERR
ERR
N/A
N/A
RES
RES
RES
RES
RES
RES
RES
RES
CWI
CCE
CPE
RES
RES
RES
RES
PPE
Always Condition
ZERO
CCE
CPE
RES
RES
RES
RES
PPE
Always Always
ESE
IERR
RES
RES
COE
CIE
TIE
RNG
Always Ignore
ESE
IER
RES
RES
COE
CIE
TIE
RNG
Always Always
07

06

05

Note 1: Attempts to access reserved locations will result In Command Rejects (ESR.CCE set to ONE).
Note 2: Bits in the conditional write registers are only written when the corresponding bit in the Compare Register is equal to the bit to be overwritten and the bit is
not changing in that cycle.

2-153

....
en

~ r---------------------------------------------------------------~--------------__,

~
C")
co
a.

6.0 Control Information (Continued)
TABLE 6-4. MAC Parameter RAM (Continued)

TABLE 6-4. MAC Parameter RAM

C

Register
Contents

Address

Name

Register
Contents

40

MLAO

MLA(47-40)

60

PGM10

PGM(87-80)

41

MLA1

MLA(39-32)

61

PGMll

PGM(8F-88)

42

MLA2

MLA(31-24)

62

PGM12

PGM(97-90)

43

MLA3

MLA(23-16)

63

PGM13

PGM(9F-98)

44

MLA4

MLA(15-8)

64

PGM14

PGM(A7-AO)
PGM(AF-A8)

Address

Name

45

MLA5

MLA(7-0)

65

PGM15

46

MSAO

MSA(15-8)

66

PGM16

PGM(B7-BO)

47

MSAl

MSA(7-0)

67

PGM17

PGM(BF-B8)

48

GLAO

GLA(47-40)

68

PGM18

PGM(C7-CO)

49

GLAl

GLA(39-32)

69

PGM19

PGM(CF-G8)

4A

GLA2

GLA(31-24)

6A

PGM1A

PGM(D7-DO)

4B

GLA3

GLA(23-16)

6B

PGM1B

PGM(DF-D8)

4C

GLA4

GLA(15-8)

6C

PGM1C

PGM(E7-EO)

4D

Reserved

6D

PGM1D

PGM(EF-E8)

6E

PGM1E

PGM(F7-FO)

6F

PGM1F

PGM(FF-F8)

70

PGMO

PGM(7-0)

4E

GSAO

4F

Reserved

50

TREQO

TREQ(31-24)

GSA(15-8)

51

TREQl

TREQ(23-16)

71

PGMl

PGM(F-8)

52

TREQ2

TREQ(15-8)

72

PGM2

PGM(17-10)

53

TREQ3

TREQ(7-0)

73

PGM3

PGM(lF-18)

54

TBTO

TBT(31-24)

74

PGM4

PGM(27-20)
PGM(2F-28)

55

TBTl

TBT(23-16)

75

PGM5

56

TBT2

TBT(15-8)

76

PGM6

PGM(37-30)

57

TBT3

TBT(7-0)

77

PGM7

PGM(3F-38)

58

FGMO

FGM(7-0)

78

PGM8

PGM(47-40)

59

FGMl

FGM(F-8)

79

PGM9

PGM(4F-48)

5A-5F

RES

Reserved

7A

PGMA

PGM(57-50)

7B

PGMB

PGM(5F-58)

Note: The MAC Parameler RAM is accessible in Stop mode and In RUN
mode while Ihe MAC Transmitter is in Ihe stales TO, T1 or T3; Option.ITC and
Oplion.lRR are sel; and Function.BCN and Funclion.ClM are not set. Other·
wise a command reiect Is given (ESA.CCE) and the Parameter RAM will not
be read or written.

2-154

7C

PGMC

PGM(67-60)

7D

PGMD

PGM(6F-68)

7E

PGME

PGM(77-70)

7F

PGMF

PGM(7F-78)

r-------------------------------------------------------------------------~

6.0 Control Information

0:1

(0)

TABLE 6-5. MAC Counters and Timer Thresholds
(Continued)

TABLE 6-5. MAC Counters and Timer Thresholds
Address

Name

80-86

Reserved

87

THSH1

88-92

Reserved

93

TMAX

Register
Contents

Null(7-4),
THSH1(3-0)

Null(7-4),
TMAX(3-0)

Address

Name

Register
Contents

BO

FNCTO

Zero(31-24)

B1

FNCT1

Null(7-4),
FNCT(19-16)

B2

FNCT2

FNCT(15-8)

B3

FNCT3

FNCT(7-0)

B4

FTCTO

Zero(31-24)

94-96

Reserved

B5

FTCT1

97

TVX

Null(7-4),
TVX(3-0)

Null(7-4),
FTCT(19-16)

B6

FTCT2

FTCT(15-8)

98

TNEGO

TNEG(31-24)

B7

FTCT3

FTCT(7-0)

99

TNEG1

TNEG(23-16)

B8

TKCTO

Zero(31-24)

9A

TNEG2

TNEG(15-8)

B9

TKCT1

9B

TNEG3

TNEG(7-0)

Null(7-4),
TKCT(19-16)

9C-9E

Reserved

TKCT(15-8)

9F

LTCT

Null(7-4),
LTCT(3-0)

AO

FRCTO

Zero(31-24)

A1

FRCT1

Null(7-4),
FRCT(19-16)

A2

FRCT2

C
."

(Continued)

FRCT(15-8)

BA

TKCT2

BB

TKCT3

TKCT(7-0)

BC

RLCTO

Zero(31-24)

BD

RLCT1

Null(7-4),
RLCT(19-16)

BE

RLCT2

RLCT(15-8)

BF

RLCT3

RLCT(7-0)

A3

FRCT3

FRCT(7-0)

Note: The MAC event counters and timer thresholds are always readable,
and are writable in Stop mode.

A4

EICTO

Zero(31-24)

Note: Null(7-4) indicates that these bits are forced to zero on reads, and are
ignored on writes.

A5

EICT1

Null(7-4),
EICT(19-16)

A6

EICT2

EICT(15-8)

A7

EICT3

EICT(7-0)

A8

LFCTO

Zero(31-24)

A9

LFCTO

Null(7-4),
LFCT(19-16)

AA

LFCT1

LFCT(15-8)

AB

LFCT2

LFCT(7-0)

AC

FCCTO

Zero(31-24)

AD

FCCT1

Null(7-4),
FCCT(19-16)

AE

FCCT2

FCCT(15-8)

AF

FCCT3

FCCT(7-0)

Note: The value obtained on reads from reserved locations is not specified.

The Event Counters are 20·bit counters and are read
through three control accesses. In order to guarantee a
consistent snapshot, whenever byte 3 of an event counter is
read, byte 1 and byte 2 of the counters are loaded into a
holding register. Byte 1 and byte 2 may then be read from
the holding register. A single holding register is shared by all
of the counters but (for convenience) is accessible at several places within the address space. Consistent readings
across counters can be accomplished using the Counter
Increment Latch Register (CILR).
The Event Counters are not reset as a result of a Master
Reset. This may be done by either reading the counters out
and keeping track relative to the initial value read, or by
writing a value to all of the counters in stop mode. The
counters may be written in any order. With some exceptions, interrupts are available when the counters increment
or wraparound.
6_3 OPERATION REGISTERS
The Operation Registers are used to control the operation
of the BMAC device. The Operation Registers include the
following registers.
• Mode Register (Mode)
• Option Register (Option)
• Function Register (Function)
• Revision Register (REV)

2-155

N

a>
-'"

6.0 Control Information (Continued)
Mode Register (Mode)
The Mode Register (Mode) contains the current mode of the BMAC device.
ACCESS RULES
Address

I

Read

I

OOh

Write

I

Always

I

Always

REGISTER BITS
07

I

DIAG

Bit

06

I

ILB

05

I

RES

04

I

RES

03

I

PIP

02

I

MRP

01

I

CBP

Symbol

DO

I

RUN

I

Description

DO

RUN

RUN/Stop:
0: Stop Mode
All state machines return to and remain in their zero state. All counters and timers are disabled. The Ring
Engine transmits Idle symbols.
1: Run Mode. Must'be in Run Mode to achieve an operational Ring.

D1

CBP

Control Bus Parity: Enables Odd Parity checking on the Control Bus Data pins (CBD7 -0) during write
accesses.
If a parity error occurs, the CPE bit of the Exception Status Register is set to One and an 'interrupt is
generated. The write data will not be deposited in the register. Parity is always generated on CBD7 -0 during
read accesses

D2

MRP

MAC Request Parity: Enables Odd Parity checking on the MAC Request Data pins (MRD7 -0). A parity
error causes the transmission to be aborted. In REV 1 of the BMAC device MIP is always passed
transparently from PIP. In all later revisions correct Odd parity is always generated on MIP.

D3

PIP

PHY Indicate Parity: Enables Odd Parity checking on the PHY Indicate Data pins (PID7 -0). Parity errors
are treated as code violations and cause the byte in error to be replaced with Idle symbols. In REV 1 of the
BMAC device Parity is passed transparently between, MRP,and PRP during transmission. When repeating,
Parity is passed transparently from PIP to PRP. Odd Parity is generated for all internally generated fields. In
all later revisions correct Odd Parity is always generated on the PHY Request Data pins (PRD7 -0).

D4-5

RES

Reserved

D6

ILB

Internal Loopback: Enables the internalloopback that connects PRP, PRC, and PRD7 -0 to PIP, PIC, and
PID7 -0 respectively. When enabled, the PHY Indicate Interface is ignored.
Since the Ring Engine Transmitter and Receiver work as independent processes, a ring can be made
operational in this mode, albeit consisting only of a single MAC. With an operational ring many diagnostic
tests can be performed to test out MAC level and system level diagnostics including: the Beacon Process,
the Claim Process, Ring Engine frame generation, token timers, event counters, transmission options, test
of event detection capabilities, test of addressing modes, test of state machine sequencing options, etc. In
addition, a large portion of the system interface logic can be tested, such as full duplex transmission to self
within the limits of the system interface performance constraints, status handling and generation, etc.
The same system tests can also be performed at different levels of loopback including through the various
paths within a station: through the PMD interface of the PLAYER device, and through the CRD device.
System level tests can also be performed through the ring during normal operation.

D7

DIAG

Diagnose Mode: Enables access to all BMAC device registers. When set, interoperability is not
guaranteed. This bit should only be set when the BMAC device is not inserted in a ring.
In diagnose mode, should an internal error occur the Current Receive and Transmit Status Registers are
frozen with the errored state until the internal state machine error condition is cleared (lELR.RSMERR
and/or IELR.TSMERR).

2·156

.----------------------------------------------------------------------,0
~

6.0 Control Information (Continued)
Option Register (Option)
The Ring Engine supports several options. These options are typically static during operation but may be altered during
operation. This register is initialized to Zero after a master reset.
ACCESS RULES
Read

Address

I

I

01h

Always

w
~

....

Write

I

Always

I

REGISTER BITS
D7

I

D6

ITC

I

D5

EMIND

D4

I IFCS I IRPT

D3

I

IRR

D2

I

ITR

D1

I ELA

DO

I

ESA

I

Bit

Symbol

DO

ESA

Enable Short Addressing: Enables the setting of A-J'lag on matches of received Short Destination
Addresses with MSA. Enables the setting of M_Flag and stripping on matches of received Short Source
Addresses with MSA.
Permits transmission of frames with Short Addresses. Frames with Short Addresses can be transmitted when
Short Addressing is not enabled if the SA Transparency option is selected.
Void frames are sent with the Short Address if ESA is set to One. If ESA is Zero and ELA is One, Void frames
are sent with the Long Address.
When both the ESA and ELA bits are Zero, the ring is effectively interrupted at this station. The token capture
process and Error Recovery logic are suspended and no frames are repeated. Immediate requests are
serviced if the SA Transparency option is selected.

Description

D1

ELA

Enable Long Addressing: Enables the setting of A-Flag on matches of received Long Destination
Addresses with MLA. Enables the setting of M_Flag and stripping on matches of received Long Source
Address with MLA.
Permits transmission of frames with Long Addresses. Frames with long addresses can be transmitted when
long addressing is not enabled if the SA transparency option is selected.
Claim and Beacon frames are sent with the Long Address if ELA is One. If ELA is Zero and ESA is One, Claim
and Beacon frames are sent with the Short Address.
When both ESA and ELA are Zero, the ring is effectively interrupted at this station. The token capture process
and Error Recovery logic are suspended and no frames are repeated. Immediate requests are serviced if the
SA Transparency option is selected.

D2

ITR

Inhibit Token Release: When bit ITR is set to One, the station will not issue a token after winning the Claim
Process. The station remains in the Claim state while the station's Claim frames are returning to the station
and it has won the Claim Process. At this point the station is in control of the ring as long as no Higher_Claim
or Beacon frames are received.
While in control of the ring, the station may transmit special Claim or Management frames for a variety of
implementation specific purposes. For example, the station might send out a Claim frame with a unique
identifier to make sure that another station with its address and TREQ is not also Claiming.

D3

IRR

Inhibit Recovery Required: When bit IRR is set to One, the Ring Engine does not take the transitions into the
Claim state (T4). This option inhibits all the recovery required transitions as defined in the FDDI MAC Standard.
This bit does not inhibit entry to the Claim state on a Claim Request generated at the MAC Request Interface
via the Function Register.
This option can be used to guarantee that implementation specific Beacon frames will be transmitted from the
Beacon state. It is also useful in systems where Local Address Administration is used, to prohibit stations with
the Null Address (or any address) from Claiming. The option could also be used to enable the use of the Ring
Engine in full duplex applications (in conjunction with the Inhibit Repeat option) to disable the recovery timers.

2·157

•

6.0 Control Information (Continued)
Option Register (Continued)
Bit

Symbol

04

IRPT

Inhibit Repeat: When enabled,
1. the Ring Engine cannot enter the Transmitter Repeat and Issue_Token states. This causes all received
POUs to be stripped and prevents tokens from being issued.
2. Void frames are not transmitted during a service opportunity.
3. Idle to Repeat transition is inhibited and all received tokens and MAC frames except Lower_Claim and
My_Beacon frames are ignor~d (Lower_Claim and My_Beacon frames may be ignored by setting
Option.IRR).
When the ring is operational, enabling this option causes the Reset actions to occur upon the completion of
the Service Opportunity, if any. When the ring is not operational, Immediate Requests are serviced and
continue to completion.
The Inhibit Repeat option can be used to scrub the ring for a period longer than the Ring Latency. The option is
also useful in full duplex applications.

Description

05

IFCS

Implementer FCS: Enables use of the standard CRC as the FCS on Implementer frames (FC.FF = 10). When
enabled, Implementer frames are treated like all other frames. When Implementer frames are received with
bad FCS and Er= R, the E Indicator is transmitted as Sand EICT is incremented.
On Implementer frames, the Standard does not mandate the setting of the E Indicator on the result of the FCS
check. This allows Implementers to use alternate Frame Check Sequences aside from the standard 32-bit
CRC. Implementers may also choose not to use any FCS in applications such as packet voice.
If other stations in the ring are using Implementer frames with a non-standard FCS, if used, this option may
cause an interoperability problem.

06

EMINO

External Matching Indicators: Enables the setting of the transmitted A Indicator (Ax) as an S symbol when
the EA pin is set. Also enables the setting of the transmitted C Indicator (Cx) as an S symbol when the VCOPY
pin is set if the A Indicator is set as a result of an external match. The Copied/Not Copied Frame Counters are
also incremented as a result of external comparisons when this option is enabled.

07

ITC

Inhibit Token Capture: When enabled, the Ring Engine is prohibited from transmitting any (more) frames.
This option prohibits entry to the Transmit Void and Data states from the Idle state, and causes exit from the
Data state aiter the current frame has been transmitted ..
When enabled, it is still possible to perform Immediate transmissions from the transmitter Claim and Beacon
states, but not from the Data state.
This option can be used to temporarily block normal data service. it can also be used in conjunction with the
Inhibit Recovery Required option to permit access via the Control Interface to the MAC Parameter RAM during
MAC operation.

2-158

6.0 Control Information

(Continued)

Function Register (Function)
The Ring Engine performs the MAC Reset, Claim Request, and Beacon Request using the Function Register. The Register is
initialized to Zero after a master reset. A function is performed by setting the appropriate bit to One. When the function is
complete, the bit is cleared by the Ring Engine.
ACCESS RULES
Address

Read

Write

02h

Always

Always

I

I

I

I

REGISTER BITS

I

D7

D6

D5

D4

D3

D2

D1

DO

RES

RES

RES

ClM

BCN

MCRST

RES

MARST

Bit
DO

I

I

I

I

I

I

Symbol
MARST

I

I

Description
Master Reset: Produces the functions of an SM_CONTROl(MAC Reset) as specified by the FDDI MAC
Standard. Sets all internal state machines and registers to known values.
Master Reset causes the MCRST bit to be set. It also clears the Mode, Option, Event and Mask Registers.
The Timers are set to their defaults. The Event Counters are not cleared.
When the Master Reset function is complete, MARST is cleared. At this time, all bits in the Function
Register should be Zero.

D1

RES

D2

MCRST

Reserved
MAC Reset: Forces the Receiver to state RO (Listen) and the Transmitter to state TO (Idle).
TNEG (Registers 98-9B) is not loaded with TMAX (this operation can be performed as part of the MAC
Reset Request actions by writing to TNEG before the MAC Reset is initiated).
MCRST takes precedence over bits D3 (BCN) and D4 (ClM), but does not clear these bits.
A MAC Reset that occurs while a frame is being transmitted will cause the frame to be aborted. Frames
without the Frame Status are not transmitted by the Ring Engine. Whenever the byte with the Ending
Delimiter is transmitted, valid frame status is transmitted as well. If a MAC Reset occurs during the byte
where the Ending Delimiter and E Indicator should be transmitted, it will not be transmitted. If a MAC Reset
occurs on the cycle where the A and C Indicators are transmitted, they will still be transmitted.

D3

BCN

Beacon Request: Produces the functions of an SM_CONTROL.request (Beacon) as required by the FDDI
MAC Standard. The Ring Engine Transmitter is forced to enter the Beacon State. Beacon frames are then
transmitted until the Beacon Process completes. The Beacon Process will not complete if Option.IRR = 1.
Beacon frames are generated by the Ring Engine unless an Immediate Beacon Request is present at the
MAC Request Interface and a frame is ready to be transmitted. Even with an External Immediate Beacon
Request the Ring Engine transmits at least one Beacon frame before the Beacon frames from the MAC
Request Interface are transmitted.
If an external Beacon frame is to be transmitted, the Beacon frame should first be set up, then the request
should be given to the MAC Request Interface and then bit BCN should be set to One.
Writing to this bit also sets bit D2 (MCRST). This bit is cleared on entry to the Beacon state. If both bits D3
(BCN) and D4 (ClM) are set, bit D3 takes precedence.

D4

ClM

Claim Request: Produces the functions equivalent to an SM_CONTROL.request (Claim) and causes entry
to the Claim State. The Ring Engine Transmitter is forced to enter the Claim State unless the Transmitter is
in the Beacon State or bit BCN is set to One. Claim frames are then transmitted until the Claim Process
completes. The Claim Process will not complete if Option.ITR = 1.
A Claim Request is honored immediately from any state except the Beacon state. It is honored in the
Beacon state when a My_Beacon returns. Claim requests are honored even when Option.IRR = 1.
Claim frames are generated by the Ring Engine unless an Immediate Claim Request is available at the MAC
Request Interface. Even with an Immediate Claim Request at the interface, the Ring Engine transmits at
least one Claim frame before the Claim frames from the MAC Request Interface are transmitted.
If an external Claim frames is to be transmitted, the Claim frame should first be set up, then the request
should be given to the MAC Request Interface before the ClM bit is set to One.
The Claim bit is reset upon entry to the Claim or Beacon state.

D5-7

RES

Reserved

2-159

~

~
co
C')

a.
C

r-----------------------------------------------------------------------------------------~

6.0 Control Information (Continued)
Revision Register (Rev)
The Revision Register (Rev) contains the revision number of the BMAC device.
ACCESS RULES
Address

I

Write

Read

I

02h

Always

I

I

Data Ignored

REGISTER BITS
07

I

REV7

Bit
00-7

06

I

REV6

I

05
REV5

04

I

REV4

02

03

I

REV3

I

REV2

01

I

REV1

Symbol
REV

00

I

REVO

I

Oescription
Revision Number: Bits 00-7 contain the version 10 of the BMAC device.
Software should consult this register for any software-specific issues related to the current version.
OOh reserved
01 h Initial Release
02h First Revision
• Programmable Group Address Modification
• Not copied count does not increment on reception of NSA frames with Ar = S
• Detection of Idle on reception of nl
• Generation of ODD Parity at all times
• Reset of Latency Count on initiation of new measurement

2-160

6.0 Control Information

(Continued)

6.4 EVENT REGISTERS
The Event Registers record the occurrence of events or
series of events. Events are recorded and contribute to generating the Interrupt signal. There is a two-level hierarchy in
generating this signal.
'
,

that have not changed since the last read can be written to
a new value.
Whenever a Condition Latch' Register is read, its contents
are stored in the Compare Register. Each bit of the Compare Register is compared with the current contents of the
Register that is to be written. Writing a bit with a new value
to a Condition Register is only possible when the corresponding bit in the Compare Register matches the bit in the
Condition Register. For any bit that has not changed, the
new value of the bit is written into the Register. For any bit
that has changed, the writing of the bit is inhibited. The fact
that an attempt was made to change a modified bit in the
Register is latched in the Condition Write Inhibit bit in the
Exception Status Register (ESR.CWI).

At the first level of the hierarchy. events are recorded as bits
in the Latch Registers (e.g., Ring Event Latch Registers,
Counter Increment Latch Register). Each Latch Register
has a corresponding Mask Register (e.g., Ring Event Mask
Registers, Counter Increment Mask Register). When a bit in
the Latch Register is set to One and its corresponding bit in
the Mask Register is also set to One, a bit in the Interrupt
Condition Register is set to One.
At the second level of the hierarchy, if a bit in the Interrupt
Condition Register is set to One and the corresponding bit
in the Interrupt Mask Register is set to One, the Interrupt
signal is asserted.
Bits in Conditional Write Registers (e.g., Ring Event Latch
Registers) are only written when the corresponding bits in
the Compare Register are equal to bits to be overwritten.

In the BMAC device, the Compare Register is shared by all
of the Condition Latch Registers and always reflects the
most recent read of one of these registers. (In the
DP83251/5 PLAYER Device, there is a Compare Register
for every Event Register.) For the cases where more than
one register must be read before writing a new value, the
software may write the Compare Register with the most recently read value before writing the register again. Alternatively, the register may be read again before being written.
The Event Registers include the following registers as:

Servicing Interrupts
In the process of servicing an interrupt, a Management Entity may use one or both levels of condition masks to disable
new interrupts while one is being serviced. Soon after the
Management Entity has processed the interrupt to some extent, it is ready to rearm the interrupt in order to be notified
of the next condition.

• Compare Register (CMP)
• Current Receiver Status Register (CRSO)
• Current Transmitter Status Register (CTSO)
• Ring Event Latch Registers (RELRO-1)

The Interrupt Control Register always contains the merged
output of the masked Condition Registers as shown in Figure 6-1. It is only possible to remove a condition by setting
the corresponding Condition Latch Register bit to Zero. By
storing the events on-chip, and having the ability to selectively set bits to Zero, the need for the software to maintain
a copy of the Event Registers is alleviated.

• Ring Event Mask Registers (REMRO-1)
• Token and Timer Event Latch Register (TELRO)
• Token and Timer Event Mask Register (TEMRO)
• Counter Increment Latch Register (CILR)
• Counter Increment Mask Register (CIMR)
• Counter Overflow Latch Register (COLR)

To prevent the overwriting and consequent missing of
events, an interlock mechanism is used. In the period between the Read of a Condition Latch Register, and the corresponding Write to reset the condition, additional events
can occur.

• Counter Overflow Mask Register (COMR)
• Internal Event Latch Register (IELR)
• Exception Status Register (ESR)
• Exception Mask Register (EMR)

In order to prevent software from overwriting bits which
have changed since the last read and losing interrupt
events a conditional write mechanism is employed. Only bits

• Interrupt Condition Register (lCR)
• Interrupt Mask Register (lMR)

II
TLlF/103B7-7

FIGURE 6-1. Event Registers Hierarchy

2-161

,..
CD
N
M
CO

a.
C

r-------------~--------------------------------------------------------------------__,

6.0 Control Information (Continued)
Compare Register (CMP)

The Compare Register (CMP) is written with the contents of a coriditional event latch registers when it is read. The Compare
Register may also be written to directly. During a write to any of the conditional write registers, the contents of the Compare
Register (CMP) is compared with bits 00-7 of the accessed register. Orily bits for which the comparison matches can be written
to a new value.
ACCESS RULES
Address

Read

Write

OSh

Always

Always

REGISTER BITS

07

06

05

04

03

02

01

DO

CMP7

CMP6

CMP5

CMP4

CMP3

CMP2

CMP1

CMPO

2·162

6.0 Control Information (Continued)
Current Receiver Status Register (CRSO)
The Current Receiver Status Register (CRSO) records the status of the Receiver state machine. It is continuously updated. ·It
remains stable when accessed.
When in Diagnose Mode, this register is frozen on an internal error until the internal error event is cleared by resetting the
RSMERR bit in the Internal Event Latch Register.
ACCESS RULES
Address

I

Write

Read

I

OCh

I

Always

Data Ignored

I

REGISTER BITS
07

I

RFLG

06

I

RS2

05

I

RS1

Bit

Symbol

DO-2

RTS(0-2)

04

I

RSO

D3

I

RES

D2

I

RTS2

01

I

RTS1

DO

I

RTSO

I

Description
Receive Timing State: RTS(0-2) represent the current state of the Receiver Timing state
machine. The encoding is shown below.
RTS2

0
0

0
0
1
1
1

RTS1
0
0
1
1
0
0
1

RTSO
1
1
0
1
0
1
x

Receive Timing State
AwaiLSD
ChecLFC
Check-SA
Check-DA
Check-INFO
ChecLMAC
Reserved

D3

RES

Reserved

D4-6

RS(0-2)

Receive State: RS(0-2) represent the current state of the Receive state machine that
implements the ANSI standard MAC Receive Functions. The encoding is shown below.
RS2
RS1
RSO
Receive State
0
0
0
Listen
0
0
1
AwaiLSD
RC_FR_CTRL (Receive FC)
0
1
0
RC_FR_BODY (Rec FR Body)
1
0
1
RC_FFL-STATUS (A & C Ind)
0
0
1
1
0
1
CHECK-TOKEN (Check Token)
RC_FR_STATUS (Optionallnd)
1
1
0
1
1
1
Reserved

D7

RFLG

R_Flag: Current value of the Restricted Flag. When not holding the token indicates the type of
the last valid token received. When holding the token indicates the type of token that will be
issued at the end of the current service opportunity.
0: Non-restricted
1: Restricted

I

2-163

~

~

C")

CD

~

r-------------------------------------------------------------------------------------,
6.0 Control Information (Continued)
Current Transmitter Status Register (CTSO)
The Current Transmitter Status Register (CTSO) records the status of the Transmitter state machine. It is continuously updated.
It remains stable when accessed. When in Diagnose Mode, this register is frozen on an internal error until the internal error
event is cleared by resetting the TSMERR bit of the Internal Event Latch Register. "
ACCESS RULES
Address

I

Read

I

OEh

Write

I

Always

I

Data Ignored

REGISTER BITS
D7

I

ROP

D6

I

TS2

D5

I

TSI

Bit

Symbol

DO-3

TTS(O-3)

D4

I

TSO

D3

I

D2

TTS3

I

Dl

"TTS2

I

TTSI

TTSO

I

TRANSMIT TIMING STATE: TTS(O-3) represent the current state of the Transmitter
Timing state machine. The encoding is shown below.
TTS2

o
o

TTSI

TTSO

0
0
0
0
0 0 1
0 0 1
o
1
0
o
1
0

0
1
0
1
0
1

1

1

0

1
0

1
0

1
0

o
o
1

9h-Fh
TS(O-2)

I

Description

TTS3

D4-6

DO

Transmit Timing State
Idle
Transmit Preamble
Wait for Data (FIFO)
Transmit SD & FC Fields
TransmitDA
Transmit SA
Transmit INFO
Transmit FCS
Transmit ED & FS
Reserved

Transmit State: TS(O-2) represent the current state of the Transmit state machine that
implements the ANSI standard MAC Transmit Functions. The encoding is shown below.
TS2
TSI
TSO
Transmit State'
o
0
0
Idle
0
1
Repeat
o
1
0
Data
o
1
1
Issue Token
1
0
0
Claim
1
0
1
Beacon
1
1
0
Reserved
1
1
1
Void

o

D7

ROP

Ring Operational Flag: Indicates the current value of the local Ring Operational Flag.

2-164

6.0 Control Information (Continued)
Ring Event Latch Register (RELRO)
The Ring Event Latch Register 0 (RELRO) captures conditions that occur on the Ring including the receipt of Beacon and Claim
frames, transitions in the Ring Operational flag, and the receipt of duplicate addresses. Each bit may be masked via the Ring
Event Mask Register 0 (REMRO).
ACCESS RULES
Address

I

Read

I

10h

Always

Write

I

Condition

I

D3

D2

REGISTER BITS
D7

D6

D5

D4

D1

DO

I RES I OUPAOO I PINV I OTRMAC I CLMR I BCNR I RNOP I ROP I
Bit

Symbol

Description

DO

ROP

Ring Operational Set: Is set when the Local Ring Operational flag transitions from 0 to 1.

01

RNOP

Ring Non·Operatlonal Set: Is set when the Local Ring Operational flag transitions from 1 to O.

02

BCNR

Beacon Frame Received: Indicates that a valid Beacon frame was received. When set, restricted and
synchronous requests are not serviced. The type of Beacon frame received is given in Register RELR 1.

03

CLMR

Claim Frame Received: Indicates that a valid Claim frame was received. When set, restricted requests are
not serviced. The type of Claim frame received is given in Register RELR1.

04

OTRMAC

Other MAC Frame Received: Indicates that a MAC frame other than a Beacon or Claim frame was received.
When set, restricted requests are not serviced.

05

PINV

PHY_Invalid Received: Indicates that a PHY_Invalid was received. This could be the result of a PLAYER
device Reset operation.
PHY_Invalid causes the MAC Receiver to enter state RO (Listen).

06

DUPAOO

Duplicate Address Received: Indicates that a valid individual frame addressed to this station was received
with the A indicator set. This could be caused by either a MAC using the same address (duplicate address) or
a strip error at the Source (the frame was received twice).

D7

RES

Reserved

2·165

.,...
co

N

C')

co
Il..
C

6.0 Control Information (Continued)
Ring Event Mask Register 0 (REMRO)
The Ring Event Mask Register 0 (REMRO) is used to mask bits in Register RELRO. If a bit in Register REMRO is set to One, the
corresponding bit in Register RELRO will be applied to the Interrupt Condition Register, which can then be used to generate an
interrupt.
ACCESS RULES
Address

I

I

11h

Write

Read

I

Always

Always

I

REGISTER BITS
07

06

05

04

03

02

01

DO

I RES I OUPAOO I PINV I OTRMAC I CLMR I BCNR I RNOP I Rap I
Bit

Symbol

Description

00

Rap

Ring Operational Mask: This bit is used to mask RELRO.ROP.

01

RNOP

Ring Non-Operational Mask: This bit is used to mask RELRO.RNOP.

02

BCNR

Beacon Frame Mask: This bit is used to mask RELRO.BCNR.

03

CLMR

Claim Frame Mask: This bit is used to mask RELRO.CLMR.

04

OTRMAC

Other MAC Frame Mask: This bit is used to mask RELRO.OTRMAC.

05

PINV

PHY_lnvalid Mask: This bit is used to mask RELRO.PINV.

06

OUPAOO

Duplicate Address Mask: This bit is used to mask RELRO.DUPAOO.

07

RES

Reserved

2-166

6.0 Control Information

(Continued)

Ring Event Latch Register 1 (RELR1)
The Ring Event Latch Register 1 (RELR1) captures the progress of the Beacon and,Claim Processes. During the Beacon
Process, it records reception of an Other_Beacon or a My:.....Beacon. It also identifies Claim frames as Higher, Lower, or My
Claim. Each bit may be masked via the Ring Event Mask Register 1 (REMR1).
ACCESS RULES
Read

Address

I

I

12h

Always

Write

I

Condition

I

REGISTER BITS
D7

D6

D5

D4

D3

D2

D1

DO

I LOCLM I HICLM I MYCLM I RES I RES I RES I MYBCN I OTRBCN I
Bit
DO

Description

Symbol
OTRBCN

Other_Beacon Received: Indicates that an Other_Beacon frame was received.

D1

MYBCN

My_Beacon Received: Indicates that a My_Beacon frame was received.

D2-4

RES

Reserved

D5

MYCLM

My_Claim Received: Indicates that a My_Claim frame was received. (This includes the comparison
between the T_Bid_Rec and TREQ as specified in the standard).

D6

HICLM

Higher_Claim Received: Indicates that a Higher_Claim frame was received.

D7

LOCLM

Lower_Claim Received: Indicates that a Lower_Claim frame was received.

2-167

....

I
Q

6.0 Control Information (Continued)
Ring Event Mask Register 1 (REMR1)
The Ring Event Mask Register 1 (REMR1) is used to mask bits in Register RELR1.lf a bit in Register REMR1 is set to One,the
corresponding bit In Register RELR1 will be applied to the Interrupt Condition Register, which can then be used to generate an
Interrupt to the CPU.
All bits in this register are set to Zero upon reset.
ACCESS RULES
Addre88

I

Read

I

13h

Write

I

Always

Always

I

REGISTER BITS

I

D7
LOCLM

Bit
00

I

D6
HICLM

I

D5
MYCLM

I

D4
RES

I

D3
RES

I

D2
RES

I

D1
MYBCN

Symbol
OTRBCN

I

DO
OTRBCN

I

Description
Other_Beacon Mask: This bit is used to mask RELR1.0TRBCN.

01

MYBCN

My_Beacon Mask: This bit is used to mask RELR1.MYBCN.

02-4

RES

Reserved

05

MYCLM

My_Claim Mask: This bit is used to mask RELR1.MYCLM.

06

HICLM

Higher_Claim Mask: This bit is used to mask RELR1.HICLM.

07

LOCLM

Lower_Claim Mask: This bit is used to mask RELR1.LOCLM.

2-168

6.0 Control Information (Continued)
Token and Timer Event Latch Register 0 (TELRO)
The Token and Timer Event Latch Register 0 (TELRO) informs software of expirations of the Token Rotation Timer (TRT) and
Valid Transmission Timer (TVX). The TELRO Register also reports token events such as duplicate token detection, restricted
token reception, and general token capture and release. The completion of the Ring Latency measurement Is also indicated in
the TELRO Register. Each bit may be masked via the Token and Timer Event Mask Register (TEMRO).
ACCESS RULES
Address

I

14h

I

Read

Write

Always

Condition

I

I

REGISTER BITS
D7

D6

D5

D4

D3

D2

D1

DO

IRLVDITKPAsslTKCAPTICBERRIDUPTKRITRTEXplTVXEXplENTRMDI
Bit

Symbol

DO

ENTRMD

Enter Restricted Mode: Indicates that a Restricted Token was received and that the R_Flag transitioned
from 0 to 1.

Description

D1

TVXEXP

TVX Expired: Indicates that a valid frame or token was not received in TVX time.

D2

TRTEXP

TRT Expired: Indicates that a valid token was not received within 2·TNEG.

D3

DUPTKR

Duplicate Token Received: Indicates that a valid token was received while the transmitter was in state T2
orT3.

D4

CBERR

Claim and/or Beacon Error: Indicates that the Claim and/or Beacon Process failed because TRT expired
while the Transmitter was in state.T4 or T5.

D5

TKCAPT

Token Captured: Indicates that a token has been captured.

D6

TKPASS

Token Passed: Indicates that a valid token has been passed (without capturing it) or has been issued after a
service opportunity.

D7

RLVD

Ring Latency Valid:
0: This bit is set to Zero to request a new latency value from the Ring Engine. In Rev 01 and all future
Revisions, the Ring Latency count is set to zero before each measurement.
1: This bit is set to One when the Ring Latency measurement is complete.
This bit is written unconditionally and is not protected by the Compare Register.

•
2-169

...
~

CD

a.
Q

6.0 Control Information (Continued)
Token and Timer Event Mask Register 0 (TEMRO)
The Token and Timer Event Mask Register 0 (TEMRO) is used to mask bits in Register TELRO. If a bit in Register TEMRO is set
to One, the corresponding bit in Register TELR will be applied to the. Interrupt Condition Register, which can then be used to
generate an interrupt.
All bits in this register are set to Zero upon reset.
ACCESS RULES
Address

I

15h

I

Read

Write

Always

Always

I

I

REGISTER BITS
D7

D6

D5

D4

D3

D2

D1

DO

IRLVolTKPASSITKCAPTICBERRIOUPTOKITRTEXplTVXEXplENTRMOI
Bit

Symbol

00

ENTRMO

Enter Restricted Mode Mask: This bit is used to mask TELRO.ENTRMD.

Description

01

TVXEXP

TVX Expired Mask: This bit is used to mask TELRO.TVXEXP.

02

TRTEXP

TRT Expired and Set Lat8.-Flag Mask: This bit is used to mask TELRO.TRTEXP.

03

OUPTOK

Duplicated Token Received Mask: This bit is used to mask TELRO.OUPTOK.

04

CBERR

Claim/Beacon Error Mask: This bit is used to mask TELRO.CBERR.

05

TKCAPT

Token Captured Mask: This bit is used to mask TELRO.TKCAPT.

06

TKPASS

Token Passed Mask: This bit is used to mask TELRO.TKPASS.

07

RLVO

Ring Latency Valid Mask: This bit is used to mask TELRO.RLVO.

2·170

6.0 Control Information (Continued)
counter Increment Latch Register (CllR)
The Counter Increment latch Register (CllR) records the occurrence of any increment to the Event Counters. Each bit
corresponds to a counter and is set when the corresponding counter is incremented. Each bit may be masked via the Counter
Increment Mask Register (CIMR).
ACCESS RULES
Address

I

Read

I

1Bh

Write

I

Always

Condition

I

REGISTER BITS

07

06

05

04

03

02

01

DO

I RES I TKRCVO I FRTRX I FRNCOP I FRCOP I FRlST I FREI I FRRCV I
Bit

Symbol

DO

FRRCV

Frame Received: Is set when the Frame Received Counter (FRCT) is incremented, indicating the reception
ofa frame.

D!

FREI

Frame Error Isolated: Is set when the Error Isolated Counter (EICT) is incremented, indicating an error has
been insolated.

02

FRlST

Frame lost Isolated: Is set when the lost Frame Counter (lFCT) is incremented, indicating a format error
has been detected in the frame.

03

FRCOP

Frame Copied: Is set when the Frame Copied Counter (FCCT) is incremented, indicating a frame has been
copied.

04

FRNCOP

Frame Not Copied: Is set when the Frame Not Copied Counter (FNCT) is incremented, indicating a frame
could not be copied.

05

FRTRX

Frame Transmitted: Is set when the Frame Transmitted Counter (FTCT) is incremented, indicating a frame
has been transmitted.

06

TKRCVO

Token Received: Is set when the Token Received Counter (TKCT) is incremented, indicating that a token
has been received.

07

RES

Reserved

Description

I

II

2-171

...

CD
N

C')

CD

a.
Q

6.0 Control Information (Continued)
Counter Increment Mask Register (CIMR)
The Counter Increment Mask Register (CIMR) is used to mask bits from the Counter Increment Latch Register (CILR). If a bit in
Register CIMR is set to One, the corresponding bit in Register CILR will be applied to the Interrupt Condition Register, which can
then be used to generate an interrupt.
All bits in this register are set to Zero upon reset.
ACCESS RULES
Address

I

19h

Read

I

Write

I

Always

I

Always

REGISTER BITS
D7

D6

RES

TKRCVO

I I

I

D5
FRTRX

I

D4
FRNCOP

I

D3
FRCOP

I

D2
FRLST

I

D1
FREI

I

DO
FRRCV

I

Bit

Symbol

00

FRRCV

Frame Received Counter Increment Mask: This bit is used to mask CILR.FRRCV.

Description

Error Isolated Counter Increment Mask: This bit is used to mask CILR.FREI.

01

FREI

02

FRLST

Lost Frame Counter Increment Mask: This bit is used to mask CILR.FRLST.

03

FRCOP

Frame Copied Counter Increment Mask: This bit is used to mask CILR.FRCOP.

04

FRNCOP

Frame Not Copied Counter Increment Mask: This bit is used to mask CILR.FRNCOP.

05

FRTRX

Frame Transmitted Counter Increment Mask: This bit is used to mask CILR.FRTRX.

06

TKRCVO

Token Received Counter Increment Mask: This bit is used to mask CILR.TKRCVO.

07

RES

Reserved

2·172

6.0 Control Information (Continued)
Counter Overflow Latch Register (COLR)
The Counter Overflow Latch Register (COLR) records carry events from the 20th bit of the Event Counters. Each bit in the
COLR corresponds to an individual counter. Each bit may be masked via the Counter Overflow Mask Register (COMR).
ACCESS RULES
Address

I

Read

I

lCh

Write

I

Always

Condition

I

REGISTER BITS
06

07

05

04

03

02

01

DO

I RES I TKRCVO I FRTRX I FRNCOP I FRCOP I FRLST I FREI I FRRCV I
Bit

Symbol

DO

FRRCV

Frame Received: Is set to One when the Frame Received Counter (FRCT) overflows.

Description

01

FREI

Frame Error Isolated: Is set to One when the Error Isolated Counter (EICT) overflows.

02

FRLST

Frame Lost Isolated: Is set to One when the Lost Frame Counter (LFCT) overflows.

03

FRCOP

Frame Copied: Is set to One when the Frame Copied Counter (FCCT) overflows.

04

FRNCOP

Frame Not Copied: Is set to One when the Frame Not Copied Counter (FNCT) overflows.

05

FRTRX

Frame Transmitted: Is set to One when the Frame Transmitted Counter (FTCT) overflows.

06

TKRCVO

Token Received: Is set to One when the Token Received Counter (TKCT) overflows.

07

RES

Reserved

•
2-173

6.0 Control Information (Continued)
Counter Overflow Mask Register (COMR)
The Counter Overflow Mask Register (COMR) is used to mask bits Irom the Counter Overflow Latch Register (COLR). II a bit in
Register COMR is set to One, the corresponding bit in Register COLR will be applied to the Interrupt Condition Register, which
can then be used to generate an interrupt.
All bits in this register are set to Zero upon reset.
ACCESS RULES
Read

Address

I

10h

I

Write

I

Always

Always

I

REGISTER BITS
07

06

05

04

03

02

01

00

I RES I TKRCVO I FRTRX I FRNCOP I FRCOP I FRLST I FREI I FRRCV I
Bit

Symbol

00

FRRCV

Frame Received Counter Overflow Mask: niis bit is used to mask COLR.FRRCV.

01

FREI

Error Isolated Counter Overflow Mask: This bit is used to mask COLR.FREI.

02

FRLST

Lost Frame Counter Overflow Mask: This bit is used to mask COLR.FRLST.

03

FRCOP

Frame Copied Counter Overflow Mask: This bit is used to mask COLR.FRCOP.

04

FRNCOP

Frame Not Copied Counter Overflow Mask: This bit is used to mask COLR.FRNCOP.

05

FRTRX

Frame Transmitted Counter Overflow Mask: This bit is used to mask COLR.FRTRX.

06

TKRCVO

Token Received Counter Overflow Mask: This bit is used to mask COLR.TKRCVO.

07

RES

Reserved

Oescription

2-174

6.0 Control Information

(Continued)

Internal Event Latch Register (IELR)
The Internal Event Latch Register (IELR) reports internal errors in the BMAC device. These errors include MAC Parity errors and
inconsistencies in the Receiver and Transmitter state machines.
After an internal state machine is detected and reported (bit RSMERR for the receiver and TSMERR for the transmitter), the
Current Receive Status Register (CRSO) and Current Transmit Status Register (CTSO) continue to be updated as normal.
Errors internal to the BMAC device cause a MAC_Reset.
ACCESS RULES
Address

I

Read

I

28h

Write

I

Always

Condition

I

REGISTER BITS
07

I

RES

Bit
DO

06

I

RES

05

I

RES

04

I

RES

03

I

TSMERR

02

I

01

RSMERR

I

Symbol
MPE

DO

RES

I

MPE

I

Description
MAC Interface Parity Error: Indicates a Parity Error on the MAC Request Data pins (MR07-0) when
parity is enabled on the MA-Request interface (bits MRP of the Mode Register is set and pin TXACK is
asserted).

01

RES

Reserved

02

RSMERR

Receive State Machine Error: Indicates inconsistency in the Receiver state machine. When set, causes
bit MCRST of the Function Register to be set.

03

TSMERR

Transmit State Machine Error: Indicates inconsistency in the Transmitter state machine. When set,
causes bit MCRST of the Function Register to be set.

04-7

RES

Reserved

2-175

.-

I
c

6.0 Control Information (Continued)
Exception Status Register (ESR)
The Exception Status Register (ESR) reports errors to the software. Errors include PHY Interface Parity errors, illegal attempts
to access currently inaccessible registers, and writing to a conditional write location if a register bit has changed since it was last
read. Each bit may be masked via the Exception Mask Register (EMR).
ACCESS RULES
Address

I

Write

Read

I

2Ch

I

Always

I

Condition

REGISTER BITS
D7

I

CWI

Bit

DO

D6

I

CCE

D5

I

CPE

D4

I

RES

D3

I

RES

D2

I

RES

D1

I

RES

Symbol
PPE

DO

I

PPE

I

Description
PHY Interface Parity Error: Indicates parity error detected on PID7 -0. Parity errors are reported when
parity is enabled on the PHY_Request Interface (bit PIP of the Mode Register is set).

01-4

RES

Reserved

05

CPE

Control Bus Parity Error: Indicates a Control Bus Parity Error was detected on the Control Bus Data pins
(CBD7 -0) during a write operation to a register. Parity errors are reported if parity is enabled on the Control
Bus Interface (bit CBP of the Mode Register is set).

06

CCE

Control Bus Command Error: Indicates that a Control Bus command was not performed due to an error,
i.e., illegal command or a Control Bus Write Parity error. An illegal command is an attempt to access a
currently inaccessible register.

07

CWI

Conditional Write Inhibit: Indicates that at least one bit of the previous conditional write operation was not
written. This bit is set unconditionally after each write to a conditional write register if the value of the
Compare Register is not equal to the value of the register that was accessed for a write before it was
written. This may Indicate that the accessed register has changed since it was last read.
This bit is cleared after a successful conditional write. This occurs when the value of the Compare Register
is equal to the value of the register that was accessed for a write before it was written.
CWI does not contribute to setting the ESE bit of the Interrupt Condition Register (it is always implicitly
masked).

2-176

C

.."

6.0 Control Information (Continued)

OCI
Co)

N

The Exception Mask Register (EMR) is used to mask bits in the Exception Status Register (ESR). If a bit in Register EMR is set
to One, the corresponding bit in Register ESR will be applied to the Condition Register, which can then be used to generate an
interrupt.
All bits in this register are set to Zero upon request.
ACCESS RULES
Address

I

Read

I

20h

Write

I

Always

Always

I

REGISTER BITS
07

I

ZERO

Bit
00

06

I

CCE

05

I

CPE

04

I

RES

03

I

RES

02

I

RES

01

I

00

RES

Symbol
PPE

....

en

Exception Mask Register (EMR)

I

PPE

I

Oescription
PHY Interface Parity Error Mask: This bit is used to mask ESR.PPE.

01-4

RES

Reserved

05

CPE

Control Bus Parity Error Mask: This bit is used to mask ESR.CPE.

06

CCE

Control Bus Error Mask: This bit is used to mask ESR.CCE.

07

ZERO

Zero: This bit is always Zero. This implies that the CWI bit never contributes to the Interrupt Signal.

2-177

6.0 Control Information (Continued)
Interrupt Condition Register (ICR)
The Interrupt Condition Register (ICR) collects unmasked interrupts from the Event Registers. Interrupts are categorized into
Ring Events, Token and Timer Events, Counter Events, and Error and Exceptional Status Events. If the bit in the Interrupt Mask
Register (IMR) and the corresponding bit in the ICR are set to One, the INT pin is forced low and thus triggers an interrupt.
Note: Bits are cleared ONLY by cleartng underlying conditions (Mask bit andlor Event Bit) In the approprtate Event Register.

ACCESS RULES
Address

I

Read

I

2Eh

Write

I

Always

Data Ignored

I

REGISTER BITS
07

I

ESE

Bit

06

I

IERR

05

I

RES

04

I

RES

03

I

CaE

02

I

CIE

01

I

TIE

Symbol

DO

I

RNG

I

Description

DO

RNG

Ring Event Interrupt: Is set if corresponding bits in the Ring Event Latch and Mask Registers are set.

D1

TIE

Token and Timer Event Interrupt: Is set if corresponding bits in the Token and Timer Event Latch and
Mask Registers are set.

D2

CIE

Counter Increment Event Interrupt: Is set if corresponding bits in the Counter Increment Latch and Mask
Registers are set.

D3

CaE

Counter OverflOW Event Interrupt: Is set if corresponding bits in the Counter Overflow Latch and Mask
Registers are set.

D4-5

RES

Reserved

D6

IERR

Internal Error Interrupt: Is set if any bits in the Internal Event Register are set.

D7

ESE

Exception Status Event Interrupt: Is set if corresponding bits in the Exception Status and Mask Registers
are set.

2-178

C
"tI
co

6.0 Control Information (Continued)

c.:I
N

Interrupt Mask Register (IMR)

0)

The Interrupt Mask Register (IMR) is used to mask bits in the Interrupt Condition Register (lCR). If a bit in Register IMR and the
corresponding bit in Register ICR are set to One, the INT pin is forced low and causes an interrupt. Each bit in the IMR
corresponds to an Event Register or a pair of Event Registers and associated bits.
ACCESS RULES
Address

I

Write

Read

I

2Fh

I

Always

I

Always

REGISTER BITS
D7

I

ESE

Bit

D6

I

IERR

D5

I

RES

D3

D4

I

RES

I

CaE

D2

I

CIE

D1

I

TIE

Symbol

DO

I

RNG

I

Description

DO

RNG

Ring Event Mask: This bit is used to mask ICR.RNG.

D1

TIE

Token and Timer Event Mask: This bit is used to mask ICR.TIE.

D2

CIE

Counter Increment Event Mask: This bit is used to mask ICR.CIE.

D3

CaE

Counter Overflow Event Mask: This bit is used to mask ICR.COE.

D4-5

RES

Reserved

D6

IERR

Internal Error Mask: This bit is used to mask ICR.IER.

D7

ESE

Exception Status Event Mask: This bit is used to mask ICR.ESE.

2-179

......

6.0 Control Information (Continued)
6.S MAC PARAMETERS
The MAC Parameters are accessible in the Stop Mode. These parameters are also accessible in the Run Mode when the
following conditions are met:
a) the MAC Transmitter is in state TO, T1, or T3; and
b) bits ITC and IRR of the Option Register are set to One; and
c) bits CLM and BCN of the Function Register are set to Zero.
Otherwise read and write accesses will cause a command error (bit CCE of the Exception Status Register is set to One) and the
access will not be performed.
The MAC Parameters are stored in the MAC Parameter RAM. They include the following control information:
• Individual Addresses: My Long Address (MLAO-5) and My Short Address (MSAO-1).
• Group Addresses: Group Long Address (GLAO-4) and Group Short Address (GSAO), Programmable Group Map
(PGMO-1F), and Fixed Group Map (FGMO-1) .
• MAC Frame Information: Requested Target Token Rotation Time (TREQO-3) and Transmit Beacon Type (TBTO-3).
6.S.1 Individual Addresses
The Ring Engine supports both Long and Short Individual Addresses simultaneously. The Station's Long Address is stored in
registers MLAO-5. The Station's Short Address is stored in register MSAO-1.
For received frames, MLA or MSA is compared with the received DA in order to set the Address recognized Flag (A Flag) and
compared with the received SA in order to set the My Address recognized Flag (M Flag). In transmitted frames, MLA or MSA
normally replaces the SA from the frame data stream (exception: when SA transparency is used).
Bits MLA(47) and MSA(15) are the most significant bits of the address and are transmitted and received first. Bits MLA(O) and
MSA(O) are the least significant bits of the address and are transmitted and received last.
MLA and MSA should be valid for at least 12 byte times before the Addressing Mode is enabled and should remain valid for at
least 12 byte times after the Addressing Mode is disabled in order to guarantee proper detection.
Bits ELA (Enable Long Addressing) and ESA (Enable Short Addressing) in the Option Register determine the address types that
may be recognized and generated by this MAC.
My Long Address
My Long Address (MLAO-MLA5) represent this station's long 48-bit address.
ACCESS RULES
Address

Read

Write

40-45h

Stop Mode

Stop Mode

07

D6

os

04

D3

02

01

DO

MLAO

MLA(47)

MLA(46)

MLA(45)

MLA(44)

MLA(43)

MLA(42)

MLA(41)

MLA(40)

MLA1

MLA(39)

MLA(38)

MLA(37)

MLA(36)

MLA(35)

MLA(34)

MLA(33)

MLA(32)

MLA2

MLA(31)

MLA(30)

MLA(29)

MLA(28)

MLA(27)

MLA(26)

MLA(25)

MLA(24)

MLA3

MLA(23)

MLA(22)

MLA(21)

MLA(20)

MLA(19)

MLA(18)

MLA(17)

MLA(16)

MLA4

MLA(15)

MLA(14)

MLA(13)

MLA(12)

MLA(11)

MLA(10)

MLA(9)

MLA(8)

MLAS

MLA(7)

MLA(6)

MLA(5)

MLA(4)

MLA(3)

MLA(2)

MLA(1)

MLA(O)

Note: MLA(47) should always be set to O.

My Short Address
My Short Address (MSAO-MSA1) represent this station's short 16-bit address.
ACCESS RULES
Address

Read

Write

46-47h

Stop Mode

Stop Mode

MSAO

MSA1
Note: MSA(15) should always be set to O.

2-180

6.0 Control Information (Continued)
6.5.2 Group Addresses
The Ring Engine supports detection of Group Addresses within programmable and fixed blocks of consecutive addresses. The
algorithm used by the Ring Engine first performs a comparison between the most significant bits of the received DA with
programmable and fixed addresses. If the most significant bits match, the remaining bits are used as an index into a programmable bit map. If the indexed bit is 1, the A Flag is set to 1; if the indexed bit is 0 the A flag remains O.
One programmable block of 128 group addresses is supported for group long addresses (GLA) and one programmable block of
group addresses is supported for group short addresses (GSA). Both of the programmable ranges share the same programmable group address map (PGM).
For short addresses, the first byte of a received DA is compared with GSAO (bits GSA(15-8)}. If they match then the second
byte is used as an index into the PGM. For long addresses the first 5 bytes of a received DA are compared with GLAO through
GLA4 (bits GLA(47-8)}. If all 5 of these bytes match the corresponding byte in the received DA, then the 6th byte of the
received DA is used as an index into the PGM. The last byte of the address is used as an index into the PGM in both long and
short group addressing.
A fixed block of 16 group addresses is supported for both long and short addresses at the end of the address space that
includes the Universal/Broadcast address (FF ... FF). For short addresses, if the first 12 bits of the received DA are all 1 's then
the last 4 bits are used as an index into the 16-bit Fixed Group Map (FGM). Similarly, for long addresses if the first 44 bits are all
1's, the last 4 bits are also used as an index into the 16-bit FGM.
The Group Addresses should be valid for at least 12 byte times before the Addressing Mode is enabled and should remain valid
for at least 12 byte times after the Addressing Mode is disabled in order to guarantee proper detection.
Bits ELA (Enable Long Addressing) and ESA (Enable Short Addressing) in the Option Register determine the address types that
will be recognized by this MAC.
Alternative group addressing schemes may be implemented using external matching logic that monitors the byte stream at the
PHY Interface. The result of the comparison is returned using the EA (External A-Flag) pin.

Group Long Address
Group Long Address (GLAO-GLA4) represents the first 5 bytes of the long address, bit GLA(47} to bit GLA(8}.
To disable Long Group Address matches, bits GLA(46-8} should be set to all 1 'so

ACCESS RULES
Address

Read

Write

48-4Ch

Stop Mode

Stop Mode

07

06

05

04

03

02

01

DO

GLAO

GLA(47}

GLA(46}

GLA(45}

GLA(44}

GLA(43}

GLA(42}

GLA(41}

GLA(40}

GLAl

GLA(39}

GLA(38}

GLA(37}

GLA(36}

GLA(35}

GLA(34}

GLA(33}

GLA(32}

GLA2

GLA(31}

GLA(30}

GLA(29}

GLA(28}

GLA(27}

GLA(26}

GLA(25}

GLA(24}

GLA3

GLA(23}

GLA(22}

GLA(21}

GLA(20}

GLA(19}

GLA(18}

GLA(17}

GLA(16}

GLA4

GLA(15}

GLA(14}

GLA(13}

GLA(12}

GLA(ll}

GLA(10}

GLA(9}

GLA(8}

Nole: Bit GLA(47) should always ba sat to ONE.

2-181

~

CD
N

C")

CD

a..

Q

r-----------------------------------------------------------------------------------------,
6.0 Control Information (Continued)
Group Short Address
Group Short Address (GSAO) represents the station's short 16-bit address, bit GSA(15) to bit GSA(8).
It is possible to disable Short Group Addressing by programming bits GSA(14-8) to all Ones.
ACCESS RULES
Address

Read

Write

4Eh

Stop Mode

Stop Mode

GSA4

07

06

05

04

03

02

01

00

GSA(15)

GSA(14)

GSA(13)

GSA(12)

GSA(11)

GSA(10)

GSA(9)

GSA(8)

Design Note: GSA(15) is not used in the comparison since the comparison will only be accomplished if the received OA(15) is a One.

Fixed Group Address MAP (FGMO-FGM1)
Ifthe first 44 bits of a long DA, DA(47-4), or ifthe first 12 bits of a short DA, DA(15-4) are 1, the last 4 bits of the DA, DA(3-0),
are used as an index into FGM.
The 4-bit index into FGM can be viewed in two different ways. It can be viewed as 4 bits selecting one of 16 bits where the
hexidecimal equivalent of DA(3-0) can be used as the index. For example the broadcast address would index FGM(F). Alternatively it can be viewed as one bit, DA(3), selecting the byte (FGMO or FGM1) and three bits, DA(2-0) selecting one of 8 bits
within a byte.
ACCESS RULES
Address

Read

Write

58-59h

Stop Mode

Stop Mode

FGMO
FGM1
Note: Bit FGM(F) must be set to One to ensure proper handling of frames with the Universal/Broadcast address including the SMT NSA frames. This is mandatory
for interoperability on an FOOl Ring.

2-182

C

6.0 Control Information

"'a

co

(Continued)

Co)

N

Programmable Group Address MAP (PGMO-PGM1F)

0)

If the first 40 bits of a long DA, DA(47-8), match the GLA or if the first 8 bits of a short DA, DA(15-8), match the GSA, the last 8
bits of the DA are used as an index into PGM.
The 8-bit index into PGM can be viewed in two different ways.
1. As B bits selecting one of 256 bits where the hexidecimal equivalent of DA(7 -0) can be used as the index. For example a DA
with the last byte as A2h indexes PGM(A2).
2. As 5 bits, DA(7-3), selecting the byte (PGMO to PGM1F) and three bits, DA(2-0) selecting one of B bits within a byte. For
example a DA with the last byte of A2h (10100010b) selects PGM14 bit 2.
It is possible to disable Long and Short Group Addressing by filling the Group Address Map with O's.
In REV 1 of the BMAC device, PGM(OO) to PGM(7F) are hardwired to 0 and are not accessible via the Control Interface. This
implies that group addresses with DA(7) = 0 can not be recognized.
In REV 2 of the BMAC device, PGM(OO) to PGM(7F) are set equal to PGM(BO) to PGM(FF) and are accessible via the Control
Interface. This implies that DA(7) of group addresses is a don't care.
ACCESS RULES
Address

Read

Write

70-7Fh

Stop Mode

Stop Mode

PGMO

07

06

05

04

03

02

01

DO

PGM(7)

PGM(6)

PGM(5)

PGM(4)

PGM(3)

PGM(2)

PGM(1)

PGM(O)

PGM1

PGM(F)

PGM(E)

PGM(D)

PGM(C)

PGM(B)

PGM(A)

PGM(9)

PGM(8)

PGM2

PGM(17)

PGM(16)

PGM(15)

PGM(14)

PGM(13)

PGM(12)

PGM(11)

PGM(10)

PGM3

PGM(1F)

PGM(1E)

PGM(1D)

PGM(1C)

PGM(1B)

PGM(1A)

PGM(19)

PGM(18)

PGM4

PGM(27)

PGM(26)

PGM(25)

PGM(24)

PGM(23)

PGM(22)

PGM(21)

PGM(20)

PGM5

PGM(2F)

PGM(2E)

PGM(2D)

PGM(2C)

PGM(2B)

PGM(2A)

PGM(29)

PGM(28)

PGM6

PGM(37)

PGM(36)

PGM(35)

PGM(34)

PGM(33)

PGM(32)

PGM(31)

PGM(30)

PGM7

PGM(3F)

PGM(3E)

PGM(3D)

PGM(3C)

PGM(3B)

PGM(3A)

PGM(39)

PGM(38)

PGM8

PGM(47)

PGM(46)

PGM(45)

PGM(44)

PGM(43)

PGM(42)

PGM(41)

PGM(40)

PGM9

PGM(4F)

PGM(4E)

PGM(4D)

PGM(4C)

PGM(4B)

PGM(4A)

PGM(49)

PGM(4B)

PGMA

PGM(57)

PGM(56)

PGM(55)

PGM(54)

PGM(53)

PGM(52)

PGM(51)

PGM(50)

PGMB

PGM(5F)

PGM(5E)

PGM(5D)

PGM(5C)

PGM(5B)

PGM(5A)

PGM(59)

PGM(58)

PGMC

PGM(67)

PGM(66)

PGM(65)

PGM(64)

PGM(63)

PGM(62)

PGM(61)

PGM(60)

PGMO

PGM(6F)

PGM(6E)

PGM(6D)

PGM(6C)

PGM(6B)

PGM(6A)

PGM(69)

PGM(68)

PGME

PGM(77)

PGM(76)

PGM(75)

PGM(74)

PGM(73)

PGM(72)

PGM(71)

PGM(70)

PGMF

PGM(7F)

PGM(7E)

PGM(7D)

PGM(7C)

PGM(7B)

PGM(7A)

PGM(79)

PGM(78)

2-183

......

_,-------------------------------------------------------------------------,

re

CO)

CD

a.
C

6.0 Control Information (Continued)
Programmable Group Address MAP (PGMO-PGM1F) (Continued)
ACCESS RULES
Address

Read

Write

60-6Fh

Stop Mode

Stop Mode

07

06

05

04

03

02

01

00

PGM10

PGM(B7)

PGM(B6)

PGM(B5)

PGM(B4)

PGM(B3)

PGM(B2)

PGM(B1)

PGM(BO)

PGM11

PGM(BF)

PGM(BE)

PGM(BD)

PGM(BC)

PGM(BB)

PGM(BA)

PGM(B9)

PGM(BB)

PGM12

PGM(97)

PGM(96)

PGM(95)

PGM(94)

PGM(93)

PGM(92)

PGM(91)

PGM(90)

PGM13

PGM(9F)

PGM(9E)

PGM(9D)

PGM(9C)

PGM(9B)

PGM(9A)

PGM(99)

PGM(9B)

PGM14

PGM(A7)

PGM(A6)

PGM(A5)

PGM(A4)

PGM(A3)

PGM(A2)

PGM(A1)

PGM(AO)

PGM15

PGM(AF)

PGM(AE)

PGM(AD)

PGM(AC)

PGM(AB)

PGM(AA)

PGM(A9)

PGM(AB)

PGM16

PGM(B7)

PGM(B6)

PGM(B5)

PGM(B4)

PGM(B3)

PGM(B2)

PGM(B1)

PGM(BO)

PGM17

PGM(BF)

PGM(BE)

PGM(BD)

PGM(BC)

PGM(BB)

PGM(BA)

PGM(B9)

PGM(BB)

PGM18

PGM(C7)

PGM(C6)

PGM(C5)

PGM(C4)

PGM(C3)

PGM(C2)

PGM(C1)

PGM(CO)

PGM19

PGM(CF)

PGM(CE)

PGM(CD)

PGM(CC)

PGM(CB)

PGM(CA)

PGM(C9)

PGM(CB)

PGM1A

PGM(D7)

PGM(D6)

PGM(D5)

PGM(D4)

PGM(D3)

PGM(D2)

PGM(D1)

PGM(DO)

PGM1B

PGM(DF)

PGM(DE)

PGM(DD)

PGM(DC)

PGM(DB)

PGM(DA)

PGM(D9)

PGM(DB)

PGM1C

PGM(E7)

PGM(E6)

PGM(E5)

PGM(E4)

PGM(E3)

PGM(E2)

PGM(E1)

PGM(EO)

PGM10

PGM(EF)

PGM(EE)

PGM(ED)

PGM(EC)

PGM(EB)

PGM(EA)

PGM(E9)

PGM(EB)

PGM1E

PGM(F7)

PGM(F6)

PGM(F5)

PGM(F4)

PGM(F3)

PGM(F2)

PGM(F1)

PGM(FO)

PGM1F

PGM(FF)

PGM(FE)

PGM(FD)

PGM(FC)

PGM(FB)

PGM(FA)

PGM(F9)

PGM(FB)

2-184

6.0 Control Information (Continued)
6.5.3 Claim Information: Requested Target Token Rotation Time (TREQ)
The Requested Target Token Rotation Time (TREQ) is stored in registers TREQO-TREQ3. TREQ(31-0) is represented as a
negative two's complement number. This value is transmitted in all Claim frames generated by the Ring Engine.
Bits TREQ(31-24) are always transmitted as and compared with FFh and bits TREQ(7-0) are always transmitted as and
compared with OOh, independent of the value stored in the MAC Parameter RAM. TREQ is therefore programmable with
20.48 p.s resolution and a maximum value of 1.34 seconds.
ACCESS RULES
Address

Read

Write

50-53h

Stop Mode

Stop Mode

07

06

05

04

03

02

01

DO

TREQO

TREQ(31)

TREQ(30)

TREQ(29)

TREQ(28)

TREQ(27)

TREQ(26)

TREQ(25)

TREQ(24)

TREQ1

TREQ(23)

TREQ(22)

TREQ(21)

TREQ(20)

TREQ(19)

TREQ(18)

TREQ(17)

TREQ(16)

TREQ2

TREQ(15)

TREQ(14)

TREQ(13)

TREQ(12)

TREQ(11)

TREQ(10)

TREQ(9)

TREQ(8)

TREQ3

TREQ(7)

TREQ(6)

TREQ(5)

TREQ(4)

TREQ(3)

TREQ(2)

TREQ(1)

TREQ(O)

6.5.4 Beacon Information: Transmit Beacon Type (TBT)
Transmit Beacon Type 0-3 (TBTO-3) represents the Transmit Beacon Type to be transmitted in the information field of a
Beacon frame.
When the Beacon state is reached as a result of a failed Claim process, the first byte of the Beacon Information field, bits
TBT31-24, are forced to Zero to produce a Beacon Type 0 as required by the MAC Standard. Bits TBT(23-0) are transmitted
as the rest of the Information field.
When the Beacon state is reached as a result of a Beacon Request (when Function.BCN is set), bits TBT(31-0) are transmitted
as the Information field. Bit TBT(O) is transmitted last.
ACCESS RULES
Address

Read

Write

54-57h

Stop Mode

Stop Mode

07

06

05

04

03

02

01

DO

TBTO

TBT(31)

TBT(30)

TBT(29)

TBT(28)

TBT(27)

TBT(26)

TBT(25)

TBT(24)

TBT1

TBT(23)

TBT(22)

TBT(21)

TBT(20)

TBT(19)

TBT(18)

TBT(17)

TBT(16)

TBT2

TBT(15)

TBT(14)

TBT(13)

TBT(12)

TBT(11)

TBT(10)

TBT(9)

TBT(8)

TBT3

TBT(7)

TBT(6)

TBT(5)

TBT(4)

TBT(3)

TBT(2)

TBT(1)

TBT(O)

•
2·185

9-

~
co
CO)

a.
C

.-----------------------------------------------------------------------------------------~

6.0 Control Information (Continued)
6.6 TIMER VALUES
The Ring Engine stores several timer values and thresholds used in normal operation. With the exception of TNEG. the timers
use an exponential expansion on a 4·bit value to produce a negative twos complement 24·bit value used by the Timer Logic.
The timer values are always readable and are writable in Stop Mode.
Asynchronous Priority Threshold (THSH1)
The Ring Engine currently supports one Asynchronous Priority Threshold (THSH1) in addition to the one at TTRT. The Asynchronous Priority Threshold is used in a magnitude comparison with THT when an Asynchronous Priority Request is presented
to the MAC Request Interface.
Bits 7-4 are always written to Zero and are always read as Zero.
When more than one threshold is used, the users of THSH1 have the lowest priority. All asynchronous transmissions are limited
by TTRT. If the Late Flag is set, no frames may be transmitted, regardless of the value of the Asynchronous Priority Threshold.
ACCESS RULES
. Address
87h

THSH1

Read

Write

Always

Stop Mode

I

07

06

05

04

03

02

01

00

Zero

Zero

Zero

Zero

THSH(3)

THSH(2)

THSH(1)

THSH(O)

THSH1(3-0)

Time remaining In THT
when token becomes unusable

0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F

10.24/-f.S
20.48/Ls
40.96/Ls
81.92/Ls
163.84/Ls
327.68/Ls
655.36/Ls
1.3107ms
2.6214ms
5.2429ms
10.486 ms
20.972 ms
41.943 ms (default)
83.886ms
167.77 ms
335.54ms

Warning: The default value may not be appropriate for aU values of TNEG.
In some cases, this could result in a request that is NEVER serviced.

2-186

6.0 Control Information (Continued)
Maximum Token Rotation Time (TMAX)
The Maximum Token Rotation Time (TMAX) denotes the maximum Target Token Rotation Time supported by this station.
TMAX is stored as a 4·bit value that is expanded to a binary exponential value. Bits 7-4 are ignored during write operations and
are always read as Zero.
TMAX has a maximum value of 1.34 seconds with a threshold of 40.96 x 2TMAX p,s. On a Master Reset (Function.MARST set
to One), TMAX is set to the value of Ch which corresponds to 167.772 ms, the default specified by the FOOl MAC Standard.
ACCESS RULES
Address
93h

TMAX

Read

Write

Always

Stop Mode

07

06

05

04

03

02

01

DO

Zero

Zero

Zero

Zero

TMAX(3)

TMAX(2)

TMAX(1)

TMAX(O)

TMAX(O-3)
0
1
2
3
4
5
6
7
8
9
A
B
C

0
E
F

Time

40.96 p,s
81.92 p,s
163.84 p,s
327.68 p,s
655.36 p,s
1.3107 ms
2.6214 ms
5.2429ms
10.486 ms
20.972ms
41.943 ms
83.886ms
167.77 ms (default)
335.54ms
671.09 ms
1.3422s

fI

2·187

~

!j
~

c

r---------------------------------------------------------------------------------,
6.0 Control Information (Continued)
Valid Transmission Time (TVX)
The Valid Transmission Timer (TVX) is used to increase the responsiveness of the ring to errors that cause ring recovery. The
TVX value denotes the maximum time in which a valid frame or token should be seen by this station. TVX is stored as a 4-bit
value that is expanded to a binary exponential value. Bits 7-4 are ignored during write operations and read as Zero ..
TVX has a maximum value of 1.34 seconds with a threshold of 40.96 X 2TVX p.s. On a Master Reset (Function.MARST is set to
One), TVX is set to the value of 6h which corresponds to 2.62 ms, the default by the FOOl MAC Standard.
ACCESS RULES
Address

Read

Write

97h

Always

Stop Mode

TVX

07

06

05

04

03

02

01

00

Zero

Zero

Zero

Zero

TVX(3)

TVX(2)

TVX(1)

TVX(O)

TVX(O-3)

Time

0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F

40.96 p.s
81.92 p.s
163.84 p.s
327.68 p.s
655.36 p.s
1.3107 ms
2.6214 ms (default)
5.2429ms
10.486ms
20.972ms
41.943ms
83.886ms
167.77ms
335.54ms
671.09ms
1.3422s

2-188

6.0 Control Information (Continued)
Negotiated Target Rotation Time (TNEG)
The Negotiated Target Rotation Time (TNEGO-3) is a 32·bit twos complement value. It is the result of the Claim Process. TNEG
is loaded either directly from the received Claim Information field (T_Bid-Rc) or via the Control Interface.
The first byte of TNEG (bits TNEG(31-24)) always contains FFh. TNEG has a maximum value of 1.34 seconds and a resolution
of 80 ns.
TRT is loaded with TNEG when the RinQ-Operational flag is set. TNEG is not automatically compared with TREQ when the
RinQ-Operational flag is set. This should be checked by software whenever the ring becomes operational to make sure that
TNEG is less than or equal to TREQ.
An implementation of the SM_Control.Request (Reset) should load TNEG with TMAX to remove any possibility of the station
entering Claim early.
On a Master Reset (Function.MARST is set), TNEG is set to FFEOOOOO, which corresponds to 167.772 ms, the default TMAX
specified by the FDDI MAC Standard.
ACCESS RULES
Address

Read

Write

98-9Bh

Always

Stop Mode

D7

D6

DS

D4

D3

D2

D1

DO

TNEGO

TNEG(31)

TNEG(30)

TNEG(29)

TNEG(28)

TNEG(27)

TNEG(26)

TNEG(25)

TNEG(24)

TNEG1

TNEG(23)

TNEG(22)

TNEG(21)

TNEG(20)

TNEG(19)

TNEG(18)

TNEG(17)

TNEG(16)

TNEG2

TNEG(15)

TNEG(14)

TNEG(13)

TNEG(12)

TNEG(11)

TNEG(10)

TNEG(9)

TNEG(8)

TNEG3

TNEG(7)

TNEG(6)

TNEG(5)

TNEG(4)

TNEG(3)

TNEG(2)

TNEG(1)

TNEG(O)

EI

2·189

~

~
co
CO)

a.
C

,-----------------------------------------------------------------------------------------,
6.0 Control Information (Continued)
6.7 EVENT COUNTERS
The Event Counters are used to gain access to the internal 20·bit counters u'sed to gather statistics.
The following event counters are included:
• Frame Received Counter (FRCT1-3)
• Error Isolated Counter (EICT1-3)
• Lost Frame Counter (LFCT1-3)
• Frame Copied Counter (FCCT1-3)
• Frame Not Copied Counter (FNCT1-3)
• Frame Transmitted Counter (FTCT1-3)
• Token Received Counter (TKCT1-3)
• Ring Latency Counter (RLCT1-3)
• Late Count Counter (LTCT)
6.7.1 Processing Procedures
The counters are 20·bit wrap·around counters except for the Late Count Counter which is a 4·bit sticky counter (see Figure 6·2).
Since the Control Bus Interface is an a·bit interface and the counters are 20·bits wide, a register holding scheme is implement·
ed. In order to provide a conSistent snapshot of a counter, while the least significant byte is read, the upper 12 bits are loaded
into a holding which can then be read. The least significant byte must be read first.
The Counters are always readable and are writable in Stop Mode., The Counters are not reset as a result of a Master Reset. This
may be done by either reading the Counters out and keeping track relative to the initial value read, or by writing a value (Zero) to
all of the Counters in Stop Mode. The Counters may be written in any order. Interrupts may be requested when the counters
increment (except for Ring Latency Counter) or wrap·around (except for Ring Latency Counter and Late Count Counter).

..

..
..
""

FRRCV

Overflow

Increment

FRRCV

..

FREI

Overflow

Increment

FREI

.c

FRlST

Overflow

Increment

FRlST

~

FRCOP

Overflow

Increment

FRCOP

1:

'E
!I!
0

.
.s

FRNCOP

Overflow

Increment

FRNCOP

c

FRTRX

Overflow

Increment

FRTRX

.
1l

TKRCVD

Overflow

Increment

TKRCVD

il.,.
""u
:3

.3"

il.,.
.c

~

..

E
~
u

.E

.3"

START RING LATENCY
l TCT Increment

Holding

Regr-l~st-ers--...,..--L---.---....I.---.,

Counters Must be Read In this order (3,2, 1)
TLlF/10387-10

FIGURE 6·2. Event Counters

2·190

r----------------------------------------------------------------------, C

~

6.0 Control Information (Continued)

Co)

Frame Received Counter (FRCn
The Frame Received Counter (FRCn is specified in the FDDI MAC Standard. It is the count of all complete frames received
including MAC frames, Void frames and frames stripped by this station.
Interrupts are available on increment (CILR.FRRCV) and when the 20-bit counter overflows and wraps around (COLR.FRRCV).
ACCESS RULES
Address

Read

Write

AO-A3h

Always

Stop Mode

07

06

05

04

03

02

01

00

FRCTO

Zero

Zero

Zero

Zero

Zero

Zero

Zero

Zero

FRCT1

Zero

Zero

Zero

Zero

CT(19)

CT(18)

CT(17)

CT(16)

FRCT2

CT(lS)

CT(14)

CT(13)

CT(12)

CT(ll)

CT(10)

CT(9)

CT(8)

FRCT3

CT(7)

CT(6)

CT(S)

CT(4)

CT(3)

CT(2)

CT(l)

CT(O)

2-191

...
N

Q)

.-

I
Q

,---------------------------------------------------------------------------------,
6.0 Control Information (Continued)
Error Isolated Counter (EICT)
The Error Isolated Counter (EICn is specified in the FOOl MAC Standard. It is the count of aU error frames detected by this
station and no previous station.
It is incremented when:
1) an FCS error is detected and the received Error Indicator (Er) is not equal to S; or
2) a frame of invalid length (i.e., off-boundary n is received and Er is not equal to S; or
3) Eris not R orS
Interrupts are available on increment (CILR.FREI) and when the 20-bit counter overflows and wraps around (COLR.FREI).
ACCESS RULES
Address

Read

WrIte

A4-A7h

Always

Stop Mode

02

07

06

05

EICTO

Zero

Zero

Zero

Zero

Zero

Zero

Zero

Zero

EICT1

Zero

Zero

Zero

Zero

CT(19)

CT(18)

CT(17)

CT(16)

EICT2

CT(15)

CT(14)

CT(13)

CT(12)

CT(11)

CT(10)

CT(9)

CT(8)

EICT3

CT(7)

CT(6)

CT(5)

CT(4)

CT(3)

CT(2)

CT(1)

CT(O)

D4

2-192

03

01

00

6.0 Control Information (Continued)
Lost Frame Counter (LFCn
The Lost Frame Counter (LFCT) is specified in the FDDI MAC Standard. It is the count of all instances where a Format Error is
detected in a frame or token such that the credibility of the PDU reception is in doubt.
The Lost Frame Counter is incremented when any symbol other than a data or Idle symbol is received between the Starting and
Ending Delimiters of a PDU (this includes parity errors).
Interrupts are available on increment (CILR.FRLST) and when the 20·bit counter overflows and wraps around (COLR.FRLST).
ACCESS RULES
Address

Read

Write

AS-ABh

Always

Stop Mode

07

06

05

04

03

02

01

00

LFCTO

Zero

Zero

Zero

Zero

Zero

Zero

Zero

Zero

LFCT1

Zero

Zero

Zero

Zero

CT(19)

CT(1S)

CT(17)

CT(16)

LFCT2

CT(15)

CT(14)

CT(13)

CT(12)

CT(11)

CT(10)

CT(9)

CT(S)

LFCT3

CT(7)

CT(6)

CT(5)

CT(4)

CT(3)

CT(2)

CT(1)

CT(O)

In REV 1 of the BMAC device the Lost Count includes frames stripped on an ODD symbol boundary. This may cause larger than
expected counts in Rings where an upstream station produces valid remnants that begin on an ODD symbol boundary. (The
Ring Engine converts these remnants to byte aligned remnants, so that only the downstream station would increment its Lost
Count.) In subsequent revisions remnants that begin on an odd symbol boundary are not considered lost frames and do not
cause the Lost Count to increment.

2·193

...

re

Cf)

co
a,. ,
C

.---------~--------------------~--------~------------------------------------------,

6.0 Control Information (Continued)
Frame Copied Counter (FCCT)
The Frame Copied Counter (FCCT) maintains the count of the number of frames successfully copied by this station. This
counter can be used to accumulate station performance statistics.
The Frame Copied Counter is incremented when an internal or external match occurs on the Destination Address, no errors
were detected in the frame, and the frame was successfully copied (VCOPY signal is asserted). Copied MAC and Void frames
are not included in this count.
For 8MT N8A frames, the Frame Copied Count only increments for N8A frames received with the A Indicator as an R symbol for
which the frame was copied. 8MT N8A frames received with the A Indicator as an 8 do not cause this count to increment, even
if the frame is successfully copied.
Increments are available on increment (CILR.FRCOP) and when the 20-bit counter overflows and wraps around
(COLR.FRCOP).
ACCESS RULES
Address

Read

Write

AC-AFh

Always

Stop Mode

07

06

05

04

03

02

01

00

FCCTO

Zero

Zero

Zero

Zero

Zero

Zero

Zero

Zero

FCCT1

Zero

Zero

Zero

Zero

CT(19)

CT(18)

CT(17)

CT(16)

FCCT2

CT(15)

'CT(14)

CT(13)

CT(12)

CT(II)

CT(10)

CT(9)

CT(8)

FCCT3

CT(7)

CT(6)

CT(5)

CT(4)

CT(3)

CT(2)

CT(I)

CT(O)

2-194

6.0 Control Information (Continued)
Frame Not Copied Counter (FNCT)
The Frame Not Copied Counter (FNCn maintains a count of the number of frames intended for this station that were not
successfully copied by this station. This count can be used to accumulate station performance statistics such as insufficient
buffering or deficient frame processing capabilities for frames addressed to this station.
The Frame Not Copied Counter is incremented when an internal or external match (when Option.EMIND enabled) occurs on the
Destination Address, no errors were detected in the frame, and the frame was not successfully copied (VCOPV Signal not
.
asserted). Not Copied MAC frames and Void frames are not included in this count.
Interrupts are available on increment (CILR.FRNCOP) and when the 20-bit counter overflows and wraps around
(COLR.FRNCOP).
ACCESS RULES
Address

Read

Write

BO-BSh

Always

Stop Mode

FNCTO

07

06

05

04

03

02

01

DO

Zero

Zero

Zero

Zero

Zero

Zero

Zero

Zero

FNCT1

Zero

Zero

Zero

Zero

CT(19)

CT(1B)

CT(17)

CT(16)

FNCT2

CT(15)

CT(14)

CT(1S)

CT(12)

CT(11)

CT(10)

CT(9)

CT(B)

FNCT3

CT(7)

CT(6)

CT(5)

CT(4)

CT(S)

CT(2)

CT(1)

CT(O)

In REV 1 of the BMAC device, the Frame Not Copied Counter does increment for all NSA frames received with the A indicator
as an S symbol, if it was copied or not. This will result in higher than expected values in the Not Copied Counter. To obtain a
more accurate value with REV 1 of the BMAC device, the number of copied NSA frames received with the A Indicator set should
be subtracted from the value in the Not Copied Counter.
In subsequent revisions of the BMAC device, NSA frames received with the A Indicator as S that are not copied will not be
counted.
In REV 2 the handling of SMT NSA has been modified in accordance with the MAC-2 Draft Standard. For SMT NSA frames, the
Frame Not Copied Count only increments for NSA frames received with the A Indicator as an R symbol for which the frame was
not copied. SMT NSA frames received with the A Indicator as an S do not cause this count to increment, even if the frame is not
successfully copied. Group addressed frames transmitted by this station and recognized by this station that are not copied will
also cause this counter to increment.

2-195

,.. r---------------------------------------------------------------------------------,
~

f
c

6.0 Control Information (Continued)
Frame Transmitted Counter (FTCT)
The Frame Transmitted Counter (FTCT) maintains the count of frames transmitted successfully by this station. The counter can
be used to accumulate station performance statistics.
The Frame Transmitted Counter is incremented everY time a complete frame is transmitted from the MAC Request Interface.
MAC'and Void frames generated by the Ring Engine are not included in the count.
Interrupts are available on increment (CILR.FRTRX) and when the 20·bit counter overflows and wraps around (COLR.FRTRX).
ACCESS RULES
Address

Read

Write

B4-B7h

Always

Stop Mode

FTCTO

07

06

05

04

03

02

01

00

Zero

Zero

Zero

Zero

Zero

Zero

Zero

Zero
CT(16)

FTCT1

Zero

Zero

Zero

Zero

CT(19)

CT(1B)

CT(17)

FTCT2

CT(15)

CT(14)

CT(13)

CT(12)

CT(11)

CT(10)

CT(9)

CT(8)

FTCT3

CT(7)

CT(6)

CT(5)

CT(4)

CT(3)

CT(2)

CT(1)

CT(O)

2·196

.----------------------------------------------------------------------.0
;g

6.0 Control Information (Continued)

w

Token Received Counter (TKCT)
The Token Received Counter (TKCn maintains the count of valid tokens received by·this station. The counter can be used with
the Ring Latency Counter to calculate the average network load over a period of time. The frequency of token arrival is inversely
related to the network load.

....~

The Token Received Counter is incremented every time a valid token arrives.
Interrupts are available on increment (CILR.TKRCVD) and when the 20-bit counter overflows and wraps around
(COLR.TKRCVD).

ACCESS RULES
Address

Read

Write

BS-BBh

Always

Stop Mode

TKCTO

07

06

05

04

03

02

01

00

Zero

Zero

Zero

Zero

Zero

Zero

Zero

Zero

TKCT1

Zero

Zero

Zero

Zero

CT(19)

CT(1S)

CT(17)

CT(16)

TKCT2

CT(lS)

CT(14)

CT(13)

CT(12)

CT(1l)

CT(10)

CT(9)

CT(S)

TKCT3

CT(7)

CT(6)

CT(S)

CT(4)

CT(3)

CT(2)

CT(l)

CT(O)

fII

2-197

.- r------------------------------------------------------------------------------------------,

CD
C"I

Cf)

CO

a.
C

6.0 Control Information (Continued)
Ring Latency Counter (RLCT)
The Ring Latency Counter (RLCT) is a measurement of time for PDUs to propagate around the ring. This counter contains the
last measured ring latency whenever the RLVD bit of the Token and Timer Event Latch Register (TELR.RLVD) is One.
The current ring latency is measured by timing the propagation of a My_Void frame around the ring. A new latency measurement can be requested by clearing the Ring Latency Valid bit of the Token Event Register (TELR.RLVLD).
When the ring is operational, the next early token is captured. Before the token is re-issued, a My_Void frame is transmitted and
the Ring Latency Counter (RLCn is reset. The token will not be captured if the Inhibit Token Option (Option.ITG) is set and the
ring latency will not be measured.
When the ring is not operational, ring latency timing will commence at the end of the next immediate request. A My_Void is
transmitted and RLCT is reset. This could be used to time how long the ring is non-operational since the My_Void frame will not
return.
The Ring Latency Counter increments once every 6 byte times from when the Ending Delimiter of the My_Void frame is
transmitted, until the Ending Delimiter of the My_Void frame returns. When the My_Void frame returns, the ring latency valid bit
(TELR.RLVLD) is set and may cause an interrupt. When set, RELR.RLVLD indicates that RLCTwili be valid within 1.28I£s. The
Ring Latency Counter can measure ring latencies up to I.S421772 seconds with accuracy of 1.28 I£s.
The ring latency timing function is automatically disabled when exceptions are detected and retried at the next opportunity.
Since a Master Reset (Function.MARSn causes TELR.RLVLD to be cleared, the ring latency will automatically be measured on
the first opportunity (at the end of the first immediate request or with the first early token).

ACCESS RULES
Address

Write

Read

BC-BFh,

Always

Stop Mode

07

06

05

04

RLCTO

Zero

Zero

Zero

Zero

Zero

Zero

Zero

Zero

RLCTI

Zero

Zero

Zero

Zero

CT(19)

CT(18)

CT(17)

CT(16)

RLCT2

CT(15)

CT(14)

CT(IS)

CT(12)

CT(II)

CT(10)

CT(9)

CT(8)

RLCT3

CT(7)

CT(6)

CT(5)

CT(4)

CT(S)

CT(2)

CT(I)

CT(O)

03

02

01

00

In REV 1 of the BMAC device, the Latency Counter is not reset to Zero when a new latency measurement is initiated. The
latency count will be the difference between the value of RLCT after the measurement is complete and the value of RLCT
before the measurement was initiated.
If a new latency measurement causes the latency counter to overflow, the new latency value will be less than the previous value.
In this case, no subtraction is necessary. The new value is equal to the ring latency. This is because the Ring Engine recognizes
the overflow condition and restarts the latency count from zero.
It is not possible to reset the Latency counter in software once the BMAC device has been put into RUN mode (Mode. Run = 1).
This counter is only writable while in STOP mode (Mode. Run = 0).

2-198

C

"tJ

co
Co)

6.0 Control Information (Continued)

N

Late Count (LTCT)

Late Count is provided to assist Station Management in the isolation of serious ring errors. In many situations, it is helpful for
SMT to know how long it has been since the ring went non-operational in order to determine if it is necessary to invoke recovery
procedures. When the ring becomes non-operational, there is no way to know how long it will stay non-operational, therefore a
timer is necessary. If the Late Count Counter is not provided, SMT would be forced to start a timer every time the ring goes nonoperational even though it may seldom be used. By using the provided Late Count Counter, an SMT implementation may be able
to alleviate this additional overhead.
Late Count is incremented every time TRT expires while the ring is non-operational and Late_Flag is set (once every TMAX).
This counter is never writable, not even in Stop Mode. The counter is set to Zero as a result of a MAC Reset when a Beacon or
Claim Request is not also present (Function.MCRST is set and Function.BCN and Function.CLM are not set) and every time the
ring becomes non-operational. The Late Count Counter is a sticky counter at 15.
Events reported in the Token and Timer Event Latch Register (TELR.CBERR, TELR.TRTEXP) can be used to determine that
Late Count Counter has incremented. No overflow event is provided.
ACCESS RULES
Address

Read

Write

OFh

Always

n/a

LTCT

....
Q)

The Late Count Counter (LTCn is implemented differently than suggested by the FDDI MAC Standard, but provides similar
information. The function of the Late Count Counter is divided between the Late_Flag and a separate counter. The Late_Flag
is equivalent to the Standard Late Count with a non-zero value. It is maintained by the Ring Engine to indicate if it is possible to
send asynchronous traffic. When the ring is operational, Late Count indicates the time it took the ring to recover the last time the
ring went non-operational. When the ring is non-operational, Late Count indicates the time it has taken (so far) to recover the
ring.

07

06

05

04

03

02

01

DO

Zero

Zero

Zero

Zero

CT3

CT2

CT1

CTO

2-199

I
Q

7.0 Signal Descriptions
Interface Organization
The BMAC device signals are organized into five Interfaces:
Control Interface: Used for processor access to the BMAC device.
PHY Interface: Interface signals to the DP83251 155 PLAYER device.
MAC Indicate Interface: Signals for receiving and processing incoming frames.
MAC Request Interface: Signals used to capture tokens and transmit frames.
Electrical Interface: Signals associated with power supply and clocking.
Application Note 689, BMAC Device Hardware Design Guide, provides a discussion of design considerations and tradeoffs for
using the BMAC Device.
7.1 CONTROL INTERFACE
The Control Interface operates asynchronous to the operation of the data services. During an access, the external Control Bus
is synchronized with the internal Control Bus.
The ACK and INT signals are open drain signals to allow wire ORing several such signals.
Symbol

Pin #

1/0

Description

10

110

Control BU8 Parity: Odd parity on CBD7 -0.

CBD7-0

9-6,3-1,
132

110

Control BU8 Data

CBA7-0

131-129,
127-123

I

Control BU8 Addre..: Address of a particular register.

~

120

I

Control BU8 Enable: Handshake signal used to begin a Control Interface access. Active low signal.

R/W

119

I

Read/- Write: Determines current direction of a Control Interface access.

AOR

122

00

- Acknowledge: Acknowledges that the Control Interface access has been performed. Active low,
open drain signal.

!NT

121

00

-Interrupt: Indicates presence of one or more enabled condition(s) from the Event Registers.
Active low, open drain Signal.

CBP

2-200

7.0 Signal Descriptions (Continued)
7.2 PHY INTERFACE
The PHY Interface signals transfer symbol pairs between the BMAC and PLAYER devices. Transfers are synchronous using the
12.5 MHz Local Byte Clock signal (signal provided by the Clock Distribution Device).
A control bit is used to indicate if a Data symbol pair or Control symbol pair or a mixed Control/Data symbol pair are being
transferred.
Parity is generated on the PHY_Indicate and MA....Jndicate data. Parity is checked on the PHY_Request and MA-Request
data.
Pin #

I/O

PRP

114

0

PHY Request Parity: Odd parity for PRC and PRD7 -0.

PRC

112

0

PHY Request Control:

Symbol

Description

0: Indicates PRD7 -0 contains a Data symbol pair.
1: Indicates PRD7 -0 contains a Control or mixed Control/Data symbol pair.
PRD7-0

110,108,
105, 103,
99,97,
95,92

0

PHY Request Data: Contains a Data or Control symbol pair.

PIP

115

I

PHY Indicate Parity: Odd parity for PIC and PID7 -0.

PIC

113

I

PHY Indicate Control:
0: Indicates PID7 -0 contains a Data symbol pair.
1: Indicates PID7 -0 contains a Control or mixed Control/Data symbol pair.

PID7-0

111,109,
107,104,
102,98,
96,93

I

PHY Indicate Data: Contains a Data or a mixed Control/Data symbol pair.

fII

2·201

~

~

ell)

~

Q

r-------------------------------------------------------------------------------------,
7.0 Signal Descriptions (Continued)
7.2.1 PHY Interface Codes
The DPB3251/155 PLAYER device converts the Standard 4B/5B FDDI symbol code to the internal code used at the PHY
Interface. The PH_DATA.lndication table shows how the Ring Engine interprets the codes generated by the PLAYER device
and the PH-DATA. Request table shows the codes generated by the Ring Engine.
The internal code is actually an BB/9B code with parity where one bit is used to determine whether the symbol pair contains two
data symbols or at least one control. symbol.
PH-DATA.lndlcatlon
The Ring Engine interprets the byte stream the PLAYER device as defined in Table 7·1.
TABLE 7-1. Internal PHY Indicate Coding
PIP

PIC

PID(7-4)

PID(3-0)

Type

0

1

0

0000

0000

Data Symbol Pair
Data Symbol Pair

Value

where:
PIP

1

0

0

0000

0001

:

:

:

:

:

254

0

0

1111

1110

255

1

0

1111

1111

Data Symbol Pair

JK

P

1

1101

xxxx

Start Delimiter

PI

P

1

x011

x1xx

PH_Invalid

PI

P

1

x011

xx1x

PH_Invalid

II

P

1

10xx

xxxx

Idle Symbols

:
Data Symbol Pair

nl

P

1

0000

10xx

Data/Idle Symbol

RR

P

1

0110

0110

Frame Status

RS

P

1

0110

0111

Frame Status

RT

P

1

0110

0101

Frame Status

SS

P

1

0111

0111

Frame Status

SR

P

1

0111

0110

Frame Status

ST

P

1

0111

0101

Frame Status

SX

P

1

0111

xxxx

Frame Status

TX

P

1

0101

xxxx

Ending Delimiter

TR

P

1

0101

0110

Ending Delimiter

TS

P

1

0101

0111

Ending Delimiter
Ending Delimiter

TT

P

1

0101

0101

nT

P

1

0000

0101

Mixed Symbol Pair

Parity Error

-P

0

1??1

1111

Code Violation

Otherwise

1

1

Else

Code Violation

PHY Indicate Parity bit, ODD parity

PIC

PHY Indicate Control bit:
0= > data byte,
1 = >control/mixed byte
PID(7-0) PHY Indicate Data(7-0)
P

represents ODD Parity ( - P is Bad Parity)

x1

represents a don't care and is not decoded
represents a 1 or 0 but not both.

The PLAYER device aligns the received JK to a byte boundary. Thus, no provision is made in the internal code or by the Ring
Engine for off boundary JKs.
The Idle and PH_Invalid encodlngs overlap. Idle symbols received while the PLAYER device is in Active Line State (ALS) or Idle
Line State (ILS) are not considered PH_INVALID. Idle symbols received while the PLAYER device is in states other than ALS or
ILS are treated as PH_Invalid.

2·202

,----------------------------------------------------------------------, C

~

7.0 Signal Descriptions (Continued)

W
N

PH_OATA.Request
The Ring Engine generates the 10 bit byte stream as defined in Table 7-2. Note that all symbol pairs are either control or data
symbol pairs. Mixed data/control symbol pairs are never generated or repeated by the Ring Engine.
TABLE 7-2. Internal PHY Request Coding
Value

PRP

PRC

PRO(7-4)

PRO(3-0)

Type

0

1

0

0000

0000

Data Symbol Pair

1

0

0

0000

0001

Data Symbol Pair

:

:

:

:

:

:

254

0

0

1111

1110

Data Symbol Pair

255

1

0

1111

1111

Data Symbol Pair

JK

0

1

1101

1101

Start Delimiter

II

0

1

1010

1010

Idle Symbols

RR

0

1

0110

0110

Frame Status

RS

1

1

0110

0111

Frame Status

RT

0

1

0110

0101

Frame Status

SS

0

1

0111

0111

Frame Status

SR

1

1

0111

0110

Frame Status

ST

1

1

0111

0101

Frame Status

TR

0

1

0101

0110

Ending Delimiter

TS

1

1

0101

0111

Ending Delimiter

IT

0

1

0101

0101

Ending Delimiter

Where:
PRP
PRC

....
Q)

PHY Request Parity bit, parity for all symbol pairs is ODD
PHY Request control bit:
0= > data byte

1 = > control byte
PRD(7 -0) PHY Request Data (7-0)
The Ring Engine can repeat the RS, RT and ST symbol pairs but does not create them.

2-203

.- r-----------------------------------------------------------------------------------------,

re

CO)

CD

a.
C

7.0 Signal Descriptions (Continued)
7.3 MAC INDICATION INTERFACE
The MAC Indication Interface provides a delayed version of the byte stream presented to the Ring Engine at the PHY Indication
Interface. Every byte of all incoming frames is presented at the MAC Indication Interface. Every byte time (80 ns) one byte of
data with Odd parity is presented at the MAC Indication Interface. This byte stream is interpreted by the system interface logic
using the control signals that are provided in parallel with the byte stream. These control signals are used to determine frame
boundaries in the byte stream, determine whether or not to (continue to) copy a frame, and to provide status on received PDUs.
In the following sections, an overview of the signals is provided (Section 7.3.1) as well as a detailed explanation (Section 7.3.2)
with several example timing scenarios (Section 7.3.3).
7.3.1 Overview
The MAC Indication Interface is divided into one group of data signals and five groups of control signals.
The data signals consist of the 8 bits of MAC Indicate Data (MID) with parity.
The control signals consist of 5 groups:
• PDU Sequencing to aid in delimiting PDUs from the byte stream and sequencing through fields in the received PDUs.
• PDU Flags to aid in the decision of whether or not to continue to copy a PDU.
• Termination Event to determine when and how a PDU terminated.
• Termination Status to provide status on received frames.
• External Flags to allow external address comparison and copy information to be conveyed back to the Ring Engine.
The PDU Sequencing signals are asserted at different pOints within a PDU.
RCSTART when the Starting Delimiter is present on MID
FCRCVD

when the Frame Control Field is on MID

DARCVD

when the last byte of the DA is on MID until the next Starting Delimiter

SARCVD

when the last byte of the SA is on MID until the next Starting Delimiter

INFORCVD when the fourth byte of the info field is on MID until the next Starting Delimiter
Not all of the sequencing signals would be used in a typical implementation.
The PDU Flags provide the input for potential copy criteria and status breakpoints. The results of the comparisons between the
station's long or short address and the frame's source and destination addresses are provided in the AFLAG and MFLAG
signals. The sequencing information is used to determine when this information is valid. Since the Ring Engine is capable of
accomplishing four internal comparisons on any given frame, two signals give the internal comparison that was accomplished.
AFLAG

Internal DA Match. There are actually four AFLAGs as determined by the two signals: FCSL-Short/Long, DAIGIndividual/Group. Valid with DARCVD.

MFLAG

Internal SA Match. There are actually two MFLAGs as determined by the values of FCSL. Valid with SARCVD.

SAMESA

SA same as in previous frame. Valid with SARCVD on Non-MAC frames. Can be used by external logic to batch
status or reduce the number of interrupts when multiple frames are received from the same station.

SAMEINFO First four bytes of Info same as in previous frame. Valid with INFORCVD on MAC frames. Can be used to inhibit
copying of identical MAC frames.
No temporary buffering is provided in the Ring Engine. The system interface must provide this buffering while the decision is
made on whether or not to continue to copy the frame.
Termination Event: One of these signals is asserted at the end of every PDU:
EDRCVD

when the Ending Delimiter is on MID until the end of the Frame Status (typically asserted for two byte times)

TKRCVD

when the Ending Delimiter of a token is on MID

FRSTRP

when the first Idle byte of a stripped frame is on MID

FOERROR when the byte with the format error is on MID
MACRST

when a MACRST occurs or Ring Engine in Stop Mode

2-204

7.0 Signal Descriptions (Continued)
Termination Status: These signals provide status on reception of a valid ending delimiter on a frame.

VDL

Valid Data Length.
Criteria:
1. more than the minimum number bytes
2. integral number of symbol pairs.
Valid with EDRCVD

VFCS

Valid FCS Criteria: Received FCS matches with standard CRC polynomial.
Valid with EDRCVD

External Flags: These signals are used for setting the outgoing control indicators, the interface accepts:
EA
For external address matches for the setting of the A indicator (bridging, Group addressing, Aliasing)
VCOPY

For the setting of the C Indicator when AFLAG or EA is set.

•
2-205

7.0 Signal Descriptions (Continued)
7.3.2 Signals
All output signals change relative to the rising edge of the Local Byte Clock signal (provided by the Clock Distribution Device)
and are active high.
7.3.2.1 Indication Data
Symbol
MIP
MID7-0

Pin

;I'

Description

1/0

73

0

MAC Indicate Parity: Odd parity on MID7-0. Only valid with Data and Status Indicators.

74-76,
79-83

0

MAC Indicate Data:
Data: Indicates data is being presented on MID7 -0 between the rising edge of Frame Control Receive
FCRCVD and the rising edge of one of the following signals:
Ending Delimiter Received (EDRCVD),
Token Received (TKRCVD),
Format Error (FOERROR),
Frame Strip (FRSTRP),
or MAC Reset (MACRST).
Status: Indicates Status Indicators are being presented on MID7 -0 while Ending Delimiter Received
(EDRCVD) or Token Received (TKRCVD) is asserted.

The Contents and interpretation of MID7-0 are given in Table 7·3.
TABLE 7·3. MAC Indication Coding
Contents

Value

MID(7-4)

MID(3-0)

Data

0
1
2
:
:
254
255

0
0
0
:
:
F
F

0
1
2
:
:
E
F

Status

TT
TR
TS
TX
nT
RT
RR
RS
ST
SR
SS

5
5
5
5
0
6
6
6
7
7
7

5
6
7
*5,60r7
5
5
6
7
5
6
7

otherwise

x

x

undefined

2·206

Condition
Between RCSTART and
EDRCVDor
TKRCVDor
FRSTRPor
FOERRORor
MACRST
with EDRCVD or TKRCVD
withEDRCVD
with EDRCVD
withEDRCVD
withEDRCVD
withEDRCVD
withEDRCVD
withEDRCVD
withEDRCVD
withEDRCVD
withEDRCVD
otherwise

C

"tJ

7.0 Signal Descriptions (Continued)

CD
W
N

7.3.2.2 PDU Sequencing
The PDU Sequencing signals apply to the data and status available at the MAC Indicate Interface. They are used to determine
the validity of the data (MID7 -0) and parity (MIP). In addition the sequencing signals are used to determine the validity of the
Addressing Flags, and the Frame Status such as the Control Indicators. All timing is explained relative to the byte present on the
MAC Indicate Interface.
Symbol

Pin #

1/0

RCSTART

51

0

Receive Start: Indicates that a MAC PDU Starting Delimiter has been received. It is asserted when
the Starting Delimiter is present at the MAC Indicate Interface.

FCRCVD

52

0

Frame Control Received: Indicates that the Frame Control field is present. It is asserted when the
Frame Control field is present at the MAC Indicate Interface.

DARCVD

55

0

Destination Address Received: Indicates that the Destination Address has been received. It is
asserted on the last byte of the Destination Address and remains asserted until the next PDU Starting
Delimiter is received.

SARCVD

59

0

Source Address Received: Indicates that the Source Address has been received. It is asserted on
the last byte of the Source Address and remains asserted until the next PDU Starting Delimiter is
received.

INFORCVD

62

0

Information Field Received: Indicates that four bytes of the Information field have been received. It
is asserted on the fourth byte of the INFO field and remains active until the next PDU Starting
Delimiter is received.

Description

2·207

Q)
.....

7.0 Signal Descriptions (Continued)
7.3.2.3 PDU Flags
The PDU flags may be used with the received Frame Control field to determine if an attempt should be made to copy the frame.
Pin ..,

I/O

AFLAG

56

0

My Destination Address Recognized: Indicates that an internal address match occurred on the
Destination Address field. The internal address (MSA, MLA, GSA, GLA) match is indicated by the
assertion of FCSL and DAIG. AFLAG is asserted along with DARCVD. It is reset when the next PDU
Starting Delimiter is received.

DAIG

54

0

Individual/Group Address Flag: Indicates the address type. Valid on the first byte of the Destination
Address.

Symbol

Description

0: Individual Address
1: Group Address
FCSL

53

0

Short/Long Address Flag: Indicates the size of the Destination Address. Signal is valid when
FCRCVD is asserted.
0: Short Address
1: Long Address
Used in conjunction with TKRCVD to indicate the type of token received.
0: Non-restricted token
1: Restricted token

MFLAG

60

0

My Source Address Recognized: Indicates that the received Source Address field matched the
MLA or MSA. SA.lG is ignored in the comparison. MFLAG is asserted along with SARCVD. It is reset
when the next PDU Starting Delimiter is received.

SAMESA

61

0

Same Source Address: Indicates three conditions:
1. The Source Address of the current frame is the same as the Source Address of the previous frame
AND
2. The current and previous frames were not MAC frames AND
3. The current and previous frames have the same address field size.
SAMESA is asserted along with SARCVD. It is reset when the next PDU starting delimiter is received.

SAMEINFO

63

0

Same MAC Information: Indicates two conditions:
1. The first 4 bytes of the information field of the current frame are identical to the first 4 bytes of the
previous non-Void frame AND
2. The current and previous non-Void frames were MAC frames.
SAMEINFO is asserted along with INFORCVD. It is reset when the next PDU Starting Delimiter is
received.
Note that the FC field is not checked to insure that it is the same as in the previous frame. This
includes the address size comparison.
In REV1 of the BMAC Device Void frames are not ignored as stated in 1 and 2 above.

2-208

C

"tI

7.0 Signal Descriptions (Continued)

Q)

7.3.2.4 Termination Event

Q)

W
N

The terminating event for all PDUs is provided in the PDU Status signals.
When a token is terminated by a valid Ending Delimiter (TT symbol pair), the TKRCVD signal is asserted. When a frame is
terminated by a valid Ending Delimiter, the EDRCVD is asserted and remains asserted until all frame status has been passed to
the MA-Indicate Interface. Every PDU is terminated by one of the following:
1. A valid Ending Delimiter (TKRCVD or EDRCVD)
2. An IDLE symbol indicating that the frame was stripped by another station (FRSTRP)
3. A symbol other than data, Idle or an Ending Delimiter indicating that a Format Error occurred (FOERROR)
4. A MAC Reset (MACRST)
Pin #

I/O

TKRCVD

Symbol

69

0

Token Received: Indicates that the Ending Delimiter for a valid token is being received.

EDRCVD

66

0

Ending Delimiter Received: Indicates that the Ending Delimiter for a frame is being received. The
values of the received Status Indicators are available through the MID byte stream on this and
subsequent cycles while this signal is asserted.

FRSTRP

71

0

Frame Stripped: Indicates that an Idle symbol was received while expecting part of a PDU. This
usually indicates that the PDU was stripped by an upstream station. This signal may be asserted
anytime during reception of a frame after RCSTART is asserted.

FOERROR

70

0

Format Error: Indicates that a Format Error (non· DATA, IDLE or Ending Delimiter Symbol) was
detected. This signal may be asserted anytime during reception of a frame including with RCSTART
for the next frame.

MACRST

72

0

MAC Reset: Indicates that a MAC Reset has been issued. This signal is asserted as a result of a
software or hardware reset, or internal errors. This signal is asserted whenever bit MCRST of the
Function Register is set. This signal may be asserted anytime.

Description

7.3.2.5 Termination Status
When a valid Ending delimiter is received after a valid starting delimiter, the termination status signals provided the results of the
Frame validity check and the Frame Check Sequence Check.
The received values of the control indicators are presented in the data stream while EDRCVD is asserted.
Pin #

I/O

VDL

68

0

Valid Data Length: Indicates that a frame meeting the minimum length requirements of the Standard
and of an even number of symbols was received. This signal is valid with EDRCVD.

VFCS

67

0

Valid Frame Check Sequence: Indicates that a frame with the standard CRC was received. This signal
is valid with EDRCVD.

Symbol

Description

2·209

......

7.0 Signal Descriptions (Continued)
7.3.2.6 External Flags
The External Flags provide input to the Ring Engine in order to set the A and C indicators or in order to initiate stripping based on
external logic.
Pin '"

110

Description

EA

38

I

External A.....Flag: Indicates that an external address match occurred. The value of EA is used to alter
the values of the transmitted A and C Indicators (Ax and Cx). EA must be valid one byte time before
EDRCVD is asserted. When the EMIND bit in the Option Register is set, the A Indicator is repeated as set
(S symbol) and either the Copied or Not Copied Frame Counter is incremented depending on the value of
VCOPY.

EM

39

I

External M_Flag: Indicates that the current frame should be stripped. Three byte times after the EM
signal is asserted, the Ring Engine begins to source Idle symbols and the frame is stripped.

VCOPY

85

I

Valid Copy: Indicates that the C Indicator (Cx) should be repeated as an S symbol for received frames
when VCOPY is asserted, the received frame is not an SMT NSA frame received with the A indicator as
Set and

Symbol

1. the internal A-flag is set or
2. Option.EMIND= 1 and the external A-flag (EA) is set;
See Section 5.5 for a complete description of the setting of the control indicators.
VCOPY must be valid one byte time before EDRCVD is asserted and remain asserted until EDRCVD is
asserted.
The sampled value of VCOPY with EDRCVD also affects the incrementing of the frame copied and frame
not copied counters. See the description of the event counters for more information.

2·210

7.0 Signal Descriptions (Continued)
7.3.3 Timing Examples
The following examples show the sequencing of signals at the MAC Indicate Interface for well formed frames, for stripped
frames and for several special cases. The diagrams show the logical operation of the interface with 0 ns delays. The actual
delays are specified in Section 8. Also, in place of specifying the actual values for the flags and inputs, the cycles where they are
valid (for outputs) or must be valid (for inputs) are shown.
Frame Reception
The examples shown in Figures 1-1 through 1-3 display normal frame reception for a frame with a Short Address and a frame
with a Long Address.
LBC
UID IDLE

R~~~

101..[

IDLl

IDlE

IJK

Ire

PAD

~I

SAD

:s-"

IHroO

INFOI

INF02

~r03

:[0

rs

!DlE

IDlE

:::::: IDLE

:JK

Fe

r--,~:--~'~~-------+'--------------+'------~--~'-------+--------------J~

------t----!~,....:-i_-_t------+--~_:i_-_t-----....;..-n
~SL ____________~--~~~~~~N~~Vlli~E~--~----------~----~~~----~------------t______

,CRCVO

~O

____________t_-+--t_~

AFUG __________________________~~.~W~.________________________~------------------------_+------~RCVO _____________+--~--+_~----___!

MRAG ______________

S~~

~~~~--~------L-~.=~=---------~----~--~------~------------+-------

_______________+--_r--~--~------~-V~Mm~--------_+------~--~------+-------------_+-------

INfORCVO ______________~---!---~--"!_------~------------~
~DNfO _______________+--_r--~--~------+_------------_+~·~W~.--~--~------_+--------------+_------

,

DmCVO ______________
~

~--~--~--"!_------~------------_+------~_:~--------------~----, ,

________________--__--__--__________--__________________~rwel~·~W~.~--______------_______+------_

VOOpy ______________
V,~

,

_+--~--~--+_------r_------------_+------~~~.~W~.~:------_+--------------+_------

____________________________________________________________

~~VMm~

_________________+_______

VOL ______________-+__-r__~--~------~------------_+------~--4_~VMm~--~------------_+------TLlF/10387-5

FIGURE 7-1. Frame Reception with Short Address

2-211

DP83261

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MID

""

b

rL
ru

IDLE

RCSTART

IDLE

IDlE

JK

n

Fe

DAD

FCRCVD

.-------------+--~r___1,

FCSL

~'"'""l

DAt

rw:

OM

DA5

SAO

SAt

SA2

SAl

SA4

SA5

INroo

INFOt

1NF02

1NF03

ED

FS

fS

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r-L

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r VALID
...--,.--...----r---------,-------------

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0'

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,

,

U

SARCVD

IIFlAG

VALID

SAIIESA

VALID

:::J

(I)

g

a

__ : _________ _

I\l

INFDRCVD

.

.

.

.

r

SAllElNFD _

EDRCVD _ _ ,

:.
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EA

{!¥I

VCOPV

tvm

~

B

B

IL-________~~~

C~

YDL

VALID

TUF/l03B7-B

FIGURE 7-2. Frame Reception with Long Address

:::I

<:

e

,

'l'

~

:.Ie : FC

NEW VALUE

DARCVD

mAG

:::::: III.E

~ cCD

~
',.,"'''.
".~ NEW VALUE

DAIG

DA3

c

-a

7.0 Signal Descriptions (Continued)

CD

Co)
I\)

en
....

LBC
MID IDLE

IDLE

IDLE

IDLE

Fe

JK

TT

IDLE

IDLE

JK

Fe

RCSTART

________~r_1~__________~

FCRCVD

__________~r_1~___________r_l
~
~

FCSL

TKRCVD

NEW VALUE (RESTRICTEO/NON)

______________~r-l~____________

EDRCVD
TL/F/l0SB7-B

FIGURE 7·3. Token Reception

Remnant Reception
In these examples, the remnants of frames that were stripped by an upstream station are received. Examples are shown for
frames where the strip point occurred at an upstream station before, during and after the SA field. (See Figures 7-4 through 7-6.)

LBC
MID IDLE

RCSTART

IDLE

IDLE

IDLE

,'JK

,'Fe

OM

,'IOLE

LE :::::::::: IDLE

,

:JK

,'Fe
,

--------~~r__~I-+--------~~----~~r-l
,

FCSL

~
, ,

DAIG

~~~

FRSTRP

DA3

-------~rl~
, ____------~~-----rlL_
,

FCRCVD

DA2

DAI

NEW;ALUE

,

NEW VALUE

~

--------~~~~--------~,

FIGURE 7·4. Frame Stripped before SA Field

2-213

,~----~~--

TLiF/103B7-9

DP83261
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LBC

RCSTART

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MID IDLE

IDLE

IDLE

IDLE

DAI

DA2

DA3

DA4

SAO

SAl

SA2

SA3

IDLE

SA4

IDLE

rl-

-

"'"
ii"
0"
::l

(II

FCRCVD

FCSL

DAIG

"---------+~r_l
~ -

r-l

g>
3:i"
c:

~

~~ NEW VALUE

~
~'\.~ NEW VALUE

I\)

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.... 1

u

DARCVD

r-vAUD

AFLAG

---~~

I

FRSTRP

~~~

____________~______________~r-l~______~~
I

TUF/103B7-12

FIGURE 7-5. Frame Stripped during SA Field

......
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en

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~

LBe
MID
RCSTART

FCRCVD

C
IDLE

IDLE

IDLE

IDLE

JK

, FC

______~r1

'DAD

'DAl

DA2

DA3

DM

'DA5

SAO

SAl

SA2

SA3

SA4

SA5

INFDD

INFDl

IDLE

IDLE

IDLE' JK

r-1

__________~r_1
~"\fNEW

FCSL

CD

, FC

~

VALUE

-_. - - -

----- -

:--:

en
(')

..,

-

ii'
0'
:::l
en
g>
::J

S"
c:

DARCVD

~I

CD

~~~ NEW VALUE

DAIG

.&

--------------+--+--+---------~r_
~

AFLAG

~

j

SARCVD

MFLAG

VALID

SAMESA

VALID
--

----

~~~--------~--------------~------~~~'------~~

FRSTRP

TLlF/10387-l3

FIGURE 7-6, Frame Stripped after SA Field

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DP83261
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LBC
MID 111£

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IDlE

IDLE

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1lLE1ILE1ILE1DLE1lLE1lLE1lLE1lLE1lLE1lLE1OLE

I

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INf06

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INFOI

IIIf02

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14104

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IILE

IDLE

IDlE

IDLE

IDLE

IDlE

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IlLE

IILE

IDLE

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I

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~

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:::1

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-.=:::i
-I

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MFLAG

SAIIESA .

,

NEW VALUE

,----+-+---!---~-

AFLAG

,JK

I

FtsL

DARCYD -,

,

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_

t-L ~
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en

Q

tn
_.

VAIJD

w

INFORCYD

I

VAUD

----

--- -----

I

SAllEiNFO
EIlRCYD _

~-~-~-+------------~---------------~Im

FS

IVAIJD

VFts _,

fYiLiD--

VIll _,

TUF/l03B7-14

FIGURE 7-7. Stripping Based on M Flag

L8C

IL.....I'--I.....,L...IL-IL....IL-IL--IL....IL....IL-I.....,.....,I.-I

PIO IDlE

JK

PC

DAD

OAl

SAO

SAl

MID

IDLE

IDLE

IDLE

IDLE

: JK

: Fe

: DAD

PRO

IDLE

IOLE

IDLE

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7.0 Signal Descriptions (Continued)
LBC
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= 0 MACRST is asserted and remains asserted.
FIGURE 7·10. MAC Reset

PI

2·219

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7.0 Signal Descriptions (Continued)
7.4 MAC REQUEST INTERFACE
The MAC Request Interface is used to gain access to the ring and to transmit data Into the ring. After a Request is submitted to
the interface, the Ring Engine awaits for an appropriate Service Opportunity in which to service the Request. Frames associated
with the Request are transmitted during an appropriate Service Opportunity. Sections 5.2 and 5.3 provide important information
related to the functional operation of the interface.
In the following sections, an overview (Section 7.4.1) and detailed signal description (Section 7.4.2) are provided. The detailed
description includes a signal by signal description followed by a state diagram that details the operation of the handshaking
signals. Finally several example timing scenarios are shown (Section 7.4.3).
7.4.1 Overview
The MAC Request Interface signals provide the Request and Frame level handshakes required to transmit frames.
The MAC Request Interface is divided into one group of data signals and four groups of control signals.
The data signals consist of the 8 bits of MAC Request data with optional parity.
The control signals consist of:
• Handshake signals that implement a Request level and Frame level handshake. The state machines that specify the
interface handshake are provided and described in detail in Section 7.4.3.
• Service Parameters that convey the requested type of Service Opportunity.
• Frame Options that convey the special transmission options. These are especially useful for MAC level bridging applications.
• Transmission Status that report the success and/or failure of the transmission.
7.4.2 Signals
Request Data
The MRD7 -0 signals change on the rising edge of the Local Byte Clock signal (provided by the Clock Distribution Device).
Symbol
MRP
MRD7 -0

Pin #

110

41

I

MAC Request Parity: Odd parity on MRD7 -0.

42-49

I

MAC Request Data: Data byte conveyed for transmission while the Transmit Acknowledge (TXACK)
signal Is asserted.

Description

2-220

7.0 Signal Descriptions (Continued)
Handshake
The Handshake signals control the Request Interface handshaking process. They are used for token capture and transmission
of PDUs.
Symbol

Pin ",

1/0

Description

TXPASS

28

0

Transmit Pass: Indicates the absence of a Service Opportunity. This could result from an unusable
request class, waiting for a token, timer expiration or MAC Reset. TXPASS is always asserted between
service opportunities. It is deasserted when TXRDY signal is asserted at the beginning of a Service
Opportunity.

TXRDY

29

0

Transmit Ready: Indicates that the Transmitter is ready for another frame. For a non-immediate
request, a usable token must be held in order to transmit frames. TXRDY is asserted when:
a) A usable token is being held or
b) An immediate request becomes serviceable or
c) After frame transmission if the current Service Opportunity is still usable for another frame.
It is deasserted when the TXPASS or TXACK signal is asserted.

RORDY

23

I

Request Ready: Indicates that the Transmitter should attempt to provide a Service Opportunity as
indicated by the RORCLS(3-0) signals one cycle before RORDY is asserted. The Service Opportunity
will be maintained as long as possible. If RORDY is asserted within 6 byte times after TXRDY signal is
asserted, the Transmitter will wait at least LMax plus one Void frame (4.16 /Ls or 4.80 /Ls) for
ROSEND to be asserted before releasing the token.

ROSEND

24

I

Request Send: Indicates that the Transmitter should send the next frame. The MRD(7 -0) signals
convey the FC byte when the ROSEND signal is asserted. If ROSEND is asserted within 6 byte times
after the TXRDY signal Is asserted, the Transmitter will send the frame with a minimum length
preamble. If ROSEND is not asserted within LMax plus one Void frame after RORDY signal has been
asserted (4.16 /Ls or 4.60 /Ls), the token may become unusable (due to a timer expiration).
For Immediate transmissions from the Claim or Beacon State (when ROCLM or ROBCN is asserted),
ROSEND must be asserted no later than 8 byte times after TXRDY is asserted.
ROSEND may only be asserted when TXRDY and RORDY signals are asserted and ROFINAL is
deasserted. ROSEND must be deasserted not later than one byte time after TXRDY is deasserted.

TXACK

30

0

Transmit Acknowledge: Indicates that the Transmitter is ready for the next data byte. TXACK is
asserted when the FC byte is accepted on MRD7 -0, and remains asserted for each additional data
byte accepted. It is deasserted one byte time after ROEOF ro ROABT is asserted. The signal is also
deasserted when TXABORT or TXPASS is asserted.

ROEOF

25

I

Request End of Frame: Indicates that MRD7-0 conveys the last data byte when asserted. Normally,
this is the last byte of the INFO field of the frame (exceptions: FCS transparency, invalid frame length).
ROEOF causes TXACK to be deasserted and is ignored if TXACK is not asserted.

ROABT

27

I

Request Abort: Indicates that the current frame should be aborted. Normally this causes the
Transmitter to generate a Void, Claim, or Beacon frame. ROABT causes TXACK to be deasserted and
is ignored when TXACK is not asserted.

ROFINAL

26

I

Request Final: Indicates that the final frame of the request has been presented to the MAC Interface.
When asserted, the Issue Token Class (as opposed to the Capture Token Class) becomes the new
Token Class (TXCLASS). ROFINAL may only be asserted when RORDY Is asserted and ROSEND is
deasserted. ROFINAL is ignored unless RORDY has been asserted for at least one byte time and the
service parameters have been valid for at least three byte times. ROFINAL must be deasserted not
later than two byte times after ROSEND is deasserted.

2-221

.,...
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7.0 Signal Descriptions (Continued)

a..

Service Parameters

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C

The Service Parameters define the Service Request. They must be valid for at least one byte time before the RQRDY signal is
asserted and must not change while RDRDY remains asserted. See Section 5.3.1 for the encoding of RQRCLS.
The Requested Service corresponds to the Request Service Class and the Token Class parameters of the
(SM_)MLDATA.request and (SM_)MLToken.request primitives as specified in the Standard.
Encoded into each of the 14 possible values of RQRCLS in the Service Class (Non-Restricted Asynchronous, Restricted
Asynchronous, Synchronous, Immediate), the Token Capture and Issue Class, and THT Enable.
Requests are serviced on a Service Opportunity meeting the requested criteria.
External support is required to limit the requests presented to the MAC Interface by different MAC Users (SMT, LLC, etc.).
Symbol

Pin #

I/O

RQRCLS(3-0)

19-22

I

Description
Request Class: Indicates the Service Class parameters for this request (see Section 5.3.1).
When RQRCLS > 0, the Transmitter will capture a usable token (for non-immediate requests)
and assert TXRDY. The Service Opportunity continues as long as the token is usable with the
current service parameters, even if RQRDY is not asserted. If RQRCLS indicates a service class
that is not serviceable for any cycle of a service opportunity, the service opportunity will conclude
after the current frame and a token of the issue .token class will be issued.
If RQRCLS = 0, the Service Opportunity will terminate after the current frame and a token of the
issue token class will be issued (even if RQRCLS subsequently becomes non-zero). See
Table 5-3.

RQCLM

15

I

Request Claim: Indicates that this request is to be serviced in the Claim state. Ignored for nonimmediate requests.

RQBCN

16

I

Request Beacon: Indicates that this request is to be serviced in the Beacon state. Ignored for
non-immediate requests.

Frame Options
The Frame Options signals are selected for each frame. They must be valid while the RQSEND signal is asserted. These
options are typically used in bridging applications.
Pin #

I/O

STRIP

13

I

Void Strip: Forces two My_Void frames to be transmitted on end of current Service Opportunity.
Stripping continues until a My_Void frame returns. If any frame of a Service Opportunity requests this
option, then all frames on that Service Opportunity will be stripped using this method.

SAT

12

I

Source Address Transparency: When SA transparency is selected, the SA from the data stream is
transmitted in place of the internal MSA or MLA stored in the MAC Parameter RAM.

SAIGT

11

I

Source Address I/G Transparency: With this option, the MSB of the SA is sourced from the data
stream, as opposed to being forced to zero.

FCST

14

I

Frame Check Sequence Transparency: When selected, the Ring Engine generated FCS is not,
appended to the end of the Information field.

Symbol

Description

2-222

C

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7.0 Signal Descriptions (Continued)

01)

W
N

Transmission Status

Q)
.....

Pin #

1/0

Description

TXED

31

0

Transmitted Ending Delimiter: Indicates that the Transmitter completed transmission of the current
or previous PDU. TXED is asserted when the current PHY Request byte is a transmitted (not
repeated) Ending Delimiter. It remains asserted until the beginning of either the next transmitted (not
repeated) PDU or the next Service Opportunity. TXED is cleared by the Master Reset (bit MARST of
the Function Register).

TXABORT

32

0

Transmission Aborted: Indicates that the Transmitter aborted transmission of the current or
previous PDU before the Ending Delimiter, or that the current Service Opportunity was aborted by
Reset or Recovery actions. TXABORT is asserted when the current transmitted (not repeated) PDU
has been aborted, and remains valid until the beginning of either the next transmitted (not repeated)
PDU or the next Service Opportunity.

Symbol

TXABORT is cleared by Master Reset (bit MARST of the Function Register). It is also cleared when
an Immediate Claim or Beacon Service Opportunity is terminated by My_Claim or My_Beacon
received (I.e., when transition T(47) or T(54) occurs during an Immediate Service Opportunity).
TXRINGOP

37

0

Ring Operational: Indicates the current value of the Ring_Operational flag.

TXCLASS

35

0

Token Class: Indicates the class of the current or previous token in the Transmitter. TXCLASS is set
to FL-Flag when a valid token is received. TXCLASS is set to the Issue Token Class when the
RORDYand ROFINAL signals are asserted (before Token FC time) for the current Service
Opportunity. It is cleared by Reset and Recovery actions.

THTDIS

36

0

Token Holding Timer Disabled: Indicates that the Token Holding Timer was disabled when the
current PHY Request byte was generated. THTDIS only changes between frames. When either signal
TXRDY or TXPASS is asserted after a frame, THTDIS reflects the THT usage for that frame for at
least two byte times. When TXPASS is asserted while THTDIS is asserted it indicates that TRT
expired.

2-223

.....
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7.0 Signal Descriptions (Continued)
7.4.3 Operation
The MAC Request Interface has three logical states as determined by TXRDY and TXPASS. The interface state machine is
shown in Figure 1·11 followed by a description of the conditions. states and transitions.
State

Description

TXRDY

MRO: Not Ready

Ring Engine is not ready to service a request

0

1

MR1: Ready

Ring Engine is ready to transmit a frame

1

0

MR2: Sending

Ring Engine is sending a frame

0

0

MRO: NOT READY
f.lR(01)

MR1:READY

MR2: SENDING

SERVICE OPPORTUNITY
f.lR(12)

SET TXRDY. CLEAR TXPASS

END OF SERVICE OPPORTUNITY
SET TXPASS. CLEAR TXRDY

SEND FRAf.lE
CLEAR TXRDY. TXPASS

FRAf.lE SENT It
CONTINUE SERVICE OPPORTUNITY
MR(10)

TXPASS

SET TXRDY. CLEAR TXPASS

END OF SERVICE OPPORTUNITY
SET TXPASS. CLEAR TXRDY

f.lR(21)

f.lR(20)
TL/F/10387-18

FIGURE 7-11. MAC Request Interface State Machine
Conditions
Send Frame

A frame can be sent from the interface when at least 8 bytes of preamble have been transmit·
ted. TXRDY. RQRDY and RQSEND are asserted. and RQFINAL has not yet been asserted for
this request.

Service Opportunity

A Service Opportunity occurs when it is possible to service the current request. as defined by
the current service parameters (RQRCLS. RQCLM and RQBCN). The rules for servicing reo
quests are described in Section 5.2.

Continue Service Opportunity

A Service Opportunity is continued after the current frame if valid service parameters continue
to be presented during the frame. and the timer(s) used for the (next) requested service class
have not reached their threshold.

End of Service Opportunity

The end of a Service Opportunity occurs when it is no longer necessary or possible to continue
the Service Opportunity. The service parameters are continuously compared with the current
state of the Transmitter. If an unserviceable request is presented or any timer threshold is
reached. the Service Opportunity will not continue after the current frame (if any).

Table 7·4 shows the timer thresholds used to determine if a Service Opportunity is possible for each service class.
TABLE 7·4. Thresholds Used to Determine Service Opportunities
Request Service Class

Threshold

All Requests

TRT Expiration

All Requests with THT Enabled

THT Expiration

Priority Asynchronous Requests

Asynchronous Priority Threshold

2·224

7.0 Signal Descriptions (Continued)
State Descriptions

The send window is held open until

MRO: Not Ready

1) ROSEND or ROFINAL is asserted or

In this state the Ring Engine does not have a Service Opportunity. If RQRCLS is not zero, the Ring Engine is trying to
secure a Service Opportunity meeting the requested service
parameters.

2) until LMax has expired (3.20 ,""s), a Void frame has
been sent (0.96 '""S or 1.60 ,""s), and 7 more bytes of
preamble have been sent (0.56 ,""s). (When
Op1ion.IRPT = 1 this condition does not apply.)

On a valid Service Opportunity, the MR(01) transition is taken. The status signals TXED and TXABORT are cleared and
TXRDY is set to indicate that the Transmitter is ready to
service a request.

At any time after RORDY has been asserted and the final
frame of the request has been sent, ROFINAL may be asserted to indicate that a token of the Issue Token Class
should be transmitted at the end of the current Service Opportunity. If the MR(10) transition occurs while ROFINAL is
asserted, and all the other conditions for accepting ROFINAL hold, the transmitted token will be of the Issue Token
Class.

MR1: Ready
In this state the Ring Engine has secured a Service Opportunity and is ready to service the current request. The Transmitter is sourcing Preamble, Fill or internally generated Void
(from the Data state), Claim (from the Claim state) or Beacon (from the Beacon state) frames.

After ROFINAL has been asserted, no more frames can be
sent until RORDY has been deasserted and then reasserted. RORDY should be deasserted and the service parameters updated to reflect the next request (if any) as soon as
pOSSible, to allow the Ring Engine to make better ring
scheduling decisions. If RORDY is not deasserted by the
end of the last frame of a Service Opportunity, a Void frame
will be transmitted before the token.

The Service Opportunity is governed by the requested service parameters. If an unserviceable request is presented for
one or more cycles the Service Opportunity ends. If THT
expires or a priority threshold is reached, the Service Opportunity will end immediately or after the next frame, depending on the state of the send window.

When the Service Opportunity ends, the MR(10) transition is
taken and TXPASS is asserted to indicate the end of the
current Service Opportunity. ROFINAL (and RORDY) must
be asserted not later than one byte time after TXPASS to
insure that a token of the appropriate issue class is issued.

The send window is an opportunity to send a frame without
being interrupted by time thresholds. The Service Opportunity may end during a send window if the service parameters change.
The send window opens each time TXRDY is asserted (entry to MR1). It remains open for a minimum of 6 byte times.
The send window also opens if RORDY is asserted while
TXRDY is asserted, and if TXPASS is not asserted within
one byte time after RORDY is asserted.

When a frame can be sent from the interface, the MR(12)
transition is taken and TXACK is set to indicate that the
Transmitter is sending the frame.
The state diagram for the internal substates within state
MR1 is shown in Figure 7-12.

MRRO:PREAMBLE

MRR1: FILL

AFTER 8 BYTES & RQRDY & RQSEND &
(lRPT I... TXABORT)
RQRDY & RQSEND
MR( 12) --C-LEA=-R-TX-=--ED-;-SET-T-'XA'--C-K--<.( MR2 l---C-LEA-R'--T-X-ED-;-SET'----TX-A-CK-- MR( 12)
AFTER 8 BYTES & T2 & ... RQSEND & (IRPT 1(RQRDY & ... TXABORT»
MRR(01) - - - - - - - - - - - - - ' - - - - ' - ' - - - - - - - ' - ' - - - - - 1

MRR2: SOURCE_FR
ELSE AFTER 8 BYTES

MRR(02) - - - - - - - - - - 1
AFTER ED

1---------SET TXED; CLEAR TXABORT

ELSE ... IRPT &
(AFTER 32 BYTES I... RQRDY)

1---'-----'--'----:.......-

MRR(12)

MRR(20)

r::::::\

MR(10)

END OF SERVICE OPPORTUNITY
END OF SERVICE OPPORTUNITY
SET TXPASS
• ~.
SET TXPASS

MR(10)
TLlF/l0387-19

FIGURE 7-12_ MR1 Substate Diagram

2-225

~

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r------------------------------------------------------------------------------------------,
7.0 Signal Descriptions (Continued)
On entry to MR2 TXACK is asserted. It remains asserted
while data is being accepted from the interface. ROSEND
must be deasserted within one byte time after entering
MR2.

SUBSTATE MRRO: Preamble
Upon entry to MR1, 8 bytes of Preamble (Idles) are transmitted in substate MRRO.
After the Preamble, if a frame can be sent from the interface, transition MR12 occurs. The frame options are
latched, TXED is cleared and TXACK is asserted.

At any time after ROSEND is deasserted for the final frame
of a request, ROFINAL may be asserted to indicate that a
token of the Issue Token Class should be transmitted at the
end of the current Service Opportunity. If the MR(20) transition occurs while ROFINAL is asserted, and all the other
conditions for accepting ROFINAL hold, the transmitted token will be the issue token class.

If a frame cannot be sent from the interface, either Fill (additionalldles) or an Internally generated frame (Void, Claim, or
Beacon) is transmitted.
SUBSTATE MRR1: Fill
For requests, if RORDY is asserted (indicating that the current request has been selected for service) or Option.IRPT
is set (indicating that the ring is being interrupted), additional
fill bytes (Idles) are transmitted in substate MRR1.

After ROFINAL has been asserted, no more frames can be
sent until RORDY has been deasserted and then reasserted. RORDY should be deasserted and the service parameters updated to reflect the next requests (if any) as soon as
pOSSible, to allow the Ring Engine to make better ring
scheduling decisions.

Fill continues until:
1) a frame can be sent from the interface, or

The last byte of data at the interface is indicated by ROEOF,
which must be asserted with the last byte of data. After the
Ending Delimiter of a frame is transmitted, TXED is asserted. When not using FCS transparency, TXED is asserted 7
byte times after ROEOF is asserted. When using FCS transparency, it is asserted 3 byte times after ROEOF is asserted. TXACK is deasserted no later than one byte time after
ROEOF is asserted.

2) the Service Opportunity ends, or
3) 32 bytes of Idles are transmitted or RORDY is deasserted. After that, an internal Void frame is generated
in substate MRR2. (If Option.IRPT is set Void frames
are not generated.)
If RORDY is not asserted, if ROCLM or ROBCN is asserted,
or (unless Option.IRPT is set) if the previous frame in the
current Service Opportunity was aborted, an internal Void,
Claim or Beacon frame is generated in substate MRR2.

At any time during frame transmission, TXABORT may be
asserted. This indicates that the frame was aborted due to
internal errors, buffering errors, parity errors, ROABT, MAC
reset, reception of a MAC frame etc. TXACK is deasserted
no later than TXABORT is asserted. When a transmission is
aborted due to an error (and Option.IRPT is not set), a Void
frame is transmitted to reset the TVX timers in all stations in
the ring.

At the end of an internal frame, TXED is set, TXABORT is
cleared and another preamble is generated in substate
MRRO.
MR2: Sending
In this state the Ring Engine is transmitting a frame from the
MAC Request Interface. While the frame is being sent, if an
unserviceable request is presented or any timer threshold is
reached, the Service Opportunity will end after the current
frame.

After a successful or unsuccessful frame transmission, if the
current Service Opportunity can be continued transition
MR(21) occurs and TXRDY is asserted; otherwise transition
MR(20) occurs and TXPASS is asserted.

This implies that a Service Opportunity is never longer than
TMAX plus one maximum length frame interval for Immediate Requests (unless Option.IRPT is set), or TNEG plus one
maximum length frame interval for Non-immediate Requests. The maximum length of the frame interval is the
maximum send window open time (4.64 ,,"s-5.28 ,,"s) plus
F_max. F_max is the maximum length of a frame, including 2 bytes of Preamble. The default value of F_max for
FOOl is 4500 bytes = 360.00 ,,"s.

If at any time during a frame transmission, the end of Service Opportunity condition is detected, transition MR(20) will
occur after the current frame transition.

2-226

.----------------------------------------------------------------------.0
"'CI
7.0 Signal Descriptions (Continued)

CC)

an over-allocation of synchronous bandwidth or a station
used more than it was allocated. The ring will likely be claiming when this occurs.

7.4.3.3 Transmission Status
Upon leaving MR2, transmission status is available after
TXRDY or TXPASS is asserted. TXED and TXABORT are
normally valid for at least 9 byte times (exception: 2 byte
times when an Immediate Service Opportunity ends without
issuing a token, and another Service Opportunity begins immediately upon return to state MRO). THTDIS is valid for at
least 2 byte times. When TXPASS is deasserted and for at
least two byte times after is reasserted, TXCLASS denotes
the token that will be issued at the end of the current Service Opportunity.

7.4.4 Timing Examples
Several example sequences of the MAC Request Interface
are provided. While this in no way is an exhaustive list of
sequences, several likely sequences are shown. It is useful
to follow the state diagrams of Section 7.4.3 (Figures 7-11
and 7-12) while examining the scenarios.
The timing is shown for all signals available at the MAC
Interface.
The data shown in MRD and PRD are the data at those
interfaces.

TXED indicates that the Ending Delimiter of the previous
PDU was transmitted. TXABORT indicates that the previous
frame was aborted as a result of a request abort (RQABT),
an internal error or the Reset or Recovery Required condi·
tions became true.

The data at PRD is duplicated with the TXED to show its
relationship with the transmitted Ending Delimiter.
TXPASS and TXRDY show the relationship to the data at
the transmitter. This is one byte time before the data is
transmitted. The relationship to incoming tokens is shown
explicitly.
RQRCLS contains the Requested service class. In several
examples this is shown as generic requests (rt, r2) to make
the examples more general purpose. The RQCLM and
RQBCN signals are not shown, but have the same timing as
the RQRCLS signals.
The Frame Options are grouped together since they have
the same timing. These include the SAT, SAIGT, FCST and
STRIP options.

If TXED is asserted, TXABORT may also be asserted (within
9 byte clocks) if this station backed off to another station
after a complete Claim frame was transmitted.
When transmitting Claim/Beacon frames from the Transmitter Claim or Beacon, if TXPASS is asserted the Claim or
Beacon Process has completed. In this case, TXABORT
indicates if this station won (TXABORT = 0) or lost
(TXABORT = t) the Claim or Beacon process.
The interpretation of TXED and TXABORT is given in Table

7-5.

TXED

TABLE 7-5. Transmission Status
TXABORT
Condition

0

0

Single Frame Transmission with Prestaglng
Prestaging refers to the staging of data before the Service
Opportunity begins. Prestaging occurs in interfaces where
data is loaded into a FIFO or dedicated memory used as a
FI FO before the token arrives.
In Figure 7-13 RQRDY is asserted one byte time after
RQRCLS has been passed to the interface. At this pOint the
Ring Engine is awaiting an appropriate Service Opportunity.
Upon capture of a usable token, TXRDY is asserted.
TXRDY causes RQSEND to be asserted.
RQSEND causes TXRDY to be deasserted, which in turn
causes RQSEND to be deasserted.

After a Master Reset or frame
aborted during successful
immediate Claim or Beacon
service due to My_Claim or
My_Beacon.

t

0

Complete frame transmitted.

0

t

Frame aborted.

t

t

Complete frame transmitted,
followed by reset or recovery
actions or unsuccessful immediate
Claim or Beacon service due to
timeout.

Notice that after RQSEND is deasserted, RQFINAL is asserted for one cycle to indicate that the issue token class
should be used for the token. RQRDY is then deasserted
and RQRCLS is set to zero. Since RQRCLS goes to zero,
the end of Service Opportunity condition becomes true and
the token is issued at the end of the current frame.

If TXPASS is asserted and THT was disabled during the last
frame that was transmitted (THTDIS is asserted), TRT has
expired. This is a serious error and indicates that there was

2-227

W
N

...c»

DP83261

.....

o

en

TXRINGOP

~i
jk

TXPASS
RORCLS :

re ulL 1_____________________________

::::J r1

1

n

____________---1 rr

::J

!.

nUjkfcU

ii

cCD

11

en

.,
()

ROROY
THTDIS
TXRDY
FR OPTIONS

-

.~:

-6'
0'
::J
en

1r1
~1-·-

i

__,_-:-....,........,....-..,....-,.....--------.J.1

::s
c

1,..........,-,...--:--:-...,....-_

CD

valid ...

So

ROSENO

1\)'

MRD

i\:,

_ _ _ _ _ _ _--,- 11

:,

11 111 i21 i3114IiSfi6fl7fi8 : f1YJizlr....,--:---:-_--:---:---..,..._,_...,....----------

I\)


ROFINAI.

.

.

.

:~~~--------~-----i1

11

n

UUnjkfcU

n

--,---,---,-.--,-.--,-.--,-.--,-.--,-.--,-.--,---,---,---,-~
. . ~.--,-.--,-.~

TXCLASS
PRO

_ _ _ _ _...;.._u...;...;.n...;.......;;,.U I jk

11 i2 i3

S

A

i6

~

~

~

~

n a a

M ~ ITlii

fi

fi

fi
TUF/l03B7-20

FIGURE 7·13. Asynchronous Request with Prestaglng

7.0 Signal Descriptions (Continued)
If RORCLS remained asserted the token would be held as
long as possible and multiple frames could be transmitted.
In this case the t TXRDY t ROSEND - J- TXRDY
- J- ROSE NO handshake for the beginning of each
frame remains identical.

In Figure 7-16 the MAC Reset occurs while the Ending Delimiter is being transmitted. In Figure 7-17the boundary case
is shown where the MAC Reset occurs during the Frame
Status. Note that the Ending Delimiter of the frame is transmitted with the frame status. TXRDY is asserted for one
cycle followed by TXPASS with TXABORT.

Single Frame Transmission without Prestaglng
In Figure 7-14, prestaging is not used. Multiple requests are
present at the interface, of which only the highest priority
request is presented to the interface. RORCLS is changing
because higher priority requests become ready to be serviced. The scheduling decision is made until a Service Opportunity occurs. Once TXRDY is asserted, RORDY is asserted and the rS request is serviced.

Synchronous Request followed by Asynchronous
Request
In Figure 7-18, frames from two requests are serviced on
the same Service Opportunity. Once the synchronous frame
is being transmitted, the RORCLS is changed to that for the
asynchronous frame. At the end of the synchronous frame
TXRDY is asserted since the token is still usable for the
asynchronous request. RORDY is then asserted and the
Asynchronous frame is then transmitted.
Notice that the value of THTDIS changes after the Frame
Status for the synchronous frame is transmitted. THT is disabled for synchronous transmission and enabled for normal
asynchronous transmission.

When the data associated with rS is ready to be transmitted,
ROSEND is asserted. This in turn causes TXRDY to be
deasserted when transmission begins (entrance to MR2).
The deassertion of TXRDY causes ROSEND to be deasserted.
During the first frame of the request, the end of Service
Opportunity condition becomes true as a result of:
THT reaching the THT priority threshold if the request
was an asynchronous priority request,
THT expiration if the request was an asynchronous request or
TRT expiration if the request was a synchronous request.
TXPASS is asserted to indicate that this Service Opportunity
is complete.

Restricted Begin
In Figure 7-19, a restricted dialogue is begun. A non-restricted Token is captured, a single frame is transmitted and a
Restricted Token is issued.
An Rbeg Request is a request to capture a Non-restricted
Token and issue a Restricted Token. Since there is only one
frame in this example, ROFINAL is asserted during the first
frame. In the example, ROFINAL is asserted one byte time
after ROSEND is deasserted while RORDY is still asserted,
but it may be asserted anytime while RORDY is asserted.
Notice that TXCLASS changes to restricted after ROFINAL
is asserted.

If RORCLS remains greater than 0, the next usable token
will be captured and servicing of the request will continue. If
RORCLS remained asserted the token would be held as
long as possible and multiple frames could be transmitted.
In
this
case
the
t TXRDY - t ROSEND J- TXRDY - J- ROSEND handshake for the beginning of
each frame remains identical.

Immediate Claim
In Figure 7-20, an immediate Claim frame is transmitted
from the Claim state.
A Lower_Claim frame is received from an upstream station,
causing this station to enter its Claim state and deassert
TXRINGOP.RORCLS is set to immediate and ROCLM is asserted.

Aborted Frame Transmission
A transmission as in Figure 7-14 is started. During the transmission, an interface error occurs (for example) and ROABT
is asserted to cause the current frame to be aborted (see
Rgure 7-15). TXACK is then deasserted and TXABORT is
asserted to indicate that the frame was aborted as a result
of a FIFO underrun or an equivalent reason. This is signaled
with ROABT. After the frame is aborted, TXRDY is asserted
to indicate that another frame may be transmitted. Since no
frames are ready to be transmitted a Void fill frame is transmitted. During the Void frame transmission, the interface
then sets RORCLS to zero to indicate that the Token should
be issued. TXPASS is then asserted once the Ending Delimiter of the Void frame is transmitted.
In this scenario the transmitted Void frame serves two purposes. It is transmitted because the interface was stalling
waiting for another frame and also in response to the aborted frame. A Void frame is transmitted every time a transmission is aborted.

An internally generated Claim frame is first transmitted (at
least one internally generated Claim or Beacon frame is always transmitted upon entry to the Claim or Beacon state).
After the internally generated Claim frame is transmitted,
TXRDY is asserted since the transmitter is still in the Claim
state (the ring can hold more than one Claim frame). The
frame is then transmitted following the normal handshake.
Similar timing applies for externally generated Beacon
frames.
Remember that for Immediate Requests from the Claim and
Beacon States, ROSE NO must be asserted no later than
B byte times after TXRDY is asserted. This guarantees that
a minimum size preamble will be generated.
After the frame is transmitted, TXRDY is asserted again
since the transmitter is still in the Claim state.

MAC Reset

If this station wins the Claim Process TXPASS is asserted
without TXABORT. If another station causes this station to
backoff (this station receives a Higher_Claim), TXPASS is
asserted with TXABORT.

In Figure 7-16, a MAC reset occurs during a frame transmission. This causes the current frame to be aborted and the
Ring Operational Flag (TXRINGOP) to be deasserted.
TXPASS is asserted with TXABORT after the frame is aborted. Since the ring is not operational, no Void frames are
transmitted.

2-229

DP83261
......

b

TXRINGOP

en

~r6

TXPASS

nCRDY

'"'"

0,

II

Jk fe It

::l

!!.

cCD
tn

...n
.:s'

-

iiI r6

TX1HTDIS

1\)'

II

-r6

RQRDY

RQSEND

~...,..-..,..-~....,.....,.~I rr

II

rl I r21 r31 r41 rsl r6

RQRCLS : _

FR OPlIONS

(6'
II

0'
::l

tn

gs

Jk fe tt I r41 rsl r6

,

.

.

.

.

~

~

. vand ....
1:'""....,..-..,..---,._ _
.

.

.

. . .

.

,.

E

....

~

:~I

------~~.~
. . . . . . ~.~.~~~.~.~.~.~.~.~.~.~~~~~~~~

t.4RD

11

11

11 Ji2lI31i4PSfI6

ri71 18 : IIy liZ 1.....--,.__..,....---,.....,...-..,.....--,.-....,...----,.-

:1

D:ACK

~.~.~.~.~.~.~.~~~.~.~.~.~.~.~

RCIABT
TXABORT

~~~~~~~~:~~~-:-~~-:-~~~~~~~~....,...

RCiEOF
lXED

_____~...L..-,......,......':'"": ~

Itr rr Ii

II

iI

II

II

iI

II

Jk feltt

RQFINAL
TXCLASS
PRO

"

"

II

II fiklL.;.1....;;:......;;;....,;,;.....:;...

____"....1jk

11

i2 i3 S Ii. i6

I

-ii _---'
iw Ix Iy Iz f1 f2 f3 f4 tr rr .._iI_ _ _ _ _
TLlF/10387-21

FIGURE 7-14. Asynchronous Request without Prestaging

......
(:)
TXRINGOP

TXPASS

~Ii

RORCLS

L.C

jk

en
cO'
j
e!.

Ie tt

cCD

en
(')

~,

RORDY

"0

0'
j
en

-----, r

TXTHTOIS

~

TXRDY

Ii

I

oo
:::J

5'
c

FR OPTIONS

'"

S
ROSEND

~I

MRD

fi6Ti7l

i8

! iI --:--:---:---:---:-......,..---:-......,..---:---:---:---:-,..-,---:---:---:---:---:-~
L..:,!

TXACK

.~~~~~~~~~~~~~~

ROABT

.~~~~~~~~~~~~~~ ~~~
-:-~---:i1-'1 ii

TXABORT

Ii

Ii

Ii

jk 0

0

0

SAl

12 13 14

LI_ _ _ _ _ _ __

RQEOF

________~~~~--~~~~~~~~~~~---'!tr rr

TXED

jk Ie

IIt

RQFINAL

TXCLASS

PRD

S

A

6

ij

ik

iI

I ii

iI

iI

I jk

0

0

0

SAl

12 13 14 tr

rr L'...;......;...,.;...___,.;...

~

TL/F/l0387-22

FIGURE 7,15. Frame Abort

~9~C9da

II

~

CI)

f
Q

.---------------------------------------------------~---------------------,

7.0 Signal Descriptions (Continued)

:~:-:--:-~
~~~~~~~:~:

TXRINGOP

RQRDY

~lr6

TXTHIDIS
TXRDY
FR OPTIONS
RQSEND
MRD

~~~~~~":"'"""~~_ : ~

1
..._ _ _-.,._...,...

valid

""":"'""":---:--:--:~~~-:- :.-J
~"":"'"""~~...,..."":"'"""~~: ~ 1"

1111211311~11~11~1~11~

: 1 ;11 ...,......,...

lk 11 12 13 14 15 16 17

:"ik"iil-:
..
. --:---,-

11

-_.....I

TXACK

~

RQAST
TXABORT
RQEOF
TXED
RQFINAL
TXCLASS

....
PRD

nllnll[jkJIIIRIlIl

II

n n nllk 11 1213 SA 16

:~:

_ _ __
TL/F110387-23

FIGURE 7·16. MAC Reset

2·232

r----------------------------------------------------------------------, C

;g

7.0 Signal Descriptions (Continued)

~

a)

-:--:--:-~~-:--:--:-,I

TXPASS
RQRCLS

....

L

TXRINGOP

:oJ ;q r~. .r~ .r~ .r~ .
I

TXTHTOIS

I

I

I r6

r51 r6

TXROY

FR OPTIONS
RQSENO

-:--:--:--:--:--:--:--:--:-~ ::oJ
-:--:--:--:--:--:--:--:--:-~

:

.alld

& . . 1: - - : - - : - - : - - : - - : - - : -

.J
II

iI

II

-:--:--:-,1 jk

11211~ II~ II~ II~ II~ 118

:

II~ I I~ I,-:-,,":-,,-:--:--:--:,,--:--:-~

12 13 14 15 16 17

:

~,-':--:--:--:--:--:--:--:--:-

II

~-:--:--:--:--:--:---:-,I tr
RQFINAL

PRO

rr

ii

~-:--:--:--:--:--:--:--:--:-

Ii

ii

i~ HklL.I_;__1_1_ii_li_

Iw Ix Iy Iz

11 12 13 14 Ir rr

I!..

TL/F/l0387-24

FIGURE 7·17. MAC Reset at End of Frame

2·233

DP83261

.....

b

en

~.

::l

e!-

lXRINGOP
lXPASS

---:~~,~~~~~~~~

ROReLS

:J~:

THlDIS

lXRDY
FR OPTIONS

· ..

---

~

""'"
"'"

MRO

L!!..!J"nll
...,....,....,.....,.....,.....,.....,....,_y"J.. va.1Id ~ ...C,.....,......,.....,.....,....,....,...

· ..

~.~.~.~.~.~.~.~.~
. . . ~.~.~~~

--· ..

r--'"""l

..,......,....,.....,.....,.....,....,.....,.....,...11 11

11~5lf6T17P8

lXACK
·

ROAST
TXABORT
RQEOr
lXED
ROnNAL
lXCLASS
PRO

"tJ

----.""'.-.,.....,....,-.,..

.... . r

I o"n I

..

. "",.I....,.....,.....,.....,......,.....,.....,....,..
valid

~~~~~~...,....,...I.

.

o:

CD

.l~.~~~

fiYTiZl:--.-.-.-.--.-.-.---.-.-.• " " i i ,ipifl3fUPsp 1 pa Ilyll%..,I,....,......,.....,....,.....,.....,.....,....,..
-"--l
-'
-"--l...,......,.....,....,.....,....,.....,....~
6 17

~...,......,......,.....,...~,.....,.,...I'r

-=___ ·:::::J
n n n

:..!ffl

8

~

8

n n n

~

Ilk 11

8

8 8-n-8-8ol...,..
. ...,......,.....,-..,....,....,.....,,..

. ................. :n~:~~

n

· ..

.~~:....,......,~~....,....~

rr

12 i3 S

A 16

iw Ix Iy Iz f1 f2 f3 14 Ir

rrl R

i

n

8

n n

8

Ilk 11

12 13 S A i6

~~~~~~~.~

tw Ix I)' iz f1 f2 f3

,.e.

tr

rrl.!...

TlIF/l0387-25

FIGURE 7-18. Synchronous Request followed by Asynchronous

l'
.s

· ..

-::· ___
•:::::J
......

en
g-

I...,......,.....,-,-....,......,,.....,..

....,....~~....,....~....,......,~~....,.....,-,-....,....,.....,...~:

o::l·
::l

-::___ ::::::J
· ..

~.

I I

luyn

..

·

ROSENO

I ~"n
I I ";Yn

,""""",....;.....,.....,.....,.....,...1 ~yn
).yn

RQRDY

O

CD

en
~~~~~~~.~ ()

.....
b

en

TXRINGOP

I rbeg

TXPASS
RQRCLS
RQRDY

.:=J

-:-_:___:__~~___:_~I rr

cO"
:::s
!!.

Jk Ie It

C

I I

rbeg

I rbeg

.

---:--:----:....-~:-:~

~=====-----------~~t=============-.

I
I rbeg

THTDIS
TXRDY

Jk Ie It I ii

II I"

II

Ii

iI

II

...
CD

(I)
()

-S"
0"

ii L.I,.........,_ _---,-.....,...._ _

:::s
(I)

'§
:::I

g.

-:--:--:--:--:--:--:--:--:-~I

FR OPTIONS

valid

MRD

-:--.,........,.........,......,.........,......,.........,.........,.---,..- 11

N

""

CD

B

-~I----:----:~...,....

RQSEND

1\)1

C

-L.I,....-,....-,....-,....-,....-,....-,....

11 11 1 i21 i31141151161 i7118

U1

:

riy 1 iz ~I-:---:---:---:----:--:--:--:--:----:--:-:---:--.,........,..---:--:--,........,....

:~~~~~~~-,....--,....--,....-~-:--,..-

TXACK
RQABT
TXABORT

-----~~-------------------------:~~-:--.....,....~---:-.....,....-,....-:---:--~~---:-.....,....---:---:--~,....

RQEOF

_ _ _ _ _ _ _....JI tr

TXED

rr

II

II jk Ie It

II

II 1 Jk Ie It

-,....--:--:--:--:--:--:--:--:--:--:-~n~-:--:-_ __

RQFINAL
TXCLASS

.
PRD

_ _ _"_"_ :

~ II

rotr token

II

II

Ii I jk i1 12 13

S A

6

Iw ix

iy iz 11 12 13 14 tr rr III

II

~

TLlF/l0387-26

FIGURE 7-19" Restricted Begin

~9~&8da

II

DP83261

.....

b
tn
iff
::J

!.
llCRINGOP

oCD

:~

llCPASS

-----

RORClS :

::1-.-: :

(IJ

...n

...........

RORIJY

. ...... r:_~Io~I~

-----

lower

claim

..........................................

I»
I\)
Co>
C»

MRD

lXABDRT

-------------

. . . . . . .

III'

rr

Inn

11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 111~1i31~1~1~[I7I~II9-

. . . ..

-------------

liil~

..r:,... ..,....,....,......,....,.-,....,....,....,....,...

...,.....,....,.-,.....,.-.,......,....,....,....,...

~L,.:

........................................ :~L,.:-.,....,....,.....,.....,.-.,....,....,....,....,..
. . . . . . . . . . . . . . . . . . . . . . . . . lirrr----g ••

1XED

::J

.............................................

RQEOF

RQFIIIAL

(IJ

g
a

Bunlal

...... .

. . . . . ..

11 12 13

'" Ix IJ Iz II f2 13 14

III'

rr

B • U

-----

lXClASS
PRD

~: i..i.fii;l~

n

D

Illk

10

A

A cO.l c2 c3 II f2 13 14

II' rrll

.Ilk

A 115 17

II' rrl.!...!...!..
TUF/l0387-27

FIGURE 7-20. Immediate Claim

c:

!

lXACK
RQABT

::J

..Del

FR OPlIOHS
RQS£ND

..... .

I.

1IIIIIIS

1XRDY

-

ii'
0'

111!III1Od1a1o .lalm

C

7.0 Signal Descriptions (Continued)

."

7.5 ELECTRICAL INTERFACE

....

co
~
en

The Electrical Interface signals comprise all of the clocking, power supply, and ground pins.
Pin #

1/0

LSC

87

I

Local Symbol Clock: 25 MHz clock with a 40/60 duty·cycle. Typically generated by the COD.

LBC

86

I

Local Byte Clock: 12.5 MHz clock 50/50 duty·cycle in phase with LSC. Typically generated by the
COD.

RST

118

I

Master Reset: Equivalent to setting the Master Reset bit in the Function Register. An asynchronous
input that must be asserted for at least 5 LSC clock cycles. When asserted, all bi·directional signals
are tri·stated. Active low signal.

Vee[ll]

4,17,34
58, 78
94, 100
106,117

I

Positive Power Supply: 5V, ± 5% relative to GND.

GND[11]

5,18,33
57,77,
88-91,
101,
116,128

I

Power Supply Return

Symbol

Description

7.6 PINOUT SUMMARY
TABLE 7·6. Pinout Summary
Pin #

Signal Name

Symbol

110

1

Control Bus Data 1

CBD1

I/O

2

Control Bus Data 2

CBD2

1/0

3

Control Bus Data 3

CBD3

1/0

4

Positive Power Supply

Vee

I

5

Ground

GND

I

6

Control Bus Data 4

CBD4

1/0

7

Control Bus Data 5

CBD5

1/0

8

Control Bus Data 6

CBD6

1/0

9

Control Bus Data 7

CBD7

I/O

10

Control Bus Parity

CBP

I/O

11

Source Address I/G Transparency

SAIGT

I

12

Source Address Transparency

SAT

I

13

Void Strip

STRIP

I

14

Frame Check Sequence Transparency

FCST

I

15

Request Claim

ROCLM

I

16

Request Beacon

ROBCN

I

17

Positive Power Supply

Vee

I

18

Ground

GND

I

19

Request Class 3

RORCLS3

I

2·237

7.0 Signal Descriptions (Continued)
7.6 PINOUT SUMMARY (Continued)
TABLE 7·6. Pinout Summary (Continued)
Symbol

I/O

20

Request Class 2

RORCLS2

I

21

Request Class 1

RORCLS1

I

22

Request Class 0

RORCLSO

I

23

Request Ready

RORDY

I

24

Request Send

ROSEND

I

25

Request End of Frame

ROEOF

I

26

Request Final

ROFINAL

I

27

Request Abort

ROAST

I

28

Transmit Pass

TXPASS

0

29

Transmit Ready

TXRDY

0

30

Transmit Acknowledge

TXACK

0

31

Transmit Ending Delimiter

TXED

0

32

Transmit Abort

TXASORT

0

33

Ground

GND

I

34

Positive Power Supply

Vee

I

35

Token Class

TXCLASS

0

36

Token Holding Timer Disabled

THTDIS

0

37

Ring Operational

TXRINGOP

0

38

External A-Flag

EA

I

39

External M_Flag

EM

I

40

Positive Power Supply

Vee

I

41

MAC Request Parity

MRP

I

42

MAC Request Data 7

MRD7

I

43

MAC, Request Data 6

MRD6

I

44

MAC Request Data 5

MRD5

I

45

MAC Request Data 4

MRD4

I

46

MAC Request Data 3

MRD3

I

47

MAC Request Data 2

MRD2

I

48

MAC Request Data 1

MRD1

I

49

MAC Request Data 0

MRDO

I

50

Ground

GND

I

Pin #

Signal Name

51

Receive Start

RCSTART

0

52

Frame Control Recevied

FCRCVD

0

53

Short/Long Address Flag

FCSL

0

54

Individual/Group Address Flag

DAIG

0

55

Destination Address Received

DARCVD

0

56

My Destination Address Recognized

AFLAG

0

57

Ground

GND

I

58

Positive Power Supply

Vee

I

59

Source Address Received

SARCVD

0

2-238

C

"U

7.0 Signal Descriptions (Continued)

OJ

Co)
I\)

....
en

7.6 PINOUT SUMMARY (Continued)
TABLE 7·6. Pinout Summary (Continued)
Pin #

Signal Name

Symbol

1/0

60

My Source Address Recognized

MFLAG

0

61

Same Source Address

,SAMESA

0

62

Information Field Received

INFORCVD

0

63

Same MAC Information

SAMEINFO

0

64

Ground

GND

I

65

Positive Power Supply

Vee

I

,0

66

Ending Delimiter Received

EDRCVD

67

Valid Frame Check Sequence

VFCS

0

68

Valid Data Length

VDL

0

69

Token Received

TKRCVD

0

70

Format Error

FOERROR

0

71

Frame Stripped

FRSTRP

0

72

Media Access Control Reset

MCRST

0

73

MAC Indicate Parity

MIP

0

74

MAC Indicate Data 7

MID7

0

75

MAC Indicate Data 6

MID6

0

76

MAC Indicate Data 5

MID5

0

77

Ground

GND

I

78

Positive Power Supply

Vee

I

79

MAC Indicate Data 4

MID4

0

80

MAC Indicate Data 3

MID3

0

81

MAC Indicate Data 2

MID2

0

82

MAC Indicate Data 1

MID1

0

83

MAC Indicate Data 0

MIDO

0

84

Ground

GND

I

85

Valid Copy

VCOPY

I

86

Local Byte Clock

LBC

I

87

Local Symbol Clock

LSC

I

88

Ground

GND

I

89

Ground

GND

I

90

Ground

GND

I

91

Ground

GND

I

92

PHY Request Data 0

PRDO

0

93

PHY Indicate Data 0

PIDO

I

94

Positive Power Supply

Vee

I

95

PHY Request Data 1

PRD1

0

96

PHY Indicate Data 1

PID1

I

97

PHY Request Data 2

PRD2

98

PHY Indicate Data 2

PID2

I

99

PHY Request Data 3

PRD3

0

2·239

0

•

I

....

m
c

7.0 Signal Descriptions (Continued)
7.6 PINOUT SUMMARY (Continued)

TABLE 7-6. Pinout Summary (Continued)
Pin #

Symbol

Signal Name

1/0

100

Positive Power Supply

Vee

I

101

Ground

GND

I

102

PHY Indicate Data 3

PID3

I

103

.PHY Request Data 4

PRD4

0

104

PHY Indicate Data 4

PID4

I

105

PHY Request Data 5

PRD5

0

106

Positive Power Supply

Vee

I

107

PHY Indicate Data 5

PID5

I

108

PHY Request Data 6

PRD6

0

109

PHY Indicate Data 6

PID6

I

110

PHY Request Data 7

PRD7

0

111

PHY Indicate Data 7

PID7

I

112

PHY Request Control

PRC

0

113

PHY Indicate Control

PIC

I

114

PHY Request Parity

PRP

0

115

PHY Indicate Parity

PIP

I

116

Ground

GND

I

117

Positive Power Supply

Vee

I

118

Master Reset

RSf

I

119

Read/- Write

RIW

I

120

- Control Bus Enable

CE

I

121

-Interrupt

INT

0

122

- Acknowledge

~

0

123

Control Bus Address 0

CBAO

I

124

Control Bus Address 1

CBA1

I

125

Control Bus Address 2

CBA2

I

126

Control Bus Address 3

CBA3

I

127

Control Bus Address 4

CBA4

I

128

Ground

GND

I

129

Control Bus Address 5

CBA5

I

130

Control Bus Address 6

CBA6

I

131

Control Bus Address 7

CBA7

I

132

Control Bus Data 0

CBDO

I/O

2-240

.----------------------------------------------------------------------,0
"U

7.0 Signal Descriptions (Continued)

C»
Co)

N

....

7.7 PINOUT DIAGRAM

GND
RQRCLS3
RQRCLS2
RQRCLSI
RQRCLSD
RQRDY
RQSEND
RQEOF
RQFINAL
RQABT
TXPASS
TXRDY
TXACK
TXED
TXABORT
GND

Vee
TXCLASS
THTDIS
TXRINGOP
EA
EM

Q)

o

Vee

DP83261

BMAC

Vee

PRD5
PID4
PRD4
PID3
GND

Vee
PRD3
PID2
PRD2
PIDI
PRDI

Vee

MRP
MRD7
MRD6
MRD5
MRD4
MRD3
MRD2
MRDI
MROO
GND

PIOO
PROD
GND
GND
GND
GND
LSC
LBC
VCOPY
GND

TUF11 03B7 -11

FIGURE 7-21. DP83261132-Pin PQFP Pinout

Order Number DP83261AVF
See NS Package Number VF132A

•
2-241

....
CD
N
C')

CO

Il..

C

8.0 Electrical Characteristics
8.1 ABSOLUTE MAXIMUM RATINGS
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Symbol

Parameter

Min

Conditions

Max

Units

Vee

Supply Voltage

-0.5

7.0

V

VIN

DC Input Voltage

-0.5

Vee + 0.5

V

VOUT

DC Output Voltage

-0.5

Vee + 0.5

V

TSTG

Storage Temperature Range

-65

+150

·C

h

Lead Temperature

Soldering, 10 sec.
(IR or Vapor) (Phase Reflow)

230

·C

ESD Rating

RZAP
CZAP

BOO

V

=
=

1.5k,
120 pF

8.2 RECOMMENDED OPERATING CONDITIONS
Symbol

Parameter

Vee

Supply Voltage

PD

Power Dissipation

T

Operating Temp

Conditions

Min

Max

4.75

5.25

V

400

mW

70

·C

0

Units

8.3 DC ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Conditions

=

VOHl

Minimum High Level
Output Voltage

Cl

VOH2

Minimum High Level
Output Voltage

IOH

VOll

Maximum Low Level
Output Voltage

Cl

= 50pF

VOL2

Maximum Low Level
Output Voltage

10l

= 4mA

VOl3

Maximum Low Level
Output Voltage INT
and ACK (Open Drain)

IOL

= BmA

=

50 pF
-2mA

Min

Max

Units

Vee - 0.5

V

2.4

V
0.4

V

0.4

V

0.4

V

VIH

Minimum High Level
Input Voltage

Vil

Maximum Low Level
Input Voltage

O.B

V

V

2.0

IIH

Input High Current

+10

p.A

III

Input Low Current

-10

p,A

10Zl

TRI·STATE Leakage for
CBD(7-0) and CBP

±10

p,A

IOZ2

TRI-STATE Leakage for
INT and ACK (Open Drain)

±10

p,A

IOZ3

Dynamic Supply Current

70m

rnA

Cl

= 50 pF. 12.5 MHZ

2-242

8.0 Electrical Characteristics (Continued)
8.4 AC ELECTRICAL CHARACTERISTICS
See Figures 8-8 and 8-9 for AC Signal and TRI-STATE Testing Criteria.
8.4.1 Control Bus Interface
Symbol
T1

Parameter

Min

Max

Units

CE Setup to LBC

15

T2

LBCPeriod

SO

T3

LBC to ACK Low

T4

CE Low to ACK Low

T5

LBC Low to CBD(7 -0) and CBP Valid

T6

LBC to CBD(7 -0) and CBP Active

T7

CE Low to CBD(7 -0) and CBP Active

225

475

ns

TS

CE Low to CBD(7 -0) and CBP Valid

265

515

ns

290

ns
ns
45

ns

540

ns

60

ns

60

ns

T9

LBC Pulse Width High

35

45

ns

T10

LBC Pulse Width Low

35

45

ns

45

ns

T11

CE High to ACK High

T12

R/IN, CBA(7-0), CBD(7-0) and
CBP Set up to CE Low

5

ns

T13

CE High to R/W, CBA(7-0),
CBD(7 -0) and CBP Hold Time

0

ns

T14

R/W, CBA (7-0), CBD(7-0)
and CBP Setup to LBC

20

ns
ns

T15

ACK Low to CE High Lead Time

0

T16

CE Minimum Pulse Width High

20

T17

CE High to CBD(7-0) and CBP TRI-STATE

T1S

ACK High to CE Low

0

ns

T19

CBD(7 -0) Valid to ACK Low Setup

20

ns

T20

LBC to INT Low

55

Asynchronous Definitions
T4(min)

T1

T4 (max)

T1

T7 (min)

T1

T7 (max)

T1

TS(min)

T1

TS (max)

T1

+ (3 * T2)
+ (6 * T2)
+ (2 • T2)
+ (5 • T2)
+ (2 • T2)
+ (5 • T2)

Note: MiniMax numbers are based on T2

~

ns
55

+ T3
+ T3
+ T6
+ T6
+ T9 + T5
+ T9 + T5

eo ns and T9 ~ T1 0 ~ 40 ns.

2-243

ns

ns

,..

~
C')
CIO

,---------------------------------------------------------------------------------,
8.0 Electrical Characteristics (Continued)

a.
C

Tl6
R/W
T13
CBA

ADDRESS VALID IN

CBD &:
CBP

DATA VALID IN
T1S

T4
TLlFI10387-28

FIGURE 8-1. Control Bus Interface Write Cycle

CE
T1S
T12
R/W
T13
CBA

ADDRESS VALID IN

CBD &:
CBP

T8
T19

T1S

T11

T4
TLIF110387-29

FIGURE 8-2. Control Bus Interface Read Cycle

2-244

C

8.0 Electrical Characteristics

""D
00
c.:I

(Continued)

N

0'1

.....

T16

R/W
T13
CBA

CBD &
CBP

TL/F/l0387-30

FIGURE 8-3. Control Bus Interface Synchronous Write Cycle

TL/F/l0387-31

FIGURE 8-4. Control Bus Interface Synchronous Read Cycle

2-245

fJI

.,...
CD
N

C')
CC)

a.
C

8.0 Electrical Characteristics (Continued)
8.4.2 Clock Signals
Symbol

Parameter

Min

Max

T21

LSC to LBC Lead Time (Skew Left)

-4

6

T22

LSC Pulse Width High

12

Units
ns
ns

T23

LSC Pulse Width Low

21

T24

LBC Pulse Width High

35

45

ns

T25

LBC Pulse Width Low

35

45

ns

T23
LSC

T22

r
'I

I

ns

121

I+-

LBC~

~
125

124

TUF/l0387-32

FIGURE 8·5. Clock Signals

8.4.3 PHY Interface
Symbol
T26

Parameter

Min

PHY Data Input Setup

15

Max

ns

Units

T27

PHY Data Input Hold

5

ns

T28

PHY Data Sustain

10

ns

T29

PHY Data Valid

45

I

LBC
126
PID7-0.
PIP, 8c PIC

ns

~

127

DOOOOQOOO~.

XXXXl

I--i
PRD7-0,
PRP, 8c PRC

129
T28

IXXXXXX
TL/F/l0387-33

Note: All setup and hold testing is done on single edges only (i.e., no combined setup/hold testing Is done for pulse signals. This Implies that the signal makes only
one low to high or high to low transition per CYcle).

FIGURE 8·6. PHY Interface Timing

2·246

-

C

"tI

8.0 Electrical Characteristics (Continued)

(X)
Co)
II.)
0)

8.4.4 MAC Interface

.....

Pin Groups
Group #

1/0

1

I

Pins
SAIGT, SAT, STRIP, EA, VCOPY, ROEOF, ROSEND, ROFINAL

2

I

RORDY

3

I

FCST, ROBCN, ROCLS(3-0), EM, ROABT

4

I

ROCLM

5

I

MRD(7-0), MRP

6

0

TXPASS, TXED, TXABORT, RCSTART, FCRCVD, SAMESA, INFORCVD, SAMEINFO, TXRDY, TXACK,
TXCLASS, THTDIS, TXRINGOP, DIAG, DARCVD, AFLAG, SARCVD, MFLAG, EDRCVD, VFCS, VDL, TKRCVD,
FOERROR, FRSTRIP, MACRST

7

0

MID(7-0), MIP

Symbol

Max

Units

Parameter

Min

T30

MAC Control Setup (Groups # 1 and # 3 and # 4)

15

ns

T31

MAC Control Setup (Group #2)

30

ns

T32

MAC Control Hold (Group #3)

2

ns

T33

MAC Control Hold (Groups #1 and #2 and #4)

5

ns
ns

T34

MAC Data Setup (Group #5)

15

T35

MAC Data Hold (Group #5)

6

ns

T36

MAC Control Sustain (Group #6)

15

ns

T37

MAC Control Valid (Group #6)

T3B

MAC Data Sustain (Group # 7)

T39

MAC Data Valid (Group #7)

45
15

ns
ns

45

ns

LBC
130
131
T34
IofAC INPUTS
GROUPS 1-5

T32
T33
135

T30
T31,
T34

r--

IXXXXXXXX~

XXXXl
_

IofAC OUTPUTS
GROUPS 6-7

T36
T38

T37
T39

XXXXXX
TUF/I0387-34

Note: All selup and hold testing is done on single edges only (i.e., no combined setup/hold testing is done for pulse signals. This implies that the signal makes a
single low to high or high to low transition per cycle).

FIGURE 8·7. MAC Interface Timings

2·247

....

CD
C'II

C")

CO

a.
Q

8.0 Electrical Characteristics (Continued)
Test Conditions for AC Testing
VIH

3.0V

VIL

O.OV

VOH

1.SV

VOL

1.SV

IOL

8.0 mA (AeR, iliJ'I')

CL

SOpF

AC Signal Testing

REF SIGNAL

MEASURE SIGNAL

MEASURE SIGNAL

MEASURE SIGNAL
TUF/t0387-35

Nole: All setup and hold testing is done on single edges only (i.e.. no combined setup/hold testing Is done lor pulse signals. This Implies that the signal makes only
one single low to high or high to low transition per cycle).

FIGURE 8-8. A.C. Signal Testing
TRI-STATE Timing

LBC

50%

CBD(7-0) .II CBP

CBD(7-0) .II CBP

VOL + 0.5V
TUF/t0387-36

FIGURE 8-9. TRI-STATE Timing

2-248

.----------------------------------------------------------------------,0
"'C
8.0 Electrical Characteristics (Continued)

co

W
N

....
Q)

Test Equivalent Loads
VOL2 Testing

VOH2 Testing

61''-

~
I

OUT OUTPUT

i

SOPf

SOPf
TL/F/103B7-3B

TL/F/103B7-37

Tlo-trl

Thi-tri

61''-

~
I

18!smA

~"ft~"
I

SOPf

SOPf
TLlF/103B7-40

TL/F/103B7-39

Open Drain VOL Testing

T~!smA
I

AC, VOL1, VOH1 Testing
OUT OUTPUT

OUT OPEN
DRAIN OUTPUT

TL/F/103B7-42

S0Pf

TL/F/103B7-41

FIGURE 8-10. Test Equivalent Loads

fI

2·249

Appendix A. Ring Engine State Machines
A.1 RECEIVER
A.1.1 MAC Receiver State Diagram
RO: LISTEN
DISABLE lVX

Rl:AWAIT SO
PH_INDICATION(II)

R(Ol)

RESET TVX; ENABLE TVX
MAC_RESET

R(10A)

PH_INVALID

R(10B)

SET RELR.PINV

R5:CHECK_TK
PH_INDICATlON(II)

R(SlA)

MAC_RESET

SIGNAL FR_STRIP

R(SOA)

PH_INVALID

R(SOB)

SIGNAL FO_ERROR; INC LOSLCT; SET RELR.PINV

PH_INDICATlON(NOT{II, TT)

R(SlB)

SIGNAL FO_ERROR;
INC LOSLCT

R2:RC FR CTRL
AFTER FCr & FCr

R(2S)

AFTER PH_INDICATION(TT)

R(SlC)

= TOKEN

TlLRECEIVEDJCTlONS

PH_INDICATION{JK)
SIGNAL RC_START; CLEAR A, M, E, L, H-FLAGS

MAC_RESET

R(20A)

PH_INDICATION(II)

R(21 A)

SIGNAL FR_STRIP
PH_INDICATlON(NOT(II, NN»

R(21 B)
PH_INVALID
SIGNAL FO_ERROR;
INC LOSLCT;
SET RELR.PINV

SIGNAL FO_ERROR; INC LOSLCT

R3: RC FR BODY
DA. SA. CT ACTIONS

R(20B)

R(23)

AFTER FCr & FCr .. TOKEN
IF FCr

= NSA THEN

SET N_FLAG

MAC_RESET

R(31 B)

R4:RC FR STATUSl
AR ACTIONS

R(31 C)

PH_INDICATION(TK)
EDJCTlONS
R(41)
PH_INVALID
SET RELR.PINV

SIGNAL FR_STRIP
PH_INDICATlON(NOT(II. TK. nT. NN»
SIGNAL FO_ERROR;
INC LOSLCT

R(30B)

SIGNAL FO_ERROR; INC LOSLCT; SET RELR.PINV

R(40A)

PH_INDICATION(II)

R(31A)

R(30A)

PH_INVALID

MAC RESET

R(12)

R(34)

PH_INDICATION (nT)
SIGNAL FILRECElVED;
SIGNAL EDRCVD;
INC FRAME..CT;
IF ER " S INC ERROILCT

PH_INDICATlON(NOT(RR, RS, RT, SR, SS, sT)

R6:RC FR STATUS2

R(40B)

R(46) PH_INDICATlON(RR, RS, RT, SR, SS, ST}
R(61)
PH_INVALID

PH_INDICATlON(NOT(RR, RS,
RT, SR, 5S, sT)

R(60)

SET RELR.PINV

TUF/10387-43

FIGURE A·1, Ring Engine Receiver State Diagram

2-250

C

Appendix A. Ring Engine State Machines (Continued)

"'tJ
CD

A.l.2 MAC RECEIVER FOOTNOTES

en
.....

~

A 1.2.1 Internal Conditions
(1) ESA:

Option.Enable_Short_Address
(2)ELA:

Option.Enable_Long_Address
(3)IRR:

Option.Inhibit_Recovery_Required I

(~ESA

& ~ELA)

(4)IFCS:

Option. Implementer_FCS
(5)EMIND:

Option.External_Matching_Indicators
(6) MAC_Reset:

Function.MAC_Reset

I~Mode.Run

A.l.2.2 Transition Conditions
(1) PH_Invalid:

See encoding of PH_Invalid in Section 7.2.1.1
(2) PH_Indication (Sl S2):

Sl is the first symbol received, S2 is the second symbol received. See encoding of
PH_ Indication in Section 7.2.1.1
(3) Transition R( 12):

This Transition may be a 0 time transition from any state except RO:Listen
A.l.2.3 Actions
1. DA-Actlons:

IF FC.L = 0 CLEAR FCSL ;short address
ELSE SET FCSL ;long address
After DAOr
IF DA.IG = 0 CLEAR DAIG ;individual address
ELSE SET DAIG ;group address
IF FCSL = 0 ;short address
After DAlr
SIGNAL DARCVD
IF DAIG = 1
THEN IF DAr is contained in set of Group Addresses
THEN SET A_Flag
IF DAIG = 0
THEN IF DAr = MSA
THEN SET A_Flag
IF FCSL = 1 ;long address
After DA5r
SIGNAL DARCVD
IF DAIG = 1
THEN IF DAr is contained in set of Group Addresses
THEN SET A_Flag
IF DAIG = 0
THEN IF DAr = MLA
THEN SET A_Flag
NOTE: A_Flag may be set on reception of VOID frames.

2-251

II

...

CD
N

('I)

fc

r-------~--------------------------------------------------------------------------__,

Appendix A. Ring Engine State Machines (Continued)
2. SAJctlons:
IF FCSL = 0; short address
After SAlr
SIGNAL SARCVD
IF ESA
THEN IF SAr = MSA
THEN SET MFLAG. Signal FR_Strip
ELSE IF SAr > MSA THEN
SET HFLAG
ELSE SET LFLAG
IF ((SAr = previous SArI & (previous FCSL = 0) &
(FC.FF = ~MAC & previous FC.FF = ~MAC) THEN
SIGNAL SAMESA
IF FCSL = 1: long address
After SA5r
SIGNAL SARCVD
IF ELA
THEN IF SAr = MLA
THEN SET MFlag. Signal FR_Strip
ELSE IF SAr > MLA
THEN SET H_Flag
-ELSE SET L_Flag
IF ((SAr = previous SArI & (previous FCSL = 1) &
(FC.FF = ~MAC & previous FC.FF = ~MAC)
THEN SIGNAL SAMESA
NOTE; A station, with a null address may not win Claim when Option.IRR is set ••
3. CT-Actions:
After 4_Info_Octets
If FCr = Claim
IF T_Bid_Rc
TREQ
CLEAR MFLAG
IF T_Bid_Rc > TREQ
THEN IF L_Flag
SET H_Flag
CLEAR L_Flag
ELSE IF H_Flag
SET L_Flag
CLEAR H_Flag
IF L_Flag
SIGNAL FR_Strip
IF ((INFOr = previous INFO) & (FCSL = previous FCSL) &
(FC.FF = MAC'& previous FC.FF'= MAC)
THEN SIGNAL SAME INFO

*'

4. TLRecelved-Actions:
IF Token_Class = Restricted
THEN IF ~R_Flag
THEN SET R_Flag
SET TELR.ENTRMD [Entered_Restricted_Model
ELSE RESET TVX
CLEAR R_Flag
SIGNAL TK_Received
INC TKCT [token countl
SET CILR.TKRCVD [Token-Receivedl

2-252

Appendix A. Ring Engine State Machines (Continued)
5. ED-AcUons:

INC FRCT {Frame_Received_Ctl
SIGNAL FR_Received, EDRDVD
SET CILR.FRRCV
If Valid_Data_Length & (Valid_FCS_Rc I (FCr = Void)
(FCr = Implementer and ~(Option.IFCS»
THEN RESET TVX;
IF (A_Flag I(EA & Option.EMIND» & VCOpy
THEN SET C_Flag
ELSE SET E_Flag {This E_Flag is used during rest of the ED_Actionsl
CLEAR A_Flag, M_Flag, H_Flag, L_Flag
IF Er
S & E_Flag
THEN INC EICT {Error_Ctl
SET CILR.FREI {Frame_Error_Isolatedl
IF Er = R & ~E_Flag
THEN
IF FCr = Claim
THEN SET RELR.CLM
IF A_Flag & M_Flag
THEN SIGNAL My_Claim
SET RELR.MYCLM
CLEAR R_Flag
SET TNEG = T_Bid_Rc
IF H_Flag
THEN SIGNAL Higher_Claim
SET RELR.HICLM
CLEAR R_Flag
SET TNEG = T_Bid_Rc
IF L_Flag
THEN SIGNAL Lower_Claim
SET RELR.LOCLM
CLEAR R_Flag
IF FCr = Beacon
THEN SET RELR.BCN
IF M_Flag
THEN SIGNAL My_Beacon
SET RELR.MYBCN
CLEAR R_Flag
IF ~ (M_Flag IE_Flag)
THEN SIGNAL Other_Beacon
SET RELR.OTRBCN
CLEAR R_Flag
IF FCr = Other_MAC
THEN SIGNAL Other_MAC
SET RELR.OTRMAC
IF FCr = VOID
THEN
IF M_Flag & A_Flag & ~DAIG
SIGNAL My_Void
ELSE IF ~A_Flag
SIGNAL Void
ELSE IF ~M_Flag
SIGNAL Other_Void

'*

2·253

fI

~ r-------~------------------------------------------------------------~----~--~

CD
C'I
('I)

'CO

DC

Appendix A. Ring Engine State Machines (Continued)
6. ArJctlons:
After Ar
IF Ar = R
THEN CLEAR N_Flag
IF A_Flag & Ar = S & DA.IG = 0 & ~E_Flag'
THEN SET RELR.DUPADD (Duplicate_Address I Strip Error' detected}
IF REVl & ~E_Flag & (A_Flag I (EA & EMIND)) & FCr 9= (MAC I Void) .
IF (VCOPY & FCr 9= NSA) I (VCOPY & FCr = NSA & Ar = R)
THEN SET CILR.FRCOP
INC FCCT (Frame_Copied_Ct}
ELSE IF ~VCOPYI (FCr =' NSA & Ar = S)
SET CILR.FRNCOP
INC FNCT (Frame_Not_Copied_Ct}
IF REV2 & ~E_Flag & (A_Flag I (EA & EMIND)) & FCr 9= (MAC I Void) & ~ (FCr =
NSA & Ar = S)
IF VCOPY
THEN SET CILR.FRCOP
INC FCCT (Frame_Copied_Ct}
ELSE SET CILR.FRNCOP
INC FNCT (Frame_Not_Copied_Ct}

2-254

C

-a
01)

Appendix A. Ring Engine State Machines (Continued)

w

N

A.2 TRANSMITTER

Q)

......

A.2.1 MAC Transmitter State Diagram

TO:TLIDlE

T4: ClAIM_TK

11: REPEAT
RC_START Ie

T(OI)

VOID_STRIP Ie

~

= TOKEN

BErORE rcx /I; rCr

~

llCRECEIVED Ie

~

IRPT

Ie CAPTURE-TK

T(10A)

IRPT

T(10B)

PASS_ACTIONS

I rO_ERROR

rR_STRIP

RECOVERY-ACTIONS

T(IOC)

MAC_RESET I IRPT

T(IOO)

RESET-ACTIONS
rR-RECEIVED

T(10E)

TILRECEIVED I< USABLE-TOKEN I<

T(02A)

RECOVERY-REQUIRED

T(14)

~ ITC

T2:TLDATA
Ie

~ IRPT

CAPTURUCnONS
USABlUMMEDIATE Ie

T(02B)

~ ITC

RESET_REQUIRED
RESET-ACTIONS

= LOPR;

RESET lMAX

= NONE

T(20B)

SET LATE

T(22)

T7:TX VOID
llCRECEIVED /I;

~ USABLE-TOKEN

~ITC

T(07)

I<

I

I<

T(27)

ArTER rsx &:

T(72)

SET VSENT

~ TX.PASS

~ TX.PASS

<~:I

RECOVERY-REQUIRED

T(74)

ANOTHER_VOID

ArTER rsx Ie

ELSE ArTER rsx Ie TX.PASS Ie
SEND_VOID

~IRPT

PASS-ACTIONS

RECOVERY-ACTIONS

T(20A)

ELSE ArTER rsx I< TX.PASS I< TX.CLASS
RESET TRT

RECOVERY-REQUIRED

T(24)

IMMEDIATE-ACTIONS

RECOVERY-ACTIONS

T(77)

MY-CLAIM I<

I

~ ITR /I; ~ IRPT

T(47)

START-ACTIONS

RESET_REQUIRED

T(70A)

RESET-ACTIONS
ELSE ArTER rsx /I; TX.PASS '"
TX.CLASS ¢ NONE
RESET TRT = LOPR;
SET LATE

T3; ISSUE-TK

T(70B)
T(73)

ELSE ArTER rsx &: TX.PASS '"
TX.CLASS ¢ NONE

llCRECEIVED '" ITC Ie ~ IRPT

T(03)

PASS-ACnONS

T(34)

RESET_REQUIRED

RECOVERY_REQUIRED
RECOVERY-ACTIONS

T(30A)

RESET-ACTIONS
ArTER ED(lT)

T(30B)

ISSUUCTIONS

RECOVERY-REQUIRED

T(04)

RECOVERY-ACnONS
RESET_REQUIRED

T(40)

RESET-ACTIONS
T(OO)

I

T5: TX BEACON

RESET-ACTIONS

TRT EXPIRES

MAC-'!ESET I (OTHER_BEACON '" ~ IRPT)
RESET-ACTIONS
T(OS)

fII

RESET_REQUIRED

BEACON_REQUEST
RESET TRT

SET BEACON_TYPE = UNSUCCESSrUl CLAIM;
SET DA = NUll; RESET-ACTIONS

T(SO)

T(54)

= LOPR

T(45)

MY-BEACON'" (CLAIM_REQUEST I .."RR)
RECOVERY-ACTIONS
Tl/F/l0387-44

FIGURE A·2. Ring Engine Transmitter State Diagram
2-255

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Appendix A. Ring Engine State Machines (Continued)

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A.2.2 MAC TRANSMITTER FOOTNOTES
A.2.2.1 Internal Conditions
(1) ESA:

Option.Enable_Short_Address
(2) ELA:

Option.Enable_Long_Address
(3)IRPT:

Option. Inhibit_Repeat

I

(,ESA & ,ELA)

(4)ITC:

Option. Inhibit_Token_Capture
(5)IRR:
(6)ITR:

Option. Inhibit_Token_Release
(7)IFCS:

Option. Implementer_FCS
(8)EMIND:

Option. External_Mat ching_Indicators
(9) MAC_Reset:

Function.MAC_Reset I ,Mode.Run
(10) Beacon,Request:

Function.Beacon_Request & ,MAC_Reset
(11) Claim_Request:

Function.Claim_Request & ,Beacon_Request & ,MAC_Reset
A.2.2.2 Transition Conditions
(1) Usable_Token:

Ring_Operational & ,RQ.Send &
((RQ.Class = synchronous & ,RELR.Beacon_Received)
(RQ.Class = asynchronous & ,Late & RQ.Class.Capture = FCr.L &
(RQ.Class oF priority I TRT < T_Pri[RQ.Class.Priority]) &
,(RQ.Class = restricted &
(RELR.Beacon_Received I RELR.Claim_Received I
(RQ.Class.Capture = nonrestricted & ,RbeginOK)))))
(2) Capture_TK:

,ITC & ,IRPT & (Usable_Token I
(Ring_Operational & ,TELR.Ring_Latency_Valid & ,Late & ,FCr.L))

(3) Immediate Request:

RQ.Class

=

immediate & ,RQ.Claim & ,RQ.Beacon

(4) Usable_Immediate:

,Ring_Operational & TX.Class = none &
,(TK_Received & ,IRPT) & ,RQ.Send & Immediate_Request
(5) Send_Void:

TX.Abort I
(After FSx &
((TX.Ready &
(,RQ.Ready I ((Immediate_Request I Lmax expired) & ,RQ.Send))
(TX.Pass &;
(Void_Strip I (,TELR.Ring_Latency_Valid & Early)
,(TX.ED I TX.Class = none))

2-256

I

Appendix A. Ring Engine State Machines (Continued)
(6) Another_Void:

After FSx & TX.Pass & Void_Strip & ,Vsent
(7) ReseLRequired:

MAC_Reset I
(,IRPT & (Higher_Claim I Other_Beacon I Other_MAC» I
(IRPT &: (T3 I (TO & (Ring_Operational I TX.Class 7'= none I ,Late»»
Note: Any other MAC frame received while RING_Operational must be a My_Claim or a bad frame. These frames are ignored here.

(8) Recovery_Required:

Claim_Request I
(,IRR &:
(Lower_Claim I My_Beacon I TVX expires I
(TRT expires &: Late & ,«TO I TIl & TK_Received»»
Nole: (Ring_Operational & T_Opr < T-Req) must be detected by softwarel

A.2.2.3. Transition Actions
(1) PassJctions:

CLEAR TX.Ready, Void_Strip;
IF Tl THEN SET RbeginOK = ,FCr.L;
SET TX.Class = FCr.L; SET TX.Pass, TELR.Token_Passed;
If Ring_Operational
THEN IF ,Late
THEN RESET TRT = T_Opr
ELSE CLEAR Late
ELSE SET T_Opr
T_Neg; RESET TRT
T_Opr; SET Late;
SET RELR.Ring_Operational_Set, Ring_Operational

=

=

(2) Capture-Actions:

CLEAR TX.ED,
SET TX.Class
RESET Lmax;
IF ,Late
THEN
ELSE

TX.Abort, TX.Pass, Void_Strip;

= FCr.L; SET TX.Ready, TELR.Token_Captured;
SET Early; SET THT
CLEAR Early, Late

=TRT; RESET

TRT

=T_Opr

(3) Immedlate-Actlons:

CLEAR TX.ED, TX.Abort, TX.Pass, Void_Strip;
SET TX.Class = none; SET TX.Ready;
SET Early; RESET TRT = T_Opr; CLEAR Late
(4) Reset-Actions:
IF T41T51(T2 &: ,TX.Ready &: ,TX.Pass &: ,TX.ED)

THEN SET TX.Abort
CLEAR TX.Ready, TX.Ack, Void_Strip;
SET TX.Class = none; SET TX.Pass;
SET T_Opr
T_Max; RESET TRT
T_Opr; SET Late;
IF Ring_Operational
THEN SET RELR.Ring_Operational_Reset
IF MAC_Reset IRing_operational
CLEAR Late_Count, Ring_Operational, Function.MAC_Reset

=

=

2-257

~ r-----------------------~------------------------------------------------------------,

~
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Appendix A. Ring Engine State Machines (Continued)

a.

(5) Recovery-Actlons:

C

IF T2 & ~TX.Ready & ~TX.Pass & ~TX.ED
THEN SET TX.Abort
IF T5
THEN CLEAR TX.Abort
CLEAR TX.Ready, TX.Ack, Void_Strip;
SET TX.Class = nonrestricted; SET TX.Pass;
SET T_Opr T_Max; RESET TRT
T_Opr; SET Late;
IF Ring_Operational
THEN SET RELR.Ring_Operational_Reset;
CLEAR Late_Count, Ring_Operational

=

=

(6) StarLActlons:

CLEAR TX.Ready, TX.Ack, TX.Abort; SET Void_Strip, TX.Pass;
RESET TRT = T_Opr
(7) Issue-Actlons:

IF

~Ring_Operational

=

THEN SET T_Opr T_Neg; RESET TRT
IF TX.Class = nonrestricted & ~R_Flag
THEN SET RbeginOK
ELSE CLEAR RbeginOK

= T_Opr;

SET Late

A.2.2.4 State Actions
(1) TRT-Actlons:

Always:
IF TRT expires
THEN RESET TRT = T_Opr;
IF ~ «Tolnl & TK_Received & ~IRPTl
THEN IF ~Late
THEN SET Late
ELSE SET TELR.TRT_Expired;
IF ~Ring_Operational
THEN INCREMENT Late_Count
IF (T4 & ~(My_Claim & ~ITR & ~IRPTlll
(T5 & ~(My_Beaoon & (Claim_Requestl~IRRlll
THEN SET TELR.Recovery_Failed
(2) RLCT-Actlons:

Always:
IF TELR.Ring_Latenoy_ValidIMAC_Resetl (~ESA & ~ELAll
(TRT expires & LatellPH_Invalidl
Lower_ClaimlMy _BeaoonlHigher_Claiml
Other_BeaoonlOther_MACITK_Recei vedlOther _Void
THEN DISABLE Latency_Count
IF My_Void & Latency_Count enabled
THEN SET TELR.Ring_LatencY_Valid
(3) T)Lldle-Actlons (TO):

Always:
PH_Data. request (Ill ;
IF My_VoidIOther_Void
THEN CLEAR Void_Strip

2·258

.----------------------------------------------------------------------.0
"tI
Appendix A. Ring Engine State Machines (Continued)

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(4) RepeaLActlons (T1):

IF -llRPT II: (Higher_ClaimIOther_BeaconIOther_MACl II:
(Ring_Operationallrx.Class oF nonel,Late)
THEN SET TX.Class = none;
SET T_Opr = T_Max; RESET TRT = T_Opr; SET Late;
IF Ring_Operational
THEN SET RELR.Ring_Operational_Reset;
CLEAR Late_Count. Ring_Operational
Still-Usable:
Ring_Operational II: ,RQ.Send II:
«RQ.Class = synchronous II: ,RELR.Beacon_Receivedll
(RQ.Class
asynchronous II: ,Late II: RQ.Capture
FCr.L II:
(RQ.Class oF prioritylTRT < T_Pri[RQ.Class.Priority)l II:
,(RQ.Class = restricted II:
(RELR.Beacon_ReceivedIRELR.Claim_Receivedl
(RQ.Class.Capture = nonrestricted II: ,RbeginOKlllll

=

=

(5) T}L.DatLActlons (T2):

IF Lmax

= expired

II: RQ.Ready
THEN RESET Lmax; SET Used
IF ,RQ.Ready
THEN RESET Lmax; CLEAR Used
IF Abort
THEN SET TX.Abort;
IF Still_Usable
THEN SET TX.Ready
ELSE SET TX.Pass
After ED
SET rx.ED;
IF Still_Usable
THEN SET TX.Ready
ELSE SET TX.Pass

(6) IssuL-TKJctions (T3):

Always:
IF My_Void
THEN CLEAR Void_Strip
(7) Clal'"-.TKJctlons (T4):

CLEAR Function. Claim_Request·
(8) T}L.BeaconJctlons (T5):

CLEAR Function.Beacon_Request
(9) T}L.VolcLActlons (T7):

Always:
IF MY_Void II: Vsent
THEN CLEAR Void_Strip

2-259

....

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

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~National

PRELIMINARY

~ Semiconductor

DP83265 BSITM Device
(FOOl System Interface)
General Description

Features

The DP83265 BSI device implements an interface between
the National FOOl BMACTM device and a tiost system. It
provides a multi-frame, MAC-level interface to one or more
MAC Users.
The BSI device accepts MAC User requests to receive and
transmit multiple frames (Service Data Units). On reception
(Indicate), it receives the byte stream from the BMAC device, packs it into 32-bit words and writes it to memory. On
transmission (Request), it unpacks the 32-bit wide memory
data and sends it a byte at a time to the BMAC device. The
host software and the BSI device communicate via registers, descriptors, and an attention/notify scheme using clustered interrupts.

• 32-blt wide Address/Data path with byte parity
• Programmable transfer burst sizes of 4 or 8 32-bit
words
• Interfaces to low-cost DRAMs or directly to system bus
• 2 Output and 3 Input Channels
• Supports Headerllnfo splitting
• Bridging support
• Efficient data structures
• Programmable Big or Little Endian alignment
• Full Duplex data path allows transmission to self
• Confirmation status batching services
• Receive frame filtering services
• Operates from 12.5 MHz to 25 MHz synchronously with
host system
TO HOST SYSTEM

fJ;J.Kf.t~iE~:*f:m

~.: (SYSTEM INTERFACE) :. ;
.~ :.: :.: :.: :.:..:.: :.: :.: :.;.........:.; ;.; ,'.;:

.. .. .. .. .. .. ..

.. ..

DP83241
CDD
(CLOCK
DISTRIBUTION)

DP83231
CRD
(CLOCK
RECOVERY)

"---v----'
TO FIBER OPTIC
TRANSCEIVER PAIR

FIGURE 1. FOOl Chip Set Block Diagram

2-260

TL/F/10791-1

r-----------------------------------------------------------------,c
Table of Contents
5.0 CONTROL INFORMATION
1.0 FOOl CHIP SET OVERVIEW

5.1 Overview

2.0 ARCHITECTURE DESCRIPTION

5.2 Operation Registers

2.1 Interfaces

5.3 Control and Event Register Descriptions

2.2 Data Structures

5.4 Pointer RAM Registers

2.3 Map Engine

5.5 Limit RAM Registers
5.6 Descriptors

3.0 FEATURE OVERVIEW
3.1 32-Bit address/Data Path to Host Memory

5.7 Operating Rules

3.2 Multi-Channel Architecture

5.B Pointer RAM Register Descriptions

3.3 Support for Header/Info Splitting

5.9 Limit RAM Register Descriptions

3.4 MAC Bridging Support

5.10 BSI Device Descriptors

3.5 Confirmation Status Batching Services

6.0 SIGNAL DESCRIPTIONS

3.6 Receive Frame Filtering Services

6.1 Pin Organization

3.7 Two Timing Domains

6.2 Control Interface

3.B Clustered Interrupts

6.3 BMAC Device Indicate Interface
6.4 BMAC Device Request Interface

4.0 FUNCTIONAL DESCRIPTION
4.1 Overview

6.5 ABus Interface

4.2 Operation

6.6 Electrical Interface

4.3 Bus Interface Unit

2-261

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r---------------------------------------------------------------------------------,
1.0 FDDI Chip Set Overview
National Semiconductor's FOOl chip set consists of five
components as shown in Figure 1-1. For more information
about the other devices in the chip set, consult the appropriate data sheets and application notes.

DP83261 BMACTM Device
Media Access Controller
The BMAC device implements the Timed Token Media Access Control protocol defined by the ANSI FOOl X3T9.5
MAC Standard.

DP83231 CRDTM Device
Clock Recovery Device

Features

The Clock Recovery Device extracts a 125 MHz clock from
the incoming bit stream.

• All of the standard defined ring service options
• Full duplex operation with through parity
• Supports all FOOl Ring Scheduling Classes (Synchronous, Asynchronous, etc.)
• Supports Individual, Group, Short, Long and External
Addressing

Features
• PHY Layer loopback test
• Crystal controlled
• Clock locks in less than 85 p.s

• Generates Beacon, Claim, and Void frames internally

DP83241 CDDTM Device
Clock Distribution Device

• Extensive ring and station statistics gathering
• Extensions for MAC level bridging
• Separate management port that is used to configure and
control operation

From a 12.5 MHz reference, the Clock Distributon Device
synthesizes the 125 MHz, 25 MHz, and 12.5 MHz clock required by the BSI, BMAC, and PLAYER devices.

• Multi-frame streaming interface

DP83251/55 PLAYERTM Device
Physical Layer Controller

DP83265 BSITM Device
System Interface

The PLAYER device implements the Physical Layer (PHY)
protocol as defined by the ANSI FOOl PHY X3T9.5 Standard.

The BSI Device implements an interface between the
BMAC device and a host system.

Features

Features

• 32-bit wide Address/Data path with byte parity
• Programmable transfer burst sizes of 4 or 8 32-bit words
• Interfaces to low-cost DRAMs or directly to system bus

• 4B/5B encoders and decoders
• Framing logic
• Elasticity Buffer, Repeat Filter and Smoother

• Provides 2 Output and 3 Input Channels

• Line state detector/generator

• Supports Header/Info splitting
• Efficient data structures
• Programmable Big or Little Endian alignment

• Link error detector
• Configuration switch
• Full duplex operation
• Separate management port that is used to configure and
control operation
In addition, the DP83255 contains .an additional
PHY_Data. request and PHY_Data.indicate port required
for concentrators and dual attach stations.

• Full duplex data path allows transmission to self
• Confirmation status batching services
• Receive frame filtering services
• Operates from 12.5 MHz to 25 MHz synchronously with
host system

2-262

2.0 Architecture Description
The BSI device is comppsed of three interfaces and the
Map Engine,
'

The Control Bus Interface is separate from the BMAC device and ABus Interfaces to 'allow independent operation of
the Control Bus.

The three interfaces are the BMAC device, the ABus, and
the Control Bus. They are used to connect the BSI device to
the BMAC device, Host System, and external Control Bus.

The host uses the Control Bus to access the BSI device's
internal registers, and to manage the attention/notify logic.

The Map Engine manages the operation of the BSI device.

2.2 DATA STRUCTURES

2.1 INTERFACES

2.2.1 Data Types

The BSI device connects to external components via three
interfaces: the BMAC device Interface, the ABus Interface,
and the Control Bus Interface (see Figure 2-1).

The architecture of the BSI device defines two basic kinds
of objects: Data Units and Descriptors. A Data Unit is a
group of contiguous bytes which forms all or part of a frame
(Service Data Unit). A Descriptor is a two-word (64-bit) control object that provides addressing information and control/
status information about BSI device operations.

2.1.1 BMAC Device Interface
The BSI device connects to the BMAC device via the
MA-Indicate (receive) and MA-Request (transmit) Interfaces, as shown in Figure 2-1.
'

Data and Descriptor objects may consist of one or more
parts, where each part is contiguous and wholly contained
within a 1k or 4k memory page. A single-part object consists.
of one Only Part; a multiple-part object consists of one First
Part, zero or more Middle Parts, and one Last Part. In Descriptor names, the object part is denoted in a suffix, preceded by a dot. Thus an Input Data Unit Descriptor (IDUD),
which describes the last Data Unit of a frame received from
the ring, is called an IDUD.Last.

Received Data is transferred from the BMAC device to
the BSI device via the MA-Indicate Interface. the
MA-Indicate Interface consists of a parity bit (odd parity)
and byte-wide data along with flag and control signals.
Transmit Data is transferred from the BSI device to
the BMAC device via the MA-Request Interface. The
MA-Request Interface consists of a parity bit (odd parity)
and byte-wide data along with flag and control signals.

A single-part Data Unit is stored in contiguous locations
within a single 4k byte page in memory. Multiple-part Data
Units are stored in separate, and not necessarily contiguous
4k byte pages. Descriptors are stored in contiguous locations in Queues and Lists, where each Queue or List occupies a Single 1k byte or 4k byte memory page, aligned on
the queue·size boundary. For both Queues and Lists, an
access to the next location after the end of a page will automatically wrap-around and access the first location in the
page.

2.1.2 ABus Interface
The BSI device connects to the Host System via the ABus
Interface. The ABus Interface consists of four bits of parity
(odd parity) and 32 bits of multiplexed address and data
along with transfer control and bus arbitration signals.

2.1.3 Control Bus Interface
The Control Bus Interface connects the BSI device to the
external Control Bus.
To HOST SYSTEM

Bus Control &:
Arbitration
Signal.

AB..AD(3t:O)

-

ABUS INTER.ACE

B
U
5

MAP ENGINE

I

I
N
T
E
R

I

•

BMAC INTERFACE

MA.JNDICATE(7:0)
MA.JNDICATE PARITY

Flags I<

Control
Signals

Transmit
Parameters &
Handshake
Signals

C
0
N
T
R
0
L

-

II

A
C
E

MILREQUEST(7:0)
MILREQUE5T PARITY

To BMAC DEVICE
TLlF/l079t -2

FIGURE 2·1. BSI Device Interfaces

2-263

~r-----------------~----------------~---------------------------------,

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c

2.0 Architecture Description (Continued)
Data Units (MAC Service Data Units) are transferred between the BSI device and' BMAC device via five simplex
Channels, three used for Indicate (receive) data and two for
Request (transmit) data. Parts of frames received from the
ring and copied to memory are called' Input Data Units
(IDUs); parts of frames read from memory to be tansmilled
to the ring are called Output Data Units (ODUe).
Descriptors are transferred between the BSI device and
Host via the ABus, whose operation is 'for the most part
transparent to the user. There are five Descriptor types rec·
ognized by the BSI device: Input Data Unit Descriptors
(IOU Os}, Output Data Unit Descriptors (ODUDs); Pool
Space Descriptors (PSPs), Request Descriptors (REQs),
and Confirmation Message Descriptors (CNFs):
Input and Output Data Unit Descriptors describe a single
Data Unit part, i.e., its address (page number and offset),
its size In bytes, and its part (Only, First, Middle, 'or
Last). 'Frames consisting of a single part are described by
a Descriptor.Only; frames consisting of multiple parts
are described by a Descriptor.First, zero or more
Descriptor.Middles, and a Descriptor.Last.

Every Output Data Unit part is described by ari Output Data
Unit Descriptor (ODUD). Output Data Unit Descriptors are
fetched from memory so that frame parts can be assembled
for transmission,
Every Input Data Unit part is described by an Input Data Unit
Descriptor (lOUD). Input Data Unit Descriptors are generat·
ed on Indicate Channels to describe where the BSI device
wrote each frame part and to report status for the frame.
Request Descriptors (REQs) are wri~en by the user to spec·
ify the operational parameters for aSI deviCe Request oper·
ations. Request Descriptors also contain the start address
of part of a stream of ODUDs and the number of frames
represented by the ODUD stream part (i.e., the number of
ODUD.Last descriptors). Typically, the user will define a sin·
gle Request Object consisting of multiple frames of the
same request and service class, frame control, and expect·
ed status.
'
Confirmation Messages (CNFs) are created by the BSI de·
vice to record the result of a Request operation.
Pool Space Descriptors (PSPs) describe the location and
size of a region of memory space available for writing Input
Data Units.
Request (transmit) and Indicate (receive) data structures
are summarized in Figures 2·2 and 2-3.

--,
I

First ODU

REQuest.Only

~

I
I

I
I

I
I

I
I

.--------04
~_:r-----·

l
J

Frame #1

ODUD.Flrst

I--Last ODU

ODUD.Last
ODUD.F1rst
ODUD.Mlddle

I--First ODU

ODUD.Last

'1
Last ODU

Middle ODU

l

Frame #2

j

TL/F/l0791-3

FIGURE 2·2. aSI DeVice Request Data Structures

2·264

C

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2.0 Architecture Description (Continued)

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U1

Frame #1

I -_ _---I.-J

l
L..-----,J

Frame #2

IDUD.La.t

l

II~
I

r--------,

I
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~-

l

I

- - - - - - -

~

La,t IOU

Frame #3

U------~ ~J
Middle ODU

TL/F/l0791-4

FIGURE 2·3. BSI Device Indicate Data Structures
2.2.2 Descriptor Queues and Lists
The BSI device utilizes 10 Queues and two Lists. These
queues and lists are circular. There are six Queues for Indicate operations, and four Queues and two Lists for Request
operations. Each of the three Indicate Channels has a Data
Queue containing Pool Space Descriptors (PSPs), and a
Status Queue containing Input Data Unit Descriptors
(lDUDs). Each Request Channel has a Data Queue containing Request Descriptors (REQs), a Status Queue containing
Confirmation Messages (CNFs), and a List containing Output Data Unit Descriptors (DOUDs).

2.3 MAP ENGINE
The Map Engine, which manages the operation of the BSI,
is comprised of seven basic blocks: Indicate Machine, Request Machine, Status/Space State Machine, Operation
RAM, Pointer RAM, Limit RAM, and Bus Interface Unit. An
internal block diagram of the BSI device is shown in Figure

2-4.
2.3.1 Indicate Machine
The Indicate Block accepts Service Data Units (frames)
from the BMAC device in the byte stream format (MA.-Indicate).

During Indicate and Request operations, Descriptor Queues
and Lists are read and written by the BSI device, using registers in the Pointer and Limit RAM Register files. The Pointer RAM Queue and List Pointer Registers pOint to a location
from which a Descriptor will be read (PSPs, REQs, and
ODUDs) or written (IDUDs and CNFs).

Upon receiving the data, the Indicate Block performs the
following functions:
• Decodes the Frame Control field to determine the frame
type
• Sorts the received frames onto Channels according to
the Sort Mode

For each Queue Pointer Register there is a corresponding
Queue Limit Register in the Limit RAM Register file, which
holds the Queue's limit as an offset value in units of 1 Descriptor (8 bytes). The address in the Queue Pointer is incremented before a Descriptor is read and after a Descriptor is
written, then compared with the value in the corresponding
Queue Limit Register. When a Descriptor is accessed from
the location defined by the Queue Limit Register, an attention is generated, informing the host that the Queue is empty. When a pOinter value is incremented past the end of the
page, it wraps to the beginning of the page.

• Filters identical MAC frames
• Copies the received frames to memory according to
Copy Criteria
• Writes status for the received frames to the Indicate
Status Queue
• Issues interrupts to the host at host-defined status breakpoints
2.3.2 Request Machine
The Request Machine presents Service Data Units (MAC
frames) to the BMAC device in the byte stream format
(MA.-RequestJ.
The Request Machine performs the following functions:

2.2.3 Storage Allocation
The maximum unit of contiguous storage allocation in external memory is a Page. All BSI device addresses consist of a
16-bit page number and a 12-bit offset.

• Reads frames from host memory and assembles them
onto Request Channels

The BSI device uses a page size of 1K or 4k bytes for storage of Descriptor Queues and Lists (as selected by the
user), and a page size of 4K bytes for storage of Data Units.
A Single page may contain multiple Data Units, and multiplepart Data Units may span multiple disjoint or contiguous
pages.

• Prioritizes active requests
• Transmits frames to the BMAC device
• Writes status for transmitted and returning frames
• Issues interrupts to the host on user-defined group
boundaries

2-265

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2.0 Architecture Description (Continued)
Control

C

Address/Data

Bu. Clock

ABu. Interface

BIU
Bus Interface Un"

Control Bus

r---..., Interface
Data
Indicate
Burst

Request
Burst

FIFO

FIFO

Reque.t
Machine

Indicate
Machine
Indicate
Data

Request
Data

FIFO

FIFO

Indicate
Data

Control
Bus

1-____t>llndlcate
Control

Request 1+____-1 Request
Data
Control

BMAC Device
Interface

TL/F/10791-5

FIGURE 2·4. BSI Device Internal Block Diagram
3. Confirmation Message Descriptor stream

2.3.3 Status/Space Machine
The Status/Space Machine is used by both the Indicate Ma·
chine and the Request Machine.

4. Request Descriptor stream
The BIU arbitrates between the Subchannels and issues a
Bus Request when any Subchannel requests service. The
priority of Subchannel bus requests is generally as follows,
from highest priority to lowest priority:

The Status/Space Machine manages all descriptor Queues
and writes status for received and transmitted frames.

2.3.4 Bus Interface Unit

1. Output Data Unit reads (highest priority)

The Bus Interface Unit (BIU) is used by both the Indicate
and Request Blocks. It manages the ABus Interface, provid·
ing the BSI device with a 32·bit data path to local or system
memory.
The Bus Interface Unit controls the transfer of Data Units
and Descriptors between the BSI device and Host memory
via the ABus.
Data and Descriptors are transferred between the BSI de:
vice and Host memory in streams, where a stream is a flow
of logically related information (I.e., a single type of data or
descriptor object) in one direction (either to or from host
memory). Each Channel supports a subset of object
streams, via Subchannels. The three Indicate Channels
each support three Subchannels:
1. input Data Unit stream

2. Input Data Unit writes
3. Input Data Unit Descriptor writes

4.
5.
6.
7.

Confirmation Message Descriptor writes
Pool Space Descriptor reads
Mailbox reads/writes
Pointer RAM and Limit RAM Service functions (lowest
priority)

Addresses for Subchannel accesses are contained in the
Pointer RAM Registers.

2.3.5 Pointer RAM
The Pointer RAM Block is used by both the Indicate and
Request Machines. It contains pOinters to all Data Units and
Descriptors manipulated by the BSI device, namely, Input
and Output Data Units, Input and Output Data Unit Descrip·
tors, Request Descriptors, Confirmation Messages, and
Pool Space Descriptors.

2. input Data Unit Descriptor stream
3. Pool Space Descriptor stream

The two, Request Channels each support four Subchanne!s:
1. Output Data Unit stream
2. Output Data Unit Descriptor stream

2·266

3.2 MULTI-CHANNEL ARCHITECTURE
The BSI device provides three Input Channels and two Output Channels, which are designed to operate independently
and concurrently. They are separately configured by the
user to manage the reception or transmission of a particular
kind of frame (for example, synchronous frames only).

2.0 Architecture Description
(Continued)
The Pointer RAM Block is accessed by clearing the PTOP
(Pointer RAM Operation) bit in the Service Attention Register, which causes the transfer of data between the Pointer
RAM Register and a mailbox location in memory.

3.3 SUPPORT FOR HEADERIINFO SPLITTING
In order to support high performance protocol processing,
the BSI device can be programmed to split the header and
information portions of (non-MAC/SMT) frames between
two Indicate Channels. Frame bytes from the Frame Control
field (FC) up to the user-defined header length are copied
onto Indicate Channel 1, and the remaining bytes (info) are
copied onto Indicate Channel 2.

2.3.6 Limit RAM
The Limit RAM Block is used by both the Indicate and Request Machines. It contains data values that define the limits of the ten Queues maintained by the BSI device.
Limit RAM Registers are accessed by clearing the LMOP
(Limit RAM Operation) bit in the Service Attention Register,
which causes the transfer of data between the Limit RAM
Register and the Limit Data and Limit Address Registers.

3.4 MAC BRIDGING SUPPORT

3.0 Feature Overview

Support for bridging and monitoring applications is provided
by the Internal/External Sorting Mode. All frames matching
the external address (frames requiring bridging) are sorted
onto Indicate Channel 2, MAC and SMT frames matching
the internal (BMAC device) address are sorted onto Indicate
Channel 0, and all other frames matching the BMAC device's internal address (short or long) are sorted onto Indicate Channel 1.

The BSI device implements a system interface for the FOOl
BMAC Device. It is designed to provide a high-performance,
low-cost interface for a variety of hosts.
On the system side, the BSI device provides a simple yet
powerful bus interface and memory management scheme to
maximize system efficiency. It is capable of interfacing to a
variety of host busses/environments. The BSI device provides a 32-bit wide multiplexed address/data interface,
which can be configured to share a system bus to main
memory or communicate via external shared memory. The
system interface supports virtual addressing using fixed-size
pages.

3.5 CONFIRMATION STATUS BATCHING SERVICES
The BSI device provides confirmation status for transmitted
and returning frames. Interrupts to the host are generated
only at status breakpoints, which are defined by the user on
a per Channel basis when the Channel is configured for
operation.

On the network side, the BSI device performs many functions which greatly simplify the interface to the BMAC device, and provides many services which simplify network
management and increase system performance and reliability. The BSI device is capable of batching confirmation and
indication status, filtering out MAC frames with the same
information field, and performing network monitoring functions.

The BSI device further reduces host processing time by
separating received frame status from the received data.
This allows the CPU to quickly scan for errors when deciding whether to copy the data to memory. If the status were
embedded in the data stream, all the data would need to be
read contiguously to find the Status Indicator.
3.6 RECEIVE FRAME FILTERING SERVICES

3.1 32-BIT ADDRESS/DATA PATH TO HOST MEMORY

To increase performance and reliability, the BSI device can
be programmed to filter out identical (same FC and Info
field) MAC or SMT frames received from the ring. Filtering
unnecessary frames reduces the fill rate of the Indicate
FIFO, reduces CPU frame processing time, and avoids unnecessary memory bus transactions.

The BSI device provides a 32-bit wide synchronous multiplexed address/data interface, which permits interfacing to
a standard multi-master system bus operating from
12.5 MHz to 25 MHz, or to local memory, using Big or Little
Endian byte ordering. The memory may be static or dynamic. For maximum performance, the BSI device utilizes burst
mode transfers, with four or eight 32-bit words to a burst. To
assist the user with the burst transfer capability, the three
bits of the address which cycle during a burst are output
demultiplexed. Maximum burst speed is one 32-bit word per
clock, but slower speeds may be accommodated by inserting wait states.

3.7 TWO TIMING DOMAINS
To provide maximum performance and system flexibility, the
BSI device utilizes two independent clocks, one for the MAC
(ring) Interface, and one for the system/memory bus. The
BSI device provides a fully synchronized interface between
these two timing domains.

The BSI device can operate within any combination of cached/non-cached, paged or non-paged memory environments. To provide this capability, all data structures are contained within a page, and bus transactions never cross a
page. The BSI device performs all bus transactions within
aligned blocks to ease the interface to a cached environment.

3.8 CLUSTERED INTERRUPTS
The BSI device can be operated in a polled or interrupt-driven environment. The BSI device provides the ability to generate attentions (interrupts) at group boundaries. Some
boundaries are pre-defined in hardware; others are defined
by the user when the Channel is configured. This interrupt
scheme significantly reduces the number of interrupts to the
host, thus reducing host processing overhead.
(

2-267

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c

r---------------------------------------------------------------------------------,
4.0 Functional Description
whether they are synchronous or asynchronous, high-priority asynchronous or low-priority asynchronous, whether their
address matches an internal (BMAC device) or external address, or the header and Information fields of all non-MACI
SMTframes.
The Synchronousl Asynchronous Sort Mode is Intended for
use in end-stations or applications using synchronous transmission.
With High-priority/Low-priority sorting, high-priority asynchronous frames are sorted onto Indicate Channel 1 and
low-priority asynchronous frames are sorted onto Indicate
Channel 2. The most-significant bit of the three-bit priority
field within the FC field determines the priority. This Mode Is
intended for end stations using two priority levels of asynchronous transmission.

The BSI device is composed of the Map Engine and Interfaces to the Control Bus (Control Bus Interface), the BMAC
device (BMAC Device Interface) and the ABus (Abus Interface).
In this section, the Map Engine is described in detail to provide an in-depth look at the operation of the BSI device.
4.1 OVERVIEW
The Map Engine consists of two major blocks, the Indicate
Machine and the Request Machine. These blocks share the
Bus Interface Unit, Status/Space Machine, Pointer RAM,
and Limit RAM blocks.
The Map Engine provides an interface between the BMAC
FDDI Protocol chip and a host system. The Map Engine
transfers FDDI frames (Service Data Units) between the
FDDI device and host memory.

With External/Internal sorting, frames matching the internal
address (In the BMAC device) are sorted onto Indicate
Channel 1 and frames matching an external address (when
the EA input is asserted) are sorted onto Indicate Channel
2. This mode is intended for bridges or ring monitors, which
would utilize the ECIP/EA/EM pins with external address
matching circuitry.

4.1.1 Indicate Machine
On the Receive side (from the ring) the Indicate Machine
sequences through the incoming byte stream from the
BMAC device. Received frames are sorted onto Indicate
Channels and a decision is made whether or not to copy
them to host memory. The Indicate Machine uses the control signals provided by the BMAC device Receive State
Machine on the MAC Indicate Interface.

The proper use of the ECIP, EA, and EM pins is as follows.
External address matching circuitry must assert ECIP somewhere from the assertion of FCRCVD (from the BMAC device) up to the clock cycle before the assertion of
INFORCVD (from the BMAC device). Otherwise, the BSI device assumes that no external address comparison is taking
place. ECIP must be negated for at least one cycle to complete the external comparison. If it has not been deasserted
before EDRCVD (from the BMAC device) the frame is not
copied. EA and EM are sampled on the clock cycle aiter
ECIP is negated. ECIP is ignored aiter it is negated until
FCRCVD is asserted again.
Note that this design allows ECIP to be a positive or negative pulse. To confirm frames in this mode, (typically with
Source Address Transparency enabled), EM must be asserted within the same timeframe as EA.
With the Headerllnfo Sort Mode, Indicate Channels 1 and 2
receive all non-MAC/SMT frames that are to be copied, but
between them split the frame header (whose length is userdefined) and the remaining portions of the frame (Info). Indicate Channel 1 copies the initial bytes up until the host-defined header length is reached. The remainder of the
frame's bytes are copied onto Indicate Channel 2. Only one
IDUD stream is produced (on Indicate Channel 1), but both
PSP Queues are used to determine where the IDUs will be
written. When a multi-part IDUD is produced, the Indicate
Status field is used to determine which parts point to the
header and which point to the Info. This Mode is intended
for high-performance protocol processing applications.
The Indicate Machine filters identical MAC and SMT frames
when the SKIP bit in the Indicate Mode Register is set, and
the Indicate Configuration Register's Copy Control field (2
bits) for Indicate Channel 0 is set to 01 or 10.

4.1.2 Request Machine
On the Transmit side (to the ring) the Request Machine prepares one or more frames from host memory for transmission to the BMAC device. The Request Machine provides all
the control signals to drive the BMAC device Request Interface.
4.2 OPERATION
4.2.1 Indicate Operation
The Indicate Block accepts data from the BMAC device as a
byte stream.
Upon receiving the data, the Indicate Block performs the
following functions:
• Decodes the Frame Control field to determine the frame
type
• Sorts the received frames onto Channels according to
the Sort Mode
• Filters identical MAC frames
• Copies the received frames to memory according to
Copy Criteria
• Writes status for the received frames to the Indicate
Status Queue
• Issues interrupts to the host on host-defined status
breakpoints
The Indicate Machine decodes the Frame Control (FC) field
to determine the type of frame. Ten types of frames are
recognized: Logical Link Control (LLC), Restricted Token,
Unrestricted Token, Reserved, Station Management (SMT),
SMT Next Station Addressing, MAC Beacon, MAC Claim,
Other MAC, and Implementer.
The Indicate Machine sorts incoming frames onto Indicate
Channels according to the frame's FC field, the state of the
AFLAG signal from ihe BMAC device, and the host-defined
sorting mode programmed in the Sort Mode field of the Indicate Mode Register. SMT and MAC Service Data Units
(SDUs) are always sorted onto Indicate Channel O. On Indicate Channels 1 and 2, frames can be sorted according to

Received frames are copied to memory based on the
AFLAG and MFLAG, ECIP, EA, and EM input signals from
external address matching logic, input signals from the
BMAC device, as well as the Indicate Channel's Copy Control field. Received frames are written as a series of Input
Data Units to the current Indicate page. Each frame is
aligned to the start of a currently-defined, burst-size memory
block (16 or 32 bytes as programmed in the Mode Register's SMLB bit). The first word contains the FC only, copied
2-268

4.0 Functional Description (Continued)
into all bytes of the first word written, with the DA, SA and
INFO fields aligned to the first byte of the next word. The
format differs according to the setting of the Mode Register's BIGEND (Big Endian) bit, as shown in Figure 4-1.
Byte 0
Bit 31

Byte 3
Bit 0

Big Endlan Indicate Data Unit Format

FC

FC

FC

FC

DAO

DAI

SAO

SAl

Byte 3
Bit 31

Breakpoint bits (Breakpoint on Burst End, Breakpoint on
Service Opportunity, and Breakpoint on Threshold) in the
Indicate Mode Register, and enabling the breakpoints to
generate an attention by setting the corresponding BreakpOint bit in the Indicate Notify Register.

Little Endlan Indicate Data Unit Format

When an Indicate exception occurs, the current frame is
marked complete, status is written into an lOUD. Last, and
the Channel's Exception (EXC) bit in the Indicate Attention
Register is set.
When an Indicate error (other than a parity error) is detected, the Channel's Error (ERR) bit in the State Attention Register is set. The host must reset the INSTOP Attention bit to
restart processing on the Indicate Channel.

Byte 0
Bit 0

FC

FC

FC

FC

SAl

SAO

DAI

DAO

When parity checking is enabled and a parity error is detected in a received frame, it is recorded in the Indicate Status
field of the lOUD, and the BMAC device Parity Error (PBE)
bit in the Status Attention Register is set.

FIGURE 4·1. Indicate Data Unit Formats
(Short Addresses)

4.2.2 Request Operation
The Request Block transmits frames from host memory to
the BMAC device. Data is presented to the BMAC device as
a byte stream.

For each Input Data Unit, the Indicate Machine creates an
Input Data Unit Descriptor (lOUD), which contains status information about the IOU, its size (byte count), and its location in memory. For IDUs that fit within the current Indicate
page, an IDUD.Only Descriptor is created. For IDUs that
span more than one page, a mUlti-part lOUD is created, i.e.,
when a frame crosses a page boundary, the BSI device
writes an IDUD.First; if another page is crossed, an
IDUD.Middle will be written; and at the frame end, an
IDUD.Last is written. IDUDs are written to consecutive loca·
tions in the Indicate Status Queue for the particular Indicate
Channel, up to the host-defined queue limit.

The Request Block performs the following functions:
• Prioritizes active requests to transmit frames
•
•
•
•

Requests the BMAC device to obtain a token
Transmits frames to the BMAC device
Writes status for transmitted and returning frames
Issues interrupts to the host on user-defined group
boundaries
The Request Machine processes requests by reading Request Descriptors from the REQ Queue, then assembling
frames of the specified service class, frame control and expected status for transmission to the BMAC device. Request and ODUD Descriptors are checked for consistency,
and the Request Class is checked for compatibility with the
current ring state. When an inconsistency or incompatibility
is detected, the request is aborted.
When a consistency failure occurs, the Request is terminated with appropriate status. The Request Machine then locates the end of the current object (REQ or ODUD). If the
current Descriptor is not the end (Last bit not set), the Request Machine will fetch subsequent Descriptors until it detects the end, then resume processing with the next Descriptor.First or Descriptor.Only.
Requests are processed on both Request Channels simultaneously. Their interaction is determined by their priorities
(Request Channel 0 has higher priority than Request Channell) and the Hold and Preempt/Prestage bits in the Request Channel's Request Configuration Register. An active
Request Channel 0 is always serviced first, and may be programmed to preempt Request Channel I, such that uncommitted Request Channell's data already in the request
FIFO will be purged and then refetched after servicing Request Channel o. When prestaging is enabled, the next
frame is staged before the token arrives. Prestaging is always enabled for Request Channel 0, and is a programmable option on Request Channell.
When a REQ.First is loaded, the Request Machine commands the BMAC device to capture a token of the type
specified in the REQ Descriptor, and concurrently fetches
the first ODUD. If prestaging is enabled, or a service opportunity exists for this Request Channel, data from the first

The Indicate Machine copies IDUs and IDUDs to memory as
long as there are no exceptions or errors, and the Channel
has data and status space. When a lack of either data or
status space is detected on a particular Channel, the Indicate Machine stops copying new frames for that Channel
(only). It will set the No Status Space attention bit in the No
Space Attention Register when it runs out of Status Space.
It will set the Low Data Space bit in the No Space Attention
Register when the last available PSP is prefetched from the
Indicate Channel PSP Queue. The host allocates more data
space by adding PSPs to the tail of the PSP Queue and then
updating the PSP Queue Limit Register, which causes the
BSI device to clear the Low Data Space attention bit and
resume copying (on the same Channel). The host allocates
more status space by updating the lOUD Queue Limit Register and then explicitly clearing the Channel's No Status
Space bit, after which the Indicate Machine resumes copying.
The BSI device provides the ability to group incoming
frames and then generate interrupts (via attentions) at
group boundaries. To group incoming frames, the BSI device defines status breakpoints, which identify the end of a
group (burst) of related frames. Status breakpoints can be
enabled to generate an attention.
The breakpoints for Indicate Channels are defined by the
host in the Indicate Mode, Indicate Notify, and Indicate
Threshold registers. Status breakpoints include Channel
change, receipt of a token, SA change, DA change, MAC
Info change, and the fact that a user-specified number of
frames have been copied on a particular Indicate Channel.
Status breakpoint generation may be individually enabled
for Indicate Channels 1 and 2 by setting the corresponding

2-269

4.0 Functional Description

(Continued)
ODU is loaded into the Request FIFO, and the BSI device
requests transmission from the BMAC device. When the
BMAC device has captured the appropriate token and the
frame is committed to transmission (the FIFO threshold has
been reached or the end of the frame is in the FIFO), transmission begins. The BSI device fetches the next ODUD and
starts loading the ODUs of the next frame into the FIFO.
This continues (across multiple service opportunities if required) until all frames for that Request have been transmitted (I.e., an REO.ONLY or an REO. LAST is detected), or an
exception or error occurs, which prematurely ends the Request.
The BSI device will load REO Descriptors as long as the
ROSTOP bit in the State Attention Register is Zero, the
REO Oueue contains valid entries (the REO Oueue Pointer
Register does not exceed the REO Oueue Limit Register),
and there is space in the CNF Oueue (the CNF Oueue
Pointer Register is less than the CNF Oueue Limit Register).

frames are ignored by the BSI device. The frame count ends
when any of the following conditions occur:
1. All the frames have been transmitted, and the transmitted
and confirmed frame counts are equal.
2. There is a MACRST (MAC Reset).
3. The state of the ring-operation has changed.
4. A stripped frame or a frame with a parity error is received.

5. A non-matching frame is received.
6. A token is received.
When Source Address Transparency is selected (by setting
the SAT bit in the Request Configuration Register) and Full
confirmation is enabled, confirmation begins when a frame
end is detected with either MFLAG or EM asserted.
When a non-matching frame is received, the BSI device
ends the Request, and generates the Request Complete
(RCM), Exception (EXC), and Breakpoint (BRK) attentions.
Any remaining REOs in the Request object are fetched until
a REO.Last or REO.Only is encountered. Processing then
resumes on the next REO.First or REO.Only (any other type
of REO would be a consistency failure).
Request errors and exceptions are reported in the State
Attention Register, Request Attention Register, and the
Confirmation Message Descriptor. When an exception or error occurs, the Request Machine generates a CNF and
ends the Request. The Unserviceable Request (USR) attention is set to block subsequent Requests once one becomes unserviceable.

Request status is generated as a single confirmation object
(single- or multi-part) per Request object, with each confirmation object consisting of one or more CNF Descriptors.
The type of confirmation is specified by the host in the Confirmation Class field of the REO Descriptor.
The BSI device can be programmed to generate CNF Descriptors at the end of the Request object (End Confirmation), or at the end of each token opportunity (Intermediate
Confirmation), as selected in the E and I bits of the Request
Class Field of the REO Descriptor. A CNF Descriptor is always written when an exception or error occurs (regardless
of the value in the Confirmation Class field), when a Request completes (for End or Intermediate Confirmation
Class), or when an enabled breakpoint occurs (Intermediate
Confirmation Class only).

4.2.3 State Machines
There are three state machines under control of the host:
the Request Machine, the Indicate Machine, and the
Status/Space Machine. Each Machine has two Modes:
Stop and Run. The Mode is determined by the setting of the
Machine's corresponding STOP bit in the State Attention
Register. The STOP bits are set by the BSI device when an
error occurs or may be set by the user to place the Machine
in Stop Mode.
The BSI Control Registers may be programmed only when
all Machines are in Stop Mode. When the Status/Space
Machine is in Stop Mode, only the Pointer RAM and Limit
RAM Registers may be programmed.
When the Indicate and Request Machines are in Stop
Mode, all indicate and request operations are halted. When
the Status/Space Machine is in Stop Mode, only the PTOP
and LMOP service functions can be performed.

There are three basic types of confirmation: Transmitter,
Full, and None. With Transmitter Confirmation, the BSI device verifies that the Output Data Units were successfully
transmitted. With Full Confirmation, the Request Machine
verifies that the ODUs were successfully transmitted, that
the number of (returning) frames "matches" the number of
transmitted ODUs, and that the returning frames contain the
expected status. When the None Confirmation Class is selected, confirmation is written only if an exception or error
occurs.
For Full Confirmation, a matching frame must meet the following criteria:
1. The frame has a valid Ending Delimiter (ED).
2. The selected bits in the FC fields of the transmitted and
received frames are equal (the selected bits are specified
in the FCT bit of the Request Configuration Register).
3. The frame is My_SA (MFLAG or both SAT & EM asserted).
4. The frame matches the values in the Expected Frame
Status Register.

4.3 BUS INTERFACE UNIT
4.3.1 Overview
The ABus provides a 32-bit wide synchronous multiplexed
address/data bus for transfers between the host system
and the BSI device. The ABus uses a bus request/bus grant
protocol that allows multiple bus masters, supports burst
transfers of 16 and 32 bytes, and supports virtual and physical addressing using fixed-size pages. The BSI is capable of
operating directly on the system bus to main memory, or
connected to external shared memory.

5. FCS checking is disabled or FCS checking is enabled and
.
the frame has a valid FCS.
6. All bytes from FC to ED have good parity (when the
FLOW bit in the Mode Register is set, i.e., parity checking
is enabled).
The confirmed frame count starts after the first Request
burst frame has been committed by the BMAC device, and
when a frame with MY_SA is received. Void and My_Void

All bus signals are synchronized to the master bus clock.
The maximum burst speed is one, 32-bit word per clock, but
slower speeds may be accommodated by inserting wait
states. The user may use separate clocks for the ring (FDDI
MAC) and system (ABus) interfaces. The only restriction is
that the ABus clock must be at least as fast as the ring clock

2-270

C

"U

4.0 Functional Description

01)
Co)

(Continued)
(lBC). It is important to note that all ABus outputs change
and all ABus inputs are sampled on the rising edge of
AB_ClK.

Burst transfers are always word-aligned on a 16- or 32-by1e
(burst-size) address boundary. Burst transfers will never
cross a burst-size boundary. If a 32-by1e transfer size is chosen, the BSI device will perform both 16-by1e and 32-by1e
bursts, whichever is most efficient (least number of clocks
to load/store all required data).
The Bus Interface Unit can operate in either Big Endian or
Little Endian Mode. The bit and by1e alignments for both
modes are shown in Figure 4-2. Byte 0 is the first by1e received from the ring or transmitted to the ring.

Addressing Modes
The Bus Interface Unit has two Address Modes, as selected
by the user: Physical Address Mode and Virtual Address
Mode. In Physical Address Mode, the BSI device emits the
memory address and immediately begins transferring the
data. In Virtual Address Mode, the BSI device inserts two
clock cycles and TRI-STATE™s the address between emitting the virtual address and starting to transfer the data. This
allows virtual-to-physical address translation by an external
MMU.

N

en

U1

Bus Arbitration
The ABus is a multi-master bus, using a simple Bus Request/Bus Grant protocol that allows an external Bus Arbiter to support any number of bus masters, using any arbitration scheme (e.g., rotating or fixed priority). The protocol
provides for multiple transactions per tenure, and bus master preemption.
The BSI device asserts a Bus Request, and assumes mastership when Bus Grant is asserted. If the BSI device has
another transaction pending, it will keep Bus Request asserted, or reassert it before the completion of the current
transaction. If Bus Grant is (re)asserted before the end of
the current transaction, the BSI device retains mastership
and runs the next transaction. This process may be repeated indefinitely.

The BSI device interfaces to byte-addressable memory, but
always transfers information in words. The BSI device uses
a word width of 32 data bits plus 4 (1 per byte) parity bits.
Parity may be ignored.
Bus Transfers
The bus supports several types of transactions. Simple
reads and writes involve a single address and data transfer.
Burst reads and writes involve a single address transfer followed by multiple data transfers. The BSI device provides
the incrementing address bits during the burst transaction.
Burst sizes are selected dynamically by the BSI.
On Indicate Channels, when 8-word bursts are enabled, all
transactions will be 8 words until the end of the frame; the
last transfer will be 4 or 8 words, depending on the number
of remaining by1es. If only 4-word bursts are allowed, all
Indicate Data transfers are 4 words.
On Request Channels, the BSI will use 4- or 8-word bursts
to access all data up to the end of the ODU. If 8-word bursts
are enabled, the first access will be an 8-word burst if the
ODU begins less than 4 words from the start of an 8-word
burst boundary. If 8-word bursts are not allowed, or if the
ODU begins 4 or more words from the start of an 8-word
burst boundary, a 4-word burst will be used. The BSI will
ignore unused bytes if the ODU does not start on a burst
boundary. At the end of an ODU, the BSI will use the smallest transfer size (1, 4, or 8 words) which completes the ODU
read. To coexist in a system that assumes implicit wraparound for the addresses within a burst, the BSI device never emits a burst that will wrap the 4- or 8-word boundary.

If the Bus Arbiter wishes to preempt the BSI device, it deasserts Bus Grant. The BSI device will complete the current
bus transaction, then release the bus. From preemption to
bus release is a maximum of (11 bus clocks + (8 times the
number of memory wait states» bus clocks. For example, in
a 1 wait-state system, the BSI device will release the bus
within a maximum of 19 bus clocks.
Big-Endian Byte Order

0[31]

0[0]
Word

HalfwordO
By1eO

I

By1e1

I
I

Halfword 1
By1e2

I

By1e3

llttle-Endian Byte Order

0[31]

A Function Code identifying the type of transaction is output
by the BSI device on the upper four address bits during the
address phase of a data transfer. This can be used for more
elaborate external addressing schemes, for example, to direct control information to one memory and data to another
(e.g., an external FIFO). To assist the user with the burst
transfer capability, the BSI device also outputs three demultiplexed address bits during a burst transfer. These indicate
the next word within a burst to be accessed.

0[0]
Word

Halfword 1
By1e3

I

By1e2

I
I

HalfwordO
Byte 1

I

By1eO

FIGURE 4-2. ABus Byte Orders
Parity
There are two options for parity: one for systems using parity, the other for systems not using parity. Parity checking on
the ABus can be disabled by clearing the FLOW bit in the
Mode Register. When parity is enabled (FLOW bit is set), it
operates in flow-through mode on the main datapath, that
is, parity is not checked at the ABus but simply flows between the ABus and the BMAC device interface, and is
checked by the BMAC device as it is received. When the
FLOW bit is set, parity checking is also enabled on the Control Bus and MAC Indicate Interfaces.
The BSI device generates parity on all addresses output on
the ABus.

Byte Ordering
The basic addressable quantum is a byte, so request data
may be aligned to any by1e boundary in memory. All information is accessed in 32-bit words, however, so the BSI
device ignores unused bytes when reading.
Descriptors must always be aligned to a word address
boundary. Input Data Units are always aligned to a burstsize boundary. Output Data Units may be any number of
by1es, aligned to any by1e-address boundary, but operate
most efficiently when aligned to a burst-size boundary.

2-271

fII

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

~

CO)

~

c

4.0 Functional Description (Continued)
Bandwidth
The ABus supports single reads and writes, and burst reads
and writes. With physical addressing, back-to-back single
reads/writes can take place every four clock cycles. Burst
transactions can transfer 8, 32·bit words (32 bytes) every 11
clock cycles. With a 25 MHz clock this yields a peak bandwidth of 72.7 Mbytes/sec.

two Burst FIFOs, each containing two banks of 32 bytes,
which provide ABus bursting capability.
The amount of latency covered by the Data FIFO plus one
of the banks of the Burst FIFO must meet the average and
maximum bus latency of the external memory. With a new
byte every 80 ns from the ring, a 64-byte FIFO provides
64 x 80 = 5.12,..s maximum latency.
To assist latency issues, the BSI device can completely
empty or fill the Burst FIFO in one bus tenure by asserting
Bus Request for multiple transactions. Since one bank of
the Burst FIFO is 8 words deep, if 8-word bursts are enabled, that half of the Burst FIFO can be emptied in one
transaction. If the second half of the burst FIFO is also full, it
can be emptied in the same bus tenure by again granting
the bus to the BSI device.
The BSI device may be preempted at any time by removing
Bus Grant, which causes the BSI device to complete the
current transaction and release the bus. There will be a
maximum of 11 clocks (plus any memory wait states) from
preemption to bus release (fewer if 8-word bursts are not
enabled).

To allow the bus to operate at high frequency, the protocol
defines all signals to be both asserted and deasserted by
the bus master and slaves. Having a bus device actively
deassert a signal guarantees a high-speed inactive transition. If this were not defined, external pull-up resistors
would not be able to deassert signals fast enough. The protocol also reduces contention by avoiding cases where two
bus devices simultaneously drive the same line.
The BSI device operates synchronously with the ABus
clock. In general, operations will be asynchronous to the
ring, since most applications will use a system bus clock
that is asynchronous to the ring. The BSI device is designed
to interface either directly to the host's main system bus or
to external shared memory. When interfaced to the host's
bus, there are two parameters of critical interest: latency
and bandwidth.

4.3.2 Bus Ststes
An ABus Master has eight states: idle (Ti), bus request
(Tbr), virtual address (Tva), MMU translate (Tmmu), physical
address (Tpa) , data transfer (Td), wait (Tw) and recovery
(Tr). The ABus Master state diagram is shown In Figure 4-3.
An ABus Slave has five states: idie (Ti), selected (Ts), data
transfer (Td), wait (Tw), and recovery (Tr).

Data moves between the Request and Indicate Channels
and the ABus via four FIFOs, two in the receive path (Indicate) and two in the transmit path (Request). On the BMAC
Device Interface, there are two, 16 x 32 bit data FIFOs for
Indicate and Request data. On the ABus Interface, there are

2-272

01:0.

BO:Ti

--.-(00)

Bl:Tbr
!rqst

]

B2:Tpo

rqst

(01)

AB_BR;ociLrqst

~I (23b)

ABiiG &; imode.VIRT
AB-AS;AB_SIZO;AB-AO;AB-AD(Addr);

(12)

--.-

-

I

e!..

B3:Td

--.-(23a)

iAB_BG
(11)-=
AB_BR

bursLend

AB-DEN;iAB-AS;losLdoto;AB-AD(doto)
!bursLend
AB_DEN;AB-AD(doto)

-+
~

II(read)AB_R/W=I;else AB_R/W=O

AB_BG

&;

mode.VIRT

B5:Tvo

B6:Tmmu

-.-

-,-

(15)

~I

(62)

AB-AS;AB_SIZO;AB-AO;A8-AD(Addr );
II(reod)A8_R/W=I;else ALR/W=O

(56)

TRISTATE

AB-ACK

&;

bursLend

&;

!losLdota

10sLdato;iAB-AS

---+

(330)

AiLACK &: !bursLend &: !lasLdata

~I

I

(33b)

nexLdata

(AB-AD)
85:Tr

(:)
."
c::::
:::J

n

0"
:::J

cCD

en
.,n
-6"

c)"
:::J

'§
a
5'
t:

B4:Tw

(D

.90

14

'".....

'"'"

14

rqst
ockJqst

iAiLACK

-.(51)

ilosLdoto

(50)

'AB-ACK &; bursLend
•
!AB-AS;losLdoto

(44a)

I
!A8-ACK

irqst
TRISTATE(oU outputs)

&;

~

&;

10sLdoto

(44b)

iAB-ACK

14

&;

(340)

ibursLend

)
(34b

!A8-AS;losLdoto
(43a)

A8-ACK

&;

bursLend

&;

ilosLdoto

!AB-AS;losLdoto

14

A8-ACK

&;

10sLdota
(45)

1

4

AB-ACK
(43b)

Negote(AB_SIZO.A8_R/W.AB_DEN);
TRISTATE(AB-AS)
AB-ACK

&;

lasLdoto

&;

!bursLend

nexLdata

~I

(35)

Negate(AB_SIZO.AB_R/W.A8-DEN); TRISTATE(A8-AS)
TUF/l0791-6

Note 1: If (AB-AGK) nexLdata decrements bursLcQunt, processes data.
Note 2: BursLcount is pipelined 1 ahead, so is true in last Td state.

Note 3: II (AB-ACK) lasLdata negates AB-AS. processes data.
Note 4: Timing for AB_BR not shown.

FIGURE 4-3. BSI Device ABus Master State Machine (from the BSI Device)

S9l!£8dO

II

~

CD

,-------------------------------------------------------------------------,

~

4.0 Functional Description (Continued)

a.

Master States
The Ti state exists when no bus activity is required. The BIU
does not drive any of the bus signals when it is in this state
(all are released). If the BIU requires bus service, it may
assert Bus Request.
When a transaction is run, the BIU enters Tbr and asserts
Bus Request, then waits for Bus Grant to be asserted.

CD

Q

cle). If the slave can drive data at the rate of one word per
clock (in a burst), it keeps ABJCK asserted.
Following the final Td/Tw state, the BIU enters a Tr state to
allow time to turn off or turn around bus transceivers.
A bus retry request is recognized in any Td/Tw state. The
BIU will go to a Tr state and then rerun the transaction when
it obtains a new Bus Grant. The whole transaction is retried,
i.e., all words of a burst. Additionally, no other transaction
will be attempted before the interrupted one is retried. The
BIU retries indefinitely until either the transaction completes
successfully, or a bus error is signaled.

The state following Tbr is either Tva or Tpa. In Virtual Address Mode, the BIU enters Tva and drives the virtual address and size lines onto the bus. In Physical Address
Mode, Tpa occurs next (see Section 4.3.3).
Following a Tva state is a Tmmu state. During this cycle the
external MMU is performing a translation of the virtual address emitted during Tva.

Bus errors are recognized in Td/Tw states.

4.3.3 Physical Addressing Bus Transactions
Bus transactions in Physical Address Mode are shown in
Figure 4-4 through 4-7. BSI device signals are defined in
Chapter 6.

Following a Tmmu state (when using virtual addressing) or a
Tbr state (when using physical addressing), is the Tpa state.
During the Tpa state, the BSI device drives the read/write
strobes and size signals. In physical address mode, it also
drives ABJD with address. In virtual address mode, the
BSI device TRI-STATEs AB_BD so the host CPU or MMU
can drive the address.

Single Read
Tbr:
BSI device asserts AB_BA to indicate it wishes to
perform a transler. Host asserts AB_BG. Moves to
Tpa on the next clock.
BSI device drives ABJ and ABJD with the adTpa:
dress, asserts ABJS, drives AB~W and
AB_SIZ[2:0], negates AB_BR if another transaction is not required.

Following the Tpa state, the BIU enters the Td state to
transfer data words. Each data transfer may be extended
indefinitely by inserting Tw states. A slave acknowledges by
asserting ABJCK and transferring data in a Td state (cylbr

AB~R

~~~

lbr

Tpa

Tr

Td

______~~~

F%a~A_

lbr

--------------~~a-

-

A1LRW

address

______~'b_~~----~~~~__________~~_-------

BSI addr

AB-AD(31:0)

Tr

Tw

Td

______________________________________

address

AB-A(4:2)

Tpa

Slave data

BSI data

~

>?< >;>~------~;>---------

t2221

'2223

12,,3
P221

F%a

IZZZ3...--

WI

IZZZ3...--

V,)]

Master B - - - -..

TUF/l0791-7

FIGURE 4·4. ABus Single Read, Physical Addressing, 0 W-S, 1 W-S, Bus Handover

2·274

4.0 Functional Description
Td:

Tr:

(Continued)

BSI device negates ABJS, asserts AB_DEN,
samples ABJCK and AB_ERR. Slave asserts
ABJCK, drives AB_ERR, drives ABJD (with
data) when ready. The BSI device samples a valid
ABJCK, capturing the read data. Tw states may
occur after Td.
BSI
device
negates
AB_RW,
AB_DEN,
AB_SIZ[2:01. releases ABJ, and ABJS. Slave
deasserts ABJCK and AB_ERR, releases
ABJD

Tpa: BSI device drives ABJ and ABJD with the ad-

Td:

Tr:

Single Write

Tbr:

BSI device asserts AB_BR to indicate it wishes to
perform a transfer. Host asserts AB_BG. Moves to
Tpa on the next clock.
Tbr

Tbr

Tpa

Td

Tr

Tbr

dress, asserts ABJS, drives AB_RW and
AB_SIZ[2:01. and negates AB_BR if another transaction is not required.
BSI device negates ABJS, asserts AB_DEN,
drives ABJD with the write data and starts sampling ABJCK and AB_ERR. Slave captures
ABJD data, asserts ABJCK, drives AB_ERR.
Tw states may occur after Td if the slave deasserts
ABJCK.
BSI
device
negates
AB_RW,
AB_DEN,
AB_SIZ[2:01, releases ABJ, ABJD, ABJS.
Slave deasserts ABJCK and AB_ERR, and stops
driving ABJD with data.
Tpa

----------~~~

____~»u~------0g~__________~»~~~-----

BSI addr
AB..AD(31 :0)

Tr

address

address

AB..A(4:2)

Tw

Td

BSI data

BSI addr

0g

}'?(

};;>

(2223

®

')<2)

BSI data

«Z2)

1/2;3

1/223

M

'2223

23

M

.2223

2a

Master B
TL/F/l0791-B

FIGURE 4-5. ABus Single Write, Physical Addressing, a W-S, 1 W-S, Bus Handover

2-275

fII

4.0 Functional Description

(Continued)

Td:

Burst Read
Tbr: BSI device asserts AB_BR to indicate it wishes to
perform a transfer. Host asserts AB_BG. Moves to
Tpa on the next clock.
Tpa: BSI device drives ABJ and ABJD with the address, asserts ABJS, drives AB_RW and
AB_SIZ[2:0], and negates AB_BR if another transaction is not required.

AB~R

~~~______~~~

~~~________________________________________

•

addre •• (n)

AB..A{4:2)

addre •• (n + I)

addro •• (n + 2)

addr... (n + 3)

addre .. (n)

_____*£".aill....____..*r.:2i_____*I2!l...____....»,~~

--------~"'~_ _MiIE~
BSI addr

AB..AD{31:0)

Tr:

BSI device asserts AB_DEN, samples AECACK
and AB_ERR, increments the address on ABJ.
Slave asserts ABJCK, drives AB_ERR, and
drives ABJD (with data) when ready. BSI device
samples a valid ABJCK, capturing the read data.
Tw states may occur after Td. Td state is repeated
four or eight times (according to the burst size). On
the last Td state, the BSI device negates AB.::AS.
BSI
device
negates
AB_RW,
AB_DEN,
AB_SIZ[2:0], and releases ABJ and ABJS.
Slave deasserts ABJCK and AB_ERR, and releases ABJD.

Slave data{n)

-----------¢(

Slave dat.{n+l)

»----« »--

Siavo dat.{n+2)

»>---« »>---«

_____________~~_____I~~
--------,~ZZL_
««1
~

Siavo data{n+3)

1222J
-----

12 223
AB-SIZ{2:0)

________

~~,.~~--------------------------.~~ft--

AB~EN -------------------~ZL

12223

__________________________________________

r

AB..ACK _______________.....JtlZ?4

--,LW.!

~

f@

~

I~~

~

~~.,."..--r...
It?.,.,~""~---'rmr-"""
TL/F110791-9

FIGURE 4·6. ABus Burst Read, Physical Addressing, 16 Bytes, 1 W-S

2·276

C

"tI

4.0 Functional Description (Continued)

Q)
Co)

Td:

Burst Write
Tbr: BSI device asserts AB_BR to indicate it wishes to
perform a transfer. Host asserts AB_BG. Moves to
Tpa on the next clock.
Tpa: BSI device drives ABJ and ABJD with the address, asserts ABJS, drives AB_RW and
AB_SIZ[2:01, and negates AB_BR if another transaction is not required.

AO~R

~~~______~~~

•a

~~~__________________________________________

addre •• (n + 1)

addre .. ?<

addre •• (n + 2)

OSI data (n + 1)

OSI data (n)

OSI addr

>?<

address (n + 3)

>?<

>?<
>?<

address (n)

>?<
OSI data (n + 2)

>?<

OSI dota (n + 3)

>?<
f@I

»-»--

P2?d

AO...AS

t2223

AO_RW

12223

w.r

®

~

AO_SIZ(2:0)

AD_DEN

AO...ACK

wa-

12223
f221

L.W.I E%I f%I

~

~

VAl rmrTLlF/l0791-10

FIGURE 4-7. ABus Burst Write, Physical Addressing, 16 Bytes 1 W-S

2-277

N

en

UI

4.0 Functional Description

(Continued)

4.3.4 Virtual Addressing Bus Transactions

Burst Read
BSI device asserts AB_BR to indicate it wishes to
Tbr:
perform a transfer. Host asserts AB_BG, BSI
drives ABJ and ABJD when AB_BG is asserted. Moves to Tva on the next clock.
Tva: BSI device drives ABJ and ABJD with the virtual address for one clock, negates ABJS, asserts
AB_RW, drives AB_SIZ[2:0], and negates
AB_BR if another transaction is not required.
Tmmu: Host MMU performs an address translation during
this clock.
Tpa: Host MMU drives ABJD with the translated (physical) address. BSI device drives ABJ and asserts
ABJS.
Td:
BSI device asserts AB_DEN, samples ABJCK
and AB_ERR. Slave asserts ABJCK, drives
AB_ERR, drives ABJD (with data) when ready.
BSI device samples a valid ABJCK, capturing the
read data. Tw states may occur after Td. This state
is repeated four or eight times (according to burst
size). On the last Td state the BSI device negates
ABJS.
BSI device negates AB_RW,
AB_DEN,
Tr:
AB_SIZ[2:01, releases ABJ and ABJS. Slave
deasserts ABJCK and AB_ERR, and releases
ABJD.

Single Read
BSI device asserts AB_BR to indicate it wishes to
Tbr:
perform a transfer. Host asserts AB_BG, and B~I
device drives ABJ and ABJD when AB_BG IS
asserted. Moves to Tva on the next clock.
Tva: BSI device drives ABJ and ABJD with the virtual address for one clock, negates ABJS, asserts
AB_RW, drives AB_SIZ[2:01, and negates
AB_BR if another transaction is not required.
Tmmu: Host MMU performs an address translation during
this clock.
Tpa: Host MMU drives ABJD with the translated (physical) address, BSI device drives ABJ and asserts
ABJS.
Td:
BSI device negates AB::AS, asserts AB_DEN,
samples ABJCK and AB_ERR. Slave asserts
ABJCK, drives AB_ERR, drives ABJD (with
data) when ready. BSI device samples a valid
ABJCK, capturing the read data. Tw states may
occur after Td.
Tr:
BSI device negates AB_RW, AB_DEN, and
AB_SIZ[2:01, releases ABJ and ABJS. Slave
deasserts ABJCK and AB_ERR and releases
ABJD.
Single Write
BSI device asserts AB_BR to indicate it wishes to
Tbr:
perform a transfer. Host asserts AB_BG, BSI d~.
vice drives ABJ and ABJD when AB_BG IS
asserted. Moves to Tva on the next clock.
Tva: BSI device drives ABJ and ABJD with the virtual address for one clock, negates ABJS, negates
AB_RW, and drives AB_SIZ[2:0].
Tmmu: Host MMU performs an address translation during
this clock.
Tpa: Host MMU drives ABJD with the address, BSI device drives ABJ asserts ABJS, and negates
AB_BR if another transaction is not required.
Td:
BSI device negates ABJS, asserts AB_DEN,
drives ABJD with the write data and starts sampling ABJCK and AB_ERR. Slave captures
ABJD data, asserts ABJCK, and drives
AB_ERR.
BSI device samples a valid
ABJCK. Tw states may occur after Td.
Tr:
BSI device negates AB_RW, "'"A=B_--":D""EN"',
AB SIZ[2:01, releases ABJ, ABJD, and
ABJS. Slave deasserts ABJCK and
AB_ERR, and stops driving ABJD with data.

Burst Write
Tbr:
BSI device asserts AB_BR to indicate it wishes to
perform a transfer. Host asserts AB_BG, BSI d~­
vice drives ABJ and ABJD when AB_BG IS
asserted. Moves to Tva on the next clock.
Tva: BSI device drives ABJ and ABJD with the virtual address for one clock, negates ABJS, negates
AB_RW, drives AB_SIZ[2:0].
Tmmu: Host MMU performs an address translation during
this clock.
Tpa: Host MMU drives ABJD with the address, BSI device drives ABJ asserts ABJS, and negates
AB_BR if another transaction is not required.
Td:
BSI device asserts AB_DEN, drives ABJD with
the write data and starts sampling ABJCK and
AB_ERR. Slave captures ABJD data, asserts
ABJCK and drives AB_ERR. BSI device samples a valid ABJCK. Tw states may occur after
Td. This state is repeated as required for the complete burst. On the last Td state, the BSI device
negates ABJS.
Tr:
BSI
device negates AB_RW,
AB_DEN,
AB_SIZ[2:01, releases ABJ, ABJD, ABJS.
Slave deasserts ABJCK and AB_ERR, stops
driving ABJD with data.

2-278

5.0 Control Information
5.1 OVERVIEW
Control information includes the parameters that are used
to manage and operate the BSI device.
Control information is divided into four basic groups: Opera·
tion Registers, Pointer RAM Registers, Limit RAM Regis·
ters, and Descriptors. The Control information Register Ad·
dress Space is shown in Table 5·1.
Operation registers are accessed directly via the Control
Bus. Limit RAM Registers are accessed indirectly via the
Control Bus, using the Limit RAM Data and Limit RAM Ad·
dress Registers. The Pointer RAM Registers are accessed
indirectly via the Control Bus and ABus using the Pointer
RAM Address and Control Register, the Mailbox Address
Register, and a mailbox location in ABus memory.

• Limit Address Register (LAR) is used to program the
parameters and data used in the LMOP (Limit RAM Op·
eration) service function.
• Limit Data Register (LOR) is used to program the data
used in the LMOP service function.
o Request Channel 0 Configuration Register (ROCR) is
used to program the operational parameters for Request
ChannelO.
o Request Channel 1 Configuration Register (R1CR) is
used to program the operational parameters for Request
Channell.
• Request Channel 0 Expected Frame Status Register
(ROEFSR) defines the expected frame status for frames
being confirmed on Request Channel O.
o Request Channel 1 Expected Frame Status Register
(R1EFSR) defines the expected frame status for frames
being confirmed on Request Channell.
o Indicate Threshold Register (ITR) is used to specify a
maximum number of frames that can be copied onto an
Indicate Channel before a breakpoint is generated.

5.2 OPERATION REGISTERS
The Operation Registers are divided into two functional
groups: Control Registers and Event Registers. They are
shown in Table 5·2.
Control Registers
The Control Registers are used to configure and control the
operation of the BSI device.

o Indicate Mode Register (IMR) specifies how the incom-

ing frames are sorted onto Indicate Channels, enables
frame filtering, and enables breakpoints on various burst
boundaries.
o Indicate Configuration Register (ICR) is used to program the copy criteria for each of the Indicate Channels.

The Control Registers include the following registers:
• Mode Register (MR) establishes major operating pa·
rameters for the BSI device.
• Pointer RAM Control and Address Register (PCAR) is
used to program the parameters for the PTOP (Pointer
RAM Operation) service function.

• Indicate Header Length Register (IHLR) defines the
length of the frame header for use with the Header/Info
Sort Mode.

• Mailbox Address Register (MBAR) is used to program
the memory address of the mailbox used in the data
transfer of the PTOP service function.

Table 5.1 Control Register Address Space
Address
Range

Description

Read
Conditions

Write
Conditions

00-IFh
00-15h*
0-9h*'

Operation Registers
Pointer RAM Registers
Limit RAM Registers

Always
Always
Always

Always (Conditional)
Always
Always

'Bits 0-4 of Pointer RAM Address and Control Register
"Bits 4-7 of Limit RAM Address Register

2-279

5.0 Control Information (Continued)
TABLE 5-2. Control and Event Registers
Register
Group

Address

Access Rules

Register Name

Write

Read

C

00

Mode Register (MR)

Always

C

01

Reserved

N/A

Always
N/A

C

02

Pointer RAM Control and Address Register (PCAR)

Always

Always

C

Always

03

Mailbox Address Register (M8AR)

Always

E

04

Master Attention Register (MAR)

Always

Data Ignored

E

05

Master Notify Register (MNR)

Always

Always

E

06

State Attention Register (STAR)

Always

Conditional

E

07

State Notify Register (STNR)

Always

Always

E

08

Service Attention Register (SAR)

Always

Conditional

E

09

Service Notify Register (SNR)

Always

Always

E

OA

No Space Attention Register (NSAR)

Always

Conditional

E

08

No Space Notify Register (NSNR)

Always

Always

C

OC

Limit Address Register (LAR)

Always

Always

C

OD

Limit Data Register (LDR)

Always

Always

E

OE

Request Atlention Register (RAR)

Always

Conditional

E

OF

Request Notify Register (RNR)

Always

Always

C

10

Request Channel 0 Configuration Register (ROCR)

Always

Always

C

11

Request Channel 1 Configuration Register (R1 CR)

Always

Always

C

12

Request Channel 0 Expected Frame Status Register (ROEFSR)

Always

Always

C

13

Request Channel 1 Expected Frame Status Register (R1 EFSR)

Always

Always

E

14

Indicate Atlention Register (IAR)

Always

Conditional

E

15

Indicate Notify Register (INR)

Always

Always

C

16

Indicate Threshold Register (ITR)

Always

INSTOP Mode
or EXC = 1 Only

C

17

Indicate Mode Register (lMR)

Always

INSTOPMode
Only

C

18

Indicate Configuration Register (ICR)

Always

Always

C

19

Indicate Header Length Register (IHLR)

Always

INSTOPMode
or EXC = 1 Only

1A-C
E

1F

Reserved

N/A

N/A

Compare Register (CMP)

Always

Always

C - Control Register
E = Event Register

2-280

5.0 Control Information (Continued)
TABLE 5·3. Control and Event Registers Following Reset

Address

Register

00

Mode Register

00

02

Pointer RAM Control and Address Register

NA

03

Mailbox Address Register

04

Master Attention Register

00

05

Master Notify Registers

00

.

06

State Attention Register

07

07

State Notify Register

00

08

Service Attention Register

OF

09

Service Notify Register

00

OA

No Space Attention Register

FF

OB

No Space Notify Register

00

OC

Limit Address Register

NA

00

Limit Data Register

NA

OE

Request Attention Register

00

OF

Request Notify Register

00

10

Request Channel 0 Configuration Register

NA

11

Request Channell Configuration Register

NA

12

Request Channel 0 Expected Frame Status Register

NA

13

Request Channell Expected Frame Status Register

NA

14

Indicate Attention Register

00

15

Indicate Notify Register

00

16

Indicate Threshold Register

NA

17

Indicate Mode Register

NA

18

Indicate Configuration Register

NA

19

Indicate Header Length Register

NA

lF

Compare Register

NA

• = Initialized to a silicon Revision code upon reset. The Revision code remains until it is overwritten by the host.

NA

Reset

= Not altered upon reset.

2·281

U)

CD
C\I

C")

~

c

r---------------------------------------------------------------------------------,
5.0 Control Information (Continued)
Event Registers
The Event Registers record the occurrence of events or series of events. Events are recorded and contribute to generating the
Interrupt signal. There is a two-level hierarchy in generating this signal, as shown in Figure 5-1.
At the first level of the hierarchy, events are recorded as bits in the Attention Registers (e.g., No Space Attention Register). Each
Attention Register has a corresponding Notify Register (e.g., No Space Notify Register). When a bit in the Attention Register is
set to One and its corresponding bit in the Notify Register is also set to One, the corresponding bit in the Master Attention
Register will be set to one.
At the second level of the hierarchy, if a bit in the Master Attention Register is set to One and the corresponding bit in the Master
Notify Register is set to One, the Interrupt signal is asserted.
Bits in Conditional Write Registers (e.g., No Space Attention Register) are only written when the corresponding bits in the
Compare Register are equal to the bits to be overwritten.

TL/F/10791-11

FIGURE 5-1. Event Registers Hierarchy
Events are recorded in Attention Registers and contribute to
the Interrupt when the bit in the corresponding Notify Register is set (see Table 5-2).

• Service Notify Register (SNR) is used to enable attentions in the Service Attention Register.
• No Space Attention Register (NSAR) presents attentions generated when the lOUD, PSP, or CNF Queues
run out of space or valid entries.

The Event Registers include the following registers:
• Master Attention Register (MAR) collects enabled attentions from the State Attention Register, Service Attention Register, No Space Attention Register, Request Attention Register, and Indicate Attention Register.

• Request Attention Register (RAR) presents attentions
generated by both Request Channels.
• Request Notify Register (RNR) is used to enable attentions in the Request Attention Register.

• Master Notify Register (NMR) is used to selectively enable attention in the Master Attention Register.

• Indicate Attention Register (IAR) presents the attentions generated by the Indicate Channels.

• State Attention Register (STAR) presents attentions
for major states within the BSI device and various error
conditions.

• Indicate Notify Register (INR) is used to enable attentions in the Indicate Attention Register.

• State Notify Register (STNR) is used to enable attentions in the State Attention Register.

• Compare Register (CMP) is used for comparison with a
write access of a conditional write (Attention) register.

• Service Attention Register (SAR) presents attentions
for the PTOP and LMOP service functions.

2-282

5.0 Control Information

(Continued)

5.3 CONTROL AND EVENT REGISTER DESCRIPTIONS
Mode Register (MR)
The Mode Register (MR) is used to program the major operating parameters for the BSI device. This register should be
programmed only at power-on, or after a software Master Reset.
This register is cleared upon reset.
Access Rules
Address

I

Read

I

OOh

Write

I

Always

Always

I

Register Bits
D7

I

SMLB

D6

I

SMLQ

D5

I

VIRT

D4

I

BIGEND

D3

I

FLOW

Dl

D2

I

MRST

I

FABCLK

DO

I

TEST

I

Description .

Bit

Symbol

DO

TEST

Test Mode: Enables test logic, in which the transmitted frames counter will cause a
service loss after four frames, instead of 255 frames.

Dl

FABCLK

Fast ABus Clock: Determines the metastability delay period for synchronizing between
the ABus clock and the Ring clock (LBC). Upon reset this bit is cleared to Zero, which
selects one ABus clock period as the delay. When this bit is set to One, only % of an ABus
clock delay is used. When AB_CLK = LBC, (i.e., at 12.5 MHz and in phase), this bit
should be set. For any AB_CLK greater then LBC, this bit must be Zero.

D2

MRST

Master Reset: When this bit is set, the Indicate, Request, and Status/Space Macines are
placed in Stop Mode,and BSI device registers are initialized to the values shown in Table
5-5. This bit is cleared after the reset is complete.

D3

FLOW

Flow Parity: When this bit is set, parity flows between the ABus and the BMAC device,
that is, incoming data is not checked at the ABus interface, but is Checked (by the BMAC
device) as it is passed to the BMAC device. The parity check includes the frame's FC
through ED fields. When this bit is set, Control Bus parity is also checked, and errors are
reported in the CPE bit of the State Attention Register. When this bit is Zero, no parity is
checked on the Control Bus or ABus.

D4

BIGEND

Big Endlan Data Format: Selects between the Little Endian (BIG END = 0) or Big Endian
(BIGEND = 1) data format. See Figure 4-2.

D5

VIRT

Virtual Address Mode: Selects between virtual (VIRT = 1) or physical (VIRT = 0)
address mode on the ABus.

D6

SMLQ

Small Queue: Selects the size of all Descriptor queues and lists. When SMLQ = 0, the
size is 4k bytes; when SMLQ = I, the size is 1k bytes. Note that data pages are always
4k bytes.

D7

SMLB

Small Bursts: Selects size of bursts on ABus. When SMLB = 0, the BSI device uses 1-,
4-, and 8-word transfers. When SMLB = I, the BSI device uses 1- and 4-word transfers.

fII

2-283

5.0 Control Information (Continued)
Pointer RAM Control and Address Register (PCAR)
The Pointer RAM Control and Address Register (PCAR) is used to program the parameters for the PTOP (Pointer RAM
Operation) service function, in which data is written to or read from a Pointer RAM Register.
This register is not altered upon reset.
Access Rules

Address

Read

Write

02h

Always

Always

Register Bits
D7

I
Bit

BP1

D6

I

SPO

I

D5

04

D3

D2

01

DO

PTRW

A4

A3

A2

A1

AO

Description

Symbol

00-4

AO-4

Pointer RAM Address: These five bits contain the Pointer RAM Register address for a

05

PTRW

PTOP Read/Write: This bit determines whether a PTOP service function will be a read

subsequent PTOP service function.
from the Pointer RAM Register to the mailbox in memory (PTRW
Pointer RAM Register from the mailbox (PTRW = 0).
06-7

SPO-1

= 1), or a write to the

Byte Pointer: These two bits are used to program an internal byte pointer for accesses to
the 32-bit Mailbox Address Register. They are normally set to Zero to initialize the byte
painter for four successive writes (most-significant byte first) and are automatically
incremented after each write.

2-284

5.0 Control Information (Continued)
Mailbox Address Register (MBAR)
The Mailbox Address Register (MBAR) is used to program the word-aligned 28-bit memory address of the mailbox used in the
data transfer of the PTOP (Pointer RAM Operation) service function.
The address of this register is used as a window into four internal byte registers. The four byte registers are loaded by
successive writes to this address after first setting the SPR bits in the Pointer RAM Control and Address Register to Zero. The
bytes must be loaded most-significant byte first. The BSI device increments the byte pOinter internally after each write or read.
Mailbox Address bits 0 and 1 forced internally to Zero.
This register is initialized to a silicon Revision code upon reset. The Revision code remains until it Is overwritten by the host.
Access Rules
Address

Read

Write

03h

Always

Always

Register Bits

o

7
Mailbox Address [27:24]
Mailbox Address [23:16]
Mailbox Address [15:8]
Mailbox Address [7:0]

2-285

5.0 Control Information (Continued)
Master Attention Register (MAR)
The Master Attention Register (MAR) collects enabled attentions from the State Attention Register, Service Attention Register,
No Space Attention Register, Request Attention Register, and Indicate Attention Register. If the Notify bit in the Master Notify
Register and the corresponding bit in the MAR are set to One, the INT is forced to LOW and thus triggers an interrupt.
Writes to the Master Attention Register are permitted, but do not change the contents.
All bits in this register are set to Zero upon reset.
Access Rules
Address

I

Read

I

04h

Write

I

Always

Data Ignored

I

Register Bits
D7

I
Bit
DO-2

STA

D6

I

NSA

D5

I

SVA

D4

I

RQA

D2

D3

I

INA

Symbol

I

RES

D1

I

RES

DO

I

RES

I

Description

RES

Reserved

D3

INA

Indicate Attention Register: Is set if any bit in the Indicate Attention Register is set.

D4

RQA

Request Attention Register: Is set if any bit in the Request Attention Register is set.
Service Attention Register: Is set if any bit in the Service Attention Register is set.

D5

SVA

D6

NSA

No Space Attention Register: Is set if any bit in the No Space Attention Register is set.

D7

STA

State Attention Register: Is set if any bit in the State Attention Register is set.

2-286

C

"0

5.0 Control Information (Continued)

co
W

Master Notify Register (MNR)
The Master Notify Register (MNR) is used to enable attentions in the Master Attention Register (MAR). If a bit in Register MNR
and the corresponding bit in Register MAR are set to One, the INT signal is deasserted and causes an interrupt.

N

en

U1

All bits in this register are set to Zero upon reset.
Access Rules
Address

I

Read

I

05h

Write

Always

I

I

Always

Register Bits

07

I
Bit

STAN

06

I

NSAN

05

I

SVAN

04

I

ROAN

03

I

INAN

Symbol

01

02

I

RES

I

RES

DO

I

RES

I

Description

00-2

RES

Reserved

03

INAN

Indicate Attention Register Notify: This bit is used to enable the INA bit in Register MNR.

04

ROAN

Request Attention Register Notify: This bit is used to enable the ROA bit in Register MNR.

05

SVAN

Service Attention Register Notify: This bit is used to enable the SVA bit in Register MNR.

06

NSAN

No Space Attention Register Notify: This bit is used to enable the NSA bit in Register MNR.

07

STAN

State Attention Register Notify: This bit is used to enable the STA bit in Register MNR.

EI

2-287

5.0 Control Information (Continued)
State Attention Register (STAR)
The State'Attention Register (STAR) controls the state of the Indicate, Request, and Status/Space Machines. It also records
parity, internal logic, and ABus transaction errors. Each bit may be enabled by setting the corresponding bit in the State Notify
Register.
Access Rules
Address

I

Read

I

06h

Write

I

Always

Conditional

I

Register Bits
07

I

ERR

06

I

BPE

05

I

04

CPE

I

CWI

03

I

CMDE

02

I

01

SPSTOP

I

ROSTOP

DO

I

INSTOP

I

Bit

Symbol

Description

DO

INSTOP

Indicate Stop: This bit is set by the host to place the Indicate Machine in Stop Mode. This
bit is set ,by the BSI device when the Indicate state machine detects an internal error,
enters an invalid state, or when the host loads the Indicate Header Length Register with an
illegal value. This bit is set upon reset.

D1

ROSTOP

Request Stop: This bit is set by the host to place the Request Machine in Stop Mode. This
bit is set by the BSI device when the Request Machine detects an internal error or enters
an invalid state. It is also set when an ABus error occurs while storing a Confirmation
Status Message Descriptor (CNF). This bit is set upon reset.

D2

SPSTOP

Status/Space Stop: This bit is set by the host to place the Status/Space Machine in Stop
Mode. This bit is set by the BSI device when the Status/Space Machine has entered
STOP Mode because of an unrecoverable error. In STOP Mode, only PTOP or LMOP
service functions will be performed. This bit is set upon reset.

D3

CMDE

Command Error: Indicates that the host performed an invalid operation. This occurs when
an invalid value is loaded into the Indicate Header Length Register (which also sets the
INSTOP attention). This bit is cleared upon reset.

D4

CWI

Conditional Write Inhibit: Indicates that at least one bit of the previous conditional write
operation was not written. This bit is set unconditionally after each write to a conditional
write register. It is also set when the value of the Compare Register is not equal to the
value of the register that was accessed for a write before it was written. This may indicate
that the accessed register has changed since it was last read. This bit is cleared after a
successful conditional write. CWI bit does not contribute to setting the STA bit of the
Master Attention Register because its associated Notify bit is always O. This bit is cleared
upon reset.

D5

CPE

Control Bus Parity Error: Indicates a parity error detected on CBD? -0. If there is a
Control Bus parity error during a host write, the write is suppressed. Control Bus parity
errors are reported when flow-through parity is enabled (the FLOW bit of the Mode
Register is set). This bit is cleared upon reset.

D6

BPE

BMAC Device Parity Error: Indicates parity error detected on MID? -0. BMAC device
parity is always checked during a frame. This bit is cleared upon reset.

D?

ERR

Error: This bit is set by the BSI device when a non-recoverable error occurs. These
include an ABus transaction error while writing confirmation status, an internal logic error,
or when any state machine enters an invalid state. This bit is cleared upon reset.

2-288

5.0 Control Information (Continued)
State Notify Register (STNR)
The State Notify Register (STNR) is used to enable bits in the State Attention Register (STAR). If a bit in Register STNR is set to
One, the corresponding bit in Register STAR will be applied to the Master Attention Register, which can be used to generate an
interrupt to the host.
All bits in this register are cleared to Zero upon reset.
Access Rules
Address

I

Write

Read

I

07h

I

Always

I

Always

Register Bits
D7

I

ERRN

D6

I

BPEN

D5

I

CPEN

D4

I

CWIN.

D3

I

D2

CMDEN

I

SPSTOPN

DO

D1

I

RQSTOPN

I

INSTOPN

I

Bit

Symbol

DO

INSTOPN

Indicate Stop Notify: This bit is used to enable the INSTOP bit in Register STAR.

Description

D1

RQSTOPN

Request Stop Notify: This bit is used to enable the RQSTOP bit in Register STAR.

D2

SPSTOPN

Status/Space Stop Notify: This bit is used to enable the SPSTOP bit in Register STAR.

D3

CMDEN

Command Error Notify: This bit is used to enable the CMDE bit in Register STAR.

D4

CWIN

Conditional Write Inhibit Notify: This bit is used to enable the CWI bit in Register STAR.

D5

CPEN

Control Bus Parity Error Notify: This bit is used to enable the CPE bit in Register STAR.

D6

BPEN

BMAC Device Parity Error Notify: This bit is used to enable the BPE bit in Register STAR.

D7

ERRN

Error Notify: This bit is used to enable the ERR bit in Register STAR.

•
2·289

5.0 Control Information (Continued)
Service Attention Register (SAR)
The Service Attention Register (SAR) is used to present the attentions for the service functions. Each bit may be enabled by
setting the corresponding bit in the State Notify Register.
Access Rules
Read

Address

I

I

OSh

Write

Always

I

Conditional

I

RES

I

Register Bits
D7

I

RES

D6

I

RES

D5

I

RES

D3

D4

I

ABRO

D2

I

ABR1

DO

D1

I

LMOP

I

PTOP

I

Description

Bit

Symbol

DO

PTOP

Pointer RAM Operation: This bit is cleared by the host to cause the BSI device to transfer
data between a Pointer RAM Register and a mailbox location in memory. The Pointer RAM
Control and Address Register contains the Pointer RAM Register address and determines
the direction of the transfer (read or write). The memory address is in the Mailbox Address
Register. This bit is set by the BSI device after it performs the data transfer.
While PTOP = 0 , the host must not aiter the Pointer RAM Address and Control Register
or the Mailbox Address Register.

D1

LMOP

Limit RAM Operation: This bit is cleared by the host to cause the BSI device to transfer
data between a Limit RAM Register and the Limit Data and Limit Address Registers. The
Limit Address Register contains the Pointer RAM Register address and determines the
direction of the transfer (read and write). This bit is set by the BSI device after it data
performs the transfer.
While LMOP = 0, the host must not alter either the Limit Address or Limit Data Registers.

D2

ABR1

Abort Request RCHN1: This bit is cleared by the host to abort a Request on RCHN1. This
bit is set by the BSI device when RQABORT ends a request on RCHN1. The host may
write a 1 to this bit, which mayor may not prevent the request from being aborted. When
this bit is cleared by the host, the USR1 bit in the Request Attention Register is set and
further processing on RCHN1 is halted.

D3

ABRO

Abort Request RCHNO: This bit is cleared by the host to abort a Request on RCHNO. This
bit is set by the BSI device when RQABORT ends a request on RCHNO. The host may
write a 1 to this bit, which mayor may not prevent the request from being aborted. When
this bit is cleared by the host, the USRO bit in the Request Attention Register is set and
further processing on RCHNO is halted.

D4-7

RES

Reserved

2·290

5.0 Control Information (Continued)
Service Notify Register (SNR)
The Service Notify Register (SNR) is used to enable attentions in the Service Attention Register (SAR). If a bit in Register SNR is
set to One, the corresponding bit in Register SAR will be applied to the Master Attention Register, which can be used to
generate an interrupt to the host.
All bits in this register are set to Zero upon reset.
Access Rules
Address

I

Read

I

09h

Write

I

Always

I

Always

Register Bits
07

I

RES

06

I

RES

Bit

Symbol

00

PTOPN

05

I

04

RES

I

RES

03

I

02

ABRON

I

ABR1N

01

I

LMOPN

DO

I

PTOPN

I

Description
Pointer RAM Operation Notify: This bit is used to enable the PTOP bit in Register SAR.

01

LMOPN

Limit RAM Operation Notify: This bit is used to enable the LMOP bit in Register SAR.

02

ABR1N

Abort Request RCHN1 Notify: This bit is used to enable the ABR1 bit in Register SAR.

03

ABRON

Abort Request RCHNO Notify: This bit is used to enable the ABRO bit in Register SAR.

RES

Reserved

04-7

2-291

5.0 Control Information (Continued)
No Space Attention Register (NSAR)
The No Space Attention Register (NSAR) presents the attentions generated when the CNF, PSP, or lOUD Queues run out of
space. The host may set any attention bit to cause an attention for test pUrposes only, though this should not be done during
normal operation.
The No Data Space attentions are set and cleared by the BSI device automatically. The No Status Space attentions are set by
the BSI device, and must be cleared by the host.
Upon reset this register is set to Oxffh.
Access Rules
Address

I

Read

I

OAh

Write

I

Always

I

Conditional

Register Bits
D7

I

NSRO

D6

I

NSR1

D5

I

LDIO

D4

I

NSIO

D3

I

LDI1

D1

D2

I

NSll

I

LDI2

DO

I

NSI2

I

Bit

Symbol

DO

NSI2

No Status Space on ICHN2: This bit is set by the BSI device upon a Reset, or when an IDUD has been written to
the next-to-Iast available entry in the Indicate Channel's IDUD Status Queue. When this occurs, the BSI device
stops copying on ICHN2 and the last lOUD is written with special status. This bit (as well as the USR Attention bit)
must be cleared by the host before the BSI device will resume copying on this Channel.

Description

01

LDI2

Low Data Space on ICHN2: This bit is set by the BSI device upon a Reset, or when a PSP is prefetched from
ICHN2's last PSP Queue location (as defined by the PSP Queue Limit Register). Note that the amount of warning
is dependent on the length of the frame. There will always be one more page (4k bytes) available for the BSI
device when this attention is generated. Another FDDI maximum-length frame (after the current one) will not fit in
this space. If SPS fetching was stopped because there were no more PSP entries, fetching will resume
automatically when the PSP Queue Limit Register is updated.

D2

NSll

No Status Space on ICHN1: This bit is set by the BSI device upon a Reset, or when an lOUD has been written to
the next-to-Iast available entry in the Indicate Channel's lOUD Status Queue. When this occurs, the BSI device
stops copying on ICHNl and the last lOUD is written with special status. This bit (as well as the USR Attention bit)
must be cleared by the host before the BSI device will resume copying on this Channel.

D3

LOll

Low Data Space on ICHN1: This bit is set by the BSI device upon a Reset, or when a PSP is prefetched from
ICHNl 's last PSP Queue location (as defined by the PSP Queue Limit Register). Note that the amount of warning
is dependent on the length of the frame. There will always be one more page (4k bytes) available for the BSI
device when this attention is generated. Another FOOl maximum-length frame (after the current one) will not fit in
this space. If PSP fetching was stopped because there were no more PSP entries, fetching will resume
automatically when the PSP Queue Limit Register is updated.

D4

NSIO

No Status Space on ICHNO: This bit is set by the BSI device upon a Reset, or when an lOUD has been written to
the next-to-Iast available entry in the Indicate Channel's IDUD Status Queue. When this occurs, the BSI device
stops copying on ICHNO and the last IDUD is written with special status. This bit (as well as the USR Attention bit)
must be cleared by the host before the BSI device will resume copying on this Channel.

D5

LDIO

Low Data Space on ICHNO: This bit is set by the BSI device upon a Reset, or when a PSP is prefetched from
ICHNO's last PSP Queue location (as defined by the PSP Queue Limit Register). Note that the amount of warning
is dependent on the length of the frame. There will always be one more page (4k bytes) available for the BSI
device when this attention is generated. Another FDDI maximum-length frame (after the current one) will not fit in
this space. If PSP fetching was stopped because there were no more PSP entries, fetching will resume
automatically when the PSP Queue Limit Register is updated.

D6

NSRl

No Status Space on RCHN1: This bit is set by the BSI device upon a Reset, or when it has written a CNF
Descriptor to the next-to-Iast Queue location. Due to internal pipelining, the BSI device may write up to two more
CNFs to the Queue after this attention is generated. Thus the Host must set the CNF Queue Limit Register to be
one less than the available space in the Queue. This bit (as well as the USR attention bit) must be cleared by the
Host before the BSI device will continue to process requests on RCHN1.

D7

NSRO

No Status Space on RCHNO: This bit is set by the BSI device upon a Reset, or when it has written a CNF
Descriptor to the next-Io-Iast Queue location. Due to internal pipelining, the BSI device may write up to two more
CNFs to the Queue after this attention is generated. Thus the Host must set the CNF Queue Limit Register to be
one less than the available space in the Queue. This bit (as well as the USR attention bit) must be cleared by the
Host before the BSI device will continue to process requests on RCHNO.

2-292

5.0 Control Information (Continued)
No Space Notify Register (NSNR)
The No Space Notify Register (NSNR) is used to enable attentions in the No Space Attention Register (NSAR). If a bit in
Register NSNR is set to One, the corresponding bit in Register NSAR will be applied to the Master Attention Register, which can
be used to generate an interrupt to the host.
All bits in this register are set to Zero upon reset.
Access Rules
Address

I

Read

I

OSh

Write

Always

I

I

Always

Register Bits
D7

I

D6

NSRON

I

NSR1N

D5

I

LDION

D4

I

NSION

D3

I

LDl1N

D2

I

NSI1N

D1

I

LDI2N

DO

I

NSI2N

I

Bit

Symbol

DO

NSI2N

No Status Space on ICHN2 Notify: This bit is used to enable the NSI2 in Register NSAR.

Description

D1

LDI2N

Low Data Space on ICHN2 Notify: This bit is used to enable the LDI2 in Register NSAR.

D2

NSI1N

No Status Space on ICHN1 Notify: This bit is used to enable the NSI1 in Register NSAR.

D3

LDI1N

Low Data Space on ICHN1 Notify: This bit is used to enable the LDI1 in Register NSAR.

D4

NSION

No Status Space on ICHNO Notify: This bit is used to enable the NSIO in Register NSAR.

D5

LDION

Low Data Space on ICHNO Notify: This bit is used to enable the LDIO in Register NSAR.

D6

NSR1N

No Status Space on RCHN1 Notify: This bit is used to enable the NSR1 in Register NSAR.

07

NSRON

No Status Space on RCHNO Notify: This bit is used to enable the NSRO in Register NSAR.

PI

2-293

5.0 Control Information (Continued)
Limit Address Register (LAR)
The Limit Address Register (LAR) is used to program the parameters for a LMOP (Limit RAM Operation) service function.
This register is not altered upon reset.
Access Rules
Address

I

Read

I

OCh

Always

Write

I

I

Always

Register Bits

07

I

LRA3

06

I

LRA2

05

I

LRA1

04

I

LRAO

03

I

LMRW

02

I

RES

01

I

RES

DO

I

LROS

I

Bit

Symbol

DO

LROS

Limit RAM Data Bit 8: This bit contains the most-significant data bit read or written from
the addressed Limit RAM Register.

RES

Reserved

LMRW

LMOP Read/Write: This bit determines whether a LMOP service function will be a read
(LMRW = 1) or write (LMRW = 0).

LRAO-3

Limit RAM Register Address: Used to program the Limit RAM Register address for a
subsequent LMOP service function.

D1-2
03
04-7

Description

2-294

5.0 Control Information (Continued)
Limit Data Register (LDR)
The Limit Data Register (LOR) is used to contain the B least-significant Limit RAM data bits transferred in a LMOP service
function. (The most-significant data bit is in the Limit Address register.)
This register is not altered upon reset.
Access Rules
Read

Address

I

I

ODh

Always

Write

I

Always

I

Register Bits
D7

I

LRD7

D6

I

LRD6

Bit

Symbol

00-7

LRDO-7

D5

I

LRD5

D4

I

LRD4

D2

D3

I

LRD3

I

LRD2

D1

I

LRDl

DO

I

LRDO

I

Description
Limit RAM Data Bits 0-7: These bits contain the least-significant data bits read from or
written to a Limit RAM Register in a LMOP service function.

2-295

I
Q

5.0 Control Information (Continued)
Request Attention Register (RAR)
The Request Attention Register (RAR) Is used to present exception, breakpoint, request complete, and unserviceable request
attentions generated by each Request Channel. Each bit may be enabled by setting the corresponding bit in the Request Notify
Register.
All bits in this register are set to Zero upon reset.
Access Rules
Address

I

Read

I

OEh

Register Bits
D7

D6

Write

I

Always

D5

Conditional

D4

I
D3

02

01

00

I USRRO I RCMRO I EXCRO I SRKRO I USRR1 I RCMR1 I EXCR1 I SRKR1 I
Bit

Symbol

DO

SRKR1

Breakpoint on RCHN1: Is set by the SSI device when a CNF DeSCriptor Is written on
RCHN1. No action Is taken by the SSI device if the host sets this bit.

Description

D1

EXCR1

Exception on RCHN1: Is set by the SSI device when an exception occurs on RCHN1. No
action Is taken by the SSI device if the host sets this bit.

D2

RCMR1

Reque.t Complete on RCHN1: Is set by the SSI device when it has completed
processing a Request object on RCHN1, an error occurs. or a completion exception
occurs. No action is taken if the Host sets this bit.

D3

USRR1

Un.ervlceable Reque.t on RCHN1: Is set by the SSI device when a Request cannot be
processed on RCHN1. This occurs when the Request Class is inappropriate for the current
ring state, or when there Is no CNF status space, or when the host aborts a request by
clearing the ASR bit in the Service Attention Register. While this bit is set, no requests will
be processed on RCHN1. The host must clear this bit to resume request processing.

D4

SRKRO

Breakpoint on RCHNO: Is set by the SSI device when a CNF Descriptor Is written on
RCHNO. No action Is taken by the SSI device if the host sets this bit.

D5

EXCRO

Exception on RCHNO: Is set by the SSI device when an exception occurs on RCHNO. No
action Is taken by the SSI device If the host sets this bit.

D6

RCMRO

Request Complete on RCHNO: Is set by the SSI device when it has completed
processing a Request object on RCHNO, an error occurs, or a completion exception
occurs. No action is taken if the Host sets this bit.

D7

USRRO

Unserviceable Request on RCHNO: Is set by the SSI device when a Request cannot be
processed on RCHNO. This occurs when the Request Class is inappropriate for the current
ring state, or when there Is no CNF status space, or when the host aborts a request by
clearing the ASR bit in the Service Attention Register. While this bit is set, no requests will
be processed on RCHNO. The host must clear this bit to resume request processing.

2-296

5.0 Control Information (Continued)
Request Notify Register (RNR)
The Request Notify Register (RNR) Is used to enable attentions in the Request Attention Register (RAR). If a bit in Register
RNR is set to One, the corresponding bit in Register RAR will be applied to the Master Attention Register, which can be used to
generate an interrupt to the host.
All bits in this register are set to Zero upon reset.
Access Rules
Read

Address

I

I

OFh

Register Bits
D7

I

USRRON

Always

D6

I

RCMRON

Bit

Symbol

00

BRKR1N

Write

I

D5

I

EXCRON

Always

D4

I

BRKRON

I
D3

I

USRR1N

D1

D2

I

RCMR1N

I

EXCR1N

DO

I

BRKR1N

I

Description
Breakpoint on RCHN1 Notify: This bit is used to enable the BRKR1 bit in Register RAR.

01

EXCR1N

Exception on RCHN1 Notify: This bit is used to enable the EXCR1 bit in Register RAR.

02

RCMR1N

Request Complete on RCHN1 Notify: This bit is used to enable the RCMR1 bit in
Register RAR.

03

USRR1N

Unserviceable Request on RCHN1 Notify: This bit is used to enable the USRR1 bit in
Register RAR.

04

BRKRON

Breakpoint on RCHNO Notify: This bit is used to enable the BRKRO bit in Register RAR.

05

EXCRON

Exception on RCHNO Notify: This bit is used to enable the EXCRO bit in Register RAR.

06

RCMRON

Request Complete on RCHNO Notify: This bit is used to enable the RCMRO bit in
Register RAR.

07

USRRON

Unserviceable Request on RCHNO Notify: This bit is used to enable the USRRO bit in
Register RAR.

!II

2·297

5.0 Control Information (Continued)
Request Channel 0 and 1 Configuration Registers (ROCR and R1CR)
The two Request Configuration Registers (ROCR and R1CR) are programmed with the operational parameters for each of the
Request Channels. These registers may only be altered between Requests, i.e., while the particular Request Channel does not
have a Request loaded.
These registers are not altered upon reset.
Access Rules
Address

I

Write

Read

I

10-11h

Always

I

Always

I

Register Bits
D7

I

TI1

D6

I

TIO

D5

I

PRE

D4

I

HLD

D3

I

FCT

D1

D2

I

SAT

I

VST

.DO

I

FCS

I

Bit

Symbol

DO

FCS

Frame Check Sequence Disable: When this bit is set, the BSI device asserts the FCST
signal throughout the request. This may drive the BMAC device FCST pin, or also the SAT
or SAIGT pins, depending on the application. This bit is normally used to program the
BMAC device not to concatenate its generated FCS to the transmitted frame. The Valid
FCS bit in the Expected Frame Status Register independently determines whether a frame
needs a valid FCS to meet the matching frame criteria.

Description

D1

VST

Void Stripping: When this bit is set, the BSI device asserts the STRIP output signal out
throughout the request. This may drive the BMAC device STRIP (Void Strip) pin, or also
the SAT pin, depending on the application.

D2

SAT

Source Address Transparency: When this bit is set, the BSI device asserts the SAT
output signal throughout the request. This may drive the BMAC device's SAT and/or
SAIGT pins, depending on the application. When SAT is set, Full Confirmation requires the
use of the EM (External SA Match) signal.

D3

FCT

Frame Control Transparency: When this bit is set, the FC will be sourced from the ODU
(not the REO. First Descriptor). When Full Confirmation is enabled and FCT = 0, all bits of
the FC in returning frames must match the FC field in the REO Descriptor; if FCT = 1, only
the C, Land r bits must match.
Note that since the BSI device decodes the REO.F Descriptor FC field to determine
whether to assert ROCLM/ROBCN, FC transparency may be used to send Beacons or
Claims in any ring non-operational state, as long as the FC in the REO Descriptor is not set
to Beacon or Claim. By programming a Beacon or Claim FC in the REO Descriptor, then
using FC transparency, any type of frame may be transmitted in the Beacon or Claim state.

D4

HLD

Hold: When this bit is set, the BSI device will not end a service opportunity until the
Request is complete. When this bit is Zero, the BSI device ends the service opportunity on
the Request Channel when all of the following conditions are met:
1. There is no valid request active on the Request Channel.
2. The service class is non-immediate.
3. There is no data in the FIFO.
4. There is no valid REO fetched by the BSI device.
This bit also affects Prestaging on RCHN1 (Request Channel 1). When HLD = 0,
prestaging is enabled on RCHN1, regardless of the state of the PRE bit (except for
Immediate service classes). When HLD = 1, prestaging is determined by the PRE bit. This
option can potentially waste ring bandwidth, but may be required (particularly on RCHNO,
Request Channel 0) if a small guaranteed service time is required.
When using the Repeat option, HLD is required for small frames. If HLD is not used, the
other Request Channel will be checked for service before releasing the token between
frames. This may not be the desired action, particularly if there is a request on RCHN1 that
needs servicing after the completion of RCHNO's Repeated Request.

2-298

C

."

5.0 Control Information (Continued)

CD
Co)

Request Channel 0 and 1 Configuration Registers (ROCR and R1CR) (Continued)
Symbol

Bit

Description

D5

PRE

Preempt/Prestage: When this bit is set, preemption is enabled for RCHNO, and prestaging is enabled for
RCHN1 (prestaging is always enabled for RCHNO). When this bit Zero, preemption is disabled and prestaging is
enabled only on RCHNO.
When preemption is enabled, RCHNO preempts a (non-committed) frame of RCHN1 already in the FIFO,
causing it to be purged and refetched after RCHNO's request has been serviced. When the Request Machine is
servicing a request on RCHN1 and a request on RCHNO becomes active, if preemption is enabled on RCHNO,
the Request Machine will finish transmitting the current frame on RCHN1, then release the token and move
back to the start state. This has the effect of reprioritizing the Request Channels, thus ensuring that frames on
RCHNO are transmitted at the next service opportunity. When RCHNO has been serviced, transmission will
continue on RCHN1 with no loss of data.
When prestaging is enabled, the next frame for RCHN1 is staged (ODUs are loaded into the FIFO before the
token arrives). If prestaging is not enabled, the Request Machine waits until the token is captured before
staging the first frame. Once the token is captured, the Request Machine begins fetching data, and when the
FIFO threshold has been reached, transmits the data on that Request Channel. For requests with an Immediate
service class, prestaging is not applicable.
When this bit is Zero, preemption is disabled for RCHNO, and requests on RCHN1 will not be prestaged unless
the HLD bit is Zero, in which case RCHN1 will prestage data regardless of the setting of the PRE bit.
Note that when prestaging is not enabled on RCHN1, data is not staged until the token is captured. Since there
is no data in the FIFO (if there is no active request on RCHNO), the BSI device will immediately release the
token if the HLD option is not set.

D6-7

TTO-1

N
CD

en

Transmit Threshold: Determines the threshold on the output data FIFO before the BSI device requests
transmission.
TT1
TTO
Threshold Value
o
0
a Words
o
1
16 Words
1
o
Reserved
1
1
Reserved

•
2-299

5.0 Control Information (Continued)
Request Channel 0 and 1 Expected Frame Status Registers (ROEFSR and R1EFSR)
The Expected Frame Status Registers (ROEFSR and R1EFSR) define the matching criteria used for Full Confirmation of
. returning frames on each Request Channel. A returning frame must meet the programmed criteria to be counted as a matching
frame.
These registers are not altered upon reset.
Access Rules
Address

I

12-13h

Read

I

Always

Write

I

I

Always

Register Bits
D7

I

VOL

Bit

Symbol

00-1

ECO-1

02-3

04-5

EAO-1

EEO-1

D6

I

VFCS

D5

I

EE1

D4

I

EEO

D3

I

EA1

D2

I

EAO

DO

D1

I

EC1

I

ECO

I

Description
Expected C Indicator:
EC1
ECO
0
0
0
1
0
1
1
1

Value
Any
R
S
RorS

Expected AIndicator:
EA1
EAO
0
0
0
1
0
1
1
1

Value
Any
R
S
RorS

Expected E Indicator:
EE1
EEO
0
0
0
1
0
1
1
1

Value
Any
R
S
RorS

06

VFCS

Valid FCS: When this bit is set, returning frames must have a valid FCS field to meet the confirmation criteria.

07

VOL

Valid Data Length: When this bit is set, returning frames must have a valid VOL field to meet the confirmation
criteria.

2-300

5.0 Control Information

(Continued)

Indicate Attention Register (lAR)
The Indicate Attention Register (IAR) is used to present exception and breakpoint attentions generated by each Indicate
Channel. An Attention bit is set by hardware when an exception or breakpoint occurs on the corresponding Indicate Channel.
Each bit may be enabled by setting the corresponding bit in the Indicate Notify Register.
Access Rules
Address

I

Write

Read

I

14h

Always

I

Conditional

I

Register Bits
D7

I

RES

D6

I

RES

D5

I

EXCIO

D4

I

BRKIO

D3

I

EXCI1

D2

I

BRKI1

D1

I

EXCI2

DO

I

BRKI2

I

Bit

Symbol

00

BRKI2

Breakpoint on ICHN2: Is set when a breakpoint is detected on Indicate Channel 2. No
action is taken if the host sets this bit.

01

EXCI2

Exception on ICHN2: Is set by the BSI device when an exception occurs on Indicate
Channel 2. May be set by the host to disable copying on ICHN2, which is convenient when
updating the Indicate Header Length and Indicate Threshold registers. While this bit is set,
copying is disabled on ICHN2.

02

BRKI1

Breakpoint on ICHN1: Is set when a breakpoint is detected on Indicate Channel 1. No
action is taken if the host sets this bit.

03

EXCI1

Exception on ICHN1: Is set by the BSI device when an exception occurs on Indicate
Channel 1. May be set by the host to disable copying on ICHN1, which is convenient when
updating the Indicate Header Length and Indicate Threshold registers. While this bit is set,
copying is disabled on ICHN1.

04

BRKIO

Breakpoint on ICHNO: Is set when a breakpoint is detected on ICHNO. No action is taken
if the host sets this bit.

05

EXCIO

Exception on ICHNO: Is set by the BSI device when an exception occurs on Indicate
Channel O. May be set by the host to disable copying on ICHNO, which is convenient when
updating the Indicate Header Length and Indicate Threshold registers. While this bit is set,
copying is disabled on ICHNO.

RES

Reserved

06-7

Description

- ---

_. - --

•
2·301

5.0 Control Information (Continued)
Indicate Notify Register (INR)
The Indicate Notify Register (lNR) is used to enable attentions in the Indicate Attention Register (lAR). If a bit in Register INR is
set to One, the corresponding bit in Register IAR will be applied to the Master Attention Register, which can be used to generate
an interrupt to the host.
All bits in this register are set to Zero upon reset.
Access Rules
Address

I

Read

I

15h

Write

I

Always

Always

I

Register Bits
D7

I

RES

Bit
DO

D6

I

RES

D5

I

D4

EXCON

I

BRKON

D3

I

EXC1N

Symbol

D2

I

BRK1N

01

I

EXC2N

DO

I

BRK2N

I

Description

BRK2N

Breakpoint on ICHN2 Notify: This bit is used to enable the BRK2 bit in Register IAR.

D1

EXC2N

Exception on ICHN2 Notify: This bit is used to enable the EXC2 bit in Register IAR.

D2

BRK1N

Breakpoint on ICHN1 Notify: This bit is used to enable the BRK1 bit in Register IAR.
Exception on ICHN1 Notify: This bit is used to enable the EXC1 bit in Register IAR.

D3

EXC1N

D4

BRKON

Breakpoint on ICHNO Notify: This bit is used to enable the BRKO bit in Register IAR.

D5

EXCON

Exception on ICHNO Notify: This bit is used to enable the EXCO bit in Register IAR.

D6-7

RES

Reserved

2-302

.----------------------------------------------------------------------.0
"'CI
CCI
5.0 Control Information (Continued)
Co)

N

Indicate Threshold Register (ITR)

Q)

The Indicate Threshold Register (lTR) specifies the maximum number of frames that can be received on Indicate Channel 1 or
Indicate Channel 2 before an attention will be generated. This register may be written only when the INSTOP bit in the State
Attention Register is set, or when the Indicate Channel's corresponding EXC bit in the Indicate Attention Register is set.

U1

This register is not altered upon reset.
Access Rules
Address
16h

Read
Always

I

Write
I

INSTOP Mode or EXC = 1 Only

I

Register Bits
07
I

THR7

06
I

THR6

05
I

THR5

04
I

THR4

03
I

THR3

01

02
I

THR2

I

THR1

DO
I

THRO

I

Bit

Symbol

Description

DO-7

THRO-7

Threshold Data Bits 0-7: The value programmed in this register is loaded into an internal
counter every time the Indicate Channel changes. Each valid frame copied on the current
Channel decrements the counter. When the counter reaches Zero, a status breakpoint
attention is generated (i.e., the Channel's BRK bit in the Indicate Attention Register is set)
if the Channel's Breakpoint on Threshold (BOn bit in the Indicate Mode Register is set.
Loading the Indicate Threshold Register with Zero generates a breakpoint after 256
consecutive frames are received on anyone Indicate Channel.

FII

2-303

5.0 Control Information (Continued)
Indicate Mode Register (IMR)
The Indicate Mode Register (lMR) defines configuration options for all three Indicata Channels, including the sort mode, frame
filtering, and status breakpoints.
This register may be written only when the INSTOP bit in the State Attention Register is set. It may be written with Its current
value any time, which is useful for one-shot sampling.
This register is not altered upon reset.
Access Rules
Address

I

Read

I

17h

Always

Write

I

INSTOP Mode Only

I

Register Bits
D7

I

SMl

D6

I

SMO

D5

I

SKIP

D4

I

RES

D3

I

BOTl

D1

D2

I

BOT2

I

BOB

DO

I

BOS

I

Bit

Symbol

00

BOS

Breakpoint on Service Opportunity: Enables the end of a service opportunity to
generate an Indicate breakpoint attention (i.e., set the Channel's BRK bit in the Indicate
Attention Register). Service opportunities include receipt of a Token, a MAC Frame, or a
ring operational change following some copied frames.

Description

01

BOB

Breakpoint on Burst: Enables the end of a burst to generate an Indicate breakpoint
attention (i.e., set the Channel's BRK bit in the Indicate Attention Register). End of burst
includes Channel change, OA change, SA change, or MAC INFO change. A Channel
change is detected from the FC field of valid, copied frames. A OA change is detected
when a frame's OA field changes from our address to any other. A SA change is detected
when a frame's SA field is not the same as the previous one. A MAC INFO breakpoint
occurs when a MAC frame does not have the identical first four bytes of INFO as the
previous frame. This breakpoint always sets the BRK bit (I.e., this breakpoint is always
enabled).

02

BOT2

Breakpoint on Threshold for ICHN2: Enables the value in the Indicate Threshold
Register to be used to generate an Indicate breakpoint attention on Indicate Channel 2,
(i.e., set the BRK2 bit in the Indicate Attention Register).

03

BOTl

Breakpoint on Threshold for ICHN1: Enables the value in the Indicate Threshold
Register to be used to generate an Indicate breakpoint attention on ICHN1, (i.e., set the
BRKl bit in. the Indicate Attention Register.

04

RES

Reserved

05

SKIP

Skip Enable: Enables filtering on Indicate Channel 0 when the Copy Control field for
ICHNO in the Indicate Configuration Register is set to 01 or 10. When this bit is set, only
the unique MAC and SMT frames received on Indicate Channel 0 will be copied to
memory, i.e., those having an FC field or first four bytes of the Information field that differs
from the previous frame.
A write to the Indicate Mode Register disables filtering.

2-304

.----------------------------------------------------------------------,0
;g

5.0 Control Information (Continued)

~

m

Indicate Mode Register (lMR) (Continued)

UI

Bit

Symbol

Description

SMO-1

06-7

Sort Mode: These bits determine how the BSI device sorts Indicate data onto Indicate Channels 1 and 2.
(Indicate Channel 0 always receives SMT and MAC frames.)
SM1
SMO
ICHN2
ICHN1
o
0
Asynchronous
Synchronous
o
1
External
Internal
1
0
Info
Header
1
1
Low Priority
High Priority
The Synchronous/Asynchronous Sort Mode is intended for use in end-stations or applications using
synchronous transmission.
The Internal/External Sorting Mode is intended for bridging or monitoring applications. MAC/SMT frames
matching the internal (BMAC device) address are sorted onto ICHNO, and all other frames matching the
BMAC device's internal address (short or long) are sorted onto ICHN1. All frames matching the external
address (frames requiring bridging) are sorted onto ICHN2 (including MAC/SMT). This sorting mode
utilizes the EM, EA, and ECIP input signals with external address matching circuitry. External address
circuitry must assert ECIP sometime from the assertion of FCRCVD up to the clock before the assertion of
INFORCVD. Otherwise, the BSI device assumes no external address comparison is taking place. ECIP
must be negated before EDRCVD; if not, the frame is not copied. EA and EM are sampled on the clock
after ECIP is negated. ECIP is ignored after it is negated, until FCRCVD is asserted again. To confirm
transmitted frames in this mode (typically using SAT), EM must be asserted within the same time frame as
EA. Note that internal matches have precedence over external matches.
The Header/Info Sort Mode is intended for high performance protocol processing. MAC/SMT frames are
sorted onto ICHNO, while all other frames are sorted onto ICHN1 and ICHN2. Frame bytes from the FC up
to the programmed header length are copied onto ICHN 1. The remaining bytes (info) are copied onto
ICHN2. Only one stream of IDUDs is produced (on ICHN1), but both Indicate Channel's PSP queues are
used for space (i.e., PSPs from ICHN1 for header space, and PSPs from ICHN2 for info space). Frames
may comprise a header only, or a header+ info. For frames with info, multi-part lOUD objects are
produced. For mUlti-part IDUDs, the Indicate Status field in the lOUD is used to determine which part of
the lOUD object pOints to the end of the header. The remainder of the lOUD object points to the Info.
For example, if page crosses occur while writing the header and while writing out the Info, the BSI Device
will generate a four part lOUD object (lDUD.First, IDUD.Middle, lOUD. Middle, lOUD. Last). The lOUD. First
will have a status of "page cross". The first IDUD.Middle will have a status of "end of header". The next
IDUD.Middle will have a status of "page boundary crossed". The IDUD.Last will have an "end of frame"
status.
The High Priority/Low Priority Sort Mode is intended for end stations using two priority levels of
asynchronous transmission. The priority is determined by the most-significant z-bit of the FC
(zzz = Oxx = low-priority; zzz = 1xx = high-priority).

fJI

2-305

5.0 Control Information (Continued)
Indicate Configuration Register (lCR)
The Indicate Configuration Register (ICR) is used to program the copy criteria for each of the Indicate Channels.
This register is not altered upon reset.
Access Rules
Address

I

18h

Read

I

Always

Write

I

Always

I

D4

D3

Register Bits
D7

I

D6

Bit
00-1

D5

I

CCO

RES

I

D1

D2

I

CC1

RES

I

DO
CC2

I

Description

Symbol
CC2

Copy ControllCHN2:
CC1
CCO
0
0
1
0
1
0
1
1

02

RES

Reserved

03-4

CC1

Copy ControllCHN1:
CC4
CC3
0
0
1
0
0
1
1
1

05

RES

Reserved

06-7

cco

Copy ControiICHNO:
CC7
CC6
0
0
0
1
0
1
1
1

Copy Mode
00 Not Copy
Copy if (AFLAG
ECIP & EA)) & - MFLAG
ECIP & EA)) MFLAG
Copy if (AFLAG
Copy Promiscously.

I(I (-

I

Copy Mode
00 Not Copy
Copy if (AFLAG
ECIP & EA)) & - MFLAG
Copy if (AFLAG
ECIP & EA)) MFLAG
Copy Promiscuously.

I (I (-

I

Copy Mode
00 Not Copy
Copy if (AFLAG
ECIP & EA)) & - MFLAG
ECIP & EA)) MFLAG
Copy if (AFLAG
Copy Promiscuously.

I (I (-

I

~

.-

2-306

r----------------------------------------------------------------------.c
;;g
5.0 Control Information (Continued)

Co)
I\)

en

Indicate Header Length Register (IHLR)
The Indicate Header Length Register (IHLR) defines the length (in words) of the frame header, for use with the Header/Info Sort
Mode.
The Indicate Header Length Register must be initialized before setting the Sort Mode to Headerllnfo. This register may be
changed while the INSTOP bit in the State Attention Register or the EXC bit in the Indicate Attention Register is set.
This register is not altered upon reset.
Access Rules

I

Address
19h

Read

I

Always

I

HL6

I

Write
INSTOP Mode or EXC = 1 Only

I

Register Bits
D7

I

HL7

D6

Bit

Symbol

DO-7

HLO-7

D5

I

HL5

I

D4
HL4

I

D2

D3
HL3

I

HL2

I

D1

DO

HL1

HLO

I

Description
Header Length: Specifies the length (in words) of the frame header, for use with the
Headerllnfo Sort Mode. The frame FC is written as a separate word, and thus counts as
one word. For example, to split after four bytes of header data in a frame with long
addresses, this register is programmed with the value 05 (1 word FC, 1.5 DA, 1.5 SA,
1 HDR_DATA).IHLR must not be loaded with a value less than 4. If it is, the SSI device
sets the Command Error (CMDE) and Indicate Stop (INSTOP) attentions.

2-307

UI

U)

CD
N

('I)

CO

D-

C

r---------------------------------------------------------------------------------,
5.0 Control Information (Continued)
Compare Register (CMP)
The Compare Register (CMP) is used in comparison with a write access of a conditional write register. The Compare Register is
loaded on a read of any of the conditional event Attention Registers or by directly writing to it.
All bits in this register are set to Zero upon reset.
Access Rules
Address

Read

Write

1Fh

Always

Always

Register Bits

I

D7
CMP7

I

D6
CMP6

Bit

Symbol

DO-7

CMPO-7

I

D5
CMP5

I

D4
CMP4

I

D3
CMP3

I

D2
CMP2

I

D1
CMP1

I

DO
CMPO

I

Description
Compare: These bits are compared to bits DO-7 of the accessed register, and only the
bits in the Attention Register that have the same current value as the corresponding bit in
the Compare register will be updated with the new value.

2·308

5.0 Control Information (Continued)
5.4 POINTER RAM REGISTERS
Pointer RAM Registers contain pointers to all data and DesCriptors manipulated by the SSI device, namely, Input and
Output Data Units, Input and Output Data Unit Descriptors,
Request Descriptors, Confirmation Messages, and Pool
Space Descriptors. Pointer RAM Registers are shown in Table 5-4.

Descriptors include the following:
• Input Data Unit Descriptors (IDUDs) specify the location, size, part, and status information for Input Data
Units.
• Output Data Unit DescrIptors (ODUDs) specify the location and size of Output Data Units. For multi-ODUD
frames, they also specify which part of the frame is pOinted to by the ODUD.

5.5 LIMIT RAM REGISTERS

• Pool Space DescrIptors (PSPs) describe the location
and size of a region of memory space available for writing Indicate data.

The Limit RAM Registers are used by both the Indicate and
Request machines. Limit RAM Registers contain data values that define the limits of the ten queues maintained by
the SSI device. Limit RAM Registers are shown in Table
5-5.

• Request Descriptors (REQs) describe the location of a
stream of Output Data Unit Descriptors and contain operational parameters

5.6 DESCRIPTORS
Descriptors are used to observe and control the operation
of the SSI device. They contain address, status, and control
information about Indicate and Request operations. Descriptors are stored in lists and wrap-around queues in
memory external to the SSI device and accessed via the
ASus.

• ConfirmatIon Status Messages (CNFs) describe the result of a Request operation.
5.7 OPERATING RULES
Multi-Byte Register Ordering
When referring to multi-byte fields, byte 0 is always the most
significant byte. When referring to bits within a byte, bit 7 is
the most significant bit and bit 0 is the least significant bit.
When referring to the contents of a byte, the most significant bit is always referred to first.

2-309

U) . - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

CD
C\I

C')

~

5.0 Control Information (Continued)

c

TABLE 5-4. Pointer RAM Registers
Group

P

0
N

T
E
R
R
A
M

Address

Register Name

Access Rules
Read
Write

00

ODU Pointer RCHN1 (OPR1)

Always

Always

01

ODUD List Pointer RCHN1 (OLPR1)

Always

Always

02

CNF Queue Pointer RCHN1 (CQPR1)

Always

Always

03

REQ Queue Pointer RCHN1 (RQPR1)

Always

Always

04

ODU Pointer RCHNO (OPRO)

Always

Always

05

ODUD List Pointer RCHNO (OLPRO)

Always

Always

06

CNF Queue Pointer RCHNO (CQPRO)

Always

Always

07

REQ Queue Pointer RCHNO (RQPRO)

Always

Always

08

IOU Pointer ICHN2 (lPI2)

Always

Always

09

lOUD Queue Pointer ICHN2 (IQPI2)

Always

Always

OA

PSP Queue Pointer ICHN2 (PQPI2)

Always

Always

OB

Next PSP ICHN2 (NPI2)

Always

Always

OC

IOU Pointer ICHN1 (lPI1)

Always

Always

00

lOUD Queue Pointer ICHN1 (IPQI1)

Always

Always

OE

PSP Queue Pointer ICHN1 (PQPI1)

Always

Always

OF

Next PSP ICHN1 (NPI1)

Always

Always

10

IOU Pointer ICHNO (IPIO)

Always

Always

11

lOUD Queue Pointer ICHNO (IQPIO)

Always

Always

12

PSP Queue Pointer ICHNO (PQPIO)

Always

Always

13

Next PSP ICHNO (NPIO)

Always

Always

14

lOUD Shadow Register (ISR)

Always

Always

15

ODUD Shadow Register (OSR)

Always

Always

161F

Reserved

N/A

N/A

TABLE 5-5. Limit RAM Registers
Group

Address

R
A
M

Access Rules
Read
Write

REQ Queue Limit RCHN1 (RQLR1)

Always

Always

CNF Queue Limit RCHN1 (CQLR1)

Always

Always

2

REQ Queue Limit RCHNO (RQLRO)

Always

Always

3

CNF Queue Limit RCHNO (CQLRO)

Always

Always

4

lOUD Queue Limit ICHN2 (IQLl2)

Always

Always

5

PSP Queue Limit ICHN2 (PQLl2)

Always

Always

6

lOUD Queue Limit ICHN1 (IQLl1)

Always

Always

7

PSP Queue Limit ICHN1 (PQLl1)

Always

Always

8

lOUD Queue Limit ICHf\lO (IQLlO)

Always

Always

PSP Queue Limit ICHNO (PQLlO)

Always

Always

N/A

N/A

0

L
I
M
I
T

Register Name

9

A-F

Reserved

2-310

5.0 Control Information

(Continued)
PSP Queue Pointer Register: Points to the next available
PSP. Initialized by the host with the start address of the PSP
Queue, after the Queue has been initialized with valid PSP
Descriptors. As each PSP is read from memory, this register
is loaded with the address in the Next PSP Register.
Next PSP Register: Written by the BSI device with the PSP
fetched from the PSP Queue.

5.8 POINTER RAM REGISTER DESCRIPTIONS
The Pointer RAM Register set contains 32, 28·bit registers.
Registers 23 through 31 are reserved, and user access of
these locations produces undefined results.
Pointer RAM Registers are read and written by the host
usirig the Pointer RAM Operation (PTOP) service function
and are accessed directly by BSI device hardware during
Indicate and Request operations.
During Indicate and Request operations, Pointer RAM registers are used as addresses for ABus accesses of data and
Descriptors, i.e., the subchannel addresses for loads
(reads) of streams of PSPs, ODUs, ODUDs, and REQs, and
for stores (writes) of streams of IDUs, IDUDs, and CNFs.

Indicate Shadow Register: Written by the BSI device with
the start address of the last IDU copied to memory.
Request Shadow Register: Written by the BSI device with
the address of the current ODUD.
See Table 5-4 for Summary including address and access
rules.

Pointer RAM Registers include the following:

5.9 LIMIT RAM REGISTER DESCRIPTIONS
The Limit RAM Register set contains 16, 9-bit registers.
Registers 11 through 15 are reserved, and used access of
these locations produces undefined results.
The Limit RAM registers contain data values that define the
limits of each of the ten queues maintained by the BSI device.
Limit RAM Registers are read and written by the host using
the Limit RAM Operation (LMOP) service function when the
Status/Space Machine is in STOP Mode, and are read directly by BSI device hardware during Indicate and Request
operations.
Limit RAM Registers include the following:

ODU Pointer: Contains the address of an Output Data Unit.
During Request operations, this register is loaded by the BSI
device from the Location Field of its Output Data Unit Descriptor.
ODUD List Pointer: Loaded by the BSI device from the
Location Field of the REQ Descriptor when it is read from
memory. The address is incremented by the BSI device as
each ODUD is fetched from memory.
CNF Queue Pointer: Contains the current CNF Status
Queue address. This register is written by the user after he
has allocated space for the CNF Queue. During Request
operations, this register is incremented by the BSI device
after each CNF is written to the CNF Queue.
REQ Queue Pointer: Initialized by the host with the start
address of the REQ Descriptor Queue after the Queue has
been initialized. During Request operations, the address is
incremented by the BSI device as each REQ is fetched.

REQ Queue Limit: Defines the last valid REQ written by the
host.
CNF Queue Limit Register: Defines the last Queue location where a CNF may be written by the BSI device. Due to
pipelining, the BSI device may write up to two CNFs after it
detects a write to the next-to-Iast CNF entry (and generates
a No Status Space Attention). For this reason, the host must
always define the CNF queue limit to be one Descriptor less
than the available space.

IOU Pointer: Written by the BSI device with the Location
Field of the PSP Descriptor when it is read from memory.
lOUD Queue Pointer: Points to the Queue location where
IDUDs will be stored. Written by the user after he has allocated space for the IDUD Status Queue. Incremented by
the BSI device as IDUDs are written to consecutive locations in the Queue.

lOUD Queue Limit Register: Defines the last Queue location where an IDUD may be written by the BSI device.
PSP Queue Limit: Defines the last valid PSP written by the
host.
See Table 5-5 for Summary including address and access
rules.

II

2-311

5.0 Control Information (Continued)
5.10 BSI DEVICE DESCRIPTORS
Input Data Unit Descriptor (lOUD)
Input Data Unit Descriptors (IOU Os) are generated on Indicate Channels to describe where the BSI device wrote each frame
part and to report status for the frame.
For multi.part IDUDs, intermediate status is written in each lOUD, and when a status event occurs, definitive status is written in
the last IDUO.
A detailed description of the encodings of the Indicate Status bits is given in Table 5·6.
31

29

30

28

27

IS

I

I

F-L

24
FRA

I

RES

23

I

16
FRS

15

I

VC

I

14

13
RES

12

I

LOC

0
CNT

I

WordO
Word 1

Word 0
Bit

Symbol

Description

00-12

CNT

Byte Count: Number of bytes in the SOU.

013-14

RES

Reserved

VC

VCOPY: Reflects the state of the VCOPY signal sent to the BMAC device for this
frame.
0: VCOPY was negated.
1: VCOPY was asserted.

FRS

Frame Status: This field is valid only for Full Confirmation, and if the frame ended
with an ED.

016-17

C

C Indicator:
00: none
01: R
10: S
11: T

018-19

A

A Indicator:
00: none
01: R
10: S
11: T

020-21

E

E Indicator:
00: none
01: R
10: S
11 : T

022

VFCS

Valid FCS:
0: FCS field was invalid
1: FCS field was valid

023

VOL

Valid Data Length:
0: Data length was invalid
1: Oata length was valid

015

016-23

2·312

5.0 Control Information (Continued)
5.10 BSI DEVICE DESCRIPTORS (Continued)
Input Data Unit Descriptor (IDUD) (Continued)
Word 0 (Continued)
Bit

Symbol

024-27

Description

FRA

Frame Attributes

02425

TC

Termination Condition: This field is valid only for Full Confirmation.
00: Other (e.g., MAC Reset/token).
01: ED.
10: Format error.
11: Frame stripped.

026

AFLAG

AFLAG: Reflects the state of the AFLAG input Signal, which is sampled by the BSI device at
INFORCVO.This field is valid only for Full Confirmation.
0: External OA match.
1: Internal OA match.

027

MFLAG

MFLAG: Reflects the state of the MFLG input signal, which is sampled by the BSI device at INFORCVO.
This field is valid only for Full Confirmation.
0: Frame sent by another station.
1: Frame sent by this station.

IS

Indicate Status: The values in this field are prioritized, with the highest number having the highest
priority. A detailed description of the encodings is given in Table 5-6.
153
152 151 ISO Meaning
Non-end Frame Status
0
0
0
0
Last IOU of queue, page-cross.
0
1
Page boundary crossed.
0
0
0
0
1
0
End of header.
0
0
1
1
Page-cross with header-end.
Normal-end Frame Status
0
0
0
Intermediate (no breakpoints).
1
Burst boundary.
0
1
0
1
0
1
1
0
Threshold.
1
1
Service opportunity.
0
1
Copy Abort due to No Space
1
0
0
0
No data space.
0
0
1
No header space.
1
0
Good header, info not copied.
1
0
1
Not enough info space.
1
0
1
1
Error
1
1
0
0
FIFO overrun.
0
1
Bad frame (no VOL or no VFCS).
1
1
0
Parity error.
1
1
1
Internal error.
1
1
1
1

028-31

Word 1
Bit
00-27

Symbol
LOC

Description
Location: 28-bit memory address of the start of an IOU. For the first IOU of a frame, the address is of
the fourth FC byte of the burst-aligned frame (i.e., bits [1 :0] = 11). For subsequent 10Us, the address
is of the first byte of the IOU (i.e, bits [1 :0] = 00).

028-29

RES

Reserved

030-31

F-L

First/Last Tag: Identifies the IOU object part, i.e., Only, First, Middle, or Last.

2-313

,.

5.0 Control Information (Continued)
TABLE 5-6. Indicate Status Field (IS) of IOU Descriptor
NON-END FRAME STATUS
[0000]

Last lOUD of Queue, with a Page Cross: The last available location of the ICHN's lOUD queue was written. Since there
was a page cross, there was more data to be written. Since there was no more lOUD space, the remaining data was not
written. Note that this code will not be written in a IOU. Middle, so that a Zero IS field with Zero F-L tags can be utilized by
software as a null descriptor.

[0001]

Page Cross: Must be an IDUD.FIRST or IDUD.MIDDLE. This is part of a frame that filled up the remainder of the current
page, requiring a new page for the remainder of the data.

[0010]

Header End: This refers to the last IOU of the header portion of a frame.

[0011]

Page Cross and Header End: The occurrence of a page cross and header end.

NORMAL-END FRAME STATUS
[0100]

Intermediate: A frame ended normally, and there was no breakpoint.

[0101]

Burst Boundary: A frame ended normally, and there was a breakpoint because a burst boundary was detected.

[0110]

Threshold: The copied frame threshold counter was reached when this frame was copied, and the frame ended normally.

[0111]

Service Opportunity: This (normal end) frame was preceeded by a token or MACRST, a MAC frame was received. or there
was a ring-op change. Any of these events marks a burst boundary.

NO SPACE COPY ABORT
[1000]

Insufficient Data Space: Not all the frame was copied because there was insufficient data space. This code is only written
in non-Headerllnfo Sort Mode.

[1001]

Insufficient Header Space: The frame copy was aborted because there was insufficient header space (in Headerllnfo
Sort Mode).

[1010]

Successful Header Copy, Frame Info Not Copied: There was sufficient space to copy the header, but insufficient data
space to copy info, or insufficient IOU space (on ICHN2), or both. No info was copied.

[1011]

No Info Space: The frame's header was copied. When copying the data, there was insufficient data and/or IOU space.

ERROR
[1100]

FIFO Overrun: The Indicate FIFO had an overrun while copying this frame.

[1101]

Bad Frame: The frame did not have a valid data length, or had invalid FCS, or both.

[1110]

Parity Error: There was a parity error during this frame.

[1111]

Internal Error: There was an internal logic error during this frame.

2-314

5.0 Control Information

(Continued)
The BSI device checks for the following inconsistencies
when the REO is loaded from memory:

REQ Descriptor (REQ)
Request Descriptors (REOs) contain the part, byte address,
and size of one or more Output Data Unit Descriptors. They
also contain parameters and commands to the BSI device
associated with Request operations.

1. REO.F with invalid Confirmation Class (as shown in the
Table 5-8).
2. REO. First with Request Class = O.

Multiple REO Descriptors (parts) may be grouped as one
Request Descriptor object by the host software, with the
REO. First defining the parameters for the entire Request
object. Also, multiple Output Data Unit Descriptors may be
grouped contiguously, to be described by a single REO Descriptor.

3. REO.First, when the previous REO was not a REO.Last
or REO.Only.
4. REO which is not a REO. First, when the previous REO
was a REO. Last or a REO.Only.
When an inconsistency is detected, the BSI device aborts
the Request, and reports the exception in the Request
Status field of the CNF Descriptor.

Each REO part is fetched by the BSI device from the Request Channel's REO Descriptor Oueue, using the REO
Oueue Pointer Register. Each Request Channel processes
ane Request Descriptor, per service opportunity, until a
REO. Last is encountered.
31

30

29

28

RES

I

27
UID

I

F-L

RES

I

24

The encodings of the ROCLS and CNFCLS bits are described in more detail in Tables 5-7 and 5-8 respectively.

23

I

16
SIZE

15

I

12

CNFCLS

11

I

8
ROCLS

LOC

0

7

I

FC

Word 0

I

Word 1

Word 0
Bit

Description

Symbol

00-7

FC

Frame Control: Frame control field to be used unless FC transparency is enabled. This field is
decoded to determine whether to assert ROCLM or ROBCN. This decoding is always active, i.e.,
regardless of frame control transparency. This field is also used for comparing received frames
when confirming (without FC transparency).

08-11

ROCLS

Request/Release Class: This field encodes the Request Class for the entire Request object, and is
thus only sampled on a REO.First or REO.Only. The field is asserted on the RORCLS output signals
to the BMAC device when requesting a token. If the Request Class is incompatible with the current
ring state, the BSI device sets the RCHN's USR bit in the Request Attention Register. The encoding
of this field is shown in Table 5-7.

012-15

CNFCLS

Confirmation Class: This field encodes the Confirmation Class for the entire Request object, and is
only sampled on a REO.First or REO.Only. The encoding of this field is shown in Table 5-8.

012

E

End: Enables confirmation on completion of request.
0: CNFs on completion disabled.
1: CNFs on completion enabled.

013

I

Intermediate: Enables Intermediate Confirmation.
0: Intermediate CNFs disabled.
1: Intermediate CNFs enabled.

014

F

Full/Transmitter: Selects between Transmitter and Full Confirmation.
0: Transmitter confirm.
1: Full confirm.

015

R

Repeat: Enables repeated transmission of the first frame of the request until the request is aborted.
This may be used when sending BEACON or CLAIM frames.
0: Fetch all frames of REO.
1: Repeat transmission of first frame of REO.
A Request may use Repeat on RCHN1, and have a Request loaded on RCHNO, but not vice-versa.
Specifically, when a Request with the Repeat option is loaded on RCHNO, RCHN1 must not have
any REOs active or visible to the BSI device. Thus REOs on RCHN1 may be queued externally but
the queue's Limit Register must not be set at or after that point. Requests with the Repeat option
should only be used on one Request Channel at a time, and preferably on RCHNO.

2-315

fI

5.0 Control Information (Continued)
REO Descriptor (REO) (Continued)
Word 0 (Continued)
Bit

Symbol

Description
Size: Count of number of frames represented by the ODUD stream pOinted to by LOC. REO Descriptors
with a frame count are permitted, and are typically used to end a Request, without having to send data.
For example, to end a restricted dialogue, a REO.Last with SIZE = 0 will cause the Request Machine to
command the BMAC device to capture and release the specified classes of token. The response of the
BSI device to REOs with SIZE = 0 is as follows:
1. REO. First: BSI device latches the REO DeSCriptor fields, then fetches the next REO. REORCLS is
asserted, but RORDY remains deasserted.
2. REO.Middle: BSI device fetches the next REO.
3. REO.Only: BSI device requests the capture of the appropriate token. When it is captured, the BSI
asserts ROFINAL and ends the request.
4. REO. Last: BSI device captures the token, asserts ROFINAL, then marks the req~est complete.

D16-23

SIZE

D24-29

UID

User Identification: Contains the UID field from the current REO.First or REO.Only.

D30-31

RES

Reserved

Word 1

Bit
DO-27

Symbol

Description

LOC

Location: Bits [27:2] are the memory word address of ODUD stream. Bits [1 :0] are expected to be 00,
and are not checked.

D28-29

RES

Reserved

D30-31

F-L

FlrsVLast Tag: Identifies the ODUD stream part, i.e., Only, First, Middle, or Last.

2-316

5.0 Control Information (Continued)
TABLE 5·7. REQ Descriptor Request Class Field Encodlngs
RQCLS
Value

RQCLS
Name

Class
Type

THT

Token
Capture

Token
Issue

Notes

0000

None

None

-

none

non

0001

Apr1

Async pri1

E

non-r

non-r

0010

Reserved

Reserved

0011

Reserved

Reserved

0100

Syn

Sync

D

any

capt

1

0101

Imm

Immed

D

none

none

4

0110

ImmN

Immed

D

none

non-r

4
4

0111

ImmR

Immed

D

none

restr

1000

Asyn

Async

E

non-r

non-r

1001

Rbeg

Restricted

E

non-r

restr

2,3

1010

Rend

Restricted

E

restr

non-r

2
2

1011

Rent

Restricted

E

restr

restr

1100

AsynD

Async

D

non-r

non-r

1101

RbegD

Restricted

D

non-r

restr

2,3

1110

RendD

Restricted

D

restr

non-r

2

1111

RcntD

Restricted

D

restr

restr

2

E = enabled, D = disabled, non·r = non·restricted, restr = restricted, capt = captured
Note 1: Synchronous Requests are not serviced when bit BCNR of the Ring Event Latch Register Is set.
Note 2: Restricted Requests are not serviced when bit BCNR, CLMR, or OTRMAC of the Ring Event Latch Register is set.
Note 3: Restricted Dialogues only begin when a Non-Restricted token has been received and transmitted.
Nota 4: Immediate Requests are serviced when the ring is Non-Operational. These requests are serviced from the Data state I! neither signal ROCLM nor ROBCN
is asserted. I! signal ROCLM is asserted, Immediate Requests are serviced from the Claim State. I! signal ROBCN is asserted, Immediate Requests are serviced
from the Beacon State. ROCLM and ROBCN do not cause transitions to the Claim and Beacon States.

TABLE 5·8. REQ Descriptor Confirmation Class Field Encodlngs
[R]

[F]

[I]

[E]

Confirmation Class

x
x
0
0
0

0
x
x
0
0

0
1
0
0
1

0
0
0
1
1

0
0

1
1

0
1

1
1

1
1

1
0

0
0

0
1

1

0

1

1

1

1

0

1

1

1

1

1

Invalid (conSistency failure)
Invalid (consistency failure)
None: Confirmation only on exception
Tend: Transmitter confirm, CNF on exception or completion
Tint: Transmitter confirm, CNF on exception,
completion or intermediate
Fend: Full Confirm, CNF on exception or completion
Fint: Full Confirm, CNF on exception,
completion or intermediate
NoneR: Confirmation only on exception, repeat frame
TendR: Transmitter confirm, CNF on exception
or completion, repeat frame
TintR: Transmitter confirm, CNF on exception, completion
or intermediate, repeat frame
FendR: Full confirmation, CNF on exception or
completion, repeat frame
FintR: Full Confirmation, CNF on exception,
completion, or intermediate, repeat frame

2-317

5.0 Control Information (Continued)
Output Data Unit Descriptor (ODUD)
An Output Data Unit Descriptor (ODUD) contains the part, byte address and size of an Output Data Unit. During Request
operations, ODUDs are fetched by the BSI device from a list in memory, using the address in the ODUD List Pointer Register (in
the Pointer RAM).
ODUDs may have a zero byte count, which is useful for fixed protocol stacks. One layer may be called, and if it has no data to
add to the frame, it may add an ODUD with a zero byte count to the list.
The BSI device checks for the following inconsistencies when an ODUD is loaded from memory:

1. ODUD.First, when the previous ODUD was not an ODUD.Last or ODUD.Only.
2. ODUD which is not an ODUD.First, when the previous ODUD was an ODUD.Last or ODUD.Only.
3. ODUD.First with zero byte count.
When an inconsistency is detected, the BSI device aborts the Request, and reports the exception in the Request Status field of
the CNF Descriptor.
ODUDs must contain at least 4 bytes (for short addresses).

31

30

29

28

27

I

F-L

I

RES

12

13

I

RES

I

LOC

0
Word 0

CNT

I

Word 1

Word 0
Bit

Description

Symbol

00-12

CNT

Byte Count: Number of bytes in the ODU. The size may be Zero, which is useful for fixed
protocol stacks.

013-31

RES

Reserved

Word 1
Bit

00-27

Symbol

Description
Location: Memory byte address of SOU.

LOC

028-29

RES

Reserved

030-31

F-L

First/Last Tag: Identifies the Output Data Unit part, i.e., Only, First, Middle, or Last.

,

2-318

5.0 Control Information

(Continued)

Confirmation Status Message Descriptor (CNF)
A Confirmation Status Message (CNF) describes the result of a Request operation.
A more detailed description of the encoding of the RS bits is given in Table 5-9.
31

30

29

28

27

I

RS

I

I

F-L

UID

24

23

FRA

16

15

FRS

I

FC

7

8
TFC

I

CS

0
CFC

I

RES

Word 0

I

Word 1

Word 0
Bit

Symbol

Description

DO-7

CFC

Confirmed Frame Count: Number of confirmed frames. Valid only for Full
Confirmation.

D8-15

TFC

Transmitted Frame Count: Number of frames successfully transmitted by the
BSI device and BMAC device. Valid for all confirmation classes.

D16-23

FRS

Frame Status: This field is valid only for Full Confirmation, and if the frame
ended with an ED.

D16-17

C

C Indicator:
00: None
01: R
10: S
11 : T

D18-19

A

A Indicator:
00: None
01: R
10: S
11: T

D20-21

E

E Indicator:
00: None
01: R
10: S
11: T

D22

VFCS

Valid FSC:
0: FSC Field was Invalid.
1: FSC Field was Valid.

D23

VDL

Valid Data Length:
0: Data Length was Invalid.
1: Data Length was Valid.

D24-27

FRA

Frame Attributes: This field is valid only for Full Confirmation.

TC

Terminating Condition:
00: Other (e.g., MAC Reset/token).
01: Ed.
10: Format Error.
11: Frame Stripped.

D26

AFLAG

AFLAG: Reflects the state of the AFLAG input signal, which is sampled by the
BSI device at INFORCVD.
0: No DA Match.
1: DAMatch.

D27

MFLAG

MFLAG: Reflects the state of the MFLAG input Signal, which is sampled by the
BSI device at INFORCVD.
0: Frame Sent by another Station.
1: Frame Sent by this Station.

D24-25

2-319

5.0 Control Information (Continued)
Confirmation Status Message Descriptor (CNF) (Continued)
Word 0 (Continued)
Bit

028-31

Description

Symbol
RS

Request Status: This field represents a priority encoded status value, with the highest number having the
highest priority. This field is described in Table 5-9.
Meaning
RS2
RS3
RS1
RSO
Intermediate
0
0
0
0
None
0
0
Preempted
1
0
0
0
1
0
Part Done
Breakpoints
0
0
1
1
Service Loss
0
0
1
Reserved
0
Completion
0
1
0
1
Completed BEACON
0
1
1
0
Completed OK
Exception Completion
0
1
1
1
Bad Confirmation
1
0
0
0
Underrun
1
0
1
Host Abort
0
1
0
1
0
Bad Ringop
0
1
1
1
MAC Abort
1
1
0
0
Timeout
1
1
1
MAC Reset
0
1
1
1
0
Consistency Failure
Error
1
1
1
1
Internal or Fatal ABus Error

2-320

5.0 Control Information

(Continued)

Confirmation Status Message Descriptor (CNF) (Continued)
Word 1
Bit

Symbol

00-7

RES

08-15

Description
Reserved

CS

Confirmation Status

FT

Frame Type: This field reflects the type of frame that ended Full Confirmation.
00: Any Other.
01: Token.
10: Other Void.
00: My Void.

010

F

Full Confirm: This bit is set when the Request was for Full Confirmation.

011

U

Unexpected Frame Status: This bit is set when the frame status does not
match the value programmed in the Request Expected Frame Status Register.
This applies only to Full Confirmation.

012

P

Parity: This bit is set when a parity error is detected in a received frame. Parity is
checked from FC to EO inclusive if the FLOW bit in the Mode Register is set.

013

E

Exception: This bit is set when an exception occurs. The RCHN's EXC bit in the
Request Attention Register is also set.

014

R

Ring-Op: This bit is set when the ring enters a bad operational state after
transmission but before all returning frames have been confirmed.

015

T

Transmit Class:
0: Restricted.
1:· Non-Restricted.

016-23

FC

Frame Control: Frame Control field of the last frame of the last confirmed burst,
Valid only for Full Confirmation.

024-29

UIO

User Identification: Contains the UIO field copied from the current REQ.FIRST
or REQ.ONLY.

D30-31

F-L

First/last Tag: Identifies the CNF part, i.e., Only, First, Middle, or Last.

08-9

2-321

5.0 Control Information (Continued)
TABLE 5-9. Request Status (RS) Field of CNF Descriptor
INTERMEDIATE
[0000]

None: Non status is written. This may be used by software to identify a NULL or invalid CNF.

[0001]
[0010]

Preempted: RCHN1 was preempted by RCHNO. RCHNI will be serviced following RCHNO.
Part None: The BSI device is servicing a Request, but it cannot hold onto a token, and the last frame of a
Request.part has been transmitted.

BREAKPOINTS
[0011]

Service Loss: The THT expired during a Request with THT enabled. Only occurs for Intermediate Confirmation.

[0100]

Reserved

COMPLETION
[0101]

Completed BEACON: When transmitting from the BEACON state, this status is returned when the BMAC device
receives a My_Beacon. When transmitting from the CLAIM state, this status is returned when the BMAC device
wins the CLAIM process.

[0110]

Completed OK: Normal completion with good status.

EXCEPTION COMPLETION
[0111]

Bad Confirmation: There was an error during confirmation, causing the Request to complete with this status, or one
of higher priority. Confirmation errors include MACRST, ring-operational change, receiving an Other_Void or My_
Void or token, receiving a bad frame, or receiving a frame that did not match the programmed expected frame status.

[1000]

Underrun: There was no data in the request data FIFO when it was required to be presented to the BMAC device.

[1001]

Host Abort: The host aborted the Request on this Request Channel, either directly by clearing the ABT bit in the
Service Attention Register or indirectly by having insufficient entries in the CNF queue.

[1010]

Bad Rlngop: A Request was loaded with a Request Class inappropriate for the current ring operational state.

[1011]

MAC Device Abort: The BMAC device aborted the Request and asserted TXABORT. This could be from an
interface parity error, or because the transmitted frame failed the FC check, or because the BMAC device received a
MAC frame while transmitting in the BEACON state. This status is also returned when the BMAC device receives an
Other_Beacon while the BSI device is transmitting in the BEACON state, or when the CLAIM process is lost while
the BSI device is transmitting in the CLAIM state.

[1100]

Timeout: The TRT expired during a Request with THT disabled. The Request is aborted.

[1101]

MAC Reset: The BMAC device asserted MACRST.

[1110]

Consistency Failure: There was an inconsistency within the REQ or ODUD stream.

ERROR
[1111]

Internal or Fatal ABus Error: There was an internal logic error or a fatal ABus error while writing a CNF.

2-322

C

"tJ

5.0 Control Information (Continued)

CC)

Pool Space Descriptor (PSP)

en

Co)

N

Pool Space Descriptors (PSPs) contain the address and size (in bytes) of a free space in host memory available for writing Input
Data Units. When PSPs are read by the BSI device, the address field of the PSP is loaded into the Indicate Channel's IOU
Pointer Register, and is used as the subchannel address for the IOU memory write.
31
30
29
28
27
13
12
0

I

RES

I

I

F-L

RES

I

Word 0

CNT

LOC

I

Word 1

Word 0
Bit

Symbol

Description

00-12

CNT

Byte Count: Number of bytes in the available memory area (up to 4k bytes).

013-31

RES

Reserved

Word 1
Bit

Symbol

Description

00-27

LOC

Location: Memory byte address of memory area available for writing 10Us. Normally the
page offset will be Zero to simplify space management.

030-31

RES

Reserved

2-323

CJ1

U) , - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,

CD

C\I
C')

CD

D-

C

6.0 Signal Descriptions
6.1 PIN ORGANIZATION
The BSI device pinout is organized into five groups:
Control Interface: Used for host microprocessor access to the BSI device.
BMAC Device Indicate Interface: Pins for receiving and processing incoming frames from the DP82361 BMAC device.
BMAC Device Request Interface: Pins for transmitting frames to the BMAC device.
ABus Interface: Pins for transferring data and data information between system memory and the BSI device.
Electrical Interface: Pins associated with power supply, clocking, and scan test.

I :IL.iCR(O
2 oILERR(O
3 AU4(0)
4 .lLA3(o)

.lLAD5(VO)
AUD4(VO)
AB..AD.l(Vo)
oILAD2(I/O)

ABUS Interface

5 AIl..A2(O)

oILRYi(O)
Ai:iiEN(O)
I
10
II
12
13
14
15
18
17
18
II
20
21
22
23
24
25
21
27
28
21
30
31
32
33
34

GND

Vee

Vee
GNO

ALSIZ2(O)
ALSIZ1(0)
ALSIZO(O)
lDR(0)
.100(1)

FCRCVil(I)
MIDS(O
AfUG(1)
MFUG(I)
SAMESA(O
INroRCVD(O
SAWDNrO(Q
EDRCVD(Q
YFCS(I)

DP83265
BSI
160-PIN PQFP

VDL(Q
TKRCVD(O

ttl

tt8
tt7
ttl
tt5
tt4

oILADl(VO) m
AB...AOD(I/O) tt2
oIL8PO(I/O) Itt
CBP(I/O) ttO
CBD7(I/O) 101
CBDI(VO) 108
~I/O) 107
CB04(I/O) 108
GND 105
Vee 104
CBD3(I/O) 103
CB02(I/O) 102
CBDt(VO) 101
CBDO(I/O) 100

CBA4(Q II
CW(Q

88

CIA2(Q 17
CBAl(Q
CBAO(Q
ACK(DO)
iili(OD)

roERRoR(Q
FRSTRP(Q
VCOPY(O)
WACRST(Q
MIP(I)
WID7(Q
MI06(O
WID5(I)
WI04(O

18
15
14
15

ii(O 12
RYi(Q

II

RST(Q 10
SAT(O)
STRI'(O)
GND

81
88
87

35

"103(0

Vee

86

31

WI02(O
WID1(Q
WIDO(O

rcsr(O)
RQCLII(O)
RQ8CN(O)

85
84
83

GNO(....)

82
81

37
38

31

Vcc<....)

40

GNO(....)

MAC Request Interface

Vcc<....)

TL/F/l0791-12

FIGURE 6·1. DP83265 160·Pin Pinout

Order Number DP83265VF
See NS Package Number VF160A

2-324

6.0 Signal Descriptions (Continued)
DP83265 Pinout Description
Pin

1

Description

ABJCK

2

AB_ERR

1/0

Pin

Description

I

41

LBC1

I

42

1/0

Pin

I

81

1/0

Pin

Description

1/0

Vee

Core

121

ABJD7

I/O

Core

122

AB_BP1

I/O
I/O

Description

LBC3

I

82

GND

I

3

ABJ4

0

43

LBC5

83

RQBCN

0

123

ABJD8

4

ABJ3

0

44

GND

84

RQCLM

0

124

GND

FCST

0

125

Vee

126

ABJD9

5

ABJ2

0

45

NC

85

6

AB_RW

0

46

NC

86

7

AB_DEN

0

47

GND

87

GND

8

Vee

48

NC

88

STRIP

0

9

GND

Vee

I/O

127

ABJD10

I/O

128

ABJD11

I/O
I/O

49

ECIP

I

89

SAT

0

129

ABJD12

10

AB_SIZ2

0

50

EA

I

90

RST

I

130

ABJD13

I/O

11

AB_SIZ1

0

51

EM

I

91

RW

I

131

ABJD14

I/O

12

AB_SIZO

0

52

MRQO

0

92

CE

I

132

ABJD15

i/O

13

AB_BR

0

53

MRQ1

0

93

INT

OD

133

AB_BP2

I/O

14

AB_BG

I

54

MRQ2

0

94

ACK

OD

134

GND

15

FCRCVD

I

55

MRQ3

0

95

CBAO

I

135

Vee

16

MIDS

I

56

Vee

96

CBA1

I

136

ABJD16

I/O

17

AFLAG

I

57

GND

97

CBA2

I

137

ABJD17

I/O

18

MFLAG

I

58

MRQ4

0

98

CBA3

I

138

ABJD18

I/O

19

SAMESA

I

59

MRQ5

0

99

CBA4

I

139

ABJD19

100

CBDO

I/O

140

GND

Core
Core

I/O

20

INFORCVD

I

60

MRQ6

0

21

SAMEINFO

I

61

MRQ7

0

101

CBD1

I/O

141

Vee

22

EDRCVD

I

62

MRP

0

102

CBD2

I/O

142

ABJD20

I/O

23

VFCS

I

63

TXRINGOP

I

103

CBD3

I/O

143

ABJD21

I/O

24

VDL

I

64

TXCLASS

I

104

144

ABJD22

I/O

25

TKRCVD

I

65

TXABORT

I

105

GND

145

ABJD23

I/O

26

FOERROR

I

66

TXED

I

106

CBD4

I/O

146

GND
Vee

Vee

27

FRSTRP

I

67

MRDS

I

107

CBD5

I/O

147

28

VCOPY

0

68

TXRDY

I

108

CBD6

I/O

148

AB_BP3

I/O

CBD7

I/O

149

ABJD24

I/O
I/O

29

MACRST

I

69

TXPASS

I

109

30

MIP

I

70

RQABORT

0

110

CBP

I/O

150

ABJD25

31

MID7

I

71

RQFINAL

0

111

AB_BPO

I/O

151

ABJD26

I/O

32

MID6

I

72

RQEOF

0

112

ABJDO

I/O

152

ABJD27

I/O

33

MID5

I

73

RQSEND

0

113

ABJD1

I/O

153

ABJD28

I/O

34

MID4

I

74

Vee

114

Vee

154

ABJD29

I/O

35

MID3

I

75

GND

115

GND

155

ABJD30

I/O

36

MID2

I

76

RQRDY

0

116

ABJD2

I/O

156

GND

37

MID1

I

77

RQRCLSO

0

117

ABJD3

I/O

157

Vee

38

MIDO

I

78

RQRCLS1

0

118

ABJD4

I/O

158

ABJD31

I/O

39

Vee

Core

79

RQRCLS2

0

119

ABJD5

I/O

159

ABJB

I/O

40

GND

Core

80

RQRCLS3

0

120

ABJD6

I/O

160

AB_CLK

I/O

2-325

6.0 Signal Descriptions (Continued)
6.2 CONTROL INTERFACE
The Control Interface operates asynchronously to the operation of the BMAC device and ABus interfaces.
The ACK and TfiI'j' signals are open drain to allow wire ORing.
Symbol

Pin #

1/0

Description

110

1/0

Control Bus Parity: Odd parity on CBD7 -0.

CBD7-0

109-106,
103-100

I/O

Control Bus Data: Bidirectional Data bus.

CBA4-0

99-95

I

Control Bus Address: Address of a particular BSI device register.

CE

92

I

Control Bus Enable: Handshake signal used to begin a Control
Interface access. Active low signal.

R/W

91

I

Read/Write: Determines current direction of a Control Interface
access.

ACK

94

00

Acknowledge: Acknowledges that the Control Interface access has
been performed. Active low, open drain signal.

INT

93

00

Interrupt: Indicates presence of one or more enabled conditions.
Active low, open drain signal.

RST

90

I

Reset: Causes a reset of BSI device state machines and registers.

CBP

2-326

6.0 Signal Descriptions (Continued)
6.3 BMAC Device Indicate Interface
The BMAC Device Indicate Interface signals provide data and control bytes as received from the BMAC device. Each Indicate
Data byte is also provided with odd parity.
MID7-0 signals are valid on the rising edge of the Local Byte Clock signal (provided by the Clock Recovery Device).
Data:
Symbol
MIP

MID7-0

Pin #

I/O

Description

30

I

MAC Indicate Parity: This is connected directly to the corresponding BMAC device
pin of similar name. Odd parity on MID7-0. Only valid with Data and Status
indicators.

31-38

I

MAC Indicate Data: This is connected directly to the corresponding BMAC device
pin of similar name.
Data: The BMAC device indicates data is being presented on MID7 -0 during the
time when RCSTART is asserted until one of the following Signals is asserted:
EDRCVD, TKRCVD, FOERROR, or MACRST.
Status: The BMAC device indicates Status Indicators are being presented on
MID7 -0 when EDRCVD or TKRCVD is asserted.

,

Frame Sequencing:
The Frame Sequencing Signals apply to the data available at the MAC Indicate Interface (MIP and MID7-0). The Frame
Sequencing signals can be used to control the latching of appropriate Frame Status.
Pln#

I/O

Description

FCRCVD

15

I

Frame Control Received: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates that the Frame Control Field
has been received.

INFORCVD

20

I

Information Field Received: This is connected directly to the corresponding
BMAC device pin of similar name. The BMAC device indicates that four bytes of the
Information Field have been received. It is asserted by the BMAC device on the
fourth byte of the INFO field and remains active until the next JK symbol pair is
received.

EDRCVD

22

I

EDFS Received: This is connected directly to the corresponding BMAC device pin
of similar name. The BMAC device indicates that the End of Frame Sequence has
been received.

MIDS

16

I

MAC Indicate Data Strobe: Asserted by BMAC device to indicate valid data. This
signal should be tied to Vee for FDDI-I, and used for FDDI-II.

Symbol

Frame Information:
Pin #

I/O

AFLAG

17

I

My Destination Address Recognized: This is connected directly to the
corresponding BMAC device pin of similar name. The BMAC device indicates that
an internal address match occurred on the Destination Address field. It is reset
when the next JK symbol pair is received.

MFLAG

18

I

My Source Address Recognized: This is connected directly to the corresponding
BMAC device pin of similar name. The BMAC device indicates that the received
Source Address field matched the MLA or MSA BMAC device registers. It is reset
when the next JK symbol pair is received.

SAMESA

19

I

Same Source Address: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates that the SA of the current
frame is the same as the previous frame, that the frames were not MAC frames, and
that the frames are the same size. It is reset when the next KJ symbol pair is
received.

SAMEINFO

21

I

Same MAC Information: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates that the first four bytes of
the IF of the current frame are the same as the previous frame, that the frames were
MAC frames, and that their address lengths are the same. SAMEINFO is asserted
along with INFORCVD. It is reset when the next JK symbol pair is received.

Symbol

Description

2-327

6.0 Signal Descriptions (Continued)
Frame Status:
Pin #

I/O

VOL

24

I

Valid Data Length: The BMAC device indicates a valid data length for the current
frame.

VFCS

23

I

Valid Frame Check Sequence: The BMAC device indicates a valid FCS for the
current frame.

TKRCVD

25

I

Token Received: The BMAC device indicates that a complete token was received.

FRSTRP

27

I

Frame Stripped: The BMAC device indicates that the current frame was stripped.

FOERROR

26

I

Format Error: The BMAC device indicates a standard-defined format error.

MACRST

29

I

MAC Reset: The BMAC device indicates an internal error, MAC frame, MAC reset,
or hardware or software reset.

EA

50

I

External AFlag: This signal is used by external address matching to signal that a
Destination Address (DA) match has occurred. Assuming that the proper timing of
EA and ECIP are met, the assertion of EA will cause the BSI device to copy this
frame. EA is sampled on the cycle after ECIP is deasserted. The sample window is
from FCRCVD to EDRCVD.

EM

51

I

External MFlag: This signal is used by external address matching logic to signal a
Source Address (SA) match. II is sampled on the clock cycle after ECIP is
deasserted.

VCOpy

28

0

Valid Copy: Affects the setting of the transmitted ex (Copied Indicator).
The value of VCOPY is used to determine the value of the transmitted Cx. VCOPY
must be asserted one byte time before EDRCVD is asserted.

ECIP

49

I

External Compare In Progress: This signal is asserted to indicate that external
address comparison has begun. II is deasserted to indicate that the comparison has
completed. EA and EM are sampled upon the deassertion of ECIP. ECIP must be
asserted during the period from the assertion of FCRVCD (by the BMAC device) to
the assertion of INFORCVD (by the BMAC device) in order for the BSI to recognize
an external comparison. II must be deasserted for at least one cycle for the external
comparison to complete. If ECIP has not been deasserted before EDRCVD (from
the BMAC device), the BSI device will not copy this frame. ECIP may be
implemented as a positive or negative pulse.

Symbol

Description

2-328

6.0 Signal Descriptions (Continued)
6.4 BMAC Device Request Interface
The BMAC Device Request Interface signals provide data and control bytes to the BMAC device as received from the Host
System. Each Request Data byte is also provided with odd parity.
Symbol
MRP
MRD7-0

Pin #

I/O

Description

62

0

MAC Request Parity: This is connected directly to the corresponding BMAC device
pin of similar name. Odd parity on MRD7 -0.

61-58,

0

MAC Request Data: This is connected directly to the corresponding BMAC device
pin of similar name. The BMAC device Indicates data is being presented on
MRD7-0.

55-52
Service Parameters:
Symbol

Pin #

I/O

Description

RQRCLS3-0

80-77

0

Request Class: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device Indicates the service class parameters for this
request. When RQRCLS > 0, the BMAC device Transmitter will capture a usable
token for non-immediate requests) and assert TXRDY. The service opportunity
continues as long as the token is usable with the current service parameters, even if
RQRDY is not asserted. When RQRCLS = 0, the service opportunity will terminate
aiter the current frame (even if RQRCLS subsequently becomes non-Zero).

RQCLM

84

0

Request CLAIM: This is connected directly to the corresponding BMAC device pin
of similar name. The BMAC device indicates that this request is to be serviced in the
Transmit CLAIM state. Ignored for non-immediate requests.

RQCBN

83

0

Request BEACON: This is connected directly to the corresponding BMAC device
pin of similar name. The BMAC device Indicates that this request Is to be serviced in
the Transmit BEACON state. Ignored for non-Immediate requests.

2-329

6.0 Signal Descriptions (Continued)
Frame Options:
Pin #

1/0

STRIP

88

0

Void Strip: Connected to STRIP and possibly SAT on the BMAC device.

SAT

89

0

Source Address Transparency: Connected to SAIGT on the BMAC device and to
SAT on the BMAC device if STRIP is not:

FCST

85

0

Frame Check Sequence Transparency: This is connected directly to the
corresponding BMAC device pin of similar name. When selected. the BMAC device
will not append FCS to the end of the Information field.

Symbol

Description

Request Handshake:
Symbol

Pin #

110

Description

TXPASS

69

I

Transmit Pass: This is connected directly to the.corresponding BMAC device pin of
similar name. The BMAC device indicates the absence of a service opportunity. This
could result from an unusable request class. waiting for a token. timer expiration. or
MAC Reset. TXPASS is always asserted between service opportunities. It is
deasserted when TXRDY is asserted at the beginning of a service opportunity.

TXRDY

68

I

Transmit Ready: This is connected directly to the corresponding BMAC device pin
of similar name. The BMAC device indicates that the BMAC device transmitter is
ready for another frame. For a non-immediate request. a useable token must be
held in order to transmit frames.
TXRDY is asserted by the BMAC device when:
a. a usable token is being held. or
b. an immediate request becomes serviceable. or
c. after frame transmission if the current service opportunity is still usable for
another frame.
TXRDY is deasserted when TXPASS or TXACK is asserted.

RORDY

76

0

Request Ready: This is connected directly to the corresponding BMAC device pin
of similar name. The BMAC device indicates that the BMAC device transmitter
should attempt to use a service opportunity.
If RORDY is asserted within 6 byte times after TXRDY is asserted. the BMAC device
transmitter will wait at least LMax plus one Void frame (4.16 ms - 4.80 ms) for
ROSEND to be asserted before releasing the token.

ROSEND

73

0

Request Send: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device indicates that the BMAC device transmitter should
send the next frame. The MRD7-0 signals convey the FC byte when this signal is
asserted.
If ROSEND is asserted within 6 byte times after TXRDY is asserted. the BMAC
device transmitter will send the frame with a minimum length preamble. If ROSEND
is not asserted within LMax plus one Void frame after RORDY has been asserted
(4.16 ms - 4.60 ms). the token may become unusable due to timer expiration.
ROSEND may only be asserted when TXRDY and RORDY are asserted and
ROFINAL is deasserted.
ROSEND must be deasserted not later than one byte time after TXRDY is
deasserted

MRDS

67

I

MAC Request Data Strobe: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates that data on MRD7 -0 is
valid. This signal should be connected to the TXACK on the BMAC device.

ROEOF

72

0

Request EOF: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device indicates that MRD7 -0 conveys the last data byte
when asserted. Normally. this is the last byte of the INFO field of the frame
(exceptions: FCS transparency. invalid frame length).
ROEOF causes TXACK to be deasserted and is ignored when TXACK is not
asserted.

2-330

6.0 Signal Descriptions (Continued)
Request Handshake: (Continued)
Symbol

Pin #

1/0

Description

ROABORT

70

0

Request Abort: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device indicates that the current frame should be aborted.
Normally this causes the BMAC device transmitter to generate a Void, CLAIM, or
BEACON frame.
ROABORT causes TXACK to be deasserted and is ignored when TXACK is not
asserted.

ROFINAL

71

0

Request Final: This is connected directly to the corresponding BMAC device pin of
similar name. The BMAC device indicates that the final frame of the request has
been presented to the BMAC device Interface.
When asserted, the Issue Token Class (as opposed to the Capture Token Class)
becomes the new Token Class (TXCLASS). ROFINAL may only be asserted when
RORDY is asserted and ROSEND is deasserted. ROFINAL is ignored unless
RORDY has been asserted for at least one byte time and the service parameters
have been valid for at least three byte times.
ROFINAL must be deasserted not later than two byte times after TXPASS is
deasserted.

TXED

66

I

Transmit End Delimiter: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates that the ED is being
transmitted.

TXABORT

65

I

Transmit Abort: This is connected directly to the corresponding BMAC device pin
of similar name. The BMAC device indicates that the MAC Transmitter aborted the
current frame.

Symbol

Pin #

1/0

Description

TXRINGOP

63

I

Transmit Ring Operational: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates the state of the MAC
Transmitter.

TXCLASS

64

I

Transmit Token Class: This is connected directly to the corresponding BMAC
device pin of similar name. The BMAC device indicates the class of the current
token.

Transmit Status:

•
2-331

U) r-----------------------------------------------------------------------~------__,

~
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~

6.0 Signal Descriptions (Continued)
6.5 ABus Interface
The ABus Interface signals provide a 32-bit multiplexed address/data bus for transfers between the host system and the BSI
device. The ABus uses a bus request/bus grant protocol that allows for multiple bus masters, supports burst transfers of 4 or 8
32-biI words, and permits both physical and virtual addressing using fixed-size pages.
Address and Data:
Symbol

Pin #

I/O

AB_BP3-0

148,133,
122,111

110

ABus Byte Parity: These TRI-STATE signals contain the BSI device-generated parity
for each address byte of ABJD, such that AB_BPO is the parity for ABJD7 -0,
AB_BP1 is the parity for ABJD15-B, etc.

ABJD31-0

15B,
155-149,
145-142,
139-136,
132-126,
123,
121-116,
113-112

110

ABus Address and Data: These TRI-STATE signals are the multiplexed ABus address
and data lines. During the address phase of a cycle, ABJD27 -0 contain the 28-bit
address, and ABJD31-28 contain a 4-bit function code identifying the type of
transaction, encoded as follows:
ABJD[31:28]
Transaction Type
o
RSAP1 ODU Load
1
RSAP1 ODUD Load/CNF Store
RSAP1 REO Load
2
RSAPO ODU Load
3
4
RSAPO ODUD Load/CNF Store
RSAPO REO Load
5
ISAP2 IDU Store
6
ISAP2 IDUD Store
7
ISAP2 PSP Load
B
ISAP1 IDU Store
9
ISAP1 IDUD Store
A
B
ISAP1 PSP Load
C
ISAPO IDU Store
D
ISAPO IDUD Store
ISAPO PSP Load
E
PTR RAM Load/Store
F

3-5

o

ABus Burst Address: These TRI-STATE signals contain the word address during burstmode accesses. They are driven from Tpa to the last Td state, negated in the following
Tr state, then released. Note that the address presented allows external pipelinlng for
optimum memory timing.

ABJ4-2

Description

2-332

6.0 Signal Descriptions (Continued)
Bus Control:
Symbol
ABJS

Pin # I/O
159

Description

0 ABus Address Strobe: When asserted, This TRI-STATE signal indicates that data on ABJD is valid.
When this signal is inactive and ABJCK is asserted, the next cycle is a Tr state, in which the bus arbiter
can sample all bus requests, then issue a bus grant in the following cycle.

AB_RW

6

0 ABus Read/Write: This TRI-STATE signal determines the current direction of an ABus access.

AB_DEN

7

0 ABus Data Enable: This TRI-STATE signal indicates that data on ABJD31-0 is valid.

AB_SIZ2-0 10-12 0

ABus Size: These TRI-STATE signals indicate the size of the transfer on ABJD31-0, encoded as
follows:
Transfer
AB_SIZO
AB_SIZ2
AB_SIZ1
Size
4 Bytes
0
0
0
Reserved
0
0
1
Reserved
1
0
0
1
Reserved
0
1
16 Bytes
0
1
0
1
32 Bytes
1
0
0
Reserved
1
1
Reserved
1
1
1

ABJCK

1

I

ABus Acknowledge: Indicates a bus slave's response to a bus master. The meaning of this signal
depends on the state of ABus Error (AB_ERR), as described below.

AB_ERR

2

I

ABus Error: This signal is asserted by a bus slave to cause a transaction retry or transaction abort.
Together with ABJCK, the encoding is as follows:
AB_ERR
AB-ACK
Definition
1
1
Insert Wait States
Bus Error
1
0
Transaction Retry
0
0
Acknowledge
0
1

Bus Arbitration:
Symbol

Pin #

I/O

Description

AB_BR

13

0

ABus Bus Request: This signal is used by a bus master to request use of the ABus.

AB_BG

14

I

ABus Bus Grant: This signal is asserted by external bus arbitration logiC to grant
use of the ABus to the BSI device. When AB_BG is deasserted, the BSI device
completes the current transaction and releases the bus. If AB_BG is asserted at
the start of a transaction (Tbr), the BSI device will run a transaction.

AB_ClK

160

I

ABus Clock: All ABus operations are synchronized to the rising edge of AB_ClK.

•
2-333

6.0 Signal Descriptions (Continued)
6.6 ELECTRICAL INTERFACE
Symbol

Pin #

I/O

LBC5, 3, 1

43-41

I

Description
Local Byte Clock: 12.5 MHz clock with a 60/40 duty-cycle. Generated by CDD.

Vccl13)

8,39,56
74,81,86,
104,114,
125,135,
141,147,157

Positive Power Supply: 5V, ± 100/0 relative to GND.

GND[13)

9,40,57
75,82,87,
105,115,124,
134,140,146,
156

Power Supply Return.

GND
NC

44,47
45,46,48

Must be grounded.
No Connect: Must be left unconnected.

2-334

Section 3
Development Support

Ell

Section 3 Contents
OP83200EB FOOl AT Evaluation Kit...... ........... ..... ........... .... .............
OP83200SMT XLNT Manager FOOl Station Management (SMT) Software Support Package.

3-2

3-3
3-15

C

"tI

co

~National

W

~

~ Semiconductor
OP83200EB
FOOl AT Evaluation Kit

o

m

til

General Description
The OP83200EB FOOl is a complete design/evaluation kit
(using an AT or compatible platform), that includes hardware, software and application documentation, to implement a single node compliant with an ANSI X3T9.5 FOOl
network. The kit has been designed to demonstrate the capabilities of National Semiconductor's FOOl chip set.

The DP83200EB can be combined with a OP83200EK Kit to
create a dual attach station. The OP83200EK Kit contains
the additional Link card (PHY Layer) and appropriate cables.

It contains a Link card and MAC card, that together implement one FOOl Single Attach node.
The Evaluation Boards allow evaluation of the many capabilities of the chip set and serve as an educational tool for
customers deSigning products with the FOOl chip set. High
performance as a goal was sacrificed at the expense of
simplicity and accessibility. There are many laboratories
around the world with a spare IBM® PC® or compatible.

• System modularity supports single attachment or dual
attachment
• Utilizes a PC-AT® compatible form factor
• Built-in diagnostic capability for fault detection
• Supports an external optical bypass switch
• Supports asynchronous and synchronous transmission
classes
II PAL based buffer management
III Supported by demonstration and diagnostic software
III Board schematics

Features

These boards allow users to experiment and gain experience with the FOOl chip set in order to unleash its capabilities in their own products.

II
3-3

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TLlF/11122-2

SAS Configuration

TLlF/III22-3

DAS Configuration

FIGURE 1. Single attach and optional dual attach configuration
3-4

IC
"tJ

1.0 Link Card

CI)

• System modularity supports single attachment or dual
attachment configurations.
• Utilizes a PC-AT compatible form factor
• Built-in diagnostic capability for fault detection
• Supports an external optical bypass switch
• Power consumption is 1.5 amps typical per Link Card

1.1 Link Card Description
The Link Card is intended for evaluation of the following
three National Semiconductor devices which implement the
FOOl Physical Layer and clock distribution.
DPB3255 Physical Layer Controller (PLAYERTM device)
DPB3241 Clock Distribution Device (CDDTM device)
DPB3231 Clock Recovery Device (CRDTM device)

2.0 Link Card System Description
2.1 Block Diagram Description

The design goal of the Link Card was to allow the user to
exercise the Physical Layer devices and COD device. The
Link Card can be used in tandem with the DPB3291 EB MAC
Card (see Section 2.3). A Link Card connected to a single
MAC Card inplements a single attachment station. Dual attachment stations require two Link Cards. The Link Card
requires a PC-AT compatible machine which is a readily
available platform capable of supporting an FOOl application.

The Link Card block diagram is composed of the following
seven blocks:
1. AT Bus Interface
2. Clock Bus Interface
3. Clock Distribution Device (COD device)
4. Clock Recovery Device (CRD device)
5. Link Bus Interface

1.2 Link Card Features

6. Physical Layer Controller (PLAYER device)

The Link Card offers many features to provide a flexible and
convenient evaluation platform:
• Utilizes the National FOOl Chip Set
DP83255 PLAYER Device
DP83241 COD Device
DP83231 CRD Device

7. Transceiver Interface

Figure 2 is a detailed representation of the block diagram .

3-5

W

I'.)

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2.0 Link Card System Description

C')

EXTERNAL
CONNECTORS

co

a.

(Continued)

liNK CARD
INTERFACE

'~--+

C

--+

CLOCK
BUS

...z~
":~ r-

A PORT

...

B PORT

CDDClK 12.5 +
CDDClK 12.5-

CDDClK 12.5

DS3695
TRANSCEIVER

A PORT INDICATE

0

>=

LINK

_

U

'::>!;;:

Y

10

-244

' 10

'L::'
'::>!;;:
::E
0

b'"
t;;

3

--+
lA ADDR

"-

841

MAC CTl

0

'"u0
..J

,S!
B PORT REQUEST

u

,L

B PORT INDICATE

BUS

'":::>
;;:
"z

.r;;l

A PORT REQUEST

"S!

....

SA ADDR

"t::

DATA

co

AT CTl

"....

IRQ

"....

AT DATA

co

AT ADDR

,on"

u

PLAYER DP83255
PHYSICAL lAYER CONTROllER

-,....

AT CTl
AT
BUS

...'"
'"

..J

,

u

lBC

DIAG PE

-

'"<><>

TBC

N

TXC

N

COD DP83241
CLOCK
DISTRIBUTION
DEVICE

..J

0

'"

t;;

f:l

'"<>

~
'"..J

'"'"...

Q

<>

<>

D..

>-

'"
..J

..J

'"

x

'"

<>

U

<>

x

t;

2

~

:5
U

III

u

u

5

2

lZ
0

'"

if

2

, 2 ' 2

...
U

~

>=
D..

- RJ-45
PHONE
JACK

CRD DP83231
CLOCK
RECOVERY
DEVICE

0

I+-

75452
DRIVER

...

~

Q

'"

!;;:

Q

...~

C

i
!

l.-

2

ELECTRICAL
(ELECTRONS)

I.2

x
l-

RX OUT EN
FIBER OPTIC
TRANSCEIVER

OPTICAL (PHOTONS)

TO FIBER OPTIC RING

!l

;::!

...

c

~

TlIF111122-4

FIGURE 2. Link Card Block Diagram

3·6

C

2.0 Link Card System Description (Continued)

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N

2.2 AT Interface Block
The function of the AT Interface Block is to interface the
Link Card with the AT host. This block features a full 24-bit
address bus for flexible Link Card memory map placement.
The data bus is B bits wide which is adequate for this demo
platform. Bits B through 15 are not used on the base Link
Card, but they have been tapped to test points on the board.
The test pOints are included in the event that an application
requires a 16-bit data bus. In addition to the address and
data buses, seven AT bus interrupts and the necessary control signals are included. All address and data signal lines
are buffered with independent parity generation supplied for
the data bus.

2.5 CRD Device Block
The Clock Recovery Device has been designed for use in
this FDDI implementation. The device receives serial data
from a Fiber Optic Receiver (FORX) in differential ECl NRZI
4B/5B group code format and outputs resynchronized NRZI
received data and a 125 MHz received clock in differential
ECl format for use by the PLAYER device.
2.6 link Bus Block
The function of the Link Bus is to provide a data path between the Link and MAC Cards that form an FDDI station.
Each connection contains two 10-bit data buses (Indicate
and Request) and station configuration signals. The pinout
of the Link Bus has been designed to allow the user to build
Single Attachment and Dual Attachment/Single MAC configurations. To build one of these configurations, the user
must simply connect the cabling in the manner shown in
Appendix E of the User's Guide.
Every otlier write in the Link Bus is grounded to insure data
integrity. This cabling scheme has been tested for resistance to data corruption induced by crosstalk.

The AT bus block is the 50/e power supply for the link Card.
The address decoding scheme is accomplished with generic array logic devices (GAls). Equations for each of the four
GAL devices are included in Appendix G of the DPB3290EB
FDDI Physical layer Evaluation Board User's Guide.
Beyond these basic functions, the AT Interface offers a
number of modes such as autoconfiguration, base register
area select, and memory map configuration.
2.3 Clock Bus Block
The Clock Bus Block is included in the Link Card design to
provide a physical bus among all Link and MAC Cards that
form a station. The consruction of the bus is a twenty pin
ribbon cable capable of supporting 9 Signals. Each Signal is
surrounded on either side by a ground line to reduce crosstalk.

2.7 PLAYER Device Block
The Physical layer Controller is a part of National Semiconductor's FDDI Chip Set. It implements one Physical layer
entity as defined by the ANSI X3T9.5 PHY standard. The
PLAYER device performs the 4B/5B encoding and decoding, serialization and deserialization of data, repeat filter,
and line state control and detection. It also contains a configuration switch. The PLAYER device supports many types
of station configurations as allowed by the standard.

2.4 COD Device Block
The Clock Distribution Device is a clock generation and distribution device intended for use in FDDI networks. The device provides the complete set of clocks required to convert
byte wide data to serial format for fiber medium transmission and to move byte wide data between the PLAYER and
BMAC devices in various station configurations. 12.5 MHz
and 125 MHz differential ECl clocks are generated for the
conversion of data to serial format and 12.5 MHz and
125 MHz TIL clocks are generated for the byte wide data
transfers.

Although tailored to the FDDI specification, the PLAYER device is also well suited for use in high speed pOint-to-point
communication links over optical fibers and coaxial cable.
2.8 Transceiver Block
The transceiver block consists of two parts: fiber optic receiver and fiber optiC transmitter. The Link Card supports
the following FDDI optical transceiver modules:
AT&T ODl 125 Lightwave Data Links
Sumitomo DM-742 1300nm Data Link
Any Transceiver pair which supports the
AT&T footprint 2.1.B.1 pin format
composed of 2 independent 16·pin DIP (footprints)
See Appendix A of the User's Guide for a detailed footprint
description.

3-7

o
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r-------------------------------------------------------------------------~

2.0 Link Card System Description

(Continued)

N

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~

2.9 Installation

A.1.1 Setup

ON
orr

ON

ADDRESS SET TO OCCOO
ChAP - ENABLED
SEL - DISABLED
hAAP - DISABLED

orr

ON
INTERRUPTS DISABLED
orr

SELECT REr IN rOR COD DEVICE

SELECT INTERNAL VCO rOR COD DEVICE

SELECT 8 ns LBC SKEW rOR COD' DEVICE
PLYRa

13~

+----

SELECT LBC3 rOR PLAYER LBC

II

~
r

L1
L2
L3

SELECT LBCI rOR AT I/r

~~

TL/F/11122-5

3·8

C

."

2.0 Link Card System Description (Continued)

CI)

~
o
o
m

A.1.1 Setup (Continued)

m

NO

CK
NO

SELECT CLOCKED t.40DE
FOR REQUEST DATA
LATCHES

INSURE PROPER PART SEATING AND
PLACEt.4ENT

il

TL/F/11122-6

3·9

m
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3.0 MAC Card
3.1 MAC CARD DESCRIPTION

3.3 MAC CARD SYSTEM DESCRIPTION

The DP83291 EB FDDI MAC Layer Evaluation Board is a
PC-AT compatible board that implements the MAC Layer
functions of the FDDI standard. The Board utilizes the National Semiconductor DP83261 BMACTM device along with
PAL®-based Buffer Management Logic to implement a simple MAC Layer.

The MAC Evaluation Board is designed to perform simple
transmission and reception scenarios. One 8k and 8 Static
RAM is used for Transmission and another is used for Reception and Status. See Figure 3 for a detailed block diagram.
On Transmission, the Transmission Counter is used to address the TlL-RAM where the frames to be transmitted are
written. The Transmit Sequencer controls the sequencing of
frames across the BMAC device's MAC Request Interface.

3.2 MAC CARD FEATURES
The MAC card offers many features on a convenient platform:
• PC-AT compatible full size card

On Reception, the Receive Sequencer controls the sequencing of frames across the BMAC device's MAC indicate interface. Transmit and Receive Status is stored and
multiplexed into the RlL-RAM between frames. The Receive Counter is used to address the RlL-RAM. The Receive Counter is under the control of the Receive Sequencer. The Copy PAL monitors the addressing information
across the BMAC device and determines whether to continue to copy frames. This is signaled to the Receive Sequencer which then adjusts the Receive Counter accordingly.

• Dual ported memory interface-full duplex data path
• Interfaces to link cards for DAS or SAS configurations
• Supported by demonstration software
• Utilizes DP83261 BMAC device
• Full network statistics
• Supports asynchronous and synchronous transmission
classes
• PAL based buffer management

PCJDDRESS

BMAC
COD

TL/F/11122-7

FIGURE 3. MAC Card Block Diagram

3-10

,----------------------------------------------------------------------, c

;g

3.0 MAC Card (Continued)
The Tx-RAM contains either one maximum size frame or
up to 16 frames of 512 bytes or less. The Rx-RAM may be
filled with up to B frames.

o
o
m

1000-3FFF reserved for future use

tD

See Figure 4.

The DPB570A is used as a timer on this board and provides
support for Station Management. Its registers are accessed
via the PC interface and is memory mapped.

MAC Registers
OOOO-OOFF BMAC Device Registers
0100-01FF Board Registers

The PC interface provides access to the Transmit and Receive RAM in addition to the Board Registers and BMAC
device. The Board Registers include a Mode, Function and
Status Register.

BMAC Device Registers
The BMAC Device Registers are mapped directly into the
64k segment of the address space as defined in the BMAC
Device Datasheet.

3.4 ADDRESS MAPPING
PC BUS INTERFACE

MAC Evaluation Board Registers
The board registers are mapped into the 64k segment of the
address space as:
0100 Mode Register
0140 Function Register
01 BO Status Register
01AO Timer Registers
01 CO Board Reset

Board Address Mapping
The Evaluation Board Control Bus is mapped into a 64k
segment within the lowest 1M of the PC address space. The
64k offset is selected (by a jumper) as shown below:
Sel = 0
Sel = 1

(,)
I\)

0400-0FFF reserved for future use

offset is COOOO
offset is 00000

64k Segment Mapping

Note: For MACI add 200lh 10 each address.

The 64k segment reserved for the evaluation board is divided as shown below:
0000-3FFF Used for control registers (See Figure 3)
4000-7FFF reserved
BOOO-9FFF used to access Bk Tx-RAM
AOOO-BFFF shadow to Tx-RAM
COOO-DFFF used to access Bk Rx-RAM
EOOO-FFFF shadow of Rx-RAM
Board Register Address Mapping
The address space used for control registers is divided into
512 byte pages for each PHY or MAC. The MAC is selectable as either MAC 0 or MAC 1.
0000-01 FF MACO
0200-03FF MAC1

BMAC 0 REGISTERS

OOOO-OOFF

BOARD 0 REGISTERS

00FF-01FF

BMAC 1 REGISTERS

0200-02FF

BOARD 1 REGISTERS

0300-03FF

RESERVED

0400-0FFF

RESERVED

1000-3FFF

RESERVED

4000-7FFF

TXRAM

BOOO-9FFF

SHADOW TX RAM

AOOO-BFFF

RXRAM

COOO-DFFF

SHADOW RX RAM

EOOO-FFFF

FIGURE 4. Board Address Map

•
3-11

III
W

g

3.0 MAC Card

~

3.5 MAC Board Installation
The MAC Card requires a full length slot. It can be installed
in either an AT or XT slot. There are several options that
can be programmed via jumpers provided on the MAC Card.
The position of the jumpers on the board are shown in
Figure 5.

~
C

(Continued)
Interrupts

·m
10

• • • • • • • •
• • • • • • • • • i~
• • • • • • • • • •

JUMPER SETTINGS

10

J1: Base Address, MA~ Select, Interrupt and Option Selection
J1 is used to select the Base Address of the MAC Card,
MAC Number. interrupt to be used for the interconnected
MAC and Link Cards and Option Selections on the BMAC
device. The possible settings and factory defaults follow.

• • • • • • • • • •
• • • • • • • •
........
:
• • • • • • • •

.jl
· ..

IRQ4

'

10

Iff·.

• • • • • • • •
• • • • • • • • :;~
• • • • • • • • • •

10

OPTION
SELECT

IRQ3

rt ~

IRQ5

10

• • • • • • • • • •
• • • • • • • •
• • • • • • • • :'.':,

m·.

INTERRUPT SELECT
L._- - - - B A S E AOORESS SELECT
L . . . - - - - - M A C SELECT

TLlF/11122-B

Factory Default Shown

IRQ6

TL/F/11122-9

Factory Default = IRQ4
MAC Select
10

• • • • • •
• • • • • •
• • • • • •

• • •
• • •
• • •

• • • • • •
• • • • • •
• • • • • •

• • •
• • •
• • •

t.tACO

10

MACI

TLlF/11122-10

Factory Default = MACO
J5

TL/F111122-11

FIGURE 5. MAC Card Jumper Locations

3·12

3.0 MAC Card

c"'tI
CD
W

(Continued)

N

Base Address Select

0
0

2

3

4

5

6

8

• • • • • • • • • •
• • • • • • •
• •
• • • • • • •
• •
2

4

m

m

10

5

BOARD BASE=DOOO

10

• •
• • • • • • •
• • • • • • •
• •
• • • • • • • • • •

BOARD BASE=COOO

TL/F/11122-12

Factory Default

=

DODO

Options Selection
7

8

10

• • • •
• • • •
• • • •
7

8

9

10

• • • •
• • • •
• • • •
7

8

9

SAIGT, SAT AND STRIP
OPTIONS CONTROLLED
BY SAT OPTION IN t.40DE
REGISTER

OPTIONS GROUNDED

10

• • • •
• • • •
• • • •

OPTIONS ALWAYS SET HIGH

TL/F/11122-13

Factory Default

=

Options Controlled by SAT Option in Board Mode Register

II
3-13

m

III

!

CO

a.
C

3.0 MAC Card (Continued)
J5: Master Clock Select
J5 programs whether or not this board provides the master
clock for the node. Typically in a DAS or SAS configuration,
only a Single MAC is used. The MAC card will provide the
clock for the entire system. If two MACs are present in the
node, only one of the MAC Boards should provide a clock.
This jumper should only be programmed when configuring Dual MAC systems.
J5: Master Clock Select

J2: Latch Clock Select
J2 is used to select which phase of the LBC to transfer data
between the Link and MAC Cards. This is used to optimize
set up and hold time on data transfers between the BMAC
and PLAYER devices when using a bus. This jumper '
should always be left at the default setting (LBC5).
J2: Latch Clock Select

• •
• •
• •

It'

LBC1
LBC2
3 LBC3'

• •

'2 ,',.",

4 LBC4

:¥:, J:

,f4 ....... "" "'""Y ""'" =

5 LBCS (FACTORY SETTING)
TL/F/11122-14

J3: CDD Device Feedback Select
J3 is used to select which phase of the LBC that the CDD
device will use in its feedback loop This jumper should be
left at the default setting (LBC1).
J3: CDD Device Feedback Select

::, ::i:~::::
2
3
4

5

•
•
•
•

•
•
•
•

LBC1

-+ BOARD SUPPLIES MASTER CLOCK

1.-_ _ _ _

(FACTORY SETTING)
TL/F/11122-17

INSTALLING THE BOARD WITH A LINK CARD
The MAC Card should be Inserted into the PC-AT or XT slot
along with the Link Card. Make sure that the board is inserted into the connectors accurately. The next step Is to connect the cabling between the MAC Card and the Link Card.
Two configurations are pOSSible, Single Attach Station
(SAS) and a Dual Attach Station (DAS).

(FACTORY SETTING)

LBC2
LBC3
LBC4

SAS Configuration
To implement a SAS Configuration a MAC Card and a Link
Card are inserted into two slots on the AT. Two cables are
required. First connect the 20-Pln Clock Cable Into the 20
Pin header on the top of both the Link Card and MAC Card.
Then connect the 50-Pin Cable between the two "A" port
connectors on the Cards. This is the connector farthest
from the back of the AT chassis (see Figure 5). Make sure
the cables are properly engaged with the pins by pressing
down on the top of the cable with your thumbs. Once the
cables have been attached inspect the cards to make sure
that they are straight in the connectors. Pressing in the cables has a tendancy to skew the cards in the slots.

LBCS
TL/F/11122-15

J4: Reference Select
J4 is used to select either the clock on the clock bus or the
local crystal oscillator as a reference. In order to provide
less skew between the Link and the MAC Cards, the CDD
device is locked to the Clock Bus signal. This jumper
should be left at he default setting.
J4 Reference Select

:1
3 •

I'"

:~

'~

1.-_ _ _ _•

""""' ""'"'" (LOO< " .....
(FACTORY SElT1NG)

DAS Configuration
To implement a DAS Configuration an additional Link Card
is required. (Two Link Cards + 1 MAC Card implements a
DAS). Insert a MAC Card and two Link Cards adjacent to
each other as shown in Figure 1. Connect the Cable between the Link Cards as shown, then connect the Clock Bus
Cable and the final Data Cable between the Link and MAC
Cards as shown. Note that the clock cable must attach to all
three boards. Make sure the cables are properly engaged
with the pins on the cards. Also confirm that the cards are
straight in the card cage after connecting the cables.

'"'J

INTERNAL REFERENCE (LOCK TO LOCAL XTAL)
TLlF/11122-16

3-14

~National

~ Semiconductor

OP83200SMT XLNT Manager™
FOOl Station Management
(SMT) Software Support Package
General Description
The XLNT Manager™ Software Package completely implements all required and most optional FOOl SMT Protocol
functions. It comes complete with well documented source
code written in the C programming language and an easy to
use Integration Guide. The source code is modular so that it
can be partitioned over multiple processors and can be
used in all FOOl applications including concentrators, and
dual and single attach stations. The porting guide includes
step by step instructions how to port the software to your
hardware platform. XLNT Manager FOOl SMT Software is a
product of XLNT Design Inc., and is made available to National Semiconductor FOOl customers through a sublicensing agreement. Technical support is provided by National
Semiconductor's fully trained FOOl Applications team.
XLNT Manager FOOl SMT Software combined with National
Semiconductor's FOOl chip set provides a complete FOOl
solution.
The software can easily be integrated into an operating environment using minimal hardware and system support from
the operating environment. The design of the software also
allows for rapid updating to implement changes to the SMT
Standard. Custom Management services can interface with
the SMT software through a standard, well defined, soft-

ware interface. An integration sequence example is included.

Features
• Implements all required and most optional ANSI X3T9.5
Station Management Protocol functions
• Complete portability of the code to most hardware platforms
• Oirect interface with the FOOl Chip Set for compact
and efficient implementation
• Flexible architecture to allow code partitioning for single
and multiple processors
• Standard interface between SMT software and custom
management applications
• Well documented source code (C Language)
• Supports single and dual attach stations and concentrators
• Operating System Independent
• Includes easy-to-use porting guide
• Free updates through 1991

Managemenl
Service.
Process

(MSP)

I
I
I
I

XLNT lIanager

~-------------.,

TLlF111121-1

FIGURE 1. Station Management (SMT) Software Block Diagram

3-15

2.0 Functional Description

Table of Contents

The XLNT Manager Software Package completely imple·
ments all required and most optional FOOl SMT Protocol
Functions. The software package consists of three main
functional blocks as shown in Figure 1. The three main functional blocks are 1) Management Services Process (MSP),
2) the Frame Services Process (FSP) and 3) the Connection
Services Processes (CSP).
.

1.0 OVERVIEW
2.0 FUNCTIONAL DESCRIPTION
3.0 INTEGRATION PROCEDURE
4.0 SUBLICENSE AGREEMENT AND MAINTENANCE

2.1 MANAGEMENT SERVICES PROCESS

5.0 TECHNICAL SUPPORT

The Management Services Process (MSP) processes information in the Management Information Sase (MIS). The
MIS is an information database which is defined by the FOOl
SMT Standard. It includes Information about the status and
performance of a station. The information is collected from
the hardware and other processes and stored in a central
database. The Management Information Sase (MIS) can be
accessed by a Management Application Process like the
Simple Network Management Protocol (SNMP) or by a remote station over the network. The Management Services
Process maintains the MIS and provides a uniform interface
to the Management Application Process, the Frame Services Process (FSP) and the Connection Services Process
(CSP).

1.0 Overview
One of the key areas in the FOOl standardization process
has been Station Management (SMT). The SMT document
provides the guidelines and protocols which can be used to
manage an FOOl network.
To ensure inter.operability in a multi-vendor environment,
some of the protocols described in the SMT document are
mandatory. However, to facilitate the diverse network environments envisioned for FOOl, many of the protocols described are optional. Implementation of the optional protocols' will depend upon the application need.
The basic SMT functions required are:
-

Fault management for high network availability
Reliable error detection and.recovery
Access to networked resources
Fast and reliable connection management procedure

-

Management for multi·vendor networks
Access to individual station information

-

Flexible network configuration

2.2 FRAME SERVICES PROCESS
The Frame Services Process (FSP) implements the framed
based services defined by the FOOl SMT Protocol. The
FOOl SMT Protocol defines several different frame types
which are used to convey status and control information
between stations on the network. For example, Neighbor
Information Frames (NIFs) convey information about the
station to its neighbor. This information can be used in the

Frame Service. Proce•• (FSP)

r--

r--------~~--------~I
Ring Manarment
(RMT

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Optional Optical Bypass
Switch Control

Configuration
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Physical
Layer
Protocol
(PHy)

Physical
Connection
Management
(PCM)

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Media
Access

Control
(MAC)

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DAC

2

2-3

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• testing of slave before insertion into ring
• determining the topology of a concentrator tree before
insertion into the Primary or Secondary ring
• graceful insertion of slave stations or concentrator trees.
There are still several problems associated with each of
these uses. There is no interoperable method for setting
parameters in a slave station and no protocol defined for
testing a slave before inserting it into a ring. Similarly it is not
clear that a roving MAC could find out more about a slave
station than a station self test could.

Naming Conventions
The concentrators are named according to the greatest
number of attachments they can handle (Null, Single or
Dual Attachment Concentrator NAC, SAC, DAC respectively). It is debatable whether this is the best way to name
concentrators since the other parameters are more likely to
vary.

These same problems could be solved in the context of
SMT without resort to a non-standard local path. A slave
could do a self test before requesting insertion into the ring
by causing remote loopback at the concentrator. The station could come into the ring with default parameters that
could also be changed during normal operation. And to
solve the ring mapping problems, an efficient protocol using
well known SMT Group Addresses could be used. There is
still a fair amount of work to be done in the area of inserting
slave stations into a ring. Use of the local path does not
solve these problems and the extra cost and complexity of
adding an additional path is questionable in terms of the
minimal payoff.

Attach Count
This refers to the number of attachments that are available
for use to either the trunk ring or to the concentrator tree. A
concentrator with an attach count of 2 could default to a
concentrator with an attach count of 0 or 1 if those attachments are not connected to anything else.
Paths
This refers to the number of token paths possible in a concentrator. These paths may then be used as part of the

4-13

III

ment services between stations that do not implement the
particular management protocol but do implement SMT and
the actual management application.

MACs
In order for a Concentrator to provide management services
and act as a manageable entity in a network, it should contain at least one MAC. This gives the concentrator the ability
to participate in the SMT frame based protocols and help
isolate, announce and recover from all types of problems.
By having MACs in concentrators, better logical and physical ring maps can be built.
To simplify the relationship between MACs and Paths, it is
easiest to have one MAC per Path. Otherwise it is necessary to multiplex a MAC between the paths. It is difficult to
manage inserted stations on a path that has no MAC.
The data throughput requirements for a MAC implementation are rather minimal, thus low cost management MACs
can easily be added. The cost associated with MACs has
been one of the main points of resistance to standardizing
the presence of at least one MAC in a concentrator. The
incremental cost of adding a MAC compared with the benefits of the added manageability makes it worthwhile, especially in configurations where it amounts to only two extra
chips. (In these configurations all of the memory and processor support is already present.)

2.4 Diagnostic Capabilities
Since a concentrator is one of the most complex nodes in
the network, it should contain extensive diagnostic capabilities. Essential to this is the ability to perform sophisticated
Path Testing and Resource testing of all resources within
the concentrator. The National Semiconductor DP83200
FDDI chipset has numerous diagnostic capabilities built in to
aid in isolating and resolving problems.
2.5 Bridging/Routing Capabilities
The concentrator is also a natural location to add in a MAC
level bridging or routing function between similar or different
media, networks, speeds, and protocols. Because of the
concentrator position within an installation it may offer a natural point to segment the local traffic contained exclusively
in the tree versus traffic that must go outside of the tree.
Such a concentrator would become a multi purpose network
attachment that could be a repeater/bridge/router and
manager where each function is added in as needed on a
common backplane. You could think of it as a ring in a box.

Master Ports
A concentrator will have several Master Ports, each of
which can connect to a Slave or Peer Port. The number of
ports is very implementation specific, and ranges from small
departmental concentrators with 4 M Ports to large multiboard concentrators with up to over 250 ports.

3.0 USING THE NATIONAL DP83200 FOOl CHIPSET
The National Semiconductor DP83200 FDDI chip set was
partitioned for use in all of the Standard FDDI configurations
including Single and Dual Attach Stations with one or two
MACs and in numerous Concentrator configurations.
The DP83251/55 Physical Layer Controller (PLAYER device) implements the Physical Layer (PHY) of FDDI and provides all of the support required by a processor running
SMT. In addition to providing all of the functions required by
an FDDI PHY, the PLAYER device includes support for the
Link Error Monitor Function, the Noise Counter (TN E), Line
State Detection and Generation, and Configuration Management. Two full duplex parallel ports are supported along
with a built in Configuration Switch in order to provide the
flexibility to support all of the station types (SAS, SM-DAS,
DM-DAS) and configurations (THRU, WRAP, ISOLATE).
Concentrator configurations with numerous M Ports and 2
internal paths can be created without any external logic.
The low power dissipation and minimal real estate required
by the PLAYER device makes these chips ideal for concentrator applications.
The DP83231 Clock Recovery Device (CRDTM device) provides a very high performance analog Phased Locked Loop
with very high noise immunity. It can lock to the worst legal
patterns in under 85
and provides a very high dynamic
lock range.
The DP83261 Basic MAC Layer Controller (BMAC device)
implements the Media Access Control Layer (MAC) of FDDI
and provides the support required by a processor running
SMT. In addition to providing all of the functions required by
an FDDI MAC, the BMAC device includes support for RMT,
all of the required and optional frame counters, measurements of the ring/path latency and many tunable parameters.
The DP83265 BMAC System Interface (BSITM device) is
also available for providing a straightforward system memory interface. Tile BSI device also provides several features
that are useful for SMT such as independent channels for
Management Data (SMT /MAC).

2.2 Expandability/Configurability
Another way in which concentrators can be differentiated is
by their packaging. In many instances a low cost fixed configuration makes sense. In other cases an expandable and
configurable concentrator might be attractive.
An attractive fixed configuration might consist of 8 ports that
could be used as an 8 port NAC, a 7 port SAC or a 6 port
DAC.
An attractive flexible configuration might consist of Slave or
Peer Attach boards and Master Port boards. On each Master Port Board there might be 4 or 8 Master Ports.
An example of both a fixed and flexible concentrator are
outlined as examples in Section 4.
Another dimension in which concentrators can be configurable is in the PMD that is supported. FDDI already supports
both a multi-mode and a single mode fiber optic PMD and it
is very likely that additional lower cost PMDs such as Shielded Twisted Pair and shorter distance fiber optic connections
will be supported. By isolating the PMD to a separate board
the PMD could be a configurable option.

"'S

The Concentrator could also serve as a repeater between
different media domains by using different PMDs in different
ports.
2.3 Management Capabilities
Concentrators can also be differentiated by the management capabilities that they provide. The SMT Standard provides many implementation options does not specify how
the services that it provides will be used. The Concentrator
is a convenient location to run Network Management Applications slich as a ring monitor, ring mapper, traffic analyzer,
traffic generator, etc. It also is a logical location to run higher level management agents such as SNMP and/or CMIP.
Management agents serve as proxy agents for manage-

4-14

The DPB3241 Clock Distribution Device (CDDTM device)
generates all of the clocks required by the PLAYER, BMAC
and BSI devices. The CDD device accepts either an external reference or a local crystal. In a concentrator the CDD
device is particularly useful in that all of the clocks required
by the PLAYER device can be generated locally and only
slower speed 12.5 MHz clocks need be distributed. The
CDD device also provides 10 different phased clock outputs.
The chipset also provides numerous diagnostic features.
These include full duplex data paths to allow diagnostic
transmission to self, multiple levels of loopback to isolate
individual chip and interconnect errors and the ability to inject errors and make sure that proper recovery takes place.
In addition, while operational, several levels of self checking
are also employed. These include through parity support,
full duplex data paths so that every frame transmitted can
also be received and the FCS can be checked (the frames
could also be copied), and a full implementation of the FDDI
protocol which is self checking in itself.
The chipset also includes several programmable features
that allow compatibility with the ongoing enhancements to
the ANSI specification.

A and B Ports (A to Sand B to S connections). When there
is a tree to connect into, the concentrator can be configured
to allow M to A and/or M to B connections. In this way, this
concentrator could be used as a Null Attach Concentrator
with 10 leaf connections, a Single Attach Concentrator with
9 leaf connections or a Dual Attach Concentrator with 8 leaf
connections.
With the two path design shown and correct programming
of the configuration switches, the second path could be
used as a local path while bypassing the ring's secondary
path within the concentrator (see Figure 4-4). Note the subtle differences between Figure 4-2 and Figure 4-4. Only the
connection surrounding the Peer Ports is changed. Thus effectively, three paths are present within the concentrator,
although not all of them can be active simultaneously. With
additional external multiplexing, a dedicated third path could
be added to the deSign. The third local path would then
always be available for internal testing for use with a roving
MAC. The benefits of a dedicated third path versus the additional cost are questionable.
The processor controls the BSI, BMAC and PLAYER devices through the common control interface. The control bus
uses a simple asynchronous handshake. The processor can
accomplish all of software oriented portions of SMT (CMT,
RMT, monitoring functions) using this common interface.
The SMT frames are typically generated and processed in a
shared memory.

For more details see the appropriate device datasheets.
4.0 EXAMPLE DESIGNS
The following examples illustrate the simplicity of building
concentrators with the National Semiconductor DPB3200
FDDI chipset. Two example designs are shown representing
two ends of the spectrum. First a Single Board, Single Processor Concentrator is shown, followed by a Multi-Board,
Multi-Processor deSign.

»

z
......
"'......"'
I

Moderate interrupt response time is required to assure compliance with the default requirements (3 ms) of the Physical
Connection Management (T_REACT, PC_REACT, etc.).
Depending on the interrupt latency of the processor, as additional M Ports are added, the processor will eventually
reach its limit in terms of the number of ports that can be
handled Simultaneously. In concentrators with many M
Ports, in order to guarantee the required response times, it
may become necessary to partition tasks among multiple
processors or switch to a processor with a better interrupt
latency (provided that it is not saturated).

4.1 A Single Board Single Processor Concentrator
A simple FDDI concentrator contains a Single processor and
is designed on a single card. The clear advantage of this
type is reduced cost, though forfeiting flexibility and expandability.
Figure 4-1 shows a simple single processor dual attach dual
path deSign. The diagram also suggests a physical layout of
the devices. Even the pinout of the devices in the chipset
were optimized for these applications.

A concentrator requires a moderately high performance
processor with support peripherals such as timers and interrupt control. In many designs it is preferable to use a processor that includes these support peripherals. National
Semiconductor offers a full range of processors that are
appropriate for this application from the HPC family of High
Performance Controllers to the 32000 family of processors.

The concentrator shown has an A Port, B Port, 4 or more M
Ports and 2 MACs. It also has two complete physical paths,
one of which can be used as the Primary Path, and the
other as a Secondary Path or Local Path. The M Ports connect into the Primary or Secondary Path through the PLAYER device's configuration switch as shown in Figure 4-2.

4.2 A Multi-Board Multi-Processor Concentrator
A multi-board concentrator will be used where flexibility and
expand ability is desired over lower cost. For an organization
where adding functionality with time is attractive, the multiboard design is appropriate.

Extensive Path testing can be accomplished as two complete rings can be made operational as shown in Figure 4-3.
For the ring to be operational, all data paths have to be
working properly. The MAC on each ring will go through the
Claim Process and if it receives its own Claim frame successfully, a token will be issued which will continue to circulate. That MAC could then send frames to itself for even
more robust path testing.
The port types are distinguishable by the fiber optiC connector receptacle keying. During the connection establishment
procedures of SMT (Physical Connection ManagementPCM), the connected port types are checked for compatibility. Typically SMT will only allow A to B, B to A and M to S
connections, but SMT can be configured to override this
protection mechanism.

The design is partitioned into three basic cards and a backplane is defined (see Figure 4-5). The three cards include: a
Master Port Card, a Slave Port Card, and a Peer Port Card.
A controller is present on each card to allow very large configurations beyond the constraints of a single processor.
This also decreases the performance requirements of the
main processor by reducing the response time requirements. Having a processor on each card coupled with a
high enough performance serial bus between all cards also
reduces the size and complexity of the backplane to less
than 50 Signal pins all at or below 12.5 MHz.

When there is no trunk ring or concentrator tree to connect
into, SMT can be configured to allow slaves to attach to the

4-15

•

AN-741

TO RING

TO RING

!en

TO SLAVE

TO SLAVE

TO SLAVE

TO SLAVE
TL/F/11120-1

FIGURE 4-1. Single Board Concentrator

PRUN
PIUND
A..JND

---+

PH-.lND

I

PH--'lEO

--.

...J

r---

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SEC_OUT

SEC-.lN

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PM-.lND

B--'lEO

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~

-

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!

I PRLOUT

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~

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B--'lEO

~

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B--'lEO

-

PHY2

B-.lND

MAC2

PM--'lEO

~

PH--'lEO

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PH-.lND

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MACI

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.LIND

~

.LREO

B--'lEO

-,

PM-.lND

-

PHY3

r

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B-.lND

PM--'lEO

TO SLAVE ACTIVE
ON PRIMARY

+--

--.

UNO

r--.LREO

-,

PM-.lND

r---

PHY4

r

I

B_IND

PM--'lEO

TO SLAVE ACTIVE
ON PRIMARY

----

.LREO

B--'lEO

~
/
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PM-.lND

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-

B_IND

PM--'lEO

~

r----+

.LIND

r--.LREQ
PM-.lND

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r---

PHY6

.--------.

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B_IND

+-

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TO SLAVE ACTIVE
ON SECONDARY
TUF/11120-2

FIGURE 4-2. Configuration Switch Insertion

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AN-741

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PM_IND

J

SEC_OUT

SECIN

PM_REQ

PM_IND

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L--.....I

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~IND

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----'-

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~REQ

~

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r---+

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MAC2

PILREQ

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~REQ

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r-~REQ

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PHY3

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I
ISOLATE

LIND

PfoLREQ

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~IND

-

-

PHY4
~REQ

PM_IND

,..------,

I
ISOLATE

B--'ND

PM_REQ

r-----+

B_REQ

~IND

r-~REQ

PM_IND

r--

PHY5

,..------,

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ISOLATE

B_IND

PM_REQ

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r-----+

~REQ

PM_IND

B_REQ

-

PHY6

,..------,

I

B_IND

+-

-

PM_REQ

ISOLATE
TL/F/11120-3

FIGURE 4-3. Internal Path Testing

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TUF/11120-4

FIGURE 4-4. Use of Local Path

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PRIMARY PATH
SECONDARY OR
LOCAL PATH

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INCLUDES:
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MAIN SMT
PROCESSOR

INCLUDES:
2,4 OR MORE
MASTER PORTS
AND LOCAL
SMT
PROCESSOR

•••••

INCLUDES:
2,4 OR MORE
MASTER PORTS
AND LOCAL
SMT
PROCESSOR

TLlF/11120-5

FIGURE 4-5. Concentrator Backplane

memory used for frame transactions (PDUs). The SMT processor handles all lower level SMT tasks (PCM, CFM, etc.).
This main SMT processor also uses a serial controller, to
interface to the other processors in the concentrator across
the serial bus.
National Semiconductor offers a variety of processors and
controllers for this task. The NS32GX320 is a 15 MIP CISC
machine with on-chip cache, timers, interrupt control and
DMA support. The NS32CG160 is a lower performance and
lower cost alternative and is suitable for the SMT function
as is the HPC. The HPC also includes an on-chip 1 MHz
serial interface and an on-chip UART that could be used for
a local RS-232 connection. This connection can be used for
diagnostic purposes, or for connection to a network analyzer console.

Master Port Card
The Master Port card provides several (2, 4, 8 +) M Ports.
The Card shown in Figure 4-6 shows 4 M Ports. These M
Ports are typically connected to the S Port of slave stations.
The slave station could be a single attach workstation or
single attach concentrator at the next lower (or same) level
of the concentrator tree. The M Ports could also be used to
connect Dual Attach Stations and Dual Attach Concentrators where Dual Homing is permitted. In these configurations, to maximize redundancy, the two attachments would
be connected onto two different concentrators.
The M Port card can be designed with multiple PLAYER
devices (PHY layers). The number of ports per card is restricted by the physical limitations of the card such as the
space required by the connectors, optical components and
PLAYER and CRD devices. The processor or microcontroller must service physical SMT tasks within the maximum
times specified in the Standard (T_React, PC react, etc.).
The increase in service latency that accumulates as additional PLAYER devices are connected to the control bus
might also limit the number of Ports that can be supported
on a card for a given processor configuration. SMT tasks
are serviced locally by the processor and reported back to
the main SMT processor located on the slave (or peer) card.

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Backplane Design
The cards plug into a common backplane as shown in Figure 4-4. The backplane provides the interconnection between the various cards and provides a common clock reference and the serial bus. Less than 50 signal pins are necessary, all at or below 12.5 MHz so no sophisticated backplane design is required.
At each slot, two complete token paths are provided. The
10-bit internal National code is sent over the backplane. For
each path, 10 input and 10 output signals are used. For
each slot, 40 signals are present. The output of one slot is
connected to the input of the next slot in order to create the
token paths. The two physical paths are used by SMT as in
the single board design.
A backplane design can use speCial shorting connectors on
a terminator card which would keep the daisy chain paths
connected when no board is plugged into a slot.
In a single processor design, the backplane must also provide a control path for inter-board communications. The
control bus would have to be extended across the backplane in order to provide access to all of the devices. Depending on the capabilities of the main processor, the limitations of its response time, the desired extendability of the
concentrator, this mayor may not be warranted.
The requirements placed on the serial bus/ring are rather
minimal if partitioning of the SMT functions is done well.
Typically, all of PCM would be done locally on each M Port
Card and the simple portions of CMT as well. One very simple protocol to run on a serial bus uses a two or three wire
interface where a main processor polls the other processors
in the system, one at a time. Small (size and cost) RS-485
transceivers such as National's DS75176B or DS3695 can
be used for a simple interface to the backplane.

The National Semiconductor High Performance Microcontroller (HPC) is well suited for this local task. It provides low
interrupt response time, fast 25 MHz operation, embedded
timers for CMT and serial communications capabilities for
implementing a serial bus.
Peer and Slave Port Cards
The Peer and Slave Port Cards provides ports for connection into the larger Ring. With the Peer Port Card, A and B
Ports are provided for connection into either the trunk ring
or a concentrator tree. With the Slave Port Card, an S Port is
provided for connection into a concentrator tree.
Figure 4-7 shows a Peer Port Card design which includes
the A and B Ports, two MACs and the main SMT processor.
The Slave Port Card shown in Figure 4-8 includes one S
Port, one MAC and the main SMT processor. An advantage
of placing the main SMT processor on the same card as the
MAC implementations is to avoid providing support for a full
databus on the backplane or on another potentially expensive special connector. With the DP83200 chipset including
the DP83265 BSI, System Interface device, space efficient
and cost-effective memory interfaces are possible.
The Clock Distribution Device provides all of the clocks required for the DP83200 chipset. Since there is typically only
one Slave or Peer Port in a system, this card drives the
12.5 MHz reference clock onto the backplane. Each card
has a local CDD device which uses the reference to generate the appropriate clocks for the card. Clock distribution in
very large concentrators is discussed separately.
The SMT processor interfaces directly to the local PLAYER,
BMAC and BSI devices across the 8-bit Control Bus. This
bus is used for access to registers, parameters and counters (configuration switch, line state detector, statistic counters, etc.). The SMT processor also interfaces to the local

Concentrator Extensions
The backplane defined could be viewed as links between
stations. The SMT standard only makes assumptions about
the MAC at the exit ports and makes provisions for additional MACs within concentrators. This allows additional cards
to be developed to provide a bridging function either to other rings, or even between paths.

II
4-21

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Another possibility for add in cards for a concentrator are
special network monitoring cards and network testing cards.

Before moving a MAC from one path to the other, it is necessary to remove all frames transmitted by this MAC in order not to create ownerless frames on the path that the
MAC is leaving.

Another extension is the ability to support live insertion of
boards to avoid interruptions. This might even involve intelligent backplanes that could involve sophisticated multiplexing functions.

With the BMAC device, one way to accomplish this is to
enable the Inhibit Token Capture option (Option.ITC) for at
least one ring latency (after this station issues the token, if it
is being held) before changing paths. Before leaving, it is
also helpful to capture the token in order to avoid corrupting
any frames. When placing the MAC on the new ring, it is
necessary to insert while claiming. It is not possible to guarantee graceful entry if a token is not being held on that path.
When the situation exists for this station to scrub the ring of
ownerless frames, several options are provided. The BMAC
device provides a robust stripping mechanism that can be
used without any destructive side effects, namely the STRIP
option where stripping continues until a My_Void frame
comes back around the ring, thus stripping all of the ownerless frames. This occurs automatically after this station wins
Claim before the first token is issued. Similarly, the Inhibit
Repeat option or the ability to block the MAC input from the
PLAYER device for more than one ring latency also provide
this function.

A standard for a concentrator backplane is a likely possibility at some pOint so that many different cards could be developed. This would allow customers to build concentrators
with boards from many different vendors just as standard
buses are used today to create customized computing environments.
This does cause one problem, when does a concentrator
stop being a concentrator?
5.0 SMT NOTES
Several topics relating to implementations of Station Management for a Concentrator are worthy of discussion, many
of these are covered below. Some of these topics relate to
SMT implementations for stations as well.
5.1 Processor Performance Requirements
The most stringent requirement on an implementation of
PCM using the PLAYER device is the Active to Break transition. The Standard requires that this transition takes place
within 3 ms. This implies that within 3 ms after an interrupt is
generated by the PLAYER device, a register is written to
send out Quiet symbols and change the programming of the
configuration switch. By using a low end processor to control several M Ports, the requirements on the main processor are reduced significantly. When bringing links up and
going through the PCM signalling, the timing constraints are
much less severe since there are no requirements for bringing up multiple links simultaneously. It is acceptable to distribute processing with several PLAYER devices controlled
by a single processor.

5.4 Graceful Insertion of Slaves
The graceful insertion (also known as smooth or bumpless
insertion) of slave stations or slave concentrators into a ring
allows stations to be placed Into a ring without disrupting
other stations in the ring. Unlike a ring consisting only of
Dual Attach Stations where the ring must go through at least
the Claim Process on each insertion/deinsertion and possibly cause frames to be corrupted, with concentrators it is
possible to provide the capability to insert and deinsert stations gracefully without any data corruption.
Two methods of varying complexities are shown for graceful
insertion.
With the first method to gracefully insert a slave the following must be accomplished:

5.2 Path Test
A complete path test in a concentrator is invaluable for isolating problems. Especially in large configurations, the ability
to isolate errors, such as marginal connectors or connections, faulty components, etc., is extremely important.
The two complete token paths suggested in both example
designs allows operational rings to be created within concentrators to check connectivity and components. The
DP83200 chipset provides numerous features that aid in
isolating problems down to the chip level. Modes such as 4
loopback paths, error insertion and statistic counters are
just a few of the features included that give true networkl
system testing capability without complex external circuitry
or equipment.

1) make the slave ready to bring the ring operational on the
next received token
2) capture a token on the path on which the slave will be
inserted
3) while holding the token, modify configuration switch of
the M Port to insert the slave
4) hold the token for at least actual ring latency of the new

ring (the inserted slave concentrator might be bigger than
the rest of the ring)
5) issue the token
Step 2 above requires a MAC on the path on which the
slave will be inserted. The slave is inserted into the ring in
step 3 above. The token must be held for a ring latency in
order to guarantee that no frames are corrupted. This could
occur if a slave connected to this concentrator transmitted a
frame to an upstream slave connected to this concentrator.
To avoid a TRT expiration in a downstream station while
holding the token, a pool of synchronous bandwidth could
be allocated and shared by all concentrators on the ring.
This can be done using asynchronous transmission with
THT disabled (one of the service classes provided by the
BMAC device).

By having two complete paths, if a fault exists, the fault can
be isolated precisely by careful programming of the configuration switch (see Figure 4-3). Once it is known which configurations are physically possible, it then becomes necessary to decide which paths should be connected and when
this should be done. The current configuration must always
be valid and up to date (there are still conflicting views on
how this information should be kept in the MIB).
5.3 Moving MACs between Paths
In designs with fewer MACs than paths, it is necessary to
move the MAC between paths. In many cases it is easier to
just put a MAC on each path than to build all of the necessary software interlocks..

4-25

,- r----------------------------------------------------------------------------------------------,
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Depending on the assumptions you can rely on concerning
Concentrators have more stringent packaging demands
.....
than most end attachments due to environmental, modulari:Z a slave station after PCM, Step 1 mayor may not require a

Since all frames that are transmitted, must be stripped before the 7th symbol of the INFO field, the VOIO stripping still
must be used, because it would not be tolerable to strip
based on a bridge number later in the frame.
There are some subtle requirements placed on the transmission of frames in Source Routing Bridges. For example
in some frames, the Most Significant Bit of the SA remains
unchanged for some frames and is forced to zero in others.
The SAT and SAIGT BMAC device input signals can be
driven from the SAT signal on the BSI device. In addition,
the STRIP option also needs to be used to strip frames
forwarded by this station.

ing Information Field is denoted when the most significant
bit of the SA field is set to One. The Routing Information
Field contains a string of 16-bit bridge numbers that the
frame is to be routed to. These 16-bit bridge numbers are
considered aliases of a certain bridge.
Source Routing Bridges fall under the category of explicit
bridges used in the MAC-2 Oraft Standard. In explicit bridges, the addresses that the bridge recognizes are considered
its aliases, and the A Indicator is set for this class of address
matches. (For this reason, in these implementations it is
possible to connect the EA signals of the BMAC and BSI
devices together.)
5_1 Address Filter
The Address filter is much simpler in Source Routing bridges than in transparent bridges. The address filter is required
to parse the Routing Information Field, when present, and
look for this bridge's 16-bit 10 number. If the number is present in the Routing Information Field then the frame is copied
and the control indicators are set appropriately using the EA
and ECIP inputs to the BMAC and BSI devices. The frame is
then forwarded to the next destination in the list.
5.2 Discovery Process
In order for an end station to determine the route to another
end station, the discovery process is necessary. In one variation of the discovery process, a station transmits out several all route frames. Each bridge then adds its bridge number
into the Routing Information Field, until the addressed station has been reached. The addressed station then transmits back a frame according to the "best" route. This route
is then used for future transmission.
5_3 Forwarding
Once the bridge's, bridge number is detected in the Routing
Information Field, the frame can be forwarded to the next
bridge number using the appropriate port (in a multi-port
bridge).

5.4 End to End FCS Checking
Between FOOl and FOOl rings complete End to End FCS
checking is possible. It may also be possible to provide this
type of service between IEEE802.5 and FOOL In any event,
the FCST (FCS Transparency) input is used to control this
option.
6.0 SOURCE ROUTING BRIDGING IMPLICATIONS FOR
END STATIONS
There are a few requirements placed on End Stations that
participate in Source Routing protocols. The end station
maintains the responsibility for discovering the route to its
peers using the All route frame. Once the route has been
discovered, it must be used in all future correspondences as
part of the Routing Information Field.
An End station has no requirements for any ex1ernal address matching logic. End stations can use the ability to
transmit only the MSB of the SA (the Routing Indication
Indicator) from the data stream using SAIGT. When using
the BSI device, the BSI device SAT could be connected to
the BMAC device SAIGT; similarly, SAT could be grounded
and the BSI device STRIP could be connected to the BMAC
device STRIP Signal. The reason the rest of the SA can
come from the Ring Engine is to insure proper stripping
based only on the transmitted SA. This implies that in End
Stations there is no need to use Void stripping.

4-35

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National Semiconductor
Application Note 726

:Z Station Management

< Simplified

MyLe

INTRODUCTION
One of the key areas in the FOOl standardization process
has been the work on Station Management (SMT). The
SMT document provides the guidelines and protocols which
can be used to manage an FOOl network.
To ensure interoperability in a multi-vendor environment,
some of the protocols described in the SMT document are
mandatory. On the other hand, to facilitate the diverse network environments enviSioned for FOOl, many protocols described are optional. Thus the users need to determine the
SMT protocols to be implemented based on their application and configuration requirements.
This application note provides an introduction to FOOl Station Management with the assumption that the reader is familiar with the MAC, PHY, and PMO portions of the FOOl
protocol.
The following topics are included in this paper:
• Station Management Requirements
• Structure of FO,OI Station Management
• Basic SMT frame work to manage an FOOl network
• Optional management protocols based on configurations
and applications
• SMT features provided by the National's OP83200 FOOl
chip set

1.0 SMT Requirements
Before determining the SMT requirements for FOOl, let's
define the major types of users of the network. Based on
the requirements of the users, we can then determine the
functions required by SMT.

ue to operate. And finally, the error should be detected and
removed from the network in a deterministic fashion as
quickly as possible.
Thus, SMT needs to provide extensive and complete Fault
Oetection and Recovery procedures to satisfy the requirement of network's reliability.
• Access to All Authorized Networked Resources
SMT can be used to provide the mechanism for the End-Users to obtain the services available on the network. This
service is useful, especially in a multi-vendor environment,
to guarantee that all stations can receive the same types of
network services regardless of their particular implementations.
An example of the services provided by the FOOl network is
Synchronous Bandwidth Allocation. Using this service, stations can then obtain part of the bandwidth to transmit synchronous data.
• Plug-and-Play
Connection to a network should be made as simple as possible such that the End-Users can plug into the network
without the need for complicated instructions or the possibility of bringing down the network by mistake.
This requirement is especially important in a large network
such as FOOl where a large number of stations can potentially be connected, disconnected, or moved at any given
time.
To satisfy this reqUirement, SMT needs to provide a comprehensive connection management procedure to allow stations to be connected quickly and correctly to the network.

1.1 TYPES OF USERS

Network Administrators

Users can be divided into two main groups: End-Users and
Network Administrators.

The main requirements of the network by Network Administrators are:

The End-Users are mainly interested in the services which
the network provides; thus, SMT operations on the network
should appear transparent to the End-Users.
The second major type of user in an FOOl network is the
Network Administrators. While the End-Users would like to
know as little as possible about the network, the Network
Administrator's goal is to gather as much information about
the network and its attachments as possible; thus SMT
should be designed to allow the Network Administrators to
control the network in a manner that is unobtrusive to the
End-Users.
End-Users

• Ability to Gather Information
One of the key functions of Network Administrators is to
monitor the status of the network and the attached stations.
To achieve this goal, the Network Administrators must have
the capability of requesting and receiving information from
stations on the network.
From the information gathered, the Network Administrators
can then determine the status of the network and invoke
any recovery mechanisms if necessary.
To meet this reqUirement, SMT needs to provide a monitoring procedure where the Network Administrator can gather
information frequently and accurately.

The main requirements of the network by End-Users are:
• Standardized Management Services
• Network Services Reliability
One of the top requirements from the End-Users is the reliability of the network. The network should remain up and
running with the probability of an error occurring as infrequently as possible.
When an error does occur, it should be isolated while the
rest of the network that is free from the error should contin-

In an open network environment where the Network Administrators have to control equipment from a large number of
vendors, there is a need for standardized management
services to allow the Network Administrators to communicate with any station on the network regardless of its implementation.

4-36

l>
The standardized management services also allow the Network Administrators to interpret the information received
from the stations.

• Reliable error detection and recovery management

• Flexible Network Configuration

• Management for multi-vendor networks

Networks can be designed in many configurations depending on many factors such as applications used, building
structure, etc. A network that can be configured in many
different forms gives the Network Administrators the flexibility to design the network based on their own requirements
and constraints.

• Access to individual station information

• Access to networked resources
• Fast and reliable connection management procedure

• Flexible configuration

2.0 SMT Structure
SMT is the layer management service for FOOl networks
which covers the Physical (PHY) and Media Access Control
(MAC) Layers. SMT serves two main purposes in an FOOl
network:
1. To collect information to report to the Management
Agent Process which is responsible for the management
of the entire station (above the PHY and MAC Layers),
and

FOOl Station Management provides the Connection Management procedure which allows the network to be connected into many different configurations (e.g., dual ring of
trees, single tree, dual ring, etc.).
• Ability to Manage the Network Remotely

It is desirable for the Network Administrators to monitor activities on the network or trouble-shoot problems from a
central location. It is also desirable to down-load information
without physically being at the stations.

2. To manage stations on the network by starting and maintaining the PHY and MAC Layers.

To provide these types of services, SMT needs the capabilities to control the remote stations and order them to perform certain operations.

SMT is divided into three main groups: Connection Management, Ring Management, and SMT Frame Services. The
functions of these entities are described followed by a more
detailed discussion on each.

1.2 SMT FUNCTIONS

Figure 1 shows the overall SMT Architectural model.

Based on the types of users on an FOOl network and their
applications as described above, a list of the SMT requirements can be drawn up as follows:
• Fault management for high network availability

SMT

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FIGURE 1. Station Management (SMT) Architectural Model

4-37

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Configuration Control Management
The Configuration Control Management (CCM) controls the
interconnection of PHYs and MACs within a node to configure one of the following node types:
• Single Attach Station (SAS)
• Dual Attach Station (DAS)
• Single Attach Concentrator (SAC)
• Dual Attach Concentrator (DAC)
There is one CCM entity per Port.

2.1 Connection Management
Connection Management (CMT) is the management entity
in SMT that is responsible for the Ports (a Port is a PHY and
PMD pair) and their interconnections to their neighboring
Ports. It Is also responsible for the configuration of MACs
and PHYs within a station.
CMT's functions include the following:
• Establish and initialize physical connections
• Control station configuration
• Detect Physical Layer faults
The CMT entity is further divided into three sub·entities: Entity Coordination Management, Physical Connection Man·
agement, and Configuration Control Management.

2.2 Ring Management
Ring Management (RMn is the entity in SMT that is responsible for the MACs within a station.
RMT's functions include the following:
• Notify station of MAC availability
• Detect logical MAC Layer faults
The RMT entity receives status information from the MAC
and the Configuration Control Management (CCM) entity.
The information is then reported to the higher-level management entity.
There is one RMT entity for each MAC in a Station or Concentrator.
Figure 2 shows the internal structure of the CMT and RMT
entities.

Entity Coordination Management
The Entity Connection Management (ECM) indicates when
the media is available (i.e. when signals can be transmitted
and received). It is also used to coordinate activities of other
entities within CMT and RMT.
There is one ECM entity per Station or Concentrator.
Physical Connection Management
The Physical Connection Management (PCM) initializes the
connection of Ports and manages the Signaling Sequence
between each physical connection.
The PCM uses the Line States available in the PHY to perform the Signaling Sequence.
There is one PCM entity for each Port.

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FIGURE 2. RMT and CMT Entities

4-38

2.3 Frame Services
Frame Services is the management entity in SMT that is
responsible for providing a number of frames that may be
used to gather information and control the stations attached
to the network. These frames are used in SMT protocols
which collect information for higher-level management entities.
Frame Services are used by the Management Agent Process to:

-

ECM performs the Trace function by invoking the
PCM to transmit the appropriate Line States.

• Disconnects the PMD from the network
• A Path Test function is used to test all the components
and paths within a node. Since the test occurs entirely
within a node and cannot be verified, it is considered an
implementation dependent issue and is not specified by
the Standard.
The Path Test is used to ensure that the node will operate
correctly once it joins the ring. It is also used to determine
if the node causes errors on the ring.
For example a Path Test can include the following steps:

• Gather statistics
• Detect, isolate, and resolve network failures
• Tune performance
• Change topology

• Test all accessible data paths within the node
• Perform loopback testing of the PHY as close as possible to the PMD interface

3.0 Basic SMT Framework

• Confirm parameters provided to the MAC: addresses,
timer values, etc.

All entities within SMT, Connection Management, Ring Management, and Frame Services, are operated based upon
the following inputs:

• The MAC recovery process for this node including the
resolution of the Beacon and Claim Processes

• Signals from higher level management
• Internal conditions'triggered by the expiration of timers
• Signals received from other stations on the network
Since SMT is considered as an intelligent entity, the higher
level management does not need to control every level of
operation within SMT. Rather, SMT will perform the necessary procedures and protocols to accomplish a task requested when the ,higher layer management entities set the
appropriate signals (Connect, Disconnect, Reset, etc.).

Physical Connection Management
PCM is initialized by the PC_Start signal from the ECM.
PCM provides the following services:
• Initializes a physical connection. The physical connection
procedure is performed at the PHY Layer as follows:
- Determines that a neighboring PHY exists
-

3.1 CONNECTION MANAGEMENT
CMT controls the Physical Layer (PHY and PMD) and the
Configuraiton Control Element which connects the MACs
and PHYs within a station or concentrator.
The operation of CMT is based upon the requests from SMT
which in turn come from a higher level of management. The
requests used to control CMT are:

Determines that the neighboring PHY has the correct
PC_Type to establish a legal connection between the
two Ports. [In a typical network configuration, there
are two types of legal connections: A to B (Dual Attach Stations on dual rings) and M to S (Single Attach
Station connected to a Concentrator).]

• Runs the Link Confidence Test. The Link Confidence
Test is used to determine if the link quality is adequate for
ring operation. Its aim is to detect major link quality problems, not to determine the exact Link Error Rate.

• Connect Request: this request is used to signal the Physical Layer to connect to or disconnect from the network
(signals Connect and Disconnect).

The Link Confidence Test is performed in the PCM State
Machine before the link is allowed to join the ring. A minimum Link Confidence test requires the transmission of
Idle symbols for a period of 50.0 ms providing that the link
has not had any recent link quality problem. Errors that
occur during the testing period are recorded. If the number of errors recorded exceeds the acceptable error rate,
the test fails. Otherwise, the link is considered to have
passed the Link Confidence test.
The result of the Link Confidence Test is reported to higher level management. If the link fails the test, it will continue to be tested until the test is passed or until higher level
management disconnects the link.
Once the Link Confidence test has been completed successfully, the link is ready to be included in the network.
The PCM then signals the CCM to connect the appropriate MACs and PHYs together within a station.
The Link Error Monitor (LEM) is used to examine the link
error rate of an active link. The LEM function complements the initial Link Confidence test to monitor the link
quality once it has joined the ring.
LEM is performed by SMT using the facilities available in
the PHY.

• Control Request: this request is used to signal the CMT
to perform certain operations or to report status.
CMT communicates with SMT via Status Indication which is
used to report CMT status changes.
Entity Coordination Management
The ECM is initialized when the CMT receives a Connect
Control Request from SMT.
The services provided by the ECM Entity are:
• Connects the PMD to the network when CMT is initialized:
- Allows the Transmitter and Receiver to begin to transmit and to receive.
- Once the Fiber Optic Transmitter and Receiver are
ready, a signal is set to initialize the PCM.
• Starts the Trace process to localize a Stuck Beacon condition based on the Trace_Prop signal from the Ring
Management or Physical Connection Management entity.
- After the ring is stuck in the Beacon state for a period
of time (:20 8.0 seconds), a signal is set to begin the
Trace process.

4-39

Once the Trace function has been completed, it will indicate the result to ECM.

Link Error Events are counted to produce the LEM.-CT
count. A Threshold test is used to compare the current
Link Error Rate with the cutoff and alarm Link Error Rate
thresholds.

• Supports Maintenance.
In the Maintenance state, the PCM can transmit any
sequence of symbols. This feature is useful to ensure
that the PHY Transmitter can transmit all the symbols in
the FDDI Code. It is also used to force the other end of
the connection into a particular state manually without
going through the Connection Sequences.

Once the LER reaches the alarm LER threshold, SMT
reports the status to higher level management. If the LER
is equal to or greater than the cutoff LER thresholds, the
link is automatically removed from the ring and this event
is reported to higher level management.
• Performs the Trace function.
Upon the reception of signal PC_Trace from ECM, PCM
transmits the appropriate Line States required by the
Trace function.
The Trace function provides a recovery mechanism for
Stuck Beacon conditions on the FDDI ring. Whereas PCM
is designed to recover from most physical faults that occur between two nodes, the Trace function is intended to
provide recovery from a Stuck Beacon condition which
cannot be localized to a single link.

Configuration Control Management
The CCM is initialized by the CF---Join signal from the PCM.
The services provided by the CCM Entity are:
• Inserts Single Attachment Station or Concentrator to the
Primary Path.
• Connects the MAC of Dual Attachment Station or Concentrator with a Single MAC to the Primary Path.
In this configuration, all Dual Attach Stations with one
MAC are connected to the Primary Ring. Only Dual Attach
Stations with two MACs can transmit and receive frames
on both the Primary and Secondary Rings.

The Trace function causes all stations and concentrators
in the suspected fault domain to leave the ring and complete a Path test, so that the fault may be localized. The
fault domain is defined as the area between the Beaconing MAC and its nearest upstream neighbor MAC.
The Trace function is performed as follows:

Single Attach Stations are connected to the Primary ring
as the default configuration.

• When a station enters the Beacon State, a timer is reset.
If the station is still in the Beacon state when the timer
expires, a Stuck Beaconing condition has occurred and
the RMT sets the Trace_Prop signal to the ECM to initialize the Trace function.
-

The Trace function starts at the node with the Beaconing MAC and traverses to the nearest upstream
MAC.

-

The ECM controls the configuration information and
sets the PC_Trace signal to the appropriate PCM.
When a PCM receives a PC"":'Trace signal, it tral]sitions to the Trace state to transmit a special line
state that indicates Trace.
The Port at the other end of the link receives the
"Trace" Line State and will set the Trace_Prop flag
to indicate that the Trace function is to be propagated upstream.

-

-

-

When the Trace Line State arrives at a Port that is
connected to the input of a MAC, the Trace has
been completed.
The node with the MAC that receives the Trace removes itself from the ring from Path Test.
The removal of this node causes the node downstream from it to remove itself also.
Thus, all nodes in the Trace domain will eventually
remove themselves from the ring to perform Path
Tests. This process should take less than the
Trace_Max timer value (7 seconds).

• Performs the Scrub function.
The Scrub function is used to remove PDUs sourced by
MACs that no longer form part of the same token path.
These MACs may have been removed from the token
path internally within its node or due to a network topology change. It is controlled by the CEM entity.
The Scrub function removes left over PDUs after a reconfiguration to ensure that aU PDUs on the ring have been
created since the last reconfiguration.
The Scrub function may be performed by using one of
several mechanisms listed below.
-

Transmit Beacon or Claim frames for a sufficient time
while the input to the MAC is blocked (stripping old
frames while transmitting Beacon or Claim frames)

-

Transmit Idle symbols for a sufficient time while discarding input stream received at the PHY. This method may be used for a node that does not have a MAC
after reconfiguration.

-

Frames can also be stripped by the node that is performing the Scrub function. '

3.2 RING MANAGEMENT
RMT manages the basic information and condition of each
MAC. The operation of RMT is based upon the control request from SMT, which in turn comes from the higher level
of management. This request is used to signal RMT to reset, to change the basic information in the MAC, or to report
its status. RMT is also responsible for initiating fault recovery actions to recover the ring.

If the Trace function has not been completed within the
Trace_Max time, the process has failed and manual intervention is required.

4-40

Based on the Upstream Neighbor Address provided in NIF
frames, a station can then build a ring map of the stations'
locations and their connections to other stations.
There are three types of NIFs: Announcement, Request,
and Response.

RMT communicates with SMT via the Status Indication
which is used to report its status changes.
Services provided by RMT are:
• Identification of a Stuck Beacon condition
If the ring remains in the Beaconing state for a long time
(~ B.O seconds), the Stuck Beacon condition has occurred. RMT will report this error condition to higher level
management as well as starting a new error recovery
mechanism.
RMT uses a timer (T_Stuck) to keep track of the Struck
Beacon condition.

• Announcement
A NIF Announcement frame is broadcast to the entire ring.
A station can choose to transmit a NIF Announcement or
NIF Request. If a NIF Announcement is to be transmitted, it
will be sent every 30 seconds when the ring is operational
and under zero load conditions.

• Initiation of the Trace function
Once the ring has been identified to be in the Stuck Beacon condition, RMT starts the Trace function by setting
the Trace_Prop signal to ECM.

• Request
A NIF Request is sent to a station, a group of stations, or
the entire ring. The NIF Request announces the station's
information while requesting that the corresponding station(s) respond with a NIF Response.
If an NIF Request is to be transmitted, it will be sent every
30 seconds when the ring is operational, under zero load
conditions.

• Notification of MAC availability
After the CCM sets the RM_Join signal to indicate that
the MAC is connected to the appropriate PHY in a station
(or concentrator), the RMT can then set the
MACJvaiiable signal to higher level management to indicate that the MAC is ready to transmit and receive data.

• Response
A NIF Response is sent in response to a NIF Request.
Upon receiving a NIF Request, a station is required to send
a NIF Response within 30 seconds if the ring is operational,
under zero load conditions.
In addition to the Upstream Neighbor Address, the NIF Response frame also provides the Downstream Neighbor Address, and the mechanism to detect Duplicate Addresses.

• Detection of Duplicate Addresses
By observing the order in which Beacon and Claim
frames are received at the MAC, RMT can detect Duplicate Addresses which can prevent the ring from becoming operational.
Upon detecting this condition, RMT will notify higher level
management of the condition. It will also take actions to
resolve the Duplicate Address problem.

Resource Allocation Frame
A Resource Allocation Frame (RAF) is defined to support a
variety of network policies for allocation of resources. At this
point, only the Synchronous Bandwidth is identified as the
only resource supported by the Resource Allocation
Frames. However, the protocol can also be used to support
other types of resource allocation which have yet to be
specified in the Standard.

• Resolution of Duplicate Address Problem
One of three possible solutions can be taken by RMT to
eliminate the Duplicate Address problem:
1. Change the MAC's address to a unique universal address
2. Change the bidding time to guarantee that this station
will lose the Claim Process

Request Denied Frame
A Request Denied Frame (RDF) is used to respond to optional frames that the station does not support. It is also
used to respond to an SMT frame with a Version ID that this
station does not support.

3. Remove the station from the ring
3.3 FRAME SERVICES
A number of frames are specified as SMT frames. These
frames are used to gather information and control the operation of the stations on the network. There are four types of
mandatory SMT frames:

Status Report Frame
The Status Report Frame (SRF) is used to periodically announce the station's status which may be of interest to the
Network Administrator.

• Neighbor Information Frame
• Resource Allocation Frame
• Request Denied Frame

Two types of information are included in the SRF: Conditions and Events. Conditions include the station state which
may be of interest to a network manager as long as the
condition remains asserted. Events are instantaneous occurrences which are of interest to a network manager.

• Status Report Frame
Neighbor Information Frame
A Neighbor Information Frame (NIF) is used by a station for
periodic announcement of its basic operating information.

4-41

~r---------------------------------------------------------~

z~
cc

Although these connections are considered legal, higher
level management needs to be notified so that the link can
then be rejected.

4.0 Optional Protocols
Aside from the mandatory functions listed in Section 2.0,
FDDI SMT also provides many optional protocols that can
be implemented in addition to the mandatory ones.

• LInk Confidence Test
Aside from the minimum Link Confidence Test described in
Section 3.4, other types of Link Confidence tests can be
performed.
The two PHYs of the link need to agree beforehand which
type of Link Confidence test is to be carried out. This information is exchanged via a bit in the PCM Signaling Sequence.

4.1 CONNECTION MANAGEMENT
Entity Coordination Management
ECM has two optional features, the Optical Bypass Switch
Control and Hold Policy.
• Optical Bypass Option
The Optical Bypass is used to allow a Dual Attachment Station or Concentrator to be inserted and deinserted from a
dual ring without disrupting the operation of the ring.

Other Link Confidence tests to be considered include the
following:
• Transmitting PDUs and counting link errors. Errors are
detected and counted at the PHY.

If the Optical Bypass Option is available, the ECM allows for
the switching time of the optical bypass switch during the
Insertion process. It also allows time for the optical bypass
switch to deinsert during the Deinsertion Process.,

This Link Confidence test requires at least one MAC connected to one of the two PHYs.
• Transmitting PDUs and counting Frame Check Sequence
errors. Errors are detected and counted as frame errors
at the MAC.
This Link Confidence 'test requires at least one MAC connected to one of the two PHYs.

• Hold Policy Option
When the Hold Policy is invoked, it prevents the dual rings
from wrapping when a fault occurs on one of the two rings.
The Hold Policy may be used in Dual Attachment Stations
and Concentrators.

• Looping back symbols received from the other end of a
connection and counting link errors on reception. Errors
are detected and counted at the MAC.
This Link Confidence test is performed at the PHY layer.
The length of the Link Confidence Test can be:

The Hold Policy is useful in preventing the disruption of a
ring when an error occurs on the other ring of the dual rings
(disruption occurs when the ring attempts to wrap).
Physical Connection Management
PCM has the following two optional Features

• Short (50.0 ms)
• Medium (500.0 ms)

• Physical Connection
In a normal dual ring of trees structure, there are two types
of physical connections between two ports: A-B (A port to
B port) and M-S (Master port to Slave port). In addition to
these two connections, other connections can also be acceptable as legal:

• Long (5.0 sec.)
• Extended (rio maximum time specified)
The length of the Link Confidence test is indicated by two
bits of the PCM Signaling Sequence.

• A port to A port (A-A)
• B port to B port (B-B)
• A port to Master port (A-M)
• B port to Master port (B-M)
• Slave port to Slave port (S-S)
The A-A and B-B connections may be used when two Dual
Attachment Stations are connected together to form a ringlet (a dual ring with two stations).
The A-M and 8-M connections may be used when a Dual
Attachment Station is used as two Single Attachment Station. In this case, the station can only be connected to the
ring via a Concentrator. This scenario is called Dual-Homing.

Configuration Control Management
Aside from the Primary Path, there are two other optional
paths available in CCM: Secondary and Local.
• A PHY or a MAC can be connected to the Local Path.
While connected to the Local Path, these entities are removed from the ring and can be used to perform local
testing.
• A Single Attachment Station can initially be connected to
the Secondary Path. Single Attach Stations can then
choose to transmit and receive frames on either the Primary or Secondary ring depending upon the initial connection.
• The MAC of a Dual Attachment Station with a Single
MAC can also optionally be connected to the Secondary
Path. Stations with one MAC can then choose to transmit
and receive frames on either the Primary or Secondary
ring.

The S-S connection may be used to connect two Single
Attachment Stations together to form a link. The two stations thus form a single ring.

4-42

r----------------------------------------------------------------,~

4.2 FRAME SERVICES
The following SMT frames are provided by the Frame Servo
ices to gather status and control the nodes on the ring:
o Station Information Frames

The structure of the ESF is defined by the owner of the
Extended_Type.

o Echo Frames
o Extended Service Frames
o

Status Report Frames

o Parameter Management Frames

Station Information Frame (SIF)
Station Information Frames (SIFs) are used to request and
provide, in response, a station's configuration and operating
information. There are two classes of SIFs: Configuration
and Operation.
o

Extended Service Frame
The Extended Service Frame (ESF) can be used to test new
SMT services that are intended for inclusion in later versions of the FDDI SMT document.

Configuration SIF

Parameter Management Frames
The Parameter Management Frames (PMF) are used to get,
change, add or remove parameters in a node. There are 4
classes of PMFs: PMF Get, PMF Change, PMF Add, and
PMF Remove.
There are two types of frames for each class: Request and
Response.
PMFs are transmitted with an optional authorization code to
provide a type of security check.

A station can request a station, a group of stations, or all
stations on the ring to respond with its (their) configuration
information using the SIF Configuration Request. The transmission of these Request frames is optional.
A station is required to respond to SIF Configuration Request frames with a SIF Configuration Response frame within 30 seconds of receiving a Request frame, under zero load
conditions. Stations can also deny the request by sending
back a Request Denied Frame.

PMFGet
A station can issue a PMF Get Request Frame to query the
value of one or a group of attributes in the Management
Information Base (MIB) of an individual, group, or all stations.
The receiving station can respond with the current value of
the requested attributes. If the protocol is not supported, a
station can transmit a Request Denied Frame in return.

The SIF Configuration Response provides the configuration
structure of the node by describing the connections of the
PHYs and MACs within the node. It is used to build the full
ring map (both logical and physical).

PMFChange
A station can issue a PMF Change Request Frame to
change the value of a single attribute in the Management
Information Base of an individual, group, or all stations.
The receiving station can act to change the requested attribute. It can then respond with a PMF Change Response. A
station could also transmit a Request Denied Frame in return.

o Operation SIF

A station can request a station, a group of stations, or all
stations on the ring to respond with its (their) operation information using the SIF Operation Request. The transmission of these Request frames is optional.
A station is required to respond to SIF Operation Request
frames with a SIF Operation Response frame within 30 seconds of receiving a Request frame, under zero load conditions.
The SIF Operation Response provides the operating parameters in a node; information such as timer values, counter
values, etc. It is used to detect faults by monitoring the station's status and counter values.
Echo Frames
A station can request another station on the ring to re-transmit a test pattern using the Echo Request Frame (ECF).
This test pattern is stored in the Information field of the
Echo Request Frame.
Upon receiving the Echo Request Frame, the recipient
builds an Echo Response Frame and sends it to the Request Frame's Source Address.
The Response Frame is required to be transmitted within 30
seconds after receiving the Request frame if the ring is operational and there is zero load. The recipient can also send
a Request Denied Frame instead of the Response Frame.
Echo Frames can be used to test for data-sensitive network
failures by placing the suspect data pattern in the Echo Information field. It can also confirm that a station's Port,
MAC, and SMT are partially operational.

PMFAdd
A station can issue a PMF Add Request Frame to add a
value of a single attribute in the Management Information
Base of an individual, group, or all stations.
The receiving station can act to add the requested value. It
can then respond with a PMF Add Response. A station
could also transmit a Request Denied Frame in return.
PMF Remove
A station can issue a PMF Remove Request Frame to remove the value of a single attribute in the Management Information Base of an individual, a group, or all stations.
The receiving station can act to remove the requested value. It can then respond with a PMF Remove Response. The
station could transmit a Request Denied Frame in return
instead.

5.0 National's FDDI Chip Set
National's DP83200 FDDI Chip Set has been designed to
provide maximum support to the Station Management functions. Both the PLAYER and BMAC devices have separate
management interfaces via the Control Bus. Furthermore,
each chip has many registers on-board to provide the information required by the different SMT entities.
5.1 PLAYER DEVICE
Connection Management
The Connection Management Entities (ECM, PCM, and
CCM) can control the operation of the PMD and PHY using
the registers available on the PLAYER Device.

4-43

ZI

......

N

en

• Entity Coordination Management
The user can control the operation of the PMD by setting or
resetting bits 4 to 7 of the MODE Register.
• Physical Connection Management
The PCM Signaling Sequence can be implemented using
the Current Transmit State Register and Current Receive
State Register in the PLAYER device.
Line States can be transmitted by setting the appropriate
bits in the Current Transmit State Register. Line States received can be monitored observing the Current Receive
State Register.
Furthermore, a historical record of the Line States received
is kept in the Receive Condition Registers. This information
is useful for keeping track of the Signaling Sequence.
The Noise Threshold and Noise Prescale Threshold Registers are used to ensure that the noise conditions do not
persist beyond the maximum tolerated level.
• Configuration Control Management
Using the Configuration Register, the CCM can control the
connection of the PHYs and MACs in a node. Each PLAYER Device can be connected to the Primary Path, Secondary Path, and Local Path. In addition, it can also be connected to the PHY Invalid Bus where the PLAYER Device can
continuously transmit PHY Invalid to the ring or indicate
PHY Invalid to the entity it is connected to internally within
the node (I.e., a BMAC Device or another PLAYER Device).
The PLAYER Device can be configured via the Configuration Register without external logic.
Link Error Monitor
SMT can use the following registers to perform the Link
Error Monitor functions once the PLAYER Device is connected to the ring:
• Current Noise Count Register
• Current Noise Prescale Count Register
• Link Error Threshold Register
These registers enable the user to implement different
methods of monitoring link errors according to their requirements.
Loopback
The PLAYER Device can be programmed to perform Internal or External Loopback. These Loopback operations are
useful during Path Testing.
The Internal Loopback mode can be used to test the functionality of the PLAYER Device or to test the data path between the PLAYER and BMAC Devices.
The External Loopback mode can be used to test the functionality of the PLAYER Device and to test the data paths
between the PLAYER Device, Clock Recovery Device, and
BMAC Device. This mode is especially useful when the Path
Test requires testing as close to the PMD as possible.
5.2 BMAC Device
The BMAC Device provides extensive ring and station statistics via the on-board Timer and Counter Registers. Furthermore, it can internally generate Claim and Beacon
frames that are used in the FDDI MAC Protocol to detect
errors.

Timers and Counters
Information can be provided to RMT and other SMT entities
to represent the operating status of the node using the following Counters and Timers:
•
•
•
•
•

Late Count Counter
Frame Received Counter
Error Isolated Counter
Lost Frame Counter
Frame Copied Counter

• Frame Not Copied Counter
• Frame Transmitted Counter
• Token Received Counter
• Ring Latency Counter
• Negotiated Target Rotation Timer
• Maximum Token Rotation Timer
• Valid Transmission Timer
• Asynchronous Priority Threshold
The information provided can then be transmitted to other
stations on the ring in the Station Information Operation Response Frame and Status Report Frame.
Loopback
The BMAC Device can be programmed to perform loopback
testing.
There are three Self-Test Paths:
• Internal to the BMAC Device
• Through the PLAYER Device(s)
• Through the CRD Device
These paths allow the user to perform Path Tests on the
BMAC, PLAYER, and CRD Devices.
Stripping Protocol
A special stripping protocol can be invoked by asserting the
STRIP signal (pin 13). The stripping protocol starts with the
transmission of two My_Void frames at the end of a current
service opportunity. The stripping will continue until a
My_Void frame returns. The stripping protocol can be invoked when the initial token is issued after a successful
Claim to remove all fragments and ownerless frames from
the ring as required by the Scrub function of the Configuration Control Management entity.
Inhibit Recovery
By setting bit 3 of the Option Register, the MAC can be
prevented from entering the Claim state.
This option is useful in allowing the ring to recover from the
Duplicate Address scenario where two stations with the
same address also have the winning Claim frames. By prohibiting one station to enter the Claim state, the other station can then win the Claim process thus allowing the ring to
become operational.
Claim and Beacon Frames
The BMAC Device reports the reception of a Claim or Beacon frame by setting the appropriate bit in the Ring Event
Latch Registers.
By keeping track of the received Claim and Beacon frames,
the user can then determine if the Error Recovery process
(Claim or Beacon) has succeeded or failed.

4-44

Duplicate Address Detection
Upon the detection of a Duplicate Address, the BMAC Device reports the incident by setting the appropriate bit in the
Ring Event Latch Registers.

Duplicate Token Detection
Upon the detection of a Duplicate Token, the BMAC Device
reports the incident by setting the appropriate bit in the Token and Timer Event Latch Register.

6.0 Summary
The Station Management (SMT) facilities, an essential part
of an FDDI network, provide a rich set of tools to manage an
FDDI network. As a summary, the Connection Management
services of SMT manage the configuration of the station
and the link between the station's Ports and their neighboring Ports; the Ring Management facilities provide control of

the MACs of a station in the FDDI rings; the Frame Services
provide a tool to manage the complete FDDI network, the
services are the most flexible and extensive part of SMT.
The implementation of Station Management software can
be rather complicated without adequate support from the
hardware. As a result, the National Semiconductor Corporation DP83200 FDDI Chip Set integrated many essential
functions on the chip set and provides maximum support to
FDDI Station Management functions. The PLAYER Device
and the BMAC Device support the Connection Management
services and the Ring Management service respectively.
The BSI Device provides separate Station Management
channel and data frame channels for the maximum support
of the SMT Frame Services. The invaluable Station Management features in the DP83200 Chip Set can shorten the
Station Management software development cycle and provide higher reliability of the FDDI network.

•
4-45

I

~

,------------------------------------------------------------------------,

~ A Guide to the
cc Implementation

National Semiconductor
Application Note 727
My Le, Michael Yip

z

of Physical Connection
Management .
1.0 Introduction
The FDDI Station Management (SMn standard provides
the necessary control of an FDDI station (node) so that the
node may work cooperatively as a part of an FDDI network.
To effectively implement the functions required, SMT is divided into three entities, namely the Connection Management entity (CMn, the Ring Management entity (RMT) and
also the Frame Based Services. The Connection Management is further divided into three entities, the Physical Connection Management (PCM), Configuration Element Management (CEM), and Entity Coordination Management
(ECM).
The Physical Connection Management is an entity within
Connection Management whose functions include:
• Initialization of the connection of neighboring ports pair
where each port is comprised of one PMD entity and one
PHYentity.
• Enforcement of port connection policies and withholding
of unacceptable connections
• Testing of link confidence and monitoring of link quality
between neighboring ports
• Detection of physical connection level faults between two
ports and invocation of path test
• Support of maintenance line state
• Participate in the Trace action
For a general description of SMT, please consult the application note entitled "SMT Simplified", AN-726.
In this document, the operation of the Physical Connection
Management entity is described along with a guide to the
implementation of the PCM using the PLAYERTM device. In
addition, one implementation of the Link Error Monitor using
the PLAYER device is also discussed. For a more detailed
description of PCM and other SMT entities, please consult
the ANSI FDDI Station Management Standard.

2.0 PCM Functions Overview
Many instances of PCM can exist on a FDDI node and each
instance of PCM controls one port in a node. For example,
two separate instances of PCM exist in a Dual Attached
Station (DAS) and only one instance of PCM exists in a
Single Attached Station (SAS). Each PCM communicates
with the ECM and CEM entities and directly controls the
PHY layer device of a port.
One of the most important functions of PCM is to establish a
connection between two ports. The connection process is
achieved through a lock-step handshaking procedure. The
handshaking procedure controlled by PCM is divided into
three stages:
• Initialization sequence
• Signaling sequence
• Join sequence

The initialization sequence is used to indicate the beginning
of the PCM handshaking process. It forces the neighboring
PCM into a known state so that the two PCM state machines can run in a lock-step fashion.
Following the initialization sequence is the signaling sequence. The signaling sequence communicates information
about the port and the node with the neighboring port. A
Link Confidence Test (LCn is also conducted during the
signaling sequence to test the link quality between the two
ports. If the link quality is not acceptable or the type of connection is not supported by the nodes then the connection
will be withheld.
If the connection is not withheld during the signaling sequence, the PCM state machine can move onto the join
sequence and establish the connection between the two
neighboring ports.
In addition to establishing the connection, PCM also supports the Maintenance function and performs the Trace
function. During the Maintenance function, PCM forces the
PHY layer device to transmit a specified line state continuously. The Maintenance function allows SMT to force the
PCM of the neighbOring port into a known state manually
and line faults may be traced when both end nodes are in
known states and do not change state due to line noise.
The operation of PCM can be implemented by a state machine. The state machine is comprised of ten states: Off,
Break, Trace, Connect, Next, Signal, Join, Verify, Active and
Maintenance. The next section of this document describes
the PCM State Machine.

3.0 Detailed PCM Description
3.1 CONNECTION SEQUENCE
The connection sequence starts with the reception of the
PC_Start signal from the Entity Coordination Management.
PC_Start indicates that the physical media is available for
communication. The PC_Start signal causes the PCM state
machine to enter the Break state which is the beginning of
the initialization sequence.
In each sequence the two PCM state machines exchange a
sequence of line states. The PCM state machine sends the
line state to its neighboring PCM by directing the PHY layer
devices to transmit a continuous stream of line state symbols. This line state is transmitted for a duration of time to
ensure that the neighboring PCM receives the information.
While transmitting, the PCM state machine also expects to
receive a particular line state from the neighboring PCM. If
things go as planned, the connection progresses through
the three sequences and PCM Signals the Configuration Element Management entity to include the connection into the
token path.

4-46

:I>
The remainder of this section describes the detail operation
of each sequence in the connection process.

Join Sequence
The final stage of the connection sequence is the join sequence. The join sequence is comprised of three states running in sequence. The three states are Join state, Verify
state and finally the Active stage. The join sequence is a
unique sequence of transmitted symbol streams received as
line states (HLS-MLS-ILS) that leads to an active connection. At the end of the join sequence, the PCM state machine signals the CEM entity and CEM will incorporate the
connection into the token path.

Initialization Sequence
The Break state and the Connect state are used in the initialization sequence to start the connection.
The Break state is the entry point in the start of a PCM
connection. In the Break state, a continuous stream of Quiet
Symbols is transmitted to force the other end of the connection to break any existing connection and restart the connection sequence. The Break state is entered upon the reception of the PC_Start signal from ECM or other PCM
states when external events force a reinitialization of the
connection. Reinitialization is required if the Link Confidence Test fails, the expected line state is not received, a
noise condition occurs for a period of time, or the neighboring port is forced to break the connection.

....z•
~

The PCM state machine enters the Join state when the signaling sequence finishes exchanging the ten bits of information. After the tenth bit is transmitted, the PCM state machine enters the Next state. The reception of Idle line state
in the Next state causes the PCM state machine to transition to the Join state. In the Join state, a continuous
stream of Halt symbols is transmitted.

When Quiet line state or Halt line state is entered during
Break state, the connection has been initialized successfully
in the Break state and the PCM state machine can transition
to the Connect state. The Connect state is used to synchronize the two ends of the connection to begin the signaling
sequence. In the Connect state, a continuous stream of Halt
symbols is transmitted for a sufficient amount of time for
clock acquisition by the receiving PHY.

The reception of Halt line state in the Join state causes the
PCM state machine to transition to the Verify state. In the
Verify state, a continuous stream of Halt-Quiet (Master)
symbol pairs is transmitted.
The last state of the connection sequence is the Active
state. The reception of Master line state in the Verify state
causes the PCM state machine to transition to the Active
state. In the Active state, a continuous stream of Idle symbols is transmitted. Upon the reception of Idle line state in
the Active state, the PCM state machine directs the PHY
device into the Active Transmit Mode, which transmits the
PDUs from the PHY device's request port.

Signaling Sequence
The second stage of the connection sequence is the signaling sequence. The Next state and the Signal state is used in
the signaling sequence to exchange port information with
the neighboring PCM. Link Confidence Test and/or MAC
Loop Back Test are also performed during the signaling sequence.

Many timers are used to ensure the connection sequence
proceeds in lock-step fashion on the two ports of the link.
The timers used in PCM are listed in Section 5.3 together
with a brief explanation of each timer. The state diagram of
the PCM state machine and a list of PCM states are also
presented in Section 5.1.

The PHY line states are used to signal bit information and
provide handshaking during the signaling. During the signaling sequence, three line states are used. The Idle line state
is used as a bit delimiter, the Halt line state is used to represent a logical one (set) and the Master line state is used to
represent a logical zero (clear). If Quiet line state is entered
during any part of the signaling sequence, the PCM state
machine should make a transition to the Break state and
restart the connection sequence again. During the signaling
sequence, ten bits of information are exchanged with the
neighboring PCM. Section 5.2 has a list of the format of the
10 bits of information.

3.2 MAINTENANCE FUNCTION
The Maintenance state is used to perform the Maintenance
Function. In the Maintenance state, the symbol stream
specified by higher level management agent shall be forced.
During the Maintenance state, the PCM state machine is
insensitive to the received line state.
The Maintenance state is useful to ensure that the PHY and
PMD devices can transmit all the symbols specified in the
FDDI standard. The Maintenance state is also used to force
the other end of the connection to a particular state manually (without going through the Connection Sequence).

The Initialization sequence leaves the PCM state machine in
the Connect state while the PHY Port is transmitting Halt
symbols. The reception of Halt line state in the Connect
state causes the PCM state machine to transition to the
Next state. The signaling sequence starts upon the first
transition to the Next state. In the Next state, a continuous
stream of Idle symbols is transmitted. The Next state is
used to separate the bit Signaling performed in the Signal
state.

3.3 TRACE SUPPORT
Trace support is needed to localize a Stuck Beacon condition. The Trace function is used to recover from the Stuck
Beacon condition by propagating the Trace signal along the
ring, causing all the stations and concentrators in the suspected fault domain to leave the ring and perform a Path
Test. In the Trace state, a continuous stream of Halt-Quiet
(Master) symbol pairs is transmitted to the upstream station.

The reception of Idle line state in the Next state causes the
PCM state machine to transition to the Signal state. In the
Signal state, a continuous stream of Halt symbols or HaltQuiet (Master) symbol pairs are transmitted. Therefore one
bit of information is transferred each time when the Signal
state is entered. The reception of Halt line state or Master
line state in the Signal state will cause the PCM state machine to transition to the Next state again. The Next state
and Signal state cycle repeats ten times to exchange all ten
bits of information in the Signaling sequence.

Two possible sequences of events can cause the PCM
state machine to enter the Trace state. In the first case, the
reception of Master (or Trace) line state in the Active state
causes the PCM state machine to send the Trace_Prop
signal to ECM. ECM will direct the appropriate PCM state
machine to transition to the Trace state by sending the
PC_Trace signal to that PCM. Upon the reception of the
PC_Trace Signal, a continuous stream of Halt-Quiet (Master) symbol pairs is transmitted.

4-47

•

~ r-------------------------------------------------------------------------------~

C'I

I';Z
011(

The LCT can be performed using one of the following methods:
• Transmit Idle symbols and count link errors. The error
measurement is taken from the PHY device.
• Transmit valid PDUs and count link errors. Again, the error
measurement is taken from the PHY layer device.
• Transmit valid PDUs and count Frame Check Sequence
(FCS) errors from the MAC frames. In this method, the
MAC layer device is used to source the PDUs and also
take error measurements.
• The PHY will reiransmit what is received and the transmitter will check for link errors. This method requires at least
one MAC device connected to the link to send PDUs. The
error measurement is taken from the PHY layer device.
Because multiple levels of the LCT can be performed, a
minimum capability of transmitting Idle symbols and counting link errors is required for each port.

The second situation that causes PCM state machine to
enter the Trace state is a bit more involved. When the Ring
Management entity detects a Stuck Beacon condition, RMT
sends the TraceJrop signal to the ECM. Like the first
case, the ECM entity will direct the appropriated PCM state
machine to transition to the Trace state.
3.4 Link Confidence Test
The Link Confidence Test (LCT) tests the link quality before
the link is inserted into the token path. If the link quality is
not adequate for ring operation then LCT will fail. Failure of
LCT will cause PCM to return to the Break state and the
connection is reinitialized. As a result, the LCT and the
whole connection sequence will be repeated until the LCT is
passed. The LCT is intended to detect major link problems
and not to determine the exact Link Error Rate.
The Link Confidence Test is performed after bit 6 is transmitted in the Signaling sequence. During the duration of the
test, either Idle symbols or valid PDUs are transmitted. The
reception of Master line state signifies the successful completion of the LCT, while the reception of Halt line state
signifies the failure of the LCT. If Quiet line state is entered
during the LCT, the test is aborted and PCM returns to the
Break state.
The duration of the LCT and the type of LCT is determined
by the bit signaling process in the Signaling sequence. LCT
is defined to have four durations, namely LC_Short
(50 ms), LC_Medium (500 ms), LC_Long (5 sec) and LC_
Extended (50 sec). When a port is started the first time, it
requests the shortest test duration. Every time the LCT fails,
the duration is increased up to a maximum duration of LC_
Extended. If the two ports on the link request different LCT
duration in the Signaling sequence, the longer LCT duration
is used to ensure a better measurement of link quality.

3.5 LINK ERROR MONITOR
The Link Error Monitor (LEM) continuously examines the
link error rate (LER) of an Active connection. Its function
complements the LCT to ensure that the link quality is adequate for ring operation at all times. When the LER exceeds
the cutoff value, the connection is flagged as faulty and
shall be removed from the token path.
The LEM and LER are based on the link error count from
the PHY level device. However, the implementation of LEM
and LER is not specified in the FDDI SMT Standard. One
way of calculating LER is to keep a running time average of
link error events occurred in a given time period. See Table I.

TABLE I. Link Error Rate (LER) Calculation Example
Time
(In ms)

LEC
in

Starting
Time

Ending
Time

Total Time
(In ms)

Total
LEC

LER
(In BIt/Sec)

T+100
T+200
T+300
T+400
T+500
T+600
T+700
T+BOO
T+900

0
1
0
0
0
2
1
0
0

T
T+100
T+100
T+200
T+300
T+400
T+500
T+600
T+700

T+100
T+200
T+300
T+400
T+500
T+600
T+700
T+BOO
T+900

100
200
300
300
300
300
300
300
300

0
1
1
1
0
2
3
3
1

 T.Out
THEN BreakCondi tion = TRUE, Done = TRUE
07 End Loop i f Done = TRUE
08 Wait (TL.Min)
09 IF BreakCondi tion = TRUE
THEN DO BreakAction
10 IF LSF1ag = TRUE
THEN TxLS = RCode (n) , CTSR = TxLS

The LETR value is loaded into the LEM counter when a
value is written to the LETR or when the internal LEM counter reaches zero. When the internal LEM counter reaches
zero, an interrupt condition is generated. The interrupt condition is registered in the Interrupt Condition Register. If the
corresponding bit (Bit4) in the Interrupt Condition Mask Register is also set, an interrupt is generated.
Current Link Error Count Register
The Current Link Error Count Register (CLECR) serves a
function similar to the Current Noise Count Registers. The
CLECR takes a snap shot of the internal LEM counter, thus
allowing the control process to read the LEM counter without interrupting the LEM counter. The CLECR can be used
to calculate the Link Error Rate and it is also needed in the
Link Confidence Test during the PCM connection sequence.

FIGURE 1. Polling Technique Example Code
Let's examine the code in more detail. Line 01 instructs the
PLAYER device to transmit Idle symbols. Line 02 is the beginning of the polling loop which ends at line 07.

State Threshold Register and
State Prescale Threshold Register
The State Threshold Register (STR) and the State Prescale
Threshold Register (CPTR) are used to set the threshold
value of the internal 15-bit state counter. The state counter
counts the duration that the PLAYER device receives a line
state.
The State threshold Register is a 7-bit register. It forms the
most significant bits of the state counter threshold value.
The State Prescale Threshold Register is an 8-bit register. It
forms the least significant bits of the state counter threshold
value. Like the Noise Threshold Registers, the STR and
SPTR together can specify a threshold value of 2.62 ms.
When the internal state counter reaches zero, the State
Threshold (Bit1) is set to one, therefore, an interrupt can be
generated.

In the polling loop, line 03 polls the CRSR register and
stores the received line state in the variable RxLS. If received line state is Quiet line state, line 04 sets the BreakCondition variable to indicate the PCM state machine needs
to return to the Break state. If the received line state is
Super Idle line state, it sets the variable LSFlag, indicating
that the correct line state is received. Super Idle line state is
tested instead of Idle line state because it is required to wait
for at least 12 Idle symbols in the Next state before any
action. Line 06 checks for the time out condition to ensure
the state machine does not get stuck in the Next state waiting for Idle symbols. The polling loop is repeated until one of
the conditions is met.
After existing the polling loop, the PCM state machine has
to wait for 30 ms (TLMin) before starting the next action
(Line 08). It is used to make sure that the PHY device on the
other side has enough time to recognize the line state symbols. If the BreakCondition is TRUE, line 09 will transit to the
Break state by executing a subroutine BreakAction. If everything is fine and the expected line state is received, the
PCM Psuedo Code machine determines the next transmission mode and directs the PCM state machine to transmit
the new line state symbols.
During the polling loop, the PCM software needs to monitor
the Current Receive State Register very frequently so that
line state information will not be missed. Failure to recognize all the changes of line state can cause failure in the
connection sequence and reinitialization of the connection.

The internal state counter can be used to keep track of the
length of time a particular line state is required to be transmitted or received before the PCM state machine can take
appropriate actions. For example, while the PCM state machine is in the Next state, the State Counter can be set at a
threshold of 1.6 ms to ensure that the state machine has
sent a sufficient number of line state symbols in the Connection state before it moves to the Next state.

4-51

l>
Z

..:...

N

......

~

~
~

r-------------------------------------------------------------------~

At this point, the PLAYER device is ready to receive new
line states. Line 14 sets up the mask for RCRA so that when
the expected line state is received, an interrupt can be generated. The value 0010 1111 written to RCMRA in this example allows the PLAYER to watch for Halt line state, Master line state, Quiet line state and also the Noise condition.
All these are required in the Next state. Line 15 clears the
mask for RCRB. This line is not necessary since RCMRB is
cleared at the beginning of the code. It is only included as a
reminder for other PCM states.
The next line state is finally transmitted in line 16. After the
new line state is transmitted, this code segment ends and
returns to the calling process.

4.3 INTERRUPT TECHNIQUE
The interrupt technique can also be used in implementing
the PCM software. This section explains a simple sample of
a portion of the PCM software using the interrupt capability
built in to the PLAYER device.
The code segment shown in Figure 2 is part of an interrupt
handler that responds to the line state reception during the
signaling sequence. It serves the same purpose as the'code
shown in the previous section.
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17

RCMRA

=O.

RMMRB

=0

tmp = ICR
tmp = tmp AND 1001 0000
ICR = tmp

4.4 OTHER TECHNIQUES
Interrupt and polling are by far the most popular techniques
used to implement PCM software. However, implementation
of the PCM software is not limited by the two techniques.
One other approach is to use the interrupt technique together with an event queue schedular.
The mix design that uses the interrupt technique and the
event queue provides less interrupt handling time and decouples the interrupt handling code from the PCM software.
When an event or line state occurs and an interrupt is generated, the interrupt handler unmasks the interrupt condition
and enqueues the line state event into the event queue.
Events in the event queue are taken care of one after another outside of the interrupt handling routines.
Many more possible designs can be used to Implement
PCM with the PLAYER device. The implementations depend on the underlying hardware platform and cannot be
covered by this paper.

RxLS = CRSR
IF RxLS = QLS
THEN DO BreakAction. RETURN
IF RxLS = lLS
THEN
TxLS = RCode(nl.
tmp = RCRA. RCRA = O.
tmp
RCRB. RCRB
O.
RxLS = CRSR.
RCRA = RCRARxMsk [RxLsl.
RCRB = RCRBRxMsk [RxLsl.
RCMRA = 0010 1111.
RCMRB = 0000 0000.
CTSR = TxLS .
RETURN
FIGURE 2. Interrupt Technique Example Code

=

=

Line 01 is first line of this part of the interrupt handler. The
interrupt handler has to examine the device and condition
that generates the interrupt before executing the code.
Lines 01 to 04 stop the PLAYER device from generating the
interrupt. It first stops the interrupt condition by clearing both
RCMRA and RCMRB. Then, it clears the Receive Condition
A (Bit5) and the Receive Condition B (BitS) in the Interrupt
Condition Register. Note that the ICR Is a conditional write
register, as a result, it is read in line 02 before a value is
written to it.
Lines 05 to 07 decide what to do with the received line
state. If the current line state is Quiet line state, BreakAction
is executed and this section of the interrupt handler is com·
pleted. However, if the received line state is Idle line state,
the interrupt handler needs to prepare the PLAYER for the
reception of the next line state and also transmits the next
line state.

5.0 Appendix
This section provides explanations and definitions of terms
needed to help understand PCM. However, the ANSI SMT
document shall be used as the standard reference. The
State diagram from the ANSI SMT document is reprinted in
Figures 3 and 4.
5.1 PCM STATES
The PCM State Machine is comprised of ten states. Section
4.1 explains the meaning and functions of each PCM state.
PCG: Off State
The Off state is the initial state of the PCM State Machine.
The PCM returns to this state upon the reception of the
PC_Stop signal from the Entity Coordination Management
Entity (ECM).

It first runs the PCM Psuedo Code machine by calling the
subroutine RCode(n), where n is the nth bit during the sig·
naling sequence. Lines 09 and 10, prepare the reception of
the next line state by clearing the registers RCRA and
RCRB. However, clearing all the line states in the RCRA
and RCRB register means that the current line state information is also cleared from the two registers. As a result,
the line state that PCM is expecting may also be erased.
Lines 11 to 13, prevent such a condition by writing the current line state information back to RCRA or RCRB.

In the Off state, the PMD optical transmitter is optionally
disabled and the PHY device is required to transmit Quiet
symbols.
PC1: Break State
The Break state is the entry point of the PCM connection
sequence. The Break state is entered upon the recepiion of
the PC_Start signal from ECM. The Break state is also entered from any other state when the connection sequence
cannot be completed and a reinitialization is required.
In the Break state, the PMD optical transmitter is disabled
and the PHY device is required to transmit Quiet symbols. A
few variables are also cleared and intialized during the
Break state.

4-52

PCO:OFF

PC1:BREAK

From st.t.s 0 to S:
PC( 00 ) -PC (SO)

PC-St.rt
Br •• Uclions

PC9:MAINT

CD

OILActions
PC_Stop
PC_t.l.int(m.inUs)
PC(09)
!.f.inLActions @

From st.t.s 0 to S:
PC(01)-PC(S1)

CD

PC.J:n.bl. PC(90

PCJlis.bl.
OILActions

CD

From .11 st.t.s:
PC(09)-PC(99)

PC.J.t.int(m.inUs)
PC(99) - - - - - : : " . ,
M.inLActions

@I

PC3:CONNECT

PC4:NEXT

T10>lS_J.fln &. not lS....FI.g PC( 44.)
I
SET lS_FI.g
PC5:SIGNAL lS....FI.g &. not RC....FI.g &. TPC>TLMin PC(44b)
SET RC....FI.g; PC....RCod.(n)....Actions
PUS = HlS &. not lS....FI.g
PC_Sign.1
PC(55.)I+------...;..;;==-=---PC(45)
SET lS....Fl.g; SET U.I{n)
l~igFI:~c¥P~~T@Min

r------

'I

PC-LS = MlS &. not lS....FI.g
...------PC(55b)
SET lS....Fl.g; CLEAR fLV.I(n)

PC(54)-~~=O"';;'~;...;.;:~----~

®

INC n; N.xLAclions
PC....POR
PC(44c)
ISM....PHJ.INE-STATE,r.qu.st{TRANSMIT....POR)
TD....FI.g &. not TC....FI.g &.
(PC_lS=(HlS or t.tlS) or TPC>LN.xt{n»
SET TC....FI.g; PC TCod.(n)....Actions
PC( 44d)

I

Br •• k-R.quir.d ®
1+----""--:::PC(51)
Br •• Uctions CD
PC6:JOIN
Br •• k-R.quir.d ® or (PC_lS = IlS &. lS....FI.g)
1+-----....:...-.....::::..........:....----:------....::.:. PC(61)
PC Join
PC(46)
Br •• k....Actions CD
Join....Actions TLMin
,,®PC(67)
V• .,fy_Act,ons S

PUS = HlS &. not lS....FI.g
PC(66)-::::::-:-::-:::----,
SET lS_FI.g
I

®

PC8:ACTIVE

Br •• k....R.qulr.d
or
PC{7S)-----..;;l...;S....F;;..;;;I."'g...;&..;.,TP.;.,..;;C->TLt.I=;:::i~n---_+I
(PC-LS = IlS &. not LS....FI.g)
Acliv• ....Aclions
1+-----;:::-PC(71)
TIO>lS_t.tin &. not LS....FI.g
PC{SS.)
Br•• k_Actions
I
SET LS....FI.g

®

CD

not TlLFI.g &. (PUS=HlS or RE..FI.g &. (Br•• k....R.quir.d

® or LEt.I....F.iI or TNE>NU.x»

1+--------------=~-------PC(SI)

CD

Br •• k....Actions
PC2:TRACE
TPC>Tl_Min &. LS FI.g &. not CF _Join
(
)
PC_lS = (OlS or HlS) &.
1SET CF_Join
PC BBb
not lS....FI.g &. P.lh_T.st = P.ss.d
SM PH lINE-STATE,r.qu.st(TRANSMIT POR)
PC(22.) SET P.th_T.sI = P.nding
lS....FI.g &. PC-LS = MLS &. not TR....FI.g
PC_LS = MlS &. not lS....FI.g &. not TR....FI.g
SET TR FI.g; SET Tr.c. Prop PC(SSc)
PC{22b) SET LS FI.g; SET Tr.c. Prop I

I

1+___________--'p~C;;;;T~r.::.c:.:·:..",,_ _ _ _ _ _ _ _ PC(82)
TraceJ.ctions

®

FIGURE 3. PCM State Diagram

4-53

TL/F111081-1

.....
C'II
r;-

Physical Connection Management Footnotes.

Z

1. OILActions:
SM_PM-CONTROLrequest(TransmiLOisable)'
SM_PH_Line-State.request(TRANSMIT_QUIET)
CLEAR CF_Loop
CLEAR CF---Join
CLEAR BS_Flag

T_Out)
Optionally. BreaLRequired may include the condition TNE> NS_Max:
PC_LS=QLS or (not LS_Flag & TPC> T_Out) or TNE> NS_Max
12. RestarLRequired:
PC_LS=QLS or (not LS_Flag & m"O & TPC>T_Out)
Optionally, RestarLRequired may include the condition TNE>NS_Max:
PC_LS=QLS or (not LS_Flag & ",00 & TPC>T_Out) or TNE>NS_Max

13. Transitions effected by the BreaLRequired or RestarLRequired conditions shall take precedence over other transitions. The reception of QLS while in
states 4 to B shall cause the PCM to transition to the Break State within PC_React time.

14. RESET TPC on every transition. This includes transitions where the destination state is the same as the originating state.
*This primitive is not required for all PMD implementations.

FIGURE 4. PCM State Diagram Footnote

4-54

Upon the reception of Quiet line state or Halt line state, the
PCM state machine leaves the Break state and enters the
Connect state. If the state machine is stuck in the Break
state for a long time (TB_Max), the state machine sets the
BS_Flag so that other management agents can examine
the condition and takes the appropriate action.

Once each individual bit has been transmitted and received,
the state machine moves to the Next state before returning
to the Signal state for the next transmission. Thus the Next
state is used as the bit delimiter between two signaling bits.

PC2:Trace
The Trace state is used to localize the fault domain of a
Stuck Beacon condition where the ring cannot recover from
its Beacon state. The state machine enters the Trace state
when receiving the PC_Trace signal from ECM while in the
Active state.
During the Trace state, the PHY entity transmits a stream of
Halt-Quiet (Master) symbol pairs.

PC6: Join State
The Join state is the first of three states in the join sequence
that leads to an active connection. The join sequence assures that both ends of a connection enter the Active state
together at the completion of the sequence.
The Join state is entered upon the completion of the signaling sequence when the PC---Join signal is issued from the
Psuedo Code machine. In Join state, a continuous stream of
Halt symbols is transmitted.

When all signaled bits have been transmitted and received,
the Signaling Sequence ends.

The only way to leave the Trace state is receiving the
PC_Start or PC_Off signals from ECM.

PC7: Verify State
The Verify is the second of three states in the join sequence. The Verify state is entered when Halt line state is
received when the state machine is in the Join state.

PC3: Connection State
The Connection state is used to synchronize the two ends
of the connection to begin the signaling sequence. It is also
used for clock recovery since the Break state does not
transmit any clocking information through the optical transmitter.
In the Connect state, the PMD level optical transmitter is
enabled and a continuous stream of Halt symbols is transmitted.
Upon the reception of Halt line state, the state machine
leaves the Connect state to the Next state. If Idle line state
is received before Halt line state, then the connection is not
synchronized and the state machine transmits to the Break
state to restart the connection sequence.

A continuous stream of Halt-Quiet (Master) symbols pairs is
transmitted during the Verify state.
PCB: Active State
The Active state is the last of three states in the join sequence. In this state, the port is incorporated into the token
path.
On initial entry into the Active state, a continuous stream of
Idle symbols is transmitted. Upon the reception of Idle line
state during the Active state, the PHY device is allowed to
enter the Active Transmit Mode and PDUs presented to the
PHY Port Request interface can be transmitted.
In addition to the normal break conditions, when Halt line
state is received in place of Idle line state, the connection is
not synchronized and a reinitialization of the connection is
required. If the Link Error Rate is too high, the connection
also needs to be reinitialized upon entering the Active state.

PC4: Next State
The Next state is one of the two states used in the signaling
sequence. The main purpose of the Next state is to separate the "bit" signaling performed in the Signal state. The
Next state is also used to transmit PDUs while MAC Local
Loop or Link Confidence Test is performed. The PCM PSl!edo Code machine is also started in the Next state.
On initial entry into the Next state, a continuous .stream of
Idle symbols is transmitted. While in the Next state, either a
continuous stream of Idle symbols or PDU symbol stream is
transmitted.
The Next state terminates and the state machine transits to
the Signal state upon the reception of Halt or Master Iilne
state or when the PC_Signal signal is received from the
Psuedo Code machine. The state machine transit to the
Break state upon the reception of Quiet line state.

PC9: Maintenance State
The Maintenance state is tr.led to perform the Maintenance
function. The Maintenimce state is entered upon the reception of the PC_Maint or PC_Disable signal from other
management agency.
5.2 PCM PSEUDO CODE
The PCM Pseudo Code provides and processes the information that Is sent between the neighboring PCMs during
the signaling sequence. As mentioned in the previous sections, the information is communicated via the bit signaling
technique whereas a bit value is represented by a stream of
line state symbols. The Halt symbols are used to represent
a logical one and the Master symbols pairs for a logical
zero.
This section explains the meaning of the ten bits of information communicated during the signaling sequence.

PC5: Signal State
The Signal state is one of the two states used for the signaling sequence. In the Signal state, individual bits of information are communicated across the connection by transmitting either Halt symbols or Halt-Quiet (Master) symbols pair.
Transmitting the Halt symbols is equated to the transmission of a logical one and the transmission of the Master
symbols pairs is a logical zero.

Blt{O): Escape Bit
Bit(O) is called the Escape Bit. It's value is zero for SMT
Version 6.2. The setting of Bit(O) is reserved for future assignment by the standard.

II
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Blt(1,2): PC_Type
Bit(1) and 'Bit(2) together state the PC_Type of this port.
The four PC_Types defined in the FOOl standard are encoded as shown in Table V.
TABLE V. PC rype Encoding

Blt(7): LCT Failed
Bit(7) is set to indicate that the Link Confidence Test was
failed by this end of the connection.
If either side signals that the LCT failed, the connection is
restarted and a long Link Confidence test is used next time.

-

PC_Type

Blt(1)

Blt(2}

0
0
1
1

0
1
0
1

PHY-A
PHY_B
PHY_S
PHY_M

Blt(8): MAC for Local Loop
Bit(8) is set to indicate that this end of the connection will
provide a MAC for the MAC Local Loop. MAC Local Loop
may optionally be used to verify MAC recovery processes,
token passing and the neighbor notification process.
If neither side set Bit(8), then the MAC Local Loop is omitted. If this end does not support MAC Local Loop and the
other end does, this end of the connection has the option of
not performing the MAC local Loop.

The PC_Type is communicated during the signaling sequence so that the connection policy can be enforced be,fore the station is inserted into the token path.
Blt(3): Port Compatible

Blt(9): MAC on Port Output
Bit(9) is set to indicate that this end of the connection intends to place a MAC in the output token path.

Bit(3) is set to one if the two ports on the link are compatible
which means that this connection is allowed and supported
by both stations. Connections that are not allowed are withheld until Bit(9) is received and a PC_Start signal is generated to reinitialize the connection. All the conne,ctions are
allowed in the standard except a M-M connection, however
certain types of connection can be rejected depending on
the implementation.

5.3 PCM TIMERS AND
TIMER EXPIRATION VALUES
There are only a few timers used in PCM to determine the
length of certain operations and the time in which an appropriate response is expected However, one timer can have
different expiration values depending on the state of the
PCM software.
For most of the time, the timers are used to measure the
maximum timer to wait for the reception of certain line
states, the minimum duration to transmit certain line states,
the duration for LCT, etc. Therefore, the timer operations
help to ensure the two PCMs are synchronized.
The following timers are employed in PCM:

Blt(4,5): LCT Duration
Four durations of Link Confidence Test are allowed and
Bit(4) and Bit(5) specify the LCT duration suggested by this
port. If the suggested values from the two ports are different, then the longer duration is used for the Link Confidence
Test. The LCT duration is encoded into Bit(4) and Bit(5) as
shown in Table VI.
TABLE VI. LCT Duration Encoding
LCT
Duration

Blt(4)

Blt(5)

Short
Medium
Long
Extended

0
0
1
1

0
1
0
1

TPC
Physical Connection Timer is the main timer that PCM uses.
It is used to ensure state transitions proceed at the desired
rate.
TID
The Timer for Idle Detection is used by PCM to measure the
time of continuous ILS reception.

The Short LCT duration is used when' there is no recent
history of excessive link errors. The Medium LCT duration is
used when a failure in LCT occurred. The Long LCT duration is used after the rejection of a link due to an excessive
Link Error Rate. And finally, the Extended LCT duration is
used when LCT is used to withhold an undesirable connection.

TNE
The Timer for Noise Event is used by PCM to detect the
length of noise events. If an excessive number of noise is
received, the PCM state machine can optionally reinitialize
the connection by moving to the Break state,
The rest of this section lists the timer expiration values used
in the PCM state machine. All of the expiration values are
used for TPC timer unless specified otherwise. The default
value is also highlighted for the ease of referencing.

Bit(6): MAC Available for LCT
Bit(6) is set to indicate that a MAC will be placed at this end
of the connection during the Link Confidence Test.

PC-React: 3.0 rns
PC_React states the maximum timer for PCM to make a
state transition to the Break state when the connection
needs t6 be restarted. The reinitialization of the connection
is needed upon the reception of Quiet line state, when a
fault condition is detected, or PC_Start is presented.

If the other port on the link does not have a MAC available
for the Link Confidence Test, then this end may optionally
source valid PDUs.
If this end cannot connect to a MAC during the Link Confidence Test, then this PHY device is configured to repeat
any received PDUs.
Note that LCT is performed after Bit(6) is communicated,
during the Next state.

4-56

TB-Mln:ems
The minimum time that PCM transmits Quiet symbols and
receives Quiet line state during Break state. This value is
rather large because PCM has to wait for the other end to
response.

NLMax: 1.3 ms
The maximum time that noise is tolerated before the connection is considered to be unreliable and needs to be restarted. This timeout value is based on the TNE timer.
5.4 SIGNALS
A signal is used to initiate a state change within PCM. It is
also used to communicate with other SMT entities. The signals can be generated by PCM or other entities.

TBJax:50 ms
The maximum time the state machine is allowed to remain
in the Break state before an error flag (BS_Flag) is set to
indicate that the PCM is stuck in the Break state.

The following signals are used in PCM:

C_Mln: 1.6 ms

PC_Start

The minimum time the state machine is required to send
Halt symbols after the reception of Halt line state during the
Connect state. This timer is used to assure that the other
end of the connection has recognized the Halt symbols being transmitted in the Connect state.

A signal that is set by the Entity Coordination Management
Entity (ECM) to PCM. PC_Start is used to signal the PCM
to initialize a connection.
PC_Start is also signaled by PCM when the Link Confidence Test fails and the connection is re-initialized.

LLMln: 480 ns
The minimum time of continuous reception of Idle line state
before Idle line state is recognized by the PCM state machine. The duration of LS_Min is greater than or equal to
12 symbol times to ensure robustness. This expiration value
to be used in the Next state and the Active state. It is measured by the TID timer.

PCJaint
A signal that is set by a higher-level management entity to
PCM. PC_Maint is used to signal PCM to enter the Maintenance state.
PC_Trace
A signal that is set by ECM to PCM. PC_Trace is used to
signal PCM to enter the Trace State.

TLMln: 0.3 ms
TLMin is the minimum time to transmit a line state before
advancing to the next state. It is used in the following states:
Next. Signal. Join. Verify and Active. The TLMin value is
set to twice the time required for a line state to be recognized by the PHY device in the other end of the link.

PC_Stop
A signal that is set by ECM to PCM. PC_Stop is used to
signal PCM to enter the Off state.
PCJnable
A Signal that is set by a management entity to PCM.
PC_Enable is used to signal PCM to move from the Maintenance state to the Off state.

T_Out: 100 ms
T_Out specifies the Signaling timeout value. It is defined as
the minimum time the state machine is required to remain in
a state to wait for the line state reception before reinitializalion of the connection.
The expiration of T_Out indicates that a line state change
is expected but did not happen. the connection has failed
and needs to be re-started in the Break state.

PC_Disable
A signal that is set by a management entity to PCM.
PC_Disable is used to signal PCM to move from any state
to the Maintenance state.
PC_Signal
A signal that is set by PCM for its internal use during the
Signaling Sequence. PC_Signal is used to indicate that the
next value is available and ready for transmission.

TJext(n): 100 ms
T_Next(n) is the same as the T_Out values but it is used
in the Next state since LCT and MAC Local Loop is to be
performed during the Next state. T_Next(n) specifies the
timeout value for the nth bit in the signaling sequence.
T_Next(7) and T_Next(9) specifies a different timeout value other than the default ones.

PC_PDR
A signal that is set by PCM for its internal use. PC_PDR is
used to indicate that a PDR is to be transmitted.
PC-",oln

TJext(7): LCT Duration
The T_Next(7) value is the negotiated value of the Link
Confidence Test duration after the Signaling of Bit(4) and
Bit(5). It can take on one of the following values: LC_Short
(50 ms). LC_Medium (500 ms). LC_Long (5.0 sec) or
LC_Extended (50 sec).

A signal that is set by PCM for its internal use. PC--!oin is
used to indicate that the Signaling Sequence has been completed successfully and the Join Sequence is started.

T_Next(9): 200 ms
The maximum time for the optional MAC Local Loop to be
performed. This timer is used to prevent deadlock while allowing sufficient time for MAC recovery process completion
and exchange of neighbor information frames.

II
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5.5 PCM FLAGS AND VARIABLES
A flag is a variable that shall take one of two values: set(I)
or cleared(O). Flags are used to reflect the status of the
state machine and also to signal other entities of the PCM
status.
Variables can take on a wider but still a limited set of values.
Variables serve the same function of Flags.
The following is a list of flags and variables used in PCM:

PCJelghbor
A variable that is set by PCM to other management entities.
This variable is set to indicate the PC_Type of the PHY at
the other end of the connection. PC_Neighbor is set during
the signaling sequence.
PC_Neighbor can have one of five values: A, B, S, M, or
None.

PC_MAC_LCT

A variable that is set from PCM to other management enti·
ties. This variable is set after the signaling sequence has
been completed to indicate the mode of physical connection that has been performed.
PC_Mode can have one of three values:
Peer
PC_Mode is set to Peer when neither the port
under control or the port at the other end are of
type M. It indicates that this connection exists
within the trunk ring.

PC_Mode

A flag that is available internally to PCM. This flag is used to
indicate that a MAC will be used for the Link Confidence
test.
PC-MAC_Loop
A flag that is available internally to PCM. This flag is used to
indicate that the MAC Local Loop will be performed before
the connection is made active.
CFJAC
A flag that is set by the Configuration Control Management
(CCM) to PCM. This flag is used to indicate that a MAC is
available for the Link Confidence test or MAC Local Loop.

Tree

None

BS-Flag
The Break State Flag (BS_Flag) is set by PCM to indicate
that the PCM state machine is not leaving the Break state in
an expected time interval and a problem is suspected. It can
be used by other management agencies to indicate a prob·
lem in PCM or the link that needs to be resolved.

PC_Withold
A variable that is set by PCM to other management entities.
This variable is used to indicate the reason the connection
did not get incorporated in the ring.
PC_Withold can have one of the following three values:
None, Port M to Port M, or Other incompatible Port Types.

LEMJaii
A flag that is set by PCM to other management entities. It is
set to indicate that the Link Error Rate exceeds the
LEA-Cutoff threshold. The flag is cleared when the Link
Error Rate Threshold test is passed. It is used to remove
connection with excessive Link Error Rate.

MalnLLS
A variable that is set by other management entities to PCM.
This variable is used to indicate the symbol stream to be
transmitted when the PCM is in the Maintenance state.

PC_Type

MainLLS has one of the following values: Quiet, Halt, Idle,
.Master or PDR.

A variable that is set by the higher level management agen·
cy to PCM. It is used to specify the type of port being man·
aged by the PCM.
Four different ports are defined:
A

The port in a Dual Attachment Station or Concentrator
which attaches to the Primary In and Secondary Out
when attaching to the dual ring.

B

The port in a Dual Attachment Station or Concentrator
which attaches to the Secondary In and Primary Out
when attaching to the dual ring.
The port in a Single Attachment Station (SAS) or one of
the port in a Single Attachment Concentrator (SAC).

S
M

PC~ode is set to Tree when orie of the port is
of type M. It indicates that the connection exists
with a concentrator tree.
The connection is neither of the two previous values. PC_Mode is set to None when the connection type is yet unknown.

PC_LS
A variable that is set by PCM to another management entity.
This variable is set to indicate the line states received by the
PHY.
PC_LS can have one of the following values: QLS, HLS,
MLS, ILS, ALS, NLS or LSU.
PC_LCT_Faii
A variable that is set by PCM to other management entities.
This variable is used to indicate the number of consecutive
failures of the Link Confidence Test.

n

The port in a Concentrator that is used to connect with
aSASorSAC.

A variable that is set by PCM for its internal use. This variable is used to indicate the number of the next value to be
signaled in the Next state and the current value being signaled in the Signal state.

4-58

.

l>
National Semiconductor
Application Note 728
Robert M. Grow, Jim Schuessler

fDOI Station Ma.nagement
with the Na.tional Chip Set
1.0 INTRODUCTION
The National OP83200 FOOl Chip Set includes special features that aid in the management of an FOOl station as well
as the management of an FOOl ring. An attempt is made
here to guide you through some of the details of Station
Management (SMT) using National's OP83200 FOOl Chip
Set with as little pain as possible. Special circumstances for
non-standard applications are also discussed.
Oue to the universally acknowledged complexity of the
FOOl Standard, it is always a wise idea to have ready access to the original documents when reading collateral material-this is no exception! We recommend obtaining the
ANSI X3T9.5 FOOl Standards set1.
The BMACTM device and PLAYERTM device are two of the
devices comprising the National OP83200 FOOl Chip Set.

They both provide a rich set of fully maskable interrupts.
These interrupts are used to drive SMT protocols, including
Frame Based Management, Connection Management and
Ring Management. The BMAC device includes counters for
fault isolation and station and ring performance monitoring
that ease the implementation of SMT protocols. The PLAYER device includes multiplexing capability to implement the
node configurations called out in the SMT Configuration
Management state machine (the most popular being a Single Attach Station (SAS) and Oual Attach Station (OAS)),
internal hardware for link error monitoring, and noise timing
(see Figure 1). The full duplex architecture of the chip set
provides for comprehensive testing and fault isolation.

DP83261 BMAC DEVICE (BASIC MEDIA ACCESS CONTROLLER)
IJ SMT multicast addressing on·chip
IJ Full duplex architecture
IJ Auto generation of Beacon and Claim frames
IJ Multiple transmit immediate modes

[]
[]
[]
[]

Multiple diagnostic counters
Ring latency timer
4-bit late counter
Same information field detection for MAC frame filtering
IJ Ouplicate address detection
[] Multiple token detection
DP83251 155 PLAYER DEVICE (PHYSICAL LAYER CONTROLLER)
IJ On-chip configuration switch

[] Line state history registers
IJ Link error detector
IJ Noise threshold timer
IJ Unique injection register
IJ Full duplex architecture

FIGURE 1. National DP83200 FDDI Chip Set SMT Features

1 There are four documents comprising the FDDI Standard: PMD, PHY, MAC and SMT. The first three are published standards available through ANSI (phone:
212·6424900), the last, SMT, is still in draft form at the publication time of this Application Note. It can be obtained through Global Engineering Documents,
phone 800·854·7179, or 714-261-1455.

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A simplified Claim Process flow is shown in Table I:

Four general areas of management will be discussed in this
paper: how to select values of operational parameters, how
to use the BMAC device for fault isolation, how to use the
PLAYER device for implementing Connection Management
(CMn, and how to monitor network status and performance.

TABLE I. Timer Values In the Claim Process

2.0 OPERATIONAL PARAMETERS
FDDI supports a broad range of network configurations, and
the FDDI standard specifies default parameters for operation of large configurations. The National FDDI Chip Set is
designed to operate over an even larger range of configurations for special applications. The default values of these
parameters must be changed for larger configurations. In a
few systems, it is also valuable to optimize parameters in
small ring configurations.
At the core of the timed token protocol implemented in the
BMAC device are timers used to control the transmission of
information on the network and to detect when ring recovery is required. These timers are loaded with values which
ultimately determine the performance of the ring. Ring recovery/startup is a function which can be performed by the
BMAC device automatically with default timer values. Other
values for these timers can be loaded, but be warned:
changing these values from the defaults may cause poor
performance, (high usable token latency or low throughput)
or worse yet, oscillation between Claim and operational
states. For instance, a shorter Valid Transmission Timer
(TVX) value might be used on a small ring to accelerate ring
recovery, but if the shorter value was used on a large ring it
could cause the above problems.

Value

Becomes

Value

TREQ
Shortest Tbid
TNEG

-+
-+
-+

Tbid in a station's Claim frames
TNEG in all stations
Token Rotation Timer (TRn
when the ring becomes
operational

Note: See Recovery Required in MAC Standard

The BMAC device is capable of automatically generating
Claim frames. It starts the Claim Process when TVX times
out or Tlate = 2 (Tlate is a 4-bit counter which increments
once each time TRT goes to zero). When the frames are
transmitted, the BMAC device places the TREQ value
stored in the BMAC device Parameter RAM into the Claim
frame. This value then becomes Tbid to the next station on
the ring. The receiving BMAC device saves the Tbid from
the Claim frame as the potential TNEG, while comparing it
to its TREQ. If the received Tbid time is shorter than its own
TREQ, it stores the Tbid value as its new TNEG, stops
transmitting Claim frames and repeats incoming Claim
frames. If the received Tbid is larger than the current TREQ,
the station keeps (or starts) transmitting its current Claim
frame. The Claim Process completes when the BMAC device receives Claim frames with both source and destination
address equal to its own, (its own Claim frame) as well as
the Tbid value equal to its TREQ. This process insures that
the shortest Tbid value of any node participating in the
Claim process ends up as TNEG for all nodes. If an implementation externally generates Claim frames instead of letting the BMAC device generate them, then it is very important that TREQ in the BMAC device Parameter RAM be
equal to the first four bytes of the Claim frame (Tbid). If this
isn't done, the Claim Process may not complete, and a false
duplicate address condition may be detected by the SMT
Ring Management protocol.

In most cases, the operation and performance of FDDI is
determined by the most demanding (typically the shortestl)
parameter in all stations on the ring. For example, the station with the shortest TVX value will frequently be the station starting a Claim Process. This is because any timed out
TVX will cause the BMAC device to start the Claim Process
(TVX timeout indicates no frame received within TVX time).
When powering up, or after a hardware reset, the BMAC
device has been designed to revert to default values for
many critical parameters; though, a station must initialize
the Parameter RAM before participating in an FDDI ring.
Parameter RAM values include the long and short addresses, for example.
The use of the BMAC device's programmable timers is discussed below to help illustrate the different alternatives for
management of the parameters and selection of proper values for desired operational characteristics.

2.2 Selection of TREQ
Two major factors are used in selecting a TREQ value. The
first is the delay and segment size for synchronous traffic.
The second is the desired queuing delay for all traffic, both
asynchronous and synchronous. 3 The first factors: delay
and segment size are just another way of specifying the
throughput necessary for the synchronous application. The
data source is usually isonchronous (periodic) and therefore
must be serviced or "disaster" will strike. (An example might
be voice data, where a delay would result in a noticeable
blank spot in continuous speech.)
An application must be able to rely on the stability of TNEG,
therefore, TREQ should not be changed frequently. It is
generally a bad idea to change TREQ as application processes start and stop. In fact, there are really only two reasons for changing TREQ from the default TMAX: To create
a synchronous service period, or to adjust the asynchronous
maximum usable_token latency-both relate to token latency.

2.1 The Claim Process
Claim is a ring state which must be completed before the
ring can become operational. The objective is to create an
interoperable environment in which all stations may communicate with both asynchronous and synchronous traffic. The
process does this by setting the ring's Target Token Rotation Time (TTRn and determining who will issue the first
token (the "winner" of claim). Following FDDI rules for the
Claim Process, the station with the shortest Requested Target Rotation Time (TREQ) is the "winner", and will determine the Negotiated Token Rotation Time (TNEG) for the
ring. TNEG is used as the operational value for the Token
Rotation Time (TRn in all stations on the ring.2

3 For B discussion of Asynchronous versus Synchronous traffic, see the

ANSI X3T9.5 FOOl MAC Standard.

2 In many cases, stations will have the same TREQ value. In this case other
information in the Claim frame is used to select the "winner".

4-60

2.2.1 Selection of TAEQ for Synchronous Traffic

20 ms Case:
28 bytes overhead + 200 bytes data = 228 bytes/
frame-12% overhead
228 bytes/frame • 50 frames = 11,400 total bytes
(10,000 bytes data)

Changing TNEG, and thus TRT, has significant implications
on synchronous traffic. Synchronous service is usually
viewed as some number of bits per second; but in FOOl,
synchronous service is provided in bytes per token rotation.
Each time a token is received, a station may transmit X
bytes based on its synchronous allocation. The total synchronous bandwidth allocation for the ring may not exceed
TNEG less overhead. 4
A synchronous application will generally determine the
bandwidth requirement on application layer (OSI Layer 7)
data; but the synchronous allocation requested in SMT protocols must include overhead for placing the application
data in a frame. A change in TNEG changes the framing
overhead. This is because the number of bytes of overhead
is the same for 1 byte of application data or 4 kBytes of
application data. Since an objective of synchronous service
is to guarantee bandwidth to an application, a shorter TTRT
will cause the application data to be segmented into smaller
sizes. So as TNEG is lowered, response time decreases
(faster token rotation) but overhead increases and therefore
overall throughput decreases. This is the tradeoff between
response time and throughput.

There is a 37% decrease in bandwidth in the 5 ms TRT
case verses the 20 ms TRT.
If other protocol information like an LLC is transmitted on
each frame, the increase would be even worse. In addition,
a change in TNEG also creates ring stability problems for
previously enqueued synchronous information. Frames
which are queued at 20 bytes, for example, would cause the
ring to go into the Claim Process if enough of them were
queued when TRT changed to a lower value requiring 50
byte frames.
Synchronous service is not well specified in current FOOl
documents. If each synchronous application is allowed to
pick its own TREQ, then as applications start and stop,
TNEG will increase or decrease. In most cases, it is better
for an application to learn what the synchronous target time
is and segment to that size, rather than dynamically changing it as applications start and stop. This Simpler model of
operation can be handled in the ring's synchronous bandwidth allocation algorithm.

For example, the synchronous requirement for an application layer requiring 10,000 bytes per second above the MAC
layer would increase 37% on MAC overhead alone when
TNEG changes from 20 ms to 5 ms. A little math will illustrate this.
Remember that all bytes transmitted must be counted in the
synchronous allocation. The fixed bytes of overhead per
frame are shown in Table II.

All this is to say that applications (OSI Layer 7) should not
specify or have control over TREQ. Synchronous allocation
should be done by a process which has global knowledge of
the throughput and latency requirements of all stations.
SMT is uniquely qualified for this purpose.
2.2.2 Selection of TAEQ for Asynchronous Traffic
Asynchronous traffic is not effected significantly by the value of TNEG in typical systems. Here, the desired TNEG is
based on a tradeoff between network throughput and response time. For example, on a large ring of 150 stations (n)
at 1 p.s latency per station, the maximum throughput is 99%
at 20 ms. TNEG, and 97% at 5 ms TNEG.

TABLE II. Fixed Bytes of Overhead per Frame
Number
of Bytes

Portion
of Frame

8
1
1
12

2

Preamble
SO (JK Symbol)
FC
Addresses: SA, OA
OATA
FCS
EO

28

Total

...
4

n(TNEG - Ring Latency)
n(TNEG) + Ring Latency = Percentage Throughput
Therefore: 150 (20 ms - 150 p.s)/(150(20 ms)
= 99%
and:

150 (5 ms - 150 p.s)/(150(5 ms)
= 97%

+

+

(1)

150 p.s)

150 p.s)

Another important performance characteristic is the maximum usable_token latency. Usable_token latency is the
time for a token to return to a particular station, and be
usable for asynchronous traffic. This means the TRT has
not timed out once since the station last saw the token.
(This is opposed to maximum token latency which is 2 times
TNEG, a much smaller time.)

If TRT is 20 ms that means the token will circulate 50 times
per second (1/20 ms) at the maximum network utilization.
Our requirement is for 10,000 bytes/s which means 200
bytes per frame (10,000 bytes/s)/(50 frames/s). If TRT is
5 ms, the other alternative, the token rotates 200 times per
second (1/5 ms). The same 10,000 bytes are delivered in
50 bytes per frame (10,000 bytes/s)/(200 frames/s). Therefore:

It is possible, though highly improbable, that each station in
an overloaded ring could use the token for TNEG time (minus ring latency) when the token is captured. This is a worst
case scenario. The maximum usable_token latency would
then be (n - 1) (TNEG) + 2 (Ring Latency). For this improbable event to occur each station on the ring must transmit for the maximum allowable time-in this case TNEG minus ring latency.

5 ms Case:
28 bytes overhead + 50 bytes data = 78 bytes/
frame - 36% overhead
78 bytes/frame • 200 frames = 15,600 total bytes
(10,000 bytes data)

In the above configuration, the maximum usable_token latency is 3 seconds at 20 ms TNEG, and 0.75 seconds at
5 msTNEG.

4 Actual time Is Target Token Rotation TIme (TTRT) less the sum of maxi·
mum Ring Latency (D_MAX = 1.617 ms), maximum Frame Time (F-MAX
= 0.361 ms), and Token TIme (0.00088 ms).

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(n - 1) (TNEG)
Latency

+

frames were transmitted on the last rotation. In the large
150 station ring described earlier, a 1 kByte frame would
represent 50% network load to the MAC timers. A longer
latency would require a larger frame to get the same 50%
load factor. The latency timing feature of the BMAC device
allows determination of the appropriate threshold for a load
factor. (See Network Monitoring, Section 5, for an example
load factor calculation).
The threshold may also be viewed as a reservation of time
for transmission of frames at higher priority. In this case the
thresholds can be set directly from the tables contained in
the BMAC device datasheet (end of Section 5).

2 (Ring Latency) = Max. Usable Token
(2)

Therefore: (150 - 1) • 20 ms + 2(150 ,..s) = 3.0s
and:
(150 - 1) • 5 ms + 2(150 ,..s) = 0.75s
This kind of tradeoff can best be made by a network management station as described later, since a station that attemps to minimize the usable_token latency can adversely
effect network throughput in some configurations. For example, if the Ring_latency were 1· ms, instead of the
150 ,..S above, the change in TNEG from 20 ms to 5 ms
would change the maximum throughput from 95% to 85%.
TABLE III. Example Configurations and TNEG Value
Stations

TNEG

Maximum
Throughput

Maximum
Usabl&-Token
Latency

10

8
64
167

0.9986
0.9998
0.9999

0.072ms
0.576ms
1.503 s

150

8
64
167

0.9811
0.9976
0.9991

1.192s
9.536s
24.883 s

500

8
64
167

0.9374
0.9922
0.9970

3.993 s
31.937s
83.334s

2.4 Selection of TMAX and TVX
Stations should only change the TVX and TMAX values
when there are critical responsiveness requirements. No improvement in throughput will be achieved, and in most rings,
no improvement in network availability will be achieved.
However, a discussion of their selection. criteria is provided
her as guidance for tuning these parameters to the latency
of the network.
2.4.1 Selection of TMAX
The BMAC device has been designed so that it can be applied to rings with extremely large latencies. In these cases,
the value of TMAX will need to be longer than the default.
Making TMAX shorter has a statistically insignificant impact
on ring availability, therefore, most implementors need only
use the default specified in the FOOl Standard. The BMAC
device sets TMAX to default on reset. Special closed systems may benefit from a shorter TMAX value, since a very
small set of ring failures is detected by timing for TMAX. In
either the longer or shorter TMAX case, the BMAC device
can be loaded with the desired value after reset. S

Note: At 1 f's per stetlon latency (Including optical fiber propagation delay).
actual latency may be different.
.

Note that a TNEG (TREQ) of 8 ms can significantly reduce
the usable_token latency (a good thing) and still not decrease throughput significantly for rings of under about 150
stations.
A· robust method of contrOlling the TNEG of a ring can be
created using the operational characteristics described
above, and the management features of the BMAC device.
Normal stations operate with the default TMAX (approximately 167 ms) and TREQ equal to the TMAX. A network
management station determines the desired TNEG for the
ring based on knowledge of synchronous applications requirements and ring throughput implications. The network
management station sets its TREQ to the desired TNEG
value, thus determining the TNEG resulting from the Claim
Process. See Table III.
If implementors allow stations to set TREQ independently,
then it is advisable that a lower bound on TREQ be enforced to protect the network from serious denial of service
problems. When TREQ is changed, the station can cause a
Claim Process by setting the ClM bit of the Function Register (FR) in the BMAC device. If this is not done, then it may
be a long time before the desired change in TNEG would
occur.

2.4.2 Selection of TVX
The Valid Transmission Time (TVX) register is used to hold
the FOOl parameter TVX....valid. The token is assumed to
be lost if the time between receiving valid frames or non-restricted tokens is longer than TVX. The BMAC device loads
TVX with the default value recommended in the FOOl MAC
Standard upon reset. TVX need only be changed in rings
with latencies larger than 1.7 ms. If a station has a TVX
value that is too small, the likely symptom will be a ring that
oscillates between the Claim Process and being operational. The optional SMT Parameter Management Frame (PMF)
capability can be used by a network manager to attempt to
fix an oscillation condition. The National FOOl chip set has
been deSigned with larger than default counters to allow
large latency networks, other implementations may not be
able to interoperate in one of these very large networks.
In stations which need a non-default TVX value, station implementors can provide a non-volatile storage location. This
feature would avoid potential oscillation between the ring
being operational and being in the Claim Process, when stations are powered off and on in a larger network than supported by the default value.

2.3 Selection of Asynchronous Priority Thresholds
Asynchronous priorities are set in the THSH1, THSH2, and
THSH3 Registers. These priorities are of greatest value
when the ring latency is large. Two approaches can be used
for setting the thresholds. The first sets the threshold at a
load factor, for example 50% load. In the majority of systems, the latency will be small enough that all load factors
default to the same effective leilel, namely transmit if no

2.5 Adjustment of Value for Parameter Encoding
Two representations are used for timer values in the BMAC
device. Where accuracy and resolution are important, the
chip uses binary encoding. Where network manageability
5 See the FOOl Standard for the calculation of these values. The value of
OMAX should be computed from the equations In the PHY Stendard. TVX
and TMAX equations are given in the MAC Stendard.

4-62

the ring being non-operational, and other times the ring may
be OSCillating between operational and non-operational
states. The BMAC device is designed to support network
management applications that correct or isolate these rare
faults. Described below are several methods which facilitate
fault isolation.

would not be compromised, an exponential representation
was used. Tables for converting exponential values are included in the BMAC device datasheet. This optimization
saved circuitry which allowed other functions to be included
in the BMAC device. When desired values cannot be represented exactly in the chip, the guidelines shown in Table IV
can be used.

3.1 How to Perform Transmit Immediate
Transmit Immediate is a BMAC device feature which allows
the transmission of any frame without the ring becoming
operational. In other words, no token needs to be received,
the station just strips anything received and transmits its
frame-thus: Transmit Immediate.
The transmit immediate capability can be used to isolate
many faults. One tool that is useful is to allow a network
manager to segment the ring. USing this capability, faults
can be localized by monitoring the symptom of the failure.
For example, if the ring cannot become operational, an application can segment the ring by forCing a configuration
change in a remote station(s). If the symptom goes away in
the segment containing the network management station,
the fault is probably in the isolated segment of the network,
if it doesn't, the fault is probably in the remaining segment of
the network. The same procedure can then be used with a
different remote station until the fault domain is located.

TABLE IV. BMAC Device
Parameter Encoding Guidelines
TREQ
TMAX

TVX
THSH

Loaded Time s: Desired Time
Loaded Time :2: Desired Time
Loaded Time :2: Desired Time
Loaded Time Is the Closest to Desired Time

2.6 Changing Addresses
The BMAC device has been designed to reduce the number
of things that an implementor needs to worry about. The
setting of the station addresses, unfortunately, is not one of
those things. Addresses can be changed by the SMT processor through the control interface, and here lies potential
danger. Dangers exist for both Group and Individual Addresses; but the more serious implications are in changing
an Individual Address. If an Individual Address is changed
while a frame is on the ring, or still enqueued, then a no
owner frame can be created, since the address is changed
one byte at a time (a no owner frame will eventually be
stripped when it runs into a station which is transmitting).
This can be avoided by waiting for the transmit queue to
become empty, then disable the Individual Address with the
BMAC Device Option Register, until the change is complete.
If the implementation uses the optional external Claim or
Beacon frames, the address must be changed in those
frames also.

In the case of timer parameter faults, the problem may be
corrected directly by performing a transmit immediate of an
SMT PMF Request Frame to the station with the invalid
parameter.
Applications using the transmit immediate capability must
take into account three important items. Differing implementations of transmit immediate, transmission of MAC frames,
and the effect of the Ring being Operational.
The BMAC device has the capability to perform transmit
immediate under all ring conditions; other implementations
do not. Therefore, the application cannot expect a response
from other stations.
The fault isolation protocol must take into account that in a
ring stuck at the Beacon Process, each repeating station
will enter Claim every TMAX, destroying traffic being repeated at that time. As a result, the source or destination of the
frame, or any station between may make the transition to
Claim, causing an abort of the management frame. The
probability of getting a frame to the destination is improved
with a few techniques. Setting the Inhibit Recovery Required
option (lRR bit in the BMAC device Option Register) will
allow the station to transmit complete frames independent
of the station's TRT expirations. Setting the IRPT option will
stop MAC frames generated by other stations from aborting
transmission. A short frame has a statistically smaller
chance of being aborted by other stations; but retry of the
frame may also be necessary.

The BMAC device also includes an on-chip SMT group address recognition capability. The SMT committee has request addresses for use in SMT frame protocols. These reserved addresses are for the exclusive use of SMT processes. Changes to the base group addresses may result in
frames being copied as the result of comparison against a
partially changed address. If the group address capability is
used for SMT addresses, individual addresses can be enabled and disabled without this problem.
2.7 Denial of Service Protection
Some of the discussion on individual parameters indicated
how the ring can become unusable with the improper setting of that parameter. Improper use of parameters or
frames can result in disruption of service to the entire ring,
or in some cases, to a single station. These conditions can
be grouped together as denial of service problems. In general, it is prudent that an implementor only allow operational
changes by trusted software. This includes the setting of
parameters, as well as the ability to source MAC frames
(e.g., Claims and Beacons) and SMT frames. This is simplified by features in the BMAC device like internal Claim and
Beacon generation, transmission of Source Address from
the Parameter RAM, and reset to default values of important parameters.

3.2 Implementing SMT Events
The BMAC device and PLAYER device are deSigned to allow for reporting of significant network events. This includes
timer expirations, received frame conditions, and counter increments and overflows. All 0.1 these conditions are implemented as maskable interrupts. Use of these interrupt conditions can eliminate any need for pOlling of status in the
FOOl logic. SMT frames are transmitted as the result of
some of these events. The ability for generation of interrupts on increment of a BMAC device statistical counter
(e.g., Error Counter) allows for generation of event report
frames directly from BMAC device interrupts.

3.0 USE OF THE BMAC DEVICE
FOR FAULT ISOLATION
In some failure cases, communication on an FOOl ring will
be impossible because of a low probability failure within
some station on the network. Sometimes, this may result in

4-63

=r-------------------------------------------------------------~

.

~

~

4.0 USE OF THE PLAYER DEVICE
FOR CONNECTION MANAGEMENT
The interface between the PLAYER device and the FOOl
connection management (CMD protocol is designed so that
time critical operations are performed by the PLAYER device. The most time critical operation to be performed by the
CMT software is PC_React. PC_React is equal to 3 ms
and is defined by the standard as the maximum time for the
Physical Connection Management (PCM) state machine
(implemented by a combination of hardware and software)
to make a transition from the active state to the break state
in response to the Quiet Line state (QLS), a fault condition,
or a request to start the PCM protocol (PC_Start).

LOAD

TRT
I

I

ROTATION TIME

Important fault isolation features are provided in the Connection Management (CMD protocols specified in the SMT
standard. The PLAYER 'device includes counter and interrupt logic to aid in implementing these protocols. The line
state reporting of the PLAYER device includes individual
reporting of each state transitioned, thus providing a history
of all line states seen since the register was cleared. (Registers: Receive Condition A and B (RCRA, RCRB». This is
important since the Physical Connection Management
(PCM) is intended to run, even when the optical link has an
extremely high error rate. The line state history thus provides greater flexibility to the software implementing these
protocols. In addition, individual masking of line state interrupts can eliminate interrupts for line states that are ignored
in a specified operational state.

TUF/11084-1

FIGURE 2. Timed Token Protocol
If the Token Rotation Time is equal to TNEG, then the network is at the maximum utilization. In a similar way, a T-pri
value can be determined for loading into a THSH register by
picking the desired load factor and determining the corresponding time value. Conversely, a time value can be
picked to determine the maximum utilization at that T_pri.

LOAD

Another fault isolation capability supported directly by the
PLAYER device is the noise timer, which detects jabber
conditions (continuous transmission) and other faults that
may occur in a system. This timer is referred to as the TNE
timer in the standard. The PLAYER device has prescale and
count registers which load countdown counters. Each Noise
Line State, Active Line State or Line State Unknown symbol
will decrement the noise counter. The noise counter is used
by the Physical Connection Management (PCM) state machine to detect the length of the noise events.
When the TNE timer threshold is exceeded, an interrupt can
be generated by the PLAYER device which causes the PCM
state machine to transition from the active to the break
state. The PLAYER device also includes hardware that implements the Link Error detector function of SMT. The
LETR and CLECR registers are also used for performing the
Link Confidence Test during link establishment.
5.0 NETWORK MONITORING
Maximum network throughput can be calculated as:
n(TTRT - Ring Latency)/(n(TTRT) + Ring Latency)

I

I
I

Lprl
I
I
I
I

L e9
I
I

ROTATION TIME
TL/F/11084-2

FIGURE 3. Asynchronous Priorities
The same basic equation (Eqn. 3) is used to monitor the
throughput of the network. Either monitoring the throughput
or setting timer parameters requires determination of the
rhig latency. The BMAC device includes hardware that performs a latency measurement of the ring. The latency of a
ring will vary slightly through expansion and contraction of
the elasticity buffers and smoothers required in PHY components like the PLAYER device, and more significantly
through stations entering and exiting the network. Therefore
periodic measurement may be necessary for network monitoring. The latency measurement, obtained through the
RLCT counter in the BMAC device, can be used in conjunction with the token counter (TKCT) to determine average
load over time. Average load is then represented by the
equation.
(Time - (Token_Ct· Ring Latency»/Time
(4)

(1)
Again

Where n is the number of stations in the network.
This basic equation can be used to determine the proper
values for TREQ. This function determines the asymptote
for network throughput. The actual utilization of the network
can be calculated as:
(3)
(TRT - Ring Latency)/TRT

For example:
(5 sec - (5000 Tokens· 150 ,",s»/5 sec = 85% Utilization

Where TRT is the actual token rotation time.
This function produces the curve shown in Rgure 2.

4-64

r-------------------------------------------------------------------~~

REFERENCES

Over a measurement period of 5 seconds, 5000 tokens
were counted in TKCT and the ring latency counter read
150 '""S. Working the formula through results in an 85% load
on the ring.
The BMAC and PLAYER devices also include required and
optional statistical counters that can be used to evaluate
traffic in terms of frames. One of the important counters
added is the Frame Not Copied (FNCT) count of the BMAC
device. This counter is very useful for evaluation of overload
on stations in a network, since it indicates inability of the
station to keep up with frames sent to it. Network managers
need this type of information for proper administration of
server stations. The BMAC device transmit and receive
frame counters (FTCT and FRCT) provide valuable traffic
information with virtually no software overhead. The error
counters in the BMAC and PLAYER devices are useful indications of error rate problems on communication links in the
ring. All of these counters are designed to simplify the implementation of station software.

1. National Chip Specifications.
2. Fiber Distributed Data Interface (FDDI)-Token Ring Media Access Control (MAC), ANSI XS.139-1987.
3. Fiber Distributed Data Interface (FDDI)-Token Ring
Physical Layer Protocol (pHy), ANSI XS.148-1988.

Z

..:..
N
C»

4. Fiber Distributed Data Interface (FDDI)-Token Ring
Physical Layer Medium Dependent (PM D), ANSI
X3.166-1990.
5. Fiber Distrubuted Data Interface (FDDI)-Station Management (SMT), X3T9.5/84-49, Rev. 6.2.
6. R. Jain, Performance Analysis of FDDI Token Ring Networks: Effect of Parameters and Guidelines for Setting
nRT, DEC-TR-655, September 1989.

III
4-65

Interfacing the HPC46064
to the OP83200 FOOl
Chip Set

National Semiconductor
Application Note 736
Simon Stanley

TABLE OF CONTENTS

2.0 FDDIINTELLIGENT STATION ARCHITECTURE
In FOOl, the Station Management (SMT) service is split into
three main sections, SMT Frame Services, Ring Management (RMn and Connection Management (CMT). Within
the National Semiconductor implementation of FOOl, any
controller handling RMT and CMT services need only access the Control Bus directly, although a communications
channel to the host is also required. An architecture using
the HPC from National Semiconductor is shown in Figure 1.
This can be implemented directly using the interface shown
in Figure 2. Using this architecture, the SMT frame services
are provided by the host.

1.0 INTRODUCTION
2.0 FDDIINTELLIGENT STATION ARCHITECTURE
3.0 DP83200 FDDI CHIPSET
4.0 HPC46064 HIGH PERFORMANCE
MICROCONTROLLER (HPCTM)
5.0 CONTROL BUS INTERFACE

1.0 INTRODUCTION
Fiber Oistributed Oata Interface (FOOl) is a high bandwidth
(100 Mbits per second) local area network (LAN) which
uses a dual redundant ring architecture. The network consists of a number of pOint to point links connected to form a
. ring. The physical and electrical characteristics of the ring
protocol are covered by the Physical Media Dependent
(PM D), Physical (PHy) and Media Access Control (MAC)
Standards as defined by the American National Standards
Institute (ANSI) X3T9.5 committee, and can be implemented
using the OP83200 FOOl chipset from National Semiconductor. The on-line verification of these point to point links,
and the formation of a ring is covered by the FOOl Station
Management (SMn Standard.
This application note covers the use of the HPC46064 High
Performance Microcontroller from National Semiconductor
to provide the local processing power required within a Fiber
Distributed Oata Interface (FOOl) node for Station Management (SMn. The note covers the interface between the
HPC and the FOOl chipset from National Semiconductor
and a possible system architecture.

The architecture shown is one of several that could be implemented with the HPC and the National FOOl chipset.
This architecture connects the HPC multiplexed address/
data bus to the control bus of the FOOl devices, allowing
the HPC to access these devices directly with single instructions. The 16 Kbyte ROM of the HPC46064 is used to minimize chip count, though this architecture allows external
ROM or RAM to be used if additional functions are implemented.
The HPC has sufficient performance to handle all of SMT,
including frame based management, but this would require
that the HPC have access to the frame buffer memory. This
requires an arbitration scheme to resolve conflicts between
the host and the HPC in accessing the buffer RAM. The
arbitration scheme could be simply implemented using the
HOLD and HLOA (Hold Acknowledge) pins of the HPC.
An advantage of putting all of SMT on the board is that the
SMT function need not be resident in the host memory. The
removal of TSRs or daemons from host memory leaves
more room for applications.
An alternative architecture would run the HPC in single chip
mode, reducing the chip count and allowing the Universal
Peripheral Interface (UPI) port to be used as the host interface. This would require software drivers to simulate the
FOOl control bus signals using the 1/0 ports of the HPC.

4-66

INTERRUPT
TO HOST

INTERRUPT
FROM HOST

HOST SYSTEM BUS

Station Management (SMT) Task Allocation
SMT Frame Services

HOST

Ring Management (RMT)

HPC

Connection Management (CMT)

HPC

To Fiber Optic
Transceiver
TUF/lll03-1

FIGURE 1. FDDI Station Architecture Using HPC for Partial Station Management

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TUF/lll03-2

FIGURE 2. HPC to FOOl Chipset Interface

3.0 DP83200 FDDI CHIPSET
The DPB3200 FDDI chipset from National Semiconductor
implements the PHY and MAC Standards as defined by the
American National Standards Institute (ANSI) X3T9.5 com·
mittee. The chipset includes the following devices.

The HPC46064 features include 16 bit internal architecture,
16- or B-bit external data bus, 16 bit address and up to 52
general purpose I/O lines. The HPC46064 also includes a
full duplex UART, four 16-bit timers, 16 Kby1es of ROM and
512 by1es of RAM.
The HPC46064 is used in this design because its 16 Kbytes
of on-Chip ROM remove the need for an external EPROM.
For prototyping or small production runs the pin compatible
HPC467064 may be used, which has 16 Kbytes of on-Chip
EPROM.
Devices in the HPC family can directly address 64 Kbytes of
external memory. This address range can be expanded to
over 500 Kbytes without additional devices by using I/O
pins to implement a simple bank switching technique.
This additional addressing range may be needed if the HPC
implements the whole SMT function. The HPC development
tools support this bank switching technique, allowing this
low-cost microcontroller to handle the whole SMT function
while minimizing the software development effort.
The performance of the system will not be affected by using
this bank switching approach because many of the SMT
functions are never performed simultaneously. The HPC
could, for example, run the Physical Connection Management (PCM) from one memory bank, then switch to the bank
containing the frame-based management functions at its leisure.

DP83231 Clock Recovery Device (CRDTM DEVICE)
The Clock Recovery Device extracts a 125 MHz clock from
the incoming data of the upstream station. Its features in·
clude on-chip loop back control, on-chip PLL, ability to lock
to a Master Line State in less than 100 p's, and a Single
+5V supply.
DP83241 Clock Distribution Device (CDDTM DEVICE)
From a 12.5 MHz reference. the CDD generates the
125 MHz, 25 MHz and 12.5 MHz clocks required by the
PLAYERTM and BMACTM devices.
DP83251/DP83255 Physical Layer Controller
(PLAYERTM DEVICE)
The PLAYER device converts the BMAC 12.5 Mby1e/s
stream into a 125 Mbaud 4B/5B encoded bit stream as
specified in the FDDI PHY Standard. It synchronizes the
received bit stream to the local 12.5 MHz clock and decodes the 4B/5B data into internal code. The DPB3255
PLAYER device also contains a configuration switch for use
in dual attachment stations and concentrators.
DP83261 Basic Media Access Controller (BMACTM
DEVICE)
The BMAC implements the functions defined by ANSI
X3T9.5 FDDI Media Access Control Standard. The BMAC
consists of the transmit and receive state machines, an address magnitude compare unit, a CRC checker, a CRC generator, protocol timers and diagnostic counters.

5.0 CONTROL BUS INTERFACE
The FDDI chipset from National Semiconductor provides
the PHY and MAC services as detailed in the FDDI Standard. The chipset does not provide the Station Management
(SMT) services, but does provide access to all the necessary data through a large array of B-bit registers located onboard the PLAYER, BMAC, and BSI devices. The interface
to these registers is via the Control Bus defined in the data
sheet for the BMAC Device (Media Access Controller). The
interface consists of an B-bit address bus, B-bit data bus
and several control lines. The control lines consist of a read/write Signal, a chip enable signal and an acknowledge
signal. There is also an interrupt signal and a parity bit,
which for this application, has been disabled. The interrupt
signal and the acknowledge Signal are open drain signals
and can be wire-ORed.

DP83265 BMAC System Interface (BSITM DEVICE)
The BSI device provides a multiframe, multiple channel interface between the BMAC device and a host system. The
BSI device interfaces directly to the system bus or through
low-cost DRAMs. The efficient data structures employed
provide high throughput with minimal host intervention.
For more information on these and other devices in the
chipset please consult the appropriate data sheets and application notes.

A transfer cycle on the bus is started when the processor
drives the Chip Enable (CE) signal low. Within 20 ns, the
data (write cycle only), address and read/write signals must
all be valid. The device being accessed will respond by driving the Acknowledge (ACK) Signal low when data is valid
(read cycle) or when the data has been clocked in (write
cycle). The processor can now end the transfer by driving
CE high and the device will complete the cycle by driving
ACK TRI-STATE®.

4.0 HPC46064 High Performance Microcontroller
(HPC DEVICE)
The HPC46064 is a member of the HPC family of High Performance Microcontrollers. Each member of the family has
the same core CPU with a unique memory and I/O configuration to suit specific applications. The HPC46064 has
16 Kby1es of on-chip ROM and is fabricated in National's
microCMOS technology. This process combined with the
advanced architecture provides fast, flexible I/O, efficient
data manipulation, and high speed computation.

4-69

U)

~

z•

c(

r---------------------------------------------------------------------------------,
No pOlling of the Control Bus is required as the interrupt
signals for each device are brought into the HPC separately.
A simple host interface is provided consisting of two interrupt signals and two eight bit ports, one for read and one for
write.
Device U1 is a GAL16V8 (a programmable logic device) and
performs all of the logic functions required to generate the
control signals used by this system. The programming of
this device using the ABEL language is straightforward, as
shown by Figure 5.

The HPC provides a multiplexed 16 bit bus for interfacing to
external memory. As only 8 bits are required for the Control
Bus, the interface can be achieved with minimal components (see Figure 2). The multiplexed address is latched by
the flow-through latch, US. The data bus is buffered by the
bi-directional buffer, U2, which is enabled whenever either
read or write signals is asserted by the HPC. The direction is
controlled by the Write (WR) signal. Two chip enables are
provided (PCE and BCE) by decoding the read, write and
upper address bits. The chip enables are delayed until the
next Clock (CK2) falling edge so that during a write cycle,
the data is available within 20 ns of the chip enable. The
Ready (ROY) signal forces the HPC to insert wait states
until an ji£j( is received from the Control Bus. (See Figures
3 and 4 for interface waveforms.)

TA
CKI
CK2
ALE
AD-IS
iW

WR

~~~~;(~:::==========C=ON=TR=O=L=BU=S=A=OO=R=ES=S~VA=l1=D==~~~~~~~~~~~}-~
CONTROL BUS DATA VALID
}--

CBA(0-7)
CBD (0 -7) :

~

\~--------~--------------------------~I
FIGURE 3. Control Bus Interface READ Cycle

4-70

TLlF/lll03-3

TA

TW

CK1

CK2

ALE

AO-15

iW
ViR
iffiY

CE
ACK

CBA(0-7)

CONTROL BUS ADDRESS VALID

CBD(0-7)

CONTROL BUS DATA VALID

BOE

\

/
TLlF/11103-4

FIGURE 4. Control Bus Interface WRITE Cycle

Title 'HPC to C Bus Interface
Simon Stanley
National Semiconductor 12 Dec. 1990
UOl
device 'GAL16V8';
CK2,WR,RD,ACK
pin 2,3,4,8;
A15,A14,A13
pin 5,6,7;
RDY,NCK2,PCE,BCE, BSICE, BOE
pin 18,19,16,17,14,15;
Address = [A15,A14,A13,x,x,x,x,x,x,x,x,x,x,x,x,xl;
equations
!PCE := (!RD# !WR) II: (Address >= h8000) II: (Address <= h9FFF) ;
!BCE := (!RD# !WR) II: (Address >= hAOOO) II: (Address <= hBFFF) ;
RDY = (WR II: RD)# !ACK;
!BOE = !WR# !RD;
NCK2 = !CK2;
FIGURE 5. ABEL Source File for HPC FDDllnterface PAL

4-71

BMACTM Device Software
Design Guide

National Semiconductor
Application Note 678
David Brief

Table of Contents

1.0 INTRODUCTION
This application note describes how to initialize the BMAC
device and what to do while it is inserted in a ring. The
software support to implement the Media Access Control
(MAC) level protocol and the necessary services to a Sta·
tion Management (SMn entity in an FDDI node are de·
scribed. The necessary data service support for transmitting
and copying frames is not covered in this application note.
The MAC protocol and all of the services required by SMT
(except the SMT data services) are supported through the
BMAC device's Control Interface. The processor running
this software must have access to the Control Bus and have
the ability to respond to interrupts.

1.0 INTRODUCTION
2.0 CONTROL SERVICES
3.0 INITIALIZATION PROCEDURE
3.1 Put the BMAC Device in Stop Mode
3.2 Load the MAC Parameter RAM
3.3 Clear the MAC Event Counters
3.4 Clear the Event and Mask Registers-Optional
3.5 Modify the Timer Thresholds-Optional
3.6 Set the Option Register

2.0 CONTROL SERVICES
The Control Services provided by the BMAC device are accessed through the Control Interface. A more detailed de·
scription of the facilities and services provided by the BMAC
device is given in the BMAC device datasheet.

3.7 Set the Mode Register
3.B Loopback Testing-Optional
4.0 DURING OPERATION

The BMAC Control Bus address space is divided into 4 ad·
dress ranges:
The Operation registers control the current mode of opera·
tion of the BMAC device (Run/Stop, Internal Loopback) in·
cluding the options that are being used (Short/Long Addressing, MAC state machine options). In addition several
functions may be initiated (Master Reset, MAC Reset,
Claim, Beacon).
The Event registers record the occurrence of events which
may cause interrupts (each event bit has a corresponding
mask bit). These include Ring, Token and Counter Incre·
ment/Overflow Events.

4.1 Control Interface Event Registers
4.2 Event Control
4.3 Servicing Interrupts
4.4 Event Counters
5.0 EXAMPLE PROCEDURES
5.1 Getting the Ring Operational
5.2 Receiving and Copying a Frame
5.3 Initiating Claim
6.0 DIAGNOSTIC SCENARIOS

The MAC Parameter RAM contains all of the MAC related
parameters such as this station's long and short addresses.
The MAC Counter/Timer Thresholds contain the event
counters (Frame, Error, Lost, Copied, Not Copied, Transmit·
ted, Token) in addition to the programmed thresholds for
the various MAC timers such as TMAX and TVX.

6.1 For (At Least) One Station
6.2 For Two or More Stations
6.3 Path Tests

The various ranges may be accessed for reading and/or
writing either always or only in stop mode as shown below.

Address Range

Description

00-07
OB-2F
40-7F
SO-BF

Operation Registers
Event Registers
MAC Parameter RAM
MAC Counters/Thresholds

ReadCond
always2
always2
stopl,3
always

WriteCond
always2
always (Cond)2
stop1,3
stop1

Nota 1: An attempt to access a currently inaccessible location because of the current mode or because it is a reserved address
space will cause a command error (ESR.CCE set to One).
Nota 2: Read and write accesses to reserved locations within the Operation, Event Address ranges cause a command error
(ESR.CCE set to One).
Note 3: The MAC Parameter RAM is also accessible when:
a) the MAC Transmitter Is In states TO, Tt or T3;
b) Option.ITC and Optlon.lRR are set
c) Function.ClM and Function.BCN are not set otherwise accesses will cause a command error (ESR.CCE set to One).
Nota 4: Reserved bits In registers are always read as 0 and are not writable.

4-72

Determining TREQ
TREQ is this MAC's requested value for the token rotation
time, I.e., in the worst case, this station wants to "see" a
token at least once every 2"TREQ. For example if a station
wanted to be guaranteed to capture a token every 2 ms it
would set TREQ to 1 ms.
1 ms is 12,500 ticks of the 80 ns clock or 3004 hex. Subtracting this from 1-0000-0000 yields. FF-FF-CF-2B for
TREQ since TRT is an unsigned twos complement up counter.
Since the least significant byte of TREQ is transmitted as 0,
the value should be rounded up in order to guarantee that
this station will see the token as often as it needs to. In this
case TREQ would be written to FF FF 00 00.

3.0 INITIALIZATION
Before being inserted into a ring, the BMAC device must be
initialized. To initialize the BMAC device the following steps
should be followed. Each action is explained further below.
Put the BMAC device in Stop Mode
Load the MAC Parameter RAM
Individual Addresses (MLA, MSA)
Group Addresses (GLA, GSA, MAP, SGM)
Requested Token Rotation Time-TREQ
Beacon Information-TBT
Clear the MAC Event Counters
Clear the Event and Mask Registers-Optional
Modify the Timer Thresholds-Optional
TVX
TMAX
Asynchronous Priority
Set the Option Register
Set the Mode Register
Loopback Testing-Optional

Beacon Informatlon-TBT
TBT(31 :0) should be loaded with 00 00 00 00.
This is only modified in the case of specialized Beacon
Frames. Additional Beacon frames are being defined by the
FOOl standards committee.
The BMAC device has two limitations on the Beacon
Frames it can transmit. Firstly, only frames with a Null OA
with four bytes of information are transmitted by the BMAC
device. This precludes the use of the internally generated
Beacon Frames for the directed Beacon because it can not
be sent to the SMT multicast address. Secondly the size
restrictions on Beacon Frames also preclude their use for
conveying useful information. The Beacon Frame is the penultimate immediate transmission. (Blocking the MAC Indication Input with Option.IRPT will allow transmission of Beacon Frames in the presence of an upstream Beaconer.)

3.1 Put the BMAC Device in Stop Mode
The Mode Register is programmed first to place the BMAC
device into STOP mode so that all registers can be accessed.
The Parity for the different interfaces is enabled here as is
the ability to be in MAC Loopback. At Initialization it doesn't
matter if the part is configured in loopback, but since loopback testing will probably be done after initialization it could
be set now as well.
In a system without parity checking on the Control Bus or
the MAC Interface the Mode register would be set to 44h.
This enables the parity checking on the PHY interface which
is actually part of the Ring. (Parity is always generated by
the BMAC device to the PLAYERTM device.)

3.3 Clear the MAC Event Counters
The counters are 20-blt counters, but SMT requires 32-blt
counters. This implies that the upper 12 bits are maintained
by software.
In order to use the low order bits directly without having to
calculate how much they have changed since the last time
they were read, the counters should be cleared at initialization.

3.2 Load the MAC Parameter RAM
Load RAM with values as indicated in the following passages.
Individual Addresses (MLA, MSA)
MLA-the 48-bit address
MSA-the 16-bit address-Optional

3.4 Clear the Event and Mask Reglster&-Optlonal

Group Addresses (GLA, GSA, MAP, SGM)
The same MAP is used for the short and long group addresses. To disable Group Addressing, GLA and/or GSA
must be set to all ONE's.
Long Addresses-GLA plus MAP (Optional)
Short Addresses-GSA plus MAP (Optional)
Fixed Group Address-FGM(15:1) This is located at FF
(FF FF FF FF) Ox where the last nibble is fanned out
using the Fixed Group Map (SGM).
The Broadcast Address-FGM(O) must be set to One
in order to participate properly in the Next Station
Addressing protocols that rely on the Broadcast
Address.

The Event and Mask registers are actually cleared on a
Master Reset. If you did not do a Master Reset before the
initialization sequence it is good practice to clear these registers.
3.5 Modify the Timer Threshold&-Optlonal
At Master Reset the timer thresholds are set to the defaults
recommended by the standard. In most applications there is
little incentive to modify the defaults.
TVX
In most applications, the valid transmission timer, TVX,
would remain at its default value. The value of TVX determines in how long a valid transmission should be seen. If a
valid frame is not seen in this period of time the Claim process is started. This is one of the recovery required conditions.

Requested Token Rotation Time-TREQ
This should be loaded with FFOOOOOO unless this station is
using/managing Synchronous Bandwidth.
When this station is using Synchronous Bandwidth and
needs a faster average response time for its Synchronous
Bandwidth, the value of TREQ is used in the Claim process
to negotiate the target timer rotation time.
If this station wins the Claim process, every station will use
this station's value of TREQ as TNEG.

II
4-73

co

~
Z

Z
I

CJ)

......
co

Example Interrupt Service Routine
1. Disable Interrupts
2. Determine which event is triggering the interrupt
3. Determine which condition(s) exist that need(s) attention

After a conditional write register is read, if another conditional write register is read before a condition is cleared, the
compare register will no longer have the appropriate value
in it. In such cases the compare register should be written
with the previously read value of the register.

a. Read ICR
b. Read appropriate Condition Register
4. Process event
a. Complete Processing for the event or

The compare register may also be useful for software compare/update sequences and for diagnostic purposes.

b. Queue a process to handle the event
5. Clear or Mask the condition
a. To Clear:
i. Will only clear conditions that have not changed
since last read
ii. Make sure that last value read is in the Compare
Register
b. To Mask:
i. Clear the appropriate Mask Bit
ii. Before the Mask Bit is set to reenable interrupts, the
condition must be cleared as shown above.
6. Reenable interrupts
Additional Notes
1. Nesting of Interrupts:
Nesting of interrupts may be of use in driver level software.
For example if an error condition occurs while "processing"
a frame it may be prudent to stop processing the frame and
handle the error condition. Alternatively, once processing of
frames begins, it may not be necessary to reenable frame
related interrupts until all copied frames have been processed. This is especially true with token ring protocols where
bursts of frames between stations is common (or at least
should be common to optimize performance of the media
and the software. Software performance would be increased because the software performance can be related
closely to the number of interrupts that need to be processed).
2. Conditional Writes:
In the period between the Read of a condition latch register,
and the corresponding Write to reset the condition, additional events could occur. To prevent the overwriting and consequent missing of events, an interlock mechanism is used.
Whenever a condition latch register (RELRO, RELR1, TELR,
GILR, COLR, or ESLR) is Read, its contents are stored in
the Compare Register.
Each bit of the Compare Register is compared with the current contents of the register that is to be written. For any bit
that has not changed, the new value of the bit is written into
the register. For any bit that has changed the writing of the
bit is inhibited. This prevents the software from overwriting
bits which have changed since the last read and losing interrupt events. The fact that an attempt was made to modify
a changed bit in the register is latched in the Conditional
Write Inhibit bit of the Exceptional Status Register
(ESR.CWI). This bit is written unconditionally after each
write to a conditional write register. This is different than in
the PLAYER device.
The Compare Register may also be written unconditionally
by software. There is a single compare register for all of the
conditional write registers in the BMAC device. This is different than in the PLAYER device where each conditional write
register has its own compare register.

4.4 Event Counters
The event counters are 20-bit counters, but the SMT MIB
and SMT frames requires 32-bit counters. This implies that
the upper 12 bits are maintained by software.
The counters may be read either periodically or upon an
event. The fact that individual counters incremented or
overflowed is reported as an event in the GILR or GOLR
event registers respectively.
In order to use the low order bits directly without having to
calculate how much they have changed since the last time
they were read, the counters should be cleared at initialization.
Some uses of the counter may require that a consistent
value be obtained across two counters. Since the event that
a counter incremented is stored, software can tell if a consistent reading was obtained.
When reading individual counters, the upper 12 bits of the
counter are latched when the low order 8 bits are read. This
allows consistent readings of a single counter and implies
that the low order byte must be read first.
At least one of the event counters is incremented for every
Starting Delimiter (JK) received.
After a Starting Delimiter (JK) is detected:
If Token Ending Delimiter-Increment Token Count
(or) If Format Error-Increment Lost Count
(or] If Frame Ending Delimiter-Increment Frame Count
If Er = Rand FCS error detected-Increment Error Isolated Count
Else If AFLAG and VCOPY-Increment Frame Copied
Count
Else If AFLAG and not VCOPY-Increment Frame Not
Copied Count
5_0 EXAMPLE PROCEDURES
5_1 Getting the Ring Operational
To get the ring operational requires setting the Run bit in the
Mode Register to a ONE. Once TVX expires, the Claim process will be entered, and if a single token path exists, the
Claim process will quickly complete, a token will be issued
and the ring will become operational. This occurs even
when in internal loopback.
e.g.:
- Set Mode.Run = 1.
-

4-76

TVX will soon expire causing entrance to Claim.
Claim will resolve and a token will be issued.
The reception of a valid token causes the ring to become operational.
Once the ring is operational the station should check to
make sure that TNEG > T min to ensure that it can operate on the ring as an equal station (if this is not true it
may be denied service for excessively long periods of
time).

.---------------------------------------------------------------~~

5.2 Receiving and Copying a Frame
All frames are received by the BMAC device, but only
frames addressed to this station are copied. Every frame
received by this station causes the frame received counter
to be incremented. In addition for frames addressed to this
staion (when the A flag is set) either the frame copied
(FRCOP) or frame not copied (FRNCOP) bit is set and the
appropriate counter is incremented.
e.g.:
-

CILR.FRCOP is set indicating that a frame was copied
by external_logic

-

Can be used to wake up driver software

-

Software that receives this interrupt should
• Process the Frame Status
• Process some of the frame
• Pass remainder of frame to another process to be processed

5.3 Initiating Claim
- Enter stop mode (this breaks the ring)
Load a new value of TREO into the parameter RAM.
Load TNEG with TMAX.

-

Clear the events related to claim in RELRO and RELR1
Enter run mode.
Initiate the claim process by writing the Function Register with 14.
Wait until Function Register is zero.

-

Check that TNEG :<: TREO when claim completes.
See if this station won claim:

6.1 For (At Least) One Station

z

a,
.....
00

Control Interface Checkout
Internal Frame Generation Tests
State Machine Sequencing Tests
External Frame Transmissions
Test of Token Timers
Test of Transmission Options
Full Duplex Operation
6.2 For Two or More Stations
Beacon Scenarios
Claim Scenarios (Need Three To Do Complete Testing)
Duplicate Token Conditions
Duplicate Address Conditions
Abnormal Frame Termination (Format Errors. FCS Errors.
etc.)
6.3 Path Tests

-

-

6.0 DIAGNOSTIC SCENARIOS

A path test is performed to determine that everything is
working in that path. By doing successive path tests on
parts of the same path, the Fault Domain can more accurately be determined (i.e., which chip/connector is broken).
The fact that the chip set is full duplex greatly aids the path
tests. This allows identical tests to be run at all levels.
Paths that can be tested in a node:
Through the BMAC Device
Through All of the Station Paths
Through the CRD device for SAS and through Each CRD
device for DAS and Concentrators
Through Every Station on the (Logical) Ring

• See if RELR1.MYCLM is set
• If set see that TNEG = TREO.

II
4-77

BMACTM Device Hardware
Design Guide

National Semiconductor
Application Note 689
David Brief

Introduction

ring of stations. CLAIM, BEACON and Void frames are generated by the Ring Engine when appropriate. The Ring Engine transmits, strips or repeats Protocol Data Units (PDUs~
i.e., Tokens and Frames) and handles the token management functions required by the timed token protocol in accordance with the FDDI MAC standard.
On output (to the ring), interface logic prepares one or more
frames for transmission and requests a service opportunity.
Based on the requested service class and requested token
type, the Ring Engine waits for a token meeting the requested criteria. When a token is captured, the Ring Engine signals the interface and soon thereafter transmission begins.
After traversing the ring, frames are stripped based on the
Source Address. Frames with a Source Address matching
one of the station individual addresses are stripped by the
Ring Engine. Status is available at the MAC interface for
every transmitted frame.
On input, the Ring Engine sequences through the incoming
byte stream, comparing against the station short or long
addresses. The results of these comparisons are made
available at the MAC Interface. Interface logic then decides
how to handle the frame. In the normal case, a frame with a
Destination Address matching one of the station addresses
is copied and passed to the system.

The BMAC device provides the basic facilities required to
implement the Media Access Control functions required by
the ANSI X3T9.5 FDDI MAC standard. This document describes how to use the BMAC device to implement the MAC
level functionality required by stations in an FDDI network.
A short overview of the BMAC device is given followed by a
discussion of design considerations and tradeoffs for using
the BMAC device.
Familiarity with the ANSI standard and BMAC Device Datasheet is recommended before using this document.
The state machines and timing shown in this document provide illustrative examples only. Should there be a descrepancy, the BMAC Device Datasheet is the overriding authority.

Table of Contents
1.0 OVERVIEW
2.0 CONTROL INTERFACE
3.0 PHY INTERFACE
4.0 MAC INTERFACE
5.0 BRIDGING/EXTERNAL MATCHING SUPPORT

1.0 Overview
The BMAC device interfaces to one or more PLAYERTM
components, a Control Bus and to external logic that tunes
the MAC interface to the requirements of the system.
The BMAC device is comprised of the Ring Engine, the PHY
Interface, the Control Interface and the MAC Interface as
shown in Figure 1.
The BMAC device utilizes a full duplex, byte wide (symbol
pair) architecture. There are two bytes of delay in the transmit path, and three bytes of delay in the receive and repeat
paths. Two bytes of delay are present in the loopback path.
1.1 RING ENGINE
The Ring Engine implements the FDDI MAC protocol for
transmitting, receiving, repeating and stripping frames in a

1.2 CONTROL INTERFACE
The Control Interface implements the interface to the Control Bus by which to initialize, monitor and diagnose the operation of the BMAC device. The Control Interface of the
BMAC device is identical to the control interface of the
PLAYER device. Typically, all of the BMAC and PLAYER
devices within a station will all be addressable on a shared
Control Bus.
1.3 PHY INTERFACE
The PHY Interface provides a byte stream to the PLAYER
device (PHY Request) and receives a byte stream from the
PLAYER device (PHY Indication). The Configuration Switch
in the PLAYER device allows the BMAC device to be
switched into the Primary and Secondary rings as desired.

MAC Indication

PHY Indication

PHY Request

FIGURE 1. BMAC Device Block Diagram

4-78

TL/F/10825-15

1.4 MAC INTERFACE
The MAC Interface provides the interface to external buffering and control logic. A byte stream is provided to interface
logic with appropriate control signals (MAC Indication), and
a byte stream is provided to the BMAC device with appropriate handshake control signals (MAC Request).

ported in an Event Register). This means that all Control
Interface accesses complete in a deterministic amount of
time. This can be useful in the design of certain interfaces to
simplify synchronization circuitry. The Exceptional Status
Register must be checked to insure that the operation terminated normally.
The registers accessible through the Control Interface maintain the Operation, Event, Status and MAC Parameters.
The Operation Registers are used to control the operation
of the BMAC device. The Operation Registers include the
Mode, Option and Function Registers. The Mode Register
determines the current operational mode (run/stop, loopback, etc.). The Option Register determines how the BMAC
device will work while in run mode. The Function Register
initiates functions and provides polled status on their completion. These include a Software Master Reset, a MAC reset and the CLAIM and BEACON requests.
The Event Registers are used to report the occurrence of
events. The Event Registers are used to generate interrupts
when selected conditions occur (under program control).
The Status Registers are used to access either current
status or long term status from event counters.

It is the job of the external interface logic to transform the
byte streams to and from the BMAC device to implement
the data services required by the system interface.

2.0 Control Interface
The Control Interface provides an a-bit asynchronous interface to the Control Bus. Through the Control Interface, access is provided to all internal registers. These registers
control the operation of the BMAC device as described below. The interface to the Control Bus is identical to that of
the PLAYER device.
The Control Interface provides the synchronization between
the asynchronous Control Bus and the synchronous operation of the Ring Engine. The Ring Engine is a synchronous
device running exclusively on the 12.5 MHz Local Byte
Clock and the in phase 25 MHz Local Symbol Clock.
FDDI components within a station will typically share the
same Control Bus. The processor on this bus may be a
dedicated microcontroller that is running time critical portions of SMT (i.e., CMT), or it may be a more general purpose microprocessor which gets called on to handle interrupts.

The Parameter Registers are used to set up parameters
used by the Ring Engine such as the station's address and
the group address maps.

3.0 PHY Interface
The PHY Interface provides the data paths to connect the
BMAC device to one or more PHY Layer devices. The interface is synchronous; with every rising edge of the Local
Byte Clock ten bits are transferred in each direction-from
the BMAC device to the PLAYER device on the PHY Request Interface and from the PLAYER device to the BMAC
device on the PHY Indicate Interface. The elasticity buffer of
the PLAYER device removes the asynchronous element
from the data stream and allows the BMAC device to work
as a synchronous device with synchronous interfaces.
One BMAC device may drive one or more PLAYER devices
while only one PLAYER device should be driving the BMAC
device at any given time. TRI-STATE® control and pullups
are provided within the PLAYER device to allow several
PLAYER devices to share one PHY Indicate Bus. This is
very important in most Dual Attach and many Concentrator
configurations.

The Control Interface is separated completely from the
MAC Interface in order to allow the data paths to run at full
speed and not be shared with the slower control transfers.
Access to registers may occur simultaneously with the data
transfer.
All communication that is not synchronized with the (high
speed) data services uses the Control Interface. For example, error conditions are reported through the Control Interface, while frame reception status is reported at the MAC
interface synchronized with the data stream. Likewise, options for frame transmission that can change with every
frame are submitted to the interface with every frame.
All events are latched in condition latch registers, and may
generate interrupts. Only enabled events may generate interrupts. Events are reported through a two level logical hierarchy. Events are grouped into classes according to their
probable usage. Each event of a class may be enabled individually in the mask registers and event classes are enabled
via mask registers at the Interrupt Register.
Conditions are used to signify that an event or series of
events has occurred. The Interrupt signal becomes active to
notify the managing entity that a condition or set of conditions exist.
All of the events suggested by the MAC standard are reported by the BMAC device. In addition, the BMAC device provides events on each counter increment and overflow.
The Control Interface also manages access to shared registers. Certain Status and Parameter Registers are not accessible while in Run mode because the Ring Engine may be
accessing those locations. All Control Interface accesses
are checked against the current operational mode to determine if the register is currently accessible. If not currently
accessible, the Control Interface access is rejected (and re-

FDDI uses a 4B/5B symbol encoding scheme that is normally byte aligned. The PLAYER device aligns starting delimiters of all PDUs to the byte boundary. This allows the
BMAC device to detect the JK starting delimiter as a single
code point and greatly simplifies the alignment issues. The
BMAC device aligns delimiters of all transmitted or repeated
PDUs to the byte boundary.
The 10 bits transferred with each clock consist of B bits of
data and one bit of control to say if the data represents a
data code pOint or a control code pOint. Mixed data/control
symbol pairs are encoded to a set of control code pOints
with the data being given as zero regardless of the actual
data symbol value. Odd parity is also provided with every
byte.
Through parity is important in this path because every station's data goes through this path. Parity errors detected in
the MAC are treated as all other code violations (format
errors).

4-79

4.0 MAC Interface

INFORCVD when the fourth byte of the Info Field is on MID
until the next JK

4.1 OVERVIEW

Not all of the Signals would be used by a typical implementation. The sequencing signals are reset on a Master Reset.

The BMAC device is partitioned at the MAC Interfaces to
allow a full spectrum of system interface organizations. We
discovered early on that it would be difficult, if not impossible to develop an interface that met cost and performance
goals for all potential uses of FDDI. However, in crafting the
MAC Interface, we did not just guess what a good interface
would include. We modeled a complete System Interface
Architecture including a real time multi-tasking operating
system at the register transfer level on top of the MAC under the assumption that all lower performance interfaces
would be some subset of a very high performance interface
architecture.

One of these Termination Event Signals is asserted at the
end of every PDU as described below:
EDRCVD

when the Ending Delimiter of a frame is on MID
until the end of the Frame Status (typically asserted for two byte times)

TKRCVD

when the Ending Delimiter of a token is on MID
for one byte time

FRSTRP

when the first Idle byte of a stripped frame is on
MID

FOERROR when the byte with the format error is on MID

The MAC Interface provides independent Indication (receive) and Request (transmit) Interfaces. Separate signals
for control and data are presented at the interface to allow
overlapping/pipelining of data and control (status/ command) processing. A byte stream is transferred in each direction. On input, the MAC Indication Data byte stream
(MID(7:0» is handled by interface logic using the provided
sequencing and status signals. On output, the MAC Request Data byte stream (MRD(7:0» is generated by interface logic and passed through the BMAC device to the ring
on a service opportunity.

MACRST

The Flags provide the input for potential copy criteria and
status breakpoints as follows:

The interface is synchronous using the 12.5 MHz Local Byte
Clock (LBC). All Outputs change and all Inpuls are latched
on the riSing edge of LBC.

AFLAG

Internal DA Match (Short/Long: FCSL); Individual/Group: DIAG): Valid with DARCVD.

MFLAG

INTERNAL SA Match (Short/Long: FCSL); Valid with SARCVD

SAMESA

SA Same as in previous frame: Valid with
SARCVD on non-MAC frames.

SAMEINFO First four bytes of Info same as in previous
frame; Valid with INFORCVD on MAC frames.
VDL

Valid Data Length; Criteria-more than the
minimum number of bytes and an integral number of symbol pairs: Valid with EDRCVD.

VFCS

Valid FCS: Criteria-received FCS matches
with standard CRC polynomial: Valid with
EDRCVD.

The remainder of this section describes the structure of the
MAC Interface.
4.2 MAC INDICATION INTERFACE
Overview
Every byte of all incoming frames is presented at the MAC
Indication interface. The MID byte stream is effectively a
three byte time delayed version of the PID byte stream. Sequencing signals and addressing flags are provided to help
make the decision of whether or not to (continue to) copy
the frame.

Nate: The Flags are only valid when the corresponding sequencing Signal is
also set.

For setting the outgoing control indicators, the interface accepts the following:

The Sequencing Signals are asserted at different paints
within the frame. They are asserted under the following conditions:
when the Frame Control Field is on MID

DARCVD

when the last byte of the DA is on MID until the
next JK

SARCVD

when the last byte of the SA is on MID until the
next JK

EA

For external address matches for the setting
of the A Indicator (Bridging Group addressing,
Aliasing)

VCOpy

For the setting of the C Indicator

When AFLAG or EA is set and the EMIND bit of the Option
Register is set, the frame copied counter or the frame not
copied counter will be incremented depending on the value
of VCOPY for all repeated frames.

RCSTART when the Starting Delimiter is present on MID
FCRCVD

when a MACRST occurs or BMAC device is in
Stop Mode

Ten MAC Indication Timing Examples are shown in Figures

2-11.

4-80

LBC
MID IDLE
RCSTART

FCRCVD

FCSL

DAIG

IDLE

IDLE

IDLE

:JK

,'FC

pAO

OAI

SAO

(AI

INFOO

INF'01

INF'02

I~F'03

:::::::i:::

'ED

rs

10LE

------~Il

IDLE

:::::: IDLE

:JK

FC

~

--------~~r-1

r-l

~'_~ NEW ~ALUE

I NEW VALUE

------

--,

,

----,

DARCVD

AFLAG

1--vAliD

---~

SARCVD

.".

~

MFLAG

VALID

SAMESA

VALID

-----,

-~

INFORCVD

SAMEINFO

EDRCVD

I

VAUD

------------~~--~~------~----------~----;i=~:UD~i

lED

Irs

EA
VCOPY

I

VALID

I

VFCS

VALID

VOL

IVAUD

~
TL/F/10825-1

FIGURE 2. MAC Indication Timing Example-Short Frame

6S9"NV

iii

AN-6S9

LBC

.

MID IDLE

RCSTART

.......,......., .............................................................................................................................................. .....
IDLE

IDlE

IDlE

JK

n

Fe

DAO

~

H
,
,

F'CSL

I

DAIG

DAI

DA2

0A3

DA4

DA5

SAD

SAl

SAl

SA3

SA-4

SAS

!Hroo

INFOI

IHF02

INF03

ED

FS

FS

IDlE

: JK

: Fe

rL

'

~
,
NEW VAlUE

, NEW VALUE

~

DARCVD
AFLAG

:::::: IDlE

VAUD

----- ,

~

SARCVD

MFLAG

VAUO

SAMESA

VAUO

.j>.

Co

I\)

~

INFORCVD

SAMEINFO

EDRCVD

fV!U0-:-________~------.;,...--..,;.....JI

-

ED

'"

1______

'" ..

Sl

EA

~

vrcs

I -VAliD

VOL

VAlID

----,

TL/F/10825-2

FIGURE 3. MAC Indication Timing Example-Long Frame

LBC
MID IDLE

IDLE

IDLE

IDLE

RCSTART

: JK

n

:rc

~Al

pAO

DA2

DA3

OM

:IDLE

:IDLE::::::::::

IDLE

: JK

o

H

rCRCVD

,

rCSL

:rc

n0

h

,

0

NEW ,VALUE

DAIG

NEW VALUE

nl--------...;_-.--

rRSTRP

TLiF/1DB2S-3
Note: FRSTRP may be asserted any time after ReSTART; All signals are held at their current value until the next ReSTART.

FIGURE 4. MAC Indication Timing Example-5tripped Frame before SA

f"

LBC

'"

MID

a>

RCSTART

rCRCVD

rCSL

IDLE

IDLE

IDLE

IDLE

o

n
o

JK

o
o

Fe

'DAD

DAl

DA2

DA3

DA4

'DA5

SAO

SAl

SA2

SA3

SA4

'IDLE

n

IDLE

o

o

JK

rL
II
o

I NEW VALUE

I NEW VALUE

DAIG

---- --

L.:

DARCVD

~
rRSTRP

IDLE

~

~~~

1

____________~______________~f-l~______~~
TL/F/1DB25-4

Note: FRSTRP may be asserted any time afier RCSTART; All signals are held at their value until the next RCSTART.

FIGURE 5. MAC Indication Timing Example-Stripped Frame during SA

689-N'd

iii

AN·689

LBC
MID IDLE
RCSTART

fCRCVD

fCSL

DAIG

IDLE

IDLE

IDLE

JK

, Fe

______~r1,

'DAD

'DAt

DA2

CAl

DA4

'CAS

SAD

SAt

SA2

SAl

SA4

SA5

INFOO

INFOt

IDLE

'

IDLE

IDLE' JK

, Fe

~
,
,

-----------~rl

rI

--IIiEW~E

I NEW VALUE

DARCVD

f"1

AfLAG

VALID

ex>

-'"

--ll---i--

SARCVD

,

MfLAG

VAlID

SAIAESA

VALID

fRSTRP

~~~

i

__________~______________~______~r-1~______~~
TUF/l0825-5

Note: FRSTRP may be asserted any time aiter RCSTART; All signals are held at their value until the next RCSTART.

FIGURE 6. MAC Indication Timing Example-Stripped Frame after SA

LBC
~

______~rJ

MID IDLE
RCSTART

FCRCYD

IDLE

IDLE

IDLE

JK

re

DAD

-------.

-----.

OAt

DA2

DA3

DA4

DAS

----,

SAO

SAt

SA2

SA3

SA4

SAS

I

INrOD

INrOt,

NOT (DATA

'

OR 1)

---.
:::::::

IDLE

!I

FCSL

N~)ALUE

DAIG

I

DARCYD

---,----

NEW VALUE

7-'---:---!------.Jr-, ----

c"
(J1

r

AFLAG

1
1

~

SARCYD

I!-:--+_
r-VAL-ID-

MFLAG

SAMESA

FOERROR

re

r-L-

------~~~

.j>.

-.

JK

--- -

1

VALID

~

__~~________~______________~____~r-1~______~~
TUF/t0825-6

Note: FOERROR may be asserted at any time.

FIGURE 7. MAC Indication Timing Example-Format Error

689-N\f

iii

AN-689

LBC

I

L-I L-I L-I L-I
IDLE
IDLE
IDLE
: JK

MID IDLE

n

RCSTART

rCRCVD

: Fe

:DAO

:DA1

0A2

DA3

:DM

::::::: IDLE

: JK

: Fe

r-L

---------i--In

n
NEW ~ALUE

rCSL

NEW VALUE

DAIG

,
~..._ _ _ _......_.....;.._ _

MACRST*

TUF/l0825-7
Note: MACRST may be asserted if Mode Run ~ o.

FIGURE 8. MAC Indication Timing Exampl_MAC Reset

f"

g:
LBC
MID IDLE
RCSTART

rCRCVD

IDLE

IDLE

IDLE

JK

n

Fe

IDLE

IDLE

JK

Fe

r-L

n

n
I NEW VALUE (RESTRICTED/NON)

rCSL

TKRCVD

TT

___________

~nl.-...

___________

EDRCVD
TUF/l0825-8

FIGURE 9. MAC Indication Timing Exampl_Token Reception

LDC

WID IDLE
FRD

RCSTART

~
rCSL

IDLE

IDLE

IDLE

IIlLE

IDLE

IDLE

:JK

,

,: Fe

, JK

,re

,

,

-------~,

,

IDLE

n

DAD

I

ArLAG

~
.....

SAO

SAl

INfOO

INf01

INF02

INf03

SAO

~

~

~

~

~

INf04

!NrOS

iNros

INf07

INf08

INf09

ED

rs

IDLE

IDLE

IIlLE

IDLE

~

~

~

~

~

~

IDLE

IDLE

IDLE

IDLE

IDLE

IDLE

I

SAYESA

INrORCVD

,JK

,

"n

,: re
, re

~

,

n
NEW'JALUE

I

HEW VAlUE

:--- -.-

H

--------~-+_7~

1

,

VALID

I,

SARCVD

MrLAG

: JX

,

i---l

DAIG

DARCVD

DAI
OAl

I

DAD

~--~--------------------~LJ
VALID

~------------------------ILJ
,
.
I

VALID

------- ----------

SAMEINrO

EDRCVD

vrcs
VOL

+-__~--------------------~----------------------------~Iro

rs

I VALID

I VALID

-----1
TUF/l0825-9

FIGURE 10. MAC Indication Timing Example-Internal Stripping based on MFLAG

6S9-NY

II

AN·SS9

LBC
PID IDLE

J](

PC

DAO

OAf

MID IDlE

IDLE

IDLE

IDlE

:JK

:rc

PRO IDLE

IDLE

IDLE

IDLE

IJI(

Ire

RCSTART

FCRCVD

SAO

INF01

INroz

IHF03

INFO"'

INf05

INFOS

INr07

INF08

INF'09

::::::::rn

FS

IDlE

IDLE

JK

SAO

:SA1

INFOO

INFOf

INF02

I~F03

INFO"'

INf'OS

INrcG

tNF07

INroa

INFog :::::::ED

:rs

IDlE

IDLE

::::::: IDlE

IDLE:JK

SAO

'SA1

IDLE

IDlE

IDLE

IDlE

IDlE

IDLE

IDLE

IDLE

IDLE

!IDLE

IDLE

IDl.£

::::::: IDlE

IX.[

'DAD

I

'OAf

'IDlE
I

IDlE

:::::: 'IDLE
,

NEW *,"u,

CD

-----

VAll1l

..,

MFLAG

VAll)

SAUESA

VAll)

Elf

Fe

:-~

AFLAG

SARCVD

Fe

fIn
IJK

'

DARCVD

f>
CD

I

:-

I NEW VAlUE

DAIG

rc :::::::

INroo

:DA1

hi"
n

FCSL

:lDLE

SAt

:DAO

______-;-_i--r_~'VAlJD

IXXX~XXXX~

r "

I

I

INFORCVD

I

SAUBNFO

EDRCVD

VAll1l

jm

~~~~--~------~------------~

VFCS

VOL

~

I~

------.

rvAiiil;-

.~

TL/F/l0825-10

Note: EM may be asserted at any time; Stripping begins 3 byte times after EM is asserted.

FIGURE 11. MAC Indication Timing Example-External Stripping based on External MFLAG

RECEIVE SEQUENCER
An example receive sequencer is shown in Figure 12 for the
Indicate byte stream..

COPY CRITERIA
The decision to copy or not copy a frame is made by external hardware that looks at flags from the BMAC device qualified by the sequencing signals. The Copy decision may also
use inputs from additional address matching logic. The
Copy Criteria may be different for frames with different FC
values. For example, SMT frames might only be copied on
the basis of internal address matches while LLC frames
might be copied on the basis of external matches as well.
When using different frame copying criteria for different FC
values, the copy logic must latch the relevant bits of the FC,
or alternatively map the FC, or other fields within the frame,
to one of several groups, each of which share the same
copy criteria. The frame copying criteria might also be programmable in each group. The BMAC device thus provides
the mechanisms by which to create very complicated or
simple copy criteria.
A simple copy criteria might be as follows:

RSO:ldle
Remain in the Idle state while not copying any data or writing any status. Leave Idle when there is a place to put an
incoming frame and the beginning of a frame (RCSTARn is
received. At this point the Stage state is entered.
RSl1:Stage
Remain in the Stage state while deciding whether or not to
copy a frame. The decision is made at the commit point.
The commit pOint occurs any time after both the relevant
address comparisons are complete, and after the pOint in
the frame where it is not considered a legal fragment (4
bytes into the Information Field, when INFORCVD Is asserted). At the commit pOint the results of the address comparisons as indicated by the Flags from the BMAC device are
compared against the copy criteria. If the criteria matches
and no frame termination event has occurred, the decision
Is made to continue copying the frame and the Copy state is
entered. Otherwise, the Idle state is entered and the rest of
the frame is not copied.

All Frames

AFLAG and not MFLAG (so that you don't
copy frames that you sent, i.e., broadcast
and multicast)
A more sophisticated copy criteria might have different copy
criteria for each of several groups. In this example, groups
are differentiated by the FC.
MAC
Not (SAMEINFO and SAMEFC)
SMT
LLC Synch

AFLAG or MFLAG
Short and AFLAG and Not MFLAG

LLC Asynch
Reserved

Long and AFLAG and Not MFLAG
Do not copy

RS2:Copy
Remain in the Copy state while copying a frame into memory or temporary storage. Once committed to copying, continue copying until a Termination Event (TE) occurs. Upon a
TE, status is written. For every frame or partial frame copied, there should be a place to record status.
RS3:Status
Remain in the Status State while Status is being written.
After Status has been written, return to the Idle state.

Implementer Short and external address match
The copy criteria for MAC frames allows a station to skip
copying MAC frames with the same (first four bytes of) information and the same FC value.

RSO: Idle

RS1: Stage

RS2: Copy

RS3: Status

-~

-..--

-..--

-..--

RCSTART &c
,lasLpage

1£
,RSTART I
lasLpage

I
no status

status
loop

I
ST5

TLlF/10825-16

FIGURE 12. Example Receive Sequencer

4-89

en ,---------------------------------------------------------------------------------,
co
As a burst of frames is being received, several options are
CONDITIONS
~

z


set the TVX timers in all stations. During an immediate request from the CLAIM or BEACON states, when no CLAIM
or BEACON frames are ready, the internally generated
CLAIM or BEACON frames are transmitted.

Reporting Status related to a transmission is one of the
most challenging aspects of designing an interface to the
BMAC device. During a transmission several errors can occur. A transmission may be terminated unsuccessfully because of external buffering or interface parity errors, internal
Ring Engine errors, a MAC reset, or reception of a MAC
frame. When a transmission is aborted due to an external
error (and Option.IRPT is not set), a Void frame is transmitted to reset the TVX timers in all stations in the ring.
The BMAC device also guarantees that a valid frame is sent
with at most LMAX preamble (3.20 /Ls of preamble). This
alleviates the requirement from being handled by the interface logic. During a service opportunity when data is not
ready to be transmitted, Void frames are transmitted to re-

SERVICE CLASSES
A token capture class of "non-rstr" indicates that the transmitter token class must be non-restricted to begin servicing
the request. A token capture class of "rstr" indicates that
the transmitter token class must be restricted to begin servicing the request. A token issue class of "non-rstr" means
that the transmitter token class will be non-restricted upon
completion of the request. A token issue class of "rstr"
means that the transmitter token class will be restricted
upon completion of the request. (See Figure 13.)

RQRCLS (3:0)

Name

Class

THT

Token
Capture

Token
Issue

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111

None
April_1
April-2
ApriL3
Syn
Imm
ImmN
ImmR
Asyn
Rbeg
Rend
Rcnt
AsynD
RbegD
RendD
RcntD

None
Asyncthsh1
Asyncthsh2
Asyncthsh3
Synch
Immediate
Immediate
Immediate
Async
Restricted
Restricted
Restricted
Async
Restricted
Restricted
Restricted

enabled
enabled
enabled
disabled
disabled
disabled
disabled
enabled
enabled
enabled
enabled
disabled
disabled
disabled
disabled

non-rstr
non-rstr
non-rstr
any
none
none
none
non-rstr
non-rstr
rstr
rstr
non-rstr
non-rstr
rstr
rstr

non-rstr
non-rstr
non-rstr
captured
none
non-rstr
rstr
non-rstr
rstr
non-rstr
rstr
non-rstr
rstr
non-rstr
rstr

Notes

1

4
4
4
2,3
2

2
2,3

2
2

Note 1: Synchronous requests are not serviced when RElR.BCNR is set.
Note 2: Restricted requests are not serviced when RElR.BCNR or RElR.ClMR are set.

Note 3: Restricted Dialogues only begin when a

non~restricted

token has been received and transmitted.

Note 4: Immediate Requests are serviced when the ring is non-operational. These requests ars serviced from the Data stats if neither RQCLM nor RaBeN are
asserted. tl RaClM is asserted, Immediate requests are serviced Irom the CLAIM state and il RaBCN is assarted, Immediate requests are serviced from the
BEACON state. RaClM and RaBCN do not cause transitions to the CLAIM and BEACON states. Function.ClM and Function.BCN cause these tranSitions.

FIGURE 13. Request Service Classes
MRO: NOT READY

MR1: READY

MR2: SENDING

MR(OI) __S;.;E;;;.RV;.;.IC==E~O-=PP~O~RT~U;.;NI;.;TY_ _ _-+I ( ) SEND FRAME
SET TXRDY
MR 12
SET TXACK
FRAME SENT &
END OF SERVICE OPPORTUNITY MR(10)
SET TXPASS

~ CONTINUE SERVICE OPPORTUNITY

SET TXRDY

MR(21)

I+_ _ _ _ _ _ _ _..::E:.;;ND;..O;;;F;.;.S::;E::;.RV;.;IC::;E;.;O;.:.P;.;PO:.:.R:.:.;TU;.:.N::;ITY.:...._ _ _ _ _ _ _ MR(20)
SET TXPASS
TL/F/l0B25-12

FIGURE 14. MAC Request Interface State Diagrams

4-91

Z

en
CD
CQ

en
co
~

Z

cc

r---------------------------------------------------------------------------------,
The Logical States of the MAC Request Interface
The MAC Request Interface has three logical states: either

RORDY and ROSEND are asserted, and ROFINAL has not
yet been asserted for this request.

the Ring Engine is not ready to service a request, the Ring
Engine is ready for the next frame from the interface, or the
Ring Engine is sending a frame from the interface. See Figure 14.

Continue Service Opportunity: The Service Opportunity is
continued after the current frame if valid service parameters
continue to be presented during the frame, and the timer(s)
used for the (next) requested service class have not
reached their threshold.

The values of TXRDY and TXPASS associated with these
three states are shown below.

State

TXRDY

TXPASS

Not ready
Ready
Sending
Internal error

=0
= 1
=0
= 1

= 1
=0
=0
=1

The table below shows the timer thresholds used for each
service class:

Conditions
Service Opportunity: A service opportunity occurs when it

Service Class

Threshold

All Requests
All Requests with THT Enabled
Priority Asynchronous Requests

TRT Expiration
THT Expiration
Asynchronous Priority
Threshold

End of Service Opportunity: The end of a service opportu-

The last latched version of RORCLS is used when RORDY
is asserted.

nity occurs when it is no longer necessary or possible to
continue the service opportunity. The service parameters
are continuously compared with the current state of the
Transmitter. If an unserviceable request is presented or any
time threshold is reached, the service opportunity will not
continue after the current frame (if any).

Send Frame: A frame can be sent from the interface when
at least 8 bytes of preamble have been transmitted, TXRDY,

Two MAC Request Timing Examples are shown in Figures
1Sand 16.

is possible to service the current request, as defined by the
current service parameters (RORCLS, ROCLM and
ROBCN).

4-92

TXRINGOP

RORCLS

..............

~L'~r1_'__________________________

TXPASSK

______________...1rr
1

~.

THTDIS

-------

FR Options
ROSEND
MRD

i

------. . . . .

cC

. . . . .

ROEOF

;11;2Ii~I;41;51;61~,;81·li~li~l·

~

.....

TXCLASS

: : : : :

PRD

ii Ii Ii ii

.......... : 1~1 ~1:1 :11;2Ii~II~II:511:4~1:8 :li~l:z" .................. .

••••••••••••••••••••

j

••••••••••••••••••••••••••••

·4···············I··:······~·····················

JJ'-____________

jJ'

"'--'--'-1

..
ROFINAL

LI__.--.--.-. . . . . . . . . . . . . . . . . . . . . . . .

~~~~~.~ . . . . . . . . . . . . . . . . . . . . . . ~~.~:~~~~~~~~~~~~

-.-.-.-.-. -.-.-.-

TXED -'-'-'-'-'

•

.'. ~AI.~Dn~IL.•

TXACK

: : : : :

•

...i;'---________________

1

_ _ _ _ _ _-1 VALID I

. . . . . . .

ROABT

•

Ir1

------- ......... ";1 ;1

TXABORT

•

. . . . . . . .

.l>-

"'I

•

Ir1

~--

TXRDY

\I n

:(~

~.

RORDY

n jk Ie

Itrrr Ii
. . . . . . . . . . . . . . . . _.-.-,..""'.-,-._.-.--'

................

ii'l' ,

. • n' 11'
______________..., tr rr
. . . . . 1...-...,-,-..,.....-,.-

iI jk Ie \I

. ................. '. [lL..,..
. .,.-,-,.......

~
~ ~ Itkfn ..~

~
.. .. .. .. " .. " .. , jk i1 12 i3 S A i6

iw ix Iy iz 11 12 f3 14 tr

IT

I ii

ii

1

I jk 111

i2 i3 S A is

iw ix iy iz 11 12 13 14 tr

IT I"

"

..

..

..

..

..

..,

TUF/10825-13

FIGURE 15. Asynchronous Request with Prestaging
(normal completion after two frames)

689-N'd

II

AN·689

lXRINGOP

lXPASS~

· ...................
. , . , . ,. ,. i .

rrOOOOOOOOJkfcllOO

.

RQRCLS ..Jr,Ir2lr3Ir4IrSlrS
RQRDY

r;;--

. • • . ••

~ ........................
.
· ............
.
---'L,-,.....,.....,....,.....,....,....,..
lXRDY~.~.
IrS

TXTHTDIS

.~ .VA~ID .1 . . . . . . . . . . . . . . . . . . . . . . ~. V~LID. LI._._._._._._.. ________________
.......................................

fR Options

RQSEND
MRD

t

."..

••••••••••.
.•••••••••

~ ••••.•••••••••• ~ •••••••••••••••••••••••

:jl~ I~ '~H~Hi~H+ .1'd~L

lXACK _ _ _ _ _ _ __

:j~lI~ ,+H,~H,~H{H~z

--,

~

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FIGURE 16. Asynchronous Request without Prestaging
(token times out during second frame)

.

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REQUEST MACHINE

rising edge of TXPASS or TXRDY. While TXACK is asserted, data is transmitted rrXACK could be used as an enable
for a byte counter). On the last byte of the frame, ROEOF is
asserted and in response TXACK is deasserted. TXACK is
used by the frame level handshake and ROEOF is returned
from the frame level handshake. The Request Machine
does not use TXACK or provide ROEOF.
The Last Frame and Last Request Signals help control the
sequencing for multiframe requests or multirequest service
opportunities. Only between requests can the Requested
Service Class change. The frame options may change on
each frame.

The Request Machine shown in Figure 17 is a simplified
version of a Transmit Sequencer. This could be used as the
basis for many designs.
Note that all signals that begin with TX come from the
BMAC Device Transmitter, and all signals that begin with
RO come from the PAL Sequencer (the Request Machine or
Transmit Sequencer).
RQO:IDLE

While in the Idle State, there are no frames to be sent and
all of the status from previous frames has been reported.
When a frame is to be sent, it is loaded into the temporary
buffer. Once a frame is ready to be sent RORCLS is loaded
with the appropriate value. This requests a service opportunity as described by the 4-bit RORCLS field in addition to
the ROCLM and ROBCN which are used with Immediate
transmissions. A transition to the Ready State then occurs.

RQ3:STATUS

After the frame is sent, status related to that frame is written
or accumulated as appropriate either on the transmitted
frame only or the returning frame as well. In short rings, this
should be several byte times after the frame is transmitted,
but in large rings there could be a several microsecond delay.

RQ1:READY

RORDY is asserted to indicate that the interface has or will
soon have a frame that is ready to be sent. RORDY causes
the RORCLS to be latched into the BMAC device and used
while RORDY is asserted. Once the token is captured a
transition to the Send State occurs. Alternatively, enough
data could be loaded into temporary storage to keep it not
empty over transmission of the frame.

Conditions
Frame_Ready
• Frame_Ready is True when a frame is ready to be sent
• The Frame options (SAT, SAIGT, STRIP, FCST) must be
valid at this time.
Instead of loading the entire frame into the temporary buffer before telling the MAC Interface, it would be possible to
load in enough of the frame to guarantee that the temporary buffering will have enough data to keep up with the
ring over the duration of the frame. An implementation like
this could employ a FIFO or an equivalent speed matching
device to match or smooth the bandwidth characteristics
of the hardware feeding the temporary buffering.

RQ2:SEND

Upon entry to the Send State ROSEND is asserted and the
Frame Options are latched by the MAC interface. TXRDY is
deasserted and TXACK asserted when the beginning of the
frame is sent. A flag is set that causes us to remain in the
Send State until the end of the frame as denoted by the

- ..--

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RQRCLS >0 &
Frame_Ready
SET RQRDY

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CD
CD

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Started_to_Send &
(TXRDYI TXPASS)
TXRDY
Set RQSENDClear
Started_to_Send

~ Frame_Ready

~ TXRDY&~ TXPASS

Set Started_to_Send
If LastJrame
Clear RQRDY
If Last_Request
Set RQRCLS =0

IRQRCLS =0

I

Status Complete & ~ LasLFrame
Status Complete & LasLFrame

TL/F/l0B25-17

FIGURE 17. Example Transmit Sequencer

III
4-95

Holding the Token
At end of the frame, TXRDY is asserted if possible (THT or
TRT has not expired) or desirable (there are more frames to
transmit on this service opportunity). Otherwise TXPASS is
asserted.
Issue Token Class
If RQRCLS goes to zero at any time during a service opportunity a token will be issued.
TXCLASS indicates the class of token that was issued, in
the case of TXPASS, or would have been issued in the case
of TXRDY. Since the issue token class is given in the
RQRCLS encoding, this is a sanity check, especially in a
non-pipelined implementation .
For certain SMT frames (NSA frames), the returning status
is of considerable interest. In these cases, it may be easier
to just turn on copying of SMT frames based on MFLAG
(i.e., AFLAG or MFLAG instead of the normal AFLAG and
not MFLAG). The status can be the same as the reception
status.

Notice that on the transition to the Ready State
RQRCLS>O is also used as a condition. This implies that
the token could be captured before the data is actually
ready. In other words, from the word go a race takes place
between the data becoming ready in the temporary buffering and the MAC capturing a useable token.
StartecL.to_Send
• This is true any time after the MAC transmitter has started
to send a frame.
Status-Complete
• This is true when status for the transmitted frame has
been recorded.
• This may be a result of the transmitted frame, and optionally the returning frame.
Notice that in the case where status is written for every
frame, additional frames may not be transmitted until after
status is written. A further alternative approach would allow status on frames of a request to be stored in a temporary location and then only write status between requests.
An extension to this idea would be to store temporary
status separately for each individual request. This last approach would allow both of the Status Complete transitions to occur immediately. At some point however the
interlock with the actual writing of status would have to
occur. For example, even in the case where status is written into temporary storage for each request, a new request could not be started until status for the previous
request has been written.

PROVIDING A TRANSMISSION CONFIRMATION
SERVICE
Providing a Transmission Confirmation Service is one of the
most challenging aspects of designing an interlace to the
BMAC device. Some useful hints for providing such a service are given below.
Overview
A transmission confirmation service returns ending status
for a request to transmit one or more frames. As frames of a
request are transmitted, the status on the returning frames
is accumulated. When all of the frames of the request return
around the ring, a positive status is given. Should anything
other than the expected frames (with the correct FC, SA,
FCS, and frame status values) return before all of the transmitted frames return, a negative status is generated. Status
is thus generated when either all of the frames return, or an
abnormal condition is detected.

A pipelined multiple request machine could even take the
status-complete and lasLframe transition before the
end of the frame and begin to load in the new parameters
for the next frame. This would allow frames of the next
Request to be transmitted very soon after the frames of
the previous Request.
TRANSMISSION STATUS
Transmission status concerning the previous transmission
is valid in all cases one cycle after TXRDY or TXPASS is
asserted.
Transmission Completion
If an Ending Delimiter was transmitted TXED will be active
one cycle after TXRDY or TXPASS is asserted until the
starting delimiter of the next frame is transmitted. If the
frame was aborted TXABORT is active one cycle after
TXRDY or TXPASS is asserted.
The frame could have been aborted for several reasons:

The transmission confirmation service is similar to
the (SM_)MA-UNITDATA-STATUS.indication (formerly
called (SM-lMA-DATA.confirmation) defined in the ANSI
FDDI MAC standard.
Ring Assumptions
• Returning frames can be associated with transmitted
frames.
At most one request can be serviced (for each SAP) during a given token opportunity. Since the order of SAP
serviced is fixed, the order for matching returning frames
with their corresponding requests is also known. The returning FC, SA and FCS could be used to distinguish a
frame transmitted by this station and match it with its corresponding SAP. Additional fields may be used to increase
confidence in the association.
• Frames return in the order transmitted.

• a MAC Reset
• the ring going non operational
• an internal BMAC device error
• an RQABORT during the frame
TRT Expiration
If TXPASS is asserted and THT was disabled during the last
frame that was transmitted (THTDIS is asserted), TRT has
expired. This is a serious error and indicates that there was
an overallocation of synchronous bandwidth or a station
used more than it was allocated. The ring will likely be in the
CLAIM state when this occurs.

We assume that no frames are maliciously inserted into
the ring.
• After a token is captured by a station for transmission, the
next returning frames will be those transmitted by this station.

External CLAIM/BEACON Transmission
When transmitting CLAIM/BEACON frames from the
CLAIM/BEACON state, if TXPASS is asserted the CLAIM/
BEACON process is complete. In this case TXABORT indicates if this station won (TXABORT=O) or lost
(TXABORT= 1) the CLAIM/BEACON process.

Since there is a single token, the next frame received by
this station should be the (first) one it transmitted unless
another station has failed to strip its frame(s).

4-96

~----------------------------------------------------~~

• Synchronization points:
At these synchronization pOints, the number of frames
transmitted and the number of frames received should be
equal.

• Frame Lost due to line hit
This type of error is more difficult to handle because it
cannot be detected until the next synchronization point. At
the next synchronization point the received and transmitted counts for the current request will not be equal. A
negative confirmation is generated and the request is optionally terminated.

• Token received
• Frame with a different SA is received, after receipt of a
frame with my SA.

• Frame not recognized by source station

Error Conditions

This type of error is more difficult to handle because it
creates a false synchronization point. At this point the received and transmitted counts for the current request will
not be equal. A negative confirmation is generated and
the request is optionally terminated.

• Frame not recognized by addressed station
No station recognizes the Destination Address, and as a
result the A indicator is not set. Either the station is not
present or a line hit corrupted the Destination Address.
• Frame not copied by addressed station

• Frame incorrectly recognized by source station

The addressed station runs out of buffering resources and
as a result does not set the C indicator. This is probably
the most likely of the error conditions.

This condition will be detected unless the line hit caused a
formerly invalid FCS to become valid. When detected, this
condition may produce a false negative confirmation, but it
will not produce a false positive confirmation.

• Frame Error due to line hit
For example when a line hit causes an FCS error.

5.0 Bridging/External Matching
Support

• Frame Lost due to line hit
For example the starting or ending delimiter is destroyed,
or a data symbol becomes a non-data symbol. This may
have different effects when the lost frame is:

There are two major considerations for MAC level Bridging
products on FDDI:

•

first frame of request

1. How stripping will be accomplished and

•
•

a middle frame of a request
the last frame of a request

2. How the control indicators will be handled.
The FDDI standard does not have a recommended Bridging
algorithm like 802.3's Transparent Bridging and 802.5's
Source Routing Bridging.

• Frame not recognized by source station
A line hit corrupted the FC or the Source Address.

The issue with stripping is that every station needs to strip
every frame it transmits. Typically this is accomplished by
stripping based only on the Source Address. However, in
bridging applications where the SA is not necessarily of this
station, this station needs to either watch out for all of its
frames (and use CAM technology to assist the strip decision) or use some other mechanism. Currently, the FDDI
X3T9.5 Committee has agreed that the strip pOints of all
frames is before the fourth byte of the INFO field. That implies that any fragment with more than three bytes of INFO
is an illegal fragment.

• Frame incorrectly recognized by source station
Frame insertion or misdirection can occur during reconfiguration, but CMT will remove such frames by scrubbing.
An alias could be caused by a line hit on the FC or SA, but
it is highly unlikely to contain the proper FCS value (this
would require multiple errors or an unfortunate pattern on
a transparent FCS transmission). Indiscriminate use of
transparent FCS transmission could diminish the integrity
of the confirmation service.

Error Handling
For each request, an expected status parameter is given
either explicitly with the request or implicitly (it was given
explicitly previously and has not changed). The expected
status contains the expected value of the returning FCS, E,
A and C indicators. If the expected value of these indicators
is not returned, a negative confirmation is generated.

The BMAC device provides an alternate stripping mechanism to accomplish the stripping by sending out two
My_Void frames before the token and stripping everything
until the first My_Void returns.
The definition of a bridgeable frame also has impact in
bridging applications. Only LLC frames are bridgeable. Management frames (MAC and SMT frames) are not bridgeable.
BEACON frames, CLAIM frames and SMT frames are local
to a Single ring. Likewise, synchronous and restricted dialogs are local to a Single ring.

• Frame not recognized by addressed station
This condition can be handled using the expected status.
The returning A indicator is not set, so the expected frame
status is not returned. A negative confirmation is generated and the request is optionally terminated.

5.1 EXTERNAL MATCHING LOGIC

• Frame not copied by addressed station

External Matching Logic is used to allow this station to recognize additional addresses. These additional addresses
may be aliases (additional addresses that are not this station's management address) or additional group addresses
not recognized by the BMAC device. In addition, more perfect filtering or routing could be done on certain classes of
frames. Certain bridges and routers (not 802.1 d transparent
bridges since these address matches do not set the ~ind)
can be viewed as having a set of aliases.

This condition can be handled using the expected status.
The returning C indicator is not set, so the expected frame
status is not returned. A negative confirmation is generated and the request is optionally terminated.
• Frame Error due to line hit
This condition can be handled using the expected status.
The returning E indicator is not reset or the FCS is invalid,
so the expected frame status is not returned. A negative
confirmation is generated and the request is optionally terminated.

4-97

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bridge will only set the A-INO if the frame is explicitly addressed to the bridge and may optionally set the C_INO for
all frames copied with the intent to be forwarded. If an end
station receives a frame addressed to it with the A indicator
reset, the C indicator set, and it does not copy the frame,
the station sends it out with the A indicator set but the C
indicator reset.

The result of the address comparison is then fed into the
copy criteria and used to set the A indicator .(the BMAC
device EA input). The C indicator should be set as usual
unless the frames recognized by the external matching logic
are sent to a different buffer memory and generate a separate VCOPY signal.
There are two choices of where the external matching logic
may tap into the data stream, either at the PHY Indicate
Interface or at the MAC Indicate Interface. We recommend
using the PHY Indicate Interface between the PLAYER device and BMAC device, because it provides a three byte
time advantage over the alternative.

END STATIONS
For end stations and bridges which also act as end stations,
the BMAC device always implements the option recommended by the Bridging Working Committee to X3T9.5. For
frames with A not set and C set for which the station intends
to Set the A indicator but not the C, the A indicator is transmitted as set and the C indicator is transmitted as Reset.

When using alias addressing it is also possible to strip
frames on the basis of these additional aliased source addresses if the STRIP option is not used or desired. Three
byte times aiter the EM signal is asserted, Idle symbols are
transmitted into the ring and the frame is stripped.

BRIDGES
For stations acting as bridges, the committee recommends
that for frames copied with the intent to forward (for which a
station address or alias match did not occur), only the C
indicator should be set, not the A indicator.

5.2 SA, SAIG, FCS TRANSPARENCY OPTIONS
These transparency options are particularly useful in bridging applications. The SA transparency options are useful in
certain Transparent Bridging algorithms and in Source Routing Protocols. The SA and SAIG transparency options allow
the SA to be sent transparently from the data stream as
opposed to being sent from the MAC Parameter RAM. The
FCS transparency is particularly useful between bridged
rings (end to end FCS checking with FOOl to FOOl bridges).
The FCS transparency could also be useful for diagnostic
purposes and with implementer defined FCSs on implementer frames.

To accomplish this, since the BMAC device will not set the
C indicator without setting the A indicator as well, it is necessary to intercept the byte stream between the BMAC device and the PLAYER device. Fortunately, the difference
between the Rand S symbol is only a single bit. Thus, when
a frame is copied with the intent to forward it, the received A
indicator is not set, and the station's AFLAG is not set, the C
indicator must be changed from an R to an S. This occurs
one byte time aiter EORCVO is asserted and requires that
PRO(O) be changed from a 0 to a 1.

5.3 IMPLEMENTING THE BRIDGING COMMITTEE
RECOMMENDATIONS

This easily fits into a small slice of a PAL and is only required in bridges implementing this option.

The meaning of the control indicators also is impacted in
bridging applications. The ANSI committee decided that a

4-98

.------------------------------------------------------------------.~

~~

BSITM Device Software
Design Guide

National Semiconductor
Application Note 730
Robert Macomber, Mark Travaglio

Table of Contents

corresponding bits in the CMP register will be actually
stored in STAR. With the BSI device in "Stop Mode", and
no intervening accesses to the BSI device Control Bus, it is
guaranteed that all 8 bits will match.

1.0 INTRODUCTION
2.0 INITIALIZATION

Finally, write Ox07 to the STAR. This clears all the error bits
and sets all the stop bits (the STAR is automatically loaded
with Ox07 upon reset of the BSI device).

3.0 SERVICING INTERRUPTS
4.0 MEMORY MANAGEMENT SCHEMES
5.0 SENDING FRAMES

2.2 Set the Mailbox Address Register

6.0 RECEIVING FRAMES

When loading Pointer RAM data into the BSI device, a
"mailbox" mechanism is used. The mailbox is a 32-bit word
in off-chip memory which the BSI device uses to load or
dump the Pointer RAM Registers. This mailbox may be located anywhere within the 28-bit ABus address space of the
BSI device and accordingly its address must be explicitly
defined. This is accomplished via the 8-bit Mailbox Address
Register (MBAR).

7.0 QUEUE MANIPULATION
1.0 INTRODUCTION
This application note describes how to initialize the National
Semiconductor BSI device (DP83265) and interact with it.
Initialization and data service support occur through the
Control Bus and via memory that is accessible by both the
BSI device and the host. The host processor must be able
to respond to interrupts and have access to both the BSI
device Control Bus and some mutually accessible memory.
This application note should be read in conjunction with the
BSI datasheet.

To load the Mailbox Address Register (MBAR) first load
OxOO into the Pointer RAM Control and Address Register
(PCAR). This tells the BSI device to internally point to the
first byte of the mailbox address. Then execute four successive writes to the MBAR to load the full mailbox address;
writing the most significant bytes first. Each write automatically increments the byte pointer to the next byte.
When the BSI device is reset, the Mailbox Address Register
(MBAR) is loaded with a hardware revision code. The host
may obtain this revision code by sequentially reading four
bytes from the MBAR before loading the mailbox address.

2.0 INITIALIZATION
Before BSI device operation can begin, the device must be
initialized. The BMACTM and PLAYERTM devices must also
be individually initialized. To initialize the BSI device, the
steps shown below should be followed. Each action is explained further in the subsections that follow.
o Put the BSI Device in Stop Mode
o Set the Mailbox Address Register
o Load the Pointer RAM
o Set the Event Notify Registers
o

Set the Mode Register

o Set the Request Configuration Registers
o Set the Request Expected Frame Status Registers
o Set the Indicate Configuration Register
o

Set the Indicate Mode Register

o Set the Indicate Threshold Register
o
o

Set the Indicate Header Length Register
Load the Limit RAM

2.3 Load the Pointer RAM
The BSI device maintains pointer registers for acceSSing
and manipulating the various queues. Prior to normal operation, some of these pointer registers must be initialized with
queue addresses (see Table I). For active Request queues
the host software must load the Confirmation Message
(CNF) Queue Pointer Register and the Request (REQ)
Queue Pointer Register. For Indicate queues the host software must load the Indicate Data Unit Descriptor (lOUD)
Queue Pointer Register and the Pool Space (PSP) Queue
Pointer Register. For information about choosing initial
Pointer RAM values see Section 7 on Queue Manipulation.
TABLE I. Pointer Registers Used
during Queue Initialization

o Clear the Attention Register
• Put the BSI Device in Run Mode

Painter Registers
CNF
REQ
CNF
REQ
lOUD
PSP
lOUD
PSP
lOUD
PSP

2.1 Put the BSI Device in Stop Mode
During initialization the BSI device must be in "Stop Mode".
This is necessary to prevent the device from attempting to
perform any actions or respond to any external stimulus prior to the completion of the initialization sequence. The BSI
device may be placed in Stop Mode by setting three bits in
the State Attention Register (STAR).
Since the State Attention Register (STAR) is a conditional
write register, it must be read before it is written. By doing so
the original contents of the STAR register are loaded into
the Compare Register (CMP). When a subsequent write to
the STAR register occurs, only those bits that match the

Queue Pointer Register (RCHN1)
Queue Pointer Register (RCHN1)
Queue Pointer Register (RCHNO)
Queue Pointer Register (RCHNO)
Queue Pointer Register (ICHN2)
Queue Pointer Register (ICHN2)
Queue Pointer Register (ICHN1)
Queue Pointer Register (lCHN1)
Queue Pointer Register (ICHNO)
Queue Pointer Register (ICHNO)

Addr
Ox02
Ox03
Ox06
Ox07
Ox09
OxOa
OxOd
OxOe
Oxll
Ox12

Before loading a Pointer RAM Register, first read the Service Attention Register (SAR) to verify that the PTOP bit is

4-99

•

C)

~

:i

r---------------------~--------------------------------------------------------__,

Indicate breakpOints are instances that generate interrupts.
You may configure the BSI device to interrupt at the end of
each service opportunity, at the end of a burst (i.e., channel
change) or after a user defined number of frames have
been received. Prudent use of Indicate breakpoints can significantly reduce interrupt processing overhead by reducing
the number of Interrupts generated by the BSI device.

set; signifying that a previous Pointer RAM operation has
completed. If this bit is not set wait for the previous operation to finish.
Write the value one wishes to store in the Pointer RAM
Register (i.e., the base address of the relevant queue) in the
memory location selected as the BSI device Mailbox.
Next configure the Pointer RAM Control and Address RegIster (PCAR) with the PTRW bit cleared and the address of
the Pointer RAM Register placed in the least significant five
bits. A zero value in the PTRW bit specifies that the next
Pointer RAM operation will read from the Mailbox and write
to the Pointer RAM Register. The two most significant bits in
the PCAR (BPO, BP1) are not used in this context and may
be loaded with O's. For example, when loading the PSP
Queue Pointer for Indicate Channel 0, one would write Ox12
to the PCAR.
Finally, clear the PTOP bit in the Service Attention Register
(SAR). The SAR is a conditional write register, so it is necessary to read it immediately before writing to it. Clearing
the PTOP bit causes the BSI device to perform the actual
Pointer RAM operation. The device Signals the completion
of the operation by setting the PTOP bit in the SAR.

2.10 Set the Indicate Threshold Register
The Indicate Threshold Register (ITR) specifies how many
frames must be received before a threshold breakpoint is
realized. The value in this register is only used when the
appropriate bits are set in the IMR.
Loading the ITR with OxOO specifies a value of 256. This
value is loaded into an internal working register each time
the state of any Indicate Channels change.
2.11 Set the Indicate Header Length Register
If the Headerllnfo frame sorting mode is specified. one
must load the Indicate Header Length Register (IHLR) with
the length (in units of four byte words) of the header portion
of the frame. The FC field occupies an entire word. For example, to separate an 8 octet header when using long. sixoctet MAC addresses, one would load a value of 6 (FC = 1.
DA/SA = 3, header = 2) into this register.

The above steps must be done for all painters associated
with those channels that will be used.

2.12 Load the Limit RAM
During normal operation of the BSI device, the CNF and
lOUD queues must be given status space. This, may be
done as part of the initialization procedure. For information
about choosing initial Limit RAM values see Section 7 on
Queue Manipulation.

2.4 Set the Event Notify Registers
You may specify which events will trigger an interrupt by
setting the corresponding bit in the Notify Registers; where
a 1 enables interrupts from that event and a 0 disables
those interrupts. The Notify Registers may be written without being read previously (not conditional write registers).
See Section 3, Servicing Interrupts, for a more complete
treatment of this subject.

Before loading a Limit RAM Register, first read the Service
Attention Register (SAR) to verify tihat tihe LMOP bit is set
(signifying that the previous Limit RAM operation has completed). If this bit is not set wait for the previous operation to
finish.
Next load the Limit Address Register (LAR). The top four
bits of the LAR define the target Limit RAM Register, the
LMRW bit specifies what the next Limit RAM operation will
be (LMRW = 0 means a write to the Limit RAM) and the
MSBD bit contains the most-significant data bit of the 9-bit
Limit value.
Next load the Limit Data Register (LOR) with the lower 8 bits
of the limit value.

2.5 Set the Mode Register
Load the BSI device Mode Register (MR) to configure the
BSI device with global bus and queue parameters. For example a value of Ox52 causes the BSI device to generate 32
byte bursts when accessing the data bus, use 1k (small)
queues, operate in a physical memory environment, use
"big-endian" data alignment, check parity on access to the
ABus and Control Bus and optimize operation for clock
speeds over 12.5 MHz.
2.6 Set the Request Configuration Registers

Finally. write a 0 into the LMOP bit in the Service Attention
Register (SAR). The SAR is a conditional write register,
making it necessary to read it immediately before writing to
it. Clearing the LMOP bit causes the BSI device to perform
the actual Limit RAM operation. The BSI device signals the
completion of the operation by setting the LMOP bit in the
SAR.
Repeat the above steps for all desired limits.

Load the Request Configuration Registers (ROCR and
R1CR) for both Request Channels (RCHNO and RCHN1) to
establish channel specific operating parameters; such as
Source Address and Frame Control Transparency.
2.7 Set the Request Expected Frame Status Registers
Load the Request Expected Frame Status Registers
(ROEFSR and R1EFSR) for both Request Channels
(RCHNO and RCHN1) to set up the expected status for
frame confirmation services. A value of OxOO in these registers means that any frame status is acceptable.

2.13 Clear the Attention Registers
Clear the Request Attention (RAR) and Indicate Attention
Registers (IAR) by first reading the register, to load the
Compare Register (CMP), and then writing a OXOO value to
the register. Both of these registers are automatically initialized to 0 upon BSI device reset.
The No Space Attention Register (NSAR) should be initialized to reflect the state of space of all the queues. If space
was given to all of the CNF and PSP queues, read and write
OXOO into NSAR.

2.8 Set the Indicate Configuration Register
Load the Indicate Configuration Register (ICR) to establish
copy control parameters for each Indicate Channel. A typical register value is Ox49; which instructs the BSI device to
copy frames addressed for the owned MAC address or to
an externally matched group address.
2.9 Set the Indicate Mode Register
Load the Indicate Mode Register (lMR) to set the frame
sorting mode, skip option and the desired Indicate breakpOints.
4-100

r-------------------------------------------------------------------,>
2.14 Put the BSI Device In Run Mode

=F
......

TABLE II. Attention Registers

Initialization of the BSI device is now complete. The device
may be made fully operational by reading the State Atten·
tion Register (STAR) and immediately writing OxOO to it. This
will clear the stop bits for the Indicate, Request and Status/
Space machines; putting them in "Run Mode".

Master Attention Register (MAR)
State Attention Register (STAR)
No Space Attention Register (NSAR)
Service Attention Register (SAR)
Request Attention Register (RAR)
Indicate Attention Register (IAR)

The BSI device should immediately begin fetching PSP De·
scriptors for the Indicate Channels to use for frame recep·
tion. At this point a write to one of the REQ queue Limit
RAM Registers would cause the BSI device to begin fetch·
ing REQ Queue Descriptors for frame transmission.

The host may control which attention bits will generate an
interrupt by configuring the Notify Registers (see Table III).
TABLE III. Notify Registers

3.0 SERVICING INTERRUPTS
Master Notify Register (MNR)
State Notify Register (STNR)
No Space Notify Register (NSNR)
Service Notify Register (SNR)
Request Notify Register (RNR)
Indicate Notify Register (INR)

The BSI device provides facilities for selecting which events
will generate an interrupt and a mechanism for determining
which events are present after an interrupt has been raised.
3.1 Event Registers
The BSI device supports a two-level hierarchy of Event Registers; where the presence of attention signals in lower level
attention registers is recorded in a single upper level attention register. Attention signals may be disabled at either of
the two levels. Events may only be cleared by resetting the
attention bits in the lower level registers.

For each Attention Register a corresponding Notify Register
exists. Each Attention Register is ANDed with its corresponding Notify Register and then all of the resulting signals
are ORed together and presented to the next level (see
Figure 1).

The upper level attention register is called the Master Attention Register (MAR). It contains five attention bits that indicate the presence or absence of any events recorded in
each of the five corresponding attention lower level registers. Those registers are listed in Table II.

For example, to disable all interrupts caused by service
events: clear the Service Attention Register Notify (SVAN)
bit in the Master Notify Register (MNR). To disable only interrupts caused by Pointer RAM Operations: set the SVAN
bit in the MNR and clear the PTOPN bit in the Service Notify
Register (SNR).

Int.rrupt Signal

Ma.t.r Notify
Ma.t.r Att.ntion

stat. Notify
Stat. Att.ntlon
TLlF/ll088-1

FIGURE 1. BSI Device Event/Notify Registers

4-101

~

or-------------------------------------------------------------------i
~

Z

11(

When checking attention registers for the cause of an interrupt, one should perform a bit-wise AND operation between
the attention and notify registers and examine the result.
Just checking the attention registers may be misleading. For
example, to disable an Indicate Channel one may wish to
leave its PSP queue empty and mask off the "Low Data
Space" attention bit for that channel; via the Indicate Notify
Register (INR). Under these circumstances the IAR, by itself, may contain misleading information.

• attaching the previous page to a PSP Descriptor of the
same queue
• incrementing the PSP Limit Register for that queue
The management of space for ODUs (outgoing frame data)
and ODU Descriptors (ODUDs) must be done by the host.
A fully allocated 1k PSP queue consumes 512 kbytes of
buffer space. A fully allocated 4k PSP queue uses 2 MB of
buffer space.

3.2 Example Procedure

4.3 Shared Buffer Pool

A typical procedure for servicing BSI device interrupts is as
follows:

To maximize memory utilization, multiple Indicate Channels
may share a single pool of data buffers. This does not mean
that Indicate Channels can be made to share a Pool Space
(PSP) queue, but rather that data buffers attached to the
various PSP queues are allocated and freed from a global
buffer pool on an "as needed" basis. When using a shared
buffer pool, the Indicate buffer management becomes the
following:

• disable host interrupts
• determine the event that triggered the interrupt by checking the Master Attention Register and then querying the
appropriate lower level attention register
• process the event (or post the event to a service queue)
• clear the attention bit (or mask the attention bit)

• Detecting page boundary crosses; to determine when
the BSI device is finished filling the previous page

• enable host interrupts

4.0 MEMORY MANAGEMENT SCHEMES

• Obtaining confirmation that the host has finished processing all frames in that page

The BSI device may be configured to use memory shared
between itself and the host or it may be configured to use
the host's memory. In addition, it can be made to operate in
a vitural memory environment.

• Returning that page to a shared buffer pool or, upon determining that the page has been dedicated to a given
channel, reattach the page to the channel's PSP queue
• Responding to interrupts caused by a "Low Space" condition by allocating buffer space to one or more PSP Descriptors and incrementing the PSP Limit Register for
that queue

Although the BSI device manages space for incoming data
(from channel specific Pool Space (PSP) queues); the host
must implement a memory management mechanism to replenish the PSP queues and manage the space needed to
hold output data (ODU) and ODU Descriptors (ODUDs).

Again, the management of space for ODUs (outgoing frame
data) and ODU Descriptors (ODUDs) must be done by the
host.

4.1 Memory Requirements
Up to ten distinct queues may be established; two for each
channel. Depending upon the value of the Small Queue
(SMLQ) bit in the Mode Register (MR), these queues will
each consume 1k or 4k of memory; collectively occupying
either 10k or 40k of memory.

One danger with sharing pool space is that a heavily used
low priority channel may starve a high priority channel by
consuming all of the buffer space. This is contrary to the
idea of priority. It is recommended that some mechanism be
implemented for reserving memory for a given channel and
that at least four buffer pages be dedicated to Indicate
Channel 0 (ICHNO). This is to ensure that FDDI-SMT frames
will not be dropped when there is a greal deal of activity on
the other Indicate Channels.

A 4 byte word must be allocated as the BSI device Mailbox.
This word is only used when accessing the BSI device
Pointer RAM Registers.
Space must also be allocated for buffering frames. Any buffers drawn from this space must be no larger than 4 kbytes
and may not cross a 4 kbyte boundary. At the current time
the Count (CND field in the PSP Descriptor is ignored by the
BSI device. Pool space is intended to be allocated in
4 kbyte pages.

5.0 SENDING FRAMES
This section describes how to use the BSI device to queue a
frame for transmission on an FDDI ring. It is assumed that
the BSI device has been initialized and that the Request
Configuration Registers (ROCR and R1 CR) and the Request
Expected Frame Status Registers (ROEFSR and R1 EFSR)
have been previously loaded with the desired values.

Space must be allocated for buffering ODU Descriptors
(ODUDs). As with frame data, buffers drawn from this space
must be no larger than 4 kbytes and may not cross a 4 kbyte
boundary.

The mechanism for sending a frame is as follows:
• Obtain space for data structures

4.2 Dedicated Buffer Pools

• Load the ODU(s)
• Process previous CNFs (optional)

To simplify memory management, buffer pages may be dedicated to individual PSP queues. When using dedicated buffers, the Indicate buffer management task becomes a matter
of:

• Build the ODUD(s)
• Build the REQ
• Signal the BSI device

• detecting page boundary crosses; as an indication that
the BSI device has finished filling the previous page
• obtaining confirmation that the host has finished proceSSing all frames in the previous page

4-102

Subsection 5.7 describes some special considerations for
sending multiple frames in a single request object.

be set to a value of 1; since, in this case, only a single frame
will be transmitted.

5.1 Obtain Space for Data Structures

The Confirmation Class (CNFClS) field defines the level of
request confirmation that the BSI device will use and should
be set as needed. To turn off request confirmation put a hex
value of Ox4 in the CNFClS field; although, the BSI device
will always generate CNF Descriptors whenever an exception is encountered. Please note that request processing will
halt for a given channel should that channel's CNF queue
become full. Thus, a provision for processing CNF Descriptors must be included in all applications; even those applications that do not wish to receive confirmation for most requests.
The Request Class (ROClS) field defines the class of the
request (i.e., asynchronous, synchronous, restricted token,
etc.). The FC field should be loaded with an appropriate
FDDI Frame Control value.

BSI device addressable memory must be obtained to:
• hold the frame data
• hold the ODU Descriptor(s)
• hold the Request Descriptor
It is the responsibility of the host software to manage space
for frame data and the ODUDs. Section 4, Memory Management Schemes, describes two simple memory allocation
methods. If multiple ODUDs are required, these must be
contiguously allocated in the form of an array of ODUDs.
Space for the Request Descriptor must be located within
the area designated as the Request queue (see Section
2.3). It must also be allocated in a serially contiguous fashion; immediately following the previously allocated descriptor. All BSI device queue pOinters "wrap" to the first location upon reaching the end of the queue area.
The frame data may need to be divided between multiple
ODUs. Each ODU may start anywhere within a 4k page, but
it must end at or before the next 4k boundary. Multiple
ODUs must be generated for frames over 4k in length.

When sending a single frame, both bits in the First and last
bits should be set; indicating that this is the only REO Descriptor in this request object. Finally, the address of the first
ODUD should be put into the laC field.
5.6 Signal the BSI Device about the Request
The BSI device may be caused to examine either of its REO
queues by writing to the corresponding Limit RAM Register
with a value that raises the limit to reference the new REO
Descriptor.

For each ODU, space must be allocated for a corresponding ODU Descriptor (ODUD). System configurations in
which the BSI device directly addresses host memory, may
be able to contrive ODU Descriptors (ODUDs) that refer directly to host specific memory buffers.

5.7 Sending Multiple Frames in a Single Request Object
The BSI device is capable of transmitting multiple frames in
a single service opportunity. This feature becomes important on a heavily loaded FDDI ring, with relatively infrequent
service opportunities. The BSI device can be caused to process multiple frames by:
o building an ODUD list that contains multiple frames

5.2 Process Confirmation Status Message Descriptors
(CNF)-Optional
When the BSI device processes a request it places confirmation messages in the CNF queue for that Request Channel. By examining these messages, the host may determine
when the BSI device has finished using ODU, ODUD and
REO queue space.
If the BSI device has been instructed to generate interrupts
after writing confirmation messages, then an autonomous
interrupt handler should be available to asynchronously process CNFs. Conversely, if these interrupts have been disabled, then CNFs should be processed when attempting to
send a frame.

• building a request object that contains multiple REO Descriptors or
o a combination of the above two methods.
The first method is extremely simple. Allocate and fill the
ODU buffers for all of the frames. Build multiple ODU Descriptor objects (demarcated by the First and last bits in
each ODUD) and concatenate the ODUDs together into one
array of descriptors. Build the REO Descriptor, as before,
except load the frame count into the SIZE field.

5.3 Copy Frame Data to Buffer
If the ODU buffers are distinct from the host specific memory buffers, copy the frame data from the host buffer(s) to the
ODU buffer(s).

The second method consists of a creating a REO Descriptor
marked as being "first", zero or more REO Descriptors
marked as "middle" descriptors and an ending REO Descriptor marked as being "last". The Limit RAM Register, for
the given request queue, must be set beyond the last REO
Descriptor. The parameter fields in first REO Descriptor are
used for the entire request object.

5.4 Build the ODU Descrlptor(s)
An ODU Descriptor (ODUD) must be written for each ODU.
The address and size of the ODU must be recorded in the
ODUD.lOC and ODUD.CNT fields, respectively.
When only a single ODUD is needed both the First and last
bits should be set (only). With multiple ODUDs the first
ODUD should has the just First bit set (first) and the last
ODUD should have the just last bit set (last). Any intervening ODUDs should have both bits cleared (middle).

5.8 Batching Single Frame Requests
On a heavily loaded FDDI ring service opportunities occur
less frequently than on an FDDI ring with only light traffic.
On a loaded network it makes sense to send multiple
frames per service opportunity. However, many network
communication systems send only a single frame at a time.
This subsection tells how one may use the capabilities of
the BSI device to batch single frame requests into a larger
request object.
The BSI device will only attempt to send a single request
object in any given service opportunity. A request object is
defined here to consist of one or more REO Descriptors
delimited using the First and last bits found inside each

5.5 Build the Request Descriptor
A Request Descriptor must be constructed which references the ODUD(s) that were just built.
The User Identification (UID) field may be assigned a host
defined value. This UID value will reemerge in one or more
CNFs and may be useful when processing a CNF (i.e., deallocating ODUD and buffer space). The SIZE field should

4-103

•

Interrupt Service Routine Logic (Optional)
if Open_Req = TRUE
generate empty REO. LAST
Open_Req = FALSE
Req_Size = 0
endif
Queue_Cnt is the number of queued request objects on
the request queue and is set to 0 queue initialization time.
Rell-Slze is the number of frames in the currently open
request object and is set to 0 at queue initialization time.
Open_Req is a boolean variable indicating the presence or
absence of an open request object and is set to FALSE at
queue initialization time. MalL-Req is a maximum number
of frames per request object defined by the host software.
Please note that the BSI device will not hold the token unnecessarily when processing an open request object. It will
only hold the token when explicitly instructed to do so, via
the ROCLS field in the Request Descriptor (REO).

descriptor. The BSI device interface software needs to build
different types of REQ Descriptors when queuing a frame
such that:
• A single frame request object is generated when the
queue is empty
• The resulting request object is limited to a maximum size
• Optionally the resulting request object is closed whenever a service opportunity is detected.
The following pseudo-code may be used to satisfy the
above requirements.
Transmit Logic
Rell-Size = Req_Size + 1
if Queued-Cnt = 0
mark as REQ.ONLY
Ope"--Req = FALSE
Queued_Cnt = 1
RE
• How to handle queue "wraps"
• How to detect boundary conditions (empty queue, full
queue)

• Each active Indicate Channel should have at least two
buffers placed on its PSP queue. With only one buffer,
the BSI device will immediately raise the Low Data Space
attention bit for that channel.
The host software must maintain its own pOinter and limit
variables for each queue. For REO and PSP queues, the
limit variable should reference the next available queue slot
for writing a new descriptor; while the pOinter variable
should correspond to the pointer variable on BSI device. For
CNF and lOUD queues, the software pointer should reference the next queue slot to be used when reading a new
descriptor. The software limit variable must always reflect
the limit variable on the BSI device. The software pointer
variable must be maintained independently from the BSI device queue pointer.

7.1 Queue Organization
A BSI device queue consists of a contiguous block of BSI
device addressable memory logically sub-divided into eight
byte queue slots. Oueues sized at 1 kbytes must be aligned
on 1 kbyte boundaries, while queues sized at 4 kbytes must
be aligned on 4 kbytes boundaries.
The BSI device embodies two indexing variables for each
queue: a pOinter to the next available queue position to
read or write (stored in BSI device Pointer RAM) and a
queue limit (stored in BSI device Limit RAM). The BSI device increments the pointer variable after reading from a
queue or writing to a queue. The host software may control
channel operation by manipulating the value of the limit variable. With this in mind there are a few simple rules governing queue manipulation by the BSI device.

To initialize queues that the BSI device writes (lOUD, CNF)
one must set the limit variable to reference the penultimate
available queue slot (required due to pipelining). For example, to make all but one of the queue slots available one
could set the pOinter variable to reference the first queue
slot and the limit variable to reference the "next to the next
to the last" queue slot. Also, one should clear the queue
area by overwriting it with binary zeroes; effectively marking
all queue slots as "null descriptors".
See Figure 5 for a pictorial description of initialized queues.
7.3 Queue "Wraps"
Upon reaching the end of the queue memory block, queue
indexing variables "wrap" to the beginning of the queue
memory block. The BSI device automatically performs
queue "wraps" for pointer variables; while the host software
must perform queue "wraps" for limit variables and software queue pointers. The method for calculating the next

6. Read operations are triggered by Limit RAM updates.
There are also some special considerations caused by the
pipe lined processing of CNF, lOUD and PSP Descriptors.
• The BSI device may generate two additional CNF/IDUD
Descriptors after detecting pointer/limit equality. It is
necessary to set the limit value such that it references
the penultimate available queue slot.
hardware/software

hardware/software

CNF

PSP

null

~

lOUD
null

null

null

null

null

null

null

null

null

null

null

null

null

null
null

nutl
null

~

o

7.2 Queue Initialization
To initialize queues that the BSI device reads (REO, PSP)
simply set the pointer (BSI device and software versions)
and software limit to reference the first queue slot. Do not
update the queue's Limit RAM Register until actually queuing the queue's first descriptor.

1. Pointer and limit variables reference a given queue slot by
pointing to the first word of the descriptor.
2. The pOinter variable always pOints to the next available
position on the queue.
3. The BSI device always increments the pointer variable
after a read or write operation.
4. The BSI device halts channel processing when the pointer and limit variables are logically equal.
5. The BSI device tests for pointer/limit equality during
queue read operations (REO, PSP) and after queue write
operations (lOUD, CNF). When detecting pointer/limit
equality during a read operation, the current read operation and no further read operations are made.

~

Z

cj

null

null

null

null

null

null

null

null

null

~

null
null
null

hardware/software

hardwa.re/software

TL/F/11088-5

FIGURE 5. Suggested Queue Initialization

4-107

II

queue position is dependent upon the form of data representation that the host software uses (i.e., BSI device addressable pOinters, queue byte offset, ... ). For example,
when representing the limit variable as a queue offset one
could use simple modulo arithmetic. When the limit variable
is maintained as a pointer into BSI device addressable
memory the host software might use the following method
to increment the variable (specified with C code using
4 kbyte queues).
new = «old + 8)& Oxfff) + (old & OxOffffOOO)
7.4 Detecting Boundary Conditions
The BSI device detects both queue empty (when reading)
and queue full conditions (when writing) by testing for pointer/limit variable equality. As noted above, this test is done
during read operations and after write operations.

REQ/PSP
Queue

When reading, a queue empty condition cannot be determined by comparing the pointer and limit variables. Instead
the host software may recognize the presence of a "null
descriptor" on the queue. To ensure that there will always
be at least one "null descriptor" to demarcate the queue
empty condition; the host software must never set the limit
variable to indicate that all of the queue slots are available
and must mark each available queue slot as a "null description" (binary zeroes are recommended).
The host software can detect a queue full condition using
the same basic mechanism as the BSI device. When writing,
a queue may be considered full when the software limit
pointer references the queue slot immediately "before" the
slot referenced by the software pOinter variable. Queue
"wraps" must be taken into account in the queue variable
arithmetic.
See Figure 6 for a graphical representation of the various
queue boundary conditions.

REQ/PSP
Queue

CNF/IDUD
Queue

CNF/IDUD
Queue

null
null
null

851 device sees
Empty Queue

null

O.Req

null

F.Req

null

null

null

null

null

null

oS

Host sees
Full Queue

Host sees
Empty Queue

null

aSI device sees
Full Queue

TLlF/11088-6

FIGURE 6. Queue Boundary Conditions

4-108

Layout Recommendations
for a System Using
National's FOOl Chip Set

National Semiconductor
Application Note 674
Bruce Wolfson

This application note covers basic PCB layout recommen·
dations and design techniques for high speed signal distri·
bution in National's FDDI system. Due to the high signal
speeds in FDDI, proper layout is critical. Many digital design·
ers are not aware of problems that can arise in a high speed
system from improper routing, incorrect termination, and
poor power and ground layout.

the differential ECl signals. In National's FDDI chip set
these include the following:
• 125 MHz and 12.5 MHz ECl clocks from the DP83241
(CDDTM device)
• Receive Data and Receive Clock from the DP83231
(CRDTM device)
• Data to and from the fiber optic transceiver, and

ROUTING
Line reflections are a reflection of the signal waveform in a
transmission line. They are caused by a difference in imped·
ance between the transmission line and the load at the end
of the line. If the line propagation delay is small compared to
the rise time of the signal, the reflection is hidden during the
rise time and is not seen as overshoot or ringing. However
with the fast edge rates of the signals in a FDDI system, the
line length becomes critical. The distortion that results from
reflections can give false triggering or data errors. The sig.
nals most susceptible to reflections in a FDDI system are

o

DP83251/55

• loopback data from the DP83251 155 (PLAYERTM
device)
It is imperative that these signal lines be kept as short as
possible. To achieve this, the DP83241 should be placed
close to the DP83251 155, the DP83231 should be placed
close to the fiber optic receiver and the DP83251/55, and
the fiber optiC transmitter should be placed close to the
DP83251/55 (Figures 1 and 2). The pinout of the
PLAYER device determines the placement of the CDD and
CRD devices. All the ECl signals that travel between these
devices line up perfectly. To keep the ECl signals traveling
between these three devices as short as possible, the CDD
and CRD devices should be oriented with pin 1 facing the

TBC :I:

~

TBC :I:

TXC :I:

~

TXC :I:

o

DP83241

TXD :I:

...

LBO :I:

RXD :I:

~

RXC :I:

~

FOTX

LBO :I:
RXD :I:

o

DP83231

RXC :I:
DATA :I:

...

FORX
TL/F/10790-1

FIGURE 1. Recommended Component Placement for a Single Attach Station (SAS)

4-109

o

DP83251/55

TBC :I:

+-

TXC:I:

.-

TXD :I:

•

LBO :I:

rOTX

LBO :I:
RXD :I:

RXD :I:

RXC :I:

RXC :I: .

o

DP83231
DATA :I:

•

rORX

TBC :I:

o

DP83241'

TXC :I:

TBC :I:

TXC :I:

o

DP83251/55

.- t.-

TXD :I:

...

LBO :I:

rOTX

LBO :I:
RXD :I:

RXD :I:

RXC :I:

RXC :I:

o

DP83231
DATA :I:

•

FORX
TLlF/l0790-2

'See DP83241 Datasheet for driving multiple DP83251 155 devices.

FIGURE 2. Recommended Component Placement for a Dual Attach Station (DAS)

4-110

PLAYER device. In addition, the PLAYER device must have
its ECl signals facing toward the fiber optic transceiver.

but the orientation was chosen to allow an easy connection
to the system interface, the control logic and the PLAYER
device. Since the system interface logic is on the end of the
board opposite the fiber optic transceiver, it was logical to
have these signals facing that end of the board. It also allowed the control signals of the BMAC device to be near the
control signals of the PLAYER device. All the TTL signals in
this design can be autorouted. However, none of these signals should pass through the CDD or CRD device circuitry
areas to avoid the possibility of noise due to crosstalk. In a
Dual Attach Station (DAS) or a Concentrator design, the
CRD device should still be placed as close as possible to
the PLAYER device but the one CDD device responsible for
clocking all the PLAYER and BMAC devices should be
placed so as to minimize the skews between each PHY
layer. More information regarding the CDD device driving
multiple PLAYER devices can be found in the DP83241 datashee!.

A Single Attach Station (SAS) in an AT form factor was
chosen to demonstrate recommended chip placement and
signal routing. Figures 3 through 7 show the basic connections between National's FDDI chips in a Single Attach Station. The silkscreen showing chip and component placement is shown in Figure 8 and the actual signal traces are
shown in Figure 9. The FOTX and FORX placement is set
by the PMD specification. The CDD, CRD and PLAYER devices should be placed as described in the previous paragraph. However, due to the constraints of the AT form factor, it is necessary to rotate the CDD device and its external
components 90 degrees counter clockwise. The only remaining chip to be placed was the DP83261, BMACTM device. Once again the form factor determined the placement,

CONTROL BUS

CONTROL DATA
CONTROL ADDRESS

1

CONTROL SIGNALS

~
TXD :!:

FOTX

TXE
MAC INDICATE

PHY INDICATE

lBD :!:

BMAC

!

PLAYER

MAC REQUEST

PHY REQUEST

DATA :!:

RXC :!:
RXD :!:

CRO

SO :!:

FORX

TTlSD

LSC

I

LBC

ClK DEl

I

CRD CONTROL SIGNALS
L---

I--

COO

TXC:!:

TBC :!:

TL/F/10790-3

FIGURE 3. Basic Block Diagram of a Single Attach Station Using National's FOOl Chips

4-111

~
,....
CD
Z•

To BMAC
device

900n



z

APPENDIX A
ECl DESIGN GUIDE:
TRANSMISSION liNE CONCEPTS

CD
..,.
.,..
I

(eq.3)
Lo = IlZo
II
(eq.4)
Co=Zo
More formal treatments of transmission line characteristics,
including loss effects, are available from many sources. 1- 3

INTRODUCTION
The interactions between wiring and circuitry in high-speed
systems are more easily determined by treating the interconnections as transmission lines. A brief review of basic
concepts is presented and simplified methods of analysis
are used to examine situations commonly encountered in
digital systems. Since the principles and methods apply to
any type of logic circuit, normalized pulse amplitudes are
used in sample waveforms and calculations.

TERMINATION AND REFLECTION
A transmission line with a terminating resistor is shown in
Figure t. As indicated, a positive step function voltage travels from left to right. To keep track of reflection polarities, it
is convenient to consider the lower conductor as the voltage
reference and to think in terms of current flow in the top
conductor only. The generator is assumed to have zero internal impedance. The initial current 11 is determined by V1
and Zoo

SIMPLIFYING ASSUMPTIONS
For the great majority of interconnections in digital systems,
the resistance of the conductors is much less than the input
and output resistance of the circuits. Similarly, the insulating
materials have very good dielectric properties. These circumstances allow such factors as attenuation, phase distortion, and bandwidth limitations to be ignored. With these
simplifications, interconnections can be dealt with in terms
of characteristic impedance and propagation delay.

V1,h ---..

,.~

CHARACTERISTIC IMPEDANCE
The two conductors that interconnect a pair of circuits have
distributed series inductance and distributed capacitance
between them, and thus constitute a transmission line.
For any length in which these distributed parameters are
constant, the pair of conductors have a characteristic impedance Zoo Whereas quiescent conditions on the line are
determined by the circuits and terminations, Zo is the ratio
of transient voltage to transient current passing by a point
on the line when a signal charge or other electrical disturbance occurs. The relationship between transient voltage,
transient current, characteristic impedance, and the distributed parameters is expressed as follows:

~=

Zo =

I

[CO
'iCc

1.=.'2

zo

--v~1 l)
I,

RT

DELAV=T= lb
TL/F/l0790-14

FIGURE 1. Assigned Polarities and
Directions for Determining Reflections
If the terminating resistor matches the line impedance, the
ratio of voltage to current traveling along the line is matched
by the ratio of voltage to current which must, by Ohm's law,
always prevail at RT. From the viewpoint of the voltage step
generator, no adjustment of output current is ever required;
the situation is as though the transmission line never existed
and RT had been connected directly across the terminals of
the generator. From the RT viewpoint, the only thing the line
did was delay the arrival of the voltage step by the amount
of time T.
When RT is not equal to Zo, the initial current starting down
the line is still determined by V1 and Zo but the final steady
state current, after all reflections have died out, is determined by V1 and RT (ohmic resistance of the line is assumed to be negligible). The ratio of voltage to current in the
initial wave is not equal to the ratio of voltage to current
demanded by RT. Therefore, at the instant the initial wave
arrives at RT, another voltage and current wave must be
generated so that Ohm's law is satisfied at the lineload interface. This reflected wave, indicated by Vr and Ir in
Figure t, starts to return toward the generator. Applying

(eq.1)

PROPAGATION VELOCITY
Propagation velocity v and its reciprocal, delay per unit
length II, can also be expressed in terms of Lo and Co. A
consistent set of units is nanoseconds, microhenries and
picofarads, with a common unit of length.
II = ~LoCo

v,

LINE LENGTH = I

where La = inductance per unit length, Co = capacitance
per unit length. Zo is in ohms, Lo in Henries, Co in Farads.

1
v = ~LoCo

-

1._

(eq.2)

Equations t and 2 provide a convenient means of determining the La and Co, of a line when delay, length and impedance are known. For a length I and delay T, II is the ratio TIl.
To determine Lo and Co, combine Equations t and 2.

4-117

greater than ZOo In turn, this means that the initial current I,
is larger than the final quiescent current, dictated by V, and
RT. Hence, Ir must oppose I, to reduce the line current to
the final'quiescent value. Similar reasoning shows that if V,
is negative, I, flows in the same direction as I,.

Kirchoff's laws to the end of the line at the instant the initial
wave arrives, results in the following.
I, + I, = IT = current into RT
(eq. 5)
Since only one voltage can exist at the end of the line at this
instant of time, the following is true:
V, + V, = VT
VT
V, + V,
IT = RT = ~

thus

V,

It is sometimes easier to determine the effect of Vr on line
conditions by thinking of it as an independent voltage generator in series with RT. With this concept, the direction of I, is
immediately apparent; its magnitude, however, is the ratio of
V, to Zo, i.e., RT is already accounted for in the magnitude of
V,. The relationships between incident and reflected Signals
are represented in Figure 2 for both cases of mismatch between RT and Zoo
The incident wave is shown in Figure 2a, before it has
reached the end of the line. In Figure 2b, a positive V, is
returning to the generator. To the left of V, the current is still
I" flowing to the right, while to the right of V, the net current
in the line is the difference between I, and I,. In Figure 2c,
the reflection coefficient is negative, producing a negative
V,. This, in turn, causes an increase in the amount of current
flowing to the right behind the V, wave.

(eq. 6)

V,

I, = - and I, = - Zo
Zo
with the minus sign indicating that V" is moving toward the
generator.
Combining the foregoing relationships algebraically and
solving for V, yields a simplified expression in terms of V"
Zo and RT.
also

V, _ V, = V, + V, = V, + V,
Zo
Zo
RT
RT
RT

V,

(2. - ...!.-)
Zo

RT

=

V,

(...!.+ 2.)
RT
Zo

(eq.7)

~II--__

V, = V, (RT - Zo) = PL V,
RT + Zo
The term in parenthesis is called the coefficient of reflection
p. With RT ranging between zero (shorted line) and infinity
(open line), the coefficient ranges between -1 and + 1 respectively. The subscript L indicates that P refers to the
coefficient at the load end of the line.
Equation 7 expresses the amount of voltage sent back
down the line, and since
VT = V, + V,
(eq.8)

I Zo

(eq.9)

The foregoing has the same form as a simple voltage divider involving a generator V, with internal impedance Zo driving a load RT, except that the amplitude of VT is doubled.
The arrow indicating the direction of V, in Figure 1 correctly
indicates the V, direction of travel, but the direction of I, flow
depends on the V, polarity. If V, is positive, I, flows toward
the generator, opposing I,. This relationship between the
polarity of V, and the direction of I, can be deduced by noting in Equation 7 that if V, is positive it is because RT is

TL/F/l0790-17

c. Reflected Wave for Rr < Zo
FIGURE 2. Reflections for Rr Zo

'*

4-118

SOURCE IMPEDANCE, MULTIPLE REFLECTIONS

ducing Rs (Figure 3) to 130. increases Ps to -0.75V, and
the effects are illustrated in Figure 4. The initial value of VT
is 1.BV with a reflection of 0.9V from the open end. When
this reflection reaches the source, a reflection of 0.9V x
-0.75V starts back toward the open end. Thus, the second
increment of voltage arriving at the open end is negative
going. In turn, a negative-going reflection of 0.9V x -0.75V
starts back toward the source. This negative increment is
again multiplied by -0.75 at the source and returned
toward the open end. It can be deduced that the difference
in amplitude between the first two positive peaks observed
at the open end is

When a reflected voltage arrives back at the source (generator), the reflection coefficient at the source determines the
response to Yr. The coefficient of reflection at the source is
governed by Zo and the source resistance Rs.
Rs - Zo
Ps = Rs + 20

(eq.10)

If the source impedance matches the line impedance, a reflected voltage arriving at the source is not reflected back
toward the load end. Voltage and current on the line are
stable with the following values.

PU V1 - (1 + PU V1 p2L p 2s
(eq.12)
PU V1 (1 - p2L p 2sl.
The factor (1 - p2L p 2s) is similar to the damping factor
associated with lumped constant circuitry. It expresses the
attenuation of successive positive or negative peaks of ringing.

(eq.11)

VT - V'T = (1
= (1

If neither source impedance nor terminating impedance
matches Zo, multiple reflections occur; the voltage at each
end of the line comes closer to the final steady state value
with each succeeding reflection. An example of a line mismatched on both ends is shown in Figure 3. The source is a
step function of 1V amplitude occurring at time to. The initial
value of V1 starting down the line is 0.75V due to the voltage divider action of 20 and Rs. The time scale in the photograph shows that the line delay is approximately 6 ns. Since
neither end of the line is terminated in its characteristic impedance, multiple reflections occur.

+
+

-

The amplitude and persistence of the ringing shown in Figure 3 become greater with increasing mismatch between
the line impedance and source and load impedances. Re-

Vr

- v,

Zo=930

RT= co

1

VT
H =20 nsldiv
V=0.4 V/div

TL/F/l0790-1B

31 - 93
+ 93 = -0.5

PS = 31
I ..

mtlally:

v,

TL/F/l0790-20

"" - 93
PL=""+93=+1

FIGURE 4. Extended Ringing when Rs
of Figure 31s Reduced to 130.

Zo
93
= Zo + Rs • Vo = 124'1 = 0.7SV

LATTICE DIAGRAM
In the presence of multiple reflections, keeping track of the
incremental waves on the line and the net voltage at the
ends becomes a bookkeeping chore. A convenient and systematic method of indicating the conditions which combines
magnitude, polarity and time utilizes a graphic construction
called a lattice diagram.4 A lattice diagram for the line conditions of Figure 3 is shown in Figure 5.
The vertical lines symbolize discontinuity pOints, in this case
the ends of the line. A time scale is marked off on each line
in increments of 2T, starting at to for V1 and T for VT. The
diagonal lines indicate the incremental voltages traveling
between the ends of the line; solid lines are used for positive voltages and dashed lines for negative. It is helpful to
write the reflection and transmission multipliers p and
(1 + p) at each vertical line, and to tabulate the incremental
and net voltages in columns alongside the vertical lines.
Both the lattice diagram and the waveform photograph
show that VI and VT asymptotically approach 1V, as they
must with a 1V source driving an open-ended line.

Vr

v,

H =20 ns/div
V =0.5 V/div
TL/F/l0790-19

FIGURE 3. Multiple Reflections Due to
Mismatch at Load and Source

4-119

.

l>
Z

en
.....
-'="

~

r---------------------------------------------------------------------------

CD

- -

VT

V,

Z
c(
SUM:

:+0.76 V

+ 0.375 V
+1.125V

~
+0.937V

- P=+1

p= -0.5

(Hp)- +0.6

1=10

(1 +p)_

+2
SUM:

T

+1.60V

3T

-0.75 V
+0.75 V

5T

+0.375 V
+ 1.125 V

7T

~::~:;:

9T

+0.094 V
+1.031 V

2T

4T

+ 0.094 V
+1.031 V

8T

-0.047 V
+ G.984 V

8T

TLlF/l0790-21

FIGURE 5. lattice Diagram for the Circuit of Figure 3
SHORTED LINE
The open-ended line in Figure 3 has a reflection coefficient
of + 1 and the successive reflections tend toward the
steady state conditions of zero line current and a line voltage equal to the source voltage. In contrast, a shorted line
has a reflection coefficient of -1 and successive reflections
must cause the line conditions to approach the steady state
conditions of zero voltage and a line current determined by
the source voltage and resistance.
Shorted line conditions are shown in Figure 6a with the reflection coefficient at the source end of the line also negative. A negative coefficient at both ends of the line means
that any voltage approaching either end of the line is reflected in the opposite polarity. Figure 6b shows the response to
an input step-function with a duration much longer than the

line delay. The initial voltage starting down the line is about
+ 0.75V, which is inverted at the shorted end and returned
toward the source as -0.75V. Arriving back at the source
end of the line, this voltage is multiplied by (1 + ps), causing a -0.37V net change in V1. Concurrently, a reflected
voltage of +0.37V (-0.75V times Ps of -0.5) starts back
toward the shorted end of the line. The voltage at V 1 is
reduced by 50% with each successive round trip of reflections, thus leading to the final condition of zero volts on the
line.
When the duration of the input pulse is less than the delay
of the line, the reflections observed at the source end of the
line constitute a train of negative pulses, as shown in Figure
6e. The amplitude decreases by 50% with each successive
occurrence as it did in Figure 6b.

TLlF/l0790-99

0-93
PL ~ 0 + 93 ~ -1

PS ~ -0.5

a. Reflection Coefficients for Shorted Line

v,
v,
H = 10nsldiv
V=O.2 V/dlv

H= 10 ns/div
V=O.2 V/dlv

TLlF/l0790-23

TL/F110790-22

b. Input Pulse Duration

> Line Delay

c. Input Pulse Duration

FIGURE 6. Reflections of Long and Short Pulses on a Shorted Line

4-120

< Line Delay

EXTRA DELAY WITH TERMINATION
CAPACITANCE
DeSigners should consider the effect of the load capacitance at the end of the line when using series termination.
Figure 9 shows how the output waveform changes with increasing load capacitance. Figure 9b shows the effect of
load capacitances of 0, 12, 24, 48 pF. With no load, the
delay between the 50% pOints of the input and output is just
the line delay T. A capacitive load at the end of the line
causes an extra delay I!o.T due to the increase in rise time of
the output signal. The midpoint of the output is used as a
criterion because the propagation delay of an ECl circuit is
measured between the 50% points of the input and output
signals.

SERIES TERMINATION
Driving an open-ended line through a source resistance
equal to the line impedance is called series termination. It is
particularly useful when transmitting signals which originate
on a PC board and travel through the backplane to another
board, with the attendant discontinuities, since reflections
coming back to the source are absorbed and ringing thereby
controlled. Agure 1 shows a 930 line driven from a 1V generator through a source impedance of 930. The photograph
illustrates that the amplitude of the initial signal sent down
the line is only half of the generator voltage, while the voltage at the open end of the line is doubled to full amplitude
(1 + PL = 2). The reflected voltage arriving back at the
source raises VItO the full amplitude of the generator signal. Since the reflection coefficient at the source is zero, no
further changes occur and the line voltage is equal to the
generator voltage. Because the initial signal on the line is
only half the normal signal swing, the loads must be connected at or near the end of the line to avoid receiving a 2step input signal.
An ECL output driving a series terminated line requires a
pull-down resistor to VEE, as indicated in Figure 8. The resistor Ro shown in Figure 8 symbolizes the output resistance of the EeL gate. The relationships between Ro, RS, RE
and Zo are discussed in Appendix B.

TUF/l0790-27

a. Series Terminated line with load Capacitance

TUF/l0790-24

HI::1 ns/div
V=O.2 Vldlv

TL/F/l0790-28

b. Output Rise Time Increase with
Increasing load Capacitance

O%
~

LINE

INPUT

LINE
OUTPUT

H=1D nsldiv

V=O.4V/dlv

TLlF/l0790-29

TUF/l0790-25

c. Extra Delay I!o. T Due to Rise Time Increase

FIGURE 7. Series Terminated line and Waveforms
AS

T

FIGURE 9. Extra Delay with Termination Capacitance

Zo

TUF/l0790-26

FIGURE 8. ECl Element Driving
a Series Terminated line

4-121

~

"'CD

:Z
c(

r-------------------------------------------------------------------------------~

V~N (I)

The increase in propagation delay can be calculated by using a ramp approximation for the incident voltage and characterizing the circuit as a fixed impedance in series with the
load capacitance, as shown in Figure 10. One general solution serves both series and parallel termination cases by
using an impedance Z' and a time constant T, defined in
Figure 10a and 10b. Calculated and observed increases in
delay time to the 50% point show close agreement when T
is less than half the ramp time. At large ratios of Tla (where
a = ramp time), measured delays exceed calculated values
by approximately 7%. Figure 11, based on measured values, shows the increase in delay to the 50% point as a
function of the Z'C time constant, both normalized to the
10% to 90% rise time of the input signal. As an example of
using the graph, consider a 1oon series terminated line with
30 pF load capacitance at the end of the line and a no-load
rise time of 3 ns for the input signal. From Figure 10a, Z' is
equal to 100n; the ratio Z'Clt, is 1. From the graph, the
ratio AT It, is 0.8. Thus the increase in the delay to the 50%
point of the output waveform is 0.8 t" or 2.4 ns, which is
then added to the no-load line delay T to determine the total
delay.
Had the 100n line in the foregoing example been parallel
rather than series terminated at the end of the line, Z' would
be 50n. The added delay would be only 1.35 ns with the
same 30 pF loading at the end. The added delay would be
only 0.75 ns if the line were 50n and parallel terminaled.
The various trade-offs involving type of termination, line impedance, and loading are important considerations for crilical delay paths.

-_zo'---l""

r

TLlF/10790-30

a. Thevenln Equivalent for
Series Terminated Case

z'=~

Zo

2

V'N ( I ) l 1
C

1,.-1'-...

VIN(I)~·i
C

RT=Zo~

~

T=Z'C=ZoC

2

~

I

Vo

~

TLlF/l0790-31

b. Thevenin Equivalent for
Parallel Terminated Case

v
1,=0.88
8=1.251,

I

1=0

1=8
TLlFI1 0790-32

Vin(t) =

a[tu(t) V

Ofor I <
u(t) = 1 for t >

(t - a)u (I - a))

a
a

2.5

~I

u(t - a) = Ofort < a,
1forl>a

N

V

:e
"
a:

1.5

z

iii

en
~
a:

T(1 - e- tlT )) u(t)

1.0

V

u

~

5w

V
--[(I-a)

a

0.5

0

!.=.!

o

/'

/

0

V
1
Vc(S) = - .
(1 - e- as)
ar s2(s+1/T)

aV [I -

7

::i

VIN(S) = as2 (1 - e- as)

vc(t) =

2.0

0

W

/

./

/

1/

0.5
1.0
1.5
2.0
2.5
LINE·LOAD TIME CONSTANT, NORMALlZED-Z'CIt,

- T(1 - e)1 u (I - a)
c. Equations for Input and Output Voltages
T

TLlF110790-33

FIGURE 11. Increase in 50% Point Delay Due
to Capacitive Loading at the End
of the Line, Normalized to T r

FIGURE 10. Determining the Effect
of End-of-Line Capacitance

4-122

DISTRIBUTED LOADING EFFECTS ON
LINE CHARACTERISTICS

This analogy is strengthened by observing the effect of reducing RT from 930 to 750, which leads to the middle
waveform of Figure 12c. Note that the final (steady state)
value of the line voltage is reduced by about the same
amount as that caused by the capacitive reflections. In the
lower trace of Figure 12c the source resistance Rs is reduced from 930 to 750, restoring both the initial and final
line voltage values to the same amplitude as the final value
in the upper trace. From the standpoint of providing a desired signal voltage on the line and impedance matching at
either end, the effect of distributed capacitive loading can
be treated as a reduction in line impedance.
The reduced line impedance can be calculated by considering the load capacitance CL as an increase in the intrinsic
line capacitance Co along that portion of the line where the
loads are connected. 6 Denoting this length of line as I, the
distributed value Co of the load capacitance is as follows.

When capacitive loads such as ECL inputs are connected
along a transmission line, each one causes a reflection with
a polarity opposite to that of the incident wave. Reflections
from two adjacent loads tend to overlap if the time required
for the incident wave to travel from one load to the next is
equal to or less than the signal rise time. s Figure 12a illustrates an arrangement for observing the effects of capacitive loading, while Figure 12b shows an incident wave followed by reflections from two capacitive loads. The two capacitors causing the reflections are separated by a distance
requiring a travel time of 1 ns. The two reflections return to
the source 2 ns apart, since it takes 1 ns longer for the
incident wave to reach the second capacitor and an additional 1 ns for the second reflection to travel back to the
source. In the upper trace of Figure 12b, the input signal rise
time is 1 ns and there are two distinct reflections, although
the trailing edge of the first overlaps the leading edge of the
second. The input rise time is longer in the middle trace,
causing a greater overlap. In the lower trace, the 2 ns input
rise time causes the two reflections to merge and appear as
a single reflection which is relatively constant (at ::::: -10%)
for half its duration. This is about the same reflection that
would occur if the 930 line had a middle section with an
impedance reduced to 750.
With a number of capacitors distributed all along the line of
Figure 12a, the combined reflections modify the observed
input waveform as shown in the top trace of Figure 12c. The
reflections persist for a time equal to the 2-way line delay
(15 ns), after which the line voltage attains its final value.
The waveform suggests a line terminated with a resistance
greater than its characteristic impedance (RT > Zo).
RS=93Q

Co is then added to Co in Equation
duced line impedance Zoo
Z'

-

{TO _~

o - ,,~ -

Co (

1 to determine the re-

Lo

CD)
1+Co

(eq.13)

fCO

Z'

+

VCo

=

Zo

°RH
1 +....Q

Co

1 +....Q

Co

Zo=93Q

I
Vo
2V

I

.1.

! I

TLlF/l0790-34

a. Arrangement for Observing Capacitive Loading Effects

.. Rs=Rl=
93 ~!
Rs=93~!

+-Rr=7Stl
.. Rs=RT=
75 n

H=2ns/div
V = 0.25 V/div

H =5nsldlv
V =0.25 V/dlv

TL/F/l0790-35

TL/F/l0790-36

b. Capacitive Reflections Merging
as Rise Time Increases

c. Matching the Altered Impedance
of a Capacitively Loaded Line

FIGURE 12. Capacitive Reflections and Effects on Line Characteristics

4-123

•

.... ,---------------------------------------------------------------------------------,
In the example of Figure 12c, the total load capacitance is
MISMATCHED LINES
~

~

z
cc

33 pF while the total intrinsic line capacitance lCo is 60 pF.
(Note that the ratio ColCo is the same as Cll/CO.) The
calculated value of the reduced impedance is thus
93
93
Z'o = g 3 = ff.55 = 750
(eq.14)
1+60
This correlates with the results observed in Figure 12c when
RT and Rs are reduced to 750.
The distributed load capacitance also increases the line delay, which can be calculated from Equation 2.

8' =

~Lo(Co + Co) = ~LoCo~1 + ~~

Reflections occur not only from mismatched load and
source impedances but also from changes in line impedance. These changes could be caused by bends in coaxial
cable, unshielded twisted-pair in contact with metal, or mismatch between PC board traces and backplane wiring. With
the coax or twisted-pair, line impedance changes run about
5% to 10% and reflections are usually no problem since the
percent reflection is roughly half the percent change in impedance. However, between PC board and backplane wiring, the mismatch can be 2 or 3 to 1. This is illustrated in
Figure 14 and analyzed in the lattice diagram of Figure 15.
Line 1 is driven in the series terminated mode so that reflections coming back to the source are absorbed.
The reflection and transmission at the pOint where impedances differ are determined by treating the downstream line
as though it were a terminating resistor. For the example of
Figure 14, the reflection coefficient at the intersection of
lines 1 and 2 for a signal traveling to the right is as follows.
Z2 - ZI
93 - 50
P12 = - - - - - = - - = +0.3
(eq.18)
Z2 + ZI
143
Thus the signal reflected back toward the source and the
signal continuing along line 2 are, respectively, as follows.

(eq.15)

=8~1 + CD

Co
The line used in the example of Figure 12c has an intrinsic
delay of 6 ns and a loaded delay of 7.5 ns which checks
with Equation 15.

18'

=

18 ff.55

= 6

ff.55 =

7.5 ns

(eq.16)

Equation 15 can be used to predict the delay for a given line

and load. The ratio ColCo (hence the loading effect) can be
minimized for a given loading by using a line with a high
intrinsic capacitance Co.
A plot of Z' and 8' for a 500 line as a function of CD is
shown in Figure 13. This figure illustrates that relatively
modest amounts of load capacitance will add appreciably to
the propagation delay of a line. In addition, the characteristic impedance is reduced significantly.
8

~

\

/

/'

L.J=-"V

V

Vlr= P12Vl = +0.3Vl
(eq.19a)
V2 = (1 + P12) VI = + 1.3 VI
(eq.19b)
At the intersection of lines 2 and 3, the reflection coefficient
for signals traveling to the right is determined by treating Za
as a terminating resistor.
Za-Z239-93
P23 = - - - - - = - - = -0.41
(eq.20)
Za + Z2
132
When V2 arrives at this pOint, the reflected and transmitted
signals are as follows.

80

co
I

50i

V2r = P23 V2= -0.41 V2
= (-0.41) (1.3) VI
= -0.53Vl

6' =1.778n8l11
CD=2.8pFlin 40~

"!

/

()

~ r-....

10

-

30
20

V3 = (1 + P2a) V2 = 0.59 V2
= (0.59)(1.3) VI
(eq.21b)
= 0.77 VI
Voltage V3 is doubled in magnitude when it arrives at the
open-ended output, since Pl is + 1. This effectively cancels
the voltage divider action between Rs and ZI.

~

~

II:

:l!

ZD'

20

iii

()

10 I

~

o

V4 = (1 + pu V3 = (1 + Pu (1 + P2a) V2
= (1 + pu (1 + P23)(1 + P12) VI

30

CD- DISTRIBUTED CAPACITANCE- pFlln

(eq.22)

Vo
= (1 + pu (1 + P23)(1 + P1V"2

TL/F/l0790-37

FIGURE 13. Capacitive Loading
Effects on Line Delay and Impedance
Worst case reflections from a capacitively loaded section of
transmission line can be accurately predicted by using the
modified impedance of Equation 9. 6 When a signal originates on an unloaded section of line, the effective reflection
coefficient is as follows.
Z'o - Zo
P = Z'o + Zo

(eq.21a)

V4 = (1 + P23) (1 + P12) Vo
Thus, Equation 22 is the general expression for the initial
step of output voltage for three lines when the input is series
terminated and the output is open-ended.

(eq.17)

4-124

Note that the reflection coefficients at the intersections of
lines 1 and 2 and lines 2 and 3 in Figure 15 have reversed
signs for signals traveling to the left. Thus the voltage reflected from the open output and the signal reflecting back
and forth on line 2 both contribute additional increments of
output voltage in the same polarity as Vo. Lines 2 and 3
have the same delay time; therefore, the two aforementioned increments arrive at the output simultaneously at
time 5T on the lattice diagram (Figure 15).
In the general case of series lines with different delay times,
the vertical lines on the lattice diagram should be spaced
apart in the ratio of the respective delays. Figure 16 shows
this for a hypothetical case with delay ratios 1:2:3. For a
sequence of transmission lines with the highest impedRs=500

ance line in the middle, at least three output voltage increments with the same polarity as Vo occur before one can
occur of opposite polarity. On the other hand, if the middle
line has the lowest impedance, the polarity of the second
increment of output voltage is the opposite of Vo. The third
increment of output voltage has the opposite polarity, for
the time delay ratios of Figure 16.
When transmitting logic signals, it is important that the initial
step of line output voltage pass through the threshold region
of the receiving circuit, and that the next two increments of
output voltage augment the initial step. Thus in a series terminated sequence of three mismatched lines, the middle
line should have the highest impedance.

Z,=500

Z,=930

z.,=390

;-~~~~--------~~----------.-----------.. ~==

Ps=o

P12= +0.3
P21= -0.3

P23= -0.41

P32= +0.41
TL/F/l0790-38

H = 2Ons/div

V=0.4 Vldl.

TUF/l0790-39

FIGURE 14_ Reflections from Mismatched Lines

v,

+ 0.50 V

1=0

~
+ 0.55 V

T

P12=+O.3

V3
P23= -0.41

P21

P32= +0.41

V.

p=O

= -0.3

--

V.
PL=1 (1+PLl= +2

2T
+0.77 V

3T
-0.19V
+0.46 V

4T
+O.40Y

5T
+D.35V
+D.8IV

+1.17V

5T

7T
+0.24 V

IT.1"5V

6T
-0.12V
+1.05V

9T

ETC.

TLlF/l0790-40

FIGURE 15_ Lattice Diagram for the Circuit of Figure 14

4-125

•

v~ Tl_.+r•.--T2--...,. .Vt-i'._----T3-----i.~y
taO

...TL/F/l0790-41

FIGURE 16. Lattice Diagram for Three Lines with Delay Ratios 1:2:3
RISE TIME VERSUS LINE DELAY
When the 2-way line delay is less than the rise time of the
input wave, any reflections generated at the end of the line
are returned to the source before the input transition is completed. Assuming that the generator has a finite source resistance, the reflected wave adds algebraically to the input
wave while it is still in transition, thereby changing the shape
of the input. This effect is illustrated in Figure 11, which
shows input and output voltages for several comparative
values of rise time and line delay.
In Figure 11b where the rise time is much shorter than the
line delay, VI rises to an initial value of 1V. At time T later,
VT rises to 0.5V, i.e., 1 + PL = 0.5. The negative reflection
arrives back at the source at time 2T, causing a net change
of -0.4V, i.e., (1 + psI (-0.5) = -0.4.

The net input voltage at any particular time is determined by
adding the reflection to the otherwise unaffected input. It
must be remembered that the reflection arriving back at the
input at a given time is proportional to the input voltage at a
time 2T earlier. The value of V 1 in Figure 11d can be calculated by starting with the 1V input ramp.

1
VI = -et forO"; t ,,;4T

t,

=

1V

~

fort

(eq.23)

4T

The reflection from the end of the line is
V - pdt - 2T).

,-

t,

(eq.24)

'

the portion of the reflection that appears at the input is

The negative coefficient at the source changes the polarity
of the other 0.1 V of the reflection and returns it to the end of
the line, causing VT to go positive by another 50 mV at time
3T. The remaining 50 mV is inverted and reflected back to
the source, where its effect is barely distinguishable as a
small negative change at time 4T.
In Figure 11c, the input rise time (0% to 100%) is increased
to such an extent that the input ramp ends just as the negative reflection arrives back at the source end. Thus the input
rise time is equal to 2T.
The input rise time is increased to 4T in Figure 11d, with the
negative reflection causing a noticeable change in input
slope at about its midpoint. This change in slope is more
visible in the double exposure photo of Figure 11e, which
shows VI (t, still set for 4T) with and without the negative
reflection. The reflection was eliminated by terminating the
line in its characteristic impedance.

V' = (1 + psI pdt - 2T).
,
t,'

(eq.25)

the net value of the input voltage is the sum.
_-.,::2-'-!.T)
v,1_- -t +-,-,(1_+---"-p,,,S)_+-,-,PL::..:(,-,-t
-

t,

t,

(eq.26)

The peak value of the input voltage in Figure 11d is determined by substituting values and letting t equal 4T.
V'I = 1 + (0.8) (-0.5) (4T - 2T)

t,

(eq.27)

= 1 - 0.4 (0.5) = 0.8V

After this peak pOint, the input ramp is no longer increasing
but the reflection is still arriving. Hence the net value of the
input voltage decreases. In this example, the later reflections are too small to be detected and the input voltage is
thus stable after time 6T. For the general case of repeated
reflections, the net voltage Vl(l) seen at the driven end of
the line can be expressed as follows, where the Signal
caused by the generator is VI (I)'

4-126

The voltage at the output end of the line is expressed in a
similar manner.

V'I(t) = Vl(t)

forO < t < 2T
V'I(t) = Vl(t)

+

(1

+

VT(t) = 0

PS) PL Vl(t-2T)

forO<-

T

2T

3T

4T

5T

6T

7T

8T

9T

lOT

l1T

12T

13T
TL/F/l0790-49

c. Net Output Signal Determined by Superposition
FIGURE 18. Basic Relationships Involved in Ringing

4-128

In Figure 18c, the output increments are added algebraically
by superposition. The starting point of each increment is
shifted upward to a voltage value equal to the algebraic sum
of the quiescent levels of all the preceding increments (i.e.,
0, 2B, O.4B, 1.68B, etc.). For time intervals when two ramps
occur simultaneously, the two linear functions add to produce a third ramp that prevails during the overlap time of the
two increments.

are intended to focus attention on the general methods
used to determine the interactions between high-speed logic circuits and their interconnections. Considering an interconnection in terms of distributed rather than lumped inductance and capacitance leads to the line impedance concept,
i.e., mismatch between this characteristic impedance and
the terminations causes reflections and ringing.
Series termination provides a means of absorbing reflections when it is likely that discontinuities and! or line impedance changes will be encountered. A disadvantage is that
the incident wave is only one-half the signal swing, which
limits load placement to the end of the line. ECl input capacitance increases the rise time at the end of the line, thus
increasing the effective delay. With parallel termination, i.e.,
at the end of the line, loads can be distributed along the line.
ECl input capacitance modifies the line characteristics and
should be taken into account when determining line delay.

It is apparent from the geometric relationships, that if the
ramp time A is less than twice the line delay, the first output
increment has time to rise to the full 2B amplitude and the
second increment reduces the net output voltage to O.4B.
Conversely, if the line delay is very short compared to the
ramp time, the excursions about the final value VG are
small.

Agure 18c shows that the peak of each excursion is
reached when the earlier of the two constituent ramps
reaches its maximum value, with the result that the first
peak occurs at time A. This is because the earlier ramp has
a greater slope (absolute value) than the one that follows.

REFERENCES
1. Metzger, G. and Vabre, J., Transmission Lines with Pulse
EXCitation, Academic Press, (1969).

Actual waveforms such as produced by ECl or TTL do not
have a constant slope and do not start and stop as abruptly
as the ramp used in the example of Figure 18. Predicting the
time at which the peaks of overshoot and undershoot occur
is not as simple as with ramp excitation. A more rigorous
treatment is required, including an expression for the driving
waveform which closely simulates its actual shape. In the
general case, a peak occurs when the sum of the slopes of
the individual signal increment is zero.

2. Skilling, H., Electric Transmission Lines, McGraw-Hili,
(1951).
3. Matick, R., Transmission Lines for Digital and Communication Networks, McGraw-Hili, (1969).
4. Millman, J. and Taub, H., Pulse Digital and Switching
Waveforms, McGraw-Hili, (1965).
5. "Time Domain Reflectometry", Hewlett-Packard Journal,
Vol. 15, No.6, (February 1964).

SUMMARY

6. Feller, A., Kaupp H., and Digiacoma, J., "Crosstalk and
Reflections in High-Speed Digital Systems", Proceedings, Fall Joint Computer Conference, (1965).

The foregoing discussions are by no means an exhaustive
treatment of transmission line characteristics. Rather, they

4-129

~

""CD

:2:

: 5

u

0= 0.1481nslln

z

::;:

;4

(eq.2)

w

u

where d = wire diameter, h = distance from ground to wire
center.
Comparing Equation 1 and 2, the term 0.67 (0.8 w + t)
shows the equivalence between a round wire and a rectangular conductor. The term 0.475 Er + 0.67 is the effective
dielectric constant for microstrip Ee, considering that a microstrip line has a compound dielectric consisting of the
board material and air. The effective dielectric constant is
determined by measuring propagation delay per unit of line
length and using the following relationship.
Il = 1.016. ~ nslft
(eq. 3)

z

~

3

Q

2

::(j<>
:!!
::>
III

iE

Ii;

1

is

I

80

where Il = propagation delay, ns/ft.
Propagation delay is a property of the dielectric material
rather than line width or spacing. The coefficient 1.016 is
the reciprocal of the velocity of light in free space. Propagation delay for microstrip lines on glass-filled G-10 epoxy
boards is typically 1.77 nslft, yielding an effective dielectric
constant of 3.04.

"'"""
-----40

60
80
100
120
Zo - CHARACTERISTIC IMPEDANCE-II
TL/F/l0790-54

FIGURE 3. Mlcrostrlp Distributed Capacitance
Versus Impedance, G-10 Epoxy
Stripline
Stripline conductors are totally embedded. As a result, the
board material determines the dielectric constant. G-10
epoxy boards have a typical propagation delay of 2.26 nslft.
Equation 4 is used to calculate stripline impedances. 1•2

120~'-----r----.-----r----;-,

c:

I
w

Z _ (60) I (
4b
.fEr n 0.67 1T (0.8 w
o-

u

~100~~~--+-----r-----r---~~

+ t)

)

(eq.4)

where b = distance between ground planes, w = trace
width, t = trace thickness, w/(b-t) < 0.35 and lib < 0.25.
Figure 4 shows stripline impedance as a function of trace
width, using Equation 4 and various ground plane separations for G-10 glass-filled epoxy boards. Related values of
Co are plotted in Figure 5 .

w

Do

;;§
u

ti

iE

...
:!!
u
II:

:>:

u
I

co
I
w

~

<>
z

~

70 f--l1r-.....30<4------+------l'-----l

Do

;;§

TUF/l0790-53

<>

ti

FIGURE 2. Microstrip Impedance
Versus Trace Width, G-10 Epoxy

60 ""',---*-.....::!~+-----l-----l

iE

~

Using Er = 5.0 in Equation 1, Figure 2 provides microstrip
line impedance as a function of width for several G-10
epoxy board thicknesses. Figure 3 shows the related Co
values, useful for determining capacitive loading effects on
line characteristics, (Equation 15).

~ 50~---~----~~--~~~~

<>
I
~

~.0~5::-0-......~:::---~~~-~~:O""'~0.025

System designers should ascertain tolerances on board dimensions, dielectric constant and trace width etching in order to determine impedance variations. If conformal coating
is used the effective dielectric constant of microstrip is increased, depending on the coating material and thickness.

TRACE WIDTH - INCHES
TUF/l0790-55

FIGURE 4. Strlpllne Impedance
Versus Trace Width, G-10 Epoxy

4-131

~ r-------------------------------------------------~----------------------------__,

.....

z~
II(

supply can provide the Thevenin equivalent of a single resistor to - 2V if a separate termination supply is not available, Figure 6b. The average power dissipation in the
Thevenin equivalent resistors is about 10 times the power
dissipation in the single resistor returned to - 2V, as shown
in Figures 10 and 13. For either parallel termination method,
decoupling capacitors are required between the supply and
ground (Chapter 6).

:z: 5
~0.188 nslln
~

~

4

......

w

CJ

z

i!

~
~

..

~

3

~
...............

'--....

_ a. Parallel Termination

2

o--~:>-

o
-D• --"-0

II

E

--=......-q

1

is

I
(]

VTT

0

40

Zo -

50
60
70
80
CHARACTERISTIC IMPEDANCE - II

TLlF/t0790-57

TLlF/l0790-56

b. Thevenln Equivalent of RT and Vrr

FIGURE 5. Strlpline Distributed Capacitance
Versus Impedance, G-l0 Epoxy
Wire Wrap

Rl= VEE RT
VEE-VTT
Rl

~~ --f~

Wire-wrap boards are commercially available with three
voltage planes, positions for several 24-pin Dual-In-Line
Packages (DIP), terminating resistors, and decoupling capacitors. The devices are mounted on socket pins and interconnected with twisted pair wiring. One wire at each end of
the twisted pair is wrapped around a signal pin, the other
around a ground pin. The #30 insulated wire is uniformly
twisted to provide a nominal 930 impedance line. Positions
for Single-In-Line Package (SIP) terminating resistors are
close to the inputs to provide good termination characteristics.

VEE

'"

R2= VEE RT

VTT
TL/F/l0790-58

c. Equivalent Circuit for Determining
Approximate VOH and VOL Levels

Stitch Weld

60
EOH= -0.85 v --'"\N'v--. VOH

Stitch-weld boards are commercially available with three
voltage planes and buried resistors between planes. The
devices are mounted on terminals and interconnected with
insulated wires that are welded to the backside of the terminals. The insulated wires are placed on a controlled thickness over the ground plane to provide a nominal impedance
of 500. The boards are available for both DIPs and flatpaks.
Use of flatpaks can increase package density and provide
higher system performance.

EOL=-1.67V

~

Rr
VOL
VTT

811

TL/F/l0790-59

Discrete Wired

d. FlOOK Output Characteristic with Terminating
Resistor RT Returned to Vrr = -2.0V

Custom Multiwire' boards are available with integral power
and ground planes. Wire is placed on a controlled thickness
above the ground plane to obtain a nominal impedance line
of 550. Then holes are drilled through the wire and board.
Copper is deposited in the drilled holes by an additive-electrolysiS process which bonds each wire to the wall of the
holes. Devices are soldered on the board to make connection to the wires.

-0

~ .J/:. SLJPE~8.0~ , ~slopt=aro
I
1 -8 '\ r-..~r--...
I\~ f'., 1'...,
I
...z -12
........ ~=1000
w
\\
-4

II:
II:
:::I

'Multiwire is a registered trademark of the Multiwire Corporation.

...
......

CJ

Parallel Termination
Terminating a line at the receiving end with a resistance
equal to the characteristic line impedance is called parallel
termination, Figure 6a. FlOOK circuits do not have internal
pull-down resistors on outputs, so the terminating resistor
must be returned to a voltage more negative than VOL to
establish the LOW-state output voltage from the emitter follower. A -2V termination return supply is commonly used.
This minimizes power consumption and correlates with
standard test specifications for ECL circuits. A pair of resistors connected in series between ground (Vee) and the VEE

:::I

\

-20

\

-24

:::I

0

I

I'\.
I\. ['\.

-16

\

..........

"-

1\

-28

\

!; -32

E

RT=2501\

-36
-40
-2.0

VOL

V6Hl

\

~n

'\.RT=500

['.1
"e.~ = 37 j5 0

1

-1.2
-0.6
-0.4
Vour - OUTPUT VOLTAGE - V

-1.6

-0
TLlF/t0790-60

FIGURE 6. Parallel Termination

4-132

Using 15% reflection limits as examples, the range of the
RT/ZO ratio is as follows.

FlOOK output transistors are designed to drive low-impedance loads and have a maximum output current rating of
50 mAo The circuits are specified and tested with a 50D.load
returned to -2V. This gives nominal output levels of
-0.955V at 20.9 mA and -1.705V at 5.9 mAo Output levels
will be different with other load currents because of the transistor output resistance. This resistance is nonlinear with
load current since it is due, in part, to the base-emitter voltage of the emitter follower, which is logarithmic with output
current. With the standard 50D. load, the effective source
resistance is approximately 6D. in the HIGH state and 6D. in
the lOW state.
The foregoing values of output voltage, output current, and
output resistance are used to estimate quiescent output levels with different loads. An equivalent circuit is shown in
Figure 6e. The ECl circuit is assumed to contain two internal voltage sources EOH and EOL with series resistances of
6D. and 6D. respectively. The values shown for EOH and
EOL are -0.65V and -1.67V respectively.

1.15 RT 0.65
RT
- > - > - 1.35>->0.74
(eq.6)
Zo
1.15
Zo
0.65
The permissible range of the RT/ZO ratio determines the
tolerance ranges for RT and ZOo For example, using the
foregoing ratio limits, RT tolerances of ± 10% allow Zo tolerance limits of + 22% and -19%; RT tolerances of ± 5%
allow Zo tolerance limits of +26% and -23%.
An additional requirement on the maximum value of RT is
related to the value of quiescent 10H current needed to insure sufficient negative-going signal swing when the ECl
driver switches from the HIGH state to the lOW state. The
npn emitter-follower output of the ECl circuit cannot act as
a voltage source driver for negative-going transitions. When
the voltage at the base of the emitter follower starts going
negative as a result of an internal state change, the output
current of the emitter follower starts to decrease. The transmission line responds to the decrease in current by producing a negative-going change in voltage. The ratio of the voltage change to the current change is, of course, the characteristic impedance Z00 Since the maximum decrease in current that the line can experience is from 10H to zero, the
maximum negative-going transition which can be produced
is the product 10H Zoo
If the 10H Zo product is greater than the normal negative-going signal swing, the emitter follower responds by limiting
the current change, thereby controlling the signal swing. If,
however, the 10H Zo product is too small, the emitter follower is momentarily turned off due to insufficient forward bias
of its base-emitter junctions, causing a discontinuous negative-going edge such as the one shown in Figure 14. In the
output-lOW state the emitter follower is essentially nonconducting for VOL values more positive than about
-1.55V. Using this value as a criterion and expressing 10H
and VOH in terms of the equivalent circuit of Figure 6e, an
upper limit on the value of RT can be developed.

The linearized portion of the FlOOK output characteristic
can be represented by two equations:
For VOH: VOUT = -650 -6 OUT
For VOL: VOUT = -1670 -6 lOUT
where lOUT is in mA, VOUT is in mY.
If the range of lOUT is confined between 6 mA to 40 mA for
VOH, and 2 mA to 16 mA for VOL, the output voltage can be
estimated within ± 10 mV (Figure 6d).
An ECl output can drive two or more lines in parallel, provided the maximum rated current is not exceeded. Another
consideration is the effect of various loads on noise margins. For example, two parallel 75D. terminations to -2V
(Figure 6d) give output levels of approximately -1.000V
and -1.716V. Noise margins are thus 35 mV less in the
HIGH state and 11 mV more in the lOW state, compared to
50D.load conditions. Conversely, a single 75D.load to -2V
causes noise margins 36 mV greater in the HIGH state and
11 mV less in the low state, compared to a 50D. load.
The magnitude of reflections from the terminated end of the
line depends on how well the termination resistance RT
matches the line impedance Z00 The ratio of the reflected
voltage to the incident voltage Vi is the reflection coefficient

AV

p.

RT

(eq.5)
Vi
RT+ZO
The initial signal swing at the termination is the sum of the
incident and reflected voltages. The ratio of termination signal to incident signal is thus:

RT < 1.64 Zo + 3.86D.
For Zo = 50D., the emitter follower cuts off during a negative-going transition if RT exceeds 66D.. Changing the voltage level criteria to -1.60V to insure continuous conduction
in the emitter follower gives an upper limit of 77D. for a 50D.
line. For a line terminated at the receiving end with a resistance to -2V, a rough rule-of-thumb is that termination resistance should not exceed line impedance by more than
50%. This insures a satisfactory negative-going signal swing
to ECl inputs connected along the line. The quiescent VOL
level, after all reflections have damped out, is determined by
RT and the ECl output characteristic.

VT

2RT
1 + P = --(eq.6)
Vi
RT + Zo
The degree of reflections which can be tolerated varies in
different situations, but to allow for worst-case circuits, a
good rule of thumb is to limit reflections to 15% to prevent
excursions into the threshold region of the ECl inputs connected along the line. The range of permissible values of RT
as a function of Zo and the reflection coefficient limitations
can be determined by rearranging Equation 5.

- =

=

1+ P
1- P

Zo - -

< (EOH

- Vn) Zo - (1.55 - IVnl) Ro
(eq.9)
1.55 -IEoHI
For a Vn of -2V, Ro of 6D. and EOH of -0.65V, Equation
4-9 reduces to

-=p=--

RT

10HZO > 1.55 - IVOHI

( EOH - Vn) Zo > 1.55 _IVnRo = EOHRTI
Ro + RT
Ro + RT

RT - Zo

V,

=

(eq. 7)

INPUT IMPEDANCE
The input impedance of ECl circuits is predominately capacitive. A single-function input has an effective value of
about 1.5 pF for FlOOK flatpak, as determined by its effect
on reflected and transmitted signals on transmission lines.

4-133

III

signal. The initial signal at the driver end is half amplitude,
rising to full amplitude only after the reflection returns from
the open end of the line. In Figure 7, one load is shown
connected at point D, aways from the line end. This input
receives a full amplitude signal with a continuous edge if the
distance I to the open end of the line is within recommended
lengths for unterminated line (Figure 10).

In practical calculations, a value of 2 pF should be used.
Approximately one third of this capaCitance is attributed to
the internal circuitry and two thirds to the flatpak pin and
internal bonding.
For F100K flatpak circuits, multiple input lines may appear
to have up to 3 pF to 4 pF but never more. For example, in
the F1 001 02, an input is connected internally to all five
gates, but because of the philosophy of buffering these
types of inputs in the FlOOK family this input appears as a
unit load with a capacitance of approximately 2 pF. For applications such as a data bus, with two or more outputs
connected to the same line, the capacitance of a passivelOW output can be taken as 2 pF.
Capacitive loads connected along a transmission line increase the propagation delay of a signal along the line. The
modified delay can be determined by treating the load capacitance as an increase in the intrinsic distributed capacitance of the line, discussed in Chapter 3. The intrinsic capacitance of any stubs which connect the inputs to the line
should be included in the load capaCitance. The intrinsic
capaCitance per unit length for G-10 epoxy boards is shown
in Figure 3 and 5 for microstrip and stripline respectively.
For other dielectric materials, the intrinsic capacitance Co
can be determined by dividing the intrinsic delay a (Equation
3) by the line impedance Zoo
The length of a stub branching off the line to connect an
input should be limited to insure that the signal continuing
along the line past the stub has a continuous rise, as opposed to a rise (or fall) with several partial steps. The point
where a stub branches off the line is a low impedance point.
This creates a negative coefficient of reflection, which in
turn reduces the amplitude of the incident wave as it continues beyond the branch pOint. If the stub length is short
enough, however, the first reflection returning from the end
of the stub adds to the attenuated incident wave while it is
still rising. The sum of the attenuated incident wave and the
first stub reflection provides a step-free signal, although its
rise time will be longer than that of the original signal. Satisfactory signal transitions can be assured by restricting stub
lengths according to the recommendations for unterminated
lines (Figure 10). The same considerations apply when the
termination resistance is not connected at the end of the
line; a section of line continuing beyond the termination resistance should be treated as an unterminated line and its
length restricted accordingly.

RS

Zo

RE
VEE
TL/F/l0790-61

FIGURE 7. Series Termination

The signal at the end has a slower rise time that the incident
wave because of capacitive loading. The increase in rise
time to the 50% point effectively increases the line propagation delay, since the 50% point of the signal swing is the
input signal timing reference pOint. This added delay as a
function of the product line impedance and load capacitance is discussed in Chapter 3.
Quiescent VOH and VOL levels are established by resistor
RE (Figure 7), which also acts with VEE to provide the negative-going drive into Rs and Zo when the driver output goes
to the lOW state. To determine the appropriate RE value,
the driver output can be treated as a simple mechanical
switch which opens to initiate the negative-going swing. At
this instant, Zo acts as a linear resistor returned to VOH.
Thus the components form a simple circuit of RE, Rs and Zo
in a series, connected between VEE and VOH. The initial
current in this series circuit must be sufficient to introduce a
0.38V transient into the line, which then doubles at the load
end to give 0.75V swing.
VOH - VEE
0.38
(eq.10)
~-RE + Ps + Zo
Zo
Any IOH current flowing in the line before the switch opens
helps to generate the negative swing. This current may be
quite small, however, and should be ignored when calculating RE.
Increasing the minimum signal swing into the line by 30% to
0.49V insures sufficient pull-down current to handle reflection currents caused by impedance discontinuities and load
capaCitance. The appropriate RE value is determined from
the following relationship.
IRE =

SERIES TERMINATION

Series termination requires a resistor between the driver
and transmission line, Figure 7. The receiving end of the line
has no termination resistance. The series resistor value
should be selected so that when added to the driver source
resistance, the total resistance equals the line impedance.
The voltage divider action between the net series resistance
and the line impedance causes an incident wave of half
amplitude to start down the line. When the signal arrives at
the unterminated end of the line, it doubles and is thus restored to a full amplitude. Any reflections returning to the
source are absorbed without further reflection since the line
and source impedance match. This feature, source absorption, makes series termination attractive for interconnection
paths involving impedance discontinuities, such as occur in

VOH - VEE ,0.49
'"
(eq.11)
RE + Rs + Zo
Zo
For the RE range normally used, quiescent VOH averages
approximately 0.955V and VEE = -4.5V. The value of Rs
is equal to Zo minus Ro (Ro averages 70). Inserting these
values and rearranging Equation 11 gives the following.
RE s: 5.23 Zo + 70
(eq. 12)
Power dissipation in RE is listed in Figure 14. The power
dissipation in RE is greater than in Rr of a parallel termination to - 2V, but still less than the two resistors of the
Thevenin equivalent parallel termination, see Figure 10, 13
and 14.

bac~Plane wiring.

.
...
..
The number of driven inputs on a series terminated line is
A disadvantage of series ter.mlnallOn I.S that .d~lven Inputs -limited by the voltage drop across Rs in the quiescent HIGH
must be near the end of the line to aVOid receiving a 2-step
state, caused by the finite input currents of the ECl loads.
IIH values are specified on data sheets for various types of

4-134

.

r-------------------------------------------------------------------,~

Z
en

inputs, with a worst-case value of 265 /LA for simple gate
inputs. The voltage drop subtracts from the HIGH-state
noise margin as outlined in Figure 8a.
However, there is more HIGH-state noise margin initially,
because there is less IOH with the RE load than with the
standard 50nload to -2V. This makes VOH more positive;
the increase ranges from 43 mV for a 50n line to B2 mV for
a 100n line. Using this VOH increase as a limit on the voltage drop across Rs assures that the HIGH-state noise margin is as good as in the parallel terminated case. Dividing
the VOH increase by Rs + Ro (= Zo) gives the allowed load
input current (Ix in Figure 8a). This works out to 0.B6 mA for
a 50n line, 0.92 mA for a 75n line and 0.B2 mA for a 100n
line. load input current greater than these values can be
tolerated at some sacrifice in noise margin. If, for example,
an additional 50 mV loss is feasible, the maximum values of
current become 1.B6 mA, 1.59 mA and 1.32 mA for 50n,
75n and 100n lines respectively.
An ECl output can drive more than one series terminated
line, as suggested in Figure 8b, if the maximum rated output
current of 50 mA is not exceeded. Also, driving two or more
lines requires a lower RE value. This makes the quiescent
IOH higher and consequently VOH lower, due to the voltage
drop across Ro. This voltage drop decreases the HIGHstate noise margin, which may become the limiting factor
(rather than the maximum rated current), depending on the
particular application.
The appropriate RE value can be determined using Equation
13 for VEE = - 4.5V.

.2... ~
RE

1
6.23 Zl - RS1

+

6.23 Z2 - RS2

......

""'

TL/F/l0790-62

a. Noise Margin loss Due to Load Input Current

TL/F/l0790-63

b. Driving Several lines from one Output

--~--+--4----VEE

TUF/l0790-64

c. Using Multiple Output Element for load Sharing
FIGURE 8. loading Considerations
for Series Termination
able. Undershoot (following the overshoot) must also be limited to prevent signal excursions into the threshold region of
the loads. Such excursions could cause exaggerated transition times at the driven circuit outputs, and could also
cause multiple triggering of sequential circuits. Signal swing,
exclusive of ringing, is slightly greater on unterminated lines
that on parallel terminated lines; IOH is less and IOL is greater with the RE load, (Figure 9a) making VOH higher and VOL
lower.
For worst case combinations of driver output and load input
characteristics, a 35% overshoot limit insures that system
speed is not compromised either by saturating an input on
overshoot or extending into the threshold region on the following undershoot.
For distributed loading, ringing is satisfactorily controlled if
the 2-way modified line delay does not exceed the 20% to
BO% rise time of the driver output. This relationship can be
expressed as follows, using the symbols from Chapter 3 and
incorporating the effects of load capacitance on line delay.

+ ..,....".,:-::-'---::--

6.23 Zs - Tss
(eq.13)

Circuits with multiple outputs (such as the F1 00112) provide
an alternate means of driving several lines simultaneous
(Figure 8e). Note, each output should be treated individually
when assiging load distribution, line impedance, and RE value.
UNTERMINATED LINES
Lines can be used without series or parallel termination if
the line delay is short compared to the signal rise time. Ringing occurs because the reflection coefficient at the open
(receiving) end of the line is positive (nominally + 1) while
the reflection coefficient at the driving end is negative (approximately - O.B). These opposite polarity reflection coefficients cause any change in signal voltage to be reflected
back and forth, with a polarity change each time the signal is
reflected from the driver. Net voltage change on the line is
thus a succession of increments with alternating polarity
and decreasing magnitude. The algebraic sum of these increments if the observed ringing. The general relationships
among rise time, line delay, overshoot and undershoot are
discussed in Chapter 3, using simple waveforms for clarity.
Excessive overshoot on the positive-going edge of the signal drives input transistors into saturation. Although this
does not damage an ECl input, it does cause excessive
recovery times and makes propagation delays unpredict-

tr = 2T' = 2t 8' = 2t 8

~1 +

CL

tCo

Solving this expression for the line length (t ):

_ 1 ~(CL)2
(tr)2
t max-+2

4-135

Co

8

_..9:.
2Co

(eq.14)

~ r-------------------------------------------------------------------------------~

.....

~

z011(

(II and Co), maximum lengths are calculated using Equation
14. For the convenience of those who are also using 10K
ECl, maximum recommended lengths of unterminated lines
are listed in Figure 10b to 10e.

-w- -r>. .;:-e
. . ~Zo-----'+:~,
Vee

Number of Fan-Out Loads

Zo
TLlF110790-65

a. Untermlnated Line

1

2

3

4

50
62

1.37·
1.33

1.13
1.07

0.95
0.S7

O.Sl
0.70

75
90
100

1.25
1.18
1.15

0.95
0.85
0.S2

0.75
0.66
0.61

0.61
0.53
0.49

·Length in inches.
Unit load = 2 pF, 8 = 0.148 nslinch

FIGURE 10a. F100K Maximum Worst-Case
Line Lengths for Untermlnated
Microstrip, Distributed Loading

Zo

H = 10 ns/diy
V =0.3 V/diy

TLIF110790-66

b. Line Voltages Showing Stair-step Trailing Edges

Number of Fan-Out Loads

2

3

4

6

8

50
62

4.15·
3.95

3.75
3.50

3.45
3.15

2.S5
2.55

2.45
2.10

75
90
100

3.75
3.55
3.45

3.25
3.00
2.85

2.85
2.60
2.45

2.25
2.00
1.85

1.S5
1.60
1.45

'Length In Inches.
Unit load = 3 pF, 8

= 0.148 ns/ln.

FIGURE 10b. 10K Maximum Worst-Case
Line Lengths for Unterminated
Mlcrostrip, Distributed Loading
Number of Fan-Out Loads

Zo

c

1

2

4

6

8

50
62

4.40·
4.30

3.65
3.45

2.60
2.30

1.90
1.60

1.40
1.15

75
90
100

4.20
4.05
3.90

3.20
2.95
2.80

2.05
1.75
1.60

1.40
1.05
0.90

0.95
0.65
0.50

'Length In Inches.
Unn load = 3 pF, 8

= 0.148 ns/ln.
FIGURE 10c. 10K Maximum Worst-Case
Line Lengths for Unterminated
Microstrip, Concentrated Loading

H = 1 ns/div
V =0.3 V/diy

TLIF110790-67

c. Load Gate Output Showing Net
Propagation Increase for Increasing
Values of RE: 3300, 5100,1 kO

Zo

FIGURE 9. Effect on RE Value
on Trailing-Edge Propagation
The shorter the rise time, the shorter the premissible line
length. For F100K ECl, the minimum rise time from 20% to
SO% is specified as 0.5 ns. Using this rise time and 2 pF per
fan-out load, calculated maximum line lengths for G-l0
epoxy microstrip are listed in Figure 10a. The length (I) in
the table is the distance from the terminating resistor to the
input of the device(s). For FlOOK ECl the case described in
Figure 10a is the only one calculated, since all other combinations are approximately the same. For other combinations
of rise time, impedance, fan-out or line characteristics

Number of Fan-Out Loads

2

3

4

6

8

50
62

3.30·
3.15

3.00
2.S0

2.70
2.50

2.25
2.00

2.90
1.65

75
90

3.00
2.S0

2.60
2.40

2.25
2.05

1.80
1.55

1.45
1.25

·Length in inches.
Unit load = 3 pF, 8

= 0.188 ns/in.
FIGURE 10d. 10K Maximum Worst-Case
Line Lengths for Untermlnated
Strlpllne, Distributed Loading

4-136

lines to the driver output. Waveforms at the termination resistor (point A) are shown in the multiple exposure photograph of Figure 11b. The upper trace shows a normal signal
without stubs connect.3d to the driver. The middle trace
shows the effect of connecting one stub to the driver. The
step in the negative-going edge indicates that the quiescent
IOH current through RT is not sufficient to cause a full signal
for both lines. The relationship between the quiescent IOH
current through RT and the negative-going signal swing was
discussed earlier in connection with parallel termination .
The bottom trace in Figure 11 shows the effect of connecting two stubs to the driver output. The steps in trailing edge
are smaller and more pronounced. The deteriorated trailing
edge of either the middle or lower waveform increas-

Number of Fan-Out Loads

Zo

1

2

4

6

8

50
62

3.45·
3.40

2.85
2.70

2.00
1.80

1.50
1.30

1.10
0.90

75
90
100

3.30
3.15
3.10

2.55
2.35
2.20

1.60
1.40
1.25

1.10
0.85
0.70

0.75
0.50
0.40

• Length in inches.
Unit load

~

3 pF, 8

~

0.188 ns/in.

FIGURE 10e. 10K Maximum WorstCase Line Lengths for Unterminated
Stripllne, Concentrated Loading
A load capacitance concentrated at the end of the line restricts line length more than a distributed load does. Maximum recommended lengths for fiberglass epoxy dielectric
and a 0.5 ns rise time are listed in Figure 10 for microstrip.
For line impedances not listed, linear interpolation can be
used to determine appropriate line lengths. Appropriate line
lengths for dielectric materials with a different propagation
constant /) can be determined by multiplying the listed values by the fiberglass epoxy /) and then dividing by the /) of
the other material. For example, a line length for a material
which has a microstrip /) of 0.1 ns/inch is determined by
multiplying the length given in the microstrip table (for a
desired impedance and load) by 0.148 and dividing by 0.1.
Resistor RE must provide the current for the negative-going
signal at the driver output. Line input and output waveforms
are noticeably affected if RE is too large, as shown in Figure
9b. The negative-going edge of the signal falls in stair-step
fashion. with three distinct steps visible at point A. The
waveform at point B shows a step in the middle of the negative-going swing. The effect of different RE values on the
net propagation time through the line and the driven loads is
evident in Figure ge which shows the output signal of one
driven gate in a multiple exposure photograph. The horizontal sweep (time axis) was held constant with respect to the
input signal of the driver. The earliest of the three output
signals occurs with an RE value of 330n. Changing RE to
510n increases the net propagation delay by 0.3 ns, the
horizontal offset between the first and second signals.
Changing RE to 1 kn produces a much greater increase in
net propagation delay, indicating that the negative-going
signal at B contains several steps. In practice, a satisfactory
negative-going signal results when the RE value is chosen
to give an initial negative-going step of 0.6V at the driving
end of the line. This gives an upper limit on the value of RE,
as shown in Equation 15.
initial step =

t:. t • Zo

= (VOH - VEE)

RE +Zo

a. Multiple Lines

vn
TUF/l0790-68

b. Waveforms at Termination Point A

H= 5 ns/dlv
V=O.S V/dlv
Tl/F/l0790-69

c. Equivalent Circuit for Determining Initial·

Zo ~ 0.6

Negative Voltage Step at the Driver Output

-'AT

RE = s: 6.25 Zo
(eq.15)
An ECl output can drive two or more unterminated lines,
provided each line length and loading combination is within
the recommended constraints. The appropriate RE value is
determined from Equation 15. using the parallel impedance
of the two or more lines for Zo0

z,

-

Q

-r-x
R

Z3

An ECl output can simultaneously drive terminated and unterminated lines, although the negative-going edge of the
signal shows two or more distinct steps when the stubs are
long unless some extra pull-down current is provided. Figure
11a shows an ECl circuit driving a parallel terminated line,
with provision for connecting two worst-case unterminated

VEE

TL/F/l0790-70

FIGURE 11. Driving Terminated
and Unterminated Lines in Parallel

4-137

es the switching time of the cirucit connected to point A. If
this extra delay cannot be tolerated, additional pull-down
current must be provided. One method uses a resistor to
VEE as suggested in Figure 11a. The initial negative-going
step at point A should be about 0.7V to insure a good fall
rate through the threshold region of the driven gate. The
initial step at the driver output should also be 0.7V. If the
driver output is treated as a switch that opens to initiate the
negative-going signal, the equivalent circuit of Figure 11c
can be used to determine the initial voltage step at the driver output (point X). The value of the current source IRT is the
quiescent IOH current through RT. Using Z' to denote the
parallel impedance of the transmission lines and I::. V for the
desired voltage step at X, the appropriate value of RE can
be determined from the following equation, using absolute
values to avoid polarity confusion.
RE = (IVEEI -lvoHI- I::. VI) • (II::. vi

vn
TLlF/10790-71

FIGURE 12. Data Bus or Party Line
using multiple output gates (F100112) and paralleling two
outputs for each driver. In the quiescent LOW state, termination current is shared among all the output transistors on
the line. This sharing makes VOL more positive than if only
one output were conducting all of the current. For example,
a 1000 line terminated at both ends represents a net 500
DC load, which is the same as the data sheet condition for
VOL. If one worst-case output were conducting all the current, the VOL would be -1.705V. If another output with
identical DC characteristics shares the load current equally,
the VOL level shifts upward by about 25 mV. Connecting two
additional outputs for a total of four with the same characteristics shifts VOL upward another 22 mY. Connecting four
more identical outputs shifts VOL upward another 20 mY.
Thus the VOL shift for eight outputs having identical worstcase VOL characteristics is approximately 67 mV. In practice, the probability of having eight circuits with worst-case
VOL characteristics is quite low. The output with the highest
VOL tends to conduct most of the current. This limits the
upward shift to much less than the theoretical worst-case
value. In addition, the LOW-state noise margin is specified
greater than the HIGH-state margin to allow for VOL shift
when outputs are paralleled.
In some instances a single termination is satisfactory for a
data bus, provided certain conditions are fulfilled. The single
termination is connected in the middle of the line. This requires that for each half of the line, from the termination to
the end, the line length and loading must comply with the
same restrictions as unterminated lines to limit overshoot
and undershoot to acceptable levels. The termination
should be connected as near as possible to the electrical
mid-point of the line, in terms of the modified line delay from
the termination to either end. Another restriction is that the
time between successive transitions, i.e., the nominal bit
time, should not be less than 15 ns. This allows time for the
major reflections to damp out and limits additive reflections
to a minor level.

~'IIRTIZ')

For a sample calculation, assume that RT and the line impedances are each 1000, VOH is -0.955V, I::. V is 0.750V,
VEE is -4.5V and Vn is - 2V. IRT is thus 10.45 mA and the
calculated value of RE is 2320. In practice, this value is on
the conservative side and can be increased to the next larger (10%) standard value with no appreciable sacrifice in
propagation through the gate at pOint A.
Again, the foregoing example is based on worst-case stub
lengths (the longest permissible). With shorter stubs, the
effects are less pronounced and a point is reached where
extra pull-down current is not required because the reflection from the end of the stub arrives back at the driver while
the original signal is still falling. Since the reflection is also
negative going, it combines with and reinforces the falling
Signal at the driver, eliminating the steps. The net result is a
smoothly falling signal but with increased fall time compared
to the stubless condition.
The many combinations of line impedance and load make it
practically impossible to define just with stub length begins
to cause noticeable steps in the falling Signal. A rough ruleof-thumb would be to limit the stub length to one-third of the
values given in Figure 10.
DATA BUSSING
Data bussing involves connecting two or more outputs and
one or more inputs to the same signal line, (Figure 12). Any
one of the several drivers can be enabled and can apply
data to the line. Load inputs connected to the line thus receive data from the selected source. This method of steering data from place to place simplifies wiring and tends to
minimize package count. Only one of the drivers can be
enabled at a given time; all other driver outputs must be in
the LOW state. Termination resistors matching the line impedance are connected to both ends of the line to prevent
reflections. For calculating the modified delay of the line
(Chapter 3) the capacitance of a LOW (unselected) driver
output should be taken as 2 pF.
An output driving the line sees an impedance equal to half
the line impedance. Similarly, the quiescent IOH current is
higher than with a single termination. For line impedance
less than 1000, the IOH current is greater than the data
sheet test value, with a consequent reduction of HIGH-state
noise margin. This loss can be eliminated if necessary by

WIRED-OR
In general-purpose wired-OR logic connections, where two
or more driver outputs are expected to be in the HIGH state
simultaneously, it is important to minimize the line length
between the participating driver outputs, and to place the
termination as close as possible to the mid-point between
the two most widely separated sources. This minimizes the
negative-going disturbances which occur when one HIGH
output turns off while other outputs remain HIGH. The driver
output going off represents a sudden decrease in line current, which in turn generates a negative-going voltage on
the line. A finite time is required for the other driver outputs
(quiescently HIGH) to supply the extra current. The net re-

4-138

suit is a "V" shaped negative glitch whose amplitude and
duration depend on three factors: current that the off-going
output was conducting, the line impedance, and the line
length between outputs. If the separation between outputs
is kept within about one inch, the transient will not propagate through the driven load circuits.
If a wired-OR connection cannot be short, it may be necessary to design the logic so that the signal on the line is not
sampled for some time after the normal propagation delay
(output going negative) of the element being switched. Normal propagation delay is defined as the case where the element being switched is the only one on the line in the HIGH
state, resulting in the line going LOW when the element
switches. In this case, the propagation delay is measured
from the 50% point on the input signal of the off-going element to the 50% point of the signal at the input farthest
away from the output being switched. The extra wiring time
required in the case of a severe negative glitch is, in a
worst-case physical arrangement, twice the line delay between the off-going output and the nearest quiescently
HIGH output, plus 2 ns.

transient reaches point B. Consequently, the transient duration observed at C is shorter by twice the line delay from A
to B.

I'DRr

VTT
TLlF110790-72

FIGURE 13_ Relative to Wired-OR Propagation
BACKPLANE INTERCONNECTIONS
Several types of interconnections can be used to transmit a
signal between logic boards. The factors to be considered
when selecting a particular interconnection for a given application are cost, impedance discontinuities, predictability of
propagation delay, noise environment, and bandwidth. Single-ended transmission over an ordinary wire is the most
economical but has the least predictable impedance and
propagation delay. At the oPPosite end of the scale, coaxial
cable is the most costly but has the best electrical characteristics. Twisted pair and similar parallel wire interconnection cost and quality fall in between.
For single-wire transmission through the backplane, a
ground plane or ground screen (Chapter 5) should be provided to establish a controlled impedance. A wire over a
ground plane or screen has a typical impedance of 1500.
with variations on the order of ±33%, depending primarily
on the distance from ground and the configuration of the
ground. Figure 14 illustrates the effects of impedance variations with a 15-inch wire parallel terminated with 1500. to
-2V. Figure 14b shows source and receiver waveforms
when the wire is in contact with a continuous ground plane.

An idea of how the extra waiting time varies with physical
arrangement can be obtained by qualitatively comparing the
signal paths in Figure 13. With the outputs at A and B quiescently HIGH, the duration of the transient observed at C is
longer if B is the off-going output than if A is the off-going
element. This is because the negative-going voltage generated at B must travel to A, whereupon the corrective signal
is generated, which subsequently propagates back toward
C. Thus the corrective signal lags behind the initial transient,
as observed at C, by twice the line delay between A and B.
On the other hand, if the output at A generates the negativegoing transient, the corrective response starts when the
A

1=15"

WIRE OVER GND PLANE OR SCREEN
1500

-2.0V
TL/F/l0790-73

a. Wire over Ground Plane or Screen

_A

_B

H::;5 nsJdiv
V=O.4 Vldiv

H =5 nsldiv
V=O.4 nsldiv

TLIF/10790-7S

TL/F110790-74

c. Wire Spaced 'Ia" from Ground Screen

b. Wire in Contact with Ground Plane

FIGURE 14. Parallel Terminated Backplane Wire

4-139

»
z
I

CD

:;;:!

Signal propagation along a single wire tends to be fast because the dielectric medium is mostly air. However, impedance variations along a wire cause intermediate reflections
which tend to increase rise and fall times, effectively increasing propagation delay. Effective propagation delays
are in the range of 1.5 to 2.0 ns per foot of wire. Load
capacitance at the receiving end also increases rise and fall
time (Appendix A), further increasing the effective propagation delay.

The negative-going signal at the source shows an initial step
of only 80% of a full signal swing. This occurs because the
quiescent HIGH-state current IOH (about 7 mAl multiplied by
the impedance of the wire (approximately 900) is less than
the normal signal swing, and this condition allows the driver
emitter follower to turn off. The negative-going signal at the
receiving end is greater by 25% (1 + P = 1.25). The receiving end mismatch causes a negative-going reflection which
returns to the source and establishes the VOL level. The
positive-going signal at the source shows a normal Signal
swing, with the receiving end exhibiting approximately 25%
overshoot.
Figure 14c shows waveforms for a similar arrangement, but
with the wire about Ys inch from a ground screen. The impedance of the wire is greater than 1500 termination, but
small variations in impedance along the wire cause intermediate reflections which tend to lengthen the rise and fall
times of the signal. As a result, the received signal does not
exhibit pronounced changes in slope as would be expected
if a 2000 constant impedance line were terminated with
1500.
Series source resistance can also be used with single wire
interconnections to absorb reflection. Figure 15a shows a
16-inch wire with a ground screen driven through a source
resistance of 1000. The waveforms (Figure 15b) show that
although reflections are generated, they are largely absorbed by the series resistor, and the signal received at the
load exhibits only slight changes and overshoot. Series termination techniques can also be used when the Signal into
the wire comes from the PC board transmission line. Figure
16a illustrates a 12-inch wire over a ground screen, with 12inch microstrip lines at either end of the wire. The output is
heavily loaded (fan-out of 8) and the combination of impedances produces a variety of reflections at the input to the
first microstrip line, shown in the upper trace of Figure 16b.
The lower trace shows the final output; a comparison between the two traces shows the effectiveness of damping in
maintaining an acceptable signal at the output. Figure 16c
shows the signals at the input to the driving gate and at the
output of the load gate, with a net through-put time of 8.5
ns. The circuit in Figure 16a is a case of mismatched transmission lines, discussed in Appendix A.

16" WIRE OVER GROUND SCREEN B

TLlF/10790-76

a. Wire over Ground Screen

H = 10 ns/dl.
V =0.3 V/dl.
TLlF/10790-77

b. Series Terminated Waveform
FIGURE 15. Series Terminated Backplane Wire

4·140

~------------------------------------------------------------------,>

[

P

12' MICROSTRIPSl

OUTPUT

12' WIRE OVER
GROUND SCREEN

r£>-

_ _ .-1- _ _

INPUT
10011

a
-D;::::-~-=,~t!--- -----,-l--.-tR~

~

1

'h = 10011 Zo = 150 lila = 100 liB I
~

Vn
TLiF/l0790-81

a. Single-ended Twisted Pair

VEE

P

TL/F/l0790-78

a. Backplane Wire Interconnecting PC Board Lines

TL/F/l0790-82

-A

b. Differential Transmission Reception

H= 10 ns/di.
V=0.4 V/dl.
TL/F/l0790-79
TLiF/l0790-83

b. Signals into the First Microstrip and at the Loads

c. Backplane Data Bus
FIGURE 4-17. Twisted Pair Connections
gle-ended driving and receiving. In addition to improved
propagation velocity, the magnetic fields of the two conductors tend to cancel, minimizing noise coupled into adjacent
wiring.
Differential line driving and receiving complementary gates
as the driver and an F100114 line receiver is illustrated in
Figure 4-17b. Differential operation provides high noise immunity, since common mode input voltages between
-0.55Vand -3.0V are rejected. The differential mode is
recommended for communication between different parts of
a system, because it effectively nullifies ground voltage differences. For long runs between cabinets or near high power transients, interconnections using shielded twisted pair
are recommended.
Twisted pair lines can be used to implement party line type
data transfer in the backplane, as indicated in Figure 4-17c.
Only one driver should be enabled at a given time; the other
outputs must be in the VOL state. The VBB reference voltage is available on pin 22 of the fiatpak and pin 19 of the
dual-in-line package for the F100114.
In the differential mode, a twisted pair can send high-frequency symmetrical signals, such as clock pulses, of
100 MHz over distances of 50 to 100 feet. For random data,
however, bit rate capability is reduced by a factor of four or
five due to line rise effects on time jitter.3

H= 10 nsldi.
V=O.4 Vldiv
TL/F/l0790-80

c. Input to Driving Gate and Output of Load Gate
FIGURE 4-16. Signal Path with Sequence
of Microstrip, Wire, Mlcrostrlp
Better control of line impedance and faster propagation can
be achieved with a twisted pair. A twisted pair of AWG 26
Teflon' insulated wires, two twists per inch, exhibits a propagation delay of 1.33 nslft and an impedance of 1150.
Twisted pair lines are available in a variety of sizes, impedances and multiple-pair cables. Figure 4-178 illustrates sin'Teflon is a registered trademark of E.I. du Pont de Nemours Conpany.

4-141

ZI

en
~

Coaxial cable offers the highest frequency capability. In addition. the outer conductor acts as a shield against noise.
while the uniformity of characteristics simplifies the task of
matching time delays between different parts of the system.
In the single-ended mode. Figure 4-188.50 MHz signals can
be transferred over distances of 100 feet. For 100 MHz operation. lengths should be 50 feet or less. In the differential
mode. Figures 4-18b.c, the line receiver can recover smaller signals, allowing 100 MHz signals to be transferred up to
100 feet. The dual cable arrangement of Figure 4-18c provides maximum noise immunity. The delay of coaxial cables
depends on the type of dielectric material. with typical delays of 1.52 nslft for polyethylene and 1.36 nslft for cellular
polyethylene.
.

REFERENCES
1. Kaupp. H. R., "Characteristics of Microstrip Transmission
Lines." IEEE Transaction on Electronic Computers. Vol.
EC-16 (April. 1967).
2. Harper. C. A.. Handbook of Wiring, Cabling and Interconnections for Electronics. New York: McGraw-Hili, 1972.
3. True. K. M.• "Transmission Line Interface Elements." The
TTL Applications Handbook, Chapter 14 (August 1973).
pp.14-1-14-14.

-D-irH;---:;'Zo------+l+J
....
-, -rRT=Zo
D-

f

VTT

-If
'

TLlF/l0790-84

a. Single-Ended Coaxial Transmission

~~"2
2

VTT
TL/F/l0790-85

b. Differential Coaxial Transmission
VTT

,-

4

,-

~

,-

RT

fj>

i JR~
VTT

TL/FI10790-86

c. Differential Transmission with Grounded Shields
FIGURE 4-18. Coaxial Cable Connections

4-142

APPENDIXC
ECl DESIGN GUIDE:
POWER DISTRIBUTION AND THERMAL CONSIDERATIONS
INTRODUCTION

In practice, two communicating circuits might be located on
widely separated PC cards with other PC cards in between.
The net resistance then includes the incremental resistance
of the ground distribution bus from card to card, while the
ground current is successively increased by the contribution
from each card. Figure 2 illustrates a distribution bus for a
row of cards with incremental resistances along the bus.

High-speed circuits generally consume more power than
similar low-speed circuits. At the system level, this means
that the power supply distribution system must handle the
larger current flow; the larger power dissipation places a
greater demand on the cooling system. The direct current
(DC) voltage drop along ground busses affects noise margins for all types of ECl circuits. Voltage drops along VEE
busses have only a slight effect on F100K circuits, but they
require consideration to obtain the performance available
from the family.

~~~.-~---~
3 _ _ _ j· _ _ _ _ _ k _ _ _ _ _ n

CARD
POSITION

LOGIC CIRCUIT GROUND, Vee

TL/F/l0790-BB

The positive potential Vee and VeeA in ECl circuits is the
reference voltage for output voltages and input thresholds
and should therefore be the ground potential. When two
circuits are connected in a single-ended mode, any difference in ground potentials decreases the noise margins, as
discussed in Chapter 1. This effect for TTLlDTl circuits, as
well as for ECl circuits, is illustrated in Figure 1. The following analysis assumes some average value of current flowing
through the distributed resistance along the ground path between two circuits. For the indicated direction of IG, the shift
in ground potential decreases the lOW-state noise margin
of the TTLlDTl circuits and the HIGH-state noise margin of
the ECl circuits. If IG is flowing in the opposite direction, it
increases these noise margins, but decreases the noise
margins when the drivers are in the opposite state. For tabulation of ground currents in ECl, the designs must include
termination currents as well as lEE operating currents. ECl
logic boards which use microstrip or stripline techniques
generally have large areas of ground metal. This causes the
ground resistance to be quite low and thus minimizes noise
margin loss between pairs of circuits on the same board.

r = Incremental Bus Resistance between Positions
i = Average Ground Current per Card

FIGURE 2. Ground Shift Along a Row of PC Cards
The ground shift can be estimated by first determining an
average value of current per card based on the number of
packages, the mix of 881 and M81, and the number and
types of terminations. With n cards in the row, an average
ground current (i) per card, and an incremental bus resistance (r) between card positions, the bus voltage drops between the various positions can be determined as follows:
between pOSitions 1 and 2: vl-2 = (n - 1) ir
between positions 1 and 3: vl-3 = (n - 1) ir
(n - 2) ir

+

between pOSitions 1 and 4: vl-4 = (n - 1) ir
(n - 2)ir
(n - 3)ir

+
+

between 1 and n:

I

rr:

vl-n = ir [en - 1) +
(n - 2) + (n - 3)
+ ... + [n - (n - 1)1l
= ir [1 + 2 + 3
+ ... + (n - 1)1
n-l
vl-n = ir

TOTAL RESISTANCh Ro

L

n

1

For a row of 15 cards, for example, the total ground shift
between positions 1 and 15 is expressed as in Equation 1.
14
vl-15 = ir
TTl/DTl

L
1

TL/F/l0790-B7

= 105 ir

ECl

V'OL =VOL = +IGRG
V'OH=VOH+IGRG
IGRG=(V'OL -VmJ = Noise Margin Decrease=IGRG=(V'OH-VOH)

FIGURE 1. Effect of Ground Resistance
on Noise Margins

4·143

n = ir (1

+ 2 + 3 + ... + 13 + 14)
(eq.1)

~

"'~"

z

c(

,---------------------------------------------------------------------------------,
The ground shift between any two card positions j and k can
be determined as follows for the general case.

+ [n - 0 + 1)1 ir +
+ 2)1 ir
+ ... + (n - ij + (k-j-1)11 ir
(k - j) nir - ir (j + 0 + 1) + 0 + 2)
+ ... + ij + (k-j-1)]l

Vj-k = (n - j) ir

[n - (j

=

k-I

Vj_k = (k - j) nir - ir

L

(eq. 2)
k-I

n = irl(k - j) n -

j

L

nl

Resistance
mn Per Foot

#2
#6
#10
#12
#18
#22
#26
#30

0.156
0.395
0.999
1.588
6.385
16.14
40.81
103.2

Cross-Sectional
Area
Square Inches·
5.213 x 10- 2
2.062 x 10- 2
8.155 x 10- 3
5.129 x 10- 3
1.276 X 10- 3
5.046 X 10- 4
1.996 x 10- 4
7.894 x 10- 5

FIGURE 3. Resistance and Cross-Sectional Area
of Several Sizes of Annealed Copper Wire

J

In a row of 15 cards, the ground shift between positions four
and nine, for example, is determined as follows.
Vj_k = ir [(9 - 4) 15 - (4 + 5 + 6 + 7 + 8)1
(eq. 3)
= ir (75 - 30) = 45 ir

Copper resistivity = p = 1.724 X 10 -6 ncm

@

20·C

.
I
I
ReSistance of a conductor = p A= p

tw

The ground shift between the same number of positions
further down the row is less because of the decreasing current along the row. Consider the ground shift between card
positions 10 and 15.
vIO-15 = ir [(15 - 10)15 (10 + 11 + 12 + 13 + 14)]
= ir (75 - 60) = 15 ir .

AWG
BaS
Gauge

t = thickness

where: I = length
Sheet resistance Ps =

w = width

£ 0. per.!..

t
w
The length/width ratio (lIw) is dimensionless; therefore, the
resistance of a length of conductor of uniform thickness can
be calculated by first determining the number of "squares,"
then multiplying by the sheet resistance. For example, a
conductor one-eighth inch wide and three inches long has
24 squares; its resistance is 24 times the sheet resistance.
Since many thickness dimensions are given in inches, it is
convenient to express the resistivity in ohm-inch, as follows.
p(nin.) = p(ncm) + 2.54 = 6.788 x 10- 7 nino

(eq.4)

These examples illustrate several principles the designer
should consider regarding the ground distribution bus and
assignment of card positions. The bus resistance should be
kept as low as possible by making the cross-sectional areas
as large as practical. Logic cards which represent the heaviest current drain should be located nearest the end where
ground comes into the row of cards. Cards with single-ended logic wiring between them should be assigned to positions as close together as possible. Conversely, if the
ground shift between two card positions represents an unacceptable loss of noise margin, then the differential transmission and reception method i.e., twisted pair, should be
used for logic wiring between them, thereby eliminating
ground shift as a noise margin factor.

The use of sheet resistance and the "squares" concept is
illustrated by calculating the resistance of the conductor
shown in Figure 4. Assume the conductor is a 1 oz. copper
cladding with a 0.0012 inch minimum thickness on a PC
card.

+

11=2'

13=I.S"..i.

12=1-

Wl=114'I-Rl_:~R2
.
.'~R3---"

t

CONDUCTOR RESISTANCES
Conductors with large cross-sectional areas are required to
maintain low voltage drops along power busses. For convenience, Agure 3 lists the resistance per foot and the crosssectional area for more common sizes of annealed copper
wire. Other characteristics and a complete list of sizes can
be found in standard wire tables. A useful rule-of-thumb regarding resistances and, hence, areas is: as gauge numbers
increase, resistance doubles with every third gauge number;
e.g., the resistance per foot of # 10 wire is 1 mn, for # 13
wire it is 2 mo.. Similarly, the resistance per foot of #0 wire
is 0.078 mn, which is half that of # 2 wire.

I

'

•

,
~ IT

R TOTAL

11

w2=1/2"

TL/F/l0790-B9

FIGURE 4, Conductor of Uniform Thickness
but Non-Uniform Cross Section
Sheet resistance = Ps =

~

= 5.657 X 10- 4 0. per square
The number of squares S for the rectangular sections are as
follows.

For calculations involving conductors having rectangular
cross sections, it is often convenient to work with sheet
resistance, particularly for power distribution on PC cards.
Copper resistivity is usually given in ohm-centimeters, indicating the resistance between opposing faces of a 1 cm
cube. The sheet resistance of a conductor is obtained by
dividing the resistivity by the conductor thickness. These
relationships follow.

S1

=

.!!. = 8
WI

13
S3=-=3
W2

The middle average segment of the conductor has a trapeziodal shape. The average of WI and w2 can be used as the
effective width, within 1% accuracy, if the W2/WI ratio is 1.5
or less. Otherwise, a more exact result is obtained as follows.
S2 = __
12_ln (W2) = 41n 2 = 2.77 squares
w2 -WI
WI
Total R = Rt + R2
= 7.51 mn

4-144

+ R3

= Ps(SI

+ S2 + S3)

(eq.5)

1.0~~m

As another example, assume that a 1 oz. trace must carry a
200 rnA current six inches with a voltage drop less than
10 mY.
Vmax 0.Q1
Rmax = - , - = Q.2 = 0.050
(eq.6)

0.05 = PSw

~

\

~

0.10 \ .

~

T=

0.5 ~~~~~~~~~~~~~~
."
"

,\.1\

~ 0.20'1--~1\1r-P..r-r.:1W-H1"",\,.-l.d-I\-4.-+++++H--~~

I

w

ffl~

1\

..

~ 0°'"

is',-0J\'''

~

20 Ps

ti 0.05 ~-+~~~c~~~.~~~~~,~~~
Il:~
E
0.."

w = 120 Ps = (120) 5.657 X 10- 4 = 67.9 X 10- 3
:. minimum trace width, w = 6B mils
At a higher current level, consider the voltage drop in a
conductor 20 mils thick, 1.25 inches wide and 3 feet long
carrying a 50A current.
6.7BB X 10-7
Ps = 2 X 10 2 = 3.364 X 10- 5 0 per square

8

2 oz.
3 oz.
5 oz.
0.Q1 in.

Sheet
Resistance
o per
Square
2.715
1.B86
1.077
6.7BB

X
X
X
X

Thickness

0.02 in.
0.05 in.
Y1s in.
% in.

1

X
X
X
X

Nominal
Weight

oz/ft2

Weight, %

In.

0.0007
0.0014

0.0178
0.0355

1f2

+10
+10

+0.0002
+0.0004
-0.0002
+0.0007
-0.0003
+0.0006
+0.0006
+0.0007
+O.OOOB
+0.001
+0.0014
+0.002

2

+10

0.0042
0.0056
0.0070
0.0084
0.0098
0.014
0.Q196

0.1065
0.1432
0.17BO
0.2130
0.2460
0.3530
0.4920

3
4
5
6
7
10
14

+10
+10
+10
+10
+10
+10
+10

20

50

100 200

500

mn PER FOOT

RT = R20'C [1 + 0.004 (T + 20'C)1
At 55'C:

(eq. B)

R = R20'C [1 + 0.004 (55'C - 20'C)1 = 1.14 R20'C
When specifying power bus dimensions for PC cards can·
taining many IC packages, designers should bear in mind
that excessive current densities can cause the copper tern·
perature to rise appreciably. Figure 8 illustrates the ohmic
heating effect of various current densities.1
10r----,-----r~~~--

mm

0.0715

10

TEMPERATURE COEFFICIENT
The resistances in Figures 3, 5, and 7, as well as those used
in the sample calculations, are 20'C values. Since copper
resistivity has a temperature coefficient of approximately
0.4%I"C, the resistance at a temperature (T) can be deter·
mined as follows.

__----~

J~/V

Tolerances
By

0.0028

5

TUF/10790-90

10- 5
10- 5
10- 5
10- 6

In.

1

\rI\

FIGURE 7. Conductor Resistance vs
Thickness and Width

FIGURE 5. Sheet Resistance for Various
Thicknesses of Copper
Nominal Thickness

2

RESISTANCE -

Sheet
Resistance

3.364
1.358
1.OB6
2.715

II \. I\~

0.011-....L.....L..u.u.u~I...L...L.:L.L.IlI.J.I.u......IlI..A.u

0 per Square

10- 4
10- 4
10- 4
10- 5

~I'\

f'%l."

I-

0.02

V = IR - (50) (3.364 X 10- 5) ~
(eq.7)
1.25
= 0.0484 = 48.4 mV
Sheet resistances for various copper thicknesses are listed
in Figure 5. Standard thicknesses and tolerances for copper
cladding are tabulated in Figure 6 and resistance per foot as
a function of width is shown in Figure 7.
Weight
or
Thickness

"

c

..
I

8.01----t-V,~/(~0.C+-/--1-/--..1

zw

a:
a:

::>

6.0

/

/

1

'

V

(.)

/

/

4.0,/

/10'C

Y

2.0 5~0-----'1~00~--1.,-J5~0----2J...00----2..L50----300.J
CROSS-SECTIONAL AREA - mU2
TUF/10790-91

FIGURE 8. Temperature Rise with Current
Density In PC Board Traces

FIGURE 6. Thickness and Tolerances for
Copper Cladding

4·145

..... r---------------------------------------------------------------------,
DISTRIBUTION IMPEDANCE
ground direclly underneath the signal trace. Therefore, if
~

~

z

l~

R2

VEE = -4.5 V

VTT= -2 V
TL/F/l0790-96

RT

.n

R1fi
= 1.80RT

R2.!l
= 2.25RT

lEE (avg)
mA

PO(8vg)mW
Resistors

50
62
75
82
90
100
120
150

90
112
135
148
162
180
216
270

113
140
169
185
203
225
270
338

28.2
22.7
18.8
17.2
15.7
14.1
11.7
.9.4

109
87.9
72.7
66.5
60.5
54.5
45.4
36.3

FIGURE 13. Series Divider for Thevenln
Equivalent Terminations

rVEE= -4.5 v

TUF/l0790-97

Po (avg)mW

Zo
.n

RE

.n

lEE (8Vg)
mA

ICOutput

RE

50
62
75
90
100
120
150

269
331
399
477
530
634
791

9.8
7.9
6.5
5.4
4.9
4.1
3.2

12.9
10.4
8.6
7.1
6.5
5.4
4.2

25.8
20.6
16.8
13.9
12.7
10.6
8.1

TJ = TA

+ P08JA

(eq.10)

24·PIN FLATPAK (4 VI Al203 BASE

24-PIN FLATPAK (4 0) BoO BASE

FIGURE 14. Average Current and Power Dissipation
Using Pull-Down Resistor to VEE
THERMAL CONSIDERATIONS
System cooling requirements for ECl circuits are based on
three considerations: (1) the need to minimize temperature
gradients between circuits communicating in the single-ended mode, (2) the need to control the temperature environment of each circuit to assure that the parameters stay with·
in guaranteed limits, and (3) the need to insure that the
maximum rated junction temperature is not exceeded.
Temperature gradients are of no practical concern with
F100K circuits since they are temperature compensated;

AIR FLOW RATE - LINEAR FTJMIN.
TL/F/l0790-98

FIGURE 15. Junction-to-Air Thermal
Resistance vs Air Flow Rate

4·148

.

3>
instance, on a densely packed logic board in a horizontal
attitude in still air, the effective ambient temperature for an
IC varies with its position. An IC in the middle of the board is
subjected to air that is partially heated by surrounding ICs.
Additionally, the temperature of the board rises due to heat
flow through the component leads. These effects can cause
a much higher junction temperature than might be expected.

Conversely, when the maximum rate junction temperature
(+ 150·C), the package power dissipation, and the air temperature are known, the minimum flow rate can be determined by first determining the maximum thermal resistance.
Maximum 6JA =

(150~~ TAl

(eq.11)

For this value of 6JA the minimum flow rate is determined
from Figure 15.
When the system designer plans to depend on natural convection for cooling, it is recommended that thermal tests be
conducted to determine actual conditions. The effectiveness of natural convection for cooling varies greatly. For

REFERENCE
1. Harper, C.A., Editor, Handbook of Wiring, Cabling and Interconnecting for Electronics, McGraw-Hili, 1972.

4-149

Z

en
.....
.;:.

National Semiconductor
Application Note 679
FilipeSanna
Louise Yeung

Point-to-Point
Fiber Optic Links
TABLE OF CONTENTS

FOOl PHY layers in parallel require only one pair of fiber
optiC cables, one pair of transceivers, and one set of PHY
layer chips per channel, while yielding a typical data
throughput of 600 Mbits/sec (for a system with eight channels).

1.0 POINT-TO-POINT APPLICATIONS
2.0 SYSTEM OVERVIEW
3.0 CHANNEL SYNCHRONIZATION
3.1 Synchronization Timing Examples
4.0 PHY LAYER COMPONENTS
4.1 System Block Diagram
4.2 Channel Block Diagram
5.0 HOST INTERFACE CONSIDERATIONS
5.1 Data Interface
5.2 Control Bus Interface
6.0 TIMING BUDGET FOR WIRED AND STRUCTURE
6.1 Pull-Up Scheme
6.2 GAL Scheme
INTRODUCTION
A station using the ANSI X3T9.5 (FDDI) physical layer standard can transmit and receive data at 100 Mbits/ sec
through a fiber optic cable. However, with several physical
layers connected together in parallel, each with its own fiber
optic cables for transmission and reception, the station can
transmit and receive data at much higher speeds. National
Semiconductor's physical (PHy) layer devices can be connected together in parallel to achieve such high bandwidth
pOint-to-point links. The National devices required to implement a PHY layer are the DP63231 Clock Recovery Device
(CRDTM device), the DP63241 Clock Distribution Device
(CDOTM device), and the OP63251/55 Physical Layer Controller Oevice (PLAYERTM device). The bandwidth of the
system depends on the number of PHY layers used-each
set of PHY layer devices contributes 100 Mbits/ sec to the
system.

Any application where data throughput is the limiting factor
to system performance is a candidate for a high-speed
point-to-point link. For example, a pOint-to-point link can be
installed between a CPU and a disk controller to speed up
information storage and retrieval times. Another application
area could be in the display capabilities of a graphics workstation which can be combined with the data processing
power of a supercomputer to achieve visualization for data
intensive simulations (Figure 1). As a third example, a highspeed networking backbone using a point-to-point link is depicted in Figure 2. Here, separate FOOl rings are connected
together with a high speed link which provides bridging between rings without loss of performance.
Fiber optiCS afford a greater physical separation between
stations than electrical signals. Hence, a fiber pOint-to-point
link can be used to extend SCSI or IPI transmissions up to
one kilometer.

TLlF/10797-1

FIGURE 1. Polnt-To-Polnt Link between a
Supercomputer and a Graphics Workstation

1.0 POINT-TO-POINT APPLICATIONS
The use of parallel FOOl PHY layers is a cost effective
method to increasing the data throughput in multiples of 100
Mb/s. This task can be accomplished utilizing an existing
FDOI fiber plant.

4-150

TLlF/10797-2

FIGURE 2. High Speed Networking Backbone
Using a Fiber OptiC Point-To-Point Link

2.0 SYSTEM OVERVIEW

After travelling through the fibers, the data arrives at Stetion
II. Each PHY layer on the receiving end reads data from the
fiber and presents its byte to the corresponding PHY"--INO
port (at 12.5 MHz) in Stetion II. SYS_INO then rejoins the
bytes back into the 32-bit word sent by Station I and can
present the data to the host (at 12.5 MHz). This demonstrates how Station I can send 32 bits to Station II in BO ns,
giving an effective data throughput of 400 Mbits/sec.
Even though this is a non-FOOl application, the general
rules for FOOl framing must be followed. In particular, each
frame must start with a JK symbol and end with valid FOOl
ending delimiter (Figure 4). Furthermore, the frame size
must be between three and 4500 bytes long (see PLAYER
device datasheet for more detail). At least four pairs of idle
symbols should be inserted between the frames to allow for
readjustment of the PLAYER device's elasticity buffer. However, to guarantee at least one opportunity to recenter the
elasticity buffer between frames in the event of clock drift or
a single line hit in the interframe gap, the user is advised to
insert eight idle symbol pairs.

A system using four PHY layers in parallel is shown in Figure
3. The diagram demonstrates conceptually how data is
passed from Station I to Station II at 400 Mbits/sec. Each of
the four PHY layers in Station I is connected to a PHY layer
in Station II with fiber optic cables. Since National Semiconductor PHY layers are full duplex, each pair of PHY layers is
linked by two fibers, one for transmission in each direction.
The system interface shown contains two parts.
SYS_REQ. which handles data transmission, and
SYS_INO, which handles data reception.
Suppose that Station I wants to transmit a 32-bit word of
data to Station II. SYS_REQ in Station I takes the data and
splits it into four bytes, one for each PHY channel. Each
PHY layer reads its byte from the PHY"--REQ ports of
SYS_REQ (at 12.5 MHz) and sends the data out across
the fiber as an B-bit serial stream at 100 Mbits/sec. (Note
that due to the 48/58 encoding scheme used by the PLAYER devices the data actually passes through the fiber as a
10-bit serial stream at 125 MHz.)
132 bits 130D47FAI

SYSJND

SYS..REQ

1

.1-

I

.1-

T

T

.1-

PHYLIND

PHYLREQ PHYLREQ PHY3_REQ PHY4_REQ

i

T

PHY2JND 1 PHY3_IND

PHY4_IND

~'~$.
3D

D4

7F

AI

!

AJND

A..REQ

A..IND

PHYI
PlUND

I

I A..REQ

A..IND

PHY2

PM_REQ

PM../HD

I PM_REQ

A..REQ

------ - - - - - - - - - - - --

PM_IND

A..REQ

AJND

PHY4

PHY3

PM_IND

PILREQ

PM-REQ

-

--

------- --------

Station I

Fibor Optic Links

-- - PM_REQ

-------- - - PM_REQ I PM_IND

PM_INO

,

PHYI
A..REQ

-- - - -- ----------- -I- PILREQ

PHY2

A..IND

A..REQ

I A..IND

A..REQ

~

3D

I
i

T

PILREQ

PM_IND

A..IND

A..REQ

T

.1PHY1..JHD

T

.1-

SYS_REQ

A..IHD

8

AI

7F

I

Station II

PHY4

$.

PHY1-REQ PHY2_REQ PHY3_REQ PHY4_REQ

i

P\LIND

PHY3

IPHY2JND I PHY3JNDl PHY4_IND
1

1

1

SYSJND
132 bits 13DD47FAI
TL/F/l0797-3

FIGURE 3. System Using Four PHY Layers In Parallel
4-151

~

z



LBC _ _----'

+ ___. . .

Cascado Roady _ _ _ _ _ _ _ _ _ _ _

+ __________---1

Cascado Start _ _ _ _ _ _ _ _ _ _ _

..JX'-_____-'X~__...;;...__..JX....__....;J;;..K_ _..JX~___J;;;K_ _ _>G!::

A...lnd Pert _ _ _

TL/F/10797-5

FIGURE 5a_ First PLAYER device to receive a JK symbol in a large skew scenario. The CS
signal goes high about 60 ns after the CR line Is asserted. This Indicates that some of the
channels received JK symbols more than one LBC period after the channel shown.
PWD_IND

<'____JK_ ____"X'____n_n_1_ _-'X'____n;;..n;;..2_ _-'X'____n_n;;..3_ _-'X'____n;;..n4_ _--'>

LBC _ _---'

Cascado Ready

Cascade start

------------t-----'
------------t-------~

X

A...lndPort

X

X

JK

X

nn1

~
TUF/10797-6

FIGURE 5b. First PLAYER device to receive a JK symbol In a small skew scenario. The CS signal goes
high shortly after assertion of the CR slgnal,indlcating that all of the channels received JK symbols within t4.
PMD_IND

<

JK

X

nn1

X

>

nn2

X

nn3

X

nn4

X

JK

X

nn1

~

LBC

Cascado Roady

Cascado start

X

A...lnd Port

X

TL/F/10797-7

FIGURE 5c. Last PLAYER device to receive JK symbol (in any scenario). Since this device
was the last to assert its CR line, is is due only to the delay of the wired-AND structure.
PMD_IND

<'-___JK_ ____"X'____n_n_1_ _-'X'____n_n_2_ _-'X'-___n_n3_ _--'X'____n_n4_ ____">

LBC _ _---I

+ ___-'
_ _ _ _ _ _ _ _ _ _ _ _ _ _+ ________________________________________

Cascade Ready _ _ _ _ _ _ _ _ _ _ _
Casc~eStart

JX'___..;;..__-'X~__...;;...__..JX'___....;J;;..K_ _JX. . ____...;J;;..K___.....>G!::

A...Ind Port _ _ _

TL/F/10797-8

FIGURE 5d. PLAYER device which receives JK symbol In scenario
where one or more channels never receive JK symbols.
4-153

~
~

Figure 7 illustrates the source of timing deviations between

4.0 PHY LAYER COMPONENTS

the channels and demonstrates the need to minimize timing
skews between the channels wherever possible. In Station
I, we are concerned with TXC and TBC while in Station Ii we
examine LBC, since Station I is transmitting to Station Ii.
The time parameters shown in the figure represent the maximum deviations in propagation delay between channels.
For example, if t1 were 10 ns, this would mean that TXCI
TBC could arrive at PHYI up to IOns before arriving at
PHY2.

4.1 System Block Diagram
The number of PHY layers connected together in parallel is
limited only by the timing budget of the CS line (explained in
Section 5.2) and the timing skews between channels. As an
example, a system level block diagram using four PHY layers connected together in parallel is presented in Figure 6.
All of the PHY layers within a given station are driven with a
single set of clock Signals, and all are controlled and monitored by the host system through the Control Bus interface.
Each channel has two dedicated fibers, one for transmission and one for reception. The full duplex architecture eliminates the need for complex handshaking between the two
stations. The four channels communicate through the CR
and CS signals. For simplicity, the CR lines are shown connected to a pullup resistor-a more detailed look at the connection of these pins is given in Section 6.

t1 represents the skews in TXC/TBC between the channels,
t2 encompasses the skews in the PHY layer's transmitting
path, t3 represents the differential skews amongst the fibers, I.j includes all of the skews inherent in the PHY layer's
receiving path, and ts represents the skews in LBC between
the channels in the receiving station. All of the skews together must not exceed 80 ns in order to prevent synchronization errors, and smaller total skews will provide greater
stability across temperature and power fluctuations.
In a worst case scenario where all devices were badly
skewed, t2 together with I.j yields a base 30 ns of skew
between the channels. This leaves 50 ns available for differential skews in the clock Signals and the fiber. It is recommended that t1 be held to 4 ns and ts kept under 8 ns to
prevent misclocking of the data. Hence, the maximum skew
among fibers should be less than 38 ns.

The global clock scheme should be arranged to minimize
the skews in the clock signals between PHY layers. Smaller
clock skews between channels will leave more tolerance for
device skews and fiber optic variations. For further recommendations concerning the COD device in a multiple PLAYER device environment, see the COD device datasheet
(COD Device Driving Multiple PLAYER Devices).

Vec

Contro I Bu,
Interface

/).

pullu

PHYI

..

To FOTX ...
From FORX

r

r-

TX Data
RX Data

Port A Req

.

From

rORX

,......
r

Port A Ind

Clock Inputs

JK Deloci 1
Cascade Ready
10
10

Data In
Data Out

ij
PHY2

To FOTX ...

Cascad. Start
Cascade Ready

Ca,cade Start

TX Data

Cascade start
Cascade Ready

RX Data

Port A Req
Port A Ind

Clock Inputs

Cascade Start
JK Detecl2
Cascade Ready
10
10

Data In
Data Out

j'j
....

.

To FOTX ...
From FORX

,......
r

PHY3
TX Data

Cascade Start
Cascade Ready

RX Data

Port A Req
Port A Ind

Clock Inputs

Cascade Start
JK 0elocl3
Cascade Ready
10
10

Data In
Dala Out

j'j
PHY4

....

To FOTX ....
From FORX

.-

COO
LBC
TBC
TXC

5

TX Data

Cascade Start
Cascade Ready

RX Data

Port A Req

Clock Inpuls

Port A Ind

Cascade Start
JK Detect 4
Ca,cade Ready
10
10

Data In
Data Oul

-iJ
TL/F/l0797-9

FIGURE 6. PHY Layer Block Diagram for an Example System Using Four PHY Layers In Parallel
4-154

.

~------------------------------------------------------------------~~

For example, for a typical FOOl fiber optic cable, s = 1.9 X
108 mIs, v = 0.005, and w =0.001. Solving for I with
these parameters results in a length of 667 meters.

The following equation summarizes the tradeoff between
cable length and variance:

~-~<38ns
s (1 - w) s (1 + w)

z

G'I

........

co

where: s is the speed of the signal in the cable
I is the average length of the fiber in meters
v is the variance in the length of the cable
w is the variance in the speed of the signal through
the fiber
TXC
~
COD

11

Slation I

'

,

I

I

I

I

Slation II

~

LBC

-+- 12 - - : - - 13 - . : - 14 -+- 15

H

H

PHY1:

PHY2

~

-:

PHYl

11--.
"'_1IIj1

PHY2

~--~I

~

COD

t-t--

I~__~

TUF/10797-10
Where:
t,

~

Worst case clock skew between two PHYs

t2 ~ Worst case skew between PLAYER device propagation delays

ta = Worst case skew between Fibers
t,

~

Worst case skew between PLAYER device propagation delays

t5

=

Worst case clock skew between two PHYs

Total skew = t1

+ t2 +

t3

+

t,

+ t5

Note: Total skew must not exceed 80 ns in order to prevent synchronization errors.

FIGURE 7. Origin of skew between channels. Adding all of the skews
(tl through t5) gives the total possible skew for the system.
4.2 Channel Block Diagram
Figure 8 shows the components which constitute a single
PHY channel (the COO device is common to all channels so
it is not shown here). The fiber optic transceivers are stan·
dard FOOl devices which translate electric signals to light
pulses and vice versa. The fiber optic receiver accepts data
from the fiber and sends two pairs of differential ECl signals
to the CRO device. namely signal detect and data. The CRO
device extracts a clock signal from the incoming data and
passes a resynchronized equivalent of this data and are·
covered clock signal to the PLAYER device, as well as sig·
nal detect and clock detect signals.

PLAYER device, then the Cascade Sync Error (CSE) bit will
be set in the Control Bus register RCRB by the first PLAYER
device to have recognized a JK symbol.
5.0 HOST INTERFACE CONSIDERATIONS
5.1 Data Interface
The system interface should consist of a transmit holding
register and buffer for transmission and a buffer and receive
register for incoming data. A state machine is required to
decode the symbols coming from the PLAYER device so
that only data is stored. Furthermore, a controller will be
required to monitor and manage the PLAYER device
through the Control Bus interface. This controller must han·
die the initialization of the PLAYER device and report error
conditions to the host.

Within the PLAYER device, the incoming data stream is de·
coded (from 5B to 4B) and placed in the elasticity buffer.
When in cascade mode, the elasticity buffer is used not only
to absorb variations between the received clock and the
local clock, but also to smooth out skews between incoming
data presented to the different PHY channels. If all of the
PLAYER devices receive JK symbols within 80 ns of each
other and release their CR pins, then the CS pin will go high
and all of the PLAYER devices will read from the first data
location of the elasticity buffer. This cell contains the first
byte of data received after the JK symbol. Hence, the elas·
ticity buffers facilitate the coordination of data output be·
tween the different PHY channels. If the last PLAYER de·
vice receiving a JK does so more than 80 ns after the first

Each PLAYER device takes ten bits of data at the A Request Port, a pair of 4·bit data symbols plus a parity and
control bit. (See the PLAYER device datasheet for the
PHY_MAC byte wide interface table.) The system interface
can thus generate parity and control for each PLAYER device separately and check control and parity coming from
each channel. To simplify the system interface, however,
the parity pins can be tied to ground and parity checking can
be disabled in the Current Transmit State Register (CTSR).
Parity information coming from the PLAYER device can similarly be ignored.

4·155

II

AN·679

--------------------------------------------------------------------.
Channel N
(PHY N)

I

l~~Q

PLAYER N
lJ(
lJ(

out~~~~

Data
Control

fOTX

IncomIng
Fiber

,
I

FORX

Signal Detect
RX Clock
RX Data

Data

eRD

~ I Decoding

:I

Clock Detect

Logic

I

~

Loopback Data
CRD Control

I I
A

81C

I

D

r

ElasticHy Buffer

L~~D

E

~

I

M,5

Data

10

1MUX Select

L----JI-"-;;;..;=;.;.;..1

U1
O'l

8egln
Set JK

DQ

D 8egln
DQ

~ I~
~

~
....- - -...........- - - - - - - - - '
000

~ ~ ~

Con~!~~tlon

).... Sync
Error

I r<:I....J _-

I~
"'?~'J:.

From Host
Transmit
Register

8

:
I
I
Control

I
I

Parity
Data

I
•

cascade Start

pin 47

cascade Ready

pin 48

~

'"

To Host Receive
Register

:

Control8u.
Interfaca

------------------------ --------------------'"
CDD Int.rface
(Global)

I

I
I

I

L.....,.[JK

!

Control
Parity
Data 8

TX Block

""'--'""1 Signal Detect

:

...

15

I
I
I

JK Detect

I

~
I
I

I
I

~---------------.

7

To Host Controller
TL/F/l0797-11

FIGURE 8. Block diagram of one PHY channel. The components shown here are repeated for each separate channel in the system.

In error situations, one or more PLAYER devices may report
a Cascade Sync Error, but they may not do so simultaneously depending on when they receive JK symbols. The
Cascade Sync Error (CSE) bit of the Receive Condition
Register B (RCRB) will be set by each PLAYER device
which receives a JK but does not sense the CS pin go high
before the second falling edge of LBC from when CR was
released. CS has to be set approximately within 80 ns of CR
release. If a JK symbol is completely corrupted from a line
hit or bad connection, the PLAYER device on that channel
will not report a CSE. Only the data on the channel(s) which
did not report a CSE will be corrupt, however, these are the
channels which were unable to synchronize with the rest of
the group. All of the PLAYER devices which receive a JK
symbol (and release the CR pin) will read data from the first
cell of the Elasticity Buffer. Therefore, a line hit on a single
fiber will not wipe out the entire frame. The rest of the channels may still output synchronized data. This is particularly
important in applications where partial data reception is still
useful. For example, during screen updates in high resolution graphics systems, only one line of pixels would be lost
instead of an entire block of the screen blanking out.

Thus if m is 20 pF and n is 2, the maximum pullup resistor is
5000, which meets the specification for the minimum resistor size. However, it is apparent that for many PLAYER devices a passive pullup resistor is too slow.
6.2 GAL Scheme
As a result, we recommend using external logic devices for
any system with three or more cascaded PLAYER devices.
The choice of devices is limited by the propagation delay as
well as fan in or fan out. Each CR pin should be pulled up
with a 4000 resistor and fed into the AND gate. A recommended device to perform the AND function is the
GAL16V8A chip, which offers 8 inputs and supplies 8 outputs with a propagation delay of IOns. This chip will allow
up to eight PLAYER devices to be cascaded together while
still maintaining the necessary delay, fan in and fan out
characteristics. The device should be place in the electrical
center of the cascaded devices to prevent excessive timing
skews among the chips. Figure 9 depicts an eight channel
system using the GAL16V8A to AND the CR signals together.

v

.~

5.2 Control Bus Interface
If no JK symbols are corrupted, but they arrive with more
than 80 ns of skew, all of the PLAYER devices will eventually report a CSE error. Hence the control microprocessor has
the ability to pin point the corrupted channel or determine if
the problem is due to excessive skew between the channels. Note that the Control Bus registers can be programmed to assert the interrupt (INn pin upon detection of
the CSE flag.
To place the PLAYER devices in Cascade Mode, the Mode
Register (MR) must have the Cascade Mode (CM) bit set to
one. The Cascade Synchronization Error (CSE) of the Receive Condition Register B (RCRB) is set to one if the CS
signal fails to go high within 80 ns of recognizing the JK
symbol. The RCRB also reports Elasticity Buffer errors
through the EBOU bit, signaling a loss of data from the fiber.
These bits must be cleared by the Control Bus controller.
When the number of PLAYER devices and the total capacitance is small, it may be possible to tie all CR pins and CS
pins together and use a single pullup resistor. The lower
limit of the pullup resistor is calculated as follows. The CR
pins typically sink a 13 mA maximum, so the equation for
the smallest resistor which should be used is:
RMIN = Vee/0.0130
Hence for a voltage supply of 5V, the resistor value is
5/0.013 = 3850. The upper limit of the pullup resistor depends on the capacitance of the system and the number of
PLAYER devices used. Restricting the timing budget (tb) to
20 ns (worst case) for the AND function, we arrive at the
following equation:
RMAX = tb/(m x n) 0
where: m is the capacitance associated with each PLAYER
device's CR line (including the IC capacitance (4
pF), the socket capacitance, and the trace capacitance) measured in pF
n is the number of PHY channels (number of cascaded PLAYER devices).

4-157

,. 400D.

CRLt-_+_---.

PHYl

c~ !t----+---------.
400D.

PHY2

CR I

C~ I

'.

'-'----

•
•
•
•
•

~J

r--

GAL 16V8A
Vee

;:
400D.

..

CRLt-_+_---'

PHYB

cs:L

........................................~

~

---'

TL/F/10797-12

FIGURE 9. Example of an eight channel system
using a GAL16V8A chip to perform the AND
function on the CR lines. The resulting signal (CS)
is fed bacl, Into each of the PLAYER devices.

...mr----------------------------------------------------------------------------.
High Speed, Point to Point,
r-.

o

tn

National Semiconductor
System Brief 107

Fiber, Data Communication

HOST

HOST

FIBER OP1lC CABLE

TL/F/l0857-1

Serial Polnt-to-Polnt Data Communications
SYSTEM DESCRIPTION
Point-to-Point links are needed in any application where
data throughput is the limiting factor to system performance.
They can be installed between a CPU and disk controller to
speed up information storage and retrieval times or the display capabilities of a graphics workstation can be combined
with a supercomputer to achieve visualization for data intensive simulation. Point-to-Point links can also be used in a
high-speed networking backbone where separate FOOl
rings are connected with a fiber link to provide bridging with-

out loss of performance. Fiber optics can be used to extend
SCSI or IPI transmissions. High bandwidth, greater than
100 Mb/s, pOint-to-point applications can use parallel FOOl
PHY layers. High bandwidth point-to-point solutions prove
parallel FOOl PHY layers to be cost effective, simple systems with minimal logic, and requiring only standard FOOl
fiber optic transceivers (which operating at 125 MHz, are
less expensive than a GHz laser).

System Block Diagram: Two Parallel PHY Layer In Cascade Mode

__

CONTROL BUS INTERFACE

L..--._~~

pullup
PLAYER 1
Cosoade Start
-I1J( Data
Cosoade Start
JK Delect 1
Cosoade Ready I-:Co:-so-ad-:-e-=R:-e.--d:-y......

t----+-+---tlRX Data

PortA Roql+--...,.S"-+-Data In
Pori A Ind
S
Data Oul

200Mb!.

fiber Optic
Link

PLAYER2 Co

~""'''''_''-I1J( Data
RX Data

d start Coscade Start
soa 0
1-:,..........,...-=-.......---1 JK Delect 2
Coscade Roady Coscade Roady
Port A Req
PortA Ind

S
S

Data In
DataOui

CDD

LBC
TBCI-~'"
1J(C

TLlFI10857-2

4-158

DESIGN CHALLENGES

1. Need for high bandwidth, high throughput, and high reliability.
2. Need to interface with a variety of system applications
and maintain security and reliability.
KEY COMPONENTS
1. Clock Distribution Device (CDDTM) provides the clocks
needed for the PLAYERTM device and the host if needed. It provides 125 MHz differential ECl signals from an
inexpensive 12.5 MHz crystal.

2. Physical layer Controller Device (PLAYERTM) performs
the encoding and serialization of transmitted data, and
deserialization and decoding of received data. It is compatible with 48/58 and NRZI transmission code, and
supports both Single and dual attach station configurations.
3. Clock Recovery Device (CRDTM) extracts the clock signal from incoming data and passes a resynchronized
equivalent and a recovered clock signal to the PLAYER
Device.
4. Transceiver provides electrical to light conversions.

BilL OF MATERIAL
Function

Description

Decoding

PLAYER

Clock Recovery

NSC

Other Mfg.

Qty

DP83251/55

2

CRD

DP83231

2

Clock Distribution

CDD

DP83241

Transceiver

FOTX
FORX

AND Function

GAL

2

2
GAl16V8A

1-8

II
4-159

....

N.---------------------------------------------------~====::l

National Semiconductor
System Brief 112

;i; FOOl Concentrator
rn

FOOl Applications

FOOl TO
FOOl
BRIOG!:

FOOl TO
ETHERNET
BRIDGE

FOOl F1I0NTINO

TUF/11005-1

SYSTEM DESCRIPTION
The Concentrator plays an important role in the Fiber Distributed Data Interface (FDDI) architecture. FDDI offers a
whole range of network topology alternatives. The concentrator simplifies the wiring of networks and allows logical
ring topologies to be created from the typical star wiring
configuration. The concentrator provides a very reliable and
economic method of obtaining fault tolerance. The concentrator provides drops to individual nodes in order to include
them in the network. When the concentrator senses a failure on one of the drops, it 'heals' the ring by electronically
bypassing that station. Properly designed concentrators can
bypass any number of drops with no degradation in performance.
The concentrator is an extremely chip intensive system. The
small footprint, low power consumption, and special bridging features provide the ideal solution for concentrator applications. Concentrators are ideal for the needs of interconnectivity as addressed through high performance FDDI networks.

KEY DESIGN CHALLENGES
Management Software
Developing the Network Management software to manage
all aspects of the concentrator and participate in the network management protocols is not a trivial task. The concentrator is also the best location for network diagnostic
support including network monitors.
Modular Design
Keeping the design modular, while maintaining its manageability and flexibility, can save design time and manufacturing
costs. Key to the architecture is to provide high throughput
and flexibility to interface to a variety of system configurations.
In a multiboard design several other design challenges are
present including other clock distribution, multi-processor
communication, and backplane design issues.
Clock Distribution
Each port within a concentrator requires 125 MHz and
12.5 MHz clocks; the distribution of these clocks is not a
Simple task; the CDD device provides an elegant solution.

4-160

System Diagram
HETWORI( WONITOR

-OR-

~

TO TR1JHX """

!

~

10 STATlOM

TO STATION

TO STATION

TO STAmM

TLlF/11005-2

Single Board Concentrator Design

U~·8S

iii

N

.,....
.,....

iii
(/)

CDDTM

KEY COMPONENTS
PLAYERTM (Physical Layer Controller) device converts the
BMAC device Mby1e stream into an encoded bit
stream as specified in the FDDI PHY standard.
It synchronizes the received bit stream to the
local clock and decodes the 4B/5B data into
internal code. The PLAYER device also contains a configuration switch for use in dual attachment stations and concentrators.
BMACTM (Basic Media Access Controller) device implements the functions defined by the ANSI
X3T9.5 FDDI Media Access Control (MAC)
standard. The device consists of the transmit
and receive state machines, an address magnitude compare unit, a CRC generator and checker, protocol timers, and diagnostic counters.

(Clock Distribution Device) device generates
the clocks required by the PLAYER and BMAC
devices, one per board.
(Clock Recovery Device) device extracts specific incoming clock data from the upstream station. Its features include on-chip loopback control, crystal control, the ability to lock to a master line state in less than 100 P.s, and a single
+5V supply.

CRDTM

NS32GX32
or HPC
Performs the control interface with fast and flexible 1/0 control, efficient data manipulation, and
high speed computation.

BILL OF MATERIAL
Function

Description

Part No.

Quantity

Controller
Controller
Clock Distribution
Clock Recovery
Controller or
Processor
Logic
RAM

BMAC
PLAYER
CDD
CRD
HPCor
GX
PAL
8k DRAM or
16kSRAM
+5VSupply

DP83261
DP83251 155
DP83241
DP83231
HPC16400
NS32GX32

1/2

Power

4-162

4
1(4)
4
1
1
1
1
1
1

.

en

m
......
......

National Semiconductor
System Brief 115

An FODI-Ethernet Router

U1

ETHERNET LAN

COMPUTERS/
TERMINALS

ROUTER

FILE
SERVER

TL/F/11047-1

FIGURE 1. A Router Configuration in a Typical Network
SYSTEM DESCRIPTION
A router connects multiple networks and routes packets between them. Figure 1 illustrates a typical router configuration. Here, a dual attach FDDI node and four Ethernet ports
enable the router to interconnect an FDDI ring and up to
four Ethernet LANs. The FDDI and Ethernet interfaces are
implemented using high performance peripherals: the
DP83200 FDDI chip set and the DP83932 Systems Oriented
Network Interface Controller (SONICTM).
TCP/IP is an industry standard for networking and many
routers implement the IP protocol. The router presented
here implements TCP/IP in full, providing reliable routing of
packets across multiple networks. In doing so it offers such
services as confirmation of packet delivery, packet routing

and fragmentation, error reporting, address filtering and so
on. Such a software intensive application requires a highly
integrated, high performance embedded processor and
therefore the NS32GX320 was chosen.
Figure 2 illustrates the router architecture. It consists of two
32-bit wide buses that separate network traffic from the
processor bus activity. Each contains a 4/16 Mbyte bank of
DRAM: one for the GX320 to run it's application software
and the second for buffering received packets and queuing
new ones to be transmitted.

In addition, there is a third "bus" for accessing the FDDI
chip set registers and all the 8-bit system devices, such as
EPROMs, an EEPROM, a UART and a SCSI controller.

4-163

r--------------------------------------------------------------------------------....
....
U)

cD

U)

TO ETHERNET LANS

TLlF/11047-2

FIGURE 2. The Router Block Diagram
KEY COMPONENTS
a. DP83200 FOOl Product.
Includes: BSI, BMAC, PLAYER, CRD, COD Devices and
SMT software. The FOOl chip set fully implements a 32bit wide system interface, all MAC (Media Access Control) functions and the physical layer interface to the fiber
optic ring. The FOOl Product also includes FOOl SMT
software.
b. DP83932 SONIC
The Systems Oriented Network Interface Controller provides a 32-bit wide system interface, implements all MAC
functions and includes an ENDEC (Encoder-Decoder) for
the serial interface to an Ethernet transceiver.
c. NS32GX320
The GX320 is a highly integrated, high performance embedded system processor designed for compu1ation intensive applications. It incorporates a four stage instruction pipeline, on chip instruction and data caches and a
hardware multiplier unit. The internal organization allows
for a high degree of parallelism in instruction execution.
Integrated on the same chip with the CPU are also two
channel DMA controller, a fifteen level Interrupt Controller Unit and three 16-bit timers.

DESIGN CHALLENGES
Throughput and Bandwidth Considerations
A router must be able to process frames arriving at a peak
rate of 100 Mbits/sec over the FOOl ring and 10 Mbits/sec
on each of the four Ethernet LANs and then route them
back onto the network with minimum latency. This is
achieved using the above architecture and National Semiconductor's advanced chips.
Application Software
The application software plays a dominant role in a router.
The software design consists of a router program and TCPI
IP protocol (compatible with BSD UNIX 4.3 implementations
of Routed and TCPIIP, respectively), buffer management
and device drivers. Also included is FOOl SMT (Station
Management) software. All these modules must run coherently to produce high performance and throughput.
Future Expansion
The router's design accommodates future enhancement
and expansion. It may also serve as a hardware platform for
other applications such as a multiple network file server or a
network printer interface.

a

BILL OF MATERIALS
Description

Function

Part No.

Quantity

System Processor

Embedded Controller

NS32GX320

1

Controller

BSITM

DP83265

1

Controller

BMACTM

DP83261

1

Controller

PLAYERTM

DP83255

2

Clock Recovery

CRDTM

DP83231

2

Clock Distribution

CDDTM

DP83241

1

Controller

SONIC

DP83932

Memory

4/16 Mbyte Bank of DRAM

2

Logic

PAL4Ds/GAL4Ds
Octels

17
12

Optical

Transceivers

2

Power

+5V, + 12V, -12V

1

4-164

1

.

(/)

m
.....
.....

National Semiconductor
System Brief 116

FOOl-Adapter Card

CD

roDI BACK END
DISK

CONTROLLER

fOOl TO
fOOl
BRIDGE

roor TO
ETHERNET

CONCENTRATOR

BRIDGE

TlIF/l104B-l

FIGURE 1. System Diagram of Adapter Cards Found in WS/PCs and the Concentrator
SYSTEM DESCRIPTION
Computer vendors have unique system architectures like
countries of the world have different languages. The goal of
an FOOl adapter card is to bridge the "language barrier"
between the host and an FOOl network in a speedy and
efficient manner. Choosing the interface that best fits the
application is the key to achieving this goal.
The National Semiconductor FOOl chipset provides a simple but powerful interface that can deliver the potential
bandwidth of an FOOl network to a wide variety of system
architectures. This interface gives the designer the flexibility
to define systems which require high network bandwidth
with minimal latency or systems in which footprint size and
system cost are the most important constraints.
An example of the need for a high bandwidth network can
be found in a factory environment. Such a network would be
responsible for tying together time critical tasks in a highly
reliable manner. An FOOl network, which is fiber based and
inherently reliable, is ideally suited for this application. The
interface from the FOOl network to the system host must
provide low latency and high throughput. With the National
Semiconductor FOOl chipset, it is possible to connect di-

rectly to the system bus as a bus master with a peak bandwidth of 96 megabytes per second. In this configuration, the
constraints of the design are met with a solution that is efficient and requires little or no external logic.
Workstations that pack supercomputer power, fit into a footprint that fits on a desktop, and cost under $10,000 are
leading edge example of the evolutionary growth of computer technology. This ability to process information at break
neck speeds has increased the need for high bandwidth,
cost effective networking solutions that can effectively connect these systems. Features of the National Semiconductor chipset allow the designer to tailor the network interface
to satisfy constraints imposed by the host architecture. For
example, the chipset may be connected directly as a bus
master on the system bus or through shared memory which
may use low-cost ORAMs or faster SRAMs. Bit ordering and
high-speed protocol processing are also handled by the National Semiconductor FOOl implementation. Additionally,
the chipset can easily be used to implement an FOOl concentrator which delivers the power of FOOl at a lower cost
by reducing the number of networking ICs built into each
end station.

4-165

•

~r-----------------------------------------------------------~
..-

m

BUFFER
MEMORY
64k x 32
.t.

?AI~--------------~"

...; !:rr'f---;::=::=;---v'il'

PC-AT
BACKPLANE

AT
INTERFACE

r--~~-.......I--.JI LOCAL L-----.
____ SYSTE~~~;ERFACE rr 1 OSCILLATOR .-----ro
(BSI)

1+-+

DP83265
ARBITER

r+
...

CLOCK
DISTRIBUTION
DEVICE
(CDD)
DP83241

1---1.....

7'

.... 7"
PHYSICAL

L.. LAYER CONTROLLER
--.

... ".

BASIC MEDIA ACCESS . ._ _ _ _ _ _+1
CONTROLLER
(BMAC)
DP83261
... ~

I PROM
I TIMER

j+-.

CONTROL BUS

j+-.

-(PLAYER)
DP83251/55

CLOCK
RECOVERY
DEVICE
(CRD)
DP83231

1

TO FIBER OPTIC TRANSCEIVER
TLlF/ll048-2

FIGURE 2. Example of AT Based FOOl Adaptor Card
KEY C~MPONENTS
DP83261 Basic Media Access Controller (BMACTM Device)
DP83255/51 Physical Layer Controller (PLAYERTM Device)
DP83231 Clock Recovery Device (CRDTM Device)
DP83241 Clock Distribution Device (CDDTM Device)

MAJOR CHALLENGES
1. Choice of an FDDI implementation
A successful adapter card design must first start with the
best FDDI solution. The National Semiconductor FDDI
chipset offers a full-featured and complete solution.

The four devices listed above compose an FDDI-compliant,
full-featured networking solution. The solution offers a fullduplex data pipe that delivers maximum FDDI bandwidth.
Additional features include a thorough SMT interface and
provisions for the straight forward design of bridges, routers,
and concentrators.

2. Design of the network/host interface
The design of an FDDI interface must eliminate data "bottle necks without demanding excessive design complexity or component count. The National Semiconductor
FDDI chipset provides full FDDI bandwidth through a simple but powerful system interface. This interface can be
tailored to create an optimal interface to a variety of system architectures.

DP83265 BMAC System Interface (BSITM Device)
The BSI provides a simple but powerful system interface.
The architecture can be connected directly to the host bus
as a bus master or connected to the host through a shared
memory -architecture which uses low-cost DRAMs or faster
SRAMs.

3. Future Integration
In order to maintain a leadership position in FDDI networking, an FDDI vendor must follow the same evolutionary path on the performance/value curve that has been
defined by the computer industry. National Semiconductor has developed an aggressive strategy to provide the
user with a consistent interface to work with while driving
toward a one chip FDDI solution.

4-166

.----------------------------------------------------------------------.~

BILL OF MATERIAL
Function

Description

Part No.

Quantity

System I/F

BSI

DP83265

1

Controller

BMAC

DP83261

1

Controller

PLAYER

DP83251/55

1

Clock Recovery

CRD

DP83231

1

Clock Distribution

CDD

DP83241

1

SMT Node Processor

Embedded Controller

HPC46003

1

SMTTimer

Real Time Clock

DP8570A

1

Memory

DRAM/SRAM
PROM

(if necessary)

Logic

PALS/GALS
Octels

(if necessary)
(if necessary)

Fiber Optic Transceivers

125 MHz RX/TX

4-167

1

2

'P
.....
.....
G)

Section 5
Appendixl
Physical Dimensions

II

Section 5 Contents
FOOl and Networking Acronyms. . . • . . . . . . . • . • . . . . . . . • . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary of Terms for FOOl. . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . • . . . . . • . . . . . . . . . . . . .
Physical Dimensions............................................... .................
Bookshelf
Distributors

5·2

5·3
5·4
5·7

FOOl and Networking Acronyms
Description

Acronym

Acronym

Description

ALS

Active Line State

LSU

Line State Unknown

ANSI

American National Standards Institute

MAC

Media Access Control Layer

BMAC

Basic Media Access ControllerPart of National's Solution

MIB

Management Information Base

BMAC System InterfacePart of National's Solution

MIC

Media Interface Connector

MLS

Master Line State

BSI
CCE

Configuration Control Element

MPM

MAC Placement Management

CDD

Clock Distribution DevicePart of National's Solution

NFS

Network File System

NIF

Neighborhood Information Frame

CFM

Configuration Management

NLS

Noise Line State

CMT

Connection Management

NRZ

Non-Return to Zero

CRC

Cyclic Redundancy Check

CRD

Clock Recovery DevicePart of National's Solution

NRZI

Non-Return to Zero Invert on Ones

OSI

Open Systems Interconnection

CSMAlCD Carrier-Sense Multiple
Access with Collision Detection

PCM

Physical Connection Management

PDU

Protocol Data Unit

DA

Destination Address

PHY

Physical Layer

DAC

Dual Attach Concentrator

PLAYER

DAS

Dual Attach Station

Physical Layer ControllerPart of National's Solution

DLL

Data Link Layer

PMD

Physical Medium Dependent Layer

ECM

Entity Coordination Management

QLS

Quiet Line State

Fe

Frame Control

RMT

Ring Management

FCS

Frame Check Sequence

SA

Source Address

FDDI

Fiber Distributed Data Interface

SAS

Single Attach Station

FTP

File Transfer Protocol

SDU

Service Data Unit

HLS

Halt Line State

SMT

Station Management

IEEE

Institute of Electrical and Electronic Engineers

SNMP

Simple Network Management Protocol

ILS

Idle Line State

TCPIIP

ISO

International Standards Organization

Transmission Control
Protocollinternet Protocol
Token Holding Time

LAN

Local Area Network

THT

LCT

Link Confidence Test

TNE

Noise Events Timer

LED

Light Emitting Diode

TRT

Token Rotation Timer

LEM

Link Error Monitor

TVX

Valid Transmission Timer

LLC

Logical Link Control

WAN

Wide Area Network

5-3

.~National

~ Semiconductor

Glossary of Terms for FOOl
(listed alphabetically)
4B/5B: The symbol coding method specified by the FOOl
standard where each set of four bits is encoded as five bits
as compared with the Manchester coding method which requires eight bits of coding for each four bit set.

Concentrator: A Node on the FOOl ring, which in tum provides connections for multiple FOOl stations so that they
may communicate with other attachments to the FOOl ring.
A concentrator has at least two Physical Layer entities and
mayor may not have one or more Oata Link Layer entities. It
provides a logical star topology while stations are physically
connected as a ring. The concentrator (or center of the star
topology) can actively bypass a station connected to it.
Connection Management (CMT): That portion of the Station Management (SMn function that controls network insertion, removal, and connection of PHY and MAC entities
within a station.

ANSI: The American National Standards Institute. They are
responsible for setting many standards, including FOOl.
Asynchronous: A class of data transmission service
whereby all requests for service contend for a pool of dynamically allocated ring bandwidth and response time.
Attenuation: Level of optical power loss expressed in units
of dB.
Average Power: The optical power measured using an average reading power meter when the FOOl station is retransmitting a stream of Halt symbols.

Connector Plug: A device used to terminate an optical conductor(s) cable.
Connector Receptacle: The fixed or stationary half of a
connection that is mounted on a panel/bulkhead. Receptacles mate with plugs.
Dual Attachment Concentrator (OAC): A concentrator
that offers two attachments to the FOOl network which are
capable of accommodating a dual (counter-rotating) ring.

Backbone Network: A network which interconnects networks via gateways, bridges, and concentrators.
Back End Network: A network which interconnects mainframe computers to high performance mass storage devices, high speed controllers and file servers.
Bandwidth: The level of communication capability of a
transmission link. The greater the bandwidth, the greater
the volume of information the link can carry in a given time.

Dual Station (or dual attachment station): A station that
offers two attchments to the FOOl network which are capable of accommodating a dual (counter-rotating) ring. It may
offer additional attachments (see concentrator).

BEACON Frame: Frame sent during the BEACON process
to indicate and recover from a break in the ring.

Entity: An active element, or functional agent, within an
Open System Interconnection (051) layer, or sublayer, or
SMT, in a specific station, including both operational and
management functions.
Extinction Ratio: The ratio of the low, or off optical power
level, (PL) to the high, or on optical power level, (PH) when
the station is transmitting a stream of Halt symbols.
Extinction Ratio (%) = (PL/PH) °100

Bit: A single character of a language having just two characters, as either of the binary digits 0 or 1.
Bypass: The ability of a station to be optically isolated from
the network while maintaining the integrity of the ring.
Cable Plant: This term refers to the installed cabling, connectors, splices and patch panels within a given plant.
Carrier Source: The component of a fiber optic system
which generates the light wave, or carrier, on which information is transmitted. e.g., LEOs or LOs.

FOOl: Fiber Oistributed Oata Interface.
Fiber: Oielectric material that guides light; waveguide.
Fiber Optic Cable: A jacketed fiber(s).

Capture: The act of removing a Token from the ring for the
purpose of Frame transmission.

Fiber Optics: A technology whereby signals are transmitted
over an optical waveguide medium through the use of lightgenerating transmitters and light-detecting receivers.

Center Wavelength: The average of the two wavelengths
measured at the half amplitude points of the power spectrum.
CLAIM Frame: Frame sent during the CLAIM process
whereby one or more stations bid for the right to initialize
the ring.

Frame: A Protocol Oata Unit (POU) transmitted between cooperating MAC entities on a ring, conSisting of a variable
number of octets.
Front End Network: A network which interconnects workstations, word processors, personal computers, facsimiles,
terminals, and printers.

Code-Bit: The smallest Signaling element used by the Physical Layer for transmission on the medium.
Code Group: The specific sequence of five code bits representing an FOOl symbol.

5-4

Multlmode: An optical fiber which allows the signal carrying
light to travel along more than one path.
Network: A set of communication channels interconnecting
several or many locations.

Hub: An active fiber optic device which allows multiple connections. Signals are transmitted on all connections or
ports. Signals are not retimed.
IEEE: The Institute of Electrical and Electronic Engineers
(American). They are active in setting lAN standards. It has
established a number of technical committees, prefixed by
IEEE 802 (e.g., 802.3, 802.5, 802.6).
Interchannel Isolation: The ability to prevent undesired optical energy from appearing in one signal path as a result of
coupling from another signal path: cross talk.
Jitter, Data Dependent (DDJ): Jitter that is related to the
transmitted symbol sequence. DDJ is caused by the limited
bandwidth characteristics and imperfections in the optical
channel components. DDJ results from non-ideal individual
pulse responses and from variation in the average value of
the encoded pulse sequence which may cause base-line
wander and may change the sampling threshold level in the
receiver.
Jitter, Duty Cycle Distortion (DCD): Distortion usually
caused by propagation delay differences between low-tohigh and high-to-low transitions. DCD is manifested as a
pulse width distortion of the nominal baud time.
Jitter, Random (RJ): RJ is due to thermal noise and may
be modeled as a Gaussian process. The peak-peak value of
RJ is of a probabilistic nature and thus any specific value
requires an associated probability.
LAN: A local Area Network is a communications network
that provides interconnection of a variety of data communicating devices within a small area (e.g., a single site or
group of buildings).
lED: A Light Emitting Diode is an electrical component
which produces light when stimulated by electricity. It is
commonly used as a method for transmitting infra-red light
along an optical fiber.

Node: A generic term applying to any FDDI network attachment (station, concentrator, or repeater).
Nonrestricted Token: A Token denoting the normal mode
of asynchronous bandwidth allocation, wherein the available bandwidth is time-sliced among all requesters.
Nonreturn to Zero (NRZ): A technique in which a polarity
level high, or low, represents a logical "1" (one), or "0"
(zero).
Nonreturn to Zero Invert on Ones (NRZI): A technique in
which a polarity transition represents a logical "1" (one).
The absence of a polarity transition denotes a logical "0"
(zero).
Numerical Aperture (NA): The sine of the radiation or acceptance half-angle of an optical fiber, multiplied by the refractive index of the material in contact with the exit or entrance face.
Octet: A data unit composed of eight ordered bits (a pair of
data symbols).
Optical Fall Time: The time interval for the falling edge of
an optical pulse to transition from 90% to 10% of the pulse
amplitude.
Optical Reference Plane: The plane that defines the optical boundary between the MIC Plug and the MIC Receptacle.
Optical Rise Time: The time interval for the riSing edge of
an optical pulse to transition from 10% to 90% of the pulse
amplitude.
OSI: The Open Systems Interconnect is an objective designed to obtain the most effective internetworking. Namely,
it allows different devices to communicate without regard to
the manufacturer. It is obtained by adhering to appropriate
international standards throughout the system.
Physical (PHy): The Physical layer responsible for delivering a symbol stream produced by an upstream MAC Transmitter to the logically adjacent downstream MAC Receiver
in an FDDI ring.
'

llC: logical Link Control (IEEE 802.2) is the part of the ISO
7 layer model which is responsible for contrOlling the flow of
information over the link between stations.
logical Ring: A network which is treated logically as a ring
even though it may be cabled as a physical star topology.
Media Access Control (MAC): The Data Link layer (Dll)
responsible for scheduling and routing data transmissions
on a shared medium local Area Network (LAN) (e.g., an
FDDI ring).

Physical Connection: The full-duplex physical layer association between adjacent PHY entities (in concentrators, repeaters, or stations) in an FDDI ring, i.e., a pair of Physical
Links.

Media Interface Connector (MIC): An optical fiber connector which connects the fiber media to the FDDI attachment.
The MIC consists of two halves. The MIC plug is the male
half used to terminate an optical fiber signal transmission
cable. The MIC receptacle is the female half which is associated with the FDDI attachment.

Physical link: The simplex path (via PMD and attached
medium) from the transmit function of one PHY entity to the
receive function on an adjacent PHY entity (in concentrators, repeaters, or stations) in an FDDI ring.
Physical Medium Independent (PMD): The portion of the
FDDI protocol which provides the digital baseband pOint to
point communication between stations in the FDDI network.
It specifies the point of interconnection requirements for
conforming station and cable plants (i.e., optical power budget, MIC receptacle mating, optiC cable specifications, and
services provided to the PHY and SMT layers).

MIC Plug: The male half of the MIC which terminates an
optical signal transmission cable.
MIC Receptacle: The fixed or stationary female half of the
MIC which is part of an FDDI station.
Modulator: The component of a fiber optic system which
converts the electrical message into the proper format.

5-5

Station: An addressble'logical and physical node on an
FOOl ring capable of transmitting, repeating and receiving
information.

Primitive: An element of the services provided by one entity
to another.
Protocol Data Unit (PDU): Information delivered as a unit
between peer entities that may contain control information,
address information, and data (e.g., a Service Data Unit
(SOU) from a higher layer) or any combination of the three.
The FOOl MAC PO Us are Tokens and Frames.

Station Management (SMT): The supervisory entity within
an FOOl station that monitors station activity and exercises
overall appropriate control of station activity.
Symbol: The smallest signaling element used by the Data
Link Layer (OLL). The symbol set consists of 16 data symbols and 8 control symbols. Each symbol corresponds to a
specific sequence of code bits (code group) to be transmitter by the Physical Layer.

Receive: The action of a station of accepting a frame, token, or control sequence from the medium.
Receiver: An optoelectronic circuit that converts an optical
signal to an electrical logic signal.

Synchronous: A class of data transmission service whereby each requester is preallocated a maximum bandwidth
and guaranteed a response time not to exceed a specific
delay.

Repeat: The action of a station in receiving a code-bit
stream (e.g., frame or token) from an upstream station and
placing it on the medium to the next station. The station
repeating the code-bit stream examines it and may copy it
into a buffer and modify control indicators as appropriate.

TCPIIP: A widely used de facto standard transport/network
protocol. It requires a Type Field when carried over Ethernet
V2 networks.

Repeater: An FOOl node that minimally comprises the functionality of two PMOs and provides only a repeat function. A
repeater does not have any MACs or concentrator functionality.

Token: An explicit indication of the right to transmit on a
shared medium. On a Token Ring, the Token circulates sequentially through the stations in the ring. At any time, it may
be held by zero or one station. FOOl uses two classes of
Tokens: restricted and non-restricted.

Restricted Token: A Token denoting a special mode of
asynchronous bandwidth allocation, wherein the bandwidth
available for the asynchronous class of service is dedicated
to a single extended dialogue between specific requesters.

Topology: The layout or configuration of a network. The
principal network topologies !ire star, bus, and ring.

Ring: Two or more stations connected by a physical medium wherein information is passed sequentially between active stations, each station in turn examining or copying the
information, finally returning it to the originating station.

Transmit: The action of a station that consists of generating
a frame, token, or control sequence, and placing it on the
medium to the next station.

Ring Management: The part of SMT which ensures the
integrity of unique addresses on the FDOI ring.

Transmitter: An optoelectronic circuit that converts an
electrical logic signal to an optical Signal.

Service Data Unit (SOU): The unit of data transfer between
a service user and a service provider.
Services: A set of functions, or services, provided by one
OSI.layer or sublayer entity, for use by a higher layer or
sublayer entity or by management entities.

TTRT: The Target Token Rotation Time is the target time
for the token to pass every FOOl node in the token path.
WAN: A Wide Area Network is a network that uses links
provide by the postal, telegraph, and telephone (PT&T) administrations and usually connects disperse locations (e.g.,
greater than 50 miles).

Singlemode: An optical fiber which allows the Signal carrying light to travel along only one path. It is also called monomode.

Wavelength: A measurement of the length of any electromagnetic wave. The shorter the wavelength, the higher the
frequency.

SlngleAHachment 'Concentrator (SAC): A concentrator
that offers one attachment to the FOOl network.

Workstation: An end user device typically comprised of
high resolution screens, local graphics proceSSing, keyboard, pointing device, and network connection.

Single Station (or Single Attachment Station): A station
that offers one attachment to the FOOl network.

X3T9.5: The ANSI committee responsible for specifying the
FOOl standard.

Spectral Width, Full Width Half Maximum (FWHM): The
absolute differenc!l between the wavelengths at which the
spectral radiant intensity is 50.0 percent of the maximum
power.

Sources
1. ANSI X3T9.5 Protocol Documents for PMO, PHY, MAC
and SMT Layers.

ST: One type of connector used for terminating optical fibers.

2. BICC Booklet "FOOl, Business Communications for the

Star: A network configuratio!1 where all th~ nodes are connected to one common central pOint via individual cables.

1990's".
3. Handbook of Computer Communications Standards, V2
(W. Stallings).

5-6

~National

~ Semiconductor

All dimensions are in inches (millimeters)

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NOTES

~National

D

Semiconductor

Bookshelf of Technical Support Information
National Semiconductor Corporation recognizes the need to keep you informed about the availability of current technical
literature.
This bookshelf is a compilation of books that are currently available. The listing that follows shows the publication year and
section contents for each book.
Please contact your local National sales office for possible complimentary copies. A listing of sales offices follows this
bookshelf.
We are interested in your comments on our technical literature and your suggestions for improvement.
Please send them to:
Technical Communications Dept. M/S 16-300
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara. CA 95052-8090

ALS/AS LOGIC DATABOOK-1990
Introduction to Advanced Bipolar Logic. Advanced Low Power Schottky. Advanced Schottky

ASIC DESIGN MANUAL/GATE ARRAYS & STANDARD CELLS-1987
SSI/MSI Functions. Peripheral Functions. LSIIVLSI Functions· Design Guidelines· Packaging

CMOS LOGIC DATABOOK-1988
CMOS AC Switching Test Circuits and Timing Waveforms. CMOS Application Notes. MM54HC/MM74HC
MM54HCT/MM74HCT. CD4XXX. MM54CXXX/MM74CXXX. Surface Mount

DATA ACQUISITION LINEAR DEVICES-1989
Active Filters. Analog Switches/Multiplexers. Analog-to-Digital Converters • Digital-to-Analog Converters
Sample and Hold • Temperature Sensors. Voltage Regulators. Surface Mount

DATA COMMUNICATION/LAN/UART DATABOOK-1990
LAN IEEE 802.3 • High Speed Serial/IBM Data Communications • ISDN Components. UARTs
Modems • Transmission Line Drivers/Receivers

DISCRETE SEMICONDUCTOR PRODUCTS DATABOOK-1989
Selection Guide and Cross Reference Guides. Diodes. Bipolar NPN Transistors
Bipolar PNP Transistors • JFET Transistors • Surface Mount Products. Pro-Electron Series
Consumer Series. Power Components. Transistor Datasheets • Process Characteristics

DRAM MANAGEMENT HANDBOOK-1989
Dynamic Memory Control • Error Detection and Correction. Microprocessor Applications for the
DP8408A109A117/18/19/28/29. Microprocessor Applications for the DP8420Al21A122A
Microprocessor Applications for the NS32CG821

EMBEDDED SYSTEM PROCESSOR DATABOOK-1989
Embedded System Processor Overview. Central Processing Units • Slave Processors • Peripherals
Development Systems and Software Tools

FDDI DATABOOK-1991
FDDI Overview. DP83200 FDDI Chip Set. Development Support. Application Notes and System Briefs

F100K ECL LOGIC DATABOOK & DESIGN GUIDE-1990
Family Overview. 300 Series (low-Power) Datasheets • 100 Series Datasheets • 11 C Datasheets
ECl BiCMOS SRAM, ECl PAL, and ECl ASIC Datasheets. Design Guide • Circuit Basics. logic Design
Transmission Line Concepts. System Considerations. Power Distribution and Thermal Considerations
Testing Techniques. Quality Assurance and Reliability. Application Notes

FACTTM ADVANCED CMOS LOGIC DATABOOK-1990
Description and Family Characteristics • Ratings, Specifications and Waveforms
Design Considerations • 54AC174ACXXX • 54ACT/7 4ACTXXX • Quiet Series: 54AC0174ACQXXX
Quiet Series: 54ACTQ174ACTQXXX • 54FCT 174FCTXXX • FCTA: 54FCTXXXA174FCTXXXA

FAST® ADVANCED SCHOTTKY TTL LOGIC DATABOOK-1990
Circuit Characteristics. Ratings, Specifications and Waveforms. Design Considerations. 54F174FXXX

FAST® APPLICATIONS HANDBOOK-1990
Reprint of 1987 Fairchild FAST Applications Handbook
Contains application information on the FAST family: Introduction. Multiplexers. Decoders. Encoders
Operators. FIFOs • Counters. TTL Small Scale Integration • Line Driving and System Design
FAST Characteristics and Testing • Packaging Characteristics

GENERAL PURPOSE LINEAR DEVICES DATABOOK-1989
Continuous Voltage Regulators. Switching Voltage Regulators. Operational Amplifiers. Buffers. Voltage Comparators
Instrumentation Amplifiers. Surface Mount

GRAPHICS HANDBOOK-1989
Advanced Graphics Chipset. DP8500 Development Tools. Application Notes

INTERFACE DATABOOK-1990
Transmission Line Drivers/Receivers. Bus Transceivers • Peripheral Power Drivers. Display Drivers
Memory Support • Microprocessor Support • level Translators and Buffers • Frequency Synthesis. Hi-Rei Interface

LINEAR APPLICATIONS HANDBOOK-1986
The purpose of this handbook is to provide a fully indexed and cross-referenced collection of linear integrated circuit
applications using both monolithic and hybrid circuits from National Semiconductor.
Individual application notes are normally written to explain the operation and use of one particular device or to detail various
methods of accomplishing a given function. The organization of this handbook takes advantage of this innate coherence by
keeping each application note intact, arranging them in numerical order, and providing a detailed Subject Index.

LS/S/TTL DATABOOK-1989
Contains former Fairchild Products
Introduction to Bipolar logic • low Power Schottky. Schottky. TTL. TTl'-low Power

MASS STORAGE HANDBOOK-1989
. Rigid Disk Pulse Detectors. Rigid Disk Data Separators/Synchronizers and ENDECs
Rigid Disk Data Controller. SCSI Bus Interface Circuits • Floppy Disk Controllers. Disk Drive Interface Circuits
Rigid Disk Preamplifiers and Servo Control Circuits. Rigid Disk Microcontroller Circuits. Disk Interface Design Guide

MEMORY DATABOOK-1990
PROMs, EPROMs, EEPROMs. TTL I/O SRAMs. ECl I/O SRAMs

MICROCONTROLLER DATABOOK-1989
COP400 Family. COP800 Family. COPS Applications. HPC Family. HPC Applications
MICROWIRE and MICROWIRE/PlUS Peripherals. Microcontroller Development Tools

MiCROPROCESSOR DATABOOK-1989
Series 32000 Overview. Central Processing Units. Slave Processors. Peripherals
Development Systems and Software Tools. Application Notes. NSC800 Family

PROGRAMMABLE LOGIC DATABOOK & DESIGN MANUAL-1990
Product Line Overview. Datasheets • Designing with PLDs • PLD Design Methodology. PLD Design Development Tools
Fabrication of Programmable Logic. Application Examples

REAL TIME CLOCK HANDBOOK-1989
Real Time Clocks and Timer Clock Peripherals • Application Notes

RELIABILITY HANDBOOK-1986
Reliability and the Die • Internal Construction. Finished Package. MIL-STD-883. MIL-M-38510
The Specification Development Process. Reliability and the Hybrid Device. VLSIIVHSIC Devices
Radiation Environment • Electrostatic Discharge • Discrete Device • Standardization
Quality Assurance and Reliability Engineering • Reliability and Documentation. Commercial Grade Device
European Reliability Programs. Reliability and the Cost of Semiconductor Ownership
Reliability Testing at National Semiconductor. The Total MilitarylAerospace Standardization Program
883B/RETSTM Products. MILS/RETSTM Products. 883/RETSTM Hybrids. MIL-M-38510 Class B Products
Radiation Hardened Technology. Wafer Fabrication. Semiconductor Assembly and Packaging
Semiconductor Packages. Glossary of Terms. Key Government Agencies. ANI Numbers and Acronyms
Bibliography. MIL-M-3851 0 and DESC Drawing Cross Listing

SPECIAL PURPOSE LINEAR DEVICES DATABOOK-1989
Audio Circuits. Radio Circuits. Video Circuits • Motion Control Circuits. Special Function Circuits
Surface Mount

TELECOMMUNICATIONS-1990
Line Card Components. Integrated Services Digital Network Components. Analog Telephone Components
Application Notes

~ National

~ Semiconductor



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